1988_Datel_Data_Conversion_Catalog 1988 Datel Data Conversion Catalog

User Manual: 1988_Datel_Data_Conversion_Catalog

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COMPANY HISTORY
DATEL is a multinational company which was founded in 1970, and is located approximately 35
miles from Boston in Mansfield, Massachusetts. Our modern 180,000 square-foot facility houses
our administrative offices, components and sUb-systems engineering groups, modular and subsystems production facilities, and the most modern thin-film and thick-film hybrid production facility
in the industry. DATEL's hybrid manufacturing operation is a fully certified MIL-STD-1772 facility,
supporting our high quality standards.
Our worldwide sales network extends to every major data acquisition product marketplace. And,
the people who implement this sales network are skilled professionals dedicated to providing our
customers with the highest possible standards of data acquisition products available today.

PRODUCT INFORMATION
DATEL offers one of the industry's broadest product lines, meeting the rapidly growing need for
data acquisition components and sUb-systems to interface with computers in industrial, commercial, scientific and military applications. These products employ five basic technologies: monolithic
CMOS, monolithic bipolar, thin-film hybrid, thick-film hybrid and discrete component circuits. Many
products employ a combination of these technologies to achieve higher levels of performance and
complexity. The present product lines include: data converters, sample-hold amplifiers, analog
multiplexers, amplifiers, data acquisition sub-systems, computer analog I/O boards, process monitor/controllers, digital panel meters, thermal printers, digital calibrators and power supplies.

ABOUT THIS CATALOG
This comprehensive catalog includes detailed data sheets on DATEL's complete product line.
Products are categorized by function and organized into QUICK SELECTION CHARTS at the
beginning of each section for your convenience.
Further details and applications information may be obtained by returning the enclosed reply card.
For immediate attention, contact the nearest DATEL sales office.
DATEL application engineers are always available to answer any questions that may arise concerning the application of our products.

DATEL. Inc. 11 Cabot Boulevard, Mansfield, MA02048·1194
TEL. (508) 339·3000rrLX 174388IFAX (508) 339·6356

PRODUCT INDEX

Analog-toDigital
Converters

Page

Digital-toAnalog
Converters

Page

ADC-207
ADC-208
ADC-300

1-5
1-11
1-19
1-23
1-27
1-33
1-39
1-43
1-49
1-55
1-61
1-65
1-71
1-77
1-82
1-92
1-100
1-106
1-110
1-115
1-121
1-127
1-131
1-135
1-139
1-143
1-147
1-152
1-157
1-163
1-169
1-175
1-183
1-186
1-189
1-192
1-195
1-199
1-205
1-209
1-213
1-217
1-223
1-229
1-235
1-241
1-247
1-253

DAC-08
DAC-0805
DAC-330
DAC-562
DAC-608
DAC-7134
DAC-7523

2-3
2-7
2-11
2-15
2-19
2-25
2-31
2-35
2-39
2-43
2-47
2-51
2-55
2-59
2-64
2-68

ADC-301/302

ADC-303
ADC-304
ADC-310
ADC-500/505

ADC-508
ADC-510/515

ADC-5101
ADC-511
ADC-520/521

ADC-5210
ADC-7109
ADC-800
ADC-810/811
ADC-815/825
ADC-816/826
ADC-817/827

ADC-830
II.DC-847 NB
!\DC-856
!\DC-868
!\DC-881
!\DC-974
XDC-8301
\DC-8302
I.DC-8303
mC-8304
\DC-8310
IDC-8500/8505

.DC-EH108
,DC-EH12B1,2
DC-EH1283
DC-EH88
DC-EK
DC-ET
DC-HC12
DC-HS12
DC-HXlHZ
DS-1 05/1 06
DS-111
DS-115/116
DS-125/126

DS-21
DS-22
)C-574/674

DAC-8308/8318

DAC-HF
DAC-HK
DAC-HP
DAC-HZ12B
DAC-IC10
DAC-IC8
DAC-UP10
DAC-UP8

Sample/Hold
Amplifiers
SHM-20
SHM-360/361
SHM-40
SHM-45
SHM-4860
SHM-5
SHM-6
SHM-7
SHM-9
SHM-91
SHM-HU
SHM-IC-1
SHM-LM2
SHM-UH

3-3
3-7
3-11
3-15
3-19
3-22
3-24
3-28
3-32
3-37
3-41
3-43
3-47
3-49

Amplifiers
AM-1435
AM-227
AM-427
AM-430
AM-453-2
AM-460/450

AM-464
AM-500
AM-542/543
AM-551
I AM-7650
I SCM-1 00/1 01
I SCM-102/103

4-3
4-7
4-11
4-15
4-17
4-19
4-23
4-25
4-27
4-31
4-35
4-41
4-45

Analog
Multiplexers

Page

Instrument
Products con't

Page

MV Series
MX Series

5-3
5-7
5-11

DM-31 00Ll31 03
DM-3100MIL
DM-3100N/3101
DM-3100U1
DM-3100U2/U3
DM-3100X
DM-3102A/B
DM-4100D
DM-4101 D
DM-4101 L
DM-4101N
DM-41 02/3/6
DM-4104
DM-4105
DM-4200
DM-500
DM-9000
DM-LX3
PC-6
PM-5050
PM-5060
PM-5070
PM-5080
DVC-350A
DVC-8500

10-53
10-55
10-57
10-59
10-61
10-63
10-65
10-68
10-71
10-74
10-76
10-78
10-80
10-82
10-84
10-86
10-89
10-95
10-106
10-111
10-117
10-123
10-129
10-135
10-142

MX-818/1616

Active Filters
FLJ-AC01
FLJ-ACR1
FLJ-D1,D2,DC
FLJ-D5,D6
FLJ-R
FLJ-UR
FLJ-VL,VH,VB
FLT-U2
ROJ-20,1 K

6-3
6-7
6-11
6-23
6-25
6-27
6-37
6-41
6-47

Data
Acquisition
Subsystems
DAS-952
HDAS-16/8
MDAS-16/8D
MDAS-940
SDAS-8

7-3
7-9
7-17
7-23
7-29

Voltage-toFrequency
Converters
VFQ-1,2,3

Data
Acquisition
Boards

8-1

Power
Products
Power Supplies
VI-7660
VR-182

9-2
9-27
9-33

Instrument
Products
APP-20A1
APP-20A21
APP-20A3
APP-48A1
APP-48A2
APP-48A3
APP-M20
APP-M48
APP-TR1,2,5
DPP-Q7
MPP-20A
D8M-20
DM-31
DM-31 008/31 04

10-5
10-8
10-12
10-15
10-18
10-22
10-26
10-28
10-30
10-32
10-36
10-47
10-49
10-51

I

DVME-601
DVME-602R
DVME-602T
DVME-611/612
DVME-624
DVME-626
DVME-628
DVME-641
DVME-643
DVME-645
DVME-660
DVME-691
DVME-Util
ST-519
ST-701
ST-702
ST-702R
ST-703
ST-705
ST-711/732
ST-716
ST-724
ST-728

I

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1

(508) 339-30001TLX 174388/FAX (508) 339-6356

11-3
11-9
11-15
11-21
11-29
11-33
11-37
11-41
11-43
11-45
11-47
11-51
11-57
11-59
11-65
11-73
11-77
11-81
11-89
11-101
11-109
11-115
11-122

NEW PRODUCTS FROM DATEL
DVME-601
16S or 8D-Channel 68010-based
VME A/D Coprocessor Board
Local 8 MHz 6801 0 CPU Plus:
- 64 Kb Private RAM
- 64/128 Kb EPROM
- 64 Kb Dual-ported RAM
A/D choices 12 to 16 bits, down to 2 IlSec.
16 Single-ended or 8 differential analog input channels
Simultaneous AID scanning. Ideal for DSP, FFT, ATE, and
graphics.
Monitor/Executive firmware to run in "no program mode" or
from user programs
Peripheral 68901 I/O:
- RS-232 serial port
- 3 timer/counters, 5 I/O bits
Sample-to-memory transfers at up to 250 KHz
Easy interrupt intergration with VERSAdos, PDOS, OS-9, etc.

DC-DC Converters
More than 60 new DC-DC converters have been added to the Product Line which include these features:
Efficiency up to 80%
2-1 input voltage ranges
• Miniature size
Single, dual, and triple outputs

ADS-115/116
10-Bit, 1 MHz
Sampling A/D Converters
• 10-Bit resolution
1 MHz throughput
15 M ohm input impedance
Includes fast Sample/Hold amplifier
3-state output TIL and CMOS compatible

ADC-520,521
12-Bit, Ultra-fast
Low-power A/D converter
12-Bit resolution
• 800 nanosecond maximum conversion time
Pin-programmable input ranges
• Internal high impedance buffer
Low 1.6 walls power consumption
Three-state output buffers
Small 32-pin DIP

SHM-30C
Very high speed, precision Sample/Hold amplifier
500 nSec. acquisition time to 0.01%
0.01IlV/IlSec droop rate
• 90V/IlSec slew rate
Internal hold capacitor

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

NEW PRODUCTS FROM DATEL
ADC-511
12-Bit, High-Speed,
Low Power AID Converter
1.0 Microsecond maximum conversion time
Low-power, 925 milliwatts
Three-state output buffers
Functionally complete
Small 24-pin DIP

ADS-111
12-Bit, 500 KHz, Low Power
Sampling AID Converter
Internal SamplelHold
Functionally complete
Small 24-pin DIP
Low-power, 1.4 Watts
Three-state output buffers

ADS-125,

ADS-126

12-Bit, 700 KHz, Low Power
Sampling AID Converters
15 M ohm input impedance
Pin-programmable input ranges
Low-power, 2.1 Watts
Three-state output buffers

ADC-208
a-Bit, 20 MSPS
1.2 Micron CMOS Flash AID Converter
10 MHz full power bandwidth
Sample-hold not required
Low power CMOS
+5V dc operation
8-Bit latched three-state outputs with overflow bit
MIL-STD-883B versions

ADC-574Z,

ADC-674Z

Complete 12-Bit AID Converters
with Sample-Hold, Reference, and Clock
Pin-to-pin compatible with industry standard HI574A/674A
No missing codes over temperature
15 IISec. conversion time (ADC-674Z)
150 mW max. power dissipation

ADS-1 05/1 06
12-Bit, 1 MHz
Sampling AID Converters
12-Bit resolution
1 MHz throughput
15 M ohm input impedance
Includes fast SamplelHold amplifier
3-state output, TTL and CMOS compatible

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

iii

NEW PRODUCTS FROM DATEL
PM-SOSO
Thermocouple Input
Process Monitor/Controller
Supports direct connection of thermocouple types J, K, T,
S, B, E, N, and R
DC or OF display; 0,1 or 1,0 degree resolution
Cold junction compensation disable option
Automatic display of open TC input condition

PM-SOGO
RTD and Thermistor Input
Process Monitor/Controller
Supports direct connection of 1OOQ platinum RTD's (American or European standards) and thermistors (2252£1,
3000Q, 5000Q, 10000Q)
Two-, Three-, or four-wire operation
°C or of display; 0,1 or 1.0 degree resolution
Automatic display of open circuit condition

PM-S070
Strain Gage
Process Monitor/Controller
Two inputs: ±50 mV (bridge output) ±1 OV reference
Simple bridge calibration and scaling function
Two user-defines math functions for sophisticated output
manipulation and control algorithms
Cycling six digit display of up to eight system variables, including input peaks and valleys

PM-SOSO
Dual-Channel Voltage/Current Signal Input
Process Monitor/Controller
Two input channels: 0-100 mV (jumper selectable for 0-20
mAl and 10V
Two user-defined math functions for sophisticated output
manipulation and control algorithms
Cycling six digit display of up to eight system variables, including input peaks and valleys
Simple scaling procedure with standard or user-defined engineering units

Tunable Active Filters
More than 30 new Active Filters have been added to
the Product Line
Digital, Voltage, and Resistive Tuning
State Ready Filters
Selectable for Bessel, Butterworth, Chebychev, or Elliptical
Response
Small Hybrid Packaging
Rolloffs up to 140 dB/Octave
High Pass, Low Pass, Band Pass, Band Reject Filters
Switched Capacitor 7th Order Low Pass Filtering

iv

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

HIGH-RELIABILITY PROGRAMS
DATEL is committed to meeting the demanding requirements of military, aerospace and severe environment applications. Toward that end, DATEL offers a few options in its quality programs.

OPTION 1 MIL-STD-883 CLASS B COMPLIANT DEVICES
DATEL has received MIL-STD-1772 certification for its hybrid facility. This approval certifies that DATEL meets the stringent
standards requirements surrounding the facilities, material, processes, personnel training, design analysis, documentation and
equipment used to manufacture hybrid microcircuits. MIL-STD-883 establishes uniform methods, controls and procedures for
designing, testing and certifying microelectronic devices.
New contracts negotiated after December 31,1984 require that, if MIL-STD-883 compliancy is called for, parts supplied must
meet the current intent of MIL-STD-883 (i.e., Element Evaluation and MIL-STD-1772 Certification, etc). DATEL's -883 program
offers products in full compliance with MIL-STD-883, Class B.
The accompanying chart gives a concise overview of MIL-STD-883 screening requirements and their implications for DATEL
customers.

METHOD

TEST
i

Internal Visual

I

(Precap)
Stabilization

Method 2017
--------- ----------------------Method 1008

-~~'"'"~:~:~~;;: ~~:,:',:0::"-I

I

PURPOSE
Eliminates devices with potential for failure under mechanical,
electrical or thermal stress
Eliminates device failure due to storage at elevated temperatures.
Determines resistance of device to sudden exposure to extreme
temperature changes. Removes potential failures due to thermal stress on bonds, etc.

Constant
Acceleration

Method 2001,
Test Condition A, Y AXIS, 5 kg.

Eliminates potential failures due to structural or mechanical weakness not detected in shock or vibration tests.

Burn-in Test

Method 1015,
Test Condition B, 160 hrs. at +125 °C

Stresses devices at temperature in order to eliminate infant mortailty failures.

Static Tests performed at +25 °C

Percent defective allowable-Rejects lots with static test failures
greater than 10%.

Final Electrical
Tests

Performed at +25 °C and at max. and min.
operating temperatures

Verifies that device still meets specified data sheet parameters.

Seal Fine
and Gross

Method 1014,
Test Condition A (fine), 1 x 10 7 cc/Sec. for
volume of ",0.5 to <1 .0 cm' and 5 x 10-8 ccl
Sec. for volume of", 1.0 to <10.0 cm'. Test
condition C (gross)

Insures hermeticity of device package. Eliminates degradation
due to absorption of water vapor or other contaminants.

External Visual

Method 2009

Insures that materials, design, construction, marking, and workma"1ship conform with applicable procurement documentation.

PDAW~---I

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

MIL-STD-883 compliancy also requires that complete documentation be available to support the product. An analysis of the design along with element and package evaluations are performed to ensure a high quality product. The manufacturing process is
also stringently controlled in order to obtain the high quality level.
Initial qualification requires passing the MIL-STD-883 tests for groups A, B, C and D. After initial qualification, groups A & Bare
tested for all lots. Group C is tested iniitially and to qualify any product changes which may occur. Group D testing is also performed initially and at intervals not exceeding 6 months for future lots.

MODEL NO.
ADC-HZ12B/883B
ADC-HX12B/883B
ADC-816/883B
ADC-208/883B
ADC-207/883B

MIL-STD-883

PRODUCTS

ANALOG-TO-DIGITAL

CONVERTERS

RESOLUTION

CONVERSION TIME

LINEARITY

12 Bits
12 Bits
10 Bits
8 Bits
7 Bits

81lSec
20llSec
800 nSec
50 nSec
50 nSec

± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1.5 LSB
± 1 LSB

DIGITAL-TO-ANALOG
MODEL NO.
DAC-HP16B/883B
DAC-HZ12B/883B
DAC-HK12B/883B

CONVERTERS

RESOLUTION

SETTLING TIME

LINEARITY

16 Bits
12 Bits
12 Bits

151lSec
31lSec
31lSec

± 1/2 LSB
± 1/2 LSB

±2 LSB

DATA ACQUISITION SUBSYSTEMS
MODEL NO.
HDAS-16/883B

RESOLUTION

INPUT CHANNELS

THROUGHPUT

12 Bits

16 SINGLE-ENDED

50KHz

Contact DATEL for information on future MIL-STD-883 compliant devices now being qualified.

OPTION 2 -QL PROGRAM
DATEL's -QL (Quality Level) program offers enhanced reliability over the standard DATEL products through subjecting the devices to environmental stresses. The -QL screening is not intended to imply compliance with MIL-STD-883 and any devices
screened to this program are classified as non-compliant devices as defined in paragraph 1.2 of MIL-STD-883.
It should be noted however, that if a contract was negotiated prior to December 31, 1984 and you supplied a part which your
Specification Control Drawing (SCD) described as compliant to MIL-STD-883, you may continue to fulfill that contract with parts
which satisfy the conditions of that specification. Contact DATEL to determine if a particular -QL product is applicable.

The accompanying chart gives a concise overview of the -QL screening requirements and their implications for DATEL
customers.

vi

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DATEL QL SCREENING PROGRAM
TEST

TEST CONDITION

PURPOSE

Internal Visual
(100% Precap)

Test Method 2017

Eliminate visual defects prior to seal

Stabilization Bake
100%

TM 1008, Condition C 24 hours at + 150 DC
(Optional ifTM 1030 is used)

Eliminates failures due to high temp storage

Temperature Cycling, 100%

TM 1010, Condition C -65 to + 150 DC, 10 cycles

Eliminates failures due to mechanical weakness

100% Constant Acceleration

TM 2001, Condition A VI Axis, 5000 G

Eliminates failures due to mechanical weakness

100% Burn-in

Static burn-in 160 hrs. at + 125 DC
(Similar to TM 1015 or TM 1030)

Eliminates failures due to infant mortality

1------ --------------+
100% Final Electrical
Performed at +25 DC, TMIN, and TMAX operating
Test
temperatures

Verifies that devices meet speicifications over
temperature range

100% Fine and Gross
Leak

Test Method 1014 Condition A (fine)
5 x 10.7 cc/Sec. Condition C (gross)

Insures hermeticity for high humidity
environments

100% External Visual

Test Method 2009

Insures proper marking, construction,
workmanship

-QL PRODUCTS

SAMPLE-HOLD
MODEL NO.
SHM-91 MM-QL
SHM-45MM-QL
SHM-4860MM-QL
SHM-9MM-QL
SHM-6MM-QL
SHM-HUMM-QL
SHM-40MM-QL

AMPLIFIERS

LINEARITY

ACQUISITION TIME

HOLD MODE DROOP

0.003%
0.01%
0.01%
0.01%
0.02%
0.1%
0.1%

2 ~Sec.
200 nSec.
200 nSec.
6 ~Sec.
2 ~Sec.
25 nSec.
40 nSec.

5.0 ~V/~Sec.
0.5 ~V/~Sec.
0.5 ~V/~Sec.
0.2 mV/mSec
10 ~V/~Sec.
50 ~V/~Sec.
100 ~ VI~Sec.

OPERATIONAL

MODEL NO.
AM-500MM-QL
AM-1435MM-QL

AMPLIFIERS

INPUT
OFFSET
VOLTAGE

GAIN
BANDWIDTH

OUTPUT

3 mV
5 mV

130 MHz
1000 MHz

+10V at 50 mA
+ 7Vat 14 mA

DATA ACQUISITION SUBSYSTEMS
MODEL NO.
HDAS-16MM-QL
HDAS-8MM-QL

RESOLUTION

INPUT CHANNELS

THROUGHPUT

12 Bits
12 Bits

16 Single-Ended
8 Diff-Ended

50 KHz
50 KHz

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

vii

ANALOG- TO-DIGITAL
MODEL NO.
ADC-505BMM-OL
ADC-50BBMM-OL
ADC-520MM-OL
ADC-521 MM-OL
ADC-B17AMM-OL
ADC-B10MM-OL
ADC-B27 AMM-OL
ADC-B11 MM-OL
ADC-HZ12BMM-OL
ADC-5211 H-OL
ADC-5212H-OL
ADC-5214H-OL
ADC-5215H-OL
ADC-5216H-OL
ADC-HX12BMM-OL
ADC-HC12BMM-OL
ADC-510BMM-OL
ADC-515BMM-OL
ADC-B16MM-OL
ADC-B26MM-OL
ADC-B15MM-OL
ADC-5101H-OL
ADC-B25MM-OL

CONVERTERS

RESOLUTION

CONVERSION TIME

LINEARITY

12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
10 Bits
10 Bits
10 Bits
10 Bits
B Bits
B Bits
B Bits

550 nSec.
700 nSec.
BOO nSec.
BOO nSec.
2 flSec.
2 flSec.
3 flSec.
3 flSec.
B flSec.
13 flSec.
13 flSec.
13 flSec.
13 flSec.
13 flSec.
20 flSec.
300 flSec.
510 nSec.
700 nSec.
BOO nSec.
1.4 flSec.
700 nSec.
900 nSec.
1 flSec.

± 1 LSB
± 1 LSB
± 1/2 LSB
± 1/2 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
±1/2LSB
± 112 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
±1/2LSB
±1/2LSB
± 112 LSB
± 1/2 LSB

SAMPLING ANALOG-TO-DIGITAL CONVERTERS
ADS-105MM-OL
ADS-106MM-OL
ADS-125MM-OL
ADC-HS 12BMM-OL
ADS-115MM-OL
ADS-116MM-OL

12
12
12
12
10
10

Bits
Bits
Bits
Bits
Bits
Bits

1 MHz
1 MHz
700 KHz
66 KHz
1 MHz
1 MHz

DIGITAL-TO-ANALOG
MODEL NO.
DAC-HP16BMM-OL
DAC-HF12BMM-OL
DAC-HK12BMM-OL
DAC-HZ12BMM-OL
DAC-HF10BMM-OL
DAC-HFBBMM-OL

viii

RESOLUTION
16
12
12
12
10
10

Bits
Bits
Bits
Bits
Bits
Bits

± 1 LSB
± 1 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB

CONVERTERS

SETTLING TIME

LINEARITY

15 flSec.
50 nSec.
3 flSec.
3 flSec.
25 nSec.
25 nSec.

±2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB
± 1/2 LSB

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

OPTION 3 8S9000 PROGRAM
DATEL also has a BS9000 program in compliance with British Standards for high reliability devices. BS9000 is the United
Kingdom's national system for the independent inspection approval and surveillance of manufacturers, distributors and test laboratories in the electronic component industry.

The accompanying product flow gives an overview of the BS9000 products through screening and quality conformance
inspection.

859000 Screening Requirements

I

I
I

Production batch formed

I
Screening Level B

Fine and gross leak tests
BS 9400 1.2.6.14

Electrical tests at 25 'C as per
subgroups A1 (a) (1). and A2

1

Pre-cap Inspection
BS 9400 1.2.10 Level B

I

High temperature storage
BS 9400 1.2.6.3 150 'C
for 24 hours

L

I

Inspection Lot Formed

I

Sample Test to groups
A,B,C as appropriate

I
Rapid change of temperature
BS 9400 1.2.6.13 10 cycles
-65 'C to + 150 'C

Burn-in Screen
BS 9400 1.2.9.2
160 hr. minimum at 125°C

J.

I
I
I
I

I

I
Acceleration steady state
BS 9400 1.2.6.9
294000 m/Sec.'direction Y1

859000

PRODUCTS

ANALOG- TO-DIGITAL
MODEL NO.
ADC-303-XXXXX
ADC-208-XXXXX

CONVERTERS

RESOLUTION

CONVERSION TIME

LINEARITY

8 BITS
8 BITS

10 nsec
50 nsec

+ 1/2 LSB
+ 1.5 LSB

Parts qualified to the BS9000 specification have a quality level equivalent to MILM-38510 giving a quality factor of 1.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

ix

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

GENERAL INDEX

ANALOG- TO-DIGITAL CONVERTERS
General Purpose AID Converters
High-Speed AID Converters
Flash AID Converters
Sampling AID Converters

SECTION.

DIGITAL-TO-ANALOG CONVERTERS

SECTION . .

SAMPLE-AND-HOLD

SECTION.

AMPLIFIERS

!

II

SECTION

ANALOG MULTIPLEXERS

SECTION

ACTIVE FILTERS

SECTION

DATA ACQUISITION SUBSYSTEMS

SECTION

VOLTAGE-TO-FREQUENCY CONVERTERS

SECTION

POWER PRODUCTS
Power Supplies
Voltage Inverters
Voltage References

SECTION

INSTRUMENT PRODUCTS
Thermal Printers
Digital Panel Meters
Process MonitorslControllers
Voltage Calibrators

SECTION.

DATA ACQUISITION BOARDS
VM Ebus 1/0 Boards
MULTIBUS I/O Boards

SECTION.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

•

I

AMPLIFIERS
Operational Amplifiers
Instrumentation Amplifiers
Signal Conditioning

xi

!.

ANALOG-TO-DIGITAL
CONVERTERS

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (50S) 339-30001TLX 17438S/FAX (50S) 339-6356

HIGH SPEED AID CONVERTERS
MODEL
ADC-815MC
ADC-B15MM
ADC-Sl01
ADC-Sl01H
ADC-82SMC
ADC-B2SMM
ADC-881
ADC-Sl0MC
ADC-510MM
ADC-515MC
ADC-515MM
ADC-816MC
ADC-816MM
ADC-826MC
ADC-B26MM
ADC-86B

RESOLUTION

CONVERSION
TIME (Max)

LINEARITY
(Max)

8 Bits

100 ns

±1/2 LSB

8 Bits

900 ns

±1/2 LSB

8 Bits

I fls

±1/2 LSB

8 Bits

I flS

±0.04 LSB

10 Bits

425 ns

±1/2 LSB

10 Bits

650 ns

±1/2 LSB

10 Bits

800 ns

±1/2 LSB

10 Bits

1.4 fls

±1/2 LSB

12 Bits

500 ns

±1/2 LSB

ADC-B17AMC
ADC-B17AMM
ADC-B27AMC
ADC-B27AMM
ADC-BllMC
ADC-BllMM
ADC-BOO
ADC-974

1-2

±5V

o to +IOV, +20V
±IOV
Oto +IOV, +20V
±IOV
oto -10V, -20V
+2.5V, ±5V, +1 OV
o to -5V, -10V, -20V
±2.5V, ±5V, ±I OV

oto +5V
±2.5V

550 ns

±1/2 LSB

±IOV

oto +70

Hybrid

-55 to + 125

24-pin DIP

o to +70

Hybrid

-55 to +125

Bin,2C
Bin
Bin, CBin
Bin, CBin
Bin,2C
Bin,2C
Bin

24-pin DIP

oto +70

Hybrid

-55 to +125

800 ns

±1/2 LSB

1-139
1-55

Hybrid
32-pin DIP

-55 to +125

Hybrid
32-pin DIP

-55 to +125

Hybrid
32-pin DIP

-55 to + 125
oto +70

Hybrid

-55 to +125

MODULE

oto +10
o to +70

12 Bits

I fls

±3/4 LSB

12 Bits
12 Bits
12 Bits

2flS
2flS
3 fls

±I LSB
±I LSB
±I LSB

12 Bits

3 fls

±I LSB

15 Bits

400 ms

2 LSB

16 Bits

2.5 fls

oto +10
oto +10

-55 to +125

oto +70

CBin

Hybrid

-55 to +125

±1/2 LSB

@14Bits

±IOV

C Bin, C2C

oto +5V

Offset Bin

o to +10

32-pin DIP

-55 to + 125

o to +70

C Offset Bin
Bin, CBin

24-pin DIP

o to +70

±5V

Offset Bin

Hybrid

-55 to +125

C Bin

32-pin DIP

C2C

Hybrid

oto +70
-55 to +125

32-pin DIP

o to +10

Hybrid
32-pin DIP

-55 to +125
oto +10

+2.5V, +5V, +IOv
oto -5V, -IOV
±2.5V, ±5V, ±I OV

o to +IOV, +20V
±5V, ±IOV

Bin,2C
Bin,2C
C Bin, C2C

-Vs +1.5V to +Vs-I.5V

Bin

±5V

C2C

1-110
1-110
1-135

1-43

1-49

1-71

-55 to +125

+2.5

a to -5V, -IOV

1-55

o to +70

oto +IOV
o to +IOV, +20V

1-106

oto +70

-55 to +125

12 Bits

1-61

oto +70

32-pin DIP

Bin,2C

1-106

MODULE

Offset Bin

o to +IOV, +20V, -20V

PAGE

32-pin DIP

C Offset Bin

ADC-S21MM

ADC-Bl0MM

±2.5V, ±5V, ±I OV

TEMPERATURE
RANGE (OC)

24-pin DIP

Bin

ADC-S20MC

ADC-Bl0MC

o to +5V, +10V, +20V

o to +IOV

700 ns

ADC-511MM

Bin

0.0125% FSR

ADC-508BMM

ADC-SllMC

o to -5V, -IOV, -20V
o to +5V, +1 OV, +20V

550 ns

100 ns

ADC-520MM

Bin,2C

500 ns
12 Bits

ADC-508BMC

ADC-521MC

±2.5V, ±5V, ±I OV

PACKAGE

500 ns

ADC-500BMM
ADC-50SBMM

oto +5V, +1 OV, +20V

OUTPUT
CODING

±2.5V, ±5V, ±I OV

ADC-500BMC
ADC-50SBMC

INPUT
RANGE

1-65
1-100
1-115
1-115

Hybrid

-55 to + 125

32-pin DIP

oto +70

Hybrid

-55 to + 125

40-pin DIP

oto +10

1-92

oto +70

1-143

Monolithic
MODULE

I-laO

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

•

FLASH AID

CONVERTERS

MODEL

RESOLUTION

CONVERSION
TIME (MAX)

LINEARITY
(MAX)

INPUT
RANGE

OUTPUT
CODING

PACKAGE

TEMPERATURE
RANGE (0C)

PAGE

ADC-207MC
ADC-207MM

7 Bits

50 nS

±1/2 LSB

o to +5V

Bin

18-pin DIP
Monolithic

o to +70
-55 to +125

1-5

ADC-303

8 Bits

10 nS

±1/2 LSB

Oto -2V

Bin, C Bin
C2C,2C

42-pin DIP
Monolithic

-20 to +100

1-27

ADC-302

8 Bits

20 nS

±1/2 LSB

o to -2V

Bin, C Bin
C2C,2C

28-pin DIP
Monolithic

-20 to + 100

1-23

ADC-301

8 Bits

33 nS

±1/2 LSB

o to -2V

Bin, C Bin
C2C,2C

28-pin DIP
Monolithic

-20 to + 100

1-23

ADC-300

8 Bits

50 nS

±1/2 LSB

o to -2V

Bin, C Bin
C2C,2C

28-pin DIP
Monolithic

-20 to + 100

1-19

ADC-304

8 Bits

50 nS

±1/2 LSB

Oto -2V

Bin, C Bin
C2C,2C

28-pin DIP
Monolithic

-20 to +100

1-33

ADC-208MC
ADC-208MM

8 Bits

50 nS

±0.6 LSB

o to +5V

Bin

24-pin DIP
Monolithic

o to +70
-55 to +125

1-11

10 Bits

50 nS

±1.75 LSB

Oto -2V

C Bin

28-pin DIP
Monolithic

-20 to +75

1-39

ADC-310

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-3

SAMPLING
MODEL

AID

RESOLUTION

ADS-11SMC
ADS-11SMM
ADS-116MC
ADS-116MM

CONVERTERS
THROUGHPUT

LlNEARITV
(MAX)

INPUT
RANGE

OUTPUT
CODING

PACKAGE

TEMPERATURE
RANGE (OC)

PAGE

10 Bils

1 MHz

±112 LSB

010 +10V

Bin. CBin

32 - pin DIP
Hybrid

010 +70
-5510 +125

1-229

10 BilS

1 MHz

±112 LSB

-1010+ 10V

Off. Bin
COff.Bin

32 - pin DIP
Hybrid

010 +70
-5510 +125

1-229

Bin. C Bin
Off. Bin
C Off. Bin

46 - pin DIP
Module

010 +70

1-241

ADS-21

12 Bils

1.3 MHz

±0.0125% FSR
±112 LSB

Olo+IOV
010 -5V. -IOV. -20V
±5V. ±10V

ADS-22

12 Bils

1 MHz

±0.0125% FSR
±112 LSB

010 +IOV
010 -5V. -10V. -20V
±5V. ±10V

Bin. C Bin
Off. Bin
COff. Bin

46 - pin DIP
Module

010 +70

1-241

12 Bils

1 MHz

±0.0125% FSR
±112 LSB

010 +IOV

Bin. C Bin

32 - pin DIP
Hybrid

010 +70
-5510 +125

1-217

12 Bils

1 MHz

±0.0125% FSR
±112 LSB

±IOV

Off. Bin
COff.Bin

32 - pin DIP
Hybrid

010 +70
-5510 +125

1-217

Bin. C Bin. Off. Bin
C Off. Bin. 2C. C2C

32 - pin DIP
Hybrid

010 +70
-5510 +125

1-235

ADS-105MC
ADS-10SMM
ADS-106MC
ADS-106MM
ADS-12SMC
ADS-125MM
ADS-126MC
ADS-126MM
ADS-111MC
ADS-111MM
ADC-HS12BMC
ADC-HS12BMM

12 Bils

700 kHz

±112 LSB

010 +IOV
±IOV

12 Bils

700 kHz

±112 LSB

010 +5V
±2.5V

Bin •. C Bin. Off. Bin
C Off. Bin. 2C. C2C

32 - pin DIP
Hybrid

Bin. C Bin
Off. Bin. C Off. Bin

24 - pin DIP
Hybrid

010 +70
-5510 + 125
010 +70
-5510 +125

1-235

12 Bils

500 kHz

±314 LSB

Oto +10V
±5V

12 Bits

66 kHz

±112 LSB

010+5V. +10V
±2.5V. ±5V. ±IOV

C Bin. C2C

32 - pin DIP
Hybrid

010 +70
.5510 +125

1-209

12 Bils

55 kHz

±1 LSB
±IJ2 LSB

010 +IOV. +20V
±5V. ±10V

Bin
Off. Bin

28 - pin DIP
Monolilhic

010 +70
-5510 + 125

1-253

12 Bits

35 kHz

010 +10V. +20V
±5V. ±10V

Bin
Off. Bin

28 - pin DIP
Monolilhic

oto +70

1-253

6.3 X 4 in.
(160 X 102 mm)

oto +70

1-223

ADC-674ZA
ADC-674ZB
ADC-674ZC
ADC-S74ZA
ADC-S74ZB

±1 LSB
±112 LSB

±IJ2 LSB

ADC-S74ZC
718 Bils

20 MHz

±0.6 LSB

Oto +5V

Bin

8 Bits

100 MHz

±1!2 LSB

Oto +IV
+0.5V

Bin. C Bin. Off. Bin
C Off Bin. 2C. C2C

Eurocard size

ADC-B303E
ADC-B302E

8 Bits

50 MHz

±1!2 LSB

Oto +IV
±0.5V

Bin. C2C
Off. Bin. 2C

ADC-B301E

8 Bits

30 MHz

±IJ2 LSB

010 +IV
±0.5V

ADC-B304E

8 Bits

20 MHz

±IJ2 LSB

ADC-B10E

10 Bits

12MHz

±1.75 LSB

12 Bits

1.25 MHz

±O.0125% FSR
±1!2 LSB

ADC-B2071208

ADC-BSOO

.

ADC-BSOO-1

ADC-BSOS

12 Bils

1.1 MHz

±0.0125% FSR
±1!2 LSB

oto +70

1-157

Eurocard size
Pin connector

oto +70

1-152

Bin. C2C
Off. Bin. 2C

Eurocard size
Pin connector

010 +70

1-147

Oto IV
+0.5V

Bin. C Bin. Off. Bin
C Off. Bin. 2C. C2C

Eurocard size
Pin connector

010 +70

1-163

Oto IV
±0.5V

Bin
Off Bin

Eurocard size
Pin connector

oto +70

1-169

o to -5V. -IOV
oto -20V. +IOV

Bin. C Bin
Off. Bin. C Off. Bin

3.8 X 4.5 in
(97XI14mm)
Board

oto +70

1-175

Bin. C Bin
Off. Bin. C Off. Bin

3.8 X 4.5
(97 X 114mm)
Board

010 +70

1-175

±5V. ±IOV
010 -5V. -IOV

oto -20V. +10V
±5V. ±10V

Pin connector

• Includes ADC-500 and SHM-4S

1-4

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC·207
VIDEO FLASH CONVERTER

•

FEATURES
•
•
•
•
•
•

7 Bit Flash AID Converter
35 MHz Sampling Rate
Low Power (250 mw)
+5V dc Operation
1.2 micron CMOS
7-Bit Latched 3-state Output With
Over1low Bit

APPLICATIONS
•
•
•
•
•
•

TV video digitizing
Radar
High-speed digital oscilloscopes
Medical imaging (ultrasound)
Robotic vision
High-Speed, low power applications

GENERAL DESCRIPTION
The ADC-207 is the industry's first 7·bit flash
converter using a high-speed 1.2 micron
CMOS process. This process offers some
very distinctive advantages over other
processes, making the ADC-207 a very
unique device. The smaller geometrics of the
process achieves high-speed, better linearity and better temperature performance. Since
the ADC-207 is a CMOS device, it also has
very low power consumption (250 mw). The
device draws power from a single +5V supply, and is conservatively rated for 20 MHz
operation. The ADC-207 allows using sampling apertures as small as 12nS, making it
more closely approach an ideal sampler. The
small sampling apertures also let the device
operate at greater than 20 MHz.
The ADC-207 has 128 comparators which are
auto-balanced on every conversion so as to
cancel out any offsets due to temperature
andlor dynamic effects. The resistor ladder
has a midpoint tap for use with an external
voltage source to improve integral linearity
beyond 7 bits. The ADC-207 also provides the
user with 3-state outputs for easy interfacing
to other components. There are two models
of the ADC-207 covering two operating temperature ranges, 0 to 70 degrees C and -55
to +125 degrees C. For MIL-Std-883C
versions, consult factory.

Figure 1. ADC-207 Simplified Block Diagram

INPUT/OUTPUT CONNECTIONS

MECHANICAL DIMENSIONS

PIN

PIN l)~:;"""~;::;:O;:;:;~~=-~

~

IDENT

,.

--II I1-..- 0100
(2,51

_____

PIN

FUNCTION

1

CLOCK

10

OVERFLOW

2

DIGITAL GROUND

FUNCTION

11

BIT 1 (MSB)

3

- REFERENCE

12

BIT 2

4

ANALOG INPUT

13

5

MID POINT

14

BIT 4

6

+ REFERENCE

15

BIT5

BIT 3

7

ANALOG GROUND

16

BIT6

8

CHIP SELECT'

17

BIT 7 (lSB)

9

CHIP SELECT 2

18

+VDD SUPPLY

~()018

,(j

4(;.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-5

ADC·207
FUNCTIONAL SPECIFICATIONS
(Typical at +5Vdc power, +25 deg. C, 20 MHz clock,
+Reference = 5V, -Reference = Ground, unless noted)
DESCRIPTION

MIN.

TYPICAL

MAX.

UNITS

ABSOLUTE MAXIMUM RATINGS
Power supply voltage
(+Vdd, pin lB)
Digital inputs
Analog input

-0.5

-

+7.0

Vdc

-0.5
-0.5

-

Vdc
Vdc

Reference inputs
Digital outputs
(short circuit protected
to ground)
Lead temperature,
10 sec. ma
Ambient temperature

-0.5
-0.5

+5.5
+Vdd
+0.5
+Vdd
+5.5

-

-

Vdc
Vdc

-

-

+300

·C

-65

-

+150

·C

MIN.

TYPICAL! MAX.

1.

UNITS

POWER REQUIREMENTS
Power supply range (+Vdd)
Power supply current
Power dissipation

+3.0

-

+5.0
+50
250

'+5.5
+70
3B5

Vdc
mA
mW

+70
+125
+150

·C

ENVIRONMENTAL - MECHANICAL
Operating temp. range:
MCgrade
MMgrade
Storage temp, range
Package type

0
-55
-65

-

OC
OC

Pins

hermetically sealed, ceramic dual inline
package
lB pins, 0.100" centers, 0.300"between

Pin material

.010 x .01B inch Kovar

rows

NOTES: 1. At full power input and chip selects enabled
2. At 4 MHz input and 20 MHz clock

INPUTS
ANALOG SIGNAL INPUT
single·ended, non-isolated
Input range
dc-20 MHz
Input impedance
Input capacitance,
full input range
DIGITAL INPUTS:
Logic "1" level
Logic "0" level
Logic "1" loading
Logic "0" loading
Sample pulse width,
during sampling portion
of clock
Reference ladder
resistance

3. For 10-step, 40 IRE NTSC ramp test

-

0

-

1000
10

2.0

+/-1
+/-1

+5.0

-

-

V
Ohms
pF

12

-

-

V
V
microamps
microamps
nS

-

330

-

Ohms

-

O.B
+/-5
+/-5

DIGITAL OUTPUTS
Straight binary

Data coding
Data output resolution
Logic "1" level
Logic "0" level
att.6mA
Logic "1" loading
Logic "0" loading
Output data valid delay

7
2.4

-

-

4.5

-

-

0.4

4
4

-

-

-

-

15

17

-

V
V
mA
mA
nS

from rising edge

TECHNICAL NOTES

1. Input Buffer Amplifier-Since the ADC-207 has a switched
capaCitor type input, the input impedance of the 207 is
dependent on the clock frequency. At relatively slow conversion rates a general purpose type input buffer can be
used; at high coversion rates DATEL recommends either
the HA-5033, the LH-0033 or Elantec 2003.
2. Reference Ladder-Adjusting the voltage at + Ref adjusts
the gain of the ADC-207. Adjusting the voltage at -Ref
adjusts the offset or zero of the ADC-207. The midpoint pin
is usually bypassed to ground through a .1uf capaCitor,
although it can be tied to a pr-ecision voltage halfway
between + Ref and -Ref. This would improve integral linearity beyond 7 bits.
3. Clock Pulse Width-To improve performance at Nyguist
bandwidths, the clock duty cycle can be adjusted so that the
low portion of the clock pulse is 12 nseconds wide. The
smaller aperature allows the ADC-207 to closely resemble
an ideal sampler.
CAUTION

PERFORMANCE
Conversion rate'

20

35

-

Harmonic distortion 2
(B MHz 2nd order harmonic)
Differential gain'
Differential phase'
Aperture delay
Aperture jitter
No missing codes
MC grade
MM grade
Integral linearity at 25·C
Adjustable over temp. range
Differential nonlinearity
at 25·C
Over temp. range
Power supply rejection

-

-40

-

-

-

-

3
1.5
B
50

0
-55

-

1-6

DESCRIPTION

-

-

+/-0.8
+/-1.0

-

+/-0.3
+/-0.4
0.02

+70
+125
+/-1

+/-0.5
+/-0.6

-

mega
samples/sec
dB
%
degrees
nS
pS

OC
·C
LSB
LSB
LSB
LSB
%FSR/%Vs

Since the ADC-207 is a CMOS device, normal precautions against static electricity should be taken. use
ground straps, grounded mats, etc. The Absolute Maximum Ratings of the device MUST NOT BE EXCEEDED
as irrevocable damage to the ADC-207 will occur.
TIMING DIAGRAM
AUTO SAMPLE AUTO SA~~LE AUTO SAMPLE
N
ZERO
+
ZERO
N+2
ZERO
02

M N DATA

MN+1 DATA

1-1

1-1

17NS
MAX

17NS
MAX

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC·207
OUTPUT CODING

for code changes at the midpoints between these center values
shown in Table 1. For example, at the half-scale major carry, set
the input to 2.54V and adjust the reference until the code flickers equally between 63 and 64. Note also that the weighting for
the comparator resistor network leaves the first and last
thresholds to within '/2 LSB of the end pOints to adjust the code
transition to the proper midpoint values.

(+Ref= +5.12V, -Ref=Gnd, MID POINT=no connection)
NOTE: The reference should be held to 0.1% accuracy or better. Do not use the +5V power supply as a reference
input without precision regulation and high frequency
decoupling.
Values shown here are for a 5.12Vdc reference. Scale other
references proportionally. Calibration equipment should test

Table 1. ADC-207 Output Coding

Analog In
(Center Value)

, -

Code

Overflow

O.OOV
Zero
0
+1 LSB
+0.04V
0
+1.2BV
0
+1/4 FS
+2.52V
+1/2FS-l LSB
0
+2.56V
+1/2FS
0
+2.60V
+ 1/2FS + 1 LSB
0
+3.B4V
+314FS
0
+5.0BV
0
+FS
. Overflow
+5.12V
1
Note that the overflow code does not clear the data bits.

1 2 3 4 5 6 7
MSB D A T A LSB
0
0
0
0
1
1
1
1
1

0
0
1
1
0
0
1
1
1

0
0
0
1
0
0
0
1
1

0
0
0
1
0
0
0
1
1

0
0
0
1
0
0
0
1
1

0
0
0
1
0
0
0
1
1

0
1
0
1
0
1
0
1
1

Decimal Hexadecimal
(incl.OV)
0
1
32
63
64
65
96
127
255'

00
01
20
3F
40
41
60
7F
FF

THEORY OF OPERATION
The ADC-207 uses a switched capacitor scheme in which there
is an auto-zero phase and a sampling phase. (Figure 1 shows
the simplified block diagram of the ADC-207.) The ADC-207
uses a single clock input. When the clock is at a high state (logic
1), the ADC-207 is in the auto-zero phase (01). When the clock
is at a low state (logic 0), the ADC-207 is in the sampling phase
(02). During phase 1, the 12B comparator outputs are shorted
to their inputs through CMOS switches. This serves the purpose of bringing the inputs and outputs to the transition levels
of the respective comparators. The inputs to the comparators
are also connected to 128 sampling capacitors. The other end
of the 128 capacitors are also shorted to 128 taps of a resistor
ladder, via CMOS switches. Therefore during phase 1 the sampling capacitors are charged to the differential voltage between
a resistor tap and its respective comparator transition voltage.
This eliminates offset differences between comparators and
yields better temperature performance. During phase 2 (0'2) the
input voltage is applied to the 128 capacitors, via CMOS
switches. This forces the comparators to trip either high or low.
Since the comparators during phase 1 were Sitting at their transition pOint, they can trip very quickly to the correct state. Also
during phase 2 the outputs of the comparators are loaded into
internal latches which in turn feed a 128 to 7 encoder. When going back into phase 1 the output of the encoder is loaded into
an output latch. This latch then feeds the 3-state output buffer.

conversion requires one cycle/sample (one positive pulse and
one negative pulse). The 3-state buffer has two enable lines,
CS1 and CS2. Table 2 shows the truth table for chip select signals. CSl has the function of enabling/disabling bits 1 through
7. CS2 has the function of enabling/disabling Bits 1 through 7
and the overflow bit. Also a full-scale input produces all ones,
including the overflow bit at the output. The ADC-207 has an
adjustable resistor ladder string. The top end, middle pOint, and
bottom end are brought out for use with applications circuits.
These pins are called +Ref, MID POINT, and -Ref, respectively. In typical operation +Ref is tied to +5V, -Ref is tied to
ground, and MID POINT is bypassed to ground. Such a configuration results in a 0 to 5V dc input voltage range. The MID
POINT pin can also be tied to a 2.5V source to further improve
integral linearity. This is usually not necessary unless better
than 7 bit linearity is needed.
Table 2. Chip Select Truth Table
CS1

CS2

0
1
0
1

0
0
1
1

Bits 1-7
3 State Mode
3 State Mode
DATA Outputed
3 State Mode

Overflow Bit
3 State Mode
3 State Mode
DATA Outputed
DATA Outputed

This means that the ADC-207 is of pipeline design. To do a single conversion, the ADC-207 requires a positive pulse followed
by a negative pulse followed by a positive pulse. CtJntinuous

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-7

•

ADC·207
APPLICATION #1: Using the ADC·207
Figure 2 shows typical connections for using the ADC·207. In
this configuration the input voltage range is 0 to 5V dc. The input
voltage range is determined by the reference voltage. For oper·
ating in lower input voltage ranges, the reference input must
be tied to the corresponding lower voltage value. For example
to operate the ADC·207 in 0 to 3V input voltage range the + REF
input must be tied to +3V dc. Further, for higher speed operation (above 20 MHz) user may modify the clock signal to facilitate duty cycle adjustment. Figure 3 shows a pulse shaping
circuit which is usable to modify the clock signal.

APPLICATION #2: Using 1\vo ADC·207's for
B·bit resolution.
Two ADC-207's (A and B) are cascadable for applications
requiring a-bit resolution. The device A provides a typical7-bit
output. The OVERFLOW signal of device A turns off device A
and turns on the device B. The OVERFLOW signal of device
A is also used as MSB for a-bit operation. The device B provides
the other seven bits from the input signal. Figure 4 shows the
circuit connections for the application.

,..----"1----+---- BIT 1 lMSB)

elK

Pi

2 DIGITAL
GROUND
J

V'N

VDD
B7

B7

86 16
B5

(LSB)

B6

15
B5

84 14

6 REF+

83 13

7 ANALOG

62 12

8 GROUND

eso
eS2
'UF

B'

"

BJ
B2
B'

(MSB)

OF 10

~

DIGITAL
GROUND

Figure 2. Typical Connections for Using the ADC-207
Note: The output data bit numbering is offset by a bit to the
device B's output.
Figure 4. Using ADC·207's for B·bit Operations

CLOCK OUT
CLOCK IN

GROUND

+5VOLTS
NOTE: Reduce the sample time (sample pulse) to 12 nsec. to improve
performance above 20 MHz. Such a configuration will closely
resemble an ideal sampler.

Figure 3. Optional Pulse Shaping Circuit

1-8

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC·207
APPLICATION #3: Beat Frequency And Envelope Tests

1. Full power input bandwidth of all 128 comparators. (Any gain
loss would show as signal distortion.)
2. Phase response linearity vs. instantaneous signal magnitude. (Phase problems would show as improper codes.)
3. Comparator slew rate limiting.

Figure 5 shows the actual plot olthe Beat Frequency Test. This
test uses a 20 MHz clock input to the ADC-207 with a 20.002
MHz full-scale sine wave input. Although the converter would
not normally be used in this mode because the input frequency violates Nyquist criteria for full recovery of signal information,
the test is an excellent demonstration of the ADC-20Ts highfrequency performance.

Envelope Test:
Figure 6 shows the actual plot of the Envelope Test. This test
is a variation of the previous test but uses a 10.002 MHz sine
input to give two overlapping cycles when the data is reconstructed by a D/A converter output to an oscilloscope. The
scope is triggered by the 20 MHz clock used by the AID. Any
assymmetry between positive and negative portions of the signal will be very obvious. This test is an excellent indication of
slew rate capability. At the peaks of the Envelope, consecutive
samples swing completely through the input voltage range.

The effect of the 2 KHz frequency difference between the input
and the clock is that the output will be a 2 KHz sinusoidal digital data array which "walks" along the acutal input at the 2 KHz
beat note frequency. Any inability to follow the 20.002 MHz input
will be immediately obvious by plotting the digital data array.
Further arithmetic analysis may be done on the data array to
determine spectral purity, harmonic distortion, etc. This test is
an excellent indication of:

120
110
100
90
80
OUTPUT
CODES

70
60
50

/

40
30
20
10

1.2

.6

1.8

1.6

1.4

X10 3
NUMBER OF SAMPLES

Figure 5. Beat Frequency Test at 20 MHz

120
110
100
90
80
OUTPUT
CODES

70
60
50
40
30
20
10

o.

.9

.3

1.1

1.2

1.3

1.4

1.5

Xl0 J
NUMBER OF SAMPLES

Figure 6. 10 MHz Envelope Test

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-9

•

ADC·207
APPLICATION #4: FFT Test
This test actually produces an amplitude versus frequency
graph (Figure 7) which indicates harmonic distortion and signal to noise ratio. The theorectical RMS signal-to-noise ratio for
a 7-bit converter is +43.8 dB.
FFT WI T8 = 25n8

70

4 MHz FUNDAMENTAL
1........ 69.2

65
60
55
50
45
w

40

::l

35

0..

30

c

....
:::;
~

"..,
."

...... 27.3

25
20
15
10
5
0
-5
-10

1i~~I'

o

2

3

4

5

I

I

III
1.111 L----------.-.J
The ADC-208 utilizes an advanced VLSI
1.2 micron CMOS in providing 20 MHz
sampling rates at 8-bits. The flexibility of
the design architecture and process delivers effective bit rates to 30 MHz in the
burst mode, one shot mode conversion
times of 35 nanoseconds, low power
modes to 150 mW, latch-up free operation without external components and operation over the full military temperature
range.
The ADC-208 has 256 auto-zeroing comparators which are auto-balanced on every conversion to cancel out any offsets
due to temperature and/or dynamic effects. These comparators sample the difference between the analog input and the
reference voltages generated by the precision reference ladder network. Parallel
output data and the overflow pin have
Three-State outputs. The overflow pin allows cascading two devices for 9-bit operation.
The ADC-208 has no missing codes over
the full operating temperature range of
-55°C to + 125°C. Operation is from a
single +5V dc power supply.

Figure 1.

ADC-208 Simplified Block Diagram

ADC-208 LCC

..
llm...o...m
....o...m
....oml!

..i
T

0.075

I. ""

'Q.
+0.010

AOC-",
Lee

-0.005

ADC-208 DIP

I---

1.250
(3t,7)

J

----,

+[E~[I~

...l r~-~===~-.,.LO_060

0.190(4,9)

0.190(4,9)I

+ o.os;! f--

UUUUUUUUUUUUT(1,5)
0.020

(1,3)

--j

1-0.100
(2,5)

INPUT/OUTPUT
CONNECTIONS

±0.008

PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16.
17
18
19
20
21
22
23
24

FUNCTION
Voo
CLOCK
-REFERENCE
ANNDIG GND (VSS)
ANALOG INPUT
REFERENCE MID-POINT
ANALOG INPUT
ANNDIG GND (VSS)
+ REFERENCE
Voo
CST (OUTPUT ENABLE)
CS2 (OVERFLOW ENABLE)
OVERFLOW BIT
BIT 1 (MSB)
BIT2
BIT3
BIT4
REF 314 FS
Voo
REF1/4FS
BIT 5
BIT 6
BIT 7
BIT 8 (LSB)

(0,5)

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-11

ADC-208
ABSOLUTE MAXIMUM RATINGS

PERFORMANCE

DESCRIPTION

LIMITS

UNITS

Power Supply Voltage
(Voo Pin 1,10,19)
Digital Inputs
Analog Input
Reference Inputs
Digital Outputs
(short circuit protected
to ground)
Lead Temperature(10 sec)
Storage Temperature

-O.S to +7.0

Vdc

-O.S to +S.S
-O.S to +Voo+O.S
-O.S to +Voo +O.S
-O.S to +S.S

Vdc
Vdc
Vdc
Vdc

+300 max.
-6Sto +1S0

°C
°C

FUNCTIONAL SPECIFICATIONS
Apply over the operating temperature range and over the
operating power supply range unless otherwise specified (1S
MHz clock, +Reference = +SV, -Reference = Ground, unless
otherwise noted).

ANALOG INPUTS
Slngle-Ended,NonIsolated Input Range
dc-20 MHz
Analog Input
Capacitance
(static - Pin 5 to Pin 7)
(dynamic- Pin 5 to Pin 7)
Ret. Ladder
Resistance
Ret. input (Note 5)

MIN. TYP. MAX.

UNITS

0

-

+5.0

V

-

10
64

-

If'
If'

-

300

-

Ohms
Vdc

No Missing Codes

-

-0.5

Voo +0.5

DIGITAL INPUTS
Logic Levels
Logic 1
Logic 0
Logic Loading
Logic 1
Logic 0
Clock Low Pulse
Width

MIN. TYP.

Int. Lin. at +25 °C
(See Tech. Note 7)
(Ref. adjusted)
End-point
Best-fit Line
Int. Lin. Over Temp.
(Ref. adjusted)
Best-fit Line
Int. Lin. at +25 o C
(Ref. unadjusted)
End-point
Best-fit Line
Int. Lin. Over Temp.
(Ref. unadjusted)
End-point
Best-fit Line
Zero-Scale Offset
(Code "0" to "1" Transition)
Gain Error
Differential Galn@
Differential Phase@
Aperture Delay
Aperture Jitter
Harmonic Distortion
(8 MHz 2nd Order Harm.)
Ref.Bandwidth
(See Tech. Note 5)
Power Supply Rej.

POWER

MAX.

UNITS

-

-

±1/2
±1/2

LSB
LSB

-

±1/2

±1

LSB

-

:f2
±1.6

±2.5
±1.9

LSB
LSB

-

±2.3
1.8
1

±2.6
±2.0
3

LSB

-

±1

-

-

-

2
1.1
8

-

LSB
LSB
LSB
%
degree
nSec.
pSec.

ffi

-

-40

-

46
10

-

dB
MHz

-

-

0.02

%FSR/%lVs

-

-

Over the ooeratino temoerature ranoe

REQUIREMENTS

Pwr. Supply Range (+VDD )
Power Supply Current
Power Dissipation

+3.5

-

+5.0
+100
500

+5.5
+130
715

Vdc

+70
+125
+150

OC
OC
OC

rnA
rITN

PHYSICAL-ENVIRONMENTAL

-

2.0

-

-

-

0.8

Vdc
Vdc

-

-

+1
+1

iii
iii

f.lA
f.lA

15

2)

-

nSec.

-

4.5

-

5.0
0.4

Vdc
Vdc

4
4

-

-

mil.
mil.

5

10

15

nSec.

Oper. Temp. Range
MCILCGrade
MM/LM/883B
Storage Temp. Range
Package Types
(DIP)
(LCC)
Pins (DIP)

0

-55
-65

-

24-pin hermetic sealed, ceramic DIP
24-pin hermetic sealed, ceramic LCC
0.01 x 0.018 inch Kovar

DIGITAL OUTPUTS
Logic Levels
Logic 1
Logic 0
Logic Loading
Logic 1
Logic 0
Output Data Valid
Delay from Rising
Edge
Coding
Resolution

Straight Binary
8 Bits

1-12

TECHNICAL NOTES
1. Tie all V DD pins (1,10, & 19) together.
2.

PERFORMANCE
Sampling Rate.@
Full Power Bandwidth
Diff. Linearity a1+25°C
(See Tech, Note 7)
Code Transitions
Center of Codes
Ditt. Lin. Over Temp.
Code Transitions
Center of Codes

NOTES:
_..'_<__~

0.0

0.2

04

\,
\\

_ _~--'LL_~_ _~_.w...-'--

0.6

08

_ __

10

18

Figure 5b.
Beat Frequency Test at
Fclock = 10 MHz, Fin -= 10.015 MHz

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-15

ADC-208
CODES
E + 3

DHUTAL

15.02 MHz BEAT FREQUENCY TEST

CODES

15 MH~ CLOCK, 15 KHz ENVELOPE

0.26

0.18
0.16

0.12

\

0.10

\

0.08

006

0.06

;'

0.02

o~----------~~~-------------=--~--------A
~2
U
~
U

0.0
0.0

02

0 ..

1.0

1.2

1.6

1.8

2.0
OUTPUT SAMPLQ

Figure 5c. Beat Frequency Test at
Fclock
15 MHz, Fin
15.02 MHz

=

Figure 6c. Envelope Test at Fclock = 15 MHz

=

DIOffAl
CODES

ENVELOPE

20 MHz CLOCK, 20 KHz ENVELOPE

TEST

Figures 6a, 6b, 6c, and 6d show the actual plot of the Envelope Test. This test is a variation of the Beat Frequency test
using a sine wave input to give two overlapping cycles when
the data is reconstructed by a OfA converter output to an oscilloscope. An input signal offset in frequency from the Nyquist Rate will result in consecutive samples at 180 degree intervals on the waveform.

0.22

0.14

DIGITAL
CODES

5 MHz

CLOCK,

5 KHz ENVELOPE

o~--------~--=---------~--~~~----------o
0.2

Figure 6d. Envelope Test at Fclock = 20 MHz
The scope is triggered by the clock used by the AID. Any
asymmetry between positive and negative portions of the signal will be very obvious. This test is a an excellent indication
of slew rate capability. At the peaks of the envelope, consecutive samples swing completely through the input voltage
range.
U

~

OUTPUT SAMPLES

Figure 6a.

Envelope Test at

Fclock

=5

MHz

DIGITAL
CODa

FFT TESTS
These tests produce an amplitude versus frequency graph
(Figures 7a, 7b, 7c, and 7d) which indicates harmonic distortion and signal to noise ratio. The theoretical RMS signalto-noise ratio for an 8-bit converter is 49.8 dB.

lOMHz CLOCK, lOKHzENVELOPE
AMPUfUDE
dB
5MH z CLOCK, 2MH z In,.42.5dB SNA

0.24

~-~-.,.---.

t

-T-- ---r-----'--- --,
,

I

,

0.2
0.18

0.08

0,

0.8

0.9
0.4

OUTPUT SAMPLES

Figure 6b. Envelope Test at
1-16

Fclock = 10 MHz

0.6

16

Figure 7a. FFT Test at Fclock = 5 MHz, Fin = 2 MHz

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

,

ADC-208

,.

,.

AMPLITUDE

AMPLITUDE

10 MHz

,

;

CLOCK, "MHz In, 42.6 d8

SNR

"

"

"

15MH, CLOCK, 2MH z In, 4300B

SNR

"

&1~~~~~,il~ij~I~~~I~~I\\~I~1
"o
FFT Test at Fclock = 10 MHz,
Fin = 2 MHz

Figure 7b.

0.5

1,0

15

2.0

30

35

4.0

45

S,D

FFT Test at Fclock = 15 MHz,
Fin = 2 MHz

Figure 7c.

,.

25

AMPLITUDE

LOW POWER MODES

20MHz CLOCK, "MHz "', 41.4dB

SNR

Power Supply Aspect of Power Dissipation
,

Reduction of the Voo power supply of the ADC-208 results in
lower power dissipation. Refer to the curve of Figure 8 for power dissipation as a function of Voo, The limiting factor is Voo
must be greater than the TIL or CMOS output levels, Interfacing to standard logic families presents little problem as the output drivers go to Voo for a high state and to VSS for a low state,

50

~

-

~

-

-- ~ - -

-------,_ ... _-'---,----- -,

,

,

-.,,, --- _.. -- ,,... -- --- - -,,, -,
,
-

---," -- --

-

-

I
"---'-

- - - -- -'-- -. _.- - --

- -- -'--

- ~.

I
-"-

,

I

I

I

- "_.'
I

I

, --" -- _..., ------ - ,' - - " -- -- ,
"
,

~

"

~

i·~~~~

BURST MODE
Applications can utilize an inherent system clock up to 30
MHz in the burst mode, The system clock can generate a one
shot for a single conversion without requiring generation of a
separate clock at a lower frequency,
AUTOZEAO

"·-----i-- --- ------- .....

." o

FREQUENCY

FFT Test at Fclock = 20 MHz,
Fin = 2 MHz

Figure 7d.

AUTOZERO

CLOCK

LO POWER

LOW

IDD(mA)

Figure 9a.

Burst Mode for Low Power

200

/

/
//

/

Po (5V)

Po (3.5V)

//
/

/

-----

/

875mW-----613mW /

-

-

_ _ 175mW

//

-

175

.....

_

150

-

--

~____ --

--.---

.,'

--- - - - ----

"

/.-;a

100

/'

!.~5MHz

..

75

/'

.... ~...-.......-1 MHz

---

--------

/~.f'

/.'

/.~.• ,

10MH z

--

.,'
/

125

____ -

5OOmW----- 350mW ---375mW - - - - - 2 6 3 m W - 125mW - - - - - 88mW

//
/

/ / __

750mW-----525mW 625 mW - - - - - 438 mW -

250mW -

/

'

/,.

50

..

, .'/ "

/.

25

... -: ..
--;.",: ..:

/

.; "
'

-

VOO(VOLTSI

Figure 8. Power Dissipation Versus

VDD

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

1-17

ADC·208
Clock Aspects of Power Dissipation
Varying the CLOCK rate or duty cycle results in lower power
dissipation. The majority of the power dissipation occurs during the auto zero mode.

Figure 11 shows power dissipation as a function of the clock
duty cycle. A conversion time of 35 nanoseconds can be obtained for a single conversion by leaving the clock in the Autozero mode. To initiate a conversion, the clock is put in the
sample mode for 25 nanoseconds and then brought back high
to the Auto-zero mode. Data is valid 15 nanoseconds after the
clock goes high, eliminating the pipeline delay.
POWER
DISSIPATION

CLQCKIN

BOOmW

700mW
GROUND

600mW

+5VOlT$

N01E: Reduce the sample time (sample pulse) to 12 nsec. to improve
perfonnance above 20 MHz. Such a configuration will closely
resemble an ideal sampler.

Figure 9b. Optional Clock Pulse Shaping Circuit

500mW

400mW

300mW

Figure 10 shows power dissipation as a function of burst rate
and repetition rate. Applications not requiring continuous
conversions can give a double clock pulse, the clock returning low between conversions to reduce power dissipation.
Power dissipation is essentially eliminated when the clock
and signal input are turned off.

25 n Sec.
AUTO-ZERO

200mW

I

25 n se~. SAMPLE

100mW'4---~--+---+---r-~~~--~---+--~--~
10% 20%
30% 40% 50%
60% 70%
80% 90% 100%
CLOCK DUTY CYCLE

Figure 11. Power Dissipation vs. Duty Cycle
for One-Shot Mode

BOmA
25MHz

70mA

60mA

SOmA

J:1iJl"F REP I •SQ:
40mA

H

LATCH VAllO
DATA

lIF BURST

ORDERING INFORMATION

30mA

0.1

0.5 1MH z

2MH z

3MH z

4MHz

5MH z

6MH z

REPITJTlON RATE

.,BURST RATE = 35 MHz

X-15 MHz BURST RATE

...·BURST RATE = 25 MHz

.·20MHz BURST RATE

.·30 MHz BURST RATE

Figure 10. Power Dissipation vs. Burst Rate
vs. Repetition Rate

1·18

MODEL

TEMPERATURE
RANGE

PACKAGE

ADC-208MC
ADC-208MM
ADC-208/883B

o°C to +70 °C
-55 °C to +125 °C
-55°C to +125 °C

24-pin DIP
24-pin DIP
24-pin DIP

ADC-208LC
0 °C to +70 °C
ADC-208LM
-55 OCto +125 °C
ADC-208L1883B -55°Cto+125°C

24-pin LCC
24-pin LCC
24-pin LCC

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-300
a-Bit Video
AID Converter
FEATURES
•
•
•
•
•
•
•

8 Bits at 20 MHz
700 mW power dissipation
+ V. lSB linearity
Buffered outputs
Single supply operation
Eel-compatible
Input bandwidth 5.5 MHz
(MSB)

High
Comparator

GENERAL DESCRIPTION
DATEl's ADC-300 is a bipolar monolithic
video speed, low power, 8-bit flash AID
converter capable of digitizing an analog
signal at conversion rates up to 20 MHz
minimum with power consumption of only
700 mW.
A serial/parallel technique is employed to
obtain the high conversion speed using a
single -S.OV power source. The analog
input range is 0 to -2V (with -2V ref) and
digital inputs and outputs are ECl-compatible. The outputs are buffered and provide an open emitter output.

Output
Butler

aod
Encoder

Low

Matrix
Circuit

Comparator

Output

.od

Buffer

Encoder

+VREF

28

(LSB)

elk

The ADC-300 is designed to operate with
an external sample and hold together with
external clock and reference sources. It is
ideally suited for applications that require
high speed digitization and low power, e.g.
CRT graphics, radar pulse analysis, motion
signature analysis and optical character
recognition.
The ADC-300 is supplied in a 28-pin DIP
and operates over temperature range of
-10 to +70°C.

APPLICATIONS
•
•
•
•
•
•
•
•

High speed data acquisition
Radar pulse analysis
TV video encoding
High energy physics
Transient analysis
Medical electronics
Fluid flow analysis
Sonar systems

MECHANICAL DIMENSIONS
Inches
Unil'(mm)

1------''';.c6c;.61----I'1

0155

'::;:'~'f~ ~~

~'5~{][~IT

INPUT/OUTPUT CONNECTIONS

P'"

,
6
7

FUNCTION

PIN

BIAS (NOT TO BE CONNECTED)

28

REF. VOLTAGE I 2.0V)

CLOCK INPUT

27

ADJUST REF, (AR3)

CLOCK INPUT

26

,cIDJUST REF. (AR2)

DIGITAL GROUND

25

B!T 8 (lSB) ___

"
"
"
"
"
"
"

BIT7
81T6

20

0019
O'5IMON

0.022 ±O.009

~

lo,ss)j

""

DIGITAL GROUND

V SUPPLY

5

"

FUNCTION

ADJUST REF. (ARt)
REF VOLTAGE(OV)

V,SUPPLY( 5\1)
ANALOG GROUND
ANALOG INPUT

ANALOG GROUND
V_SUPPLY ( 5V)

~~~~~~~~~:~~-NO CONNECTION
DIGITAL GROUND

(3,2)0.125

0,05111,31

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-19

ADC-300
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Vs) ...... . -9.0V
Analog Input (VIN) ........ . Vsto +0.3V
Clock Input .............. . Vsto +0.3V
Reference Voltage Input .. . Vs to +0.3V
Digital Output Current .... . 10 mA
Package Dissipation ...... . 1.47 Watts

1. Analog input signals must be 'held' by an external sample-hold
e.g. using a DATEl SHM-40, SHM-360 or SHM-361. Careful
attention must be paid to the timing relationship between the
sample-hold transition of the sample-hold amplifier and positive
transilion of the clock pulse - see liming diagram.

FUNCTIONAL SPECIFICATIONS
Typical at +25°C, Vs = -5V dc, reference volt.
otherwise stated.
INPUTS
Analog Input Range ...
Analog Input Current
VIN = -1.0V ..........
Analog Input
Capacitance ........
Ladder Impedence ....
Reference VOltaRe ....
Clock Voltage (1 .....
Clock Voltage (0) .....
Clock Current ........
Clock Frequency ......

2. The input capacitance to the converter, pin 21, is 70 pF (typical)
and the input bias current 20 !LA (typical).

= -2V

dc unless

MIN.

TYP.

MAX.

UNITS

0

-

-2.0

V

20

37

/LA

45
-1.90
-0.74
-1.60

-

20

70
50
-2.0V
-0.89
-1.75
20
30

56
-2.10
-1.04
-1.90
34.5

pF
Ohms
V
V
V
/LA
MHz

OUTPUTS
Output Logic
(1) RL = 4.3K ....... Output Logic
(0) RL = 4.3K ....... -1.35

-0.75

-0.90

V

-1.50

-

V

POWER

Po~e~ ~~~~~~.~~~ ...

110
Supply Voltage .. .. ... - 4.75

140
-5.0

160
-5.25

mA
V

PERFORMANCE

3. The reference voltage, -2.0 volts, is connected to pin 28 with
pin 24, the upper end of the resistor chain, grounded. The 'R'
value between pins 24 and 28 is 50 Ohms (typical). It is recommended the reference input is decoupled using a 1 /LF (tantalum)
and a 1000 pF (ceramic) capacitor located as close to pin 28 as
possible.
4. For most applications, the ADC-300 accuracy will be more than
sufficient. However where accuracy greater than that specified
is required, the VREFJ4, VREFJ2 and VREF3J4 points can be
trimmed using external resistors connected from pins 25, 26
and 27 to ground, pin (24), or VREF, pin (28), as required.
When pins 20, 26, and 27 are not being used, they should be
connected to ground via a 0.047 /LF capacitor.
5. The printed circuit board should be laid out to have substantial
analog and digital ground planes. The ground plane separation
is required as part of the chip design and should be maintained
on the PCB. The planes should be connected at one pOint only,
usually power common.
6. The -5.0V supply should be decoupled using 3.3 /LF tantalum
and 0.022 ,...F ceramic capacitors.
7. The digital output terminals are driven from open emitters. The
output current should not exceed 10 mA (4.3K Ohms are equivalent to 1 mAl. Table 1 shows the digital codes relating to the
analog input voltages.
8. An external complementary ECl signal source is required to
drive the clock input terminals.

Resolution ................ 8 Bits
Conversion Speed (Min) ... 20 MHz
Non Lineari:J. (Max) ....... ±'hLSB
Differential on Linearity
. (Max) ................... ±V2 LSB
Differential Gain (T~) ..... 0.7%
Differential Phase ( yp) .... 0.3 Degrees

9. Pin 1 must be left open and not used; pins 16, 17 and 18 are not
internally connected and should be grounded.

PHYSICAUENVIRONMENTAL
Operating Temperature
Range ..................
Storage Temperature
Range ..................
Package ..................

-10°C to 70°C
-50°C to 150°C
28-Pin plastic DIP

TABLE 1. DIGITAL OUTPUT CODES
OUTPUT CODE

1-20

lSB

STEP

INPUT VOLTS (-2V FSR)

0
1
2

O.OOOOV
-0.0078V
-0.0156V

1
1
1

1
1
1

1
1
1

1
1
1

1
1
1

1
1
1

1
1
0

127
128
129

-0.9961V
-1.0039V
-1.0118V

1
0
0

0
1
1

0 0
1 1
1 1

0
1
1

0
1
1

0 0
1 1
1 0

255

-2.0000V

0

0

°

0

0

0

0

MSB

1
1
1

0

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

ADC-300
TIMING DIAGRAM

•

(SAMPLE)

N
Sampling pulses

N+2

N+l
(HOLD)

v,

Sample/hold

Output

v,

Clock

8;151.2.3&4
output

Bits 5, 6, 7,&8
output

v,

v,

Data-N

Data N+l

Data Valid

~

DataValid

TIMING DIAGRAM NOTES
1. The high comparator (MSB, Bits 2, 3 and 4) compares VREF with
V,N on the negative transition of the clock. The timing must be
such that the sample/hold has acquired the input level and
settled in the hold mode. If TA is the time between the sample/
hold transition to the negative transition of the clock then:
TA > sample hold aperature delay + settling time.

(b) In time TE the data for MSB, bits 2, 3, and 4 become valid
where:
TE < 8 nsec.
(e) In time TE + TD the data for bits 5, 6, 7, and 8 become valid
where:
TE+ T D < 12 nsee.

2. The positive transition of the external clock should occur
after time T. where: T. > 22 nsec. where:
From this transition three operations will be timed.
(a) In time Tc the next sample/hold pulse can be sent where:
Tc> 2 nsec.

3. At the time TA + T B + T E + To' all data outputs become valid.
The output data can be latched at this time, however, the simpler
and more reliable time to latch the outputs is the negative transition of the clock.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-21

ADC-300

CONNECTION AND APPLICATION

-5V

1

Note: 1. Analog inputrangeOto -2v.
2. Input bandwidth 5.5 MHz typical

~

4

r r
V'N

-

-2 Volt
Reference

O.022J.d~ 3.3~F'±

28

21

Ay

13 20 22 24 14 19 23

~

Sample!
Hold
SHM-361

A A AA AAA

1 III I I 1

AOe-30D

12

MSB

"

81T2

10

81T3

9

81T4

8

BIT5

7

81T6

6

BIT7

5

LSB

27

=
=~ ::h

O.047~F

0.047 p.F

26
R

25

~

4.3KOhms

'Ff
O.047p.F
24

3

I

eLK

2

lelK

20 MHz Clock
sod
Timing Circuit

ORDERING INFORMATION
MODEL NO.

OPERATING
TEMPERATURE
RANGE

ADC-300

-10°C to + 70°C

NOTE: For units with high-reliability processing, contact the
factory.

1-22

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-301, ADC-302
8-Bit Video
Flash AID Converter

•

FEATURES
ADC-301
•
•
•
•
•
•

8-Bit resolution
Non-linearity ±'12 LSB
Conversion rate 30 MHz
15 MHz bandwidth
35 pF input capacitance
Power dissipation 420 mW

ADC-302
•
•
•
•
•
•

8-Bit resolution
Non-linearity ±'h LSB
Conversion rate 50 MHz
25 MHz bandwidth
35 pF input capacitance
Power dissipation 550 mW

GENERAL DESCRIPTION
These ADC's are video speed 8-bit flashes
capable of digitizing analog signals at conversion rates of 30 MHz (ADC-301) and
50 MHz (ADC-302) with a power consumption of 420 mW and 550 mW respectively.
The 256 clocked comparators have the
analog voltage applied to one input and a
voltage derived from the reference voltage
and reference resistors applied to the other
comparator input.

MIN V LlNV

The comparator outputs are 'anded' with
adjacent outputs and these outputs latched
into a 6-bit encoder. These 6-bit codes
are further encoded to 8-bit codes and
latched. The final ECl output buffer stage
requires external pull down resistors, the
output being delayed from the sampling
point by the time of one clock cycle.
Output polarity of the MSS and lSS's respectively can be controlled on two digital
input lines.

MECHANICAL DIMENSIONS

With a reference of -2V the analog input
range will be 0 to -2V.

INPUT/OUTPUT CONNECTIONS

0.010 + 0.004
·0.002

APPLICATIONS
•
•
•
•
•
•
•
•

High speed data acquisition
Radar pulse analysis
TV video encoding
High energy physics
Transient analysis
Medical electronics
Fluid flow analysis
Sonar systems

,lo.5I..l.M
I
JI n6~~1

1

%'I'I'I'I'I'I'¥I'¥I~d
10.51

0.047 (1.2)
:t;

0.007

FUNcnON

28

ANALOG Vs 1- 5.2V)

27

REFERENCE INPUT V, 1- OV)

D'GITAL GROUND

26

ANALOG Vs 1-5.2V)

BIT8ILSB)

25

ANALOG GROUND

BIT7

2'
23

ANALOG INPUT

BIT6
7

BIT5

22

REFERENCE Vm

8

BIT 4

2,

ANALOG GROUND

BIT 3

9
,0

20

ANALOG INPUT

,9

ANALOG GROUND

,8

ANALOG Vs 1- 5.2V)

17

REFERENCE INPUT Vb - 2

'6

CLOCK INPUT

i : = = I 4 (4.8)

"

,2

DIGITAL GROUND

,.

DIGITAL Vs 1-5.2V)

_

r

0.118
(3.0) MIN

'3

ANALOG GROUND

BIT 2
BIT, MSB)

11

0.020 + 0.005

PIN

DIGITAL Vs (- 5.2V)

3

0.019
'N-

FUNCTION
OUTPUT POLARITY ILlNV)

OUTPUT POLARITY MIN

,5

CLOCK INPUT

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-23

ADC-301, ADC-302
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS
Supply Voltage Vs ........ . 010 -7V
Input Voltage (V'N) ....... . 0.5Vlo Vs
Reference Voltage
V" Vb, Vrn .•.•••.•..••••.• 0.5Vlo Vs
Reference Voltage
(Vb -V.) ................ . -2.5V
Digitallnputs ............ . O.5V to -4V
Vm Input Current. ........ . -3 mA to +3 mA
Digital Outputs ........... . Oto-l0mA
Operating Temperature ... . -20°C to +100°C
Storage Temperature ..... . -55°C to +150°C
Allowable Power
Dissipation ..... .
1.48W

1. Even with the input capacitance down to 35 pF, or less, the
converter still requires an input amplifier with good drive capability. The amplifier will require wide bandwidth and a high slew
rate (250V / !J.S typical) to take full advantage of the input
bandwidth of the converter.
2. The input impedance of the AID's are capacitive which may
result in the input amplifier becoming unstable and cause oscillations. A resistor with a value between 2 and 10 Ohms
between the amplifier and the input to the converter will stop
any oscillations.
3. Clock and Clock (ECl) are usually differentially supplied to pins
16 and 15.

FUNCTIONAL SPECIFICATIONS
Typical al +25°C, Vs = -5.2V dc, VB = -2.0V
unless otherwise stated.
PERFORMANCE

ADC-30l

ADC-302

Resolution ................
Conversion Rate (Min) .....
Non-Linearity (Max) .......
Diff. Non-Linearity (Max) ...
Diff. Gain (Max) ...........
Diff. Phase (Max) ..........
Aperture Jitter (Tr.r,) ......
Input Bandwidth ~) .....
Power Dissipation yp) ...

8 Bits
30MHz
+';' LSB
+'h LSB
1.5%
0.5 Deg.
45 psec.
15 MHz
420mW

8 Bits
50 MHz
+';' LSB
+';' LSB

INPUTS
Reference Input
Voltage ....... .....
Reference
Resistance ...... ...
Analog Input
An~~~t:Y;pu't' .........
Capacitance ........
Analog Input Bias
Current
(ADC-30l) ........
(ADC-302) ........
Offset Voltage V. . ....
Vb .....
Digital Input Voltage
Vh .................
V, ..................
Di?-ita~ Inc.ut Current
Vh - - .9V) .......
(V, = -1.75V). . . . . . .

5. The digital outputs Bits 1 to 8 require pull down resistors, in the
range 500 to 1000 Ohms, connected to the negative supply rail
to prevent waveform distortions by reflection.

1.5%

0.5 Deg.
30 psec.
25 MHz
550mW

6. The reference voltage range (-2.0V to OV typical) determines
the dynamic range of the input voltage.

MIN.

TYP.

MAX.

UNITS

-1.8

-2.0

-2.2

V

70

80

0.1

-

-2.2

V

-

35

40

pF

7
15

60
75
9
17

90
115
11
19

-<).7
-1.6

-0.9
-1.75

100

Ohms

Adjustments to this range can be made within the range VB
= 2V ± 0.2V and V T =OV ±O.IV. The reference input VB (pin 17)
should be decoupled to analog ground using 1 !J.F and 0.01 !J.F
capacitors. Improvement in the high frequency stability can be
achieved by decoupling terminal V M (pin 22) using a 0.01 !J.F.
7. Terminal V M is used to achieve less than a!. 'f? lSB nonlinearity error. The external circuit to achieve this is shown in the
application drawing.
8. All pins not being used should be grounded.

-

0
-0.05

-

-1.0

-

-1.0
-1.9

!J.A
!J.A
mV
mV
V
V

0.4
0.35

mA
mA

OUTPUTS
Digital Output Voltage
Vh(Rl=6200) .....
V,(Rl=6200) ......
OUW,U! Data Delay
( l- 620 0) ...... ..

4. The polarity of the output data is controlled by two pola;ity
inversion inputs, MINV (pin 14) which controls the MSB alone
and LlNV (pin 1) which controls Bit 2 to Bit 8 (lSB). The combination of 'O's and '1' on these inputs offer the user various code
options. Detailed coding is shown in Table 1. logic level '0' is
obtained by leaving inputs open, logic level '1' is obtained by
connecting a 3.9K Ohm resistor to digital ground.

-

-

-

V

-1.6

4.0

5.0

nsec.

9. Substantial analog and digital ground planes must be provided.
It is recommended that these ground planes are taken to a
common point, the power ground line, as close to the converter
as possible.
10. The power supplies to analog and digital inputs (-5.2V) should
be supplied from separate, isolated power supplies. If one of
the power supplies fails or is shorted to ground for more than 1
second there is a possibility the device may be destroyed. Both
-5.2V lines should be decoupled using 1 !J.F and 0.01 !J.F
capacitors located as close to the pins as possible.

V

TABLE 1. DIGITAL OUTPUT CODES

POWER
Supply Voltage, Vs ....
Supply Current
(ADC-30ll
(ADC-302l

1·24

-5.0

-

-5.2

-5.7

V

MINV
LlNV

0
0

0
1

1
0

1
1

-75
-95

-100
-120

mA
mA

O.OOOOV
-0.0078V

1111 1111
1111 1110

1000 0000
1000 0001

0111 1111
0111 1110

0000 0000
0000 0001

-0.9961 V
-1.0039V

1000 0000
0111 1111

1111 1111
0000 0000

0000 0000
1111 1111

0111 1111
1000 0000

-1.9922V
-2.0000V

0000 0001
0000 0000

0111 1110
0111 1111

1000 0001
1000 0000

1111 1110
1111 1111

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-301, ADC-302

TIMING DIAGRAM

•

V,N

Analog input

Clock

ClK
ClK
Comparator output
Master

Slave

6 Bit latch output

8 Bit latch output

Data output Bit 1 - Bit 8

Dots (e) Indicate latch timings

TIMING NOTES
1. Both Clock and Clock are required and the input levels are ECL.
The timing T, and T2 should be:
T, (MIN)
T2 (MIN)
ADC-301
25 nsee.
8 nsec.
ADC-302
15 nsec.
5 nsec.

2. The positive transition of the clock latches the comparator outputs into the 'and' gates.

3. The negative transition latches the 'anded' outputs into the 6-bit
encoder.
4. The next positive transition will latch the 6-bit encoder output as
well as starting the next conversion cycle.
5. The 8-bit encoder output will appear at the output pins 4.0 nsec.
(typical) T3 after 6-bit encoder output has been latched on the
next negative transition of the clock.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

1-25

ADC-301, ADC-302

CONNECTION AND APPLICATION

A.Gnd

D.OM

OIGV"

AN,V,.

5.2V

I.'

GND

GNO

52V

O.Ol,.F

",

18.26,28

19.21.23.25

J.12

A,Gnd

10

ov

REF

,v

ADC-301
or
ADC-302

v

,V

2,13

20.24

....-+-++-H-+-+--

B."

t-....++-H-+-+-t---+-H-+-+--

8,,3

(M$B)

8,12

t----H-+-+-- 8,,4
t---~'_t-+-+-- BI15

t------4'-t-+-t-------+-t--------4---

17

B,,6

B'I7

B,,8 (LSBI

• 8" 620Qhms
• • AlternatIVely AM 1435

ORDERING INFORMATION
MODEL NO.

ADC-301
ADC-302

OPERATING
TEMPERATURE
RANGE
-20°C to + 100°C
-20°C to + 100°C

ACCESSORIES

Part Number

Description

TP 1K

Trimming Potentiometer

Note: For units with high-reliability processing. contact the factory.

1-26

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-303
a-Bit Video
Flash AID Converter

•

FEATURES
•
•
•
•
•
•

a-Bit resolution
Speed up to 100 MHz guaranteed
±'hLSB linearity
Input bandwidth 40 MHz
Output latch and buffer
Low input capacitance, 35 pF typical

GENERAL DESCRIPTION
The ADC-303 is a video speed 8-bit flash
converter capable of digitizing analog signals at conversion rates up to 100 MHz
minimum and with a power consumption
of only 1.2 watts at 100 MHz sampling rate.
The 256 clocked comparators have the
analog voltage applied to one input and a
voltage derived from the reference voltage
and reference resistors applied to the other
comparator input.
The comparator outputs are 'anded' with
adjacent outputs and these outputs latched
into a 6-bit encoder. These 6-bit codes
are further encoded to 8-bit codes and
latched. The final ECl output buffer stage
requires external pull down resistors, the
output being delayed from the sampling
point by the time of one clock cycle.
Output polarity of the MSB and lSB's respectively can be controlled on two digital input
lines.

MINV

lINV

With a reference of -2V the analog input
range will be 0 to -2V.

APPLICATIONS
•
•
•
•
•
•
•
•

High speed data acquisition
Radar pulse analysis
TV video encoding
High energy physics
Transient analysis
Medical electronics
Fluid flow analysis
Sonar systems

MECHANICAL DIMENSIONS

INPUT/OUTPUT CONNECTIONS

UNIT: INCHES
(MM)

2.13

C=(53.9) MAX -

~~:~

42
1

~

---l
I

J
~~

22

-'-

",,~=~~~;;;;-'---

1~'8

It-.
x 0.100 =2.0

/0-9

0.178
(4,5).MAX

20

f

21o~..l

0.53
(13,5)

-110.'00(2.54)

0.010

" [ - (0.25)

(0.46)

0.039

~(l'O)MIN

-~

-tllr

0.145

~1~~r--l ~(3.7) MIN

,7

DIQI1Al SUPPLY DV,(

"<\Ii

26

ANALOG SUPPLYV,I-52V1

25

ANALOG SUPPLY V, I

23

AEHREN(.;EVel 20111

~2Vl

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-27

ADC-303
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS
Power Supply - Vs ....... . o to -7V
Analog Input (VIN) ........ . +0.5V to Vs
Reference Voltage
VT + VM + Va ............ . +0.5V to Vs
[V, - Vi]· ... · .... ·· ... ·. 2.5V
Input current at VM ....... . -3 mA to +3 mA
Digital Inputs ............ . 0.5V to -4.0V
Digital Output Current .... . 010 -10mA
Operating Temp•.......... -20°C to +100°C
Storage Temp............ . -55°C to +150°C
Power Dissipation ........ . 3.1 Watts

1. Even with the input capacitance down to 35 pF, or less, the
converter still requires an input amplifier with good drive capability. The amplifier will require wide bandwidth and high slew
rate (250V I p.S typical) to take full advantage of the 40 MHz
bandwidth of the converter.
2. The input impedence of the AID is capacitive which may result
in the input amplifier becoming unstable and cause oscillations.
A resistor with a value between 2 and 10 Ohms between the
amplifier and the input to the converter will stop any oscillations.
3. Clock and Clock (ECl) are usually differentially supplied to pine
20 and 21. However a single clock input can be used if a 1000
pF capacitor is added between pin 20 (clock) and pin 16 (digital
ground).
4. The polarity of the output data is controlled by two polarity
inversion inputs, MINV (pin 18) which controls the MSB alone
and LlNV (pin 3) which controls bit-2 to bit-8 (lSB). The combination of 'a's and '1' on these inputs offer the user various code
options. Refer to the coding table. logic level '0' is obtained by
leaving inputs open, logic level '1' is obtained by connecting a
3.9K .Ohm resistor to digital ground.

FUNCTIONAL SPECIFICATIONS.
Typical at +25°C, V. = -5.2 V dc, Va = -2.0V unless otherwise
stated.
ELECTRICAL
PERFORMANCE

MIN.

Conversion Rate ....... ...
100
Input Capacitance ..... ....
Input Bias Current
(VIN =-IV) ..............
-1.8
Ref. Voltage .............
Reference Resistance
70
(Vrlo Va) ...............
6
Offset Voltage VT ..........
14
Va ..........
Digital Input Voltage VIH ... -0.7
Vil ... -1.6
Di~itallnput Current
0
VIH Typ.) IIH .............
Vil T~P.) i!L ............. -0.05
Di"ital utput Voltage
Rl =620) VOH ........... -1.0
VOL ...........
Interral Non-Linearity
100 MH~ ...........
Differential
on-Linearity
(35 MHz) .............
Differential Gain ...........
Differential Phase .........
Aperture Jitter ............
Supply Voltage ...... ...... --5.2
Supply Current ...... ..... -180
Output Data Delay........
3.0
(RLd20)
Sampling Delay ...........
1.9

TYP.

-

-

MAX.

-

UNIT
MHz

35

40

pF

150
-2.0

220
-2.2

p.A
V

SO
9
17
-0.9
-1.75

100
12
20
-1.0
-1.9

Ohms
mV
mV
V
V

5. The digital outputs, bits 1 to 8, require pull down resistors, in
the range of 500 to 1000 Ohms, connected to the negative
supply rail to prevent waveform distortion by reflection.

-

-1.6

-

V
V

6. The reference voltage range (-2.0V to OV typical) determines
the dynamic range of the input voltage. Adjustments to this
range can be made within the range of VB = 2 ±0.2V and VT =
OV ±0.1 V. The reference input VB (pin 23) should be decoupled
to analog ground using 1 p.F and 0.01 /IF capacitors. Improvement in the high frequency stability can be achieved by decoupiing terminal VM (pin 32) using a 0.01 /IF.

-

i:: 112

LSB

7. Terminal VM is used to achieve a less than ±V2 lSB linearity

-

± 112

LSB

error. The external circuit to achieve this is shown in the application drawing.

-

0.4
0.35

mA
mA

1.5
0.5

%

15
-5.2
-220
3.5

--5.7
-260
4.2

De9·
psec.
V
mA
nSec

2.2

2.5

nSec

-

S. All pins not being used should be grounded.

9. Substantial analog and digital ground planes must be provided.
It is recommended that these ground planes are taken to a
common point, the power ground line, as close to the ADC-303
as possible.
10. The power supplies to analog and digital inputs (-5.2V) should
be supplied from separate, isolated power supplies. If one of
the power supplies fails or is shorted to ground for more than 1
second there is a possibility the device may be destroyed. Both
-5.2V lines should be decoupled using 1 /IF and 0.01 /IF
capacitors located as close to the pins as possible.

DIGITAL OUTPUT CODES

MINV
LlNV

1-28

a

a

a

1

1

1
1

a

O.OOOOV
-0.00l8V

1111
1111

1111
1110

1000 0000
1000 0001

0111
0111

1111
1110

0000
0000

-0.9961V
-1.0039V

1000
0111

0000
1111

1111
0000

1111
0000

0000
1111

0000
1111

0111 1111
1000 0000

-1.9922V
-2.0000V

0000
0000

0001
0000

0111
0111

1110
1111

1000 0001
1000 0000

1111
1111

0000
0001

1110
1111

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-303

TIMING DIAGRAM

Analog mput

•

V1f>.J

_I_T,
Clock

eLK
eLK
Comparator output
Master

Slave

6 Bit latch output

8 Bit latch output

Data output Bit 1 - Bit 8

DaIs (e) Indicate latch timings

TIMING NOTES
1. Both Clock and Clock are required and the input levels are ECl.
The timing T, and T2 should be T, min. = 7.5 nsec. T2 min. = 2.5
nsec.

2. The positive transition of the clock latches the comparator outputs into the 'and' gates.

4. The next positive transition will latch the 6-bit encoder output as
well as starting the next conversion cycle.
5. The a-bit encoder will appear at the output pins 3.5 nsec. (typical) T 3 after 6-bit encoder output has been latched on the next
negative transition of the clock.

3. The negative transition latches the 'anded' outputs into the 6-bit
encoder.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

1-29

ADC-303

PERFORMANCE CURVES
Digital Output Vo~age

Input Bias current

-0.5

-0.9

~

200

-

r-

150

j

1

-1.3

~

z

~

100

~

i'- r-.

>

-1.7

50

-2.1
-25

25

75

50

100

-25

Ta ("Ci

40

100

r-----~r------r------~----_,

--.....

100

"~

N

I

.i!

75

Input Bias Voltage-Analog Input
Capacitance (typ.)

120

'"E"

50

TaCCi

Maximum Conversion Rate

~

25

80

20 ~-----4------4-------~----~

60

40
10r-----~r-----~------t-----_;

20
-25

25

75

50

100

TaCCi
-1

-2

Input DC Level M
Supply Voltage-Maximum Conversion
Frequency (typ.)

SNR

120

./

100

---

V

/'

~

50

~----~-------+------;-------r-~

~
~

80

E
.i!

60

40

4.5

1·30

5.0

5.5

6.0

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-303

PERFORMANCE CURVES
Spectrum with the aid of FFT at 102.4 MHz
sampling and 10.1 MHz input.

Elfectivebit
(dB)

F sample- 102.4000 (MHz)
Fin - 25.1 000 (MHz)
1024 Points FFT

0.0

SNR - 38.68 (dB)
EN Bit - 6.35 (bit)

-20.0

-40.0

-60.0

-80.0
5L__ _ _ __L_ _ _ _ _ _

o

10

~

_ _ _ __L_ _ _ _ _ _

0.00

40

30

20

L_~

10.00

20.00

30.00

40.00

fin (MHz)

Reconstructed waveform. 102.4 MHz
sampling, 10.1 MHz input.

Fsample = 102.400(MHz)

50.00
(MHz)

Spectrum with the aid of FFT at 102.4 MHz
sampling and 25.1 MHz input.

Fin" 10.000(MHz)
(dB)
0.0

32

F sample = 102.4000 (MHz)
Fin = 25.1000 (MHz)
1024 Points FFT

64
-20.0
96
128

SNR

=

30.60 (dB)

EN Bit = 6.35 (bit)

-40.0

160

-60.0

192
224
256

~

__

---'~=_""""

200

___-'-___L-_ _-LJ

400

600

800

-80.0

1000

0.00

10.00

20.00

30.00

40.00

50.00
(MHz)

Reconstructed waveform with the best
fitted sine wave. 102.4 MHz sampling,
25.1 MHz input.

F sample = 102.400 (MHz)

Envelope test waveform at 41.04 MHz
input and 81.92 MHz sampling.

Fin = 25.100 (MHz)

Or---------------------------------,

o

32

32

64

64

96

96

128

128

160

160

192

192

224

224

256 L-_ _--'-_ _ _-'-_ _......._ _ _......_ _--U

o

200

400

600

800

1000

rF_s_am~PI_e_=_8_1_.9_2_0~(M
__
H~Z)___
F_in_=_4_1_.04
__0~(M
__
H~Z)____________~

256

o

200

400

600

800

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1000

1-31

ADC-303

CONNECTION AND APPLICATION

AGnd

DGnd

DIGV~

ANV"

GNO

GND

1 ?5,26.J839

29.)1,33.35

5,6,15.16

14-+++-H-+-+--

,;>--_'11----; "
A Gnd

Bit 1 (MSB)

1--4--+-+-H-+-+-- Sit 2
I---+-H-+-+-- B'13

ADC-303
"

REF V
2V

I---+-H-+-+--

8,14

I-----<~_++--

8'15

1-----4_++-- B,16
2V

1---4-~'----i

23

f--------4---

"

8.t8 ILSBI

20

ORDERING INFORMATION
MODEL NO.

ADC-303

OPERATING
TEMPERATURE
RANGE
-20·C to +100·C

NOTE: For units with British Standard BS·9000 or other highreliability processing, contact DATEL.

1-32

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

ADC·304
a-BIT, 20 MHz

LOW POWER, FLASH AID
FEATURES
o
o
o
o
o
o
o

a-Bit resolution.
±V2 LSB non-linearity.
20 MHz conversion rate.
a MHz input bandwidth (-3 dB).
Low power consumptIon (390 mW).
TTL-compatible.
Single or dual supply operation.
~-

~­
~­

APPLICATIONS

~o
o
o

o
o
o
o

High-speed data acquisition.
Radar pulse analysis.
TV video encoding.
High energy physics.
Transient analysis.
Medical electronics.
Sonar systems.

y.~.

.~~':========~
GENERAL DESCRIPTION
DATEt.:s ADC·304 is an a·bit, 20 MHz analog·to·digital flash
converter. The ADC·304 offers many performance features not
obtainable from other flash AID's.
Key features include a low·power dissipation of 390 mWand
TTL compatible outputs. A wide analog input bandwidth of
a MHz (-3 dB) allows operation without the need of a samplehold. Also, single +5V supply operation is obtainable with an
input range of +3 to +5V, eliminating the need for an additional
power supply. A 0 to -2V input range is available with ±5V
supply operation.
Another novel feature of the ADC-304 is its user-selectable output coding. The MINV and LlNV pins allow selection of Binary,
Complementary Binary and if external offset circuitry is used
for bipolar inputs, Offset Binary, Two's Complement and Complementary Two's Complement coding.
The ADC-304 is supplied in a 2a-pin dual in-line package and
operates over a -20°C to + 75°C temperature range. Storage
temperature range is from -65°C to + 150°C.

___-=---<=1' ,::::,

Figure 1: ADC-304 Simplified Block Diagram
Table 1. ADC-304 Input/Output Connections
Pin

Function

Pin

Function

1
2
3
4
5
6
7
8
9
10
11
12
13
14

BIT 1 OUT (MSB)
BIT20UT
BIT30UT
BIT 40UT
DIGGND
+ 5V POWER (Vee)
- 5.2V POWER (VEE)
- 5.2V POWER (VEE)
- 5.2V POWER (VEE)
+ 5V POWER (Vee)
DIGGND
lINV
BIT50UT
BIT60UT

15
16
17
18
19
20
21
22
23
24
25
26
27
28

BIT70UT
BIT 8 OUT (LSB)
CLOCK INPUT
VRT
ANAGND
NO CONNECTION
ANAIN
NO CONNECTION
ANAIN
NO CONNECTION
ANAGND
VRs
VRM
MINV

MECHANICAL DIMENSIONS
INCHES
(mm)

g:3

1.44 ~
(366 + 04 )

:~--'=-""'--

L. .~o~I~~)

O..,.J"

,

01
I'~'
(2.54)--- L

0.02 ± 0.004
(0.55 ± 0.1)

--/1-- .• .

0.51 ~ ~:~3

~

0.009 ~ ~::~
(0.25 ~ ~:~5)

m=\ \

lnt" ~,.

(13,2. ..g
. . 3.') •.

0.6
(15.24)

r----- 0.02

.

I.... ~
i'-(0.05 min.)

~.
-~1 O.177~.g~
nn< . nnn~--l -1'
~ gi)
0.05 ± 0.006 _.(1.3 ± 0.15)

\

(4.5
0 13
(3.4 min)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-33

ADC·304
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS (Ta = 25"C)
Supply Vollage Vcc-GND
VEE-GND

V
V

010 +6
010 -6

I npul Voltage
(analog)

Vin
(Dual Power Supply) VEE 10 ANA GND +0.3 V

Inpul Vollage
(reference)

VRT, VRs, VRM
(Dual Power Supply) VEE 10 ANA GND +0.3 V
2.5
V
I VRT-VRs I

Inpul Currenl

IVRM

Inpul Vollage

Digiialinpuis

-3.010 +3.0
-0.510 vee

1. DIG GND pins (5 and 11) and Vee
pins (6 and 10) connect to separate
internal circuits within the ADC-304.
Connect these pins to their respective
PCB patterns.
2. Layout of the analog and digital sections should be separated to reduce
interference from noise. To further
guard against unwanted noise, it is
recommended to bypass, as close as
possible, the voltage supply pins
(6,10) to their respective ground pins
(5,11) with a 1 /JF and a 0.01 /JF ceramic disk capacitor in parallel.

rnA

V

FUNCTIONAL SPECIFICATIONS
Unless otherwise noted, the following specifications apply to
the ADC-304 when used either with a Single or dual power
source. The test conditions are:

3. The input capacitance of the analog
input is much smaller than that of a
typical Flash AID Converter. It is
necessary to use an amplifier with
sufficient bandwidth and driving
power. The analog input pins (21,23)
are separated internally, so they
should be connected together externally. If the ADC-304 is driven with a
low- output impedance amplifier,
parasitic oscillations may occur.

For Single Power Supply Operation:
Vcc(Pins6 + 10) = +5V, DIGGND = OV
VEE (Pins 7, 8 + 9) = OV, VRT (pin 18) = + 5V
VR. (Pin 26) = + 3V, Ta = 25°C
ANA GND (Pins 19 + 25) = + 5V
For Dual Power Supply Operation:
Vee (Pins 6 + 10) = +5V, DIG GND (Pins 5 + 11) = OV
ANA GND = OV, VEE = -5V
VRT (Pin 18) = OV, VR. (Pin 26) = -2V
Ta = 25°C
DESCRIPTION
Inputs
Analog
Input Range ...............
Input Capacitance' ..........
Input Bias Current2 . . . . . . . . . .
Offset Voltage:
(VAT) ...................
(VRs) ...................
Digital
Logic Levels:
Logic "1" .... ............
Logic "0" ................
Logic Input Currents3 :
Logic "1" ................
Logic "0" ................

TYP.

MIN.

VRs

MAX.

UNITS

-

30
50

VRT
35
100

V
pF
/J A

8
0

13
5

19
11

mV
mV

2.0

-

-

0.8

V
V

-100
-0.32

0
-0.5

/J A
mA

-

-

Outputs
Resolution
Output Coding

Logic levels:
Logic "1" ........ ........
Logic "0" ................
Logic Level Loading:
Logic "1" ............ ....
Logic "0" ............ ....
Output Data Delay
(TDLH) ..................
(TDHL) ..................

1-34

8
Straight Binary
Complementary Binary
2's Complement
Complementary 2's
Complement
2.7

3.4

-

-500

25
26

-

0.5

-

Bits

V
V

3

/J A
mA

30
35

nSec.
nSec.

These parasitic oscillations can be
prevented by introducing a small
resistance of 2 to 10Q between the
amplifier output and the ADC-304's
AID input. This resistance must be of
very low value of inductance at high
frequencies.
Note that each of the analog input
pins are divided in this manner with
these resistances. Connect the driving amplifier as close as possible to
the AID input of the ADC-304.
4. The voltage between VRT (pin 18)
and VRs (pin 26) is equivalent to the
dynamic range of the analog input.
Bypass VRs to ANA GND (pins 19
and 25) by means of a 1 /J F and 0.01
/J F capacitor in parallel. To balance
the characteristics of the ADC-304 at
high frequencies, bypass VRM (pin
27) with a 0.01/J F capacitor to ANA
GND (pins 19 and 25).
Also, VRM (pin 27) can be used as a
trimming pin for more precise linearity compensation. A stable voltage
source with a potential equal to - FSR
and a 1 KQ potentiometer can be connected to VRM (pin 27) as shown in
Figure 3 for this purpose.
5. Separate the clock input, CLK (pin 17),
from other leads as much as possible,
observing proper EMI and RFI wiring
techniques. This will reduce the
inductive pick-up of this lead from
interfering with the "clean'" operation
of the ADC-304.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-304
Performance
Conversion Rate' ...........
Non-Linearity ..............
Differential Non-Linearity .....
Differential Gain Errors .......
Differential Phase Errors .... ..
Aperture Delay ..............
Aperture Jitter ..............
Clock pulse width: Tpw1 .....
TpwO .....
Reference

MIN.
20

5
35
10

Reference Pin Current .......
Reference Resistance
(VRTto VRB)
Reference Input (Dual Supply)
(VRT) ...................
(VRB) ...................
Power Supply Requirements
Single Power Supply
Supply voltage
(Vee) ...................
(VEE) ...................
Supply Current:
(ICC + lEE) ..............
Power Dissipation ...........
Dual Power Supply
Supply Voltage:
(Vee) ...................
(VEE) ...................
Supply Current
(ICC) ...................
(lEE) ...................
Power Dissipation ...........
Physical/Environmental
Operating Temperature .......
Storage Temperature ........

-0.1
-1.8

MAX.

TYP.

-

±1/2
±1/2
1.5
0.5
9

-

7
30

-

-

15
130

-

mA
ohms

0
-2.0

+0.1
-2.2

V
V

-

18

UNITS
MHz
LSB
LSB
%
Degrees
nSec.
pSec.
nSec.
nSec.

5.25

0

-

V
V

71
360

88
442

mA
mW

4.75
-4.75

5.0
-5.2

5.25
-5.5

V
V

-

10
62
390

14
75
440.

mA
mA
mW

-20
-55

-

+75
+150

°C
°C

4.75

-

TECHNICAL NOTES (CONT.)
6. The analog input signal is sampled on
the positive-going edge of ClK. Corresponding digital data appears at the
output on the negative-going edge of
theCLKpulseafterasmalldelayof35
nSec. maximum (TDlH, TDHl).
Refer to the Timing diagram, Figure 4,
for more information.
7. Connect all free pins to ANA GND
(pins 19 and 25) to reduce unwanted
noise.
The analog input range is equal to a
2V spread. The voltage on VRT-VRB
will equal 2V. The connection of VRT
and ANA GND is 2V higher than VRB.
Whether using a single or dual power
supply, the analog input will range
from the value of VRT to VRB. If VRT
equals +5V, then VRB will equal +3V
and the analog input range will be
from +5 to +3V.
SINGLE SUPPLY
OPERATION

ADC-304

DUAL SUPPLY
OPERATION

ADC-304

Footnotes:
1. Vin = 4V + 0.07 VRMS for single power supply
Vin = -1V + 0.07 VRMS for dual power supply
2. Vin = 4V for single power supply
Vin = -1V for dual power supply
3. Logic "1''' = 2.7V
Logic "0'" = 0.5V
4. fin = 1 KHz, ramp
5. NTSC 40 IRE-modulated ramp, Fe = 14.3 MSPS

lK

Figure 3: Improving Linearity
Compensation

DATEL, Ine. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-35

•
:i

ADC·304
Analog Input

Clock

I

Comparator
Output

6-Bit Latch Output

DataOutpuI
Bits '-8

~
:I
:

X

E
I

1

m
1

I

:

I

I

I

I

N-' Data Valid

:X

: N Data Valid :

t-t--

--fTDLH
----jTDHL

I

I"

I

I

I I

1
I •
I I

35 nsec

1

X:

: N + , Data Valid

I
I
I 35 nsecI II

I"

,.

I

I

I

Figure 4: ADC·304 Timing Diagram
THEORY OF OPERATION
The ADC-304 consists of 4 sections: the resistor string, the
comparator latches, the encoder, and the latchable output
buffer. Refer to the block diagram (Figure 1) and timing diagram
(Figure 4) as needed.

encoder, and the Exclusive-OR gates to the input of the output
latch. The output latch, with the clock in a high state, has the
previous conversion latched. The clock is required to be high
for a minimum of 35 nSec.

The reference resistor string consists of 256 equal value resistors with 256 internal taps and 3 external taps. The external taps
are represented as VRT, VRs and VRM. VRT is the top of the
resistor string, VRM is the mid pOint of the resistor string and
VRs is the bottom of the resistor string. VRM can be used as
a trimming pin for an improved linearity specification. See
Figure 3 for more information.

Upon the clock going low, the latch shown on the block diagram
with the 256 to 24 bit encoder is latched. This allows the comparators to be in the sampling mode in preparation for the next
conversion. The now latched and encoded data word proceeds
into the output latch which became enabled with the clock
going low (10 nSec. minimum required). The data will be ready
at the output 35 nSec. maximum after the negative edge of the
clock.

The 256 internal taps feed 256 comparator inputs. The reference voltage is applied to the +(positive) input side of the 256
clocked comparators. The analog input is applied to the
- (negative) input of the comparators. The comparator section
consists of 256 comparators which compare the analog input
signal to the voltage at the reference ladder's resistor taps for
each comparator. All the comparators' clock (ClK) inputs are
tied together so they are clocked simultaneously.
The comparison between the reference ladder taps and input
voltage is made on the positive going edge of the clock. The
latched comparator output then goes to the latch/256-to-24 bit
encoder. Each of the four groups of 64 comparators are
encoded once into 6-bit data. The four 6-bit data groups are
then encoded to the 8-bit output data word. This latch is enabled when ClK is high and the latched comparator outputs proceed through the 256-to-24-bit encoder, the 24-bit-to-8-bit

Output coding of Binary, Complementary Binary, and if external offset circuitry is used, Offset Binary, Two's Complement
and Complementary Two's Complement is selectable using the
MINV and LlNV pins. The most significant bit is Exclusive ORed with an external pin labeled MINV.
This pin allows for inversion of the MSB, simply by applying the
correct logic level to MINV. The remaining 7 bits are exclusive
OR-ed with an external pin labeled LlNV. This pin allow~ for
inversion of the 7 lSB's, by applying the correct logic to LlNV.
Both MINV and LlNV have TTL-compatible inputs. Refer to
Tables 2 and 3 for appropriate connections.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388fFAX (508) 339-6356

ADC·304
APPLICATION CIRCUITS

(MS8)

(MS6)

Analog input

Analog input
o to -2v

+5 to +3V
(TTL level)

(TTL level)

l

(TTL level)

ILSB)

BI18~---1~-+--------~

Figure 5: Connections for +5V

Figure 6: Connections for ±5V

Power Supply Operation

Power Supply Operation

CLI( IN

OUlpul CO""OI

""

""

1880

80'

1170

ii

13

~o

.0 •

30.

'"

ZO,

<20

'"

.0 "

ONO

'02

'"

74LS314 isalllO available

fo. 15 MSP$ Or Ie" conv8'$;Cm rate

~

Analog GND

~

Oi9'taIGND

ca'amicCh,pcapaci!orOm

'GJ ~
DG=

.,r

AU'8!liSlOrv8luesarainohmsandcapacilancevaluas
8,e in mK:rola,ads unlessolhe ....... sa noted

Figure 7: Typical Circuitry for +5Vand ±12V Power Supply Operation

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-37

ADC·304
Table 2. Output Coding for + 5V Power Supply Operation
(+5 to +3V Signal Input)
Straight
Binary

0
0

0
1

1
0

1

LlNV
+4.9922V
+4.7S00V
+4.SOOOV
+4.0000V
+3.5000V
+3.2S00V
+3.0078V
+3.0000V

11111111
11011111
10111111
01111111
00111111
00011111
00000001
00000000

10000000
10100000
11000000
00000000
01000000
00100000
01111110
01111111

01111111
01011111
00111111
11111111
10111111
11011111
10000001
10000000

00000000
00100000
01000000
10000000
11000000
11100000
11111110
11111111

MINV

Unipolar
Scale
+FS -1 LSB
+'/aFS
+'I4FS
+'/2 FS
+'14 FS
+'/aFS
+1lSB
Zero

Complement 2'$
Complement
2's
Complement
Complement
Binary

1

Table 3. Output Coding for ± 5V Power Supply Operation
(0 to - 2V Signal Input)
Straight
Binary

0
0

0

1

Lin. V

1

0

1

OV
-7.813 mV
-2S0.00 mV
-SOO.OO mV
-1.0V
-1.SV
-1.7SV
-1.9922V

11111111
11111110
11011111
10111111
01111111
00111111
00011111
00000000

10000000
10000001
10100000
11000000
00000000
01000000
00100000
01111111

01111111
01111110
01011111
00111111
11111111
10111111
11011111
10000000

00000000
00000000
00100000
01000000
10000000
11000000
11100000
11111111

Min. V

Unipolar
Scale
0
-1lSB
-'/aFS
-'14 FS
_'/2 FS
_3,4 FS
-'/aFS
-FS+llSB

Complement 2'8
2'8
Complement
Complement
Complement
Binary
1

'"

1.ll<

GHO

102

C9ramic Chip capacitor 0.Q1

74LS374is alsoavailablo
for 15 MSPS or lesscooyersion rat\>

+M'+

~

To be ...loc1ed

AnalogGND
Digital GNO

Figure 8: Typical Circuitry for ±5V and ±12V Power Supply Operation

ORDERING INFORMATION
MODEL

DESCRIPTION

ADC-304

a-bit, 20 MHZ, Low-power, flash AID
For higher reliability versions, contact the factory

1·38

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

ADC-310
1O-Bit Video
AID Converter
FEATURES

•
•
•
•
•
•

10-Bit resolution
20 MHz conversion rate
Very low power 360 mW
Buffered output
Eel-compatible
Input bandwidth 10 MHz

+l.5V

-5V

AGRND

DGRND

GENERAL DESCRIPTION
The ADC-310 is a bipolar monolithic 10bit video analog to digital converter capable
of digitizing analog input signals at conversion rates up to 20 MHz minimum with
a typical power consumption of only 360
mW.

Output
Buffer

A serial/parallel technique is used to obtain
the high conversion speed using dual power
source of +1.6 volts and -s.o volts.
Output
Bufier

Miltrox
C,rcUlt

The analog input range, with -2V reference,
is OV to -2V and digital inputs and outputs
are ECL compatible with outputs buffered.

3

The converter is designed to operate with
an external sample and hold (SHM-40, or
similar) together with external clock and
reference source.

Bill 0 IlSB)

Ok

The ADC-31 0 is packaged in a 28 pin DIP
and operates over temperature range
-20°C to +7SoC.
Clock

Clock

APPLICATIONS

•
•
•
•
•
•
•
•

High speed data acquisition
Radar pulse analysis
TV video encoding
High energy physics
Transient analysis
Medical electronics
Fluid flow analysis
Sonar systems

MECHANICAL DIMENSIONS

INPUT/OUTPUT CONNECTIONS

Un~:lmml

'"

10,3)

~

11-1.'00'

C:i::LJ} ~~~.~T"'"
!

11-

t

r-

13. [2,54 m 33,02]
0100-1.300

,

eLK INPUT

2

CLK1NPUT

3

BIT IOll$8)

26

INTERNAL CONNECTION~ LEAVE OPEN

24

+1,5VOLTSUPPlV

23

-2.0VOLTREFERENCESUPPlV

12,16\0_085

(0,76)0.030

,~=r

'''" II~ ~~

M
'i11~4'191

ZO

VREF ADJUST 1

19

OVOlTREFERENCESUPPlV

18

INTERNAL CONNECTION- LEAVE OPeN

12

BIT 1 (MSR)

17

ANALOG INPUT

13

ANALOG GROUND

16

ANAlOG INPUT

11.271-i

_~~~~

-{

~165

(7,62)0.300

15 • -5.2 VOlT POWER SUPPLY

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

1-39

ADC-310
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS
Supply Voltage Vs ........ . o to -7.0V
Supply Voltage Vcc ....... . o to +2.5V
Analog Input Voltage ..... . Vs to 0.3V
Reference Voltage ........ . Vs to 0.3V
Digital Output Current .... . Oto -20 rnA
Power Dissipation ........ . 1.23Wal\s
Storage Temperature ..... . -55°C to +150°C
Operating Temperature ... . -20°C to +75°C

1. Analog input signals must be 'held' by an external sample/hold
e.g. DATEl SHM-40, with careful attention being paid to the
timing relationship between the sample/hold transition of the
sample/hold amplifier and the positive transition of the clock
pulse - see timing diagram.
2. Analog input, pins 16 and 17, must be linked externally. The
input bias current is 15 J.l..A typical.

FUNCTIONAL SPECIFICATIONS.
Typical at +25°C, Vs = -5.2 V dc, Vee = +1.6, Vref = -2.0 V de

unless otherwise stated.

4. The reference input should be decoupled using 0.1 pF capacitor located as close as possible to pin 23. It is also recommended that the external connections to the resistor network,
pins 20, 21 and 22, are also decoupled using 0.1 "F capacitors whether they are used or not.

PERFORMANCE
Resolution ................
Conversion Rate (Min) .....
Integral Non-Linearity ......
Differential Non-Linearity ..
Input Bandwidth .. ........
INPUTS
Input VOlta~e .......
Input Bias urrent ...
Input Capacitance.

10 Bits
20 MHz
± 1.75 LSB
±1.75LSB
10MHz

MIN.

TYP.

MAX.

UNITS

0

-

-2.0
80

V
!LA
pF

-14
-0.51
V
-1.51
-2.10

rnA
V

-

40
230

-

REFERENCE
Current. ... ...... . · .
VRI .
....
VR2 .. . . . . . . . . ..... .
VR3 .... . .. ........
VREF. .. . ....

-

-0.49
-0.99
-1.49
-1.90

-12.5
-0.5
-1.0
-1.5
-2.0

V
V

CLOCK
Bias Current. ...... .

5

-

8

J.l..A

OUTPUT
Digital (high) .........
Digital (low) ..........

-

-

-1.5

-

V
V

-

55
17

80
25

rnA
rnA

-0.9

3. The -2.0 volt reference voltage is connected between pins 23
(-2V) and pin 19 (analog ground). The 'R' value between pins
19 and 23 is 200 Ohms (typical).

5. For most applications, the ADC-310 accuracy will be more
than sufficient. However, it is possible that some improvement
may be achieved at the % 'full-scale', V2 'full-scale', and the %
'full-scale' pOints by connecting external resistors from pins 20,
21, and 22 to analog ground pin 19, or to VREF (pin 23).
6. The printed circuit board should be laid out to have substantial
analog and digital ground planes. The planes should be connected at one pOint only - usually power common and as
close to the source as possible.
7.

Internal pull down resistors (10K Ohms typ.) to the digital output
terminals are provided. However, to boost the transition, external resistors greater than 3K Ohms can be added .

8. An external complementary ECl signal source is required to
drive the clock input terminals pins 1 and 2.
9. The -5.0V power supply and +1.6V power should be decoupled
using 3.3 uF tantalum and 0.022 uF ceramic capacitors. Mount
these components as close as possible to pins 15 and 24 .
10. Under no circumstances must external circuits be connected to
pin 18 and pins 25 to 28. These five terminals must be left
open circuit.

POWER
-5.0V ±0.25V ..... · .
+ 1.6V to 2.1 ...... · .

1-40.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

ADC-310

TIMING DIAGRAM
v?

Sample N+1

Sampling Pulse

Sample N + 1

Sample N+2

Sample N

Sample/Hold Output

Clk
Clock

T,

T,

N
Data Valid

riMING DIAGRAM NOTES
The timing must be set such that the negative transition of the
clock (clk) occurs time T, after the sample pulse, and the time T,
being greater than sample/hold aperture delay and settling time

T, > TA
,

The first half cycle of clock must not be less than 22 nsec.
T2

2:

22 nsec.

4. The second half cycle of the clock must not be less than 20
nsec.
T4

",

20 nsec.

5. Data becomes valid in not less than 15 nsec. after the first clock
cycle.
T5 ", 15 nsec.

The next sample/hold pulse must not occur less than 2 nsec.
after the positive transition of the first half cycle of the clock.
T3 '" 2 nsec.

;.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6~

".

ADC-310

CONNECTION AND APPLICATION

f1,

Ground

+1.6V

-5.2V

A R

2 VOLT

1---_T~

REFERENCE

+ 1.6V

~~~ 8~~

-5.2V

23 VREFS

-±:-

A

A R

A R

A R

* CAN

BE ADDED TO BOOST
TRANSITION A > 3.3K OHMS

R'"

~-++++-H-+++---111-~+++-H-+++---_

12

BIT 1 (MSB)

10

BIT 3

9
8

81T4
BIT5

'lI-'F
~

61T2

7

BIT 6

6

BIT7

ADC-310

"

~"-------l

22 VREF ADJ 3

F

21 VREF ADJ 2

·"1

01

...----1

f·li-'F

r:-:--::-

~.l ... F

T
~'--'--"""~

r

1r------4-l
SAMPLE/HOLD

SHM-40

5

BIT8

4

BIT9

3

BIT 10 ILSB)

20 VREF ADJ 1

27
28 ]

19 VREFr

26

16 ANA IN

25

17 ANA IN

18
elK

I

I

NO CONNECTION

eLK

20 MHz CLOCK &
TIMING CIRCUIT

I

DIGITAL OUTPUT CODES
INPUT VOLTAGE

DIGITAL OUTPUT CODE

MSB

O.OOOOV
VREFT
-0.0020V

1
1

1
1

-0.9990V
-1.0010V

a

1

a a a a

-1.9980V
VREFB -2.0000V

1

1
1

1

1
1

1

1
1

1

a a a a a
a a a a a

1
1

1
1

LSB
1
1

1
1

1

a

a a a a a
1

1

1

1

1

a a a a 1
a a a a a

ORDERING INFORMATION
MODEL NO.

OPERATING
TEMPERATURE
RANGE

ADC-310

-20°C to + 75°C

NOTE: For units with high-reliability processing, contact DATEL.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-500, ADC-505
12-Bit, Ultra-fast, Low-power
AID Converters
FEATURES
• 12-Bit resolution
• 500 Nanosecond maximum
conversion time
• Low-power, 1.6W
• Small initial errors
• Three-state output buffers
• - 55°C to + 125 °C operation
• Small 32-pin DIP

GENERAL DESCRIPTION
DATEL's ADC-500 and ADC·505 reflect
the ultimate in state·of-the·art analog signal conversion technology. The ADC-500
boasts a remarkable conversion speed of
500 nanoseconds, along with a low-power
consumption of 1.6 watts.
DATEL's ADC-500 and ADC-505 are
12-bit analog-to-digital converters which
have small initial errors and can also provide adjustment capability for system errors. Both models have identical specifications except for conversion times. The
ADC-505 has a maximum conversion time
of 550 nanoseconds while the ultra-fast
ADC-500 accomplishes a 12-bit conversion in less than or equal to 500 nanoseconds. Figure 1 is a simplified block dia·
gram applicable to both devices.
Manufactured using thick-film and thin-film
hybrid technology, these converters'
remarkable performances are based upon
a digitally·corrected subranging architecture. DATEL further enhances this technology by using a proprietary custom chip
and unique laser trimming schemes. The
ADC-500 and ADC-505 are packaged in a
32-pin ceramic DIP and consume 1.6
watts.
The ADC-500 and ADC-505 feature three
pin-programmable input ranges: 0 to
+ 10V, 0 to + 20V, and ± 10V dc. The input impedance is specified at 1. 75K
minimum for unipolar ranges and 3.75K
minimum for the bipolar range, reducing
stringent drive requirements. Other specifications include no missing codes over
temperature, a maximum gain tempco of
± 35 ppm/oC and a maximum differential
linearity tempco of ± 2.5 ppm/oC.
All digital inputs and three-state outputs
are TTL- and CMOS-compatible. Output
coding can be in straight binary/offset
binary or complementary binary/complementary offset binary by using the COMP
BIN pin. An overflow pin indicates when inputs are below or above the normal fullscale range.

Figure 1. ADC-500, ADC-505 Simplified Block Diagram

INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (mm)

~ 1101 MAX -----.J

r--I
I~

0150 (3,8) MIN

(28.01-1

.L

~

I

0.190 (4.9) MAX

0,010

ITt

x 0.Q18 Kovar

116

17

T~1
{43.51

BOTTOM
VIEW

1
I

32

11

f.--O.900

(22,9)

'1,"'""j

at 0 100 each
(251

..

--0

NOTE: Pins have 0.025 Inch, ± 0.01
stand off from case

0.100
{2.51

PIN

SIGNAL NAME

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

+1DV REF
RANGE
INPUT HIGH
INPUT LOW
OFFSET ADJUST
NO CONNECTION
COMP BIN
OVERFLOW
ENABLE (6 101
ENABLE (1·5 0 F I
+5V
DIGITAL GROUND
+15V

-15V
-5V
ANALOG GROUND
S/H CONTROL
EOC
BIT 12 (lSB)
BIT 11
BIT 10
BIT 9
BIT8
BIT 7
BIT6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1 (MSBI
START CONVERT
GAIN ADJUST

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

1·43

ACC-SOO, ACC-SOS
Another novel feature of the ADC-500 is the provision of a Sample/Hold control pin for applications where a sample-hold is used in
conjunction with the ADC-500. This feature allows the sample-andhold device to go back into the sample mode a minimum of 30
nanoseconds before the conversion is complete, improving the
overall conversion rate of the system.
Power required for both models is ± 15V dc and ± 5V dc. Models
are available in the commercial O°C to + 70°C, and military - 55°C
to + 125°C operating temperature range. Typical applications include spectrum, transient, vibration, and waveform analysis. These
devices are also ideally suited for radar, sonar and video digitization,
medical instrumentation, and high-speed data acquisition systems.
For information on versions with high reliability screening, contact
the factory.

ABSOLUTE MAXIMUM RATINGS
Parameters
MINIMUM
+ 1SV Supply (Pin 13) ...
0
-1SV Supply (Pin 14) ...
0
+ SV Supply (Pin 11) .... -0.5
- SV Supply (Pin 1S) .... +0.5
Di~ital Inputs
Pins 7,9, 10 & 31) ... -0.3
Analog Input (Pin 3) ....
-15
Lead temp. (10 sec) ....

MAXIMUM
+18
-18
+7
-7

UNITS
Volts dc
Volts dc
Volts dc
Volts dc

+6
+15
300

Volts dc
Volts dc
°C

FUNCTIONAL SPECIFICATIONS
Apply over the operating temperature range and over the operating
power supply range unless otherwise specified.
DESCRIPTION

MIN.

TYP.

MAX.

UNITS

INPUTS
Input Voltage Range ... (See Tech. Note 9)

--

o to + 10
o to +20
±10

-

-

Logic Levels: Logic 1 .. 2.0
Logic 0 .. Logic Loading: Logic 1
Logic 0 -

-

-

-

-

0.8
2.5
-100

Volts dc
Volts dc
Volts dc
Volts dc
Volts dc
p.A
p.A

OUTPUTS
Output Coding:
(Pin 7 High) ........
(Pin7Low) ........
Logic Levels: Logic 1 .. 2.4
Logic 0 .. Logic Loading: Logic 1 Logic 0 Internal Reference:
Voltage, + 2SoC .... 9.98
Drift .............. Extemal Current .... -

straight binary/offset binary
complementary binary
complementary offset binary
Volts dc
0.4
Volts dc
-160
p.A
mA
6.4
-

±5

-

10.02
±30
1.5

Volts dc
ppm/DC
mA

1.44

DESCRIPTION
Unipolar Zero Error,
+2S·C .............
Unipolar Zero Tempco ..
Bipolar Zero Error,
+2S·C .............
Bipolar Zero Tempco ...
Bipolar Offset Error,
+2S0C .............
Bipolar Offset Error
Tempco ............
Gain Error, + 2S·C .....
Gain Tempco ..........
Conversion Times:
ADC-SOO
+2S·C ...........
O·C to + 70·C .....
-SSoC to + 12SoC
ADC-50S
+2SoC ...........
O·C to + 70·C .....
- SSOC to + 12S·C ..
No Missing Codes
(12 Bits): ............

MIN.

TYP.

MAX.

UNITS

-

±1
±13

±3
±25

LSB
ppm/DC

--

±1
±13

±3
±25

LSB
ppm/DC

-

±2

±5

LSB

-

± 17.5
±2
± 17.5

±35
±5
±35

ppm/DC
LSB
ppm/DC

500
540
560
550
590
620

nsec.
nsec.
nsec.
nsec.
nsec.
nsec.

-

-

-

-

-

Over the Operating Temp. Range

POWER SUPPLY REQUIREMENTS
Power Supply Range:
+ 1SV dc Supply .....
-1SV dc Supply .....
+ SV dc Supply ......
- SV dc Supply ......
Power Supply Current:
+ 1SV Supply ........
-1SV Supply ........
+SVSupply· ........
-5VSupply .........
Power Dissipation ......
Power Supply Rejection.

+ 14.25
-14.25
+4.75
-4.75

-

-

+15
-15
+5
-5

+ 15.75
-15.75
+5.25
-5.25

+23
-11
+55
-175
1.6

+30
-15
+90
-210
1.8
0.01

-

Volts
Volts
Volts
Volts

dc
dc
dc
dc

mA
mA
mA
mA
Watts
%FSRI%V

PHYSICAUENVIRONMENT AL
Operating Temp. Range:
-BMC .............
0
+70
-BMM ............. -55
+125
Storage Temperature
Range .............. -65
+150
Package Type ......... 32-pin hermetic sealed, ceramic
Pins ................. 0.010 x 0.Q18 inch Kovar
Weight ............... 0.42 ounces (12) grams

°C
°C
°C
DIP

• + 5V power usage at 1TIL logic loading per data output bit.

TECHNICAL NOTES

1. Use external potentiometers to remove system errors or the

PERFORMANCE
Integral Nonlinearity:
+2S·C ............
o·c to + 70·C ......
-SS·Cto + 12S·C ..
Integral Nonlin. Tempco.
Differential Nonlinearity
+2SoC ............
O°Cto +70°C ......
-SS·Cto +12S·C ..
Differential Nonlin.
Tempco ...........
Full-Scale Absol.
Accuracy:
+2S·C ............
O·Cto + 70°C ......
-SS·Cto + 12S·C ..

PERFORMANCE (cont.)

-

-

-

±3

±0.0125 %FSR ±'h LSB
±0.0125 %FSR ±'h LSB
±0.0125 %FSR ±3 LSB
ppm/DC
±8

-

-

±0.0125 %FSR ±'h LSB
±0.0125 %FSR ±'h LSB
±0.0125 %FSR ±1 LSB

-

-

±2.5

ppm/DC

-

±3
±4
±8

±8
±14
±29

LSB
LSB
LSB

-

-

-

-

small initial errors to zero. Use a 20K trimming potentiometer for
gain adjustment with the wiper tied to pin 32 (ground pin 32 for
operation without adjustments). Use a 20K trimming potentiometer with the wiper tied to pin 5 for zer%ffset adjustment
(leave pin 5 open for operation without adjustment).
2. Rated performance requires using good high frequency circuit
board layout techniques. The analog and digital grounds are not
connected internally. Avoid ground-related problems by connecting the digital and analog grounds to one point, the ground
plane beneath the converter (versus at the power supply terminals when the power supplies are located some distance from
the ground plane) .. Due to the inductance and resistance of the
power supply return paths, return the analog" and digital ground
separately to the power supplies. This prevents contamination
of the analog ground by noisy digital ground currents.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194iTEL (508) 339-3000iTLX 174388/FAX (508) 339-6356

ADC-500, ADC-505
3. Bypass all the analog and digital supplies and the + 10V reference (pin 1) to ground with a 4.7 p.F, 25V tantalum electrolytic
capacitor in parallel with a 0.1 p.F ceramic capacitor. Bypass the
+ 10V reference (pin 1) to analog ground (pin 16). The -5V dc
supply is treated as an analog supply and analog ground (pin 16)
should be treated as its return path for decoupling purposes.
4. Obtain straight binary/offset binary output coding by tieing
COMP BIN (pin 7) to + 5V dc or leaving it open. The device has
an internal pull-up resistor on this pin. To obtain complementary
binary or complementary offset binary output coding, tie the
COMP BIN pin to ground. The COMP BIN signal is compatible
to CMOSITTL logic levels for those users deSiring logic control
of this function.
5. An overflow signal, pin 8, indicates when analog input signals
are below or above the desired full-scale range. The overflow
pin also has a three-state output and is enabled by pin 10
(Enable bits 1-5 & 0 .F.).

8. Over temperature, input capacitance is 50 pF maximum and input impedance is 1. 75K minimum (2.5K typical) for unipolar and
3.75K minimum (5K typical) for bipolar. These values are guaranteed by design.
9. Requirements for ± 2.5V inputs can be satisfied using DATEL's
AM-1435 amplifier in front of the SHM-45/ADC-500 configuration, shown in Figure 4, at the appropriate gain. The SHM-45's
gain of 2 mode allows 0 to + 5V or ± 5V input ranges.

TIMING
Figure 2 shows the relationship between the various input signals.
The timing cited in Table 1 applies over the operating temperature
range and over the operating power supply range. These times are
guaranteed by design.

TABLE 1_ SIGNAL TIMING SUMMARY

6. The Sample/Hold control signal, pin 17, goes low following the
rising edge of a START CONVERT pulse and high 30 nanoseconds minimum before EOC goes low. This indicates that the converter can accept a new analog input.
7. The drive requirements of the ADC-500/505 may be satisfied
with a wide-bandwidth, low output impedance input source. Applications of these converters that require the use of a samplehold may be satisfied by using DATEL's model SHM-45. Using
this device with multiplexers or for test purposes will require an
input buffer.

""'----=

!
i'-...:

,,

50 nsec. minimum
150 nsec. minimum

Analog Input Settling Time
Start Convert Low to EOC
High Propagation Delay

35 nsec. maximum

Start Convert low to Previous
Output Data Invalid

350 nsec. minimum

Data Valid Before EOC
Goes Low

25 nsec. minimum

Enable to Output Oats Valid
Propagation Delay

10 nsec. maximum

NOTE NOT DRAWN TO SCALE

,
:

~150nSec
-:

DURATION IN NANOSECONDS

--------~,r---------------------------------------------

~

S~~~~I:G

UNE
Start Convert (AID)

MINIMUM

I

------'1-,--------------------------------------------I

TIME

I

,

105 nSec MINIMUM (when used with SHM-45)

,

-+1,

!
I

1

--1:

f+
':: - !

1-,

I,

: :

I I

,

I'

i
:
1- 1-----------:

200nSec ACOUISITIONTIME

I

-------+-': ---1
I I
Ii-:
L
i '-------+;-11_:1----"

,

, 1+

:

S'H

--,

I

lDOnSec HOLD MODE SETTLING TIME

I

I

::

:
EOe

I

,,

T. MAXIMUM

------------~-ll

L

20nSecMINIMUM
3SnS",c MAXIMUM

10nSec MINIMUM

I

25 nSec MAXIMUM

_I

L

30nSec.

1-

MINIMUM

~i-!----------+'...,IL;-!__________________________________~I-------.l----,
I ~-, 1---M@XJ
1---___________

OUTPUT DATA

350nSec

MINIMUM

DATA N-1 VALID

ENABLED DATA N-t VALID
(BITS t-S.OF)

ENABLED DATA N-1 VALID
(BITS 6-12)

F

ENABLED DATA N
VALID

10nSec
MAXIMUM

I

10 "Sec
MAXIMUM

I

_

1

I:'NABLED DATA N
VALID

r-

TEMPERATURE: +25 "C 0 10 +70 "C -5510 +125 "C
ADC-SOO
CONVERSION
TIME(T1)

500 nSec

540 nSec

560 nSec

ADC-505
CONVERSION
TIME(T1)

550nSec

590 nSec

620 nSee

'NVAUD DATA

~

Figure 2. ADC-500/505 and SHM-45 Timing Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-45

•

I

ADC-500, ADC-505
TABLE 4. OUTPUT CODING FOR UNIPOLAR
OPERATION

CALIBRATION PROCEDURE
Removal of system errors or the small initial errors is accomplished
as follows:
1. Connect the converter per Figure 3 and Table 2 for the appropriate full-scale range (FSR). Apply a pulse of 50 nanoseconds
minimum to the START CONVERT input (pin 31) at a rate of 500
kHz. This rate chosen to reduce flicker if LED's are used on the
outputs for calibration purposes.
2. Zero Adjustments
Apply a precision voltage reference source between the analog
input (pin 3) and ground (pin 16). Adjust the output of the reference source per Tables 3a and 3b for the unipolar zero adjustment ( + V2 LSB) or the bipolar zero adjustmenj{zerQ + '12 LSB)
for the appropriateFSR. For unipolar, adjust the :zero trimming
potentiometer so that the output code mckers equally between
0000 0000 0000 and 0000 0000 0001 with the COMP BIN
(pin 7) tied high or between 1111 1111 1111 and 1111 1111
1110 with the COMP BIN tied low.

UNIPOLAR
SCALE

INPUT RANGES,
VOLTS de

OUTPUT CODING
STRAIGHT BINARY

+FS -1 LSB

Oto +10V

010 +20V

MSB

+9.9976V

+ 19.9951V

1111

COMP. BINARY

LSB

MSB

1111

1111

0000 0000 0000

LSB

T,j,FS

+8.7500V

+ 17.S00V

1110

0000

0000

0001

1111

%FS

+7.S000Y

+lS.000V

1100

0000

0000

0011

1111

1111

112 FS

+S.OOOOV

+10.000V

1000

0000

0000

0111

1111

1111

V4 FS

+2.5000V

+S.OOOOV

0100

0000

0000

1011

1111

1111

'AoFS

+ 1.2S00V

+2.S000V

0010

0000

0000

1101

1111

1111

1 LSB

+O.OO24V

+O.0049V

0000

0000

0001

1111

1111

1110

O.OOOOY

O.OOOOV

0000

0000

0000

1111

1111

1111

0

1111

For bipolar operation, adjust the potentiometer such that the
code flickers equally between 100000000000 and 10000000
0001 with COMP BIN tied high or between 0111 1111 1111 and
0111 1111 1110 with COMP BIN tied low.
3. Full-Scale Adjustment
Set the output of the voltage reference used in step 2 to the
value shown in Table 3a or 3b for the unipolar or bipolar gain adjustment ( + FS -1'12 LSB) for the appropriate FSR. Adjust the
gain trimming potentiometer so that the output code flickers
equally between 1111 1111 1110 and 1111 1111 1111 for
COMP BIN (pin 7) tied high or between 0000 0000 0001 and
0000 0000 0000 for COMP BIN tied low.

4. To confirm proper operation of the device, vary the precision reference voltage source to obtain the output coding listed in
Tables 4 and 5.

TABLE 2. INPUT CONNECTIONS
INPUT VOLTAGE RANGE

INPUT PIN

Oto+l0Vdc

3

CONNECT PIN 2 (RANGE) TO PIN:

3

Oto +20Vdc

3

16

± lOV de

3

1

TABLE 3a. ZERO AND GAIN ADJUST FOR UNIPOLAR
USE
UNIPOLAR FSR

ZERO ADJUST

+112 LSB

GAIN ADJUST
+FS -1% LSB

Oto +10Vdc

+1.22 mV

+9.9963V de

a to +20V de

+2.44 mV

+ 19.9927V de

TABLE 3b. ZERO AND GAIN ADJUST FOR BIPOLAR
USE

1-46

BIPOLAR FSR

ZERO ADJUST
ZERO +10 LSB

GAIN ADJUST
+FS -1% LSB

±10V de

+2.44 mV

+9.9927V de

Figure 3. ADC-500/505 Calibration Circuit

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-500, ADC-505
TABLE S. OUTPUT CODING FOR BIPOLAR
OPERATION
BIPOLAR
SCALE

INPUT
RANGE

OUTPUT CODING
OFFSET BINARY

±'0V de

MSB

+FS -1 LSB

+9.99S1V

1111

+¥.t FS

+ 7.S000V

1110

+ V:! FS

+S.OOOOV

0

O.OOOOV

-1f2 FS

COMP. OFFSET BINARY

LSB

MSB

1111

1111

0000

0000

0000

LSB

0000

0000

0001

1111

1111

1100

0000

0000

0011

1111

1111

1000

0000

0000

0111

1111

1111

-S.OOOOV

0100

0000

0000

1011

1111

1111

-'14 FS

-7.S000V

0010

0000

0000

1101

1111

1111

-FS +1 LSB

-9.99S1V

0000

0000

0001

1111

1111

1110

-FS

-lO.OODV

0000

0000

0000

1111

1111

1111

THEORY OF OPERATION (ADC-SOO AND SHM-4S)
This theory of operation describes the ADC-500's operation in conjunction with DATEL's SHM-45. The SHM-45 sample-and-hold
device captures fast signals for an ADC-500 to then digitize. Figure
4 shows a typical ADC-SHM circuit. The ADC-500 employs a
subranging architecture with digital error correction. Also known as
a two-step method of conversion, this technique uses a single 7-bit
flash converter twice in the conversion process to yield a final
resolution of 12 bits. Refer to the ADC-SHM connection diagram,
the ADC block diagram, and the timing diagram as needed
(Figures 4, 1 and 2 respectively).

7-bit ADC. The result of this second conversion is then latched to
determine the least 7 significant bits. The outputs from the two
registers are then added by the digital correction logic to produce a
12-bit word. EOC goes low, indicating the conversion is complete,
and the output passes to three-state output buffers.
Once the second step of the flash ADC is finished, the analog input
can change even though the conversion cycle has not been completed (EOC going low). The Sample/Hold control pin goes high a
minimum of 30 nanoseconds before EOC goes low, indicating that
the SHM-45 can be put back into the sample mode. This feature
improves the overall throughput of the ADC-SHM system.
Data from the previous conversion would be valid up to 350 nanoseconds after the falling edge of the START CONVERT pulse. Data
from the new conversion is valid a minimum of 25 nanoseconds
before EOC goes low and valid up to 350 nanoseconds after the
falling edge of the next START CONVERT pulse. There is a 10
nanosecond maximum delay after the three-state output buffers
are enabled before the data is valid at the device output.
The overall throughput using the ADC-500 and the SHM-45 consists of 200 nanoseconds for the sample time, 100 nanoseconds
for the hold and input settling time, 15 nanoseconds for observance
of min-max propagation delays and 470 nanoseconds for the conversion process (S/H control pin saves 30 nanoseconds). Total
throughput is a maximum of 785 nanoseconds for the system for a
guaranteed throughput rate of 1.25 MHz.

The ADC-500's conversion rate without a sample-hold would be
150 nanoseconds for input settling time and 500 nanoseconds for
The SHM-45, upon acquiring the input signal on the hold capacitor the ADC-500, yielding a minimum of 1.5 MHz conversion rate.
(200 nanoseconds maximum acquisition time to 0.01 %), is put into Retriggering of the start convert pulse before EOC goes low will
the hold mode prior to the analog-to-digital conversion. In the hold not initiate a new conversion.
mode, the SHM-45 requires a maximum of 100 nanoseconds to The performance characteristics shown in Table 6 apply over the
have its output buffer settle to 0.01 % accuracy. The ADC-500 re- operating temperature range and over the operating power supply
quires a maximum of 150 nanoseconds for the input signal to settle range unless otherwise specified. These charateristics are guaranbefore starting a conversion. The input of the ADC-500 starts set- teed by design.
tling to its final value while the SHM-45 is in the acquisition mode.

At the end of the SHM-45's hold mode settling time, the ADC-500's
input is fully settled. The missing 50 nanoseconds of the required
maximum analog input settling time is made up by the time the
Sample/Hold is in the acquisition mode. the end of the SHM-45's
hold mode settling time, the ADC-500's input is fully settled.
The SHM-45 is in the sample mode when the ADC-500's S/H control (Pin 17) is high. The S/H control pin is high and thus in the sample mode when the AID is not performing a conversion.
The S/H control pin goes low after the rising edge of the START
CONVERT pulse a minimum of 10 nanoseconds and a maximum
of 25 nanoseconds later. To assure the SHM has 200 nanoseconds
maximum acquisition time, the START CONVERT pulse should be
given a minimum of 190 nanoseconds after the desired start of the
acquisition time. The width of the START CONVERT pulse should
be 105 nanoseconds minimum to assure the hold mode settling
time of 100 nanoseconds is observed. The 105 nanoseconds takes
into account the min-max propagation delays of the START CONVERT high to S/H control low propagation delays and the START
CONVERT low to EOC high propagation delays.

TABLE 6. PERFORMANCE CHARACTERISTICS AT
DIFFERENT TEMPERATURES
VALUE

CHARACTERISTIC
Conversion Rate (Changing Inputs):

AOC-SOO
+25°C
DOG to + 70 0 e
_ 55°C to + 125°C
AOC-SOS

+25°C

oDe to

+ 70 0e

_55°C to + 125°C

Harmonic Distortion (Below FS)'
+25°e
aoe to + 70°C
_55°C to +125°e

1.5 MHz minimum
1.4 MHz minimum
1.4 MHz minimum
1.39 MHz minimum
1.35 MHz minimum
1.29 MHz minimum

- 72 dB minimum
- 72 dB minimum
- 65 dB minimum

To fully utilize the dynamic range of the ADC-500 and ADC-505, the
SHM-45 can be hardware-programmed to provide the appropriate
output voltage range. Table 7 shows the different input ranges
which can be obtained by selecting the appropriate SHM-45. See
the SH M-45 data sheet for connection details.

Conversion being initiated, switch S1 of the ADC closes and S2
opens. The analog input, having been configured for the appropriate range (± 10V range shown), is buffered and then digitized by
the 7-bit flash ADC to determine the seven most significant bits.
The seven bits of data are then stored in a register and provided to
the input of a 7-bit digital-to-analog converter. The DAC has 13 bits
of linearity.

TABLE 7. ADC-SHM INPUT RANGES

The first pass finished, S2 closes and S1 opens. The output of the
DAC is then subtracted from the analog input. The result is a
voltage difference between the first 7-bit digitization and the analog
input. This voltage difference is amplified and converted by the

-5 to
-10 to
o to
o to

VIN

Range

o to
o to

+ 10
-10
+5
+10
-20
-5

Gain
+1
-1
-2
-1
-0.5
-2

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-47

.'.',

ADC-500, ADC-505
.15V

·5V

.5V

ENABLE
BITS 1-5 & O.F.

BIT' (MSB)

81T2
BIT3
81T4

BIT 5

ADC-500/505

BIT6

81T7
BIT8
BIT9
BIT 10

81T11
BIT 12 (LSB)

OVERFLOW
ENABLE

BITS 6-12

Figure 4. ADC-SHM Connection Diagram

OFFSET ADJUST

ORDERING INFORMATION
MODEL
ADC-500-BMC
ADC-500-BMM
ADC-505-BMC
ADC-505-BMM
ACCESSORIES
Part Number
TP20K

OPERATING
TEMP. RANGE
O°C to +70°C
-55°C to +125°C
O°C to +70 oC
- 55°C to + 125°C

SEAL
Hermetic
Hermetic
Hermetic
Hermetic

Description
Trimming Potentiometers:
(Two required).

Receptable for PC board mounting can be ordered through
AMP Incorporated, #3-331272-8 (Component Lead Socket), 32
required.
For high reliability version of the ADC-SOO and ADC-505, contact DATEL.

1-48

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-508
12-Bit, Unra-fast, Low-power
AID Converter

•

FEATURES
• 12-Bit resolution
• 700 Nanosecond maximum
conversion time
• Low-power, 1.6W
• Small initial errors
• Three-state output buffers
• - 55°C to + 125°C operation
• Small 32-pin DIP

!

GENERAL DESCRIPTION
DATEL:s ADC-508 reflects the ultimate in
state-of-the-art analog signal conversion
technology. The ADC-508 boasts a conversion speed of 700 nanoseconds, along
with a low-power consumption of 1.6 watts.
DATEL:s ADC-508 is a 12-bit, analog-todigital converter which has small initial
errors and can also provide adjustment
capability for system errors. The ADC-508
has a maximum conversion time of 700
nanoseconds. Figure 1 is a simplified
block diagram.
Manufactured using thick-film and thin-film
hybrid technology, this converter's remarkable performance is based upon a
digitally-corrected subranging architecture. DATEL further enhances this technology by using a proprietary custom chip
and unique laser trimming schemes. The
ADC-508 is packaged in a 32-pin ceramic
DIP and consumes 1.6 watts.
The ADC-508 features three pin-programmable input ranges: 0 to + 10V, 0 to
+20V, and ± 10V dc. The input impedance is specified at 1.75K minimum for
unipolar ranges and 3.75K minimum for
the bipolar range, reducing stringent drive
requirements. Other specifications include
no missing codes over temperature, a
maximum gain tempco of ± 35 ppm/oC
and a maximum differential linearity
tempeo of ± 2.5 ppmloC.
All digital inputs and three-state outputs
are TTL- and CMOS-compatible. Output
coding can be in straight binaryloffset
binary or complementary binarylcomplementary offset binary by using the COMP
BIN pin, An overflow pin indicates when inputs are below or above the normal fullscale range.

Figure 1. ADC-508 Simplified Block Diagram

INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (mm)
PIN

L . ,.,o, MAX-----.l

r---

~I

(28.0)

I

Ie:

0.150 (3,8) MIN

J.

----L-

I

0.190 (4,9) MAX

ft

0,010 x 0.Q18 Kovar

'16

17

-fl
T

'
I
L~

1712 MAX

;:~~.

BOTTOM

VIEW

11

32

L.._ _ _ _ _-:-' - - 0

I~

*"......

0.900 ____

_0.100

r--{22,9)

NOTE: Pins have 0.025 inch, ± 0.01
stand off from case

(2,5)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

SIGNAL NAME

+10VAEF
RANGE
INPUT HIGH
INPUT LOW
OFFSET ADJUST
NO CONNECTION
COMP BIN
OVERFLOW
ENABLE (6·12)
ENABLE (1·5. OF)
+5V
DIGITAL GROUND
+1SV

-lSV
-5V
ANALOG GROUND

S/H CONTROL
EOC
BIT 12 (LSB)
BIT 11
BIT 10
BIT9
BIT 8
BIT 7
BIT6
BIT 5
BIT 4
BIT 3
BIT2
BIT 1 (MSB)
START CONVERT
GAIN ADJUST

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

1-49

ADC-508
3. Bypass all the analog and digital supplies and the + 10V reference (pin 1) to ground with a 4.7 "F, 2SV tantalum electrolytic
capacitor in parallel with a 0.1 "F ceramic capacitor. Bypass the
+ 1OV reference (pin 1) to analog ground (pin 16). The - SV dc
supply is treated as an analog supply and analog ground (pin 16)
should be treated as its return path for decoupling purposes.
4. Obtain straight binary/offset binary output coding by tieing
COMP BIN (pin 7) to + SV dc or leaving it open. The device has
an internal pull-up resistor on this pin. To obtain complementary
binary or complementary offset binary output coding, tie the
COMP BIN pin to ground. The COMP BIN signal is compatible
to CMOSITTL logic levels for those users desiring logic control
of this function.
S. An overflow signal, pin 8, indicates when analog input signals
are below or above the desired full-scale range. The overflow
pin also has a three-state output and is enabled by pin 10
(Enable bits 1-S & O.F.).

8. Over temperature, input capacitance is SO pF maximum and input impedance is 1. 7SK minimum (2.SK typical) for unipolar and
3.7SK minimum (SK typical) for bipolar. These values are guaranteed by design.
9. Requirements for ± 2.SV inputs can be satisfied using DATEL's
AM-143S amplifier in front of the SHM-4S/ADC-S08 configuration, shown in Figure 4, at the appropriate gain. The SHM-4S's
gain of 2 mode allows 0 to + SV or ± SV input ranges.

TIMING
Figure 2 shows the relationship between the various input signals.
The timing cited in Table 1 applies over the operating temperature
range and over the operating power supply range. These times are
guaranteed by design.

TABLE 1. SIGNAL TIMING SUMMARY

6. The Sample/Hold control signal, pin 17, goes low following the
rising edge of a start convert pulse and high 30 nanoseconds
minimum beiore EOC goes low. This indicates that the converter can accept a new analog input.
7. The drive requirements of the ADC-S08 may be satisfied with a
wide-bandwidth, low output impedance input source. Applications of these converters that require the use of a sample-hold
may be satisfied by using DATEL's model SHM-4S. Using this
device with multiplexers or for test purposes will require an input
buffer.
ANALOG

INPUT

~

:
-r-

Data Valid Before EOC
Goes low

25 nsec. minimum

Enable to Output Data Valid
Propagation Delay

10 nsec. maximum

I

I

105nSec MINIMUM

:

-H

I

I'

.f+-:
,

-1:

I

I
I

r-,

,

:
I

200nSec ACOUISITIONTIME

I

I I

I

14-:,_--.J!
~

,
H-

L - - - - f o l....
, ....

"

I

I

~

I
----.J

:

'00 nSec HOLD MODE SETTLING TIME

I

II

,

!

!,

(when used with SHM-4S)

~-~:---------------------,

,

I

51H

350 nsec. minimum

I

I

:
I

35 nsec. maximum

Start Convert Low to Previous
Output Data Invalid

I

I

,,

Start Convert Low to EOC
High Propagation Delay

------'1-'- ____________________

I
I
I

,,
,

Eoe

150 nsec. minimum

'

~~~~~~~

I

START
CONVERT

50 nsec. minimum

Analog Input Settling Time

I

I

SETTLING
TIME

DURATION IN NANOSECONDS

NOTE NOT DRAWN TO SCALE

,

AI:~~G

LINE
Start Convert (AID)

I

T,MAXIMUM

---------11

L

20nSec MINIMUM

35 nSec MAXIMUM

IOnSec MINIMUM

I

25rtSec MAXIMUM

_I

30nSec

L

MINIMUM

,-

I

Lr!----------------~I----,'!----1 L__

1\

I

1 - - - - - - - - . =t~~~

I

--------1

OUTPUT DATA

-,

I

25 nSec

MINIMUM

DATA N VALID

ENABLED DATA N·1 VALID
(BITS 1·5,OF)

F

ENABLED DATA N·1 VALID
(BITS 6-12)

I:"NABLED DATA N

ENABLED DATA N
VALID

,VALID

A()().5Oa
CONVERSION
TIME(T1)

700 nSec ,740 nSec

no nSec

INVALID DATA

~

Figure 2. ADC-508 and SHM-45 Timing Diagram
1-50

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-S08
TABLE 4. OUTPUT CODING FOR UNIPOLAR
OPERATION

CALIBRATION PROCEDURE
Removal of system errors or the small initial errors is accomplished
as follows:
1. Connect the converter per Figure 3 and Table 2 for the appropriate full-scale range (FSR). Apply a pulse of 50 nanoseconds
minimum to the START CONVERT input (pin 31) at a rate of 500
kHz. This rate is chosen to reduce flicker if LED's are used on
the outputs for calibration purposes.
2. Zero Adjustments
Apply a precision voltage reference source between the analog
input (pin 3) and ground (pin 16). Adjust the output of the reference source per Tables 3a and 3b for the unipolar zero adjustment ( + '/2 LSB) or the bipolar zero adjustment (zero +Y2 LSB)
for the appropriate FSR. For unipolar, adjust the zero trimming
potentiometer so that the output code flickers equallv between
000000000000 and 0000 0000 0001 with the COMP BIN (pin 7)
tied high or between 1111 1111 1111 and 1111 1111 1110 with
the COMP BIN tied low.
For bipolar operation, adjust the potentiometer such that the
code flickers egually between 100000000000 and 10000000
0001 with COMP BIN tied high or between 0111 1111 1111 and
0111 1111 1110 with COMP BIN tied low.
3. Full-Scale Adjustment
Set the output of the voltage reference used in step 2 to the
value shown in Table 3a or 3b for the unipolar or bipolar gain adjustment ( + FS - 1V2 LSB) for the appropriate FSR. Adjust the
gain trimming potentiometer so that the output code flickers
equally between 1111 1111 1110 and 1111 1111 1111 for
COMP BIN (pin 7) tied high or between 0000 0000 0001 and
0000 0000 0000 for COMP BIN tied low.
4. To confirm proper operation of the device, vary the precision reference voltage source to obtain the output coding listed in
Tables 4 and 5.

UNIPOLAR
SCALE

INPUT RANGES,
VOLTS de

OUTPUT CODING
STRAIGHT BINARY

Oto +10V

o to

+20V

MSB

+FS - LSB

+9.9976V

+ 19.9951V

1111

1111

COMP. BINARY

LSB

MSB

1111

0000 0000 0000

LSB

%FS

+B.7500V

0000

0000

0001

1111

1111

+7.5000V

+ 17.500V
+ 15.000V

1110

%FS

1100

0000

0000

0011

1111

1111

lh FS

+5.0000V

+10.000V

1000

0000

0000

0111

1111

1111

V4 FS

+2.5000V

+5.0000V

0100

0000

0000

1011

1111

1111

Va FS

+1.2500V

+2.5000V

0010

0000

0000

1101

1111

1111

+O.OO24V

+O.OO49V

0000

0000

0001

1111

1111

1110

O.OOOOV

O.OOOOV

0000

0000

0000

1111

1111

1111

1 LSB
0

TABLE 2. INPUT CONNECTIONS
INPUT VOLTAGE RANGE

INPUT PIN

Oto +10Vdc

3

CONNECT PIN 2 (RANGE) TO PIN:

3

o to +20V de

3

16

± 10V de

3

1

TABLE 3a. ZERO AND GAIN ADJUST FOR UNIPOLAR
USE
UNIPOLAR FSR

ZERO ADJUST

GAIN ADJUST

+112 LSB
Oto +10Vdc

+1.22 mV
+2.44 mV

+FS -H'2 LSB
+9.9963V de

Oto +20Vdc

+ 19.9927V de

TABLE 3b. ZERO AND GAIN ADJUST FOR BIPOLAR
USE
BIPOLAR FSR

± lOV de

ZERO ADJUST
ZERO +"12 LSB

+FS -l1f2LSB

GAIN ADJUST

+2.44 mV

+9.9927V de

Figure 3. ACC-50S Calibration Circuit

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

1-51

•

ADC-508
Another novel feature of the ADC-50B is the provision of a Sampie/Hold control pin for applications where a sample-hold is used in
conjunction with the ADC-50B. This feature allows the sample-andhold device to go back into the sample mode a minimum of 30
nanoseconds before the conversion is complete, improving the
overall conversion rate of the system.
Power required is ± 15V dc and ± 5V dc. Models are available in the.
commercial O°C to + 70°C, and military -55°C to + 125°C operating temperature range. Typical applications include spectrum, transient, vibration, and waveform analysis. These devices are also
ideally suited for radar, sonar and video digitization, medical instrumentation, and high-speed data acquisition systems. For information
on versions with high reliability screening, contact the factory.

ABSOLUTE MAXIMUM RATINGS
Parameters
MINIMUM
+ 15V Supply (Pin 13) ...
0
0
-15V SUP~IY (Pin 14) ...
+ 5V Supp y (Pin 11) .... -0.5
- 5V Supply (Pin 15) .... +0.5
Di8HBI Inputs
Pins 7,9, 10 & 31) ... -0.3
Analog Input (Pin 3) ....
-15
Lead temp. (10 sec) ....

MAXIMUM
+18
-18
+7
-7
+6
+15
300

UNITS
Volts de
Volts de
Votts de
Volts de
Volts de
VoHs de
~C

FUNCTIONAL SPECIFICATIONS

Apply over the operating temperature range and over the operating
power supply range unless otherwise specified.
DESCRIPTION

MIN.

TYP.

MAX.

UNITS

INPUTS
Input VOlta~e Range ... (See Tec . Note 9)

-

Logic Levels: Logic 1 .. 2.0
Logic 0 .. Logic Loading: Logic 1 . LogicO. -

o to + 10
o to +20
±10

-

--

-

-

0.8
2.5
-100

Volts
Volts
Volts
Volts
Volts

dc
dc
dc
dc
dc

pA
pA

OUTPUTS
Output Coding:
!Pin 7 High) ........
Pin7Low) ........

straight binary/offset binary
complementary binary
complementary offset binary

Logic Levels: Logic 1 .. 2.4
Logic 0 ..
Logic Loading: Logic 1 . LogicO.
Internal Reference:
Voltage, + 25°C .... 9.98
Drift .............. External Current .... -

-

±5

-

-

0.4
-160
6.4
10.02
±30
1.5

1-52

-

--

-

-

±3

-

-

-

-

-

±'/2

DESCRIPTION
Unipolar Zero Error,
+25·C .............
Unipolar Zero Tempeo ..
Bipolar Zero Error,
+25·C .............
Bipolar Zero Tempeo ...
Bipolar Offset Error,
+25·C .............
Bipolar Offset Error
Tempeo ............
Gain Error, + 25·C .....
Gain Tempeo ..........
Conversion Times:
ADC-508
+25°C ...........
O°C to + 70·C .....
-55·Cto +125·C ..
No Missing Codes
(12 Bits): ............

MIN.

TYP.

MAX.

UNITS

-

±1
±13

±3
±25

LSB
ppm/oC

-

±1
±13

±3
±25

LSB
ppm/oC

--

±2

±5

LSB

±17.5
±2
±17.5

±35
±5
±35

ppm/oC
LSB
ppm/oC

700
740

nsec.
nsee.
nsee.

-

770

Over the Operating Temp. Range

POWER SUPPLY REQUIREMENTS
Power Supply Range:
+ 15V de Supply .....
- 15V dc Supply .....
+ 5V dc Supply ......
- 5V de Supply ......
Power Supply Current:
+ 15V Supply ........
- 15V Supply ........
+5VSupply' ........
-5VSupply .........
Power Dissipation ......
Power Supply Rejection .

+ 14.25
"':14.25
+4.75
-4.75

-

+15
-15
+5
-5

+15.75
-15.75
+5.25
-5.25

Volts dc
Volts dc
Volts dc

+23
-11
+55
-175
1.6

+30
-15
+90
-210
1.8
0.01

rnA
rnA
rnA
rnA
Watts
%FSRI%V

-

Volts de

PHYSICAL/ENVIRONMENTAL
~

Operating Temp. Range:
-BMC .............
0
+70
-BMM ............. -55
+125
Storage Temperature
Range .............. -65
+150
Package Type ......... 32'pin hermetic sealed, ceramic
Pins ................. 0.010 x 0.018 inch Kovar
Weight ............... 0.42 ounces (12) grams

°C
°C
°C
DIP

• + 5V power usage at 1TTL logic loading per data output bit.

VoHs de
Volts dc
pA

rnA
Volts dc

ppm/oC
rnA

PERFORMANCE
Integral Nonlinearity:
+25·C ............
O°C to + 70°C ......
-55°Cto +125°C ..
Integral NonHn. Tempco.
Differential Nonlinearity
+25°C ............
O·C to + 70·C ......
-55·Cto +125·C ..
Differential Nonlin.
Tempeo ...........
Full-Scale Absol.
Accuracy:
+25°C ............
O·C to + 70·C ......
-55·Cto + 125°C ..

PERFORMANCE (eont.)

±0.0125 %FSR ±'/2 LSB
±0.0125 %FSR ±V2 LSB
±0.0125 %FSR ±3 LSB
pprn/oC
±8
±0.0125 %FSR ±'/2 LSB
±0.0125 %FSR +'/2 LSB
±0.0125 %FSR ±1 LSB

-

±2.5

ppm/oC

±3
±4
±8

±8
±14
±29

LSB
LSB
LSB

TECHNICAL NOTES
1. Use external potentiometers to remove system errors or the
small initial errors to zero. Use a 20K trimming potentiometer for
gain adjustment with the wiper tied to pin 32 (ground pin 32 for
operation without adjustments). Use a 20K trimming potentiometer with the wiper tied to pin 5 for zer%ffset adjustment
(leave pin 5 open for operation without adjustment).
2. Rated performance requires using good high frequency circuit
board layout techniques. The analog and digital grounds are not
connected internally. Avoid ground-related problems by connecting the digital and analog grounds to one point, the ground
plane beneath the converter (versus at the power supply terminals when the power supplies are located some distance from
the ground plane). Due to the inductance and resistance of the
power supply return paths, return the analog and digital ground
separately to the power supplies. This prevents contamination
of the analog ground by noisy digital ground currents.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048~ 1194ITEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-508
TABLE 5. OUTPUT CODING FOR UNIPOLAR
OPERATION
BIPOLAR
SCALE

INPUT
RANGE

OUTPUT CODING
OFFSET BINARY
COMP. OFFSET BINARY
MSB
t1DV de
LSB
MSB
LSB
+FS-1LSB
+9.99S1V
1111
1111
1111
0000
0000
0000
+ 7.S000V
1110
+34 FS
0000 0000
0001
1111
1111
+s.oooov
1100
0000 0000
0011
1111
1111
O.OOOOV
1000 0000 0000
0111
1111
1111
-1J2 FS
-5.0000V
0100 0000 0000
1011
1111
1111
-_-=-"':-:F=S----_"""'7::-:.5:::00:-:077V---:O""01c:-0-----,00c:-0:c:0-0:c:00"'0:---1-,10"'"1--11-'1-1--1--11-1-FS +1 LSB
-99951V
0000 0000 0001
1111
1111
1110
--"'=F::-S-'-'-=----l"'O':::.ooo=V--:o:::oo'=-o---'o'=-ooo:::-.-....:oo:.:::.:OO:---l:.:l.:.:ll--'-'-ll:.:l.:..l-"":1:':11:':1-

THEORY OF OPERATION (ADC-50B and SHM-45)

7-bit ADC. The result of this second conversion is then latched to
determine the least 7 significant bits. The outputs from the two
registers are then added by the digital correction logic to produce a
12-bit word. EOC goes low, indicating the conversion is complete,
and the output passes to three-state output buffers.
Once the second step of the flash ADC is finished, the analog input
can change even though the conversion cycle has not been completed (EOC going low). The Sample/Hold control pin goes high a
minimum of 30 nanoseconds before EOC goes low, indicating that
the SHM-45 can be put back into the sample mode. This feature
improves the overall throughput of the ADC-SHM system.
Data from the previous conversion would be valid up to 350 nanoseconds after the falling edge ofthe START CONVERT pulse. Data
from the new conversion is valid a minimum of 25 nanoseconds
before EOC goes low and valid up to 350 nanoseconds after the
falling edge of the next START CONVERT pulse. There is a 10
nanosecond maximum delay after the three-state output buffers
are enabled before the data is valid at the device output.

This theory of operation describes the ADC-50S's operation in conjunction with DATEL's SHM-45. The SHM-45 sample-and-hold,
device captures fast signals for an ADC-50S to then digitize. Figure
4 shows a typical ADC-SHM circuit. The ADC-50S employs a
subranging architecture with digital error correction. Also known as
a two-step method of conversion, this technique uses a single 7-bit
flash converter twice in the conversion process to yield a final
resolution of 12 bits. Refer to the ADC-SHM connection diagram,
the ADC block diagram, and the timing diagram as needed
(Figures 4, 1 and 2 respectively).

T.he overall throughput using the ADC-50S. and the SHM-45 conSIStS of 200 na~osecond~ for.the sample time, 100 nanoseconds
for the hold and Input settling time, 15 nanoseconds for observance
of m.ln-max propaga!!.on delays ~nd 770 nanoseconds for the conversion pro?ess (S/~ control pin saves 30 nanoseconds). Total
throughput IS a maximum of 10S5 nanoseconds for the system for
a guaranteed throughput rate of 920 KHz.
The ADC-50S's conversion rate without a sample-hold would be
150 nanoseconds for input settling time and SOO nanoseconds for
the ADC-50S, yielding a minimum of 1.0 MHz conversion rate.
Retriggering of the start convert pulse before EOC goes low will
The SHM-45, upon acquiring the input signal on the hold capacitor
not initiate a new conversion.
(200 nanoseconds maximum acquisition time to 0.01 %), is put into
the hold mode prior to the analog-to-digital conversion. In the hold The performance characteristics shown in Table 6 apply over the
mode, the SHM-45 requires a maximum of 100 nanoseconds to operating temperature range and over the operating power supply
have its output buffer settle to 0.01 % accuracy. The ADC-50S re- range unless otherwise specified. These charateristics are guaranquires a maximum of 150 nanoseconds for the input signal to settle teed by design.
before starting a conversion. The input of the ADC-50S starts settling to its final value while the SHM-45 is in the acquisition mode.
At the end of the SHM-45's hold mode settling time, the ADC-50S's
input is fully settled. The missing 50 nanoseconds of the required
maximum analog input settling time is made up by the time the
sample/hold is in the acquisition mode.

The SHM-45 is in the samme mode when the ADC-50S's S/H control (Pin 17) is high. The S/H control pin is high and thus in the sample mode when the AID is not performing a conversion_
The siR control pin goes low after the rising edge of the START
CONVERT pulse a minimum of 10 nanoseconds and a maximum
of 25 nanoseconds later. To assure the SHM has 200 nanoseconds maximum acquisition time, the START CONVERT pulse
should be given a minimum of 190 nanoseconds after the desired
start of the acquisition time. The width of the START CONVERT
pulse should be 105 nanoseconds minimum to assure the hold
mode setting time of 100 nanoseconds is observed. The 105 nanoseconds takes into account t~ min-max propagation delays of the
START CONVERT high to S/H control low propagation delays and
the START CONVERT low to EOC high propagation delays.
Conversion being initiated, switch S1 of the ADC closes and 82
opens. The analog input, having been configured for the appropriate range (± 10V range shown), is buffered and then digitized by
the 7-bit flash ADC to determine the seven most significant bits.
The seven bits of data are then stored in a register and provided to
the input of a 7-bit digital-to-analog converter. The DAC has 13 bits
of linearity.
The first pass finished, S2 closes and S1 opens. The output of the
DAC is then subtracted from the analog input. The result is a
voltage difference between the first 7-bit digitization and the analog
input. This voltage difference is amplified and converted by the

TABLE 6. PERFORMANCE CHARACTERISTICS AT
DIFFERENT TEMPERATURES
VALUE

CHARACTERISTIC
Conversion Rate (Changing Inputs):

ADC·508

DOG to + 70 0 e
- 55°C to + 125°C

1.0 MHz minimum
960 KHz minimum

Harmonic Distortion (Below FS):

+ 25°C
OOG to + 70 Ge
-55°C to +125 0 ( ;

- 72 dB minimum

- 72 dB minimum
- 65 dB minimum

To fully utilize the dynamic range of the ADC-50S , the SHM-45 can
be hardware-programmed to provide the appropriate output
voltage range. Table 7 shows the different input ranges which can
be obtained by selecting the appropriate 8HM-45. See the SHM-45
data sheet for connection details.

TABLE 7. ADC-SHM INPUT RANGES

V1NRange

o to
o to
-5 to
-10to
Oto
o to

+ 10
-10
+5
+10
-20
-5

Gain
+1
-1
-2
-1
-0.5
-2

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-53

•

Ace-508
+15V

~5V

+5V

ENABLE
BITS 1-5 & O.F
GAIN ADJUST

Bll 1 (MSB)
BIT2
+tOV REF
81T3
RANGE

BIT 4

SHM-45

BIT 5
INPUT HI

ADC-50S
INPUT lOW

BIT6
BIT 7

BIT B

HOLD
81T9

BIT 10
BIT 11
BIT 12 (LSB)
STAAT CONVERT
OVERFLOW

ENABLE
BITS 6-12

SfH CONTROL

L---------------------------------_.---{17

si'H CONTROL

Figure 4. ADC-SHM Connection Diagram

-15V
OFFSET ADJUST

ORDERING INFORMATION
MODEL
ADC-508-MC
ADC-508-MM
ACCESSORIES
Part Number
TP20K

OPERATING
TEMP. RANGE

SEAL

O°C to + 70°C
-55°C to + 125°C

Hermetic
Hermetic

Description
Trimming Potentiometers:
(Two required).

Receptable for PC board mounting can be ordered tbrough
AMP Incorporated, #3-331272-8 (Component Lead Socket), 32
required.
For high reliability version of the ADC-508 contact DATEL.

1-54

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 0204S-1194ITEL (50S) 339-3000ITLX 1743SS/FAX (50S) 339-6356

ADC-510, ADC-515
10-Bit, Ultra-fast, Low-power
AID Converters
FEATURES
•
•
•
•
•
•
•

10-Bit resolution
450 Nanosecond conversion time
Lower-power, 1.6W
Small initial errors
Three-state output buffers
- 55°C to + 125°C operation
Small 32-pin DIP

GENERAL DESCRIPTION
DATEL's ADC-5l0 and ADC-5l5 reflect
the ultimate in state-of-the-art analog signal conversion technology. The ADC-5l0
boasts a remarkable conversion speed of
380 nanoseconds, along with a low-power
consumption of 1.6 watts.
DATEL's ADC-5l0 and ADC-5l5 are
10-bit analog-to-digital converters which
have small initial errors and can also provide adjustment capability for system errors. Both models have identical specifications except for conversion times. The
ADC-5l5 has a maximum conversion time
of 650 nanoseconds while the ultra-fast
ADC-510 accomplishes a 10-bit conversion in less than or equal· to 425 nanoseconds. Figure 1 is a simplified block
diagram applicable to both devices.
Manufactured using thick-film and thin-film
hybrid technology, these converters'
remarkable performances are based upon
a digitally-corrected subranging architecture. DATEL further enhances this technology by using a proprietary custom chip
and unique laser trimming schemes. The
ADC-5l0 and ADC-5l5 are packaged in a
32-pin ceramic DIP.
The ADC-5l0 and ADC-5l5 feature three
pin-programmable input ranges: 0 to
+ 10V, 0 to +20V, and ± 10V dc. The input impedance is specified at 1.75K
minimum for unipolar ranges and 3.75K
minimum for the bipolar range, reducing
stringent drive requirements. Other
specifications include a maximum nonlinearity of ± '12 LSB, a maximum gain
tempco of ± 35 ppm/oC and a maximum
differential linearity tempco of ± 2.5
ppm/cC.
All digital inputs and three-state outputs
are TTL- and CMOS-compatible. Output
coding can be in straight binary/offset
binary
or
complementary
binary/
complementary offset binary by using the
COMP BIN pin. An overflow pin indicates when inputs are below or above
the normal full-scale range.

FN"~lf(6.IOJ

Figure 1. ADC-510, ADC-515 Simplified Block Diagram

INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (mm)
PIN

~'10' MAX----.l

I

.L

~I~

(28,0)

I

I
~t

0.190(4.9)MAX

I=C

0.150 (3,8) MIN

0.010 x 0.Q18 Kovar

116

17

BOTTOM
VIEW

11

32

rl
;: : :.I
L,"

~------:-' - - 0

I~

,,~..."t-_0100

0900 _ _

~(22,91

NOTE: Pins have 0.025 inch, ±O.01
stand off from case

(2,5)

1
2
3
4
5
6
7
8
9
10
11

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

SIGNAL NAME

+10V REF
RANGE
INPUT HIGH
INPUT LOW
OFFSET ADJUST
NO CONNECTION
COMP BIN
OVERFLOW
ENABLE 16·101
ENABLE 11-5, O.FI
+5V
DIGITAL GROUND
+15V
-15V
-5V
ANALOG GROUND
SIH CONTROL
EOC
NC
NC

BIT 10 (LSB)
BIT9
BIT8
BIT 7
BIT6
BIT 5
BIT 4
BIT3
BIT2
BIT 1 (MSB)
START CONVERT
GAIN ADJUST

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1·55

ADC-510, ADC-515
Another novel feature of the ADC-510 is the provision of a Sample/Hold control pin for applications where a sample-hold is used in
conjunction with the ADC-510. This feature allows the sample-andhold device to go back into the sample mode a minimum of 30
nanoseconds before the conversion is complete, improving the
overall conversion rate of the system.
Power required for both models is ± 15V dc and ± 5V dc. Models
are available in the commercial O°C to + lO°C, and military
- 55°C to + 125°C operating temperature range. Typical applications include spectrum, transient, vibration, and waveform
analysis. These devices are also ideally suited for radar, sonar and
video digitization, medical instrumentation, and high-speed data
acquisition systems. For information on versions with high reliability
screening, contact the factory.
ABSOLUTE MAXIMUM RATINGS
Parameters
MINIMUM
+ 15V Supply (Pin 13) ...
0
-15V Supply (Pin 14) ...
0
-0.5
+ 5V Supply (Pin 11) ....
+0.5
- 5V Supply (Pin 15) ....
Digital Inputs
(Pins 7,9,10 & 31) ....
-0.3
Analog Input (Pin 3) .....
-15
Lead temp. (10 sec) .....

MAXIMUM
+18
-18
+7
-7

UNITS
Volts dc
Volts dc
Volts dc
Volts dc

+6
+15
100

Volts dc
Volts dc
°C

FUNCTIONAL SPECIFICATIONS
Apply over the operating temperature range and over the operating
power supply range unless otherwise specified.
DESCRIPTION

MIN.

TYP.

MAX.

UNITS

INPUTS
Input Voltage Range ....
Logic Levels: Logic 1 ...
LogicO ...
Logic Loading: Logic 1 ..
Logic 0 ..

2.0
-

o to + 10
o to +20
±10

-

-

-

0.8
2.5
-100

Volts
Volts
Volts
Volts
Volts

dc
dc
dc
dc
dc

J.-----'
I

-55 to +125 "C

460nSec.

:

I I

L-______

Oto+70"C

AOC510

CONVERSION
TrME(T1)

10 r>Sec

MAXIMUM

F

NABLED DATA N
VALID

1':.NABLED DATA N
,VALID

INVALID DATA

~

Figure 2. ADC-510 and SHM-45 Timing Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-57.

ACC-510, ACC-515
CALIBRATION PROCEDURE

TABLE 4. OUTPUT CODING FOR UNIPOLAR
OPERATION

Removal of system errors or the small initial errors is accomplished
as follows:
1. Connect the converter per Figure 3 and Table 2 for the appropriate full-scale range (FSR). Apply a pulse of 50
nanoseconds minimum to the START CONVERT input (pin 31)
at a rate of 500 kHz. This rate chosen to reduce flicker if LED's
are used on the outputs for calibration purposes.
2. Zero and Offset Adjustments
Apply a precision voltage reference source between the analog
input (pin 3) and ground (pin 16). Adjust the output of the
reference source per Tables 3a and 3b for the unipolar zero adjustment (+ V,LBS) orthe bipolar zero adjustment (Zero +V,LBS)
for the appropriate FSR. Adjust the zero trimming potentiometer so that the output code flickers equally between 00 0000
0000 and 00 0000 0001 with the COMP BIN (pin 7) tied high or
between 1111111111 and 1111111110withthe COMP BIN tied
low.
For bipolar operation, adjust the potentiometer such that the
code flickers equally between 1000 0000 0000 and 1000 0000
0001 with COMP BIN tied high or between 011111111111 and
011111111110 with COMP BIN tied low.

UNIPOLAR
SCALE

INPUT RANGES,
VOLTS de

OUTPUT CODING
STRAIGHT BINARY

010

+

10V

Oto +20V

MSB

COMP.BINARY

LSB

MSB

11
11
11

1111

1111

0000

0000

1000
0000

0000
0000

00
00
00

0111

1111

LSB

1111

1111

10

0000

0000

01

1111

1111

0000

0000

10

1111

1111

7laFS

+9.99023V
+B.7500V

3j4FS

+ 7.5000V

lkFS

+5.0000V

+ 19.9a04V
+ 17.S00V
+ lS.aODV
+ 10.000V

1/4FS

+2.S000V

+S.OOOOV

01

llaFS

+ 1.2500V

+2.S000V

00

1000

0000

11

0111

1111

+O.00977V

+O.0195V

00

0000

0001

1111

1110

O.OOOOV

O.OOOOV

00

0000

0000

11
11

1111

1111

+FS-1LSB

+1 LSB

0

3. Full-Scale Adjustment
Set the output of the voltage reference used in step 2 to the
value shown in Table 3a or 3b for the unipolar or bipolar gain adjustment (+ FS -1 1hLSB) for the appropriate FSR. Adjust the
gain trimming potentiometer so that the output code flickers
equally between
11 1111 1110 and 11 1111 1111 for
COMP BIN (pin 7) tied high or between 00 0000 0001 and
00 0000 0000
for COMP BIN tied low.
4. To confirm proper operation of the device, vary the precision
reference voltage source to obtain the output coding listed in
Tables 4 and 5.

TABLE 2. INPUT CONNECTIONS
INPUT VOLT AGE RANGE
Oto+1DVdc

o to +20V de

± IOV de

INPUT PIN

CONNECT PIN 2 (RANGE) TO PIN:

3
3
3

16

3
1

TABLE 3a. ZERO AND GAIN ADJUST FOR UNIPOLAR
USE
UNIPOLAR FSR

ZERO ADJUST

GAIN ADJUST

+ Viz LSB

+FS -IV2 LSB

Oto +10Vdc

+4.88mV

+ 9.9927Vdc

010 +20V de

+9.77mV

+ 19.9854Vdc

Figure 3. ADC-510 Calibration Circuit

TABLE 3b. ZERO AND GAIN ADJUST FOR BIPOLAR USE
BIPOLAR FSR

ZERO ADJUST

t. 10V de

ZERO +'hLBS
+9.77mV

1-58

GAIN ADJUST

+FS -1VizLSB
+9.9707V de

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-510, ADC-515
TABLE 5. OUTPUT CODING FOR UNIPOLAR
OPERATION
BIPOLAR
SCALE

INPUT
RANGE

OUTPUT CODING
OFFSET BINARY

COMPo OFFSET BINARY

·+10Vdc

MSB

+9.9a05V

11

1111

LSB
1111

MSB

+F$ 1lSB

00

0000

0000

+3f4FS

+ 7.5000V

0000

00

0111

1111

+5.0000V

11
11

1000

+lkFS

0000

0000

00

1111

1111

0

O.OOOOV

10

0000

0000

01

1111

1111

-lhFS

-5.OOOOV

01

0000

0000

10

1111

3f4FS

7.5000V

11

1000

0000

11

0111

1111

FS+1LSB

9.9B05V

00

0000

0001

11

1110

-lO.ODOV

00

0000

0000

11

1111
1111

-FS

LSB

1111

1111

THEORY OF OPERATION (ADC·S10 and SHM-4S)
This theory of operation describes the ADC-510's operation in conjunction with DATEL's SHM-45. The SHM-45 sample-and-hold
device can be used to capture fast signals for an ADC-510 to then
digitize. Figure 4 shows a typical ADC-SHM circuit. The ADC-510
employs a subranging architecture with digital error correction.
Also known as a two-step method of conversion, this technique
uses a single 7-bit flash converter twice in the conversion process
to yield a final resolution of 10 bits. Refer to the ADC-SHM connection diagram, the ADC block diagram, and the timing diagram as
needed (Figures 4, 1, and 2 respectively).
The SHM-45, upon acquiring the input signal on the hold capacitor
(170 nanoseconds maximum acquisition time to 0.1%), is put into
the hold mode prior to the analog-to-digital conversion. In the hold
mode, the SHM-45 requires a maximum of 80 nanoseconds to
have its output buffer settle to 0.1% accuracy. The ADC-510 requires a maximum of 150 nanoseconds for the input signal to settle
before starting a conversion. The input of the ADC-510 starts settling to its final value while the SHM-45 is in the acquisition mode.
At the end of the SHM-45's hold mode settling time, the ADC-510's
input is fully settled.
A minimum START CONVERT pulse of 85 nanoseconds is
required, conversion starting on the falling edge of the START
CONVERT pulse with EOC going high a maximum of 35 nanoseconds later. The missing 30 nanoseconds of the required maximum analog input settling time is made up bythetimethe sample/hold is in the acquisition mode.
The SHM-45 is in the sample mode when the ADC-510's SiR
control (Pin 17) is high. The S/H control pin is high and thus in the
sample mode when the A/D is not performing a conversion.
The S/H control pin goes low after the rising edge of the START
CONVERT pulse a minimum of 10 nanoseconds and a maximum
of 25 nanoseconds later. To assure the SHM has 170 nanoseconds
maximum acquisition time, the START CONVERT pulse should be
given a minimum of 160 nanoseconds after the desired start of the
acquisition time. The width of the START CONVERT pulse
should be 85 nanoseconds minimum to assure the hold mode
settling time of 80 nanoseconds is observed. The 85 nanoseconds
takes into account the min-max propagation delays of the START
CONVERT high to S/H control low propagation delays and the
START CONVERT low to EOC high propagation delays.
Conversion being initiated, switch S1 of the ADC closes and S2
opens. The analog input, having been configured for the appropriate range ( ± 10V range shown), is buffered and then digitized
by the 7-bit flash ADC to determine the seven most significant bits.
The seven bits of data are then stored in a register and provided to
the input of a 7-bit digital-to-analog converter. This DAC has 13 bits
of linearity.
The first pass finished, S2 closes and S1 opens. The output of the
DAC is then subtracted from the analog input. The result is a

voltage difference between the first 7-bit digitization and the analog
input. This voltage difference is amplified and converted by the
7-bit ADC. The result of this second conversion is then latched to
determine the least 7 significant bits. The outputs from the two
registers are then added by the digital correction logic to produce a
10-bit word. EOC goes low, indicating the conversion is complete,
and the output passes to three-state output buffers.
Once the second step of the flash ADC is finished, the analog input
can cha~even though the conversion cycle has not been completed (EOC going low). The Sample/Hold control pin goes high a
minimum of 30 nanoseconds before EOC goes low, indicating the
the SHM-45 can be put back into the sample mode. This feature
improves the overall throughput of the ADC-SHM system.
Data from the previous conversion would be valid up to 275
nanoseconds after the falling edge of the START CONVERT pulse.
Data from the new conversion is valid up to 275 nanoseconds after
the falling edge of the next START CONVERT pulse. There is a 10
nanosecond maximum delay after the three-state output buffers
are enabled before the data is val id at the device output.
The overall th roug hput of the ADC-51 0 and the SH M-45 config u ration consists of the 170 nanoseconds for the sample time, 80
nanoseconds for the hold and input settling time, and 480 nanoseconds for the conversion process (S/H control pin saves 30
nanoseconds). Total throughput is a maximum of 730 nanoseconds for the system or a throughput rate of 1.35 MHz. The ADC510's conversion rate without a sample-hold would be 150 nanoseconds for input settling time and 480 nanoseconds for the
ADC-510, yielding a minimum of 1.55 MHz conversion rate.
Retriggering of the START CONVERT pulse before EOC goes low
will not initiate a new conversion.
The performance characteristics shown in Table 6 apply over the
operating temperature range and overthe operating power supply
range unless otherwise specified. These characteristics are guaranteed by design.

TABLE 6. PERFORMANCE CHARACTERISTICS AT
DIFFERENT TEMPERATURES
CHARACTERISTIC

VALUE

Conversion Rate (Changing Inputs):
ODC to + lOce (ADC-510)

- 55°G to + 125°C (ADC·S15)
Harmonic Distortion (Below FS)"

1.55 MHz minimum
, .25 MHz minimum

-60db minimum
-60db minimum

+25°C
O°C to + lODe
-55°C to + 125°C

-60db minimum

To fully utilize the dynamic range of the ADC-510/515, the
SHM-45 can be hardware programmed to provide the appropriate output voltage range. Table 7 shows the different input
ranges which can be obtained by selecting the appropriate
SHM-45 gain. See the SHM-45 data sheet for connection
details.

TABLE 7. ADC·SHM INPUT RANGES
VIN Range

o to
o to
-5 to
-10 to
o to
o to

+10
-10
+5
+10
-20
-5

Gain
+1
- 1
-2
-1
-0.5
-2

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

1·59

•

ADC·5tO, ADC·515
+15V

·5V

+5V

ENABLE
BITS 1-5 & O.F

GAIN ADJUST
BIT 1 (MSB)

BIT 2

+lOV REF

BIT 3
RANGE
BlT4

BIT5
INPUT HI
BIT 6

ADC·510
INPUT lOW

BIT 7

81T8

B1T9
BIT 10 (lSB)

no connection

no connection

STAAT CONVERT

OVERFLOW

CONTROL &
DELAY CIRCUIT

ENABLE
SITS 6-10

SiHCONTROl

START CONVERT
AND
HOLD COMMANDS

Figure 4. ADC·SHM Connection Diagram

OFFSET ADJUST

ORDERING INFORMATION
MODEL
ADC·510·BMC
ADC·510BMM
ADC·515·BMC
ADC·515·BMM
ACCESSORIES
Part Number
TP20K

OPERATING
TEMP. RANGE
OOC to + 70°C
-55 DC to + 125°C
ODC to + 70 DC
-55 DC to + 125°C

SEAL
Hermetic
Hermetic
Hermetic
Hermetic

Description
Trimming Potentiometers:
(Two required).

Receptable for PC board mounting can be ordered through
AMP Incorporated, #3·331272·8 (Component Lead Socket), 32
required.
For high reliability version of the ADC·51 0 and ADC·515, con·
tact DATEL.

1-60

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·1194ITEL (508) 339·30001TLX 174388/FAX (508) 339·6356

ADC·5101
Adjustment.Free
8·Bit AID Converter

FEATURES
• 900 Nanoseconds maximum conversion time
• Adjustment-free operation
• Industry standard converter
• -55°C to + 125°C Version
• Wide power supply range

GENERAL DESCRIPTION
DATEL's ADC-5101 is a high-speed,
adjustment-free, 8-bit analog-to-digital
converter. Pin-compatible with industrystandard 5101 converters, these devices
offer high speed and high accuracy with a
full military temperature range version
available.
Using the successive approximation
method, the ADC-51 01 achieves a conversion time of only 900 nanoseconds maximum, making it an ideal choice for high
speed, multiplexed data acquisition systems. Active laser trimming of highly
stable thin-film resistor networks eliminates the need for external gain or offset
adjustments. Overall full-scale absolute
accuracy is only ± % LSB at + 25°C and
only ± 2 LSB over the full military
operating temperature range.

BIPOLAR
OFFSET

REF

our

ANALOG
GND

DIGITAL
GND

ANALOG
INPUT
ANALOG
INPUT

SERIAL EO C
OUTPUT

1

2
MSB

3

4

5

6

7

BIT NO

PARALLEL DATA

Output coding is straight binary for
unipolar operation and offset binary for
bipolar operations with both parallel and
serial outputs brought out. Digital outputs
are TTL-compatible and can drive 5 TTL
loads. Nine analog input voltage ranges
are programmable by external pin
connection.

La,""

o 150MIN
13,81

-I

I

I

r --.--

J

,------

I

KOVAR
112

"'" models require ± 15V dc and + 5V dc
for operation and are packaged ina
24-pin, hermetically sealed ceramic
Jackage.

D.190 (4,9) MAX

0010",0018

I

13 I

1

1200

11 SPACES
I

BOTTOM

I

V lE W

DOT ON TOP
REFERENCES
PIN 1

,-o_,__

our

I

MAX-----.I
(20,3~

1~

CLOCK IN

INPUT/OUTPUT CONNECTIONS

MECHANICAL DIMENSIONS
INCHES(MM)
24·PIN CERAMIC

The ADC-5101H is specified for operation
over the full military operating temperature
range of -55°C to +125°C. Other models
are specified for operation over the commercial OOC to + 70°C operating temperature.

8

lS8

'---

4_:.....
_ _2_

PIN FUNCTION

1 SERIAL DATA OUT

13

- 15V POWER

2 BIT 4 OUT

14

REF. OUT

3

BIT 3 OUT

15

N/C

4

BIT 2 OUT

16

+ 15V POWER

17

BIT 8 OUT (LSB)

5 BIT 1 OUT (MSB)

+ 5V POWER

AT0100

6

18

BIT 7 OUT

EA 12,51

7 BIPOLAR OFF.

19

BIT6 OUT

8 SUM JUNCTION

LJ~"

1_"

1

PIN FUNCTION

0100
12,51

20

BIT 5 OUT

BIPOLAR OFF.

21

E.O.C. (STATUS)

10 ANALOG GND.

22

DIGITAL GND.

11

ANALOG INPUT

23

CLOCK INPUT

12 ANALOG INPUT

24

START CONVERT

9

NOTE: PINS HAVE 0,025 INCH STANDOFF FROM CASE. ±O.Ol"

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-61

ADC-5101
PHYSICAL/ENVIRONMENTAL

ABSOLUTE MAXIMUM RATINGS
AnalogSupply .•••••.....•.•••....•....•
Logic Supply •...•.....................•.
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . • ..
Digita"nputs ..•...........•.•.•........•

±0.5V de to ± 17V de
-0.5V de to + 7V de
± 25V de
- 0.5V de to + 5.5V de

FUNCTIONAL SPECIFICATIONS

Operating Temp.
Range,
AOC-5101 ..... OOC to + 70°C
ADC-5101H •••. - 55°C to + 125°C
Storage Temp.
Range ........ -65°C to + 150°C
Package Type ... 24 pin hermetically
sealed ceramic

Typical at + 25°C, ± 15V dc and + 5V dc supplies, unless otherwise noted.
FOOTNOTES:

INPUTS
Analog Input Ranges, unipolar ............. 0 to - 5V dc, 0 to - 10V dc, 0 to - 20V dc
o to + 5V dc, 0 to + 10V dc, 0 to + 20V de
bipolar. . . . . . .. .. .. .. ± 2.5V dc, ±5V dc, ± 10V dc
Input Impedance, 5V range ............... 1.5 kll
10V range ...•....••..... 3.0 kll
20V range ............... 6.0 kll
Input Logic Levels, Logic" 1 " , min. . • . . . • • .. + 2.0V
Logic "0", max ......... + O.BV
Start Conversion .................•....... Negative going pulse with duration of 25
nsec. min. Loading;2 2 TTL loads
Clock Input, Pulse width high, min .......... 20 nsec.
Pulse width low, min .......•... 46 nsec.
OUTPUTS

1. Converter will reset on the first edge of the clock
after START CONVERT goes low and will convert the MSB on the next rising edge of the
clock. If the START CONVERT is held low, the
converter will be reset but will not convert the
MSB until the first rising edge of clock after the
START CONVERT returns high.
2. One TIL load is defined as 40 p.A at logic "1"
and - 1.6 mA at Logic "0".
3. Clock inpulloading is 1 TIL load.
4. At Ihe end of the conversion, the E.O.C. signal
will remain low until the converter is reset. The
parallel data is valid for the entire time the
E.O.C. signal is low.
5. Absolute accuracy includes offset, gain, linearity. and all other errors. See Technical Note 3.
6. FSR is full-scale range.

Parallel Output Data .••.•.......•...•....• 8 parallel lines of data held until next conversion command.
Outpu~ ~?~i,c L~vels

LogiC 1 ,min •........................
Logic "0", max.
Fanout .••••....•....•••...............•
Coding, unipolar .........................
bipolar ....•••.......••..........
Serial Output Data ....••.....•...........

+2AV
+OAV
5 TTL loads
Straight binary
Offset binary
NRZ successive decision pulses out, MSB
first, at the clock frequency.
.
End of Conversion (E.O.C.)4 .•....•........ Conversion Status Signal. Output is high
during reset and conversion, low when conversion is complete
Reference Output Voltage .........•.....•. -6.2V

.......................

PERFORMANCE
Resolution ..............................
Conversion Time, max • . . . . . . • . . . . . . . . . . . .
Nonlinearity max •........................
Differential Nonlinearity, max ...........••..
Absolute Accuracy, max.- ....••.....•.....
Absolute Accuracy vs. temperature
Oto + 70°C, max......•.............
-55 to + 125°C, max . .•............•...
Reference Output Tempco .................
Power Supply Rejection
Positive Supply ........................
Negative Supply ..............••.....•.
L09iCSU~IY ..........................
No Missing odes •....••.....•...........

B Bits
900 nsec. max.
±v. LSB
±v. LSB
±v. LSB
+1 LSB
±2 LSB
5 ppm/DC typ., 20 ppm/DC max.
± 0.002% FSR6/% Supply
± 0.002% FSR/% Supply
±0.01% FSR/% Supply
Over operating temperature range

POWER REQUIREMENTS
Analog Supply, Pin 16 ............•..•....
Pin 13 ....................
Logic Supply, Pin 6 .......................
Power Dissipation, max . .... •.•.......•...

1-62

+ 10V dc to + 16V dc at 35 mA max.
-IOV dc to -16V dc at 35 mA max.
+5V dc ±0.25V de at 100 mA max.
1.2W

TECHNICAL NOTES
1. The use of good high frequency circuit
board layout techniques is required for
optimum performance. The analog
common (Pin 10) and digital common
(Pin 22) are not connected internally
and therefore should be connected externally as close to the package as
possible. For best results, this common
connection should be a large ground
plane running under the device
package.
2. Both analog and digital supplies shoulc
be bypassed to ground with 1.0 I'F electrolytic capacitors in parallel with 0.1 I'F
disc ceramic capacitors. Bypass capac'
itors should be located directly adjacen'
to, or on, each supply pin.
3. The absolute accuracy error of an A/[
converter is defined as the differenc~
between the theoretical analog inpu
voltage required to produce a givel
digital output and the unadjusted ana
log input voltage actually required tl
produce that same code. Because thi
error is measured and specified withol
adjustment, it includes all factors th~
may effect the devices accuracy at th
point of measurement: offset erro
linearity error, gain error, and no is
error.
4. The ADC-5101 should be driven frol
low impedance sources capable of hig
frequency current variations. DATEL
AM-452, a wide bandwidth, fast se
tling, monolithic operational amplifier
recommended for use as a drivir
amplifier.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-S101
TIMING DIAGRAM

CLOCK

~6~~ERT~~

______

~1
r-------------------------------------~I~I-----------------------

~
~

MSB

BIT
2

r-------------------------------~I~I------------------------

~~'-0'-0~~~------------------------------------------~I~I-------.L_____~~
LSB

I

E.O.C'

L

II

L-----~~----~----~I~l------~------~~

SERIAL'
OUTPUT

FOOTNOTES:
1. The converter is reset by holding the START CONVERT low
during a low to high clock transition. The START CONVERT
must be low for a minimum of 25 nanoseconds prior to the
clock transition. After the START is set high, the conversion
will begin on the next rising clock edge. The START CONVERT may be set low at any time during a conversion to
reset and begin again.

2. At the end of the conversion, the E.O.C. will remain low until
the converter is reset. The parallel data is valid for the entire
time the E.O.C. is low.
3. The serial output is non-return to zero.

OUTPUT CODING AND RANGE SELECTION

I
I
I

DIGITAL
OUTPUT
0000
0000
0111
1000

0000
0001
1111
0000

1111 1110
11111111

ANALOG INPUT-UNIPOLAR RANGES
o TO -5V

o TO -10V

o TO -20V

O.OOOV
-O.019V

O.OOOV
-0.039V
-4.961V
- 5.000V

a.OODV
-D.07av
-9.922V
-lO.DOOV
-19.844V
-19.922V

-2.481V
-2.500V
-4.961V
-4.981V

-9.922V
-9.961V

o TO

+9.961V
+9.922V

+ 2.481 V

+4.961V

aTO +20V
+ 19.922V
+ 19.844V
+ 10.00DV
+9.922V

+O.019V

+O.039V

+O.07BV

BOTTOM

I

VIEW

I

EFERENCES

+10V

+s.ooov

a.ooov

DIGITAL
OUTPUT

24~

IN 1

THIS BASIC GROUND PLANE LAYOUT SHOULD BE MODIFIED BEFORE
IMPLEMENTATION TO INCLUDE UNUSED ANALOG INPUTS.

ANALOG INPUT ±2.5V

BIPOLAR RANGES

±5.0V

0000 0000
0000 0001

+2.500V
+2.481V

0111 1111
1000 0000

+O.019V
o.OOOV
-2.461V
-2.481V

1111 1110
11111111

a.ooov

+s.oov
+4.961V
+O.039V
O.OOOV
-4.922V

-4.961V

±10.0V

+ lO.aoov
+9.922V
+O.078V
O.OOOV
-9.B44V
-9.922V

INPUT RANGE SELECTION

13 I

I

OTONTOP

+5V

O.OOOV

BASIC GROUND PLANE LAYOUT

~12

o TO

+4.981V
+4.961V
+2.500V

INPUT
VOLTAGE RANGE
o to -5V
o to -10V
o to -20V
o to +5V
Oto +10V
o to +20V
±2.5V
±5V
+10V

CONNECT
ANALOG
INPUT
TO PIN
11
11
12
11
11
12
11
11
12

CONNECT
PIN 8
TO PIN
12

-

CONNECT
PIN 10
TO PIN
7,9
7,9
7,9

7,9,12
7,9
7,9
9,12
9
9

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

--

-

-

7
7
7

1-63

ADC-S101
CLOCK>-_ _..
INPUT

ADC·5101
BIT N

~~

+ 1

ANALOG
INPUT

~~
CONVERT

IC1 SN7400N

When less than 8·bit resolution is required, the ADC·5101 may
be operated at higher conversion speeds by truncating the con·
version when the desired number of bits have been converted.
Connect the converter as shown in the logic diagram. The bit
output used to drive gate "A" should be one more than the
number of bits to be converted; for example, for 6 bits resolu·
tion, connect this gate to the bit 7 output.

QUAD

NAND

GATE

MAXIMUM CONVERSION SPEEDS
BITS
7
6
5
4

CONVERSION SPEED
750 nanoseconds
650 nanoseconds
500 nanoseconds
400 nanoseconds

ORDERING INFORMATION
MODEL NO.

OPERATING
TEMP. RANGE

ADC-5101
ADC-5101H

O°C to + 70°C
-55°C to + 125°C

For military versions compliant to MIL-STD-883, contact
DATEL.

1-64

DATEL. Inc. 11 Cabot Boulevard. Mansfield. MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-S11
12-Bit, High-Speed,
Low-Power AID Converter
I

FEATURES

III

12-Bit resolution
1.0 Microsecond maximum conversion time
Low-power, 925 milliwatts
Three-state output buffers
Functionally complete
Small 24-pin DIP
GENERAL DESCRIPTION
DATEL's ADC-511 uses an advanced design to provide a high-speed, functionally
complete 12-bit A/D converter in a small
24-pin DIP. The ADC-511 delivers a conversion speed of 1 microsecond while
consuming only 925 milliwatts of power.
Manufactured using thin- and thick-film hybrid technology, the ADC-511 's exclusive
performance is based upon a digitallycorrected subranging architecture.
DATEL further enhances this technology
by using a proprietary custom chip and
unique laser trimming schemes.
Functionally complete, the ADC-511 contains an internal clock, three-state outputs
and an internal reference. The internal
reference can supply +1 OV at 1.5 milliamps externally. System errors or small initial errors can be adjusted to zero using
external circuitry.

Figure 1.

ADC-511 Simplified Block Diagram

The ADC-511 features two pin programmable analog input ranges: 0 to +1OV, and
±5V dc. The input impedance is specified
at 2.0 Kohms minimum, reducing stringent
drive requirements. Other specifications
include no missing codes over temperature, a maximum gain tempco of +35 ppm/
°C and a maximum differential linearity
tempco of +2.5 ppm/ DC.
All digital inputs and three-state outputs
are TTL and CMOS compatible. Output
coding can be in straight binary/ offset binary or complementary binary/
complementary offset binary by using the
CaMP BIN pin.
Power required is ±15V dc and +5V dc.
Models are available in the commercial 0 °C
to +70 °C and military -55°C to + 125 °C operating temperature ranges.
For information on versions with high reliability screening, contact DATEL.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-65

ADC-Sl1
ABSOLUTE MAXIMUM RATINGS
PARAMETERS

LIMITS

+15V Supply (Pin 22)
-15V Supply (Pin 24)
+5V Supply(Pin 13)
Digital inputs
(Pins 16, 17, and 18)
Analog input
Lead temp. (10 sec.)

UNITS

Oto+18
oto -18
-0.5 to +7
-0.3 to +7

Volts dc
Volts dc
Volts dc
Volts dc

-25 to +25
300

Volts dc
°Cmax.

FUNCTIONAL SPECIFICATIONS
The following specifications apply over the operating temperature range and power supply range unless otherwise indicated.
INPUTS

MIN.

TYP.

Analog Signal Range
(See Table 5 also)

-

o to+10

Input Impedance
Resistance
Capacitance

2

2.5

2.0

Logic Levels:
Logic 1
Logic 0
Logic Loading:
Logic 1
Logic 0

-

MAX.

-

UNITS

-

Volts
Volts

-

50

KOhms
pF

-

0.8

Volts
Volts

±5

-

Logic Loading:
Logic 1
Logic 0
Internal Reference:
+Voltage, +25° C
Tempco
External current

2.5
-100

!,A
!,A

Output Coding:
(Pin 18 High)
(Pin 18 Low)

12

-

-

Bits

2.4

-

-

0.4

Volts
Volts

-

-

-160
6.4

!,A
mA

9.98

10
±5
-

10.02
±30
1.5

Volts dc
ppm/oC
mA

-

MIN.

TYP.

Full·Scale Absolute
Accuracy
+25°C
o °C to +70 °C
-55°C to +125 °C

-

±3
±4
±8

±7
±13
±28

LSB
LSB
LSB

Unipolar Zero Error

-

±1

±3

LSB

Unipolar Zero Tempco

-

±13

±25

Bipolar Zero Error

-

(fJ

MAX. UNITS

ppm/oC

-

±1

±3

LSB

Bipolar Zero Tempco

-

±2

±5

ppm/oC

Bipolar Offset Error

-

±2

±4

LSB

Bipolar Offset Tempco

-

±17.5

±35

ppml°C

Gain Error

-

±2

±4

LSB

Gain Error Tempco

-

±17.5

±35

ppm/oC

Conversion Time
+25°C
o OCto +70 °C
-55 OCto +125 °C

-

-

1.0
1.0
1.15

!,Sec.
!,Sec.
!,Sec.

(fJ

(fJ

(fJ

No missing codes
(For 12 binary bits)

Guaranteed over operating temp. range

POWER
REQUIREMENTS

OUTPUTS
Resolution
Logic Levels:
Logic 1
Logic 0

PERFORMANCE

Straight binary/Offset binary
Complementary binary
Complementary offset binary

Power Supply Range
+ 15V dc Supply
-15V dc Supply
+5V dc Supply

+14.25
-14.25
+4.75

+15
-15
+5

+15.75
-15.75
+5.25

Volts dc
Volts dc
Volts dc

-

+20
-20
+65

+25
-28
+75

mA
mA
mA

Power Dissipation

-

925

1200

rrW

Supply Rejection

-

-

±0.01

%FSR/%V

Operating Temperature
Range
-MCModels
-MMModels

0
-55

-

-

+70
+125

°C
°C

Storage Temperature
Range

-65

-

+150

°C

Supply Current
+15V Supply
-15V Supply
+5V Supply'

PHYSICALI
ENVIRONMENTAL

PERFORMANCE
Integral Nonlinearity
+25°C
o°C to +70 °C
-55°C to +125 °C
Integral Nonlinearity
Tempco
Differential Nonlinearity
+25°C
o °Cto+70°C
-55°C to +125 °C

-

±1/2
±1/2
-

±3/4
±3/4
±3

LSB
LSB
LSB

±3

±8

ppm/oC

±1/2
±1/2

±3/4
±3/4
±1

LSB
LSB
LSB

±2.5

ppm/oC

Package Type
Pin Type
Weight

24-pin hermetically sealed ceramic DIP
0.010 x 0.018 inch Kovar
0.42(12)oz.(gram)

• + 5V power usage at 1 TIL logic loading per data output bit.

ill

Specifications cited are at +25 °C. See Techical Note 1 for further information.

APPLICATIONS
High-speed Data Acquisition Systems
Vibration and Resonance/transient Analysis
Medical Imaging and Scanning

Differential Nonlinearity
Tempco
1-66

Spectrum and Noise Analyzers
Radar, Sonar, and Video Processing Systems

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-S11
TECHNICAL NOTES

INPUT CONNECTIONS

1. Applications unaffected by endpoint errors or those that remove them through software will use the typical connections
shown in Figure 2. The optional external circuitry of Figure 4
removes system errors or helps adjust the small initial errors of
the ADC-511 to zero. The external adjustment circuit has no affect on the throughput rate. Table 1 shows how to select the
input range.

Table
INPUT VOLTAGE
RANGE

1.

Input Connections

INPUT
PIN

JUMPER THESE
PINS:

19
19

Pin 20 to GROUND
Pin 20 to Pin 21

Oto +10V dc
±5Vdc

2. Additional input ranges are available by using optional external adjustment circuitry. Refer to Figure 4 and Table 5.
3. Rated performance requires using good high frequency circuit board layout techniques. The analog and digital grounds
are not connected internally. Avoid ground-related problems
by connecting the digital and analog grounds to one point. the
ground plane beneath the converter (versus at the power supply terminals when the power supplies are located some distance from the ground plane). Due to the inductance and resistance of the power supply return paths, return the analog and
digital ground separately to the power supplies. This prevents
contamination of the analog ground by noisy digital ground currents.
4. Bypass the analog and digital supplies and the + 10V reference (pin 21) to ground with a 4.7 flF, 25V tantalum electrolytic
capacitor in parallel with a 0.1 flF ceramic capacitor. Bypass the
+ 10V reference (pin 21) to analog ground (pin 23).
5. Obtain straight binary/offset binary output coding by tying
COMP BIN (pin 18) to +5V dc or leaving it open. The device
has an internal pull-up resistor on this pin. To obtain complementary binary or complementary offset binary output coding,
tie the COMP BIN (pin 18) to ground. The complementary signal is compatible to CMOSITTL logic levels for those users desiring logic control of this function.
6. To obtain Three-State outputs, connect ENABLE (pin 17) to
a logic "0" (low). Otherwise, connect ENABLE (pin 17) to a logic "1" (high).
+ l:N

TIMING
Figure 3 shows the relationship between the various input signals. The timing shown in Table 2 applies over the operating
temperature range and over the operating power supply
range. These times are guaranteed by design.
Table 2. Signal Timing Summary
SIGNAL

DURATION IN
NANOSECONDS

Start Convert
Pulse Width

200 nSec minimum

Analog Input Settling Time

600 nSec minimum

Start Convert Low to EOC
High Propagation Delay

35 nSec maximum

EOC Low to Previous
Output Data Invalid

1320 nSec minimum

Data Valid After EOC
Goes Low

20 nSec maximum

Enable to Output Data Valid
Propagation Delay

10 nSec maximum

- 15V

+ !'iV

ANALOG
INPUT

10

9
8

START
CONVERT

l--C:--2~!-

---- -----?:

I

I

21

~

I

"

_____::

BIPOLAR
I
OPERATION

21

To-htF
~

2
15

BIT 12
EOC

5

I;

I

BIT
BIT
BIT
BIT
BIT
BIT
BIT
BIT

ADC-511

UNIPOLAR

OPE:RATION

&4_7~F

BIT 1 (MSB)
BIT 2
BIT 3

4
5
6
7
8
9
10
11

ENABLE(I-121

I~------------I
Figure 2. Typical Input Connections for the ADC-S11.

L __________1

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

1-67

ADC-S11
Temperature
Conversion
Time(T1)
ANALOG
INPUT

o to

+70 C

-55 C to +125 C

1.0~Sec.

1.15

~Sec.

~-----~---------------------------I
I

1-4----600 nSec .....,.J
I
minimum
I

I

EOC

I

~_2_00_n_se_c_m_'_nim_u_m_ _ _ _ _ _ _ __

START
CONVERT

I

:

I

I

I

' : ' - - T 1 maximum

---i --.: F
I

i
OUTPUT
DATA

DATA INVALID

20 nSec minimum
35 nSec maximum

t:' 20 nSec maximum

I><1XIDATA N VALID
10 nSec

maXlll1Utn

~Enabled

Data N Valid

NOTE NOT DRAWN TO SCALE

Figure 3.

ADC-511 Timing Diagram

THEORY OF OPERATION
The ADC-511 employs a subranging architecture with digital
error correction. Also known as a two-step method of conversion, this technique uses 7-bits of a single flash converter in
the conversion process twice to yield a final resolution of 12
bits. Refer to the connection diagram, block diagram, and timing diagram as needed.
The ADC-511 requires a maximum of 600 nanoseconds for
the input signal to settle before starting a conversion. Upon
conversion, switch S1 of the ADC closes and S2 opens. The
input, having been configured for the appropriate range, is
buffered and then digitized to 7-bits by the flash ADC to determine the seven most significant bits. The seven bits of
data are then stored in a register and provided to the input of
a 7-bit digital-to-analog converter. The DAC has 13 bits of linearity.
The first pass finished, S2 closes and S1 opens. The output
of the DAC is then subtracted from the analog input. This voltage difference is amplified and converted by the 7 -bit ADC.
The result of this second conversion is then latched to determine the least 7 significant bits. The outputs from the two registers are then added by the digital correction logic to produce
a 12-bit word. EOC goes low, indicating the conversion is
complete, and the output passes to the three-state output
buffers.

The performance characteristics shown in Table 3 apply over
the operating temperature range and over the operating power supply range unless otherwise specified. These characteristics are guaranteed by design.

Table 3.

Characteristic
Conversion Rate (Changing Inputs):
+25°C
O°Cto +70 °C
-55°C to +125 °C
Harmonic Distortion (Below FS)
+25°C
o°C to +70 °C
-55°C to +125 °C

The ADC-511 's conversion rate is based upon 600 nanoseconds for analog input settling time and a 1 microsecond conversion time, yielding a minimum of 600 KHz conversion rate
(changing inputs, AID 0!!!Yl Retriggering of the START
CONVERT pulse before EOC goes low will not initiate a new
conversion.
1-68

Value
600 KHz minimum
600 KHz minimum
575 KHz minimum
-72 dB minimum
-72 dB minimum
-65 dB minimum

Table 4a. Zero and Gain Adjust, Unipolar Operation
UNIPOLAR FSR ZERO ADJUST GAIN ADJUST
+ 1/2 LSB
+FS - 1 1/2 LSB
Oto+10Vdc

Data from the conversion is valid and capable of being latched
20 nanoseconds after the falling edge of EOC and remains
valid for 1300 nanoseconds. Data from the new conversion is
valid a maximum of 20 nanoseconds after the next EOC low
transition. There is a 10 nanosecond maximum delay after the
three-state output buffers are enabled. before the data is valid
at the device output.

Performance vs. Temperature

+1.22mV dc

+9.9963Vdc

Table 4b. Zero and Gain Adjust, Bipolar Operation
BIPOLAR FSR
±5Vdc

ZERO ADJUST
o +1/2 LSB
+1.22 mV dc

GAIN ADJUST
+FS -1 1/2 LSB
+4.9963Vdc

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-S11
CALIBRATION

Table 5. Input Ranges
(using external calibration)

Remove system errors or the small initial errors by adjusting
the zero and full-scale adjustment potentiometers of the usersupplied circuit shown in Figure 4. Connect this circuit to the
ADC-511's ANALOG INPUT (pin 19). Apply power and other
connections as shown in Figure 2 .

R1

INPUT RANGE

a to +1OV,+5V
a to +5V, ±2.5V
a to +2.5V,+ 1.25V

Unit

R2
2
6
14

2
2
2

KOhms
KOhms
KOhms

Procedure
1. Refer to Table 1 for the appropriate full-scale input range
(FSR). The data outputs should be connected to LED's to
observe the resulting data values. Apply a pulse of 200 nanoseconds minimum to the START CONVERT input (pin 16) at a
rate of 250 KHz. This rate is chosen to reduce flicker if LED's
are used on the outputs for calibration purposes.

For bipolar operation, adjust the potentiometer such that
the code flickers equally between 1000 0000 0000 and
1000 0000 0001 with the COMP BIN tied high or between
0111 1111 1111 and 0111 1111 1110 with COMP BIN tied
low.

2. Zero Adjustments:

3. Full-Scale Adjustment:

Apply a preCision voltage reference source between the amplifier's signal input and analog ground. Use a very low-noise
signal source for accurate calibration.

Set the output of the voltage reference used in step 2 to the
value shown in the Tables 4a and 4b for the unipolar or
bipolar gain adjustment (+F.S. -1 1/2 LSB) for the
appropriate FSR. Adjust the gain trimming potentiometer so
that the output code flickers egually between 1111 1111
1110 and 1111 1111 1111 for COMP BIN (pin 18) tied high
or between 0000 0000 0001 and 0000 0000 0000 for
COMP BIN tied low.

Adjust the output of the reference source per Tables 4a
and 4b for the unipolar zero adjustment (+ 1/2 LSB) or the bipolar zero adjustment (zero + 112 LSB) for the appropriate
full-scale range. For unipolar operation, adjust the zero trimming potentiometer so that the output code flickers equally
between 0000 0000 0000 and 0000 0000 0001 with the
COMP BIN (pin 18) tied high or between 1111 1111 1111
and 1111 1111 1110 with COMP BIN tied low.
Table 6.

To confirm proper operation of the device, vary the precision reference voltage source to obtain the output coding listed in Tables
5 and 6.

Output Coding for Uniplar Operation

UNIPOLAR
SCALE

INPUT RANGE

o to
+FS - 1 LSB
7/8 FS
3/4 FS
1/2 FS
1/4 FS
1/8 FS
1 LSB
0

Table 7.
BIPOLAR
SCALE

+FS - 1 LSB
+3/4 FS
+1/2 FS
0
-1/2 FS
-3/4 FS
-FS + 1 LSB
-FS

OUTPUT CODING
Straight Binary
Complementary
Straight Binary

+10V

MSB

+9.9976V
+B.7500V
+7.5000V
+5.0000V
+2.5000V
+1.2500V
+0.0024V
O.OOOOV

1111
1110
1100
1000
0100
0010
0000
0000

1111
0000
0000
0000
0000
0000
0000
0000

LSB

MSB

1111
0000
0000
0000
0000
0000
0001
0000

0000
0001
0011
0111
1011
1101
1111
1111

LSB
0000
1111
1111
1111
1111
1111
1111
1111

0000
1111
1111
1111
1111
1111
1110
1111

R2

+ 15V

Rl

SIGNAL
INPUT

TO PIN 19
ADC-S11

Output Coding for Bipolar Operation

INPUT RANGE

OUTPUT CODING
Offset Binary
Complementary
Offset Binary

± 5V

MSB

+4.9976V
+3.7500V
+2.5000V
O.OOOOV
-2.5000V
-3.7500V
-4.9976V
-5.0000V

1111
1110
1100
1000
0100
0010
0000
0000

1111
0000
0000
0000
0000
0000
0000
0000

LSB

LSB

MSB

1111
0000
0000
0000
0000
0000
0001
0000

0000 0000 0000
0001 1111 1111
00 11 1111 1111
0111 1111 1111
101111111111
110111111111
1111 1111 1110
1111 1111 1111

Figure 4. Optional
Calibration Circuit

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-69

•

ADC-S11
Combining the ADC-511 with Datel's SHM-45
Sample-and-Hold Device

mode would be initiated upon EOC going low.
Upon completion of the SHM-45's acquisition mode (200 nanoseconds maximum), there is still an additional 400 nanoseconds required to meet the analog input settling time of the
ADC-511. The SHM-45 requires 100 nanoseconds for hold
mode settling. The user would adapt the START CONVERT
pulse width to meet the additional time required for analog input settling. There is a 20 nanosecond minimum delay from
START CONVERT low to EOC high. Therefore, if the START
CONVERT pulse goes high as the HOLD COMMAND goes
low, the start convert pulse width would be 380 nanoseconds
wide.

The application shown in Figure 6 uses the ADC-511 in conjunction with DATEL's SHM-45, a 0.01% accurate, 200 nanosecond acquisition time sample-hold. This configuration
obtains a 600 KHz (minimum) throughput rate. An optional
end-point calibration circuit may also be used. The optional
calibration circuit has no effect on the throughput rate.
This capability is based upon the sample-hold acquisition
and hold mode settling times occurring during the ADC511 's analog input settling time period of 600 nanoseconds.
This timing relationship is shown in Figure 5. The optional calibration circuit would also use this time period in settling to the
required accuracy before the ADC-511 determines the seven
most significant bits of data.

As long as the 600 nanosecond analog input settling time is
met, the time in the acquisition or hold mode could be varied
as long as the minimum times are observed.

The SHM-45 is put into the sample mode when the HOLD
COMMAND is high. For continuous conversions, the sample

ANALOG

INPUT

~
I
6~OO~o~Se~c-'1- - - - - - - - - - - - - - - - - - - - - - - - - - - ..-- minimum-I

START
CONVERT

_

~..::20::.:0..::oS::.:e::..c"'mi:.::.mm.:..;c:...m___________________
I

I

EOC - :

I I
I 1---

T1 maximum

~

I..___________

I

I

I

I

~Old Mode Sewing Time

t4 ACQUISITION TIME

HOLD COMMAND ---.

~
t:
I

g~;:UT

I

1

J ~ ~;~ ~~:~ ~~~ii:~:1
nSec maximum
1300 nSec minimum--l

1)(1

rx1>;

13

-15VSUPPLY

14

ANALOG INPUT

2

+5V SUPPLY

3

SERIAL OUTPUT

15

4

BIT 6 OUT

16

BIT 12 OUT (LSB)

5

BIT 5 OUT

17

BJT 11 OUT

•
1

P,N

STAAT CONVERT

7

,,
,

FUNCTION

1

6

17

,16

Models are available specified over the
full military operating temperature range
of -55 to + 125°C and commercial, O°C to
+ 70°, operating temperature ranges.

SERIAL
OUTPUT

-6.4V

:

DATEL's ADC-5210 Series are high performance, hybrid, 12-bit successive approximation AID converters. These devices combine high speed with extreme
accuracy to provide the best possible performance in systems that require low
power consumption, adjustment free operation, and miniature size.

E.o,C
(STATUS)

+5V
SUPPLY

9

BrT 4 OUT

~15VSUPPlY

18

BIT 10 OUT

BIT 3 OUT

19

BIT 9 OUT

BIT 2 OUT

20

BIT 8 OUT

BIT lOUT (MSB)

21

BIT 7 OUT

10

NO CONNECTION

22

E.O.C. (STATUS)

11

ANALOG GROUND

23

DIGITAL GROUND

12

REF. IN/OUr

24

CLOCK INPUT

'THE ADC-5211, 5212, AND 5216 HAVE AN
INTERNAL REFERENCE. THE ADC-5214 AND 5215
REQUIRE AN EXTERNAL REFERENCE.

0900
(22.9)
NOTE' PINS HAVE 0,025 INCH STAND OFF FROM CASE, ± 001

DATEL. Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-77

ADC-S210 SERIES
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range:
ADC-521X ......•....•...............
ADC-521XH .................•........
Storage Temperature Range ............. .
Positive Supply, Pin 15 ................. .
Negative Supply, Pin 13 ................. .
Logic Supply, Pin 2 ..................... .
Analog Input, Pin 14 .................... .
Digital Inputs, Pins 1, 24 ................. .
Digital Outputs .....•...................
Reference Input' ....................... .

DOC to + 7DoC
-55°C 10 +125°C
-65°C to + 15DoC
+18V
-18V
-D.5V to + 7V
25V
-0.5V to +5.5V
Logic Supply
o to -15V

FUNCTIONAL SPECIFICATIONS
Typical at + 25°C, ± 15V dc supplies, VREF = - 1O.OOOV, unless otherwise noted.
ANALOG INPUTS'

MODEL NUMBER'

MODEL NUMBER'

ADC·5211
ADC-5212
ADC-5216

ADC-5214
ADC-5215

Input Range (Input Impedance)
- 5V to + 5V (SKU) ......................
-10V to + 10V (10KU) ...................
Oto +10V(5KU) ......•.................
TRANSFER CHARACTERISTICS

TYPICAL

MAXIMUM

TYPICAL

MAXIMUM

Linearity Error: + 25°C ...................
O°C to + 70°C ........................
-55°Cto +125°C ....................
Differential Linearity Error ................
No Missing Codes .....•.................
Full-scale Absolute Accuracy Error3

±% LSB
±% LSB
± 'h LSB

± 'h LSB
± 'h LSB
±o/. LSB

±% LSB
±% LSB

± V2 LSB
± 'h LSB
±o/. LSB

+25°C ..............................
O°C to + 70°C ........................
-55°Cto+125°C ....................
Zero Error: + 25°C ......................
O°C to + 70°C ........................
- 55°C to + 125°C ....................
Zero Error: ADC-5216
+25°C .....•........................
O°C to + 70°C ........................
-55°Cto +125°C ....................
Gain Error .............................
Gain Drift ..............................
Conversion Times ........•........ , .....

± 'h LSB

Guaranleed over temperature
±0.025%
±0.1%
±D.l%
±0.01%
±0.025%

FSR
FSR
FSR
FSR
FSR

±0.05%
+0.2%
+0.4%
±0-:-025%
±0.05%
±0.05%

-

FSR
FSR
FSR
FSR
FSR
FSR

±0.025%
±0.05%
±0.05%
±0.01%
±0.025%

-

-

13 "sec.

-

FSR
FSR
FSR
FSR
FSR
FSR

-

±0.025%
± 3 ppm/oC

-

±0.025%
± 10 ppm/oC

±0.05%
+0.1%
+0.1%
±0-:-025%
±0.D5%
±0.05%

-

±0.05% FSR
±0.75% FSR
±0.75% FSR

-

FSR
FSR
FSR
FSR
FSR

-

13 "sec.

-

POWER SUPPLIES
Power Supply Range: ± 15V dc supplies ...
+ 5V dc supply ......................
Power Supply Rejection.: + 15V dc supply .
-15V dc supply .....................
Current Drain: + 15V dc supply . . . . . . . . . .
-15V dc supply ............•........
+ 5V dc supply .....•................
± 12V dc, + 5V dc supplies 11 . . . . . . . . . .
- 10V dc reference' ..................
Power Consumption ...................
DIGITAL INPUTS (All Models)
Logic ~e.~e!~: Logic "'" ................
Logic 0 ...........•...•..........
Clock Input:
Pulse Width High ....................
Pulse Width Low ....................
Loading High (VIN = 2.4V) . . . . . . . . . . . . .
Loading Low (VIN = 0.3V) ..............
Frequency .........................
Start Convert Input:
Loading High (VIN = 2.4V) .............
Loading Low (VIN = O.3V) ..............
Set-up Time Start Low to Clock· ..........

1-78

-

-

±0.005% FSR/%V s
±0.01% FSR/%Vs
+9 mA
-23 mA
+35 mA

±3%
±5%
±0.02% FSR/%V s
±0.05% FSR/%V s
28 mA
-35 mA
68 rnA

±0.OD5% FSR/%V s
±0.005% FSR/%V s
+9 mA
-23 mA
+35 rnA

695 mW

lW

-1.5 rnA
695 rnW

-

MINIMUM
2.0V

100 nanoseconds
175 nanoseconds
-

-

-

25 nanoseconds

-

±3%
±5%
±0.01% FSRlVs
±0.01% FSRlVs
28 mA
-35 mA
68 rnA
-2 rnA
800 rnW

-

TYPICAL
-

2~

MAXIMUM
0.8V
-

-

-0.25 rnA
-

20 "A
-0.4 mA
1 MHz

4"A
-0.25 rnA

-0.4 mA

-

40~

-

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-5210 SERIES
DIGITAL OUTPUTS (All Models)
Complementary Straight Binary
Complementary Offset Binary

Logic Coding·: Unipolar range ...........
Bipolar ranges .......•..............
Logic Levels: Logic "1" ................
Logic "0" ................•.........
Outpu~ ~.ri~~ Capability, All Outputs'·:

t~:~,,~,,::::::::::::::::::::::::::

+2AV

8 TIL Loads
2 TIL Loads

+3.6V
+0.15V

-

+0.3V

III

-

I

REFERENCE INPUT/OUTPUT'
Internal Reference: Voltage .............
Accuracy ..........................
Tempco of Drift .......................
Maximum External Current ..............
External Reference: Voltage .............
Loading ...........................

-

-

-6AV
+2%
±5-ppm/ o C

-

-

100 ",A

-

-2 mA

-10.000V

FOOTNOTES:
1. The ADC·5211, 5212, and 5216 include a -6.4V internal reference. The ADC·5214 and 5215 require an external -10.000V reference for specified operation.
2.
3.
4.
5.

6.
7.
S.
9.

Analog input ranges are internally set at the factory.
Absolute Accuracy Error includes offset, gain, linearity and all other errors. See Technical Notes for further information.
FSR stands for Full Scale Range and is equal to the peak voltage of the selected analog input range.
Conversion Time is defined as the width of the converter's STATUS (E.O.C.) pulse. The ADC·5210 Series will meet all specifications with clock frequencies up to
1 MHz. A 1 MHz clock gives a STATUS pulse that is 12 microseconds wide, however, unless careful timing precautions are taken, it will usually take 13
microseconds to update digital output data.
Power Supply rejection is guaranteed over the ± 15V ± 3% range.
The clock may be asymmetrical with minimum positive or negative pulse width.
In order to reset the converter, START CONVERT must be brought low at least 25 nanoseconds prior to a low-to-high ctock transition. See Timing Diagram.
Serial and Parallel output data have the same coding. Serial data is NAZ successive decision pulses out, MSB first, at the clock frequency. Both serial and parallel
output data become valid on the same riSing clock edge. Serial data is valid on subsequent falling edges, and these edges can be used to clock serial data into
receiving registers.
One TTL load is defined as sinking 40 pA with a logic 1 applied and sourcing 1.6 rnA with a logic 0 applied.

10.
11. For ± 12V dc, + 5V dc operation, contact the factory.

TECHNICAL NOTES
1. The use of proper layout and decoupling techniques are required to obtain
rated performance. The ground pins
(pins 11 & 23) are not connected internally, and therefore must be connected
externally as directly as possible. They
should be connected to the system
analog ground, preferably through a
large ground plane underneath the
package. Power supplies should be bypassed to ground at the supply pins
with 1 "F electrolytic capacitors in
parallel with 0.01 F ceramic capacitors.
2. These converters can be made to continuously convert by tying the E.O.C.
output (Pin 22) to the start convert input
(Pin 1). When connected in this manner, the E.O.C. (START CONVERT) will
go low at the end of conversion and the
next rising edge of the clock will reset
the converter and bring the E.O.C.
(START CONVERT) high again. The
MSB will be set on the next riSing clock
edge. The E.O.C. (status) will be low for
approximately one clock period following each conversion.
3. The absolute accuracy error of an A/D
converter is defined as the difference
between the theoretical analog input
voltage required to produce a given
digital output and the unadjusted
analog input voltage actually required
to produce the same code. Because

this error is measured and specified
without adjustment, it includes all factors that may affect the devices accuracy at the pOint of measurement:
offset error, linearity error, gain error,
and noise error.
4. Because of propagation delays, the
LSB of any given conversion may not
be valid until a maximum of 30 nanoseconds after the E.O.C. (status) output has returned low. If the E.O.C. is
used to strobe latches holding output
data, adequate delays must be provided. Gate delays may be employed or
the E.O.C. can be made the input of a
D flip flop whose clock input is the same
as the converter clock. Connected in
this manner, the Q output will change
one clock period after the E.O.C.
changes. If the converter is connected
in the continuous mode, the E.O.C. can
be NORed with the converter clock to
produce a positive strobe pulse y,
period wide, y, period after the E.O.C.
output has gone low. The rising edge of
the pulse can be used to latch data
after each conversion.
5. Applications of these converters that
require the use of sample-hold may be
satisfied by DATEL's SHM-4860, a high
speed hybrid unit featuring a 200
nanosecond acquisition time and
0.01% accuracy.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

1-79

ADC-S210 SERIES
TIMING & CONNECTION
TIMING DIAGRAM

CLOCK

START
CONVERT'

JLJ
LS
~

BIT 1 (MSB)

' I------------------------------------~I~I----------------------

~£--------"

LJr-----------1It----'- - -

~
BIT2

[-

~~~~~--------------------------------------------~Il~------_.

BIT12(LSB)

~

'------>

l~l--------------_,~
E.O.C
(STATUS)'

SERIAL OUT'_ _ _ _ _ _ _ _

~

L -_ _ _ _ _ _

NOTES: 1. The converter is reset by holding the START CONVERT low during a low to high clock transition. The
START CONVERT must be low for a minimum of
25 nanoseconds prior to the clock transition. After
the START is set high, the conversion will begin on
the next rising clock edge. The START CONVERT
may be set low at any time during a conversion to
reset and begin again.

~

______

~ ~II~--------~----~~
__

2. At the end of conversion, the E.O.C. will remain low
until the converter is reset. The parallel data is valid
for the entire time the E.O.C. is low.
3. The serial output is non-return to zero.

POWER SUPPLY DECOUPLING

DIGITAL OUTPUT CODING

PIN20
ANALOG INPUT VOLTAGE
DIGITAL
OUTPUT

1"F
PIN11.230

aTa +10V

:!:.5V

,10V

ADC·5216

ADC-S211, 5214

ADC·S212, 5215

0000 0000 0000
0000 0000 000 1
011111111111

+ 10.aODOV
+ 9.9976V

+ 5.DOODV

t

+ 4,9976V

5.D024V

+ O.D024V

+ 9.9951V
+ O.OO49V

1000 0000 0000
111111111110

+ 5.00DOV
O.OO24V

- 4.9976V

-

111111111111

o.oooov

- 5.0DODV

- la,DOOOV

t-

+

Q,DOODV

~

~

T

T

~+5V

001"F

~GND

5 VOLT POWER SUPPLY

la,DOOOV

I

PIN150

I

~+15V

1J-'F
IO.01j.1F
PIN 11.23 o>---f~-----I~-~ GND

Q,aOODV

1"F

9.9951V

PIN 13 0
~

I001eF

T - - ,. - 15V

15 VOLT POWER SUPPLY

TRIGGERING WITH A POSITIVE EDGE

START
SIGNAL

o

1-80

The ADC-521 a Series AID's may be made to start converting on a positive going edge by employing the circuit shown. The rising edge of the start signal will drive
the output of IC2 low. The converter will reset on the
next rising clock edge. When the converter resets, the
status output (pin 22) goes high, the output of IC1 goes
low; and since the start signal is still high, the output of
IC2 goes high allowing the conversion to continue immediately. The start signal should be brought low
before the conversion is complete.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-S210 SERIES
APPLICATIONS
SERIAL TO PARALLEL CONVERSION

74164

QA

lSB

ADC·5210
SERIAL
OUT

7474

ClK

E.O.C. 2 ; > , > - - - - - _ . , D

o
7400

SHORT CYCLE CONTINUOUS CONVERTING

CLOCK IN

ClK

In many applications, the transmission of the parallel output
data from the ADC-521 0 Series may be impractical. With the circuit shown, data may be sent in serial form and converted to
parallel at the destination. For a 12-bit AID, this conversion can
reduce the number of wires needed for data transmission from
14 to 3.
74164

MSB
QD

IC

= 7400

To continuously convert at N bits, the circuit shown may be
used. The output of bit (N + 1) acts like a status when one converts at N bits. The START CONVERT input is made the AND
function of bit (N + 1) and the STATUS output to prevent the
possibility of a lock up condition at power-on.

SHORT CYCLE OPERATION

EOC

IC 1 SN7400N OUAD NAND GATE

ORDERING INFORMATION
MODEL NO.

If an application requires less than 12 bits
resolution, the ADC-5210 Series may be
truncated to the desired number of bits,
with a proportionate decrease in conversion time, by using the circuit shown. With
this circuit the start convert and E.O.C.
signals function normally.

INPUT
VOlT.RANGE

REFERENCE

OPERATING
TEMP. RANGE

ADC-5211
ADC-5211H

±5V
±5V

Internal
Internal

o to + 70°C
- 55 to + 125°C

ADC-5212
ADC-5212H

±10V
±10V

Internal
Internal

o to + 70°C
- 55 to + 125°C

ADC-5214
ADC-5214H

±5V
±5V

External
External

o to + 70°C
-55to +125°C

ADC-5215
ADC-5215H

±10V
±10V

External
External

o to + 70°C
- 55 to + 125°C

ADC-5216
ADC-5216H

o to
o to

Intern<31
Internal

o to + 70°C
-55 to + 125°C

+ 10V
+ 10V

For military devices compliant to MIL-STD-883, consult the factory.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-81

ADC·7109
12·Bit AID Converter with
Microprocessor Interface
FEATURES
• Parallel or serial bus interface
• 12 Bits with plus sign and overrange
• Differential signal and reference
inputs
• low noise
• low power

GENERAL DESCRIPTION
DATEl's ADC-7109 is a low power, 12-bit
integrating AID converter deSigned to interface directly to 8- or 16-bit ",p data
busses without any external active component requirements. Output data may be
accessed directly under the control of two
byte enable and chip select inputs for
parallel bus interface or data may be
transmitted serially via industry standard
UART in the handshake mode.
The ADC-7109 is completely self contained including a buffer amplifier, integrator, comparator, clock oscillator with
scaling circuit, 12-bit binary counter with
output latches and TTL-compatible threestate output drivers, data bus control and
UART handshake logic.
Important features of the ADC-7109 include a typical input bias current of 1 pA,
less than 1 ",V/oC zero drift, typical input
noise of 15 ",Vpeak-to.peak and a power consumption of only 20 mW. The combination
of ",p compatibility, low cost and high accuracy make the ADC-7109 an ideal
choice for remote data logging applications and true differential analog and
reference inputs allow for measurement of
bridge type transducers.
The ADC-7109 is available for operation
over the commercial, O°C to + 70°C
temperature range and is packaged in a
40-pin plastic DIP.
NOTE: The ADC-7109 is a CMOS device.
However, all the inputs are fully protected
against static discharge and no special
handling precautions are necessary.

COUN-

TER
AND
LATCHES

PUTS

MECHANICAL DIMENSIONS
INCHES (MM)

I·

2.04{) (51,8161

I

1
J8S 3.25
[:::::=::=I-o.0

INPUT/OUTPUT CONNECTIONS

.,.1
2
3
4
5

FUNCTION

DIG. GND.
STATUS

POLARITY
QVERRANGE

BIT 12

6

BIT 11

,

BIT9

7
8

10
11

BIT 10

FUNCTION

MODE
OSCIN
OSCOUT

asc SELECT
BUFOSC
RUN/HOLD
SEND

-Vs

29

AEF OUT

30

BUFFER

BIT 6

BIT3
81T2

17

22
23
24
25
26
27
28

BIT 7

15

18
"20

.,.21

BIT 8

12
13
14
16

1-82

THREE
STATE
OUT-

81T5

BIT4

BIT 1
TEST

lBEN

31
32
33
34
35
36
37
4{)
38

AUTO ZERO
INTEGRATOR

COMMON
-INPUT

+ INPUT
+REF IN
+AEF CAP

-REF CAP

-REF IN

HBEN

CE/LOAO

3'

+Vs

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-7109
POWER REQUIREMENTS

ABSOLUTE MAXIMUM RATINGS
+vs ....... ·· ... · .. · ................ .
-Vs ................................ .
Analog Input Voltage Range' ............ .
Reference Input Voltage Range' ......... .
Oigitallnput Voltage Range (Pins 2-27)2 ... .
Power Dissipation ..................... .

+6.2V
-9V
+Vs to -Vs
+ Vs to - Vs
+Vs +0.3V,
GND -0.3V
500 mW at 70°C

FUNCTIONAL SPECIFICATIONS
Typical at 25·C, ±5V Supplies unless otherwise noted.

Supply Voltage ........................
Supply Current (+ Vo to GND.) max,17 ......
Supply Current( + Vo to - Vo) max,17 .......

±5V de
1.5 mA
1.5 mA

PHVSICAUENVIRONMENTAL
Operating Temperature Range ............
Storage Temperature Range .............
Lead Temperature (soldering 60 sec.) ......
Package ..............................

O°C to + 70°C
-55°C to +125°C
300·C
40 Pin Plastic DIP

ANALOG INPUT CHARACTERISTICS
Type Analog Input ......................
Zero Input Reading, max. (Octal ReadingI' ..
Ratiometric Reading, max. (Octal Reading)'
Input Leakage Current, max. (VIN = OV) ....
Common Mode Rejection Ratio13 ..........
Input Common Mode Voltage Range, min.
max ..

Differential
+0000,
4000,
10 pA
86 dB
- Vs plus 1.5V
+ Vs minus 1.0V

DIGITAL INPUT
Control 1/0 Pull-up Current' ..............
Control 1/0 Loading, max." ...............
Input Voltage Range 7 (Pins 18-21, 26, 27)
High,min ...........
Low,max.
Input Pull-up Current" (Pins 26, 27) .......
(Pins 17, 24) .......
Input Pull-down Current (Pin 21)9 ..........
Mode Input Pulse Width, min. ............

5pA

50 pF
2.5V
1V
5pA

25 pA
5pA

50 nsec .

OUTPUT CHARACTERISTICS
Output Voltage," high min ...............
low max ...............
Output Leakage Current, max. (Pins 3-16)
Reference Output Voltage, min ...........
max.
Oscillator Output Current," high .........
low ..........
Buffered Oscillator Output Current," high
low ..

3.5V at 100 pA
O.4V at 1.6 mA
1pA

-2.4V
-3.2V
1 mA
1.5 mA
2 mA
5mA

PERFORMANCE
Resolution ............................ 12-bits, plus sign and
overrange
± 1 Count
Non-Linearity, max . ....................
Roll-over Error12 .......................
± 1 Count
Noise, peak-to-peak 14 •••••••••••••••••••
15 ~V
1 !"V/oC
Zero Drift, max .........................
5 ppm/oC
Scale Factor Tempco, max." ............
80 ppm/oC
Reference Output Tempco'" .............
FOOTNOTES:

1. Positive or negative input. Input voltage can exceed the supply voltage
provided the input current is limited to 100 /lA.
2. It is recommended that no inputs from sources other than the devices power

supply be applied to the device before its power supply is established, and that
in multiple supply systems, the supply to the device be activated lirst. This will
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.

avoid destructive device latchup.
Vin=O.OV, Fuli·Scale=409.6 mV.
Vin Vrel = 204.8 mV.
Pins 18, 19, 20. Vout= + Vs minus 3V. Mode input at ground.

=

HBEN (Pin 19) LBEN (pin 18).

With respect to ground.
Voul= +Vs minus 3V.
Vout = Ground plus 3V.
Pins 2 through 16, 18, 19 and 20.
Vout=2.5V.
Difference in reading for equal positive and negative inputs near full·scale.
Vcm ± IV, Vin=OV. Full·scale=409.6 mV.
Not exceeded 95% of the time.
Vin=40B.9 mV. External reference tempco=O ppm/oC.
25 kO between + V s and reference output.
Vin =0. Cryslal osciliator 3.58 MHz. Pins 2·21. 25, 26, 27, 29, open.

TECHNICAL NOTES
1. Differential voltages from 1.0V below the positive supply to
1 .5V above the negative supply can be applied to the
device's input. In this range, the system has a typical CMRR
of 86 dB. However, since the integrator also swings with the
common mode voltage, care must be taken to assure that
the integrator output does not saturate. To avoid this, the integrator swing can be reduced to less than the recommended 4V full scale with some loss of accuracy. The integrator output can swing to within 0.3V of either supply
without loss of linearity.
2. The buffer amplifier and integrator have a Class A output
stage with 100 /LA of quiescent current. They supply 20 !"A of
drive current with negligible non-linearity. The integrating
resistor should be large enough to remain in this very linear
region over the input voltage range, but small enough that
undue leakage requirements are not placed on the PC
board. For a full-scale range of 4.096V, 200 kD is optimum;
for 409.6 mV, 20 kD should be used. For other values of fullscale: RINT = V Fs/20/LA.
3. The integrating capacitor should be selected to give the maximum integrator output voltage swing without saturating the
integrator (approximately 0.3V from either supply). The value
for the integrating capacitor is given by the following equation: C'NT = (2048 x TCLOCK) (20 "A)/lntegrator VOUT Swing.
The integrating capacitor should be selected to have low
dielectric absorption to prevent roll-over errors. Many types
of capacitors are adequate for this application, however,
polypropylene capacitors will give undetectable errors up to
+ 70°C.
4. The value of the auto zero capacitors depends upon the requirements of the applications. For example, for a full-scale
voltage range of 409.6 mV, where noise is a major consideration and the integrating resistor is very small, a value of CAZ
twice CINT is optimum. Similarly, for a full-scale range of
4.096V, where recovery is more important than noise, a
value of CAZ equal to half C INT is recommended.
5. The analog input required to generate a full-scale output of
4096 counts is VIN = 2 VREF . Thus, for a normalized scale, a
reference of 2.048V should be used for a 4.096V full-scale,
and 204.8 mV for a 0.4096V full-scale. However, in many applications where the AID is sensing the output from a
transducer, a scale factor other than the unity between the
absolute output voltage to be measured and a desired digital
output will exist. For example, in a weighing system, a fullscale reading may be desired with 0.682V from the
transducer, In this case, rather than dividing the input down
to 409.6 mY, it should be applied directly and a reference
voltage of 0.341V should be used. Values for RINT and CINT
would be 34K and 0.15 /LF.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-83

•

ADC-7109
6. The stability of the reference is a major factor in the overall
absolute accuracy of the converter. It is recommended that
an external high quality reference be used where the ambient temperature is not controlled or where high-accuracy
absolute measurements are being made.

If using the internal reference, REF OUT (Pin 29) should be
connected to - REF IN (Pin 39), and + REF IN should. be
connected to the wiper of a precision trimpot between REF
OUT and + Vs. (See typical connections.)

PIN DESCRIPTION
INPUT/OUTPUT CONNECTION AND DESCRIPTION
PIN
1

FUNCTION

2

DIGITAL GROUND
STATUS

3
4

POLARITY
OVER-RANGE

5
6

Bit 12 (MSB)
Bit 11

7

Bit 10

8
9

Bit 9
Bit 8

10
11

Bit 7
Bit 6

12
13

Bit 5
Bit 4

14
15

Bit 3
Bit 2

16

Bit 1 (LSB)

17

TEST

18

19

20

1-84

LBEN

HBEN

CE/LOAD

DESCRIPTION
Ground return for all digital logic.

PIN

FUNCTION
MODE

Input Low - Direct output mode where
CE/LOAD (Pin 20), HBEN (Pin 19)
and LBEN (Pin 18) act as inputs
directly controlling byte outputs. Input
Pulsed High - Causes immediate entry
into handshake mode.
Input High - Enables CE/LOAD (Pin
20), HBEN (Pin 19) and LBEN (Pin 18)
as outputs, handshake mode will be
entered and will be valid at the end of
conversion.

22
23

OSCIN
OSC OUT

Oscillator Input
Oscillator Output

24

OSC SELECT

Oscillator Select - Input high configures OSC IN, OSC OUT, BUF OSC
OUT as RC oscillator - clock will be
same phase and duty cycle as BUF
OSC OUT.
- Input low configures OSC IN, OSC
OUT for crystal oscillator - clock frequency will be 1158 of frequency at
BUF OSC OUT.

25
26

BUFOSC OUT
RUN/HOLD

27

SEND

Input - Used in handshake mode to indicate ability of an external device to
accept data.
Must be tied high if not used.

28

-Vs

Negative Supply Voltage - Nominally
- 5V with respect to GND (Pin 1).

29

REF OUT

Reference Voltage Output - Nominally, 2.8V down from + Vs (Pin 40).
Buffer Amplifier Output

Output - High during integrate and
deintegrate until data is latched.
- Low when analog section is in AutoZero configuration.
High for Positive Input
High if Overranged

Data Bits. Three-State Output

Input High - Normal Operation.
Input Low - Forces all bit outputs high,
and disables internal clock. When
returned high and 1 clock pulse is input, the counter outputs will enter
negative state. Must be tied high if not
used. Note: This input is used for test
purposes only.
Low Byte Enable - With Mode (Pin 21)
low, and CE/LOAD (Pin 20) low, taking
this pin low activates low order byte
outputs Bl-B8.
High Byte Enable - With Mode (Pin
21) low, and CE/LOAD (Pin 20) low,
taking this pin low activates high order
byte outputs B9-B12, polarity and overrange outputs.
Chip Enable Load - With Mode (Pin
21) low, CE/LOAD serves as a master
output enable. When high, Bl-BI2,
polarity and overrange outputs are
disabled.
- With Mode (Pin 21) high, this pin
serves as a load strobe used in handshake mode.

DESCRIPTION

21

30
31

BUFFER

Buffered Oscillator Output
Input High - Conversions continuously
performed every 8192 clock pulses.
Input Low - Conversion in progress
completed, converter will stop in AutoZero 7 counts before integrate.

Auto-Zero Mode Select

32

AUTO-ZERO
INTEGRATOR

33

COMMON

Analog Common - System is autozeroed to COMMON.

Integrator Output

34

- ANALOG IN

Negative Differential Analog Input

35

+ ANALOG IN

36
37

+ REF IN

Positive Differential Analog Input
Positive-Differential Reference Input

38

- REF CAP

+ REF CAP

39

- REF IN

40

+Vs

Positive Reference Capacitor
Connection
Negative Reference Capacitor
Connection
Negative Differential Reference Input
Positive Supply Voltage - Nominally
+ 5V with respect to GND (Pin 1).

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-7109
TIMING AND CONNECTION
CONVERSION TIMING

TYPICAL CONNECTION
{TEST CIRCUIT)

POLARITY
DETECTED ~

EXT REF

~+V5
IN

INTEGRATOR
OUTPUT

~~,..---

1-.-

-Vs

AUTO.IER0---j_INTEGRATE - - I '

POLARITY

3

IJ-r--'l'IN'--D + IN

OVERRANGE

4

9-'----,,...cc.--o-IN

-

I

~!

i
I

:

AUTO

DEINTEGRATE -------r--!ERO--

I

I

I

MIN

COUNTS

I

0

i
I

4096COUNTS--------J
,MAX
I

t-/~

" :~t~~E:EOcf,~~sX~2
~~~NF,~~T~I~~~

THE CONVERSION PROCESS

7

BIT 9

There are three steps in the conversion process for the
ADC-71 09:

BIT 8

BIT 7

1. Auto Zero
2. Signal Integrate

BIT 6
BIT 5

3. Deintegrate

~----~OGNO

BIT 4

BIT 2

In the auto zero step, the high and low inputs are internally disconnected from the pins and shorted to analog common. At this
pOint, the reference capacitor is charged to the reference
voltage. Then a feedback loop is closed to charge the autozero
capacitor (CAV which compensates for offset voltages in the
buffer amplifier, integrator and comparator. The offset referred
to the input is less than 10 /LV.

25 BUFFERED OSC OUT

8JT 1

RINT :::;

lERO CPlOSSING
,/,"OETECTED

2048
I
FIXED
I__ · ___ CQUNTS--------t-------1I_ _ - f - 2048

NUMBER OF COUNTS TO ZEAO CROSSING
PROPORTIONAL TO V,

*

•

(....

hI" LI1JUL
J~ ~ UU1fJU
I'

IN

1

BIT 10

lERO CROSSING
OCCURS

---- I ~ ~/

20K FOR O.2V REF

** IF USING 409-6 mV SCALE AND HIGH CMV
EXISTS, USE

200K FOR 2.0V REF

lO~F

In the signal integrate step, the auto-zero loop is opened and the
inputs are connected (internally) back to the external pins. At
this point, the differential signal between the inputs is integrated
for a fixed time of 2048 clock periods. Upon completion of this
phase, the polarity of the integrated signal is determined.

REF. CAP

NOTES: INPUTS SHOULD SWING FROM GNO TO + VS FOR MINIMUM POWER
CONSUMPTION. TIL DRIVEN INPUT SHOULD HAVE 3·5K1! PULL·UP RESISTORS ADDED FOR MAXIMUM NOISE IMMUNITY.

The deintegrate step is the final phase. Here, the negative input
is connected to analog common and the positive input is connected across the previously charged reference capacitor,
which returns the integrator output to the zero crossing (from
auto-zero step) with a fixed slope. Thus, the time for the output
to return to zero is proportional to the input signal.

RUN/HOLD OPERATION
DEINT TERMINATED

INT

~~f€~~8~OSSING ~ AUTOZERO--!

,

INTEGRATOR
OUTPUT
INTERNAL CLOCK

____________

j;--"
---Jr------r

I

?

STATIC IN
~ PHASE II
"IMIN 1790 COUNTS I HOLDSTATE
1
~-! ~IMAX2041 C?UNTS I
I
1_______
I
~ ~'/ r+==7COUNTS ____1

L..rf fu1.n.n..t rfU1.JUl-.fU1.f ,JlI1.flSl-flf ~
--'n

~

I

II-------...J.---

AUN/H5tDtNPUT--------,-~-_-_-_-_-_-_-_-_-_-~

~ ~ ____ h_~---

INTERNAL LATCH _ _ _ _ _ _ _ _ _ _ _ _ _ _

I

STATUS OUTPUT _ _ _ _--'

NOTE
The conversion rate is determined by the clock rate (8192 clock
periods per cycle) wiih the RUN/HOLD input left open or connected to + Vs.

,

r--

If RUN/HOLD goes low any time during the Deintegrate phase
after zero crossing has occurred, the deintegrate phase will terminate and the converter will go to auto zero. This feature can
be used to save time in deintegrate after zero crossing.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-85

ADC-7109
TIMING AND OPERATION
DIRECT MODE OUTPUT

With MODE input low, the data outputs (bits 1-8 low order byte,
bits 9-12, polarity and overrange high order byte) are accessible
under control of the byte and chip enable terminals as inputs.
These three inputs are active low, and are provided with pullup
resistors to ensure an active high level when left open.

6~BYTE - - - - - - - - -

-

-

___ -f f--

Note that the control inputs are asynchronous with respect to
the internal clock-the data may be accessed at any time.
Therefore it is possible to access the data while it is being updated which could result in scrambled output data. To prevent
this, the access of data should be synchronized with the conversion cycle by monitoring the STATUS output. Data is never updated while STATUS is low.

DATA
VALID

DonED LINE INDICATES HIGH IMPEDANCE STATE

HANDSHAKE MODE
The handshake mode is an alternative means of interfacing the
ADC-7109 to digital systems. In this mode, the AID actively controls the flow of data rather than passively responding to chip
and byte enable inputs and can be interfaced directly to industry
standard UART's with no external logic.

The device enters the handshake mode when the MODE input
is held high after new data has entered the output latches at the
end of every conversion performed. (See timing diagrams.) The
MODE input may also be used to trigger entry into the handshake mode on demand. Any time during the conversion cycle,

HANDSHAKE TIMING WITH SEND HELD POSITIVE
ZERO CROSSING
OCCURS
ZERO CROSSING
/
DETECTED

INTEGRATOR
OUTPUT
INTERNAL
CLOCK

I

:

INTERNAL;-----i
I
~TCH
------------~~-__~--~------------~--+_------------~I--~--------I
I
STATUS
OUTPUT
I
I
::
,:

------------------1

~~S~

MODE HIGH ACTIVATES

UART
INTERNAL NORM CE/LOAD, HBEN, LBEN
MODE

:

WI/lf!////7///ff/ll//IIJ/1///1/1////WA
I
I

1

I

I

--!.-- SEND

.~ I

I

I

SENSED

I
1
I
I

I
1

SEND
SENSED

I

1TERMINATES
UART MODE

~I--_ _ __

/"

i

SEND
INPUT -I-.<.LL.<-u'.LL.LLfW-.LL.~,,",

~~t,. BYTE

MODE LOW, NOT IN
' - - - - - - - ' - - - - ' : , HANDSHAKE MODE ___________
~-=-:-::-:--:-:-:-:-=-_~I
I DISABLES OUTPUTS CE/LOAD, HBEN, LBEN
DATA VALID
~--I----- - - ~-

-1- -;-- -

---- --- -

LBEN

~~f/YTE - - -

1-86

I
-

-

- - - -

1

I

I

:

I

I

I

- - -:-- -:- - -- - - - --:- -

I-

I

- - -

:t __ !_
I

-<"---::D""A=TA:-:-:V""AL:-:ID::-~x,- - -~ -

II!
..
THREE-STATE HIGH IMPEDANCE
_
_ :L -

-- - -

THREE·STATE WITH PULLUP

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-7109
TIMING AND OPERATION (CO NT)
the MODE input can be pulsed from low to high and the device
will immediately enter the handshake mode. If the pulse occurs
while new data is being stored, entry into handshake mode will
be delayed until the data is stable. While in the handshake
mode, the MODE Input will be ignored, and although conversions will still be performed, data updating will be inhibited until
the output cycle is completed and clears the handshake mode.
The timing diagram (Handshake With SEND Held High) shows
the sequence of the output cycle with the SEND input held high.
The handshake mode is entered after the data latch pulse
(generated internally). The SEND input (held high) is sensed on
the same high to low internal clock edge. On the next low to high
clock edge, the CE/LOAD and HBEN terminals go low

enabling the high-order byte (bits 9 through 12, polarity and
overrange). The CE/LOAD terminal remains low for one clock
period only, the data outputs remain active for 1% clock periods,
and the high byte enable remains low for 2 clock periods. Note
that the CE/LOAD terminals low level or low to high edge may
be used as a synchronizing "OUTPUT" signal to ensure valid
data, and the byte enable terminal as an "OUTPUT" may be
used as a byte identification flag (in the handshake mode only).
With the SEND input remaining high, the converter completes
the output cycle using CE/LOAD and LBEN while the low order
byte outputs (bits 1 through 8) are activated. When both bytes
are sent, the handshake mode is terminated.

TYPICAL UART INTERFACE TIMING.
(HANDSHAKE MODE)

ZERO CROSSING
OCCURS
ZERO CROSSING
DETECTED

INTEGRATOR
OUTPUT

INTERNAL
CLOCK
INTERNAL
LATCH

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SEND
71,---SENSED .........
Mlir/TT7~'TT7Tr.rTT

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(UART TBRE)

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LOWBYTE
DATA

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THREE-STATE HIGH IMPEDANCE

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-87

ADC-7109

HANDSHAKE MODE (CO NT)
The send input may be utilized in delaying portions of the output
sequence, or handshake to ensure correct data transfer. The
timing diagram (typical UART interface timing) shows the relationships when using the ADC-7109 with an industry standard
UART to interface to serial data channels. In this type of interface, the SEND input of the ADC-7109 is driven from the TBRE
(Transmitter Buffer Register Empty) output of the UART, and
the CE/LOAD terminal drives the TBRL (Transmitter Buffer
Register Load) input of the UART. The data outputs of the
ADC-7109 are paralleled into the Transmitter Buffer Register inputs of the UART.
Assuming the UART Transmitter Buffer Register is empty, the
SEND input will be high when the handshake mode is entered
after new data is stored. After the SEND input is sensed, the
CE/LOAD and HBEN terminals will go low, activating the high
order byte outputs. At the end of 1 clock period, the CE/LOAD
goes low and the high order byte data is clocked into the UART
TBR. The UART TBR output will now go low, which stops the
output cycle with the HBEN output low, and high order byte outputs active. After the output data has been transferred to the
UART transmitter register and cleared the TBR, the TBRE output returns high. On the next clock high to low edge, the high
order byte outputs are disabled, and % clock pulse later, the
HBEN terminal returns high, and the CE/LOAD and LBEN outputs go low, activating the low order byte outputs. The low order
byte outputs are similarly clocked into the UART (when
CE/LOAD returns high) transmitter buffer register and TBRE
again goes low. When TBRE returns high, it is sensed on the
next high to low clock edge, disabling the data outputs. One half
clock pulse later, the handshake mode is cleared, and the
CE/LOAD, HBEN and LBEN terminals return high and stay active as long as the MODE input stays high.
While the MODE input is high, the ADC-7109 will output the
results of every conversion except those completed during a
handshake operation. A low to high pulse (edge triggered) on
the MODE input will enter the handshake mode and handshake
output sequence may be performed on demand.

HANDSHAKE TRIGGERED BY MODE INPUT
ZERO CROSSING DETECTED

STATUS OUTPUT UNCHANGED
IN UART MODE

,

-:---------

:__ L_L_
r-------

'POSITIVE TRANSITION CAUSES ENTRY INTO HANDSHAKE MODE

1-88

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-7109
TIMING AND OPERATION (CONT)

The timing diagram (Handshake Triggered by Mode Input)
shows a handshake output sequence triggered by such an
edge. The SEND input is shown as being low when the converter enters the handshake mode. In this case, the entire output sequence is under the control of the SEND input, and the
sequence for the high order byte is similar to the low order byte.
This timing diagram also shows the output sequence taking
longer than the conversion cycle. Note that conversions are still
performed with the STATUS output and RUN/HOLD input functioning normally. The only difference is that new data will not be
latched when in handshake mode and is therefore lost.

OSCILLATOR 1

CRYSTAL OSCILLATOR
CRYSTAL

-f1 !Dl C
OSC
SEC

OSC
IN

osc

OUT

BUF
OSC OUT

CRYSTAL OSCILLATOR
Using an inexpensive 3.58 MHz TV crystal provides an integration time given by:
T = (2048 clock periods) x

3.5:~HZ

= 33.18 msec.

Note this is very close to two 60 Hz periods or 33.33 milliseconds. The error is less than 1% which yields better than 40 dB
60 Hz rejection. The ADC-7109 will operate reliably at conversion speeds of up to 30/second, which corresponds to a clock
frequency of 245.8 kHz. See Crystal Oscillator Connection.
To overdrive the internal oscillator, the overdriving signal is applied to the OSCILLATOR INPUT and the OSCILLATOR OUTPUT is left open. The internal clock frequency will be of the
same frequency, duty cycle and phase as the input when the
OSCILLATOR SELECT input is left open. With the
OSCILLATOR SELECT at ground, the clock will be a factor of
58 below the input frequency.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-89

ADC-7109
APPLICATIONS
DIRECT INTERFACE TO INTEL 8080/8055

+sv

GNO

and minimum pulse widths are met. Drive limitations on long
busses should also be considered. This type of interface is
favored if the memory peripheral address density is low so that
simple address decoding can be used.

The three-state output capability of the ADC-7109 enables it to
be interfaced directly to most microprocessor busses. Note that
system timing in this type of interface should be carefully considered to be sure that requirements for set-up and hold times,

HANDSHAKE INTERFACE TO AN INTEL MICROPROCESSOR

07-00

8IT51---""-

9·12
POL. OR
81TS

AO-A1

cs

PArPAo

1·8
ADC·7109

87C48,
8008,8080,
8085,8048 ETC

8255

PC.
ANALOG
IN

PC,

»-4--.., PC,
1 ) 4 - - . . , PC,

INTR

~-------~

The handshake mode allows ready interface with a wide variety
of external devices. The byte enables may be used as byte identification flags or as load enables and external latches may be
clocked by the rising edge of the CE/LOAD.
This application shows a handshake interface to Intel microprocessors using an 8255 programmable peripheral interface.
Handshake operation with the 8255 is controlled by inverting its
Input Buffer Full (IBF) flag to drive the SEND input to the
ADC-7109 and using the CE/LOAD to drive the 8255 strobe.
The internal control register of the 8255 should be set in MODE
1 for the port used. If the 8255 IBF flag is low and the ADC-71 09
is in handshake mode, the next word will be strobed into the
port. The strobe will cause IBF (of the 8255) to go high (SEND

1-90

goes low), which will keep the enabled byte outputs active. Thl
8255 will generate an interrupt which when executed will resu
in the data being read. The IBF will be reset low when the byte i
read, causing the converter to sequence into the next byte. Th
MODE input to the ADC-7109 is connected to a control line 0
the 8255.
The data from every conversion will be sequenced in two byte
in the system, if the output is left high, or tied high separatel~
Data access must take less time than a conversion. The outpl
sequence can be obtained on demand if this output is force
from low to high and the interrupt may be used to reset tt
MODE bit. Conversions may be performed on command undl
software control by driving the RUN/HOLD input to the co
verter by a bit from the 8255.

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-7109
MULTIPLEXING SEVERAL CONVERTERS TO A SINGLE UART

SERIAL OUTPUT
6402 CMOS UART
SERIAL INPUT _
TBR1·TBR8

+5V

In this application, several ADC-7109's are multiplexed to one
UART. The word received by the UART (at the UART's RBR
outputs when DR is high) is used to select which converter will
handshake with the UART. This configuration will allow up to
eight ADC-7109's to interface with one UART with no external
component requirements.

ORDERING INFORMATION
ACCESSORIES
Part Number

Description

ADC-7109
TP 1k

Mating Sockets
Trimming Potentiometers

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-91

ADC-800
is-Bit Plus Sign AID Converter
with Microprocessor Interface

FEATURES
• 15-Bits Plus Sign Bit
• Parallel or Serial Bus Interface
• Three State Outputs
• High Impedance Differ-ential Input
• UART Control Signals
• Low Noise

-',

GENERAL DESCRIPTION
DATEL's ADC-800 is a low power, 15-bit
plus sign integrating AID converter. Microprocessor interface signals allow 16-bit,
single byte or 8-bit, two byte parallel data
transfer or data may be transmitted serially
via industry standard UART in the "handshake"mode. Conversion time is typically
2.5 convlsec with a maximum differential
linearity error of ± % LSB.
The ADC-800 uses an improved dual slope
conversion technique which incorporates
system zero and integrator output zero
phases. Offset error sources are automatically zeroed. The externally adjustable clock allows integration periods
which are integral multiples of 50 or 60 Hz
for maximum power-line noise rejection.
By using the 2.4576 M Hz crystal oscillator
mode, 50, 60 and 400 Hz signals are rejected. A serial count output can be derived by gating the clock signal with data
valid (OVO). The count output pulses may
be used in serial fiber optic transmission
systems.

i

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SWITCH/"'-,l-

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OUTPUTS

--- 9

8

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c-~

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'cloc~ I~ ;AT~ "IANIe I ~
CONTROL

Other important features of the ADC-800
include: high. impedance differential inputs, 5 pA typical input bias current, 15 p.V
peak-to-peak typical input noise, 20 mW
power dissipation and static discharge protected inputs. the combination of low cost,
high accuracy and low power consumption
make the ADC-800 an ideal choice for
process control, data logging and intelligent measurement system applications.
The ADC-800 operates over the commercial, O°C to + 70°C temperature range
and is packaged in a 40-pin plastic DIP.

1-92

2

3

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

'6

ADC-800
ABSOLUTE MAXIMUM RATINGS
Positive Supply Voltage (+ Vs to gnd) ..............
Negative Supply Voltage (- Vs to gnd) ..............
Analog Input Voltage Range (+ or - Vin) ...........
Reference Input Voltage Range (Vref) ..............
Digital Input Voltage Range .......................
Power Dissipation (package) ......................

.
.
.
.
.
.

+6.2V
-9.0V
+Vsto -Vs
+Vsto -Vs
+ Vs +0.3V to gnd -0.3V
0.5W to 70°C

FUNCTIONAL SPECIFICATIONS
Typical at 25'C, ±5V supplies, 2.5 conv/sec. conversion speed, 2.4576 MHz crystal,
3.2768V full-scale voltage unless otherwise noted.
ANALOG INPUTS
Type Analog Input . . . . . . . . . . . . . . . . . . . . . . . .
. ..
Zero-Scale Error, max. 1 . • • • . • • • • • • • • • • • . • • • • • • • • • .

Input Current,2 max. . ..... " ..................... .
Common Mode Input Range ...................... .
Common Mode Rejection Ratio' ................... .
Input Noise' ................................... .

Differential
±0.5 LSB
15 pA
- V s + 1.5V to + V s - 1.0V
80 ~VIV
15 ~V peak·to·peak

DIGITAL INPUTS

5""

Control Input Pull-Up Currents .................. .
Input Voltage, (Pins 18-21, 26, 27)
High Min ......................... .
Low Max ......................... .
Input Pull-up Current' (pins 26, 27) ................. .
(pins 17, 24) ................. .
Input Pin Pulldown Current' (pin 21) ................ .
!ru1!!t Capacitance, max. (pins 18, 19) ............... .
BUS/Hand Control Pulse Width, min.' .............. .
Byte Enable Pulse Width, min.' .................... .
Chip Enable Pulse Width, min.' ......•...•..........
Byte Enable Access Time, max.' .................. .
Chip Enable Access Time, max.' .................. .
Data Hold from Byte Enable Change, max.' .......... .
Data Hold from Chip Enable Change, max.' .......... .

2.5V
2V

5""
5""

25 ""
50 pF
70 nsec.
350 nsec.
500 nsec.
350 nsec.
400 nsec.
300 nsec.
400 nsec.

OUTPUTS
Output Voltage, high min................... .
low max. 9 • • • • . • • . • • • • • • . • • . " ••••.•
Output Leakage Current(high Z state), max .......... .
Oscillator Output Current, (Vo 2.5V) .............. .
2.5V) ....... .
Buffered Oscillator Output Current (Vo

=

3.5Vat 100 mA
O.4V at 1.6 mA

1""

1 mA
5mA

=

PERFORMANCE
Resolution ..................................•..

Linearity Error, 10 max . ........................... .
Differential Linearity, max. . ...................... .
Conversion Time ............................... .
Full-Scale Gain Tempco" max..................... .
Zero-Scale Error Tempco, max. . .................. .
Full-Scale Magnitude Symmetry Error, max. 12 .••....•.

15-bits plus sign
2 LSB
±0.5 LSB
2.5 cony/sec. (400 msec.)
5 ppm/oC
2 ~V/oC
2 LSB

POWER REQUIREMENTS
Supply Voltage ................................. .
Supply Current, max ............................. .
typical ......••...................

±5V

±3.5 mA
±2.0 mA

PHYSICAUENVIRONMENTAL
Operating Temperature Range .................... .
Storage Temperature Range ...................... .
Lead Temperature (soldering 60 sec) ............... .
Package ...................................... .

O°C to + 70°C
-55°C to + 150°C
+ 300°C
40-pin Plastic DIP

TECHNICAL NOTES
1. The internal class A output stage amplifiers will supply a 20 p.A drive current
with minimal linearity error. RINT is
calculated for a 20 pA full-scale current
using the following expression: RINT
(MO) = Full-Scale Input Voltage (V)/20.
2. The integrating capacitor should be
selected to give the maximum integrator output voltage swing without saturating the integrator (approximately O.4V
from either supply). With a 20 p.A fullscale buffer output current, the integrating capacitor (C INT) is calculated as
follows: CINT (p.F) = 16.384 (1/FcLK
(kHz) (20 pA)/lntegrator Output Voltage
Swing (V). With an external 2.4576 MHz
crystal, the clock frequency will be
163.8 kHz and conversion time is 2.5
CONV/SEC. A 0.47 p.F CINT is recommended with low dielectric absorption
such as polypropylene to prevent rollover errors. The outer foil of CINT should
be connected to Pin 31.
3. A 1.0 p.F polypropylene capacitor is
recommended for Csz . (System Zero
Capacitor.) The inner foil should be connected to Pin 32.
4. For the reference capacitor, a 1.0 p.F is
recommended. Larger values may be
used to limit roll-over errors. Low leakage capacitors, such as polypropylene
should be used.
5. The analog input required to generate
the 32,768 8 full-scale count is 2 VREF .
The reference voltage source should be
selected for temperature stability. The
ADC-800 will provide 30 ppm resolution. With a 5 ppm/oC reference, a 6°
change in temperature will introduce a
1-bit absolute error. A stable reference
must be used where ambient temperature is controlled and accurate absolute
measurements are needed. The
reference voltage input must be a
positive voltage with respect to analog
common. A reference circuit is shown
below.
6. The Rs (delay resistor) in combination
with CINT compensate for comparator
delay time. With a 0.47 p.F CINT, a 200
series resistor is recommended.
REFERENCE VOLTAGE CIRCUIT

FOOTNOTES:

1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.

Vin =ov
At 25 Q C, Vin = av. For O°C to + 70"C, lin = 125 pA.
Vern = ±1V.
Not exceeded 95% of the time.
Pin 18, 19, 20, 21 = av. Vout = 2V.
V = 2V.
V = 3V.
Parallel data transfer. (BUS/Hand = 0)
For pins 18, 19, 20. lout = 750 pA.
- F.S. ~ Vin ~ + F.S., best straight line. End pOint is typically 2.8 LSB.
External Reference Tempco = 0 ppm/oC O°C ~ TA :::.: + 70°C.

VREF 9
100k

12. Yin = 3.27V.
13. Static sensitive device. Unused units must be stored in conductive material. Protect devices
from static discharge and static fields.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-93

ADC-800
PIN DESCRIPTION

PIN SYMBOL

DESCRIPTION

PIN SYMBOL

1

SGN

Sign Bit: Logic "1" indicates positive input. Input
signal polarity is determined at the end of the
signal integrate phase.

21

2

DB15 (MSB)

3

DB14

4

DB13

5

DB12

6

DB11

7

DB10
DB9

9

DB8

10

DB7

11

DB6

12

DB5

13

DB4

14

DB3

15

DB2

16

DB1 (LSB)

17

TEST

18

Data Bits. Three-State Outputs

Test: Logic "0" forces data bits to Logic "1" and
disables clock. Logic "1" enables counter
latches.

LBEN/LBFLG Low da~e enable input or flag output depend(Input/Output) ing on BUS/HAND (Pin 21) status.
With BUS/HAND (Pin 21) low and CE/LDSTRB
(Pin 20) low, DB8 through DBI (low data byte)
are output, when input LBEN is low.

HBEN/HBFLG High data byte enable input or flag output
(Input/Output) depe~ on BUS/HAND (Pin 21) sta~
With BUS/HAND (Pin 21) low and CE/LDSTRB
low, the sign bit and DBI5-DB9 (high data
byte) are output, when input HBEN is low.
With BUS/HAND (Pin 21) high, valid data (sign
and DBI5-DB9) is indicated by the flag output
HBFLG when low.

20

Inpu~w, yields parallel output data mode.
The CE, HBEN and LBEN (Pins 20, 19, 18)
are inputs and directly control the 16 data
bits.

OSCIN

Oscillator Input

23

OSC OUT

Oscillator Output

24

OSC CON

Selects internal oscillator structure. Input
high: RC oscillator. Internal clock frequency
is same frequency and duty cycle as BUF
OSC (Pin 25).
Input Low: Crystal oscillator. Internal clock
frequency is frequency at BUS OSC + 15.

With BUS/HAND high, valid data (DB8-DB1) is
indicated by the flag output LBFLG when
low.
19

DESCRIPTION

Input pulsed HIGH causes immediate entry
into handshake data transfer mode for
UART interfacing. LDSTRB, LBFLG and
HBFLG are TTL compatible outputs in this
mode.
22

8

BUS/HAND

CE/LDSTRB With BUS/HAND (Pin 21) low, CE ~n 20) is
(Input/Output) the master CHIP ENABLE. When CE input is
high, the sign bit and DJ!!5-DB1 are in the high
impedance state. With CE low, data is transferred under control of LBEN and HBEN input
signals as follows:
CE LBEN HBEN FUNCTION
0
0
0
0

0
1
0
1

1
0
0
1

25

BUF OSC

Buffered oscillator output

26

CONVERT/STOP

Input high: Performs continuous conversion.
Input low: Stops conversion process 7
counts before entering signal integrate
phase. Conversion in progress is completed.

27

DROST

Data output request Signal. Input used in the
handshake mode to indicate an external
device is ready to accept data.

28

-Vs

Negative supply ( - 5V)

29

VREF

Voltage reference input

30

COM

Analog common. The device is auto-zeroed
to the analog common potential.

31

VINT

Integrator output

32

Csz

System zero capacitor

33

VBUF

Input signal buffer output

34

-CR

Negative reference capacitor connection

35

+CR

Positive reference capacitor connection

36

-VIN

Negative differential analog input

37

+VIN

Positive differential analog input

38

+Vs

Positive supply ( + 5V)

39

DIG GND

Ground return for all digital logic

40

DVD

Data valid signal: high during signal integrate and reference integrate phases until
data is latched. Low when in auto zero
phase. Data does not change when
DVD = 0

Low data byte output
High data byte output
Low and high data byte output
High impedance state

With BUS/HAND high (Pin 21). LDSTRB
Pin 20) is a load strobe output sign and a low output signal instructs the receiving device to accept
data.

1-94

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADe-800
TIMING AND OPERATION
THE CONVERSION PROCESS

ANALOG INPUT DESCRIPTION

The conventional dual-slope converter measurement cycle has
two distinct phases: Input signal Integration, and Reference
Voltage Integration (deintegration).

System Zero Phase: Errors due to buffer, integrator and
comparator offset voltages are compensated for by charging
Csz with a compensating error voltage.

The analog input signal is integrated for a fixed time period
which is measured by counting clock pulses. An opposite
polarity constant reference voltage is then integrated until the
integrator output returns to zero. The reference voltage
integration time is directly proportional to the input signal. A
complete conversion requires the integrator output to "rampup" and "ramp-down".

Input Signal Integration Phase: The differential voltage between
the inputs is integrated. The differential voltage must be within
the specified common-mode range. The input signal is
integrated for 16,384 clock cycles. The polarity is determined at
the end of the phase.
Reference Voltage Integration: CR (Reference Capacitor),
which was previously charged is connected with proper polarity
to ramp the integrator output back to zero. The time for the
output to return to zero is proportional to the input signal
magnitude. This phase lasts for a maximum of 32,768 clock
periods.

The ADC-800's accuracy is unrelated to the integrating resistor
and capacitor values as long as they are stable during a
measurement cycle. An inherent advantage in the dual-slope
converter is noise immunity. Noise spikes are integrated or
averaged to zero during the integration periods.

Integrator Output Zero: This phase guarantees the integrator
output is at zero volts when the system zero phase is entered
and that the true system offset voltages are compensated for.
This phase lasts for 4096 clock cycles.

The following equation relates the input signal, reference
voltage and integration time:
1 STSI
RC
Vin(t) dt =

V R TRI

o

RC
Reference Voltage
Signal Integration Time (fixed)
Reference Voltage Integration
Time (variable)

CONVERT ON COMMAND OPERATION
(CONV/STOP = 0 AFTER ZERO CROSSING IS DETECTED)

For a constant Vin: Vin = VR [TRI]
TSI

CONTINUOUS CONVERSION
(CONV/S'i'OP = 1)

I

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SIGNAL

:

: INTEGRATOR ! NEXT
!
~ PZ::~E ~~~~EERSION~

REFERENce INTEGRATE

~:~~~~~~R04+-~':;r:~R(~i)E---;+--io~~:i~~ATE)

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HIGH IMPEDANCE STATE

VALID DATA

SGN, 0815 to DB1
LOW

gm---------------

P777]OON'T
~CARE

HANDSHAKE MODE DATA TRANSFER
The ADC·800 actively controls the data transfer to
peripherals through the handshake data transfer
mode. In this mode LBEN/LBFLG, HBEN/HBFLG
and CE/LDSTRB (Pins 18, 19, 20) are TIL
compatible outputs. The LDSTRB signal indicates
valid data is available for the peripheral. The LBFLG
and HBFLG signals indicate which data byte is being
transferred. DROST (Pin 27) informs the AID that a
peripheral is ready to accept data. A complete cycle
transfers two 8-bit bytes.
A logic "1" on BUS/HAND (Pin 21) enters the
handshake mode after data is stored in the output
data latches. Once the handshake mode internal
latch is set, the BUS/HAND signal is ignored, the
DROST signal controls data transfer to the external
requesting peripheral. (See adjacent diagram.)
This d~am shows the timing for the data transfer
with BUS/HAND at logic "1" (throughout the
transfer). Note that the DROST is at logic "1"
throughout the transfer. The transfer rate is set by the
internal clock. A complete data transfer occurs in 4
clock periods after a DROST logic" 1" is detected on
a high to low clock edge transition.

1-96

ZERO CROSSING

INTEGRATOR
OV

OUTPUT

\

INTERNAL CLOCK

I

~~~~N~~~:rTEA

1

~:~I~D:I1"NAl)

~

!

I
I0:

INTERNAL
I
DATA TRANSFER
MODE CONTROL S'GNAL,-------fir.\\.
,,=HANDSHAKE.O=WSI

I
I
I
I

DROST
(DATA REQUEST ~::~~:ROM PERIPHERAL)

I

(LOAD DATA STROBE OUTPUn
(HIGH DATA

BYT~=Ekg OUTPUT)

HIGH DATA BYTE

HIGH

I

I

II

I

"z" STATE
I

I

(LOW DATA

I:

:
I!
I:
!I'l47777777ZpZa77777Z?ZPOI

EiUS/HAND
INPUT SIGNAL

I
I
I
I
r.;'\1'
1
I

0

:

I

I

I

f
I
1"::\'

I

I

t-

0 '

~!'

6

..

1

lIT

tilT NO

MS8

SEFHAL

an ~:~A
I

PARAllEL O... T.... OUT

MECHANICAL DIMENSIONS

INPUT/OUTPUT
CONNECTIONS

1---,.101 MAX-----J

I

'I~

(28,0)

I

I

O.'5~)~__

ij

0.190(4,9) MAX

--r

1

0.010 K0.Q18 KOVAR

116

17

1

~ F\7~ ~ ~- .
1_

T~l
15 SPACES
at 0.100 EA

BOTTOM
VIEW

PIN

1,712
(43,5)

0.900

J

BIT 11 OUT

18

REF,QUT

BIT 10 OUT

19

CLOCK OUT

•

BIT9 OUT

20

E.O.C. (STATUS)

BIT 8 OUT

21

START CONVERT

6

BIT 7 OUT

22 COMPAR. INPUT

7

BIT 6

our

23

BIPOLAR OFFSET

8

BIT 5 OUT

9

BIT 4 OUT

2'
25

20V INPUT

10

BIT 3 OUT

26

ANALOG COM

11

BIT 2 OUT

27

GAIN ADJUST

5

('_'10;= "

~ (22,9) ~

__

1_0.,00
(2,5)

FUNCTION
CLOCK RATE

2

13

32

PIN

3

12

1

FUNCTION

BIT 12 OUT (LSB) 17

lOV INPUT

BIT lOUT (MSB)

28

+15V POWER

81T lOUT (MSB)

29

BUFFER OUTPUT

SHOAT CYCLE

30

BUFFER INPUT

1~

DIGITAL COM

31

-15V POWER

16

+5V POWER

32

SERIAL OUTPUT

·NOTE: PINS HAVE Q,025 INCH STANDOFF FROM CASE. to.Ot"

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-810, ADC-811
FUNCTIONAL SPECIFICATIONS, ADC-810, ADC-811
± 15V and + 5V supplies unless otherwise noted

TECHNICAL NOTES

Typical at 25 ·C,

DESCRIPTION
INPUTS
Analog Input Ranges, unipolar' ..... 0 to + 10V FS, 0 to + 20V FS
Analog Input Ranges, bipolar' ...... ± SV. ± loV FS
Input Impedance. . . . . . . . . . . . . . . .. l.OS k(J (0 to + 1ov. ± SV)
4.2 k(J (0 to + 2oV. ± 10V)
Input Impedance with Buffer ....... 100 Megohms
Input Bias Current of Buffer ........ 12S nA typical, 2SO nA max.
Input Overvoltage2 . . . . . . . . . . . . . .. ± ISV
Start Conversion ................. 2V min. to S.SV max. positive pulse with duration of 50 nsec. min. Rise and fall times < 30
nsec. Logic "1" to "0" transition resets converter and initiates next conversion. Loading: 1
TTL load
OUTPUTS'
Parallel Output Data . . . . . . . . . . . . .. 12 parallel lines of data held until next conversion command.
Your ("0")" +o.4V
Your ("1")", +2.4V
Coding, unipolar ................. Complementary Binary
Coding, bipolar .................. Complementary Offset Binary
Complementary Two's Complement
Serial Output Data ................ NRZ successive decision pulses out, MSB first.
Complementary Binary or Complementary Offset Binary Coding.
End of Conversion (Status) ......... Conversion status signal. Output is 10gic"I"
during reset and conversion and logic "0"
when conversion complete.
Clock Output .......... _......... Train of positive going + SV, 70 nsec. pulses.
6.S MHz for ADC-81o, and 4.3 MHz for
ADC-811 (Pin 17 grounded).
PERFORMANCE
Resolution ......................
Nonlinearity, max_ .... , ...........
Differential Nonlinearity, max. . .....
Gain Error, max_, before ad~ .......
Zero Error, max_, unipolar, efore adj_
Offset Error, max_, bipolar, beforeadj_
Temp_ Coeff, of Gain, max. ........
Temp. Coeff, of Zero, unipolar, max..
Temp_ Coeff_ of Offset, bipolar, max.
Diff_ Nonlinearity Tempeo, max.
Conversion Time', 12 bits .........
10 bits· . . . . . . ..
8 bits. . . . . . . ..
Buffer Settling Time, 10V step .......
Power Supply Rejection max .......

12-bits (1 part in 4096)
±1 LSB
±1 LSB
± 0.1 %
± o.IS% of FSR4
±0.15% of FSR4
± 20 ppm/DC
± 10 ppm/DC of FSR5
± 10 ppm/o C of FSR5
± 5 ppm/" C of FSR
2.0 p,sec. max.
1.7 p,Sec. max.
1.4 p,Sec. max.
500 nsec. to 0.01 %
0.01%/% Supply max.

ADC-811
3.0 p,sec.
2.6 p,sec.
2.1 I'sec.

only
max.
max .
max .

POWER REQUIREMENTS
Analog Supply, positive ....... , ... + 15V dc ± 0.5V at 70 rnA max.
negative .......... -15V dc ± 0.5V at 30 rnA max.
Logic Supply ... _... _............ + SV dc ± 0.2SV at 240 rnA max.
PHYSICAWENVIRONMENTAL
DoC to + 70°C
Operating Temperature Range, MC .
MM. -55°C to + 12SoC
Storage Temperature Range .......
PackageSize. _.... _.............
Package Type ...................
Pins ...........................
Weight .........................

-6S0Cto +ISo°C
1.700 x 1.100 x 0.160 inches
32 pin ceramic
0.010 x 0.018 inch Kovar
O.S ounces (14 grams)

FOOTNOTES:

1. For information on models with 0 to + SV de and ± 2.SV de input voltage ranges, please
contact the factory.

2. The input buffer cannot be used with the 0 to + 20V de input range.
3. All digital outputs can drive 5 TTL loads.
4. Without buffer amplifier used. ADC·810/811 may require external adjustment of clock rate using the
buffer amplifier.

5. FSR is full scale range and is 10V de for 0 to + lOV de or ± 5V de input and 20V de for
± 10V de inpul.
6. Short cycled operation.

1. Use of good high frequency circuit
board layout techniques is required for
rated performance. Digital common
(Pin 15) and analog common (Pin 26)
are not connected internally and
therefore must be connected as directly
as possible externally. Also, it is
recommended that the analog and
digital supplies be externally bypassed
with a 0.01 f.1F ceramic capacitor in
parallel with a 1 f.1F electrolytic capacitor. The ±5V dc supply should be bypassed to ground with a 10 f.1F electrolytic capacitor. Additionally, Pin 27
(Gain Adjust) should be bypassed to
ground with a 0.01 f.1F ceramic
capacitor.
2. External adjustment of zero or offset
and gain are provided for by trimming
potentiometers connected as shown in
the connection diagrams. The potentiometer values can be between 10k
and 100 k ohms and should be 100
ppm/oC cermet types (such as
DATEL's TP Series). The adjustment
range is ± 0.2% of FSR for zero or offset and ±0.3% for gain. The trimming
pots should be located as close as
possible to the converter to avoid noise.
3. Short cycled operation results in
shorter conversion times where the
conversion can be truncated to less
than 12 bits. This is done by connecting
Pin 14 to the output bit following the last
bit desired. For example, for an 8-bit
conversion, Pin 14 is connected to bit 9
output. Maximum conversion times are
given for short-cycled conversions of 8
or 10 bits. In these two cases, the clock
rate is also speeded up by connecting
the clock rate adjust (Pin 17) to + 5V
(10 bits) or + 15V (8 bits). The clock
rate should not be arbitrarily speeded
up to exceed the maximum conversion
rate at a given resolution, however, or
miSSing codes will result.
4. These converters dissipate 2.8 watts of
power. The case to ambient thermal
resistance is approximately 20°C per
watt. For ambient temperatures above
50°C, care should be taken not to
restrict air circulation in the vicinity of
the converter. Also, it is recommended
that the converter be mounted directly
to the circuit board (without the use of a
mounting socket) and that good thermal contact be established between
the case bottom and the circuit board
grounded plane by use of a silicone
thermal joint compound such as
Wakefield type 120 or equivalent. For
operation in ambient temperatures exceeding 85°C, air flow of at least 400
linear feet per minute is recommended.

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

1-101

ADC-810, ADC-811
TIMING DIAGRAM FOR ADC-810, ADC-811

~
I
VALID

PARALLEL

T,

II
----1r--

-+i

20 NSEC

r--

70 NSEC

_ _ _ _ _ _ _ _ _--t_JoIDATANOW

~:_50NSEC
TIMING DIAGRAM
OPERATING PERIODS

SERIAL
DATA
OUT

ADC-810

ADC-811

T, 2.0I'sec.
T2 98 nsec.

3.0 I'sec.
2S8 nsec.

BlT 1
(MSB)

BIT 2

OUTPUT: 101010101010

BIT12
(LSB)

CLOCK RATE ADJUSTMENT

SHORT CYCLE OPERATION

Refer to Technical Note 3 for methods of reducing the
overall ADC-810 or ADC-811 conversion time ..
CLOCK
RATE

• FOR CONNEC·
TION TO 15V
USE 5 kO TO
TRIMPOT

TO SELECTED
DATA OUTPUT PIN

PIN 14 CONNECTION

CLOCK RATE VS. VOLTAGE
PIN 17

CLOCK RATE

VOLTAGE

ADC·811

ADC·810

OV
+5V
+15V

4.3 MHz

6.5 MHz
7.8 MHz
8.1 MHz

5.2 MHz
5.4 MHz

RES. (BITS)
1
2
3
4
5
6

PIN 14TO
PIN 11
PIN 10
PIN9
PIN 8
PIN 7
PIN 6

RES. (BITS)
7
8
9
10
11
12

PIN 14TO
PIN 5
PIN 4
PIN 3
PIN 2
PIN 1
PIN 16

CLOCK RATE ADJUSTMENT RANGE

8, 10, .. 12 BIT CONVERSION
SV. 2kQ Trim Pot
6.S MHz to 7.8 MHz (ADC-810)
3.2 MHz to 3.6 MHz (ADC-811)
lSV. SKQ Trim Pot
6.S MHz to 8.1 MHz (ADC-810)
3.2 MHz to 4 MHz (ADC-811)

1-102

RESOLUTION
ADC-810 CONY. TIME
ADC·811 CONY. TIME
CONNECT THESE
PINS TOGETHER

12 BITS
2 "sec
3 J.1sec
17 & 15
14 & 16

10 BITS
1.7 "sec
2.6 J.1sec
17 & 16
14 & 2

8 BITS
1.4 "sec
2.1 j.LSec
17 &28
14 &4

DATEL, Inc. 11 Cabot Boulevard, Mansfield. MA 02048-1194ITEL (508) 339"3000ITLX 174388/FAX (508) 339-6356

ADC-810,-811
INPUT CONNECTIONS
INPUT
VOLT.
RANGE
OVto +10V
OV to +20V
±5V
± 10V

WITHOUT BUFFER
INPUT
CONNECT THESE
PIN
PINS TOGETHER
24
23 & 26
25
1 23 &26
24
23 & 22
25
23 & 22

-

OUTPUT CODING TABLES

±10V

COMPo
OFFSET BINARY

COMP.TWO·S
COMPLEMENT

:t5V

MSB

+ 9.9951V

+ 4.9976V

0000

... 7.5000
+5.500
0.0000
-5.0000

+ 3.7500

0001

1111

+ 2.5000
0.0000

0011

1111

0111

1111

-2.5000

1011

1111

1111
1111

- 3.7500

1101

1111

1111

0101

1111

1111

-5.0000

1111

1111

1111

0111

1111

1111

- 7.5000
- 10.000

0000

LSB

MSB

0000

1000

0000

1111

1001

1111

1111

1111

1011

1111

1111

1111

1111

1111

0011

1111

1111

LSB
0000

UNIPOLAR OPERATION
COMPo
BINARY CODING

INPUT RANGE

+10V

OTO +20V

MSB

+9.9976V
+8.7500
+ 7.5000
+5.0000
+2.50000·
+0.0024
0.0000

+ 19.9952V
+ 17.5OOOV
+ 15.OOOOV
+ 10.OOOOV
+5.0000V
+ 0.0049V
+O.OOOOV

0000
0001
0011
0111
1011
1111
1111

OTO

LSB
0000
1111
1111
1111
1111
1111
1111

WITH BUFFER
CONNECT THESE
PINS TOGETHER

30
30

30
30

-

-

1 23&26
1 29&24
NA
NA
23&2229&24
23&22
29&25

CALIBRATION PROCEDURE

BIPOLAR OPERATION
INPUT VOLTAGE
RANGE

INPUT
PIN

0000
1111
1111
1111
1111
1110
1111

1. Connect the converter as shown in the applicable connections diagram. A trigger pulse of 50 nanoseconds minimum is
applied to the start conversion input (pin 21) at a rate of 200
kHz..
2. Zero and Offset Adjustments
Apply a precision voltage reference source between the appropriate input for the selected full scale range and ground.
Adjust the output of the reference source to the value shown
in the Calibration Table for the unipolar zero adjustment (0 +
% LSB) or the bipolar offset adjustment (0 - % LSB). Adjust
the offset trimming potentiometer so that the output code
flickers equally between 1111 1111 1111 and 1111 1111
1110 for the unipolar range and between 0111 1111 1111
and 1000 0000 0000 for the bipolar range.
3. Full Scale Adjustment
Set the output of the voltage reference source used in step 2
to the value shown in the Calibration Table for the unipolar or
bipolar gain adjustment (+ FS - 1% LSB). Adjust the gain
trimming potentiometer so that the output code flickers
equally between 0000 0000 0000 and 0000 0000 0001.

CALIBRATION TABLE

TYPICAL CONNECTIONS

UNIPOLAR RANGE

a to
a to

+ 10V
+ 20V

LSB

BIPOLAR RANGE

-1/2 LSB

±5V

-1.22 mV
-2.44 mV

± 10V
SERIAL OUT

+ Y.

+ 1.22 mV
+2.44 mV

+ F.S.-l Yo

LSB

+9.9963 V
+ 19.9927V

+ F.S.-l Y.

LSB

+ 4.9963 V
+9.9927 V

For mformatlon on models with 0 to + 5V and ± 2.5V Input
voltage ranges please contact the factory.

PARALLEL

DATA
OUTPUTS

GAIN
AoJ

+t.

'5V

10K

510K
(min)

TO

~

100K

ft • •

1- ~II

-.O;+'.F@

-15V

I

7

I
I

_ 15V~+ 15V

~~

O~~~ET

*UNIPOlAA OPERATION. OV TO + 10V. CONNECT PIN 2310 26
BIPOLAR OPERATION. _ 5V TO + 5V, CONNECT PIN 23 to 22

100K

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-103

ADC-810, ADC-811
Providing Three-State Outputs

NOTE

For applications where the coverted input must interface
to tri-state TTL or CMOS logic, the ADC-B10 or ADC-B11
outputs are easily converted using buffers such as the
DMB095's shown in the diagram. Signal length must be
less than one inch between devices to ensure signal
integrity. Also note that two's complement outputs are
available from the ADC-B10 and ADC-B11 by using pin 13
instead of Pin 12 as the MSB output. The timing diagram
shows the delays incurred as the signal passes through
the buffers.

In any application using the ADC-B10 or the ADC-B11,
signal integrity and noise isolation are a function of grounding. The suggested ground plane shown should be used
whenever possible.

GROUND PLANE LAYOUT

HIGH SPEED THREE-STATE OUTPUT BUFFER

."

MSB OUT

" r-----'

10

Y4 r - - - D MSB OUT

A3

Y3 r - - - O

A5

'-

9

8

A4

A2

DMB095

7

Y5

f------o

Y2 - - - - - - D
Y6 ,-------0

A6
AI

Y1 - - - - - - D BIT 6 OUT

BIT £ OUT
01

ADC·810
OR
ADC -811

1

--D OUTPUT

r

BIT 7 OUT

G1

ENABLE

6

A4

5

A3

Y3

4

A5

Y5 - - - - - - - D

3

A2 DM8095 Y2

2

A6

Y6 - - - - - D

AI

Y 1 - 0 lSB OUT

,
lSB

our

Y4 - - - - - - - D BIT 7 OUT
~.---o

----0

"FOR TWO'S COMPLEMENT OUTPUT CODING THIS CONNECTION IS PIN 13 (MSB)

AFTER 27 NSEC MAXIMUM

----1 t- ~~~~,,gpUE~~:~E~~~T~

DATA OUTPUTS IN
HIGH IMPEDANCE STATE

OUTPUT ENABLE
CONTROL

L:--l

I

_, I c - c - I - - - - - '
i
r-- AFTER 37 NSEC MAXIMUM
DELAY, DATA APPEARS AT

OUTPUTS

1·104

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-810, ADC-811
HIGH SPEED DATA ACQUISITION SYSTEM
SERIAL DATA

OUT
GAIN RESISTOR

•

ADC-810
OR

ADC-Bll

CHANNEL
INPUTS

OUT A
MX~1616

OUTB

AM-5S1 A-~--(i13-13

U

GAIN
SELECT

~~~18~--------------~-----'~

LEAD

GAO CA 1 CA2 CA3

DELAY STROBE

The four DATEL components shown in the diagram make up a 12-bit,
high-speed data acquisition system capable of throughput rates of 200
kHz. The system can accept up to 16 single-ended input channels using
DATEL's MX-1616 CMOS multiplexer or up to eight differential channels using the MX-808.
Other DATEL components in the system are the AM-551, a hybrid precision programmable gain instrumentation amplifier and the SHM-4860, a
200 nanosecond, 0.01 % hybrid sample-and-hold device.

ORDERING INFORMATION
MODEL

TEMP_ RANGE

ADC-810MC
ADC-810MM
ADC-811MC
ADC-811MM

O°C to + 70°C
-55°C to + 125°C
O°C to + 70°C
-55°C to + 125°C

ACCESSORIES
Part Number

Description

TP10K or TP100K

Trimming Potentiometers

DATEL, Inc_ 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-105

ADC-815, ADC-825
Ultra-Fast 8-Bit
AID Converters
FEATURES
• 8-Bit resolution
• 700 Nanoseconds or 1 microsecond
conversion time
• 6 Input ranges
• Parallel or serial outputs
• No calibration required

-"

+15V
POWER

POWER

1

SERIAL DATAourpUT

GENERAL DESCRIPTION
DATEL's ADC-815 and ADC-825 are veryhigh-speed-8-bit successive approximation A/D converters in miniature hybrid
form. Both models have identical specifications except for conversion time. The
ADC-825 has a maximum conversion time
of 1 microsecond while the ultra-fast
ADC-815 accomplishes an 8-bit conversion in only 700 nanoseconds, maximum.

SUCCESSIVE
APPROXIMATION

REGISTER

These converters feature six analog input
voltage ranges: 0 to + 5V dc, 0 to + 10V
dc, 0 to + 20V dc, ± 2.5V dc, ± 5V dc
and ± 10V dc. Selection of input ranges
is accomplished by simple external pin
connection.

,,,
START
CONVERSION

Operation of these devices is further
simplified by complete functional laser trimming, resulting in a factory-trimmed converter that requires no external adjustments.
Each converter is a functionally complete
unit requiring a minimum of passive external components for operation, and is
packaged in a miniature, hermetically
sealed 24-pin ceramic DIP.
Output data is available in parallel or serial
form by external pin connection. Parallel
output coding is straight binary for unipolar
operation and offset binary or two's complement for bipolar operation. Output
coding in the parallel mode is accomplished by connection to either the MSB
output or the MSB output. Serial output
data is coded as straight binary for
unipolar operation or offset binary for
bipolar operation.
Both models have max. integral non± Y2 LSB, differential
linearity of
nonlinearity of ± Y2 LSB max., gain
tempco of 20 ppm/oC max., power supply
rejection of ±0.06%/% supply max., and
long-term stability of ±0.02%/year. Both
models require ±15V and 5V supplies,
and are available in different versions for
operating temperature ranges of OOC to
+70°C, or -55°C to +125°C.

1-106

MECHANICAL DIMENSIONS
INCHES (mm)
0.800MAX
(20.3)

0.190 MAX

~
~

~0.010XO.018
KOVAR Pins

,,,
,,
,,
,,,
,
,,,

13

,12

BOTTOM

VIEW

!

,,
!

1

24

INPUT/OUTPUT
CONNECTIONS

,
,,,
,,
,

,,
,,
,
,,,
,,,
,
!

PIN
1

0.150 MIN.
(3.8)

Tl
11
SPACES
ATO.l00
(2.5)

1.310 MAX.
(33.3)

FUNCTION
SERIAL DATA OUTPUT

r23 ~'POWERIN

•

5
6
7
8
9
10
11
12

15VPOWER IN
ANALOG GROUND
ANALOG GROUND
ANALOG GROUND
BIPOLAR OFFSET
ANALOG INPUT 5V RANGE
ANALOG INPUT, lOV RANGE
ANALOG INPUT. 20V RANGE

START CONVERSION

PIN
13

FUNCTION

,.

~~~~~

15
16
17
18
19

+5V P()AIER IN
BIT 1 OUT ('§131

20
21

~}
2.

BIT lOUT (MSB)

Bll 2 OUT
BIT 3 OUT
81T40UT
BIT 5 OUT
BIT60UT-taIT-7 OUT ----~BIT 8 OUT (LSB)

-bL

0.600
(15.2)
NOTE: Pins have a 0.025 inch. ±0.01
stand-off from case.

DATEL. Inc. 11 Cabot Boulevard. Mansfield. MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC~815, ADC~825
ADC-815

ABSOLUTE MAXIMUM RATINGS
Positive Supply .................
Negative Supply ................
Logic Supply ...................
Digital Inputs ...................
Analog Inputs ..................

I

ADC-825

+18V
-18V
+7V
+5.5V
±25V

POWER REQUIREMENTS
Analog Supply .................. ± 15V ±0.5V at 35 mA max.
- 15V ± 0.5V at 15 mA max.
Logic Supply ................... +5V ±0.25V at 100 mA max.
Power Dissipation ............... 1.25W max.
PHYSICAL/ENVIRONMENTAL

FUNCTIONAL SPECIFICATIONS
Typical at 25 'C, ± 15V dc and + 5V dc supplies, unless
otherwise noted.
INPUTS
Analog Input Ranges, 1 Unipolar ....
Bipolar .....
Input Impedance, 5VRange ......
10V Range ......
20VRange ......
Start Conversion ................

o to

+5V. 0 to +10V, 0 to
+20V
±2.5V, ±5V, ±10V
1.34K
2.3K
4.27K
+ 2V min. to + 5.5V max.
Positive Pulse 50 nsec. min.
duration, 10 nsec. typo rise and
fall times. Positive Going Edge
resets outputs to 011 ... 1 and
sets EOC high.
Negative going edge initiates

Operating Temp. Range, MC ......
MR
MM ......
Storage Temp. Range ............
Package Type ..................
Pins ..........................
Weight ........................

DoC to + 70°C
-25°C to +85°C
-55°C to +125°C
-65°C to +150°C
24 pin Ceramic DIP
0.010 x 0.018 inch Kovar
0.2 ounces (6 grams)

FOOTNOTES:
1. Unused analog inputs must be grounded.

2. At 15.9 MHz for the ADC-815, 9.52 MHz for the ADC-825.
3. The conversion time temperature coefficient for these converters is O.15%/oC.
This tempeo is positive.
4. Doubles outside this temperature range.

5. FSR is Full Scale Range.

conversion.

Loading: 2 TTL loads.
Bipolar Offset ................... Hold high (+5V) for bipolar
operation, hold low (ground)
for unipolar operation.

TECHNICAL NOTES

OUTPUTS
Parallel Output Data

.............

Serial Output Data ...............

Coding, Unipolar ................
Bipolar .................
--

EOC

..........................

Clock Output ...................

9 parallel lines (8 binary bits
plus MSB)
VOUT ("0") s + O.4V
VOUT ("1");" +2.4V
Loading: 4 TTL loads
NRZ format successive
Decision pulse output at
internal clock rate generated
during conversion. MSB first.
Loading: 4 TTL loads
Straight Binary
Offset Binary, Two's
Complement
Conversion Status Signal.
High ;" + 2.4V during
conversion and reset periods.
Lows +O.4V when conversion
complete.
Loadi ng: 4 TTL loads
Internal clock pulse train of
negative going pulses2 from
+5V to OV.
Loading: 6 TTL loads

PERFORMANCE
Conversion Time3 , max . .......... 700 nsec.

Resolution .....................
Nonlinearity ....................
Differential Nonlinearity . . . . . . . . . .
Gain Error ......................
Zero Error ......................
Gain Tempco, O'C to + 70'C'
Zero Drift ......................
Offset Tempco ..................
Long Term Stability ..............
No Missing Codes ...............
Power Supply Rejection, max ......

I

1 usec.
8 bits
±% LSB max.
±% LSB max.
±% LSB max.
±% LSB max.
± 20 ppm of FSR/oC max. 5
± 150 ,NloC max.
±15 ppm of FSRI"C Max. 5
±0.02% year
Over Operating Temp. Range
±0.06%1% Supply

1. The high operating speed of these converters requires that
good high frequency board layout techniques be used. Leads
from data outputs should be kept as short as pOSSible, output
leads longer than 1 inch (2.5 cm) require the use of an output
register. Use of a ground plane is particularly important with
high-speed data converters as it reduces high frequency
noise and aids in decoupling analog Signals from digital
Signals. Ground loop problems are avoided by connecting all
grounds on the board to the ground plane. The basic configuration of the ground plane directly below the ADC-815 or
ADC-825 is shown in the ground plane layout diagram. This
layout should be modified after selection of analog input
range to include unused analog inputs.
2. Analog input leads should be as short and direct as possible.
The use of shielded cable as an analog input lead will ensure
isolation of analog signals from environmental interference.
Unused analog inputs should be grounded.
3. Applications of the ADC-815 and ADC-825 that require an
input buffer amplifier may be satisfied by the use of DATEL's
AM-1435, an ultra fast hybrid device featuring a maximum
settling time of 85 nanoseconds.
4. Analog and digital supplies are internally bypassed to ground
with 0.01 j.tF capacitors; however, it is recommended that the
+15V, -15V and +5V supplies be additionally bypassed
externally with 1 j.tF electrolytic capacitors as shown in the
connection diagrams.
5. In the bipolar mode, two's complement output coding is available by using the MSB output (pin 16); offset binary coding is
obtained by using the MSB output (pin 17). Unipolar
operation requires use of the MSB output (pin 17) to achieve
straight binary output coding.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

1-107

ADC-815, ADC-825
BASIC GROUND PLANE LAYOUT
6. Serial output data is available at pin 1 in standard N RZ format
with the MSB appearing first. Coding is straight binary for
unipolar operation or offset binary for bipolar operation.
Synchronization of serial output data is achieved by use of
the ciock output (pin 13). Each data bit is valid when the clock
output is high and appears in succession from the MSB at the
second clock low to high transition to the LSB at the ninth
clock low to high transition.
7. Applications of these converters that require the use of a
sample-hold may be satisfied by DATEL:s model SHM-40,
an ultra-fast hybrid unit featuring 40 nanosecond acquisition
time and a ±2.5V input range.
8. These converters have a maximum power dissipation of
1.25W. The case-to-ambient thermal resistance for this package is approximately 33°C per watt. For operation in ambient
temperatures exceeding + 83°C, airflow of at least 400 linear
feet per minute is recommended.

~'2

13C!)
I

I

BOTTOM

I

VIEW

I

~,

DOT ON TOP
REFERENCES
PIN 1

24 I

THIS BASIC GROUND PLANE LAYOUT SHOULD BE
MODIFIED BEFORE IMPLEMENTATION TO INCLUDE
UNUSED ANALOG INPUTS.

TIMING DIAGRAM FOR ADC-815, ADC-825
OUTPUT: 10100001
START
CONVERT

HI_.~_
LO

=:J

HI

l

C,50 NSEC. MIN ..

: 'lL============~T'==============~I-L
~

LO=:LJ=40NSEC.TYP:

.OC
HI

!

CLOCK
OUTPUT

~T4

SERIAL DATA
OUTPUT
LD

~5

~T6

81Tl

I

~~

I

HI~

BIT HMSB)
OUT

81T 2
OUT

LO \ \ \ \ \1

HI~
LO

I

I

BIT B\lSBI
OUT

LlJ
-1

HI~

LO

~

NSEC. MAX

CODING TABLES

BIPOLAR OPERATION

UNIPOLAR OPERATION
UNIPOLAR
OUTPUT CODING'
SCALE
STRAIGHT BINARY
F.S. - 1 LSB
1111 1111
l> F.S
11000000
)I, F.S.
10000000
X F.S.
01000000
1 LSB
00000001
0
00000000
-FOR PARALLEL OR SERIAL OUTPUT

ANALOG INPUT
010 +SV 010 +10V 010 +20V
+4980V
+9961V +19.922V
+3.150V
+7.500V +15.OOOV
+2.500V
+5.OOOV +10.OOOV
+1.25OV
+2.5OOV +5.OOOV
+0.020V
+0.039V +0.078V
O.OOOV
O.OOOV
O.oooV
DATA

BIPOLAR
SCALE

OUTPUT CODING

INPUT VOLTAGE RANGE

OFFSET
lWO'S
BINARY' COMPLEMEN"
±2.5V
+F.S.-l LSB 11111111
0111 1111
+2.480V
+)I,F.S.
l100
01000000
+1.250V
+1 LSB
10000001
+0.020V
00000001
0
10000000
O.OOOV
00000000
-)I, F.S.
0100000c
11000000
-1.25OV
-F.S.+1 LSB 00000001
-2.480V
10000001
-F.S.
-2.5OOV
10000000
OOOOOOOC

000c

±5V

±10V

+4.961 V
+2.500v
+0.039V
O.OOOV
-2.5OOV
-4.961V
-5.OOOV

+9.922V
+5.000\1
+0.078V
o.oooV
-5.OOOV
+9.922V
+10.CJOCJIi

NOTES: 1. FOR PARALLEL OR SERIAL OUTPUT DATA
2. FOR PARALLEL OUTPUT DATA ONLY

1-108

DATEL, Inc. 11 Cabot Boulevard,Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-815, ADC-825
HIGH SPEED DATA SYSTEM

+15V

-15V

+15V

74S299
17

19

IMSSI

Bll'

18
19

16

BIT3

20

18

SHM-40

BIT 5

22

24

BIT 7
ILSSI

BITS (LSBI

3

-------,

r -------I
I
I

I
3.9KO

I
I

I

BIT6

23

-15V

OUTPUT
DATA BUS

81T4

21

ADC-815

lMSB)

BIT 2

'KO

:

lOp'

'KO

:

12

15

I
I
+5V

I

I

I

ENABLE
+5V

I

I

~---

-----------'
TTL INTERFACE CIRCUIT

START COMMAND

This diagram represents a high speed data system using DATEL's SHM-40 and ADC-815, with an output register, to drive
a data bus. The Start Command is a 60 nsec wide, TTL-compatible pulse with a maximum frequency of 1.5 MHz. Upon
receipt of a start command, the SHM-40 will track the input voltage and the ADC-815 will reset. On the trailing edge of t.he
start command, the SHM-40 will hold the input and the ADC-815 will begin its conversion. On the leading edge of the next
start command, the output data will be clocked out of the output three-state register. The ADC-815 is an 8-bit, 700 nsec,
analog-to-digital converter. With this system, a ±2.5V input step can be acquired to 0.1 % accuracy in 40 nsec and held to
within 80 pV while the AID conversion takes place. The SHM-40 can also be used with the DATEL's ADC-816, which will
yield 10 bits of resolution.

ORDERING INFORMATION
MODEL NO.

OPERATING
TEMP. RANGE

ADC-815MC
ADC-815MM

OOC to + 70°C
- 55°C to + 125°C

ADC-825MC
ADC-825MM

O°C to +70°C
-55°C to + 125°C

ACCESSORIES
Part Number

Description

DILS-3

Mating Socket, 24-pin socket

For military devices compliant with MIL-STD-883, contact
DATEL.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388lFAX (508) 339-6356

1-109

ADC-8.16. ADC-826
Ultra-Fast 10-Bit AID
Converters
FEATURES
• 1O-Bit resolution
• 800 Nanoseconds or 1.25 microseconds conversion time
• 6 Input ranges
• Unipolar and bipolar operation
• Programmable output coding

15V REF

r

Specifications shared by both models include maximum nonlinearity of ± % LSB
and differential nonlinearity of ± % LSB
maximum,
These converters are functionally complete units requiring a minimum of passive
external components for operation. Each
unit is composed of a high-speed comparator, an ultra-fast settling D/A converter, a precision voltage reference, successive approximation register, clock
generator and control logic circuits. The
combination of unique design and the
latest hybrid fabrication technology allows
this level of performance to be achieved in
a miniature hermetically sealed 32-pin
ceramic DIP package.
Both models require± 15V dc and +5V dc
supplies, and are available in versions for
the 0 to +70°C or -55 to +125°C
operating temperature ranges.

1-110

20~ (jj'

~

~
g

5000
FAST
SETTLING

CON~E~TER
2500

va

~l "N~:-.!. ~

r-@'SB
f-- ~
f-- '26
f-- ~~25

r-r-r--

RANGE

....J

PWR

r--

R~~}~~~2E

10V
11 _
:@

'lSV

CD P@R CD

RANGE..,!! - - -

1

f---

SUCCESSIVE

r--r--r-r---

APPROXIMATION
REGISTER

BIT 9

BIT

a

rr-

I

f--

22

81T4

20

BlTl

II

MSB

BIT 1

24

BIT 6

23

BIT 5

f_I""
r-

--'r--

BIPOLAR-----~-_~~=:t=::r:=:::f-=tll
tt~~'b~ (!:J-----l
fg~~~A~UTPUT
INPUT

These converters feature six analog input
voltage ranges: 0 to - 5V dc, 0 to - 10V
dc, 0 to - 20V dc, ± 2.5V dc, ± 5V dc and
± 10V dc. Selection of input range is
accomplished by simple external pin
connection.
Output data is available in parallel or serial
form by external connection. Data is
coded as straight binary for unipolar
operation and as either offset binary or
two's complement for bipolar operation.
Two's complement is available in the
parallel output mode only and is selected
by pin connection.

10VREF

N""AC
~

GENERAL DESCRIPTION
DATEL's ADG-S16 and ADC·S26 are very
high speed 10-bit successive approximation AID converters, realized as miniature
thick and thin-film hybrids. Both models
have identical specifications except for
conversion time. The ADC-S26 has a maximum conversion time of 1.4 microseconds. The ultra-fast ADC-S16 offers a
maximum conversion time of only SOO
nanoseconds.

at

-lOV REF

POCfS

1 KO

29

1

C~~~~2L

MSa

32 EOC

L_,-_J----+--~--t3G CLOCK OUT

S~T

COM~ATOA
GROUND

CONVERSION

INPUT /OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS

r-'.101 MAX--t
(2B.O)

I

O.15~~__

~

I

~

0.190 (4,9) MAX

-r

0.010.0.018 KOVAR

DOT ON TOP
REFERENCESPIN 1

116
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 ,

"
BOTTOM

I---

15 SPACES
at 0.100 EA
(2,5)

VIEW

32

0.900

(22,9)

11

---j

1.712
(43,5)

MAX

1. .

---a--

1_

0.100
(2,5)

"NOTE: PINS HAVE 0.025 INCH STANDOFF FROM CASE. ± O.Ot"

PIN

FUNCTION

PIN

I

POWER COM

17

FUNCTION
'SV POWER

2

REF OUT

18

MSB I

3

REF POWER

19

MSB I

4

-15V POWER

20

BIT 2

5

REF IN

21

BIT 3

6

SIG COM

22

BIT 4

7

COMPARATOR COM

23

BIT S

8

BIP IN

24

BIT6

9
10

5V IN

25

BIT 7

10V IN

26

BIT 8

II

20V IN

27

BIT 9

28

LSB 10

12

'15V POWER

13

NC

29

SERIAL DATA OUT

14

NC

30

CLOCK OUT

15

NC

31

START

16

NC

32

EOC

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-816, ADC-826
ABSOLUTE MAXIMUM RATINGS
Positive Supply, pin 12 . . . . . . . . . . . . . . . .
Negative Supply, pin 4 ..•....•........
Logic Supply, pin 17 ..................
Logic Inputs. . . . . . . . . . . . . . . . . . . . • . . . .
Analog Inputs .............•.........

POWER REQUIREMENTS
+ 16V dc
- 16V dc
+ 7V dc
+ 7V dc
± Twice selected analog
input range

FUNCTIONAL SPECIFICATIONS
Typical at + 25°C, ± 15V dc and + 5V dc supplies, unless otherwise
noted.

Analog Supply, pin 12 ................. + lSV dc ± lV dc at
106 rnA max.
pin4 .................. -lSVdc ±lVdcat
60 mA max.
Reference Supply, pin 3 ............... -lSV dc ±O.SV dc at
34 mA max.
Logic Supply, pin 17 .................. + SV dc ± 0.2SV dc at
80 mA max.
Power Dissipation •................... 1 .7 watts typical,
2.9 watts max.

INPUTS

PHYSICAL/ENVIRONMENTAL

Analog Input Ranges unipolar' .......... 0 to - SV, 0 to -10V, 0
to -20V
bipolar ........... ±2.SV, ±SV, ±10V
reference ..•...... - 9.SV to - 10.SV
Input Impedance'
5V range .......... 3121l
10V range ......... 62SIl
20V range .....•••. 1.2S KIl
bipolar input ......• 1 KIl
reference (pin 5) .... 2 KIl
Start Conversion .....••.............. 2V min. to S.SV max.
positive pulse with
duration of 2S nsec. min.
Rise and fall times typical
10 nsec. Logic "1" resets
converter. Logic "0"
initiates conversion.
Loading: 1 TIL load.

Operating Temp. Range Suffix C ....... 0°Cto +70°C
Suffix M .•...... - 55°C to + 12SoC
Storage Temperature Range ........... -6SoC to + lS0°C
Package Type •.......•.............. 32-pin hermetically sealed
Ceramic DIP
Pins ..........•....•..•...•.......• 0.010 x 0.018 inch gold
plated Kovar
Weight ............................. 0.8 ounces (23 grams)

FOOTNOTES:
1.
2.
3.
4.
5.

OUTPUTS
Parallel Output Data •............•.... 11 Parallel lines of data
(10 binary bits + MSB)
held until next conversion
command. Your ("0")
:5 +O.4V,Vour("l")
;,: +2.4V.
Loading: 2 TIL loads
Coding', unipolar ...•••...•.......... Straight Binary
bipolar" .•..............••... Offset Binary, Two's
Complement
Serial Output Data •....•.............. NRZ successive decision
pulses out, MSB first, at
internal clock frequency
Loading: 4 TIL loads.
End of Conversion (EOC) .............. Conversion Status Signal.
Output is logic high
during reset and
conversion, low when
conversion is complete.
Loading: 4 TIL loads.
Clock Output •................•...... Train of positive going, 0
to + SV, 30 nsec. pulses.
Clock Frequency ADC-816MC/MM .... ·14.6 MHz
ADC-826MC/MM •.•.. 8.1 MHz
Reference Output, Voltage ............. -10.00V ± 0.02V
Current ........•••.. 0 to + 20 mA (sink only)
Impedance ••••....•• lOll max. fo :5 10 MHz
PERFORMANCE
Resolution ...•........•...•......... 10 bits
Conversion Time", ADC-816MC ..•...• 800 nsec. max.
ADC-826MC/MM .... 1.4 "sec. max.
Nonlinearity ....•.....•...••...•...•• ± '12 LSB max.
Differential Nonlinearity•............... ± '12 LSB max.
Gain Error7 , before adjustment, unipolar .. ± 0.3% of FSR max.·
bipolar .•. ± 0.2% of FSR max.
Zero Error, before adjustment, unipolar ... ± 0.2% of FSR max.
Offset Error, before adjustment, bipolar •. ± 0.1 % of FSR max.
Gain Tempeo', unipolar ............... ± 37 ppm/oC max.
bipolar ...•....••...... ± 28 ppm/oC max.
Zero Tempeo, unipolar ................ ± 12 ppm/oC max.
bipolar ............•.... ± 23 ppm/oC max.
Conversion Time Tempco ......•••....• ± 0.1 %/OC
Reference Output Tempco .......•..... ± 20 ppm/oC max.
Power Supply Rejection ............... ±0.008%1% supply
No missing codes ..•....•......•..... Over operating Temp.
Range

6.
7.
8.
9.

Bipolar input must be tied to ground.
Resistance tolerance is - 30%, + 50%, ± 50 ppm/oe.
All coding is inverted analog.
Two's Complement Binary available for parallel output only.
Maximum conversion time is specified at full rated operating temperature. The
ADC-816MM has a maximum conversion time of 900 nanoseqonds at full rated
operating temperature. See Technical note 3 for 25°C conversion time.
Tested over full rated operating temperature range.
Includes Zero Error.
FSR is Full-Scale Range.
Includes internal reference TempeD. Given as a maximum for 5V FSR, these
values improve by 10% for 10V FSR, and by 20% for 20V FSR.

TECHNICAL NOTES
1. Use of good high frequency circuit board layout techniques is
required for rated performance. The power common (pin 1),
comparator common (pin 7), and signal common (pin 6) are
not connected internally, and therefore must be connected
externally as directly as possible, through a low resistance,
low inductance path. The extensive use of a ground plane for
all common connections is highly recommended. Also, it is
recommended that the analog and digital supplies, although
they are internally bypassed with 0.033 I'F capacitors, be additionally bypassed externally at the supply pins with 1 I'F
electrolytic capacitors.
2. The digital outputs are not buffered from their internal
application and so are sensitive to unusual loading or long
lines. Terminate these outputs with normal TTL inputs not
more than 3 inches from the data output pin. Analog inputs
must be non-reactive such that leads should be short and
purely resistive. The reactive component of any analog input
source, as seen at the analog input pin, should be less than
0.3% of the analog input resistance at that pin, for
frequencies below 20 MHz.
3. Conversion time is measured from the riSing edge of a 40
nanosecond start input pulse to the falling edge of the EOC
output. The conversion time is factory set at +25°C for the
ADC-816MC/MM at 750 nanoseconds and 1.25 microseconds for the ADC-826MC/MM. The worst case conversion time at the maximum rated operating temperature is
given as a maximum specification.
4. To use the internal reference, the reference supply pin (pin 3)
must be connected to the -15V supply. If the reference
supply pin (pin 3) is disconnected or grounded, the internal
reference will be disabled at a power saving of approximately
200 mW.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-111

ADC-816, ADC-826
5. Serial output data is available in NRZ format successive decision pulses, MSB first, in straight binary or offset binary coding. Synchronization of the serial output data is achieved
through the use of the clock output (pin 30). This same clock
output also controls the output register such that at the rising
edge of the output clock the previous data bit may be clocked
out. However, there will be no clock edge to clock out the
LSB. A Serial DATA Recovery circuit is diagrammed on the
applications page that will correct this.
6. These converters have a case-to-ambient thermal resistance
of 22°C per watt. At temperatures above + 70°C, an air flow
of at least 400 linear feet per minute is recommended. To

operate at elevated temperatures it is recommended that the
converter be mounted directly to the circuit board (without the
use of a mounting socket) and that good thermal contact be
established between the case bottom and the circuit board
ground plane by use of a silicone thermal joint compound
such as Wakefield Type 120 or equivalent.
7. Applications of these converters that require the use of a
sample-hold may be satisfied by DATEL's model SHM-HU,
an ultra-fast hybrid unit featuring 25 nanoseconds acquisition
time and a ± 2.5V input range.

APPLICATIONS
TIMING DIAGRAM FOR ADC-816, ADC-826
\I-------T,---------I

HI

START

CALIBRATION PROCEDURE

=:J [
~===============~--90
'0:
r. --u "'''MAX ~ ~20"'"'MIN --M40 nsee MIN

LO

HI

:

HI

....,

L :

1. Connect the converter as shown in the applicable connections diagram. A trigger pulse of between .40 nanoseconds
and 100 nanoseconds is applied to the start conversion input
(pin 31) at the rate of 200 kHz.
2. Zero and Offset Adjustments
Apply a preCision voltage reference source between the
appropriate input for the selected full scale range and ground.
Adjust the output of the reference source to the value shown
in the Calibration Table for the unipolar zero adjustment
(0 - '/2 LSB) or the bipolar offset adjustment ( + FS-1/2 LSB).
Adjust the appropriate timing potentiometer so that the output
code flickers equally between XOOOO 00000 and
XOOOO 00001. The MSB indicated by X will be 0 for straight
binary and offset binary coding or 1 for two's complement
output coding.
3. Full Scale Adjustment
Set the output of the voltage reference source used in step 2
to the value shown in the Calibration Table for the unipolar or
bipolar gain adjustment ( - FS + 1V2 LSB). Adjust the gain
trimming potentiometer so that the output code flickers
equally between X111111111 and X1111 11110. The MSB
indicated by X, will be 1 for straight binary and offset binary
coding or coding or 0 for two's complement output coding.
UNIPOLAR
INPUT
RANGE ADJUST. VOLTAGE
o To -5V
Zero
-2.4 mV
Gain
-4.9927V
OTo-l0V
Zero
-4.9 mV
Gain
-9.9854V
o To -20V Zero
-9.8 mV
Gain
-19.9707V

n

BIPOLAR
INPUT
RANGE ADJUST. VOLTAGE
±2.5V
Offset
±2.4975V
Gain
-2.4927V
Offset
±5V
±4.9951V
Gain
-4.9854V
Offset
±9.9902V
±'0V
Gain
-9.9707V

CLOCK
LO

:

i

HI
SERIAL
DATA OUT

La

BIT 1
MSB

BIT
2

HI~
LO

BIT
10
LSB

ljf=MAX

HI.

LoB
T,MAX

ADC·816MCIMM

800 n sec

44 n sec

23-64 n sec

1,4 /.1 sec

1UO n sec

79-114 n sec

ADC·826MC/MM

T,

CODING TABLES
UNIPOLAR OPERATION
INPUT RANGE
010 -20V 010 -10V 010 -5V
-19.9805
-9.9902V
-4.9951
-17.5000
-8.7500
-4.3750
-15.0000 -7.5000
-3.7500
-10.0000
-5.0000
-2.5000
-5.0000
-2.5000
-1.2500
-2.5000 -1.2500
-0.6250
-0.0198
-0.0098
-0.0049
0.0000
0.0000
0.0000

STRAIGHT BINARY
MSB
LSB
1111
11
1111
1110
00
0000
1100
00
0000
1000
00
0000
0100
00
0000
0010
00
0000
0000
00
0001
0000
00
0000

BINARY OPERATION
INPUT RANGE
±'0V
-9.9805
-7.5000
-5.0000
0.0000
+5.0000
+ 7.5000
+9.9805
+ 10.0000

1·112

T,

MODEL

±5V

±2.5V

-4.9902
-3.7500
-2.5000
0.0000
+2.5000
+3.7500
+4.9902
+5.0000

-2.4951
-1.8750
-1.2500
0.0000
+ 1.2500
+ 1.8750
+2.4951
+2.5000

OFFSET BINARY
MSB
LSB

TWO'S
COMPLEMENT
MSB
LSB

1111
1110
1100
1000
0100
0010
0000
0000

0111
0110
0100
0000
1100
1010
1000
1000

11
00
00
00
00
00
00
00

1111
0000
0000
0000
0000
0000
0001
0000

11
00
00
00
00
00
00
00

1111
0000
0000
0000
0000
0000
0001
0000

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-816, ADC-826
'15V '5V

BIPOLAR OPERATION

UNIPOLAR OPERATION

~6j~ ~j15_V-,\"r;K\'-I:~,~_~_ST___-<
20KlI
lOOI!

15V

HIGH SPEED THREE-STATE OUTPUT BUFFER
GROUND PLANE LAYOUT

UNCONDITIONAL/START CIRCUIT

r-

LESS THAN

3""1

.

FOR TWO'S COMPLEMENT
OUTPUT CODING

r--------...;~"""-"""-~-j;;---~
r--~-~A,>
r--~--

g~~T

)--+-------"'"

DMB095

y~~

AI

DM~~96" y<~

f--~--A6

Y6~

t-;;-;=~--Al

Yl~

LOT-'"':"1"---'

ADCB16
De
ADC826

31

IS PINCONNECTION
18 {MSBI
THIS

YJ~

Al

~jt-j-----~

~B","."-'O",C"-'~_ _

A3Gl

r--~--

A, DM80SS

G1

YJ~
y5t---------~

DUTPUTENABLE

USE OM 6096

fOR INVERTING THE
OUTPUT CODING

f--~--A1DM~~96' Yl~

SERIAL

DATA

1--~-~A6

Yo~

Yl~

L-_-----'
DATA OUTPUTS IN
HIGH IMPEDANCE STATE

OUTPUT
ENABLE CONTROL

AFTER 37 nsec MAXIMUM
DELAY, DATA APPEARS AT
OUTPUT

SERIAL
DATA RECOVERY
CIRCUIT

The Unconditional Start Circuit, shown for the ADC-816/826 insures the initiation of a conversion cycle upon the application of
one start pulse of 40 nanoseconds minimum pulse width
regardless of converter status.
The serial data output of the ADC-816/826 is converted into
parallel form, with the addition of an MSB output, by the
Serial Data Recovery circuit. Users should refer to technical
note No.2 on the loading of the ADC-816/826 digital outputs
when using these circuits.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-113

ADC-816, ADC-826

ADC-816/SHM-HU CONNECTION

GROUND PLANE LAYOUT

'"

INPUT

ECLIOOOO
LINE DRIVER

When the ADC-816 or ADC-826 is configured as shown here with
DATEL's SHM-HU hybrid sample-hold, a ±2.SV input step can be acquired to 0.1 % accuracy in 30 nanoseconds and held to within 40 I'V
while the AID conversion takes place. Use of the SHM-HU reduces the
time over which the input signal is averaged to a few nanoseconds (an
AID converter without a sample-hold averages the analog input signal
over the total conversion time of the AID).

ORDERING INFORMATION
OPERATING
TEMP. RANGE

MODEL NO.
ADC-816MC
ADC-816MM

O°C To + 70°C
-SsoC To +12SoC

ADC-826MC
ADC-826MM

-O°C To +70°C
-SSoc To +12SoC

ACCESSORIES
Part Number
DILS-2
TP20K, TP100,
TPSO

Description
Mating Socket (2 per converter)
Trimming Potentiometers

For military devices compliant to MIL-STD-883, consult
DATEL.

1·114

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-817 A,

ADC-827 A
Fast 12-Bit
AID Converters

•

FEATURES
12-Bit resolution
2 Microseconds or 3 microseconds
conversion times
Unipolar and bipolar operation
6 Programmable input ranges
Parallel data output
GENERAL DESCRIPTION
The ADC-817A and ADC-827A are highspeed two-pass AID converters in miniature
hybrid from using thick-and thin-film hybrid
technology. Both models have identical
specifications except for conversion times.
The ADC-827 has a maximum conversion
time of 3.0 microseconds, while the ADC817A accomplishes a 12-bit conversion in
only 2.0 microseconds, maximum.
These converters feature six analog input
voltage ranges: 0 to -5V dc, 0 to -1 OV dc, 0
to -20V dc, ±2.5V dc, ±5V dc, and ±1 OV dc.
Selection of input range is accomplished by
simple external pin connection. Both devices provide a user-selectable, fast settling
precision input buffer with input impedance
of 100MO, allowing them to be driven directly from a high impedance source. The input
buffer may be bypassed.
Output data is coded as straight binary for
unipolar operation and as either offset binary
or two's complement for bipolar operation.
Specifications shared by both models include maximum nonlinearity of ±1 LSB maximum and a gain tempco of 25 ppml DC maximum.

Figure 1.

ADC-817 A,-827 A Simplified Block Diagram

MECHANICAL DIMENSIONS
INCHES (mm)
1.101 MAX
(28,0)

~0.010 X 0.Q18 ~
KOVAR Pins

These converters are functionally complete
units requiring a minimum of passive external components for operation. Each unit is
composed of a fast settling precision input
buffer, an ultrafast settling D/A converter, a
precision voltage reference, clock generator
and control logic circuits. The combination
of unique design and the latest hybrid fabrication technology allows this level of performance to be achieved in a minature, hermetically sealed 32-pin ceramic DIP package.
Both models require ±15V dc and +5V supplies, and are available in versions for the 0
to 70°C or -55 to + 125°C operating temperature ranges.

NO CONNECTION

ANAGND

,16

17

,

,,,
,,,
:

BOTTOM

:

VIEW

,

,,,
,,
,

!

32

0.190 MAX

IT
Tl
15
SPACES
ATO.l00
(2,5)

1.712 MAX.
(43,5)

--bl

0.900
(22,9)
NOTE: Pins have a 0.025 inch, ±0.01
sland·off from case.

1/0 CONNECTIONS
PIN

FUNCTION

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

BIT 12 OUT (LBS)
BIT 11 OUT
BIT 100UT
BIT 9 OUT
BIT80UT
BIT 7 OUT
BIT60UT
BIT50UT
BIT 40UT
BIT30UT
BIT20UT
BIT 1 OUT (MSB)
BIT 1 OUT (MSB)
NO CONNECTION
DIGITAL GROUND
+5V POWER
NO CONNECTION
REFERENCE OUTPUT
NO CONNECTION
EOC OUTPUT
START CONVERSION
SUMMING JUNCTION
BIPOLAR OFFSET
5/10V INPUT RANGE
20V INPUT RANGE
ANALOG GROUND
REFERENCE INPUT
+ 15V POWER
BUFFER OUTPUT
BUFFER INPUT
·15V POWER
NO CONNECTION

24

25
26
27
28
29
30
31
32

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-115

ADC-817A, ADC-827A
ABSOLUTE MAXIMUM RATINGS
Positive Supply............................ + 18V
Negative Supply........................... -18V
Logic Supply................................... + 7V
Digitallnputs ................................... +5.5V
Analog Inputs ................................ ±20V
Buffer Amplifier Input. ............. ±15V

FUNCTIONAL SPECI FICATIONS
Typical at 25 "C, ±15V supplies, unless otherwise noted.

INPUTS
Analog Input Ranges Unipolar ........ 0 to -5V, 0 to -10V, 0 to -20V
Bipolar............................................ ±2.5Vm ±5V, ±10V
Input Impedance
5V/10V Ranges ........._................. 1.05 KQ
20V Range .................................... 4Q
Start Conversion ......................... 2V min. to 5.5V max. positive
pulse with duration of 50 nsec.
min. Rise and fall times <30
nsec. Logic "1" to "0" transition initiates next conversion.
Logic. ~,e~els:
.
Logic 1 ........................................ 2.4V min.
Logic "0" ........................................ O.4V max.
Logic Loading:
Logic"1"........................................ -160 ~ max.
Logic "0" ........................................ 6.4 mA max.
Buffer Amplifier Gain ................. ±1
Buffer Amplifier Input Voltage ......... ±1 O.OV
Buffer Amplifier Input Impedance ... 100 MQ
Buffer Amplifier Settling Time' ........ 500 nsec. max.

POWER

REQUIREMENTS

Supply Voltage ............................ +15V dc ±O.5V at +70 mA max.
-15V dc ±0.5V at -50 mA max.
+5V dc ±0.25V at +65 mA
max.
Power Dissipation ....................... 2.2 W max.

PHYSICAL/ENVIRONMENTAL
Operating Temp. Range,
MC ................................. 0"Cto+70"C
MM ................................ -55 "Cto+125"C
Storage Temp. Range .............. -65"C to +150"C
Package Type ............................... 32 pin hermetically sealed ceramic DIP
Pins.................................................... 0.01 0 x 0.018 inch Kovar
Weigh!... ........................................... 0.5 ounce (14 grams)
FOOTNOTES
1.

10V step to 0.01%, 5V and 20V steps settle to 0.01%
in 150 nanoseconds and 800 nanoseconds, respectively.
2. These converters operate with inverted analog, that is
F.S. + 1 LSB is encoded as 1111 1111 1111 and +FS
is encoded as 0000 0000 0000 (examples given are
for offset binary coding).
3. Parallel output data only is available in offset binary
(uses MSB out) or two's complement coding (uses
MSB out).
4. For DoC to + 70°C operation, these values double outside of this temperature range.
5. FSR is Full Scale Range.

OUTPUTS

TECHNICAL NOTES

Parallel Output Data .................. 13 parallel lines (12 binary bits
plus MSB) valid from negative
going edge of EOC pulse to
positive going edge of START
CONVERSION pulse. Vout
"0":;; +0.4V VOUT "1";" +2.4V
Loading: 4 TIL loads
Coding:
Unipola,'........................................ Straight Binary
Bipolar'.......................................... Offset Binary, Two's Complement3
End of Conversion (EOC) ................ Conversion Status Signal: 4
TIL Loads VOUT "0":;; +O.4V for
conversion complete VOUT "1" :;;
+2.4V for conversion in
progress

1. The high operating speed of these converters requires
that good high frequency board layout techniques be
used. Capacitance from long leads on the data outputs
can prevent the internal DAC from turning on in time,
creating linearity errors. Leads from data outputs
should be kept as short as possible, output leads longer than 1 inch (2.5 cm) require the use of an output register. Ground loop problems are avoided by connecting all grounds on the board to the ground plane.
Analog and digital grounds are connected internally.

PERFORMANCE
Resolution ...................................... 12 binary bits'
Nonlinearity, max ........................ ±1 LSB
Differential Nonlinearity, max ........... ±1 LSB
Temp. Coeff. of Gain, max· .... ±25 ppm/"C of FSR
Temp. Coeff. of Zero,
unipolar max ................................. ±150 IlV/"C of FSR
Temp. Coeff. of bipolar, zero
error, max4 ............................ .. .. ±15 ppm of FSRI "CO
Diff. Nonlinearity Tempco, max ....... ±5 ppm/"C of FSR
Power Supply Rejection ......... ±0.01%1% Supply max.
Conversion Time Over
Full Temp ....................................... 2.0 Ilsec. max., ADC-817A
3.0 Ilsec. max., ADC-827A

1-116

2. Analog input leads should be as short and direct as possible. The use of shielded cable as an analog input
lead will ensure isolation of analog signals from environmental interference.

3. The ADC-817A/827A provides an internal buffer amplifier. Use of this buffer provides an input impedance
greater than 100 MQ, allowing the AID to be driven
from a high impedance source or directly from an analog multiplexer. When using the input buffer, a delay
equal to its setting time must be allowed between input
level change and the negative going edge of the start
conversion pulse. If the buffer is not required,,its input
should be connected to analog ground to avoid introducing noise in to the converter.

4. Both analog and digital supplies should be bypassed to
ground with 1 I1F electrolytic capacitors in parallel with
0.1 I1F ceramic capacitors as shown in the connections
diagrams. Bypass capacitors should be located directly

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-817A,
adjacent to, or on, each supply pin. The -10V reference output (pin 18) should be bypassed to ground with a 2.2 ~F
electrolytic capacitor mounted as previously indicated.
5. In the bipolar mode, two's complement output coding is available by using the MSB output (pin 13); offset binary coding
is obtained by using the MSB output (pin 12). Unipolar operation requires use of the MSB output (pin 12) to achieve
straight binary output coding.

ADC-827A

NOTE
In any application using the ADC-817A or the ADC827A, signal integrity and noise isolation are a function
of grounding. The suggested ground plane shown
should be used whenever possible.

•

GROUND PLANE LAYOUT
6. Applications of these converters that require the use of a
sample-hold may be satisfied by DATEL's model SHM-45 or
SHM-4860 featuring 200 nanosecond acquisition time and
0.01% accuracy. The SHM-45 offers gains of -1 or -2.
7. These converters have a maximum power dissipation of
2.2W. The case--to-ambient thermal resistance for this package is approximately 28°C per watt. For operation in ambient
temperatures exceeding +70°C, care must be taken to ensure free air circulation in the vicinity of the converter.

TIMING DIAGRAM
OPERATING PERIODS
ADC-817A
T1 2.0

ADC-827A

~SEC.

3.0 ~SEC.

2~
I

Figure 3.

Ground Plane Layout

50 n5ecMINUMUM

----------------------------------------

- : 1_30nsec
EOG

I

1______________ ________________1

--I:...J

(S:...TA__
TU'-'S__

PARALLEL
DATA NOW

I

T1

I

.

VALID

I

I

I
I

I

I

I

I

25 nSec

r- MINIMUM

!
OUTPUTDATA_

DATAVAUO

Figure 2. Timing Diagram for ADC-817A, ADC-827A
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-117

ADC-817A, ADC-827A
OUTPUT CODING
UNIPOLAR
UNIPOLAR ANALOG INPUT
SCALE
20V RANGE -10V RANGE -SV RANGE
-FS + 1 LSB
-7/8 FS

-3/4 FS
-1/2 FS
-1/4 FS
-1 LSB
0

BIPOLAR
SCALE
-FS + 1 LSB
-1/2 FS
-1 LSB
0
+1 LSB
+1/2 FS
+FS -1 LSB
+FS

-19.9952V
-17.5000V
-15.0000V
-10.0000V
-5.0000V
-0.0049V
-O.OOOOV

-9.9976V
-8.7500V
-7.5000V
-5.0000V
-2.5000V
-0.0024V
-O.OOOOV

-4.9988V
-4.3750V
-3.7500V
-2.5000V
-1.2500V
-0.0012V
-O.OOOOV

ANALOG INPUT
±10V RANGE ±SV RANGE
±2.SV RANGE
-9.9951 V
-5.0000V
-0.0049V
O.OOOOV
+0.0049V
+5.0000V
+9.9951V
+10.0000V

-4.9976V
-2.5000V
-0.0024V
O.OOOOV
+0.0024V
+2.5000V
+4.9976V
+5.0000V

-2.4988V
-1.2500V
-0.0012V
O.OOOOV
+0.0012V
+1.2500V
+2.4988V
+2.5000V

STRAIGHT BINARY
OUTPUT CODE
1111
1110
1100
1000
0100
0000
0000

1111
0000
0000
0000
0000
0000
0000

1111
0000
0000
0000
0000
0001
0000

DATA OUIP JT r.OnlNr.
TWO's
OFFSET
BINARY
COMPLEMENT
1111
1100
1000
1000
0111
0100
0000
0000

1111
0000
0000
0000
1111
0000
0000
0000

1111
0000
0001
0000
1111
0000
0001
0000

0111
0100
0000
0000
1111
1100
1000
1000

1111
0000
0000
0000
1111
0000
0000
0000

1111
0000
0001
0000
1111
0000
0001
0000

Providing Three-State Outputs
For applications where the converted input must interface to tristate TTL or CMOS logic, the ADC-817A OR ADC-827A outputs are easily converted using buffers such as the DM8095's
shown in the diagram. Signal length must be less than one inch
between devices to ensure signal integrity. Also note that
two's complement outputs are available from the ADC-817A
and ADC-827 A by using pin 13 instead of pin 12 as the MSB
output. The timing diagram shows the delays incurred as the
signal passes through the buffers.

hss~
."
"

A5

10

A2

DMB095

"

Y5
Y6

BIT60UT
BIT 6 OUT

G'
Aoe-817
OR
ADC..s27
81T7 OUT

G'

DATA OUTPUTS IN
HIGH IMPEDANCE STATE

Y3
A5

OUTPUT ENABLE

CONTROL

Y5

A2 DM8095 Y2
A6

Y6

'FOR TWO'S COMPLEMENT OUTPUT CODING THIS CONNECTION IS PIN 13 (MSs)

Figure 4_
High Speed
Three-State Output Buffer
1-118

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194iTEL (508) 339-3000iTLX 174388/FAX (508) 339-6356

ADC-817A,
CALIBRATION

TYPICAL CONNECTIONS

ADC-827A

PROCEDURE

1. Connect the converter as shown in the applicable connections diagram. A trigger pulse of 50 nanoseconds
minimum is applied to the start conversion input (pin 21)
at a rate of 200 kHz.

UNIPOLAR
OPERATION

2. Zero and Offset Adjustments

11 BIT2

AOC-S17A

OR

ADC·827A

9 81T4

8 81TS

PARALLEL

7 81T6

DATA
OUTPUTS

6 BIT7

l

BIT 10

GAO •
.6.OJUST

Apply a precision voltage reference source between
the appropriate input for the selected full scale range
and ground. Adjust the output of the reference source
to the value shown in the Calibration Table for the unipolar zero adjustment (0 -112 LSB) or the bipolar offset
adjustment (+FS -1/2 LSB). Adjust the appropriate trimming potentiometer so that the output code flickers
equally between XOOO 0000 0000 and XOOO 0000
0001. The MSB, indicated by X, will be 0 for straight binary and offset binary output coding, or 1 for two's complement output coding.

3. Full Scale Adjustment

'FOR GREATER UNIPOLAR ZERO GAIN ADJUSTMENT THE 2 MEG OHM
RESISTOR MAY BE REDUCED TO A VALUE OF 500 KO

Set the output of the voltage reference source used in
step 2 to the value shown in the Calibration Table for the
unipolar or bipolar gain adjustment (-FS + 1 1/2 LSB).
Adjust the gain trimming potentiometer so that the output code flickers equally between X 1111 1111 1111
and X111 1111 1110. The MSB, indicated by X, will be
1 for straight binary and offset binary output coding, or 0
for two's complement output coding.

BIPOLAR
OPERATION

CALIBRATION TABLE

19

~gNNECTION

J2

~gNNECTION

DAC-817A

UNIPOLAR
RANGE

INPUT VOLTAGE

OTO-5V

ZERO
GAIN

-0.6mV
-4.9982V

OTO -10V

ZERO
GAIN

-1.2mV
-9.9963V

OTO ·20V

ZERO
GAIN

-2.44mV
-19.9925V

±2.5V

OFFSET
GAIN

+2.4994V
-2.4982V

±5V

OFFSET
GAIN

+4.9988V
-4.9963V

±10V

OFFSET
GAIN

+9.9976V
-9.9927V

PARALLEL

OR

ADJUST

DATA
OUTPUTS

AOC-827A
4

91T9

BIPOLAR RANGE

BIPOLAR OFfSET
ADJUST

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-119

•

ADC-817A,

ADC-827A

GAIN RESISTOR

ACC-S17A
OR

ADC-827A

~I

SHM~
OUT A

CHANNEl
INPUTS

10V INPUT

MX-1818

OUrB
1 START
CONVERSION

MUX
lHH18

DELAY STROBE

CAO CA' CA2 CA3

Figure 5.

High Speed Data Acquisition System

The ADC·817A/827A configured as shown with DATEL's MX·
1616, a high speed CMOS multiplexer, AM-551, a hybrid precision programmable gain instrumentation amplifier, and SHM4860, a 200 nanosecond, 0.01% hybrid sample hold forms an
8-channel (differential), 12-bit, hight speed data acquisition system capable of throughput rates of 200 kHz.

INPUT CONNECTIONS
INPUT
VOLTAGE
RANGE

oto -5V
o to -10V
±2.5V
±5V
±10V

·WITH INPUT BUFFER
INPUT CONNE(;T THESE
PIN
PINS TOGETHER
30
30
30
30
30

29
29
29
29
29

to
to
to
to
to

24
24
24
24
25

WITHOUT INPUT BUFFER
CONNE(;I THI::sE
INPU I
PIN
PINS TOGETHER

22 to 25

24
24
24
24
25

22 to 25

-

22 to 25

-

22 to 25

-

-

ORDERING
MODEL
ADC-817A
ADC-817A
ADC-827A
ADC-827A

30
30
30
30
30

to
to
to
to
to

26
26
26
26
26

INFORMATION
TEMP. RANGE

MC
MM
MC
MM

QOCto+70°C
-55 °C to +125 °C
0°Cto+70°C
-55 °C to +125 °C

ACCESSORIES
Part Number

Description

TP25K or TP1 OOK

Trimming Potentiometers

For military devices compliant to MIL-STD-883, consult the factory.

1-120

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC·830
Microprocessor·Compatible
8·Bit AID Converter

•
I

FEATURES
• Microprocessor-compatible

• ± Yo lSB total adjustment error
• 100 Microseconds conversion time
• Differential analog inputs
• Ratiometric operation
• Single-supply operation

DIGITAL

3_ jfu 0L
r-------~-~-

--l

GENERAL DESCRIPTION

DATEl's ADC-830 is a low cost, 8-bit,
CMOS AlD converter designed to operate
directly with the 8080A control bus via
three-state outputs. The device appears
as a memory location or I/O port to the
microprocessor and thus does not require
interfacing logic. The ADC-830's digital
control inputs, CS, RD, and WR, are active
low, and are available in all microprocessor memory systems. Upon completion
of a conversion, an Interrupt signal is generated at the converter's output. The
ADC-830 will operate as a normal AID for
non-microprocessor based applications.

I

.--8

----8

DB7IMS8'
DBB

~DBb

Using the successive approximation technique and a modified potentiometric
resistor ladder, the ADC-830 achieves an
8-bit conversion in 100 microseconds with
a maximum total adjusted error of only
± Yo lSB. No zero adjust is required. Also,
the differential analog input allows the user
to increase the common mode rejection
and offset the zero value of the analog
input.
Other features include single supply operation and an internal clock generator. The
clock generator requires only an external
RC network or, it may be driven by an external clock. The clock frequency range is
100 kHz to 1.2 MHz. In addition, the
ADC-830 operates ratiometrically or with a
2,5V dc, 5V dc, or, to allow the encoding of
smaller analog input voltage ranges, an
analog-span-adjusted reference.
The ADC-830 is packaged in 20-pin plastic
DIP and operates over the O°C to + 70°C
commercial temperature range. Power requirement is + 5V dc. With it's combination of low cost, small size, ease of digital
interfacing, and versatility of analog interfacing, the ADC-830 is the ideal choice for
many process control and instrumentation
applications.

INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (MM)

PIN

FUNCTION

1

CS (CHIP SELECT)

11

DB 7 (MSB)

2

RD (READ STROBE)

12

DB 6

3

WR (WRITE STROBE)

13

DB 5

PIN

PIN I
IDENT

FUNCTION

4

CLOCK IN

14

DB 4

5

INTERRUPT

15

DB 3

6

+ ANALOG IN

16

DB 2

7

- ANALOG IN

17

DB 1

8

ANALOG GROUND

18

DB 0 (LSB)

9

SPAN ADJUST

19

CLOCK RETURN

10

DIGITAL GROUND

20

+VSUPPLY

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 1743881FAX (508) 339-6356

1-121

ADe-830
ABSOLUTE MAXIMUM RATINGS
Supply Voltage. . . . . . . .. . . . . ...
Digitallnput Voltage ............
Analog Input Voltage. . . . . . . . . ..
Package Dissipation ...........

PHYSICAL/ENVIRONMENTAL
+ 6.5V
- 0.3V to + 18V
- 0.3V to (Vs + 0.3V)
875 mW

FUNCTIONAL SPECIFICATIONS
Typical at + 25°C, + 5V dc supply voltage, unless otherwise noted.
ANALOG INPUTS
Analog Input Range' ...........
Common Mode Voltage Range ...
Common Mode Rejection,
dc, max.
Input Resistance, Span Adjust,
min ........................

...................

- 0.05V to + Vs + 0.05V
Gnd to + Vs
±2A4 mV

2.5 kG

DIGITAL INPUTS
Input Logic Level, Vin (" 1 ")2 ....•
Input Logic Level, Vin("0")3 .....
Clock IN Threshold Voltage",
Pos........................
Neg ........................
Clock IN HysteresiS< ............
CS (Chip Select) ...............

+2.0V min. to +15V max.
+0.8V max.

+2.7V min. to +3.5V max.
+ 1.5V min. to +2.1V max.
+ 0.6V min. to + 2.0V max.
Active low state, enables the
ADC-830 for read and write
operations.
WR (Write Strobe) .............. Start conversion pulse. Input low
of 100 nsec. min., in conjunction
with a low on CS, resets SAR.
_
and shift register.
RD (Read Strobe) .............. Ouput enable pulse. Input low, in
conjunction with a low on CS,
enables three-state outputs. Max.
enable delay is 200 nsec.
Digital Input Capacitance, max. .. 7.5 pF
DIGITAL OUTPUTS
Parallel Output Data ............ 8 parallel lines of three-state,
gateable output data.
INT (Interrupt) ................. Device status signal. Low when
conversion complete. High when
conversion in progress and when
output data enabled.
Output LogiC Level,
Vout("I")' ................. + 2AV min. at - 360 pA
Vout ("0")6 ................. + OAV max. at 1.6 mA
Output Short Circuit Current,
Gnd, min. . ................. 4.5 mA
Vs., min.................... 9.0 mA
Off-State Output Current ........ ±3 pA
Digital Output CapaCitance, max .. 7.5 pF
PERFORMANCE
Resolution ...................
Total Adjusted Error7 , max .......
Conversion Times ............. ,
Conversion Rate., max..........
Clock Frequency Range' •.......
Output Enable Delay", max ......
Three-State Control Delay", max.
Interrupt Output Delay, max ......
Power Supply Sensitivity'3 ......

8 binary bits
± '12 LSB
100 ~sec.
8770 CPS
100 kHz to 1.2 MHz
200 nsec.
250 nsec.
450 nsec.
±2A4 mV

POWER REQUIREMENTS
Supply Voltage Range .......... + 4.5V dc to + 6.3V dc
Supply Current, max. . . . . . . . . . .. 1.8 mA

1-122

Operating Temperature Range ... OOC to 70°C
Storage Temperature Range ..... - 65°C to + 150°C
Package Type ................. 20 pin plastic DIP
FOOTNOTES
,. When - Analog IN (Pin 7) is '" + Analog IN (Pin 6), the digital qutput code will
be 0000 0000. Two internal diodes are connected to each analog input which
will forward conduct for input voltages one diode drop below ground or above

2.
3.
4.
S.
6.
7.
8.

Vs.
Vs = +S.2SVdc,atVs = +SVdc, high level input current = 1 ~maximum.
Vs = +4.7SVdc,atVs = +SVdc, low level input current = 1 ~maximum.
Clock IN (Pin 4) is the input of a Schmitt Trigger circuit.
Vs = +4.7SV. ForVout("I") = 4.SV high level output current = -10~.
Vs = + 4.7SV. Low level output current for the Interrupt Output is 1.0 mAo
Specified after full-scale adjustment.
With an asynchronous start pulse, up to 8 clock periods may be required
before conversion starts.

9. Conversion rate in free-running mode; INTR (Pin S) connected to WR (Pin 3),
CS (Pin 1) = OV, and folk = 740 kHz.
10. Vs = +6V. Clock frequency range at Vs = +SV is 100 kHz to 800 kHz.
11. C, = 100 pf, use bus driver for large C,.
12. C, = 10 pf, R, = 10 KIl.
13. Vs = + SV ± 10% over full analog input range.

TECHNICAL NOTES
1. The digital control inputs (CS, RD, and WR) are active low to
allow easy interface to microprocessor control busses. For
non-microprocessor based applications, the CS input (Pin 1)
can be grounded and the standard AID START function is
obtained by an active low pulse on the WR input (Pin 3) and
the Output ENABLE function is obtained by an active low
pulse on the RD input (Pin 2).
2. The ADC-830 has a differential analog voltage input (Pins 6 &
7). The switching time between the inputs is 4.5 clock
periods. The maximum error voltage due to this sampling
delay is tJ.V e (maximum) = (Vp) (21rfcm) (4.5/fclk) where: tJ.Ve
is the error voltage due to sampling delay, Vp is the peak
value of the common-mode voltage, and fcm is the commonmode frequency. Because of this internal switching action,
displacement currents will flow at the analog inputs. These
current transients occur at the leading edge of the internal
clock, rapidly decay, and do not cause errors as the comparator is strobed at the end of the clock period. However, if
the voltage source applied to Ana. IN + (Pin 6) exceeds Vs
by more than 50 mV, a large current may flow through a
parasitic diode to Vs. If these currents could exceed 1 mA,
an external diode should be connected between Ana. IN +
(Pin 6) and Vs (Pin 20).
3. The leads to the analog inputs should be kept as short as
possible to prevent noise pickup. The source resistance for
these inputs should be kept below 5 kO. Input bypass
capacitors should not be used as they will average the transient input svyitching currents of the converter causing scale
errors.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

Ace-830
7. The ADC-830 will require a bus driver when the total capacitance of the data bus gets large. For systems with a slow
CPU clock frequency, higher capacitive loads may be driven.
low power Schottky or high current bipolar bus drivers with
PNP inputs are recommended.
8. The use of good circuit board layout techniques is required
for rated performance. Sockets on a PC board should be
used, all logic signal leads should be grouped and kept as far
as possible from the analog inputs, and the analog inputs
should be shielded. A single point analog ground should be
used that is separate from the digital ground. Vs should be
bypassed, as close to the Vs pin as possible, with a low inductance 1 I'F tantalum capacitor. The Vs bypass capacitor
and self-clocking capacitor (if used) should be returned to
digital ground.

4. The ADC-830 may be used with a 5V, 2.5V or adjusted voltage reference. The reference is either % the value of Vs or
equal to a voltage applied to the span adjust pin (Pin 9). This
allows for operation in either a ratiometric mode or an absolute mode. The internal gain for the span adjust input is 2.
5. The clock for the ADC-830 may be derived from the CPU or
an external RC can be added to provide self clocking. A
resistor ( ~ 10 k!l) is connected between ClK Return (Pin 19)
and CLOCK IN (Pin 4) and a capacitor is connected between
CLOCK IN and ground. The resultant clock frequency is folk
= 1/1.1 RC. Heavy capacitive or dc loading of the Clock
Return pin should be avoided, a CMOS or low power TTL
Buffer should be used to drive loads greater than 50 pF.
6. For continuous conversion operation, the CS input (Pin~
grounded and the WR in~in 3) is connected to the INTR
output (Pin 5). WR and INTR should be momentarily forced
low following a power-up cycle to guarantee operation.

TYPICAL PERFORMANCE CHARACTERISTICS
eLK IN SCHMIIT TRIP LEVELS

FULL-SCALE ERROR VStC~K

VS SUPPLY VOLTAGE

"
CD

7

~
a:

5

w

~

IE

V,
4

-'
-'
=>
LL

9o 2.7 1-1-"'+++-+-I--H-+-+-+-+--1
C·C -'- TA "-"_ + 70'C

"'~ HH--+-+-++-+--+-+-+-H

IL

2.3

iO

2

1. r-r- l-

lL:

;;; 1.9

v,
400

800

--

H-+v,<,1,j-.-+I-"'+~o!"""F-+-+-H
..

3.'

I

3

()

"'

'~~"

r-

LL

5V

v,

W

;i,

4.5V

1200

1600

:5

6V

I---H--+--++~~V';.'''i''""'t....
==t--+--1
~I-

()

1.5 L-L.....J-+-+---'-----'----'----'---'----'---J.......J
4.50
4.75
5.00
5.25
5.50

2000

fCL~(kHz)

Vs -

1.

Vr

1,8

~

~ 17

r--+

~

"is

1.6

i

~ 1.5
fo-

=>

14

t

,

I--

r-~-

()

ag 1.34.50

4,75

---

500

r-

~

r-

2.4

2,0

<>-------+
r------------------

INT(141

ii"OWR(2n'

,..----------------_IIORD(25)"
10K

I

1

cs

-t

REi
eLK IN

~
6

fNf

ADC-830

+IN

7

LlZOpti

IT,:,

elK R

ViR

4

ANALOG
INPUTS

Vs

~

~1Of'

t~~::::::~_...:..L,:,:.-+ DBO(13),
DBl (16),

DB2

16

DB2 (111'

DB3

15

DB3 (9)'

14
13

D84(5)'

AGND

DB5

SPAN ADJ

D86

12

DB6 (201"

OGND

DB7

l'

OS70)"

L
t: ~:

t

I

DBOr:
DBt 17

DB4

-IN

cfo

~+5V

OUT

T3

~~

TO

OBS{18r

Vee

DMS131
BUS

COMPARATOR

B5

AD15(36)

B4

AD14 (39)

B3

AD13(38)

B2

AD1213n

B1

AD11 (40)

BO

ADIOII)

The ADC-830 is designed to interface directly with derivatives of the 8080 flP. The converter can be mapped
into memory space using standard memory address
decoding, or it can be controlled as an 110 device by
using the 1/0 Rand 1/0 W strobes and decodi!!9.address bits AO - Al (or A8 - A15) to obtain
the CS input. Using the 1/0 space provides 256 additional addresses and may allow a simpler 8-bit address
decoder but the data can only be input to the accumulator. In systems where the AID converter is 1 of
8 or less 1/0 mapped devices, no address decoding circuitry is required. Each of the 8 address bits (AO to Al)
can be directly used as CS inputs, one for each 1/0
device.

L..--r---r--...J

NOTE 1: 'PIN NUMBERS FOR THE INsa228 SYSTEM CONTROLLER,
OTHERS ARE INS8080A
NOTE 2 PIN 23 OF THE INsa22S MUST BE TIED TO +12V
THROUGH A lKU RESISTOR TO GENERATE THE
RSTl INSTRUCTION WHEN AN INTERRUPT IS
ACKNOWLEDGED AS REQUIRED BY THE ACCOMPANYING
SAMPLE PROGRAM

MC 6800 CPU INTERFACE
. - - - - - - - - - - - - - - - - - - _ ffiol'll" 101 "

.----------<>< 1-.-..10-----...

RWI341161

1"'-----....

00/3311311

1-":-----....

0113211291

r.;::.----....

1"'-----....
E - - - -....

1"'-----.

0213111KI

D3(3011HI

04(2911321
D5(2811301

Fo----+

061271111

(0'-'-----+

071261iJi

1-'-----04

A12 (22! 13<11

1"-----04

A141]411MI

The control bus for the 6800 flP derivatives does not
use the RD and WR strobe signals. Instead it employs
a single RtW line and additional timing, if needed, can
be derived from the 02 clock. All 1/0 devices are
memory mapped in the 6800 system and a special
signal, VMA, indicates that the current address is valid.
In many 6800 systems an already decoded 4/5 line is
brought out to the common bus a!.Qin 21. This can be
tied directly to the ADC-830's CS pin if no other
devices are addressed at Hex ADDR: 4XXX or 5XXX.

A1312311NI

A1SI2511331

1"-----......
NOTE 1: NUMBERS IN PARENTHESES REFER TO Me6S00 CPU PIN OUT
NOTE 2: NUMBERS OR LETTERS IN BRACKETS REFER TO STANDARD M6800

l

VMA!51IFI

GNDI"

[~1'2;;1

SYSTEM COMMON BUS CODE

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

1-125

ADC-830
MICROPROCESSOR INTERFACING
MULTIPLE ADC-830's IN A MC6800 SYSTEM

When transferring analog data from several channels
to a single JLP system, a multiple converter scheme
presents several advantages over the conventional
multiplexer single converter approach. With the
ADC-830, the differential inputs allow individual span
adjust for each channel. Also, the channels are sensed
simultaneously, reducing the microprocessor's total
system servicing time.
In the system shown; the ADC-830's have been arbitrarily located at HEX address 5000 in the MC6800
memory space. To save components, the clock signal
is derived from just one RC pair on the first converter.
The system can easily be extended to allow the interfacing of more converters.

ABBO_----i
ADB'Z_----i
A5B3_----i

MULTIPLE ADC-830'S IN A Z-80 INTERRUPT DRIVE MODE

..-----+_

A2111)[OI
Al [1011\11
A019i[401

IIII
IIII
IIII
IIII
IIII
IIII

••

DM

• • 74LS138
G2A 4

In data acquisition systems where more than one peripheral device will be interrupting program execution
of a microprocessor, the CPU must determine which
device requires servicing. The circuit shown allows the
ADC-830's to be started in any sequence, but will input
and store valid data with a priority sequence of AID #1
through AID #7. Only the converters whose INT is
asserted will be read.

ORDERING INFORMATION

AHIl3JIN;

MODEL

OPERATING
TEMP. RANGE

ADC-830C

O°C to + 70°C

ACCESSORIES
Part Number

Description

TP100, TP10K

Trimming Potentiometers

A14(241IMI

1·126

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC·847
Microprocessor·Compatible
8·Bit AID Converter

FEATURES
• Microprocessor compatible
• 9 Microseconds conversion time
• a-Bit resolution
• ± V. LSB linearity error
• Ratiometric operation

GENERAL DESCRIPTION
DATEL ADC-847 is a low cost, mono~thic,
8-bit AID converter designed to interface
directly with a microprocessor via threestate outputs. The device appears as a
memory location or 1/0 port to the microprocessor and thus requires a minimum of
interfacing logic. Using the successive approximation technique, the ADC-847 completes an 8-bit conversion in 9 microseconds with a maximum linearity error as low
as
LSB.

tv.

The data outputs of the ADC-847 are provided with three-state buffers to allow connection to a common data bus. The digital
control lines; WR, RD and BUSY are active low and are available in most microprocessor memory systems. The BUSY
output uses a passive pull-up for
CMOSmL compatibility which also allows
up to four BUSY outputs to be connected
together to form a common interrupt line.
The ADC-847 will operate as a normal
AID converter for non-microprocessor
applications.
Other important features include single
supply operation capability, ratiometric
operation, internal reference circuit and internal clock generator. The clock generator requires only an external capacitor or
the device may be driven with an external
clock. The reference circuit only requires
an external resistor and capacitor or an
external reference voltage can be connected to the reference input (Pin 7) if required. The ADC-847 is an ideal choice for
many process control and instrumentation
applications.

MSB

MECHANICAL DIMENSIONS
INCHES (MM)

I

0925
(23.51

I

g~l~~: ::::: :lJg;l,
PIN 1

18 PIN PLASTIC DIP

The ADC-847 is available for operation
over the commercial, O°C to + 70°C and
military, - 55°C to + 125°C temperature
ranges and is packaged in either an 18 pin
plastic or ceramic DIP.

18 PIN CERAMIC DIP

lSB

INPUT/OUTPUT CONNECTIONS
PIN
1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

FUNCTION
BUSY tSTATUSl
RD (OUTPUT ENABLE)
CLOCK
WR (START CONVERSION~
EXTERNAL RESISTOR
ANALOG INPUT
REFERENCE INPUT
REFERENCE OUTPUT
GROUNO
+ V SUPPLY
DB7(MSBl
DB6
DB5
DB4
DB3
DB2
DB1
DBO (LSB)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1·127

ADC-847
ABSOLUTE MAXIMUM RATINGS, ALL MODELS

ADC-847A

Supply Voltage .•...•........•.••..••......•
Digital Input Voltage ......•..•..•••...•....•
Analog Input Voltage ...•••..•...•..........•

ADC-847B

ADC-847M

+7.0V
Vs
Vs

FUNCTIONAL SPECIFICATIONS, ALL MODELS
Typical at +25 DC, +5V dc supply voltage, 900 kHz clock frequency, unless otherwise
noted.
ANALOG INPUTS

ADC-847A

Analog Input Ranges ............•...•....•.•
Input Resistance •••....•••..•...•..•.••••..
Reference Input Range ..........•...••...•.•
Input Current' .............................

ADC-847B

ADC-847M

Oto +5V,Oto +10V, ±5V, ±10V
100 kO
+IV to +3V
1~

PHYSICAL/ENVIRONMENTAL
Operating Temp.
Range
ooe to + lOoe
ADC-847A ...
ooe to + lODe
ADC-847B
ADC-847M •..
- 55°C to + 125°C
Storage Temp.
Range .......
-55°C to + 125°C
Package Type,
lS-Pin DiP ••.. Plastic Plastic Ceramic
FOOTNOTES:

1. Input voltage ~ + 3V and Rex! ~ 82 k{l.
2. Input voltage ~ 2.4V, supply voltage ~ 5.5V.
For RD input. lin (" 1") ~ - 150 ,.A.
3. Input voltage ~ + O.4V, supply voltage ~ 5.5V.
For RD input, lin ("0") ~ - 300 ,.A .
4. Rre! ~ 390{l, Gre! ~ 4.7 pF.

DIGITAL INPUTS
Input Logic Level, Vin (" 1 "), minimum .........
Input Logic Level, Vin ("0"), maximum ..•.....•
Input Logic Level, lin ("1 ")2 ..................
Input Logic Level, lin ("0")3 ..................
Clock Input Voltage (pin 3)
high level, minimum .•••..••...............
low level, maximum .......................
Clock Input Current, high level, maximum ......
low level, maximum ...••..
Clock Pulse Width, minimum
.....
WR(Write) ................................

2V
O.BV

TECHNICAL NOTES

300~
±10~

4.0V
O.BV
BOO~
-500~

............

500 nsec .
Start conversion pulse. 200 nsec.
minimum pulse width. Active low input.
RD(Read) ..••....•....•.....••..•....•.... Active low state enables 3·state outputs.
-1.5V
Input Clamp Diode Voltage, maximum ..........

DIGITAL OUTPUTS

........................ B parallel lines of three-state, gateable
output data.
Output Coding, Unipolar .••.....•........•...
Binary
Bipolar ....................•.
Offset Binary
BUSY .................................... Active low output. High when conversion
complete. Low when conversion in
progress.
Output Logic Level, Vout("l"), minimum ..•...
2.4V
Vout ("0"), maximum ......
O.4V
Output Logic Level, lout("l"), maximum ......
100~
lout ("0"), maximum ......
1.6mA
Off-state output leakage current, maximum .....
2~
Parallel Output Data

PERFORMANCE
Resolution ................................
Linearity Error, maximum ..•..•...•....•.....
Differential Linearity Error, maximum .........•
Conversion Time ...........................
Internal Clock Frequency, maximum ..•..•.....
External Clock Frequency, maximum ..........
Reference Output Voltage, maximum' ..•..•....
Reference Slope Resistance, maximum
Reference Voltage Tempco .•...•...••........
Reference Current, maximum ................
minimum •................
Linearity Tempco .....•.............•.......
ZeroTempco ........••...................•
Full-Scale Tempco ..........................

± 1 LSB
±1 LSB

2.600V

B binary bits
± V. LSB
± 'h LSB
9!,sec.
1 MHz
1 MHz
2.5l0V

± V. LSB
± '12 LSB

20
50 ppm/oe
15 mA
4mA
±3.0 ppm/oe
±B.O ppm/oe
±2.5 ppm/oe

POWER REQUIREMENTS
Supply Voltage Range ......•..............•.
Supply Current, maximum .................•.
Power Consumption ....................... ,

1-128

+4.5V dc to +5.5V dc
40 mA
125 mW

2.5l0V

1. The internal clock generator requires
an external capacitor (1 00 pf for 1 MHz)
connected between Pin 3 and ground.
The oscillator frequency may be
trimmed with an external trim resistor (2
K!l maximum) connected in series with
the capaCitor. For optimum accuracy
and stability of the oscillator frequency
without trimming, the use of a crystal or
ceramic resonator connected between
Pins 3 and 9 is recommended.
An external clock signal from a TTL or
CMOS gate to Pin 3 may be used if the
application requires.
2. A 390!l reference resistor (Rref) should
be connected between Pins 8 and 10.
This will supply a nominal reference
current of 6.4 mA. Also, a 4.7 pF
stabilizingldecoupling capaCitor (Cref)
should be connected between Pins 8
and 9. For internal reference operation,
Vref OUT (Pin 8) is connected to Vref
IN (Pin 7).
3. An external reference may be used if
required. Voltage should be in the
range of + 1.5 to + 3.0 volts and may
be connected to Vref IN. The slope of
such a reference source should be less
than 2.5 !lIn, where n is the number of
converters supplied.
4. A continuous conversion can be accomplished by inverting the BUSY and
feeding it to the convert (WR) input.
To ensure reliable operation, an initial
start pulse is required. This can be accomplished by using a NOR gate instead of an inverter and feeding it with a
positive going pulse. The pulse can be
derived from a simple R.C. network that
gives a single pulse when power is
applied.
5. For ratiometric operation, if the output
from a transducer varies with its supply,
then an external reference for the AID
should be derived from the same supply. The external reference can vary

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-847
from + 1.5V to + 3.0V. Operation with a reference voltage
less than + 1.5V is possible but reduced overdrive to the
comparator will increase its delay and the conversion time
will need to be increased.
6. The WR (start conversion pulse) can be completely
asynchronous with respect to the clock, and will produce
valid data between 7% and 8% clock pulses later depending
on the timing of the clock and CONVERT signals.
7. Upon receiving a convert pulse, the AID is reset. (The
MSB is set to "1" all other bits are set to "0" and the BUSY
output goes lOw.) The AID will remain in this state until the
convert pulse returns high. After the start conversion input
goes high, the MSB decision will be made on the falling clock
edge after a rising clock edge (See timing diagram). This will
insure that the MSB is allowed to settle for at least half a
clock period or 550 nanoseconds at maximum clock
frequency.
The START CONVERSION (WR) input is not locked out
during a conversion. Therefore, if pulsed low at any time, the
conversion will restart.
8. The ADC-847 can be operated with a single supply. However, a negative supply voltage is required to supply the tail
current of the comparator. Since this current is only 25 to 150
pA and does not have to be well stabilized, it can be supplied
by a simple diode pump circuit driven from the BUSY output.
(See single supply operation.)

ZERO
ADJUST

TP,
GAIN
ADJUST

GND

=
CONNECTION FOR UNIPOLAR OPERATION

OFFSET

ADJUST TP,

AOC-647

t--~---{6

VIN

CALIBRATION PROCEDURE
For calibration procedure, unipolar and bipolar, apply continuous
convert pulses to start conversion (WR) input long enough to
allow a complete conversion and monitor the digital outputs.

CALIBRATION

•

ADC-847

GND

GAIN
ADJUST

CONNECTIONS FOR BIPOLAR OPERATION

UNIPOLAR
Zero Adjust Apply 0.5 LSB to the analog input and adjust the
ZERO ADJUST pot until the LSB (Bit 8) just flickers between 0
and 1 with all other bits at O.
Gain Adjust Apply FS - 1.5 LSB to the analog input and adjust the GAIN ADJUST pot until the LSB (Bit 8) output just
flickers between 0 and 1 with all other bits at 1.
COMPONENT VALUES
INPUT RANGE I TP, I TP2 I R,
I R2
+5V
I 5k 11M I 5.6k I 8.2k
+10V
I 10k 11M I 11 k I 5.6k

I

I
I

R3
680k
680k

CODING TABLES
UNIPOLAR
DIGITAL
OUTPUT
11111111
11000000
10000000
01000000
00000000

ANALOG INPUT
FS-l LSB
0.75 FS
0.5 FS
0.25 FS
0
1 LSB

BIPOLAR

=

FS
256

Offset Adjust Apply - (FS - 0.5 LSB) to the analog input and
adjust the OFFSET ADJUST pot until the LSB (Bit 8) output just
flickers between 0 and 1 with all other bits at O.
Gain Adjust Apply + (FS - 1.5 LSB) to the analog input and
adjust the GAIN ADJUST pot until the LSB (Bit 8) just flickers
between 0 and 1 with all other bits at 1.
After gain adjust, repeat offset adjust procedure.
COMPONENT VALUES
INPUT RANGE I TP, I TP2 I R,
+5V
I 5k I 5k I 13k
+10V
I 10k I 5k I 27k

I
I
I

R2
13k
8.2k

I
I
I

R3
7.5k
8.2k

BIPOLAR
DIGITAL
OUTPUT
11111111
11000000
10000000
01000000

ANALOG INPUT
+ (FS-1 LSB)
+ 0.5 FS
0
-0.5 FS
1 LSB = 2 FS
256

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-129

ADC-847
TIMING AND CONNECTION
TYPICAL CONNECTION

TIMING DIAGRAM
,

500

,

:-"nsec;~
ClOCK

~Y~
::
200 nsec.
~ :--- MIN

: :
1 I

~.-------jll

-.j

:.-

+5V

;:

250 nsec.

r--

-..: :.... 380 nsec.

----'-'-\i

II

I

39011

~f--fB_OE_e_'SIO_N_ _ _ _ _ _ _ _ __

Msa

lSB DECISION

EOC AD

CK

-5V VIN

VIN = VREF

SINGLE SUPPLY OPERATION
+5V

Vs

OUTPUT ENABLE/DISABLE DELAYS
_____

~I

BUSY

~~~-----~~50%
!..-260

LOGIC
"1"
OUTPUT

i

/

90%

!
,

:_100

I

,

~

nsec.+-!

I

10%

14Q

R,

4.7kn

IN914

r,.

--'"l
,

I'"'

e,'

ADC CLOCK

:--.1()() .-:10%
I nsec.

~,

1N914

C2),}------.
r:k~QlJENCY

DIODE PUMP CIRCUIT TO SUPPLY COMPARATOR
TAIL CURRENT. SeE TECHNICAL NOTE 8.

TYPICAL CONNECTION TO MICROPROCESSOR DATABASE

DATA BUS

WR
elK

mr

AQC.847

L------=ZE'"'R-O-'< I MEG

IOUT(max)

ADJUST

I MEG. >--Ot--~Z""E"'RO~--{
ADJUST

* Rs is chosen so that the parallel combination of R., R5 and R6 is approximately
625[l. This determines the D/A time constant and conversion time.

lOOK
lOOK

*The nearest preferred value may be used
for these resistors.

EXTERNAL REFERENCE

INTERNAL REFERENCE

FOR UNIPOLAR OPERATION WHERE R4 APPROACHES
co AND A ZERO ADJUSTMENT IS REQUIRED,
THIS CIRCUIT MAY BE USED TO REPLACE R4.

* *F.S.R. is the Full Scale Range, the difference between maximum input voltage
and minimum input voltage.

RESISTOR TABLES
ANALOG INPUT
RANGE

o to +2.5V
o to +5.0V
±2.5V
010 +10V
±5V
±10V

NOTES:

1-134

VREF2

R,'

R2'

R3

R4

Rs

R6'

2.5V
2.5V
2.5V
2.5V
2.5V
2.SV

2.5K
2.5K
2.5K
2.5K
2.5K
2.5K

62511
62S!!
62511
62511
62S!!
62S11

2.5K
2.SK
2.SK
2.5K
2.5K
2.5K

00

625!!
1.2SK
I.2SK
2.5K
2.5K
SK

00

00

I.2SK
00

1.25K
1.2SK

,. The nearest preferred value may be used for R" R2 and R6.
2. For external reference set R, = VREF (Kohms)

1.25K

""
835!!
2.5K
1.67K

ORDERING INFORMATION

MODEL
ADC-856C
ADC-856M

OPER.TEMP.RANGE
DoC to +70 oC
-55°C to + 125°C

THESE CONVERTERS ARE COVERED BY
GSA CONTRACT

DATEL, Inc, 11 CabotBoulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-868
Ultra High Speed, 12-Bit
Modular AID Converter

FEATURES
• 12-Bit resolution
• 500 Nanoseconds (maximum)
conversion time
• 3-State output
• ± 'h LSB linearity
• On board offset & gain adjustments
• No missing codes guaranteed

GENERAL DESCRIPTION
DATEL's ADC-868 is an ultra high speed,
12-bit, modular AID converter. Providing a
maximum conversion time of 500 nanoseconds, this converter guarantees no
missing codes over the ODC to + 70 DC
temperature range.
Standard input ranges are OV to + SV for
unipolar operation and ± 2.SV for bipolar
operation. Extended input ranges of OV to
+ 10V and ± SV can be implemented by
the addition of 2 external resistors. A low
input impedance of 1K allows for maximum speed applications with low impedance sources such as a sample and
hold amplifier.

MECHANICAL DIMENSIONS

Output data is available through a 3-state
output register, as 12 parallel lines with 2
enable inputs providing accurate data
transferal. Data is coded as straight binary
for unipolar operation and offset binary for
bipolar operation.
The ADC-868 is comprised of a fast settling precision input buffer, flash converter,
high-speed DAC, high-speed comparator,
precision voltage reference, clock generator and control logic circuits. Complete
with on-board offset and gain adjustments,
no external components are required.
Excellent specifications include a maximum gain tempco of 30 ppm/DC, and
± 'h LSB maximum differential nonlinearity.
The combined use of a high-speed AID
with "state-of-the-art" flash conversion
techniques, makes the ADC-868 an ideal
selection for high speed data acquisition,
real time waveform analysis, radar signal
processing and analytic instrumentation.
This module is packaged in a 4 x 6 x 0.37S
inch black enameled CR steel case with a
34 pin male connector located at one end.
requirements are ± 1SV dc and
± SV dc with a total current drain of 1070
nA, maximum.
~ower

~---------oo--~

CB

T

o.

I ~l

(BOTTOM VIEW)

,>0I

~l

8)

ADC-868

I

~

-11

~ 50

I

OFFSET ADJ.
I POT.

/

I
I

,-- - -'___ ___ .J
,--- --"

~

~

-

'"

®

J_

I

"

1843

---'

8)- ...L.i

'''GAIN

AOJ. POT.

-j H,,,!

0.156 diameter access holes for
ADJUSTMENT POTENTIOMETERS

~~tOl
'"

INPUT/OUTPUT
CONNECTIONS
PIN
1

11

FUNCTION
BIT 5

PIN

ANALOG
GROUND

20

+ 15V de

12

BIT 6

21

13

:~~B}!

DIGITAL
GROUND

22

rnAetE

23

FUNCTION

2

ANALOG
GROUND

3

5V de

4

-5Vetc

5

BIT 10

•

BIT 9

7

BIT 12 (lSB)

8

BIT 11

9

BIT 7

10

BIT 8

PIN

14

,.
,.
15

BITS 5-12

BIT 3

tSV de
DIGITAL

PIN

FUNCTION

27

START
CONVERT

28

ANALOG IN

2.

E.G,C. (STATUS)

30

ANALOG

GROUND

GROUND

+5V de

2,

BtPOLAA

31

OFFSET OUT

32

DIGITAL
GROUND

33

DIGITAL
GROUND

BIPOLAR

34

DIGITAL
GROUND

BIT 4

17

BIT 1 (MSB)

25

18

BIT 2
DIGITAL

2.

GROUND

FUNCTION

OFFSET IN

+SV de

DATEL. Inc. 11 Cabot Boulevard. Mansfield. MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-135

ADC-868
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS
+ 16V de
-16V de
±7V de
+5.5V
±6.25V

Positive Supply ................... .
Negative Supply .................. .
Logic Supply ..................... .
Logic Inputs ...................... .
Analog Inputs .................... .

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ! 15V and! 5V supplies, unless otherwise noted.
DESCRIPTION

TYPICAL

MINIMUM

MAXIMUM

ANALOG INPUTS (See Technical Note #2 lor extended input ranges.)
Unipolar ........................ ..
Bipolar ........................... .
Impedance, Unipolar ............... .
(with Pin 26 grounded)

OV to +5V
~2.5V

1KIl

1.01 KIl

DIGITAL INPUTS

Start Conversion . .

A 2V (minimum to 5V (maximum) positive pulse
with a SO nsec. (minimum) duration. Positive going
edge initiates conversion
2 TTL Loads
Logic low "0" enables bits 1 (MSB) thru 4
Logic low "0" enables bits 5 thru 12 (LSB)
1 TTL Load

~:::::::::::::::::::::::::::

Enable 5-12 ...................... .
Loading .......................... .

OUTPUTS
Urlipolar Coding .................. .
Bipolar Coding .................... .
Output Data .................... .
End of Conversion ................ .

Loading .......................... .

OutP~, ~,ogic Levels (enable lines low)

r------,------,-------j

V OUI 0 ......................... .

Vout "1" ......................... .
Loading..

Straight Binary
Offset Binary
12 Paraliellines
2V (minimum) to SV (maximum) positive going
pulse, 500 nsec. (maximum) width. Negative going
edge indicates conversion complete.
10 TTL Loads
+ 2.4V

. .............. .

+ O.2SV
+ 3.1V

+OAV

7 TTL Loads

1. Configuration for unipolar or bipolar
operation is as follows:
Unipolar operation-ground pin 26
leaving pin 24 open.
Bipolar operation-strap pin 24 to pin
26.
2. Analog input ranges may be extended
to OV to + 10V unipolar and ± SV bipolar by the addition of two precision resistors. See Extended Input
Configuration.
3. The high operating speed of these
converters requires that good high frequency board layout techniques be
used.
Analog input leads should be as short
and direct as possible. The use of
shielded cable as an analog input lead
will ensure isolation of analog signals
from environmental interference and
digital crosstalk.
4. Applications of these converters that
require the use of a sample-hold may
be satisfied by DATEL's model
SHM-4860, a high-speed hybrid unit
featuring 200 nanoseconds acquisition
time to 0.01% accuracy. See SampleHold Diagram.
5. These converters have a maximum
power dissipation of 8.6W. The case-toambient thermal resistance for this
package is approximately 40°C maximum.

PERFORMANCE
Resolution ....................... .

Conversion Time . ................. .
Differential Linearity Error . ......... .

450 nsee.
± '/, LSB
± '/, LSB
OOG to + 70 0 e
±20 ppm/oe
± 15 ppm/oe
± 10 ppm/oe

Integral Linearity Error ........... .
No Missing Codes ............... .
Gain Tempco ................... .
I

Zero Drift ......... " ............ .
Offset Tempco ................. .
Long Term Stability ............. .
Output Enable Delay ............. .

12 bits
500 nsec.
± '/, LSB
± 1 LSB

30 ppm/oe
20 ppm/oe
20 ppm/oe
0.2S%/year

6. For TTL operation, tie both enable inputs to digital ground.
7. Logic and analog supply lines are internally bypassed so that external bypass
capacitors are not necessary.

28 nsee.

20 nsee.

POWER SUPPLY SENSITIVITY, %1% Supply

± 15V de .......................... .
±5V de ....................... .

±0.03
±0.01

POWER REQUIREMENTS
Supply Voltage: Analog ............. .
Logic ............. ..
Supply Current: ± 15V ............... .
- 15V ............. ..
+ 5V ................ .
- 5V ............... .

Power Dissipation . ................ .

± 14.5V de

± 15V de

± 4.75V de

± 5Vde
lS0mA
100 mA
450 mA
225 mA
7.1 watts

± 15.5V de
± 5.25V de
200 mA
120mA
500mA
2S0 mA
8.6 watts

PHYSICAL/ENVIRONMENTAL
Operating Temperature ............ .
Storage Temperature .............. .
M.T.B.F.. .
. ............... ..
Package Type ..................... .

1-136

ooe ~o + 70 e
0

-25°e to + 85°e
125,000 hrs.
4 x 6 x 0.375 inch black enameled 25 gauge eR
steel, with a 34 pin male connector at one end.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

ADC-868
EXTENDED INPUT CONFIGURATION
Unipolar
An extended unipolar input range of 0 to 10V can be achieved
by the termination of the bipolar OFFSET IN (pin 26) to ground
through a 1.02 k{), .1 % resistor and connecting a 1.10 k{), .1 %
resistor in series with the ANALOG IN (pin 28).

BIPOLAR
OFFSET OUT

0 - - - { 24

BIPOLAR
OFFSET IN

Bipolar Operation
For extended input range operation,. see Extended
Input Configuration.
1. Apply START CONVERT PULSES to Pin 27. (Pin 26 connected to Pin 24.)
2. Connect a precision voltage reference of - full-scale + '/2
LSB (- 2.4994V or - 4.9988V for extended input range
operation) to the analog input. Adjust the offset potentiometer so that the LSB is flickering at 0000 0000 OOOX.
3. Connect a precision voltage reference of + F.S. - 1V. LSB
( + 2.4982V or + 4.9963V for exlended input range operation) to the analog input. Adjust the gain potentiometer so
that the LSB is flickering at 1111 1111 111 X.

ADC 86
- 8
OUTPUT CODING

ANALOG IN

Extended Input, Unipolar Configuration

Bipolar
An extended bipolar input range of ± SV can be attained by
strapping the bipolar OFFSET OUT (pin 24) to the bipolar OFFSET in (pin 26) through a 1.02 k{), .1 % resistor and connecting a
1.1 0 k{), 1% resistor in series with the ANALOG IN (pin 28).

BIPOLAR

A)----(24 OFFSET OUT

•

BIPOLAR
OFFSET IN

ADC 868
-

SEE)
( TEXT

t

rJ'v'V\A-128

UNIPOLAR
SCALE
+F.S. - 1 LSB
+~ F.S.
+%F.S.
+'12 F.S.
+ V. F.S.
+1 LSB
0

10V
RANGE
+9.9976V
+8.7S00V
+ 7.S000V
+S.OOOOV
+2.S000V
+0.0024V
O.OOOOV

5V
RANGE
+4.9988V
+4.37S0V
+3.7S00V
+2.S000V
+ 1.2S00V
+0.0012V
O.OOOOV

STRAIGHT
BINARY
111111111111
111000000000
11 00 0000 0000
1000 0000 0000
010000000000
000000000001
0000 0000 0000

BIPOLAR
SCALE
+F.S. - 1 LSB
+%F.S.
+'/: F.S.
0
- '12 F.S.
-%F.S.
-F.S. + 1 LSB
-F.S.

±5V
RANGE
+4.9976V
+3.7S00V
+2.S000V
O.OOOOV
-2.S000V
-3.7S00V
-4.9976V
-S.OOOOV

±2.5V
RANGE
+2.4988V
+ 1.87S0V
+ 1.2S00V
O.OOOOV
-1.2S00V
":'1.87S0V
-2.4988V
-2.S000V

OFFSET
BINARY
111111111111
111000000000
11 00 0000 0000
1000 0000 0000
010000000000
001000000000
0000 0000 0001
0000 0000 0000

ANALOG IN

Extended Input, Bipolar Configuration
6gNRJERT

-11=

~o-~~;~~~~

--- ----------------

_n_ n _ n n _________

"1'

GAIN AND OFFSET ADJUSTMENTS
Unipolar Operation
"or extended input range operation, see Extended
Input Configuration.
I. Apply start convert pulses to pin 27. (Pin 26 grounded)
~. Connect a precision voltage reference of + V. LSB (+ 0.61
mV or + 1.22 mV for extended input range operation) to the
analog input. Adjust the offset potentiometer so that the LSB
is flickering at 0000 0000 OOOX.
I. Connect a precision voltage reference of + full-scale - 1V.
LSB ( + 4.9982V or + 6.34V for extended range input operation) to the analog input. Adjust the gain potentiometer so
that the LSB is flickering at 1111 1111 l1IX.

.•

gIJT~0~ ______________~c= ~.

E.O.C.

__

:e-

lS~-6NSEC

ADC-868 TIMING DIAGRAM

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

1-137

ADC-868
ULTRA HIGH SPEED AID WITH SAMPLE/HOLD

+ 15V

-15V

+5V

-5V

•

ALLOW LESS
THAN 1"
BETWEEN
DEVICES

4 BIPOLAR
OFFSET OUT
BIPOLAR
OFFSET IN
ANALOG IN

ADC·868

r------~~n ~bA~JERT
E.O.C.
(STATUS)

START CONVERT
AND
HOLD COMMAND

When DATEL's ultra-high speed ADC-868 is used
in conjunction with a high speed sample-hold
amplifier, such as DATEL's SHM-4860, a throughput
rate of 1.25 MHz can be achieved.
'See Technical Notes for configuration.

ORDERING INFORMATION

1-138

MODEL

DESCRIPTION

ADC-868

500 nanoseconds, 12-bit
AID Converter

Mating Connector

34-Pin AMP #1-86063-3

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC·881
Ultra.Linear,8·Bit
AID Converter

FEATURES
• a-Bit resolution
• Statistically linearized conversion
• 14-Bit linearity
• ± 5V dc Input range
• 1.5 Microseconds conversion time
• Out-ot-range indication

GENERAL D.ESCRIPTION
The ADC-881 is an 8-bit analog-to-digital
converter with an internal sample-hold.
This converter employs a stochastic
distributional technique to enhance the
statistical (average) linearity by a factor of
11.2, thus achieving a linearity error of
only 0.005%. Systematic nonlinearities
are scattered in a pseudorandom fashion
over the range of the converter, thus appearing as noise rather than nonlinearities.
This result is particularly desirable in applications that use the digital output of an
AID converter to compile a histogram. The
fundamental properties of any nondistributive AID converter cause class
widths within the histogram to vary from
the ideal, thereby artificially increasing or
decreasing the frequency within discrete
class widths.
The ultra-linear AID has a wide range of
applications in spectrum analysis, nuclear
research, vibration analysis, geological
research, sonar digitizing, medical imaging systems, industrial testing and other
signal analysis applications.

INPUT/OUTPUT
CONNECTIONS
PIN

The ADC-881 has an analog input range of
± 5V dc and will accomplish an eight-bit
sample and conversion in 1.5 microseconds maximum. Output data is coded as
offset binary with an over range output to
indicate analog values out of the converter's range,
Additional specifications include a gain
tempco of 25 ppm/oC maximum, offset
tempco of 25 ppm 1°C maximum, zero
crossing tempco of 8 ppm/oC maximum
and long term stability of ± 0.02%lyear.
Each converter is a functionally complete
unit requiring only ± 15V dc and + 5V
power supplies for operation. The device is
packaged in a compact 5" x 3" x 0.375"
black enameled steel module. For information on extended temperature range
versions contact the factory.

1
2
3
4

MECHANICAL DIMENSIONS
INCHES

6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

(BOTTOM VIEW)

OFFSET ADJ

0.'

I

I

POT

:r:1.1
J.

-----,,-,-1-;-~r_ ~ 1

0.156 diameter access hOle'-,-,o-,

ADJUSTMENT POTENTIOMETERS

.'

BIT 4
START SELECT

r--;;- ~~~

AOC-BBl

-.i

FUNCTION
OVER RANGE

1-1 f--o,

1m ,

2'
26
27
28
29
30
31
32
33
34

BIT 2
EOC
BIT 1 (MSB)
EOC
BIT 8 (lSB)
Random, Enable

BIT7
NC

BIT6
NC

BIT5
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Digital Common
Digital Common

+5V dc
+5Vdc

+15Vdc
15V dc
Power Common
Power Common
15V dc
15V dc
Signal Common
Signal Common

Analog Input
Signal Common

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-139

ADC-881
FUNCTIONAL SPECIFICATIONS
Typical at +2S oC, ±lSV dc and +SV dc supplies, unless otherwise noted.
INPUTS
Analog Input Range. • • • . . • • . .• ± 5V
Analog Input Impedance ....... 14 k!l
Start Conversion .....•..•..•. A pulse' 20 nsec. to 80 nsec. duration with rise and fall
times less than 10 nsec. Logic "0" = OV to + 0.8V. Logic
"1" + 2.0 to + 5.5V. Conversion commences on the
leading edge of the pulse.
Loading: 1 LSlTL load.
Start Select .•.....•.•.••••.. For positive start input pulses, set Start Select to a Logic
"1". For negative start input pulses, set Start Select to a
Logic "0" or ground.
Randomizer Reset .•..•.•.••.. Hold at logical high for randomizing operations after reset 2 .
Loading: 4 LSlTL loads.
OUTPUTS
Parallel Output Data ........•. 8 parallel latched data lines -8 bits binary. V out
"0"" +OAV, V out "1";;,: +2AV.
Loading: 5 lTL loads
Coding ..............••.•... Offset Binary
EOC •••...••.•..•........•. Conversion Status Signal; High (V out "1" ;;,:2AV) from 32
nsec. typical after leading edge of Start Convert to 14
nsec. typical after all data outputs are valid. V out
"0"" + OAV.
Loading: 5 lTL loads.
EOC ..•...•..•.••...•••••.. Conversion Status Signal. Complement of EOC.
Loading: 5 TIL loads
Over Range3 ................ Ou1 of Range Signal. High (Vout ''1'' ;;,: + 2AV) for all
Signal Input values within ±5V, Low (V out "0" :s +OAV
for all Signal Input values beyond ± 5V.
PERFORMANCE
Conversion time', max. .......
Resolution ..................
Integral Linearity Error' .•..•...
Differential Linearity Error" .....
Noise(RMS)6 ................
Gain Error •...••..•.•.•..••..
Offset Error ...........•..••.
Gain Tempeo, max. . . . . • . . . . •.
OffsetTempco, max. ...•.••.•
Zero Crossing Tempco, max •...
. Long Term Stability .........•.

1.5 !~MH',

'0

""'o'P

ADC-974

Figure 4. Typical Connection Drawing

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-145

•

ADC-974
SHM-91

t
SHM-91

t
I

I
I
I

a:
w
X
w
...J

~

;/'

ADC-974

Il.

5

=>
:=;

§
«
z
«

I

SHM-91

I

START
CONVERT
CONTROL

EOC

Figure 5_ AID Application with Simultaneous
Sample-and-Hold
In the application depicted in Figure 5, the input circuitry
shown samples all analog inputs at the same time, holding the samples for conversion by the ADC-974.

SHM-91

ADC-974

INPUT
START CONVERT
CONTROL

Figure 6_ Ultra-Fast AID Conversion Application
Acquisition time of a sample-and-hold sometimes takes up
a sizeable part of the analog-la-digital conversion cycle.
As shown in Figure 6, interleaving two sample-and-hold
devices (using DATEL's SHM-91) lets one device acquire
the signal while the ADC-974 converts the other device's
output.

1-146

ORDERING INFORMATION
MODEL

DESCRIPTION

ADC-974

16-bit resolution (14-bit linearity) 2.5!,Sec. conversion time
AID Converter

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-B301E
SAMPLING AID BOARD
FEATURES
•
•
•
•

•

10 MHz Input bandwidth
High-speed sampling rate of 40 MHz
8-Bit resolution across entire bandw,~ith
TTL logic compatible

• Eurocard size, DIN connector
APPLICATIONS
• Video signal processing
• High speed voice signal analysis
• Radar system
• Transient analysis
• Atomic energy-related instrument control

DATEL's ADC-B301E is a stand-alone Eurocard-sized sampling AID board offering true 8-bit accuracy across the
entire dc to 10 MHz bandwidth. Also, the ADC-B301 E eliminates the need for custom test equipment when evaluating DA TEL 's ADC-301 Flash Converter.
GENERAL DESCRIPTION
The ADC-B301 E is a complele sampling AID conversion
board designed around DATEL's ADC-301 flash AID converter. The ADC-B301 E is functionally complete containing a
buffer amplifier, offset and gain adjustment circuitry, filtering
and timing circuitry.

DATEL's ADC-301 ftash AID converter.
DATEL's deSign takes into consideration crucial factors such
as board layout, impedance matching, input buffering, filtering
and timing.

DATEL designed the ADC-B301 E with two purposes in mind;
first, as a self-supporting, high-speed sampling analog-todigital converter board. Secondly, as a means to evaluate

ANALOG

~_ _- ,

1---0

BIT' (MS8)

1---0

BIT 8 ILSB)

L-----------o

EGe

0>-------

~-----------_

----OeOM

-15V

0>-------

_---O_S2V

+1SV
i+Vs)

(-Vs)

Figure 1. ADC-B301E Simplified Block Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-147

ADC·B301E
The ADC-8301 E performs AID conversions at sampling rates
up to 40 MHz. Using a four-layer printed circuit board and
high frequency noise filtering techniques assures perfect
conversions free from noise problems. Linearity error and differentiallinearity error are guaranteed to be less than one half
LS8.
The ADC-8301 E sampling board provides true 8-bit accuracy
across the entire 10 MHz input bandwidth. Video signal digitizing, radar signal processing, and transient signal analysis
are ideal applications for this wide-bandwidth, highly-accurate
front-end board.

ABSOLUTE MAXIMUM RATINGS
Power Supply Voltages
±Vs (Pins A30, A32) ..
Vee (Pins A18, B18) ...
Vcc (Pin A26) .......
Digital Input (A21) ...
..
Analog Inputs
(Pins A28, B28) . .
. .....

±17.5V
-8V to OV
+ 7V
+ 7V
±5V

TECHNICAL NOTES
As a design tool, the board relieves the design engineer of
the labor- and time-intensive task of constructing an evaluation circuit to test the applicability of the DATEL's ADC-301
flash converter in their design. The board allows fast hook-up
and prototype evaluation, shortening the design cycle. The
ADC-8301 E also makes an ideal test fixture for incoming inspection and component qualification.

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ±15V, -5.2V, +5V dc power unless otherwise
specified.
INPUTS
Analog Input Range
(See Technical Note 2)
Input Impedance
(See Technical Note 4)
Input Signal Bandwidth
Digital Input
Logic Level 0

1
Convert Pulse Width

o to +1V, ±0.5V
50 ohms
10 MHz
TTL-compatible
OV to +O.8V dc
+2V to +5.5V dc
10 nSec. minimum

OUTPUTS
(See Technical Note 7)
PERFORMANCE
Conversion Rate
Non-Linearity
Differential Non-Linearity
Missing Codes
Differential Gain Error
Differential Phase Error
POWER
+Vs/+ls
-Vs/-Is
Vee/lee
Vccllcc

30 MHz minimum,
40 MHz typical
±1/2 LS8 maximum
±1/2 LS8 maximum
None
1.5%
0.5 degrees

REQUIREMENTS
+14.5 to +15.5Vi+45 mA
-14.5 to -15.5V/-150 mA
-5.7 to -4.7V/480 mA
+4.5 to +5.5V/110 mA

PHYSICAL-ENVIRONMENTAL
Operating Temperature
Range
Storage Temperature
Range
Mechanical Dimensions

1-148

Oto +70 °C
-25 to +85 °C
100(W) x 160(D) x 19
(H) mm Eurocard Size

Refer to the Simplified 810ck Diagram (Figure 1) and the
Schematic Diagram (Figure 2) for further information.
1. The ± 15V dc analog power supply commons and the ±5V
dc digital power supply common are grounded to one point
at J1 on the board. DATEL does not recommend having this
common ground outside the board; noise problems may
result from ground loops. If it is, however, required to have
a common point outside the board, cutthe etch to J1. In this
case, avoid creating different potentials between digital and
analog grounds.
2. The analog input voltage signal range is adjusted at ±0.5V
dc at the time of the shipment from the factory. An offset
adjustment trimpot, labeled 'OFFSET' on the board, allows
shifting the input level to, for instance, a 0 to + 1V dc range.
Input voltage amplitude to the ADC-301 is always 1V peakto-peak.
3. Supply the analog input signal to the coaxial cable input
terminal (CN1). This input signal can be also supplied via
the DIN connector. In this case, connect the two sets of
feedthrough holes labeled 'SIG' in Figure 3 with a short
coaxial cable and then supply the Signal to the A28 (signal) and 828 (signal GND) terminals.
4. Resistor R1 is not installed, but is short-circuited with a jumper wire at the time of shipment from the factory; this sets
the input impedance at 50 ohms. Replace this jumper wire
with a 24 ohm resistor when 75 ohms of input impedance
is required.
5. A gain adjustment trimpot, labeled 'GAIN', is installed on
the board to adjust the -2V reference voltage required for
the AID converter. This trimpot is adjusted at the time of
shipment. If necessary, fine tune the gain while taking the
input fro rTl test point TP1 into a high-impedance digital
multimeter.
6. A trimpot, labeled 'LIN', is installed on the board to fine tune
the board's linearity. This trimmer is strictly fine tuned at
the time of shipment. When linearity is suspect, use this
trimpot to maintain one-half the reference voltage present
on TP1. Use a high-impedance multi meter to measure the
linearity voltage at pin 22 of the ADC-301.
7. Digital output coding is factory-set to positive true, offset
binary coding. There are L1NV and MINV etch pads on the
board. These are used to change the output code to 2's
complement, or negative true, logic. These pOints connect
to analog ground through 3.9K ohm resistors (R48, R49) at
the time of shipment to keep both pOints at logic "1" level.
To obtain a logic "0" level, cut the etch, leaving L1NV and
MINVopen. Refer to Table 1 for output coding information.
To re-establish logic "1" levels, solder jumper wires
between the feedthrough holes provided.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-8301E

Il,U4SSl

D.

0,
D.

0,
0,
0,

l1I?ti1
O"ILS6)

AGt;O~

Figure 2. ADC-B301E Schematic Diagram

.

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I~--------------144.5mm--------------_t~1
Figure 3. Component Layout Diagram

1-154

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-8302E
8. Output digital data is valid after three START CONVERT
pulses. Output data is then available on the falling edge of
the EOC pulse. Refer to Figure 4, the ADC-B302E timing
diagram.

ANALOG SIG

9. There are several test points (TP2, TP3, TP4) for checking
the performance of the board. While these points are available, the user should check the signals with highimpedance test probes only.
Performance of the board deteriorates if large external
loads are applied to these points. The following signals are
present on the indicated test points:

TEST POINT
TP2

SIGNAL
ANALOG INPUT signal
to the ADC-302
CLOCK
START CONVERT pulse

TP3
TP4

Eoe

10. Digital input and output signals are all differential EClcompatible except the START CONVERT pulse which is an
ECl-compatible, positive true input. This start convert
pulse is pulled up to ground with 220 ohms and pulled
down to the -5.2V power supply with a 300 ohm resistor
11

Output data lines and the EOC signal are differential. The
pull-up and pull-down resistors can be removed at the
board side, then installed at the signal receiver side in applications requiring long signal transfer distances.

12 An EOC signal output is available through a delay circuit
in order to optimize timing with any external circuits. Four
delay steps of 3 nanoseconds each are available. The delay
time is set at zero nanoseconds at the time of shipment
Figure 5 shows Jumper positions to set the EOC delay time

Figure 4. ADC-B302E Timing Diagram (not drawn to scale)

Table 1. Output Coding
INPUT/OUTPUT CODE
Input Voltage
0
3.9
7.7
15.6
35.25
62.5
125.0
250.0
500.0
750.0
996.1

V
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV

2

Step

Output Code

0
0
2
4
8
16
32
64
128
192
255

00000000
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
11000000
11111111

/

3

4

IlJlPlrl
a

3

6

9

COM
nSEC

FACTORY SET

Figure 5. EOC Selection Chart

BIPOLAR INPUT/OUTPUT CODE
Input Voltage
-0.500V
- 0.496V
- 0.492V
- 0.484V
- 0.469V
- 0.438V
-0.375V
-0.250V
O.OOOV
+0.250V
+ 0.496V

Step

Output Code

0
1
2
4
8
16
32
64
128
192
255

00000000
00000001
00000010
00000100
00001000
00010000
00100000
01000000
10000000
11000000
11111111

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-155

ADC-B302E
Table 2. Pin Connections
FUNCTION

CONNECTOR PINS
A B

NC
NC
NC
Bit 1 (MSB)
Bit 2
Bit 3
Bit4
Bit 5
Bit 6
Bit 7
Bit 8 (LSB)
NC
NC
NC
NC
NC
NC
-5.2V (Vee)
NC
NC
Start Convert Input
EOC
NC
NC
NC
NC
NC
Analog Input Signal
NC
+ 15V (+Vs)
NC
-15V (-Vs)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Dynamically Testing The ADC-302
FUNCTION

Digital Ground
Digital Ground
Digital Ground
Bit !J.I'I!SB)
Bit 2
Bit 3
Bit4
Bit 5
Bit 6
Bit 7
Bit 8 (LSB)
Digital Ground
Digital Ground
Digital Common
Digital Common
NC
NC
-5.2V (Vee)
NC
NC
Digital Gnd
EOC
Digital Gnd.
Digital Ground
NC
Analog Gnd
Analog Gnd
Analog Input Signal Gnd
Analog Common
Analog Common
Analog Common
Analog Common

Using basic lab equipment and popular software, the design
engineer can perform advanced, dynamic tests of the ADCB302E board, and the ADC-302, with relative ease.
The user may wish to dynamically test the ADC-302 using the
equipment configuration shown in Figure 6. A sine wave generator, with a low noise floor (below 8 bits), feeds an input signal
to the ADC-B302E board to provide a clean signal source. A
clock generator then provides a clock signal to the START
CONVERT input at the specified conversion rate.
Once power is applied, the ADC-B302E produces a digitized
version of the input signal. This output is then stored in RAM,
sampled over a period of time to ensure an adequate sample
base. Using widely-available Fast Fourier Transform programs, the data in RAM provides the basis for total system
response analysis. Parameters such as second harmonic distortion, total harmonic distortion, and signal-to-noise ratios can
be derived from this information.

ORDERING INFORMATION
ADC-B302E

SAMPLING AID BOARD

DATA
COLLECTION/STORAGE

r-----,

SINE WAVE
GENERATOR

ADC·B302E

I ADC-3021

I

I
I
I

I

I

I

:
I
I

I

I

' - - -.... OUTPUT

.- I

L ____

I
..J

Figure 6. Dynamically Testing the ADC-302

1-156

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388fFAX (508) 339-6356

ADC-8303E
a-BIT, 100 MHz
SAMPLING AID BOARD
FEATURES
a-Bit Resolution

40 MHz (-3d B) Input Bandwidth
100 MHz Sampling Rate
ECl logic Compatible
Eurocard Size, Din Connector
APPLICA TlONS
Video signal processing
High-speed voice signal analysis
Transient analysis
Atomic energy-related instrument control

DA TEL's ADC-B303E is an 8-bit, 100 MHz Sampling AID board, offering an input bandwith of dc to 40 MHz. Also, the
ADC-B303E eliminates the need for developing a test board when evaluating DA TEL's ADC-303 flash converter.

GENERAL DESCRIPTION
The ADC-B303E is a complete video AID converter board
designed around DATEl's ADC-303, 8-bit, 100MHz flash
converter. Contained on the board are local power supplies,
timing circuitry, input buffer amplifier, linearity adjustment circuitry, filtering, timing and an output buffer register.

versions up to 100MHz. The board serves as a selfsupporting high-speed analog-to-digital converter board.
The four-layer printed circuit board and high frequency
noise filtering construction techniques by DATEl, assure perfect conversions free from noise problems.

The ADC-B303E performs analog-to-digital conversions with
linearity and differential linearity errors less than 112 lSB for
input signal bandwidths up to 40MHz (-3dB).
The Eurocard board also contains offset and gain circuitry, is
ECl logic compatible and can perform ultra high-speed conANAlOG IN

BUFFER AMPLIFIER

START CONVERT IN

L -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

ANALOG COMMON 0 0------,.

Figure 1.

o~

--------0 -

'.2V

"'----0

DIGITAlCOMMON

ADC-B303E Simplified Block Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-157

ADC-B303E
ABSOLUTE MAXIMUM RATINGS

GENERAL DESCRIPTION (cont.)

Power Supply Voltages:
+15V Supply (Pin A30)
-15V Supply (Pin A32)
-5.2V Supply (Pin A18, B18)
Clock Pulse Input Voltage (Pin A2l)
Analog Input Volgate (ANA IN) (pin A28)

The board also offers the design engineer fast
hook-up for prototype evaluation. The labor-andtime intensive task of constructing an evaluation
circuit to test the applicability of the ADC-303 flash
converter is virtually elimintated. The ADC-B303E
also makes an ideal test fixture for incoming inspection and component qualification.

+18V
-18V
·8V
·8V
±5V

FUNCTIONAL SPECIFICATIONS

TECHNICAL NOTES

Typical at 25 degrees C, ±15V, -5.2V power unless otherwise stated.

Refer to the Simplified Block Diagram and the
Schematic Diagram for more information.

DESCRIPTION

MIN.

TYP.

-

Oto +1
±0.5

-

Volts
Volts

-

50
75

40

-

-

Ohms
Ohms
MHz

5

-

-

nS

8

-

-

Bits

MAX.

UNIT

ANALOG INPUTS
Input Ranges
Input Impedance
R1
0 n (standard)
R2
24 n (user-supplied)
Input Signal Bandwidth (-3 dB)

=
=

1. The ± 15Vdc analog power supply commons
and the - 5.2V dc digital power supply common are
grounded to one point on the board. The analog
and digital grounds should not be connected externally as the ground loop created may result in
unwanted noise. If a common ground is outside the
board, cut the etch to Jl. In this case, avoid creating potentials between digital and analog grounds
on the ADC-B303E Sampling AID board.

DIGITAL INPUT
Start Convert Pulse Width
OUTPUTS
Resolution
Digital Output Logic Levels:
Logic 1
Logic 0
Logic Loading 1
Logic Loading 0

-0.81
-1.65
-

0.5

-1.75

-

-0.96
-1.85
265

-

Volts
Volts
llA
llA

PERFORMANCE
Conversion Rate
Non-Linearity
Differential Non-Linearity
Differential Gain Error
Differential Phase Error

100
-

-

-

1.5
0.5

-

MHz
LSB
LSB

± 1/2
± 1/2
-

%

-

Oeg.

POWER SUPPLY REQUIREMENTS
Power Supply Range:
+15V Supply
-lSV Supply
-S.2V Supply
Power Supply Current:
+15V Supply
-15V Supply
-5.2V Supply

+14.5
-14.5
-4.7

+15.0
-15.0
-5.2

+15.5
-15.5
-5.7

Volts
Volts
Volts

-

+40
-350
-750

-

mA
mA
mA

+70
+85

"C
"C

-

PHYSICAL-ENVIRONMENTAL
0
-25

Mechanical Dimensions

3.94" (W) x 6.3" (0) x 0.67" (H)
100 (W) x 160 (0) x 17 (H) mm
0.31 Lbs. (165 Grams)

1-158

The START CONVERT pulse is pulled up to
ground with an 82 ohm resistor and pulled
down to the -5.2V dc power supply with an 130
ohm resistor. As a result, input impedance of
the START CONVERT pulse is 50 ohms.

4. The START CONVERT pulse width must be
a minimum of 5 nanoseconds. Care should be
taken to match the impedance of the START
CONVERT pulse signal to the characteristic impedance of the START CONVERT input on the
ADC-B303E board.
5. The pull-up and pull-down resistors of the
output data lines and EOC can be removed
from the board and installed on the receiver
side of the digital outputs for applications requiring a long signal transfer distance.

6. Approximately 15 minutes of warm-up time is
-

Operating Temperature Range
Storage Temperature Range

Weight

2. The digital input and output signals are differential ECl-compatible except the START
CONVERT pulse. It is supplied from the coaxial
cable connector lab led "CONV" on the board or
the terminals of the DIN connector, A21 (START
CONVERT) and B21 (START CONVERT signal
GND).

required for maximum accuracy and stable performance.
7. The surface temperature of some components on the board reach 70°C when the board
is operated at room temperature (25°C). It is recommended to operate the board with adequate
air circulation.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-8303E

~tf~==j:~~~lt!t!!!i~,~~
~

." 0"""

-; S'"2}()'S

~<

Figure 2.

NlALOOGAOLND

ADC-8303E Schematic Diagram
Table 1.

ADC-8303E Pin Connections

THEORY OF OPERATION

Refer to the timing diagram, schematic and board layout of the
AOC·B303E board as necessary. The AOC·B303E Sampling
NO board has built·in offset, gain and reference adjustment
trimpots plus an analog input signal amplifier which accepts
I Vp·p input signals. The board also contains regulated, on·
board power supplies which adds stability to the board's func·
tions. Supporting timing circuitry, and easy signal and power
connections make the board easy to use.
The analog input signal can be applied to either the analog
input connection (AIN) or to the pins on the DIN card edge
connector ANA IN. If the signal is to be applied to AIN, insert a piece of coax of the same characteristic impedance as
the input impedance of the ADC-B303E. Connect one end
of the coax to the feed-through holes labled "SIG" and the
other end to terminals A28 (ANA IN) and 828 (SIG GND).
Analog input impedance matching of 50 or 75 ohms is ob·
tained by placing a jumper wire in resistor RI's mounting
feedthrough holes for 50 ohms impedance, or a 24 ohm resistor if 75 ohms of input impedance is required. Other input
impedances are calculated by subtracting 50 ohms from the
desired input impedance, and placing the difference value in
the feed through holes to resistor RI.
After the analog input signal is offset adjusted on the board,
it is fed to the input terminals of the ADC-303 Flash ND.

FUNCTION

PIN

PIN

FUNCTION

NC
NC
NC
BIT 1 (MSB)
BIT2
BIT3
BIT 4
BIT5
BIT6
BIT7
BIT8(LSB)
NC
NC
NC
NC
NC
NC
-5.2V
NC
NC
START CONVERT
EOC
NC
NC
NC
NC
NC
ANA. IN
NC
+15V
NC
-15V

AI
A2
A3
A4
A5
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

Bl
B2
B3
B4
B5
B6
B7
B8
B9
Bl0
Bll
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

DIG. GND.
DIG. GND.
DIG.GND.
BIT 1 (MSB)
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT 8 (LSB)
DIG.GND.
DIB.GND.
DIG. COM.
DIG. COM.
NC
NC
-5.2V
NC
NC
DIG.GND.
EOC
DIG.GND.
DIG. GND.
NC
ANA.GND.
ANA.GND.
SIG.GND.
ANA. COM.
ANA. COM.
ANA. COM.
ANA. COM.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-159

ADC·B303E
N+l
N+2
N
ANAlOG IN

SfART CONVERT

Te

TWPI

TWPD

AD CLK

TP3

--+--1'1
Te

EO C

OUTPUT DATA

N -2

N-I

N

nSoc
I---T_c_w_m'_"-t-_T
_w
_p TW._P_D_""_"+-_T_D_I---_T_A_+-_T_E_C_I---_T_c_.---I

7.S=C=Z.S

Figure 3.

7.5

ADC-B303E Timing Diagram

The input of the ADC-303 has two series resistors that inhibit parasitic oscillations, thus imporving the overall performance of the board. Supporting gain and reference
circuitry adjusts the input range of the ADC-303.
The gain and offset adjustments are described in detail in
the calibration section of this data sheet. The output of
the ADC-B303E is ECl compatible, and its timing is described as follows:
The START CONVERT pulse is applied to pin A21 and
B21 or to the connector located on the board. Seven (7)
nanoseconds later, the ADC-303 and the "10176" Master-Slave D-type latch are clocked simultaneously. Data
that was at the output of the ADC-303 is now clocked into
the "10176" latch, and the data that was in the "10176"
master-slave latch goes to the slave and proceeds
through an output buffer.
The data from the two previous AID conversions is now at
the output of the I\DC-B303E board. It takes a total of
three AID clock pulses before the data is displayed at the
output of the ADC-B303E board. The AID clock Signal
from the delay circuitry gives a positive pulse 7.5 nanoseconds in duration and returns to a "low" state for the remainder of 2.5 nanoseconds for a total of ten (10) nanoseconds between the rising edge of each ClK pulse.
Consequently, the data at the output of the ADC-B303E

board changes every 10 nanoseconds. It is from this data
change time duration that the 100MHz Sampling rate is
derived.
An EOC signal is available to the user which indicates
when the data is valid after the rising edge of the AID clock
pulse to the ADC-303. There is another delay linejDl2)
which adds a delay of 0 to 3 nanoseconds to where the
EOC pulse will go high. Therefore, a minimum of four (4)
nanoseconds to a maximum of 7 nanoseconds after the
rising edge of the AID ClK pulse the EOC signal goes
high.
The EOC pulse train is shifted (delayed) a minimum of 4
nanoseconds from the AID ClK pulse train, and it takes a
total of three (3) AID ClK pulses before the first AID conversion that was taken can be read. There is an elapsed
time of 25 nanoseconds that exists between the rising
edge pulse of the "first" AID conversion when this "first"
data can be outputted from the ADC-B303E board.

DL2

~ FACTORY SET

41....-~--?--O-;dt-----,
I
3

2

1

0

COM

nSec

EOC SELECTION

1-160

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADe-B303E
6.6'
(167.6) - - - - - - - - - - - - - - - - " " "

6.3'
(160)

B-303E
SN_

5.68"
(144.5)

INCHES
(mm)

Figure 4.

ADC-B303E Component Layout Drawing

CALIBRATION
There are three trimpots on the board, labeled "Offset",
"Gain" and "LIN". Each function of these trimpots is described as follows:
1. OFFSET TRIMMER
The analog input signal voltage range is 1V peak-to-peak.
This trimpot permits the user to match the output of their application to the input of the ADC-B303E board. For example,
Input voltage ranges may be adjusted from a to + 1V, ± 0.5V,
-O.4V to +0.6V, etc. This trimpot permits the offset adjustment range from a to -2.000V dc.
Unipolar Operation (0 to +1V)
Adjust the Offset trimpot with +1.9531 mV (+ 1/2 LSB) applied to ANA IN so the straight binary output code flickers between 0000 0000 and 0000 0001.
Bipolar Operation (±0.5V)
Adjust the Offset trimpot with +0.4980 mV (-FS + 1/2 LSB)
applied to ANA IN so the offset binary output code flickers
between 0000 0000 and 0000 0001.

3. LINEARITY TRIMMER
This trimpot is used to fine tune the linearity of the board.
Connect a high-impedance digital multimeter to test point
TP1 and ANA GND and measure this voltage. Reconnect
the multimeter to pin 32 (VRM of the ADC-303 and ANA
GND and adjust the Linearity trimpot to one-half (1/2) of
the voltage indicated on test point TP1.
The following test pOints are provided on the board for calibration purposes. Care must be taken to minimize the
loading of these test pOints when performing calibration
and warranted adjustments.
TEST POINT DESCRIPTION
TP 1
TP2
TP3
TP4

Reference Voltage
Analog Input signal with offset compensation
AID Clock
Start Convert pulse

2. GAIN TRIMMER (0 to +1V, ±5V)
This trim pot is installed to adjust the -2V reference voltage
required for the ADC-303. Adjust the Gain adjust trimpot
with +FS - 1 1/2 LSB applied to ANA IN (+0.99414V for Unipolar or +0.49414V for Bipolar operation) so the straight binary or offset binary output code flickers between 1111
111 a and 1111 1111.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-161

ADC-8303E

Table 2. Output Coding for Unipolar and Bipolar Operation

UNIPOLAR OPERATION
UNIPOLAR
SCALE

INPUT
VOL T AGE

+ FS - 1 LSB
+ 7/8 FS
+ 3/4 FS
+ 1/2 FS
+ 1/4 FS
+ 1 LSB
0

+ .9961
+ 875
+ 750
+ 500
+ 250
+3.906
0

I MINV
I

LlNV

V
mV
mV
mV
mV
mV
V

BIPOLAR OPERATION
BIPOLAR
SCALE

INPUT
VOLTAGE

+
+
+
+
-

+
+
+
+
-

FS - 1 LSB
3/4 FS
1/2 FS
0
112 FS
3/4 FS
FS+ 1 LSB
FS

496.1
375
250
0
250
375
496.1
500

I MINV
I

mV
mV
mV
mV
mV
mV
mV
mV

LlNV

STRAIGHT
BINARY

COMPo
BINARY

1
1

0
0

11111111
11100000
11000000
10000000
01000000
00000001
00000000

00000000
00011111
00111111
01111111
10111111
11111110
11111111

OFFSET
BINARY

COMP. OFFSET
BINARY

2'5
COMPo

1
1

0
0

0

1

1

0

11111111
11100000
11000000
10000000
01000000
00100000
00000001
00000000

00000000
00011111
00111111
01111111
10111111
11011111
11111110
11111111

01111111
01100000
01000000
00000000
11000000
10100000
10000001
10000000

10000000
10011111
10111111
11111111
00111111
01011111
01111110
01111111

COMPo
2'5 COMPo

NOTES: MINV is the output control pin for data bit 1 (MSB).

LlNV controls output data bits 2 through 8.

ORDERING INFORMATION
ADC-B303E
100 MHz, 8-Bit

Sampling AID Board

1-162

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC·B304E
a-BIT, 20 MHz
SAMPLING AID BOARD
FEATURES
• 8-Bit resolution
• 20 MHz sampling rate
• 8 MHz Input bandwidth
• TTL logic compatible
• Eurocard size, DIN connector
APPLICATIONS
• Video signal processing
• High-speed voice signal analysis
• Radar systems
• Transient analysis
• Atomic energy-related instrument control

GENERAL DESCRIPTION
The ADC-B304E Sampling AID board is a complete AID
conversion board designed around DATEL.:s ADC-304 flash
converter. The ADC-B304E is TTL logic compatible and
offers built-in offset and gain adjustment circuitry. The board
contains a buffer amplifier as well as filtering and timing
circuitry.

such as board layout, impedance matching, input buffering
and filtering. Design engineers must consider these factors
when evaluating high-speed flash converters.
As a design tool, the board relieves the design engineer of
the labor- and time-intensive task of constructing an evaluation circuit to test the applicability of the ADC-304 flash
converter in their design. The board allows fast hook-up and
prototype evaluation, shortening the design cycle.

DATEL designed the ADC-B304E sampling AID board with
two purposes in mind; first, to serve as a self-supporting,
high-speed analog-to-digital converter board and secondly,
as a means of evaluating DATEL.:s ADC-304 flash converter.
DATEL.:s design takes into consideration crucial factors
ANA
IN

c!-~-ODGND

v

___ { ) BIT 1

IMS8)

4.7Q

--"~.-----o

OIT 3

-OBIT4

-----OBITS

--------;..

-----0

0116

---D

BIT 7

o

61TS

!LS81

-5VA,

~+15V

~'"'COM
~-15V
1~D1GCOM

Figure 1. ADC-304 Simplified Block Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-163

ADC·B304E
As a stand-alone analog-to-digital converter board, the wide 8 MHz input
bandwidth makes the AOC-B304E adaptable to many advanced design-in applications.

ABSOLUTE MAXIMUM RATINGS
Power Supply Voltages:
+ 15V Supply (Pin A30)
- 15V Supply (Pin A32)
+ 5V Supply (Pin A26)
Clock Pulse Input Voltage (Pin A21)
Analog Input Voltage (ANA IN) (Pin A28)

+18V
-18V
+7V
+7V
±6V

The ADC-B304E sampling AID board
provides true 8-bit accuracy across the
entire 8 MHz input bandwidth. Video signal digitization, radar signal processing,
and transient signal analysis are ideal
applications for this wide-bandwidth,
highly-accurate front-end board.

FUNCTIONAL SPECIFICATIONS
Typical at 25 degrees C, ± 15V, +5V power unless otherwise stated.
DESCRIPTION
ANALOG INPUTS

I

Input Ranges
Input Impedance
R1 =0 ohms (standard)
R1 =24 ohms (user-supplied)
Input Signal Bandwidth ( - 3dB)
DIGITAL INPUTS
Digital Input Logic Levels:,
Logic "1"
Logic "0"
Logic Loading "1"
Logie Loading "0"
OUTPUTS
Resolution
Digital Output Logic Levels:
Logic "1"
Logic "0"
Logie Loading "1"
~ic Loading "0"
EOC Output Logic Levels:
Logic "1"
Logic "0"
Logic Loading" 1"
Logic Loading "0"
PERFORMANCE
Conversion Rate
Non-Linearity
Differential Non-Linearity
Differential Gain Error
Differential Phase Error
POWER SUPPLY REQUIREMENTS
Power Supply Range:
+15V Supply
-15V Supply
+5V Supply
Power Supply Current:
+15V Supply
-15V Supply
+5V Supply
PHYSICAL-ENVIRONMENTAL
Operating Temperature Range
Storage Temperature Range
Mechanical Dimensions
Weight

1-164

MIN.

TYP.

-

o to

+ 2
0

MAX.

UNITS

-

Volts
Volts

-

Ohms
Ohms
MHz

-

-

+ 5.5
+ 0.8
20
24

Volts
Volts
iJA
mA

8

-

-

Bits

+ 2.4
0

-

+ 0.4
2.6
24

Volts
Volts
mA
mA

-

+ 5.5
+ 0.4
2.5

Volts
Voits
mA
mA

-

MHz
LSB
LSB

-

Degrees

+1
± 0.5
50
75
8

-

-

-

-

-

-

20

-

The ADC-B304E performs AID conversions at sampling rates up to 20 MHz.
Using a four-layer printed circuit board
and high frequency noise filtering assures
perfect conversions free from noise problems. Linearity error and differential
linearity error are guaranteed to be less
than one half LSB.

TECHNICAL NOTES

-

+ 2.4
0

The ADC-B304E sampling AID board also
makes an ideal test fixture for incoming
inspection and component qualification.

-

1.5
0.5

± 1/2
± 112
-

%

+ 14.5
-14.5
+ 4.5

+ 15.0
-15.0
+ 5.0

+ 15.5
-15.5
+ 5.5

Volts
Volts
Volts

-

-

+65
-140
+200

mA
mA
mA

0
-25

-

+70
+85

°C
°C

3.93"(W) x 6.3"(0) x 0.55"(H)
100(W) x 160(0) x 14(H) mm
0.308 Lbs. (140 Grams)

Refer to the ADC-B304E's Block Diagram
(Figure 1) and Schematic Drawing (Figure
2) for further information.
1. The on-board ± 15V dc analog power
grounds and the + 5V dc digital power
grounds are joined at a point labeled J 1
on the board. DATEL does not recommend having this common ground outside the board, otherwise noise
problems may result from ground loops.
If it is required to have a common point
outside the board, cut the etch between
the J1 pins. In every case, avoid creating different potentials between the
digital and analog grounds on the
board.
2. Supply the analog input signal to the
coaxial cable input terminal labeled
AIN. This input signal can be also supplied via the DIN connector. In this case,
connect two sets of feedthrough holes
labeled "SIG" in Figure 4 with a short
coaxial cable and then supply the signal to the A28 (ANA IN) and B28 (SIG
GND) terminals. The short coaxial cable
should have a characteristic impedance
matching the ADC-B304E's input
impedance.
Analog input impedance matching of 50
or 75 ohms is available. As shipped
from the factory, the ADC-B304E has an
input impedance of 50 ohms. A jumper
wire in resistor R1 's mounting feedthrough holes selects this value.
Replacing the jumper wire with a 24
ohm resistor provides an input impedance of 75 ohms. Refer to the Functional Specifications section for more
information.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

ADC·B304E
OUTPUT COOING
POLARITY
JUMPERS
~r~J

U~DIOGND

-b
"r"-~~~8IT 1 (MS8)

f ' - - - - - - - - - - - ' l8 70

•

7I1P"'---~"__~
6Q I4

1'-------------'1'm

f-------------'-I' '"

'w

F----"'-->

BIT B (LSB)

812,13
, - - - . ) DIG GND

-b
0'

'''0'

+

823,24 ( DIG GND

~5

",

) EOC

~"G
~SlGGNO

NOTE: RESISTORS WITH 'F' FO\..LOWING VALUE
ARE METAL FILM: ALL OTHERS CAASON

Figure 2. ADC-B304E Schematic Diagram
TECHNICAL NOTES (cont.)
3. Output digital data is obtained at the falling edge of
EOC. Refer to the timing diagram of the ADC-8304E.
4. Digital input and output signals are all TTL-compatible.
The START CONVERT pulse width should be a minimum
of 15 nanoseconds and Ts-15 nanoseconds maximum. Ts
is the sampling period. The START CONVERT pulse
should also be supplied through a buffer such as the
74LS240.

Table 1. ADC-B304E Pin Connections
FUNCTION

PIN

PIN

FUNCTION

DIG GND
DIG GND
DIG GND
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8 (LSB)
NC
NC
NC
NC
NC
NC
NC
NC
NC
START CONVERT
EOC
NC
NC
NC
+5V
NC
ANA IN
NC
+15V
NC
-15V

Al
A2
A3
A4
AS
A6
A7
A8
A9
Al0
All
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

Bl
B2
B3
B4
B5
B6
B7
B8
B9
Bl0
Bll
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

DIG GND
DIG GND
DIG GND
DIG GND
DIG GND
DIG GND
DIG GND
DIG GND
DIG GND
DIG GND
DIG GND
DIG GND
DIG GND
NC
NC
NC
NC
NC
DIG COM
DIG COM
DIG GND
NC
DIG GND
DIG GND
NC
ANA GND
ANA GND
SIG GND
ANA COM
ANA COM
ANA COM
ANA COM

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1·165

ADC·B304E
TS
t E - - - - - - 50

- - - - " " " ' ' - - - - TS - 15
MIN

1~,~

----- --,

f-----;-- - - - ----.

o

START

-----7;

MAX

CONVERT

------:;.,E 11
MIN

:

~----------------~

I

AID eLK (T P 4)

I

LATCH

CLK

tE--~-37----~

EOC (T P 5)

OUTPUT

;:I{

N-'

DATA

(BIT1"-BIT

JUMPER

81

N
DATA VALID

SelECTABLE

UNIT: NANOSECOND

Figure 3. ADC-8304E Timing Diagram

THEORY OF OPERATION
The ADC-8304E is a fully functional sampling AID board with
on-board offset, gain, and linearity adjustments_ The buffered
analog input provides for 0 to + 1V and ± 0_5V full scale input
ranges. The ADC-8304E also contains regulated on-board
power supplies to assure stable operation. Refer to the block
diagram and timing diagram as needed.
Figure 3 shows the timing relationships between the START
CONVERT pulse, clocks, EOC, and the output data.
The START CONVERT pulse must be at least 15 nanoseconds long and can be no longer than the sampling period
minus 15 nanoseconds. The rising edge of the START
CONVERT pulse generates an internal clock command to
the ADC-304. This AID clock typically goes high after a delay
of 13 nanoseconds. This signal causes the ADC-304's
comparators to latch the comparison between the internal
reference ladder taps and the input voltage.
NOTE
In the following discussion, the present conversion, and its associated data, is called the 'N
conversion' while the previous conversion is
called the 'N-1 conversion'.
During the time the clock to the ADC-304 is high, the N-1

1-166

conversion is latched at the output of the ADC-304. The output
latch of the ADC-8304E is enabled while this internal AID
clock pulse is high, allowing the N-1 conversion to become
present at the output of the ADC-8304E. The internal AID
clock is typically high for 37 nanoseconds.
When the internal AID clock pulse goes low, the N-1
conversion is now latched at the output of the ADC-8304E.
The N conversion now becomes available at the output of
the ADC-304. This N conversion becomes available at the
output of the ADC-8304E upon the next START CONVERT
(and consequently AID clock going high), and becomes
latched on the next AID clock low cycle. Upon the AID clock
pulse going low, the comparators of the ADC-304 go back
into the sampling mode in preparation for the next conversion.
Output data becomes valid typically 6 nanoseconds after the
AID clock goes low and stays valid for the duration of the
AID clock pulse. The EOC signal, when low, indicates that
the data at the output of the ADC-8304E is valid. EOC goes
low 20 nanoseconds after the AID clock goes low to assure
data stability. The 20 nanosecond delay (factory setting) can
be jumper-selectable to 16 nanoseconds if shorter set-up time
requirements of external gates allow.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-B304E
6.3"
(160)

rC37

INCHES~

0.14"

(MM)

4 -

2.8

R 2 --'VV'v-

04

R 1 --'VV'v-

:P~

t

Q

1

HA- 2539-5 ]
T P1

008

::

~
..

...

q
q

OFFSET

GAIN

iii
'"
• UI
!? ~ ! :
0

--CJ-

I
I

~

}.IPC-O.8

I

01

D

TP.

0

rUJ
[Jj .,
Q3

,+,

0

"

10-01

TP2

AGND

0

a

LIN

®)
J 1

lINV

~
MINV

DO I

~

74FOO

~

74LSOO

SDM-103

r=:=J

I

I

I

I

o II

~R-8
SN

I

74ASS74

ADC -304

0

SIG

•

+0

k/
TP3

TP5

0

0

I
I [J

D
D

~+ss-

Figure 4. ADC-B304E Component layout Drawing

CALIBRATION
There are three trimpots on the board labeled "Offset," "Gain"
and "LIN." The following information describes the functions
of each of these trimpots.
1. Offset Adjust
The analog signal voltage range is adjusted to ± O.SV dc
at the time of shipment from the factory. The input voltage
amplitude to the ADC-B304E is always 1V peak-to-peak.
The offset range can be adjusted between - 2.3V and
+ 2.3V. To measure this offset voltage, connect the two
leads of a high-impedance digital multi meter to test pOint
TP1 and ANA GND.
Unipolar Operation
Adjust the Offset trim pot with + 1.9S3 mV (+ 112 LSB)
applied to ANA IN (pin A28) so that the straight binary output code flickers between 0000 0000 and 0000 0001.
Bipolar Operation
Adjust the Offset trimpot with - 498.0S mV (- FS +
112 LSB) applied to AIN IN (pin A28) so that the offset
binary output code flickers between 0000 0000 and 0000
0001.
2. Gain Adjust
This trimmer adjusts the - 2V reference voltage required
for the ADC-304. Vary this trim pot with + FS
- 1-112 LSB applied to ANA IN (pin A28). This value
should be + 0.9941 V for unipolar operation or + 0.4941 V

for bipolar operation. Adjust the trimpot so that the straight
or offset binary output code flickers between 1111 1110
and 1111 1111.
3. Linearity Trimmer
This trimpot fine tunes the linearity of the board. Connect
a high-impedance digital multimeter to test point TP2 and
ANA GND (pins B26 or B27) and measure the reference
voltage. Reconnect the multi meter to Pin 27 (VRM) of the
ADC-304 and ANA GND (pins B26 or B27) and adjust the
"LIN" trimpot to one-half (1/2) of the reference voltage
measured on TP2.
To confirm the operation of the ADC-B304E, vary the input
voltage with a precise reference voltage source to obtain the
output coding listed in Table 2. Repeat the previous steps,
if necessary, to achieve the desired operation of the
ADC-B304E.
The following Test Points are available to the user of the ADCB304E. Refer to Figure 4 for the exact location of these test
points on the board.
TEST POINT
TP1
TP2
TP3
TP4
TPS

DESCRIPTION
Buffered, Offset, Analog Input Voltage
Reference Voltage
Start Convert Pulse
AID Clock Input
EOC

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-167

ADC·B304E

74 F 00

16 ; - - - - - - ,

G-

-o---z[
~
20

Dl-1

~

T P 5

o
FACTORY

SET

R24

Figure 5. EOC Selection

Figure 6. Output Inversion Control Pins

OUTPUT CODING
Digital output coding is factory-set to positive true offset binary
coding. There are LlNV and MINV etch pads on the board.
These are used to change the output code to 2's complement
or negative true logic. These pOints connect to + 5V through
a 1K ohm pull-up resistor on the board, making these points
a "logic 1."

To obtain a "logic 0" on either or both of these points, short
the selected point to ground with a jumper(s). Refer to Table
2 and Figure 6 for coding information and "LlNV/MINV
Selection." Figure 4 shows the locations of these jumpers anc
etch.

Table 2. Output Coding for Unipolar and Bipolar Operation

UNIPOLAR OPERATION
UNIPOLAR
SCALE

INPUT
[ MINV
VOLTAGE
LINV

+ FS - 1 LSB
7/8 FS
3/4 FS
1/2 FS
1/4 FS
+ 1/8 FS
+ 1 LSB
0

+ 996.1
+ 875
+ 750
+ 500
+ 250
+ 125
+3.906
0

+
+
+
+

mV
mV
mV
mV
mV
mV
mV
mV

BIPOLAR OPERATION

I MINV

BIPOLAR
SCALE

INPUT
VOLTAGE

+ FS - 1 LSB

+ 496.1 mV
+ 375 mV
+ 250 mV
mV
0
- 250 mV
- 375 mV
- 496.1 mV
- 500 mV

+ 3/4 FS
+ 1/2 FS
+
-

0
1/2 FS
3/4 FS
FS+ 1 LSB
FS

LINV

STRAIGHT
BINARY

COMPo
BINARY

2's
COMPo

COMPo
2's COMPo

1
1

0
0

0
1

1
0

11111111
11100000
11000000
10000000
01000000
00100000
00000001
00000000

00000000
00011111
00111111
01111111
10111111
11011111
11111110
11111111

01111111
00100000
01000000
00000000
11000000
10100000
10000001
10000000

10000000
11011111
10111111
11111111
00111111
01011111
01111110
01111111

OFFSET
BINARY

COMPo OFFSET
BINARY

2's
COMPo

COMPo
2's COMPo

1
1

0
0

0
1

1
0

11111111
11100000
11000000
10000000
01000000
00100000
00000001
00000000

00000000
00011111
00111111
01111111
10111111
11011111
11111110
11111111

01111111
01100000
01000000
00000000
11000000
10100000
10000001
10000000

10000000
10111111
10111111
11111111
00111111
01011111
01111110
01111111

NOTES: MINV is the output control pin for data bit 1 (MSB).
LlNV controls output data bits 2 through 8.

ADC-B304E

1-168

ORDERING INFORMATION
ADC-304 Sampling AID Board

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-B310E
10-BIT, 12 MHz
SAMPLING AID BOARD
FEATURES

•
•
•
•
•

10-Bit resolution
12 MHz sampling rate
10 MHz input bandwidth
TTL logic compatible
Eurocard size, DIN connector

APPLICATIONS

•
•
•
•
•

Video signal processing
High-speed voice signal analysis
Radar systems
Transient analysis
Atomic energy-related instrument control

DATEL's ADC·B310E is a 10·bit, 12 MHz sampling AID board, offering an Input bandwidth of de to 10 MHz. The ADC·B310E eliminates
the need for custom test equipment when evaluating DATEL's ADC·310 flash converter

GENERAL DESCRIPTION
The ADC·B310E is a complete sampling AID conversion board
designed around DATEL:s ADC-310 flash converter. The ADCB310E is functionally complete containing a sample-hold amplifier, offset and gain adjustments, filtering and timing circuitry.

The ADC-B310E performs AID conversions at sampling rates
up to 12 MHz. Using a four-layer printed circuit board and high
frequency noise filtering techniques permits perfect conversions, free of noise problems.

DATEL designed the ADC-B310E with two purposes in mind;
first, as a self-supporting, high-speed sampling analog-todigital converter board. Secondly, as a means of evaluating
DATEL:s ADC-310 flash converter. The ADC-B310E also makes
an ideal test fixture for incoming inspection and component
evaluation.

Video signal digitizing, radar signal processing, and transient
signal analysis are ideal applications for this wide-bandwidth,
highly-accurate front-end board.

DATEL:s design takes into consideration crucial factors such
as board layout, impedance matching, input buffering, filtering and timing.
ANALOG IN
SAMPLE/HOLD

BIT 1 (MSB)

BUFFER
AMPLIFIER

START
CONVERT IN

<'----~o

DIGITAL COMMON
+----~o

-6.2V
ANALOG COMMON

+-----<0

Q-----,>.

Figure 1. ADC-B310E Simplified Block Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1·169

ADC-B310E
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltages:
+15V Supply (Pin A30~
-15V Supply (Pin A32)
-5.2V Supply (Pins A18, B18)
+5.2V Supply (Pin A26)
Clock Pulse Input Voltage (Pin A21)
Analog Input Voltage (Pin A28)

As a design tool, the board relieves the
design engineer of the labor-and-timeintensive task of constructing an evaluation
cir-cuit to test the applicability of the
ADC-310 flash converter in their design.
The board allows fast hook-up and prototype evaluation, shortening the design
cycle.

+17V dc
-17V dc
-7Vdc
+7Vdc
+7Vdc
±2.5V dc

TECHNICAL NOTES

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ± 15V, -5.2V, +5V dc power unless otherwise specified.
MIN.

TYP.

MAX.

UNITS

ANALOG INPUTS

oto+ 1

Analog Input Range

Volts
Volts

±0.5
Input Impedance
R54 0 Q (standard)
R54 24 Q (user supplied)
Input Signal Bandwidth

=
=

DIGITAL INPUTS
Digital Input (START CONVERT)
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"
OUTPUTS
Resolution
EOC, Data Outputs
Logic "1"
Logic "0"
Logic Loading "1"
Logic loading "0"
PERFORMANCE
Resolution
Convert Pulse Width
Conversion Rate
Non-Linearity
Differential Non-Linearity
Warm-Up Time for
Stable Operation
POWER SUPPL Y REQUIREMENTS
Power Supply Range:
+15V Supply
-15VSupply
- 5.2V Supply
+5V Supply
Power Supply Current:
+15V Supply
-15V Supply
- 5.2V Supply
+5V Supply
PHYSICAL-ENVIRONMENTAL
Operating Temp. Range
Storage Temp. Range
Mechanical Dimensions
Weight

1-170

-

50
75
10

-

+2
0

-

-

-

+5.5
+0.8
40
1.6

Vdc
Vdc
p.A
mA

8

-

-

Bits

+2.4
0

-

-

+5.5
+0.4
0.4
16

Vdc
Vdc
mA
mA

-

-

10
25
12

-

-

-

-

Ohms
Ohms
MHz

Bits
nSec.
MHz
LSB
LSB
Minutes

-

15

-

+14.5
-14.5
-4.7
+4.5

+15.0
-15.0
-5.2
+5.0

+ 15.5
-15.5
-5.7
+5.5

Vdc
V dc
Vdc
Vdc

-

+ 140
-210
-500
+140

-

mA
mA
mA
mA

0
-25

-

± 1.75
± 1.75

-

+70
+85

°C
°C
3.93"(W) x 6.3"(D) x 0.67"(H)
100(W) x 160(D) x 17(H)mm
Eurocard Size
0.4 Lbs. (175 Grams)

Refer to the Simplified Block Diagram and
the Schematic Diagram for further information. Also refer to Table 1 for complete signal pinout information.
1. The ± 15V dc analog power supply commons labeled "ANA COM" and the
+ 5V, - 5.2V dc digital power supply
commons labeled "DIG COM" are
grounded to one point atJ1 on the board.
DATEL does not recommend having this
common ground outside the board;
noise problems may result from ground
loops.
If it is, however, required to have a common point outside the board, cut the etch
to J1. In this case, avoid creating different potentials between digital and analog grounds on the board. Points labeled
"DIG GND" on the ADC-B310E board
are used for the digital signal grounds.
Likewise, points labeled "ANA GND"
refer to the analog circuitry grounds.
2. Supply the analog input signal to the
coaxial cable input terminal (AIN). This
input signal can be also applied via the
DIN connector. In this case, connect the
two sets of feedthrough holes labeled
"SIG" in Figure 4 with a short coaxial
cable and then supply the signal to the
A28 (ANA IN) and B28 (SIG GND)
terminals.
The short coax cable should be of the
same characteristic impedance as the
input of the ADC-B310E. Refer to
"INPUTS" of the Functional Specifications section for more information.
3. Some components on the board operate
at high temperatures. The ADC-310
operates at 60°C when the board is at
room temperature. DATEL recommends
using the board in a free air circulation
environment.
4. There are several test points (TP1
through TP8) for checking the performance of the board. When using these
test points, only use high-impedance test
probes to check the signals.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

ADC-B310E

•
NOTE: Resistors with "F" following value are
metal film; all others carDoIl

Figure 2. ADC-B310E Schematic Diagram
Performance of the board deteriorates if large external loads
are applied to these pOints. The following signals are present
on the indicated test points:
TEST POINT SIGNAL
TP1
Analog input signal before the StH with
offset adjustment.
TP2
Analog input signal to the ADC-310
TP3
Vref B
TP4
Vcc
TP5
siR Signal
TP6
Clock to the ADC·310
TP7
START CONVERT pulse
TP8
EOC Signal
Digital input and output signals are TTL·compatible. The
width of the START CONVERT pulse should be a minimum
of 25 nanoseconds and should be supplied through a buffer
such as a 74LS240. Logic circuits on the board are driven
by the rising edge of the START CONVERT pulse.
5. The ADC-B310E's design allows it to convert analog input
signals from dc up to 10 MHz. A capacitor in the feedback
loop of the buffer amplifier regulates this analog input signal bandwidth.

Table 1. ADC-B310E Pin Connections
FUNCTION

PIN

PIN

FUNCTION

DIGGND
DIGGND
DIGGND
BIT 1 (MSB)
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
BIT9
BIT 10 (LSB)
NC
NC
NC
NC
-5.2V
NC
NC
START CONVERT
EOC
NC
NC
NC
+5V
NC
ANA IN
NC
+15V
NC
-15V

A1
A2
A3

B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32

DIG GND
DIGGND
DIGGND
DIGGND
DIGGND
DIGGND
DIGGND
DIGGND
DIGGND
DIGGND
DIGGND
DIGGND
DIGGND
DIG COM
DIG COM
NC
NC
-5.2V
DIG COM
DIG COM
DIGGND
DIGGND
DIGGND
DIGGND
NC
ANAGND
ANAGND
SIGGND
ANA COM
ANA COM
ANA COM
ANA COM

A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-171

ADC-B310E

START
CONVERT
PULSE N
4

25

SIR CLOCK

,,
_oJ

Td

Tc

59

21
AID CLOCK - - t + - - - - - . t - ,

,,

\
\
\

I
I

_J

DATA
N-l

N-2

N

To

25
-1
\
I

\

_J

EOC

UNIT: NANOSECONDS
Ts and Td can be varied.
Figure 3. ADC-B310E Timing Diagram

THEORY OF OPERATION
The following describes the operation of the ADC-B310E
Sampling AID board as configured from the factory. Refer to
the ADC-B310E schematic diagram (Figure 2) and timing diagram (Figure 3) as needed.
The ADC-B310E receives the analog input signal through either
the board-edge pin (pin A28) or the coaxial analog input connector (refer to Technical Note 2). The signal is offset adjusted
and sent to the sample-and-hold amplifier. The next START
CONVERT pulse "locks-in" the sampled signal to the gaincompensated amplifier.
There are two resistors connected between this amplifier output and the input to the ADC-310. These resistors are adjustable and designed to prevent parasitic oscillations. There are
two on-board power supplies/regulators providing the voltages
necessary for stable operation of the ADC-310 and its supporting circuitry.
The ADC-310 analog-to-digital conversion is done in two steps.
The ADC-310 contains two 5-bit flash AID's consisting of comparators. These two stages are done sequentially. The analog
input to the ADC-310 must be stable throughout the conversion,
a requirement satisfied by the on-board sample-and-hold (S/H)
device.

1-172

The rising edge of the START CONVERT pulse (for conversion
N), changes the S/H device from the hold mode into the sample (or acquisition) mode. The acquisition mode lasts for 25
nanoseconds (factory setting) and is determined by the internal gate delays and delay line 1 (Dl1). To lengthen the acquisition time, vary the setting of Dl1 (see Figure 5).
Upon going into the hold mode, a delay time occurs, allowing
the signal to settle at the output buffer of the S/H. This delay
is approximately 37 nanoseconds, determined by the internal
gate delays as well as Dl1 and Dl2. Dl1 can be varied per
Figure 5 to lengthen the duration of the hold mode.
Upon the internal clock pin going low (Pin 1 of the ADC-310),
the internal comparators of the ADC-310 latch the analog input.
When the ClK goes high, the previous conversion, N-1, is
present at the 10176 output latch of the ADC-310. The N-2 data
is now available at the output of the 10125 buffer, thus at the output of.the ADC-B310E.
Data from conversion "N" will become available at the output
of the ADC-B310E after three START CONVERT pulses have
been issued. An EOC signal is given after the START CONVERT pulse for conversion "N" is given, indicating data from
conversion "N-2" is now valid to be read.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC·B310E
2-(2.8)

INCHES

\iiiiiiI
DAMP

TPl
21

il ~£~

~

AIN

°

®D

10176 Z6

r:=J

HA2539·5

o[J

H

° ®O

TP2

S@=
=
r:=J
@OTP.
SHM·HUMC

~
Z3

i!J

D

Vee
ADJ

Jl

SIG

~

10176 ZJ

~~I

IG

[§:Q] 0

J

10125 Z9

10125 Z10

ZM0530

~ElAY

TP6

10125 Z8

<
~08CJ

D

0 51H

l3

2724211815

TPS

30000,,)

~ ~ u~" 1

aa0

i ,--

12 . -_ _ _-,

(~, ~'"

DO]

0

O~ILCl 00=

8-310E S N _ _ _

6.3"
(160)

0

D~
SIG

---~------------

Figure 4. ADC-B310E Component Layout Diagram

CALIBRATION
Following are descriptions of the six trimpots on the ADC-B310E
board. All of the six trimpots are adjusted for optimum performance atthetime of shipment. Should adjustment be required,
use the following procedures. Refer to Figure4 forthe locations
of these components.
Vee Trimmer
It is necessary to supply + 1.6V to the Vcc pin of the ADC·310.
This supply voltage is generated from a +5V regulator (+5 VA)
on the ADC-B310E board and adjusted by the trimpot labeled
"VCCADJ". Connecta high·impedancedigital multimetertotest
point TP4 and adjust the VCC trimpot for + 1.600V.
Adjust this trimpot correctly since the overall linearity of the
device is sensitive to this adjustment. Repeat this adjustment
whenever replacing the ADC·31O on the ADC-8310E Sampling
AiD board.
Offset Trimmer
Using this trimpot allows an offset range adjustment between
-2.4V to +2.4V dc.
1. Unipolar Operation
Adjustthe Offsettrimpotwith +0.4883 mV (+ 1/2 LSB) applied
to ANA I N so the straight binary output code flickers between
0000 0000 00 and 0000 0000 01.
2. Bipolar Operation
Adjust the Offset trimpot with -499.51 mV (- FS + 1/2 LSB)
applied to ANA IN so the offset binary output code flickers
between 0000 0000 00 and 0000 0000 01.

Gain Trimmer
Thistrimmer adjusts the -2Vreferencevoltage required forthe
ADC·310. Adjust the Gain adjust trimpot with +FS-11I2 LSB
applied to ANA IN (+0.99853V for Unipolar or +0.49853V for
Bipolar operation) so that the straight or offset binary output code
flickers between 1111 1111 10 and 1111 111111.
Linearity Trimmer
Thistrimpot fine tunes the linearityolthe board. Connecta highimpedance digital multimeter to test pOint TP3 and ANA GND
and measure this voltage. Reconnect the multimeter to pin 21
(VREF ADJ 2) of the ADC·310 and ANA GND, and adjust the
Linearitytrimpotto one half (1/2) olthe voltage indicated on test
point TP3.
Damping Trimmers "DAMP H" and "DAMP L"
The differential linearity of the board is sensitive to the frequency
of the analog input signal. At the time of shipment, the differ·
entiallinearity of the board is fine tuned under conditions of
Yin = ±0.5V, Fin = 5 MHz and Fs = 10 MHz uSing the envelope method. When the differential linearity is suspect, use
these two trimmers to re-adjust the differential linearity.
Differential linearity is most sensitive to changes in the setting
of the DAMP L potentiometer. Adjust the DAMP L potentiometer first without moving DAMP H.
The value of DAMP H will be around zero ohms at the time of
shipment. When the differential linearity is not adjustable with
DAM P L, increase the value of DAM P H by a small amou nt and
then adjustthe differential linearity with DAMP L. Repeatthese
two adjustments until proper operation is attained. When the
values of DAMP H and DAMP L are varied, gain error is
introduced into the ADC-8310E. It will be necessary to adjust
the gain at this time.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

1-173

ADC·B310E
To confirm the operation ofthe ADC-B310E, vary the input voltage with a precision reference voltage source to obtain the output coding listed in Tables 2 and 3. Repeat the previous steps
if necessary to achieve the desired operation ofthe ADC-B310E.

HOLD MODE
DELAY

S/H
ACQUISITION

t:r IME

Table 2. Unipolar Output Coding
30

UNIPOLAR
SCALE
0
+ 1 LSB
+'!4 FS
+ 3/s FS
+ 1/2 FS
+ 3/4 FS
+ 7/s FS
+FS-1 lSB

INPUT
VOLTAGE
+0.0000
+0.9766
+250
+375
+500
+750
+875
+999.02

V
mV
mV
mV
mV
mV
mV
mV

27

24

21

18

15

12

9

STRAIGHT
BINARY

TP7

0000000000
0000000001
0100000000
0110000000
1000000000
1100000000
1110000000
1111111111

9

5

6

10

4

11

12

ZM-05-60

DL1

Figure 5. SIR and Delay Selection Settings

Table 3. Bipolar Output Coding
BIPOLAR INPUT
SCALE
- FS
- FS + 1 lSB
- 3,4 FS
-1/2 FS
+0
+ 1/2 FS
+ 3/4 FS
+FS-1 lSB

INPUT
VOLTAGE
-500
-499.02
-375
-250
+0
+250
+375
+499.02

mV
mV
mV
mV
mV
mV
mV
mV

OFFSET
BINARY
0000000000
0000000001
0110000000
0100000000
1000000000
1100000000
1110000000
1111111111

TIMING SETTING

1. There are feedthrough holes labeled as "12, 15, ...30" close
tothe Dl1 delay line component and two more holes labeled
as "DELAY" and "S/H" close to these holes. Refer to Figure
5 for the specific locations of these holes.
2. Althe time of shipmentfrom the factory, DELAY is connected
to 21 yielding a Td of 42 nanoseconds and SIR is connected
to Tap 9 of Dl1 yielding a Ts of 18 nanoseconds.
3. Delay time increases by 6 nanoseconds by connecting to a
higher order tap. For example, Td is increased from 42 to 48
nanoseconds by changing the DELAY jumper wire connection from tap 21 to 24. Likewise, Ts increases frum 18 nanoseconds to 24 nanoseconds once the jumper wire connection
is changed from tap 9 of DL1 to tap 12.

ADC-B310E

1-174

The time delays for DL1 are listed in the following table:
ACQUISITION MODE TIME SETTING
TAP
15
12
9

SIH SETTING (Ts)
30 nSec.
24 nSec.
18 nSec. "S/H" (Factory Setting)

HOLD MODE SETTLING TIME DELAY
TAP
30
27
24
21
18

TIME DELAY (Td)
60 nSec.
54 nSec.
48 nSec.
42 nSec. "Delay" (Factory Setting)
36 nSec.

TIMING CHANGE
It is possible to change the timing relation of S/H ClK and ADC
ClK.lftheanalog input signal frequency is lower than 100 KHz
or it is not necessary to obtain ±1.75 lSB bit accuracy, then the
conversion rate can be increased toa value greater than 12 MHZ.
The values of Ts and Td depend on the jumper setting of delay
line DL1 on the board.

ORDERING INFORMATION
ADC-310 Sampling AID Board

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-B500, ADC-B505
HIGH-SPEED A/D-SHM
EVALUATION BOARDS
FEATURES

•

• 12-Bit, 1.25 MHz/1.1 MHz conversion rates
• Includes ADC-500/505MC
• Includes SHM-45MC
• Jumper-plug selectable input ranges
• On-board offset and gain adjustments
• On-board -5V supply
• BNC connectors for start convert/analog inputs
• Connectors provided with 2 foot flat ribbon
cables using interwoven grounds.

DESIGNED FOR PERFORMANCE EVALUATION OF DATEL'S ADC·5001505 AND SHM45, THE ADC-B500 AND ADC
B505 EVALUATION BOARDS ARE COMPLETE 12·BIT AID SYSTEMS WITH 1.25 MHz AND 1.1 MHz CONVERSION RATES
RESPECTIVELY.
GENERAL DESCRIPTION
DATEL offers three models of its ADC-8S00 Series highspeed evaluation boards. The ADC-8S00 includes the
ADC-S008MC and SHM-4SMC while the ADC-8S0S includes
the ADC-SOS8MC and SHM-4SMC. The final version offered
is the ADC-8S00-1 which is an evaluation board without the AID
and SHM hybrid converters. The ADC-8S00-1 is usable as an
incoming inspection test fixture. Additionally, users purchasing military temperature grades of the ADC-SOS and SHM-4S
would be able to evaluate these converters over the commercial temperature range using the ADC-8S00-1 for initial system
prototyping.
ANALOG GRND
DIGITAL

C1

J4
START CONVERT
(BNC)

+lSV

-15V
C14

C1.

.2
(34 PIN)

19

J3
INPUT
(BNC)

U2
ADC·500J505

20
21
22
23
24
25
26
27
28
29

I

else

•
10

12
14

16

18
20
22
24
2.

~~~~~}:1I~-r----~~~~---T--~~~~~~~========~~2.M~
EciC
VL
.2

-

VERFlON

~DIGITAL

GROUND

Figure 1. ADC-B500/B505 Evaluation Board Schematic

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

1-175

ADC·B500, ·B505
GENERAL DESCRIPTION (cont.)
The ADC-8500's conversion rate is 1.25 MHz while the ADC8505 offers a 1.1 M Hz conversion rate. The evaluation boards
feature selection of six full scale input ranges: 0 to -5V, 0 to
-10V, 0 to -20V, 0 to + 10V, ±5V, and ± 10Vdc. Jumper-plugs
are used for ease of range selection.
The functionality of the evaluation boards includes adjustments
for calibration of the offset and gain errors. A minus 5V supply
required for the ADC-500/505 is generated by the evaluation
boards to aid in quick prototype set-up. 8NC inputs are provided
for easy interface to start convert and analog input Signal generators. Connectors for power supply and digital outputs are
provided with 2 feet of flat ribbon cables for ease of use. The
flat ribbon cables use interwoven grounds to assure good
ground connections.

ABSOLUTE MAXIMUM RATINGS
PARAMETERS

MINIMUM

MAXIMUM

UNITS

+15V Supply .............
-15V Supply. ...........
+5V Supply .............

0
0
-0.5

+18
-18
+7

Volts de
Volts de
Volts de

Digital Inputs
Analog Input .............

-0.3
- 15

+5.5
+ 15

Volts de
Volts de

FUNCTIONAL SPECIFICATIONS (cont.)

DESCRIPTION

FUNCTIONAL SPECIFICATIONS

MIN.

TYP.

MAX.

o to 5
o to -10
oto +10
oto -20

INPUTS
Input Voltage Ranges ..... .

UNITS

Volts de
Volts de
Valls de

±10, ±5
Input, Impedance
20V FSR ....... .
10V FSR .............. .
5V FSR ............... .
Logic Levels: Logic 1 ......
Logic 0 .... ..
Logic Loading: Logic 1 .... .
Logic 0 .... .

lK
lK
500
0.8

ohm
ohm
ohm
Volts de
Volts de

2.5
-100

~A
~A

2.0

OUTPUTS
Output Coding:

Logic Levels: Logic 1 ..... .
Logic 0 ..... .
Logic Loading: Logic 1 .... .
Logic 0 .... .
Internal Reference
Voltage, +25°C ..... .
Drift ................. .
External Current ...... .

straight binary/offset binary
complementary binary
complementary offset binary
2.4
0.4

9.98

±5

Valls de
Valls de

-160

~A

6.4

mA

10.02
± 30

Valls de
ppm/oC
mA

1.5

TRACK MODE DYNAMICS
Frequency Response:
Small Signal (-3dB) ... .
Slew Rate ............. ..

16

MHz

300

V1~S

TRACK TO HOLD SWITCHING
Aperture Delay Time
Aperture Uncertainty
(Jitter) ............ .
Setting Time:
10V to ±0.1% FS
(±1 mV) ........... .
10V to ±.I'1o FS
(±10mV) .............. .

nS
pS

±50

Feedthrough Rejection .....
Signal to Noise Ratio (SNR) ...
Inband Harmonics
dc to 100KHz ...........
100KHz to 500KHz .......

UNITS

-

-74

-

dB
dB

-

dB
dB

-72

-80 below FS

-72
-72

-80 below FS
-75 below FS

-

PERFORMANCE FOR ±10V RANGE

Integral Nonlinearity:
+25°C .. .......... , ...
OQC to + 70 QC .. .........
Integral Nonlin. Tempco ....
Differential Nonlinearity:
.........
+25°C .....
OOC to + 70 QC ..........
Differential Nonlin. Tempco .
Full·Scale Absol. Accuracy:
+25°C ........... .....
O°C to +70°C .. ..
.. ...
Unipolar Zero Error, +25 QC .
Unipolar Zero Tempco .....
Bipolar Offset Error, +25°C .
Bipolar Offset Tempco .....
Gain Error, +25°C .........
Gain Tempco ...... .. .....
Conversion Rate:
ADC·B500;
+25°C. .. .... .....
o to 70°C ... .. . ... . ...
ADC·B505:
+25°C ........ .... .. .
o to 70°C .. .........
No Missing Codes (12 Bits):

±0.0125% FSRmax
± 0.0125% FSR max

-

-

± 0.0125% FSR
± 0.0125% FSR

.

-

-

-

±5
±6
±2
±13
±2
±13
±3
±18

-

-

1.25
1.20

1.5

-

±1fzLSB
±1I2LSB
±3

ppm/oC

±112

LSB
LSB
ppm/oC

±1f2
±2
±12
±15
±5
±25
±5
±25
±8

±40

-

LSB
LSB
LSB
ppm 1°C
LSB
ppm/oC
LSB
ppmloC

MHz
MHz

1.19
MHz
1.14
MHz
Over the Operating Temp. Range

POWER SUPPLY REQUIREMENTS
Power Supply Range:
+ 15V dc Supply ....... ..
-15V dc Supply ... ... ...
+5V de Supply .... ....
Power Supply Current:
+15V Supply. ....... ..
~15V Supply ....... ....
+5V Supply.
.....
Power DIssipation ..... ....
Power Supply Rejection. ..

100

40

nS
nS

Operating Temp. Range:
ADC·B500 ......... ..
Storage Temperature
Range. .. . .. ..... .. .

,.

...

Weight.

1-176

MAX.

+ 14.25
-14.25
+4.75

+15
-15
+5

+15.75
-15.75
+5.25

Volts de
Volts de
Volts de

-

-

0

-

+70

-55

-

+85

°C

6

oz

mA
+48
-325
mA
+85
mA
'6.1
Watts
001
%FSR/%V

PHYSICAL·ENVIRONMENTAL
60

HOLD TO TRACK DYNAMICS

Acquisition Time:
10V step to ±1.0mV
(.01% FS) ........ .
10V step to ± 10mV
(.I%FS) ......... .

TYP.

DYNAMIC PERFORMANCE

Apply over the operating temperature range and over the power
supply range unless otherwise specified.

DESCRIPTION

MIN.

160

200

nS

100

170

nS

..... .... .......

°C

'The ADC·500/505 and SHM·45 combined maximum power dissipation
is 2.7W.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

ADC-8500, -8505

~
1

NOTE. NOT DRAWN TOSCAL[

- - - - - - - - - "- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

:
:
-t~~~In~~~ ---,!-'_____________________________________________
1

'

1

START
CONVERT

l:

---n- i
~

~

:

l05ntfCc MINIMUM

~J--~,----------------------------------------------

1

,

J--

J

•

1

--T1

1
1

: I

:

"

I

,
,

,

-1:

I
:

,i

,

P : - '

,

I I

:

,

I

IOOnSec HOLD MODE SE:TTLING TIME

200"S,,~ ACOUISITIONTIMl

'

~--------

:

:

1

I

,+,

: I I

Iroc

I

:

1

"

1

20 n5el

MI~-o>-:...:A=DJ:..;'_ _

-15V

...-.....---1-023

GAIN
ADJ.

GAIN
ADJ.

200

~~~LOG

ANALOG o------4~-+--o 31
GND.
ANALOG
32
IN

...-.---+--0 23
200

0 - - - - _ - - + - - 0 31

~NALOG 0 - - - - - - - + - - 0 3 2

UNIPOLAR OPERATION

BIPOLAR OPERATION

1. Apply START CONVERT pulses to pin 24.
2. Apply a precision reference voltage source to
ANALOG IN (pin 32) and ANALOG GROUND
(pin 31). Adjust the output of the voltage
reference to Zero + '/2 LSB ( + 1.2mV). Adjust
the zero trim for an output code of between
0000 0000 0000 and 0000 0000 0001.
3. Adjust the output of the voltage reference to
+ F.S. _1'/2 LSB (+ 9.9963V). Adjust the
GAIN trim for an output code of between 1111
1111 1110 and 1111 1111 1111.

1. Apply START CONVERT pulses to pin 24.
2. Apply a precision reference voltage source to
ANALOG IN (pin 32) and ANALOG GROUND
(pin 31). Adjust the output of the voltage
reference to O.OOOOV. Adjust the offset trim for
an output code of 1000 0000 0000.
3. Adjust the output of the voltage reference to
+ F.S. - 1'/2 LSB ( + 4.9963V). Adjust the
GAIN trim for an output code of 1111 1111
1110 and 1111 1111 1111.

OUTPUT CODING
ORDERING INFORMATION

UNIPOLAR (OV TO + 10V)
SCALE

INPUT VOLTAGE

STRAIGHT BINARY

+FS-1LSB

+9.9976V
+8.7S00V

+2.50DOV
+O.OO24V

111111111111
1110 DODO DODO
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0001

O.DODOV

0000 0000 0000

+%FS

+ 7.5000V

+%FS
+%FS

+5.0000V

+%
+1 LSB
0

BIPOLAR ( - 5V TO

INPUT VOLTAGE

OFFSET BINARY

+FS -1 LSB

+4.9976V
+3.7500V
+2.5000V
O.OOOOV
-2.5000V
-3.7500V
-4.9976V
-S.OOOOV

111111111111
1110 0000 0000

+V2 FS
0
_1/2 FS

-%FS
-FS+1LSB

-FS

ACCESSORIES
Part Number
DILS-2
TP20, TP200,
TP20K

Description
Mating Sockets: (2 per module)
Trimming Potentiometers

+ 5VI

SCALE

+%FS

ADC-EH12B3

1100 0000 0000
1000
0100
0010
0000
0000

0000
0000
0000
0000
0000

0000
0000
0000
0001
0000

TWO'S COMPLEMENT"
0111
0110
0100
0000
1100
1010

1111
0000
0000
ooaD
0000
0000
1000 0000
1000 0000

1111
0000
0000
0000
0000
0000
0001
O('JO

* Using MSB output for Bit 1

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

1-191

ADC·EH8B
Fast, 8-Bit Analog-to-Digital
Converters

FEATURES
• 8-Bit resolution
• 4.0 and 2.0 microseconds conversion
time
• Unipolar or bipolar operation
• Parallel and serial outputs
• Low cost

+5V de + 15V de -15V de PWA GROUND
20

ANALOG

GROUND

GENERAL DESCRIPTION
The model ADC·EH8B is a fast, 8-bit successive approximation type analog-todigital converter in a compact 2 x 2 x 0.375
inch module. These converters are low
cost devices with application in pulse code
modulation systems and instrumentation
and control systems requiring fast data
conversion rates up to 500,000 per second. There are two models to choose from
based on conversion speed: ADC-EH8B1
with a conversion time of 4.0 microseconds (250 kHz rate), and ADC·EH8B2
with a conversion time of 2.0 microseconds (500 kHz rate).

ANALOG
INPUT
BIPOLAR
OFFSET

21

r---L-~~-L-L-L-L-L-c____~~EOC
(STATUS)

2

CLOCK
OUT

""1

BIT NO.

MSB

The high speed in a small size is made
possible by the use of an MSI integrated
circuit which provides all the necessary
successive approximation logic, along with
other new integrated circuit components.
The analog input range is either unipolar
o to + 10V or bipolar -5V to +5V, determined by external pin connection. For
unipolar operation no external adjustments are necessary; for bipolar operation
only a bipolar offset adjustment must be
made externally. Parallel output coding is
straight binary for unipolar operation and
offset binary or two's complement for
bipolar operation. A serial output gives
successive decision pulses in NRZ format
with straight or offset binary coding. Other
outputs are clock output for synchronization with serial data, and MSB output for
two's complement coding.
Other specifications include full scale
temperature coefficient of 50 ppm/oC
maximum, long term stability of 0.05%1
year, and linearity of ± 1/2 LSB. Power requirement is ± 15V dc and + 5V dc.

1

2

3

4

5

6

MSa

7

SERIAL
DATA
OUT

8
LSB

~-------vr------~

PARALLEL DATA OUT

MECHANICAL DIMENSIONS
INCHES (MM)

INPUT/OUTPUT
CONNECTIONS

P'N

FUNCTION

1
2
3
4

E.O.C. (STATUS)

5
6

BIT lOUT (MSB)
BIT 2 our
BIT 3 OUT
BIT 4 OUT
BIT 5 our
BIT 6 OUT
BIT 7 OUT
BIT 8 OUT (lSB)
CLOCK OUT
+SV POWER IN
+,15V POWER IN
-15V POWER IN
POWER GROUND
BIPOLAR OFFSET
ANALOG GROUND
ANALOG INPUT

SIDE VIEW

0.020 DIA

110 PINS (0,5)

.17 __________________ 1
• ,8

2

.,9
.20
.21

3
4
5

o
o

------,- 1.650

~1_150

-.-L..

025 - - - - - - - - - _______ 9
10
11
12
13

o

.~

AT q.100 EACH

0

0------1.8oo-----....\
(45,7)

0.'50

4 SPACES

.32----------------160

f - o.
l .

•
9

7 SPACES
AT 0.100 EACH

6
7
024 ---------------~- 8
BOTTOM VIEW

o
o
o
o

7

--,-~:::~

10
11
12
13
17

18

"

20
21
31
32

SERIAL DATA OUTPUT
START CONVERT

BiT1 OUT (MSB)

- - - - 0.150
"0"

~ 0.100

NOTES:
1. OPEN DOTS DESIGNATE OMITTED PINS.
2. 0.100 INCH = 2,5 mm, 0.150 INCH = 3,8 mm.

1-192

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-EHS8
FUNCTIONAL SPECIFICATIONS
Typical at 25 ·C, ± 15V and + 5V supplies, unless otherwise
indicated.
INPUTS

PERFORMANCE

Analog Input Range ........ OV to + 10V Full-Scale or ± 5V FullScale
Input Impedance ........... 4.45K ohms ± 50 ohms
Input Overvoltage .......... ± 20V (no damage)
Start Conversion ........... 2V minimum to 5.5V maximum
positive pulse with duration 01100
nanoseconds minimum. Rise and fall
times < 50 nanoseconds.
Logic "1" resets converter.
Logic "0" initiates conversion.
Loading: 1 TTL load

Resolution ................
Linearity Error .............
Differential Nonlinearity .....
Temp. Coeff. of Gain •.......
Temp. Coeff. of Zero,
Unipolar ................
Temp. Coeff. of Offset,
Bipolar .................
Long Term Stability .........
Power Supply Rejection .....

8 Bits (1 part in 256)
± 112 LSB maximum.
± 1/2 LSB maximum.
± 50 ppm/oC maximum.
± 100 p.V/oC maximum.

± 35 ppm of FS/oC maximum.
± 0.05%/year
± 0.02% of Full-Scalel% supply,
maximum.
Conversion Time ........... 4.0 microseconds maximum,
ADC-EH8B1
2.0 microseconds maximum,
ADC-EH8B2

OUTPUTS
Parallel Output Data ........ 8 parallel lines of data held until next
conversion command.
V out ("0") :s + O.4V
V out ("1") ;,: + 2.4V
Each output capable of driving up to
4 TTL loads.
Coding, Unipolar Operation .. Straight Binary, positive true.
Bipolar Operation ... Offset Binary, positive true.
Two's Complement, positive true.
Serial Output Data .......... NRZ successive decision pulse output
generated during conversion, with
MSB first. Straight binary or offset
binary coding.
Loading: 4 TTL loads.
End of Conversion (EOC) .... Conversion Status Signal.
V out ("0") :s O.4V indicates
conversion time completed.
V out ("1") ;,: + 2.4V during reset and
conversion periods.
Loading: 4 TTL loads.
Clock Output .............. Internal clock pulse train of negative
going pulses from + 5V to OV gated
on during conversion time.
Loading: 6 TTL loads.

POWER REQUIREMENTS
Power Supply Voltage

... ...

± 15V dc ±0.5V at 25 mA maximum .
+5V dc ±0.25V at 125 mA
maximum.

PHYSICAUENVIRONMENTAL
Operating Temp. Range", ..
Storage Temp. Range .......
Relative Humidity . . . . . . . . ..
Case Size .................

O°C to + 70°C
-55°Cto +85°C
Up to 100% non-condensing
2 x 2 x 0.375 inches (50,8 x 50,8 x
9,5 mm)
Case Material ...........•.. Black diallyl phthalate per MIL-M-14
Pins ..................... 0.020" round, gold plated, 0.250"
long minimum.
Weight ...........•....... 2 ounces maximum (57 grams)

Output: 10101010

- _
~
-----------------------------------------0
-----------------------_-_-_-,

gb~~,rERT

100 nsec mlO

I I

-,

E.O.C.
(STATUS)

80 nsec typ

I
I I
I
'I
.~ L: ~O nsec'lI

Iii

CLOCK

OUT

I

-·--·T 4 .. - - - - - - -

1yp.

I-T1

------HI (
SERIAL

DATA
OUT

,

I,

--1I

25nsec. typo

fy~.nsec.

II BIT 1 I

----11---rI
_ _-;,1

BIT 1
(MSB)
BIT 2

--,

I

:

nsec. I

25
typo

I,
I.

______.LJ

I
I

1

I

--1-+- 4

:

I

I

~~

,--r-t-i-I--t--i-t-~~;_1

I
~gg

I

1
----.1--/-------0

I

---t'
BIT 8
(LSB)

(MSB)I

: ~~~g~

0

I
T,

~6g

1'----~-BIT-;--1

I
T2

~~

T3

~cig

T4

gggg ~~:~: ~g:

I.

I

OFF

0

I

TIMING DIAGRAM FOR ADC·EH8B

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-193

ADC-EHS8
ADC-EH8B CALIBRATION
+ 15V de
017
CONNECTION FOR
BIPOLAR OPERATION
r-----~--~1B
ONLY

"-.

a 19

BOTTOM
VIEW

020
~-'VVVv-----t--<>

TRIMMING POTENTIOMETER
IS 100 PPM/DC CERMET TYPE,
15 TURN. ORDER DATEL MODEL
TP100.

21

100 n

UNIPOLAR OPERATION

BIPOLAR OPERATION

1. UNIPOLAR - No adjustments are necessary
and 100n trimming pot is not used. Full scale
and zero are internally set to better than '12
LSB. Pin 21 is left open.

2. BIPOLAR - Connect pin 18 (+ 15 V de) to pin
21 through a 1DOn trimming potentiometer as
shown. Connect a precision voltage source to
pin 32 and set the input voltage to + V2 LSB or
+0.020V. Adjust the trimming potentiometer
so that the output code flickers equally between 1000 0000 and 1000 0001.

OUTPUT CODING
BIPOLAR (
UNIPOLAR (0 TO ... 10V)

SCALE

INPUT VOLTAGE

STRAIGHT BINARY

+FS-l LSB
+7!e FS
+%FS
+% FS
+%FS

+9.96V

11111111
1110 0000
1100 0000
1000 0000
0100 0000
0000 0001
0000 0000

+1 LSB

0

+8.75V
+ 7.S0V

+5.00V
+2.S0V
+O.04V
O.OOV

- 5V TO + 5V)

SCALE

INPUT VOLTAGE

OFFSET BIN

+FS-l LSB
+%FS

+4.96V
+3.75V
+2.50V
O.OOV
-2.S0V
-3.7SV
-4.96V
-S.OOV

11111111
11100000
1100 0000
1000 0000
0100 0000
0010 0000
0000 0001
0000 0000

+1fz FS
0

-%FS
-%FS
-FS+1LSB

-FS

2'S COMPLEMENT

0111
0110
0100
0000
1100
1010
1000
1000

1111
0000
0000
0000
0000
0000

0001
0000

ORDERING INFORMATION
ADC-EHB8

Lc

CONVERSION TIME

1 = 4.0 Microseconds
2 = 2.0 Microseconds

1-194

ACCESSORIES
Part Number

Description

DILS-2
TP100

Mating Sockets: (2 per module)
Trimming Potentiometers

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-EK Series
Monolithic Integrating
Analog-to-Digital Converters

FEATURES
•
•
•
•
•
•

Monolithic CMOS
Binary or BCD models
20 mW power consumption
To 12-bit accuracy
No missing codes
Low cost

REFERENCE 13

GENERAL DESCRIPTION
The ADC-EK series are low power, integrating AID converters fabricated on a
single monolithic chip using CMOS
technology. The circuit employs a charge
balancing integrator, current switch comparator, clock counter, data counter, and
control logic circuitry to implement conversion. The charge balancing integration
technique gives high linearity and noise
immunity along with inherent monotonicity
resulting in no missing codes. Output data
appears in parallel form on latched outputs
which are CMOS, low power TTL, or low
power Schottky TTL compatible. The
ADC-EK series consists of 5 different
models with 8-, 10-, and 12-bit binary
coding and 3% digit BCD coding.
Conversion time is 1.8 to 24 milliseconds
maximum depending on model. Nonlinearity is ± % LSB maximum while differential nonlinearity is ± % LSB typical. Other
specifications include gain tempco of ± 25
ppm/oC typical and zero drift of ± 50
/lV/oC maximum. An external reference,
integrating capacitor, and several other
components are required for operation.
The analog input voltage range is programmable by means of an external
resistor which sets the current into the integrator at 10 ~ full scale. Standard
operating mode is unipolar but bipolar
operation is accomplished using an external op amp to provide an offset current
from the reference.

AMPLIFIER
OUT

~Np~~OG

14

ZERO
ADJUST

DATA COUNTER
AND
OUTPUT
LATCHES

1

MSB

3

4

MSB

5

6

7

B

OVERRANGE
(AOC-EK12D ONLY)

9 10 11 12

MSB

LSB

12 BITS 10 BITS 8 BITS

MECHANICAL DIMENSIONS
INCHES (MM)
CERAMIC

PLASTIC
PACKAGE

PACKAGE

1.500

~(38,1)~

T
0.600

OATH

(15,1)

T
g.~~~

1

16'~~ o!1'r;-n"""'TTTTrTrn''rrrrrn'..1.
0.250 1

1 'Tn'lmncn-n===,J
1

12

16,41,-_ _ _ _ _ _- ,

[~

H

0.100

[-0100
(2,5)

(2,5)

CERDIP

INPUT/OUTPUT CONNECTORS

Power requirement is ± 5V dc at 2 mA,
giving a power consumption of only 20
mW. The units are packaged in 24 pin
ceramic or plastic DIP's.
CAUTION: The ADC-EK Series are CMOS
devices and should be handled carefully to
prevent static charge pickup which might
damage the devices. The devices should
be kept in the shipping containers until
ready for installation.

2

BCD

PIN

,--------,..9.:.?.lQ

~I
0.023
(5,8)

1
2
3
4
5
6
7
8
9
10
11
12

FUNCTION
BIT 1 OUT (MSB - 12 BITS)
BIT 20UT
BIT 3 OUT (MSB)-10 BITS
BIT 4 OUT
BIT 5 OUT (MSB - 8 BITS)
BIT 6 OUT
BIT 7 OUT
BIT 8 OUT
BIT 9 OUT
BIT100UT
BIT 11 OUT
BIT 12 OUT (LSB-ALL)

PIN

FUNCTION

13
14
15
16
17
18
19
20
21
22
23
24

REFERENCE
ANALOG INPUT
AMPLIFIER OUT
ZERO ADJUST
BIAS
-5V POWER
+5V POWER
GROUND
START CONVERT
E.O.C. (STATUS)
DATA VALID
BCD OVERRANGE'

'NO CONNECTION FOR OTHER MODELS
NOTE:
ForB- and 10-bit models, do not connect to unused data output
terminals since they have internal connections.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-195

ADC-EK SERIES
ABSOLUTE MAXIMUM RATINGS

ADC·EK8B/
10B/12B

liN .....•....•.••••.........
IREF ...••.•...............•.
Digital Input Voltage .•..•••...
Voo - V.................... .
Package Dissipation .......•.•

I

ADC·EK12DC/
DR/OM

±10 mA
±10 mA
-0.3V to Voo + 0.3V
18V
SOO mW

PHYSICAUENVIRONMENTAL
Operating Temp. Range .•••..•
Storage Temp. Range ........•
Package ....................

See Ordering Information
- 6S·C to + lS0·C
24 Pin DIP

FOOTNOTES:
1. For the ADC-EK 120M only. Initial gain error is ±5%. Gain. Tempeo is ±40

ppm/DC typical, ± 80 ppm/DC maximum and Zero Drift Tempco is 80
2. ADC-EK 120M outputs can sink and source 500 ~.
3. Supply Sensitivity given for Voo
VSS
SV ± lV.

=

~V/oC.

=

FUNCTIONAL SPECIFICATIONS
Typical at 2S·C, ±SV Supplies, RBIAS = lOOK, unless otherwise
noted.

TECHNICAL NOTES

ANALOG INPUTS
Type Analog Input ..•.•..•....
Full Scale Input Current ........
Reference Current .......••...

Single Ended
+10~

-20 p.A

DIGITAL INPUTS
Log!cal ::1:: VIN ...........••.
Logical 0 VIN ......•..••...
Start Convert Pulse ...........

3.SV minimum
l.SV maximum

> 3.SV for SOO nanoseconds
minimum

OUTPUTS
Parallel Output Data ..•..•.... 8, 10, 12 Lines112 Lines and
Overrange
Logic "1" Output Voltage ••....
+4.SV minimum at -10~.
+2.4V minimum at -360 ~2
Logic "0" Output Voltage •...••
+0.4 maximum at -360 ~2
E.O.C. (Status) ..............
High During Conversion, Low
When Completed
Data Valid .•...............•• High When Data Valid. Low When
Data Changing
PERFORMANCE
Resolution .................. 8, 10, 12 Bits
3'12 Digits
Coding ......•.••........... Straight Binary BCD
Nonlinearity ..•.••...•....... % LSB,
maximum
0.02S% maximum
Differential Nonlinearity . . . • . . . Yo LSB, typical.
% LSB
maximum
0.02S% maximum
Diff. Nonlinearity Tempco ......
± 2.S ppm/DC typical,
± S ppm/DC maximum
Over Operating Temperature
No Missing Codes .•..........
Range
Initial Gain Error, Adj. to Zero ...
+S, -3% maximum'
Gain Temperature Coefficient ... ± 2S ppm/DC typical, ± 7S ppm/DC
maximum'
Initial Zero Error, Adj. to Zero ...
+ SO mV maximum
± 50 p.V/·C maximum'
Zero Drift Tempco .•..........
Conversion Time, maximum. . .. 1.8 milliseconds 12 milliseconds
(8 Bits)
(3% Digits)
6 milliseconds
(10 Bits)
24 milliseconds
(12 Bits)
± O.OS% of Full-Scale Gain3
Power Supply Sensitivity ......
POWER REQUIREMENTS
Voltage, Rated Performance ....
Voltage Range, Operating ......
Supply Quiescent Current
ADC-EK8B, EK12DC ...•..••
ADC-EK10B, EK12B,
EK12DR ...............•.
ADC·EK12DM ........•.....

1-196

±SV dc
±3.SV dc to ± 7V dc
±S.O mA
± 2.S mA maximum
± 3.S mA maximum

1. The ADC-EK series are CMOS devices and must be properly handled to prevent damage from static piCk-up. Proper
anti-static handling procedures should be observed including storage in conductive form or shorting all pins together
with aluminum foil. Do not connect in circuits under "power
on" conditions. The input voltage should be applied after
power is on. Do not open circuits the zero adjust, reference,
or start convert pins while power is on. It should also be
noted that the top and bottom of the ceramic package are
connected to the positive supply.
2. Nominal values of input, reference, and offset resistors are
given in the resistor table. Due to the possible ± 5%
tolerance of the external reference and + 5% - 3% tolerance on the converter scale factor, the actual resistor value
can vary by almost ± 10% RG and RT in the diagrams are
for trimming gain and bipolar offset during calibration. It is
recommended that RG be 1% of RIN (nominal) and RT be
1% of ROFF (nominal). They should both be 100 ppm/DC
cermet trimming pots. The recommended procedure for
selecting RIN and ROFF is to set the RG and RT to center of
range and then choose 1 % metal film resistor which gives
the nearest fit at the full scale point 1111 ... 111 for RIN and
one that gives the nearest fit to zero scale point
1000 ... 000 for RT.
3. To choose any intermediate scale values for RIN and RT or
values of RREF for other reference voltages, use the following formulas:
R (
. I)
FSR FSR is the full scale range or total
IN nomma = 10 pA input voltage span for the
converter.
ROFF (nominal) = VREF
5pA

RREF (nominal) = VREF
20 p.A

It is recommended that large full-scale voltage ranges be
chosen such as 0 to + 10V, 0 to + 5V etc., in order to keep
the error due to input offset voltage drift to a minimum.
4. The temperature stability of the ADC·EK converters
depends directly on the converter itself, RIN , RREF, ROFF ,
and VREF . Since the converter is typically ± 20 ppm/DC it is
recommended that a 10 ppm/DC reference be used along
with 10 ppm/DC metal film resistors for RIN, RREF, and ROFF
for best performance over temperature. On a statistical
basis this would give about 28 ppm/DC stability for the
complete converter.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·11941TEL (508) 339·30001TLX 174388/FAX (508) 339·6356

ADC-EK SERIES
TECHNICAL NOTES (Cont'd)
5. Other passive components used with
the converter may have tolerances as
indicated here: Rc is a ± 10% carbon
composition resistor; Cc is a ± 20%
ceramic capacitor; C1NT is a ± 10%
glass or ceramic capacitor; RS1AS is a
± 10% carbon composition resistor;
and the two zero adjust resistors are
± 10% carbon composition type. It is
recommended that two 0.1 I'F bypass
capacitors be used right at the power
supply pins. C1NT should be connected as close as possible to pins 14
and 15 away from any noisy lines.
6. The start convert pulse initiates conversion on the low to high transition
after which the conversion cycle
cannot be interrupted and must run to
completion.
7. Logic signals should not be routed
under these devices or near the input
reference, or zero adjust pins.
8. The unused data output pins on the 8and 10-bit models should not be used
for external connection pOints since
they have internal connections to the
converter.
9. All digital outputs will drive 2 low
power TTL loads or 1 low power
Schottky TTL load. They should not
be overloaded as this will affect the
performance of the converter.
10. Conversion accuracy is directly dependent on VREF . In order to avoid
degrading accuracy, VREF voltage
regulation must be ± 0.04% for 8 bit
models, ±0.01 % for 10-bit models
and ± 0.0025% for 12-bit models.

CLOCKED OPERATION

DATA
OUT

H
-------D-A-TA-F-Ao-M-LA-sT""76?~7EAStON LATCHED
LO-----------

~ ~~~c~~t;'

DATA

CHANGIN~--::- 500 n,.,
II

FREE RUNNING OPERATION

START

HI - - - - - - - - - - - - ,

CONVERT

LO- - - - - - BUSY

HI

LJ

_________ .S ~ _____________________ _
'
~ECYCLE
I

- - - - - - - - - CONVERSION TIME - - - - ..- - - .., - -

LO

I

TIME

2.5 J.(sec.

I

HI----------~

DATA
VALID
DATA
OUT

~(

LO
HI _ _ _ _ _ _ _ _ _ _- - ,

D_A_~_F_AO_M_LA_ST_CO~N~ER~SI_ON_L_A_TC_H_ED_ __J~~~"'N~J~~~C~~~~t--

W ______

DATA CHANGING
START CONVERT (PIN 21) IS TIED TO + 5V de (PIN 19)

CONNECTION FOR UNIPOLAR OPERATION

- i ~ 500 nsec
II

RESISTOR TABLES

A1N • AREF ARE 1% METAL FILM RESISTORS.
+5Vdc

AetAS- Rc ARE 10% CARBON COMP RESISTORS

-5Vdc

Cc is 20% CERAMIC CAPACITOR
ZERO ADJUSTMENT RESISTORS ARE 10% CAR-

BON COMPo
ALL TRIMMING POTS ARE 100 ppm/OC CERMET
TYPE

SUPPLY BYPASS CAPACITORS ARE CERAMIC
OR TANTALUM
C'NT IS 10% GLASS OR CERAMIC CAPACITATOR

ANAlOG
INPUT

UNIPOLAR
RANGE
o TO +2V

BIPOLAR
RANGE
±1V

RIN
(NOMINAL)
200K

OTO +5V

±2.5V

500K

o TO
o TO

+10V

±5V

1 MEG.

+20V

+10V

2 MEG.

o-......W,rv'MM--<~{)jl~'1

RREF
(NOMINAL)

ROFF
(NOMINAL)

-1.22V

61K

244K

-2.5V

125K

500K

-6.4V

320K

1.28 MEG.

VREF
-5V
START
CONVERT

~
'33 pF FOR ADC·EK88

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

1.197

ADC-EK SERIES
CALIBRATION PROCEDURE

CONNECTIONS
CONNECTION OF BIPOLAR OPERATION
(BINARY MODELS ONLY)
.5V d,

1.
-5V"

.5V

2.

~~.rN ADJ

5pA_
F.S.

RSET
6.2
MEG

C,
270pF

-5V

J
3.

R 1N . RREF' AOFF AND THE TWO 20K RESISTORS ARE 1%

METAL FILM TYPES.
ALL OTHER RESISTORS ARE 10% CARBON COMP, TYPE
Cc IS 20% CERAMIC CAPACITOR.
GINT IS 10% GLASS OR CERAMIC CAPACITOR

ALL TRIMMING POTS ARE 100 ppmfOC CERMET TYPE
SUPPLY BYPASS CAPACITORS ARE CERAMIC OR TANTALUM.

'33 pF FOR ADC-EKBB

Connect the converter as shown in
the connection diagrams for either
unipolar or bipolar operation. Determine the input voltage range and
select the required input resistors.
Apply a logic high to the start convert
input (pin 21) to give free-running
operation.
Zero and Offset Adjustments. Apply
a precision voltage reference source
from the analog input resistor to
ground. Adjust the reference source
to zero + % LSB for unipolar operation or - FS + % LSB for bipolar
operation. Adjust the zero or offset
potentiometer so that the output code
flickers between 000 .... 000 and
000 .... 001.
Gain Adjustment. Set the output of
the reference source to + FS - 1%
LSB and adjust the gain trimming
potentiometer so that the output code
just flickers between 111 .... 110 and
111 .... 111.
For BCD coding the output code
should flicker between 1001 1001
1000 and 1001 1001 1001.

REFERENCE CIRCUITS
6AY ZENER REFERENCE
REQUIRES -15V SUPPLY

1.22V BAND GAP REFERENCE
USES EXISTING - 5V SUPPLY

REDUCTION OF STAND-BY POWER

_-'\A.I\"~---<

-6AV

B.2K

-5V

THIS REDUCES POWER CONSUMPTION TO
ABOUT 200 ~ DURING STANDBY.

-15V

CODING TABLES
STRAIGHT BINARY
10-BIT

8·BIT

12-BIT

SCALE

OTO +10Y

CODe

OTO +10V

CODe

FS-l Lse

+9.96V
+5.00
+0.04
0.00

11111111

+9.990V
+5.000
+0.010
0.000

1111111111

V2 FS
1 lS8

a

10000000
0000 0001
0000 0000

10 0000 0000
00 0000 0001
00 0000 0000

o TO

coDe

+10V

+ 9.9976V
+ 5.0000

111111111111
1000 0000 0000
0000 0000 0001
0000 0000 0000

+ 0.0024
0.0000

OFFSET BINARY
a·BIT

10-BIT

12-81T

SCALE

t'V

CODE

±5V

CODE

t5V

CODE

+FS-1LSB

+4.96V
0.00
-4.96
-5.00

11111111
1000 0000
0000 0001
0000 0000

+4.990V
0.000
-4.990
-5.000

1111111111
10 0000 0000
00 0000 0001
00 0000 0000

+4.9976V
0.0000
-4.9976
- 5.0000

111111111111
1000 0000 0000
0000 0000 0001
0000 0000 0000

-FS+1 LSB

-FS

BCD
FULL SCALE RANGE
SCALE

o TO +2V

OTO+l0V

o TO +20V

FS-l LSB
V2 FS

+ 1.999V
+ 1.000
+0.001
0.000

+ 9.995V
+ 5.000
+0.005
0.000

+ 19.990V
+ 10.000
+ 0.010
0.000

1 LSB

0

1-198

ORDERING INFORMATION
MODEL NO.
BINARY
ADC-EKSB
ADC-EK10B
ADC·EK12B

OPER. TEMP.
RANGE

PACKAGE

O°C to +70°C
-25°C to +S5°C
-25°C to +S5°C

Plastic
Cerdip
Ceramic

BCD
ADC-EK12DC
O°C to + 70°C
ADC-EK12DR
-25°C to +S5°C
ADC·EK12DM - 55°C to + 125°C

Plastic
Ceramic
Ceramic

CODE
1
1
o
o

1001
0000
0000
0000

1001
0000
0000
0000

1001
0000
0001
0000

THESE CONVERTERS ARE COVERED
UNDER GSA CONTRACT

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-ET Series
Monolithic AID Converters
with Three-State Outputs

FEATURES
•
•
•
•
•
•

Monolithic CMOS
Three-state outputs
12-Bit accuracy
No missing codes
Low cost
Microprocessor-compatible

START

DATA

CONVERSION

REFERENCE

BUSY VALID

GENERAL DESCRIPTION
I

The ADC-ET series devices are low cost
integrating A/D converters optimized for
high accuracy, linearity and noise immunity. They operate at low power consumption, with sufficient speed to handle most
industrial and instrumentation requirements. Discretely controllable three state
outputs allow bus organized output connections making these units ideal for
microprocessor interfacing.
Fabricated with monolithic CMOS techniques, each device is housed in a single
24 pin dual in-line package. The converter
consists of an integrating operational amplifier, comparator, current switch, internal
clock, two counters, latching output buffers and control logic circuitry. Operation
of the circuit requires only a few external
passive components and connection to
external reference and power supplies.
Conversion is accomplished by an incremental charge balancing technique which
assures high linearity and noise immunity,
along with inherent monotonicity resulting
in no missing codes. At the completion of a
conversion, the binary coded result appears in parallel form on discretely controlled latched outputs which are CMOS,
low power TIL, or low power Schottky TIL
compatible. The controllable outputs may
be switched to a high impedance or off
state by holding the ENABLE high.
Conversion times are 1.8, 6, and 24 milliseconds for the 8-, 10- and 12-bit units
respectively. Other typical specifications
include linearity to V4 LSB and a gain
tempco of 25 ppm/oC. The analog input
voltage range is programmable by means
of an external resistor which sets the current into the integrator at 10 "A full scale.
Standard operating mode is unipolar but
bipolar operation can be implemented by
using an external operational amplifier to
provide an offset current from the reference. Power requirement is ± 5V dc at 2
mA which, for intermittent duty applications, may be reduced to only 200 "A during standby periods without affecting data
in the output latches.

I

I
I
OUTPUT I
LATCHES!

I

CONTROL

I

lOGIC
AND
INTERNAL
CLOCK

:I DRIVERS
~~~~~

DATA
COUNTERS

I

MECHANICAL DIMENSIONS
INCHES (MM)
CERAMIC

PLASTIC

PACKAGE

PACKAGE

0.555
(t4,l)

'-(IT,~",,",onn:rtrotr ..l
12;)0450.155
{l,t} (3,9)

PINt
tDENT

O~IIL
0100-1
fB136
l

(t ,3)

-

(2,5)

~O~~)1

1_

0085

(3,5)

(2.2)

INPUT/OUTPUT CONNECTIONS
CERDIP

PIN
1
2
3

•

--========1
t-

I

0.210

0.023
(5.8)

5
6
7
8
9
10
11
12

FUNCTION
BIT 1 (MSB-12 BITS)
BIT 2
BIT 3 (MSB·10 BITS)
BIT 4
BIT 5 (MSB·8 BITS)
BIT6
BIT7
BIT8
BIT 9
BIT10
BIT 11
BIT 12 (LSB-ALL)

PIN

FUNCTION

13
1.
1.
16
17
18
19
20
21
22
23
2.

REFERENCE
ANALOG INPUT
AMPLIFIER OUT
ZERO ADJUST
BIAS
-5V POWER
+5V POWER
GROUND
START CONVERT
BUSY OUTPUT
DATA VALID
ENABLE

NOTE: Do not connect unused data output pins on 8- and 10-bIt
models, they are internally connected to the converter.

DATEL. Inc. 11 Cabot Boulevard. Mansfield. MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

1-199

ADC-ET SERIES
ABSOLUTE MAXIMUM RATINGS
hN ..
IREF ...... .
Digital Input Voltage.
Voo-Vss.
Package Dissipation.

'" ±10 mA
.... ±10 mA
. -0.3V to VDD +0.3V
" .18V
....... 500 mW

FUNCTIONAL SPECIFICATIONS
Typical at 25 ·C, 5V Supplies, RBIAS lOOK, unless otherwise noted.
ANALOG INPUTS

PHYSICAL/ENVIRONMENTAL
Operating Temperature Range
CSuffix .................. O°Cto +70°C
RSuffix .................. -25°Cto +85°C
M Suffix .................. - 55°C to + 125°C
Package
C Suffix .................. 24 Pin Plastic DIP
R & M Suffix ............... 24 Pin Ceramic DIP
FOOTNOTES:
1. Nonlinearily for model ADC-ET12BC only is typically ± V. LSB, ± 11'2 LSB
maximum.

2. For M suffix unils only gain tempco is Iypically 40 ppm/DC, 80 ppm/DC max·
imum and zero drift tempeo is ± 80 ItV/oC.
3. VOD ± 1V, Vss ± 1V.
4. M suffix logic outputs can sink and source 500 p,A.

Type Analog Input
......... Single-Ended
Input Current Range. .. , .. .. . .Oto +10~
Reference Current ...... . .. .. -20~
DIGITAL INPUTS

TECHNICAL NOTES

Logical "1" V,N .. .. . ......... 3.5V minimum
Logical "0" Y'N ......... . . . . . 1.5V maximum
Start Convert Pulse Width ... .. 500 nanoseconds minimum
ENABLE Propagation Delay. · .. 500 nanoseconds

1. The ADC-ET series are CMOS devices and must be prop-

OUTPUTS
Output Off State Current
· .. 0.1 ~ typical, ± 10 ~A maximum
Logic "1" Output Voltage .. · .. +4.5V minimum at -10 ~A
+2.4V minimum at -360 ~A4
Logic "0" Output Voltage ..... + O.4V maximum at 360 ~A4
Data Valid Output ............ High for Data Valid, Low When
Loading
Busy Output ................ High During Conversion
PERFORMANCE
Resolution .................. 8,10,12 Bits
Coding, Unipolar ............ Straight Binary
Bipolar ............. Offset Binary
Conversion Times
8 Bits ................... 1.8 milliseconds maximum
10 Bits ................... 6 milliseconds maximum
12 Bits ................... 24 milliseconds maximum
Nonlinearity ................ ± '/4 LSB typical,
± V. LSB maximum'
Differential Nonlinearity ....... ± % LSB typical,
± V. LSB maximum
Diff. Nonlinearity Tempco ..... ± 2.5 8pm/oc
No Missing Codes ............ Over perating Temp. Range
Initial Gain Error, (Adj. to Zero) . ± 5% maximum
Gain Temperature Coefficient .. ± 25 ppm/DC typical, ± 75 ppm/DC
maximum 2
Initial Zero Error (Adj. to Zero) .. ± 50 mV maximum
Zero Drift Tempco ........... ± 50 ~V/oC maximum'
Power Supply Sensitivity ...... ± 0.05%/% maximum 3
POWER REQUIREMENTS
Voltage, Rated Performance ... ± 5V dc
Voltage Range, Operating ..... ± 3.5V dc to ± 7V dc
Supply Quiescent Current
CSuffix .................. 5.0 mA maximum
RSuffix .................. 2.5 mA maximum
M Suffix .................. 3.5 mA maximum

erly handled to prevent damage due to static discharge.
Proper anti-static precautions should be taken, including
storage and transport in anti-static containers or conductive
foam, and grounding of work stations, handling equipment
and personnel. Do not connect in circuits under "power
on" conditions. The input voltage should be applied after
power is on. Do not open the circuitry for the zero adjust,
reference or start convert pins while the power is on. It
should be noted that the top and bottom of the ceramic
package are connected to the positive supply.

2. Nominal values of input, reference and offset resistors are
given in the resistor table. Due to the possible ± 5% tolerance of the external reference and the + 5%, - 3% tolerance of the converter scale factor, the actual resistor value
can vary by almost ± 10%. RG and RT in the diagrams are
for trimming gain and bipolar offset during calibration. It is
recommended that RG be 1% of R'N (nominal) and that RT
be 1 % of ROFF (nominal). They should both be 100 ppm/DC
cermet trimming pots. The recommended procedure for
selecting R'N and ROFF is set to RG and RT to the center of
their ranges and choose a 1 % metal film resistor which
gives the closest fit at the full scale point 1111 .... 111 for
R'N and one that gives the closest fit to the zero scale point
0000 ... 000 for RT.

3. The temperature stability of the ADC-ET converters
depends directly on the converter itself, R'N, RREF, ROFF
and VREF' Since the converter is typically ± 25 ppm/DC. It is
recommended that a 10 ppm/DC reference be used along
with 10 ppm/DC metal film resistors for R,N , RREF and ROFF
for best performance over temperature.

4. Passive components used with the converter may have
tolerances as indicated here: Cc is a ± 20% ceramic
capacitor; C 'NT is a ± 10% glass or ceramic capacitor; Rc1 ,
RBIAS and the two zero adjust resistors are ± 10% carbon
composition type.

5. It is recommended that two 0.1 I'F bypass capacitors be
used at the power supply pins as shown in the connection
diagram. C 'NT should be connected as close as possible to
pins 14 and 15 and as far as possible from any noisy lines.

6. Logic signals should not be routed under these devices or
near the input, reference or zero adjust pins.

7. All digital outputs will drive two low power TTL loads or one
low power Schottky TTL load. The outputs should not be
overloaded as this will affect the performance of the
converter.

1-200

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388fFAX (508) 339-6356

ADC-ET SERIES
TECHNICAL NOTES (Cont'd)
8. It should be noted that there is a propagation delay of approximately 500 nanoseconds between the time ENABLE
changes state and the time that the outputs change state.
9. Two's complement coding can be implemented by inverting
the MSB signal.
10. liN and IREF' pins 14 and 13 respectively, connect to the
summing junction of an operational amplifier which requires
a current input. Voltage sources cannot be attached directly to them, but must be buffered by external resistors.
Refer to Test Circuit Diagrams. Analog input can be any
positive voltage when applied through the proper scaling
resistor.
11. Conversion accuracy is directly dependent on VREF . In
order to avoid degrading accuracy, VREF voltage regulation
must be ± 0.04% for 8-bit models, ± 0.01 % for 10-bit
models and ± 0.0025% for 12-bit models.

TIMING DIAGRAMS
CLOCKED OPERATION

NEW DATA
LATCHED

DATA

00'
DATA CHANGING

FREE RUNNING OPERATION

C8~~~~T :~ __________________S~ ___________ _

"' L.F=

/

J
-~~-CONVERSION
TIME~~-----

LO

I

~ECYCLE
TIME

I

2,S"sec

START CONVERT (PIN 2111S TIED TO +5V de (PIN 19)

DESCRIPTION OF OPERATION
When the START CONVERT input is strobed with a positive
pulse of at least 500 nanoseconds duration, the busy line
latches high and a start up cycle of approximately 10
microseconds begins, during which the integrating capacitor is
discharged and both counters are reset. Conversion begins at
the end of an internal reset pulse.
During conversion, the sum of a continuous current, liN and
pulses of an inversely signed reference current IREF' is integrated. liN is proportional to the analog input voltage and IREF is
proportional to the reference voltage. A pulse of IREF is applied
as required to maintain the summing input of the integrating
operational amplifier near zero. The total number of pulses of
'REF required to maintain the summing input near zero is
counted and the binary coded result is latched into the outputs
at the end of conversion.
The end of conversion is signaled by a pulse generated by the
clock counter or by the data counter when an overflow condition
occurs; this pulse disables further inputs into both counters and
begins a 10 microseconds shutdown cycle. During the shutdown
cycle, Data Valid goes low for 5 microseconds, while the result
of the latest conversion is being transferred to the outputs. Until
transfer is complete, the data at the outputs is not valid. At the
end of the shutdown cycle, Data Valid goes high indicating that
the outputs are latched with the result of the last conversion,
and the Busy Output goes low indicating the completion of the
conversion cycle and the availability of the converter for the next
conversion.
When the converter is employed in a free-running mode, the
START CONVERT input is held high (simply connect pin 21 to
pin 19), the Busy Output will go low for aproximately 2.5
microseconds to mark the completion and initiation of consecutive conversion cycles. It should be noted that once conversion is initiated, the cycle cannot be interrupted; the START
CONVERT pin is disabled when the Busy Output is high, and
thus its logiC state has no effect until completion of the conversion cycle. After the completion of a conversion, the output data
remains valid for as long as power is applied to the circuit, or until Data Valid goes low at the end of a conversion.

CODING TABLES
STRAIGHT BINARY
8 BIT

10BIT

12 BIT

SCALE

OTO+l0V

CODE

OTO +10V

CODE

FS-l LSB
'/2 FS
lLSB
0

+9.96V
+5.00

11111111
10000000
00000001
0000 0000

+9.990V
+5.000
+0.010
0.000

1111111111
100000 0000
0000000001
000000 0000

+0,04
0.00

o TO

+10V

+ 9.9976V
+ 5.0000
+ 0.0024
0.0000

CODE
111111111111
1000 0000 0000
00000000 0001
0000 0000 0000

OFFSET BINARY
881T

10 BIT

12 BIT

SCALE

±5V

CODE

±5V

CODE

±5V

CODE

+FS·l LSB
0
-FS+1LSB

+4.96V
0.00
-4.96
-5.00

11111111
1000 0000
0000 0001
00000000

+4_990V
0.000
-4.990
-5.000

1111111111
100000 0000
0000000001
00 0000 0000

+4.9976V
0_0000
-4.9976
-5.0000

111111111111
1000 0000 0000
0000 0000 0001
0000 0000 DODO

-FS

RESISTOR TABLES
UNIPOLAR
RANGE
o TO +2V
o TO +5V
o TO + 10V
o TO +20V

VREF
-1.22V
-2.5V
-6.4V

BIPOLAR
RANGE
±1V
±2.5V
±5V
+10V

RIN
(NOMINAL)
200K
500K
1 MEG
2 MEG

RREF
(NOMINAL)

ROFF
(NOMINAL)

61K
125K
320K

244K
500K
1.28 MEG.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-201

•

ADC-ET SERIES
CONNECTIONS AND CALIBRATION
CONNECTION FOR BIPOLAR OPERATION

CONNECTION FOR UNIPOLAR OPERATION
R1N' RREF ARE 1% METAL FILM RESISTORS.
RaIAS - Ac ARE 10% CARBON COMP RESISTORS.
Cc is 20% CERAMIC CAPACITOR.
ZERO ADJUSTMENT AESISTORS ARE 10% CARBONCQMP.
ALL TRIMMING POTS ARE 100

ppm~

+5Vdc -5Vdc

CERMET

TYPE.
SUPPLY BYPASS CAPACITORS ARE CERAMIC
OR TANTALUM.
G'NT IS 10% GLASS OR CERAMIC CAPACITATOR.

RSIAS

'OOK

ArN • AAEF ARE 1% METAL FILM RESISTORS.
ReiAs , Rc ARE 10% CARBON COMP RESISTORS.
Cc is 20% CERAMIC CAPACITOR
ZERO ADJUSTMENT RESISTORS ARE 10% CAR·
BONCOMP.
All TRIMMING POTS ARE 100 ppmfOC CERMET
TYPE.
SUPPLY BYPASS CAPACITORS ARE CERAMIC
OR TANTALUM.
C'NT IS 10% GlASS OR CERAMIC CAPACITATOR

+SVdc

-SVdc

+5V

j

r

C,
270pF

-5V

36~~~RT o---------.C-(; , , r - - - - - - - - - - - '

·33 pF FOR AOc.ET6BC

'33 pF FOR ADC-ET68C

REDUCTION· OF STAND-BY POWER

REFERENCE CIRCUITS
f.22V

BAND GAP REFERENCE
USES EXISTING - 5V SUPPLY

6.4V ZENER REFERENCE
REQUIRES - t5V SUPPLY

THIS REDUCES POWER CONSUMPTION TO
ABOUT 200 ~ DURING STANDBY.

-5V

-lSV

LOW COST MICROPROCESSOR AID, D/A INTERFACE

I
I

ANALOG 0 UTPUT

CALIBRATION PROCEDURE
1. Connect the converter as shown in the connection diagrams
for either unipolar or bipolar operation. Determine the input
voltage range and select the required input resistors. Apply a
logic high to the start convert input (pin 21) to give freerunning operation.
2. Zero and Offset Adjustments. Apply a precision voltage
reference source from the analog input resistor to ground.
Adjust the reference source to zero + 1f2 LSB for unipolar
operation or - FS + 1f2 LSB for bipolar operation. Adjust the
zero or offset potentiometer so that the output code flickers
between 000 .... 000 and 000 .... 001.
3. Gain Adjustment. Set the output of the reference source to
+ FS -11f2 LSB and adjust the gain trimming potentiometer
so that the output code just flickers between 111 .... 110
and 111 .... 111.

1-202

ANALO G
INPUTS

l'":'"IfI

CH'
CH'

:=
:=
~
:=

~

SAMPLE HOLD

-

8-BIT DIA CONVERTER
DAe UP8B

LOAD

8·CHANNE
MUX L
Mva08

c---

SHM

'C 1

-

8-BITNO
CONVERTER

ADC

ETas

-r-

.-

-

~

DATA

YO sus

f--

DATA VALID

OUTPUT ENABLE

INITIATE. CONVERSION

SAMPLE CONTROL
CHANNEL ADDflESS CONTROL

a·BIT
MICROPROCESSOR

MUX INHIBIT CONTROL

DATEL. Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

ADC-ETSERIES
TYPICAL PERFORMANCE CURVES
CONVERSION TIME
VS. TEMPERATURE

CONVERSION TIME

VS. RalAs
1.4

10

r=
r--

,

TA '" 2S"C
Voo - 5V
Vss = -5V

-

~~

,

,

\

1.5

1

~
0.9

I

1..

Voo = 5V
Vss = -5V

-

1. 2

V

1

,

CONVERSION TIME

vs. SUPPLY VOLTAGE

..-'

\

1.4

1.3

r---

\

1.2

\.

1

"\

1.0
0.9

V-'

I
TA = 25"C

l".......

o. e
o. 7

I'..

0 .•

./

o. e

o. 5
0.4

0.7

o. 1

lOOK

10K

-55

1M

25

-25

50

75

100

125

VDD :;: Vss (VOLTS)

TEMPERATURE (OC)

RalAS (OHMS)

SUPPLY CURRENT
VS. RRIAS

SUPPLY CURRENT
VS. SUPPLY VOLTAGE
10

I

-

I
TA = 25"C

/

/

/'

~

e-

/

f--

-

./
./

~

""'" ~
TA
25"C
Veo
5V
5V
V55

1 I I II

I

0.1
10K

7

lOOK
R01AS (OHMS)

V DO '" Vss (VOLTS)

OUTPUl' SOURCE CURRENT

OUTPUT SOURCE CURRENT

VS. TEMPERATURE

VS. SUPPLY VOLTAGE

SUPPLY CURRENT

VS. TEMPERATURE

Voo = 7V

I

2.2

111111

5.0
Voo '" 5V
V
-5V

::::::-....-we

ss '"

2. 0

1.

......

'""'-

........

...........

•

4.5

,III

5

r- r--

3.0

-

I111
Voo = 5V
Vss

=

-5V

5-llllll1

2.

- - r--

1.4

-55

-25

o.

25

50

75

100

125

-

25.e~ ~"

t----

'"I'

2.0

0.1

1
10

'OH(mA)

~~
V55 • -5V

1\\

125"C

0.1

Vss '" _7''/

Voo

=

............

3.5V-..............

......
.....\

Vss = -3.SV

"

\

1

10

IOH(mA)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1·203

ADC-ET SERIES
TYPICAL PERFORMANCE CURVES

OUTPUT SINK CURRENT
VS. TEMPERATURE

I

VOD '" 5V

VSS
1.25

OUTPUT SINK CURRENT
VS. SUPPLY VOLTAGE
1.5

1.5

f--_.

=

-5V

I IIII

Voo = 5V

1.25

25"C

i

...I

~

1.0

1.0

~

I \Doe

i

/ I-we

0.75

IV

0.5

0.25

__ LUi II
Vss'" -5V

r--

Voo = 3.SV

0.75

l'

r-

Vss '"

1/

V./
~

o. 1
10

J

II

0.25

0.1

II

J

-3.SV

0.5

~

~ ..... ~

I

I "III

'I

~""

Voo = 7V

io"'"

.Vss

='

0.1

10

'OL(mA)

'OLemA)

LINEARITY VS. 'REF

THREE·STATE PROPAGATION DELAY
1.3

3.0

ICINT

I

33pF

68pF·

2.0

150pF

1.0
0.5

300pF

'i--,

1

~il!

68pF

150pF

-2

I

1.0

./
,/'

f

:A1'
r-

1.1

0

/CINT

'(

0

!il

,

o.g
0.8

/'

/

1.2

'"
~

!;i

'(

~

-0.5
1

~
z

1 I
7 rJII

33pF

-

-7V

./

~

t/
V DO '" 5V

V"

¥ss

=

-5V

0.7

300 pF

I I

0.0

I II

3

10

20

-55
50

100

200

SOD

-25

25

50

75

100

125

TEMPERATURE (GC)

ORDERING INFORMATION
MODEL

1-204

OPERATING
TEMP. RANGE

PACKAGE

ADC-ETSBC
ADC-ETSBM

DoC to + 70°C
-55°C to + 125°C

Plastic
Cerdip

ADC-ET10BC
ADC-ET10BM

DoC to + 70°C
-55°C to +125°C

Plastic
Cerdip

ADC-ET12BC
ADC-ET12BR
ADC-ET12BM

DoC to + 70°C
-25°C to +S5°C
-55°C to +125°C

Plastic
Ceramic
Ceramic

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADC-HC12B
12-Bit, Low-Power
AID Converter

FEATURES
•
•
•
•
•

Single supply operation
Automatic standby mode control
Low power consumption
Six input ranges
MIL temperature ranges available

GENERAL DESCRIPTION
The ADC-HC is a complete, 12-bit, lowpower, analog-to-digital converter utilizing
CMOS technology. This hybrid IC incorporates active laser trimming of highly
stable thin-film resistors to provide module
performance with IC price, size and
reliability.
The device is ideal for portable and remote
as
seismology,
applications
such
oceanography, meteorology, and pollution
monitoring. Other key applications include
military and aerospace, requiring wide
operating temperature ranges and high
reliability.

DIGITAL

GAIN
ADJ

Voo COM Vss

ZERO
TRIM

WIPER

ZERO
TRIM

POWER
MODE

REF.

our@)----====-{

20V
INPUT

10V
INPUT

SUM
JUNe
ANALOG
COM

14

SERIAL

16

E.O.C.

21

START

our

CONVERT

BiT1 BIT 1 2

CLOCK

\(iTse)

OUT

3

4

(MSB)

5

6
7
BIT NO.

B

I

PARALLEL DATA OUT

The ADC-HC converter can operate from
either a single + 9V dc to + 15V dc power
source (interrupt power mode) or from a
± 9V dc to ± 15V dc power source (continuous power mode) at a maximum conversion rate of 3.3 kHz.
A key feature of this unit when operating in
the interrupt power mode is the extremely
low quiescent power consumption (less
than 10 p.A at 12V, 25°C).
Upon receipt of a convert command, the
analog circuitry of the converter is energized and stabilizes in 50 microseconds. A
complete conversion is performed at
which time the EOC goes low, turning 011
the analog circuitry, and returns to its
~uiescent state. The digital data remains
talid until it is updated by the next
:onversion.
'ower consumption is a function of con'ersion rate. For 100, 1K and 2K conver:ions per second, the average power drain
>approximately 3.5, 26 and 50 milliwatts
espectively.
jix input voltage ranges are provided by
xternal pin connection: 0 to + 5V, 0 to
f10V, 0 to +20V, ±2.5V, ±5V, and
: 10V dc. Nonlinearity is specified at ± %
S8 maximum with a gain tempco of ± 30
pm/oC. Output coding is straight binary,
ffset binary or 2's complement. Serial
ata is also brought out.
he converters are cased in 32-pin DIP
ackages. Models are available for two
illerent operating temperature ranges: 0

INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (MM)
1 101 MAX

(28,0)

I

~0~~0;~gi~~
17

16

P'"

0190 MAX

~I p i
~

TI
15

BOTTOM
VIEW

(3,8)

SPACES
AT 0, 100

1712 MAX
(43,5)

,---------,32

1-

~;~~)

-hL

FUNCTION

17

POWER MODE

BIT 1 (MSB)

18

V DD
VSS
REF aUT

elT2

19

4

BIT 3

20

5
6

BIT 4

2t

START CONVERT

BIT 5

22

DITITAL COM

7

BIT6

23

ANALOG COM

8

BIT 7

24

BIPOLAR OFFSET

SUM. JUNe

9

BIT 8

25

10

BIT9

26

10V INPUT

"

BIT 10

27

20V INPUT

BIT "
BIT 12 (lSB)

28

GAIN ADJ

13
14

SERIAL OUT

30

ZERO ADJ (WIPER)

15

CLOCK OUT

31

ZERO TRIM

16

E.O,C. (STATUS)

32

N.C

12

(2,5)

P'"

Sir 1 (MSB)

3

0.150 MIN

FUNCTION

1
2

29

ZERO TRIM

-I

NOTE: PINS HAVE 0.025 INCH STANDOFF FAOM CASE,

± 0.01

to +70°C, and -55 to +125°C. High reliability versions of each temperature range
are also available.
CAUTION: The ADC-HC Series are CMOS
devices and should be handled carefully to
prevent static charge pickup which might
damage the devices. The devices should
be kept in the shipping containers until
ready for installation.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1·205

ADC-HC12B
CONNECTIONS AND CALIBRATION
ADC·HC TIMING DIAGRAM
Voo

_____ 50 JISEIC MIN FOR INTERRUPT MODE
_

START CONVERT

5pSeC MIN FOR CONTINUOUS MODE

~~ -If- -11-

2

_+ _-1
2

~23""

VOO
CLOCK OUT

----, 1_ 0.15 JISEIC MAX

Voo---,

[
I

__11_

:"J

0.5 JISEIC MAX

LE.O.C
CONNECTIONS DIAGRAM

E.O.C.
CLOCK OUT

E.Q,C

CLOCK OUT

SERIAL OUT

ILs

B

,.

23

AOC-HC

9

24
25

-------: UNIPQLARCONNECTIQN, 23 TO 24
.' BIPOLAR CONNECTION, 24 TO 25

27

UNIPOLAR

ZERO

+9.9976
+5.0000
+0.0024
0.0000

+ 10.0000
+0.0049
0.0000

STRAIGHT BINARY

o to

+5V

MSB

+4,9988
+2.5000
+0.0012

1111
1000
0000
0000

o.oaoo

BIPOLAR

+FS-l LSB
+1;2FS
+1 LSB
ZERO

-FS-l LSB
-FS

±10V

±5V

+9.9951
+5.0000
+0.0049
0.0000
-9.9951
-10.0000

+4.9976
+2.5000
+0.0024
0.0000
-4.9976
-5.0000

LSB

1111
0000
0000
0000

1111
0000
0001
0000

OFFSET BINARY·
±2.5V

~For 2's COMPLEMENT, MSB is inverted, use

MSB

+2.4988

1111

+ 1.2500

1100
1000
1000
0000
0000

+0.0012
0.0000
- 2.4988
- 2.5000

'MSi3 (pin

LSB

1111
0000
0000
0000
0000
0000

1111
0000
0001
0000
0001
0000

1)

INPUT PIN CONNECTIONS
INPUT VOLTAGE RANGE

INPUT PIN

CONNECT THESE
PINS TOGETHER

o to +5V

26

23 to 24, 25 to 27

Oto +10V

26

23 to 24

o to +20V

27

23 to 24

±2.5V

26

24 to 25, 25 to 27

+5V

26

24 to 25

±10V

27

24 to 25

1-206

,.

I -=I+

REFOUT
START

23
AOC-HC

31

MSB

32

-9VTO

J IlFT-+15VSUPPLY
l _

-15 SUPPLY

- - - - - - -: UNIPOLAR CONNECTION, 23 TO 24

24

MSB

0.1
I'F

, BIPOLAR CONNECTION, 24 TO 25
10V !?PUT

~

PI~OOK ~J

1.0M(I

GAIN ADJ.

10K ZERO ADJ.
NC

CALIBRATION PROCEDURE
COOING

+ 19.9951

22

MODE-DUAL SUPPLY OPERATION

OUTPUT CODING

+FS-l LSB
+%FS
+1 LSB

20
21

11

2.

NC

INPUT VOLTAGE RANGE
Oto+10V

12

29
30

10K ZERO ADJ

MODE-SINGLE SUPPLY OPERATION

Oto +20V

13

27 20V

31

32

CONTINUOUS MODE CONNECTION

'.~-+--------------~-'+
19 ~----~--, _
0,1=.. +9V TO

14

~

GAIN ADJ.

2.
29
30

17

15

9
DIGITAL
OUTPUT

3.9MO

26

,.

1. Connect the converter as shown in the Connection Diagram
Use the Input Pin Connections table for the desired inpu'
voltage range. Apply start conversion pulses to start pin.
2. Zero and Offset Adjustment
Apply a precision voltage reference source between th~
selected analog input range and ground. Adjust the output 0
the reference source to + % LSB. Adjust the zero trimminl
potentiometer so that the output code flickers equally be
tween 0000 0000 0000 and 0000 0000 0001 for unipolar an
1000 0000 0000 and 1000 0000 0001 for bipolar mode.
3. Full Scale Adjustment
Change the output of the precision reference source f(
+ FS -1 % LSB. Adjust the gain trimming potentiometer s
that the output code flickers equally between 1111 111
1110 and 1111 11111111.
4. For bipolar operation, the offset and Full Scale Adjustmel
are interactive. Repeat the offset and Full Scale Adjustmel
procedure as necessary until both pOints are set.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADC-HC12B
ABSOLUTE MAXIMUM RATINGS

PHYSICAUENVIRONMENTAL

Positive Supply (Voo)
Negative Supply (Vss) ..
Analog Inputs.
Digitallnputs .
. ...

Operating Temperature
Range.

+18V
-18V
±25V
0 to Voo

Storage Temperature Range
Package Type
.........
Pins
.
Weight .
. .......

O°C to + 70°C (BGC, BMC)
- 55°C to + 125°C (BMM)
- 65°C to + 150°C
Ceramic
0.010 x 0.018 inch Kovar
0.5 ounces (14 g.)

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ± 12V, unless otherwise noted.
INPUTS
Analog Input Ranges,
unipolar
Analog Input Ranges,
bipolar.
Input Impedance .

TECHNICAL NOTES
.0 to +5V, 0 to + 10V, 0 to +20V
±2.5V, ±5V, ±10V
... 5K (0 to + 5V, ± 2.5V)
10K(Oto +10V, ±5V)
20K(Oto +20V, ±10V)

Start Convert, Interrupt
Mode ...

Positive Pulse with duration of 50
microseconds minimum

Start Convert,
Continuous Mode.

· Positive Pulse with duration of 5
microseconds minimum
0.3 Voo maximum
0.7 Voo minimum
30 pA
15 pF

......
VldLogic "0") .
VIH (Logic "1 ")
·
Input Current ..
. .......
Input Capacitance .
OUTPUTS
Parallel Output Data
...
VodLogic "0") .
VOH (Logic "1 ") . .... .
·
All Digital Outputs . . . . . .
Coding, unipolar .........
......
Coding, bipolar
·
Serial Output ...
Clock Output . ...........
E.O.C. (Status) .. ........

12 parallel lines of data, held until next
conversion command
OV, -2.0 rnA
Voo, + 4.0 rnA
CMOS Compatible
Straight Binary
Offset Binary, 2's Complement
NRZ successive decision pulses out
MSB first, Straight Binary or Offset
Binary
Train of positive going (Voo)
25 microseconds pulses, 40 kHz
Conversion Status Signal, Logic "1"
during reset and conversion, Logic "0"
when conversion complete (data valid)

PERFORMANCE
. ..
Resolution .... ...
Nonlinearity .
Differential Nonlinearity
Gain Error . . . . . . . . . . . . . . .
Offset or Zero Error .......
Gain Tempco ..
Offset Tempco
Zero Tempco .....
Diff. Nonlinearity Tempco .
.....
No Missing Codes

12 Bits
± % LSB maximum
± % LSB maximum
Adjust to zero
Adjust to zero
± 30 ppm/oC maximum
± 20 ppm/oC of FSR maximum
± 10 ppm/oC of FSR
± 2 ppmloC of FSR
Guaranteed over operating temperature
range
Conversion Time .
. . . . 300 microseconds maximum
Throughput Time .. . . . . . . . 305 microseconds maximum continuous
power mode
350 microseconds maximum interrupt
power mode
Power Supply Rejection
· 003%1% Supply
POWER REQUIREMENTS
Continuous Power Mode

Voo .
. +9.0Vto +15.0V
-9.0V to -15.0V
Vss
nterrupt Power Mode Voo . +9Vto +15.0V
'ower Consumption,
Continuous Mode.
165 mW typical, 200 mW maximum
Quiescent Mode ..
150 ,"W maximum, 15 ,"W typical
"

1. The ADC-HC contains CMOS components and must be properly handled to prevent damage from static pick-up. Proper
anti-static handling procedures should be observed including
storage in conductive foam or shorting all pins together with
aluminum foil. Do not connect in circuit under "power on"
conditions. Digital signals should be applied after the converter's power has been turned on.
2. For single supply (+ 12V nominal) or dual supply (± 12V
nominal) operation, bypass the power input pins to ground
with a 0.1 I'F ceramic capacitor. It is not critical that the supplies be balanced.
3. Analog and digital grounds should be kept separate
whenever possible to prevent digital signals from flowing in
the analog ground circuit and inducing spurious analog signal
noise. Analog Common (Pin 23) and Digital Ground (Pin 22)
are not connected internally and must be tied together
externally .
4. The ADC-HC can operate from either a single or dual supply .
When using dual supplies, tie POWER MODE (Pin 17) to VDD
(Pin 18). In this continuous power mode, an AID conversion
will take place when a 5 microseconds or greater positive going pulse is applied to START CONVERT (Pin 21). For single
supply operation (interrupt power mode), tie Power Mode (Pin
17) to E.O.C. (Pin 16). When EOC goes low, the converter is
switched to standby mode (power is disconnected to analog
circuitry) and digital output data becomes valid and remains
valid until next start pulse is applied. Upon receipt of a 50
microseconds minimum, 500 microseconds maximum pulse
on START CONVERT (Pin 21), the converter will stabilize,
make a complete conversion and return to standby mode.
5. Digital output codes are listed in coding tables. Parallel data
is valid when EOC is in low state. This data can be transferred
into latches during a logic" 1" to logic "0" transition of the
EOC line. Serial data out (Pin 14) is in NRZ (non-return to
zero) format. This data is guaranteed valid in a 50
nanoseconds to 300 nanoseconds time frame after the
positive edge of the clock. All digital inputs and outputs are
CMOS compatible. See application notes for CMOS-TTL
interface .
6. REF OUT (Pin 20) is a 6.3V ± 5% internal reference pin
connection.
7. For zero or offset and gain adjustment, refer to connections
and calibration notes. The trim pots should be located as
close as possible to the converter to avoid noise pickup. Zero
point is always adjusted first, followed by gain, the adjustment with analog input at the most positive end of analog
range. The range of the OFFSET (ZERO) ADJ. is ± 15 mV.
The range of GAIN ADJ. is 0.1% of full scale range can also
be increased by decreasing the value of the series resistor
(3.9 Mf! nominal). Potentiometer values are 10K and should
be 100 ppm/oC ceramic type (such as DATEL's TP series).

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-207

ADC-HC12B
APPLICATIONS
ADC-HC INTERRUPT POWER MODE

ADC-HC CONTINUOUS POWER MODE

AVERAGE POWER
DISSIPATION (mW)

/

TYPICAL

TYPICAL @25°C

SUPPLY CURRENT
rnA@25°C

1000 mW

/

l00mW

~

lOmW

1 mW

0.1 mW

/

Vs '" +15V

~VS=> + 1 2 V -

~ Vs

=

- --100

10

-

+9V

~~

~~

~VS

---

-----

L

QUIESCENT DISSIPATION

@12V,25°C 120 j-TTL

LOGIC

LOGIC

HIGH
VOLTAGE

TTL

'ADe-He

CD4050

CMOS and TIL logic are not compatible due to different
threshold levels. They can, however, be interfaced by
simple techniques
The START CONVERT (Pin 21) can be driven directly
from an open collector, high voltage TTL gate. Resistor
Rx is used to source current and bring the TTL output up
to the CMOS threshold level. Typical values of Rx are
3.3K to 10K ohms.
CMOS to TTL interface requires sufficient sink current
in the low state. The C04049 (inverting) and C04050
(noninverting) buffers, powered from +5V logic supply
can accept input voltage swings of +5 to + 15V from the
CMOS system Each buffer gate can drive at least one input from any TTL family.

1-208

ORDERING INFORMATION
MODEL

TEMP. RANGE

SEAL

ADC-HC12BMC
ADC-HC12BMM

o to +70°C
-55°C to +125°C

Hermeti(
Hermeti(

ACCESSORIES
Part Number

TPK 10K
(10K ohms)

Description
Trimming Potentiometers

TP 100K
(100K ohms)
For military devices compliant with MIL-STD-883, contact DATE I

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

'

ADC·HS12B
12·Bit Microelectronic
AID Converter
With Sample·Hold
FEATURES
•
•
•
•
•
•

12-Bit resolution
Internal sample and hold
6 Microseconds acquisition time
9 Microseconds conversion time
Programmable input ranges
Parallel & serial outputs

GH

SAMPLE BIPOLAR REF
CONTROL OFFSET lOUT

+15Vdc

-15Vdc +SVdc

GENERAL DESCRIPTION
The ADC-HS12B is a high performance
12-bit hybrid AID converter with a selfcontained sample-hold. It is specifically
designed for systems applications where
the sample-hold is an integral part of the
conversion process. The internal samplehold has a 6 microseconds acquisition
time for a full 1OV dc input change; the AID
converter has a fast 9 microseconds conversion time. Five input voltage ranges are
programmable by external pin connection:
Oto +5V,Oto +10V, ±2.5V, ±5V,and
± 10V. Input impedance to the samplehold is 100 megohms. Output coding is
complementary binary for unipolar operation and complementary offset binary for
bipolar operation, with both parallel and
serial outputs brought out.

E.O.C.
(STATUS)

6

II:

12

§§ ~~!LSB

11

10

~8

9

8

7

6

5

BIrNO.

4

3

2

1

~

I

PARALLEL DATA OUT

The ADC-HS12B uses a fast 12-bit monolithic DAC which includes a precision
zener reference source. The circuit also
contains a fast monolithic comparator, a
monolithic 12-bit successive approximation register, a clock and a monolithic
sample-hold.
Other features include a gain tempco of
20 ppm/oC maximum and differential
nonlinearity tempco of ± 2 ppm/oC; there
are no missing codes over the operating
temperature range. The package is a
miniature 32 pin triple spaced DIP and different models are offered for each of the
operating temperature ranges: 0 to 70°C
and -55 to + 125°C. Power supply requirement is ±15V de and +5V de. High reliability versions are also available.

MECHANICAL DIMENSIONS
INCHES (MM)

INPUT/OUTPUT
CONNECTIONS

L - l . 1 0 1 MAX--l

I

I~

(28,0)

I

I

II

.

0.010

.

I

x 0.160 (4,1) KOVAR

17O=r1

• 16

15sLs

I

_." '" I.J

BOTTOM

~~:~~,_
PIN 1

0.190 (4,9) MAX

,,--.-

-.-~
---L- ~

0.150 MIN (3,8)

ATO,100EA

" ' -_ _ _ _ _- '

1712

---0--'--

"'N

FUNCTION

1

BIT 12 OUT (LSBJ

2

BIT 11 OUT

"'N

FUNCTION

17

CH

3

BIT 10 OUT

"

REF OUT

19

CLOCK OUT

4

BIT 9 OUT

20

E.O C (STATUS)

5

BIT 8 OUT

21

START CONVERT

ti

BIT 7 OUT

22

COMPAR INPUT

7

BIT 6 OUT

23

BIPOLAR OFFSET

6

BIT 5 OUT

24

tOV RANGE

9

BIT 4 OUT

25

20V RANGE

"

BIT 3 OUT

26

ANALOG COM

11

BIT 2 OUT

27

GAIN ADJ

12

BIT lOUT (MSB)

28

+ 15V POWER

13

SERIAL DATA OUT

29

S.H OUTPUT

14

SHORT CYCLE

30

15
16

DIGITAL COM

31

-15V POWER

+5V POWER

32

SAMPLE CONTROL

ANALOG IN

~O,900_.J_O,100

I

-

NOTE: PINS HAVE

(22,8)

O.02~

-I

(2,5)

INCH STANDOFF FROM CASE, ±Q,Ol"

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1·209

ADC·HS12B
ABSOLUTE MAXIMUM RATINGS
Positive Supply, pin 28 ........
Negative Supply, pin 31 ........
Logic Supply Voltage, pin 16 ....
Digital Input Voltage,
pins 14, 21, 32 . . . . . . . . . . . . ..
Analog Input Voltage, pin 30 . . ..

PHYSICAL/ENVIRONMENTAL

+ 18V
-18V
+ 5.5V

+ 5.5V
± 15V

Operating Temperature Range ..
Storage Temperature Range. . ..
Package Type ................
Pins ........................
Weight. .....................

FUNCTIONAL SPECIFICATIONS

FOOTNOTES:

Typical at 25°C, ± 15V and + 5V supplies unless otherwise noted.

1.
2.
3.
4.

INPUTS
Analog Input Ranges, unipolar ..
Analog Input Ranges, bipolar ...
Input Impedance' .............
Input Bias Current' ............
Start Conversion .............

0 to + 5V, 0 to + t OV
±2.5V, ±5V, ± tOY
tOO megohms
50 nA typical, 200 nA max.
2V min. to + 5.5V max. positive
pulse with 100 nsec. duration min.
Rise and fall times < 30 nsec.
Logic high to low transition resets
converter and initiates next
conversion.

Loading: 2 TIL loads
Sample Control Input .......... Logic high = hold
Logic low = sample
Loading: 1 TIL load
OUTPUTS'
Parallel Output Data. . . . . . . . . .. 12 parallel lines of data held until
next conversion command.
VouT("O"):s +O.4V
VOUT ("1");,: +2.4V
Coding, unipolar .............. Complementary Binary
Coding, bipolar ............... Complementary Offset Binary
Serial Output Data ............ Successive decision pulses out,
NRZ format. MSB first
End of Conversion (status) . . . . . Conversion status signal. Output is
logic high during reset and
conversion and low when
conversion is complete.
Clock Output ................ Train of positive going + 5V, 100
nsec. pulses at 1.5 MHz rate.
SAMPLE-HOLD PERFORMANCE'
Input Offset Drift ..............
Acquisition Time, 10V to 0.01 % .
Bandwidth ..................
Aperture Delay Time ..........
Aperture Uncertainty Time .....
·Sample to Hold Error ..........
Hold Mode Droop .............
Hold Mode Feedthrough .......

25 p.VloC
6 p.sec.
1 MHz
100 nsec.
10 nsec.
2.5 mV max.
200 nVIp.sec. max.
0.01% max.

CONVERTER PERFORMANCE
Resolution ..................
Nonlinearity .................
Differential Nonlinearity ........
Temp. Coefficient of Gain ......
Temp. Coefficient of Zero,
unipolar ...................
Temp. Coefficient 01 Offset,
bipolar ....................
Differential Nonlinearity
Tempco ...................
Missing Codes ...............
Conversion Time .............
Power Supply Rejection ........

12 bits (1 part in 4096)
±v, LSB max.
± 3/4 LSB max.
± 20 ppmloC max.

± 5 ppmloC of FSR max.
± 10 ppmloC of FSR max.
± 2 ppmloC of FSR
None over oper. temp. range
9 p.sec. max.
0.004%1% max.

POWER REQUIREMENTS
Power Suppy Voltage .......... + 15V dc ± 0.5V at 20 mA
-15V dc ± 0.5V at 25 mA
+ 5V dc ± 0.25V at 85 mA
± 12V dc, + 5V dc operation4

1-210

(BMC)
O°C to 70°C
-55°C to +125°C(BMM)
- 65°C to + 150°C
32 pin ceramic
0.010 x 0.Q18 inch Kovar
0.5 ounce (14 grams)

For sample-hold input
All digital outputs can drive 2 TIL loads
For 1000 pF external hold capacitor
For ± 12V de or + 5V de operation, contact the factory

TECHNICAL NOTES
1. It is recommended that the ± 15V power input pins both be
bypassed to ground with a 0.01 (.tF ceramic capaCitor in
parallel with a 1 (.tF electroly1ic capacitor and the + 5V power
input pin be bypassed to ground with a 1 (.tF electroly1ic
capacitor as shown in the connection diagrams. In addition,
pin 27 should be bypassed to ground with a 0.01 (.tF ceramic
capacitor. These precautions will assure noise free operation
of the converter.
2. Digital Common (pin 15) and Analog Common (pin 26) are
not connected together internally, and therefore must be
connected as directly as possible externally. It is recommended that a ground plane be run underneath the case between the two commons. Analog ground and ± 15V power
ground should be run to pin 26 whereas digital ground and
+ 5V dc ground should be run to pin 15 .
3. External adjustment of zero or offset and gain are provided
for by trimming potentiometers connected as shown in the
connection diagrams. The potentiometer values can be between 10k and lOOk ohms and should be 100 ppm/oC
cermet types (such as DATEL's TP series). The adjustment
range is ± 0.5% of FSR for zero or offset and ± 0.3% for
gain. The trimming pots should be located as close as possible to the converter to avoid noise pickup. Calibration of the
ADC-HS12B is performed with the sample-hOld connected
and operating dynamically. This results in adjusting out the
sample-hold errors along with the AID converter. For slow
throughput applications it is recommended that a 0.01 (.tF
hold capaCitor be used for best accuracy. With this value the
acquisition time becomes 25 microseconds and the externa
timing must be adjusted accordingly.

4. The recommended timing shown in the Timing Diagrarr
allows 6 microseconds for the sample-hold acquisition anc
then 1 microsecond after the sample-hold goes into the hoic
mode to allow for output settling before the AID begins iti
conversion cycle.
5. Short cycled operation results in shorter conversion time:
where the conversion can be truncated to less than 12 bits
This is done by connecting pin 14 to the output bit followinl
the last bit desired. For example, for an 8-bit conversion, pi
14 is connected to bit 9 output. Maximum conversion time
are given for short-cycled conversions in the Table.
6. Note that output coding is complementary coding. Fe
unipolar operation it is complementary binary and for bipolf
operation it is complementary offset binary. In cases wher
bipolar coding of offset binary is required, this can b
achieved by inverting the analog input to the converter (usin
an operational amplifier connected for gain of - 1 .0000).

n

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

ADC-HS12B
converter is then calibrated so that - FS analog input gives
an output code of 0000 0000 DODO, and + FS - 1 LSB gives
1111 1111 1111.
7. These converters dissipate 1.81 watts maximum of power.
The case to ambient thermal resistance is approximately
25°C per watt. For ambient temperatures above 50°C, care
should be taken not to restrict air circulation in the vicinity of
the converter.
8. These converters can be operated with an external clock. To
accomplish this, a negative pulse train is applied to START

CONVERT (Pin 21). The rate of the external clock must be
lower than the rate of the internal clock. The pulse width of
the external clock should be between 100 nanoseconds and
300 nanoseconds. Each N bit conversion cycle requires a
pulse train of N + 1 clock pulses for completion, e.g., an
8-bit conversion requires 9 clock pulses for completion. A
continuous pulse train may be used for consecutive conversions, resulting in an N bit conversion every N + 1 pulses, or
the E.O.C. output may be used to gate a continuous pulse
train for single conversions.

TIMING DIAGRAM FOR ADC·HS12B
T_R_'G_G_ER
____
-1l....J:___ 100 nsee. MIN

,
SAMPLE

CONTROL

_r---I

START

~_J

I~"--'-~-'------------------------------

C_O_N_VE_R_T_ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~: ~60nsec

'.J'"=============;,:;~~:-=-===========~
4
9psec_ MAX
NOW VALIDDATA
PARALLEL

I_ST_A_TU_S_I_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _",:
E.O.C.
II

- --...; : - 50 nsee
CLOCK
OUT

SERIAL

DATA OUT

BIT 1
OUT (MSB)

81T2
OUT

81T3
OUT

BIT 12

our (LSB)
NOTE: TRIGGER, SAMPLE CONTROL, AND START CONVERT
PULSES MUST BE EXTEANALl Y GENERATED

UNIPOLAR OPERATION, 0 TO + 10V
-15V + 15V

f,"F
=

"'qF

0.01

0.01

/IF

I'F
31

BIPOLAR OPERATION, ±5V
-15V + 15V

+5V

,,~
+15V

+15V

-=

-=

28
ANALOG IN
(+5V) 0

30
1.5 MEG
26

50K

ANALOG

OFFSET

29

24

23

+5V

2.8 MEG
27i---o--.-A/'<'V---i----0

1 .8750
1 2500

00000
- 1 2500

---------

C~O~M~P-.-----'--~~~~~-­

----,~

INPUT VOLTAGE RANGE

1.5MHz
1.8MHz
2.2MHz

4

5
6

BIPOLAR OPERATION, - 5V TO + 5V

12 BITS
20/lsec.
8 #-,sec.
17 & 15
14& 16

PIN 14 CONNECTION
PIN 14TO
RES.IBITS)
PIN 11
7
PIN 10
8
PIN 9
9
PIN 8
10
PIN 7
11
PIN 6
12

8 BITS
10#-,sec.
4 Ilsec.
17 & 28
14 & 4

PIN 14 TO
PIN 5
PIN 4
PIN 3
PIN 2
PIN 1
PIN 16

UNIPOLAR OPERATION, 0 TO + lOV

,"

ADC-HXI2B

,-------1----1--+.-- 15V GNO

1 "F CAPS

10BITS
15 #-,sec.
6 #-,sec
17 & 16
14& 2

om

OR
AOC-HZ12B

"F CAPS ARE CERAMIC TYPES

t::-==----t---t-+r-

1 "FCAPS

15V GND

0.01 "F CAPS ARE CERAMIC TYPES

ORDERING INFORMATION
MODEL
ADC-HX12BGC
ADC-HX12BMC
ADC-HX12BMM
ADC-HZ12BGC
ADC-HZ12BMC
ADC-HZ12BMM

1-216

TEMPERATURE
RANGE
o to +70°C
o to + 70°C
-55to +125°e
o to + 70 0 e
o to + 70 0 e
- 55 to + 125°C

SEAL
EPOXY
HERM.
HERM.
EPOXY
HERM.
HERM.

ACCESSORIES
Part Number

Description

DILS-2

Mating Socket (2 per converter)

TP10K, or
TP100K

Trimming Potentiometers

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADS-105,

ADS-106

12-BIT, 1 MHz
SAMPLING AID CONVERTERS
FEATURES

III

12-Bit resolution
1 MHz throughput
15 Megohm input impedance
Includes fast Sample/Hold
amplifier
3-State output, TTL and CMOS
compatible

GENERAL

I

DESCRIPTION

The ADS-105 and ADS-106 provide
high-speed, highly accurate, multiple
sample digitization of sinusoidal signals.
These devices use a two-pass, digitally
correcting subranging architecture. Both
models have an analog-to-digital (A/D)
converter and a sample-and-hold amplifier
(S/H). Combining both the A/D and S/H in
one device eliminates critical layout
problems assuring stable, high-bandwidth
operation.
The ADS-105 accepts unipolar analog
inputs (0 to +1 OV) while the ADS-106
accepts full scale bipolar inpu~s (±1 OV).
The ADS-1 05/-1 06 offer outstanding high
speed analog performance. Maximum
differential linearity error is 0.025% FSR
±1/2 LSB of full scale (0 °C to +70 °C).The
maximum gain temperature coefficient is
±35 ppm of FSR/oC. Both models
guarantee no missing codes over the full
-55°C to +125 °C operating temperature
range.

Figure 1.

ADS-105, ADS-106 Simplified Block Diagram

For high-reliability versions of either the
ADS-1 05 or the ADS-1 06, contact the factory.

CONNECTIONS
PIN

1.101 MAX
(28,0)

~

0.190 MAX

~
0.010 XO.018
KOVAR

Dynamic specifications include a total
sampling rate of 1 MHz for sinusoidal
signals which do not exceed the internal
bandwidth, settling, and slew rate
specifications. The input bandwidth of the
S/H accepts sinusoidal signals up to 40
KHz (1 OV peak to peak) with -70 dB typical
harmonic distortion.
Applications for the ADS-1 05/1 06 include data acquisition and control systems, array processing, vibration and
resonance analysis, medical imaging and
scanning, communications signal processing, noise and spectrum analyzers,
and video processing.

INPUT/OUTPUT

MECHANICAL DIMENSIONS
INCHES (mm)

~

15
SPACES
AT 0.100
(2,5)

32_..J
' - -_ _ _

0.150 MIN.
(3,8)

1.712 MAX.
(43,5)

~

0.900
(22.9)
NOTE: Pins have a 0.025 inch, ±0.01
sland-off from case.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

SIGNAL NAME
+ 1OV REF OUT
RANGE IN
INPUT HIGH
INPUT LOW
OFFSET ADJUST IN
NO CONNECTION
CaMP BIN IN
OVERFLOW OUT
ENABLE (6-12) IN
ENABLE (1-5 OF) IN
+5V POWER IN
DIGITAL GROUND
+15V POWER iN
-15V POWER IN
-5V POWER IN
ANALOG GROUND
sii=i CONTROL OUT
EOC OUT
BIT 12 (LSB) OUT
BIT 11 OUT
BIT100UT
BIT9 OUT
BIT 8 OUT
BIT 70UT
BIT6 OUT
BIT5 OUT
BIT 4 OUT
BIT3 OUT
BIT2 OUT
BIT 1 (MSB) OUT
START CONVERT IN
GAIN ADJUST IN

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-217

ADS-105,

ADS-106

ABSOLUTE MAXIMUM RATINGS
PERFORMANCE
PARAMETERS

LIMITS

+15V Supply (Pin 13)
-15V Supply (Pin 14)
+5V Supply(Pin 11)
-5V Supply (Pin 15)
Digital inputs
(Pins 7, 9, 10, and 31)
Analog input
Lead temp. (10 sec.)

UNITS

Oto+18
Oto-18
-0.5 to +7
+0.5 to -7
-0.3 to +5.5

Vottsdc
Voltsdc
Voltsdc
Voltsdc
Vo~s dc

-15to+15
300

Voltsdc
°Cmax.

FUNCTIONAL SPECIFICATIONS
The following specifications apply over the operating temperature range and power supply range unless otherwise indicated.

INPUTS

MIN.

Analog Signal Range
ADS-l05
ADS-l06
Input Impedance
Resistance
Capacitance
Input Bias Current

Logic Loading:
Logic 1
Logic 0

_. ----

-

7

-

±20

±500

nA

-

-

0.8

Volts
Volts

-

2.5
-100

Il A
Il A

_._._ ..

-

...

_._-

MIN.

TYP.

-

90
20

-

V/IlSec.
nSec.

-

±100

-

pSec.

-

-

Sinusoidal Input

Volts
Volts
MOhms
pF

-

S/H Acquisition Time
to 0.01% (10V step)
+25°C
O°Cto +70°C
-55°C to +125 'C

-

-

-

Slew Rate
Aperture Delay Time
Aperture Uncertainty
(Jitter)

UNITS

15
5

2.0

SAMPLE/HOLD
SPECIFICATIONS

MAX.

- o to +10
±10
5

Logic Levels:
Logic 1
Logic 0

TYP.

--

--

MAX.

UNITS

715
765
900

nSec.
nSec.
nSec.

395

•
•
•
•

1-218

MAX.

UNITS

-

±0.0125
±0.0125
±0.0125

%FSR ±1/2LSB
%FSR ±1/2LSB
%FSR±3LSB

-

-

±8.5

ppml'C

Differential Nonlinearity
+25°C
°Cto+70°C
-55°C to +125 'C

-

-

±0.0125
±0.0125
±0.0125

%FSR ±1/2LSB
%FSR ±1/2LSB
%FSR±lLSB

Differential Nonlinearity
Tempco

-

-

±6.1

ppm/'C

-

-

±3
±4
±8

±8
±14
±29

LSB
LSB
LSB

-

±1

±3

LSB

-

±13

±25

ppm/oC

-

Integral Nonlinearity
Tempco

o

Full·Scale Absolute
Accuracy
+25°C
O°Cto +70 °C
-55 'C to +125 °C
ADS·l0S
Unipolar Zero
Error, +25 'C
Unipolar Zero
Error
Tempco
ADS·l06
Bipolar Offset
Error, +25 °C
Bipolar Offset
Error Tempeo
Bipolar Zero Error,
+25°C
Bipolar Zero Error
Tempco

-

±2

±5

LSB

-

±17.5

±35

ppm/oC

-

±1

±3

LSB

-

±13

±25

ppm/oC

Gain Error

-

±2

±5

LSB

Gain Error Tempco

-

±17.5

±35

ppm/oC

No missing codes
(For 12 binary bits)

Guaranteed over operating temperature
range.

OUTPUTS

MIN. TYP.

Logic Levels:
Logic 1
Logic 0

2.4

Logic Loading:
Logic 1
Logic 0

-

-

-

MAX.

UNITS

-

0.4

Volts
Volts

-

-160
6.4

mA

10
±5

10.02
±30
1.5

Volts dc
ppm/oC
mA

-

IlA

nSec.
--

--

-_.

APPLICATIONS

•

MIN. T.YP.

Integral Nonlinearity
+25°C
0°Cto+70°C
-55 'Cto +125 °C

High-speed Data Acquisition and Control
Systems
Array Processing, Vibration and Resonance/
transient Analysis
Medical Imaging and Scanning
Communications Signal Processing
Spectrum and Noise Analyzers
Video Processing Systems

Internal Reference:
+Voltage, +25' C
Tempco
External current
Output Coding:
ADS·l0S
(Pin 7 High)
(Pin 7 Low)
ADS-l06
(Pin 7 High)
(Pin 7 Low)

9.98

-

-

Straight binary
Complementary binary
Offset binary
Complementary offset binary
---

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (50S) 339-6356

ADS-l05,
MIN.

TYP.

MAX.

lJIIITS

Conversion Rale:
+25°C
o°C to +70 DC
-55°C to +125 °C

1
1
1

-

-

-

MHz
MHz
MHz

AID Conversion Time:
+25 DC
o'Cto +70 DC
-55 DC to +125 DC

-

-

500
540
560

nSec.
nSec.
nSec.

DYNAMIC
PERFORMANCE

Total Harmonic
Distortion:
DC to 100 KHz,
(Vin = <5V pk-pk)
+25 DC
-55 DC 10 +125 DC
DC to 40 KHz,
(Vin = 10V pk-pk)
+25 DC
-55 DC to +125 °C
DC to 25 KHz,
(Vin = 20V pk-pk)
+25°C
-55 DC to +125 °C

-70
-66

-65
-61

-70
-66

-65
-61

-70
-66

-

-

I

I

-

dB
dB

dB
dB

dB
dB

i
I

TECHNICAL

TYP.

MAX.

UNIT:;

Power Supply Range
+14.25
+ 15V dc Supply
-14.25
-15V dc Supply
+4.75
+5V dc Supply
-4.75
-5V dc Supply

+15
-15
+5
-5

+15.75
-15.75
+5.25
-5.25

Volls dc
Volls dc
Voltsdc
Volts dc

Supply Current
+15V Supply
-15V Supply
+5V Supply'
-5V Supply

-

+40
-30
+56
-173

+54
-40
+90
-210

mA
mA
mA
mA

-

2.2

2.7
±0.01

Watts
%FSR/%V

I~~~~~REMENTS

Power Dissipalion
Supply Rejection
-65
-61

NOTES

1. Use external potentiometers to remove system errors or
to reduce any small initial errors to zero. Use a 20K
trimming potentiometer for gain adjustment with the wiper tied to pin 32 (ground pin 32 for operation without adjustments). Use a 20K trimming potentiometer with the
wiper tied to pin 5 for zer%ffset adjustment (leave pin
5 open for operation without adjustment).
2. Rated performance requires using good high frequency
circuit board layout techniques. The analog and digital
grounds are not connected internally. Avoid groundrelated problems by connecting the digital and analog
grounds to one point, the ground plane beneath the
converter.
Do not connect these grounds together at the power supply terminals when the power supplies are located some
distance from the ground plane. Due to the inductance
and resistance of the power supply return paths, return the analog and digital ground separately to the
power supplies. This prevents contamination of the analog ground by noisy digital ground currents.
3. Bypass all the analog and digital supplies to ground with
a 4.7J..LF, 25V tantalum electrolytic capacitor in parallel
with a 0.1J..LF ceramic capacitor. Bypass the +1 OV reference (pin 1) to ground (pin 16) also using a 4.7J..LF, 25V
capacitor. The -5V dc supply is treated as an analog supply and analog ground (pin 16) should be treated as its
return path for decoupling purposes.
4. Obtain straight binary/offset binary output coding by tying
the CaMP BIN signal (pin 7) to +5V dc or leaving it open.
The device has an internal pull-up resistor on this pin.
To obtain complementary binary or complementaryoffset binary output coding, tie the CaMP BIN pin to
ground. The CaMP BIN signal is compatible to CMOS/
TTL logic levels for those users desiring logic control of
this function.

ADS-l06

PHYSICAL!
ENVIRONMENTAL
Operating Temperature Range
MC Models
MM Models
Storage Temperature Range
Weight
Package Type
Pin Type

MIN.

-

I

-

-

MIN.

TYP.

0
-55

-

+70
+125

'C
°C

-65
-

-

+150
0.42(12)

°C
oz. (gram)

-

MAX.

UNITS

32-pin hermetically sealed ceramic DIP
0.010 x 0.018 inch Kovar

• + 5V power usage at 1 TTL logic loading per data output bit.

5. An overflow signal, pin 8, indicates when analog input signals are below or above the desired full-scale range. The
overflow Rin also has a three-state output and is enabled
by pin 10 (Enable bits 1-5 & O.F.).
6. The S/H Control signal, pin 17, goes low following the rising
edge of a start convert pulse and high 30 nanoseconds
minimum before EOC goes low. This indicates that the converter can accept a new analog input.
7. Full-scale absolute accuracy refers to the unadjusted performance of the ADS-1 05/1 06. These figures may be improved substantially using external trim circuits.

THEORY OF OPERATION
This theory of operation describes the ADS-1 05/1 06's function
in conjunction with its internal Sample/Hold amplifer for digitizing sinusoidal signals. The ADS-1 05/1 06 employs a subranging
A/D conversion architecture with digital error correction. Also
known as a two-step conversion method, this technique uses a
single 7 -bit flash AID converter twice in the conversion process
to yield a final resolution of 12 bits. Refer to the connection diagram, the block diagram, and the timing diagram as needed.
The ADS-1 05/1 06 guarantees a 1 MHz throughput rate when
the START CONVERT pulse of 50 nanoseconds is provided at
a 1 MHz rate. The 1 MHz rate is based upon sinusoidal input frequencies up to those specified in the harmonic distortion specifications. The acquisition time for pulse or level signals is longer
and listed under the acquisition specifications (1 OV step).
The ADS-1 05/1 06 is i!lJhe sample mode when the S/j:j CONTROL pin is high (S/H is in high-state on power-up). The
START CONVERT pulse should be given at a time delay equal
to the desired acquisition time minu.§. the 10 nanosecond delay
from START CONVERT high to S/H CONTROL low. This as

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

•

1-219

ADS-105,

ADS-106

THEORY OF OPERATION (Cont.)
sures the sample·hold has the minumum required acquisition
time for the particular application mode. Sinusoidal inputs being digitized by using a repetitive START CONVERT pulse will
automatically give the appropriate acquisition time when continuously sampling.

puts consists of 395 nanoseconds for acquisition time, 75 nanoseconds for START CONVERT and min-max propagation delays, 560 nanoseconill> for ND conversion time minus 30 nanoseconds for the S/H CONTROL pin. A throughput time of
1000 nanoseconds is obtained and a 1 Mhz throughput rate is
realized.

Upon going into the hold mode, there will be a 75 nanosecond
delay before EOC goes high and the AID conversion begins.
This consists of the remaining 40 nanoseconds of the START
CONVERT (10 nanoseconds is part of the acquisition time)
and a 35 nanosecond maximum delay from START CONVERT
low to EOC high. The hold mode settling time and input settling time requirements required are met by observing this timing.

Combining the ND and S/H in one device allows the ADS-1051
106 to guarantee a total throughput period of 1.0 microsecond
maximum over the ·55 °C to + 125°C temperature range for the
complete system or a throughput ratu!..1 MHz. Retriggering
the START CONVERT pulse before EOC goes low will not initiate a new conversion.

The practical results of this means that single-channel (non·
multiplexed) full-scale inputs with spectral content not exceeding 40 KHz for 1OV peak-peak signals may be digitized up
After conversion is initiated, switch S1 of the ADC closes and
to a 1 MHz rate. This will give about 25 data samples per cycle
S2 opens. The analog input, having been configured for the to 12-bit accuracy and linearity. This type of resolution is ideal
appropriate input range, is buffered and then digitized by the
for capture of signals with a broad spectral content of 40 KHz
7-bit flash ADC to determine the seven most significant bits.
and below (10V peak-to-peak signals). Because many samThe seven bits of data are then stored in a register and provid- ples may be taken in a short sampling interval, the ADS-1 051
ed to the input of a 7-bit digital-to-analog converter. This DAC 106 are ideal for computer-aided spectral analysis of a complexhas 13 bits of linearity.
frequency signal. The 12-bit performance is ideal for larger fast
fourier transform sizes of 1024 to 4096 points by reducing freWhen the first pass finishes, S2 closes and S1 opens. The quency binning resolution noise.
output of the DAC is then subtracted from the analog input.
The result is a voltage difference between the first 7 ·bit digiti· For multi-channel multiplexed signals, the very high multiplexzation and the analog input. This voltage difference is ampli- ing rate allows larger numbers of channels while still retaining
fied and converted by the 7-bit ADC. The result of this second moderate bandwidth per channel. Users requiring higher input
conversion is then latched to determine the least 7 significant bandwidth or faster acquisition times should review Datel's
bits. The outputs from the two registers are then combined by ADS-21 or ADS-22 Sampling ND converter.
the digital correction logic to produce a 12-bit word. EOC goes
low indicating the conversion is complete, and the output Table 1. ADC-105, ADC-106 Timing Specifications
passes to three·state output buffers.
TIMING

Once the second step of the flash ADC is finished, the analog
input can change even though the convers[Q.n cycle has not
been completed (EOC goi.ng.Jow). The S/H Control output
goes high shortly before EOC goes low, indicating that the
Sample/Hold is back sampling the input. This feature improves
the overall throughput of the ADS-1 05/1 06.
Data from the previous conversion is valid up to 350 nanoseconds after the falling edge of the START CONVERT pulse.
Data from the new conversion is valid a minimum of 25 nanoseconds before the EOC goes low and valid up to 350 nanoseconds after the falling edge of the next START CONVERT
pulse. There is a 10 nanosecond maximum delay after the
three-state output buffers are enabled before the data is valid
at the device output.
The overall throughput of the ADS-1 05/1 06 for sinusoidal in·

MIN.

TYP.

MAX.

UNITS

i
I

Start Convert Pulse
Width:
Start Convert Low
to EOC High Delay
Start Convert Low
to Previous Data
Invalid
Data Valid Before
EOC Goes Low
Enable to Output
Data Valid Delay
EOC Low to Start
Convert High
(Sinusoidal Inputs)

50

i

-

nSec.

35

nSec.

20

-

350

-

-

nSec.

25

-

-

nSec.

-

-

10

nSec.
nSec.

355

-

Note: Table 1 applies over the operating temperature range
and over the operating power supply range.
NOTES:
1, Drawmg IS not to scale

_~t>---"--17
31

29

HI

BIT 3 OUT

28

BITS

elT 4 OUT

27

our

26

~:~ ~ ~ ~ ~i

COMPl BIN
START CONVERT

"

BIT 10 OUT

21

BIT 11 OUT

20

our (LSB)

19

BIT 12

ZERO/OFFSET

•

~}

BIT 2 OUT

BIT 5

ADS-106

ENABCE:-U'fBiTSTKi

9

EO(; OUT

18

JLO

BITS

AOJ IN

20KO

Figure 3. ADS-l06 Typical External Connections, ± 10V dc
SYSTEM CALIBRATION PROCEDURE
For bipolar operation, adjust the potentiometer such that
the code flickers equally between 1000 0000 0000 and
1. Connect the converter per Figure 3 and Table 2 for the ap- 1000 0000 0001 with the COMP BIN tied hi~ or between
propriate full-scale input range (FSR). The data outputs 0111 1111 1111 and 0111 1111 1110 with C MP BIN tied
should be connected to LED's to observe the resulting data low.
values.
3. Full Scale Adjustment:
Remove system errors or the small initial errors as follows:

Table
INPUT VOLTAGE
RANGE
Oto +10V dc
±10Vdc

2.

Input Connections

INPUT
PIN

JUMP PIN 2
TO PIN:

3
3

No connection
1 (+10VRef.)

Apply a pulse of 50 nanoseconds minimum to the START CONVERT input (pin 31) at a rate of 500 KHz. This rate is chosen to
reduce flicker if LED's are used on the outputs for calibration
purposes.
2. Zero Adjustments:
Apply a precision voltage reference source between the analog input (pin 3) and analog ground (pin 16). Use a very lownoise signal source for accurate calibration.
Adjust the output of the reference source per Tables 3 and
4 for the unipolar zero adjustment (+1/2 LSB) or the bipolar
zero adjustment (zero + 1/2 LSB) for the appropriate full
scale range. For unipolar operation, adjust the zero trimming
potentiometer so that the output code flickers equally between
0000 00000000 and 0000 0000 0001 with the COMP BIN
(pin 7) tied high or between 1111 1111 1111 and 1111
1111 1110 with COMP BIN tied low.

Set the output of the voltage reference used in step 2 to the
value shown in the Tables 3 and 4 for the unipolar or bipolar
gain adjustment (+F.S. -1 112 LSB) for the appropriate FSR.
Adjust the gain trimming potentiometer so that the output
code flickers equally between 1111 1111 1110 and 1111
1111 1111 for COMP BIN (pin 7) tied high or between 0000
0000 0001 and 0000 0000 0000 for COMP BIN tied low.
To confirm proper operation of the device, vary the
precision reference voltage source to obtain the output
coding listed in the Tables 5 and 6.

Table 3. Zero and Gain Adjust for Unipolar Use
RANGE
UNIPOLAR FSR
o to+10V

ZERO ADJUST
(+ 1/2 LSB)
+1.22mV dc

GAIN ADJUST
(+FS -1 1/2 LSB)
+9.9963V dc

Table 4. Zero and Gain Adjust for Bipolar Use
RANGE
BIPOLAR FSR
±10V

ZERO ADJUST GAIN ADJUST
(+ 112 LSB)
+2.44mV

(+FS -1 1/2 LSB)
+9.9927V

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

1-221

ADS-105,

ADS-106
Table S. Output Coding for Unipolu,Operation
UNIPOLAR
SCALE

INPUT RANGE

o to
+FS - 1 LSB
7/8 FS
3/4 FS
1/2 FS
1/4 FS
1/8 FS
1 LSB

0

BIPOLAR
SCALE

MSB

+10V

1111
1110
1100
1000
0100
0010
0000
0000

+9.9976V
+8,750V
+7.500V
+5.000V
+2,500V
+1.250V
+0.0024V
O.OOOOV

Table S.

0
-1/2 FS
-3/4 FS
-FS + 1 LSB
-FS

1111
0000
0000
0000
0000
0000
0000
0000

LSB

MSB

LSB

1111
0000
0000
0000
0000
0000
0001
0000

0000 0000
0001 1111
0011 1111
0111 1111
10111111
1101 1111
1111 1111
1111 1111

0000
1111
1111
1111
1111
1111
1110
1111

Output Coding for Bipolar Operation

INPUT RANGE

+FS - 1 LSB
+3/4 FS
+1/2 FS

OUTPUT CODING
Straight Binary
Complementary
Straight Binary

OUTPUT CODING
Straight Binary
Complementary
Straight Binary

± 10V

MSB

+9.9951 V
+7,5000V
+5,0000V
O.OOOOOV
-5.0000V
-7.5000V
-9.9951 V
-10.000V

1111
1110
1100
1000
0100
0010
0000
0000

1111
0000
0000
0000
0000
0000
0000
0000

LSB

MSB

1111
0000
0000
0000
0000
0000
0001
0000

0000
0001
0011
0111
1011
1101
1111
1111

LSB
0000
1111
1111
1111
1111
1111
1111
1111

0000
1111
1111
1111
1111
1111
1110
1111

ORDERING INFORMATION
ADS-lOS
ADS-lOS
MODEL

ADS-l0SMC
ADS-l0SMC
ADS-l0SMM
ADS-l0SMM

12-Bit, 1 MHz
Sampling AID Converters

TEMPERATURE INPUT VOLTAGE
RANGE
RANGE
OOCto +70°C
OOCto +70°C
-55°C to + 125°C
-55 °C to + 125°C

o to +1 OV
-10 to +10V

o to +10V
-10 to +10V

Trimming Potentiometer:
TP 20K (2 required)
A receptacle for PC board mounting can be ordered through AMP
Incorporated. #3-331272-8 (Component Lead Socket). 32 required,
For high-reliability versions of the ADS-1 05/-1 06. contact the factory.

1-222

DATEL. Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

ADS-111
12-Bit, 500 KHz, LowPower
Sampling AID Converter
FEATURES
•
•
•
•
•
•
•

•

12-Bit resolution
Internal Sample/Hold
500 KHz minimum throughput
Functionally complete
Small 24-pin DIP
Low-power. 1.4 Watts
Three-state output buffers
r--~ENABLE(112)

GENERAL DESCRIPTION
BIT llMSBl

DATEL's ADS-111 is a 12-bit, functionally
complete, sampling AID converter that is
packaged in a space-saving 24-pin ceramic DIP. A minimum throughput rate of
500 KHz is achieved while only dissipating 1.4 Watts.
Manufactured using thick-film and thinfilm hybrid technology, the ADS-111's exclusive performance is based upon a digitally-corrected subranging architecture.
DATEL further enhances this technology
by using a proprietary chip and unique laser trimming schemes. Figure 1 is a simplified block diagram of the ADS-111.
The ADS-111 features two pinprogrammable analog input voltage ranges: 0 to + 1OV and ± 5V. The input impedance is specified at 15 M Ohms. The
ADS-111 is also guaranteed to have no
missing codes over the operating temperatu re range.
All digital inputs and three-state outputs
are TTL- and CMOS-compatible. Output
coding can be in straight binary/offset binary or complementary binary/
complementary offset binary.
The power requirements are ±15V dc and
+5V dc. The ADS-111 is available in the
commercial 0 degrees Celsius to +70 degrees Celsius and military -55 degrees
Celsius to +125 degrees Celsius operating temperature range.
Typical applicationf include spectrum,
transient, vibration and waveform analysis. This device is also ideally suited for
radar, sonar, video digitization, medical
instrumentation and high-speed data acquisition systems. For information on
high reliability screening, contact DATEL.

Figure 1. ADS-iii Simplified Block Diagram

MECHANICAL DIMENSIONS
INCHES (mm)
0.800MAX
(20,3)

~0.010 X 0.018 ~
KOVAR Pins

13

12

BOTTOM
VIEW

24_- '
L...-_ _ _

0.190 MAX

~
~

0.150 MIN.
(3,8)

TI
11
SPACES
AT 0.100
(2,5)

1.310 MAX.
(33,3)

-hL

0.600
(15,2)
NOTE: Pins have a 0.025 inch, 0.01
stand-off from case.

1/0

CONNECTIONS

PIN

FUNCTION

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

BIT 12 OUT (LSB)
BIT 11 OUT
BIT100UT
BIT90UT
BIT 8 OUT
BIT 7 OUT
BIT 6 OUT
BIT50UT
BIT40UT
BIT30UT
BIT 2 OUT
BIT 1 OUT (MSB)
+5V
DIGITAL GROUND
EOC
START CONVERT
ENABLE (1-12)
COMPBIN
ANALOG INPUT
BIPOLAR
+10V REF
+15V
ANALOG GROUND
-15V

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-223

ADS-lll
ABSOLUTE MAXIMUM RATINGS

OUTPUTS

PARAMETERS

LIMITS

UNITS

+15V Supply (Pin 22)
-15V Supply (Pin 24)
+5V Supply (Pin 13)
Digital Inputs
(Pins 16, 17, 18)
Analog Input (Pin 19)
Lead Temp.(10 Sec.)

oto + 18
oto -18

Volts dc
Volts dc
Volts dc

-0.5 to +7.0
-0.3 to +6.0
-15to+15
300 max

Volts dc
Volts dc

"C

Apply over the operating temperature range and over the op·
erating power supply range unless otherwise specified.

Input Voltage Range
ADS-111 ....................
(See Table 4 also) .........
Input Impedance ......
Input Capacitance .....

MIN.

TYP.

MAX.

UNITS

-

±5
oto +10
15.0
3

-

5.0

-

-

Volts de
Volts de
MOhms

5

~

-

Volts de
Volts de

-

DIGITAL INPUTS
Logic Levels

~~~:~ ::~::::::.::::::,::::,:::::::::

Log!e Load!ng ,,1 "...........
Logic Loading 0 ...........

2.0

-

-

0.8
2.5
-100

IJA
IJA

A/D PERFORMANCE
Integral Non-Linearity
+25 'C .........................
o 'C to +70 'C ................
-55 C to +125 'C .............
Integral Non-Lin.
Tempco ...................
Differential Non·Linearity
+25 'C .........................
o 'C to +70 'C ................
-55 C to +125 'C .............
Differential Non-Lin.
Tempco ...................
Full Scale Absolute
Accuracy
+25 'C .........................
o 'C to +70 'C ................
-55 C to +125 'C .............
Unipolar Zero Error,
+25 'c (See Tech Note 1)
Unipolar Zero Tempco.
Bipolar Zero Error,
+25 'C (See Tech Note 1)
Bipolar Zero Tempco ...
Bipolar Offset Error,
+25 'C (See Tech Note 1)
Bipolar Offset Tempco
Gain Error, +25 'C .....
(See Tech Note 1)
Gain Tempeo ............
Conversion Times
+25 'C ........................
o 'C to +70 'C ...............
-55 'C to +125 'C ............
No Missing Codes
(12 Bits)

1·224

-

±1/2
±1/2

-

±3/4
±3/4
±3

LSB
LSB
LSB

-

±5

±10

ppm/'C

-

±1/2
±1/2

-

±3/4
±3/4
±1

LSB
LSB
LSB

-

-

±2.5

ppm/'C

-

-

±5
±6
±10

±10
±18
±32

LSB
LSB
LSB

-

±3
±15

±5
±30

LSB
ppmI'C

-

±3
±5

±5
±8

LSB
ppmI'C

-

±4
±20
±4

±8
±40
±8

LSB
ppm/'C
LSB

-

±20

±40

ppmI'C

-

-

1.0
1.0
1.15

~Sec.
~Sec.
~Sec.

-

-

LogiC. ~,e~els

~~~:~ ,,6,,::::.::::::,;::,~:::::::::.

UNITS

MAX.

2.4

LogiC Loading "1,, .......... .
LogiC Loading 0 .......... .
Internal Reference
Voltage, +25 'C ....... .
+9.98
Drift. ......................... .
External Curren!... ........ .
Resolution ............ .
Output Coding
(Pin 18Hi)
(Pin 18 Low)

FUNCTIONAL SPECIFICATIONS

ANALOG INPUTS

MIN. TYP.

Volts dc
Volts dc

0.4
-160
6.4
+10.0
±5

IJA

rnA

+10.02 Volts dc
±30
ppmI'C
1.5
mA

12 Bits
Straight binary/offset binary
Complementary binary
Complementary offset binary

SAMPLE/HOLD PERFORMANCE
90
20
±100

Slew Rate ............... .
Aperture Delay Time ...
Aperture Uncertainty ..
S/H AcquiSition Time
to 0.01% (10V step)
+25 'C ....................... .
o 'C to +70 'C .............. .
-55 'C to +125 °C ........... .
(Sinusoidal Input) ......... .

V/~Sec.

nSec.
pSec.
715
765
900
465

nSec.
nSec.
nSec.
nSec.

+15.0
-15.0
+5.0

+15.75
-15.75
+5.5

Volts dc
Volts dc
Volts dc

+38
-36
+66
1.4

+43

-44
+75
1.75
0.01

rnA
rnA
rnA
Watts
%FSR/%V

0
-55

+70
+125

'C
'C

-65

+150

'C

POWER REQUIREMENTS
Power Supply Range
+15V dc Supply .......... .
-15V dc Supply ........... .
+5V dc Supply ............ .
Power Supply Current
+15V dc Supply .......... .
-15V de Supply ........... .
+5V dc Supply· .......... .
Power Dissipation ... .
Power Supply Rejection .. .

+14.25
-14.25
+4.5

PHYSICAL/ENVIRONMENTAL
Operating Temp. Range
·MC.........................
·MM........................
Storage Temperature
Range.................
Package Type ...... .
Pins
Weight

~--~--~----~----~

24-pin hermetic sealed, ceramic DIP
0.010 x 0.Q18 inch Kovar
0.42 ounces (12 grams)

• +5V power usage at 1 TTL logic loading per data output bit.

TECHNICAL NOTES
1. Applications which are unaffected by endpoint errors or re·
move them through software will use the typical connec·
tions shown in Figure 4. Remove system errors or adjust
the small initial errors of the ADS-111 to zero using the op·
tional external circuitry shown in Figure 3. The external ad·
justment circuit has no affect on the throughput rate.

Over the Operating Temp. Range.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ADS-111
2. When the optional external adjustment circuitry is used,
additional input ranges are available. Refer to Figure 3 and
Table 4.
3. Rated performance requires using good high-frequency circuit board layout techniques. The analog and digital
grounds are not connected internally. Avoid groundrelated problems by connecting the digital and analog
grounds to one point, the ground plane beneath the converter (versus at the power supply terminals when the power supplies are located some distance from the ground
plane).
Due to the inductance and resistance of the power supply
return paths, return the analog and digital ground separately to the power supplies. This prevents contamination
of the analog ground by noisy digital ground currents.
4. Bypass the analog and digital supplies and the + 1OV reference (pin 21) to ground with a 4.7IlF, 25V tantalum electrolytic capacitor in parallel with a 0.1 IlF ceramic capacitor.
Bypass the + 1OV reference (pin 21) to analog ground (pin
23).
5. Obtain straight binary/offset binary output coding by tying
COMP BIN (pin 18) to +5V dc or leaving it open. The device has an internal pull-up resistor on this pin. To obtain
complementary binary or complementary offset binary out~ coding, tie the COMP BIN pin to ground. The COMP
BIN signal is compatible to CMOS/TTL logic levels for
those users desiring logic control of this function.
6. To obtain three-state outputs, connect ENABLE (pin 17) to
a logic "0" (low). Otherwise, connect ENABLE (pin 17) to a
logic "1" (high).

THEORY OF OPERATION
This theory of operation describes the ADS-Ill's function in
conjunction with its internal sample-and-hold amplifier for digitizing sinusoidal signals. The ADS-lIt employs a subranging ND conversion architecture with digital error correction. Also known as a two-step method of conversion, this
technique uses a single 7-bit flash converter twice in the
conversion process to yield a final resolution of 12 bits. Refer to the connection diagram, block diagram, and timing diagram as needed.
The ADS-ttl guarantees a 500 KHz throughput rate over
the temperature range when the START CONVERT pulse of
200 nanoseconds is provided at a 500 KHz rate. The 500
KHz rate is based upon sinusoidal input frequencies up to
those specified in the harmonic distortion specifications.
The acquisition time for pulse or DC level signals is longer
and listed under the acquisition specifications (1 OV step).
The ADS-III is in the sample mode when the internal SiR
CONTROL is high (S/R is in the high state on power-up). The
START CONVERT pulse should be given at a time delay
equal to the desired acquisition time minus the 10 nanosecond delay from START CONVERT high to SiR CONTROL low.
This assures the sample-hold has the minimum required acquisition time for the particular application mode. Sinusoidal
inputs being digitized by utilizing a repetitive START CONVERT pulse will automatically give the appropriate acquisition time when continuously sampling.

Upon going into the hold mode, there will be a 225 nanosecond delay before EOC goes high and the ND conversion begins. This consists of the remaining 190 nanoseconds of the
START CONVERT (10 nanoseconds is part of the acquisition
time) and a 35 nanosecond maximum delay from START CONVERT low to EOC high. The hold mode settling time and input
settling time requirements required for the first pass of the N
D conversion are met when observing this time.
After conversion is initiated, switch SI of the ADC closes and
S2 opens. The analog input, having been configured for the
appropriate input range, is buffered and then digitized by the
7-bit flash ADC to determine the seven most significant bits.
The seven bits of data are then stored in a register and provided to the input of a 7-bit digital-to-analog converter. The
DAC has 13 bits of linearity.
When the first pass finishes, S2 closes and SI opens. The
output of the DAC is then subtracted from the analog input.
The result is a voltage difference between the first 7-bit digitization and the analog input. This voltage difference is amplified and converted by the 7-bit ADC. The result of this second conversion is then latched to determine the least 7 significant bits. The outputs from the two registers are then combined by the digital correction logic to produce a 12-bit word.
EOC goes low, indicating the conversion is complete, and the
output passes to the three-state output buffers.
Once the second step of the flash ADC is finished, the analog
input can change even though the conversion cycle has not
been completed (EOC going 10!!L. The sample/hold control
outputJJoes high shortly before EOC goes low, indicating that
the S/H is back sampling the input. This feature improves the
overall throughput rate of the ADS-III.
Data from the previous conversion is valid and capable of being latched 20 nanoseconds after the falling edge of EOC and
remains valid for 1300 nanoseconds. Data from the new conversion is valid a minimum of 20 nanoseconds after the next
EOC low transition. There is a 10 nanosecond maximum delay after the three-state output buffers are enabled before the
data is valid at the device output.
The overall throughput rate over temperature of the ADS-III
for sinusoidal inputs consists of 465 nanoseconds for the acquisition time, 225 nanoseconds for the START CONVERT
and min-max propagation delays, and 1150 nanoseconds for
the ND conversion. An internal function reduces this cumulative time by 30 nanoseconds by putting the sa~.~/hold
back into the sample mode 30 nanoseconds before EOC goes
low. A throughput time of 1810 nanoseconds is obtained and
the minimum throughput rate of 500 KHz is easily met.
Combining the ND and S/H in one device allows the ADS-III
to guarantee a throughput rate of 500 KHz over the -55 degrees Celsius to + 125 degrees Celsius temperature range for
the complete~tem. Retriggering of the START CONVERT
pulse before EOC goes low will not initiate a new conversion.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-225

•

ADS-111

ANALOG
INPUT

NOTE: NOT DRAWN TO SCALE

-,........,.

.I

ANALOG
INPUT
SETTLING
TIME

- - - - - - - - . - - - - - -_ _ _ _ __
600

I

- I - nSec
I

--..1'1._ _ _ _ _ _ _ _ _ _ _ _ _ _ __

MINIMUM

I

START
CONVERT

'465 nSec ACQUISITION TIME (SINUSOIDAL INPUT)

--l

I"

"I

CONVERSION TIME
20n Sec. MINIMUM
35n Sec. MAXIMUM

30 nSec :
MIN

-l I(INTERNAL)
SIR

I

I
I

--

OUTPUT
DATA
ENABLE

I:8J

I

r1300 nSec MINIMUM--i
1--20 nSecMAXIMUM

10~

ENABLED DATA

ENABLED DATA
I-N·1 VALID

+j I- N VALID

10 nSec.
MAXIMUM

MAXIMUM

Figure 2.

DATA
INVALID

ADS-111 Timing Diagram

TIMING

INPUT CONNECTIONS

Figure 2 shows the relationship between the various input
signals. The timing shown in Table 1 applies Over the operating temperature range and over the operating power supply
range. These times are guaranteed by design.

Table 1. Signal Timing Summary
LINE

DURATION

Table 2.

ADS-111 Input Range Selection

INPUT RANGE

INPUT PIN

TIE

±5Vdc
Oto+10Vdc

Pin 19
Pin 19

Pin 20 to PIN 21
Pin 20 to GROUND

Table 3a.

TOGETHER

Zero and Gain Adjust, Unipolar Opertion

UNIPOLAR FSR

ZERO ADJUST GAIN ADJUST
+ 1/2 LSB
+FS - 1 1/2 LSB

START CONVERT
Pulse Width

200 nSec. minimum

Analog Input Settling Time

600 nSec. minimum

START CONVERT Low to EOC
High Propagation Delay

35 nSec. maximum

BIPOLAR FSR

ZERO ADJUST
o + 1/2 LSB

EOC Low to Previous
Output Data Invalid

1320 nSec. minimum

±5Vdc

+1.22mVdc

Data Valid After EOC
goes Low

20 nSec. maximum

CALIBRATION PROCEDURE

ENABLE to Output Data Valid
Propagation Delay

10 nSec. maximum

Should removal of system errors or the small initial errors be
desired, adjustment is accomplished as follows:

EOC Low to START CONVERT High
(Sinusoidal Inputs)

425 nSec. minimum

1·226

oto +10V dc
Table 3b.

+1.22mVdc

+9.9963Vdc

Zero and Gain Adjust, Bipolar Operation
GAIN ADJUST
+FS - 1 1/2 LSB
+4.9963V dc

1. Connect the converter per Figure 3, Figure 4, and Table 2 for
the appropriate full-scale range (FSR). Apply a pulse of 200
nanoseconds minimum to the START CONVERT input (pin
16) at a rate of 250 KHz. This rate is chosen to reduce flicker
if LED's are used on the outputs for calibration purposes.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADS-111
Calibration con't.
R2

2. Zero Adjustments
Apply a precision voltage reference source between the
amplifier's analog input and ground. Adjust the output of
the reference source per Tables 3a and 3b for the unipolar
zero adjustment (+ 1/2 LSB) or the bipolar zero adjustment
(zero + 1/2 LSB). For unipolar, adjust the zero trimming potentiometer so that the output code flickers eqU~b~~­
tween 0000 0000 0000 and 0000 0000 0001 with the
BTIiI (pin 18) tied high (straight binary) or between 1111
1111 1111 and 1111 1111 1110 with the COMP BIN (pin 18)
tied low (complementary binary).

+

5Kn
SIGNAL
INPUT v--vvv",.,

GAIN
ADJUST

Figure 3. Optional Calibration Circuit
The performance characteristics shown in Table 5 apply over
the operating temperature range and over the operating power supply range unless otherwise specified. These characteristics are guaranteed by design.

Table 5. Dynamic Performance
Throughput Rate
(Changing Inputs)
+25°C
0°Cto+70 °C
-55CIO +125 °C

Table 4. Input Ranges
(using external calibration)
R1

o to +10V,±5V
o to +5V, ± 2.5V
o to +2.5V, ±1.25V

2
2
2

R2
2

6
14

50n

5Kn

4. To confirm proper operation of the device, vary the precision reference voltage source to obtain the output coding
listed in Tables 6 and 7.

INPUT RANGE

•

R1

For bipolar operation, adjust the potentiometer such that
the code flickers equally between 1000 0000 0000 and
100000000001 with COMP BIN (pin 18) tied high (offset binary) or between 0111 1111 1111 and 0111 1111 1110 with
COMP BIN (pin 18) tied low (complementary offset binary).
3. Full-Scale Adjustment
Set the output of the voltage reference used in step 2 to
the value shown in Table 3a or 3b for the unipolar or bipolar
gain adjustment (+FS -1 1/2 LSB). Adjust the gain trimming
potentiometer so that the output code flickers etjally between 1111 1111 1110 and 1111 1111 1111 for C MP BIN
(pin 18) tied high or between 0000 0000 0001 and 0000
00000000 for COMP BIN (pin 18) tied low.

15V

AID Conversion Time
+25OC
o°Clo+70 °C
-55 Clo +125 °C

UNIT

Total Harmonic Distortion
DC to 100 KHz al Vin ~V pop
DC 10 60 KHz at Vin = 10V pop

KOhms
KOhms
KOhms

+ 15V

MIN

TYP

500
500
500

600
600

-

KHz
KHz
KHz

-

-

-

-

1.0
1.0
1.15

~Sec.
~Sec.
~Sec.

-65
-65

-70
-70

-

dB
dB

-151/

MAX UNITS

-

+ sv

ANALOG

INPUT

Figure 4.

81T 1 (MSBI

Typical ADS·111
Connection Diagram

11

+5V DC

81T 3

START
CONVERT

ADS·111

1-14
l®

I
I

I

~

_ _ _ _ .1

BIPOLAR
OPERATION

BIT 2

BIT 6
81T 1

BIT9
BIT 10
BIT 11

BIT 12

+ 10 REF

r--""'-(21

me

E"NABTE( '·12)

~., ~F 14.7~F!-,_ _ _ _ _ _ _ _ _ _ _---'

,

-----------1

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-227

ADS-111
Table 6. Output Coding for Bipolar Operation
INPUT RANGE
OUTPUT CODING
(Volts de)
OFFSET BINARY· COMPo OFFSET BINARY
±5V
MSB
LSB
MSB
LSB

BIPOLAR
SCALE
+FS-1 LSB
+3/4 FS
+1/2 FS

0
-1/2 FS
-3/4 FS

-FS+1 LSB
-FS

111111111111
111000000000
1100 0000 0000
1000 0000 0000
010000000000
001000000000
0000 0000 0001
0000 0000 0000

+4.9976V
+3.7500V
+2.5000V
O.OOOOV
-2.5000V
-3.7500V
-4.9976V
-5.0000V

0000 0000 0000
0001 1111 1111
0011 1111 1111
0111 11111111
1011 1111 1111
110111111111
111111111110
111111111111

Table 7. Output Coding for Unipolar Operation
UNIPOLAR
SCALE

INPUT RANGE
OUTPUT CODING
STRAIGHT BINAR
COMPo BINARY
(Volts de)
MSB
LSB
MSB
LSB
to +10V

+FS-1LSB
7/S FS
3/4FS
1/2 FS
1/4 FS

1/S FS
1 LSB
0

o

+9.9976V
+S.7500V
+7.5000V
+5.0000V
+2.5000V
+1.2500V
+0.0024V
O.OOOOV

111111111111
111000000000
1100 0000 0000
1000 0000 0000
010000000000
0010 0000 0000
000000000001
0000 0000 0000

0000 0000 0000
0001 1111 1111
0011 1111 1111
0111 1111 1111
1011 1111 1111
1101 1111 1111
111111111110
111111111111

ORDERING INFORMATION
MODEL NUMBER
ADS-111MC
ADS-111MM

OPERATING TEMP. RANGE

SEAL

o°C to +70 °C
-55°C to +125 °C

Hermetic
Hermetic

ACCESSORIES

Part Number

Description

TP10K*
TP50*

Trimming Potentiometer
Trimming Potentiometer

* Only required if .optional external calibration circuitry is used.
Receptacle for PC board mounting can be ordered through AMP Inc.,
Part # 3-331272-S (Component Lead Socket), 24 required.
For high reliability versions of the ADS-111 contact DATEL.

1-228

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADS-115,

ADS-116

10-BIT, 1 MHz
SAMPLING AID CONVERTERS
FEATURES
10-Bit resolution
1 MHz throughput
• 15 Megohm input impedance
Includes fast Sample/Hold
amplifier
3-State output, TTL and CMOS
compatible

GENERAL DESCRIPTION
DATEL's ADS-115 and ADS-116 combine
a tracking Sample/Hold amplifier and a
high-speed, 10- bit Analog-to-Digital converter, all in one small device. The ADS115 and ADS-116 provide digitized outputs of sinusoidal signals at up to one million samples per second. By combining
both the S/H and AID circuits in one device, critical layout and thermal factors are
overcome. This offers stable, highbandwidth performance with negligible
degradation over time.
The ADS-115 accepts unipolar inputs
from 0 to +10 volts and the ADS-11 6 has
a ±10 volt input range. Both models are
offered in commercial (0 °C to +70 °C) and
military (-55 °C to +125 °C) temperature
ranges. For 12-bit applications, users
should consider Datel's ADS-1 05/1 06 or
the SHM-45/ADC-500 pair.
Linearity error is ±1/2 LSB (0 °C to +70 0C)
and the maximum gain temperature coefficient is ±35 ppm of full scale range per degree Celsius. Maximum power required is
2.7 watts using ±15 and ±5 volt dc supplies.
The ADS-115/116 may be sampled up to
1 MHz. The input bandwidth of the S/H
will accept up to 60 KHz (1 OV pk-pk) with
-60 dB typical harmonic distortion.
These miniature hybrid sampling AID converters are ideal for fast data acquisition
and control systems, array processing,
DSP applications, imaging, medical scanning, signal processing, acoustic, resonance, and vibration analyzers.
For high reliability versions of either the
ADS-115 or the ADS-116, contact the factory.

Figure 1.

ADS-115, ADS-116 Simplified Block Diagram
INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (mm)
PIN

1.101 MAX
(28,0)

0.190 MAX

~0.010 X 0.018 ~
KOVAR Pins

17

,16

,,
,,
,
,,,
,,
,,
,,
,,
I

I

BOTTOM

VIEW

I

I

!

,
,,
,,,
,,
,,
,,
,,
,

1

32

I
,
!

~
~

4

0.150 MIN.
(3,8)

Tl
15
SPACES
AT 0.100

1.712 MAX.

(43,5)

(2,5)

-hL

0.900
(22,9)
NOTE: Pins have a 0.025 inch, ±0.01

stand·off from case.

1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

SIGNAL NAME
+10VREFOUT
RANGE IN
INPUT HIGH
INPUTLOW
OFFSET ADJUST IN
NO CONNECTION
COMPBININ
OVERFLOW OUT
ENABLE (6·10) IN
ENABLE (1·50.F.) IN
+5V POWER IN
DIGITAL GROUND
+15V POWER IN
-15V POWER IN
·5V POWER IN
ANALOG GROUND
S/H CONTROL OUT
EOCOUT
NO CONNECTION
NO CONNECTION
BIT 100UT
BIT90UT
BIT80UT
BIT 7 OUT
BIT60UT
BIT5 OUT
BIT4 OUT
BIT30UT
BIT20UT
BIT 1 (MSB) OUT
START CONVERT IN
GAIN ADJUST IN

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

1-229

ADS-115,

ADS-116

ABSOLUTE MAXIMUM RATINGS
PERFORMANCE
PARAMETERS

LIMITS

+ 15V Supply (Pin 13)
-15V Supply (Pin 14)
+5V Supply(Pin 11)
-5V Supply (Pin 15)
Digital inputs
(Pins 7, 9, 10, and 31)
Analog input
Lead temp. (10 sec.)

o to +18
o to -18

UNITS

-0.5 to +7
+0.5 to-7
-0.3 to +6

Volts
Volts
Volts
Volts
Volts

de
de
de
de
de

-15to +15
300

Volts de
°Cmax.

FUNCTIONAL SPECIFICATIONS
The following specifications apply over the operating temperature range and power supply range unless otherwise indicated.

INPUTS

MIN.

Analog Signal Range
ADS-115
ADS-116

-

TYP.

MAX.

UNITS

o to +10

-

Volts
Volts

±10

Input Impedance
Resistance
Capacitance

15
5

-

-

7

MOhms
pF

Input Bias Current

-

±20

±500

nA

-

Logic Levels:
Logic 1
Logic 0
Logic Loading:
Logic 1
Logic 0
SAMPLE/HOLD
SPECIFICATIONS
Slew Rate
Aperture Delay Time
Aperture Uncertainty
(Jitter)

5

2.0
-

-

-

0.8

Volts
Volts

-

2.5
-100

itA
itA

MIN.

TYP.

MAX.

UNITS

-

90
20

-

V/ltSec.
nSec.

-

±100

-

pSec.

S/H Acquisition Time
to 0.048% (10V step)

-

-

500

nSec.

Sinusoidal Input

-

-

395

nSec.

APPLICATIONS
High-speed Data Acquisition and Control
Systems
Array Processing, Vibration and Resonance/
transient Analysis
Medical Imaging and Scanning
Communications Signal Processing
Spectrum and Noise Analyzers
Video Processing Systems

1-230

Integral Nonlinearity
+25°C
0°Cto+70°C
-55°C to +125 °C
Integral Nonlinearity
Tempco
Differential Nonlinearity
+25°C
o OCto +70 °C
-55°C to +125 °C

MIN. TYP.

-

MAX.

UNITS

-

-

±1/2
±1/2
±1

LSB
LSB
LSB

-

-

±10

ppm/DC

-

-

-

-

±1/2

±1/2
±1/2
±3/4

LSB
LSB
LSB

Differential Nonlinearity
Tempeo

-

-

±7.5

ppm/DC

Full·Scale Absolute
Accuracy
+25°C
o°C to +70 °C
-55°C to +125 °C

-

±2
±4
±8

±6
±9
±15

LSB
LSB
LSB

-

±t/4

±1

LSB

-

±13

±25

ppm/oC

±2

±5

LSB

ADS·tt5
Unipolar Zero
Error, +25 °C
Unipolar Zero
Error
Tempco
ADS·116
Bipolar Offset
Error, +25 °C
Bipolar Offset
Error Tempco
Bipolar Zero Error,
+25°C
Bipolar Zero Error
Tempco

-

±17.5

±35

ppm/DC

-

±1/4

±1

LSB

-

±13

±25

ppm/DC

Gain Error

-

±2

±5

LSB

Gain Error Tempco

-

±17.5

±35

ppm/DC

No missing codes
(For 12 binary bits)

Guaranteed over operating temperature
range.

OUTPUTS

MIN. TYP.

Logic Levels:
Logic 1
Logic 0

2.4
-

9.98

Logic Loading:
Logic 1
Logic 0
Internal Reference:
+Voltage, +25 0 C
Tempco
External current
Output Coding:
ADS·115
(Pin 7 High)
(Pin 7 Low)
ADS·tI6
(Pin 7 High)
(Pin 7 Low)

-

MAX.

UNITS

-

-

-

0.4

Volts
Volts

-

-160
6.4

itA
rnA

10
±5

10.02
±30
1.5

Volts dc
ppm/DC
mA

-

Straight binary
Complementary binary
Offset binary
Complementary offset binary

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADS-115,
MIN.

TW.

MAX.

lHIS

Conversion Rate:
+25°C
o OCto +70 °C
·55 °C to +125 °C

1
1
1

-

-

-

-

MHz
MHz
MHz

AID Conversion Time:
o OCto +70 °C
·55 °C to +125 °C

-

-

480
510

nSec.
nSec.

·55
-52

-60
-56

-

dB
dB

-55
-52

-60
-56

-

dB
dB

-55
-52

-60
-56

-

dB
dB

DYNAMIC
PERFORMANCE

Total Harmonic
Distortion:
DC to 110 KHz,
(Vin = <5V pk-pk)
+25°C
-55°C to +125 °C
DC to 60 KHz,
(Vin = 10V pk-pk)
+25°C
-55°C to +125 °C
DC to 30 KHz,
(Vin = 20V pk-pk)
+25°C
-55°C to +125 °C

-

TECHNICAL NOTES
1. Use external potentiometers to remove system errors or
to reduce any small initial errors to zero. Use a 20K
trimming potentiometer for gain adjustment with the wiper tied to pin 32 (ground pin 32 for operation without adjustments). Use a 20K trimming potentiometer with the
wiper tied to pin 5 for zer%ffset adjustment (leave pin
5 open for operation without adjustment).
2. Rated performance requires using good high frequency
circuit board layout techniques. The analog and digital
grounds are not connected internally. Avoid groundrelated problems by connecting the digital and analog
grounds to one point, the ground plane beneath the
converter.
Do not connect these grounds together at the power supply terminals when the power supplies are located some
distance from the ground plane. Due to the inductance
and resistance of the power supply return paths, return the analog and digital ground separately to the
power supplies. This prevents contamination of the analog ground by noisy digital ground currents.
3. Bypass all the analog and digital supplies to ground with
a 4.7/LF, 25V tantaium electrolytic capacitor in parallel
with a O.I/LF ceramic capacitor. Bypass the +10V reference (pin 1) to ground (pin 16) also using a 4.7/L F, 25V
capacitor. The -5V dc supply is treated as an analog supply and analog ground (pin 16) should be treated as its
return path for decoupling purposes.
4. Obtain straight binary/offset binary output coding by tying
the COMP BIN signal (pin 7) to +5V dc or leaving it open.
The device has an internal pull-up resistor on this pin.
To obtain complementary binary or complementary offset binary output coding, tie the COMP BIN pin to
ground. The COMP BIN signal is compatible to CMOS/
TTL logic levels for those users desiring logic control of
this function.

ADS-116

TYP.

MAX.

UNITS

Power Supply Range
+15V dc Supply
+14.25
-15V dc Supply
-14.25
+5V dc Supply
+4.75
-5V dc Supply
-4.75

+15
-15
+5
-5

+15. 75
-15.75
+5.25
-5.25

Voltsdc
Voltsdc
Voltsdc
Voltsdc

Supply Current
+15V Supply
-15V Supply
+5V Supply'
-5V Supply

+40
-30
+56
-173

+54
-40
+90
-210

mA
mA
mA
mA

2.2

2.7
±0.01

Watts
%FSR/%V

POWER
REQUIREMENTS

MIN.

Power Dissipation
Supply Rejection
PHYSICAL!
ENVIRONMENTAL
Operating Temperature Range
MC Models
MM Models
Storage Temperature Range
Weight
Package Type
Pin Type

MAX.

UNITS

0
-55

+70
+125

°C
°C

-65

+150
0.42(12)

°C
oz. (gram)

MIN.

TYP.

•

32-pin hermetically sealed ceramic DIP
0.010 x 0.018 inch Kovar

• + 5V power usage at I TIL logic loading per data output bit.
5. An overflow signal, pin 8, indicates when analog input signals are below or above the desired full-scale range. The
overflow j:1in also has a three-state output and is enabled
by pin 10 (Enable bits 1-5 & O.F.).
6. The S/H Control signal, pin 17, goes low following the rising
edge of a start convert pulse and high 30 nanoseconds
minimum before EOC goes low. This indicates that the converter can accept a new analog input.
7. Full-scale absolute accuracy refers to the unadjusted performance of the ADS-115/116. These figures may be improved substantially using external trim circuits.

THEORY OF OPERATION
This theory of operation describes the ADS-115/116's function
in conjunction with its internal Sample/Hold amplifer for digitizing sinusoidal signals. The ADS-115/116 employs a subranging
AID conversion architecture with digital error correction. Also
known as a two-step conversion method, this technique uses a
single 7 -bit flash AID converter twice in the conversion process
to yield a final resolution of 10 bits. Refer to the connection diagram, the block diagram, and the timing diagram as needed.
The ADS-115/116 guarantees a 1 MHz throughput rate when
the START CONVERT pulse of 50 nanoseconds is provided at
a 1 MHz rate. The 1 MHz rate is based upon sinusoidal input frequencies up to those specified in the harmonic distortion specifications. The acquisition time for pulse or dc level signals is
longer and listed under the acquisition specifications (10V
step).
The ADS-115/116 is io..the sample mode when the S/H CONTROL pin is high (S/H is in high-state on power-up). The
START CONVERT pulse should be given at a time delay equal
to the desired acquisition time minuli...the 10 nanosecond delay
from START CONVERT high to S/H CONTROL low. This

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-231

ADS-115,

ADS-116

THEORY OF OPERATION (Cont.)
assures the sample-hold has the minimum required acquisition
time for the particular application mode. Sinusoidal inputs being digitized by using a repetitive START CONVERT pulse will
automatically give the appropriate acquisition time when continuously sampling.
Upon going into the hold mode, there will be a 75 nanosecond
delay before EOC goes high and the AID conversion begins.
This consists of the remaining 40 nanoseconds of the START
CONVERT (10 nanoseconds is part of the acquisition time)
and a 35 nanosecond maximum delay from START CONVERT
low to EOC high. The hold mode settling time and input settling time requirements required are met by observing this timing.
After conversion is initiated, switch Sl of the ADC closes and
S2 opens. The analog input, having been configured for the
appropriate input range, is buffered and then digitized by the
7 -bit flash ADC to determine the seven most significant bits.
The seven bits of data are then stored in a register and provided to the input of a 7-bit digital-to-analog converter. This DAC
has 13 bits of linearity.
When the first pass finishes, S2 closes and Sl opens. The
output of the DAC is then subtracted from the analog input.
The result is a voltage difference between the first 7-bit digitization and the analog input. This voltage difference is amplified and converted by the 7-bit ADC. The result of this second
conversion is then latched to determine the least 7 significant
bits. The outputs from the two registers are then combined by
the digital correction logic to produce a 1O-bit word. EOC goes
low indicating the conversion is complete, and the output
passes to three-state output buffers.

puts consists of 355 nanoseconds from EOC low to START
CONVERT high (logic delays and S/H control going low 30
nanoseconds earlier included), 50 nanoseconds for the hold
and input settling time, and 500 nsec for the conversion process. The Sample/Hold control pin saves 30 nanoseconds by
allowing the S/H to return to the sample mode 30 nanoseconds before the conversion is complete.
Combining the AID and S/H in one device guarantees a total
throughput of 1.0 microsecond maximum over the -55 °C to
+ 125 OC temperature range for the complete system or a
throughput rate of 1 MHz. Retriggering the START CONVERT
pulse before ~ goes low will not initiate a new conversion.
The practical results of this means that single-channel (nonmultiplexed) full-scale inputs with spectral content not exceeding 60 KHz for 10V peak-peak signals may be digitized up
to a 1 MHz rate. This will give about 16 data samples per cycle
to la-bit accuracy and linearity. This type of resolution is ideal
for capture of signals with a broad spectral content of 60 KHz
and below (10V peak-to-peak signals). Because many samples may be taken in a short sampling interval, the ADS-115/
116 are ideal for computer-aided spectral analysis of a complex-frequency signal. The la-bit performance is ideal for larger fast fourier transform sizes of 256 to 1024 pOints by reducing frequency binning resolution noise.
For multi-channel multiplexed signals, the very high multiplexing rate allows larger numbers of channels while still retaining
moderate bandwidth per channel. Users requiring higher input
bandwidth or faster acquisition times should review Datel's
ADS-.21 or ADS-22 Sampling AID converters.
Table 1.

ADC-115, ADC-116 Timing Specifications

TIMING

Once the second step of the flash ADC is finished, the analog
input can change ~ though the conversi.Qn cycle has not
been completed (EOC go[ngJow). The S/H Control output
goes high shortly before EOC goes low, indicating that the
Sample/Hold is back sampling the input. This feature improves
the overall throughput of the ADS-115/116.

Start Convert Pulse
Width:
Start Convert Low
to EOC High Delay
Start Convert Low
to Previous Data
Invalid
Data Valid Before
EOC Goes Low
Enable to Output
~ Valid Delay
EOC Low to Start
Convert High
(Sinusoidal Inputs)

Data from the previous conversion is valid up to 275 nanoseconds after the falling edge of the START CONVERT pulse.
Data from the new conversion is valid a minimum of 25 nanoseconds before the EOC goes low and valid up to 275 nanoseconds after the falling edge of the next START CONVERT
pulse. There is a 10 nanosecond maximum delay after the
three-state output buffers are enabled before the data is valid
at the device output.
The overall throughput of the ADS-115/116 for sinusoidal in-

MIN.

TYP.

MAX.

UNITS

50

-

-

nSec.

20

-

35

nSec.

275

-

-

nSec.

25

-

-

nSec.

-

-

10

nSec.
nSec.

355

-

Note: Table 1 applies over the operating temperature range
and over the operating power suply range.

ANALOG 'NPUT ~

,~,~-=~~~1~OO~"~S~~~~~~~~U~~,~~PU,UT~P~EA,A'~OD~===;·fi---I

STAAT CONVEATIIN

------l:-----!
I

SIR CONTROL OUT __-"iS~",M"-,PL",E,<;-,

,,,

,

I

AID EGe OUT

IL'---------i~

NOTES:
1. Drawing is not to scale

I

35 nS max

,
I

20 nS min

,~

30 nSec min

,
I

Figure 2.

ADC-115, ADC-116
Timing Diagram

OUTPUT DATA ________......::D::::":.:.A.;.:,N•.:.'.::.VA;::LI=-D______+-~ST.':'!;-=DA.:cJA.:..:N.:..V.::.A=LlD

loe lOMAA87

1-232

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADS-115,

ADS-116

OV'AFCOW OU' 30B}

BtT lOUT (MSB)

3

ANA INPUT HI

BIT 2 OUT

29

HI

BIT 3 OUT

28

BITS

81T 4 OUT

27

BIT 5 OUT

ADS-116
""60U'
81T 7 OUT
31

~ART CONVERT

BIT 8 OUT

"l
26

24

23

BIT 9 OUT

22

im to OUT (LSB)

21

ENABLE LO BITS IN

9

EOC OUT

18

ZERO/OFFSET

ADJ IN

LO

aiTS

Figure 3_ ADS-116 Typical External Connections, ± 10V dc
SYSTEM CALIBRATION PROCEDURE
Remove system errors or the small initial errors as follows:
1. Connect the converter per Figure 3 and Table 2 for the appropriate full-scale input range (FSR). The data outputs
should be connected to LED's to observe the resulting data
values.
Table
INPUT VOLTAGE
RANGE
Oto +10V dc
±10V dc

2_

Input Connections

INPUT
PIN

JUMP PIN 2
TO PIN:

3
3

No connection
1 (+10VRef.)

For bipolar operation, adjust the potentiometer such that
the code flickers equally between 10 0000 0000 and 10
0000 0001 with the COMP BIN tied high or between 01
11111111 and0111111110withCOMPBINtiedlow.
3. Full Scale Adjustment:
Set the output of the voltage reference used in step 2 to the
value shown in the Tables 3 and 4 for the unipolar or bipolar
gain adjustment (+F.S. -1 1/2 LSB) for the appropriate FSR.
Adjust the gain trimming potentiometer so that the output
code flickers equally between 11 1111 1110 and 11 1111
1111 for COMP BIN (pin 7) tied high or between 00 0000
0001 and 00 0000 0000 for COMP BIN tied low.
To confirm proper operation of the device, vary the
precision reference voltage source to obtain the output
coding listed in the Tables 5 and 6.

Apply a pulse of 50 nanoseconds minimum to the START CONVERT input (pin 31) at a rate of 500 KHz. This rate is chosen to
reduce flicker if LED's are used on the outputs for calibration
purposes.
2. Zero Adjustments:
Apply a precision voltage reference source between the analog input (pin 3) and analog ground (pin 16). Use a very lownoise signal source for accurate calibration.
Adjust the output of the reference source per Tables 3 and
4 for the unipolar zero adjustment (+ 112 LSB) or the bipolar
zero adjustment (zero + 1/2 LSB) for the appropriate full
scale range. For unipolar operation, adjust the zero trimming
potentiometer so that the output code flickers equally between
00 0000 0000 and 00 0000 0001 with the COMP BIN (pin 7)
tied high or between 11 1111 1111 and 11 1111 1110 with
COMP BIN tied low.

Table 3_ Zero and Gain Adjust for Unipolar Use
RANGE

ZERO ADJUST

UNIPOLAR FSR
a to+10V

Table 4_

(+1/2 LSB)
+4.88 mV dc

GAIN ADJUST
(+FS -1 112 LSB)
+9.9927V dc

Zero and Gain Adjust for Bipolar Use

RANGE
BIPOLAR FSR
±10V

ZERO ADJUST GAIN ADJUST
(+1/2 LSB)
+9.77 mV

(+FS -1 1/2 LSB)
+9.9707 V

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

1-233

ADS-115,

ADS-116
Table 5.
UNIPOLAR
SCALE

Output Coding for Uniplar Operation

INPUT RANGE

o to
+FS - 1 LSB
FS
FS
FS
FS
FS
1 LSB
0
7/8
3/4
1/2
1/4
1/8

+10V

MSB

+9.99023V
+S.750V
+7.500V
+5.000V
+2.500V
+1.250V
+0.00977V
O.OOOOV

1111
1110
1100
1000
0100
0010
0000
0000

Table 6.
BIPOLAR
SCALE

1111
0000
0000
0000
0000
0000
0000
0000

LSB

MSB

11
00
00
00
00
00
00
00

0000
0001
0011
0111
1011
1101
1111
1111

LSB
0000
1111
1111
1111
1111
1111
1111
1111

00
11
11
11
11
11
11
11

Output Coding for Bipolar Operation

INPUT RANGE

+FS - 1 LSB
+3/4 FS
+1/2 FS
0
-1/2 FS
-3/4 FS
-FS + 1 LSB
-FS

OUTPUT CODING
Straight Binary
Complementary
Straight Binary

OUTPUT CODING
Offset Binary
Complementary
Offset Binary

± 10V

MSB

+9.9S05V
+7.5000V
+5.0000V
O.OOOOOV
-5.0000V
-7.5000V
-9.9S05V
-10.000V

1111
1110
1100
1000
0100
0010
0000
0000

1111
0000
0000
0000
0000
0000
0000
0000

LSB

MSB

LSB

11
00
00
00
00
00
00
00

0000 0000 00
0001 1111 11
0011 1111 11
0111 1111 11
1011111111
1101 1111 11
1111 1111 11
1111 1111 11

ORDERING INFORMATION
ADS-115
ADS-116
MODEL

ADS-115MC
ADS-116MC
ADS-llSMM
ADS-116MM

1a-Bit, 1 MHz
Sampling AID Converters
TEMPERATURE INPUT VOLTAGE
RANGE
RANGE

a OCto +70 °C

a to +10V

0°Cto+70°C
-55 °C to +125 °C
-55°C to +125 °C

a to + 10V

-10 to +10V
-10 to + 10V

Trimming Potentiometer:
TP 20K (2 required)
A receptacle for PC board mounting can be ordered through AMP
Incorporated, #3-331272-S (Component Lead Socket), 32 required.
For high-reliability versions of the ADS-115/-116, contact DATEL.

1-234

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADS-125, ADS-126
12-81T, 700 KHz, LOW-POWER
SAMPLING AID CONVERTERS

•

FEATURES
• 12-Bit resolution
Internal Sample/Hold
700 KHz minimum throughput
15Mohm input impedance
Pin-programmable input ranges
Low-power, 2.1 Watts
Three-state output buffers
Small 32-pin DIP

GENERAL

DESCRIPTION

DATEL's ADS-125 and ADS-126 are 12-bit,
sampling AID converters with a 700 KHz
minimum throughput rate for sinusoidal inputs.
The performance of these converters is
based upon a digitally-corrected subranging architecture. DATEL further enhances
this technology by using unique laser trimming schemes. The ADS- i 25 and ADS-126
are packaged in 32-pin ceramic DIP's and
consume 2.1 Watts.
Input impedance to the sample-and-hold for
these devices is 15 Mohms. Both the ADS125 and the ADS-126 have two pin programmable input voltage ranges. The ADS125 has ranges of ±1 OV and 0 to 10V while
the ADS-126 has ranges of ±2.5V and 0 to
5V. All digital inputs and three-state outputs are TIL- and CMOS-compatible. Output coding can be in two's complement,
complementary two's complement, straight
binary/offset binary or complementary binary/complementary offset binary ..

Figure 1. ADS-125, ADS-126 Simplified Block Diagram
I/O CONNECTIONS
MECHANICAL DIMENSIONS
INCHES (mm)

I

1.101M~

--(28,0)

I

0.190 MAX

~0.010 X 0.018
KOVAR Pins

The power requirements are ±15V dc and
+5V dc. These parts are available in the
commercial 0 degrees Celsius to +70 degrees Celsius and military -55 degrees Celsius to +125 degrees Celsius operating
temperature range.

~

! (4t

0.150 MIN.
(3,8)

T
15
SPACES
AT 0.100
(2,5)

Typical applications include spectrum,
transient, vibration and waveform analysis.
This device is also ideally suited for radar,
sonar, video digitization, medical instrumentation and high-speed data acquisition
systems. For information on high reliability
screening, contact the factory.

32

1
1.712 MAX.
(43,5)

--bL

0.900
(22,9)
NOTE: Pins have a 0.025 inch, ±0.01
stand·off from case.

PIN

FUNCTION

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Bit 12 OUT (LSB)
Bit 11 OUT
Bit 10 OUT
Bit90UT
Bit 8 OUT
Bit 7 OUT
Bit60UT
Bit50UT
Bit 4 OUT
Bit30UT
Bit 2 OUT
Bit 1 OUT (MSB)
Bit 1 OUT (f.iISB)
EfJAB['E

DIGITAL GND.
+5V
COMPBIN
REF. OUT (+ 1OV dc)
OFFSET ADJUST

me

START CONVERT
DO NOT CONNECT
DO NOT CONNECT
INPUT HIGH
BIPOLAR OFFSET
INPUT LOW
GAIN ADJUST
+15V
SIR OUTPUT
SIR INPUT
-15V
ANALOGGND.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

1-235

ADS-125,

ADS-126

ABSOLUTE MAXIMUM RATINGS
PARAMETERS

LIMITS

o to +18

+15V Supply (Pin 28)
·15V Supply (Pin 31)
+5V Supply (Pin 16)

Oto-18
-0.5 to +7.0

Digital Inputs
(Pins 14,17,21)
Analog Input (Pin 30)
Lead Temp. (10 sec.)

-0.3 to +6.0
-15to+15
300 max.

UNITS

OUTPUTS

Volts de
Volts de
Volts de

Resolution
Output Coding:
(Pin 17 Hi)
(Pin 17 Low)

°C

Apply over the operating temperature range and over the operating
power supply range unless otherwise specified.

Input Voltage Range:
ADS-125
ADS-126
Input Impedance
Input Capacitance

MIN.

5.0

-

TYP.
±10

oto +10
±2.5
Oto+5
15.0
3

MAX.

5

UNITS
Voltsdc
Volts dc
VoHs de
Volts dc
Mohms
pf

DIGITAL INPUTS
Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"

2.0

-

-

-

-

0.8
2.5
-100

-

Volts de
Volts de

J.1A
J.1A

A/D PERFORMANCE
Integral Non-Linearity
+25°C
O°Cto +70 °C
-55°C to +125 °C
Integral Non-Lln. Tempeo.
Differential Non-LineariIy
+25°C
o °C to +70 °C
-55°C to +125 °C
DiHerenllal Non-Lin. Tempeo.
Full Scale Absolute
Accuracy
+25°C
o °C to +70 °C
-55°C to +125 °C
Unipolar Zero Error,
+25°C
Unipolar Zero Tempco
Unipolar Zero Adlust Range
Bipolar Zero Error,
+25°C
Bipolar Zero Tempco
Bipolar Zero Adjust Range
Bipolar Offset Error,
+25°C
Bipolar Offset Tempco
Bipolar OOSet Adlust Range
Gain Error, +25 °C
Gain Tempco
Gain Error AdjuSI Range

-

-

-

-

-

-

±5

-

-

-

±1/2
±1/2
±3
±10

LSB
LSB
LSB
ppm/oC

±1/2
±1/2
±1
±2.5

LSB
LSB
LSB
ppm/oC

Logic Levels
Logic "1"
Logic "0"
Logic Loading "1"
Logic Loading "0"

2.4

-

-

Internal Reference
Voltage, +25 °C
Drift
External Current

9.98

-

±5
±6
±10

±10
±18
±32

LSB
LSB
LSB

-

MAX.

UNITS

-

10.0
±5

-

0.4
-160
6.4

Volts de
Volts dc

J.1A

rnA

10.02
± 30
1.5

Voltsdc
ppm/DC

rnA

SAMPLE/HOLD PERFORMANCE

-

90
20
±100

-

-

V/IlSec
nSee
pSec

-

-

-

715
765
900
395

nSec
nSec
nSec
nSec

+14.25
-14.25
+4.75

+15.0
-15.0
+ 5.0

+15.75
-15.75
+ 5.25

Volts dc
Volts de
Volts de

-

+ 70
- 52
+ 66
2.1

+ 82
- 61
+ 71
2.4
0.01

rnA
rnA
rnA
Watts
%FSR/%V

-

+70
+125
+150

°C
°C
°C

Slew Rate
Aperture Delay Time
Aperture Uncertainty
S/H Acquisition Time
to 0.01% (10V step)
+25°C
o °C to +70 °C
-55°C to +125 °C
(Sinusoidal Input)
POWER REQUIREMENTS
Power Supply Range:
+ 15V dc Supply
-15V de Supply
+5V dc Supply
Power Supply Current
+15V dc Supply
-15V dc Supply
+5V dc Supply'
Power Dissipation
Power Supply Rejection

-

-

PHYSICAL/ENVIRONMENTAL
Operating Temp. Range

-

TYP.

12 Bits
Straight binary/offset binary
Complementary binary
Complementary offset binary
Two's complement
Complementary Two's complement

(Note 4)

Volts de
Volts de

FUNCTIONAL SPECIFICATIONS

ANALOG INPUTS

MIN.,

-MC
-MM
Storage Temperalure Range

0
- 55
- 65

-

±3
±15

±5
±30

±5

-

-

LSB
ppm/oC
LSB

Package Type
Pins
Weight

-

±3
±5

±5

LSB
ppm/oC
LSB

• +5V power usage at 1 TIL logic loading per data output bit.

-

±5
±8

-

±4
±20

±8
± 40

-

±4
± 20

±5

-

±8
±40

-

LSB
ppm/oC
LSB
LSB
ppm/DC
LSB

-

-

800
850
880

nSec.
nSec.
nSec.

±5

-

-

32-Pin hermetic sealed, ceramic DIP
0.010 x 0.018 inch Kovar
0.42 ounces (12 grams)

Conversion Times:
+25°C
o °C to +70 °C
-55°C to +125 °C
No Missing Codes
(12 Bits)

1-236

-

Over the Operating Temp. Range.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

ADS-125,

ADS-126

----------------------------------------------------~r:i=~:~~M~~~~--=i4==~:------------------------------------------

,,
,,

I

'I

I

:

[OC

: I :

I

I

I

t

---1

I

I

I

I

iH-

I

I

I,
----+'- - j

I

I

:

I i1
I
- 'I

I

3950 Sec ACQUISITION TIME (SINUSOIDAL INPUTS)

MAXIMUM

I

:1
:
, 1 I
I

f--

'--_ _--+!.....I ....: _ - - '

I

"",ERNA,,S,H

I

I

!

'

!-I:

:

I

•

, --ll-- "" ,~S" "'N'''U''
l;.JJ : .

C6~AV~TRT -+______---1~;

1+~

I I

i

I

------j
~

20 nSe( MINIMUM
JJnSp( MAXIMUM

I

WnSp, MINIMUM

2'1 "S('(

_

I

L

-I

MA~IMlJM

[-

~r----"--'I,+-!_______-=---1---,I

~

OUTPUT DATA

~

-I

OM'N"''')

F

LNABI (OOATA N 1 VALID

""""

ENABL l D DATA N

IOnS",

_

MAXIMUM

VALID

Figure 2. ADS·125, ADS·126 TIMING DIAGRAM

TECHNICAL NOTES

INPUT CONNECTIONS
Table 2a. ADS·125 Input Connections

1. Use external potentiometers to remove system errors or
the small initial errors to zero. Use a 20K Ohm trimming
potentiometer for gain adjustment with the wiper tied to pin
27 (ground pin 27 for operation without adjustments). Use
a 20K Ohm trimming potentiometer with the wiper tied to
pin 19 for zer%ffset adjustment (leave pin 19 open for operation without adjustment).
2. Rated performance requires using good high-frequency
circuit board layout techniques. The analog and digital
grounds are not connected internally. Avoid groundrelated problems by connecting the digital and analog
grounds to one point, the ground plane beneath the converter (versus at the power supply terminals when the power supplies are located some distance from the ground
plane). Due to the inductance and resistance of the power
supply return paths, return the analog and digital ground
separately to the power supplies. This prevents contamination of the analog ground by noisy digital ground currents.
3. Bypass the analog and digital supplies and the + 1OV reference (pin-18) to ground with a 4.7 JlF, 25V tantalum electrolytic capacitor in parallel with a 0.1 JlF ceramic capacitor.
Bypass the + 1OV reference (pin 18) to analog ground (pin
32).

INPUT RANGE

TIE TOGETHER

INPUT PIN

Bipolar
± 10Vdc

Pin 30

tie Pin 29 to Pin 24
tie Pin 18 to Pin 25

Unipolar
o to +10V dc

Pin 30

tie Pin 29 to Pin 24
tie Pin 24 to Pin 25

Table 2b. ADS·126 Input Connections
INPUT RANGE

INPUT PIN

TIE TOGETHER

Bipolar
±2.5V

Pin 30

tie Pin 29 to Pin 24, &
tie Pin 25 to Pin 18

Unipolar
Oto +5Vdc

Pin 30

tie Pin 29 to Pin 24
tie Pin 25 to Pin 26

Table 3a. Zero and Gain Adjust for Unipolar Operation
UNIPOLAR FSR

oto +5V dc
o to +10V dc

ZERO ADJUST
+ 1/2 LSB
+0.61mV dc
+1.22mV dc

GAIN ADJUST
+FS· 1 1/2
LSB
+4.9982V dc
+9.9963V dc

Table 3b. Zero and Gain Adjust for Bipolar Operation
4. Obtain straight binary/offset binary output coding by tying
CaMP BIN (pin 17) to +5V dc or leaving it open. The device has an internal pull-up resistor on this pin. To obtain
complementary binary or complementary offset binary output coding, tie the CaMP BIN pin to ground. The CaMP

BIPOLAR FSR
±2.5V dc
±10V dc

ZERO ADJUST
o + 1/2 LSB
+0.61mV dc
+2.44mV dc

GAIN ADJUST
+FS· 1 1/2
LSB
+2.4985V dc
+9.9927V dc

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-237

ADS-12S,

ADS-126

users desiring logic control of this function. In the bipolar
mode, two's complement or complement~o's complement
~ut coding is available by using the MSB output (pin 13).
fVfSB (pin 13) does not have a three-state output.
5. The three-state outputs are enabled by connecting ENABLE
(pin 14) to a logic "0" (low). MSB (pin 13) does not have a
three-state output and therefore is not controlled by
ENABLE.

TIMING
Figure 2 shows the relationship between the various input
signals. The timing shown in Table 1 applies over the operating
temperature range and over the operating power supply range.
These times are guaranteed by design.

Table 1. Signal Timing Summary

ment and complementary two's complement requires the use
of MSB versus MSB as given for offset binary or complementary offset binary respectively.
3. Full-Scale Adjustment
Set the output of the voltage reference used in step 2 to the
value shown in Table 3a or 3b for the unipolar or bipolar gain
adjustment (+FS -1 1/2 LSB) for the appropriate FSR. Adjust
the gain trimming potentiometer so that the output code flickers equally between 1111 1111 1110 and 1111 1111 1111 for
COMP BIN (pin 17) tied high or between 0000 0000 0001 and
00000000 0000 for COMP BIN pin tied low. Two's Complement and Co~mentary Two's Complement respectively requires using MSB versus MSB.
4. To confirm proper operation of the device, vary the precision
reference voltage source to obtain the output coding listed in
Tables 4 and 5.

Table 6. Dynamic Performance

LINE

DURATION IN
NANOSECONDS
200 nSec. minimum

START CONVERT Low to EOC
High Propagation Delay

35 nSec. maximum

START CONVERT Low to Previous
Output Data Invalid

350 nSec. minimum

Data Valid Before EOC
goes Low

25 nSec. minimum

ENABLE to Output Data Valid
Propagation Delay

10 nSec. maximum

EOC Low to START CONVERT High
(Sinusoidal Inputs)

355 nSec. minimum

PROCEDURE

Removal of system errors or the small initial errors is accomplished as follows:
1. Connect the converter per Figure 3 and Table 2 for the appropriate full-scale range (FSR). Apply a pulse of 200 nanoseconds minimum to the START CONVERT input (pin 21) at a rate
of 500 KHz. This rate chosen to reduce flicker if LED's are
used on the outputs for calibration purposes.
2. Zero Adjustments
Apply a precision voltage reference source between the analog input and ground, refer to Table 2 for input pin. Adjust the
output of the reference source per Tables 3a and 3b for the
unipolar zero adjustment (+ 1/2 LSB) or the bipolar zero adjustment (zero +1/2 LSB) for the appropriate FSR. For unipolar, adjust the zero trimming potentiometer so that the output
code flickers equally between 0000 0000 0000 and 0000 0000
0001 with the COMP BIN (pin 17) tied high (Straight Binary) or
between 1111 1111 1111 and 1111 1111 1110 with the COMP
BIN pin tied low (Complementary Binary).
For bipolar operation, adjust the potentiometer such that the
code flickers equally between 1000 0000 0000 and 1000 0000
0001 with COMP BIN (pin 17) tied high (offset binary) or between 0111 1111 1111 and 0111 1111 1110 with COMP BIN
(pin 17) tied low (complementary offset binary). Two's comple1-238

MIN

TYP

MAX UNIT
S

(Sinusoidal Inputs)

START CONVERT
Pulse Width

CALIBRATION

Throughput Rate
+25°C
DoC to +70 °C
-55°C to +125 °C

700
670
650

KHz
KHz
KHz

AID Conversion Time
+25°C
OCto +70 °C
-55°C to + 125 °C

800
850
880

o

nSec
nSec
nSec

Total Harmonic Distortion
DC to 100 KHz at Vin = <5V pop -65
DC to 60 KHz at Vin = 10V pop -65
DC to 25 KHz at Vin = 20V pop -65

-70
-70
-70

dB
dB
dB

The performance characteristics shown in Table 6 apply over the
operating temperature range and over the operating power supply range unless otherwise specified. These characteristics are
guaranteed by design.

THEORY OF OPERATION
This theory of operation describes the ADS-125/126's function in
conjunction with its internal sample-and-hold amplifier for digitizing sinusoidal signals. The ADS-125/126 employs a subranging
AID conversion architecture with digital error correction. Also
known as a two-step method of conversion, this technique uses
a single 7-bit flash converter twice in the conversion process to
yield a final resolution of 12 bits. Refer to the connection diagram, block diagram, and timing diagram as needed.
The ADS-125/126 guarantees a 650 KHz throughput rate over
the temperature range when the START CONVERT pulse of 200
nanoseconds is provided at a 650 KHz rate. The 650 KHz rate is
based upon sinusoidal input frequencies up to those specified in
the harmonic distortion specifications. The acquisition time for
pulse or DC level signals is longer and listed under the acquisition specifications (1 OV step).
The ADS-125/126 is in the sample mode when the S/H CONTROL
pin is high (S/H is in high-state on power-up). The START CONVERT pulse should be given at a time delay equal to the desired
acquisition time minus the 10 nanosecond delay from START
CONVERT high to S/H CONTROL low. This assures the samplehold has the minimum required acquisition time for the

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADS-125,
particular application mode. Sinusoidal inputs being digitized
by utilizing a repetitive START CONVERT pulse will automatically give the appropriate acquisition time when continuously
sampling.
Upon going into the hold mode, there will be a 225 nanosecond
delay before EOC goes high and the AID conversion begins.
This consists of the remaining 190 nanoseconds of the START
CONVERT (10 nanoseconds is part of the acquisition time) and a
35 nanosecond maximum delay from START CONVERT low to
EOC high. The hold mode settling time and input settling time reqUirements required for the first pass of the AID conversion are
met when observing this time.
After conversion is initiated, switch SI of the ADC closes and S2
opens. The analog input, having been configured for the appropriate input range, is buffered and then digitized by the 7-bit
flash ADC to determine the seven most significant bits. The seven bits of data are then stored in a register and provided to the
input of a 7-bit digital-to-analog converter. The DAC has 13 bits
of linearity.
When the first pass finishes, S2 closes and Sl opens. The output of the DAC is then subtracted from the analog input. The result is a voltage difference between the first 7-bit digitization
and the analog input. This voltage difference is amplified and
converted by the 7-bit ADC. The result of this second conversion is then latched to determine the least seven significant
bits. The outputs from the two registers are then combined by
the digital correction logic to produce a 12-bit word. EOC goes
low, indicating the conversion is complete, and the output passes to the three-state output buffers.

ADS-126

Once the second step of the flash ADC is finished, the analog
input can change even though the conversion cycle has not
been completed (EOC going lo~The Sample/Hold Control
output-.9oes high shortly before EOC goes low, indicating that
the S/H is back sampling the input. This feature improves the
overall throughput rate of the ADS-125/126.
Data from the previous conversion would be valid up to 350
nanoseconds after. the falling edge of the START CONVERT
pulse. Data from the new conversion is valid a minimum of 25
nanoseconds before EOC goes low and valid up to 350 nanoseconds after the falling edge of the next START CONVERT
pulse. There is a 10 nanosecond maximum delay after the
three-state output buffers are enabled before the data is valid at
the device output.
The overall throughput rate of the ADS-125/126 for sinusoidal
inputs consists of 395 nanoseconds for the acquisition time, 225
nanoseconds for the START CONVERT and min-max propagation delays, 880 nanoseconds for AID conversion time minus 30
nanoseconds for the SIR CONTROL pin. A throughput time of
1470 nanoseconds is obtained and a 650 KHz throughput rate
is realized.
Combining the AID and SIR in one device allows the ADS-1251
126 to guarantee a throughput rate of 650 KHz over the -55°C
to +125 °C temperature range for the comple~stem. Retriggering of the START CONVERT pulse before EOC goes low will
not initiate a new conversion.

-15V

+15V

)---"C 20K
-15V

3. ADS·125, ADS·126
CALIBRATION CIRCUIT

(LSB) BIT 12

COMP START
BTN CONV

1

EOC ENABLE

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-239

•

ADS-125,

ADS-126

UNIPOLAR
SCALE

+FS-1LSB
7/8 FS
3/4 FS
1/2 FS
1/4 FS
1/8 FS
1 LSB
0

INPUT RANGES,VOLTS de

OUTPUT CODING

oto +10V

Ot0+5V

Straight Binary
Compo Binary
MSB
LSB MSB
LSB

+9.9976V
+8.7500V
+7.5000V
+5.0000V
+2.5000V
+1.2500V
+0.0024V
O.OOOOV

+4.9988V
+4.3750V
+3.7500V
+2.5000V
+1.2500V
+0.6250V
+0.0012V
O.OOOOV

1111 1111 1111 0000 0000 0000
111000000000 0001 1111 1111
1100 0000 0000 0011 1111 1111
1000 0000 0000 0111 1111 1111
0100 0000 0000 1011 1111 1111
0010 0000 0000 1101 1111 1111
000000000001 1111 1111 1110
0000 0000 0000 1111 1111 1111

Table 5. OUTPUT CODING FOR BIPOLAR OPERATION
BIPOLAR
SCALE

INPUT RANGE
±10V de ±2.5V de

+FS -1 LSB
+3/4 FS
+1/2 FS
0
-1/2 FS
-3/4 FS
-FS +1 LSB
-FS

+9.9951 V
+7.5000V
+5.0000V
O.OOOOV
-5.0000V
-7.5000V
-9.9951 V
-10.000V

+2.4988
+1.8750
+1.2500
0.0000
-1.2500
-1.8750
-2.4988
-2.5000

OUTPUT CODING
Offset Binary
Comp Offset Binary Comp Two's Comp
Two's Comp
LSB
LSB MSB
LSB MSB
LSB MSB
MSB
1111 1111 1111
111 0 0000 0000
1100 0000 0000
1000 0000 0000
0100 0000 0000
0010 000 0000
000000000001
0000 0000 0000

0000
0001
0011
0111
1011
1101
1111
1111

0000 0000
1111 1111
1111 1111
1111 1111
1111 1111
1111 1111
11111110
1111 1111

1000 0000
1001 1111
1011 1111
11111111
0011 1111
0101 1111
0111 1111
0111 1111

0000
1111
1111
1111
1111
1111
1110
1111

0111 1111 1111
011000000000
0100 0000 0000
0000 0000 0000
1100 0000 0000
101000000000
1000 0000 0001
1000 0000 0000

ORDERING INFORMATION
MODEL NO.
ADS-125MC
ADS-126MC
ADS-125MM
ADS-126MM
ACCESSORIES
Part Number
TP20K

OPER. TEMP. RANGE
0°Cto+70°C
0°Cto+70°C
-55°C to +125 °C
-55°C to +125 °C

SEAL
Hermetic
Hermetic
Hermetic
Hermetic

Description
Trimming Potentiometers
(Two required)

Receptacle for PC board mounting can be ordered through
AMP Inc., Part # 3-331272-8 (Component Lead Socket),32 required.
For high reliability versions of the ADS-125 and the ADS-126
contact DATEL.

1-240

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADS·21AC
Low-Power, 12-Bit, 1.3 MHz
Sampling AID Converter

•

FEATURES
•
•
•
•

12-8it resolution
1.3 MHz throughput rate
StH included
Single 46-pin DIP

I

GENERAL DESCRIPTION
DATEL:s ADS-21AC Sampling Converter combines a 12-bit AID hybrid and a StH hybrid (the
ADC-SOS and SHM-4S) in one space-saving
package. The ADS-21AC functional block diagram shows the AtD conversion technique
used to achieve the 1.3 MHz throughput rate
in a conservative low-power design. Designed
and manufactured at DATEL:s modern, certified hybrid assembly facility using state-of-theart integrated circuits, the ADS-21AC provides
the highest quality and performance for signal processing applications.
The ADS-21AC's 1.3 MHz throughput rate can
typically be increased to about 1.S MHz before
any performance degradation. This superior
performance gives design engineers a highresolution, high-speed A/D capable of easily
meeting the 1.3 MHz throughput rate for many
signal processing applications.
The ADS-21AC features six pin-programmable input ranges: 0 to + 10V, 0 to -SV, 0 to
-10V, Oto -20V, ±SVand ±10V dc. The input
impedance is specified at 1.0 K ohm. Other
specifications include no missing codes over
temperature, a maximum gain tempco of
±40 ppm/oC and a maximum differential
linearity tempco of ±2.SppmtOC. Power
required by both models is +/-1SV dc and
+ /-SV dc at 2.7W maximum.
All digital inputs and three-state outputs are
TTL-compatible. Output coding can be
selected as straight binary/offset binary or
complementary binary/complementary offset
binary by using the CaMP BIN pin. An overflow pin indicates when inputs are below or
above the normal full-scale range.
Manufactured using thick-film and thin-film
hybrid technology, this converter's remarkable performance is based on a digital
subranging architecture. DATEL further
enhances this technology by using a
proprietary custom chip and unique laser trimming schemes. The ADS-21AC uses hermetically sealed hybrids packaged in a 46-pin DIP
capable of operation over the O°C to + 70°C
temperature range.
These devices are ideally suited for spectrum,
waveform, vibration, and transient analysis
applications in military and industrial
instrumentation systems. For information on
versions with high reliability screening or
extended temperature operation, contact the
factory.

ANALOG
GROUNDS

DIGITAL GROUNDS

Figure 1. ADS-21AC Functional Diagram

1.300,,------,
(3302)

PIN DIAMETER
~ 0.020
(51)

I o~o2e

2640
(671)

MAX

j

"I

go ~ ~ ~

!

0

0

g

g

0

0

g

~I_,- - - - - - ,-,g~

@::E

tn Q
is

()

~ z

~~

I~",,--l
1416)

MA<

Figure 2. Mechanical Dimensions

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-241

ADS-21AC
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
+ 15V Supply (Pin 31) . . .
-15V Supply (Pin 45). . .
+5V Supply (Pin 9)
-5V Supply (Pin 42)
Digital Inputs
(Pins 3, 10, 34)
Analog Input (Pin 39) .
Lead temp. (10 Sec.). .

MINIMUM MAXIMUM
-0.3
+ 18
+0.3
-18
-0.5
+7
+0.5
-7

UNITS
Voltsdc
Volts dc
Volts dc
Volts dc

-0.3

+5.5

-15

+ 15

Voltsdc
Volts dc

300

°C

FUNCTIONAL SPECIFICATIONS
Apply over the operating temperature range and over the operating power supply range unless otherwise specified. For test
aspects, contact the factory.
DESCRIPTION

MIN.

TYP.

MAX. UNITS

-

-

-

Oto +10
Oto -5V
Oto -10V
o to -20V
±10, ±5

-

lK
500

-

INPUTS
Input Voltage Ranges.

-

Input Impendance
Oto -10V, Oto +10V,
oto -20V, ±10V
oto -5V, ±5V ..
Logic Levels: Logic 1 .
Logic O.
Logic loading: Logic 1 .
Logic 0 .

2.0

-

-

-

-

-

0.8
2.5
-100

Volts de
Volts de
Volts de
Volts de
Volts de
ohm
ohms

Volts de
Volts de
~A
~A

OUTPUTS
Output Coding Options:

Logic Levels: Logic I .
Logic 0 ..
Logic loading: Logic 1 .
Logic O.
Internal Reference (Pin 43)
Voltage, +25°C
Drift ..
External Current (for Pin 39).

straight binary/offset binary
complementary binary
complementary offset binary
2.4
- Volts de
0.4 Volts de
-160
~A
mA
6.4
9.98

-

±5

10.02 Volts de
±30 ppm/oC
1.5
mA

-

-

-

16
300

-

MHz

-

V/~S

-

6
±50

-

nS
pS

-

60

100

nS

-

40

-

nS

-

-74
-80 below FS

-

dB
dB

-72 -80 below FS
-72 -75 below FS

-

dB
dB

-

160

200

nS

-

100

170

nS

SAMPLE MODE DYNAMICS
Frequency Response:
Small Signal (-3dB)
Slew Rate.

-

SAMPLE-TO-HOLD SWITCHING
Aperture Delay Time.
Aperture Uncertainty (Jitter)
Settling Time:
10V to ± .01% FS
(± lmV).
10V to ±.1% FS
(± 10mV).
DYNAMIC PERFORMANCE
Feedthrough Rejection ..
Signal to Noise Ratio (SNR)
Inband Harmonics
(See Fig. 6)
dc to 100KHz .
100KHz to 500KHz .......•

-72

-

HOLD-TO-SAMPLE DYNAMICS
Acquisition Time:
10V step to ±1.0mV
(.01% FS) ....•.........
10V step to ±10mV
(.I%FS) .•..........•.•

1-242

DESCRIPTION
MIN. TYP. MAX.
UNITS
PERFORMANCE FOR ±10V RANGE
Integral Nonlinearity
+25OC .
- ±0.0125 oAlFSR± V2lSB
OOC to + 7OOC ..
- ±0.0125 %FSR± 'hlSB
ppm/oC
Integral Nonlin. Tempeo ..
±3
Differential Nonlinearity:
+25OC .
±0.0125
%FSR±
V2lSB
O°C to +70°C ...
- ±0.0125 %FSR± V2lSB
ppm/oC
Differential Nonlin Tempco
±2
Full·Scaie Absol. Accuracy:
+25OC
±12
lSB
±5
OOCto +70 oC ..
lSB
±6
±15
Unipolar Zero Error, +25°C
lSB
±2
±5
ppm/oC
Unipolar Zero Tempco ..
±13
±25
Bipolar Zero Error
lSB
±5
ppm/DC
Bipolar Zero Tempco .
±13
±25
Bipolar Offset Error,
+25°C.
lSB
±2
±8
ppm/oC
Bipolar Offset Tempco .
±17
±40
Gain Error, +25°C
lSB
±3
±S
ppm/oC
Gain Tempco.
±1a
±40
Conversion Times:
+25°C
750
770
nSee
O°C to +70°C ..
825
nSee
Throughput Rate:
1.3
+25°C
MHz
O°C to +70OC ..
1.1
MHz
No Missing Codes (12 Bits):
Over the Operating Temp. Range
POWER SUPPLY REQUIREMENTS
Power Supply Range:
+ 15V de Suppiy
+14.25 +15 +15.75
Volts de
-15V de Supply
-14.25 -15 -15.75
Volts de
+5.25
+5V dc Supply
+4.75 +5
Volts de
-5V dc Supply .
-4.75 -5
-5.25
Volts de
Power Supply Current:
+15V Supply ...
+45
+60
mA
-15VSupply ..
-35
-50
mA
+5VSupply.
+65 +100
mA
-5VSupply.
-ISO -210
rnA
Power Dissipation
2.3
2.7
Watts
Power Supply Rejection.
0.01
0.05
°AlFSRV/OfoV
PHYSICAL-ENVIRONMENTAL
Operating Temp.
Range· .
0
+70
°c
Storage Temperature
Range
-65
+125
°C
Package Type .
46-pin DIP
Pins.
0.020 brass
Weight.
2 oz (50g) approx.
*For extended temperature range versions, contact the factory.

TECHNICAL NOTES
1. Use external potentiometers to remove system errors or the
small initial errors to zero. Use a 20K trimming potentiometer for gain adjustment with the wiper tied to pin 36 (ground
pin 36 for operation without adjustments). Use a 20K trimming potentiometer with the wiper tied to pin 37 for zerol offset
adjustment (leave pin 37 open for operation without adjustment).
2. Rated performance requires using good high frequencycircuit board layout techniques. The analog and digital grounds
are connected internally. Avoid ground-related problems by
connecting the digital and analog grounds to one pOint, the
ground plane beneath the converter(versus atthe powersupply terminals when the powersupplies are located some distance from the ground plane). Due to the inductance and
resistance olthe power supply return paths, return the analog and digital ground separately to the power supplies. This
prevents contamination olthe analog ground by noisy digital ground currents.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

ADS·21AC
3. Bypass all the analog and digital supplies and the +10V
reference (pin 43) to ground with a4.7JLF, 25Vtantalum electrolytic capacitor in parallel with a 0.1 JLF ceram ic capacitor.
Bypass the +10V reference (pin 43) to analog ground
(pin 30). The -5Vdc supply is treated as an analog supply
and analog ground (pins 24-30) should be treated as its
return path for decoupling purposes.
4. The COMP BIN input (pin 34) allows selection of binary/
offset binary or complementary binary/complementary offset binary. Refer to Table 2 for the desired coding selection.
The COMP BIN pin has an internal pull-up resistor and
is TTL-compatible for those users desiring logic control of
this function.

•

INPUT

ADS-21AC

5. An overflow signal, pin 33, indicates when analog input signals are below or above the desired full-scale range. The
overflow pin also has a three-state output and is enabled by
pin 10 (Enable for bits 1 through 12 and overflow.)
6. The internal Sample/Hold control signal goes low following
the rising edge of a start convert pulse and hig!130 nanoseconds minimum before EOC goes low. This S/H low signal
indicates that the converter can accept a new analog input.
-t15

Table 1. lnput/Output Connections
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

FUNCTION

PIN

NIC
DIG GND
8T ART CONVERT
DIG GND
DIG GND
EOC
DIG GND
NIC
+5V
ENABLE
NIC
BIT 1 (MSB)
BIT 2
BIT 3
81T4
BIT 5
BIT6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12(L8B)

24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

OFFSET ADJUST

FUNCTION
ANAGND
ANAGND
ANAGND
ANAGND
ANAGND
ANAGND
ANAGND
+ 15V
NIC
OVERFLOW
COMP BIN
NIC
GAIN ADJUST
OFFSET ADJUST
BIAS
INPUT
RANGE
ANAGND
-5V
+ 10V REF OUT
S/H OUT

INPUT
CONNECT
VOLTAGE INPUT PIN
RANGE
38 TO:

CONNECT
PIN 40
(RANGE) TO,

Removal of system errors or the small initial errors is
accomplished as follows:
1. Connect the converter per Figure 3 and Table 2 for the
appropriate full-scale range (FSR). Apply a pulse of
100 nanoseconds minimumto the START CONVERT input
(pin 3) at a rate of 500 KHz. This rate chosen to reduce flicker
if LED's are used on the outputs for calibration purposes.

-15V

CONNECT PIN 34 TO:

COMPo BINARYI
CONNECT PIN 34 TO:

44

-

2,4,5,7

o to -10V

-

44

-

2,4,5,7

o to

44

44

-

2.4,5,7

-20V

o to +10V
±5V

± 10V

EXT
-lOV Ref.'

44

2.4.5,7

-

39

43

2,4,5,7

-

-

43

2,4,5,7

-

• May be Referenced to + 1OV Ref. (Pin 43)

2. Zero Adjustment.
Apply a precision voltage reference source between the analog input (pin 39) and ground (pin 24). Adjust the output of
the reference source per Table 4a and 4b for the unipolar
zero adjustment (+ '/2 LSB) or the bipolar zero adjustment
(zero + '/2 LSB) for the appropriate FSR. Adjust the zer%ffset trimming potentiometer so that the output code flickers
equally between 0000 0000 0000 and 0000 0000 0001 or
between 1111 11111111 and 1111 11111110 depending on the
output coding selected per Tables 2 and 6.

COMPo OFFSET BINARY

39

a to - SV

and 41 MUST BE CON·
NECTED TO THE SAME
GROUND PLANE AS
CLOSE AS POSSIBLE
TOTHECASE

CALIBRATION PROCEDURE

NIC

BINARYI
OFFSET BINARV

NOTE'PINS2,4,5,7,24-30.

Figure 3. Connection Diagram

Table 2. Input Connections

,

20K
GAIN ADJ

For bipolar operation, adjustthe potentiometer until the displayed code flickers equally between 100000000000 and
100000000001 with COMP BIN tied high or between 0111
1111 1111 and 01111111 1110 with COMP BIN tied low. Refer to Table 5.
3. Full-Scale Adjustment.
Set the output of the voltage reference used in step 2 to the
value shown in Table 4a or 4b for the unipolar or bipolar gain
adjustment (+FS - 1'/2 LSB) for the appropriate FSR.
Adjust the gain trimming potentiometer so that the output
code flickers equally between 1111 1111 1110 and 1111 1111
1111 or between 0000 0000 0001 and 0000 0000 0000
depending on the output coding selected per Tables 2 and 4.
4. To confirm proper operation of the device, vary the precision
reference voltage source to obtain the output coding listed
in Tables 5 and 6.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-243

ADS-21AC

~
,
--------,'---------------------------------------,,
''
NOTE NOTDRAWNTOSCAlE

,

INPUT
SETTLING

I

--t- ~~~~~~~ -----'f-'--------------------------------------I

I

:
:

N

-11I
~
~
100

I

,
,,
,,
I

--j,

TEMPERATURE

;

I

I

:

-.iJ :

I

: I:

:

I

1__

I-

i-II

I

MINIMUM

~

:

IOOnSec HOLDMODESETTLINGTIME

!!: I-i·: - !: 2001lSe~
,r:
, ,II '1------------

:

ACOUISITIONTIM[

I

,,
,

ADe 500
CONVERSION
TIMErTl1

n.sec

~,--~I~--------------------------------------

I

I

I

I I

I

I

I I

,,

I

I

I

I

I

I

I

r

'I I

:-t-:
----: H-

I

Iroc

!,

T, MAXIMUM

-----------1

20 nSec MINIMUM
35 nSec MAXIMUM

1 I I
I

I

lOnSec MINIMUM

I

2SnSec MAXIMUM

~r--------~i'li

_I

L ___

r--

,""s", _ _
MINIMUM

1-

Ir-----------

i

!INTERNAL) SlH

L

JOnSel
MINIMUM

I

-----1
-I

'--___
I

~~N~~~~

----,

DATANVALID

OATA N 1 VALID

ENABLED DNA N-I VALID

F

ENABLED DATA N

1{)fl5ec
MAXIMUM

VALID

Figure 4. Timing Diagram

TIMING
Figure 4 shows the relationship between the various input signals. The timing cited in Table 3 applies over the operating temperature range and over the operating power supply range.
These times are guaranteed by design.

Table 3. Signal Timing Summary
LINE

DURATION IN NANOSECONDS

Start Convert

100 nSec maximum

Analog Input Settling Time

150 nSec minimum

Start Convert Low to EOC
High Propagation Delay

35 nSec maximum

Start Convert Low to Previous
Output Data Invalid

350 nSec minimum

Data Valid Before EOC
Goes Low

25 nSec minimum

Enable to Output Data Valid
Propagation Delay

10 nSec maximum

THEORY OF OPERATION
The sample-and-hold is used to capture fast signals for the ADC
to then digitize. The ADS-21AC consists of a fast sample-andhold device (SHM-45) coupled to a high-performance analogto-digital converter (ADC-500). Figure 5 is a detailed block
diagram showing DATEL:s SHM-45 along with the ADC-500's
internal registers and logic. The ADC-500 used in the
1-244

ADS-21AC employs a subranging architecture with digital
error correction. Also known as a two-step method of conversion, this technique uses a single 7-bit flash converter twice in
the conversion process to yield a final resolution of 12 bits. Refer
to the Timing Diagram shown in Figure 4 for further clarification.
The SHM-45 used in the ADS-21AC acquires the input signal
on the internal hold capacitor (200 nanoseconds maximum
acquisition time to 0.01%). The SHM-45 is then put into the hold
mode prior to the analog-to-digital conversion. In the hold mode,
the SHM-45 requires a maximum of 100 nanoseconds to have
its output buffer settle to 0.01% accuracy. The ADC-500
requires a maximum of 150 nanoseconds since the previous
conversion for the Input signal to settle before initiating a conversion. The input of the ADC-500 starts settling to its final value
while the SHM-45 is in the acquisition mode. The missing 50
nanoseconds of the required maximum analog input settling
time is made up by the time the samplelhold is in the acquisition mode. Thus by the end of the SHM-45's hold mode
settling time, the ADC-500's input is fully settled.
The SHM-45 is in the sample mode when the internal
ADC-500's SIR control is high. During this period of time, the
AID is not performing a conversion.
The SIR control pin goes low after the rising edge of the start
convert pulse, a minimum of 10 nanoseconds and a maximum
of 25 nanoseconds later. To assure the SHM has 200 nSec maximum acquisition time, the start convert pulse should be given
a minimum of 190 nanoseconds after the desired start of the
acquisition time. The width of the start convert pulse should be
100 nsec minimum to assure the hold mode settling time of 100
nanoseconds is observed. The 100 nanoseconds takes into

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADS-21AC

Figure 5. Detailed Block Diagram
account the min-max propagation delays of the start convert
high to S/Fi control low propagation delays and the start
convert low to EOC high propagation delays.

throughput of the ADS-21AC is a maximum of no nanoseconds
for the system for a guaranteed throughput rate of 1.3 MHz.
Retriggering of the start convert pulse before EOC goes low will
not initiate a new AID conversion.

The analog input, having been configured forthe appropriate
range, is buffered and then digitized by the 7 bit flash analogto-digital converter to determine the seven most significant bits.
The seven bits of data are then stored in a register and provided
to the input of a 7-bit digital-to-analog converter. This DAC has
13 bits of linearity.

The performance characteristics shown in Table 7 and Figure
6 apply over the operating temperature range and over the
operating power supply range unless otherwise specified.
These characteristics are guaranteed by design.

The first pass finished, internal switching occurs effectively subtracting the output of the DAC from the analog input. The result
is a voltage difference between the first 7-bit digitization and the
analog input. Thi:; voltage difference is amplified and converted
by the 7-bit analog-to-digital converter. The result of this second
conversion is then latched to determine the least 7 significant
bits. The outputs from the two registers are then added by the
digital correction logic to produce a 12-bit word. EOC goes
low, indicating the conversion is complete, and the output is
present at the three-state output buffers.

Table 4a. Zero And Gain Adjust For Unipolar Use
UNIPOLAR FSR

The overall throughput of the ADS-21AC using the ADC-500
and the SHM-45 internally consists of 200 nanoseconds for the
sample time, 100 nanoseconds for the hold and input settling
time, 15 nanoseconds for observance of min-max propagation
delays and 470 nanoseconds for the conversion process (S/Fi
control pin saves 30 nanoseconds). However, total guaranteed

GAIN ADJUST
+FS - 1V. LSB

Oto -5V

-0.61mV

- 4.9982V

010 -1OV

-1.22mV

- 9.9963V

o to
o to

-20V

-2.44mV

-19.9927V

+10V

+1.22mV

+ 9.9963V

Table 4b. Zero And Gain Adjust For Bipolar Use

Once the second step of the flash analog-to-digital converter
is finished, the analog input can change even though the conversion cycle has not been completed (EOC going low). The
internal Sample/Hold control signal line goes Iowa minimum of
30 nanoseconds before EOC goes low, indicating that the
SHM-45 can be put back into the sample mode. This feature
improves the overall throughput of the ADC-SHM system.
Data from the previous conversion would be valid up to 350
nanoseconds aiter the falling edge of the start convert pulse.
Data from the new conversion is valid a minimum of 25 nanoseconds before EOC goes low and valid up to 350 nanoconds after the falling edge of the next start convert pulse.
There is 10 nanosecond maximum delay after the three-state
output buffers are enabled before the data is valid.

ZERO ADJUST
+V. LSB

GAIN ADJUST

BIPOLAR FSR

ZERO ADJUST
ZERO +V.
LSB

±10V de

+2.44mV

+9.9927V de

±5V de

+1.22mV

+4.9963V de

+FS - 1'12 LSB

Table 5. Output Coding for Bipolar Operation
OUTPUT COMING
BIPOLAR
SCALE

INPUT RANGES
VOLTS de

OFFSET BINARY

COMPo
OFFSET BINARY

±5V

+10V

+FS-1LSB

+4.9976V

+9.99S1V

111111111111

0000 0000 0000

+ % FS

+ 3.7S00V

+ 7.S0DOV

1110 0000 0000

0001 1111 1111

+ 1f2 FS

+ 2.S000V

+5.0000V

1100 0000 0000

0011 1111 1111

O.OOOOV

O.OOOOV

1000 0000 0000

0111 1111 1111

- 112 FS

-2.S000V

- S.OODOV

010000000000

1011 1111 1111

- 3J4 FS

-3.750DV

- 7.5000V

001000000000

1101 1111 1111

- FS + 1 LSB

-4.9976V

-9.9951V

0000 0000 0001

1111 1111 1110

-FS

- 5.0000V

-lO,DOODV

0000 0000 0000

111111111111

0

MSB

LSB

MSB

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

LSB

1-245

ADS·21AC
Table 6. Output Coding For Unipolar Operation
UNIPOLAR
SCALE

INPUT RANGES
VOLTS de
010 -5V

010 -10V

010 +10V

OUTPUT CODING
STRAIGHT BINARY
010 -20V

MSB

COMPo BINARY

LSB

MSB

LSB

+FS -1 LSB
7/, FS
3(" FS

- 4.99BV

-9.9976V

+9.9976V

-19.9951V

1111

1111

1111

0000

0000

0000

-4.375V

-B.750V
-7.500V

+B.750V

-17.500V

1110

0000

0000

0001

1111

1111

-3.750V

+ 7.500V

-15.00V

1100

0000

0000

0011

1111

1111

,(, FS

-2.500V

-5.00V

+5.00V

-10.00V

1000

0000

0000

0111

1111

1111

V4 FS

-1.250V

-2.500V

+ 2.500V

-5.000V

0100

0000

0000

1011

1111

1111

'/, FS
1LSB

-0.625V

-1.250V

+ 1.250V

-2.500V

0010

0000

0000

1101

1111

1111

-0.0012V

-0.0024V

+0.0024V

-0.0049V

0000

0000

0001

1111

1111

1110

O.OOOOV

O.OOOOV

O.OOOOV

0000

0000

0000

1111

1111

1111

a

O.OOOV

SOdS

60dS

40dB

20dB

OdB

-20dB

AOS-21AC FFT Report for Total Harmonic Distortion - 500 KHz Input
100dB

SOdS

60dS

40dB

20dB

OdB

-20dB

100 KHz

300 KHz

700KHz

500 KHz

ADS-21AC FFT Report for Total Harmonic Distortion -

100 KHz Input

Figure 6. Harmonic Distortion Performance
Table 7. Performance Characteristics At
Different Temperatures
CHARACTERISTICS

VALUE

Conversion Rate (Changing Inputs):
+2SoC
O°C to + 70°C

1.3 MHz minimum
1.1 MHz minimum

Harmonic Distortion (Below ES)
+2SoC
O°C to + 70°C

- 72dB minimum
- 72dB minimum

1-246

ORDERING INFORMATION
MODEL NO.
ADS-21AC*

TEMP RANGE

THROUGHPUT
RATE
1.3MHz

·Contact factory for high reliability or extended temperature range versions.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADS-22AC
Low-Power, 12-Bit, 1.0 MHz
Sampling AID Converter
FEATURES

•
•
•
•

12-Bit resolution
1.0 MHz throughput rate
S/H included
Single 46-pin DIP

OFFSET GAIN
ADJ
ADJ

SIHOUTPur

+ lOV
REF/OUT

GENERAL DESCRIPTION
DATEt.:s ADS-22AC sampling converter combines a 12-bit AID hybrid and a S/H hybrid (the
ADC-505 and SHM-45) in one space - saving
package. The ADS-22AC functional block diagram at the right shows the A/D conversion
technique used to achieve the 1.0 MHz
throughput rate in a conservative low power
design. Designed and manufactured at
DATEt.:s modern, certified hybrid assembly
facility using state of the art integrated circuits,
the ADS-22AC provides the highest quality
and performance for signal processing
applications.
The ADS-22AC's 1.0 MHz throughput rate can
typically be increased to about 1.25 MHz
before any performance degradation. This
superior performance gives design engineers
a high-resolution, high-speed AID capable of
easily meeting the 1.0 MHz throughput rate for
many signal processing applications.
The ADS-22AC features six pin-programmable input ranges: Oto +10V, Oto -5V, Oto
-10V, 0 to -20V, ±5Vand ± 10V dc. The input
impedance is specified at 1.0 K ohms. Other
specifications include no missing codes over
temperature, a maximum gain tempco of
±40 ppm/oC and a maximum differential
linearity tempco of ±2.5ppm/oC. Power
required by both models is ± 15V dc and ±5V
dc at 2.8 W maximum.
All digital inputs and three-state outputs are
TTL-compatible. Output coding can be in
straight binary/offset binary or complementary
binary/complementary offset binary by using
the COMP BIN pin. An overflow pin indicates
when inputs are below or above the normal
full-scale range.
Manufactured using thick-film and thin-film
hybrid technology, this converter's remarkable performance is based on a digital
subranging architecture. DATEL further
enhances this technology by using a
proprietary custom chip and unique laser trimming schemes. The ADS-22AC uses hermetically sealed hybrids packaged in a 46-pin DIP
capable of operation over the O°C to + 70°C
temperature range.
These devices are ideally suited for spectrum,
waveform, vibration, and transient analysis
applications in military and industrial
instrumentation systems. For information on
versions with high reliability screening or
extended temperature operation, contact the
factory.

11

NIC

12

B!T1 (MSB)

13

BIT2

14

81T3

15

81T4

16

BIT5

17 BITS
18 BlTl
19

BlTa

20

8119

21

81TlO

22

BIT 11

'--_~.Jo+l23 BITI2(LSB)

NIC 46

'------~o{6

EOC

ANALOG

DIGITAL GROUNDS

GROUNDS

Figure 1. ADS-22AC Functional Diagram

r--I--I,mm,
1

INCHES

0.375L

~;~)

'u

U

0.)50.

(3.81)

t

1-

1,300 - - - - - - .
(33.02)

L

~~~

0

g

PIN DIAMETER
3
0.020
(.51)

"I

°olg23

2640

M1N

g

8

~

o ;; ~ ~

BOTTOM

VIEW

o

o0

" ~
CIJ

g

~~

a

~.~ ~

1

L1_'_ _ _ _ _ _"....J

L-,,,o.---l
(416)

MAX

Figure 2. Mechanical Dimensions

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-247

ADS·22AC
ABSOWTE MAXIMUM RATINGS
PARAMETERS
+ 15V Supply (Pin 31) .
-15V Supply (Pin 45).
+5V Supply (Pin 9)
-5V Supply (Pin 42)
Digital Inputs
(Pins 3, 10, 34) ....
Analog Input (Pin 39) .
Lead temp. (10 Sec.).

MINIMUM MAXIMUM
-0.3
+ 18
+0.3
-18
-0.5
+7
+0.5
-7
-0.3
-15

UNITS
Volts de
Volts de
Volts de
Volts de

+5.5
+ 15
300

Volts de
Volts de

·c

FUNCTIONAL SPECIFICATIONS
Apply over the operating temperature range and over the operating power supply range unless otherwise specified. For test
aspects, contact the factory.
DESCRIPTION

MIN.

TYP.

MAX. UNITS

INPUTS
Input Voltage Ranges .

-

-

Input Impendanee
o to -10V, Oto +10V,
oto -20V, +10V
oto -5V, ±5V .
Logic Levels: Logic 1 ..
Logic O.
Logic Leading: Logic 1 .
Logic 0 .

-

2.0

-

Oto +10
Oto -5V
Oto -10V
a to -20V
±10, ±5

-

lK
500

-

-

-

-

-

-

-

Volts de
Volts de
Volts de
Volts de
Volts de

ohm
ohms
Volts de
O.S Volts de
2.5
~
-100
~

OUTPUTS
Output Coding Options:

Logic Levels: Logic 1 .
Logic O.
Logic Leading: Logie 1 .
Logic 0 .
Internal Reference (Pin 43)

Voltage, +25°C
Drift .
External Current (for Pin 39).

straight binary/offset binary
complementary binary
complementary offset binary
2.4

-

9.9S

-

-

-

-

±5

-

-

- Volts de
0.4 Volts de
-160
~
6.4
mA
10.02 Volts de
±30 PPMf'C
1.5

mA

16
300

-

MHz

-

6
±50

-

nS
pS

-

60

100

nS

-

40

-

nS

-

-74
-SO below FS

-

-72

dB
dB

-72
-72

-SO below FS
-75 below FS

-

-

dB
dB

DESCRIPTION
UNITS
I MIN. TYP. MAX.
PERFORMANCE FOR ±10V RANGE
Integral Nonlinearity
±0.0125 %FSR± 'I2LSB
+25°C
O°C to + 70°C.
- ±0.0125 %FSR± 'I2LSB
ppm/OC
Integral Nonlln. Tempeo
±3
Differential Nonlinearity:
+2SoC
- ±0.0125 %FSR± 'I2LSB
O°C to + 700C .
- ±0.0125 %FSR± 'I2LSB
ppmfOC
Differential Nonlin Tempeo
±2.5
Full-Scale Absol. Accuracy:
+2SoC
LSB
±5
±12
LSB
±6
±15
OOC to + 70°C.
LSB
Unipolar Zero Error, +2SOC
±2
±5
ppm/oC
il3
Unipolar Zero Tempeo .
±25
LSB
&:Ipolar Zero Error
±5
ppmfoC
±13
Bipolar Zero Tempeo .
±25
LSB
Bipolar Offset Error, +25°C
:1:2
±S
ppmfoC
Bipolar Offset Tempeo .
±17
±40
LSB
Gain Error, +25°C
±3
±S
ppmfoC
Gain Tempeo.
±1S
±40
Conversion Times:
ADS-22AC.
900
nSee
l~ee
Throughput Rate:
ADS-22AC ..
1.0
MHz
No Missing Codes (12 Bits):
Over the Operating Temp. Range

-

POWER SUPPLY REQUIREMENTS
Power Supply Range:
+14.25 +15 +15.75
+ 1SV de Supply
-14.25 -15 -15.75
- 15V de Supply
+SV de Supply
+4.75 +5
+5.25
-5V de Supply .
-4.75 -5
-5.25
Power Supply Current:
+60
+ 15V Supply .
+45
-35
-50
-15V Supply .
+65
+100
+SVSupply.
-150
-210
-5VSupply.
2.3
Power Dissipation
2.7
0.Q1
Power Supply Rejection.
0.05
PHYSICAL-ENVIRONMENTAL
Operating Temp.
Range· .
0
+70
Storage Temperature
-65
+125
Range
46-pin DIP
Package Type .
0.020 brass
Pins.
2 oz (50g) approx.
Weight.

Volts de
Volts de
Volts de
Volts de
mA
mA
mA
rnA
Watts
%FSRVf%V

°C
°C

*For extended temperature range versions, contact the factory_

SAMPLE MODE DYNAMICS
Frequency Response:
Smalt Signal (-3dB) .
Slew Rate.

TECHNICAL NOTES
-

-

V/~S

SAMPLE-TO-HOLD SWITCHING
Aperture Display Time .
Aperture Uncertainty (Jitter)
Settling Time:
10V to ±.Olo/, FS
(±lmV
10V to ±.1% FS
(±10mV)
DYNAMIC PERFORMANCE
Feedthrough Rejection.
Signal to Noise Ratio (SNR)
Inband Harmonics
(see Fig 6)
de to 100KHz .
100KHz to 500KHz FS .

-

HOLD-TO-SAMPLE DYNAMICS
Acquisition Time:
10V step to ± 1.0mV
(.01% FS) ..............
10V step to ± lOmV
(.1'/0 FS) ...............

1-248

-

160

200

nS

-

100

170

nS

1. Use external potentiometers to remove system errors or the
small initial errors to zero. Use a 20K trimming potentiometer for gain adjustment with the wiper tied to pin 36 (ground
pin 36 for operation without adjustments). Use a 20K trimming potentiometer with the wiper tied to pin 37 for zero/ offset
adjustment (leave pin 37 open for operation without adjustment).
2. Rated performance requires using good high frequencycircuit board layouttechniques. Theanalog and digital grounds
are connected internally. Avoid ground-related problems by
connecting the digital and analog grounds to one pOint, the
ground plane beneath the converter (versus atthe power supply terminals when the power supplies are located some distance from the ground plane). Due to the inductance and
resistance olthe power supply return paths, return the analog and digital ground separatelytothe powersupplies. This
prevents contamination of the analog ground by noisy digital ground currents.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADS·22AC
3. Bypass all the analog and digital supplies and the +10V
reference (pin 43) ground with a 4.7/,F, 25V tantalum electroly1ic capacitor in parallel with a O.l/,F ceramic capacitor.
Bypass the + 10V reference (pin 43) to analog ground (pin
30). The -5V dc supply is treated as an analog supply and
analog ground (pins 24-30) should be treated as its return
path for decoupling purposes.
4. The COMP BIN input (pin 34) allows selection of binary/
offset binary or complementary binary/complementary offset binary. Refer to Table 2 for the desired coding selection.
The COMP BIN pin has an internal pull-up resistor and
is TTL compatible for those users desiring logic control of
this function.

l'

NIC

12 BITI (MSB)

13 81T2
INPUT

14 Bin

15 81T4

ADS-22AC

5. An overflow signal, pin 33, indicates when analog input signals are below or above the desired full-scale range. The
overflow pin also has a three-state output and is enabled by
pin 10 (Enable for bits 1 through 12 and overflow).

16 BIT5
17 BIT6
18 BIT7

19 BIT8
20 81T9
21 SlT10

22 BIT'1

6. The internal Sample/Hold control signal goes low following
the rising edge of a start convert pulse and high 30 nanoseconds minimum before EOC goes low. This siR low Signal
indicates that the converter can accept a new analog input.
+15

-15
20K
GAIN ADJ

Table 1. Input/Output Connections
PIN

FUNCTION

1
2
3
4
5
6
7
8
9
10

N/C
DIG GND
START CONVERT
DIG GND
DIG GNO
EOC
DIGGND
N/C
+5V
ENABLE
N/C
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
SlTa
BIT 9
BIT 10
BIT 11
BIT 12 (LSB)

11
12
13
14
15
16
17
18
19
20
21
22
23

PIN
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46

FUCTION

Figure 3. Connection Diagram

ANAGND
ANAGND
ANAGND
ANAGND
ANAGND
ANAGND
ANA GND
+ 15V
N/C
OVERFLOW
c-6-MP BIN
N/C
GAIN ADJUST
OFFSET ADJUST
BIAS
INPUT
RANGE
ANAGND
-5V
+ 10V REF OUT
S/H OUT
-15V
N/C

CALIBRATION PROCEDURE
Removal of system errors or the small initial errors is
accomplished as follows:
1. Connect the converter per Figure 3 and Table 2 for the
appropriate full-scale range (FSR). Apply a pulse of 100
nanoseconds minimum to the START CONVERT input
(pin 3) at a rate of 500 KHz. This rate chosen to reduce flicker
if LED's are used on the outputs for calibration purposes.

Table 2. Input Connections
INPUT
CONNECT
VOLTAGE INPUT PIN
RANGE
38 TO:

a to -

CONNECT
PIN 40
(RANGE) TO,

BINARYI
OFFSET BINARY

CONNECT PIN 34 TO:

COMPo BINARY!
CQMP. OFFSET BINARY
CONNECT PIN 34 TO:

39

44

-

2,4,5,7

010 -10V

-

44

-

2,4,5,7

o to

44

44

-

2,4,5,7

5V

-20V

010 +1DV

±5V
±10V

EXT
-10V Ref.'

44

2,4,5.7

-

39

43

2,4.5,7

-

-

43

2,4,5,7

-

'May be Referenced to +1DV Ref. (Pin 43)

NOTE,PINS2,4,5.7.24-30
and41 MUST BE CON
NECTED TO THE SAME
GROUND PLANE AS
CLOSE AS POSSIBLE
TOTHECASE

2. Zero Adjustment.
Apply a preCision voltage reference source between the analog input (pin 39) and ground (pin 24). Adjust the outut olthe
reference source per Table 4a and 4b for the unpolar zero
adjustment (+ V2 LSB) or the bipolar zero adjustment (zero
+ '12 LSB) for the appropriate FSR. Adjust the zer%ffset
trimming potentiometer so that the output code flickers
equally between 0000 0000 0000 and 0000 0000 0001 or
between 111111111111 and 111111111110 depending on the
output coding selected per Tables 2 and 6.
For bipolar operation, adjust the potentiometer until the displayed code flickers equally between 100000000000 and
100000000001 with COMP BIN tied high or between 0111
1111 1111 and 0111 1111 1110 with COMP BIN tied low.
Refer to Table 5.
3. Full-Scale Adjustment.
Set the output of the voltage reference used in step 2 to the
value shown in Table 4a or 4b for the unipolar or bipolar gain
adjustment (+ FS - 1V2 LSB) for the appropriate FSR.
Adjust the gain trimming potentiometer so that the output
code flickers equally between 1111 1111 1110 and 1111 1111
1111 or between 0000 0000 0001 and 0000 0000 0000
depending on the output coding selected per Tables 2 and 4.
4. To confirm proper operation olthe device, vary the precision
reference voltage source to obtain the output coding listed
in Tables 5 and 6.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

1-249

•

ADS·22AC
ANALOG

~
--------r'--------------------------------------,,,
,''
NOTE NOT DRAWN TO SCALE

INPUT

SETTLING

TIME

-r- ~~~~~~~ ~t-'-------------------------------------I

~

i

START:
CONVERT

,,
,,
I

:I

I

I

-1:

TEMPERATURE:

Aoe-5OS

CONVERSION
TIME (TI)

N

---r-l--~
L

I

~
100 n,Se<; MINIMUM

---i-;--------------------

i~:

-.lJ
!-I,!

I-1---

I

I I

I

I

1:

I

"

,I

1
I

I

, ,I ,
I

I

r~----------- T, MAXIMUM

I

I

'I'
'I'
:;-:

I

I

IEOc '-----+,-+,--<,------'
I_i
:
i r-r-~j-'-------+i--,\ j

35nSec MAXIMUM

---------------1

l-

--j

IOnSec MINIMUM
25nSec MAXIMUM

(INTERNAL~SIH

~

1I 200nSec ACOUI$ITIONTIME

II I

!,,

'NVA"DD"A

I

'H--

I I
I I

IOOnSec HOLD MODE SETTLING TIME

1

: I:

30nSec

1-------MINIMUM

....

~'f-~-_-_-_-----------~---~~-~I~-SU~-"--~~~~~~~~~~~-I----'

-1 t- ~~~~~cM

MXWXJ
ENABLED DATA N·' VALID

IOnSec
MAXIMUM

DATA N VALID

F

ENASLED DATA N
VALID

Figure 4. Timing Diagram
TIMING

Figure 4 shows the relationship between the various input signals. The timing cited in Table 3 applies over the operating temperature range and over the operating power supply range.
These times are guaranteed by design.
Table 3. Signal Timing Summary
LINE

DURATION IN NANOSECONDS

Start Convert

tOO nSec maximum

Analog Input Settling Time

t50 n Sec minimum

Start Convert Low to EOC
High Propagation Delay

35 nSec maximum

Start Convert Low to Previous
Output Data Invalid

350 nSec minimum

Data Valid Before EOC
Goes Low
Enable to Output Data Valid
Propagation Delay

25 nSec minimum
10 nSec maximum

the ADC-SOS's internal registers and logic. The ADC-SOS used
in the ADS-22AC employs a subranging architecture with digital
error correction. Also known as a two-step method of conversion, this technique uses a single 7-bit flash converter twice in
the conversion process to yield a final resolution of 12 bits. Refer
to the Timing Diagram shown in Figure 4 for further clarification.
The SHM-4S used in the ADS-22AC acquires the input signal
on the internal hold capaCitor (200 nanoseconds maximum
acquisition time to 0.01%). The SHM-4S is then put into the hold
mode prior to the analog-to-digital conversion. In the hold mode,
the SHM-4S requires a maximum of 100 nanoseconds to have
its output buffer settie to 0.01% accuracy. The ADC-SOS
requires a maximum of 1S0 nanoseconds since the previous
conversion for the Input signal to settie before initiating a conversion. The input of the ADC·SOS starts settling to its final value
while the SHM-4S is in the acquisition mode. The missing SO
nanoseconds of the required maximum analog input settling
time is made up by the time the samplelhold is in the acquisition mode. Thus, by the end of the SHM-4S's hold mode settling
time, the ADC-SOS's input is fully settled.

THEORY OF OPERATION

The SHM-4S is in the sample mode when the internal
ADC-SOS's SIR control is high. During this period of time, the
AID is not performing a conversion.

This theory of operation describes how the ADS-22AC uses
an internal sample-and-hold to capture fast signals for an
internal ADC to then digitize. The ADS-22AC consists of a fast
sample-and- hold device (DATEL.:s SHM-4S) and a high perfor·
mance analog· to-digital converter (DATEL.:s ADC-SOS). Figure
S is a detailed block diagram showing the SHM·4S along with

The SIH control pin goes low after the rising edge of the start
convert pulse a minimum of 10 nanoseconds and a maximum
of 2S nanoseconds later. To assure the SHM has 200 nSec maximum acquisition time, the start convert pulse should be given
a minimum of 190 nanoseconds after the desired start of the
acquisition time. The width of the start convert pulse should be

1-250

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ADS·22AC
OF'SET

''"

DIGITAL GROUNDS

Figure 5. Detailed Block Diagram
100 nsec minimum to assure the hold mode settling time of 100
nanoseconds is observed. The 100 nanoseconds takes into
account the min-max propagation delays of the start convert
high to SiR control low propagation delays and the start
convert low to EOC high propagation delays.
The analog input, having been configured for the appropriate
range, is buffered and then digitized by the 7 bit flash ADC to
determine the seven most significant bits. The seven bits of data
are then stored in a register and provided to the input of a 7-bit
digital-to-analog converter. This DAC has 13 bits of linearity.
The first pass finished, internal switching occurs effectively subtracting the output of the digital-to-analog converter from the
analog input. The result is a voltage difference between the first
7-bit digitization and the analog input. This voltage difference
is amplified and converted by the 7-bit ADC. The result of this
second conversion is then latched to determine the least 7 significant bits. The outputs from the two registers are then added
by the digital correction logic to produce a 12-bit word. EOC
goes low, indicating the conversion is complete, and the out
put is present at the three-state output buffers.

teed throughput rate of 1.0 MHz. Retriggering of the start
convert pulse before EOC goes low will not initiate a new
AID conversion.
The performance characteristics shown in Table 7 and in Figure
6 apply over the operating temperature range and over the
power supply operating range unless otherwise specified.
These characteristics are guaranteed by design.
Table 4a. Zero And Gain Adjust For Unipolar Use
UNIPOLAR FSR

ZERO ADJUST
+v, LSB

GAIN ADJUST
+FS - IV, LSB

-O.61mV

- 4.9982V

-1.22mV

- 9.9963V

o to -5V
o to -10V
o to -20V
o to +10V

-2,44mV

-19.9927V

+1.22mV

+ 9.9963V

Table 4b. Zero And Gain Adjust For Bipolar Use
Once the second step of the flash analog-to-digital conversion
is finished, the analog input can change even though the conversion cycle has not been completed (EOC going low). The
internal Sample/Hold control signal line goes Iowa minimum
of 30 nanoseconds before EOC goes low, indicating that the
SHM-45 can be put back into the sample mode. This feature
improves the overall throughput of the ADC-SHM system.
Data from the previous conversion would be valid up to 350
nanoseconds after the falling edge of the start convert pulse.
Data from the new conversion is valid a minimum of 25 nanoseconds before EOC goes low and valid up to 350 nanoseconds after the falling edge of the next start convert pulse.
There is 10 nanosecond maximum delay after the three-state
output buffers are enabled before the data is valid.
The overall throughput of the ADS-22AC using the ADC-505
and the SHM-45 internally consists of 200 nanoseconds for the
sample time, 100 nanoseconds for the hold and input settling
time, 15 nanoseconds for observance of min-max propagation
delays and 560 nanoseconds for the conversion process (SIR
control pin saves 30 nanoseconds). Total guaranteed throughput is a maximum of 1 microsecond for the system for a guaran-

BIPOLARFSR

ZERO ADJUST
Zero +v, LSB

GAIN ADJUST
+FS - IV2 LSB

±10V

+2,44mV

+9.9927V

±5V

+1.22mV

+4.9963V

Table 5. Output Coding for Bipolar Operation
OUTPUT COMING
BIPOLAR
SCALE

INPUT RANGES
VOLTS de

±5V

± 10V

+ FS - 1 LSB

+4.9976V

+9.9951V

+ 3f4 FS

+3.7500V

+ 1/2 FS

+ 2.5000V
O.OOOOV

0
- 112 FS

~

2.S000V

OFFSET·BINARY
MSB

lSB

COMPo .
OFFSET BINARY
MSB

lSB

111111111111

0000 0000 0000

+ 7.5000V

1110 0000 0000

0001 1111 1111

+ 5.0000V

1100 0000 0000

0011 1111 1111

O.OOOOV

1000 0000 0000

0111 1111 1111

SOOOOV

0100 0000 0000

1011 1111 1111
1101 1111 1111

~

FS

- 3.7500V

-7.5000V

0010 0000 0000

- FS + 1 LSB

- 4.9975V

-9.9951V

0000 0000 0001

1111 1111 1110

- 5.0000V

-10.0000V

0000 0000 0000

111111111111

-

~

3/4

FS

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-251

ADS·22AC
Table 6. Output Coding For Unipolar Operation
UNIPOLAR
SCALE

INPUT RANGES
VOLTS de
010 -5V

+FS -1 LSB

7/. FS
3f4 FS
'/2 FS
V4 FS
'/. FS
1LSB

010 -10V

-4.99SV

-9.9976V

010 +10V
+9.9976V

OUTPUT CODING
STRAIGHT BINARY
010 -20V

MSB

-19.99S1V

1111

COMPo BINARY

LSB

MSB

1111

1111

0000

0000

0000

LSB

-4.37SV

-S.7S0V

+S.7S0V

-17.S00V

1110

0000

0000

0001

1111

1111

-3.7S0V

-7.S00V

+ 7.S00V

-IS.00V

1100

0000

0000

0011

1111

1111

-2.S00V

-S.OOV

+S.OOV

-10.00V

1000

0000

0000

0111

1111

1111

-1.2S0V

-2.S00V

+2.S00V

-S.OOOV

0100

0000

0000

1011

1111

1111

-0.62SV

-1.2S0V

+1.2S0V

-2.S00V

0010

0000

0000

1101

1111

1111

-0.0012V

-0.0024V

+0.0024V

-0.0049V

0000

0000

0001

1111

1111

1110

O.OOOOV

O.OOOOV

O.OOOOV

0000

0000

0000

1111

1111

1111

a

O.OOOV

SOdS

60dS

40dB

20dB

OdB

-20dB

100KHz

300 KHz

500 KHz

700 KHz

ADSM22AC FFT Report for Total Harmonic Distortion - 500 KHz Input

100dS

BOdS

60dB

40dB

20dB

OdB

- 20dB

100KHz

300 KHz

500KHz

700 KHz

ADS-22AC FFT Report for Total Harmonic Distortion - 100 KHz Input

Figure 6. Harmonic Distortion Performance
Table 7. Performance Characteristics At
Different Temperatures
CHARACTERISTICS

VALUE

Conversion Rate (Changing Inputs):
DOC to + 70°C

1.0 MHz minimum

Harmonic Distortion (Below E5)
+25°C
DOC to + 70°C

- 72dB minimum
- 72dB minimum

1-2S2

ORDERING INFORMATION
MODEL NO.
ADS-22AC·

TEMP RANGE

o to

+ 70°C

THROUGHPUT
RATE
1.0MHz

·Contact factory for high reliability or extended temperature range versions.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-574Z, -674Z
12-Bit, Microprocessor-Com patible
AID Converter with S/H
FEATURES
NC

• Complete 12-Bit AID converters with
sample-hold, reference, and clock
• Pin-to-pin compatible with industry
standard HI574A/674A

, - - - - - - - - - . { 1 t STS
0811 (MSB)

• No missing codes over temperature

0810

• 15 !,Sec. Conversion time (ADC-674Z)

DB.
DB.

• 150 mW maximum power dissipation

DB7
DB'

GENERAL DESCRIPTION
DATEL:s ADC-574Z/674Z family of AID converters are single chip monolithic CMOS
versions of the industry standard devices.
The sample-hold feature of this device
allows conversion of input frequencies of
up to 5 KHz without requiring an external
circuit.
These units include a reference, clock,
three-state outputs, and digital interface circuit which allows direct connection to the
microprocessor address bus and control
lines. The ADC-574Z completes a 12-bit
conversion in 25 microseconds, while the
ADC-674Z converts in 15 microseconds.
Four user selectable input ranges are
provided: 0 to +10V, 0 to +20V, ±5V, and
± 10V dc. Laser trimming ensures specified
linearity, gain, and offset accuracy.
Monolithic CMOS construction keeps the
power consumption to a low 150 mW maximum, plus it reduces ground noise and
parasitics.
The ADC-574Z/674Z are available for operation over the commercial, O°C to +70°C
temperature range. All models are packaged in 28-pin dual-in-line sidebrazed ceramic packages.

REF

IN

MECHANICAL DIMENSIONS
INCHES (MM)

.,.,

.

INPUT/OUTPUT CONNECTIONS
FUNCTION

V,

ie' +5V

2

121f. DATA MODE SELECT

3

~, CHIP SELECT

A., BYTE AOORESSISHOAT CYCLE

"N FUNCTION

,."

DGND

DBO(LSB}

"

DB'

18

002

,

Alt. READ/CONVERT

18

DB3

CEo CHIP ENABLE

20

DB<

7

Vee

OM

8

REFERENCE OUT

"

22

0..

9

"oNO

23

DB7

'0

REFERENCE IN

24

DB8

HC

5

"02

BIPOLAR OFfSET

,.

DB10

13

tOV IN

27

DB11 (MSB)

"

20V IN

28

STS

25

0..

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

1-253

ADC-574Z, -674Z
ABSOWTE MAXIMUM RATINGS
Analog Supply Voltage (Vc~to DGNo) .................................... .
logic Supply Voltage (Pin 1 ........................................... .
Analog Common (Pin 9) to igital Common (Pin 1S) ........................ .
Digital Control Inputs (Pins 2-6) to Digital Common ........................ .
Analog Inputs (Pins 10, 12, 13) to Analog Common ......................... .
20V Input (Pin 14) to Analog Common ................................... .
Ref. Out (Pin 8) Short Circuit Duration ................................... .

Oto +16.5
OVto+7V

±1V

-0.5V to VI"!!;C +0.5V
±16.5V
±24V
Indefinite to common momentary to Vs
1000C
1000mW
300°C, 10 Sec.
48°CIW

~:r~::8~~~uar;:ci~' ::::::::::::::::::::::::::::::::::::::::::::::::::

Lead Temperature, soldering ........................................... .
Thermal Resistance, Junction-to-Ambient ................................ .

FUNCTIONAL SPECIFICATIONS
Typical at 2SoC, +1SV dc (or +12V dc) and +5V dc supply voltage, unless otherwise noted.
ANALOG INPUTS

oto

Input Voltage Range, unipolar .......................................... .
bipolar ........................................... .
Input Impedance, 10V range ........................................... .
20V range ........................................... .

+10V, 0 to +20V
±5V, ±10V
5KQ ±25%
10 KQ ±25%

ANALOG OUTPUTS'
Internal Reference, voltage ............................................ .
current ............................................ .
DIGITAL INPUTS'

+10.00V ±O.1 max.
2.0 mAmax.

::::::::::::::::::::::::::::::::::::::::::::::::

Logic Levels: :~g:~ ::~':"
Loading: logic current, min. . .......................................... .
max ............................................ .
Capacitance ........................................................ .

+2.4V min. to +5.5V max.
-O.SV min. to +0.8V max.
-5 "A
+5 "A
5pF

DIGITAL OUTPUTS'
Logic Levels: logic "0" (I sink, 1.6 mAl ................................... .
logic "1" (I source, 500"A) ................................. .
Leakage (high Impedance state) ........................................ .
Capacitance ........................................................ .

+O.4V max.
+2.4Vmin.
-5 ~ min. to +5"A max.
5pF

POWER ReQUIREMENTS
Analog Supply Voltage Range .......................................... .
Logic Supply Voltage Range ........................................... .
Supply Cur-rent ",ax., Analog Supply .................................... .
logic Supply ..................................... .
Power Consumption (±Vs = ±15V), max ................................. .

+11.4V to +16.5V
+4.5V to +5.5V
+7mA
+1 mA
150mW

PHYSICAL/ENVII\ONMENTAL
Operating Temperature Range ................ .' ........................ .
Storage Temperature Range ........................................... .
Package Type ....................................................... .
574ZC
Resolution .............................. '....... .
Unipolar Offset, max.- ........................... .
Conversion Time, max ............................ .
Full Scale Calibration Error, max .•
at 2S.C ..................•....................
over temp" ................................... .
over temp.' ................................... .
Linearity Error, max. (over temp) ................... .
Differential Linearity Error< ........................ .
Bipolar Offset, max.•..............................
Tempco:·
Unipolar Offset ................................ .
Bipolar Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Full Scale Calibration ........................... .
Power Supply Rejection:'.
+Vs = 13.5V to 16.SV or +11.4V to +12.6V .......... .
±Vloglc = +4.5V to +5.SV ....................... .

674ZC

r

OOC to +70°C
-65°C to + 150°C
28 pin side brazed ceramic DIP
574ZB

674ZB

574ZA

674ZA

12 Bits
±2 LSB
25 "Sec.
15 "Sec.

12 Bits
±2LSB
25 "Sec.
15 "Sec.

12 Bits
±2LSB
25 "Sec.
15 "Sec.

0.3% of F.S.
0.5%
0.22%
±1 LSB
±1 LSB
±10 LSB

0.3% of F.S.
0.4%
0.12%
±'12 LSB
±'12 LSB
±4 LSB

0.3% of F.S.
0.35%
0.05%
±V. LSB
±'12 LSB
±4LSB

10 ppm/oC
10 ppm/oC
45 ppm/oC

5 ppm/oC
5 ppm/DC
25 ppm/oC

5 ppm/OC
5 ppm/oC
10 ppm/OC

±2LSB
+'12 LSB

+'12 LSB

±1 LSB

±1 LSB

±'12 LSB

FOOTNOTES:
1. Available for externalloads.lOxternalload should not change during conver·
sion. When supplying an external load and operating on ±12V supplies, a
buffer amplifier must be provided for the reference output.
2. Logic Inputs - CE, CS, RIC, Ac, 12/8.
3. Logic Outputs - DB11·DBO, STS.
4. Over temperature.

1-254

5.
6.
7.
8.
9.
10.

Adjustable to zero.
With 50 Q fixed resistor from REF OUT to REF IN. Adjustable to zero.
No adjustment at 25OC.
With adjustment at 25°C.
Guaranteed maximum change, Tmin to Trnax (using internal reference).
Maximum change in full scale calibration.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

ADC-574Z, -674Z
TYPICAL CONNECTIONS
TECHNICAL NOTES
1. The ADC-574Z, -674Z may interface directly to a microprocessor which can take full control of each conversion, or the
device can be operated in the "stand alone" mode (controlled
only by the RIC input). Full control consists of selecting an
8- or 12-bit conversion cycle, initiating the conversion and
reading the output data when ready. The data may be read
12 bits at once or 8 followed by 4 in a left-justified format. There
are five control inputs (12/8, CS, Ao, RIC and CE) and all are
TIL/CMOS compatible. (See Control Input Truth Table.)
2. A conversion is initiated ~ a logic transition on any of the
three inputs: CE, CS, RIC. One, two, or all three may be
dynamically controlled. The nominal delay for each of the
three inputs is the same and if necessary, all three may
change states simultaneously. If it is required that a
particular input controls the start of conversion, the other two
should be set up at least 50 nanoseconds earlier. (See Start
Convert Timing.)
3. To read the output data, four conditions must be met (or the
output buffers will remain in high il11£..edance state): RIC
taken high, STS low, CE high and CS low. When this is
accomplished, the data lines are activated according to the
state of the 12/8 and Ao inputs. (See START CONVERT,
READ CYCLE TIMING and APPLICATION.)
4. The analog signal source driving the ADC-574Z, -674Z's input
will see a nominal load of 5 KQ (10V range) or 10 KQ (20V
range). However, the other end of these input resistors may
change 400 mV with each bit decision, causing sudden
changes in current at the analog input. Therefore, the signal
source must maintain its output voltage while supplying these
step changes in load current which occur at 1.6 microsecond
intervals. This requires low output impedance and fast settling
by the signal source. If a samplelhold is required to precede
the converter, DATEt.:s SHM-20 is recommended.
5. The power supply used should be low noise and well regulated. Voltage spikes can affect accuracy. If a switching supply is used, the outputs should be carefully filtered to assure
"noise free" dc voltage to the converter. Decoupling capacitors should be used on all power supply pins; the +5V dc
supply decoupling capacitor should be connected directly
from +V\ogic (Pin 1) to digital common (Pin 15). Vee (Pin 7)
should be decoupled directly to AGND (Pin 9). It is recommended that a 10 J.lF tantalum type in parallel with a 0.1 J.tf
ceramic type be used for decoupling.
6. The use of good circuit board layout techniques is required
for rated performance. It is recommended that a double
sided printed circuit board with a ground plane on the
component side is used. Other techniques, such as wirewrapping or pOint-to-point wiring on vectorboard will have an
unpredictable effect on accuracy. Sensitive analog signals
should be routed between ground traces and kept away from
digital lines. If analog and digital lines must cross, they
should do so at right angles.

DB11 (MS8)

0810

•

DB.

,

0 ..
DB7

0..

+15V

,~,!~
-15V

UNIPOLAR CONFIGURATION
NOTES: The trimpots shown are for calibration of offset and gain. If
adjustment is not required in unipolar; replace R2 with a 50Q, 1% metal
film resistor, omit the network on Pin 12 and connect Pin 12 to Pin 9. In
bipolar; either R" or R2 or both can be replaced by SOQ, 1% metal film

resistors.

DB11jMSB)

0810

DB'

0"
0.7

DB.

BIPOLAR CONFIGURATION

CODING TABLES
INPUT RANGE
010 + 10V 010+20V
+10.000
+9.9963
+5.0012
+4.9988
+4.9963
+00012
0.0000

+20.0000
+19.9927
+10.0024
+9.9976
+9.9927
+0.0024
+0.0000

OUTPUT CODING
MSB
1111
1111
1000
¢OOO
0111
0000
0000

INPUT RANGE

LSB
1111
1111
0000
0000
1111
0000
0000

1111
111¢'
0000'
OOO¢'
111~'

OOO~'

0000

OUTPUT CODING

±5V

±10V

MSB

+5.0000
+4.9963
+0.0012
-0.0012
-0.0037
-4.9988
-5.0000

+10.0000
+9.9927
+0.0024
-0.0024
-0.0073
-9.9976
-10.0000

1111
1111
1000
¢OOO
0111
0000
0000

LSB
1111
1111
0000
0000
1111
0000
0000

1111
111~'
0000'
OOO¢,
111~'
OOO~'
0000

*Voltages shown are theoretical values for the transitions indicated.

Ideally, in the continuous conversion mode, the output bits indicated as $I will change from "1" to "0" or "0" to "1" as the input
voltage passes through the level indicated.
Output coding is straight binary for unipolar and offset binary for
bipolar.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

1-255

ADC-S74Z, -674Z
CALIBRATION

TIMING AND OPERATION

UNIPOLAR CALIBRATION
Offset Adjust
Apply an input of + '12 LSB
(+1.22 mV for the 10V range;
+ 2.44 mV for the 20V range).
Adjust the offset trimpot (R,)
until the first code transition
flickers between 0000 0000
0000 and 0000 0000 0001.
Gain Adjust
Apply 1'h LSB's below the
nominal full-scale (+ 9.9963V
for the 10V range; + 19.9927V
for the 20V range). Adjust the
gain trim pot (R 2) so that the
output flickers between 1111
1111 1110 and 1111 1111
1111.

BIPOLAR CALIBRATION
Offset Adjust
Apply 'h LSB above negative
full-scale (- 4.9988V for the
± 5V range; - 9.9976V for the
± 10V range.) Adjust the
offset trimpot (R,) so that the
output flickers between 0000
0000 0000 and 0000 0000
0001.
Gain Adjust
Apply 1'h LSB's below
positive full scale (+ 4.9963V
for the ± 5V range; + 9.9927V
for the ± 10V range). Adjust
the gain trimpot (R 2) so that
the output flickers between
1111 1111 1110 and 1111
11111111.

TIMING CONTROL
The variety of the ADC-574Z, -674Z's control modes (as shown
in the "CONTROL INPUTS TRUTH TABLE") allow for simple interface in most system applications.
The output signal STS indicates the status of the device;
high during a conversion, and low at the completion of a
conversion. During a conversion (STS output high). the output buffers remain in the high impedance state and data
cannot be read. A start convert during conversion will not
reset the converter or reinitiate a conversion. However, if Ao,
changes state after a conversion begins, an additional start
convert pulse will latch the new state of Ao, causing a wrong
cycle length for that conversion.

Stand-Alone Mode Timing
For stand-alone ~eration, all \bat is required ~a single
control line to RIC. CE and 12/8 are tied high, CS and Ao
are tied low, and the output appears in words of 12 bits.
The RIC signal may have any duty cycle within the limits
shown in the diagrams below.
The data may be read when RIC is high unless STS is
also high indicating a conversion is in progress.

STS---'-----.../

Outputs Enabled Alter Conversion

""i,~~t~j~

STS--...;-------;----

-1

150n5
MAX

0811·080 -:-::HIG"'H"'.Z-'---<

25"5
MIN
DATA

VALID

HIGH·Z

Outpuls Enabled With RIC High

CE-----'

CS
tHSC

RIC

Control Inputs Truth Table
CE CS RIC 12/8 Ao
0

X

X

1
0
0
1-0
1-0
0
0
0
0
0

0-1
0-1
1
1
1
1
1
1
1

1-256

X
X
0 X
0 X
0 X
0 X
1-0 X
1-0 X

X
X

1
0
0

X

X
X

1
1
1

0
1
0
1
0
1
0
1

OPERATION
None
None
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Initiate 8-bit conversion
Initiate 12-bit conversion
Enable's 8 MSB's only
Enable's 4 LS8's plus 4
trailing zeroes

A,

ISAC::)

STS

1

I_H_Rc_ _ _ _ _ _ ____

r
:

I~---------­
HAC,,-_ _-"I-_---.

===::JKD.
t;:'1

:----1:-----

tDSC ...

1

:

DB11·DBO

:

HIGH IMPEDANCE

1

1

Start Convert Timing

A read operation in most applications begins after the
conversion is complete and STS is low. For earliest access
to the data however, the read should begin no later than
(tDD + tHS) before STS goes low. (See Technical Note 3.)

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ADC-574Z, -674Z
Read Mode
Symbol
Parameter
Access Time from CE
tDD
Data Valid after CE Low
tHD
~tput Float Delay
tHL
tSSR CS to CE Setup
tSRR RIC to CE Setup
tSAR A, to CE Setup
tHSR CS Valid after CE Low
tHRR RIC High after CE Low
tHAR A, Valid after CE Low
STS Delay after Data Valid
tHS

CE

CS
tHRR~

:

R/C~,
-----J

H

r~
I

tSRR

A.,==X~tS"R
~i-~l

x==

tHARH

25 nS
50 nS
0
50 nS
0
0
50 nS
300 nS

Typ.
Max.
75 nS 150 nS
35 nS
100 nS 150 nS
0
0
25 nS
0
0
0
0
25 nS
500 nS 1000 nS

I

STS

I

I
I
1

0811·080

Min.

tHS

---------t'f.H~IG~H~~~lE~~~:c==J
NCE
: 1M PEOA
I: I
t-I

too

---i

Interface To An 8-Blt Data Bus

Read Cycle Timing

ADC-674Z Convert Mode
Symbol
Parameter
tDSC ISTS Delay From CE
tHEC CE Pulse Width
tssc CS to CE Setup
IHSC CS_Low during CE High
tSRC RIC to CE Setup
tHRC RIC Low during CE High
tSAC A, to CE Setup
tHAC A, Valid during CE High
Conversion Time, 12 bit cycle
tc
8 bit cycle

Min.

Typ.
Max.
100 nS 200 nS
30 nS 20 nS 20 nS 0
20 nS
0
0
20 nS
18 ~S 25 ~S
10 ~S 13~S 17 ~S

-

50 nS
50 nS
50 nS
50.oS
50 nS
0
50 nS
15 ~S

The 12/8 input will be tied either high or low in most
applications. With 12/8 high, all 12 output lines become
active simultaneously for interface to a 12- or 16-bit data
bus. AD is ignored. Taking 12/8 low organizes the output
in two B-bit bytes, which are selected one at a time by AD'
This allows an B-bit data bus to be connected as shown
above. AD is normally tied to the LSB of the address bus
for storing the converter's output in two consecutive
memory locations. This two byte format is called "left justified data" for which a decimal point is assumed to the
left of byte 1. In addition, AD may be toggled at any time
without damage to the converter. Break-before-make
switching is guaranteed between two data bytes, which
assures that the outputs strapped together as shown are
never enabled at the same time.

ADDRESS BUS

ADC-574Z Convert Mode
Symbol
Parameter
tDSC I::> I::> Delay From CE
tHEC CE Pulse Width
tssc Q§ to CE Setup
tHSC CS Low during CE High
tSRC RIC to CE Setup
tHRC RIC Low during CE High
tSAC A, to CE Setup
tHAC A, Valid during CE High
Conversion Time, 12 bit cycle
Ie
8 bit cycle

Min.

-

0
-

-

Typ.
Max.
200ms 200 nS

-

-

-

-

-

0

15
10

~S
~S

0

-

25
17

~S
~S

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

1-257

•

ADC-574Z, -674Z
FAST AID WITH SAMPLE HOLD
+5V

-15V +15V

....----{IJ

ADC-574ZI
-674Z

SHM·20

1218

ADDRESS BUS

ORDERING INFORMATION
The above diagram shows the ADC·574Z, -674Z configured for
unipolar (0 to + 10V) operation. Preceding the ADC-574Z, -674Z
is DATEL:s SHM-20, a 1 microsecond precision sample/hold.
All sample/hold amplifiers are compatible with the ADC-574Z,
-674Z; however, many will require an additional wide-band
buffer amplifier to reduce their output impedance.

MODEL NO.

TEMPCO

ADC-574ZC
ADC-574ZB
ADC-574ZA
ADC-674ZC
ADC·674ZB
ADC-674ZA

45 ppm/DC
25 ppm/DC
10 ppm/DC
45 ppm/DC
25 ppm/DC
10 ppm/DC

ACCESSORIES

1·258

Part Number

Description

TP100 or TP100K

Trimming Potentiometers

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DIGITAL-TO-ANALOG
CONVERTERS

•
OJA CONVERTERS
MODEL

RESOLUTION

SETTLING
TIME (MAX)

DAC-8303

8 Bits

7.5 ns

DAC-0805

8 Bits

TEMPERATURE
RANGE ("C)

OUPUT
RANGE

CODING

PACKAGE

±t/2 LSB

oto -1.054V

Bin

2 x 3 x 0.375 in.
(50x75xl0mm)
Module

oto +70

2-35

8 ns

±1/2 LSB

o to -637.5 mV

C Bin

24-pin DIP
Hybrid

-25 to +85

2-7

8 Bits

25 ns

±1/2 LSB

Oto+5mA
±2.5 mA

Bin

24-pin DIP
Hybrid

o to +70

2-39

-55 to +125

8 Bits

150 ns

±1/2 LSB

Oto -2 mA

Bin

16-pin DIP
Monolithic

-55 to +125

8 Bits

200 ns

±1/2 LSB

±Vref I Rin

Bin

16-pin DIP
Monolithic

o to +70

8 Bits

300 ns

±1/2 LSB

Oto -2 mA

Bin

16-pin DIP
Monolithic

-55 to +125

DAC-60BC

8 Bits

1 ~s

±1/2 LSB

Bin

20-pin DIP
Monolithic

o to +70

DAC-UP8BC
DAC-UP8BM

8 Bits

2~s

±1/2 LSB

Oto+l0V
±5 V

Bin

22-pin DIP
Monolithic

-55 to +125

DAC-330

10 Bits

4.7 ns

±1 LSB

Oto -IV

Bin

28-pin DIP
Monolithic

-20 to +75

2-11

25 ns

±1/2 LSB

Oto+5mA
±2.5 mA

Bin

24-pin DIP
Hybrid

o to +70

10 Bits

2-39

-55 to +125

10 Bits

250 ns

Oto-4mA

Bin

16-pin DIP
Monolithic

DAC-HFBBMC
DAC-HFBBMM
DAC-OBBC
DAC-08BM
DAC-7523
DAC-ICBBC

DAC-HFI DBMC
DAC-HF10BMM
DAC-IC10B
DAC':.IC10BC

LINEARITY
ERROR (MAX)

Vref
15kQ

D
256

±1/2 LSB

DAC-ICIDBM

±1 LSB
±1/2 LSB

DAC-610C

10 Bits

500 ns

±1/2 LSB

DAC-7533

10 Bits

800 ns

±O.1%

Vref
15kQ

D
256

±Vref I Rin

o to +70

o to +70

o to +70

o to +70
oto +70

PAGE

2-3
2-31
2-59
2-19
2-68

2-55

-55 to +125

Bin

20-pin DIP
Monolithic

oto +70

2-19

Bin

16-pin DIP
Monolithic

oto +70

2-31

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

2-1

DIGITAL-TO-ANALOG
CONVERTERS

D/A CONVERTERS
MODEL
DAC-HF12BMC
DAC-HF12BMM
DAC-562C

RESOLUTION

t2 Bits

50 ns

LINEARITY
ERROR (MAX)
±1/2 LSB

±1 mA

12 Bits

50 ns

±1/2 LSB

12 Bits

11ls

±1/2 LSB

DAC-7541

12 Bits

11ls

±0.012%

DAC-7134BJ

±5 V, ±10V
Vrel
15kQ

D
4096

±Vref I Rin
±Vrel!Rin

12 Bits

31ls

±1/2 LSB

12 Bits

31ls

±1/2 LSB

DAC-HK12BGC
DAC-HK12BMC

oto -10, ±5 V, ±10 V

Vret I Rin

PACKAGE

Bin

24-pin DIP
Hybrid

-55 to +125

Bin

24-pin DIP
Hybrid

-55 to +125

CBin
C2C

4 x 2 x 0.4 in.
(102 x 51 x 10 mm)

oto +70

Bin

24-pin DIP
Hybrid

oto +70

2-19

Bin

18-pin DIP
Monolithic

oto +70

2-31

I3lil

28-pin DIP
Monolithic

o to +70

2-25

Bin

24-pin DIP
Hybrid

oto +70
o to +70

2-43

2C

Oto+5V,+10V

±2.5 V, ±5 V, ±10 V

DAC-HK12BMC-2

12 Bits

31ls

±1/2 LSB

DAC-HK12BMM-2
DAC-HZ12BGC
DAC-HZ12BMC

12 Bits

31ls

±1/2 LSB

DAC-HZ12BMM
DAC-HZ12DGC
DAC-HZ12DMC
-------DAC-HZ12DMM
DAC-7134BK
DAC-7134UK
DAC-7134BL

3 Digits

31ls

±1/4 LSB

13 Bits

31ls

±1/2 LSB

14 Bits

31ls

±1/2 LSB

16 Bits

1511S

0.003%

DAC-HP16BGC
DAC-HP16BMM

2-2

±2.5 V, ±5 V, ±10 V

o to ±5 V, ±10 V
±2.5 V, ±5 V, ±10 V

oto 2.5 V
o to +5 V

Bin

C Bin

24-pin DIP
Hybrid

24-pin DIP
Hybrid

oto +70

2-39
2-15

oto +70
oto +70

2-43

-55 to +125

oto +70
o to +70

2-51

-55 to +125
CBCD

24-pin DIP
Hybrid

o to +70
oto +70

2-51

-55 to +125

Oto+l0V

DAC-7134UL
DAC-HP16BMC

o to ±5 V, ±10 V

oto +70

PAGE

-55 to +125

DAC-HK12BMM
DAC-HK12BGC-2

TEMPERATURE
RANGE (0C)

CODING

±2.5 mA
Oto -2 mA

DAC-612C

DAC-7134UJ

Oto +5 mA

±1/4 LSB

400 ns

DAC-DG12B2

OUPUT
RANGE

±1/2 LSB

12 Bits

DAC-562M
DAC-DG12B1

SETTLING
TIME (MAX)

±Vrel I Rin
---Vrel I Rin

~

28-pin DIP
Hybrid

oto +70

2-25

±Vret I Rin

~

Bin

28-pin DIP
Hybrid

o to +70

2-25

C Bin

24-pin DIP
Hybrid

o to +70
oto +70

2-47

Vrel/Rin
Oto ±10 V

oto ±5 V

Bin

-55 to +125

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339·3000ITLX 174388/FAX (508) 339-6356

DAC-08B
High Speed, 8·Bit Monolithic
Digital·to.Analog Converter

FEATURES
• 85 Nanoseconds settling time
• -10 to + 18V compliance
• ± 4.5 to ± 18V supply
• 8-Bit resolution
• 1- or 2-Quadrant multiplication
• Low cost

GENERAL DESCRIPTION
The DAC-OBBC and DAC-OBBM provide
very high speed performance coupled with
low cost and application flexibility. These
units
have
guaranteed
full
B-bit
monotonicity with nonlinearity of 0.19%
over the full operating temperature range.
High-speed current steering switches
achieve B5 nanoseconds settling time with
a very low glitch for full·scale changes. A
large output voltage compliance range
( - 10 to + 1BV) allows direct current to
voltage conversion with just an output
resistor, omitting the need for an operational amplifier in many cases.
The DAC-OB consists of B fast-switching
current sources, a diffused R-2R resistor
ladder, a bias Circuit, and a reference control amplifier. The diffused resistor ladder
gives excellent temperature tracking,
resulting in a gain temperature coefficient
of 10 ppm/oC. The monolithic fabrication
results in excellent linearity and tempco,
fast output settling and low cost. Linearity
is ±'h LSB.
An external reference current of 2 mA
nominal programs the scale factor of the
DAC. This reference current can also be
varied, resulting in one or two quadrant
multiplying operation. The output voltage
can be unipolar or bipolar dependent upon
the connection of the two complementary
output sink currents.
DAC-OB applications include fast AID converters, waveform generators, audio en·
coder and attenuators, CRT display
drivers, and high-speed modems.
Power supply requirements are ± 4.5V to
± 1BV. Operating temperature range is
O°C to 70°C for the DAC-OBBC and
-55°C to +125°C for the DAC-OBBM.
These models have equivalent specifications and pinouts to industry standard
DAC-OB's.

DIGITAL INPUTS
I

I

LSB \

MSB

•
INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (MM)
1615

1413

12 11 109

P'"
.291.

]

(7.41

MAX

1

121

3

4

5 6

7 8

~ ~O.060

0.200

(5,1)
MAX
{19.9)~--*-

~785 MAX...----1

1-

I I -ll+
~ f.- 0.100

MIN.
~

0.018

THRESHOLD CONTROL (VLC)

lOUT

I

VEE

4

lOUT

5

BIT 1 IN (MSB)

6

81T21N

7

81T3 IN

8

T~-- ~25

SEATING
P~NE

1
2

3

TTT"TT'rrTTTI'TT=-'

FUNCTION

81T4 IN

9

BIT 5 IN

10

BIT6 IN

11

BIT 7 IN

12

B[T 8 IN (MS8)

13

Vee

14

VREF+

15

VREF-

16

COMPENSTION

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-3

DAC-OS8
ABSOLUTE MAXIMUM RATINGS
Vcc Supply to VEE Supply ..............
Digital Input Voltage ..................
VLC ................................
Reference Input Voltage ...............
Reference Input Current ...............

TECHNICAL NOTES
36V

- VEE to - VEE plus 36V
- VEE to + Vee
- VEE to + Vee
5.0 mA

IFS = 255 X IREF (lREF is current at Pin 14)
256

FUNCTIONAL SPECIFICATIONS
Typical at 2SoC, Vs = ± 15V, IREF = 2.0 mA unless otherwise noted.
INPUTS
Resolution ..........................
Coding, Unipolar Output ...............
Coding, Bipolar Output ................
Input Logic Level, Bit ON ("1") .........
Input Logic Level, Bit OFF("O") .........
Nominal Reference Current ............
Reference Bias Current. ...............
Reference Input Slew Rate .............

8 Bits
Straight Binary
Offset Binary
+ 2.0V minimum at
+ 10.0 pA
+0.8V maximum at
-10.0 pAl
2.0 mA
-1.0 pA
8 mAJ~sec.

OUTPUTS
Output Current, IREF = 2.0 rnA ..........
Output Current Range, VEE = - SV ......
Output Current Range, VEE = - 7
to -18V ........................
Output Current, all bits OFF ............

1.99 mA ± 0.05 mA2
0 to 2.1 mA

0 to 4.2 mA
± 0.2 pA typical ± 2.0 pA
maximum
Full-Scale Symmetry .................. ± 1.0 ~A typical ± 8.0 pA
maximum
Output Voltage Compliance ............ -10 to + 18V
PERFORMANCE
Relative Accuracy .................... ±% LSB (±0.19%)
maximum
Nonlinearity ......................... ±% LSB (±0.19%)
maximum
Differential Nonlinearity ............... ± V2 LSB (±0.19%)
Full-Scale Tempco ................... ± 10 ppm/oe typical
± 50 ppm/oe maximum
Settling Time, 2 rnA to % LSB ........... 85 nsec. typical
150 nsec. maximum
Propagation Delay .................... 60 nsec. maximum
Power Supply Sensitivity,
IREF = 1 rnA ....................... ±0.002%/%

Vcc ................................ +4.5V to + 18V
VEE ................................ -4.5V to -18V
Power Supply Current,
IREF = 1.0 mA V = ±5V ............. +3.8, -5.8 mA
maximum

V= ±15V

.......
........................

+ 3.8, - 7.8 mA
maximum
+ 3.8, - 7.8 mA
maximum

PHYSICAL/ENVIRONMENTAL
Operating Temperature Range
DAC-OBBC ........................
DAC-OBBM ........................
Storage Temperature Range ...........
Package ...................... : .....

ooe to + 70°C
- 55°C to + 125°C
-65°C to +150 oe
16 Pin Dip

FOOTNOTES
1. For TTL. DTL Interiace. VLC = av. For other digital interfaces see TECHNICAL
NOTE 3.
2. lOUT (Pin 4) + 'OUT (Pin 2) = Output Current

2-4

2. Reference Amplifier Set-up. If a regulated power supply is
used as the reference, a resistor divider should be used with
the junction by-passed to ground with a 0.1 p.f capacitor. TTL
logic supplies are not recommended to be used as the
reference. AC and dc reference applications will require the
reference amplifier to be compensated using a capacitor
(Cel from pin 16 to VEE' For fixed reference application (dc),
a 0.01 p.F capacitor is recommended. For AC reference applications, the value of Cc depends on the impedance present at pin 14. For RREF values of 1.0, 2.5 and 5.0 KO,
minimum values of Cc are 15, 37 and 75 pf respectively.
Larger values of R'4 require proportionately increased values
of Cc for proper phase margin. See Graph on Reference Input Frequency Response. Low RREF values enable small Cc
achieving highest throughput on V REF' If pin 14 is driven by a
high impedance such as a transistor current source, the
amplifier must be heavily compensated which will decrease
overall bandwidth and slew rate. For RREF = 1.0 KO and Cc
= 15 pf, the reference amplifier slews at 4.0 mA/microsecond, enabling a transition from IREF = 0 to IREF = 2.0 mA
in 500 nanoseconds.
3. InterfaCing Various LogiC Families. The DAC-08 design incorporates a unique logic input circuit which enables direct
interface to all popular logic families and provides maximum
noise immunity. A large input swing capability allows adjustable logic threshold voltage and 200 pA maximum source
current on pin 1. Mimimum input logic swing and minimum
logic threshold voltage is given by VEE + (lREF X 1.0 KO) +
2.5V. Logic threshold is adjusted by appropriate voltage at
VLc. The Interfacing Various Logic Families Diagram shows
appropriate connections. Fastest settling times are obtained
when V LC sees a low impedance. Use 0.01 p.F by-pass
capacitors whenever possible.
4. Analog Output Currents. Both true and complemented output sink currents are provided, 10 +
= IFS ' Both outputs
can be used simultaneously. If one of the outputs is not required, it must be connected to ground or a point capable of
sourcing IFS ' Do not leave unused output pin (10 or
open. The compliance voltage is the voltage swing on output
pin without affecting DAC accuracy. Positive compliance is
36V above VEE and is independent of V +. Negative compliance is VEE + (lREF X 1 KO) + 2.5V.
5. Settling Time. The DAC-08 is capable of extremely fast settling times, typically 85 nanoseconds at IREF = 2.0 mAo
Judicious circuit design and careful board layout must be
employed to obtain full performance. The output capaCitance
of the DAC including the package is approximately 15 pf,
therefore the output RC time constant dam inates at
RL > 500 O.

10

POWER REQUIREMENTS

Power Supply Current,
IREF = 2.0mAV = +5V,-lSV

1. The DAC-08 series is a multiplying D/A converter in which the
output current is a product of the digital word and the input
reference current. Excellent performance is obtained for IREF
from 4.0 mA to 4.0 pA. Monotonic operation is maintained
from 4.0 mA to 100 pA. The full-scale output current is a
linear function of the reference current and is given by:

10)

Settling time remains essentially constant for IREF values
down to 1.0 mA, with gradual increases for lower IREF values.
The switching transients (glitches) are very low and may be
further reduced by small capacitive loads at the output. Settling time will be increased slightly.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

DAC-OS8
TECHNICAL NOTES (Cont'd)

APPLICATION DIAGRAMS (Cont'd)
ACCOMMODATING BIPOLAR REFERENCES

6. Power Supplies. The DAC-08 operates over a wide range of
power supply voltages from a total supply of 9V to 36V. When
operating at supplies of ± 5V or less, IREF :5 1 rnA is recommended. Low reference current operation decreases power
consumption and increases negative compliance, reference
amplifier negative common mode range, negative logic input
range, and negative logic threshold range. For example,
operation at - 4.5V with IREF = 2 rnA is not recommended
because negative output compliance would be reduced to
near zero. Operation from lower supplies is possible, however at least 8V total must be applied to insure turn-on of the
internal bias network. It is recommended that Vcc and VEE
always be bypassed to ground with at least 0.1 /if capacitors.
Symmetrical supplies are not required, as the DAC-08 is
quite insensitive to variations in supply voltage. Battery
operation is feasible, as no ground connection is required;
however, an artificial ground may be useful to insure logic
swings, etc. remain between acceptable limits.
Power consumption may be calculated as follows:
Pd = (I + )(V + ) + (1- )(V -) + (2 'REF)(V - ). A useful feature
of the DAC-08 design is that supply current is constant and
independent of input logic states; this is useful in cryptographic applications and further serves to reduce the size
of the power supply bypass capacitors.
7. Temperature Performance. For most applications, a
+ 10.0V reference is recommended for optimum full scale
temperature coefficient performance. Full scale trimming
may be accomplished by adjusting IREF (changing value of
RREF)' RREF and RL should be selected for similar
temperature coefficient to minimize accuracy error. Setting
time of the DAC decreases approximately 10% at - 55°C
and increases 15% at + 125°C.

R"

IlifF 1- PEAK NEG'" TlVE SWING OF 11111

.IIFlH

B3

84

85

86

87

15

HIGH'IIIPUT
IIofPEO.... NCf

AIS (OPTIONAl)
AAEf =:-R1S'-_ _ _ _ _ _ _ _ _- - - '

\IlifF MUST BE ABOVE PEAl( POSITIVE SWING OF V,IO

REFERENCE INPUT FREQUENCY RESPONSE

~

o~H-I-+..t:1++1<","

g -2
5

~ -6
~

-8

"

FAEQUENCY IMHZI

CURVE 1: Cc s lSpF. V'N '" 2.OV",p CENTERED AT + '.ov
CURVE2:Cc ~ 15pF. V,IO = SOmVp-pCENTEREDAT +2OOmV

CURVE 3, Cc = OpF. VIN ~ l00mVp- p ceNTEREOAT OVANO APPlIEOTHRU 50Q
CONNECTEOTO PIN 14. +2.0VAPPLlEO TO RI'

INTERFACING VARIOUS LOGIC FAMILIES

BASIC POSITIVE REFERENCE OPERATION
82

•

DAC-08BC
Vlt.~

APPLICATION DIAGRAMS

MSB
BI

DAC-08BC

TTl,OTL
Vn'l '" + 1,4V

LSB
B8

c:El
i

Eel

VlC

_10

,31(

VTM '" VlC + 1.4V
+ 15V CMOS. HTl, HNll
VTM'" +7.fN

"AU

1SV

~

JIll(

9.1K

FOR FIXED REFERENCE. TTL
OPERATION, TYPICAL VALUES

ARE
"REF" + 10.oooV
RREf .. 5.000k
R'S"'RRH
Cc "O.01~F
VlC '" 0 V (GROUNDI

+1Jf!iF ~~
RREF
256
10 + TO = IFS FOR ALL lOGIC STAlES
ifS'"

'3

6.2K

-..

,--~_-,I

V"

TO'"

6.2KQ .

-5.ZV
IREf ",UlmA

LOGIC INPUT CURRENT VS. INPUT VOLTAGE

BASIC NEGATIVE REFERENCE OPERATION

1....
~

DAC-08BC

....

ii'

<>-'--'V\/\r'-1

15

4.0

"'::>u
--To

0;: 2.0
u

1

i3

9

iFS" - VRH , 255
R REF 256
(R,S" R REF)

OL--L__
-12

-10

~~

__

J-~~-L~~

-8.0 -6.0 -4.0 -2.0

2.0

__

~

4.0

LOGIC INPUT VOLTAGE (VOLTSI

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

2-5

DAC-OB8
APPLICATION DIAGRAMS (Cont'd)
BASIC UNIPOLAR NEGATIVE OPERATION

BASIC BIPOLAR OUTPUT OPERATION
+ 1O.000V

MSB

MSB

LSB

LSB
10K

EO

'REF

=

2.000 rnA

'REF = 2.000 rnA

'0

DAC-OBBC

14

DAC-OBac

14

5K

RANGES EO = OV TO - 9.960V
'0 = OTO -1.992mA

RANGES EO = - 9.922V TO + lO.OODV
'0 = -0.9920 rnA TO + 1.0 rnA

EO

SEE CODING TABLE

SEE CODING TABLE

VOLTAGE OUTPUT OPERATION

RECOMMENDED FULL SCALE ADJUSTMENT CIRCUIT

5K

DAC-088C

DAe-oeBM

LQWT.C.
+ lOV

4.5K
IREF<+)~

'REF

=

2 rnA

L-______
DA_C-_OO_BC____

~:~

DAc-oaBC

>___",'V'-------j15

5K

~-.~
BINARY

OTO +lOV

,

SOKO
POT

APPAOX. 5K

EO

CALIBRATION AND CODING TABLES
CALIBRATION PROCEDURE

BIPOLAR OPERATION-OFFSET BINARY CODING
For 10k load resistors from pins 2 and 4 to + 10V.

1. Select the desired output range by means of the feedback
resistor of the external operational amplifier and the externally programmed reference current.
2. Zero and Offset Adjustments
For unipolar operation, set all digital inputs to "a" and adjust
the output amplifier zero adjustment for zero output voltage.
For bipolar operation, set all digital inputs to "a" and adjust
the offset adjustment for the negative full-scale voltage
shown in the Coding Table.
3. Gain Adjustment
For either unipolar or bipolar operation, set all digital inputs to
"1" and adjust the gain adjustment for the positive full-scale
voltage shown in the DAC-088 Coding Table.

INPUT
1111
1110
1100
1000
0100
0000
0000

UNIPOLAR OPERATION-STRAIGHT BINARY CODING
For 5k load resistors at pins 2 and 4
INPUT
1111
1110
1100
1000
0100
0000
0000

2-6

CODE
1111
0000
0000
0000
0000
0001
0000

Eo
-9.961
-8.750
-7.500
-5.000
-2.500
-0.039
0.000

Eo
0.000
-1.211
-2.461
-4.961
- 7.461
-9.922
-9.961

10

10

1.992
1.750
1.500
1.000
0.500
0.008
0.000

0.000
0.242
0.492
0.992
1.492
1.984
1.992

CODE
1111
0000
0000
0000
0000
0001
0000

Eo
- 9.922
- 7.500
- 5.000
0.000
+ 5.000
+ 9.922
+ 10.000

Eo

+ 10.000
+ 7.578
+ 5.078
+ 0.078
-

4.922
9.844
9.922

ORDERING INFORMATION
MODEL NO.
DAC-088C
DAC-088M

OPERATING
TEMP. RANGE
O°C to + 70°C
- 55°C to + 125°C

PACKAGE
Plastic
Ceramic

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC-0805
Ultra-Fast, Low-Glitch
Composite Video OfA

FEATURES
• Composite Video Output
• a-Bit resolution
• a Nanoseconds maximum settling
time
• Single supply operation
• Industry-standard pin-out

GLITCH ADJUST

10% BRIGHT

10% BRIGHT
CURRENT
SWITCH

REFERENCE WH'TE

GENERAL DESCRIPTION

•

DATA STROBE

DATEL:s DAC-OB05 is a high performance,
ultra-fast, hybrid digital-to-analog converter specifically designed for video and
graphic display applications. This converter has the self-contained digital sync,
blanking, 10% bright, and reference white
control inputs required for compatibility
with EIA standards RS-170 and RS-343A.

BIT' IN (MSB)
BIT 21N
81T31N
BIT 41N

ECl
INPUT
REGISTERS

BIT SIN
BIT61N

ECl
CURRENT
SWITCHES

R/2R
lADDER
NETWORK

16

OUTPUT

BIT 71N
BIT 8 IN (lSB)

The DAC-OB05 provides B bits of resolution, or 256 levels of gray scale, and settles in a maximum of only B nanoseconds.

COMPOSITE SYNC

The DAC-OS05 uses high speed ECl input
registers and current switches to minimize
time skew and glitch amplitude. Glitch
energy, typically 50 pV-S, may be optimized for individual system performance
with the glitch adjust input.
Other important features include an output impedance of 750, full-scale output
current of -17 mA, ±'/2 lSB linearity and
guaranteed monotonic performance.
Model DAC-OS05 is cased in a 24-pin ceramic package and operates over the
industrial, -25°C to +S5°C temperature
range. Power requirement is -5.2V. The
ultra-high speed, low cost, small size and
circuit completeness of these converters
make them an excellent choice for applications including high resolution raster
scan graphics displays (both color and
monochrome) TV video reconstruction,
and function generation.

MECHANICAL DIMENSIONS
INCHES (MM)

I

f-0~~,AX-j
~I
o 150M"
1381

r

-l-

-'---.

,
,
,
,
,
,
,
,
,
,
DOT ON TOP

0.190(4,8) MAX

f

KOVAR

112

P1N 1

)

0010)( 0018

·1

REFERENCES

INPUT/OUTPUT CONNECTIONS

,

13'

,,
,

BOTTOM
VIEW

1-' 1
1_ 0600

,
,
,
,
,
,

24,

J

I - 115,211

1

'200

1,"

"

SPACES
AT 0 100
EA (2.5)

MAX

33. 3

PIN FUNCTION
1 Ground
2 - 5.2V S~llQl'l
3 Bit 1 MSB
4 Bit 2
5 Bit3
6 Bil4
7 Dala 51 robe
8 Bil5
9 Bil6
10 Bil7
11 Bil8 LSB
12 Ground

PIN FUNCTION
13 Glitch Ad'ust
14 Ground
15 Ground
16 Ground
17 Ground
18 AnalQgOuJQ.ul
19 Co~osite §ync
20 Setup
21 10% Bri hi
22 Com.Q9site Blanki'l9.
23 Reference White
5.2V Supply
24

0'00
--0
0 '00

1__

1(2,51

NOTE: PINS HAVE 0.025 INCH STANDOFF FROM CASE, ±O.Ol"

DATEl, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrlX 174388/FAX (508) 339-6356

2-7

DAC-0805
FUNCTIONAL SPECIFICATIONS

TECHNICAL NOTES

Typical at +2SoC, -S.2V dc supply, unless otherwise noted.
DAC-080S

DIGITAL INPUTS
Resolution ...........................
LSB Weight, Voltage ...................
Current. ..................
Coding ..............................
Logic Compatibility ....................
Input Logic Level, Bit ON, "0" ...........
Input Logic Level, Bit OFF, "1" ..........
Logic Loading1 ........................
Data Strobe Input: Set Up Time, min ......
Hold Time, min ........
Propagation Delay .....
Logic Loading ........

8 bits
2.5 mV
6.7 pA

Complementary Binary
ECL
-1.7V
-0.9V
5 pF and 50 kll to - 5.2V
2.5 nsec.
1.5 nsec.
3 nsec.
50 pF and 5 kll to -5.2V

SETUP CONTROl' (Pin 20)
Setup Grounded .......................
Setup Open ..........................
Setup at - S.2V .......................

a mV (0 IRE Units)
71 mV (10 IRE Units)
142 mV (20 IRE Units)

OUTPUTS
Output Current ........................
a to -17 mA
Output Voltage, 7SIl Load' .............. a to - 600 mV a to - 630 mV a to - 637.5 mV
Compliance Voltage
±1.1V
Output, 10% Bright (Pin 21) = Logic "0"
Current ............................
-1.9mA ±5%
Voltage ............................
-71 mV ±S%
Output, Composite Sync (Pin 19) =
Logic "0"
Current ............................
-7.6 mA ±S%
Voltage ............................
-286 mV ±S%
Output, Composite Blanking (Pin 22) =
Logic "0"
Current4(±1%) .....................
-17 mA, -18.9 mA or -20.8 mA
Voltage4 (±HiJ) .....................
- 637.S mV, - 708. 7S mV or - 780 mV

...................

PERFORMANCE

1. The use of a good ground plane around
the device must be used. A double
sided copper board with ground plane
on one side and conductors on the
other side is recommended. All ground
pins should be soldered to the ground
plane as close as possible to where
they leave the package.
2. Standard 24-pin sockets are not recommended for use with the DAC-080S
series. If sockets must be used, use
only spring-loaded pin sockets for each
pin. Insert through plated holes on the
printed circuit board and solder them to
pads on the conductor side.
3. The power supply should be bypassed
with a 1 p.F or larger tantalum capacitor
and a 0.1 p.F high frequency ceramic
capacitor as close as possible to the
power pin (within 'h inch).
4. A well regulated and ripple free, - S.2V
power supply must be used for maximum accuracy. The output of these
devices will change 1 mV for every 1
mV of power supply change. Therefore,
it is important that the supply ripple be
less than 'h LSB or less than 1 mV for
the DAC-080S. The use of a stable
power supply will also enhance the
accuracy of the devices over the effects
of time and temperature.

Absolute Accuracy' ....................
Integral Linearity Error ..................
Integral Linearity Tempco ...............
Monotonicity .........................
Zero Offset Error ......................
Zero Offset Tempco ....................
Gain Tempco .........................
Voltage Output Settling Time, max ........

±'12 LSB
± 'Ii LSB
16 ppm of FSRloC
Guaranteed
0.9 mV
6 ppm of FSR/oC
17 ppm/oC
8 nsec. to
0.4% GS

S. The minimum set-up time for these
D/A's is specified at 2.S nanoseconds;
this is the time the data must remain on
the inputs before the strobe is applied .
A minimum strobe hold time of 1.S nanoseconds must be allowed to ensure
that the data is latched.

Output Slew Rate ......................
Output Rise Time ......................
U~date Rate" .........................
G itch Energy' ........................
Digital Input Settling Time" ..............

200 V/p.sec.

6. The DAC-080S has extremely low glitch
energy levels and normally needs no
adjustment. However, if glitch adjustment is required, an external 2000
trimpot should be connected to the
GLITCH ADJUST (pin 13) as close to
the pin as pOSSible, and adjusted for
equal positive and negative peak glitch
signal levels. (See typical connections.)

3 nsec.
100 MHz
SO pV - S
8 nsec.

POWER REQUIREMENTS
Power Supply Voltage ..................
Power Supply Range ...................
Quiescent Current .....................

-S.2V
-4.75V to -S.4SV
320 mA

PHYSICAUENVIRONMENTAL
Operating Temperature Range ...........
Storage Temperature Range .............
Package Type ........................
Pins .................................

-2SoC to +8SoC
-SsoC to + 12SoC
24-Pin Ceramic DIP
0.010 x 0.018 inch Kovar

FOOTNOTES:
1. Excepl Dala Strobe input (Pin 7).
2. Setup refers to the difference between the reference black level and the blanking level.
3. The difference between the full·scale output of 637.5 mV and 643 mV shown elsewhere in this data sheet is
because an LSB value of 2.5 mV was chosen for ease of calibration. This difference is well within the

tolerance allowed by RS·170.
4. The three currents and voltages correspond to setup levels of 0, 10 and 20 IRE units.
5. Absolute accuracy error is relative to gray scale and includes linearity.
6. These converters may be updated to a maximum of 125 MHz with some degradation of settling time.

7. Reducible to less than 25 pV - S with glitch adiustment.
8. Settling time to 10% of final value. Specified for sync, blanking, reference white, reference black and 10%
bright inputs.

2-8

GLOSSARY OF VIDEO TERMS
COMPOSITE VIDEO SIGNAL
The combined video signal, with or
without Setup, plus the Sync Signal.
VIDEO SIGNAL
The visually perceived portion of the
composite video Signal which varies in
gray scale levels from Reference White
to Reference Black. Also known as the
picture signal.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DAC-0805
GLOSSARY OF VIDEO TERMS (Con't)

CONNECTIONS AND PERFORMANCE

SYNC OR COMPOSITE SYNC SIGNAL
That portion of the composite video signal which synchronizes the scanning
process.

TYPICAL CONNECTIONS
STROBE IN
-5.2V
270f!

SYNC LEVEL
The peak level of the composite Sync
signal.
SETUP
The difference between the Reference
Black level and the Blanking level. Not
to be confused with setup as used in
conjunction with digital logic.
RASTER-SCAN
The basic method of sweeping across a
CRT, a line at a time, to generate and
display pictures as commonly used in
commercial TV in the USA.
MONOC~IROME

VIDEO
Conventional black-and-white television video in which the Z-axis, or intensity, of the beam is modified during
scanning to shade and/or outline
images.

BIT 1IMSB)

131----l.. ~

•

GE?$2H
ADJ.

1

I
I
I

,

1 8 1 - - - -G
,.--AC-IN
,-,-A=-DJ,--.--7-5"n OUTPUT

I
I

DAC·080S

BIT 8 (LSB)

'2 kn

1

L_~

11

__ _

1-...,....--1>--.._----0 - 5.2V
COMPOSITE SYNC-

19

COMPOSITE BLANKING

22

10% BRIGHT

21

REFERENCE WHITE

23

BLANKING LEVEL
The level which separates the Sync
portion from the video signal, with or
without Setup. This level is sometimes
also called the pedestal, back porch or
front porch. It usually refers to the level
which will cut off the CRT, producing
the blackest possible picture.

241-...,....---'

'OPTIONAL

NOTE: All digital inputs terminated
to - 5.2V through 2 kfl except
strobe.

REFERENCE BLACK LEVEL
The maximum negative polarity amplitude of the video signal.
REFERENCE WHITE LEVEL
The maximum positive polarity amplitude of the video signal.
10% BRIGHT LEVEL
A "Whiter than White" Level not within
the range of the normal picture.
Sometimes used for generating cursors
or outlines because it contrasts with all
gray shades including white.
GRAY SCALE
The discrete levels of the video signal
between Reference White and Reference Black levels.
COLOR VIDEO (RGB)
As used herein, this refers to the
method of generating color images by
combining the three primary colors of
red-green-blue (RGB). The associated
monitor would be identified as an
"RGB" monitor. Three OAC-0805
series 0/A converters are required to
drive such a monitor, one each for red,
green and blue.

COMPOSITE VIDEO OUTPUT SIGNAL

-----------r--------- .-----

__ 1~ __________________ _

~ ~

-

- - -

10"" BRIGHT LEVEL

a,071V

1
Q.643V

Q.714V WITH

~~;~E

STANDSAEj~~~lO IRE)

t - - - - --~~~:

= ~~1} ~
o 286V

1

::VEf:,~~EL~~~L

I
I

_ _ _ _ _ 1_
I

-

-

REFERENCE
BLACK LEVEL

LEVEL

I
_ ____

I
~

I

______ _
I

1-4------ SYNC. PORTION ~I"'" VIDEO PORTION ~I
I

-

- - BLANKING

SYNC
LEVEL

I

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-9

•

DAC-0805
APPLICATION
TYPICAL RASTER SCAN DISPLAY SYSTEM

r-------.

PGM

CPU

MEMORY
CONTROL

,
I

+
X&Y
CONTROL
CIRCUIT

MEMORY

1
X-AXIS

BUFFER
REGISTER

Y-AXIS

~'~
INPUTS

DAC-0805

Z-AXIS

CRT

The DAC-080S is particularly useful in raster scan display
systems. The above system functions as an intelligent peripheral to the host CPU, and drives a standard television
monitor.

The system consists of a MaS RAM memory buffer for storing
display data, a memory controller for updating the CRT display,
and a programmable microprocessor for graphics generation
and image manipulation.

DIGITAL CONTROL INPUTS
STROBE-(pin 7)
Logic "0" to Logic" 1" transition transfers digital input data to
the register.
SETUP-(Pin 20)
Three user programmable levels:
INPUT
1. Grounded
2. Open
3. -S.2V

BLANKING LEVEL
(from Reference Black)

o mV
-71 mV
-142 mV

IRE Units

o

COMPOSITE BLANKING-(Pin 22)
Logic "0" resets the input register to all "O's" and sets the output voltage negative by the amount of setup voltage with
respect to the Reference Black Level.

10
20

10% BRIGHT-(Pin 21)
Logic "0" causes output to go positive by 71 mV. The most
positive voltage remains OV absolute. All other levels are shifted
down by 71 mV.
REFERENCE WHITE-(Pin 23)
Logic "0" set the D/A's output to Full-Scale (Reference White
Level). This is OV absolute or 714 mV more positive than the
Blanking Level (643 mV more positive than the Reference Black
Level) with Standard Setup.
NOTE: This pin should be held at a logic "1" when the Composite Blanking input is activated.

2-10

COMPOSITE SYNC-(pin 19)
Logic "0" resets the input register to all "O's" and the output
voltage goes negative by 286 mV with respect to the Composite
Blanking Level.

ORDERING INFORMATION
MODEL
DAC-080SMR

RESOLUTION

SETTLING
TIME

8 Bits

8 nsec.

For military devices compliant to MIL-STD-883, consult the
factory.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC·330
10-Sit, Multiplying
D/A Converter
FEATURES
A Grnd

•
•
•
•
•
•
•

Vbl3S

AVs

0 Grnd

10-Bit resolution
160 MHz conversion rate
Multiplying - 14 MHz bandwidth
Eel compatible
Single (-5V) supply
low-power
low-glitch

APPLICATIONS
•
•
•
•
•
•

20

Graphic displays
High definition video displays
Ultra high-speed signal processing
Digital VTR
Digital attenuators
High-speed function generators

•

vout

'R
Network

GENERAL DESCRIPTION
16

A.Grnd

The monolithic DAC-330 is an ultra highspeed, 10-bit digital-to-analog converter.
This ECl-compatible device has a 160 MHz
update rate and a 14 MHz multiplying bandwidth capability.
The DAC-330 develops an output voltage of
-1.0V and can directly drive a 75Q
impedance load. Settling time is 5.2 nSec.
while glitch energy is a low 15
picovoltlsecond. Other features of this D/A
are integral linearity of 0.1% FS, and a
differential linearity of ±1/2 lSB maximum.

o to

MECHANICAL DIMENSIONS

Input coding of the DAC-330 can be
programmed for straight binary or complementary binary through use of the COMP
BIN control input line.
The DAC-330 is a low-power device requiring only a single -5.2V supply with a maximum current draw of 100 mAo The DAC-330
is packaged in a 28-pin plastic DIP and has
an operating temperature range of -20°C
to +75°C.

INPUTIOUTPUT CONNECTIONS
PIN

FUNCTION

PIN

FUNCTION

1

BIT 1 (MSB)

28

ANALOG GROUND

2

BIT2

27

3

BIT3
BIT4

26

VBIAS
ANALOG SUPPLY(-5.0V)

5

6

BITS
81T6

•
7

BIT7

8

BIT8

22
21

NlC
NlC
NlC
NlC
NlC

9

ANALOG OUTPUT

25
2.
23

BIT 6

20

10

BIT 10(LSB)

19

NlC

11

NlC
NlC

18
17

ANALOG GROUND (R-2R)

12

DIGITAL GROUND

13

CLOCK INPUT (CLK)

16

CODE INVERSE INPUT

I.

CLOCK INPUT

cD--~"""4-{) Vs(-S.2V)

-180
DAC 330
LSB

o-----110

AOUT 20

1---.,..-----0

AGND 18

1----'-,

-20
100k

10k

fMUl- -

DONO 17 I-~~.:.......,~,

100M

10M

1M

Multiplying input signal frequency (Hz)

Multiplying input/output characteristics

1........::r-~-113

(elk)

./'~-+--I14

(elk)

Figure 8. Multiplying Input/Output Characteristics
VO(FS) == 1.00V, with VEE"" -5.2V

DVs15 1--~-~-OVs(-S.2V)

-2.0

~

Figure 7. Connection Diagram

I I

'~"

r-~I,~I

:2

f IL
-1.0

!
I

ORDERING INFORMATION

MODEL
DAC-330

2·14

OPERATING
TEMPERATURE
RANGE

~

V

~ ...

f-, ",&O'Y"

~

~:;.1:

I " 1~'\

~~ ......

~

...
.....

~

>

0.5

1.0

1.5

VSIAS-VEEM

- - - - Linear Operati~g Area

Output voltage full-scale v.s. VREF -Vs

Figure 9. Output Voltage Full-Scale vs VREF - Vs

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

DAC·562
Monolithic, High Performance
12·Bit D/A Converter

FEATURES
• 12-Bit resolution
• 300 Nanoseconds settling time
• ± 10 ppm/oC maximum tempco
• 5 Output ranges
• ± V. LSB linearity
• 562 Pin compatibility

DIGITAL INPUTS

LOGIC
+SUPPLY SELECT

MSB

LSB

1

2

3

4

5

6

7

8

9

10

11

12

BIT NO.

GENERAL DESCRIPTION
The DAC-562 is a new high performance
monolithic 12-bit D/A converter fabricated
with advanced bipolar technology. The circuit uses a precision, laser-trimmed thin
film R-2R ladder network driven by equalvalue switched current sources to achieve
% LSB typical linearity, 300 nanoseconds
setting time, and ± 10 ppm/oC maximum
gain tempco.

REF.

BIPOLAR
OFFSET OUT

The DAC-562 is completely pin and function compatible with industry standard
562 D/A converters. The package is a
24-pin hermetically sealed ceramic DIP;
power requirement is +5V to +15Vand
-15V dc. The DAC-562C operates over a
O°C to + 70°C temperature range.

BIPOLAR
OFFSET IN

REF.

The DAC-562 operates from TTL or CMOS
input logic and provides a 0 to 2 mA or ± 1
mA output current. The converter contains
tracking feedback and bipolar offsetting
resistors to provide five output voltage
ranges when used with an external operational amplifier: 0 to + 5V, 0 to + 1OV,
± 2.5, ± 5V, and ± 10V. Since these
resistors closely track the R-2R ladder with
temperature, gain stability of better than
10 ppm/oC is achieved. Differential linearity error is % LSB typical and % LSB
maximum, with output monotonicity guaranteed over the operating temperature
range.
Output settling time for a full-scale change
to % LSB is 300 nanoseconds typical and
400 nanoseconds maximum.

THIN-FILM R·2R
LADDER NETWORK

IN

GND.

-SUPPLY

MECHANICAL DIMENSIONS
INCHES (MM)

T

24

c

13

DATEl

~--l-

0500

0610

112,71

115,~1

~~"rn~D~A,C'T56r2~~",,~
i~~~T

I N PUT/OUTPUT
CONNECTIONS

PIN
1
2 -3
4
5
6
7
8
9
10
11
12

PIN
13
14
15
16
REFER~~.N_Qf=JI\J 17
- SUP~PLY __ 18
BIP OFF IN
19
BI~QFF OUT-=: 20
OUTPUT
21
22
lQVR...6NGE
23
2o.V_RANG_E
GROUND
24

FUNC!I()H___
+ SUF'P_lL __
L,QQlg SELECT
REF
GROUND
- " - - - - - _.. _N.C.
--

-~--------

FUNCTlO_t>!~ ~

BIlJ11f':J[1S.BJ
BIT 11 IN
BIT 10 IN

El.11_911'J
BITJ3LN_
BIT 71IL_._
BIT GIN
BIT 5 IN
BIT 4 IN
-- -- -----------'BIT 3 IN
BIT- - -2
IN
-----------BIT 1 IN (MSB)
~--

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

2-15

DAC-562
ABSOLUTE MAXIMUM RATINGS
Positive Supply, pin 1 .............. .
Negative Supply, pin 6 .............. .
Reference Input, pin 5 .............. .
Reference Ground, pin 3 ............ .
Digital Inputs, pins 13-24 ............ .
Logic Select Input, pin 2 ............ .
Output, pin 9 ..................... .
Resistors, pins 7, 8, 10, 11 .......... .

DAC-562C
+20V
-20V
±Supply
OV
-IVto +12V
-IVto +12V
+ Supply. - 5V
±Supply

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, +5V and -15V Supplies, + 10V" reference unless otherwise noted.
INPUTS

DAC-562C

Resolution ........................
Coding, unipolar output ..............
Coding, bipolar output ...............
Input Logic Level, bit ON (" 1")' .......
Input Logic Level, bit OFF ("1 ")' ......
Reference Input Voltage .............
Reference Input Resistance ..........

12 Bits
Straight Binary
Offset Binary
+2.0 min. at 100 nA max.
+0.8V max. at -100 pA max.
+10V
20 K{l

OUTPUTS
Output Current, unipolar ............
Output Current, bipolar ..............
Output Voltage Ranges, unipolar ......
Output Voltage Ranges, bipolar .......
Output Voltage Compliance ..........
Output Resistance ..................
Output Capacitance .................

Oto-2mA
±1 mA
o to +5V
Oto +10V
±2.5V
±5V
±10V
±IV
2 K{l
20 pF

PERFORMANCE
Linearity Error, max. ................
Linearity Error Over Temp., max .......
Differential Linearity Error, max ........
Monotonicity ......................
Gain Error, max." ...................
Unipolar Zero Error, max." ...........
Bipolar Offset Error, max." ...........
Gain Tempco, max.- ................
Zero Tempco, max.- ................
Bipolar Offset Tempco, max.- .........
Settling Time to '12 LSB4 .............
Power Supply Sensitivity, max . .......

±% LSB
±1 LSB
±% LSB
Over Oper. Temp. Range
±0.25%
±0.05%
±0.25%
± 10 ppm/oC
±2 ppmloC
±4 ppmloC
300 nsec. typ., 400 nsec. max.
± 3.5 ppm of FSR/% Supply

POWER REQUIREMENTS
Rated Power Supply Voltage ..........
Positive Supply Range- ..............
Negative Supply Range ..............
Power Supply Quiescent Current,
max. s

..........................

+ 5V dc, - 15V dc
+4.75V to + 16.5V
-15V dc ± 10%
+ 15 mA, -23 mA

PHYSICAUENVIRONMENTAL
Operating Temp. Range .............
Storage Temp. Range ...............
Package, Hermetically Sealed ........

O°C to + 70°C
-65°C to + 150°C
24 pin ceramic DIP

• Specifications same as first column
FOOTNOTES:
L + Supply must be +5V ±50f0. For operation with CMOS logic, see Technical Note 1.
2. Adjustable to zero using external potentiometers. Specified error is for 100 ohm trim resistors and external
operational amplifier using internal feedback resistor.
3. Using external operational amplifier and internal feedback and offset resistor. Zero TempeD and Bipolar

Offset Tempeo are in ppm/oC or FSR (Full Scale Range)
4. For full·scale change: all bits ON·to·OFF, or all bits OFF·to·ON.
5. Maximum Pos~ive Supply Voltage is + 16V for high level logic only, I.e., when Pin 2 is tied to Pin t. See

TECHNICAL NOTES

1. For TTL input logic; pin 2 should be connected to pin 12 and the + supply must
be +5V dc (±5%). For CMOS input
logic, connect pin 2 to pin 1 and use any
+ supply voltage from +9.5V to + 12V
dc. CMOS threshold levels are then +
Vs x 0.7 for bit ON and + Vs x 0.3 for
bit OFF. Logic input current is the same
as that specified for TTL.
2. Gain and bipolar offset errors are adjustable to zero by means of two 100
ohm trimming pots. The adjustment
range is ± 0.3% of FSR for gain and
± 0.6% of FSR for bipolar offset. The
unipolar zero error is adjustable to zero
by means of the offset adjustment of
the external output amplifier.
3. The output voltage compliance range
of ± 1V should not be exceeded or else
accuracy will be affected. If a resistor
load is driven instead of an operational
amplifier summing junction then the
maximum resistor value is 500 ohms
for unipolar operation and 1K ohms for
bipolar operation.
4. Output settling time is specified for current output and is measured with a
small current sampling resistor to
ground (100 ohms). Voltage output settling time depends on the output operational amplifier used. DATEL's AM-500
is recommended for about 500 nanoseconds settling and AM-452-2 is recommended for about 1.5 microseconds
settling. Both should be used with a
3-20 pF variable compensating capacitor across the feedback resistor which
should be adjusted for optimum settling
time.
5. For best high speed performance, both
power supplies should be bypassed
with 1 p.F electrolytics in parallel with
0.01 p.F ceramic capacitors as close as
possible to the ± supply pins.
6. The gain and bipolar offset temperature
coefficients are specified with the internal feedback and offset resistors used
in conjunction with an external operational amplifier. This is because these
resistors track the R-2R ladder with
temperature
and
therefore
the
tempeo's do not depend on absolute
resistor tempco. The tempco of the external + 10V reference must also be included in the total converter tempco,
however.
7. The DAC-562 wideband output noise
with all bits ON is typically 100 p.V peakto-peak over 0.1 Hz to 5 MHz.

Technical Note 1.
6"

2-16

Allow 30 seconds

warm~up

time.

DATEL. Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC-562
UNIPOLAR OPERATION-See Output Range Selection Table
+5VDC

GAIN
ADJUST

-15VDC

DAC-562 EQUIVALENT CIRCUIT

+
10V
OUTPUT
10 TO +10VI

"FOR VALUE SEE OUTPUT
RANGE SELECTION TABLE

TTL
CONNECTION -"

OUTPUT VOLTAGE RANGE SELECTION (See Connection Diagrams)
OUTPUT
VOLTAGE
RANGE
o to +5V
o to + 10V
±2.5V
±5V
+10V

RB , BIAS
A
A
A
A
A

&
&
&
&
&

CONNECT THESE
PINS TOGETHER
10 9 & 11
10
10 9 & 11 8&9 7&8
10
8&9 7&8
11
8&9 7&8

COMPo
RESISTOR'
1.11kfl
1.43 kfl
1 kfl
1.25 kfl
1.43 kfl

·Carbon composition resistor value used from amplifier
positive input terminal to ground to compensate for offset
due to bias current.

BIPOLAR OPERATION-See Output Range Selection Table
+5VDC

GAIN
ADJUST

-15VDC

DAC-562 EQUIVALENT CIRCUIT

+
10V
OUTPUT
±5V

TTL
CONNECTION -"

"FOR VALUE SEE OUTPUT
RANGE SELECTION TABLE

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 33S

•

DAC-562
CALIBRATION AND APPLICATION

CIRCUIT FOR FAST VOLTAGE OUTPUT
(:::::1.5 !,SEC. SETTLING)

CODING TABLE-See Calibration Procedure
3-20pF

C,'

o to

INPUT CODE
1111 1111 1111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0001
0000 0000 0000

+5V
+4.9988V
+3.7500
+2.5000
+ 1.2500
+0.0012
0.0000

OUTPUT VOLTAGE RANGE
±2.5V
±5V
+2.4988V
+4.9976V
+ 7.5000
+ 1.2500
+2.5000
0.0000
+5.0000
0.0000
+2.5000
-1.2500
-2.5000
-2.4988
-4.9976
+0.0024
-2.5000
-5.0000
0.0000

o TO

+10V
+9.9976V

±10V
+9.9951V

+5.0000
0.0000
-5.0000
- 9.9951
-10.0000

DAC·562
~~~-Q

CALIBRATION PROCEDURE

f

'ADJUST FOR OPTIMUM
SETTLING

OUTPUT
OTO +10V)

ZERO ADJ,

+15V

UNIPOLAR OPERATION
1. Set all digital inputs low. Adjust the output amplifier offset for
o volts output.
2. Set all digital inputs high. Adjust Gain trimming pot for an out·
put of + FS - 1 LSB.
FS -1 LSB = + 9,9976V for 0 to + 10V range.
= + 4,9988V for 0 to + SV range.

+10V REFERENCE CIRCUIT
R,
3.57K M.F.

+ 6.4V t-'VVv-----j

.:r-t-------0
+15V

50K

OUTPUT
OTO +10V

t

910K
ZERO
ADJ.

1.43K

DAC·S62C

OPERATING
TEMP. RANGE

o to

+ 70°C

ACCESSORIES
Part Number

Description

TPSO-

Trimming potentiometer

'ADJUST FOR OPTIMUM
SETTLING

--15V

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DAC-608, DAC-610, DAC-612
Microprocessor-Compatible,
Double-Buffered D/A
Converters
FEATURES
•
•
•
•

Microprocessor-compatible
Double-buffered inputs
8-, 10- and 12-Bit resolution
500 Nanoseconds settling timeDAC-610
• 4-Quadrant multiplication
MSB

GENERAL DESCRIPTION
DATEL's
DAC-60B,
DAC-610
and
DAC-612 are low cost monolithic B-,
1O-and 12-bit multiplying D/A converters
designed to operate directly with most
popular microprocessors. Double-buffered
inputs allow the converters to output an
analog voltage corresponding to one
digital word while holding the next, permitting simultaneous updating of multiple
D/A's via a common strobe signal. The
converters appear as a memory location
or 1/0 port to the microprocessor and thus
do not require interfacing logic. All models
will operate as normal D/A's for nonmicroprocessor based applications.
Excellent temperature tracking characteristics are provided by precision siliconchromium R-2R resistor ladder networks.
Output settling time for a full-scale change
to % LSB, is as low as 500 nanoseconds
and the maximum linearity error on all
models is ± % LSB. Monotonicity is
guaranteed over the full operating temperature range.
Other features include a low, 3 mV peakto-peak, digital feedthrough error, 30 mW
power dissipation and single supply operation. The reference input is selectable over
a range of ± 10V and may also be used as
the analog input for four quadrant multiplication applications.
The DAC-612C is packaged in a 24-pin ceramic DIP. Models DAC-60B and DAC-610
are packaged in a 20-pin plastic DIP. All
units are specified to operate over the commerical 00 C to +70 0C temperature range.
These devices are an ideal choice for innumerable applications involving industrial
process control, programmable attenuators,
audio signal processing and low frequency
sine wave generation.
CAUTION: These devices contain CMOS
circuits and should be handled with standard anti-static procedures.

C f----o

1C

LSB

~
INPUT
REGISTER

f----t
O/A
REGISTER

It

:-----

f----t

~

I-I--

O/A

•

8Pi

VREF
loul2
oull

ORFb

r
CONTROL
LOGIC

I
()

~R2

.S2

CS

8

VS
GNO

I

WRl

0_
JiR

Byle l/Byle 2

INPUT/OUTPUT CONNECTIONS
OAC·60S
PIN

FUNCTION

OAC·612

OAC·610
FUNCTION

PIN

1

CS (CHIP SELECT)

1

CS (CHIP SELECT)

f-PIN

FUNCTION

1

CS (CHIP SELECT)

2

WRl (WRITE 1)

2

WR (WRITE)

2

WRl

3

ANALOG GROUND

3

BYTE llBYTE 2

3

ANALOG GROUND

4

013

4

XFER

4

015

5

012

5

015

5

014

6

011

6

016

6

Dl3
012

7

010 (LSB)

7

017

7

8

REFERENCE IN

8

DI8

8

011

9

FEEDBACK

9

019 (MSB)

9

010 (LSB)

10

DIGITAL GROUND

10

GROUND

10

REFERENCE IN

11

OUTPUT 1

11

OUTPUT 2

11

FEEDBACK

12

OUTPUT 2

12

OUTPUT 1

12

DIGITAL GROUND

13

017 (MSB)

13

REFERENCE IN

13

OUTPUT 1
OUTPUT 2

14

016

14

FEEDBACK

14

15

DIS

15

010 (LSB)

15

0111 (MSB)

16

014

16

011

16

0110
019

17

XFER (Trans. Cont!.)

17

012

17

18

WR2 (Write 2)

18

013

18

018

19

ILE (In. Latch ENB)

19

014

19

DI7

20

Vs

20

Vs

20

DI6

21

XFER (Trans. Cont!.)

22

WR2 (Write 2)

23

BYTE lIBYTE 2

24

Vs

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-19

DAC-60S/61 0/612
ABSOLUTE MAXIMUM RATINGS

DAC·608

Power Supply Voltage ••••••••.
Logic Input Voltage ••••...••..
Reference Input Voltage •....•..
Output Voltage •.•••••••••••..
Package DisSipation ....••..•..

PHYSICAL/ENVIRONMENTAL

DAC·610
+17V dc
Vs to ground
±25V
Vs to 100 mV
500mW

Operating Temp.
Range .... , .........
O·C to 70"C
Storage Temperature
Range ............ -65°C to + 150°C
Package Type:
DAC·608I610 ••... 20-pin plastic DIP
DAC·612 ........ 24-pin ceramic DIP

FOOTNOTES:

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, 15V Supply, Reference In = + 10V unless otherwise noted.
INPUTS

DAC·608

DAC·610

DAC·612

Resolution ...••••..•......•..
8 bits
10 bits
12 bits
Straight Binary
Coding, Unipolar operation ....•
Bipolar operation ......
Offset Binary
Input Logic Level,
bit ON ("1") ••••••.•.....•••
+2.2V minimum at + 10.,.A maximum
Input Logic Level,
+ 0.8V maximum at - 200 ,.A maximum
-.-l>it OFF ("0") . . . . . . . . • • . . . . .
CS (Chip Select) •......•..•... Active low state in combination with ILE enables the O/A
for Wri~J operation. Minimum pulse duration is 320
nsec .. CS must remain Iowan additional 10 nsec. after
_
Write Pulse returns high.
ILE (Input Latch Enable)' ••..... Active high state in combination with CS enables the O/A
for Write 1 operation. Minimum Pulse duration is 320
nsec. ILE must remain high an additional 10 nsec. after
Write Pulse returns high.
WRl (Write 1) ...•••.......•.. Active low state is used to load the digital data bits into
the input latch. A high ON WR1, and a high on ILE will
update the input latch. Minimum Pulse duration is 320
nsec.
WR2 (Write 2) ................ Active low in combination with XFER transfers available
data in the input latch to the O/A register. The data in the
O/A register is latched when WR2 is high. Minimum Pulse
Duration is 320 nsec.
Byte l/Byte 2 (Byte Sequence
Control)' ........••........ All locations of the input latch are enabled when this
control is high. When low, only least significant bits are
enabled. Pulse Duration is 320 nsec.
XFER (Transfer Control
Signal) .....••...........•. Active low in combination with WR2, will transfer the data
available in the input latch to the O/A register.
OUTPUTS
Output Capacitance, Output 13 ..
Output 23 ••
Output 14 ..
Output 24 ..
Output 1, Current Ranges .....•.
Output 2, Current Ranges .....•.
Feedthrough Error" •......•....

70 pF
200 pF
200 pF
70 pF
VREF
0
15 k!l 256
VREF
256-0
-15 k!l
256
3 mV P-P

60 pF
250 pF
250 pF
60 pF
VREF
0
15 k!l
1024
VREF
1024-0
15 k!l
1024
90 mV P-P

70 pF
200 pF
200 pF
70 pF
VREF
0
15 k!l
4096
VREF
4006-0
15 k!l
4096
3 mV P-P

PERFORMANCE
Linearity Error Maximum .......
Differential Linearity Error
Maximum ..................
Monotonicity .••........•..•..
Gain Error"
Zero Error" ..................
Gain Tempeo Maximum ........
Settling Time, Full Scale
change to ± Yo LSB ..........
Power Supply Rejection4 •••....

..................

± 'h LSB
±0.o18% FSR
Over operating temperature range
Adjustable to Zero
Adjustable to Zero
±6 ppm/oC
± 10 ppm/oC
±6 ppm/oC
1 I'sec.
±2 ppmN

500 nsec.
±30 ppmN

POWER REQUIREMENTS
Rated Power Supply Voltage ....
Power Supply Voltage Range ...
Supply Current Maximum

......

2-20

+ 15V de
+4.7V dc to + 15.75V dc
2mA

1 !'5ec.
±3 ppmN

1. OAC-60a only.
2. OAC-610/612 only.
3. All data inputs latched low. To achieve this low
leedthrough on the OAC-612, the metal lid must
be grounded. II the lid is left Iloating the
leedthrough is typically 6 mV.
4. All data inputs latched high.
5. "0" stands lor digital input.
6. Using internal feedback resistor.

TECHNICAL NOTES
1. The output operational amplifier to be
used should have as Iowa value of in·
put bias current as possible. DATEL's
AM·41 o operational amplifiers are
highly recommended for use with these
devices.
In order to maintain the specified tem·
perature tracking specifications, the
D/A's internal feedback resistor should
be used in the operational amplifier
feedback loop.
2. The voltage at the current outputs must
be as close to ground potential as
possible so that the changes in the applied digital codes do not affect the out·
put current linearity.
3. In fast data acquisition applications, the
addition of a 10 to 22 pF capacitor (Cc)
in parallel with the feedback resistor of
the operational amplifier may be required to minimize overshoot and ringing at the output.
4. Due to the rapid switching of internal
logic gates that respond to the input
changes, a narrow spike could flow out
from the current output terminals. In
order to minimize this effect, the input
register must always be used as the
data latch. Reducing Vs from + 15V to
+ 5V offers a factor of 5 improvement
in the magnitude of the feedthrough,
however, this causes a loss of internal
switching speed. Also, increasing
capacitor Cc (if being used) to a value
consistent with the actual circuit band·
width requirements, can provide a
substantial damping effect on any out·
put spikes.
5. For flow through operalion, (operation
with the buffers continuously enabled)
CS, WR1, WR2 and XFER must be tied
to ground and Byte l/Byte 2 (ILE for
DAC-608) must be high. This will allow

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·1194ITEL (508) 339·30001TLX 174388/FAX (508) 339·6356

DAC-60S/61 0/612
to Vs or ground in order to prevent
damage to the chip from static
discharge. If any of the digital inputs are
inadvertently left floating, the D/A will
interpret the pin as a logic "1".
8. The input registers of the DAC-610 and
DAC-612 are arranged to accept a left
justified data word from the microprocessor with 8 bits coming first and
the lower bits second. Left-justified
means that the binary point is assumed
to be located to the left of the most significant bit.
9. The use of good circuit board layout

both internal registers to follow the applied digital inputs, directly affecting the
device output.
6. For stand alone operation where control signals are generated by discrete
logic, double buffering can be controlle~pplying a logic "0" to CS
and XFER and a logic "1" to ILE
and pulling WR1 low to load data in the
input latch. Pulling WR2 low will then
update the analog output. A logic "1"
on either of these lines will prevent the
changing of the analog output.
7. All unused digital inputs should be tied

techniques are required for rated performance. Minimization of lead lengths
around analog circuitry is recommended. It is important that a good
ground be used. A single point ground
distribution technique for analog signals and supply returns will prevent
other devices in the system from affecting the output of the D/A's. Vs should
be bypassed as close to the Vs pin as
possible with a low inductance 1 pF tantalum capacitor.

CODING AND CALIBRATION
CALIBRATION PROCEDURE
FULL·SCALE ADJUST

UNIPOLAR

OUTPUT 1 b---1--N
OUTPUT
OUTPUT 2 b---...--It.-1

Zero Adjust-Set all data bits to logic "0" (logic" 1" if using output 2) and adjust the OFFSET ADJUST pot on the external
operational amplifier for O.OOOV.
Full Scale-Set all data bits to logic" 1" (logic "0" if using output 2) and set the FULL Scale ADJUST for an output equal to:
Vout = - Vref (N -l)/N, where "N" is equal to: 256 (DAC-608),
1024 (DAC-610) or 4096 (DAC-612).

UNIPOLAR CONFIGURATION
10k

BIPOLAR

OUTPUT

BIPOLAR CONFIGURATION

Zero Adjust-Set all data bits to logic "0" and adjust the OFFSET ADJUST for an output voltage equal to Vref.
Full Scale-Set all data bits to logic "1" and adjust the FULL
SCALE ADJUST for an output voltage equal to: Vout = Vref
(N-X)/X where "N" is equal to: 255 (DAC-608), 1023 (DAC-610)
or 4095 (DAC-612); and "X" is equal to: 128 (DAC-608), 512
(DAC-610) or 2048 (DAC-612).

'ONE GROUND ON DAC·610

OUTPUT CODING TABLES

UNIPOLAR OPERATION
INPUT CODE
LSB
MSB
111 ....... 111
110 ....... 000
100 ....... 000
010 ....... 000
000 ....... 000

IDEAL OUTPUT
- (VREF + 1 LSB)
-0.75 (VREF)
-0.5 (VREF)
- 0.25 (VREF)
0

BIPOLAR OPERATION
INPUT CODE
MSB
LSB
111 ..... .. 111
110 ....... 000
100 ....... 000
010 ....... 000
000 ....... 000

IDEAL OUTPUT
-VREF
+VREF
+VREF -1 LSB
-VREF + 1 LSB
0.5 (-VREF)
0.5 (+ VREF)
0
0
0.5 (- VREF)
0.5 (+VREF)
-VREF
+VREF

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-21

•

DAC·608/610/612
TIMING AND PERFORMANCE
TIMING DIAGRAM
ILE,

CS,

CS. (608)

1+-------32ons------~...10ns

BYTElIBYTE2. (610/612)

I+-------A----~

DATA BITS

---~

DATA VALID

MODEL
DAC·608
DAC·610
DAC·612

~

90ns
200ns
90ns

NOTE:

1. smtling time;s measured from the leading edge of the
WRpulse.
2. All digital controls are level actuated.

MECHANICAL DIMENSIONS
INCHES (MM)

T
r-r-~~TnTtrD~ALCn-6T1rr2C~rrrrr~
DATEL

.5N

.Il00

I~:~

12

'"
(33)

~
APPLICATIONS
Typical Connection to Popular Microprocessor Data Bus

The logic functions of the DAC-60B/61 0/612 have been oriented
towards an ease of interface with all popular microprocessors,
_r.~--~~-~~FEEDBACK

The devices are treated as a typical memory device or I/O
peripheral requiring no external logic in most systems due to the
timing and logic level convention of the input control signals,
C>-~--<>OUTPUT

OUT2p---V

~----~X~F~ER~__~n_--~

2-22

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DAC-60S/61 0/612
DAC·608 Gain and Lhlearity Error
Variation vs. Reference Voltage

DAC·608 Gain and Linearity Error
Variation vs. Supply Voltage
0.4

0.2

~

1\

0

a:
a:

'\

w

0

~

w

z

"":r:u

~
w

t l r lN ,ERRr-

25~C

vs-v

Js

Cl
Z

""

I

TA 1=

ER~OR

w

V
VREF - 5V

-0.2

tlllNEIR,TY

0.2

a:
0
a:
a:

........ .'-.

V-

VREF = 2.5V

Cl

I

1

VREF= 5V

VREF = 2.5V

la:

0.4

lliNJARIT~ ER~OR

7

IT

V

Vs = 15V

V
vd = 15V

= 12V""

1

:r: - 0.2
u

I--

I

""

tlGAINTERROR
TA = 25'C
- 0.4

-0.4
10

12

Vs SUPPLY VOLTAGE (VDC)

VOLTAGE MODE OPERATION

14

16

10
VOLT AGE MODE
OPERATION

VREF. REFERENCE VOLTAGE (VDC)

DAC·610 Gain and Linearity Error
Variation vs. Reference Voltage

DAC·610 Gain and Linearity Error
Variation vs. Supply Voltage
+.1

+.1
\ tlllNEARITY ERROR

~

a:
0
a:
a:
w
~

+ .05

\
,- ~GAIN ERROR

w

Cl
Z

"":r:
u

- .05
1-+( =
-.1

+ .05

I

a:
0
a:
a:
w

I'100..

0

tlllNEARITY ERROR /

~

-'

~

tlGAIN ERRO';;'" ...........

w

Cl
Z

:r:
""

r

- .05

u

I-Vs = 15V

-I

-.1
10

12

14

REFERENCE VOLTAGE + V (VDC)

DAC·612 Gain and Linearity Error
Variation vs. Supply Voltage

DAC·612 Gain and Linearity Error
Variation vs. Temperature

?=
~

a:
0
a:
a:

0.005

-

w
~ -0.005

Vs = 15VDC

25'C

-J~ERRt- -

w

~

0.01

Mf~

a:
~

a:

0.005

w

tlct;1RRO~

~

~ -0.005

""i5 - 0.01

z

~
u

10

1

16

SUPPL Y VOLTAGE. Vs (VDC)

0.01

V

15

Vs - SUPPLY VOLTAGE (VDC)

-0.Q1

.

....

, ,"

-25 -15 5
TA -

25

45

tlllNEARITY

65 85

AMBIENT TEMPERATURE (OC)·

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

2·23

•

DAC-608/610/612
APPLICATIONS
MULTIPLE D/A SYSTEM

ANALOG

>----0 OUTPUT 1
0
E
C
0
0
E
R

ADDRESS
BUS

CS1
CS2
CS(n)
XFER

ANALOG

>---"'--Q OUTPUT 2

>---0 OUTPUT(n)
ANALOG
SYSTEM'
DAe DISABLE

SYSTEM WR
STROBE

0----,

0---------+-----------1
'TIE TO LOGIC 1 IF NOT NEEDED

TIMING DIAGRAM
DATA BUS

CS

====><~___

DA_T_A_V_A_L_ID
____

><===:~:--------------

-~\'-_ _ _- - ' /

WR1 & WR2 - - - - \

II

Lr----i/I

'-_ _ _ _-'"-. INPUT
...... LATCH
UPDATED

\
~
ANALOG ,'-_ _ _ _ _ _' OUTPUT K 'D/A REGISTER LATCHED
UPDATED

XFER----------------II~-~

ILE=LOGIC"1"

For simultaneous updating of multiple DIA's, the CS line
of each device is decoded individually. However, the converter
can share a common XFER.
The ILE function is very useful in applications where more than
one processor is being used. If another processor took control of
the data bus and control lines using the same addresses as the
first, a low on the ILE pin would latch the data in the input
register holding the outputs at their present state.

2-24

ORDERING INFORMATION
MODEL NO.

RESOLUTION

DAC·608C
DAC·610C
DAC-612C

8 Bits
10 Bits
12 Bits

OPERATING
TEMP. RANGE
O°C to + 70°C
O°C to + 70°C

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC·7134B, DAC·7134U
14-Bit Microprocessor-compatible
Multiplying D/A Converters

FEATURES

GENERAL DESCRIPTION

• 14-Bit linearity (0.003% FSR)

The DAC-7134 achieves true 14-bit linearity by combining a fourquadrant, multiplying DAC with on-chip, PROM-controlled correc·
tion circuits. The DAC uses thin-film resistors and CMOS circuitry
for stability while the PROM-controlled correction circuit eliminates
errors introduced by the thermal stresses of packaging.

• Microprocessor-compatible with doubled-buffered
inputs
• 3 Microsecond maximum output current settling time (0.9I'S
typical)

There are two versions of the DAC-7134, both represented by the
block diagram, Figure 1. The DAC·7134U is programmed for unipolar operation while the DAC-7134B is programmed for bipolar
applications. Microprocessor bus interfacing is easy using standard memory write cycle timing and control signals. Two input
buffer registers are separately loaded with the 8 least significant
bits (LS register) and the 6 most significant bits (MS register). Their
contents are then transferred to the 14·bit DAC register, which controls the output switches. The DAC register can also be loaded
directly from the data inputs.

• Low power dissipation
• Full four-quadrant multiplication
• Gain Tempco of +1-8ppm/degree C maximum
• PROM-controlled correction circuits

There are two reference voltage inputs feeding the resistor ladder
network. The VREF input to the most significant bit of the DAC is
separated from the reference input to the remainder of the ladder.
For unipolar use, the two reference inputs are tied together. For
bipolar applications, the polarity of the MSB reference is reversed
through an external operational amplifier. This flexibility gives the
DAC a true 2's complement input transfer function. The DAC·7134
contains two resistors used along with the external op-amp to in·
vert the reference. The PROM is coded to correct for errors in these
resistors as well as the inversion of the MSB.

VAFL

VRFM
RINV

F

R

R

R

2R

RF.

F

2R

,
----~--~_+--~L-_+----------~--~L-------~-+----~_+~-o~UT
----~--~-4----~_+----------~--~L-------~-t------_+---oAGN~

AGNDF
C·DAC

.-----+-------------------t--tDECODE

PROM

-----oPROG

MSB
14·BIT DAC REGISTER
REGISTER
....------------+++-+-H------l A~~~~~

1--------0 A,

Ao

Cs
1--------0 WR

Do • • • • • • D7

08 •

Figure 1.

•

•

• 013

DAC-7134 Simplified Block Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-25

,
. " ".

DAC·7134B, DAC·7134U
MINIMUM

DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

TYPICAL

MAXIMUM

UNITS

+6.0

V de

2.5

rnA

500

mW

+70

DC

+150

DC

POWER

Supply Voltage:
v+ to DGND

-0.3V dc to + 7.5V dc

+/-15V dc
-0.1V dc to V+
25 mA
-0.3V to V +
+0.3V dc

FUNCTIONAL SPECIFICATIONS
Validal +25degreesC, +5VdcpowersuppIY,andVREF =
+ 10V dc, unless otherwise specified.
DESCRIPTION

MINIMUM

+3.5
1.0

Supply Current
(Excluding ladder)

Analog Signals:
VRFL' VRFM, RINV, RFB to DGND
lOUT, AGNDF, AGNDS
Current in AGNDS, AGNDF
Digital Signals:
__
AO' A 1, Do to 0 13, WR, CS, PROG

Supply Voltage
Range

TYPICAL

MAXIMUM

UNITS

Power Dissipation
PHYSICAL/ENVIRONMENTAL
Operating Temperature
Range

0

Storage Temperature
Range

-65

28-pin CERDIP only

Package

The timing diagram represented in Figure 2 shows the relationships between the various bus interface signals. These AC characteristics are listed in Table 1.

INPUT

Resolution

14

Logic Levels
Logical 0
Logical 1

2.4

bits

Logic Input Currents
Reference Input
Resistance

4.0

7.0

Reference Input
Voltage Range

0.8

V
V

1.0

"P-

10

K ohms
V

DETAILED DESCRIPTION

0.012
0.006
0.003

% FSR
% FSR
% FSR

The DAC-7134 consists of a 14-bit primary DAC, two PROMcontrolled correction DAC's, input buffer registers, and
microprocessor interface logic (refer back to Figure 1). The 14-bit
primary DAC is an R-2R thin film resistor ladder with N-channel
MaS SPOT current steering switches. Precise balancing of the
switch resistances, and all other resistances in the ladder, results
in excellent temperature stability.

2

ppm/DC

0.024
0.012
0.006

% FSR
% FSR
% FSR

8

ppm/DC

±12

Coding
Unipolar
Bipolar

straight binary
2's complement

ACCURACY
Non~linearity 1,2

J
K
L
Non-linearity
Temp. Coef.
Gain Error 1,2

1

J
K
L

Gain Error
Temp. Coel.

2

Monotonicity
J
K
L

bits
bits
bits

12
13
14

Settling Time

0.9

3

MSec.

Power Supply
Reiection

10

100

ppmlV

Output Current
Range

2.14

±3.75

Output Capacitance
DAC all O's
DACaIl1's

160
235

pf
pf

7

K ohm

250
500

MVP-P
MVP-P

True 14-bitlinearity is achieved by programming a floating polysilicon gate PROM array which controls two correction DAC circuits. A 6-bit gain correction DAC (G-DAC) diverts up to 2Pfo of the
feedback resistor's current to analog ground and reduces the gain
error to less than 1 LSB, or 0.006%.
The 5 most significant outputs of the DAC register address a
31-word PROM array that controls a 12-bitlinearity correction DAC
(C-DAC). For every combination of the primary DAC's most significant bits, a different C-DAC code is selected. This corrects summation errors (caused when more than one bit is turned on
simultaneously) and voltage non-linearity in the feedback resistor.

OUTPUT

Output Noise (Equiv.
Johnson Noise)
Feedthrough Error
DAC·7134U
DAC-7134B

rnA

FOOTNOTES:
1. Full-scale range (FSR) is 10 volts for unipolar mode. 20 volts (± 10 volts
for bipolar mode.
2. Using internal feedback and reference inverting resistors.

2-26

Figure 2.

DAC-7134 Timing Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield; MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DAC-7134B, DAC-7134U
Table 1.

PARAMETER (v+

= +5V de)

Table 2.

AC Characteristics

SYMBOL

MINIMUM (nS)

Pin Assignment and Function Description

PIN

DESCRIPTION

1

CHIP SELECT (active low).
Enables writing to the register.

Address write set-up time

TAWs

100

Address-write hold time

TAWh

0

2

WRITE, (active low). Enables writing to the register along with
CHIP SELECT.

Chip select-write set-up time

TCWs

0

3

BitO

4

Bit 1

5

Bit2

6

Bit3

Chip select-write hold time

TCWh

0

WRITE pulse width, low

TWR

200

Data write set-up time

TOWs

200

Data write hold time

TOWh

7

Bit4

S

Bit5

9

Bit6

10

Bit 7

11

BitS

12

Bit9

Least Significant Bit

•

INPUTOATA

0

BITS
High

= True

!

PIN DESCRIPTIONS
The input and output pins for both the analog and digital signals
used by the DAC·7134 are listed in Table 2 and shown in Figure 3.

DGNo

.F.
0,

13

Bit 10

14

Bit 11

15

Bit 12

16

Bit 13

17

Used for programming only. Tie to +5V de for normal operation.

18

VREF for lower bits

19

Summing node for reference inverting amplifier

20

VREF for MSB only (bipolar).

21

Feedback resistor for voltage output applications

22

Digital ground return

23

Analog ground force line. Carries current from internal analog
ground connections. Tied internally to AGNDS.

24

Analog ground sense line. Reference point for external circuitry.
Pin should carry minimal current; tied internally to AGNDF'

25

Current output pin

26

Positive supply voltage

27

Address 1

28

Address 0

RINV

VAH

0,

PROG

0"

013 (MSB)

011

012

Figure 3.

Most Significant Bit

I

I

Control register
lines

DAC-7134 Pin Configuration

ANALOG SECTION
-VAEF

The DAC-7134 provides both unipolar and bipolar operation. The
bipolar application circuit (Figure 4) requires one additional operational amplifier, but no external resistors. Two on·chip resistors
(RINV1, RINV2), together with the op-amp, form a voltage inverter which drives the MSB reference terminal (VRFM) to -VREF·
VREF is the voltage applied at the less significant bits' reference
terminal, VRFL. This reverses the weight of the MSB, and gives
the DAC a 2's complement transfer function. The op·amp and
reference connection to VRFM and VRFL can be reversed, without
affecting linearity, but a small gain error will be introduced. For
unipolar operation the VRFM and VRFL terminals are both tied
to VREF, and the RINV pin is left unconnected.

VREF

fN-------,

TO
REST OF
LADDER

Figure 4.

Bipolar Operation, with Inverted VREF to MSB

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-27

DAC-7134B, DAC-7134U
Since the PROM correction codes required are different for bipolar and unipolar operation, the DAC-7134 is available in two different versions; the DAC-7134U, which is corrected for unipolar
operation, and the DAC-7134B, which is programmed for bipolar
application. The feedback resistance is also different in the two
versions, and is switched under PROM control from "R" in the
unipolar device to "2R" in the bipolar part. These feedback resistors have a dummy (always ON) switch in series to compensate
for the effect of the ladder switches. This greatly improves the gain
temperature coefficient and the power supply rejection of the
device.

VREI' IN - - - _ - - - - ,

DATA
INPUTS

DIGITAL SECTION
Two levels of input buffer registers allow loading of data from an
8-bit or 16-bit data bus. The AO and A1 pins select one offour operations:
1. Load the LS buffer register with the data at inputs DO to D7,
2. Load the MS buffer register with the data at inputs D8 to
D13,
3. Load the DAC register with the contents ofthe MS and LS buffer
registers, and,
4. Load the DAC register directly from the data input pins. (See
Table 3).
The CS and WR pins must be low to allow data transfer to occur.
When direct loading is selected (CS, WR, AO and A1 low), the
registers are transparent and the data input pins control the DAC
output directly. The other modes of operation allow double buffered
loading of the DAC from an 8-bit bus.
These input data pins are also used to program the PROM under
control of the PROG pin. This is done in manufacturing, and for
normal read-only use the PROG pin should be tied to V + (+5V
dc).

Figure 5.

Table 4.

Unipolar Binary, Two-Quadrant Multiplying
Circuit

Code Table-Unipolar Binary Operation

DIGITAL INPUT
MSB

ANALOG OUTPUT
LSB

111 .................................. 111
110 ............... ..

... 000

1 00 ................................... 000
010

............... 000

000 .................................. 000

- (VREF + 1 LSB)
- 0.75

x (VREF)

- 0.5 X (VREF)
- 0.25 X (VREF)

o

Zero Offset Adjustment
(See Figure 5)
Table 3.

CONTROL LINES

Data Loading Controls

DAC-7134 OPERATION

Ao

A,

CS

WR

X

X

X

,

X

X

1

X

0

0

0

0

0

1

0

0

1

0

0

0

Load MS register from data bus

1

1

0

0

Load OAC register from MS and
LS register

No operation. device
not selected

.

1. Connect all data inputs and WR, CS, AO and A1 to DGND. (Connect pins 1 through 16, 27, and 28 to pin 22).
2. Adjust the offset zero-adjust trim-pot of op-amp A2, if used, for
a maximum of OV ±50J.lV dc at AGNDS.
3. Adjust the offset zero-adjust trim-pot of output op-amp A1 for
a maximum of OV ±50J.lV dc at VOUT-

Load registers from data bus
Load LS register Irom data bus

Gain Adjustment (Optional)

UNIPOLAR BINARY OPERATION

1. Connect ~ data inputs (pins 1 through 16) to V+ (pin 26).
Connect CS, WR, A1 and AO (pins 1, 2, 27, and 28 respectively) to DGND (pin 22).
2. Monitor VOUT for a -(VREF + 1 LSB) reading.
3. To decrease VOUT, connect a series resistor of 100 ohms or
less between the reference voltage and the VRFM and VRFL
terminals (pins 20 and 18).
4. To increase VOUT, connect a series resistor of 100 ohms or less
between OP-AMP A1's output and the RFB terminal (pin 21).

Figure 5 shows a typical circuit configuration for unipolar mode
operation using a DAC-7134U. With positive and negative VREF
values, the circuit is capable of two-quadrant multiplication. Table
4 presents a digital input code/analog output value' reference for
unipolar mode operation. The Schottky diode (HP5082-2811 or
equivalent) protects lOUT from negative excursions which could
damage the device, and is only necessary with certain high speed
amplifiers.

For applications where the output reference ground point is established somewhere other than at the DAC, a circuit similar to that
shown in Figure 6 could be used. Here, op-amp A2 removes the
slight error due to IR voltage drop between the internal analog
ground node and the external ground connection. For 13-bit or
lower accuracy, omit A2 and connect AGNDF and AGNDS directly
to ground through as Iowa resistance as possible.

Note: Data is latched on low-to-high transitions of either WR
orCS.

2-28

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC·7134B, DAC·7134U
YRH IN

---~---,

Table 5.
RFa 1"'.'-'- t _ - - - - - - - ,

Code Table-Bipolar (2's complement) Operation

DIGITAL INPUT

lOUT

1"25'--+---1

011.

ANALOG OUTPUT

LSB

MSB

.. ................... 111

010 ..

............. 000

000 ..

... 000

110 ..

. ...... 00 0

100 ..

..................... 000

DATA
INPUTS

DAC-7134

I

-

AGNOs

1"'.'-0- - - - - - - - - ,

/

+vREF

-VREF

+VREF-1LSB

-VREF + 1LSB

0.5(+VREF)

05(-VREF)

0

a

0.5(·vREF)

0.5(+VREF)

·VREF

+VREF

<
Offset Adjustment
(See Figure 7)

Figure 6.

Unipolar Binary Operation with Forced Ground

1. Connect all data inputs and WR, CS, AO and Al to DGND. (Connect pins 1 through 16, 27, and 28 to pin 22).
2. Set data to 00000 .... 00. Adjust the offset zero adjust trim-pot
of output op-amp Al for a maximum of OV ±501'V dc VOUT.
3. Connect D13 (MSB, pin 16) data input to V+ (pin 26).
4. Adjust the offset zero-adjust trim-pot of op-amp A2 for a maximum of OV ±SOuV dc at the RINV terminal (pin 19).

BIPOLAR (2's COMPLEMENT) OPERATION
Gain Adjustment (Optional)
Figure 7 shows a circuit configuration for bipolar mode operation
using a DAC-7134B. Using 2's complement digital input codes and
positive and negative reference voltage values, four-quadrant multiplication is obtained. Table 5 lists the digital input codes and their
respective analog output values for bipolar mode operation.
Amplifier A2, together with internal resistors RINV1 and RINV2,
forms a simple voltage inverter circuit. The MSB ladder leg sees
a reference input of approximately -VREF, so the MSB's weight
is reversed from the polarity of the other bits. In addition, the
DAC-7134B's feedback resistance switches to 2R under PROM
control.

1. ConnectCS, WR, A1 and AO (pins 1, 2, 27, and 28 respectively) to DGND (pin 22).
2. Connect DO through D12 (pins 3 through 15) to V+ (pin 26).
Connect D13 (MSB, pin 16) to DGND (pin 22).
3. Monitor VOUT for a -VREF + 1LSB reading.
4. To increase VOUT, connect a series resistor of 200 ohms or less
between op-amp Al's output and the RFB terminal (pin 21).
5. To decrease VOUT, connect a series resistor of 100 ohms or
less between the reference voltage and the VRFL terminal
(pin 18).

The resultant bipolar output range is +VREFto-(VREF + 1 LSB).
Again, the grounding arrangement of Figure 6 can be used.

APPLICATIONS

General Recommendations
Ground Loops
Careful consideration must be given to ground loops in any system with 14-bit accuracy. The current into the analog ground point
inside the chip varies significantly with the input code value, and
the inevitable resistances between this point and any external connection pOint can lead to significant voltage drop errors. For this
reason, two separate leads are brought out from this point on the
IC, and AGND F and AGND s pins. The varying current should be
absorbed through the AGND F pin, and the AGND s pin will then
accurately reflect the voltage on the internal current summing
point. Thus, output signals should be referenced to the sense pin
AGND s , as shown in the various application circuits.

DATA
INPUTS

Power Supplies

Figure 7.

Bipolar (2's Complement), Four-Quadrant
Multiplying Circuit

The V + (pin 25) power supply should have a low noise level, and
no transients exceeding 7 volts. Note that the absolute maximum
digital input voltage allowed is V + , which therefore must be applied before digital inputs are allowed to go high. Unused digital
inputs must be connected to GND or V + for proper operation.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194JTEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-29

•

DAC·7134B, DAC·7134U
Operational Amplifier Selection

The op-amp requirements can be readily met using an AM-7650
chopper stabilized device. For faster settling time, DATEL:s AM-460
or AM-462 can be used with an AM-7650 providing automatic offset null.

To maintain static accuracy, the lOUT potential must be exactly
equal to the AGND s potential. Thus, output amplifier selection is
critical, in particular low input bias current (less than 2nA),low offset voltage drift (depending on the temperature range) and low offset voltage (less than 25" V) are advisable if the highest accuracy
is needed. Maintaining a low input offset over a OV to 10Vdc range
also requires that the output amplifier has a high open loop gain
(AVOL >400k for effective input offset less than 25"V).

The output amplifier's non-inverting input should be tied directly
to AGND s . A bias current compensation resistor is of limited use
since the output impedance at the summing node depends on the
code being converted in an unpredictable way. If gain adjustment
is required, low tempco (approximately 50ppm/DC) resistors or trimpots should be selected.

The reference inverting amplifier used in the biopolar mode circuit must also be selected carefully. If 14-bit accuracy is desired
without adjustment,low input bias current (less than 1nA),low offset voltage (less than 50"V), and high gain (greater than 400k) are
recommended. If a fixed reference voltage is used, the gain
requirement can be relaxed. For highest accuracy (better than 13
bits), an additional op-amp may be needed to correct for IR drop
on the analog ground line (op-amp A2 in Figure 6). This op-amp
should be selected for low bias current (less than 2nA) and lowoffset voltage (less than 50"V).

PACKAGE DIMENSIONS
The DAC-7134B and DAC-1734U differ only in the programming
instructions. Therefore, the same package dimenSions, as shown
in Figure 8, apply to both model numbers. The device is available
only in a standard 28-pin CERDIP package.

't~;, r~~~:~
[ "OJ
:::T~iRIiTmjjt '~-ll
"= l

PACKAGE DIMENSIONS All dimenSIons in Inches (mIllimeters)

f-~

I

-

r-1.475 (37.465) MAX----j

Figure 8.

I

-I g:::~g:~: -J

~.~ (~~2::;J1

i

L..-I - JL,~ ~~I172721_1

0,110 !2.794J
0,090 (2.286)

0.060 (1,524)
0.045 11.143\

0.023
0.015 (0.3810)

0.610 (15.494\

28-Pin CERDIP Package Dimensions

1

ORDERING INFORMATION
DAC-7134

L:.,! "

12-8' U"~rity (U01% FSR)

K = 13-Bit Linearity (0.006% FSR)
L = 14-Bit Linearity (0.003% FSR)

=

B Bipolar Version
U = Unipolar Version

2-30

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

DAC·7523, DAC·7533,
DAC·7541
Monolithic 8·, 10·, and 12·Bit
Multiplying D/A Converters
FEATURES
• 8-, 10-, and 12-Bit resolution
• 150 Nanoseconds settling time
DAC-7523
• 4-Quadrant multiplication
• Low gain and linearity tempco's
• Single supply operation
• DTL/TTL/CMOS-compatible
• Industry standard pin-out

+v,

0
10k

•
I

10k

10k

REF·C

IN

DESCRIPTION

20k

DATEL'S DAC-7523, DAC-7533 and
DAC-7541 are monolithic 8-, 10-, and
12-bit multiplying digital-to-analog converters. These devices use advanced thinfilm-on-CMOS technology to fabricate a
highly stable thin-film R-2R resistor ladder
network and NMOS SPDT switches.
CMOS level shifters provide low power
DTU TTUCMOS compatible operation. All
that is required for most voltage output applications are an external voltage or current reference and output operational amplifier. All models are capable of four
quadrant multiplication and the inputs are
fully static protected.
Important features include a settling time
for the DAC-7523, DAC-7533 and
DAC-7541 of 150 nanoseconds, 600 nanoseconds and 1 microsecond respectively
to ± % LSB maximum. Maximum linearity
error tempco is 2 ppm/oC and feedthrough
error is ± % LSB maximum. Power supply
rejection is as low as 0.005% of FSR/%.
The devices require only a single supply
for operation. Power supply range is + 5V
dc to + 15V dc.
The combination of low cost, four quadrant
multiplication, full input protection and low
power dissipation make these devices an
ideal choice for many applications including digitally controlled gain circuits, attenuators, CRT character generation, programmable power supplies, motor speed
controls and low noise audio gain control
circuits.
The DAC-7523 and DAC-7533 are packaged in 16-pin plastic cases with the
DAC-7541 being packaged in an 18 pin
plastic case. All models are specified for
operation over the commercial, O°C to
+ 70°C temperature range.

20k

20k

20k

20k

' - - 2)GROUND

9f

~i?

(: f
,I

y

~OUTPUT2

I
I

I

I
I
I
I
I

I

~2

~3

(D0UTPUT 1

~1
IN

o

R'

:

------S¥N

IN

IN

FEEDBACK

IN

INPUT/OUTPUT CONNECTIONS
DAC·7523

-PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

FUNCTION
OUTPUT 1
OUTPUT 2
GROUND
BIT 1 (MSB)
BIT 2
BIT 3
BIT 4
BIT 5
BIT6
BIT 7
BIT 8 (LSB)
N.C.
N.C.

vs
REFERENCE IN
FEEDBACK

DAC·7533
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

FUNCTION
OUTPUT 1
OUTPUT 2
GROUND
BIT 1 (MSB)
BIT2
BIT3
BIT 4
BIT5
BIT6
BIT 7
BIT 8
BIT9
BIT 10 (LSB)

vs
REFERENCE IN
FEEDBACK

DAC·7541
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18

FUNCTION
OUTPUT 1
OUTPUT 2
GROUND
BIT 1 (MSB)
BIT2
BIT3
BIT 4
BIT5
BIT6
BIT 7
BIT 8
BIT9
BIT 10
BIT 11
BIT 12 (LSB)

vs
REFERENCE IN
FEEDBACK

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

2-31

DAC-7523/7533/7541
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, (Vs) ......•..••...
Logic Input Voltage Range •••••....
Reference Input Voltage Range .....
Output Voltage Compliance ...••...

DAC-7S23

-0.3V to Vs

DAC-7S33
+17V
Vs to GND
±25V
-0.3V to Vs

DAC-7541

-100mV to Vs

FUNCTIONAL SPECIFICATIONS
Typical at 2SoC, + 15V Supply, + 10V Reference unless otherwise noted.
INPUTS

DAC-7S23

DAC-7S33

DAC-7S41

8 Bits

10 Bits
Straight Binary
Offset Binary

12 Bits

Resolution ........•..•..........
Coding, Unipolar Operation .•••.•..
Coding, Bipolar Operation •..••....
Logic Threshold,
Bit ON (" 1"), min. . .........•...
Logic Threshold,
Bit OFF ("0"), max ....••..•.....
Logic Input Current, max. 1 •••••••••
Input Capacitance, max •....••....•
Reference Input Voltage Range .....
Reference Input Resistance2 •••••••

·
·
··
··
·

2.4V
0.8V
±1~

4 pF
±10V
10 kll

·
·
··
··
·

OUTPUTS
Output Voltage Compliance .••.....
Output Capacitance, output 1,
max.' •...•..••..•••..••...•••
Output Capacitance, output 2,

max. 3

••••••.•••••••.••.•••••.

Output Capacitance, output 1,
max. 4 . . . . . • . . . . . . • . . . . . . . . . . .
Output Capacitance, output 2,
max.- •••.•..•..•....•...••.•.

-100 mV to Vs

·

100 pF

100 pF

tOO pF

30 pF

35 pF

60 pF

30 pF

35 pF

60 pF

100 pF

100 pF

200 pF

.,.

±v. LSB
2 ppm/DC
±t.4% of FSR
15 ppm FSR/oC
±50 nA

±0.3% of FSR
15 ppm fSRloC

PERFORMANCE
Non Linearity, max. S

• • • • . • . . • • • . . •

Non Linearity Tempco, max. s . . . . . . .
*
Gain Error, max.' ...•...•.......•. ± 1.5% of FSR
Gain Error Tempco, max.•......... 10 ppm FSR/oC
Output Leakage Current, max. 7 • • • • •
•
Output Current Settling Time,
max.. ........................
150 nsec.
Feedthrough Error, max.' •.........
Power Supply Rejection ........... 0.02% FSR/%

··

600 nsec.
±v. LSB
0.005% FSR/%

0.01% FSR/%

100~

·

+5V to + 16V
2 mA

2 mA

··

O°C to +70°C
-65°C to + 150°C
16-Pin DIP

IS-Pin DIP

t ,,;ec.

TECHNICAL NOTES
1. The digital control inputs are zener protected, however, permanent damage
may occur to unconnected units under
high electrostatic fields. All unused
devices should be kept in conductive
foam at all times.
Unused digital inputs must be connected to Vs or ground for proper operation of the device. Voltages higher
than Vs or less than ground should not
be applied to any terminal except Vref
or damage may occur.
2. Static performance of these devices
depends on output 1 and output 2 (Pins
1 and 2) being exactly at ground potential (Pin 3).
3. The output amplifier should be selected
to have a low input bias current (typically less than 75 nA), and a low drift
(depending on the temperature range).
The voltage offset of the amplifier
should be nulled (typically less than
± 200 p.V). A bias current compensation resistor in the output amplifier's
non-inverting input (when used) can
cause a variable offset. To prevent this,
the non-inverting input should be connected directly to ground with a low
resistance wire.
4. To prevent ground loop problems, connect all pins going to ground to a common pOint using separate connections.
5. The power supply used should have a
low noise level and should not have any
transients which exceed + 17V.
6. If gain adjustment is required, low
tempco (approximately 50 ppm/°C)
resistors or trim-pots should be
selected.

POWER REQUIREMENTS
Power Supply Voltage Range •...•..
Power Supply Current, max .......•.

·

PHYSICAL/ENVIRONMENTAL
Operating Temp. Range ...•.......
Storage Temp. Range ....•...••...
Package Type, Plastic •..••..••....

16-Pin DIP

·

'Same specification as listed for DAC-7533
FOOTNOTES:

1.
2.
3.
4.
5.
6.
7.
S.
9.

2-32

For input voltage = OV or + 15V.
All digital inputs tied high, OUTPUT 1 tied to ground.
All digital inputs high.
All digital inputs low.
USing internal feedback resistor.
Using internal feedback resistor. Specification for DAC-7523 only is maximum.
Accuracy not guaranteed unless outputs at ground potential.
Either output. Specified to ± 'h lSB for a full scale change. load resistance = 1001l
Reference voltage = ± 10V, 200 kHz for DAC·7523, 100 kHz for DAC·7533. and 10 kHz for DAC-7541. All
digital inputs low.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC-75231753317541
CODING AND CALIBRATION
CONNECTION·UNIPOLAR MODE

CONNECTION-BIPOLAR MODE

R1
1k

R2
1k

DIGITAL
INPUTS

o vOUT

•

NOTES: Do not use R1 and R2 if gain adjustment is not required.
CR1 (HP5082·2811 or euivalent) protects the D/A from neg·
ative transients and is necessary only with certain high
speed amplifiers.
~

IOV

NOTES: R5, R6 and R7 are used to adjust Vout = Ov at input 1000.
Do not use R1 and R4 if gain adjust is not required.
R2 and R3 should be 0.01% low-TCR resistors.

ZERO ADJUST

GAIN ADJUST

-

-

CALIBRATION

CODING TABLES

UNIPOLAR MODE

UNIPOLAR CODING TABLE

Set all digital inputs to logic low and adjust the zero adjust trim pot of the output
operational amplifier to OV.
Set all digital inputs to logic high and adjust R 1 and R2for an output equal to:
Vout = Vref (N-l)/N, where "N" equals:
256 (DAC-7523), 1024 (DAC-7533), 4096
(DAC-7541 ).

INPUT CODE
MSB
LSB
111 .... 111
110 .... 000
100 .... 000
010 .... 000
000 .. .. 000

ANALOG OUTPUT

- VREF + 1 LSB
-0.75 (V REF)
-0.5 (VREF)
-0.25 (V REF)
OV

BIPOLAR MODE
OFFSET ADJUST -

GAIN ADJUST

-

Set all digital inputs to logic high and adjust the output of A2 (with A2 offset adjust
trim pot) for OV. Set MSB "Bit 1" high and
all others low and adjust the output of AI
(with A 1 offset adjust trim pot) for OV. Adjust R7 for OV at Vout.
Set all digital input's to logic high and adjust Vout for: Vout = Vref (N-X)/X using
Rl and R4. Where "N" = 255 (DAC7523), 1023 (DAC-7533) or 4095 (DAC7541); and "X" = 128 (DAC-7523), 512
(DAC-7533) or 2048 (DAC-7541).

BIPOLAR CODING TABLE
INPUT CODE
MSB
LSB
111 .... 111
110 .... 000
100 .. .. 000
010 .... 000
000 .. .. 000

ANALOG OUTPUT

+ 1 LSB
-0.5 (V REF)

-VREF

a

+0.5 (V REF)
VREF

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-33

DAC-7S23/7S33/7S41
MECHANICAL DIMENSIONS
INCHES (mm)
16·PIN DIP
CERAMIC PACKAGE

18·PIN DIP
CERAMIC PACKAGE
925
IL - O
_ _.__
(23,49)

•

I

T

10.260

0.300

DAC·7523/33

(6,60)

(7,62)

~.~.=-=-.::r=-r-::r=-' ~
PIN 1
IDENT

*~!'
0.130
(3,30)

0.110
~

I-- 0 100 J I-- 0,018
I I (2,5) I
(0,46)

--J

I

TYPICAL CONNECTION AND APPLICATION
MODIFIE[' SCALE FACTOR AND OFFSET

DIGITALLY CONTROLLED
LIMIT DETECTOR

'>--_~I"I OUTPUT
t Vs

TEST IN (0 TO - VREFl

DIGITAL
INPUT
"D"

OUTPUT = V REF
WHERE: D =

I(

R1:2R2) - ( : , ' :

~ +

.E!I; 2 +

~2)1

=

. . B~NN

DIGITALLY CONTROLLED
GAIN

TYPICAL CONNECTION WITH
COMPENSATION CAPACITOR

VOUT
OUTPUT 1

VOUT

WHERE:
D = ~ + BIT 2 +

21

The output amplifier should be selected carefully in order to
maintain the dynamic performance of the D/A. In low speed or
static applications, AC specifications of the op-amp are not
critical. However, in high speed applications slew-rate, settling
time, open loop gain and gain/phase margin specifications
should be selected for the desired performance.
A compensation capacitor Cc should be used when a high
speed operational amplifier is used on the output.

2-34

22

BIT N

... ~

ORDERING INFORMATION
MODEL NO.

DAC-7523
DAC-7533
DAC-7541

RESOLUTION

8 Bits
10 Bits
12 Bits

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC·8308
Ultra·Fast 8·Bit
Composite Video D/A

FEATURES
• 40 MHz update rate
• Composite synchronization and
blanking
• No deglitching required
• Direct drive to 75 n load
• Adjustable setup
• O°C to + 70°C operation

REF
WHITE STROBE

BIT 1 (MSa,

GENERAL DESCRIPTION
DATEt.:s DAC-8308 is a high performance,
ultra-fast, 8-bit digital-to-analog converter.
Functionally complete, including an internal input register, equidelay current
switches and a high speed 75 n summation network; these devices are specifically designed for video and graphic
display applications.
The DAC-8308 accepts 8 bits at throughput rates up to 40 MHz and produces a
composite video output signal with 256
gray levels, including setup, blanking and
sync., all derived from separate digital inputs. The output will directly drive a terminated 75 ohm coaxial cable giving a 0 to
- 1.054V output that is in general conformance with EIA standards RS170 and
RS343A. Models with a "B" suffix have
the output voltage offset by + 392 mV so
that an input code of 0111 1111 (the middle of the gray scale) produces an output
of approximately OV. Output steps are so
,clean that deglitching is not required.
The DAC-8308 is packaged in 2 x 3 x
0.375 inch cases, allowing V2 inch board
spacing and operates over the O°C to
+70°C temperature range. Digital inputs
are TTL compatible and power requirement is ±5V. These devices are an
excellent choice for applications involving
raster scan high resolution video (both
color and monochrome), graphic display
systems, function generation and time
base correction.

STROBE
RTN

GLITCH
ADJUST

•

CI----I

BIT 2

ANA RTN

BIT 3

VIDEO OUTPUT

INPUT

BIT 4

REGISTERS

EQUIDELAY

7SI!

CURRENT

SUMM!NG
NETWORK

SWITCHES

BIT5

ANA ATN

81T 6
81T 7
BIT 8 (L$B)

Q----I
RESET

SYNC
BLANKING Lr""-r-1'"'£...->'

,----D_E_V>_EW_ _ _ _ _

U

··

----.~

CAe·8308

~I~
D 250 MIN

PIN
1
2
3
4
5

164)

-1

'-,g'J!D>UOPtNS
.17

INPUT/OUTPUT
CONNECTIONS

..

---------- 1.

•

0

024
-------------8e
•
0

TQPVIEW

02

g2S------------- 9g 1

(51)

•
•

069
p7.5)

•
•

:32--------------16: ~
r---'~"'1)___1 ~100
NOTES
1 OPEN DOTS DESIGNATE OM/TIED PINS

150,81

8
12
13
14
15
16
17
18
19
20
21
22
23
24
28
29
30

BIT 6 INPUT

31
32

BIT 7 INPUT
BIT 8 LSB INPUT

2. 0.100 INCH = 2.5mm

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

2-35

DAC-8308
FUNCTIONAL SPECIFICATIONS
Typical at + 25°C, ± 5V supplies unless otherwise noted.
OUTPUT CHARACTERISTICS
Output Voltage Range' ......... OV to -lV ± 5% into 75 n
termination.
Output Current ............... - 28 mA short circuit, -14 mA
into 75 n.
Recommended Load Impedance. 75 n ± 5%, dc to 10 MHz.
Source (Thevenin) Impedance ... 75 n ± 5%, dc to 50 MHz.
Output Bandwidth minimum. . . .. 100 MHz at - 3 dB.
LSB Size; DAC-8308 ..•••...... 2.52 mV nominal.
Rise and Fall Time, 10% to 90% .. 3 nsec. typical, 4 nsec.
maximum.
Full Step Settlin\! Time, to 1 LSB . 7.5 nsec.
Glitch Settling Time. to 1 LSB2 ... 5 nsec.
.
Glitch Area; DAC-8308 ......... 70 pV-sec. maXimum,
50 pV-sec. typical.

TRANSFER CHARACTERISTICS
Resolution ...................
Coding" .....................
Differential Linearity, maximum..
Monotonicity ...••............
Offset' .•......•.............

8 bits, 256 levels.
Binary.
± y, LSB.
Guaranteed, 10°C to 70°C.
± Y, LSB maximum, DoC to
70°C.

Transfer Gain (Slope) Tempco,
maximum .............••... +0.02%!OC.
Propagation Delay. . . . . . . . . . . .. fo nsec. typical, strobe to output,
.
50% points.
INPUT CHARACTERISTICS
Update Rate .................. 40 MHz.
Input Register" ................ 8 ECL Type 0 Flip-Flops .
Strobe Input. . . . . . . . . . . . . . . . .. Data entered on positive-going
edge (timing reference).
Setup, minimum ......•....... 7.0 nsec. before strobe.
Hold, minimum .........••.... 6.0 nsec.
Logic Levels ................. Standard 7400 TIL Levels.
Data Input Loading
(Each of 8 Inputs) ............ Two-unit load.
Strobe Input Loading ..••...... Two-unit load.
Control Input Loading, maximum 2 units each line.
POWER SUPPLY REQUIREMENTS
Supply Voltage ............... + 5V and - 5V, nominal.
Positive Supply: DAC-8308 ..... 5.0V ± 5% at 50 mA.
Negative Supply .............. -4.75V to -5.5V at 400 mAo
Supply Regulation ............. Negative supply should not have
more than 5 mV peak-to-peak
ripple.
Supply Common .............. Digital Return is the common for
the + 5V and - 5V supplies.
ENVIRONMENTAL AND PACKAGING
DoC to + 70°C.
Operating Temp. Range. . . . . . . .
Storage Temp ..•.............• -25°C to +85°C.
.
Relative Humidity ............. 0 to 100%, non-condensing.
Mechanical Dimensions .......• 2" x 3" x 0.375"
(50 x 75 x 10 mm).
FOOTNOTES:
1. The output of the DAC·8308 will be 0 to -1.054V.
2. For worst case (MSB) transition.

3. DAC·8308: 1111·1111 input code produces. - 71 mV
0000 0000 input code produces - 714 mV with standard setup
-see "Video Characteristics".

4. DAC·8308-dc output with peak white input
5. Includes built-in TIL to EeL translaters in data input lines and strobe.

2-36

VIDEO CHARACTERISTICS; DAC-8308
Typical at + 25°C, ± 5V supplies unless otherwise noted.
CompOSite Video Signal ...•.... Consists of 256 gray levels plus
Peak or 110% white, blanking
level and sync level.
Gray Scale Range ............. 0.643V peak-to-peak.
Step Size .................... 2.52 mV step.
Peak White Level •..••......... OV, absolute; +0.768V (110 IRE
Units) relative to blanking level
with standard Setup; +0.714V
relative to Reference Black,
+0.071V (10 IRE units) relative to
Reference White.
Input Code for White Level . . . . .. 11111111.
Peak White Control •........... Logic "0" (TIL) on Peak White
line overrides video input data
and drives the output to OV.
Reference Black Level ......... -0.714Vabsolute; +54 mV (7.5
IRE Units) relative to blanking
level with standard Setup.
Input Code for Reference
Black Level. . . . . . . . . . . . . . . . . 00000000.
Composite Blanking Level ...... -0.768V absolute, with standard
Setup.
Input Command for Blanking!
Pedestal Level ......•.••.... Logic "0" (TIL) on "Blanking"
line simultaneously resets input
register to 00000000.
-1.054V absolute with standard
CompOSite Sync Level
Setup; - 0.286V ( - 40 IRE Units)
with respect to blanking level
(back porch).
Input Command for Sync Level .. Logic "0" (TIL) on "Sync" line
simultaneously resets input
register to 00000000.
Sync and Blanking Rise and Fall
Times, maximum .••......... 100 nanoseconds.
Sync and Blanking Overshoot,
maximum ...•.........•.... 2%.
Setup (Reference
Black-to-Blanking) . . . . • • . . . .. Externally programmable from 0
mV (0 IRE Units) to 142 mV (20
IRE Units).
Setup Control Line ............ Input ground: Standard 54 mV
(7.5 IRE Units)
Input Open: 71 mV (lOIRE Units)
Setup. Input tied to - 5V: 142 mV
(20 IRE Units). Input tied 10 + 5V:
o mV (0 IRE Units).

TECHNICAL NOTES
1. The DAC-8308 has three additional current switches in the
equi-delay bank: One to inject the Blanking level and one for
the Synchronizing level, as required to generate a composite
video signal. The Setup Control provides a means for varying
brightness in reproducible steps. TV monitors cut off the picture tube in response to the Blanking level, producing the
blackest possible visible picture. The Setup control varies the
offset between Reference Black level and Blanking level
which produces an apparent shift in the "brightness" of Reference Black.
The Blanking and Sync. control lines are asynchronous. The
DAC output goes to the command level in about 12 nanoseconds. 12 nanoseconds after removal, the DAC output goes to
Reference Black until the next strobe command.
The DAC-8308 has additional user flexibility, achieved by the
addition of a Peak White control. Assertion of this input
drives the output to its most positive voltage: The whiter than
white level, or 110% white to be used for cursors etc.
Peak White sets the input register which turns off the eight
gray scale current switches, and the third additional cU.rrent
switch. The Sync or Blanking inputs reset the input register,
producing full scale output from the gray scale current

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

DAC-8308
switches; the output from the Sync. or Blanking current
switches is added to the full scale .output. Obviously, Peak
White should not be activated during the Sync. or Blanking
intervals.

a small capacitor across the DAC output. This will result in
slower rise times. The absolute glitch amplitude will
decrease, but the energy (or net area) of the glitch will be
unchanged.

2. The DAC-8308 is capable of operation from a negative
supply voltage between -4.75V to -5.5V. The output amplitudes specified are nominal values set by internal reference.
However, if user adjustment is required, the glitch area will
vary slightly as a function of the negative supply voltage.
The factory trim is carried out at -5.0V, connect a 10K
potentiometer to the Glitch Adjust Terminal. Adjust this pot
for minimum glitch area at the major carry transition. This
pot may be omitted and the Glitch Adjust Terminal left open.
3. EIA Industrial Electronics Tentative Standard No.1 which
will, in the future, become a part of RS170-A, details the exact waveform and timing characteristics of the composite
video signal at the output of a color television studio.
The products described in this data sheet are in general conformance with such needs. Exact compliance requires additional circuitry which would, at a minimum, provide Sin XIX
correction and bandwidth filtering.
4. The output bandwidth may be reduced, if desired, by adding

5. The DIG RTN, ANA RTN and STROBE RTN terminals are all
tied together internally. The + 5V and - 5V supply common
should be connected to DIG RTN. If a long printed circuit wiring connection is required for integration of the DAC into a
video system, stripline wiring techniques may be implemented by taking advantage of the physical arrangement
of the output terminals i.e., the ANA RTN terminals are
located on each side of the VIDEO OUT terminal. ANA RTN
normally connects to the shield of an external 75 ohm coaxial cable. STROBE RTN is included as a convenience and
may be used optionally to facilitate connection.
6. The sync and blanking outputs of the MM5320 TV Timing
ROM may not be capable of driving the DAC-8308 series,
under worst case conditions, without the use of a logic driver.
7. All timing is referenced to the positive edge of the strobe.
Setup and Hold require 7.0 nanoseconds and 6.0
nanoseconds, respectively.

COMPOSITE VIDEO OUTPUT (NOT TO SCALE)
-

----- ----- --- ------- ------

---t

-

-

PEAKWHITE,110%~OmV(+110IRE)

-

-

-

REFERENCE
WHITE LEVEL: -71mV (+100 IRE)

-

-

-

REFERENCE
BLACK LEVEL: -714mV(+7.5IRE)

GRAY
SCALE
RANGE'

_

I - - - -- ------

SET~~P~~_~~_/ f

0.2B6V

L,

_ _ _

_

~~~~

_

_

_

_

_

_ _ _

_ _

BLANKING
LEVEL: - 768mV (0 IRE)'

,

_1 ____ 1_
I

_____ 2.. ______ _

I
I
I_SYNC. PORTION_I"" VIDEO PORTION ....I

I

SYNC.
LEVEL: -1.054V (-40 IRE)'

I

1. ForS1andard -7.5 IRE Setup. For -10 IRE Setup = -785mV, -201RE
2. For Standard - 7.51RE Setup with Blanking present during Sync time.
For -10 IRE Setup = 1.07tV, - 20 IRE = -1.143V.
o IRE Setup or with Blanking not present during Sync = -1.000V
3. Gray Scale: LSB = 2.52 mV = 0.363 IRE
MSB
321 mV
46.43 IRE

=

= -857mV.

=

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-37

• .'.

CAe-8308

PEAK
WHITE
CONTROL

MONITOR
(7511INPUT)

MEMORY ARRAY
FOR VIDEO DATA

CONTROL
AND
ADDRESS
LOGIC

SETUP

PEAK WHITE

7.51RE UNITS
010 IRE UNITS

1

20 IRE UNITS

COMPOSITE
BLANKING

MM 5321

DUAL-PHASE
CLOCK DRIVERS
2.04 MHz
OR
1.26 MHz

-5V

COMPOSITE
SYNC.

TTL BUFFERS

TYPICAL SMALL DISPLAY SYSTEM
With this circuit, digital video data, digital sync. and digital blanking are converted directly to a composite monitor input. Analog mixing
and/or generation of the sync/blanking is not required, nor is a separate high power driver amplifier required ahead of the monitor. With the
inherently low glitch of the DAC-8308, a deglitcher is not required and video data need not be "aligned" to achieve low glitch performance.

GLOSSARY OF VIDEO TERMS
COMPOSITE VIDEO SIGNAL
The combined video signal, with or without Setup, plus the Sync
signal.
VIDEO SIGNAL
The visually perceived portion of the composite video signal
which varies in gray scale levels from Reference White to
Reference Slack. Also known as the picture signal.
SYNC OR COMPOSITE SYNC SIGNAL
That portion of the composite video signal which synchronizes
the scanning process.
SYNC LEVEL
The level of the peak of the Sync signal.
SETUP
The difference in level between the Reference Slack level and
the Sianking level. Not to be confused with setup as used in conjunction with digital logic.

REFERENCE WHITE LEVEL
The maximum positive polarity amplitude of the video signal.
PEAK WHITE LEVEL
A "Whiter than White" Level not within the range of the normal
picture. Sometimes used for generating cursors or outlines
because it contrasts with all gray shades including white.
GRAY SCALE
The discrete levels for the video signal between Reference
White and Reference Slack levels.
COLOR VIDEO (RGB)
As used herein, this refers to the method of generating color images by combining the three primary colors of red-green-blue
(RGS). The associated monitor would be identified as an
"RGS" monitor. Three DAC-8308 series D/A converters are required to drive such a monitor, one each for red, green and blue.

RASTER-SCAN
The basic method of sweeping across a CRT, a line at a time, to
generate and display pictures such as used in commercial TV in
the USA.
MONOCHROME VIDEO
Conventional black-and-white television video in which the
Z-axis, or intensity, of the beam is modified during scanning to
shade and/or outline images.
BLANKING LEVEL
The level which separates the Sync portion from the video
signal, with or without Setup. This level is sometimes also called
the pedestal, back porch or front porch. It usually refers to the
level which will cut off the TV tube, producing the blackest possible visual picture.
REFERENCE BLACK LEVEL
The maximum negative polarity amplitude of the video signal.

2-38

ORDERING INFORMATION
MODEL NO.

OUTPUT

DAC-8308

Unipolar

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DAC-HF Series
Ultra-Fast D/A Converters

FEATURES
• 8-, 10-, 12-Bit resolution
• Settling times to 25 nanoseconds
• 20 ppm/oC tempco
• Unipolar or bipolar operation
• Current output
• Internal feedback resistor

+15V

-15V

GROUNDS

~

@

@@@@
~ REF_l~lOV

l

GENERAL DESCRIPTION
The DAC-HF Series of hybrid DAC's are
ultra high-speed, current output devices.
They incorporate state-of-the-art performance in a miniature package, achieving
maximum output settling times of 25
nanoseconds for the 8- and 10-bit models
and 50 nanoseconds for the 12-bit model.
They can be used to drive a resistor load
directly for up to ± 1V output or a fast
operational amplifier (such as DATEL's
AM-SOO) for higher voltage outputs with
sub-microsecond settling times. A tapped
feedback resistor and a bipolar offset
resistor are included internally to give five
programmable output voltage ranges with
an external operational amplifier.

Applications for the DAC-HF series include
high-speed function generators, fast computer control systems, graphic display
systems, and CRT displays.

l

~

2K

I I I I I I I

1

~ (5) (5)

2

3

4

5

6

W

~ 0.800 MAX---l

8

9

10

11

r

lr~
0.010

I

12

f

PIN FUNCTION

KOVAR

13,

,,

,

BOTTOM

VIEW

,
,
,
,
,
,
,
,

24 ,

1

'200

11 SPACES
AT 0.100
EA (2.5)

1.1""
(33.3)

--0
1-0600--1 1-0.100
(15,2)

IN PUT/OUTPUT
CONNECTIONS

0.190 MAX (4,8)

x 0.D18

,,2

PIN 1

REF.IN

LSB

I

(20.3)

~I

,
,
,
,
,
,
,
,
,
~~;E~~~g:S - "

~

(5) ~)

7

MECHANICAL DIMENSIONS
INCHES (MM)

~

20V RANGE
lOV RANGE

FOR DAC-HF10B PINS 11 & 12 ARE NO CONNECTION
FOR DAC-HFBB PINS 9, 10, 11 & 12 ARE NO CONNECTION

NOTE:

0.150 MIN
(3.B)

~

~~ OUTPUT

CONTROL
CIRCUIT

DIGITAliNPU1S

MSB

•

BIPOLAR
OFFSET

I I I

I I i2JI I I I l2!I I (!oJI Q1)I C'3l

l') @

2K

~~

1

FAST PNP CURAENT SWITCHES

BIT

2°'0)

OUT

4K

THIN FILM R-2R
LADDER NETWORK

The DAC-HF design combines· proven
hybrid production techniques with advanced circuit design to realize high speed
current switching. The design incorporates
fast PNP current switches driving a low impedance R-2R thin-film ladder network.
The. nichrome thin-film resistor network is
deposited by electron beam evaporation
on a low capacitance substrate to assure
high-speed performance. The resistors are
then functionally trimmed by laser for optimum linearity.
The digital inputs are TTL-compatible and
use straight binary coding for unipolar
operation and offset binary coding for
bipolar operation. Output current is 0 to
+ 5 mA for unipolar operation and ± 2.5
mA for bipolar operation into an output
amplifier summing junction. Linearity is
± 1 LSB, and the converters are
monotonic over the operating temperature
range
specified
for
each.
Gain
temperature coefficient is ± 20 ppm/oC
maximum.

REFERENCE
'ov

(2.5)

PIN

FUNCTION

1

BIT 1 IN (MSB)

13

GROUND

2

BIT 2 IN

14

GROUND

3

BIT 3 IN

15

GROUND

4

BIT 4 IN

16

REF. IN

5

BIT SIN

17

20 V RANGE

6

BIT 6 IN

18

OUTPUT

7

BIT 7 IN

19

10V RANGE

8

BIT 8 IN

20

BIPOLAR OFFSET

9

BIT 91N

21

REF. OUT

10

BIT 10 IN

22

15 VDC

11

BIT 11 IN

23

GROUND

12

BIT 12 IN (LSB)

24

+15 VDC

NOTE: PINS HAVE 0.025 INCH STANDOFF FROM CASE, fO.Ot"

Power supply requirements is ± 15V dc
with less than 780 milliwalts consumption.
The DAC-HF is available in models covering three operating temperature ranges.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-39

DAC-HF Series
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS, ALL MODELS
Positive Supply, Pin 24 .......... + 18V
Negative Supply, Pin 22 . . . . . • • . .. - 18V
Digital Input Voltage, Pins 1 to 12 .. + 15V

FUNCTIONAL SPECIFICATIONS
Typical at 25'C, ± 15V supplies unless otherwise specified.
DESCRIPTION

I

8B

I

lOB

I

12B

INPUTS
Resolution, Bits ................
Coding, Unipolar Output .........
Coding, Bipolar Output .••..••...
InputLogicLevel,BitON("1") ....
Input Logic Level, Bit OFF ("0") ...

10
12
8
Straight Binary
Offset Binary
+2.0 to +5.5V at +40~
OV to + 0.8V at 2.6 rnA

OUTPUTS
Output Current Range, Unipolar ...
Output Current Range, Bipolar .. ..
Output Voltage Compliance ..••..
Output Voltage Ranges2 •••••••••

0 to + 5 rnA
± 2.5 rnA
± 1.2V
0 to - 5V
o to -10V
±2.5V
±5V
±10V
Output Resistance .............. 400 ohms
Output CapaCitance . . . . . . . . . . . .. 15 pF
Output Leakage Current, All Bits
OFF .....................••. 15 nA
PERFORMANCE
Linearity Error, max .................. 0.012%
TMINtoTuAX ..................... '" .0.024%
Differential Linearity Error, Max ...... 0.012%
TMINtoTuAX ......................... 0.024%
Monotonlclty ..................... Guaranteed over oper. temp. range
Gain Tempco, max .............. ± 20 ppm/oC
Offset Tempco, Bipolar, max ...... ± 10 ppm/oC of F.S.R.3
Zero Tempco, max •...•••....... ± 1.5 ppm/oC of F.S.R.3
25
25
50
Settling Time, nsec. max.' .......
Power Supply Sensitivity ......... 0.01 %1% Supply
POWER REQUIREMENTS
Supply Voltage ...•...•••....... ±15Vdc ±0.5V
Positive Quiescent Current, max •.. 35mA
40mA
Negative Quiescent Current, max.
15mA
15mA

45mA
15mA

PHYSICAUENVIRONMENTAL
Operating Temperature Range ....
Storage Temperature Range .••...
Package Type ..•...............
Pins ..•...•..................•
Weight .......................•

O°C to + lO°C (BMC)
-55°C to +125°C(BMM)
-65°C to + 150'C
24-Pin Ceramic DIP
0.010 x 0.018 inch Kovar
0.2 oz (6g.)

1. Proper operation of the DAC-HF series converters is dependent on good board layout and connection practices. Bypass
supplies as shown in the connection diagrams. Mount bypass
capacitors close to the converter, directly to the supply pins
where possible.
2. Use of a ground plane is particularly important in high speed
D to A converters as it reduces high frequency noise and aids
in decoupling the digital inputs from the analog output. Avoid
ground loop problems by connecting all grounds on the board
to the ground plane. The remainder of the ground plane
should include as much of the circuit board as possible.
3. When the converter is configured for voltage output with an
extemal operational amplifier, keep the leads from the converter to the ouptut amplifier as short as possible.
4. The high speed current switching technique used in the DACHF series inherently reduces the amplitude and duration of
large transient spikes at the output ("glitches"). The most
severe glitches occur at half-scale, the major carry transition
from 011 ... 1 to 100 ... 0 or vice versa. At this time, a skewing
of the input codes can create a transition state code of 111 ...
1. The duration of the "transition state code" is dependent
on the degree of skewing but its effect is dependent on the
speed of the DAC (an ultra-fast DAC will respond to these
brief spurious inputs to a greater degree than a slow DAC).
Minimize the effects of input skewing by using a high-speed
input register to match input switching times. The input
register recommended for use with the DAC-HF is easily implemented with two Texas Instruments SN74S174 hex Dtype flip-flops. This register will reduce glitches to a very low
level and ensure fast output settling times.
5. Test the DAC-HF using a low capacitance test probe (such as
a 10X probe). Take care to assure the shortest possible connection between probe ground and circuit ground. Long probe ground leads may pick up environmental E.M.1. causing
artifacts on the scope display, i.e., signals that do not
originate at the unit under test.
6. Passive components used with the DAC-HF may be as indicated here: 0.1 I'F and 1 I'F bypass capacitors should be
ceramic type and tantalum type respectively; the 4000 output load is a 0.1 % 10 ppm/oC metal film type; adjustment
potentiometers are ceremet types: other resistors may be
± 10% carbon composition types.
7. Output voltage compliance is ± 1.2V to preserve' the linearity
of the converter. In the bipolar mode, the DAC-HF can be
operated with no load to give an output voltage of ± 1.0V. In
the unipolar mode, the load resistance must be less than
6000 to give less than + 1.2V output. The specified output
currents of 0 to + 5 mA and ± 2.5 mA are measured into a
short circuit or an operational amplifier summing junction.

FOOTNOTES:
1. Full scale current change to 1 LSB with 4000 load.
2. With External Operational Amplifier.
3. F.S.R. is Full Scale Range, or the difference between minimum and
maximum output values.

2-40

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

DAC-HF Series
CONNECTION AND CALIBRATION
UNIPOLAR CURRENT OUTPUT CONNECTIONS

f'

BIPOLAR CURRENT OUTPUT CONNECTIONS

ZERO
ADJUST

25KII

,9
,7

BIT,

,8

lOUT

20

,9
,7
,8

BIT,

-'5V

40011 LOAD
IFOR a TO

+'v FS.I

40011 LOAD
(FOR cO.5V FS.I

.1

DAC-HF

2'

2'
GAIN
ADJUST

16

'5
'4
'3

81T '2

OFFSET
ADJUST

20

DAe-HF

,2

OUTPUT

OUTPUT

,2
81T '2

UNIPOLAR CURRENT OUTPUT
CALIBRATION PROCEDURE

GAIN
ADJUST

'6
,5
,4

,3

BIPOLAR CURRENT OUTPUT
CALIBRATION PROCEDURE

1. Connect the converter as shown in the connection diagram.

1. Connect the converter as shown in the connection diagram.

2. Set all inputs low and adjust the ZERO ADJUST potentiometer for a reading of OV at the output.

2. Set all inputs low and adjust the OFFSET ADJUST potentiometer for an output reading of + F.S., (given in the coding
table for 12-bit units).

3. Set all inputs high and adjust the GAIN ADJUST potentiometer for a reading of - F.S. + 1 LSB (given in the coding
table for 12-bit units).

3. Set all inputs high and adjust the GAIN ADJUST potentiometer for an output reading of - F.S. + 1 LSB, (given in
the coding table for 12-bit units).

CODING TABLES
UNIPOLAR OUTPUT
UNIPOLAR
INPUT CODING
SCALE
STRAIGHT BINARY
-F.S. +1 LSB
1111 1111 1111
- J.4 F.S.
1100 0000 0000
-1/2 F.S.
1000 0000 0000
-% F.S.
0100 0000 0000
-1 LSB
000000000001
0
0000 0000 0000

ANALOG OUTPUT
Oto+1VF.S o to -5V F.S Oto-l0VF.S
+0.9998V -4.9988V -9.9976V
-7.5000V
+0.7500V -3.7500V
-5.0000V
+0.5000V -2.5000V
-2.5000V
+0.2500V -1.2500V
-0.0024V
+0.0002V -0.0012V
O.OOOOV
+O.OOOOV +O.OOOOV

PROGRAMMABLE OUTPUT
RANGE PIN CONNECTIONS
OUTPUT
VOLTAGE
RANGE

o to

-5V

BIPOLAR
SCALE
-F.S. +lLSB
_1/2 F.S.
-1 LSB
0
+'/2 F.S.
+F.S. -lLSB
+F.S.

INPUT CODING
OFFSET BINARY
1111 1111 1111
1100 0000 0000
1000 0000 0001
1000 0000 0000
0100 0000 0000
0000 0000 0001
0000 0000 0000

ANALOG OUTPUT
±O.5V F.S. ±2.5V F.S. ±5V F.S. ±10V F.S ..
+0.4998V
+0.1250V
+0.0002V
O.OOOOV
-0.1250V
-0.4998V
-0.5000V

-2.4988V
-1.2500V
-0.0012V
O.OOOOV
+ 1.2500V
+2.4988V
+2.5000V

CONNECT
THESE PINS
TOGETHER

PIN 19

PIN 17to PIN 18
PIN 20 to PIN 23

PIN 19

PIN 20 to PIN 23

PIN 19

PIN 17to PIN 18
PIN 20 to PIN 18

+5V

PIN 19

PIN 20 to PIN 18

±lOV

PIN 17

PIN 20 to PIN 18

°

to -10V
±2.5V

BIPOLAR OUTPUT

FEEDBACK
CONNECTION

In all programmable output ranges
pin 18 connects to external
operational amplifier inverting input

-4.9976V -9.9951V
-2.5000V -5.0000V
-0.0024V -0.0049V
O.OOOOV
O.OOOOV
+2.500V +5.0000V
+4.9976V +9.9951V
+5.0000V + 10.0000V

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-41

DAC-HF Series
APPLICATIONS
UNIPOLAR FAST VOLTAGE OUTPUT CIRCUIT

UNIPOLAR ULTRA-FAST VOLTAGE OUTPUT

"

alT 1

'FEEDBACK, seE PROGRAMMABLE OUTPUT
RANGE PIN CONNECTION TABLE
24

"FEEDBACK. seE PROGRAMMABLE OUTPUT
RANGE PIN CONNECTION TABLE

19
17

18~-------"1

lat------'1

20

GAIN

16
15

--+-A,Jvv---i ~::
750K

ADJUST

-

BIT 12

23

22

ADJUST

R

_

12

-,sv

ZEROn

n

15V
RFEEDBACK ~ 400

R~---~

RFEEDEIACK

t

400

12

BIT 12

13

23

VOLTAGE OUTPUT WAVEFORMS
EQUIVALENT OUTPUT CIRCUIT
4KtQ.l%

, - - - f l V \ f \ r - - - - - - o 2 0 ~I~~~R
t------------<>21

2V/DIV

~~E(~i~~;2%)

,------<>19 ~1~~ ~~~g~CK

lav

17 &~~~~~g~CK

+

t---~-------_-....,.,~_----I:" lOV RANGE

SUM.
JUNCTION

+5V

.>---->:15

1

2

3

4

6

(MSB)

The DAC-HK Series contains a precision
zener reference circuit. This eliminates
code-dependent ground currents by routing current from the positive supply to the
internal ground node as determined by the
R-2R ladder network. The internal feedback resistors for the on-board amplifier
track the ladder network resistors, enhancing temperature performance. The excellent tracking of the resistors results in a differential nonlinearity tempco of 2 ppm/oC
maximum. The temperature coefficient of
gain is 20 ppm/oC maximum and tempco
of zero is ±3 ppm/oC maximum.
The converters are cased in 24-pin
ceramic packages. Models are available
for operating temperature ranges of 0 to
+70, and -55 to +125°C. Power requirement is ±15V dc and +5V dc. Total power
dissipation is 700 mil Iiwatts.

+Vs

... @L __

GENERAL DESCRIPTION

7

a

BIT

9

1011

OUTPUT

12

(LSB)

MECHANICAL DIMENSIONS
INCHES (mm)
0.800MAX
(20.3)

0.190 MAX

INPUT/OUTPUT

~

==c

~0.010 X 0.018
KOVAR Pins

CONNECTIONS
0.150MIN
(3.8)

PIN
13

,12
I
I
I
I
I
I
I
I

,

BOTTOM
VIEW

I
I
I
I

,

,
I

,
I
I
I
I
I
I
I
I

,
,

11
SPACES
AT 0.100
(2.5)

!

~

I
I
I
I
I
I
I
I

I
I

!

1

L
I"

24

T)
1.310 MAX.
(33,3)

1
2
3
4
5
6
7
~

9
10
11
12

FUNCTION
BIT 1 IN IMSB~
BIT 21N
BIT31N
BIT 41N
BIT 51N
l.):!I 61N
BIT 71N
I tll ~ IN
BIT91N
BIT lOIN
BIT lllN
BIT 12 IN (L:::.tli

PIN
13
14
15
16
17
18
19
20
21
22
23
24

FUNCTION
+5VDC
15 VD
OUTPUT
LOAD
BIP LAR OFF
10V RANGE
20 V RAN E
3MI\I1~J"I,"-""'GROUND
+ 15 VDC
GAIN ADJ
REF. OUT

0.600
(15,2)

NOTE: Pins have a 0.025 inch, ±O.01
stand~off from case.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-43

DAC-HK SERIES
ABSOLUTE MAXIMUM RATINGS
Positive Supply, pin 22 ..... .
Negative Supply, pin 14 ..•••
Logic Supply, pin 13 ••.•....
Digital Input Voltage, pins
1-12 & 16 ....•....•.....
Output Current, pin 15 •.....

PHYSICAL/ENVIRONMENTAL

DAC-HK12B
+18V
-18V
+S.25V

Operating Temperature Range .

+S.SV
±20 mA

Storage Temperature Range .
Package Type .........••..
Pins ...•...•••...........
Weight ...................

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ± 15V and +5V supplies unless otherwise

O°C to + 70°C (BGC, BMC)
-SSOCto +12S0C(BMM)
-65°C to + 125°C
24-pin Ceramic DIP
0.010 x 0.018 inch Kovar
0.2 ounces (6 grams)

FOOTNOTES:

noted.

INPUTS

1. For two's complement coding order the model described under ordering
information.
2. Logic levels are the same as for data inputs.
3. By external pin connection.

4. For ± 12V dc, + 5V de operation, contact factory.

Resolution ..••.•.••.......
Coding, unipolar output •....
Coding, bipolar output ......
Input Logic Level, bit ON
("1 ") ..................
Input Logic Level, bit OFF
("0") •............••...
Logic Loading .......•.....
Load Input' ...........•...
Load Input Loading .........

12 bits
Straight Binary
Offset Binary
Two's Complement'
+2.0V to +S.SV
OV to +0.8V
1 LSTTL load
High (" 1 ") = hold data
Low ("0") = transfer data
3 LSTTL loads

OUTPUT
Output Vqltage Ranges3 ,
unipolar •...••........••
Output Voltage Ranges3 ,
bipolar ....•.....•.....•
Output Current ............
Output Impedance . . . . . . . .

.

Oto +10V
±2.SV
±SV
±10V
±S mA min.
O.OS ohm

PERFORMANCE
Linearity Error, max ......•..
Differential Linearity Error,
max ...........•........
Gain Error, before trimming .•
Zero Error, before trimming ..
Gain Tempco, max .....•....
Zero Tempeo, unipolar,
max ..............•.....
Offset Tempco, bipolar,
max ....................
Diff. Linearity Error Tempco,
max ....•...•.......•...
Monotonicity .••...•.......
Settling Time, SV change ....
Settling Time, 10V change ...
Settling Time, 20V change ...
Settling Time, 1 LSB change .
Slew Rate ......•..........
Power Supply Rejection .•...

± '/2 LSB
±3I4LSB
±0.1%
±O.OS%
±20 ppm/oC
± S ppm/oC of FSR
± 10 ppm/oC of FSR
± 2 ppm/oC of FSR
Guaranteed over oper. temp. range
3!,sec.
3!,sec.
4l'see.
800 nsec.
20V/!'sec.
± 0.002% FSR/%

POWER REQUIREMENTS
Power Supply Voltage

2-44

......

+ 1SV dc ±O.SV dc at 10 mA
-1SV de ±0.5V de at 25 mA
+5V dc ±0.25V dc at 35 mA
± 12V dc, + 5V operation4

TECHNICAL NOTES
1. It is recommended that these converters be operated with
local supply bypass capacitors of 1 flF (tantalum type) at the
+ 15, -15, and + 5V supply pins. The capacitors should be
connected as close to the pins as possible. In high RFI noise
environments these capacitors should be shunted with 0.01
flF ceramic capacitors.
2. The analog, digital, and power grounds should be separated
from each other as close as possible to pin 21 where they all
must come together.
3. The "load" control pin is a level triggered input which causes
the register to hold data with a high input and transfer data to
the DAC with a low input.
4. A setup time of 50 nanoseconds minimum must be allowed
for the input data. The DAC output voltage begins to change
when the register output changes.
5. The external gain adjustment shown in the Connection
Diagrams has a range of ± 0.2% of full scale. If a wider range
is desired the2.8 Megohm resistor can be decreased slightly
in value. The full-scale output is typically accurate within
± 0.1 % with no adjustment. The zero, or offset, adjustment
has a range of ± 0.35% of FS.
6. If the reference output terminal (pin 24) is used, an operational amplifier in non-inverting mode should be used as a
buffer. Current drawn from pin 24 should be limited to ± 10
flA in order not to affect the T.C. of the reference.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC-HK SERIES
TIMING DIAGRAM
Hold
LOAD

~~~"-'-----~
1
1

DATA IN

V!1
1

I-

'

!

.J!1

_0 _ _

'LJ

1
I

\

1

1
1

tsetup
1
50 nsec.min.---I

~

REGISTER
OUTPUT TO DAC

I~

1

I

1

I

1

I

1

I

1

I
1

I--

I

1

1

1

1
1

tsetup
I
50 nsec.min.-j
I

1

-+,--J,
I

____________________

•

-I t I-

-.J t I-pHL

pLH

60 nsec.

60 nsec.

All rise and fall times <;;10 nsec.

CONNECTION DIAGRAMS
UNIPOLAR OPERATION

(0 to +10V)
LOAD

BIT

LSB

F

12

"

10'

10

"

f--o-+---"?------

13

I.

+5VOC

f--o-+---+----<~_.._-- "15VDC

f--o-+--t-+----;I-:-:-+---O OUT

15

(-5 TO +5V)

16

I.
17

DATA

IN

19
20
21
22

1--o-+--+-,'V\N'vl---< b~,~

23
MSB

ADJ

24

+15VOC

OUTPUT RANGE SELECTION

OUTPUT CIRCUIT
r-----------~

FULL SCALE 'out
= 2 mA (BINARY)

5K

'-~~~~~~~~AJv--Q19

'------0

lout

20

20VRANGE

18 10V RANGE

>------0 15

t

SUM. JUNCTION

5K

OUTPUT

6.3K
_-~""'''',~--o

17 BIPOLAR OFF.

t---------o

24 REF. OUT

t--------o

21

RANGE
±10V
±5V
±2.5V
+10V
+5V

CONNECT THESE PINS TOGETHER

15 &
15 &
15 &
15&
15 &

19
18
18
18
18

17 &
17 &
17 &
17 &
17 &

20
20
20
21
21

19 & 20
19& 20

6.3V
REF ..
GROUND

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

2-45

DAC-HK SERIES
CODING TABLES
BIPOLAR OPERATION

UNIPOLAR OPERATION
STRAIGHT BINARY
MSB

LSB

111111111111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0001
0000 0000 0000

OFFSET BINARY

OUTPUT RANGES

Oto+1DV

o to +5V

+9.9976

+4.9988
+3.7500
+2.5000
+1.2500
+0.0012
0.0000

+ 7.5000
+5.0000
+2.5000
+0.0024
0.0000

MSB

LSB

TWO's COMPLEMENT
MSB

111111111111
1100 0000 0000
1000 0000 0000
0100 0000 0000
0000 0000 0001
0000 0000 0000

LSB

0111
0100
0000
1100
1000
1000

1111
0000
0000
0000
0000
0000

1111
0000
0000
0000
0001
0000

OUTPUT RANGES

±10V
+9.9951
+5.0000
0.0000
-5.0000
-9.9951
-10.0000

±5V
+4.9976
+2.5000
0.0000
-2.5000
-4.9976
5.0000

±2.5V
+2.4988

+ 1.2500
0.0000
-1.2500
- 2.4988
- 2.5000

APPLICATIONS
INTERFACING TO 2! 12 BIT DATA BUS

INTERFACING TO 8 BIT DATA BUS

----l-T

r

-l-------.-J

__ - '

I

r

J

ADDRESS

I

STROBE

WAITE
STROBE

CALIBRATION PROCEDURE
Select the desired output voltage range and connect the
converter up as shown in the Output Range Selection Table and
the Connection Diagrams. Refer to the Coding Tables.
UNIPOLAR OPERATION
1. Zero Adjustment. Set the input digital code to 0000 0000
0000 and adjust the ZERO ADJ. potentiometer to give
O.OOOOV output.
2. Gain Adjustment. Set the input digital code to 1111 1111
1111 (straight binary) and adjust the GAIN ADJ.
potentiometer to give the full-scale output voltage shown in
the Coding Table.
BIPOLAR OPERATION
1. Offset Adjustment. Set the digital input code to 0000 0000
0000 (offset binary) or 1000 0000 0000 (two's complement)
and adjust the OFFSET ADJ. potentiometer to give the
negative full-scale output voltage shown in the Coding Table.
2. Gain Adjustment. Set the digital input code to 1111 1111
1111 (offset binary) or a 0111 1111 1111 (two's complement)
and adjust the GAIN ADJ. potentiometer to give the positive
full-scale output voltage shown in the Coding Table.

2-46

ORDERING INFORMATION
OPERATING
TEMP. RANGE

SEAL

O°C to + 70°C
O°C to + 70°C
-55°C to + 125°C

Epoxy
Herm.
Herm.

MODEL NO.
Binary Coding
DAC-HK12BGC
DAC-HK12BMC
DAC-HK12BMM

2's Complement Coding
DAC-HK12BGC-2
DAC-HK 12BMC-2
DAC-HK12BMM-2
ACCESSORIES
Part Number
DILS-3
TP100K

O°C to + 70°C
O°C to + 70°C
-55°C to +125°C

Epoxy
Herm.
Herm.

Description
24-pin Mating Socket
Trimming Potentiometer

For military devices compliant to MIL-STD-883, contact DATEL.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 0204S-11941TEL (50S) 339-30001TLX 17438S/FAX (50S) 339-6356

DAC-HPi6B
i6-Bit, Micro-electronic
Digital-to-Analog Converter
FEATURES
•
•
•
•

16-Bit binary model
Voltage outputs
15 ppmf"C Maximum gain tempco
Linearity to ± 0.003%

BIPOLAR

OFFSET

+ 15V

GND

-15V

@

@

@l

@

GENERAL DESCRIPTION
The DAC·HP series are high resolution
hybrid DfA converters with voltage output.
They are self-contained, including a low
tempco zener reference circuit and output
operational amplifier, all in a miniature
24-pin double spaced ceramic DIP package. The DAC-HP16B has 16-bit binary resolution with ± 0.003% linearity. Input
coding is complementary binary and complementary offset binary for the DACHP16B. This device operates in both unipolar and bipolar modes with output voltages of 0 to + 10V dc and ± 5V dc respectively. Binary versions with a bipolar output
voltage range of ± 10V dc are available,
denoted by the suffix" - 1" after the model
designation.
The DAC-HP design incorporates. both
thin- and thick-film hybrid technology. The
design includes an on-board amplifier and
precision zener reference circuit. This
eliminates code-dependent ground currents by routing current from the positive
supply to the internal ground node as
determined by the R-2R ladder network.
The internal feedback resistors for the onboard amplifier track the ladder network
resistors, enhancing temperature performance. The excellent tracking of the
resistors results in a differential nonlinearity tempco of 2 ppmfoC maximum. The
temperature coefficient of gain is 15
ppmfoC maximum and tempco of zero is
± 5 ppmfoC maximum.
The resolution, stability and voltage output of these converters make them ideal
for precision applications such as speech
and waveform reconstruction, precision
ramp generators, and computer controlled
testing. They are available in operating
temperature ranges 0 to +70 oC and -55°
to +125°C. Power requirement is ±15V
dc.

•

I

6.2K

~~~@

l~

~
REF.

5K
~-'VV'v

T-~ @OUTPUT

~:K
VVv

J

------

A~JA0~T@

~ffi-1
CONT~Ol

®

SUMMING
JUNCTION

16-81T

CKT

AID CONVERTER

III J I I I II I I I I I

800000000@@@@@@@
BIT

1 2 3

4 5

6

MSB

7 B 9 10 11 12 13 14 15 16
DIGITAL INPUTS

INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (MM)

r--

~I
o 150MIN
13,81

0 800 MAX----1

~

j

120,31

r

T

10.190 MAX (4.8)

t

0010)(0018
KOVAR

13,

012

,
,
,

,
,
,
,
,
,
,

DOT ON TOP

REFERENCES
PIN'

"

BOTTOM
VIEW

,
,
,
,
,
,
,
,
,
,

-1

'200

11 SPACES

AT0100
EA 12,5)

_1 ","""
33.3

24,

r- ~1~--1

LSB

01~

PIN

FUNCTION

PIN

FUNCTION

1
2
3
4
5
6
7
8
9
10
11
12

BIT
BIT
BIT
BIT
BIT
BIT

13
14
15
16
17
18
19
20
21
22
23
24

BIT 13 IN
BIT 141N
BIT 151N
BIT 16 IN (LSB)
OUTPUT
BIPOLAR OFF
15VOC
GROUND
SUM JUNCTION
GAIN ADJ
+15VDC
REF OUT

1 IN (MSB)
21N
31N
41N
51N
61N

BIT 7 IN

BIT
BIT
BIT
BIT
BIT

SIN
91N
10 IN
11 IN
121N

--0

f---

0 100
12,5)

NOTE: PINS HAVE 0.025 INCH STANDOFF FROM CASE, ±O.Ol"

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-47

DAC-HP168
ABSOLUTE MAXIMUM RATINGS
Positive Supply, pin 23. . . • . .. + 18V
Negative Supply, pin 19 ...... -18V
Digital Input Voltage, pins 1-16 + 5.5V
Output Current, pin 17 • . . • . .. ± 20 mA

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, and ± 15V supplies unless otherwise noted.
INPUTS
Resolution ................
Coding, unipolar output. . . . ..
Coding, bipolar output •......
Input Logic Level,
bit ON ("0")' . . . . . . . . . . • •.
Input Logic Level,
bitOFF("1")1 ............
Logic Loading. . • . . . . • . . . . ..

16 bits
Compo Binary
Compo Off. Binary
OV to + 0.8V at - 1 mA
+2.4V to +5.5V at +40!"A
1 TIL load

OUTPUTS
Output Voltage Range,
Unipolar2 • • • • • • • • • • • • • • ••
Output Voltage Range,
Bipolar. . . . . . . . . . . . . . • • ..
O~!put,yolta!le Range,
-1 SuffIx .............
Output Current, min... . . . . • ..
Output Impedance. . . . . . . . ..

0 to + 10V
± 5V
± 10V
± 5 mA
0.05 ohm

TECHNICAL NOTES
1. It is recommended that these converters be operated with
local supply bypass capacitors of 1 (. ......•.
Gain Tempco, max. BGC .....
Zero Tempco, unipolar, max.
Offset Tempco,
bipolar, max •.............
Differential Linearity
Tempco, max •............
Settling Time, 10V changeS ...
Slew Rate ...............••
Power Supply Rejection ..... .

±0.003%
14 bits
±0.1%
±0.1%
± 15 ppm/oC
±20 ppm/oC
± 5 ppm/oC of FSR4
± 8 ppm/oC of FSR4
± 2 ppm/oC of FSR4
15 !"sec.
20VI!"sec.
± 0.002% FSR/%

POWER REQUIREMENTS
(Quiescent, all bits high) ..... + 15V dc, ± 0.5V dc at 20 mA
-15V dc, ±0.5V dc at 25 mA
± 12V de operation 7
PHYSICALIENVIRONMENTAL
Operating Temperature Range OOC to + 70°C (BMC, BGC)
-55°C to + 125°C (BMM)
Storage Temperature Range .. -65°C to +150°C
I Package Type ............•. 24 pin ceramic
Pins ......•........••..... 0.010 x 0.018 inch diameter Kovar
IWeight .............•...... 0.2 ounces (6 grams)
FOOTNOTES:

1. Drive from TTL output with only the DAC-HP as load.
2. Unipolar output range for suffix "- 1" models, 0 to + 10V, is reached at 'h
scale input.
3. For all models except DAC-HP16BGC.
4. FSR is 0 to +FS or -FS to +FS voltage.
5. To 0.005% FSR.
6. Pin 17.

7. For ± 12V dc operation, consult factory.

2-48

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

DAC-HP168
APPLICATION
OUTPUT CIRCUIT
21 SUM. JUNC.
FULL SCALE lOUT
= 2mA (Binary)

5K'

> - - - - - 4 > - - - - - 0 17 OUTPUT
lOUT

t

5K
6.4K

•

18 BIPOLAR OFF.
~--------o

24 REF. OUT

+
6.4V
REF
10K FOR -1 MODELS

20 GROUND

POWER SUPPLY BYPASSING

USE OF REFERENCE OUTPUT

NOTE, THE ADDITIONAL 0.01 ~F
CERAMIC BYPASS IS RECOMMENDED
FDR NOISY ENVIRONMENTS.

DACHP16B

DAC-HP16B

+ 6.4V.

24\-----o-----::---t
± 5mA

EXTERNAL
CIRCUITRY

'MAXIMUM OUTPUT
CURRENT IS ± lOIJA

PRECISION INDUSTRIAL POSITION CONTROLLER
POSITION
INPUT
POSITION FEEDBACK

POWER

CaMPARA

DAC-HP16B

TO~/

~P

t---V

-"

r------16BIT
UP/DOWN COUNTER

DIGITAL
CONTROL

r----

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-49

DAC-HP168
CONNECTION AND CALIBRATION
CODING TABLES
BIPOLAR OUTPUT - Complementary Offset Binary
INPUT
MSB
0000 0000
0011 1111
0111 1111
1011 1111
1111 1111
1111 1111

CODE
0000
1111
1111
1111
1111
1111

LSB
0000
1111
1111
1111
1110
1111

SCALE
+FS-1 LSB
+%FS
0
-%FS
-FS+1 LSB
-FS

OUTPUT
VOLTAGE
+4.99985V
+2.50000
0.00000
-2.50000
-4.99985
-5.00000V

OUTPUT VOLTAGE
SUFFIX .. - 1" MODELS
+9.99969V
+5.00000
0.00000
-5.00000
-9.99969
-10.00000V

UNIPOLAR OUTPUT - Complementary Binary
INPUT
MSB
0000 0000
0011 1111
0111 1111
1011 1111
1111 1111
1111 1111

CODE
0000
1111
1111
1111
1111
1111

LSB
0000
1111
1111
1111
1110
1111

SCALE
+FS-1 LSB
+%FS
+%FS
+%FS
+1 LSB
0

OUTPUT
VOLTAGE
+9.99985V
+7.50000
+5.00000
+2.50000
+ 153 fLY
0
BIPOLAR OPERATION

UNIPOLAR OPERATION

17

DAC-HP16B

OUTPUT (0 TO + 10VI

, - - - - - r - - - + 15VDC

18

OUTPUT ( ± 5VI

17

,----~--

18

-----Yv'V--

21

2.2MEG
150K

1-------O--'~---'\IVv-------j'-----~<

1.

ADJ.

50K

150K

22

+ 15VDC

OFFSET

ZERO
2.2MEG ADJ

GAIN
ADJ.

22 1---<>--~---..J'Nv-----f-;G:-:-A;-;:'N--< 50K

50K

I

O.Ol,..F

'----+--_

-15VDC

ADJ.
0.01

'--_--4-_ _ -15VDC

_F

CALIBRATION PROCEDURE
Connect the converter as shown in the application diagrams.
For bipolar operation connect Bipolar Offset (pin 18) to Summing Junction (pin 21). For unipolar operation connect Bipolar
Offset (pin 18) to Ground (pin 20). In making the following adjustments, refer to the coding tables.

UNIPOLAR OPERATION
1. Zero Adjustment. Set the input digital code to 1111 1111
1111 1111 and adjust the ZERO ADJ. potentiometer to give
O.OOOOOV output.
2. Gain Adjustment. Set the input digital code to 0000 0000
0000 0000 (complementary binary) and adjust the GAIN
ADJ. potentiometer to give + 9.99985V output.

BIPOLAR OPERATION
1. Offset Adjustment. Set the digital input code to 1111 1111
1111 1111 and adjust the OFFSET ADJ. potentiometer to
give the - F.S. output shown in the coding table above for
the model being calibrated.
2. Gain Adjustment. Set the digital input code to 0000 0000
00000000 and adjust the GAIN ADJ. potentiometer to give
the + FS - 1 LSB output shown in the coding table above the
model being calibrated.

2-50

ORDERING INFORMATION
MODEL NO.

OPERERATING
TEMP. RANGE

SEAL

DAC-HP16BCG
DAC-HP16BMC

OOC to + 70°C
OOC to + 70°C

EPOXY
HERM.

DAC-HP16BMM

- 55°C to + 125°C

HERM.

DAC-HP16BMC-1
DAC-HP16BMM-1

O°C to + 70°C
-55°C to + 125°C

HERM.
HERM.

ACCESSORIES
Part Number

Description

DILS-3
TP50K

Mating Socket (24-pin socket)
Trimming Potentiometer

For military devices compliant to MIL-STD-883, consult the
factory.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC-HZ Series
12-Bit Hybrid
Digital-to-Analog Converters
FEATURES
•
•
•
•

12-81t binary
5 Output ranges
3 Microseconds settling time
Internal reference and output
amplifier
• High performance

Mse

1

2

3

4

5

6

7

e

9

10

11 12

N/c

@

20VRANGE

@

GENERAL DESCRIPTION
The DAC-HZ Series are high performance,
hybrid 12-bit binary digital-to-analog converters. These converters are manufactured using thin- and thick-film technology.
They are complete and self-contained with
a precision internal reference and fast output operational amplifier. Pin-programmable output voltage ranges are provided
for a high degree of application flexibility;
the output voltage ranges are 0 to + 5V dc,
o to + 10V dc, ± 2.5V dc, ± 5V dc, and
± 10V dc. Current output is also provided.

LSB

I
I

DIA
CONVERTER

I

""

@
CURRENT

@Jour

REFEAENCE
INPUT

@II---~

VOLT. OUT

@

BIPOLAA@~

+6.3V

OFFSET

REFERENCE

~_

REF. OUT

@f----<~-<~

The DAC-HZ Series contains a precision
zener reference circuit. This eliminates
code-dependent ground currents by routing current from the positive supply to the
internal ground node as determined by the
R-2R ladder network. The internal feedback resistors for the on-board amplifier
track the ladder network resistors, enhancing temperature performance. The excellent tracking of the resistors results in a
differential nonlinearity tempco of 2
ppm/oC maximum. The temperature coefficient of gain is 20 ppm/oC maximum and
tempeo of zero is ± 3 ppm/oC maximum.

@+lSVde

@

GAINADJ

@

-15Vdc

MECHANICAL DIMENSIONS
INCHES (MM)

I_

The DAC-HZ Series consists of 6 different
models covering the operating temperature
ranges of O°C to + 70°C, and - 55°C to
+ 125°C. The models come in a 24-pin
ceramic package. Power requirement is
± 15V dc with no 5V dc logic supply required. Input coding is complementary
binary. Voltage output settling time is 3
microseconds to Y2 LSB.

O.190(4*,

1.290 MAX
(32,77)

I

r_----=====>-----,

~~~~~~~~~~~~

T

~050(1,27)
:=E,SOI3.• ,)

---j ~100;2,~~.018(O,46}
ALL DIMENSIONS ARE IN INCHES (MM)

INPUT/OUTPUT CONNECTIONS
PIN
1

5
6

FUNCTION
BIT liN
BIT21N
BIT31N
BIT41N
BIT51N
BIT61N

PIN
7
B
9
10
11
12

FUNCTION PIN
13
BIT7 IN
14
BITB IN
BIT91N
15
BIT 10 IN
16
17
BIT lllN
lB
BIT 12 IN

FUNCTION
NO CONN.
-15VDC
VOLT. OUT
REF. IN
BIPOLAR OFF.
10V RANGE

PIN
19
20
21
22
23
24

FUNCTION
20V RANGE
CURRENT OUT
GROUND
+15VDC
GAIN ADJ.
REF. OUT

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

2-51

•

DAC·HZ SERIES
TECHNICAL NOTES

FUNCTIONAL SPECIFICATIONS
Typical at 25°C and ±15V supplies unless otherwise noted.
DAC-HZI2B
(Binary)

INPUTS
Resolution ...•.••..•••..•
Coding, unipolar output .•••
Coding, bipolar output •....•
Input logic Level,
bit ON ("0") ••.•••••..•••
Input logic Level,
bit OFF ("1 ") •...•••••.••
logic loading ••..•.••.•.••

12 Binary bits
Compo Binary
Compo Off. Binary

DAC-HZI2D
(BCD)
3 BCD Digits
Compo BCD

-

OV to +0.8Vat -1 rnA
+2.4V to +S5V at +40 IJft.
1 TILioad

OUTPUTS
Output Current, unipolar ••.•
Output Current, bipolar •••..
Voltage Compliance, lout ••..
Output Impedance, lout,
unipolar ................
Output Impedance, lout,
bipolar .................
Output Voltage Ranges,
unipolar ................

Output Voltage Ranges,
bipolar .................

Output Current, Vout •..•••.
Output Impedance, Vout .•••

o to -2 rnA, ±20%
±1 rnA, ±20oA>
±2.SV

Oto -1.2SmA, ±10%

-

S kohms
2.8 k ohms

-

OVto + SV
OVto + 10V

Oto + 25V
Oto +SV
Oto +IOV

±2.SV
±5V
±10V
±S rnA min.
O.OSohm

-

PERFORMANCE
Voltage Output
Nonlinearity ............
Differential Nonlinearity .••••
Gain Error, before trimming . .
Zero Error, before trimming •.
Gain Tempeo, max..........

Zero Tempco, unipolar, max ..
Offset Tempco, bipolar, max ..
Dlff. Nonlinearity Tempeo,

max ....................
Monotonlclty .............
Setting Time, lout to Va LSB••
Settling Time, Vout to Va LSB
Slew Rate ................
Power Supply Rejection ....•

±'/2 LSBmax.
± '14 LSB max.
±0.1% of FSR'
±0.05% of FSR'
±20 ppm/·C
± 3 ppmJOC of FSR'
± 10 ppm/OC of FSR'
±2 ppm/OC of FSR'
Over oper. temp. range
300 nsec.

3,",sec. 3
2OV/;t39c.
±0.002% FSR/% Supply'

±V4 LSB max.
±V4 LSB max.

·
··

POWER REQUIREMENTS
Power Supply Voltage •.••••

+15V dc, ±O.SV de at 10 rnA
-ISV dc, ±O.SV de at 16 rnA
± 12V de operation 4

PHYSICAL/ENVIRONMENTAL
Operating Temperature
Ranges ............. , ••
Storage Temperature Range.
Package Size .............
Package Type .... , ........
Pins .....................
Weight .•.....•..•.•.•....

OOCto +70OC
and ·SS·C to + 12S·C
-6S·C to + IS0·C
1.300 x 0.800 x 0.160 inches
24 Pin Ceramic DIP
Kovar 0.010 x 0.Q18 inches
0.22 ounces (63 grams)

·Specifications same as first column
FOOTNOTES:
1. FSR is full scale range and is tOVlor 0 to +IOV or -SV to +SVoutput; 20V for
± 10V output, etc.
2. Current output mode.
3. For 2.Sk or Sk feedback. For 10k feedback the settling time is 4 microseconds.
4. For ±12V de operation, contact lactory.

2-52

1. The DAC-HZ12 series converters are designed and
factory calibrated to give ±V2 LSB linearity (binary
version) with respect to a straight line between end
pOints. This means that if zero and full scale are exactly adjusted externally, the relative accuracy will be
±V2 LSB everywhere over the full output range
without any additional adjustments.
2. These converters must be operated with local supply by-pass capacitors from + 1SV to ground and
-1SVto ground. Tantalum type capacitors of 1!F are
recommended and should be mounted as close as
possible to the converter. If the converters are used
in a high frequency noise environment a 0.D1!F ceramic capacitor should be used across each tantalum
capacitor.
3. When operating in the current output mode the
equivalent internal current source of 2 mA must drive
both the internal source resistances and the externalload resistor. A 300 nanosecond output settling
time is achieved for the voltage across a 100 ohm
load resistor; for higher value resistors the settling
time becomes longer due to the output capacitance
of the converter. For fastest possible voltage output
for a large transition, an external fast settling amplifier such as DATEt.:s AM-SOO should be used in the
inverting mode. Settling time of less than 1 microsecond can be achieved. See application diagram.

CALIBRATION PROCEDURE
1.

Select the desired output range and con nect the converter up as shown in the Output Range Selection table and the Standard Connection diagrams.

2. To calibrate, refer to the Coding Tables. Note that
complementary coding is used.
3. Zero and Offset Adjustments
For unipolar operation set all digital inputs to "1"
(+2.0 to +S.SV) and adjust the ZERO ADJ. potentiometer for zero output voltage or current. For bipolar operation set all digital inputs to "1" and adjust the
OFFSET ADJ. potentiometer for the negative full
scale (for voltage out) or positive full scale (for current out) output value shown in the Coding Table.
4. Gain Adjustment
Set all digital inputs to "0" (OV to +0.8V) and adjust
the GAIN ADJ. potentiometer for the positive full
scale (for voltage out) or negative full scale (for current out) output value shown in the Coding Table.

OUTPUT RANGE SELECTION
BIN. RANGE

CONNECT THESE PINS TOGETHER

±10V
±5V
±2.5V
+10V
+SV

15 & 19
15 & 18
15 & 18
15 & 18
15 & 18

17 &20
17 &20
17 &20
17 &21
17 & 21

±1 rnA
-2mA

-

17 &20
17 &21

-

-

16 & 24
16&24
19 & 20 16 & 24
16 & 24
19 & 20 16&24

-

-

16&24
16&24

VOLTAGE OUTPUT IS AT PIN 1S.
CURRENT OUTPUT IS AT PIN 20.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DAC·HZ SERIES
CURRENT OUTPUT CONNECTIONS

VOLTAGE OUTPUT CONNECTIONS
(FOR DIFFERENT OUTPUT SCALING REFER TO OUTPUT RANGE
SELECTION TABLEI

lSB

12

UNIPOLAR
LSB

12

DIGITAL

INPUTS

DIGITAL

Your .. 0 TO -200 mV

1

INPUTS 6
100 \1

_15V

C (0.00.
TO 0,01 "F)

MSB

1

GAIN

AOJ

Mse

10K TO lOOK

28 MEG

,

GAIN
ADJ
10K TO lOOK

.15V

BIPOLAR
LS8

lSB

12

BIPOLAR

12

ZERO AOJ

2" MEG
DIGITAL 7

INPUTS 6
2" MEG

Your

ZERO

= i

100 mV

0>-+----->--1f----~NY~~,0K ~gJ lOOK
C (0001

TOOO' "F)

MSB

GAIN
ADJ
10K TO lOOK

2.8 MEG

1

MSB

.15V
GAIN
ADJ
10K TO lOOK

CODING TABLES

BIPOLAR OUTPUT COMPLEMENTARY OFFSET BINARY

UNIPOLAR OUTPUT - COMPLEMENTARY BINARY
BINARY INPUT CODE
MSB

0000
0011
0111
1011
1111
1111

LSB

0000
1111
1111
1111
1111
1111

0000
1111
1111
1111
1110
1111

UNIPOLAR OUTPUT RANGES

o TO

+10V

+9.9976V
+ 7.5000
+5.0000
+ 2.5000
+0.0024
0.0000

o TO

BIPOLAR OUTPUT RANGES

INPUT CODE

+5V

OTO -2mA

MSB

+4.9988V
+3.7500
+2.5000
+ 1.2500
+0.0012
0.0000

-1.9995 mA
-1.5000
-1.0000
-0.5000
-0.0005
0.0000

0000 0000 0000
0011 1111 1111
0111 1111 1111
1011 1111 1111
1111 1111 1110
111111111111

LSB

t 10V
+9.9951V
+5.0000
0.0000
-5.0000
-9.9951
-10.0000

t5V
+4.9976V
+2.5000
0.0000
-2.5000
-4.9976
-5.0000

t 2 .5V
+2.4988V
+ 1.2500
0.0000
-1.2500
-2.4988
-2.5000

±1 rnA

-0.9995 mA
-0.5000
0.0000
+0.5000
+ 0.9995
+ 1.0000

EQUIVALENT CURRENT MODE OUTPUT CIRCUIT
6.3k
VOUT

=

.t2,~V MAXIMUM
(OUTPUT VOL T AGE
COMPLIANCE'

.'OUT

DAC·HZ12B

REa
Rea

= RO =- 5K for unipolar operation
= RR II Ro = 2.BK for bipolar operation

lOUT = 2mA binary

DATEl, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194iTEl (508) 339-3000iTlX 174388/FAX (508) 339-6356

2-53

DAC·HZ SERIES
USE OF HIGH SPEED EXTERNAL OP AMP FOR FASTER SETTLING
flefer to the
Output flange
Selaction Table.
11}-'·::;IP:..::O:.::L~AR=O:..:FF..:S.:.ET,--_ _ _ _ Pm 20 Of 21
Where pin 15 appears
use pin X of external
amplifier and scale as
18
10 v. RANGE
DACHZ12B
desired
19

2OV.RANGE

~,}-..:CU~R~R~E~N~T.:.O.:.UT,--_ _ _'O~U~T_ _~
A,

+
A,

~

EXTERNAL HIGH SPEED INVERTING
OPAMP, USE DATEl
AM-500 FOR LESS THAN 10.SEC
OUTPUT SETTLING

PRECISION, LOW COST BASE LINE RAMP GENERATOR

12

1281l
BINARY
COUNTER

DAe
HZ12B

RATE
ADJUST

RESET

.10V

EXTAEMEL Y LINEAR
OUTPUT

ov~

_ _ _ _ _ _ _ __

THIS CIRCUIT DEVELOPS A HIGHLY LINEAR \.01%)
OUTPUT VOLTAGE RAMP FROM 0 TO .'0V. THE RAMP
CAN 8E MADE AS SLOW AS DESIRED WITHOUT
AFFECTING LINEAR lTV BY SETTING THE PULSE
RATE OF THE TIMING CIRCUIT TO THE PROPER

VALUE. THE OUTPUT RAMP IS GENERATED IN
DISCRETE STEPS OF .02.% FS 14096 STEPS FOR

ORDERING INFORMATION
MODEL NO.

OPERATING
TEMP. RANGE

SEAL

DAC·HZ12BGC
DAC·HZ12BMC
DAC·HZ12BMM
DAC·HZ12DGC
DAC·HZ12DMC
DAC·HZ12DMM

O°C to + 70°C
O°C to + 70°C
-55°C to + 125°C
O°C to +70°C
O°C to +70°C
O°C to + 70°C

Epoxy
Hermetic
Hermetic
Epoxy
Hermetic
Hermetic

ACCESSORIES
Part Number

Description

DILS·3
TP10K or TP100K

24·pin Mating Socket
Trimming Potentiometers

For military devices compliant to MIL-STD·883, consult
DATEL

FSCHANGE).

2-54

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC-IC10B Series
Low Cost, 10-Bit Monolithic
Digital-to-Analog Converter

FEATURES
•
•
•
•
•
•

10-Bit resolution
Straight binary coding
Current output
250 Nanosecond settling time
TTL/CMOS-compatible
Low cost

DIGITAL INPUTS

BIT NO.

MSB
1

lSB
3

8

4

9

10

•

GENERAL DESCRIPTION
The DAC-IC1 OB is a low cost, 10-bit monolithic DAC with fast output current settling
time. It is packaged in a l6-pin ceramic
DIP and requires only an external reference and operational amplifier for voltage
output operation. A full-scale change in
output current settles in 250 nanoseconds,
and with a fast I.C. operational amplifier
(such as DATEL's AM-452) a 10V output
change can settle within 1 microsecond.
Digital input coding is straight binary for
unipolar operation, and offset binary for
bipolar operation; the logic inputs are compatible with TTL or CMOS.
This converter is manufactured with monolithic bipolar technology. The circuit incorporates 10 fast switching current sources
which drive a diffused resistor R-2R network. The ladder network is laser trimmed
by cutting aluminum links. The circuit also
contains a reference control amplifier and
a bias circuit. An external reference current of 2 mA is required at the + Reference input terminal; this is accomplished
by an external voltage reference and a
metal film resistor.
Other characteristics of the DAC-IC10B include linearity to ± % LSB and guaranteed
monotonic performance. The gain temperature coefficient of this unit is typically
- 20 ppm/oC. Output voltage compliance
is - 2.5V to + 0.2V, permitting direct driving of a 6250 resistor for a voltage output.
The reference input current can be varied
from 0.5 mA to 2.5 mA to give monotonic
operation as a one- or two-quadrant
multiplier.
Power supply requirement is + 5V dc and
-15V dc. The DAC-IC10B is available in
three models covering two temperature
ranges, O°C to + 70°C and - 55°C to
+125°C.

OUTPUT
CURRENT

FAST CURRENT SWITCHES

INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (MM)

FUNCTION

P'N

16
1

DATEl

2

PIN 1
REF.

1

1

L.

-I I- o.ow.mAX.

~r--

0.810 MAX.
(20,6)

8

---I-)

.2
00MAX'Mm --L
1
(5,1)

-r

I

.055 MAX.

O'Ofo.~t~ L
-W

---.J

L

-r [-

0.100
(2,5)

(1,4)

A- o.ol~.~AX
1_

!

0.300--l
(7,6)

-I

.

-VEE
GROUND

3

OUTPUT CURRENT

4

BIT 1 IN (MSB)

5

BIT 21N

6

BIT 31N

7

BIT 41N

8

BIT 5 IN

9

SIT61N

10

BIT 71N

a IN

11

SIT

12

BIT91N

13

BIT 10 IN

14

+Vcc

15

-REFERENCE

16

+ REFERENCE

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

2-55

DAC-IC10B
ABSOLUTE MAXIMUM RATINGS
Vcc ••...•...................
V!'E .•..•.....•.•......•••••..
Digital Input Voltage. . . . . . . . . • ..
Output Voltage, Pin 3 . . . . . . . • . ..
Reference Current. . • • . . . . . . . •.
Different Reference Voltage .•••.

TECHNICAL NOTES
+7.0V
+ 18.0V
+ 15V
+ 0.5, - 5.0V
2.5 rnA
0.7V

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, Vcc

= +5V, VEE = -15V, IREF = 2.0 mAo

INPUTS
Resolution ...•.......•.......
Coding, Unipolar Output ....... .
Coding, Bipolar Output .•.......
Input Level, Logic" 1" ......... .
Input Level, Logic "0" ..•.....••
Nominal Reference Current,
Pin 16 .......•.............
Reference Current Range ...... .
Reference Bias Current,
Pin 15 ........•..•.•.......

10 Bits
Straight Binary
Offset Binary
+ 2.0 to + 15V at + 20 I'A
o to +0.8V at -.02 rnA
2.0 rnA
0.5 rnA to 2.5 rnA
-5

~

maximum

OUTPUTS
Output Current •..•.••......•..
Output Current Range ......... .
Output Current, All Bits "0"
Output Voltage Compliance .•...
Output Capacitance •..••.....••

4.0 rnA ± 0.2 rnA

o to 5.0 rnA

2.0 ~ maximum'
-2.5 to +0.2V
25 pF

PERFORMANCE
Linearity Error, B, BM .•...••.•.
BC .•...•.......
Differential Linearity Error ...•...
Monotonicity, B, BM .......... .
BC ....••....•.•.
Gain Tempeo ......•.......•..
Reference Current, Slew Rate .•..
Reference Current Settling .•....
Output Current Settling ...••.•..
Update Rate ................. .
Power Supply Sensitivity .••.....

± 'h LSB, maximum
± 1 LSB, maximum
± 'h LSB

Full Temperature Range2
At 25°C
-20 ppm/oC,
60 ppm/oC maximum 3
20 rnA/microseconds
2.0 microseconds4
250 nanoseconds'
4 MHz
02%/% maximum

POWER REQUIREMENTS
VccVoltage ............•••....
VccCurrent. .•.....•..........
VEE Voltage. . . • . . . . • . . . • . . . . ..
VEE Current. • . . . . • • . . . . . . . . . ..

+5Vdc +0.25V
+4 rnA maximum
-15V de ± 0.75V
-18 rnA maximum

PHYSICAL/ENVIRONMENTAL
Operating Temperature Range
DAC-IC10B, BC ......•.......
DAC-IC10BM .•.......•.......
Storage Temperature Range. . . ..
Package ...........••...•••..

OOC to + 70°C
-55°C to +125°C
- 65°C to + 125°C
16-Pin Ceramic DIP

FOOTNOTES:

,. 4.0 "A maximum for DAC·IC' aBC only.
2. All converters in this series typically retain rated monotonicity for values of input
reference current from 0.5 rnA to 2.5 rnA.
3. 70 ppm/oC maximum for DAC·IC'OBM only.
4. Zero to 4 rnA output change to rated accuracy.
5. Full scale change to y, LSB.

2·56

1. The General Connection Diagram shows the basic connections for the converter. The scale factor is set by a reference
current injected into pin 16. Pins 15 and 16 are the input terminals to the reference control amplifier:When connected as
shown, pin 15 is grounded through R,s and pin 16 is at virtual
ground. Therefore, the reference current is determined by
the external voltage reference and R'6: IREF = VREFfR,6. R'6
should be a stable metal film resistor. R,s is used only to
compensate for the input bias current into pin 15 (1 pA
typical). R,s, if used, should be equal to R'6 and may be a
carbon composition type. An IREF of 2.0 rnA is recommended
for most applications.
2. There is a second method of connecting the reference
shown in Two Ways to Connect Referencl;!. A negative reference can be applied to pin 15. In this case only the bias current must be supplied from the reference since pin 15 is a
high impedance input. Pin 16 is at the negative voltage and
IREF still flows into pin 16. Again, R,s is used only to campen·
sate for bias current. There is an important requirement for
this connection: the negative reference voltage must
always be 3 volts above VEE'
3. lOUT is inversely proportional to the reference input current
(lREF) times the digital word. Scaling of the applied reference
can be represented as follows:
VREF
An
RREF
2n
where n = 10 (10-bit DAC)
An = digital code
Note: 1) The largest digital code for a 10 bit DAC is 1023.
2) The reference current is scaled by a factor of 2
within the DAC.
Example:
lOUT = - 2

lOUT (FS)

-2

2.5V
1.25K

1023
1024

- 3.996 rnA (nominal)
lOUT (ZERO)

-2

2.5V
1.25K

_0_
1024

o rnA (nominal)
4. The reference amplifier is internally compensated. The
minimum reference current supplied from a cumint source is
0.5 rnA for stability.
5. The voltage on pin 3 is restricted to a range of - 2.5V to
+0.2V. This compliance voltage is guaranteed at 25°C and
nearly constant over temperature.
6. Full-scale output current of 3.996 rnA is guaranteed for input
reference currents to pin 16 between 1.9 and 2.1 rnA.
7. It is recommended that pin 14 (Vce) and pin 1 VEE) always be
bypassed to ground with at least 0.1 "F capacitors located
close to the pins.
8. The accuracy of the converter is specified for a reference
current of 2.0 rnA; the accuracy, however, is essentially can·
stant for reference currents from 1.5 rnA to 2.5 rnA. Typically,
this device is monotonic for all values of reference current
above 0.5 rnA.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC-IC10B
TECHNICAL NOTES (Cont'd.)

CONNECTION FOR DIRECT VOLTAGE OUTPUT

9. For fastest voltage output settling times in either unipolar or
bipolar modes, two circuits using DATEL AM-452 monolithic
operational amplifiers are recommended. These circuits,
with the compensation shown, result in output settling times
of typically 550 nanoseconds for a 10V change to 1 LSB.
This is the worst case settling time which occurs when all bits
are turned on. For current output and RL less than 500 ohms,
this time is 250 nanoseconds; when all bits are turned off the
time is shorter, typically 100 nanoseconds. The two circuits
shown also illustrate a simple method of deriving both
reference current and offset current from a precision 6.4V
Zener reference diode.
10.Both one and two quadrant multiplication are also possible
with the converter as shown in the two diagrams. V ,N is
shown operating into pin 16; this results in an input impedance of 2.5K. Alternatively, V ,N can be applied to pin 15
for a high impedance input as explained previously. The
range of V,N is then 0 to - 10V. For two quadrant multiplication V,N is unipolar and the digital input is bipolar with offset
binary coding. VOUT then varies over the bipolar range of
±5V. In multiplication applications, it is recommended that
full scale IREF be set to 2.0 rnA; the output is then monotonic
as the reference current varies over 0.5 rnA to 2.0 rnA.

+5VDC

r-1

=O.l~F

BIT

1.25K MF

14

MSB

16

IREF

+

5
6

2.5V

15

Oto-2.5V

10

,.

625<2

11
12
13

LSB 10

i

~F
Mf-Metal Film
-15V

GENERAL CONNECTION DIAGRAM
+5VDC

TWO WAYS TO CONNECT REFERENCE
BIT
14

MSB

+
VREF

10
11
12
13

LSB 10
VREF

=

2mA

R'6

~F
MF-Metal Film

-15VDC

CONNECTION FOR BIPOLAR VOLTAGE OUT
+5VDC

DIGITAL4-TO-20 MA OR
1-TO-5 VOLT CONVERTER

01~

~F

BIT
14

MSB 1

16
15

IVCCQf7411-3V)

+VREF -

R'6
__ 2mA
R'5

+VLOOP (MUST NOT EXCEED

1105mA
4.99 K

R,

FmA

R,

REF
IN

,oon

VREF
MPS A66

7

10

B

11

LSB 10

13

0704;A

:!:5V
4K

12

~

14to20mA

R,+R 2

2V

1-----;,"-

'K

1 to5V

O.l~F

~

VREF :::= 2mA
R'6

VREF
R,

- 2 A
- m

-15V DC

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

2-57

DAC-IC10B
APPLICATION DIAGRAMS
TWO QUADRANT MULTIPLICATION

ONE QUADRANT MULTIPLICATION

BIT

MSB

14

4.99K l%MF
I. I--~V\,'~"" VIN

1

15 f---<>-'VV\n

BIT

mTO + lOV)

MSB

14

15

2.49Kl%MF

5K

4.99K l%MF
'.I--o-../\J"'.A~~-o

1

t---o--'V'",'v-~

5K

2.49K l%MF

OAeIC10B

Your
(0

LSB

Vour) ±5V)

TO + lOV)

10

FAST, UNIPOLAR VOLTAGE OUTPUT

FAST, BIPOLAR VOLTAGE OUTPUT

GAIN ADJ.

GAIN ADJ.

+5V

r'\MM"'N'v-.-------<: + 15V

t"'\1V\~--'r--"v'A----'VV'",

15 r-- and pin 3 (VEE) always
be bypassed to ground with at least 0.1 p,F capacitors located
close to the pins.

PHYSICAUENVIRONMENTAL
Operating Temp. Range,
DAC-IC8BC .....................
Operating Temp. Range,
DAC-IC8BM .....................
Storage Temp. Range, either
model .........................
Package, DAC-IC8BC ..............
Package, DAC-ICBBM . . . . . . . . . . . . ..

2. There is a second method of connecting the reference
shown in Two Ways to Connect Reference. A negative
reference can be applied to pin 15. In this case only the bias
current must be supplied from the reference since pin 15 is a
high impedance input. Pin 14 is at the negative voltage and
IREF still flows into pin 14. Again, R15 is used only to compensate for bias current and may be omitted. There is an important requirement for this connection: the negative reference
voltage must always be 3 volts above VEE'

±V. LSB (±O.19%) max.
±'h LSB ~±0.19%) max.
±'hLSB ±0.19%)
- 20 ppmloC
2. 7 ~N max.
300 nsec.
3.3 MHz
4.0 mNl'sec.

POWER REQUIREMENTS
Vcc Voltage .......................
Vcc Current .......................
VEE Voltage .......................
VeE Current .......................

1. The General Connection Diagram shows the basic connections for the DAC-ICB8 converter. The scale factor is set by a
reference current injected into pin 14. Pins 14 and 15 are the
input terminals to the reference control amplifier. When connected as shown, pin 15 is grounded through R. s and pin 14
is at virtual ground. Therefore, the reference current is determined by Ihe external voltage reference and R 14: IREF =
VREF/R14. R14 should be a stable metal film resistor. R15 is
used only to compensate for the input bias current into pin 15
(1 p,A typical) and can be shorted out with negligible effect.
R 15, if used, should be equal to R14 and may be carbon composition type. An IREF of 2.0 mA is recommended for most
applications .

O°C to 70·C
-55°C to +125°C
-65°C to + 150°C
16 Pin Plastic DIP
16 Pin Ceramic DIP

6. As shown in the General Connection Diagram, pin 1 may be
either connected to ground or left open. This connection
determines the voltage compliance at pin 4 (lOUT)' For pin 1
grounded, the output compliance is - 0.6 to + 0.5 volt. This
is satisfactory when pin 4 is used to drive a current to voltage
converter and pin 4 is held at virtual ground. It is also
satisfactory for low values of Rl connected to pin 4 to directly
convert the output current to a voltage. The voltage compliance may be extended to - 5.0 volts by leaving pin 1 open
and using a VEE more negative than -10 volts. In this way a
2.5K load resistor may be used at pin 14 to give an output
voltage range of 0 to - 5 volts (with reference current of 2
mAl. As shown in the table of Settling Time vs RL, the output
settling time is constant (300 nseconds) for RL values from
D to 500 O.l:)[Tl5; thereafter itincre?sel?, to, 1,.~ fol?econds Jor
FlL = 2.5K.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DAC-ICS8
recommended. These circuits, with the
compensation shown, result in output
settling times of typically 600
nanoseconds for a 10 volt change to 1
LSB. This is the worst case settling time
which occurs when all bits are turned
on. For current output and RL less than
500 ohms, this time is 300 nanoseconds; when all bits are turned off the
time is shorter, typically 100 nanoseconds. The two circuits shown also illustrate a simple method of deriving
both reference current and offset current from a precision 6.4 volt Zener
reference diode.
9. Both one and two quadrant multiplication are also possible with the DAC-

TECHNICAL NOTES (Con't)
7. The accuracy of the DAC-ICBB is
specified for a reference current of 2.0
mA; the accuracy, however, is essentially constant for reference currents
from 1.5 mA to 2.5 mA. Typically, this
device is monotonic for all values of
reference current above 0.5 mAo
Reference currents up to 4.2 mA may
be used. When using a 4 mA reference
current, VEE must be more negative
than - 6 volts.
B. For fastest voltage output settling times
in eith.er unipolar or bipolar modes, two
circuits
using
DATEL's
AM-452
monolithic operational amplifiers are

ICBB as shown in the two diagrams. V1N
is shown operating into pin 14; this
results in an input impedance of 2.5K.
Alternatively, V 1N can be applied to pin
15 for a high impedance input as explained previously. The range of V 1N is
then 0 to -10V. For two quadrant multiplication V1N is unipolar and the digital
input is bipolar with offset binary
coding. VOUT then varies over the
bipolar range of ± 5 volts. In multiplication applications, it is recommended
that full scale IREF be set to 4.0 mA; the
output is then monotonic as the
reference current varies over 0.5 mA to
4.0 mAo

CONNECTION DIAGRAMS
HIGH COMPLIANCE OUTPUT

OUTPUT CONNECTIONS

'5V

0.1
,F

R

.I
221K,1%

MS6

1

,-o-AN'v-<>-"N\~-Q Ot6.4V REF

i---':>----T---0 ~~~T -'5VI
2.49K
1%

LSB

S

SETTLING TIME VS. RL
R

0
500
1K
2.5 K

GENERAL CONNECTION DIAGRAM

S.T.
JUU nsec.

300 nsec.
400 nsec.
1.2 I'sec.

Vee (+5V)

0.1

"FI
13

14 '-O--''I'v'\r--....- - - ,
15 f-0---'VV'v-,

f-0----0

'OUT

.OPEN

16

COMPENSATION TABLE
Ale

Cc

t.OK

1SpF

2.SK

37 F

S.OK

75 pF

0.1

"FI

VEE 1-5 TO· 15VI

For high compliance output (+O.5V to --5.0V)
leave pin 1 open and use -10 to -15V tor VEE'

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2·61

•

DAC-ICS8
CONNECTION DIAGRAMS
TWO WAYS TO CONNECT REFERENCE

ALTERNATIVE COMPENSATION
+Vcc

4 - Z IN"'R , 4
R'4

IREF

",.

1.OK

, S!-.(}--JVVV--.

"'5

-:;:

-:;:

R+1K
-:;:
IREF = VREF/R,4
NOTE: -VAEF must be 3 volts above

Vee

15pF

APPLICATION DIAGRAMS
ONE QUADRANT MULTIPLICATION

MSB

2.49K 1% MF
14I-o-~Wv---o

1

VIN

(0

TWO QUADRANT MULTIPLICATION

TO +10Vf

2.4K

VOUT (t5V)

O.l.11 F

I

FAST, BIPOLAR VOLTAGE OUTPUT

FAST, UNIPOLAR VOLTAGE OUTPUT
FULL SCALE

ADJ.

+6.4V

/ '

t---"'Vv---.....~Wv--o +1SV

..

2,15K

r-JI}..I'v1p.M.-~----ot15V

.

500

2.0K

13
MS8

1%

2.B7K

2.0K
1%
IN4571

loOK 1%

MSB

1

1-00-'II\1\r--1 0.1 lmA
.I-o-~~-'.' t---~I\r---_,

1
Q,l"F

4.99K 1%

lOUT

AM-452

510

VOUT (-5V TO +SV)
OUTPUT SETTLING

'" 600 Nsec. to 1 LSB.

NOTE: t15V POWER SUPPLY
CONNECTIONS NOT SHOWN FDA

NOTE: t15V POWER SUPPLY
CONNECTIONS NOT SHOWN FOR
AMPLIFIER

AMPUFIER

-15V

2-62

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

DAC-ICSB
CALIBRATION AND CODING TABLES
1. Select the desired output range by means of the feedback
resistor of the external operational amplifier and the externally programmed reference current.
2. Zero and Offset Adjustments
For unipolar operation, set all digital inputs to "0" (OV to
+0.8V) and adjust the output amplifier ZERO ADJUSTMENT for zero output voltage. For bipolar operation, set all
UNIPOLAR OPERATION-STRAIGHT BINARY CODING
INPUT
MSB
1111
1110
1100
1000
0100
0000
0000

CODE
LSB
1111
0000
0000
0000
0000
0001
0000

o TO +5V
+4.980
+4.375
+3.750
+2.500
+1.250
+0.020
0.000

UNIPOLAR OUTPUT RANGES
OTO +10V OTO -2 rnA
-1.992 rnA
+9.961V
-1.750
+8.750
+ 7.500
-1.500
-1.000
+5.000
-0.500
+2.500
+0.039
-0.008
0.000
0.000

OTO -4 rnA
-3.984 rnA
-3.500
-3.000
-2.000
-1.000
-0.016
0.000

digital inputs to "0" (0 to + 0.8V) and adjust the OFFSET
ADJUSTMENT for the negative full scale voltage shown in
the Coding Table.
3. Gain Adjustment
For either unipolar or bipolar operation, set all digital inputs to
"1" (+ 2.0 to + 5.5V) and adjust the GAIN ADJUSTMENT
for the positive full scale voltage shown in the Coding Table.

BIPOLAR OPERATION-OFFSET BINARY CODING
INPUT CODE
MSB
LSB
1111
1111
1110
0000
1100
0000
1000
0000
0100
0000
0000
0001
0000
0000

BIPOLAR OUTPUT RANGES
±1 rnA
±10V
-0.992 rnA
+9.922V
-0.750
+ 7.500
-0.500
+5.000
0.000
0.000
-5.000
+0.500
-9.922
+0.992
-10.000
+1.000

±5V
+4.961V
+3.750
+2.500
0.000
-2.500
-4.961
-5.000

±2rnA
-1.984 rnA
-1.500
-1.000
0.000
+1.000
+1.984
+2.000

ORDERING INFORMATION
DAC-ICSB

4

ACCESSORIES
Part Number
TP500, TP1K, and
TP20K are available
from DATEL

0PER. TEMP. RANGE
C
M

= O°C TO +70°C
= -55°C TO + 125°C

Description
Trimming Potentiometers

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-63

DAC·UP10B
10·Bit Monolithic DAC
With Input Registers

FEATURES
•
•
•
•
•

Input registers
10-Bit resolution
Voltage output
Internal reference
Guaranteed monotonicity

GENERAL DESCRIPTION
The DAC-UP10B is a low cost, monolithic
10-bit D/A converter with internal registers.
The device also includes a high speed output amplifier, stable internal reference,
and an input reference amplifier. Low
loading latches, adjustable logic thresholds and addressing capability allow the
DAC-UP10B to directly interface with
many microprocessor and logiC controlled
systems.
The input registers are controlled by two
enable lines (LOAD 1, LOAD 2). When the
enable inputs are low, the registers are active, and any change on the digital inputs
will be reflected on the analog output.
When the enable inputs are high, the
digital inputs become very high impedances and the data present is retained
until the enable lines go low. The two
enable inputs allow the converter to be
directly interfaced with an 8-bit data bus.
The output voltage range is 0 to + 10V dc
for unipolar mode, ± 5V dc for bipolar. A
full-scale output change settles to within
0.05% in 5 microseconds. The internal
band gap reference is buffered and
amplified to provide the 5V reference output. Either the internal reference or, for increased accuracy, an external reference
can be used to bias the current switching
networks.
Other characteristics of the DAC-UP1OB
include guaranteed monotonic performance, a Gain Temperature Coefficient of
only 20 ppm/oC, and Zero Tempco of 5
ppm/oC. The power supply voltage range
is ± 11.4V dc to ± 16.5V dc.
The DAC-UP10B is packaged in a 24-pin
plastic DIP, and operation is specified over
the 0 to + 70°C operating temperature
range.

MSB Bif
1
2

BIT BIT !;lIT BIT
3
4
5
6

MECHANICAL DIMENSIONS
INCHES (MM)
24

T

DATEL

0.550
(13.9)

~
PIN 1
IDENT

j

13

12

I

~~5~

0.18
(4.6)

PIN

0.052
(1.3)

0.110
(2.6)

FUNCTION

PIN

FUNCTION

1

OIG. GRND

2

BIT 10 IN (LSB)

I

,.

[OAll2

3

BIT giN

REF. OUT

•

15

SIT81N

16

- REF IN

5

BIT71N

17

+ REF IN

6

BIT BIN

18

BIPOLAR OFF.

7

SlT51N

19

- 15

8

BIT 41N

20

OUTPUT

0.20

~)

~---.l0.il45

-- JI KKK KKK KWKWl

LOAD!

0.600
(15.2)

~

I

BIT BIT BIT lSB
7 B
9
1_o

INPUT/OUTPUT
CONNECTIONS

-1

DAC·UP10B

n~~ ~

2-64

DIGITAL
GND

~I_ r-r
(1.1)

13

REF. ADJ

voe

9

BIT 31N

21

+ 15 VDC

10

BIT 21N

22

SUM. JUNC.

11

=,

BIT 11N

23

AMP. COMP.

2.

ANALOG GRNO.

12

0.021
(0.5)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DAC-UP10B
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS
Positive Supply, Pin 21 •.....•......
Negative Supply, Pin 19 ........... .
Digital Input Voltage, Pins 2-11 .....•
Reference Input, Pin 17 ........... .
Summing Junction, Pin 22 ......... .

+ IBV de
-IBV
+ lBV
+ 12V
+ 12V

de
de
de
de

FUNCTIONAL SPECIFICATIONS
Typical at + 2SoC, ± lSV dc supplies, ref. in = + SV unless otherwise
noted.
INPUTS
Resolution . • • . . . . . . . . • . . . . . . . . . ..
Coding, Unipolar ..................
Bipolar ........•...••...•.
Input Logic Level,
Bit ON ("1") min.' ......•........
~ OFF ("0") max.' .............
Load Inputs ......................

10 Bits
Straight Binary
Offset Binary

+2Vat 10"A
+O.BVat 10 pA
High ("I ") = Hold Data
Low ("0") = Transfer Data
Load Pulse Width, min. . . . . . . . . . . . .. 150 nsee.
Reference Input Voltage ...•........ 5V dc, ± 10%
Reference Input Resistance . . . . . . . . . 5 k!l

OUTPUT
Output Voltage Range, Unipolar .....
Bipolar. . . . ..
Output Current ............•...•..
Reference Output Voltage2 •••.••••••
Reference Output Current, max. . ....

+ 10V de
± 5V de
5 mA
5V ± 10%
3 mA

PERFORMANCE
Linearity Error, max ................
Differential Linearity Error . . . . . . . . . .
Monotonicity .....................
Gain Error .......................
Zero Error .......................
Gain Tempc03 • • • • • • • • • • • • • • • • • • • •
Zero Tempco, Unipolar3 ••••••••••••
Reference Tempc02 •••••••••••••••
Settling Time, 10V to O.OS% .........
Power Supply Sensitivity, max .......

±1 LSB
±1 LSB
Over Operating Temp. Range
Adjustable to Zero
Adjustable to Zero
20 ppm/oe
5 ppm/oe
60 pprn/oe
5 psee.
±0.01% FS/%Vs

POWER REQUIREMENTS
Rated Power Supply Voltage ........
Power Supply Voltage Range ........
Supply Current, Quiescent max. 4 ••..
Power Dissipation, max. 4 •••••••••••

1. The Load control inputs (pins 12, 13) are level triggered inputs. The Load 2 in~in 13) controls the two most significant bits while the Load 1 inpuUQi.rl. 12) controls the eight
least significant bits. When the Load inputs'are "Logic 1",
the input registers will hold the data present, a "Logic 0",
activates the registers, transferring data to the converter
output.
2. A set-up time of 100 nanoseconds minimum must be allowed
before the Load inputs go from low to high. In addition, a 50
nanosecond minimum Hold Time must be allowed for the input data after the Load inpu~ from low to high. The
minimum pulse width for the Load inputs is 150 nanoseconds. The maximum update rate is determined by the output
settling time. See Timing Diagram.
3. The digital inputs of the DAC-UPI OB utilize a differential logic
system with a threshold level of + 1.4 volts with respect to
the voltage level on the digital ground pin (pin 1). Bias circuits
are shown that will provide the proper threshold voltage
levels for various logic families.
4. The - Ref input (pin 16) is uncommitted to allow utilization of
negative polarity reference voltages. In this mode, the + Ref
input (pin 17) is grounded and the negative reference is tied
directly to th6 - Ref pin.
5. It is recommended that the ± 15V power input pins both be
bypassed to ground with 0.1 p.F ceramic capacitors. Also, to
minimize capacitance, external resistors should be mounted
as close to the ref. adj. pin (pin 14) as possible. These
precautions along with good layout practices will insure noise
free operation.
6. The gain tempco of the DAC-UP10B without the internal
reference is 20 ppm/oC. By using the internal reference,
which has a tempco of 60 ppm/oC, a total tempco of 80
ppm/oC typical results for the converter. If greater temperature stability is required, a more stable external reference
may be used.
7. The output amplifier incorporates output short circuit protection for both positive and negative excursions. Short circuit
current is typically limited at ± 15 mAo

± 15V de
± llAV de to ± 16.5V de
+ 14 rnA, -15 mA
435 mW

PHYSICAL/ENVIRONMENTAL
Operating Temperature Range ....... ooe to + 70 0 e
Storage Temperature Range ........ -65°e to +150 oe
Package ......................... 24 Pin Plastic Dip
FOOTNOTES:

1. Bias circuits shown will provide the proper threshold voltage levels for various
logic families. See technical note 3.

2. Ref. output current == 1 mA
3. Ref. in = +5V
4. Vs = ± 15V dc, Iref = 1 mA

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

2-65

."
"

DAC-UP10B
CONNECTION AND CALIBRATION
LOAD 1

LOAD 2

CALIBRATION PROCEDURE
1. Select the desired output range and connect as shown in
OUTPUT RANGE SELECTION TABLE.
2. Apply Logic "0" to LOAD pins (pins 12, 13).
3. Zero and Offset Adjustments
For unipolar operation, set all digital inputs to "0" and adjust
ZERO ADJ potentiometer for zero output voltage. For bipolar
operation, set all digital inputs to "0" and adjust ZERO ADJ
potentiometer for negative full scale voltage of -5.000V.
4. GAIN ADJUSTMENT
For either unipolar or bipolar operation, set all digital inputs to
"1" and adjust GAIN ADJ potentiometer for the positive full
scale voltage of + 9.9902V (Unipolar) or + 4.9902V (Bipolar).

5K

CODING TABLES
BIPOLAR OFFSET

1 8 ) - - - - - - -_ _--'

BIPOLAR OPERATION

INPUT CODE
MSB
LSB
1111 11 1111
1110 00 0000
1100 00 0000
1000 00 0000
0100 00 0000
0010 00 0000
0000 00 0001
0000 00 0000

UNIPOLAR OPERATION

LOGIC BIAS CIRCUITS
TTL,DTL

+15VCMOS. HTL.HNIL

VTH::: 1.4V

VTH ::: VPIN 1 + lAV
VTH ::: + 7.6V

+12VTO

:o1:,}v &9:::
PIN 1
6.2V

62Kn

ZENER

+5VCMOS

'

PIN 1

T
rh

O.l/-t F

OUTPUT RANGE SELECTION
MODE
Unipolar
Bipolar

+10VCMOS
VTH ::: + S.OV

VTH ::: + 2.8V

+5V

+ 10V

3.BKH

OUTPUT RANGES
Oto +10V
±5V
+9.9902
+4.9902
+8.7500
+3.7500
+ 7.5000
+2.5000
+5.0000
0.0000
-2.5000
+2.5000
+ 1.2500
-3.7500
-4.9902
+0.0098
0.0000
-5.0000

RANGE
Oto ±10V
+5V

CONNECTION
Pin 18 open
Pin 18 to Pin 20

6.2KU

PIN 1

.---<1>---<) PI N

1

3.6K!?

TIMING DIAGRAM

=l~"o~~,~;,------,\~"o~:,,~j'r-",,"

PMOS

10KECL
VTH ::: -1.29V

VTH ::: OV

IN4148

WAD

1
1.3Ktl

~'A ~~

PIN 1

:

\L__________4-________________________

I
I~ _ _ _ _ _ _ _,
I~

,OKfl

5~sac,'yp ~
(SeWngTime)

,

3.9KU

I

+10----+--------------- --

-5V"lo -10V

VOLTAGE

OU,

NOTE DO NOT EXCEeD NEGATIVE

t'S:;;~::.)-I 1'1":;;"'~;~

5,2V

~:rx;y~ec

I

I

IProp&galion
Delay)

i

LOGIC INPUT RANGE OF DAC

2-66

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

DAC-UP10B
APPLICATIONS
INTERFACING TO A !-,PROCESSOR

APPLICATIONS
Programmable Power Supplies
Test Equipment
Process and Control
Measurement Instruments
Computer 1/0 Equipment

INTERFACING TO 8 BIT DATA BUS

(

8 BIT DATA BUS

BIT

1

,I,

4

5

6

~I

7

,

9

'0

I

INPUT
REGISTER

REG

NOTE:
The independent LOAD lines allow the DAC-UP10B to be directly interfaced with an a-bit data bus. Data for the two MSB's
is supplied and stored when LOAD 2 is activated low and returned high according to the DAC-UP10B timing requirements.
Thon LOAD 1 is activated low and the remaining eight LSB's of
data are transferred into the DAC-UP10B. When LOAD 1
returns high, the loading of a ten bit data word from an eight bit
data bus is complete.

LOAD 1

DAC·UP10B

PRELOADING 2 MSB'S TO PROVIDE SINGLE STEP OUTPUT
+5V

8 BIT DATA BUS
'J

~,

~4

<--'0
'-----13

74lS 74

3

11

I I

PRE-LOAD

BIT

lOAD 2

LOAD

5

.':~

,I J

11

INPUT
REGISTER

3

II

r4

5

6

7

8

9

'0

INPUT
REGISTER

I

J LOAD 1

ORDERING INFORMATION
NOTE:

Occasionally the analog output must change to its data value
within one data address operation. This is no problem when using the DAC-UP10B with a data bus with 10 or more data bits. It
can be accomplished from an a-bit data bus by utilizing an external latch circuit to preload the two MSB data values. After
preloading the external latch with the two MSB values, the DACUP10B LOAD inputs are activated low and the eight LSB's and
two MSB's are concurrently loaded into the DAC-UP10B in one
operation.

OPERATING
MODEL NO.

TEMP. RANGE

DAC-UP10BC

o to

ACCESSORIES
Part Number

Description

TP10K, TP20K

Trimming Potentiometers

+ lO°C

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

2-67

DAC-UP8B
8·Bit Monolithic D/A Converter
with Input Register

FEATURES
•
•
•
•
•

,

DIGIT AllNPUTS

Input register
Internal reference
Voltage output
Low cost
a-Bit resolution

~

15V

DIGITAL GND

GENERAL DESCRIPTION
The DAC-UP8BC and DAC-UP8BM are
8-bit monolithic DAC's with internal
registers. Contained in the 22-pin DIP is an
8-bit DAC, stable reference, a high-speed
output amplifier and an 8-bit input latch.
These microprocessor-compatible converters are ideal for low-cost applications.
The output voltage range is 0 to + 10V for
unipolar mode and ± 5V for bipolar.
Typical settling time is 2 microseconds for
a full-scale change. Either the internal
reference or an external reference can be
used to bias the current switching network.
The converter can function as a multiplying DAC by varying the reference input
voltage. The reference and output amplifier are short circuit protected.
The input register is controlled by an
enable line (LOAD). When low, the
registers are transparent and any change
on the digital input pins will be reflected on
the analog output. A high state level will
latch this digital information, and the data
is retained until this enable line goes low.
The data and latch enable input lines have
low input load currents.
The DAC design consists of 8 fastswitching current sources, a diffused R-2R
resistor ladder network and a control
amplifier. The diffused resistor network
gives excellent temperature tracking
resulting in a gain temperature coefficient
of 30 ppm/oC. This bipolar monolithic
fabrication results in excellent linearity and
temperature coefficient.
With an accuracy of 0.19% the device is
monotonic (no missing codes) over the entire operating temperature range. Power
supply requirements are ± 12V to ± 18V.
The operating temperature range of the
DAC-UP8BC is 0 to + 70°C while the
DAC-UP8BM operates from -55°C to
+ 125°C.

2-68

OAe
COMP

15V

MECHANICAL DIMENSIONS
INCHES (MM)
CERAMIC PACKAGE
DAC·UPSBM

PLASTIC PACKAGE
DAC-UPSBC

r=---I~~.~ MAX~

,:1

~L...1L.li....ll.-ll-~"""""""'1
0.400
(10,2)

DATEL

r

.L,,;n:-:>"-.:-:rc-:n=-:~:n:-:n::-:rt::-:lrrJ)

j~{)t1{)

~~2

0.450

DATEL
DAC·UP88C

MAX

PIN 1
IDENT

12

0

U

(10;~5)

11

0.160

~:;:;:;:;~ji

INPUT/OUTPUT CONNECTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11

FUNCTION
DIGITAL GND
BIT 8 IN (lSB)
BIT 71N
BIT 6 IN
BIT 51N
BIT 4 IN
BIT31N
BIT 2 IN
BIT 1 IN (MSB)
lOAD
NC

PIN
12
13
14
15
16
17
18
19
20
21
22

FUNCTION
REFADJ
REF OUT
REF IN
BIPOLAR OFFSET
DAC COMP
-15V
OUTPUT
+15V
SUM JUNCTION
AMP COMP
ANALOG GND

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DAC-UPS8
ABSOLUTE MAXIMUM RATINGS
Positive Supply, pin 19 .....•.•......
Negative Supply, pin 17 .........•...
Digitallnput Voltage, pins 2-10 . . . . . . ..
Reference Input, pin 14 • . . . . . . . . . • . ..
Summing Junction, pin 20 ...........

TECHNICAL NOTES
+18V
-18V
+ 18V
+ 12V
+ 12V

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ± 15V Supply, Ref. In = + 5V unless otherwise
noted.
INPUTS
Resolution . . . . . . . . . . . . . . . . . . . . . . . .
Coding, unipolar output .............
Coding, bipolar output ..............
Input Logic Level, bit ON ("1") .......
Input Logic Level, bit OFF ("0") .......
Load Input ........................

8 bits
Straight Binary
Offset Binary
+ 2.0V to + 5.5V at 10 ~
OV to + 0.8V at - 10 ~
High (" 1") = Hold Data
Low ("0") = Transfer Data
Load Pulse Width' .............••... 150 nsec. minimum
Reference Input Voltage. . . . . . . . . . . .. + 5V ± 10%
Reference Input Resistance .........• 5K
Reference Input Slew Rate ........... 25V/fLsec.

OUTPUT
Output Voltage Range, unipolar ...•...
Output Voltage Range, bipolar ........
Output Current ......•............•
Output Resistance •.•........••....•
Reference Output Voltage .......•...
Reference Output Current ...........

0 to + 10V
±5V
5 mA
5 ohms
+ 5V ± 10%
5 mA

PERFORMANCE
Linearity Error .................•... ± '12 LSB maximum
Differential Linearity Error ........... ± '12 LSB
Monotonicity .........•............ 8 Bits over operating
temperature range
Gain Error .......••.•........•..... Adjustable to zero
Zero Error .•....................... Adjustable to zero
Gain Tempco ..........•.......•... 20 ppm/oC
Zero Tempco, Unipolar ••...........• 5 ppm/oC of FS.
Offset Tempco, Bipolar ••.•••...•..•• 10 ppm/oC of FS.
Reference Tempco ................. 60 ppm/oC
Settling Time to '12 LSBz •.•...••..... 2 fLSec.
Power Supply Rejection ............. ± 1 mV/v
POWER REQUIREMENTS
Rated Power Supply Voltage ......... ± 15V de
Power Supply Voltage Range •....•... ±12to±18Vdc
Supply Current, quiescent ........... +7mA, -10mA
PHYSICAUENVIRONMENTAL
Operating Temperature Range ....•...

DoC to + 70°C (BC)
55°C to + 125°C (BM)
Storage Temperature Range ......... -65°C to +150 oC
Package Type ..................•.. 22 pin plastic (BC)
22 pin ceramic (BM)

1. It is recommended that the ± 15V power input pins both be
bypassed to ground with 0.1 Jlf ceramic capacitors. This
precaution will assure noise-free operation of the converter.
2. Both the Output (pin 18) and Reference Output (pin 13) are
short circuit protected. Output short circuit current is typically
40 rnA for the Output and 15 rnA for the Reference Output.
3. The "LOAD" control pin is a level triggered input which
causes the register to hold data with a logic "1" input state
and transfer data to the DAC with a logic "0" input.
4. A Setup Time of 200 nanoseconds minimum must be allowed for the input data before the LOAD input goes from low
to high. In addition, a 50 nanoseconds minimum Hold Time
must be allowed for the input data after the LOAD input goes
from low to high. The minimum pulse width for the LOAD input is 200 nanoseconds. The maximum update rate is determined by the output settling time. See the Timing Diagram.
5. The output settling time may be decreased somewhat by
decreasing the value of the 50 pF feedback capacitor from
the amplifier Output (pin 18) to the Summing Junction (pin
20). The minimum capacitance value is 10 pF.
6. The gain temperature coefficient of the DAC-U P8B without
the internal reference is 20 ppm/oC. By using the internal
reference, which has a tempco of 60 ppm/oC, a total tempco
of 80 ppm typical results for the converter. If greater
temperature stability is required, a more stable external
reference should be used.
7. The data inputs (Bits 1 through 8) are high impedance inputs
which give minimal logic loading. For an input low, the current that must be sinked is only 50 ~ maximum, or about
1/32 of a standard TTL load. This minimizes the loading of
the DAC-UP8B on a data bus.

CALIBRATION PROCEDURE
1. Select the desired output range and connect as shown in
OUTPUT RANGE SELECTION table.
2. Apply a logic "0" to LOAD (pin 10).
3. Zero and Offset Adjustments
For unipolar operation, set all digital inputs to "0" and adjust
ZERO ADJ for zero output voltage. For bipolar operation, set
all digital inputs to "0" and adjust ZERO ADJ for negative full
scale voltage of - 5.000V.
4. Gain Adjustment
For either unipolar or bipolar operation, set all digital inputs to
"1" and adjust FULL SCALE ADJ for the positive full scale
voltage of +9.961V (unipolar) or +4.961V (bipolar).

FOOTNOTES:

CODING TABLE

1. See Timing Diagram
2. For lOV change

OUTPUT RANGE SELECTION
RANGE
Oto +10V
+5V

CONNECTION
Pin 15 open
Pin 15 to 20

INPUT
MSB
1111
1 1 10
1100
1000
0100
0000
0000

CODE
LSB
1111
0000
0000
0000
0000
0001
0000

OUTPUT RANGES
+10V
±5V
+9.961V
+4.961V
+3.750
+8.750
+2.500
+7.500
0.000
+5.000
-2.500
+2.500
-4.961
+0.039
0.000
-5.000

o to

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

2-69

•

DAC-UPS8
CONNECTION AND CALIBRATION

22
BIT

21

LSB

!

AMP
COMP

+15V

20-t--",Su;;.UM",C'-.-~----+----J\NY---_
1M
r - - f -..:
J N

10K

Zftf.?

-15V

R
E
G
I

DATA IN

DACOUTPUT

S
T
E
R

a-BIT
DAC

5K
f--~--~-

16

15

-15V

COMP
BIPOLAR
OFFSET-

PIN 20 FOR BIPOLAR
OPEN FOR UNIPOLAR

14 I---,R.::~::.F_ _ _ _-,

MSB

LOAD

13

--+----'

REF
OUT

15K

~_ _ ~~~5yK~R~EF~~~<

NC

12

GAIN ADJ.
10K

ADJ. aOK

5K

TIMING DIAGRAM

~ 15~7~eC1

Hold

LOAD

T~ranSfer

~ 15~7~eC-1

/r---_\ /r----Hl00m~~ec, -lI II-~H~~~"ri;;;~)' IH-i lOOm7~ec I J
IJ

-----,\'

____ 50 nsec.
min.

(Setup Time)

~TA l------/r-l~,----------~\, _______________~/'~~i----------~\
I
I

.0----- (k:t#~~'-rl~~I-----'~1

"'i

+10--------1-----------I

~

VOLTAGE
OUT

2-70

3OOnsec.

I

(prO~~~~tion

:

Delayl

I
I

'----------

'~---(~;t#~~Tl~~I------t

"'1

I
I
I

I
I

~

I

,--

I

lSOnsec.

I

I

(Propagation

I

Delayl

typo

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DAC-UPSB
APPLICATIONS

INTERFACING T08 BIT DATA BUS

DAC-UPBB
BH B (lSB)
Bit 7

R

Bit6

8-BIT
DATA
BUS

E
G

Bit 5

I
S
T

Bil4
Bit 3

E

Bit 2

-T--------'

Bit 1 (MSB)

R

,
LOAD

APPLICATIONS

ADDRESS

STROBE

Process and Control
Measuring Instruments
Test Equipment
Programmable Power Supplies
Computer I/O Equipment

This illustrates the connection for
loading parallel data into the input
register. The register circuit is a static
latch and is controlled by the LOAD, active low_ When the data is stable on the
data inputs (bits 1-8), it can be transferred
on the positive edge of the LOAD pulse.
The voltage levels on the data bus should
be stable for at least 200 nsec before
LOAD goes HI. The minimum pulse width
of the iJ5At5 command is 200 nsec_

ORDERING INFORMATION
MODEL NO.
DAC-UPBBC
DAC-UPBBM

OPERATING
TEMP. RANGE

o to 70°C
- 55 to 125°C

CASE
Plastic
Ceramic

ACCESSORIES
Part Number

Description

TP10K

Trimming Potentiomelers

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

2-71

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

SAMPLE-AND-HOLD
AMPLIFIERS

SAMPLE/HOLD AMPLIFIERS
MODEL
SHM-91MC
SHM-91MM
SHM-45MC
SHM-45MM
SHM-4860MC
SHM-4860MM

LINEARITY
0.003%
0.01%
0.01%

APERTURE
DELAY

INPUT
RANGE

HOLD-MODE
DROOP

BANDWIDTH

PACKAGE

2~

15 ns

±10V

5 ~V/~s

1 MHz

24-pin DIP
Hybrid

-5510 +125

16MHz

24-pin DIP
Hybrid

010 +70
-5510 +125

16MHz

24-pin DIP
Hybrid

o to +70

5 MHz

2 x 2 x 0.375in
(50x50xl0mm)
Module

2MHz

14-pin DIP
Monolithic

2 MHz

14-pin DIP
Monolithic

200 ns
200 ns

6 ns
6 ns

±5,±10V
±10V

0.5 ~V/~s
0.5 ~V/~s

SHM-5

0.01%

350 ns

20 ns

±10V

SHM-20C

0.01%

1 ~s

30 ns

±10V

0.08

0.01%

5~s

50 ns

±10V

50

0.01%

6~s

200 ns

±10V

0.2 mVlms

SHM-IC-1
SHM-IC-1M
SHM-LM-2
SHM-6MC
SHM-6MM
SHM-9MC
SHM-9MM
SHM-UH3
SHM-HUMC
SHM-HUMM
SHM-7MC
SHM-40MC
SHM-40MM
SHM-360
SHM-361
SHM-30C

TEMPERATURE
RANGE(°C)

ACQUISITION
TIME

20 ~V/~s

~V/~s

~Vlms

1 MHz

8-pin TO-99

010 +70

-55 to + 125

PAGE
3-37
3-15
3-19

010 +70

3-22

oto +70
o to +70

3-3
3-43

-5510+125

Monolithic

oto +70

3-47
3-24

0.02%

2~s

20 ns

±10V

10~V/~s

5 MHz

32-pin DIP
Hybrid

010 +70
-55 to +100

0.01%

6~s

200 ns

±11.5V

0.2 mVlms

4MHz

16-pin DIP
Hybrid

010 +70
-55 to +125

3-32

0.05%

30 ns

5 ns

±5V

50

~V/~s

45 MHz

2 x 2 x 0.375in
(50x50xl0 mm)
Module

oto +70

3-49

0.01%

25 ns

6 ns

±2.5V

50

~V/~s

50 MHz

24-pin DIP
Hybrid

-55 to +100

0.01%

40 ns

3 ns

±5V,±2.5V

40 MHz

24-pin DIP
Hybrid

010 +70

~V/~s

40 MHz

24-pin DIP
Hybrid

mV/~s

25 MHz
55 MHz

24-pin DIP
Monolithic

-20 to +75

4'.5 MHz

14-pin DIP
Monolithic

010 +70

0.01%

40 ns

0.15%

12nS

0.01%

3 ns

20 ns

500 ns

20 ns

100 ~V/~s

±2.5V

100

±3V

10

±10V

0.01 ~V/~s

010 +70

oto +70
-55 to +125

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

3-41
3-28
3-11
3-7

3-1

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

SHM·20
High Speed, 0.010/0
Monolithic Sample/Hold
FEATURES
•
•
•
•
•
•

Internal hold capacitor
1 Microsecond acquisition time
1 Nanosecond aperture uncertainty
0.01 % Accuracy
0.08 MicroV/Microsecond droop rate
Differential inputs

GENERAL DESCRIPTION
DATEL's SHM-20 is a low·cost, complete
monolithic sample/hold amplifier which includes an internal 100 pF MaS hold
capacitor. Primarily designed for high
speed analog signal processing applications, the SHM-20 features a typical acquisition time of 1.0 microsecond for a 10V input step to 0.01%. Aperture uncertainty is
typically 1 nanosecond and droop rate is
as low as 0.08!,V/microsecond.

•

The SHM-20 consists of an input transconductance amplifier, a low leakage analog
switch, an output integrating amplifier and
a 100 pF MaS hold capacitor. Charge injection on the hold capacitor is constant
over the entire input/output voltage range.
The pedestal voltage resulting from this
charge injection can be adjusted to zero by
using the offset adjust inputs. For improved droop rate, an external hold
capacitor may be added at the expense of
acquisition time.
Other important features of the SHM-20
include a 30 nanosecond aperture delay
time, 1 mV pedestal error, a minimum dc
gain of 106VN and fully differential inputs
with a ± 10V input voltage range. Maximum input offset voltage is as low as 0.5
mV with a maximum input offset voltage
drift as low as 15 !'v/oC.
Its low cost and high performance make
the SHM-20 an excellent choice for innumerable applications including, precision data acquisition systems, deglitching
circuits, auto-zero circuits, data distribution systems and peak amplitude detectors. Power requirement is ± 15V dc.
The SHM-20 is available in two models for
operation over the commercial, O°C to
+ 70°C, and military, - 55°C to + 125°C
temperature ranges. Both models are
packaged in a 14-pin ceramic DIP.

GND

-Vs

MECHANICAL DIMENSIONS
INCHES (MM) MAX.

"I

I-r;~

If:::,::::!:I
.-.------------.

EXT
HOLD

REF
GND

INPUT/OUTPUT CONNECTIONS

.,.
1
2
3

•
5
6
7

•
9

0.100

(0,6)

(2,54)

FUNCTION
-INPUT
+lNPUT
OFFSET ADJUST
OFFSET ADJUST

-Vs
REFERENCE GROUND
OUTPUT
INTEGRATOR COMPENSATION

+Vs

10

NO CONNECTION

11

EXTERNAL HOLD CAPACITOR

12
13

NO CONNECTION

,.
0.023

INT
COMP

SUPPLY VOLTAGE GROUND
SIH CONTROL

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-3

SHM-20
ABSOLUTE MAXIMUM RATINGS, BOTH MODELS
Voltage between Supply Pins (Pins 9, 5) ..••••••••..•••....
Differential Input Voltage ....•..........................
Digitallnput Voltage, Pin 14 •..••.•••••....••.•••••...••
Output Current, Continuous' .••••.•.•..•••.......••••...

SHM·20C

SHM·20M

40V
±24V

+BV to -15V
±20 rnA

FUNCTIONAL SPECIFICATIONS, BOTH MODELS
+ 25°C, ± 15V dc, using internal hold capacitor, unless otherwise noted.

Typical at

PHYSICAUENVIRONMENTAL
Operating Temp.
Ranges,
SHM·20C ••...
SHM·20M ••.•
Storage Temp.
Range .....•.
Package Type

..

O°C to + 70°C
-55°C to + 125°C
-65°C to + 150°C
14 Pin, Ceramic DIP

FOOTNOTES:

ANALOG INPUTS
Input Voltage Range,' minimum ...••••....•.•••••......•
Input Impedance, minimum ..•••.•••......••....••..••.
Input Capacitance, maximum .......................... .
Input Offset Voltage, maximum .....•••....••..••.......
Input Offset Voltage Drift, maximum •......•••.••.•..•••.
Input Bias Current, maximum •••.................•......
Input Offset Current, maximum ..............•.••.......

SHM·20C

SHM·20M

±10V
1 Mil
3 pF

1 mV
20 ",V/oC

300 nA
300 nA

0.5 mV
15 ",V/oC
200 nA
100 nA

DIGITAL INPUTS'
Logic Level High, Vin ("1"), minimum, Hold Mode ......... .
Logic Level Low, Vin ("0"), maximum, Sample Mode ....... .
High Level Input Current, maximum ..•••.....•••••......•
Low Level Input Current, maximum .....••.•.............

2.0V
O.BV
0.1 ",A
10~

1. Internal power dissipation may limit output
current below + 20 mAo
2. Over full operating temperature range.
3. Cannot tolerate even a momentary short ,circuit
to ground or either supply.
4. Voltage gain = + 1
5. Voltage gain = + 1, load resistance = 1 kG,
load capacitance = 50 pF, output voltage =
100 mV pop.
6. Input voltage = OV. digital input voltage = 3.5V
7. Output voltage = 10V step.
8. A power supply voltage as low as ± 12V may be
used. However, this will cause some degradation in performance.

TECHNICAL NOTES

OUTPUT
Output Voltage Range', minimum ...................... .
Output Current', minimum ••...............•...........
Output Impedance, Hold Mode' ..•.....•................

±10V

±10mA
1 Il

PERFORMANCE
Accuracy .......•...•....•.•........................
0.01%
DC Gain, minimum ................................... . 3xl0'VN
106 VN
0.5 x 1O- 4% FSR
Gain Accuracy' •.......••......•...•......••.........
Gain Error Tempco ...••.•......•••.....••.............
±0.6 ppm/oC
Gain Bandwidth ProductS ..•...........................
2 MHz
Hold Mode Feedthrough, 10V p.p, 100 kHz' ...••.......•...
2 mV
Droop Rate ......•••......••.....................•...
O.OB ",VI!"Sec.
17 ",Vlp.sec.
Droop Rate' .....•.•••....•.....•.....•..•........... 1.2",V/p.sec.
Charge Transfer" •....................................
0.1 pc
Pedestal Error ...........•....................•.....•.
1 mV
Total Output NOise, DC to 10 MHz, maximum •...........•..
200 p.V RMS
Power Supply Rejection Ratio, minimum + VS ............ .
BO dB
-VS ............. .
65 dB
Pedestal Error ......•...•....••...•......•.........••.
1 mV
DYNAMIC CHARACTERISTICS
Acquisition Time, 10V to 0.1% ...•••.....••........•....
10VtoO.Ol% ........................ .
Aperture Delay Time ..........................•.......
Aperture Uncertainty Time ............................ .
Aperture Time ..••..••..............•................
Hold Mode Settling Time, 0.01 %' ......•.......•........•
RiseTime ..•..•..............••......••........•....
Overshoot. ........•...•.....•.••................•.•.
SiewRate 7 • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • •

O.B !"Sec.

1.0 ",sec.
30 nsec.
1 nsec.
25 nsec.
lB5 nsec.
100 nsec.
15%

1. A printed circuit board with ground
plane is recommended for best performance. The supply pins (Pins 5,9)
should be bypassed to ground with a
0.01 to 0.1 "F ceramic capacitor as
close to the pins as possible.
2. If an external hold capacitor (C H) is used, 8 then a noise bandwidth capacitor
with a value of 0.1 CH (10% of the value
of the external hold capacitor) should be
connected from Pin 8 to ground. Exact
value and type are not critical.
3. The Hold Capacitor (C H) should have
high insulation resistance and low
dielectric absorption to minimize droop
error. For operating temperatures up to
70 D C, polystyrene dielectric isa good
choice. Any PC connections to the hold
capacitor terminal (Pin 11) should be
kept short and "guarded" by the
ground plane to avoid errors due to drift
currents from nearby signal lines or
power supply voltages.

45 Vlp.sec.

POWER REQUIREMENTS.
Positive Supply, Pin 9 ..••..............•..........•...
Negative Supply, Pin 5. . . . . . . • • . . . . . . . . . . . . . . . . . . . . . . . .

3-4

+ 15V ± 0.5V at 11 rnA
-15V ± 0.5V at -11 rnA

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339·30001TLX 174388/FAX (508) 339-6356

SHM-20
TYPICAL PERFORMANCE AND DEFINITIONS
OPEN LOOP GAIN AND PHASE RESPONSE
120

100

80

co

"0

z·
:;;:

"

""'"""'- ""'-

"-

"'- ......... "-

60

45

~

""'- ""'Gain .....

40
IC H

I
I
~
10

JJ
IC H

= 1100 pF) ""'-

20

100

DRIFT CURRENT
VS. TEMPERATURE

1K

100K

135

\
\

'l

"
0

(f)

\

" ""'- 1--. ""'-

1000.

w
w
a:
w

W

= 100 pF) '\

""'-Gain

10K

90

.........

C H = 100 pF, INTERNAL

(f)

100.

«0.

'"

I
0..

180

10.

\
1M

,,

10M

•

/
/

to

/

/

/

SAMPLE AND HOLD DEFINITIONS:

•••••

"

ACQUISITION TIME: The time required, after the sample command is given, for the hold capacitor to charge to a full-scale
voltage change and then remain within a specified error band
around the final value.

-25

0 +25 +50 + 75 + 100 + 125
TEMPERATURE, ·C

APERTURE TIME: The time required for the Sample & Hold
switch to open, independent of delays through the switch driver
and input amplifier circuitry.

TYPICAL SAMPLE AND HOLD PERFORMANCE
AS FUNCTION OF HOLDING CAPACITOR

APERTURE DELAY TIME: The time elapsed from the hold
command to the actual opening of the sampling switch.
APERTURE UNCERTAINTY TIME: The time variation, or time
jitter, in the opening of the sampling switch; also the variation in
aperture delay time from sample to sample.

I

I

VOLTAGE DROOP

CHARGE TRANSFER: The small charge transferred to the
holding capacitor from the inter-electrode capacitance of the
switch when the unit is switched to the hold mode. This is
caused by the switch control voltage change coupling through
switch capacitance to the hold capacitor. Also called charge
dumping or charge injection.

1.0

1'.----'\;I--DU~~Lrl~gCfs~~DE,

MILLISECONDS
0.5 f--'<----1--'1.---i----i

0.1

DRIFT CURRENT: The net leakage current from the hold
capacitor during hold mode.

.05

HOLD MODE DROOP: The output voltage change per unit time
with the sampling switch open. Commonly expressed in
V/seconds or IN/microseconds

.01

f----~----'\;I-----I

100

PEDESTAL ERROR: For a sample-hold, the change in output
voltage from the sample-mode to the hold-mode, with constant
input voltage. This error is caused by the sampling switch
transferring charge onto the hold capacitor as it opens.

1000

10K

100K

C H VALUE, PICOFARADS

PEDESTAL VS. INPUT VOLTAGE

>

.sw

(!)

1.0

CH=100pF

0.1

CH = 1000 PF

~
CJ
0

>
...J
~

(fJ

w
w

CH = .01

0.01

~F

0

"-10

8

6

4

2

0

2

4

6

8

10

DC INPUT (VOLTS)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

3-5

SHM-20
APPLICATION
UNITY GAIN NON-INVERTING
S/H AMPLIFIER
-t5V

+15V

10k

DATA
OUTPUTS

+ VIN

0----\.2]
I

I
I
I
1

(LSB),

O.lCH

SIGNAL
GND

POWER
GND
SIH CONTROL AND
STAAT CONVERT

L

HOLD COMMAND - - - - - - - '

S/H OUTPUT

__....JI

START CONVERT - - - - - - '

L

E.O.C. - - - - - - - - - - - - - '

The above diagram shows the SHM-20 connected as a unity
gain non-inverting StH amplifier, with DATEL's ADC-HZ 12-bit
successive approximation AID converter. The SHM-20's
pedestal error is adjustable to zero, by the offset adjust trim pot,
allowing a 12-bit accurate output from the ADC-HZ.
If an external hold capacitor (C H) is required, it may be connected as shown between Pins 11 and 7. If an external hold

capacitor is used, a capacitor, 0.1 CH (10% of the value of the
external hold capacitor) is then required from Pin 8 to ground to
reduce output noise in hold mode. The RC network on Pin 14
delays the S/H Control/Start Convert pulse to allow the sample
to hold transient time to settle before a conversion begins. See
Timing Diagram.

ORDERING INFORMATION

3-6

MODEL NO.

OPERATING
TEMP. RANGE

SHM-20C
SHM-20M

O°C to + 70°C
- 55°C to + 125°C

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

SHM-360, SHM-361
Video Speed
Sample-Holds
FEATURES
• 8 nSec. and 12 nSec. acquisition
times
• Sampling frequencies of 18 MHz and
35 MHz
• Input amplifier bandwidths of 25 MHz
and 55 MHz

12 ANALOG GROUND

11

GAIN OF 2 AMP OUTPUT 1 4 1 ) - - - - - ,

• Linearity 0.08%
• Low power

SlI-IOUTPUT

16

L-_ _-{g

GAIN OF 2 AMP INPUT 17

8

DlGITAlGROUND

7

CLKOJTPUT

6

ClKOOTPUT

5

ANAlOO· Vs

4

-2V REF. OUTPUT

3

EXTE~AlR

ANALOG GROUND

•

ANAlOO-Vs

GENERAL DESCRIPTION
The SHM-360 and SHM-361 are two very
high speed sample/hold devices featuring
separate wideband input amplifiers, and
reference voltage and clock outputs. The two
devices are pin-for-pin identical.
Both devices offer very fast S/H capabilities
for AiD's such as the ADC-300 and ADC-303,
but can be used in any application demanding very fast acquisition times.
The input amplifier has a - 3 dB bandwidth
at 25 MHz or 55 MHz depending on the
device used and both have offset adjustment controls.
An internal amplifier may be used to buffer
a - 2V dc reference voltage output for an
AiD converter.
The single or 2-phase clock inputs are available as buffered outputs for use as high
speed video analog-to-digital converter
clock inputs.

L-_ _ _-(2 -2VREEINPUT

}-~----{1

DIGITAl-Vs

APPLICATIONS
•
•
•
•
•
•
•
•

High speed data acquisition
Radar pulse analysis
TV video encoding
Infrared imaging
Transient analysis
Medical electronics
Fluid flow analysis
Sonar systems

ORDERING INFORMATION
MODEL NO.

OPERATING
TEMPERATURE
RANGE

SHM-360
SHM-361

-20°C to + 75°C
-20°C to +75°C

INPUT/OUTPUT CONNECTIONS

MECHANICAL DIMENSIONS

PIN FUNCTION
1 DIGITAL -Vs (-5V)

J

(3.0] MIN

o.o:w

,0.51
!O.OOS

0.11S

24 DIGITAL GROUND

2 REF INPUT (-2V)

23 CLOCK INPUT

3 EXTERNAL R

22 CLOCK INPUT

4

~
Llj
~
110.51
MIN
o.~~~~~.21 ~ 1_

PIN FUNCTION

REF. OUTPUT (-2V)

21

ANALOG -Vs (-5V)

20 DIGITAL +Vs (+5V)

CLOCK OUTPUT

19

7 CLOCK OUTPUT

CLOCK REF OUTPUT
OFFSET ADJUST

18 ANALOG -Vs (-5Vj

DIGITAL GROUND

17

ANALOG -Vs (-5V)

16 ANALOG GROUND

ANALOG +Vs (+5V)

15 ANALOG +Vs (+5V)

11

S/H OUTPUT

14 GAIN OF 2 AMP OUTPUT

12

ANALOG GROUND

13

10

GAIN OF 2 AMP. INPUT

S/H INPUT

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

3-7

SHM-360, SHM-361

ABSOLUTE MAXIMUM RATINGS
Operating Voltage $Vs . . . . . . • . . . . . .
-VS ............
Operating Temperature .. . . . . . . . . ..
Storage Temperature . • . . . . . . . . . . ..
Power Dissipation ....•....•......

+5.5
-6.0V
200C to + 750C
-55OC to + 1500C
1.2 Watts

FUNCTIONAL SPECIFICATIONS, SHM-360, SHM-361
lYplcal at +25°C, VS = ±5V dc unless otherwise stated.
INPUTS

MIN.

TYP.

MAX.

Analo~

-3.0
60
-0.9

±3.0
100
-0.80
-1.60

+3.0

V

-1.5

V
V

Input Voltage Range ........
Input mpedance .................
Digital Input VH ...........•......
VL

..................

-

-

UNIT
KQ

OUTPUTS
Analog Range ...................
Output Impedance •..............
Clock (Reference) ................
Reference Buffer Range ...........
Clock - Amplitude .•.............
- Low Level ............•..
- Rise Time (Tr) .....•.•....
- Fall Time (Tf) •...•........

-

-3.0

-1.3

0
0.2
-1.2

--

POWER

+3.0

40

20
-1.2
-2.0
0.3
-1.1
7
5

-1.1
-2.3
0.4
11.9
10
8

........................

MIN.

TYP.

-

48

5.0
-5.0
60

78

48

60

78

100

125

-

80

-

PERFORMANCE
SAMPLE/HOLD
Acquisition Time .................
Settling Time ....•...•...........
Linearity ..............••........
Droop ..........................
Sampling Rate .••................
Gain ...........................
Full Power Bandwidth
(-3 dB, VIN = 2V p-p) ............
Hold Feedthrough ................
Sample-to-hold Transient ...........
DC Offset .......................
Dlff. Gain .....•..................
Dlff. Phase .....•................
Input Bias Current .•..............

-40

MAX.

-

-

MIN.

TYP.

MAX.

-

5.0
-5.0
35
35
75
-70

45

-

25
25
60

-

TYP.

MAX.

-5

8
25
0.08
2

12

0.99

1.00

-

12
-50
10
±15
0.5
0.5
15

-

-

-

-

45
98

-

UNIT

V
V
mA
mA
mA
dB

SHM-360

SHM-361
MIN.

V
V
V
V
nSec.
nSec.

SHM-360

SHM-361

Supply Voltage +Vs ...............
-Vs .•.............
Supply Current +Is ...............
-Is (No Ref) ....•...
-Is (with Ref) .......
P.S.R_R.

V
Q

-

0.15
20
35
1.01

-40
50
±100
1.0
1.0
30

MIN.

-

-2

TYP.

MAX.

12
36
0.08
2

20

0.15

0.99

1.0

10
18
1.01

-

6
-50
10
±15
0.5
0.5
9

-40
50
±100
1:0
1.0
18

--

-

-

-

UNIT
nSec.
nSec.
%
mV/l'S
MHz
MHz
dB
mV
mV
%
Deg

f'A

GAINOF2AMP
Bandwidth (-3db, VIN = tV p-p) .....
Input Voltage Range ...............
Imput Impedance .............•...
Output Impedance ................
Voltage Gain .•...................
Input Bias Current ................

45
-1.3
10

55

-

+0.8

-

15
-1.3
10

-

-10

+0.8

MHz

V

-

6.9
10

f'A

34
28

36
24

38
26

45
33

nSec.
nSec.

1.1
10
10

0.9

1.0
5
2

1.1
10
10

f'QA

5.1

-

10
6.9
20

20
14

28
22

0.9

1.0
5
2

-

5.1

25
20
4
6.0
5

20
4
6.0
9

-

KQ
Q

dB

CLOCK OUTPUT
Clock Delay T1 ••••••••.••.••.••.•
Clock Delay T2 ..•................

-2V REF AMP
Voltage Gain Ratio ....•.......•...
Input Bias Current ....••..........
Output Impedance ....•...........

3-8

-

-

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

SHM-360, SHM-361

TIMING DIAGRAM (NOT DRAWN TO SCALE)

,

......•,
,

Tset.. '

,,
,

1-

SAMPLE HOLD OUTPUT

- --

~

,

Tset = SETTLING TIME
T3 = ACQU ISITION TIME

l::J. V = 1.2V

.... T31~
CLKINPUT

I

I

1

\

,

\

1 ---.,~Ir-:------t,r----,
,~~

i

11 = CLOCK DELAY
T2 = CLOCK DELAY

t1
1<11...
. - ._ __ .....

-0.8V T
CLKOUTPUT

1

I:

~

,,

I

,

I

-0. 95V-t---t-:':t--+-----I:-t'-------t------;J-----

90%~:'

CLKOUTPUT

t.~~
-1. 1V

t

~,

'. _..:.R_-" _____,~L __

10%

T F (MAX) = 8 nSec.
T R (MAX) = 10 nSec.

TIMING DIAGRAM NOTES
1. The hold to sample transition occurs 6 nSecs. for the
SHM-361 and 12 nSecs. for the SHM-360, after positive
edge of the clock input.
2. Acquisition times for the two devices are 12 nSecs. (max.)
forthe SHM-361 and 20 nSecs. (max.) for the SHM-360 for
a change of 1.2V at the analog input.

3. Sample-to-hold transient is 50 mV (max.) for the SHM-361
and 30 mV (max.) for the SHM-360.
4. To achieve the correct timing the CLOCK and CLOCK outputs are delayed. For the SHM-361, the delay will be between 20 nSecs. and 34 nSecs. and forthe SHM-360 it will
be between 36 nSecs. and 45 nSecs.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

3-9

SHM-360, SHM-361

CONNECTION AND APPLICATION

10

DIGITAL
OUTPUT
(Eel)

VIN

ADC-300
6dBAMP
OFFSET
OBJUST

5

-5V

NOTES:

*1
*2
*3
*4

3-10

R is a ringing preventing resistor. Select between 10 to 50Q according to pattern length.
Pulldown R for Vref'
Rl = 4.3kQ.
R1 = 2kQ, R2 = 1kQ, R3 = 2kQ.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

SHM-40
Video Speed
Sample-Hold
FEATURES
• 40 nSec acquisition time
• Dual outputs
• 10 pSec aperture uncertainty
• 40 MHz bandwidth
• 30 mA Output Current

GENERAL DESCRIPTION
DATEl's SHM-40 is an ultra-fast sample
and hold designed for high speed analog
signal processing applications. The
SHM-40 acquires a 2V input change to
0.1% in only 40 nsec and aperture uncertainty time is less than 10 psec.
Sample-mode bandwidth is 40 MHz.
The SHM-40 is a complete Sample-Hold,
containing an input buffer amplifier, a
precision 53 pF MaS holding capacitor,
and two output buffer amplifiers. The
sampling switch is controlled by a series
10,000 complementary ECl input. An
ECl differential line driver can be conveniently used for the sample control
inputs.

130

co~:~~

SAMPLE

,

SAMPLE 3

Other features of the SHM-40 include a
±2.5V input voltage range, a fixed gain
of +0.995, and a maximum gain temperature coefficient of 33 ppm/o C. The
device has two outputs, each with a ±2.5V
output voltage swing at 30 mA and an
output impedance of only 13Q. The outputs may be tied together for decreased
output impedance and increased output
current. The SHM-40 is functionally laser
trimmed at the factory for offset, sample
to hold offset, and gain errors, and is
designed to be used without external
adjustment circuits.
The SHM-40 is an ideal choice for use in
ultra-high speed data acquisition systems,
and video processing applications, and
with its dual outputs, it is especially useful
in two stage flash converter systems.
Power requirement is ±15Vdc at 60 mAo
Two models are available for operation
over the O°C to 70°C and -55°C to
+125°C temperature ranges. All models
are cased in a 24-pin, hermetically
sealed, ceramic package.

130

21}-----'

MECHANICAL DIMENSIONS
INCHES (MM)
~O,ID) MAX ,

1---

(20.3)

-L I
o '50M'N
13,8)

_I

r

lr

_~

-.--

I

I-'-O.'C:'90c:-'c(4.""9)cc
Mcc
AX

0010 1I 0018

I

KOVAR

'3,

"'

~ FTEg~NTc~

VIEW

1

1200

J

11 SPACES
AT0100
fA 12.5)

BOTTOM
,

PIN 1

t

:

L.1-_"_'___'_4_'-,

_ _ _0

1.31~3~AX

~~

INPUT/OUTPUT CONNECTIONS
PIN
1
2
3
4
5
6
7
8
9
10
11
12

FUNCTION
SAMPLE
N.C.
SAMPLE
N.C.
N.C.
N.C.
N.C.
N.C.
-15VDC
N.C.
POWER COM.
POWER COM.

PIN
13
14
15
16
17
18
19
20
21
22
23
24

FUNCTION
POWER COM.
ANALOG COM.
POWER COM.
OUTPUT 2
ANALOG COM.
OUTPUT 1
+ 15VDC
ANALOG COM.
INPUT COM.
ANALOG INPUT
N.C.
N.C.

NOTE: PINS HAVE 0.025 INCH STANDOFF FROM CASE, ±O.Ol"

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

3-11

SHM-40
FUNCTIONAL SPECIFICATIONS (continued)

ABSOLUTE MAXIMUM RATINGS
Positive Supply ............... .
Negative Supply .............. .
Digital Input Voltage .......... .
Analog Input Voltage .......... .

-0.5V dc to +18V dc
+0.5V dc to -18V dc
-5.0V dc to +5.0V dc
-5.0V dc to +5.0V dc

FUNCTIONAL SPECIFICATIONS
The following specifications apply over the full operating
temperature range and power supply range unless otherwise
specified.

DESCRIPTION
INPUTS
I n put Voltage Range ...
Input Bias Current .....
Input Impedance ......
Max Source
ImpedanceCD .........
Sample&Ontrol
Inputs 2 •••••••••••••
OUTPUTS
Output Voltage
Range ...............
Output Current0 ......
Output Impedance0 ...

MIN.ITYPICAL MAX. UNITS
±2.5

-

-

-

±30
1M

±100

Vdc
/lA

-

Q

50

Q

-

-

100K

-

-

±2.5
±30
8

±60
13

-

Vdc
mA

20

Q

.2% %of FS
+1.0
+20 ppm/oC
±50

mV

±50

mV

±100

/lV/oC

-

-

±714
±278

/lV/oC
/lV/oC

-

-

-66

-60

dB

-

-

-

-

20
500

100
2500

/lV//lS
/lV//lS

DYNAMIC CHARACTERISTICS
Acquisition Time
2V to 0.1 & ...........
2V to 1.0% ...........
4V to 0.1% ...........
4V to 1.0% ...........
Aperture Delay Time ...
Aperture Uncertainty
Time ................
Hold Mode Settling
Time ................
Sample Mode
Bandwidth, -3dB ....
25

3·12

PHYSICAL/ENVIRONMENTAL
Thermal Resistance
Junction to Case ......
Case to Ambient .......
Operating Temp.
Range
SHM-40MC ........
0°
SHM-40MM
Storage Temp. ........
Package Type Pins ....

-55 0

.030
.035

-

-

°C/mW
°C/mW

+25°

+70°

°C

+25 0

+125 0

°C

-65°
°C
+25° +150°
24 Pin, hermetically sealed,
ceramic 0.010 x 0.018 in. kovar

FOOTNOTES:
1. Should be purely resistive. See technical note 3.

PERFORMANCE
.1%
Linearity ..............
Gain ................. +0.980 +0.993
-20
Gain Tempco ......... -60
Sample to Hold
±15
Offset Error ..........
Sample Mode Offset
Voltage ..............
±10
Sample to Hold Offset
±25
Volt Drift. ............
Sample Mode Offset
Volt Drift. ............
±143
SHM-40MC
SHM-40MM ........
±56
Hold Mode
Feedthrough .........
Hold Mode Droop .....
at25°C ............
at 125°C ...........

DESCRIPTION
MIN. TYPICAL MAX. UNITS
POWER SUPPLY REQUIREMENTS
Supply Voltage
±15
±15.5
Range ±V ............ ±14.5
Vdc
Power Supply
Rej. Ratio ............ -20
-30
dB
Current Drain
mA
±15V dc .............
60
80
mA
-15V dc .............
60
80
1.8
2.4
Watts
Power Dissipation .....

-

2. Input logic voltage levels are Yin "0" = -1.5V to -1.4V,
and Yin "1" = -0.7V to -1.05V. These are differential ECl
10,000.
3. Specified for each output. both outputs may be tied
together for decreased output impedance and increased
output current.

TECHNICAL NOTES
1. The use of good high frequency circuit board layout
techniques is required for rated performance. The power
common (Pins 11. 12, 13 and 15), analog common (Pins
14.17 and 20), and input common (Pin 21) pins are not
connected internally and therefore must be connected
externally as directly as possible through a low inductance, low resistance path. The extensive use of a
ground plane for all common connections is highly
recommended.
2. Although they are internally bypassed with .033 /IF capacitors the supply pins (Pins 19, 9) should be externally
bypassed with 0.1 /IF ceramic chip capaCitors mounted
as close to the supply pins as possible.
3. The SHM-40 inputs and outputs are sensitive to unusual
loading or long lines. The analog input must be nonreactive so that leads should be short and purely resistive. Also, the complementary ECl driver should be as
close as possible to pins 1 and 3 to minimize lead lengths
to these pins.

-

40
25
50
35

3

-

nS
nS
nS
nS
nS

10

-

pS

20

40

nS

5. The SHM-40 has no significant acquisition time drift
with temperature.

40

-

MHz

6. A positive pulse on Pin 3 and a negative pulse on Pin 1
selects the HOLD mode.

4. The maximum, differential, digital input voltage is ±5V.
For example, if pin 3 is at a potential of -5V, pin1 may
not exceed OV.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

SHM-40
6. Hold-Mode Droop
The output voltage change per unit of time while in the
hold mode.
7. Bandwidth
The frequency at which the gain is down 3 dB from its
dc value. It's measured in the sample-mode with a smallsignal sine wave.

BASIC GROUND PLANE LAYOUT

I 12

•

13 I

I

I

CD

CD

I

I

BOTTOM
VIEW

CJ
I

I

CD

I
I

I

CD1

DOT ON TOP
REFERENCES
PIN 1

24 I

SAMPLE-HOLD DEFINITIONS

1. Acquisition Time
Time required, after receipt of the sample command, for
the hold capacitor to charge to a specified voltage
change and remain within a specified error band such
as 0.1%.

ACQUISITION ACCURACY VS ACQUISITION TIME

2. Aperture Delay Time (effective)
The time elapsed from the hold command to the opening
of the sampling switch minus the delay from the analog
input to the sample switch.

~

,

v

3. Aperture Uncertainty Time
Time variation, or jitter, in the opening of the sampling
switch.
4. Aperture Uncertainty Error
An amplitude uncertainty in the held value due to the
change in the analog input signal during the aperture
uncertainty time. This error is the product of the rate of
change of the input signal and the aperture uncertainty
time.
5. Hold-Mode Settling Time
The time from the hold command transition until the
output of the Sample-Hold has settled within the specified error band (0.1%). It includes aperture delay time.

j
4V

1\

\

1.0%

\

>-

~

a::
u
u

::J

f-f- f-f-

INPUT VOLTAGE STEP

.....

"- I.....

0.3%

---......------J:!.J

GENERAL DESCRIPTION
DATEL's SHM-45 is a high-speed, high
accuracy sample-hold designed for precision, high-speed analog signal processing
applications. Manufactured with modern,
high quality hybrid technology, the SHM-45
features excellent dynamic specifications
including a maximum acquisition time of
only 200 nsec for a 10V step to 0.01%.
Sample-to-hold settling time to 0.01%
accuracy is 100 nsec maximum with an
aperture uncertainty of ±50 psec.

--.-+--+----1:12 - 15V

SYSTEM
GROUND

The SHM-45 is a complete sample-hold circuit, containing a precision MaS hold capacitor and a MOSFET switching configuration
which results in faster switching and better
feedthrough attenuation. Additionally, a FET
input amplifier design allows faster acquisition and settling times while maintaining a
considerably low droop rate.
Other important features include a minimum
output voltage range of ± 10.25V, an aperture delay time of 6 nsec, a typical droop rate
of ±0.5I'V/JLSec, and a sample-to-hold offset
error as low as ±2.5mV. Sample-to-hold offset is constant regardless of the input/output
voltage level. Output slew rate is typically
300V/JLSec and small signal bandwidth ( - 3
dB) is 16 MHz.

MECHANICAL DIMENSIONS
INCHES (MM)

I

L....0800 MAX - J
1(20,31
I

...L I
o 150MIN
13.81

rI

1

----,---

0 OlD

I

The SHM-45 has a TTL-compatible HOLD
digital control input.

l(

PIN 1

t

0018
13 I

I
I
I
I
I
I
I
I
I
I

DOT ON TOP
REFERENCES

0.190 (4.9) MAX

KOVAR

112

Applications for the SHM-45 include highspeed data acquisition and data distribution
systems, peak measurement systems, fast
fourier analysis, transient recorders and
analog signal delay and storage.
Power requirements ±15V dc and +5V dc
with a maximum power consumption of
875 mW. The SHM-45 is available in two
models for operation over the commercial
OOC to +70 oC and military -55°C to
+125°C operating temperature ranges.
All models are cased in a 24-pin,
hermetically-sealed, ceramic package.

•

OUTPUT

I
I
I
I
BonOM I
VIEW
I
I
I
I
I
24 I
11

1

'200

J01~'"'" "

11 SPACES
AT 0 100

EA 12,51

33.3

INPUT/OUTPUT CONNECTIONS
PIN
1
2
3
4
5
6
7
8

9
10
11
12

FUNCTION
FUNCTION
PIN
13 INPUT A
OUTPUT
14 RANGE
NIC
15 GROUNO
NIC
16 NIC
NIC
17 NIC
NIC
18 NIC
NIC
19 NIC
NIC
20 N/C
N/C
21 GROUND
+5V SUPPLY
22 -15V SUPPLY
GROUND
23 GROUND
N/C
HOLO COMMAND 24 +15V SUPPLY

--0

L

[-

0.600....J
115.211

1__ 0100
I

12.51

NOTE: PINS HAVE 0.025 INCH STANDOFF FROM CASE. ±O.01"

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

3-15

SHM·45
DESCRIPTION

ABSOLUTE MAXIMUM RATINGS

MIN.

TYPICAL

MAX.

UNITS

-

160

200

nS

-

100

170

nS

-

±3%
±5%
±0.5

-

mV/v

-

+21
-22
+17
730

+25
-25
+25
875

mA
mA
mW
mW

HOLD TO TRACK DYNAMICS

±15V Supply Voltage (Pins 24, 22) ..
+5V Supply Voltage (Pin 9).
Analog Input (Pin 13, 14)1.
Digital Input (Pins 11, 12).
Output Current> ....

±18V
-0.5V to +7V
±18V
-0.5V to +5.5V
±65mA

POWER SUPPLY REQUIREMENTS

FUNCTIONAL SPECIFICATIONS
Specified at +25°C, gains of -1, ±15V, and +5V power supplies unless otherwise specified.

DESCRIPTION

MIN.

TYPICAL

MAX.

UNITS

±10
-

lK

-

V
ohm

+2.0
-

-

ANALOG INPUTS (pin 13, 14)
Input Volt. Range1 .
Input Impedance.
"1"
"0"
"1"
"0"

Voltage.
Voltage.
Current.
Current.

+0.8
40
-1.6

V
V
p.A
mA

ANALOG OUTPUTS (pin 1)
Output Volt. Range.
Output Current 2 ..
Output Impedance.
Max. Capacitive Load.

±10.25
-

-

+11.5

0.1
250

±40

-

V
mA
ohm
pf

-

-1.0
±.05
±0.5
±0.005
+1

±.1
±5
±.01
±5

16
300

-

MHz
V/p.S

-

6

-

nS

-

-

±50
±1

±5

pS
mV

-

60

100

nS

-

40

-

nS

-

0.5
15
1.2
-74

5
-

p.V/p.S
p.V/p.S
mV/p.S
dB

-

-

V/v
%
ppm/DC
%FS
mV

TRACK MODE DYNAMICS
Frequency Response
Small Signal (-3dB).
Slew Rate.

-

-

-

TRACK TO HOLD SWITCHING
Aperture Delay Time.
Aperture Uncertainty
(Jitter) .
Offset Step (pedestal)'
Settling Time
lOV to ± .01% FS
(±1 mV)6.
10V to ±.1% FS
(+10 mY).
HOLD MODE DYNAMICS
Droop Rate
at T= +25°C
at T= +70°C
at T= +125°C
Feedthrough Rejection

Operating Temp. Range
SHM-45-MC
SHM-45-MM
Storage Temp. Range
Thermal Resistance
Junction-to-Case
Case-to-Ambient
Package Type
Package Dimensions
Pins

PERFORMANCE
Gain3.
Gain Error3..
Gain Tempco.
Linearity Error3.
Initial Offset Voltage.

Supply Voltage Range
±15V.
+5V ..
Power Supply Rej. Ratio
Current Drains
+15V
-15V
+5V
Power Consumption

-

-

-

PHYSICAL ENVIRONMENTAL

LOGIC INPUTS (TTL)
Logic
Logic
Logic
Logic

Acquisition Time'
10V step to ±1.0mV
(.01% FS) ..
10V step to ±10mV
(.1% FS).

O°C to + 70°C (ambient)
-55°C to + 125°C (ambient)
-65°C to + 150°C
0.015°C/mW
0.035C/mW
24 pin ceramic
refer to Mechanical Dimensions
drawing
Kovar (0.010 x 0.018)

Footnotes:
1- Input signal times gain should not exceed the output voltage
range.
2- The SHM-45 output is current limited at approximately ±65
mAo The device can withstand a sustained short to ground.
However, shorts to either supply will cause permanent
damage. For normal operation, the load current should not
exceed ±40 mAo
3- Specified at +25°C.
4- Sample-to-Hold offset error (Pedestal) is constant regardless of
input/output level.
5- Acquisition time is tested with no load and is relatively
unaffected by capacitive loads to 50 pF and resistive loads to
250 ohms.
6- Sample-to-Hold settling time between the point the sample-tohold command is given and the point at which the analog output (following a transient) settles to within a specified error
band around the final value.

TECHNICAL NOTES
1. All ground pins (10, 15, 21, 23) should be tied together and
connected to system analog ground as close to the package as possible. It is recommended to use a ground plane
under the device and solder all four ground pins directly to
it. Care must be taken to insure that no ground potentials
can exist between Pin 10 and the other ground pins.
2. Although the power supply pins (9, 22, 24) are internally
bypased to ground with 0.Q1 /iF ceramic capacitors, additional external 0.1 /iF to 1/iF tantalum bypass capacitors may be
required in critical applications.

3-16

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

SHM·45
3. A logic "1" onthe HaLO COMMAND INPUT, Pin 12will put
the device in the sample mode. In this mode, the device acts
as an inverting unity gain amplifier and its output will track
its input. A logic "0" on Pin 12 will put the device in the HOLD
mode, and the output will be held constant at the last input
level present when the hold command was given.

INPUT A
Jl

4. The maximum capacitive load to avoid oscillation is typically
2S0 pF. Recommended resistive load is soon, although
values as low as 2son may be used. Acquisition and sampleto-hold settling times are relatively unaffected by resistive
loads down to 2son and capacitive loads up to so pF.
However, higher capacitances will affect both acquisition
and settling time.

J2

1

OUT

14
RANGE

r

Figure 2. V OUT Range Selection
Table 1. Jumper Selections for V OUT Ranges

SHM·45 OUTPUT VOLTAGE RANGE SELECTION
The RANGE pin of the SHM-4S is usable to select different output voltage ranges. The output voltage ranges are selectable
by hardware programming the SHM-4S to operat~ at different
gains. Figure 2 shows the configuration to select different
voltage ranges. In this configuration INPUT A (Pin 13) is the voltage input and RANGE (Pin 14) is used as a gain selector input.
Table 1 shows the jumper selection details.

1

13

Y'N

Install
Jumper

Operating
Gain

-10

Jl

-10

-

+10

Jl

-2
-1
-2
-1
-O.S
-O.S

V OUT

VIN

+10 to
+10to
o to
to
+S to
Oto

-S to +S

-10 to +10
Oto -S

o to

o

-10
-10to +10
o to -10

+10

-

-S
+S

J2
J2

SHM·45 PERFORMANCE CHARACTERISTICS

-

1.0
0.9

:>
:>

0.8

mv(%F.S.)

""'-

"-~

0.7

0.6
~ O.S

0.4
CD 0.3
.~

-

I

II
~

./

0.2
0.1
0.01 0.03

0.1

0.3

0.1

3.0

f'; I!~: ~- -=:-;:+~ -':-J:-~t~-~ I:f- =~_rt=1~- ~-~ I
:11- -=:+-

u:::

so

..

100

-=:+-1

150

200

2S0

300

Time (nsec)
10.0

Frequency (MHz)

Acquisition Accuracy vs. Acquisition Time for a lOV Step

Track Mode Gain Amplitude and Phase Response

Ill\

I

[~;fI

r-------t-I

10

100

Input Signal Slew Rate (VII' sec)
Aperture Jitter Window
100psec
For vet)
10sinwt, dv/dt (max)
20rrF

=

=

=

12

m

ill

I
I
I

I
I

I
I
I
I
I

13

I
Bottom
View

W
I
CD
I
CD

24

Accuracy Error Due to Aperture Uncertainty

Ground Plane Layout

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-17

SHM·45
Table 2. Jumper Selections for VIN Ranges

APPLICATION: Using The SHM-45
with DATEl:s ADC-500/505
VIN

The SHM-45 is designed to accept different voltage ranges.
However, to fully utilize the dynamic range of DATEL.:s
ADC-500/505, the SHM-45 must be hardware programmed to
provide the appropriate output voltage range. In the configuration shown in the Figure 3, RANGE functions as a gain selector. Refer to Table 2 for jumper selection details. This application
configuration can sample at 1.2 MHz rate.

Gain

Range

o to
o to

Install Jumpers

+1-1
-2
-1
-0.5
-2

+10
-10
-5 to +5
-10to +10
oto -20
Oto -5

J2,J3
J2
J1, J4
J1
J1, J5
J2,J4

-Note: The application in this configuration operates at an overall effective gain of + 1.

13

1

3

1
J4
J3

14

INPUT

SHM-45

ADC-500

J5

J2

2

RANGE

J1

J

I

r--~~--------A---'

I
I
I

10KO
LF4y

~h

I

10KO

I
I

1

SEE NOTE 2.
+REF COMP
BIN

I

I
I
I

J6 17

.1

NOTES
1. The amplifier circuit shown is only needed if a positive unipo·
2. Positive Unipolar System Coding
lar signal is input to the SHM-45 (0 to + 10V).
J6 Open
VIN
OV(GND)
+ 10V (+FS)

1111 1111 1111
0000 0000 0000

J6 Closed
0000 0000 0000
1111 1111 1111

Figure 3. Using SHM-45 with ADC-500/ADC-505

SHM·45 IS IDEALLY SUITED FOR
USE WITH ADC·500/ADC·505
ADC-500 FEATURES
•
•
•
•
•
•

12-bit resolution
500 nanoseconds maximum conversion time
Low-power, 1.8W maximum
Three-state output buffers
-55°C to +125°C operation
Small 32-pin DIP

3·18

ORDERING INFORMATION
MODEL
SHM-45-MC
SHM-45-MM

TEMPERATURE RANGE
O°C to +70°C
-55°C to +125°C

For devices compliant to MIL-STD-883, contact DATEL.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

SHM·4860
High Speed, 0.010/0
Hybrid Sample/Hold
FEATURES
• 200 Nanoseconds maximum acquisition time
• 0.01 % Accuracy
• 100 Nanoseconds maximum samplehold settling time
• 74 dB feedthrough attenuation
• ± 50 Picoseconds aperture
uncertainty

1KU

GENERAL DESCRIPTION
DATEL's SHM-4860 is a high-speed,
highly accurate sample-hold designed for
precision, high-speed analog signal processing applications. Manufactured using
modern, high-quality hybrid technology,
the SHM·4860 features excellent dynamic
specifications including a maximum acquisition time of only 200 nanoseconds
for a 10V step to 0.01%. Sample-to-hold
settling time, to 0.01% accuracy, is 100
nanoseconds maximum with an aperture
uncertainty of ± 50 picoseconds.

t-

1KG
INPUT

HOLD COMMAND
HOLD COMMAND

©

Ci1

Both HOLD and HOLD digital control inputs are provided for use with either positive or negative true input commands.
Applications for the SHM-4860 include
high-speed data acquisition and data distribution systems, peak measurement
systems, fast fourier analysis, transient
recorders, and analog signal delay and
storage.
Power requirement is ± 15V dc and + 5V
dc with a maximum power consumption
of 875 mW. The SHM-4860 is available in
two models for operation over the commercial ooe to + 70°C, and military,
- 55°C to + 125°C operating temperature ranges. All models are cased in a
24-pin, hermetically sealed, ceramic
package.

tv

~~v

©

~

I

..!. 3l
~

•

OUTPUT

~+5V

r

DRIVER

The SHM-4860 is a complete sample-hold
circuit, containing a precision MaS hold
capacitor and a MOSFET switching con·
figuration which results in faster switching
and better feedthrough attenuation. Addi·
tionally, a FET input amplifier design
allows faster acquisition and settling
times while maintaining a considerably
lower droop rate.
Other important features include a minimum input voltage range of ± 10.25V, an
aperture delay time of6 nanoseconds, a
typical droop rate of ± 0.5 /1V//1second,
and a sample-to-hold offset error as low
as ± 2.5 mV. Sample-to-hold offset is constant regardless of the input/output voltage level. Output slew rate is typically
300V/microsecond and small signal bandwidth (-3 dB) is 16 MHz.

~

l

=\U
?

~+15V
I""

15V

\ . . - SUPPLY BYPASS
CAPACITORS

SYSTEM
GROUND

MECHANICAL DIMENSIONS
INCHES (MM)
l-0.800 MAX---j
(20,3)

INPUT/OUTPUT CONNECTIONS

(

~L~O.'90(4.a)MAX.

--r-l

f

D.150 MIN
(3.B)

0.010 x 0.018
KOVAR

012

DOT ON TOP _
REFERENCES
PIN 1

f

··
··
···
··
·,

'3.

··
···
··· 0..[
·
•

BOTTOM
VIEW

,'.200

1 ""
11 SPACES
AT 0,100
EA (2,5)

(33.3)

24 •

--0

~O.100
~0.6DD-I
(15,2)
(2.5)

PIN
1
2
3
4
5
6
7

8
9
10
11
12

FUNCTION
OUTPUT

PIN
13
N/C
14
N/C
15
16
N/C
17
N/C
N/C
18
19
N/C
NIC
20
+5VSUPPLY
21
22
GROUND
HOLD COMMAND 23
HOLD COMMAND 24

FUNCTION
INPUT
NIC
GROUND
N/C
N/C
N/C
N/C
N/C

GROUND
-15V SUPPLY
GROUND
+ 15V SUPPLY

NOTE: PINS HAVE 0.025 INCH STANDOFF FROM CASE, ±O.Q1"

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-19

SHM-4860
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS
± ISV Supply Voltage (Pins 24, 22) ••.••
+ SV Supply Voltage (Pin 9) .•.....•..•
Analog Input (Pin 131' ..•...•...•••..
Digitallnput (Pins II, 12) ....•••••••..
Output Current. . ...•......•••••••••

±18V
-0.5V to + 7V
±18V
-0.5V to +5.5V
±65 mA

FUNCTIONAL SPECIFICATIONS
Typical at2S·C, ± ISV and + SV supplies unless otherwise noted.
ANALOG INPUT/OUTPUT

MIN

.Input/Output Voltage Range •......... ± 10.25V
Input Impedance ...................
Output Current" ••...........••.••..
Output Impedance .........•...•••..
Maximum Capacitive Load
-

-

...........

TYP

MAX

-

± 11.5V
1 kll

-

±40 mA

-

+5.0V
+0.8V

0.1 11
250 pF

DIGITAL INPUT
Input Logic Level,' Logic "I" ........
Logic "0"
Loading" ••.•...••••••.•..•......••

+2.0V
OV

-

-

1 TIL Load

-

-1.0 VN

-

TRANSFER CHARACTERISTICS
Gain •...........................•.
Gain Accuracy •••.............•....
Gain Linearity Error" .................
Sample-Mode Offset Voltage ..........
Sample-to-Hold Offset Error
(Pedestal)"
Gain Tempco (Drift) ........••••..•..
Sample-Mode Offset Drift' ..........••
Sample-ta-Hold Offset
(Pedestal) Drift" ..................

......................

±0.05%
±0.005% FS
±0.5 mV

±0.1%
±0.01% FS
±5 mV

-

±2.5 mV
±20 mV
±0.5 ppm/·C
±5 ppm/·C
± 3 ppm of FSR/oC ± 15 ppm of FSR/oC

-

± 4 ppm of FSR/oC

-

-

160 nsec.
100 nsec.
90 nsec.
75 nsec.

200 nsec.
170 nsec.

60 nsec.
40 nsec.

100 nsec.

DYNAMIC CHARACTERISTICS
Acquisition Time;7
10Vto ±O.OI%FS(±1 mY) ....•....
10Vto ±O.I%FS(±10mV) ...•.....
10Vto ±1%FS(±100mV) ..•••....
Wto ±1%FS(±100mV) •.•••••...
Sample-ta-Hold, Settling Time.
10Vto ±O.Ol% FS (± 1 mV) •.••.....
10Vto ±O.1%FS(±10mV) .••.••...
Sample-ta-Hold Transient ••••.....•..
Aperture Delay Time •••••..........•
Aperture Uncertainty (Jitter) ..........
Output Slew Rate •............•••...
Small Signal Bandwidth (- 3 dB) ••••...
Droop: + 2S·C ••...•.•..••.••......
+70·C ••...••••.••...•••...
+12S·C .•••••••.•..........
Feedthrough .•••.........••.•.••...

-

-

--

-

--

180 mV pop

-

6 nsec.
±50 psec.

300 V/p.Sec.
16 MHz
0.5 pWpSec.
15 ",V/pSec.

--

5 ",V/pSec.

1.2 mV/pSec.
74 dB

-

POWER REQUIREMENTS
Voltage Range: ± ISV ......•....•...
+SV .......••...••..
Power Supply Rejection Ratio .•.••....
Quiescent Current Drain: + ISV •....•.
-1SV .......
+SV ........
Power Consumption ....•...•...••...

-

-

±3%
±5%
±0.5 mVN
+21 rnA
-22 mA+ 17 mA730 mW

+25 mA
-25 rnA
+25 rnA
875 mW

1. All ground pins (10, 15, 21, 23) should
be tied together and connected to system analog ground as close to the
package as possible. It is recommended to use a ground plane under
the device and solder all four ground
pins directly to it. Care must be taken to
insure that no ground potentials can exist between Pin 10 and the other
ground pins.
2. Although the power supply pins (9, 22,
24) are internally bypassed to ground
with 0.01 I'F ceramic capaCitors, additional external 0.1 I'F to 1 I'F tantalum
bypass capacitors may be required in
critical applications.
3. A logic "0" on the HOLD COMMAND
INPUT, (Pin 11) (or a logic "I" on the
HOLD COMMAND INPUT, Pin 12) will
put the device in the sample mode. In
this mode, the device acts as an inverting unity gain amplifier and its output
will track its input. A logic" I" on Pin 11
(logic "0" on Pin 12) will put the device
in the HOLD mode, and the output will
be held constant at the last input level
present when the hold command was
given.
If the HOLD COMMAND INPUT (Pin
11) is used to control the device, Pin 12
must be tied to digital ground. If HOLD
COMMAND INPUT (Pin 12) is used to
control the device, Pin 11 must be tied
to +5V.
4. The maximum capacitive load to avoid
oscillation is typically 250 pF. Recommended resistive load is 5000,
although values as low as 2500 may be
used. Acquisition and sample-to-hold
settling times are relatively unaffected
by resistive loads down to 2500 and
capacitive loads up to 50 pF. However,
higher capacitances will affect both acquisition and settling time.

OFFSET AND GAIN ADJUSTMENTS

PHYSICAUENVIRONMENTAL
Operating Temperature Ranges
SHM-4860 MC .••..............•..
SHM-4860 MM .•.•...••..•......••
Storage Temperature Range ........••
Package Type .•..................••
Pins ..............................

O°C to + 70°C
- 55°C to + 125°C
-65°C to + 150°C
24 Pin Ceramic
Kovar (0.010 x 0.018)

FOOTNOTES:
. 1. Input signal should not exceed the supply voltage.
2. The SHM-4860's output is current limited at approximately ± 65 mA. The device can withstand a sustained
short to ground. However, shorts from the output to either supply will cause permanent damage. For normal
operation, the load current should not exceed ± 40 mAo
3. See Technical Note 3.
4. One TTL load is defined as sinking 40 ~ with a logic "I" input and sourcing 1.6 mA with a logic "0" input.
5. Full Scale (FS) = 10V. Full Scale Range (FSR) = 20V.
6. Sample-Io-Hold offset error (Pedestal) is constanl regardless of input/outpul level.

Critical offset adjustments may be performed utilizing this configuration. Apply
zero volts (OV) to the analog input and adjust R2 so that the output measures zero
volts (OV) during the hold mode period of
the SHM-4860.
Gain may be trimmed by applying an FS
voltage to the analog input and adjusting
Rl so that the output measures the same
FS voltage during the hold mode period.

7. Acquisition time is tested with no load and is relatively unaffected by capacitive loads to 50 pF and resistive

loads to 2500.
8. Sample-Io-Hold settling time is the time between the point the sample-to-hold command is given and the
point at which the analog output (following a transient) settles to within a specified error band around the
final value.

3-20

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

SHM-4860
OFFSET AND GAIN ADJUSTMENTS
(GAIN ADJ.)

10K,O.1%
R1
10K,O.1%
ANALOG
INPUT
()------'\iV'---JWyIr--JI/VI,--,

13

50K
-15V~+15V

SHM·4860

----0

ANALOG
OUTPUT

SAMPLE

~

+5V

R2
(OFFSET ADJ.)

HIGH SPEED AID USING SHM·4860

PERFORMANCE
Track Mode Gain Amplitude and Phase Response
1.0

-....

GAIN

0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1

........

"-]Ii
I
I
~

,., . /

PHASE

0.01 0.03 0.1 0.3 0.1
Frequency (MHz)

3.0 10.0

cquisition Accuracy vs. Acquisition Time for a 10V Step

STARTCONVEAT

'"

HOLD COMMANOS

mv(%F.S.)

'~ ~il=1- - -+- t=~t
+-1 I =-+----+--tlll
50

100

150

200

250

300

DATEL's SHM-4860, a high·speed sample/hold amplifier, is
shown here coupled with DATEL's ADC-500/505. Together,
they provide a high-speed analog to digital converter with
sample/hold which can attain throughput rates exceeding
1.25 MHz.

Time (nsec)

ORDERING INFORMATION

Accuracy Error Due to Aperture Uncertainty
MODEL NO.

lil 1

LJ ·1

10
100
Input Signal Slew Rate (V/Jlsec)
Aperture Jitter Window = 100psec
For v(t) = 10sinwt, dv/dt (max) = 20 ... F

SHM-4860MC
SHM-4860MM
ACCESSORIES
Part Number
DILS-3

OPERATING
TEMP. RANGE
O°C to + 70°C
- 55°C to + 125°C
Description
24-Pin Mating Socket

For military devices compliant to MIL-STD-883, consult the
factory.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-21

SHM·5
Ultra·Fast, 0.010/0
Sample·Hold

FEATURES
• 200 Nanoseconds acquisition to 0.1 oAl
• 350 Nanoseconds acquisition to
0.01%
• 5 MHz Bandwidth
• 0.005% Linearity
• 250 Picoseconds aperture uncertainty

GENERAL DESCRIPTION
Model SHM-5 is a new, ultra-fast acquisition sample-hold module for use with high
speed 10- and 12-bit AID converters.
When used with DATEL's model ADCEH12B3, a 12-bit, 2 microseconds AID,
the SHM-5 permits sampling and conversion at rates up to 425 kHz. The key circuit
element in the SHM-5 is an ultra-fast settling hybrid operational amplifier manufactured in DATEL's thin-film hybrid facility.
This amplifier operates in the inverting
mode as a hold amplifier. A fast FET
sampling switch operates between two virtual ground points in order to keep switching errors small and independent of signal
level. A second FET switch operates out,
of-phase with the first one to minimize
signal feed-through errors.

R

SAMPLE
CONTROL
ANALOG
; - - - - - - - - 1 " 6 OUTPUT
GND

The SHM-5 is designed primarily for fast
track & hold and simultaneous sampling
applications with AID converters. From the
tracking mode it realizes acquisition times
of 200 nanoseconds to 0.1 % or 350 microseconds to 0.01 % for a 10V change.
When the input buffer amplifier must also
make a 10V change, as in multiplexer applications, the total acquisition time is 1
microsecond to 0.01 %.
The SHM-5 operates in the inverting mode
with a gain of - 1 and an input impedance
of 108 ohms. Dynamic characteristics include a 5 MHz small signal bandwidth, and
25V/microseconds slew rate in the sampling (tracking) mode. When acquiring a
new sample, however, the internal slew
rate across the holding capacitor is
200Vlmicroseconds. Aperture delay time
is 20 nanoseconds and aperture uncertainty time is 250 picoseconds.
This device is packaged in a 2 x 2 x 0.357
inch epoxy encapsulated module. Operating temperature range is OCC to
+ 70 c C and power requirement is ± 15V
dc at 75 mA maximum. The SHM-5 is
pin compatible with DATEL's model
SHM-UH3.

3-22

MECHANICAL DIMENSIONS
INCHES (MM)

I

IT:o,

SlOE VIEW

T

~.020DIA.

i17-------------~~
•

0

.21

0

824-----------

8

f

7 SPACES
AT. 100 EA.

8f
0
0

2
15
16

,.00

8& ---..t.-,.160

BonOM VIEW

25 - - - - - - - - - - - - 9

o
o

PIN
1

U .250 MIN.

IL

.850

7 SPACES
AT.l00EA.

:~L---------l:: --.L

.150

INPUT /OUTPUT
CONNECTIONS

~6:':;

FUNCTION
SAMPLE CONTROL
SAMPLE CONTROL GND
ANALOG OUTPUT GND
ANALOG OUTPUT

17

NO CONNECTION

18
19

OFFSET ADJ.
+15V POWER

20
21
31

-15V POWER
POWER GND

32

ANALOG INPUT GND
ANALOG INPUT

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

SHM-5
FUNCTIONAL SPECIFICATIONS

TECHNICAL NOTES

Typical at 2S ·C, ± lSV supply unless otherwise noted.
INPUTS
Input Voltage Range ............
Input Overvoltage, no damage ...
Input Impedance ...............
Input Bias Current ..............
Sample Control,
sample mode ................
hold mode ..................
Sample Control Loading .........
Offset Adjustment Range ........

± 10V minimum
+15V
fOB ohms
250 nA maximum
+2.0 to +5.5V
OV to +0.8V
+1 mA
±300 mV

OUTPUT
Output Voltage Range, minimum . +10V
Output Current, S.C. protected ... ±40 mA
Output Impedance .•........... 0.1 n maximum
PERFORMANCE
Gain .........................
Gain Temp. Coefficient . . . . . . . . .
Output Offset Voltage,
sample mode ......••........
Output Offset Voltage Drift .......
Sample to Hold Offset Error ......
Tracking Nonlinearity ...........
Hold Mode Droop ..............
Hold Mode Feedthrough,
DC-SOO kHz .................
Output Offset vs Supply .........

-1.000 ± 0.1 %
± 15 ppm/·e maximum
± 50 mV maximum
± 30 /lV/·e maximum
± 5 mV maximum
+ 0.005% maximum
20 I'V/I'sec. maximum

1. The SHM-S initial gain error of ± 0.1 % must be adjusted out
separately from the sample hold. This is most easily done by
using the gain adjust of the A/D converter used with the
SHM-S.
2. The maximum sample-to-hold offset error of S mV is constant with signal level. This error can be adjusted out in the
hold mode by means of the external offset adjustment shown
in the diagram. It should be noted that the SHM-S can be
adjusted for zero output offset in either the sample (tracking)
mode or the hold mode, but not in both at the same time.
3. The sample control input is compatible with standard TTL
levels. It is recommended that this input be driven from its
own active pull-up Schottky TTL circuit, such as the 74S132.
This will readily supply the + 1 mA drive current required by
the SHM-S.
4. The analog signal delay from the input of the SHM-S to the
sampling switch is approximately 32 nanoseconds. Aperture
delay is 20 nanoseconds.
S. When the SHM-S is switched into the hold mode, about SO
nanoseconds is required for the switch transient to settle.
This time should be allowed for before the first AID
conversion is made.

CONNECTION TO ADC-EHI283

0.02%
1 mVIV

DYNAMIC RESPONSE
Acquisition Time', 10VtoO.l% ... 200 nsec. maximum
Acquisition Time', 10VtoO.Ol% .. 350 nsec. maximum
Acquisition Time2 , 10VtoO.Ol% .. 1.0 psec. typical
1.5 I'sec. maximum
Bandwidth, tracking, - 3 dB ..... 5 MHz
Slew Rate, tracking ............ 25V/l'sec.
Aperture Delay Time ............ 20 nsec.
Aperture Uncertainty Time ....•.. 250 psec.
POWER REQUIREMENTS
Power Supply Voltage .......... ±15Vdc ±0.5V
Quiescent Current ............. 75 mA maximum

ANALOG
OUTPUT

ANALOG
INPUT

PHYSICAL/ENVIRONMENTAL
Operating Temp. Range .........
Storage Temp. Range ..........
Relative Humidity ..............
Case Size .....................

o·e to + 70·e
-55·e to +85·e
Up to 100% non-condensing
2.0 x 2.0 x 0.375 in,
50,8 x 50,8 x 9,5 mm
Case Material ................. Black diallyl phthalate per
MIL-M-14
Pins ......................... 0.020" round, gold plated; 0.25"
long minimum
Weight ....•.................. 2 ounces (57 grams)
FOOTNOTES:

I

1. From tracking mode.
2. From input buffer.

=-:n--

TIMING DIAGRAM

STAAT
CONVERT

E.O,C
(STATUSI

n

100 nsec

_ _ _ _-I L-_ _ _ _ _ _ _ _

~

2.0 sec

/'.

_ __

AJD CONVERT

AID CONVERT
(ADC.EH12B31

!I.-------

~

~

I

350

nsec

--II

OFFSET ADJUSTMENT

!

+ 15V

ORDERING INFORMATION
SHM-S

20K

OFFSET
ADJUST

ACCESSORIES

Part Number

Description

DILS-2
TP20K

Mating Sockets: (2 per module)
Trimming Potentiometer

-15V

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-23

SHM·6
0.020/0, 2.0 Microseconds
Microelectronic Sample·Hold
FEATURES
•
•
•
•
•
•

0.02% Accuracy
2.0 Microseconds acquisition time
2 Nanoseconds aperture uncertainty
5 MHz Bandwidth
25 rnA Output current
Gain-programmable from ± 1 to ± 10

DIGITAL
CONTROL

GENERAL DESCRIPTION
The SHM-6 is a high speed, high accuracy
sample-hold circuit manufactured with thin
film hybrid technology. This design offers
the speed and performance of modular
sample-holds with the compactness and
integrity of advanced hybrid techniques.
The unit's excellent high-speed characteristics include a guaranteed acquisition
time of 700 nanoseconds to 0.1 % accuracy and 2.0 microseconds to 0.02% for
a 10 volt change.

CH (OPTIONAL

@)

INPUT AMPLIFIER
(TRANSCONDUCTANCE)

I

SWITCH

DRIVER

~

,r.

(J.l)

I

OUTPUT

,~-

>--r---

~

OUTPUT

~
ANALOG
COMMON

INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (MM)
L - l . 1 0 1 MAX-----l

I"

I~

,28.0)

I

I •.

o.150~a)~__

,.

The SHM·6 is a key component in fast
data acquisition systems. A 100 KHz
throughput rate can be accomplished using the SHM-6 'in conjunction with
DATEL's ADC-HZ 12-bit A/D converter
(which offers 8 microseconds maximum
conversion time).
The sample-hold is cased in a 32-pin
ceramic package. Models are available in
two operating temperature ranges: 0 to
+70°C and -55 to +100°C.

400pF

~MPLIFIER

I

.'N~-'

The SHM-6 is a complete sample-hold
containing a precision MOS holding
capacitor. The input amplifier is an open
loop transductance amplifier which can be
externally connected for closed loop gains
from ± 1 to ± 10. In addition to its speed,
accuracy and selectable gain, the SHM-6
has an output capability of 25 mAo These
features allow this unit to offer an unusual
degree of adaptability.
The most frequently utilized configuration
of the SHM-6 is a unity gain, noninverting
sample-hold. In this mode, the device has
a ± 10V input and output range with 108 n
input resistance. Full power bandwidth is
500 KHz, and small signal tracking
capability is 5 MHz. The input offset
voltage and sample to hold error can be
adjusted to zero with the use of two exter·
nal trim pots.

II

ij
0.010

x 0.160 (4,1)

KOVAR

",,[I

BOTTOM

,~

DOT ON TOP
REFEAENCES - PIN 1

PIN

190(4,9, MAX

-r

17

S/H STEP ADJUST .

-IN

18

5fH STEP ADJUST

3

NC

19

4

OFFSET ADJUST

2.

NC

5

•

NC

21

Ne

OFFSET ADJ. (Wiper)

22

DIGITAL CONTROL

7

NC

23

NC

8

OFFSET ADJUST

24

+Vde

· ~I J ,.

~ 0.900

I"

(22,8)

Ne

25

NC

ANALOG COMMON

2.

POWER GROUND

11

OUTPU
Ne

27
28

NC

12
13

Ne

29

NC

C.H. (OPTIONAL)

30

Ne

Ne

31

-15Vde

SfH ADJ. (Wiper)

32

Ne

14

_-.J_ 0.100
I

NC

,.

15

1

FUNCTION

P1N

• IN

9

ATO.l00EA 1.712

FUNCTION

1

2

'----'-------'

+ 15V de

(2,5)

NOTE: PINS HAVE Q,Q25 INCH STANDOFF FROM CASE, ±O,Ot"

3-24

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

SHM-6
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS
Positive Supply. . . . . . . . . . . . . . . . . ..
Negative Supply. . . . . . . . . . . . . . . . ..
Logic Supply ...••................
Digital Input Voltage. . . . . . . . . . . . . ..
Analog Input Voltage . . . . . . . . . . . . ..
Differentiallnput Voltage. . . . . . . . . ..

+ 18V
- 18V
+ 7.0V
+ 5.5V
± Vs
± 30V

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ± 15V and +5V supplies unless otherwise noted.
INPUT AMPLIFIER SPECIFICATIONS
Offset Voltage ..............•.....
Offset Voltage Tempco ............
Offset Current ....................
OffsetCurrentvs. Temp ......••....
Bias Current ......•..............
Input Resistance. . . . . . . . . . . . . . . . ..
Common Mode Voltage Range ......
Common Mode Rejection Ratio ......
Open Loop Gain .............•....
Gain Bandwidth Product ..........•
Power Supply Rejection Ratio .......

±2 mV
± 100 ",V/oC
1 nA maximum
Doubles every 10°C
lanA maximum
10. {l
± 10V minimum
74 dB minimum
1O·VN
5 MHz
0.004%1% Supply

DIGITAL INPUT CHARACTERISTICS
Digital Control Logic ............... DTL, TTL
Input Logic Level, Sample Mode ..... OV to + 0.8V at - 3.2 rnA
Input Logic Level, Hold Mode ....... + 2.0V to + 5.0V at + 80~
ANALOG OUTPUT CHARACTERISTICS
Output Voltage Range •........••.. ± 10V minimum
Output Current.'.................. ± 25 rnA maximum
Output Resistance .............•.. 0.1 {l maximum
SAMPLE/HOLD CHARACTERISTICS (Non inverting unity gain)
Acquisition Time,
10VSteptoO.H'o ............... 700 nsec. maximum
Acquisition Time,
10V Step to 0.02% ....•......... 1.5 ",sec. typical
2 ",sec. maximum
Aperture Delay Time .......••...... 20 nsec.
Aperture Uncertainty Time .......... 2 nsec.
Sample to Hold Error .............. Adjustable to Zero
Hold Mode Voltage Droop .......... 10 ",V/",sec. maximum
Hold Mode Feedthrough ............ 0.02% maximum
Offset .......................... Adjustable to Zero
Gain ....•...................•... +1 to +10
Gain Error ....................... 0.01 % maximum
Nonlinearity, VOUT = ± 10V ......... 0.02% maximum
Full Power Bandwidth,
VOUT = ± 10V .................. 500 KHz
Slew Rate ....................... 40 V/",sec.

1. It is essential that the + 15V, - 15V and + 5V supplies, pins
28,31, and 24 respectively, each be bypassed to ground with
a 0.1 I'F ceramic capacitor connected as close to the pins as
possible.
2. Digital Common, pin 26, and Analog Common, pin 10, are
not connected together internally, therefore they must be
connected externally as directly as possible. It is strongly
recommended that a ground plane be run underneath the
case between the two commons. Analog ground and ± 15V
power ground should be run to pin 10, digital ground and
+ 5V power ground should be run to pin 26.
3. An external holding capacitor can be added to decrease hold
mode vOltage droop but with consequently longer acquisition
time. For temperatures up to + 85°C, pOlystyrene capacitors
are recommended; for higher temperatures, pOlypropylene
or teflon capacitors should be used.
4. In the inverting unity gain operating mode, the feedback and
input resistors should be carefully matched or trimmed to
yield the desired gain of one. In general, the operating
parameters are the same as the noninverting unity gain configuration, except that the sampling bandwidth is reduced by
a factor of two. For applications of the SHM-6 with gain
greater than one, sampling bandwidth is inversely proportional to gain.
5. Capacitive loads on the output should be limited to 100 pF to
maximize acquisition time. The SHM-6 has a ± 25 mA current drive capability.
6. This device dissipates approximately 2 watts of power due to
the transconductance amplifier. The case to ambient thermal
resistance is approximately 25°C per watt. For ambient
temperatures above +50 o C, care should be taken to maintain air circulation in the vicinity of the case.
7. The adjustment procedures for the SHM-6 are as follows.
Ground the input pin and connect the output to a D.V.M.;
operate the offset adjustment potentiometer to yield an output of zero as read on the D.V.M. The sample-hold step adjustment is performed with the input pin grounded and the
output connected to an oscilloscope set to 1 mV/cm sensitivity. The digital input pin is driven with a compatible square
wave at approximately 250 KHz and the sample-hold step
adjustment potentiometer is operated to produce a flat-line
output on the oscilloscope.

POWER REQUIREMENTS
Positive Supply ................... +15Vdc ±0.5V at 55 rnA
Negative Supply .................. -15Vdc ±0.5V at 60 rnA
Logic Supply ..................... +5V dc ±0.5V at 30 rnA
PHYSICAL/ENVIRONMENTAL
Operating Temperature Ranges
SHM-SMC .................•....
SHM-SMM .....................
Storage Temperature Range .•......
Package Type ....................
Pins ............................
Weight. .........................

O°C to + 70°C
-55°C to +100°C
-65°C to +150°C
32 Pin Ceramic
Kovar (0.010 x 0.018)
0.5 Ounce (14 grams)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

3-25

• .,
II:!

SHM-6
OPERATING MODES
-15V

+15V

+5V

+'N

NONINVERTING SAMPLE-HOLD

+

GAIN

OUTPUT
___ ...1

1

= +1

The 2K{J offset trimming potentiometers should be of the
100PPM/oC cermet type. These are available from DATEL's as
model TP2K.
ANALOG
COMMON

OFFSET ADJUST

-15V

+ 15V

+5V

NONINVERTING SAMPLE-HOLD
OUTPUT

ANALOG
COMMON

GAIN

=1

+ R.
Rt

Bandwidth decreases proportionately with gain. Resistors R1
and R2 should be 100PPM/oC or better, metal film type
resistors. The indicated ratio between R1 and R2 should be matched as closely as possible and trimmed if necessary.

OFFSET ADJUST

R,

INVERTING SAMPLE-HOLD
-IN

GAIN
OUTPUT

R,

For again of· -1 the bandwidth is one half that of the noninverting mode, for higher gains the sampling bandwidth is proportionately reduced. The above-mentioned matching procedures
should be followed.

R,

3·26

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (SOB) 339-6356

SHM-6
TYPICAL PERFORMANCE
(Noninverting unity gain at 25 ·C, ± 15V and + 5V supplies unless otherwise noted)

ANALOG
INPUT

ANG.
GND.

MUX
1~

1
J

A high speed data acquisition system
employing the SHM-6. This system is
capable of a 110kHz throughput rate
with 12 bit resolution. In this system the
SHM-6 is used with DATEL's ADCHZ12, a high-speed hybrid 12 bit AID
converter, and DATEL's MV-808, a low
cost monolithic analog multiplexer. Use
of a low on-resistance MUX is recommended, so that the time constant
formed by MUX on-resistance and bus
capacitance does not limit the acquisition performance of the SHM-6 .

DIGITAL

ADC-HZ12

OUTPUTS

SEC ACQUISITION TIME
START

STATUS iE.O.CI

s,.SEC CONVERSION TIME

CHANNEL
ADDRESS

20

I

~

I

~ 10

-~

~ 8
~

o

--

4

1---

'"~
~

.

I
I

o
o

:2

o

~

1

20

-h+t,~

.~

2

,

+ ---

--

6

o

~

24

~

",
'\

16

u

~ 12

• I

----c-c

0.8

---

06

i
1

0.4

,

V
/

V

V

V

V

f--5~

"' , r

3

---.

"-

~f--

-

1 - - c__

.e----

J--.

--

f---

-------

0.5

--1---

6

8 10

GAIN
200

400

600 800 1K

2K

4K

CAPACITANCE IpFI

6K BK 10K

400 800 1600

3200

4800

6400

8000

9600

CAPACITANCE IpF)

ORDERING INFORMATION
0

B

6-

1

r-

--

V
J/
1

/

/

V

OPERATING
TEMP. RANGE

MODEL
SHM-6MC
SHM-6MM
ACCESSORIES
Part Number
DILS-2

2

10
GAIN

TP2K

DOC to + 70°C
- 55°C to + 100°C

SEAL
Hermetic
Hermetic

Description
Mating Socket
(2 required per SHM-6)
Trimming Potentiometers
(2 required per Sample-Hold)

For high reliability devices, contact DATEL.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

3-27

•

SHM-7
Video Speed
Sample-Hold

FEATURES
• 40 Nanoseconds acquisition time
• Dual outputs
• 10 Picoseconds aperture uncertainty
• 40 MHz bandwidth
• 30 rnA Output current
GENERAL DESCRIPTION
DATEl's SHM-7 is an ultra-fast sample
and hold designed for high speed analog
signal processing applications. The
SHM-7 acquires a 2V dc input change to
0.1 % in only 40 nanoseconds and aperture uncertainty time is less than 10
picoseconds. Sample-mode bandwidth is
40 MHz.
The SHM-7 is a complete Sample-Hold,
containing an input buffer amplifier, a
precision 53 pF MOS holding capacitor,
and two output buffer amplifiers. The
sampling switch is controlled by a series
10,000 complementary ECl input. An ECl
differential line driver can be conveniently
used for the sample control inputs.
Other features of the SHM-7 include a
± 5V dc input voltage range, a fixed gain
of + 0.995, and a maximum gain temperature coefficient of 33 ppm/oC. The device
has two outputs, each with a ± 5V dc output voltage swing at 30 mA and an output
impedance of only 13Q. The outputs may
be tied together for decreased output impedance and increased output current.
The SHM-7 is functionally laser trimmed at
the factory for offset, sample to hold offset, and gain errors, and is designed to be
used without external adjustment circuits.
The SHM-7 is an ideal choice for use in
ultra-high speed data acquisition systems,
and video processing applications, and
with its dual outputs, it is especially useful
in two stage flash converter systems.
Power requirement is ± 15V dc at 60 mAo
The SHM-7 is available for operation over
the O°C to + 70°C operating temperature
range and is cased in a 24 pin, hermetically
sealed, ceramic package.

13"

13D

MECHANICAL DIMENSIONS
INCHES (MM)

-L5a
~0

[-

1381
---,---

112

131

I
BOTTOM
VIEW

11

I
24 I

t

PIN

1

FUNCTION

SAMPLE
N.C

'200

13

I.

FUNCTIOt-.

PQWEACOM.
ANALOG COM.

15

PQWERCOM,

N.C,

1.

OUTPUT 2

N.C

17

ANALOG COM.

N.C

1.

OUTPUT 1

N.C.
N.C.

"
20

ANALOG COM.

-15V de

21

INPUT COM

10

N.C.

22

ANALOG INPUT

11

POWER COM.

23

12

POWER COM

2'

N.C.
N.C.

1"'"""
AT0100
fA 12,51

33.3

011
r- 0100

PIN

SAMPLE

11 SPACES

--0

r-~1~-1

INPUT/OUTPUT
CONNECTIONS

O.I90(••alMA><.

0010 II. 0018
KOVAR

I

DOT ON TOP

MODEL NO.

j

---.J
---I

o 150MIN

REFERENCES
PIN 1

ORDERING INFORMATION

800 MAX
(20,3)

+15V de

12.5)

NOTE: PINS HAVE 0.Q25INCH STANDOFF FROM CASE, ±O.O1»

OPERATING
TEMP. RANGE

SHM-7MC

3-26

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

SHM-7
PHYSICAL/ENVIRONMENTAL

ABSOLUTE MAXIMUM RATINGS
Positive Supply . . . . . . . . . . . . . . . . ..
Negative Supply. . . . . . . . . . . . . . . . ..
Digital Input Voltage ..............
Analog Input Voltage. . . . . . . . . . . . ..

+ laV dc
- 18V dc
± 5V dc
± 5V dc

Operating Temperature Ranges
SHM-7MC ..................... DoC to + 70°C
Storage Temperature Range ........ -65°C to + 150°C
Package Type ................... 24 Pin. hermetically sealed,
ceramic.
Pins ............................ 0.010 x 0.018 Inch Kovar

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ± 15V dc Supplies Unless Otherwise Noted.
INPUTS
Input Voltage Range', minimum ....
maximum. . ..
Input Bias Current ................
Input Impedance, minimum ........
Maximum Source Impedance2 • . • . • •
Sample Controllnputs3 ••••••••••••

+ 2.5V dc
5V dc
50 ~
10 kll
501l
Differential ECl 10,000
Positive Pulse on Pin 3 and
Negative Pulse on Pin 1 gives
Hold Mode.

±

FOOTNOTES:
1. The SHM· 7MC has a maximum input'output voltage range of ± 5V.
2. Should be purely resistive. See technical note 3.
3. Input logic voltage levels are Vm "0" = -1.5Vto-1.4V,andVin "1" = -O.7Vto
-l.05V.
4. Specified for each output, both outputs may be tied together for decreased output impedance and increased output current.
5. For a ± 2V input.

6. lOV is a step from -SV to +SV de.

•

,

OUTPUTS
Output Voltage Range', minimum ...
maximum ..
Output Current' . . . . . . . . . . . . . . . . ..
Output Impedance' . . . . . . . . . . . . . . .

"

±2.5V dc
±5V dc
± 30 mA
131l

PERFORMANCE
Linearity ± 2.SV input volt. range ...
± SV input volt. range .....
Gain ...........................
Gain Tempco, maximum ...........
Sample-to-Hold Offset Error,
maximum .....................
Sample-Mode Offset Voltage,
maximum .....................
Sample-to-Hold Offset Voltage Drift ..
Sample-Mode Offset Voltage Drift ...
Hold Mode Feedthrough, maximum ..
Hold Mode Droop .................

0.1%
0.2%
+0.995
±33 ppm/oC
40 mV
±20 mV
75/LV/oC
± 250 /LV/oC
-66 dB
100 /LV/microseconds

DYNAMIC CHARACTERISTICS
Acquisition Time,

2V to 0.1% ......
2V to 1% .......
4V to 0.1 % ......
4V to 1% .......
1OV to 0.1 %6 .....
10V to 1%6 ......
Aperture Delay Time ..............
Aperture Uncertainty Time,
maximum .....................
Hold Mode Settling Time ...........
Sample-Mode Bandwidth; -3 dB .....
Sampling RateS ..................

TECHNICAL NOTES
1. The use of good high frequency circuit board layout techniques is required for rated performance. The power common (Pins 11, 12, 13 and 15), analog common (Pins 14, 17
and 20), and input common (Pin 21) pins are not connected
internally and therefore must be connected externally as
directly as possible through a low inductance, low resistance
path. The extensive use of a ground plane for all common
connections is highly recommended.

2. Although they are internally bypassed with 0.033 IlF
capacitors the supply pins (Pins 19, 9) should be externally
bypassed with 0.1 IlF ceramic chip capacitors mounted as
close to the supply pins as possible.

3. The SHM-7 inputs and outputs are sensitive to unusual load40 nanoseconds
25 nanoseconds
50 nanoseconds
35 nanoseconds
60 nanoseconds
45 nanoseconds
3 nanoseconds
10
20
40
17

picoseconds
nanoseconds
MHz
MHz

ing or long lines. The analog input must be non-reactive so
that leads should be short and purely resistive. Also, the
complementary Eel driver should be as close as possible to
pins 1 and 3 to minimize lead lengths to these pins.

4. The maximum, differential, digital input voltage is ± 5V. For
example, if pin 3 is at a potential of - 5V, pin 1 may not
exceed OV.

POWER REQUIREMENTS
Positive Supply, Pin 19 '" ......... + 15V dc ± 0.5V dc at 60 mA
Negative Supply, Pin 9 ............ -15V de ±O.5V dc at 60 mA

SAMPLE-HOLD DEFINITIONS
1. Acquisition Time
Time required, after receipt of the sample command,
for the hold capacitor to charge to a specified voltage
change and remain within a specified error band such
as 0.1%.
2. Aperture Delay Time (effective)
The time elapsed from the hold command to the opening of the sampling switch minus the delay from the
analog input to the sample switch.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

3-29

SHM-7
PERFORMANCE AND CONNECTION
BASIC GROUND PLANE LAYOUT

3. Aperture Uncertainty Time
Time variation, or jitter, in the opening of the sampling
switch.
4. Aperture Uncertainty Error
An amplitude uncertainty in the held value due to the
change in the analog input signal during the aperture
uncertainty time. This error is the product of the rate of
change of the input signal and the aperture uncertainty
time.
5. Hold-Mode Settling Time
The time from the hold command transition until the
output of the Sample-Hold has settled within the
specified error band (0.1 %). It includes aperture delay
time.
6. Hold-Mode Droop
The output voltage change per unit of time while in the
hold mode.
7. Bandwidth
The frequency at which the gain is down 3 dB from its
dc value. It's measured in the sample-mode with a
small-signal sine wave.

12

I

I

I

I

CD

CD

I

I

BonOM
VIEW

C!)
I
I

CD

I

I

CD'

DOT ON TOP
REFERENCES
PIN 1

24

I

ACQUISITION TIME
VS. INPUT VOLTAGE

1

H-

I

+15V

I-

1\

1.0%

j

j--t-

j-

INPUT VOLTAGE STEP

rHv1\ r-Hv1\ H-

TYPICAL CONNECTION

0.1

13

l~Vl
1\

\

1

1

\

~F

~

0.3%

L"
I'

I.....

-'"

0.1%

19

I'

l'.
20

40

30

50

60

ACQUISITION TIME (nsec)

NOTE: 10 VOLTS IS A -5V TO + 5V de STEP

22

ACQUISITION TIME
VS. TEMPERATURE

ANALOG
INPUT
SHM-7

21

16

-

90

-::::

18 ~-*---C OUTPUT

11

70

-

12

14

17

"oSI

50

~

40

20

I I

.

r

+-4VTOO.l%

f--ZVTOO.l%

30

DIFF. LINE
DRIVER

±::::

~

10

~L

I
I

20
0.1 /IF

3-30

-i

-. .

w

Eel 10,000

-15V

:Ft=

--

lOVl TO 0.1%

60

15'

-

.

I

13

+-L-

- -

-

80

+I

rt

-25

- -

I

0

+10

+25

-t=t=

-;-

-4-

-10

-t-- t--+

+50

~++.

.
+70

=f

+85

TEMPERATURE (OC)
NOTE: 10 VOLTS IS A - 5V TO + 5V de STEP.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

SHM-7
TYPICAL APPLICATIONS
TWO STAGE CONVERSION SYSTEM
OUTPUT

2

lrq

SHM-7
OUTPUT
1

I
AOC-HU38

BIT

1

2

3

4

5

6

7

6

DATA OUTPUTS

HIGH SPEED DATA SYSTEM
+15V

-15V

+15V
745299

17

(MSB)
BIT 1 (MSB)

19

18

~-oBIT2

19
BIT 3
ANALOG
INPUT

22

16

20

o----------~~

BIT 4

18

21

ADC-81S

SHM·7

BIT 5

22

---0

24

,
I

r-~

I

lK

{l

I

10pF

L___ ~ __

(LSS)

------,

I

I

BIT 7
BIT 8 (LSB)

3

--------

II

BIT 6

23

-15V

OUTPUT
DATA BUS

lKn

l'~"

i
I

I
__________ -1I

12

15
ENABLE

.sv

TTL INTERFACE CIRCUIT
START COMMAND

A high speed data system using DATEL's SHM-7 and ADC-B1S, with an output register, to drive a data bus. The Start
Command is a 60 nanosecond wide, TTL-compatible, pulse with a maximum frequency of 1.5 MHz. Upon receipt of a start
command, the SHM-7 will track the input voltage and the ADC-B1S will reset. On the trailing edge of the start command,
the SHM-7 will hold the input and the ADC-B1S will begin its conversion. On the leading edge of the next start command,
the output data will be clocked out of the output three-state register. The ADC-B1S is an B-bit, 700 nanosecond, analog-todigital converter. With this system, a ± 2.SV input step can be acquired to 0.1 % accuracy in 40 nanoseconds and held to
within BO p.V while the AID conversion takes place.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-31

SHM-9
Low Cost, Fast, Sample-Hold
FEATURES
•
•
•
•

Low cost
0.01 % Accuracy
6 Microseconds acquisition time
0.2 Millivolt/millisecond hold-mode
droop
• No external adjustments needed
COM

Its low cost, high performance and input
control flexibility make the SHM-9 a good
choice for unnumerable applications including sampling for AID conversion, analog demultiplexing circuits and simultaneous sampling circuits. The small size
of the SHM-9 allows it to be easily used
with automatic insertion equipment.
The SHM-9 is available in two models
for operation over the commercial OOG to
+70°C and military -55°G to +125°C
operating temperature ranges. Power
requirement is ±15V dc and ±5V dc. All
models are packaged in a 16-pin,
hermetically sealed, ceramic DIP.

3-32

GUARD
COM.

2
SIGNAL
IN

The SHM-9 is a complete self-contained
unit, including a bipolar input amplifier, a
low-leakage electronic switch, a FET output amplifier, a precision 1000 pF hold
capacitor and logic control circuitry. The
control circuitry allows the SHM-9 to be interfaced with virtually any A/D converter
using the converter's start/convert and
EOG signals. This allows the user to put
the SHM-9 into the hold mode using the
start/convert pulse; thus when the AID's
EOG signal goes high and conversion
begins, the SHM-9 will already be providing a stable analog input signal. When
the EOG goes low, signaling the end of
conversion the SHM-9 is switched into the
sample mode. If this is not practical, the
SHM-9 can also be used with a single control signal. An external hold capacitor may
be added if necessary.
Other important features include 1010{J input impedance, a hold-mode feedthrough
of 0.01%, and a hold-mode droop of only
0.2 millivolts/milliseconds maximum input/output voltage range is ± 11.5V dc, input bias current is 50 nA maximum, and
the input offset voltage drift is 20 fLV/oC.
The SHM-9 is functionally laser trimmed to
eliminate offset, and sample to hold offset
errors, and is designed to be used without
external adjustment circuits.

pow

GUARD

GENERAL DESCRIPTION
Datel's SHM-9 is a fast, hybrid samplehold amplifier that combines high performance versatility and low cost. Acquisition
time, for a 10V dc change to 0.01%, is
only 6 microseconds, and aperture delay
time is 200 nanoseconds. The small signal
bandwidth is 4 MHz.

4

14

SIGNAL HOLD HOLD SIGNAL
OUT
CAP. CAP.
OUT
HI
La

MECHANICAL DIMENSIONS
INCHES (mm)

INPUT/OUTPUT
CONNECTIONS

f.I 1:;;:1 )l'~ I-'P -'i:. :Nf-~ =~': ~C: ;-'. :C : ': :'- M- O-N +P'- 1'~:. :N~ ~5;:. :c : , -:c :O .cN'- _- l
~ 0.808 MAX-----;1

PIN1
!DENT.

1

8

3

-*---

0.035 (0,9)

T ~ J.....

-15VOC(V-)
11 CK
OUTPUT
12 PR
EXT. HOLD CAP. HI 13 POWER COMMON
6 OUTPUT
14 EXT. HOLD CAP. LO
f--'7'--f-,N'-"V'-'=E'-R
c==T'-O
c- U-T--+'1-'-5+'+::'1"5'-'V-"O-':'C"'(V'-'+"-)"..:..:=-J

0.~4,3) MIN

0.104 MAX
(2,65)

8

INVERT IN

16 GUARD COMMON

----L
1..-°.100
I I (2,5)

----J

-11_

0.018
11(0,46)

NOTE: PINS HAVE 0.035 ± 0.010 INCH STANDOFF FROM CASE.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

SHM-9
ABSOLUTE MAXIMUM RATINGS
Positive Supply, Pin 15 ......... .
Negative Supply, Pin 3 .....••...
Logic Supply, Pin 10 ........... .
Analog Input Voltage ...•........

TECHNICAL NOTES
+18V
-18V
5.5V
±Vs

FUNCTIONAL SPECIFICATIONS
Typical at 25 'C, ± 15V dc and + 5V dc supplies, unless otherwise
noted.
ANALOG INPUT
Input Voltage Range ............
Inpullm~edance ...............
Input 0 set Voltage, max. 1 •••••••
Input Offset Voltage Drift .........
Input Bias Current, max •.........

+ 11.5V
-10 ' O{J
±2 mV
20 ",V/oC
SO nA

DIGITAL INPUTS

..

Logic Level High, Vin ("1"), min.
Logic Level Low, Vin ("0"), max. "
High Level Input Current .........
Low Level Input Current .........
Inverter Input Delay, max.' .......

1. An external hold capacitor may be added from Pin 5 (EXT.
CAP. HIGH) to Pin 14 (EXT. CAP. LOW). For best results,
this should be a good quality capacitor with very high insulation resistance and low dielectric absorption; such as MOS,
polystyrene or polypropylene type capacitors. Hold mode
droop and sample to hold offset will decrease proportionately
with the size of this capacitor, and acquisition time will increase proportionately. For lowest hold mode droop, a guard
ring connected to the output should be put around EXT.
CAP. HIGH Pin (Pin 5), as shown in the circuit board layout.
2. Fast rise time logic signals can cause hold errors by feeding
externally into the analog input at the same time the amplifier
is put into the hold mode. To minimize this, the circuit board
layout should keep logic lines as far as possible from the
analog input. Grounded guarding traces may also be used
around the input line, especially if it is driven from a high impedance source.

+2V
+0.8V
60~

-0.8 rnA
30 nsec.

OUTPUT

PERFORMANCE CURVES

Output Voltage Range ...........
Output Current, S.C. Protected ...
Output Impedance ..............

+ 11.5V
-5 rnA
O.SO

ACQUISITION TIME

PERFORMANCE
~

VIN

Accuracy ......•..........•...
Gain ........................ :
Gain Error, max.

3 •••••••••••••••

Sample to Hold Offset, max." ••...
Hold Mode Feedthrough .........
Hold Mode Droop, max •..........
Output NOise, Hold Modes .......•
Power Supply Rejection Ratio min.

0.01%
+ 1 VN
0.01%
2.S mV
0.01%
0.2 mV/msec.
8.5 ",V RMS
80 dB

TJ

OTO ± lOV
~

25°C

100 I------~::.:..:.~,,..---'~

DYNAMIC CHARACTERISTICS
Acquisition Time, 10V to 0.1 0;& ••••
10VtoO.Ol0f0 '"
20VtoO.l0f0 ....
20V to 0.01 Ofo •••
Aperture Delay Time ............
Small Signal Bandwidth, - 3 dB ...

S ",sec.
6 f"Sec.
1 ",sec.
8 ",sec.
200 nsec.
4 MHz

1000 L-_ _ _ _.L._ _ _ _---l

0.01

OPEN

0.1

EXTERNAL HOLD CAPACITOR ",F)

POWER REQUIREMENTS
Analog Supply Range ...........

±5V de to ±18V de

Su~~~~~~~g:: ~.a.t~~ ...........

APERTURE TIME

± 15V de at 6.5 rnA max.
Logic Supply .................. + SV de ± 0.25V at 9 rnA max.

PHYSICAL/ENVIRONMENTAL
Operating Temperature Range: MC
MM
Storage Temperature Range ......
Package ......................

O°C to + lO°C
-5SoC to + 12SoC
-65°C to +lS0'C
16 pin hermetically sealed
ceramic DIP

450 f-vl

~lv_l~lL

400

O

350

g
w

::;;

>=

300

NEGATIVE
250 f- INPUT
STEP

200

FOOTNOTES:

150

1. Adjustable to zero
2. This specification refers to the time delay between the invert input (Pin 8) and
invert output (Pin 7).

100

3.RL~10kn

4. VOlJ1 = OV
5. 10 Hz to 100 kHz

I-r r""mv

50

..,.

V
V
a

lVI~~
~

1/

...........

1
::::F"'i
POSITIVE
INPUT STEP

1 1
1 T

V

0
-50 -25

I I
I I

25

50

75100125150

JUNCTION TEMPERATURE 1°C)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

3-33

SHM-9

DYNAMIC SAMPLING ERROR

"HOLD" SETTLING TIME

1.8

V+;V-;15V
SEnU NG TO 1mV

1.6
1.4

;;;

-"

1.2

w

1

;:::

0.8

::;

0.6
0.4
0.2

--

....

.......

./

~

o
-50 -25 0

25

50

0.1

75 100 125150

10

100

1000

INPUT SLEW RATE (V/ms)

JUNCTION TEMPERATURE ("C)

PHASE AND GAIN
(INPUT TO OUTPUT, SMALL SIGNAL)

HOLD STEP

OUTPUT DROOP RATE
10"r----r----.----,----~

2l
V+ ; V- ; 15V
Tj ; 25"C

Z
"0

~

-;

o

o
c:

-;
"0

~

"0

I

10-1

S

en

Il.

~

I-

!:;

())

0.2

0

'1

...J

0
I

10-3

m

10 - 4 '-----'-------'------'--"'--'

r'

~

lOOK

w

10-2

en
m
o

10K

"I"
"

0;-

6w

l>

lK

2

0.02

0.002

10M

1M

EXTERNAL HOLD CAPACITOR

FREOUENCY (Hz)

EXTERNAL HOLD CAPACITOR

FEEDTHROUGH REJECTION RATIO
(HOLD MODE)

HOLD STEP INPUT VOLTAGE

GAIN ERROR
0;-

S

-130
0;-

+8

S

+6

0

:::>

+4

::;
Il.
::;

+2

w

I-

«

Il.

w

-2
-4

0

...J

0
I

-120
.....

~; ~OO°C

0 t--lj; 25";;-""

en

I-

-6

I

-110

10 -100

:---....

0

-90

«
II:

-80

;:::

....... 1--

Tj; -55"C-

I I

r-....

r--

~

Ch

I

- 5

0

-50

5

INPUT VOLTAGE (V)

10

15

0Ol jF

~
o

10

100

lK

10K lOOK 1M

FREOUENCY (Hz)

0.6
0.4

:::>

0.2

~

o

I-

I

-0.2

Cl

-0.4

w

"

1
0.8

>

o

.'\

I I
I I

-60
I

'I

I"-

Ch ; OPEN

-70

-8

w

Il.

~

...........
...........

~

-15 -10

3·34

v+ ; v - ; 15V
i VIN; 10V p.£""
V7,B ; 0
Tj ; 25"C
Ch ; O.l.F

I

~

~
~

Il.

~

Tj ; 25"C
RL; lOKI.
SAMPLE MODE

....

.....

-- -

""'-

-0.6
-0.8
-1

-15 -10

-5

o

5

10

15

INPUT VOLTAGE (V)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

SHM-9
PERFORMANCE CURVES
OUTPUT SHORT CIRCUIT CURRENT

INPUT BIAS CURRENT

20
18

25
20
~

.s

~

10

§.

r-..

>-

z

w

>-

I'-.... r--...

a:
a:

:>
0

.......

~

-5

12

z

10
8

:>

.....

0

I'-....

-10

140

14

a:
a:

w

160

I\..

16

15

-

"

r-

~;;

SOURCING

1--...
1'-

-r-

SINKING

2

-15
-50-25

OUTPUT NOISE

25

.s

80

en

60

\-HOLD" MODE

..... t--..,.

0z

'\
...........

40
20

25

50

75 100 125150

""""=

10

100

JUNCTION TEMPERATURE (0C)

JUNCTION TEMPERATURE (0C)

"

SAMPLE MODE

0

-50-25 0

50 75 100125150

\

100

w

o
0

\

120

lK

10K

lOOK

FREQUENCY (Hz)

POWER SUPPLY REJECTION
160
140

iii

:g
0

;::
«
a:

120
100

z

80

;::

80

0
0

w

iil
II:

J

CONNECTIONS

Tj ; 25°C
V + ; V - ; 15V
VOUT; OV

-

SINGLE LINE CONTROL

-..........:::,
_NEGATI~

"""

SUPPLY

40
20
0
100

lK

POSITIVE_
r-(UPPLY

10K

SAMPLE
CONTROL
INPUT

~

!liH
SAMPLE

SHM·9

~.

-.....;:
1M

lOOK

FREQUENCY (Hz)

+ 5V (}--+-{f61

CIRCUIT BOARD LAYOUT
GUARD
RING

SAMPLE
CONTROL
INPUT

S/H
HOLD

SHM·9

~

16 GUARD COMMON

14

C HOLD LO

~ POWER COMMON

+5V

~ PR INPUT

OUTPUT

I

~
INVERTOUT
INVERTIN

~

CKINPUT

~ +5VDC

~ _________ ~ IT INPUT

"ADDITIONAL EXTERNAL CAP, IF USED

The SHM-9 sample/hold switch can be controlled with one hold
command input. The above diagrams give the circuit connection
for either a Sample/Hold or a Sample/Hold control input. When
using the SHM-9 with an A/D converter, the converters' E.O.C.
(STATUS) output can be used to control the SHM-9.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-35

•

SHM-9
APPLICATION
AID INTERFACE
SHM·9

AID

+ 15V

SIG
IN
GUARD
COM.

SIGNAL INPUT

-15V

roc

SIG
OUT

OUT

C HOLD
HI
SIG
OUT
INV.
OUT

EOCOUT

Jl...
+5V

START/
CONVERT

START IN

ANALOG IN

TIMING DIAGRAM

START/CONVERT

~L

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

I
I

I
I

~

S/H STATE

;'-100 TO 400 NSEC

--.lJ

HOLD

~

-+l

i+-- 100 TO 400 NSEC

bE

The SHM·9 is easily interfaced with most A/D converters. The diagram shows a typical connection in which the SHM-9 is controlled by the Start/Convert and EOC (Status) signals of the A/D converter. The Start/Convert signal puts the SHM-9 into the
hold mode. The intemal inverter allows the designer to use either a positive or negative Start/Convert signal. When the E.O.C.
signal goes high and the A/D begins its conversion cycle, the SHM-9 is already providing a stable analog input to the A/D's
comparator. When the E.O.C. goes low, signaling the end of conversion, the SHM-9 is switched back to the sample mode.

ORDERING INFORMATION
MODEL NO.

OPERATING
TEMP. RANGE

SHM-9MC
SHM-9MM

O°C to + 70°C
-55°C to + 125°C

For high reliability devices, contact DATEL.

3-36

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

SHM·91
PRECISION DUAL
SAMPLE-AND-HOLD

FEATURES
+15 V de

• Contains two precision sample/hold
amplifiers
• Designed for use with 12- or 14-bit
A/D converters
• Fast acquisition time (2 "Sec. to
to.002 %)
• No external components required
• Wide temperature range (-55 ·C to
+125 ·C available)
• 24-pin dual in-line package
• Multiplexed inputs and outputs for
application versatility

'---......-+v

•

BEN
1B

GENERAL DESCRIPTION

2B

DATEl's SHM-91 is a high performance/
high resolution dual sample/hold amplifier.
This hybrid device is designed for multichannel analog signal processing applications with 12- to 14-bit accuracy requirements. Typical applications for this device
would demand high speed and high resolution. The SHM-91 offers both of these
features at a low cost.

BADDR
B SAMPLE

Figure 1. SHM-91 Simplified Block Diagram

The SH M-91 consists of two separate sample/hold amplifiers, each independently
controlled to allow flexibility when
implementing a system design. Each half
consists of a two-channel input multiplexer
and a sample/hold amplifier. The output of
each sample/hold is available directly or
through a multiplexed output.

INPUT/OUTPUT
CONNECTIONS

Other features of the SHM-91 include a
t 10V dc input range, a fixed gain of 1, and
a maximum gain temperature coefficient of
10ppm/ °C. The SHM-91 is actively laser
trimmed at the factory for low initial offset
and sample-to-hold offset. By deSign, the
SHM-91 operates without external adjustment circuits.

L..,oooo

MAX---l
120,3) ~

1~I

I

T
K

13,

112

,

DOT ON TOP
PIN 1

f

0018

KOVAR

,
,
,
,
,
,
,
,
,
REFERENCES

1

~

jO.190(4,9)MAX

O''''MINT
13.81
-,--0010

The SHM-91 also features a maximum
acquisition time of 2 microseconds for a
10V dc input step to 0.002%. Aperature
uncertainty is typically 300 picoseconds
and pedestal error will not exceed t 1 mV.
Power requirements is t15V dc with a
maximum power consumption of 900 mW.
The SHM-91 is available in two models for
operation over the commercial O·C to
+70 oC and military -55°C to +125°C
operating temperature ranges. All models
are cased in a 24-pin, hermetically-sealed
ceramic package.

PIN

MECHANICAL DIMENSIONS
INCHES (MM)

-

BOTTOM
VIEW

"
1_

,
,
,
,
,
,
,
,
,

1

11

1
11 SPACES
ATO 100
EA 12,51

33,3
".om,

,
24,

0600 _ -1
1-115.21)

1200

011

--0

1_
1

0 '00
12 ,51

NOTE: PINS HAVE 0.025 INCH STANDOFF FAOM CASE,

1
2
3
4
5
6
7
8
9
10

± 0.01"

12
13
14
15
16
17
18
19
20
21
22
23
24

SIGNAL
AOUT
GROUND
1A
2A
+15V de
-15V de
AEN
AADDR
A SAMPLE
NO CONNECTION
MUXOUT
GROUND
BOUT
GROUND
1B
28
+15V de
-15V de
8 EN
BADDR
8 SAMPLE
NO CONNECTION
MUXOUT
GROUND

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

3-37

SHM .. 91
FUNCTIONAL SPECIFICATIONS (continued)

ABSOLUTE MAXIMUM RATINGS
Positive Supply (Pins 5, 17) ...
Negative Supply (Pins 6, 18) ..
Digital Input Voltages
Address, Sample (Pins 8, 9,
20,21) .................. .
Mux. Enable (Pins 7, 19)
Analog Input Voltage.

-0.5V dc to +18V dc
+0.5V dc to -18V dc

-0.5V dc to +7V dc
-18V dc to +18V dc
±15V dc

FUNCTIONAL SPECIFICATIONS
The following specifications apply over the full operating
temperature range and power supply range unless otherwise
specified. For test aspects, contact the factory.
DESCRIPTION

MIN.

TYPICAL

MAX.

UNITS

ANALOG INPUTS
Input Voltage Range.
Input Impedance
Input Capacitance
Input Bias Current

-

-

-

-

30
1.5

2.4

-

-

-

0.8
1
1

±10
1M

-

-

V
Ohm
pf
pA

LOGIC INPUTS (TTL/CMOS
Logic
Logic
Logic
Logic

1 voltage
0 voltage
1 current
0 current

.
..
..
..

-

-

V
V
pA
pA

ANALOG OUTPUTS
Direct Output (pins I, 13)
Output Voltage Range .
Output Current.
Output Impedance.
Mux. Output (pins II, 23)
Output Voltage Range .
Output Current ..
Output Impedance.
OFF Output Leakage .
OFF Output Capacitance.
Output Switch Delay.

-

-

±10
to
-

-

±10
10

-

-

50

150
1
20
500

-

-

1

-

2

V
mA
Ohm
V
mA
Ohms
pA

pf
nS

PERFORMANCE
Gain (1) .
Gain Error (1)
Gain TempcD
Linearity Error (1) .
Linearity Tempco ..
Initial Offset Voltage (2)
Offset TempcD., Hold Mode
Crosstalk, channel-tochannel ..
Offset TempcD. Tracking
(Avs. B)
Gain Tracking (A vs. B) .
Gain Tracking Tempco ..

-

+1
1

-

%
ppm/DC
%FSR
ppm/DC
mV
!'VloC

-

20

±0.02
10
0.003
±1
±1
50

-90

-

-

dB

-

±10
-

±20
±50
+0.5

!'VloC
ppm
ppm/DC

-

45

1
-

Mhz
V/p.S

-

-

TRACK MODE DYNAMICS
Frequency Response
Small Signal (-3dB).
Slew Rate ..............

3-38

DESCRIPTION

MIN. TYPICAL MAX. UNITS

TRACK-TO-HOLD SWITCHING
Aperture Delay Time ...
Aperture Uncertainty (JittEir) ..
Offset Step (2) ..
Settling Time to +2mV

-

15
300
-

1.000
±1
600

nS
pS
mV
nS

-

-

5
20
100

-

!,VI!,S
/-NlJ.lS
!,VlJ.lS
dB

-

2
1.5

J.IS
J.IS

±145
-60

±15
-

±15.5
-

Vdc
dB

-

-

700

30
30
900

mA
mA
mW

-

0.015
0.035

-

°C/mW
°C/mW

HOLD MODE DYNAMICS
Droop Rate
At +25 °C.
At +85 °C .
At +125 °C .
Feedthrough Rejection.

-

-90

HOLD-TO-TRACK DYNAMICS
Acquistion Time
10 Volt Step to ±0.2 mV
10 Volt Step to ± 1 mV .

-

POWER SUPPLY REQUIREMENTS
Supply Voltage Range ± V .
Power Supply Rej. Ratio.
Current Drains
+15V dc
-15V dc
Power Dissipation .
PHYSICAl/ENVIRONMENTAL
Thermal Resistance
Junction-to-Case.
Case-to-Ambient .

Operating Temperature Range (3)
DoC to +70 °C (ambient)
SHM-91MC
SHM-91MM
-55°C to + 110°C (ambient)
Storage Temp. Range
-55°C to +125°C
Package Type
24-pin. hermetically sealed
ceramic DIP
Refer to the Mechanical
Package Dimensions
Dimensions
FOOTNOTES:
1- Specified at +25 DC.
2- Tested at +25 °C with input source impedance of 50 ohms.
3- Free air.

TECHNICAL NOTES
1. All ground pins (2, 12, 14, 24) should be tied together and
connected to system analog ground as close to the package as possible. It is recommended to use a ground plane
under the device and solder all four ground pins directly to
it. The power supply pins (5, 6, 17, 18) should be bypassed
to analog ground with .01 ,..F ceramic capacitors located as
close to the pins as possible. In certain critical applications,
additional bypass precautions using 0.1 or 1.0,..F tantalum
capacitors are suggested.
2. A logic "I" on the sample pins (9, 21) will put this device in
the sample mode. In this mode, the device acts as an unity
gain amplifier and its output will track its input. A logic "0"
on the sample pins (9, 21) will put the device in the hold
mode, and the output will be held constant at the last input
level present before the hold command was given.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

SHM·91
When ADDR goes high, it switches the sampled channel to
1A. On the next occurence of a sample pulse, the output will
reflect any amplitude change occuring on 1A during the
sampling period. The subsequent hold state signal is at
whatever level the 1A input was at when the sample pulse
ended.

3. Care should be taken when using the mul!i£lexer output pins
(11,23) that the A EN (pin 7) and the B EN (pin 19) are not
active (logic 0) at the same time. This condition could possibly damage the device.
4. The output of the SHM-91 should drive a high impedance
receiver to minimize voltage divider losses. The receiver
input impedance should be 100K ohms or greater when using the direct outputs from the amplifiers (pins 1 and 13). The
receiver input impedance should be 2.5 M ohms or greater
when using the multiplexer outputs (pins 11 and 23).

+15V de

5. The SHM-91 should not be left in the hold mode for long periods of time. It should be left in the sample mode when long
or indeterminate periods of time are involved. If left in the
hold mode for several seconds, the output will continue to
"droop" toward the power supply Voltage. Eventually the output amplifier will saturate. The unit will require longer than
the specified acquistion time to acquire a signal when the
output amplifiers are saturated.

5

7
AEN

....

3

/

lA

1
AOUT

6. See charts in Figures 2b and 3b for input selection.

4

SHM-91
2A

2

Fi

APPLICATIONS
Single Channel Application
Figure 2a shows how to use one of the SH M-91's sample-andholds with multiplexed inputs. The output reflects the sampled
input. The timing diagram, Figure 2b, shows that with the
ADDR line low, the leading edge of the SAMPLE line pulse
causes the input on 2A to be passed on to the output. The output reflects any amplitude change on 2A that occurs during
the pulse width of the sample pulse. The falling edge of the
sample pulse causes the output to hold the current 2A input
level.

I

I

~

-

8

=

"7" See
Technical Note 1

6

AADDR
A SAMPLE

-15V de
Figure 2a. SHM-91 Single Sample-and-Hold Configuration

I I
II

o-=C\~C\I

lA

9

I

I

I

I~

.

II

(\~{

\JlI II \ J 1 J
J \ = {I II \ J
I I

I
I

\LJ
I

II
II
1.1
I~I
~II~II

~II~II

2A

SAMP

L

ADDR

OUT

ADDR

INPUT
CHANNEL

o

2

1

Figure 2b. Typical Timing for Single Channel Sampling

1

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

3-39

SHM·91

2A

2B

~II

~

SAMP

MUXSEL

~

II

o~ -----1H
0- -----01-

H.-I________

I
I
I
I
I
I
+

I
I
I
I
I
I
1

I

I

:
I
I
I

:
I
I
I

----I

::

BOUT

0-

MUXOUT

0--

I
I
I
I

:
I
I
I

::

:
I

INPUT
CHANNEL

o

2

I

I

I

I

I

I

I

I

I

I

Figure 3b. SHM-91 Simultaneous Sample-and-Hold Timing

1
Simultaneous Sample-and-Hold

SHM-91
2A
AADR

:
I
I
I

I

The SHM·91 is ideally suited for simultaneous sample·andhold applications. Figure 3a represents a typical connection
diagram along with a timing diagram (Figure 3b) of the
SHM-91 's operation. In a simultaneous sample-and-hold application, data mustbe taken from all analog inputs at precisely the same time.

17

20

I

l-

I

+15 V dc

16

I

I
I

:: :
:
-----I-lti----t:-------+--c=t-+~i=----l==~i'--

ADDR
1

9

I
I
I
I
I
I
I

------tt=-i:--+---f------l:~j===i====f:
-I I
I I
I

::

8

I
I
I
I
I
I
I

o--------+r~!----+_------~--~r-~r!~~~~~~~=====~!=~

AOUT

4

II~

II

11
MUX
23
OUT
2
12
14
24

A SAMPLE
2B
BADR

All SHM-91's in the application are given the hold command
at the same time. The internal multiplexer then sequentially
switches between sample-and-hold outputs while an AID converter would digitize the outputs. A high-impedance buffer
amplifier would be required between the multiplexer and the
AID converter.

21

18 6

See Technical
Note 1

MUXSEL

Figure 3a. SHM-91 Simultaneous Sample-and-Hold
Configuration

ORDERING INFORMATION
MODEL

TEMPERATURE RANGE

SHM-91-MC
SHM-91-MM

O°C to +70°C
-55°C to + 125°C

For high reliability versions of the SHM-91, contact DATEL.

3-40

DATEL, Inc. 11 Cabot Boulevard. Mansfield. MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

SHM-HU
Ultra-Fast, 0.10/0
Micro-electronic
Sample/Hold
FEATURES
•
•
•
•

25 Nanoseconds acquisition time
50 MHz bandwidth
10 Picoseconds aperture uncertainty
Up to 8-bit accuracy
• ± 2.5V Input range

+BIAS 1

+!W de

+ BIAS 2

GENERAL DESCRIPTION
The SHM-HU is an ultra high speed
sample-hold capable of video speed signal
processing. The SHM-HU acquires a fullscale 5V input change in just 25 nanoseconds and features a 10 picoseconds
aperture uncertainty time. Bandwidth is 50
MHz and the slew rate is 200
Vlmicroseconds.
Through the use of thin film hybrid construction, this ultra high speed circuit is
contained in a miniature 24-pin ceramic
package. A 53 picofarad MOS hold capacitor is incorporated inside the package and
provision is made for externally added
capacitance when
necessary. The
sample-hold requires four external resistors and an lH0033 fast buffer amplifier
for completion. The circuit is zeroed byadjustment of the lH0033 amplifier.
Other features of this unit include a ± 2.5V
input/output voltage range and a fixed gain
of 0.955. The sampling switch is controlled
by a complementary series 10,000 ECl input. An ECl differential line driver can be
conveniently used for the sample control
inputs.
Power requirements are±15V dc at 60 rnA
and ±5V dc at 70 rnA. There are three basic
models covering two operating temperature ranges, 0 to +70 0 C and -55 to +1 00 0 C.

•

I

I

_____ .J

-BIAS 1

-BIAS 2

MECHANICAL DIMENSIONS
INCHES (MM)
La.BOO MAx~1
]-

(20.3)

I

_--.L _ _

~c=:J
-l,..".,.._ ",..J
(J.81

-,-

KOVAR

131

112
I
I
I
I
I

DOT ON TOP

,1200

I
I

I

BOnOM
VIEW

11 SPACES

I
I
I

ATC.1oo
EA (2,5)

I

I
I

I
I

I
11

1., " "

I

I

INPUT/OUTPUT
CONNECTIONS
PIN
1
3

6

0010",0018

I

REFERENCES
PIN 1

0.190(4,9)

_5Vdc

33.3

01~

I
24 I

7
9
10
12
14
15

16
18
19
20
22
23

FUNCTION
SAMPLE CONTROL
SAMPLE CONTROL
-BIAS 1
-BIAS 2
-5V POWER
GROUND
+5V POWER
GROUND
GROUND
GROUND
OUTPUT
+5VPOWEA

+ BIAS 2
INPUT
+ BIAS 1

NOTE: ALL OTHER PINS ARE
NO CONNECTION

--0

1_ 0600 ---.l 1_ 0 100

I

115.21

-]

t

12.5)

NOTE: PINS HAVE 0.025 INCH STANDOFf FROM CASE, ±O.Ol"

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-41

SHM-HU
ABSOLUTE MAXIMUM RATINGS
Power Supplies, Pins 9-19 . . . . ..
Analog Input Voltage, Pin 22 . . ..
Sample Inputs, Pins 1 & 3. . . . . ..
Current, Pins 6, 7, 20, 23, .......

TECHNICAL NOTES
± 6V
± SV
± SV Differential
50 mA

1. It is recommended that the ± 5V supplies of the SHM-HU be
bypassed with 0.1 "F ceramic capaCitors as close as possible
to pins 9 and 19. The ± 15V supplies to the lH0033 should
be bypassed with the same value capaCitors.

2. It is essential that the output lead from pin 18 to pin 5 of the

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ± lSV and ±5V supplies with external LH0033
Buffer Amplifier unless otherwise noted.
INPUTS
Input Voltage Range, Min .......
Input Bias Current. ............
Maximum Source Impedance ...
Input Impedance ..............
Sample Control Inputs' ........

±2.5V
2S pA
51 Ohms
10. Ohms
Differential ECl 10,000 Positive
Pulse on Pin 1 and Negative
Pulse on Pin 3 gives Sample
Mode

lH0033 be kept as short and direct as possible. Also, the
complementary ECl driver should be as close as possible to
pins 1 and 3 to minimize leadlengths to these pins.
3. With model SHM-HUMC the lH0033C should be used, and with
model SHM-HUMM, model lH0033 should be used.
4. An external hold capacitor may be added from pin 18 to pin
15. This capaCitor should be an MOS or polystyrene type.
Hold mode Droop and sample-to-hold offset error will
decrease proportionately with the size of this capacitor and
acquisition time will increase proportionately.

CONNECTION DIAGRAM
OUTPUT'

+15V

+15V

+5V
+15V

Output Voltage Range, Min ...... ±2.SV
Output Current . . .. .. . . .. . . . .. ± 10 rnA
Output Impedance ............ 6 Ohms
PERFORMANCE

11 __ ~) OUTPUT

9

Accuracy ....................
Gain ........................
Output Offset Voltage',
Sample Mode ...............
Output Offset Voltage Drift ......
Sample to Hold Offset Error .....
Hold Mode Droop .............
Hold Mode Feedthrough ........

0.1 %
+0.995

7

6

10

o.tl

!~~~F-

± 100 mV max.
± 100 "V/·C max.
± 100 mV max.
50 "V/,,$ec.
0.02%

zWc>

ADJ.

-15V

-15V

1

-15V

-sv

DYNAMIC RESPONSE
Acquisition Time,
5V Step to 0.2% ............
Bandwidth, - 3 dB,
Sample Mode ...............
Slew Rate ...................
Aperture Delay Time. . . . . . . . . ..
Aperture Uncertainty Time. . . . ..

25 nsec.
50 MHz
200V/pllec.
6 nsec.
10 psec.

POWER REQUIREMENTS3
Power Supply Voltage ......... ± 15V dc ±0.75V at 60 rnA
± 5V dc ± 0.25V at 10 rnA
PHYSICAUENVIRONMENTAL
Operating Temperature Ranges
SHM·HUMC ..................
SHM-HUMM ..................
Storage Temperature Range ....
Package Type ................
Pins ........................
Weight ......................

a to

+ 10·C
- 55 to + 100·C
-65 to + 150·C
24 Pin Ceramic
0.010 x 0.018 inch Kovar
0.2 ounces (6 grams)

FOOTNOTES:
1. Output is from LH0033 amplifier and is not short circuit proof.

2. Output offset voltage adjustable to zero by LH0033 offset adjustment.
3. ± 12V supplies can be used if the 360 ohm resistors at the Bias 1 pins are

ORDERING INFORMATION
MODEL NO.

OPERATING
TEMP. RANGE

SHM·HUMC
SHM·HUMM

a to + 10·C
-55 to +100·C

ACCESSORIES
Part Number

Description

DllS·3 (24·Pin Socket)
TP100 (100 ohms)

Mating Socket
Trimming Potentiometer

changed to 240 ohms and the 240 ohm resistors at the Bias 2 pins are changed

to 160 ohms.
4. The SHM·HU can be driven by TTL logic input by biasing SAMPLE CONTROL
input to + 1.2V and driving the SAMPLE CONTROL with a positive pulse for

For high reliability devices, contact DATEl.

sampling mode.

3-42

DATEl, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEl (508) 339-3000fTlX 174388/FAX (508) 339-6356

SHM·IC·1
Monolithic Sample·Hold

Features
•
•
•
•
•
•

5 Microseconds acquisition to 0.01%
50 Nanoseconds aperture
Inverting or non inverting
2 MHz Bandwidth
0.01 % Feedthrough
14-pin DIP package

-15V de + 15V de

GENERAL DESCRIPTION

HIGH GAIN
OIFF. INPUT
AMPLIFIER

The SHM-IC-1 is a new monolithic integrated circuit sample and hold with excellent performance features. It is a selfcontained device requiring only an external holding capacitor, the value of which
can be chosen by the user to achieve his
desired speed and accuracy requirement.
The unit consists of a high gain differential
input amplifier, a digitally controlled electronic switch, and a high input impedance
buffer amplifier. The SHM-IC-1 operates in
a closed loop configuration, either inverting or noninverting, with accuracy and
speed determined by the input amplifier
characteristics and the value of the holding capacitor. The electronic switch is controlled by a DTUTTL compatible logic
input.
The most common configuration for the
SHM-IC-1 is a unity gain, noninverting
sample and hold. In this configuration the
device has a ± 10V input and output range
with 10 ohms input impedance. Specifications are given for this unit with two different values of holding capacitor, 0.001
I'F and 0.01 I'F. The 0.001 I'F capacitor
gives a 4 microsecond acquisition time to
0.1 % for a 10V change, a 2 MHz tracking
bandwidth and 50 mV/miliisecond maximum hold mode droop. The 0.01 I'F
capacitor gives a 10 microsecond acquisition time, 1 MHz tracking bandwidth, and 5
mV/miliisecond maximum droop. Characteristics for other values of holding
capacitor can be determined from graphs
which are shown. The SHM-IC-1 can also
be configured as either an inverting or
noninverting sample and hold with gain by
the use of two external resistors.
This device is housed in a 14-pin hermetically sealed dual-in-line package. Operating temperature range is O°C to + 70°C
for the SHM-IC-1 and - 55°C to + 125°C
for the SHM-IC-1 M.

ONO

ELECTRONIC
SWITCH

,,
,

•

1'"--------,

,

,

HIGH Z
OUTPUT BUFFER

MECHANICAL DIMENSIONS
INCHES (MM)
14

13 12

11

10

OATEL
SHM·IC·l

9

INPUT/OUTPUT
CONNECTIONS

8

PIN

FUNCTION

1
2
3
4
5
6
7
8
9
10
11
12
13
14

-IN
+ IN
OFFSET TRIM
OFFSET TRIM
-15VDC POWER
NO CONNECTION
OUTPUT
NO CONNECTION
+15VDC POWER
GUARD
HOLD CAPACITOR (CHI
GUARD
GROUND
DIGITAL CONTROL

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-43

SHM-IC-1
FUNCTIONAL SPECIFICATIONS

TECHNICAL NOTES

Typical at 25 ·C. ± 15V dc Supplies. unless otherwise noted.
INPUT AMPLIFIER SPECIFICATIONS
DC Gain. volts/volt' ....••.....•••. SOK, 25K minimum
Bias Current ..................... 50 nA, 200 nA maximum
Offset Current .....•......•...... 10 nA, 50 nA maximum
Offset Voltage (adjustable to zero) ••• 3 mY, 6 mV maximum
Offset Voltage Drift ....••.....•.•• 20 "Vioe
Common Mode Voltage Range .•.... ± 10V minimum
Common Mode Rejection Ratio •••.• 74 dB minimum
Power Supply Rejection ••.....••.• ± 30 "V/%maximum
Gain Bandwidth Product ........... 2 MHz
GENERAL SPECIFICATIONS. SAMPLE & HOLD. G

= +1

Input Voltage Range •.•.........•• ± 10V minimum
Inputlmpedance ••....••.....•••• 10. ohms
Output Voltage Range .•.•....••••• ± 10V minimum
Output Current. S.C. protected .•... ± 10 mA minimum
Outputlmpedance ................ 0.2 ohm
Aperture Delay •.....••......•...• 50 nanoseconds
Aperture Uncertainty •..••.....•••• S nanoseconds
Gain Error. sampling mode •....•••• 0.01 % maximum
Hold Mode Noise .......•......... 350 p.V RMS
Digital Input. Sample Mode.
DTL/TTL ••...•.•.....•.......• 0 to +0.8Vat -0.8 mA
Hold Mode. DTLlTTL2 ....•........ + 2.0 to + 5.5V at + 20 p.A
SAMPLE & HOLD. G

= + 1. CH = 0.001 "F

Acquisition Time. 10V to 0.1% •..... 4 microseconds
Acquisition Time. 1OV to 0.01 % .•••• 5 microseconds
Bandwidth. small signal. sampling ... 2.0 MHz
Slew Rate .••.................... 5 V/microseconds
Hold Mode Voltage Droop .••....... 50 mV/miliisecond maximum
Hold Mode Feedthrough •......••.. 0.01 % maximum
Sample-to·Hold Offset Error.
VIN 0 ...................••.. 20 mV maximum
Sample·to·Hold Gain Error.
± 10V .••••...•........•. 0.05% maximum of output
VIN
Sample·to·Hold Nonlinearity Error •.. 0.01 % maximum of output

=
=

SAMPLE & HOLD. G

= +1. CH = 0.01 p.F

Acquisition Time. 10V to 0.1 % ...... 10 microseconds
AcquisitionTime.l0VtoO.Ol% ..... 12 microseconds
Bandwidth, small signal. sampling ... 1.0 MHz
Slew Rate ......•.............••. 3 V/microseconds
Hold Mode Voltage Droop .......... 5 mV/millisecond maximum
Hold Mode Feedthrough ........... 0.002% maximum
Sample-to·Hold Offset Error.
VIN 0 .•...•••............... 2 mV maximum
Sample·to·Hold Gain Error.
VIN
± 10V •.................. 0.005% maximum
Sample·to·Hold Nonlinearity
Error .•.•...•••....•.......... 0.001% maximum

=
=

POWER REQUIREMENTS
Power Supply Voltage .•......•....

± 15V dc at 5.5

mA maximum

The most commonly used sample and hold configuration for the
SHM·IC-l is the noninverting unity gain circuit. This gives a high
input impedance of 108 ohms, and the output voltage in the
sample module follows the input. Specifications are given for
this configuration for two values of CH • 0.001 /LF and 0.01 /LF.
The 0.001 /LF capacitor gives excellent speed (4 microseconds
acquisition) with good hold mode voltage droop (only 50
mV/millisecond maximum). For even better speed. a 100 pF
capacitor may be used to give an acquisition time of only 2
microseconds. The hold mode droop. however. increases by an
order of magnitude to 500 mV/millisecond, and the sample·to·
hold errors also increase. For excellent accuracy a 0.01 /LF
capacitor should be used, giving an acquiSition time of 10
microseconds, and a hold mode droop of only 5 mV/miliisecond
maximum_ Even larger values of holding capacitor can be used
with proportionate increases in accuracy but slower speed. The
application graphs show the results for the different values.
For best results, CH should be a good quality capacitor with very
high insulation resistance and low dielectric absorption. For
temperatures up to + 85°C polystyrene type capaCitors are
recommended. It is also recommended for lowest hold mode
droop that a guard ring be used around the CH terminal (pin 11)
in the circuit board layout as shown on the last page. This is
done to prevent leakage to other conductors on the circuit board
due to board leakage and contamination_ If a large value
polystyrene capacitor is used, such as 1 /LF. hold mode droop as
low as 20 /LV/seconds (typical) can be achieved with an acquisi·
tion time of about 3 milliseconds.
Three error contributions are specified for sample·to·hold errors:
offset error, gain error. and nonlinearity error. These sampling
errors are caused by a small amount of charge being dumped to
or from the holding capaCitor by the sampling switch and are
reduced by a larger value of CH • It is possible to compensate for
these errors by changing the gain and offset elsewhere in the
external circuitry for the noninverting unity gain case. For thlj! in·
verting case, the gain can be accomplished by adjusting the ex·
ternal resistor values and an offset can be applied to pin 2 of the
input amplifier. When this external compensation is used, the
output will be in error during sampling, but will be accurate in the
hold mode. Only the nonlinearity error will remain of the sample·
to·hold errors. The offset adjustment of the input amplifiers
should be used only to zero the device in the sample mode.
In the inverting gain of one operating mode. the feedback and
input resistors should be carefully matched or trimmed to give
the desired gain of one. In general, the operating parameters
are the same as in the noninverting unity gain configuration ex·
cept that the sampling bandwidth is reduced by a factor of two.
Likewise. for higher gain configurations the sampling bandwidth
is proportionately reduced.

PHYSICALIENVIRONMENTAL
Operating Temperature
ooe to 70°C
Range, SHM·IC-l ...........•••.
Operating Temperature
Range.SHM·IC-1M .............. -55°C to +125°e
Storage Temperature Range .••..... - 65°C to + 150°C
Package, hermetically sealed
ceramic DIP ................... TO-116
FOOTNOTES:

1. 40K and 20K respectively at + 125°C for SHM-IC-1M.
2. +3.0 to +5.5V at -55°C for SHM-IC-1M.

3-44

CATEl. Inc. 11 Cabot Boulevard. Mansfield. MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

SHM-IC-1

NON INVERTING SAMPLE-HOLD, UNITY GAIN
GAIN
/ " " - v )"---.--~

OUTPUT

=

+1

The 100K ohm offset trimming potentiometer should be a 100
ppm/oC cermet 15 turn type. These are available from DATEL.
To zero, ground input (pin 2) and digital control (pin 14) and
adjust 100K offset trim for zero output (pin 7).

INPUT~~...---.

NONINVERTING SAMPLE-HOLD
GAIN

___->.'J---.--- OUTPUT

=

1 +

~2
R1

Bandwidth decreases proportionately with gain. R3 is equal to
the parallel combination of R1 and R2 and is used to compensate for voltage offset caused by input bias current. R1 and R2
should be 100 ppm/oC metal film type resistors.

+ 15V de

INVERTING SAMPLE-HOLD
GAIN
OUTPUT

For a gain of - 1 the bandwidth is one half of that giVfJn for the
noninverting mode. R3 is equal to the parallel combination of R1
and R2 and is used to compensate for voltage offset caused by
input bias current. R1 and R2 should be matched 100 ppm/oC
metal film type resistors for a gain of - 1. For higher gains the
ratio should be matched closely or trimmed with a small value
carbon composition type resistor.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-45

SHM-IC-1
ACCURACY CHARACTERISTICS VS. CH
Typical at 25°C, ± 15V Supplies

OPEN LOOP FREQUENCY RESPONSE
Typical at 25°C, ± 15V Supplies

10000

100

l lllllll I
IIII II 111m I
C H ~ 1.00OpF I

90

ao

I"i:

70

~

60

~

~

f

"

50
40

~

30

.§

20

!

1 000

V C H ,;; 100pF

,

~OLD MODE VOLTAGE
DROOP (mVfsec)

"-I'..

100

C H = O.OljtF

V

C H - 1.0!,F

:"\

10

~

-.-

"-"-

10

CH~O.lI1F

_10

"'"

""

0

,

"- "-

o. 1

-20

~SAMPLE TO !-lOLD OFFSET ERROR (m~

-30

lOOK

10K

lK

100

10

10M

1M

100M

~

"-1.0"F

0.0 1

Frequency (Hz)

10pF

l00pF

l000pF

O.OlpF

O.l,.F

'H

SPEED CHARACTERISTICS VS. CH
Typical at 25°C, ± 15V Supplies
1000

UNITY GAIN PHASE MARGIN (deg)

100

t::==

HOLD MODE VOTLAGE DROOP VS. TEMPERATURE
Typical ± 15V Supplies
00

/

/

10

-=-

1.0

~

~~:rciw~~+~ (MHz) ==

Ll

CH - O.OOt/,F ../

SLEW,~

r:~~LTS

ACQUISiTION TIME

~~~G:~~ 6~lV%

10~

IpSEC

'\.

0.1

/

/

......

/\
0.01
10pF

/

1000pF

loopF

O.OlI'F

O.lpF

C H = O.Ol/,F

~

CH

1

25

50

75

TEMPEAATURE (0C)

RECOMMENDED CIRCUIT BOARD LAYOUT
USING GUARD RING

N
DiGITAL

G

HOLD
CAP

':,"

CON~TAOL

~.

r----,

__ ,
...

ORDERING INFORMATION

~

~IN(-)

MODEL NO.
:

I

•

SHM-1C.l

_

$
$

IN(+J
OFFSET TRIM
OFFSET TRIM

_-15VdC
GUARD

$

RING

+15Vdc_
N.C.

$

N.C.
OUTPUT

SHM-IC-1
SHM-IC-1M

ACCESSORIES
Part Number

Description

TP100K (100 KO)

Trimming Potentiometer

Contact Factory for Quantity Pricing

I _ _ _ _ _ _ _ _ ..J

BonOMV1EW

3-46

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

SHM·LM·2
Low Cost Monolithic
Sample·Hold
FEATURES
• 5 Microseconds acquisition time
• 0.01% Gain accuracy
• TTL/CMOS-compatible
• ±5V to ± 18V supplies
• TO-99 package
• Low cost

OFFSET

+Vs

-Vs

GENERAL DESCRIPTION
The SHM-LM-2 is a low cost monolithic
sample-hold circuit with excellent performance features. It is self-contained requiring
only an external hold capacitor with the
value selected by the user for desired
speed and accuracy characteristics. Acquisition time is 6 microseconds for a 10V
change to 0.01 % using a 1000 pF capacitor and 25 microseconds using a 0.01 I'F
capacitor. It is 5 microseconds and 20
microseconds respectively for a 10V
change to 0.1%. This device is internally
configured as a unity gain follower with a
gain error of less than 0.01 % in the sample mode.
The circuit consists of a bipolar input
amplifier, a low leakage electronic switch,
and an FET output amplifier. The
monolithic fabrication process combines P
channel junction FET's with bipolar transistors to achieve a low noise, high input
impedance output amplifier. Other important specifications include 1010 ohms input
impedance and 1 MHz bandwidth. Aperture time is less than 100 nanoseconds
and hold mode feedthrough is less than
0.005%. Hold mode droop is 200
I'V/mseconds maximum with a 1000 pF
hold capacitor and 20 I'V/mseconds maximum with a 0.01 I'F capacitor. The SHMLM-2 can operate over a power supply
range of ±5V to ± 18V.
Applications include sampling for AID conversion, deglitching circuits, automatic
zeroing circuits, and analog demultiplexing circuits. It is recommended that the
holding capacitor (C H) be a teflon,
polystyrene, or polypropylene type for best
results. Operating temperature range is
O°C to + 70°C for SHM-LM-2 and - 55°C
to + 125°C for SHM-LM-2M.

> - - - 1 : 5 OUTPUT

300n
SWITCH
DRIVER

SAMPLE
CONTROL

SAMPLE
CONTROL
REFERENCE

HOLD
CAPACITOR

MECHANICAL DIMENSIONS
INCHES (MM)

f

INPUT/OUTPUT
CONNECTIONS

f;~l01R

1+--O'325

~

0.175

(4,4)

0.500 MIN

B

LEADS,4]O

0.Ot7 TVP

0 OO~

FUNCTION

PIN

1

+ POWER SUPPLY

2

OFFSET ADJUST

3
4

INPUT
- POWER INPUT

5

OUTPUT

6

HOLD CAPACITOR (CH)

7

SAMPLE CONTROL REF.

B

SAMPLE CONTROL

BOTTOM
VIEW

NOTE: ALL LEADS GOLD PLATED KOVAR

DATEL, Inc. 11 Cabot Boulevard, Mansfield. MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-47

SHM-LM-2
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage,
pinsland4 ......•.........
Input Voltage, pin 3 •••.•......
Sample Control to Sample
Reference, pin 8 to pin 7 • . . . ..
Hold Capacitor Short Circuit . . ..

TECHNICAL NOTES
±18V

± Supply
+ 7, - 30V
10 seconds

FUNCTIONAL SPECIFICATIONS
Typical at 25 ·C, ± 15V supplies and CH = 0.01 ",F unless otherwise

stated.

INPUTS
Input Voltage Range •.....•••••
Input Overvoltage, no
damage •.••..••.••...•.••.
Input Impedance .........•...
Input Bias Current .•.•.••••••.
Sample Control. •••........•..
Sample Control Input
Current' . . • • . . • . . • • . . • . . • ..

1. The sample to hold offset can be adversely affected by stray
capacitive coupling from input sample control signals to the
hold capacitor. It is recommended that a guard ring connected to the output be put around pin 6 in a circuit board
layout in order to minimize this effect.
2. For various types of logic inputs, the logic threshold (VT) is set
by two biasing resistors as shown in the diagram. Inverted or
non-inverted pulses may be used by using either pin 7 or pin 8
as the sample control input.

CONNECTION DIAGRAM

± 11.SV minimum

+ 15V de

±Supply
10'0 ohms
10 nA typical, SO nA maximum
TTL or CMOS

lK

24K

10",A maximum

OUTPUT
INPUT

Output Voltage Range ..•...•.. ± 11 .SV minimum
Output Current, S.C.
protected. . . . . • • • . . . • . • • • •• ± S rnA
Output Impedance •..••.••.•.. O.S ohm

=

OUTPUT

SAMPLE
CONTROL
(TTL) 0 - - - - - '

SA::~: -=.=Jt( :~4V)

PERFORMANCE
Gain ..••.••••••...•••••.....
Output Offset Voltage, adj.
tozero ..••••.......•....••
Offset Voltage Drift,
SHM-LM-2 ••••.•.•••.......
Offset Voltage Drift,
SHM-LM-2M .••.•..••••••...
Sample to Hold Offset ..•.••.••
Hold Mode Feedthrough •••..•••
Power Supply Rejection
Ratio .•....••....••••••.••
Output Noise, hold mode
(10 Hz-l00 kHz) ..•.•.•...•••
Hold Mode Droop,
CH 1000 pF •.....••..•..•
CH = 0.01 ",F ••....••.•••...

0-----''-\

+1.000, +0, -0.01%

-15V de

± 7 mV maximum
20 ",Vloe
10 ",Vl°e>
2.5 mV maximum
0.01 % maximum

SAMPLE-CONTROL CONNECTIONS
+15V

80 dB minimum
8.5 ",V RMS
24K

200 ",Vlmseconds maximum
20 ",Vimseconds maximum
+2.8V

DYNAMIC RESPONSE
Acquisition Time
10V Change, CH 1000 pF .••
10V Change, CH
1000 pF .••
20V Change, CH 1000 pF ...
20V Change, CH
1000 pF ..•
10V Change, CH O.OlI'F .•..
10VChan~e, CH
O.OlI'F ...•
Aperture De ay Time ..........
Hold Mode Settling Time' ....•.
Bandwidth, Sample Mode,
-3dB ....................

=
=
=
=
=
=

S.6K

5 microsecoonds to 0.1 %
6 microseconds to 0.01 %
7 microseconds to 0.1 %
8 microseconds to 0.01 %
20 microseconds to 0.1 %
25 microseconds to 0.01%
100 nanoseconds
800 nanoseconds

FOR TTL CONNECT PIN 7 TO GROUND

FOR TTL USE VALUES SHOWN AT RIGHT

1 MHz

POWER REQUIREMENTS
Voltage, rated performance. . . .. ± lSV dc
Voltage Range, operating .•.... ± 5V to ± 18V dc
Quiescent Current •..•••••.... 6 rnA

ORDERING INFORMATION
MODEL NO.

OPERATING
TEMP. RANGE

SHM-LM-2
SHM-LM-2M

ooe to 70°C
-55°C to + 125°C

PHYSICAUENVIRONMENTAL
Operating Temp. Range,
SHM-LM-2 ••.....•......•..
SHM-LM-2M ................
Storage Temperature Range ...•
Case ...•..••.....•.........

ooe to + 70°C
-ssoe to + 12Soe
-65°C to + lS00e
8 pin TO-99

FOOTNOTES:
1. For either Sample Control or Sample Control Reference inputs
2. 28 IlVloC maximum
3. The time for the output to settle within 1 mV of final value after the logic
command to switch into hold mode.

3-48

ACCESSORIES
Part Number

Description

TP1K

Trimming Potentiometer

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

SHM-UH Series
Ultra-High Speed
Sample-Holds
FEATURES
•
•
•
•
•

10 MHz sampling rate
30 Nanoseconds acquisition time
30 Picoseconds aperture uncertainty
Diode bridge switch
45 MHz bandwidth

GENERAL DESCRIPTION
The SHM-UH series is comprised of two
ultra-fast sample-holds specifically designed for use with ultra-fast 6-, 8- and
10-bit AID converters. Both models in this
series use an open loop design optimized
for ultra-high speed operation. This design
consists of an ultra-fast input buffer
amplifier, a transformer driven diode
bridge switch, and a high impedance output buffer amplifier.

These sample-holds are encapsulated in 2
x 2 x 0.375 inch (51 x 51 x 5 mm) cases
with dual-in-line pinning compatibility.
Power requirements are ± 15V dc and
+ 5V dc. Standard versions operate over a
temperature range of 0 to + 70°C with extended temperature range versions also
available.

EXT. ADJUSTMENT
SCREW

ANALOG
INPUT

ANALOG
OUTPUT

ANALOG
INPUT
31
GROUND

ANALOG
OUTPUT
GROUND

•

+ 5V
5V SAMPLE SAMPLE
POWER GND CONTROL CONTROL
GROUND
INPUT

The SHM-UH3 is the newest member of
this series and embodies substantial performance improvements on an already
high performance design. This model is
recommended for inclusion in new design
applications. In addition to a 30 nanosecond acquisition time with only 30 picoseconds of aperture uncertainty, linearity is
0.05% of full scale and hold-mode feedthrough is - 66 dB for inputs from dc to 10
MHz.
The
SHM-UH3
utilizes
all
hermetically sealed semiconductors in its
design.

Both models have sample-mode bandwidths of 45 MHz, output slew rates of
500V/microseconds and output current
drive capabilities of ± 30 mA. Each has an
output offset adjustment accessible from
the side of the module.

-15VDC

"I'

The unique pulse transformer driven diode
bridge switch is a key design feature in attaining a 30 nanosecond acquisition time
for a 10V signal change. This switch also
holds aperture uncertainty time to less
than 30 picoseconds for the SHM-UH3
and less than 200 picoseconds for the
SHM-UH.

The SHM-UH is the lower cost version of
the series. An acquisition time of 50 nanoseconds, aperture uncertainty of less than
200 picoseconds, and linearity of 0.25%
make this model well suited to use with
ultra-high speed AID converters with up to
8 bits resolution.

15V
POWER
END

+ 15VDC

INPUT/OUTPUT
CONNECTIONS

MECHANICAL DIMENSIONS
INCHES (MM)

PIN

1
SW r
'l'

18Wi r7-7 SPACES
AT lOOEA

'''''

•
.21

lT50~g24--­
7 SPACES

AT l00EA

,.
"
o
o
o

-00

g25---------------9 g
0

g

0

g

OIEO~ :~ --------------:~:

2
15
16
17
18
19
20
21
31
32

FUNCTION
SAMPLE CONTROL IN
SAMPLE CONTROL GND
ANALOG OUTPUT GND
ANALOG OUTPUT
+5V POWER
5V POWER GND
+15V POWER
-15V POWER
15V POWER GND
ANALOG INPUT GND
ANALOG INPUT

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

3-49

SHM-UH Series
SHM-UH
ABSOLUTE MAXIMUM RATINGS'
Input Voltage ....... ± 15V
Samp e Control Input
Voltage ............... " + 5.5V
Sample Pulse Width 7 ••••••• 70 nsec.
Analog Supply Voltage. . . . .. ± 18V
Digital Supply Vohage ...... + 5.5V
Anal~

SHM-UH3

±5.5V
+5.5V
100 nsec.
±18V
+5.5V

PHYSICAUENVIRONMENTAL
Operating Temp. Range .....
Storage Temp. Range. . . . . ..
Relative Humidity ..........
Case Size ................•

ooe to + 70°C
- 55°C to + 85°C
Up to 100% Non-condensing
2 x 2 x 0.375 inches
(50,8 x 50,8 x 9,5 min)
Case Material .............. Black Diallyl Phthalate, per
MIL-M-14
Pins ..................... 0.020" Dia, Gold Plated
0.25" Long, min.
Weight ................... 3 ounces (85 grams)

FUNCTIONAL SPECIFICATIONS,
Typical at 25°C and ± 15V dc and + 5V dc Supplies, unless otherwise
noted.
INPUTS
Input Voltage Range . . . . . . ..
Inputlmpedance ...........
Input Bias Current. . . . . . . . . .
Sample Control Pulse .......
Sample Control Pulse Width ..
Sample Control Input
Impedance ..............
Sample Pulse Rise or
Fall Time ...............

± 5V
100 Meg
50 pA2
+5Vat 130 rnA
40 ± 10 nsec.

±5V
lOOk
±20 pA
+3.5 at 60 rnA
35 ± 10 nsec.

500

500

3 nsec .• max.

3 nsec., max.

±5V
± 30 rnA
30
5000
100 pF

±5V
±30 rnA
30
5000
100 pF

+0.92 to +0.95

+ 0.95 to + 0.98

± 0.25%, max."

± 0.05%, max.

OUTPUTS
Output Voltage Range, min...
Output Current, max. .......
Output Impedance, dc ......
Output Load' . . . . . . . . . . . . . .
Maximum Capacitive Load ...

FOOTNOTES:
1. Maximum ratings represent the limits of device operation without damage.
The devices should not be operated at these limits.

2. 150 pA maximum at 25·C. Doubles every 10·C (SHM-UH Only).
3, For full scale signal outputs. For small signal outputs (± lV), output load
resistance may be decreased to 1001l.
4. See Feedlhrough Attenuation Graph.
5. Model SHM-UH requires three sampling pulses to acquire a full scale signal

change.
6. For the SHM·UH this will vary by ±2 nanoseconds maximum with
temperature.

7. See Technical Note 10.
8. This may vary between units by 3 nanoseconds.
9. For input signal changes of ± 1.25V maximum. larger input signal changes reo
quire additional sample pulses and settling time. See Technical Note 9.
10. 30 nanoseconds sampling pulses with 70 nanoseconds between pulses.
11. See Technical Note 4.

TECHNICAL NOTES

PERFORMANCE

1. These devices are true sample-holds, rather than track and
Gain .....................
Linearity Error,
% of Full Scale ...........
Output Offset Voltage,
Hold Mode ..............
Output Offset Voltage Drift ...
Hold Mode Droop ..........
Hold Mode Feedthrough4 ....

Adj. to Zero
± 50 p.v/oe
50 p.V/p.Sec.
- 50 dB at
10 MHz
Analog Supply Rejection .... 6mVN

Adj. to Zero
± 50 p.v/oe
50 p.V/p.sec.
-66 dB,
dc to 10 MHz
25 mVIV

DYNAMIC RESPONSE
Acquisition Time ...........
AcqUisition to Output
Time" .................
Hold Mode Settling Time .....
Bandwidth, Sample Mode ....
Output Slew Rate ..........
Aperture Delay Time ........
Aperture Uncertainty Time ...
Sampling Rate, max ........

holds, in that they take an "instantaneous" sample of the
input signal rather than continuously track it and hold on
command. The extremely high speed available with this
series allows a close approximation to sampling period of
the ideal zero-order hold. Design considerations necessary
to attain this level of performance place a limit on long-term
holding ability. AID converters used with these sampleholds should be selected for compatible speed and
accuracy.

2. Aperture uncertainty time is a measurement of the time
50 nsec?

30 nsec.

70 nsec.
20 nsec.
45 MHz
500V/p.sec.
12 nsec."
200 psec.
10 MHz'o

50 nsec.
20 nsec.
45 MHz
500V/p.sec.
12 nsec.·
30 psee.
10 MHz'o

POWER REQUIREMENTS

uncertainty or jitter of the actual point in time of the switch
change to the off state. It is an indication of the repeatability
of the switch characteristics. This time should not be confused with the aperture delay time which is a fixed delay
and can be compensated for.

3. Acquisition time is the time required, after the sampling
switch is closed, for the hold capacitor to charge to a fullscale voltage change and remain within a specified error
band around the final value.

4. Acquisition to output time is defined as the period from the
Analog Power Supply ....... ± 15V dc ±0.2V dc at 100 rnA
Digital Power Supply ........ +5V de ±0.25V de at 100 rnA

receipt of the sample command until the output of the
sample-hold has settled to within a specified error band of
its final value. This is the operating period of the samplehold, including all internal delays and settling time, and consequently defines the total time required for a single
sample-hold operation.

5. Digital and analog grounds are not connected internally.
When using these sample-holds with AID converters, good
design practice dictates the connection of analog and
digital grounds from both devices at one pOint, preferably at
the AID converter to avoid ground loops. Use of a ground
plane is recommended for best performance.

3-50

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

SHM-UH Series
6. For Model SHM-UH only, hold mode droop is from the held
value of the analog input signal toward the signal level at
the input. The droop experienced is also dependent on input signal characteristics and is related to the feedthrough
attenuation characteristics. The combination of these factors may cause the observed hold mode voltage droop to
be significantly less than 50 ,N/microseconds for some applications, e.g., droop is zero for a constant input signal. In
the case of Model SHM-UH3, droop is independent of
feedthrough.
7. For both the SHM-UH and the SHM-UH3 input sources
should be purely resistive.
8. Input overvoltage protection may be added to the SHM-

UH3 by connecting diodes from the analog input and the
analog input ground to the + 5V and - 5V supplies.
9. To acquire full-scale input signal changes, the SHM-UH requires three sampling pulses with a 100 nanoseconds settling time allowed between each to acquire full-scale input
changes to rated linearity.
10. Sample pulse widths greater than those specified under
MAXIMUM RATINGS will give unsatisfactory performance
due to drive transformer saturation. For Model SHM-UH3,
excessive pulse widths will result in the sample-hold returning to the hold mode before the sample control input is
taken low. Model SHM-UH may be damaged by exceeding
sample pulse width limits.

APPLICATION
HOLD MODE FEEDTHROUGH ATTENUATION

SAMPLE CONTROL INTERFACE SHM-UH

o dB
.-10 dB

~

~

_\

-20 dB

,,r - -

~

-30 dB

~NJtC~~ND) !,
,

\

-40 dB

+5V

c_
-SOdB

SAMPLE
CONTROL
INPUT

+5~
40 nsee

~

SHM-UH

-BOd8

±

10

nsee

SHM-UH3

OV

.1
10 Hz

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

10 MHz

SINUSOIDAL INPUT FREQUENCY

HOLD-MODE FEEDTHROUGH IS A
PHENOMENA THAT OCCURS AFTER THE
SWITCH HAS BEEN OPENED AND THE
SIGNAL IS BEING HELD. A SMALL PART
OF THE SIGNAL ON THE INPUT WILL BE
COUPLED TO THE OUTPUT.

SAMPLE CONTROL INTERFACE SHM-UH3

SHM-UH3

+3·~35nsec ±
OV..J

L-

10nsec

lhSN74S140
(DUAL NAND)

ADJUSTMENT PROCEDURE
1. Connect the Analog Input (pin 32) to the Analog Input
Ground (pin 31).
2. Connect a precision pulse generator with negative going
output pulses via a terminated coaxial cable to the Sample
Control Input (pin 1) and the Sample Control Ground (pin 2).
Use the sample control interface shown in the applicable
diagram.
3. Pulse Repetition Rate
50kHz
40 nsec
Pulse Width
Pulse Amplitude
+5V
Note: Sample Control Input Impedance is 50 Ohms.
4. Connect a precision digital voltmeter to the Analog Output
(pin 16) and the Analog Output Ground (pin 15).

SAMPLE

CONTROl
INPUT

+~5V
OV

35 nsee

± 10 nsee

5. Adjust the Offset Adjust Potentiometer (accessible through
side of case) until the digital voltmeter reads O.OOOOV.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

3-51

SHM-UH Series
APPLICATION
SAMPLE-HOLD DEFINITIONS

,

\

I

/

/
I
I
I

I

I

I
I
I

SAMPlE·HOLD
OUTPUT

I

I

I

I

,

',-

----_

....

SAMPLE
COMMAND

SAMPLE CONTROL PULSE

APERTURE DELAY TIME, T 1
The period between the receipt of the hold command and opening of the sampling

switch. Due to sampling switch characteristics, the measurement of this period

HOLD MODE SETTLING TIME, T 4
The time from the hold command transition until the output has settled within a
specified error band around the final value.

contains a small amount of uncertainty, i.e., the actual point in time of the opening
of the sampling swi1ch will vary by a small amount with each operation. This
variance falls within a narrow_ time range which is specified as the aperture uncertainty time (see definition below).

ACQUISITION TO OUTPUT TIME, T5
The time from the receipt of the sample command until the output of the samplehold has settled within a specified error band around the final value.

ACQUISITION TIME, T2
The time required, after the closing of the sampling switch, for the hold capacitor to
charge to a full scale voltage change and then remain within a specified error band
around the final value.

APERTURE UNCERTAINTY ERROR
An amplitude uncertainty in the held value due to the change in the analog input
signal during the aperture uncertainty time. This error is the product of the rate of
change of the input signal and the aperture uncertainty time. Therefore, small
values of aperture uncertainty time yield small values of aperture uncertainty error.

APERTURE UNCERTAINTY TIME, T3
The time variation, or jitter, in the opening of the sample switch.

SHM-UH3
-5V

+5V

NOTE: OPTIONAL
INPUT PROTECTION
SHOWN

-15V

+15V

IN4148

ANALOG
INPUT

32

SHM·UH3

15

2000
31

16

ANALOG
OUTPUT

ORDERING INFORMATION

ANALOG
GROUND

MODEL NO_
+5V de

SHM-UH
SHM-UH3

DESCRIPTION

50 nanoseconds, 0.25%
30 nanoseconds, 0.05%

+3'5V~
35 nsee
OV
TYPICAL SAMPLE
CONTROL PULSE
SAMPLE
CONTROL
INPUT

3-52

ACCESSORIES

Part Number

Description

DILS-2

Mating Socket, 2 required/Module

DATEL, Inc_ 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

AMPLIFIERS

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

4·1

OPERATIONAL AMPLIFIERS
MODEL

DC OPEN
LOOP GAIN

(V/V)
AM-427-1A

6.3X 10'

AM-427-1B

10'

AM-427-2A

6.3 X 10'

AM-427-2B

10'

SEITLING
TIME
10V to 0.1%

SLEW
RATE
(V/fiSec)

BANDWIDTH

1.7

5 MHz

1.7

5MHz

GAIN

OFFSET
DRIFT
(fiVrC)
I.S
0.6

I.S
0.6

AM-430A

1.3

TEMPERATURE
RANGE
('C)

PAGE

OUTPUT

PACKAGE

±IIV/±ISmA

S-pin DIP
Monolithic

oto +70

4-11

±11V/±IS mA

S-pin TO·99
Monolithic

oto +70

4-11

±IOV/±25 mA

S-pin TO-99
Monolithic

oto +70

4-15

lOOK

II fis

0.5

2.5 MHz

25K

330 ns

30

12 MHz

20

±IOV/±IO mA

S-pin TO-99
Monolithic

-55 to +125

15K

200 ns

120

20 MHz

30

±IOV/±I0 mA

S·pin TO-99
Monolithic

-55 to +125

13

10MHz

30

±12V/±20 mA

S-pin TO-99
Monolithic

·55 to +125

7

12MHz

10

±IOV/±I0 mA

S·pin TO·99
Monolithic

oto +70

4-19

0.6

AM-430B
AM-45Q-2
AM-45Q-2M
AM-452-2
AM-452-2M
AM-453-2C
lOOK
AM-453-2M

o to +70

oto +70
oto +70

4-19

4-17

4-17

AM-46Q-2C

150K

AM-462-2

150K

35

100 MHz

15

±IOv/±IO mA

S-pin TO-99
Monolithic

oto +70

4-19

AM-464-2

lOOK

5

4MHz

15

±35V/±10 mA

S·pin TO-99
Monolithic

oto +70

4-23

1000

100 MHz

±IOV/±50 mA

14·pin DIP
Hybrid

oto +70

14-pin DIP
Hybrid

·55 to +125

14-pin DIP
S-pin TO-99

oto +70

1.5 fis

AM-500GC
AM-500MC

200 ns
to 0.01%

AM-500MM
AM-1435MC
AM-1435MM

o to +70

5
10'

70 ns
to 0.01%

10'

7
10

·55 to +125

300

1000 MHz

5

±7V/±14 mA

2.5

2MHz

0.05

±4.7V

AM-7650-1
AM-7650-2

10'

INSTRUMENTATION
MODEL

AM-542MC
AM-542MM
AM-543MC
AM-551MC
AM-551MM

DESCRIPTION

High Performance
Hybrid
Digitally
Selectable
Gain Ranges
Low Cost, High
Performance
Hybrid

4-25

oto +70

4-3

4-35

AMPLIFIERS

GAIN
RANGE

GAIN
NONLINEARITY

SEITLING
TIME

INPUT
IMPEDANCE

OUTPUT

COMMON
MODE
REJECTION

PACKAGE

1101024

0.005%

150 fisec.

IO'Q

±10.5Vat
±5mA

86dB

24-pin DIP

OPERATING
TEMPERATURE
RANGE ('C)

PAGE

o to +70
4-27
-55 to +125

I to 128

0.01%

6fisec.

10"Q

±IIVat
±lmA

86dB

24-pin DIP

I to 1000

0.01%

2 fisec.

10"Q

±11V at
±5mA

100dB

16-pin DIP

oto +70
o to +70

4-27

4-31

-55 to +125

SIGNAL CONDITIONING AND ISOLATION AMPLIFIERS
MODEL

±1000V dc

10 to 1000

Low-Cost, Four
Channel Isolation
Amplifier

±IOOOV dc

1 to 1000

4-chan Strain
gage condo

None

Precision

Isolation Amplifier

SCM-l00A
SCM-l00B
SCM-l0l
SCM-l03

4-2

RANGE

Low~cost

AM-227

GAIN

ISOLATION
VOLTAGE

DESCRIPTION

COMMON
INPUT
GAIN
INPUT
NONRESISTMODE
OFFSET
LINEARITY
ANCE
REJECTION VOLTAGE
±0.005%

100 MQ

±0.03%
100MQ
±O.02%

166.6VN
or50VN

±O.01%

100MQ

OUTPUT

OPERATING
TEMPERATURE
RANGE ('C)

±IOVat±5 mA

o to +70

4-7

156 dB
±20 flV
- - - - - - - - - ±5V at ±5 mA
±50 IN
145 dB

oto +70

4-41

o to +70

4-45

176 dB

94 dB

±150fiV

±5Vat±5 mA

PAGE

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

AM·1435
Ultra·High Speed Wideband
Operational Amplifier

FEATURES
•
•
•
•
•

70 Nanoseconds settling to 0.01%
1 GHz Gain bandwidth product
100 dB Open loop gain
80 dB Minimum CMRR
-55·Cto +125·COperation

OFFSET
ADJUST

GENERAL DESCRIPTION
DATEL's AM-1435 is an ultrafast settling,
wide-band operational amplifier. Utilizing
precision thin-film hybrid construction and
differential input operational amplifier
design techniques, the AM-1435 achieves
a settling time of only 70 nanoseconds for
a 10 volt step to 0.01% accuracy. High
speed performance is optimized with high
open-loop gain, flat frequency response
beyond 10kHz and a roll-off of 6 dB/octave to beyond 100 MHz. Typically, gain
bandwidth product is 1 GHz and slew rate
is 300 V/microsecond.

-IN
AM-1435

OUTPUT
'--------{] 3 CURRENT
SOURCE

+IN

' - - - - - - - f l 4 COMMON

AM-1435 dc characteristics include a dc
open loop gain of 100 dB, 1 MO input impedance, and an initial input offset voltage
of only ± 2 mY. Input offset voltage drift is
typically ± 5 /LV/oe. Also featured is a
minimum common mode rejection ratio of
80 dB and full power frequency of 8 MHz.
The AM-1435 is designed specifically for
applications requiring high accuracy in the
amplification of complex wide-band waveforms. Such applications would include
radar and sonar signal processing, video
instrumentation and ultra-fast, AID, D/A
converters and sample-hold amplifiers.
Power supply requirement is ± 15V dc at 30
mA maximum quiescent current. Models are
specified for operation over the commercial
ooe to + 70oe, and military -55°e to + 125°e
operating temperature ranges. The device
package is a 14-pin, hermetically sealed, ceramiccase.

3
- 15V OPT COMP

CAP CAP

MECHANICAL DIMENSIONS
INCHES (MM)

--.LR r. ,_

r-

0.500 MAX.
I
(12,7) - I ~

190('.8IMA><.

0.150 MIN.
(3,8)

~

""" 0.010

lI.

0.018 KOVAR

8',

,

17

0.700
6 SPACES
AT 0.100 EA.
(2,5)

I BOTTOM I

,
I

OOTONTOP
REFERENCES
PIN 1

INPUT/OUTPUT
CONNECTIONS

I 1

VIEW

I

0.800 MAX.
(20,3)

I
14 I

y ___

l

0.100

•

~

_
1

0

PIN
1
2
3
4
5
6

7
8
9
10
11
12
13
14

FUNCTION
OPTIONAL CAP
OUTPUT
COMPENSATION CAP.
+ 15V SUPPLY +11"'
OFFSET ADJUST
OFFSET ADJUST
- INPUT
+ INPUT
N.C.
N.C.
N.C.
V,
15VSUPPLY
OUTPUT CURRENT SOURCE
COMMON

. ,00

(2,5)

NOTE: PINS HAVE 0.025 ::!::O.Ol INCH STANDOFF FROM CASE

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

4·3

AM·1435
FUNCTIONAL SPECIFICATIONS

PHYSICAUENVIRONMENTAL

Typical at + 25 ·C, ± 15V dc supplies, unless otherwise noted.
INPUT CHARACTERISTICS
Differential between inputs •.•••.••...•
Common Mode Voltage Range ...•..••.
Common Mode Rejection Ratio;
dc •••••••••...••••••..••.••••••.
1 MHz •••••••••••••.•...••.....••
Input Impedance;
common mode
differential mode ..•.••••••••.•••..
Input Offset Voltage" .......•......••
Input Bias Current. •...•..•..•••...•.
Input Offset Current

...................
.................

80 dB
70 dB

-

-

Operating Temp.
Range:
AM-1435MC •..•.
oDe to + 70 0 e
AM--1435MM9 •••. - 55 0 e to + 125 0 e
Storage Temp.
Range.......... -65°e to + 150 0 e
Package. • . • . • . • •. 14-pin. hermetically
sealed ceramic DIP

1 Mil II 2 pF
2.5 kll ~ 2 pF

-

-

FOOTNOTES:

MINIMUM

±7V

-

--

TYPICAL

±8.5V

±2 mV
10 pA
0.3 pA

MAXIMUM
±4V

-

±5 mV
20 pA

-

OUTPUT CHARACTERISTICS
Output Voltage' ...•••.••......••..•.
outut Current' .•.......••...••.••.•
Sta Ie Capacitive Load' ••.•...••...•.

-

±5V
±10 mA

±7V
±14 mA
1000 pF

90 dB

-

100 dB
±5 "ViDe
50 nAloe
2 nAloe

..................

-

15p.V p.p
1.6 p-V RMS
5.2 p-V RMS

--

..................

--

2.5 nA pop
2.5 nA RMS
3.5 nA RMS
0.15 mVIV LNs

--

1000 MHz
150 MHz
10 MHz
60 nsec.
70 nsec."
25 nsec.
40 nsec.
10 nsec.
20 nsec.
300 VI".sec.

75 nsec.

-

--

PERFORMANCE
dc Open Loop Gain' .................
Input Offset Voltage Drift .••...••.••..
Input Bias Current Drift .•.••.••.••••..
Input Offset Current Drift •••••.••••..•
Input Voltage NOise,
O.Ot Hz to 10 Hz ...••.•••.•.••.••••
tOO Hz to to kHz
tOHztot MHz ..•.................
Input Current Noise',
O.Ot Hz to 10 Hz ••..•....•..••..•••
tOO Hz to to kHz
to Hz to t MHz •.••••....•••..••.••
Power Supply Rejection Ratio ••••••.••

-

-

±25 p'v/oe
100 nAloe

-

-

DYNAMIC CHARACTERISTICS
Gain Bandwidth Product •.•••.••..•...
Unity Gain Bandwidth •...•••••• : ••...
Full Power Frequency' •.••••.•••...••
Settling Time, tOV to 0.025%7 ...••....
tOVtoO.Ot% •...•...•..
5Vtot.0% •••••.••••.••
5VtoO.t% .•.•••.•••...
tVtot.O% •.••.••....••
tVtoO.1·'" •••.•.•....••
Slew Rate
Overshoot ...•.•.....•...••..•....•
Propagation Delay ..............•...
Rise Time, tOV Step •.••••••.•....•••
Overload Recovery Time •..••..••..••

.........................

700 MHz

8 MHz

-

-

250 V/".sec. 6

-

-

5 nsec.
40 nsec.
50 nsec.

-

60 nsec.
1%

-

--

POWER REQUIREMENTS
Rated Supply Voltage .••••.•.......••
Quiescent Current' ...•.....•......•.

±12V

-

±15V
-

±16V
±30 mA

I. Specified for dc linear operation. Common
mode voltage range prior to fault condition is

± 10V de maximum.
2.
3.
4.
5.
6.
7.
S.
9.

Adjustable to zero.
f\. = 5000.
C, = 3 pF.
Referred 10 input.
C, = 0.5 pF.
C, = 1 pF.
±Vs = ±15Vdc.
Wilh ISDe/watt heal sink.

TECHNICAL NOTES
1. The use of good high frequency circuit
board layout techniques is required for
rated performance. The extensive use
of a ground plane for all common connections is recommended. Lead length
should be kept to a minimum with pointto-point connections wired directly to
the amplifier pins. 1 p.F tantalum bypass
capacitors ~hould be used at the + Vs
and - Vs pins.
2. Operation of the AM-1435MM over the
+85°C to + 125°C temperature range
requires additional thermal dissipation
to achieve rated performance. Use of
an 18°C/W heat sink is recommended.
3. No input protection is provided so as to
maximize frequency response. As a
result, several precautions must be
observed: Do not apply positive supply
voltage before the negative supply. Do
not apply power to either input prior to
power-up. If frequency response is not
critical, installation of an external input
protection circuit is recommended.
4. A 1 p.F bypass capacitor connected
from Pin 1 to common (Pin 14) may be
required to inhibit output oscillation
when driving capacitive loads.
5. To ensure stable operation when the
noise gain is less than 10. a 2 pF compensation capacitor must be connected
between pins 3 and 7. The value of the
compensation capacitor may be application sensitive.

6. TheAM-1435 is a prime choice as a current to voltage converter due to its excellent Eos and los temperature coefficient ratings. Input bias currents are
easily compensated by adding a resistor
from pin 8 to ground, which is equal to
the parallel combination of the feedback resistor and input impedance.

4-4

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

AM-1435
TYPICAL CONNECTION AND PERFORMANCE
TYPICAL CONNECTION DIAGRAM
+15V

2 OF
R1
INPUT

C1

<..>--vv~----{:

1 k!J
OUTPUT
R2

-15V

TYPICAL CONNECTION AND COMPENSATION
The typical connection diagram (above) shows the AM-1435 in a
unity gain inverting configuration. Operational in any conventional operational-amplifier circuitry, the AM-1435 as a noninverting amplifier requires a noise gain of at least two (NOISE
GAIN = 1 + RJR,).
The 2 pF compensation capacitor at C, is required for stable
operation when the noise gain is less than 10. Compensation for
bias current is provided by R2 and its value determined by the
formula

R2

= (R,) x (R4)
R, + R4

The offset adjust potentiometer at R3 and the compensation
capacitor at C4 are optional. Note however, C4 should be implemented when driving capacitive loads to prevent oscillation
of the output stage.
Operation of the AM-1435 at low impedances requires careful
attention to include the feedback resistor as a part of the total
output load.
The use of good, high frequency circuit board layout techniques
is required for rated performance. The amplifier should be
mounted on a ground plane using minimum lead length and
point to point wiring directly to the amplifier pins.

GAIN AND PHASE VS. FREQUENCY
(UNCOMPENSATED)

GAIN AND PHASE VS. FREQUENCY
(COMPENSATED 2 pF)

120

120r-----

100

00

IN _ ____...
100 e-...:G::::A::c.

180 0

iif
80

\=
J

 12-bits) applications of the
AM-227.

BRIDGE TRANSDUCER INTERFACE
+15V

-15V
OFFSET
ADJ.
50 kO

BRIDGE
EXCITATION

+Vs

AM·227

'"'"....

~ OUTPUT

AUTO ZERO
RETURN

The AM-227 is designed to interface with low-level signal transducers such as thermocouples and strain gages. Because the
transducers are often situated in noisy industrial environments and the output signal produced is extremely small, they are often
connected in a bridge circuit. The AM-227 provides the user with the high input impedance, high common mode rejection, isolation
(for ground loop elimination) and gain required for bridge interfacing.

ORDERING INFORMATION

4-10

MODEL NO.

OPERATING
TEMP. RANGE

AM-227

DoC to + 70°C

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

AM-427
Ultra Low-Noise
Operational Amplifier

FEATURES
• 5.5 nV/$zMaximum noise density
• 0.08 Microvolt peak-to-peak low frequency noise
• 25 Microvolt maximum input offset
voltage
• ± 40 nA Maximum input offset current
• 0.6 Microvoltl°C maximum offset voltage drift

+SUPPLY
7

GENERAL DESCRIPTION
The AM-427 is a low cost monolithic instrumentation grade amplifier that combines
ultra-low noise operation with exceptional
dc performance. Input noise voltage density is typically 3.5 nV/vIRZ at 10 Hz while
input noise current density is as low as 0.4

-INPUT

~--,)6

+ INPUT

30---;

Other significant features include a maximum input offset voltage of 25 microvolts,
eliminating the need for external zeroing in
most applications. Maximum input offset
voltage drift is only 0.6 microvolt/°C. The
AM-427 is internally compensated to provide a phase margin of 70 0 in the unity
gain mode which eliminates peaking and
ringing in low gain feedback applications.
Output voltage is typically ± 13.5V at
± 6.75 mA load current with a short circuit
protected output.

The AM-427 is an ideal choice for applications requiring high accuracy, low drift and
low noise performance such as the amplification of low level transducer signals.
The AM-427 is available for operation over
the industrial -25°C to +B5°C temperature ranges. Models are packaged in
either an B-pin, hermetically sealed TO-99
case or an B-pin ceramic DIP.

OUTPUT

:A

pAl~Hz.

Dynamic characteristics include an B MHz
gain bandwidth product and 2.BV/microseconds slew rate. Power supply rejection
ratio and common mode rejection ratio are
both in excess of 120 dB.

•.

20----1

4
-SUPPLY

MECHANICAL DIMENSIONS
INCHES (mm)

INPUT/OUTPUT
CONNECTIONS

rr~
1h
19:'.f

1_O'325

0:175
(4.41

_11_.

.005t(0.13)
.390_
(9.91)

045
(1.14)

0.500 MIN

OLEADS

J]O 0 OO~

0.017 TYP

.200TJ:
(5,08)j ....L

.200TJ;

(508)M

(~~~)-I ~ 100
(2.54)

BOTTOM
VIEW

PIN

FUNCTION

f--

1

OFFSET VOLTAGE ADJ

2

-INPUT

3

+INPUT

4

-SUPPLY VOLTAGE

5

N.C.

6

OUTPUT

7

+ SUPPLY VOLTAGE

8

OFFSET VOLTAGE ADJ.

DATEL, Inc. 11 Cabot BoUlevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

4-11

..

:.'."

)'

AM-427
ABSOLUTE MAXIMUM RATINGS
Power Supply Voltage ••.•.•••••...
Input Voltage •••..•••.••••..•...•
Differential Input Voltage •.......••.
Power Dissipation ••.•..••••.•••..

A MODELS

B MODELS
±22V
±22V
±0.7V
658 mW

FUNCTIONAL SPECIFICATIONS
Typical at 25 ·C, ± 15V dc supplies, unless otherwise noted.
INPUT CHARACTERISTICS
Input Voltage Range, minimum ..•.•.
Input Resistance, diff. mode,
minimum .•...•..•••••.•..•••..
Input Offset Voltage, maximum •.•••
Input Bias Current, maximum .••••..
Input Offset Current, maximum .....

±11V
0.8 Mil
100 p.V
±80 nA
75 nA

1.5 Mil
25p.V
±40 nA
35 nA

OUTPUT CHARACTERISTICS
Output Voltage, minimum' ••..•••.•
Output Current, S.C. protected,
minimum .......

o

••••••••

0

± 11V
±18 mA
7011

•••••

Output Resistance, open loop2 ......
PERFORMANCE
DC Open Loop Gain, minimum' .....
116 dB
1.8 p.V/oC
Input Offset Voltage Drift, maximum' •
Long Term Stability .........•..••.
2p.V/mo
Input Bias Current Drift, maximum ±700 pN°C
600 pA/oC
Input Offset Current Drift maximum ••
Common Mode Rejection Ratio,
minimum' •...•.....••.........
100 dB
Input Noise Voltage, maximum,
O.1to10Hz ..••..........•..... 0.25 p.V peakto-peak
Input Noise Voltage Density,
maximum, 10 Hz •...............
8 nV/-JRZ
Input Noise Current Density,
maximum, 1 kHz ...••.....•...•• 0.6pN-JRZ
Power Supply Rejection Ratio,
minimum
94 dB
Gain Bandwidth Product, minimum ••
Slew Rate, minimum •.•..•..•...••

120 dB
0.6 p.V/oC
1 p.V/mo
±200 pA/oC
150 pA/oC
114 dB
0.18 p.V peakto-peak
5.5 nV/-JRZ
0.6pN-JRZ
100 dB
5.0 MHz
1.7V/microsecond

TECHNICAL NOTES
1. In order to maintain the specified drift
performance, both input pins should be
maintained at the same relative temper·
ature. This is to avoid stray thermoelectric voltages which are generated by the
dissimilar metals at the contacts of the
input terminals.
2. To obtain the best possible linearity. circuit design should call for the minimum
output current required by the applica·
tion to assure high gain performance
and excellent linearity. the output
current range should be held to a maximum of ± 10 mAo
3. The AM-427 provides stable operation
with load, capacitance of up to 2000 pF
and ± 10 volt swings. Larger capacitances should be decoupled with a 500
decoupling resistor. To avoid additional
phase shifting and phase margin, a 20
pF capacitor should be used in parallel
with the feedback resistor when the
value of the feedback resistor is greater
than 2K ohm.
.
4. If adjustment of offset voltage is
required, a 10 kO trim pot can be used
without degrading the offset voltage
drift specifications. A 1K ohm to 1 MO
trimpot can be used. however, a 0.1 to
0.2 "v/oe degradation may occur.
Trimming to a value other than zero will
create a drift of (offset voltage/300)
p.v/oe. A 10K ohm offset trimpot will
yield an adjustment range of ±4 mY. A
smaller trim pot in conjunction with fixed
resistors can be used to obtain a
smaller adjustment range with higher
sensitivity and resolution.

POWER REQUIREMENTS
Voltage, Rated Performance ...•..•.
Quiescent Current, maximum .......
Power Dissipation •.••.••••..••..•

±5.7 mA
170 mW

± 15V dc
±4.7 mA
140mW

PHYSICAL-ENVIRONMENTAL
Operating Temperature Range:
AM·427A,B •........••....••..•
Storage Temperature Range ..•..•.•
Package, AM·427·1 ••••....••.•••.
AM·427·2 .•.•••..•.•.••.

-25°C to +85°C
-65°C to + 150°C
8-Pin Ceramic DIP
8·Pin Hermetically Sealed TO-99

TYPICAL CONNECTION DIAGRAM

10KO
FOOTNOTES:
I.
2.
3.
4.
5.
6.

4·12

RL = 600!)
Output Voltage = 0, output current = O.
RL = 2K ohm, VOUT?UT = ± 10V.
Guaranteed unnulled or when nulled with an B kll to 20 kll potentiometer.
Common mctde voltage = ± ltV.
Vs = ±4V to ± IBV.

~-----o+Vs

7 6
OUTPUT

DATEL. Inc. 11 Cabot Boulevard. Mansfield. MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

AM-427
TYPICAL PERFORMANCE
VOLTAGE NOISE VS.
FREQUENCY

CURRENT NOISE VS.
FREQUENCY

10

TA .. +25°C
Vs'"' ±15V

........

I'- .....

r-t

r-

l/F CORNER = 2.7 Hz

111111111
100

10

0.1 L-...J......L..L.l..U.w....-'--'-J...U..llll_.L....1~.I.llJJ
10K
10
100
lK

1000

FREQUENCY (Hz)

FREQUENCY (Hz)

VOLTAGE NOISE VS.
TEMPERATURE

VOLTAGE NOISE VS.
SUPPLY VOLTAGE

--

ATJ

I-I--

- -......-

H-::

-

f--f--- ~

AT 1 kHz

ArltO Hz

I
AT 1 kHz

I

I
-50

-25

25

50

100

75

10

125

TEAlPERTURE (0C)

CMRR VS. FREQUENCY

!
i
Q

VCM = ±10V

i

['..
100

'"~

"-

80

150
TA = +25°C _
140
120
100

=- ~

NEGATIVE
~SUPPlY

80
50

~

40

;0

20

ffi

~

POSITIVE
SUPPLY

I

~

~
~

~

60
102

104

10"

105

FREQUENCY (Hz)

OPEN LOOP GAIN VS.
FREQUENCY

MAXIMUM UNDISTORTED
OUTPUT VS. FREQUENCY

130

I'..

.....

,

50
30

I"-

10

.....

-10
10

100

lK

10K

E

28

~

24

~

20

~

16

§

12

II 111111

...

.....

70

tOOK

FREQUENCY (Hz)

~

10·

FREQUENCY (Hz)

90

40

PSRR VS. FREQUENCY

TA = +25°C
Vs = ±15V
120

30

20

TOTAL SUPPLY VOLTAGE = (V + to V - )(VOLTS)

140

110

•

TA = +25°C

Vs'" ±15V

1M

"
10M

100M

I

I

TA = +2SOC
Vs = ±15V

"lK

10K

tOOK
FREQUENCV (Hz)

-

1M

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10M

4-13

AM-427
TYPICAL PERFORMANCE AND APPLICATIONS
SLEW RATE, GAIN BANDWIDTH
PRODUCT, PHASE MARGIN VS.
TEMPERATURE

GAIN, PHASE SHIFT VS.
FREQUENCY

1

~.M
Vs

~GBW

+15V

.t-.

20

==
-

15

.

~

"

5
0

SLEW

I 11111

5

70"
M~RGIN

-25

0

25

501

75

100

120
140

160

\

'.0

r---..

'00

1\
10

125

100

"\

-1 0

-75 -SO

TC '" 2S"c .
Vs = ±15V

'p~!~~'\

0

=

IIIIII

"I"tWJ

"-GAIN

220
100

FREQUENCY (MHz)

TEMPERATURE (Oe)

INSTRUMENTATION AMPLIFIER
R5
500 (0.1%)

R3

R.
20K (0.1%)

R,

390

lOOK

>V'N

C,
1000 pF

r-I

>-_>--0 VauT

R.

R,

500 (0.1%)

19.8K

RIO
500
TRIM R, FOR AAvL = 1000
-=TRIM RIO FOR DC CMRR
TRIM R, FOR MINIMUM VauT AT VCM = 20Vp·p, 10kHz

The AM·427 is particularly useful in instrumentation applications. In a single difference amplifier configuration,
the AM-427 exhibits excellent common mode rejection and spot noise voltage so low, it is dominated by the
resistor Johnson noise.
The three amplifier configuration shown avoids the low input impedance characteristics of difference
amplifiers. Because of the additional amplifiers used, the spectral noise voltage will increase from a typical of 3
nV/v'HZ to approximately 4.9 nV/v'HZ. The overall gain of the circuit is set at 1000, and with balanced source
resistors, a CMRR of 100 dB is achieved.

ORDERING INFORMATION
MODEL NO.

AM-427-1A
AM-427-1B
AM-427-2A
AM-427-2B

4-14

PACKAGE
a·Pin Ceramic DIP
a·Pin Ceramic DIP
a·Pin TO-99
a·Pin TO-99

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

AM·430
Ultra·Low Drift,
Monolithic Operational
Amplifier
FEATURES
• 0.6 Microvolts/oC maximum drift
• 25 Microvolts maximum input offset
voltage.
• 2.5 MHz Bandwidth
• 107 Open loop gain
• 9 nV/$z Voltage noise
• ±4 nA Maximum bias
GENERAL DESCRIPTION
The AM-430 is a chopperless, ultra-low
drift monolithic operational amplifier. Excellent input characteristics in conjunction
with 2.5 MHz unity gain bandwidth make
this amplifier extremely useful for precision integrator, biomedical, and low level
signal amplification applications. This
amplifier features 25 microvolts maximum
input offset voltage, eliminating the need
for external zeroing in most applications,
and a maximum input offset voltage drift of
only 0.6 microvolts/DC; specifications that
rival those of more expensive chopper
stabilized amplifiers.
Other significant features include 10 7 open
loop voltage gain, 100 dB minimum common mode rejection ratio, and ± 4 nA
maximum bias current. The AM-430 also
has low input noise characteristics of 9
nV/..jFfZ voltage noise density and 0.2
pAl..jFfZ current noise density. Output
voltage range is ± 10V minimum at ± 25
mA load current with a short circuit protected output.
Dynamic characteristics include a settling
time of 11 microseconds to 0.1 %, and a
minimum slew rate of 0.5V/microsecond.
Its unique combination of specifications
make the AM-430 ideal for transducer
amplification, threshold detector applications, low drift active filters and preCision
D/A converter output amplifiers.

+SUPPLY
7 OFFSET ADJ
1 8

-INPUT

2
>-----6----0 OUTPUT

1 ..0325(.2~ I

o '.5(4

70Ir~£

0500(12701

£0

00

0

0.370 (9.40)

•

0030 (761

0045(1141
INSULATOR

0.017 orA
8 LEADS

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

4·19

AM-4S0, AM-460 SERIES
ABSOLUTE MAXIMUM RATINGS

AM·450

AM·452

Power Supply Voltage •••.•••...•..•••••...•
Differentiallnput Voltage ••....••.•••.......
Peak Output Current ••..•..............•...

±20V
±lSV
SO mA

±20V
±lSV
50 mA

AM·460
±22.SV
±12V
Short Circuit Protected

AM·462
±22.SV
± 12V
Short Circuit Protected

AM·450

AM·452

AM·460

AM·462

±10V
SO Meg
20 Meg
±4mV
20 nA
50 nA
125 nA
250 nA

±10V
100 Meg
20 Meg
±S mV
20 nA
50 nA
125 nA
250 nA

±llV
300 Meg
40 Meg
±3 mV
5 nA
25 nA
5 nAB
25 nA

± l1V
300 Meg
40 Meg
±3 mV
5 nA
25 nA
5 nA
25 nA

±10V
±10 rnA

±10V
±10 rnA

±10V
±10 mA

±10V
±10 rnA

25kVN
500 kHz
12 MHz

15kVN
1600 kHz
20 MHz

150k VN
75 kHz
12 MHz

150k VN
600 kHz
100 MHz

30V/pSec.

120V/~sec.

7V/pSec.

35V/pSec.

330 nsec."
90 dB
74 dB

200 nsec."
90 dB
74 dB

1.5 pSec. 4
100 dB
74 dB

FUNCTIONAL SPECIFICATIONS
Typical at +25°C, ±15V dc supplies, RL

= 2K, unless otherwise noted.

INPUT CHARACTERISTICS

.....

Common Mode Voltage Range', minimum
Input Resistance •••.••••.•••......•••..•..
Input Resistance, minimum •••.••.•.•••••...
Input Offset Voltage .••.••..•..••....••.••..
Input Offset Current, typical .••.....•••••.••
maximum •••..•.•••.••.
Input Bias Current, typic:al ..•........•..•...
maximum ••.••...•••••••
OUTPUT CHARACTERISTICS
Output Voltage, minimum .••••••....••••..••
Output Current, minimum7 •..•.•..•..•...•..
PERFORMANCE
DC Open Loop Gain" .•.•••.••••••••.••••.••
Full Power Bandwidth" ••.•.......••..•....•
Gain Bandwidth Product •••..........••.•..•
SlewRate ••••••.....•••••.•••••.•..•.••••
SelllingTime,10VtoO.l% •..••••••.........
Common Mode Rejection Ratio', typical ....••
maximum ••••
Input Offset Voltage Drift •••..••.•..••••••...
External Compensation Required ••••...••....
Power Supply Rejection Ratio ...............

None
90 dB

Gains <3
90 dB

Gains <3
90 dB

1.0 ~sec.
100 dB
74 dB
15 ~V/·C
Gains 

PIN

......

40

~

0

g

~

1
20

r\

180"

i'-

-20
lK

'0

lOOK

10K

1M

100M

10M

FREQUENCY (Hz)

2
3
4
5
6

FUNCTION
OFFSET ADJUST
-INPUT
+INPUT
-vs
OFFSET ADJUST
OUTPUT

+vs
BANDWIDTH
8
CONTROL
ON AM-460, AM-462 THE CASE
IS CONNECTED TO·SUPPLY
7

AM-452
~

~
~

~
i!;

g

~

-

120
100

111111

IIIIII

60

PHASE

60

~II
.,....

40

\.

GAIN

20

III
III

-20

100

10

10K

lK

lOOK

100M

10M

1M

FREQUENCY (Hz)

AM-460

EXTERNAL OFFSET ADJUSTMENT
AND BANDWIDTH COMPENSATION
(ALL MODELS)

120

Vs = ± 15V

ii"tOO ~
!!.

~

60

~

r--.......

60

"'l ,,~,)

TA = +25"C

......

'-.....
~

g
20

ffi
i!;

0"

~PHASE ' "

40

i!;

f---

~

~

-

OFFSET ZERO ADJ
100 Kfl (AM-460, AM-462)
20 KO (AM-450, AM-452)

-IN <>----1
-20
10 Hz

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz:

>---------I

AM-462

1

Joo

pF'

'CONNECT FROM OUTPUT TO
GROUND WHEN COMPENSATION
IS USED ON AM460 AND AM462
MODELS ONLY

120

NOTE: PINS SHOWN FOR TO-99 CASE

iii'100

!!.
Z

60

~

~

60
40

i!;
g

20

*

r-..

.......

'"

-20
10 Hz 100 Hz

0"

' " G'-'1/l

I--....

"-

20°

60°

i'..

PHASE

100°

~

I

i
~

140"

\.\

1

1 kHz

10 kHz

100 kHz

1 MH;;-:

10 MHz 100 MHz

FREQUENCY (Hz)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

4·21

AM-4S0, AM-460 SERIES
TYPICAL PERFORMANCE CURVES
OPEN LOOP FREQUENCY RESPONSE AND
EXTERNAL BANDWIDTH COMPENSATION

INPUT BIAS AND OFFSET CURRENT
VS.TEMPERATURE
AM-450 AND AM·452

II 1111111
'pF

AM..60 AND ""'.462

11111111

1111111

IIIIIII!

"pF

11111111

~

-

t'-..

I

r--- t---

""pF

li-!IllIII
,.,. pF

~

OFfSE~

r-"

~

~M-452

",OK
FREQUENCY

--

AM-450 BIAS

t!iI1!III-

300pF

IIIHI

VSUPPlY '" ± 15V
AM-4LeIAS

OFFSET

-AM-4~

(tu1

NOTE: EXTERNAL COMPENSATION COMPONENTS AAE NOT REQUIRED
FOR STABUTY, BUT MAY BE ADDED TO REDUCE BANDWIDTH IF DESIRED

I

-20

-...;;

I

.---

rr-

'\

..,." V

F::"'

+25

+50

t75

+100 +125

TEMPERATURE (DC)

-40
-55_50 -25

0

+25

+50

+75

TEMPERATURE (Ge)

: 11111111 1111111

~

'''''III 1111111

::.::
"'pF

11111

SOpF

~

100 pF

111111l000pF
11111
10K

lOOK

I

OPEN LOOP VOLTAGE GAIN VS.
TEMPERATURE

COMMON MODE VOLTAGE
RANGE VS. SUPPLY VOLTAGE
AM-4&OANOAJot.462
10M

FREQUENCY (Hz)
NOTE: EXTERNAL COMPENSATJON IS REQUIRED fOR CLoseD LOOP GAIN <:3

AM-46O AND AM-462

OV~R OPERA~NG
TEMP.
RANGE

./

/

V

V

V

./'"

1.t20vLpPl)
±15V SUPPLY

!

±1 0V SUPPlY

~ 100

±5VSUPPLY

--

~

-t-

'"

85

-55 -35

105

SUPPLY VOLTAGE (V)

FREQUENCY (tk)
NOTE: EXTERNAL COMPENSATION COMPONENTS ARE NOT REQUIRED
FDA STABILITY, BUT MAY BE ADDED TO REDUCE BANDWIDTH IF DESIRED
IF EXTERNAL COMPENSATION IS USED, ALSO CONNECT 100 pF CAPACITOR
FROM OUTPUT TO GROUNO

ORDERING INFORMATION
MODEL NO.

m 100

Fs:;:~E<''''''--+

~

I--~"""P.A~~.Y.I---

"~
~

60

AM-450-2
AM-450-2M
AM-452-2
AM-452-2M
AM-460-2
AM-460-2M
AM-462-2
AM-462-2M

§ ,,~~-~--~~~~~~
~ '~-4~-r--~--~~~~
10 Hz 100 Hz

1 kH~

10 kHz

100 kHz

1 MHz

OPERATING
TEMP. RANGE

ooe
-55°C
ooe
-55°C
ooe
-55°C
ooe
-55°C

to
to
to
to
to
to
to
to

+ 70°C
+125°e
+ 70°C
+125°e
+ 70°C
+ 125°C
+ 70°C
+125°e

ACCESSORIES

Part Number

Description

TP100K. TP20K

Trimming Potentiometers

10 MHz

FREQUENCY (Hz)
NOTE: EXTERNAL COMPENSATION IS REQUIRED FOR CLOSED LOOP
GAIN <5. IF EXTERNAL COMPENSATION IS USED, ALSO
CONNECT 100 pF CAPACITOR FROM OUTPUT TO GROUND.

4-22

DATEL.lnc. 11 Cabot Boulevard. Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

125

AM·464·2
High Voltage, Monolithic
Operational Amplifier

FEATURES

• ± 35V Output swing

• ± 10V dc to ±40V dc supply
• 4 MHz Gain bandwidth
• 5 VIMicrosecond slew rate
• 74 dB Minimum CMRR

GENERAL DESCRIPTION

BANDWIDTH

The AM-464-2 is a monolithic IC operational amplifier with an input common
mode voltage range of ± 35V dc and an
output voltage swing of ± 35V dc when
operated from a ± 40V dc supply. Along
with high voltage performance, this amplifier has a 4 MHz gain bandwidth product
and a 5 V/microsecond output slew rate. It
is particularly useful in data conversion circuits and other signal processing applications where higher than normal common
mode voltage and output voltage swings
are required. The AM-464-2 is internally
compensated for all gains and has an onchip temperature sensing, output currentlimiting circuit for absolute output shortcircuit protection.
Other features of this amplifier include:
common mode rejection of 74 dB minimum, input bias current of 30 nA maximum, and open loop voltage gain of
100,000 minimum. The output slew rate of
5 volts per microsecond gives a 70 volt
peak-to-peak sinusoidal output voltage at
up to 23 kHz. The power supply voltage
can range from ± 10V dc to ± 40V dc to
give output swings from ±5V to ±35V.
Power supply quiescent current is only 3.2
rnA typical.
The AM-464-2 is packaged in an 8-lead,
hermetically sealed TO-99 case and may
be used as a pin-for-pin replacement for
general purpose IC operational amplifiers
such as 741, 101, and 108 for higher
voltage applications. Operating temperature range is DoC to + 70°C for the
AM-464-2.

4
-SUPPLY

MECHANICAL DIMENSIONS
INCHES (MM)

f f9~1h
~
1+--O.'25

INPUT/OUTPUT
CONNECTIONS

0.175
(4,4)

~O

8 LEADS
0.017 TVP

0.500 MIN

0OD~

PIN

FUNCTION

1

TRIM

2

-IN

3

+IN

4

-SUPPLY

5

TRIM

6

OUTPUT

7

+SUPPLY

8

BANDWIDTH (CBI

NOTE: All LEADS GOLD PLATED KOVAR

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

4-23

AM-464-2
ABSOLUTE MAXIMUM RATINGS
Input Overvoltage ..................... .
Supply Voltage ....................... .
Internal Power Dissipation .............. .

PERFORMANCE PARAMETERS
±37V max.
±50V max.
680mW

OFFSET TRIMMING AND BANDWIDTH
REDUCTION
NOTES:
Cs is not required for
stability since amplifier
is internally compensated. It may be used
to reduce bandwidth.
however. C, = 100 pF
may be required for
stability if external Cs
is used .

+10TO +40Vdc

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ±40V dc supply, unless otherwise noted.
INPUT CHARACTERISTICS

...........

Common Mode Voltage Range
Input Impedance, AM·464·2 .............
Input Offset Voltage, AM·464·2

..........

cL

'" 100 pF

±6 mV max .

Input Bias Current, AM·464·2 ............

30 nA max.

..........

30 nA max.

Input Offset Current, AM·464·2

T

±35V min.
200 Megll

-10 TO -40Vdc

OPEN LOOP FREQUENCY RESPONSE
FOR VARIOUS VALUES OF CB

OUTPUT CHARACTERISTICS
Output Voltage ........................
Output Current" AM·464·2 ..............

±35V min.
±IO rnA min.

Output Resistance .....................
Stable Capacitive Load

500 ohms
100 pF

.................

PERFORMANCE
DC Gain, 5 K!l Load ....................
Common Mode Rejection", AM·464·2 .....

100K VIV min.
74 dB min.

Input Offset Voltage Drift ................
Input Offset Current', AM·464·2 ..........

15 "v/oe
50 nA max.

Input Noise Voltage, 10 Hz·l0 kHz .........

3 "V RMS

-,o~---t---i---;---r---~-_:"1

10

1K

100

100K

10K

10M

10M

FREQUENCY (Hz)

DYNAMIC CHARACTERISTICS
Unity Gain Bandwidth ...................
Slew Rate ............................
Full Power Frequency, 70V peak·to·peak ...

INPUT BIAS AND OFFSET CURRENT
VS.TEMPERATURE

4 MHz
5 V/pSec.
23 kHz

20

15

o~

POWER REQUIREMENTS
Voltage, Rated Performance .............
Power Supply Voltage Range ............
Quiescent Current, AM·464·2 ............

±40V dc
± 10 to ±40V dc
4.5 rnA max.

5

f"-.- tr---

BIAS CURRENT

'":::>
I

0
-25

PHYSICAL/ENVIRONMENTAL

OFFSET CURRENT

+25

I

I

+50

+75

.+100

TEMPERATURE (DC)

Operating Temperature Range, AM·464·2 ..

ooe to + 70 0 e

Storage Temperature Range .............
Package, Hermetically Sealed ............

-65°e to + 150°C
TO-99

INPUT NOISE CHARACTERISTICS
100

'0

FOOTNOTES:

VOLTAGE
NOISE

70

1. Overload protected by current limiting and temperature sensing.
2. For common mode voltage = ± 30V.
3. At maximum operating temperature.

MODEL

10- 12

90

ORDERING INFORMATION
OPERATING
TEMP. RANGE

AM-464-2

O°C to +70°C

ACCESSORIES
Part Number

Description

TP10K

Trimming Potentiometer

~;;;

60

~

50

So

S
z

~

ill
~
ili

'0

~

~
~

~

30

~
~

:0

CURRENT
NOISE

20

10
10,

"

i

10- 13

100

1K

10K

lOOK

FREQUENCY (Hz)

4-24

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339·30001TLX 174388/FAX (508) 339-6356

AM·SOO Series
Ultra·Fast
Operational AmplHier

FEATURES
•
•
•
•
•

•

200 Nanoseconds settling to 0.01%
100VlMicrosecond slew rate
100 MHz Minimum gain-bandwidth
108 Open loop gain
1 Microvolt/°C drift
± 50 mA Output current

GENERAL DESCRIPTION
The AM-SOO series amplifiers are ultra-fast
settling operational amplifiers for use in inverting applications. A unique feedforward
amplifier design combines the characteristics of a low drift dc amplifier with those of
a very fast AC amplifier. For optimum fast
settling performance, this amplifier has an
open loop gain roll·off of 6 dB per octave to
beyond 100 MHz. Miniature thin-film
hybrid construction permits an optimum
combination of semiconductor devices
and minimum lead lengths to realize the
amplifier circuitry. Applications for the
AM-SOO Series include fast integrators,
sample-holds, fast waveform drivers, and
fast D/A converter output amplifiers.
Output settling time is 200 nanoseconds
maximum to 0.01% for a 10 dc volt step
change. Slew rate is 1000V/microsecond
for positive output transitions and
1800VImicrosecond for negative transitions. This high slew rate permits undistorted reproduction of a full load, 20V
peak-to-peak sinewave out to 16 MHz.
Gain bandwidth product is 100 MHz
minimum.
AM-SaO series dc characteristics include a
dc open loop gain of 106 , 30 megohm in·
put impedance, and 1 nanoampere bias
current. Input offset voltage is ± O.S mV
and input offset voltage drift is 1 microvolVoC. Although these amplifiers do not
operate differentially, a dc offset voltage in
the range of ± SV dc can be applied to the
positive input terminal.
Power supply requirements is ± 15 V dc at
22 rnA quiescent current. The amplifiers
will operate over a supply range of ± 10V
to ± 18V dc. Output current capability is
± SO rnA with output short circuit protection. Three basic versions are available:
AM-500GC and AM-SOOMC for O°C to
+ 70°C, and AM-SOOMM for - 5SoC to
+ 125°C. The device package is a 14-pin
ceramic DIP.

INPUT/OUTPUT
CONNECTIONS
NC

NC

NC

-'N

+ 'N

-v.

NC

P'N

FUNCTION
N.C.

.¢

N.C.
N.C.
-INPUT

+ INPUT
-SUPPLY
N.C,

COMMON
N.C.

10
NC

NC

+v.

NC

OUT

NC

COM.

OUTPUT

11

+ SUPPLY

12
13

N.C.
N.C,

14

N.C.

MECHANICAL DIMENSIONS
INCHES (MM)

R
1_

r-

---.L

0.500 MAX,-!

l~

(12,7)

0.190 (4.8) MAX.

-----r---

0.150 MIN.
(3,8)

~

" " 0.010

x 0.Q18 KOVAR

·ORDERING INFORMATION
17

6I
I

MODEL

I BonOM I

t

VIEW

I

I
DOT ON TOP
REFERENCES
PIN 1

I

'-+---+-!I_

0.805 MAX
(20,3)

01~
0.100 0
(2,5)

AM-500GC
AM-500MC
AM-500MM

OPERATING
TEMP. RANGE
DoC to + 70°C
OOC to + 70°C
-55°C to +125°C

SEAL
Epoxy
Herm.
Herm.

For military devices compliant to MIL-STD-883,
contact DATEL.

NOTE: PINS HAVE ±O.01 INCH STANDOFF FROM CASE

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

4-25

AM-SOO SERIES
FUNCTIONAL SPECIFICATIONS, AM-500 SERIES

TECHNICAL NOTES

Typical at 25'C, ± 15V dc supply, unless otherwise noted.

1. The circuit design shows the connection of the AM-SOO series
for fast settling operation with a closed loop gain of - 1. It can
be used for fast settling at closed loop gains up to - 10. The
equivalent resistance seen by the summing junction should
be 500 ohms or less. For gains larger than - 1 use an input
resistor of 500 ohms and pick a feedback resistor for the required closed loop gain (1 k for - 2, 1.Sk for - 3, etc.).

INPUT CHARACTERISTICS
Input Common Mode Voltage
Range' ..•.......••........... ±5V
Maximum Input Voltage, no
damage .........•..•......••. ± 18V
Differential Input Impedance .•..... 30 Meg. typical, 3 Meg. min.
Input Bias Current ................ 1 nA typical, 4 nA max.
Input Offset Current .............. 0.5 nA typ., 8 nA max.
Input Offset Voltage .•....•....... 0.5 mV typ., 3 mV max.
OUTPUT CHARACTERISTICS
Outpu1 Voltage ..................
Output Current, S.C. protected .•...
Stable Capacitive Load ......•.....
Outputlmpedance ...............

2. A small feedback capaCitor should be used across the feedback resistor. Determine C in nanofarads from the following
formula:
1 + IGI
0.816Rf
where G is closed loop gain and Rf is in kilohms.
C

± 10V min.
± 50 mA typ., ± 25 mA min.
100 pF
25!l

PERFORMANCE
DC Open Loop Gain ...•.......... 1D· voltslvolt
Input Offset Voltage Drift,
O'Cto +70'C ........•..... 1 p'v/oe typ., 5 p'v/oe max.
-55°Cto +125'C ............. 5 p'v/oe typ., 10 p'v/oe max.
Input Bias Current Drift,
-55°Cto +70'C .............. -20 pA/oe
+ 70'C to + 125°C ............. doubles every 10°C
Input Voltage Noise,'
0.01 Hz to 1 Hz ................. 5 p.V peak·to·peak typ.,
25 p.V peak·to·peak max.
100 Hz to 10 kHz ............... 1 p.V RMS typ., 5 p.V max.
1 Hzt010MHz ................. 20 p.V RMS typ., 100 p.V max.
Power Supply Rejection Ratio ...... 80 dB min.

3. Summing point leads must be kept as short as possible. Input
and feedback resistors should be soldered close to the body
of the resistor directly to the summing point (pin 4). Summing
pOint capacitance to ground must be kept very low.
4. Low output impedance power supplies should be used with 1
I'F tantalum bypassing capacitors at the amplifier supply ter·
minals. There are internal 0.03 !,F ceramic capaCitors in the
amplifier.
5. Although these amplifiers are inverting mode only, a dc volt·
age in the range of ± SV may be applied to the positive input
terminal for offsetting the amplifier.
6. For interrupted power applications, apply power to the
AM-SOO three (3) seconds before operating the device.

CONNECTION FOR FAST SETTLING
WITH GAIN OF -1

DYNAMIC CHARACTERISTICS
Gain Bandwidth Product. .......... 130 MHz typ.,
100 MHz min.
Slew Rate, positive going .......... 1000V/p.sec.
Slew Rate, negative going ......... 1800V/p.sec.
Full Power Frequency
(20V peak-ta-peak) ............... 16 MHz
Settling Time,
10V step to 1%3
'" ......... 70 nsec.
10V step to 0.1%3 ......•....... 100 nsec.
10V step to 0.01 %3 ..........•.. 200 nsec. max.
Overload Recovery Time .......... 10 !,sec.

=

+15Vdc

2.4pF

KEEP THEse
LEADS AS SHOAT
AS POSSIBLE
11'F TANTALUM
INPUT

"

o----'VI/II'--'-..,
.......--"--~OUTPUT

ZEAO
AOJ.
(±10mV)

POWER REQUIREMENTS

,
20K

Voltage, rated performance ........ ± 15V dc
Voltage, operating ............... ±10Vdcto ±18Vdc
Quiescent Current. .....•......... 22 mA typ., 33 mA max.
PHYSICAUENVIRONMENTAL
Operating Temperature Range
AM-500GC •..•................ Doe to + 70°C
AM-500MC .................... DoC to + 70°C
AM-500MM .....•.............. - 55°C to + 125°C
Storage Temperature Range ....... - 55°e to + 125°C
Package Type ... , ...•........... 14 pin ceramic
Pins .•.............•....•.....• 0.010xO.018" Kovar
Weight. , ..........•.........••. 0.09 ounces (2.5 grams)

_15Vdc

INPUT BIAS CURRENT VS. TEMPERATURE

:
,

,,,
,

i

~

~

10nA

II' n" r--

~

C

FOOTNOTES:

1. dc only
2. - 3 dB Single·pole bandwidth
3. 1k Input and feedback resistors, 2.4 pF feedback capacitor

4·26

'CU1AENT
100 pA

.

',ATYP.@

i.........

,

V

/

,, h~BLES
,
EVERY

'1/

r\i,

10~C

-CU~RENT

I

TEMPERATURE (0e)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

AM·542, AM·543
Programmable Gain
Instrumentation Amplifiers

FEATURES
•
•
•
•
•

1 to 1024 Gains
Digital gain selection
109 Input impedance
6 Microseconds settling time, AM-543
1 MicrovolU·C offset drift, AM-542
• ±3 to ± 18V dc Analog supply range,
AM-542
• 6 mV Peak-to-peak output voltage
noise, AM-543

°

INPUT OFFSET ADJUST WIPER

G '" 1024

GENERAL DESCRIPTION
The AM-542 and AM-543 are high performance, digitally controlled, Progammable
Gain Instrumentation Amplifiers. The
AM-542 permits selection of gains from 1
to 1024 in 11 binary weighted steps, while
the AM-543 permits selection of gains
from 1 to 128 in 8 binary weighted steps.
Gain selection is accomplished by the input of a 4-bit word. One version is optimized for low drift with extremely low noise
and the other is optimized for fast settling.
Use of these devices in data acquisition
applications yields a system with wide
dynamic range and high resolution.
The AM-542 is optimized for low drift performance, having an input offset voltage
drift specified at only 1 microvolt/oC, while
the gain temperature coefficient is a maximum of only ± 5 ppm/oC. Other specifications include an input impedance of 109 0,
Common Mode Rejection of 90 dB minimum, and an output voltage range of ±
10.5V dc minimum at 5 mAo The AM-542
operates from analog supply voltages from
± 3V dc to ± 18V dc with very low power
dissipation.
The AM-543 is tailored for high speed applications; a 20V dc step settles to 0.01 %
in only 6 microseconds maximum at unity
gain. These devices also feature a slew
rate of 13V1microseconds, an input impedance of 10120, Common Mode Rejection of 80 dB minimum, and a gain
temperature coefficient of ± 10 ppm/DC
maximum. The AM-543 operates with
analog supply voltages from ± 10V de to
± 16V dc.
Both devices are packaged in a compact,
hermetically sealed 24-pin ceramic DIP
and are available for operation over the
O°C to + 70°C, - 25°C to + 85°C, and
- 55°C to + 125°C temperature ranges:

4A

+INPUT

4R

2R

•

I

1

:

R

I
I

,

J___ G...:=_2_, G '" 512

G '" 1

L -________

I

~

G = 1024

,-~_;c______,

MECHANICAL DIMENSIONS
INCHES (MM)

..L
0.150 MIN
(3,8)

5C=.T

--.----

0.010

I

0.19 MAX (4,8)

13,

,
,
,
,
,

,
,
,
,
,

BonOM
VIEW

, 1

,
,
,
,
,
,
,
,
,
,

240

J.,1,"

11 SPACES
AT 0.100
EA (2.5)

(33,3)

----0

L
I

0.600 ---'
(15,2) -

-[

+tNPUT

2

Ne
Ne

3

•

,'200

L

0.100

1(2,5)

NOTE: PINS HAVE 0.025 INCH STANDOFF FADM CASE, ±O.Ol"

FUNCTION

I

5
6

x 0.018

KOVAR

,,2

DOT ON TOP REFERENCES
PIN 1

P,N

I
1

L 0.800
MAX
-'
1(20,3) ~

INPUT/OUTPUT
CONNECTIONS

lOGIC SUPPLY

Ne
-15Vdc

7

Ne

8

ANALOG COMMON

•

10
11

OUTPUT OFFSET ADJUST

OUTPUT OFFSET ADJUST
OUTPUT

12

FEEDBACK

13

Ne
As
A4

14
15
16
17

,.
16

A2

AD
Ne
+ 15V de

20

POWER COMMON

21

INPUT OFF. ADJ. WIPER

22

INPUT OFFSET ADJUST

23

INPUT OFFSET ADJUST

2'

-INPUT

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

4-27

AM-542 and AM-543
ABSOLUTE MAXIMUM RATINGS
Positive Supply, Pin 19 ....... .
Negative Supply, Pin 6 ....... .
Input Voltage Range ......... .
NoDamage ................ .

AM-542
+22V de
-22V de
± 20V de
±vee

AM-543
+ 16V de
-16V de
±20V de
±vee

FUNCTIONAL SPECIFICATIONS

PHYSICAL/ENVIRONMENTAL
Operating Temperature Range
MC ......................
MM'· •..........••......
Storage Temperature Range .•
Package Type ..............

Typical at + 25°C, ± 15V dc and + 5V dc supplies, unless otherwise noted.
INPUT CHARACTERISTICS
Input Offset Voltage, adjust
tozero ....................
Input Bias Current, max.
MCmodels ................
MRfMM models ............
Input Offset Current, max.
MCmodels ..•......•......
MRfMM models ............
Input Impedance, Diff. Mode ..
Com. Mode ..
Common Mode Volt. Range min.'
Digitallnputs, Logic 1, min.' ....
Digital Inputs, Logic 0, max. . ...

AM-542
± 200 ,.V dc, max.

AM-543
±200,.V de

±50 nA
± 14 nA

±50 pA
±50 pA

±50 nA
±14 nA
10"!!
2 x 10"!!
± 11V de
+ 2.4V de at 2 p.A
+ 0.8V de at 50 p.A

±50 pA
±50 pA
10'2!!
10'2!!
± 10.25V dc
+ 2.4V de at 2 p.A
+ 0.8V de at 50 p.A

± 10.5V de
±5 mA
± 1 mV dc

± 11V dc
±1 mA
±12 mVde

6 mV dc (P·P)

7 mV (P-P)

Gain Range ......•.....•....
Gain Accuracy, max •..........
Gain Nonlinearity, max ..•.....
Gain Temp. Coefficient, max ..•.
Input Offset Temp. Drift,
Oto + 70°C ......•.........

1 to 1024
±0.02%
0.005%
±5 ppm/oe

1 to 128
±0.05%
0.01%
± 10 ppm/oe

1 ,.V de/oe

+ 70°C to + 85°C ....•....••

5,.V de/oe

+85°Cto +125°C .........•

10 p.V defoe

Power Supply Reject. Ratio, min.
Input Current Noise, max .•.....
Common Mode Rejection Ratio,
60 Hz, min.· .......•.......
DC,min.' ........•........
Small Signal Bandwidth,
(-3 dB)
G 1 ....................
G 1024 .................
Slew Rate ...................
Settling Time, 20V de to 0.01%,

80 dB
90 pA (P·P)

30 p.V de/G
+30 p.V defoe
35 p.V de/G
+30,.V de/oe
40,.V de/G
+30 p.V dc/oe
80 dB
270 pA (P-P)

86 dB
90 dB

86 dB
80 dB

500 kHz
500 Hz
0.14V de/p.see.

13V de/,.see.

OUTPUT CHARACTERISTICS
Output Voltage Range, min.' ...
Output Current, min •..........
Output Offset Voltage, max. 4 •••
Output Voltage Noise,
dc to 1 MHz, max." •....•....

7MHz

-

max.

G
G
G
G
G
G
G

= 1 ....................
= 16 ...................
= 64 ...................
= 128 ..................
= 256 •.................
= 512 •..•..............
= 1024 .................

FOOTNOTES:
1. As with any three amplifier instrumentation amplifier configuration,
the voltage at either input ± % the output voltage must not exceed
± 12V de (± l1V de - AM543) for linear operation.
2. Requires pull up resistor for TTL logic. Please refer to technical
note 3.
3. AM·S42, Al
2kU. AM'S43, Al
'OKU.
4. G = 1, adjustable to zero.
5. AM·S42, As
SkU, G
1024. AM·S43, As
SkU, G
128.
6. Maximum for AM-S42MM/MR. Maximum for AM·S42MC is

=
=

=

=

=

=

±O.O5%.
7. Maximum for AM~542MM/MR. Maximum for AM-S42MC is 0.010/0 .
8. DC to , kHz.

9. 1KO source imbalance, G

=:

2.

10. AM-542 only.

TECHNICAL NOTES

PERFORMANCE

=
=

o to + 70°C
-55 to + 125°C
- 65 to + 150°C
Hermetically sealed
24·Pin DIP

150 p.see .
200 p.see.
400 p.see.
400 p.see.
700 p.see.
1.4 msee.
2.8 msee.

6 p.see.
10 p.see.
40 p.sec.
100 p.see.

-

1. The AM-542 and AM-543 have an offset adjustment capability for each
stage, input and output. The output trim
should be sufficient to zero out offset
errors on the lower gain ranges, adjustment should be made with a gain of 1
selected. For the higher gain ranges,
the input offset zeroing circuit should
be used to optimize accuracy. Adjustment of the input offset should be made
with a gain of 1024 selected on the
AM-542, and a gain of 128 selected for
the AM-543.
2. Power supply inputs to the AM-542 and
AM-543 are bypassed internally.
However, for best performance both
power supplies should be bypassed
with 1 microfarad electrolytics in
parallel with 0.01 microfarad ceramic
capaCitors as close as possible to the
± supply pins .
3. The digital inputs of the AM-542/543
are TTUCMOS-compatible. However,
when interfacing with TTL logic, it is
recommended that 10 kO pull-up
resistors be used. When interfacing
with CMOS logic, the logic supply pin
(pin 4) should be connected to the
system logic supply.

POWER REQUIREMENTS
Analog Supply, Rated Value .... ± 15V de at 20 mA, max. ± 15V dc at 40 mA, max.
Analog Supply Range .........
±3V de to ± 18V dc
±10V de to ±16V de
Logic Supply ................ +3V de to + 18V de at
+3V de to +18V de at
5 nA max.
5 nA max.

4-28

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

AM-542 and AM-543
CONNECTION AND APPLICATION
OFFSET ADJUSTMENT

The AM-5421543 are functionally laser trimmed to reduce initial offset
voltage and offset voltage change due to gain change to a minimum level_
However, for critical applications where zero offset is required, the following procedure can be followed to externally zero the offset
/1_ Allow the Amplifier to reach
4_ Adjust R2 for zero output
operating temperature_
5_ Set gain to 1024 (128-AM-543)
2. Set R, and R2 to mid-range.
VN
3. Set gain to 1 VN.
6. Adjust R, for zero output.
This technique minimizes the offset voltage change over the maximum
change in gain. Trimming may cause input offset temperature drift to
increase slightly.

+15Vdc

r--'--o

GAIN STATE TRUTH TABLE
OUTPUT

A,(PIN 14)
+5V

101Ul

1,.1

10kfl

0.011.11
-15V

10k!]

10kll
PUlL·UP
RESISTORS

AO

A2

A4

AS

GAIN PROGRAMMING
INPUTS

DIGITAL INPUTS
GAIN
A (PIN 15) A.(PIN 16) A (PIN 17) AM·542 AM-543
1
2

1

0
0

0
0

0
0

0
1

0

0

1

0

4

4

0

0

1

1

8

0

1

0

0

16

8
16

0

1

0

1

32

32

0
0

1

1

64

64

1

128

128

1

0

1
0

0
1
0

256

1

0

0

1

512

1

0

1

0

1024

-

.:

2

HIGH ACCURACY/HIGH SPEED DATA ACQUISITION SYSTEM
I
HIGH SPEED

:

MED. ACCURACY I
CHANNELS

MX-1616

I

I

ADC·HZ128

n BITS

n BITS
LOW SPEED
HIGH ACCURACY

MXD·B07

CHANNELS

DATA BUS

This diagram shows a system that uses the AM-542 with high gain, high accuracy, low-to-moderate speed transducers and the AM-543 with
moderate gain, moderate-to-high speed transducers.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

4-29

AM·542 and AM·543
TYPICAL APPLICATIONS
HIGH SPEED DATA ACQUISITION SYSTEM
r---- ---,
I

I

r - -,

..

LOAD

Ao

A2

A4

As

CLEAR

MSB

MSB

THREE
DM-8095

STATE

OUTPUT
DATA

BIT 6
BIT 6
SHM·6

Ace-617

ENABLE

BIT 7

HOLD

BIT 7

MUX ENABLE

THREE

STAAT

STATE
OUTPUT

OM-B09S

DATA

lSB
lSB

EOC

This diagram shows a high-speed data acquisition system with 8 differential inputs and 12-bit resolution using the AM-543. If the control logic is
timed so that the Sample-Hold-ADC section is converting one analog value while the mux-amplifier section is allowed to settle to the next input
value, throughput rates greater than 156 KHz can be achieved. The AM-543 is used with Datel's ADC-817, a 12-bit hybrid AID with a 2 Msec conversion rate, the SHM-6, a 0.01 %, 1 I'sec hybrid Sample-Hold, and the MX-1616, a low cost, high-speed, monolithic analog multiplexer.
The system works as follows:
The MP selects a channel and initiates a conversion at G = 1 and then looks at the MSB of the conversion result. If the MSB = 1, the I'P will store
the value. If the MSB = 0, the I'P will select G = 2. The I'P will repeat the cycle of gain incrementing, comparison, and analog-to-digital conversion until the MSB = 1. The I'P will then test for an output of all 1's, as this is the full-scale output of the AID. If the output is all 1's, the I'P will
decrement the gain by 1 step and perform the final conversion.

MICROPROCESSOR BASED OAT A ACQUISITION SYSTEM

ORDERING INFORMATION
MODEL NO.
A typical application of the AM-542/543 is in a microprocessor controlled data acquisition system. The microprocessor loads the
RAM with thedesired gain coding. Thiscoding relates the selected
gain ranges to a specific address. When the processor instructs
the multiplexer to multiplex a particular analog input channel, this
instruction is also received by the RAM, which puts out the appropriategain code to the AM-542/543. This system allows acquisition
of signals over a wide dynamic range at high resolution.

4-30

AM-542MC
AM-542MM
AM-543MC

OPERATING
TEMP_RANGE

O°C to + 70°C
-55°C to + 125°C
O°C to + 70 0 C

For military devices compliant to MIL-STD883, consult DATEL.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

AM·551
Low Cost, Programmable
Gain Instrumentation Amplifier

FEATURES
• 1 to 1000 Gain range

• ± 0.01 % Maximum nonlinearity
• 2 Microseconds settling time
• 100 dB CMRR
• Low cost
GENERAL DESCRIPTION
DATEL's AM-551 is a low cost, high performance, programmable gain instrumentation amplifier manufactured with hybrid
thin-film technology. Gain is adjustable
over a range of 1 to 1000 by the addition of
a single external resistor and a simple
user-selectable pin-strapping option. Maximum gain nonlinearity is ± 0.01 %.
The AM-551 dynamic characteristics include a settling time of 2 microseconds for
a 20V dc output step to 0.01 % accuracy.
Slew rate is 23V dc/microsecond and
small signal bandwidth is 400 kHz. Other
specifications include a common mode rejection ratio of 100 dB, a 10120 input impedance and a minimum output voltage
swing of ± l1V dc. Maximum offset
voltage drift is ± 15 microvolts/oC.
The AM-551 is a self-contained, functionally complete device, containing a high impedance variable gain voltage follower input stage followed by a differential output
stage with user selectable gains of 1 or 10.
High accuracy, ultra-low drift thin-film
technology is used in the fabrication of all
interconnected resistor networks.
The combination of high accuracy, speed,
low cost, and rugged hybrid construction
make the AM-551 an ideal choice for applications involving the remote amplification
of low-level signals produced by thermocouples, strain gages and RTD's, high
performance data acquisition systems and
remote instrumentation systems.
Power requirement is ± 15V dc and all
devices are cased in miniature, hermetically sealed, 16-pin ceramic packages.
Models are available for operation over the
commercial, O°C to + 70°C industrial,
- 25°C to + 85°C, and military, - 55°C to
+ 125°C operating temperature ranges.

INPUT OFFSET ADJUST

-INPUT ,05) _ _--<

II

GUARD ("13N--------~

~
9~

OUTPUT OFFSET ADJUST

>--.....J\,/'./\r......---"vvv---------l77) SIGNAL COMMON
+ INPUT ,'3'.1----1"

MECHANICAL DIMENSIONS
INCHES (MM)

INPUT/OUTPUT
CONNECTIONS

PIN

T

r=-"~~~"-=-i

0,300

INPUT OFFSET ADJUST

2

RG (Gain Resistor)

3

+ INPUT

4

RG (Gain Resistor)

5

- INPUT
-VS

17,6)

..L-~~~~.,..,...J
PIN 1
IDENT

6

~

T
""

0~5

0,03510,9)

~'I'"

...L

I'

---I (.... 0 100
II
I I 12.51 I r

16·PIN CERAMIC DIP

0018
10,46)

FUNCTION

1

7

SIGNAL COMMON

8
9

OUTPUT OFFSET ADJ. WIPER

10

OUTPUT OFFSET ADJUST

11

OUTPUT

12

OUTPUT GAIN SELECT

13

GUARD

OUTPUT OFFSET ADJUST

14

+VS

15

INPUT OFFSET ADJUST

16

INPUT OFFSET ADJ. WIPER

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

4-31

AM-551
TECHNICAL NOTES

ABSOLUTE MAXIMUM RATINGS
Positive Supply, Pin 14 ....••..........
Negative Supply, Pin 6 •............•.•
Input Voltage Range ......•.....•.....
Differential Input Voltage Range •......•
Output Short Circuit ................. .
Power Dissipation ..............••....

+18V
-18V
±18V
±30V
Continuous
810 mW

FUNCTIONAL SPECIFICATIONS
Typical at + 25 ·C, ± 15V dc supplies, unless otherwise noted.
INPUT CHARACTERISTICS
Input Offset Voltage, unadjusted', max ...
Input Bias Current, max •...............
Input Offset Current, max ..............
Input Impedance, Diff. or Com. Mode .•..
Common Mode Voltage Range, min ......

± 1 mV x gain
± tOO pA
±20 pA
10'2!)
± 11V

1. A 25 kll trimpot may be used for both input and output offset

adjusts. The trimpot is connected across the input offset adjust pins (Pins 1, 15) and the wiper is connected to Pin 16.
For output offset adjust, the trim pot is connected across the
output offset adjust pins (Pins 10, 9) with the wiper connected
to Pin 8.
2. For unity gain, RG is left open and the output gain select pin
(Pin 12) is tied to the output pin (Pin 11). To avoid oscillation
in the unity gain configuration, the connection between the
output gain select pin and the output pin should be kept as
short as possible.
3. Gain selection is accomplished in two stages. The input stage
gain (G ,) is selected by an external gain resistor (RG) connected across the (RG) pins, (Pins 2, 4) and is expressed as
follows:

G, =

OUTPUT CHARACTERISTICS
Output Voltage Range, min.- ......•....
Output Current, min •..................
Output Impedance3 • • • • • • • • • • • • • • • . • • •
Output Offset Voltage, unadjusted', max.

1

+

20k

RG
±11V
+5 mA
-0.5!)
± 1 mV x gain

PERFORMANCE
Gain Range" .........................
1 to 1000 VN
Gain Equation 7 • • • • • • • • • • • • • • • • • • • • • • • G = (1 + 20klR G)G 2
Gain Accuracy, max .•.........•......•
±0.04%
Gain Nonlinearity, max .................
±0.01%
50 ppmloC
Gain Tempco, max? ..................
Offset Voltage Drift, max. . . . . . . . . . . . . . .
15 ~VI·C
Input Bias Current Drift ...........•.... Doubles for e$z 10°C
Input Voltage NOise, dc to 100 Hz . . .. . . . .
20 nVI Hz
82 dB
Power Supply Rejection Ratio, min. ......
Common Mode Rejection Ratio·
1 kHz .............................
96 dB
100Hz ............................
98 dB
dc ...............................
100 dB
SlewRate ...........................
23 VI~sec.
Small Signal Response, (- 3 dB)
400 kHz
G 1 ............................
150 kHz
G 10 ...........................
100 kHz
G 100 .........................•
G 1000 .........................
40 kHz
Settling Time, 20V to 0.01%
2.0 ~ec .
G 1 .................... ........
G 10 ...........................
4.6~ec.
G = 100 .........•...............•
20 ~ec.
200 ~sec .
G 1000 ............. ..... .......

The output stage gain (G 2) is selected by external pinstrapping: For G 2 = I, connect the gain select pin (Pin 12) to
the output pin (Pin 11). For G 2 = 10, connect the gain select
pin (Pin 12) to the signal common pin (Pin 7).
The total gain of the amplifier (is as f;~:W)S:
Gt

= G,

x G2

=

1

+

R;

G2

4. Both power supplies should be bypassed to ground with 0.1

microfarad electrolytic capacitors.

=
=
=
=
=
=
=

POWER REQUIREMENTS
Rated Power Supply Voltage ............
Supply Current, max. .................
Power Supply Range ............•....•

± 15V de
±27 mA
±5V to ± 18V

PHYSICAL/ENVIRONMENTAL
Operating Temperature Range
MC ..............................
MM ..............................
Storage Temperature Range ............
Package Type .......................

DoC to + 70°C
-55°C to + 125°C
-65°C to +150°C
16-Pin Ceramic DIP

FOOTNOTES:
1. Adiustable to zero.
2. R, = 2 k!l
3. At 1 kHz, for ali gain ranges.
4. To 0.01 % accuracy. Higher gains are achievable, however, performance will
degrade.
5. Tempco of RG = ± 0 ppm/oe. For RG = 00. Gain Tampeo = 5 ppm/oC
6. 1 k!l Source Imbalance.
7. G2 is the gain of the second stage of the AM-SSI. Connecting output gain select
(Pin 12) to the output (Pin 11) sets the second stage gain at 1. Connecting output
gain select (Pin 12) to signal common (Pin 7) sets the second stage gain at 10.
~ is the gain resistor for the first stage and is connected to RG (Pins 2, 4).

4-32

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 0204S-11941TEL (50S) 339-30001TLX 1743SSfFAX (50S) 339-6356

AM-551
TYPICAL CONNECTION DIAGRAM
+15V

(-) Input

(+) Input

AM·551

11
1

---<> Output

**

AG

II

GUAAD
DAIVE

** See application note '3
BRIDGE
EXCITATION

TYPICAL BRIDGE TRANSDUCER INTERFACE

+V,

G
5 Kn

/7"-,
/

I

r-_-+ _____-,-1-;'/c../_ _....\ , -_ _ _......z5 -INPUT
I

I

\

I

I

I

25 KI1

1

1

7 COMMON
I I
I
I
I
\
I
" ) - - - ' " , - ' c , - - - : l - - - - - - { 3 + INPUT

AM·551

OUTPUT

/

\,

',"

INPUT
OFFSET
ADJUST

1

\

/

"

I

"
I ''

II

"

GUARD

I

AM·'60

The AM-551 is shown configured ina typical bridge application. Low level, high impedance sources, such as this, require proper
shielding and grounding, particularly in noisy environments. Shielding of the input leads as well as the gain resistor will minimize induced noise.
The AM-551 provides a guard output to drive the input cable shield at the input common mode voltage, greatly reducing noise
pick-up and system bandwidth degradation as well as improving AC CMRR.
* Connect Pin 12 to Pin 11 for a gain selection of G = (1

Connect Pin 12 to Pin 7 for a gain selection of G

(1 +

+

~:)

2~:) 10

Refer to Technical Note #3 for more information.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

4-33

AM-551
GUARD DRIVE CONNECTION

, ,

~

EIN

\

I I

\

I I

\

A guard (pin 13) is provided to improve AC common mode rejection by compensating for unbalanced capacitance due to long
input leads. Use of the guard function is recommended where
input leads are longer than a few inches. In cases where the input leads are very long or where system bandwidth is very high,
the addition of a buffer amplifier is recommended. The diagram
shows a typical guard drive connection to the AM-551 using
DATEL's AM-460.

t--\I\--\-\.-+.l----(
\

AM-460

HIGH SPEED DATA ACQUISITION SYSTEM

"

AOC-811

AM·551

"

MX·1616

8
DIFF.
INPUT

I

,,

CHANNELS I

,,
I

CH.81

.L-_ _- '

START

AOA1A2A3

CAOCA1 CA2 CA3 CLR LO

DELAY

STROBE

This diagram shows a high speed data acquisition system employing the AM-551. This system is capable of a 130 kHz throughput
rate with 12-bit resolution. In this system. the AM-551 is coupled with DATEL's MX-1616. a 0.01% high speed multiplexer.
SHM-4860, a 0.01% high speed sample/hold and ADC-811. a 12-bit, 4 microseconds hybrid analog to digital converter. Although
shown with a differential front end, 16 single input channels can also be used.
"The guard drive circuit (AM-460) is only necessary when using long lead lengths between the MUX and the AM-551.

ORDERI.NG INFORMATION
MODEL NO.

OPERATING
TEMP. RANGE

AM-551MC
AM-551MM

OOC to + 70°C
-55°C to + 125°C

ACCESSORIES
Parts Number

Description

TP25K

Trimming Potentiometer

For military devices compliant to MIL-STD-883. contact
DATEL.

4-34

DATEL, Inc. 11 Cabot Boulevard. Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

AM-7650
Low Cost
Chopper-Stabilized
Operational Amplifier

FEATURES

• ± 5 Microvolt maximum input offset
• 0.05 Microvolt/OC maximum offset
drift
• Low cost
• 110 dB Minimum CMRR
• 10 pA Maximum input bias

GENERAL DESCRIPTION
The AM-7650 is a low cost, monolithic
chopper-stabilized operational amplifier
fabricated using CMOS technology. The
amplifier consists of a main dc amplifier,
nulling amplifier, output clamp, compensation circuit, and switches controlled by a
two-phase oscillator. The extremely low
offset voltage drift, 0.05 microvoltlOe
maximum, and the initial input offset voltage of only ± 5 microvolt maximum eliminate the requirement for external zero adjustment in most applications.
The amplifier achieves its low offset by
comparing the input voltages to a nulling
amplifier that spends alternate clock
phases nulling itself and the main
amplifier. Two external capacitors, the
only external components necessary, are
required to store the correcting potentials
on the two amplifier nulling inputs. The
compensation circuit minimizes the intermodulation between the applied signal
and the chopping frequency. The output
clamp circuit reduces the over-load recovery time of the amplifier.
Besides providing virtually glitch-free output and very fast recovery from overloads,
the AM-7650 offers differential inputs,
maximum input bias current of 10 pA, input noise voltage of only 2 microvolt peakto-peak, and an input resistance of 10 120.
Unity gain bandwidth product is 2 MHz,
CMRR is 110 dB minimum and the open
loop gain is a minimum of 120 dB. Long
term stability is typically 100 nVI ,jmnth.
The clock oscillator and all the other circuitry is entirely self-contained, however,
the AM-7650-1 includes a provision for the
use of an external clock, if required for a
particular application. In addition, the
AM-7650 is internally compensated for
unity gain operation.
Any application where system performance can be significantly improved by a
reduction in input offset voltage and bias
current is right for the AM-7650. These applications would include inverting or noninverting amplifier configurations, strain
gauge pre-amplifiers, nulling amplifiers,
and low offset comparator circuits.
The AM-7650-1 is packaged in a 14-pin
DIP and the AM-7650-2 is packaged in an
a-lead, hermetically sealed TO-99 case.
Models are available in the 0 to + 70 0 e
operating temperature range.

,---------".J

OUTPUTut_ _--i
CLAMP

INT/EXT
EXT CLOCK IN
CLOCK OUT
OUTPUT

+in

C EXT B

-Vs

CEXT A

II

+Vs

I________-===~==========================~ CRETN

INPUT/OUTPUT CONNECTIONS

MECHANICAL DIMENSIONS
inches (mm)
..,--- r"'-'c.L.CL..D..~'-Tl

AM·7650·1

0.225
(5,72)

~ S·"...,...,.....".-TT1"TTT'

PIN

1
2

3
4

5
6
7

'--Q

~

0.185

(4,699) .

~ -

0.500 I
,

~-

-vs

(9,40)

10
11
12
13
14

FUNCTION
C RETURN
OUTPUT CLAMP
OUTPUT

+vs
INT CLOCK OUT
EXT CLOCK IN
I NT/EXT

0.035

AM·7650·2

- I

--+-. '"-.U UU" 0.040 11.016)
0.370

PIN
8
9

1.- (O,esll)

"

112[O)JU

FUNCTION
C EXTB
C EXTA
NC (GUARD)
-IN
+IN
NC(GUARD)

~. INSULATOR

-.,

~O~~A~~'

PIN

1
2
3
4

FUNCTION

PIN

C EXTA

5

-IN

6
7
8

+IN

-vs

FUNCTION
OUTPUT CLAMP
OUTPUT

+vs
C EXTB

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

4-35

AM·7650
ABSOLUTE MAXIMUM RATINGS
AM-7650-1 AM-7650-2
18V
Power Supply Voltage ( + V. to - VJ .... .
Input Voltage ....................... .
(+V. +0.3)10
(-V. -0.3)
Lead Temperature (soldering,
10 seconds)
300°C
Oscillator Control Voltage (Pins, 12, 14)' .
±V.
10mA
Current into any Pin ............ : .... .
100 p.A
Current into any Pin while operating' ... .
Total Power Dissipation .............. .
375mW
250mW

FUNCTIONAL SPECIFICATIONS
Typical at 25 ·C, ± 5V supplies unless otherwise noted.
INPUT CHARACTERISTICS
Input Resistance .....................
Input Offset Voltage, maximum> ........
Input Bias Current, maximum' ..........
Input Offset Current ..................

10'2Q
±5 ~V
10 pA
8 pA

OUTPUT CHARACTERISTICS

PHyslCAUENVIRONMENTAL

. ........

Operating Temperature Range
O°C 10 + 70·e
Storage Temperature Range ...........
-55·C 10 + 150·C
Package ........................... 14 Pin Plaslic
8 Pin
DIP
TO-99
FOOTNOTES:
1. AM-7650-1 only. Voltage on EXT CLOCK IN

= (+ V, +0.3V) to (V, -6.0V)
2. Limiting input current to 100 pA is recommended to avoid latCh-Up problems.
Typically 1 rnA is safe, however, it is not guaranteed.

3. Specified at 25°C. Typically ± 1.0 microvolts over temperature (O°C to
+ 70°C).
4. Specified at 25°C. Typically 35 pA over temperature (O°C to + 70°C). Doubles
every 10°C.
5. OUTPUT CLAMP not connected. RL = 10 kll. With RL = 100 kG, the output
voltage swing is typically ± 4.95V.
6. RL = 10 kll.
7. Rs = 1000. 0 to 10 Hz.
8. CL = 50 pF, RL = 10 kO.
9. Pins 12 and 14 open (DIP).
10. See Technical Note 2.

TECHNICAL NOTES

Output Voltage Swing, minimumS .. : ....
Output Short Circuit Duration

..........

±4.7V
Indefinile

PERFORMANCE
Large Signal Voltage Gain, minimums ....
Input Offset Voltage Drift, maximum .....
Long Term Stability ..................
Common Mode Voltage Range,
minimum .........................
maximum .........................
Common Mode Rejection Ratio,
minimum .........................
Power Supply Rejection Ratio,
minimum .........................
Input Noise Voltage 7 •••••••••••••• _ •••
Input Noise Current, 10Hz .............
Unity Gain Bandwidth .................
Slew Rate8 • . . . . . • . • • • . • • • . . . • • • . . . • •
Rise Time ..........................
Overshoot ..........................
Internal Chopping frequency,.
minimum .........................
maximum .........................
Clamp ON Current'., minimum .........
Clamp OFF Current'· .................

10·VIV
0.05 ~V/oC
100 nV/"jmonlh
-S.OV
+3.5V
120 dB
120 dB
2 ~V peak-Io-peak
0.01 pA/Hz
2.0 MHz
2.5V/~ec
0.2 ~ec

20%
120 Hz
375 Hz
25 p.A
1 pA

POWER REQUIREMENTS
Power Supply Range ( + V. to - VJ,
minimum .........................
maximum .........................
Power Supply Current (no load),
maximum .........................

4.5V
16V
3.2 rnA

1. NUll-storage capacitors should be connected to the C EXTA
and C EXTB pins, with a common connection to the C RETN pin
(for the AM-7650-1) or the - Vs pin (for the AM-7650-2). This
connection should be made directly by either a separate wire
or PC trace to avoid injecting load current IR drops into the
capacitive circuitry. The outside foil, where available, should
be connected to C RETN (or - Vs for TO-99). CEXTA and CEXTB
have optimum values which depend on the clock or chopping
frequency. For the preset internal clock, the correct value is
0.1 ",F. If an external clock is used, the value of C EXTA and
C EXTB should be scaled approximately in proportion in order
to maintain the same relationship between the chopping
freqency and the nulling time constant. A high quality filmtype capacitor such as mylar is preferred, however, a ceramic
or other lower-grade capacitor may be suitable for many
applications. For the quickest settling on initial turn-on, low
dielectric absorption capacitors (such as polypropylene) are
recommended.
2. To reduce overload recovery time which is inherent with
chopper-stabilized amplifiers, tie the OUTPUT CLAMP to the
inverting input pin or summing junction. A current path between this point and the output pin occurs just before the
device output saturates. Thus, uncontrolled differential inputs
are avoided, along with the consequent charge build-up on
the correction-storage capacitors. The output swing is slightly
reduced.
3. To avoid latch-up, no voltage greater than O.3V beyond the
supply rails should be applied to any pin. In general, the
amplifier supplies must be established either at the same
time or before any input signals are applied. If this is not
possible, the drive circuits must limit input current flow to
under 1 mA to avoid latch-up, even under fault conditions,

4. All of the AM-7650's inputs are static-protected by the use of
input diodes. However, strong static fields and discharges
should be avoided as this can cause degraded diode junction
characteristics, which may result in increased input-leakage
currents.

4-36

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

AM-7650
5. The open loop gain of this amplifier will be 17 dB a lower with
a 1 kflload than with a 10 kflload. If the device is used strictly
for dc applications, the lower gain is of little consequence
since the dc gain of this device is greater than 120 dB with
loads down to 1 kfl. For wide band applications, the best
frequency response will be achieved with a load resistor of 10
kfl or greater. This will result in a smooth 6 dB/octave
response from 0.1 Hz to 2 MHz, with phase shifts of less than
10° in the transition region where the main amplifier takes
over from the null amplifier.
6. Due to thermo-electric or Peltier effects arising in the
thermocouple junctions of dissimilar metals, alloys, silicon,
etc., special precautions should be made to avoid
temperature gradients. All components should be enclosed
to eliminate air movement, especially that caused by powerdissipating elements in the system. Low thermoelectric-coefficient connections should be used where possible and power
supply voltages and power dissipation should be kept to a
minimum. High impedance loads are preferable, and good
separation from surrounding head-dissipation elements is
recommended.

7. Care must be taken in the assembly of printed circuit boards
to take full advantage of the AM-7650's low input currents.
The boards should be thoroughly cleaned with TCE or alcohol
and blown dry with compressed air. After cleaning, the
boards should be coated with epoxy or silicone rubber to
prevent contamination. Even with properly cleaned and
coated boards, leakage currents may cause trouble, particularly since the input pins are adjacent to pins that are at
supply potentials. This leakage can be significantly reduced
by using guarding to lower the voltage difference between the
inputs and the adjacent metal runs. Input guarding of the
a-pin TO-99 package can be accomplished by using a 10 lead
pin circle, with the leads of the device formed so that the
holes adjacent to the inputs are empty when the device is
inserted into the board. The guard which is a conductive ring
surrounding the inputs, is connected to a low impedance
point that is approximately the same voltage as the inputs.
Leakage currents from high-voltage pins are then absorbed
by the guard. The pin configuration of the 14-pin DIP version
is designed to facilitate guarding since the pins adjacent to
the inputs are not used.

PERFORMANCE

SUPPLY CURRENT VS.
SUPPLY VOLTAGE

........-

---

/

SUPPLY CURRENT VS.
AMBIENT TEMPERATURE

/

/

/

10

14

12

_5L-__

16

~

o

__

~

12.5

____

~

__

~

37.5

25

__

50

~

70

TOTAL SUPPLY VOLTAGE (V)
AMBIENT TEMPERATURE (0C)

MAXIMUM OUTPUT CURRENT
VS. SUPPLY VOLTAGE

"...

/

--

10Hz pop NOISE VOLTAGE
VS. CHOPPING FREQUENCY

r-

~

~

~

\

i'--- r--......

-20

-30
2

10

-12

TOTAL SUPPLY VOLTAGE (V)

+2r---r---r---r---r---r-~

+1r---r---r---r---r---r-~

~

\
-10

INPUT OFFSET VOLTAGE CHANGE
VS. SUPPLY VOLTAGE

~ -t~__~__~__~__~__~~
:--....

r-16

~~

o

-2~__~__~__~__~__~~

_3L-_ _L -__L -__L -_ _L -_ _
4
10
12
14

L-~

10

100

1K

CHOPPING FREQUENCY (CLOCK OUT) (Hz)

10K

16

TOTAL SUPPLY VOLTAGE (V)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

4-37

AM-7650
PERFORMANCE
INPUT OFFSET VOLTAGE
vs. CHOPPING FREQUENCY

OPEN LOOP GAIN AND PHASE SHIFT
vs. FREQUENCY
160 I

+B
UJ

CD

+6

"0

..... +4

(!)
0..

100

ff

...J

BO

UJ
0..

60

(!)

~

'\

140

~

z

<

~

UJ

0
0

u..
0+2

Z

v

o

0

40

10
100
1K
10K
CHOPPING FREOUENCY (CLOCK·OUT) Hz

"
--

120

50

"\,

70

,-

'\

"

0.1

90

" '"

RL = 10K

f- CEr =11PF

0.Q1

..,

10

100

1K

110
130

I"

10K

100K

FREQUENCY Hz
VOLTAGE FOLLOWER LARGE SIGNAL
PULSE RESPONSE

+2


+1

CLOCK OUT

UJ
(!J

-

+2


f-

-1

::J

0

-2

IL

+1

'~"

~

§2
f-

::J
0..

f-

~

\

UJ

HIGH

0

12f-

~

VOLTAGE FOLLOWER LARGE SIGNAL
PULSE RESPONSE

-1

::J

t\ j\

0

CLbcK

I'"

-2

0.5

1.5

r~~~

CLOCK OUT
LOW

~

~~

-

2.5
0.5

TIME· "S

1.5
TIME "S

THE TWO DIFFERENT RESPONSES CORRESPOND TO THE TWO PHASES OF THE CLOCK

N·CHANNEL CLAMP CURRENT
vs. OUTPUT VOLTAGE
100 "A
10 "A

V

1 "A

.....

Z
...JUJ
UJe:
Ze:
Z:::>
«u
I 0..
q::;;
Z«
...J
U

P·CHANNEL CLAMP CURRENT
vs. OUTPUT VOLTAGE

-

10 "A

1/

100 nA

1 "A

.....
z
...JUJ 100 nA
UJe:
ze:
Z:::>
«u 10 nA
I a.
q::;;
1 nA
0..«

L

10 nA
1 nA

r-

100 "A

/

; -r--

...J

100 pA

U

/

100 pA

1/

10 pA
10 pA
1 pA

+O.B

+0.6

+0.4

OUTPUT VOLTAGE AV-

+0.2

o

/

1 pA
-O.B

-0.6

-0.4

-0.2

OUTPUT VOLTAGE AV +

4-38

DATEL. Inc. 11 Cabot Boulevard. Mansfield. MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

o

AM-7650
CONNECTION
INPUT GUARD CONNECTION
INVERTING AMPLIFIER

YOl TAGE FOLLOWER

"2

>-.......---0

'>--.....- - - 0

OUTPUT

IN

OUTPUT

0--;""';'--1

SUGGESTED

SUGGESTED

BOARD LAYOUT AM-7650-2

BOARD LAYOUT AM-7650-1

NON-INVERTING AMPLIFIER
EXTERNAL

"3'

CAPACITORS

EXTERNAL
CAPACITORS

I \

II

"

+VS

OUTPUT . . .
'7 8 "
EXTERNAL
CAPACITORS

76~
3~'" ~CJ
• 5

4

g,~

-Vs

>--~'----o OUTPUT

2

GUARD
BOTTOM

~

view

THIS LAYOUT REQUIRES A
to-PIN LEAD CIACLE.

CeXTA
R11A2 COMBINATION

(~

CeXTa

) MUST BE LOW IMPEDANCE

Rt +A2

·COMPENSATES FOR LARGE SOURCE RESISTANCE

BonOMvrEW

TYPICAL CONNECTION
NON·INVERTING AMPLIFIER WITH
OPTIONAL CLAMP

0.1 /-IF 0.1 /-IF

INVERTING AMPLIFIER WITH OPTIONAL
CLAMP

A2
IN 0-------1
CLAMP
AM-7650

>--+---() OUTPUT IN
AM-7650

CLAMP

A3 + (A 1I/A2) ~ 100Krl
FOA FULL CLAMP EFFECT

>--"""--0 OUTPUT
CEXTB

0.1 /-IF 0.1 /-IF
(A 1I/A2) ~ 100Krl
FOA FULL CLAMP EFFECT

The AM·7650 can be used in any application where the performance of a circuit can be significantly upgraded
by improved input offset voltage and bias current. This application shows the basic connection for inverting
and non·inverting configurations of the AM·7650. The "Output Clamp" function is used to improve the
overload recovery performance.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

4-39

AM-7650
APPLICATION

DIFFERENTIAL PRE-AMP FOR ADC-7109

Two AM-7650s may be used with Datel's ADC-71 09, 12-bit integrating AID converter to construct a preamplifier for signals from bridge type transducers such as strain gages. The circuit will maintain high differential
gain without any common-mode gain.
This circuit also works well with thermocouples in noisy environments where shielding is grounded at the sensing end.

LOW OFFSET COMPARATOR

BOOSTING OUTPUT DRIVE CAPABILITY

+ 7.5V -7.5V
0.1 /-IF 0.1 /-IF

>---0 OUTPUT
OUTPUT
~_~_-v~_OTHRESHOLD

VOLTAGE

2M

10K

10K

The AM-7650 will operate well as a low offset comparator. Other
chopper amplifiers perform poorly under overload conditions. However, the optional overload avoidance feature (output clamp) allows
the AM·7650 to be used in many of these applications.

The AM-7650 is an ideal replacement for any operational
amplifier with the only limitations being the supply voltage (± 8V
max) and the output drive capability, (10 kG load for a full output
swing). These limitations can be overcome by using a booster
amplifier as shown.

ORDERING INFORMATION
MODEL NO.
AM-7650-1
AM-7650-2

4-40

OPERATING
TEMP. RANGE

o to
o to

+ 70°C
+ 70°C

PACKAGE
Plastic DIP
TO-99

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

SCM.100, SCM·101
Four·Channel, Isolated
Signal Conditioning Modules

FEATURES
• Wide input span range
• 4-Channel operation
• ± 1000 Volts peak isolation voltage
• 156 dB CMR
• ± 0.02% Maximum nonlinearity
• ± 1 Microvolt! °C input offset drift
• Low cost

SCM-100, SCM-101

GENERAL DESCRIPTION
The SCM·l00 and SCM-l0l are low-cost,
high performance signal conditioning
modules designed to interface with lowlevel thermocouple and high-level analog
input signals respectively. Each module is
a functionally complete unit, consisting of
four individually isolated input channels
multiplexed into a single output amplifier.
Common Mode isolation is ± 1000 volts
peak.

II

The SCM-100 is optimized for low level
signal conditioning. An input span range of
±5 mV to ± 100 mV and common mode
rejection ratio of 156 dB minimum make
this module an ideal choice for interfacing
with thermocouples or strain gages, where
low level signals require amplification in
the presence of high common mode voltages. The SCM-100B features a maximum gain temperature coefficient of ± 25
ppm/oC and an input offset temperature
drift of only ± 1 microvolt/oC maximum.
The SCM-101 is optimized for ± 50 mV to
± 5V or 4-to-20 mA input signals. Other
specifications include a minimum common
mode rejection ratio of 145 dB, a maximum gain temperature coefficient of ± 25
ppm of FS/oC and a maximum input offset
voltage drift of ± 5 microvolt/aC.
All mOdels feature a minimum channel
scanning rate of 400 channels/second.
Long term stability is specified at 1.5
microvolts/month and gain nonlinearity as
low as ± 0.02% maximum. Their combination of functionally complete deSign, wide
input range, high noise rejection, small
size, and low cost make these devices an
ideal choice for applications involving
multi-channel data acquisition systems,
computer interface systems, process signal isolators, and temperature measurement and control instrumentation.
Each device is packaged in a compact
2" x 4" x 0.4" encapsulated module.

MECHANICAL DIMENSIONS
INCHES (MM)

r-- 2"l&,~8~01 ~1----.l..

PIN

14°o ±0.01

t

(10,2)

'T----:=c:-----rr'.250 MIN

,-

:36 - - - - - - - - - - - - - :

39:

~29

~:,~
v

37~

.,

::

BonOM
VIEW

3.000

PIN

FUNCTION

dot!' desiQnale
omitted pms.

FUNCTION

1

- CHAN. D. SELECT

40 CHAN A RGICOMMON

2

+ CHAN

41

D. SELECT

CHAN A LOIOFFSET

3 SWT. OUTPUT ENABLE

42 CHAN A (-1150. POWER

4 SWITCHED OUTPUT

43

6 DIRECT OUTPUT

47 CHAN B HI INPUT

7 OUTPUT SENSE

NOTE: Open

43~ 17AV.~ES

49 CHAN B AG

9 OUTPUT OFF ADJ
11

OUTPUT POWER,

CHAN A (+) ISO. POWER

50 CHAN B RGICOMMON
t5V

51

CHAN B LO/oFFSET

~:O.'lEACH4.000 (101,6

12 OUTPUT POWER, COMMON

52 CHAN B(-) ISO. POWER

13 OUTPUT POWER, -t15V

53 CHANB(-t)ISO.POWER

15

- CHAN C SELECT

56 CHAN C HI INPUT

52:

18

-tCHANCSELECT

58 CHANRG

""

"19 ____________ 54 0
:18

1

INPUT/OUTPUT CONNECTIONS

+0.02
2.100

---------- ~~
58:
61:

,,:
:6

":
67:

_

70:

-1 _ _ _ _ _ _ _ _ _ _ 72_

CHAN B SELECT
21

+ CHAN 8

17 SPACES
AT.1oo

r:

59 CHAN C RGICOMMON

SELECT

30 OSCILLATOR POWER,

80 CHAN C LO/OFFSET

+ V.

61 CHAN C ( ) ISO. POWER

31 OSCILLATOR POWER,
COMMON

62 CHAN C (-t) ISO. POWER

32 SYNC IN

66 CHAN D HI INPUT

33 SYNC OUT

88 CHAN D RO

35

- CHAN A SELECT

36

-t CHAN A SELECT

69 CHAN D RGICOMMON

10 CHAN D LOIOFFSET

31 CHAN A HI INPUT

11

39 CHANARG

12 CHAND(-t)ISO.POWER

CHAN D (-) ISO. POWER

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

4-41

SCM-100, SCM-101
FUNCTIONAL SPECIFICATIONS
Typical at +25°C, ± 15V dc supplies, unless otherwise noted.
INPUT CHARACTERISTICS

SCM-l00A

SCM-l00B

Number of Channels ......
4
4
InputSpanRange ........ ±5mVto ±100mV ±5mVto ±100mV
Input Offset Voltage, max.' .
±20 flV
±20flV
0.6flV pop
0.6flV pop
Input Noise Voltage" ......
Input Bias Current, max....
+8 nA
+8 nA
Input Resistance
100 M!)
100 MO
PowerOn ..............
35K!)
35K!)
Power Off, min.
Common Mode Voltage
Range",
ac,60Hz .............
750V RMS
750V RMS
ac or dc, max..........
± 1000 V pk
±1000 V pk
Common Mode Rejection
RatiO"',
min., G = 1000 ........
156 dB
156 dB
128 dB
G=50 ..........
128 dB
G = 100 .........
G = 1 ...........
Nonnal Mode Input
Without Damage 60 Hz ..
130V RMS
130V RMS
Nonnal Mode Rejection,
55 dB
min., G = 1000 ........
55 dB
G = 100 .........
Open Input Detection Time"
G = 1000 ............
6 sec.
6 sec.
120 sec.
120 sec.
G = 100 .............

SCM-l0l
4
±50 mV to ±5V
±50 flV
0.6 flV pop
+8 nA
100 MO
74KO
750V RMS
±1000 V pk

PHYSICAl/ENVIRONMENTAL
Operating Temp.
Range .......
Storage Temp.
Range .......
Relative
Humidity9 .....
Case Size ......

ooe to + 70 0 e
-55°e to +85°e
o to 85%
2" x 4" x 0.4"
(50,8 x 101,6 x 10,2 mm)

FOOTNOTES;
1. Adjustable to zero.
2. Rs = lKO, 0.D1 Hz to 100 Hz.
3. Channel to channel or channel to ground.

4. Rs '" 1000, I " 50 Hz.
145 dB
110 dB

5. Response time can be reduced by addition of
external resistors.

6. Short circuit protected.
7. Gain nonlinearity is specified as a percentage of

130V RMS

output signal span representing peak deviation
from the best straight line.
a. A negative gain error is purposely introduced to

55 dB

allow all channels to be matched at G

= > 1 by

trimming the input gain. The gain is then set by the

output gain adjustment.
9. To + 0.01 % lull scale .

OUTPUT CHARACTERISTICS
TECHNICAL NOTES
Output Voltage Swing" ....
Output Offset Voltage,

max. 1

...............

Output Noise,
dc to 100 kHz ..........
Output Resistance
Direct Output ..........
Switched Output .......

±5Vat ±5 mA

±5Vat ±5 mA

±5Vat ±5 mA

±12 mV

±12 mV

±12 mV

0.8 mV pop

0.8 mV pop

0.8 mV pop

O.W

O.W

O.W

350

350

35!)

PERFORMANCE
Gain Equation ........... G = 1 + 10k(JfRG G = 1 + 10k(JfRG G = 1 + 10K(JfRG
Gain Nonlinearity7,
-0.2% min. to
max., G = 1 to 100•....
-0.55% max.
G = 50 to 300 ....
±0.03%
0.02%
Typical, G = 1000 ......
±0.03%
±0.03%
±35 ppmloe
Gain Temp. Coet., max....
±25 ppm/oe
±25 ppm/oe
Input Offset Temp. Drift,
± 1 p'v/oe
±2.5 flV/oe
±5 flV/oe
max.................
Input Offset Drift vs Time ..
± 1.5 flVlmonth
± 1.5 flV/month
± 1.5 flVlmonth
Output Offset Temp. Drift,
max.................
±50 flV/oe
±50 flV/oe
±50 flVloe
Total Offset Drift, RTI,
max................. ± (2.5 + 50/G) flV/oe ± (1 + 50/G) flVloe ±(5 +50/G) flVloe
Channel Selection Time",
max.................
2.5 msec.
2.5 msec.
2.5 msec.
Channel Scanning Speed,
min.................. 400 channels/sec. 400 channels/sec. 400 channels/sec.
Channel Select Input
Reverse
Voltage Rating, max.....
3V
3V
3V
POWER REQUIREMENTS
Analog Supply, rated value.
Analog Supply Range, max.
Analog Supply Current,
max. ±V. = 15Vdc ....
Oscillator Supply, rated
value ................
OSCillator Supply, absolute
value max. ...........
Oscillator Supply Current,
max.+vor,= +15V ....
Power Supp y Sensitivity,
RTI
Analog Supply .........
Oscillator Supply .......

4-42

±15Vdc ±10%
±12Vdcto ±18Vdc
±4 mA
+ 13.5V de to + 24V de
+26V de
40 mA
lflVN
lflVN

1. To minimize coupling between input
and output, keep all leads associated
with signals on the input as far as possible from leads associated with output
signals. The use of a guard track on
both sides of the board (see typical connection) may be helpful. The power
supplies should be decoupled with tantalum capacitors mounted as close to
the device as possible.
2. For lowest noise, the grounding
scheme shown in the typical connection diagram should be used. To prevent power supply currents from flowing
in the low lead of the signal output, the
output signal common should be tied
directly to the output power common
pin (pin 12), with the power supply
returns brought separately to pin 12.
3. When using an unregulated power
source for the oscillator, a 0.1 /If
capacitor should be connected directly
from the output power common (pin 12)
to the oscillator power common (pin
31). Since the output and oscillator circuits are not fully isolated, a dc path
must exist between the two power supply commons. A one or two volt potential difference between the two power
supply commons will not affect
operation.
4. Channel selection is determined by the
select inputs. Each select input consists of an LED in series with a resistor.
Turning the LED on (± 2:2.5 mAl turns
the channel on, and turning the LED off
(± :5 50 pAl turns the channel off. The
easiest way to use the select inputs is to

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

SCM-100, SCM-101
tie all the Select ( + ) inputs (pins 2, 18, 21 and 36) to + 5V and
drive the Select ( -) inputs (pins 1, 15, 20 and 35) from TTL
logic. Open-collector or totem pole outputs can be w,\ed.
With a + 15V logic supply, a standard CMOS decoder or gate
can supply enough current to drive the select inputs. At
higher CMOS supply voltages, more current than the required 2.5 mA will flow into the select inputs. While this will
not affect operation, it can be brought back to the minimum
value if desired by putting a resistor in series with the decoder
or gate output and the select ( - ) input. For 10V dc operation,
a 2KO resistor should be used and at 15V dc, a 2.9KO.
5. The maximum reverse voltage applied to any select input
must be limited to 3V to avoid damage to the LED. Maximum
forward current should be kept below 25 mAo Select inputs
are isolated from all other circuits in the module and may be
operated at up to ± 50V with respect to output and power
ground. Channels may be selected in any order with no
restrictions on rate or duty cycle - except the 2.5 nanoseconds settling time for channel access. However, selecting
two or more channels simultaneously for more than a few
microseconds will result in very long settling times.

6. Output filtering is not required in most applications, since the
affect of the small carrier-related noise spikes on the output
« 1 = mV peak-to-peak, 100 kHz BW.) drops off rapidly as
bandwidth decreases. To eliminate the carrier noise, a simple
R-C filter (for example - 1KO, 0.0047 I'f) may be used at the
output. Only one filter is required, even when using multiple
modules. However, if the load to be driven has an input
resistance of less than 10 MO, a buffer will be needed.
7. Output errors caused by differences in individual oscillator
frequencies may occur in applications where multiple
SCM-100/101's are used in close proximity or when system
clock signals are present near the isolator. To eliminate these
errors, multiple units may be synchronized by connecting the
Sync Output (pin 33) of one module to the Sync Input (pin 32)
of the adjacent module. The first module of a group may be
synchronized to an external source via the SYNC IN (Pin 32).
Sync wiring should be separated from analog signal runs to
keep noise pickup at a minimum. (See External Synchronization.) The frequency of the external Sync Source (if used) will
have a slight effect on the gain and output offset of the
device. Thus, any adjustments should be made with the
modules synchronized.

II

TYPICAL CONNECTION AND CALIBRATION
INPUT OFFSET AND GAIN ADJUST

GAIN ADJUST - The gain of each channel is independently
adjusted by an external gain resistor (RG)' A trimpot may be
connected in parallel with RG to trim out RG's tolerance and the
modules gain error. RG should be chosen to give an untrimmed
gain slightly less than the desired trimmed gain.
OFFSET ADJUST (optional) - The input offset of each channel
may be fine adjusted with an external trimpot if required. This
fine adjust has a limited range of ± 250 I'V and can be used to
adjust each channel for zero offset while operating at the
desired gain. Since the range of this adjustment is so limited, it
is recommended that the output offset be adjusted first. Output
Offset Adjustment should be made as follows:
1. Select the desired channel.
2. Apply zero volts in and set for unity gain. (This can be done
by disconnecting RG')
3. Set the OUTPUT OFFSET ADJUST for an output of OV.

OUTPUT OFFSET AND GAIN ADJUST
SWITCHED OUT.

41}------o

DIRECT OUT

6i)-....,.-.--O

SENSE OUT

7

5000

OUTPUT GAIN·
ADJ.

POWER COM

OUTPUT OFF ADJ.

I

+15V

SCM-100, SCM-101
10kO

9

~
~

20Kfl
OUTPUT OFFSET
ADJ.

15V

TRIM POTS ARE 10 TURN
GAIN ADJUST RANGE SHOULD NOT
EXCEED 10% TO MAINTAIN GAIN
STABILITY

OPEN INPUT DETECTION
SCM·100/101

SCM·1001101

ONE
CHAN
ITYP\

+-C-"*-D RGleOM

'-+-,,,,,-_.(j LQIOFS

(-)ISO.PWR

4_._-d (+) ISO
(A)

PWR

(B)

Since only a few nA of input bias current is available to charge
the input filter, the response time for open input detection can
be in the tens of seconds. Shorter response times and a positive
overscale if required may be achieved with one of the above circuits which will augment or reverse the input bias current. Either
circuit will supply a bias current of approximately 20 nA which
may be used to aid or oppose the 3 nA supplied from the
module. Circuit A has the advantage of simplicity, however, the
high value resistor may not be readily available. Circuit B solves
the problem at the expense of complexity. The component
values may be varied to give an optimum trade of bias current
for response time as required. The values shown will give a
typical response time of 2 to 5 seconds.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

4-43

SCM-100, SCM-101
TYPICAL CONNECTION

EXTERNAL
SYNCHRONIZATION

SCM·l00, SCM·l0l

(see Tech Note 7)
EXTERNAL SYNC
SOURCE (IF USED,
400KHZ, :!: 10%. IV

15V poP 30% TO 70%
DUTY CYCLE
NOTE', NO
CONNECTION
SHOULD BE MADE

TO THESE PINS FOR
UNSYNCHRONIZED
OPERATION

THERMOCOUPLE TEMPERATURE MEASUREMENT

GUARD TRACK ON PAINTED

'CIRCUIT BOARD. {OPTIONAL)

EXPANSION TO 32 CHANNELS
CHANNEL
SELECT

MODULE
SELECT

eo,

~
OPTIONAL

BUFFER

TO AID

~S~C~M;;,.l;,;OO;;/l;O;;ll100 MO

OUTPUT CHARACTERISTICS
Output Voltage Swing ••.•...•..•..•
Output Resistance;
Direct Output ...••••.••..••...••
Switched Output ................
Max. Switched Voltage ....•..••..•.

±5Vdcal5mA
0.10
350, +0.5%/oe
± 10V dcl

PERFORMANCE
Gain RangeS, RG = 9450 .•.........•
Gain Error, max., G = 50
...•..•.
G = 166.6 .•...••.
Gain Nonlinearity, max. ............
Transfer Function .................

166.6 VN or 50 VN
±0.6%
±0.8%
± 0.01 % of Span

Gain Tempco" ..................•.
Input Offset Temp. Drift ..•••.•.•...
Total Offset Temp. Drift, RTI .......•
Channel Selection Time, max. 7 ••••••
Channel Scanning Speed, min. • ••.••
Input Settling Time,
to ± 0.01 % Full·Scale ......•...•.
Bandwidth .......................
Sensor Excitation Level" ....•...•..•

±25 ppm/oe
± 1 /Lv/oe
± 1 /Lv/oe
300 !'Sec.
> 3000 chan/sec.

Sensor Excitation Level Tempco •....
Power Supply Rejection •.••..•..••.

0.4 sec.
4 Hz

±0.003%/%Vs

POWER REQUIREMENTS
Analog Supply, Rated Value •...••.•.
Analog Supply Current, max.,
+15V ••....•.....••..•..•••...
-15V ••.....••.....•..••..••.•

± 15V dc ±5%

1. Channel selection for the SCM-l03 is
accomplished by applying the proper
binary code to the channel select in·
puts (Pins 22 and 23). Channels may
be selected in any order, the only
restriction being the 300 microsecond
channel selection settling time.
Channel
Select 1
(Pin 22)
0
0
1
1

Channel
Select 0
(Pin 23)
0
1
0
1

Channel
A
B

C
D

2. The SCM-l03 is precalibrated to pro·
vide gains of 50 VN and 166.6 VN.
Gain selection is accomplished by
applying the appropriate binary code to
the gain select input (Pin 24). A logic
high applied to Pin 24 gives a gain of
50 VN while a logic low gives a gain of
166.6 VN. A 2000 potentiometer con·
nected in series with an 8450 resistor
across the RG pins of each channel
will provide ±3% full·scale span ad·
justment.
Gain Select
(Pin 24)
0
1

Gain
166.6
50

3. The gain range of the SCM-l03 may be
expanded by the use of an external
amplifier. A low-drift amplifier, such
as DATEL:s AM-427 should be used to
maintain signal integrity.
4. All unused inputs should be shorted to
common.

+35 mA
-15 mA

PHYSICAL/ENVIRONMENTAL
Specified Temperature Range ..•...•
Operating Temperature Range ••.•...
Storage Temperature Range .......•
Case Size •••...•.....•..•...•.••.

ooe 10 + 70°C
-25°C 10 +85°C
-55°C 10 +85°C
2" x 4" x 0.4"
(50.8 x 101.6 x 10.2 mm)

FOOTNOTES:
1.
2.
3.
4.

Rs = 1 kO
Rs = 1 kO. f
RL = 2 kO
No load

= 60 Hz

5. Gain range may be expanded by use of an external amplifier. Expanded gain range for SCM-103 is 50 VN to

1000VN.
6. Does not include effects of sensor excitation drift.
7. To 0.01% Full Scale.
8. Per channel.

4-46

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

SCM-103
CONNECTION AND APPLICATION
SCM-l03

CALIBRATION

~~MMO:\(-l

~

( ,POWER " ~J=+15Vg¥im

INPUT
OFFSET
ADJUST

ADJUST

- 15V

Each channel of the SCM-l03 has a typical input offset (RTI)
specification of only ±150 ",V. While this is adequate for most
applications, provision has been made for fine adjustment of
the input offset (RTI) of each channel as well as the output
offset (RTO) of the entire module.
To adjust the SCM-l03, short the channel inputs (Pins 37, and
41 for channel A) to common and center the input offset potentiometer. The output offset is then adjusted for a null at the
selected gain. The input offset adjustments of other channels
may then be used to eliminate errors on subsequent channels
that are selected.

L

SCM-l03
Rl -50k!l
} Resistors are metal film
R -10kn mF}

-

,

SWITCH
OUTPUT

SWITCH
INPUT

OIRECT
OUTPUT

~:
3

SWT OUT
ENABLE

CHAN. SEL 1

l

CI"IANNEL

ANALOG
BUS

For calibration of the SCM-1 03 these values should be changed as follows:

CHAN SEL 2

~-------SV

15

INHIBIT
BOUT

"'3

4BIN

'2

3BIN

"

2BIN
lBIN

10
9

.

NC

2.
27
26

161N

25

1SIN

121N

2.
23
22
2'

ltlN

20

NC

141N
131N

lOIN

'0

91N
GNO
NC
CA8

"
12

lAIN

A OUT
2AIN
lAIN
. . ,N

,.

.v,
BOUT

NC
8BIN

7BIN
6BIN
48 IN

CA = CHANNel ADDRESS
Vs " SUPPlY VOLTAGE
NC " NO CONNECTIONS

36IN
28IN

TOP VIEW SHOWN

GNO
NC

lBIN

INHIBIT

I.

17

c.,

15

C.2
CA.

28
27

AOUT

26
2,
2.
23
22
21

BAIN

-vs
7AIN

6AIN
SAIN
4AIN
3AIN

9

20

2AIN

10

19

lAIN

I.'.

"12

INHIBIT

CAl
CA2
CM

17

'3

NC

"N
31N
21N
liN

MVD-807

5BIN

NOTES:

-v,
81N
7IN
61N
SIN

'8

"

-v,
.v,

OUT

19

13

CAl

~

MV-1606

,

.v,

15

"

TECHNICAL NOTES
1. The transfer accuracy of the MV series multiplexers depends
on both the source resistance and load resistance. For example, with zero source resistance and assuming 500 ohms
maximum channel ON resistance, the load impedance must
be at least 5 megohms to achieve 0.01% accuracy. In practice it is recommended that a load impedance of 108 ohms or
more be used. This is a typical input impedance value for
most IC operational amplifiers connected in the follower
mode (see DATEL's AM-400 series) or for IC sample-holds
(see OATEL's SHM-1 C-1, SHM-lM-2, or SHM-20). Source
resistance should be kept as low as possible so that accuracy
or settling time are not degraded. less than 250 ohms is
recommended.
2. For differential operation, either two unity gain buffers or an
instrumentation amplifier (such as OATEl's AM-551) is
recommended as the output load. To maintain high CMR,
source impedance unbalance must be kept to a minimum,
and amplifiers with high CMR should be used.
3. The maximum analog input overvoltage for the MV series is
± 1Vs + 2V I. The maximum digital input voltage is ± Vs. It
should be noted that the logic (channel address) inputs are
protected with resistors and clamp. diodes but the analog inputs are not. Because the analog inputs are not protected,
the low ON resistance is achieved.
4. Channel expansion is accomplished by use of the inhibit input of the multiplexers. To expand the number of channels,
use multiple multiplexers with the inhibit inputs connected to
a decoder.
5. For the MV-808 and MVD-409 it is recommended that 1K
pull-up resistors to the + 5V logic supply be used when the
logic inputs are driven from OTl or TTL circuits. Only these
two models require a + 5V logic supply.

CIRCUIT CONNECTIONS

ANAL OG
INPUTS

MV-1606

OUT

IN

SHM-LM-2

OR
SHM-IC-l

16

-

OUT

-

,.

aUlA

lB
OUT

MVD-807

B'

OUT 8
G :: 1 + 20K/RG (G 2)

8B

(G ::: lor 10)

~N =

10 12 OHMS

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

5-5

II,'

MV SERIES
PERFORMANCE GRAPHS
ON RESISTANCE VS.TEMPERATURE

LEAKAGE CURRENT VS. TEMPERATURE
100nA

350

!.

.,
.......

J'2••J

g300

~

-

....... .,

+25"e

250

55°C

1

200

I 1

~ 150

I I

100
-10

-8

-6

-4

-2

0

",

+2

+4
V, SIGNAL LEVEL (V)

+6

./

./
+8

+10

1""

./ ././

/'

10""

/' //'/

./ ./././

Sir J.3 Ji'fJ.D

l..QJ

/ L LL
l00pA

BREAK·BEFORE·MAKE DELAY
(tOPEN)

/ ' / / /'
V

10pA

7.

50

25

100

125

TEMPERATURE (OC)

VA INPUT
2VIOIV

f--

,

S,ON

(j)
@

S,60N

l-

bUTPUT
WtDlV

.I

I

IY

I

I--

@
@
G)

MV·1606, MV[)..807 CHANNEL OFF OUTPUT LEAKAGE

MV-808 CHANNEL OFF OUTPUT LEAKAGE
MVO-409 CHANNEL OFF INPUT LEAKAGE
MV-l606, MV[).807 CHANNEL OFF INPUT LEAKAGE
MV-808, MVO-409 CHANNEL OFF INPUT LEAKAGE

100rI88CIDlV

NORMALIZED ON RESISTANCE
VS. SUPPLY VOLTAGE

ENABLE DELAY
(tON(EN). tOFF(EN»

~

II
-

J-

~~

~~
~e

ENABlE
DRIVE
2V/DIV

JJ
I II
52 THAU 8 ,6 OFF/

2.2

+ 1250C~TAz, -55°C

w -; 2.0

I

5, ON

lureuT'
2VIOlV

~
fli
Ifi

~

,

1.8

Y,N = OV

.....

1.6

.......

1.4

.........

1.2

1.0

0.8
0.6
±7

±a

-

±9 i10 tff t12 ±13 if4 ±tS
SUPPLY VOLTAGE (V)

I II

\.

I ,

' ......

100 nsecJDlV

ACCESS TIME

I
-

ORDERING INFORMATION

\

r- VA INPUT
2V/DIY

\

8, ON

f
OUTPUT
5V/OIV

I
5 ,6 ON

I

lJ

MODEL NO.

CHANNELS

OPERATING
TEMP. RANGE

MV·808
MV·1606
MV-1606M
MVD-409
MVD-807

8 S.E.
16 S.E.
16 S.E.
4 Diff.
8 Diff.

o to 70°C
o to 70°C
-55to + 125°C
o to 70°C
o to 70°C

2OO.-1D1V

5·6

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

MX Series
4-, 8-, and 16-Channel
CMOS Multiplexers

FEATURES
•
•
•
•
•
•

Dielectrically isolated CMOS
Break-before-make switching
Single-ended and differential
Overvoltage protection
DTLlTTLlCMOS-compatible
7.5 mW Standby power

CMOS

SWITCHES
I-.,.I;-----~-D OUT

GENERAL DESCRIPTION
The MX series analog multiplexers are
4-, 8-, and 16-channel monolithic
devices manufactured with a dielectrically isolated complementary MaS
process.
The
circuits
incorporate
analog and digital input protection
which protects the units from both
overvoltage and loss of power. The
digital inputs are DTUTTUCMOS compatible and address the proper channel by
means of a 2-, 3-, or 4-bit binary code. An
inhibit input enables or disables the entire
device and thus permits expansion of the
number of channels by using several
devices together. Another important feature of these multiplexers is the use of
break-before-make switching to insure
that no two channels are ever momentarily
shorted together.
Transfer accuracies of 0.01 % can be
achieved at channel sampling rates up to
200 kHz and over ± 10V signal ranges.
These multiplexers are ideal for multichannel data acquisition systems where
the multiplexer operates into a highimpedance load such as a sample-hold,
buffer amplifier, or instrumentation amplifier. Channel ON resistance is typically
1.5K at + 25°C and is less than 2K over
the operating temperature range.
Power consumption is only 7.5 mW at
standby and 15 mW at 100 kHz switching
rate. Power supply range is ± 5V to ± 20V.
The devices are packaged in 16 pin or 28
pin DIP's and operate over the O°C to
+ 70°C temperature range.
CAUTION: These are CMOS devices and
may be damaged by static discharge.
Standard anti-static precautions should be
taken to prevent possible damage.

•

INHIBIT

MECHANICAL DIMENSIONS - INCHES (MM)
MX-1606, MXD-807

MX-808, MXO-409

I

DATEl

-W.J..LLW-,-"-,--'-1.J.-'-'-'-,~

0.520

~"~TTI,,~MrXn~1,600rnTr~~~

-LJrrrTTTrTT"TTTT"TTr'

i

0270

PIN 1
PIN1
!DENT

IDENT

I
I- L
-) G1W~~AX
~~
-r I
'070M"
137,31

0
· ' ' ' 1!;
14,5)

('I(~

I ---H- OO:g.~AX
I.J

~,,,:

-1

0.1)40

lI,OI

h~~

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

5-7

MX SERIES
MX-1606

MX-808
ABSOLUTE MAXIMUM RATINGS
Voltage Between Supply Pins •..••..••.•
VREF to Ground, V + to Ground •..•••....
Digital Input Overvoltage .•...••..••....
Analog Input Overvoltage •..•...•......
Package Dissipation, maximum •.•.••.•.

40V
+20V
±[Vs +4V]
±[Vs +20V]
725 mW

40V
+20V
±[Vs +4V]
±[Vs +20V]
1200 mW

MXD-409
40V
+20V
±[Vs +4V]
±[Vs +20V]
725 mW

MXD-807
40V
+20V
±[Vs +4V]
±[Vs +20V]
1200 mW

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, ± 15V supplies, R source < 1K, unless otherwise noted.
MXD-409

MX-1606

MX-808

MXD-807

ANALOG INPUTS
Number/Type of Channels ••..••......••
Input Voltage Range ...................
Channel ON Resistance
Channel ON Resistance, Over Temp •.....
Channel OFF Input Leakage .•......•...
Channel OFF Output Leakage .•...•...••
Channel ON Leakage ........•.........
Channel OFF Input Capacitance .. : ......
Channel OFF Output Capacitance .•......

8 Single-ended
±15V
1.5 Kn
2.0 Kn, maximum
30 pA
1.0 nA
100 pA
5 pF
25 pF

16 Single-ended
±15V
1.5 Kn
2.0 Kn, maximum
30 pA
1.0 nA
100 pA
5 pF
50 pF

4 Differential
±15V
1.5 Kn
2.0 Kn, maximum
30 pA
1.0 nA
100 pA
5 pF
12 pF

+ 0.8V, maximum
+4.0V, minimum
+6.0V, minimum
5 pA, maximum
3 Bits
Logic "0"

+0.8V, maximum
+4.0V, minimum
+ 6.0V, minimum
5 pA, maximum
4 Bits
Logic "0"

-

0.01%
0.005%

0.01%
0.005%

2 ! 100 megohms in parallel with 2 pF.

5-8

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

MX SERIES
CONNECTION & APPLICATION

CHANNEL ADDRESSING

PIN CONNECTIONS
MX·80B

CAl

INHIB

"

MX-1606

I.

CA2

15

CA.

I.

.VS
NC·

27

13

GND
.VS

161N

25

SIN

15tN

2.

3IN

11

61N

14tN

23

4IN

10

7IN

13tN
12 IN

22
21

3IN

11tN

20

BIN

OUT

NC

10 IN

I.

MXD-409

CAl

10

15

-VS

14

'VS

13

18 IN

2A IN

•

12

4A IN

10

A OUT

11

12

VR
CA.

14

19

13

28 IN

48 IN

BOUT

NOTES:
NOTES:
CA CHANNEL ADDRESS

~B ~~5~~~~~~gtlAGE

.vs

1 •

NC

X X X

0

1

0

0

0

1

1

21N

0

0

0

1

1

2

0

0

1

1

2

tiN

0

0

1

0

1

3

0

1.0

1

3

0

0

1

1

1

4

0

1

1

1

4

0

1 0

0

1

5

1

0

0

1

5

0

1 0

1

1

6

1 0

1

1

6

0

1

1

0

1

7

1

1 0

1

7

0

1

1

1

1

8

1

1

1

8

CAl
CA2

15

CA<

our

2.

A

27

-VS

1

0 0

0

1

9

0

0

1

1

10

1

0

1

0

1

11

1

0

1

1

1

12

1

1 0

0

1

13

tA IN

1

1 0

1

1

14

0

INHIBIT

1

1

1

0

1

15

1 0

1

3

1

1

1

1

1

16

1

1

4

6A IN

23

SA IN

58 IN

22

4A IN

48 IN

21

3A IN

20

2A IN

13
14

17

15

1

1

24

11

NONE

mHIBtT

78 IN

12

ON
INHIB. CHANNEL

NONE

68 IN

VR
NC

1

1

7A IN

GND

2

0

'"

18 IN

4

0

17

I.I.
I.

ON
INHIB. CHANNEL

0 0

25

10

1

X X X X

88 IN

28 IN

2

0

SA IN

38 IN

4

4IN

MXD-a07

BOUT

8

.'N
51N

GND

38 IN

3A IN

I.
I.

10

9IN
GND

.'N
7IN

CA2

INHtB

lAIN-

2.

MX-808, MXD-807

-VS

12

-VS
tiN
21N

MX-1606

28 -OUT

"

MXD·409
INHIB.

ON
CHANNEL

X X

0

NONE

0

0

1

1

1

1

2

2

1

CAl
CA2

1

CA<

TECHNICAL NOTES
1. The transfer accuracy of these multiplexers depends on both
the source resistance and the load resistance. With zero
source resistance, and assuming 2K ohms maximum channel ON resistance, the load impedance should be at least 20
megohms to achieve 0.01% accuracy. In practice, it is
recommended that a load impedance of at least 100 megohms be used to minimize errors. This can be done by using
a good high-gain, high-CMR operational amplifier as a buffer
(such as DATEL's AM-462). Source resistance should be
kept as low as possible so that accuracy is not affected; less
than 1K ohms is recommended. Higher source resistance, in
addition to affecting accuracy, will degrade the settling time
of the multiplexer.
2. For differential operation, two buffer amplifiers or a good
quality instrumentation amplifier (such as DATEL's AM-201)
should be used. To maintain high CMR, source impedance
unbalance should be kept to a minimum, the highest possible load impedance should be used, and an amplifier with
high CMR should be chosen.
3. The maximum analog input overvoltage for these models is
± [Vs + 20V]. Maximum logic input overvoltage is ± [Vs
+4V].
4. Channel expansion is accomplished using the inhibit input of
the multiplexer. A logic "0" on this input disables the multiplexer. The expansion technique shown in the diagram applies to all of the multiplexer models.
5. The reference terminal (VR) sets the noise immunity level of
the input logic for models MX-1606 and MXD-807. In most
cases this terminal is left open (TIL inputs). For higher level
inputs ( + 6V minimum), this terminal should be connected to
+ 10V dc. When addressing from DTUTIL logic, use 1K
ohm pull-up resistors to the + 5V dc supply.

EXPANSION TO 64 CHANNELS

~

ANALO GIN

OUT

MX-1606

"

~
~

~CA.

I.

INHIB

17 -

OUT

CHANNEL
ADDRESS

CAl
MX.1606

#2

32

CA2
CA.
CAB
INHIB

CAl
CA2
CA<
CAB

~
DECODER

33

-

OUT

MX-1606
#3

48

--v CAt6

--0

CA32

~

~-

~
CAB
INHIB

-

4. -

OUT

MX-1606

#4

.4 -

ANALOG
OUT

~

~~
CA.
INHIB

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

5-9

MX SERIES
PERFORMANCE GRAPHS
BREAK-BEFORE-MAKE DELAY
(t OPEN)

CROSSTALK VS. FREQUENCY
OF INPUT SIGNAL

SETTLING TIME VS. SOURCE
RESISTANCE (20V STEP)
1000

I

"
C

I

ADDRESS

VA INPUT
2VIDIV

r--

DRIVE

*~
~
t

0

V

--I

If- t

I!Ii

I

~

TO 0.01%

;::

0.01

~

\,

10

"

~~

Z

~

i!'.

,I

I

r

~

\ 1

OUIUr
5V/OIV

1
:V:

~

100

0.1

~

'""'"

0.001

~

~

TO 0.01%

~

0.1

0.0001

O;EN

0.1

0.01'

100 nsec/DIY.

INPUT SIGNAL FREQUENCY (Hz)

10

100

SOURCE RESISTANCE (RS) In KILOHMS

LEAKAGE CURRENT VS. TEMP.
l00nA

./
OFF OUTPUT
LEAKAGE CURRENT
'0 (OFF)
10 nA

O°CsTA s70"C

1•5

./

V

NORMALIZED ON RESISTANCE
VS. SUPPLY VOLTAGE

fv/"
./

ON LEAKAGE

CURRENT

./

VIN

//

[D(ON)

4

YV

......

3

""" ......

2

1

/

/' V

loopA

.......

........

0

./ "

r---

9

OFF INPUT
LEAKAGE CURRENT
'SCOFF)

O.8

±s

i6

±7

±a

±9

±10

±tt

±12

±13

±14

SUPPLY VOLTAGE

lJ"

10pA

500

25°

750

1000

TEMPERATURE (OC)

SUPPLY CURRENT VS.
SAMPLING FREQUENCY

I
I

VSUPPLY =

I

0

lK

10K

MODEL NO.

""'"

}J

± tOV

I

I

ORDERING INFORMATION

I

VSUPPLY"" ±tS

t?I'
lOOK

1M

10M

CHANNELS

MX-808

8 S.E.

MX-1606

16 S.E.

MXD-409

4 Diff.

MXD·807

8 Diff.

OPERATING
TEMP. RANGE

ooe to + 70°C
ooe to + 70°C
ooe to + 70°C
ooe to + 70°C

SAMPUNG FREQUENCY (Hz)

5-10

_

= +5V

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

±tS

MX.1616, MX·818
High·Speed CMOS
Analog Multiplexers

FEATURES
•
•
•
•
•

800 Nanoseconds settling time
Programmable input mode
Break-before-make switching
Dielectrically isolated CMOS
TTL/CMOS-compatible

LS

GENERAL DESCRIPTION
The MX-1616 and MX-818 are high-speed,
high performance analog multiplexers
manufactured with a dielectrically isolated
CMOS process. Both devices achieve
transfer accuracies of 0.01 % at channel
sampling rates of up to 1.25 MHz over
± 10V signal ranges. These multiplexers
are ideal for high-speed, multi-channel,
data acquisition systems where the
multiplexer operates into a high impedance load such as a sample-hold, buffer
amplifier or instrumentation amplifier.
Channel ON resistance is 7500 maximum
at +25°C and only 1KO maximum over
the full operating temperature range. The
channel OFF Output Leakage current is
typically only 35 pA for the MX-1616 and
100 pA for the MX-818.

SA IN

CA3 DECODE

a

CA3 Q

H

H

L

L

L

H

v-

l

L

A unique feature of these circuits is the
ability of the user to program their inputs
for either single-ended or differential operation. The MX-1616 is user programmable
either as a single ended 16-channel or as a
differential 8-channel multiplexer while the
MX-818 is user programmable either as a
single-ended 8-channel or as a differential
4-channel multiplexer.

MECHANICAL DIMENSIONS
INCHES (MM)

Digital inputs are user selectable for either
TTL or CMOS compatibility. The proper
channel is addressed by means of a 3- or
4-bit binary word. An inhibit function enables or disables the entire device, permitting expansion of the number of channels
by using several devices together. Another
important feature of these devices is the
use of break-before-make switching to insure that no two channels are ever
momentarily shorted together.
These multiplexers are packaged in
18-pin and 28-pin ceramic DIP's. Commercial versions operate over the O°C to
+70°C operating temperature range.

•

MULTIPLEXER
SWITCHES

INPUT BUFFER AND DECODERS

2.

,.

15

I

DATEl-

0.520
(13,2)

MX·1616

~

10

~[::~~::H-

14
0.185

MAX

I

I

1 470
(37,3)

~ 0.900

r

~

~m;TIrnmmmr-~AX'~:
~4'~i
'

II U
if
u

i ~~
MAX.
U

- - , - ----ILO.019
(a,S)

I

-!l

0.055
(1,4)

-1

~
0.040 r

~(1.0)
0.100
(2,5)

0.160 ±± 0.254)
0.010.
(4.06

lJ~
-4
.

0.018
(0.457

MAX.

±

---.J

0.015
(4.70)
(22.9 ± O . 3 8 1 ) - l

l

± 0.003) 0.060 TYP.
± 0.076) (1,52)

0.100 TYP.

0.040
± 0.020
(1.02
± 0.508)

(2,54)

CAUTION: These multiplexers are CMOS
devices and should be handled with antistatic precautions until installed in a circuit
with anti-static return paths.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

5-11

~ ~[L

MX-1616, MX-818
ABSOLUTE MAXIMUM RATINGS

MX-1616

Voltage Between Supply
Pins ................... 33V
Analog Input Voltage ••...•• ±(Vs +2V)
Digital Input Voltage:
TTL' ..•••..••....•... CA3=(-Vs -2VI
-6V .............
Channel ON Res. over
Temp., maximum> •••..••
Channel OFF Input
Leakage •••••••........
Channel OFF Output
Leakage ...............
Channel ON Leakage .......
Channel OFF Input
Capacitance ..•••....•.•
Channel OFF Output
Capacitance . . . . . • • . . . •.

7501l
1 KIl

MX-818
8 Single-Ended
4 Differential

·
·

10 pA

50 pA

35 pA
40 pA

100 pA
100 pA

2.5 pF

1.9 pF

18 pF

10 pF

DIGITAL INPUTS
Logic "0" Threshold,
maximum: TTL ..........
CMOS ........
Logic "1" Threshold,
minimum: TTL •..•......
CMOS ....•...
Input Leakage Current,
maximum: High . . . . . . . ..
Low .........
Channel Address Coding .•..
Channel Inhibit,
All Channels OFF ..•.•...

+0.8V
+0.3V
+2.4V
0.7 (Logic sup.)
1 pA

25pA
4 Bits
Logic "0"

··
··
·
·

20 pA
3 Bits

PERFORMANCE
Transfer Error, maximum •..
Settling Time,
10V step to 0.1% ...•••.
10V step to 0_01% ......
Access Time, maximum ••..
Enable Delay
"ON", maximum .•.•..••
Enable Delay
"OFF", maximum •••...•
Break Before Make Delay ..•

0.01%
250 nsec.
800 nsec.
150 nsec."
150 nsec.
125 nsec.
20 nsec.

·
··
·
··

125 nsec?

POWER REQUIREMENTS
Rated Power
Supply Voltage .....•.... ± 15V
Quiescent Current
maximum
±30 mA
Power Dissipation,
maximum ....•..•.....• 900 mW

.............

5-12

·
±18 mA
540 mW

TECHNICAL NOTES
1. The transfer accuracy of the MX-1616 and MX-818 depends
upon both the source and the load resistance. With zero
source resistance and assuming 1 KO maximum channel on
resistance the load impedance must be at least 10MO to
achieve 0.01 % accuracy. This can be done by using a good
high gain, high CMR operational amplifier as a buffer (such as
DATEL's AM-410). Source resistance should be kept as low
as possible so that accuracy or settling time are not degraded. Less than 5000 is recommended.
2. For differential operation, two buffer amplifiers or a good instrumentation amplifier (such as DATEL's AM-551) should be
used. To maintain high CMR, source impedance unbalance
should be kept to a minimum, the highest possible load impedance should be used and an amplifier with high CMR
should be chosen .
3. These devices have the added feature of being programmable for single-ended or differential operation. The
MX-1616 is user programmed for single-ended 16-channel
operation by connecting A out (Pin 28) to B out (Pin 2) and using CA3 (Pin 14) as a digital address input. To program the
MX-1616 for differential 8-channel operation, CA3 (Pin 14) is
simply connected to - Vs (Pin 27). The MX-818 may be programmed as a single-ended 8-channel multiplexer by connecting Aout (Pin 18) to Bout (Pin 2) and using CA2 (Pin 9) as
a digital input address, or as a differential 4-channel
multiplexer by connecting CA2 (Pin 9) to - Vs (Pin 17). Refer
to the truth tables for channel addressing information.
4. Both devices are selectable for either TTL or CMOS compatibility. For TTL compatibility, the Logic Select Pin (MX-1616
Pin 13, MX-818 Pin 8) is left open or grounded. For CMOS
compatibility, the Logic Select Pin should be connected to
the system Logic Supply.
5. Channel expansion is accomplished by the use of the inhibit
input of the multiplexers. To expand the number of channels,
use multiple multiplexers with the inhibit inputs connected to
a decoder.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

MX-1616, MX-818
CONNECTION & APPLICATION
MX-1616 - USED AS 16 CHANNEL MULTIPLEXER
USE CAl AS DIGITAL
ADDRESS INPUT

1

0 INHIB.

1

2

MX-818 - USED AS 8 CHANNEL MULTIPLEXER

ON CHANNEL TO
OUPUT
A

USE CA2 AS DIGITAL
ADDRESS INPUT

OUTPUT
B

X

X

X

X

0

NONE

NONE

0

0

0

0

1

1A

--

0

0

0

1

1

2A

--

0

0

1

0

1

3A

--

0

0

1

1

1

4A

--

0

1

0

0

1

SA

--

0

1

0

1

1

6A

--

0

1

1

0

1

7A

--

0

1

1

1

1

8A

--

1

0

0

0

1

--

1B

1

0

0

1

1

--

2B

1

0

1

0

1

--

3B

1

0

1

1

1

--

4B

1

1

0

0

1

--

5B

1

1

0

1

1

--

6B

1

1

1

0

1

--

7B

1

1

1

1

1

--

8B

2

ON CHANNEL TO

0 INHIB.

OUTPUT
A

OUTPUT
B

X

X

X

0

NONE

NONE

0

0

0

1

1A

--

0

0

1

1

2A

--

0

1

0

1

3A

--

0

1

1

1

4A

1

0

0

1

--

1

1

0

1

1

--

2

B

1

1

0

1

--

3

B

1

1

1

1

--

4

B

-B

MX-818 - USED AS DUAL 4 CHANNEL MULTIPLEXER

CONNECT CA2 TO
-V SUPPLY

1

MX-1616 - USED AS DUAL 8 CHANNEL MULTIPLEXER
CONNECT CAl TO
-V SUPPLY

1

0

ON CHANNEL TO

INHIB.

OUTPUT
A

OUTPUT
B

X

X

0

NONE

NONE

0

0

1

1

1B

0

1

1

2

2B

1

0

1

3

3B

1

1

1

4

4B

•

ON CHANNEL TO
OUTPUT
A

OUTPUT
B

2

1

0 INHIB.

X

X

X

0

NONE

NONE

0

0

0

1

1A

1B

0

0

1

1

2A

2B

0

1

0

1

3A

3B

0

1

1

1

4A

4B

1

0

0

1

SA

5B

1

0

1

1

6A

6B

1

1

0

1

7A

7B

1

1

1

1

8A

8B

EXPANSION TO 64 CHANNELS

~

ANALOG IN

-

OUT

MX-1616

,. -

#1

~

ANALOG
OUT

fcF

~
INHIB
CHANNEL

17

PIN CONNECTIONS

-

MX-818

MX-1818

MX-1616
.2

+VS

2.

A OUT

8 OUT

27

-VS

NC

2.

8.1. IN

4BIN

1.

4AIN

sa IN

25

7A IN

38 IN

15

3.1. IN

+VS

1.

AOUT

BOUT

17

-VS

CA3
INHIB

32

-

OUT

24

SA IN

28 IN

14

2.1. IN

MX-1616

23

5.1. IN

.18 IN

13

1A IN

#3

4A IN

GND

22

12

INHIBIT

21

3A IN

LS

11

CAO

38 IN

20

2A IN

CA2

10

CA1

,.

19

MIN

,.

INHIBIT

17

CAO

28 IN

10

18 IN

11

GND

12

LS

13

CA3

14

15

CA1
CA2

CA3

~

-v CA4
- - - 0 CAS

CAO

78 IN

58 IN

CAO
CA1
CA2

DECODER

68 IN

48 IN

ADDRESS

OUT
CAO
CA1
CA2

48
49

-

~

fcF
IffiINHIB

OUT
CAO

NOTES:
CA CHANNEL ADDRESS
Vs SUPPLY VOLTAGE
LS lOGIC SELECT
NC NO CONNECTION

MX-1616
.4

64

-

~
CA2

Fcfr-INHIB

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

5-13

MX-1616, MX-818
APPLICATION
r

---..,

I

,...__

I

LOAD

AO A2 A4 AS

CLEAR

Msa
MSB

THREE·

OM-

STATE

8095

OUTPUT

DATA
CHANNEL

INPUTS

A[)C.817A
BIT 6

MX-1616

alTs

MUX ENABLE
ENABLE
alT 7

BtT7
THREE·

OM-

STATE

8095

OUTPUT

DATA
LSa
LSa

Eoe
AO

Al

A2

A3

LOAD CAO CAl CM CAS

CLEAR

DELAY

STROBE

NOTE: "Fhis application diagram shows a high-speed data acquisition system with 8 differential inputs and 12-bit resolution that utilizes the
MX-1616. If the control logic is timed so that the sample-hold-AID section is converting one analog value while the mux-amplifier section is
allowed to settle to the next input value, throughput rates greater than 156 KHz can be achieved. The MX-1616 is used with Datel's
AM-543, a high speed digitally programmable gain amplifier, the ADC-817A, a 12-bit hybrid AID with a 2 microsecond conversion rate,
and the SHM-6, a 0.01%, 1 microsecond hybrid sample-hold.

, STROBE

NOTE: The switches in a CMOS multiplexer will conduct equally
well in either direction, making it feasible to use them as single
input-selected multiple output switches. The circuit shown is
capable of sample rates of 78 KHz for inputs of ± 10V. The
MX-1616 is used with Datel's DAC-HK12, a 12 bit hybrid D/A
with input registers and the SHM-LM-2, a low cost monolithic
sample-hold.

DELAY

INHIBIT

OAeHK12

INPUT

MX-161S

I

CHANNELS

OUTPUT

I .CHANNELS
I
I
I

I

+
ORDERING INFORMATION
MODEL NO.
MX-818C
MX-1616C
CLEAR LOAD

5-14

CAO CAl CA2 CA3

AO

Al

A2

CHANNELS
8 S.E. or 4 Diff.

OPERATING
TEMP. RANGE
o to +70°C

16 S.E. or 8 Diff.

A3

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ACTIVE FILTERS

MODEL
FLJ-DC

2

FLJ-D1

2

FLJ-D2

2

FW-DSLA1

5

•
•
•

6

FLJ-D6LA2

6

•
•
•
•
•

FLJ-DSLA2
FLJ-D6I,.A1

•

•
•
•
•

•
•
•

•
•
•

•
•
•

•
•

FLJ-R3BA1
FLJ-R3BA2

3

FLJ-RSLA1

8

FLJ-RSLA2

8

FLJ-R8LBl

8

FLJ-RSLB2

8

FLJ-UR1BA1

1

•

·1

FLJ-UR1BA2

1

•

•

FLJ-UR2BA1

2,

FLJ-UR2BA2

2

FLJ-UR2EAl

2

FLJ-UR2EA2

2

•
•
•
•

FLJ-UR2LH1

2!.

FLJ-UR2LH2

I

FLJ-UR4HA1

•
•
•
•

2

•

4

•
•

FLJ-UR4HA2

I

4

FLJ-UR4HB1

i

4

FLJ-UR4HB2

i

4

-------+1 ·---L4 ,i .FLJ-UR4~Al
I

4

•

FLJ-UR4LB1

4

FLJ-UR4LB2

4

FLJ-VB

2

FLJ-VH

4

•
•
•
•

FLJ-VL

4

•

FLT-U2

2

•

FLT-C1

7

FLJ-UR4LA2

•

•

•

1

•
•

•
•
•
•
•

•
•
•
•
•
•

•
•
•
•

•
•
•

0.1%

0.1%

1-1.6 kHz

6-11

0.1%

100-160 kHz

6-11

•

3%

10 Hz-2 kHz

6-23

•
•
•

3%

100 Hz-20 kHz

6-23

3%

10 Hz-2 kHz

6-23

3%

100 Hz-20 kHz

6-23

2

10 Hz-2 kHz

6-25

2

100 Hz-20 kHz

6-25

•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•

•

•

2

10 HZ-2 kHz

6-25

2

100 Hz-20 kHz

6-25

2

10 Hz-2 kHz

6-25

2

100 Hz-20 kHz

6-25

3

40 Hz- 1.6 kHz

6-27

3

400 HZ-10kHz

6-27

3

40 HZ-1.6 kHz

6-27

3

400 Hz-10kHz

6-27

3

40 HZ-1.6 kHz

6-27

3

400 Hz-10kHz

6-27

3

40 HZ-1.6 kHz

6-27

3

400 Hz-20 kHz

6-27

3

40 HZ-1.6 kHz

6-27

3

400 Hz-5 kHz

6-27

3

40 HZ-1.6 kHz

6-27

•

3

400 Hz-20 kHz

6-27

•
•
•
•

3

40 Hz-1.6 kHz

6-27

3

400 Hz-20 kHz

6-27

3

40 HZ-1.6 kHz

6-27

3

400 Hz-20 kHz

6-27

±3

200 Hz-20 kHz

6-37

±3

20 Hz-20 kHz

6-37

±3

100 Hz-100 kHz

6-37

±5

p.001HZ-200 kHz

6-41

•
•

6-11

•

,

•
•
•

•
•
•
•

Note 1

•

•

± O.S

78 Hz-20 kHz

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

6-1

6-2

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

FLJ-AC01
Oscillator Adaptor
for FW-D Series

PRODUCT DATA SHEET

FEATURES
eoutput 2.5Vrrns ±O.5% accuracy
e500mV-20Vp-p wide amplitude range
e Single inline Hybrid package

GENERAL DESCRIPTION
FLJ-AC01 is an accessoryof FLJ-D1, 02
and DC to build a digital programmable
oscillator which is controlled with 3
digits of BCD logic input. The setting
method, set frequency accuracy and TC
depend on FLJ-D1, 02 and DC which
are to be used with this FLJ-AC01, but
the specifications related to output voltage such as output voltage accu racy,
stability and amplitude TC are determined with the FLJ-AC01. The output
voltage is trimmed internally to provide
2.5Vrms ±0.5% output. With connections of the pins so assigned, 20Vp-p
(~50kHz) output is available. Other intermediate output amplitude is also available by adding external resistors. Oscillation frequency range is 100Hz to 100
kHz. This range is widened toward lower
and higher frequency ranges once a few
external components are used.

* 1. 0veJ Vohage ProtecIion

GND +15V -15V

."
rI
"

BLOCK DIAGRAM (Fig. 1)

MECHANICAL DIMENSIONS
INCHES (mm)
PIN SECTION
O.02XO.OI (O.5xO.25)

PIN CONNECTIONS

,

PIN
FUNCTION
1 RQ
2 LOOP OUTPUT
3 GND
4 +15V Supply
15V Supply
5
6 NC
7 NC
8 NC
9 NC
10 Cex!

PIN
11
12
13
14
15
16
17
18
19
20

FUNCTION
OUTPUT PROTECTION
COMPENSATION 1
SUB (_90°) OUTPUT
COMPENSATION 3
MAIN OUTPUT
-Vret IN
COMPENSATION 2
OUTPUT RANGE 1
OUTPUT RANGE 2
-Vret OUT

DO NOT CONNECT NC PINS TO ANY.
PIN 14 SHOULD BE LEFT OPEN NORMALLY,

DATEL, inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

6-3

FU-AC01
TECHNICAL NOTES

SPECIFICATIONS
Typical at 25°C, with ±15V power supplies unless otherwise specified.

±18V
±Vs
±Vs

1. Oscillation
depending
Filter to be
FLJ-D1
FLJ-D2
FLJ-DC

2.5Vrms normal '1
500mVrms to 2.5Vrms
500mVrms to 20Vp-p
±0.5% max.
100 ppm/DC
50 max .
0.01 %@10kHz
-90° phase of Main Output

2.

ABSOLUTE RATINGS
Power Supply Voltage (±Vs) ......
Signal Input (Pin 13)
Detector Input (Pin 15) ..........
0

•••••••••••

OUTPUT
Output Voltage •••••.••••••••• o.
Voltage Range ~1 OOkHz
~ 50kHz .........
Voltage Set Accuracy ............
Amplitude TC
Output Resistance
Distortion .....................
Sub Output
••••

••••••••••

•••••

•••••••••

0

00.

0

0

••••

•••••••

••••••••

0

•••••••

FREQUENCY

_.-

Frequency Range ...............
Frequency Set Error .....•.......
Setting Method .................

100Hz to 100kHz '2
±0.1%
BCD 3 digits

POWER SUPPLIES & ENVIRONMENT
±15V ±10%
Supply Voltage
Supply Current ................. +14mA,-24mA
Operating Temperature Range .•.. -20°C to 70°C
Storage Temperature Range ...... -30°C to 80°C
Operating/Storage Humidity ...... 10% to 95%/80% RH
•••••••

'1.
'2.

0

•••••••••

3.

20Vp-p with pin connections, other voltage output ranges are available
with the use of external components.
Expandable to wider range with the use of external components.

4.

5.

frequency range varies
on 'the Digital Tuneable
used with FLJ-AC01.
1Hz - 1.599kHz
100Hz - 159.9kHz
Determined by external
capacitors
Any model can be used being connected as shown in Figure 3 to get
the performance that meets the values shown on the specifications at
the frequency range of 100Hz to
100kHz for 2.5Vrms output amplitude and 100Hz to 50kHz for 20Vp-p
output.
FLJ-DC needs two external capacitors. The relationship between capacitance and oscillation frequency
fc is:
N_ fc: Hz, Cext: /L F
fc == __
20'Cext N: Digital Number
For example, once Cext of 0.0051LF
and N of 1000 are given, fc shall be
10kHz. Therefore, with N of 1 to
1599, fc can be set at any frequency
of 10Hz to 15.99kHz range with BCD
logic inputs.
Expansion to higher frequency
range:
The maximum frequency is 50kHz
for 20Vp-p output even if FLJ-D2 is
used. Connect Pin 11 of both FLJDC and FLJ-AC01 together to expand the oscillation frequency range
to higher levels. Up to 100kHz of
frequency range is obtained for 20
Vp-p amplitude even though distortion ratio is slightly derated as the
protection circuit in FLJ-AC01
works. Up to 159.9kHz of oscillation
shall be available for 2.5Vrms output
with the same connection.
Expansion to lowerfrequency range:
Distortion at lower frequency range
shall be improved with the addition
of a few external components. See
Figs. 7, 8 and 9.
a.
With FLJ-D1 (1 Hz to 1.599kHz):
Connect as shown in Fig. 4. As
little as 0.01% distortion can be
attained at 4Hz oscillation. See
Fig. 7.
b. With FLJ-DC, Cext==5000pF:
Figure 5 shows the circuit with
which 10Hz to 15.99Hz oscillation range can be achieved. Distortion at 10Hz shall be improved to 0.005%. See Fig. 8.
Adjustment of output voltage:
Normal 2.5Vrms output voltage is
obtained with SW1 of Fig. 3 open and
20Vp-p is obtained with SW1 closed.
For other output voltage, follow Fig.
6 and the following equation.

R==~
(kO)
Vo(rms)
The range of Vo is 0.5Vrms to 20
Vp-p.
6-4

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

FU-AC01
FW-D1 FOR LOWER FREQUENCY (Fig. 4)

TYPICAL CONNECTION (Fig. 3)

r~1
12

17

10

FW-DC FOR LOWER FREQUENCY (Fig. 5)

10K

+15V>--~-+--M

Note: FW-D1 or ft..H)C with 5OClOpf d C8kT: fer lower than 10Hz oscillation,
use one r:I the8e circuits.

GND>---+-~~+---~

-15V>---+-~~+--------l

I~I~

_____ ---- - _1-

,

I

OUTPUT VOLTAGE ADJUSTMENT (Fig. 6)

fc Set Logic Input

R

Note 1. Open SW1 and SW2 for 2.5 V!mS output. Close SW1 and SW2 for 2OVp-p output
2. Two Cext we required fa FW-OC.

LOGIC INPUT FOR FW-O

~

~
16

Logic Input
Oscillation F (Hz)
MSD
LSD
Dec. FLJ D1 FLJ-D2 FLJ-OC

ID


IDk
2k
ID>
0100 
12k
lID>
1IDk
lll0 
1&X>
lOOk
15k
1111 1001 1001
1599
1599 1!i}.9k 15.99k

17

•..

20

':..

Note1. Only MSD is hexadecimal.

2. Logic 1: +5V, 0: GNO or OPEN
3. Cext=5000pF used with FW-OC

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

6-5

FW-AC01
DISTORTION AT LOWER FREQUENCY (Fig.10)

DISTORTION vs. FREQUENCY (Fig. 7)
With FW·DI, 2.5Vrms output, technical note 48.
eDNo external component ®Cc=l,uF only ®with all componets of Fig.4

,

00

(%)

D.

D.D

,

WUhFW·DI
eDNa external component (VWith all components of Fig.4

"

I\(j)

,

D

®

D

\
(j)

D

0.00

,

-10

~

(j)

10

'DO

"-

'K

2

'OK

DISTORTION vs. FREQUENCY (Fig. 8)
With FW-OC, Cext=5000pF, technical note 4b.
eD20Vp-p. no external component ®2.5Vrms. no external components
®2.5Vnns. Cc=l,uF only @2.5Vrms. with all components of Fig. 5

,Ot"

,

fe ACCURACY AT LOWER FREQUENCY (Fig. 11)
With FW-DI
eDWith all components of Fig.4

®No external component

(%)

II

@

(%)

D. ,

0.01

'"

Jf

,

D

r-...

/'

,
•
,

......

/
/

/
/(j)

•
10

'DO

'K

10K

10

lGOKH:!:

DISTORTION vs. FREQUENCY (Fig. 9)

20Hz;

OUTPUT VOLTAGE VARIANCE vs. FREQUENCY (Fig.12)

With FW-OC, Cext=500pF, 2.5Vrms, no external component
eDsw, of Fig.3 closed ®sw, of Fig.3 open

With FW'[)2, 10kHz base

,

eD20Vp-p (V1Vrms ®2.5Vrms

(%)

D.

=

(j)

I-

,
2

.
0.001

+

,

(%)

D.

--

,V

D.D

(j)
(j)

D. 2

,
-0.2

D.DO

CD
~~

,®,

-

,
'DO

6-6

CD

•

D.

'K

10K

1001« ...*)

IOD

'K

10K

20K

100KHz

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

LOGIC CONTROLLED
RESISTOR NETWORK
FLJ-ACR1,2
FEATURES
• Cutoff frequency of resistor tuneable
fiHers can be set with BCD logic.
• Single Inline Hybrid.
• Small Size, Low Cost

GENERAL DESCRIPTION

FLJ-ACR series are logiC controlled resistor networks, They are designed to be
used with resistor tuneable filters such as
FLJ-UR series,
Four separate resistor networks are included in one package, One network
consists of four resistors such as R, R/2,
R/4 and RIB. The value of R in FLJ-ACR1
is 1,59MO while that of FLJ-ACR2 is
159kO.
A combination of an FLJ-ACR and an
FLJ-UR makes it possible to make a filter
whose cutoff frequency or center frequency is set with BCD logic. It is also
possible to use this resistor network in the
negative feedback loop of an amplifier
circuit and control the gain with BCD
logic.

Network

Logic Input

Logic Input

#2
GND +15V -15V

R =1.59M Q (FW-ACR1)
R= 159kQ(FW-ACR2)

BLOCK DIAGRAM (Fig. 1)

MECHANICAL DIMENSIONS (Fig. 2)
INCHES (mm)

PIN SECTION
0.02 xO.OI (D.S x 0.25)

0.16(4)

2.03(51.5)

~

.;

I

0.05(1.2)

FLJ-UR Series List
Model No.

FLJ-UR4LAl
FLJ-UR4LBl
FLJ-UR4HAl
FLJ-UR4HBl
FLJ-UR2LHl
FLJ-UR1BAl
FLJ-UR2BAl
FLJ-UR2EAl
FLJ-UR4LA2
FLJ-UR4LB2
FLJ-UR4HA2
FLJ-UR4HB2
FLJ-UR2LH2
FLJ-UR1BA2
FLJ-UR2BA2
FLJ-UR2EA2
LP: Lowpass
HP: Highpass
B P: Bandpass

tc Range

40Hz 1.6KHz

400Hz 20KHz

No. 01 Pole

4
4
4
4
2
tE_air
2 pair
2_Eair
4
4
4
4
2
l_pair
2~air

2 pair

Type
LP. Butt.
LP. Cheb.
HP. Butt.
HP. Cheb.
LP/HR.Butt.
BP, Butt.
BP. Butt.
BE. Butt.
LP. Butt.
LP. Cheb.
HP. Butt.
HP. Cheb.
LP/HP.Butt.
BP, Butt.
BP, Butt.
BE. Butt.

BE: 8andelimination

Butt.: Butterworth
Cheb.: Chebychev

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

6-7

FW-ACR1,2
SPECIFICATIONS
Typical at 25°C, ±15VDC power supplies unless otherwise specified.
ABSOLUTE RATINGS
Power Supply Voltage (±Vs) ..•.•.•.......•......•................. ±18V
Input Signal Voltage ...•..•.••.................................... ±Vs
Control Logic Voltage .............................. +5.5Vmax., ~0.5V min.
FREQUENCY SET MODE
BCD 1 Digit. . . .. . . . ... . . . . ... . . . .• . . . •. . . . . . . . . . . . . . . . . . .... .. 0 to 15
BCD 1 Digit +1 •..•.. ,......................................... 1 to lS
FREQUENCY SET RANGE (WITH FLJ-UR) Unit: Hz

a. FLJ-ACR1 OR ACR2 SINGLE USE
FLJ-UR Suffix
Frequency Set Mode
From
FLJ-ACRl
To
Resolution
From
FLJ-ACR2
To
Resolution

b. FLJ-ACR1 AND ACR2
FLJ-UR Suffix
Frequency I -ACR2
Set Mode I -ACRl
From
r=----To
Resolution

-1 (Low Range)
BCD+l
BCD
O·
10
150
160
10
10
O·
100
1.5k
1.6k
100
100

PARALLEL USE
-1 (Low Range)
BCD
BCD
BCD+l
BCD
BCD+l
BCD
O·
10
100
1.59k
1.60k
1.69k
10
10
10

-2 (High Range)
BCD
BCD+l
O·
100
1.5k
1.6k
100
100
O·
lk
15k
16k
lk
lk

-2 (High Range)
BCD
BCD
BCD+l
BCD
BCD+l
BCD
O·
100
lk
15.9k
16.0k
16.9k
100
100
100

Output saturates at 11VDC with zero logic code input.

PERFORMANCE
Frequency Set Error ........................................ ±1% or less
CONTROL CHARACTERISTICS Logic Code ........... BCD 1 digit (1, 2, 4, 8)
Logic and Level ..........................................•.... OV: ON
+5V or Open: OFF
POWER SUPPLIES AND ENVIRONMENT
Power Supplyl(Operating Range) ...................... ±15V (±5V to ±18V)
Current .............................................. +S.2mA, -1.2mA
Operating Temperature Range ••..•............................ 0 to 70°C
Storage Temperature Range ............................... -30°C to 80°C
Operating Humidity Range ............................... 10% to 95% RH
Storage Temperature Range .............................. 10% to 80% RH

TECHNICAL NOTES

1. FLJ-ACR1 and FLJ-ACR2 contain
four separate resistor networks which
are controlled by common logic inputs. There are two types of FLJ-UR's
(reSistor tuneable filters) which areto
be connected with FLJ-ACR's to build
BCD Logic Programmable Filters.
One type such as FLJ-UR2LH or FLJUR1 BA requires two external resistors
while all other FLJ-UR's require four
external resistors to set a cutoff frequency. Therefore, one FLJ-ACR can
control two FLJ-UR2LH's or FLJUR1 BA's. See Fig. 3.
2. Typical examples of connection are
shown in Figs. 4a, 4b, 5a and 5b. Such
connections shown in Figs. 4a and 4b
generate a problem at the time when
an input logic code "0000" is given
because no resistor is selected as an
external resistor of FLJ-UR's. The filter output is saturated at approximately 11VDC with zero logic code input.
The merit of these modes of connec"
tion is that the digital code corresponds to the value of fc directly.
Figs. 5a and 5b illustrate BCD+1
mode of connections. The lowest end
frequency is obtained with the input
code of "0000" and no output saturation takes place even with zero code
logic input. See Table 1.
3. Figs. Sa, Sb and Sc illustrate the connections how to program· fc in two
digits range. See Table 2.
4. FLJ-ACR1, -ACR2 are designed as
accessories of FLJ-UR series resistor
tuneable filters. FLJ-ACR can be used
as external resistors of operational
amplifier circuits to build a programmable gain amplifier.

TYPICAL CONNECTION (Fig. 3)

'"put

-+-+--+

-15V>-_ _

+15V>---r~r:+-i

GND>-........~

'"put
6-8

DATEL, Inc. ·11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

FW-ACR1,2
BCD & BCD MODE CONNECTION (Rg.68)

BCD MODE CONNECTION (Fig.4a)
8>-______________________________- ,
4>-____________________________--,

,-

o
iii

FLJ-ACRl,2

T

15

\ ®CD®®@@@@ 14 1\

@0®0(D®D~(~®@@@~~~@~~

FLJ-ACR2

-15V>---+-+---+
+ 15Vr - - - - H
GNO'>---~

7>-----~+-~~4_+-~----~_+~__,

,T

\ ®CV®®@@@@ 14 I
Input

((1)0(3)(i)(5)® 7)(8) 9)~0)@@@(11l(1~1~1~@~i})

FLJ-U R 1BA, 2LH

FLJ-ACRI
-15'1

~~

+~:~,>-.u..:*~*-4
BCD MODE CONNECTION(Fig.4b)

((!)0(3)(<)®®(7)®(' lii)@®@®(I~(~®@@@~

8>---____________________________- ,

Output

Input

FLJ UR4XXX,2BA,2EA

4~----------------------------~

+~

FLJ-ACRl,2

I

("GD~)-'*
G~~:

BCD & BCD + 1 MODE CONNECTION (Rg.6b)

-15V>----+--+---+
+15V>---~

GNO>-------+
C,-8~=============:I
T

h

I

h

@0(3)C!)([)®17)(!)' g)@@@ @(I4)II:!>@(7)@(I9)G ~)

FLJ·ACRI

-15V

+~~~

**

I I .~~
("'(jj)=-'0""'2)--;C3~)-'*
(14)---'(!-i.l"""'
" ®:-)C±-71-'(j8~D(-'*,---'~!-!>-"
, '@:-@=1Z~@:-)(!-±I')-(Il--lj(!-+I~-I(i'
I-I--I~~@---'@~I'~~))

-15'1r---+-+---+

FLJ-UR4XXX,2BA,2EA

loput

Outpul

+15V>----H

GNOr----i

BCD + 1 & BCD MODE CONNECTION (Fig.6c)

Input

BCD+1 MODE CONNECTION (Fig.5b)

8~=============;!
,-4>T

,T

((1)0(3)(<) '->®(7) 8)(v(tii)@@@(19 is) 16) I~@@G~)

FLJ·ACRI
-ISV

~~

+~~~)>--U..I*
......
*--4
®0(i)@'->®(7)(s)(i)(@@@@@ M~(I @@@)
Input

lop",

FLJ.UR4xXX,2BA,2EA

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

Output

6·9

FU-ACR1,2
FW-ACR1 OR ACR2 SINGLE USE, SET FREQUENCY (Table 1)

FLJ· UR Suffix
Input Logic
Dec.
BCD
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
10
1010
11
1011
12
1100
13
1101
14
1110
15
1111

FLJ-ACRI
-1
Fig.4
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150

Fig. 5
10
20
30
40
50
60
70
80
90
100
110
120
130
140
150
160

Fig.4
100
200
300
400
500
600
700
800
900
lk
1.1 k
1.2k
13k
l.4k
1.5k

-2

FLJ-ACR2
-1
-2
fc(Unit: Hz)
Fig. 5 Fig: 4 Fig. 5 Fig.4 Fig. 5
100
100
lk
200
100
200
lk
2k
2k
200
300
300
3k
300
400
3k
4k
400
500
400
500
4k
5k
5k
600
500
600
6k
700
6k
700
600
7k
7k
800
700
800
8k
800
900
8k
9k
900
900
lk
9k
10 k
lk
lk 1.1k
10k
11k
1.1 k
11k
1.2k 1.1 k 1.2 k
12 k
12k
13 k
1.3k 1.2k 1.3k
13k
14 k
1.4k 1.3k 1.4 k
14 k
15 k
1.5k 1.4k 1.5 k
15k
16 k
1.6k 1.5k 1.6 k

FW-ACR1 & ACR2 PARALLEL USE, SET FREQUENCY (Table 2 )

-1
FLJ·UR Suffix
fc (Unit: Hz)
Input Logic
Fig.6a Fig.6b Fig.6c Fig.6a
BCD
Dec.
10
100
0000 0000
0
100
0000 0001
20
110
1
10
120
200
2
00000010
20
30
140
400
0000 0100
50
4
40
800
90
180
8
0000 1000
80
900
190
0000 1001
90
100
9
lk
200
110
0001 0000
100
10
2k
300
200
210
20
0010 0000
4k
500
01000000
400
410
40
900
8k
810
80
1000 0000
800
9k
1000
1001 0000
900
910
90
10k
1100
1010
100
1010 0000
1000
11k
1200
1100
1110
110
1011 0000
12k
1300
1200
1210
11000000
120
13k
1400
1101 0000
1300
1310
130
14k
1500
1110 0000
1400
1410
140
15k
1600
1510
1111 0000
1500
150
1690 15.9k
1590
1600
1111 1001
159

6·10

-2
Fig.6b
100
200
300
500
900
lk
1.1 k
2.1k
4.1 k
8.1 k
9.1 k
10.1 k
11.1k
12.1 k
13.1 k
14.1 k
15.1 k
16.0k

Fig.6c
lk
1.1 k
1.2k
1.4 k
1.8k
1.9k
2.0k
3.0k
5.0k
9.0k
1O.0k
11.0 k
12.0 k
13.0 k
14.0k
15.0 k
16.0 k
16.9k

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000iTLX 174388/FAX (508) 339-6356

FLJ.D1,D2,DC
DIGITAL PROGRAMMABLE
FILTER
FEATURES
• Cutoff frequency is set by logic inputs.
• Lowpass, Highpass and Bandpass
output functions are available simultaneously.
• Gain and
are set by external components.
• High accuracy, high stability

a

GENERAL DESCRIPTION
FLJ-D1, -02 and -DC are digital programmable filters which can set the cutoff
frequency and center frequency with 3
digit BCD inputs.
Two-pole lowpass, bandpass and highpass output functions are available simultaneously from three different outputs
and notch function is available by combining these outputs to the uncommitted
op amp.
To realize higher order filters, several
filters can be cascaded. And to obtain
higher performance of higher order filters,
both Gain and Q are designed to be set
with external components.

*C'NT FLJ-Dl 50,OOOpF
FLJ-D2
500pF
FLJ-DC None. Need Cext.

BLOCK DIAGRAM (Fig.1)

MECHANICAL DIMENSIONS (Fig. 2)
INCHES{mm)

l-mnnmnII~:

PIN SECTION
0.02xO.01 (0.5xO.25)

------------------.-1
r2. 12 (53.9)----1

0.34~1

I~
I

~.J~IIIIIIIIIIII=l11111 0.2(5.0)
0.1 (2.54)

2.14(54.4)

•

t

l . 20 (30.5H!
1.33(33.7H

PIN CONNECTIONS (Table 1)
FUNCTION
INPUT (BPI
ANALOG GND
INPUT (HP, LPI
ANALOG GND
OUTPUT HP
ANALOG GND
AMP (+1 INPUT
AMP. (-I INPUT
AMP. OUTPUT
ANALOG GND
Cext 1
NC
OUTPUT (BPI
ZERO ADJ. HP, LP)
NEG. FEEDBACK IN
ANALOG GND
Cext 2.
NC
OUTPUT (LPI
ZERO ADJ. (BPI

PIN
1
40
2
39
3
38
4
37
5
36
6
35
7
34
8
33
9
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21

FUNCTION
+VS (+15VI
5V ZENER OUTPUT
Vc(+5V)
DIGITAL GND
ANALOG GND
NC
,Vs(-15VI
NC
LOGIC 800
LOGIC 400
LOGIC 200
LOGIC 100
LOGIC 80
LOGIC 40
LOGIC 20
LOGIC 10
LOGIC 8
LOGIC 4
LOGIC 2
LOGIC 1

DO NOT CONNECT He PINS TO OTHERS.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

6-11

FW-D1, D2, DC
SPECIFICATIONS (Table 2)
Typical at 25 'C, ±15V and +5V supplies, gain of -1, Q = V2/2 unless otherwise
specified.
ABSOLUTE RATINGS
Power Supplies ......... ±Vs : ±20V, Vc : +5.5V
Control Logic Input ................ Vc+O.5V
Analog Input .......................... ±Vs
FILTER CHARACTERISTICS
Frequency Program Range: FLJ-D1 •••
iFLJ-D2 •••
FLJ-DC •••
Frequency Program •••••.•.•.•••
Frequency Program Accuracy
Q Range .•.•••••••••••••..••
Rolloff .....................
Number 01 poles ••••.••••.•.•••
Voltage Gain ................ .
Pass Band Gain Variance .........
Resonant Frequency T.C.
Gain TC.
Distortion ...................
Noise ...•.•••••••••••••..•.
Load Resistance ...............
••

0

0

•••••

•

0"

••

••••••••

•••••••

0

••••

TECHNICAL NOTES
1. The cutoff frequency of lowpass and
highpass, and the center frequency of
bandpass filters can be set with three
digit BCD, TTL compatible logic inputs.
The MSD is hexadecimal. See table 1,
2. The cutoff frequency is shown as either
one equation of the following:
fc =

1Hz - 1.599KHz
100Hz -159.9KHz
Determined by external capacitors
BCD 3 digits, MSD is hexa-decimal (0-15)
±O.I%
1/3~Q~ 1 x 10· Ilc
12dB/oct (LP, HP), 6dB/octBW (BP)
2pole (1 pole pair)
1-10
Depends on external resistors

Number
C = 50,OOOpF is contained in FLJ-D1
and C = 500pF is contained in FLJ-D2
respectively, while no capacitor is contained in FLJ-DC .
The fc's of each model are:
N
FLJ-D1 : fc = N or fc

O.OI%f'C
0.2dB Full Temperature Range
0,002%
35pVrms (LP), l00pVrms (HP), 30jIVrms (BP)
2KO

FLJ-D2: fc=100N or fc

N

FLJ-DC : fC=20'C or fc

±10Vmin,
3OOKO
0,5mV
200nA

SiNf'C
±10Vl5mA min,
50 max,
38mA
10MHz
8V/pSec

POWER SUPPLIES AND ENVIRONMENT
Supply Voltages ............... ±VS : ±15V ±10%, Vc +5V±10%
+2,2mA
Supply Current •.••.••••.•.•••• +15mA,-18mA
Operating Temperature Range ...... -20'C - t70'C
Operating Humidity Range ........ 10%-95%RH
Storage Temperature Range ....... -30'C - +80'C
Storage Humidity Range •••••••••• 10%-80%RH

3.

4.

5.

ZENER OUTPUT (Fig. 3)
6.
+15V

1.4lK

IIfW

+

C : pF, N : Digital

N
fc = 21T'C'Af Hz, C: F, Af: 0, N : Digital

AMPLIFIER CHARACTERISTICS

Input Voltage Range ............
Input Impedance •••.••..••••.••
Input Offset Voltage •••••••••••••
Input Bias Current •.•.••..•••••.
Input Offset Drift •••.•••••••••••
Output Voltage/Current ..........
Output Impedance .0 ••..••••••.
Output Short Circuit Current .......
Small Signal Frequency Bandwidth ...
SlewRate ...................

2~C Hz,

Number

N
21T'5x10 l0'Af

N

21T.Cext.Af

The val ue of Af is 3.183KO for the
programmed fc logic is 1,000.
The value of Cext is calculated taking
these factors into consideration.
Each logic input is connected to
CMOS4000 series internally. Then each
input is pulled down with 1ooKO resistors. The use of 10KO pull-up resistors to +5V is recommended when
filters are programmed with TTL logic.
An independent +5V zener diode is
contained in the filter. The output voltage range of this diode is +4.87V +5.12V. The connection shown in
Figure 3 is recommended if a filter is
driven by ±15V supplies only.
Analog GND (Pin36) and logic GND
(Pin37) are separated to be useful for
universal applications. Connect
grounds of ±15V and +5Vexternally.
No return current of the digital power
supply should flow through the analog
ground.
The use of 4.7pF and 0.1pF bypass
capacitors for both ±15V and +5V lines
close to the module is highly recommended.

O.b

4.1# -

COM

+
4.7". -

0.1,1.1

-15V

6-12

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

FLJ-D1, D2, DC
BUTTERWORTH HIGHPASS (Fig. 4)

LOGIC INPUT CODING TABLE (Table 3)
Logic Input· 1

(LSD)

(MSD)

o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 0
o0 0 1
o0 1 0
o1 0 0
1 0 0 0
1 0 0 1
1 0 1 0
1 1 0 0
1 1 1 0
1 1 1 1
1111

o0
o0
o0
o0
o0
o0
o1
1 0

o0
o0
o0
o0
o0
o0
o0
o0
o0
1 0

0 0
0 0
0 0
0 0
0 1
1 0
00
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1

Note: 1. logiC 1 = + fN
logic 0 = GND

o0
o0
o1
1 0
o0
o0
o0
o0
o0
o0
o0
o0
o0
o0
o0
o0
o0
1 0

0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0

1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1

Decimal
Number

fc(Cutoff Frequency)

FLJ-Dl

1
2
4
8
10
20
40
80
100
200
400
800
900
1000
1200
1400
1500
1599

1Hz
2
4
8
10
20
40
80
100
200
400
800
900
1000
1200
1400
1500
1599Hz

FLJ-D2
100Hz
200
400
800
1KHz
2
4
8
10
20
40
80
90
100
120
140
150
159.9KHz

Ii

I

-I 0

O.IHz
0.2
0.4
0.8
1
2
4
8
10
20
40
80
90
100
120
140
150
159.9Hz

0

i· II

lAmp.

'.

j

I

0

I'
,I

0

o.

I

I

I

2
240

I
30

10

0.3

0.1

2 80

BUTTERWORTH LOWPASS (Fig.S)

iI

-I 0

!g

-2 0

:g

-30

1

-4 0

---j-{

I'i
I! ;

'"

N-

I

!:
I
! I,

I!,

I

n

I
40

'{Amp

II \.
. I

!

111I

I

iii I
-50

I
I

-60

i
I

II

-)0

0.03

~

~

I 60

i
Ii

0.3

~

"
T
.%

"\

2 00
2 40

I

0.1

80
I 20

i I Phase '-.

I

I i iI

,

_ Rg·(Rq+10')
0- Rq'(2Rg+10')

I

(f/fe)

The gain and 0 of this filter are set with the following equations.
1. Lowpass and highpass filters
G ="Rgx 10 (Rg. 0)

4G

I

i

-) 0 0.D3

f!

Gain

~se

V

0

-1

1

I--

a- OPEN

a

I-

i

-5
-6

Vi

11/

I-

'2.IFlJ-DC needs edemal capacitors.
These values are ones when two o. SJlF are used as
external capacitors

GAIN AND

I !II

lll\lI

0

FLJ-DC"

2 80

10

(f/fe)

10'
Rg = 10KO when G = -1. Then, Rq = 30-1
BANDPASS (Fig. 6)

Then, the following values are obtained.

o

~

Butterworth
0.70711
8.918KO
Bessel
0.57735
13.66KO
See Figure 4 and 5 for "Amplitude/Phase vs. Frequency"
characteristics.
2. Bandpass filter
-1
,
Gain.
G =Rgx 10 (Rg. 0)

o.

0= H(1/Rg+1/Rq)'10'

104
Rg = 10KO when G = -1. Then, Rq = 2(0-1)
Then, the following values are obtained.
2
5
10
See Figure 6 for reference.

~
5.00KO
1.25KO
5560

._-

~~

-10

-3

~

-4 0

~

°v

E
<0:

1

/

o~

-60

~"
\\\ "-

1./1/

-,0
~

-5

2

o

-'

l--'

V
-10

VV

I:/V

V/

V
0.1

_.-

)I

f--

V
0.03

\\ "-

0.3

.-

"-

-itt!

~I--

o~?'o~~ '-

~

O~I~~

10

30

(f/fo)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

6-13

II

FLJ-D1, D2, DC
APPLICATIOMS

I.

HIGHER ORDER LOWPASS AND HIGHPASS FILTERS
Several units of FLJ-D Series filters can be cascaded to
realize higher order filters. Any model can be used to make
Butterworth filters as the cutoff frequency of each stage is
equal.
The use of FLJ-OC is recommended for other type of filters
such as Chebyshev and Bessel because the cutoff frequency of each stage is different.
The value of external components are different at each
stage. The Tables 7 and 8 show the values of fn and an at
each stage.

N
then, 4.2170N = 20Cext therefore, Cext = 0.011857pF
= 11857pF
.
10'
Rq = 30 -1 here a =0.57503. therefore, Rq1 =13.7KO.
f. Rqn and Cextn of 2nd, 3rd and 4th stages are calculated
in similar ways. The Table 6 shows the results of the
calculations.
= Design Example 2 =
• Higher Order Highpass Filter/Calculation Example
To build 8th order Butterworth highpass filter using
FLJ-OC .
Gain should be +1, the cutoff frequency range should be
10Hz -15.99KHz.
a. Use 4 pieces of FLJ-OC. Gain of each stage is -1 and it
becomes +1 at the final stage.
-1
•
G =FiQx 10 , therefore, Rg = 10KO.

= Design Example 1. =
• Higher Order Lowpass Filter/Basic Theory
Following points should be understood referring to the
Figure 9.
a. Connections are the same either for Butterworth, Bessel
or Chebyshev.
b. Each module is used as a two-pole filter in case of even
order.
c. The first module is used as a one-pole filter and the rest
are used as two-pole in case of odd order.
d. Even order filter: Input is given to Input #2 ot Fig. 9.
Output is either Output #3, #4 or #5 depending on the
number of order.
In case of sixth order filter, for example, 3 pieces of
FLJ-O are used, input and output are Input #2 and
Output #4 respectively.
Proper values of Rg1 - Rg4, Rq1 - Rq4 and Cext1 Cext 4 are to be selected depending on filter type. See
Table 4,5,6.
e. Odd order filter: Input is given to Input #1 of Fig. 9.
Output is either Output #2, #3, #4. In case of fifth order
filter, 3 pieces of FLJ-O are used, input is given to Input
#1, Output #1 and Input #2 are connected, output is
taken from Output #3.
f. The fc program logic lines are connected to each other
of filter in equal ways.
• Higher Order Lowpass Filter/Calculation Example
To build 8th order, 0.05dB ripple, Chebyshev filter using
four FLJ-DC's.
Here, gain=+1, the cutoff frequency should be programmed befween 10Hz and 15.99KHz.
a. Use 4 pieces of FLJ-DC.
b. Output is inverted at every 2nd order. Output becomes
in phase with input at the final stage, in this case.
c. The relationship between the cutoff frequency and the
external capacitors of FLJ-OC is shown in the following
equation.
fc = 20NCext N: Digital Number (1-1,599) Cext pF,

b. See table 4 and obtain values of fn and an of each stage
under 8th Butterworth.
fc= 20~ext N: Digital Number(1-1,599) CextpFfcHz
The fn of each stage is 1.
N
Therefore, 10N = 20Cext then, Cext = 5000pF
c. Gain is -1 at each stage.
Rq =

3~-~ substitute values of an to obtain Rq of each

stage.
The results are shown in Table 9. See Table 10 for
Chebyshev highpass filter.
II.

BANDPASS FILTER
One-pole pair, two-pole pair and three-pole pair connections are shown in Figure 11. The values of external
components are shown in Table 11 .

III. BAND ELIMINATION FILTER
A band elimination (=notch) filter can be made using
FLJ-O Series filters.
A non-inverting type which employs LP + HP method is
shown inFigure 12.
An inverting type which employs 1-BP method is shown in
Figure 13.lt is recommended to use a non-inverting type for
a:§; 1 and inverting type for O;;E; 1 applications. A bandpass
filter of higher order is shown in Figure 14.

fc:Hz
If digital range of 10Hz -15.99KHz is desired, fc is equal
to 10N.
N
10N = 20 Cext then, Cext = 0.005pF = 5000pF
d. Gain of each stage is -1, then G=-1/Rgx10', then
Rg=10KO.
e. Refer to Table 7 and find out fn=0.42170 and
On=0.57503 at the crossing pOint of "8 Poles, 1st stage"
and "Chebyshev, 0.05dB ripple".
These figures mean that the cutoff frequency of the 1st
stage should be 0.42170 times of the total cutoff
frequency, and that the a of 1st stage should be 0.57503
respectively.
0.42170fc =

6-14

20~ext here substitute fc=10N

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

FLJ-D1, D2, DC
LOWPASS & HIGHPASS CONNECTIONS (Fig. 7)

HP Output

LP Output

10K

~-T-"--~--""'

+ 15V

:>...--+-+----'!oo COM
M-~4--~

Input RG

-15V

.>-1-....--..--_ + 5V
~~+---_GND

v

fe Set Logic Input

BANDPASS FILTER CONNECTIONS (Flg.S)

\-~_-_+15V

>-.-+-+--_ COM
\+........4--....-".. -15V
·H-....--..--_+5V
)~~----;,.GND

SpO 400 200 100 SO 40

v

20

10

S

4

2

1

-'

fc Set Logic Input

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

6-15

FU-D1, 02, DC
HIGHER ORDER LOWPASS RLTER (Fig. 9)

~~~~~~~~2~~§~~~~~~,~~~4~~~le~============~======~668~~le~=========,~-------8~le--------~\
Output #3

Output #2

Output #4

I
I

I

I
[
[

I

I

~--~----~-4~-F~~--_r----_r~~-r~~--_r-----r~~-r~~~_r~+15V

[
[

~-+~----~----+--+4-~----~~--~--t1-+~----_r----~-t_r~------~COM

[

L-------~----~_r~~------~----r__r+_~------~----r__r+_~------~ -15V
L--------------r~~--------------r_~~------------_t-~-L--------~+5V
GND

[
[

[

I
[

I
I

L __

---- --- - - ---- --- ---- ----- -- - - - -------,
. , - - - 1 Fble
' :
10K 10K
Input

0 Output

#1
Note: RIwer lines byJ)aSS capacitors;

#1

4.7"F and Q.1pF

'-"---t---~

;--H-+.------j----->"

12 logic lines

+ 15V

COM

-15V
'------------_ +5V
' - - - - - - - - - > " GI'[)
HIGHER ORDER HIGHPASS FILTER (Fig.10)

~-:~~~~~~~§~~~~==::::;4~p~o~le~============~=======ti6~p;;;iol;e=======::::::,------- 8 pole ----------\
.::

2

pole

,

Output #3

Output #2

I
I

I

I
[
[
I

I

~--_r----_r~~-f~~---r-----r~~-rt-~---r-----t~~-rt-~---r~+IW

[

I
I

I
I

I

I

~-+4---+--~-~rt~--i_--r-+-rt~----i-----t-~ti~----r~COM

-15V

L-------------~~~~------------~r_~L-------------~r_~~--------~ +5V
L------------------~~-------------------i_~----------------r_+----------~GI'[)

I

I
IL ______________________ ..... _____ - - - - - - - - - - - . ,

,

. , - - - 1 po~
10K 10K Cur
Input # 1

13 11

Output #1
Note: Power II,.. bypasS capecitcrs:

5

'--''--t---__>_

12 logic lines

6-16

1-H-------t-~

'.1 /.IF and O.lpF

+ 15V
COM

-15V
'-----------_ +5V
' - - - - - - - - - - > " GI'[)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

FLJ-01, 02, DC
BUTIERWORTH, LOWPASS EXTERNAL COMPONENTS (Table 4)

BUTIERWORTH, HIGHPASS (Table 9)

(FLJ-DC. fe:IOHz-IS. 99KHz. IGI = 1) (See Fig. g)
(FLJ·DC. fe:IOHz-IS. 99KHz, IGI= 1) (See Fig. 10)
2 pole

CEXTl

3 pole

4 pole

SOOOpF

CUT

SOOOpF

SOOOpF

CEKT2

5 pole

6 pole

7pole

SOOOpF

8pole

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

CUT]

Cuu

SOOOpF

CEXT!

3pole

4pole

5000pF

Cur
SOOOpF

SOOOpF

CEXT2

5pole

6pole

7pole

Spole

SOOOpF

SOOOpF
SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

SOOOpF

CEXTl

SOOOpF
SOOOpF

Cu.u

R••

10KQ

10KQ

IOKQ

10KQ

10 KQ

10K Q

10K Q

RG2

Rs

Rs

IOKQ

IOKQ

10 KQ

10K Q

10KQ

Rs

R.3

Rs

R..
R••

2pole

SOOOpF

8. 87K Q

4.99K

R.,

10 KQ

10KQ

10KQ

Rs

Rs

10KQ

16.2KQ

11.8KQ

18.2K Q

lSKQ

18.7KQ

3.4KQ

2.61KQ

8.87K Q 6.98KQ

12.4KQ

2.10KQ

R. 3

1. 74K Q S. 90K Q
I.S0K Q

R..
Input

#2

#1

#2

#1

#2

#1

#2

Output

#2

#2

#3

#3

#4

#4

#5

R••

10KQ

IOKQ

10KQ

10KQ

10KQ

10KQ

10K Q

R"

49.9 Q

49.9Q

10KQ

10KQ

10KQ

10KQ

10K Q

49.9Q

49.9 Q

10KQ

10K Q

10K Q

49.9 Q

49.9Q

10K Q

IS.OKQ

18.7KQ

R"
R..
R••

8.87K Q 4. 99K Q 16.2KQ

11.8KQ

18.2KQ

RQ2

3.4KQ

2.61KQ

8.87K Q 7 .ISK Q 12.4KQ
2.IOKQ

R. 3

1. 74K Q

S.9KQ

I. SDK Q

R..
Input

#2

Itl

1t2

Itl

1t2

Itl

#2

Output

1t2

1t2

1t3

#3

1t4

1t4

1t5

Rs=49.9Q

BESSEL, LOWPASS EXTERNAL COMPONENTS (Table 5)

CHEBYSHEV, HIGPASS (Table 10)

(FLJ-DC. fe:1 OHz- 15. 99KHz. IGI = I)(See Fig.9)
2pole

CEXT

Cun
CUT2

3 pole

4 pole

3924pF

3448pF

5 pole

7 pole

6 pole

3323pF

3774pF

Spole

(FLJ·DC. fe:IOHz-IS.99KHz, IGI=I) (See Flg.1O)
4pole(0.SdB) 5pole(O.SdB) 6pole(O.1 dB) 7pole(O.1 dB) 8pole(O.OSdB)

2964pF

1812pF

1884pF

3491pF

3208pF

3112pF

2908pF

2807pF

CUT

3113pF

2844pF

29SSpF

2739pF

272SpF

CEXll

298SpF

34S2pF

2566pF

2873pF

2109pF

2621pF

2436pF

2SS6pF

CEXT2

SIS6pF

S089pF

4172pF

4339pF

3348pF

2281pF

CEXll

S314pF

S226pF

10KQ

10K Q

10KQ

CUTe

CEXTl

CEXU

4SS8pF
S248pF

R••

10KQ

10KQ

10KQ

10KQ

R.,

Rs

Rs

10KQ

10KQ

10KQ

10KQ

10KQ

R••

IOKQ

IOKQ

IOKQ

10K Q

IOKQ

Rs

Rs

10KQ

10KQ

10K Q

R..

10K Q

IOKQ

IOKQ

10K Q

10K Q

49.9Q

49.9 Q

RG3

Rs

Rs

IGKQ

R. 3

18.7KQ

16.9KQ

19.1KQ

R..

5. 76K Q 12.1KQ

10.2KQ

14.7KQ

R••

8. 87K Q

4.87K Q 4.22K Q 8 .B7K Q

R.,

1. 27K Q

R..
R••

13. 7K Q

9.31KQ

17 .8K Q 14.3KQ
6.98K Q

RQ2
R.3

IOKQ

IOKQ

10K Q

49.9Q

49.9 Q

IOKQ

3.92KQ

12.4KQ

6.49K Q

13.7KQ

787Q

3.32K Q

2.21KQ

4.S3KQ

768Q

S62 Q

1. 78K Q

3. 74K Q

R.,

Input

#2

#1

#2

#1

#2

#1

#2

R..

Output

#2

#2

#3

#3

#4

#4

#5

Input

1t2

Itl

1t2

Itl

1t2

Output

1t3

1t3

1t4

1t4

1t5

R..

Rs=49.9Q

487 Q

CHEBYSHEV, LOWPASS EXTERNAL COMPONENTS (Table 6)
(FLJ-DC. fe:IOHz-IS.99KHz, IGI=I) (See Fig.9)

(

):Ripple

4pole(0.SdB) 5pole(0.SdB) 6pole(O.1 dB) 7pole(0.1 dB) Spole(O.OSdB)
13270pF

13800pF

e""
CUTl
CUT2
Cun

Rs=49.9Q

837SpF

7241pF

9743pF

8701pF

118S7pF

4848pF

4913pF

S992pF

S761pF

7467pF

470SpF

47B4pF

S48SpF
4764pF

Cuu
R••

10KQ

IOKQ

IOKQ

10KQ

10K Q

R..

10KQ

IOKQ

IOKQ

10KQ

10K Q

RG3

Rs

Rs

IOKQ

10K Q

10K Q

Rs

Rs

10KQ

R..
R••

8. 87K Q

3.92KQ

12.4KQ

6.49K Q

13. 7K Q

R.,

1. 27K Q

787 Q

3.32K Q

2 .21K Q

4.S4KQ

768Q

S62Q

1. 78K Q

R.,

487 Q

R..
Input

#2

#1

#2

#1

#2

Output

#3

#3

#4

#4

;!f5

DATEl, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194iTEl (508) 339-3000iTlX 174388/FAX (508) 339-6356

6-17

.i

FW-D1, 02, DC
HIGHER ORDER BUTTERWORTH{LP, HP), BESSEL(LP), CHEBYSHEV(LP)·· ·fn, On Table (Table 7)
Butterworth

No.
of
FIlla
2
3

1st
2nd,

4

1st
2nd

1st
5 2nd
3rd
1st
6 2nd
3rd
1st
2nd
7
3rd
4th
1st
2nd
8
3rd
4th

Chebyshev(LP)
0.2dB
0.25dB
In
In
On

Bessel(LP)

fn

Qn

fn

Qn

1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0
1.0

0.707107
0.5
1.000000
0.541196
1.306563
0.5
0.618034
I. 618034
0.517638
0.707107
1.931852
0.5
0.554958
0.801938
2.246980
0.509796
0.601345
0.899976
2.562915

I. 2742

0.57735
1.32475 0.5
I. 44993 0.69104
I. 43241 0.52193
I. 60594 0.80554
I. 50470 0.5
I. 55876 0.56354
1.75812 0.91652
1. 60653 0.51032
1. 69186 0.61120
1. 90782 1. 0233
1.68713 0.5
1.71911 0.53235
I. 82539 0.66083
2.05279 1.1263
I. 78143 0.50599
1. 83514 0.55961
1.95645 0.71085
2.19237 J. 2257

0.05dB(Aipple)
fn
On

0.88526
I. 22098
0.61901
0.85362
1.13476
0.56933
0.87014
1. 09094
0.43017
0.61098
0.89236
I. 06561
O. 4~170
0.66965
0.91166
I. 04963

0.60017
I. 99842
0.5
0.85227
2.96615
0.58116
1. 21335
4.15611
0.5
0.78823
1. 66357
5.56621
0.57503
1. 07710
2.19456
7.19539

O.ldS
fn

Qn

0.78926
1.15327
0.53891
0.79745
I. 09313
0.51319
0.83449
1.06273
0.37678
0.57464
0.86788
1. 04520
0.38159
0.64514
0.89381
J. 03416

0.61880
2.18293
0.5
0.91452
3.28201
0.59946
1. 33157
4.63290
0.5
0.84640
I. 84721
6.23324
0.59318
1.18296
2.45282
8.08190

0.70111
1.09483
0.46141
0.74726
I. 05708
0.46032
0.80306
1.03823
0.32431
0.54170
0.84643
1. 02745
0.34344
0.62334
0.87820
J. 02070

0.64590
2.43501
0.5
I. 00091
3.70686
0.62595
I. 49172
5.26890
0.5
0.92694
2.09299
7.11866
0.61944
J. 32615
2.79620
9.25500

0.67442
I. 07794
0.43695
0.73241
1.04663
0.44406
0.79385
I. 03112
0.30760
0.53186
0.84017
I. 02230
0.33164
0.61692
0.87365
I. 01679

0.3dB

0.5dB

On

In

On

0.65725
2.53611
0.5
I. 03593
3.87568
0.63703
1.55565
5.52042
0.5
0.95956
2.19039
7.46782
0.63041
1.38326
2.93174
9.71678

0.65324
I. 06482
0.41713
0.72076
I. 03851
0.43103
0.78666
I. 02560
0.29400
0.52411
0.83528
1.01829
0.32219
0.61189
0.87011
1.01375

0.66778
2.62790
0.5
I. 06790
4.02836
0.64729
I. 61360
5.74741
0.5
0.98931
2.27837
7.78256
0.64058
I. 43501
3.05398
10.1327

In

On

0.59700

0.70511
2.94055
0.5
1.17781
4.54496
0.68364
I. 81038
6.51285
0.5
I. 09155
2.57555
8.84180
0.67657
I. 61068
3.46567
II. 5308

I. 03127

0.36232
0.69048
I. 01773
0.39623
0.76812
1.01145
0.25617
0.50386
0.82273
1.00802
0.29674
0.59887
0.86101
I. 00595

HIGH ORDER CHEBYSHEV(HP)·· ·tn, On Table (Table 8)

No.
of
FIlle
4
5

6

7

8

6-18

Chebyshev(HP)
O. 05dB(Aipple)

O.ldS

O.ldS

0.25dS
2.53611
0.65725

0.3d8
fn
Qn
2,62790
1. 530831
0.939126
0.66778

O.5dB
fn
Qn
1. 675042
2.94055
0.969678
0.70511

2.28859
1.365355
0.955447

3.87568
1.03593
0.5

2.397334
1. 387424
0.962918

4.02836
1.06790
0.5

2.759991
1. 448268
0.982579

4.54496
1.17781
0.5

5.26890
1. 49172
0.62595

2.25195
1. 259684
0.969819

5.52042
1. 55565
0.63703

2.320024
1. 271197
0.975039

5.74741
1. 61360
0.64729

2.523787
1. 301880
0.98868

6.51285
1. 81038
0.68364

3.083470
1. 846040
1.181433
0.973283

7.11866
2.09299
0.92694
0.5

3.25098
1. 880194
1.19024
0.97819

7.46782
2.19039
0.95956
0 ..5

3.401361
1.907996
1.197203
0.982039

7.78256
2.27837
0.98931
0.5

3.903658
1. 984678
1. 215466
0.992044

8.84180
2.57555
1. 09155
0.5

2.911117
1. 604261
1.138693
0.97972

9.25500
2.79620
1. 32615
0.61944

3.015318
1. 620956
1.144623
0.98349

9.71678
2.93174
1. 38326
0.63041

3.103759
1. 634281
1.149280
0.986436

10.1327
3.05398
1. 43501
0.64058

3.369953
1. 669811
1.161427
0.994085

11.5308
3.46567
1. 61068
0.67657

fn

Qn

fn

Qn

fn

Qn

fn

Qn

1st
2nd

1.129612
0.819014

J. 99842
0.60017

J. 267010
0.861100

I. 426310
0.913384

2.43501
0.64590

1. 482756
0.927695

1st
2nd
3rd
1st
2nd
3rd
1st
2nd
3rd
4th
1st
2nd

1. 615483
1.171481
0.881244

2.96615
0.85227
0.5

1. 855597
1. 253997
0.914804

2.18293
0.61880
3.28201
0.91452
0.5

2.167270
1. 338222
0.946002

3.70686
1. 00091
0.5

1. 756451
1. U9240
0.916641

4.15611
1. 21335
0.58116

1. 948596
1.198337
0.940973

4.63290
1. 33157
0.59946

2.172402
1. 245237
0.963178

2.324662
1. 636715
1.120624
0.938430
2.371354
1. 483317
1. 096900
0.952717

5.56621
1. 66357
0.78823
0.5

2.654069
1. 740220
1.152233
0.956755

6.23324
1. 84721
0.84640
0.5

7.19539
2.19456
1. 07710
0.57503

2.620614
1.55005i
1.118806
0.966968

8.08190
2.45282
1.18296
0.59318

3rd
4th

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

FLJ-01, 02, DC
HIGHER ORDER BANDPASS FILTER (Fig. 11)
~-------------------------3pole·pair(6pole)---~

r - - - - - - - - - - - - - - - 2pole·palr(4pole)-----,
r-----lpole·pair(2pole)~

Output #2
Output#3

Input

~~~--+--~+-~~~-+--~-~~-+~~~-~-~+15V
~~~---+---+--4-+~~---4--4--~4-+-~--~--~COM
L----~--+--~4-~----4--~--+-+~-

___ ·~_ _~-15V

L--------+--~~-------~--+~--------~+5V
L--------+--+--------+--~-------~GND

12 logic lines

BANDPASS FILTER (1 POLE-PAIR, 2 POLE-PAIR, 3 POLE-PAIR) (Table 11)
(TotaIIGI=l, Q=2, 5, 4.32, 10

fo=10-15.99KHz)

(See Flg.ll)

1 pole-pair, Inverting

3pole-pair, Inverting

2pole-palr. Non-Inverting

Q

2

5

10

2

5

10

2

4.32 (I/30cl)

5

10

CEXTl

5000pF

5000pF

5000pF

4182pF

4658pF

4826pF

4027pF

4523pF

4585pF

4788pF

5978pF

5367pF

5180pF

CEXT2
CEXT.1

5000pF

5000pF

5000pF

5000pF

6208pF

5527pF

5452pF

5221pF

10K 9

10K 9

10K 0

10K 0

10K 9

10K 0

10K 0

RG,

lOKI)

lOKI)

lOKI)

10K 0

10KO

RG,

49.90

49.99

49.99

4.87K 9

4. 99K 9

49.90

49.90

49.99

2. 37K 0

2. 49K 0

2. 49K 0

2. 49K 0

2.67K 0

8250

3839

1.62K 0

6490

5490

2619

3. 74K 0

8870

3920

4. 99K 0

1.5K 9

I. 24K 0

5490

3.40KO

8060

6650

2870

RG,
RQ ,

4.99KO

I. 24K 9

5620

RQ,

10K 0
4. 99K

Q

RQ,
f,

1.0

1.0

1.0

f,

Q,

2.0

5,0

10.0

!

1.19550

1.07340

1.03600

1.24166

1,10547

I. 09046

1.04425

0,93162

0.965251

1.0

1.0

1.0

1.0

0.80537

0,90459

2.87

7.09

14.15

4.094

8.68040

2.87

7.09

14.15

2. 00000

4,31847

4.094

8.68040

Q,
Gain

•

Q

0.83647

f,

Q,

10K

6.30dB

6,06dB

6.03dB

12.45dB

12.13dS

0.91704
10.04
5.0000

0.95763
20,01
10 .000

10 .04

20,01

12, lidS

12.06dB

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

6·19

FW-D1, 02, DC
1POLE-PAIR(2 POLE)BAND ELIMINATION FILTER (Fig.13)

1POLE-PAIR(2 POLE)BAND ELIMINATION FILTER (Fig.12)
Non-Inverting (LP + HP, fo: I OHz- 15. 99KHz)

Inverting(I-BP. fc:IOHz-IS.99KHz) 0=5

Zt<

9.09K

Note:UseatO;:;;;1

~K

~
10K

9.09K

Note: Use at a;;ct

~
49.9

10K

10K

,-J\1\rt-""""".....--~JVv---
-10

0

~ r-----

~ :'\ "- ~

-20

~

-30

\\\

\\\ \

-'0

~

2~

-20

r---..

\

3~

\\\\ 1\ \

-so

.~ 1\
\\\\ !&~ \ '\

-10

8j\\'m \ \
0.05

0.1

0.2

0.5

10

'V V

. / v1~

0

'"

\\\\

-60

.---;j} t<-

-IO

'PO~

V 1//;$
/3""jt //~

0

-50
-60
-1 0

20

/1,
V /;~

1/

1

/

II
O.OS

;'~'///1
&~ '1/1

/po~U 18i~
11,7po~

0.1

0.2

Relative Frequency(f/fc)

0.5

LOWPASS, CHEBYSHEV (Fig. 17)

~

-20

~

\\\ 1,\

-30

-.

\

-40

\ \ 4po1e(0.SdB)

-so

!

0.05

0.1

0.2

0.5

0.05 0.1

20

'po~

0.2

RelatIVe Frequency(f/fc)

8 .... \
10

0.5

20

Relative Frequency(f/fc)

BANDPAss, 2 POLE.pAlR(4 POLE) (Fig.19)

BAND EUMINATlON, 1 POLE-PAIR(2 POLE) (Fig. 20)
Q=IO

VI

-10

\\
V/ / \\ \ \
/ V 'I \ \ \
,\ Q,\
/ / /1/

I

-30
-'0

-SO
-60
-10

/

1//

1

V II

0.05

0.1

O.S
Relative Frequency(f/fc)

-,0

~'

r'\

-so

r'\

[\\
'\

'\

\
0.2

Q=I

-30

\ '\

/ /

ff

-20

~=I:0 Q=S

1/ /

~

-I 0

/1/

-2C

i

0

1\\

10

20

-60
-10

0.1

0.2

O.S

1

10

Relative Frequency(f/fc)

DATEL, Inc. 11 Cabot Boulevard, Mansfield. MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

•.

\
,:

r\\\ &"""

8po~

10

I

\t

l\\ \'"\

7~ l\\\

-1 0

1)\6poje(0.'d8)
7P<'e(0.ld8) \ \i \1

2"""1

l\\

-60

\\\ l

-10

~I\ \

0

-so

1\\~OSdB;,

-60

20

~~

-I0

\\

-20

10

LOWPASS, BESSEL (Fig.la)
0

-10

1

Relative Frequency(f/c)

6-21

FW-D1, 02, DC
HIGHPASS, BUTTERWORTH (Fig. 16)

LOWPASS, BUTTERWORTH (Rg.15)
--.,
-10

~ "-

\\\ .'\ ",\\

'!

!!

-30

-40

\\\\

-50

-70

0.1

0.2

O.S

lC/VI
Vlpo~ VI;

""

0/

-6

\

-70

\

10

/ 3po'

-50

1\

,
20

11

V IIII,
i' I/h

0

3pole

1

./

0

"-

SpoIe\\6F,le \
1 7pole\
0.05

-20

~"-

2pole

\
\\\\ 4~e
\\\ \ 115~1e \

-60

/ ' ~~

-I0

lpo~

""
~\ \ \

-20

I

0

II)
/ 5~~1 1//
IApoIe'!

/

II
0.05

Ilpole [f)_Spole
11,7pole '1
0.1

0.2

Relative Frequency(f/fc)

0.5

1

10

20

Relative Frequency(f/c)

LOWPASS, CHEBYSHEV (Fig. 17)

LOWPASS, BESSEL (Fig. 18)
0

-10

-20

~

-'0

,

-3 0

0.05

0.1

0.2

0.5

10

l\\

-60

8 pole
0.05 0.1

20

\Ie\

7po1e \\ \ '

-70

6poIe(0.ld8)
7pole(0.ld8) \

~

l\\

-50

1\\\
l
1)\
\r \ 'I

-70

f\
1\ '\ 2pole l

-40

~pole(O.5dB)

\\5~~05d8i

-60

~

-20

,

-so

" \\

-I0

~

0.2

Relative Frequency(f/fc)

0.5

4 pole

\\\ 5,01.
6 pole \
10

1\
20

Relative Frequency(f/fc)

BANDPASS, 2 POLE-PAlR(4 POLE) (Fig.19)

BAND ELIMINATION, 1 POLE-PAIR(2 POLE) (Fig. 20)
Q=IO

-10

-2C

I..

-30
-40

E

-50

V; 1\\

\1\
VI Ii \\ 1\ \
/ II 'I \ \ \
/ / III \\ Q~ ~I
~=I.0
VI
/ /
1\ '\
\ \
,,\
1// I V
/ /
\ '\ "
/11

Q=5

-60
-70

0.05

0.1

0.2

0.5

Relative Frequency(f/fc}

6-22

10

20

\\ ~r

-I0

Q 1

-20

-30

-.

0

-50
-60

-70
0.1

0.2

0.5

1

10

Relative Frequency(f/fc)

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

FLJ-D5,D6
DIGITAL-PROGRAMMABLE,
HIGH-ORDER LOWPASS FILTER
FEATURES
• 6OdB, SOdB/octave rolloff lowpass
fiRer
• Cutoff frequency programmed by
logic at B points
• Compact, lightweight, hybrid IC
construction

_,

Input

;.. ';':).;'J.

>---'-0

~

•

Cf

28.1K

11

1

1

A

A

.

28.1K

56.21<

Ro,

.

"'"
I.

;'L

. ~

;'L

~v ~v ~v

~ 1~Aoor1001(

.,

"""~

2

iNH 4

2

t

A

~

1

1

1>

~

CI

~
•

1

'Wrj

~

.

Cf

A

~

4

•

A

A

. !.

CI

~

R

IControl Circuit

Opm,.01

CI

(> ~ .~

~

4.7,.,

1

A

56.2K

GENERAL DESCRIPTION
The FLJ-OS and -06 series are lowpass
filters that although are compact, have
higher order and high attenuation performance. They are Chebyshev type filters.
The FLJ-OSLA is a 5-pole filter which has a
rolloff of 60 dBloct and the FLJ-06LA is a
6-pole filter with a rolloff of 80 dBloct. The
cutoff frequency is programmed with 3-bit,
TTL-compatible digital logic and the settings can be changed to 8 different levels.
Cutoff frequency range of the lower range
type which has suffix 1 is 10Hz-2kHz, and
the higher range type has suffix 2 is 100Hz20KHz.
Ripple within the pass band is minimal at
0.13dBp-p and the distortion rate is held
extremely low at O.OS%. These filters are
optimal as anti-aliasing filters in AlO
conversion circuits of data acquisition
systems.

ReXl3

Re"'2

:·_;·/-TU·'··-':·/·-r··1h

('Mi
180

701<

1

L·,,·'.:"~_ --it-- ~~-':··r~·-1 .. --J

"''''.

~

3
<

",,,,5

.'5~~5V '----- Output

Offset Adjustment

4.7"

+ 15V GND -15V

FLJ-DSLA 1, 2 Block Diagram and Connection Diagram (Fig. 1)
Cf in the diagram is 10000pF for the Suffix 1 model and 1000pF for the Suffix 2 model.

~t

ReX! 1 Cexl Rext 2 CelCI

Rexl3

;l-J'-r -~~-~.JV"r-~i ~--~
5

Rext 4

Cext

~¥~;"-r-"'!'~':-~~-1

•

•

I

FLJ-DSLA1, 2 (Fig_4)

0.2

,
!,

-0. 2

·50
-60

f'.. W

·0.4
0.1

-30
-40

~ 0 ,......
c:(

·10
·20

II
I

:!O

~

,

I
I

m

•

10

I

i
1

fH.lli

10

·70

100

Normalized frequency fffe

FLJ-D6LA1,2 (Fig. 5)
10

I

o

I

II
I
I

~

i
'5. o.
.!1

2

0.1

·20
·30

\

0
.0. 2
.0 4

-10

I
1

"

-40

o.Om10.01

·50

+ -

+-

-60

4.7~

4.7"

·70
10

Normalized frequency fife

100

.'5V

GNO

'2 T
+ 15V 10K .15V

Output

Offset Adjustment

·15V

FLJ-DSLA1, 2 Block Diagram and Connection Diagram (Fig. 2)
Cf in the diagram is 10000pF for. the Suffix 1 model and 1000pF for the Suffix 2 model.

ORDERING INFORMATION
Low Cutoff Frequency Type (10Hz-2KHz)
FLJ-OSLA 1: 6OdBloct., 5-pole lowpass,
Chebyshev
FLJ-06LA 1: 8OdBloct., 6-pole lowpass,
Chebyshev
High Cutoff Frequency Type (100Hz-20KHz)
FLJ-OSLA2: SOdB/oct., 5-pole Iowpass,
Chebyshev
FLJ-06LA2: SOdBloct., 6-pole Iowpass,
Chebyshev

MECHANICAL DIMENSIONS (Fig. 3)
Inches
(mm)

Pin 1 Identification

~:;;)

r---='-----j

Pin Cross Section 0.009 )( 0.009"
(0.25 • 0.25mm)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

6-23

FW-D5,D6
SPECIFICATIONS (Table 1)

Typical at 25°C and ±15V supply voltage unless otherwise specified.
ABSOLUTE RATINGS

Supply voltage (±Vs) ....•...........••......••....•.....••...... ±16V
Input voltage •...•....•.....•..••••..........••.......•..••..... ±Vs
Logic input voltage ....•..........•.••........••.•......•..•... +5.5V
FILTER CHARACTERISTICS, CUTOFF FREQUENCY
Low Range (10, 20, 50, 100, 200, 500., 1K, 2KHz, 8 points programmable, at -3dB)
FLJ-D5LA1 •• "."........ 5-pole Chebyshev
FLJ-D6LA 1 ".".,........ 6-pole Chebyshev
High Range (100, 200, 500, 1K, 2K, 5K, 10K, 20KHz, 8 pOints programmable, at OdB)
FLJ-D5LA2 •• • • • • • • • • • • • •• 5-pole Chebyshev
FLJ-D6LA2 ••••• , • • • • • • • •• 6-pole Chebyshev
Setting of Cutoff Frequency ••• 3-bit binary, TTL-compatible
Control

Model 2 lNH T
T l'
"0": +5V or OPEN
100Hz
0
0
0
0
''1'':
OV
20
200
0
1
0
0
50
500
0
0
1
0
100
1KHz
0
1
0
1
200
2K
0
1
0
0
500
51<
0
1
1
0
lK
10K
0
1
1
0
2K
20K
0
1
1
1
Accuracy of setting of
cutoff frequency •• , •••••••• ±3%max.
Modell
10Hz

PASS BAND CHARACTERISTICS
Gain
OdB±O.3dBmax. (0.05fc)
Ripple •••••••••••••• , •••• 0.13dBp-p (central designed value)
Distortion rate
0.05%
ROLLOFF CHARACTERISTICS
FLJ·D5LA 1,2
FLJ-D6LA 1,2
RoUoff ••••••••••••••••••• 6OdB!oct
SOdB!oct
Attenuation volume , , •••••••• 60dB (1.821e)
74dB (1.9fe)
Minimum attenuation
74dB
60dB
Attenuation at 10fc·1MHz •••••• 55dBmin.
6OdBmin.
INPUT CHARACTERISTICS
Input impedance •••••• , ••••• 5OKOmin.
Maximum input voltage ••••••• ±10Vmin.

....................

.............

OUTPUT CHARACTERISTICS
Output impedance •• , •••••••• 1000max.
Maximum output voltage •••••• ±10Vmin.
Noise (input shorted) ••••••• ,. 140llVrms max. (BW1 OHz-5OOKHz)
Offset voltage •••••••••••••• 10mV adjustable
POWER SUPPLY AND ENVIRONMENTAL CONDITIONS
Supply voltage •••• , •••••••• ±15V ±1Vmax.
Power consumption current ••• ' ±2BmA (FLJ-D5),
±33mA (FLJ-D6)
Operating temperature!
Humidity range •••• , •• , ••••• -20°C to +70°C, 10%-95%RH
Storage temperature!
Humidity range ••••••••••••• _30° C to +80° C, 10%-80%RH

LOGIC INPUT PINS (Fig. 6)

CASCADE WIRING DIAGRAM (Fig. 7)

TECHNICAL NOTES
,. Use a series-type power supply lor the FLJ-D5
and -D6, because a switching-type power supply
is not recommended. Install O.OIIlF multilayer ceramic and 4.71lF tantalum bypass capacitors in
parallel as close to the lilter as possible.
2. Each logic input (Pins 21-24) which programs the
cutoff Irequency hasan internal analog comparator as shown in Fig. 6. External logic signals are

TTL-compatible.
3. The Ic selling input logic is negative true. Terminal open or +5V represents logic "0", while GND
level is logic "1". The 1NH terminal is used
normally open. Once INH is given logic "I ", ali4.2
andTlogic inputs are inhibited and all internal
resistor network switches are opened. The fe
setting with external resistors becomes available

with logic "1" at this INH terminal. The relationship between 1e and the external resistors in this
case is as follows:
FLJ-D5LA 1 (Low Range Type)

Rext1

31.423 x 10' (KO)
Ie (Hz)

Rext2 = Rext3

21.399 x 10'
Ie (Hz) (KO)

Rext4 = RextS

16.358 x 10' (KO)
Ie (Hz)

FLJ-V6LA1 (Low Range Type)

Rext2

29.622 x 10' (KO)
Ie (Hz)

Rext3 := Rext4

18.633 x 10' (KO)
Ie (Hz)

Rext5:= Rext6

15.215 x 10' (KO)
Ie 1Hz)

Rextl

=

FLJ-DSLA2 (High Range Type)

Rext1 =

Rext2 = Rext3

314.23 x10' (KO)
Ie 1Hz)
213.99 x10' (KO)
Ie (Hz)

x 10'
Rex!4 = Rex15 = 163.58
Ie 1Hz) IKO)
FLJ-D6LA2 (High Range Type)

Rext1 = Rext2

296.22 x 10' IK
Ie 1Hz)
0)

Rex!3 = Rex!4 = 186.33 x 10' IKO)
Ie 1Hz)
Rex!5 = Rext6

152.15 x 10'
Ie 1Hz) IKO)

4. An II-pole ultra-high allenuation Ii Iter is available once cascaded as shown in Fig. 7. As can be
seen Irom the curves (Figs. 4,5), the amplitude 01
the ripple in the pass band is reversed between
FLJ-D5LA and FLJ-D6LA. As a result, when
connected in a cascade, the pass band ripple
amplitude is greatly reduced, and moreover, the
rolloff becomes steeper.

5. Forlilters that have been constructed like those in
this series, it is not recommended to change the Ic
selling range with external capacitors. This is
because trimming of. 'the internal constants is

performed with pairs 01 internal resistors and
capacitors. Although shifting to a lowerlc selling
range is possible through the addition 01 external
(Pins

6-24

21-24)

capacitors, in this case a change will result in

ripple amplitude.

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

FLJ-R SERIES
HIGHER ORDER,
RESISTOR-TUNEABLE FILTER
FEATURES

Input

• 135dB, 100dB/octave high order,
lowpass filter
• 1/3 octave bandwHh (Q=4.32)
bandpass fiher
• Can set cutoff (fc) frequency wHh 6 or
8 external resistors
• Uhra-compact size, high-function
hybrid construction

AI

r'.''r-',";'''\!

AI

Cext

Cext

--n-'U-l
""---fi,'-',''''''''J' }----{!or--*~_(33\HI&-~>---~~

GENERAL DESCRIPTION
The FLJ-R series filters are of the highest
order and have the highest attenuation
characteristics among the entire group of
DAlELfilter products. Through the use of
hybrid techniques, even though compact in
size, the FLJ-R series filters have complete
8-pole lowpass and 3-pole pair bandpass
fiHer functions. The cutoff (centrai) frequency
can be set with only 8 or 16 external
resistors.
Bandpass ripple in the lowpass filter is
0.1 dB and boasts outstanding performance
with the distortion ratio for all models being
a mere 0.005%. Each model is composed
of the Suffix 1 and Suffix 2 types and varies
according to cutoff frequency setting
range. The Suffix 1 model has a range
from 10Hz-2KHz and the Suffix 2 model
has a range from 100Hz-20KHz. The FLJ-R
series filters are optimum as anti-aliasing
filters in AID conversion circuits of data
acquisition systems.
The FLJ-R3BA1 ,2 are 1/3 octave, bandpass
filters that meet IEC-225 Standard requirements.

~.::...':

C~xt

AI
;. 15V

Output

GND -15V

FLJ-R8LA, B Block Diagram with External Connections (Fig. 1)
Input
RI

Cext

--H--

AI

Cel(!

-;;'-1

ORDERING INFORMATION
70K

50

Low Cutoff Frequency Type (10Hz-2KHz)
FLJ-R8LA 1: 135dB/oct., 8-pole lowpass,
Chebyshev
FLJ-R8LB1: 100dB/oct., 8-pole lowpass,
Chebyshev
FLJ-R3BA1: 3-pole pair bandpass
High Cutoff Frequency Type (100Hz-20KHz)
FLJ-R8LA2: 135dB/oct., 8-pole lowpass,
Chebyshev
FLJ-R8LB2: 100dB/oct., 8-pole lowpass,
Chebyshev
FLJ-R3BA2: 3-pole pair bandpass

11

Output

FLJ-R3BA Block, Diagram with Extemal Connections (Fig. 2)
MECHANICAL DIMENSIONS (Fig. 3)
Inches
(mm)

Pin 1 Identification

~5~~)

1"'-----'----'----1

Pin Cross Section 0.009 x 0.009"
(0.25 x 0.25mm)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

6-25

FW·R
TECHNICAL NOTES
1. Setting the cutoff (central) frequency
is accomplished with 8 external resistors which are equal in value for lowpass filters and 6 external resistors
which are equal in value for bandpass
filters. The relationship between the
resistance Rf of the external resistors
and the cutoff frequency fc is as
follows:

SPECIFICATIONS
Typical at 25°C and ±15V supply voltage unless otherwise specified.
ABSOLUTE RATINGS
Supply voltage (±Vs) ............•.•.•.•...••••.•••......••...•.. ±18V
Input voltage ...•.•...........•••..•.•••••.•............•...•... ±Vs
FILTER CHARACTERISTICS
Ic setting range ............
Ic setting •..•.•..•..•••••.

Suffix 1: 10Hz·2KHz
Suffix 2: 1ooHz·20KHz
8 equivalent lowllass or
6 equivalent bandpass
external resistors

Ic setting accuracy •.••.•••.•

±2"/omax.

Suffix 1 model (10Hz·2KHz)

RI =

PASS BAND CHARACTERISTICS
FlJ·R8LA B
FLJ·R3BA
Gain ........ ............ OdB±O.l dBmax. OdB±ldBmax.
Gain after RI adjustment ......
OdB±
Ripple p.p ................ O.l5dB
Ripple ~.9fc .............. O.3dBmax.
Ripple after RI adjust .•••..•.. O.ldB
Distortion ratio ••..••••••.•. O.oo5%@lKHz
'Same as left
ROLLOFF CHARACTERISTICS
FlJ·R8LA
FlJ·R8LB
Attenuation rollol! •.••...•••• 135dB/oct
1oodB/oct
a ......................
92dB@2.0Ic
Attenuation volume ......•••. 86dB@l.56fc
Minimum attenuation
86dB
l06dB
Attenuation at lOfc·1MHz .•...• 8OdBmin.
86dBmin.
INPUT CHARACTERISTICS
Input impedance .••......•.. 5OKOmin.
Maximum input voltage ...•.•. ±10Vmin.
OUTPUT CHARACTERISTICS
Output impedance ...•••.•... 1oo0max.
Maximum output voltage ••..•. ±10Vmin.
Noise (input shorted) .......•• 140pVrms max. (BW10-500KHz)
Offset voltage ......••.••••. ±10mV zero adjustable
POWER SUPPLY AND ENVIRONMENTAL CONDITIONS
Supply voltage (operating range) ±15V (±5V-±18V)
Power consumption current .... 40mA(FLJ-R8),
25mA (FLJ-R3)
Operating temperature I
Humidity range ..•........•• -20·C to +lO·C, 10%-95%RH
Storage temperaturel
Humidity range •...••..•.... -30·C to +80·C, 10%-80%RH

o-

+20

f-

f-

o

m
'0

-20

-; 0.1
'0

~

0

v

-60

Q.

~-0.1

l-

-80

I-

-100

I.---

L.

0.1

1

10

Normalized frequencyfllc

6-26

FLJ·R3BA
4.32(BWl/30ct)
18dB/octBW

159

100

8OdBmin.

1\

\

-20

l-

-40

;--20

I-

-60

~-40

-80
-100
0.1

(KQ)

C.X!

159

ICox! +0.001) x te

(KQ)

FW-R3BA1, 2 (Fig. 6)
10
0
m-l0

-0.2
0.01

Suffix 2 model

(C.x! +0.01) x te

In this case, the external capacitors
should have high dielectric characteristics. It is recommended to usemultilayer ceramic capacitors. Further, tolerance of these capaCitors should be
within ±O.25%. For filters such as
these of higher order and with high
attenuation characteristics, the uniformity of the tolerance of external
resistors and capacitors has an effect
not only on the accuracy of the setting range, but also on the size of pass
band ripple.
2. Use series type power supplies forthe
±15V power supplies because switching-type power supplies are not recommended. Install 4.7pF tantalum
and O.01pF multilayer ceramic bypass
capacitors. It is recommended that
these be installed in parallel, and as
close to the filter as possible, between
the ±15V powersupplies and ground.
3. Use metal film resistors with a tolerance better than 1% for the 6 or 8 fc
setting resistors.

0

0.1
.~
0

IKQ)

where Cext is measured in 11 F and fe in Hz.

+20

f-

~

-0.2
0.01

Cex! =

f-

-40

~-0.1

«

Suffix 1 model

~

m
~

= 1591~ 10'

The FC setting range can be shifted to
a lower band by adding external capacitors Cext. The equation shown below should be used for reference.

FW-RBL81, 2 (Fig.S)

c-

RI

where Ie is measured in Hz.

-

FW-RBLA1, 2 (Fig. 4)

Suffix 2 model (100Hz-20KHz)

15.91~ 10' IKQ)

1

1/

10

Normalized frequency flfc

100

1\

\

\
\

~-30

« -50

1\

-60
0.1

1

Normalized frequency fllc

10

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

FLJ-UR Series
Single In-line Hybrid
Resistor Tuneable Filter
FEATURES
• Small and thin size
• A variety of families
• Cutoff frequency fc is set by only
two or four resistors
• Light weight, low cost

GENERAL DESCRIPTION
The FLJ-UR series filters are single in-line
package resistor tuneable filters. They are
small in size and can reduce installation
space on the printed circuit board. The
cutoff frequency can be easily set by only
two or four external resistors. The series
have a variety of products, allowing system designers to make a wide-ranging
selection to suit the applications.

FW-UR4LB1/2 Block Diagram (Fig. 1)

•
LOW CUTOFF FREQUENCY TYPE (40 HZ-1.6 kHz)
FLJ-UR4LA 1:
FLJ-UR4LB1:
FLJ-UR4HA 1:
FLJ-UR4HB1:
FLJ-UR2LH1:
FLJ-UR1 BA1:
FLJ-UR2BA 1:
FLJ-UR2EA 1:

4-pole
4-pole
4-pole
4-pole
2-pole
1-pole
2-pole
2-pole

lowpass, Butterworth
lowpass, Chebyshev
highpass, Butterworth
highpass, Chebyshev
lowpass/highpass, Butterworth
pair bandpass, Butterworth
pair bandpass, Butterworth
pair band elimination, Butterworth

HIGH CUTOFF FREQUENCY TYPE (400 Hz-5 13 kHz)
FLJ-UR2LH; fel10 (LPF). 10 Ie (HPF)
'3 Gain of 0 dB at above stated frequencies, (See '2)
'4 Connection 01 a specified pin to GND allow 10. 20. 30. 40 and 50. External resistors allow a range of 1.61 ;;aQ;;a50

6-28

DATEL. Inc. 11 Cabot Boulevard. Mansfield. MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

FLJ-UR
TECHNICAL NOTES

1. Do not use a switching regulator but use a well regulated
±15V power supply. Install 0.01 J,LF bypass capacitors as
close to the filter as possible.
2. Use metal film resistors of 1% tolerance for fc setting.
When making a higher-order filter, use more accurate resistors.
3. Connect external resistors with short leads as close to the
filter as possible.

put signal and the output signal at pin 9 reaches at
180° looking at a phase measuring instrument such
as an oscilloscope.
• An input signal of frequency fc is given.
• Tune VR 2 until the phase difference between the input signal and the output signal at pin 20 set to 0°
FLJ-UR4LA1/2 Block Diagram (Fig. 3)

4. Use external capacitors with good stability and high dielectric resistance. It is recommended to use multilayer ceramic capacitors or plastic film capacitors.
5. Regulate output offset voltage by using an external trimmer
(10 kO to 50 kO).

6. The FLJ-UR series filters are packaged in single in line and
are compact in size. Installation at high-density may cause
temperature rises between elements. Installation with 0.8"
or more of space between filters can eliminate the problem.
7. Relation between fc and external resistor/capacitor
With the FLJ-UR series, a cutoff or center frequency can
be set by 2 or 4 external resistors. The values of R of 2 or 4
external resistors for normal use can be calculated as;
R -

15.9x10B

fc (Hz)

(0)

Suffix 1 model

(0)

Suffix 2 model

159x10 B

R=

fc (Hz)

Analog
input

GND +15V

~15V

FLJ-UR4HA1/2 Block Diagram (Fig. 4)

In the applications given later, the resistance of each of 2 or
4 resistors may be changed. R, to R. shown in the block
diagrams are the external resistors explained here. In the
standard use, the fc can be set to a minimum of 40 Hz. This
is because the values of R have to be increased to about
400K according to the relation between Rand fc. The fc
setting range can be expanded to lower band by adding 2
or 4 external capacitors.
R -

159x103
(Cext+0.01) fc

(0)

Suffix 1 model

R =

(Cext+0.001) fc (0)

Suffix 2 model

.

•~

where Cext is rneasured in J,LF and Fc in Hz.
In the applications in which the output offset, time drift, or
output noise must be minimal, use the above external
capacitors if the values of external resistors exceed 100 kO
each.

FLJ-UR4HB1/2 Block Diagram (Fig. 5)

8. How to tune fc
As shown in the specifications, the fc setting accuracy is
3% depending on the accuracy of elements used. There is
no practical problem in tuning when they are used as lowpass or highpass filters. However, bandpass filters and
band elimination filters may require sharp tuning. Such filters can be tuned with external trimmers as shown in
Fig. 10. R" R2 and VR, are not used with the FLJUR1BA1/2.
a. FLJ-UR1BA1/2
• An input signal of oscillating frequency fc is given.
• I/O signals are monitored with a phase measuring
instrurnent such as an oscilloscope.
• Tune VR2 until the phase difference between I/O
signals can be reduced to 0°.
b. FLJ-UR2BA 1/2
• An input frequency of 1.0734xfc is provided.
• Tune VR, until the phase difference between the in-

f'nalog
Input

GND +15V -15V

Cf in each figure is 10000 pF for suffix 1 model and 1000 pF
for suffix 2 model.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

6-29

'.

FLJ·UR
FU-UR2EAl/2 Block Diagram (Fig. 9)

FW-UR2LHl/2 Block Diagram (Fig. 6)

50

Analog

;.put

GND +15V -lSV

FU-UR1BA1/2 Block Diagram (Fig. 7)

fc tuning method (Fig. 10)

GND +l5V -15V

APPLICATIONS
This section illustrates configuration examples of filters with
various characteristics in which external resistors are changed
or 2 filters are used. Each application is provided with a circuit
diagram and a table of resistor values. The first example explains how to look up the table of resistor values in detail. This
can be applied to the others.
1. A 4-pole Bessel or Chebyshev filter (pass band ripple of 0.5
dB) modified from FLJ·UR4LA1/2
The circuit diagram is shown in Fig. 11.
FW-UR2BA1/2 Block Diagram (Fig. 8)
(Fig. 11)

Install external resistors with the resistance obtained
from Table 1 in the procedure given below. In (he standard application of FLJ·UR4LA1/2, the relation between
fc and R (external resistor) is:

Cf in each figure is 10000 pF for suffix 1 model and 1000 pF
for suffix 2 model.

R =

15.9x106
fc (Hz) (0); FLJ-UR4LA1

R =

159x106
fc (Hz)
(0); FLJ-UR4LA2

~u\jext

6·30

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

FLJ-UR
Obtain R that corresponds to the desired fc from the
above equation first. (In a standard application, the R
calculated here serves as R" R2, R3 or R4 shown in
Fig. 11.)

b. Setting of 0 at the range of 5<0<50
Connect pins as shown in Fig. 14. Obtain Rq from
the equation given below.

Based on the R calculated here, obtain external resistance R" R2, R3 and R4 referring to Table 1. For example, a Bessel lowpass filter has:
R,
R2
R3
R4

=
=
=
=

(Fig. 12)

0.673xR
0.712xR
0.384xR
1.014xR

Design Example
A Chebyshev lowpass filter (pass band ripple of 0.5 dB)
with Ie = 4 kHz using FLJ-UR4LA2
From R =
R=

159x106
fc (Hz)

-'....:c=-"....:...=_
r~VVV'-~ OUlpUI

159x106
4x103 =39.75kO

From Table 1,
R,=2.182R=2.182x39.75
R2=1.286R=1.286x39.75
R3=2.178R=2.178x39.75
R4=0.432R=0.432x39.75

kO=86.73
kO=51.12
kO=86.57
kO= 17.17

kO
kO
kO
kO

(Fig. 13)

4-pole lowpass filter resistance table (Table 1)
Bessel
0.673R
0.712R
0.384R
1.014R

R,
R2
R3
R4

Chebyshev (0.5 dB ripple)
2.182R
1.286R
2.178R
0.432R

GND +15V -15V

(Fig. 14)

4-pole highpass filter resistance table (Table 2)
Chebyshev (0.5 dB ripple)
0.726R
0.491 R
0.386R
2.757R

R,
R2
R3
R4

FUURIBAI.2

R,

GND'+15V -lSV

2. A 4-pole Chebyshev highpass filter modified from FLJUR4HA 1/2 (normal band ripple of 0.5 dB).
The circuit diagram is shown in Fig. 11.
Obtain external resistance R, to R4 from Table 2.
3. Application of FLJ-UR1 BA 1/2

0=5 band elimination filter
A band elimination filter can be made using an external
operational amplifier as shown in Fig. 12.
a. Cutoff frequency Ie is set by R. Adjust VR, to tune
the fc accurately.
b. Then, adjust VR2 to control volume of attenuation.
c. Fig. 12 shows 0=5. For 0=10 or 20, connect one of
pins 6 to 10 to ground.
How to set operational 0

4. How to change 0 of FLJ-UR2BA 1/2
The 0 of FLJ-UR2BA1/2 is set 5 at the time of shipment.
This can be changed from 5 to 10.
a. Connect pins as shown in Fig. 15.
b. Rq, R" R2, R3 and R4 are to be changed.
Calculations are:
Rq = 3.92 kO
Resistances for setting fc are:
R, = 1.0355R
R4 =0.95R3
R2=0.95R,
VR,~0.1 R,
R3=0.9657R
VR2~0.1 R2.

The FLJ-UR1BA1/2 pin connection allows selection of

0=5, 10,20,30, 40 or 50. For other than the above, set

o as follows: where the range of 0

(Fig. 15)

is 1.81 ~0~50

a. Setting of 0 at the range of 1.81 ~0<5
Connect pins as shown in Fig. 13. Obtain Rg from
the equation given below.
R
10(0-1)X103 (0)

q

=

5-0

GND +15V -j5V

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

6-31

FLJ·UR
R given here is the fc setting resistance in the standard.
use as mentioned above and obtained from the follow·
ing equation:

R = 159x10
fc (Hz)

Input

...GND!=tfr~g~~L
,
_____~~~_J

R = 15.9x106 (0)' FLJ-UR2BA1
fc (Hz)
,
6

(Fig. 16)

-15V

(0)' FLJ-UR2BA2
,

Unlike the FLJ·UR1 BA 1/2, FLJ·UR2BA 1/2 requires fine
adjustments.
c. Adjustment procedure
&-pole lowpass filter resistance table (Table 3)

1. Set the input signal frequency to 1.036xfc.
2. Adjust VR l to obtain a phase difference of 180° between the input signal and the output signal at pin 9.
3. Set the input signal frequency to fc.
4. Adjust VR2 to obtain a phase difference of 0° between the input signal and the output signal (pin 20).
5. A 2-pole Bessellowpass filter modifying FLJ-UR2LH1/2,
FLJ-UR2LH1/2 is a 2-pole Butterworth lowpass/highpass
simultaneous output filter. A 2·pole Bessellowpass filter is
implemented just by changing fc setting resistances Rl and
R2. The output is obtained at pin 20. Calculate Rl and R2
as shown below.

Bessel
0.4492R
0.8625R
0.6675R
0.5234R
0.4105R
0.6693R

Butterworth Chebyshev (0.1 dB)
0.7303R
1.6520R
1.3694R
2.2985R
0.9540R
2.9484R
1.0482R
0.4871R
1.4786R
3.3366R
0.6763R
0.2654R

(Fig. 17)
Input

Rl = 0.6408R
R2 = 0.9612R
6. A 6-pole lowpass/highpass filter example FLJ·UR2LH1/2,
FLJ-UR4LA1/2 and FLJ·UR4HA1/2 can be combined to
make 6·pole lowpass/highpass filters.
a. Lowpass filter
Fig. 16 shows the circuit diagram for the 6·pole lowpass
filter configuration. Table 3 is the external resistance
table. The combination of FLJ-UR2LH1 and FLJUR4LA1 or FLJ-UR2LH2 and FLJ·UR4LA2 depends on
the fc setting range.
Design Example
Example of 6·pole Butterworth lowpass filter with fc =
6kHz.Assume the desired cutoff frequency is 6 kHz. The combination of FLJ-UR2LH2 and FLJ-UR4LA2 should be
selected because of the fc desired.
According to the relation between fc and external resist·
ance R, external resistance values Rll to R24 are as
follows:
R = 159x66 = 265 kO
6x103
.
From the Butterworth resistance values in Table 3,
Rll=0.7303R=0.7303x26.5=19.35
R 12 =1.3694R=1.3694x26.5=36.29
R2l =0.9540R=0.9540x26.5=25.28
R22=1.0482R=1.0482x26.5=27.78
R23 =1.4786R=1.4786x26.5=39.18
R24=0.6763R=0.6763x26.5=17.92

kO
kO
kO
kO
kO
kO

b. Highpass filter
Fig. 17 shows the circuit diagram for a 6·pole highpass
filter configuration. Table 4 is the external resistance
table. External resistance values can be determined in
the same way as the 6·pole lowpass filter configuration.

6-pole highpass filter resistance table (Table 4)
Rll
R12
R2l
R22
R23
R24

Butterworth Chebyshev (0.1 dB)
0.732R
0.435R
1.366R
0.605R
1.215R
0.831 R
O.823R
0.838R
0.434R
0.356R
2.303R
3.172R

7. A 8-pole lowpass/highpass filter example
a. Fig. 18 shows the circuit diagram for a lowpass/high·
pass filter configuration. Two FLJ·UR4LA 1's or FLJUR4LA4's can be used in a lowpass filter configuration,
and two FLJ-UR4HA 1's or FLJ-UR4HA2's in a highpass
filter configuration. Table 5 gives the resistances for the
lowpass filter, and Table 6 for the highpass filter configuration.
b. A 8-pole Butterworth lowpass filter
Fig. 19 shows another example of 8·pole Butterworth
lowpass filter. Two FLJ-UR4LA 1's or FLJ-UR4LA2's are
used in the same manner as in Fig. 18. Same resist·
ances are employed for eight resistors (Rll to R24) but
Ra values are varied at 2 poles each internally. Four
more external resistors are used, but the advantage is
that the eight resistances are the same. R is obtained
from the equation given below.

R=

~
fc (Hz)

X

106 (0); FLJ·UR4LA1

_~
6·
R - fc (Hz) x 10 (0), FLJ-UR4LA2

6·32

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 0204S-1194ITEL (50S) 339-3000ITLX 1743SS/fAX (50S) 339-6356

FLJ·UR
(Fig. 18)

(Fig. 20)

Input

!=!:r.;=~~~J

+lSV
GNO

-15V

8-pole lowpass filter resistance table (Table 5)
R'1
R'2
R'3
R14
R21
R22
R23
R24

Bessel
0.525R
0.600R
0.233R
1.272R
0.671 R
0.389R
0.428R
0.486R

Butterworth Chebyshev (0.05 dB)
0.942R
2.520R
1.062R
2.232R
0.689R
1.842R
1.452R
0.653R
1.111 R
2.986R
0.900R
O.750R
1.962R
5.248R
0.501 R
O.173R

(Fig. 21) R shown here is 1.59 MO for FW-ACRl and 159 kO
for FW-ACR2.
FLJ·UR4LA1,2
7

a ,

8-pole highpass filter resistance table (Table 6)
Rll
R'2
R'3
R'4
R21
R22
R23
R24

Butterworth Chebyshev (0.05 dB)
1.416R
0.5619R
0.706R
O.3165R
0.915R
0.3762R
1.093R
2.2090R
1.111R
0.7039R
0.900R
0.6371 R
0.391 R
0.3287R
2.561 R
3.3520R

A %Rf.%

R%%% Ro/z%%

Ph%%

.,."::

FLJ·ACR1,2

(Fig. 22)
FLJ·URIBA1,2
7

(Fig. 19)

a ,

Input

GNO~~~~~~~============+=~~~~
i

+lSV
-ISV
Input

+ I5V
-ISV
GND

t=t~==t:~t1:J
Output

"%P!.%

"'Y,'Y.%,

"'X'Y.%

.'Y,%%

FLJ·ACR1,2

8. 72 dB/oct high rolloff lowpass filter
Fig. 20 shows an example of a Chebyshev lowpass filter
with high rolloff of 72 dB/oct achieved by combining FLJUR4LBl /2 and FW-UR4LA 1/2. Resistances R" to R24 are
as follows:
R"
R21
R22
R23
R24

(Fig. 23)
FLJ·UR4LA1,2
7

a ,

Input

GN°E==~tO

+15V

-lSV

= R'2 = R'3 = R'4 = R

= 1.801R
= 1.221R
= 1.797R
= 0.4788R

9. Example of a digital tuneable filter
The FLJ-ACR1/2 is provided as FLJ-UR series accessory.
FLJ-ACR 1/2 is composed of resistance networks and analog switches. Combined use of those instead of external
resistors provides a digital tuneable filter in which fc can be
set by digital (BCD) codes (See Fig. 21).

FLJ·ACR1,2

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

6-33

FLJ·UR
A model SUCh as FLJ-URIBAI 12 that requires two external
resistors is shown in Fig. 22. A model that requires 4 resistors
is shown in Fig. 21. In the examples shown in Figs. 21 and 22,
when all digitals are 0 (when no filter external resistor is installed), no filter function is expected. The wiring shown in Fig. 23
is also possible. See FLJ-ACR data sheets.

FU-UR2EA Frequency Response (Fig. 25)

~ -10~---r--~~_rHH~--_+--+-+-r+++~

ID
"0

~ -20r----r--~~_rHH~--_+--T_T_r+Tr~

FU-UR4LA, 4HA, 2LH Frequency Response (Fig. 24)
10

ID
"0
L.....J

III
III

-10

I
I

-g

...

II
-30

111111I

II
-7~01

.1

~

Normalized frequency f/fc

1\

/iLnmnl

[\

I

I

FU-UR4HB Frequency Response (Fig. 27)
III

Normalized frequency f/fc

100

10

w

FU·UR4LB Frequency Response (Fig. 26)

\

ID
"0

(EO,
-

ripple)

~

"-

\

(Enlarged ripJlle)

L

-50

/

t---

-3

I

-50
-60

FU·URI BA, 2BA Frequency Response Enlarged Diagram
(Fig. 29)

I

Normalized frequency f/fc

,'VI' ~~

-I

w

FU-URI BA, 2BA Frequency Response (Fig. 28)

-3

L'I -.L 1

"- -6

E

~ -7

-Ill

-20
FLJ-UR~:A

v

"E

-51l
-60

f/

Vv

.8

~

,

,

,

," 'tJ !"mill!-5
Norma 11 zed

6-34

-I 0

\;

lr
5. V'

.1

-9

I\\~

~

:.. -40
~

V

I

V

-8

~

J

/

~ -5

ID

'»

'/ i l hl ~\
1./ II I 1\

~ -4

10

"0

-3

Norma !lzed frequency f/fc

~ -2

~

-2
I \

-40

If

I

~

-I

1/

f-

-71l
.1

-30

/

.1

,f

~

-20

-2

-4

o

-60

1

-I

10

-g -30
; -40

-10

"E

-50r---~---r-r~_rHHH_--_+--+-+-r++T~

\

IIW-TI'

-60

E

I\F LJ -UR2LH

II

-50

-40r----r--r-rt-rHHi----t--t-t-rttt~

"-

- 7 0. TI----L--L-L--'--LLL..LfI------'---'--'--L.L.L-'-'T
10

II

"-

E

\

-20

.: -40
~

~

-30 r----r--~~_rHH-t---_+--T_T_r+++~

;

...

1! W!!

FLJ-UA2LH

w

w

-g

,

/

/

I

/

I

1
I
.9

J

~

\

\

URIBA

\"
,

y-

,-,

,"",

0-18 \

I

/

"

~ 'UR2B~~

j

\ 1\0-,.
10- ~

.\

\

\

~

1.1

,,
,

,
1.2

Normalized frequency f/fc

l""
~i'III

IIlIl

frequency f/fc

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

FLJ-UR
Higher Order Butterworth Lowpass Filter Frequency
Response (Fig. 30)

Higher Order Bessel Lowpass Filter Frequency Response
(Fig. 31)

10

10

o

0

-10

-10

I~

CD -20

"

;;;

j\

-30

~

\

w

~ -40

.,

I>.

8POle~ \

-70
-8~01

. I

Normalize

~I

Iillilll

frequency

10

f/fc

-70
Spoles

-8~01

100

-

-50

;;;

\

1.0

~

INII\
10

f/fc

100

.2

-3.

".,, -,a

I.IB

-

I\
\

-2.

w

l'l

B.IB

Q.

E

a:

!

frequency

6-pole Chebyshev Lowpass Filter Frequency Response
(Fig. 33)
Ripple 0.1 dB (The center shows the enlarged ripple.)

-I.

\

"D

-'0

!

Normal! ze

II

-20

w

4 poles

6 poles

I.

-10

.,,

2poles

E -60

10

"D

\

a:

6 poles

4-pole Chebyshev Lowpass Filter Frequency Response
(Fig. 32)
Ripple 0.5 dB (The center shows the enlarged ripple.)

-30

-30

I>.

~ -60

m

-20

•
".,, -,0
- -50

1\

::. -50

~

-5B

BIB

\

I::::::

-",12

1\

Q.

-60

E

a:

-70

-6B
-7B

-8~ ell

NormalIzed

IB

I

I

IB

frequency f/fc

-BB
.BI

.1

I

Normalized

8-pole Chebyshev Lowpass Filter Frequency Response
(Fig. 34)
Ripple 0.05 dB (The center shows the enlarged ripple.)

frequency

IB

IB

f/fc

Higher Order Butterworth Highpass Filter Frequency
Response (Fig. 35)

IB

10

-IB

-10

o

m

-2B

"

-3B

w

.,,

"D

-

-4B

m-20
\

.1
B .IB

j

I--

1

II
-5B

6 poles

Q.

8 poles

E -6B

a:

'11111

-70

-7B

.1

Norma 11 zed

I

l.\.

frequency

IB

f/fc

IB

-8~el

. I

Norma 11 zed

IIIII
I

frequency

10

f /fc

100

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

6-35

FLJ-UR
4-pole Chebyshev Highpass FiRer Frequency Response
(Fig. 36)
Ripple 0.5 dB (The center shows the enlarged ripple.)

6-pole Chebyshev Highpass Filter Frequency Response
(Fig. 31)
Ripple 0.1 dB (The center shows the enlarged ripple.)

'"
~

e;;

'0

~'0

'0

~'0



-ISV

21

2OP----o Output

Z2

+lSV

IZe'~dl

lOOK

III<

-lSV

AMPUTUDE VS. FREQUENCY (Fig. 4)
FW-VL (Fig. 4-1)

oL

-10

It° blv

r

-'0

1\

'\

FW-VH (Fig. 4-2)

I

rl~

rIll'

\

1\

Control V.

I
-10

~ -30

-30

1\

-40

1\

\

-50

1\

\

\

-60

II

j

1\

\

i

\

t

-60

'-

lOOK

1M

I

II

-40

-SO

l\_

10K
IK
F requency(Hz)

100

I

-,0

I

II

1

/

11000'<01

II
I

J

I

v.

•.

I

II

II

1

l,.~o~J

Iv

O.IV

O.OIV

.'.'.:
,

/

I

10K

lOOK

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

6-39

10

100
IK
Frequency(Hz)

FW-VB (Fig. 4-3)
0

M·IV
-I 0

-,0
-30
-4 0

-50
-60
-10

/

I

r~O.3V ",IV

Control V.

1

JIt-

tx'

\

3V

IOV

I 1\ / \ I \ I \ I 1\
I V \'1 V \1 \
/\ 1\ /\ \ \
tx'

/

\

/ / / \/ \! \ \
V /
V V \ V\ 1\ \
/
/ I\,
\.
5

100

2

IK
F requency(Hz)

5

10K

2

"'

\
'-...
5

lOOK

FLJ-VL, VH, VB
FW-Vl DISTORTION VS. fIfe (Fig. 5-1)

FU-VH DlSTOR11ON Vs. fIfe lFig. 5-2)

"...

Ir\.

/

\

jevrmslnput

.....

DISTORTION

,

I

"-

\

,

_

ii

/

f
0.2

0.1

I

0.03

f

O.S

0.2

0.1

,.....

/

-

V

~ ,1V Input

I

j

~l
2

~

/

tc: 2OFU-VIi

Vc : lOY

ii
O.S

,

CDfU-YB

-

' " 6Vrms Input

II
ii

vs. INPUT LEVEL (Fig. 6)

w%:

0.1

())

0.05
0.05

±1V IOjf
0:03

0.5

3

4

5 6 7

Inqut Level (Vrms)

0.2

0.1

0.3

0.5

fife

fife

NOISE VS. CONTROL VOLTAGE (Fig. 7)

...

(PVrma)

/

/1

...
FlHL

/

~/

I---

-- ~

~
---- --- ----- - ----

.00

0.01

'.02

'.05

0.'

,..

0.'

-y

--

VFU-V8

'/

,.-/

FU-'"

.0

Control Voltage(V)

6-40

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

FLT-U2
Microelectronic
Universal Active Filter

FEATURES
•
•
•
•
•
•

State variable filter
LP, BP, or HP functions
2-Pole response
Low-noise operational amplifiers
- 55°C to + 125°C Operation
Low cost

3 14

GENERAL DESCRIPTION

5 10

13 7

+ 15VDC

4

lOOk

The FLT-U2 is a universal active filter manufactured with thick-film hybrid technology. It uses the state variable active filter
principle to implement a second order
transfer function. Three committed operational amplifiers are used for the second
order function while a fourth uncommitted
operational amplifier can be used as a
gain stage, summing amplifier, buffer
amplifier, or to add another independent
real pole.
Two-pole lowpass, bandpass, and highpass output functions are available
simultaneously from three different outputs, and notch and all pass functions are
available by combining these outputs in
the uncommitted operational amplifier. To
realize higher order filters, several
FLT-U2's can be cascaded. Q range is
from 0.1 to 1,000 and resonant frequency
range is 0.001 Hz to 200 kHz. Frequency
stability is 0.01 %I"C and resonant frequency accuracy is within ± 5% of
calculated values. Frequency tuning is
done by two external reSistors and Q tuning by a third external resistor. For resonant frequencies below 50 Hz, two external tuning capacitors must be added. Exact tuning of the resonant frequency is
done by varying one of the resistors
around its calculated value.
The internal operational amplifiers in the
FLT-U2 have 3 MHz gain bandwidth products and a wideband input noise specification of only 10 nV/.jF1z. This results in considerably improved operation over most
other competitive active filters which
employ lower performance amplifiers. By
proper selection of external components
any of the popular filter types such as Butterworth, Bessel, Chebyshev, or Elliptic
may be designed. Applications include
audio, tone signalling, sonar, data acquisition, and feedback control systems.
Two models are available for operation
over the commercial, O°C to + 70°C, and
military, -55°C to + 125°C, temperature
ranges.

11

12
-1SVDC

MECHANICAL DIMENSIONS
INCHES (MM)
16 15 14 13 12 11 10

CONNECTIONS
DIAGRAM

9

1
~~;:::;-;::;-;:::----' 1
DATEL
FLT-U2

PIN
ONE
IDENT.

,.

OQ

15

.590114.91
HP OUT
V>

12345678

FLT-U2
(TOP VIEW)

LPOUT

I"

.19514.91
.900122, 91-1...l.

.05011,21

~tt_~.~:

_I

1-.l00TYP
12,51

11S,21

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

6-41

FLT-U2
FUNCTIONAL SPECIFICATIONS
Typical at 25°C,

±lSV supplies,

THEORY OF OPERATION

unless otherwise stated.

FILTER CHARACTERISTICS
Frequency Range" .............
Q Range' .....................
to Accuracy ....... . . . . . . . . . . ..
to Temperature Coefficient .......
Voltage Gain' ..................

0.001 Hz to 200 kHz
0.1 to 1.000
± 5%
0.01 %IOC
0.1 to 1.000

The FLT-U2 block diagram is shown in Figure 1. This is a second order state-variable filter using three operational amplifiers.
Lowpass, bandpass, and highpass transfer functions are
simultaneously produced at its three output terminals. These
three transfer functions are characterized by the following
second order equations:

K,

H(s) =

Input Offset Voltage ............
Input Bias Current ..............
Input Offset Current ............
Input Impedance ...............
Input Com. Mode Voltage Range ..
Input Voltage Noise, wideband ....
Output Voltage Range ...........
Output Current ................
Open Loop Voltage Gain .........
Common Mode Rejection Ratio ...
PowerSupplyRejection .........
Unity Gain Bandwidth ...........
Slew Rate .....................

o

0.5 mV typ., 6 mV max.
40 nA typ., 500 nA max.
5 nA typ., 200 nA max.
5 Megohms
± 12V min.
10 nV/y'Hz
± 10V min.
± 5 rnA min.
300,000
100 dB
10 p.VN
3 MHz
1 Vlp.sec.

POWER SUPPLY REQUIREMENTS

H(s) =

BANDPASS

K 3S2
S2+~S+w02

HIGHPASS

o

H(s) =

o

where K" K2, and K3 are arbitrary gain constants.
A second order system is characterized by the location of its
poles in the s-plane as shown in Figure 2. The natural radian frequency of this system is woo In Hertz this is fo = Wo .
The resonant radian frequency of the circuit is different from the
natural radian frequency and is:

w,

= Wo sin B = y'w02 _(1,2

The damping factor d determines the amount of peaking in the
filter frequency response and is defined as:

PHYSICAUENVIRONMENTAL
OOC to + 70°C
-55°C to + 125°C
-55°C to + 125°C
Ceramic 16-pin DIP
(double-spaced)

d = cos

o is found

from d and is a measure of the sharpness of the
resonance of the peaking:

0= J..

1. 100 ,; 5 x 10' optimally

2d

Also, 0 =

TECHNICAL NOTES
1. The FLT-U2 has simultaneous lowpass, bandpass, and
high pass output functions. The chosen output for a particular
function will be at unity gain based on Tables II and III. This
means that the other two unused outputs will be at other gain
levels. The gain of the lowpass output is always 10 dB higher
than the gain of the bandpass output and 20 dB higher than
the gain of the'highpass output.
2. When tuning the filter and checking it over its frequency
range, the outputs should be checked with a scope to make
sure there is no waveform clipping present, as this will affect
the operation of the filter. In particular the lowpass output
should be checked since its gain is the highest.
3. Check f" the center frequency for bandpass and the cutoff
frequency for lowpass or highpass, at the bandpass output.
Here the _peaking frequency can easily be determined for
high 0 filters and the 0 0 or 180 0 phase frequency can easily
be determined for low 0 filters (depending on whether inverting or noninverting).
4. Tuning resistors should be 1% metal film resistors with 100
ppm/oC temperature stability or better for best performance.
Likewise external tuning capacitors should be NPO ceramic
or other stable capacitor types.

B

The point at which the peaking becomes zero is called critical
damping and is d = ~/2 ..

FOOTNOTE:

6-42

K2S
S2+~S+w02

2 ...

Voltage, rated performance . . . . .. ± 15V dc
Voltage Range, operating. . . . . . .. ± 5V to ± 18V
Quiescent Current .............. 11.5 rnA max.

Operating Temperature Range
FLT-U2 .....................
FLT-U2M ....................
Storage Temperature Range .....
Case .......................

LOWPASS

S2+~S+w02

AMPLIFIER CHARACTERISTICS

fo

- 3 dB Bandwidth

= -'£ll..
2(1,

For high 0 filters the natural frequency and resonant frequency
are approximately equal.

w,

w, '" Wo or f,

'" fo

This is true since
= Wo sin B and sin
close to the jw axis in the s-plane.

B '" 1 as the poles move

For high Os (0 > 1) we therefore have for the second order
filter:
fo '" Bandpass center frequency
'" Lowpass corner frequency
'" Highpass corner frequency
In the simplified tuning procedure which follows, the tuning is accomplished by independently setting the natural frequency and
of the filter. This is done most simply by assuming unity gain
for the output of the desired filter function. Unity gain means a
gain of one ( ± ) at dc for lowpass, at center frequency for bandpass, and at high frequency (f> >fo) for highpass. Unity gain
does not apply to all outputs simultaneously but only to the
chosen output based on the component values given in the
tables. Figure 3 shows the relative gains of the three simultaneous outputs assuming the bandpass gain is set to unity.
Note that lowpass gain is always 10 dB higher than bandpass
gain and high pass gain is always 10 dB lower than bandpass
gain.

o

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

FLT-U2,
SIMPLIFIED TUNING PROCEDURE

OUTPUTS

BP

HP

c,

TABLE I

i

---I r-~

1. Select the desired transfer function (Ibwpass, bandpass, or
highpass) and inverted or non inverted output. From this
determine the filter configuration (inverting or noninverting)
using Table I.

LP

FILTER CONFIGURATION

INVERTING INPUT
NONINVERTING INPUT
2. Starting with the desired natural frequency and 0 (determined from the filter transfer function or s-plane diagram), compute foO, For foO> 104 the actual realized 0 will exceed the
calculated value. At foO = 104 the increase is about 1% and
at foO = lOs it is about 20%.

Figure 1.
FlT-U2 Block Diagram

3. Inverting Configuration. Using the value of 0 from Step 2
find Rl and R3 from Table II. R2 is open, or infinite.
TABLE II

+jw

d

INVERTING CONFIGURATION

Q

Rl

R2

LOWPASS

lOOK

OPEN

BANDPASS

OX 31.6K

OPEN

lOOK
--

HIGHPASS

10K

OPEN

-lOOK
--

f =

2~

",

6.640-1

LOWPASS

OPEN

BANDPASS

OPEN

100k

---

HIGHPASS

OPEN

31.6K
0

lOOK
0.3160-1

R3
lOOK
3.160-1

x-------

5 -

fo

107

where R4 and Rs are in ohms and fo is in Hertz. The natural
frequency varies as .Ji"i:;Rs and therefore one value may be
increased and the other decreased and the natural frequency will be constant if the geometric mean is constant. To
maintain constant bandwidth at the bandpass output while
varying center frequency, fix R4 and vary Rs.

-IW

I

-10

IHls)1
IdB)
-20

-30
-40
0.5

0.1

1.0

5.0

10.0

fo

RELATIVE FREQUENCY

Figure 3.
Relative Gains of Simultaneous Outputs, Q=l
R,

R,

= Rs = 5.03 X 1010

(C in pF)
foC
For unequal value capacitors this becomes:

~

.'

Lowpass

"0~---'----"':"

6. For 10<50 Hz the internal 1000 pF capacitors should be
shunted with external capacitors across pins 5 & 7 and 13 &
14. If equal value capacitors are used, ~ and Rs are then
computed from:
R4

-iw,

Figure 2.
S-Plane Diagram

lOOK
3.480-1

5. Using the value of fa from Step 2, set the natural frequency of
the filter by finding R4 and Rs from the equation:
4 -

~

3.480

R2
316K
0

R -' R _ 5.03 X

201

fo
- 3 dB Bandwidth

NONINVERTING CONFIGURATION
Rl

=
= cos 8
= J... =~
2d

R3
lOOK
3.800-1

4. Noninverting Configuration. Using the value of 0 from Step
2 find R2 and R3 from Table III. Rl is open, or infinite.
TABLE III

Relationships
Wo sin 8 = vw02-a12

Wt

OUT
IN C>-"'V\./V'II\r--i

= Rs = 5.03 X 1010 (C1C2 in pF)
fO.JC1C2

In both cases the capacitance is the sum of the external
values and the internal 1000 pF values.

.",.

G = , + ilL
R,
Figure 4,
R,
Uncommitted Op Amp Gain Configurations
G = - R,

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

6-43

FLT-U2
c,

SIMPLIFIED TUNING PROCEDURE, (Cont'd)
7. This procedure is based on unity gain output for the desired
function. For additional gain, the fourth uncommitted operational amplifier should be used as an inverting or noninverting
gain stage following the selected output. See Figure 4. A
third pole on the real axis of the s-plane may also be added to
the transfer function by adding a capaCitor to the gain stage
as shown in Figure 5.

R.

R,

POLE FREO

FILTER DESIGN EXAMPLES

I c'

= 2"~,C,

""'" POLE FREQ = 2;R,C,

Figure 5.
Using the Uncommitted Op Amp to Add;a Real Axis Pole

Bandpass Filter With 1 kHz Center Frequency Q = 10 and Inverted Output
1. From Table I the noninverting configuration is chosen to
realize an inverted bandpass output foQ = 104 which means
the realized Q will be about 1% higher than calculated.
2. From Table III, using Q = 10, we find:
R, = open
R2 = lOOK ohms
R3 = lOOK = lOOK
33.8
3.48 Q-l

R,

R,

R.

R4

BANDPASS
OUTPUT

R5

50.3K

50.3K

10

= 2.96K ohms

3. Using fa of 1 kHz, R4 and Rs are found from the equation:
R4

= Rs = 5.03 X 107 = 50.3K ohms
1000

4. This completes the filter design which is shown in Figure 6.
To choose the nearest 1% standard value resistors either
49.9K or 51.1 K ohms could be used; likewise one value of
49.9K and one of 51.1 K could be used giving the geometric
mean of 'l'R4RS = 'l'49.9K x 51.1 K = 50.5K which is even
closer. But due to the filter ± 5% frequency tolerance it may
be better to hold R4 constant while varying Rs to tune it
exactly.

Figure 6.
Bandpass Filter Example

+jw

Three-Pole Noninverting Butterworth Low Pass Filter With
dc Gain of 10 and Cutoff Frequency of 5 kHz.
The s-plane diagram of the 3-pole Butterworth filter is shown in
Figure 7. We will use a second order filter to realize the two complex conjugate poles and the uncommitted operational amplifier
to provide the third real axis pole and a dc gain of 10.
1. From Table I, the noninverting filter configuration would normally be used to give a non inverting low pass output. In this
case, however, we choose an inverting uncommitted op amp
with a gain of 10 and therefore we use the inverting configuration for the filter. By comparing the second order portion of the Butterworth function S2 + waS + w02 to the standard second order function S2 + waS + w02 we find Q = 1
foQ is then 5 x 103 so that Q will not exceed its specified
value.
2. From Table II, using Q = 1, we find:

+0

-jw

=~
3.80 Q-l

3. Using fa of 5 kHz,
R4

~

R,

4. For the uncommitted output amplifier, a gain of - lOis required. This defines R7/Rs = 10 and we arbitrarily choose Rs
= 2K, R7 = 20K ohms.

6-44

10.1K

13~

3~
R,
100K
IN

2

--A.J\/\/\r--

and Rs are found from the equation:
5000

K

(S+wo)(S' +WoS+Wo')

Ro

10.1K

= 35.7K ohms

= Rs = 5.03 X 107 = 10.lK ohms

=

Figure 7.
S-Plane Diagram of 3-Pole Butterworth Lowpass Filter

R, = lOOK ohms
R2 = open
R
3

H(s)

R,

f

35.7K '::'"

J.

9

FigureS.
Three Pole Butterworth Low Pass Filter Example

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

FLT-U2
FILTER DESIGN EXAMPLES, (Cont'd)

+jw

5. The final step is to realize the real axis pole of the Butterworth filter. This pole is at 5 kHz and is set by using capacitor
C3 across the feedback resistor R7:

C3

= ~1_ =
21rfR7

1
6.28 x 5 x 103 X 20

X

103

= 1590 pF

6. This completes the 3-pole Butterworth filter which is shown in
Figure 8.

d

cos 1>

==

~=

_ ,_ _ = 0.707
2x.707

2d
~-------

I
I

I
I

i

+jwt

Wo

0.707

==

0=

fj = 20kHz

! = _,,_ = 20kHz
o sin¢
0.707

= 28.3kHz

45°

-Ol:

+0

I
I
I

I

X - - - - - - - -'WI

Highpass Filter with Gain of - 1, 20 kHz Cutoff Frequency,
and Critical Damping
1. From Table I the inverting configuration must be used to
realize a highpass gain of - 1. An s-plane diagram of this
function is shown in Figure 9. Critical damping requires the
pole positions to be on a line 45° with respect to the real axis
and this results in no frequency peaking. The damping factor
dis:

-iw Figure 9.
. S-Plane Diagram of Highpass Filter with Critical Damping

= cos" = cos 45° = 0.707
Q = ~ = __
1_ = 0.707
d

and

2d

2(0.707)

Because this is a Iowa system the natural frequency will not
be the same as the highpass cutoff frequency fl. From Figure
9:
fo

= _f,_ = 20 kHz = 28.3 kHz

HIGHPASS OUTPUT

R,
1.78K

Ro
1.7BK

cos"

0.707
Then foa = 0.707 x 28.3 x 103 = 2 X 10' and the a will exceed its desired value by slightly over 1%.

10

2. From Table II, using Q = 0.707 we find:
R, = 10K ohms
R2 = open
R3

= ~ = 100K = 27.1K ohms
6.64 a-1

3.69

3. Using fo = 28.3 kHz, R. and Rs are found from the equation:
R4

= Rs = 5.03 X 107 = 1.78K ohms
28.3 x 103

Figure 10.
Highpass Filler Example

4. This completes the highpass filter design which is shown in
Figure 10. When using this filter, care should be exercised so
that clipping does not occur in the filter due to excessive input levels. If clipping occurs, the filter will not operate properly. Clipping will first occur at the lowpass output around fo
since its gain is 20 dB higher than the highpass output. The
signal level should be reduced so that clipping does not occur anywhere in the frequency range used. If higher signal
level is required, the highpass output should be amplified by
a gain stage using the uncommitted operational amplifier.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

6-45

FLT-U2
ADVANCED FILTERS

+jw

All of the common filter types can be realized by using cascaded
FLT-U2 stages. This includes multi-pole Butterworth, Bessel,
Chebyshev, and Elliptic types. The basic procedure is to implement each pole pair with a single FLT-U2 and cascade enough
units to realize all poles. A real axis pole is implemented by an
uncommitted operational amplifier stage. Each stage should be
separately tuned with an oscillator and scope and then the
stages connected together and checked. See Figure 11.
A notch filter can be constructed in several ways. The first way is
to use the FLT-U2 as an inverting bandpass filter and sum the
output of the filter with the input signal by means of the uncommitted operational amplifier. This produces a net subtraction at
the center frequency of the bandpass which produces a null at
the output of the amplifier. (See Figure 12.) Likewise lowpass
and highpass outputs (which are always in phase) can be subtracted from each other with an external operational amplifier.
The highpass output must have some gain added to it, however,
so that its gain is equal to that of the lowpass output. A third
method is to use two separate FLT-U2's, one as a two-pole
lowpass filter and the other as a two-pole highpass filter. Again
the outputs are subtracted in an operational amplifier. This
method permits independent tuning of the two sections to get
the best null response.

I""X ...
UNCOMMITTED
OPAMP

x'

I

~:'

___ x --''<---,I---t------_
+0
FLT·U2::2

C

IN
OUT

Figure 11.
Realization of a Complex Multipole Filter

R,

Further discussion of filter designs is beyond the scope of this
data sheet and the user is referred to the various texts on filter
design, some of which are listed below.

>--4-~OOUT

Estep, G.J., The State Variable Active Filter Configuration Handbook, 2nd Edition, Agoura, Ca., 1974.
Reference Data for Radio Engineers, Howard W. Sams & Co.
Inc., 5th Edition.

Christian, E., and Eisenmann, E., Filter Design Tables and
Graphs, McGraw-Hili Book Co., 1974.

R3
Figure 12.
Realization of Notch Filter

ORDERING INFORMATION
MODEL
FLT-U2
FLT-U2M

6-46

OPERATING
TEMP. RANGE
OOC to + 70°C
- 55°C to + 125°C

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

ROJ.20,1K
RESISTOR TUNEABLE
OSCILLATOR

PRODUCT DATA SHEET

......

FEATURES
• Oscillation frequency is set by two
external resistors.
• Ultra-low distortion ..• 0.0018% typical.
• Stable.
• Small hybrid package.

r ....

AUT

1
tI

Output 1

GENERAL DESCRIPTION
ROJ-20 and ROJ-1 K are resistor tuneable
osciliators whose oscillation frequency is set
with two external resistors.
Output frequency range of the ROJ-20 is
20Hz to 20KHz while that of the ROJ-1 K is
1KHz to 100KHz. Output distortion is as low
as 0.0018% typical at 1KHz frequency
range. Output voltage temperature coefficient is also as low as 50ppml"C.

1> Output

BLOCK DIAGRAM (Fig.1)

Hybrid construction has made it possible to
build highly stable oscillators in small size at
low cost.

,,,----------~ ~~.:'-------------:,,
,,
,,,
,
,,,
,,,
,,
,,
,
,

TECHNICAL NOTES
1. Typical connections are shown in
Figure 3. Do not connect unused pins
to any pOints. The external synchronization pin (Pin 1) is left open normally.
2. Output voltage level is 20Vp-p when
the pins 12 and 14 are connected,
2.5Vrms when these pins are disconnected.
Any output voltage level can be set
using external resistors RV1 and RV2
as shown Figure 4-a and 5-a.
The curves 4-b and 5-b show approximate values. The use of potentiometers

l

---......--rl

-ISV

--......-ft+1

R. n
I-----50KHz)

POWER REQUIREMENTS & ENVIRONMENT
Power Supply Voltage
Power Supply Current ....•...••
Operating Temperature Range ....
Storage Temperature Range ......
Relative Humidity

·
·
·
··

0.1% «50KHz)

Rext

15.9

fo (KHz)
159

Rext

fo (KHz)

LARGE CAPACInVE LOAD (Fig. 6)
(Technical Note 4)

(K h )
0

m

,--_R_O_J_-,ru11'-__R_O_J--'~--l,

(Kohm)

Pins 12 and 14 OPEN.
Pins 12 and 14 CONNECTED.

7

v

OUTPUT LEVEL ADJUSTMENT (Technical Note 2)
2.5Vnns or less

~

,.l.

PHASE DIFFERENCE BElWEEN SYNC INPUT AND OUTPUT
(Fig. 7)
(Technical Note 5)
180' rn:::----r.~-.--y----y---"'"T"1

(Vrms I

'5 150'1-+"'<---+\-.'

:>

1

~

/

8..5

O. 3

(Fig.4-a)

5K

SIlK 10OK(Q)

10K

(Fig.4-b)
2.5Vnns over

g
e~
£(1)

,/

i

00. 5

RV2

(Vrms )

~--~~~~---r---H

go' ~---r--""II;::---r---H

0" 60' 1+---+----+--\-'<-""""'___--+-1

$1

~.il

30' H---+---+-I,---\f-----"'rt-I

II

7

~

i'
(Fig.!;-a)

'"

RVUJ

fin: Sync Input Frequency
fo: Frequency when no Sync In is given.

I--

-......"

RV2=IOKa

DlSTORnON VS, FREQUENCY (Fig. 8)

""
"
1

I"-lK
(Fig.!;-b)

6-48

120·

10K
RVI

lOOK(a)

i~1 NI~
10

zo

so

100

2CID

ttl tl·-t-fi

50D

IK

2K

51(

10K

2CIK

50K

._

Frequency(Hz)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DATA ACQUISITION
SUBSYSTEMS

.:'

DATA ACQUISITION SUBSYSTEMS
MODEL
DAS-952R

RESOLUTION

8 Bits

CHANNELS

16 Single
Ended

THROUGHPUT RATE

17kHz

LINEARITY
(MAX)

GAIN
RANGE

TEMPERATURE
RANGE (OC)

INPUT RANGE

PACKAGE

±1/2 LSB

o to +5V

40-pin DIP
Monolithic

-25 to +85

7-3

62-pin
Hybrid

o to +70
-55 to +125

7-9

62-pin
Hybrid

to +70
-55 to +125

7-9

Module

oto +70

7-17

PAGE

12 Bits

8 Diff.

50 kHz

±3/4 LSB

1 to 200

o to +50 mV
o to +10V
±50 mV to ±1 OV

12 Bits

16 Single
Ended

50 kHz

±3/4 LSB

1 to 200

to +50 mV
to +10V
±50 mV to ±10V

MDAS-8D

12 Bits

8 Diff.

50 kHz

±1 LSB

to +5V
to +10V
±2.5V, ±5V, ±10V

MDAS-16

12 Bits

16 Single
Ended

50 kHz

±1 LSB

to +5V
o to +10V
±2.5V, ±5V, ±10V

Module

oto +70

7-17

MDAS-940D

12 Bits

8 Diff.

33 kHz

±1/2 LSB

oto +5V
oto +10V

Module

oto +70

7-23

Module

oto +70

7-23

HDAS-SMC
HDAS-SMM
HDAS-16MC
HDAS-16MM

o
o

o
o

o

1,2,4,8

±5V, ±10V
MDAS-940S

12 Bits

16 Single
Ended

33 kHz

±1/2 LSB

1,2,4,8

oto +5V
oto +10V
±5V, ±10V

o

Output logic for all devices is three-state TTL.

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

7-1

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DAS·952R
16 Channel, a·Bit Monolithic
Data Acquisition System

FEATURES
•
•
•
•
•
•

16 Single-ended channels
8-Bit resolution
Monolithic CMOS construction
Three-state outputs
Ratiometric operation
low cost

MUX AID

+Vs

OUT

IN

-REF
IN

+REF

IN

GND

31 BIT 1 (MSB)
CH 239
CH 340

GENERAL DESCRIPTION

CH -4 1

CH 5

The DAS-952R is a single-chip, 16channel, 8-bit data acquisition system.
Using monolithic CMOS technology, this
single DIP product includes a 16-channel
multiplexer, an 8-bit successive approximation AID converter, and microprocessor-compatible control logic.
The design of this system emphasizes
high accuracy, excellent repeatability, low
power consumption, and a minimum of adjustments (no full scale or zero adjustment
required). latched and decoded address
inputs and latched TTL three-state outputs
allow easy interfacing to microprocessors.
The input multiplexer allows random access to anyone of 16 single-ended analog
input channels and provides necessary
logic for additional channel expansion.
Connection of the multiplexer output to the
converter input is by external pin connection. This permits easy signal conditioning
such as amplification, linearization, or the
use of a sample and hold.
The 8-bit AID converter uses a 256R ladder network, successive approximation
register, and a chopper-stabilized comparator to implement the successive approximation conversion technique with a
switching tree. Using a 256R ladder network ensures monotonicity while the
chopper-stabilizer comparator makes the
converter highly resistant to thermal effects and long term drift. In ratiometric
conversion, the converter expresses the
analog value being measured as a percentage of reference input. Full-scale range
may be selected within limits, to adjust the
sensitivity of the converter to the desired
application or to refer the output to a
secondary standard.
Accuracy, speed, flexibility, excellent performance over a wide temperature range
( - 25°C to + 85 0c) and low cost make the
DAS-952R an easy and practical answer
to many data acquisition needs.

;?

CH 6 3
CH~ 7 4

16 CHANNEL
ANALOG
MULTIPLEXER

CH 8 5

CH 9 6
CH 10

THAEe-STATE
8 BIT AID
CONVERTER

OUTPUT
LATCHES

7

CH 11 8
CH 13 10
CH 1411

CH 15 12

CH 16 14

CA 1 3
CA 2 35
CHANNEL
ADDAESS

CA 4 34

CAS 13

CONTROL

ADDRESS ENABLE _32
EXPANSION CONTROL

,,":.r--L----..J

,
STAAT
EOC CLOCK
CONVERT
IN

MECHANICAL DIMENSIONS
(INCHES (MM)

INPUT/OUTPUT
CONNECTIONS
P'N

--r·

)

(

D:!!~52R

?1'~~

3

20

----l ~ ~3~~f

~~=ft020
L
!

0.075
(1,9)

_-1 L 0.100
I I t~~.

-- ...ll..- 0.018

II

(0,5)

0.125

~i~~

(0,5)

MIN.

FUNCTION

P'N
21

OUTPUT ENABLE

CH 51N

22

CLOCK INPUT

23
24

BIT 8 OUT (LSB)

CH SIN

-REF. IN

,

CH 81N
CH 91N

2'
2ll

7

CH 10 IN

27

BIT 5 OUT

CH 111N

28

BIT 4 OUT

CH 121N

29
30

BIT 3 OUT

PIN NO.1 INDENT

0.050 (1.3) TYP.

FUNCTION
CH 41N

CH 71N

~=rn=====m==~~
1

OUTPUT
ENABLE

10

CH 131N

11

CH 141N

12

CH 151N

13
14

E.D.C.

15
16
17

18

"

20

31
32

BIT 7 OUT
BIT 6 OUT

BIT 2 OUT
BIT 1 OUT (MSB)
ADDRESS ENABLE

CH lSIN

"

CA 8 INPUT

34

CA 4 INPUT

MUlTJPlEXER OUTPUT

35

CA 2 INPUT

START CONVERT

36

CA 1 INPUT

+Vs

37

EXPANSION CONTROL

AlO IN

CH 1 INPUT

+REF.IN

38
3.

GROUND

40

CH 3 INPUT

CH 2 INPUT

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

7-3

DAS-9S2R
ABSOLUTE MAXIMUM RATINGS
Voltage at Any Pin
(Except Digital and REF inputs) ....
Voltage at Digital Inputs .........
+V•.........................
+REF ..................•.....

PHYSICAL/ENVIRONMENTAL
-0.3V to Vs +0.3V
- 0.3V to + 15V
+6.5V
Vs +O.IV

Operating Temperature Range .... -25'C to +85°C
Storage Temperature Range ...... - 65°C to + 150'C
Package ...................... 40 Pin Plastic DIP
FOOTNOTES:
1. Logic is provided for expanding the number of channels externally.

FUNCTIONAL SPECIFICATIONS

= + VREF ,

Typical at 25°C, + VSUPPLY
kHz unless otherwise noted.

-

VREF

= GND, clock = 640

2. Channel ON-resistances matched to within 75!l maximum difference
between any two channels.
3. Measured from + REF input to - REF input.
4. This is the comparator input current, a bias current into or out of the
. chopper stabilized comparator. It varies directly with clock frequency
and is, relatively independent of temperature.

ANALOG INPUTS

5. Total unadjusted error is the sum of linearity, zero, and full-scale errors

Number of Channels ............
In~ut Voltage Range ............
CannelON-Resistance .........
Channel ON-Resistance, 8SoC ....
Channel OFF Leakage Current,
VIN
+ SV ..................
Channel OFF Leakage Current,
VIN OV ....................
Channeillut Capacitance .......
REF Input esistance ...........
REF Input Voltage ..............
AID Converter Input Curren14 .....

=
=

16 Single Ended'
0 to + 5.25V max.
1.5KO typ., 3KO max. 2
6KO max.

at any point on the transfer function.

6. V, = +REF = +5V ±0.25V.
7. For clock frequency of 640 kHz. See technical note 4.

10 nA typ., 200 nA max.
.,-10 nA typ., -200 nA min.
5 pF type., 7.5 pF max.
1KO min., 4.5KO typ.3
+0.512V to +5.25V3
±0.5 pA

DIGITAL INPUTS
Logic high (" I") Threshold, min ...
Logic low ("0") Threshold, max. ..
Input Current, Max. high or low. . ..
Input Capacitance ..............
Clock Frequency ...............

Vs - 1.5V
+ 1.5V
1.0 pA
7.5 pF max.
10kHz min., 1.2 MHz max.

DIGITAL OUTPUTS
Logic high ("I") OUT,
lOUT
+360pA .....•........
Logic low ("0") OUT,
I~ln
-1.6 mA . . . . . . . . . . . . ..
EO
ogic low OUT,
lOUT
-1.2mA ..............
3-State Output Current,
VOUT = +SV .................
3-State Output Current,
VOUT OV ...................
3-State Output Capacitance . . . . ..
Output Coding .................

=
=
=

=

Vs -O.4V min.
+ 0.45V max.
+0.45V max.
+3 pA max.

-3 pA max.
10 pF
Straight Binary, Positive True

CONVERTER PERFORMANCE
Resolution ....................
Linearity Error .................
Zero Error .....................
Full Scale Error ................
Total Unadjusted Error ..........
Power Supply Rejection .........

8 Bits
±% LSB, max.
±% LSB, max.
±% LSB, max .
± % LSB, max?
±0.15%/V max?

DYNAMIC PERFORMANCE
Conversion Time ............... 100 J'Sec. typ., 116 "sec. max.?
MUX Delay, from ADDRESS
ENABLE .................... 1 "sec. typ., 2.5 J'Sec. max.
3-State Tum-ON Delay .......... 250 nsec. max.
POWER REQUIREMENTS

TECHNICAL NOTES
1. The analog input voltage is expressed as a percentage of fullscale voltage range. Full-scale voltage range may be varied
from + 0.512V to + 5.25V. The system uses an 8-bit converter with the full-scale range divided into 256 steps (one
step = 1 LSB). The ability to select the full-scale range by
means of the reference voltage allows selection of the size of
the LSB, thereby allowing selection of the converter's sensitivity. The center of the full-scale voltage range must be
held within ± 0.1 V of the center of the supply range because
the analog switch tree changes from N-channel switches to
P-channel switches at this point. Failure to maintain the symmetry of these ranges may result in erratic switch operation.
This condition is automatically satisfied in configurations
where + REF = + Vs and - REF = GND. For configurations
where + REF < + V s, - REF must be greater than GND by
an equal amount. + REF can never exceed + Vs and - REF
can never be less than GND.
2. The system requires less than 1 rnA of supply current. For applications where full scale range is selected between + 4. 75V
and + 5.25V, the reference can be used to generate the
supply.
3. To preserve the accuracy of the system over its full operating
temperature range, the reference source should have a temperature coefficient of 20 ppm/oC or less. For ambient temperature changes less than 75°C, a reference temperature
coefficient of 30 ppm/oC is sufficient to maintain accuracy.

4. Conversion time and throughput rate for the DAS-952R is
Supply Voltage, rated performance + 5V ± 0.25V
Supply Voltage, operating range .. + 4.5V to + 6V
Supply Current ................. 300 pA typ., 3.0 rnA max.

7-4

dependent on external clock frequency. The clock may be
varied from 10kHz to 1.2 MHz (see comparator input current
graph).

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DAS-952R
TYPICAL PERFORMANCE

DESCRIPTION OF OPERATION
Anyone of 16 single-ended analog inputs may be selected by
using the address decoder. The multiplexer input selection table
shows the channel address input states required to select each
channel. Channel address input states are latched into the address decoder on the low-to-high transition of the ADDRESS
ENABLE input. Channel address inputs are required to be
stable for 50 nanoseconds before and after the ADDRESS
ENABLE low-to-high transition. Additional channel expansion is
accomplished by disabling the internal multiplexer (all channels
are off when EXPANSION CONTROL input is low) and connecting the additional signals directly to the converter input.

MULTIPLEXER ON RESISTANCE

The converter input may also be used to introduce various
signal conditioning devices into the analog signal path. The
analog signal at the multiplexer input selected is available to the
comparator after a maximum delay time of 2.5 microseconds.
The converter's successive approximation register is reset on
the positive going edge of 200 nanoseconds start conversion
pulse, and conversion is initiated on the falling edge of the
pulse.
1.25

A conversion in progress may be interrupted by a new start conversion pulse. The EOC output goes low in 1 to a clock periods
after the riSing edge of the start conversion pulse. For continuous conversions the EOC output can be tied to the start conversion input and an initial external start conversion pulse applied after power up.

2.5

3.75

INPUT VOLTAGE (V)

COMPARATOR INPUT CURRENT

The a-bit AID converter requires 64 clock periods to resolve the
analog signal voltage level. The converter employs a chopperstabilized comparator for extreme resistance to input offset drift
errors. The 256R ladder network ensures monotonicity and
does not cause load variations on the reference voltage. The
values of the top and bottom resistors are different from the rest
of the ladder so that the first output transition occurs when the
analog voltage level reaches + % LSB and each succeeding
output transition occurs at intervals of 1 LSB up to full scale.

1.5

.:

0.5

The a-bit, straight binary, positive true result appears at the
three-state output latches, which are enabled when the OUTPUT ENABLE control is high.

- 0.5

1---:;;o:;.,e:.+--P'-----+-----1I----j

-1.5 1<...._ _- ' -_ _--'-_ _---'_ _----'

2.5

1.25

3.75

COMPARATOR INPUT
VOLTAGE (V)

RATIOMETRIC CONVERSION
SYSTEM

CHANNEL ADDRESS TABLE
CHANNEL ADDRESS INPUT
8
4
2
1
X
X
X
X
a
0
a
0

a
a
a
a
a
a
a
1
1
1
1
1
1
1
1

a
a
a
1
1
1
1

a
a
a
a
1
1
1
1

a
1
1

a
a
1
1

a
a
1
1

a
a
1
1

1

a
1
a
1
a
1
a
1
a
1
a
1
a
1

INHIBIT
CONTROL

a

I

1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

ON
CHANNEL
NONE
1

2
3

4
5
6

RATlOMETRtC
TRANSDUCER

\

+ 5V de

r----+--+---c>---j Vs
+REF
MSB

#1

~-r--+---~~CHl

BIT 1

7

8
9
10
11
12
13
14
15
16

OUTPUT
DATA

DAS·952R

1----0---1

CH 16

t

LSB

BIT 8

-REF

' - - - -......--+-----c>---j

GND

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

7-5

DAS-9S2R
TIMING DIAGRAM
CLOCK
INPUT

1-

1 CLOCK

IPERIOD

START
CONVERSION

J
"1
CONVERSION
INITIATED

ADDRESS
ENABLE

CHANNEL
ADDRESS
INPUT

MUX

INPUT
STABLE

------~-----------------

MUX OUTPUT SETILED
TO WITHIN V2 lS8 OF INPUT
MUX

OUTPUT

OUTPUT
ENABLE

EOC

EOC DELAY, 1-8 CLOCK
PERIODS

1.OUTPUT
DATA

CONVERSION TIME, 64 CLOCK PERIODS

_ _ _ _ _ _ _ _ _ _ aUTPUT QFF STATE

DATA ACQUISITION SYSTEM WITH. SAMPLE-HOLD
+ 15V de
24K

For applications where a sample-hold is required,
connections are made as shown in the accompanying diagram. The sample-hold may be put in the
sample mode after the multiplexer output settles (see
timing diagram). The start conversion input can be
taken high as shown in the timing diagram but should
not be taken low until the sa[Tlple-hold has acquired
the input voltage. The acquisition time of the samplehold is dependent on the value of the hold
capacitance. This value must be selected for the
acquisition time and hold-mode voltage droop
required by the converter speed and accuracy,
respectively. Optimal values of holq, capacitance
may be selected after throughput rate is determined.
See SHM-LM-2 data sheet.

lK

CH liN

ANALOG
INPUTS

j

MSB

BIT 1

f

OUTPUT
OATA

CH 161

DA&952R
BIT8
LSB

5K

l%MF
CA 1

I--_--..-A""~_ + 15V de

CHANNEL
ADDRESS {
INPUTS

CA.

7-6

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DAS-9S2R
APPLICATIONS
DIFFERENTIAL INPUT CONNECTION

EXPANSION TO 6'

CHANNEL~".I

CH'

:,

DIFFERENTIAL INPUT
CONNECTION
CH 16

ADDRESS

DAS 952R

ENABLE

ADDRESS ENABLE
START CONVERSION
START
CONVERT

CA>
CA2
CA<
CA'

COMPARATOR

'N

EXPANSION

MX-1606

CONTROL

MUX
OU,

cn
CA 8 MUX
OUTPUT

~~~~~~~
INPUTS

"""j

GAIN SELECT
~'NPUTS

!

CA 1
16 CHANNEL, DIFFERENTIAL
INPUT DATA ACQUISITION
SYSTEM WITH PROGRAMMABLE

ADDRESS
CHANNEe

GAIN.

INPUTS

MUX
OU,

CH32

1~:; ~~~~~~iai~~~
CA4

CA 8

o-C--+-H

MX·1606

CA ,
CA2
CA<
CA'

o--=C'-'A-'4-+++....
CA16

COMPARATOR
INPUT

10F4

CH3J

DECOOER

ANAWGj
INPUTS

MSB)

MUX
OU,

,
CH4I!

OUTPUT
DATA

OAS-952R

LSB

I

MXl606

CA ,
CA2
CA<
CA'
INHIBIT

CH"

ANALOG
INPUTS

MUX
OU'

CH54

CA ,
CA2
CA<
CA'

32 CHANNEL, 35 kHz DATA ACQUISITION SYSTEM

~
~
~
,,
,,
,

II

MUX COMPARATOR

OUT

~N

~

IN

DA8-952R

LSB

CA 1
CA 2
CA 4

CA'

~

o---++-H

~::~

OUTPUTf6
ENABLE
ADDRESS START CLOCK
ENABLE CONV. IN E.O.C.

CA 1 C>--

MSB

·CAoo---+-+~t-----+--+-~-i--~

~'1

E.O.C.o---+-+~t-----+--+-~~

OUTPUT
DATA

CLOCK INPUT o---+-+~t-----+--+--1 START CONVERSION o---+-+~t-----+----1
ADDRESS ENABLE

H---H--t-t-t--t---<> 1

E.O.C.
CA 1

ADDRESS START CLOCK
CONV. IN

'--I-+~~g.""~!-lENABlE
~
*CA 0 IS NOT APPLIED UNTIL E.O.C. GOES HIGH
O\T THE END OF THE CONVERSION CYCLE.

~

~

~
,

DAS·952R

,,
I

~
LSB
MUX
OUT

COMPATOR
IN

LJ
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

7-7

DAS-9S2R
REFERENCE AND SUPPLY CIRCUITS
30 PPM/oC REFERENCE AND SUPPLY

DUAL ADJUSTABLE REFERENCE

+15V de
+15V de
5K

1%MF
5K
1%MF

I

2mA

Vs

+---......-+--<>--j+ REF
CH 1
CH 2

i

CH 1

,

CH 2

I

DA8-952R

I

:

CH 15

1

I

DAS-OS2R

OUTPUT

DATA

I

CH 16

CH 15

I>~--<>--l-REF

CH 16

GND

-REF
GND

ADJUSTABLE REFERENCE AND SUPPLY

TYPICAL MICROPROCESSOR INTERFACE

EocH~---

6.6K

r--~r""'~-- + 15V de
1.33K

1000pF
MSB

5K

Vs
+ REF
CH 1

IN4571
15K

CH 2

OAS-952A

OUTPUT
DATA

LSB

eM 15
CH 16
GND

-REF
GND

+s.ooov

o.ooov

ORDERING INFORMATION

7-8

MODEL

DESCRIPTION

DOS-952R

16 Channel, a-Bit Monolithic
Data Acquisition System

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

HDAS·16, HDAS·8
12·81t Microelectronic
Data Acquisition Systems
FEATURES
•
•
•
•
•

Miniature 62-pln hermetic package
12-Blt resolution, 50 KHz
Full-scale gain range of 50 ~ to 10V
Three-state outputs
16 Channels single-ended or
8 channels differential
• Auto-sequencing channel addressing
• MIL-STD-883 versions

GENERAL DESCRIPTION

i g
~ ~
Ii? Ii?

;)

§

~~ cia

in

~~ii

19

4OlB3631

%

< <
~ :t

~o

CHOHIICHO
CHI HIICHI

CH2HlleH2

2

eH3HlleH)

J5BIT 1 }MSBI

1

J481T2

eH"HIICH4 62

33enl

«

eH5HlieHS 61

,,~....r~ 1281T4

~

Using thin-and thick-film hybrid technology.
DATEL offers complete low-cost data acquisition systems with superior performance
and reliability.
The HDAS-8 (with 8 differential input channels). and the HDAS-16 (with 16 singleended input channels). are complete high
performance 12-bit data acquisition systems
in 62-pin packages. Each HDAS may
expand to 32 single-ended or 16 or more
differential channels by adding external
multiplexers.
Combined acquisition and AID conversion
time is 20 microseconds maximum. giving
a minimum throughput rate of 50 KHz. The
12-bit binary data may be transferred out in
three 4-bit bytes using the three-state data
bus drivers. Output coding is straight binary
in unipolar operation. and offset binary in
bipolar operation.

Jlail'·4' ....

Lr--I-';;JOBIT5}~8

CH7HI/CH159

2981T6

3~

2881T]

~=>

CH)LO/CHll 56

26mt&-81

w

C!-tHO/CHI25oi
CHSLOICH1)SJ
eH6 LOICHI. 52

258IT9}. ~
24 SIT '0
....
2J BIT 11

CHOLO/CHI 58

CH!LOICH9 51

,,~....r~ ~lBITB

CH2LOICHTOS6

CH7l0lCH15 51

~~

~--'1Bl~~f~~~i~~n----L~-...JH~...Je---<> 228tT
ai 12 Il~8)
21

19-121

L------~7fiX

pl~llr

12 11 10 9

:( ~

;

~

MUX

ADDRESS OUT

1-"

13

20

:5>IIO.~:'
~ a:: a:: II: a::

I~

6
~

a::

8

19 16 15
~

MUX
ADDRESS IN

41

44 42

o&J'"

~

~8

88~

~

~

11

.* If. ~~§
z

z

HDAS-16/HDAS-8 Simplified Block Diagram

MECHANICAL DIMENSIONS - INCHES (MM)
1--_ _ _ _----'2~~~,AJ("'------I
sealing 0.035
plane

II

20 SPACES
- - - - A T O . l 0 0 (2.5f EACH----i·

~ 0 150

(3:8101

. ---0.1581

Internal channel address sequencing is
automatic after each conversion. or the user
may supply external channel addresses.
The internal instrumentation amplifiers are
supplied with a gain of 1 and a 10 volt fullscale range. An external resistor may be
added to achieve gains of up to 200. corresponding to a 50 mV full-scale input range.
This key feature is useful in low-level signal
applications involving bridge amplifiers.
transducers. strain gauge and thermocouple interfaces.

a
a

g

. " .. .
CH6HIiCH6 110

Internal HDAS circuitry includes:
• Analog signal multiplexer
• Resistor programmable gain instrumentation amplifier
• A sample-and-hold circuit. complete with
MOS hold capacitor
• a 10 volt buffered reference
• A 12-bit AID converter with three-state
outputs and control logic.
All that is required to power the HDAS
devices are external +5V and ±15V dc
supplies.

i

a
a

, .. ---- .. -----------~
~--

_'3,8'0'

I(~:~I
9 SPACES
ATO.l00EA
'2,5)

BOTTOM VIEW

J~

1.400 (35,6) ..-lAX
PIN SPACING fS 0. 100

62:
DOT ON TOP

REF~~~~CES

•

_ .. - .............. - ............ - - - -

..-.1-'--'_ _ _ _ _ _ _ _ _ _ _ _21-J

--1,250

~NuC~JlSA~~~~%~)
MAXIMUM PIN DIMENSIONS

~R3E xooo~~~~ 022 INCHES

The HDAS devices are cased in a 62-pin
hermetic package measuring 1.4" W x
2.3" L x 0.23" H. Models are available in
two temperature ranges: 0 OC to +70 "C and
-55°C to +125 °C.
DATEL.lnc. 11 Cabot Boulevard. Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

7-9

HDAS·16,HDAs·a
ABSOWTE MAXIMUM RATINGS
Parameters
+15V Supply (Pin 43) ..........•
-15V Supply (Pin 44) ..........•
+5V Supply (Pin 18) ............
Analog Inputs •................
(Note 1)
Dlgltallnputs ..................
Thermal Resistance
Junction-Case ...............
Case-Ambient
Junction-Ambient .••.........
Power Dissipation •.............
Laad Temp. (10 Sec.) ..•....•..•.

PERFORMANCE (cont.)
Min.
-0.5
+0.5
-0.5
-35

Max.
+18
-18
+7
+35

-0.5

+7
13
17
30
1.75
300

...............

Units
Volts de
Volts de
Volts de
Volts
Volts
OClWatt
OClWatt
OClWatt
Watts
OC

The following specifications apply over the operating temperature range and power supply range unless otherwise indicated.
ANALOG INPUTS

MIN.

=

Input Gain Equation
(Note 2)
Gain Equation Error

..............
..............

Instrumentation Amp.
Input Impedance •...•..•.......

TYP.

MAX.

UNITS

0
0

-

+10 Volts
+50 mV

-10
-50

-

+10 Volts
+50 mV

= 1 ± (20K Ohm/RGAIN)

Gain

-

-

10·

1012

±0.1 %

-

Ohms

Input Bias Current:
±250 pA
O·C to + 70·C ...............•
-55·Cto +125·C •.•......... Doubles every 1O·C above 70·C
Input Offset Current:
O·C to + 70·C •.....••.......
±1 nA
-55·Cto +125·C .......•...• Doubles every 10·C above 70·C

-

Multiplexer
Channel ON Reslatance •..•.••..•
Channel OFF Input
Leakage ••..•.•..••...........
Channel OFF Output
Leakage •........••....•..••.•
Channel ON Leakage ....•......
Input Capacltsnce
HDAS-16, Channel On ...........
HDAS-6, Channel On •..•....••.•
+ 25 ·C, Channel Off •.•..•..••.•
Input Offset Voltege
Gain = 1 to 200, +25·C ...........
-55·Cto +125·C .....•...

<

-

-

-

30

-

pA

--

1.0
100

--

nA
pA

-

100

--

50
5

±11

-

CMRR, Gain = I, at 60 Hz ..•...•.••

-70

-82

Input Voltage Noise (Referred
to Input)
Galn=I •...•.••.••.•..••.••.•
Channal Croaatalk ••.••.•••••.••.•

-80

150

Resolution •••.••.•.•.•••..••....

12

-

Integral
Nonlinearity:
+25·C ...•.•.•..••.•..•.....•
0°Ct070°C ....................
_55°C to +125°C

--

--

-

UNITS

±% LSB
±1 LSB
±1 LSB
±2 ppm/DC

Unipolar Zero Error
+ 25·C (Note 3) .•..............
-55·Cto +125·C .............•
Unipolar Zero Tempco •...........
Bipolar Zero Error
±25°C(Note3) ................
_55°C to +125·C ..............
Bipolar Zero Tempco
Bipolar Offset Error
+25°C(Note3) ................
- 55°C to + 125·C ..............
Bipolar Offset Tempco ......•....•
Gain Error
+ 25·C (Note 3) ................
-55°Cto +125·C ..............
Gain Error Tempco ...............

±0.1 %FSR
±0.3 %FSR
±20 ppm/DC
+0.1 %FSR
±O.3 %FSR
±35 ppm/DC
0.1 %FSR
0.3 oAlFSR
±35 ppm/DC
±0.2 %FSR
±0.3 'AlFSR
±30 ppm/·C

No Missing Codes •....•.......... Over the operating temperature range
DYNAMIC CHARACTERISTICS
Acquisition Time,
At Gain = I, +25°C ..•.•.••.•...•
-55·Cto +125·C ..•....•.....•
At Gain = 10, +25°C .•...•.•.•..•
At Gain = 50, +25°C ............ .
At Gain 200, +25°C .......... ..
Aperture Delay Time •.••.•.•..•...
Aperture Uncertainty ............ .
S/H Droop Rate ................. .
Feedthrough Accuracy ••.•.•.•....

9
9
16
60
100

=

AID Conversion Time:
+25·C ..•.•..•..•.•.•.•.•.•..
-55°C to +125°C ...•.•.•......
Throughput Rate
+25·C ...................... .
-55°C to +125°C .•.•.•..•.•.•.

9

50
33

55

10 j.tSec.
15 j.tSec.
j.tSec.
j.tSec.
j.tSec.
500 nSec.
1 nSec.
800 mV/Sec.
±0.01 %
10 j.tSec.
15 j.tSee.
KHz
KHz

DIGITAL INPUTS

-

-

pF
pF
pF

-

Volts
dB

200 j.tV RMS
dB

Logic Levels:
(Pins 5, 8, 13, 14, 15, 16, 19, and 20)
Loglcl ...... ..................
LogleO ........................

2.0
0

5.5 Volts
0.8 Vo"s

(pIns 21,26, 31)
Loglcl ......... ...............
LogicO ........................

2.0
0

5.5 Volts
0.7 Volts

Logic Loading:
(Pins 5, 8, 13, 14, 15, 16, 19, and 20)
Loglcl ...................... .
LogicO ..•.•.••.•..•.•.•.....•

1 j.tA
-280 j.tA

(Pins 21, 26, 31)
Loglcl ...................... ..
LogicO •..•.•• , ••••.•.•.•••.•.•

20 j.tA
-0.40 j.tA

Multiplexer Address Set-up
Time .........................

-

Enable to Date Valid

-

STROBE (Note 4) • . . . . • . • . • . • . . . • •

Bits

nSec.

20

Delay ........................ .

PERFORMANCE

7-10

MAX.

2.0 KOhms

±2 mV
± (30ppm/°C x Gain) ± 20
ppm/DC (max)

Common Mode Range .....•.....•.

...............

TYP.

.............

FUNCTIONAL SPECIFICATIONS

Signal Range
Unipolar
Galn=I .••......•..•..•......
Gain = 200 ........•....•...•..
Bipolar
Galn=I .......•.•......•..•..
Gain 200 ....................

MIN.

Differential
Nonlinearity:
+25°C
0·Ct070oC ...................
-55°C to +125°C
Differential Nonlinearity
Tempco •.......................

20
40

30 nSec.
nSec.

±"4 LSB
±1 LSB
±1 LSB

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

HDAS-16, HDAS-8
OUTPUTS

MIN.

Logic Levels:
(Pin 7 & Output Data)
Logic 1 .......................
Logic 0 .......................

TYP.

MAX.

UNITS

-

-

Volts
0.4 Volts

PIN NO.
2.4

-

(Pins 9, 10, 11, and 12)
Logic 1 . . . . . . . . . . . . . . . . . . . . . .
Logic 0 .......................

4.4

-

-

-

- Volts
0.1 Volts

Logic Loading:
Logic 1 .......................
Logic 0 .......................

-

-

400 ~A
4 mA

.

Internal Reference:
Voltage, +25'C •...............
Drift ..... , ... '" ..............
External current ................

+9.99

-

+10.00 +10.01 Volts de
±20 ppm/'C
1 mA
-

-

Data Output Coding .............. Straight binary (unipolar) or offset
binary (bipolar)
POWER REQUIREMENTS
Power Supply Range:
+ 15V dc Supply ................
-15V de Supply ................
+ 5 de Supply ..................
Supply Current:
+ 15V Supply •.................
-15V Supply ..................
+5V Supply ...................
Power Dissipation ...............

PIN CONNECTIONS

+14.5
-14.5
+4.75

--

+15.0
-15.0
+5.0

-

-

1.45

+15.5 Volts de
- 15.5 Volts de
+5.25 Volts de
+40
-45
+95
1.75

mA
mA
mA
Watts

PHYSICAL - ENVIRONMENTAL
Operating
Temperature Range:
Me Models ....................
0
+70 deg. C
MM MOdels ....................
-55
+125 deg.C
Storage Temperature
-65
+150 deg.C
Range: ........................
1.4(39.7)
oz. (gram)
Weight ........................
Package Type .................. 62-pin hermetically sealed Ceramic DIP
Kovar
Pin Type ......................

SPECIFICATION NOTES
1. Analog inputs will withstand ± 35 volts with power on. II the power is off,
the maximum safe input (no damage) is ± 20 volts.
2. The gain equation error is guaranteed before external trimming and applies
at gains under 50. This error increases at gains over 50.
3. Adjustable to zero.
4. STROBE pulse width must be smaller than EOC period to achieve
maximum throughput rate.

TECHNICAL NOTES
1. Input channels are protected to 20 volts beyond the power supplies. All dig·
ital output pins have one second short circuit protection; CHOLD has a ten
second short circuit protection.
2. To retain high system throughput rate while digitizing low level signals, apply
external high-gain amplifiers for each channel. Datel's AM-551 is suggested
for such amplifier-per-channel applications.
3. The HDAS devices have sell-starting circuits for free-running sequential operation. II, however, in a power-up condition the supply voltage slew rate is less
than 3V per microsecond, the free running state might not be initialized. Apply
a negative pulse to the STROBE, to eliminate this condition.
4. For unipolar operation, connect BIPOLAR INPUT (pin 38) to S/H OUT (pin 39).
For bipolar operation, connect BIPOLAR INPUT (pin 38) to + 10V REFERENCE
OUT (pin 40).

5. RDELA Y may be a standard value 5% carbon composition orfilm type resistor.
6. RGAIN must be very accurate with low temperature coefficients. II necessary,
fabricate the gain resistor from a precision metal film type in series with a low
value trim resistor or potentiometer. The total resistor temperature coefficient
muet be no greater than ± 10 ppm/"C.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62

HDAS·16

HDAS·8

CH31N
CH21N
CHI IN
CHOIN
MUX ENABLE
R DELAY
EOC
STROBE
A8
MULTIPLEXER
A4
ADDRESS
A2
OUT
Al
RA8
MULTIPLEXER
RA4
ADDRESS
RA2
IN
RAI
DIGITAL COMMON
+5V dc
LOAD ENABLE
CLEAR ENABLE
ENABLE (Bits 9-12)
BIT 12 OUT (LSB)
BIT 11 OUT
BIT 10 OUT
BIT 9 OUT
ENABLE (Bits 5-8)
BIT 8 OUT
BIT 7 OUT
BIT 6 OUT
BIT 5 OUT
ENABLE (Bits 1-4)
BIT 4 OUT
BIT 3 OUT
BIT 2 OUT
BIT lOUT (MSB)
GAIN ADJUST
OFFSET ADJUST
BIPOLAR INPUT
SAMPLE/HOLD OUT
+10V OUT
ANALOG SIGNAL COMMON
ANALOG POWER COMMON
+ 15V dc
-15V dc
C HOLD HIGH
C HOLD LOW
R GAIN LOW
RGAIN HIGH
AMP. IN HIGH'
AMP. IN LOW'
CHIS IN
CH14 IN
CH13 IN
CH12 IN
CHll IN
CH10 IN
CH91N
CH81N
CH71N
CH61N
CH51N
CH41N

CH3
CH2
CHI
CHO

HIGH
HIGH
HIGH
HIGH

IN
IN
IN
IN

··
··
···
··
··
··
···
···
··

·
··
·
··

··
··
·
·
·
CH7 LOW IN
CH6 LOW IN
CH5 LOW IN
CH4 LOW IN
CH3 LOW IN
CH2 LOW IN
CHI LOW IN
CHO LOW IN
CH7 HIGH IN
CH6 HIGH IN
CH5 HIGH IN
CH4 HIGH IN

* Same as HDAS-16
1. Caution: pins 49 and 50 do not have overvoltage protection; therefore,
protected multiplexers, such as DATE!.:s MX-1606 an MX·808 are recom·
mended. See the channel expansion description.

DATEL. Inc. 11 Cabot Boulevard. Mansfield. MA 02048·1194fTEL (508) 339·3000fTLX 174388/FAX (508) 339·6356

7-11

HDAS-16, HDAS-8
Table 1.

Description of Pin Functions

FUNCTION
DIGITAL INPUTS
STROBE

LOGIC
STATE

LOAD

MULTIPLEXER
ENABLE
MULTIPLEXER
ADDRESS IN
DIGITAL OUTPUTS
EOC
ENABLE (1-4)

1 to 0 Initiates acquisition and conversion
of analog signal
o Random Address Mode Initiated
on falling edge of STROBE
1
Sequential Address Mode
o Allows next STROBE pulse to reset
MULTIPLEXER ADDRESS to CHO
overriding mAD COMMAND
o Disables internal MULTIPLEXER
1
Enables internal MULTIPLEXER
Selects channel for Random Address
Mode 8, 4, 2, and 1 natural binary coding

ENABLE (9-12)

o
1
o

o
1
o
1

MULTIPLEXER
ADDRESS OUT

Calibration Table

UNIPOLAR RANGE

o TO

+SV

o TO

+10V

ADJUST
ZERO
GAIN
ZERO
GAIN

INPUT VOLTAGE
+0.6 mV
+4.9982V
+1.2 mV
+9.9963V

OFFSET
GAIN
OFFSET
GAIN
OFFSET
GAIN

- 2.4994V
+2.4982V
-4.9988V
+4.9963V
-9.9976V
+9.9927V

BIPOLAR RANGE
±2.SV
±SV
±10V

CALIBRATION PROCEDURES

1

ENABLE (S-8)

DESCRIPTION

Table 2.

End of Conversion (STATUS)
Conversion complete
Conversion in process
Enables three-state outputs bits 1-4
Disables three-state outputs bits 1-4
Enables three-state outputs .bits 5-8
Disables three-state outputs bits 5-8
Enables three-state outputs bits 9-12
Disables three-state outputs bits 9-12
Output of MULTIPLEXER Address
Register 8, 4, 2, 1 natural binary
coding

ANALOG INPUTS
Channel Inputs . . . . . . limit voltage to ± 20V beyond power supplies.
Bipolar Input
. For unipolar operation, connect to pin 39
(s/H OUT)
,For biploar operation, connect to pin 40
(+10VOUT)
AMP. IN HIGH
These pins are direct inputs to the instrumenAMP. IN LOW
tation amplifier for external channel expansion
beyond 16SE or 8D channels.
ANALOG OUTPUTS
S/H OUT.
. Sample/Hold Output
+ 1OV OUT.
. Buffered + 10V reference output

1. Offset and gain adjustments are made by connecting two 20K
trim potentiometers as shown in Figure 1.
2. Connect a precision voltage source to pin 4 (CHO IN). If the
HDAS-8 is used, connect pin 58 (CHO LOW IN) to analog
ground. Ground pin 20 (CLEAR) and momentarily short pin 8
(STROBE). Trigger the AID by connecting pin 7 (EOC) to pin
8 (STROBE). Select proper value for RGAIN and RDELAY by
referring to Table 3.'
3. Adjust the precision voltage source to the value shown in Table
2 for the unipolar zero adjustment (ZERO + V2 LSB) or the
bipolar offset adjustment ( - FS + '/2 LSB). Adjust the offset trim
potentiometer so that the output code flickers equally between
000000000000 and 000000000001.
4. Change the output of the preCision voltage source to the value
shown in Table 2 for the unipolar or bipolar gain adjustment
(+ FS - 11/2 LSB). Adjust the gain trim potentiometer so that
the outputflickers equally between 1111 1111 1110 and 11111111
1111.

-

+ 15VDC

GAIN

ADJ

20K

36

ADJUSTMENT PINS
ANALOG SIGNAL
COMMON

Low level analog signal return

GAIN ..
ADJUSTMENT

External gain adjustment, see calibration
instructions.

20K

37

OFFSET
External offset adjustment. See calibration
ADJUSTMENT.
instructions.
R GAIN
....... Optional gain selection point. Factory adjusted
for G = 1 when left open.
C HOLD ........... Optional hold capacitor connection.
R DELAY. . . . . . . . . .. Optional acquisition time adjustment when
connected to +SV, factory adjusted for 9 "Sec.
Must be connected to +SV either directly or
through a resistor.

OFFSET
ADJ

Figure 1.

-15VOC

External Adjustment

THEORY OF OPERATION
The HDAS devices accept either 16 single-ended or 8 differential
input signals_ For single-ended circuits, the AMP IN LO (pin 50)
input to the instrumentation amplifier must terminate at ANALOG
SIGNAL COMMON (pin 41), For differential circuits, both the HI
and LO signal inputs must terminate externally for each channel.
Tie unused channels to the ANALOG SIGNAL COMMON (pin 41)_
Obtain additional channels by connecting external multiplexers
to the AMP IN HI (pin 49) and the AMP IN LO (pin 50), (See Figures
5 and 6)_
The acquisition time is the amount of time the multiplexer,
instrumentation amplifier, and sample/~~cgB~uire to settle within
a specified range of accuracy after
(pin 8) goes low,
The acquisition time period can be ObSSTR~~YEmeasuring how
long EOC is low after the falling edge of
(See Figure 2.)
For higher gains increase the acquisition time. Do this by connecting a resistor from RDELAY (pin 6) to +5V (pin 18). An external
resistor, RGAIN, can be added to increase the gain value. The gain

7-12

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

HDAS-16, HDAS-8
Table 3.

INPUT RANGE
±10V
±5V
±2.5V
±1V
±200 mV
± 100 mV
+50 mV
NOTES

Input Range Parameters (Typical)

RGAIN (0)

GAIN
1
2
4
10
50
100
200

OPEN
20.0K
6.667K
2.222K
408.2
202.0
100.5

ACQUISITION
AND SETTLING
RDELAY (0)
DELAY
o (SHORT)
9 "Sec.
o (SHORT)
9 "Sec.
o (SHORT)
9 "Sec.
o (SHORT)
9 "Sec.
7K
16 "Sec.
21K
30 "Sec.
51K
60 "Sec.

THROUGHPUT
55.5 KHz
55.5 KHz
55.5 KHz
55.5 KHz
40.0 KHz
25.6 KHz
14.5 KHz

SYSTEM
ACCURACY
(%of FSR)
0.009%
0.009%
0.009%
0.009%
0.010%
0.011%
0.016%

RGAIN (Q) ~ 20.000 RDELAY (Q) ~ (Delay ~sec. x 1000) _ 9000
(GAIN-I)
I. For gains between I and 10, RDELAY (pin 6) must be
3. The analog input range to the NO converter is 0 to +IOV for
shorted to + 5V (pin 18).
unipolar signals, and -IO.OV to + 10.0V for bipolar signals.
4. Full~scale can be accommodated for analog signal ranges of ±50mv
2. Throughput period equals Acquisition and Setlling Delay,
plus AID conversion period (10 microseconds maximum).
to ±10V.

is equal to 1 without an RGAIN resistor. Table 3 refers to the
appropriate RDELAY and RGAIN resistors required for various
gains.
The HDAS devices enter the hold mode and are ready for conversion as soon as the one-shot (controlling acquisition time) times
out. An internal clock is gated ON, and a start-convert pulse is sent
output high.
to the 12-bit AID converter, driving the

me

The HDAS devices can be configured for either bipolar or unipolar operation. (See Table 2). The conversion is complete within a
now returns low, the data
maximum of 10 microseconds. The
is valid and sent to the three-state output buffers. The sample/hold
amplifier is now ready to acquire new data. The next falling edge
olthe"STROBE pulse repeats the process forthe next conversion.

me

Table 4.

Output Coding

UNIPOLAR
+ FS -1 LSB
+ 'I2FS
+1 LSB
ZERO

STRAIGHT BINARY

Oto +10V

o to

+9.9976
+5.0000
+0.0024
0.0000

+4.9988
+2.5000
+0.0012
0.0000

+5V

BIPOLAR
+FS -1 LSB
+ 'I2FS
+1 LSB
ZERO
-FS+ 1 LSB
-FS

OFFSET BINARY·

±10 V

±5V

+9.9951
+5.0000
+0.0049
0.0000
-9.9951
-10.000

+4.9976
+2.5000
+0.0024
0.0000
-4.9976
-5.0000

"For 2'5 complement -

111111111111
1000 0000 0000
0000 0000 000 1
0000 0000 0000

111111111111
11 00 0000 0000
1000 0000 000 1
1000 0000 0000
0000 0000 000 1
0000 0000 0000

add inverter to MSB line.

FREE RUNNING SEQUENTIAL ADDRESS
Set pin 19 (LOAD) and pin 20 (CLEAR) to logic 1 or leave open.
Connect pin 7 (EOC) to pin 8 (STROBE). The falling edge of EOC
will increment channel address. This means that when the EOC
is low, the digital output data is valid for the previous channel (CHn
-1) than the channel indicated on MUX ADDRESS OUTPUT. The·
HDAS will continually scan all channels.
Example:

roc

CH4 has been addressed and a conversion takes place. The
goes low. That channel's data becomes valid, but MUX ADDRESS
CODE is now CH5.

TRIGGERED SEQUENTIAL ADDRESS
Set pin 19 (LOAD) and pin 20 (CLEAR) to logic 1 or leave open.
Apply a falling edge trigger pulse to pin 8 (STROBE). This negative transition causes the contents of the address counter to
be incremented by one, followed by an AID conversion in 9
microseconds.
DIFFERENTIAL OR SINGLE-ENDED INPUTS
The location of the analog signals being digitized dictates whether
to use single-ended or differential inputs. Problems arise when the
ground of the internal AID converter is at a potential difference far
from the ground of the analog signal. This results in a common
mode voltage.
Table 5.

Mux Channel Addressing

-+-- MUX ADDAESS-I
PIN
10
11
12
9
AAI
AA8
AA4
AA2

MULTIPLEXER ADDRESSING
X

The HDAS devices can be configured in either random or sequential addressing modes. Refer to Table 5 and the subsequent
descriptions. The number of channels sequentially addressed can
be truncated using the MUX ADDRESS OUT (pins 9, 10, 11 and
12) and appropriate decoding circuitry for the highest channel
desired. The decoding circuit can drive the CLEAR (pin 20) function low to reset the addressing to channel O.
RANDOM ADDRESS
Set pin 19 ([OA[) to logic O. The next falling edge of STFIDl3E
will load the MUX CHANNEL ADDRESS present on pin 13 to
pin 16. Digital address inputs must be stable 20 nanoseconds
before and after falling edge of STROBE pulse.

..J

5
MUX
ENAB.

X
0
0
0

X
0
0

X
0

0
0

1

0

0

0

1

0

1

0
D

1
1

(J

1

1
0
0
1
1

1
1
1
1

0

c

,

,,
1
1
1
1
1

,

g

g

0
0
1
1
1
1

1
0
0
1
1

1

,

0

1

1

0

1
1

1

~

0
1
0
1
0
1

,
1

1
1
1
1
1
1

w
Z
Z

c(

z::t

OU
NONE
0
1

2
3
4
5
6
7

HDAS-8
(3-BIT ADDAESS)

~

10
11
12
13
14
15

HDAS-16
(4-BIT ADDAESS)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

7-13

.;

HDAS-16, HDAS-8
- - I I - - 40 nSec MINIMUM
STAOBE

~ _ _ _ _ _- '

,

1- 40 nSec MINIMUM

--j

EXTERNAL
STROBE PULSE
CH12
DATA VALID

EDC

LOAD

1-11+ 12
ClEAA

-I

I, 12

2:

50

nsec

~

,

-1

I--

t 2::

20 nSec

~-.--------------------

AAe
RA4

AA2

AA1

1- 40 nSec TYPICAL

A8

Lx::RXi->L"'-""_ _ _ _ _ _-,--_ _ _ _ _ _, -_ _ _ _ _
--,--;-"

A4

x::RXi

A2

Lx::RXi~~"_

A1

Lx::RXi~~"_

_______,~------U
:LI___________
_____--_~:rF_-40-n-Sec-n-PI-CA-L------------~:~IL_____________________

I
MODE

I

CHO AOORESSEO

I

Cffiii

;

I

seOUENTIAL

CH1 ADDRESSED

Figure 2.

r---------------------,
+ 15V

I

I

I
I

I
I

A1

A,

A2

CH2 ADDRESSED

:

I CH12 ADDRESSED

RANDOM

><><><

MAY

~ANGE

DON't CARE

HDAS Timing Diagram

This common mode voltage occurs often when analog signals are
taken from different locations away from the AID converter. If signal sources are monitored from various locations, a differential
type input is needed.
I

I

(EOC TIED TO STAc5iE1

I

CHn
INPUT

problems by connecting the commons to one point ... the ground
plane beneath the converter when the above special grounding
considerations do not apply.

INPUT VOLTAGE PROTECTION
As shown in Figure 3, the multiplexer has reversed biased diodes
which protect the input channels from being damaged by overvoltage signals. The HDAS input channels are protected up to 20V
beyond the supplies and can be increased by adding series resistors (Ri) to each channel. The input resistor must limit the current
flowing through the protection diodes to 10 rnA.
The value of Ri for a specific voltage protection range (Vp) can
be calculated by the following formula:

RON == Rl + R2 == 2K

Figure 3.

Multiplexer Equivalent Circuit

Location of signal sources close to the HDAS devices (essentially
on the same chassis) eliminates the common mode voltage. A
single-ended hook-up can then be used, reducing the cost per
channel.

Vp = (R signal

+ Ri + Ron) (10 rnA)

=

where RON
2K
NOTE: Increased input series resistance will increase multiplexer settling time significantly.
THERMOCOUPLES
STRAIN GAGE

ATD (RESISTIVE THERMAL DEVICE)

The single-ended mode can still be used, even when the signal
sources are far from the HDAS, if all the signal sources are returned
to the same pOint. In effect, the analog signals are remote from the
HDAS, but in one location. The instrumentation amplifiers' LO (pin
50) input would then be tied to this common return point of the signal sources.
ANALOG SIGNAL COMMON, POWER COMMON, and DIGITAL
COMMON are connected internally. Avoid ground-related

7-14

e2-e,

=v¥c(~~:)
EXCITATION VOLTAGE
Velie"" 10V

+ 10V at 1 mA

R"" 100n

Figure 4.

Low-Level Inputs

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

HDAS·16, HDAS·8

CHO

0----;I
I
I
I
I

I

CHI5

o---!-

RA 1 RA2 RA4 RAS

I

RAI
RANDOM
{
ADDRESS
INPUT

12-BIT DIGITAL OUTPUT
WITH THREE STATE BUFFER

HDAS-16

I

I

RA2
RA4
RAB

II

AMPIN
MUX
ENABLE AS MA2 Al HI LO

~ANALOG

I
r--

IT

D

!,..,
v
CHI6

~

TPM-15/IOO - 5/500

POWE R SUPPLY
±15V at 100 rnA
+5Vat500mA

ICI
CK 0
'-----

MUX
OUT

I

I
I

!NHIBIT

"'}

I

AS

I
I
I
I

CH31

I f Gt t

SIGNAL
COMMON

RAI6

15v

+SV+15V

AS
A4

A4

MXI606

,

A2

I

Al

MULTIPLEXER
ADDRESS
OUTPUT

A2
Al

MXI60616 CHANNEL CMOS MULTIPLEXER
lel - TYPE "0" FLIP FLOP

Figure 5.

32-Channel, Single-Ended Data Acquistion System

Remote monitoring of low level signals can be difficult, especially when analog signals pass through an environment with
high levels of electrical noise. One solution is to use an instrumentation amplifier to extract the common mode voltage
and amplify the voltage difference. The HDAS-8, an eight channel differential input system, can reject common-mode noise
and allow amplification up to a gain of 200. Direct connections to
thermocouples, transducers, strain gages and RTD can be made

through shielded twisted pairs. A differential RC filter may be used
to attenuate normal mode noise.

MULTIPLEXER EXPANSION
Figure 5 shows an interconnection scheme for expanding the multiplexer channel capacity of the HDAS-16 from 16 channels singleended to 32 channels. Figure 6 shows a similar scheme to expand
the HDAS-16 to 16 differential channels.
'0.'.'

CHO HI

;-

•

12-BIT DIGITAL OUTPUT
WITH THREE STATE BUFFER

HDAS-16

CHI5 HI

o----i-

I

RAI

RANDOM
ADDRESS
INPUT

RAI RA2 RA3 RMI!

1

RA2 0

I

AMPIN
La

AS A4 A2 Al

t

+y+15V

I

RA4
RAS

~

STROBE

.
GtD

r

TPM-15/100- 5/500

POWE R SUPPLY
±15Vat100mA
+5Vat 500mA

CHO La

MUX
OUT

I

I
INHIBIT

I

I

I
I
I
I

CH15 La

I---- + 5V

AS
MX-I606

M
ASl MUX
ADDRESS
OUTPUT

M

,

A2

I

Al

A2
Al
MXI606

Figure 6.

16 CHANNEL CMOS MULTIPLEXER

16-Channel Differential Data Acquistion System

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

7-15

:'

HDAS-16, HDAS-8
+5V ± O.5Vat + 95mA

CHO

CHIl •

HOAS

AMP IN LO
SH

-lOV

OUl

~

BIPOLAR
IN

OUT

+15V

40:1- _BIPOLAR
1-,,38
_ _ _ _ _ -.J
:

39:

± MV at 40 rnA

+15V

___________ J

POWER
SUPPLY

UNIPOLAR

15V

-1SV ± O.5Vat -45 rnA

OATH MODEL BPM 15 100
OR EQUIVALENT

Figure 7.

Simple Connection Diagram

NOTES:
1. For HDAS-16, tie pin 50 to a "signal source common" if possible. Otherwise tie pin 50 to pin 41 (ANA SIG COM).
2. BIPOLAR connection yields ±10V range. UNIPOLAR connection yields 0 to +10V range. Other ranges are created by selecting appropriate value for RGAIN

3. DIG COM, ANA PWR COM, and ANA SIG COM are internally
connected.

DATA8US

ORDERING INFORMATION
12

MODEL
Al

RAS} MUX

DIGITAL

ADDRESS

PROCESSOR
RAl

IN

1

STROBE
LOAD

AS,

MUX
ADDRESS

OUT

HOAS-16

HOAS 8

=
EN

(1-41

EN (5·8)
EN (9·121

EOC

,Bin

BIT12,

THREE -STATE
OUTPUT
OATA

OPERATING
TEMP. RANGE
OOCto + 700C
-55OC to + 1250C
-55OC to + 1250C
OOCto + 700C
-55OC to + 1250C
-55OC to + 1250C

HDAS-16MC
HDAS-16MM
HDAS-1618838
HDAS-8MC
HDAS-8MM
HDAS-8/8838
ACCESSORIES
Part Number

Description

58-6322-1
TP20K (20 K ohms)

Evaluation Socket
Trimming Potentiometer

Receptacle for PC board mounting can be ordered through AMP
Incorporated, #3-331272-4 (component lead spring socket) 62
required.
Each includes PC board with offset and gain potentiometers,
bifurcated terminals for electrical connections.

/8838 Models are fully compliant to MIL-STD-883.

Figure 8.

7-16

Processor Interface

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

MDAS·16, MDAS·8D
Modular Data
Acquisition System

FEATURES
• 16 Channels single ended or 8
channels differential
• 12·81t resolution
• 50 kHz Throughput rate
• Three-state outputs
• Low cost

DESCRIPTION
The MDAS-16 and MDAS-8D data acquisition modules are complete, self-contained
systems featuring 16-channel singleended or 8-channel differential operation
respectively. Resolution is 12 bits and
throughput rate is 50 kHz. Output data is
buffered three-state for interfacing to minior microcomputer data buses. Output data
can be transferred in three 4-bit bytes.
Output coding is straight binary for
unipolar operation and offset binary or
two's complement for bipolar operation.
The 4.6 x 2.5 x 0.375 inch size of these
modules is % inch narrower than other
competitive models. The small size and
low cost are made possible by extensive
use of hybrid and monolithic circuits to
reduce parts count and increase reliability.
Both models use DATEL's ADCHZ12BGC 12-bit hybrid AiD converter
along with a monolithic sample-hold and
analog multiplexer.
The MDAS-16 and MDAS-8D feature a
high degree of user flexibility with pinprogrammable input ranges of 0 to + 5V, 0
to +10V, ±2.5V, ±5V, and ±10V dc.
The systems may be operated in either
random or sequential channel addressing
modes. For applications where lower than
12-bit resolution can be used, the AiD converter can be short-cycled to achieve a
faster conversion rate. Output data is also
available in serial form with a gated clock
output.

MECHANICAL DIMENSIONS
INCHES (MM)

r.=====~36r=,T
................................... . --, ~
....................................

1B

lfoo.......- - - -

~~~~~~CH -----~

0.375 (9,S)

T

36B

WHEN MOUNTING TO CIRCUIT BOARD

I

AllOW THIS CLEARANCE IN ORDER
TO SEPARATE MODULE FROM RIGHT

________ L/A:~~~~NECTOR
0.300

The modules are housed in a shielded
steel case. Input-output connections are
made using a 72-pin connector.

GAJAOJo

(INTERNAL)

OFFStAOJo
(INTERNAL)

tw:t"~LTlT
(63.5)

2.125
(54,0)

.. .-l

-+

~-----------------~

0.200

~1·-----4.-60-_-_(_;~_.7)_ _ _ _ _.. ~0.200

..
1j . , . . - - - - - - -

I

--II
..

(116,8)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·11941TEL (508) 339·30001TLX 174388/FAX (508) 339-6356

7-17

MDAS-16 & MDAS-SD
FUNCTIONAL SPECIFICATIONS
Typical at 25 ·C, ± 15V and.

+5V supplies unless otherwise indicated.

ANALOG INPUTS
Number of Channels .......... 16 Single Ended (MDAS·16)
8 Differential (MDAS·8D)
Input Voltage Ranges
unipolar •..••••...••..••.. O to +5V 0 to + 10V
bipolar ....•.............. ±2.5V. ±5V. ±10V
Common Mode Range, min ..... ± 10V
Max. Input Voltage,
no damage •....•.. ; .••.•.. ± 15V
Inputlmpedance .•..•.•....•• 100 megohms
Input Bias Current ...••....... 3 nA. 10 nA max. 0 to 70°C
Input Capacitance
OFF channel ..•••..•.•...• 10 pF
ON channel .....•....•.... 100 pF
ACCURACY
Resolution •..••••..•••...... 12 Bits
Error, max. 50 kHz sampling .... ± 0.025% of FSR
Nonlinearity, max ••..•••...... ± 1 LSB
Diff. Nonlinearity, max .•...•... ± 1 LSB
Gain Error •••...•........... Adj. to zero
Offset Error ..••.•..••....... Adj. to zero
Temp. Coeff. of Gain, max. . ... ± 30 ppm/oe
Temp. Coeff. of Offset, max. . .• ± 7 ppm/oe of FS
Diff. Linearity Tempco, max •.•• ± 3 ppm/oe of FS
Common Mode Rejec., min •.... 70 dB at 1 kHz
Monotonicity ................ 0 °e to 70°C
Power Supply Rejection •••..•• 0.01%/% Supply
DYNAMIC CHARACTERISTICS
Throughput Rate, max.•••.••.• 50 kHz
Acquisition Time ..•.•••..•••. 6 pSec.
Conversion Time .......••..•• 14 pSec.
Aperture Time, max •..••..... '. 100 nsec.
Sample-Hold Droop, max •.•.•. 200 pV/msec.
Feedthrough, max•........... 0.01%
Channel Crosstalk (Mux.) •.•••. -80 dB at 1 kHz
DIGITAL OUTPUTS

DIGITAL INPUTS
Enable ••••..••••...•.•....• Three separate inputs which
enable three-state outputs in 4 bit
bytes.
1 TTL load
Mux Address In ••....••....•• 3 bit (MDAS-8D) or 4 bit (MDAS-16)
binary address
1 LS TTL load
Strobe ..................... 1 LS TTL load with 10K pull-up
resistor
AID Trigger .•.....••...••••. 1 LS TTL load with 10K pull-up
resistor
AID Trigger ................. 1 LS TTL load
Mux Enable .•..•....•...•••• 1 TTL load with 10K pull-up resistor
Count Enable •.....••...••••. 1 LS TTL load with 10K pull-up
resistor
Load Enable .....•.••..•••... 1 LS TTL load with 10K pull-up
resistor
Clear Enable •..•.•••...•...• 1 LS TTL load with 10K pull-up
resistor
MSB In ••........•••...••... 1 TTL load
Short Cycle ..•••....••...••• 1 TTL load with 10K pull-up resistor

POWER REQUIREMENTS
Power Supply Voltage .•••...•• + 15V dc ± 0.5V at 65 rnA
-lSV dc ±O.SV at 60 mA
+SV dc ±0.2SV at 200 mA
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range .•..... ooe to + 70°C
StorageTemperatureRlinge ... -2S0eto +8Soe
Package Size .•.....••....•. .4.6 x 2.S x 0.375 inches
(116.8 x 63.S x 9,S mm)
Package Type ....•...••..... Steel. shielded on S sides
Weight ..•••..•••..••••...•• 6 ounces (170 grams)
FOOTNOTES:

1. All outputs are Vout ("0") '" + O.4V. Vout ("1") ,,+ 2.4V
2. All inputs are Vin ("0") '" +0.8V. Vin ("1") "+2.0V

Parallel Data Out ..••..•.•...• 12 parallel lines of buffered threestate output data.
Drives 12 TTL loads.
Coding •...••...•.•........• Straight binary. offset binary. and
two's complement.
Serial Out. .............•...• Output data in MSB first. NRZ
format. Straight binary and offset
binary coding.
Drives 5 TTL loads.
Mux Address Out •......•••••• Buffered output of address register.
Drives 20 TTL loads.
Delay Out. •...••...••••.•••. Drives 5 TTL loads.
Clock Out •........•...••...• Drives 5 TTL loads.
EOC (Status) .••.•.•.••••.••• Drives 4 TTL loads.
MSB Out ................... Drives 5 TTL loads.
MSBOut ................... Drives 5 TTL loads.

7-18

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

MDAS-16 & MDAS-SD
BLOCK DIAGRAM MDAS-16, MDAS-SD
0

~
:?
in

to

rH

3T
4T

[H

CH

0

~T

CH
CH
CH

3
4

CH 0 lOCH

R

CH 1 L() CH

9

CH ? LO
CH ] LO
CH 4 LO
CH5l0
CH 6 LO

'-J

3

'z"
;;'
"'"
~

r.l.-L-...Li===::::;

~---<>

6T
7T
8T
9T

r---I

6
7 lOT
18

238 MSB our
28B MSBOUT
24T MSB IN

29T
298
JOT
r-~ JOB

BIT
BIT
BIT
BIT

1 }
2
3
4

14TENABU
Ir--,

- 3lT BIT 5 }
31B BIT 6

48

32T BIT 7
328 BIT 8
158 ENABLE

CH 10 t>B
CH 11 68
CH 12 7B
CH13 88
CH 14 98

33T BIT 9 }
338 BIT 10
j41 BIT 11

rH7LOCH'~10B

L,_~~J"L..C=:; ~;~ ~~~~~E
'--+-~+I-+-----o 278 Eoe

'-----U
",2

~~

CH 0 3T

1---------<> 18T SERIAL OUT
1--_______<> 268 CLOCK OUT
/--------<> 238 MS8 OUT
r--------<> 288 MS8 OUT

CH 1 4T
CH 2 5T

CH 3 6T

CH4 7T

16SING. CH

8 DIFF CH
ANALOG
MULTIPLEXER

CH 5 8T
CH6 9T

,--------<>

24T MS8 IN

CH 7 lOT
CH 0 LOICH 8

38

CH 1 LOICH 9

48

CH 2l0lCH 10 58
CH 3 LOICH"

68

29T 81T 1 (MS81

MX-1606
MXD·807

12 BIT
AID
CONVERTER

CH 4 LOfCH 12 78
CH 5 LOICH 13 88
CH 6 LQICH 14 98
CH 7 LOICH 15 lOB

THREE·
STATE
OUTPUT

298 81T 2

o 30TBIT3
30B BIT4

L -_ _-<>

ADC·HS

14TENABLE 1·4

31T BIT 5
THREE·
STATE
OUTPUT

31BBIT6
32TBIT7
32881T8

L -_ _-<> 158 ENA8LE 5-8

33T81T9

:!!

t-t-tN N _
~ -0'"

w

1

~

'"

<
~

~~
w w
2 4 8 ~
~

MUX
ADDRESS
OUT

X
;:)

1

'" 17TENABLE 9-12

t-

Amplifier In +

Gain 1 Select In
Enable (6its 9-12)

348 81T 12 (LS81

u

Range 2 Select
Sample Hold Out
Enable (6its 1-4 Out)

Bipolar Offset

34T BIT 11

:0

Signal
+ 15V de
Analog Gnd.
Ch. 0 In/Ch. 0 High
Ch. 1 In/Ch. 1 High
Ch. 2 In/Ch. 2 High
Ch. 3 In/Ch. 3 High
Ch. 4 IniCh. 4 High
Ch. 5 In/Ch. 5 High
Ch. 6 In/Ch. 6 High
Ch. 7 In/Ch. 7 High

338 81T 10
-0

Cl

PIN CONNECTIONS FOR MDAS-940
Signal

THREE·
STATE
OUTPUT

Positive analog supply voltage. +15V dc at
65 rnA typical.
Negative analog supply voltage. - 15V dc
at 60 rnA typical.
Analog common. Analog common and
digital common (Pins 35T/35B) are connected within the module and should not
be connected externally.
Analog inputs to multiplexer. MOAS-94DS
has 16 single-ended inputs. The
MOAS-940D has 8 differential inputs.
Analog monitoring point for the positive input of the internal Programmable Gain
Amplifier.
Analog monitoring point for the negative input of the internal Programmable Gain
Amplifier. For normal operation on the
MOAS-940S this pin must be grounded.
NO converter input resistor. Should be
grounded when not being used. See Input
Range Selection Chart.
NO converter input resistor. Should be
grounded when not being used_ See Input
Range Selection Chart.
Sample-Hold output. Connect to
desired range select pin for normal operation. See Input Range Selection Chart.

...

*Three-State Outputs

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

7-25

~~IL

MDAS-940S, MDAS-940D
PIN

MNEMONIC DESCRIPTION

13B

P.G.A. Out

14T

Enable 1-4

14B

15T

15B

Summing
Junction

Bipolar
Offset

Enable 5-8

16T116B Gain Select
IN 1 & 2

17T

Enable 9-12

17B

Mux. Enable

18T

Serial Out

18B

Count Enable

19T
through
22T
19B
through
22B

Mux. Address
Out

23T

Delay Out

Mux. Address
In

23B

MSB Out

24T

MSB In

24B

Load
Enable

25T

Strobe

7-26

Analog monitoring point for the output of
the internal Programmable Gain Amplifier.
Enable line for three-state output, bits
1-4. Input low enables output, input high inhibits output. Max. enable delay is 30
nsec.
Comparator input for AID converter,
used in range selection. See Input Range
Selection Chart. Make no other external
connections to prevent performance
degradation.
AID Converter Bipolar Offset. Connnect
to Summing Junction (Pin 14B) for bipolar
operation, or to analog common (Pins
2T/2B) for unipolar operation. See Input
Range Selection Chart.
Enable Line for three-state outputs, bits
5-8. Input low enables output, input high inhibits output. Max. enable delay is 30
nsec.
Address lines that select gain 8 of
Internal Programmable Gain Amplifier.
Gains of 1, 2, 4, or 8 may be selected.
See Gain Selection Chart.
Enable line for three-state outputs, bits
9-12. Input low enables output, input high
inhibits output. Max. enable delay is 30
nsec.
Enable line for analog multiplexer. Input
high enables mUltiplexer, Input low disconnects multiplexer for external channel
expansion.
Serial Output data in NRZ format, MSB
first. Data is synchronous with Clock Out
(Pin 26B), use negative edge of clock to
strobe each bit.
Enable line for Mux. Address Register
Sequencing. Input high enables register
sequencing, Input low inhibits register
sequencing. Enable delay is 20 nsec.
Binary coded output of Mux. Address
Register. Should be buffered externally if
long etch runs or cables are to be driven.
Address lines that select one out of 16
(8-MDAS-940D) input channels when
operating in the random addressing mode.
Straight binary coding.
20 !'5ec. pulse used to delay start of AID
conversion to allow settling of the multiplexer, amplifier, and sample-hold.
Negative going edge initiates AID
conversion.
Bit 1 output of AID converter. Connected to
MSB In (Pin 24T) for straight binary or offset binary coding.
Bit 1 input to three-state output buffer.
Connect to MSB Out (Pin 23B) for straight
or offset binary coding. Connect to MSB
Out (Pin 28B) for Two's Complement
coding.
Input high for sequential addressing.
Input low for random addressing.
Loads address code for random ad~
dreSSing on high to low transition of
STROBE.
Negative input transition initiates channel
sequencing and gain selection in sequential mode, AID conversion when in random
mode.

PIN

MNEMONIC DESCRIPTION

25B

Clear
Enable

26T

Trigger

26B

Clock Out

27T

Gain 1
Select Out
EOC

27B

28T
28B

Gain 2
Select OUT
MSB out

29T129B Data Outputs
through
34T134B
35T/35B Digital Ground

36T/36B Logic Supply

Input low in conjunction with a negative
transition on Strobe (Pin 25T) will reset
the mux address register to zero.
Logic low to high transition resets AID converter and initiates next conversion.
AID converter clock output. Used as shift
clock for serial output data.
Output 1 of Gain Select Register.
Conversion status signal. Output high
during conversion, low when conversion is
complete.
Output 2 of Gain Select Register.
Complimented Bit-l output of AID converter. Connected to MSB in (Pin 24T) for
two's complement coding.
Three-state digital outputs.

Digital common. Digital Common and
Analog Common (Pins 2T/2B) are connected within the module and should not
be connected externally.
+ 5V dc at 200 mA typical.

CONNECTION AND CALIBRATION
1. Select input voltage range desired and connect pins 12B,
12T, and 15T in accordance with Table II. If the MDAS- 940S
is used, ground pin 11 B. Ground all analog channel inputs
which are not to be used. Leave pin 17B open.
2. Select the output coding desired. For straight binary
(unipolar) or offset binary (bipolar) connect pin 23B (MSB
Out) to pin 24T (MSB In). For two's complement (bipolar),
connect pin 28B (MSB Out) to pin 24T.
3. Select desired multiplexer mode.
A. Free Running Sequential Addressing
Connect pin 27B (EOC) to pin 25T (strobe). Leave pins
24B (Load Enable) and 25B (Clear Enable) open.
Sequencing is initiated by a positive logic transition applied
to pin 26T (Trigger). Pin 26T must remain high during free
running sequential addressing. Sequencing is stopped by
a low applied to pin 26T.
B. Triggered Sequential Addressing
Leave pins 24B (Load Enable) and 25B (Clear Enable)
open. Apply a falling edge trigger to pin 25T (Strobe). The
negative transition of the strobe will cause the contents of
the address counter to be incremented by one.
4. CALIBRATION
A. Connect power supplies to module and ground all analog
channel inputs. Monitor PGA Out pin (Pin 13B) and adjust
P.G.A. Null adjustment for O.OOOOV.
B. Connect a precision voltage source to pin 3T (Chan 0 In). If
the MDAS-940D is used, connect pin 3B (Chan 0 low) to
analog ground. Ground pin 25B (Clear Enable) and
momentarily short pin 25T (Strobe) to ground. Use an
oscilloscope to monitor the serial output code at pin 18T.
Trigger the AID converter with 50 kHz positive going
pulses applied to pin 26T (Trigger).

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

MDAS·940S, MDAS·940D
C. Adjust the precision voltage source to the value shown in
the Calibration Table for the unipolar zero adjustment
(zero + % LSB) or the bipolar offset adjustment (- FS
+ % LSB). Adjust the offset trimming potentiometer so
that the output code flickers equally between 0000 0000
0000 and 0000 0000 0001.
D. Change the output of the precision voltage source to the
value shown in the Calibration Table for the unipolar or
bipolar gain adjustment (+ FS - 1% LSB). Adjust the gain
trimming potentiometer so that the output flickers equally
between 1111 1111 1110 and 11111111 1111.

MUX CHANNEL ADDRESSING

19B

8
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

CALIBRATION TABLE
UNIPOLAR RANGE

o TO

+5V

o TO

+10V

ADJUST.
ZERO
GAIN
ZERO
GAIN

INPUT VOLTAGE
+0.6 mV
+4.9982V
+ 1.2 mV
+9.9963V

OFFSET
GAIN
OFFSET
GAIN

-4.9988V
+4.9963V
-9.9976V
+9.9927V

BIPOLAR RANGE
±5V
±10V

GAIN
SELECT
0
1
0
1

4
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

2
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

17B
MUX
ENAB.
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1

ON
CHANNEL
MDAS
MDAS
940S
9400

-

-

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

1
2
3
4
5
6
7
8

-

-

Data must be present far 70 nsec. min. after the high to low transition of STROBE.

GAIN SELECTION CHART
GAIN
SELECT
0
0
1
1

MUX ADDRESS
PIN
21B
22B
20B

INPUT RANGE SELECTION

PGA
GAIN1
1
2
4
8

lA factory option allows the gain range to be incremented upwards (for example:
10,20,40 and 80) for OEM orders. To retain 12·bit linearity, the P.G.A. gain must
not exceed 100. For more information contact your nearest DATEL sales office.

CONNECT THESE PINS TOGETHER
RANGE 2
BIPOLAR OFF.
RANGE 1
PIN 12T
PIN 1ST
PIN 12B
14B
13T
2T or 2B
13T
2T or 2B
13T
14B
13T
14B

INPUT
RANGE
o TO +5V
o TO +10V
±5V
±10V

TIMING DIAGRAM OUTPUT CODE: 010101010101

u

STROBE

~~YOUT ________________-fi':=============~2;O':~~'==============~~_______________________________

...,X'-________________________________+-________________~-------------

MUX ADDRESS OUT_ _ _ _ _ _ _ _ _ _ _ _

--i?<'-________________________________-:-,_______________________________

GAIN SELECTOUT_ _ _ _ _ _ _ _ _ _

1_.-----------

EDG

10 .usee

--------~-------------------------

L

-----------~.

CLOCK GUll

SERIAL OUT

,

BIT10UT----·----

-

__

---------~-------------------~

BIT20UT__________________

i-____

,

,

--------h---!-------

,u___

__

~i~---------------~--

--------W, ---i -------,----------

-_--+~____________________________________ii'----....Jh-· --..

BIT 3 OUT_______·_·
__
- _-_._._._._-

u

-

-

-. u

,
81T120UT

I

_________

~~

____

~.L..

_____________________

_

.

------1------

-. --. -

r-. --

c_

Ie

L -__________________-....J

1. Negative going edge of Delay pulse initiates conversion if Trigger (pin-26T) is open or high.
Allows for multiplexer and amplifier settling time and sample-hold acquisition time.
2. Train of negative going - 5V, 100 nsec. pulses at 1.5 MHz rate.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

7-27

•

MDAS-940S, MDAS-940D
CHANNEL EXPANSION WITH MDXP-32 AND MDXP-32-1
SINGLE LEVEL MULTIPLEXING FOR 48 SINGLE-ENDED CHANNELS
MDAS-940S

MOXP-32

ANALOG
GND

DIGITAL
GNO

ANALOG
GND

3T --lOT 38 - - - lOT 1T 2T/8

CH1S

I
I

l1BAMPIN-

I

MUX OUT

I

MUXQUT

CH31

A16A32

CH32

I

ADDRESS

I

OUTPUT

29B
30T

28T

1 - - - - - - - - - / 1 7 8 MUX ENS

30B

33T

1------- - ..

+5VDC REG. PWR IN

+ 15 VDC REG. PWR IN

-15VDC REG. PWR IN

CH.1 HI IN

CH.1LOIN

CH.2HIIN

<5

CH.2LOIN

CH.3HIIN

::

;;;

CH. 3 LOIN

CH.4HIIN

C;;

CH.4LOIN

CH.5HIIN

U;

:;:
a,
0;

CH.6LOIN

~

CH.7LOIN

~

CH.8LOIN

CH.6HIIN
CH.7HIIN

'iO"

CH.8HIIN

~

COLD JCT. COMPo IN

'"
'"'"
'"'"

ADCIN
RGAININ

c.>

BAUD 2 SELECT

ill

Rx DATA IN

~

SCAN TRIG. IN.
TxDATAOUT
- LOOP OUT (ISOL.)

c.>

'"
'"'"
'"'"

.'"

RGAININ

'"'"

BAUD 4 SELECT

~

BAUD 1 SELECT

c.>

LOOP I RS·232·C SEL.

~

BAUD 8 SELECT

'"
'"'"
'"'"
~

- LOOP IN (ISOL.)

fZ

:!I~
f:;
t

CONNECTOR
END
VIEW

REF. OUT

~

SIG.lDIG. GND.
SIG.lDIG. GND.

CH. 5 LO IN

LABEL

SIDE

+ LOOP OUT (ISOL.)
+ LOOP IN (ISOL.)
REO. TO SEND OUT
SIG.lDIG. GND.
SIG.lDIG. GND.

DATA LINK HANDSHAKING

ERROR DETECTION

SDAS-8 uses a minimal subset of the EIA RS-232-C I/O line
designation (refer to the block diagram), consisting of Transmitted Data, Received Data, Signal Ground and Protective
Ground. SDAS-8 also supplies an RS-232-C level Request-toSend output which is always asserted when power is applied.
Users may also need to assert the Data Set Ready input to the
terminal or computer.
Otherwise, it is assumed that SDAS-8 will be used full duplex and
all handshaking is data-encoded. Users who must operate halfduplex may suppress normal character echo from SDAS-8 back
to the display by using the Q (CR) command. Users would
normally write their computer program to change a half-duplex
line from transmit to receive after the X (CR) scan command is
sent with the echo suppressed. After a polled (X command) AID
scan was received, the host should tum the line around to transmit to be ready for the next command.
SDAS-8 also interprets the XOFF/XON protocol (control S or
DC3/controi Q or DC1) to intermittently halt the SDAS-8 transmitter in mid-string. This is used with computers which have a
limited input string buffer length to prevent buffer overflow.

All data is tagged with a 4-character hexadecimal checksum. The
16-bit (4 ASCII hex character) checksum is a 2's complement
sum of all the previous data and control characters sent in the
string before the checksum characters (the MSB bit 7 in each
previous character is set to zero). By adding the checksum to the
string sum, a zero result will indicate no data errors. Normally a
user's program should perform this addition and CALL an errorflagging subroutine if the algebraic result is not zero. If the data
link reliability is high, or occasional data errors are tolerable,
this procedure is not required.
DISPLAY FORMATTING

For higheSt data efficiency, data is packed with a minimum of
formatting characters. Normally, for data logging or display
applications, the user would format the data (arrange it in tabular
columns), apply labels ("gallons per hour," "RPM," "pump No.4"
etc.) and apply offset and span scaling arithmetic to the data. This
is best done in the user's computer, probably using high-level
language such as BASIC or FORTRAN which have displayl
printout formatting syntax.

Send Escape first when operating SDAS-8 from a terminal

Using SDAS-8 with Datel's MPP-20 and APP-48A2 Printers

User's who wish to operate SDAS-8 manually from a CRT or
printer terminal or from a microcomputer which is emulating an
ASCII terminal should first send an Escape character to remove
SDAS-8 from the power-up printer mode. This mode is intended
for direct connection to Datel's APP-20 and APP-48 miniature
thermal printers using the triggered scan start. These printers
require suppression of Line Feed and 216 NUL characters
following the Carriage Return to allow time to print each line.
Sending an Escape after power-up reinstates the Line Feed
following Carriage Return and cancels the filler NUL's.

When SDAS-8 is first powered up, either of these full serial
RS-232-C printers may be directly connected and operated in the
triggered scan mode with a TTL start pulse to SDAS-8 pin 33. The
216 NUL filler characters following CR allow adequate time for the
750mS print cycle provided that 2400 BAUD or lower is selected.
In addition, the printer connector jumpering and DIP switches
must also match the SDAS-8 word format (8 data, no parity, 1
stop).

7-34

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

SDAS-S
SERIAL COMMAND SUMMARY
LEGEND:
1. XXX - X are characters entered and displayed on the
terminal.
2. ( ) are blind control characters (such as carriage return or
escape) which do not appear on the terminal.
3. [ ) are notes on the command. They are not entered or
displayed.
4. Carriage return (CR) requests the SDAS-8 to execute the
command consisting of the previous character string.
5. The asterisk (*) confirms that the command was executed,
and is ready for the next command.
6. The pound sign (#) indicates that the returned character
string is not executable. Re-enter a corrected string.
COMMAND CHARACTERS

G (CR) - Display status message
B (CR) - Display time (HR: MIN: SEC)
B 23:59:59 (CR) - Set time in 24 hour format
(Escape) - Reset all controls to power-up status except clock
(Backspace) - Delete previous character
(Control S or DC3 or XOFF) - [13 HEX) Stop transmission
immediate and wait
(Control Q or Del or XON) - [11 HEX] Start transmission
immediate, mid-string
R - Stop output transmission from SDAS-8.
Stop L mode auto-start timer. (CR) not required. Revert to
trigger or polled-start mode.
AID CONTROLS

X (CRI - Displav one scan
M:2 (CR) - Set up to display channel 2 only
M:l, 8 (CR) - Set up to display channels 1-8
L02 (CR) - Start automatic scan transmissions every 2
seconds. R or (ESC) are the only way to stop L mod.
L59:59 (CR) - Start automatic scan transmissions every 59
minutes :59 seconds
L17:59:59 (CR) - Start automatic scan transmissions every
17:59:59 hours: minutes I seconds (max).
H (CR) - Format AID data as hexadecimal ASCII

o (CR) -

Format NO data as decimal ASCII (cancel hex)

V (CR) - Format NO data as DC volts, (cancel thermocouple)

J (CR) -Format AID data linearized to selected thermocouple

•-

Power-up prompt. Previous command executed; ready for
next command.
# - Echoed string not executable; try again.

Transmit AID data from CJC channel, equivalent
ambient temperature. Range :±:99°C
F (CR) - Format AID data as Fahrenheit.
C (CR) - Format AID data as Celsius.

A (CR) -

TERMINAL CONTROLS

W (CR) - Toggles between rubout echo as BS-SP-BS
or /X where X is the last character.
Set column width to 20,40,48,72,80 or 132 (20 ~
power up state)
E (CR) - Echo all printables (power up state) for full duplex
(CR) - Don't echo printables (for half duplex)
N nnn (CR) - Insert nnn nulls between, CR, NULL's, LF
N255 (CR) - Suppress line feed. End all scans with CR,
(NULL's), no line feed, N255 (CR) is a toggle,
which cycles on and off with each application.
Confirm the line feed status bit using the G
status.
P80 (CR) -

a

IDENT STRING

I : nnn - n (CR) - Start all AID scans with the Ident character
string nnn - n (20 characters max)

All lower case prlntables - Echo if selected. Not acted upon.
All non-specified controls - Echo if selected. Not acted upon.
BN (CR) - Delete, time and station

BY (CR) - Resume, time and station
POWER UP MODE
Station 1
20 characters per line
Trigger/polled scan start
8 channels, 1-8
Echo on
Elapsed time from power-on
The line terminator sequence at power up is:

For CRTs, send ESCAPE to cancel the NUL's and restore

LF.

K(CR)
S(CR)
T(CR)

NOTICE
The circuits and software programs contained in SDAS-8
are proprietary to Datel. Purchase of this product entitles
the customer to the product's usage in his application but
does not transfer rights to the circuits orsoftware programs
contained within the product. The user may not disclose to
third parties any information learned about SDAS-8 internal proprietary information. The user is explicitly prohibited
from disassembling the software program. Reproduction of
the software program by any means is illegal except under
contract agreement. Circuits or software programs which
are developed by the user and are incorporated within this
product via EPROM reprogramming which are based on
contracted disclosure of information proprietary to Datel,
may convey rights as agreed to in the terms of said contract.
The applications information shown in this brochure is in-

tended to illustrate design suggestions for many possible
applications. It is not intended as production-ready circuits
for specific applications. Since Datel has no control over
the selection, mounting, interconnection, fabrication and
environmental factors of external components in the user's
application, explicit performance in a specific application
cannot be warranted.
This information is believed to be accurate and reliable.
Datel cannot assume responsibility for infringement of
present or future patents or other third party rights resulting from product use. No license is granted by implication
or otherwise under any patent, patent rights or otherwise of
Datel. Prices and specifications may be subject to change
without notice consistent with product improvement or
manufacturing conditions. Datel's policy is to prevent specification changes within a specific product model number.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

7-35

•

SDAs-a
DATA OUTPUT FORMAT
The following message samples were prepared on an SDAS-8
directly connected to an RS-232-C Datel APP-48A2 thermal
printer and a CRT terminal. These data printouts indicate the
degree of formatting control. channel selection. editing and message readability offered by SDAS-8. Note throughout these
samples the visual format consistency even when changing line
length. Each data point uses a constant 9 characters and is
tagged with a hex checksum for optional error detection. Hexadecimal samples always include an "H" in the data with optional C
or F temperature tags trailing the H. The suppressable clock line

includes the station number aM an optional 2Q-character identl
header message is retumed with each sample (4 headers may be
used with 4 muHidrop stations).
While some computer programs may re-format returned data
strings. many will simply reflect the string out to a printer or other
ASCII device. SDAS-8 data will preserve the consistent readability of this output.
ASCII Controls which are blind (CR. LF. NUL·s. DEL. ESCAPE.
etc.) of course are not displayed but their effects can be seen in
the editing and non-executable command strings.

LOADING AN IDENT/HEADER STRING:

STATUS MESSAGE:

*G
B80481/ HEX STATUS
STATION 1 ONLINE
TINE 2:3: ~37: 15
40 CHARS PER LINE
START CHAN. IS 1
FINAL CHAN. IS 8
TYPE j THERMOCOUPLE
ECHO I:=:; ON
OUTPUT IS HEX. DEG F
DEL ECHOED /LAST CHR
NO LF AFTH: CF.:

*I:APP-20/48 PRINTOUT:
SETTING AND DISPLAYING THE CLOCK: .

*B2::::: 0t1: 00
*B
2:;:: 00: 02

2()'COLUMN OUTPUT:
PREVIOUS ~* ::.::.__SCAN START COMMAND

~~~~YPT.

APp-20 . . . 4::: PF.'INTOUT:.....~~~/NAL

~2:3 :
~:Ol~~:~g~ CK ~~11:

02:

NUMBER

21 : 14 1=
~i~I~~R
+::::. 1 '3 7
+0. (H3[i-4-s CHARACTER AID SAMPLE

1"1':" +1"1 I"1fU71
: 4'-' •

: ' : : : ..... (CR, NUL'S, LA

~j' : +1::.1. I::.H~Uj
05: +~~1. 000

BLIND, SELECTABLE TERMINAL
CONTROLS TRAILING EACH LINE

AMBIENT CJC CELSIUS DECIMAL OUTPUT:

*A
SDAS-8 IDENT STRING

~:H~i.0[H3
g~~~~~L NUMBER

07: +0. 001
t18: +[1. [127 HEX CHECKSUM
DOUBLE SLASH".. ...... Eqr·q.....-DATA DELIMITER

;+:':" -' -' -' _

23: H1: i3 i=

CJC:

cO~~:~~B~~~~Rc~g~~~~~pr

RESPONSE TO NON-EXECUTABLE COMMAND STRING:

4O-COLUMN OUTPUT USING THE IDENT/HEADER AS A DATE
STAMP WITH FAHRENHEIT THERMOCOUPLE PRESENTATION:

*BAD CONMAND SAMPLE
BAD COMMAND SAMPLE#

*::-:;

10/17.····:::::3 BATCH 'j
2:3: 15: 56 i=
01:+i824F/02:
+83F/03:
+83F
04:
+83F/05:
+83F/06:
+83F
07:
+83F/08:
+97FIIEA89

+27CIIF98:3

RESPONSE TO PRINTER-COMPATIBLE BACKSPACE
FUNCTION:

*DEL,/L./E./D
Note: Terminate each line
entered from the keyboard w~h carriage retum

48-COLUMN CELSIUS THERMOCOUPLE OUTPUT:

IBM PC SOASLOGGER
2:;:: 22: 00 1=
01: +7:36C/02:

+2'3C/06:
.·....····E'34'3
1"1~:

+29C/03:
+29C/07:

+29C/04:
+29C/08:

+29C
+35C

HEXADECIMAL CELSIUS OUTPUT AFTER SELECTING CHANNELS 1-3:

*1"1: 1 =- ::::

LO PRESS TURBO TEMP

: 30: 12 1=
01:02EOHC/02:001CHC/03:001CHCIIF1DF
~Xi

HEX.VOLTS OUTPUT, CHANNELS 1-3:

:+:::.::

MANIFOLD GAL..... HF::
::::[1: 2[1 1=
01: OC7EH/02: 0000H/03: 0000HIIF259
~X1:

7-36

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

SDAs-a
STATUS MESSAGE FORMAT
In response to a G (CR) command (or 2G, 3G, 4G for Multidrop
stations), SDAS-8 will transmit a status message in 20 column
format. The status message contains two parts: an encoded
hexa-decimal header and a plain-English body. The header may
be read by the user's host computer (after being intercepted by a
string-capture parsing program)
The status message indicates the contents of 3 status bytes (24
bits) which SDAS-8 assembles when status is requested. The 3
bytes are represented by 6 ASCII hex Gharacters such that the
least significant 4-bit hex nybble of each ASCII hex character

Status Message format (0

=

variable)

I FFFFFI/HEX STATUS 
STATION [!JON LINE 
[gQ] CHARS. PER LINE 
G~~~ER ISCAN START 

OJ

START CHAN. =

FINAL CHAN. = [ [ ] 
TYPEGDTHERMOCOUPLE : not listed on
default

ECHO IS

roNl
lQEEJ

I I

OUTPUT = DEC. VOLTS 
HEX. DEG.C
BS = I LAST CHAR. 
BS-SP-BS
LF ADDED AFTER CR 
NO LF AFTER CR

Encoded HEX Status:

TT

FFFFFF/HEX STATUS 
T
CHAN. SELECT BYTE (HI CHAN., LO CHAN.)
2ND STATUS BYTE
1ST STATUS BYTE
Power up default state will be: 000081
1st Status Byte
7 6 5 432

I

1 0

I I

10101010 0 1010 0
BITS 1 +

BIT 2
BIT 3

a -

-DEFAULTSTATE

00 For J type thermocouples (default state)
- 01 For K type thermocouples
- 10 For S type thermocouples
- 11 For T type thermocouples
- 0 = ECHO ON (default state)
-1 = ECHO OFF
- 0 = Output in volts [default) [overrides bits
0+1+5)
- 1 = Output in temperature

comprise the upper and lower nybbles of each of the 3 bytes.
Two of the status bytes indicate various formatting parameters
and the third byte indicates AID channel selection for that station.
The encoded hex status is placed at the beginning of the message to simplify the task of the user's parsing program (to avoid
searching the entire message string for status information).
At power-up, the status defaults to the state shown including 216
filler NUL's after CR and suppression of line feed. An Escape
command sent anytime thereafter reverts to this default state
except that the NUL's are deleted and LF is inserted after CR.
BIT 4
BIT 5
BIT 6
BIT 7

-

0 =
1=
0=
1=
0 =
1=

Output in Decimal (default state)
Output in Hexadecimal
Output in Celcius (default)
Output in Fahrenheit
Rubout or Backspace as / last char~defaul1)
Rubout as BS-SP-BS sequence
a = LF enabled after fill characters
1 = LF disabled after CR (default)

2nd Status Byte
76543210
10 I X 10 10 I 01010101

-

DEFAULT STATE

BITS 1+0

- 00 = Communicating with station 1 (default)
- 01 = Communicating with station 2
- 10 = Communicating with station 3
- 11 = Communicating with station 4
BITS 4+3+2 - 000 = 20 Characters per line (default)
- 001 = 40 Characters per line
- 010 = 48 Characters per line
- 011 = 72 Characters per line
- 100 = 80 Characters per line
- 101 = 132 Characters per line
- 0 = Trigger or polled start mode (default)
BIT 5
- 1 = Timer start mode
BIT 6
- Don't care
BIT 7
- 0 = XON SET (default)
-1 = XOFFSET
3rd Channel Selection Byte
7 6 543 2 1 0
1110\0\0\0\0\0\1\-DEFAULTSTATE
BITS 0+ 1+2+3 - Low channel scan selection
BITS 4+5+6+7 - High channel scan selection

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

7-37

SDAS-S
DUMB TERMINAL SESSION

A typical application for SDAS-8 is a remote A/D data transmitter
controlled by a host computer which continually logs A/D scans.
However, SDAS-8 may also be controlled manually from a dumb
terminal.
For demonstration purposes, a typical session with a dumb
terminal will be described. The dumb terminal consists of a
keyboard input device and a data output device consisting of a
printer or a CRT display.
All conversations use ASCII characters (ANSI x3.4-1977) sent
over EIA RS-232-C digital data lines. A minimum of 4 wires (RxD,
TxD, signal ground and chassis ground) carry all information.
SDAS emulates an on-line data base by echoing all printable
characters it receives. The user's dumb terminal would normally
be configured in full duplex so that the keyboard characters
appear on the display as SDAS-8 echoes them.
Power to the terminal is first turned on. Then SDA&8 is
turned on and after several seconds of self-tes~ it transmits
an asterisk (*) prompt indicating that it is ready for a command
For a dumb terminal, the user must send ESCAPE to cancel
the power-up printer mode. To see a plain-language status
message, the user then presses G and carriage return (CA).
SDA&8 responds by transmitting a status message terminated by an asterisk. The carriage return tells SDA&8 to
interpret the G (status) co'mmand and execute it
The returned asterisk indicates that SDA&8 successfully
completed the command and is ready for a new command In
this way, SDA&8 operates similarly to a microcomputer
monitor program.
The user may then send anyofthe commands, most of which
are a few characters long. Sending an X(CR) will immediately
send a full analog scan in decimal volts format The scan will
begin with the elapsed time from power on, the analog chair
nel data and ends with a 4-character hexadecimal checksum
This checksum is used by a host data logging computer to
continually verify the integrity of the data link
Repeated X (CA) commands will send subsequent analog

scans. This is the normal polled mode that a host computer
would use.
SDA&8 can also initiate its own scans by commanding it into
the timer auto-start mode. By pressing L03 (CA) for example,
SDA&8 will automatically send scans every 3 seconds and a
wide range of other timer intervals may be commanded, from
1 second to 17:59:59 hours.
A full menu of other commands may be invoked at any time during
operation since SDAS-8 continually listens to its serial input
except during scan transmission.
These commands alter the data format, printout format, and other
controls. Data may be sent as decimal or in 2's complement
hexadecimal, either as DC volts or linearized to J, K, S, or T
thermocouples in degrees Fahrenheit or Celsius. The local connector temperature may also be sent to invoke cold junction
compensation.
Power-up display width is initiated for 20 columns but may be
selected up to 132 columns. Therefore, all popular printers may
be employed.
Editing controls include 2 popular rubout formats, and a pound
sign (#) acknowledgement of an unintelligible (non-executable)
command string.
The 24 hour clock may be set and read for actual time or it may be
suppressed in returned scan strings to reduce transmission time.
Popular XON/XOFF transmitter controls are accepted by SDAS8 to accommodate host computers which need to avoid overflowing their input buffers. This is a common time-share/modem
control.
Users who prefer to use local half-duplex display of their keyboards may suppress the echo feature.
A selectable number of NULL characters may be inserted
between Carriage Return and Line Feed to accommodate certain
printers. Line feed may be suppressed so that carriage return
alone acts like a print command or NEWLINE/ENTER.
The polled scan transmission mode will also accept a local
SDAS-8 TTL trigger start pulse. For example, a simple data
logger requiring no keyboard may be built using a 74123 one-shot
trigger generator and Datel's miniature MPP-20 thermal printer.

SDAS-8 CALIBRATION PROCEDURE
This calibration is performed by alternately connecting the
inputterminals for channel 1 to ground (zero volts) and +/- 4.000
Vdc (nearly full scale). Adjustments are made to the calibra:tion
potentiometers until the instrument performs properly.
1. Make the normal external connections from SDAS-S to a DC
power supply and a separate video RS-232-C CRT terminal.
A microcomputer executing a dumb terminal emulator program may also be used instead as well as a printing terminal.
If a keyboard input device is not available, SDAS-8 scans may
be seen on a printer only using the local scan trigger input
repeatedly pulsed at pin 33. Strap the baud rate pins to as
high a baud rate as possible. Set the input PGIA gain equal
to one by making no connection to pins 26 and 27. The
complete ST-705 is recommended to simplify connections.
2. Assuming the use of a video terminal oremulator, firstturn on
the terminal power.
3. Turn on the SDAS-8 power supply. An asterisk (*) prompt
will appear on the terminal after ppwer up self-test. Because
of the power-up printer mode, the asterisk may take many
seconds at low baud rates.
4. Cancel the printer mode by sending an ESCAPE character
to SDAS-S.

7-38

5. Delete the clock line by sending BN(CR)
6. Delete the ident line by sending I:
7. Select channel 1 by sending M:1 
S. Select decimal volts display by sending D and V.
9. Cancel filler NUL's by sending Ncp
10. SDAS-S should now be ready for operation. Sending a G
status request will confirm the previous parameters. A single
analog scan may be seen by sending X
11. Start SDAS-S sampling once per second by sending Lcp 1.
This may be terminated with an R command.
12. Connect a precision DC voltage source of known accuracy
(such as Datel's DVC-85oo or DVC-350 DC voltage calibrators)
to pins 7, 8 and 1. Connect the calibrator HI (positive)
output to pin 7 and the LO (negative or ground) output to
pins Sand 1 connected together. All 3 pins must be
connected.
13. Set the calibrator output to zero output. SDAS-S should display zero or within a few counts of zero. An identical
reading should be seen if the calibrator is disconnected
and pins 7 and 8 are both grounded to pin 1.
14. Adjust any small offset error to a reading of 0.000 by

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

SDAS-8
CALIBRATION, CONTINUED
rotating the "ZERO" potentiometer at the end of the SDAS-B
case using a small slotted screwdriver.
15. Select an output of +4.000 Vdc on the calibrator.
16. Adjust the SDAS-B displayed output on the terminal to read
+4.000 by rotating the "GAIN" potentiometer on the SDAS-B
case, adjacent to the "ZERO" pot.
17. The "ZERO" and "GAIN" adjustments interact somewhat,
therefore repeat steps 14 through 16 until no further
improvement can be achieved.
1B. A rollover test can be made by reversing the positive and
negative calibrator output leads (sometimes this is available
using a polarity inversion switch). The SDAS-B displayed
output should be within -3.99B to -4.002 volts. If the
application will use predominantly negative inputs, the user
may wish to readjust the "GAIN" pot.
19. This completes the calibration for a gain of one. The user may
now proceed to higher gain and thermocouple input calibration if desired.
20. Programmable Gain Instrumentation Amplifier Calibration:
If the user is increasing the system amplification by adding
an external gain resistor connected adjacent to pins 26 and
27, calculate the desired resistance using the gain equation
(RGAIN=20Kn+(GAIN-1) ).
21. Connect the gain resistor and repeat the calibration steps
using proportionately lower calibrator output voltages (a
precision attenuator may be desirable).
22. Two important exceptions should be noted: PGIA gain
should be adjusted by trimming the external gain resistor,
not by adjusting the SDAS-B "GAIN". This is to avoid offset
interaction.
23. Similarly, higher gain offset corrections should be made
externally in the user's circuit with small offset adjustment
circuits.

If both external PGIA offset and gain adjustments are
impractical, the SDAS-B pots may be used but will no longer
be calibrated at a gain of one.
The guiding rule is to recalibrate if
gain changes are made.
24. SDAS-B is internally resistor-trimmed before shipment for
common mode rejection errors. To prevent PGIA settling
time difficulties, the channel multiplexing is inhibited and
the PGIA is continuously connected toChannel 1 by sending
the command Y:Eq:.q:.2. SDAS-B must be powered
down to reset this command. The PGIA analog output then
appears continuously on pin 25 and ND scans are terminated.
The CMR should not normally need adjustment. Contact
Datel if you need assistance.
25. Temperature Measurements are a complex interaction
between the calibration accuracy of the selected thermocouple, the PGIA gain resistor, the CJC sensor, any CJC
gradient error and previous SDAS-B "GAIN" and "ZERO"
pot adjustments.
A suggested procedure is to make two calibrated temperature sources available (an ice bath and a calibrated
oven), and a reference-grade thermocouple. Since this
may be impractical, an attenuated voltage calibrator
developing equivalent millivolt temperature outputs may
be used which track the published ANSI and NBS thermocouple tables. Using the calibrator method, ground the
CJC input (connect pin 23 to pin 2).
Select the appropriate linearization using the J,K,T, or S
 commands and degrees Celcius using C.
Calibrate as before, using the PGIA resistor if possible
for the high calibration temperature. Use the ice bath and
the SDA&B "ZERO" pot forO°Celsius. Null out any interaction with the "ZERO" and "GAIN" pots after initial PGIA
resistor adjustment

DETAILED COMMAND DESCRIPTION (SEE NEXT PAGE)
Command descriptions: The tables on the next page list ASCII character commands sent by the host computer or use(s terminal and
then acted upon by SDAS-a. All commands are upper case capitals
only. Lower case letters sent to SDAS-a are echoed back to the host
or terminal but are not acted upon.
Command Sequence - As each character is sent from the host or
terminal, it is immediately retransmitted (echoed) so that it may be
displayed on the terminal (in full duplex mode) to aid in typing or for
the host to confirm proper transmission. Execution of the command
by SDAS-a does not begin until the host or terminal sends ASCII
Carriage Return (CR). Until CR is sent, typing or transmission errors
may be fixed by sending ASCII backspace or delete characters. After
SDAS-a performs the command, it indicates completion by sending
as asterisk(*). The next command may begin immediately after the
asterisk and host software should test for errors if the asterisk is not
sent when expected. The only mode which appears to withhold
asterisk acknowledgements is the auto-scan L mode. During the L
mode, no other commands ean be accepted (true to the asterisk
convention) except the R or Escape command to terminate the L
command, at which time an asterisk is sent
These tables listthe command character, its hexadecimal byte equ~
valent code, and its keyboard input equivalent using the "contror'
(if' ) key. Other keyboard forms are also shown.

All control characters are "blind' (do not remain displayed) and are
designated by parenthesis ( ).The parenthesis should not be sent
Although command characters sent to SDAS-a are terminated with
a single (CR), output character strings returned from SDAS-a are
terminated with a selectable (CR. NUL's. LF) format to suit differing
terminals and printers.
These tables also include (where applicable) the command(s) to
alter the command which is listed
Most printable characters may be optionally echoed (full duplex) or
non-echoed (half-duplex). Control characters vary and this is shown
in the "echo" column.
The command formats listed below are for a single SDAS-a, channels 1-a, station 1. For multidrop applications. most commands require a station number prefix (1,2,3, or 4) for channels 9-16, 17-24,
and 25-32 respectively. Some commands (such as the L mode) are
not allowed in multidrop. The "Multidrop Usage" column lists these
variations.
During locally-triggered scans (trigger input to pin 33), SDAS-a
ignores inport serial characters but stores a single character in its
UART buffer.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

7-39

SDAS-8
INPUT ASCII
CHARACTERS

EQUIVALENT
CONTROL
( llCHAR.
ORHEX

MULTIDROP
USAGE

FUNCTION

NOTES:
ECHOABLE?
HOW TO ALTER?
OUTPUT RESPONSE, ETC.

FILL CHARACTERS AND LINE
FEED SUPPRESSION

Nnnn

Acted upon by
all stations
simultaneously,

Insert nnn NULL's ("HI atter CR to allow buffering delay for printers. nnn may be 8 " 2, or 3 digit
digit number with a range of 0 to 254 nulls

The power up state of the SDAS-8
is 216 NUL's after CR and no LF
for Datel APP-20/48 printer
usage with locally-triggered

scans.

Only Sta. 1
aCknowledges,

Example:
N3 causes all SDAS-8
transmissions to end with

Acted upon by
all stations
simultaneously.

N255

Only Sta, 1
acknowledges.

N255 alternately_ toggles Une Feed (IF)
suppression on and off after the CR. NUL's sequence
sent from SOAS-S. IF suppression state may be
checked with the G (status) command.

ECHO COMMANDS FOR HALF
OR FULL DUPLEX

Acted upon by
ALL stations. NO
PREFIX. Only Sta.
1 acknowledges

E

Echo all characters as sent except

After with

a 

eR echoes as selectable 
'(see description)
Escape echoes as ' (see
description)

Rubout or Delete (see W description)
Acted upon by
ALL stations. NO

Q

Stop echo on all commands including the

Alter with E  or Escape.

next E  until echo is restored

PREFIX. Only Sta
1 acknowl~~_~S

Normal X and L scans occur at all times.

ALL

~~:~~~:~~,f:~~~~t~~n ~~n:u~~~sas~~~~ ~~~~:8f

COMMANDS



00 hex.
Also desig·
nated 4"
or "ENTER"
or "NEWLINE"
or "RETURN"
on some
keyboards

STATIONS

NO
PREFIX

responds with an asterisk (oJ prompt. If the string is
not executable. SOAS-8 echoes the string. terminated with a pound (") sign  and a
new' prompt. The hne terminator sequence  always includes the CR, and useroptional filler NUL's (ASCII 00H) and user-optional
Une Feed. Successfull command execution delays
the prompt until R or Escape  clears the command buffer

Output responses:
1) If executable"


(e~ecution

interval]

2) If not executable

(unintelligible stringl'
~CA. NUL's LF>
An empty string (CA) alone
is not executable and is
returned as'
 ,
'

TERMINAL EDITING CONTROLS
Ruboul

7FH

0<

Delete

Echoed by selected
station only

Delete echoes as one of two formats depending
on the last state of the W command toggle. For
printer usage, delete echoes as slash, last
character (this is the power-up default mode).
Example: ABC (an unintelligible command
string) prints ABC/C/B/A if 3 deletes are sent
For video display terminal usage, delete echoes
as backspace-space-backspace, moving t~e
cursor backwards on the display and erasing
previously sent characters

Deletes always echoes unless no
previous characters were sent
after the last' prompt

Echoed by
selected station
only

W alternately toggles delete or backspace
characters sent to SDAS-8 as either slash, last
character or BS-space-BS (see delete). Delete
usage (W state) may be checked using the G
(status) command

W is selectable echo

ALL
STATIONS

Halt transmission immediately in mid-string
(a character in progress will be completed).
Send only XON or Escape after sending XOFF

Restored by XON

Resume transmission in mid-string, XON/XQFF
are commonly used for flow control of computers
and printers with limited buffer size

Do not set XOFF within a
command string before sending CR

0'

Backspace

D8H or
Control H.

W

HOST BUFFER OVERFLOW HANDSHAKES

XOFF

DC3.

Control S
0'

13 HEX

XDN

OCt, Control
00rl1 HEX

ALL
STATIONS

Pnnn

ALL
STATIONS,
no prefix

o
H

Use station
prefix, example:
3D  for station 3
(Ch. 17-24) only

LINE LENGTH CONTROLS
Pnnn  establishes the maKimum number
of characters sent per line before the line terminator. SOAS-8 supports
line lengths from 20 characters per.line (powerup default .value) to 132 character/h!'e. Channel
samples WIll be spaced for easiest vlewmg
and vertical tabular alignment to avoid skewing
a data sample over 2 lines. nnn may be 20, 40,
48.72.80,132 characters per line
AID CONTROLS
Radix controls:
o  formats output AID data as ASCII
bipolar (Sign/magnitude) decimal. H  formats output as sign-extended, 2's complement
binary transmitted as ASCII hexadecimal

Number of channels'
M:n,m

Use station prefix,
example: 3M: 17, 18


The M command selects the channels 10 be sent
M:5  sends channel 5 only.

XON/XOFF do not echo. XOFFI
XON may be sent several times
during transmission without
losing characters.

Example:
P80  will adjust SOAS-8
output not to exceed 80 char.lline.
The G status message is always 20
char.lline. Pnnn  is selectable
echo.

o and H are selectable echo,
Refer to the coding table for
information
Power-up default is Decimal. HEX
data is always tagged with an "H"
last character
M:n,m  is selectable echo.
Only one sequential interval is
aI/owed per station. Power-up
default mode enables all channels

4M:25, 29  sends channel 25 through 29
whenever station 4 is polled.

7-40

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

SDAS-8
INPUT ASCII
CHARACTERS

EQUIVALENT
CONTROL
(' ) CHAR.
OR HEX

MULTIDROP
USAGE

FUNCTION

NOTES:
ECHOABLE?
HOW TO ALTER?
OUTPUT RESPONSE, ETC.

SCAN TRANSMISSION STARTS,

X

Use station prefiJ(,

example: X

X starts a single scan transmission and is
the normal polled mode from a host computer

X is selectable echo

l mode is an auto-start scan transmission Butomatically sent from SDAS-8 using the timer interval specified in the L mode command string

Disable l mode with R  or

scans station 1
4X scans
channels 25-32
Not allowed in
multI-drop

Use for station
1 only

L mode timer range is 01 second to 17:59:59
hours: minutes: seconds.
Examples
L01  is 1 second
l~5: ~  is 5 minutes
LOS: 3e: 00  is 8'h hours
L20:  not allowed.
L2: 00  not allowed
L: 30  not allowed

Escape . All other commands except XON/XOFF are
ignored. L mode is not aI/owed
in multi-drop to avoid data cOllisions. An • acknowledgement
is not sent until R or Escape.

IDENTIFICATION/HEADER STRING
l:n--n

Use station prefix
for separate station
Example: 31' Ident


I:  is a general purpose user-loaded message line which will accept 96-character ASCII
printables of upper or lower case letters. numbers and punctuation. The character string will
truncate at 20 columns and is returned with each
scan as a first optional line before the clock
and station line

Delete the ident. string by sending
I: . the empty string which is
the power-up default state. 00
not send controls except CA, DEL.
LF. BS. Escape

SYSTEM RESETS
Escape

A


1B HEX
control (

ALL
STATIONS

ALL
STATIONS

Master reset, accepted at any time. Cancels
transmission tn progress. Clears command buffer. Does not reset clock registers

Echoes as ·
Video terminals must send ESC
first to reset printer mode.

Used to stop L mode or any transmission in
progress without changing other parameters
Cancelled strings are lost

Echoes as A ·
unless echo is off.

TIME~OF-DA Y

B
Bhh: mm: ss

BN
BY 

CLOCK CONTROLS

Use station
prefix for
separate stations
Example
3B
(no prefix) 8--sets all clocks
simultaneously

Sends clock string in 24 hour (23:59:59 Hours:
Minutes: Seconds) format
Sets clock. Example: B16:oo:oo  sets
4 PM. B0fj:00:00  is midnight

ALL

All controls not listed will have echo if selected
but will have no effect on SDAS-B. This allows
standard terminal control functions

Clock powers up at 00:00:00 with
clock and station number line
enabled. Clock is not reset by
Escape
Echo is selectable.

BN InhIbits clock characters in scan transmission,
to reduce transmisSion time BY Enables clockl
station line

MISCELLANEOUS
All nonspecified
controls

STATIONS

STATIONS

Will echo if selected but will have no effect and
wiU return a non-executable # with  unless cleared by Escape or Deletes. Ident strings
(see I' command) will accept all printables

ALL

Reserved, do not use

ALL
upper case
printables
O,U,Y,l

For calibration purposes onlv. the
command Y:E002  stops AID scanning and continuously switches the
anatog mux to channel t and the PGIA
output appears on pin 25 Power down
to reset

STATIONS

STATUS MESSAGE
May be terminated by A or Escape

Use slation prefix for separate
stations. Example
2G

The G command causes SDAS-B to transmit a
status message conSisting of a hexa-decimal
status code followed by a plain-language translalion. in 20-column format. See the status mess.age example. Status i.ncludes station number,.
time, char.lline, starVflnal channels, echo, declmat/hex, volts/thermocouple, delete usage and
LF suppression

Use station prefix for separate
stations

Linearize the AID data using ANSI/NBS J. K. S
or T thermocouple tables and correct for ambient temperature input voltage (COld junction
compensation) to pin 23. Data will be in decimalar hex format depending on the last state
of the H or 0 commands, and Celsius or Fahrenheit conversions

External PGA gain resistors (J, K
use gain = X8D : S. T use gain =
Xt60) and a CJC sensor circuit
are required. Cancel TC linearization using V (volts) command.

C
F

Use station prefiX for separate
stations

C and F format temperature data to Celsius or
Fahrenheit respectively

Escape or power-up defaults to
Celsius decimal format

A

Use station prefix for separate
stations

The A command returns the ambient temperature measured through the CJC sensor circuit
connected to pin 23 Data may be fornlatted
in decimal/hex, Celsius/Fahrenheit. In 20-column line length. the CJC output will be 3 lines
(times/station. CJC temp., checksum)

The local SOAS-8 temperature
may be accessed anytime a CJC
sensor circuit is installed, even if
thermocouples are not used. In
fact, this fi.ICed-gain (X100) ninth
channel may be used for any purpose but is only sent with the A
command. The maximum CJC
range is±99<> C (±4.095Vdc) and
resolves'" C.

G

THERMOCOUPLE TEMPERATURE
MEASUREMENT CONTROLS
J
K
S
T

Example:
00:39:35

CJC

1=

26C

II FBtE.
By suppressing the clock (BN  command) and requesting more than 20 characters
per tine (Example: P40 .) the CJC and
checksum will form on one line
Example' CJC: +26C//FD82

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

7·41

SDAs-a
MULTIDROP APPLICATIONS

This application shows up to four multidrop SDAS-8 stations
sharing common transmit and receive 20mA serial data loops.
Because each TfR serial port is optically isolated, the internal
analog channels may have several hundred volts of isolation from
station to station (within a single station however, analog inputs
must remain within the ± 11 V common mode voltage range). By
using the current loop mode, stations may be separated thousands of feet in low noise environments. The two current loops
require a source of excitation and a typical circuit and external
power supply is shown. Some host computers and terminals
include their own excitation supplies. Users should carefully test
~uch remote systems because low data errors are a complex
result of shielding, noise protection, wire type, baud rate, and link
ringing suppression.
Multidrop SDAS-8 stations are addressed with a station number
prefix before each command (Example: "3M:2(CR)" configures
station 3 (channels 17-24) to respond with only channel 18 in
returned data strings). Ommission of the station number prefix
aliNays implies station 1 (channels 1-8), which responds with or
without the 1 prefix.

In multidrop applications, separate stations may have differing
identification header strings and the station number is always
included at the end of the clock line.
Self start auto scans (L mode) are not allowed in multidrop applications, to avoid data collisions on the host computer's receive
port. Locally triggered scan starts are also not advisable in multidrop. Normal multidrop applications should use a polled mode,
"4X(CR)" for each station.
Multidrop allows a mix of different gains and transducer types
from station to station. Longer distance applications or those
demanding only two wires or applications where installing more
wires is unsuitable should consider using auto-answer RS-232-C
modems and either telephone or radio links.
The serial loop port circuits shown for each SDAS-8 station have
been simplified for this drawing. The actual circuits contain some
additional protection not shown for miswiring abuse (reverse
polarity clamps, current limiters, etc.).

TYPICAL 20mA ISOLATED SERIAL LOOP
MULTIDROP WIRING, 4 CONDUCTOR
WIRE MAY BE COAX.
lWlSTED PAIR, SHIELDED
PAIR, AS REQUIRED FOR LOW
DATA ERRORS.

+
37

tt
SDA&8
STATION
1
CH.1-8

UP
TO SEVERAL
THOUSAND
FEET IN
PROPER
CONDITIONS

tt
SDA&8
STATION
2

INCREASE
SHIELDING, REDUCE
DISTANCES AND
LOWER BAUD
RATES IF DATA
ERRORS OCCUR.

tt
SDA&8

HOST
COMPUTER

CH.9-16

tt

I
I

I

TRANSMIT
PORT

39

I

i

STATION
L_
SHIELDING
ANDRFI
-BYPASSING
AS REQUIRED

+

_ _ _ _ --r:"'-_....

-4-4-

I

T

NOTES:
1.
2
3.
4.
5.

The wiring sequence of each station is of no consequence
Select the loop excitatIon reSIstors, R, for loop current equals 20mA In mark.ing
(no data sent) conditions. R range approx. 430n to 6S0n
True 2-wire applications should consider voice grade, dial-up telephone
modems.
Some applications may require separate isolated T&·R port power supplies.
To preserve isolation, do not use the SDAS-8 15V DC power supply

=

R

R

+
+12VDC, COM
DATEL
UPM-12{100A

=:JIIC

AC
POWER

TRANSFORMER-ISOLATED
DC POWER SUPPLY. 12 to 18VDC

7-42

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

SDAS-8
MISCELLANEOUS APPLICATION NOTES
1. The baud rate code is internally stored in the SDA&8
memory at power-up. To change the baud rate, turn off
power first to reload the baud rate code.
2. Since SDA&8 is a software-based subsystem, excessive
electrical noise can introduce data errors or can disable
SDA&8, requiring power down to reset Use power supplies with larger bypass capaCitors to maintain continuous
voltage in the presence of power dropouts. This is partiCularly important forthe+5V supply powering the microprocessor and memory. In cases of severe, unavoidable
power supply problems, use an external means (relay,
microprocessor reset pil\ etc.) to remotely reset SDA&8
by momentarily powering down.
Similarly, excessive serial data link noise could send characters which affect data integrity. Periodic G status code
tests by the host computer may be recommended
Sources of high radiation should be avoided to prevent
errors in command/control bits. PROM checksum errors
will print a warning on power up if they occur.
3. For video terminals, send ESCAPE first after power up to
disable the 216 NUL's and reinstate LF's. At low baud
rates, ESCAPE is not acknowledged until the * asterisk
appears on power-up after many seconds of initial NUL's.
4. Be aware that the analog signal inputs are high impedance differential but are not isolated Therefore the common mode voltage range can be exceeded Even with a
transformer-isolatedAC powersupply, the R&232-C ports
are not isolated from the analog section. Use the 20mA
isoloop ports if required Or, external isolation amplifiers
such as DatersAM-227 may be used Telephone modems
also provide some isolation methods.
5. When connecting SDA&8 to a host computer, the host
must have a spare programmable auxiliary R&232-C
serial port which is not connected to the host console
device. On some personal computers, the "console" is an
internal connection to the keyboard and display. Therefore, the R&232-C port is truly a spare which is aSSignable
toSDA&8.
On some older microcomputers, the R&232-C port in the
CPU is for an external terminal used as a console. An additional R&232-C port board and driver programs may be
required

This port must be programmable, either using a terminal
emulator program forthe computer or as a port with known
internal addresses and register formats. The port baud
rate and word format may need to be altered and this is
usually done with jumpers or switches or with control data
loaded into registers or memory addresses.
6. SDA&8 is intended for DC or slowly-varying inputs such as
from transducers. A limited amount of increased data rate
may be obtained by suppressing the clock/station and
header lines, increasing the baud rate, and requesting only
one channel The NO converter however continuously
overwrites all 8 channels into RAM buffer at 15 samples
per second on interrupt basis.
7. Except for the L-mode autoscal\ users should write their
host control programs to inhibit sending new commands
until the previous asterisk (*) command acknowledgement is received
8. Miscellaneous uses for the Ident/Header string include:
A. Separation of adjacent records by loading 1 space
character in the Ident
B. Self-sorting of data from multidrop SDA&8 clusters on
several serial ports to multiple mass storage/disk files.
The header string would contain the drive number and
file name. For temporary buffering, the header could
contain a hex memory location or displacement which
could be dynamically incremented with each scan
block

C. Operator names (locally entered from hand-held terminals), dates, locations, job numbers, batch numbers,
reflected (G) status hex codes, calibration data results
from previous host computations, system revision
levels, driver program information

BOTH TRANSMIT AND RECEIVE
LINES IDLE IN THE "MARKING"
STATE (="1 "=-3V =20mA)

... ~~~~

HOST
COMPUTER

31)-~_ _ _ _ _ _ _-1----,-,XIc::"5",B",H),-,-,C~A'!.:I"",a""DH"')",-L-_W_HE_N_N_a_DA_T_A_'S_B_EI_NG_S_E_NT_._ _--1

IN

NOTES

SERIAL DATA FORMAT

HOST /f'
COMPUTER

OUTPORT

(REQUESTING 1 SCAN OF 8 AID CHANNELS)

SDAS..a

NOTE:
RS-232-C data is LO true, handshakes are HI true.

.... XMTD
DATA

aUT

w

Z

g

1 CHARACTER. (EXPANDED BIT VIEW)

=10 BITS
1 BIT =(l/BAUD RATE) SECONDS
(1.04mS/CHAR.at 9600 BAUD)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

7-43

•

SDAS-S
SDA5-S THERMOCOUPLE INPUT
Direct thermocouple inputs may be accepted by SDA5-8 for
J, K, S, and T ANSI thermocouple types. Thermocouple measurement requires several data manipulation and signal conditioning factors which are automatically provided by SDA&8
and some external circuits. Thermocouples require substantial gain since they are millivolt level outputs. The internal
SDA&8 resistor-·programmable gain amplifier(PGA) should
be selected for a gain of X80 for J, K thermocouples and X160
for S, T thermocouples. These gains require low-drift precision gain resistors listed below which must be mounted close
to SDA&8 to avoid noise errors:
TC

Gain

Gain Resistor"

Temp. Range

J
K
S
T

)(80
X80
X160
X160

253.16n
253.16n
125.79n
125.79n

-165°C/+ 760°C
-t65°C/+1232°C
0°C/+1768°C
-200°C/+400°C

* The PGA gain resistor is normally developed using a higher
value precision metal film or wirewound resistor which is
adjusted to final value with a parallel trim resistor.
Thermocouples are nonlinear devices which require linearization correction. In SDA&8, this is automatically
performed in software using a look-up table and linear interpolation algorithm. This function is invoked by sending a J, K,
S, or T command first (e~ample: 3K (CA) for station 3, channels 17-24) to SDA&8. All subsequent analog scans will be
linearized to the selected thermocouple. The user may subsequently request offset and scaling to degrees Celcius or

TYPICAL SDAS-8 COLD
JUNCTION COMPENSATION (CJC)
EXTERNAL SENSOR CIRCUT
(Included on ST -705)

Fahrenheit and data formatting to ASCII decimal or ASCII
hexadecimal (These are all automatically performed in software by SDA&8). The thermocoople linearization mode is
negated by sending the V (CA) command to revert to de
volts.
Thermocouple connections also require correction for the
EMF voltage error which is developed by the two junctions at
the screwterminal input connector. On this connector, two
thermocouple-ta-copper junctions are formed Since the two
thermocouple wires are dissimilar, the EMF voltages developed at the connector are different and this voltage difference changes over temperature. Over a small temperature
range, this function is essentially linear. SDA&8 automatioally performs a software correction for this voltage difference
error which is called cold junction compensation (CJC). To
make this correction however requires temperature measurement of the screw terminal connector. This temperature
is converted to a voltage input to a 9th SDA&8 Single-ended
channel input (pin 23). The conversion function for this CJC
input is VCJC = (Temp. - O°C) X40.96mV. Simple external circuits and a semiconductor temperature sensor will perform
this conversion This entire CJC function is offered on Daters
ST· 705 complete SDA&8 single-board subsystem. A sample
circuit is shown in this brochure. The user may access this
CJC channel at any time by sending the A (CA) command
(ambient temperature). For non-thermocouple applications,
this channel may also be used to measure local equipment
temperature as long as a CJC sensor and circuit are connected In volts mode (V command), a normal scan (X command) ignores any input on the CJC channel

CHAN.1 IN
SCREW
TERMINAL

OTHER

CONNECTOR

CONNECTIONS
NOT SHOWN

//

",CONNECTOR
,/

,/ ; /

TEMP.

1

1000PF,5QV

SDAS-8

58

SENSOR,!

I
I

CJC IN

,,

VCJc=(SENSOR TEMP.) x 40.96mV.

/

I
,_

lQKO /
0.1%/
-,SOTHERMAL.TO CONNECTOR
Te/COPPER JUNCTION

VCJC=OV. at OoC,

+1SV

A GAIN=20KO+(GAIN-l)

R GAIN (mount close to pins)
FOR J, K Te's, use GAIN=Xao
FOR S, T Te's, use GAIN=X.160

7-44

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339·6356

VFQ-1, VFQ-2, VFQ-3
Low Cost, Monolithic
V/F Converters

FEATURES
• 10 kHz to 100 kHz FS
• 0.01% Maximum linearity at 10 kHz
(VFQ-2)
• Single- or dual-supply operation
• Open collector output
• Pulse and square wave outputs
• Operates as V/F or FIV

GENERAL DESCRIPTION
DATEL's VFQ series is a family of lowcost, monolithic voltage· to-frequency converters combining bipolar and CMOS
technologies. These devices accept a
positive analog input current and produce
an output pulse train with a frequency
linearly proportional to an input current.
The full-scale output pulse rate can be set
from 10kHz to 100 kHz by means of two
external capacitors.

+Voo

ANALOG

GROUND

~~~TOR

8

l'

J--~~-1

7

r-~~,

INTEGR
OUT
-REF. IN

SQ. WAVE

OUT 11 0 12)

DIGITAL
GROUND

INPUT

CURRENT

Each model is available in a 14-pin Plastic
DIP for DoC to + 70°C operation, with the
VFQ-1 also available in a 14-pin Ceramic
DIP for - 25°C to + 85°C operation.

NO
CONNECTION

}-~~~-tYINTEGRATOR

Linearities are specified for both 10kHz
and 100 kHz full-scale outputs. The maximum linearity, at 10kHz, of the VFQ-1 is
0.05%, while the VFQ-2 has a maximum
of 0.01%, and the VFQ-3 has a 0.25%
maximum. The linearity holds over the full
output range of zero to full scale.
The internal circuitry of these converters
includes an operational integrator, a comparator, digital delay circuit, single-pole
double-throw electronic switch, a start circuit, a divide by two circuit, and two output
driver circuits. Operation is based on the
well-known charge balancing integrator
principle. The two outputs are open collector NPN which can sink up to 10 mA and
give a logical high output up to + 18 volts.
In normal operation these devices require
only five external components and a
reference. If the zeroing adjustment is
used, a trimming potentiometer and two
more resistors are required. The VFQ
series can be operated from dual ± 4 to
± 7.5V supplies or from a single + 10V to
+ 15V supply. They may also be operated
as frequency-to-voltage converters.

PULSE OUT
(fol

BIAS

-Vss

•

MECHANICAL DIMENSIONS
INCHES (MM)
CERAMIC PACKAGE

PLASTIC PACKAGE

0280 MAX
(7,n

~ ~-'--'-'--rn"TT"1--rr-,--J
PIN 1
IDENT

~

f--

0,070 MAX
(l,8)

PIN 1
IDENT

1

I

J 1_
I

0.070 MAX.
0,8/

-.-L r - - - - - - - ,

02OOMAX~.
15,1)

--r

---I

U

~

1-012,51
100

---I

100
1- 012,5)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

8-1

VFQ SERIES
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, pin 4 to pin 14 .•........•....
Input Current, pin 3 .........•..............
Output Voltage, pins 8 to 10 •••.......••.....
Reference (pin 7) to - Vos .••..•..•••..•.••..

VFQ-l
18 Volts
±10 mA
+25 Volts
± 1.5 Volts

VFQ-2

VFQ-3

FUNCTIONAL SPECIFICATIONS
Typical at 2SoC, ± SV supplies, - SV ref., unless otherwise noted.
INPUTS
Input Current Range .••.•••..••...••..•....
Input Current Overrange, max ..•.............
Input Offset Voltage, max.' ......••......•••
Reference Input. ••...•.•.....••.•..•...•..

Otol°itA

··

··

+50 itA
±50mV
±50mV ±100mV
Negative Voltage Within ± 1.5V of
negative supply

OUTPUTS
Type Outputs ...................•........•
Pulse Output, 8in 8 •......•.•..•••.......•.
Square Wave utput, pin 10 ....••........••.
Output Logic Levels •...••.......•.........

Open Collector NPN
Negative Going, 3 "sec. pulses at fo
Square Wave at fo/2
VOUT ("0") " + OAV at - 10 mA
Voud"l") = +Voo

PERFORMANCE
Linearity, 10 kHz Full-Scale, max. ............
Linearity, 100 kHz Full-Scale, max ............
Gain Tempco, max .........................
Zero Tempco, max ........•••••.....••.....
Full Scale Accuracy, before trim ....•....•.•.
Output Settling Time, 0.01 % ................

0.01%
0.25%
0.05%
0.25%
0.08%
0.5%
40 ppm/oC
40 ppm/oC 100 ppm/oC
SO "V/oC
50 "'floC 100 ,,;V/oC
±10%
2 Pulses of New Frequency

SPECIFICATIONS AS FIV
0.05%
Nonlinearity, max.' .........•..............
Input Frequency Range ..................... 10Hz to 100 kHz
Input Voltage, min. ...••..••...••...••.•••.
± OAV
Input Voltage, max. . . . . . . . . . . • . . . . . . . . • . . .. - 2V to + Voo
Input Pulse Width, Negative pulse, min. .......
O.S f'Sec.
Input Pulse Width, Positive pulse, min. ••• . . • . .
5.0 "sec.
Output Voltage Range> • . . . • • . . . . . . . • . . • . • .. OV to ( + Voo - 1)
Output Load, min. . . • . • • . . . • . . . • • . . . • • . . • . .
2 kO

0.02%

0.25%

··
··
·

···
·

POWER REQUIREMENTS
Positive Supply (pin 14) ....................
Negative Supply (pin 4) .....•.•.....•....•..
Quiescent Current, max. 4 VFQ-l C, 2C •.......
VFQ-1R ...........
VFQ-3C ...........

+4.0V to +7.5V
-4.0V to -7.SV
±4 mA
±6 mA
±10 mA

PHYSICAL/ENVIRONMENTAL
Operating Temperature Range:
Suffix C ..•.......••...••..•...••....•...
Suffix R ••..•.•....•.......•...•...•....
Storage Temperature Range ................
Package, C Suffix .....•............••..•..
Package, R Suffix ••..•••.....••.......••..
• Specifications same as VFQ-1.

DoC to + 70 0 e
-2SoC to +8SoC
-65°C to + 150°C
14 pin Plastic DIP
14 pin Ceramic DIP

·

TECHNICAL NOTES
1. To calibrate the VFQ as a V/F converter, connect as shown in the diagrams. Connect a precision voltage
source (such as DATEL DVC-8500) to
the input resistor. Connect a 5 digit
counter, with time base set to one second, to the output (pin 8).
Zero. Set the voltage reference to
+ O.OlV and adjust the zero adjust potentiometer for an output
frequency of 10Hz (for 10kHz
FS) or 100 Hz (for 100 kHz FS).
Gain. Assuming the 10V FS input, set
voltage
reference
to
the
+ 10.000V and trim the value of
Rl to give an output frequency of
10,000 Hz (for 10kHz FS) or
100,000 Hz (for 100 kHz FS).
2. The two outputs (pins 8 and 10) are
open collector NPN transistors for easy
interfacing to a variety of standard logic
circuits. A pull-up resistor must be used
as shown in the diagrams. The resistor
may be tied to any voltage up to + 18V,
which can be separate from + Vdd.
3. Note that the negative reference voltage must be within ± 1.5V of the negative supply (- V55)' For a given fullscale output frequency the value of C2
is dependent on the negative reference
voltage.
4. Note the minimum-maximum waveform requirements for the input when
using the VFQ as a frequency-tovoltage converter. See "Input Waveform Limits" diagram. The minimum
± O.4V must be observed as well as the
minimum widths for both positive and
negative going portions of the waveform. If the input waveform exceeds the
maximum amplitude limits, an input
resistor and back-to-back clamping
diodes should be used as shown in the
connection diagram.
5. For FN operation, the input signal must
cross through zero in order to trip the
comparator. In order to overcome the
hysteresis the amplitude must be
greater than ± 200 mV. If only a unipolar input signal (Fin) is available, it is
recommended that either an offset circuit using resistors be used or that the
signal be coupled in via a capaCitor.

FOOTNOTES:

1. Before Trimming, liN
2. 10 Hz to 100 kHz
3.RL"2kll
4. V,N = -O.1V

8-2

= O.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

VFQ SERIES
PERFORMANCE CHARACTERISTICS
MAX. NONLINEARITY - 100 KHZ FULLSCALE

MAX. NONLINEARITY - 10 KHZ FULLSCALE

0.25

II"
I I/VFO.3

d.'

~

0

0.15

~

/

~

;r.
~

/

0.1

Ii:

;OJ

~

«

~

I

;r.
~

/,/

:>

0.3

fFO"/~1\

;OJ
Z

:J
Z

\;

D.'

z

~

:>

I

!

0

\

I/VFO.3

/

0.4

Ii:

/VFO.,,,.)

0.05

n

w

J

I

/

z

:J
z
0

z

0.5

II

0.1

,,/VFO·2
0.01

"

/

0
10

100

1000

10K

10

100

1000

10K

100K

OUTPUT FREQUENCY, HZ

OUTPUT FREQUENCY, HZ

OUTPUT WAVEFORMS

PULSE
OUT

VDD
+

3F",sec

o _______

\ typ,)

u

F~F'N~
UlJ
~lL

fL

u

=

-v

+VDO _ _ _- ,

NOTE:

SQ. WAVE
OUT

For FIV operation, il only a unipolar
input signal is available, an offset
circuit using resistors should be
used or the signal should be capacitor coupled.
.

0----INTEGRATOR
OUTPUT

INPUT WAVEFORM LIMITS (FIV CONVERTER)

~ '00 -------------~~~~---- -- ------

--l

VFQ FORMULAS

lOUT

R,

+O.4V--------

---

-------------

---

________

1__

=~
R,

X

__
1_

VREF

C,

V,N (max.)
10JlA

82K::;; R,::;; 120K
MAX

-'~ : :~:: ~-~ ~- : ~ ~ - ~- -~ ~-~-:- :~ - - - ~ ~- -j-

3C, ::;; C, ::;; 10 C,
C, (optimum) = 4 C,
F/V CONVERTER
VaUT

= F,N (V

REF

x C, X R1)

OUTPUT TIME CONSTANT:

T= R, C,

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

8-3

•

VFQSERIES
APPLICATION DIAGRAMS
BIPOLAR OPERATION (0 to 20 kHz)

NORMAL CONNECTION-10 kHz FULL SCALE

10K

+5v
REF.

11

e,

12

l000pF

1 MEG!

s,.A

~foOUT

12

~fo/20UT

1MEG

INPUT
(0 TO +10V)

11

~foOUT

<5V

INPUT

h5V)

R,

-uL f o!20UT

10
R11MEG.

+5V

vFa

;s;::

S10K

S10K
50K

-5V

OFFSET

REF.

AOJ

10K

50K

-5V

ZERO

REF.

ADJ.

10K

-5V

-5V

-5VOC

-5VOC

NOTE: fOR l00kHl FULL SCALE, C,

co

'IOOpf AND C.

~

20 pF

SINGLE SUPPLY OPERATION
+VOD

( ... 10VDC TO + 15VDC)

FREQUENCY TO VOLTAGE CONVERTER
(0 to 100 kHz INPUT)

+-__-".---,
10K

+10v

+5VOC

REF.

~foOUT

1;""'

+5v

"K

INPUT
fO

TO +10V)

"

FReOUENCY
IN

e,

VFa

-5V

REF

47pF

S10K

R,

50K

ZERO
AOJ

10K

180K

e,

lOOK

51lK

12
>_-.,f\1V'--'--412_~_~.::.I1oij~--4--<>
OUTPUT
'(0 TO + 4.2V)
1000

5K

pF
2.2K

+Voo

R,
lOOK

5.1V

ZENER

-5VOC
NOTE: IF THE AMPlITUOE OF THE INPUT WAVEFORM EXCEEDS
THE speCIFIED MAXIMUM. THE FOLLOWING INPUT CIRCUIT
SHOULD BE ADDED

TEMPERATURE TO FREQUENCY CONVERTER
... 1.2V REF. (LM113)

+5VDC

=Vgo
14

10K

VFa

ORDERING INFORMATION

-5VDC

NOTES:
1, Vgo IS THE EXTRAPOLATED ENERGY·BAND·GAP VOLTAGE FOR
SILICONATO'K.
2. R IS A STABLE METAL FILM RESISTOR (50 PPMI'C OR BETTER I
ITS EXACT VALUE SHOULD BE FOUND BY ADJUSTING ITTO
GIVE AN OUTPUT FREQUENCY OF 10 X 'K IN HZ FOR
A KNOWN TEMPERATURE SUCH AS 300'K. IT WILL THEN
BE CORRECTLY CALIBRATED FOR ALL OTHER TEMPERATURES.
3, WHEN PROPERLY IMPLEMENTED THIS CONVERTER IS
ACCURATE TO 10 K,

8-4

MODEL NO_

OPERATING
TEMP. RANGE

LINEARITY

VFQ-1C
VFQ-1R
VFQ-2C
VFQ-3C

O°C to +70°C
-25°C to +85°C
O°C to +70 o C
O°C to +70°C

0.05%
0.05%
0.01%
0.25%

ACCESSORIES
Part Number

Description

TP50K

Trimming Potentiometer

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

POWER PRODUCTS
DATEL manufactures a wide range of power supplies for data conversion and general purpose applications. We offer quality products, competitive pricing, and fast delivery. Power Supplies are a
major part of DATEL business, not just a convenient sideline.
DATEL's comprehensive line of dc-to-dc converters feature:
1-, 3-, 4.5-, 5-, 10-, and 15-Watt devices
Single, Dual, and Triple Output versions
High Efficiency
Miniature Size
Wide Input Voltage Range Models
DATEL also offers compact modular AC line-operated supplies for
circuit board and chassis mounting. Single, Dual, and Triple output
versions are available. Included in this line are switching supplies
and plug-in power adapters.

.i
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

9-1

Single Output Line Operated
Power Modules

SPECIFICATIONS, 25°C
Output Voltage
Output Voltage Accuracy
Rated Output Current
Line Regulation, max.
Load Regulation, max.
Temp. Coefficient, max.
Output Ripple, RMS max.
Output Impedance, max.
Trans. Recovery Time, max.
Isolation Resistance, min.
Isolation CapaCitance, max.
Breakdown Voltage, min.
Operating Temp. Range
Storage Temp. Range
Case Material
Module Size, Inches
Module Size, Millimeters
Module Weight
Case/Pin Configuration
Mating Socket

UPM-5/250
5V dc
±1%
250mA
0.05%
0.1%
0.02%/OC
1 mV
0.050
50 !'Sec.
100 Meg.
250 pF
1500 VAC

Phenolic
3.5 x 2.5 x 0.875
88,9 x 63,5 x 22,2
14 oz. (397g)
C1
MS-7

UPM-5/500
UPM-5/1000
5V dc
5V dc
±1%
±1%
500mA
1.0A
0.05%
0.05 0Al
0.1 oAl
0.1%
0.02%/OC
0.02%/OC
1 mV
1 mV
0.050
0.010
50,.sec.
50 !'Sec.
100 Meg.
100 Meg.
250 pF
250 pF
1500 VAC
1500 VAC
- 25 °C to + 71°C (No Derating)
-25°C to +85°C
Phenolic
Phenolic
3.5 x 2.5 x 0.875
3.5 x 2.5 x 1.25
88,9 x 63,5 x 22,2
88,9 x 63,5 x 31,8
18 oz. (510g)
14 oz. (397g)
C1
C2
MS-7
MS-7

UPM-5/1000B
5V dc
±2%
1.0A
0.25%
0.25%
0.02%/OC
1 mV
0.010
50 p.Sec.
100 Meg.
250 pF
1500 VAC

Phenolic
3.5 x 2.5 x 1.25
88,9 x 63,5 x 31,8
18 oz. (510g)
C2
MS-7

FOOTNOTES:
1. For UPM-512000 operating temperature range should be restricted for a maximum case temperature of SO°C in use.

9·2

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

This line of single output voltage regulated
dc power supplies features five 5 volt output models with output currents from 250
rnA to 2 amperes. In addition, there are 4
other models with 6V to 15V outputs. All
outputs have current limiting short circuit
protection. Temperature coefficients are
0.02%/OC and output ripple voltage is 1 to
2 millivolts RMS.

INPUT VOLTAGE SPECIFICATIONS
Standard input specification:
115 VAC ± 10% at 60-440 Hz

UPM-S/2000
SV dc

UPM-6/1S0A
6V dc

±1%
2.0A
0.05%
0.1%
0.02%/OC

±1%
150 rnA
0.05%
0.1%
0.02%/OC

1 mV
0.0050
50 !,sec.
100 Meg.
250 pF
1500 VAC

1 mV
0.050
50 !,sec.
100 Meg.
250 pF
1500 VAC

'CD
Phenolic
3.5 x 2.5 x 1.56
88,9 x 63,5 x 39,6
24 oz. (680g)
C3
MS-7

UPM-9/100A
9V dc
±1%
100 rnA
0.05%
0.1%
0.02%/OC

UPM-12/100A
12V dc

UPM·1S/100A
15V dc

±1%
100 rnA
0.02%
0.05%
0.02%/oC
2 mV
0.010
50 !,sec.
100 Meg.
250 pF
1500 VAC

±1%
100 rnA
0.02%
0.05%
0.02%/oC
2 mV
0.010
50 !,sec.
100 Meg.
250 pF
1500 VAC

2 mV
0.010
50 "sec.
100 Meg.
250 pF
1500 VAC
- 25°C to + 71°C (No Derating)
-25°C to +85°C
Phenolic
Phenolic
Phenolic
3.5 x 2.5 x 0.875
3.5 x 2.5 x 0.875
3.5 x 2.5 x 0.875
88,9 x 63,5 x 22,2
88,9 x 63,5 x 22,2
88,9 x 63,5 x 22,2
14 oz. (397g)
14 oz. (397g)
14 oz. (397g)
C1
C1
C1
MS-7
MS-7
MS-7

•

Phenolic
3.5 x 2.5 x 0.875
88,9 x 63,5 x 22,2
14 oz. (397g)
C1
MS-7

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

9-3

Dual Output Line Operated Power
Modules

SPECIFICATIONS, 25°C
Output Voltage
Output Voltage Accuracy
Rated Output Current
line Regulation, max.
Load Regulation, max.
Temp. Coefficient, max.
Output Ripple, RMS max.
Output Impedance, max.
Trans. Recovery Time, max.
Isolation Resistance, min.
Isolation Capacitance, max.
Breakdown Voltage, min.
Operating Temp. Range
Storage Temp. Range
Case Material
Module Size, Inches
Module Size, Millimeters
Module Weight
Case/Pin Configuration
Mating Socket

BPM·5/250
±5V de
±1%
+250 mA
0.05%
0.1%
0.02%/oC
1 mV
0.050
50 !6,SV dc.
Contained on chip are a series dc power
supply regulator, RC oscillator, voltage
level translator, four output power MOS
switches, and a unique logic element
which senses the most negative voltage in
the device and ensures that the output Nchannel switches are not forward biased.
This assures latch-up free operation.
The oscillator, when unloaded, oscillates
at a nominal frequency of 10kHz for an input supply voltage of S.O volts. This frequency can be lowered by the addition of
an external capacitor to the OSC terminal,
or the oscillator may be overdriven by an
external clock.
The LV terminal may be tied to GROUND
to bypass the internal series regulator and
improve low voltage operation. At medium
to high voltages ( + 3.S to + 10.0 volts), the
LV pin is left floating to prevent device
latch-up.
Typical applications for the VI-7660 will
be data acquisition and microprocessor
based systems where there is a + SV dc
supply available for the digital functions
and an additional - SV dc supply is required for the analog functions. The
VI-7660 is also ideally suited for providing
low current, - SV dc body bias supply for
dynamic RAMs.

J
GROUND

MECHANICAL DIMENSIONS
INCHES (mm)

f-,-',8""""'.L...LL,.,\ - ,
0.325

0.310

(8,255)

(7,874)

~I

4...,L

LI9~2)J

INPUT/OUTPUT CONNECTIONS

?'~4h
f
~
1_O'J25

0.175

(4,4)

0.500 MtN

OLEAOS./]O
0.017 TYP

0OO~

PIN
1
2

3
4
5
6
7
8

FUNCTION
N.C.
+CAP
GROUND
-CAP
OUTPUT
LV
OSCILLATOR
+Vs (Input)

BOnOM
VIEW

The VI-7660 operates over the commercial
O°C to + 70°C temperature range. It is
available packaged in either an a-pin
TO-99 can or an a-pin plastic DIP.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

9·25

VI-7660
TECHNICAL NOTES
1. For improved low voltage operation, the
"LV" terminal (Pin 6) should be connected to ground (this disables the
regulator). For supply voltages greater
than 3.5V, the "LV" terminal must be left
open to insure latch-up proof operation.
Never exceed the maximum rated supply
voltage ( + Vsl.
2. The output (Pin 5) should not be shorted to
the supply voltage pin (Pin 8) for supply
voltages above 5.5V for extended periods
of time. However, transient conditions, including start-up are acceptable.
3. If using polarized capacitors for charge
pumping and charge reservoir functions,
the positive terminal of C1 must be connected to Pin 2 of the VI-7660 and the
positive terminal of C2 must be connected
to ground. (See typical connection
diagrams, page 4.)
4. To operate with voltages up to 10V over
temperature without the danger of latchup, a general purpose diode (Dx) must be
added in series with the devices output.
The affect of the diode (Dx) is the reduction of output voltage by one diode drop
(O.6V).
Dx must be used in high-voltage elevated
temperature applications. The device will
function properly in the specified temperature range with only the 2 external
capacitors, provided the supply voltage
does not exceed 6.5V at 70°C. Exceeding
this maximum could result in destructive
latch-up of the device. (Refer to the
OPERATING VOLTAGE VS TEMPERATURE graph and the typical connection
diagrams.)
5. The oscillator operates (unloaded) at a
nominal frequency of 10 kHz for an input
supply voltage of 5.0V. This frequency can
be lowered by the addition of an external
capaCitor to the OSCILLATOR terminal
(Pin 7) or the oscillator may be overdriven
by an external clock. For large values of
the OSCILLATOR CAPACITOR, (> 1000
pF), C, and C2 should be increased to 100

ABSOLUTE MAXIMUM RATINGS
10.5V

Power Supply Voltage ..••.•..•••.•...••.....•
Input Voltage' LV, OSC (Pins 6,7) •••..•..•••••..

~: ~ ~:~~ :::::::::::::::::::

-0.3V to (Vs +0.3V)
(+Vs - 5.5V) to (+Vs +0.3V)
20~

Input Current LV (Pin 6) •....••••.•..••••...•..
Output Short Circuit Duration" ••••...•...••....•
Power Dissipation: VI-7660-13 ..•••....•••..••..
VI-7660-2 .••.....•...•.....•

Continuous
300 mW
500 mW

FUNCTIONAL SPECIFICATIONS
Typical at 25·C, +5V Supply, Cosc = 0, unless otherwise noted.
INPUT CHARACTERISTICS
500~

Supply Current, Max' ••.••••.••••..•..•.••...•
Supply Voltage Range High, min.- •...•...•......
max ••.•.••••••...••
Supply Voltage Range Low, min .•••..........•..
max •....•..••..•...
Supply Voltage Range High, min •••••......•••••.
max ••...•........•.
Supply Voltage Range Low, min.' •••..•••.••...•
max ••...•..........

3.0V
6.5V
1.5V
3.5V
3.0V
10.0V
1.5V
3.5V

PERFORMANCE
Output Source Resistance, max •••••..........•.
Oscillator Frequency ..•...•..•........•..••..
Voltage Conversion Efficiency, min ••...•..••..•.
Power Efficiency, min ••.••••••••...••••.•....•
Oscillator Impedance, +V. = 2V ...............
+V. = 5V

1000
10 kHz
97%
95%
1 MO
100 kO

...............

PHYSICAUENVIRONMENTAL

.................

Operating Temperature Range
Storage Temperature Range ••..•••.•....•.....
Soldering Temperature, (10 sec) .•••.•....•...•.

O·C to + 70·C
- 65·C to + 150·C
300·C

FOOTNOTES:
1. Do not connect any terminal to voltages greater than + V, or less than ground or destructive latch·up may
occur. It is recommended that no inputs from sources operating from external supplies be applied prior to

"power up" of the device.
2. For + V, greater than or equal to S.SV.
3. Derate linearly above SO·C by S.S mW/·C:
4.RL=oo

S.
6.
7.
8.
9.

O·C to + 70·C, RL = 10 kIl, LV open and Ox out of circuit.
O·C to + 70·C, RL = 10 kll, LV open and Ox in circuit.
O·C to + 70·C. RL = 10 kll, LV to ground, Ox in circuit.
O·C to + 70·C, RL = 10 kll, LV to ground. Ox out of circuit.
lout = 20 rnA. TA = 2S·C. 1201l max., over O·C to + 70·C. 4001l max over O·C to + 70·C. +V,=2V.
lout = 3 rnA, LV to ground.
10. RL = S kll.

PERFORMANCE

J. 2

w

I

~

§ -3
-4

-5 , /
'0

,/
SLOPE
20

30

2V

\
\

\

~

50

60

LOAD CURRENT IL(mA)

9-26

+Vs =

55q
40

1\

TA:: +25°C

:
:
:

/

~ -2

o

+2

70

80

-2

.....-

o

-

........ V

./
I...-::

r

p

°1

5
,'

2
3
4
LOAD CURRENT IL(mA)

7

8

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

VI-7660
PERFORMANCE
OUTPUT SOURCE RESISTANCE AS
A FUNCTION OF TEMPERATURE

OUTPUT SOURCE RESISTANCE AS A
FUNCTION OF SUPPLY VOLTAGE
10k

~A

UJ

350

l

1+25 C_

S

()

= 1

~A

()

z

z 250

f:!

f:!

!!.l1000

II)

\

(/)

UJ

a:

Si
a:

UJ
()

200

-

UJ

1i:::>

a:

:::>

5l

tOUT
300

UJ

100

I

V'N 1 2V

o
II) 100

........

>:::>
a.

150

>-

:::>

:=:::>

S
o

50

o

10

o

2

3

6

7

V'N,5V

o

O°C + 12.5°C + 25°C + 37.5°C + 50°C + 70°C

8

TEMPERATURE (0C)
SUPPLY VOLTAGE (+ Vs)

UNLOADED OSCILLATOR FREQUENCY
AS A FUNCTION OF
TEMPERATURE

SUPPLY CURRENT & POWER CONVERSION
EFFICIENCY AS A FUNCTION OF
LOAD CURRENT

~

>-

r- .........
90

zw

80

u:

70

"w

z

60

Q

50

()

G


0

()

II:

w

~

10

90

r

~

80

" "-[\

/
/

V

TA :::: +25°C
+Vs:::: +5V -

/
20

30

40

50

!:(
()

w
::> 14

IEw
0

50

12

II:

40

LOAD CURRENT I, (mA)

c

:0
:0

m

z
....
-;

"3

20 J!
10

60

~TAI=+2°C

80

60

0
10

it

~ 16

30
fose ~ 1 kHz _

ft--.....

"0
"0

40

/

(f>

C

~"-

G 70

z

iii
w

II:

g
j

M

>

0 ............

+Vs = +-;- '-B
6

o0 c + 12.5 0 C + 250 C + 37.5 0 C + 50 0 C + 70 0 C

60

z

30

()

20

0

II:

w

~"-

10
0
0

1\

~ lK

"\

::>

e:

§ 10

1.0

10

100
Cos< (pF)

1000

10k

~

B.O

~
"3

~

6.0

4.0
2.0

./

OmA

1.5

3.0

4.5

6.0

7.5

9.0

.'

T", :::: +25°C

9B

lOUT:::: 1 rnA

~
1
lOUT:::: 15 rnA

90

88

-

86

()

84

II:

:

~

I"-..

96
94

z
o

_;&",,= +25°C

10.0

./

92

ffi

5V

::0

/

:t
>

·+Vs

~

g

12.0

/

~

iii

II: 100

= +2.0V

"0

14.0

POWER CONV£RSION EFFICIENCY AS A
FUNCTION OF OSC. FREQUENCY

z
o

5l

(f>

c

16.0

..... ~
./1'\.

OPERATING VOLTAGE AS A
FUNCTION OF TEMPERATURE

it

w

1B.O

-""

LOAD CURRENT I, (mA)

o

j

-......

I'

l100

10K

l

g
~

+Vs

TEMPERATURE

FREQUENCY OF OSCILLATION
AS A FUNCTION OF
EXTERNAL OSC. CAPACITANCE

20.0

~
>- 90
()

70
50

\

1/

20

_100

100

100

SUPPLY CURRENT & POWER CONVERSION
EFFICIENCY AS A FUNCTION OF
LOAD CURRENT

2

o +Vs:::.
100

+5V

lk

10k

OSC. FREOUENCY lose (Hz)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

9-27

VI-7660
TYPICAL CONNECTION AND APPLICATION
CASCADING VI-7660's

NEGATIVE VOLTAGE CONVERTER

(ARITHMETIC CASCADING)

0,

VI·7660

r--j+-,
~

___ j I

0

OUTPUT

101'~C2
6 ,

Ox must be included
for proper operation at
high voltages (>6.5V)
and/or elevated temperatures.
'Ground if + Vs <3.5V

VI-7660's may be cascaded for increased output
voltage. The practical limit is 10 devices for light loads
due to the finite efficiency of each device. The output
equation is as follows:
VOUT = -n (Vs)
where "n" is the number of devices cascaded. The
output resistance is the sum of each VI-7660's ROUT'

This application shows the typical connections to provide a negative supply where a positive supply is
available. The output characteristics of this circuit are
those of a nearly ideal voltage source in series with
700. Thus, for a load current of - 10 mA and a supply
voltage of +5V, the output voltage will be -4.3V. The
output equations are as follows:
VOUT without Ox
VOUT = -Vsfor +Vs = 1.5Vt06.5V
VOUT with Ox
VOUT = -Vs + VFDX for +Vs = 6.5Vt010.0V
Where: VFDX = Forward Voltage across Ox
The dynamic output impedance due to the capacitor
impedance is approximately 1/wC where:
C = C, = C2
Giving _1_ =
1
= 30
wC
2fI fose x 10- 5
For C = 10 p.F and fose = 5 kHz (% of oscillator
frequency)

+v,

c,

PARALLELING VI-7660's

VI·7660

=

0,

EXTERNAL CLOCKING

,.
CMOS

GATE

VI-7660's may be paralleled to reduce output
resistance. The reservoir capacitor, C2, serves all
devices; however, each device requires its own pump
capacitor (C,).
ROUT (of VI-7660)
Output Resistance =
n (number of devices)

The oscillator frequency may be increased by overdriving the oscillator from an external clock. The 1 kO
resistor is used to prevent latch-up when using CMOS
logic. If TTL is used to over drive the oscillator, a 10 kO
pullup resistor to + Vs is required.

9·28

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

VI-7660
APPLICATIONS
DECREASING OSCILLATOR FREQUENCY

POSITIVE MULTIPLICATION
case
+5V

,)----t't--+--Q

OUTPUT

8

Conversion efficiency can be maximized by lowering
the oscillator frequency. This is achieved by connecting an additional capacitor Cosc as shown. Lowering
the frequency will cause an increase in the impedance
of C, and C2 . This can be overcome by increasing the
values of C, and C2 by the same factor that the frequency has been decreased.

VH660

10 pF

VI·7660

5

3

5

+

OUT -15V
OUTPUT

10P~C'

This circuit will generate -15V dc from + 5V dc using two VI-7660's. The two devices are connected in
cascade fashion with Pin 3 of device #2 connected to V1N rather than ground. The geometric increase performed by this circuit is good until the input voltage limit is reached, at which point, arithmetic cascading
should be utilized. Cascading is recommended for use in light load applications.

+5V

POSITIVE AND NEGATIVE MULTIPLICATION

..--------I*"----t-------:-t-----{) + 15V (out)

VH660
1 Mil

VH660
;)-t------~~--t_-----~o -5V

8

VH660

l.5)-+I--t---{)

10p~

-15V OUTPUT

c,

This application shows a combination of positive and negative multipliers. This circuit is an extension of the
above application providing ± 15V dc supplies from a + 5V dc input. The 1 MO resistor on Pin 6 of device
number 1 is used to avoid startup problems by forcing the internal regulator on.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

9-29

VI-7660
EFFICIENT SUPPLY SPLITTING

t

Vs

VJ.7660 LV [ID----.

1 Mil

GND
@

r'---------I~----O

Vout =

+:j-'

cl+C,

100~~

In this application, the VI-7660 is connected as a voltage splitter. Note the "normal" output pin is connected to
ground and the "normal" ground pin is used as the output. (The switches that allow the charge pumping are
bidirectional; therefore, charge transfer can be performed in reverse as well as forward). The 1 MO resistor is
used to avoid start-up problems by forcing the internal regulator on.
An application for this circuit would be driving low voltag9 ( ± 7.5V dc) circuits from
voltage logic from 9V to 12V batteries.

THREE-STAGE

VIN

± 15V dc supplies, or low

+ 15V TO -15V CONVERSION

+ 15V

,------+-------0

+15V

The circuit shown here will convert + 15V dc to -15V
dc using three VI-7660's. Device number 1 acts as a
voltage splitter. Device number 2 is a voltage converter
and device number 3 is configured as a voltage
doubler. The output impedance of this circuit is approximately 2500.

1 Mil

'-------..--------0' + 7.5V

VJ.7660

ORDERING INFORMATION
ID--.,-+.......--o
50~a: c,

9-30

-15V

MODEL NO.

PACKAGE

VI·7660-1
VI-7660-2

8-PIN PLASTIC DIP
8·PIN TO·99

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

VR·182 Series
Precision Bandgap
Voltage References
FEATURES
• 2.455V dc Output
• Tempcos to 30 ppm/DC
• 2-to-120 mA Reference current
• ± 1.4% Tolerance
• Two terminals
• Low cost

+

GENERAL DESCRIPTION
The VR-182 series precision references
are two-terminal monolithic bandgap
devices which feature 2.455 volts output
with tight tolerance and low tempcos.
Temperature coefficients are 100, 50, and
30 ppm/DC respectively for Models
VR-182A, VR-182B, and VR-182C.
An active regulator around the bandgap
circuit results in 0.1 ohm typical dynamic
impedance with a wide 2-to-120 mA
reference current range. Furthermore, the
dynamic impedance is flat to 4 kHz rising
to only 1.2 ohms at 50 kHz. Other
specifications include ± 1.43% voltage
tolerance, 10 (LV RMS output voltage
noise, and 10 ppm per 1000 hours long
term stability.
These low cost references are easy to use
and are ideal for use with monolithic AID
and D/A converters which do not have internal references. They are also useful in
voltage regulator circuits, switching power
supplies, comparator circuits, and other
analog signal processing applications.
The low 2.455 reference voltage allows
these references to be used with 5V dc
logic supplies and other power supply
voltages as low as 3.5V dc. In many cases
they give improved performance over
higher priced Zener diode references
which require higher supply voltages and
have much higher dynamic impedances.
The VR-182 devices are supplied in a twolead hermetically sealed TO-18 package
and operate over the ODC to + 70 DC
temperature range.

MECHANICAL DIMENSIONS
INCHES (MM)

~

CONNECTION

15,61
0'220~

I_O.185J
[14,711

+Vs

1-----.+..--1

--L

R

0.19

14,81

IT
0.5 MIN.
112,71

+

VOUT

BOTTOM
VIEW

~-G+
I

-l1 120.1, 5 1 -

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

9-31

VR-182 SERIES
FORWARD CHARACTERISTIC

ABSOLUTE MAXIMUM RATINGS
Reference Current. . . . . . . . . . . . . . . . . . . •. 120 rnA"
Dissipation ........................... 300 mW

1000

FUNCTIONAL SPECIFICATIONS
Typical at 25°C, IREF = 2 mA unless otherwise noted.

100

1
z>w

OUTPUT

a:
a:

Output Voltage ....................... 2.455V
Output Voltage Tolerance, % ............ ± 1.43%
Output Voltage Tolerance, mV ........... ±35 mV

:::J

u

10

o
a:

~

a:

PERFORMANCE

ou.

Reference Current Range ...............
Temperature Coefficient, ppm/oC
VR·182A ...........................
VR·182B ...........................
VR·182C ...........................
Dynamic Impedance, DC ...............
Dynamic Impedance, 50 kHz ............
NOisevOlta~e,l Hz to 10Hz .............
Long Term tability....................

2 to 120 rnA'
60 typ., 100 max.
35 typ., 50 max.
23 typ., 30 max.
0.1 typ., 0.2 ohm max.
1.2 ohms
10"V RMS
± 10 ppm/lOOO hours

,"

0.1

004

0.8

1.2

1.6

2.0

204

2.8

FORWARD VOLTAGE

PHYSICAUENVIRONMENTAL
Operating Temperature Range ........... OOC to + 70°C
Storage Temperature Range .. : ......... -55°C to +150°C
Package Type ........................ 2-lead TO-18
• Derate the 120 rnA by 1 mA/oC above 25°C

DYNAMIC IMPEDANCE
10 _

__

APPLICATION
VR·182 series voltage references are recommended for use with
the following DATEL products:
AID Converters
ADC·EK Series
ADC-ET Series

Application Equation: R

D/A Converters
DAC·08B
DAC·IC8B
DAC-IC10B
= Vs-2.455
IL + IR

1.0~~~

,

Io'"~~

-20 A

~""""""'''''''~_'''''''''''''_!C?~::--....L..JAt_J.L~luliuil.!-:!l

0.1
0.1

1.0

=

10

100

FREQUENCY 1kHz)

Vs
Supply Voltage
IR = Reference Current
IL = Load Current
CONNECTION TO DATEL ADC-EK OR
ADC·ET SERIES AID CONVERTERS

13
124K
l%MF

ADC·ET
OR

ORDERING INFORMATION

EK SERIES

1.24K

l%MF

MODEL

TEMPCO/MAXIMUM

VR·182A
VR-182B
VR-182C

100 ppm/oC
50 ppm/oC
30 ppm/oC

-5VDC

9-32

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339·3000fTLX 174388/FAX (508) 339·6356

INSTRUMENT
PRODUCTS

PANEL MOUNT
THERMAL PRINTERS

;1,1.

MODEL

COLUMNS

INPUT
INTERFACE

POWER
(Note 1)

DPP-Q7

7

BCD

115/230 VAC

Numeric
(decimal or hex)
plus sign

APP-20Al

20

Parallel

115/230 VAC

APP-20Dl

20

Parallel

+12 Vdc

APP-20A21

20

RS-232120 mA loop

SPECIAL FEATURES

PAGE

A

Simple interface to DATEL DPMS

10-32

96 char ASCII

A

Inverted, tall character options

10-5

96 char ASCII

A

Inverted, tall character options

10-5

115/230 VAC

96 char ASCII

A

Inverted, tall, condensed character options

10-8

CHARACTER SET

CASE

APP-20D21

20

RS-232/20 mA loop

+12 Vdc

96 char ASCII

A

Inverted, tall, condensed character options

10-8

APP-20A3

20

IEEE-488

115/230 VAC

96 char ASCII

A

Inverted, tall character options

10-12

APP-20D3

20

IEEE-488

+12 Vdc

96 char ASCII

A

Inverted, tall character options

10-12

MPP-20A

20

RS-232/Parallel

115VAC

127 char ASC II

A

Inverted, tall, enhanced character options

10-36

MPP-20D

20

RS-232/Parallel

+12 Vdc

127 char ASCII

A

Inverted, tall, enhanced character options

10-36

MPP-20E

20

RS-232/Parallel

230 VAC

127 char ASC II

A

Inverted, tall, enhanced character

o~tions

10-36

APP-48Al

48

Parallel

115VAC

192 char ASCII

B

Inverted character option

10-15

APP-48Dl

48

Parallel

+12 Vdc

192 char ASC II

B

Inverted character o[ltion

10-15

APP-48A2

48

RS-232

115/230VAC

192 char ASCII

B

Inverted character option

10-18

APP-48D2

48

RS-232

+12 Vdc

192 char ASCII

B

Inverted character option

10-18
10-22

APP-48A3

48

IEEE-488

115/230 VAC

192 char ASCII

B

Inverted character option

APP-48D3

4B

IEEE-488

+12 Vdc

192 char ASCII

B

Inverted character optio-,,---

10-22

APP-48A4

48

RS-232

115/230 VAC

192 char ASCII

B

132-character buffer lor continuous through[lut

10-18

APP-48D4

4B

RS-232

+12 Vdc

192 char ASCII

B

132-character buffer for continuous throughput

APP-M20Al

20

Parallel

115/230 VAC

96 char ASCII

C

10-26

APP-M20Dl

20

Parallel

+12 Vdc

96 char ASCII

C

10-26

APP-M20A21

20

RS-232

115/230 VAC

96 char ASCII

C

APP-M20D21

20

RS-232

+12 Vdc

96 char ASCII

C

APP-M20A3

20

IEEE-4BB

115/230 VAC

96 char ASCII

C

APP-M20D3

20

IEEE-48B

+12 Vdc

96 char ASCII

C

10-26

APP-M48Dl

4B

Parallel

+12 Vdc

192 char ASC II

D

10-28
10-28

APP-M48D2

48

RS-232

+ 12 Vdc

192 char ASC II

D

APP-M48D3

4B

IEEE-48B

+12 Vdc

192 char ASC II

D

APP-M48D4

4B

RS-232

+12 Vdc

192 char ASCII

D

10-18

10-26
10-26

Hardened for shock, vibration and
humidity (mobile)

10-26

10-2~

Hardened; 132-character buffer for continuous
throughput

10-28

NOTE 1: 100 VAC versions available for most models ("J" version); European line cords also available ("E" version), Consult factory.
CASES:
A ~ 4.44" W x 2.76" H x B.OO" D
B

~

8.20" W x 2.84" H x B.14" D

C

~

5.36" W x 3.47" H x B.OO" D (including mobile-mount brackets)

D

~

9.25" W x 3.25" H x 10.44" D (including mobile-mount brackets)

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-1

II

PANEL MOUNT DIGITAL PANEL METERS
MODEL

DIGITS

OISLAY

POWER

CASE

DATA

I/O

FEATURES

PAGE

OM-SOO

31/2

LED

+5Vdc

o

OM-3100L

31/2

LED

+5Vdc

B

OM-3100MIL

31/2

LED

+5Vdc

B

MIL-STD-202 for shock, vibration

10-55

OM-3100N

31/2

LED

+5Vde

A

Provisions for 4 - 20 rnA input

10-57

Low cost

10-86
10-53

OM-3101

31/2

LED

+5Vde

A

High-intensity display

10-57

OM-3103

31/2

LED

+5Vde

B

High-intensity display

10-53

OM-9100

31/2

LED

+5Vde

C

Meets NEMA 12 vibration standards

10-89

OM-3100Ul

31/2

LCD

+5 or +9V de

A

Units display; battery powered operation

10-59

OM-3100X

31/2

LCD

+50r +9V de

B

Battery powered operation

10-63

OM-9150

31/2

LCD

+5Vdc

C

Meets NEMA 12 vibration standards

10-89

OM-3100B

31/2

LED

115/230VAC

B

OM-3100U2

31/2

LCD

115VAC

A

Units display

10-61

31/2

LCD

230 VAC

A

Units display

10-61

B

OM-3100U3

10-51

OM-31 04

31/2

LED

115/230 VAC

OM-9115

31/2

LED

115/230 VAC

C

Meets NEMA 12 vibration standard

10-89

OM-9165

31/2

LCD

115/230 VAC

C

Meets NEMA"t 2 vibration standard

10-89

OM-LX3

31/2

LCD

+5V de

uneased

Uneased; battery powered operation

10-95

uncased

10-51

OM-31

31/2

LED

+5Vde

Uneased

10-49

OM-4101N

41/2

LED

+5Vde

A

High-inlensity display

10-76

OM-9200

41/2

LED

+5V de

C

Meets NEMA 12 vibration standards

10-89

OM-9250

41/2

LCD

+5Vde

C

Meets NEMA 12 vibration standards

10-89
10-89

OM-9215

41/2

LED

115/230 VAC

C

Meets NEMA 12 vibration standards

OM-9265

4 1/2

LCD

115/230VAC

C

Meets NEMA 12 vibration standards

10-89

OM-3102A

3 1/2

LCD

+5Vdc

A

Serial BCD out

Autoranging 200 mV to 200V; units display

10-65

OM-3102B

3 1/2

LCD

+5Vde

A

Serial BCD out

Autoranging 2V to 1000V; units display

10-65

OM-41000

41/2

LED

+SVde

A

Serial/parallel BCD out

High-speed sampling mode

10-68

OM-41 01 0

41/2

LED

+5Vde

A

Serial/parallel BCD out

High-intensity display

OM-4101L

41/2

LED

+5Vde

B

Serial BCD out

10-71
10-74

~~~~~-

41/2

LCD

+SVde

A

Serial BCD out

OM-4200

4 1/2

LED

+5Vde

A

Serial BCD out

OM-4102

41/2

LED

+5Vde

A

Serial BCD in

Display-only slave meter

10-78

OM-4103

41/2

LED

+5Vde

B

Serial BCD in

Display-only slave meter

10-78

OM-4104

41/2

LED

+SVde

A

Parallel/Serial BCD in

Display-only slave meter

10-80

41/2

LCD

+5Vde

A

Serial BCD in

Display-only slave meter

10-78

LED

+5Vde

A

TIL out

LED

+SVde

B

OM-4105

OM-41 06
OBM-20
PC-6

6

CASES:
A = 2.53"W x 3.34"0
B = 3.00"W x 2.15"0
3.60"W x 3.57"0
C
o 1.89"W x 1.22"0

=
=

10-2

x
x
x
x

0.94"
1.76"
1.67"
0.94"

(64
(76
(91
(48

x
x
x
x

85
55
91
31

x
x
x
x

Battery powered operation

10-82
10-84

20-segment analog bar graph display
10 megahertz counter/event timer

10-47
10-106

24mm)
45mm)
42mm)
24mm)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

PROCESS MONITORS
PM-50.1. 0- 1 ,... U:O
INPUTS
~. ~
;..
Thermocouple types J, K, T, S, B, E, N R
·6\
•.t:;;
';;';"'+.~""'"--- RTDlTh ermls
. tor
. . -~
j.'i.;
•.•.;r
Strain Gage
1~
:>.: •...
Voltage/Current
,:!,'

'I'

Ii

"j

~-i,

A' A!<:<

COMMUNICATIONS
:.0·.·
....
·
~......---­ RS-232-C (Standard)
+
·.t: ..........................._ - - RS-422/485

MODE

i·,<:w,

~......---

ANALOG
OUTPUT
None
One output (0-10V/4-20mA)

II

POWER
~.
115 VAC
;.E~
230 VAC
j.
100 VAC
0 - - - ±5Vdc
 for 21 0-260 VAC)
APP-20E21 : ................. 210 to 260 VAC Oumper selectable> for 105-130 VAC)
APP-20J21 :................. 85 to 105 VAC (jumper selectable> for 170-210 VAC)
APP-20D21 :................. +10.5 to +15V dc
>Jumpers are located in the
printer housing and are accessible when the print module assembly is removed.
Input Frequency Range

47 to 440 Hz

Power Consumption
AC models ................... 5 watts at idle, 17 watts avg.
during printing.
DC models ................... 360 mA at idle, 1.2 Avg. while
printing.
Note: The APP-20D21 (and APP-M20D21) will operate off
a typical 3 A (min.) linear regulated general purpose power
supply having transient tolerance of 10 A for 10 mS. If the
supply is not exclusively for use with the APP-20, a larger
unit is required because line disturbances may occur.
Line Cords
AC models ................... Captive 3-wire line cord approximately 6 feet (2m) long
supplied with grounding plug
for US (A and J models) or two
prongs and ground shell for
European (E and V models).
DC models ................... MOLEX@ 03-09-1094 housing
with MOLEX@ 02-09-1118
crimp-on female terminals
(sockets).
Fuse
AJ models .......... .............. 112 amp SLO-BLO
E models .......................... 1/4 amp SLO-BLO
D models ........................... 2 amp SLO-BLO
3AG type, dimensions ......... 0.25" dia. x 1.25" long, mounted on printer housing rear panel.

PHYSICAL/ENVIRONMENTAL
Operating Temperature Range

0 to 10,000 feet (3048 meters)

Relative Humidity

0% to 90% (no condensation)

Acceleration (Non-Operating)

10-10

Housing Outline Dimensions
4.44"W x 2.76"H x 8.75"D> (113 x 70 x 222 mm)
>Allow an additional 1.5" for connector hood and cable clearance.
Bezel Dimensions
5.25"W x 2.82"H x 0.78"D (134 x 72 x 20 mm)
Front Panel Mounting Cutout
4.50"W x 2.78"H x (115 x 71 mm)
Mounting Method
Using 4 sets of 4-40 hardware in printer housing mounting
flanges. Mounting bolts are concealed be the bezel attached to the slide out print module assembly.
Interface Type
Serial asynchronous 20 mA current loop or RS-232-C compatible.
Input Data Rates
The following data rates, which are selectable at the rear
connector by either jumpers or TTL logic levels, are supported: 75,110, 150, 300, 600, 1200, 2400, 4800, 9600.
Word Length
Automatic word length recognition is standard. Word
lengths of 9, 10 and 11 bits consisting of the following are
supported:
A. 1 Start bit always
B. 7 or 8 data bits
C. Parity or no parity (parity adds 1 bit, no parity adds 0
bits)
D. 1 or 2 stop bits
Note: 8 data and one parity are not allowed.
Data Coding Levels
"1" (MARK)

Current Loop: 20 mA nominal
(15 to 25 mAl
RS-232-C: -3 to -15V

"0" (SPACE)

Current Loop: 0 mA nominal
(0 to 0.5 mAl ,2.6 to 2.8V,
drop to "1" Isolation: 300
Vrms, 100 Megoms

-20°C to +50°C

Storage Temperature Range
-45°C to +85°C (Warning: The paper will begin to darken after several days of exposure to temperatures exceeding
+60°C).
Altitude

Weight
AC models: .................. 4.25 Ibs (1.9 kg), paper included
DC models: .................. 2.2 Ibs (1 kg). paper included

+5G, 3 axes, 0 to 50 Hz

RS-232-C: +3 to +15V (refer
to EIA spec. for further information)
Input Logic Levels
All connections are compatible with DTUTTL and TTL-LS
levels. CMOS 4049 buffers may also be used. Outputs can
drive 2 TTL loads, min.
All logic inputs include internal pullup resistors and may be
floated for the positive level, and tied to signal GND (pin 7)
for low level. All inputs are level sensitive; risetime is not
critical.

DATEL,lnc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

APP-20A21, 021, E21, J21
Exceptions:

Tall character control (pin 8) floats to
ground via a 2K ohm resistor. Tall
character control (pin 9) has a t K ohm
pullup and may not be driven by type
4049GMOS.

ORDERING GUIDE
I

MODEL

DESCRIPTION

!

APP-20A21

115 VAG powered, (jumper-selectable for
230 VAG) USA type power cord and plug
included.

APP-20D21

+ 10.5 to + 15V dc powered, MOLEX® connector and pins included.

APP-20E21

230 NAG powered, (jumper-selectable for

I

I

115 VAG) European power cord included.
I

I

APP-20J21

100 VAG powered, USA type power cord
included.

APP-M20D21 + 10.5 to + 15V dc ruggedized mobile printer, including mounting bracket, power
cable and printout illuinating lamps.

I APP-TR2A

Automatic take-up reel/rewind accessory,
115 VAG powered

APP-TR2E

Automatic take-up reel/rewind accessory,
230 VAG powered

APP-TR2D

Automatic take-up reel/rewind accessory,
+12V dc powered

32-2242572

20 column thermal printer paper (10 130'
rolls)

•
I

33-8193200

Printer stand kit for bench top applications.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-11

APP-20A3, E3,J3, 03
IEEE-488 Bus Compatible
20-Column Thermal Printer
FEATURES
• Complete 20-column panel-mount printer with
IEEE-488 interface and power supply built in
• Full 96-character ASCII set, TALL character
mode, inverted printing option
• Fast 1.1 lineslsecond
• Quiet, inkless, virtually maintenance-free
• Light-weight and compact; only 4.25 Ibs (AC
version), 2.2 Ibs (dc version)
• Available with dual 115/230 VAC, 100 VAC, or
+12V dc power supply

GENERAL

DESCRIPTION

The APP-20A3/E3/J3/03 is a miniature 20-column panelmount alpha-numeric thermal printer with complete power
supply and interface electronics to accept data using the
IEE-488 Standard General Purpose Instrument Bus (GPIB).
The APP-20 functions as a Listen Only device with its own
user-selectable 5-bit My Listen Address (MLA). While sharing a party-line 488 Instrument Bus, unique addressed messages can be sent to only the selected APP-20 or to
groupes of remotely-addressed APP-20's.
The APP-20 prints the full ASCII character set of upper and
lower case letters, numerals, punctuation, etc. in 20 columns across 2 5/16" wide (58,6 mm) thermal paper. A dotline thermal printhead forms 5 x 7 matrix characters which
are 0.11 inches (2,8 mm) high. The printing rate is 1.1 lines
per second regardless of the number of characters printed
and a 150 foot roll of thermal paper prints almost 9,000 lines
of data (180,000 characters max.) at 5 lines per inch
(2 Iines/cm) spacing.
The internal control microprocessor of the APP-20 offers
special OEM programming features which would be impossible with a conventional mechanical printer. Perhaps the
most striking feature is the inverted text printout mode. In
this mode, printing appears upside down from the front panel. However, when the paper is torn off and inverted, the
last line printed is at the bottom as normal text would be. In
fact, the APP-20 may be mounted with its front panel horizontal (facing upward) for text printing applications. In
these applications, the APP-20 is a text printer, like a teletypewriter. In the normal front-panel application, the APP20 prints the last line at the top (Lister mode). This mode is
commonly used in printing data logger applications. Since
the Text and Lister Modes are pin-selected, users may combine inverted text with normal listings in the same printout.
Other programming features are either data-coded or pinselected (see specifications). These include double-height
characters, single-character printing, form feed, horizontal
tab, backspace, delete, and selected data polarity.

10-12

Extended-height characters are used for emphasis and may
be intermixed on one line with regular height characters.
A form feed (FF) character advances the paper 11 lines to
separate adjacent records and a horizontal tab (HT) command indexes input data to print in columns 4, 9, and 15 for
tabular data. The AC power supply used in the APP-20A3
and APP-20E3 is a dual voltage type (115/230 VAC) so that
OEMs need to stock only one version. Power consumption
is 5 watts at idle and averages 17 watts while printing. Also
available are 100 VAC and +12V dc models (J3, 03)
The printer may be operated at +1O°C to +40°C.
,-------I For a ruggedized version of the APP-20, suitable for mo- I
: bile applications, see the APP-M20~ ________..-J

DATEl, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEl (508) 339-3000ITLX 174388/FAX (508) 339-6356

APP-20A3, E3, J3, 03
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C unless noted)

GENERAL
Function ..................... The APP-20 prints alphanumeric information on internal
roll paper from externally supplied ASCII character codes.

PRINTOUT
Number of Columns .... 20
Characters Printed .... All upper and lower case
ASCII letters, numbers, punctuation and special symbols
shown in the ANSI X3. 4-1977
specification.
Printing Format. ......... 5 columns x 7 row matrix
Character Spacing
(Horizontal) ................ Approx. 9 characters per inch
Line Spacing .............. Approx. 0.2 inches (5,1 mm).
5 lines per inch (4 dot widths
spaced between lines)
Character Size
Normal. ................... 0.11 "H x O.07"W
Tall ......................... 0.165"H x 0.07"W
Printing Method ......... Dot-line, thick-film non-impact
ceramic thermal printhead
Paper Motion .............. Stepping Motor, Friction Roller, and gear reduction. Paper advance (4 dot widths)
occurs automatically after
printing. A line may be viewed
immediately after printing.
Printing Rate
(Max.) ......................... 1.1 lines per second regardless of number of printed
characters per line.
Data Byte Throughput Period
1. All printable characters, 400 microseconds/
character max.
2. CR print command or LF, 0.9 seconds typical., 1
second max.
3. FF character, 5 seconds max.
Printing Paper ............ Thermal paper 2.31 inches
wide (58,6 mm) with active
surface facing away from roll
center. Supplied on rolls of
150 feet length (45 m). Approx. 140 feet usable (42 m).
Supplied in boxes of 10 rolls,
DATEL model number 322242572
Printout Color ............ Black characters on white paper
Data Capacity ............ Approximately 8,400 lines
(168,000 characters max.)
per 140 feet of paper roll
Print head Life ............ 30 million lines typ (random
character distribution and usage with DATEL-supplied paper and unmodified printers)
Mechanism Life .......... 5,000 hours, typical

Maintenance .............. Periodic cleaning with isopropyl alcohol of mechanism,
printhead and roller is suggested for dirt accumulation
depending on operating conditions. Printhead design is
self-cleaning.

FRONT PANEL
Power On .................... Red Light-emitting diode illuminates when power is applied
Feed ........................... 2 position momentary toggle
switch. Actuating either up or
down advances paper continuously at 2.9 lines/second or
0.6 inches/second (1,5 cm/
sec).
End of Paper Indicator ........................... A red light emitting diode illuminates when the paper supply has one inch remaining.
DATEL thermal paper features a red "paper low" warning stripe on the last six feet
of paper.
Housing Latch ............ Rotating "UNLOCK" knob 1/4
turn counter-clockwise frees
mechanism from housing and
electronics. Knob is pulled
out to replace paper roll. This
disconnects power to the
mechanism and stops printing.

POWER SUPPLY
Supply Voltage
APP-20A3 ............... 105 to 130 VAC Uumper selectable' for 210-260 VAC)
APP-20E3 ............... 210 to 260 VAC Uumper selectable' for 105-130 VAC)
APP-20J3 ............... 85 to 105 VAC Uumper selectable' for 170-210 VAC)
APP-20D3 ............... +10.5 to + 15V dc
'Jumpers are located in the printer housing and are
accessible when the print module assembly is removed
Freq uency .................. 47 to 440 Hz
Power Consumption
AC models: ............. 5 W idling, 17 Waverage while
printing
DC models: ............. 200 mA idling, 1 A average
while printing
Line Cords .................. Captive 3-wire line cords approximately 6 feet (2 m) long
supplied with grounding plugs
for US (A and J models) or European (E models, 2 prong
and ground shell)
Fuses
A and J models: ..... 1/2 Amp SLO-BLO
E models: .............. 1/4 Amp SLO-BLO
D models: ............... 2 Amp SLO-BLO

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-13

APP-20A3, E3, J3, 03
PHYSICAL·ENVIRONMENTAL·MECHANICAL
Operating Temper·
ature Range ............... +10°Cto+40°C
Storage Tempera·
ture Range ................. -25°G to +85°G (Paper darkens above +60°C)
Altitude ...................... 0 to 10,000 feet (3,000 meters)
Relative Humidity ...... 0% to 90% (no condensation)
Acceleration (Non·
operating) .................. ±5G, 3 axes, 0 to 50 Hz
Weight
AC models: ............. 4.25 Ibs (with paper roll), 1,93
kg
DC models: ............. 2.2Ibs, 1 kg
Dimensions: ........... 0.25" dia x 1.25" long 3AG
type accessible on rear panel
Housing Outline Di·
mensions ................... .4.44"W x 2.76"H x 8.75"0
(113x70x222mm)
Allow an additional 1.5" for
connector hood and cable
clearance.
Bezel Dimensions ...... 5.25"W x 2.82"H x 0.78"0
(134 x 72 x 20 mm)
Front Panel Mount·
ing Cutout .................. 4.50"W x 2.78"H
(115 x 71 mm)
Mounting Method ....... Using four sets of 4-40 hardware (not supplied) in housing
mounting flanges. Mounting
bolts are concealed by slideout front panel bezel.

INPUT/OUTPUT CONNECTIONS
Type ............................. Byte-paralieIIEEE-488-1978
General Purpose Instrument
Bus
List of Allowable Subsets (see IEEE-4881978, Appendix G) ........... SHel, AH1, Tel, TEel, L1,
LEel, SRel, RL2, PPel, OG1,
DTel,Gel
Drivers .......................... E1 (open collector)

ORDERING GUIDE
MODEL

DESCRIPTION

APP-20A3

20-column thermal printer, IEEE-488
Interface, 115/230 VAG transformer
wired as 115, USA line cord.
20-column thermal printer, IEEE-488
Interface, 115/230 VAG transformer
wired as 230, 2-prong and ground shell
line cord.
20-column thermal printer, IEEE-488
Interface, 100 VAG, USA line cord.
20-column thermal printer, IEEE-488
Interface, + 12V dc power at 1A typ.,
6A max. 20 mS.
Box of 10 paper rolls, black image
Printer stand kit for bench-top applications
Automatic take-up reel/Rewind accessory, 115 VAG powered
Automatic take-up reel/Rewind accessory, 230 VAG powered
Automatic take-up reel/Rewind accessory, +5V dc powered

APP-20E3

APP-20J3
APP-20D3
32-2242572
33-8193200
APP-TR2A
APP-TR2E
APP-TR2D

10-14

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

APP-48A 1, E1, J1, 01
Byte-Parallel Input
48 Column
Thermal Printer
FEATURES
• Complete 48-column panel-mount printer with
byte-parallel Centronics-compatible data
electronics and power supply built-in.
• Prints full 96-character, upper and lower case
ASCII alphanumerics. Includes 2nd
96-character set of special figures, currency
symbols, mathematical operators.
• Thermal printhead, 5 X 7 dot matrix, few
moving parts for OEM reliability. No ink, no
ribbons, no hammers, no mess!
• Prints inverted text (like a TTY) under
data-coded control. Last line printed at
bottom of text.
• Internal microprocessor includes 1-line,
48-column data register.
• 6 pound mini-lightweight.
• Prints up to 72 lines per minute.
• Choice of 100/115/230 VAC or 12V dc power
supplies.

GENERAL DESCRIPTION
The APP-48 A 1, El, Dl, Jl series is a miniature, panelmounting 48-column alphanumeric printer with quiet, inkless
thermal printing and complete, internal byte-parallel data electronics and power supply. The 8-bit parallel data signals
are directly compatible with the universally-accepted Centronics Interface standard which uses an asynchronous 3wire handshake.
This interface is ideal for connection to popular microprocessors through Peripheral Interface (PIA/PIO) parallel port
LSI integrated circuits. A conventional 25-pin D-connector
is mounted on the APP-48 A l's rear panel for connection to
a host computer data source.
The APP-48 is designed as a miniature, panel-mounting
printing RO data terminal for applications in test and measurement, instrumentation, analytical instruments, diagnostic test systems, custom automatic test equipment and microcomputer development systems.
Besides the 8-bit parallel interface, the APP-48 is also available with full serial RS-232-C/20 mA loop interfaces and a
byte-parallel IEEE-488 GPIB interface BUS. DATEL also
manufactures a 20-column APP-20 mini-thermal printer with
choice of parallel, serial or IEE-488 interfaces. A sevencolumn numeric full-parallel BCD thermal printer is also
available as model DPP-Q7.
The printing technology on the APP-48 uses a quiet OEMrugged thermal 5 X 7 dot matrix method with no ink ribbons,
platens, hammers or ink mess. Only two moving parts are
used to provide very long life and high reliability.

i For a ruggedized version of the APP-48, suitable for
l.:obile_ apPli~tions, see the APP-M48.

The internal microprocessor controls the data electronics,
printhead and motor drivers. Data-coded control characters
(STX/ETX) allow inverted printout for text applications so
that the' last line will appear either at the top or bottom of the
printout. Normal data entry uses standard 96-character
ASCII-encoded alphanumerics. SOISI data-coded control
characters map the input ASCII coding into a second set of
96 characters stored in a type 2716 Programmable Memory.
The lightweight 6 pound (2,7 kg) APP-48 mounts through a
8.40"W X 2.92"H (213, 4 X 74,2 mm) front panel cutout with
four screws. A choice of power supplies are available:
100VAC, 115VAC, 230VAC, or 12V dc. For AC units, power
consumption is 40 watts printing, 12 w idle; DC units average 1.5A while printing, 0.7A idle. The operating temperature range is 0 to +50°C.

ORDERING GUIDE
MODEL
APP-48Al

DESCRIPTION
Printer with 115/230 VAC (XfmR, USA line
cord, 115V wired.
APP-48-El Printer with 115/230 VAC XfmR, European
line cord, 230V wired.
APP-48Jl
Printer with 100 BAC XfmR, USA line cord.
APP-48Dl Printer with + 12VDC Power.
32-2242568 Box of 10 paper rolls, black image.
33-8193205 Printer Stand Kit.
APP-TR5A Take-up Reel/Rewind Accessory, 115 VAC
powered.
APP-TR5E Take-up Reel/Rewind Accessory, 230 VAC
powered.
APP-TR5D Take-up Reel/Rewind Accessory, +12V dc
powered.
58-2079130 Spare Mating DB-25S Connector (1 supL _ _ _ _---"p~lie=_=d"___) ___ ~ ______ ~_. ____ ._

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-15

•

APP·48A1, E1, J1, 01
----------- ---------------- --- ----------- -------1

FUNCTIONAL SPECIFICATIONS
(Typical at +25°C unless noted)

PRINTOUT
Number of Columns 48
Characters Printed
96-character set per ANSI X3.4-1977 specification. A second 96-character is accessed by SOISI control.

DATA CODED FUNCTIONS
I

~~ ~"", Ig"",e~--- -I """;;=
Backspace, delete previous I
character, decrement column
address counter toward the i
left

BS

Printing Inversion Selectable using STX/ETX control
characters (may not be intermixed on the same line)

08

i
I

I.
I

Printing Format 5 dot columns x 7 dot row matrix per
character.

SO

Line Spacing
0.164 inch (4,2 mm) line to line. Approximately 6 lines per
inch.

Map input data to 2nd 96I
character set, mixable within
aline.
I

SI

Reset to normal ASCII charac-I
ter set, mixable within a line. I

0F

STX

Change to inverted (text)
printing. Not mixable within
a line.

02

ETX

Ch;:mge to non-inverted
(lister) printing. Not mixable
within a line.

i

Printout Width (48 columns)
4.77 inches (121,2 mm)

1

0E

I

I

Character Size
0.070"W x 0.110"H (1,8 X 2,8 mm)
Printing Rate
1.2 lineslsecond maximum. Depends on data loading period
and printing period. Data Loading Period equals 110 J,tS minute per character. Printing period equals 750 mS minute per
line.
Printing Paper
Thermal paper 5 inches (127 mm) wide by 150 foot (45 m)
rolls. A red stripe appears when approximately 10 feet of
paper remain. User-supplied paper must detach from the
roll.

HT

Tab successively to columns
9,17,25,33.

LF

Feed one line, no print, no
data register change.

I
I
I

03

I

09

0A
I

Data Capacity
Approximately 11.000 lines in 150 feet usable per roll.

FF

Advance 11 lines, no register I
change.
I

Printhead Life
30 million characters with random data and DATEL-supplied
paper.

CR

Print register contents, advanceone line, clear register.
Requires 750 mS during
which input data may not be
loaded. LF is not required
LF will be ignored in the sequence CR, LF. Loading
of 48 characters and/or
spaces will automatically
start printing.

0C

1

Mechanism Life
5000 hours in non-hostile applications.

I

DEL

Decrement column address
to the left, clear that data register, load a rubout obliteration pattern and increment
column address to the

NOl

right.

!

00

I
I
I
.

I
I
I
1

7F

NOTE: Data is loaded starting at the left margin.
1

10-16

I

1

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

APP-48A1, E1, J1, 01
POWER SUPPLY
Required Power
APP-48A1 ..................... 10S to 130 VAC@47t0440 Hz,
jumper-selectable' for 210 to 2S0
VAC. Includes USA-style power
cord.

Outline Dimensions
8.20"W X 3.2S"H X 8.14"D
(208,3 X 72,1 X 206,8 mm)

Bezel Dimensions
9.2S"W X 3.2S"H X 0.7S" Thick
(23S,O X 82,6 X 19,1 mm)

Front Panel Mounting Cutout
APP-48E1 ..................... 210 to 2S0 VAC @ 47 to 440 Hz,
jumper-selectable' for 10S to 130
VAC. Includes European-style
power cord.
APP-48J1 ...................... 100 VAC@47t0440 Hz. Includes USA-style power cord.

8.40"W X 2.92"H 213,4 X 74,2 mm)
requiring 4 #8 mounting bolts.

Connector Type
DB-2SP mounted on rear panel (2S pint D connector).
Mates to a supplied DB-2SS connector (DATEL PIN S82079130).

APP-48D 1..................... +1 O.S to 1SV dc. Line cord with
spade lugs included (black =
+12V dc, white = 12V dc return,
green = ground).
, Jurnpers are located at the top rear of the power regulator
board.

CONSUMPTION
AD models
40 watts max printing, 12 watts max idling

DC model
1.SA printing (average), 0.7 amps idling

FUSES
A 1, J1 Models ................ 1 amp
E1 ModeL ...................... 1/2 amp
D1 ModeL ...................... 3 AG SA SLO-BLO

PHYSICAL
Operating Temperature Range

oto +SO°C

Storage Temperature Range
-30°C to +8SoC without paper. Warning: The paper darkens after long exposure above +60°C.

Humidity
10% to 90%, non-condensing

Weight
6 pounds (no paper) 2,7kg)

Paper Roll
0.7 Ib (0.3 kg)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (S08) 339-3000fTLX 174388/FAX (S08) 339-6356

10-17

APP-48A2, E2, J2, 02
Serial Input 48-Column
Thermal Printers
FEATURES
Complete 48-column panel-mount printer with
full serial data electronics and power supply
built in.
• Accepts standard RS-232-C input at 110 to
9600 baud; also provides optoisolated 20 mA
current loop input for operation hundreds of
feet from the data source.
Prints full 96-character, upper and lower case
ASCII alphanumerics. Includes a second 96character set of special figures, currency
symbols, European punctuation, mathematical operators, Greek letters.
Dot-line thermal printhead, few moving parts
for OEM reliability.
• Prints inverted text like a TTY under software
control. Last printed line is at bottom of text.
Internal microprocessor includes 1-line, 48column data buffer. Optional 132 character
buffer (APP-48_ 41 permits continous data input.
• Prints up to 72 lines per minute.
6-pound (2.7 kg) mini-lightweight.
Choice of 100/115/230 VAC or +12V dc power
supplies.

GENERAL

(127 mm) wide. Input data may be accepted at switchselected data rates fromll 0 to 9600 baud. Commonly used
with teletypewriters, computer serial 110 ports and data terminals.
With the optional 132-character FIFO buffer installed (APP48_4), the printer wil accept continuous full serial input at
110 baud (11-bit word length) or 300 baud (10-bit word
length).
The 20 mA current loop data input is optoisolated so that
common mode noise is rejected. Also the APP-48 may be
operated at lower baud rates many hundreds of feet from
the data source using only voice grade telephone wire.

DESCRIPTION

Datel APP-48 panel-mount alphanumeric thermal printer
highlights half a decade of thermal printer experience and
leadership. Beginning in 1975 Datel pioneered the concept
of including all data and power supply electronics inside the
miniature housing.
The non-moving thermal printhead technology employed today in the APP-48 obsoletes ink printers with their twirling
printwheels banging hammers and internal mess due to ink
ribbons or platens.
The APP-48 accepts full serial input which has been formatted into 10 or II-bit packed ASCII characters and is driven
to either 20 mA loop or RS-232-C data levels. One printable
line (up to 48 columns) of input data is stored in an internal
input register. Data input is then halted briefly (750 mS)
while the APP-48 drives the therrnal printhead elements and
advances to the next line after printing. The character is
formed in a 5 column by 7 row dot matrix on speciallycoated, thermally sensitive paper measuring 5 inches

10-18

I---~--~~--"'--'

I For a ruggedized version of the APP-48, suitable for mobile I
i applications, se~-,he ~PP-M_~!l.- __ ~_.~__ ~_. ___ J

The RS-232-C inputs include Request-To-Send and DataTerminal- Ready standard control signals to synchronize
start-stop data transfer from a rernote source. A rear-panel
DIP switch set selects the data baud rate, input format and
other parameters.
The APP-48 prints the full 96-character set of standard ASCII characters. A second 96-character alphanumeric data
set is stored in internal memory. This set may be accessed
by transmitting the shift out control code (SO) before loading the next character. Shift in (SI) restores the normal 96character ASCII set. The second set includes special figures, currency symbols, mathematical operators, European punctuation, Greek letters, etc.
The STX/ETX control codes change the mode to inverted
printing where the last record is at the bottom of the text
when viewed normally. In this mode the APP-48 may be
mounted with its panel horizontal with printout feeding upwards like a teletypewriter. Under software control, lines
may be alternated between lister (normal) and text (inverted) print modes.

DATEL. Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

APP-48A2

The print mechanism of the APP-48 consists of a stationary
dot-line thermal printhead, Software-controlled stepping
motor and cogged belt/print roller drive. The lightweight 6
pound (2.7 kg) APP-48 mounts through a 8.40"W X 2.92"H
(213.4 X 74.2 mm) front panel cutout with four screws. A 3pronged line plug is captive to the internal AC power supply
which is available as 115, 230, or 100 VAC, 47 to 440 Hz
Power consumption is 40 watts maximum during printing and
12 watts while idling or accepting data. The printer is also
available with a + 12V dc power supply. The dc version
draws 1.5 amps while printing, 0.7 amps idling. The overall
dimensions of the APP-48 are 8.12"W X 2.84"H X 8.32"0
(206,3 X 72,2 X 211,3 mm). The operating temperature
range is 0 to +50°C and the front bezel measures 9.25"W X
3.25"H X 0.75" thick (235,0 X 82,6 X 19,1 mm)

Printing Paper ...... Thermal paper 5 inches (127
mm) wide X 150 foot (45 m) rolls.
Supplied only in boxes of 10
rolls. Reorder part no. 3322422568. A red warning strip is
displayed on the paper when approximately 10 feet of paper remain'.
Data Capacity ...... Approx. 11,00 lines in 150 feet
usable per roll.
Print head Life ...... 30 million characters typical with
random characters and Datel 332242568 paper rolls.
Mechanism Life .... 5,000 hours, typical in nonhostile environments.
'For users fabricating their own paper rolls, the end of the paper must detach from the
core when paper is exhausted.

SPECIFICATIONS,
(Typical at +25°C unless noted)

PRINTOUT
Numbers of Columns 48
Characters Printed
96-character set upper and lower case ASCII letters,
numbers, punctuation per ANSE X3.4-1977 Specification. A second 96-character set is accessible by transmitting the ASCII Shift Out (SO) character. This second set consists of European characters, mathematical
symbols, Greek letters, some graphics symbols, monetary symbols, and others. The original ANSI X3.4 set is
restored using the Shift In (SI) control character.
Printout Inversion. Character-lines may be printed
out inverted with STX and ETX
control characters. (Note: Normal and Inverted Text may not
be intermixed on the same line)
Printout Format ... 5 dot columns by 7 dot row matrix per character.
Printout Color ..... Black characters on white paper.
Line Spacing ........ 0.164 inch (4,2 mm) line to line.
Approximatelyu 6 lines per inch.
Vertical Spacing
Between Characters 0.1 inch (2.5 mm)
Printout Width
(48 columns) ........ 4.77 inches (121,2)
Character Size ..... 0.070"WXO.ll0 H (1,8 X 2.8
mm)
Printing Method .... Dot-line, non- impact inkless ceramic thermal printhead.
Printing Rate ........ Up to 72 lines per minute. (1.2
lines per second) at highest
9600 baud rate, regardless of
the number of characters printed
per line. The time required to
print each line is:

! :har
I

line #

b~s char

Baud Rate

+0.75 I
'

INTERFACE
Interface Type ..... Full serial asynchronous either
with or without data loading
handshake controls.
Input Data Rate .... A rear panel DIP switch set selects one of the following data
baud rates:
110
1200
150
2400
300
4800
600
9600
Note: The external data source
must either halt or pad nulls during the 750 mS print and advance cycle. Continuous data
input at 110 or 300 baud is possible when the 132 character
FIFO buffer option is installed
(OAPP-48_4).
Data Format .......... Selectable 10 or 11 bits per
character. 7 or 8 data bits, odd,

~~:~ or no parity.

1 or 2 stop

Electrical Data Inputs
Two inputs, EIA RS-232-C or 20 mA corrent loop on
separate pin sets on the rear panel DB-25P data connector. A Request to Send output (RS-232-C circuit
CA, pin 4) and Data Terminal Ready output (RS-232-C
circuit CD, pin 20) are provided. (Note: The logic polarity of Requst to Send is Switch Selectable)

Seconds

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

10-19

11.1

APP-48A2

CD, pin 20) are provided. (Note: the logic polarity of Request to Send is switch selectable)
Self Test. .............. An internal rotating 96-character
ASCII set rnay be printed using
two external jurnpers from pin 25
to pin 7 (ground) and from pin 2
to 3.
Data Coding Levels
Current Loop* RS-232-C

Note:

DATA-CODED FUNCTIONS
Character
meaning
NUL
BS

SI
Notel

Note 2

Character

Hf
Hex.

Octal

Null, ignored
00
000
Backspace delete
08
010
previous character
Shift Out. Maps
OE
016
input data into the
2nd 96-character
(non-standard set)
Shift In. Reset into OF
017
ASCII data set
SO and SI may be transmitted before each
character. If SO or SI are not sent, printer
will remain in last character set status. Power-on reset selects the ASCII character set.
Backspace decrements the column address
counter loads a space character, and leaves
column counter, decremented The recommended procedure to clear a line of any
length before printing is to load 48 backspaces.

LF
FF
CR

DEL

03

Octal.

002

003

STX and ETX must be transmitted before
each line and cannot be accepted within a
line. If STX and ETX are not sent, the other
printer will remain in the last mode status.
Power-on reset may be DIP switch selected
to automatically start in either the text or lister mode.

"1"

(Mark) 20 mA nom -3 to -15V
"0"
(Space) 0 mA nom +3 to +15V
*105 Megohms resistance,
1500V dc isolation.

Hex.
02

Character
Meaning
STX
Changes to inverted
printing (text) mode
ETX
Changed to normal,
non-inverted (lister)
printing mode.

Meaning

Hex.

Horizontal tab. Success09
ively indexes to columns
9, 17, 25 and 33 for data
logging or tabular aplications.
OA
Line Feed. Advances one
line, no print, no change of input register.
Form Feed. Advances 11
lines, no register change.
00
Carriage Return is used
to print register contents,
clear the register and advance one line. CR requires 750 mS, during which
input data cannot be accepted. LF is not required
to advance the line. If the
sequence CR LF is sent,
LF is ignored*
Delete. Clear previous ch- 7F
aracter column, load rubout obliteration pattern,
and advance column counter to original address.
It is not possible to backspace and obliterate previously printed characters

Octal.
011

012

015

177

* A full input register will
also automatically start
the printing cycle
FRONT PANEL
Power

10-20

On .......... Yellow Light Emitting Diode
(LED) iluminates when power is
applied. Note: Since most users
will connect the APP-48 through
a master system power on-off
switch. There is not spearate
power on-off switch on the APP48.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

APP48A2
PHYSICAL
Fee d ................ Momentary pushbutton switch
(Note 1) advances paper as long
as it is depressed. (Note 2)
End of Paper ........ Red LED illuminates when approx. one inch of paper is remaining and disables further
printing until paper is renewed. A
red warning stripe appears on
paper before the LED illuminates. (Note 2)
Note: 1 A line will finish printing if Feed is depressed while
executing the print and advance cycle.
Note: 2 Feed and End of Paper functions cause Request to
Send to go false to inhibit the data transmitter.
POWER SUPPLY
Required Power
APP-48A2 ................ 10S to 30VAC@ 47 to 440 Hz,
jumper-selectable * for 210 to
2S0 VAC. Includes USA-style
power cord.
APP-48E2 ................ 210 to 2S0 VAC @ 47 to 440 Hz,
jumper-selectable* for 1OS to
130 VAC. Includes Europeanstyle power cord.
APP-48J2 ................ 100 VAC 47 to 440 Hz. Includes
USA-style power cord.
APP-48D2 ................ +10.S to 1SV dc. Line cord with
space lugs included (black =
+ 12V dc, white = 12V dc return,
green = green).
*Jumpers are located at the top rear of the power regulator
board.
Consumption
AC Model... .............. 40 watts max printing, 12 watts
max idling.
DC Model. ................ 1.SA printing (avg), 0.7 amps
idling.

Operating Temperature
Range ............... 0 to +50°C
Storage Temperature
Range ................ -30°C to +85 without paper.
Warning: The paper begins to
darken after long exposure to
+60°C and above.
Weight.. ................ 6 pounds (no paper) (2.7 kg)
Paper Roll. ............ 0.7 Ibs. (0.3 kg)
Outline Dimension. 8,12'W X 2.84"H X 8.32"0
(206,25 X 72,14 X 211.33 mm)
Bezel Dimensions. 9.2S"W X 3.25"H X 0.7S"Thick.
(23S,0 X 82,6 X 19,1 mm).
Mounting Method. Through a front panel cutout
measuring 8.40"W X 2.92"H
(213.4 X 74.2 mm) 4 #8 mounting bolts and hardware are required.
Mounting Position Horizontal (Panel Mount) or Vertical (with panel facing upwards)
Acceleration
(non-operating) .... Within ±SG 0 to SO Hz,3 Axes
Relative Humidity. 0 to 90% non-condensing
Altitude ................. 0 to 10,000 feet (3048 m)

ORDERING INFORMATION
MODEL

DESCRIPTION

APP-48A2

Printer, 115/230 VAC (115
VAC wired), 47-440 Hz, USA
Plug
Printer, 115/230 VAC (230
VAC wired), 47-440 Hz, European Plug
Printer, 100 VAC, 47-440 Hz,
USA Plug
Printer, + 12V dc Power
Printer with optional 132character data buffer (specify
desired power supply).
Box of 10 thermal paper rolls
(150 feet per roll)
Spare Mating DB-25S Data
Connector (1 supplied)
Printer stand kit (for benchtop applications)
Take-up reel/rewind accessory, 115 VAC powered
Take-up reel/rewind accessory, 230 VAC powered
Take-up reel/rewind accessory, ±12V dc powered.

APP-48E2

APP-48J2
APP-48D2
APP-48 4

Fuses

33-2242568

AC Models ............... 11S and 100 VAC, 1 amp
230 VAC, 1/2 amp
DC Model. ................ 3 AG, SA SLO-BLO

58-2079130
33-8193205
APP-TR5A
APP-TR5E
APP-TR5D

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (S08) 339-3000/TLX 174388/FAX (508) 339-6356

10-21

II

APP-48A3, E3, J3, 03
IEEE-488 Bus Compatible
48-Column Thermal Printers
FEATURES
• Complete 48-column panel-mount printer with
IEEE-488 interface and built-in power supply
• Prints full 96-character, upper and lower case
ASCII alphanumerics. Includes second 96character set of special figures, currency
symbols, European punctuation, mathematical
operators, etc.
• Dot-line thermal printhead, few moving parts
for OEM reliability. No ink, no hammers, no
mess!
• Prints inverted text (like a TTY) under software control
• Internal microprocessor includes one line, 48column data buffer
• Prints up to 72 lines per minute
• 6 pound (2.7 kg) mini-light weight
• Choice of 100/115/230 VAC or + 12V dc power
supplies

GENERAL DESCRIPTION
The APP-48A3/E3/J3/03 is a miniature 48-column panelmount/table top alphanumeric thermal printer. It comes
complete with power supply and GPIB compatible interface
electronics to provide hard copy output via the IEEE-488
General Purpose Interface Bus (GPIB). The APP-48 operates as a "Listen Only" device using a unique userselectable 5·bit "My Listen Address" (MLA).
The IEEE-488 IB compatible devices which can send data
messages to the APP-48 include computers, programmable
calculators, digital voltmeters and spectrum analyzers. In
addition, by using readily available GPIB interface boards,
most popular mini and microcomputers can easily make use
of the APP-48.
The APP-48 is fully IEEE Std. 488-1978 GPIB (General Purpose Interface Bus) compatible. The GPIB compatible
APP-48 communicates with the controller using standard
open collector drives. One printable line (up to 48 columns)
of input data is stored in an internal data buffer register.
The data input is then halted for 750 mS while the APP-48
activates the thermal printhead elements to ouput the alphanumeric characters, after which the paper is advanced
to the next line. Each character is formed by a 5 column by
7 row dot matrix on specially coated, heat sensitive paper
which measures 5 inches (127 mm) wide. There are no baud
rate switches or jumpers to worry about as print rate is a direct function of the GPIB handshake protocol.
The APP-48 GPIB data format is 8 parallel, bi-directional
lines, normally 7 data bits and 1 parity bit with 3 handshake
lines:
A. OAV (Data Valid)
B. NRFO (Not Ready for Data)
C. NOAC (Not Data Accepted)

10-22

The APP-48 prints the full 96-character set of standard ASCII characters. A second 96 alphanumeric character set is
stored in an internal memory. This set may be accessed by
transmitting the shift out control code (SO) before loading
the next character. Shift in (SI) restores the normal 96character ASCII set. The second set includes special figures, currency symbols, mathematical operators, European
punctuation, Greek letters, etc.
The STXlETX control codes change the mode to inverted
printing where the last record is at the bottom of the text
when viewed normally. In this mode, the APP-48 may be
mounted with its panel horizontal with printout feeding upwards like a teletypewriter. Under software control, lines
may be alternated between lister (normal) and text (inverted) print modes.
The print mechanism of the APp·48 consists of a stationary
dot-line thermal printhead, software-controlled stepping motor and cogged belt/print roller drive. The lightweight 6
pound (2.7 kg) APP-48 mounts through a 8.40"W x 2.92"H
(213,4 x 74,2 mm) front panel cutout with four screws. A 3prong line plug is captive to the internal AC power supply
which is available as 115, 230 or 100 VAC, 47 to 440 Hz.
Power consumption is 40 watts, maximum during printing
and 12 watts while idling or accepting data. The printer is
also available with a +12V dc power supply. The dc version
draws 1.5 Amps while printing, 0.7mA idling. The overall dimensions of the APP-48 are 8.12"W x 2.84"H x 8.32"0
(206,3 x 72,2 x 211,3 mm). The operating temperature
range is 0 to +50°C and the front bezel measures 9.25"W x
3.25"H x 0.75" thick (235,0 x 82,6 x 19,1 mm).
For a ruggedized version of the APP-48, suitable for mobile applications, see the APP-M48

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

APP-48A3, E3, J3, 03
FUNCTIONAL

SPECIFICATIONS

(Typical at +25°C unless noted)
PRINTOUT
Numbers of Columns .. 48
Characters Printed .... 96-character set, upper and
lower case ASCII letters,
numbers, punctuation per
ANSI X3.4-1977 Specification. A second 96-character
set is accessible by transmitting the ASCII Shift Out (SO)
character. This second set
consists of European characters, mathematical symbols,
Greek letters, some graphics
symbols, monetary symbols
and others. The original ANSI
X3.4 set is restored using the
Shift In (SI) control characters.
Printout Inversion ..... Character-lines may be printed out inverted with the STX
and ETX control characters.
When switch nine at the rear
of the printer is OFF (switched
left), the unit comes up in List
mode, when it is ON (switched
right), the unit comes up in
Text (inverted) mode.
STX = Text Mode. ETX = Lister Mode. (Note: Normal and
inverted text may not be intermixed on the same line)
Printout Format. ......... 5 dot columns by 7 dot row
matrix per character.
Printout Color ............ Black characters on white paper.
Line Spacing .............. 0.164 inch (4,2 mm) line to
line. Approximately 6 lines
per inch.
Vertical Spacing
Between Characters ........................... 0.1 inch (2,5 mm)

Printout Width (48
Columns) ................... 4.77 inches (121,2 mm)

Printing Rate .............. Up to 72 lines per minute, 1.2
lines per second max. regardless of the number of characters to be printed per line.
Printing Paper ............ Thermal paper 5 inches (127
mm) wide x 150 foot (45 m)
rolls. Supplied only in boxes
of 10 rolls. Reorder part no.
33-2242568. A red warning
stripe is displayed on the paper when approximately 10
feet of paper remain.
Data Capacity ............ Approx. 11,000 lines in 150
feet usable per roll.
Printhead Life ............ 30 million characters typical
with random characters and
DATEL 33-2242568 paper
rolls.
Mechanism Life .......... 5000 hours, typical in nonhostile environments.
INTERFACE
Interface Type ........... IEEE 488 STD (1978) compatible.
Data Format.. ............. 8 parallel, bi-directional data
lines, normally 7 data bits and
1 parity bit. 3 handshake
lines: A) DAV (data valid) B)
NRFD (not ready for data) C)
NDAC (not data accepted).
Electrical Data Inputs ........................... IEEE 488 STD (1978) Inter
face Bus compatible.
Self Test.. .................. An internal rotating 96 character ACII set printed when
the bottom switch (SWel) is
switched left. The switch is
accesable at the rear panel.
NOTE: The unit must be powered down for 2 sec. min. after changing any switch position for the change to become
effective.
Data Coding Levels ... Logic Level
o(False)
1(True)

Voltage Level
'C2.0V (High)
~+0.8V(Low)

Character Size ........... 0.070"W x 0.11 O"H
(1,8 x 2,8 mm)
Printing Method ......... Dot-line, non-impact, inkless
ceramic thermal printhead.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

10-23

~ ~[L

APP·48A3, E3, J3, 03

DATA-CODED

FUNCTIONS
Hex

Character
NUL
BS

Null, ignored
Backspace, delete previous
character
Shift Out, Maps input data
into the 2nd 96-character
(non-standard set)
Shift In, Reset into standard
ASCII data set
Changes to inverted printing
(text) mode
Changes to normal, noninverted (lister) printing mode
Horizontal tab successively
indexes to columns 9, 17, 25
and 33 for data logging or tabular applications.
Line Feed advances one line,
no print, no change of input
register.
Form Feed advances 11 lines,
no register change.
Carriage Return is used to
print register and advances
one line. CR requires 750 mS,
during which input data cannot be accepted. LF is not required to advance the line. If
the sequence CR, LF is sent,
LF is ignored:
Delete. Clear previous character column, load rubout
obliteration pattern, and advance column counter to original address. It is not possible to backspace and
obliterate previously-printed
characters.

SO
SI
STX
ETX

Hr

LF
FF
CR

DEL

Octal

Meaning
00
08

000
010

OE

016

Note 1: A line will finish printing if Feed is depressed
while executing the print and advance cycle.

OF

017

Note 2: Feed and End of paper functions inhibit data
transmission from the controller to the printer.

02

002

03

003

09

011

OA

012

OC

014

OD

015

POWER

7F

177

PANEL

Power On .................... Yellow Light Emitting Diode
(LED) illuminates when power
is applied. NOTE: Since most
users will connect the APP-48
through a master system power on-off switch, there is no
separate power on-off switch
on the APP-48.
Feed ........................... Momentary pushbuttom
switch (Note 1) advances paper as long as it is depressed.
(Note 2)

10-24

SUPPLY

Required power
APP-48A3 ...... 105 to 130 VAC at 47 to 440 Hz, jumper-selectable' for 210 to 250 VAC. Includes USA-style power cord.
APP-48E3 ...... 210 to 250 VAC at 47 to 440 Hz, jumper-selectable' for 105 to 130 VAC. Includes European-style power cord.
APP-48J3 ...... 100 VAC at 47 to 440 Hz. Includes
USA-style power cord.
APP-48D3 ...... + 10.5 to 15V dc. Line cord with spade
lugs included (Black = + 12V dc, White
= 12V dc return, Green = ground)
'Jumpers are located at the top rear of
the power regulator board.

'A full input register will also
automatically start the printing cycle.
FRONT

End of Paper .............. Red LED illuminates when approximately one inch of paper
is remaining and disables further printing until paper is renewed. A red warning stripe
appeares on paper before the
LED illuminates (Note 2)

Consumption
AC models ..... 40 watts max printing, 12 watts max
idling
DC models ..... 1.5 A printing (avg), 0.7 Amps idling
Fuses
AC models ..... 115 and 100 VAC, 1 Amp
230 VAC, 1/2 Amp
DC models ..... 3 AG 5A SLO-BLO
PHYSICAL/ENVIRONMENTAL
Operating Temp·
erature Range ............ 0 to +50°C
Storage Temp
eratureRange ............. -30°C to +85°C without paper.
The paper begins to darken
after long exposure to +60°C
and above.
Weight ........................ 6 pounds (no paper) (2,7kg)
Paper Roll... ............... 0.71bs (0,3 kg)
Outline Dimensions ... 8.12"W x 2.84"H x 3.32"0
(206,25 x 74,2 x 221,33 mm)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

APP·48A3, E3, J3, 03
Bezel Dimensions ...... 9.25"W x 3.25"H x 0.75" thick
(213,4 x 74,2 mm)

Mounting Method ....... Through a front panel cutout
measuring 8.40"W x 2.92"H
(213,4 x 74,2 mm) 4 #8
mounting bolts and hardware
are required.

Mounting Position ...... Horizontal (Panel Mount) or
Vertical (with panel facing upwards)

Acceleration
(Non-operating) ......... Within ±5G, 0 to 50 Hz, 3
Axes

Relative Humidity ...... 0 to 90%, non-condensing
Altitude ...................... 0 to 10,000 feet (3048 m)

ORDERING GUIDE
MODEL

DESCRIPTION

APP-48A3

Printer, 115/230 VAC, 47-440 Hz, USA Plug
(115 VAC wired)

APP-48E3

Printer, 115/230 VAC, 47-440 Hz, European
Plug (230 VAC wired)

APP-48J3

Printer, 100 VAC, 47-440 Hz, USA Plug

APP-48D3

Printer, +12V dc Power

33-2242568 Box of 10 black image paper rolls
58-2079130 Spare Mating DB-25S Data Connector (1
supplied)
APP-TR5A

Takeup/Rewind Accessory, 115 VAC

. APP-TR5E

TakeuP/R.ewin.d Accessory, 230 VAC

I APP-TR5D

Takeup/Rewind

I

ACCeS~ry~~

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-25

APP-M20
Rugged Mobile
20-Column Thermal Printer
FEATURES
• Ruggedized construction - designed to comply
with MIL-STD-202E and 810C for shock, humidity, and vibration
• +12V dc powered, for use with standard vehicle battery; AC models also available
• Low power consumption - 1.2 A printing, 360
mA standby
• Illuminated printout, extra TALL character
printing and paper advance features for easy
viewing day or night
• 20 column output with the full 96 ASCII character set available
• Quiet non-distracting thermal printing
• Compact - smaller than a CB radio
• Slide mounted for easy removal
• Available in Serial, Parallel or IEEE-488 compatible versions

APPLICATIONS
• Radio communications system with many varied applications
• Portable personal computers
• Test and measurement equipment for field use
• Hard copy output for medical and analytical
instrumentation
Diagnostic test equipment
Remote data loggers and factory automation
productivity systems

GENERAL

DESCRIPTION

The APP-M20 is a 20 column thermal printer specifically designed for use in harsh evironments. With its slide mount
and illuminated printout, the APP-M20 is particularly well
suited for use in mobile applications. The mechanical specifications (except for the mounting bracket) and electrical
specifications correspond exactly to those of the popular
panel mount models (APP-20Dl, APP-20D21, APP-20D3).
The APP-M20 user will benefit from the microprocessor controlled interface, compact size (smaller than a CB radio) and
quiet, inkless thermal printing. The TALL character height
printing capability, Form Feed (paper advance) and illuminated paper output slot make reading the printer output at a
glance extremely easy, both day and night. In addition, the
APP-M20 offers a special "inverted text" option, where the
last line printed is at the bottom of the printout. The APPM20 thermal printing mechanism requires virtually no maintenance outside of an occasional printhead cleaning. No replacement printheads or ribbons need to be carried. The
APP-M20 can be ordered with the bracket installed either on
the top, on the bottom (by special order), or in a panel mount
configuration making it installable virtually anywhere.

10-26

Much effort has been put into the hardware design to ensure
that the printers will stand up the the rigors of mobile operation. The APP-M20 has passed testing by an independent
laboratory for shock, vibration and humidity, conforming to
MIL-STD-202E and MIL-STD-81 ~C. Copies of these test results are available from DATEL upon request.
The APP-M20 voltage input requirements are + 10.5 to + 14.5
V dc at 1.2 A while printing and 360 mA during standby. No
special powerline conditioning is required.
The APP-M20 prints the full 96 ASCII character set across
2-15/16" (58,6 mm) wide thermal paper. A single dot line,
thick film, thermal printhead forms 5 x 7 dot matrix characters which are 0.11" (2,8 mm) high at a rate of 63 lines of 20
characters per minute. A standard 130' roll of paper will display 8,400 lines of alphanumerics at 5 lines per inch (2 lines
per cm) spacing.
The operating temperature range is from -20°C to +50°C.
The printer can withstand up to 95% relative humidity.
A mounting bracket and slides are shipped with each printer
for easy installation.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

APP-M20
FUNCTIONAL

SPECIFICATIONS

(Typical at 25°C unless noted)
(For complete specifications, refer to the standard parallel,
serial, or IEEE-488 model brochures: APP-20D1, APP20D21 , APP-20D3).

INTERFACE TYPES (3)
8-bit parallel (APP-M20D1)
Serial RS-232-C or 20 mA current loop (APP-M20D21)
IEEE-488 (APP-M20D3)

PRINT CHARACTERISTICS
Printing Rate ................. 63 lines/minute
Number of Columns ........ 20
Characters Available ...... 96 Standard ASCII
Character Heigh!... ........ 0.11" (127 mm)

PHYSICAL AND ENVIRONMENTAL
Dimensions
Overall Clearance ...... 6.16"W x 3.5TH x 11 .52"D
(156,46 x 90,68 x 292,60 mm)
Housing ................... 5.36"W x 2.76"H x 8.00"D
(136,14 x 70,10 x 203,20 mm)
Mounting Hood .......... 5.36"W x 0.75"H x 8.0"D
(135,14 x 19,0 x 203,20 mm)
Bezel. ..................... 5.25"W x 2.82"H x 0.78"D
(133,87 x 71,91 x 19,89 mm)
Weight ......................... 2.5Ibs (1,14 kg)
Operating Temp Range ... -20°C to +50°C
Storage Temp Range ...... -45°C to +85°C (Caution: the
paper will begin to darken after
several days of exposure to
temperatures in excess of
+60°C)
Relative Humidity ........... 0% to 95% non-condensing
Shock ......................... 10 gat 10 to 500 Hz

POWER
Power Requiremen!... ..... + 10.5 to 14.4V dc
Current Draw ................. 1.2 A printing; 360 mA standby
Connector .................... MOLE X receptacle with crimpon female terminals

1

:::--~~----oRDERING GUIDE

I

I

MODEL

DESCRIPTION

APP-MSOD1

Parallel input 20-column ruggedized
printer
Serial input 20-column ruggedized
printer
IEEE-488 input 20-column ruggedized
printer
Automatic, panel-mount take-up reel
(+ 12V powered)
20-column thermal printer paper (10
130' rolls)

APP-M20D21

! APP-M20D3

! APP-TRD
32-2242572

DATEL. Inc. 11 Cabot Boulevard, Mansfield. MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

I

III

10-27

APP-M48
Rugged Mobile 48-Column
Thermal Printer
FEATURES
• Ruggedized construction - designed to comply with MIL-STD-202E and 8l0C for shock,
humidity, and vibration
• +12V dc powered, for use with standard auto
battery
• Low power consumption - 2.3A printing, 1A
standby
• Illuminated printout, inverted text option and
paper advance features for easy viewing
day or night
• 48 column output with the full 96 ASCII character set, plus second 96-character set of
special symbols
• Quiet, non-distracting thermal printing; virtually maintenance free
• Compact size, slide-mounted for easy removal
• Available in Serial, Parallel or IEEE-488 compatible versions (APP-M48Dl, APP-M48D2,
APP-M48D3)

APPLICATIONS
•
•
•
•

Radio communications systems
Portable personal computers
Test and measurement equipment for field use
Hard copy output for medical and analytical instrumentation
• Remote data loggers

GENERAL DESCRIPTION
The APP-M48 is a 48 column thermal printer specifically designed for use in harsh environments. With its slide mount
and illuminated printout, the APP-M48 is particularly well
suited for mobile applications. The mechanical specifications (except for the mounting bracket) and electrical specifications correspond exactly to those of the popular panel
mount models (APP-48Dl, 2, 3).

eration. The APP-M48 has passed testing by an independent laboratory for shock, vibration and humidity, conforming to MIL-STD-202E and MIL-STD-81 ~C. Copies of these
test results are available from DATEL upon request.
The APP-M48 voltage input requirements are +10.5 to
+ 14.5V dc at 2.3 A average while printing and 1 mA during
standby. No special powerline conditioning is required.

The APP-M48 user will benefit from the microprocessor controlled interface, compact size, and quiet, inkless thermal
printing. The inverted text option (last line printed is at the
bottom of the printout), Form Feed (paper advance) and illuminated paper output slot make reading the printer output at
a glance extremely easy, both day and night. In addition,
the APP-M48 thermal printing mechanism requires virtually
no maintenance. No replacement printheads of ribbons
need to be carried. The APP-M48 can be ordered with the
bracket installed either on the top, on the bottom (on special
order) or in a panel mount configuration making it installable
virtually anywhere.

The operating temperature range is from -20°C to +50°C.
The printer can withstand up to 95% relative humidity.

Much effort has been put into the hardwhere design to ensure that the printers will stand up to the rigors of mobile op-

A mounting bracket and slides are shipped with each printer
for easy installation.

10-28

The APP-M48 prints the full 96 ASCII character set across
5" (127 mm) wide thermal paper. A second 96-character set
includes special characters such as currency symbols, European punctuation, mathematical operators, Greek letters,
etc. A single dot line, thick film, thermal printhead forms
5x7 dot matrix characters which are 0.11" (2,8 mm) high at a
rate of 1.2 lines per second.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

APP-M48
FUNCTIONAL SPECIFICATIONS
(Typical at 25°C unless noted)
(For complete specifications, refer to the standard parallel,
serial, or IEEE-488 model brochures: APP-48D1, APP48D2, APP-48D3)

INTERFACE TYPES (4)
8-bit parallel (APP-M48D1)
Serial RS-232-C or 20 mA current loop (APP-M48D2)
RS-232-C/20 mA loop with 132 byte buffer (APP-M48D4)
IEEE-488 (APP-M48D3)

PRINT CHARACTERISTICS
Printing Rate ................ 72 lines/minute
Number of Columns ........ 48
Characters Available ...... 96 Standard ASCII plus 96
special characters
Character Heigh!... ........ 0.11" (127 mm)

PHYSICAL ENVIRONMENT
Dimensions
Overall Clearance .......... 9.25"W x 4.00"H x 10.44"D
(234,95 x 101,6 x 265,18 mm)
Housing ....................... 8.20"W x 2.84"H x 8.14"D
(208,28 x 72,14 x 206,76 mm)
Mounting Hood .............. 5.36"W x 0.75"H x 8.0"D
(135,14 x 19,0 x 203,20 mm)
Printer Beze ................. 19.25"W x 3.25"H x 0.75"D
(234,95 x 82,55 x 19,1 mm)
Weigh!... ..................... 6 Ibs. (2.7 kg)
Operating Temp Range ... -20°C to +50°C
Storage Temp Range ...... -45°C to +85°C (Caution: the
paper will begin to darken after several days of exposure
to temperatures in excess of
+60°C)
Relative Humidity .......... 0% to 95% non-condensing
Shock ......................... 109 at 10 to 500Hz

POWER
Power Requirement... ..... +10.5 to +14.4 V de
Current Draw ................ 2.3A printing; 1.0A standby
Connection .................. 5' long power cord

ORDERING GUIDE
MODEL

DESCRIPTION

APP-M48D1 Parallel input 48 column ruggedized printer
APP-M48D2 Serial input 48 column ruggedized printer
APP-M48D3 IEEE-488 input 48 column ruggedized
printer
APP-48D4

Same as APP-M48D2 but includes 132 character input buffer for continuous throughput

APP-TR5D

Automatic, panel-mount take-up reel (+ 12V
powered)

32-2242572 48 column thermal printer paper (10130'
rolls)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-29

II

APP-TR1,2,5
Take-Up/Rewind Reels
for Panel Printers
FEATURES
• Automatically takes up printout from all DATEL
thermal printers and many other brands of
panel mount printers
• Allows manual paper withdrawl for easy viewing while powered ON
• Very fast rewind
• Easy-lo-install panel mounting
• AC and DC powered models available
• +12 VDC model is ideal for vehicular/mobile
applications
• Low cost - dependable

DESCRIPTION
The APP-TR Series Take-up/Rewind Accessories automatically take up the printout as it is generated by DATEL panelmount thermal printers. The APP-TR is also compatible with
other brands of panel-mount printers which use similar width
paper. The APP-TR is a completely self-contained unit, designed for panel mounting.
The front bezels of the APP-TR1, APP-TR2, and APP-TRS
match the bezels of DATEL's DPP-07, APP-20, and APP-48
thermal printers respectively. The APP-TR2 is also compatible with DATEL's low-cost MPP-20 printer.
The APP-TR bezels mount on hinges which allow the user to
swing open the unit for easy access to the paper rollers.
The paper is taken up by a slotted take-up shaft which does
not require the use of spools or axles which are easily lost.
Also, the APP-TR take-up mechanisms have been designed
so that the paper can be pulled out and read while the power
is on; when the paper is released it is automatically rewound.
A front panel mounted three-position switch (TAKE UP/OFF/
REWIND) is the only operator control on the unit. The
"TAKE UP" position is the normal position, while the "REWIND" positions allows the paper to be quickly rewound to
its original state (first line printed is at the outside of the
roll).

ORDERING GUIDE
APP-TR1A
APP-TR2A
APP-TRSA

The APP-TR is available with several power supply options:
90 -130VAC (for American and Japanese line power), 210260VAC (European), and a +12V dc version ideal for mobile
applications.
All of the necessary mounting hardware is provided for
mounting the APP-TR in a standard 1/8" thick panel. The
APP-TR must be mounted directly below and in line with the
companion printer; the paper printout exiting from the printer
must travel straight down to enter into the take up reel properly. The distance between the printer and the APP-TR depends on how much usable panel space is available, and
how much of the printout the user wishes to display.

10-30

APP-TR1E
APP-TR2E
APP-TRSE
APP-TR10
APP-TR20
APP-TRSD

DPP-Q7 compatible (1.7S" paper), 11SVAC powered
APP-20/MPP-20 compatible
(2.31" paper), 11SVAC powered
APP-48 compatible (S.O' paper),
11SVAC powered
OPP-07 compatible (1.7S " paper), 230VAC powered
APP-20/MPP-20 compatible
(2.31" paper), 230VAC powered
APP-48 compatible (S.O" paper),
230VAC powered
DPP-07 compatible (1.7S" paper), + 12V dc powered.
AP(:>-20/MPP-20 compatible
(2.31" paper), +12V dc powered
APP-48 compatible (S.O" paper),
+ 12V dc powered

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194iTEL (508) 339-3000iTLX 174388/FAX (508) 339-6356

APP-TR1
FUNCTIONAL SPECIFICATIONS
25°C unless otherwise noted)

(Typical @

COMPATIBILITY
APP-TR1A, E, 0:

OATEL's OPP-Q7 Panel-mount
Thermal Printer or any printer using 1.75" - wide (max.) paper.

APP-TR2A, E, 0:

OATEL's APP-20 and MPP-20
Panel-mount Thermal Printers or
any printer using 2.31" - wide
(max.) paper.

APP-TR5A, E, 0:

OATEL's APP-48 Panel-mount
Thermal Printer, or any printer
using 5.00" - wide (max.) paper.

PHYSICALIEVIRONMENTAL
Case Dimensions
APP-TR1f
APP-TR2: 6.56"W x 3.25"H x 5.75"0 (166,62 x 82,55 x
146,05mm)
APP-TR5: 9.25"W x 3.25"H x 5.75"0 (234,95 x 82,55 x
146,05mm)
Panel Cutout Dimensions
APP-TR1f
APP-TR2: 5.944"W x 3.040"H
APP-TR5: 8.634"W x 3.040"H

(150,977 x 77,21mm)
(219,30 x 77,21mm)

(Mounting hardware supplied for all models)
Weight
APP-TR11
APP-TR2: 1.051bs
APP-TR5; 1.25 Ibs

POWER
Requirements
APP-TR1A1
APP-TR2A: 90 to 130VAC, 0.18A, 10W, 47 to 440Hz
APP-TR5A: 90 to 130VAC, 0.3A, 16W, 47 to 440HZ

Case Construction: Aluminum case, plastic front bezel
Operating Temperature Range: 0 10 + 50°C

APP-TR1 EI
APP-TR2E: 210 to 250VAC, 0.09A, 10W, 47 10 440Hz
APP-TR5E: 210 to 260VAC, 0.15A, 16W, 47t0440Hz
APP-TR101
APP-TR20: +10 to +14V dc, 0.9A, 10W
APP-TR50: +12to+14Vdc, 1.5A, 16W
Fuses
APP-TR1fTR2A 1/2 Amp. SLO BLO
APP-TR1A1APP-TR2A: 1/2 Amp, SLO BLO
APP-TR5A: 1 Amp, SLO BLO
APP-TR1 EfAPP-TR2E: 1/4 Amp, SLO BLO
APP-TR5E: 1/2 Amp, SLO BLO
APP-TR1DI
APP-TR201
APP-TR50: 2 Amp, SLO BLO
Power Cords
"A" models: 6', USA-style line cord
"E" models: 6', European-slyle line cord (2 prongs and
ground shell)
"0" models: 6'Iine cord which spade lug termination (3):
BLACK: +12V
WHITE: 12V return
GREEN: Chassis ground

PERFORMANCE
Paper roll capacity:
Paper tension:
Paper rewind time:

150' (all models)
2 oz. min, 12 oz. max
45 seconds for 150' roll

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·1194ITEL (508) 339·3000ITLX 174388/FAX (508) 339·6356

10-31

DPP-Q7
BCD Input, 7-Column
Thermal Printer
FEATURES
• 6 Numeric columns and sign
• 4 Lines/second OEM-reliable thermal printer
• Includes all electronics for parallel BCD input
Selectable leading zero blanking
• Positive or negative true TTL/DTl inputs
• Available in 100, 110, 230 VAC versions
• 4.4 Pound panel-mount featherweight
• No ink, ribbons or hammers; virtually maintenance free

GENERAL DESCRIPTION
Imagine a low cost 7-column panel-mounting printer just
slightly larger than most digital panel meters. Imagine this
lightwight, high-reliability digital panel printer installed in
your instrument or system front panel. And imagine an inkless, non-impact thermal printing method with only two
moving parts which will last for years.
This is DATEL's miniature 4 line per second DPP-Q7 thermal
panel printer. A no·nonsense, simple to apply, OEMdesigned digital output device that weighs in at only 4.4
pounds (2.0 Kg). OEM features are designed into the
DPP·Q7 such as selectable leading zero blanking, selectable positive or negative true coding inputs and choice of
100 to 230 VAC line power. Full parallel TIL input BCD electronics are included as standard.
Other OEM design features include a selection of printout
formats, manual print and advance front panel switch, and a
low paper switch output. A unique mounting technique uses
an aluminum housing which attaches directly through a
front panel cutout. This housing permanenty holds the electronics, although the mechanical assembly can be completely removed for paper replacement using a single front
panel thumbscrew.
As the mechanical assembly is removed, it disconnects
from the internal electronics PC board connectors, so that
no lethal power voltages are exposed during paper reloading. However, the external PC board connectors at the rear
of the case remain connected to the signal inputs. The
housing supports the weight of the mechanical assembly
and is mounted on a front panel through a 4.50" x 2.78" cutout and secured by four screws. Three DPP-Q7 panel printers can conviently be mounted across a 19" x 3 1/2" high
rack-mount panel.
OEM pricing makes the DPP-Q7 ideal for instrument products. Comparable impact parallel printers with BCD decoding and drive electronics usually list for more than the DPPQ7.

10-32

Standard 1 3/4" wide thermographic papers are used in
handy 130 foots rolls giving about 7,800 lines per roll with 5
lines per inch. The 7-segment digits are .155" high with leltof-digit decimal points selectable at each digit. Seven column printing formats include sign, and six digits or 2channel (ident) digits, sign and 4 data digits. Other 7column decimal formats, as well as hexidecimal formats, are
also available.
The DPP-Q7 Digital Panel Printer extends back 8.62" from
the front surface of the mounting panel, including space allowance for the two 30-conductor PC board connectors and
AC fuses.
Three universal AC line voltages (100,115, and 230 VAC)
will power the DPP-Q7 Printer at approximately 20 watts.
The DPP-Q7 is ruggedly built, using a simple, but sophisticated mechanical design which is optimized for heavy duty
OEM applications. A proprietary printhead character coating allows the head to be conservatively rated at 3 million
lines, minimum.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DPP-Q7
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C unless noted)

GENERAL
Number of columns 7-Column formats available:
a) Leading ± sign and 6 decimal digits
b) 2 Leading ident or channel digits, ± sign and 4
data digits
Decimal digit format:
7-segment 0 to 9 digits .t55" (4mm) high with 100 slant
and selectable left decimal point.
Printing method:
Thick film thermal print head, black characters on white
paper (using DATEL 32-2242570 paper)
Printer paper:
1.75" wide x 130 feet long, (44,5 x 39,62 m), thermal paper with the thermal surface facing away from the center
of the roll (DATEL PIN 32-2242570)
Paper advance:
Via stepper motor

PERFORMANCE
Max. printing rate: 4 lines per second
Print and paper advance cycle: 250 milliseconds
Line spacing: 0.2 inch (5mm)
Line density: 5 lines per inch
Line capacity per paper roll: approx. 7,800 lines
Minimum print head life: 3 million lines

INPUTS
DTUTTL compatible, selectable positive or negative true,
level sensitive, TTLLS low power Schottky logic used on all
inputs.
Logic Levels:
Positive true:

+2.0V s "I" s +5.0V
OV s "0" s +0.5V

Negative true:

OV s "I" s +0.5V
+2.0V s "O"s +5.0V

Note: Pullup resistors to +5V may be optionally removed
on all inputs and output.
Data: (24 lines)
Full parallel BCD (1-2-4-8), selectable positive or negativetrue, 1 TTLLS load plus 10 K Ohm pullup to +5V. May be
used with Form A (normally open) or Form B (normally
closed) switch closure inputs. Level sensitive (rise-time
non-critical). Data is stored.
Change Data Polarity: (Pin Cl-Bll)
Selects input polarity of data, decimal pOints and ± sign simultaneously.
LOW = positive true coding
HIGH = negative true coding
6 TTLS loads, plus 1K Ohm pullup to +5V, level sensitive

Print and Advance Command: (Pind Cl-BI4)
Level sensitive for Form A or Form B contact closure selectable positive or negative true.
1 TTLLS load plus 10K Ohm pullup to +5V.
Pulse Width: 1 microsecond to 200mSec (data must be valid
1 J.lsec after leading edge and 500 n Sec. before the print
command).
Maximum print command rate: 3 per second
Paper advance automatically occurs after digit printing.
Holding print command TRUE longer than the busy output is
true (200 to 250 mSec. typ) causes continuous 4 lines/sec
printing.
Change Print Polarity: (Pin Cl-B7)
HIGH = negative true coding
LOW = positive true coding
1 TTLLS load, plus 10K Ohm pullup to +5V, level sensitive.
Leading Zero Suppress: (Pin Cl-B4)
blanks all leading zero's to the left of decimal pOint except a
zero just left of the decimal point.
HIGH = Leading O's blanked
LOW = full print (no suppression)
2 Low Power TTL loads, plus 10K Ohm pullup to +5V, level
sensitive.
Minus Sign: (Pin Cl-Bl)
Selectable positive or negative true using data level select
input.
1 TTLS load plus 10K Ohm pullup to +5V, level sensitive.
Plus Sign: (Pin Cl-A5)
(Selectable positive or negative true using change data polarity input). (Minus sign must also be printed since it is
used as the horizontal portion of the plus sign).
1 TTLS load plus 10 K Ohm pullup to +5V, level sensitive.
Note: Printing "plus" sign only results in vertical portion of
plus sign. See above. Usable as 100% over-range digit.
Blanked Character:
Created by loading 1-1-1-1 in a given column. Can be hardwired.
Decimal Points: (6 lines)
1 TTLS load plus 10 K Ohm pullup to +5V, level sensitive.
(Selectable positive or negative true using change data polarity inputs).
No-Print Paper Advance: (Pin Cl-A3)
Ground this line .5J.lS to .1 sec. minimum to advance one
line. Hold to ground for continuous advance at 6.7 lines per
second.
No Print Paper Advance:
May also be created by loading the illegal BCD character
1-1-1-1 in all decimal locations, and disabling all decimal
points and ± signs, then initiating a print/advance command.
Test: (Pin C2-B6)
LOW = ± .8 .8 .8 .8 .8 .8 printout when print/advance command is given.
1 TTLS load plus 10K Ohm pullup to +5V, level sensitive (2
minutes max, this test, DPP-7)
Change Busy Polarity: (Pin Cl-A2)
HIGH = positive true busy out
LOW = negative true busy out
1 TTLLS load, plus 10 K Ohm pullup to +5V, level sensitive.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-33

•

DPP-Q7
OUTPUTS
OTL/TTL compatible
Positive true:

OV :0; "0" :0; +O.4V
+ 2.4:0; "1":0; +5.0V

Negative true: +2.4V:o; "0" :0; +5.0v
OV:o; "1":0; +0.4V
Busy: (Pin C2-B12) Open collector TTL 7438 with 1 k
ohm pullup to +5V)
Remains TRUE during print and advance cycle (approximately 200 to 250 milliseconds). Data inputs may be change
500 nanoseconds after transition to TRUE. Next print command can be enabled when busy goes FALSE. Selectable
positive or negative true. 10 TTL loads.
Out of Paper: (Pin C2-B4)
The switch opens when approx. 6' (2m) of paper are left on
roll. Paper roll visually indicates "low paper" within 10 to 15
feet (3 to 4.5m) of end of roll using red stripe on roll. Switch
is in series with PC board contacts which disconnect if printer mechanism is not completely seated in case. Open
switch contact or print mechanism removed will disable both
local and remote print command. Pin C2-B4 has an internal
1 K ohm pullup to +5V normally grounded by switch before
paper is low.
FRONT

PRINTOUT

Users requiring full alphanumeric printout (upper and lower
case letters, numerals, punctuation and special characters
should select Datel's model APP-20 thermal printer using a
5 X 7 dot matrix character format: The DPP-07 is also available as an extended numeric printout called hexadecimal
which includes 6 extra letters (A through F) beyond the 10
numerals. Hexadecimal code is ideal for machine microprocessor systems. Because of the 7-segment format, the b
and d must be lower case. Also, the 1-1-1-1 code will no
longer blank a column, although leading zero suppression
may be selected. The type 4 printout (.9.9.9 .9.9.9 decimal
or .F.F.F .F.F.F hexadecimal) with a blanked center column
is available for two data points printed on the same line.
Hexadecimal Coding
Input
0000
0001
0010
0011
0100
0101
0110
0111

Printout
0
1
2
3
4
5
6
7

Input
1000
1001
1010
1011
1100
1101
1101
1111

Printout
8
9
A
b
C
d
E
F

PANEL

Power On
Red light emitting diode illuminates when power is applied.
End of Paper
Yellow light emitting diode illuminates when the paper
supply has 2" remaining at which time the printer stops
printing.
Paper Roll Replacement:
By sliding out front panel printer assembly. PC board interlock automatically disconnects all power to printer assembly and power supply with electronics remain with
housing case. Removal by a single front panel 1/4 turn
thumbscrew.
Print/Remote/ Advance
Front panel 3 position toggle switch, stable in center position (REMOTE), must be held in top (ADVANCE) or bottom (PRINT) positions.
ADVANCE:
When switch is held up, the printer continuously advances paper without printing at a 6.7 line per second rate.
REMOTE:
Center position enables all external inputs.
PRINT:
When switch is pushed down, printer prints one line and
stops. After print and advance, external input is accepted even if the switch is held down.
TEMPERATURE

RANGES

Operating: 0 to + 40°C (to +50°C at derated speed)
Storage: -25°C to +85°C (Paper darkens above +60°C)
Active printhead temperature sensor is employed to adjust
drive energy to the existing head temperatures.

10-34

HEXADECIMAL

POWER

SUPLY

OPP-Q7A:
105-125 VAC, 47-440 Hz@40wattsmax (10 watts, typ
standby) U.S.A. grounding line cord. Jumper-selectable>
for 230 VAC.
OPP-Q7E:
205-240 VAC, 47-440 Hz @ 40 watts max (10 watts, typ
standby). 2 prong with 8 gnd. shell line cord. Jumperselectable> for 115 VAC.
OPP-Q7J:
90-110 VAC, 47-440 Hz @ 40 watts max (10 watts, typ
standby)
AC Fuse:
DPP-07A1J: .25" x 1.25" Buss MOL or equivalent
1/2A SLO-BLO
DPP-07E: 1/4A SLO-BLO
Notes:
1. Case is grounded to AC power ground
2. +5V, 200mA max. logic power out available
>Jumpers are located in the printer housing and are accessable when the print module is removed.
CONNECTORS
Data and Controls:
(2)30-conductor (15 per side)
Double-sided PC board connectors.
0.1" centers. Datel #58-2073083 (included)
AC Power
Supplied captive line cord with European or U.S.A. plug.
WEIGHT (with housing and full paper roll)
4.4 Ibs. (2,0 kg)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DPP-Q7
DIMENSIONS
Front panel mounting cutout:
4.50" W x 2.72" H (115 mm x 69 mm)
Front panel Bezel dimensions:
5.25" W x 2.82" H (134 mm x 72 mm)
Depth behind front surface of mounting panel including
clearance for rear PC connectors and fuses:
8.7" (221 mm)

MODEL NUMBER
DPP-Q7_-

I

I
I

I

Power Supply

Printout Format

,--------,

'I

[Characters
I

A = 115VAC'
B = 230 VAC'
J = 100 VAC I

1
2
3
4
5
6

= ±.9.9.9.9.9.9
= .9.9±.9.9.9.9
= .9±.9.9.9.9.9
= .9.9.9 .9.9.9

=

.9.9.9.9 .9.9

LeaVe}
Blank

H

=

Decimal
Digits

Hexadecimal Digits
--

------.-

= .9.9.9.9.9 .9

DPP-Q7A, E, or J
OEM Versions available (same prices)
DDP-Q7-9554 ................ no panel belt
'Include jumper-selectable dual
DPP-Q7-9555 ................ no connectors
voltage 115/230V transformers
DPP-Q7-9556 ................ no label,
no connectors
DPP-Q7 Printer stand for bench-top applications ............. 33-8193200
APP-TR1 A Automatic take-up reel/Rewind accessory, 115 VAC powered.
APP-TR1 E Automatic take-up reel/Rewind accessory, 230 VAC powered.

•
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

10-35

MPP-20
Low-Cost Serial/Parallel Input
20-Column Thermal Printer
FEATURES
• Two communications modes:
• RS-232-C serial
• Centronics® -compatible parallel
• No external interface logic required
• Two character sizes, 20-characters per line
• Prints full 96-character ASCII set with 31
additional special characters
• Enhanced and inverted character output
formats via data-encoded commands
• Front panel SELF-TEST and FEED controls
• SUPERTORQUE mode for operation in
sub-zero temperatures
• AC- or dc-powered models
• Rugged, lightweight 4.2 pounds design
• Low cost
• Very high OEM reliability
• Quiet, virtually maintenance-free operation

The MPP-20 Thermal Printer is the newest addition to DA TEL's proven line of OEM-reliable thermal printers. Able to
communicate in both serial and parallel modes, the low-cost MPP-20 thermal printer's rugged construction, variable
output styles, and ease of application make it the choice of OEM's and end-users alike.

GENERAL

DESCRIPTION

Able to use the full set of 96 ASCII characters and 31 special characters, the device prints output characters on 2-5/
16 inch wide (58,6mm) thermal printer (see Figure 1). The
printout has 20 columns of characters with the print rate varying as a function of the print format selected. Whether operating in the serial or parallel mode, all signals interface
with the device via a single connector which attaches to the
rear of the enclosure. The user accomplishes all unit wiring
using a 30-pin card-edge connector (included).
The MPP-20 uses microprocessor-driven logic for timing
character generation, printhead drive, and motor stepping.
This technology accounts for the small size of the MPP-20
printer, at the same time making it easy to install and maintain.
The serial mode of operation uses straightforward two-,
three-, or four-wire cabling schemes. One line carries serial
transmissions of data to the MPP-20. Two other lines provide handshaking and status monitoring while the fourth is a
system ground. The host queries the MPP-20 to detect
when it is ready to accept data.
When ready, the MPP-20 loads one printable line of characters (20 columns wide) into an internal data buffer. The
MPP-20 then halts any data input for a short period of time
while it prints the line and advances the paper one line.
Parallel data operations are designed to be compatible with
the Centronics® data bus configuration. This configuration
has become an accepted de-facto standard for simple data
transmission. The data is present on the data bus in the
form of an eight-bit word. The MPP-20 loads and interprets

the data word upon receipt of a strobe signal from the host.
The MPP-20 issues a negative going acknowledge pulse
upon storage of each character.
In either mode, the MPP-20 interprets the received ASCII
code into a printable character via a look-up table resident
in the microprocessor's memory. The character is then fed
to the print control logic for storage in a print buffer. After
storing 20 consecutive characters (or spaces, punctuation,
etc.), the print head burns an image of the characters onto
the term perature-sensitive paper. The print drive logic controls a stepper motor which in turn drives the paper roll. The
speed at which the motor turns is directly a function of the
various output attributes selected (see Table 1). Selection
of some attributes, such as ENHANCED feature, require
longer burning time thus affecting the overall throughput
rate. For instance, selecting the SUPERTORQUE attribute,
used to drive the motor slowly in colder environments, would
also add to the total throughput.

OR~~~I~~ p~I~I~E--------1
I.MODEL
I MPP-20A
I

MPP-20D

I

MPP-20E

I

MPP-20J
32-2242572
58-2073083

115 VAC-powered, USA-type power
cord and plug included
+ 10.5 to + 15V dc-powered, Molex
connector and pins included
230 VAC-powered, European-type
power cord and plug included
100 VAC-powered, USA-type power
cord and plug included
Black printout paper, 10 rolls
Connector, input/output, dual 15
pin 0.100 inches on center,
cardedge type (one included with
each printer)
Take-up/Rewind Reel

I'

J'

APP-TR2A/E/D/J

.------,-~--".-,,----"--.'''-,---------

10-36

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

MPP-20
FUNCTIONAL SPECIFICATIONS

f

(Typical at 25°C)

I Parameter

IMin.' Typ.)

Print Rate (1)
Normal Size

I

!

Max'l

90

i
I

50

Tall

(TTL- and TTLS- compatible)

LEVELS

1":in~":~~~p~"

I

lines/
minute
lines/
minute

I

VOLTAGE

I

:-~%~~o~~z!

Units

1

PRINTOUT

1

i

I

I

Max. 1 Units
+0.8

'

f

i
I

High

1+24

+5.0

Volts dc
(logic 1,
or True)

+0.4

Volts dc
(logic 0,
or False)

+5.0

Volts dc

I

Line Density
Normal Size

I

7
3

Tall

3.8
1.2

i

I

lines/inch
lines/inch
lines/inch
lines/inch

I

Outputs
Low

10
I

I

I

Line-to-Line Spacing
Normal Size

0.14

Tall

0.26

I 6.5

I

0.10
2.5
0.20
5.1

Height, Tall

I
Character Format
Character
Horizontal Spacing -

+24

I i i (logic 1, I,
I

1

inches
mrn
inches
mrn

PRINT

I.

5X7

. I
dot matnx

2.8
0.11

mrn
inches

MECHANISM

370
680

'T"

.

I
,
130 x 101 -

Mechanism Life

!5000

Range(2,4)
Operating

Storage

ms
m

i -

Relative Humidity
no condensation
5.8
17

I
DC Models

400
1.6

watts,
idling
watts,
printing
I mA, idling
1
amps,
printing

r------- -. _ _.L..-......L._....L...._.l...

I

;;i:;~; REQ~I~i~~! ;~ -I~~:::;-I

I

~requency Range

Frequency
MPP-200

I

47
90
47

I

-

I

100

1

-

440
110
440

I

.10.5,.12.15 I
I

1

[,-1- ~ 1-- 1-----

1
1

I

-20

+25

I

+50

Degrees I
Celcius

+85

Degrees
Celcius

1

1-45

90

..l.__

I Percent

.J_ --------i

PAPER

I

I', MPP-20J

character
life
hours

!

CONSUMPTION

AC Models

I "

ENVIRONMENT

'I~Temperature
see
table
1

i

Pnnthead Life

I
Line Feed Cycle Time
Normal
Tall

or True)

f

~ _ _ ~..J,. __ ,--,-~_.:...,_,l.._.~.~..J

i

Character Size
Height, Normal

High

I

inches
mrn
inches
mrn

i 3.6

POWER

Volts dc
(logic 0,
or False) ,

Hertz
Volts
Hertz
!
Volts, dc I
regulated

Data Capacity (3)
Normal Size
Tall
Size
Type

Lines
- 2.31 inches by 140 foot
Black on white, DATEL number
32-2242572

NOTES
1. Transmission at 9600 baud.
2. Paper darkens after 48 hours of exposure to
temperatures exceeding +60 degrees Celcius.
3. Capacity dependent upon the mix of normal and tall
characters.
4. +50 degrees Celcius operation is for continuous
operation. Derated throughput is usable up to +55
degrees Celcius.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10·37

II

MPP-20

The basic print cycle at 9600 Baud lasts 667 milliseconds.
This serial mode print cycle reflects a 640 ms-Iong busy
state and a 27 ms-Iong ready state.

AVAILABLE TYPE
ATTRIBUTES;

No,. ... o.l.
Nor~o.l'

ACTUAL OUTPUTS WITH
} VARIOUS OUTPUT
ATIRIBUTES
ENABLED (SELECTED)

no't oenho.nc:ed
.. nhO;nc:.d

Tall, not ~nh~nc~d
Tall, ~nhQnc~d

"1.nd'l-nO

apow

(1.X.~)

p.\.J .... UI

... ,,::.:~s!+O· .. u.
o:i8.aaCio9>.IfAlo.I1:III.Ol£ ....
pqrstuvwxyz{: } .....

\] t _ 1 a.bcd«f ---," A3(+5V)
22on~

:

?

EOP
TO USER

27Of1.(>

·S1
-'-

:

B6(EOP)

~

B10(GND)

~

+3V

+.5V

,

,
,
I

Figure 3. EOP Signal Support Circuit (User-Supplled)
With this circuit in place and the
print module present but out of
paper, the EOP state supports
approximately 15 TTL loads (24
mAl. Removing the print module
assembly results in pins A3, B6, and
810 being disconnected. The circuit
shown in Figure 3 supports approx·
imately 1 TTL load (1.6mA).
XON/XOFF (Pin A7): The MPP-20 uses this serial control
line to notify the user of its status.
Three basic conditions trigger
activity on this line:
1) At completion of any lengthy
operation, such as printing, the
MPP·20 issues an XON control
character to the user.
2) Upon receipt of an XON control
character from the user device,
the MPP·20 echoes a single
XON, indicating that the printer is
ready to receive.
3) The MPP·20 issues a single
XOFF whenever the MPP·20
enters the busy state for reasons
uncontrolled by user software.
Typically, TEST, FEED, and EOP
conditions trigger this state.

SUPERlORQ (Pin 87): Grounding this pin lowers the paper
feed stepper motor frequency,
providing extra torque in cold
environments if necessary. Printer
throughput is somewhat reduced.
This pin is normally at a TTL high
level (+5 Voltsdc.) See Table 1.
ENHANCE (Pin 88): If this pin is logically low when the
print cycle begins, the line prints bold
by performing a double burn of each
dot.
TEXT/LIST (Pin 82): A logic low on this pin puts the printer in
LISTER mode, which causes the
characters to appear right side up when
viewed from the front panel. The most
recent line printed appears at the top of
the printout while the first line appears
at the bottom.
Floating the pin (no connection = high)
puts the printer in the TEXT mode. In
this mode, the characters appear
upside down when viewed from the
front panel. Removing the paper from
the printer and inverting it so that the
characters are right side up, the printout
appears as normal text. Definition of
the print direction must be established
before starting the print cycle.
NEG/POS TRUE: Parallel data may be sent either
(Pin AS)
positive or negative true. Parallel data
may be inverted, for Centronics·
compatibility (positive-true data operation), by tying this pin to logic ground.
SO SUPPRESS: A logic low on this pin prevents SO
(Pin A15)
characters from taking effect. Does not
affect the tall character select line, pin
811.
TALL CHARACTER: The TTL signal on this pin identifies
characters as tall or normal (high for
(Pin 811)
tall) as an alternative to SO/51 codes.
This line also functions during serial
operation and overrides the 51 control
character (but not the SO). With the
NEG/POS TRUE pin AS floated (high),
tall characters are not available, and
SOISI therefore takes control. Centronics-compatibility requires that this pin
be grounded whenever positive true
data is selected (pin AS grounded).

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

•
10-39

MPP-20
Control Characters

The MPP-20 responds to a set of 15 specific control characters,
each causing the printer to perform a specific function. These
functions, their mnemonics, and hexidecimal codes appear in
Table 3.

Table 3. MPP-20 Responses to Control Characters
MNEMONIC

HEX CODE

NAME

NUL
BS

00
08

Null
Backspace

HT

09

Horizontal Tab

LF

OA

Linefeed

VT

OB

Vertical Tab

FF
CR
SO

OC
00
OE

Form Feed
Carriage Return
Shift Out

51
DC1

OF
11

Shift In
Device Control 1

DC2

12

DC4

14

SUB

1A

(XON)
Enhanced Print
Request
Cancel Enhance
Request
Substitute

CAN

1B

Cancel

RS

1E

Paper Feed

10-40

ACTION PRODUCED

None
Moves the column pointer back one position, deleting one character. On reaching column 1, the printer ignores subsequent BS
commands.
Successively indexes the column pointer to positions 1, 4, 9, 15, and
20. Upon reaching position 20, the printer no longer responds to HT.
Advances the paper by one line. The amount of paper fed increases
if tall characters have been requested by either invoking the SO
state or if a logical "1" is the MSB olthe parallel data input (bit 7, pin
B11.) LF clears the line buffer without printing and resets the
character column pointer to column 1.
Causes the printer to skip 5 lines. Does not print the data in the
buffer; therefore, it is lost unless first printed as a result of receiving a CR. Upon receipt, cancels any existing SO, DC2, and SUB
flags in the flag register. The column pOinter resets to position 1.
Head of form sensor will interrupt VT.
Same as VT except skips 11 lines. Head of form sense interrupts FF.
Initiates printout of characters in line buffer and causes a line feed.
Sets the tall character mode. Cancellable either by 51, VT, FF, or
RS. USing the 50/51 control characters allows mixing tall and normal sized characters on the same line. Grounding pin A15 (SO
SUPPRESS) at the user connector suppresses the tall character
selection option. The SO state can be locked on (in both serial and
parallel modes) by holding parallel data bit 7 at logic 0 at the user
connector, pin B11.
Cancels SO state. Unit powers up in 51 state.
Causes the printer to return an XON in the serial mode one time if
idle.
Useful in systems that cannot monitor the RS-232 signal input line.
Prints an entire line bold if this character is received any time before
CR. Self-clearing after each line.
Cancels the enhanced mode.
Shifts to the alternate set of 31 special characters, if not disabled
by solder-gap SG2 closure.
Shifts back to the standard set of ASCII characters. This is the
power-up default condition.
Causes a paper feed. Cancels DC2, SO, and SUB flags in the flag
register. Feed ends after:
1) 84 lines (12") are fed, or
2) A head of form sensor returns a "stop" before 84 lines, or
3) 2 lines are fed with a "stop" signal strapped low.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194iTEL (508) 339-3000iTLX 174388/FAX (508) 339-6356

APP-20 Series
OUTLINE DIMENSIONS
INCHES (MM)

.75119.06mml
Max. Ext.

I

PANEL CUTOUT

(1.5 inches
APP·20D2)

MTG. PANEL

2.7

"'·"-"31

r

.13(3,21 _ _

4.501114.31

"I,r+

+

17

1.875

147,62)

i

L -I

1+

42 {10)1

L'25

MTG. PANEL

(3,21 DIA THRU

4 HOLES #4 Hardware

-1

NOTE
TOLERANCE: .XX ± .01 (0,25)
XXX ± .005(0,10)

2.76 max

SIDE VIEW

L~~.....====~r=====~=iiii~_J

mm)

MOUNTING DETAILS
~(4)

PANEL
PRINTER
HOUSING

(4) SPLIT LOCK,
_ .-\W
WASHER
~----

-

HEXNUT

--~~
-~

HARDWARE SIZE: #4-40 (M3)

' - - - (4) PAN HEAD SCREW

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10·41

APP-48 Series
MECHANICAL DIMENSIONS -INCHES (MM)

n

,,'k-+l
(2.54)

i

174

9.25
(234.95)

r

r~~'

2.9

8 600

r

(218.440)

i

.xx

.36
(9,14)

1

PANEL MOUNTING
CUTOUT

L~I

=

840
(213.36)

± 01

CLEAAANCE FOR NO. 8 HARDWARE

.4

(.25)

TOl

I

XXX ± ,005
(.127)

SUGGESTED MOUNTING OIMENSIONS

-,

75

PRINTER REAR VIEW

r{19.05)

1 rul--@--S-ID-E-VIE-W--@~~ ,it
~ I.

,~~,

j
TOL ± ,()2

~.;

0

FUSEHOLOEA

0

ACLINECORO@
0

51
S10

~!C(_;::

El

APP-48 FUNCTION CAPABILITY CODE
SHOo AH1. TO, TEO. Ll. LEO. SRO. Rl2. PPO. DCl

oro, co

(.51)

MOUNTING DETAILS

,- ,- _- - -J- - - -= = =:. .l.: :O=C=-K-:!W: :A~S. . _:~!~.Il- \

~.. , .. ,," '0"'''0

.~ ~

_...
__
~~~~.,

~--

cusoo." ' " ' ' /
PAN HI::AD SCREW~
NO.8 HARDWARE

·V. . . . . . .

10-42

--HOUSING MOUNTING PAD (2) SUPPLIED
DATEl 58-9548

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

MPP-20/DPP-Q7
Physical Dimensions

765('9.'3.mm)

USER'S PANEL

I

40(10Qmm)

===
===
===
===
===
===
D===

~
5.25
(133.4mm)

TOP
VIEW

r

II

'~il

===
===
===
===
===
===
===

~

USER'S PANEL

n

E
E

~~

I ~g

SIDE vIEW

2.76 MAX
(70.1mm)

~=====================~~ ~F=====JJ
--j i--

t==

25(6.25mm)

B.OO(203.2mm)

NOTE: Bezel height for DPP-Q7 is 2.82" (71 ,Smm)

-I

6mm l

CUTOUT TEMPLATE

.13(3.2)

I"

4.7501120,")

UOIt1~)

=3
.,

r+ ---------

.-----~r_------------2.78

(711.8)

~

+

,.87,

(47.12)

I

Figure 11. MPP·20 Mounting Details
.125 (3,2) DIAMETER
4 HOLES,4 HARDWARE

TOLERANCE:

,xx

± .01 (0.25)
± 005 (0.10)

.xxx

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-43

APP-M20 Series

APP-M48 Series

MTG. PANEL

S.25
(133,4mm)

E----

MOLDEO HOOD
SUPPLlEO
DATEl se·2083C165

9.25

TOP VIEW

I

'I
STANDOFFS SUPPlIEO 1-' ,"

8.2.0
(208.281

I j

"1''

I
SPACER SUPPLlEO

-~~

I

I

--8.001203,~--·-··-1

2817,lmml

781198mml

MTG PANEL

~~~-~~-~~~~-,~--~--~~

SIDE VIEW

1
2 76 max

L~l.lFl-'=~~==~~=~~===;""~-]

mml

MOUNTING BRACKET
MOUNTING BRACKET

HOUSING SLIDE GUIDES

PULL TO SLIDE OUT
PRINTER MODULE

10~44

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

APP· TR1 ,. TR2
OUTLINE DIMENSIONS-INCHES (MM)
REWIND
SHAFT

-c::r:::=====4'1~l'
ggggg
Ir
00000
1

: 00000

-.f~~~~~=11

('0000
QOOOO

TAKE·UP
SHAFT '
FUSE & FUSE HOLDER

G

I'!
111----.""

POWER CABLE

------rr-~

'---n-[I

(19.05)

)

DRAWING IS
NOT rQSCAlE

DIMENSIONS: INCHES (MM)
FRONT PANEL

TOP VIEW

RIGHT-SIDE VIEW
6.56

1166,624)

POWER CABLE

FRONT VIEW

F-----

\

APP~:,.2

FRONT

PANE~_

:
CLEARANCE FOR NO.2
HARDWARE 3 PLACES

I,

k~_--_
IL

5.944
1150,977)'------."'34"'6-1

.----------ll:65:24}

NO. 2
CUSTOMER PANEL

(8,78)

hI

I
,

,

II

325
2.340
(82,55)
(59,43) 3.040
1.140
(77,21)
(28,95)

.105
(2,66)
INCHES
(mm)

SCRE(~UAp~~I~gfKWASHER~"

/g.

r-'-------_---;/',fiJ
/

APP-TR1,2

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

10-45

APP-TR5
OUTLINE DIMENSIONS-INCHES (MM)

REWIND
SHAFT

-....:::::r:=====:::jl

00000
00000
00000
00000
00000
00000

irl===:t"" POWER CABLE

FUSE & FUSEHOLDER

DIMENSIONS: INCHES (MM)

FRONT PANEL

TOP VIEW

II

~o~~~~~~~~,~I'P~'''1'l5

I

~ I=:i]

'Lim

f.1-------:(2U~)------..f

RIGHT·SIDE VIEW
POWER CABLE

FRONT VIEW

~TR5 FRONT PANEL
r r = = ,"

-

"

"
I'

..

I

..

CLEARANCE FOR NO.2

'"Ih
I:

' U--~----;;:_-_~_-25_-_-_-_-_-_--""'..-lI-+'~,;
F

CUSTOMER PANEL

~L

HARDWARE 3 PLACES

,

,

"

(234,95) _ _--"(8"',7:.8)C--l

NO.2 SCREW AND LOCKWASHER
(SUPPLIED)

'1.140

INCHES
(mm)

~

zl;9

IL-~[-:::::---7~'O~=---'~.. ~.
~--~~~~~~

3.25
(82,55)

"!

//7

:;7~
, ,

APp·TR5

10-46

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DBM-20
20 Segment LED
Bar Meter with TTL Outputs
FEATURES
• 20-segment, high-intensity analog bar graph
display
• TTL outputs for process control or alarm circuits
• Adjustable input range from +0.1 to +2.4V dc
full-scale. Higher voltage and current ranges
(including 4-20 rnA) with user-installed options
• Instant response with no overshoot

DESCRIPTION
The DBM-20 Bar Meter is a panel-mounted, self-illuminated
20-segment red LED (Light Emitting Diode) bar display. It
accepts a dc or slowly varying input signal, converts that
signal to digital form and displays it in the form of a progression of lighted LED segments arranged to shape a single bar
graph.
The DBM-20 is particularly well-suited for trend measurement, where relative changes in the measured variable must
be easily recognized. Applications of this type include
measurement of belt speed, noise level, pollution effluent
and the like.
The DBM-20 contains 20 TTL driver pads corresponding to
the 20 bar graph LED segments. TTL outputs can be wired
from the pads to any of the four unused finger connectors.
These outputs can be used as setpoint trips in simple control loops, or to control alarm circuits. The meter also provides internal pads for the installation of additional logic circuitry, such as TTL comparitors, DIP relays, and driver les,
to be used in conjunction with the TTL outputs.

The DBM-20 features an adjustable input range from +0.1 to
+2.4V dc full scale. Other voltage and current ranges (including 4-20 mAl are easily obtained by installing resistors/
potentiometer on the provided locations. The inputs provide
high input impedance (100 KO, minimum) and a low input
bias current (10 nA, typical). The DBM-20's input configuration is single-ended unipolar.
The meter displays an instant response with no overshoot.
The user has a choice of either a Bar mode display or Dot
mode display. In the Bar mode, all LED's will light up from
the left of the display up to the high end of the input signal.
In the Dot mode, only the LED at the high end of the input
signal will light.
A red optical display filter has 20-unit graduation markings
in white. The filter may be changed by opening the housing
from the rear. The low-profile housing is a rugged, black
polycarbonate case that is impact and solvent resistent.
Its dimensions are 2.53"W x 3.34"0 x 0.94"H. Panel mounting cutout dimensions are 2.56"W x 0.97"H.

VREF~251

2KQ

FULL SCALE ~----1
ADJUST
+5Vdc L - - + - - - -...

TO INTERNAL
CIRCUITS
POWER COMMON A - - + - - - -...

VREF~ 1.25V

r----l---}.. F DOT/BAR

r--,

L ____

t----t-

CONTROL
B DOT CONTROL
H BAR CO"TROL

SIG NAL IN J --+----'\,!\A,"v-.------1

Simplified Block Diagram of DBM-20

DATEL, Inc. 11 Cabot Boulevard. Mansfield. MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-47

DBM·20
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C unless noted)

INPUT CHARACTERISTICS
Input Voltage
Range ......................... Adjustable + 100 mV dc to
+2.4V dc Full Scale, Unipolar
(R3 at rear of instrument sets
the Full Scale). Higher voltage and current inputs (including 4-20 mAl are easily
configured with user-installed
options. Factory-installed
range changes available in
OEM quantities.
Input Impedance ........ 100 KQ min.
Input Bias Current ..... 10 nA typ, 50 nA max.
Input Configuration ............................. Single-ended
Input Offset Voltage ............................. Solder-gapped to signal
ground. May be adjustable 0
to + 1.25V dc with addition of a
1 KQ user-installed pot.
LED Trip Point
Nonlinearity ............... 0.5% typ, 2% max.
Input Overvoltage ..... ±35V max.
Temperature Coefficient.. ....................... 1% of Full Scale, 0 to +50°C

Case MateriaL ........... Black polycarbonate plastic,
impact and solvent resistant.
Case Outline Dimensions (Less
Bezel) ......................... 2.53"W x 3.34"0 x 0.94"H
(64,3 x 84,8 x 23,8 mm)
Front Panel Mounting Cutout.. ................ 2.56"W x 0.97"H min. (65,1 x
24,6 mm). Thickness range
0.062" to 0.625" (1,6 to 15,9
mm).
Bezel Dimensions ...... 1.32"H x 2.92"W x 0.157"0
(33,5 x 74,2 x 4 mm)
User Circuits .............. 4Internal uncommitted 14-pin
DIP pads are drilled for user
circuits such as DIP relays
and a driver IC (to be used in
conjunction with the 20 TTL
outputs).
Power required ........... +5V dc ±0.25V dc at 250 mA
typ, regulated (unregulated
power supplies cannot be
used because of display
switching currents).
Operating Temperature Range ............... Oto+50°C.
Storage Temperature Range ................. -25°Cto+85°C.

DISPLAY
Type ........................... 20 self-illuminated red lightemtiing diodes (LED). Segment size 0.20"H x O.07"W.
Modes
Bar: ........................ All LED's light starting from
the display left side, according to the input voltage (Connect pin L, F and H).
Dot: ........................ Only one LED lights starting
from the left side according to
the input voltage (Connect
pins B and F).

INPUT/OUTPUT CONNECTIONS
Pin A ........................... Power and Signal Common.
Pin F ........................... Dot/Bar Control.
Dot mode ................ Connect pins Band F.
Bar mode ................ Connect pins F, Land H.
Pin J ........................... Signal Input.
Pin l. .......................... +5 V dc Power Input.
Pins B, C, 0, E, H,
K ................................. Connected to drilled internal
PCB pads for user circuits.

PHYSICAL/ENVIRONMENTAL
Input/Output Connector ......................... Edgeboard PC type using bottom side only. 10-pins,
0.156" centers, DATEL model
58-2073082 or equivalent (included).

10-48

ORDERING GUIDE
MODEL

DESCRIPTION

DBM-20

20-segment LED bar meter (includes
one connector)
115 VAC to +5V dc power adapter (not
included)
Edgeboard connector, 10 pins

UPA-5/500
58-2073082

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

DM-31
Single Board, 31f2 Digit
LED Panel Meter
FEATURES
•
•
•
•
•
•
•

Compact single board design
0.56" bright red 3'1. digit display
Fits Into most panel cutouts
80 dB CMRR
True balanced high-Impedance Inputs
Logic powered (+5V de @ 280mA)
Standard ± 1.999V de input range; user-installed
options set other voltage or current ranges.

GENERAL DESCRIPTION
The DM-31 is a low-cost single board DPM. The DPM adapts
easily into most test instruments and data acquisition systems.
Its compact dimensions (2" x 3.5" x 0.5") let the DPM be easily
installed into most panel cutouts. The DM-31 has provisions for
modif}(ing the voltage and current ranges.

APPLICATIONS
The DM-31 may be used for any application where a physical
or electrical parameter needs to be measured and can be
converted with user-supplied external circuits into the basic dc
voltage, current or resistance ranges which the DM-31 accepts
and displays. Such parameters include temperature, pressure,
flow rate, RPM, noise, weight, velocity, frequency and many
others. The. DM-31 is intended for applications in analytical
instruments, test and measurement equipment, data acquisition systems, research and development instrumentation,
laboratory analyzers and other devices. Industries using the
DM-31 include petrochemical, power utilities, batch and
continuous processing, telecommunications, paper, glass,
metals and chemical manufacturing, photographic, automotive
and medical services.

ORDERING INFORMATION
DM-31-1
Description
Single-Board Digital Panel Meter
(including plug connector)

Model
DM-31-1

ACCESSORIES
Part Number Description
39-2106705
14-pin dip connector
UPA-5/500
115V AC to +5V dc power adaptor
39-8194910
DM-31 mounting accessory kit

POSITIVE RAIL

,-----------+-1

-----+..

12

ANALOG RETURN

10 - - - - - - + - - L - - - . . . 1 . - - t - - - ' _...

ANALOG HIIN

8.....,.'VII\1Vr-r-i

ANALOGLOIN

9----Y

REFERENCE IN

DISPLAYTEST

-_~~

REFERENCE OUT

.---I---+-- 24

DEC PT SELECT

5 POL. ENABLE
6

f=::~~-~~~~~::~-t--14

11-----+-------'

I__--L- 7

DISPLAY ENABLE
POWER COMMON
+5Vdc

HOLD 1 3 - - - - - - + - - - - - - - - - - '

Simplified Block Diagram of a DM-31

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-49

DM-31
FUNCTIONAL SPECIFICATIONS
(TypIcal at 25° C, 2V range unless noted)

ANALOG INPUT
Full-Scale Input . ....... Refer to "FEATURES"
Range
Ranges field-modifiable.
Input Impedance . ...... 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current ...... S pA (typical) SO pA
(maximum)
Input Overvoltage ...... ±2S0V dc, 17SV RMS
continuous (maximum)
±300V intermittent
(maximum)
External Reference .... . ±100 mV to ±2V referred to
Range
-Vs
Common-Mode ........ 80 dB (typical), from dc
Rejection
to 60 Hz, with a 1 Kilohm
unbalanced input
Common-Mode ........ Both the inputs must
Voltage Range
remain within O.SV dc below
the +SV dc supply and 1.0V
dc above the -SV dc supply.
Resolution . ............ 1 mV
Display Accuracy . ...... Adjustable to ±0.1 % of
reading, ±1 count
Temperature Drift ...... Autozeroed ± 1 count over
of Zero
a 0° to +SO°C temperature
range
Temperature Drift ...... ±SO ppm of reading/oC
of Gain
(typical) ±100 ppm of
reading/oC (maximum)
Sampling Time . ........ 83.3 mS (nominal)
Sampling Rate ......... 3 conversions per second.
May be rewired for up to 20
conversions per second

PHYSICAL
External Dimensions
3.S"W x 2"H x O.S"D (88.9 x SO,8 x 12,7 mm)
Panel Cutout Dimensions (For Optional Bezel/Filter)
1.1S6"H x 2.37S"W (29,36 x 60,33 mm) Bezel/Panel thickness
0.040" to 0.062" (1,0 to 1,6 mm) (snug fit at 0.062")
Optional Snap-In Bezel/Filter Dimensions
Outside dimensions: 1.343"H x 2.S31"W (34,1 x 64,3 mm)
Display opening: 0.812"H x 2.0"W (20,6 x SO,8 mm) Front panel
bezel relief height 0.062" (1,6 mm)
Mounting Kit
Optional, includes bezel/filter, DIP connector, standoffs, and
hardware. See Ordering Information.
Weight
1.2 ounces (3Sg)
ENVIRONMENTAL
Altitude
o to lS,OOO feet (4900m)
Operating Temperature Range
32°F to 122°F (0° to SO°C)
Storage Temperature Range
-13°F to +18soF (-2S0C to 8S°C)
Relative Humidity
10% to 90% non-condensing

DISPLAY
Number of Digils ....... 3 decimal digits and most
significant 41 " digit (3V2 digits)
Decimal Points . ........ Selectable using decimal
pOint select signal lines.
Display Type . .......... LED (red. high efficiency)
Display Height ........ . 0.S6" (14,2 mm)
Overscale . ............. Inputs exceeding the fullscale range display a "+1"
MSD with other digits blanked.
Autopolarity ........... A "+" sign is automatically
displayed for positive inputs
and a "-" sign for negative
inputs. The user may blank
the polarity using the
POLARITY ENABLE line.
Power Consumption . ... +SV dc nominal, -1, +2V
regulated required. Logic
spikes must not exceed SO
mY. Use an .external bypass
capacitor· or other means to
attenuate noise. Current at SV
is 280 mA average, 4S0 mA
maximum. Current varies
rapidly as digits switch so that
unregulated supplies cannot
be used. Current is
approximately S mA with
displays blanked.
10·50

DATEL,lnc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (50S) 339-30001TLX 1743SS/FAX (50S) 339-6356

DM-31 008/DM-31 04
AC powered, 31f2 Digit
LED Panel Meters

FEATURES

• 3'12 Digit red LED (DM-3100B) and high brightness
•
•
•
•
•
•

red LED (DM-3104) models
Selectable 115/230VAC powered
Balanced high-Impedance differential Inputs
80 dB CMRR
Autozerolng capability
Allows ratlometrlc reference for drift correction
Standard:t: 1.999V dc input range; user-installed
options set other voltage or current ranges.

GENERAL DESCRIPTION
The OM-3100B and the OM-3104 are 3Y, digit LEO display
devices. The OPM's are dual AC-powered OPM's, easily
configurable for a variety of applications. The versatility is due
to logic power outputs (+5V dc and -5V dc) provided by the
OPM.
The OM-31 OOB and the OM-31 04 use 0.56" and 0.6" display
respectively. The displays are clearly visible from many feet
away in normal or dim light.

ORDERING INFORMATION
DM-3100B-l
DM-3104-1
Model
Description
DM-31008-1
31/2 Digit, LED, 115/230 V AC powered
(includes one connector
DM-31 04-1
3112 Digit, LED high brightness,
115/230 V AC powered
(includes one connector)
ACCESSORIES
Part Number Description
58-2075010
Connector, dual 18-pin, 0.1" centers

Inputs to the OPM's are balanced differential (80 dB Common
Mode Rejection). The meter accurately displays small signals
even in electrically noisy industrial environments. CMOS
circuitry results in an extremely high input impedance (1000
Megohms, typically) and a very low bias current (5 picoamps).
Inputs with a source impedance as high as 100 kilohms can
be displayed accurately. The input circuitry safely tolerates
overvoltages up to ±250V dc (155V RMS).lnputs are sampled
and displayed about four times per second.
The OPM's are designed for installations where existing dc
supplies are noisy, inaccessible, or overloaded. The meters
may be used wherever a voltage, or a unit which can be made
proportional to voltage, must be displayed with accuracy and
clarity.
The OPM's are supplied in OATEL's standard short depth
black polycarbonate case.

UPA-5/500

115V ACto ±5V dc (@500mA)
power adaptor

r---~---~-----~------~-------------4r---------~---------B9

+ ________-If-+_5V____-+-I ~

p
rO_S_IT_IV_E_R_AI_L____

ANA. RTN

Al ---~<

+5VOCPWR

~~S;~~Y65~TMON

r - - - - - - - + - - - - - - - - A8 POLARITY ENABLE

nr-r---

B18 ACHIA
A16 AC LOA

ANA.HIIN

1>:3
814

ANA. LOIN

+----__-+_....J

,.----- REF. IN

B6 _ _ _

:"---REF. OUT

A6

EXT. REF. LO
OHMS LO

---~---Ih----+---

,,'--+---VOLTAGE
REFERENCE
LM 329
16.9VI

-SV

----40---04-------_-------

A7 - - - - -......-------'....
NE.lG'-A-TI-VE-R-A..
IL----O-......---t------------::::SV~d-C
87 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
Al, R2 are optional userinstalled attenuators or shunt

A12

A7

ACHIB

ACLOB

EXT REF. LOI

-5VOUT

61-- 64

DEC PT SELECT

Simplified Block Diagram of DM-3104 and DM-3100B

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194lTEL (508) 339-3000lTLX 174388/FAX (508) 339-6356

10-51

•

DM-31008 and DM-3104
FUNCTIONAL SPECIFICATIONS
(Typical at 25°C, 2V range unless noted)
ANALOG INPUT
Full-Scale Input ........ Refer to "FEATURES"
Range
Ranges field-modifiable.
Input Impedance ....... 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current ..... 5 pA (typical) 50pA (maximum)
Input Overvoltage •..... ±250V dc. 175V RMS
continuous (maximum)
±300V intermittent
(maximum)
External Reference ..... ±1 00 mV to ±2V
Range
referred to -Vs (EXT. REF

La)
Common-Mode ........ 80 dB (typical),
Rejection
from dc to 60 Hz, with a 1
Kilohm unbalanced input
Common-Mode .••••••. Both the inputs must
Voltage Range
remain within 0.5V dc below
the +5V dc supply and 1.0V
dc above the -5V dc supply.
Resolution ............. 1 mV
Display Accuracy ...... Adjustable to ±0.1 % of
reading, ±1 count
Temperature Drift ...•.. Autozeroed ±1 count
of Zero
over a 0° to +50 C
temperature range
Temperature Drift •••••• ±50 ppm of
of Gain
reading/oC (typical) ±100
ppm of reading/oC (maximum)
Warm-Up Time ••.•....• 10 minutes (typical)
Sampling Time •...••..• 83.3 mS (nominal)
Sampling Rate ......... 3 conversions per second.
May be rewired for up to 20
conversions per second
DISPLAY
Number of Digits ....... 3 decimal digits and most
significant "1" digit (3% digits)
Brightness

........... 2400 min, 4800 typ microcandelas per display segment
(seven segments per digit)

Decimal Points ...•...•. Selectable using decimal
pOint select signal lines.
Display Type .•.....•••. DM-31 OOB, red LED
DM-31 04, High brightness red
LED
Display Height ........• DM-31 OOB, 0.56" (14,2 mm)
DM-31 04, 0.6" (15,2)
Overscale •..••......... The inputs exceeding the fullscale range display a "1"
MSD and sign with other
digits blanked.
Autopolarity •.......... A "+" sign is automatically
displayed for positive inputs
and a "-" sign for negative
inputs. The user may blank
the polarity using the
POLARITY ENABLE line.

10-52

POWER REQUIREMENTS
AC Power
115 or 230 VAC, ±10%, 47 to 440 Hz, 4 watts typical
de Power
+5V ±0.25Vdc @ 250 mA typical, 400 mA maximum and -5V
dc @ 5 mA typical, 25 mA maximum. Logic spikes must be less
than 50 mY. Bypass supplies externally if necessary.
(Users will normally power from AC-only; dc-only power is
optionaL)
CALIBRATION
A multiturn screwdriver pot adjusts the full scale reading (gain).
Zero is automatic (autozeroing). Suggested recalibration in
stable conditions is 90 days.
PHYSICAL
External Dimensions
Short-Depth Case 3.0"W x 2.15"0 x 1.76"H (76,2 x 54,6 x 44,7
mm)
Panel Cutout Dimensions
1.812"H x 3.062"W (46,0 x 77,7 mm)
Weight
5 ounces (142g) approximately
ENVIRONMENTAL
Altitude
o to 15,000 feet (4900m)
Operating Temperature Range
32°F to 122°F (0° to 50°C)
Storage Temperature Range
-13°F to +185°F (-25°C to 85°C)
Relative Humidity
20% to 80% non-condensing

m

INPUT/OUTPUT CONNECTIONS OM-3104
BOTTOM It,
TOP 8
ANALOG RETURN
DEC I'T 1.1198

ANALOG LO IN
ANALOG HI IN
ATTENUATOR IN

2

DEC 1'1 111.'"

3
4

DEC PT 10g.9
DEC I'T 1099.

KEYWA' _ _ _ KEYWAY

DISPLA Y TEST; DEC PT COM
REFERENCE OUT
EXT. REF. LOI-BV

•
1

POURITY ENABLf:

B SPARE

+5V PWR COMMON •

REFERENCE IN
OHMS LO
+5VOC PWR

:~T~O. .NVN~O"::":::~~~~~
NO CONNECTION
AC LINE LO 8
NO CONNECTION
NO CONNECTION
NO CONNECTION
AC LINE LO A
NO CONNECTION
NO CONNECTION

11
12
13
14
15

NO
NO
NO
AC
NO
NO
t7 NO
18 AC

1.

CONNECTION
CONNECTION
CONNECTION
LINE HI 8
CONNECTION
CONNECTION
CONNECTION
LINE HI A

INPUT/OUTPUT CONNECTIONS OM-3100B
BOTTOM A
TOP B

'::fg~~;:g; mii jg:

KEVWAV-_ _ _ KEVWAY

E::.~:S::.:~£~~~ w: ~~~E:~~COEMIN
POLARITV ENABLE 8 SPARE
t5V PWR COMMON 9 t5VIJC PWR

:~V~OANV~O"::":::~~~~:
NO CONNECTION
AC LINE LO 1:1
NO CONNECTION
NO CONNECTION
NO CONNECTION
AC UNE LO A
NO CONNECTION
NO CONNECTION

11
12
13
14
15
16
17
18

NO
NO
NO
AC
NO
NO
NO
AC

CONNECTION
CONNECTION
CONNECTION
LINE Iii 8
CONNECTION
CONNECTION
CONNECTION
LINE HI A

DATEL, Inc. 11 Cabot Boulevard. Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

DM-31 00L/DM-31 03
Low-Cost, 3~ Digit
LED Panel Meters
FEATURES
• Balanced differential Inputs
• 1000 MO CMOS high-Impedance Inputs
• 3'1, Digit 0.56" red LED (DM-3100L) and 0.6" high
brightness red LED Models (DM-3103).
• Logic Power (+ 5V dc)
• Compact Short-Depth cases
• 80 dB CMRR
• Autozerolng Capability
Standard ± 1.999V dc input range; user-installed
options set other voltage or current ranges.
1. Accepts shunts for ± 20 fLA to ± 2A FS ranges
2. Accepts attenuators for ± 2V to ± 200V FS ranges
3. Digital ohmmeter, 2KO to 10MO FSR
GENERAL DESCRIPTION
The DM-31 DOL and DM-31 03 are 3'h digit Short-Depth versions of the DM-3100N and DM-3101 respectively.
The DPM's have bright red LED displays making them easily
readable from many feet away. The short-depth cases used are
ideally suited for shallow panels. The DPM's are easily fieldmodifiable for different input voltage and current ranges.
The DPM's accept a DC or slowly-varying input voltage and
display that input on front panel numerical indicators. They
employ conventional dual-slope A/ D converters plus 7
segment display decoder-drivers all in one LSI microcircuit.
Since the microcircuits require approximately 1OV to power the
AID section, the internal DC/DC converters generate -5Vfrom
+5V power input to form bipolar supplies.

internal circuits automatically compensate for reference drifts
in the supplies of balanced bridge or transducer sensors.
The DPM's find use in analytical instruments, industrial process
controllers, portable diagnostic instruments, automatic test
equipment, medical instruments, airborne, marine and ground
vehicles and data acquisition/data logging systems.

ORDERING INFORMATION
DM-3100L -1/DM-3103-1

The DM-31 DOL and DM-3103 employ balanced differential
inputs. When used with a bridge or transducer input, the DPM's
offer high noise immunity. In such configurations the DPM's
can accurately measure very small signals in the presence of
much larger common mode signals.
The high impedance (1 000 megohms) inputs will not load down
sensitive input circuits.
The meters can be operated ratio metrically. That is, the DPM's

Model
DM-3100L-1

Description
3 1/2-digit LED DPM in short
depth case (includes
one connector)

DM-31 03-1

High-brightness version of
DM-31 OOL (includes
one connector)

ACCESSORIES
Part Number Description
58-2075010
Connector, dual 18-pin,
0.1" centers
UPA-5/500
115V AC to ± 5V dc (@500mA)
power adaptor

r-____~___----~------~~----~~P~0~S~IT~IV~E~R~A=IL~--~----~------A18 ;~:~R
,-----------f---t---B14
ANA. RTN

A1

IN
DISPLAY TEST

------f-+.C
.....--+-7""--A10·A13

ANA. HIIN

A4

ANA. LO IN

A2

H-----B16

DEC. PT SELECT

PciLARii'Y ENABi:E

-~.....,

:.--~ REF IN

86 ------+-------t-~...J

:. _. REF. OUT

A6

------+-------t-r-----t-~.<

L.f----+-----+>"'~--! B15 DEC. PT COMMON
VOLT AGE

B18

DISPLAY ENABLE

REFERENCE
LM 329

(6.9V)
EXT REF. LO A17------......------~L-----6------+---~-+--------------~
-5Vdc

5V
POWER

OHMSLO B2--------------------------------~

Simplified Block Diagram of DM-3100L and DM-3103
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-53

DM-3100L and DM-31_03
FUNCTIONAL SPECIFICATIONS
(Typical at 25°C, 2V range unlell noted)
ANALOG INPUT
Full-Scale Input ..•.••.. Refer to "FEATURES"
Range
Ranges field-modifiable.
Input Impedance •••.•.• 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current. ..... 5 pA (typical) 50 pA
(maximum)
Input Overvoltage .. , ••• ±250V dc, 175V RMS
continuous (maximum)
±300V intermittent
(maximum)
External Reference •.... ±1 00 mV to ±2V referred to
Range
-Vs (EXT. REF LO)
Common-Mode ......•. 80 dB (typical, from dc to 60
Rejection
Hz, with a 1 Kilohm
unbalanced input
Common-Mode ..•.•... Both the inputs must
Voltage Range
remain within 0.5V dc below
+5V dc supply and 1.0V dc
above -5V dc supply.
Resolution .•.......•..• 1 mV
Display Accuracy ....••. @Adjustable to ±0.1% of
reading, ±1 count
Temperature Drift .•.... Autozeroed ±1 count over 0
of Zero
to +50°C temperature range
Temperature Drift ... , .• ± 50 ppm of
of Gain
reading / ° C (typical)
±100 ppm of reading/DC
(maximum)
Warm-Up Time .•...•••. 10 minutes (typical)
Sampling Time ••....... 83.3 mS (nominal)
Sampling Rate .••.••..• 3 conversions per second.
May be rewired for up to 20
conversions per second
DISPLAY
Number of Dlgits •.•.... 3 decimal digits and most
significant "1" digit (3Y2 digits)
Decimal Points ••..•.... Selectable using decimal
point select signal lines.
Display Type ..•.•..•• , ,DM-31 OOL, red LED
DM-31 03, High brightness red
LED
Display Height •..••.... DM-31 OOL 0.56" (14,2 mm)
DM-3103 0.6" (15,2 mm)
Brightnell .....•...•.•. 2400 minimum, 4800 typical
(DM-3103)
microcandelas per display
segment (7 segments per
digit)
Overseale ..••.•.....••• The inputs exceeding the fullscale range blank the display
leaving a "1" MSD and sign.
Autopolarity ..••.....•. A "+" sign is automatically
displayed for positive inputs
and a "-" sign for negative
inputs. The user may blank
the polarity using the
POLARITY ENABLE line.
POWER REQUIREMENTS
External +5, ±0.25V dc regulated required at 280 mA typical,
450 mA maximum. Logic spikes must not exceed 50 mV. Power
current varies rapidly so that unregulated supplies cannot be
used.

PHYSICAL
External Dimensions Short-Depth Case
3.0"W x 2.15"D x 1.76"H (76,2 x 54,6 x 44,7 mm)
Panel Cutout
1.812"H x 3.062"W (46,0 x 77,7 mm)
Weight
5 ounce (142g) approximately
ENVIRONMENTAL
Altitude
o to 15,000 feet (4900m)
Operating Temperature Range
32°F to 122°F (0° to 50°C)
Storage Temperature Range
-13°F to +185°F (-25°C to 85°C)
Relative Humidity
20% to 80% non-condensing

INPUT IQUTPUT CONNECTION OM- 3100L

BOTTOM A
ANALOG RETURN

r~
~

TOP B
NO CONNECTION

A:~l~~N~~~~~~~ ~. ~~MCSO~~ECTION
ANALOG HI INPUT

~

NO CONNECTION

NO CONNECTION ~ NO CONNECTION
REFERENCE OUT
6 REFERENCE IN
NO CONNECTION

tt

NO CONNECTION

NO CONNECTION ~ NO CONNECTION

NO CONNECTION ~ NO CONNECTION
DEC PT 1.999 ~ NO CONNECTION
DEC PT 19.99 ~ NO CONNECTION
DEC PT 199.9 ~ NO CONNECTION
DEC PT 1999. ~ NO CONNECTION

NO CONNECTION
NO CONNECTION

~

DISPLAY TEST

~

DEC PT COM

PWR COMMON

r!!

EXT. REF. LO

~

NO CONNECTION

+5VDC PWR IN

L.!.!

DISPLAY ENABLE

POLARITY ENABLE

NOTE: REFERENCE IS BIASED AGAINST
NEGATIVE RAIL (EXT. REF·. La).

INPUT/OUTPUT CONNECTION DM- 3103
BOTTOM A
TOP B
ANALOG RETURN
ANALOG LO INPUT
NO CONNECTION
ANALOG HI INPUT

:I:
~
~
~

NO CONNECTION
OHMS LO
NO CONNECTION
NO CONNECTION

NO CONNECTION ~ ""0 CONNECTION
REFERENCE OUT ~ REFERENCE IN
NO CONNECTION 2- NO CONNECTION
NO CONNECTION ~ NO CONNECTION
NO CONNECTION ~ NO CONNECTION
DEC PT 1.999 ~ NO CONNECTION
DEC PT 19.99 .!..!. NO CONNECTION
DEC PT 199.9
NO CONNECTION
DEC PT 1999. ~ NO CONNECTION
NO CONNECTION ~ DISPLA Y TEST
NO CONNECTION ~ DEC PT COM
PWR COMMON ~ POLARITY ENABLE
EXT. REF. LO ~ NO CONNECTION

..g.

N~~~~~:F~:~:C~ISD~~:~:~ :::~~:T
NEGATIVE RAIL (EXT. REF. LO).

CALIBRATION
A multiturn screwdriver pot adjusts the full scale reading (gain).
Zero is automatic (autozeroing). Suggested recalibration in
stable conditions is 90 days.
10-54
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DM-3100MIL
Ruggedized, 31/2 Digit
LED Panel Meter
FEATURES

• 3% Digits LED display, + 5V dc-powered
• Extended Operating Temperature Range ( - 46"C to
+ 49°C)
• Designed to meet Military Standards:
• Vibration Testing per MIL-STD-202
• Humidity Testing per MIL-STD-202
• Inspected per MIL-STD-105
• Balanced Different Inputs
• Withstands 3 shocks @ 25 g's for 11ms Vertical Axis
• Standard ±1.999 Vdc input range;

GENERAL DESCRIPTION
The DM-31 OOMIL is a 3V, Digit, LED Display, +5V dc-powered
digital panel meter. The DPM is designed to operate over an
extended temperature range of -46°C to +49°C and conform
to military standards. The DM-3100MIL meets and exceeds
vibration and humidity testing per MIL-STd-202. It will also
withstand shock testing (3 shocks @ 25 g's for 11 ms vertical
axis). The DPM successfully meets and exceeds the military
specifications by using all hermetically sealed components
and conformally coating the circuit boards. Its compact design
lets this DPM fit into a short-depth case. The design and
rigorous testing permits using the DM-31 OOMIL in portable test
equipment for field use, ground vehicles, submerged vessels
and aircraft. The DM-3100MIL offers a standard +/-1.999 Vdc
input range; a +/-199.9 mV range is available to OEM quantity customers.
Overall, the DM-3100MIL is a highly reliable DPM designed
for the rugged military environment.

ORDERING INFORMATION
DM-3100MIL-1
Description

Model

DM-3100MIL-1 Ruggedized, 3% digit meter

ACCESSORIES
Pan Number Description
58-2075010

Connector, dual 18-pin. 0.1" centers
(one included with each meter)

UPA-5/500

11511. AC to +5V de (@ 500 mAl adaptor

818 +SVde
POWER IN

POSITVE RAIL

A14 DISPLAY TEST

~

3

---

ANA. HI IN B1

DISPLAY

r---.
INTEGRATOR
& A/D CONV

ANA. LO ~

V

I
V" +1.'-1!i!l

AS,A5,A7

'DEC PI SELECT

.....

---v

...

DECODER
DRIVERS

.r-:
-C ~
-SVde

DC/DC
CONY

I

B4/A18
+5~de
LOGIC (fROUND

ANALOG
RETURN
A2/B2

Simplified Block Diagram of DM-3100MIL

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

10-55

DM-3100MIL
FUNCTIONAL SPECIFICATIONS
(Typical at 25°C, 2V range unle.. noted)
ANALOG INPUT
Full-Scale Input. " ..... Refer to "FEATURES"
Range
Input Impedanca ....... 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current ...... 5 pA (typical)
50 pA (maximum)
Input Overvoltage ...... ±250V dc, 175V RMS
continuous (maximum).
±300V intermittent
(maximum).
Common-Mode ........ 80 dB (typical), from dc
Rejection
to 60 Hz, with a 1
Kilohm unbalanced input.
Common-Mode ........ Both the inputs must
Voltage Range
remain within 0.5V dc
below the +5V dc supply
and 1 .OV dc above the
-5V dc supply.
Resolution . ............ 1 mV
Display Accuracy . ...... Adjustable to ±0.1 % of
reading, ±1 count.
Temperature Drift ...... Autozeroed ±1 count over
of Zero
-46° to +49°C
temperature range.
Temperature Drift ..... . ±50 ppm of reading/DC
of Gain
(typical).
±100 ppm of reading/DC
(maximum).
Warm-Up Time . ........ 10 minutes (typical)
Sampling Time ........ . 83.3 mS (nominal)
Sampling Rate ......... 3 conversions per second.
May be rewired up to 20
conversions per second.
DISPLAY
Number of Digits . ...... 3 decimal digits and
most significant "1" digit
(3Y2 digits).
Decimal Points . ........ Selectable using decimal
point select signal lines.
Display Type . .......... Red LED
Display Height .......... 3"
Overscale . ............. Inputs exceeding the fullscale range blank the display
leaving a "1" MSD and sign.
Autopolarlty ........... A "+" sign is automatically
displayed for positive inputs
and a "-" sign for negative
inputs. The user may blank
the polarity using the
POLARITY ENABLE line.

POWER REQUIREMENTS
External +5 dc, ±0.25V dc regulated required at 280 mA typical,
450 mA maximum. Logic spikes must not exceed 50 mV. Power
current varies rapidly so that unregulated supplies cannot be
used.
CALIBRATION
A multiturn screwdriver pot adjusts the full scale reading (gain).
Zero is automatic (autozeroing). Suggested recalibration in
stable conditions is 90 days.
PHYSICAL
External Dimensions
Short-Depth Case
3.0"W x 2.15"0 x 1.76"H (76,2 x 54,6 x 44,7 mm)
Panel Cutout Dimensions
1.812"H x 3.062"W (46,0 x 77,7 mm)
Weight
5 ounces (142g) approximately
ENVIRONMENTAL
Altitude
o to 50,000 feet
Operating Temperature Range
-51°F to 88°F (-46°C to 49°C)
Storage Temperature Range
-124°F to +185°F (-69°C to +85°C)
Relative Humidity
MIL-STd-202, Method 1060 (98% relative humidity)
Vibration
MIL-STd-202, Method 204C
Section 2.2, (Condition A) (10G at 10 to 500Hz)
Shock
3 shocks @ 25 g's for 11 ms Vertical Axis
Marking
MIL-STd-130
Marking Permanency
MIL-STd-202, Method 215
Inspection
MIL-STd-105

INPUT/OUTPUT CONNECTIONS DM-3100MIL
TOPB
BOTTOM A
INPUT SIGNAL LO
INPUT SIGNAL HI
ANALOG RETURN
ANALOG RETURN
NC
NC
NC
PWRCOMMON
DEC PT 100
~ NC
rDEC PTl0
NC
~ NC
DEC PT 1
~ NC
NC
~
NC
NC
9
NC
NC
NC
NC
NC
NC
NC
NC
DISPLAY TEST
~ NC
NC
NC
NC
NC
~ NC
NC
""'"'
PWR COMMON
J.!!. +5V DC INPUT

"1
~

""i"
r:t

Toit
12
"fa'
Ts"
16

10-56

DATEl, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEl (508) 339-30001TlX 174388/FAX (508) 339-6356

DM-31 00N/DM-31 01
Low-Cost, 3~ Digit
LED Panel Meters

FEATURES
•
•
•
•
•

Balanced differential Inputs
1000 Mel CMOS high-Impedance inputs
Compact low-profile case
Logic powered (+5V de)
Internal provision for an offset pot for various
applications

• 80 dB CMRR
• Standard ± 1.999V de input range; user-installed
options set other voltage or current'ranges.
• Autozeroing capability
GENERAL DESCRIPTION
The DM-3100N and its high-brightness equivalent, the
DM3101 are 3% digit Solid State devices using red LED
displays, The bright red LED displays make them easily
readable from many feet away, Packaged in compact low
profile cases, these DPM's have provisions for userinstalled resitors and offset potentiometers.
The autozeroing capability further enhances the versatility of
the meter. A pot can be internally installed so that an offset can
be obtained with a zero input to the meter, or a zero reading with
an offset input
The DPM's accept a DC or slowly-varying input voltage and
display that input on front panel numerical indicators, They
employ conventional dual-slope A/ D converters plus 7
segment display deCOder-drivers all in one LSI microcircuit
Since the microcircuits require approximately 1OV to power the
AID section, the internal DC/ DC converters generate -5V from
+5V power input to form bipolar supplies,
Another feature of these DPM's is that a balanced differential
input is used, When used with bridge or transducer inputs, it
offers high noise immunity and can accurately measure very
small signals in the presence of much larger common mode
signals,
A very noteworthy feature of the meters is that they can be
operated ratiometrically, This means that internal circuits in
the DPM's automatically compensate for reference drifts in
the supplies of balanced bridge or transducer sensors,

These DPM's find use In analytical instruments, industrial
process controllers, portable diagnostic instruments,
automatic test eqUipment, medical and patient monitoring
instruments, airborne, marine and ground vehicles and data
acquisition/ data logging systems,

ORDERING INFORMATION
DM-3100N -1/DM-3101 -1
Description
31/2 Digit LED DPM in low-profile
case (includes one connector)
DM-3101-1
High-brightness version of DM-31 OON
(includes one connector)
ACCESSORIES
Part Number Description
58-2073082
Dual 1O-pin, 0.156" centers
connector
TP-50K
Offset pot
115VACto ±5Vdc(@500mA)
UPA-5/500
power adaptor
Model
DM-3100N-1

POSITIVE RAIL

ANA. RTN

J

ATTEN.IN

5

ANA HIIN

6

ANA LOIN

H

:------ REFIN

A

'-~~~~~~-r-~~~~~~~~~~~~~~~~~-r-~-

9

+5VdcPOWERIN

r-~~~~~~+-+--

3

DISPLAYTEST
DECIMAL POINT
SELECT

L ___

10

POLARITY ENABLE

K

DISPLAY ENABLE

L

SVPOWRCOM

REF OUT 1
lV

EXT. REF LO

8

OHMSLO

4

OFFSET OLiT

2

NEGATIVE RAIL

~

OPTIONAL OFFSET
POT

Simplified Block Diagram of DM-3l00N and DM-3l0l
DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-57

•

DM3100N & DM-3101
FUNCTIONAL SPECIFICATIONS
(Typical at 25°C, 2V range unless noted)

ANALOG INPUT
Full-Scale Input ........ Refer to "FEATURES"
Range
Ranges field-modifiable.
Input Impedance ...... . 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current ..... 5 pA (typical) 50 pA (maxi
mum)
Input Overvoltage ...... ±250V dc, 175V RMS
continuous (maximum)
±300V intermittent
(maximum)
External Reference . .... ±1 00 mV to ±2V
Range
referred to -Vs (EXT. REF
LO)
Common-Mode ........ 80 dB (typical),
Rejection
from dc to 60 Hz, with 1
Kilohm unbalance
Common-Mode " ...... Both the inputs must
Voltage Range
remain within O.5V dc below
+5V dc supply and 1.0V dc
above -5V de supply
Resolution . ............ 1 mV
Display Accuracy ...... Adjustable to ±0.1 % of
reading, ±1 count
Temperature Drift . ..... Autozeroed ±1 count over 0
to +50°C temperature range
Temperature Drift . ..... ±50 ppm of
of Gain
reading/oC (typical) ±100
ppm of reading/ °C (maximum)
Warm-Up Time ......... 10 minute (typical)
Sampling Time ........ . 83.3 mS (nominal)
Sampling Rate . ........ 3 conversions per second.
May be required up to 20
conversions per second.
DISPLAY
Number of Digits . ...... 3 decimal digits and most
significant "1" digit (3Y, digits)
Decimal Points . ........ Selectable using decimal
pOint select signal lines.
Display Type . .......... OM-31 OON. Red LED
OM-31 01, High brightness
Red LED
Display Height . ........ OM-31 OON, 0.56" (14,2 mm)
OM-31 01, 0.6" (15,2 mm)
Overscale .............. The inputs exceeding the fullscale range blank the display
leaving a "1" MSO and sign.
Autopolarlty ........... A "+" sign is automatically
displayed for positive inputs
and a "-" sign for negative
inputs. The user may blank
the polarity using the
POLARITY ENABLE line.

CALIBRATION
A multiturn screwdriver pot adjusts the full scale reading (gain).
Zero is automatic (autozeroing). Suggested recalibration in
stable conditions is 90 days.
PHYSICAL
External Dimensions
Low-Profile Case 2.53"W x 3.34"0 x 0.94"H (64,3 x 84,8 x 23,8
mm)
Panel Cutout Dlmenslcns
2.56"W x 0.97"H (minimum) (65,1 x 24,6 mm)
Mounting Method
Refer to end of this section.
Weight
5 ounces (142g) approximately
ENVIRONMENTAL
Altitude
o to 15,000 feet (4900m)
'Operatlng Temperature Range
32°F to 122°F (0° to 50°C)
Storage Temperature Range
-13°F to +185°F (~25°C to 85°C)
Relative Humidity
20% to 80% non-condensing

INPUT IOUTPUT CONNEC TiONS

REFERENCE IN ~~
DEC PT 1999. ~ 2
DEC PT 199.9 ~ 3
DEC PT 19.99 ~ 4

D:~:!/ ~9:: ~
ANALOG LO IN
ANALOG RETURN
DISPLAY ENABLE
PWR COM

NOTE

DM~3

1 DON

TOP

BOTTOM

r-;

rj~

:
7
8

9

L.!:....!..Q.

REFERENCE

our

OFFSET OUT (OPT)
DISPLAY TEST
OHMS LO (OPT)
ATTENUATOR IN (OPT)
"N:ALOG HI IN
NO CONNECTION
EXT REF LO
+5VOC PWR IN

P'OL.AiiiTY EN'AiiLi

REFERENCE IS BIASED AGAINST

NEGATIVE RAIL (EXT" REF. LO)

INPUT/OUTPUT CONNECTIONS OM- 3101

NOTE: REFERENCE IS BIASED AGAINST

POWER REQUIREMENTS

NEGATIVE RAIl.. {EXT. REF. I..O}

External +5, ±0.25V dc regulated required at 280 mA typical,
450 mA max. Logic spikes must not exceed 50 mV. Power
current varies rapidly so that unregulated supplies cannot be
used.

10-58

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DM-3100U1
FEATURES
• Ultra-low power consumption
• .5" high 3'12 digits LCD readout
• SV or 9 to 1SV dc-powered
• Internal ratlometrlc reference for drift correction
• Selectable unit descriptors: A, mA, V, mV, n, Kn, AC,
or DC
• Balanced differential Inputs with 5 pA bias currents
• Autozerolng with 80 db CMR noise rejection
• User-conflgurable to accept 4 to 20 mA Inputs
Standard ± 1.999V dc input range; user-installed
options set other voltage or current ranges.
1. Offset pot for 4-20 mA and other applications
2. Accepts shunts for ± 20 fLA to ± 2A FS ranges
3. Accepts attenuators for ± 2V to ± 200V FS ranges
4. Digital ohmmeter, 2K!} to 10M!} FSR
GENERAL DESCRIPTION
The DM-3100U1 is a 3)12 digit, LCD-type DPM that uses very
little power and can be powered by +4V to +15V dc sources.
The 0.5" high numeric display is visible under ambient room
light from many feet away. This device is packaged in a lowprofile case, allowing a higher packing density on the final
product's panel. Besides measuring dc voltages and current,
unit descriptors (A, mA, V, mV, n, Kn, AC, and DC) indicate
what is being measured.
The versatility of this meter is further enhanced by its
autozeroing capabilities. If the customer desires, an offset pot
can be internally installed so that a desired reading can be
obtained with a zero output to the meter.
This DPM accepts a dc or slowly varying input voltage and
displays that input on front panel numerical indicators. It
employs a conventional dual-slope AID converter plus 7
segment display decoders I drivers all in one LSI microcircuit.
Since this microcircuit requires approximately 9V to power the
AID section, an internal dc/dc converter generates -5V from
+5V power input. Together these two voltage sources form a
bipolar power supply to power the AID converter. The DM3100U1 may also be powered directly from a single 9V battery
@ 3 mA without using the dc/dc converter.
Another feature of the DM-3100U1 is that it employs a
balanced differential input. When used with a bridge or

Micropowered 3~ Digit
LCD Panel Meters

transducer input, it offers high noise immunity and can
accurately measure very small signals in the presence of
much larger common mode noise. Another characteristic of
this balanced differential input is that it will not load down
sensitive input circuits due to its high input impedance of 1000
megohms, and low 5 pA bias current.
A very noteworthy feature of this meter is that it can be operated
ratiometrically. This means that it has internal circuits that c~n
automatically compensate for reference drifts in the supplies of
balanced bridge or transducer sensors and still give accurate
readings.

ORDERING INFORMATION
DM-3100U1 -1
Model
Description
DM-3100U1-1 31/2-digit micropowered LCD
DPM with descriptors
(Includes one connector)
ACCESSORIES
Part Number Description
58-2073083
Connector, dual 15-pin,
0.1" centers
TP-50K
Offset pot
Power Supply
UPA-5/500

POSITIVE RAIL

r---~----.-----t---~----------r-"'-- 915

r---------1r--+-ANA. RTN B2

-------+_+<

.--1->"--- 98- 910

SOLDER GAP
1

r-r-r-ATTEN. IN

B4

'"-"v~---,

:-----REF,IN 81

----"''+-i-1

-------+---+----'

A14

914
-------+-~-+----t-t_~
lV.
. " -------"-..i...-____---~+__------I~+-4~------+-----"-- A15

L_--REF. OUT A1
EXT REF LO

NEGATIVE RAIL
OHMS LO

A3-A1Q

OEC. PT. SELECT

DESCRIPTOR SELECT

DP/DESCRIPTOR COMMON
A12 HORIZPOLIN
912 HORIZ POL OUT
A13 VERT POL IN
L - , -_ _""-'''''---'''' 913 VERT POL OUT

ANA. HI IN B5 _ _ _- - J
ANA. LO IN A2

AD/PWR IN

96 DISPLAYTEST

81 - - - - - - - - - - . - - - - - '

5V DC/DC GND
+5VDC/DCPOWERIN
9VPOWR COM

"" " OPTIONAL OFFSET

POT
OFFSET OUT

B2 - - - - - - - - - - - - - - - - - - - - '

Simplified Block Diagram of DM-3100U1

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

10-59

II

DM-3100U1
FUNCTIONAL SPECIFICATIONS
(Typical at 25°C, 2V range unless noted)

POWER REQUIREMENTS
5V between B14/B15 and A14; 12mA typ., 15mA max. OR 9 to
15 V dc between B15 and A15; 9V, 9 mA; 15V, 20 mA. max

ANALOG INPUT
Full Scale Input .......• -1 .999V dc to +1.999V dc
Range
Input pad area will accept
user-installed range change
Input Impedance ..•.... 100 Megohms, minimum
Input Bias Current ...•.. 5 pA typical, 50 pA maximum
Input Overvoltage .••.•• ±250 volts dc 175 VRMS
continuous max.
±300 Volts intermittent max.
External Ref. Range •••• +1 00 mV to +2V, referred to
-Vs
Common Mode ........ 80 dB, dc to
Rejection
60 Hz, 1 Kilohm unbalance
Common Mode •....•.. Within +Vs-0.5V to -Vs+1.0V,
Voltage Range
where +Vs is the positive rail
(Pin B15) and -Vs is the
negative rail (Pin A15) -Vs is
approximately equal to -5V
below PWR. COM.
Resolution .••.•..•....• 1 mV
Displayed
Accuracy ..•••.•....•.. Adjustable to ± of reading, ±
count
Temperature Drift .••... Autozeroed ±1 count over
of Zero
0 to +50°C
Temperature Drift ..•... ±50 ppm of Reading/oC typo
of Gain
±100 ppm of Reading/ °C
max
Ramp-up Time •..•..••. (integration Period)
83.3 mS
Sampling Rate ••.•.•••. Factory set at 3 conversions
per second. May be rewired
up to 20 conversions/ second
DISPLAY
Number of Digits ....••. 3 decimal digits and most
significant "1" digit (3Y, digits)
Decimal Points ......... Selectable decimal points are
included for scale multipliers
Display Type ........••. Field effect liquid crystal
displays (LCD) requiring room
light for viewing. Black digits
against a light background
Display Height .•••...•. 0.5 inches (12.7 mm)
Overseale ...••.••.••... Inputs exceeding the full
scale range blank the display,
leaving a "1 " MSO and sign
Autopolarity .•.•••.••.• A minus sign is automatically
displayed for negative inputs,
and may also be blanked
Descriptors ..••••.•.... K, n, mA, mV, AC, and DC
This field of function labels is
positioned to the right of the
decimal digits, Individual unit
descriptors may be selected
for display.

CALIBRATION
A multiturn screwdriver pot adjusts the full scale reading (gain).
Zero is automatic (autozeroing). Suggested recalibration is 90
days.
PHYSICAL-ENVIRONMENTAL
Outline Dimensions
2.53"W x 3.25"0 x 0.94"H (64.3 x 82.5 x 23.8 mm)
Cutout Dimensions
2.56W x 0.97"H min. (65.1 x 24.6 mm)
Mounting Method
See Mounting Section
Weight
Approximately 5 ounces (142g)
TEMPERATURE RANGE
Operating
o to +50°C
Storage
O°C to +55°C
Altitude
o to 15,000 feet (4900m)
Relative Humidity
20% to 80% non-condensing
I/O SIGNAL FEATURES
Besides the common 1/0 Signals defined elsewhere, this
device also has some important 1/0 features:
Reference In/Out (Pins B1/A1)
Normally, REF. IN and REF. OUT should be jumpered together.
An external floating source referred to EXT.REF. La (Pin A15)
may be substituted for ratiometric operations.
Vertical Polarity In (Pin A13)
Vertical Polarity Out (Pin B13)
For reverse sensing applications, VERT. POL. OUT may be
jumpered to HORIZ. POL. IN (no other connections). This will
display a minus sign with positive inputs and no sign (implied
positive) with negative inputs.
See Backplane Out
Backplane Out (Pin A11)
Connect all unused Polarity, Decimal Points and Descriptors to
Backplane Out.

INPUT IOUTPUT CONNECTIONS OM-3100U 1
BOTTOM A
REFERENCE OUT
ANALOG LO IN
rnA DSCRPTA IN

10-60

2

REFERENCE IN
ANALOG RETURN

3

OFFSET OUT (OPT)

:: _: :~:~~~A~~~
:~ ~:~::~: :: +~I::~~YO
DC
~~ ~:~::~: :: ~ ~:~ :~ ~ ~~::
~~ ~!~:~~:

HI IN (OPT)

TEST

DSCRPTR IN

POWER CONNECTIONS
AID Power In (Pin B15)
Connect +9 to +15V dc source to this pin, referred to 9V dc
Power Common )PIN A15). When using a +5V dc power source,
connect this pin to pin B14.
+5V dc Power In (PIN B14)
Connect this pin to the +5V dc power source, referred to +5V dc
Power Ground (PIN A14)

TOP 8

~

BACKPLANE DUT

H:E~~ :~~ ::
+SV DC DC GND.
+9V PWR COM/EXT.REF.LD

~

DEC PT 199.9

*
~
~
~

OP/DSCRPTR COM

~~:~z p~~L O~~T

-tSY DCIDC PWR IN
AID PWR IN
•

NOTE REFERENCE IS BIASeD AGAINST
NEGATIVE RAIL(EXT. REF. LO).

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DM-3100U2,-U3
AC/dc-powered 3~ Digit
LCD Panel Meters
FEATURES
• Dual powered: +9 to +15V dc/115VAC (DM-3100U2),
+9 to 15V dc/230VAC (DM-3100U3)
• Selectable unit descriptors: A, mA, V, mA, 0, kO AC
or dc
• Balanced high-impedance differential inputs
• aOdB CMRR
• Autozerolng capability
• Internal provision for an offset potentiometer for
various applications
• Standard ± 1.9999V dc input range; user-installed
options set other voltage or current ranges.
1. Offset pot for 4-20 mA and other applications
2. Accepts shunts for ± 20 fLA to ± 2A FS ranges
3. Accepts attenuators for ± 2V to ± 200V FS ranges
4. Digital ohmmeter, 2KO to 10MO FSR
GENERAL DESCRIPTION
The OM-3100U2 and OM-3100U3 are 3Y, digit LCD display
devices. The OPM's operate with either AC or +9 to +15V dc
voltages. The OM-31 00U2 uses 115V AC at 47 to 440Hz. The
OM-3100U3 uses 230V AC at 47 to 440Hz. The input voltage
and current ranges are easily field-modifiable.
Both models use OATEL's low profile DPM case. The input
section is balanced differential for excellent noise rejection
and uses a high-impedance (1000 MO) CMOS front end with
low 5 pA bias currents.
Both meters are autozeroed and accept external ratio metric
reference inputs to reduce drift errors in instrumentation
systems.
The LCD display on both meters contains unit descriptors (A,
mA, V, mY, 0, KO, AC, dc) which are pin-programmable for
dedicated YOM and DVM applications.
The AC supply in both meters produces an additional filtered
dc output of approximately +12V dc @ 5 mA for customer use.
A suggested application is to charge standby NiCad batteries.
Since this power output pin is also used for power input when

dc-powered, the NiCads may be left continuously connected
so the meter will continue operating if there is an AC power
failure.

ORDERING INFORMATION
DM-3100U2 -1/DM-3100U3-1
Model
Description
OM-3100U2-1 31/2-Digit, LCD Digital panel meter,
115V AC or +9 to + 15V dc powered
(one connector included)
DM-3100U3-1 31/2-Digit, LCD Digital panel meter,
230V AC or + 9 to + 15V dc powered
(one connector included)
ACCESSORIES
Part Number Description
58-2073083
Connector dual 15-pin, 0.1" centers
TP-SOK

Offset pot

POSITIVE RAIL
,.----~----r__--__,..._~:.:::..::.:.;_~~------~-._- 85

.----f",'--- 87·89 DEC PI SELECT

ANA RTN/ 82 - - - - -... --+~
OHMS La

ANA. HIIN

84 -4-~~-..---+r'"

ANA La IN

A2

+9VdcPWR.IN

A3A1O

DESCRIPTOR SELECT

II

A11 HORIZ POL IN
811 HORIZ POL I OUTIDP
DESCRI PTOR COM MaN

---------+t~=__

A12 VERT POL IN
812 VERT POL OUT

__---+_~=+==-~
-+-_...J

;--~--REF.IN

81 _ _ _ _ _ _ _ _ _

L - - - REF. OUT

A1

-------...--_-+-___+-----.~

815

1151230VAC HI

A14

1151230VAC La

---------,-~c=-~___,_-------~---J-~4~------"---------l--- 813 9VPWR. COMI
~
EXT REF LOW
NEGATIVE RAIL
OFFSET OUT

83 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-.-l

OPT1~;tL OFFSET

Simplified Block Diagram of DM-3100U2 and DM-3100U3

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-61

DM-3100U2,-U3
FUNCTIONAL SPECIFICATIONS both models
(Typical at +25°C, unless noted)
ANALOG INPUT
Full-Scale Input .••....• Refer to "FEATURES"
Range
Ranges field-modifiable.
Input Impedance ••..••• 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current .•.•.. S pA (typical) SO pA (maximum)
Input Overvoltage •..•.• ±2S0V dc, 17SV RMS
continuous (maximum)
±300V dc intermittent (maximum)
External Reference ••.•• ±1 00 mV to ±2V referred
Range
to oVs
Common-Mode ..•..•.. 80 dB (typical),
Rejection
from dc to 60 Hz, with a 1
Kilohm unbalanced input
Common-Mode ...••.•. Both the inputs must
Voltage Range
remain within O.SV dc below
the +SV dc supply and 1.0V dc
above the oSV dc supply.
Resolution ....•.•...... 1 mV
Display Accuracy ....... Adjustable to ±0.1 % of
reading, + / -1 count
Temperature Drift .•..•. Autozeroed ±1 count
of Zero
over a O°C to +SO°C
temperature range
Temperature Drift ..•... ±SO ppm of reading/oC
of Gain
(typical) ±100 ppm of
reading/oC (maximum)
Sampling Time ......•.. 83.3 mS (nominal)
Sampling Rate .....•... 3 conversions per second

DISPLAY
Number of Digits ..•...• 3 decimal digits and most
significant "1" digit (3% digits)
Decimal Points ......... Selectable using decimal
pOint select signal lines.
Display Type .......•.•• Field-effect liquid crystal
display (LCD)
Display Height ••.•..•.. O.S" (12,7mm)
Overscale .•..•.....•... Inputs exceeding the fullscale range display "+1"
MSD with zeroes blanked.
Autopolarlty .......••.. A "+" sign is automatically displayed for positive inputs and
a "0" sign for negative inputs.
The user may blank the polarity.
Descriptors ...•..••..•• 0, kO, mA, mV, AC, dc, A, V.
This field of function labels is positioned to the right of the decimal
digits. Individual unit descriptors
may be selected for display.
POWER REQUIREMENTS
AC
'.4 watt, maximum, 11S or 230V AC.
de
+9 to +lSV dc, filtered@9mAtypical,20mAmaximum. Logic
spikes must be less than SO mY.

PHYSICAL
External Dimensions
2.S3"W x 3.2S"D x 0.94"H (64,3 x 82,S x 23,8mm)
Panel Cutout Dimensions
2.S6"W x 0.97"H (6S,l x 24,mm)
Mounting Method
Refer to end of this section.
Weight
S ounces (142g) approximately
ENVIRONMENTAL
Altitude
o to lS,OOO feet (4900m)
Operating Temperature Range
+32°F to 122°F (0° to SO°C)
Storage Temperature Range
+32°F to 131°F (0° to SS°C)
Relative Humidity
20% to 80% non-condensing

1/0 SIGNAL FEATURES
Besides the common liD Signals defined elsewhere, this
device also has some important liD features.
Horizontal Polarity In (Pin A11)
Horizontal Polarity Out (Pin B11)
Normally these inputs are jumpered together to continuously
display the horizontal portion of the polarity sign.
Vertical Polarity In (Pin A12)
Vertical Polarity Out (Pin B12)
Jumper these inputs when HORIZ. POL. is jumpered for
automatic sign display with bipolar inputs. For reverse sensing
applications VERT. POL. OUT may be jumpered to HORIZ.
POL. IN (no other connections). This will display a minus sign
with positive inputs and no sign (implied positive) with negative
inputs. See BACKPLANE OUT.
Backplane Out (Pin B10)
Connect all unused polarity, decimal points and descriptor pins
to BACKPLANE OUT.
Descriptors
Electrical units are displayed by connecting their respective
pins to DESCRIPTOR COMMON Pin Bll.

REFERENCE OUT
ANALOG LO IN
~J\ OSCRPTR IN
~n DSCRPTR IN
Kfi DSCRPTR IN
"'~ DSCAPTFt IN
m~ DSCRPTA IN
DC OSCRPTA IN

AC DSCRPTR IN

1
2
3
4
5
6
7
8

9

!:!!V DSCRPTR IN 10

KORtZ POL IN

11

REFERENCE IN
OHMS LO
OFFSET OUT (OPT.)
ANALOG HI IN
+9VDC PWIt IN
DISPLAY TEST
DEC 1'1 199.9
DEC 1'1 19.99

DEC 1'1 1.999
a4CKPlANE OUT

HIIZ. POL OUT/DP. COM

REFERENCE OUT

I

REFERENCE IN

2

OHMS LO

3
4
5
6

OFFSET OUT iOPl.)
ANALOG HI IN
+9VDC PWR IN
DISPLA~ TEST

IN
IN
IN
IN

;
9
10
II
12

DEC I>T 1.999
BACKPLANE OUT
HRZ. POL OUTlDP, COM
YERT POL OU,T

230 YAC La

14

NO CONNECTION

ANALOG LO IN

!!lA
I(n
K{)
mA

aSCRPTR
DSCRPTR
DSCRPTR
DSCRI>TR

IN
IN
IN
IN

~~ ~:~::~:::

CALIBRATION
A multiturn screwdriver pot adjusts the full scale reading (gain).
Zero is automatic (autozeroing). Suggested recalibration in
stable conditions is 90 days.

AC DSCRI>TR
my DSCRI>TR
HORIZ POL
VERT I>OL

~:~:~ ::.9~:

:~T~~:::ECRT:~~E ~.; B~~~E:AZG:IIN5T
NEGATIVE RAlliPIN B13)

10-62

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DM-3100X
Micropowered 3% Digit
LCD Panel Meter

FEATURES
• Consumes very low power
• Dual dc-voltage power In (+5V de or +9 to +15V de)
• Balanced high-Impedance differential Inputs
• 80 dB CMRR
• Autozerolng capability
• Standard:!: 1.999V de input range; user-installed
options set other voltage or current ranges.
1. Accepts shunts for ± 20 ,..A to ± 2A FS ranges
2. Accepts attenuators for ± 2V to ± 200V FS ranges
3. Digital ohmmeter, 2000 to 10MO FSR
GENERAL DESCRIPTION
The DM-3100X is a 3Yz digit LCD display device. The DPM
consumes typically less than 0.03 walts. Powered by a range of
+4V dc to +15V dc the DM-3100X may be configured to
measure different voltage, current and resistance ranges. The
DPM is contained in a short-depth case.
The versatility of this meter is further enhanced by its
autozeroing circuits which eliminate zero drift.
This DPM accepts a dc or slowly varying input voltage and
displays that input on front panel numerical indicators. It
employs a conventional dual-slope A/D converter plus 7
segment display decoder-drivers all in one LSI microcircuit.
Since this microcircuit requires approximately 9V to power the
AID section, an internal dc/dc converter generates -5V from
+5V power input. Together these two voltage sources form a
bipolar power supply to power the A/D converter. The DM3100X may also be powered directly from a single 9V battery @
3 mA without using the dc/dc converter.
The DM-3100X employs a balanced differential input. When
used with a bridge or transducer input, it offers high noise
immunity and can accurately measure very small signals in the
presence of much larger common mode noise. The DPM's
high-impedance input circuits .will not load down the sensitive
input circuits.
The meter can be operated·ratiometrically. That is, the DPM's
internal circuits automatically compensate for references drifts
in the supplies of balanced bridge or transducer sensors and
still give accurate readings.

The DM-3100X finds use in analytical instruments, industrial
process controllers, portable diagnostic instruments, automatic
test equipment, medical instruments, airborne, marine, and
ground vehicles, and data acquisition/ data logging systems.

ORDERING INFORMATION
DM-3100X-l
Description
3 1/2-digit LCD DPM
(Includes one connector)
ACCESSORIES
Part Number Description
58-2075010
Connector, dual 18-pin,
0.1" centers
UPA-5/500
115VACto ±5V de (@500mA)
power adaptor

Model
DM-3100X-1

POSITIVE RAIL
,-----r---~---r__--......,..--------~-r_-

AI7

,-------1--+-- 814
ANA. RTN AI

.---!--- 813

-=:;:-:-=----+<><

DEC PT COMMON

AlO·A12

DECIMAL POINT SELECT

89 HORIZ POL OUT
815 HQRIZ POLIN

ANA. HI IN A4 ......-vvo~.,----i
ANA. LO IN A2 ---~--IA

r----

AlDPWR.IN
DISPlAYTEST

A17

VERT POL IN

818

VERT POL OUT

AlB

5V DC/DC GNO

REF. IN 86

L_--REF. OUT A6 -----·---t--r--+----H_~
EXT. REF. LO 816

'--_----1'_ _ _ _ _......_.L._-4-_ _ _y_-4--"_ _ _....._ _ _ _ _ _>-_ _---''--_

+5V DC/De POWER IN

816

9VPWACOM

NEGATIVE RAIL
OHMS La B2 _ _ _ _ _ _ _ _ _ _ _ _ _....J

Simplified Block Diagram of a DM-3100X

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-63

I

II

DM-3100X
FUNCTIONAL SPECIFICATIONS
(Typical at 25°C,2V range unless noted)

ANALOG INPUT
Full-Scale Input ........ Refer to "FEATURES"
Range
Ranges field-modifiable.
Input Impedance . ...... 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current ...... 5 pA (typical) 50 pA
(maximum)
Input Overvoltage ...... ±250V dc, 175V RMS
continuous (maximum)
±300V dc intermittent
(maximum)
External Reference . .... ±1 00 mV to ±2V referred
Range
to -Vs
Common-Mode ........ 80 dB (typical),
Rejection
from dc to 60Hz, with 1
Kilohm unbalance
Common-Mode ........ Both the inputs must
Voltage Range
remain within 0.5V dc below
+5V dc supply and 1.0V dc
above -5V dc supply
Resolution ............. 1 mV
Display Accuracy . ...... Adjustable to ±0.1 % of
reading, ±1 count
Temperature Drift ...... Autozeroed ± count
of Zero
over O°C to +50°C
temperature range
Temperature Drive ..... ±50 ppm of
of Gain
reading/oC (typical) ± 100
ppm of reading/oC
(maximum)
Sampling Time . ........ 83.3 .mS (nominal)
Sampling Rate ......... 3 conversions per second
DISPLAY
Number of Digits . ...... 3 decimal digits and most
significant "1" digit (3Y, digits)
Decimal Points . ........ Selectable using decimal
paint select signal lines
Display Type . .......... Field effect liquid cryslal
display (LCD)
Display Height ........ . 0.5" (12.7mm)
Overscale . ............. The inputs exceeding the fullscale range display "+1 "
MSD with zeroes blanked.
Autopolarlty ........... A "+" sign is automatically
displayed for positive inputs
and a "-" sign for negative
inputs. The user may blank
the polarity.

Mounting Method
Refer to end of this section.
Weight
5 ounce (142g) Approximately
ENVIRONMENTAL
Altitude
o to 15,000 feet (4900m)
Operating Temperature Range
+32°F to 122°F (O°C tp 50°C)
Storage Temperature Range
+32°F to 131°F (O°C to 55°C)
Relative Humidity
20% to 80% non-condensing

I/O

SIGNAL FEATURES
Besides the common I/O Signals defined elsewhere, this
device also has some important I/O features.
Decimal Points
Connect selected pin to DECIMAL POINT COMMON (Pin
B13). See Backplane Out.
Horizontal Polarity In (Pin B15)
Horizontal Polarity Out (Pin B9)
Normally these inputs are jumpered together to continuously
display the horizontal portion of the polarity sign. Omit the
jumper for applications not requiring sign display. See
Backplane Out.
Vertical Polarity In (Pin B17)
Vertical Polarity Out (Pin B18)
Jumper these inputs when HORIZ.POL. is jumpered for
automatic sign display with bipolar inputs. For reverse sensing
applications, VERT.POL. OUT may be jumpered to HORIZ.POL.
IN (no other connections). This will display a minus sign with
positive inputs and no sign (implied positive) with negative
inputs. See Backplane Out.
Backplane Out (Pin A13)
Connect all unused Polarity, and Decimal Points to Backplane
Out. For YOM or DVM applications, a 470 kCl resistor may be
used for each Decimal Point. A rotary switch pole to BI3 will
then select th.e desired Decimal Point.

INPUT/OUTPUT CONNECTIONS

~

'1

NO CONNECTION
OHMS LO

NO CONNECTION

3

NO CONNECTION
NO CONNECTION
NO CONNECTION
REFERENCE IN

~

NR~F~~::~~T~~~ t-i

PHYSICAL
External Dimensions
Short-Depth Case 3.0"W x 2.15"D x 1.76"H (76,2 x 54,6 x
44,7mm)

OOX

ANALOG RETURN
ANALOG LO INPUT
ANALOG HI INPUT

POWER CONSUMPTION
The DPM requires 5V dc regulated at 12 mA typical and 15 mA
maximum, or 12V dc regulated, at 12 mA typical and 15 mA
maximum or 15V dc regulated at 18 mA typical and 20 mA
maximum. The logic spikes must not exceed 50 mY.

DM~31

TOP B

BOTTOM A.

NO CONNECTION 7
NO CONNECTION 8
NO CONNECTION 8
DEC PT 118.' 10
DEC PT 1 .... 11
DEC PT 1.888 12
BACKPLANE OUT 13
NO CONNECTION 14
NO CONNECTION 15

+sv

NO CONNECTION
NO CONNECTION
HORIZ POL our
NO CONNECTION
NO CONNECTION
NO CONNECTION
DEC PT COM
DISPLAY TEST
HORIZ POL IN
DC/DC PWR COM 18 +8V PWR COM

AID PWR IN 17 V,ERT POL IN
+5V DC/DC PWR IN ~ VERT POL OUT
NOTE: REFERENCE IS BIASED AGAINST
NEGATIVE RAIL (EXT. REF. LO),

Panel Cutout Dimensions
3.062"W x 1.812"H (46,0 x 77,7mm)

10-64

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DM-3102A, DM-3102B
AUTORANGING 31/2 DIGIT
PANEL METERS
FEATURES
• Two Model Ranges
-Model DM-3102A: 200 mV, 2V, 20V, and 200V dc
lull scale autoranges
-Model DM-3102B: 2V, 20V, 200V, and 1000V dc lull
scale autorangel
• Accuracy Adjustable to ±0.1% or ±1 count over any
lull Icale range
• 3'1t Digit LCD displays .S" high (12,7mm)
• Low power consumption, SV dc at 30 mA typical
• Multiplexed BCD data outputs to drive a slave display
• -SV dc power output at lS mA lor external low power
circuitry
• Seven unit descriptors: K, n, m, DC, AC, V, A
• Balanced dillerential Inputs with 9 megohms nominal
Input Impedance

DISPLA Y DESCRIPTOR SELECTION
The DM-31 02A1 B display allows enabling optional unit
descriptors by jumpering pins on the converter PWA. Polarity
and overrange indicators, as well as the unit descriptors, are
driven by logic on the converter PW A.

PIN
A3

GENERAL DESCRIPTION
The DM·3102 is a 3% digit, four decade, autoranging digital
panel meter (DPM) with true balanced differential analog
inputs. The low profile DPM is available in two model
configurations. Model DM-31 02A has 4 full-scale ranges of 200
mV, 2V, 20V, and 200V dc while Model DM-3102B has 4 fullscale ranges of 2V, 20V, 200V and 1000V dc.
Both models are powered from a +SV dc power source,
typically drawing ISmA. Output power of -SV dc at ISmA is
available to the user for powering low power external circuitry.
The multiplexed BCD data outputs allow interfacing the DPM to
micro-processors or UART'S. They may also drive an
additional slave display meter. This is made easier with the
presence of the STROBE, RUN/HOLD and BUSY IDONE
signal lines. A RUN/HOLD signal freezes the display and stops
AID conversions. Based on a single chip CMOS AID
converter, the DM-3102A/B autoranging meter has an
accuracy of ±1 count in 20,000 counts, or .1 % of any full scale
range.
Typical conversion cycle time of the AID converter is 300
milliseconds. (Worst-case autoranging time interval would be
900 milliseconds maximum.) Analog input signals enter
through a.l % matched resistor network and typical signal input
impedance is 9 megohms.

INTERFACING
To reduce the amount of wiring required to implement a slave
display, four-wire BCD data is multiplexed using four digit drive
outputs. Each digit drive sequentially turns on its respective
signal when the drive signal is high. The digit is blanked when
the drive line is low. The DM-31 02A1 B minimizes the wiring to a
remote display, UART, or microprocessor since only 14 wires
are needed to transfer the data which include 4 BCD data lines,
4 digit strobes, 4 range indications, polarity, and BUSY IDONE.

BS

A2

Al

Bl

B2

B3

B4

n

K

DESCRIPTORS
'm [V]' m [A)

AC

DC

'[m) V' '[m) A'

To activate the desired unit descriptor, the corresponding pin
must be connected to pin B6 B.P. (display common). Connect
any unused unit descriptors to pin B12 (B.P.)

ORDERING INFORMATION
Model

Description

DM-3102A

Digital panel meter autoranging
200mV, 2V, 20V, 200V full scale
ranges. (Includes two connectors)
Digital panel meter autoranging 2V,
20V, 200V, 1000V full scale ranges.
(Includes two connectors)

DM-3102B

ACCESSORIES
Part Number
Description
S8-2073083

UPA-S/SOO
DM-4106

Dual IS-pin, 0.100" centers PC
edge board connector (Not included
- order two with DPM).
AC to +SV dc power adapter.
Low-profile Slave Display
(No description)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-65

II

DM-3102A and DM-3102B
FUNCTIONAL SPECIFICATIONS
(Typical at +2S O C, 2V range unless otherwise noted)
ANALOG INPUT
Configuration •••.•.•.•• True balanced differential
bipolar inputs If single-ended
inputs are preferred, close
SG4 solder gap.
Full Scale Input Range
DM-3102A •••••••••.. ±200V dc
DM-3102B .•••.•••••• ±1000V dc
Input Bias Current •.••.. 1 pA typical, 10 pA maximum.
Display Accuracy •..••.. Adjustable to ±0.1% of
reading, +1-1 count.
Warm-Up Time •••....•. 5 minutes.
Resolution ••.••••...... 100 uV in last digit (200mV
range only).
Temperature Drift .•.•.. Autozeroed, ±1 count
of Zero
over O°C to +50°C
temperature range.
Temperature Drift .••... ±50ppm of
of Gain
readingl °C typical ±100ppm of reading/OC
maximum.
Input Impedance •...... 9 Megohms, nominal.
Input Overvoltage ..••.. ±300 volts dc intermittent
maximum, 175 VRMS
continuous maximum on the
200V range, model A.
±350 volts dc intermittent
maximum, 1500 VRMS
continuous maximum on the
1OOOV range, model B.
Reference ••••.••..•.•• Internal, referred to Analog
Common, (between pins
A131 B13). An external, usersupplied reference referenced
to pin B15 is optional for
ratiometric operation.
External Reference ••••. +90mV to +200mV dc
Range
referenced to Analog
Common, pin B15.
Common-Mode •....... Both inputs must
Voltage Range
remain within ±3V dc of
Power Common. The user
must provide external circuitry
to keep the inputs within the
comrnon-mode range.
DISPLAY
Number of Digits .....•• 3 decimal digits and most
significant "1" digit (3%
digits).
Display Type .••••...... Black digits on white Liquid
Crystal Display (LCD).
Requires external illumination
under low ambient light
conditions.
Display Height .•.•.•.•. 0.5 inches (12,7 mm).
Overrange ......••••... Inputs exceeding the full
scale range cause the 'OR'
symbol in the upper left
corner to flash (A Model
only).
Autopolarlty ......••••• A plus or minus sign is
automatically displayed for
positive or negative voltage
inputs. The polarity display
may be disabled by opening
solder gap SG1.
10-66

Sampling Rate ••••••••• Approximately 3 conversions
per second.
Decimal Points ••••••.•• Automatically shifted by autoranging logic.

POWER REQUIREMENTS
External
+5V dc unregulated is required at 15mA typical, 30mA
maximum. Logic spikes must not exceed 50mV. [Note: Any
current consumed by external devices using the -5V output
(pin A15) must be added to +5V power consumption to yield
total meter power consumption.]
Power Output
-5V dc unregulated is available to the user by closing solder
gap SG2 (normally open). The solder gap is located on the
bottom of the converter I display board.
PIN DETAILS
PIN# SIGNAL DESCRIPTION
Analog HI Input (PINS AlB12)
Analog La Input (PINS A/B9)
Differential input signals are applied to pins A/B12 and A/B9. A
single-ended input configuration is available by closing solder
gap SG4. This effectively ties the ANALOG La to input (pins
AlB9) to ANALOG COMMON (pins AlB15).
Reference IN/Out (Pins A13/B13)
The instrument is calibrated when a +0.1V dc drop exists
between pins B13 (+) and B15 (-). An internal reference
voltage circuit, adjustable by potentiometer R3, provides this
reference voltage. To use this internal reference, the user joins
pins A13 and B13 at the connector. If the user wishes to
generate an external reference voltage, pin A13 is used as the
input, biased against pin B15.
Busy/Done Out (Pin Al1)
This output is High during AID conversions. The falling edge
indicates that a new valid digit Strobe output will appear in 1.3
milliseconds. The high Busy level may be used by automatic
equipment to prevent changing the input voltage during
conversion.
Digit Strobe Out (Pin B7, B8, B9, B10)
Strobe consists of 4 positive pulses per conversion of
approximately 4 microseconds width and approximately 1.6
milliseconds apart issued after an AI D conversion. They
indicate that valid multiplexed data is available on the BCD data
output lines, starting with the Most Significant Digit (MSD). The
Polarity of the BCD data is not multiplexed out with the BCD
data. A fifth line (Polarity Out, Pin A12 must be polled io
determine the sign.
Run/Hold IN (Pin Bll)
For normal operation, leave this pin open. Grounding Pin Bll
halts AI D conversions and displays the last valid sample until
the pin returns to a high state.
Polarity Out (Pin A 12)
A high on this line indicates a positive input; a low indicates a
negative input. This output is valid even for a zero reading. In
other words, a display of +0000 means that the signal is positive
but less than the LSB.
-SV·Power Out (Pin A1S)
Up to 15mA of -5V dc power may be taken to power external
user -supplied circuits such as signal conditioners.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DM-3102A and DM-3102B
PHYSICAL-ENVIRONMENTAL
Outline Dimensions

INPUT OUTPUT CONNECTIONS DM-3102 A, B
ANALOG AND POWEll Inl-IOTToM 80ARD

2.53"W X 3.34"0 X 0.94"H (64,3 X 85 X 23,8mm).

m,!, OSeRPTI! IN

m

DC DSCRPTR IN
AC DSCRPTR IN

m!l DSCRPTR IN 2

Cutout Dimensions
2.562"W X 0.97"H min. (65,1 X 24,6mm)
Weight

~nDSCRPTR IN
J
~ii"DSCAPTR IN 4

!!lV DSCRPTIlIN
DEC PT 199.9 IN

KEVWAY-_
--KEYWAY
mA DSCRPTR IN 5 DEC 1'110.119 IN

BACKPl;NE tolSP COM)

6

INPUT OUTPUT CONNECTIONS DM·3102 A, 8

DEC PT 1.999 IN

:£\'HC ,~ 1~ ]~;:

Approximately 5 ounces (142g).

Connector

RUN'iiOlD IN

11

CONTROL IJll - TOP BOARD

2Q~:VI~~~; ::~~~

BUSY/DONE OUT

~OV

REFERENCE OUT 13 REFEIIENCE IN
·SV DC PWII IN 14 PWII COMIIION
ANALOG COM 15 -5V DC PWA OUT

LC~'s

(200V) AANGEf1J.
~_ 'm'SVMBQlll.9991 our

200~i~i:::~~:~~~ ~~c }:~~9:: ;::T~:: ~~~
:~ ~~:::~;:~:iLf;:: ~~:::~;:~:

Mounting Position
Limited by readability of

tE ~~ ~~:::~~:~:

KEVWAV--_ _ _ _ _ KEYWAV

8ACKPlANE OUT 12 POLARITY OUT

Two dual 15-pin, 0.100" centers, Datel Part #58-2073083 (two
included with meter).
(typical viewing angle of 70%).

ANALOG lO IN (-I 9 ANALOG LO IN
NO ~TCH
10
NO eTCH
NO eTCH
ANALOG HI IN (»

11
12

NO ETCH

13

Operating Temperature Range
32°F to 122°F (O°C to +50°C)

1-1

NO ETCH
ANALOG HI IN (>1
NO ETCH

NO ETCH

14

NO ETCH

ANALOG COM

15

ANALOG COM

Altitude

o to 15,000 feet (4,900m)
Storage Temperature
-13° F to 185°F (-25°C to 85°C)

Relative Humidity
20% to 80% non-condensing
'NPUT/OUTPUT CONNECTIONS OM

3~.:::d

ANALOG AND POWER 1J2) eonOM BOARD
TOPB

INPUT OUTPUT CONNECTIONS OM-3102
CONTROL (Jll - TOP BOARD
BOTTOM A
200mV 12V) RANGE
2V (20V) RANGE

ttl
2

TOPB
NO CONNECTION
NO CONNECTION

Ib--

NO CONNECTION

NOCONNECTION
ANALOG LO IN 1-1

IB"LONG

:::::>::hJ-

ANALOG HI IN(+1
t.K)ETCH

NOETCH
ANALOG COM

,-,

t--g
~

~

f---ts

'--

~ DSCRPTR

2

kll DSCRPTR

3

.!SP OSCRPTR

4

DC DSCRPm
AC DSCRPTR
mV D$CRPTR
DEC PT 199.91N
_-KEYWAY

..

~-.~-" f "'"

~(DlSPCOM)

t--"5

hi D~r::::::::;

nI.

;

KEYWAY-_

KEYWAY---r- _KEYWAY
20V(l200V)AANGE
3
'm'SYMBOlll.99910UT
200V(1000V) RANGE ~
199.9 OUT
NOCONNECTION
NOCONNECTION

BOTIOMA

~ m!!. DSCRPTR

DIGIT

OR'"
OUT

NO CONNECTION
NOCONNECTION
ANALOG LO IN I_I

6

l

04 MSB
03
02
01 lSB

RUN/HOlD IN
BACKPLANE OUT

NO ETCH

REFERENCE OUT

-

NO ETCH

"" 5

ANALOG HI IN /+'
NO ETCH

voe

rANAlOGCOM

BCD

9.2

OUT

10

B, lSB

"
"
"

BUSY/DONE OUT
POLARITY OUT

"

NO ETCH
ANALOG COM

,+,

B8-MSB

54

13

PWRIN

DECPT1.999IN

7

8

REFERENCE I N PWRCOMMON

-5 VOC PWR OUT

I

1

+5V COM

,~,

RED

DM-3102A Wiring Diagram

BLACK

INPUTfOUTPUTCONNECTIONS OM 3102
ANALOG AND POWER (Jl) BOTTOM BOARD
INPUT OUTPUT CON"IECTIONS DM-31 02
CONTROL (JI) - TOP BOARD

mV DSCRPTR
~ DSCRPTA
!Ill DSCRPTR

200mVl2Vl RANGE r~ NOCONNECTION
2Vl20VIRANGE
"1O CONNECTION
KEYWAY-_
_-KEYWAY

~I DSCRPTA
KEYWAY-_

CD

20VII200VlRANGE
200V 11 OOOVl RANGE
NO CONNECT~ON
NO CONNECTION
NO CO"lNECTIO"l
.-----A"IALOGLOIN I-I

3

m SYMBOL I L999) O U T - - - + - - - - - - t - t - - '

199.9 OUT
6

9

DEp~ I:.~:: I'::.~:: ~~~

NOCONNECTION
NO CONNECTION
ANAlOGLOIN I-I

====t=====::::t---'

mAOSCRPTRIN
BACKPL;NE (OI$PCOMI
DIGIT
DRIVE

l~; MSS

~
2
3

4

~
6

11'1' lONG

DEC PT 19.991N
DEC PT 1.9991N

D2
DllSB

9

B2

10

81 lSB

RUN/HOLD IN

11

BU$Y/DONE OUT
POLARITY OUT

OUT

II

---+----'

; ::.MS8!OCD
12

NO ETCH
ANALOGHIIN(+I

DC OSCRPTA
AC DSCFlPTR
mV DSCRPTA
DEC PT 199.91N - - - t - - '
_-KEYWAY

OUT

REFERENCE OUT

11

NO ETCH

12
13
14
15

ANALOG HI IN (+1
"1O ETCH
NO ETCH
ANALOGCOIVI _ _ _ _ _

,---+- +

5VDCpWRIN

14

-;:~~:~~:T,-==:::j::!::::::;-I

-+_-,
+5V COM

DM-3102B Wiring Diagram

,+,
BLACK

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-67

OM-41 000
4~

Digit Panel Meter
with Tri-State Data Outputs

FEATURES
• Trl-state BCD data outputs
• Data outputs gated for use with 4-, 8-, 12- or 16-blt
bus structures
• Standard:!: 1.9999V dc input range; user-installed
options set other voltage or current ranges.
• High-Impedance differential Inputs with low 5 pA bias
currents
• Autozerolng, ratlometrlc for drift-free operation
• Low power consumption: +5V dc at 500 mA
• Provides ±13.5V dc outputs at 20 mA for external
circuits
• Up to 30 conversions per second possible
• Designed for single-ended, bipolar Inputs
GENERAL DESCRIPTION
The DM-41 000 provides full 4% digit DPM capabilities with tristate BCD outputs. Built-in ability to provide 3Y, digit displays
with 10 times the normal sampling rate. Designed for singleended inputs, this meter has all the features found in DA TEL's
DPM product line plus voltage and data outputs. The unit is
accurate to within .02% FSR (±2 counts). Input circuitry is
autozeroed on each conversion cycle to reduce zero drift. All
this performance has been packed into a low-profile black
polycarbonate case only 2.53" wide x 3.34" deep x 0.94" high
(64,3 x 85 x 23,8mm).
The DM-41 OOD's 3-state BCD outputs take it beyond many socalled "microprocessor-compatible" OPM's. The 3-state
outputs mean that the meter can be connected directly to a
microcomputer's data bus. They also permit multiple OM41000's to be daisy-chained to a single set of computer or
printer input connections - the computer inputs "see" only
those meter outputs which have been enabled. And, since each
4-bit group (corresponding to a single BCD-encoded numeral)
may be gated separately, a single rear-panel change makes
the DM-41 000 compatible with processors using 4-, 8-, 12-, or

ORDERING INFORMATION
Model
OM-41 000-1

DM-4100D-1
Description
Micro-bussable 4 1/2-0igit,
single-ended input OPM
(includes 2 connectors)

ACCESSORIES
Part Number Description
58-2073083
UPA-5/500

Dual 15-pin edge connector,
0.1" centers
115V AC to 5V de power adaptor

ANA

COM

LED DISPLAY

3-STATE

BCD

B~D
BCD
10K
INSTALLED RANGE CHANGE

OR (R2) CURRENT SHUNT
RESISTORS

OUT
OF

SCD
lK

\

OVEARANGE V

OUTPUT

4K

BCD
100

BCD
400

~~

RANGE

'A1 AND R2 ARE USER

I

1,0Cl0'S DIGIT OUT (MSO)

10

40

~

100'5 DIGIT OUT

10'S DIGIT OUT

BCD
1

I

1

!d
BCD
4

,----y----'
1'S DIGIT OUT (LSD)

BCD 10K AND

AUK OUTPUTS

Simplified Block Diagram of a DM-4100D
10-68

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DM-4100D
16-bit data words. Digital outputs for the Display Polarity,
Underrange, Out of Range, E.O.C., "Data Ready" (a 10
ILsecond pulse occurring 10 ILseconds after the digital data is
valid), and meter Run/Hold status make microcomputer
control of the meter possible with minimal external hardware.
Sufficient control circuitry is already built into the DM-41 000 so
that it can directly interface with DATEL's DPP-Q7 thermal
printer (or a similar printer) to become a functional data logger.
The DM-41 ODD's input CMOS circuitry can safely handle overvoltages to ±2S0V dc. The meter's converter board contains
blank circuit pads to accept input attenuation resistors or
current shunts. Temperature drift of the autozeroed input
amplifier is ±1 count from 0° to +SO°C. Temperature drift of
gain measures ±SO ppm of FSRI °C (typical) and ±1 00 ppm of
FSR/oC maximum.
The DM-41 000 uses a dual slope integrating converter which
provides normal mode rejection of AC power line noise. It
provides an input-to-output conversion linearity to within
±.02% of reading, or ±2 counts. The standard sampling rate is
3 conversions per second, but a rear pin connector may be
used to disable the least significant digit. In the 3Y2 digit mode,
the DM-4100D provides 30 conversions/ second.
Power to the meter is +SV dc @ 380 mA typical (SOO mA
maximum), and may be supplied directly from a microcomputer bus. A built-in dc-dc converter (to power the meter's
analog input circuitry) provides ±13.SV dc ±S% (@ ±20 mA
max.) to power user-supplied circuitry. The ±13.SV output was
specifically intended to power an external instrumentation or
CAZ amp, providing the DM-41 000 with a differential analog
input. DATEL's UPA-S/SOO, SV @ SOOmA power supply is
available as an accessory.

NOTE: The DM-41 ODD's display is not latched; the display may
not track the meter's BCD data out.

DISPLAY
Number of Digits . ...... 4 decimal digits and most
significant "1" digit (4Y2 digits)
Decimal Points . ........ Selectable using decimal
point select signal lines.
Display Type . .......... Red LED's
Display Height ........ . 0.3" (7,6 mm)
Overscale .............. The display flashes when
inputs exceed the full-scale
range.
Autopolarlty ........... A "+" sign is automatically
displayed for positive inputs
and a "-" sign for negative
inputs. The user may blank
the polarity using the
POLARITY ENABLE line.
CALIBRATION
A multiturn screwdriver pot (rear-panel mounted) adjusts the
full scale reading (gain). Zero is automatic (autozeroing).
Suggested recalibration in stable conditions is 90 days.
POWER CONSUMPTION
The DPM requires +SV dc regulated (±S%) at 380 mA typical
and SOD mA maximum. Logic spikes must not exceed SO mY.
Any current taken from the ±13V dc outputs must be added to
the above specifications to yield the total meter power
consumption.

FUNCTIONAL SPECIFICATIONS
(Typical al 25°C, 2V range unless noted)
ANALOG INPUT
Full-Scale Input ........ Referto "FEATURES"
Range
Ranges field-modifiable.
Input Impedance . ...... 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current . ..... S pA (typical) SO pA
(maximum)
Input Overvoltage ., .... ±2S0V dc, 1SSV RMS
continuous (maximum)
±300V intermittent
(maximum)
External Reference . .... +1 00 mV to +2V
Range
referred to Analog Common
Common-Mode ........ 80 dB (typical),
Rejection Range
from dc to 60 Hz, with 1
Kilohm unbalance
Common-Mode ........ Both the inputs must
Voltage Range
remain within O.SV dc below
the +SV dc supply and 1.0V
dc above the -SV dc supply.
Resolutlon ............. 1 mV (least significant digit)
Display Accuracy . ...... Adjustable to ± 0.02% of
reading, ±2 counts
Temperature Drift ...... Autozeroed ±1 count
of Zero
over 0 to +SO°C temperature
range
Temperature Drift . ..... ±SO ppm of
of Gain
reading/ °c (typical) ±100
ppm of reading/DC
(maximum)
Sampling Time . ........ 83.3 mS (nominal)
Sampling Rate ......... 3 conversions per second.
May be rewired for up to 20
conversions per second

PHYSICAL
External Dimensions
2.S3"W x 3.34"0 x 0.9S"H (64,3 x 8S x 23,8mm)
Panel Cutout Dimensions
2.S62"W x 0.97"H (6S,1 x 24,6mm)
Weight
Approximately 4.1 ounces (116 grams)
ENVIRONMENTAL
Altitude
o to 1S,OOO feet (4900m)
Operating Temperature Range
32°F to 122°F (0° to SO°C)
Storage Temperature Range
-13°F to +19soF (-2S0C to +8S°C)
Relative Humidity
20% to 80% non-condensing

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-69

DM-4100D
I/O SIGNAL FEATURES
Besides the common I/O Signals defined elsewhere, this
device also has some important I/O features.

J2 ANALOG CONNECTOR (LOWER)
-13V, +13V de Power Out (Pins B11, B12)
Up to 20m A of unregulated + and -13.5V dc power may be
taken directly from the meter to power external usersupplied circuits such as signal conditioners.
Analog H1 Input (Pin B5)
Signal input normal voltage range is -1.9999 to +1 .9999V dc.
3'10/4'1. Mode Input (Pin B9)
Leave open or high for 4% digit mode. Logic low (connected to
POWER COMMON) causes Least Significant Digit to read
permanent zero, and causes meter to operate in 3Y, digit mode.
Conversions in 3% digit mode occur at 10 times usual speed,
i.e., 30 conversions per second.
+5V In (Pin B14)
Power input to the meter; connections made between +5V IN
and POWER COMMON (pins A 14 and B13); requires
regulated supply (±5%), capable of supplying 500 mA
maximum.
J1 DATA CONNECTOR (UPPER)
Digit Enable Input
These are active high, and operate on data in groups of 4 bits
(e.g., Enable 1D's controls BCD 10, 20, 40 and 80; Enable
10,000's controls BCD 10,000 (overrange), PLUS/MINUS,
OUT OF RANGE, and UNDERRANGE.
Enable 1's (Pin AI)
Enable 10's (Pin A6)
Enable 100's (Pin B1)
Enable 1,000's (Pin B6)
Enable 10,000's (Pin A11 )
BCD Data Outputs
1, 2, 4, 8 (and 10, 20, 40, 80, etc) BCD data is fully latched.
Outputs are 3-state and controlled in groups of 4. Outputs are
DTLiTTL compatible, positive true, and sink 4.0 mA@ O.4V (2Y,
TTL loads).
BCD 1 (Pin A2), 2 (Pin A3), 4 (Pin A4), 8 (Pin A5)
BCD 10 (Pin A7), 20 (Pin A8), 40 (Pin A9), 80 (Pin A10)
BCD 100 (Pin B2), 200 (Pin B3), 400 (Pin B4), 800 (Pin B5)
BCD 1000 (Pin B7), 2000 (Pin B8), 4000 (Pin B9), 8000 (Pin
B10)
BCD 10,000 (Pin A12)
Plus/Minus Polarity Out (Pin A13)
This is true for positive input. 3-state latch enabled by pin A11.
BCD OUTPUT
Format
BCD outputs 3-state, gatable in 4-bit groups, full parallel output
available.

10-70

Fanout
2Y, TTL loads.
Logic Controls
E.O.C. pulse, "Data Ready" (Print Pulse), Overrange,
Underrange, Out of Range, PLUS/MINUS Polarity OUT, and
RUN/HOLD.
D.C. Power In
+5V dc, regulated (±5%), @ 380 mA typical, 500 mA
maximum.
D.C. Power Out
±13.5V dc, ±5%, @ ±20 mA, unregulated, for external signal
conditioning.

INPUT IOUTPUT CONNECTIONS DM-4100D
ANALOG AND POWER (J2)-BOTTOM BOARD
BOTTOM A

TOP B

REFERENCE OUT; REFERENCE IN
ANALOG COM 2 ANALOG COM
NO CONNECTION 3, NO CONNECTION
NO CONNECTION 4 NO CONNECTION
KEYWAY
....
KEYWAY
NO CONNECTION ~
NO CONNECTION ~
DISPLAY TEST ~
D.P. 1234.5 ~
D.P. 123.45~
D.P. 12.345 ~
D.P. l.Z345 ~
D.P. COM ~

ANALOG HI IN
NO CONNECTION
NO CONNECTION
POLARITY ENABLE
4 1/2 3 1/2 MODE
NO CONNECTION
-13.5V OUT (20mA)
+13.5V OUT (20mA)

NO CONNECTION ~ PWR COMMON
PWR COMMON 14 +5V IN
NO CONNECTION L...:.
~ DISPLAY ENABLE

INPUT I OUTPUT CONNECTIONS DM-4100D
DIGITAL INTERFACE (J t)-TOP BOARD
TOP B

BOTTOM A
ENABLE I',
KEYWAY

[1J ENABLE

100's

BCD 1 0 BCD 100
...
KEYWAY

I

BCD 2
.BCD 200
BCD 4 ~ BCD 400
BCD 8 ~ 8CD 800
ENABLE 10 ~ ENABLE lK
BCD 10 ~ BCD lK
BCD 20
BCO 2K
BCD 40 9 BCD 4K

r-!-

~

BCD BO
BCD 8K
ENABLE 10K ~ E.C.O.
BCD 10K 12 DATA READY

PLUS/MINUS OUT ~ RUNIHOLD
OUT OF RANGE 14 +5V IN
UNDERRANGE ~ DIGITAL COMMON

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DM-4101D
FEATURES
• Tri-state BCD data outputs
• Data outputs gated for use with 4-, 8-, 12- or 16-bit
bus structures
• Standard :!:1.9999V dc I.input range; user-installed options set other voltage or current ranges.
• High-impedance differential inputs with low 5 pA bias
currents
• Autozeroing, ratiometric for drift-free operation
• Low power consumption: +5V dc at 450 mA
• Provides ±5V dc outputs at 15 mA for external
circuits
• Designed for differential, bipolar inputs
GENERAL DESCRIPTION
The DM-41 01 D provides full 4Y, digit DPM capabilities along
with tri-state BCD outputs. Designed for differential bipolar
inputs, this device provides an ideal display function without
loading down sensitive input signals. The unit is accurate to
within .02% FSR (±2 counts). Input circuitry is autozeroed on
each conversion cycle to reduce zero drift. All this performance
has been packed into a low-profile black polycarbonate case
only 2.53" wide x 3.34" deep x 0.94" high (64,3 x 84,8 x
23,8mm).
The DM-41 01 D's 3-state BCD outputs take it beyond many socalled "microprocessor compatible" DPM's. Tri-state outputs
mean that the meter can be connected directly to a
microcomputer's data bus. They also permit multiple DM4101 D's to be daisy-chained to a single set of computer or
printer input connections - the computer inputs "see" only
those meter outputs which have been enabled. And, since each
4-bit group (corresponding to a single BCD-encoded numeral)
may be gated separately, a single rear-panel change makes
the DM-41 01 D compatible with processors using 4-, 8-,12-, or
16-bit data words. Digital outputs for the Display Polarity,

R, AND R7 ARE USER
INSTALLED RANGE CHANGE
OR IA,I CURRENT SHUNT
RESISTORS

41f2 Digit LED Panel Meter
with Tri-State Data Outputs

Underrange, Out of Range, E.O.C., "Data Ready" (a 10
microsecond pulse occurring 10 microseconds after the digital
data is valid), and meter Run/Hold status make microcomputer
control of the meter possible with minimal external hardware.
Sufficient control circuitry is already built into the DM-41 01 0 so
that it can directly interface with DA TEL's DPP-o? thermal
printer (or a similar printer) to become a functional data logger.

ORDERING INFORMATION
DM-4101D-1
Model
DM-41 01 D-l

Description
Micro-bussable 4 1/2 Digit DPM
(includes 2 connectors)

ACCESSORIES
Part Number Description
58-2073083
Dual 15-pin edge connector
UPA-5/500
115V AC to 5V dc power adaptor

~
1.00C),S DIGIT OUT (MSDI

10'S DIGIT OUT

"5 DIGIT OUT ILSD)

Simplified Block Diagram of a DM-4101D
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-71

DM-4101D
The DM-41 01 D's input CMOS circuitry can safely handle overvoltages to ±250V dc. The meter's converter board contains
blank circuit pads to accept input attenuation resistors or
current shunts. Temperature drift of the autozeroed input
amplifier is ±1 countfrom 0 to+50°C. Temperature drift of gain
measures ±50 ppm of FSR/oC (typical) and ±100 ppm of
FSR/oC maximum.
The DM-41 01 D uses a dual slope integrating converter which
provides normal mode rejection of AC power line noise. It
provides an input-to-output conversion linearity to within
±.02% of reading ±2 counts. The standard sampling rate is 3
conversions per second.
Power to the meter is +5V dc @ 380 mA typical (450 mA
maximum), and may be supplied directly from a microcomputer bus. A built-in dc-dc converter (to power the meter's
analog input circuitry) provides ±5V dc ±5% (@ ±15 mA
maximum) to power user-supplied circuitry. The ±5V output
was specifically intended to power an external instrumentation
or CAZ amp, providing the DM-41 01 D with a differential analog
input. DATEL's UPA-5/500, 5V @ .5A AC power supply is
available as an accessory.

FUNCTIONAL SPECIFICATIONS
(Typical at 25°C, 2V range unless noted)
ANALOG INPUT
Full-Scale .•....•....... See "FEATURES" range
Input Range
field modifiable
Input Impedance ....... 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current ...... 5 pA (typical) 50 pA
(maximum)
Input Overvollage •..... ±250V dc, 155V RMS
continuous (maximum)
±300V intermittent
(maximum)
External Reference ..... + 100 mV to + 2V dc
Range
referred to Analog Common
Common-Mode .•...... 80 dB (typical),
Rejection Range
from dc to 60 Hz, with a 1
Kilohm unbalanced input
Common-Mode •....... Both the inputs must
Vollage Range
remain within ±2V dc
maximum of power ground
Resolution ...........•. 1 mV (least significant digit)
Display Accuracy ......• Adjustable to ±0.2% of
reading, ±2 counts
Temperature Drllt ...... Autozeroed ±1 count
of Zero
over 0 to +50°C temperature
range
Temperature Drllt ....•. ±50 ppm of
of Gain
reading/oC (typical) ±100
ppm of reading/oC
(maximum)
Sampling Time •.......• 83.3 mS (nominal)
Sampling Rate .•....... 3 conversions per second.

10-72

DISPLAY
Number of Digits •••...• 4 decimal digits and most
significant "1" digit (4% digits)
Decimal Points ....•.•.. Selectable using decimal
point select signal lines.
Display Type .•......... Red LED's
Display Height ..••..... 0.39" (9,9 mm)
Overscale ...•.......•.. The display flashes when
inputs exceed the full-scale
range.
Autopolarlty ........... A "+" sign is automatically
displayed for positive inputs
and a "-" sign for negative
inputs. The user may blank
the polarity using the
POLARITY ENABLE line.
NOTE: The DM-41 OlD's display is not latched; therefore, the
display may not track the meter's BCD data output.
POWER CONSUMPTION
The DPM requires +5 dc regulated (±5%) at 380 mA typical
and 500 mA maximum. Logic spikes must not exceed 50 mY.
Any current taken from the ±5V dc outputs must be added to
the above speCifications to yield the total meter power
consumption.
PHYSICAL
External Dimensions
2.53"W x 3.34"D x 0.95"H (64,3 x 85 x 23,8mm)
Panel Cutout Dimensions
2.562"W x 0.97"H (65,1 x 24,6mm)
Weight
Approximately 4.1 ounces (116 grams)
ENVIRONMENTAL
Altitude
o to 15,000 feet (4900m)
Operating Temperature Range
32°F to 122°F (0° to 50°C)
Storage Temperature Range
-13°F to +195°F (-252°C to +85°C)
Relative Humidity
20% to 80% non-condensing
I/O SIGNAL FEATURES

Besides the common 1/0 Signals defined elsewhere, this
device also has some important 1/0 features.
J2 ANALOG CONNECTOR (LOWER)
+5V Out (Pin B12)
-5V Out (Pin B11)
These voltage outputs provide + 1A and -1 5 mA respectively to
power user-supplied external circuitry. May be used to power
an instrumentation or CAZ. amplifier.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DM-4101D
J1 DATA CONNECTOR (UPPER)
Digit Enable Input
These are active high, and operate on data in groups of 4 bits
(e.g., Enable 10's controls BCD 10, 20, 40 and 80; Enable
10,000 controls BCD 10,000 (overrange), PLUS/MINUS, OUT
OF RANGE, and UNDER RANGE.
Enable
Enable
Enable
Enable
Enable

1's (Pin A1)
10's (Pin AS)
100's (Pin B1)
1,000's (Pin BS)
10,000's (Pin A 11)

BCD Data Outputs
1, 2, 4, 8 (and 10, 20, 40, 80, etc) BCD data is fully latched.
Outputs are 3-state and controlled in groups of 4. Outputs are
DTLlTTL compatible, positive true, and sink 4.0 mA@ O.4V (2V2
TTL loads).
BCD 1 (Pin A2), 2 (Pin A3), 4 (Pin A4), 8 (Pin AS)
BCD 10 (Pin A7), 20 (Pin A8), 40 (Pin A9), 80 (Pin A10)
BCD 100 (Pin B2), 200 (Pin B3), 400 (Pin B4), 800 (Pin BS)
BCD 1000 (Pin B7), 2000 (Pin B8), 4000 (Pin B9), 8000 (Pin
B10)
BCD 10,000 (Pin A12)
Plus/Minus Polarity Out (Pin A 13)
This is true for positive input. 3-state latch enabled by pin A 11 .

INPUT OUTPUT CONNECTIONS

BOTTOM A

BCD outputs 3-state, gatable in 4-bit groups, full parallel output
available.

Fanout
2V2 TTL loads.
Logic Controls

TOP B

~~-1

REFERENCE OUT
ANALOG COM

21

-.~-1

NO CONNECTION

REFERENCE IN
ANALOG LO IN

NO CONNECTION

NO CONNECTION ~ NO CONNECTION
KEVWAV _ _ - - K E Y W A Y

s
-r :~ .~~:::~_~:~:

NO CONNECTION
NO

o

p,

8' POi-"-RITY-ENAS-LE

1234.5

D.P

12345

O.P

12.345

ANALOG til IN

fr
..

o~S~i~~~TTi'~

9 NO CONNECTION
NO CONNECTION
C.P 1.2345 ~I -5V CUl(15 mAl
OP COM 12 "'SV OUT
~'?

NO CONNEC nON~} PWR COMMON
PWR COMMON 14 +SV IN

DISPLAY BLANK IS DISPLAY ENABLE

INPUT IQUTPUT CONNECTIONS DM-4 1 0 1 0

DIGIT Al INTERF ACE IJ 1 )-TOP BOARD
BOTTOM A

ENABLE ,'s

TOP B

GJ ENABLE

100's

BCD 1[!Jaco 100

3

KEYWAY---;;;;;-;

~KEYWAY

:t
~
+
:~~ :~ f :~~ ::
10
BCD 4
BCD 8

BCD OUTPUT
Format

OM~41010

ANALOG AND POWER (J21-BOTTQM BOA.RD

5

ENABLE 10'S

BCD 400
BCD 800

ENABLE lK'S

BCD 10

BCD lK

BCD 80
ENABLE 10K

BCD BK

~ E.C:O':
~ DATA READY OUT
OUT ~ RUN/HOLD IN

BCD 10K

PLUS/MINUS
OVEARANGE OUT 14 -tSV IN

UNDERRANGE OUT

~

DIGITAL COMMON

E.O.C. pulse, "Data Ready" (Print Pulse), Overrange,
Underrange, Out of Range, PLUS/MINUS Polarity OUT, and
RUN/HOLD.

CALIBRATION
A multiturn screwdriver pot (rear-panel mounted) adjusts the
full scale reading (gain). Zero is automatic (autozeroing).
Suggested recalibration in stable conditions is 90 days.

POWER CONNECTIONS
+5V In (Pin B14)
Power input to the meter; connections made between +SV IN
and POWER COMMON (pins J1-A14 and B13 and J2-B14);
requires a regulated supply (±S%), capable of supplying 4S0
mA max.
I

II

DATEL. Inc. 11 Cabot Boulevard. Mansfield. MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-73

DM-4101L
4% Digit LED Panel Meter
with Data Outputs
FEATURES
• Large .56" digits
• Replaces the DM-4100L with improved driver circuit
for 20% brighter LED display
• ±5V de outputs at 15 rnA for use"s circuits
• Balanced differential Inputs with 5 pA bias currents
• Internal ratlometrlc reference for drift correction
• Autozerolng with B6dB CMR noise rejection
Standard ±1.9999V de input range; user-installed
options set other voltage or current ranges.
• BCD Outputs available to drive DM-4103 slave
displays

GENERAL DESCRIPTION
The DM-4101L replaces DATEL's older DM-4100L DPM,
offering higher performance at an even lower price. The
improved display driver circuitry gives a 20% brighter output
from the .06" high LED's. Besides offering DATEL's standard
input features, this device provides multiplexed BCD outputs.
These outputs can drive a remote display, such as the DM4103, or be used by an external microprocessor. This DPM is
housed in a short-depth case, a feature appreciated by many
OEM's.
The quality performance features of the DM-41 OOL have been
retained. CMOS circuitry provides an extremely high input
impedance (1000 Megohms), and extremely low input bias
current (5 picoamps). The meter's dual slope converter
autozeroes the input in each conversion cycle for a true zero
reading. And a reference inlout loop permits use of the DM4101 Lin ratiometric and bridge-type circuits.
Additional features include a Busy I Done Output which
indicates when an AID conversion is complete. Overscale and
Underscale outputs can be used with external circuitry for
autoranging. A RunlHold line permits a reading to be held for
several seconds while an operator copies down the reading.
And an externally-accessible Display Enable line can blank the
display to minimize power consumption, while the AID

converter and BCD outputs are running to drive an external
slave display. BCD outputs, used in conjunction with a strobe
line from the DM-41 01 L's AI D converter, can drive a remote
slave display (Model DM-4103), or provide AID data

conversion for a microprocessor.
Power to the meter is +5V dc at' 350 mA maximum. A dc-to-dc
converter in the DM-41 01 L provides a -5V dc output (at 15 mA
maximum) to power user circuitry.

Model

ORDERING INFORMATION
DM-4101L-1
Description

DM-4101 L-l

DM-4103

41/2-digit DPM with BCD
outputs (Includes one
connector)
MUX'D BCD Slave Display

ACCESSORIES
Part Number Description
58-2075010

Dual 18-pin, 0.1" centers PC
edgeboard connector

UPA-5/500

115V AC to 5V dc power adaptor
A4

POWER COM MON

DEC PT COMMON

{A16
A17

-5V POWER OUT B14
+5V POWER OUT

816

5VPOWER IN

B17

ANALOG HI IN

B3

, - - - - A5-A9

DEC PT 1.2345
DEC PT 12.345
DEC PT 123.45
DEC PT 1234.5
DEC PT 12345.

POLARITY ENABLE

ANALOG LO IN

ANALOG RETURN

B4

pos/NEG POLARITY OUT

B15
B18

DISPLAY
DISPLAY ENABLE

TEST

B5-B8
REFERENCE OUT
REFERENCE IN

,,

BCD OUT

A11-A15 DIGIT DRIVES OUT
RUNrHOLiSIN

,

A1'

BUSYIDONE OUT
OVERSCALE OUT
UNDERSCALE OUT
STROBE OUT

Simplified Block Diagram of a DM-4101L
10-74

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DM-4101L
FUNCTIONAL SPECIFICATIONS
(Typical at 25°C, 2V range unless noted)
ANALOG INPUT
Full-Scale Input ........ As specified in "FEATURES"
Range
Input Impedance ....... 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current ..... 5 pA (typical) 50 pA (maximum)
Input Overvoltage ...... ±250V dc, 175 VRMS
continuous (maximum)
±300V intermittent
(maximum)
External Reference ..•. ,+100 mV to +2V
Range
referred to Analog Return
Common-Mode ........ 86 dB typical
to Analog Return
Rejection
Common-Mode ........ Both inputs must
Voltage Range
remain within ±4V of Power
Common
Resolution ............. 100 J.N in last digit
Displayed Accuracy .... Adjustable to ±0.2%
of reading, ±2 counts
Temperature Drift . , . , .• Autozeroed ±1 count
of Zero
over 0° to +50° C
Temperature Drift ...... ±50 ppm of
of Gain
reading! °C (typical), ±100
ppm of Reading!OC (maximum)
Ramp-up Time .....•... 83.3 mS
(Integration Period)
Sampling Rate .......•• Approximately 3 conversions
per second.
DISPLAY
Number of Digits ..•..•. 4 decimal digits and most
significant "1" digit (4!12 digits)
Decimal Points •.•....•. Right-of-digit selectable
decimal pOints are included
for scale multipliers
Display Type ........... Red, light-emitting diode
(LED), self-illuminated
Display Height ........• 0.56 inches (14,2 mm)
Overscale .............. Inputs exceeding the fullscale range cause the display
to blink
Autopolarity ........... A U+" is displayed for positive
inputs, a "-" for negative inputs.
Polarity may be disabled.
Sampling Rate ......... Approximately 3 conversions
per second.
POWER REQUIREMENTS
External +5V, ±0.25V dc regulated required at 350 mA
maximum, 250 mA typical. Logic spikes must not exceed 50
mY. (+5V OUT and -5V OUT current must be added to the +5V
power requirements for total meter consumption.

Mounting Method
Refer to end of this section.
Weight
5 ounces (1 42g) approximately
ENVIRONMENTAL
Altitude
a to 15,000 feet (4900m)
Operating Temperature Range
32°F to 122°F (0° to 50°C)
Storage Temperature Range
-13°F to +185°F (-25°C to 85°C)
Relative Humidity
20% to 80% non-condensing
I/O SIGNAL FEATURES
Besides the common I/O Signals defined elsewhere, this
device also has some important 1/0 features.
Reference Output (Pin B1)
Reference Input (Pin A1)
Normally Pins Aland Bl are jumpered together. The
instrument is calibrated when a + 1.0V dc drop exists between
Pins AI (+) and A3 (-). An external reference input to Pin AI
which is biased against Pin A3 may be used by disconnecting
Pin Bl. Ratiometric drift-correcting action may then be
achieved over the reference input range of +0.1 V dc to +2.0V
dc.
-5V Power Out (Pin B14)
Up to 15 mA of -5V dc power may be taken to power external
user-supplied circuits such as Signal conditioners.
+5V Power Out (Pin B16)
is an additional + 5V power source.

INPUT/OUTPUT CONNECTIONS DM-4 10' L
BOTTOM A
TOP B
REFERENCE IN

ANALOG GND

r;-

~

REFERENCE OUT

ANALOG LO IN

AD~~L~~ ~~: ~ :~:~~~:IO~~
DEC PT 1.9999

t::!

81 lSB}

DEC PT 19.999 16

82

BCD

DEC PT 199.99
DEC PT 1999.9

84
B8 MSB

OUT

DEC PT 19999.

STROBE OUT
01 LSD
02
DRIVE
03
04
OUT
05 MSD
PWR COMMON
PWR COMMON
POLARITY ENA.BLE
DIGIT

1

~
8
9

10
11
12
13
14
15

~

I~)

(+1

NO CONNECTION

BUSY IDONE OUT
RUN/HOLD IN
UNDERSCAtE OUT
OVER SCALE OUT
-SYDC PWR OUT
DISPLAY TEST IN

+5VOC PWR OUT
17 +5VDC PWR IN

t"ie

DISPlA Y ENABLE

~

PHYSICAL
External Dimensions
Short-Depth Case 3.0"W x 2.15"0 x 1.76"H (76,2 x 54,6 x 44,7
mm)
Panel Cutout Dimensions
I.B12"H x 3.062"W (46,0 x 77,7 mm)

DATEL,lnc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

10-75

DM-4101N
4% Digit Differential Input
LED Panel Meter
FEATURES
• Improved replacement for the DM-4100N
• Improved driver circuit for 20% brighter LED display
• Balanced, high-impedance differential inputs with 5
pA bias currents
• Internal ratiometrlc reference for drift correction
• ± 5V dc outputs at 15 mA for user's circuits
• Displayed digits are .3" high
• Standard ±1.9999V dc input range; user-installed options set other voltage or current ranges.
GENERAL DESCRIPTION
The DM-4101N replaces DATEL's older DM-4100N DPM,
offering higher performance at an even lower price. Improved
display driver circuitry yields a 20% brighter output from the .3"
high LED's while requiring a maximum of 350 mA current. This
device is packaged in a low-profile case, allowing a higher
packing density on the final product's panel.
The DM-41 01 N offers such high performance features as ultrahigh impedance analog signal inputs (1000 MO, typically)
which require extremely low input bias currents (5 pA typical).
Inputs are bipolar and autozeroed.
Other features include Overrange and Underrange Outputs
which can be used in external autoranging circuits; a Hold input
which permits display of a given value indefinitely; and a
Busy /Done line which goes low at the end of a conversion
cycle. The DM-41 01 N's display may be disabled to reduce
power consumption, while keeping the AID converter cycling.
A Reference In/Out line can accept an external reference for
use in ratiometric and bridge-type applications.
Power to the meter is +5V dc@250 mA max. -5V Out@ 15 mA
is available to power user circuits.

ORDERING INFORMATION
DM-4101N -1
Description

Model
DM-41 01 N-1

4 1/2-digit panel motor
(includes one connector)

ACCESSORIES
Part Number Description
S8-2073082

Dual 1O-pin 0.1S6" centers, PC
edgeboard connector (not
included with DPM)

UPA-S/SOO

11SV AC to 5V dc power adaptor

POWER COMMON
F

o DEC PT. 1.2345

+5V POWER OUT

E

C DEC PT. 12.345

+5V POWER IN

9

B DEC PT. 12345

ANALOG HI IN

H

ANALOG LO IN

5

ANALOG RETURN

K

-SV POWER OUT

A DEC PT. 1234.5
1 DEC PT
COMMON
TEST IN
L!::=~=====~=== 10· DISPLAY
DISPLAY ENABLE IN

3 RUN/HOLD IN
REFERENCE IN/OUT

4 _ _ _ _----''<-_-...J

4

2 BUSYIDONE OUT
6 OVERSCALE OUT
7 UNDERSCALE OUT

Simplified Block Diagram of a DM-4101N

10-76

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DM-4101N
FUNCTIONAL SPECIFICATIONS
(Typical at 25°C, 2V range unless noted)
ANALOG INPUT
Full-Scale Input .•.....• Refer to "FEATURES"
Range
Ranges field-modifiable.
Input Bias Current ...... 5 pA (typical) 50pA
(maximum)
Displayed Accuracy .... Adjustable to ±0.2% of
reading. ±2 counts
Resolution ............. 100 I'V in last digit
Temperature Drift ...... Autozeroed ±1 counl
of Zero
over OOG to +50°C
Temperature Drift ...... +50 ppm of
of Gain
reading/oC typical, ±100
ppm of reading/oC maximum
Input Impedance ....... 100 Megohms, minimum;
1000 Megohms, typical
Input Overvoltage
ANALOG LO IN ........ ±5V dc maximum
continuous referred to Power
Common
ANALOG HI IN ........ ±1 OOV dc maximum
continuous or
±250V dc for 5 seconds
referred to Power Common
External Reference ..... +1 00 mV to +2V
Range
referred to Analog Return
Common Mode •..•...• 86 dB typical
to Analog Return at dc
Rejection
Common Mode ........ Both inputs must
Voltage Range
remain within ±4.0V dc of
Power Common

CALIBRATION
A multiturn screwdriver pot adjusts the full scale reading (gain).
Zero is automatic (autozeroing). Suggested recalibration is 90
days.
PHYSICAL
External Dimensions
2.53"W x 3.25"0 x 0.94"H (64,3 x 82,5 x 23,8mm)
Panel Cutout Dimensions
2.56"W x 0.97"H (65,1 x 24,mm)
Mounting Method
Refer to end of this section.
Weight
5 ounces (142g) approximately
ENVIRONMENTAL
Altitude
o to 15,000 feet (4900m)
Operating Temperture Range
+32°F to 122°F (0° to 50°C)
Storage Temperature Range
+32°F to 131°F (0° to 55°C)
Relative Humidity
20% to 80% non-condensing

INPUT/OUTPUT CONNECTIONS DM-4101N

BOTTOM
DEC PT 1999.9
DEC PT 199.99

DISPLAY
Number 01 Digits ....... Four decimal digits and most
significant "1" digit
Display Type ........... Red, light-emitting diode
(LED)
Display Height ......... 0.3 inches (7,6mm)
Overscale .............. 1nputs exceeding the full
scale range cause the display
to blink.
Autopolarity •.......... A minus sign is automatically
displayed for negative voltage
inputs and may be blanked.
Sampling Rate ......... 3 Conversions per second

TOP

r--;;;r,~~

DEC PT COM
BUSY/DONE OUT

~:~ :~ ~ ~~::: ~7 :~:~~~~~TIN
+5VDC PWR OUT

~~

ANALOG LO IN/-)

:5NVADl~::~ I~~.~ ~7 ~:~=:~~~~EO~~T
DISPLAY TEST IN
ANALOG GND

PWR COMMON

~~
~

9

~~

DISPLAY ENABLE
.SVDC PWR IN

POLARITY ENABLE

POWER REQUIREMENTS
External +5, ±0.25V dc regulated required at 250 mA typical,
350 mA maximum. Logic spikes must not exceed 50 my. +5V
OUT and -5V OUT currents must be added to the +5V IN
power requirements.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-77

DM-41 02, DM-41 03, DM-4106
4% Digit Multiplexed BCD Input
LED Slave Displays
FEATURES
• Remote slave displays for DATEL digital panel meters
• Data repeater for second operator station up to 25
feet away
• Simple 12-wlre Interface, Ideal for ribbon cable
• Operates with any 3 to 4'1. digit DPM with
multiplexed BCD data outputs

GENERAL DESCRIPTION
The slave display meters function as repeaters for decimal data
from a master data source. Data sources include DATEL's
DPM's and a variety of microprocessor peripheral interface
circuits. Depending on the model, the multiplexed BCD data is
displayed using either LED or LCD display technology. The
DM-41 02 (LED) and the DM-41 06 (LCD) are packaged in a low
profile case, while the DM-41 03 (LED) is packaged in a short
depth case. The DM-4106 may use a battery source and is
suitable for digital thermometer repeater applications.

DM-4102

Any of these slave displays may be used interchangeably
with the multiplexed BCD output DPM's by rewiring the
connector.

CIRCUIT OPERATION
To reduce the amount of wiring required to implement a slave
display, 4-wire BCD data is multiplexed using 5 digit drive
outputs which directthe BCD data to the proper digit. Using
the DM-4200, -4101 Land -41 05 master DPM's as BCD data
sources, these slave displays rely on the persistence of vision
of the human eye to store an image of the displayed digit. This
multiplexing technique is commonly used with DPM's and
DVM's. Each digit drive has the effect of sequentially turning on
its respective digit when the drive signal is high. The digit is
blanked when the drive is low.
Digits are scanned in this manner in the DM-4101 L, -4200, and
-4105 approximately 150 times per second. The BCD data is
updated with every A/D conversion which is approximately 3
times per second. For applications from other multiplexed data
sources, digits must be updated at least 30 times a second (30
scans/sec) to avoid annoying display flicker.
Full parallel input data will require a multiplexer and possibly a
storage register.
These display slaves may be connected to popular microprocessors by using peripheral interface circuits and a suitable
rotating stack (FIFO) driver program.

DM-4106

ORDERING INFORMATION
Model
DM-4102
DM-4103
DM-4106

To Order, Specify Model Number.
ACCESSORIES
Part Number Description
58-2073083
15-pin edge connector for DM-41 02 and
DM-4106 (one included with each order)
58-2075013

10-78

Description
4'h digit, LED, low-profile slave
4'h digit, LED, short-depth slave
4'h digit, LCD, low-profile slave

18-pin edge connector for DM-4103
(one included with each display)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DM-4102, DM-4103, DM-4106

MICROPROCESSOR

8255
6821
Z80-PIO
6522

}

BCD

}

DIGIT DRIVES
1-4

}

DIGIT DRIVE 5,
POLARITY
_ _ _---,

SLAVE
DISPLAY
DM-4102
DM-4103
DM-4106

PERIPHERAL
ADAPTER
BCD
SCAN
PROGRAM
IN
PROM

Microprocessor Output To Slave Display

FUNCTIONAL SPECIFICATIONS
Data Input ....•........ Multiplexed 1-2-4-8 binary
coded decimal (BCD) data
and polarity, TTL logic levels
("0" :s 0_08V, "1" 2: 20V), 1
TTL load_
Multiplex rate 30 scans/
second minimum.
Display •........•••.•. . 4Y, digits (±19999 counts),
Power Required ..•...•. +5V dc regulated, wired from
master DPM,
DM-4102 5V @ 250 mA max.
DM-4103 5V @ 350 mA max.
DM-4106 5V @ 10 mA max.
Operating Temperature. 32°F to 122°F
R~~

~o~+~oq

Storage Temperature ... -13°F to +131 of
Range
-25°C to +55°C,
Case Material '" ....... Polycarbonate Plastic.
Mounting Method ...... Refer to end of this section.
Decimal Points .... " ... Jumper-selected 1.2.3.4,5, on
rear connector.

INPUT/OUTPUT CONNECTIONS OM-4103

BOTTOM A

TOP B

NO CONNECTION

NO CONNECTION

NO CONNECTION
NO CONNECTION
DEC PT COM
DEC PT 1.9999
DEC PT 19.999
DEC PT 199.99

r'

OEC PT 1999.9
OEC PT 19999.
NO CONNECTION
DIGIT
DRIVE

INPUTS

02

03 LSD
04

OS MSD
PWR COMMON
PWR COMMON
POLARITY ENABLE

NO CONNECTION

3
4

•

•
••
7

NO CONNECTION
POLAAITY INPUT

81 Ln} BCD

B2
B4

NO CONNECTION

10 NO CONNECTION
11

NO CONNECTION

""

NO CONNECTION

,.,.,.

OVEASCALE INPUT
NO CONNEC TlON
DISPLAY TEST IN
+SVOC PWA OUT

17 +SVOC PWR IN

18 DISPLAY ENABLE

INP'UT/OUTP'UT eo. .EeTIONS DtI-4106
aOTTOM A

DEC "T ,._ •••

TO" •

~

DEC "T , •••.•

~

DEC
NO CONN£CTIO"

"'_1 .•••• I

DEC
POLAR,TT tIIIPUT
INPUT IOUTPUT CONNECTIONS DM-41

DEC PT 19.999
DEC PT 1.9999
POLARITY INPUT
NO CONNECTION
NO CONNECTION

a2

TOP B

BOTTOM A

~
2

~
~
~

DEC· PT 1999.9
DEC PT 199.99
NO CONNECTION
NO CONN~ON
DISPLAY TEST

~~ ~~::~~~:~: 7 :~ LSB} 8CD
~ 84
INPUTS
(01 LSD rt B8 MSB

NO CONNECTION

DIGIT

{D2

DRIVE

03

INPUTS

04

~
11

~

INPUTS

B8 MSB

"T , •• -,.

:~ ~~:::~~:~: ~ :~G~~:~~~~':!."

• 81 La8}

NO CO"NE C TlON
7 82
NO CONNEC TlON
NO C ONNE C T ION ~ 84
I Dl
lSO

DIGIT
DRIVE

,N,.UTS

!
i

........

~ !!.

D2
OJ

I ::

.ao

.CD
.MPUTS

I .. 'UT/OUTPUT

~ B_' '''''UT I...... CCHII
121 UNDER SCALE IllPUT

~

13 OVERBCALf IllPUT

".R CO • • O" 14 +5VDC ,. • • till
.. 0 CO .... £CT'O .. ~ +5VDC " • • OUT

DISPLAY ENABLE
DEC PT COM

NO CONNECTION

PWR c~!:~~ ~ ~;::~Cp~: I~PUT
NO CONNECTION

~
~

+SVOC PWR OUT

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-79

DM-4104
4% Digit Parallel Input
LED Slave Display
FEATURES
• Bright 0.3" high LED display
• Operates with 2'12 to 4'12 digit DPM's
• Latches BCD data in 4-bit nibbles
• Interfaces directly to a 4-, 8-, 12-, or 16-Blt data bus
or to a full parallel 18-blt data bus
• Remote flashing alarm function
• Logic powered
GENERAL DESCRIPTION
The DM-4104 slave display meter interfaces directly to a
parallel 18-bit or to a multiplexed BCD (Binary Coded Decimal)
master unit. This type of master unit includes DATEL's DPM's
and a variety of microprocessor-based systems. The DM-41 04
is packaged in a compact low-profile case.
Master digital panel meters accept a dc or slowly varying input
voltage and display that input on front panel numerical
indicators. In addition to dc voltages, DPM's can be adapted to
measure practically any physical parameter which can be
converted to electrical units. If the DPM provides parallel or
multiplexed BCD outputs, the inputs of the DM-4104 Slaved
Digital Panel Display can be electrically connected to these
outputs to display the same information shown on the master
DPM. There are several uses for slaved displays, among them
being a remote workstation situation that requ ires the same upto-the-instant information as the master unit. Other uses may
be distributed networks, such as medical monitoring stations,
industrial process control stations or linked data acquisition/
data logging systems. The DM-4104 is not dependent
exclusively on master DPM's. Any device that can convert
physical parameters into bussable BCD outputs, such as a
parallel microcomputer port, can control the DM-4104.
The DM-4104 interfaces directly to 4, 8, 12 or 16-bit data
busses or full parallel 18-bit data busses. The BCD data inputs
are latchable (enables data to be stored on electrical
command) and bussable in 4-bit NIBBLES. A display blank
may be used as a flashing alarm, blinking the display off and on

"1" OVERRANGE (10K) IN B15
POS/NEG POLARITY B14
10K'S POL HOLD/FOLLOW IN A15

using an external control. Right-of-digit selectable decimal
pOints are included as well as a minus sign. The DM-4104
doesn't accept analog inputs.
Power requirements of the DM-4104 Slaved Digital Panel
Display is an external +5, ±0.25V dc, regulated at 450 mA
typical (550 mA maximum). Power current varies rapidlyunregulated power supplies cannot be used. DATEL's UPM5/1000 Single Output Power Supply is the recommended
power supply for the DM-41 04.

Model

ORDERING INFORMATION
DM-4104
Description

DM-41 04-1

4'h Digit Slave Digital Panel
Display (includes one connector)

ACCESSORIES
Part Number

Description

58-2073083
UPM-5/1000

15-pin edge connector
Power Supply

LATCH

8K·1K BCD IN A8·A11
1K HOLD/FOLLOW IN

A12, A13
812, B13,

DECIMAL
POINT

800·100 BCD IN B8·811
100'S HOLD/FOLLOW IN 87

80·10 8CD IN A3·A6
10'S HOLD/FOLLOW IN A2
8·1 BCDIN B3·B61
1'S HOI:D/FOLLOW IN B2
DISPLAY BLAN K A14

LSD

Simplified Block Diagram of a DM-4104
10-80

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DM-4104
FUNCTIONAL SPECIFICATIONS
(Typical It 25°C, 2V rlnge unle.. noted)
Input .........••....•.. Full parallel BCD,
conflgurltlon
internally latchable in 4-bit
nybbles.
Number of Digits •...... 4 decimal digits and most
signilicant "1" digit (4% digits)
DlspllY Type ...••..•... Red, light emitting diode
(LED), self-illuminated
DlspllY Height •.•..•..• 0.3 inches (7,6mm)
Declmll Points ......... Right-ol-digit selectable
decimal pOints are selected
by rear connector pins.
Power Requirement .... External +5V, ±0.25V dc
regulated required at 450 mA
typical, 550 mA maximum.
Logic spikes must not exceed
50 mV. Power current varies
rapidly so that unregulated
supplies cannot be used.
Connector .•....••...•• Dual 15-pin, 0.100" centers,
DATEL #58-2073083 (one included with meter)

INPUT IOUTPUT CONNECTIONS OM-4 104

BOTTOM A

TOP B

P('IWER/lOGIC COMMON
10'S HOLD/FOLLOW IN
80 BCD IN
40 BCD IN
20 BCD IN

1

:t
3

r4
:.I

10 BCD IN '6
lK'S HOLD/FOLLOW IN

r-r

8K BCD IN

~

lK BCD IN
OEC.Pl.t9.999IN

~
~

*SV DC POWER IN
,'S HOLD/FOLLOW IN
8 BCD IN
4 BCD IN
2 BCD IN
1 BCD IN
100'S HOLD/FOllOW IN
800 BCD IN

:: :~~ :: ~ :~~ :~~ ::

DEC.PT.t.9999 IN
DISPLAY

iI'iiii<

IN

10K/POL HOLD/FOllOW IN

tOO BCD IN
OEC.PT.1999.9 IN

13 DEC.PT.199.99 IN

~
~

POS/NEG POL.IN
"," OVERRANGE (10K) IN.

Low-Profile ..•......... 2.53"W x 3.34'''0 x 0.94"H
eese Dimensions
(64,3 x 82,5 x 23,8mm)
Cutout Dimensions ....• 2.562"W x 0.97"H (minimum)
(65,1 x 24,6mm)
Mounting Method ...... See end of this section.
Mounting Position ...•.. See end of this section.
Welght ................ 3 ounces (15,9g)
Operltlng .•..•......... (O°C to +50°C
Temperlture Ringe
32°F to 122°F)
Storlge ................ (-25°C to +85°C
Temperlture Ringe
-13°F to 185°F)
Altitude .........••..... 0 to 15,000 leet (4900m)
Relltlve Humidity ...... 10% to 90%, non-condensing

•
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-81

DM-4105
Micro-powered LCD Panel Meter
with Data Outputs
FEATURES
•
•
•
•
•

Ultra-low power consumption
.5" high 4V. digits LCD readout
Draws only 3 mA from a SV de power source
Balanced differential Inputs with 5 pA bias currents
Autozerolng with ratlometrlc reference for drift
correction
• Right-most digit may be °C or of descriptor for 3'12
digit thermometer applications
• BCD outputs available to drive DM-410B remote slave
displays
• Standard ± 1.999V de input range; user-Installed
options set other voltage or current ranges.
GENERAL DESCRIPTION
The DM-41 05 is a 4Y, digit, LCD-type DPM that uses very little
power and produces outputs usable by other devices. The 0.5"
high numeric display is visible under ambient room light from
many feet away. Digit-serial BCD outputs are available to pass
the digitized input signal on to microcomputers, data loggers, or
printers.
The DM-4105 provides excellent electrical performance in a
compact panel-mounting package. Analog inputs have a very
high input impedances (1000 Megohm typical) with very low
bias currents of 5 pA (typical). Common Mode Rejection Ratio
(CMRR) is 86 dB. The meter is autozeroed on each conversion
cycle to minimize drift of zero. A Reference In-Out loop can be
used to correct drift in externally excited ratiometric circuits.
A variety of designed-in features makes it easy to use the DM4105 in many applications. Blank circuit pads will accept usersupplied current shunts, voltage dividers, and ohmmeter
components. Overrange and Underrange outputs can be used
to trigger external autoranging circuitry (the DM-4105 display
has Overrange and Underrange descriptors which may be set
by the user). In 3Y, digit thermometer applications, a degree
sign can be enabled on the display, while the right-most digit
(LSD) can be solder-gap programmed as "C" for Celsius
readings or "F" for Fahrenheit readings.

The DM-4105 is powered from +5V dc at 3 mA typical (5 mA
maximum.). It may be powered using 4 "AA" alkaline cells. A
-5V output (at up to 15 mA output) is provided to power external
circuits. The meter's low-profile polycarbonate case is 2.53"W
x 3.25"D x 0.94"H (64,3 x 82,5 x 23,8mm).

ORDERING INFORMATION
DM-410S -1
Description

Model
DM-4105-1

4 1/2-digit micro-powered DPM
with data output (one
connector included)

ACCESSORIES
Part Number

Description

58-2073083

15-pin edge connector

UPA-5/500
DM-4106

115V AC to 5V dc power adaptor
Low-profile slave display

I

POWER COMMON

A14

o

,.........---..~--_---...,_

I

+5V

..--_ _ _ _.......;' A2

DEC PT 1.2345

-5V POWER OUT
DEC PT 12.345
+5V POWER OUT
DEC PT 123.45
+5V POWER IN

DEC PT 1234.5

ANALOG HI IN

BACKPLANE OUT
B10

ANALOG RETURN

BACKPLANE OUT

.....----=~---

ANALOG LO IN

B5

DEGREE DESCRIPTOR

L.._ _ _ _ _ _ _+..:......_________ 86 B9
L..-----------.......f:....::..------__ A9

REFERENCE IN OUT

L - - - - -_________~:-..-----___-

HOLD 4

6 }-_ _ _ _ _ _ _--,

DECIMAL POINT
SELECT

xx.xx(x)

:5
Il.

xxx.x(x)

~

a

xxxx.(x)

I
INTEGRATOR
AND
AID CONVERTER

I
I DECODER
I DRIVER

I

ANALOG LO IN

I

L-----:J~-.--_I

POLARITY
ENABLE

POLARITY OUT

DISPLAY TEST 2
REFERENCE INI OUT

L-____~3~---_T----~N

UNDERRANGE3
OVERRANGE3
BUSY/DONE 3

DIGITAL
GROUND

Er-----------------,

+5VdcOUT

POWER
CONVERTER

TES'r
3

POWER IN {15

®--

NOTE 5

NOTES:
1. The BLANK input is available only for models DM-9200 and DM9215.
2. For Models DM-9200 and DM-9215 this pin is called DISPLAY

4.
5.

~

The UNDERRANGE, OVERRANGE and BUSY outputS are available only for 4% digit DPM's.
For 4';' digit DPM's, this pin is called RUN/HOLD.
Refer to Table 1 for power supply connections.

®+Figure 1. Simplified Block Diagram
Table 1. Power Supply Connections

~

NUMBER
INPUT
VOLTAGE

5Vdc

15

13

0----11

10-90

NOTE

1

0--0--0

240VAC
100VAC

0

P

~

115 VAC
220VAC

S

0

~
(0

0

The OM-gOOD Series DPM's uses pins P, 13, 15, and S for
power connections. Use of these pins is different for dc and
AC models. AC models use different combinations of these
pins for different power inputs. It is therefore important to
check the information presented here for correct power applications.

Note 1: Pin S Is POWER COMMON lor de models.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DM·9000 SERIES
FUNCTIONAL SPECIFICATIONS
(Typical @ 25°C, 2V range unless noted)
ANALOG INPUT
Full Scale Input ........ Referto "FEATURES"
Range ................. Ranges field-modifiable
Input Impedence ....... 100 Megohms (minimum)
Input Bias Current ...... S pA (typical)
SO pA (maximum)
Input Overvoltage
±100V dc
ANALOG LO IN}
ANALOG HI IN ....... continuous. referenced to
POWER COMMON.
±2S0V dc (S seconds
maximum) referenced to
POWER COMMON.
External Ref. Range .... + 100 mV to + 2V dc
referenced to ANALOG
RETURN.
Common-Mode ........ 80 dB (typical from
Rejection
dc to 60 Hz, with a 1 Kilohm
unbalanced input
Common-Mode ........ Both the inputs must
Voltage Range
remain within O.SV dc below
the + SV dc supply and 1.0V
dc above the -SV dc supply
Resolution ............. 1 mV, 3Y, digit DPM's
100 /lV, 4Y, digit DPM's
Accuracy .............. Adjustable to ±0.02% of
reading (maximum), ±2
counts
Temperature Drift ...... Autozeroed ±1 count
of Zero
over a 0 to +SO°C
temperature range
Temperature Drift ...... ±SO ppm of
of Gain
reading/oC (typical)
±100 ppm of reading/oC
(maximum)
Warm-Up Time ......... S minutes (typical)

3V2 digit
DPM's

4V. digit

Sampling Time (nominal)

83.3 ms

74 ms

Conversion Time (nominal)

333 ms

296 ms

DPM's

DISPLAY SPECIFICATIONS
Number of Digits ...... . 3Y, and 4Y, digits
Decimal Points ......... Selectable
Display Type ........... LED (Red, high efficiency)
LCD (Liquid crystal with high
contrast ratio, high
temperature fluid)
Display Height .....•... LED 0.S6" (14,22 mm)
LCD 0.5" (12,70 mm)
Auto Polarity ........... A "+" sign is automatically
displayed for positive inputs
and a "-" sign is for negative
inputs. The user may blank
the polarity using solder gap
options.

Over Scale ............. The display indicates inputs
exceeding the full-scale
range. Refer to the table
below.

Overscale Display

Model Number
DM-91 00, DM-9115,
DM-9150, DM-9165

Blanks the display leaving a
"1" MSD and sign,

DM-9200,9215

Blanks"I" MSD and
displays all other digits as
zeroes and flashes.

DM-9250, DM-9265

Blanks "1" MSD, displays all
other digits as zeros and
flashes error sign (A. in the
top left comer).

POWER CONSIDERATIONS
Power Consumption with no external load
MODEL
DM-9100
DM-9115
DM-9150
DM-9165
DM-9200
DM-9215
DM-9250
DM-9265

Typical
0.9 W
2.6W
0.02W
0.9W
0.9W
2.6W
0.02W
0.9W

Maximum
1.IW
3.2W
0.025W
1.IW
1.IW
3.2W
0.025W
1.1W

Power output for AC models: +SV dc @ 100mA (maximum)
Power output for dc models: Limited by user's dc source
CALIBRATION
A screwdriver pot allows adjusting the full scale reading (gain).
Zero-is automatic (autozeroing). Suggested recalibration period
under normal operating conditions is 90 days.
PHYSICAL-ENVIRONMENTAL
External Dimensions
3.6"W x 3.S7"0 x 1.67"H (91,44 mm x 90,68 mm x 42,42 mm)
Panel Cutout Dimensions
NEMA Standard: 3.924" x 1.682" (99,67 mm x 42,72 mm) DIN
Standard: 3.622" x 1.772" (92 mm x 4S mm)
Weight
AC models: 11 Ounces (311,8 grlims) dc models: 6 Ounces
(170,1 grams)
Altitude
o to IS,OOO feet (4900 m)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-91

II

DM·9000 SERIES
TEMPERATURE RANGES
Operating
0° to 50° Celsius
Storage
-25° to +85° Celsius
Relative Humidity
10% to 90%, non-condensing (for LED models) 0 to 90% (noncondensing) from -25° to +35°C derated linearly to 25% at
+50°C (for LCD models)

INTERNAL GROUNDING CONNECTIONS:
The internal connections for ANALOG RETURN (Pin D),
DIGITAL GROUND (Pin E) and POWER COMMON (Pin S)
differ based on the DPM model. For 3Y, digit DPM's DIGITAL
GROUND and POWER COMMON are internally connected.
For 4Y, digit DPM's ANALOG RETURN, DIGITAL GROUND
and POWER COMMON are internally connected. Depending
on the application and input configuration, the user may have to
make the grounding connections. POWER COMMON is
internal for AC models and is not user accessible.

PIN DETAILS
Figure 2 shows the pin connections for the different models in
the DM-9000 Series.
TOP
ANALOG HI IN (+)
ANALOG LO IN (-I

I"

NO CONNECTION
REF,INIOUT

2.

•

1
•

C
0

KEY.AY - - _

BOTTOM

TOP

NO CONNECTION

ANALOG HI IN

2.

8

NO CONNECTION

NO CONNECTION
ANALOGi RETURN

NO CONNECTION 3
REF IN lOUT •
"E'fW ...., - _ _

C
0

NO CONNECTION
ANAlOO RETURN
_ _ _ K(YWA'f

·5VDC OUT I E DIGITAL GiNO
HDlP 6 F NO CONNECTION
NO CONNECTION 7 H NO CONNECTION
POLARITV OUT

8

,J

DISPLAY TEST.

I(

DEC PT

.. DEC. PT 188_8
N NO ETCH
P

NO CONNfCflON

1~

PI

NO ETCH

NO ETCH

IN 15 S

POLA!"ITY OUT 8
KE'fW"''f - - _

_ _ K('I'WA'"

NO CDNNECflON

NO CONNECTION 13
+SVOC PWA

• SVOC OUT I E DIGITAL GNO
HOLD 6 , NO CONNECTION
NO CONNECTION 1 lot NO CONNECTION

NO CONNECTION
_

I.e,. 10 L DEC. PT 18.'

DEC PT 1 •. "
tt
NO ETCH t2

POWER COMMON

DISPLAY
DEC PT
DEC PT
NO
AC LINE (2201240

NO CONNECTION
_ _ _ KEYWAY

NO ETCH '4
AC LINE (100/220 VAC) 15

NO CONNECTION
OEC PT I 1i189
DEC, PT lIfe,e
NO ETCH
AC LINE (10011171120 VAC)

A NO ETCH
S AC UNE (11111201240 VAC)

DM·9115

(.)11.

... NALOG HI IN
...NALOG La IN (-) 2
NO CONNECTION 3
REF,IN/OUT 4
KEYWAY - - _

J

9 K
10 L
18.89 11 III
ETCH 12 N
VAC) 13 P
TEST

f .888

DM·91 00
TO>

80TTOM

NO CONNECTION

ANALOG LO IN (-I

_ K E Y W ... .,

KEYWAY _

'+'1"

NO CONNECTION

BOTTOM

BOTTO..

NO CONNECTION
NO CONNECTION
NO CONNECTION
0 ANAl.OG RETURN
_ _ _ KEYWAY

ANALOG HI IN ,+) I I . NO CONNECTION
ANALOG LO IN (-) 2 a NO CONNECTION
NO CONNECTION l
C NO CONNECTION
REF IN lOUT 4 0 ANALOO RETURN
KEYWAY - - _
_ _ _ KEYWAY

.svoc.oUTIE OIOITAL aND
HOLD Ii f NO CONNECTION
NO CONNEctiON 1 H NO CONNECTION
NO CONNECTION 8
J NO CONNECTION
KEYWAY--_
_ _ _ KEYWAV

• 5VDC OUT I E DIGITAL ONO
HOLD 6 F NO CONNECTION
1 H NO CONNECTION
NO CONNECTION 8 J NO CONNECTION
KEYWAY - - _
---KEYW"'Y
DISPLAY TEST 9 K NO CONNECTION

•
C

K
l.
..
N

NO CONNECTlC."
DEC. PT. 1981i1
DEC PT, 188.9
NO ETCH

NO CONNECTION 13 P
NO ETCH , . R

NO CONNECTION
NO ETCH'

• SVOC PWR IN 15 S

POWER COMMON

DISPLAY
DEC PT;.
DEC PT.
NO

TEST.
1.889 10
'IiI.88 11
ETCH 12

,,",0 CONNECTION

DEC PT '889 10 L otc PT 1999
DEC PT 19,99 11 III DEC Pl" 1999
NO ETCH 12 N NO ETCH
"'C LINE 12201240 VAC) 13 P

AC UNE (100/1171120 VAC)

fI
S

NO ETCH
AC liNE (1171120/240 VAC)

NO ETCH 14
... C LINE 1100/220 VAe) 15

DM·9165

DM·9150
TOP

BOTTOM

N~~l::N~~~~~~

!

~ :~.~~:::~;:~:

REF IN/OUT

..

0

KEYW"Y - - _

ANALOO RETURN
_ - - KEYW ... Y

.. SVDC OUT I E DIOIT AL OND
RUN/H""O'CD Ii f NO CONNECTION

.. SVOC OU'T I E OIOITAL ONO
RUN/HOLD 8 , NO CONNECTION
BLANK
POLARITY OUT
KEYWIIoY _

1
8

BLANK 1
POLARITY
KEYWAY - - _

H UNDERRANQE
J OVERAANG£
_

"0 CONNt.CTION 13 P NO CONNECTION
NO fTCH 14 PI
.SVOC PWR IN 15 5

our a

_ _ KEYW"Y

OISPLAY TEST 8 II. BUSV/lrn"Nl
OEC PT 1.8'"
10 l DEC. PT. 1999.g
DEC PT 19,9"
11 .. DEC. PT. 199 gg
NO ETCH 12 N NO ETeH
NO ETCH
POWER COMMON

aOTTOM

... NALOG "liN (+, I A NO CONNECTION
ANUOG LO IN (-I % • NO CONNECTION
NO CONNECTION :3 C NO CONNECTION
REF.IN/OUT .. 0 AN ... LOO RETURN
KEYWAY - - _
_ _ _ KEYW"'Y

"N ... LOG "liN ( + I I A NO CONNEC TlON

~

,

'0

DEC. PT. 1 .••• 8
DEC PT. 19 .••• 11
NO IETCH 12
AC LINE (2201240 VAC) 13

H

J
_
K

UNOERRANOE
OVERRANGE
KEYW",Y
BUSY/56ii"E

L DEC. PT 1819.9
M DEC. PT. 199,IUI
N NO ETCH
P AC LINE (10011111120 VAC)

NO ETCH , .. PI NO ETCH
... C LINE 1100/220 VAC) ISSAC UNE (11711201240 V ... C)

DM·9200

DM·9215
TOP

4N ... lOG HI IN I . I I A NO CONNECTION
"N"LOG lO IN (-, % B NO CONNECTION
NO CONNECTION 3 C NO CONNECTION
REF INIOUT '"
K'I'VW"''f _ _ _

0

NO CONNECTION 3
REF IN/OUT '"
"-EYWAY - - _

ANALOO RETURN
_ _ _ KEYW.'

.. SVOC OUT I E DIGITAL GNO
RUN IHOlD 6 F NO CONNECTION
,,",0 CONNECTION
NO CONNECTION

,
e

H
J

"'0 CONNECTION

13~~0

14m~OETCH

DM·9250

10·92

1

NO CONNECTION a
KfYW"'Y - - _

H UNDERAANOE

J

NO CONNECTION 9 K
DEC. PT, 1 .••• 8 10 L

PT 19999 10 L DEC PT IIU9 II
PT 19998 11 M DEC PT IIU 911
NO ETCH 1% N NO ETCH

NO CONNECTION
CONNECTION
NOETe"
.. svOC PWR IN 15t!:j POWER COMMON

C "0 CONNECTiON
0 ANALOO RE TURN
_ _ _ KEYW"'Y

• 5VOC OUT I E OIOITAL ONO
flUN/HOtO 6/ F NO CONNECTION

UNOERRANOE
OVERR"'NG£

KEYW"'Y--_
~_--KEYW"'~
NO CONNECTION 9 I( BUSV/6"QiiE
DEC
DEC

10TTOM

"NALOO HI IN I . I I A NO CONNECtiON
AN ... tOG La IN (-I 2 I NO CONNECTION

DEC

BUSY/6(5"iiE
OEC, PT, 1919 9

PT 19.998 "
.. DEC PT 19999
NO fTCH 12 N NO fTCN

AC lINE (2201240 VAC) 13 P
NO ETCH , . PI
LINE (100/220 VAC) IS S

,.,~

OVERRANOE
_ _ _ KEYWAY

AC LINE (10011171120 VAel
NO ETC"
AC LINE (11711201240 V",CI

DM·9265

Figure 2. Pin Details of DM·9000 Series DPM's
DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DM-9000 SERIES
Table 2 lists the voltage and current levels on the DM-9000
Series DPM's input! output pins.

Table 2. Logic Levels for Input/Output Pins
Model
Number

Pin
Number

9100
9115

6

8

9150
9165

6

9200
9215
9250
9265

6

K
8
H
J

9200
9215

7

PIN# SIGNAL
1

ANALOG HI IN ~

2 ANALOG LO IN \

4

REF IN/OUT

Pin

Parameter

Minimum

Typical

Maximum

VIL
VIH

--

--

1.5

3.5

--

--

Volts
Volts

Positive
Inputs

2.5

--

--

Volts

Negative
Inputs

--

--

0.5

Volts

VIL

--

1.5

Volts

VIH

3.5

---

--

Volts

VIH

2.8

2.2

--

Volts

VIL

--

1.6

0.8

Volts

IlL (@V= OV)

--

0.02

0.1

IIH (@V=5V)

--

0.1

10

milliamperes
milliamperes

VOL (@I = 1.6mA)

--

0.25

0.4

Volts

VOH (@I = -1 mAl

2.4

4.2

--

Volts

VoH(@1 = -10p.A)

4.9

4.99

--

Volts

VIL

--

--

0.8

Volts

HOLD IN

POLARITY OUT

HOLD IN

RUN/HOLD IN

BUSY/DONE
POLARITY OUT
OVER RANGE OUT
UNDERRANGE OUT

BLANK IN

DESCRIPTION
Differential input voltages connect to these inputs. A bias
current path to POWER
COMMON (if+ 5V dc powered)
or ANALOG RETURN from both
these inputs must be externally
provided. External circuits must
restrict these inputs to be within the common-mode voltage
range.
The instrument is calibrated
when a + 1.0V dc drop exists
between this pin and ANALOG
RETURN' (Pin D). The DPM's
are provided with a solder gap
option to allow an external
ratiometric reference. The
external source must be
biased against ANALOG
RETURN (Pin D).

PIN#

SIGNAL

Units

DESCRIPTION

5

+ 5V dcOUT

This pin delivers + 5V dc
(@ 100mA maximum for AC
models) for user circuits. The dc
model output is limited to the
user's dc source limit.

6

RUN/HOLD IN
(low = HOLD)

For models DM-9200, DM-9215,
DM-9250, and DM-9265 a TTL
high (or open) on this pin
enables continuous sampling. A
TTL low (or ground) will hold
and display the last sample for
temporary single sample storage. For models DM-91 00, DM9115, DM-9150, and DM-9165
a TTL low (or open) on this pin
enables continuous sampling. A
TTL high holds the display.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-93

I

II

DM-9000 SERIES
PIN#

SIGNAL

DESCRIPTION

7

BLANK IN
(active low)

This pin's function is available
only on models DM-9200 and
DM-921S. A TIL low (or ground)
on this pin blanks the display,
excluding the selected decimal
points and the polarity sign.
Data remains valid even with
the display blanked.

8

POLARITY OUT

This pin goes low when the
DPM receives a negative input
signal. It is valid even for a zero
reading. A display of +0000
means the signal is positive but
less than the least significant
digit.

9

Connect the selected decimal
point to Pin E, Digital Ground.

SIGNAL

DESCRIPTION

D

ANALOG RETURN This pin may be used as a
IN
reference for some floating
inputs. If not possible, inputs
may be referenced to POWER
COMMON (if+ SV dc powered).
ANALOG RETURN is approximately - 2.8V below + Vs and
can sink 30 mA to - Vs.

H

UNDERRANGE
OUT (active high)

J

OVERRANGE OUT This pin is high if the previous
(active high)
input signal exceeds the A/D
converter range of + 19999
counts. Thepin remains high
until the beginning of reference integration in the next
measurement cycle.
UNDERRANGE and OVERRANGE are normally used as
up/down ranging gain selection
controls for an auto-ranging
input selection.

K

BUSY/DONE OUT This pin goes high during AID
(low=DONE).
conversions. The pin remains
high until the conversion is
complete or until the end of a
measurement in the case of an
OVERRANGE. The pin may be
used to prevent the input voltage from changing during conversions.

DISPLAY TEST IN To test the display, apply + SV
dc to this pin for models DM9100, DM-911S, DM-91 SO, and
DM-916S or ground this pin for
models DM-9200 and D M-921S.
The display will read 1.888(8).
This pin is not available in
models DM-92S0 and DM-926S.

10 DECIMAL POINT
SELECT
(active low) x.xxx(x)
11 DECIMAL POINT
SELECT
(active low) xx.xx(x)
M DECIMAL POINT
SELECT
(active low) XXx.x(x)
L DECIMAL POINT
SELECT
(active low) XXXx.(x)

10-94

PIN#

This pin goes high if the previous input displays + 1800
counts or less. The pin remains
high until the beginning of signal integration in the next
measurement cycle.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (S08) 339-30001TLX 174388/FAX (S08) 339-6356

DM-LX3
Single Board, 3% Digit
LCD Panel Meter
FEATURES
• Compact, single board design
• 3'12 digit LCD display
• Balanced high-impedance differential inputs
•
•
•
•
•
•

SOdB CMRR
Low power consumption
Fits easily into most panel cutouts
Autozeroing capability
Ratiometer reference for drift correction
Standard ± 1.999V dc input range; user-installed
options set other voltage or current ranges.

GENERAL DESCRIPTION
The DM-LX3 is a compact, uncased, single board digital panel
meter (DPM). The DPM displays a range of input voltages and
currents on a 0.75" LCD display. The DM-LX3 operates on logic
power (+5V dc) or 4 "AA" alkal.ine batteries.
Despite its small size and low cost, the DM-LX3 offers very
high instrument performance. CMOS circuitry provides 1000
Megohm input impedance and 5 picoamp input bias current;
the meter will not "load down" sensitive input signals. Analog
inputs to the meter are balanced differential, and offer 80 dB
Common Mode Rejection. Overvoltages to ±250V dc (175
VRMS) are handled without damage.
A significant feature is an externally-accessible Reference I nOut loop which sets the meter's gain. This permits the DM -LX3
to be used in ratiometric applications such as a digital
ohmmeter. Here, an external reference voltage, derived from a
bridge-type input circuit, causes the meter's gain to
compensate for voltage drift in. the bridge excitation source.
Other circuit features include autopolarity, a display hold
circuit, and a selectable display test. Autozeroing holds the
meter's zero drift to ±1 count maximum over the DoC to 50°C
operating range. Temperature drift of gain is typically within
±50 ppm of reading/oC. The meter's on-board dc-to-dc
converter can also be used to supply -5V out at 20 mA
maximum to power user-supplied signal conditioning
components.

ORDERING INFORMATION
DM-LX3-1
Model
DM-LX3-1

Description
31/2 Digit single board DPM
with Liquid Crystal Display
(includes one P1
connector)
ACCESSORIES
Part Number Description
39-2106705
P1 connector for J1 jack; 14-pin
DIP connector and cover
UPA-5/500
115VACin, +5Vdc(@500mA)
out, power adaptor

...-------------~>---- 8 DISPLAY TEST

REFERENCE OUT

5

-_o---+-.-__

ANALOG RETURN

3

------+-+-------'--+---'--'

ANALOG HIIN

2 ----r-'WWr..-l

.ANALOG LO IN

1 ----L-j

REFERENCE IN

4 ____

~~

...----+-"----_ _-+-9·11

DEC PI SELECT

12 POL ENABLE

t-----~::;;;;~~--t-.

-+-------.J

7 POWER COMMON

1 - - - 1 . - 1 4 +5V de

HOLD 6-----+-------~

L------------~~~~~~~----===~==~----13

-5WeOUT

Simplified Block Diagram of a DM-LX3

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-95

DM-LX3
FUNCTIONAL SPECIFICATIONS
(Typical at 25° C, 2V range unless noted)
ANALOG INPUT
Full-Scale Input . ....... Refer to "FEATURES"
Range
Ranges field~modifiable.
Input Impedance . ...... 100 Megohms (minimum)
1000 Megohms (typical)
Input Bias Current ...... 5 pA (typical) 50 pA
(maximum)
Input Overvoltage ...... ±250V dc, 175V RMS
continuous (maximum)
±300V intermittent
(maximum)
External Reference . .... ±1 00 mV to ±2V
Range
referred to - Vs
Common-Mode ........ 80 dB (typical),
Rejection
from dc to 60 Hz, with a 1
Kilohm unbalanced input
Common-Mode ........ Both the inputs must
Voltage Range
remain within 0.5V dc below
the +5V dc supply and 1.0V
dc above the -5V dc supply.
Resolution . ............ 1 mV
Display Accuracy ...... . Adjustable to ±0.1% of
reading, ±1 count
Temperature Drift . ..... Autozeroed ±1 count
of Zero
over a 0° to +50°C
temperature range
Temperature Drift . ..... ±50 ppm of
of Gain
reading/oC (typical) ±100
ppm of reading/oC
(maximum)
Sampling Time ........ . 83.3 mS (nominal)
Sampling Rate ......... 3 conversions per second.
DISPLAY
Number of Digits . ...... 3 decimal digits and most
significant "1" digit (3Y2 digits)
Decimal Points . ........ Selectable using decimal
point select signal lines.
Display Type . .......... LCO
Display Height . ........ 0.75" (19mm)
Overscale . ............. The inputs exceeding the fullscale range display "+1 "
MSO with zeroes blanked.
Underscale ............ The inputs below the 1800
counts display "-1" MSO with
zeroes blanked.
Autopolarity ........... A "+" sign is automatically
displayed for positive inputs
and a "-" sign for negative
inputs. The user may blank
the polarity using the
POLARITY ENABLE line.

10-96

CALIBRATION
A multiturn screwdriver pot adjusts the full scale reading (gain).
Zero is automatic (autozeroing). Suggested recalibration is 90
days.
PHYSICAL
External Dimensions
4.0"W x 2.0"H x 0.56"0 (102 x 51 x 14 mm)
Panel Cutout Dimensions
2.88" x 1.13" (72 x 29 mm) (Requires a 0.125" (3,2 mm)
diarneter hole for gain adjust pot)
Weight
1.8 ounces (52g)

ENVIRONMENTAL
Altitude
o to 15,000 feet (4900m)
Operating Temperature Range
+32°F to 122°F (0° to 50°C)
Storage Temperature Range
+32°F to +131 of (O°C to 55°C)
Relative Humidity
20% to 80% non-condensing

I/O SIGNAL FEATURES
Besides the common 1/0 Signals defined elsewhere. this
device also has some important I/O features:
-5V dc OUT (Pin 13)
A voltage output may be used from the internal dc-to-dc
converter to power user-supplied external circuitry.
POWER CONSUMPTION
+5V dc POWER IN
+5V dc (3.5 to 7.0V dc) at 3.5mA nominal. May be supplied
from four "AA" alkaline batteries in series. or a regulated
(+/-5%) power supply (DATEL UPA-5/500).
dc POWER OUT
-5V dc (-3.5V to -7.0V dc, depending on input) @ 20 rnA
maximum.
Any current taken at -5V dc out must be added to +5V power to
yield total meter power.

DATEL. Inc. 11 Cabot Boulevard. Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

CASE MOUNTING CONFIGURATIONS

DIGITAL PANEL METER
CASE MOUNTING CONFIGURATIONS
DATEL DPM cases are designed to meet different industry-standard specifications. Table 6-1 shows the different case
dimensions and the DPM models. A user may select a DPM depending on the front panel requirements: low profile, short
depth, DIN, or NEMA dimensions. Some DPM models also meet NEMA vibration specifications. Figures 6-1 through 6-4
show different DPM case dimensions and panel installation methods.

Table 10-1:

DPM Case Dimensions

Dimensions
WxDxH

DPM Model
Number

low-Profile

2.53" x 3.34" x 0.94"
(64,3 x 84,8 x 23,8 mm)

DM-3100N
DM-3100U1
DM-3100U2
DM-3100U3
DM-3102
DM-4100D
DM-41 01 D
DM-41 01 N
DM-4102
DM-4104
DM-4105
DM-4106
DBM-20

Short-Depth

3.00" x 2.15" x 1.76"
(76,2 x 54,6 x 44,7 mm)

DM-3100B
DM-3100l
DM-3100X
DM-41 01 l
DM-4103
PC-6
DM-500

Case Type

1.89 x 1.4 x 0.94
(48 x 34,3 x 24)
DIN/NEMA

3.6" x 3.57" x 1.67"
(91,44 x 90,68 x 42,42 mm)

DM-9100
DM-9115
DM-9150
DM-9165
DM-9200
DM-9215
DM-9250
DM-9265

Uncased

4.0" x 2.0" x 0.56"
(102 x 51 x 14 mm)
3.5" x 2.0" x OS
(88,9 x 50,8 x 12,7 mm)

DM-lX-3
DM-31

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

10-97

CASE MOUNTING CONFIGURATIONS

Inches (MM)

SINGLE MOUNTING CUT OUT

/

REMOVABLE
PANEL MOUNTING
HARDWARE ~

I

USER'S
FRONT PANEL

--------~---

.-----------~====:::::;!?

3.340
185\

1T

PANEL THICKNESS

.062 TOO.625
11.61 TO(15,91

0.157(4)

I+,",nnl
CICIO

I

2.92
---(74.2)

Figure 10-1a:

---------1-1

Mechanical and Panel Cutout Dimensions
for a Low-Profile DPM Case

USER'S fRONT PANEL

WITH CUT OUT

~

BRACKET SLOTS
(2 PAIRS)

tS;2~/~
/
INSERT BRACKETS
AND ROTATE FORWARD

Figure 10-1b:

10-98

/

~

"L" FLANG'
SEATING BRACKETS
11 PAIR) AND SCREWS

Panel Installation of a Low-Profile
DPM Case

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

CASE MOUNTING CONFIGURATIONS

PC BRD CONNECTOR

"'~ O~O~8IMAX

/
DRILL CLEARANCE OR
DRILL & TAP FOR
4-40 SCREW (METRIC M31

CUT OUT

TOP VIEW

I"-

/
FRONT
VIEW

/

2.120
{53.B)

"I~

IJ..---(95.1)~
3745

Figure 10-2a:

Mechanical and Panel Cutout Dimensions
of a Short-Depth DPM Case

CUSTOMER MAY DRILL
CLEARANCE OR DRILL
& TAP FOR 4-40
SCREW IMETRIC M31

-------------

BEZEL & FILTER SNAPS ON
AFTER INSTALLING UNIT

Figure 10-2b:

Panel Installations of a Short-Depth
DPM Case

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

10-99

CASE MOUNTING CONFIGURATIONS
PLASTIC POSITIONING PINS
REAR VIEW
(clips removed)
1

SIDE VIEW
TOP

I

T

1.67 (40.42)

1.90 (48.26)

BonOM

, 1

f-lol---------------------i>lIO,
4.300(10.9.22)

f-Iol-------- BonOM _ _ _ _ _ _
10

_I

3.57(90.68)
3.758(95.45)

RETAINERS

~.I 1

"I

3.60(91.44)

+ 0.024
1.772 - 000.0
45mm + 0.61

1.682 + 0..02
- 0..00
42.72mm + 0

- 0.0.0.

-00

3.622 + 0.032

3.924 + 0.032

- noaa

- 0..0.00.

92mm + 0.81

99.67mm + 0.81

- 0.00

- 0.00.
NEMACUTOUT

DIN CUTOUT

Note" The OM-9000 Series QPM Case is designed to fit into industry standard DIN or NEMA
size panel cutouts. Remove the plastic poSitioning pins 1, 2, 3and 410fitthe aPM into
NEMA size panel cutout. or, pins 5, 6, 7, and 8 to fit the DPM into a Din size panel
cutout.

Figure 10-3a:

Mechanical and Panel Cutout Dimensions
of a DIN/NEMA DPM Case

USERS FRONT PANEL
WITH CUTOUT (DIN or NEMA)

PANEL
r

DPM INSTALLED
IN A PANEL

~

Figure 10-3b:

10-100

SCREWS

Panel Installation of a DIN/NEMA
DPM Case

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

CASE MOUNTING CONFIGURATIONS

-1.I

41

2.882"

/ + - - - - - - (73,0)

-------l-

(11)

.062
(1,6)

-4rr.--_ _ _ _ _ _ _ _---,-,

~----------------------~

i

.£1 CI CI CI ! ~­
; •1.1_1.1_1.1_1 !
j

1.132
(29)

L _____________________

~

.44
(11,2)

REAR
BOARDTi
ETCH AND

~~p~~~~T08

1-0.-------- (~g~) _ _ _ _-+ ___----1

NOTES:
1. USE.,." x Yo" LG STAND-OFFS (NOT SUPPLIED WITH METER)
TO REAR MOUNT DM-LX3.
2. THESE ARE NOT OUTLINE DIMENSIONS FOR THE DISPLAY
THEY ARE PANEL CUTOUT DiMENSIONS USED WHEN
REAR MOUNTING THE METER.

Figure 10-4a:

OPTIONAL
DIP PLUG

(.020' pins)

DM-LX3 Mechanical Dimensions

OPTIONAL
USER-FABRICATED
@)CLEAR PLEXIGLASS
(2" x 4" x 'f,. THK.)
USER'S PANEL
.040 to .125 THK

(H03,1)

®
2.00

(4) STAND-OFF
'I. x '12 LG
4-40 THREAD

CD

DM-LX3

1. 1
(43,4)

2.88
(73.0)
3.70
(94,0)

.144 DIA (A)
4 HOLES

USER'S
PANEL

J

NOTES
STAND·OFFS AND HARDWARE SUPPLIED BY USER.

CD
® PANEL THICKNESS OF ABOUT 'I." MAY REQUIRE 4·40 x r" LG. SCREWS FROM THE

L
.64
(16,3)

TOTAL DEPTH
BEHIND PANEL

FRONT.

@) A CLEAR FILTER IS RECOMMENDED TO PROTECT THE DM·LX3 DISPLAY. IF USED,
INCREASE LENGTH OF FRONT SCREWS BY Y,,"

Figure 10-4b:

DM-LX3 Panel Mounting

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-101

CASE MOUNTING CONFIGURATIONS
1+-_ _ _ _ _ _ _ _ _ 3.500 - - - - - - - - - - - - - 1

.315
18)

(88,9)

''"~"''~ I"

2.735
(69,5)-----+-----1

4 PLACES 12,9)

+

III Ol~1
f 1./:1 l_l./J

1.840
146,7)

1.370
134,8)
OPTIONAL
/DIPPLUG

fUll SCALE
GAIN
ADJUST

~

2.000

,--+1-------- f6~~~--------I

REAR BOARD ETCH
AND PIN HEIGHT
APPROX. 0.1 0 12.5)

T

TOLERANCE .XX -; ± 0,01"

XXX

Figure 10-5a:

~ t

0.005"

DM-31 Mechanical Dimensions

(8) 4-40x%

~
,~

LG (OPTIONAL)

3503~

(88,9)

-

156

{r

USER'S
PANEL

.040-.125 THK
(1103,1)

2.00

\j

(4) STANO-OFF

V.xY2 lG
(OP.TIONAL)

3.187
(80,95)

Figure 10-5b:
10-102

.144 DIA (A)
4 HOLES

DM-31 Panel Mounting with Optional
Bezel/Filter

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

CASE MOUNTING CONFIGURATIONS

MECHANICAL DIMENSIONS

INCHES (mm)

01

F

0: 0.20 (5)
E: 1.22 (31)
F: 0.47 (12)

A: 0.94 (24)
B: 0.31 (8.0)
C: 1.89 (48)

Figure 10-6a:

E

DM-SOO Mechanical Dimensions

PANEL CUTOUT DIMENSIONS

INCHES

A: 1.80{+0.01, -0)

mm
45.7{+0.3, -0)

B: 0.89 (+0.01, -0)

22.7 {+0.3, -0)

Figure 10-6b:

DM-SOO Panel Mounting

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

10-103

FUNCTIONAL PINOUT DESCRIPTION
ANALOG HI IN
ANALOG LO IN

Differential input voltages connect to these inputs. A bias current path to POWER
COMMON or ANALOG RETURN from both these inputs must be externally provided.
External circuits must restrict these inputs to be within the common-mode voltage
range.

ANALOG RETURN IN

This signal line may be used as a reference for some floating inputs. If not possible,
inputs may be referenced to POWER COMMON. ANALOG RETURN is approximately
-2.8V below +Vs and can sink 30 mA to -Vs.

ATTENUATOR IN

This signal line is used as ANALOG HI IN line for higher voltage and current ranges.
Install the attenuator and shunt resistors prior to using this signal line.

BLANK IN

Activating this signal line blanks the display, excluding the selected decimal pOints
and the polarity sign. Data remains valid even with the display blanked.

BUSY/DONE OUT

This signal line is active during AID conversions. The signal line remains active until
the conversion is complete or until the end of measurement in the case of an
OVERRANGE. This signal line may be used to prevent the input voltage from
changing during conversions.

BCD OUT

Depending on the DPM model, these signal lines are digit serial outputs or 3-state
outputs. Refer to the data sheets for details on these signal lines.

DATA READY OUT

This signal is a short pulse (10 microseconds) which is produced 10 microseconds
after the data is valid in the DPM latches. This signal line may be used to trigger an
external microprocessor -based device.

DECIMAL POINT SELECT IN

The decimal pOints are selectable depending upon the application and range of
operation. To select a decimal point on the display, connect the decimal point signal
line to ground or DECIMAL POINT COMMON.

DESCRIPTORS IN

Some DPM models are equipped with descriptors to display electrical units. The
descriptors function as labels only. They do not select functions.

DIGIT DRIVES OUT

These signal lines multiplex the BCD data and direct the BCD to the proper digit.
These signal lines scan the five displays approximately 150 times per second (1.3
Milliseconds per digit). DIGIT DRIVES may be used for driving remote slave displays.

DISPLAY ENABLE IN

This signal line must be active for normal operation. Not activating this signal line
blanks the display, but keeps the A/ D converter sampling to reduce display turn-on
drift.

DISPLAY TEST IN

Activating this signal line displays 1888 on the DPM.

EOC OUT

This signal line goes high during A/D conversions. This may be used to prevent the
input voltage from changing during conversions.

EXT REF LO IN

The reference input from an external source must be referred to this signal line.

HOLD IN

Activating this signal line will hold and displays the last sample storage.

10-104

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

HORIZONTAL POLARITY

Activating this signal line displays the horizontal portion of the polarity sign.

OFFSET OUT

This signal line provides a 0 to 6.9V dc output referred to the negative rail. Using this
signal line requires installing optional offset potentiometer.

OHMS LO OUT

This signal line is used in the ohmmeter configuration only. This signal line is 6.9V dc
above the DPM's -5V dc negative rail.

OVERRANGE OUT

This signal line is high if the previous input signal exceeds the A/D converter range
of +19999 counts. The signal line remains high until the beginning of reference
integration in the next measurement cycle. UNDERRANGE and OVERRANGE are
normally used as up/ down ranging gain selection controls for an auto-ranging input
selection.

OUT OF RANGE OUT

See OVERRANGE.

OVERSCALE OUT

See OVERRANGE.

POLARITY ENABLE IN

Activating this signal line causes a '+' sign to be displayed for positive inputs and a '-'
sign for negative inputs.

POLARITY OUT

This signal line is active when the DPM receives a negative input signal. It is valid
even for a zero reading. A display of +0000 means the signal is positive but less than
the least significant digit.

POWER COMMON IN

The common of the external dc power source must be connected to this signal line.
This signal line may also be used as a bias current return path for signal inputs.

REFERENCE IN

Normally the DPM is calibrated when a + 1V dc drop exists between the signal line
and ANALOG RETURN. For ratiometric operation, an external reference is biased
against ANALOG RETURN, on EXT REF LO.

REFERENCE OUT

This signal line is normally jumpered to the REFERENCE IN LINE. This signal line is
approximately +1V dc above ANALOG RETURN.

REF IN/OUT

The DPM is calibrated when a +1 V dc drop exists between the signal line and
ANALOG RETURN. The DPM's are provided with an option to allow external
ratio metric reference. The external source must be biased against ANALOG
RETURN, on EXT REF LO.

RUN/HOLD IN

See HOLD.

STROBE OUT

After every A/ D conversion, five negative pulses of approximately 6.7 microseconds
width and approximately 1.3 milliseconds apart are issued on this line. The STROBE
signal indicates that valid multiplexed data is available on the BCD data output lines.
The data starts with the most significant digit.

UNDER RANGE OUT

This signal line is active if the previous input displays 1800 counts or less. The signal
line remains high until the beginning of signal integration in the next measurement
cycle.

UNDER SCALE OUT

See UNDERRANGE.

VERTICAL POLARITY

This signal line must be used with the HORIZONTAL POLARITY line for automatic
sign display of bipolar inputs.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356 10·105

II

PC-6
Programmable 10 MHz
Counter-Timer
FEATURES
• Performs five functions: unit counter, frequency
counter, sub-second .period counter, frequency rallo
counter, and sub-second interval timer
Offers four full-scale ranges to measure frequency
and lime (period and interval)
• All functions, ranges, and input slopes programmable
using TTL-compatible inputs or front-access
command switches
• 6-digit LED display with descriptors
GENERAL DESCRIPTION
The DATEL PC-6 is a low cost, ultra-compact, programmable
10 MHz Universal Counter-Timer. Frequency and time
measurements are displayed on a 6-digit, .3" high light
Emitting Diode (LED) display. The counter is housed in a panelmount polycarbonate short depth case.
Frequency measurements to 10 MHz can be made using an
internal crystal timebase (Frequency Counter function, with the
measured Frequency display in kHz), or with an external
timebase (Frequency Ratio Counter where FA/FB is
displayed). The PC-6 can also function as a Unit Counter, a
Sub-Second Period Timer (single input, measuring the period
of a single waveform), or a Sub-Second Interval Timer (dual
input, measuring the time period from a start pulse on Input A to
a stop pulse on Input B). Four ranges for each function permit
resolution on frequency measurements to.1 Hz and resolution
on time measurements to 100 pS.
The PC-6 differs from many available Universal counter-timers
in being programmable. Counter function, range, and input
slope are selected by a binary code. The code is input either

+5VIN

A1

INPUT A

A15

A17

INPUT B
POS/NEG
SLOPE

A14

RES'Er

818
A12

DiSPIAYfEST

SELECT

To Order, Specify: PC-6
ACCESSORIES
Part Number Description
58-2075010
Dual 18-pin edge connector
115VAC in, +5V dc (@ 500mA)
UPA-5/500
out power adaptor

A18

INPUT B

FUNCTION

ORDERING INFORMATION

A2 - - - , . - - - , . - - -.....- - - - - - - - - - - - - - - - - - - - - - - - - - - - . ,

INPUT A
POS/NEG
SLOPE

RUN/HCiLb

electrically on rear-panel, TTL-compatible digital inputs; or
manually by setting a front-access Command DIP Switch.

[

B17
B9

Fl

B6

F~

B4

CRYSTAL
OSCILLATOR

DESCRIPTOR
DECODER

S1
#1

S1
#2

81
#3

C~~~~N A3A16------------~4_-----------_4_4__4----~

Simplified Block Diagram of a PC-6
10-106

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

PC-6
SPECIFICATIONS
(Typical at +25°C unless noted)
FUNCTIONS
Unit (Event) Counter
Event counter dosplays total number of low-to-high
transitions (or high-to-Iow, see Input Slope Selection
Chart). Clears by RESET (Pin B-18).

Mealurement Range .... 999,999 counts occuring at
up to 10 MHz rate.
Frequency Counter
Measurement Range .... 10 MHz max. with 50 nS min.
pulse width.
Full Scale Rangel ...... 10000.0 kHz, 9999.99 kHz,
999.999 kHz, 99.9999 kHz.
Gate Times ............ User -selectable: 10mS.
lOOmS, 1S, lOS.
Timebase .............. Internal.
Displayed Unit ......... kHz.
Sub-Second Period Timer (Single Input)
Measurement Range .... 500 nS to .999999S.
Full Scale Ranges ...... 99999.9 p.S, 9999.99 p.S,
999.999 p.S, 99.9999 p.S.
Cyclel Measured ....... User-selectable: 1, 10, 100,
1000.
Displayed Unit ......... p.S.
Frequency Ratio Counter
Frequency Ratio Counter measures a frequency at Input A
referenced to another frequency at Input B, and displays
the unitless ratio FA/FB.
Full Scale Ranges ...... 99999.9:1, 9999.99:1,
999.999:1, 99.9999:1.
Frequency Range, ...... 10 MHz maximum
Input A
with 50% duty cycle square
waves
Frequency Range, ...... 2.0 MHz maximum
Input B
Cycles Measured ....... User-selectable: 1, 10, 100,
1000.
Displayed Unit ......... Pure ratio, FA/FB.
Sub-Second Interval Timer (Dual Input)
Time Interval Timer measures time period from a start
pulse at Input A to a stop pulse at Input B.
Mealurement Range .... 500 nS to .999999S.
Full Scale Rang........ 99999.9 p.S, 9999.99 j.lS,
999.999 j.lS, 99.9999 j.lS.
Cyclel Mealured ....•.. User-selectable: 1, 10, 100,
1000.
Dllplayed Unit .....•... j.lS.
Test
Test measures the PC-6 internal oscillator frequency (10
MHz nominally).
Relolutlon ............. 100 Hz, 10Hz, 1 Hz, .1 Hz.
Gate Tim.............. User-selectable: 10 mS, 100
mS, IS, lOS
Overall Accuracy
±1 count
Cryltal Accuracy
10 ppm accuracy, total (typical) over full temperature range.

Display
Six self-illuminated red LED digits, .3" (7,6mm) high.
Decimal Point
A decimal poini is automatically positioned to set display for
units shown
Descriptors
Set of 8 LED lamps, which illuminate lenses to indicate Function
and Displayed Unit. consists of: FREQ, TEST, UNIT, TI. (Time
Interval), F.R. (Frequency Ratio), P (Period), kHz, and p.S.
Descriptors are automatically selected with Function and
Range Selection, or may be disabled by opening Command
Switch #8.
Overrange
"Over" lamp on front panel lights: counting on displayed digits
continues
Front-Access Control
Command Switch SI can be used to select Function, Range,
Input Slope, and to enable or disable Descriptors
Time Between Measurement Cycles
200mS, all Functions, all Ranges.
I/O SIGNAL FEATURES
+5V IN (Pins A-1, A-2)
POWER COMMON (Pins A-3, A-16)
Power to PC-6 is input here: +5V (regulated) @ 350 mA
required. All logic inputs may be tied to +5V IN for Logic Hi; all
inputs may be tied to POWER COMMON for Logic Lo. All
inputs are returned at POWER COMMON.
INPUT A (Pin A-18)
INPUT B (Pin A-17)
Signals to be measured are input here (return at POWER
COMMON). INPUT A is used for all functions except Test.
INPUT B is used only in Frequency Ratio and Time Interval
functions.
INPUT A: POS/NEG SLOPE IN
(Pin A-15)
_
INPUT B: POS/NEG SLOPE IN
(Pin A-14)
These logic inputs select positive or negative slopes for INPUT
A and INPUT B (see "Input Slope Selection" Chart).
Connecting either input to POWER COMMON sets that inpultor
a negative slope; connecting either to +5V IN selects a posibite
slope.
F2 (Pin B-8) FUNCTION
F1 (Pin B-6) INPUT
FO (Pin B-4) CODE
R1 (Pin B-10) RANGE
RO (Pin B-11) INPUT CODE
These five pins select all Functions and Ranges on the PC-6.
See "PC-6 Function and Range Selection Chart" for details.
Inputs are CMOS with 1OkCl pull-ups to +5V for compatibility
with open collector logic.
1 = Logic HI (+3.5V < VH < +5V).
o = Logic LO (OV < VL < +1.5V).
RESET INPUT (Pin B-18)
Connecting this pin to POWER COMMON stops any
measurement in progress, resets the main counter, and
displays all zeros. Tie to +5V IN for normal operation. Input is to
a Schmitt Trigger (negative-going threshold = 1.5V typ;
positive-going threshold is +0.8V typ).

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10-107

•

.'

POWER REQUIREMENTS
+5V IN regulated at 350 mA typical between pins A1 I A2 (+5V
IN) and A3/A16 (POWER COMMON). Logic spikes must not
exceed 50 mV. Current varies rapidly as digits switch so that
unregulated supplies cannot be used.

INPUT

OUTPUT CONNeCTIONS PC

80TTOM A.
~...,

·sv

PWR IN {

PWR COMMON
NO CONNECTION

PHYSICAL-ENVIRONMENTAL
Outline Dimensions Short-Depth Case, 3.00"W x 2.15"0 x
1.76"H (76,2 x 54,6 x 47,7 mm)
Cutout Dimensions
1.812"H x 3.062"W (46,0 x 77,7 mm)

,.1)

TOP 6

r-i-i:~ ~~:::~ ~:~:

~J NO CONNEC TlON
liJ FUNCTION F~

KEYWAY~

NO CONNECTION
NO CONNECTION

_~-- KEYWAY

I~Sl NO CONNECTION
~

FUNCTION F 1

NO CONNECTION
NO CONNECTION

t. ~- NO
"s-1 NO

NO CONNECTION

~

CONNECTION
CONNECTION

NO CONNECTION L~--l FUNCTION f '}
NO CONNECTION ~ol RANGE R 1

Mounting Method
See end of this section.

RANGE RO

RUN/HOLD ~~~: NO CONNECTION
NO CONNECTION ~1 NO CONNECTIOf'4
B SLOPE ~-1 NO CONNEC TION
A SLOPE ~'5. NO CONNECTION

Weight
Approximately 7.4 ounces (210 g)
Operating Temperature Range
0° to +50°C (32° to 122°F)
Storage Temperature Range
-25°C to +85°C (-13° to +185°F)
Altitude
o to 15,000 feet (4900m)
Relative Humidity
10% to 90% non-condensing

PWR C?MMON

!,1_~ N?~ON._H~.C TlON

INPUT 8fl~OI~~~AY TfST
INPUT A! 1~: RESET

THE WAVEFORMS BELOW INDICATE THE MINIMUM TIMES AN INPUT MUST BE HIGH OR LOW TO INCREMENT THE COUNTER CIRCUITRY IN THE PC-6

INPUT A + 1,9 TO + 5V

o TO

FIGURE 1
FUNCTION ~ FREOUENCY, FREQUENCY RATIO, UNIT COUNTER

+ ,5V

INPUT A

OR
INPUT B

+ 1,9\0 + 5V

o TO

+ ,5V

FUNCTION

250nS

250nS

MIN

MIN

~

FIGURE 2
PERIOD. TIME INTERVAL

...In. ___________________

INPUT A _ _ _ _ _ _ _ _ _ _ _
200mS
MIN·

--J--.j
I :~!~.:
MIN

250nS

MIN

~

FIGURE 3
FUNCTION ~ TIME INTERVAL

INPUTB------------------,~r------------• 200ms REQUIRED BETWEEN MEASUREMENTS
FOR INTERNAL CIRCUITRY TO UPDATE

PC-6 Input Waveforms
10-108

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

PC-6
PC-I> FUNCTION AND RANGE SELECTION CHART
FUNCTION/RANGE SELECTION

~-----------'"'R,-,-:-,.""p''''n-'',U,;-;-:o-'.'''ic-1
RANGESCYCLESMEASUREDr-_ _ _S_'_0_1._P_S_W_'T._C_H_ _ _ _-+-,I...n"pu,..tc"~r''-,-1

FULL SCALE
FUNCTION0

DISPLAY

GATING TlMESI

TYPICAL INPUT

SIGNAL8

WAVEFORM

INPUT PINIS)

B9 B6 B4 B1C B11
UNIT (EVENT)

999999 counts

COUNTER

~1,--..;~~..;~~_ _ _p21 '" 1

OPEN

N/A

1

°

1

-

-

J1SLJLfl....

A·1S

FREQUENCY

COUNTER
(I nternal Tlme-

basel

OPEN

~999/l~_

SUB-SECOND

_ '}

9999.99/l5

PERIOD TIMER

-100

CYCLE5
MEASURED OPEN

1

OPEN

99.9999/l5

1

_ _ J.

99999.9: 1
FREQUENCY

OPEN

9999.99"

10

~YCL_E!i_

1

1

3

_·...Qm
2

2

3

o o
4

1

1

1

1

5

•

'" '"
1
D----c--Y-+-+_+-+-1
4

5

·J:L
4

5

0

•

•

3

4

5

I : .'
1

1

'"

1

+--e-

'"

1

D';;-__ ·~--~D_:_-':D~--'--i-'-t-"'_+-'t--"'-t-"'..,
2

r~-D

MEASURED OPEN

(External Time-

1

2

I• •

1000
OPEN

RATIO COUNTER

3

L7 : ~
I· • 0

~~ __n _ .... 1•

(single mput)

2

...OPEN

_

10

~---

1

2

3

4

5

_·_..Q_....
3

4

n
---.J

n
U

n
LJ

n
LJ

INPUT
L

A

A-1S (INPUT AI

L,l _"'- _'+-"'+_'+--__________+--_______-1

5

1 t/J 1
100
~. • 0
- - . - -·-t------t----+=OP=EN
1
2 -=3---:4----':5'--'--+-+--1-+-+-1

999.999"

basel

99.9999"

1000

I•

1

0

•

•

'"

1

1

'"

t/J

1 '"

SUB-SECOND

~

9999.99/l5

A-18 (INPUT AI

~TA.B_:

999.999/l5

I

3MEASURED OPEN

100

~-----i-:

99.9999/l5

3

1

4

•
--"------L
- - - - . - O~P~E=NC·,~~I~=~~~=~~t=~4~=~~~=.~r-t-i-~-t--l

1000
(.;\

OPEN

I•

1 '"

1..

0

0

••

1
0

2
•

3

4

5
0

10000.0 kHz0 .01S
I
~--------~--t----+------.."O~P~E~N~-~~I~=~~;=~~~--~~~5~
0000.00 kHz0 .15
GATING
I°
•

'"

1

'"
1

1

t/J

'" 1

'"

1

'" '" '"

'"
r---------~~t----·)-T-,M-E-5--.."O~P~E~N~=,~~2--~~~=~~~5--l-j--r-t-..,,-+~
I
I° •
I° •

TEST

A-17 (INPUT 81

'"

INTERVAL

(dual input)

-. 8

•

99999.9/l5

TIMER

~INPUT

1

'"

'"

A-17 (INPUT BI

1

N/A

N/A

000.000 kH,0 15
0
•
0
'" 1 '" 1 '"
~----~-+------+----l-O:-:P:-:E::-N~··~,~-2-~3~-4-~5~l-j-+-t--..,,-+~
00.0000 kHz0

0

105

••

=

Logic Low IOV< V L <+1.5V)
1 = Logic High (+3.5V< V H <+5.0VI

- '" Don't care,

2) FREQUENCY COUNTER may identically be selected by:

OPEN

1

2

3

~
OPEN

1

2

3

~

89

B6

84

~

Range Selection codes are those given in the above chart
for

~

if*P

Function Code.

3) TEST measures the internal oscillator frequency of the PC-6. This is nominally 10.0MH:z (lQOOOkHz). In the lower three ranges on TEST. the 10.0MHz frequency will be over-

scale (Overrange light will turn onl. The least significant digits on these ranges are accurately displayed to permit more accurate calibration of the PC-6.

41 All input signals are returned at A-16, POWER COMMON.
5) On the PC-G, Gating Times or Number of Cycles Measured is selected automatically with the Full Scale Display Range.
6) To measure a single cycle in the INTERVAL TIMER function, the PC~ must be "primed," first by a single cycle preceding that to be measured. The first cycle sets the counter
circuitry; the second cycle is measure~.
7) In FREQUENCY and P!=RIOD functions, tie INPUT B (pin A-171 to POWER COMMON (pin A-161.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rTEL (508) 339-3000rTLX 174388/FAX (508) 339-6356 10-109

III

PC-6
APPLICATION NOTES
The PC-6 is designed to fit into automatic test equipment. In
most applications, the tester's built-in logic circuitry can
program the PC-6's functions, ranges and input slopes. The
PC-6 with external circuits (switches, power supply and
connectors) may be configured as a full, self-contained
benchtop counter for test and repair applications.

+ 5V

10K!!
REAR CONNECTOR PC-6
PCB EDGE "'FINGER
'...
I - I - '-t::J--------TOCONTROLCIRCUIT

I

I

~

)

OPEN COLLECTOR
TTL GATE
(TOTEM POLE LOGIC
MAY ALSO
, BE USED)

'OPEN

~

1

~

UP

TYPICAL EXTERNAL
DRIVE CIRCUITS

PC-6 Typical Programmable Function Input

$1 COMMAND DIP SWITCH·
(BEHIND FILTER)

FUNCTION SELECT

-----+--___---'

RANGE SELECT - -_ _ _~---------'

INPUT SLOPE SELECT - - - - - - - - - ' ' ' : - - - - - - - - - - - '

DESCRIPTORS

--------------===-___..::::.----'
NOTE- TO USE REAR PANEL INPUTS OPEN ALL SWITCHES

PC-6 Command Switch Location

10-110

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

PM-5050

THERMOCOUPLE INPUT
INTELLIGENT PROCESS
MONITOR/CONTROLLER
FEATURES
• Microprocessor-based, with all operating parameters
set/recalled using the front panel or via the RS-232-C
serial communications port.
• Totally menu-driven monitor configuration including:
1. J, K, T, S, B, E, N, or R type thermocouple
measurement.
2. Cold junction compensation (CJC) enable/disable
option.
3. Celsius or Fahrenheit display option with 0.1, 1.0
degree resolution.
4. Up to 4 setpoint entries, with up to 25 degrees
hysterisis.
5. Serial communications options for baud rate, parity,
stop bits.
• Automatic display of open thermocouple conditions.
Automatic gain and offset calibration.
• Total signal-to-Iogic and line-to-Iogic isolation (1400V).
• Over 50 simple ASCII commands usable via the serial
port for data acquisition and control.
• Four MOSFET setpoint outputs (300V, 100mA load) are
individually programmable for absolute, relative, high-,
or low-going temperatures.
• Six character (five digits), 14-segment, alphanumeric
0.4" high fluorescent blue-green display with six custom
annilciators.

• Security feature to prevent front panel tampering.
• All parameter values saved in EEPROM.
• Optional analog output (0 to 10V de or 4-to-20 mA). Userprogrammable temperature range for scaling.
• Screw-terminal connectors for easy power and input
connections.
• Compact % DIN case, standard DIN panel mount cutout.
• Interfaces directly to Daters thermal printers.
• Optional RS-485 interface for 32-point multi-drop
applications.

DATEL'S pM-5050 INTELLIGENT PROCESS MONITOR AND DISPLAY IS SPECIFICALLY DESIGNED FOR REAL-TIME THERMOCOUPLE
DATA ACQUISITION AND CONTROL APPLICATIONS. THE HIGH-ISOLATION INPUT AND FOUR SETPOINTOUTPUTS ARE TOTALLY
CONTROLLABLE FROM THE EASY-TO-USE RS-232-C ASYNCHRONOUS COMMUNICATIONSPORT. ENGINEERED FOR RUGGED
INDUSTRIAL ENVIRONMENTS, THE PM-5050 OFFERS UP TO 1400V ISOLATION, 128dB CMRR, AND A HIGH RFI AND EMIIMMUNITY.
FUNCTIONAL DESCRIPTION
The functionality built into the PM-5050 allows high-precision
process monitoring with real-time display of process
parameters. The monitor supports eight thermocouple types:
J, K, T, S, B, E, N, and R. Functionally, the PM-5050 has five
sections: isolated analog input section, microprocessor and
control logic, front panel key board and display, serial communications port, and set pOint outputs. (See the Block Diagram
in Figure 1.)
The isolated analog input section consists of thermocouple
input circuitry, signal conditioning pre-amplifiers, cold junction
compensation (CJC) ci rcuits, and a vOltage-to-frequency converter. The analog input section is isolated up to 1400V RMS
from the control logic and power lines. The 128dB CMRR
ensures accurate readings by rejecting unwanted common
mode voltages sometimes introduced by ground loops. The
CJC input is located in the screwterminal connector, thus offering a true cold junction compensation reference.

monitor supports over 50 ASCII commands for operation via
the serial communications port. The command structure uses
simple command/reply message protocols. All control
parameters set on the monitor are saved in an EEPROM and
are automatically retrieved on power up.
A significant feature of the monitor is the easy-te-use front panel
keypad. All meter functions are user-selectable by a few simple keystrokes. The display is completely menu-driven with
selectable parameters appearing directly on the display. The
vacuum fluorescent display has six custom annunciators, four
for indicating setpoint status, and two for calibration parameters
(full-scale, and zero). The PM-5050 displays five digits, such
as 3001.6, providing a tenth of a degree of resolution.

The microprocessor and control logic linearizes the input signal depending on the thermocouple type used. This section
also processes commands received from both the front panel
keypad and the RS-232-C serial communications port. The

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-111

."

PM-5050
DIGITAL LOGIC
FRONT PANEL DISPLAY
CLOCK

.....

..

EEPROM
CPU
ADDRESS
DECODER

.A

"-

..,.- r--v

1/0 AND
TIMER
CONTROL

DISPLAY
DRIVE

t~

8ITJo] r

~...

,

VACUUM
FLOURESCENT DISPLAY

NTE,

:1---

V/F
CONVERTER

llSOLATION

MUX

r-~

SERIAL
PORT

~

R8-232-C

CJC IN
TC+
TC-

IISOLATIONI

7

t

12-81T

ANALOG INPUT

SETPOINT
OUTPUTS

D/A
OUTPUT

~

I-I-I--

AA~~_

ANALOG OUT
(SEE NOTE)

SP-1 SP-2 SP-3 SP-4

OUTPUT

+5Vdc_
+15Vdc+12Vdc-12Vde_

ISOLATOR
POWER
SUPPLY

-():

+30V de
3.3 VAC - - ' - -_ _ _ _..J

NOTE: The optional analog output is user-configurable for 4-to-20 mA or 0 to +10V dc.
Figure 1. PM-5050 Block Diagram

The PM-5050's serial port is configurable to perform as either
a DTE or DCE device, depending on how the communication
cable is wired. The monitor supports simple ASCII commands
to exercise the functions. In addition to the commands that
read, set, and invoke control parameters, the software in the
monitor also supports diagnostic commands. The PM-5050 is
configurable for baud rates from 110 to 9600 baud.
The PM-5050 provides the user four opto-isolated setpoint outputs (SP-1 through SP-4) to respond to four front panelselectable preset temperatures. The annunciators on the vacuum fluorescent display indicate the setpoint status.
The setpoint outputs are isolated from power lines, logic, and
input to up to 1500 volts. The setpoints are individually programmable for high- or low-going, absolute, or relative temperatures.
For relative setpoint operation, setpoints SP-2, SP-3, and SP-4
are active relative to setpoint SP-1. The setpoints may be set
in degrees C or degrees F with user-selectable hysterisis bands
up to 25 degrees.
The setpoint outputs are solid state MOSFET relays able to
drive up to 100 mA, 300V loads. The setpoint outputs are usable as alarm outputs or to control heater circuits in temperature
control applications. The alarm status is displayed through the
display annu nciators.

Table 1. Thermocouple Input Ranges, Accuracy and
Drift, (maximum)
Thermocouple
Type

J

K
S

T
B
E

R

N

Temperature
Accuracy
Range (OC)
-21010 -100
+0.2OC
+O.lOC
-10010 +760
-21210 -100
+0.3°C
-10010 0
+O.IOC
010 +1371
+0.2°C
010300
+0.7°C
+0.5C
+300101768
-27010 -200
+1.0°C
+O.soC
-20010 +400
+21010 +750
+1.0 C
+75010 +1820
+0.6°C
-270 10 -200
+0.7C
-20010 -100
+0.2°C
-10010 +900
+O.IOC
-50100
+1.2°C
010 +850
+0.4OC
+O.soC
+850 10 + 1768
-200100
+O.4°C
010 +400
+0.2°C

Temperature
Drift (OC/OC)

0.1
0.15

0.3
0.1
0.3
0.15

0.3

0.3

Table 1 shows the various types of thermocouple input ranges
available.

10-112

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

PM·5050
FUNCTIONAL SPECIFICATIONS
at 25 degrees C, unless noted)

~plcal

ANALOG INPUT
Analog-to-digital ........ VOltage-to-frequency converter,
conversion
microprocessor controlled
Conversion time ........ 300 mSec, maximum
Resolution ............. 0.1 degree or 1 degree
(User-selectable)
Range Tempco .......... +25 ppm/oC, typical
+50 ppm/oC, maximum
CJC error .............. +0.5°C, maximum
Oto 60°C
Stability ............... Automatic gain and offset
calibration every 1.8 seconds
Configuration ........... Differential (isolated)
Range ................. -10mV to + 70mV dc
Impedance ............. 100 Megohms, minimum
Common mode voltage ... 1400V (peak AC or dc)
Differential input ........ 115 VAC, continuous
overvoltage protection
(Short to or across ...... 230 VAC, 5 seconds
AC line without damage.)
Normal mode rejection ... 80 dB, minimum
ratio, at 50/60 Hz
Common mode rejection . 128 dB, minimum
140 dB, typical
ratio, dc to 60 Hz
DISPLAY SPECIFICATIONS
Type .................. 14-segment, alphanumeric,
blue-green vacuum
fluorescent
Number of ............. 6 alphanumeric characters
characters
Annunciators ........... SP-1, SP-2, SP-3, SP-4,
ZERO, F.S.
SETPOINT OUTPUT SPECIFICATIONS
Number of setpoint ......' 4
outputs
Setpoint control ........ User-programmable for high
or low-going, absolute or
relative temperatures.
For relative operation, SP-2,
SP-3, and SP-4 are active
relative to SP-1
Output type ............ Opto-isolated MOSFET's
Isolation ............... 1000V minimum, 1500V
typical
Output rating ........... 300V at 100 mA resistive load
(maximum)
Hysteresis range ........ User-selectable; 25 degrees,
maximum
POWER REQUIREMENTS
Operating Voltage ....... 100, 115, 230 VAC
+5V dc, or +9 to +36V dc
(optional)

Power Consumption
AC Models ........... 2.5W typical, 4W max.
DC Models ........... 385 mA @ 5V dc
SERIAL COMMUNICATION SPECIFICATIONS
(RS-232-C standard)
Baud rate

· .. 110 to 9600 baud

Format
Data bits .... .
Parity ....... .
Stop bits ...... .

.7 or 8
· .. Even, odd, or none
.. 1 or 2

ANALOG OUTPUT SPECIFICATIONS (OPTION)
Types
.. Voltage or current, userselectable
VOLTAGE
..... 0 to 10V dc, at 2A maximum
Resolution. . . . . ...... 12 bits
Non-linearity
.. ±0.1%
Gain Tempco .

. ... ±50 ppm/degree C

Offset Tempco . .. . ..... ±0.1 mY/degree C
Span . .
. ............ Programmable using front
panel keys.
CURRENT. . . .
. .... 4-to-20 mA
Compatibility.
. ISA type U
Excitation. . . .
. Internal
Accuracy .....
Load Resistance
Span and Offset .... '

.0.1% full-scale range
. 100 ohms, minimum
1000 ohms, maximum
.. Programmable using front
panel keys

PHYSICAL SPECIFICATIONS
Case quality.

. .... High-impact, flame retardant
polycarbonate
Case dimensions ........ 3.622"W x 1.771"H x 5.47"L
(92 W x 45 H x 139 L) mm
Length including ........ 6" (152 mm)
terminals
Bezel dimensions
.3.97" W x 2.08" H x 0.35"0
(101 W x 53 H x 9 D) mm
Panel cutout ..
. '/s DIN standard
3.622"W x 1.772"H
(92W x 45H) mm
Front panel control ...... Membrane keypad with 4 key
switches
Weight ...... .
· .. 1 pound 4 ounces
ENVIRONMENTAL SPECIFICATIONS
Operating temperature ... 0 to +60°C
range (see note)
(+32 F to + 140°F)
Storage temperature ..... -40°C to +85°C
range
(-40°F to + 185°F)
.. 0 to 90%, non-condensing
Relative humidity
NOTE: The monitor will operate from -10°C to +70°C at a
reduced accuracy.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-113

,

III

PM·5050
ANALOG OUTPUT
The PM-5050 has an optional analog output which outputs a
voltage or current in proportion (or inverse proportion) to the
temperature reading. The output is suitable for simple control
applications (e.g., heater control) or to drive external measuring devices such as strip chart recorders.
An on-board 12-bit D/A converter provides a 0 to 10V dc or 4 to
20 mA output. The temperature range for the output is programmable from either the front panel or the serial communications
port. The on-board microprocessor performs the required D/A
output scaling.

PM·5050 MENU DESCRIPTION
The PM-5050 is operable from both the front panel key pad and
the serial communications port. The front panel keypad
consists of four keys: MENU SELECT, UP ARROW, DOWN
ARROW, and ENTER. The menus are interactive, with the
process parameter appearing directly on the display. The
MENU select key scrolls through the menus available at each
level and the ARROW keys scroll through options available for
each parameter selected. The ENTER key sets the value for
the selected parameter. Table 2 shows the parameter values.
The serial communications menu also allows enabling a data
output mode. In this mode, the PM-5050 continuously outputs
a data message to a printer at a user-selectable rate. The data
message consists of information on the monitor configuration,
status of setpoints, and thermocouple data.

rates, parity, stop bits and ID number using the front panel keys.
The monitor supports over 50 simple ASCII commands usable
via the serial port for data acquisition and control.
The host may issue three types of commands to the monitor:
configuration commands, data acquisition commands, and
diagnostic commands.
Configuration commands:
These commands set the
PM-5050 to the user-selected operating mode. The monitor responds to the commands either with an acknowledge
character or by echoing the command message back to
the source.
Data acquisition commands: These commands read and
log in temperature data and the status ofthe monitor. The
monitor responds with a fixed-format ASCII message. The
reply message consists of an ASCII string containing the
monitor's ID number, thermocouple data and status, the
status of the monitor configuration, and checksum. The
data acquisition commands also operate in a continuous
mode. In this mode the PM-5050 sends data, status, and
checksum to the host system at a user-selectable rate.
Diagnostic commands: These commands test the
PM-5050 display, perform calibration, read RAM locations,
read reference voltage values, and check the result of builtin self test routines. Table 3 lists some command
descriptions.
Table 3. PM·SOSO Command Descriptions (partial list)

Table 2. PM·SOSO Front Panel Menu Options
Menu
Secu ritv Code
'Input

Setpoint
Serial
Communications

Self-test
Calibration
D/Aoutput

Menu Selection
Choice

Parameter Selection
Choices

See Notes
TCtype

Enable/Disable
J, K, T, S, B, E, N,
and R
Degree C of Degree F
O.lOC or 1.0oC
On or Off
User·selectable
Up to 25 degrees
110, 300, 600, 1200,
2400, 4800 and 9600
Odd, Even, or None
lor 2
o through 99

Unit
Resolution
CJC
1 to 4
Hysterisis
Baud rate
Parity
Stop bits
ID number
Diagnostics

AID, CJC, and D/A
Zero and full·scale

NOTES
The PM-5050 uses three different security codes for the
following:
1. Enable the security to prevent front panel tampering.
2. Enabling the calibration mode to calibrate the meter.
3. Disabling the security to change monitor settings.
PM·SOSO SERIAL COMMUNICATIONS
A standard feature included in the PM-5050 is an RS-232-C
serial communications port. The PM-5050 may operate as a
DTE or DCE device depending on the connection scheme used
from the J1 connector to a typical D-type connector.
The monitor receives configuration information and process
parameters via the serial port, using conventional ASCII message formats. The monitor is configurable for different baud

10-114

Configuration
Commands

Data Acquisition
Commands

Diagnostics
Command

Set thermocouple type
Set temperature unit (OC or OF)
Set resolution (0.1 or 1.0)
Set/Read setpoints values
Set/Read hysteresis value
Set/Read D/A scaling values
Transmit data in decimal or hex format
Transmit to host temperature measured
Transmit to host CJC temperature
Transmit to host last 64 data samples with
status
Transmit to host the PM-5050 status
Enable/Disable command echo
Enable/Disable terminal emulation mode
Enable/Disable reply messages on set·
point conditions
Set reply message format
Send thermocouple data to host
Output digital data to D/A section
Test display segments
Perform calibration
Read internal reference values
Read raw temperature value
Read CJC value
Perform self-test

APPLICATION: MONITORING AND CONTROLLING
PROCESS TEMPERATURE
The PM-5050 has built-in features applicable to controlling
process temperature. Figure 2 shows a typical PM-5050 application configuration.
The setpoi nt outputs provide the on/off control to a process, and
an alarm at preset temperatures. These setpoints may be absolute, or relative to a certain process temperature. The optional
analog output is a linear controlling voltage (0 to + 10V dc) that
is usable to control a heater coil.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

PM-5050

ALARM
SETPOINT2
RS-232-C...

PM-SOSO

TC
.INPUT

PROCESS

•

HEATER
CONTROL
.~

ANALOG
OUTPUT

SET POINT 1

...

ON/OFF
CONTROL

,
..

HOST
SYSTEM

LINEAR
CONTROL

Figure 2. Temperature Control By A Host System Using the PM-5050

The PM-SOSO automatically scales the analog output to a userprogrammed temperature range. All process parameters may
be set from the front panel or via the serial communications
port. Users may also operate the PM-SOSO from an intelligent
host system using simple ASCII commands to acquire data and
control the process.
PM-5050 INPUT/OUTPUT CONNECTIONS
The PM-SOSO uses terminal blocks TB1 and TB2 for
thermocouple inputs and power connections respectively.
The setpoint outputs and serial communications are provided on the J1 connector. Tables 4 through 6 show pinouts for
I/O connections.

Table 4b. RS-232-C Connections (Jl)
Signal
TXD
RXD
CTS
RTS
DTR
GND
+5Vdc

Table 5. Thermocouple Input Connections (TB1)
Connection
T81-2
T81-4

Table 4a. Setpoint Output Connections (Jl)
Setpoint
SP-l
SP-2
SP-3
SP-4

Connections
81
82
Al
A2
84
85
A4
A5

Connection
821
820
818
819
A16
816
A6

Table 6: AC Power Supply Connections (TB2)
Signal
GROUND
115/2301100 VAC Hot
110/2301100 VAC Neutral

Connection
TB2-1
TB2-2
T82-3

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-115

PM-SOSO
PM·5050 MECHANICAL DIMENSIONS
The PM·5050 fits into standard 1/8 DIN panel cutouts. Mount·
ing procedures involve tightening two screws through a metal

bracket (supplied) against the front panel. Figure 3 shows the
mechanical dimensions of the monitor.

r

II

1/8 DIN CUTOUT

I
menu

T

5050 RTD

CUIIEL

I
enter

V

_

2.08

1

l>.

om,.

1~4==========:;j_1

3.622"

+

+

0.024

(!:;!~gE
/

0.032

- 0.000 (92mm

+

0.81\
-0.00)

I:

- 5 . 4 7_ _1

GAIN'
ADJUST

1 - ' - - - - - - - 6 . 0 - - - - - - -..... 1

OFFSET'
ADJUST

J1

o

~~
.....-----:--r-'L..
....... ~

o

o@o

'AVAILABLE ONLY
WHEN OUTPUT
OPTION IS INSTALLED

102

Figure 3. PM·5050 Mechanical Dimensions
ORDERING INFORMATION

o

PM·50XO·

Thermaca~~~

T

5

*Strain Gage 7
'Voltage 8

POWER SUppLY
[A =
E =
J =
D =

110VAC
230VAC
100VAC
SVdcor
+9ta +36Vdc

ANALOG OUTPUT
'TO BE ANNOUNCED
COMMUNICATIONS MODE

o = No analog ouput
1 = One analog output, 4 • to - 20mA or
010 10V

0= RS-232-C
1 =20mA current loop"
2 = RS-422/485
SETPOINTS
1 =4 setpaint outputs (standard)
(100mA.300V)
DATEL warrants this product to be free of defects in material and workmanship for a period of one year from the date of shipment. under normal use and service. DATE!:s
obligation under this warranty are limited to replacing or repairing the product, at its option, at its factory or facility. The defective product must be shipped to DATE!:s
facility for repair or replacement within the warranty period, transportation and charges prepaid. This warranty shall not apply to a product which has been subject to

misuse, negligence, or accident. In no case shall DATEt:s liability exceed the original purchase price. The aforementioned provisions do not extend the original warranty period of this product which has either been repaired or replaced by DATEL.
NOTE: Equipment sold by DATEL, Inc. is not intended to be used, nor shall it be used, as a "Basic Component" under 10 CFR 21 (NRC).
Should this eqUipment be used in or with any nuclear installation or activity, you will indemnify us and hold us harmless from any liability or damage whatsoever ariSing

out of the use of the equipment in such a manner.

10-116

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·1194ITEL (508) 339·3000ITLX 174388/FAX (508) 339·6356

PM·5060
RTD/THERMISTOR INPUT
INTELLIGENT PROCESS
MONITOR/CONTROLLER
FEATURES
o

o

Microprocessor-based, with all operating parameters
set/recalled using the front panel or via the RS-232-C
serial communications port.
Totally menu-driven monitor configuration allows:
1) Measuring inputs from
a) 100Q RTD's, types:
American (Alpha
0.00391)
European (Alpha
0.00385, DIN 43760)
b) Thermistors, types:
2252Q,3000Q,5000Q,10000Q
2) Two-, three-, or four-wire operation
3) Celsius or Fahrenheit display option with 0.1, 1.0·
resolution.
4) Up to 4 setpoint entries, with up to 25· hysteresis.
5) Serial communications options for baud rate, parity,
stop bits.
Automatic display of open RTD input conditions. Automatic gain and offset calibration.
Total signal-to-Iogic and line-to-Iogic isolation.
Over 50 simple ASCII commands usable via the serial
port for data acquisition and control.
Four MOSFET setpoint outputs (300V, 100 mA load) are
individually programmable for absolute, relative, high-,
or low-going temperatures.
Interfaces directly to IBM PC or compatibles.
1400V input isolation for transient protection.

=

=

o

o
o

o

o
o

o

o

o
o

o
o
o
o

Interfaces directly to DATEL's printers: APP-20_21,
MPP-20, APP-48_2
Six character (five digits), 14-segment, alphanumeric
0.4" high fluorescent blue-green display with six custom
annunciators.
Security feature to prevent front panel tampering.
All parameter values saved in EEPROM.
Optional analog output (0 to 10V dc or 4-to-20 mAl. Userprogrammable temperature range for scaling.
Screw-terminal connectors for easy power and input
connections.
Compact 1/8 DIN case, standard DIN panel mount cutout.
Optional RS-485 interface for 32-point multi-drop
applications.

DATEL's PM-S060 Intelligent Process Monitor and Display is specifically designed for high-accuracy, real-time RTD and
thermistor data acquisition and control applications. The high-isolation input and four setpoint outputs are totally controllable
from the easy-to-use front panel or the RS-232-C asynchronous communications port. Engineered for rugged industrial
environments. the PM-S060 offers up to 1400V Isolation, 128 dB CMRR, and a high RFI and EMI immunity
GENERAL DESCRIPTION
The PM-5060 is an ideal choice for applications requiring highly
accurate high-resolution temperature measurement and display. The functionality buiit into the PM-5060 allows highpreCision process monitoring with real-time display of process
parameters. The monitor supports 100Q platinum RTD types
DIN 43760 (with Alpha = 0.00385) and American (with Alpha
= 0.00391). The device also supports inputs from 2,252Q,
3,000Q, 5,000Q, and 10,000Q thermistors. The PM-5060 is usable with two-, three-, or four-wire inputs.
Functionally, the PM-5060 has five sections: an isolated analog input section, microprocessor and control logic, front panel
keyboard and display, serial communications port and setpoint
outputs. (See the Block Diagram in Figure 1).

to 1400V RMS from the control logic and power lines. The 128
dB CMRR ensures accurate readings by rejecting unwanted
common mode voltages sometimes introduced by ground
loops.
The microprocessor and conltol logic linearize the input signal
depending on the RTD/thermistor type used. Th is section also
processes commands received from both the front panel keypad and the RS-232-C serial communications port. The monitor supports over 50 ASCII commands for operation via the
serial communications port. The command structure uses simple commandlreply message protocols. All control parameters
set on the monitor are saved in an EEPROM and are automatically retrieved on power up.

The isolated analog input section consists of RTD/thermistor
input circuitry, signal conditioning pre-amplifiers, and a voltageto-frequency converter. The analog input section is isolated up

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-117

II'
Ii

PM-5060
DIGITAL LOGIC
FRONT PANEL DISPLAY
CLOCK

~
"

EEPROM
CPU
ADDRESS
DECODER

A

' r - --V

IiOAND
TIMER
CONTROL

DISPLAY
DRIVE

tk

VACUUM
FLUORESCENT DISPLAY

8 (TICO ~NTE'

A

r-....

--

.--

~SOLATION

V/F
11-CONVERTER

MUX

r-'i

t

12-81T
D/A
OUTPUT

SERIAL
PORT

a

7

R8-232-C

RTD+
RTD-

i--

IISOLATIONI

CURRE NT
SOURC E

GROU NO

ANALOG INPUT

SETPOINT
OUTPUTS

~

ANALOG OUT

sp~sA!!P-4

(SEE NOTE)

OUTPUT

+5Vdc_
+15Vdc_
+12Vde_
-12Vde_
+30V de
3.3 VAC

ISOLATOR
POWER
SUPPLY

{}:

--1-____--'

NOTE: The optional analog output is user-configurable for 4-to-20 mA or 0 to + 10V dc.
Figure 1. PM-S060 Block Diagram
A significant feature of the monitor is the easy-to-use front panel
keypad. All meter functions are user-selectable by a few simple keystrokes. The display is completely menu-driven with
selectable parameters appearing directly on the display. The
vacuum fluorescent display has six custom annunciators, four
for indicating setpoint status, and two for indicating calibration
parameters (full-scale, and zero). The PM-S060 displays five
digits, such as 1472.3, providing a tenth of a degree of resolution.
The PM-5060's serial port is configurable to perform as either
a DTE or DCE device, depending on how the communication
cable is wired. The monitor supports simple ASCII commands
to exercise the functions. In addition to the commands that read,
set, and invoke control parameters, the software in the monitor also supports diagnostic commands. The PM-S060 is configurable for baud rates from 110 to 9600 baud.
The PM-5060 provides the user four opto-isolated setpoint outputs (SP-1 through SP-4) to respond to four front panelselectable preset temperatures. The annunciators on the vacuum fluorescent display indicate the selpoint status.
The setpoint outputs are isolated to power lines, logic, and input to up to 140OV. The setpoints are individually programmable
for high- or low-going, absolute, or relative temperatures. For
relative setpoint operation, setpoints SP-2, SP-3, and SP-4 are
active relative to setpoint SP-1. The setpoints may be set in

10-118

degrees C or degrees F with user-selectable hysterisis bands
up to 25°.
The setpoint outputs are solid-state MOSFET relays able to
drive up to 100 rnA, 300V loads. The setpoint outputs are usable as alarm outputs or to control heater circuits in temperature
control applications. The alarm status is displayed through the
display annunciators. Table 1 lists the input ranges of common
input devices and their accuracy.
Table 1. Input Ranges and Accuracy

Accuracy
Input Type

Range

Typical

Maximum

-2OOto +8S0"C

±0.1"C

±O.soC

-2ooto +850"C

±0.2"C

±O.S"C

22S2Q Thermistors

-SO to O"C
to +IS0"C

±2"C
±0.2"C

3000Q Thermistors

-SO to O"C
fo +IS0"C

±3°C
±0.2"C

SOOOQ Thermistors

+IS0"C

±0.2"C

+IS0"C

±0.3"C

100Q Platinum RTD
Alpha = 0.00391
100Q Platinum RTD
Alpha = 0.0038S
(DIN 43760)

10000Q Thermistors

o

o
oto
oto

-

-

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

PM·5060
FUNCTIONAL SPECIFICATIONS
(Typical at +25°C, unless noted)

ANALOG OUTPUT SPECIFICATIONS (OPTION)
Types.

.......... Voltage or current, userselectable

ANALOG INPUTS
Analog-to-digital . . . .. . .. Voltage-to-frequency conversion converter, microprocessor controlled
Conversion Time ......... 300 mSec., maximum

VOLTAGE ................. Oto 10V dc, at2 mA max.
Resolution ...

...... 12bits

Non-linearity ............ ±0.1%
Gain Tempco ............ ±50 ppm/oC

Resolution .............. 0.1° or 1°
(User-selectable)

Offset Tempco ........... ±0.1 mVioC

Range Tempco ........... +25 ppm/oC, typical
+50 ppm/oC, maximum

Span ................... Programmable using front
panel keys.

Stability ................ Automatic gain and offset
calibration every 1.8 Sec.
Configuration ........... Differential (Isolated)
Range .................. -10mVto +70mVdc
Impedance .............. 100 Megohms, minimum
Common mode voltage ... 1400V (peak AC or DC)
Differential Input
overvoltage protection .... 115 VAC, continuous
Short to (or across)
230 VAC, 5 Sec.
AC line without damage.

CURRENT . .

. .... .4-to·20 mA

Compatibility ............ ISA type U
Excitation ............... Internal
Accuracy ............... 0.1 % full-scale range
Load Resistance ......... 100Q, minimum
1000Q, maximum
Span and Offset .......... Programmable using front
panel keys
PHYSICAL SPECIFICATIONS

Normal mode rejection .... 80 dB, minimum
ratiO, dc to 60 Hz

Case quality ............. High-impact, flame retardant
polycarbon ate

Input bias current ........ 8 nA, maximum

Case dimensions ........ 3.622"W x 1.771"H x
5.47"L
(92 W x 45 H x 139 L) mm

DISPLAY SPECIFICATIONS
Type ................... 14-segment, alphanumeric,
blue-green vacuum
fluorescent
Number of characters.

.6 alphanumeric characters

Annunciators ............ SP-1, SP-2, SP-3, SP-4,
ZERO, F.S.
SETPOINT OUTPUT SPECIFICATIONS
Number of setpoint outputs4
Setpoint control ......... User-programmable for high
or low-going, absolute or
relative temperatures.
For relative operation, SP-2,
SP-3, and SP-4 are active
relative to SP-1.
Output type .... .
Output rating ...... .
(maximum)

.... Opto-isolated MOSFET's
. 300V at 100 mA
resistive load

Hysteresis range ......... User-selectable; 25° max.

Length, including ........ 6" (152 mm)
terminals
Bezel dimensions ........ 3.97" W x 2.08" H x 0.35"0
(101 W x 53 H x 9 D) mm
Panel cutout ...

.1/8 DIN standard
3.622"W x 1.772"H
(92W x 45H) mm

Front panel control ....... Membrane keypad with 4
key switches
Weight ................. 1 pound, 4 ounces
ENVIRONMENTAL SPECIFICATIONS
(The monitor will operate from -10°C to +70°C at a reduced
accuracy.)
Operating temperature .
range

.Oto +60 0 C
(+32°F to + 140°F)

Storage temperature ...... -40°C to +85°C
range
(-40°F to + 185°F)
Relative humidity ........ 0 to 90%, non-condensing

SERIAL COMMUNICATION SPECIFICATIONS
(Standard RS-232-C)
Baud rate ............... 110 to 9600 baud
Format
Data bits .............. 7 or 8
Parity ..
. . even, odd, or none
Stop bits.
. . 1 or 2

POWER REQUIREMENTS
Operating Voltage. .
.115,230, 100 VAC
(See Ordering Information) +5V, or +9 to +36V dc (optional)
Power Consumption
AC Models ............ 2.5 W typical, 4 W max.
DC Models ............ 385 mA @ 5V dc

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

10-119

PM·5060
ANALOG OUTPUT

PM-5060 SERIAL COMMUNICATIONS

The PM-5060 has an optional analog output which outputs a
voltage or current in proportion (or inverse proportion) to the
temperature reading. The output is suitable for simple control
applications (e.g., heater control) or to drive external measuring devices such as strip chart recorders.

A standard feature included in the PM-5060 is an RS-232-C serial communications port. The PM-5060 may operate as a DTE
or DCE device, depending on the connection scheme used
from the J1 connector to a typical D-type connector.

An on-board 12-bit D/A converter provides a 0 to 10V dc or 4 to
20 mA output. The temperature range for the output is programmable from either the front panel or the serial communications
port. The on-board microprocessor performs the required D/A
output scaling.

PM-5060 MENU DESCRIPTION
The PM-506D is operable from the both the front panel keypad
and the serial communications port. The front panel keypad
consists of four key~: MENU SELE<;:T, UP ARROW, DOWN
ARROW, and ENTER. Table 2 shows the menu structures. The
menus are interactive, with the process parameter appearing
directly on the display. The MENU select key scrolls through the
menus available at each level and the ARROW keys scroll
through options available for each parameter selected. The
ENTER key locks the value for the selected parameter.
The serial communications menu also allows enabling a data
output mode. In this mode, the PM-506D continuously outputs
a data message to a printer at a user-selectable rate. The data
message consists of information on the monitor configuration,
status of setpoints, and input data.
Table 2. PM-5060 Front Panel Menu Options

Menu

Menu Selection Parameter Selection
Choice
Choices

Security Code

See Notes

Enable/Disable

Input

RTD, American
RTD, European

Alpha
Alpha

Thermistor

2252Q
3000Q
5000Q
10000Q

Unit

Degree C or Degree F

Resolution

O.I°C or 1.0OC

1-4

User-selectable

Hysteresis

Up to 25°

Baud rate

110,300, SOO, 1200,
2400, 4800 and 9S00

Parity

Odd, Even, or None

Setpoint
Serial
Communications

Self-test

= 0.00391
= 0.00385

Stop bits

lor 2

ID number

othrough 99

Set data output
rate

Multiples of O.S Sec.

The host may issue three types of commands to the monitor:
configuration commands, data acquisition commands, and diagnostic commands.
.
Configuration commands: These commands set the
PM-5060 to the user-selected operating mode. The monitor
responds to the commands either with an acknowledge
character or by echoing the command message back to the
source.
Data acquisition commands: These commands read and
log in temperature data and the status of the monitor. The monitor responds with a fixed format ASCII message. The reply
message consists of an ASCII string containing the monitor's
ID number, RTDlthermistor data and status, the status of the
monitor configuration, and checksum. The data acquisition
commands also operate in a continuous mode. In this mode
the PM-5060 sends data, status, and checksum to the host
system at a user-selectable rate.
DiagnostiC commands: These commands test the PM-5060
display, perform calibration, read RAM locations, read reference voltage values, and check the result of built-in self test
routines. Table 3 lists some command descriptions.

Table 3. PM-5060 Command Descriptions (partial list)

Command
lYpe
Configuration
Commands

NDand D/A

D/A output

Zero and Full·scale

NOTES: The PM-5060 uses three different security codes for
the following:
1. Enabling the security to prevent front panel
tampering.
2. Enabling the calibration mode to calibrate the
meter.
3. Disabling the security to change monitor settings.

Description
Set input type
Set temperature unit (OC or OF)
Set resolution (0.1 or 1.0)
Set/Read setpoints' values
Set/Read hystereSis value
Set/Read D/A scaling values
Transmit data in decimal or hex format
Transmit to host temperature measured

Data Acquisition
Commands

Trans mil to host last 50 data samples with
status
Transmit to host the PM-50S0 status
Enable/Disable command echo
Enable/Disable terminal emulation mode
Enable/Disable reply messages on setpoint
conditions
Set reply message format
Send temperature data to host
Output digital data to D/A section

Diagnostics
Command

Test display segments
Perform calibration
Read internal reference values
Read raw temperature value
Perform self test

Diagnostics

Calibration

10-120

The monitor receives configuration information and process
parameters via the serial port, using conventional ASCII message formats. The monitor is configurable for different baud
rates, parity, stop bits and ID number using the front panel keys.
The monitor supports over 50 simple ASCII commands usable
via the serial port for data acquisition and control.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194iTEL (508) 339-3000iTLX 174388/FAX (508) 339-6356

PM·5060
TWO-, THREE-, and FOUR-WIRE RTDCONFIGURATIONS

PM-5060 INPUT/OUTPUT CONNECTIONS

The PM-5060 accepts inputs from a variety of commercial RTD's
and thermistors. The device operates with varying degrees of efficiency based upon the way the input signal is brought into the
monitor. Figure 2 shows how inputs may be connected using
two-, three-, or four-wire schemes. Each scheme has its advan,
tages; the user must weigh accuracy versus economy when
designing their configuration.

The PM-5060 uses terminal blocks TBl and TB2 for RTDI
thermistor inputs and power connections respectively. The setpoint outputs and serial communications are provided on the Jl
connector. Tables 4 through 7 show pinouts for 1/0 and power
connections.
Table 4a. Setpoint Output Connections (Jl):

NOTE: When using a thermistor sensor, a 400Q resistor rnust
be installed externally across the RTD+ and RTDinputs.

Setpoint
SP-1

Connections

SP-2

A1
A2

SP-3

B4
B5

SP-4

A4
A5

FIELD : PM-5060
I

I
I

~-----t RTO'-"V\"v----;

GROUND

Re,

e)
e)

Table 4b_ RS-232-C Connections (Jl)

-MOST ACCURATE

Figure 2a. Four-wire Input Configuration
I

FIELD [ PM-5060
I
I

T81

Re,

~-----t ROT -.

0

' - " V \ / V - - - - ; GROUND

(2)4

B1
B2

Signal
TXD

Connection
B21

RXD

B20

CTS

B18

RTS

B19

DTR

A16

GND

B16

+5Vdc

A6

Table 5. AC Power Supply Connections (TB2)
Re,

Signal

-MORE ECONOMICAL,
ASSUMES THAT Re, = R.,

Figure 2b. Three-wire Input Configuration

GROUND
115i230i100V AC Hot
11Oi230i100V AC Neutral

Connection

TB2-1
TB2-2
TB2-3

I

FIELD: PM-5060
I
I

~~~=~~T 0
r--'VIIv---+--i

RTO+

1

(Z/

ROO

,
f--d~
-MOST ECONOMICAL
-LEAST ACCURATE
-ERROR PROPORTIONAL TO OISTANCE d
-SIMILAR TO 4-WIRE CONFIGURATION,
BUT Re, AN D Re, NOT FACTORED OUT.

Table 6_ DC Power Connections (TB2)

Signal
+5Vdc
+9to +36V dc
GROUND

Connection
TB1-1
TB2-2
TB2-3

Table 7. Input Connections (TB1)

Signal
CURRENT SOURCE
RTD +
RTD GROUND

Connection
TB1-1
TB1-2
TB1-3
TB1-4

Figure 2c. Two-wire Input Configuration

DATEL, Inc_ 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

10-121

PM·5060
PM-S060 MECHANICAL DIMENSIONS
The PM-5060fits into standard 1/8 DI N panel cutouts. Mounting
procedures involve tightening two screws through a metal

bracket against the front panel. Figure 3 shows the mechanical
dimensions of the monitor.
118 DIN CUTOUT

~(~~~~

T

II

5060 RTD

a.EL

2.08
menu

enter

V

1

'"

3.622-

+ 0.032
- 0.000 (92mm

+

0.81\

-0.00 )

GAIN
ADJUST"

JI

I:

OFFSET
ADJUST"

"AVAILABLE ONLY WHEN
ANALOG OUTPUT OPTION
IS INSTALLED.

6.0

............

~

0

~

-I

5.47

~I
~

~S

Figure 3. PM-S060 Mechanical Dimensions

ORDERING INFORMATION

o

PM-SOXO-

~~~~~~~:~~ 5~

T

·Strain Gage 7

Voltage/Current 8

POWER SUPPLY
[A =
E =
J =
D =

110VAC
230VAC
100vAe
SV dc or
+910 +36V dc

ANALOG OUTPUT
0= No analog ouput
1 = One analog output, 4 • to - 20mA or

COMMUNICATIONS MODE

0lo10V

0= RS-232-C
1

= 20mA current loop·

2 = RS-422148S"
SETPOINTS

1 = 4 set point outputs (standard)

(IOomA.300V)
"TO BE ANNOUNCED

DATEL warrants Ihis product 10 be free of defects in material and workmanship for a period of one year from Ihe date of shipmenl, under normal use and service. DATE!:s obligations under this warranty are limited to replacing or repairing the product, at its option, at its factory or facility. The defective product must
be shipped to DATE!:s facility for repair or replacement within the warranty period, transportation and charges prepaid. This warranty shall not apply to a product
which has been subjected to misuse, negligence, or accident. In no case shall DATE!:s liability exceed the·original purchase price. The aforementioned provisions do not extend the original warranty period of this product which has either been repaired or replaced by DATEL.
NOTE: Equipment sold by DATEL, Inc. is not intended to be used, nor shall it be used, as a "Basic Component' under 10 CFR 21 (NRC).
Should this equipment be used in or with any nuclear installation or activity, you will indemnify us and hold us harmless from any liability or damage whatsoever
arising out of the use of the equipment in such a manner.

10-122

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

PM-5070
STRAIN GAGE INPUT
INTELLIGENT PROCESS
MONITOR/CONTROLLER
FEATURES
Two bipolar signal inputs plus a precIsion excitation output for strain gage and other bridgetype applications
• Four MOFSET setpoint outputs (300V/100 mA
load) and optional analog output for control applications
• 72 Commands to set control schemes, transmit
data, perform bridge calibration and scaling, set
communications protocol, and initiate diagnostic
routines
Microprocessor-based, with all operating parameters set through the front panel (or remote
host) and stored internally in non-volatile EEPROM memory
• Easy-to-use scaling function converts bridge
output to engineering units for display

Interfaces easily with serial-input printers, or
logs data directly to computer disk via the serial
communications port

• Two powerful math functions permit sophisticated input manipulation and advanced control algorithms

Adjustable sample rate with optional averaging

Cyclical 5-digit display of up to eight system
variables, including input PEAKS and VALLEYS
• Displays standard or user-defined engineering
units
Stand-alone, or operation via standard RS-232-C
communication interface (RS-485 optional)

• Security feature prevents front panel tampering
• Screw terminal connectors for easy power and
signal connections
Menu-driven calibration procedure requires no
potentiometer adjustments; continuous automatic gain and offset calibration
• Compact 118 DIN case fits standard panel
cutouts

DATEL's PM-S070 provides all the functions necessary for precision bridge measurement, including excitation output, input scaling,
and the toughness to withstand harsh industrial enviroments. The PM-S070 goes beyond simple measurement. With two signal inputs, four setpoint outputs, optional analog output, and two powerful math functions, the PM-S070 is equipped to handle even demanding control applications. When combined with a host computer the PM-S070 forms a full-function operator station for real-time
process monitoring and control, data archiving, and statistical analysis--all at a fraction of the cost of large dedicated systems.

GENERAL DESCRIPTION
The PM-S070 consists of six functional sections: an isolated
analog input section excitation circuit, microprocessor and
control logic, front panel keyboard and display, serial communciations port, and setpoint outputs. A seventh section, analog
output, is optional. Figure 1 is the block diagram of the PM5070.
The isolated analog input section consists of multiplexing circuitry, signal conditioning pre-amplifiers, and a voltage-tofrequency converter. The multiplexing circuitry arbitrates between the two signal inputs. Both input channels are true differential, with INPUT 1 offering a ±50 mV full-scale range and INPUT 2 providing ±10 V. Typically, INPUT 1 is used for the
bridge input, while INPUT 2, operating ratiometrically, is used
as the excitation reference input. For applications requiring
only a single input, multiplexing may be disabled and faster
sample rates obtained. The single channel sample rate can be
set to 100 ms, 200 ms, 300 ms, or 400 ms; multiplexed rates
are 200 ms, 400 ms, 600 ms, or 800 ms.

The analog input section is isolated up to IS00V RMS from the
control logic and power lines. A common mode rejection ratio of
140 dB ensures accurate readings in the presence of environmental noise and ground loops. Typical accuracy is 0.01%
over the full-scale range.
The excitation circuit utilizes a preCision reference coupled
with an amplifier to generate a +10 V excitation output. The
output can drive up to a 30 mA, more than enough for bridge excitation or to power other types of external sensor circuitry.
The microprocessor and control logic provide the system timing
used to convert the V/F output to an equivalent digital value.
This section also processes commands received via both the
front panel and the RS-232 serial communication port. The microprocessor accesses operating software contained in PROM
memory, while user-defined operating parameters are stored in
EEPROM and are automatically retrieved on power-up.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

10·123

II'

I

I,

PM-5070

DIGITAL lOGIC
FRONT PANEL DISPLAY
CLOCK

~
EEPROM
CPU
ADDRESS
DECODER

A

r-r-

...
----v

1/0 AND
TIMER
CONTROL

OISPLAY
DRIVE

t ...............

(~

A

...

-

D

R8-232-C

MUX

IISOLATIONI

7

ANALOG INPUT

12-91T
DIA
OUTPUT

SERIAL
PORT

OJ OJ ~NTE~

VIF
If--CONVERTER

II SOLATION

'i

VACUUM
FLUORESCENT DISPLAY

~

SET POINT
OUTPUTS

~

~RR!

ANALOG OUT

SP-1 SP-2 SP-3 SP-4

I

I

OUTPUT

INPUT 1

I--

INPUT 2

I--

INPUT 2

INPUT 1

I
PRECISION
REFERENCE

EXCITATION+
EXCITATlON-

+5Vdc_
+15Vdc_
+12Vdc-12Vde_

(SEE NOTE)

I-I--

ISOLATOR
POWER
SUPPLY

-Q:

+30V de
3.3 VAC - - " ' -_ _ _ _--'

NOTE: The optional analog output is user-configurable for 4-to-20 rnA or 0 to + 10V dc.
Figure 1.

PM-S070 Block Diagram

A major feature of the PM-5070 is the easy-to-use front panel
keypad. During set-up and parameter selection, the MENU
and ENTER keys are used to traverse a hierarchical menu
structure which prompts the user for operating parameter
values. The two arrow keys are used to scroll through the
choices for a particular parameter, or in some cases, to ramp a
numeric value to the required setting. If desired, the keypad
can be disabled and operating parameters entered through
the serial port using simple ASCII commands.
During set-up, the six-character alphanumeric display
presents menu choices and parameters using easy to remember mnemonics. During operation, the readout displays up to
five digits of numeric data plus engineering units. The display
also features six annunciators: four for indicating setpoint status and two for calibration parameters (full-scale and zero).
Another unique feature is the ability to alternately display up to
eight system variables. When used in this mode, each of the
selected variables displays for approximately two seconds.
The PM-5070's RS-232-C communication port connects
directly to any host computer with similar interface (e.g. IBM
PC/XT/AT or compatible). Commands and parameters can be

10-124

read/set at the host computer. In addition, data can be sent
from the PM-5070 to the host for storage and analysis. The port
is full duplex with handshake, and can be configured as DTE or
DCE_ The port supports baud rates ranging from 110 to 9,600
baud, one or two stop bits, and odd, even, or no parity.
The PM-5070 provides four opto-isolated setpoint outputs
which respond to user-defined setpoint limits. A setpoint can
be associated with any of the eight system variables (INPUT 1,
INPUT 2, PEAK 1, PEAK 2, VALLEY 1, VALLEY 2, FUNCTION
1, or FUNCTION 2)_ Further, each setpoint is assigned a trip
direction (high-or low-going) and a hysterisis (dead band) value_ The setpoint outputs are fully isolated MOSFET relays
able to drive 100 mAl 300V loads. The outputs can be used in
to trip alarm systems or in discrete control applications.
The PM-5070's optional analog output section consists of a
precision 12-bit D/A converter which is user-configured to output either 0-10V or 4-20 mAo The output value can be set
through the serial port or controlled proportionally by either INPUT 1, INPUT 2, FUNCTION 1, or FUNCTION 2. Controlling
the output with a function allows implementing sophisticated
control algorithms such as PI and PD.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

PM-5070
FUNCTIONAL SPECIFICATIONS
(Typical at 25°C, 300ms conversion rate unless noted)
ANALOG INPUTS
Conversion Technique .... Voltage-to-Frequency
V/F Resolution ................ 30,000 counts
Input 1 Range ................. ±50 mV
Input 2 Range ................. ±10V
Input 1 Accuracy ............ 0.01 % of full-scale
Input 2 Accuracy ............ 0.01% of full-scale
Conversion Time ............. User-selectable: 100 mS,200 ms,
300 ms, 400 ms (single channel)
Range Tempco ................ ± 20 ppml °C typical
± 50 ppml °C maximum
Stability .......................... Automatic gain and offset
calibration every minute
Input 1 Impedance .......... l00 M ohms
Input 2 Impedance .......... 100 K ohms
Common Mode Voltage ... 1400 VAC peak@ 50 - 60 Hz
Common Mode Rejection 140 dB to 100 Hz
Normal Mode Rejection ... 80 dB min @ 50 - 60 Hz
Over Voltage Protection 130V RMS maximum
EXCITATION
Voltage ............................ +10V dc
Load Current ................... 30 mA max
Accuracy ......................... ±1.0%
DISPLAY

SERIAL COMMUNICATIONS
Protoco!... ....................... RS-232-C, full duplex
(standard)RS-485/422 (optional)
Baud Rate ....................... User-programmable: 110 - 9600
Baud
Data Bits ......................... 7 or 8
Stop Bits ......................... 1 or 2
Parity .............................. Even, odd, or none
ANALOG OUTPUT (OPTION)
Control Source ................ INPUT 1, INPUT 2, FUNCTION 1,
FUNCTION 2, or serial port
Mode ................................ User-configured: voltage or
current
Voltage:
Range ...................... 0 -10V (2 mA max)
D/A Resolution ........ 12 bits
Non-linearity ........... ±0.1%
Gain Tempco ........... 0.1 mV/oC
Offset Tempco ........ 20 ppm/oC
Current:
Range ...................... 4-20mA
Compatibility ........... ISA type U
Excitation ..... ....... ... Internal or external
Accuracy ................ 0.1% of full-scale range
Load Resistance ..... l00 Ohm, minimum; 1000 Ohm,
maximum
PHYSICAL

Case Material... ............... High-impact, flame retardant
polycarbonate
Case Dimensions ............ 1/8 DIN cutout:
Width: 3.622" (92 mm)
Height: 1.772" (45 mm)
Depth: 5.47" (138 mm) w/o
terminals
6.00" (148mm) w/terminals
Bezel Dimensions ........... Depth: 0.35" (9 mm)
Width: 3.96" (101 mm)
Height: 2.08" (53 mm)
Front Panel Keypad ........ Membrane with 4 key switches
Weight ............................. 1.32 Ib (0.6 Kg)
Power .............................. 90-110VAC, 50 Hz
SETPOINT OUTPUTS
(PM-5070-1 XXOJ)
104 -126 VAC, 60 Hz
Number ............................ 4
(PM-5070-1 XXOA)
Control Source ................ INPUT 1, INPUT 2, PEAK 1, PEAK 2,
207 - 253 VAC, 50 Hz
VALLEY 1, VALLEY 2, FUNCTION 1,
(PM-5070-1 XXOE)
FUNCTION 2, or serial port
2.5 Watts typical, 4 Watts
Trip Direction .................. User-programmed as high- or low-going
maximum
Hysterisis Range ............ O-100%
Output Type .................... Opto-isolated MOSFET
ENVIRONMENTAL
Isolation ......................... 1500VRMS
ON Resistance ............... 25 Ohm
Operating Temperature Range
Output Rating ................. 300V, 100 mA continuous
Rated Accuracy ....... 32 to 140 OF (0 to +60 DC)
Reduced Accuracy .. 5 to 158 OF (-15 to +70 DC)
Storage Temp. Range ..... -91 to 185 OF (-40 to +85 DC)
Relative Humidity ........... 0 to 90% non-condensing

Type ................................ 14-segment, alphanumeric,
blue-green vacuum flourescent
Number of Characters .... 6 alphanumeric (5 digits plus engineering units)
Character Height ............ 0.38"
Annunciators .................. 4 setpoint status indicators;
zero and full-scale indicators
Variables Displayed ....... 1 to 8 variables displayed
alternately at 2 second intervals
(INPUT 1, INPUT 2, PEAK 1, PEAK
2, VALLEY 1, VALLEY 2, FUNCTION 1, FUNCTION 2)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-125

II

PM·5070

o = Numeric value required
•

'" Parameter selection required

L-_ _Je

Figure 2: PM-S070 Menu Flow Chart

PM-S070 MENU
The PM-5010's powerful software provides capabilities and
flexibility unmatched by conventional panel instruments. The
12 built-in software commands:

buttons, or at a host computer connected to the meter through
the serial communications port.

• Specify data acquisition and display parameters
• Define input scaling
• Define setpoint and analog output characteristics
Create custom math functions
• Configure the serial communication protocol
• Specify data transmission parameters
• Let the uSer calibrate and diagnose the unit

When configuring the PM-5010 from the front panel, the
MENU and ENTER keys are used to scan a hierarchical menu
structure. Menu items display as easy-to-understand mnemonics (or entire words) on the alphanumeric readout. At the
uppermost menu level there are seven menu items: SECURITY CODE, INPUT, SETPOINT, OUTPUT (if the analog output
option is installed), SERIAL, DISPLAY, and SELFTEST. Each
major menu contains submenus, and each submenu presents
the parameters needed to complete the configuration. Figure
2 depicts the menu structure.

Commands are issued and parameters entered in one of two
ways: either directly at the monitor using the four front-panel

10-126

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

PM-5070
Security Code Menu

Upon entering this menu the user is immediately prompted to
enter one of five security codes. The codes, when correctly
entered, allow the user to:
•
•
•
•

Reset peak, valley, and math function variables
Change operating parameters
Calibrate the meter
Set the sampling rate
Specify input scaling parameters

Input Menu

Using this menu, the user identifies the nature of each input
signal and defines how the value of the signal will appear.
Specified parameters include:
• Input is enabled/disabled
• Input is scaled/used ratiometrically
Sample averaging (1 to 10)
Engineering units displayed
Decimal point location

MATH FUNCTIONS
One of the most powerful features of the PM-5070 are the two
user-configurable math functions. The two functions have the
generalized form:
[[(Cl x Sl)

~VAR11

OPl [(C2 x S2) x VAR211 OP2 (C3)

Where:
Cl, C2, C3 = numeric constants
Sl, S2 = scaling factors
VAR1, VAR2 = anyone of the eight system variables
OP1, OP2 = an arithmetic operator: +, -,x,/
The constants, scale factors, variables, and operators constituting the function are specified either from the front panel
(within the INPUT menu), or from a host computer connected
through the serial port.

The INPUT menu also gives the user the opportunity to define
one or two custom math functions to manipulate system variables for display or control output.

During operation, the value of a function is calculated at the
monitor's sample rate. This value can be displayed and/or
used to control setpoint or analog outputs. Because of their
flexibility, the two functions may be used in a variety of ways:
for engineering units scaling, as control algorithms, or for combining inputs to calculate other physical process variables.

Setpoint Menu

SERIAL COMMUNICATIONS

This menu allows the user to define, in turn, each of the four
available setpoint outputs. For each setpoint the user specifies:
The source which controls the output (INPUT 1, INPUT 2
PEAK 1, PEAK 2, VALLEY 1, VALLEY 2, FUNCTION 1, or
FUNCTION 2)
Setpoint limit
• Hysterisis
Trip direction
Output Menu

This menu is only available when the analog output option is installed. When available, the menu allows the user to define:
• The source which controls the output (either INPUT 1, INPUT
2, FUNCTION 1, or FUNCTION 2)
The zero and full-scale limits of the controlling source
Serial Menu

Using this menu the user defines the protocol used in communications through the serial port. Parameters specified include:
• Baud rate (110 to 9,600)
• Number of stop bits
Odd, even, or no parity
Meter ID number (required for multidrop applications)
• Transmission rate ~or logging data to a printer

A standard feature of the PM-5070 is an RS-232-C serial communications port. Using this port, the PM-5070 can be connected to a host computer or PLC having a similar interface.
Any configuration parameter which can be set using the meter's front panel can alternatively be set by issuing a simple
ASCII command from the host computer. Additionally, the host
can read the current meter status, log data, and directly control the setpoint and analog outputs.
PM-5070 commands all conform to a simple ASCII format and
can be incorporated into any structured language program. As
an example, the command to change the trip limit of setpoint
number 4 to 500 is: WSP 4,500

TYPICAL STRAIN GAGE INTERFACE
Figure 3 illustrates a typical strain gage interface. The bridge
output is connected to the PM-5070's INPUT 1 connections,
while INPUT 2 is used to measure the excitation voltage. In
this configuration INPUT 2 is used ratiometrically, meaning·
that the monitor will adjust the INPUT 1 reading to compensate
for any variations in the excitation source. Ratiometric operation is specified through the front panel or with a serial port
command.

Display Menu

With this menu the user specifies which of the eight system
variables are to be displayed alternately at two second intervals.
Self test Menu

This menu provides access to a series of diagnostic tests
which verify the integrity of the display segments and the meter's internal circuitry.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-127

PM·5070
PM-5070

INP1+

~~
________~r-'~-----~---~--'~~~

INP11'8 DIN CUTOUT

~-'1'-----J..n

-.:---------------------1'---.cj

INP2+

ItwEL

INP2-

F"~

EXC-

Figure 3.

GAIN'
ADJUST

Strain Gage Interface

T

OFFSET'
ADJUST
@

1771

_I ,!e000'iu@

I

~

ORDERING INFORMATION

PM-S070·1 - ,
COMMUNICATIONS
0= RS - 232·C
1 = RS • 422/48S"

'"

3.622---1

0.81)
( 92mm +
-0,00

5.47

I:

6,0

1F

. · .3

--j ~'

A = 110VAC
E = 230 VAC
J = 100VAC
D = SVDC"
TB-l

ANALOG OUTPUT

'POWER CORD NOT INCLUDED

')

Figure 4. Mechanical Dimensions

POWER'

0= NO ANALOG OUTPUT
1 =ONE ANALOG OUTPUT;
4-20mA,0-10V

'I

- 0.000

NOTE GAIN AND OFFSET ADJUSTMENT POTENTIOMETERS
ARE AVAILABLE ONLY ON MODELS HAVING THE
ANALOG OUTPUT OPTION,

0 -,

~--...,

I---

3_622" + 0,032

I

IL _ _

EXC+

L:JI(:,:: ~~~;

T

5070SG

I

0

I

0

INP1+

I

INP1·

8

I

INP2+

1m
TB-l

CD

I

INP2-

0

I

EXC+

8

I
EXC-

GND AC HOT AC NEUT

"CONSULT DATEL FOR AVAILABILITY

Figure 5:

Signal/Power Connections

WARRANTY
DATEL warrants this product to be free from defects in material and workmanship under normal use and service for a period of one
year from the date of shipment. DATEL's obligations under this warranty are limited to replacing or repairing the unit, at its option, at
its factory or facility, when the unit is returned to DATEL's facility, transportation charges prepaid, and which is after examination disclosed to the satisfaction of DATEL to be thus defective, This warranty shall not apply to any such equipment which shall have been
repaired or altered except by DATEL or which shall have been subjected to misuse, negligence, or accident. In no case shall DATEL's
liability exceed the original purchase price. The aforementioned provisions do not extend the original warranty period of any product
which has either been repaired or replaced by DATEL.
NOTE: Equipment sold by DATEL, Inc. is not intended to be used, nor shall it be used, as a "Basic Component" under 10 CFR 21
(NRC).
Should this equipment be used in or with any nuclear installation or activity, the Purchaser will indemnify Datel, Inc. and hold Datel,
Inc. harmless from any liability or damage whatsoever arising out of the use of the equipment in such a manner.

10-128

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

PM-5D8D
VOLTAGE/CURRENT INPUT
INTELLIGENT PROCESS
MONITOR/CONTROLLER
FEATURES
• Two signal inputs, four MOSFET setpoint
outputs (300V/100 mA load) and one analog
output for control applications (optional)
• 72 Commands to set control schemes, transmit data, perform calibration and scaling,
set communications protocol, and initiate diagnostic routines
• Microprocessor-based, with all operating
parameters set through the front panel (or
remote host) and stored internally in
non-volatile EEPROM memory
• Easy-to-use input scaling function
• Two powerful math functions permit sophisticated input manipulation and advanced control algorithms
Cyclical 5-digit display of up to eight system
variables, including input PEAKS and
VALLEYS
Displays standard or user-defined engineering units
• Stand-alone, or operation via standard
RS-232-C communication interface (RS-485
optional)

Interfaces easily with serial-input printers, or
logs data directly to computer disk via the
communications port
• Adjustable sample rate with optional averaging
Security feature prevents front panel
tampering
• Screw terminal connectors for easy power and
signal connections
• Menu-driven cal.ibration procedure requires no
potentiometer adjustments; continuous automatic gain and offset calibration
• Compact 1/8 DIN case fits standard panel
cutout

DA TEL's PM-50BO Intelligent Process Monitor represents a new generation of microprocessor-based, panel-mounted instrumentation. The PM-50BO offers two voltage/current signal inputs, four programmable setpoint outputs, and an optional analog output. Powerful user-defined math functions make the PM-50BO easily adapted to a wide variety of process monitoring and control
applications. When combined with a host computer, the PM-50BO forms a full-function operator station for real-time process
monitoring and control, data archiving, and statistical analysis - all at a fraction of the cost of large dedicated systems.

GENERAL DESCRIPTION
The PM-SOBO consists of five functional sections: an isolated analog input section, microprocessor and control logic,
front panel keyboard and display, serial communciations
port, and setpoint outputs. A sixth section, analog output,
is optional. Figure 1 is the block diagram of the PM-SOBO.

one 0-10V input. For applications requiring only a single
input, multiplexing may be disabled and faster sample
rates obtained. The single channel sample rate can be set
to 100 ms, 200 ms, 300 ms, or 400 ms; multiplexed rates
are 200 ms, 400 ms, 600 ms, or BOO ms.

The isolated analog input section consists of multiplexing
circuitry, signal conditioning pre-amplifiers, and a voltageto-frequency converter. The multiplexing circuitry gives the
user a choice of two input pair combinations: one 0-100 mV
input and one 0-1 OV input, or one 0-20 mA current input and

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-30001TLX 174388/FAX (508) 339-6356

10-129

PM-SOBO
DIGITAL LOGIC
FRONT PANEL DISPLAY
CLOCK

~
EEPROM
CPU
ADDRESS
DECODER

1/0 AND
TIMER
CONTROL

A

~r-v

DISPLAY
DRIVE

Ilk

VACUUM
FLUORESCENT DISPLAY

co CD rNTE~

8

A

""

;

1~

V/F
CONVERTER

IISOLATION

.---<
SERIAL
PORT

D

R5-232-C

t

12-61T

CURRE NT IN
INPUT 1 HI
INPUT 2 HI
INPUT 1 2
LO/CU RRENT RTN

ANALOG INPUT

SETPOINT
OUTPUTS

DIA

OUTPUT

~

rr-

I--

[ISOLATION]

7

I--

MUX

ANALOG OUT
(SEE NOTE)

l~~!_

SP-1 SP-2 SP-3 SP-4

OUTPUT

+5Vdc_
+15VdcISOLATOR
+12VdcPOWER
SUPPLY
-12Vdc_
+30Vdc_
3.3 VAC - - 1 - -_ _ _ _..J

-PR). Programs may be run under breakpoint and/or trace con·
trol. The Monitor also includes several AID diagnostic com·
mands to aid in calibration or hardware troubleshooting. A list
of monitor command functions appears in Table 2.
Table 2. Summary of Monitor Command Functions
Monitor Commands
ReadlWrite CPU or memory registers.
Display memory block in hexadecimal and ASCII.
Fill memory block with a constant.
Set or display breakpoint.
Trace one or more instructions.
Start execution until optional breakpoint.
Turn Executive ON or OFF (enable/disable DPR commands).
Transition to/from Executive or Monitor.
Auxiliary serial port download.
Start AID sampling to serial port.

Executive Commands
The Executive accepts commands and optional parameters
through the DPR. A major benefit of the Executive is a uniform
sequential list method of passing subroutine parameters. User
programs may also use this syntax or may develop their own
parameter'passing method in another part of the DPR. If the
user's serial port terminal is connected, the execution of Execu·
tive Function Blocks may be analyzed at the Monitor level. The
Executive also traps non·executable subroutine addresses by
performing a soft reset.

The Executive allows for repeating or alternating blocks of
sequential subroutines. They may be selected once, N num·
ber of times, or until stopped by the host. The DPR Download
is one of the Executive commands. Most of the subroutines
available through the Executive manage the data acquisition
section. Table 3 lists the functions of executive commands
available.
Speed by Architecture
The primary difference between the DVME-601 smart AID
board and "dumb" AID boards is the increased total system
throughput achieved by offloading the host. This is a result of
simultaneous AID scanning and concurrent host processing,
plus using the DPR as a programmable buffer. Even greater
system bandwidth may be possible by having the DVME-601
do arithmetic pre·processing of AID blocks, delivering final
results rather than raw input data.
Figure 2 shows the wasted idle times in the host for dumb AID
boards because an interrupt, polling, or DTACK' delay must
occur with each sample.
The interrupt processing takes many microseconds to save
stacks and registers and arbitrate with the Real Time Operat·
ing System. To realize the full speed of a dumb board, the host
must be fully dedicated to data acquisition, leaving no time for
. non·AlD tasks. With fast converters and high bandwidth inputs,
the short sample intervals make it inefficient to run the host in
an interrupt mode, thereby locking out other host software tasks
during data acquisition. The typical lack of memory on dumb
boards for sample storage also means that the last sample is
saved in the AID converter and new sampling cannot start until
the old sample is read.
The DVME-601 efficiently runs long blocks of thousands of
samples, allowing ample time for host disk and display activity
between blocks.
DUMB AID BOARDS

Executive Commands
Select the memory destination address of AID scans as either
local RAM, single DPR or swapped DPR buffers.
Select the source of AID start triggers as external TIL, local
timer, last AID read or host command.
Select AID triggering per conversion or per scan.
Select channel address sequencer to increment or not after
each conversion.
Select start/final sequential channel addresses.
OVMEoo601 SMART AID BOARD

Select timer channel, period and control.
Transfer AID scans from local RAM to DPR (after data pre·
processing by a user·downloaded program).
Define whether scan transfers will wait for host Ready status
or transfer without waiting.

DVME-601

Select how scanning will stop (N samples, N scans, buffer full,
stop by host).
Download S records via DPR or auxiliary serial port and flag
checksum errors but do not start execution.
Load subroutine addresses or function command block with
optional parameter list and await execution.
Execute previously loaded commands or subroutine(s).
Memory block transfer.

11-6

HOST

HOST IS FREE ~. DISK. DISPLAY,

Figure 2. Speed by Architecture

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA.02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

DVME·601
110 SIGNALS AND CONNECTIONS

A settling delay control line output from each MUX board will
delay the actual AID conversion to synchronize settling times
of low-level pre-amplifiers on the MUX slave boards. Through
appropriate host AID software, board addreSSing and input
range selection, it is even possible to mix high- and low-level
expansion input boards on the same bus.

AID Channel Expansion Bus
(Please refer to the Channel Address Map, Table 4)
The DVME-S01's J3 front panel connector accepts a flat cable
assembly, such as DATEL Part Numbers DVME-C-Q1 or DVMEC-Q2, to form a channel expansion bus. The cable assembly
plugs into DATEL:s slave multiplexer boards installed in slots
adjacent to the DVME-S01 or in a nearby VME chassis. Available DATEL channel expansion boards include:

Figure 3 shows how a DVME-601 Coprocessor board physically
links to DATEL:s slave multiplexer boards and field equipment.
Table 4.

Analog Channel Expansion Address Map
($FFh)

• DVME-S41 A 32 Single-endedl1S Differential channel highspeed MUX;

Unused addresses

• DVME-S43 An 8 Differential channel low-level isolated MUX
(for sensors such as thermocouples, RTD's,
4-20 mA loops, etc.); and,

Expansion MUX Board N
:
:
Expansion MUX Board 2

• DVME-S45 A 1S Single-ended/8 Differential channel simultaneous sample/hold MUX.

Expansion MUX Board 1
DVME-S01 1SS/8D Channels

The DVME-S45 is especially suited to array processing and
DSP applications. This channel expansion bus allows the
DVME-S01 to directly control each slave MUX board and carries three classes of signals. They are:

($OFh or $07h)
($00)

Input/Output Connections
Figures 4, 5, and S show the signals present on the DVME-S01's
J1, J2, and J3 connectors respectively. The connectors are
dedicated as follows:

1. Eight-bit channel address outputs from the DVME-S01's
address register, offering up to 25S total channels. This
autosequencing register is software-controlled by the user's
host program or DVME-S01 firmware.

J1
J2
J3

2 . Buffered high-level switched differential analog signals into
the DVME-S01's instrumentation amplifier.

Local Analog Inputs
Multifunction Peripheral 110 Signals
Analog Channel Expansion Bus

3. Control and handshake lines, an external AID start trigger,
and grounds.
Channel addresses are distributed to all MUX boards along the
bus. The first 8 or 1S addresses are for local DVME-S01 channels. Address selection logic and base
address switches on each MUX board
allows it to respond to a range of
addresses. All other de_selected boards
disconnect their analog outputs from the
bus until addressed. For diagnostics,
each MUX board has a LED lamp which
turns on when that board is addressed.
J2 SERIAL PORT.
TIMERJCOUNTERS,
DATEL offers 2- and 3-connector cables
IlOanS,AlD
TRIGGER, """".u,,,---+[
to connect one or two slave MUX boards
and users may fabricate flat cables for
connecting up to 10 boards.

REMOTE nL TRIGGER INPUT

~----I--~~~~~~NG EXPANSION CABLE

JllOCAl

One of the control lines on the expansion
bus is a TTL-compatible, open-collector
AID trigger. This lets the DVME-S01's AID
start input be initiated from the trigger input on any multiplexer board. A Single
external event hardware trigger will start
either one AID sample and host interrupt
or a scan of channels and interrupt on
one or more boards. Alternatively, automatic channel sequencing and AID conversion may be started from a DVME-601
timer by jumpering the timer output to the
trigger input on the J3 connector. Software commands from the host will also
start the AID conversion process.

ANALOG INPUTS

H-___-;__ ~~~t~~~~~':'NSIONCHANNEL

OPTIONAL USER'S

TERMINAL 0l=I
COMPUTEATO

DEVELOP PAOORAMS

<'--_ SIGNAL
OVME-691 SCREW TERMINATOR
CONDITIONING PANEL

Figure 3. Front Panel Cabling and
Wiring Connections

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

II
11-9

~~[L

DVME·601
J1

J2

(VIEWED FROM FRONT OF BOARD)

SIGNAL GROUND
CHANNel 0 HI
CHANNEL 9 HIf1 LO
SIGNAL GROUND
CHANNEL 2 HI

CHANNEL 11 HI13 LO

SIGNAL GROUND
CHANNEL 4 HI

CHANNEL 13 HilS LO
SIGNAL GROUND
CHANNEL 6 HI
CHANNEL 15 Hlf7 LO

SIGNAL GROUND

25.
24.
23. .10
22.
21.
20.
1••
1•• .5
.4
1•• .3
15. .2
14.

1I081T4

."••

".

(VIEWED FROM FRONT OF BOARD)

CHANNEL 8 HIIO LO

110 BIT 3
SIGNAL GROUND
I/OBIT2
CHANNEL 1 HI
110 BIT 1

CHANNEL 10 HII2 LO

••.7
••

liD BITO

SIGNAL GROUND

DTA OUT
CHANNEL 3 HI

TIMERAOUT

CHANNEL 12 HI/4 LO

TIMER BOUT

SIGNAL GROUND

TIMER A IN
CHANNEl5 HI
TIMER B IN

CHANNEL 14 H1I6 LO

.'

SIGNAL GROUND
CHANNEL 7 HI

Figure 4. Local Analog
Input Connector Analog (J1)

SIGNAL GROUND
SIGNAL GROUND

.,3
25. .,2
24.
23. .10
22.
21.
20.
1••
1•• .5
.4
1•• .3
15. .2
14.

."••

".

••.7
••

.'

J3

(VIEWED FROM FRONT OF BOARD)

SIGNAL GROUND
EXT. ADDRESS lOUT

SIGNAL GROUND
EXT. ADDRESS 3 OUT
NOT USeD
EXT. ADDRESS 5 OUT
AfDTRIG' IN
EXT. ADDRESS 7 OUT

TtMEACOUT

NOT useD

NOfUSED
SeTILDLY'IN

SIGNAL GROUND
EOSOUT

DSA IN
NOT USED
CTS IN
AID TRIG" IN
ATS OUT
RXDATA IN
TXDATAOUT
CHASSIS GAOUND

Figure 5. Multifunction Peripheral
1/0 Connector (J2)

DIGITAL GROUND
EXT. ANALOG GROUND
EXT. ANALOG HI IN

25. .,2
24.
23. .,0
22.
21.
20.
1••
, .5
, .4
15. .2
14.

."

.9
••.7
••

.."...
.'

.'

EXT. ADDRESS 0 OUT
EXT. ADDRESS 2 OUT

EXT. ADDRESS 4 OUT
EXT. ADDRESS 6 OUT
ADDRESS VALID OUT

STROBE OUT
EOCOUT
NQTUSED

NOT USED
DIGITAL GROUND
NOT USED
EXT. ANALOG GROUND
EXT. ANALOG LO IN

Figure 6. Analog Channel Expansion
Bus Connector (J3)

ORDERING GUIDE
Model Number
DVME-601A
DVME-601B
DVME-601C
DVME-601D
DVME-601E

A/D Bits, Conversion Speed, and Input Configuration
12 Bits,
12 Bits,
16 Bits,
16 Bits,
12 Bits,

20 I'Sec., unipolar or bipolar
4 I'Sec., bipolar
35 I'Sec., bipolar
400 ms, bipolar
2 I'Sec., bipolar

Unipolar models DVME-601 B-U
and DVME·601C-U are
available under special order.

All models include a 64 Kb EPROM with Monitor/Executive firmware, and a User's Manual. A substantial amount of unused EPROM is available to the user. DATEL will review custom software requirements under special order.
HARDWARE ACCESSORIES
Part Number

Description

DVME·691A

Rack-mount screw terminator panel with signal conditioning pads for 32SI16D input channels. Includes flat signal
cables compatible with the DVME-601.

DVME-C-01

Channel expansion flat cable with 2 DB-25P connectors for use with one slave MUX board.

DVME-C-02

Channel expansion flat cable with 3 DB-25P connectors for use with two slave MUX boards.

CHANNEL EXPANSION SLAVE MUX BOARDS
Part Number

Description

DVME-641

32S/16D Channel high speed, high-level non-isolated MUX board.

DVME-643

80 Channel low-level, isolated MUX board.

DVME-645

16S/8D Channel simultaneous sampling MUX board.

Contact DATEL for DVME-601
software on disk.

D/A OUTPUT AND DISCRETE I/O BOARDS
Part Number

Description

DVME-624

4 Channel isolated 12-bit D/A board, plus 4-to-20 mA passive loops.

DVME-626

6 Channel 14/16·bit DIA board.

DVME-628

4 or 8 Channel 12-bit DIA board, plus 4-to-20 mA passive loops.

DVME-660

48-line TTL I/O and timel'linterrupt board.

11-10

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DVME·602R
VMEbus 4·CHANNEL
RTD INPUT AID BOARD
FEATURES
•
•
•
•
•
•
•

4 AID channels for RTD temperature measurements
Fully hardware-compatible with VMEbus architecture
On-board CPU for temperature calculations
Open RTD detection circuitry
Internal RTD excitation, linearization and signal conditioning
Output in degrees Celsius or Fahrenheit
12-Bit plus sign resolution

THE DVME602R IS AN INTELLIGENT VMEbus AID BOARD SPECIFICALLY DESIGNED FOR RTD INPUT MEASUREMENTS. CONDITIONING SIGNALS FROM UP TO 4 CHANNELS, THE DVME-602R PROVIDES LINEARIZED DATA TO
VMEbus-BASED HOST SYSTEMS. THE DVME602R IS PROGRAMMABLE TO PROVIDE OUTPUTS IN DEGREES C OR
F DESIGNED FOR HOSTILE ENVIRONMENTS, THE BOARD IS IDEAL FOR MOST REAL-TIME DATA ACQUISITION AND
PROCESS CONTROL APPLICATIONS
GENERAL DESCRIPTION
The Model OVME-602R measures direct RTO transducer inputs. This intelligent AID board provides signal conditioning for
up to four analog input channels. The microprocessor on the
OVME-602R performs functions relating to linearization of 100
ohm platinum RTO's with Alphas of 0.00385 European and
0.00392 American. The output data is available as either a Celsius or Fahrenheit temperature range value. On-board switches
let the user conveniently select the RTO type and the output
unit of measurement.
The OVME-602R hardware consists of four sections: VMEbus
interface, microprocessor control, AID converter and the input
signal conditioning (with RTO excitation). An internal data bus
links the control/data registers, AID converter and the
microprocessor. The board also detects open RTO's. Figure 1
shows the OVME-602R functional block diagram.
The OVME-602R AID board comes complete with a user's
manual. The manual describes the installation and calibration
procedures for different applications and presents a theory of
operation of the board. The user's manual also has a detailed
section on troubleshooting. The board is shipped with an example 68010 assembly language diagnostic program on a 5
1/4" floppy diskette, formatted using VERSAdos (pOOS format
also available). Consult the factory regarding the availability
of the diagnostic program's source code in other disk formats.

VME Interface
The OVME-602R interfaces to the host system using the P1
connector. The board uses short I/O space address lines and
16 data lines. On-board switches select the base address of the
board. The board responds to the address modifier codes 29H
and 20H for data output purposes. The DVM E-602R generates
the data acknowledge (OTACK-) signal to notify acceptance of
data from the VME data lines, 000 through 015. The OTACK'
signal is jumper-selectable for delay times from 125 nano-

seconds to 1000 nanoseconds, accommodating different host
systems.
The interface logic decodes the VMEbus WRITE', OSO', OS1-,
and SYSRESEr control lines to provide the interface control
signals. These signals control the board select and. the VMEbus transfer functions. The OVME-602R uses programmable
array logic (PAL) devices for interface and control, guaranteeing true asynchronous operation.

VMEbus Interrupt Logic
The on-board microprocessor, at the end of linearization, generates an interrupt request on one of the VMEbus interrupt lines
(IR01' through IROr). The interrupt line is jumper-selectable.
On receiving the interrupt request, the host system tests the interrupt level using address lines A01 through A03. The host system must then acknowledge using the lACK' and the daisy
chain IACKIN" signal lines. If the OVME-602R interrupt level
matches the level code on the address lines, the interrupt logic
loads the interrupt 10 number on to the VMEbus (lOW byte). The
interrupt 10 number is programmable by the host system. If the
interrupt level on the address line does not match the board's
interrupt level, the board generates the daisy chain IACKOUr
signal.

l

ORDERING INFORMATION

DVME-602

R

=

ATD Inputs

T = Thermocouple and low-level Isolated Inputs'

H =- High-level voltage and current loop Isolated Inputs'

S
Strain gage mputs
(Consult factory tor availability)
0;;;

. Refer to the DVME-602T Data Sheet for speCifications

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-11

III

DVME·602R
FUNCTIONAL SPECIFICATIONS
(Typical at 25° C, unless otherwise noted.)

RTD Excitation Level . . . . . . 0.4 mA
Gain Non-linearity ........ ± 0.01% of span
Gain Tempco ............ ± 25 ppm/oC

INTERFACE SPECIFICATIONS

Digital Output ........... Degrees C or Degrees F

Data Bus ................. 16 Bits

Digital Output Coding ..... 2's complement or sign
and magnitude

Address Bus .............. Short I/O Space
16 address lines

Resolution .............. 12 bits plus sign and
overrange

Address Modifier Codes .... Uses codes 29H and
2DH
Interrupts ................ 1 line, jumperselectable.
Memory Mapping .......... Short I/O space, user or
supervisor 256 words allocated per board.
Data Transfer ............. DTACK* signal line.
Notifies the VMEbus
host that data has been
placed or accepted from
the VMEbus data lines.
The VMEbus SYSCLK signal is required.

Conversion rate .......... 12.5 conversions/second
(Switch selectable)
at 50Hz NMR
15 conversions/second at
60Hz NMR
25 conversions/second at
50Hz NMR
30 conversions/second at
60 Hz NMR

Power Supply Requirements
With internal dc-to-dc ..... +5V dc ±0.5% at 1.6 A
Converter
2.5 Amps maximum

CONNECTOR SPECIFICATIONS
VMEbus Pl connector ...... 96-pin male DIN
connector.

Physical Characteristics

Jl Analog Input ........... Connects to a 12-pin terConnector
minal block.
Use Phoenix Contacts
MSTB 1.5/12-ST or
equivalent

Outline Dimensions ....... 9.19"W x 6.3"0 x 0.6"H
(233.35 x 160 x 15.24 mm)

J2 Digital Output .......... Connects to a 4-pin terConnector
minal block.
Use Phoenix Contacts
MSTB 1.5/4-ST or
equivalent.

ANALOG INPUT SPECIFICATIONS

Weight ................. 14.5 Oz (411 grams)
Operating Temperature .... 0 to + 60° C (+32 to
Range
+ 140° F)
Storage Temperature ...... -20 to +80° C (-4 to 176°
Range
~
Relative Humidity ........ 0 to 80%
non-condensing
Altitude ................ 0 to 15000 feet (4572
meters)

Analog Input channels. . . . . . 4
Input Configuration ........ Differential
Input Type ................ RTD (Refer to Table 1)
Input Impedance .......... <100 Megohms,
minimum
Input Bias Current ......... 10 nanoamps, maximum
Common Mode Rejection ... 94 dB, minimum
Ratio, minimum, Rs 5 lk, f 5 0.01
to'100 Hz
Maximum Safe Differential ... 130V RMS
Voltage without damage (Overvoltage protection)

Table 1. RTD Functional Specifications

RTD
TYPE

RANGE

European Alpha
of 0.00385

-200 to +850

System Accuracy
American Alpha
of 0.00392
System Accuracy

(OC)

-200 to 0
+850

o to

-200 to +630

-200 to 0
+630

o to

NOTES
Equivalent resistance of
18.49 to 390.26 Ohms

± 3 Degrees Celsius
± 1 Degree Celsius
Equivalent resistance of 17.14
to 327.02 Ohms

± 3 Degrees Celsius
± 1 Degree Celsuis

Normal Mode Rejection ..... 55 dB, minimum
at 50/60 Hz
Input Lead Resistance ...... ±0.03/0hm
Effects
Voltage Range Gain Drift, ... 45 ppm/oC, maximum

11-12

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DVME-602R

LWORD
AMO·AM5

IACK*

4 RlD INPUT
CHANNELS

SIGNAL
CONDITIONING
MODULES

050*
OSI*
WRITE*

AS*
DTACK*
AO·A7

SYSRESET*

DOO·Dl!)

Figure 1. DVME-602R Functional Block Diagram

DVME-602R PROGRAMMING INFORMATION

Word address: Base + 144

The DVME-602R maps onto 256 consecutive bytes in the host system's address space. The address space essentially consists of
the board ID number and registers. The registers are the command
register, the status register, the AID data register, the interrupt vector register, and the interrupt enable register. Table 2 lists the contents of the DVME-602R address space.

15

14

13

12

11

10

9

8

7

1

=

o = 2's complement
1

Read
Write

Command register

Base + 144

Read

Status register

Base + 146

Read

AID data register

Base + 148

Readl
Write

Interrupt vector register

Base + 150

Write

Interrupt enable register

-,-,

3

2

(WRITE)
1 0

Sequential scanning mode

Manufacturer's/Board's
identification code

Function

4

o = Random scanning mode

Contents

Address

5

Channel
Address

Table 2. DVME-602R Hardware registers

Base + 0
through
Base + 63
-Base + 144

6

=

Sign and magnitude

-PGA gain code for calibration and voltage input
,-

o = Normal operating mode
1

= Calibration

mode

Figure 2. DVME-602R Command Register Format
Status Register

Command Register
Programming this register selects the mode of scanning, mode
of operation, output format, and PGA gain. Bits 0 and 7 of the status register monitor successful completion of the command. After entering the calibration mode, the gain and offset
potentiometers may be adjusted on a per-channel basis. Figure
2 shows the command register format.

The contents of the status register indicate the channel selected,
unit of temperature, and status of the AID data and command
registers. The bits 12 through 15 of this register indicate error conditions concerning open inputs, data out of range, and possible
DVME-602R hardware failures. If the DVME-602R fails
the self-test at power-up, the status bits indicate RAM or ROM
failure and the BOARD OK lamp turns OFF. Figure 3 shows the
format of the status register and Table 3 lists the error status conditions.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-13

a

DVME-602R
Interrupt ID Register

No Interrupts
Interrupts
Enabled

Address

o = Celsius
1

If the DVME-602R interrupt level matches the level code on the address lines, the interrupt logic loads the interrupt ID number onto
the VMEbus (low byte). Figure 5 shows the format ofthe interrupt
ID register.

= Fahrenheit
o = Data/status not valid
1 = Data/status valid

o=
1

This register contains the user-loaded interrupt ID number. On
receiving the interrupt request, the host system tests the interrupt
level using address lines A01through A03. The host system must
then acknowledge using the lACK' and the daisy chain IACKIN'
signal lines.

Last command accepted. Ready for new command.

= Busy processing command. Not ready for new command.
Word address: Base + 148
15

Figure 3. DVME·602R Status Register Format

14

13 12

11

10

9

(READIWRITE)
876543210

x 11071106
Table 3. Error Status Conditions
Error Number
S7 S6 S5 S4

0
1
1
1
1
1
1
1
1

0
0
0
0
0
1
1
1
1

0
0
0
1
1
0
0
1
1

0
0
1
0
1
0
1
0
1

Error

Interrupt Enable Register

No error
Calibration mode
Data out of range
Open wire detection
Board not ready
Not used
Not used
Not used
Memory or board failure

The host system may program bit 6 of the interrupt enable register
to enable the on-board interrupt. If this bit is set, the DVME-602R
interrupts the host system when the AID data is ready. The status
of this bit is indicated in bit 6 of the status register. Bits 0 and 1 of
the interrupt enable register are programmable to function as digital outputs. These outputs are provided on the digital output connector. Figure 6 shows the format of the interrupt enable register.

Word address: Base + 150

This register contains the binary data received from the selected
channel after successful completion of a command. Bit 7 of the
status register indicates the validity of the data. Depending the
mode of operation, the data may be a raw reading from the AID
converter or the linearized data from a thermocouple input. Data
in this register can exist in two formats, as defined by bit 13 of the
command register. This bit sets up the data word as either a 16-bit
2's complement or a 15-bit number plus sign.
As a 2's complement word, 12 bits of data occupy bit locations 0
through 11. The sign bit (MSB) occupies bit location 12 and the sign
is extended to fill the 16-bit register. Figure 4 shows the format of
the AID data register.

Word address: Base + 146
14

13 12

11

MSB/
SIGN

10

9

8

7

6

5

4

3

(WRITE)
2
1 0

o = Interrupts not enabled 1 - - - - - '
1

= Interrupts enabled

Figure 6. DVME·602R Interrupt Enable Register

1/0 CONNECTIONS
The DVME-602R uses TB1 for analog input (J1) connections and
TB2 for digital output (J2) connections. Table 4 lists input signals
on the TB1 connector while Table 5 lists those on the TB2 connector.

Table 4. J1 Connector Signals (TB1)

LSB

Figure 4. DVME·602R AID Data Register 2's Complement

Pin #
1
3
5
7
9
11

11-14

I

Figure 5. DVME·602R Interrupt 10 Register Format

AID Data Register

15

11051104110311021101 1100

Signal
N.C.
CHANNEL 3 HI IN
CHANNEL 2 La IN
N.C.
CHANNEL 1HIIN
CHANNEL 0 La IN

Pin #
2
4
6
8
10
12

Signal
CHANNEL 3 LO IN
N.C.
CHANNEL 2 HI IN
CHANNEL 1 La IN
N.C.
CHANNEL 0 HI IN

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 0204S·11941TEL (50S) 339·30001TLX 17438S/FAX (50S) 339·6356

DVME-602R
Table 6. RTD Input Range/Output Range Selection

Table 5. J2 Connector Signals (TB2)

Pin #
1
2
3
4

Signal

CHANNELS 0 THROUGH 3

52·3

52·4

S2·5

S2·10

DIGITAL GROUND
DIGITAL GROUND
DIGITAL OUTPUT 1
DIGITAL OUTPUT 0

American Alpha
(0.00392)

OFF

OFF

ON

NA

European Alpha
(0.00385)

ON

ON

ON

NA

Degrees Fahrenheit

NA

NA

NA

ON

Degrees Celsius

NA

NA

NA

OFF

RTD Input Range Selection
The DVME-620R board lets the user select between American and
European Alpha coefficients for the type of RTD used in the application. Selection of the proper Alpha, and selection of the output temperature unit, is simple. A DIP switch on the board, S2,
allows the user to select these options. Table 6 lists the proper S2
settings to implement these options.

NOTES

III
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

11-15

DVME·602R
DATEL VMEbus Short 110 Memory Organization

DVME·602R Board Identification Code
Byte
Address
Base + 1
+ 3
+5
+7
+9

ASCII
Code

Function

Base
Address
Base + 0
through
Base + 63

Manufacturer's and Board's
identification code

Base + 64
through
Base + 77

DVME·660

48 line digital I/O board

-----------------------

Not Used

DVME-611

DVME-611: 32 single-endedl
16 differential channel AID
board

DVME-612

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 D/A channels

DVME-602

DVME-602: 4-channel isolated board for measuring
thermocouples RTD's, strain
gage, high-level, low-level,
and 4-to-20 mA current loop
inputs

-------.---------------

Not Used

DVME-612

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 D/A channels
DVME-624: 4-channel isolated D/A board
DVME-626: 6-channel, 16-bit
D/A board
DVME-628: 8-channel D/A
board

Identifier
This ASCII code is present
for all DATEL VMEbus boards

+ OB

D

Manufacturer ID

+ OD

A

DAT is the ID for DATEL

+ OF

T

Base + 78
through
Base + 127

+ 11

d

Board model number

Base + 128
through
Base + 143

+ 13

V
M

+ 17

E

+ 19

-

+ 1B

6

+10

0

+ 1F

2

Function

All DATEL
VMEbus
boards

V
M
E
I
D

+ 15

Board
Model Number

Base + 144
through
Base + 151

Base + 152
through
Base + 159
Base + 160
through
Base + 175

DVME-624
DVME-626
DVME-628

11-16

Base + 176
through
Base + 191

-----------------------

Base + 192
through
Base + 255

-------------.-.-------

---------------------.-

------------------_.--.

Not Used

-----------------------

Not Used

-------------------.--.

I
I
I

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048·1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DVME-602T
ISOLATED THERMOCOUPLE
4-CHANNEL VMEbus AID BOARD
FEATURES
• 4 AID channels with high isolation (1000V peak).
• Fully hardware-compatible with VMEbus architecture
• Two models to measure a choice of inputs:
DVME-602T for thermocouples and low-level inputs.
DVME-602H for high-level and 4-to-20 mA inputs.
• On-board CPU for temperature calculations
• On-board linearization for J, K, T, S, B, E, and R type
thermocouples
• On-board cold junction compensation
• Output in degrees Celcius or Fahrenheit
• 13-bit resolution

THE DVME·602T1602H ARE DATEL's HIGH END AID BOARDS SPECIFICALLY DESIGNED FOR THERMOCOUPLE AND
HIGH·LEVEL INPUT MEASUREMENTS. BOTH BOARDS CONDITION SIGNALS FROM UP TO 4 CHANNELS AND PRO·
VIDE LINEARIZED BINARY DATA TO A VMEbus·BASED HOST SYSTEM THE DVME·602T MODEL IS PROGRAMMABLE
TO PROVIDE OUTPUTS IN 0C OR of DESIGNED FOR HOSTILE ENVIRONMENTS REQUIRING HIGH-ISOLATION, THESE
BOARDS ARE IDEAL FOR MOST REAL-TIME DATA ACQUISITION AND CONTROL APPLICATIONS

GENERAL DESCRIPTION
DATEL offers the DVME-602 AID boards in two models. The model
DVME-602f measures thermocouple and low-level inputs and the
model DVME-602H measures high-level inputs. The intelligent AID
boards provide signal conditioning for up to four analog input chan·
nels. The microprocessor on the DVME-602f performs functions
relating to linearization for J, K, T, S, B, E, and R type thermocouples. The output data is available as either a celcius or fahrenheit temperature range value. On-board switches let the user
select the thermocouple type and the output unit of measurement.
Features include isolation, SO/60Hz rejection, and a 120 dB Com·
mon Mode Rejection Ratio. The on-board signal conditioning mod·
ules provide a minimum of 7S0V RMS isolation from channelto·channel and channel-to-VMEbus. The high isolation protects the
host system from high voltage damages if a thermocouple
accidentally contacts a high voltage line. The boards' 1'20 dB
CMRR allow thermocouple measurements even in the presence
of high common mode voltages.
The DVME·602f also measures low-level ±2S.6, ±SI.2 and
± 102.4 mV dc full-scale range analog signals from sources other
than thermocouples, providing the raw, unlinearized AID data to
the host system.
An on-board cold junction compensation (CJC) circuit eliminates
errors caused by temperature variations of the cold junction. The
CJC is effective over a range of 0 to +60 oc, The DVME-602H offer
±SV dc and current loop signal input capability. The board is
provided with an attenuation circuit for higher input voltage ranges.
The DVME-602T/602H hardware consists essentially of five sections: VMEbus interface section, microprocessor control section,
AID converter section, input signal conditioning section and the
CJC section. An internal data bus links the control/data registers,
AID converter and the microprocessor. Figure 1 shows the
DVME-602 functional block diagram.

The DVME-602 AID boards will be shipped with a user's manual.
The user's manual describes the installation and calibration procedures for different applications and explains the theory of operation of the AID boards. The user's manual also contains
information on troubleshooting the boards.
The boards are shipped with an example 68010 assembly language diagnostic program on a S 1/4" floppy diskette, formatted
using VERSAdos (pDOS format also available). Consult the factory regarding the availability of the diagnostiC program's source
code in other disk formats.

NOTE:
References to the DVME-602 in this Data Sheet apply to both the
DVME-602T and the DVME-602H.

ORDERING INFORMATION
DVME-602
T

= Thermocouple and low-level isolated inputs.
Types J, K, T, S, B, E, and R.
Low-level ranges: ±2S.6 mY, ±SI.2 mV and
±102.4 mV de

H

=

High-level voltage and current loop isolated
inputs
High-level voltage ranges: ±SV de
Current loop inputs: 4-to-20 rnA

R
S

= RTD inputs"
= Strain gage inputs'
(Consult factory for availability)
'See page 4
.. Refer to the DVME-602R Data Sheet for specifications.

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-17

III

DVME·602T
VME Interface

VMEbus Interrupt Logic

The DVME-602 interfaces to the host system using the P1 connector. The board uses short I/O space address lines and 16 data lines.
On-board switches select the base address of the board. The
board responds to the address modifier codes 29H, 2DH, 39H, and
3DH for data output purposes. The DVME-602 generates the data
acknowledge (DTACK* ) signal to notify acceptance of data from
the VME data lines, DOO through D15. The DTACK* signal is
jumper-selectable for delay times from 125 nanoseconds to 1000
nanoseconds, accommodating different host systems.

The on-board microprocessor, at the end of linearization, generates an interrupt request on one of the VMEbus interrupt lines
(IRQ1 * through IRQ7* ). The interrupt line is jumper-selectable.
On receiving the interrupt request, the host system tests the interrupt level using address lines A01 through A03. The host system
must then acknowledge using the IACK* and the daisy chain
IACKIN* signal lines. If the DVME-602 interrupt level matches the
level code on the address lines, the interrupt logic loads the interrupt ID number on to the VMEbus (low byte). The interrupt ID number is programmable by the host system. If the interrupt level on
the address lines do not match, the board generates 'the daisy
chain IACKOUT* signal.

The interface logic decodes the VMEbus control lines WRITE*,
DSO* , DS1 * ,and AS* to provide the interface control signals.
These signals control the board select and the VMEbus transfer
functions. The DVME-602 uses programmable array logic (PAL)
devices for interface and control, guaranteeing true asynchronous
operation.
LWORO

AMO-AM5
IACK*

4-CHANNEl

b
080* ul----l=:---,~
081*
WRITE*
AS*

DTACK*
AO·A7

SYSRESET*

DIGITAL
OUTPUTS

000·015

Figure 1: DVME-602 Block Diagram

FUNCTIONAL SPECIFICATION
(Typical at + 25 degrees Celcius, unless otherwise noted)

Data Transfer .............. DTACK* signal line.
Notifies the VMEbus host
that data has been placed
or accepted from the VME·
bus data lines.

Interface specifications
CONNECTOR SPECIFICATIONS
Data Bus ................. 16 Bits
Address Bus .............. Short I/O Space
16 address lines
Address Modifier Codes ..... Codes used 29H, 2DH,
39H, and 3DH
Interrupts ................ 1 line, jumper-selectable.
Memory Mapping .......... Short I/O space, user or
supervisor 256 words allocated per board.

ThE! VMEbus SYSCLK signal is required.

11-18

VMEbus P1 connector ...... 96-pin male DIN connector.
J1 Analog Input ............. Connects to a 12-pin termiConnector
nal block. Use Phoenix
Contacts MSTB 1.5/12-ST or
equivalent.*
J2 Digital Output ........... Connects to a 4-pin terminal
Connector
block. Use Phoenix Contacts MSTB 1.5/4-ST or
equivalent.*
*One mating connector supplied with each board.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DVME·602T
DVME·602 PROGRAMMING INFORMATION

Word address: Base + 144
15 14 13 12

The DVME-602 maps onto 256 consecutive bytes in the host system's address space. The address space essentially consists of
the board ID number and registers. The registers are the command
register, the status register, the AID data register, the interrupt ID
register and the interrupt enable register. Table 1 lists the contents
of the DVME-602 address space.

Error status bits

a
1

Table 1: DVME-602 Hardware Registers

Address

Function

Contents

Base + a
through
Base + 63

Read

Manufacturer's/Board's
identification code

Base + 144

Write

Command register

10

Base + 144

Read

Status register

Read

A/D data register

Base + 148

Read/
Write

Interrupt ID register

Base + 150

Write

Interrupt enable register

Command Register
Programming this register selects the mode of scanning, mode
of operation, coding, PGA gain code and CJC. The bits 0 and 7
of the status register monitor successful completion of the command. Figure 2 shows the command register format.

8

7

6

5

4

(READ)
321
a

No Interrupts
Interrupts
Enabled

Channel
Address

= Celcius
= Fahrenheit
a = Data/status not valid
1 = Data/status valid

a
1

Last command accepted. Ready for new command.
Busy processing command. Not ready for new command.
Figure 3:

Base + 146

9

DVME-602 Status Register Format

Table 2: Error Status Conditions
Error Number
S7 S6 S5 S4

Error

a a a a
1 a a a
1 a a 1
1 a 1 a
1 a 1 1
1 1 a a
1 1 a 1
1 1 1 a
1

1

1

No error
Calibration mode
Data out of range
Open wire detection
Board not ready
CJC out of range
CJC and data out of range
CJC and open wire
Memory or board failure

1

Word address: Base + 144
AID Data Register

a = Data from channels a through 3
1 = Data from CJC
a = Random mode
1 = Sequential mode
a = 2's complement
1 = Sign and magnitude
PGA gain code for calibration and voltage input
a = Normal operating mode
1 = Calibration mode
Figure 2:

DVME-602 Command Register Format

This register contains the binary data received from the selected
channel after successful completion ofa command. Bit 7 of the
status register indicates the validity of the data. Depending on the
mode of operation, the data may be a raw reading from the AID
converter or the linearized data from a thermocouple input. Data
in this register can exist in two formats, as defined by bit 13 of the
command register. This bit sets up the data word in either a 2's
complement of sign plus magnitude format. As a 2's complement
word, 12 bits of data occupy bit locations 0 through 11. The sign
bit (MSB) occupies bit location 12 and the sign is extended to fill
the 16-bit register. Figure 4 shows the 2's complement format of
the AID data register.
Word address: Base + 146
15

14

13

Status Register
The contents olthe status register indicate the channel selected,
unit of temperature, and status of the AID data and command
registers. Bits 12 through 15 of this register indicate error conditions concerning open inputs, CJC and data out of range, and possible DVME-602 hardware failures. If the DVME-602 fails the
self-test at power-up, the status bits indicate RAM or ROM failure
and the BOARD OK lamp turns off. Figure 3 shows the format of
the status register and Table 2 lists the error status conditions.

12

11

10

9

8

7

6

5

4

(READ)
321
a

MSB/
SIGN
Figure 4:

LSB

DVME·602 AID Data Register 2's Complement
Format

II
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

11-19

DVME·602T
110 CONNECTIONS

Interrupt 10 register
This register contains the user-loaded interrupt 10 number. On
receiving the interrupt request, the host system tests the interrupt
level using address lines A01 through A03. The host system must
then acknowledge using the IACK* and the daisy chain IACKIN*
signal lines. If the OVME-602 interrupt level matches the level code
on the address lines, the interrupt logic loads the interrupt 10 number onto the VMEbus (low byte). Figure 5 shows the format of the
interrupt 10 register.

The OVME-602 uses TB1 for analog input (J1) connections and
TB2 for digital output (J2) connections. Table 3 lists input signals
on the TB1 connector.

Table 3: Jl Connector Listing

Pin #
Word address: Base + 148
15

14

13

12

11

10

9

(READ/WRITE)
876543210

11051104110311021101 1100 I

x 11071106
Figure 5:

1
3
5
7
9
11

-12V de
CHANNEL 3 HI IN
CHANNEL 2 LO IN
-12Vde
CHANNEL 1 HI IN
CHANNELOLOIN

Word address: Base + 150

o=
1

=

13

Signal
CHANNEL 3 LO IN
-12V de
CHANNEL 2 HI IN
CHANNEL 1 LO IN
-12V de
CHANNEL 0 HI IN

Table 4: J2 Connector Listing

The host system may program bit 6 of the interrupt enable register
to enable the on-board interrupt. If this bit is set, the OVME-602
interrupts the host system when the AIO data is ready. The status
of this bit is indicated in bit 6 of the status register. Bits 0 and 1 of
the interrupt enable register are programmable to function as digital outputs. These outputs are provided on the digital output connector. Figure 6 shows the format of the interrupt enable register.

14

2
4
6
8
10
12

DVME-602 Interrupt 10 Register Format

Interrupt Enable Register

15

Pin #

Signal

12

11

10

9

8

7

6

5

4

3

Pin #
1
2
3
4

Signal
DIGITAL GROUND
DIGITAL GROUND
DIGITAL OUTPUT 1
DIGITAL OUTPUT 0

(WRITE)
210

Interrupts not enabled I - - - - - . J
Interrupts enabled

Figure 6:

DVME-602 Interrupt Enable Register

FEATURES FOR RTD and STRAIN GAGE MODELS
DVME-602R

DVME-602S

• 4 AID channels

• 4 AID channels

• RTO inputs
A. 25 to 1750
B. 0 to 3500

• Strain gage inputs
A. ±30 mV dc
B. ±100 mV dc

• Fully compatible with VMEbus hardware

• Fully hardware-compatible with VMEbus hardware

• On-board signal conditioning
• On-board constant current excitation
• On-board source and lead wire compensation
• 130V maximum safe differential input voltage

11-20

• On-board signal conditioning

• 94 dB minimum CMRR
• ±O.02% maximum nonlinearity
• 130V maximum safe differential input voltage

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DVME-602T
Digital Output ............. Degrees e or degrees F

ANALOG INPUT SPECIFICATIONS

Digital Output Coding ....... 2's complement or sign and
magnitude

Analog Input channels ...... 4
Input configuration ......... Differential
Input types ............... Thermocouples. low-level,
High-level and 4-to-20 mA
current loops
Isolation, channel-to- ....... 1000V, Peak maximum
channel and channel-tobus, AC or dc

Resolution ............... 12 bits plus sign and
overrange
Conversion rate ............ 12.5 conversions/second at
(Switch-selectable)
50Hz NMR
15 conversions/second at
60Hz NMR
25 conversions/second at
50Hz NMR
30 conversions/second at
60Hz NMR

Input Impedance ........... 100 Megohms, minimum
Input Bias Current. ........ 8 nanoamps, maximum
Common Mode Voltage ..... 750V RMS, minimum
Range, channel-to-channel 1000V peak, maximum
and channel-to-VMEbus
AC, 50 or 60 Hz
Common Mode Rejection
Ratio, minimum
(Rs = 1k, f=0.01 to 100 Hz)

With internal dc-to-dc ....... +5V dc ±0.5% at 1.6 A
Converter

Maximum Safe Differential ... 130V RMS
Voltage without damage
(Overvoltage protection)

Thermocouple Input Ranges and Accuracy (Maximum)

Normal Mode Rejection at ... 55 dB, minimum
50/60 Hz
Input Lead Resistance ...... None
Effects
Voltage Input Ranges
DVME-602T ........ ±25.6mV dc
±51.2mV dc
±102.4mV dc
DVME-602H ........ ±5.12V dc
Voltage Range Accuracy
DVME-602T ........ 0.03% FSR, minimum
DVME-602H ........ 0.1% FSR, minimum
Voltage Range Gain Drift, .... 45 ppml

°e, maximum

Input Voltage Range Offset Drift
Input Range

°e
°e

Power Supply Requirements

DVME-602T .............. 120 dB, minimum
DVME-602H .............. 110 dB, minimum

Model Number

CJC Error
Room temperature ....... ± 0.5
Full temperature range .... ± 1.5

Thermocouple
Type

Temperature
Range
(OC)

I nput Voltage
Range
(mV)

Accuracy
(OC)

J

-200 to 0
o to +760

-7.89010 -4.632
-4.632 to +42.922

±3
±1

K

-200 to -100
-100 to + 1232

-5.891 to -3.553
-3.553 to +49.988

±3
±1

S

oto +300
+300 to +1768

0.000 to +2.323
+ 2 .323 to + 18.698

±6
±3

T

-200 to 0
oto +400

-5.603 to 0.000
0.000 to + 20.869

±3
±1

E

-270 to -200
-200 to 0
o to +1000

-9.835 to -8.824
-8.824 to 0.000
0.000 to +76.358

±10
±3
±1

R

o to +300
+300 to +1768

0.000 to +2.400
+2.400 to +21.108

±4
±2

B

+300 to +500
+500 to + 1000
+1000 to +1820

+0.431 to +1.241
+1.241 to +4.833
+4.833 to +13.814

±5
±3
±2

Offset Drift

DVME-602T

±25.6mV dc
±51.2mV dc
±102.4mV dc

3p.V/ o e
3/Nl oe
3.5p.V/ o e

DVME-602H

±5.12V dc

70p.Vi

°e
Physical Characteristics

Time and Temperature Related Drift
Thermocouple
Type

J
K
S
T
E

R
B

Time related
drift
(OC/S months)

±
±
±
±
±
±
±

0.2
0.25
1.0
0.25
0.2
0.8
1.0

Temperature related
drift
(OC/°C)

±
±
±
±
±
±
±

0.1
0.15
0.3
0.1
0.15
0.3
0.3

Outline Dimensions ........ 9.19"W x 6.3"0 x 0.6"H
(233.35 x 160 x 15.24 mm)
Weight. .................. 14.5 Oz. (411 grams)
Operating Temperature ..... 0 to +60
Range

°e

Storage Temperature Range. -20 to +80

°e

Relative Humidity .......... 0 to 80%
non-condensi ng
Altitude .................. 0 to 15000 feet (4572 meters)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

11-21

III

DVME-602T
DATEL VMEbus Short 1/0 Memory Organization

DVME·602T Board Identification Code
Byte
Address

ASCII
Code

Function

V
M
E
I
D

Identifier
This ASCII code is present
for all DATEL VMEbus boards

+ OB

D

Manufacturer ID

+ OD

A

DAT is the ID forDATEL

+ OF

T

+ 11

d

Base + 1
+3
+5
+7
+9

+ 13

V

+ 15

M

+ 17

E

+ 19

-

+ 1B

6

+10

0

+ 1F

2

Board model number

Base
Address

Board
Model Number

Function

Base + 0
through
Base + 63

All DATEL
VMEbus
boards

Manufacturer's and Board's
identification code

Base + 64
through
Base + 77

DVME-660

48 line digital 110 board

-----------------------

Not Used -----------------------

DVME-611

DVME-611: 32 single-endedl
16 differential channel AID
board

DVME-612

DVME-612:32 single-endedl
16 differential channel AID
board with 2 D/A channels

DVME-602

DVME-602: 4-channel isolated board for measuring
thermocouples RTD's, strain
gage, high-level, low-level,
and 4-to-20 mA current loop
inputs

-----------------------

Not Used -----------------------

DVME-612

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 D/A channels
DVME-624: 4-channel isolated D/A board
DVME-626: 6-channel, 16-bit
D/A board
DVME-628: 8-channel D/A
board

Base + 78
through
Base + 127
Base + 128
through
Base + 143

Base + 144
through
Base + 151

Base + 152
through
Base + 159
Base + 160
through
Base + 175

DVME-624
DVME-626
DVME-628

11-22

Base + 176
through
Base + 191

-----------------------

Base + 192
through
Base + 255

-----.-----------------

Not Used -----------------------

I
I
Not Used

--------------.--------

I

DATEL, Inc_ 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DVME-611/612
32S/16D-CHANNEL
VME A/D-D/A BOARDS
FEATURES:
• Two models of VMEbus-based boards:
DVME-611: 32 single-ended/16 differential A/D channels
DVME-612: 32 single-ended/16 differential A/D channels
and 2 D/A channels
• Five levels of resolutions available:
A. 12-bit/20,..S
B. 12-bit/4,..S
C. 16-bit/35,..S
D. 16-bit/400 mS
E. 12-bit/2,..S
• Four input voltage ranges available: ± 10V, ±5V, 0 to 5V, and
o to 10V de
• Three types of output coding:
A. Bipolar 2's complement
B. Bipolar offset binary
C. Unipolar straight binary
• Up to 160,000 conversions per second throughput.

• Eight-stage programmable gain amplifier (PGA)
• ±0.05% full-scale range accuracy for D/A channels

• Up to 0.0063% full-scale range accuracy

• Channel expansion boards for up to 256 channels:
DVME-641: Non-isolated, high-level inputs
CVME-643: Isolated, thermocouple, RTD, high-level,
4-to-20mA inputs
DVME-645: Simultaneous sample/hold inputs

• ± 1/2 LSB linearity error

• Two TTL digital outputs

• Fast throughput mode for high-speed data transfers
• On-board interrupt vector register for host system's service routines.

• 80 dB CMRR at gain of 128

DATEL's DVME-611/612 ARE HIGH-PERFORMANCE AID BOARDS OFFERING SAMPLING RATES OF UP TO 160kHz
SAMPLING. DESIGNED FOR VMEbus SYSTEMS, THE PRODUCT LINE INCLUDES MODELS WITH DIFFERENT
AID CONVERTER RESOLUTIONS. WITH HIGH-SPEED REAL-TIME DATA ACQUISITION APPLICATIONS IN MIND,
THE DVME-611/612 BOARDS ARE IDEAL CHOICES FOR PROCESS CONTROL, TEST AND MEASUREMENT AND
OTHER RELATED INDUSTRIAL APPLICATIONS.
GENERAL DESCRIPTION
The DVME-611/612 are DATELs VMEbus based high-end AID conversion boards. The A/D boards provide up to 16-bit binary data
from up to 32 single-ended or 16 differential analog input channels. DATEL offers optional expansion boards for up to 256 singleended or differential analog input channels. The DVME-612 is also
equipped with two D/A channels, operable in four output voltage
ranges.
The on-board hardware essentially consists of multiplexers, a
PGA, an AID converter and registers. The PGA is programmable
for gains from 1 to 128 in binary increments. Both the DVME-611
and the DVME-612 are available in four models depending upon
the A/D converter module used. The A/D converter modules are
easily field-replaceable. All models except the DVME-611D and the
DVME-612D contain a sample/hold amplifier.
The host programmable command register controls the A/D conversion process. Depending upon the contents of the command
register, an external trigger may also initiate the AID conversion
process. The host system may obtain the information pertaining to
the AID conversion and control selections using the status register.
For an intelligent A/D board (local 68010, dual-port RAM,
RS-232, etc.), see model DVME-601)

ORDERING INFORMATION
DVME-611q]- 12-bitl20,..S ADC
B - 12 bitl4 ,..S ADC
DVME-612
C -16-bitl35 ,..S ADC
D -16-bitl400 mS
E - 12-bitl2 ,..S ADC
Optional Multiplexer Expansion Boards (See Page 4)
DVME-641 - 32S/16D-Channel high-level non-isolated inputs.
DVME-643 - 8D-Channel isolated inputs.
DVME-645 - 16S/8D-Channel simultaneous sample/hold
high-level non-isolated inputs.
ACCESSORIES
Part Number
Description
DVME-C-01
Two-connector expansion cable (for use
with one multiplexer board).
DVME-C-02
Three-connector expansion cable (for
use with two multiplexer boards).
Contact DATEL for unipolar models DVME-611/612B-U or
611/612C-U under special order.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

III
11-23

DVME·611/612
The channel and control information from the channel select logic
section is brought out to the J4 expansion connector. The control
lines include End of Conversion (EOG), End of Scan (EOS), settling
time delay and external trigger signals. These control signals on
the expansion connector are also usable with externally multiplexed input channels. The start and final channels for AID scanning process are selected by the host system.
On-board jumpers allow coding the digital output data in bipolar
2's complement, offset binary, or unipolar straight binary format.
The analog output section on the DVME-612 offers ± 1/2 LSB
differential non-linearity and operates at ±0.05% of full-scale
range accuracy.
Functionally, the analog signal from the input channels is amplified and converted into binary data. The resolution depends on
the AID converter module used. Figure 1 shows the functional
block diagram of the DVME-611/612 AID boards. Data from the AID
converter module is coded into straight binary, offset binary, or 2's
complement coding. The binary AID data is transferred to the host
system through the VMEbus transceivers.
For applications requiring fast data transfers, the DVME-611/612
AID boards can operate in fast throughput mode. This mode is
selectable using the command register. The fast throughput mode
guarantees transfer of AID data on to the VMEbus without having
to test the conversion status. This mode delays the host CPU
DTACK* while EOC = 0 when AID data is ~ead:
The DVME-611/612 AID boards come with a user's manual. The
user's manual describes the installation and calibration procedures for different applications and explains the theory of operation of the AID boards. The user's manual also contains
information on troubleshooting the boards.
The boards are shipped with an example 68010 assembly lanusing VERSAdos. Consult the factory regarding the availability
of the diagnostic program's source code in other disk formats.

able in hard copy from DATEL. Consult the factory regarding the
availability of the diagnostic program's source code in other disk
formats.
VME Interface
The DVME-611/612 interfaces to the host system using the P1 connector. The board uses short 1/0 space address lines and 16 data
lines. On-board switches select the base address of the board. The
board responds to address modifier codes 29H, 2DH, 39H, and
3DH for data output purposes. The DVME-611/612 generates the
data acknowledge (DTACK * ) signal to notify acceptance of data
from the VME data lines, 000 through 015. The DTACK* signal
is jumper-selectable for delay times from 125 nanoseconds to 1000
nanoseconds, accommodating different host systems.
The interface logic decodes VMEbus control lines (WRITE*,
DSO* , DS1 * ,and AS* ) to provide the interface control signals.
These signals control the board select and the VMEbus transfer
functions. The DVME-611/612 uses programmable array logic
(PAL) device§ for interface and control, guaranteeing true asynchronous operation.

VMEbus Interrupt Logic
The interrupt logic section senses an EOC or EOS condition and
generates an interrupt request on one of the VMEbus interrupt
lines (IRQ1 * through IRQ7*). The interrupt line is jumperselectable. The interrupt logic accepts IACK* and IACKIN * signals from the host system as interrupt acknowledge and daisy
chain input signals. Depending upon the interrupt level, the onboard logic loads the interrupt 10 number on to the VMEbus or
generates the daisy chain IACKOUT * signal.

ANALOG
INPUT

000-015

SYSRESET'

AO·A7

GPO
GPl ----1-1-......
_ _--1-1----'
Digital/Outputs

oso*
081*
WRITE*

FOR

AS'

A08-A15
VOUTO

GROUND
ANALOG

o--S;;FTIF~~

lWOAD*
AMO-AMS

VOUT1

IACK*

ANALOG
GROUND

o

11-24

IRQ1-tRQ?*

VMEbus INTERRUPT

NOTE: The VMEbus SYSClK signal is required.
Figure 1:

IACKOUT*

SELECT

DVME-S11/S12 Functional Block Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DVME·611/612
FUNCTIONAL SPECIFICATIONS
(Typical at 25 degrees Celcius, unless otherwise noted)

Common Mode Voltage

± 10V dc, maximum, non-isolated

Input Bias Current

8 nA, maximum

Over Voltage Protection ±35V dc, maximum
Interface specifications
Data Bus

16 Bits. (A16:016 slave)

Address Bus

Short I/O Space 16 address lines

Address Modifier Codes Codes used 29H, 20H, 39H, and
30H

10 megohms, minimum

Input Impedance
Differential to ground

Common Mode Rejec75 dB at a gain of 2
tion for ±10V input
80 dB at a gain of 128
signal at 60Hz, minimum

Interrupts

1 line, jumper-selectable
2 interrupt 10's for EOC and EOS
Software programmable

Memory Mapping

Short I/O space, user or supervisor
256 words allocated per board

DVME-611A/DVME-612A .025% at a gain of 1
.20% at a gain of 128
DVME-611E/612E

Data Transfer

OTACK* signal line
Acknowledges the VMEbus host that
data has been placed or accepted
from the VMEbus data lines.

DVME-611B/DVME-612B

CONNECTOR SPECIFICATIONS
VMEbus P1 connector

96-pin male OIN connector

J1 and J2 Analog Input
Connectors
J3 Analog Output
Connector

25-pin Ootype female connectors

J4 Analog Expansion
Connector

Number of Channels

32 single-ended or 16 differential

Channel Expansion

256 single-ended or differential; requires external multiplexing. Use
OATELs OVME-641, OVME-643, or
OVME-645 mux boards.

Input Configuration

Single-ended or differential.

Input Ranges

±10V, ±5V, 0 to 5V, or 0 to 10V,
jumper-selectable.

Digital Output Coding
Unipolar and Bipolar Oumperable).

DVME-611/612B
DVME-611/612C
DVME-611/612D
DVME-611 El612E

Bipolar
(For Unipolar coding consult the
factory)

Temperature Drift and Linearity

Gain
Temperature
Coefficient
(ppm/"C)
DVME-611A/612A
DVME-611 B/612B
DVME-611C/612C
DVME-611D/612D
DVME-611 E/612E

+/-20
+/-20
+/-20
+/-10
±20

PGA plus MUX Settling
Time, maximum

Zero
Temperature
Drift,
(ppm/"C)
20
20
20
10
±20

Linearity
Error,
maximum
'/2 LSB
1 LSB
'/2 LSB
2 LSB
'/2 LSB

8 I'S at a gai n of 1
12 I'S at a gain of 16
40 I'S at a gain of 64
1001'S at a gain of 128

Minimum conversion time required for step input at rated
accuracy, typical
DVME-611A1DVME-612A 20 I'S at a gain of 1
1101'S at a gain of 128
DVME-611B/DVME-612B 81'S at a gain of 1
1021'S at a gain of 128
DVME-611C/DVME-612C 35 I'S at a gain of 1
1101'S at a gain of 128

Resolution and Throughput

DVME-611 A/DVME-612A
DVME-611 B/DVME-612B
DVME-611 C/DVME-612C
DVME-611 D/DVME-612D
DVME-611E1612E

DVME-611D/DVME-612D .0063% at a gain of 1
.20% at a gain of 128

25-pin Ootype female connector

ANALOG INPUT

.05% at a gain of 1
.20% at a gain of 128

DVME-611C/DVME-612C .010% at a gain of 1
.20% at a gain of 128

9-pin Ootype female connector

ANALOG SPECIFICATIONS

DVME-611/612A

Full-Scale Range Accuracy, minimum

Resolution

Conversion

Throughput

in bits

time

conversions/sec.

12
12
16
16
12

2Ol'S
41'S
351'S
400 mS

40,320
160,000·
18,667
2.5
see notes

21'S

External Trigger

TTL compatible, negative gOing edge.
Minimum pulse width=100 nS
Maximum pulse width=2l'S

Programmable Gain
Amplifier

Uses an AM-543MC for gains of
Xl,X2,X4,X8,X16,X32,X64,X128

DVME-611D/DVME-612D 400 mS at a gain of 1
400 mS at a gain of 128
Actual Conversion Time
DVME-611A/DVME-612A

20 I'S, typical
251'S, maximum

DVME-611B/DVME-612B

41'S, typical
51'S, maximum

DVME-611C/DVME-612C

35 I'S typical
451'S, maximum

II

200 mS, typical
400 mS, maximum
• Single channel, gain = 1, convert-on-read
DVME-611D/DVME-612D

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-25

DVME·6111612
Optional Multiplexer Expansion Boards

Model
DVME-641
DVME-643T
DVME-643H
DVME-643R
DVME-643S
DVME-645

Number of expansion channels
Input type
Single·ended
Differential
High-level,
32
16
non-isolated
8
Thermocouple
Isolated
8
High-level
Isolated
RTD
8
8
Strain Gage
16
8
Simultaneous
Sample/Hold
high-level nonisolated

ANALOG OUTPUT (For DVME·612 models only)
Number of Channels

2

Output Range

±10V, ±5, 0 to 5, or 0 to 10V

Digital Input Coding

Bipolar 2's complement, bipolar offset binary or unipolar straight binary

DVME·611/612 PROGRAMMING INFORMATION
The DVME-611/612 AID boards use ten registers for data acquisition and control purposes. Table 1 lists the DVME-611/612 registers
and their base address offsets. These registers are addressable
locations in the host system's address space.
Table 1: DVME-611/612 Hardware Register Functions
Address
Base + 0
through
Base + 63

Function
Read

Contents
Manufacturer's/Board's
identification code

Base + 128

Write

Command register

Base + 128

Read

Status register

Base + 130

Write

Interrupt ID register

Base + 132

Write

EOC/EOS F/F Reset

Base + 134

Write

Gain register

Base + 136

Write

Start channel register

Base + 136

Read

Current channel register

Base + 138

Write

Final channel register

12 Bits, bits DO through D3 not used

Base + 140

Write

Start conversion register

Minus full-scale,
-10V for 2's complement and offset
binary
OV for Unipolar

Base + 140

Read

A/D data register

Base + 142

Read

Status register

Base + 160

Write

D/A channel 0

Full-Scale Range
Accuracy

.05%, minimum

Base + 162

Write

D/A channel 1

Differential
Non-linearity

.5 LSB, minimum

Zero Temperature Drift

5 ppm/oe, maximum

Resolution
Reset

Command Register

Offset Temperature Drift 20 ppm/oe, maximum
Gain Temperature Drift

20 ppm/oe, maximum

Settling time

10 flS, maximum

Output Current

5 milliamps, typical

Output Impedance

50 millibhms, typical

The 16-bit command register controls how the DVME-611/612
boards scan their selected channels. Programming the command
register selects the modes for starting conversion, calibration, and
fast throughput. This register also enables the interrupt, channel
address auto-increment, and channel rescan capabilities. Figure
2 shows the command register format.

Status Register
POWER SUPPLY REQUIREMENTS
+5V de ±5% at 2.5 Amperes
On-board dc-to-dc converter generates ± 15V de for the
DVME-611/612 logic circuits

PHYSICAL-ENVIRONMENTAL
Outline Dimensions

9.19"W x 6.3"D x 0.6"H
(233.5 x 160 x 15.24 mm)

Weight

1 Ib 0.5 OZ (467.8 Grams)

Operating Temperature
Range

0 to 60 0 e

Storage Temperature
Range

-20 to 80 0 e

Relative Humidity

o to 90%, non-condensing

11-26

The DVME-611/612 status register indicates conditions relating to
conversion status, channel scanning information, and modes
selected. Figure 3 shows the sta.tus register format.

Total System Throughput
Total sample-to-sample throughput rate depends on the AlD-S/H
settling and conversion period and the user's software period.
During this software interval, data is transferred to the host and
the next A/D conversion is started. By combining fast throughput mode (DTACK* EOe holdoff) with convert-on-read-data,
throughput over 160 kHz may be achieved for gain = 1 in single
channel mode. Data transfer and host memory pOinter management may partially overlap AID conversion by using the converton-read mode.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·11941TEL (508) 339-30001TLX 174388/FAX (508) 339·6356

DVME·611/612
Location: Base + 128 (Word address)

15···· B

7

I I I

6

5

4

I

xx·.x

I

I

I

I

1
AID Conversion Start Source:

c-

O o Conversion begins when the host system writes to the start conversion
register.

0 1 Conversion begins when the host system writes to the start conversion
register or on an AID read operation.

-

1

a

Single channel conversion begins on an external trigger.

1 1 Conversion begins on external trigger or NO data read
'--

0 - Disable AID converter
1 - Enable AID converter
0 - Disable channel increment
1 - Enable channel increment
0 - Disable channel rescan
1 - Enable channel rescan (No start channel auto reload)
Reload slart channel al EOS

0 - Disable fast throughput mode
1 - Enable fast throughput mode
(Hold off DTACK' until EGG == 1)

0 - Disable calibration mode
1 - Enable calibration mode
0 - Disable EOS and EOC interrupts
1 - Enable EOC and EOS interrupts

Note: Bits 8 through 15 are not used

Figure 2:

DVME-611/612 Command Register Format

(WRITE)

Location: Base + 128 (Word address)

15 14 13 12

11

10

9

B

7

Conversion begins when the host system writes to the start conversion
register.

o

1 Conversion begins when the host system writes to the start conversion
register or on an AID read operation.

1 0 Single channel conversion begins on an external trigger.
, 1 Conversion begins on external trigger or NO data read.

0- AiD converter dIsabled
1-

AID converter enabled

0- Calibration mode disabled (external inputs accepted)
1-

o-

Calibration mode enabled (local reference channel)

Interrupts disabled

1 - Interrupts enabled

o, -

1_

1-

EOS flag is rest
EOS, set at EOC

(Ran starMinal
comparator output)
Busy converting, data invalid
End of NO conversion, data ready

II

Note: Bits 3 through 5 and 10 through 14 are nol used

Figure 3:

DVME-6111612 Status Register Format

(READ)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194/TEL (508) 339-3000/TLX 174388/FAX (508) 339-6356

11-27

DVME·611/612
Interrupt ID Register

15

This register contains the user-loaded interrupt ID number. On
receiving the interrupt request, the host system tests the interrupt
level using address lines A01 through A03. The host system must
then acknowledge using the lACK * and the daisy chain IACKIN*
signal lines. If the DVME-611/612 interrupt level matches the level
code on the address lines, the interrupt logic loads the interrupt
ID numberon to the VMEbus (low byte). If the EOC/EOS interrupts
and the multiple channel scan option are enabled, the board loads
the ID number plus one on to the VMEbus data lines. The host system may use these ID's to differentiate the EOC and EOS interrupts. Figure 4 shows the register format of the interrupt ID register.
(Write)

Word address: Base + 130
15

14

13

12

11

10

(Write)

Word address: Base + 138

9

8

7

6

14

13

12

11

10

Figure 7:

9

876543210

Final Channel Register Format

Start Conversion Register
Writing any value to this register starts an AID conversions on the
channel indicated by the current channel register. Figure 8 shows
the format of this register.

x = Don't Care
5

4

321

0

xIID711D611DSIID411D311D211Dl I 0 I

Word address: Base + 140
15

14

13

12

11

10

(Write)
9

8

7

6

5

4

I x I x I x I x I x I x I xl xl x I x I x I xl
Figure 4:

3

x

2

0

I x I xI xI

Interrupt 10 Register Format
Figure 8:

Start Conversion Register Format

Gain Register and Digital Outputs
The least three significant bits of this register, when programmed,
assign the gain to the differential amplifier in the PGA section. This
register is programmable for gains from 1 to 128 in binary increments. Bits 6 and 7 of this register provide a general purpose digital output. The output signal lines from these two bits are available
on pins 18 and 6 of the J4 connector. Figure 5 shows the gain
register format.

Word address: Base + 134
15

14

13

12

11

10

AID Data Register
The 16 bits of the AID data register are connected to 16 VMEbus
data lines. The host system may read this register to obtain the binary data of the analog input from the channel selected. Models
DVME-611/612 A and B do not use the four least significant data
bits. The value of these bits defaults to zero for these models.
Figure 9 shows the format of this register.

(Write)
9

8

7

6

5

4

3

2

0

8

7

6

(Read)
5 4

3

2

o

I x I x I x I x I x I x I x I x IGPllGPOI x I x I x IG21 G11 GOI
Figure 5:

Gain Register Format

MS8

LS8

Figure 9:
Start Channel/Current Channel Register
User must load this register with the starting channel address
when scanning a group of channels. This register contains the address of the channel being scanned. Figure 6 shows the format
of this register.

14

13

12

Figure 6:

11

10

DIA Channel Registers
The DVME-612 boards have two D/A channel registers. These
registers form the input to the 12-bit hybrid D/A converters. These
registers are programmable by the most significant 12 bits from
the VMEbus data lines. Figure 10 shows the format of these
registers.

(Read/Write)

Word address: Base + 136
15

9

876543210

Start Channel/Current Channel Register

MS8

LS8

Figure lOa:
Final Channel Register
User must load this register with the final channel address when
scanning a group of channels. The on-board comparator compares this register contents with the current channel register and
generates the end of scan (EOS) signal. Figure 7 shows the format of this register.

D/A Channel 0 Register Format
(Write)

MS8

LS8

Figure lOb:

11-28

AID Register Format

D/A Channell Register Format

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

DVME-611/612
EOC/EOS F/F Register

Table 3:

DVME-611/612 Analog Input Connector..J2

PIN #
24
12
25

CONFIGURATION
SINGLE-ENDED
DIFFERENTIAL
CHANNEL8
CHANNEL 8 HIGH
CHANNEL 24
CHANNEL 8 LOW
ANALOG RETURN
ANALOG RETURN

Writing any value to this register resets the EOC/EOS flip-flops.
Figure 11 shows the format of this register.
Word address: Base + 132
15 14 13 12 11 10 9

8

7

6

(Write)
5 4

3

2

0

Ixlxlxlxlxlxlxlxlxlxlxlxlxlxlxlxl
Figure 11:

EOC/EOS F/F Register Format

(These F/F's are also reset by the next start of conversion.)

110 Connections
The DVME-611/612 AID boards use the J1 and J2 connectors for
analog input connections and the J4 connector for channel expansion. The DVME-612 uses the J3 connector for analog output connections. Tables 2.3.4, and 5 list the 110 signals of the J1, J2, J3,
and J4 connector respectively.
Table 2:

DVME-611/612 Analog Input Conneetor..J1

PIN#
24
12
25

CONFIGURATION
SINGLE-ENDED
DIFFERENTIAL
CHANNELO IN
CHANNEL 0 HIGH
CHANNEL 16 IN
CHANNEL 0 LOW
ANALOG RETURN
ANALOG RETURN

10
23
11

CHANNEL 1 IN
CHANNEL 17 IN
ANALOG RETURN

CHANNEL 1 HIGH
CHANNEL 1 LOW
ANALOG RETURN

21
9
22

CHANNEL21N
CHANNEL 18 IN
ANALOG RETURN

CHANNEL 2 HIGH
CHANNEL 2 LOW
ANALOG RETURN

7
20
8

CHANNEL31N
CHANNEL 19 IN
ANALOG RETURN

CHANNEL 3 HIGH
CHANNEL3LOW
ANALOG RETURN

18
6
19

CHANNEL41N
CHANNEL 20 IN
ANALOG RETURN

CHANNEL 4 HIGH
CHANNEL 4 LOW
ANALOG RETURN

4
17
5

CHANNEL51N
CHANNEL 21 IN
ANALOG RETURN

CHANNEL 5 HIGH
CHANNEL 5 LOW
ANALOG RETURN

15
3
16

CHANNEL 6 IN
CHANNEL 221N
ANALOG RETURN

CHANNEL 6 HIGH
CHANNEL 6 LOW
ANALOG RETURN

1
14
2

CHANNEL 71N
CHANNEL 23 IN
ANALOG RETURN

CHANNEL 7 HIGH
CHANNEL 7 LOW
ANALOG RETURN

Table 4:
PIN#
1
6
4
9

DVME-612 Analog Output Conneetor..Ja
SIGNAL LINE
CHANNEL 0 VOUT
ANALOG RETURN
CHANNEL 1 VOUT
ANALOG RETURN

10
23
11

CHANNEL 9
CHANNEL 25
ANALOG RETURN

CHANNEL 9 HIGH
CHANNEL9LOW
ANALOG RETURN

21
9
22

CHANNEL 10
CHANNEL 26
ANALOG RETURN

CHANNEL 10 HIGH
CHANNEL 10 LOW
ANALOG RETURN

7
20
8

CHANNEL 11
CHANNEL 27
ANALOG RETURN

CHANNEL 11 HIGH
CHANNEL 11 LOW
ANALOG RETURN

18
6
19

CHANNEL 12
CHANNEL 28
ANALOG RETURN

CHANNEL 12 HIGH
CHANNEL 12 LOW
ANALOG RETURN

4
17
5

CHANNEL 13
CHANNEL29
ANALOG RETURN

CHANNEL 13 HIGH
CHANNEL 13 LOW
ANALOG RETURN

15
3
16

CHANNEL 14
CHANNEL 30
ANALOG RETURN

CHANNEL 14 HIGH
CHANNEL 14 LOW
ANALOG RETURN

1
14
2

CHANNEL 15
CHANNEL 31
ANALOG RETURN

CHANNEL 15 HIGH
CHANNEL 15 LOW
ANALOG RETURN

Table 5:

PIN#
13
25
12
24
11
23
10
22
16
9
8
20
7
19
17
18
6
4
21
5
1
14
2, 15
3

DVME-611/612 Expansion Conneetor..J4
SIGNAL LINE
EXTERNAL CHANNEL ADDRESS 0 OUT
EXTERNAL CHANNEL ADDRESS 1 OUT
EXTERNAL CHANNEL ADDRESS 2 OUT
EXTERNAL CHANNEL ADDRESS 3 OUT
EXTERNAL CHANNEL ADDRESS 4 OUT
EXTERNAL CHANNEL ADDRESS 5 OUT
EXTERNAL CHANNEL ADDRESS 6 OUT
EXTERNAL CHANNEL ADDRESS 7 OUT
DIGITAL GROUND
EXTERNAL CHANNEL ADDRESS VALID OUT
START CONVERSION STROBE OUT
SETTLING DELAY* IN
END OF CONVERSION OUT
END OF SCAN OUT
EXTERNAL TRIGGER IN*
GENERAL PURPOSE OUTPUT 0
GENERAL PURPOSE OUTPUT 1
DIGITAL GROUND
RESERVED
RESERVED
EXTERNAL ANALOG LOW IN
EXTERNAL ANALOG HIGH IN
ANALOG COMMON
+5V de REFERENCE OUT

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-29

DVME·611/612
DVME-611/612 Board Identification Code
Byte
Address
Base -Ie 1
+3
+5
+7
+9

ASCII
Code
V
M
E
I
D

Function
Identifier
This ASCII code is present
for all DATEL VMEbus boards

+ OB

D

Manufacturer ID

+ OD

A

DATisthelDforDATEL

+ OF

T

+ 11

d

+ 13

V

+ 15

M

+ 17

E

+ 19

-

+ 1B
+10

6
1

+ 1F

1 or 2

Board model number

DATEL VMEbus Short I/O Memory Organization
Base
Address

Board
Model Number

Function

Base + 0
through
Base + 63

All DATEL
VMEbus
boards

Manufacturer's and Board's
identification code

Base + 64
through
Base + 77

DVME-660

48 line digital 1/0 board

-----------------------

Not Used -----------------------

DVME-611
DVME-612

DVME-611: 32 single-endedl
16 differential channel AID
board

Base + 78
through
Base + 127
Base + 128
through
Base + 143

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 D/A channels
DVME.602

DVME-602: 4-channel isolated board for measuring
thermocouples, RTD's, strain
gages, high-level, low-level,
and 4-to-20mA current loop
inputs

Base + 152
through
Base + 159

---------------------.-

Not Used

Base + 160
through
Base + 175

DVME-612
DVME-624
DVME-628

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 D/A channels
DVME-624: 4-channel isolated D/A board
DVME-628: 8-channel D/A
board

Base + 176
through
Base + 191

-----------------------

Base + 192
through
Base + 255

.----------------.----- Not Used -----------------------

Base + 144
through
Base + 151

Fast Throughput Mode
This mode holds off response of the DTACK* VMEbus signal
with the simultaneous ANDing of three conditions: command
register bit 5 = 1, EOC =0 and a host read of the AID data
register. While DTACK* is held off, the host CPU executes wait
states. When AID conversion finishes, EOC = 1 and DTACK* is
released. Normally the attempted AID data read now completes,
and data is transferred without any EOC polling. Fast throughput should be used with caution since the host must be completely dedicated to AID data acquisition.

11-30

Not Used

.----------------------

-----------------------

I
I

I

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DVME-624
ISOLATED 4-CHANNEL,
VMEbus D/A BOARD

12-~IT,

FEATURES
• 4-Channel memory mapped D/A board
• 300 VRMS channel-to-channel and channel-to-bus
isolation
• Hardware compatible with VMEbus specifications
• On-board isolated dc-to-dc power converter
• Optional 6 I'S or 30 I'S settling time models
• 12-Bit resolution
• Choice of output voltages:
a. Oto 5V dc
b. 0 to 10V dc
c. ±2.5V dc
d. ±5V dc
e. ±10V dc
• OptionaI4-to-20mA current loop capability conforming
to ISA standards
• ± 112 LSB differential non-linearity
• ± 0.05% Full-scale range accuracy

GENERAL DESCRIPTION
The DVME-624 is DATEL:s 12-bit, 4-channel D/A board, totally
compatible with VMEbus specifications. In a typical application the board provides analog outputs in real-time to the host
system at a high speed. The different full-scale output voltage
ranges the board offers conform to process control and test and
measurement industrial requirements.
Each channel is configurable to different output voltage ranges.
The salient feature of the DVME-624 board is the 300 VRMS
channel-to-channel and channel-to-bus isolation. The board
uses high performance optoisolators to provide the isolation.
An on-board dc-to-dc power converter provides isolated power
to each D/A converter section.
The isolation makes the DVME-624 an ideal choice for applications where a low-level signal superimposes a high voltage
such as in testing of power supplies. The channel-to-bus isolation protects the host system against any catastrophic
damages due to an external malfunction such as an actuator
failure.
The DVME-624 offers ± 1/2 LSB differential non-linearity
and operates at ± 0.05% full-scale range accuracy. The
DVME-624 models are available at two different settling
times. The lower cost DVME-624C1 and DVME-624V1
models offer 30 I'S settling time and the DVME-624C2 and
DVME-624V2 models offer 6 I'S settling time. The DVME624 may be obtained with an optional 4-to-20mA industrial
current loop outputin addition to the voltage outputs. Refer
to the ordering information for models with current loop
option.

Functionally, the digital data from the VME host system is transferred through a 12-bit data register to one-of-four D/A sections.
The DVME-624 converts the 12 most significant bits from the VME
data bus to an analog output. Data from the host system may be
in straight binary, offset binary, or 2's complement coding. The D/A
converter sections are optically isolated from the VME interface
logic. The DVME-624 uses monolithic D/A converters to increase
the product's reliability and endurance.
The DVME-624 D/A boards will be shipped with a user's manual.
The user's manual describes the installation and calibration procedures for different applications and explains the theory of operation of the DVME-624. The DVME-624 is shipped with an
68010 assembly language diagnostic program example on a 5 1/4"
VERSAdos formatted diskettes. Consult factory regarding the
availability of the diagnostic program's source code in other
disk formats.

ORDERING INFORMATION
DVME-624

1

T~~~ '" ,sso,,,", "m,
-

61'S Settling time

V - Voltage output only
C - Voltage and 4·to·20 mA current
loop output

III
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-31

DVME·624
INTERNAL HARDWARE REGISTER/SOFTWARE
ASSIGNMENTS

VME Interface
The DVME-624 interfaces to the host system using the P1 connector. The board uses short 1/0 space address lines and 16 data
lines. On-board switches select the base address of the board. The
board responds to the address modifier codes 29H, 2DH, 39H, and
3DH for data output purposes. The DVME-624 generates the data
acknowledge (DTACK*) signal to notify acceptance of data from
the VME data lines, DOO through D15. The DTACK* Signal is
jumper-selectable for delay times from 125 nanoseconds to 1000
nanoseconds, accommodating different host systems. Figure 1
shows the functional block diagram of the DVME-624 D/A board.
FUNCTIONAL SPECIFICATIONS
(Typical at 25 degrees Celcius, Vexc
ohms, unless otherwise specified.)

=

+24V dc, Rloop

= 250

INTERFACE SPECIFICATIONS

Register Memory Mapping

Relative
Address

Function

READIWRITE

o through 63

Board Identification
Code

64 through 127

See Note 1

Read Only

128 through 159

See Note 2

Write Only

160

D/A Channel 0

Write Only

162

D/A Channel 1

Write Only

164

D/A Channel 2

Write Only

Read Only

166

D/A Channel 3

Write Only

Data Bus

16 bits

168 through 255

See Note 2

Write Only

Address Bus

Short 1/0 Space,
16 address lines

Note 1: These addresses are redundant with ID PROM
addresses, base + 0 through base + 63.

Address modifiers codes

Codes used 29H, 2DH, 39H,
and 3DH

Memory Mapping

Short 1/0 space, user or
supervisor 256 bytes allocated per board (A16:D16
slave).

Note 2: These addresses are redundant in 8-byte blocks
with the DAC data registers, base + 160 through
base + 166.
The VMEbus SYSCLK signal is required.

4-lo·20mA
OUT

V OUT

---...--4

A01·A07

V
M

SYSCLK

E

4-to-20mA
OUT

DTACK"
B

VOUT

---...--1

U

DSO'

S

DS1*
WRITE·

4-to-20mA
OUT

V OUT

--_--I

A08·A15

4-to-20mA

AMO·AM5
LWORD-

OUT

lACK'
4·CHANNEL
ISOLATED
dC-lo-de
POWER
CONVERTER

+12V

GROUND

Figure 1: DVME-624 Functional
Block Diagram

11-32

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

DVME-624
CONNECTOR SPECIFICATIONS
VME bus -

CURRENT LOOP

P1 . . . . . . . . . . .. 96-pin male DIN connector

Analog Output - J1 . . . . . . .. 25-pin D Type female connector, Amp PIN 745783-1
or equivalent

Specification

Minimum

I

Maximum

-

Accuracy

0.1% of FSR

ANALOG OUTPUT SPECIFICATONS

Excitation
(user-supplied)

15V dc

36Vdc

Number of Channels ........ 4

Load resistance

100 Ohms

1000 Ohms

Channel-to-channel . . . . . . .. 300 VRMS, sustained
Isolation
maximum

Isolation
channel-to-channel

300VRMS

-

Isolation
output-to-bus

300VRMS

-

Output full-scale ........... 0 to 5V dc
0 to 10V dc
voltage ranges
±2.5V dc
±5Vdc
± 10V dc (standard)

PHYSICAL CHARACTERISTICS

Input data coding .......... Bipolar 2's complement
Bipolar offset binary
Unipolar straight binary
Resolution . . . . . . . . . . . . . .. 12 Bits. Uses 12 most
significant data bits
from the data bus.
Ignores bits DO through
D3.

Outline Dimensions ........ 9.19"W x 6.3"D x 0.6"H
(233.35 x 160 x 15.24 mm)
Weight. . . . . . . . . . . . . . . . . .. 9.6 oz (272.3 grams)
Operating temperature. . . . .. 0 to 60°C
range
Storage temperature....... -20 to +80°C
range

Reset .................... Minus full-scale, output
resets to O.OOOV dc

Relative humidity .......... 0 to 90%, non-condensing

Current Loop .............. 4-to-20 mAo Meets ISA
standard 550.1 Type 4
Class U

DVME-624 ANALOG OUTPUT CONNECTOR J1

Excitation Voltage .......... 15 to 36V dc
(User-supplied)

The DVME-624 provides analog outputs using the J1 connector.
Depending on the model, the J1 connector contains voltage and
current loop outputs. Figure 2 shows the output Signals on the J1
connector.

PERFORMANCE

Specification

Minimum

I

Typical

Differential
non-linearity

-

-

Zero temperature
drift

-

3 ppm/DC

Accuracy

0.05% of FSR

I

Maximum

0.5 LSB
5 ppm/DC

Offset temperature

-

5 ppm/DC

10 ppm/DC

Gain temp drift

-

15 ppm/DC

30 ppm/DC

Settling time:
DVME·624Vl
DVME·624Cl

-

-

30 f1seconds

DVME-624V2
DVME-624C2

-

-

6 f1seconds

Output current

-

±5mA

-

Output impedance

-

50 milliohms

-

POWER SUPPLY REQUIREMENTS
+5V dc ±0.5% at 1.0A typical, 1.2A maximum
+ 12V dc ±2.0% at O.4A typical, .7A maximum

PIN
NUMBER
1
2
3
4
5
6
7
8
g

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DESCRIPTION
DACOVOUT
DACO I LOOP
DACOV LOOP
DAC 1 VOUT
DAC 11 LOOP
DAC 1 V LOOP
DAC 2 V OUT
DAC 21 LOOP
DAC2 V LOOP
DAC 3VOUT
DAC31 LOOP
DAC3V LOOP
DAC 0 ANALOG RETURN
DAC 0 ANALOG RETURN
DAC 1 ANALOG RETURN
DAC 1 ANALOG RETURN
DAC 2 ANALOG RETURN
DAC 2 ANALOG RETURN
DAC 3 ANALOG RETURN
DAC 3 ANALOG RETURN

III

Figure 2: Analog output pinout details

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-33

DVME-624
15

DVME-624 DATA FORMAT
The DVME-624 uses a 12-bit D/A converter for converting the digital data to analog signal. The board uses the 12 most significant
bits of the VME data lines as input signals. Figure 3 shows the data
format the DVME-624 is designed for.

ASCII
Code

Base + 1
+3
+5
+7
+9

Function

V
M
E
I
D

Identifier
This ASCII code is present
for all DATEL VMEbus boards

+ OB

D

Manufacturer ID

+ 00

A

DAT is the ID for DATEL

+ OF

T

+ 11
+ 13

d
'\

V

+ 15

M

+ 17

E

+ 19

-

+ 1B

6

+10

2

+ 1F

4

MSB

DATA BITS

3

LSB

x

o

2

I

X

I

X

I

X

Not Used by DVME-624

Figure 3: DVME-624 data format

DATEL VMEbus Short 110 Memory Organization

DVME-624 Board Identification Code
Byte
Address

I

4

Board model number

Base
Address

Board
Model Number

Function

Base + 0
through
Base + 63

All DATEL
VMEbus
boards

Manufacturer's and Board's
identification code

Base + 64
through
Base + 77

DVME-660

48 line digital 110 board

-.---------------------

Not Used -----------------------

DVME-611
DVME-612

DVME-611: 32 single-endedl
16 differential channel AID
board

Base + 78
through
Base + 127
Base + 128
through
Base + 143

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 O/A channels
DVME-602

DVME-602: 4-channel isolated board for measuring
thermocouples RTO's, strain
gage, high-level, low-level,
and 4-to-20 mA current loop
inputs
.

Base + 152
through
Base + 159

-----------------------

Not Used

Base + 160
through
Base + 175

DVME-612
DVME-624
DVME-628

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 D/A channels
DVME-624: 4-channel isolated D/A board

Base + 144
through
Base + 151

-----------------------

DVME-628: 8-channel D/A
board

11-34

Base + 176
through
Base + 191

-----------------------

Base + 192
through
Base + 255

-----------------------

Not Used -----------------------

I
I
Not Used -----------------------

I

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DVME·626
16-BIT, &-CHANNEL
VMEbus D/A BOARD
FEATURES

• 6 D/A channels
• 16-Bit resolution
• 14-Bit monotonicity
• Designed to meet precision servo control
requirements
• Complete hardware-compatible with VMEbus
specifications
• 15 I'Second settling time
• Available in two models:
DVME-626V1 for ± 10V de output
DVME-626V2 for 0 to +10V dc and ±5V dc outputs
• Three input coding types:
A. Bipolar 2's complement
B. Bipolar offset binary
C. Unipolar straight binary
• Up to 0.005% full-scale range accuracy

• ±0.005% of full-scale range differential nonlinearity
• On-board dc-to-dc power converter supplies ±15V dc
for internal logic circuits

The OVME-626 is DATErs high resolution VMEbus-based OIA board that provides analog outputs for up to 6 channels. The 16-bit
OIA board is designed to deliver exceptionally high-performance in rugged industrial environments. The 14-bit monotonicity and
0.005% FSR accuracy makes the board an ideal choice for preCision servo control and similiar applications. The OVME-626 is
supported by VERSAdos-based and POOS·based software for calibration and diagnostics.

GENERAL DESCRIPTION

The DVME-626 is a D/A member of DATELs VMEbus family.
The board delivers preCision and performance that makes it
easily acceptable for various test and control applications. Onboard hardware resources provide 6 high-resolution analog
outputs with an accuracy of better than 0.005% of full-scale
range. The DVME-626 accepts 16-bit digital data, coded in bipolar 2's complement, bipolar offset binary, or unipolar straight
binary. The board is rigorously tested under extreme environmental conditions to meet DATELs stringent quality assurance
requirements.
The DVME-626 easily fits into a VMEbus card cage and is addressable using short I/O space address lines. The on-board
switches select the base address of the board. Functions relating to input data coding and output voltage range are easily
selectable using jumpers.
Functionally, the DVME-626 consists of a VMEbus interface
section and digital-to-analog converter (DAC) section. The
DAC data register section contains a data register and D/A converter for each section. One unique feature of the DVME-626
is that the DAC outputs will reset to O.OOOV during reset, regardless of whether unipolar or bipolar outputs are selected. Figure
1 shows the functional block diagram of the board.

a

The DVME-626 D/A board will be shipped with a user's manual. The user's manual describes the installation and calibration
procedures for different applications and explains the theory
of operation of the board. The user's manual also contains information on troubleshooting the board.
The board is shipped with an example 68010 assembly language diagnostic program on a 5 114" floppy diskette, formatted for either VERSAdos or PDOS operating systems. Consult
the factory regarding the availability of the diagnostic program's source code on other disk formats.

ORDERING INFORMATION

DVME-626V

4

1 - + 10V dc output range
2 - Oto 10V and ±5V dc output
ranges

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-35

•

DVME·626
VMEbus Interface
The DVME-626 interfaces to the host system using the P1 connector. The board uses short I/O space address lines and 16
data lines. On-board switches select the base address of the
board. The board responds to address modifier codes 29H,
2DH, 39H, and 3DH for data output purposes. The DVME-626
generates the data acknowledge (DTACK *) signal to notify acceptance of data from the VMEbus data lines, DOO through D15.
The DTACK * signal is jumper-selectable for delay times from

VoutO

125 nanoseconds to 1000 nanoseconds, accommodating
different host CPU response times.
The interface logic decodes the VMEbus control lines
WRITE
DSO DS1
and SYSRESET to select and control the interface. These signals control the board select and
the VMEbus transfer functions. The DVME-626 uses programmable array logic (PAL) devices for interface and control,
guaranteeing true asynchronous operation.

*,

*,

*,

*

-----1

Voul1

~-----I

Yout2

-----I

000·015

AO-A?

V
M
E
Vout3

SYSCLK

-----1
OTACK'

080'
Vout4

------1

VourS

------i

OSlO
WRITE'
AS'

A08·A15

LWORD'
AMO-AMS
lACK'

lOAC5

$YSRESET"

Figure 1:

DVME-626 Functional Block Diagram

FUNCTIONAL SPECIFICATIONS

CONNECTOR SPECIFICATIONS

(Typical at 25 degrees Celcius, unless otherwise noted)

VMEbus P1 Connector ....... 96-pin male DIN
connector.
J1 and J2 Analog Output ..... 25-pin D-type female
Connectors
connector, DB-25S

INTERFACE SPECIFICATIONS
Data Bus .................. 16 Bits (A16:D16 slave)
Address Bus ............... Short I/O Space; 16
address lines

ANALOG SPECIFICATONS

Address Modifier Codes ..... Codes used 29H, 2DH,
39H, and 3DH

Number of Channels •....... 6, non-isolated

Memory Mapping ........... Short I/O space, user or
supervisor, 256 words allocated per board.

Output Range
DVME-626V1 ............. ±10V dc
DVME-626V2 ............. 0 to 10V and ± 5V dc

*

Data Transfer .............. DTACK signal line.
Acknowledges the VMEbus host that data has
been placed or accepted
from the VMEbus data
lines.

ANALOG OUTPUT

Digital Input Coding .•....... Bipolar 2's complement
Bipolar offset binary
Unipolar straight binary
(jumperable)

Note: The VMEbus SYSCLK signal is required.

11-36

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

DVME·626
Resolution ................ 16 Bits
Monotonicity .............. 14 bits
Reset .................... Output resets to O.OOOV dc
at power-on
Accuracy ................. 0.005% of FSR, minimum
Differential ................ 0.005% of FSR, maximum
nonlinearity

Figure 2:

DVME·626 DAC Data Register Format

Zero temperature drift ....... 5 ppm/oC, typical
Offset temperature drift ...... 8 ppm/oC, typical

1/0 CONNECTIONS

Gain temperature drift ....... 20 ppm/oC, typical

The DVME-626 D/A boards provide front panel J1 and J2
connectors for analog output connections. Tables 2 and 3
list the output signals of the J1 and J2 connectors
respectively.

Settling time .............. 15 flseconds
Output current ............. ±5 mA, typical
Output impedance .......... 50 milliohms, typical
POWER SUPPLY REQUIREMENTS
+5V dc ±0.5% at 3.0 Amperes, typical
Power Supply .............. ±0.002%, typical
Rejection
PHYSICAL CHARACTERISTICS
Outline Dimensions ......... 9.19" Wx6.3" DxO.6" H
(233.35x160x15.24 mm)
Weight ................... 1 lb. (453.6 grams)
Operating Temperature•...... 0 to +60° C Range
Range
Storage Temperature ........ -20 to +80 0 C Range
Range
Humidity .................. 0 to 90%, non-condensing
DVME·626 PROGRAMMING INFORMATION
The DVME-626 contains six programmable registers that store
digital data for each 16-bit D/A converter. The board responds
only to word data transfers on write operations. Table 1 shows
the addresses of the identification code and the registers.
Figure 2 shows the format of the DAC data register.
Table 1:
ADDRESS
Base + 0
through
Base + 63

Table 2:
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DVME·626 ANALOG OUTPUT CONNECTOR J1
DESCRIPTION
DAC 0 V OUT
NO CONNECTION
NO CONNECTION
DAC 1 VOUT
NO CONNECTION
NO CONNECTION
DAC 2VOUT
NO CONNECTION
NO CONNECTION
DAC 3 VOUT
NO CONNECTION
NO CONNECTION
NO CONNECTION
DAC 0 ANALOG RETURN
DAC 0 ANALOG RETURN
NO CONNECTION
DAC 1 ANALOG RETURN
DAC 1 ANALOG RETURN
NO CONNECTION
DAC 2 ANALOG RETURN
DAC 2 ANALOG RETURN
NO CONNECTION
DAC 3 ANALOG RETURN
DAC 3 ANALOG RETURN
NO CONNECTION

DVME·626 Register Locations.

FUNCTION
Read

CONTENTS
Manufacturer's/Board's
identification code

Base + 160 Write

D/A Channel 0

Base. + 162 Write

D/A Channel 1

Base + 164 Write

D/A Channel 2

Base + 166 Write

D/A Channel 3

Base + 168

Write

D/A Channel 4

Base + 170

Write

D/A Channel 5

II
DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·11941TEL (508) 339-30001TLX 174388/FAX (508) 339·6356

11-37

DVME·626
Table 3:

DVME-626 ANALOG OUTPUT CONNECTOR J2

PIN#

Base
Address

DESCRIPTION

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DAC4VOUT
NO CONNECTION
NO CONNECTION
DAC5VOUT
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
DAC 4 ANALOG RETURN
DAC 4 ANALOG RETURN
NO CONNECTION
DAC 5 ANALOG RETURN
DAC 5 ANALOG RETURN
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION

Base
Base
Base
Base
Base

Base+64
through
Base+n
Base+78
through
Base+127

FUNCTION

48 line digital I/O board

------------------------ -- Not Used --------------------------

DVME-612

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 D/A channels

Base+144 DVME-602
through
Base+151

DVME-602:4-channel
isolated board for measuring
thermocouples, RTD's, strain
gage, high-level, low-level,
and 4-to-20 mA current loop
inputs

Base+152
through
Base+159

------------------------ -- Not Used --------------------------

Base+160 DVME-612
through
Base+175
DVME-624

Base + OB
Base + OD
Base + OF

D
A
T

Manufacturer 10.
DATisthelDforDATEL

Base+176
through
Base+191

11
13
15
17
19
1B
10
1F

d
V
M
E

Board model number

Base+192
through
Base+255

11-38

DVME-660

DVME-611: 32single-endedl
16 differential channel AID
board

Identifier.
This ASCII code is present
for all DATEL VMEbus
boards

+
+
+
+
+
+
+
+

1
3
5
7
9

Function

Base+128 DVME-611
through
Base+143

V
M
E
I
D

Base
Base
Base
Base
Base
Base
Base
ijase

+
+
+
+
+

ASCII
Code

Board
Model Number

All DATEL
Manufacturer's and Board's
Base+O
VMEbus boards identification code
through
Base+63

DVME-626 Board Identification Code

Byte
Address

DATEL VMEbus Short I/O Memory Organization

DVME-626
DVME-628

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 D/A channels
DVME-624: 4-channel isolated board
DVME-626: 6-channel 16-bit
D/A board
DVME-628: 8-channel 12-bit
D/A board

_______ w ________________

-- Not Used --------------------------

---------------._------- -- Not Used -----------------•••••-•.•

-

6
2
6

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DVME·628
12-BIT, a-CHANNEL
VMEbus D/A BOARD
FEATURES

• 8 OIA channels
• 12-Bit resolution
• Complete hardware-compatible with VMEbus specIfIcations.
• 6 ",Second settling time.
• Three types of input coding:
A. Bipolar 2's complement
B. Bipolar offset binary
C. Unipolar straight binary
• Five output voltage ranges:
A. Oto +5V dc
B. 0 to +10V dc
C. ±2.5V dc
O. ±5Vdc
E. ±10V dc
• Up to 0.05% full-scale range accuracy.
• ± 112 LSB differential nonlinearity
• 4-to-20 mA current loop output capability for
OVME-628C model.
• On-board dc-to-dc power converter supplies ± 15V dc for
internal logic circuits.

THE DVME-628 IS DATEL's HIGH-END, VMEbus-BASED DIA BOARD THAT PROVIDES ANALOG OUTPUT FOR UP TO
8 CHANNELS. THE 12-BIT DIA BOARD, WITH 6 MICROSECOND SETTLING TIME, IS DESIGNED TO DELIVER HIGHPERFORMANCE IN PROCESS CONTROL, TEST INSTRUMENTATION AND SIMILAR APPLICATIONS THE THREE INPUT
CODING SCHEMES AND FIVE ANALOG OUTPUT VOLTAGE RANGES MAKES THE BOARD AN IDEAL CHOICE FOR
MOST INDUSTRIAL APPLICATIONS.
GENERAL DESCRIPTION
DATEt:s VMEbus family of boards offer a complete solution to various data acquisition applications. The DVME-628 is the DIA member of this family, providing up to 8 analog outputs for the host
VMEbus system. The DIA board offers a resolution of 12 bits and
operates with an accuracy of beter than 0.05% of full-scale range.
The board is rigorously tested under extreme environmental conditions for DATEt:s stringent quality assurance requirements.
The DVME-628 easily fits into a VMEbus card cage and is addressable using short 110 space address lines. The on-board switches
select the base address of the board. Functions relating to input
data coding and output voltage range are easily selectable using
jumpers.
Functionally, the OVME-628 consists of a VMEbus interface section and a digital-to-analog conveter (OAC) section. The OAC data
register section contains a data register and OIA converter for each
section. For OVME-628C models the OAC section also contains
voltage to 4-to-20 mA current loop conversion logic for each channel. One unique feature of the OVME-628 is that the OAC outputs
will reset to O.OOOV during reset regardless of whether unipolar or
bipolar outputs are selected.

The OVME-628 O/A board will be shipped with a user's manual.
The user's manual describes the installation and calibration procedures for different applications and explains the theory of operation of the board. The user's manual also contains information on
troubleshooting the board.
The board is shipped with an example 68010 assembly language
diagnostic program on a 5 1/4" floppy diskette, formatted using
VERSAdos. The diagnostic program source code is available in
hard copy from OATEL. Consult the factory regarding the availability of the diagnostic program's source code in other disk formats.

ORDERING INFORMATION
OVME-628

]v -Voltage outputs only

19 -Voltage
and 4-to-20mA
current loop outputs

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-39

•

DVME·628
VMEbus Interface
The DVME-628 interfaces to the host system using the P1 connector. The board uses short 1/0 space address lines and 16 data lines.
On-board switches select the base address of the board. The
board responds to address modifier codes 29H, 2DH, 39H, and
3DH for data output purposes. The DVME-628 generates the data
acknowledge (DTACK * ) signal to notify acceptance of data from
the VMEbus data lines, DOO through D15. The DTACK* signal is

VoutO

jumper-selectable for delay times from 125 nanoseconds to 1000
nanoseconds, accommodating different host systems.
The interface logic decodes the VMEbus control lines WRITE * ,
DSO * ,DS1 * , and AS * to provide the interface control signals.
These signals control the board select and the VMEbus transfer
functions. The DVME-628 uses programmable array logic (PAL)
devices for interface and control, guaranteeing true asynchronous
operation.

~---.,;

lautO

Vout1 ~---.,;

!oull

AO-A7

lout2

V
M
E
b

Vout3 ~---.,;

SYSClK
DTACK"

lout3

050·
OSI'
WAITE'
AS'

Vout4~---"T1

lout4

A08·A15
Vout5 ~---.,;

louiS
LWORO"
AMO-AM5

lACK'

Vout6~---~

SYSAESEr

lout6

Vout7~----rI

lout?
LDAC 7

Figure 1:

DVME-628 Functional Block Diagram

FUNCTIONAL SPECIFICATIONS
(Typical at 25 degrees Celcius, unless otherwise noted)

Interface specifications
Data Bus ............•.... 16 Bits (A16:D16 slave)
Address Bus .............. Short I/O Space; 16 address
lines
Address Modifier Codes ..... Codes used 29H, 2DH,
39H, and 3DH
Memory Mapping .•.•...... Short I/O space, user or
supervisor, 256 words allocated per board
Data Transfer .............. DTACK * signal line.
Acknowledges the VMEbus
host that data has been
placed or accepted from the
VMEbus data lines

11-40

CONNECTOR SPECIFICATIONS
VMEbus P1 Connector ...... 96-pin male DIN connector
J1 and J2 Analog Output .... 25-pin D-type female
Connectors
connector.
ANALOG SPECIFICATONS
ANALOG OUTPUT
Number of Channels. . . . . .. 8 non-isolated
Output Range ............. 0 to +5V dc
Oto +10Vdc
± 2.5Vdc
± 5Vdc
± 10Vdc
Digital Input Coding ........ Bipolar 2's complement
Bipolar offset binary
Unipolar straight binary
NOTE: The VMEbus SYSCLK Signal is required.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DVME·628
Table 1:

Resolution ............... 12 Bits
Reset .................... Output resets to O.OOOV dc
at power-on
Accuracy ................. 0.05% of FSR, minimum
Differential ............... 0.5 LSB, maximum nonlinearity

DVME-628 Register Locations

ADDRESS

FUNCTION

Base + 0
through
Base + 63

Read

CONTENTS
Manufacturer's/Board's
identification code

a

Base + 160

Write

D/A Channel

Zero Temperature Drift ...... 3 ppml oC, typical
5 ppml oC, maximum

Base + 162

Write

D/A Channel 1

Base + 164

Write

D/A Channel 2

Offset Temperature Drift ..... 5 ppml oC, typical
10 ppml oC, maximum

Base + 166

Write

D/A Channel 3

Gain Temperature Drift ...... 15 ppml oC, typical
30 ppml oC, maximum

Base + 168

Write

D/A Channel 4

Base + 170

Write

D/A Channel 5

Settling Time ............. 6 IlSeconds, maximum

Base + 172

Write

D/A Channel 6

Output Current. ........... ±5 mA, typical

Base + 174

Write

D/A Channel 7

Output Impedance ......... 50 miliiohms, typical
CURRENT LOOP

Word Address: Base + 160, Base + 162, Base + 164, Base + 166,
Base + 168, Base + 170, Base + 172, and Base + 174

°

1

Current Loop .............. 4-to-20 mA, conforming to
ISA Standard 550.1, Type 4,
Class U
Accuracy ................. 0.1% of FSR, minimum
Excitation ................ +15V dc, minimum
(User-supplied) ........... +24V dc, typical
+36V dc, maximum
Load Resistance ........... 100 Ohms, minimum
1000 Ohms, maximum

Figure 2:

DVME-628 DAC Data Register Format

OUTPUT CONNECTIONS
The DVME·628 D/A boards use the J1 and J2 connectors for
analog output connections. Tables 2 and 3 list the output sig·
nals of the J1 and J2 connector respectillely.

POWER SUPPLY REQUIREMENTS
Table 2:
+5V dc ±O.5% at ............ 2.0 Amperes, typical
2.3 Amperes, maximum
PHYSICAL CHARACTERISTICS
Outline Dimensions ........ 9.19"W x 6.3"D x 0.6"H
(233.35 x 160x 15.24 mm)
Weight ................... 1 lb. (453.6 grams)
Operating Temperature ..... 0 to +60 °C
Range
Storage Temperature ....... -20 to +80 °C
Range
Humidity ................. 0 to 90%, non-condensing
DVME-628 PROGRAMMING INFORMATION
The DVME-628 contains eight programmable registers that store
digital data for the D/A converters. The board responds only to word
datatransfers on write operations. Since the DVM E·628 uses 12·bit
D/A converters, the 12 most significant bits of the DAC data
registers are used for conversion. Table 1 shows the addresses
of the identification code and the registers. Figure 2 shows the for·
mat of the DAC data register.

PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DVME-628 Analog Output Pinout Details (Jl)
DESCRIPTION
DACOVOUT
DACO I LOOP
DACOVLOOP
DAC 1 VOUT
DAC 11 LOOP
DAC 1 V LOOP
DAC 2VOUT
DAC21 LOOP
DAC 2V LOOP
DAC3VOUT
DAC31 LOOP
DAC3V LOOP
NO CONNECTION
DAC 0 ANALOG RETURN
DAC 0 ANALOG RETURN
NO CONNECTION
DAC 1 ANALOG RETURN
DAC 1 ANALOG RETURN
NO CONNECTION
DAC 2 ANALOG RETURN
DAC 2 ANALOG RETURN
NO CONNECTION
DAC 3 ANALOG RETURN
DAC 3 ANALOG RETURN
NO CONNECTION

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

•
11·41

DVME·628
Table 3:

DVME-628 Analog OutputPinout,Detaiis (J2)
DESCRIPTION
DAC4VOUT
DAC41 LOOP
DAC4VLOOP
DAC5VOUT
DAC51LOOP
DAC5VLOOP
DAC6VOUT
DAC61 LOOP
DAC6VLOOP
DAC7VOUT
DAC71 LOOP
DAC7VLOOP
NO CONNECTION
DAC 4 ANALOG RETURN
DAC 4 ANALOG RETURN
NO CONNECTION
DAC 5 ANALOG RETURN
DAC 5 ANALOG RETURN
NO CONNECTION
DAC 6 ANALOG RETURN
DAC 6 ANALOG RETURN
NO CONNECTION
DAC 7 ANALOG RETURN
DAC 7 ANALOG RETURN
NO CONNECTION

PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

Base
Address

Base + 1
+3
+5
+7
+9

Function

Manufacturer 10

+ 00

A

OAT is the 10 for DATEL

+ OF

T

+ 11

d
V
M

+ 17

E

+ 19

-

+ 1B

6

+10

2

+ 1F

8

Base + 64
tttrough
Base + 77

DVME-660

48 line digital 110 board

.--------.-------.-----

Not Used -----------------------

DVME-611
DVME-612

DVME-611: 32 single-endedl
16 differential channel AID
board

Base + 144
through
Base + 151

0

+ 15

Manufacturer's and Board's
identification code

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 D/A channels

Identifier
This ASCII code is present
for all DATEL VMEbus boards

+ 13

Function

All DATEL
VMEbus
boards

Base + 128
through
Base + 143

V
M
E
I
0

+ OB

11-42

ASCII
Code

Board
Model Number

Base + 0
through
Base + 63

Base + 78
through
Base + 127

DVME-628 BOARD IDENTIFICATION CODE
Byte
Address

DATEL VMEbus Short I/O Memory Organization

Board model number

DVME.602

DVME-602: 4-channel isolated board for measuring
thermocouples RTD's, strain
gage, high-level, low-level,
and 4-to-20 rnA current loop
inputs

Base + 152
through
Base + 159

-----------------------

Not Used -----------------------

Base + 160
through
Base + 175

DVME-612
DVME-624
DVME-628

DVME-612: 32 single-endedl
16 differential channel AID
board with 2 D/A channels
DVME-624: 4-channel isolated D/A board
DVME-628: 8-channel D/A
board

Base + 176
through
Base + 191

-----------------------

Base + 192
through
Base + 255

-----------------------

Not Used -----------------------

I
I
Not Used -----------------------

I

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DVME-641
32-CHANNEL HIGH-LEVEL,
VMEbus EXPANSION BOARD
FEATURES

• Accepts 32 single-ended/16 differential expansion
channels
• Directly accepts high-level inputs
• Hardware compatible with VMEbus specifications
• Interfaces to DATEL's DVME-601/6111612 AID boards
• 6 Microseconds settling time
• 0.01% Full-scale range accuracy
• Low-cost
• Cascadable to up to 256 channels
• Includes a board selection LED

THE DVME-641 OFFERS CHANNEL EXPANSION TO DATEL:s DVME-601/611/612 SERIES OF AID BOARDS. THE CHANNEL
EXPANSION BOARD IS DESIGNED TO ACCEPT HIGH-LEVEL INPUTS FROM UP TO 32 SINGLE-ENDED OR 16 DIFFERENTIAL
INPUT CHANNELS. THE DVME-641 DRAWS POWER FROM THE VMEbus P1 CONNECTOR AND FITS INTO VMEbus CARD
CAGES.

GENERAL DESCRIPTION

The DVME-641 is a low-cost channel expansion board that
interfaces directly to DATEL's DVME-601/611/612 high-performance AID boards. The board externally multiplexes up
to 32 single-ended or 16 differential high-level input channels.
The channel expansion board fits into a typical VMEbus host
system. The DVME-641 is specifically useful for applications
involving multiple-channel data acquisition or controlling
numerous discrete process control loops. The low cost per
channel makes the board ideal for most applications.

Figure 1 shows a typical multi-channel application for data
acquisition from different types of inputs. In this application
the host system selects the expansion channel on the
DVME-641, DVME-643 or DVME-645 through the DVME601/611/612A1D board. The DVME-601/611/612 digital data
is available on the VMEbus data lines for host system access.
ORDERING INFORMATION

DVME-641
ACCESSORIES
Part Number
DVME-C-01
DVME-C-02
HOST
SYSTEM

OVME-641
32S/160-CHANNEL
HIGH-LEVEL INPUTS

DVME-611/612
OR
DVME-601

DVME-643
8-CHANNEL
THERMOCOUPLE,

lOW-LEVEL,

328/16D MUX board

Description
Two-connector expansion cable (for
use with one multiplexer board).
Three-connector expansion cable (for
use with two multiplexer boards).

DVME-645

l6S/S0-CHANNEl
SIMULTANEOUS
SAMPLE/HOLD INPUTS

HIGH-LEVEL INPUTS

•

Figure 1: DVME-641 Application Configuration

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-43

DVME·641
CONNECTOR SPECIFICATIONS

FUNCTIONAL SPECIFICATIONS
(Typical at 25°C unless otherwise noted)

VMEbus Pl Connector ... . 96-pin male DIN connector

ANALOG INPUT

Analog Input - Jl,J2 ..... . Two 25-pin D-type DB-25S
Connectors
female connectors
External Trigger - J3 ..... . 9-pin D-type DB-98
Connector
female connector

Number of Channels
Channel Expansion
Input Configuration

32SI16D
256S/256D*

Off-Channel ........... .
Leakage current

0.03 nanoamperes, typical
60 nanoamperes, maximum

On-Channel ........... .
Leakage Current

0.1 nanoamperes,typical
300 nanoamperes, maximum

Analog Expansion - J4 .... 25-pin D-type DB-258
Single-ended
Connector
female connector
or Differential
Input Range . . . . . . . . . . .. ± 10V dc
POWER SUPPLY REQUIRMENTS
Analog Output . . . . . . . . .. Differential
+ 5V dc ± 0.5% at OAA typical, 0.6A maximum from
Interface. . . . . . . . . . . . . .. Analog Expansion Bus
P1 VMEbus connector
for DVME-601l611/612 boards
Common Mode Voltage ... ±10V dc, maximum
PHYSICAL CHARACTERISTICS
(Specified for differential
non-isolated
configuration only)
Outline Dimensions ...... 9.19"W x 6.3"D x 0.6"H
(233.35 x 160 x 15.24 mm)
Overvoltage Protection .. . ± 35V dc, maximum

Output Settling ........ . 6/lseconds, maximum
Time (0 to 10V step input,
to rated accuracy
channel-to-channel settling)

The DVME-641 uses J1, J2, J3, and J4 for analog input, external trigger, and channels expansion connections. Tables 1,2,
3, and 4 list these signals. VMEbus lACK and bus grant
signals are daisy-chained.

*Up to 10 slave MUX boards may be driven from one AID
master board at derated setting.

DVME~641

Storage Temperature. . . .. -20 to +80 DC
Range

1/0 CONNECTIONS

Output Impedance ...... . 2.5 Kohms, maximum

Table 2:

11 oz. (311.85 grams)

Operating Temperature... 0 to +60 0C
Range

Relative Humidity. . . . . . .. 0 to 90%
non-condensing

Full-scale Range ....... . 0.01%, maximum
Accuracy

Table 1: DVME-641 Analog Input Connector (Jl)

Weight. . . . . . . . . . . . . . ..

Analog Input Connector (J2)

Table 3: DVME-641 External Trigger Input Connections (J3)

PIN #

Single-ended

PIN#

Single~ended

Differential

SIGNAL

24
12
25

Channel 0 IN
Channel 16 IN
Analog Return

Channel 0 High IN
Channel 0 Low IN
Analog Return

24
12
25

ChannelS IN
Channel 24 IN
Analog Return

Channel 8 High IN
Channel 8 Low IN
Analog Return

External Trigger IN·
Digital Ground

10

Channel 1 IN
Channel 17 IN
Analog Return

Channel 1 High IN

23
11

Channell Low IN
Analog Return

10
23
11

Channel91N
Channel 25 IN
Analog Return

Channel 9 High IN
Channel 9 Low IN
Analog Return

21
9
22

Channel 2 IN
Channel 18 IN
Analog Return

Channel 2 High IN
Channel 2 low IN
Analog Return

21
9
22

Channel 10 IN
Channel 26 IN
Analog Return

Channel 10 High IN
Channel 10 Low IN
Analog Return

7
20
8

Channel 11 IN
Channel 27 IN
Analog Return

Channel 11 High IN
Channel 11 Low IN
Analog Return

18
6
19

Channel 12 IN
Channel 28 IN
Analog Return

Channel 12 High IN
Channel 12 Low IN
Analog Return

4
17
5

Channel 13 IN
Channel 29 IN
Analog Return

Channel 13 High IN
Channel 13 Low IN
Analog Return

15
16

Channel 14 IN
Channel 30 IN
Analog Return

Channel 14 High IN
Channel 14 Low IN
Analog Return

1
14
2

Channel 15 IN
Channel 31 IN
Analog Return

Channel 15 High IN
Channel 15 Low IN
Analog Return

Differential

7
20
8

Channel31N
Channel 19 IN
Analog Return

Channel 3 High IN
Channel 3 Low IN
Analog Return

18
6
19

Channel 4 IN
Channel 20 IN
Analog Return

Channel 4 High IN
Channel 4 Low IN
Analog Return

4
17
5

Channel 5 IN
Channel 21 IN
Analog Return

Channel 5 High IN
ChannelS Low IN
Analog Return

15
3
16

Channel 6 IN
Channel 22 IN
Analog Return

Channel 6 High IN
Channel 6 Low IN
Analog Returr.

1
14
2

Channel 7 IN
Channel 23 IN
Analog Return

Channel 7 High IN
Channel 7 Low IN
Analog Return

11-44

3

Table 4: DVME-641 Expansion Channel
Expansion Connections (J4)

PIN #

SIGNAL

13
25
12
24
11
23
10
22
4,16

Expansion Channel
Expansion Channel
Expansion Channel
Expansion Channel
Expansion Channel
Expansion Channel
Expansion Channel
Expansion Channel
Digital Ground

9
20
17

Expansion Channel Address Valid IN
Setling Delay OUT"
External Trigger Our

21
5

Not Used
Not Used

1
14
2,15

Analog Low OUT
Analog High OUT
Analog Common

Address
Address
Address
Address
Address
Address
Address
Address

Line a IN
Line 1 IN
Line 2 IN
Line 3 IN
Line 4 IN
Line 5 IN
Line 6 IN
Line 7 IN

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

DVME-643
8-CHANNEL
ISOLATED ANALOG
VMEbus EXPANSION BOARD
FEATURES
• Offers channel expansion to DATEL's DVME-601l611/612
AID boards
• Two models of channel expansion boards
DVME-643T: Thermocouple and low-level inputs
DVME-643H: High-level inputs
• On-board cold junction compensation sensor
• Offers 1000V peak isolation
• On-board signal conditioning
• 120 dB minimum CMRR
• 55 dB minimum NMR
• 2.5 millisecond settling time
• On-board dc-to-dc power converter
• Cascadable to up to 10 MUX boards
• Includes a board selection LED

THE DVME-643 BOARDS OFFER CHANNEL EXPANSION TO DATEL's DVME-601/611/612 A/D BOARDS. THESE
MULTIPLEXER BOARDS PROVIDE 1000V ISOLATION AND SIGNAL CONDITIONING FOR EIGHT THERMOCOUPLE,
LOW-LEVEL, OR HIGH-LEVEL INPUTS. THE DVME-643T BOARD INCORPORATES A COLD JUNCTION COMPENSA TlON OUTPUT FOR THERMOCOUPLE INPUTS TO CORRECT AGAINST REFERENCE JUNCTION TEMPERA TURE
VARIATIONS.
GENERAL DESCRIPTION
Designed specifically for applications requiring multiple channel data acquisition, the DVME-643 boards expand the analog
input capability of DATEL's DVME-601/611/612 AID boards.
The DVME-643 boards are offered in two versions. The
DVME-643T provides isolation and signal conditioning for
thermocouple and low-level inputs. The DVME-643H accepts
for high-level voltage and 4-to-20 mA current loop inputs.

The DVME-643T allows mixing thermocouple and low-level signals on the same board. The DVME-601/611/612 boards offer
channel expansion for up to 256 channels. In addition to the
DVME-643 boards, DATEL's channel expansion boards for
high-level and simultaneous sample and hold inputs may also
be used with a DVME-601/611/612 board. Figure 1 shows typical multi-channel application configuration.
ORDERING INFORMATION
DVME-643'l
r-T _ Thermocouple and low-level isolated inputs
input ranges: ±25.6, 51.2, and 102.4mV

HOST
SYSTEM

H - High-level voltage and current loop isolated
inputs
High-level voltage ranges: ±5V de
Current loop inputs: 4-to-20 mA

DVME-6111612

I-

OR
DVME-601

I-R _ RTD inputs'
~S

- Strain gage inputs'

'(Consult factory for availability)

DVME-S41
32SI160-CHANNEL
HIGH-LEVEL INPUTS

DVME·643
a·CHANNEL
THERMOCOUPLE
LOW-LI::VEL.

DVME-645
l6S/SD-CHANNEL
SIMULTANEOUS
SAMPLE/HOLD INPUTS

HIGH-LEVEL INPUTS

ACCESSORIES
Part Number
DVME-C-Ol
DVME-C-02

Figure 1: DVME-643 Application Configuration

Description
Two-connector expansion cable (for
use with one multiplexer board).
Three-connector expansion cable (for
use with two multiplexer boards).

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-45

III

DVME·643
FUNCTIONAL SPECIFICATIONS

CONNECTOR SPECIFICATIONS

(Typical at 25°C, unless otherwise noted)

VMEbus·P1 Connector ........ 96·pin male DIN
connector

ANALOG INPUT

Analog Input J1 and J2 ........ 12·pin male connector
Connectors

Number of Channels .......... 8 Differential and CJC
channels
Channel Expansion .......... Up to 256S/2560'
Isolation . . . . . . . . . . . . . . . . . .. 750V RMS
(ch-ch. & ch.·bus)
1000V Peak
Input Range DVME·643T ...... ± 25.6 mV dc
±51.2 mV dc
±102.4 mV dc
DVME·643H. . . . .. ±5V dc

Analog Expansion J4. . . . . . . . . 25·pin O·type female
Connector
connector, OB·25S

PHYSICAL-ENVIRONMENTAL
Outline Dimensions .......... 9.19"W x 6.3"0 x
0.6"H (233.35 x 160 x
15.24 mm)

Common Mode Voltage ....... 750V RMS
AC, 50 or 60Hz
1000V Peak

Weight ..................... 1 Ib (453.59 grams)

Input Bias Current ........... 8 nano amperes,
maximum
Overvoltage Protection ....... 130V RMS, maximum

Storage Temperature ......... ·20 to +80 oC
Range

Input Impedance, ............ 100 megohms
differential input to ground
Common Mode Rejection
.01 to 100Hz
Ratio, f
DVME·643T . . . . . . . . . . . . . .. 120 dB, minimum
DVME·643H ............... 110 dB, minimum

=

Operating Temperature Range .. 0 to +60°C

Relative Humidity ............ 0 to 90%, non·
condensing
• Up to 10 slave MUX boards may be driven
from one NO master board.

Table 1: Analog Input Connections (J1 and J2)
Normal Mode Rejection ....... 55 dB, minimum
50 or 60 Hz
Settling Time ............... 2.5 milliseconds,
maximum
dc Gain Accuracy
DVME·643T ............... 0.03% FSR, minimum
DVME·643H ............... 0.05% FSR, minimum
Gain Drift ................... 35 ppm/oC, maximum
Offset Drift
DVME·643T ............... 3 ,"V/oC, maximum
DVME·643H . . . . . . . . . . . . . .. 60,"VloC, maximum
CJC Error
At Room Temperature ...... 0.5°C, maximum
At Full Temperature Range ... 1.5°C, maximum
Output Impedance ........... 0.5 K ohms, maximum
POWER SUPPLY REQUIREMENTS
+ 5V dc ± 0.5% at 1A typical, 1.5A maximum from P1
VMEbus connector.

PIN #

SIGNAL(J1)

PIN #

SIGNAL (J2)

12
11
10

Channel 0 High IN
Channel 0 Low IN
Analog Return

12
11
10

Channel 4 High IN
Channel 4 Low IN
Analog Return

9
B
7

Channel 1 High IN
Channel 1 Low IN
Analog Return

9
B
7

Channel 5 High IN
Channel 5 Low IN
Analog Return

6
5
4

Channel 2 High IN
Channel 2 Low IN
Analog Return

6
5
4

Channel 6 High IN
Channel 6 Low IN
Analog Return

3
2
1

Channel 3 High IN
Channel 3 Low IN
Analog Return

3
2
1

Channel 7 High IN
Channel 7 Low IN
Analog Return

Table 2: Channel Expansion Connections (J4)
PIN#
13
25
12
24
11
23
10
22
4,16

SIGNAL
Expansion Channel Address
Expansion Channel Address
Expansion Channel Address
Expansion Channel Address
Expansion Channel Address
Expansion Channel Address
Expansion Channel Address
Expansion Channel Address
Digital Ground
Settling Delay
External Trigger OUT

0
1
2
3
4
5
6
7

our

I/O CONNECTIONS

20

The OVME-643 uses J1 and J2 for analog input connec·
tions and J4 for channel expansion connections. Tables 1
and 2 list these signals. VMEbus lACK and bus grant
signals are daisy-chained.

9

Expansion Channel Address Valid IN

14
1
2.15

Analog High OUT
Analog Low OUT
Analog Common

11·46

17

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048· 1194rrEL (508) 339·3000rrLX 174388/FAX (508) 339·6356

DVME·645
16-CHANNEL SIMULTANEOUS
SAMPLE-AND-HOLD
VMEbus EXPANSION BOARD
FEATURES
• Offers channel expansion to OVME-601/611/612 AID
boards
.
• Offers simultaneous sample-and-hold capability to up
to 16S/80 channels
• 1.2 p.VIp.S sample-and-hold droop rate
• 6 Microsecond settling time
• Complete compatibility to VMEbus hardware
specifications
• Cascadable to up to 256 channels
• 0.05% Full-scale range accuracy
• On-board dc-to-dc converter

THE DVME-645 IS DESIGNED TO PROVIDE CHANNEL EXPANSION TO DATEL 'S DVME-601/611/612 BOARDS FOR
APPLICATIONS REQUIRING SAMPLE AND HOLD CAPABILITY THE BOARD IS EQUIPPED WITH 16 SAMPLE-ANDHOLD AMPLIFIERS, ACQUIRING DATA SIMULTANEOUSLY FROM 16 CHANNELS. THE BOARD IS IDEALLY SUITED
FOR TRANSIENT ANALYSIS, SIGNAL RECONSTRUCTION AND RELATED APPLICATIONS.
GENERAL DESCRIPTION
The DVME-645 offers simultaneous sample-and-hold capability to DATEL's family of multiplexer boards. The board expands
the analog input channels of the DVME-601/611/612 AID
boards. In a typical application, the DVME-645 is usable with
other multiplexer boards using thermocouple, isolated and nonisolated voltage inputs. Figure 1 shows the channel expansion to the DVME-601/611/612 AID boards.
Simultaneous Sample-and-Hold
A sample-and-hold circuit holds or freezes a changing analog
input signal for up to a few milliseconds. With 16 on-board
amplifiers, the DVME-645 simultaneously holds analog signals from 16 individual channels. An AID subsystem (DVME6011611/612 may scan and convert the samples stored. The

digital data now represents the analog signal values at an
instant of time from all the 16 channels.
The DVME-645 also allows measuring high-speed transients
and spikes during a specified window of time. For applications
requiring sampling at rates up to 8 MHz all 16 channels may
be connected to a single measuring pOint. The sample-andhold circuits may then sequentially acquire the analog input
Signal. In this application, the DVME-645 functions as a very
low-cost 8 MHz storage device. Typical applications of the
OVME-645 with the DVME-601/611/612 include pulse analysis and reconstruction and data skew elimination for seismic
measurements.
ORDERING INFORMATION
DVME-645
ACCESSORIES
Part Number
OVME-C-01

HOST
SYSTEM

DVME.fl111612

0"

OVME-C-02

DVM€:'S43
a-CHANNEL
THERMOCOUPLE
LOW-LEVEL
HIGH·LEVEL INPUTS

16S/80 SSH MUX board

Description
Two-connector expansion cable (for
use with one multiplexer board).
Three-connector expansion cable (for
use with two multiplexer boards).

HlSIBD·CHANNEL
SIMULTANEOUS
SAMPLEI .... OLD INPUTS

III

Figure 1: DVME-645 Application Configuration

DATEL,lnc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-47

DVME·645
FUNCTIONAL SPECIFICATIONS

ANALOG SPECIFICATIONS

(Typical at 250 C, unless otherwise noted)

Common Mode Voltage .... ±10V dc, maximum
Over Voltage Protection. .. ±35V dc, maximum

Number of Channels ...... 16S/8D non-isolated

Input Bias Current ........ 300 nanoamperes, maximum

Channel Expansion ....... Up to 256S/256D'

Input Impedance ......... 1 Megohm, minimum

Input Range ............. ±10V dc
Analog Output. . . . . . . . . . . Differential
Interface . . . . . . . . . . . . . .. Analog expansion bus for
DVME·611/612 boards

Output Settling Time ..... 6 ",seconds, maximum
to rated accuracy
(For 0 to -10V step
input, channel-tochannel settling)
dc Gain Accuracy ........ 0.05%, minimum

CONNECTOR SPECIFICATIONS

Output Impedance ....... 0.5 Kohms, maximum
VMEbus P1 Connector .... 96·pin male DIN connector

Input Offset Voltage ...... 1.0 mV, maximum

Analog Input J1 Connector 25-pin D-type female
connector

Input Offset Voltage ...... 20 ",VloC, maximum
Drift

External Trigger and ...... 9-pin D-type female
Sample-and-hold Control
connector
J3 Connector

Aperture Delay .......... 50 nS

Analog Expansion J4 ..... 25-pin D-type female
connector
Connector

Sample-and-Hold Droop ... 1.2 ",VI",S, typical
2.0 ",VI",S, maximum
Rate

Aperture Time ........... 100 nS

Sample-and-Hold Pedestal. 1.0 mV, typical
2.5 mV, maximum

POWER SUPPLY REQUIREMENTS
+ 5V dc ± 0.5% at 2.0A typical, 3.0A maximum from
P1 VMEbus connector.

PHYSICAL-ENVIRONMEN-----------1482.61----------------l·1
SIGNAL SCREW
TERMINALS

...----~~~-----,/

~~

FLAT CABLE HEADER
CONNECTORS

SIDE ACCESS
WIRING CUTOUTS
(AT BOTH ENDS)

Figure 1. Connector Locations/Dimensions

DC Power Rails
Adjacent to each channel are bipolar dc power supply rails.
These may be used for clamp circuits, for sensor excitation, or
open-circuit detection. The dc rails are brought out to screw ter·
minals suitable for connection to an adjacent dc power supply.
There is ample room to mount a supply on standoffs on the rear
of the DVME-691. Voltages up to ± 15V dc may be distributed
to each chan nel.
For D/A outputs, the signal conditioning pads could be used for
excitation of 4-to-20 mA current loops. Such excitation circuits
would use the dc power supply, the distributed dc rails, and
current-excitation resistors on a per-channel basis.
Signal Conditioning Circuitry
Signal-conditioning circuitry can be of the user's design or
DATEL can provide the design, testing, and installation of such
circuitry under special quantity order.

Sensor Families

As configured, the DVME-691A is ideal for voltage and millivolt·
input sources. These include bridges, strain gages, load cells,

and RTD's. The DVME·691 adapts to 4-to-20 mA loop inputs by
adding current loop shunts. The DVME-691A accepts thermocouple inputs if the user supplies external cold junction compensation (CJC).
Alternatively, electronic CJC may be provided on the A/D board
by using DATEt:s Model DVME-602T or DVME·643T slave thermocouple channel expander boards. These two products include their own front panel screw terminals. For a stand-alone
4-channel RTD AID board with screw terminals, refer to DATEt:s
DVME-602R.
OTHER FEATURES
The DVME-691 is intended for factory-floor, industrial, and
laboratory applications. As shown in Figure 1, the screw terminals accept field signal wiring either as bare wire or terminated
with strain-relieved lugs. Access holes in the sides of the
DVME·196 permit routing the wiring through the rear of the
DVME·691. Because of this access, several DVME-691's can
mount above each other in the same rack or directly adjacent
to the host A/D-D/A computer.
The DVME-691 also includes a transparent safety shield which
prevents accidental contacts while providing a means of labelling each connection. The DVME-691 does not protrude from
the rack.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

11-55

DVME·691A and ·691D
TYPICAL RACK-MOUNT
APPLICATION

DVME·691A
SCREW
TERMINATOR ---<~"
PANEL
SIGNAL WIRING BUNDLE
TO/FROM SENSORS AND
ACTUATORS
SAFETY
SHIELD

FLAT SIGNAL CABLES
HOST VME
COMPUTER

19" RACK (NOT SHOWN)

-----I

Figure 2. Typical Rack-Mount Configuration

~plcal

Rack Mount Application

(Figure 2)
This diagram shows the DVME-691 mounted in a 19" rack adjacent to its host computer. Three supplied flat cables connect
the DVME-691 to a Model DVME-612 combination AlD-D/A
board. The DVME-691 may be positioned either above or below
the computer. The cables are each one meter long so that, if
required, the 691 may be located in an adjacent rack.
Before connecting the field wiring, the 691's PC board is removed for optional signal conditioning component installation
by the user. Signal wiring for input sensors and transducers or
output devices connects to the screw terminals along the top
ofthe DVME-691. This wiring may be collected in bundles and
routed either through the slots at the ends of the DVME-691 or
over the top edge. Wire bundl.e routing through the slots allows
adjacent equipment to be rack-mounted immediately above the
DVME-691.

11-56

This application uses three flat cables - two for AID signals
and the third for the two DVME-612 D/A channels. Usersupplied dc power, if required for sensor excitation or protective clamps, would connect to the screw terminals at the lower
left corner olthe DVME-691. Ample room is available on the rear
mounting bracket to atiach a small dc power supply.

Signal Conditioning Pads per Channel
(Figure 3)
This drawing shows the arrangement of PC board circuit pads
for each analog channel. The user selects and installs suggested components shown in the illustration. (DATELwili review
custom applications under special order). The pad area is intended for a wide range of applications and the user does not
have to use the components indicated. As supplied, connections are made straight-through from the screw terminals.
DC power rails are bussed to each channel and are brought out
to screw terminals.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DVME·691 A and ·691 D

TO OR
FROM
AID OR D/A
BOARDS
VIA FLAT
RIBBON CABLE
CONNECTORS

TO OR
FROM

f-IELD
DEVICES

+VS}

NOTE: COMPONENTS SHOWN ARE USER-SELECTED.
ALL ETCH FOR CIRCUITS SHOWN IS PROVIDED
ON THE DVME-691A AND OVME-691D.

l~~::

OPTIONAL
DC POWER

TO OTHER
CHANNELS

Figure 3. Typical Input Circuitry Layout
Filters and Attenuators
When measuring some signals, it may become necessary to
filter out unwanted noise or to attenuate the signals prior to
passing them to the analog·to·digital converter board. The
DVME·691A provides the user with a convenient area for user·
configured passive signal conditioning.

RS,

~----

I

Figures 4,5, and 6 show typical configurations of simple high·
pass, low·pass, and attenuator circuits.

CP2 _TO OUTPUT
CONNECTOR

(/)~------+
1\'plcal values for a high·pass filter

Figure 5. Typical Low·Pass Filter

If the desired cutoff frequency (Fc) is 60 Hz and if Rp is chosen
as 10K ohms for differential inputs into the DVME·691,
then, Cs -

= 0.265 p.F

1

1

2n (Rp) (Fc)

2n (10K) (60)

Refer to Figure 4, installing a '0.265 p.F capacitor in the place
of RS1 and a 10K ohm resistor in place of RP3.

(lJ~---I t------<~- - - - -RP 3

_TO OUTPUT
CONNECTOR

Typical Attenuator Circuit
If the input signal is 50V dc and the input circuit device can only
handle +10V dc maximum, an attenuation circuit can be made
up as follows:
If choosing a 100K ohm resistor for Rs,
Rp

=

Vp Rs
Vin - Vp

=

10(100K)
50 - 10

=

1 megohm
40

= 25K ohms

Refer to Figure 6, installing a 25K ohm resistor in the place of
RS3 and a 100K ohm resistor in place of RS1.

n--------...... ---- Figure 4. Typical High·Pass Filter
RP 3

1\'pical Values For a Low·pass Filter
If the desired cutoff frequency (fc) is 40 Hz, and if Rs is chosen
as 20K ohms for single·ended inputs into the DVME·691,
then, Cp =

1

1

2n (Rs) (fc)

2n (20K) (40)

= 0.2p.F

TO OUTPUT
-CONNECTOR

V } - - - - - - - -.. -- - --Figure 6. Typical Attenuation Circuitry

III,'

Refer to Figure 5, installing a 0.2p.F capacitor in the place of CP2
and a 20K ohm resistor in place of RS1.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

11·57

OVME·691A and ·6910

ORDERING GUIDE
Model Number
Description
DVME-691A
Screw terminator panel for 32 single-ended or 16 differential
(for VME)
analog input and 2 analog output channels (includes 3 cables
for DVME-6111612 boards).
DVME-691D
(for VME)

Screw terminator panel for 8 analog output channels (includes 2
cables for DVME-62X series boards).

Contact DATEL for custom component configurations.

11-58

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

DVME·UTIL

VMEbus SOFTWARE UTILITIES
for VERSAdos or PDOS
DATA ACQUISITION SOFTWARE UTILITIES SUPPORTING ALL DATEL VMEbus BOARDS
(Except DVME·601. Contact DATEL for DVME·601 software.)
FEATURES
• Three main program modules
1. UTiL module data acquisition functions
a) Physical-to-Iogical channel mapping
b) Typical data acquisition routines
2. 10SUBR module I/O console tasks
a) Input/output console routines
b) ASCII conversion routines
3. MATCH high-level language module and interface for
passing paramaters.

• Easy integration to user application software
• Includes a demonstration program written in "C" to exercise
all utilities
• All modules written in linkable 68000 assembly language
code
• All routines callable using assembly language and "C" language main programs
• Includes fully commented source code and user's manual
• VERSAdos-compatible and PDOS-compatible versions currently available

The o VME-U TIL software package offers complete data acqUisition software support for all OATEL VMEBUS liD boards.
Source code for all of the routines is provided for easy integration into users' application programs. The software modules
offer physical-to-Iogical channel mapping, analog and digital 110 functions, console liD utilities, high-level language compatibility, and even an example demonstration program written in "e"
GENERAL DESCRIPTION
The DVME-UTIL integrates DATEL:s DVME family of VMEbus
analog I/O boards to the user's application program. DVMEUTIL relieves the system programmer's burden of writing application software to drive and manage multiple analog and digital I/O boards. The full set of data acquisition utilities are callable
from either 68000 assembly language or "C" language main
programs. Other high-level languages can be easily supported
by modifying the parameter passing module.
The main feature of the DVME-UTIL is that all of DATEL:s VMEbus boards are directly usable without the user's concern for
the physical location ofthe on-board registers. At initialization
time a physical-to-Iogical channel map is generated. Once
initialized, all data acquisition functions are accomplished
through logical symbol specifiers.
The DVME-UTIL software comes complete with a detailed software manual and two 5% "diskettes formatted for either the
VERSAdos or PDOS operating systems. The diskettes contain
68000 assembly source codes and object codes for all the routines. The diskettes also contain an example demonstration
program, SHOUTIL written in "C." The list file, link list, and
executable code of the SHOUTIL is also included. A chain, or
procedure, file is also included to serve as an example of how
the DVME-UTIL modules can be assembled and linked to a
main program. The manual describes each subroutine in
explicit detail and provides syntax for using with assembly and
"C" language programs. The user's manual also provides
examples for each routine.

FUNCTIONAL DESCRIPTION
The DVME-UTIL essentially consists of three functional modules. The modules are UTIL, 10SUBR, and a high-level language MATCH module.
The UTIL module contains routines categorized into six
classes. The six classes of the routines perform functions relating to initialization, analog input, analog output, thermocouple/RTD input, expansion connector, and digital I/O. Refer to
Table 1 for a description ofthe routines in this module. The UTIL
module implements a logical channel concept which maps
physical board addresses and channel numbers to logical
channel references. When running the VERSAdos version, and

depending on the total number of channels being mapped, one
or more pages of system RAM are attached to the running task.
When running the PDOS version, the user must allocate sufficient free RAM space. This RAM area is used to hold the channel control tables which provide the physical-to-Iogical channel
mapping. Simple subroutine calls to the UTIL module replace
many lines of code that would be required by the user's main
program software. In addition to inter-board physical-to-Iogical
channel mapping, there are subroutines which perform many
of the typical data acquisition functions. Any required operating system interaction is taken care of by the UTIL module.
The IOSUBR module contains 15 console input/output and
ASCII conversion routines. Although the UTIL module only calls
a few of these routines, the entire IOSUBR module is available for the user's application program. Refer to Table 2 for a
description of the routines in this module.
The MATCH module allows calling the routines in UTIL and
IOSUBR modules using "C" language programs compatible
with Whitesmith's parameter passing convention. The MATCH
module copies the arguments of "c" language programs into
the appropriate registers in the UTIL and IOSUBR routines.
Data passed back to the calling program is also taken care of
by the MATCH module. Matching modules for other compiler
types can easily be written to meet different parameter passing requirements.
There are two possible ways to interface to UTIL and IOSUBR
module subroutines. Most high-speed and memory critical
applications will require that the main applications program be
written entirely in assembly language. In order to meet the highspeed requirements, DVME-UTIL subroutines use 68000
internal registers where ever possible. Other less time critical
applications could have their main program written in a high
level language such as "C." In these applications use the
MATCH module. Figures 1 and 2 show the data flow to the
DVME-UTIL from main programs written in assembly language
and Whitesmith's "C" respectively.

ORDERING INFORMATION
DVME-UTILIV
VERSAdos version
DVME-UTILIP
PDOS version
IBM-PC/XT/AT 5%" disk format is also available.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·1194ITEL (508) 339·3000ITLX 174388/FAX (508) 339·6356

11-59

DVME-UTIL
ANALOG/DIGITAL \/0 ....

ANALOG/DIGITAL 110. . .

ASSEMBLY
LANGUAGE
MAIN
PROGRAM
CONSOLE 110_

Figure 1.

Data Flow for Using DVME-UTIL With
Assembly Language
Table 1. List of Routines in the UTiL Module

SUBROUTINE
CLASS
Initialization

SUBROUTINE
INICCT
MAPAD
MAPDA
MAPTH
MAPDI
SHOMAP

Analog Input

ALADIN
ENADIN
ADTRC
ADGAI
ADSNG
NADSNG
ADSCN
NADSCN
ADRDM
NADROM
INFSNG
FSTSNG
FSNSNG
INFSCN
FSTSCN
FSNSCN

Analog Output

ALTHIN
ENTHIN
THSNG
NTHSNG
THSCN
NTHSCN
THRDM
NTHRDM

Expansion
Connector
Digital Output

11·60

ADGPO}
ADGP1
THGPO
THGP1

Initializes channel control tables.
Maps all AJD channels to logical reference.
Maps aU D/A channels to logical reference.
Maps all thermocouple/RTD input channels to
logical reference.
Maps all digital 1/0 channels to logical reference.
Displays physical-la-logical map.

I

Figure 2.

SUBROUTINE
CLASS
Digital 110

Controls allocation of interrupts for interrupt
driven thermocouple/RTD inputs.
Enables/disables thermocouple/RTD inputs in interrupt mode.
Performs a single scan on a thermocouplel
RTD input logical channel.
Performs "N" scans on a thermocouplel
RTD logical channel.
Performs a sequential scan on logical channels.
Performs "N" sequential scans on thermocouple/RTD logical channels
Performs a scan on thermocouple/RTD channels
from a random channel table.
Performs "N" scans on thermocoupJe/RTD channels from a random channel table.
Provide a single bit digital output
on two pins on a OVME-611/612 board.
Provide a single bit digital
output on two pins on a OVME-602 board.

Data Flow for USing DVME-U'TlL With
"c" Language

SUBROUTINE
ALTRIN

ALCMIN

ALTMIN

Controls interrupt allocation for interrupt driven
AiD conversion.
Enables/disables AlD input in the interrupt mode.
Enables/disables AiD conversion on an external
trigger.
Loads gain value.
Performs a single channel scan on a logical
channel.
Perforns "N" scans on a single logical channel.
Performs a s(ngle sequential chanel scan on logical channels specified.
Performs "N" scans on logical channels specified.
Performs single scan on channels from a table of
random logical channels.
Performs "N" scans on channels from a table of
random logical channels.
Initializes AID registers for fast AID operations on
a single logical channel.
Performs a fast scan on a channel.
Performs .oN" fast scans on a channel.
Initializes AID registers for fast AID operations on
a sequential channel scan.
Performs a fast scan on sequential channels.
Performs "N" fast scans on sequential channels.
Provides a single output to a logical channel.
Provides buffered output data to sequential logical channels.
Provides buffered output data to random logical
channels.

DASNG
DASCN
DARDM

Thermocouplel
RTD Input

DESCRIPTION

CONSOLE 1 1 0 _

ENDGIN
LODDIR
LODCMP
LED660
PRGTIM
INPBIT
INPBYT
INPWRD

OUTBYT

OUTWRD

DESCRIPTION
Controls allocation of external trigger generated interrupts from a
DVME·660 board.
Controls allocation of port 0
comparator register generated interrupts from a DVME-660 board.'
Controls allocation of timer generated interrupts from a DVME-660
board.
Enables/disables interrupts on a
DVME·660 board.
Loads port direction bits in a
DVME-660 register.
Loads port O/compare register on
a DVME-660.
Turns on or off an LED on a
selected DVME-660 board.
Loads the timer control register in
a DVME·660 board.
Accepts a data bit from a logically
mapped DVME·660 input port.
Accepts a data byte from a logically mapped DVME·660 input port.
Accepts a word from adjacent logically mapped DVME-660 input
ports.
Provides a byte output to a logically mapped DVME·660 output
port.
Provides a word output to logically
mapped DVME-660 oulput ports.

Table 2. List of Routines in the IOSUBR Module
SUBROUTINE
ASCHEX
HEX DEC
GETID
HEXASC
PRCR
PRNCR
OHXCR }
OHXNCR
PROMPT
CRLF
MAKECAP
PMTCHR
SHOCHR
INPCHR
SMPCON

DESCRIPTION
Converts "N" number hex ASCII characters to binary
format.
Converts a 16-bithexnumbertoa decimal ASCII string.
Builds a VMEbus ID output buffer from the 10 PROM
on a DVME board.
Converts a l6-bit hex number to a hex ASCII string.
Outputs '3.n ASCII message to the console followed by
a carriage return and line feed.
Outputs an ASCII message to the console without a
carriage return or line feed.
Gonvert a l6-bit number to hex ASCII and displays it
on the console with or without a carriage return.
Provides an ASCII message to the console and waits
for the console input.
Provides carriage return and line feed output.
Converts a string of ASCII characters into all capitals.
Provides an ASCII message output to the console
and waits for a single character input.
Provides a single character output to the console.
Accepts a single character input from the console.
Samples the console for any possible input. On
receiving any input halts 110 operation and sets "2"
condition flag.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

ST-519

MULTIBUS

72-Line Digital
I/O Board With Interrupt
FEATURES
• 72 Individually-programmable input/output
lines
• IEEE 796 MUL TIBUS Compatible
• Compatible with both 8- and 16-bit CPU's
(8- or 16-bit data transfer)
• Memory mapped, optional 1/0 map
• 20- or 16-bit user-selectable base address
(24-bit base address optional)
Eight maskable interrupt lines
• Interfaces to pluggable modules for 2.5KV
isolation

OATH expands its line of MUL TlBUS compatible system boards with the ST-519. The ST-519 provides 72 individually-programmable lines for input or output (liD). Also, an interrupt controller is provided to allow up to eight userprogrammable interrupt lines. Like other OATH MUL TlBUS products, the ST-519 is fully hardware- and softwarecompatible with all MUL TlBUS microcomputers. All necessary address decoders, logic controls, and data transceivers are incorporated on board.

DESCRIPTION
The DATEL ST-519 is a MUL TIBUS-compatible system
board providing 72 software programmable input/output (II
0) lines. These 110 lines are fully TTL compatible and each
line can be individually programmed as either an input or an
output.
The ST-519 may be used with both 8- and 16-bit microprocessors. The BHENlline on the MULTIBUS sets the ST519's address decoders and data latches for compatibility
with 8- or 16-bit computers. The ST -519 also supports 24bit MULTIBUS addressing capability, and is downward compatible with 16- or 20-bit address systems.
The ST-519 has an 8259A Programmable Interrupt Controller which provides vectoring information for eight userdefinable interrupt levels. In normal slave operation, the Interrupt Request (IR) lines of the 8259A are hard-wired to an
110 line. When the 110 event occurs the 8259A generates
an Interrupt (INT) which would go to one of the MULTIBUS
vector interrupt lines INT0 thru INT7.

In order to make the ST-519 compatible with different speed
CPU and memory systems, a transfer acknowledge delay
(XACK/DELAY) is provided. This permits 8 selectable delays from 100 to 800 nanoseconds.
The ST-519 is fully bus- and card-cage compatible with the
MULTIBUS and IEEE 796. The board is 12.0"W x 6.75"0 x
O.47"H (305 x 172 x 12 mm). When used with the standard
MULTIBUS card cage, the ST-519 board may be installed
adjacent to other boards.
The ST-519 draws all power from the MULTIBUS +5V de
power line. The ST -519 weighs approximately 12 ounces
(0,341 kg). It can operate over a temperature range of 0 to
+55 degrees Celcius with relative humidity from 10 to 90%
(noncondensing), and from 0 to 15,000 feet (0 to 4,600 m) in
altitude.

The 72 110 lines are brought out on three 50-pin edge-card
connectors: J1, J2, and J3. These edge-card connectors
are fully compatible to the Gordos and OPT022 type pluggable modules systems that offer an input to output isolation of 2.5K VAC. A flat ribbon cable interconnects the DATEL ST-519 to other electronic module systems.
The ST-519 is a memory-mapped peripheral occupying 16
consecutive locations in the computer's address space.
The board's base address is preset at 00FFA0 hex. However, a user may relocate the board address anywhere up to
FFFFF0 on 16-byte boundaries using DIP switches on the
board.

ORDERING GUIDE
MODEL

DESCRIPTION

ST-519

72 line digital 110 board with interrupt

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-61

ST-519
FUNCTIONAL

SPECIFICATIONS

CHANNELS
I/O number of
channels .................... 72110 Channels
Channel expansion .... Indefinite channel expansion
using separate ST-S19
boards at different base addresses; limited by available
card slots and supply current
OUTPUT DRIVER
Output current sink
(Vout = O.6V) ................. 24 mA (max.)
Output current source
(Open collector
4.7KQ from +5V) ............ 1 mA (max.)
INPUT RECEIVER
High level input
current (Vin = 2.7V) ....... 100 IlA (max.)
Low level input
current (Vin = O.4V) ....... -1.2 mA (max.)
ADDRESSING
Occupies a block of 16 consecutive memory (1/0) locations. Base address may be located on any 16 by1e boundary in the 20-bit (24-bit optional) address space by two DIP
switches.
PHYSICAL
Outline Dimensions ... 12.00"W x 6.7S"D x O.SO"H
(max.)
304,8W x 171 ,SD x 12,7H mm
Weight ........................ 12 ounces (0.34 kg)
Operating Temperature Range ............... 0 to +5SoC
Storage Temperature Range ................. -25 to +85°C
Relative Humidity ...... 10% to 90% non-condensing
Altitude ...................... 0 to 15,000 feet (4,600 m)
POWER CONSUMPTION
+5Vdc±5%
ST -519 (stand alone)....... 1.7 A typical
ST-519 + 721/0 modules .............................. 3.3 A typical
GENERAL
Bus Compatibility ...... Pin-for-pin, card guide, and
program compatible with MULTIBUS (IEEE 796) and SBC
series microcomputers
CPU Compatibility ...... 8 or 16 bit compatible
DATA FORMAT
The ST-S19 is a memory-mapped peripheral that appears to
the system CPU as 16 bytes of consecutive memory.
These registers can be accessed as 16 single bytes (8-bit
CPU) or as 8 double bytes (16-bit CPU).
The ST-S19 board automatically changes to a 16-bit format
when the BHEN/line on the MULTIBUS pin 27 of connector
P1 goes to zero volts. A high input on BHEN/, consequentIy, sets the board for an 8-bit format.

11-62

INTERRUPT
An 8259A Programmable Interrupt Controller provides onboard interrupt generation to the host's interrupt controller.
This device generates interrupts on low-to-high transitions
from user-selected digital inputs coming into the ST-S19.
Jumpers (pins 64 through 71) tie the selected digital input
lines directly to the selected IR interrupt.
Jumper pins 64 through 71 have two different uses based
upon the mode of operation. In one mode, the MULTIBUS
interrupt priority level (INT 0-7) is jumper-selectable between pin 111 (INT) and the jumper pins for the priority levels as outlined below (pins 103, 104, 10S ... ). For this single-interrupt scheme, the user wires the interrupt source to
an interrupt input pin (pins 64 through 71). Jumper pins 97
through 101, 109 and 110 are not used in this mode.
In the other mode, up to eight interrupt levels are defined
using eight digital input bits to the ST-S19. Each input has a
jumper, pins 97 through 113 (excluding 111). Pins 64
through 71 are user-prioritized and connected (through buffers and jumpers) to the MULTIBUS INT 0-7 lines. This
mode bypasses the 8259A and its interrupt vector address
function. Use this mode when the host provides the necessary vectoring information for servicing the interrupt caused
by the digital input.
~

ST-S19
Jumper
Pin#
111
67
68
66
71
65
70
64
69

Line
Name
INT
IRO
IR1
IR2
IR3
IR4
IRS
IR6
IR7

MULTIBUS
Line
ST-519
Name
Jumper
Pin#
INTO
112
INT1
113
INT2
107
INT3
108
INT4
105
INT5
106
INT6
103
INT7
104

CONNECTORS
The ST-S19 board contains five connectors: P1 and P2 are
the MULTIBUS connectors, and J1, J2, and J3 are the digital 1/0 connectors.
The P2 MULTIBUS connector is used only when a system
controller's address capability is 24 bits. The pin assignment for the four extended address lines on P2 are shown in
Table 1.
The digital 1/0 lines use connectors J1, J2, and J3; Table 2
describes these connections.
Table 1.
IGNAL
ADR16
ADR 17
ADR 14
ADR15

MUL TIBUS Connector P2
Functional Descri ion
4 address line inputs for 24
bit address controllers

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

Table 2
1/0 Connector
Connector
J1
J2
J3
Connector
J1
J2
J3
Pin
Register Register Register
1/0
Pin
Reg ister Reg ister Register
Number Addr Bit Addr Bit Addr Bit Module
Number Addr Bit Addr Bit Addr Bit
2
7
7
2
7
5
8
23
26
1
3
4
7
3
3
4
2
22
28
1
4
6
5
6
8
6
2
2
7
2
6
2
5
5
5
21
1
1
4
1
1
5
8
30
7
2
4
4
8
5
8
4
20
32
1
0
4
0
7
0
2
3
10
19
34
7
7
7
5
3
8
3
3
6
0
12
2
2
2
2
18
5
8
36
0
6
3
6
6
6
14
2
1
1
1
5
8
17
38
5
3
6
5
0
5
16
2
0
0
0
16
40
4
4
4
3
6
5
8
0
1
7
4
7
7
7
18
15
42
3
3
3
3
6
0
20
1
4
7
14
44
6
6
6
0
2
3
2
6
2
1
5
4
5
7
5
22
13
46
1
1
1
3
6
0
1
24
12
48
4
4
4
7
4
0
0
3
0
6
0
1-49: All odd number pinS are tied to ground.

1/0
Module
11
10
9
8
7
6
5
4
3
2
1
0

REGISTER
The following chart details the memory address assignments of the 16 memory locations the 8T-519 occupies. Please note that
when the 8T-519 is used with 16-bit CPU's, every other (even-numbered) address location is used.
8T-519 Register Assignments
8 BIT CPU
ADDRESS

FUNCTION

BASE+O
BASE+O
BASE + 1
BASE + 1

WRITE
READ
WRITE
READ

WRITE OUTPUT 0-7
READ INPUT 0-7
WRITE OUTPUT 8-15
READ INPUT 8-15

REGOJ1

BASE+2
BASE+2
BASE+3
BASE +3

WRITE
READ
WRITE
READ

WRITE OUTPUT 18-23
READ INPUT 16--23
WRITE OUTPUT 24--31
READ INPUT 24--31

REG2J1

BASE+4
BASE+4
BASE+5
BASE + 5

WRITE
READ
WRITE
READ

WRITE OUTPUT 32-39
READ INPUT 32-39
WRITE OUTPUT 40-47
READ INPUT 40-47

REG4J2

BASE+6
BASE + 6
BASE + 7
BASE + 7

WRITE
READ
WRITE
READ

WRITE OUTPUT 48-55
READ INPUT 48-55
WRITE OUTPUT 56--63
READ INPUT 56--63

REG6J3

BASE +8
BASE + 8
BASE + 9

WRITE
READ

REG8J3

-

WRITE OUTPUT 64--71
READ INPUT 64--71
NOT USED

BASE+A
BASE+A
BASE+B
BASE+B

WRITE
READ
WRITE
READ

CLEAR OUTPUT REG 0-7
READ CLEAR REG
CLEAR OUTPUT REG 8
READ CLEAR REG

CLR REG 0

BASE+C
BASE+C
BASE+D
BASE+D

WRITE
READ

CONTROL REG 1, 8259A
STATUS REG 1, 8259A

-

-

8259A
INTERRUPT
CONTROLLER
Refer to INTEL
data sheet

WRITE
READ

CONTROL REG 2, 8259A
STATUS REG 2, 8259A

-

-

BASE + E
BASE+E
BASE+F
BASE+F

-

REGISTER

COMMENTS

ADDRESS
(16 BIT CPU)

BASE +0
REG 1 J1

BASE + 2
REG3J2

BASE +4
REG5J2

BASE+6
REG 7 J3

BASE+8

BASE+A
CLR REG 1

BASE+C

BASE+E

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11·63

ST-519
CLEAR REGISTERS
The clear registers are used to clear (reset) the output registers to all O's. On power-up or system reset, the clear register bits reset all output registers which disables all output
lines. Only after the clear register bits have been set to 1's
will the output (write) function be enabled.
The clear registers format is shown. Refer to 1/0 line section for programming of input/output registers.

OF

07

CLEAR REGISTER FORMAT
CLRREG
(16 BIT CPU)
CLR REG 0
CLRREG 1
(8 BIT CPU)
(8 BIT CPU)
DO D7

I

DO
DO

X X X X X X XI8 7
DON'T CARE

6 5 4 3 2 1 0
OUTPUT REGISTER CLEARED

When a clear register bit is 0, the corresponding output register is cleared forcing output lines to logic high (1).
When a clear register bit is 1, the corresponding output register is enabled to be programmed.

ST-519 Block Diagram

EXTND.
AD DR.
DCDR.

I/O

Jl

ADROO-13

BASE
ADDR
DCDR.
&
CONTROL
LOGIC

in
::J
-

Local DMA
Controller
AM·9517

I

Interrupts

11-68

t···· t

3

ITL

20· or 24·Bit
Address Decoder

PI

Local Interrupt

±15V
DC·Th·DC
Power
Converter

MUITIBUS
Interrupt
Jumper
I

"-

(-,-'t
I

P2

ST-701 Block Diagram

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048·1194ITEL (508) 339·3000ITLX 174388/FAX (508) 339·6356

81·701
FUNCTIONAL SPECIFICATIONS
SYSTEM PERFORMANCE (MUX+PGA+S/H+A/D):

(Typical at +25 degrees C, unless noted)

Following specifications relate to the performance of the multiplexer, PGA, sample and hold, and the AID converter.

ANALOG INPUTS
Number of on-board . . .. . .. 32 single-ended or 16
channels
differential
Number of off-board ........ up to 224S/240D, using
channels
external channel
multiplexer (ST-742)
Total addressable channels .. up to 256S or 256D
Analog Input Range '"
(at PGA gain = 1)
Input Configuration for
on-board multiplexed
channels
AID Output Coding ....

Input Bias Current ..
Input Impedance.

. ± 10 Volts (± 5V, 0 to 10V,
o to 5 volts are jumperable)
... High impedance, voltage
input, non-isolated
. Bipolar 2's complement
binary, bipolar offset binary
or unipolar straight binary.
" .. 8 nanoamps
. .. Power on: 10 megohms
minimum differential or to
ground.
Power off: 1.5 kilohms

Common-Mode Input Range . Both inputs must remain
within ±10 Volts maximum
of analog ground.
Common-Mode Rejection .... 75 dB minimum, gain = 2,
±10V, 60Hz, 1 kilohm
80 dB minimum, gain = 128
imbalance
External AID start trigger. .. TTL compatible, falling edge,
500nS minimum, software
gatable
Input Overvoltage for on- .... ±35V dc, maximum
board channels
sustained
Software Programmable Gain 1,2,4,8,16,32,64 and 128
Amplifier range (DATEl
gain steps
AM-543).
PGA PERFORMANCE
Maximum Settling Time (PGA plus mux) at 10V output step
Gain
1
16
64
128

Settling Time
8 microseconds
12 microseconds
40 microseconds
100 microseconds

Accuracy
±0.02%
±0.05%
±0.10%
±0.20%

Specification

AID type
12-bit
41lS

12-bit
20llS

14-bit
451lS

16-bit
400mS

0.05%

.025%

0.01%

.0063%

.20%

.20%

.20%

.20%

Accuracy, minimum (%
of 10V full scale)
At gain
At gain

=1
= 128

Linearity Error,
maximum

1/2 LSB 1/2 LSB 1/2 LSB 2 LSB

Zero Tempco, maximum 20
ppm of full scale range
per degree Celsius

20

20

10

Full Scale Tempco,
maximum ppm of full
scale range per degree
Celsius

20

20

20

10

81lS

20 IlS

451lS

400mS

1021lS

110 IlS

110 IlS

400 mS

Throughput Period
(10V step input)
At gain
At gain

=1
= 128

AID Conversion Period,

Typical

41lS

20 IlS

451lS

400mS

Maximum

51lS

251lS

541lS

400mS

lOCAL MICROCOMPUTER
Microprocessor ...
Maskable interrupt

..... Z-80A, 3.6864MHz
... connected to MK3801 Serial
Interrupt Timer.

Default Priority

Function

17
16
15
14
13
12
11
10

End of AID Scan (EOS)
End of AID Conversion (EOC)
DMA end of process
Host to 701 new command interrupt
Dual Port RAM Lock
Digital 1/0 #2
Digital 1/0 #1
Digital 1/0 #0

local Random Access ...... 8K bytes, with 256 bytes
reserved for RDX use
Memory (no MUl TlBUS
access)
Dual-Port RAM ............ .4K bytes, relocatable in
Memory-mapped
host memory on 4K byte
boundaries.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

•
11-69

ST-701
Programmable Read-Only ... Up to 16,384 bytes. Accepts
Memory (no MULTI BUS
27128,2764,2732,2716
EPROM's. Supplied with 8K
access)
(2764) EPROM for monitor
and RDX Executive.
Direct Memory Access

Watchdog Timer

. Allows transfers from:
1. AID converter to
Dual-Port RAM
2. AID converter to Local
RAM
3. Local RAM to Dual-Port
RAM
.. Approximately 152 mS
timeout. Synchronizes local
DPR access with Z-80 WAIT
states while waiting for the
host MULTI BUS LOCK signal to grant DPR access.
Continuous host DPR access
cannot exceed 152mS. Also
recovers from out-of-range
memory access and failed
interrupt acknowledge.

Command Parse Time ....... 1 to 4mS, typical.

MULTI BUS INTERFACE

SERIAL INTERFACE
Uses MK3801 Serial Interrupt Timer Controller
Mode. . . .
Baud rate

. .. Full duplex, asynchronous
......... 300 to 9600 baud. Monitor
initializes at 9600 baud.
Operates above 9600 baud
using external clock.

Levels. . . .

. .... RS-232-C (standard),
RS-422/423 (optional pluggable transceivers)

Word Format

.1 start, 8 data, 1 stop, no
parity

Connector

. 26-pin, J1 edgeboard, 0.1"
centers

Digital 1/0 Ports ............ 3 bits, TTL levels, programmable as inputs, interrupts
or outputs on analog channel extension J3.
Programmable Timer ........ 4 internal timers included in
MK3801. Each 16-bit counter
is user-programmable to
interrupt the Z-80A CPU.
Timer D is assigned to the
serial port baud clock.

Specification Conformance .. IEEE-796 MULTI BUS
Type ..................... Memory-mapped, 4096 bytes
Address Selection .......... 16 or 20 bits (for models
without "/24" designator).
(Uses on-board DIP
Switches)
16,20 or 24 bits (for models
with "/24" designator).
8 or 16 bits, bus slave.

Data Transfer .....
ST-701 I nterru pt to Host

.. 1 line, 8 jumper-selectable
sources or by software
command.

Host Interrupt to ST-701 ..... caused by writing to the
DPR Statusllnterrupt Byte.
Bidirectionallnterrupt ...... Implemented in RDX to
Arbitration
resolve simultaneous
interrupt conflicts.

PROGRAMMING LEVELS
Monitor Level .............. Resident in EPROM for
ASCII commands from a
serial port
RDX Executive ............. Included in EPROM.
Accepts ASCII command
lines loaded at either the
DUAL-PORT RAM or the
serial port.
Machine Code Program Load . Local RAM accepts userprograms in Z-80A, or INTEL
HEX format, downloaded
through the Dual Port RAM.

PHYSICAL-ENVIRONMENTAL
MULTIBUS CONTROL SIGNALS
Transfer Acknowledge ...... Jumper-selectable delay,
100 to 800 nanoseconds.
(XACK/)
Note: XACKI is derived from
the bus CCLKI used to
arbitrate DPR access.
Inhibit (INH1/,INH21) ........ These lines are asserted
when the host addresses
within the DPR range.
Bus Lock (LOCK/) .......... The ST-701 will not access
MULTI BUS when the host
asserts this line. During
ST-701 DPR access, LOCK
will cause watch-dog
timeout if held more than
152 milliseconds.
BHENI .................... Controls 8-or 16-bit data
transfer.
11-70

Operating Temperature
Range

.0 to +60 degrees Celsius

Storage Temperature Range .. -25 degrees Celsius to +85
degrees Celsius
Outline Dimensions. . .

.12.0" W x 6.75" 0 x 0.5" H

MULTIBUS dimensions ...... (305 x 172 x 13mm)

"NOTE: Simultaneous DPR access attempts by the host
and the ST-701 are arbitrated by fast address steering logic.
The ST-701 CPU temporarily executes waits for delayed
access. For interleaved access, use moderate duty cycle.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

ST·701
ON-BOARD HARDWARE RESOURCES

MULTI BUS Communications

1. Analog Input Channels

Primary control and data interface to the ST-701 is through the
dual-port RAM (DPR). The DPR overlays host readlwrite
memory and maps memory addresses in the DPR range from
the host into the ST-701 using fully standard MULTI BUS
arbitration. The DPR is relocatable within 24-bit memory space
on 4K boundaries.

This section includes local, non-isolated analog channel-switching
multiplexers (for 32 single-ended or 16 differential channels),
channel address registers, and a software-programmable gain
amplifier (PGA). The channel address registers include automatic
channel sequencing and address drivers for up to 240 singleended or 224 differential external multiplexer channels through
an expansion bus connector. The differential PGA offers gains
from 1 to 128 using a software-Ioadable gain code register.

2. AID Converter ModulelSignal Conditioning
The AID converter is a plugable module with a compatible Sample
and Hold (S/H) amplifier, settling delay and start convert logic, and
buffers. Combined resolutions and speeds are offered from down
to 12 binary bits and 4 microseconds (settling and conversion), 14
bits and 45 microseconds, up to 16 bits and 400 microseconds.

3. Local MicrocomputerlDMA Controller
Using a4 MHz Z-80A CPU, the ST-701's on-board microcomputer
includes up to 16K of ROM and 8K of RAM. The ROM contents,
as shipped, include the RDX command processor and the hex
monitor. This ROM is mounted on a 24-pin socket. The user can
replace this ROM with one of a higher memory density, copying
the software supplied onto the new device. This allows the user
to further customize the microcomputer.
The local microcomputer also consists of a 4k dual-port RAM host
interface, a local DMA controller, an interrupt generator, serial port,
and programmable timers.
The local DMA provides high speed, non-host memory-mapped
transfers between the AID section, local memory and the dual-port
memory. The local microcomputer also has three general purpose
TTL digital lines available on the expansion connector. These bits
are programmable as interrupts, enables, inputs, or outputs.

4. Communications Interfaces
Communications with the ST-701 CPU is through two channels:
an asynchronous serial port and a high speed, 4 kilobyte dual-port
RAM MULTI BUS host interface.

Serial communications
The serial port uses a separate edgeboard connector and supports
conventional EIA RS-232-C communications. A programmable
timer from the CPU is assigned as a baud rate generator, offering
speeds up to 9600 baud. An external clock may be used to go
beyond 9600 baud. Optional circuits on the ST-701 offer differential multidropped RS-422 levels. The serial port has access to the
hex monitor and the RDX executive.

ST-701 transfer logic allows passing 8-or 16-bit data words. ASCII
command strings are written by the host into the DPR, and preformatted AID scans are read from the DPR from two userdefinable DPR buffers. Asynchronous control and status is
managed by bidirectional interrupts through a reserved area at the
top of DPR.
When AID data is ready, the host is notified by a maskable interrupt. The user's interrupt service routine then transfers AID data
blocks to mass storage or processes the information. All transfers
of AID data blocks from local RAM to shared DPR are fully
arbitrated on MULTI BUS using bidirectional lock and transfer
acknowledge signals. No 1/0 addresses are used.
For extended commands (either user-written or developed by
DATEL), the DPR also accepts downloads of executable Z-80 code
blocks and corresponding uploads. The RDX firmware allows for
user-defined commands. Thus the ST-70i may function as a
general purpose data acquisition computer which may be dynamically reprogrammed on the fly (for example, from downloaded disk
code blocks for different functions).

5. On-board Power Converter
A modular dc-to-dc power converter supplies low-noise ±15 volt
dc power to analog circuits. The dc-to-dc converter generates this
from the host +5V dc input, also distributed to the remaining
ST-701 circuits.

SOFTWARE OVERVIEW
Controlling the ST-701 requires using programs resident upon the
ST-701 and within the host. Those on the ST-701 consist of PROMresident routines, user-loaded command strings, and optional transient RAM-executable code. Programs in the host are written by
the user in any language to control the ST-701 and retrieve AID data
blocks. For highest speed, host programs must be linked to the
host interrupt processing scheme. This requires response to the
MULTI BUS interrupt signal selected for the ST-701 using a prestored vector address in the host interrupt service address table.

I! this is not possible, the ST-701 may be operated by polling its
control byte in the top of DPR, but at lower overall host
performance because of polling overhead. The ST-701 does not
assert a vector address on MULTI BUS when it generates an
interrupt. Therefore a host interrupt controller is required to
respond to the interrupt. If a single interrupt line must be
shared with other devices, some form of fast polling may be
required to determine whether the ST-701 caused the interrupt.

After application development, the serial port may be re-assigned
to any application under user program control, such as printer or
magnetic tape output or a LAN interface. It is even possible to fully
control the ST-701 only through the serial port, without installation
into a MULTIBUS card cage.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

11-71

ST·701
Real·Time Data Acquisition Executive (RDX)

X reg (CR) - Examines/modifies the givenZ-80 CPU register. The
register deSignations are as follows:

The ST·701 PROM operates at two levels: a low level Monitor and
a command line Executive (RDX). The RDX may be accessed from
either the serial port or the DPR whereas the Monitor uses only
the serial port. The hexadecimal Monitor accesses local memory,
the DPR, 110 channels and the local Z-80 registers. The Monitor
functions as a user-accessable area of memory for debugging routines, command strings, etc. The ST-701 can be switched between
the two levels by both a local ST-701 terminal and the MULTI BUS
host console.
The Executive mode contains a command line interpreter to load
ST-701 operation modes from an ASCII command structure. The
user builds a command line (either manually or from a host program), loads this into the ST-701, then requests execution. The
command line does not have to be reloaded to repeat an operation. Thus, sequential AID blocks may be collected at high speed.
To assure compatibility with development systems, RDX powers
up in the OFF state, ready for a wake-up command. This leaves
the DPR unaffected by host memory testing. RDX may be commanded ON or OFF at any time.

ST-701 COMMAND FAMILIES
ST·701 Monitor Level Commands
Monitor commands let the user develop ST-701 programs or
extended commands. The user may display blocks of local
memory (including the DPR), examine/modify memory locations
or CPU registers, and JUMP to start execution at any memory
address. An optional breakpoint may be used for debugging. Commands written to the RDX and the Monitor are in ASCII and
hexidecimal formats. From the serial port, the user may easily
switch between the Monitor and the Executive.

Monitor Commands
Monitor commands allow the examination and modification of
ST-701 registers and RAM memory. The contents of the examined
registers and/or memory locations remain unchanged if no new
data is entered prior to a Carriage Return. A description of the available Monitor Level commands follows.
SPOt EXECUTIVE ON (CR) - Enters the ON mode. Processes
all Executive Level commands sent through the serial port or dualport RAM command area.
ST-70t EXECUT/VE OFF (CR) - Enters the OFF mode. Processes
all Monitor Level commands sent through the serial port except
the G ... command.
S adrs (CR) - Examines/modifies ST-701 memory and ST-701
Memory Mapped hardware registers (CR) increments the address
and "." (CR) terminates the command.

Where:
adrs - Memory address in Hex.

1\ C (control C) - Returns to the MONITOR mode if operating at
the Executive Level. Processes all Monitor Level commands
entered through the serial port including the G ... command. "G
(CR)" will return the ST-701 to the prior EXECUTIVE state.

11-72

Z-80 REGISTER

reg

Accumulator
BC pair
DE pair
HL pair
X index
Y index
Stack pointer
PC
Flags

A ora
Bor b
Dord
H or h
Xor x
Y or y
S or s
P or p
For f

To access the second bank of Z-80 registers append the register
mnemonic with an apostrophe. (eg., X B')

o str adrs [,end adrs] (CR) -

Displays the ST-701 memory start-

ing at the given address.
Where:
str adrs - Start memory address (HEX)
end adrs - End memory address (HEX)
G [adrs, break adrs] (CR) - Begins executing at the given address.
A single breakpoint can be included if executing out of ST-701
RAM.
Where:
adrs - Optional starting address.
break adrs - Optional breakpoint address.
Note: This command is disabled while ST-701 is in the OFF mode.

ST·701 Executive Level Commands
The ASCII commands supported at the RDX level can be categorized into three types:

1. General purpose commands
2. MULTIBUS Host/ST-701 interface control commands
3. AID control commands
The Executive Level ASCII commands are supported either
through the serial port or the dual-port RAM (DPR) window. Command strings entered throught the dual-port RAM are to be loaded
eight (8) by1es down from the top of DPR in descending order. Once
the command has been loaded, a "01" HEX write to the top byte
of DPR causes the Executive to process the command.

General Purpose Commands
The RDX Executive (accessible from either the DPR or the serial
port) manages the command registers, A/D channel address
registers and the PGA gai n register. The user may load and read
the command, channel, status, and gain registers or download
ASCII hex programs via the DPR. The commands also allow jumping to an address, releasing ST-701 control to an executing program
in local memory.
CE (CR) - Disables echoing to the serial port of ST-701 command
received via the dual-port RAM.
CE t (CR) - Echos the ST-701 command received via the dualport RAM out through the serial port.

WC xx (CR) -

Loads the ST-701 COMMAND REGISTER.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339·6356

ST·701
Where:
xx - byte value in HEX
RC (CR) -

Reads the ST-701 COMMAND REGISTER.

RS (CR) -

Reads the ST-701 STATUS REGISTER.

WR ss[,ff] (CR) - Loads the ST-701 START CHANNEL REGISTER
and optionally loads the FINAL CHANNEL REGISTER.

Where:
ss - START CHANNEL byte address in HEX.
ff - FINAL CHANNEL byte address in HEX.
RR (CR) - Reads the ST-701 START and FINAL CHANNEL
REGISTERS.

WG xx (CR) -

Loads the ST-701 GAIN REGISTER.

Where:
xx - HEX value between 0 (GAIN
and 7 (GAIN = 128).
RG (CR) -

=

1)

Reads the ST-701 GAIN REGISTER.

MULTI BUS Host/ST-701 Interface Control Commands
The RDX manages the DPR interface by controlling dual transfer
buffers. Using these commands, the user may define the actual
dual-buffer configuration, control the origin of the command acknowledge interrupt, or disable DPR data transfers.

Interface Commands
CA (CR) - Resets bit 0 of the dual-port RAM interrupt/status byte
for status-driven command acknowledge.
CA 1 (CR) - Resets bit 0 of the dual-port RAM interrupUstatus byte
then sets it for interrupt-driven command acknowledge.
DB adr 1, len 1 [,adr2, len2] (CR) RAM transfer buffer(s).

Defines the given dual-port

LO B (CR) - Loads a program into LOCAL RAM or an EXTENDED ST-701 command. The Program or EXTENDED command
must be in INTEL HEX format and is loaded via the dual-port RAM.
Xnewcmd (CR) - Processes the EXTENDED ST-701 COMMAND
previously loaded using the "LD B" command.

Where:
X - The required prefix for all EXTENDED
COMMANDS.
newcmd - The user defined mnemonic for the given
EXTENDED COMMAND.

AID Control Commands
Using the RDX dual buffers, the A/D commands are extensively
structured to allow selection of different analog input channel scan
modes. Types of scan modes include Single channel, sequential
multi-channel and random multi-channel addressing. The start
and end addresses imbedded within a scan command could come
from a previously-downloaded address table.
The structured syntax of the AID command lines allows start/final
addresses and number of scan repeats to be specified in the command. The command also may specify output routing of the A/D
(to either DPR, local RAM and/or serial port) as well as trigger starts
from external input or AID reads. Several automatically repeating
modes are possible and groups of commands may be strung
together on the same command line as long as the AID commands
come last.
The A/D converter may operate in a free-run overlay mode where
the host continually reads scan blocks. This mode precludes entering further command lines. A second mode allows the A/D to
interrupt the host whenever the buffer is full to smoothly synchronize DMA transfers to the host.
All data transfers are fully arbitrated with the MULTIBUS host and
may occur simultaneously with host memory activity in non-DPR
space. Refer to Figure 2.

Where:
adrl - address in HEX of DPR BUF 1.
lenl - length in HEX of DPR BUF 1.
adr2 - address in HEX of DPR BUF 2.
len2 -length in HEX of DPR BUF 2.
Example: DB FOOO, 100, FAOO, 100 (CR)
Note: adr1 and 2 are relative to the ST-701 internal memory.

OS 1 (CR) - Makes BUF 1 the current Active Buffer.
(DEFAULT)

OS 2 (CR) - Makes BUF 2 the current Active Buffer.
DO (CR) - Disables dual-port RAM data transfers until a new "DB"
command is received.
TR M (CR) - Starts multiple conversions on external trigger ila
single channel AID command is sent or starts multiple channel
scans if a sequential or random channel scan A/D command is
sent.
TR (CR) -

NOTE, TIMING NOT TO SCALE

Figure 2: ST-701 and Host Processing Sequences

Disables external tngger.

G adrs (CR) - Begins executing at the given address. Releases
full ST-701 Control to the executing program.
Where:
adrs - Program starting address in HEX.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

II
11-73

ST·701
AID Commands

tive. Most applications will use only this mode since it is simple and
requires no programming (except the host interrupt routines).

AK [chan], mode (CR) - Performs single channel AID conversions

The second mode requires user l-80 programming and should
be considered for special functions (unique data structures, arithmetic, etc.) USing the X command, users may define their own extended ASCII commands which call executable code developed
by the user (or DATEL) and downloaded from mass storage for execution in local RAM. Such user programming would call routines
documented in EPROM.

according to the data acquisition mode selected. No channel increment is performed.
Where:
chan - channel address number in HEX.
S - Single conversion only.
C - Continuous conversions.
F - Continuous conversions until DPR buffer is full.
N, XXXX- "xxxx" number of conversions in HEX.

mode:

HL (CR) - Stops processing the current A/D command and
returns control to ST-701 Executive level.

AS [str chan, fin chan], mode (CR) - Performs sequential channel scanning according to the data acquisition mode selected.
Where:
str chan - Start channel in HEX.
fin chan - Final channel address in HEX.
mode:
S - Single sequential scan.
C - Continuous sequential scan.
F - Continuous requential scan until DPR buffer is
full.
N,XXXX - "xxxx" number of channel scans in HEX.
LC x, nn, adr1, adr2, adr3 . .. adrn (CR) -

Loads random channel

addresses into Channel Address Table.
Where:
x - "I" to initialize new table.
"P\' to append to table
nn - HEX number of addresses to input
adr1 ... n - Channel Addresses (HEX) to load into Channel
Address Table
AR mode (CR) - Performs random channel scanning according

to the data acquisition mode selected.
mode:

S - Single random channel scan.
C - Continuous random channel scans.
F - Continuous random channel scans until DPR
buffer is full.
N,XXXX - "xxxx" number of random scans in HEX.

Deletes the contents of the current Random Channel
Address Table.

LC (CR) -

TR S (CR) - Starts Single conversions on External Trigger if a single channel AID command is sent or start Single channel scan if
a sequential or random channel scan AID command is sent.

The third possible user programming level would be a reprogram
of the EPROM to avoid downloads and permanently store custom
data processing and/or extended commands.

DUAL.PORTED READ/WRITE MEMORY (DPR)
The ST-701 's 4096-byte read/write dual-port RAM (DPR) is shared
with the MULTIBUS host computer. The DPR's fixed base address
is selected by ST-701 address decoder switches. The DPR is accessed through a high speed arbitration circuit which resolves
simultaneous access conflicts between the ST-701 and its host.
The four major uses for the DPR are control/status, ASCII command line loading, AID data block transfer, and optional upload/download of 2-80 code or data. The control/status functions
(including interrupt flags and interrupt arbitration semaphore) occupy a few bytes at the top of DPR. Command lines (terminated
by a carriage return) load downward from this top area after being granted access by the semaphore. The host system sets a control bit in the DPR status/interrupt byte location, causing a local
ST-701 interrupt to parse the command line.
As each command is accepted for execution, the command line
is internally stored in non-MULTIBUS RAM and the host is optionally interrupted to signal successful command start. A/D data
blocks are transferred out to the host through two user-defined
buffers within the DPR space. Preloaded length and offset pointers
near the top of the DPR manage these two buffers using high level
ST-701 data transfer commands. Large data blocks overlay previous data blocks and/or command lines. This is particularly true for
some long command lines which have tables or code/data blocks.

Command Listing
ST-701 ASCII command strings sent to the DPR reflect the simplicity of the structured high-level commands. Both buffer switching
and scan starts may be combined on the same line separated by
an exclamation point. This is similar to combining BASIC statements on one line separated by colons. All the initialization commands (after turning on the RDX EXEC) could be combined on the
same command line.

LEVELS OF USER PROGRAMMING

Example: CA1!CE!WRO,1F!DBO,FF,100,FF .

Users may program the ST-701 's microcomputer at three possible
levels: command line, code download and EPROM reprogramming. The highest level uses only the ASCII command line Execu-

As a general purpose microcomputer dedicated to AID data acquiSition, many simple functions are easily programmed. Access
to the local l-80 microcomputer is fully documented in the ST-701
User Manual.

11-74

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ffEL (508) 339-3000ffLX 174388/FAX (508) 339-6356

ST-702 MULTIBUS
HIGH-ISOLATION
THERMOCOUPLE BOARD

FEATURES:
• 8-Channel MULTI BUS board for temperature
measurements
• Supports J, K, T, S, B, E, and R type thermocouples
• High-level voltage and 4-to-20 mA input capability
• On-board CPU for temperature calculation
• Up to 1,000V peak input isolation
• 13-Bit resolution
• True electronic cold junction compensation
• Output in degrees Celsius or Fahrenheit
• 128 dB CMRR
• 55dBNMR
• Screw terminal signal connections

DATEL's SINETRAC ST-702 is an intelligent MULTIBUS board designed specifically for temperature measurements from

J, K, 1, S, B, E, and R thermocouples. The B-channel AID board filters, amplifies the input signal and provides linearized
digital data to a MULTIBUS host system in °C or OF. The board performs as an ideal front-end to programmable controllers
and similar systems.

GENERAL DESCRIPTION
The ST-702 is an intelligent MULTIBUS analog input board
primarily suited for thermocouple measurements. Features
include isolation, 60 Hz line rejection, and screw terminals
for input signals. The phYSical, functional, and electrical attributes of the ST-702 meet and exceed standards demanded
by the process control industry.
Low-level isolated analog signals from up to eight thermocouples are filtered, amplified, and converted to digital data using
a 12-bit- and sign-integrating AID converter. The on-board
microprocessor linearizes the digital data and outputs a binary
quantity directly to the MULTIBUS host computer in degrees
Celsius or Farenheit. The ST-702 board also provides electronic
cold junction compensation for the thermocouple inputs. The
on-board resources relieve the host system of tasks relating to
thermocouple linearization.
The ST-702 measures temperature from J, K, S, T, E, R, and B
type thermocouples. The analog inputs are galvanically isolated from the MLJLTIBUS, providing a minimum of 750 Volts
RMS common mode isolation. The board's 128 dB Common
Mode Rejection Ratio (CMRR) allows thermocouple measurements even in the presence of high common mode voltages.
The high isolation protects the host computer from high voltage
damages if a thermocouple aCCidentally contacts a high voltage line. The on-board status register indicates error status
information which includes open thermocouple inputs, and
over and under range conditions for the thermocouple inputs.

ORDERING INFORMATION

ST-702

T<--_______
_

INPUT TYPE
A

Input Type

Thermocouple
Isolated
Types J, K, S, T, E, R, B

INPUT RANGES
J -200 to + 760°C

K -200 to +1,232 °C
400°C
S
0 to +1,768 °C
E - 270 to + 1,000 °C
R
Oto+l,768°C
B + 300 to + 1,820 °C
T -200 to +

±2S.6 mV
±S1.2 mV
±102.4 mV
B

High Level Inputs
Isolated

±2.S00 V
±S.OOO V

Current Loops

0-20 rnA
4-20 rnA
O-SOmA
10-SOmA

Part No. 60-2105600 Detachable screw terminal analog input
connector (formerly No. 60-12474-1).

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-75

ST·702
The ST-702 also measures low level ±51.2 mVor ± 102.4 mV
fu"-scale range analog signals from sources other than thermocouples, and provides the raw, unlinearized NO data to the host
CPU. The ST-702 offers gain settings of 1 and 2 when used with
low-level voltage inputs.
Applications with high-level Signal inputs may use model ST-702B.
This model provides ±5V, ±2.5V and current loop signal input
capability. High voltage isolation, 1,OOOV peak, offered by the
ST-702 makes it ideal for most industrial applications.
Functiona"y, temperature is determined by measuring the
potential difference between the measurement (hot) junction and
the reference (cold) junction of the thermocouple leads. The onboard electronic cold junction compensation .logic eliminates
errors caused by temperature variations of the cold junction. The
CJC is effective over a range of 0 to + 60 degrees Celsius.
The ST-702 hardware consists of five sections: MULTI BUS interface section, microprocessor control section, AID converter

section, input signal conditioning section, and CJC section. Figure 1 shows the functional block diagram of the board identifying these sections.
The ST-702 operates from a MULTIBUS host with up to 24-bit
addressing capability. The board also supports 8- or 16-bit data
transfers, allowing use with 8- or 16-bit MULTIBUS systems. The
ST-702 maps onto four consecutive locations in the host system's memory space. Optionally, the board is configurable in
the host system's 110 address space using jumper selections.
The ST-702's MULTIBUS interface signal includes an XACKI
signal that allows delays from 100 to 800 nanoseconds.
The ST-702 is fully bus and card cage compatible with the MULTIBUS. The board is 12.0 inches wide x 6.75 inches deep x 0.5
inches high (305 x 172 x 13 mm). Multiple ST-702's fit into
adjacent card slots of a standard .60 inch spacing card cage.
The ST-702 uses power from the MULTI BUS + 5V line. The onboard dc-to-dc converter provides ± 15V to drive the board's
analog circuitry. Total current drawn from the MULTIBUS + 5V
line is 1.6 A, typical.

!NTO·7
INH 11
INH21

CCLKI
XACKI
BHENI
MWTCI

lowel
MRDeI

IORCI
INITI

ADDRESS

Figure 1:

ST-702 Block Diagram

FUNCTIONAL SPECIFICATIONS
All specifications typical at + 25 degrees Celsius unless otherwise noted.

Electrical Characteristics
Analog Inputs ...
. ............... 8
Input Impedance ...... .
.100 Megohms
Input Bias Current, maximum ............. 8 nanoamps
Common Mode Voltage Range, Channel to Channel and
Channel to MULTI BUS ground AC,
50 or 60 Hz ............................. 750V RMS
AC or dc Isolation, peak maximum .......... ± 1,OOOV
Common Mode Rejection Ratio, minimum,
Rs
1k f
0.01 to 100 Hz
ST-702A ............. .
. ............ 128 dB
ST-702B ......... .
. .... 110 dB
Maximum Safe Differential Voltage without
Damage .................................130V RMS

=

11-76

=

Normal Mode Rejection at 50 or 60 Hz minimum ... 55 dB
Input Lead Resistance Effects .................... none
Input Voltage Ranges ...................... ± 25.6m V
(combined range jumpers and software PGA) ± 51.2m V
± 102.4m V :702A
±2.5, ±5V dc :702B
Voltage Range Accuracy, maximum
ST-702A .............................. 0.03% FSR
ST-702B ................................ 0.1% FSR
Voltage Range Gain Drift, maximum ......... 45 ppm/oC
Voltage Range Input Offset Drift
Input Range
Offset Drift (RT I)
+ 25 mV
31'V/oC
50 mV
3p.VloC
± 100 mV
3.5p.VloC
± 2.5 V
55p.VloC
±5 V
55p.V/oC
Address bus ......................... 16, 20 or 24 bits
Data transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 or 16 bits
using BHEN/, memory mapped (standard) or
110 mapped Oumperable)

±

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ST-702
Power Supply Requirements
With internal dc-to-dc ...... +5V de ±O.5% @1.6 A
Converter
No dc-to-dc Converter ..... +5V dc ±0.5% @1.0 A
+15V dc ±0.5% @.15A
-15V dc ±0.5% @.075A
Interrupt to MULTIBUS .......................... 1 line
jumperable INTOI to INT71
THERMOCOUPLE INPUT RANGES
Thermocouple
Type

J
K
S
T
E
R
B

Temperature
Range
(degrees C)
-200 to 760
- 200 to 1232
o to 1768
-200 to 400
- 270 to 1000
o to 1768
300 to 1820

Input Voltage
Range
(mV)
-7.890 to
- 5.891 to
0.000 to
- 5.603 to
- 9.835 to
0.000 to
+0.431 to

+42.922
+ 49.988
+ 18.698
+ 20.869
+ 76.358
+ 21.1 08
+ 13.814

PHYSICAUENVIRONMENTAL
Outline Dimensions ....... 12.0 inches wide x 6.75 inches deep
x 0.5 inch high (305 x 172 x 13 mm)
Weight . . . . . . . . . . . . . . . . . . 1 pound 2 ounces
Operating Temperature .... 0 to 60 degrees Celsius
Range
Storage Temperature ...... -20 to +80 degrees Celsius
Range
Relative Humidity .' ...... 0 to 80%
noncondensing
Altitude ............
. .. 0 to 15,000 feet (4,500 meters)
ST-702 PROGRAMMING INFORMATION
Programming the ST-702 essentially consists of using four
registers. The registers are the Data Ready register, Command
register, Status register and the AID data register. These registers
appear as four consecutive locations in the CPU's address space.
Table 1 lists the functions of these registers.

Table 1:

ST-702 Register AsSignments

THERMOCOUPLE TEMPERATURE ACCURACY
(Maximum) with board at +25°C
Temperature
Thermocouple
Range
Type
(degrees C)

Input Voltage
Range
(mV)

Accuracy
(degrees
C)

Address
BASE + 0

Function
READ

Register
Name

Description
Read Data Ready
status
Write Analog Data
command

Data Ready

J

-200 to -100 - 7.890 to - 4.632
-100 to + 760 - 4.632 to + 42.922

±3
±1

BASE + 1 WRITE

Command

K

-200 to -100 - 5.891 to - 3.553
-100 to +1,232 - 3.553 to + 49.988

±3
±1

BASE + 1 READ

Status

S

o to +300 0.0000 to + 2.323
+300 to +1,768 +2.323 to +18.698

±6
±3

BASE + 2 WRITE
BASE + 2 READ

AID Data (low)

BASE + 3 WRITE
BASE + 3 READ

AID Data (high) Read Analog

T

-200 to 0
o to +400

- 5.603 to 0.000
0.000 to +20.869

±3
±1

E

-270 to -200
-200 to 0
o to + 1,000

- 9.835 to - 8.824
- 8.824 to 0.000
0.000 to + 76.358

±10
±3
±1

R

o to +300
0.000 to + 2.400
+300 to +1,768 + 2.400 to + 21.108

±4
±2

B

+300 to +500 + 0.431 to + 1.241
+ 500 to + 1,000 + 1.241 to +4.833
+1,000 to +1,820 + 4.833 to + 13.814

±5
±3
±2

TIME AND TEMPERATURE RELATED DRIFT
Time related
Temperature related
Thermocouple
drift
drift
Type
(degrees C/6 months) (degrees C/degree C)

J

±0.2

±0.1

K

±0.25

±0.15

S

± 1.0

±0.3

T

±0.25

±0.1

E

±0.2

±0.15

R

±0.8

±0.3

B

± 1.0

±0.3

Read Analog Data
status

-

-

Read Analog
Data, low by1e

-

-

Data, high byte
Data Ready Register
The host CPU reads this register to determine if valid data and
status information is available in the AID Data and Status
registers. The Data Ready register indicates to the host system
if the Command register is ready to receive a new command.
Bit 0 is set to 1 when a command is written to the register, then
resets to a zero as soon as the command is accepted. Figure
2 shows the format of the data ready register.
LOCATION: BASE + 0

5

7

4

2

o

(JUMPERABlE MUlTIBUS INTERRUPT)

o~
1

~

o~
1

~

DATA/STATUS NOT VALID
DATAISTATUS VALID
COMMAND REGISTER READY
BUSY, COMMAND BEING PROCESSED

Figure 2:

ST-702 Data Ready Register

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-77

ST·702
Command Register

Table 2:

The Command register allows the ST-702 to operate in random
mode or sequential mode. Programming the Command register
selects the output data coding, PGA gain code, and calibration.
The Data Ready register monitors successful completion of the
command. Figure 3 shows the Command register format.

S7

7

6

5

3

4

2

CHANNEL ADDRESS

1
o

= SEQUENTIAL MODE
= RANDOM MODE

o = 2·S COMPLEMENT
1 = SIGN + MAGNITUDE

Error Number
S6
S5
S4

0
1
1
1
1
1
1
1
1

LOCATION: BASE + 1

Error Status Conditions

0

0

0

0
0
0
0

0
0

0

1
1

0

1
1
1
1

0
0

0

1
1

0

Error
No error
Calibration mode
Data out of range
Open wire detection
Board not ready
CJC out of range
CJC and data out of range
CJC or open wire
Memory or board failure

1
1
1
1

AID Data Register
The AID data register contains either the raw reading from the
AID converter or the linearized data from a thermocouple, depending on the operating mode. Data is either a 12-bit 2's complement or a sign plus 12-bit number. MSB or sign bit appear in the
four MSB positions for ease of sign detection. The data is in a
binary format. Figures 5a and 5b show register formats for the
AID data registers.
LOCATION: BASE + 3

Figure 3:

ST-702 Command Register Format

Status Register
The contents of the status register indicate error conditions,
channel selected, and the unit for temperature measurement.
Figure 4 shows the status register format. The status register
determines validity of data in the AID data register. Bits 4 through
7 of this register indicate open inputs, CJC and data out of range
status, and possible ST-702 hardware failures. If the ST-702 fails
the self-test at power-up, the status bits indicate RAM or ROM
failure and turn the BOARD OK lamp off. If the calibration switch
is turned on during normal operation, the status bits indicate
this condition. Table 2 lists the error status indications.
LOCATION: BASE + 1

7

7
MSB/I
SIGN.

6

5

4

MSBI
SIGN

MSBI
SIGN

MSBI
SIGN

Figure Sa:

o

3

AID Data Register Format (High Byte)

LOCATION: BASE + 2

7

6

4

3

2

o
LSB

Figure 5b:

AID Data Register Format (Low Byte)

5

CHANNeL ADDRESS

o
1

= DEGREE CELSIUS
= DEGREE FAHRENHEIT

STATUS BIT 4

'------1 STATUS BIT 5
' - - - - - - 1 STATUS BIT 6

L...------t
Figure 4:

11-78

STATUS BIT 7

Status Register Format

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ST·702R
a·CHANNEL MULTIBUS
RTD AID BOARD

FEATURES
• a·Channel MULTIBUS· board for RTD
temperature measurements
• Internal 0.4 mA current excitation
• Supports 100 ohm RTD's
• Output in degrees Celcius or Fahrenheit
• 12·bit plus sign resolution
• On·board CPU for temperature
calculation/linearization
• 4 switch selectable sample rates to 30s/sec
• Screw terminal signal connections

DATEL'S SINETRAC ST-702R IS AN INTELLIGENT MULTIBUS BOARD DESIGNED SPECIFICALLY FOR TEMPERATURE MEAS·
UREMENTS FROM 100 OHM RTD'S. THE 8·CHANNEL AID BOARD FILTERS, AMPLIFIES THE INPUT SIGNAL AND PROVIDES
LINEARIZED DIGITAL DATA TO A MULTIBUS HOST SYSTEM IN °C OR OF. THE BOARD PERFORMS AS AN IDEAL FRONT-END
TO PROGRAMMABLE CONTROLLERS AND SIMILAR SYSTEMS.

GENERAL DESCRIPTION
The ST-702R is an intelligent analog 110 board for MULTI BUS
based computers that is primarily suited for RTD
measurerl'lents. Low level analog signals from an RTD are
filtered, amplified and converted to digital data using a 12-bit
plus sign integrating AID converter. The on·board
microprocessor linearizes this data and outputs a binary
quantity to the MULTIBUS host computer directly in degrees
Celsius or Fahrenheit, thus relieving the host CPU of the time·
consuming task of RTD linearization.
The ST-702R is fullycompatiblewithall MULTI BUS computers
and supports systems with up to 24 bit addressing capability.
The board aisosupportsBor16 bit data transfers,allowing use
withBor 16bit MULTI BUS CPU boards. TheST·702R isshipped
as a memory mapped peripheral occupying 4 consecutive
locations. in the CPU address space. Alternatively, it can be
configured to appear in the 1/0 address space of the CPU
through jumper option.
In order to make the ST-702R compatible with different speed
CPU and memory systems, a Transfer Acknowledge Delay circuit (XACKIDELAY) is provided. Eight delays from 100 to BOO
nsec are jumper selectable by the user.

ST-702R PROGRAMMING INFORMATION
Programming the ST-702R essentially consists of using four
registers. The registers are the Data Ready register, Command
register, Status register and the AID data register. These
registers appear as four consecutive locations in the CPU's address space. Table 1 lists the functions of these registers.

Table 1: ST·702R REGISTER ASSIGNMENTS
ADDRESS

FUNCTION REGISTER NAME

BASE

+0

READ

ADRDY

BASE

+ 1

WRITE

ADCMD

DESCRIPTION
Read Data Ready Status
Write Analog
Data Command

BASE

+ 1

READ

ADSTAT

Read Analog Data Status

BASE
BASE

+2
+2

WRITE
READ

ADLOW

Read Analog Data Low Byte

+3
BASE + 3

WRITE
ADHIGH

Read Analog Data High Byte

BASE

READ

The ST-702R is fully bus and card cage compatible with the
MULTIBUS. The board is 12.0"W x 6.75"D x 0.5"H (305 x 172 x
13 mm). Multiple ST·702R boards may be mounted in adjacent
card slots when used with a standard .60" spacing card cage.
The ST·702R draws all of its power from the MULTI BUS + 5V
line. An on-board DC to DC Converter provides the ± 15V to
drive the board's analog circuitry. Total current drawn from the
MULTIBUS +5V is 1.6A typical.
The ST·702R hardware consists of four main sections;
MULTIBUS interface, microprocessor, AID converter and
signal conditioning (with excitation)·sections. Refer to the
block diagram in figure 1 for the general layout of the ST-702R
board.

ORDERING INFORMATION
ST-702R

RTD AID Board

60-2105600
(formerly
60·12474-1)

Detachable Screw Terminal Connector
(not included with board).

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

11-79

ST·702R
ANALOG INPUT SPECIFICATIONS
General

FUNCTIONAL SPECIFICATIONS
AID Conversion Rate Selection
The ST-702R provides for a choice of four AID Conversion rates:
15 or 30 conversions per second for 60 Hz environments, and
12_5 or 25 conversions per second for 50 Hz. Since an integrating AID converter is used on the ST-702R, it is desirable to
operate it as a multiple of the AC line frequency in order to
obtain normal mode rejection of any AC signals on the analog
inputs. The board is shipped standard configured for 15 conversions per second. Use of the faster (30/25) conversion rate will
result in decreased normal mode rejection (NMR). AID Conversion Rate'Selection is accomplished by switches S3-2 and S3-3
on the best ST-702 board. Switch settings are described below.

CONV/SEC

S3-2

S3-3

FREQ

12.5
15
25
30

OFF
OFF
ON
ON

OFF
ON
OFF
ON

50HZ
60HZ
50HZ
60HZ

Number of Channels
Isolation
Input Configuration
InputType
RTD Input Type
European curve
Alpha
.00385
American curve
Alpha
.00392
Input Lead
Resistance Effect
Internal Current
Excitation
Digital Output
Digital Output
Coding

=
=

Resolution

AID Conversion Rate Selection

Switch Selectable
Sample Rates

PERFORMANCE - ANALOG INPUT

8
None
3 Wire

RTD
Range
- 200 to 850 deg C

Equivalent Ohms
[18.49 - 390.265 ohms]

- 200 to 630 deg C

[17.14 - 327.02 ohms]

None

0.4mA
deg C or deg F
[Selected by Switch]
2's Complement or [Selected by ADCMD
Sign and Magnitude 2'Comp. for Voltage
Range]
12 Bit Plus Sign
and Over Range
12.5/Sec
(50 Hz)(60 Hz)15/Sec
251Sec
(50 Hz)(60 Hz)3O/Sec

- Frequency Environments
SPECIFICATION
Input Offset Volt
Adj. to zero
Channel to channel
Input Bias Current
Over Volt Protect
Input Impedance
[Differential
to ground]
Input Noise volt.
0.01 Hz to 100Hz
Input Span Range
Normal Mode
Rejection 50/60 Hz
Temperature Drift
Gain Drift
Offset Drift
System Accuracy
European
Alpha = .0385
-200 to O°C
o to 850°C
American
Alpha = .0392
-200 to OOC
o to 630°C

11-80

MINIMUM

MAXIMUM
±

150~V

± 25~V
10na
130VRMS

POWER SUPPLY REQUIREMENTS
With DC/DC Converter
Installed for ± 15 Volts
No DC/DC Converter

100 megohms

+ 5V dc ± 0.5% @ 1.6A

(2.5A max)

+5Vdc ±0.5%@1.0A
(1.5Amax)
+ 15V dc ± 0.5% @ .15A (.2A max)
-15Vdc ±0.5%@.075A (.lAmax)

CONNECTOR SPECIFICATIONS
1.5~V

18.49 ohms
24 DB

pop
400 ohms

± 1I'V/deg.C
25 ppm/deg.C
0.03 deg/deg

±3deg.C
± 1 deg.C

MULTIBUS

Analog Input -

Pl 86 (dual 43) pin
card edge connector
P2 60 (dual 30) pin
card edge connector
Jl 36 (dual 18) pin
card edge connector

[.100 inch center]
[.200 inch center]
Mating connector
BuchananPCB3A36A
Datel Ref.
60-12474-1

PHYSICAL - ENVIRONMENTAL
Outline Dimensions
Weight

±3deg.C
± 1 deg.C

[.156 inch center]

Operating Temperature
Range

12.0"W x 6.75"0 x 0.5"H
(305 x 172 x 13 mm)
1 lb. 2 oz.
oto 60 Degree C

Storage Temperature
Range

- 20 to + 80 Degree C

Relative Humidity
noncondensing

Ot080%

Altitude

oto 15000 feet
(4500 meters)

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ST·702R
Data Ready Register
The host CPU reads this register to determine if valid data and
status information is available in the AiD data and status
registers. Bit 0 indicates whether the on· board microprocessor
has read the previous command that was written to the Command Register by the MULTIBUS. Data Ready is cleared upon
power-up and is set by the Microprocessor when Data/Status
is loaded. Data Ready is cleared when MULTIBUS writes a command or reads AiD data. Command Ready is cleared on powerup and is set when a command is written. Command Ready is
cleared when the Microprocessor reads a command. Figure 2
shows the format of the data ready register.
LOCATION: BASE + 0

7

6

4

3

o

2

Random Mode, the data from the analog channel in BitsO-2wili
be loaded into the AiD Data Register. When the host CPU reads
this data, the ST-702R will re-execute the last command loaded
into the Command Register and load the new data into the AiD
Data Register. Operation in Sequential Mode is similar, except
that when the host CPU reads the AID Data Register, the data
from the next sequential channel is loaded. For example, in
order to. continuously monitor a Single channel, the host CPU
must wnte the channel numberwith Bit 4 set toa "0" in the Command Register. When the Data Ready Register indicates that
the data is valid, (oran interrupt occurs), the host CPU reads the
data from the AID Data Register. At this time, the ST-702R will
load the last acquired sample from the selected channel into
the AiD Data Register. It should be noted that the Command
Register may be written with a new command to change either
the channel number or the operating mode, providing that Bit 0
of the Data Ready Register is set.
Bit 5 is used to determine whether the ST-702R will output the
analog data in either 2's Complement or Sign plus Magnitude
format.

O=COMMAND NOT ACCEPTED
1 = COMMAND ACCEPTED

Figure 2:

Calibration Mode

ST-702R Data Ready Register (BASE +0)

Command Register
The ST-702R may be easily programmed to operate in two basic
modes of operation: Random Mode or Sequential. It mayalso be
programmed to output data in several different formats to the
host computer. In Random Mode, the host computer simply
writes a command word to the ST-702R Command Register as
depicted in Figure 3. The Data Ready Register may then be
monitored to determine when data and status information is
ready.

A mode is provided for use in calibrating the analog Circuitry on
the ST-702R board. Writing a 1 in bit 7 of the Command Register
will place the ST-702R in the Calibration Mode. In normal operation, the on-board microprocessor is continuously performing
AiD conversions sequentially on all eight AiD channels.

o=

RANDOM MODE
1 = SEQUENTIAL MODE

Bits 0-2 are used to map which channel theST-702R is to convert
and subsequently place the data in the AiD Data register. In Random Mode, the ST-702R will transmit the analog data for the
channel number in Bits 0-2. Data from the next consecutive
channel will be loaded into the AiD Data register when the
previous data is read by the host CPU.
Bit 4 is used to select either random or sequential scanning
operation and must be set to '0' for random mode operation. In

L....._ _ _ _

Figure 3:

~ ~ ~·I~~O+M~~EGMN~~~DE

ST-702R Command Register Format (BASE + 1)

DATA 0-7

JNT0-7

""0

INP\JT
CHANNELS _ _ _- - , . /

INH 11
INH 21

....."

CONDITIONING

CCLKI
XACKJ

""""'''

lowel

BHENI
MWTCI

MRDel

IORCI
INIT!

,ADDRESS
0-17

+5V de

Figure 1:

ST-702R Block Diagram

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11-81

ST·702R
Status Register

AID Data Register

The ST·702R Status Register is loaded by the on·board micro·
processor along with the AID Data register. This register should
be monitored by the host CPU to determine whether the AID
Data Register contains valid AID Data or if some error has been
detected. It also contains status information in Bits 4·7 in·
dicating DATA out of range status, and indications of possible
hardware malfunction in the ST·702R. Also, Bits 0·2 of the
Status register contain the channel number for the data in the
AID Data Register.

The AID Data Register is loaded by the ST·702R board and
contains either the raw reading from the AID Converter or
the linearized data from an RTD depending on the mode of
operation. Data is either a 16 bit 2's Complement or Sign
plus Magnitude format.

LOCATION: BASE

7

6

+1

ND DATA REGISTER HIGH BYTE (BASE
7

5

4

3

6

MSB/I
SIGN.

2

5

MSBI I MSBI
SIGN . SIGN

Figure 5a:

CHANNEL ADDRESS

4

AID Data Register Format (High Byte)

'------I

AID DATA REGISTER LOW BYTE (BASE

7

STATUS BIT 4

o

2

3

MSBI
SIGN

o = DEGREE CELCIUS

1 = DEGREE FAHRENHEIT

+ 3)

4

+ 2)

o

2

3

LSB

STATUS BIT 5

L -_ _ _- I STATUS BIT 6

'--_ _ _ _--1 0
1

Figure 4:

= DATNSTATUS VALID (optional
= DATNSTATUS NOT VALID

ST·702R Status Register Format (BASE

Figure 5b:

AID Data Register Format (Low Byte)

interrupt)

+ 1)

Error Status Indication
The ST·702R performs some self·testing at power·up time. The
on·board microprocessor tests its internal ROM and RAM.
While this test is being conducted, the Status Register in·
dicates the Board Not Ready Status code. Commands should
not be written to the Command Register at this time. If either
test shou Id fai I, the ST·702R sets the Status bits indicati ng RAM
or ROM failure. If this occurs, the board will endlessly loop with
the BOARD OK lamp off. If the board detects that an input chan·
nel is open, or that measurements are outside of the normal
operating RTD temperature range, the Status Bits will reflect
this condition. Finally, if the Command Register is written while
the Board Calibrate Switch is ON, the Status Register will
indicate this error condition.

RTD Type Selection
The ST·702R provides the capabilityto independently select the
desired type of RTD for each group of 4 input channels. For ex·
ample, Channels 0·3 could be set for European operation while
Channels 4·7 could be set for American. RTD type selection is
selected by a combination of switches and jumpers on the PC
Board. This is described in Figure 6.

S3·5
S3·8

S3·6
S3·9

S3·7
S3·10

European
oc .00385

ON

ON

ON

American
oc .00392

ON

ON

OFF

CH 4·7
CHO·3

=
=

Figure 6:
Error Number
S7 S6 S5 S4
0
1
1
1
1
1
1
1
1

0
0
0
0
0
1
1

0
0
0
1
1
0
0

1
1

1

0
0
1
0
1
0
1
0

1

1

Table 2:
11-82

Error
No error
Calibration mode
Data out of range
Open wire detection
Board not ready
Not used
Not used
Not used
Memory or board failure

RTD Input Range Selection

Degree C/Degree F Selection
Degree C - Place S3·4 ON position
Degree F - Place S3·4 OFF position

Error Decoding

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

SineTrac™ . ST· 703
FEATURES

12-Bit, 4 Channel Isolated
MULTIBUS D/A Board

• 4 01 A Channels using 12-bit monolithic converters
• 300 VRMS Isolation, channel-to-channel and channel·
to-bus
• Accurate to .05% of full-seal!! reading
• Uses identical programming and register assignments
to SBC-711/732/724 and ST -711/732/724 boards
• Includes 4 externally excitation 4-20 mA current loop
channels
• Memory mapped, with 24-, 20-, or 16-bit user selectable
base address
• Compatible with both 8- and 16-bit CPU's (8- or 16-bit
data transfer)
• Complete hardware and software compatibility with
MULTIBUS and SBC series microcomputers

INTRODUCTION
DATEL expands its line of MULTI BUS and SBC compatible
analog output boards with the SineTrac ST-703. The ST-703
provides 4 channels of isolated digital-to-analog (D/A)
conversion with 12 bits of resolution. Overall voltage output
accuracy is within ± .05% of full-scale range. To ensure the
board's compatibility with popular process control and test
instrumentation, four voltage ranges and a 4-20 mA current
loop output are jumper selectable for each D/A channel.
Like other SineTrac products, the ST-703 is fully hardware·
and-software-compatible with its hostiSBC or MULTI BUS
computer. All necessary address decoders, logic controls,
and data receivers are built-in. The user installs the ST-703
into an Intel·compatible card cage and wires the analog out·
puts. The ST-703 is then configured as a memory-mapped
peripheral which is addressed by the host computer as eight
consecutive memory locations with a user selectable base
address. This memory-mapped format allows unlimited D/A
channel expansion by using multiple ST-703's, each with a
different base address.
The ST-703 is pin compatible with the ST-724, SBC-724, and
ST-728 analog output boards. The ST-703 may be used with
both 8- and 16-bit microprocessors. The BHENlline on the
MULTIBUS sets the ST-703's address decoders and data
latches for compatibility with 8- or 16-bit computers. The
ST-703 also supports 24-bit MULTI BUS addreSSing capability and is downward compatible with 16- or 20-bit systems.
The most unique feature of the ST-703 is its 300 V channelto-channel and channel-to-bus isolation. Applications include
situations where a low-level analog signal must be superimposed on a high voltage, such as testing of power supplies,
isolation amplifiers, et cetera. The ST-703 is also useful in
applications where actuator failure could cause computer
errors or destruction from line voltages being applied to the
MULTIBUS. Isolation is accomplished through a combination
of optoisolators for digital signals, and transformer isolation
for power distribution. An on board dc-to-dc converter provides
four individually isolated supplies for the D/A converters.
The systems manual shipped with each board provides installation instructions, theory of operation, and engineering
drawings.

GENERAL DESCRIPTION
Data inputs to the ST-703 are from the host computer's bus.
Input coding may be straight binary, offset binary, or 2's
complement, and is selectable on the board.
The MULTIBUS BHENlline is used to set the ST-703's
address and data coding for compatibility with 8- or 16-bit
CPU's. In the eight-bit mode, the 12 bits of data required for
the D/A converters are acquired in two bytes. The lower byte
contains the four lower data bits, and is loaded into a storage
register for each D/A channel on the ST-703. The next data
byte contains the eight higher bits. Upon conversion, the eight
MSB's and the four stored LSB's are loaded simultaneously
into the DAC. In the 16-bit mode, all 12 data bits are transferred in a single word to the DAC data register. The register
outputs are optically isolated and transferred to the D/A
converter.
Each channel uses a DATEL model DAC-7541, a 12-bit monolithic device which offers linearity of ± .02% of full·scale
range. The converter output is monotonic, having a differential nonlinearity of ± .02% FSR maximum. Offset error on
each channel is preadjusted to zero. Trim positions on the
board permit recalibration of zero (or offset) and gain settings.
Two-speed versions of the board provide settling times of
5 !-,Sec. and 30 !-,Sec. respectively. Zero tempco is ± 2 ppm
of FSR/degree Celsius and gain tempco is within ± 10 ppm
of FSR/degree Celsius.
The output of each isolated DAC is fed to its own I-to-V conversion amplifier. A total of four voltage output ranges may
be jumper selected by the user: 0 to + 5V, 0 to + 1OV, ± 5V,
and ± 10V. In addition, a V-to-I converter circuit is provided
for each D/A output channel. A 4 to 20 mA output, usable
with an output load from 0 to 500 Ohms, is also jumper
selectable.
The ST-703 contains a power-on reset circuit that allows each
D/A output to be set to O.OOOV at power-on time regardless
of the input coding and output range configuration.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11·83

II

5T-703
The current output requires an external excitation source, a
+ 18V to + 30V dc regulated supply capable of 25 rnA per
D/A channel. Voltage and current ranges on the ST-703 are
selected individually for each channel. This allows a mix of
voltage or current outputs on a single board.
The ST-703 is a memory-mapped peripheral occupying eight
consecutive locations in the computer's address space. The
board's base address is factory-set at OOFF10 Hex. However,
a user may relocate the board address anywhere up to
FFFFF8 on a-byte boundaries using DIP switches on the
board.
To make the ST-703 compatible with different speed CPU's
and memory systems, a Transfer Acknowledge Delay (XACKI
Delay) is provided, permitting eight selectable delays from
o to 700 nSec. in 100 nSec. increments.

The ST-703 is fully bus-, card cage-, and software-compatible with the MULTIBUS and with Intel RMX software. The
board is 12.0 inches wide x 6.75 inches deep x 0.54 inch
high (305 x 172 x 14 mm). Multiple ST-703 boards may be
mounted in adjacent card slots when used with a standard
.60 inch spacing Intel card cage.
The ST-703 draws all its power from the MULTIBUS + 5V and
+ 12V lines. An on-board dc-to-dc converter provides four
isolated ± 15V supplies to drive the analog output circuits.
The ST-703 weighs approximately 12 ounces (0,341 kilograms). It can operate over a temperature range of 0 to + 55
degrees Celsius with relative humidity from 10 to 90% (noncondensing), and from 0 to 15,000 feet (0 to 4,600 m) in
altitude.
MULTIBUS, iSBC, and RMX are trademarks of the Intel Corp.

5T-703
BLOCK DIAGRAM

REGISTER OPTOISOLATORS
MWTC
BASE
ADDRESS
DECODER
AND
FUNCTION
CONTROL
LOGIC

CCLK
INIT
XAti<

! - -__ VOUT·

XACK
DELAY

0

"'

0



~

&::

I
~

TPI

P3

~

...

o
I»
~

TP3

...

TP4 TPS

.

TP2

1
3'
2 • • a4

.

."

...

...

34 3536

12

...

..

40

26

54

•

41 42

27 28

13 14

fi

4849 50

...

...

~

...

...

23 24 25

91011

~

30·· •
.3
33

19

6 7 8

(1)

29a31

16- • • '8

5

ffiB

...

TP7 TPS TP9

15

TP5

5556

~

~

.....

~

m

r

~
~

~
.....

~

~

~
~

~

m

~

::Den

C .....

r-..l

...

6061 62

~a

oc:

...
...

...

57 58 59

697071

12 73 74

063
'64
'65

.75

-t

076

...

...

'77

787980

666768

0').

D

. . . .. .

z-

......

9799101

103 105 107 109 111

52

98 iDO 102

104 106 108 110 112

o

o

P1

:2

PZ

~

I
F

ST-703
OPTOISOLATOR SPEED CONFIGURATION

CALIBRATION

The ST-703 is available with a choice of two setting time
options. Since/because the DAC data lines are optically
coupled, the DAC settling time is dependent on the switching
times of the optoisolators used. A jumper is provided to select
the settling time and is dependent on the type of optoisolator
installed on the board,

The ST-703 board is calibrated for a voltage output range of
± 10V and Offset Binary coding. Calibration is required if the
output range is changed for any of the D/A converters. A 4'/2
digit digital voltmeter is required. To calibrate the ST-703,
perform the following steps in order.

SETILING TIME JUMPER

1. Use the following table (speCifications) to connect the digital
voltmeter (DVM) to the test point, corresponding to the DAC
to be calibrated.

MODEL

DACO

DAC 1

DAC2

DAC3

ST-703A

E12-E13

E26-E27

E40-E41

E54-E55

ST-703B

E13-E14

E27-E28

E41-E42

E55-E56

NOTE: The settling time jumper is programmed per the
model number. It should not be changed to avoid permanent damage to the optoisolators.

(FULL-SCALE)
+9.9800 V REFERENCE ADJUSTMENT
TEST POINTS

CONNECTORS
The ST-703 board contains three connectors: P1 and P2 are
the MULTIBUS connectors, and P3 is the Analog Output
connector.
The P2 MULTIBUS connector is used only when a system
controller's address is 24 bits. The pin assignment for the
four (extended) address lines on P2 are shown in Table 1.
P3 is the Analog Output connector, which is described in
Table 2. For current loop connection, refer to the current loop
circuit.
Table 1. Multibus Connector (P2)
PIN

SIGNAL

55

ADR 16

56

ADR 17

57

ADR 14

TPI

DAC 1
TP4

DAC2

DVM + INPUT

TP7

DAC 3
TP10

DVM

TP3

TP6

TP9

TP12

R3

R25

R69

R93

DAC 0

PIN

2. Connect the digital voltmeter (DVM) to the test point in the
following table, corresponding to the DAC to be calibrated.

FUNCTIONAL DESCRIPTION

for 24 bit address controllers.
ADR 15
Table 2. Analog Output Connector (P3)
(COMPONENT SIDE)
FUNCTION

PIN

FUNCTION

Pins 1 through 22
are no connection
23
25
27
29
31
33
35
37
39
41
43
45
47
49

INPUT

Adjust the potentiometer for a reading of + 9.9800 volts.

NEGATIVE REFERENCE ADJUSTMENT
TEST POINTS

4 address line inputs
58

~

POT

Analog Ground D/ A CH 3
LOOP I RTN D/A CH 3
Analog Ground D/ A CH 3
Analog Ground D/ A CH 2
LOOP I RTN D/A CH 2
Analog Ground D/ A CH 2
Analog Ground D/ A CH 1
LOOP I RTN D/A CH 1
Analog Ground D/ A CH 1
Analog Ground D/ A CH 0
LOOP I RTN D/A CH 0
Analog Ground D/ A CH 0

24 DAC V OUT CH 3
26 LOOP I lOUT CH 3
28 LOOP V EXC CH 3
30 DAC V OUT CH 2
32 LOOP lOUT CH 2
34 LOOP V EXC CH 2
36 DAC V OUT CH 1
38 LOOP lOUT CH 1
40 LOOP V EXC CH 1
42 DAC V OUT CH 0
44 LOOP lOUT CH 0
46 LOOP V EXC CH 0
48
50
NOTE: The Analog Ground lines for the D/A channels are
not connected to each other or to the MULTIBUS ground.

DVM + INPUT
DVM

~

INPUT

POT

DACO
TP2

DAC 1
TP5

DAC2
TP8

DAC3
TPII

TP3
R2

TP6
R26

TP9
R70

TP12
R94

Adjust the potentiometer for a reading of ~ 2.500 volts if the
DAC is to be configured for the ±5 Volt range. Otherwise,
adjust the pot for a reading of ~ 3.333 Volts.
3. Monitor the D/A output to be calibrated with the DVM. If
calibrating for 4-20 mA output range, use a 250 Ohm .1 %
loop resistor to measure the voltage drop across the resistor.
Use the Diagnostic Test Program Calibration Test to enter
the ~ full-scale hexidecimal data for the D/A channel under
test. This data would be 0000 hexidecimal for binary coding,
or 8,000 hexidecimal for 2's complement coding. Adjust the
proper Zero (Offset) pot for the correct reading, as shown
below.

ZERO OR OFFSET ADJUSTMENT POTENTIOMETERS
CHANNEL

POT

DACO
DAC 1
DAC2
DAC3

R3
R27
R71
R95

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

III
11-89

ST-703
DAC - FULL-SCALE READINGS

GAIN ADJUSTMENT POTENTIOMETERS

RANGE

READING

CHANNEL

POT

o to +5 V

0.0000 V
0.0000 V
- 5.0000V
-10.0000 V
1.0000 V

DACO
DAC 1
DAC2
DAC3

R4
R28
R72
R96

Oto+10V
±5V
±10V
4-20mA

4. Monitor the D/Aoutput to be calibrated with the DVM. Use
the Diagnostic Test Program Calibration Test to enter the
+full-scale hexidecimal data for the D/A channel under
test. This data would be FFFF hexidecimal for binary coding, or 7FFF hexidecimal for 2's complement coding.
Adjust the proper GAIN pot for the correct reading, as
shown below.

DAC + FULL-SCALE READINGS
RANGE

READING

Oto +5 V
Oto+10V
±5V
±10V
4 - 20 mA

+4.9988 V
+9.9976 V
+4.9976 V
+9.9951 V
+4.9990 V

SinaTrac ™ D/A and Current Loop Boards
for SBC·80 and MULTIBUS® Microcomputers

SinaTrac ™ST·716
FEATURES
• 4 or 8 D/A Channels, 16-bit resolution
• Compatible with both 8- and 16-bit CPU's (8- or
16-bit data transfer)
• Accurate to 0.005% of full-scale reading
• Complete hardware and software compatibility with
MULTI BUS and iSBC-Series microcomputers
• 20-Bit addressing
• Memory-mapped, with User-Selectable Base
Address
• Three user-selectable output ranges available: ± 5V
dc, and 0_ +10V dc, ±10V dc
• Selectable Transfer Acknowledge Delay (XACK/);
ensures compatibility with different memory speeds

SinaTrac™ ST·728
FEATURES
• 4 or 8 D/A channels, 12-bit resolution
• Compatible with both 8- and 16-bit CPU's (8- or
16-bit data transfer)
• Accurate to .050/0 of full-scale reading
• Complete hardware and software compatibility with
MULTIBUS and iSBC-Series microcomputers
• Memory-mapped, with user-selectable Base
Address, 16-, 20- or 24-bit addressing
• Three user-selectable input data codes: Straight
Binary, Offset Binary, or Two's Complement
• Five user-selectable output ranges available: ± 5V
dc, ±10V dc, 0 _ +10V dc, 0_ +10V dc, and
4-20 mA current loop, individually selected for each
channel
• Selectable Transfer Acknowledge Delay (XACK/);
ensures compatibility with different memory speeds

11-90

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

ST-705 Analog Input
8-Channel ASCII Serial
Single Board Subsystem

FEATURES
• 8 dlfferenUal AID channels using the SDA8-8 mlcroaystem
• RS-232-C or 20mA serial Isolated loop
• Includes Input condlUonlng PC board pads
• Includes direct thermocouple measurement with coldjuncUon temperature sensor and compensation amplifier
• Local TTL one-shot scan atart trigger from pushbutton or
contact closure
• DlrecUy connects to Datal's APP-20 and 48 miniature
serial thermal panel printers
• Selectable gain lnatrumentatlon amplifier board pads and

trim pot.
(Refer to the SDA8-8 product literature for full funcUonal
deacrlpUon of the SDA8-8 mlcroaystem).

BLOCK DIAGRAM

USERS HOST
COMPUTER OR
lERMINAL

DETACHABLE
SCREW-lERMINAL
SIGNAL INPUT
CONNECTOR. P3

PIN 36

AC
POWER

/

PIN 1

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DASHED LINES ARE WIRE-WRAP
POST/BEAG PLUGS

NC-CAR. DETECT 8

ARROWS SHOW
UNCHANGING SIGNAL.
FLOW DIRECTION. OMITIED
ARROWS MEAN THAT FLOW
IS EITHER DIRECTION AS
WIRED.

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15

3
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SEE C·12301
FOR
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12

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11-94

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E72

E71

-LOOP OUT

t---®

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ST-705
RS-232-C SERIAL DATA INTERFACE
The serial data connections shown describe interface to
three common RS-232-C devices: most terminals, computer serial ports and modems. There are several basic
rules to properly interface to RS-232-C devices.
They are:
(1) One end must be the "modem" (DCE device) and the
other must be the "terminal" (DTE device). This has to
do with the direction of data transmission on pins 2 and
3 of the RS-232-C interface and not the function of the
actual devices.
Most modems are wired as DCE devices. Most terminals are DTE devices, as you would expect Many
computer serial ports are DTE but some are DCE. The
ST-705 may be jumpered either way. Do not let line

names confuse you. Instead, observe the direction of
signal flow shown by the arrows in the diagrams.
(2) Most RS-232-C devices require connection to the
important handshake signals shown. The ST-705 does
not use these handshakes but contains a mini "breakouf' function to accommodate correct connection of
these handshakes. Minimal RS-232-C connection to
ST-705 requires only pins 2, 3 and 7 between AC-isolated devices.
(3) The character coding, length and protocol between
both ends must agree. ST-705 ASCII usage is widely
accepted for terminals and computers. Modems are
transparent to coding conventions.
For further background, consult the EIA RS-232-C specification and other references on data communications.

WIRING TO MOST TERMINALS
AND COMPUTER SERIAL PORTS
HOST

ST·705
WIRED AS A MODEM

WIRED AS A TERMINAL

(DeE)

(OTE)

"'7

CHASSIS GROUND
TRANSMITTED OAT....

RECEIVED DATA
REQUEST TO SEND
CLEAR TO SEND

6 --f_ _---]..-..::DA::.;T"-AS=E:.:.T:::RE::.:AD::..:Y_ _ _ ___+_

I - - - 1
01

SIGNAL GROUND

1
, - -• - 1/
E77

_~~--~~DA=~::.;C::.;.:.:.RR='E::.:R=DETE==C:.:.T---1_
DATA TERMINAL READY

20

E78

25

•

20

.

13

....25

* User-installed optional jumper connections DTR-DSR (pins
20-6) and DTR-DCD (pins 20-8) may be required for many
terminals.

....25

The connections shown above will work for most terminals
and computer serial R5-232-C ports wired as a terminal
(Consult your computer technical documentation.)

WIRING TO MOST RS-232-C MODEMS

CHASSIS GROUND

EO'

., I

NO CONNECTION
0"1 OTHER
HANDSHAKES

SIGNAL GROUND

DISTANT

HOST OR
TERMINAL

ST-705
WIRED AS A TERMINAL
(OTE)

L

_ _ _ _ _ ..J

7LOCAL AUTo-ANSWER
MoDeM (DeE) USED
FORST-70s

* Many modems require RTS and DTR to be asserted This
may be jumpered as shown on the modem connector or on

the ST-705. The ST-705 does not require these handshake
signals.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194tTEL (508) 339-3000tTLX 174388/FAX (508) 339-6356

11-95

II

ST·705

CIRCUIT BOARD COMPONENT LOCATIONS

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DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339·3000ITLX 174388/FAX (508) 339-6356

91

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DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

11:~f

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ST-705
DETACHABLE ANALOG SIGNAL INPUT
CONNECTOR, P3
NOTE:
PfNS6,Q,12,

If;~~12~~~,
BE JUMPeRED

FOR

BLEGROUNOS

AID IN (SOAS PIN 25)
REF. OUT (SOAS PIN 24)

ANALOG GROUND

ST·705

HROUGH PADS,

MAYBe

C

CHANNEL 1

TED BY THE

RANY
1/0

NO CONNECTION

CONNECTIONS.

CHANNEL 2
NO CONNECTION

CHANNEL3

t

LO

r
LO

t'

co

NO CONNECTION

CHANNEL

41

HI
LO

T

NO

CONNECTION

1
CHANNELS

t

LO

NO CONNECTION
CHANNEL 6

tl

0
0
0
0
0
0
0

e
0
0
0
0
0

LO

0

NO CONNECTION
CHANNEL 7
NO CONNECTION

1"'

LO

CHANNEL B \ HI

r - - - -~~R.r~LNSMIT ~

OPTIONAL

TRIGGER

i _____

LO
TRIG. SWITCH IN CoIG.}

ANALOG GROUND

TRIG. SWITCH RETURN (DIG.)

0

0
0
0
0
0

1
2

:~
6
7
8

•

10

0
0
0
0

11

12

,.
13
15
16
17
18

0

"20

0

21
22

0

23
2'

e

25

0

27

e

2.

0

<:0
0
0
0
0

WIRING

SIDE

26

28

30

31
32
33
3'
35
36

~

BOARD

SIDE

POWERING THE ST-705X FROM MULTIBUS
As an alternate mounting method, users may install model
ST-705X in a low-cost MULTIBUS card cage. Although no
digital connections are made to MULTIBUS, +5V power
connections are standard MULTIBUS. Some computers
include + /-15Vdc power supplies at the standard P2 locations shown. If preferred, a separate isolated 5 and 15 volt
DC supply may be bussed along MULTIBUS to drive one or
more ST-705X's in multidrop.
(Caution: This is for the ST-705X only, which omits the AC
isolated power supply. USing DC power from a 1.1 ULTIBUS
host may no longer be isolated, causing safety, damage
and data error difficulties).

MULTIBUS
regulated
DC power

Close
jumpers

Power supplied
through

+5Vdc @ 500mA

E97-E98

P1 pins 3-6,
81-84

+15Vdc @ 50mA

E101-E102

P2 pins 23, 24

-15Vdc @ 50mA

E99-E100

P2 pins 25, 26

Power Return

E1 03-E1 04

P1 pins 1, 2, 11, 12
75,76,85,86
P2 pins1,2,21,22

DATEL,lnc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

11-99

•

ST-705
BAUD RATE SELECTION
SDA8-S PIN =

(B~~D)(B~~D)( B~~D)(B~~D)
\8 SEL

BAUD
RATE

SERIAL CHARACTER FORMATS RECEIVED

S2
DIPSWITCH =

75

~ SEL

1

\2 SEL

2

3

,; SEL.

START BIT DATA BITS
(LSB first)

4

1

0

0

1

150

1

0

0

0

300

0

1

1

1

600

0

1

1

0

1200

0

1

0

1

2400

0

1

0

0

4800

0

0

1

1

9600

0

0

1

0

ON ="0", OFF = "1"

PARITY BIT STOP Bit(s)

7

None

2

7

Odd,
Even,

VERY IMPORTANT
For CRrs, send ESCAPE first to cancel the NUL's and restore
LF.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-101

ST·705TYPICAL 20mA ISOLOOP MULTIDROP WIRING

---eST-705
STATION 1
(CHANNELS
~
1-8)
ALL OTHER CONNECTIONS
NOT USED

=SDAS-6PINS

HOST
TERMINAL
OR COMPUTER

P4
ISOLATED
20mA
SERIAL PORTS

OPEN DIP SWITCH 5-16

t~m~~ ~~~f..f~

-----7~

OPTO PORTS

UP TO SEVERAL
THOUSAND FEET IN
PROPER CONDITIONS

r-20mA="1"

; +

~
II
.---+----+---I--+--------''----+-t-

--'-1+

I--I~~~~~

I

1-- j---JV'~-;---:;:'I---.

~

18

I

25

I 10

11 I

I

I I

I

I I

I

USER-SUPPLIED
ISOLATED LOOP
SUPPlIES_
1. SELECT FOR
20mA"ON"
CURRENT
2. MAY USE A SINGLE
DC POWER
SUPPLY,
SEPARATE FROM
THE ST-705
SUPPLY

--J-' I
L _..J

ADDITIONAL ISOLATED
ST-70S STATIONS,
CHANNELS 9 AND UP

TYPICAL ST·705 MOUNTING
IN A NEMA HOUSING

11-102

DATEL, Inc_ 11 Cabot Boulevard, Mansfield, MA 02048·1194ITEL (508) 339-30001TLX 174388/FAX (508) 339-6356

SineTrac ST-711,ST-732
32 AID, 2 01 A Channel
Analog Boards for
MULTIBUS Microcomputers
FEATURES
• Model ST-711: 32S AID Channels, no D/A
Channels
• Model ST-732: 32S/16D AID Channels, Includes 2 D/A Channels plus current loop outputs

BOTH MODELS INCLUDE:
• Full mechanical, electrical, and pinout compatibility to Datel's iSBC711/732 Analog 110
Boards and Datel's ST-711RLY Board.
• Operates with all MUL TIBUS and iSBC-Series
compatible microcomputers using 16, 20 or 24bit addressing, 8-bit data transfer.
• Works directly from Datel's RMX-80 Analog 110
Driver operating software.
• Includes an 10-stage jumper-selected, program-gatable pacer start clock, 1 mS
to 1 sec., crystal-controlled.
• AID input accept up to 16 user-installed
shunts for 4-20 mA etc., current inputs.
• FET-Input differential amplifier accepts onboard resistor for fixed high gain up to Xl000
(10 mV full scale range).
• Includes Programmable Gain Amplifier (Xl, 2,
4, 8 gains).

GENERAL

DESCRIPTION

The Sine-Trac ST-711 and ST-732 AlD-D/A Analog Input!
Output systems extend Datel's SineTrac family concept of
slide-in peripheral boards for popular mini-and-microcomputers. The ST-711 and ST-732 interface to the growing
Datel's Single Board Computer (SBC) Series and other Multibus-compatible micro-computers. The iSBC has multiple
sources and has been proposed as an ANSI standard. The
ST-711/732 also interfaces to the 16-bit iSBC-86/12 from
Datel which also uses MULTIBUS, thus insuring present and
future product compatibility for the user.
Models ST-711 and ST-732 are second generation combination A/D-D/A peripheral board systems for the iSBC-80 only
boards and they feature functional, hardware and programming differences to the ST-800 by adding 2 D/A converters
plus current loop amplifiers (ST-732 only) without sacrificing
the high AlD channel density of 32 single-ended or 16 differential channels per board. Other important differences include memory-mapped interfacing (vs. conventional register transfer 1/0 for the ST-800), addition of a FET input
programmable differential amplifier (with optional high gain
operation), a jumper-programmed, 10-stage crystal Pacer
clock and complete pin-for-pin form, fit, and function identi-

ty to competitive iSBC-711/732 series A/D-D/A board systems. This last feature allows Datel's ST-7111732 to operate directly from Datel's RMX-80 Analog 1/0 Drivers (Realtime Multitasking Executive Software.).
Hardware differences include the change from an MDAS-16
data acquisition module on the ST-800 to a hybrid ADC-HS
combined AlD converter and Sample/Hold Amplifier on the
ST-711/732. Substantial addressing, register and DMA logic is saved on the ST-7111732, making room for the D/A's,
current amplifiers, and Pacer clock.

ORDERING GUIDE
ST-711

32 S/16D AlD, D/A

ST-732

32 S/16D AlD, 2 D/A Loops

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-103

ST-111, ST-132
INTRODUCTION

tors for 4-20 mA, 1-5 mA, 10-50 mA and other current input
ranges.

The ST-711 is a full analog input system only (use Model ST732 for DIA outputs) including either 32 single-ended AID input channels (standard) or 16 differential channels (jumper
change). The ST-711 includes the DCIDC Power Converter
to supply all on-board ±15 V dc requirements, Programmable Gain Amplifier (X1, 2, 4, 8 gains) with optional (added resistor) gain selection up to X100 (.1 OmV full scale range).
Also included is a 10-stage jumper-selected crystal Pacer
clock, selectable base memory address, jumper-selected
End of Conversion (EOC), End of Scan (EOS) and Pacer
Clock/External Start Interrupts (external TTL AID conversion starts are software-gatable). Up to 16 differential
channels contain pads to accept user-installed shunt resis-

For conversion control, the ST-711 includes on-board registers to store start and final AID channel address, status
bits, conversion modes and interrupt enables.
An AID Converter auto-increment mode, which is programselected, automatically advances the channel address after each conversion. Successive AID samples will continue until the program-selected last channel address is
reached.
The ST-732 is identical to the ST-711; both include two 12-

ST-111/132 COMPARISON TO ST-800
I

MODEL

HI-GAIN DIFF.
AMPL. & RANG·
AID CHANS EX PAN·
SION
AID THRUPUT RATE PROG. GAIN AMPL. ES

NO. AID
CHANS.

ST·711 32S/16D
(No O/A)

ST-732
(2 D/A's

Must use additional 711 23,000 Samples/sec
boards with different
base addresses. Indetinite expansion

"

"

Included Xl, 2, 4, 8

board.

Included, 10stage bin. devi-

base 16m

"

Loops Incl.

No

No

None

None

(DMAMode)

RC adj. oneshot start elk.
Set status bit
or interrupt

MODEL
ST·711
(No D/A)

ST-732
(No D/A)
ST·800
(No D/A)

DCIDC
POWERA

NOTES

INTERRUPTS

Included

Uses ADC·HS

End of conversion
End of Scan Pacer
elk. 2 of 3 may be
wired to INTAA, INTB
or 8 Multibus interrupts

Combined AID
Converter and
Sample/Hold.
Stores Start &
Final Chan.
Addr.

"
Included

"
Uses MDAS16 Data Acquisition Module

COMPATIBLE
COMPUTERS

OPERATING
SOFTWARE

IDENTICAL PIN·OUTS
REGISTER BITS TO
COMPET. MODELS

iSBC·80/0S
iSBC-80-10

RMX·80

iSBC-711

iSBC·732

iSBC-80-30

Analog I/O
Drivers
(Diagnostic

iSBC-80·20 (·4)

Supplied)

iSBC·80·20

"

Register Transefer Program
or interrupt 1/0

DIAGNOSTIC
TAPE PROGRAM
Includes program
listing in manual

DMA
No

iSBC-86/12 & Multibus
compatible omputers

"
EOC, EOS, Start

iSBC·80105

Clock. May be wired
to any of 8 Multibus
Interrupts

iSBC-80/10
iSBC·80/20
iSBC-80/30

"

"

"

iSBC·80/20 H)
iSBC-86/12 & Multibus
Compatible computers

11-104

INTERFACE
TYPE

Included, gata- Memoryble starts AID mapped 16
Cony.
reserved 10cations, any

2 Chans. Inc\. 4-20

"

"

35,000 Samples/sec.

None, use 732

EXTERNAL
START

CLOCK

der lmS to 1
sec, Stal or
jumper-select.
Starts AID

"

ST·800 165, BD, 32S Up to 256S/120 using
(No D/A) or l6D
ST-800ADX Boards

User-option, up to
X1000 (1 OmV FSR)

CURRENT LOOF
OUTPUTS

II

None
(Diagnostic
Supplied)

None

"
Includes program listing in manual

"
Yes, reQuires Datel'sDMA
controller
board

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ST-711, ST-732
bit hybrid DAC-HK D/A converters with input registers. Also
included with each D/A converter is a current loop output
amplifier with unipolar range of 4 to 20 mA, which is compatible with industrial process transceivers and is especially
suited to driving long cables in noisy, industrial applications.
DESCRIPTION
The AID section of the ST-711/732 used Datel's hybrid technology ADC-HI2B combined successive approximation
AID converter and Sample/Hold Amplifier. The ADC-HS features 5 Ilsec S/H acquisition time and 8 Ilsec AID conversion time and 12 bit binary resolution. System accuracy
varies from ±0.5% of FSR ±1/2 LSB (10V range) to ±.03%
FSR ±1/2 LSB (10 mV range), including noise, quantization,
nonlinearity and dynamic errors. The ST -711/732 employ
Datel's MX-1606 series fast CMOS multiplexers which incorporate ±35V overvoltage protection. Input impedance is
100 meg-ohms minimum (power on) with 30 pA typical input
bias current. Balanced inputs require 5 kilohms maximum
source impedance to maintain accuracy and throughput
rate.
All models include an FET input differential amplifier which is
wired as single-ended for the 32-channel models. This amplifier will accept a fixed resistor to increase the gain to 100,
making 10 millivolt full scale ranges practical. For differential inputs, the common mode noise rejection varies from
120 dB at dc with a gain of 8 to 60 Hz with a gain of 1000.
Sample/Hold aperature delay time is 100 nanoseconds,
maximum.
System temperature coefficients are ±25 ppm of FSRrC
(gain drift of gain = 1) and ±20 IlVoC (RTI) zero drift. Amplifier settling time is 8 microseconds (high level) and typically
110 microseconds (low level). Overall system throughput
rate for high level signals is 23,000 samples per second.
The standard AlD-D/A digital coding is offset binary (bipolar)
but jumpers may easily be changed to straight binary (unipolar) or 2's complement (bipolar). Standard AlD-D/A analog signal ranges are +10V full scale but may be jumper selected to ±5V, or +5V, or 10V unipolar.
D/A outputs include operational amplifiers for voltage outputs, giving very low output impedance (2/10's of an ohm) at
5 mA short circuit proof output current. D/A settling time is
4 IlS (Fs pk-pk change). Output temperature drift is ±50
ppm to FSR/oC. 4 to 20 mA current loop outputs accept a 15
to 30V dc voltage compliance with ±0.075% FSR accuracy
and ±50 ppm FSR/oC drift.

SPECIFICATIONS, MODELS ST·7111732
(Typical at 25°C, dynamic conditions, unless noted)
GENERAL
Configurations Available
Model ST·711
32S/16D AID Chans, No D/A Channels
Model ST·732
32S/16 AID Chans, 2 D/A Channels
ANALOG INPUTS
Number of Channels
32 single-ended or 16 differential
(Jumper-selected, 32S suplied standard)
Channel Expansion
May expand indenfinitely by using additional ST-711/732
boards with different base address. Expansion limited by
board slots and power.
Input Type
With impedance voltage input, non-isolated. Differential
inputs are balanced.
Current Inputs
Up to 16 differential voltage inputs may be converted to
differential current inputs with shunt resistors provided
and installed by the user. Pads on the board will accomodate 4-20 mA, 1-5 mA, 10-50 mA and other ranges. 4-20
mA ranges require 250-ohm, 1/4W ±1 % resistors, +100
ppm/oC max.
Input Overvoltage
±35V sustained (no damage)
Input Capacitance to Ground
5 pF - Off channels, 100 pF - On channels
Full Scale Input Ranges
±10V, ±5V ±2.5V, ±1.25V (supplied standard, selectable
by 2-bit programmable gain code). Board pads are etched
for the user to install a fixed gain resistor, providing down
to ±1 0 mV full scale range.
Programmable Gain Amplifier
Supplied, Xl, X2, X4, X8 gains (see ranges above). Fixed
high gain Xl000 optional (see above)
Input Impedance.
100 megohms min.,.differential or to ground (power on)
1.5 kilohms min. (power off)
Input Source Resistance
5K ohms max. (balanced)
1K ohms max. (unbalanced)
Input Bias Current
30 pA typ., 200 pA max.
Overall Accuracy at +25°C
(including 3-sigma noise and quantization error, dynamic
response errors, referred to input, after initial calibration)
GAIN
ACCURACY
Xl
±0.05% FSR ±1/2 LSB
X2
±O.07% FSR ±1/2 LSB
X4
±O.07% FSR ±112 LSB
X8
±O.07% FSR ±1/2 LSB
Xl00'
±O.I%FSR±I/2LSB
Xl 000'
±0.3% FSR ±1/2 LSB
'Requires rewiring diff. ampl. for fixed high gain

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356 11-105

ST-711, ST-732
Common Mode Voltage Range
Within ±12V of analog common (signal plus common
mode)
Common Mode Rejection
At Gain = 1
OHz
100dB
100 Hz
80 dB
1 KHZ
60 dB
At Gain = 8
oHz 120dB
100Hz 100dB
1 KHZ
80dB
At Gain = 1000 (Requires rewiring dill. ampl. for fixed
high gain)
60 Hz 100 dB
Nonlinearity ±1/2 LSB
Differential Nonlinearity ±1/2 LSB
Resolution 12 binary bits (1 part in 4096)
MUltiplexer Crosstalk From Off Channels
0.01% max.
Sample/Hold Switch Feed Through 0.01 % max.
Sample/Hold Aperture Time
100 nanoseconds, max.
System Temperature Coefficients
Gain
±25 ppm of FSRfOC (Gain X1)
±30 ppm of FSRfOC (Gain X2, 4, 8)
Zero
±20I1V/oC
A/D Conversion Period 20 microseconds
Amplifier Settling Time
(Input = ±FSR pk-pk step)
8 microseconds (HL)
110 microseconds (LL)
System Throughput Rate
(High Level Inputs)
23,000 samples/seconds
A/D Digital Outputs
Ollsset binary (bipolar) - Supplied standard
Two's complement (bipolar) {ReWired with jumpersl
by user
Straight Binary (unipolar)
Output Data Format
12 bit binary group compatible to SBC-Series computers. The AID Bit 1 (MSB) may be inverted by jumper to
2's complement coding.

J

ANALOG OUTPUTS (ST-732 only)
VOLTAGE OUTPUTS
Number of Channels
2 non-isolated
Full Scale voltage Output Ranges
Jumpers may be rewired
o to +5V
by the user or by Oatel
Oto +10V
in OEM quantities
-5 to +5V
-10to +10V
(Supplied Standard)

11-106

Digital Input Coding
Jumpers may be
rewired by the
user or by Oatel
in OEM quantities
Offset Binary (Supplied standard)
Output Impedance 200 milliohms
Output Current ±5 mA, short circuit proof to ground
Slew Rate 1OV/I1S (with no Ext. Cap. Load)
SettlingTime
4 microseconds to within ±1/2 LSB of final value
Accuracy at +25°C ±50 ppm of FSRrC
Straight binary
2's Complement

CURRENT LOOP OUTPUTS
Full Scale Current Output Range
4 to 20 mA, unipolar. (May be rewired to other ranges
by the user.)
Current Loop Load Resistance 0 to 500 ohms
Current Loop Voltage Compliance
18 to 30V dc, unipolar, provided by the user
Accuracy at +25°C ±50 ppm of FSRrC
PHYSICAL
Outline Dimensions
12W X 6.750 X 0.5H inches·
(305 X 171 X 13 mm)
Pin-far-pin and card guide compatible to the Multibus
SBC-Series computers
Weight 22 ounces (0.6 kg)
Operating Temperature Range 0 to +55°C
Storage Temperature Range -25°C to +S5°C
Relative Humidity 10% to 90%, non-condensing
Altitude 0 to 15,000 feet (4600 m)
POWER CONSUMPTION
+5V dc ±5% @ 2.5 Amps. max
An on-board DC/DC Power Converter operated from +5V,
is provided to supply regulated ±15V for linear circuits.
Programming and Architecture Type of Interface
Memory-mapped interface
The ST-711/732 appears to the CPU as 16 consecutive
memory locations with 4 unused locations
Compatibility
Pin-far-pin and card guide compatible to the Multibus,
SBC-Series computers
Compatible Software
RMX-80 Analog I/O Drivers
ASM-SO 80S0 Assembly Language
Compatible Computers:
iSBC-80/10
iSBC-80/05
iSBC-80/20
iSBC-80/20 (-4)
iSBC-80/30
iSBC-86/12
Data Transfer - 8 bits 00/-07/
'Cards may be stacked adjacent if standard 0.60" spacing cages are used.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ST-711, ST-732
M!:MORY
N~lfl

ADQI'II:SSASSIGNMENT~

Addr,

(All addre$ses in hex)
Datel
SuppJied_ CQ.mmandF'ur!(;tio_n

M+O
M+O
M+1

00F700
00F700
00F701

Write
Read
Write

M+1

00F701

Read

M+2

00F702

Write

M+3
M+4
M+5

Write
Read
Read

M+8

00F703
00F704
00F705
00F708

M+9

00F709

Write

M+A

00F70A

Write

M+B

00F70B

Write

CA::F

00F70C/F&
00F706/7

Load Command Register
Read Status Register
Load RGA and Ch. Addr.
Register
Read PGA and Ch. Addr.
Register
Load Last Chan. Addr,
Register
Clear Interrupts
Read AID Data LO Byte
Read AID Data HI Byte
DACo LO ByteA:: Hid,
Reg.
DACo HI ByteA:: DACo

Write

(HRA::DACo)
DAC1 LO ByteA:: Hid.
Reg.
DAC 1 HI ByteA:: DAC 1
(HRA::DAC 1)
Don't Use

- - - - - - - - - - - - - - - - - - - - - - - - ----

M must be on 16-byte boundaries (A2/-A01

= 0)

CLEAR INTERRUPTS (WRITE 00F703)

Transfer Acknowledge Delay

Bits

The ST-711/732 responds with a Transfer Acknowledge
(XACK) with any Read or Write Command. The XACK may
be delayed to suit different processors. 16 delay steps are
jumper-selected from 50 nS to 1.5 IlS. Standard units are
set to 50 nS.

7,6

5
4
3
2,1, 0

Function
Not Used

o = Clear EOC Interrupt
o = Clear EOS Interrupt
o = Clear Pacer Clk. Interrupt
Not Used

Pacer Clock
Adjustable time-base consisting of a 10-stage binary divider
capable of starting AID conversions in the External Trigger
Mode. Time-base periods are jumper-selected and the oscillator may be either crystal or RC controlled. The standard
range is 97 IlS to 1 second.

Interrupts
2 of 3 possible interrupts may be jumper-selected to one or
both (INTA and INTB) interrupt lines. The interrupts are
EOC, EOS and Pacer Clock. They are factory-jumpered as:
INT A - EOS, INT B - EOC. Additionally, any of the 8 Multibus interrupts may be wired to any combination of the EOC,
EOS Pacer Interrupts.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356 11-107

ST-711, ST-732
AID CONTROL ADDRESSES

DIA COMMANDS

LOAD COMMAND REGISTER (WRITE I2II21F7121121)

LOAD HOLD REGISTER with DAC LO Byte DIA
(Writel2ll2lF71218 DACO, Write I2II21F7I21A-DAC1)

Bits

Function

7
6

Not Used
Not Used
1 = Enable End of Convert (EOC) Interrupt
1 = Enable End of Scan (EOS) Interrupt
0 = Clear Board Busy Status
1 = Enable External Trigger
1 = Enable Automatic Ch. Addr. Increment
1 = Enable AID Conversion

Bits

5
4
3
2
1

o

Function
------~-

7
6

5
4
3,2,1,0

- - - -

DAC Bit 9
DAC Bit 10
DAC Bit 11
DAC Bit 12 (LSB)
Zeros

READ STATUS REGISTER (READ I2II21F7121121)

LOAD HI BYTE TO DACj Load Hold Reg. to DAC
(Write I2I121F71219 DACO, WriteI2lI2lF7I21B-DAC1)
Enable DAC Input Register Strobe

Bits

Bits

Function

Function'
-----

1 = AID Conversion Done
1 = Scan Done
1 = EOC Interrupt Enabled
1 = EOS Interrupt Enabled
1 = Board is Busy
1 = External Trigger Enabled
1 = Auto-increment Enabled
1 = AID Conversion Enabled

7
6

5
4
3
2
1

o

6

5
4
3
2
1
0

READILOAD PGA DNA START CHAN. ADDR. AID
(READ WRITE I2II21F71211)
Bits

---

---

DAC Bit 1 (MSB)
DAC Bit 2
DAC Bit 3
DAC Bit 4
DAC Bit 5
DAC Bit6
DAC Bit 7
DAC Bit 8

7

•A/D-D/A convention is to label the converter's Most Significant Bit as Number 1 (MSB). (Note that D/A addressing is
mapped continuous to AID addressing).

Function
--------------~

5

00 = Gain
01 = Gain
10 = Gain
11 = Gain
Not Used

7,6

4

1 = 24

3

1 =23

2

1=22

----

Xl
X2
X4
X8

1=21

AID DATA ADDRESSES
READ AID DATA HI BYTE (Read I2II21F7I21S)
Bits

Function

7
6

ADC Bit 1 (MSB)
ADC Bit 2

o

ADC Bit8

Start Chan. Addr. Select
(1 of 32)

1=20
--~--------

LOAD AID LAST CHANNEL ADDRESS (WRITE
I2II21F71212)
-- - -

---

Function

7,6,5

Not Used

4

1 =24

3

1=23

2

1=22
1 = 21

11-108

Bits

---

Bits

o

READ AID DATE LO BYTE (Read I2II21F71214)

7
6

5
4
3,2,1,0

Function
ADC Bit 9
ADC Bit 10
ADC Bit 11
ADC Bit 12 (LSB)
Not Used

Last Chan. Addr. Select
(1 of 32)

1 = 20

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

5T-711, 5T-732
INTERFACE CONNECTORS
Programmable

0 +10V
0 +5V
0 +2.5V
0 +1.25

0 +5V
0 +2.5V
0 + 1.25V
0 +675 mV

X1
X2
X4
XS

Low Level
Unipolar
Bipolar

Bipolar

Unipolar

Gain

±5V
±2.5V
±1.25V
±675mV

±10V
±5V
±2.5V
±1.25V

Upto±1V
Up to ±500mV
Up to ±200mV
Up to ±100mV

Upto +SO mV
Up to +40 mV
Upto +20 mV
Upto +10 mV

(Standard, Offset Binary)
A
Selected by on-board jumpers

Requires substitution by
user of fixed gain resistor
on the on-board differential
amplifier

Memory Base Address
The 16-location starting base address is factory set at
00F700 (hex) but may be reassigned on 16-byte
boundries (LSB = 0) by altering a supplied DIP jumper
plug. However, the supplied diagnostic program is preset to operate from base address 00F700H.

INTERFACE CONNECTORS
DESIG.

PIN SPACING

NO. OF
PINS

FUNCTION

CENTERS (IN)

MATING RIBBON
CONNECTORS

PI

SBe Multiabus
Bus Connector

86

0.156

P2

±1SV Aux. Power
(Bus)

60

0.1

Jl

2 D/A Analog
Outppul Channels

50

01

58-2076061

J2

1sl 80/165 AID Input Channels

50

01

58-2076061

J3

2nd 80/16S AID
Input Channels

50

01

58-2076061

DATA ACQUISITION COMPUTER

r---l
DISK

EXTERNAL
PROCESS BEING
MEASURED OR
CONTROLLED

~

I
I

CPU
MEMORY
~

PORTS

I

LAN

I

I
I
co~~t~RI
REMOTE

(VAX. IBM)

I

I

I

I

I

L ___ J

ST-711
ANALOG
INPUT
BOARD

TEMP.
PRESSURE

RPM
FLOW RATE
VOLTS.mV

w~
TERMINAL

SOFTWARE PROGRAM

PHYSICAL
PARAMETERS

TRANSDUCERS
& SENSORS

BUlLT BY USER

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356 11-109

en
-t
.....•

a

....
....

~
m

.r

en

:;9

49

~

~

f
.a.

R2

~

~
-'

~
m

•

~: :~ ...
47j.44

OACOINPUT
CODING SELECTION

~

n •• 758

~

~
~

<0

~
8l

54

01 A CONVERTER
U2 DAC 1
DAC-HK12BGC

1•• 90

•

89

ADCRANGE
SELECTION

49

••48

CONFIGURATION 40 41

Pl.

•

.TP2

\

113
•

111

•
112

•

•

AID OUTPUT
BINARVCODE

51
50 ••• 52

SELECTION --""::67

69
BASE ADDRESS
SELECT DIP

64

INTERRUPT
FUNCTION -

FACTORY _______ • •

59:i.B.Sl

58." 11-62A

AID CONVERTER
U8
ADCHS12BGC

•• 72

1

B

MULTIPLEXER
INPUT SELECTION

68

75A

34:32 36 30 33
35- r-,.A.rl.~.39

I

U4
MXl606

•

PACeR
CLOCK
RATE
/SELECTION

§
~

53 ••~

ACKNOWLEDGE
DELA V SELECTION

~

~

U3
MXl606

PGA'
OFFSET

O:~;ET ij ~ ij ij ~ ~ ij ij~~B

80 _~wm~

GAIN

""""""=.

73
• • 74A

~

-'

.=

~.74B) TRANSFER

<0

~

•

,
e21A

DACllNPUT
CODING SELECTION

r

0;

DACl
OUTPUT RANGE

I SELECTION

.19 /

16•• 5. 3.18
• • 820
17 l'

DAC HK12BGC

ij ij ij ij ij ij ij ~

21B 21C

22B•• ~.22C

R
16

01 A CONVERTER
U1 DAC 0

(\)

o

OF~FSET

R
13

"-.1OA
9A

2

~

»

DACO
OUTPUT RANGE
1.7____ SELECTION

4~:a: :X

s::

Ii
s::

8

••••

9B9C
10B\10C

N

DACl

DAC 1
GAIN

8

~

c:

49

49

DACO
OFFSET

-t
•
.....
Co.)

J3

J2

J1

~

SELECT
J,/MPERS

/

XAIIU31

~m

•o
S
o
:D
C

c:
-I

PLUG (ADROl
THRU ADR 131)

65".63

~......
....
....

PSI
BPM-15/150-D5

I
ASSV, 0-11861

96 •• 95
MULTIBUS
INTERRUPT
SELECTION ':::......

81~83 ~86

INSTALL U45
'---;;;;;;~~~~~~J.J
ANDRNl T O .
DECODE ADR 141
.110
THRU ADR 171
93

lOS •• 109

a:··~·~l··87

91.0092

59

PIN85

PINl

P1

P2

~

~

F

SineTrac ST-716
16-Bit D/A Board for MULTI BUS
ISBC-SO Microcomputers
FEATURES
• 4 or 8 DIA channels, 16-bit resolution
• Compatible with both 8- and 16-bit CPU's (8- or 16-bit
data transfer)
• Accurate to 0.005% of Full-Scale reading
• Complete hardware and software compatibility with
MULTI BUS and ISBC-Series microcomputers
• 24-bit addressing
• Memory-mapped, with user-selectable base address
• Three user-selectable output ranges available:
±5 V dc, 0 to +10 V dc, and ±10 V dc
• Selectable Transfer Acknowledge delay (XACK/)
ensures compatibility with different memory speeds

DATEL'S SmeTrac S7716 DIA BOARD PROVIDES END USERS AND OEM's WITH A MEANS OF PRODUCING HIGH RESO·
LUTiON ANALOG OUTPUTS FROM THEIR MULTIBUS AND ISBC MICROCOMPUTERS, WITH 16 BITS OF RESOLUTION,
THIS BOARD IS AN IDEAL CHOICE FOR PRECISION SERVO CONTROL AND SIMILAR APPLICATIONS.
GENERAL DESCRIPTION
The ST-716 provides 4 or 8 channels of digital-to-analog (O/A)
conversion with 16 bits of resolution. Overall accuracy is within
.OOS% of full scale reading. Voltage range outputs are jumperselectable to ensure the board's compatibility with popular
process control and test instrumentation.
Like other SineTrac products, the ST-716 is fully hardware and
software compatible with its host ISBC or MULTIBUS computer.
All necessary address decoders, logic controls, and data
receivers are built in. The user simply slides the ST-716 into an
Intel-compatible card cage and wires the analog outputs. The
ST-716 is then ready as a memory-mapped O/A peripheral. It is
addressed by the host computer as 16 consecutive memory
locations with a user-defined base address. This memorymapped format permits virtually unlimited O/A channel expansion by using multiple ST-716's, each with a different base
address.
A systems manual is shipped with each board, providing installation instructions, theory of operation, and engineering
drawings.
Figure 1 is a simplified block diagram of the ST-716, with the 8
O/A channel circuitry for Model ST-7160 shown within dashed
lines. The ST-716 is pin-compatible with OATEL:s ST-724, ST-728,
ISBC-724, and ISBC-728 analog output boards. The 4-channel
ST-716's are software-compatible with the ST-724's and ST-728's
while the 8-channel ST-716's are software-compatible with the
ST-728's.
Data inputs to the ST-716 are from the host computer's bus.
Input coding is offset binary.

the boards. Trim pots on the board permit recalibration of zero
(or offset) and range setting. The converter settles in 1S"S to
within±O.OOS% of FSR. Zero tempco is ±S ppm of FSR/oC,
and gain tempco is within ±20 ppm of FSR/oC.
The board's base address is factory set at OF710. However, the
user may relocate the board's address anywhere up to FFFFO
by rewiring a 20-pin DIP plug supplied with the board. The user
may also extend the addressing to a full 24 bits by soldering
jumpers into holes provided on the board adding four more bits.
This would extend the addressing capability to FFFFFO hex.
In order to make the ST-716 compatible with different speed
CPU and memory systems, a Transfer Acknowledge delay
(XACKlOelay) circuit is provided. The user enables 16 jumperselectable delays from .OS to 1.S microseconds.
The ST-716 is fully bus, card cage, and software compatible with
the MULTIBUS. The board is 12"Wx 6.7S"0 x O.S"H (30Sx 172
x 13 mm). Multiple ST-716 boards can mount in adjacent card
slots when used with a standard, .60" spacing Intel card cage.
The ST-716C and ST-7160 draw ali their power from the MULTIBUS +SV line.
An on-board dc-to-dc converter provides the ± 1SV to drive the
board analog output circuits. The St-716 weighs approximately
11.2 ounces (0,318 kg). It can operate over a temperature range
of 0 to +SsoC with relative humidity from 10 to 90% (noncondensing), and from 0 to 1S,000 feet (0 to 4600m) in altitude.
Refer to Figure 2 for information regarding the location of al'l
user-selectable jumpers for addressing, XACKlOelay, and output range selection.

Each channel uses a OATEL Model OAC-HP16B (or OACHP16B-1), a 16-bit hybrid device which offers linearity to
±0.003% of Full-Scale reading. The output of the converter is
monotonic to 14 bits between + 1Q°C and +40°C. Offset error
on each channel has been adjusted to zero prior to shipping

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356 11-111

ST-716

r---------------------------,
(USEDON716DONl.y)

r~

~ASE

16
~

/

ADDRESS

CHANNEl

DATA

SELECT

OECODER

TER

REGIS

L

AND

CHANNel
SELECT

lOGIC

1

""",.'---'1"""

DATA
REGIS-

DAC6

-B~.--------+:
'------.....
:

TER

OAC·

HP16B

J2
(USED ON

Sf.7160
ONLY)

I
1

~

"'1

IS-BIT

7l'.~=Ri:~:~:~!:R:Pl~r_J.~

..-'J.S,-'_"_CT---,I

P1

~ g:;~ J l

-<

~

RECEIVER

DATA

OAe 5

REGIS

DAC
HP16B

TER

a·BITDR

DATA
REGIS

TER

t--~~~:-~
8·BIT

DATA
RECEIVER

-'--~

I

(BPM 1')1220)

I

+15V

I

-15V

}

TO
ANALOG

-V

CIRCuiTS

DATA
AEGIS

TER

I
I

_ _ _ ~E~N~E_ _

2[

~

r---v

DAG 2
DAC
HP16B

.J

' - ----"..

'-

-BI-+---::

L_-_-_-_....J____ }.- - - - -

-

- -

-I~

fER

---------,
~

___

OAe 4
DAC
HP168

DATA
REGIS

-

± 15V
DC TO DC
CONVERTER

1
1
1

) ~

......

-B~.--------.:

' -____- - '

---v

DATA
AEGIS

TER

+15'1

f----J\
~

OAG 1
DAC
HP16B

-15V

.A
NOTE: THE ST-llse USES I DClDe CONVERTER,
THE ST·716D USES 2 oClDe CONVERTERS

DATA
REGIS

TER

~

---.I

DACO
DAC
HP168

M3
M3
M3

>

J1

_15'1
",15V

Figure 1. ST-716 Block Diagram
FUNCTIONAL SPECIFICATIONS
(Typical at 250 C, unless otherwise specified)
D/A ANALOG OUTPUT
Number of Channels
ST-716C .............. .4 D/A Channels with onboard dc-to-dc converter.
ST716D ............... 8 D/A channels with 2 onboard dc-to-dc converters.
Full Scale Output
Ranges ............... ±5V,Oto +10, ±10Vdc
Digital Input Coding. . .. Offset Binary
Output Impedance .... ' 50 Milliohms
Maximum Current Available on Voltage Outputs .. ± 5 mA
Data Register. . . . . . . . . . Reserves a block of 16 conMemory Mapping
secutive memory locations

11-112

PERFORMANCE
Accuracy at +2S·C

.. ±0.005% of FSR (includes
noise and nonlinearity)
.. 10V change, 26 "Sec. (to
Setting Time
0.005% FSR)
Power Supply Rejection .. ±0.002% FSR/%
Monotonicity . .
. . To 14 bits over +10·C to
+40°C temp Range
Zero Temperature Drift ... Within ±5 ppm of FSR/·C
(Unipolar Output Only)
.
Offset Temperature Drift .. ±8 ppm of FSR/oC
(Bipolar Output Only)
Gain Temperature Drift ... Within ±20 ppm of FSR/·C
POWER CONSUMPTION
(From MULTIBUS +5 V dc, no load)
ST-716C ................ 2.0 Amps, typical
ST-716D ................ 4.2 Amps, typical

DATEL,lnc. 11 Cabot Boulevard, Mansfield, MA 02048-1194fTEL (508) 339-3000fTLX 174388/FAX (508) 339-6356

ST·716
FUNCTIONAL SPECIFICATIONS (cont.)

also onto the selected DAC's input. Digital to-analog conversion then begins. Data transfer with a 16-bit CPU is somewhat
simpler. All 16 data bits are transmitted as a single word. Data
is loaded directly into the selected DAC, and a D/A conversion
takes place.

PHYSICAL
Outline Dimensions ..... 12.00"W x 6.75"0 x 0.50"H
(304,8 x 171,5 x 12,7 mm)
ST-716 boards may be installed adjacent to each
other in SBC card cages
with 0.60" spacing
Weight
.. 11.2 ounces (0,318 kg)
Operating Temperature
Range ................. 0 to +55°C
Relative Humidity
.... 10% to 95%, noncondensing
Altitude.
........ 0 to 15,000 ft.

Table 1. Data Formats for 8- or 16-Bit CPU's

SINGLE WORD, 16-BIT CPU
HIGH BYTE (8·BIT CPU)
BASE + 1,3,5,7,9,B,0, or F

LOW BYTE (8·BIT CPU)
BASE + 0, 2,4,6,8,A,C, or E

015014013012011 0100908

07 06 05 04 03 02 01 DO

i i i i i iii iiiiiiii

SELECTION OF 8-BIT OR 16-BIT CPU's
The ST-716 board automatically changes to a 16-bit format when
the BHENlline on the MULTIBUS goes to zero volts (pin 27 of
connector P1). A high input on BHEN/, consequently, sets the
ST-716 for the 8-bit format.

N

~-~
«
al «
OCfl 0

M

~

0

o~o 0

«
0

DATA FORMAT
The ST-716 requires 16 bits of digital data, input from the host
computer, for a single digital-to-analog (D/A) conversion. Table
1 indicates how 8-bit and 16-bit CPU's format this data.

«
«
0
0

"- co

"
«

'"

0

0

«
«
«
0 0
0

0
«
0

0

0

!;j:

~

«
0

, at the base
memory address) and are latched into a 4-bit register. The next
data byte (base address + 1) contains the 8 MSB bits, and initiates a conversion.
D/A conversion is accomplished by DATELS DAC-HK12BGC, a 12-bit
hybrid unit with an input storage register and linearity to within ± V2
LSB. The output of the converter is monotonic, having a differential nonlinearity of ±'/2 LSB maximum. Offset zero error on each
channel has been adjusted to zero prior to shipping the board; pots
on the board permit recalibration of zero or offset settings.

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-117

III

ST-724
Zero temperature coefficient (unipolar outputs only) forthe
converter is less than ±5 ppm/DC of Full Scale Reading.
Offset temperature coefficient (bipolar outputs only) is within ±10 ppm/DC of FSR. Maximum gain tempco measures
±20 ppm/DC of FSR. DAC settling time is 4 f.Lsec maximum
(to within Y:! LSB of value), and slew rate is 20V/f.Lsec.

base address anywhere up to FFF8 in the host computer's
memory by reconfiguring jumpers on the ST-724 board.

The voltage output ranges from the ST-724 board are jumper selectable and have an output impedance of 50 milliohms. Maximum available current on the voltage outputs is
±5mA. The ST-724 also provides voltage to current converters for each of its four D/A channels.

The overall size of the ST-724 is 12.0"W x 6.75"D x 0.5"H
(305 x 172 x 13 mm). Multiple ST-724 boards may be
installed in adjacent card slots if used in a standard (.60"
spacing) Intel card cage. The ST-724 weighs 18 ounces
(.51 kg). It should be operated in an ambient temperature
from 0 to +55 DC, with relative humidity from 10% to 95%
(non-condensing), and from 0 to 15,000 ft (0 to 4600m) in
altitude. The board may be stored at temperatures from
-25 DC to +85 DC. The ST-724 is powered from the host
computer bus's +5 Vdc supply, and draws 1.5A.

The current output option is jumper-selected by the user,
and requires a user-supplied external excitation source
(+18 to +30 Vdc).
The ST-724 is a memory-mapped device which occupies 8 consecutive memory locations. The starting (base) address is set
at the factory to F7¢8. However, the user may reposition this

The selectable Transfer Acknowledge DelayCircuit(XACK!
Delay) provides 16 delays from .05 to 1.5 f.Lsec which may
be jumper-programmed by the user.

ST-724
BLOCK DIAGRAM
4-Channel 0/A

EXT. LOOP
EXCITATION

~-MWTC

~
BASE +1

1\
ADR0TO'\
ADRF

v

BASE
ADDRESS
DECODER
AND
FUNCT.ION
SELECT
lOGIC

BASE +3
BASE +5
BASE +7
BASE +0 OR 20R40R6

l

CClK

'"

8::>

!!lo>

~
0

SELECTABLE
XACK
DELAY

INIT

",0>

::>u

1

XACK

"\

DACS

/

,DAC·

r----

~"OC

0

~

vi

~r

'::i'"
::;irl

....
~

4-BIT
REGISTER
LATCH

4lSB>
BITS

~

I
I
I
I

DAC0
OUT

:
I

EXT. LOOP

:

~'

~

EXCITATION I

~

~
/
v

DAC 2

VTO
I

DAC2
OUT

1\

D~TODJ)

DATA
RECEIVER

D~TOD7

SMSBBITS )

V

~
±15V
+5VDC

+15V

OCTO DC
CONVERTER
(BPM 15/150)

-15V

TO
ANALOG
CIRCUITS

J1

DAC1
OUT

~

15
~
iii

~
I

DAC1

..J

c;

::>0

p1

1-1\

~

/

DAC3

I
:
I
I
I
I
I
I
I
I

~
VTO
I

DAC3
OUT

7"

11-118

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ST-724
SPECIFICATIONS
Typical at +25°C, dynamic conditions, unless
otherwise specified
D/A ANALOG OUTPUT
Number of Channels . .4 D/A channels
Channel Expansion ... Indefin ite channel expansion
by separate, stand-alone
ST-724 boards, each with a
different base address;
limited byavailable card slots,
and power supply current.
Full Scale
0.",., R.ng~ ..... ± OOV ,".nd"'di }

C~:""")
Jumpers t.O

±5V 1OV
~+

~~~~~~~~~nges

~+5V

J.mpe,
Selectable

by User
4-20 mA
binary
(Current Loop)
Digital Input Coding ... Straight Binary }Jumper
Offset Binary
Selectable
(standard)
by User
2's Complement
Outputlmpedance .... 50 Milliohms
Maximum Current
Available on
Voltage Outputs .... ±5 mA @ ±10V short-circuitproof to ground
±10V. offset

ADDRESSING

Reserves a block of 8
memory locations, all successive to a jumper-selectable
memory base address

CURRENT LOOP EXTERNAL EXCITATION
VOLTAGE

+5Vdc ±5/% @ 1.5A from
computer bus (±15Vdc
supplied from on-board
DC/DC power converter.)

GENERAL

ORDERING GUIDE

UM-ST-n4

Outline Dimensions, ., 12.00"W x 6.75"0 x 0.50"H
(304,8 x 171, 5 x 12, 7 mm),
ST-724 boards may be
installed adjacent to each
other in SBC card cages,
Weight ......... , .. , .18 ounces (.510 kg)
Operating Temperature Range .. , , , , , ,0 to +55°C
Storage Temperature Range, , . , . , . , -25°C to +85°C
Relative Humidity, , .. 10% to 95%, non-condensing
Altitude, .. " .. , .. " ,0 to 15,000 ft (4600m)

+18V to +30VDC, regulated,
user-suppl ied.
(25 mA maximum!DAC)

Non-linearity ......... ±y,; LSB maximum
Differential
Non-linearity ....... ±y,; LSB maximum
Offset or Zero Error ... Adjustable to zero using pot.
Each channel individually
adjustable.

31·2076040

PHYSICAL

POWER
CONSUMPTION

PERFORMANCE

MODEL
ST·724

Zero Temperature
Drift .............. (Unipolar Output only)
Within ±5 ppm of FSR/oC '
Offset Temperature
Drift, , .. , , , , , , .. , . (Bipolar Output only)
Within ±10 ppm of FSR/oC
Gain Temperature
Drift. .. , , , ... , .... Within ±20 ppm of FSR 1°C
Settling Time, , , , . , , ,Maximum, 4 Ilsec to within
y,; LSB of final value
Slew Rate.,.""", ,20V/llsec
Power Supply
Rejection, , , , . , , , , ,54 dB to DC supply bus

Compatibility, , , , . , , ,Pin-for-pin, cardguide, and
program compatible with
Multibus and SBC-series
microcomputers.
A pin-for-pin replacement
for the SBC-724.
Connector ., .. , .. ,. Dual 25·pin PCB, 0,1 rr centers
~Use(s

external circuits

DESCRIPTION
4 Channel, Multibus·Compatible
D/A Board
Edge Connector, J1, Spare
(One Included with Board)
(PCB to solder tab)
ST-724 Manual
(One Included with Board)

For 8 D/A channels, use Model ST·728,

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-119

•

ST-724
LEAST SIGNIFICANT BYTE
05
04
03
02
01

INPUT DATA FORMAT

07

Since 12-bit D/A converters are used on the ST-724. and
since the Intel Multibus provides for only 8-bits of data per
memory word. two 8-bit bytes in two sequential memory
words are necessary for each 0/A conversion.

DAC DAC DAC DAC
BIT BIT BIT BIT
10
11
12
9
(lSB)

The lS Byte is loaded onto the board first and is stored in a
4-bit register until the MS Byte is loaded. Thus. the memory
location of the lS Byte is always the lower of the two locations used for a given channel. Conversion begins as soon
as the MS Byte is loaded; within 4 microseconds an analog
signal appears at the board's output.

06

X

X

X

DO

X

MOST SIGNIFICANT BYTE
DAC DAC DAC DAC DAC DAC DAC DAC
BIT BIT BIT BIT BIT BIT BIT
BIT
3
2
4
7
8
1
5
6
(MSB)
X = Don't care

REGISTERS
The memory address bit function assignments are as follows. For an explanation
of lSB and MSB Bytes. please see "Input
Data Format".

11-120

ST-724 REGISTER ASSIGNMENTS

MEMORY
ADDR.
M+{i!
M+1
M+2
M+3
M+4
M+5
M+6
M+7

FACTORY
ASSIGNED
MEM. ADDR.
F708
F7~9
F70A
F7!i1B
F70C
F7!i1D
F7!i1E
F7!i1F

FUNCTION
Output lSB Byte for DAC 0 (Channel 0)
Output MSB Byte for DAC !iI (Channel 0)
Output lSB Byte for DAC 1 (Channel 1)
Output MSB Byte for DAC 1 (Channel 1)
Output lSB Byte for DAC 2 (Channel 2)
Output MSB Byte for DAC 2 (Channel 2)
Output lSB Byte for DAC 3 (Channel 3)
Output MSB Byte for DAC 3 (Channel 3)

DATEl. Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339·3000ITLX 174388/FAX (508) 339-6356

ST-724
D/A CALIBRATION PROCEDURE
5. Enter character "0" to select Channel
CHANNEL-¢
HEX DATA

Calibration of the ST-724 should be performed every 90
days or whenever the Analog Output Range jumpers are
reconfigured. More frequent calibration may be indicated
in adverse operating conditions. The Diagnostic program
supplied with the ST-724 was written as part of the calibration procedure.

6. Making reference to the Calibration Table, enter the
hex code for the -Full Scale output voltage (or current), then enter a Carriage Return. Adjust the OFFSET
potentiometer, until the reading on the DVM corresponds to the -Full Scale reading from the table.

1. Set the board jumpers for the desired output range:
0....H5V, 0~+10V, 4~20 mA, ±5V, or ±10V. See "Output Range Selection" for details.
2. Connect a digital voltmeter (Fluke 8800A or equivalent)
to the outputs of Channel 0 (DAC 0). For voltage
ranges, measure between "V OUT" and "ANA RTN".
For current ranges the user must supply a precision
2500 or 5000 resistor; voltage measurements are then
made across this resistor (see Note 1, bottom of Calibration Table).
3. Using the Diagnostic program, select the "Calibration
Test", Call Key "C".

is (DAC 0)

7. Refer again to the Calibration Table, and enter the hex
code for + Full Scale voltage or current. Adjust the
GAIN potentiometer until the reading on the DVM is the
+ Full Scale voltage as indicated in the table.
8. Repeat steps 6 and 7.
9. Calibration for Channels 1, 2, and 3 (DAC's 1, 2 & 3)
is the same as for Channel 0.
10. The complete cal ibration may now be checked using
the Calibration Table. Any hex value on the table may
be entered followed by a carriage return. The corresponding analog output should appear on the DVM.

4. The teletypewriter will respond by printing out:
CALIBRATION TEST
CHANNELCALIBRATION TABLE

4-DIGIT HEX INPUT

ANALOG OUTPUT
BIPOLAR (OFFSET
BINARY OR 2'S
COMPLEMENT

UNIPOLAR (STRAIGHT BINARY)

4.9976V
4.9951V
4.9902V
4.9805V

9.9951V
9.9902V
9.9805V
9.9609V

STRAIGHT
OR OFFSET
BINARY NOSIGN
EXTENSION
FFF¢
FFE0
FFC¢
FF8(1

4.9844V
4.9687V
4.9375V
4.8750V

4.9609V
4.9219V
4.8437V
4.6875V

9.9219V
9.8437V
9.6875V
9.3750V

FF0¢
FE(l¢
FC(I(1
F80(l

7FrJ0
7E¢¢
7C(1(1
781616

9.5000V
9.0000V
8.0000V
6.0000V

4.7500V
4.5000V
4.0000V
3.0000V

4.3750V
3.7500V
2.5000V
O.OOOOV

8.7500V
7.5000V
5.0000V
O.OOOOV

FIt¢¢
E¢0¢
C¢0¢
81t¢¢

701616
60016
4000
0000

2.5000V
1.2500V
0.6250V
0.3125V

4.0000V
3.0000V
2.5000V
2.2500V

2.0000V
1.5000V
1.2500V
1.1250V

-2.5000V
-3.7500V
-4.3750V
-4.6875V

.... 5.0000V
-7.5000V
-8.7500V
-9.3750V

416016
2(l¢¢
1(I(I~
0816(1

C00¢
A000
90016
8800'

0.0781V
0.0391V
0.0196V
0.0098V

0.1563V
0.0781V
0.0391V
0.0196V

2.12S0V
2.0625V
2.0312V
2.0156V

1.0625V
1.0312V
1.0156V
1.0078V

-4.8437V
-4.9219V
-4.9609V
-4.9805V

-9.6875V
-9.8437V
-9.9219V
-9.9609V

1641616
1621616
¢l(l¢

8400
82(10
8100'
80816

0.0049V
0.0024V
0.0012V
O.OOOOV

0.0098V
0.0049V
0.0024V
O.OOOOV

2.0078V
2.0039V
2.0020V
2.0000V

1.0039V
1.0020V
1.001OV
1.0000V

-4.9902V
-4.9951V
-4.9976V
-5.0000V

-9.9805V
-9.9902V
-9.9951V
-10.0000V

!/l(l4¢
160216

VOLTAGE

4~20

mA CURRENT'

5000 LOAD
2500 LOAD
LOOPV+>18V LOOPV+>15V
9.9980V
4.9990V
9.9961V
4.9980V
9.9922V
4.9961V
9.9844V
4.9922V

~+5V

~10V

4.9988V
4.9976V
4.9951V
4.9902V

9.9976V
9.9951V
9.9902V
9.9805V

4.9805V
4.9609V
4.9219V
4.8437V

9.9609V
9.9219V
9.8437V
9.6875V

9.9687V
9.9375V
9.8750V
9.7500V

4.6875V
4.3750V
3.7500V
2.5000V

9.3750V
8.7500V
7.S000V
5.0000V

1.2500V
0.6250V
0.3125V
0.1563V

±5V

Note 1: Both the 2500 and the 5000 resistors (.1 %precision) provide 4 to 20
rnA output. The current Qutputcircuit is calibrated in terms of voltage
since most digital multimeters provide greater resolution and accuracy on voltage measurements than on current.
The voltages listed are those measured across a 2500 or a 5000
precision resistor, connected between "" RTN" and "lOUT" on any

±10V

¢~816

¢¢H~

160016

2'S
COMPLEMENT
WITH SIGN
EXTENSION
7FF¢
7FE¢
7FC0
7F8(1

804(1
802!/l
8(110
80160

DAC output. A user-supplied DC regulated voltage. v+ (+15V <
V + ,; + 30V for 2500 resistor. +18V < V + ,; + 30V for 5000
resistor; 25 rnA max) is required for current output and calibration,
and should be connected to "V + LOOP". The supply providing V+
should be grounded at "ANA RTN".

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-121

•

ST-724

BASE ADDRESS SELECTION
1. Select a base address, in hex, between ¢~fIlfll and FFF8.
2. Write it in squares below opposite" Base Address, Hex".
3. Convert the hex code to binary by writing 1's and O's
in the appropriate boxes below (opposite "Hex Bit
Weighting"). .
BASE
ADDRESS
HEX
HEX BIT
WEIGHTING

L

ADDRESS
BIT*
JUMPERS
IN FOR
"1", OUT
FOR BIT
"0"
.. For low on bit 3. remove 93 to 93

/

(~to

-

\..

F)
-

4. To set the base address, insert a jumper at each location
opposite a "1". Please note that to obtain a "low" ("0") on
bit 3, the jumper between 93 and 94 must be removed,
and a jumper between 94 and 95 must be added.

/

~

-L

(fIl to F)
-

\.

/

(¢to F)

5

4

3

89
to
90

91
to
92

93
to
94*

2

1

8

4

2

-

-

8

4

2

1

8

4

F

E

D

C

B

A

9

8

7

6

69
to
70

71
to
72

73
to
74

75
to
76

77
to
78

79
to
80

81
to
82

83
to
84

85
to
86

87
to
88

(fIl or 8)

-Z-S:

~

L

\.

-=-

--

1

8

2m:! ~ 94 to 95

BOARD LAYOUT

COMPONENT SIDE

J1

J3

J2

NOT USED

NOT USED
49
GAIN
DAq

OFFseT 9A lOA
DAC~
••

oLJ 03.~:.:~O
L1 •••••

11

49

OFFSET 21A 22A
DAel
••

GAIN
DAe 1

LI~

GAIN
DAC2

GAIN
DAC3

OFFSET 3:"A 34A
DAC2
••

OFFSET 45A 46A
DAC3
••

~,},:.:~~
~ ~27.i3~.:;: ~ ~3}4~.:::
~ •••••
LJ ~ ••••• LJ LJ ••••
23

t, ~: T,\ L;:'""'1"\ l:, ~:T

35

·47

_D_~_~_:_O

U_-,-__l_N_'

44 48
4_'_1___.__--,

·~------~----'----OUTPUT RANGE SELECTION

I
•••

\
• ••

495051

INPUT CODe SELECTION

525354

\• ••

555657

\• ••

58 59 60

61 63 65 67

••••
••••

62 64 66 68

t

TRANSFER
ACKNOWLEDGE

DELAY
SELECTION

69717375

77798183

85878991

• ••• •••• ••••
•••• •••• •••• •••

70727476

78808284

86889092

939495

t

BASE ADDRESS
SElECTION

P1

11-122

M'
DCIOC CONVERTER

P2

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ST-724

OUTPUT RANGE AND
INPUT CODING SELECTION
The ST-724's 4 D/A output channels may be set independently for any of four voltage ranges or a single current
output range. Full scale ranges of ±10V, ±5V, 0--;.+ 10V,
0--;.+5V, or 4--;.20 mA may be jumper-selected according
to the chart below. Input digital coding may be offset binary,
2's complement, or straight binary on any channel. Again,
refer to the chart below for details.

OUTPUT RANGE SELECTION JUMPERS
RANGE
± 10V
(STANDARD)
±5V

The ST-724 board is normally shipped with jumpers set for
the ±10Voutput, and an offset binary input coding. Please
note that whenever there is a change in output range on a
given channel, that channel should be recalibrated.

010 +10V

INPUT CODE SELECTION JUMPERS
DAC(6
DAC1
DAC2

410 20 mA
CURRENT LOOP

CODE
UNIPOLAR
OR
OFFSET BINARY
(STANDARD)
2'S
COMPLEMENT

DAC3

49-50

52-53

55-56

58-59

50-51

53-54

56-57

59-60

The ST-724 board generates a Transfer Acknowledge
(XACK/) signal in response to Write commands from the
host computer. It is sometimes desirable to delay this signal,
in order to match the XACK/ signal to the host computer
timing. A jumper selectable Transfer Acknowledge Delay
(XACK/ delay) ranging from 50 nanoseconds to 1.5 microseconds is available in the ST-724.
The accuracy of the XACK/ delay is dependent in part on the
duty cycle of the CCLK/ signal generated by the computershorter duty cycles result in greater accuracy. The delay
time is advanced on the leading edge of CCLK/; XACK/ is
generated on the trailing edge of CCLK/.
Please refer to the table below for jumper configurations
yielding different delay times.
XACK/ DELAY SELECTION
DELAY

I'sec

.

JUMPERS
-

-

61-62

-

-

63-64
63-64

61-62

61-62

61-62

61-62

61-62

61-62
-

61-62

3-5
6-7
3-5
6-8
3-4
6-8
1-2
3-4
6-8
9-10
11-12
9A-10A

DAC 1
15-17
18-19
15-17
18-20
15-16
18-20
13-14
15-16
18-20
21-22
23-24
21A-22A

DAC 2
27-29
30-31
27-29
30-32
27-28
30-32
25-26
27-28
30-32
33-34
35-36
33A-34A

DAC3
39-41
42-43
39-41
42-44
39-40
42-44
37-38
39-40
42-44
45-46
47-48
45A-46A

ANALOG OUTPUT CONNECTIONS

TRANSFER ACKNOWLEDGE
(XACK/) DELAY SELECTION

'0.05
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5

010 +5V

DAC~

63-64
63-64

63-64
63-64

63-64
63-64

-

-

65-66
65-66
65-66
65-66

-

-

67-68
67-68
67-68
67-68
67-68
67-68
67-68
67-68

-

65-66
65-66
65-66
65-66

-

J 1
ETCH SIDE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DAC3, VOUT
DAC3, lOUT
DAC 3, LOOP V + IN
DAC 2, VOUT
DAC 2, lOUT
DAC 2, LOOP V + IN
DAC 1, VOUT
DAC 1, lOUT
DAC 1, LOOP V + IN
DAC (6, VOUT
DAC~, lOUT
DAC rI, LOOP V + IN
POWER COMMON
-15 REF. VOLT. OUT'

PIN ii'S
1
2
3
4
6
5
7
8
9
10
11
12
13
14
15
16
17
18
19
20
22
21
23
24
25
26
27
28
30
29
31
32
33
34
35
36
37
38
39
40
42
41
44
43
45
46
47
48
50
49

COMPONENT SIDE
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
DAC3, I RTN
DAC 3, ANA RTN
NC
DAC 2, I RTN
DAC 2, ANA RTN
NC
DAC 1, I RTN
DAC 1, ANA RTN
NC
DAcfIl, I RTN
DAC ~, ANA RTN
POWER COMMON
+15 REF. VOLT. OUT'

"'Not Intended to power external circuitry; 1 mA max.

a

Factory supplied configuration.

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

11-123

SineTrac ST-728
Of A Board for MULTIBUS
Microcomputers

FEATURES
• 4 or 8 D/A channels, 12 bit resolution
• Compatible with both 8 and 16 bit CPU's (8 or
16 bit data transfer)
• 16, 20-, or 24-Bit addressing
• Accurate to 0.05% of Full Scale Reading
• Complete hardware and software compatibility
with MUL TIBUS and iSBC-Series microcomputers
• Memory-mapped, with user selectable Base
Address
• Three user-selectable input data codes:
Straight Binary, Offset Binary, or Two's Complement
• Five user-selectable output ranges: ±5V dc,
±10V dc, 0 to +5V dc, 0 to +1 OV dc, and 4-20
mA current loop, individually selected for each
channel
• Selectable Transfer Acknowledge Delay
(XACK/) - ensures compatibility with different
memory speeds
• ST-728A (4 D/A channels)
ST-728B (8 D/A channels)
ST-728C (4 D/A channels, DC-to·DC converter)
ST-728D (8 D/A channels, DC-to-DC converter)

APPLICATIONS
• Computer control of analog input chart recorders, process receivers, proportional controllers, actuators and displays
• Custom automatic test equipment, computer
simulators, modelling systems, pattern generators, multi-channel Waveform generators

INTRODUCTION
DATEL expands its range of MULTIBUS and SBe compatible analog output boards with the SineTrac ST-728. The ST728 provides 4 or 8 channels of digital to analog (D/A) conversion with 12 bits of resolution. Overall accuracy is within
±.05% of full scale reading. To ensure the board's compatibility with popular process receiver, control, and test instrumentation, four voltages ranges, and a 4-20 mA current loop
output are jumper selectable for each D/A channel.
Like other SineTrac products, the ST-728 is fully hardware
and software compatible with its host SBe or MUL TIBUS
computer. All necessary address decoders, logic controls,
and data receivers are built in. The user simply slides the
ST-728 into an Intel compatible card cage and wires the analog outputs. The ST-728 is then ready as a memorymapped D/A peripheral. It is addressed by the host com put-

11-124

Compatible with: iSBC-80 Series
iSBC-86 Series
er as 16 consecutive memory locations with a userlocatable base address. This memory-mapped format permits unlimited D/A channel expansion by using multiple ST728's, each with a different base address.
The ST-728 is pin compatible with the ST-724 and SBC-724
analog output boards (4 channel ST-728's are software
compatible with ST-724's; 8-channel ST-728's look like two
ST-724's). Unlike the ST-724, however, the ST-728 may be
used with both 8-and 16-bit microprocessors. The BHENI
line on the MULTIBUS sets the ST-728's address decoders
and data latches for compatibility with 8- or 16-bit computers.
A systems manual is shipped with each board, which provides a source listing of the Diagnostic as well as installation instructions, theory of operation, and engineering drawings.

GENERAL DESCRIPTION
Data inputs to the ST-728 are from the host computer's bus.
Input coding may be straight binary, offset binary, or two's
complement, and is selected by jumper plugs on the board.
The MULTIBUS BHEN/line is used to set the ST-728's address and data decoding for compatibility with 8 to 16 bit
CPU's. In the 8 bit mode, the twelve bits of data required for
D/A conversion are acquired in two bytes. The lower byte
contains the four lower data bits, and is loaded into a storage register for each D/A channel on the ST-728. The next
data byte contains the 8 higher bits. Upon converion, the 8
MSB's and the 4 stored bits are loaded simultaneously into
the DAC. In the 16-bit mode, all twelve data bits are transferred in a single byte.
Prior to being converted, the digital data is held in a storage
register. Enabling the register loads the data into the digital
to analog converter (DAC), and a conversion proceeds.
Each channel uses a 12-bit monolithic D/A device which of-

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194rrEL (508) 339-3000rrLX 174388/FAX (508) 339-6356

5T-728
board's base address is factory set at OF700 1 . However,
the user may relocate his address anywhere up to
FFFFF0H.

fers linearity to ±1!2 L8B of full scale reading. The output of
the converter is monotonic, having a differential nonlinearity
of ±1/2 L8B maximum. Offset error on each channel has
been adjusted to zero prior to shipping the boards. Trim
pots on the board permit recalibration of zero (or offset) and
range settings using the supplied Diagnostic program. The
converter settles in 400 n8 to within 1/2 L8B of it final value.
Zero tempeo is ±2 ppm of F8RfOC, and gain tempco is within
±10 ppm of F8RfOC.

In order to make the 8T-728 compatible with different speed
CPU and memory systems, a Transfer Acknowledge Delay
(XACKIDelay) circuit is provided. 16 delays from 0.05 to 1.5
).18 are jumper-selectable by the user.
The 8T-728 is fully bus, card cage, and software compatible
with the MULTIBU8 and with Intel RMX software. The board
is 12.0"W x 6.75"0 x 0.5"H (305 x 172 x 13 mm). Multiple
8T-728 boards may be mounted in adjacent card slots when
used with a standard, 0.60" spacing Intel card cage.

The output of each DAC is fed to its own I-to-V conversion
amplifier. A total of 4 voltage output ranges may be jumperselected by the user: ±5V and ±1 OV bipolar; and 0 to +5V or
o to +1 OV single-ended. In addition, a V to I converter circuit is included for each D/A output channel. 4-20 mA output, usable with an output load from 0 to 500 r.l, is also jumper-selectable.

The 8T-728C draws all its power from the MULTIBU8 +5V
line. An on-board DC-to-DC converter provides the ±15 to
drive the board's analog output circuits. The ST-728A and
8T-728B do not have a DC-to-DC converter. They are powered from the +5V MULTIBU8 line, and an external ±15V
supply.

The current output requires an external excitation source a + 18V to + 30V dc regulated supply, capable of 25 mA per
D/A channel, must be provided. Voltage and current output
ranges on the 8T-728 are selected independently for each
channel, permitting a mix of different voltage or current outputs on a single board.

The 8T-728 weighs approximately 11.2 ounces (0,318 kg).
It can operate over a temperature range of 0 to +55°C with
relative humidity from 10 to 90% (non-condensing), and
from 0 to 15,000 feet (0 to 4600 m) in altitude.

The 8T -728 is a memory-mapped peripheral occupying 16
consecutive locations in the host computer's memory. The

INPUT DATA FORMAT AND REGISTER ASSIGNMENTS
DATA FORMAT

SELECTION OF 8-BIT OR 16-BIT CPU'S

The 8T -728 requires 12 bits of digital data, input from the
host computer for single digital to analog (D/A) conversion.
The chart below indicates how 8-bit and 16-bit CPU's format
this data.

The 8T -728 board automatically changes to a 16-bit format
when the BHEN/line on the MULTIBUS goes to zero volts
(pin 27 of the connector P1). A high input on BHEN/, consequently, sets the 8T-728 for the 8-bit format.

ST-728 REGISTER ASSIGNMENTS
The following chart details the memory address assignments of the 16 memory locations the 8T -728 occupies.
Please note that when the 8T-728 is used with 16-bit CPU's,
every other (even-numbered) address location is used.

ST-728 REGISTER ASSIGNMENTS
"--"---,---,-----

""--"-"--~--:

MEMORY
ADDRESS
(B-bit CPU's)

FUNCTION

BASE +0

WRITE

Output LSB Byte for DAC 0 (Channel 0)

BASE +1

WAITE

Output MSB Byte for DAC 0 (Channel 0)

I

REGISTER ASSIGNMENT

MEMORY
,
ADDRESS
(16-bit CPU's)
BASE +0

WRITE

Output LSB Byte for DAC 1 (Channell)

I

WRITE

Output MSB Byte for DAC 1 (Channell)

'

WRIT. E

BASE +2

Note that 8-bit CPU's must transit the 12 data bits in two
bytes. The low byte contains the four least significant data
bits: these are stored in a data register on the 8T-728. The
high byte contains the remaining 8 data bits. When the high
byte is transmitted, all twelve bits of data - the 4 L8B's
stored in a register and the 8 M8B's coming from the host
computer - are loaded into the input of the selected DAC on
the 8T-728, and D/A conversion proceeds. Data transfer
with a 16-bit CPU is somewhat simpler. All twelve data bits
are transmitted in a single word. Data is loaded directly into
the selected DAC, and a D/A conversion takes place.

BASE +3
BASE +4
BASE +5

1-

BASE +6
BASE +7

1-

~

WRI!E

-

WRITE

+
I

T

Output LSB Byte for DAC 2 (Channel

I

BASE +2

2)~'

BASE +4

Output MSB Byte for DAC 2 (Channel 2)

-- --- ---..- - - - - - - -

i

--------I

Output LSB Byte for DAC 3 (Channel 3)

I
__ WRITE_

BASE +6
Outpu~ MSB _~yte for _DAC ~ (Channel 3_)- - - - -

BASE +8

WRITE

Output LSB Byte for DAC 4 (Channel 4)

i

BASE +9

WRITE

Output MSB Byte for OAC 4 (Channel 4)

I

BASE +A

WRITE

Output LSB Byte for DAC 5 (Channel 5)

I'

BASE +8

WRITE

!

_I

BASE +8

BASE +A

Output MSB Byte for DAC 5 (Channel 5)

DATEl, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194iTEL (508) 339-3000iTLX 174388/FAX (508) 339-6356

11-125

1

lI'i,

5T-728
FUNCTIONAL SPECIFICATIONS

PHYSICAL

(Typical at +25°C, dynamic conditions, unless otherwise
specified)

Outline Dimensions
12.00"W x 6.75"D x 0.50"H (304,8 x 171,5 x 12,7 mm)
ST-728 boards may be installed adjacent to each other in
SBC card cages with 0.60" spacing
Weight (ST·728B) 11.2 ounces (0,318 kg)
Operating Temperature Range 0 to + 55°C
Relative Humidity 10% to 95%, non-condensing
Altitude 0 to 15,000 ft

D/A ANALOG OUTPUT
Number of Channels
ST-728A, C - 4 D/A Channels
ST-728B, D - 8 D/A Channels
Indefinite channel expansion by separate, stand-alone ST728 boards, each with a different base address; limited by
available card slots, and power supply current.
Full Scale Output Ranges
±10V (standard)
±5V
oto +10V
Oto+5V
4-20 mA
Digital Input Coding
Straight Binary
Offset Binary (Standard)
2's Complement

Jumper
Selectable
by User for
each channel

POWER CONSUMPTION
All ST -728 models use some +5V power from the MULTIBUS. The ST-728C (4 channels) has an on-board DC-DC
converter, so that all board power comes from the +5V line
on the MULTIBUS. The ST-728A (4 channels no DC-to-DC)
and ST-728B (8 channels, no DC-to-DC) require external
±15V supplies, input to the board via connector P2. The
chart below summarizes the ST-728 board power requirements.

JumperSelectable
by User in
4-channel
groups

Output Impedance
50 Milliohms
Maximum Current Available on Voltage Outputs
±5 mA @ ±1 OV short-circuit-proof to ground
Current Loop Load Resistance
o to 500n
Current Loop External Excitation Voltage
+ 18V to +30V dc, regulated, user-supplied (25 mNDAC,
max.)

r---

,

ST.728A!
Except as noted, current
readings are:
typical, (with output load)
typical, without output load

I

from
+5V MULTIBUS

(P2)

7SOmA

140mA

70mA

(150mA)

(90mA)

110mA

275 mA

(130mA)

(300 mAl

i

l

.-

(P2)

-I

ST' 728B

1000 rnA

ST·728C

1500 mAmax.

NlA

NIA

5T-7280

2500 rnA max.

NlA

NlA

-

I

ADDRESSING
Reserves a block of 16 consecutive memory locations.
Base address may be located by jumper selection anywhere
in the host computer's memory on 16-byte boundaries.

PERFORMANCE
Accuracy at +25°C
±0.05% of FSR (includes noise and nonlinearity)
Linearity Error, max. ±1/2 LSB
Linearity Error, O°C to +70°C ±1 LSB
Differential Linearity Error ±1/2 LSB
Monotonicity
Monotonic over O°C to +70°C temp. range
Zero Temperature Drift
(Unipolar Output only) Within ±2 ppm of FSRloC
Offset Temperature Drift
(Bipolar Output only) Within ±5 ppm of FSRfOC

GENERAL
Bus Compatibility
Pin-for-pin, card guide, and program compatible with MULTIBUS and SBC-series microcomputers.

CPU Compatibility
May be used with either 8-bit or 16-bit microprocessors.

Gain Temperature Drift
Within ±10 ppm of FSR/oC
Settling Time (Board)
5 IlS to within 112 LSB of final value

11-126

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048·1194rrEL (508) 339·3000rrLX 174388/FAX (508) 339·6356

ST-728
ANALOG OUTPUT CONNECTIONS
J1 (DAC'S 0, 1, 2, 3)
r--------------------------

WIRING SIDE
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
NO CONNECTION
DAC 3, V OUT
DAC 3, I RTN
DAC 3, LOOP V+
DAC 2, V OUT
DAC 2, lOUT
DAC 2, LOOP V+
DAC1,VOUT
DAC 1, lOUT
DAC 1, LOOP V+
DAC 0, V OUT
DAC 0, lOUT
DAC 0, LOOP V+

PIN
2
4
6
8
10
12 i
14'
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46

SIDE,
1
NO CONNECTION
3
NO CONNECTION
5
NO CONNECTION
7 ' DAC 3, REF RTN
9 I DAC 3, EXT REF
11
DAC 2, REF RTN
13. DAC 2, EXT REF
15
DAC 1, REF RTN
17
DAC 1, EXT REF
19
DAC 0, REF RTN
21
DAC 0, EXT REF
23
DAC 3, ANA RTN
25
DAC 3, I RTN
27
GND
29
DAC 2, ANA RTN
31
DAC 2, I RTN
33
GND
35DAC1,ANARTN
37
DAC 1, I RTN
39
GND
41
DAC 0, ANA RTN
43
DAC 0, I RTN
45
GND
I-

I

I

I'

~~~i~~~~~~N _ ~~_L:~~~~~~~~~_ J
NOTE:

I

1

I

J2 (DAC'S 4, 5, 6, 7) 1
-- ---- ---- ---T--WIRING SIDE
PIN #'S
COMPONENT SIDE
NO CONNECTION I
2
1
NO CONNECTION
NO CONNECTION
4
3
NO CONNECTION
NO CONNECTION
6
5
NO CONNECTION
NO CONNECTION
8
7
DAC 7, REF RTN
NO CONNECTION
10
9
DAC 7, EXT REF
NO CONNECTION
12
11
DAC 6, REF RTN
NO CONNECTION
14
13
DAC 6, EXT REF
NO CONNECTION
16
15
DAC 5, REF RTN
NO CONNECTION
18
17
DAC 5, EXT REF
NO CONNECTION
20
19
DAC 4, REF RTN
NO CONNECTION
22
21
DAC 4, EXT REF
DAC 7, V OUT
24
23
DAC 7, ANA RTN
DAC 7, lOUT
26
25
DAC 7, I RTN
DAC 7, LOOP V+
28
27
GND
DAC 6, V OUT
30
29
DAC 6, ANA RTN
DAC 6, lOUT
32
31
DAC 6, I RTN
DAC 6, LOOP V+
34
33
GND
DAC 5, V OUT
36
35
DAC 5, ANA RTN
DAC 5, lOUT
38
37
DAC 5, I RTN
DAC 5, LOOP V+
40
39
GND
DAC 4, V OUT
42
41
DAC 4, ANA RTN
DAC 4, lOUT
44
43
DAC 4, I RTN
DAC 4, LOOP V+
46
45
GND
POWER COMMON
~
47
POWER COMMON
L=~~Y_ POW§~_~ _ ~_O_49 _:I:15V POWE~ __ _
NOT E S : 1. J2 not used on 4 channel versions of ST-728
2. 49 & 50 are outputs; 1 mA max (for ref. only).

1. 49 & 50 are outputs; 1 mA max (for ref. only).

['''"

;-_.

~~."".

[A"A""
i
Y\ - :

EKTEANAI.

I

l.OIIIO

i

R~ 25011
OR1~1

~~~:~~flm?P
• fOR CALIBRATION

fN

ONLY

Y.WATT

,
:

II

! RTN

Jl

CONNECTOR

COf18V LOOP V+>15V.

4.9988V
4.9976V
4.9951V [
4.9902V'

9.9976V·1
9.9951V
9.9902V 1
9.9805V 1

9.9980V
9.9961V
9.9922V
9.9844V

4.9805V
4.9609V
4.9219V
4.8437V

9.9609V'
9.9219V I
9.8437V
9.6875V

4.6875V
4.3750V
3.7500V
2.5000V

I

I

±5V

I

I

±10V

4.9990V
4.9980V
4.9961V
4.9922V

1 4.9976V
I 4.9951V
4.9902V
4.9805V

9.9951V
9.9902V
9.9805V
9.9609V

9.9687V
9,9375V
9.8750V
9.7500V

4.9844V
4.9687V
4.9375V
4.8750V

4.9609V
4.9219V
4.8437V
4.6875V

9.3750V
8.7500V
7.5000V
5.0000V

9.5000V
9.0000V
8.0000V
6.0000V

4.7500V
4.5000V
4.0000V
3.0000V

1.2500V
0.6250V
0.3125V
0.1563V

2.5000V
1.2500V
0.6250V
0.3125V

4.0000V
3.0000V
2.5000V
2.2500V

0.0781V
0.0391 V
0.0196V
0.0098V

0.1563V
0.0781V
0.0391 V
0.0196V

0.0049V
0.0024V
0.0012V
O.OOOOV

0.0098V
0.0049V
0.0024V
O.OOOOV

II'

I

I

Note 1:

NO SIGN
I EXTENSION

WITH SIGN
EXTENSION

7FFO'
7FEO
7FCO
7F80

9.9219V
9.8437V
9.6875V
9.3750V

FFOO
FEOO
FCOO
F800

7FOO
7EOO
7COO
7800

4.3750V
3.7500V
2.5000V
O.OOOOV

8.7500V
7.5000V
5.0000V
O.OOOOV

FOOO
EOOO
COOO
8000

7000
6000
4000
0000

2.0000V
1.5000V
1.2500V
1.1250V

-2.5000V
-3.7500V
-4.3750V
-4.6875V

-5.0000V
-7.5000V
-8.7500V
-9.3750V

4000
2000
1000
0800

COOO
AOOO
9000
8800

2.1250V
2.0625V
2.0312V
2.0156V

1.0625V
1.0312V
1.0156V
1.0078V

-4.8437V
-4.9219V
-4.9609V
-4.9805V

-9.6875V
-9.8437V
-9.9219V
-9.9609V

0400
0200
0100
0080

8400
8200
8100
8080

2.0078V
2.0039V
2.0020V
2,0000V

1.0039V
1.0020V
1.0010V
1.0000V

-4.9902V
-4.9951V
-4.9976V
-5.0000V

-9.9805V
-9.9902V
-9.9951 V
-10.0000V

0040
0020
0010
0000

8040
8020
8010
8000

Both the 250n and the 500n resistors (0.1% precision) provide 4 to 20 rnA
output. The current output circuit is calibrated in terms of voltage since most
digital multimeters provide greater resolution and accuracy on voltage measurements than on current

-supplied DC regulated voltage, V+ {+15V < V+ S +30V for 2500 resistor,
+ 18V < V+ :0:;: +30V for 500!~ resistor; 25 mA max} is required for current output and calibration, and should be connected to ~V + LOOP". The supply
providing V+ should be grounded at "ANA ATN".

The voltages listed are those measured across a 250n or a 500n precision
resistor, connected between "I RTN" and "lOUT" on any DAC output. A user

11-128

I

FFFO
FFEO
FFCO
FF80

i

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356

ST-728
TRANSFER ACKNOWLEDGE (XACK/) DELAY SELECTION
XACKI DELAY SELECTION

The ST-728 board generates a Transfer Acknowledge
(XACK) signal in response to Write commands from the
host computer. It is sometimes desirable to delay this signal in order to match the XACKI signal to the host computer
timing. A jumper selectable Transfer Acknowledge Delay
(XACK/delay) ranging from 50 nanoseconds to 1.5 microseconds is available in the ST-728.

DELAY
flsec.

JUMPERS

The accuracy of the XACK/delay is dependent in part on the
duty cycle of the CClKI signal generated by the computershorter duty cycles result in greater accuracy. The delay
time is advanced on the leading edge of CClK/; XACKI is
generated on the trailing edge of CClKl.
71-72
71-72
71-72
71-72

Please refer to the table for jumper configurations yielding
different delay times.
I

67 -68

65-66

.----.=--=-~i~!~---·-r-::-~=:~~~l! li~l!
'Factory supplied configuration

COMPONENT SIDE

J1

J2

J3

(USED ON SH28B ONLy)
49

NOT USED
49

GAIN
DAC 1

XACK

[

DELAY
SELECT

i6.-;;
- --,,
,..

.,... ___ _

187·-sa

I .-;.

I

69

10 I

:: I

L __ ~L 7!..1

.

I}

17'
L_!.~
J
1 13

15

INPUT
CODe

+ 5V DC·TO·DC

SELECTION

CONVERTER

BASE ADDRESS
DECODER

,.--------,
I~

I

1~81831

,

•••• I

L _ _ _ _.. ':"_ J

(SH28C ONLy)

......

PS1

P1

P2

ST-728 Board Layout

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-11941TEL (508) 339-30001TLX 174388/FAX (508) 339-6356 11-129

ST-728
BASE ADDRESS SELECTION
(For Assembly D-11625, Revision F or later)
----------------

Base Address
(Hexadecimal)

(0 to F)

(0 to F)

(0 to F)

t--~-------~~-.-~--

Hex bit
weighing

--~,~-------------

(0 to F)

-.----.---~--~-

842 1

8421

842 1

842 1

842 1

Address Bit
(Hex)

17161514

13121110

FED C

BA98

7654

Jumper
(see note 1)

A A A A
17161514

i

- ..

,-.--.~--

..-

3-0

A A A A AF AE AD AC AB AA A9 A8 _ A 7 A 6 A 5 D
13121110

- _.._ - -- - - , - - - - -

I

I

f")
I*

[see note 2]

(0 to F)

Note 1: Jumper Out;" 0", Jumper In; "1" .
• Address bits 3 - 0 are decoded by D/A channel addressing.
Note 2: For 24-bit addressing, install jumper 80~81. For 16- or 20~bit addressing, remove jumper 80~81.
Note 3: To control 8- or 16-bit transfers by detecting BHEN/, remove jumper 84-85. Install jumper 84-85 to ground
BHENI (always low).

OUTPUT RANGE
INPUT CODING SELECTION
The ST-728's D/A output channels may be set independently for any of four voltage ranges or a single current output
range. Full scale ranges of±10V, ±5V, Oto +10V, Oto +5V,
or 4-20 mA may be jumper~selected according to the chart
below. Input digital coding may be offset binary, 2's com~
plement, or straight binary. Again, refer to the chart below
for details.

INPUT CODE SELECTION JUMPERS
CODE

The ST'728 board is normally shipped with jumpers set for
the ±10V output, and an offset binary input coding. Please
note that whenever there is a change in output range on a
given channel, that channel should be recalibrated.

DAC 0 TO DAC 3

DAC4 TO DAC 7

Unipolar or Offset
Bin. (Standard)

74~ 75

77-78

2's Complement

73~74

76-77

OUTPUT RANGE SELECTION JUMPER
-----,-----,---------r------,

R:1~~E ·II>~~O

~ndard) I
±5V

4-5
2~3

~~~11

~g:12-1

~:~92
20-21
18~19

~~~ll ~~~54

1

~~~16~:~{1

28-29 +--~3~6~-37
44-45
52-53
___6Q:~LI
-26-27
34-35--1-- 42~43
50~51
58-59
28___-...
30""------+_~~3___6__
-3___8_____+_--4'-'4-~4'-"6'----_+_--"5-"'2~-"5'-'4-+--60--6-2_
28~30
36-38
44-46 +-_52-54 _
60-62
28~30
36~38
44~46
i
52-54
60-62
29-31
__3_7_-3_9_
45-47
53-55
61-63
25-26
33-34
41-42
49-50
57-58

10-11
I
12~ 14
_ 2Q:2~~ _
o to +1OV_+-------"4___-6'----~+__-1.~2___-___14_____+_- 20-22 f
------4-6
12-14
20-22 ~I
oto +5V
5-7
13-15
21-23
I
4t020mA
1-2
9-10
17-18
Current_loop
7-8
1.5_.~.1.6..~..._L __._ . . . .2.~3...-2..4. .... __L_.__ ... _..3.1-32
4~6

~~~35

~

39-40

47-4.8 ..._L._._. . . .5..5:.~5_6... _

63-64

ORDERING GUIDE
MODEL NUMBER
DESCRIPTION
ST-728A12/24
4 D/A Channels, no DC-DC Converter (±15V dc, +5V dc power required)
ST-728B12/24
8 D/A Channels, no DC-DC Converter (±15V dc, +5V dc power required)
ST-728C2I24
4 D/A Channels, with DC-DC Converter (+5V dc power required)
ST-728D2I24
8 D/A Channels, with DC-DC Converter (+5V dc power required)
Edge Connector, J1 and J2, Spare
31-2076040
UM-ST-728
ST-728 Manual (Spare; one supplied with board)
Standard (2/24) versions includes the current loop option. Versions without current 100ps(1/24) are
available at lower cost for scheduled, quantity orders. _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

11-130

DATEL, Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

;UBSTITUTION GUIDE FOR DISCONTINUED PRODUCTS
The following products are no longer available from DATEL. Where applicable, the nearest equivalent DATEL replacement is listed. Some of these replacement products are functionally similar only
and may not be pin-for-pin compatible with the discontinued product.
DISCONTINUED
MODEL

NEAREST
EQUIVALENTS

DISCONTINUED
MODEL

NEAREST
EQUIVALENTS

9639 Series
ADC-833R
ADC-84,85,87
ADC-89 Series
ADC-E Series
ADC-G10B
ADC-G8B
ADC-HU
ADC-L Series
ADC·M Series
ADC-MA Series
ADC-SH4B
ADC-TV8B
ADC-UH Series
All -E version Power Supplies
All -J version Power Supplies
AM-100 Series
AM-200 Series
AM-300 Series
AM-410,-411
AM-470
AM-490
APP-20V Series
APP-20-2 Series
APP-48 MIL Series
BPM-12/210-D48
BPM-12/420·D48
BPM-15/330-D48
BPM-18/100-D12
BPM-18/100-D28
BPM-18/100-D5
BPM-18/140-D12
BPM-18/140-D24
BPM-18/140-D48
BPM-18/140-D5
BPM-18/25-D12
BPM-18/25-D28
BPM-18/25-D5
BPM-18/280-D12
BPM-18/280-D24
BPM-18/280-D28
BPM-18/280-D48
BPM-18/280-D5
CAPP-20
CDPP-Q7
DAC-19B Series
DAC-29B Series
DAC-49B Series
DAC-69B Series
DAC-71, -72
DAC-85,-87
DAC-9B Series
DAC-HA Series
DAC-HI Series
DAC-HR
DAC-I Series
DAC-V Series
DAC-VR Series

NONE
ADC·207
ADC-HX,-HZ
ADC-856
ADC-7109, ADC-ET Series
ADC-816, ADC-510/515
ADC·815
ADC-207
ADC-HX12B
ADC-HZ12B
ADC-HX12B
ADC-HS12B
ADC-208, ADC-304
ADC-208, ADC-304
NONE
NONE
AM-551
AM-542
NONE
NONE
NONE
AM-7650
NONE
APP-2-21 Series
APP-M48 Series
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
DAC·HZ12
DAC-HZ12
DAC-HZ12
DAC-HZ12
DAC-HP16
DAC-HZ12
DAC-IC8B
DAC-7533,-7541, -7134
DAC-HF Series
DAC·HP16
DAC-HF Series
DAC-HZ12
DAC-HK12

DAS·250
DAS-256 Series
DDS-32 Series
DM-2000AR
DM-2115
DM-350
DM-4100L
DM-4100N
DPP-7
DVC-350
ICT Series
LPS-16 Series
MDXP-32/32-1
SCS-16
SHM-1
SHM-2, -2E
SHM-UH
ST·LSI-RLY
ST -6800 Series
ST-6832 Series
ST-711 RLY
ST-800 Series
ST-MNOVA
ST-NOVA Series
ST-PDP Series
UPA-9/100
UPM-12/100A
UPM-12/420-D28
UPM-12/420-D48
UPM-12/840-D24
UPM-12/840-D28
UPM-12/840-D48
UPM-12/840-D5
UPM-15/100A
UPM·15/330-D12
UPM-15/330-D24
UPM·15/330-D28
UPM-15/330-D48
U PM-15/330-D5
UPM-15/660-D12
UPM-15/660-D24
UPM-15/660-D28
U PM-15/660-D48
U PM-15/660-D5
U PM-24/125-D5
UPM-24/420-D12
UPM-24/420-D5
UPM-28/180-D12
U PM-28/180-D5
UPM-28/360-D12
UPM-28/360-D5
UPM-5/1000-D48
UPM-5/1000-D5
UPM-5/200-D5
UPM-5/2000-D12
UPM-5/2000-D5
UPM-6/150A
UPM-9/100A
VFV Series

NONE
DVME Series
DVMESeries
DM-3102A, B
NONE
DM-31 00LlDM-31 OOB
DM-4101L
DM-4101N
DPP-Q7
DVC-350A
NONE
NONE
NONE
DVME-643
SHM-IC1, SHM-20
SHM-7, SHM-40
SHM-7, SHM-40
NONE
DVMESeries
DVMESeries
ST-702
ST-711/732 and ST-728
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
NONE
VFQ-1,-2,-3

DATEL, Inc, 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-30001TLX 174388/FAX (508) 339-6356

DATEL. Inc. 11 Cabot Boulevard, Mansfield, MA 02048-1194ITEL (508) 339-3000ITLX 174388/FAX (508) 339-6356

CUSTOMER PRICE LIST
EFFECTIVE NOVEMBER 1, 1988
LOOK FOR SUBSTANTIAL
PRICE REDUCTIONS ON
SELECTED PRODUCTS.

Prices In U.S. Dollars

ORDERING GUIDE
This ordering guide is presented as a procedural guide. For a formal statement of policies, refer to the TERMS AND
CONDITIONS OF SALE found on the Quotation form or on the Customer Acknowledgement copy of the Sales Order.
PLACING AN ORDER
When ordering a DATEL product, give the complete model number, product
description, and option description. Place orders with a DATEL field sales
representative or with the factory by letter, telephone, FAX, or TELEX. Minimum
order and minimum per shpment is $100.
OUTSIDE THE U.S.A. AND CANADA Place overseas orders with a DATEL
Sales Subsidiary (In West Germany, France, the Unhed Kingdom, and Japan) or
whh a DATEL overseas sales representative. Orders received directly will be treated
the same as placed through our overseas sales representative. In countries
without a DATEL representative, orders should be placed by TELEX and confirmed
by air mall.

n

FIELD SALES REPRESENTATIVE
DATEL employs field sales representatives throughout the United States, Canada,
Europe, and the Far East. In addition, it has direct Sales Offices in Santa Ana and
San Jose, California. DATEL also has Sales Subsidiaries in Munich, West
Germany; Paris, France; London, England; and Tokyo and Osaka, Japan. Only
these sales representatives are authorized by DATEL to solicit sales, and any
information or data received by sources other than these authorized representatives
or the DATEL factory are not considered binding.
PRICES
All prices are F.O.B. , Mansfield, Massachusetts, U.S.A. in U.S. dollars. Applicable
federal, state, and local taxes are extra and paid by buyer. Prices are subject to
change without notice.
TERMS Net 30 days
DISCOUNTS
Quanthy discounts are available when placed in a single order. OEM discounts are
available on an order or contract basis; consult the factory for details
QUOTATIONS
Price and delivery quotations made by DA TEL or hs authorized field sales
representatives are valid for 60 days unless otherwise stated.
DELIVERY
DATEL uses an IBM System 4381, for efficient processing of orders. All orders
placed with DATEL are acknowledged within a few days by an acknowledgement
copy of our sales order form. This copy indicates pertinent information including a
formal statement of terms and condhlons of sale and estimated delivery date. This
date has preference over all other agreed upon dates unless otherwise specified.

DATEL ships all products in rugged commercial containers suitable for insuring safe
delivery under normal shipping conditIons. Unless shipping method Is specified,
the best available method will be used. ShippIng charges are normally prepaid and
billed to the customer except for AIr Freight charges which are sent collect. The
appropriate data sheet and/or instruction Is packed with each product shipped.
ORDER CANCELLATION
All orders entered whh DATEL are binding and are subject to a cancellation charge
if cancelled before or after the scheduled shipping date appearing on the
acknowledgement copy of the sales order form. Refer to DATEL's Standard Terms
and Condhions for specHlc charges.
WARRANTY
DATEL warrants that all of hs products are free from defects in material and
workmanship under normal use and service for a period of one year from date of
shipment. DATEL's obligations under this warranty are limited to replacing or
repairing, at hs option, at hs factory or facilhy, any-of the products which shall within
the applicable period after shipment be returned to DA TEL's facility, transportation
charges prepaid, and which are after examination disclosed to the satisfaction of
DATEL to be thus defective. This warranty shall not apply to any such equipment
which shall have been repaired or altered except by DATEL or which shall have
been subjected to misuse, negligence, or accident. In no case shall DATEL's
lIabliky exceed the original purchase price. The aforementioned provisions do not
extend the original warranty period 01 any product which has either been repaired or
replaced by DATEL.
RETURNS
You will need a return authorization number and shipping instructions from the
factory when returning products for any reason. Items should not be returned air
freight collect as they connot be accepted. It is absolutely necessary to return
products in the manner stated here, otherwise considerable delay will result in
processing the return.
RETURNS OUTSIDE THE U.S.A. AND CANADA Contact the local sales
representative or factory for authorization and shipping instructions first.
CERTIFICATE OF COMPLIANCE
When requested by the customer DATEL will provide a standard Certificate of
Compliance with all shipments. This request must be specified on the purchase
order.

DATEL, INC. 11 CABOT BOULEVARD, MANSFIELD, MASS. 02048 U.S.A.
TEL. (508) 339-3000

FAX: (508) 339-6356

TELEX: 174388

EFFECTIVE November 1, 1988
MODEL

MODEL

PRICE

CUSTOMER PRICE LIST
PRICE

ADC-B207/208
ADC-B301E
ADC-B302E
ADC-B303E
ADC-B304E

450.00
959.00
1436.00
2426.00
509.00

ADC-B310E
ADC-B500
ADC-B500-1
ADC-B505
ADC-EHI0Bl

2536.00
726.00
173.00
702.00
199.00

ADC-5212H
ADC-5212H-QL
ADC-5214
ADC-5214H
ADC-5214H-QL

201.00
330.00
155.00
201.00
330.00

AM-1435MM-QL
AM-227
AM-427-1A
AM-427-1B
AM-427-2A

ADC-EHI0B2
ADC-EH12B2
ADC-EH12B3
ADC-EH8B1
ADC-EH8B2

242.00
257.00
263.00
120.00
170.00

ADC-5215
ADC-5215H
ADC-5215H-QL
ADC-5216
ADC-5216H

155.00
201. 00
330.00
155.00
201. 00

AM-427-2B
AM-430A
AM-430B
AM-450-2
AM-450-2M

ADC-EK10B
ADC-EK12B
ADC-EK12DC
ADC-EK12DM
ADC-EK12DR

29.25
38.25
12.55
35.10
26.85

ADC-5216H-QL
ADC-574ZA
ADC-574ZB
ADC-574ZC
ADC-674ZA

330.00
83.55
47.45
36.20
93.85

ADC-EK8B
ADC-ET10BC
ADC-ET10BM
ADC-ET12BC
ADC-ET12BM

11.05
16.50
46.15
18.40
62.50

ADC-674ZB
ADC-674ZC
ADC-7109
ADC-800
ADC-810MC

'" ADC-521MM-QL
ADC-5211
ADC-5211H
ADC-5211H-QL
ADC-5212

264.00
155.00
201.00
330.00
155.00

154.00
117.00
5.00
9.40
6.50

BPM-151100
BPM-151150-D24
BPM-15/150-D28
BPM-15/150-D5
BPM-15/200

63.00
81.00
81.00
81.00
79.00

9.00
6.65
16.50
4.35
21.35

BPM-15/25-D12
BPM -15/25-D28
BPM-15/25-D5
BPM-15/300
BPM-15/60

49.00
49.00
49.00
95.00
57.00

AM-452-2
AM-452-2M
AM-453-2C
AM-453-2M
AM-460-2

6.70
20.45
5.50
6.25
6.65

BPM-150/20
BPM-180/16
BPM-5/250
BPM-5/500
BPS-121125-D12

105.00
105.00
77.00
79.00
86.00

60.95
46.45
13.45
24.75
258.00

AM-462-2
AM-464-2
AM-500GC
AM-500MC
AM-500MM

6.65
6.15
113.00
124.00
167.00

BPS-12/125-D28
BPS-12/125-D5
BPS-121l250- D12
BPS-1211250-D24
BPS-12/230-D12

86.00
86.00
169.00
169.00
112.00

AM-500MM-QL
AM-543MC
AM-551MC
AM-551MM
AM-551MM-QL
AM-7650-1

185.00
203.00
71.00
85.00
101. 00
4.05

BPS-12/230-D24
BPS-12/230-D28
BPS-12/230-D5
BPS-12/40-D5
BPS-12/625-DI2

112.00
112.00
112.00
43.00
125.00

AM-7650-2
APP-M20Al
APP-M20A21
APP-M20D1
APP-M20D21

4.95
709.00
820.00
709.00
820.00

BPS-12/625-D24
BPS-15/100-D12
BPS-15/100-D28
BPS-151l00-D5
BPS-15/1000-D12

125.00
86.00
86.00
86.00
169.00

APP-M20D3
APP-M20E1
APP-M20E21
APP-M48D1
APP-M48D2

865.00
709.00
820.00
1165.00
1165.00

BPS-15/1000-D24
BPS-151190-D12
BPS-151l90-D24
BPS-15/190-D28
BPS-15/190-D48

169.00
112.00
112.00
112.00
112.00

APP-M48D3
APP-M48D4
APP-20A1
APP-20A21
APP-20A3

1165.00
1370.00
615.00
720.00
775.00

BPS-15/190-D5
BPS-15/3S-D5
BPS-15/412-D12
BPS-15/412-D24
BPS-15/412-D28

112.00
4S.00
135.00
135.00
135.00

APP-20D1
APP-20D21
APP-20D3
APP-20E1
APP-20E21

615.00
720.00
775.00
615.00
720.00

BPS-15/412-D5
BPS-15/500-D12
BPS-15/500-D24
DAC-DG12B1
DAC-DG12B2

135.00
125.00
125.00
415.00
415.00

DAC-HF10BMC
DAC-HF10BMM
DAC-HF10BMM-QL
DAC-HF12BMC
DAC-HF12BMM

171. 00
210.00
296.00
201. 00
239.00

DAC-HF12BMM-QL
DAC-HF8BMC
DAC-HF8BMM
DAC-HF8BMM-QL
DAC-HKB-2/883B

324.00
158.00
192.00
275.00
217.00

DAC-HKB/883B
DAC-HK12BGC
DAC-HK12BGC-2
DAC-HK12BMC
DAC-HK12BMC-2

217.00
67.00
67.00
82.00
82.00

DAC-HKI2BMM
DAC-HK12BMM-2
DAC-HPB-1I883B
DAC-HPB/883B
DAC-HP16BGC

139.00
139.00
241. 00
241.00
78.00

DAC-HP16BGC-1
DAC-HP16BMC
DAC-HP 16BMC-1
DAC-HP16BMM
DAC-HP16BMM-1

78.00
93.00
93.00
163.00
163.00

DAC-HZB/883B
DAC-HZ12BGC
DAC-HZ12BMC
DAC-HZ12BMM
DAC-HZ12DGC

185.00
48.00
58.00
108.00
87.00

398.00
502.00
235.00
363.00
458.00

ADC-HC12BMM-QL
ADC-HS12BMC
ADC-HS12BMM
ADC-HS12BMM-QL
ADC-HX/883B

373.00
167.00
227.00
313.00
293.00

ADC-815MC
ADC-815MM
ADC-815MM-QL
ADC-816/883B
ADC-816MC

201. 00
258.00
284.00
370.00
218.00

ADC-HX12BGC
ADC-HX12BMC
ADC-HX12BMM
ADC-HZ/883B
ADC-HZ12BGC

106.00
135.00
189.00
307.00
137.00

ADC-816MM
ADC-817AMC
ADC-817AMM
ADC-817AMM-QL
ADC-817MC

299.00
263.00
336.00
447.00
338.00

ADC-HZ12BMC
ADC-HZ12BMM
ADC-MC8BC
ADC-MC8BM
ADC-207/883B

155.00
220.00
7.45
13.00
179.00

ADC-817MM
ADC-817MM-QL
ADC-825MC
ADC-825MM
ADC-825MM-QL

411.00
522.00
177.00
240.00
265.00

ADC-207MC
ADC-207MM
ADC-208/883B
ADC-208MC
ADC-208MM

40.00
78.00
211.00
66.00
115.00

ADC-826/883B
ADC-826MC
ADC-826MM
ADC-827AMC
ADC-827AMM

345.00
197.00
279.00
245.00
313.00

ADC-300
ADC-301
ADC-302
ADC-S03
ADC-304

40.00
105.00
215.00
550.00
43.00

ADC-827AMM-QL
ADC-827MC
ADC-827MM
ADC-827MM-QL
ADC-830C

416.00
320.00
388.00
491.00
7.00

ADC-310
ADC-500BMC
ADC-500BMM
ADC-505BMC
ADC-505BMM

590.00
249.00
274.00
240.00
264.00

ADC-847A
ADC-847B
ADC-847M
ADC-856C
ADC-856M

'" ADC-505BMM-QL
'" ADC-508MC
~ ADC-508MM
~ ADC-508MM-QL
~ ADC-510BMC

288.00
2S0.00
253.00
276.00
230.00

ADC-868
ADC-881
ADC-974
'" ADS-105MC
'" ADS-105MM

7Sl. 00
451.00
999.00
279.00
307.00

~
~

ADC-510BMM
ADC-510BMM-QL
ADC-5101
ADC-5101H
ADC-510lH-QL

253.00
276.00
224.00
300.00
360.00

'" ADS-105MM-QL
~ ADS-106MC
'" ADS-106MM
ADS-106MM-QL
ADS-lllMC

335.00
279.00
307.00
335.00
229.00

ADC-511MC
ADC-511MM
ADC-515BMC
ADC-515BMM
ADC-515BMM-QL

199.00
219.00
220.00
242.00
264.00

'"
'"
'"
'"

ADS-111MM
ADS-115MC
ADS-115MM
ADS-115MM-QL
ADS-116MC

252.00
249.00
274.00
324.00
249.00

220.00
242.00
264.00
220.00
242.00

'" ADS-116MM
'" ADS-116MM-QL
ADS-125MC
ADS-125MM
ADS-126MC

274.00
324.00
250.00
274.00
250.00

~

'"

~
~

'"

'" ADC-520MC
'" ADC-520MM
ADC-520MM-QL
~ ADC-521MC
'" ADC-521MM

'"

PRICE
128.00
128.00
128.00
57.00
105.00

ADC-810MM
ADC-810MM-QL
ADC-811MC
ADC-811MM
ADC-811MM-QL

~

MODEL
BPM-12/420-D24
BPM-12/420-D28
BPM-12/420-D5
BPM-12/60
BPM-120/25

43.50
13.15
36.40
246.00
336.00

6.70
18.30
30.50
47.00
61.95

ADS-126MM
'" ADS-21AC
'" ADS-22AC
AM-1435MC
AM-1435MM

PRICE
274.00
475.00
425.00
99.00
138.00

ADC-ET12BR
ADC-ET8BC
ADC-ET8BM
ADC-HC12BMC
ADC-HC12BMM

'"

MODEL

APP-20E3
APP-20Jl
APP-20J2
APP-20J3
APP-48Al

775.00
615.00
820.00
775.00
1060.00

APP-48A2
APP-48A3
APP-48A4
APP-48D1
APP-48D2

1060.00
1060.00
1295.00
1060.00
1060.00

APP-48D3
APP-48D4
APP-48E1
APP-48E2
APP-48E3

1060.00
1295.00
1060.00
1060.00
1060.00

APP-48E4
APP-48J2
APP-48J3
APP-48J4
BCM-151100

1295.00
1060.00
1060.00
1295.00
63.00

BCM·15/200
BCM-15/300
BCM-15/60
BPM-12/100
BPM-12/200

79.00
95.00
57.00
61.00
79.00

BPM-12/25-D12
BPM-12/25-D28
BPM -12/25-D5
BPM-12/300
BPM-12/420-D12

49.00
49.00
49.00
101. 00
128.00

(

,,

/'

i

"

'"

-"

"'--/

CUSTOMER PRICE LIST

EFFECTIVE November " '988
MODEL

MODEL

PRICE

MODEL

PRICE

720.00
636.00
660.00
635.00
650.00

FLJ-D2
FLJ-D6LA1
FLJ-D5LA2
FLJ-D6LA1
FLJ-D6LA2

226.00
220.00
220.00
222.00
222.00

PM-5060-1010A
PM-5060-10lOE
PM-5060-1010J
PM-6070-1000A
PM-5070-1000E

460.00
460.00
460.00
426.00
425.00

23.15
2.65
11.45
12.00
6.50

DPP-Q7B3
DPP-Q7B3H
DPP-Q7B4
DPP-Q7B4H
DPP-Q7B5

636.00
650.00
636.00
650.00
720.00

FLJ-R3BAl
FLJ-R3BA2
FLJ-RSLAI
FLJ-RSLA2
FLJ-RSLBI

126.00
126.00
16S.00
16S.00
16S.00

PM-5070-1000J
PM-5070-1010A
PM-5070-1010E
PM-5070-1010J
PM-5080-1000A

425.00
490.00
490.00
490.00
395.00

DAC-UP8BM
DAC-08BC
DAC-08BM
DAC-OS05MR
DAC-OS05MR-QL

16.00
2.25
4.50
105.00
124.00

DPP-Q7B5H
DPP-Q7B6
DPP-Q7E1
DPP-Q7E1H
DPP-Q7E2

720.00
720.00
635.00
650.00
635.00

FLJ-RSLB2
FLJ-UR1BA1
FLJ-UR1BA2
FLJ-UR2BA1
FLJ-UR2BA2

16S.00
40.00
40.00
61.00
61.00

PM - 50S0-1000E
PM - 5080-1000J
PM-50S0-1010A
PM-50S0-1010E
PM-50S0-1010J

395.00
395.00
460.00
460.00
460.00

DAC-330
DAC-562C
DAC-60SC
DAC-610C
DAC-612C

112.00
18.35
3.75
10.45
17.15

DPP-Q7E2H
DPP-Q7E3
DPP-Q7E3H
DPP-Q7E4
DPP-Q7E5

650.00
635.00
650.00
635.00
720.00

FLJ-UR2EA1
FLJ-UR2EA2
FLJ-UR2LH1
FLJ-UR2LH2
FLJ-UR4HA1

59.00
59.00
40.00
40.00
47.00

ROJ-1K
ROJ-20
SCM-100A
SCM-I00B
SCM-101

97.00
97.00
253.00
300.00
244.00

DAC-7134BJ
DAC-7134BK
DAC-7134BL
DAC-7134UJ
DAC-7134UK

21.40
32.95
49.45
21.40
32.95

DPP-Q7E6
DPP-Q7J1
DPP-Q7J2
DPP-Q7J2H
DPP-Q7J3

720.00
635.00
635.00
650.00
635.00

FLJ-UR4HA2
FLJ-UR4HB1
FLJ-UR4HB2
FLJ-UR4LA1
FLJ-UR4LA2

47.00
47.00
47.00
47.00
47.00

SCM-103
SDAS-SA1
SDAS-SA2
SDAS-SA3
SDAS-SA4

165.00
479.00
479.00
479.00
479.00

DAC-7134UL
DAC-7523
DAC-7533
DAC-7541
DAC-8308

49.45
3.75
6.00
13.90
162.00

DPP-Q7J4
DVC-350A
DVC-S500A
DVC-S500E
DVC-8500J

635.00
3S7.00
959.00
959.00
959.00

FLJ-UR4LB1
FLJ-UR4LB2
FLJ-VB
FLJ-VH
FLJ-VL

47.00
47.00
176.00
176.00
176.00

SDAS-8E1
SDAS-SE2
SDAS-SE3
SDAS-8E4
SHM-HUMC

479.00
479.00
479.00
479.00
150.00

DVME-C-01
DVME-C-02
DVME-IOTEST/P
DVME-IOTEST/V
DVME-UTIL/P

40.00
50.00
50.00
50.00
385.00

FLT-C1
FLT-U2
FLT-U2-M
HDAS-16/883B
HDAS-16MC

35.75
26.50
42.75
675.00
350.00

SHM-HUMM
SHM-HUMM-QL
SHM-IC-1
SHM-IC-1M
SHM-LM-2

178.00
197.00
10.05
45.85
4.05

DAS-952R
DBM-20
DILS-1
DlLS-2
DlLS-S

14.90
59.00
3.80
3.80
3.S0
65.00
49.00
99.00
65.00
195.00

DVME-UTIL/V
DVME-601A
DVME-601B
DVME-601B- U
DVME-601C

3S5.00
1995.00
2095.00
2095.00
2695.00

HDAS-16MM
HDAS-8/883B
HDAS-8MC
HDAS-8MM
MDAS-16

418.00
675.00
350.00
41S.00
339.00

SHM-UH3
SHM-2
SHM-2E
SHM-20C
SHM-30C

268.00
136.00
150.00
13.40
29.45

59.00
76.00
S5.00
S9.00
79.00

DVME-601C-U
DVME-601D
DVME-601E
DVME-602H
DVME-602R

2695.00
2195.00
2195.00
1419.00
1419.00

MDAS-SD
MDAS-940D
MDAS-940S
MPP-20A
MPP-20D

339.00
3S6.00
3S6.00
440.00
440.00

SHM-360
SHM-361
-A- SHM-40MC
-A- SHM-40MM
-A- SHM-45MC

lS.00
27.00
143.00
157.00
154.00

DM-3101-1
DM-3102A
DM-3102B
DM-3103-1
DM-3104-1

99.00
170.00
145.00
99.00
99.00

DVME-602T
DVME-611A
DVME-611B
DVME-611B-U
DVME-611C

1375.00
1495.00
1617.00
1617.00
163S.00

MPP-20E
MPP-20J
MS-1
MS-ll
MS-13

440.00
440.00
33.25
5.40
5.40

-A-A-A-A-A-

DM-4100D-1
DM-4101D-1
DM-4101L-1
DM-4101N-l
DM-4102

155.00
145.00
S9.00
95.00
65.00

DVME-611C-U
DVME-611D
DVME-611E
DVME-612A
DVME-612B

163S.00
164S.00
1717.00
1595.00
1712.00

MS-2
MS-3
MS-4
MS-5
MS-6

DM-4103
DM-4104
DM-4105-1
DM-4106
DM-4200-1

65.00
75.00
105.00
69.00
S5.00

DVME-612B- U
DVME-612C
DVME-612C- U
DVME-612D
DVME-612E

1712.00
1732.00
1732.00
1742.00
lS12.00

DM-500-1
DM-9100-1
DM-9115-1
DM-9150-1
DM-9165-1

29.00
89.00
99.00
99.00
99.00

DVME-624C1
DVME-624C2
DVME-624V1
DVME-624V2
DVME-626V1

DM-9200-1
DM-9215-1
DM-9250-1
DM-9265-1
DPP-Q7A1

95.00
109.00
115.00
109.00
635.00

DPP-Q7A1H
DPP-Q7A2
DPP-Q7A2H
DPP-Q7A3
DPP-Q7A3H
DPP-Q7A4
DPP-Q7A4H
DPP-Q7A5
DPP-Q7A5H
DPP-Q7A6

DM-LXS-1
DM-31-1
DM-3100B-1
DM-3100L-1
DM-3100MIL-1
DM-3100N-1
DM-3100U1-1
DM-3100U2-1
DM-3100U3-1
DM-3100X-1

"

PRICE

DPP-Q7A6H
DPP-Q7B1
DPP-Q7B1H
DPP-Q7B2
DPP-Q7B2H

DAC-IC10BM
DAC-IC8BC
DAC-ICSBM
DAC-UP10BC
DAC-UPSBC

,1'

MODEL

106.00
139.00
189.00
14.95
9.95

DAC-HZ12DMC
DAC-HZ12DMM
DAC-HZ12DMM-QL
DAC-IC10B
DAC-IC10BC

(

PRICE

SHM-45MM
SHM-45MM-QL
SHM-4S60MC
SHM-4S60MM
SHM-4S60MM-QL

169.00
lS5.00
149.00
164.00
179.00

33.25
33.25
33.25
33.25
5.40

SHM-5
SHM-6MC
SHM-6MM
SHM-6MM-QL
SHM-7MC

204.00
153.00
219.00
243.00
136.00

MS-7
MS-9
MV-1606
MV-1606M
MV-SOS

5.40
5.40
11.S0
25.70
12.65

SHM-9MC
SHM-9MM
SHM-9MM-QL
SHM-91MC
SHM-91MM

65.00
117.00
129.00
144.00
214.00

1363.00
1577.00
1146.00
1360.00
176S.00

MVD-409
MVD-S07
MX-1606
MX-1616C
MX-80S

12.65
11.S0
20.95
27.90
11. 75

SHM-91MM-QL
ST-519
ST-701A2
ST-701A2/24
ST-701B2

250.00
465.00
174S.00
174S.00
IS23.00

DVME-626V2
DVME-628C
DVME-628V
DVME-641
DVME-643H

1768.00
1708.00
1345.00
695.00
1523.00

MX-81SC
MXD-409
MXD-807
PC-6
PM -5050-1000A

14.50
11.70
20.95
169.00
395.00

ST-701B2-U
ST-701B2/24
ST-701C2
ST-701C2/24
ST-701D2

1823.00
1823.00
2140.00
2140.00
1674.00

650.00
635.00
650.00
635.00
650.00

DVME-643T
DVME-645
DVME-660
DVME-691A
DVME-691D

1435.00
1385.00
795.00
295.00
295.00

PM -5050-1000D
PM-5050-1000E
PM-5050-1000J
PM-5050-1010A
PM-5050-1010D

430.00
395.00
395.00
460.00
495.00

ST-701D2/24
ST-701E2/24
ST-702A
ST-702B
ST-702R

1674.00
1923.00
1478.00
1478.00
1478.00

635.00
650.00
720.00
720.00
720.00

FLJ-ACR1
FLJ-ACR2
FLJ-ACOI
FLJ-DC
FLJ-D1

80.00
80.00
40.00
190.00
225.00

PM-5050-1010E
PM -5050-1010J
PM-5060-1000A
PM-5060-1000E
PM -5060-1000J

460.00
460.00
395.00
395.00
395.00

ST-703A
ST-703B
ST-706A1
ST-705A2
ST-705A3

1033.00
1208.00
785.00
785.00
785.00

EFFECTIVE November 1,1988
MODEL

PRICE

MODEL

CUSTOMER PRICE LIST
PRICE

ST-705A4
ST-705El
ST-705E2
ST·706E3
ST-705E4

785.00
785.00
785.00
786.00
786.00

TPM-15/200-5/600
108.00
TPS-12/310-5/1600-D12107.00
TPS-12/310-6/1500-D24 107.00
TPS-5/1500-12/310-D12107.00
TPS-6/1600-12/310-D24 107.00

ST-705Jl
ST-705J2
ST-705J3
ST-706J4
ST-711

786.00
786.00
786.00
786.00
884.00

TPS-6/1600-16/260-D12 107.00
TPS-6/1600-16/260-D24 107.00
UCM-5/1000
83.00
UCM-5/1000-B
71.00
UCM-6/2000
93.00

ST-716B1
ST-716B2
ST-716C1
ST·716C2
ST-716D1

1406.00
1405.00
1006.00
1006.00
1613.00

UCM-6/260
UCM-6/600
UM - APP - 20AEJlI AEJ2
UM-APP-20AEJ3
UM - APP - 48AEJ2

ST-716D2
ST-724
ST-728A2/24
ST-728B2/24
ST-728C2/24

1613.00
849.00
773.00
1085.00
915.00

UM-APP-48AEJ3
UM-DPP-Q7
UM-DVC-350A
UM-DVME-601
UM-DVME-602

30.00
30.00
30.00
30.00
30.00

ST-728D2/24
ST-732
ST-742
TP-IK
TP-IM

1219.00
1117.00
595.-00
4.00
4.00

UM-DVME-611/612
UM-DVME-624
UM-DVME-626
UM-DVME-628
UM-DVME-641

30.00
30.00
30.00
30.00
30.00

UM-DVME-643
UM-DVME-645
UM-DVME-660
UM-DVME-691
UM-PM-5050
UM-PM-5060
UM-PM-5080
UM-ST-519
UM-ST-701
UM-ST-702

30.00
30.00
30.00
10.00
30.00
30.00
30.00
10.00
30.00
30.00

UM-ST-703
UM-ST-705
UM-ST-711/732
UM-ST-716
UM-ST-724

30.00
10.00
30.00
30.00
30.00

UM-ST-728
UPA-12/200
UPA-5/500
UPM-12/80-D5
UPM-24/125-D12

30.00
18.00
16.50
44.00
79.00

UPM-24/210-D12
UPM-24/210-D5

84.00
84.00

TP-I0
TP-I0K
TP-I00
TP-I00K
TP-2K

4.00
4.00
4.00
4.00
4.00

TP-20
TP-20K
TP-200
TP-200K
TP-25K

4.00
4.00
4.00
4.00
4.00

TP-250
TP-5K
TP-50
TP-50K
TP-500
TPM-121100-5/600
TPM-12/150-5/1000
TPM-12/200-5/500
TPM-15/100-5/500
TPM-16/160-5/1000

4.00
4.00
4.00
4.00
4.00
90.00
108.00
108.00
90.00
108.00

64.00
56.00
30.00
30.00
30.00

MODEL
UPM-24/40-DI2
UPM -24/40-D6
UPM -28/100-DI2

PRICE
43.00
43.00
73.00

UPM -28/100-D5
UPM-28/25-DI2
UPM-28/26-D5
UPM-6/1000
UPM -6/1000B

73.00
43.00
43.00
79.00
67.00

UPM -6/200-DI2
UPM -6/200-D28
UPM-6/2000
UPM-5/250
UPM-5/500

44.00
44.00
89.00
60.00
64.00

UPS-12/1260-D12
UPS-12/1260-D24
UPS-12/260-D28
UPS-12/260-D5
UPS-12/2500-D12

119.00
119.00
81.00
81.00
169.00

UPS-12/2600.-D24
UPS-12/470-D24
UPS-12/470-D5
UPS-12/80-D6
UPS-15/1000-D12

159.00
107.00
107.00
42.00
119.00

UPS-16/1000-D24
UPS-16/2000- D12
UPS-15/2000-D24
UPS-15/65-D5
UPS-6/1000-DI2

119.00
159.00
169.00
42.00
107.00

UPS-5/1000-D24
UPS-6/1000-D28
UPS-5/2000-D24
UPS-5/2000-D28
UPS-5/2000-D48

107.00
107.00
134.00
134.00
134.00

UPS-5/3000-D12
UPS-5/3000-D24
UPS-5/5000-D12
UPS-6/6000-D24
UPS-5/600-DI2

119.00
119.00
159.00
159.00
81.00

UPS-5/600-D28
UPS-6/600-D5
USC-5/3
USC-5/5
USM-5/3

81.00
81.00
135.00
144.00
135.00

USM-5/5
VFQ-IC
VFQ-IR

144.00
4.60
12.00

MODEL
VFQ-2C
VFQ-3C
VI-7660-1
VI-7660-2
VR-182A
VR-182B
VR-182C

PRICE
11.65
2.65
2.10
3.00
1.10.
1.36
1.55

48 Column Printer Paper; 10 Rolls
DPP-Q7 Printer Paper; 10 Rolls
20 Column Printer Paper; 10 Rolls
DPP-Q7/ APP-20 Stand Kit
APP-48 Stand Kit

38-8193022
38-8193900
38-8193901
38-8193902
39-2106705

DVC-8500 Panel Mount Kit
DVC-8500 10:1 Attenuator
DVC-8500 100:1 Attenuator
DVC-8500 Test Lead Set
DM-LX3/DM-3114 Pin DIP Connector

39-7267690
39-7341560
39-8194910
58-1214050
58-2073078

DVC-350A Accessory Kit (AC Recharger and NiCad Battery)
DM-9000 Screw Tenninal Connector
DM-31 Accessory Kit (Bezel, Connector, and Mounting Hardware)
Data Acquisition Handbook
DM-9000 Solder Tab Connector

58-2073082
58-2073083
58-2075010
60-2105600

DPM Connector; 10 Pin
DPM Connector; 15 Pin
DPM Connector; 18 Pin
ST-702 and ST-705 Detachable Screw Tenninal Connector (Fonnerly 6012474-1)

ADC-12/2 VME
ADC-12/20 VME
ADC-12/4 VME
ADC-12/4-UVME
ADC-16/35 VME

560.00
296.00
450.00
450.00
695.00

ADC-16/35- U VME
ADC-16/400K VME
APP-TRIA
APP-TRID
APP-TRIE

695.00
395.00
130.00
130.00
130.00

APP-TR2A
APP-TR2D
APP-TR2E
APP-TR5A
APP-TR5D
APP-TR5E

130.00
130.00
130.00
130.00
130.00
130.00

BPM-15/220-D5
32-2242568
32-2242570
32-2242572
33-8193200

115.00
55.00
35.00
35.00
10.00

33-8193205
38-8193022
38-8193900
38-8193901
38-8193902

10.00
36.00
54.00
59.00
17.00

39-2106706
39-7267690
39-7341560
39-8194910
68-12140- 50

5.00
27.00
20.00
11.00

58-2073078
58-2073082
58-2073083
58-2076010
60-2105600

6.00
4.00
5.00
6.00
62.00

DATEL makes no representation that the use of these products in the circuits described herein, or use of other technical information contained herein, will not Infringe upon existing
or future patent rights nor do the descriptions contained herein imply the granting of licenses to make, use, or sell equipment constructed in accordance therewnh.

6.95

JJCClEG

DATEL, Inc. 11 CABOT BOULEVARD, MANSFIELD, MA 02048-1194
TEL. (508) 339-3000 I TELEX 1743881 FAX (508) 339-6356
• Santa Ana, CA (714) 835-2751 or (213)933-7256 • San Jose, CA (408) 297-7944
• OVERSEAS: DATEL (UNITED KINGDOM) Tel. Basingstoke (256) 469-085 • DATEL (FRANCE) Tel. (1) 3460.0101
DATEL (GERMANY) Tel. (89) 53-0741 • DATEL (JAPAN) Tokyo Tel. (3) 779-1031 • Osaka Tel. (6) 354-2025
PRICES SUBJECT TO CHANGE WITHOUT NOTICE.

'-

ACCESSORIES

DESCRIPTION OF ACCESSORIES
32-2242568
32-2242570
32-2242572
33-8193200
33-8193205

/~

,~-.



File Type                       : PDF
File Type Extension             : pdf
MIME Type                       : application/pdf
PDF Version                     : 1.3
Linearized                      : No
XMP Toolkit                     : Adobe XMP Core 4.2.1-c041 52.342996, 2008/05/07-21:37:19
Create Date                     : 2017:07:20 17:14:27-08:00
Modify Date                     : 2017:07:20 17:54:44-07:00
Metadata Date                   : 2017:07:20 17:54:44-07:00
Producer                        : Adobe Acrobat 9.0 Paper Capture Plug-in
Format                          : application/pdf
Document ID                     : uuid:c92fb1ab-7b68-eb40-939b-92ea45c37b02
Instance ID                     : uuid:676a8501-d93c-1640-8576-fd8ba06f0e1c
Page Layout                     : SinglePage
Page Mode                       : UseNone
Page Count                      : 867