1988_SPT_Analog_Product_Catalog 1988 SPT Analog Product Catalog

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1988

Honeywell

SIGNAL PROCESSING
TECHNOLOGIES
JANUARY 1988
ANALOG PRODUCT
CATALOG

Honeywell Inc. SIGNAL PROCESSING TECHNOLOGIES 1150 E. Cheyenne Moun1ain Blvd., Colorado Springs, CO, U.S.A. 80906
(303) 577·1000 FAX (303) 577·3716 Telex *452433 Easylink #52926148 © 1988 Honeywell Inc."

Honeywell

L

GENERAL DISCLAIMER
This data book presents technical data for a wide variety of
integrated circuits and has been organized Into sections by product
type. Additional sections Include product selection guides, ordering
infonnation, package specifications, quality flows and application notes.
There are three types of data sheets in this book:

ADVANCE INFORMATION - These data sheets contain the
description of products that are in development. The specifications
are based on engineering calculations, computer simulations and/or
initial prototype evaluation.
PRELIMINARY - These data sheets contain minimum and maximum
specifications that are based upon initial device characterization.
These limits are subject to change upon the completion of full
characterization over the specified temperature and supply voltage
ranges.
FINAL - These data sheets contain specifications based on a
complete characterization of the device over the specified
temperature and supply voltage ranges.
Honeywell SPT reserves the right to make changes to its products or
specifications at any time, without notice, to improve the deSign
and/or performance in order to supply the best possible product.
Honeywell SPT does not assume any responsibility for the use of any
circuitry described in ths book other than the circuitry contained
within a Honeywell SPT product. Honeywell SPT makes no
representations that the circuitry described within this book is free
from patent infringement or other rights of third parties which may
result from its use. No license is granted by implication or
otherwise under any patent, patent rights, or other rights, of
Honeywell SPT.

Honeywell Inc., Signal Processing Technologies, reserves the right to change products and specifications without notice.
WARNING-LIFE SUPPORT APPLICATIONS POLICY-Honeywell SPT products shall not be used within any Life Support Systems
without the specific written consent of Honeywell SPT. A Life Support System is a product or system intended to support or sustain
life which, if it fails, can be reasonably expected to result in Significant personal injury or death .
• Permission is hereby expressly granted to copy this literature for informational purposes only. Copying this material for any other use
is strictly prohibited.

Honeywell

Honeywell

TABLE OF CONTENTS
SECTION 1 - Selection Guide .................... .

. ... 1·2

Product Cross Reference Guide.
SPT Product Identification Code ..... .
Ordering Information ................ .

1·5
1·6

1-4

SECTION 2 -e2~~~'4~oDlgltal ~o~ve~ers .... .

. ...
HADC674Z.
. ....... .
HADC77100 .....
HADC77200....
. .............. .
HADC77300...
. ......... .
HADC77600.....
. ....... .
...
HADC78160 .......................... .

SECTION 3 -~~'!~~~1~~.t~aIOCJ ~on.ve~ers ... .
HDAC10181AJB. . ........... .
HDAC34010.
. .......... .
HDAC34020.
HDAC50500 ..
HDAC50600 ..
HDAC50800.
HDAC51400 ..
HDAC51600..
. ........... .
HDAC52160....
.........
. ........ .
HDAC7541Z ......... .
HDAC7542A.
. .......... .
HDAC7543A... . ............ .
HDAC7545A.
HDAC97000.
HDAM51100

SECTION 4 -Comparators

HCM~6850 .... .
HCMP96870A ............ .
HCMP96900 ............ .

HINA522 ........................ .
HINA524 ............... .
HINA624 ................ .

-~f~~J?114~un~Uons....

5·3
5·5
. .............. 5·7

. ......... .

HSCF24040 ........... .

SECTION 7 -Evaluation Boards

EB100.............
.........
EB101......
EB102. . . . . . . .. ..................
. ..........
EB103........................
EB104..
...........................
EB105. . . . . . . . . . . . . . . . . . .
. ....................

SECTION 8 -~fo~c.at'~ns .1.n~orl11atlon .... .
AN101
AN102
AN103
AN104
AN106
AN108
AN109
AB100
AB101
AB102
AB103
AB1~

....
. ......... .
....
. ......... .
.............
.... .
.............. .
.....................
........... .
....
. ......... .
............
. ................ .
.......... .
..
......................... .
...
. ................................... .
..
. .................................. .
...
. ............................... .

SECTION 9 -Quality Assurance ......... .
SECTION 10

-~~cp~~~: ~utll.nes...........
PACKAGING INFORMATION. . . . . . .

SECTION 11 -Sales Representatives

3·3
3·15
3·27
3·37
3·47
3·49
3·59
3·69
3·81
3·101
3·103
3·115
3·117
3·119
3·131
3·147
4·3
4·13
4·23

SECTION 5 -Instrumentation Amplifiers

SECTION 6

2·3
2·23
2·43
2·63
2·83
2·103
2·113

6·3
6·5
7·3
7·5
7-7
7·9
7·11
7·13
8·3
8·29
8·42
8·67
8·83
8·89
8·111
8·117
8·123
8·129
8·131
8·133
8·137
9·1

. ............... 10.2
..........
. .10·9

DOMESTiC ......................................... 11·2
INTERNATIONAL .................................... 11·4

Honeywell

Honeywell

11

ANALOG TO DIGITAL CONVERTERS

•

DIGITAL TO ANALOG CONVERTERS

COMPARATORS

INSTRUMENTATION AMPLIFIERS

Ii

SPECIAL FUNCTIONS

.;J

Ii

EVALUATION BOARDS

Honeywell

APPLICATIONS INFORMATION

1:1

QUALITY ASSURANCE

U

PACKAGE OUTLINES

1[1:

SALES OFFICES AND
REPRESENTATIVES

III
1-1

PRODUCT SELECTION GUIDE
AID CONVERTERS
RESOLunoN
(BITS)

SAMPLE
RATE (MSPS)

HADC77300A

8

250

ECl

Y.

Y.

HADC77300B

8

250

ECl

'A

%

HADC77200A

8

150

ECl

Y.

Y.

HADC77200B

8

150

ECl

%

'A

HADC77100A

8

150

ECl

Y.

Y.

HADC77100B

8

150

ECl

'A

'A

HADC77800

10

50

ECl

HADC874A

12

15

TIL

Y.

Y.

HADC874B

12

15

TIL

Y.

Y.

HADC874C

12

15

TTL

HADC574A

12

25

TIL

Y.

Y.

HADC674B

12

25

TIL

Y.

Y.

HADC574C

12

25

TIL

PART NO.

CONVERSION
TIME!t4)

LOGIC
FAMILY

LINEARITY
INT
DIF

Y.

FEATURES
PIN COMPATABlE WITH HADC77200
IMPROVED ANALOG PERFORMANCE
DATA READY AND OVERRANGE OUTPUTS, QUARTER POINT LADDER TAPS,
IMPROVED ANALOG PERFORMANCE
PRE AMPLIFIER DESIGN
ON BOARD BUFFER, METASTABLE
STATE ERROR REDUCTION

s/H FUNCTION, lOW POWER,
NO NEGATIVE SUPPLY REQUIRED,
NO TRANSIENTS AT INPUT,
FUll BIPOLAR INPUT,
ALTERNATES FOR H1574, HI 674
AND AD574

D/A CONVERTERS
RESOLUTION
PART NO.

UPDATE
SETTLING
RATE (MSPS) TIME (ns)

LOGIC
FAMILY

LINEARITY
INT
DIF

FEATURES

4

100

4

TIL

Y.

Y.

HDAC34010

4

200

4

ECl

Y.

Y.

TRIPLE 4-BIT, REF, VIDEO CONTROL

HDAM61100

8

125

ECl

Y.

Y.

512 X 8 PALETTE, REF, VIDEO CONTROL

HDAC51800

8

165 (250 TYP)

3

TTL

Y.

Y.

5:1,4:1, MUX, REF, VIDEO CONTROL

HDAC 10180B

8

180

3

ECl

Y.

Y.

VIDEO CONTROL, ALTERNATE FOR TOC 1018

HDAC34020

1·2

(BITS)

TRIPLE 4-BIT, REF, VIDEO CONTROL

HDAC10181B

8

180

3

ECl

Y.

Y.

REF, VIDEO CONTROL

HDAM51200

8

200

3

ECl

V.

Y.

512 X 8 PALETTE, REF, VIDEO CONTROL

HDAC87000

8

200

10

ECl

Y.

Y.

REF, ALTERNATE FOR AD9700

HDAC 10180A

8

275

3

ECl

Y.

Y.

VIDEO CONTROL, ALTERNATE FOR TOC 1018

HDAC 10181A

8

275

REF, VIDEO CONTROL

HDAC61400

8

385

HDAC7541Z

ECl

Y.

Y.

3

ECl

Y.

Y.

REF, VIDEO CONTROL

12

500

TIL

Y.

Y.

ALTERNATE FOR AD7541A

HDAC7642A

12

500

TTL

Y.

Y.

ALTERNATE FOR AD7542

HDAC7543A

12

500

TIL

Y.

Y.

ALTERNATE FOR AD7543

HDAC7545A

12

500

TTL

Y.

Y.

ALTERNATE FOR AD7545

HDAC50600

12

500

TTL

Y.

Y.

MICROPROCESSOR INTERFACE

HDAC50800

14

500

TTL

Y.

Y.

PARAllEL INPUT

HDAC50800

14

500

TIL

Y.

Y.

2 BYTE INPUT

HDAC 52180

16

100

TTL

Y.

Y.

PARAllEL INPUT

Honeywell

PRODUCT SELECTION GUIDE
COMPARATORS
PART NO.

trltl

PROP
DELAY

(ns)

(nl)

VCM
(V)

Vos
(my)

RIN
(kO)

AV
(VIV)

FEATURES

1.76/1.72

3.0

±2.5V

±3.0

60

4k

SYMETRICAL trltf,
ALTERNATE FOR
SP9685, AM6685

HCMP 96870A

1.2/1.2

2.3

±2.5

±3.0

60

4k

HIGH PERFORMANCE,
ALTERNATE FOR
SP9687, AM6687

HCMP 96900

1.6/1.6

4.2

+10
-3

±0.5

10,000

1k

HCMP98850

D

HIGH Vem RANGE,
SYMETRICAL trlt, AND PROP
DELAY INDEPENDENT OF
OVERDRIVE AND Vem

INSTRUMENTATION AMPLIFIERS
NON·
LINEARITY

25

HINA 522

.001%
MAX
AV
1
.003%
MAX
AV
1

25

HINA524

.001%
MAX
AV
1

25

HINA824

GAIN
BANDWIDTH
(MHz)

Vos

I/LY)

PART NO.

SUPPLY
VOLTAGE
(V)

FEATURES

±15

=

25
AV = 1000

=

±15

ALTERNATE SOURCES FOR
ANALOG DEVICES
MONOLITHIC CONSTRUCTION

25
AV = 1000

=

±15

FILTER
PART NO.

DYNAMIC
RANGE
(dB)

HSCF 24040

85

MAX

BANDEDGE
TOLERANCE

BANDEDGE
(kHz)

(%)

±0,5

20

SUPPLY
VOLTAGE
(V)

±5

FEATURES
7TH ORDER LOW PASS, > 76dB
STOPBAND ATIENUATION, ON CHIP
ANTIALIAS FILTER, DIGITALLY
PROGRAMMABLE BANDEDGE AND
DC GAIN

EVALUATION
BOARDS

FEATURED
PRODUCT

FEATURES

EB 100

HADC77100

150MSPS AID, DIA

EB101

HADC77200

150MSPS AID, DIA

EB 102

NIA

100MHz BUFFER AMP, 8-BITS
300MSPS AID, DIA PING-PONG

EB 103

HADC772OO177300

EB104

HADC574/674

AID, D/A, OPTIONAL'S/H

EB 106

HSCF24040

ON-BOARD OR EXTERNAL
PROGRAMMING

Honeywell

1·3

PRODUCT CROSS 'REFERENCE GUIDE
INDUSTRY
PART NO.

J;

AD622AD
AD622BD
AD522SD
AD524AD
AD524BD
AD524CD
AD624SD
AD574AJD
AD574AJN
AD574AKD
AD574AKN
AD674ALD
AD674ALN
AD1124AD
AD1124BD
AD1124CD
AD824SO
AD7541AAQ
AD7641ASO
AD7541 ACHIPS
AD7541AJN
AD7541AKN
AD7541ASD
AD7541AlO
AD7642AD
AD7542BD
AD7542CHIPS
AD7542GSO
AD7542GKN
AD7542G1O
AD7542JN
AD7542KN
AD7542SD
AD754210
AD7543AD
AD7543BD
AD7543CH1PS
AD7643GBD
AD7543GKN
AD7543G1O
AD7643JN
AD7543KN
AD7543SD
AD754310

1·4

SPT
EQUIVALENT
H1NA522BIJ
HINA522AIJ
HINA522BMJ
HlNA524CIJ
HlNA524SIJ
HINA524AIJ
HINA524CMJ
HADC574ZCCJ
HADC574ZCCN
~574ZBCJ

HADC574ZBCN
HADC574ZACJ
HADC574ZACN
HINA824C1J
HlNA824SIJ
HINA824AIJ
HINA824CMJ
HDAC7541ZBID
HDAC7541ZA1D
HDAC7541ZBCU
HDAC7541ZBCN
HDAC7541ZACN
HDAC7541ZBMD
HDAC7541ZAMD
HDAC7542AB1D
HDAC7542AA1D
HDAC7542ABCU
HDAC7542AA1D1G
HDAC7542AACNIG
HDAC7542AAMD/G
HDAC7542ABCN
HDAC7542AACN
HDAC7542ABMD
HDAC7542AAMD
HDAC7543ABID
HDAC7543AAID
HDAC7543ABCU
HDAC7543AA1D/G
HDAC7543AACNIG
HDAC7543AAMDIG
HDAC7543ABCN
HDAC7543AACN
HDAC7543ABMD
HDAC7643AAMD

INDUSTRY
PART NO.
AD7545AO
AD7545BO
AD7545CHIPS
AD7545CO
AD7545GCO
AD7545GLN
AD7545GUD
AD7545JN
AD7545KN
AD7545LN
AD7545SD
AD754510
'A07545UD
AD9700D22A
AMe885Dl
AM8887Dl
AM8887LL
CX02118
HI1·574AJD-5
HI1·574AKD-5
HI1·574ALD-5
HI1..fl74AJD-5
HI1·874AKD-5
HI1·874ALD·5
MP7542
MP7542AD
MP7642BD
MP7542JN
MP7542KN
MP7542SD
MP754210
MP7543
MP7543AD
MP7543BD
MP7543JN
MP7543KN
MP7543SD
MP754310
MP7545
MP7545AD
MP7545BD
MP7545CD
MP7545JN
MP7545KN

SPT
EQUIVALENT
HDAC7545AB1D
HDAC7545ABID
HDAC7545ABCU
HDAC7545AA1D
HDAC7545AA1D1G
HDAC7545AACNJG
HDAC7545AAMDIG
HDAC1545ABCN
HDAC7545ABCN
HDAC7545AACN
HDAC7545ABMD
HDAC7545ABMD
' HDAC7545AAMD
HDAC970bOSJM
HCMPII8850S1D
HCMPII8870S1D
HCMP9887081C
HADC77100AIJ
HADC574ZCCJ
HADC574ZBCJ
HADC574ZACJ
HADC874ZCCJ
HADC874ZBCJ
HADC874ZACJ
HQAC7542ABCU
HDAC7542AB1D
HDAC7542AA1D
HDAC7542ABCN
HDAC7542AACN
HDAC7542ABMD
HDAC7542AAMD
HDAC7543ABCU
HDAC1543ABID
HDAC7543AA1D
HDAC7543ABCN
HDAC7543AACN
HDAC7543ABMD
HDAC7543AAMD
HDAC7545ABCU
HDAC7545ABID
HDAC7545ABID
HDAC7545AA1D
HDAC7545ABCN
HDAC7545ABCN

INDUSTRY
PART NO.
MP7545LN
MP7545SD
MP754510
MP7545UD
MP7823
MP7623AD
MP7623BD
MP7623JN
MP7623KN
MP7623SD
MP7623TD
PM7542AO
PM7542BO
PM7542SQ
PM7542EO
PM7542FO
PM7542FO
PM7542G
PM7542GP
PM7542HP
PM7542HP
PM7543AO
PM7543BQ
PM7543BQ
PM7543EO
PM7543FO
PM7543FO
PM7543G
PM7543GP
PM7543HP
PM7543HP
PM7545AR
PM7545BR
PM7545BR
PM7545ER
PM7545FR
PM7545FR
PM7545G
PM7545GP
PM7545HP
PM7545HP
SP9685DG16
SP9687DG16
TDC1018J7C

SPT
' EQUIVALENT
HDAC7545AACN
HDAC7545ABMD
HDAC7545ABMD
HDAC7545AAMD
,HDAC7541 ZCCU
HDAC7541ZBID
HDAC7541ZAID
HDAC7541ZBCN
HDAC7541ZACN
HDAC7541ZBMD
HDAC7541ZAMD
HDAC7542MMDIG
HDAC7542AAMD
HDAC7542ABMD
HDAC7542AAIDIG
HDAC7542AAID
HDAC7542ABID
HDAC7542ABCU
HDAC7542AACNIG
HDAC7542AACN
HDAC7542ABCN
HDAC7543MMDIG
HDAC7543AAMD
HDAC7543ABMD
HDAC7543AAIDIG
HDAC7543AAID
HDAC7543ABID
HDAC7543ABCU
HDAC7543AACNIG
HDAC7543AACN
HDAC7543ABCN
HDAC7545AAMD/G
HDAC754!iAAMD
HDAC7545ABMD
HDAC7545AAIDIG
HDAC7545AAID
HDAC7545ABID
HDAC7545ABCU
HDAC7545AACNIG
HDAC7545AACN
HDAC7545ABCN
HCMP968508ID
HCMP96870AID
HDAC10180AMJ

Honeywell

8PT PRODUCT IDENTIFICATION CODE

II

....- - - - - - - - - - - - - - - - - - - - - - - - - - PREFIX
...._ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ DEVICE TYPE
p-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ MODEL NUMBER

H

DAC

97000

r--------------

ELECTRIC GRADE

I

SPECIAL BY CUSTOMER
DRAWING OR SCREENING

,..-----------

TEMPERATURE OPERATING RANGE
...._ _ _ _ _ _ _ PACKAGE TYPE

I
L

1

01

S

+

J

o

C
G
N
T
M
H
U
L
S
X

OPTIONS:

+

H
G

Standard Bum-In
Standard HI-Rei Screening
Special Electric

CERAMIC SIDEBRAZED
CERDIP
LEADLESS CHIP CARRIER
PIN GRID ARRAY
PLASTIC DIP
PLASTIC QUAD
HYBRID METAL
HYBRID CERAMIC
DIE ONLY
LEADED CHIP CARRIER
SMALL OUTUNE
SPECIAL PACKAGE

M MIlitary (- 55' to + 125'C)
I Industrial (- 25' to + 85'C)
C Commercial (0 to 70'C)

~t

INCREASING GRADE

+SINGLE GRADE
.....- - - (See Product UsHngs)

ADC

- Analog-to DIgital Converter

---- gt3 :With
~::::::g:= gg;::::::~
Memory

Honeywell

CMP
INA
SCF
THA

- Comparator
- Instrumentation Amplifier
- Swnched Cepecnor FHter
- Track end Hold AmplWler

1·5

ORDERING ,INFORMATION"
ANALOG TO DIGITAL CONVERTERS
PART NUMBER

DESCRIPTION

PACKAGE TYPE

'PINS

TEMPERATURE

HADC674ZACN

12-BIT RESADC; 12-BIT LIN

PLASTIC·

28

COMMERCIAL

HADC674ZBCN

12-BIT RES ADO; 12-BIT LIN

PLASTIC·

28

COMMERCIAL

HADC674ZCCN

12-BIT RES ADC; II-BIT LIN

PLASTIC·

28

COMMERCIAL

HADC574ZACJ

12-BIT RES ADO; 12-BIT LIN

SIDEBRAZED

28

COMMERCIAL

HADC674Z8CJ

12-BIT RES ADO; 12-BIT LIN

SIDEBRAZED

28

COMMERCIAL

HADC674ZCCJ

12-BIT RES ADO; II-BIT LIN

SIDEBRAZED

28

COMMERCIAL

HADC674ZAMJ

12-BITRES ADO; 12-BIT LIN

SIDEBRAZED

28

MILITARY

HADC674ZBMJ

12-BIT RES ADO; 12-BIT LIN

SIDEBRAZED

28

MILITARY

HADC674ZCMJ

12-BIT RES ADO; II-BIT LIN

SIDEBRAZED

28

MILITARY

HADC674ZCCU

12-BITRESADC; II-BIT LIN '

DIE

HADC874ZACN

12-BIT RES ADO; 12-BITLIN ,

PLASTIC·

28

COMMERCIAL

HADC874ZBCN

12-BIT RES ADO; 12-BIT LIN

PLASTIC·

28

COMMERCIAL

HADCl74ZCCN

12-BIT RES ADO; II-BIT LIN

PLASTIC·

28

COMMERCIAL

HADC874ZACJ

12-BIT RES ADO; 12-BIT LIN

SIDEBRAZED

28

COMMERCIAL

HADCl74ZBCJ

12-BIT RI:SADO; 12-BIT LIN

SIDEBRAZED

28

COMMERCIAL

HADC874ZCCJ

12-BIT RESADC; II-BIT LIN

SIDEBRAZED

28

COMMERCIAL

HADC874ZAMJ

12-BIT RES ADc; 12-BIT LI N

SIDEBRAZED

28

MILITARY

HADC874ZBMJ

12-BIT RES ADO; 12-BIT LI N

SIDEBRAZED

28

MILITARY

HADC874ZCMJ

12-lm RES ADC; II-BIT LIN

SIDEBRAZED

28

MILITARY

042

INDUSTRIAL
MILITARY

+25'C

HADC874ZCCU

12-BIT RES ADC; II-BIT LIN'

DIE

HADC77100A1J

8-BIT, 150 MSPS ADO :t: ~ LSB

SIDEBRAZED

HADC77100AMJ

8-BIT, 150 MSPS ADO :t: V. LSB

SIDEBRAZED

42

HADcmOOAMJlMIL

8-BIT, 150 MSPS ADC :t: V. LSB

SIDEBRAZED

42

MILITARY

HADC771008IJ

8-BIT, 150 MSPS ADO :t: '.4 LSB

SIDEBRAZED

42

INDUSTRIAL

HADC77100BMJ

8-BIT,I50 MSPSADC:t:'.4 LSB

SIDEBRAZED

42

MILITARY

HADC77100AIG

8-BIT, 150 MSPS ADC :t: V. LSB

PGA

46

INDUSTRIAL

HADC77100AMG

8-BIT, 150 MSPS ADO :t: V. LSB

PGA

46

MILITARY

HADC77100AMJlMIL

8-BIT, 150 MSPS ADO :t: V. LSB

PGA

46

MILITARY

HADC77100BIG

8-BIT,150 MSPSADO :t: '.4 LSB

PGA

46

INDUSTRIAL

HADC77100BMG

8-BIT, 150 MSPS ADO :t: '.4 LSB

PGA

46

MILITARY

HADC77200AIJ

8-BIT, 150 MSPS ADO :t: V. LSB

SIDEBRAZED

46

INDUSTRIAL

HADC77200AMJ

8-BIT, 150 MSPS ADO :t: V. LSB

SIDEBRAZED

46

MILITARY

HADC772QOAMGlMIL

8-BIT, 150 MSPS ADO :t: V. LSB

SIDEBRAZED

46

MILITARY

HADC77200BIJ

8-BIT,150 MSPSADC:t: '.4,LSB

SIDEBRAZED

48

INDUSTRIAL

HADC77200BMJ

8-BIT,150 MSPSADC :t: '.4 LSB

SIDEBRAZED

.46

MILITARY

HADC77200AIG

8-BIT, 150 MSPS ADO :t: V. LSB

PGA

46

INDUSTRIAL

+25*0

HADC77200AMG

8-BIT,150 MSPSADO :t: V. LSB

PGA

46

MILITARY

HADC772OOAMJ/MIL

8-BIT, 150 MSPS ADO :t: V. LSB

PGA

46

MILITARY

HADC77200BIG

8-BIT, 150 MSPS ADO :t: '.4 LSB

PGA

46

INDUSTRIAL

HADC77200BMG

8-BIT, 150 MSPS ADO :t: '.4 LSB

PGA

46

MILITARY

HADC77300ACG

8-BIT, 250 MSPS ADC :t: V. LSB

PGA

46

COMMERCIAL

HADC77300BCG

8-BIT, 250 MSPS ADO :t: '.4 LSB

PGA

46

COMMERCIAL

HADC77100BCG

10-BIT, 50 MSPS ADC :t: V. LSB

PGA

72

COMMERCIAL

HADC77IOOSIG

H)-BIT, 50 MSPS ADC :t: V. LSB

PGA

72

INDUSTRIAL

HADC77800SMG

I()'BIT, 50 MSPS ADC :t: V. LSB

PGA

72

MILITARY

HADC78180

CONTACT FACTORY FOR ORDERING INFORMATION

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1·6

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ORDERING INFORMATION
DIGITAL TO ANALOG CONVERTERS
PART NUMBER

DESCRIPTION

PACKAGE TYPE

'PINS

TEMPERATURE

HDAC10180AID

8-BIT, 275 MWPS DAC

CERDIP

24

INDUSTRIAL

HDAC10180AMJ

8-BIT, 275 MWPS DAC

SIDEBRAZED

24

MILITARY

HDAC10180BID

8-BIT, 165 MWPS DAC

CERDIP

24

INDUSTRIAL

HDAC10180BMJ

8-BIT, 165 MWPS DAC

SIDEBRAZED

24

MILITARY

HDAC10181AID

8-BIT, 275 MWPS DAC W/REF

CERDIP

24

INDUSTRIAL

HDAC10181AMJ

8-BIT, 275 MWPS DAC W/REF

SIDE BRAZED

24

MILITARY

HDAC10181BID

8-BIT, 165 MWPS DAC W/REF

CERDIP

24

INDUSTRIAL

HDAC10181BMJ

8-BIT, 165 MWPS DAC W/REF

SIDEBRAZED

24

MILITARY

HDAC340108CJ

3 X 4-BIT DAC, 200 MWPS

SIDEBRAZED

28

COMMERCIAL

HDAC340208CJ

3 X 4-BIT DAC, 100 MWPS

SIDEBRAZED

28

COMMERCIAL

HDACSOSOOACNIQ

12-BIT RES DAC; 12-BIT LIN

PLASTIC·

20

COMMERCIAL

HDACSOIOOACN

12-BIT RES DAC; 12-BIT LIN

PLASTIC·

20

COMMERCIAL

HDAC5O&OOBCN

12-BIT RES DAC; 11-BIT LIN

PLASTIC·

20

COMMERCIAL

HDAC5O&OOAID/Q

12-BIT RES DAC; 12-BIT LIN

CERDIP

20

INDUSTRIAL

HDACSOSOOAID

12-BIT RES DAC; 12-BIT LIN

CERDIP

20

INDUSTRIAL

HDAC5O&OOBID

12-BIT RES DAC; 11-BIT LIN

CERDIP

20

INDUSTRIAL

HDAC5O&OOAMDlQ

12-BIT RES DAC; 12-BIT LIN

CERDIP

20

MILITARY

HDACSOSOOAMD

12-BIT RES DAC; 12-BIT LIN

CERDIP

20

MILITARY

HDAC5O&OOBMD

12-BIT RES DAC; 11-BIT LIN

CERDIP

20

MILITARY

HDAC5O&OOBCU

12-BIT RES DAC; 11-BIT LIN

DIE

HDAC60800AID

14-BIT RES DAC; 14-BIT LIN

CERDIP

28

INDUSTRIAL

HDAC60800BID

14-BIT RES DAC; 13-BIT LIN

CERDIP

28

INDUSTRIAL

HDAC60800AMD

14-BIT RES DAC; 14-BIT LI N

CERDIP

28

MILITARY

HDAC60800BMD

14-BIT RES DAC; 13-BIT LIN

CERDIP

28

MILITARY

HDAC60800BCU

14-BIT RES DAC; 13-BIT LIN

DIE

HDAC60800AID

14-BIT RES DAC; 14-BIT LIN

CERDIP

24

INDUSTRIAL

HDAC60800BID

14-BIT RES DAC; 13-BIT LIN

CERDIP

24

INDUSTRIAL

HDAC60800AMD

14-BIT RES DAC; 14-BIT LI N

CERDIP

24

MILITARY

HDAC60800BMD

14-BIT RES DAC; 13-BIT LIN

CERDIP

24

MILITARY

HDAC60800BCU

14-BIT RES DAC; 13-BIT LIN

DIE

HDAC514008IJ

8-BIT, 385 MWPS DAC W/REF

SIDEBRAZED

24

INDUSTRIAL

HDAC514008MJ

8-BIT, 385 MWPS DAC W/REF

SIDEBRAZED

24

MILITARY

HDAC518008CQ

8-BIT, 165 MWPS DAC

PGA

72

COMMERCIAL

II

+25°C

+25°C

+25°C

HDAC52180SCQ

CONTACT FACTORY FOR ORDERING INFORMATION

HDAC7541ZACN

12-BIT RES DAC; 12-BIT LIN

PLASTIC·

18

COMMERCIAL

HDAC7541ZBCN

12-BIT RES DAC; 11-BIT LIN

PLASTIC·

18

COMMERCIAL

HDAC7541ZAID

12-BIT RES DAC; 12-BIT LIN

CERDIP

18

INDUSTRIAL

HDAC7541ZBID

12-BIT RES DAC; 11-BIT LI N

CERDIP

18

INDUSTRIAL

HDAC7541ZAMD

12-BIT RES DAC; 12-BIT LI N

CERDIP

18

MILITARY

HDAC7541ZBMD

12-BIT RES DAC; 11-BIT LI N

CERDIP

18

MILITARY

HDAC7541ZBCU

12-BIT RES DAC; 11-BIT LI N

DIE

+25°C

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Honeywell

1·7

ORDERING INFORMATION
DIGITAL TO ANALOG CONVERTERS CONTINUED
PART NUMBER

DESCRIPTION

PACKAGE TYPE

'PINS

TEMPERATURE

HDAC7&42AACNIG

12·BIT RES DAC; 12·BIT LIN

PLASTIC·

16

COMMERCIAL

HDAC7&42AACN

12·BIT RES DAC; 12·BIT LIN

PLASTIC·

16

COMMERCIAL

HDAC7542ABCN

12·BIT RES DAC; 11·BIT LIN

PLASTIC·

16

COMMERCIAL

HDAC7542AA1D1G

12·BIT RES DAC; 12·BIT LIN

CERDIP

16

INDUSTRIAL

HDAC7542AA1D

12·BIT RES DAC; 12·BIT LI N

CERDIP

16

INDUSTRIAL

HDAC7542ABID

12·BIT RES DAC; 11·BIT LIN

CERDIP

16

INDUSTRIAL

HDAC7642AAMDIG

12·BIT RES DAC; 12·BIT LiN

CERDIP

16

MILITARY

HDAC7&42AAMD

12-BIT RES DAC; 12·BIT LIN

CERDIP

16

MILITARY

16

MILITARY

16

COMMERCIAL
COMMERCIAL

HDDC7542ABMD

12·BIT RES DAC; 11·BIT LIN

CERDIP

HDAC7542ABCU

12·BIT RES DAC; 11·BIT LIN

DIE

HDAC7543AACNIG

12·BIT RES DAC; 12·BIT LIN

PLASTIC·

HDAC7643AACN

12·BIT RES DAC; 12·BIT LIN

PLASTIC·

16

HDAC7543ABCN

12·BIT RES DAC; 11·BIT LIN

PLASTIC·

16

COMMERCIAL

HDAC7543AAIDIG

12·BIT RES DAC; 12·BIT LIN

CERDIP

16

INDUSTRIAL

HDAC7&43AAJD

12·BIT RES DAC; 12·BIT LIN

CERDIP

16

INDUSTRIAL

HDAC7543ABID

12·BIT RES DAC; 11·BIT LIN

CERDIP

16

INDUSTRIAL

HDAC7643AAMDIG

12·BIT RES DAC; 12·BIT LIN

CERDIP

16

MILITARY

HDAC7543AAMD

12·BIT RES DAC; 12·BIT LIN

CERDIP

16

MILITARY

HDAC7543ABMD

12·BIT RES DAC; 11·BIT LIN

CERDIP

16

MILITARY

HDAC7543ABCU

12·BIT RES DAC; 11·BIT LIN

DIE

HDAC7545AACNIG

12·BIT RES DAC; 12·BIT LIN

PLASTIC·

20

COMMERCIAL

HDAC7545AACN

12·BIT RES DAC; 12·BIT LIN

PLASTIC·

20

COMMERCIAL

HDAC7646ABCN

12·BIT RES DAC; 11·BIT LIN

PLASTIC·

20

COMMERCIAL

HDAC7545AAIDIG

12·.BIT RES DAC; 12·BIT LIN

CERDIP

20

INDUSTRIAL

HDAC7646AA1D

12·BIT RES DAC; 12·BIT LIN

CERDIP

20

INDUSTRIAL

HDAC7545ABID

12·BIT RES DAC; 11·BIT LI N

CERDIP

20

INDUSTRIAL

HDAC7545AAMDIG

12·BIT RES DAC; 12·BIT LIN

CERDIP

20

MILITARY

HDAC7546AAMD

12·BIT RES DAC; 12·BIT LIN

CERDIP

20

MILITARY

HDAC7545ABMD

12·BIT RES DAC; 11·BIT LIN

CERDIP

20

MILITARY

HDAC7646ABCU

12·BIT RES DAC; 11·BIT LIN

DIE

HDAC97000SIJ

a·BIT, 200 MWPS DAC W/REF

SIDEBRAZED

22

INDUSTRIAL

HDAC97000SID

a·BIT, 200 MWPS DAC W/REF

CERDIP

22

INDUSTRIAL

HDAC87000sMJ

8-BIT, 200 MWPS DAC W/REF

SIDEBRAZED

22

MILITARY

HDAM51100scG

125MHz W/512 X a MEMORY

PGA

46

COMMERCIAL

+25'C

+25'C

+ 25'C

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1·8

Honeywell

ORDERING INFORMATION
COMPARATORS
PART NUMBER

DESCRIPTION

PACKAGE TYPE

II PINS

TEMPERATURE

HCMP88850SID

HIGH SPEED COMPARATOR

CERDIP

16

INDUSTRIAL

HCMP888&OSCU

HIGH SPEED COMPARATOR

DIE

+25'C

HCMP88870AID

DUAL HIGH SPEED COMPARATOR

CERDIP

16

INDUSTRIAL

HCMP88870AIC

DUAL HIGH SPEED COMPARATOR

LCC

20

INDUSTRIAL

HCMP88870AIJ

DUAL HIGH SPEED COMPARATOR

SIDEBRAZED

16

INDUSTRIAL

HCMP88870ACU

DUAL HIGH SPEED COMPARATOR

DIE

HCMP88800

CONTACT FACTORY FOR ORDERING INFORMATION

I

+25'C

INSTRUMENTATION AMPLIFIER
PART NUMBER

DESCRIPTION

PACKAGE TYPE

II PINS

TEMPERATURE

HINA622AIJ

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

14

INDUSTRIAL

HINA622BIJ

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

14

INDUSTRIAL

HINA522BMJ

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

14

MILITARY

HINA622BCU

INSTRUMENTATION AMPLIFIER

DIE

HINA524A1J

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

16

INDUSTRIAL

HINA524BIJ

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

16

INDUSTRIAL

HINA624CIJ

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

16

INDUSTRIAL

HINA524CMJ

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

16

MILITARY

HINA624CCU

INSTRUMENTATION AMPLIFIER

DIE

HINA824AIJ

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

16

INDUSTRIAL

HINA824BIJ

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

16

INDUSTRIAL

HINA824CIJ

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

16

INDUSTRIAL

HINA824CMJ

INSTRUMENTATION AMPLIFIER

SIDEBRAZED

16

MILITARY

HINA824CCU

12-BIT INSTRUMENTATION AMPLIFIER

DIE

+25'C

+25'C

+25'C

SPECIAL FUNCTIONS
PART NUMBER

DESCRIPTION

HTHA27140

CONTACT FACTORY FOR ORDERING INFORMATION

PACKAGE TYPE

II PINS

TEMPERATURE

HSCF24040ACN

7 POLE LOW PASS SC FILTER

HSCF24040ACJ

7 POLE LOW PASS SC FILTER

PLASTIC'

32

COMMERCIAL

SIDEBRAZED

32

HSCF24040AMJ

COMMERCIAL

7 POLE LOW PASS SC FILTER

SIDEBRAZED

32

HSCF24040CCU

MILITARY

7 POLE LOW PASS SC FILTER

DI,E

+25'C

EVALUATION BOARDS
PART NUMBER

DESCRIPTION

EB100A

HADC77100AIJ DEMO BOARD

EB100B

HADC77100BIJ DEMO BOARD

EB101A

HADC77200AIJ DEMO BOARD

EB101B

HADC77200BIJ DEMO BOARD

EB102A

CLC221 BUFFER BOARD

EB102B

CLC231 BUFFER BOARD

EB103

HADC77200/77300 PING-PONG BOARD

EB104

HADC574 DEMO BOARD

EB105

HsCF24040 DEMO BOARD

'HONEYWELL RESERVES THE RIGHT TO SHIP CERDIP IN LIEU OF PLASTIC PACKAGES,

Honeywell

1-9

I

1-10

Honeywell

SELECTION GUIDE, CROSS REFERENCE
ORDERING INFORMATION

II

DIGITAL TO ANALOG CONVERTERS

COMPARATORS

INSTRUMENTATION AMPLIFIERS

Ii

SPECIAL FUNCTIONS

P

EVALUATION BOARDS

':1

APPLICATIONS INFORMATION

E1

QUALITY ASSURANCE

Honeywell

PACKAGE OUTLINES

1[':

SALES OFFICES AND
REPRESENTATIVES

III
2·1

2·2

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HADC574Z

FAST, COMPLETE 12-BIT f.1P COMPATIBLE
AID CONVERTER WITH SAMPLE/HOLD
PRELIMINARY INFORMATION

FEATURES:

APPLICATIONS:

• IMPROVED PIN·TO·PIN COMPATIBLE
MONOLITHIC VERSION OF THE HI574A
AND AD574A
• Complete 12·blt AID Converter with
Sample·Hold, Reference and Clock

• MILITARY/INDUSTRIAL DATA
ACQUISITION SYSTEMS
• 8 OR 12-b~ I!P Input Functions
• Process Control Systems
• Test And Scientific Instruments.
• Personal Computer Interface

• Low Power Dissipation (150mW Max)

• 12·bit Linearity (over temp)
• 251!S Max Conversion Time
• No Negative Supply Required
• Full Bipolar and Unipolar Input Range

GENERAL DESCRIPTION
The HADC574Z is a complete, 12-bit successive
approximation AID converter. The device is integrated
on a single die to make it the first monolithic CMOS
version of the industry standard device, HI574A and
AD574A. Included on chip is an internal reference,
clock, and a sample and hold. The S/H is an additional
feature not available on similar devices.
The HADC574Z features 25~ (Max) conversion time
of 10 or 20 Volt input signals. Also, a 3-state output
buffer is added for direct interface to an 8-, 12-, or 16-

The BEMOS process and monolithic construction
reduces power consumption, ground noise, and
keeps parasitics to a minimum. In addition, the thin film
option on this process allows active adjustment of
DAC and comparator offsets, linearity errors, and gain
errors.
The HADC574Z has standard bipolar and unipolar
input ranges of 10V and 20V that are controlled by a
bipolar offset pin and laser trimmed for specified
linearity, gain and offset accuracy.

bit~Pbus.

The HADC574Z is manufactured on Honeywell SPT's
Bipolar Enhanced CMOS process (BEMOS) which
combines CMOS logic and fast bipolar npn transistors
to yield high performance digital and analog functions
on one chip.

BLOCK DIAGRAM

L88
STS 0811 DB10 OBI DBI DBT DB6 D85 DB4 DB3 DB2 D81 DIll DGND

YLQOIC

Honeywell

Power requirements are +5V and +12V to +15V with a
maximum dissipation of 150mW at the specified
voltages. Power consumption is about five times lower
than currently available devices, and a negative power
supply is not needed.

ufi Cf

Ao

w!

CE

vee

FEF AOND REF VEE .P UN'
.ouT
IN
OFF IN

aov
IN

2-3

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25°C
Supply Voltages
PositiveSupplyVoltage(VCC to DGND) ... Oto+16.5V
Logic Supply Voltage (VLOGIC to DGND) ........... Oto +7V
Analog to Digital Ground (AGND to DGND) ...-O.5 to +1V
Input Voltages
Control Input Vo..!!age~(to DGND).
(CE, CS, Ao, 1218, R/C) .................. -O.5to VLOGIC +O.5V
Analog Input Voltage (to AGND) ..........................±16.5V
(REF IN, BIP OFF, 10Vin)
20V Yin Input Voltage (to AGND) ............................±24V

Output
Reference Output Voltage ......... lndefinite short to GND
Momentary short to VCC
Temperature
Operating Temperature, ambient.-55 to +125(case) 0c
junction .....................+1750C
Lead Temperature, (soldering 10 seconds) ....... +300 0c
Storage Temperature ...............................-65 to +1500C
Power Dissipation ............................................ 1OOOmW
Thermal Resistance (ejA) ................................. .480C/W

Notes:

1. Operation at any Absolute Maximum Rating is not implied. See Operating Conditions for proper nominal applied
conditions in typical applications.

COMMERCIAL TEMPERATURE RANGE

0 TO +70oC

Typical @ +250C, VCC = +15V or +12V, VLOGIC = +5V, Unless otherwise specified.
PARAMETER

TEST
CONDITIONS

TEST
LEVEL

HADC574ZCC

HADC574ZBC

HADC574ZAC

MIN TYP MAX

MIN TYP MAX

MIN TYP MAX

UNITS

DC ELECTRICAL CHARACTERISTICS
Resolution

12

12
±1

12 BITS

±1
2

±1
2

LSB

±1
2

±1
2

LSB

Linearity Error

Tminto Tmax

I

Differential Linearity Error

Tminto Tmax

I

Unipolar Offset

Adjustable to zero

I

Bipolar Offset 1

Adjustable to zero

I

±10

±4

±4 LSB

I

0.3

0.3

0.3 %ofFS

Full Scale Calibration Error!

±1

±.1

±2

±.1

±2

±.1

±2 LSB

No adjustment at

+2S0C

II

0.5

0.4

0.35

%ofFS

+2SoC

II

0.22

0.12

0.05

%ofFS

Tmin to Tmax
With adjustment at
TmintoTmax

Temperature Coefficients

Using intemal
reference

Unipolar Offset

I

Bipolar Offset

I

Full Scale Calibration

I

±.2
±.2

±2
(10)
±2
(10)
±9
(45)

± .1

±1
(5)

± .1

±1
(5)
±5
(25)

±1
(5)
±.1 ±1
(5)
±2
(10)

±.1

LSB
(ppmJOC)
LSB
(ppmJOC)
LSB
(ppmJOC)

Note1: Fixed 50n resistor from REF OUTto REF IN and REF OUTto BIP OFF.

2-4

Honeywell

COMMERCIAL TEMPERATURE RANGE 0 TO +70oC
Typical @+250C,VCC=+15Vor+12V, VLOGIC=+5V, UnlessotherwisespecWied.
TEST
CONDITIONS

PARAMETER

TEST
LEVEL

HADC574ZCC

HADC574ZBC

HADC574ZAC

MIN TYP MAX

MIN TYP MAX

MIN TYP MAX

UNITS

DC ELECTRICAL CHARACTERISTICS
Power Supply Rejection

Max change in full
scale calibration

+13.5V

'c

.\

DATA VALID

DB11·DBO

3.0 1.8

20

lHS

~ATAVAUD

2.4

20

~N

f9~ r
DATAVAUD>

1.8

}-

HIGH~Z

Figure 4 • High Pulse For RIC· Outputs
Enabled While RIC is High, Otherwise
High Impedance
TEST LEVEL

TEST PROCEPURE

I

Production tested at the specijied
conditions.

II

Parameter is guaranteed by design
and sampled characterization data.

Unless otherwise noted, all tests are pulsed tests, therefore
Tjunc = Tcase =Tambient·

Honeywell

2-11

DEFINITION OF SPECIFICATIONS
INTEGRAL LINEARITY ERROR

MISSING. CODES

Linearity error refers to the deyiation of each individual
code from a line drawn from "zero" through "full scale"
with all offset errorS nulled out (See Figure 5 and 7).:
The point used as ":zero" occurs 1/2LSB (1.22mVfor a
10 Volt span) before the first code transistion (all zeros
to only the LSB "on"). "Full scale" is defined as a level
1 and 112LSB beyond the last code transition (to all
ones). The deviation of a code from the true straight
line is measured from the: middle of each particular
code.

Missing codes represent a special kind of. differential
nonlinearity. The quantization step width for a missing
code is 0 LSB, which· re.sults in a differential nonlinearity of-1 LSB, Figure 7 points out two missed
codes in the transferfunetion.

The HADC574Z A and B grades are guaranteed for
maximum nonfinearity of ±1/2LSB. For these grades,
this means that an analog value which falls exactly in
the center of a given code width will result in the
correct digital output code. Values nearer the upper or
lower transition of the code width may produce the
next upper or lower digital output code. The
HADC574ZCC and CM grades are guaranteed to
±1LSB maximum error. For these grades, an analog
value which falls within a given code width will resuH in
either the correct code for that region or either
adjacent one. The linearity is not user-adjustable.
DIFFERENTIAL LINEARITY ERROR
(NO MISSING CODES)
A specification which guarantees no missing codes
requires that every code combination appear in a
monotonically increasing sequence as the .analog
input level is increased. Thus every code must have a
finite width. For theHADC574Z type BC, AC, BM, and
AM grades; which guarantee no missing codes to 12bit resolution, all 4096 codes must be present over the
entire operating temperature ranges. The HADC574Z
CC and CM grades guarantee no missing codes to 11bit resolution over temperature; this means that all
code combinations of the upper 11 bits must be
present; in practice, very few of the 12-bit codes are
missing.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is a measure of how much the
actual quantization step width varies from the ideal step
width of 1 LSB. Figure' 7 shows a differential
nonlinearity of 2 LSB - the actual step width is 3 LSB.
The HADC574Z's specification gives the worst case
differential nonlinearity in the AID transfer function
under specified dynamic operating conditions. Small,
localized differential nonlinearities may be Insignificant
when digitizing full scale signals. However, if a low level
input signal happens to fall on that part of the AID
transfer function with the differential nonlinearity error,
the effect will be significant.

2·12

(1'put

Input Voltage

Figure 5· Static Input Conditions
QUANTIZATION UNCERTAINTY
Analog-to-digital converters exhibit an inherent
quantization uncertainty of ±1/2LSB. This uncertainty
is a fundamental characteristic of the quantization
process and cannot be reduced for a converter of a
given resolution.
QUANTIZATION ERROR
Quantization error is the fundamental, irreducible error
associated with the perfect quantizing of a continuous
(analog) signal into a finite number of digital bits (AID
transfer function). A 12-bit AID converter can represent an input voHage with a best case uncertainty
of 1 part.in 212 (1 part i,n 4096) .. In real AIDs under
dynamic operating conditions, the quantization bands
(bit change step vs input amplitude) for certain codes
can be significantly larger (or smaller) than the ideal.
The ideal width of each quantization step (or band) is
Q = FSR/2N where FSR =' full scale range and N = 12.
Non- ideal quantization bands represent differential
nonlinearity errors (See Figures 5, 6 and 7).
RESOLUTION· ACTUAL VS. AVAILABLE
The available resolution of an N-bit converter is 2N.
This means it is theoretically posssible to generate 2N
unique output codes.

Honeywell

GAIN
The slope of the transfer curve. Gain is generally user
adjustable to compensate for long term drift.
111

ACQUISITION TIME/APERTURE DELAY TIME
tOt

In the HADC574Z, this is the time delay between the
Ric falling edge and the actual start of the HOLD
mode in a sample and HOLD function.

[
tDO

APERTURE JITTER
A specification indicating how much the aperture delay
time varies between samples.
DOD

SUCCESSIVE APPROXIMATION ADC
D.I

1.1

U

,.I ... ... ...

ANALOG INPUT VOLTAGE

Figure 6· Quantizing error

-

The successive approximation converter uses an
architecture with inherently high throughput rates
which converts high frequency signals with great
accuracy. A sample and hold type circuit can be used
on the input to freeze these signals during
conversion.
An N-bit successive approximation converter performs
a sequence of tests comparing the input voltage to a
successively narrower voltage range. The first range is
half full scale, the next is quarter full scale, etc., until it
reaches the Nth test which narrows it to a range of
1/2N of full scale. The conversion time is fixed by the
clock frequency and is thus independent of the input
voltage.

output

UNIPOLAR OFFSET

Input v......

Figure 7· Dynamic Conditions

The first transition should occur at a level 1/2LSB
above analog common. Unipolar offset is defined as
the deviation of the actual transition from that point.
This offset can be adjusted as discussed on the
following pages. The unipolar offset temperature
coefficient specifies the maximum change of the
transition point over temperature, with and without
extemal adjustment.

BIPOLAR OFFSET
THROUGHPUT
Maximum throughput is the greatest number of
conversions per second at which an ADC will deliver its
full rated performance. This is equivalent to the
inverse of the sum of the multiplex time (if applicable),
the SlH settling time and the conversion time.

Honeywell

In the bipolar mode, the major carry transition (0111
1111 1111 to 1000 0000 0000) should occur for an
analog value 1/2LSB below analog common. The
bipolar offset error and temperature coefficient specify
the initial deviation and maximum change in the error
over temperature.

2-13

II

CONVERSION TIME

MONOTONICITY

The time required to complete a conversion over the
specified operating range. Conversion time can be
expressed as time/bit for a converter with selectable
resolution or as time/conversion when the number of
bits is constant. The HADC574Z is. specified as
time/conversion for all 12-bits. Conversion time should
not be confused with maximum allowable analog input
.
frequency which is discussed later.

This characteristic describes art aspect of the code to
code progression from minimum to maximum input. A
device is said to be monotonic if the output code
continuously increases as the input signal increases
and if the output code continuously decreases as th~
input signal decreases. Figure 7 demonstrates nonmonotonic behavior.

FULL SCALE CALIBRATION ERROR
The last transition (from 1111 1111 1110 to 1111
1111 1111 1111) should occur for an analog value 1
and 1/2LSB below the nominal full scale (9.9963 Volts
for 10.000 Volts full scale). The full scale calibration
error is the deviation of the actual level at the last
!ransition from the ideal level. This error, which typically
IS O.OS to 0.1% of full scale, can be trimmed out as
shown in Figures 11 and 12. The full scale calibration
error over temperature is given with and without the
initial error trimmed out. The temperature coefficients
for each grade indicate the maximum change in the full
scale gain from the initial value using the internal 10
Volt reference.

TEMPERATURE COEFFICIENTS
The temperature coefficients for full scale calibration
unipolar offset, and bipolar offset specify the maxi~um
change from the initial (25 0 C) value to the value at Tmin
orTmax .

POWER SUPPLY REJECTION
The standard specifications for the HADCS74Z
assume +5.00 and +1S.00 or +12.00 Volt supplies.
The only effect of power supply error on the
performance of the device will be a small change in the
full scale calibration. This will result in a linear change in
all lower order codes. The specifications show the
maximum change in calibration from the initial value
with the supplies at the various limits.

CODE WIDTH
A fundamental quantity for NO converter specifications is the code width. This is defined as the range
of analog input values for which a given digital output
code will occur. The nominal value of a code width is
equivalent to 1 least significant bit (LSB) of the full
scale range or 2.44mV out of 10 Volts for a 12-bit ADC.

·LEFT·JUSTIFIED DATA
The data format used in the HADCS74Z is left-justified.
This means that the data represents the analog input
as a fraction of full scale, ranging from 0 to 409S/4096.
This implies a binary point to the left of the MSB.

2·14

CIRCUIT OPERATION
The HADCS74Z is a complete 12-bit Analog-To-Digital
converter which consists of a single chip version of the
industry standard 574. This single chip contains a
precision 12-bit capacitor digital-to-analog converter
(CDAC) with voltage reference, comparator, successive approximation register (SAR) , sample & hold,
clock, output buffers and control circuitry to make it
possible to use the HADC574Z with few external
components.
When the control section of the HADC574Z initiates a
conversion command, the clock is enabled and the
successive-appl'()ximation register is reset to all zeros.
Once the conversion cycle begins, it can not be
stopped or re-started and data is not available from the
output buffers.
The SAR, timed by the clock, sequences through the
conversion cycle and returns an end-of-convert flag to
the control section of the ADC. The clock is then
di.sabled by the control section, the output status
goes low, and the control section is enabled to allow
the data to be read by external command.
The internal HADC574Z 12-bit CDAC is sequenced by
the SAR starting from the MSB to the LSB at the
beginning of the conversion cycle to provide an
output voltage from the CDAC that is equal to the
input signal voltage (which is divided by the input
voltage divider network). The comparator determines
whether the addItion of each successively-weighted
bit volt.age causes the CDAC output voltage
~ummatlon to be greater or less than the input voltage;
If the sum is less, tt"\e bit is left on; if more, the bit is
turned off. Aftertesting all the bits, the SAR contains a
12-bit binary code which accurately represents the
input signal to within ±1/2 LSB.
The internal reference provides the voltage reference
to the CDAC with excellent stability overtemperature
and time. The· reference is trimmed to 10.00 Volts
±1% and can supply up to 2mA to an external load in
ad~ition to .that required to drive· the reference input
resistor (1 mAl and offset resistor (1mA) when
operating with ±15V supplies. If the HADC574Z
is used with ±12V supplies, or if external current must
be supplied over the full temperature range, an

.HoneyweU

extemal buffer amplifier is recommended. Any
external load on the HADC574Z reference must
remain constant during conversion.
The sample and hold feature is a bonus of the CDAC
architecture. Therefore the majority of the S/H specifications are included within the AID specifications.
Although the sample-and-hold circuit is not implemented in the classical sense, the sampling nature of
the capacitive DAC makes the HADC574Z appear to
have a built in sample-and-hold. This sample-and-hold
action sUbstantially increases the signal bandwidth of
the HADC574Z over that of similar competing devices.
Note that even though the user may use an external
sample and hold for very high frequency inputs, the
internal sample and hold still provides a very useful
isolation function. Once the internal sample is taken
by the CDAC capacitance, the input of the HADC574Z
is disconnected from the user's sample and hold. This
prevents transients occuring during conversion from
being inflicted upon the attached sample and hold
buffer. All other 574 circuits will cause a transient load
current on the sample and hold which will upset the
buffer output and may add error to the conversion
itself.
Fu rthermore, the isolation of the input after the
acquisition time in the HADC574Z allows the user an
opportunity to release the hold on an external sample
and hold and start it tracking the next sample. This will
increase system throughput with the user's existing
components.

SAMPLE AND HOLD FUNCTION
When using an external S/H, the HADC574Z
acts as any other 574 device because the
Internal S/H is transparent. The sample/hold
function in the HADC574Z is inherent to the capacitor
DAC structure, and its timing characteristics are
determined by the internally generated clock. However, for limited frequency ranges, the internal S/H
may eliminate the need for an external StH. This
function will be explained in the next two sections.
The operation of the S/H function is internal to the
HADC574Z and is controlled through the normal RIC
control line (refer to Figure 8.) When the RIC line
makes a negative transition, the HADC574Z starts the
timing of the sampling and conversion. The first 2
clock cycles are allocated to signal acquisition of the
input by the CDAC (this time is defined as T apq).
Following these two cycles, the input sample is taken
and held. The AID conversion follows this cycle with

Honeywell

the duration controlled by the internal clock cycle.
During Tacq' the equivalent circuit of the HADC574Z
in-put is as shown in Figure 9 (the time constant of
the input is independant of which input level is used.)
This CDAC capacitance must be charged up to the
input voltage during Tacq. Since the CDAC time
constant is 100 nsecs., there is more than enough time
for settling the input to 12 bits of accuracy during Ta9Q.
The excess time left during Tacg allows the user's buffer
amp to settle after being switched to the CDAC load.
Note that because the sample is taken relative to the
RIC transition, T acq is also the traditional "aperture
delay" of this internal sample and hold.
Since T aCQ is measured in clock cycles, its duration will
vary with the intemal clock frequency. This results in
Tacq = 2.4 j.lSecs ± 0.6 Ilsecs. between units and over
temperature.
Offset, gain and linearity errors of the S/H circuit, as well
as the effects of its droop rate, are included in the
overall specs for the HADC574Z.

APERTURE UNCERTAINTY
Often the limiting factor in the application of the sample
and hold is the uncertainty in the time the actual sample
is taken - I.e. the "aperture jitter" or TAJ.
The
HADC574Z has a nominal aperture jitter of 20 nsecs.
between samples. With this jitter, it is possible to
accurately sample a wide range of input signals.
The aperture jitter causes an amplitude uncertainty for
any input where the voltage is changing.
The
approximate voltage error due to aperture jitter depends
on the slew rate of the signal at the sample point (See
Figure 10). The magnitude of this change for a sinewave can be calculated:
Assume a sinusoidal Signal, maximum slew rate, Sr =
27tfVp (Vp = peak voltage, f = frequency of sine wave)
For an N-bitconverterto maintain +1-1/2 LSB accuracy:
Verr ~ VfS/2N+1 (where Verr is the allowable error
voltage and Vfs is the full scale voltage)
From Figure 10:
Sr= aVI aT= 27tfVp
Let aV = Verr = Vfs2 - (N+l), Vp = Vin/2 and aT = tAJ
(the time during which unwanted voltage change
occurs)
The above conditions then yield:

2-15

lEI

VfS/2N+1 :il:1tfVintAJ or f max SVfsl(7tVintAJ)2N+1
Forthe HADC574Z, TAJ = 20 nsec,
therefore f max S 2KHz.
For higher frequency signal inputs, an extemal sample
and hold is recommended.

--'I

,,'-------

co _ _

Mi~.... )
.....111100

n ••

WAIT FOR BUS

REA.

V'N

ClJACYOLTAOE

~"'"""'_''''''''''IlII1A.''''''.IIXTCOIMRT

_~OV~~~~_~~_~

,

Figure 8 - Sample and Hold Function

25 pf

TYPICAL INTERFACE CIRCUIT
The HADC574Z is a complete AID converter that is
fully operational when powered up and issued a Start
Convert Signal. Only a few external components are
necessary as shown in Figu res 11 and 12. The two
typical interface circuits are for .operating the
HADC574Z in either a unipolar or bipolar input mode.
Further information is given in the following sections
on these connections, but first a few considerations
concerning board layout to achieve the best operation .
For each application of this device, strfct attention must
be given to power supply decoupling, board layout (to
reduce pickup between analog and digital sections),
and grounding. Digital timing, calibration and the
analog signal source must be considered for correct
operation.
To achieve specified accuracy, a double-sided printed
circuit board with a copper ground plane on the
component side is recommended. Keep analog signal
traces away from digital lines. It is best to lay the P.C.
board out such that there is an analog section and a
digital section with a single point ground connection
between the two through an RF bead. If this is not
poSSible, run analog signals between ground traces
and cross digital lines at right angles only.
POWER SUPPLIES

R eq

= 4K ohms at any range

't = Req Ceq = 100 nsec.

Figure 9 - Equivalent HADC574Z
Input Circuit

"I};t~
I I
I I
-1 r-At

AV error

The supply voltages for the HADC574Z must be kept
as quiet as possible from noise pickup and also
regulated from transients or drops. Because the part
has 12-bit accuracy, voltage spikes on the supply lines
can cause several LSB deviations on the output.
Switching power supply noise can be a problem.
Careful filtering and shielding should be employed to
prevent the noise from being picked up by the
converter.
Capacitor bypass pairs are needed from each supply
pin to it's respective ground to filter noise and counter
the problems caused by the variations in supply
current. A 10J.LF tantalum and a 0.1 J.LF ceramic type in
parallel between VLOGIC (pin1) and digital common
(pin15), and Vee (pin 7) and analog com~on (pin 9) is
sufficient. VEE is generated intemally so pin'11 may be
grounded or connected to a negative supply if the
HADC574Z is being used to upgrade an already
existing design.

= 4t ,:,V

Figure 10 - Aperture Uncertainty

2-16

Honeywell

GROUNDING CONSIDERATIONS
Any ground path from the analog and digital ground
should be as low resistance as possible to
accomodate the ground currents present with this
device.
The analog ground current is approximately 6mADC
while the digital ground is 3mADC. The analog and
digital common pins should be tied together as close
to the package as possible to guarantee best
performance. The code dependant currents flow
through the VLOGIC and Vcc terminals and not through
the analog and digital common pins.
The HADC574Z may be operated by a IlP or in the
stand-alone mode. The part has four standard input
ranges: OV to +10V, OV to +20V, ±5V and ±10V. The
maximum errors that are listed in the specifications for
gain and offset may be adjusted externally to zero as
explained in the next two sections.

CALIBRATION AND
CONNECTION PROCEDURES
UNIPOLAR
The calibration procedure consists of adjusting the
converter's most negative output to its ideal value for
offset adjustment, and then adjusting the most
positive output to its ideal value for gain adjustment.
Starting with offset adjustment and referring to Figure
11, the midpoint of the first LSB increment should be
poSitioned at the origin to get an output code of all Os.
To do this, an Input of +1/2LSB or +1.22mV for the
10V range and +2.44mV for the 20V range should be
applied to the HADC574Z. Adjust the offset
potentiometer R1 for code transition flickers between
0000 0000 0000 and 0000 0000 0001.
The gain adjustment should be done at positive full
scale. The ideal input corresponding to the last code
change is applied. This is 1 and 1/2LSB below the
nominal full scale which is +9.9963V for the 10V range
and +19.9927V for the 20V range. Adjust the gain
potentiometer R2 for flicker between codes 1111
1111 1110 and 1111 1111 1111. If calibration is not
necessary for the intended application, replace A1
with a 50n, 1% metal film resister and remove the
network from pin 12. Connect pin 12 to pin 9.
Connect the analog input to pin 13 for the OV to 10V
range or to pin 14 for the OV to 20V range.
BIPOLAR

The gain and offset errors listed in the specifications
may be adjusted to zero using the potentiometers A 1

Honeywell

and A2 (See Figure 12). If adjustment is not needed,
either or both pots may be replaced by a 50n, 1%
metal film resistor.
To calibrate, connect the analog input signal to pin 13
for a ±5V range or to pin 14 for a ±10V range. First
apply a DC input voltage 1/2LSB above negative full
scale which is -4.9988V for the ±5V range or 9.9976V for the ±10V range. Adjust the offset
potentiometer A1 for flicker between output codes
0000 0000 0000 and 0000 0000 0001. Next, apply a
DC input voltage 1 and 1/2LSB below positive full
scale which is +4.9963V for the ,±5V range or
+9.9927V for the ±10V range. Adjust the gain
potentiometer A2 for flicker between codes 1111
11111110and111111111111.
ALTERNATIVE

The 100n potentiometer R2 provides gain adjust for
the 10V and 20V ranges. In some applications, a full
scale of 10.24V (for an LSB of 2.5mV) or 20.48V (for
an LSB of 5.0mV) is more convenient. For these,
replace A2 by a 50n, 1% metal film resistor. Then to
provide gain adjust for the 10.24V range, add a 200n
potentiometer in series with pin 13. For the 20.48V
range, add a 1000n potentiometer in series with pin
14.

CONTROLLING THE HADC574Z
The HADC574Z can be operated by most
microprocessor systems due to the control input pins
and on-chip logic. It may also be opermed in the
"stand-alone" mode and enabled by the RIC input pin.
Fu" j.1P control consists of selecting an 8 or 12-bit
conversion cycle, initiating the conversion, and
reading the output data when ready. The output read
has the options of choosing either 12-bits at once or 8
followed by 4-bits in a left-justified format. A" five
control inputs a@ TTUCMOS compatible and include
1218, CS, Ao, AIC and CE). The use of these inputs in
controlling the converter's operations is shown in
Table 1, and the internal control logic is shown in a
simplified schematic in Figure 13.
STAND-ALONE OPERATlON
T~

simplest interface is a control line connected to

A/C. The other controls must be tied to known states
as follows: CE and 12m are wired high, Ao and CS are
wired low. The output daJ!! arrives in words of 12-bits
each. The limits on AIC duty cycle are shown in
Figures 3 and 4. It may have duty cycle within and
including the extremes shown in the specifications on
the pages. In general, data may be read when RIC is
high unless STS is also high, indicating a conversion
is in progress.

2-17

CONVERSION LENGTH

A conversion start transition latches the state of Ao as
shown in Figure 13 and Table 1. The latched state
determines if the conversion stops with 8-bits (Ao
high) or continues for 12-bits (Ao lOw). If all 12-bits are
read following an 8-bit conversion, the three LSB's will
be a logic ·0" and DB3 will be a logic "1". Ao is latched
because it is also involved in enabling the output
buffers as will be explained later. No other control
inputs are latched.

amour"",

.,

..v

"., .1,.

·lIV

I ... ,OV

,,..

,_

"""""
......

a"IOY

...

tIV

mp

14

OFF 'I

Figure 11 • Unipolar Input Connections
0UIPUT1I11I

....

Figure 12 • Bipolar Input Connections

2-18

Honeywell

CONVERSION START
A conversion may be initiated by a logic transition ~n
any of the three inputs: CE, CS, RiC, as shown In
Table 1. The last of the three to reach the correct state
starts the conversion, so one, two or all three may be
dynamically controlled. The nominal delay from each is
the same and all three may change state
simultaneously. In order to assure that a particular
input controls the start of conversion, the other two
should be setup at least SOns earlier. Refer to the
convert mode timing specifications. The Convert Start
timing diagram is illustrated in Figure 1.
The output signal STS is the status flag and .goes hig.h
only when a conversion is in progress. While STS IS
high the output buffers remain in a high impedance
stat~ so that data can not be read. Also, when STS is
high, an additional Start Convert will not res~t the
converter or reinitiate a conversion. Note, If Ao
changes state after a conversion begins, an additional
Start Convert command will latch the new state of Ao
and possibly cause a wrong cycle length for that
conversion (8 versus 12-bits).
READING THE OUTPUT DATA
The output data buffers remain in a high impeda.!!~e
state until the following four conditions are met: RIC IS
high, STS is low, CE is high and CS is low. The. ~ata
lines become active in response to the four condltlo~
and output data according to the conditio~s of 12~8
and Ao. The timing diagram for this process IS shown In
Figure 2. When 1278 is high, all 12 data .outpu~s
become active simultaneously and the Ao Input IS
ignored. This i~for easy interface to ~ 12 o.r 16-bit data
bus. The 12/8 input is usually lied high or low,
although it is nUCMOS compatible.

When 12/8 is low, the output is separated into two 8bit bytes as shown below:
BYTE 1

BYTE 2

CE

ell

R/e"

1~8

Ao

0

X

X

X

X

Operation

J:

·Ixxxx xxxx IIXXXX

·1

0000

I

~~I----~

MSB

LSB

This configuration makes it easy to connect to an 8-bit
data bus as shown in Figure 13. The Ao control can be
connected to the least significant bit of the data bus in
order to store the output data into two consecutive
memory locations. When Ao is pulled low, the 8 MSBs
are enabled only. When Ao is high, the 4 MSBs are
disabled, bits 4 through 7 are forced to a zero and the
four LSBs are enabled. The two byte format is "left
justified data" as shown above and can be considered
to have a decimal point or binary to the left of byte 1.
Ao may be toggled without damage to the converter at
any time. Break-before-make action is guaranteed
between the two data bytes. This assures that the
outputs which are strapped together in Figure 13 will
never be enabled at the same time.
In Figure 2, it can be seen that a read operation usual!y
begins after the conversion is complete and S~S IS
low. If earlier access is needed, the read can begin no
later than the addition of times tDD and tHS before STS
goes low.

\ ..

ADDRESS BUS

X

X

X

None

0

0

X

0

Inltlat. 12 bit conversion

0

X

1

Inlt'at. 8 bit conversion

0

X

0

Initiate 12 bit conversion

0

X

1

InItIate 8 bit oonwrelon

X

0

Inftle. 12 bit oonv.... lon

,

1

+

1

0

+
+

1

0

X

1

Inftl.t. 8 bit conversion

1

0

1

1

X

Enable 12 bft Output

1

0

1

0

0

Enable 8 MSS'. Only

1

0

1

0

1

Enable 4 LSB'. Plua 4
Trailing Zeroes

Honeywell

r • ..

DB11 (MSB)

~
27

"
"

'---

24

HADC574Z

1

1

,Vi"

23

X

0

ST.
2

Non.

t
t

-.t

g'"
It)

«

~

Table 1 - Truth Table for the
HADC574Z Control Inputs

N

DATA

aus

22

21
20

"'a
'7

DBO(LSB)
DIQ.
COM.

,.

h

Figure 13 - Interfacing the HADC574Z
to an a-bit Data Bus

2-19

1-1--_
INPu;r BUFFERS

}-6--_

NIBBLE B ZERO
OVERRIDE
NIBBLEA,B

NIBBLEC

Figure 14 - HADC574Z Control Logic
+S.SV
~

...l. +SV
~

1218

3CS'
4

r-1 400HZ "/
LJ L

5
6

+5V - . . ,

OV _

A,

RIC HADC
574Z
CE

+16.SV..!.. +1SV
8 REFOUT
9
10

+SV

~

60HZ "-

.SV-"---"V-

AOND
REF IN

SOfi...ll NlC
12 BlP OFF

81'S
BIT 12

~
~

3.OKn

BIT 11 126
BIT 10 I~R
BIT 9
24
BITS
BIT 7
BIT 6

1~3

BITS
BIT 4
BIT 3

20

22

21

19
18

BIT 2

17

son

13

10VIN

BIT 1

N/C

...!!

20VIN

DONO

.!!...1!.
4.7Kn

COMMON

Figure 15 - Burn-In Schematic

2·20

Honeywell

PIN FUNCTIONS HADC574Z

PIN ASSIGNMENT HADC574Z

N

TOP VIEW

~

r-.

It)

FUNCTION

VLOGIC

Logic Supply Voltage,
Nominally +5V

DB10

12i8

Data Mode Select

Ao

DB9

CS

Chip Select

RIC

DBS

Ao

Byte Address/ Short cycle

DB7

RiC

Read/ Convert

vee

DBS

CE

Chip Enable

REFOUT

DBS

VCC

Analog Positive Supply Vo~age
Nominally +15V

REF OUT

Reference Output
Nominally +1 OV

VLOGIC

STS

1218

DB11

DB4
REF IN

DB3

N/C (VEE)

DB2

BIPOFF

DB1

10VIN
14

(,)

NAME

LSB

AGND

Analog Ground

REF IN

Reference Input

l:

N/C(VEE)

This pin is not connected to the device.

BIPOFF

Bipolar Offset

10VIN

10 Volt Analog Input

20VIN

20V Analog Input

DGND

Digital Ground

DBO

20VIN

c
c(

28 LEAD DIP

•

18

17

18

15

14

13

0

0

0

0

0

0 0

12

19

0

20

0

0

10

21

0

0

8

22

0

0

8

23

0

0

8

24

0

0

0

0

UI

~

i
~

DBO - DB11

0

25

0

0

0

28

27

28

0

0

0

2

3

0
4

11

STS

Digital Data Output
DB11-MSB
DBO-LSB
Status

8

0
5

DIE PLOT
158 MILS

20X

* *For Ordering Information See Section 1.

Honeywell

2-21

NOTES:

2·22

··Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HADC674Z

FAST, COMPLETE 12-BIT JlP COMPATIBLE
AID CONVERTER WITH SAMPLE/HOLD
PRELIMINARY INFORMATION

FEATURES:

APPLICATIONS:

• IMPROVED PIN-TO-PIN COMPATIBLE
MONOLITHIC VERSION OF THE HI674A
• Complete 12-blt AID Convener with
Sample-Hold, Reference and Clock
• Low Power Dissipation (150mW Max)
• Faster Conversion and Pin Compatible w~h HADC574Z
• 12-bit Linearity (over temp)
• 15fJ.S Max Conversion Time
• No Negative Supply Required
• Full Bipolar and Unipolar Input Range

• MILITARYIINDUSTRIAL DATA
ACQUISITION SYSTEMS
• 8 OR 12-b~ I1P Input Functions
• Process Control Systems
• Test And Scientific Instruments
• Personal Computer Interface

11

GENERAL DESCRIPTION
The HADC674Z is a complete, 12-bit successive
approximation AID converter. The device is integrated
on a single die to make it the first monolithic CMOS
version of the industry standard device, H1674A.
Included on chip is an internal reference, clock, and a
sample and hold. The S/H is an additional feature not
available on similar devices.
The HADC674Z features 151ls (Max) conversion time
of 10 or 20 Vott input signals. Also, a 3-state output
buffer is added for direct interface to an 8-, 12-, or 16bit IlP bus.
The HADC674Z is manufactured on Honeywell SPTs
Bipolar Enhanced CMOS process (BEMOS) which
combines CMOS logic and fast bipolar npn transistors
to yield high performance digital and analog functions
on one chip.

The BEMOS process and monolithic construction
reduces power consumption, ground noise, and
keeps parasitics to a minimum. In addition, the thin film
option on this prClcess allows active adjustment of
DAC and comparator offsets, linearity errors, and gain
errors.
The HADC674Z has standard bipolar and unipolar
input ranges of 10V and 20V that are controlled by a
bipolar offset pin and laser trimmed for specified
linearity, gain and offset accuracy.
Power requirements are +5V and + 12V to + 15V with a
maximum dissipation of 150mW at the speCified
voHages. Power consumption is about five times lower
than currently available devices, and a negative power
supply is not needed.

MOB

BLOCK DIAGRAM

VLOCIC

Honeywell

LIB

ITI D811 DB10 DBI DB8 DBl DB& DBI DB4 DBS D82 DB'

,211 Ci

Ao

RIC'

CE

VCC REF AGND fEF VEE ...

our

IN

oao

DONO

1GV'

lIlY

CFFII

IN

2-23

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occut)1 250C
Supply Voltages
PositiveSupplyVoltage{Vcc to DGND) ...Oto+16.5V
Logic Supply VoHage {VLOGIC to DGND) ...........Oto +7V
Analog to Dignal Ground {AGND to DGND) ...-0.5 to +1V
Input Voltages
Control Input Vo.!!age~ (to DGND).
{CE, CS, Ao, 12/8, R/C) .................. -0.5 to VLOGIC +0.5V
Analog InputVoHage {toAGND) ......................... ±16.5V
(REF IN, BIP OFF, 10Vin)
20V Yin Input VoHage (to AGND) ......... ;; ................ ±24V

Output
Reference Output Voltage.: ...... .Indefinite short to GND·
Momentary short to VCC
Temperature
.
Operating Temperature, ambient.-55 to +125{case) °c
.
junction ................... i.+1750C
Lead Temperature, {soldering 10 seconds) .......+300 0c
Storage Temperature ...............................-65 to +150 0c
Power Dissipation............................................1OOOmW
Thermal Resistance (8jAl ..................................480C/W

Notes:

1. Operation at any Absolute Maximum Rating is not implied. See Operating Conditions f()r proper nominal applied
conditions in typical applications.

COMMERCIAL TEMPERATURE RANGE

0 TO +700 C

Typical @ +250 C, VCC =+15V or +12V, VLOGIC =+5V, Unless otherwise specified.
PARAMETER

TEST
CONDITIONS

TEST
LEVEL

HADC674ZCC

HADC674ZBC

HADC674ZAC

MIN TYP MAX

MIN TYP MAX

MINTYP MAX

UNITS

DC ELECTRICAL CHARACTERISTICS
Resolution

12 BITS

12

12
±1

±1
2

±1
2

LSB

±1

±1
2

±1
2

LSB

±2

±.1 ±2

±.1 ±2 LSB

Linearity Error

Tmin10 Tmax

I·

Differential Linearny Error

Tmin10 Tmax

I

Unipolar Offset

Adjustable 10 zero

I

Bipolar Offset 1

Adjustable 10 zero

I

±10

±4

±4 LSB

I

0.3

0.3

0.3 %ofFS

Full Scale Calibration Error1
No adjustment at
+250C

II

0.5

0.4

0.35

%ofFS

+2500

II

0.22

0.12

0.05

%ofFS

±1
(5)
± .1 ±1
(5)
±5
(25)

±.1

±1
(5)
±.1 ±1
(5)
±2
(10)

LSB
(ppmJOC)

TminlOTmax
With adjustment at
Tminto Tmax

Temperature Coefficients

±.1

Using intemal
referenoe

Unipolar Offset

I

Bipolar Offset

I

Full Scale Calibration

I

±.2

±2

±.2

(10)
±2
(10)
±9
(45)

± .1

LSB
(ppmJOC)
LSB
(ppmJOC)

Note 1: Fixed son resistor from REF OUTto REF IN and REF OUTto BIP OFF.

2-24

Honeywell

COMMERCIAL TEMPERATURE RANGE 0 TO +700C
Typical @ +250C, VCC = +15V or +12V, VLOGIC = +5V, Unless otherwise specified.
TEST
CONDmONS

PARAMETER

TEST
LEVEL

HADC674ZCC
MIN TYP MAX

HADC674ZBC

HADC674ZAC

MIN TYP MAX

MIN TYP MAX

UNITS

DC ELECTRICAL CHARACTERISTICS
Power Supply Rejection

Max change in full
scale calibration

+13.5V

<

·1

'HDR

HIGH-Z

DATAVAUD

DB11-DBO

Figure 3 - Low Pulse For RIC - Outputs
Enabled After Conversion

1.4

Ie

t HS

~ATAVAUD

1.8 1.0

20

20

~N

~r f1
DATAVAUD>

1.0

Figure 4 - High Pulse For RIC - Outputs
Enabled While RIC is High, Otherwise
High Impedance
TEST LEVEL

TEST PROCEDURE

I

Production tested at the specified
conditions.

"

Parameter is guaranteed by design
and sampled characterization data.

Unless otherwise noted, all tests are pulsed tests, therefore
Tjunc = Tcase = T ambient·

Honeywell

2-31

DEFINITION OF SPECIFICATIONS
INTEGRAL LINEARITY ERROR

MISSING CODES

Linearity error refers to the deviation of each individual
code from a line drawn from "zero" through "full scale"
with all offset errors nulled out (See Figure 5 and 7).
The point used as "zero" occurs 1/2LSB (1.22mV for a
10 Volt span) before the first code transistion (all zeros
to only the LSB "on"). "Full scale" is defined as a level
1 and 1/2LSB beyond the last code transition (to all
ones). The deviation of a code from the true straight
line is measured from the middle of each particular
code.

Missing codes represent a special kind of differential
nonlinearity. The quantization step width for a missing
code is 0 LSB, which results in a differential nonlinearity of -1 LSB. Figure 7 points out two missed
codes in the transfer function.

The HADC674Z A and B grades are guaranteed for
maximum nonlinearity of ±1/2LSB. For these grades,
this means that an analog value which falls exactly in
the center of a given code width will result in the
correct digital output code. Values nearer the upper or
lower transition of the code width may produce the
next upper or lower digital output code. The
HADC674ZCC and CM grades are guaranteed to
± 1LSB maximum error. For these grades, an analog
value which falls within a given code width will result in
either the correct code for that region or either
adjacent one. The linearity is not user-adjustable.
DIFFERENTIAL LINEARITY ERROR
(NO MISSING CODES)
A specification which guarantees no missing codes
requires that every code combination appear in a
monotonically increasing sequence as the analog
input level is increased. Thus every code must have a
finite width. For the HADC674Z type BC, AC, BM, and
AM grades, which guarantee no missing codes to 12bit resolution, all 4096 codes must be present over the
entire operating temperature ranges. The HADC674Z
CC and CM grades guarantee no missing codes to 11bit resolution over temperature; this means that all
code combinations of the upper 11 bits must be
present; in practice, very few of the 12-bit codes are
missing.
DIFFERENTIAL NONLINEARITY
Differential nonlinearity is a measure of how much the
actual quantization step width varies from the ideal step
width of 1 LSB. Figure 7 shows a differential
nonlinearity of 2 LSB - the actual step width is 3 LSB.
The HADC674Z's specification gives the worst case
differential nonlinearity in the AID transfer function
under specified dynamic operating conditions. Small,
localized differential nonlinearities may be insignificant
when digitizing full scale signals. However, if a low level
input signal happens to fall on that part of the AID
transfer function with the differential nonlinearity error,
the effect will be significant.

2-32

(1'put

InputVoltq.

Figure 5 - Static Input Conditions
QUANTIZATION UNCERTAINTY
Analog-to-digital converters exhibit an inherent
quantization uncertainty of ±1/2LSB. This uncertainty
is a fundamental characteristic of the quantization
process and cannot be reduced for a converter of a
given resolution.
QUANTIZATION ERROR
Quantization error is the fundamental, irreducible error
associated with the perfect quantizing of a continuous
(analog) signal into a finite number of digital bits (AID
transfer function). A 12-bit AID converter can represent an input voltage with a best case uncertainty
of 1 part in 212 (1 part in 4096). In real AIDs under
dynamic operating conditions, the quantization bands
(bit change step vs input amplitude) for certain codes
can be significantly larger (or smaller) than the ideal.
The ideal width of each quantization step (or band) is
Q = FSR/2N where FSR = full scale range and N = 12.
Non- ideal quantization bands represent differential
nonlinearity errors (See Figures 5, 6 and 7).
RESOLUTION· .ACTUAL VS.AVAILABLE
The available resolution of an N-bit converter is 2N.
This means it is theoretically posssible to generate 2N
unique output codes.

Honeywell

GAIN

1

The slope of the transfer curve. Gain is generally user
adjustable to compensate for long term drift.
,01

ACQUISITION TIME/APERTURE DELAY TIME

,OIl

In the HADC674Z, this is the time delay between the
RiC falling edge and the actual start of the HOLD
mode in a sample and HOLD function.

APERTURE JITTER
A specification indicating how much the aperture delay
time varies between samples.

000

0.1

1.1

2.1

3.1

4.1

...

8.1

SUCCESSIVE APPROXIMATION ADC

ANALOG INPUT VOLTAGE

Figure 6 - Quantizing error

The successive approximation converter uses an
architecture with inherently high throughput rates
which converts high frequency signals with great
accuracy. A sample and hold type circuit can be used
on the input to freeze these signals during
conversion.
An N-bit successive approximation converter performs
a sequence of tests comparing the input voitage to a
successively narrower voltage range. The first range is
half full scale, the next is quarter full scale, etc., until it
reaches the Nth test which narrows it to a range of
1/2N of full scale. The conversion time is fixed by the
clock frequency and is thus independent of the input
voltage.

Output

Cod..

UNIPOLAR OFFSET

Input Volt_go

Figure 7 - Dynamic Conditions

The first transition should occur at a level 1/2LSB
above analog common. Unipolar offset is defined as
the deviation of the actual transition from that point.
This offset can be adjusted as discussed on the
following pages. The unipolar offset temperature
coefficient specifies the maximum change of the
transition point over temperature, with and without
extemal adjustment.

BIPOLAR OFFSET
THROUGHPUT
Maximum throughput is the greatest number of
conversions per second at which an ADC will deliver its
full rated performance. This is equivalent to the
inverse of the sum of the multiplex time (if applicable),
the SlH settling time and the conversion time.

Honeywell

In the bipolar mode, the major carry transition (0111
1111 1111 to 1000 0000 0000) should occur for an
analog value 1/2LSB below analog common. The
bipolar offset error and temperature coefficient specify
the initial deviation and maximum change in the error
over temperature.

2·33

CONVERSION 11ME

MONOTONICltv

The time required to complete a conversion over the
specified operatlng range. Conversion time can be
expressed as timelbit for a converter with selectable
resolution or as time/conversion when the number of
bits is constant. The HADC674Z is specified as
time/conversion for aU 12-blts. Conversion time should
not be confus~dwith maximum allowable analog input
frequency whlchis~iscussed later.

This characteristic describes an aspect of the code to
code progression from minimum to maximum input. A
device is said to be monotonic if the output code
continuously increases as the input signal increases
and if the output code continuously decreases as th~
input signal decreases. Figure 7 demonstrates nonmonotonic behavior.

FULL SCALE CALIBRATION ERROR
The last transition (from 1111 1111 1110 to 1111
1111 1111 1111) should occur for an analog value 1
and 1/2LSB below the nominal full scale (9.9963 Volts
for10.000Volts full scale). The full scale calibration
error is the deviation· of· the actual level at the last
!ransition from the ideal level. This error, which typically
IS 0.05 to 0.1 % of full scale, can be trimmed out as
shown in Figures 11 and 12. The full scale calibration
error over temperature is given with and without the
initial error trimmed out. The temperature coefficients
for each grade indicate the maximum change in the full
scale gain from the ihitial value using the internal 10
Volt reference.
TEMPERATURE COEFFICIENTS
The temperature cOefficients for full scale calibration
unipolar offset, and bipOlar offset specify the maxi~um
change from theinitilil (250 C) value to the value at Tmln
orTmax .
POWER· SUPPLY REJECTION
The standard specifications for the HADC674Z
assume +5.00 and +15.00 or +.12.00 Volt supplies.
The only effect of power supply error on the
performance of the device will be a small change in the
full scale calibration. Thiswifl result in a linear change in
all lower order codes. The specifications show the
maximum change In Calibration from the initial value
with the supplies at the variQus limits.
.
CODE WIDTH
A fundamental quantity for AID. converter specifications is the code width. This is defined as the range
of analog input values for which a given digital output
code will occur. The nominal value of a code width is
equivalent to 1 least significant bit. (LSB) of the full
scale range or 2.44mV out of 10 Volts for a 12-bit ADC.
LEFT-JUSTIFIED DATA
The data format used in the HADC674Z is left-justified.
This means that the data represents the analog input
as a fraction of full scale, ranging from 0 to 4095/4096.
This implies a binary point to the left of the MSB.

2·34

CIRCUIT OPERATION
The HADC674Z is a complete 12-bit Analog-To-Digital
converter which consists of a single chip version of the
industry standard 674. This single chip contains a
precision 12-bit capacitor digital-to-analog converter
(CDAC) with voltage reference, comparator, successive approximation register (SAR), sample & hold,
cloc~, output buffers and control. circuitry to make it
possible to use the HADC674Z with few external
components.
When the control section of the HADC674Z initiates a
conversion command, the clock is enabled and the
successive-approximation register is reset to all zeros.
Once the conversion cycle begins, it can not be
stopped or re-started and data is not available from the
output buffers.
The SAR, timed by the clock, sequences through the
conversion cycle and returns an end-of-convert flag to
the control section of the ADC. The clock is then
disabled by the control section, the output status
goes low, and the control section is enabled to allow
the data to be read by external command.
The internal HADC674Z 12-bit CDAC is sequenced by
the SAR starting from the MSB to the LSB at the
beginning of the conversion cycle to provide an
output voltage from the CDAC that is equal to the
input signal voltage (which is divided by the input
voltage divider network). The comparator determines
whether the addition of each successively-weighted
bit vo~age causes the CDAC output voltage
~ummatlon to be greater or less than the input voltage;
If the sum is less, the bit is left on; if more, the bit is
turned off. After testing all the bits, the SAR contains a
12-bit binary code which accurately represents the
input signal to within ±1/2 LSB.
The intemal reference provides the voltage reference
to the CDAC with excellent stability over temperature
and time. The reference is trimmed to 10.00 Volts
±1% and can supply up to 2mA to an extemalload in
addition to that required to drive the reference input
resistor (1 rnA) and offset resistor (1 rnA) when
operating with ±15V supplies. If the HADC674Z
is used with ±12V supplies, or if extemal current must
be supplied over the full temperature range, an

Honeywell

extemal buffer amplifier is recommended. Any
external load on the HADC674Z reference must
remain constant during conversion.
The sample and hold feature is a bonus of the CDAC
architecture. Therefore the majority of the S/H
specifications are included within the AID specifications.
AHhough the sample-and-hold circuit is not implemented in the classical sense, the sampling nature of
the capacitive DAC makes the HADC674Z appear to
have a built in sample-and-hold. This sample-and-hold
action substantially increases the signal bandwidth of
the HADC674Z overthat of similar competing devices.
Note that even though the user may use an external
sample and hold for very high frequency inputs, the
internal sample and hold still provides a very useful
isolation function. Once the internal sample is taken
by the CDAC capacitance, the input of the HADC674Z
is disconnected from the user's sample and hold. This
prevents transients occuring during conversion from
being inflicted upon the attached sample and hold
buffer. All other 674 circuits will cause a transient load
current on the sample and hold which will upset the
buffer output and may add error to the conversion
itself.
Furthermore, the isolation of the input after the
acquisition time in the HADC674Z allows the user an
opportunity to release the hold on an external sample
and hold and start it tracking the next sample. This will
increase system throughput with the user's existing
components.

SAMPLE AND HOLD FUNCTION
When using an external S/H, the HADC674Z
acts as any other 674 device because the
Internal S/H Is transparent. The sample/hold
function in the HADC674Z is inherent to the capacitor
DAC structure, and its timing characteristics are
determined by the internally generated clock. However, for limited frequency ranges, the internal S/H
may eliminate the need for an external S/H. This
function will be explained in the next two sections.
The operation of the S/H function is internal to the
HADC674Z and is controlled through the normal RIC
control line (refer to Figure 8.) When the Ric line
makes a negative transition, the HADC674Z starts the
timing of the sampling and conversion. The first 2
clock cycles are allocated to signal acquisition of the
input by the CDAC (this time is defined as Ta9Q)'
Following these two cycles, the input sample is taken
and held. The AID conversion follows this cycle with

Honeywell

the duration controlled by the internal clock cycle.
During Tacq' the equivalent circuit of the HADC674Z
in-put is as shown in Figure 9 (the time constant of
the input is independant of which input level is used.)
This CDAC capacitance must be charged up to the
input voHage during Tacq. Since the CDAC time
constant is 100 nsecs., there is more than enough time
for settling the input to 12 bits of accuracy during Tagq.
The excess time left during Tacg allows the user's buffer
amp to settle after being switched to the CDAC load.
Note that because the sample is taken relative to the
RIC transition, Tacq is also the traditional "aperture
delay" of this internal sample and hold.
Since Tacq is measured in clock cycles, its duration will
vary with the internal clock frequency. This results in
Tacq = 1.4 ~ecs ± 0.4 ~ecs. between units and over
temperature.
Offset, gain and linearity errors of the S/H circuit, as well
as the effects of its droop rate, are included in the
overall specs for the HADC674Z.

APERTURE UNCERTAINTY
Often the limiting factor in the application of the sample
and hold is the uncertainty in the time the actual sample
is taken - i.e. the "aperture jitter" or TAJ.
The
HADC674Z has a nominal aperture jitter of 20 nsecs.
between samples. With this jitter, it is possible to
accurately sample a wide range of input signals.
The aperture jitter causes an amplitude uncertainty for
any input where the voHage is changing.
The
approximate voHage error due to aperture jitter depends
on the slew rate of the signal at the sample point (See
Figure 10). The magnitude of this change for a sinewave can be calculated:
Assume a sinusoidal Signal, maximum slew rate, Sr =
27tfVp (Vp = peak voltage, f = frequency of sine wave)
For an N-bit converter to maintain +/- 1/2 LSB
accuracy:
Verr s VfS/2N+1 (where Verr is the allowable error
voltage and Vfs is the full scale voltage)
From Figure 10:
Sr= 8V/8T=27tfVp
Let 8V = Verr = Vfs2 - (N+l), Vp = Vinl2 and 8T = tAJ
(the time during which unwanted voHage change
occurs)
The above conditions then yield:

2·35

Vfsl2N+l ~7tfVintAJ or fmax SVfsl(n:VintAJ)2N+1
Forthe HADC674Z, TAJ" 20 nsec,
therefore f max S 2KHz.
For higher frequency signal Inputs, an extemal sample
and hold is recommended.

.. __....1
RiC

\'-------

~I
....

~.--~WIlfFOft
~w~

_ _.

..........
......

'..

~.--.--.DELA.

COM: VOLTAO!

-

~ ...

_.Llln-.

_.:.;,-=,,_-J.~_ ' L
_____ ,"'-_ _ _ _ __

Figure 8 • Sample and Hold Function

25 pi

TYPICAL INTERFACE CIRCUIT
The HADC674Z is a complete AID converter that is
fully operational when powered up and issued a Start
Convert Signal. Only a few external components are
necessary as shown in Figures 11 and 12. The two
typical interface circuits are for operating the
HADC674Z in either a unipolar or bipolar input mode.
Further information is given in the following sections
on these connections, but first a few considerations
conceming board layout to achieve the best operation.
For each application of this device, strict attention must
be given to power supply decoupling, board layout (to
reduce pickup between analog and digital sections),
and grounding. Digital timing, calibration and the
analog signal source must be considered for correct
operation.
To achieve specified accuracy, a double-sided printed
circuit board with a copper ground plane on the
component side is recommended. Keep analog signal
traces away from digital lines. It is best to lay the P.C.
board out such that there is an analog section and a
digital section with a single point ground connection
between the two through an RF bead. If this is not
poSSible, run analog signals between ground traces
and cross digital lines at right angles only.

POWER SUPPLIES

Aeq

= 4K ohms at any range

't = Aeq Ceq = 100 nsec.

Figure 9· Equivalent HADC674Z
Input Circuit

V,.

The supply voltages for the HADC674Z must be kept
as quiet as possible from noise pickup and also
regulated from transients or drops. Because the part
has 12-bit accuracy, voltage spikes on the supply lines
can cause several LSB deviations on the output.
Switching power supply noise can be a problem.
Careful filtering and shielding should be employed to
prevent the noise from being picked up by the
converter.
Capacitor bypass pairs are needed from each supply
pin to it's respective ground to filter noise and counter
the problems caused by the variations in supply
current. A 10j.LF tantalum and a 0.1J.1.F ceramic type in
parallel between VLOGIC (pin1) and digital common
(pin15), and VCC (pin 7) and analog common (pin 9) is
sufficient. VEE is generated Internally so pin 11 may be
grounded or connected to a negative supply H the
HADC674Z Is being used to upgrade an already
existing design.

Figure 10· Aperture Uncertainty

2·36

Honeywell

GROUNDING CONSIDERATIONS

Any ground path from the analog and digital ground
should be as low resistance as possible to
accomodate the ground currents present with this
device.
The analog ground current is approximately 6mADC
while the digital ground is 3mADC. The analog and
digital common pins should be tied together as close
to the package as possible to guarantee best
performance. The code dependant currents flow
through the VLOGIC and Vcc terminals and not through
the analog and digital common pins.
The HADC674Z may be operated by a J..I.P or in the
stand-alone mode. The part has four standard input
ranges: OV to +10V, OV to +20V, ±5V and ±10V. The
maximum errors that are listed in the specifications for
gain and offset may be adjusted externally to zero as
explained in the next two sections.

CALIBRATION AND
CONNECTION PROCEDURES
UNIPOLAR

The calibration procedure consists of adjusting the
converter's most negative output to its ideal value for
offset adjustment, and then adjusting the most
positive output to its ideal value for gain adjustment.
Starting with offset adjustment and referring to Figure
11, the midpoint of the first LSB increment should be
pOSitioned at the origin to get an output code of all Os.
To do this, an input of +1/2LSB or +1.22mV for the
10V range and +2.44mV for the 20V range should be
applied to the HADC674Z. Adjust the offset
potentiometer R1 for code transition flickers between
0000 0000 0000 and 0000 0000 0001.
The gain adjustment should be done at positive full
scale. The ideal input corresponding to the last code
change is applied. This is 1 and 1/2LSB below the
nominal full scale which is +9.9963V forthe 10V range
and +19.9927V for the 20V range. Adjust the gain
potentiometer R2 for flicker between codes 1111
1111 1110 and 1111 1111 1111. If calibration is not
necessary for the intended application, replace R1
with a son, 1% metal film resister and remove the
network from pin 12. Connect pin 12 to pin 9.
Connect the analog input to pin 13 for the OV to 10V
rangeorto pin 14forthe OVto 20Vrange.
BIPOLAR

The gain and offset errors listed in the specifications
may be adjusted to zero using the potentiometers R1

Honeywell

and R2 (See Figure 12). If adjustment is not needed,
either or both pots may be replaced by a son, 1%
metal film resistor.
To calibrate, connect the analog input signal to pin 13
for a ±SV range or to pin 14 for a ± 1OV range. First
apply a DC input voltage 1/2LSB above negative full
scale which is -4.9988V for·· the ±SV range or 9.9976V for the ±10V range. Adjust the offset
potentiometer R1 for flicker between output codes
0000 0000 0000 and 0000 0000 0001. Next, apply a
DC input voltage 1 and 1/2LSB below positive full
scale which is +4.9963V for the ±SV range or
+9.9927V for the ±10V range. Adjust the gain
potentiometer R2 for flicker between codes 1111
11111110and111111111111.
ALTERNATIVE

The 100n potentiometer R2 provides gain adjust for
the 10V and 20V ranges. In some applications, a full
scale of 10.24V (for an LSB of 2.SmV) or 20.48V (for
an LSB of S.OmV) is more convenient. For these,
replace R2 by a son, 1% metal film resistor. Then to
provide gain adjust for the 10.24V range, add a 200n
potentiometer in series with pin 13. For the 20.48V
range, add a 1000n potentiometer in series with pin
14.

CONTROLLING THE HADC674Z
The HADC674Z can be operated by most
microprocessor systems due to the control input pins
and on-Chip logic. It may also be opergted in the
"stand-alone" mode and enabled by the RIC input pin.
Full ~p control consists of selecting an 8 or 12-bit
conversion cycle, initiating the conversion, and
reading the output data when ready. The output read
has the options of choosing either 12-bits at once or 8
followed by 4-bits in a left-justified format. All five
COl11rol inputs ar~ nUCMOS compatible and include
12/8, CS, Ao, RIC and CE). The use of these inputs in
controlling the converter's operations is shown in
Table 1, and the internal control logic is shown in a
simplified schematic in Figure 13.
STAND-ALONE OPERAT10N
T~

simplest interface is a control line connected to
RIC. The other controls must be tied to known states
as follows: CE and 12,iS are wired high, Ao and CS are
wired low. The output da~ arrives in words of 12-bits
each. The limits on RIC duty cycle are shown in
Figures 3 and 4. It may have duty cycle within and
including the extremes shown in the specifications on
the pages. In general, data may be read when RIC is
high unless STS is also high, indicating a conversion
is in progress.

2·37

CONVERSION LENGTH
,

,'.'

" ,

,

A conversion start transition latches the state of Ao as
shown in Figure 13 and Table 1. The latched state
determines if the.. conversion stops with 8-bits (Ao
high) or. continues f9r12~bits (Ao low). If ~II12-bits are
read following an 8-bit conversion, the three LSB'swili
be a logic ·0· and 083 will be a logic "1". Ao is latched
because it is also i"valved in enabling the· o1;Jtput
buffers as will be explained later. No other control
inputs are latched.

.....

,...
"'

.,.,

,ao<

...

,

,...

_TIlNI

Figure 11 - Unipolar Input Connections

......,.---+.-.!!.J_~

'''''''8

",:;:'---v.-""~9 I.f--x-f-.....,,.f-:...J

Figure 12 - Bipolar Input Connections

2-38

HoneyweU

CONVERSION START

A conversion may be initiated by a logic transition on
any of the three inputs: CE, CS, RIC, as shown in
Table 1. The last of the three to reach the correct state
starts the conversion, so one, two or all three may be
dynamically controlled. The nominal delay from each is
the same and all three may change state
simultaneously. In order to assure that a particular
input controls the start of conversion, the other two
should be setup at least 50ns earlier. Refer to the
convert mode timing specifications. The Convert Start
timing diagram is illustrated in Figure 1.
The output signal STS is the status flag and goes high
only when a conversion is in progress. While STS is
high the output buffers remain in a high impedance
stat~ so that data can not be read. Also, when STS is
high, an additional Start Convert will not res~t the
converter or reinitiate a conversion. Note, if Ao
changes state after a conversion begins, an additional
Start Convert command will latch the new state of Ao
and possibly cause a wrong cycle length for that
conversion (8 versus 12-bits).
READING THE OUTPUT DATA

The output data buffers remain in a high impeda~
state until the following four conditions are met: RIC IS
high, STS is low, CE is high and CS is low. The. ~ata
lines become active in response to the four conditioI'!§.
and output data according to the conditions of 12/8
and Ao. The timing di~ram for this process is shown in
Figure 2. When 12/8 is high, all 12 data .outpu~s
become active simultaneously and the Ao Input IS
ignored. This i~for easy interface to a 12 or 1E1-bit data
bus. The 12/8 input is usually tied high or low,
although it is nUCMOS compatible.

Table 1 - Truth Table for the
HADC674Z Control Inputs
CE

e§

RiC'

1211

A.

0

X

X

X

X

eporollon

1

X

X

X

No••

t
t

0

0

x

0

Inli... 12 bit oonvendon

0

0

X

1

Inlt..... bit oon.ralon

1

1
1
1

0

x

0

Inltr.... 12 bll DOnve......

0

X

1

Innl_ • bit conwl'llion

x

0

Inlt.... 12 bit oonvendon

X

1

0

0

BYTE 2

.Ixxxx
xxxx IIXXXX
0000 I
-I
~~I----~
MSB

LSB

This configuration makes it easy to connect to an 8-bit
data bus as shown in Figure 13. The Ao control can be
connected to the least significant bit of the data bus in
order to store the output data into two consecutive
memory locations. When Ao is pulled low, the 8 MSBs
are enabled only. When Ao is high, the 4 MSBs are
disabled, bits 4 through 7 are forced to a zero and the
four LSBs are enabled. The two byte format is "left
justified data" as shown above and can be considered
to have a decimal point or binary to the left of byte 1.
Ao may be toggled without damage to the converter at
any time. Break-before-make action is guaranteed
between the two data bytes. This assures that the
outputs which are strapped together in Figure 13 will
never be enabled at the same time.
In Figure 2, it can be seen that a read operation usually
begins after the conversion is complete and S:S is
low. If earlier access is needed, the read can begin no
later than the addition of times too and tHS before STS
goes low.

~

ADDRESI_

AD

~•

~

I.

STS

DB" (MIl)

Inltl• • bit oonveralon

1

0

1

1

X

E• •I. 12 bft 0.,,1

0

1

0

0

E._ • MSa·. Only

1

0

1

0

1

EMb'_ 4 LSB'. Plu. 4
T,..IIn,Z....

r-.!L
.,
II

.
II

AD

10-,,'"
HADC674Z

DATA
IUS

•
H
II

III

,.

11

17
080(1.1111)

1

Honeywell

BYTE 1

No••

X

,,
,,

When 12/8 is low, the output is separated into two 8bit bytes as shown below:

DIG.
COlI.

11

,.

J"

Figure 13 - Interfacing the HADC674Z
to an 8-bit Data Bus

2·39

II

NIBBLE B ZERO
OVERRIDE

l - - I I - - - . NIBBLE A,B
INPUT BUFFERS

)-i.--- NIBBLEC

EOC12

Figure 14 - HADC674ZControi Logic
+5.5V
";

..1 +5V
~

1218

3Cs'
4

+~--.,

ov-

r-1
LJ L

400HZ

'-

5

/

6

A,
RIC
CE

HADC
674Z

+16.5V..1.. +15V
8 REF OUT
9 A GND
10

REF IN

5on....ll NlC
BIP OFF

+5V~
,60HZ .....

son

·5'1

N/C ~ 20VIN

' '

12

13 10V IN

STS W
BIT 12 ~
BIT 11 1BIT 10 25
BIT9
24
BIT 8
BIT7
BIT6

23

BITS
BIT 4
BIT3

20

BIT2

17

BIT 1
DGND

3.OKO

22
21

19
18

~

,n

4.7

COMMON

Figure 15 - Burn-in Schematic

2·40

Honeywell

PIN FUNCTIONS HADC674Z

PIN ASSIGNMENT HADC674

N

TOP VIEW

'It

NAME

FUNCTION

VLOGIC

Logic Supply Voltage,
Nominally +5V

1218

Data Mode Select

"co

0

c

«

STS

VLOGIC
1218

::t:

hJ

OB9

CS

Chip Select

RIC

088

Ao

Byte Address! Short cycle

OB7

RIC

Read! Convert

VCC

OB6

CE

Chip Enable

REF OUT

085

Vee

Analog Positive Supply Voltage
Nominally +15V

OB4
REF IN

OB3

N/C (VEE)

OB2

BIPOFF

OBl

10VIN

LSB

REF OUT
AGND

Analog Ground

REF IN

Reference Input

N!c(VEE)

This pin is not connected to the device.

BIPOFF

Bipolar Offset

10VIN

10 Volt Analog Input

20VIN

20V Analog Input

DGND

Digital Ground

OBO

20VIN

Reference Output
Nominally +1 OV

28 LEAD DIP

•

18

17

18

15

14

13

12

0

0

0

0

0

0 0

DBO- DB11

0

11

10

18

0

20

0

0

D
0

21

0

!.I

22

0

!

23

0

0

8

24

0

D

7

25

0

0

8

i

0
28

0
27

0

0

28

0
2

0
3

0

0

4

5

STS

Digital Data Output
DB11-MSB
DBO-LSB
Status

8
8

DIE PLOT
158 MILS

20X

* *For Ordering Information See Section 1.

Honeywell

2-41

NOTES:

2·42

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HADC77100

a-BIT, 150 MSPS FLASH AID CONVERTER
PRELIMINARY INFORMATION
FEATURES

APPLICATIONS

·150 MSPS NOMINAL CONVERSION RATE

• Digital Oscilloscopes
•Transient Capture
• Radar, EW, ECM
• Direct RF Down-conversion
• Medical Electronics: Ultrasound,
CAT Instrumentation

• 1/2 LSB Linearity
• Preamplifier Comparator Design
• Maximum Power Dissipation < 2.0 Watts

II

GENERAL DESCRIPTION
The HADC77100 is a monolithic flash AiD converter
capable of digitizing a 2 volt analog input signal with
full scale frequency components to 50 MHz into 8-bit
digital words at a 150 MSPS update rate.
For most applications, no external sample-and-hold is
required for accurate conversion due to the device's
narrow aperture time. A single standard -5.2 Volt
power supply is required for operation of the

HADC771 00, with nominal power dissipation of less
than 1.75 Watts.
The part is packaged in a 42 Lead Ceramic DIP that is
pin compatible with the CX20116. Careful attention to
design and layout has provided a device with better
linearity, lower noise floor, stable input capacitance,
and lower data error rates. The HADC77100 is
available in Industrial and Military Temperature ranges.

BLOCK DIAGRAM

CONVERT

Honeywell

2·43

o
o

.,...
:::

g
c(

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 2SoC
Supply Voltages Output
Negative Supply VoHage (VEE TOGND) ..-7.0 to +0.5 V
Ground Voltage Differentlal ......................-0.5 to +0.5V
AVEE to DVEE DifferentiaL ................................50mV

Output
Digital Output Current. .... :..........................Oto -25 rnA
Temperature. .
Operating Temperature, arnbient...........-65 to +1500C
junction .....................+1500 C
Lead Temperature, (soldering 10 seconds) ......+300oC
Storage Temperature ............................-65 to +1500C

::I:

Input Voltage
Analog Input Voltage ..............................+0.5 to VEE V
Reference Input Voltage ........................+0.5 to VEE V
Digital Input Voltage...............................+0.5 to VEE V
Reference Current VRno VRB ........................25 rnA
Midtap Reference Current........................-6 to +6 rnA

Notes:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications.

ELECTRICAL SPECIFICATIONS
INDUSTRIAL TEMPERATURE RANGE
VEE = -S.2V, RSource ~ 100, fclock _ 125MHz, Duty Cycle _ 50%
DC ELECTRICAL
PARAMETERS

TEST
CONDITIONS

VRB • -2.00V, VRT. O.OOV, Unless otherwise specified

ROOM
+25oC
LEVEL
MIN TVP MAX

TEST

HOT
COLD
+8SoC
-25°C
MIN MAX MIN MAX

UNITS

TRANSFER
CHARACTERISTICS
Integral Linearity, 77100A

II

±1

±1

±1

LSB

Differential Linearity, 771 OOA

II

±1

.:1:1

.:1:1

LSB

Integral Linearity, 77100B

II

±a

.:I: a

±a

LSB

Differential Linearity, 771 OOB
(No missing codes)

II

±a

.:I: a

.:I: a

LSB

Offset Error VRT

I

18

-30

-30

-30

mV

Offset ErrorVRB

I

18

+30

+30

+30

mV

2
2
4
4

2
2
4
4

2
2
4

4

ANALOG INPUT
CHARACTERISTICS
Input Voltage Range
Input Capacitance

I
Overfull input range

-2.0

0.0

VOLTS

V

56

pF

Input Resistance

V

4

kO

Input Current

II

175

Clock Synchronous
Input Currents

V

40

275

225

350

~
~

TEST LEVEL CODE: See page 7.

2-44

Honeywell

ELECTRICAL SPECIFICATIONS

o
o.-

INDUSTRIAL TEMPERATURE RANGE
VEE" -5.2V, RSource ,,100, fclock" 125MHz, Duty Cycle" 50%
TEST

DC ELECTRICAL
PARAMETERS

CONDITIONS

VRB .. -200V, VRT = OOOV, Unless otherwise specified
HOT
COLD
-2S0C
+8S0C
MIN MAX MIN
MAX

ROOM
+2S0C
LEVEL
MIN TVP MAX

TEST

toto-

g
c(

J:
UNITS

POWER SUPPLIES
Supply Current
(analog)

II

280

300

Supply Current
(digital)

II

50

70

300 mA

300
70

70 rnA

REFERENCE
Positive Reference
Voltage

Operating Condition

I

>VRT

Negative Reference
Voltage

Operating Condition

I

-2.5

Reference Tap
Current

VRM=-1.00V

Ladder Resistance
Reference Bandwidth

IV

0.0

VOLTS

VRT

Negative Reference
Voltage

Operating Condition

I

-2.5

VRM=-1.00V

V

Reference Tap
Current
Ladder Resistance

II

Reference Bandwidth

V

0.0

VOLTS

UNO.

DO DGN02

0 0
N/C OGN01
0 0

~ 2KSilv
goo

§

2

~O~~~O~O~~O~O~O~~O--~-A~.OO~O~SQ~.€:==~
OGN01 07

o

6

2. RING METAUZATION IS .05S·
3. DIMeNSIONING ON BONDINGPADS & DISTANCETOTHE RING·
METAUZATION PERSTC. PROCESS PRACTICE
4. CERA.Mlt OVERAlJ.. THICKNESS IS .o80± ,008
s. TOPSURFACETOBEMETAUZED
FOR HEAT·SlNKlNG PURPOSES
e. GOLD PLATING60u INCHES MIN. THICKNESS

NlC AGN01

0 0

L. _ _ _ _ _ _ _ •

!-++----+t~

AG~D2

F

G _ _ _ _ __
H -------'l'l.

~

J
N/C

.025 01A. ± .005
(46 PlCS)

.100TYP

r--------------,
G-Package

9JA = 4CYCIW
9JA = 15°ClWwith
SOD LFPM Air Flow

.350 ±.008
.460 ± .008

46 LEAD PIN GRID ARRAY

* *For Ordering Information See Section 1.

Honeywell

2-61

NOTES:

I

2·62

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HADC77200

8-BIT, 150 MSPS FLASH AID CONVERTER
PRELIMINARY INFORMATION
FEATURES

APPLICATIONS

·150 MSPS CONVERSION RATE
'100 MHz Full Scale Bandwidth
'1/2 LSB Linearity
• Preamplifier Comparator Design
• Maximum Power Dissipation < 2.7 Watts

• Digital Oscilloscopes
'Transient Capture
• Radar,EW
• Medical Electronics: Ultrasound,
CAT Instrumentation

GENERAL DESCRIPTION
The HADC77200 is a monolithic flash AID converter
capable of digitizing a 2 Volt analog input signal with full
scale frequency components to 100 MHz into 8-bit digital
words at a 150 MSPS update rate.
For most applications, no external sample-and-hold is required for accurate conversion due to the device's wide
bandwidth. A single standard -5.2 Volt power supply is
required for operation of the HADC77200, with nominal
power dissipation of 2.2 Watts.

The part is packaged in a 48 Lead Ceramic Sidebrazed
DIP and a 46 Lead PGA. The HADC77200 includes five
external reference ladder TAPS to gain better control
over linearity; an overrange bit for use in higher
resolution systems; and a data ready output pin for ease
in interfacing to high-speed memory. Careful attention to
design and layout has provided a device with low noise
floor, stable input characteristics, and low data error rate.
The HADC77200 is available in Industrial and Military
Temperature ranges.

BLOCK DIAGRAM

Honeywell

2-63

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 250C
Output
Digital Output Current.. .............................Oto -25 mA

Supply Voltages OUtput
Negative Supply Voltage (VEE TO GND) .. -7.0 to +D.5 V
Ground Voltage Differential ......................-0.5 to +0.5V
AVEE to DvEE Differential.. ................................50mV

Temperature
Operating Temperature, ambient........... -65to +1500C
junction .....................+1500 C
Lead Temperature, (soldering 10 seconds) ......+300oC
Storage Temperature ............................-65 to +1500C

Input Voltage
Analog Input Voltage ..............................+0.5 to VEE V
Reference Input Voltage ........................+0.5 to VEE V
Digital Input Voltage...............................+0.5 to VEE V
Reference Current VRTto VRB........................25 mA
Midtap Reference Current ........................-6 to +6 mA

Notes:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications,

ELECTRICAL SPECIFICATIONS
INDUSTRIAL TEMPERATURE RANGE
VEE = -5.2V, RSource • 1on, fclock = 125MHz, Duty Cycle = 50%
DC ELECTRICAL
PARAMETERS

TEST
CONDITIONS

VRS • -2.00V, VRT = O.OOV, Unless otherwise specified

ROOM
+25OC
LEVEL
MIN TVP MAX

TEST

HOT
COLD
+8SoC
-2SoC
MIN MAX MIN MAX

UNITS

TRANSFER
CHARACTERISTICS
Integral Linearity, 77200A

II

±1

±1

2

±1 LSB
2

Differential Linearity, 77200A

II

±1

±1

±1 LSB

Integral Linearity, 77200B

1/

±.a

±.a

±.a LSB

Differential Linearity, 77200B
(No missing codes)

1/

±3

Offset Error VRT

I

-8

Offset Error VRB

I

+8

2

2
4

2

4

2

4

±3

±.a LSB

-15

-15

-15

mV

+15

+15

+15

mV

4

4

4

ANALOG INPUT
CHARACTERISTICS
Input Voltage Range
Input Capacitance

I
Over full input range

-2.0

0.0

VOLTS

V

56

pF

V

4

kn

Input Current

II

300

Clock Synchronous
Input Currents

V

40

Input Resistance

500

450

650

jJ.A
jJ.A

TEST LEVEL CODE: See page 7.

2·64

Honeywell

ELECTRICAL SPECIFICATIONS
INDUSTRIAL TEMPERATURE RANGE

vEE"-52V
. , RSource .. lon'
, clock .. 125MHz, Duty Cycle =50%
TEST

DC ELECTRICAL
PARAMETERS

CONDITIONS

VRB .. -2.00 VVR
, T =O.OOV, Un ess otherwise specified

ROOM
+2SOC
LEVEL
MIN TYP MAX

TEST

HOT
COLD
-2SOC
+850 C
MIN MAX MIN MAX

UNITS

POWER SUPPLIES
Supply Current
(analog)

II

360

425

440

425 rnA

Supply Current
(digital)

II

60

80

85

80 rnA

REFERENCE
Positive Reference
Voltage
Negative Reference
Voltage
Reference Tap
Current

Operating Condition

I

>VRB

Operating Condition

I

-2.5

vRM=-1.00V

Ladder Resistance
Reference Bandwidth

IV

0.0

VOLTS

VRB

Negative Reference
Voltage

Operating Condition

I

-2.5

VRM=-I.00V

V

Reference Tap
Current
Ladder Resistance

II

Reference Bandwidth

V

0.0

VOLTS

-

23

CLK

R1
R2
R3
R4
VREF

..
8!U>
~

R2

=son 1/4 WaH CC 5%
=1Kn 1/4 Watt CC 5%

Uil!:

4 LlNV

2~~

LW

DRINV

~R2
-2.00

-'-

-::-

= 6.an 1/4 WaH CC 5"= 3.zan 112 WaH CC 5%
= -2.00 vons

VEE • -6.6
-2.00

171--------

R2

.AAA

~

von_

Pin number. refer to dip packages only.
500

'3
Vln

MC'OH018

100 0
·5.2Votla

100 0

-2.00
-2.00
500

MC101U

CLK

CLK

elK = .. 0.7 to .. 1.7 Volt.
FNquoncy
50 KHz

=

CIRCUIT TO GENERATE CLOCK
AND INPUT FOR BURN-IN CIRCUIT

Honeywell

2-75

DIFFERENTIAL NONLINEARITY

o

o
('II

.....
.....

DEFINITION OF TERMS

g

SPECIFICATIONS

.~

AID. CONVERTER ERROR SUMMAiw
Honeywell SPT realizes that the transfer function for
an AID converter is very dependent upon the slew
rate of the signal it is digitizing. The transfer function
under dynamic conditions may exhibit numerous
errors (Figure 2B) while a static dc input level may
appear close to the ideal (Figure 2A). That is why we
are including many dynamic tests as well as the the
industry standard de specifications.

EFFECTIVE BITS (SNR)
This is the difference between the measured data at
the output of an AID converter in response to a
sinewave and an ideal sinewave's data best fitted to
the measured data. The data is then plotted as usable
(effective) output bits versus frequency. This is the
most important specification since it is tested over the
entire frequency range of the part and shows true
dynamic performance. It also indicates the cumulative
effect of many error sources. These are quantizati9n
error, dynamic differential nonlinearity, missing codes
integral nonlinearity, total harmonic distortion, aper~
t~re .uncertainty and noise. Not included are DC specifications such as offset and gain errors. The result is
calculated from measured rms error for the ideal
sinewave and the measured actual rms error as
follows:

Differential nonlinearity Is a measure of how much the
actual quantization step width varieS from the ideal
step width of 1 LSB. Figure 2B shows a differential
nonlinearity of 2 LSB - the actual step width is 3 LSB.
The HADC77200's specification gives the worst case
differential nonlinearity in the AID transfer function
under specified dynamic operating conditions. Small,
localized differential nonlinearities may be insignificant
when digitizing full scale signals. However, if a low
level input signal happens to fall on that part of the AID
transfer function with the differential nonlinearity error,
the effect will be significant.
MISSING CODES
Missing codes represent a special kind of differential
nonlinearity. The quantization step width for a missing
code is 0 LSB, which results in a differential
nonlinearity of -1 LSB. Figure 2B points out two
missed codes in the transfer function.

output
Cod..

eff bits = 8 - log2 actual rms error
ideal rms error
Input Vollago

Furthermore, signal-to-noise ratio (SNR) can be
related to effective bits by the following formula:
SNR(dB) = 1.8 + 6.02 X N(eff bits)

Figure 2A Static Input Conditions
Output
Cod ..

QUANTIZATION ERROR
Quantization error is the fundamental, irreducible error
aSSOCiated with the perfect quantizing of a continuous
(analog) signal into a finite number of digital bits (AID
tranfer function). An 8-bit AID converter can represent an input voltage with a best case uncertainty of 1
part in 28 (1 part in 256). In real AIDs under dynamiC
operating conditions, the quantization bands (bit
change step vs input amplitude) for certain codes can
be significantly larger (or smaller) than the ideal. The
ideal width of each quantization step (or band) is Q =
FSRf2N where FSR = full scale range and N =8. Nonideal quantization bands represent differential nonlinearity errors (See Figures 2A and 2B).

2·76

~~e~~~1 Nonlinearity •

Input VoHll/le

Figure 28 Dynamic Conditions

Honeywell

SPECIFICATIONS CONTINUED
INTEGRAL NONLINEARITY
Integral nonlinearity is the maximum deviation of the
AID transfer function from a best fit straight line
(Figure 3A). Integral nonlinearity does not include
any gain and offset errors. Integral nonlinearity in an
AID is generally more detrimental when digitizing full
scale signals than low level signals which may fall on a
part of the transfer function which is relatively linear.
Figure 2B shows an integral nonlinearity error of 2
LSB. The HADC77200's integral nonlinearity can be
improved by using the external reference ladder taps
as shown in Figure 1. The resulting effect on the
linearity is shown in Figure 3B.
APERTURE UNCERTAINTY
Aperture uncertainty is the time jitter in the sample
point and is caused by short term stability errors in the
timebase generating the sample (encode) command
to the AID converter. The approximate voltage error
due to aperture uncertainty depends on the slew rate
of the signal at the sample point. See Figure 3C .
As in any sampled data system, the aperture width
affects the accuracy of the system. The aperture time
can be considered an amplitude uncertainty for any
input where the voltage is changing. The magnitude
of this change for a sinewave can be calculated for
time or voltage by the equation:

By calculating the aperture time for a given system
accuracy and comparing it to the aperture time
specification of the flash converter, the need for a
track and hold can be determined. The graph in Figure
4 summarizes required aperture time for a-bit resolution high speed converters using sinusoidal frequencies.
An example using an a-bit flash converter follows. If
the signal that is to be measured is known not to
contain any sinusoidal frequencies above 10MHz,
then from Figure 4 it can be determined that to assure
less than a-bits of error due to aperture alone, the AID
converter must have an aperture time of less than
70ps. Most data sheets do not state aperture time so
usually a sample and hold is used. Unfortunately, the
sample and holds generally available today are not
faster than 70ps.
Aperture time and delay are very difficult to measure,
however these values are needed to make intelligent
design decisions. Honeywell SPT supplies these
values for the HADC77200 based on both computer
design simulations and verified by characterization of
samples.

dVN=21tfta
Linearity Curves

o
I

I

N

N

P

P

U

T

U
T

Y ·1

~ ·1.0

L
T
A

A

G

G

E

E

o

L
T

·2

·2

64

128

152

255

Bit Number

FIGURE 3A Linearity Curve with no
TAP adjustment

Honeywell

o
o
.....
.....

C\I

o

64

128

152

255

8ft Number

FIGURE 38 Linearity Curve with TAPS
Forced to Within .5mV of
Ideal

2·77

~J:

CHARACTERISTIC TESTING
TESTING
All of the following tests can be performed using
Hewlett-Packard equipment as referred to in H.P.
Product Note 5180A-2. Test methods available to
measure the previous specifications are explained as
follows and listed in Table 2.

I

---t-

~rror=At ~

At

HISTOGRAM TESTING

FIGURE 3C Aperture Uncertainty
A

P

e

1E-08

r
t

u
r

e
T
I

1E-08

'"

~

lE·l0

1E-11

""

~

m

e

In histogram testing, a full scale sinewave of specified
frequency is input to the HADC77200. The frequency
of the sinewave is selected to be non-coherent with
the sample rate of the AID converter. Several hundred
thousand samples of the signal are taken and
processed into a histogram. At the end of the
sampling, the histogram is plotted with possible output
codes along the x-axis and frequency of occurance
along the y-axis. Above each possible output code
(the x-axis is from 0 to 256), a point is plotted whose
height is proportional to the total number of times that
code occurs. For a sinewave input, a perfect AID
converter would produce a cusp probability density
function described by the equation:

lE-G7

lE·12
1E+04

1E+0I

1E.08

1E+07

FREQUENCY (HZ)

'.0.=_1_

N=.

'"

1E+08

1E+Og

p(V)=-......:....-1t(A2 - V2)"1/2

2M 21ft

FIGURE 4 Aperture Time· Sinewaves

--------------------

where A is the peak amplitude of the sinewave and
p(V) is the probability of an occurance at a voltage V. If
a particular step is wider than the ideal width, then the
code associated with that step will have accumulated
more "counts" than a code corresponding to the ideal
step. A step narrower than the ideal width will
accumulate fewer counts. Missing codes are readily
apparent because a missing code will show zero
counts (See Figure 5).
FAST FOURIER TRANSFORM TESTING
The Discrete Fourier Transform (OFT) is another useful
tool for evaluating AID converter dynamic performance. Implemented using a Fast Fourier Transform
algorithm, the OFT converts a finite time sequence of
sampled data into the frequency domain. From the
frequency domain representation of the data, the
linearity of the AID converter's dynamic transfer function may be measured. Harmonics of the input sinewave, caused by the integral nonlinearity, are aliased

Reconstructed
Sinewave

Histogram

In the histogram test, AID transfer function step widths larger
than ideal show up as "spikes" in the histogram. Codes missing
from the transfer function show up as "bins" w~h zero counts.

FIGURE 5 Histogram Testing

2-78

Honeywell

SPECIFICATION TESTING
CONTINUED:

o
o
C\I
,....

into the baseband spectrum and can be readily
identified and measured. Additional effects can be
measured as shown in Table 2.

g

BEAT FREQUENCY TEST

I

c:(

SINEWAVE CURVE FITTING
In the sinewave curve fit test, a full scale sinewave of
specified frequency is digitized by the HADC77200.
USing least squared error minimization techniques, an
idealized sinewave fit to the data is calulated by
software. The sinewave is in the form:
ASin(21tft+G)+DC
where A,f,G,DC are the parameters which are selected
for a best fit to the data. The idealized best fit sinewave, Aosin(27tfot+Go)+DCo is then subtracted from
the digitized time record.

Beat frequency testing is a qualitative test for ND
converter dynamic performance and may be used to
quickly judge whether or not there are any gross
problems with the HADC77200. In this technique, a
full scale sinewave input signal is offset slightly in
frequency from the ND converters sample rate, This
frequency offset is selected such that on successive
cycles of the input sinewave, the ND's output ideally
would change by 1 LSB at the point of maximum
slope. Thus the AID sample point "walks" through the
input signal. When the data stored in memory is
reconstructed using a low speed DAC, the beat
frequency, Il f, is observed. Differential nonlinearities show up as nonuniform horizontal lines in the
observed beat frequency waveform and missing
codes show up as gaps.

TABLE 2
TESTS
The fO/lowing table summarizes the dynamic performance tests previously described and the dynamic errors which influence test results.
(Table from H. P. Product Note 51BOA·2)

BEAT
SINEWAVE

FREOUENCY

ERROR

HISTOGRAM

FFT

CURVE FIT

TEST

Differential
Nonlinearity

Yes-shows up as spikes

Yes-shows up as
elevated noise floor

Yes-part of
RMSerror

Yes

Missing CDdes

Yes-shows up as bins
with counts

Yes-shows up as
elevated noise floor

Yes-part of
RMSerror

Yes

Integral Nonlinearity

Yes (could be measured
directly w~h highly linear
ramp waveform)

Yes-shows up as
harmonics of fundamental
aliased into baseband

Yes-partof
RMSerror

Yes

Aperature Uncertainty

No-averaged out. Can be
measured with "phase
locked" histogram.

Yes-shows up as
elevated noise floor

Yes-part of
RMSerror

No

Noise

ND-averaged out. Can be
measured with "phase
locked" histogram.

Yes-shows up as
elevaled noise floor

Yes-part of
RMSerror

No

Bandwidth Errors

No

No

No

Yes-used to
measure analog
bandwidth.

Gain Errors

Yes-shows up in peak to
paak of distribution.

No

No

No

Offset Errors

Yes-shows up in ofIsei
of distribution average.

No

No

No

Honeywell

o

,....

The rms errors are then calculated and the effective
bits specification is found.

2-79

CHARACTERIZATION GRAPHS

, r-- r,
51

T

o

i--

T
A

..............

L

I--

S
I
G
N
A
L

"

H
A
R
M

o

N

!II

E
(DB)

T

"

R'

T
I

o

III

OIl

N
(DB)

.......... ,....,

III

S

o

i'--

,

0

S

..........

~

N
0
I

D
I

..........

:I

T

I
C

~

ao

o

o

10

15

25

20

30

35

40

45

FULL SCALE ANALOG INPUT FREQUENCY (MHZ)

10

0
DGND1
DVEE

00

"aNOl

8 S

00000

o

o

50

°VEE

oLINV

o

DRINV

1

l'

q

o
P"oNO.

0

o

"vEE

AGND1

0

0

VATS

VR.

0

0

VRT

J

45

DGN01

0

0

40

o

0
0

0

35

c~~

VABO

NC

30

~

~I

l! S 11 i!! 11
00000

0
CLK 0
Cu< 0

AClN02

25

OFT DERIVED SNR VERSUS
INPUT FREQUENCY FOR 125MSPS

MINV

"vEE

20

FULL SCALE ANALOG INPUT FREQUENCY (MHZ)

OFT DERIVED THD VERSUS
INPUT FREQUENCY FOR 125 MSPS

Q~ "z "z

15

0

~

0

eX

00 000 0
~

c~ ~ j ~

00000

s

}

AVEE

i~ ~ ~

DIE LAYOUT

2-80

Honeywell

PIN ASSIGNMENT HADCn200
NAME

TOP VIEW

FUNCTION

DRINV

AVEE

NAME
ClK

Inverse ECl Clock Input Pin

LlNV

DO through D6 Output
Inversion Control Pin

ClK

ECl Clock Input Pin

VRBS
AVEE

Negative Analog Supply
Nominally -S.2V

Reference Voltage Bottom, Sense
Nominally -2.0V

VRBF
DVEE

Digital Analog Supply
Nominally -S.2V

Reference Voltage Bottom, Force
Nominally -2.0V

VR1

Reference Voltage Tap 1

DGND1

Digital Ground 1
AGND1

Analog Ground 1

DGND2

Digital Ground 2
VIN

DREAD

Data Ready Output

Analog Input, can be connected to
the input signal or used as a Sense

DO

Digital Data Output Pin 1
(lSB)

AGND2

Analog Ground 2

VR2

Reference Voltage Tap 2

D1~D6

Digital Data Output Pin 2
Through 6

VIN

Analog Input, can be connected to
the input signal or used as a Sense.

Digital Data Output Pin 7
(MSB)

VR3

Reference Voltage Tap 3

D8

Overrange Output

VRTS

Reference Voltage Top, Sense
NominallyOV

MINV

D7 Output Inversion
Control Pin

VRTF

Reference Voltage Top, Force
NominallyOV

VRTS
VRTF
AVEE
AVEE
VR3
AGND2
D1

VIN

D2

AGND1

D3
D4

VR2
AGND1

D5

VIN

D6

AGND2
VR1

D8 (OVERRANGE)

AVEE

DGND2

AVEE

D7

N/c
VRBF
VRBS
AGND1
AGND2
24

N/c

8

Data Ready Inverse

AGND1

DGND2

FUNCTION

c(

AGND2

7

o
oC\I
.....
.....

AVEE

25

~

48 LEAD CERAMIC
SIDEBRAZED DIP
---./.181 ± .0121.6

5

4

3

0

0 0

0

I

PIN 1 IDEN,.·I

2

--~~~~~~~~~~~O--~n-·~oro~SQ~.~==~~
04

03

01

02

,-------.,,

,

,

A----.;;;

DO DGND2

o 0
o 0
o 0
o 0
o 0
o 0

DREADDGND1
N/c

B------~.'I': ~
:=====::jt1~
C

DVEE

.&.

0

LlNV ORINV

E

AVEE AGN02

,

,

,--------

VRTS AGN01

F

G=======Jru
H------N

&.

.025 01A. ± .005
(46 PLCS)

.3ro ± .OOB
.460 ± .008

46 PIN GRID ARRAY

G Package - aja =40°C/W
a'a = lsoC/Wwith
ShOLFPM Air Flow

NOTES,
!. CAVrrYOOWN
2. RING MEl"AUZATlON 1S.055"

3. DIMENSIONING ON BONDING·
PADS & DISTANCETOTHE RlNGMETAL1ZATION PERSTD. PROCESS PRACTICE
,c. CEAAMICOVERALL THICKNess IS ,OBO±.OO8
5. TOPSURFACETOBEMETAUZED
FORHeAT-8INKINQ PURPOSES
8. GOLD PLATING60uiNCHES MIN. THICKNESS
OVER 100p.INCHES NOM. THICKNESS NICKEL
·CONNECT ALL GROUND AND NIC PINS lOAN
APPROPRIATEGROUND.

* *For Ordering Information See Section 1.

Honeywell

2-81

II

NOTES:

2-82

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HADC77300

a-BIT, 250 MSPS FLASH AID CONVERTER
ADVANCE INFORMATION

FEATURES

APPLICATIONS

·250 MSPS CONVERSION RATE
·150 MHz Full Scale Bandwidth
• 1/2 LSB Linearity
• Preamplifier Comparator Design
• Maximum Power Dissipation < 4.3 Watts

• Digital Oscilloscopes
·Transient Capture
• Radar, EW
• Medical Electronics: Ultrasound,
CAT Instrumentation

GENERAL DESCRIPTION
The HADC77300 is a monolithic flash AID converter
capable of digitizing a 2 Volt analog input signal with full
scale frequency components to 150 MHz into 8-bit digital
words at a 250 MSPS update rate.
For most applications, no external sample-and-hold is required for accurate conversion due to the device's wide
bandwidth. A single standard -5.2 Volt power supply is
required for operation of the HADC77300, with nominal
power dissipation of 4 Watts.

The part is packaged in a 46 Lead PGA. The
HADC77300 includes five external reference ladder
TAPS to gain better control over linearity; an overrange
bit for use in higher resolution systems; and a data ready
output pin for ease in interfacing to high-speed memory.
Careful attention to design and layout has provided a
device with low noise floor, stable input characteristics,
and low data error rate. The HADC77300 is available in
Industrial and Military Temperature ranges.

BLOCK DIAGRAM
VRTS

VR3

VR.

VR1

VRIF
YRB.

CUi
CONYER
T
ClK

SENSE)

Honeywell

2-83

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25°C
Supply Voltages Output
Negative Supply Voltage (VEE TO GND) ..-7.0 to +0.5 V
Ground Voltage Differential... ................... -0.5 to +0.5V
AVEE to DVEE Differential.. ................................50mV

Output
Digital Output Current... ............................0 to -25 rnA
Temperature
Operating Temperature, ambient... ........ -65 to +150°C
ju nction .....................+175°C
Lead Temperature, (soldering 10 seconds) ......+300°C
Storage Temperature ............................-65 to +150°C

Input Voltage
Analog Input Voltage ..............................+0.5 to VEE V
Reference Input Voltage ........................+0.5 to VEE V
Digital Input Voltage...............................+0.5 to VEE V
Reference Current VRTto VRB ........................25 rnA
Midtap Reference Current ........................-6 to +6 rnA

Notes:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications.

ELECTRICAL SPECIFICATIONS
INDUSTRIAL TEMPERATURE RANGE
VEE =-5.2V, RSource =10n, fclock = 250MHz , Duty Cycle = 50%
TEST
CONDITIONS

DC ELECTRICAL
PARAMETERS

TEST
LEVEL

VRB

= -2 OOV, VRT = OOOV Unless otherwise specified

ROOM
+25°C
MIN TYP MAX

HOT
COLD
·25°C
+85°C
UNITS
MIN MAX MIN MAX

TRANSFER
CHARACTERISTICS
Integral Linearity, 77300A

II

±1
2

±1
2

±1 LSB
2

Differential Linearity, 77300A

II

±1
2

±1
2

±1 LSB
2

Integral Linearity, 77300B

II

±~

±~

±~

4

4

4

Differential Linearity, 77300B
(No missing codes)

II

±~

±~

±~

4

4

4

Offset Error VRT

I

-8

-15

-15

-15

mV

Offset Error VRB

I

+8

+15

+15

+15

mV

LSB
LSB

ANALOG INPUT
CHARACTERISTICS
Input Voltage Range
Input Capacitance

I
Over Full Input Range

Input Resistance

-2.0

0.0

Volts

V

30

pF

V

4

kQ

Input Current

II

Clock Synchronous
Input Currents

V

1.5
40

rnA

IlA

TEST LEVEL CODE: See page 7.

2-84

Honeywell

ELECTRICAL SPECIFICATIONS
INDUSTRIAL TEMPERATURE RANGE
VEE = -5.2V, RSource = lOn, fclock -- 250MHz, Duty Cycle = 50%
DC ELECTRICAL
PARAMETERS

TEST
CONDITIONS

VRB = -200V VRT = OOOV, Unless otherwise specnied

ROOM
+2S0C
LEVEL
MIN TVP MAX

TEST

HOT
COLD
+8S0C
-2S0C
MIN MAX MIN
MAX

UNITS

POWER SUPPLIES
Supply Current
(Analog)

II

Supply Current
(Digital)

II

750
60

750

775
85

80

rnA

80 mA

REFERENCE
Positive Reference
Voltage

Operating Condition

I

>VRB

Negative Reference
Voltage

Operating Condition

I

-2.5

Reference Tap
Current

VRM=-1.00V

IV

Ladder Resistance

II

Reference Bandwidth

V

0.0

Volts

VRB

Negative Reference
VoHage

Operating Condition

I

-2.5

VRM=-1.00V

V

Reference Tap
Current
Ladder Resistance
Reference Bandwidth

"

V

0.0

Volts



0

00

00000

:!i l!l ~

13

~

~
Q

Q'"

00000

0

0
0

0
CLK 0
CLK
0

0
0

"'NV

Av••

"ONDI

DVEE
UNV
"",,v

1

0

0

q

P
0

0

VR.

0

0

J

; Ji j

0

DONO I

i':i!

"""" 00
NC

8080100

i

~~

0
0

"QN02

7U

DFf DERIVED SNR VERSUS
INPUT FREQUENCY FOR 250 MSPS

DFf DERIVED THD VERSUS
INPUT FREQUENCY FOR 250 MSPS

DVEE

110110

FULLSCALEANALOGINPUTFREQUENCY(MH~

FULL SCALE ANALOG INPUT FREQUENCY (MH~

DONO I

40

0

DO ODD 0

~

j

~

J

Av••
AGND2

AGNDI

0

VATS

0

VRr

00000

"VEE

i~~~

DIE LAYOUT
DIE SIZE 225 X 280

2·100

Honeywell

HADC77300 PIN ASSIGNMENT

o
oC')

NAME

FUNCTION

NAME

DRINV

Data Ready Inverse

ClK

Inverse ECl Clock Input Pin

L1NV

DO through D6 Output
Inversion Control Pin

ClK

ECl Clock Input Pin

VRBS
AVEE

Negative Analog Supply
Nominally -S.2V

Reference Vo~age Bottom, Sense
Nominally -2.0V

VRBF
DVEE

Digital Analog Supply
Nominally -S.2V

Reference Voltage Bottom, Force
Nominally -2.0V

..

VR1

Reference Voltage Tap 1

AGND1

Analog Ground 1

VIN

Analog Input, can be connected to
the input signal or used as a Sense

AGND2

Analog Ground 2

DGND1

Dig Hal Ground 1

DGND2

Dig Hal Ground 2

DREAD

Data Ready Output

DO

Dig Hal Data Output Pin 1
(lSB)

VR2

Reference Voltage Tap 2

D1_D6

Dig Hal Data Output Pin 2
Through 6

VIN

Analog Input, can be connected to
the input signal or used as a Sense.

Digital Data Output Pin 7
(MSB)

VR3

Reference Voltage Tap 3

D8

Overrange Output

VRTS

Reference Voltage Top, Sense
NominailyOV

MINV

D7 Output Inversion
Control Pin

VRTF

Reference Voltage Top, Force
NominailyOV

D7

,...,...

FUNCTION

~:r::

HADC77300 PACKAGING INFORMATION
.050 DIA. ± .005

(45 PlCS)

o

DB

D6

DGND1

0
D7
0

o
o

oD5

DVEE DGND2

~ C~ M~V
goo
§
ci

AVEE ClK

0

0
0

AGND2 AGND1

o

,

,-------~
H-------~''-Y

&.

.025 DIA. ± .005
(46PLCS)

.100TYP
.350 ± .008

.460 ± .008

46 PIN GRID ARRAY

G Package - aja =40°C/W
a'a =15°C/W with
ShOLFPM Air Flow

NOTES:
1. CAVITVOOWN
2. RING METAUZATION IS ,055"
3. DIMENSIONING ON BONDINGPADS& DISTANCETOTHE RING·
METALIZATION PER STD. PROCESS PRACTICE
4. CERAMICOVEAALL THICKNESSIS.06O±.OO8
S. TOP SURFACE TO BE METAUZED
FOR HEAT·SINKING PURPOSES
6. GOLO PLATING SI)J INCHES MIN. THICKNESS
OVER 100p.INCHES NOM. THICKNess NICKEL
'CONNECTAUGROUNDANDNlCPlNSTOAN
APPROPRIATE GROUND.

* *For Ordering Information See Section 1.

Honeywell

2·101

NOTES:

2·102

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HADC77600

10-BIT, 50 MSPS FLASH ANALOG TO DIGITAL CONVERTER
ADVANCE INFORMATION
FEATURES:

APPLICATIONS:

• Output Glitches Eliminated
• Trimmed to ±3/4 LSB
• On-Chip Input Buffer Amplifier
• Gray Coded Logic for Low Noise
• Preamplifier/Comparator Inputs

• Radar
• Digital Oscilloscopes
• Video Equipment
• Spectrum Analyzers
• Medical Imaging

II

GENERAL DESCRIPTION
The HADC77600 is a monolithic IO-bit parallel converter
with an on-Chip buffer amplifier for ease in driving the
input. The sample rate can be set up to 50MSPS
(75MSPS TYPICAL) for digitizing signals up to 25M Hz.
Without the input buffer, the full scale input range is -2.0
to +2.0 Volts. With the input amplifier connected, the
input range is ± 400mV into a 1KQ in parallel with 5pF
input impedance.
The HADC77600 has a wide bandwidth to allow it to be
used in many applications without a track and hold. If a
track and hold is required for the application, the
converter has excellent step response.

BLOCK DIAGRAM

New design techniques have been used to eliminate
random errors commonly found in flash converters.
Glitches and metastable states have been reduced to the
This provides a great advantage to
1 LSB level.
designers of single event detection systems for better
performance than previously possible.
The device is packaged in a 72-lead Pin Grid Array (PGA),
and power dissipation is only 4.7 Watts. Operation is
guaranteed over both the commercial and military
temperature ranges.

NCLK a..K
VlN

YRTS
RI2

.

ncz
I

i

.mpl~. :~ r!'-l
Ampln+

~ut
800

VA>

I

VAS 0-- R

~~:=

::.::~_+___fi>·· ..
0

:

VR1~

VR. .

Honeywell

2-103

o ABSOLUTE MAXIMUM RATINGS 25°C (1)
o
~SUPPIY Votages,

.....

8:$
....

Output
Applied VoHage .......•.............•..........•. -.8Vto + .4V·

Positive Supply Votage (VCC to AGND) ......;t6.0 to -0.5V
Negative Supply VoHage (VEE to AGND) ....-6.0 to+0.5V
GND Voltage Differential (AGND to DGND) .. +0.5 to -0.5V

Temperature
Temperature, ambient..•.................•...-60 to +140°C
,junction .•..................•............ +150°C
lead Temperature (soldering 10 seconds) ....+300°C
Storage Temperature ...•................•....-65 to +150°C

Input Voltages
Data, Controls (ECl, measured to AGND) .....+0.5 to VEE
Analog (VIN) ...............................+/-2.SV for +/-2.0V Ref

Note: Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions
in typical applications.
.

ELECTRICAL SPECIFICATIONS

vcc = +5.0V, VEE = -S.2V, VSIAS = +2.0V, fClOCK = 50MHz, VRT= 2.0V, VRS= -2.0V, Duty Cycle = 50%, unless
otherwise specified.
DC Electrical
'Characteristics

Test
Level (1)

Test
Conditions

Room +25°C
Hot +70°C
Min Typ Max Min Typ Max

Cold ·25°C
Min Typ Max

Units

TRANSFER CHARACTERISTICS

±1

Integral Linearity

lSB

±3I4

Differential Linearity

lSB

Offset Error VRT

-15

mV

Offset Error VRS

15

mV

ANALOG INPUT CHARACTERISTICS (ADC)

Input Voltage Range
Input Capacitance

-2
Without
Amplifier

+2 ·2

+2 -2

+2 Volts

300

pF

Input Current

1.0

Input Resistance

20

mA
KOhms

Clock Synchronous Input
Currents

50

IIA

ANALOG INPUT CHARACTERISTICS

(Amplifier)

Input Voltage Range

Inverting Input

-500

+500

-500

+500 -500

+500 mV

Input Voltage Range

Non-Inverting
Input

-400

+400 -400

+400 -400

+400 mV

Input Capacitance
Input Resistance
Input Current

5
Inverting
Non-Inverting

1
500

3

pF
KOhms

IIA

(1) See page 4.

2-104

Honeywell

ELECTRICAL SPECIFICATIONS

o
o

VCC = +5.0V, VEE = -5.2V, VBIAS = +2.0V, fCLOCK = 50MHz, VRT= 2.0V, VRB= -2.0V, Duty Cycle = 50''10, unless

CD
,...
,...

otherwise specified.
DC Electrical
Characteristics

Test
Conditions

Room +25°C
Hot +70°C
Cold -25°C
Min Typ Max Min Typ Max Min Typ Max

Units

8«
J:

POWER SUPPLY CHARACTERISTICS
Positive Supply Current

440

mA

Negative Supply Current

380

mA

Bias Supply Current

130

mA

Power Dissipation

4.7

Watts

REFERENCE CHARACTERISTICS
Positive Reference Voltage

Volts

+2.5

Negative Reference Voltage

-2.5

Reference Current

Volts
6

mA
mA

Reference Tap Currents

0.4

15

Ladder Resistance

650

Ohms

Reference Bandwidth

10

MHz

DIGITAL LOGIC CHARACTERISTICS
Output High Voltage

100 Ohms to -2V

-0.98

-0.91

-0.89

-0.70

-1.10

-0.87 Volts

Output Low Voltage

100 Ohms to -2V

-1.95

-1.65

-1.95

-1.57

-1.95

-1.65 Volts

Input High Voltage

-1.13

-0.81

-1.07

-0.67

-1.27

-0.87 Volts

Input Low Voltage

-1.95

-1.48

-1.95

-1.42

-1.95

-1.50 Volts

AC Electrical
Characteristics

Test
Conditions

Room +25°C
Hot +70"C
Cold -25°C
Min Typ Max Min Typ Max Min Typ Max

Units

CONVERSION TIMING CHARACTERISTICS
Minimum Sample Rate
Clock Width (tPW)

50
Figure 1

75

Output Latency

Cycle

1

Output Delay (to)
Acquisition Time

MSPS
ns

10

5
Figure 2; Full
Scale to .1%

TBD

8 2

ns

20

ns

Aperture Jitter

12

psRMS

Aperture Delay (tAP)

5

ns

ANALOG INPUT CHARACTERISTICS

(Amplifier)

Slew Rate

300

V/jJ.S

Bandwidth

-3dB

45

MHz

Bandwidth

45° Phase Shift

25

MHz

Full Scale
to .1%

30

ns

Settling Time
(1) See page 4.

Honeywell

2-105

I

ELECTRICAL SPECIFICATIONS
VCC .. +5.0V, VEE .. -5.2V, VBIAS .. +2.0V, fCLOCK .. 50MHz, VRT.. 2.0V, VRB- -2.0V, Duty Cycle .. 50"10, unless
othelWise specified.

DC Electrical
Characteristics

Room +25°C
Hot +70°C
Cold -25°C
Min Typ Max Min Typ Max Min Typ Max

Test
Conditions

SIGNAL QUALITY CHARACTERISTICS

(fCIOCk

Units

=50MHz)

Total Harmonic Distortion

VIN=FS
@1MHz

55

dB

Total Harmonic Distortion

VIN=FS
@5MHz

50

dB

Total Harmonic Distortion

VIN=FS
@10MHz

44

dB

Signal to Noise Ratio

VIN=FS
@1MHz

58

dB

Signal to Noise Ratio

VIN= FS
@5MHz

55

dB

Signal to Noise Ratio

VIN=FS
@10MHz

48

dB

NTSC 140 IRE
Mod. Ramp

TBD

%

TBD

Degrees

Differential Gain

Differential Phase
..
(1) All electrical charactenstlcs are subject to the following conditions:

..

All parameters having minimax specifications are guaranteed. The Testlevel Column indicates the specific device testing
actually performed during production and Quality Assurance inspection. Any blank sections in the data columns indicates that the
specification is not tested at the specified condition. Unless otherwise noted, all tests performed after a three minute power soak.
Test Level 1- 100010 production tested at the specified temperatures.
Test Level 11-1 00010 production tested at TaE25°C and sample tested at the specified temperatures.
Test Level 111- QA sample tested only at the specified temperatures.
Test Level IV - Parameter is guaranteed (but not tested) by design and characterization data.
Test Level V - Parameter is a typical value for information purposes only.

2-106

Honeywell

1

FIGURE 1. CONVERSION TIME CHARACTERISTICS

0
0

co
,...,...

1lfmax

-ClK
ClK

~)\

=x
~

DATA
OUTPUT

INTERNAL
lATCH

g

to

C

r=
X

~

tap

II
~

\

FIGURE 2. ACQUISITION TIME IS WORST CASE VALUE

RECONSTRUCTED OUTPUT

Honeywell

2·107

oo

DESCRIPTION

.ERROR REDUCTION

.....

The HADC77600 is a full parallel 10-bit, 50MSPS
(75MSPS Typical) flash converter with linearity trimmeCi
to ± 3/4 LSB and random error reduction to the LSB
level. It is designed with preamplifier inputs to each
comparator and !las an on-Chip input amplifier. Linearity
is trimmed to better than ± 3/4 LSB without affecting
temperature performance or reliability.
Data sheet
specifications include both time and frequency domain
data to assist the designer in making accurate predictions
of system performance.

All flash converters prior to the HADC77600 exhibit
random errors that are called metastable states or sparkle
codes. These errors have the possibility of occurring at
any speed or at any code. A similar error is signature
error, commonly referred to as glitches. They are most
likely to appear at mid, quarter or eighth scale points and
the possibility of these errors increases as the input
frequency increases. The latter is especially true at the
very highest input frequencies that the part is capable of
accepting, while random errors increase with clock
.
frequency at a rate that appears to be exponential.

<0

8
~

TRIMMING
The linearity of the HADC77600 is capable of being
The trimming is
trimmed to at least ±3/4 LSB.
accomplished by adjusting each of the comparator
offsets that is off by greater than 3/4 LSB. The trim sites
are set for bipolar adjustments so that either direction of
offset is capable of being trimmed. Adjustments are
done in discrete steps on metal link sites. This method
of trimming completely removes resistors from the circuit.
This results in a trim that does not affect either reliability
of long-term stability. Stability and reliability are not
effected because current carrying structures are not
altered, they are either left in the circuit or they are
completely removed. The resistor ladder is not altered in
any manner.

The HADC77600 addresses this problem in a new
manner. First a Gray code is used to decrease the
internal data synchronous noise. The Gray code also
allows the addition of circuitry after the comparators to
eliminate errors. The error detection is accomplished by
looking for the thermometer code output from the
comparators and making an error detection decision
based on the comparator outputs.
This thermometer code should have the specific form of
all comparators being in either a "0" or a "1" state, and all
codes above a certain point should be zeroes and all
below should be ones. If this does not occur then an
error will be detected. Once an error is detected, the
logic looks at a number of codes near the error code or
codes, and makes a logical deciSion of what the correct
code should have been. This logical decision can either
choose the correct code or it can be off by one LSB. For
this reason errors will not be any greater than 1 LSB.

TABLE 1. LOGIC TABLE
Data Format: OVR, 09, DB, D7 through DO
MINV
LINV

0
0

1
0

0
1

1
1

>+1.998V

1

1111111111

1

1000000000

0

0111111111

0

0000000000

+1.996V
+1.992V

0
0

1111111111
1111111110

0
0

1000000000
1000000001

1
1

0111111111
0111111110

1
1

0000000000
0000000001

O.OV
-0.004V

0
0

1000000000
0111111111

0
0

1111111111
0000000000

1
1

0000000000
1111111111

1
1

0111111111
1000000000

0111111110
-1.996V
0
0000000001
0
0111111111
<-1.998V
0
0000000000
0
Note: Voltages gIVen are the mid-pOint for the codes.
1 =VOH,O=VOL.

1
1

1000000001
1000000000

1
1

1111111110
1111111111

2-108

Honeywell

REFERENCE lADDER

INPUT AMPLIFIER

The ladder of the HADC77S00 is composed of 1023
metal resistors of approximately .S3 Ohms each and a
resistor of half that value at each end of the ladder. Each
resistor is actually a different value, with each value
calculated to offset the typical 25°C bias current value of
the preamplifiers. This results in a typical integral linearity
curve that has very little, if any bow due to the effects of
the summation of bias currents. The reference top and
bottom are both connected to sense pins to reduce the
offset of the ladder. In addition to the top and bottom
reference points to the ladder there are also external
taps to the ladder at 1/8 scale increments. These taps
can be used to maintain the ladder's linearity if operation
over a wide temperature range in required.

A wide bandwidth input amplifier has been provided for
driving the input to the flash converter. This amplifier has
an inverting gain of 4 to reduce the input swing from the
±2Volt full-scale input swings to ±500mV. If the amplifier
is not used, then the inputs should be tied to ground
and the output should be left floating.

The top reference to the ladder is typically driven to +2.0
Volts, and the bottom of the ladder to -2.00 Volts. These
points can be driven by any op amp that can supply SmA.
Care must be taken to assure that the amplifier offsets
and drifts are commensurate with the system deSign.
ladder taps can be driven in a similar manner if desired. If
they are not used they can be left open or by-passed to
VRTorVRB.
INPUT PREAMPLIFIERS

The input to each comparator is buffered by a
preamplifier to prevent currents caused by the dynamic
switching of the comparator latches from feeding back to
the input. These preamplifiers also isolate the ladder
from these same currents.

Honeywell

....
....

8
~

ClK AND ClK INPUTS

The clock inputs are designed to be driven with
differential ECl levels. Single-ended operation can be
accomplished by bypassing the ClK input, which is
internally biased to -1.3V, and driving ClK input.
OVER·RANGE

A better use for the ladder taps is in applications, where
the linearity of the ladder is to be changed to piece-wise
approximate a non-linear transfer function. This is often
done to increase the dynamic range of the converter.
Each ladder tap has been designed to handle the full
reference current so that a wide variety of curves can be
accommodated.

o
o

(0

The over-range output can be used to either alarm the
system when an over-range occurs or it can be used in
applications where the dynamic range of the system is to
be increased by stacking two converters. Over-range is
true when the top reference (VRT) is exceeded by V2
and lSB. The 1/2 rather than 1 lSB limit is the result of
the top ladder resistor being 1/2 the value of the other
ladder resistors.
OPERATING TEMPERATURE RANGE

The HADC77S00 is designed to operate over the full
military temperature range. A custom package with the
cavity down has been designed for the HADC77S00.
There is an internal heat sink built into the package. This
package has a GJA of approximately 30°CIW. This can be
reduced to 15°CIW by airflow at a rate of 500 lFPM
across the package. Further reduction can be obtained
by adding a heat sink.

2-109

a

0
0

FIGURE 3. BURN-IN SCHEMATIC

...ov

(SQOmA)

CO
,....

R1

un

A3

,S.an
• .an

aeon
l00Kn

R2

,....

R4
,HI

8

(U.

:z:

880Il
lKn
4Kll

R8

Rl

c(

R7
R8

cu. 010. G11, Cl, ca. 010. Cl1

1 WaH
114 WaH
114 WaH
112 Wait
112 WaH
114Woll
114 Wall
114 WaH

CC5%
CC5%
CC5%
CCtW.
CC5%
CC5%
CC5%
CC5%

VEE

R2
A1,.'

1----1

VRB
HDACmoa

IURNoIN BOARD
(100-'
FLAOH A/OJ

.........

:::
~\s."'Ie.
K7.1C8. A7.KI.
RI

~'~~"10.

L,

ClD

PIN . . . . . . .aTOPGA

LI'

De

LI

118

H1',D1.Dt.
DtO. D11 ••S.
Al,.',AI,At

LA

D7

KI

D6

1--+--_-1 AGND, DOND, AMPIN·
R7

LI

D6

D4

L7

os

LI

D2

LI

AMPlN+

R8

A11

L11

DO

AI,"

VIN

111

AMP OUT

+--.......-1

(100mA)

LlO

Dl

RI

...oV

AI

VRT

K,

MINV

".DV
(SOD",,)

LINV

R2

...oV

VCC

('DDmA)

..a.DV
(25IImA)
1,F2"F10.F11

FIGURE 4. 77600 DIE PLOT
IUJ UJUJ u.J l.I.J CD I I ]
DO [J

II] II] II]
[J VAT

0' [J

DO[J

[J

VAl

DO[J

[J VA.

D4[J

[J VA.

D. [J

g

'liN

8
B

... [J

MHD

D7[J
01

AMPOUT

[J

B'IIN

DB[J

[J VAl

010 [J
DONO

[J VAl

B
I I ] I I ] [J [J [J

[J YR,
II] II] II]

II] II] II]
ID

~

2·110

!
"

ill
>

Honeywell

HADC71600 PIN DESCRIPTION

o
o

<0

DescrIptIon

PIns
VEE

Analog and digital negative supply. Typically -5.2 Volts.

VBIAS

Supply voltage. Typically +2.0 Volts.

VCC

Positive digital supply. Typical¥ +5.0 Volts.

AGND

Analog ground.

g""""
«

::I:

DGND

Digital ground. Return for ECl outputs. Return to termination groun d.

VRT

Most positive reference. Typically +2.00 Volts.

VRTS

Sense pin for the positive referen ceo

VRB

Most negative reference. Typically -2.00 Volts.

VRBS

Sense pin for the negative reference.

VR1 thru VR7

Reference ladder taps in 1/8 scale increments for ladder adjustments.

LlNV

Data complement control for bits 0 through 8.

MINV

Data complement control for bits 9 and 10 (OVR).

a

AMPIN-

Inverting amplifier input.

AMPIN+

Non-inverting amplifier input.

AMPOUT

Amplifier output.

VIN

Flash converter input.

DO thru D9

Digital ECl outputs. Capable of driving 100 Ohm loads to 10KH specifications.

D10orOVR

Over-range bit. True when the input exceeds the voltage at VRT.
TOP VIEW

HADC77600 PIN OUT
K

c

Q

A

88888888880
8®8888888®8
88
88
88
88
88
88
88
88
88
88
88
88
88
88
8®8888888®8 ,.
88888888888
Dli

IIINV

NCl.K

QJ(.

VEE

VIMAS

vcc

AGND

VEE

VA.

VAEF

Of

DONI

DONO

AClNO

VEE

.... IM

YOO

AClNO

VEE

Viti

A....

DI

OOND

vu

AClND

Dr

DO..,

VAl

AMPOUT

011

DGND

MIND

YIN

De

DGNO

AQND

VIM

D4

DONO

VIM

AGND

D3

DOND

VAl

NIl'-

Dr

DB..,

VAl

AGND

ot

DOND

DGND

AGND

VEE

VBIAI

vee

AGND

VEE

VRr

AGND

DO

IXifIJ

UNV

AGND

VEE

't'B1AI

vee

AGND

VEE

VATS

YATF

11

* *For Ordering Information See Section 1.

Honeywell

2-111

NOTES:

2-112

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HADC78160

16-BIT, JlP COMPATIBLE HIGH PERFORMANCE AID CONVERTER
ADVANCE INFORMATION

FEATURES

APPLICATIONS

• 3JlS CONVERSION RATE
• Low Power - .9W
• Parallel, serial or 2-byte output configuration
• 16 or 8-bit JlP Compatible
• ±2.5V or±5V pin programmable input
• External or Internal clock

• Sonar
• Digital Scales
• Instrumentation
• Communications
• DSP Interface
• Acoustic Analysis

GENERAL DESCRIPTION
The HADC78160 is a 16-bit, hybrid successive approximation ND converter containing jlP compatible control
pins. It is capable of digitizing up to a ±5Volt analog signal
at an 3jlS conversion rate.
The device contains a 16-bit DAC, comparator, and a
successive approximation register that can output 16-bit
parallel, serial or 2-byte configuration. The part has an
internal clock but can be externally clocked if necessary.
The input voltage is pin programmable at either ±2.5V or
±5V full scale input ranges. The HADC78160 is fully jlP
compatible with all

the necessary control pins for various applications.
These include a ready to convert control, SAR busy flag,
external clock enable, convert start, serial data clock, tristate control for a high impedance output state, NRZ
serial output data option, LSBs and MSB invert, and
swap bytes output format. The outputs are TTL compatible. On-board power supply bypass capacitors add
additional noise immunity and a smaller overall decrete
parts count.
The part is packaged in a 40 Lead ,600 MIL Ceramic DIP
and operates on ±15V and +5V power supplies.

BLOCK DIAGRAM

Honeywell

2-113

o

ELECTRICAL SPECIFICATIONS

....
ex>

MILITARY TEMPERATURE RANGE

g

@ 25°C case temperature and nominal supplies.

<0

....

-I_-OINVERSE
VIDEO

,

~_...J

"s

FIGURE 7B

SINGLE OAtN CONTAOL

"L

751/

75\1

TEST LOAD

OUT+
OUT-

VIDEO OUT
Oto-IVOLT

"L

37.SU
1.3V

ISET

'=
--cx(R )+R
1

2

INDIVIDUAL GAIN CONTAOl

TYPICAL RGB GRAPHICS SYSTEM
In an RGB graphics system, the color displayed is
determined by the combined intensities of the red,
green and blue (RGB) D/A converter outputs. A change
in gain or offset in any of the RGB outputs will affect
the apparent hue displayed on the CRT screen.
Thus, it is very important that the outputs of the D/A
converters track each other over a wide range of
operating conditions. Since the D/A output is proportional to the product of the reference and digital input
code, a common reference should be used to drive all
three D/As in an RGB system to minimize RGB DAC-toDAC mismatch. This may also eliminate the need for
individual calibration of each DAC during production
assembly.
the HDAC10181 contains an internal precision bandgap reference which completely eliminates the need
for an external reference. The reference can supply up
to 50~ to an external load, such as another DAC
reference input.
The circuits shown in Figure 8 illustrate how a single
HDAC10181 may be used as a master reference in a
system with multiple DACs (such as RGB). The other
DACs are simply slaved from the HDAC10181's
reference output. The HDAC10180s shown are
especially well-suited to be slaved to a 10181, since
they are essentially 10181s without the reference. The
10180 is pin-compatible with the TDC1018, which like
the 10180, does not have an Internal reference.
Although either the TDC1018 orHDAC10180 may be
slaved from an HDAC10181, the higher performance
HDAC10180 is the best choice for new designs. (See
HDAC10180 Data Sheet)

3-24

FIGURE 9

BURN·IN CIRCUIT

--uv

,.

5."

-''Oo--------f
..

'01-----...,

..

.."'.....

,.

IMAX~

CLOCK

. ........
"

'.
UPINDfP

,...'"

ALL R£8 ARE 1% 'II " "
CLOCK. -1.1_ -1.hel'll

Honeywell

PIN ASSIGNMENTS

PIN FUNCTIONS

,..
,..
0,..
ex)

~
C

NAME

FUNCTION

03
02
01
DO
VEED
CONV
CONV

Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0 (LSB)
Digital Negative Supply
Convert Clock Input
Convert Clock Input Complement
Register Feedthrough Control
Digital Positive Supply
Data Force High Control
Video Blan.k Input
Video Bright Input
Video SYNC Input
Reference Output
Reference Current + Input
Compensation Input
OAnalog Positive Supply
Output Current Negative
Output Current Positive
Analog Negative Supply
Data Bit 7 (MSB)
Data Bit 6
Data Bit 5
Data Bit 4

D3

VEEA

CONY

FT

7

BLANK "

24 LEAD DIP

VCCD
FH
BLANK
BRT
SYNC
REF OUT
ISET
COMP
VCCA
OUTOU1;+
VEEA
07
06
05
04

* *For Ordering Information See Section 1.

Honeywell

3·25

I

II
I

NOTES:

3-26

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HDAC34010

TRIPLE 4-8IT, HIGH SPEED RASTER D/A CONVERTER
PRELIMINARY INFORMATION
APPLICATIONS

FEATURES
• 200 MWPS Conversion Rate
• Complete ROB D/A Solution
• RS-343-A Compatible
• Video Controls: Sync, Blank, Bright and
Reference White
• Registered for Low Glitch
• Single Power Supply
• On-chip Bandgap Reference

The HDAC34010 is a monolithic, triple 4-bit raster
digltal-to-analog (D/A) converter, complete with
special video controls, on-chip reference, registers,
and precision output termination. Only one device is
required for a complete RGB D/A system.
Four special video controls (Sync, Blank, + 10%
Bright and Reference White) allow full reconstruction
of RS-343-A compatible video signals from composite
Inputs. All data and control inputs are ECl compatible.

•
•
•
•
•
•

RGB Color Graphics
CAD/CAE
Instrumentation Displays
Medical Electronics: CAT, PET, NMR Displays
Business Computer Graphics
CRT Terminals

The HDAC34010 will directly drive a 75 Ohm coaxial
cable and monitor termination to standard video
levels.
The gain and output termination of each D/A is
precisely adjusted using a proprietary trimming procedure. The HDAC34010 is fabricated using an advanced VlSI bipolar process for excellent performance, low power consumption, and high reliability in
a choice of convenient packages.

BLOCK DIAGRAM
SYNC (R.G.I)

I~~

6

REFWH

RED
DATA

==4t:::.::::::>1

~-. . RED

GREEN
DATA

==4t=.::::>1

>-1-..

GREEN

ILUE,-==4t=::>I
DATA_

>-II--..

8I.UE

CLOCK----....I

Honeywell

DAC
RTN

3-27

II

Absolute Maximum Ratings (Beyond which the useful life will be Impalred)1
Supply Voltages ..
Vee(measuredtoDGNO) ...... " .... -7.0 to 0.5V
~ND(measuredtoDGND) ........... -0.5toO.5V

Temperatura
Operating, ambient .............. - 60 to
junction ............... ; .....
Lead, soldering (10 seconds) ..............
Storage , ..................... - 60 to.

+ 140°C
+ 175°C
+ 300°C
+ 150°C

Outputs
Analog Output (R, G and 8), applied voltage (measured to
~ND) .......................... - 3.0 to 3.0V
Analog Output (R, G and B), applied current2 ..... 60 mA
Output Short Circuit Duration ............. Unlimited
Not.s:
1. Operation at any Absolute Maximum Ratings is not Implied. See Electrical Specifications for proper nominal
applied conditions In typical applications.

COMMERCIAL TEMPERATURE RANGE
DIC PARAMETER

TEST
CONDITIONSI

MIN

TYP

MAX

UNITS

-5.2

-5.5

V

-345

-385

mA

0.0

+0.1

V

3

5

pF

0.5

V

75

79

Ohms

STATIC CHARACTISTICS
VEE

= 5.2V, fCLOCK = 200 MHz, Test Load Figure 6 unless otherwise specified

VEE

Supply Voltage
(Measured to DGND)

-4.75

lEE

Supply Current

DGNDAGND

Ground Voltage
Differential

CI

Input Capacitance, Clock
Data and Controls

VOC

Compliance Voltage

Note 2

-2

RO

Output Resistance

Note 2

71

Co

Output Capacitance

Note 2

15

20

pF

10

Maximum Output Current Note 2

28

30

mA

IlL

Input Current, Logic
LOW, Data and Controls

70

120

p.A

IIH

Input Current, Logic
HIGH, Data and Controls

90

150

p.A

-0.1

Note.:
1. Standard test load given in Figure 6.

3-28

2. Specification applies to each R, G and B DAC.

Honeywell

COMMERCIAL TEMPERATURE RANGE
Ale PARAMETER

TEST
CONDITIONSt

MIN

TYP

MAX

UNITS

DYNAMIC CHARACTISTICS
VEE = 5.2V, fCLOCK = 200 MHz, Test Load Figure 6 unless otherwise specified
FS

Maximum Conversion
Rate

to

Clock to Output Delay

Note 2

200

MWPS

225
4

5

ns

4

ns

2.5

ns

tST

Settling Time, ± 112 LSB

± 112 LSB3

tR

Rise Time

10% to 90% of
Gray Scale'

SR

Slew Rate

200

Vlp.s

tpWL

Clock Pulse Width, LOW1

2.0

ns

tpWH

Clock Pulse Width, HIGH1

2.0

ns

ts

Setup Time, Data and
Controls

2.0

1.5

ns

tHL

Hold Time, Data and
Controls

1.0

0.5

ns

Notes:
1. Standard test load given In Figure 6. Specification applies to each R, G and BOAC:
2. MWPS

= MegaWords Per Second. Setting time from 50% point to ± YzLSB Is 3.5ns Maximum.

3. ± Vz LSB = ±3.2% of Gray Scale.
4. Gray Scale

=Ivideo white level- video black level I = 600mv (nominal).

5. The minimum specified conversion rate is given in the Dynamic Characteristics section. The sum of tFYII. and tPWH must always equal or
exceed the minimum conversion cycle time.

DIC PARAMETER

TEST
CONDITIONSt

MIN

TYP

MAX

UNITS

SYSTEM PERFORMANCE
VEE = 5.2V, fCLOCK = 200 MHz, Test Load Figure 6 unless otherwise specified
ELI

Linearity Error
Integral, Terminal Based Note 2, 3

± 1.6

±3.2

%G.S.

ELD

Linearity Error,
Differential

±0.4

±0.8

%G.S.

IOF

Output Offset Current

± 10

p.A

±1

G.S.

±0.02

%G.src

Note 2, 4
DATA = SYNC =
BLANK = 1
BRIGHT = 0

EG

Absolute Gain Error

rCG

Gain Error Tempco

PSRR

Power Supply
Rejection Ratio

Supply to OutputS

Power Supply
Sensitivity

Supply to Output

PSS

Honeywell

±0.Q1
22

28
5

db
10

mVN

3-29

II

COMMERCIALTEMPIERATURE RANGE

o
.,..
o

-.:t

(I)

D/C PARAMETER

~

YEE = 5.2Y, fCLOCK

J:

TEST
CONDITIONS'

MIN

TYP

MAX

UNITS

SYSTEM PERFORMANCE

= 200 MHz, Test Load Figure 6 unless otherwise specified

Gy

Peak Glitch Yoltage

Note 6

2

5

mY

GE

Peak Glitch Area
("Energy")

Note 7

4

10

picaYolt-seconds

FTC

Feedthrough, Clock

-50

-45

dB

FTO

Feedthrough, Data

-70

-65

dB

YIL

Input Yoltage, Logic LOW

YIH

Input Yoltage, Logic HIGH

TA

Ambient Temperature'

TC

Case Temperature'

= Constant'
Clock = Constant'
Data

-1.65

Y
-0.95

Y

0

70

0

125

°c
°c

Notes:
1. Standard test load given in Figure 6. Specification applies to each R, G, and B DAC.
2. %G.S.

= Percent Gray Scale, where G.S. = Ivideo white level-video black level I =600mv (nominal).

3. ± 3.2% G.S.

= ± 112 LSB (Least Significant Bit).

4. ± 0.8% G.S. = ± 1/8 LSB (Least Significant Bit).
5. 20kHz, 600mV pop ripple superimposed on VEE or V~ dB relative to full G.S. = OdB.
6. Peak Glitch Voltage Is the maximum voltage deviation from ideal voltage during the glitch period.
7. Glitch Area (voltage x time) Is sometimes referred to as an "energy", although this is not dimensionally correct. The Peak Glitch Area Is
the maximum area deviation from the Ideal output. Since glitches are typically "doublets" of symmetric positive and negative excursions, the average glitch area approaches zero.

8. dB relative to full G.S. = OdB, 300M Hz bandwidth limit.
9. 500 LFPM moving air required above TA = 50·C; /leA = 30· CIW Typical at 500 LFPM.

ELECTRICAL CHARACTERISTICS TESTING

TEST LEVEL TEST PROCEDURE

All electrical characteristics are subject to the following conditions:
All parameters having Mln.lMax. specifications are
guaranteed. The Test Level column indicates the specific
device testing actually performed during production and
Quality Assurance Inspection. Any blank sections In the data
columns indicates that the specification Is not tested at the
specified conditions.
Unless otherwise noted, all tests are pulsed tests, therefore
Tj = Tc
Ta'

=

3-30

100% production tested at the specified
temperature.

=

II

100 % production tested at Ta 25 ·C, and
sample tested at specified temperature.

III

QA sample tested per QA test plan TAl 00.

IV

Parameter Is guaranteed (but not tested) by
design and characterization data.

V

Parameter is a typical value for information
purposes only.

Honeywell

GENERAL INFORMATION
The HDAC34010 is especially suited for Red-GreenBlue (RGB) color raster applications. The HDAC34010
comprises three complete 4-bit digital-to-analog converters (DACs), precision bandgap reference, input
data registers, decoding logiC, video controls, and 75
Ohm source output termination as shown In the Functional Diagram. Each DAC has independent data and
control Inputs, with the exception of video Blank
Bright, and Reference White, which are common to ali
three converters. Parallel data input registers are provided for each DAC. A single Clock input synchronizes
the video data entry and conversion cycle for all three
converters. All data, clock, and control inputs of the
HDAC34010 are compatible with standard EmilterCoupled Logic (ECL).

The video control inputs (Sync, Blank, Bright and
Reference White) are used for reconstruction of RS343-A compatible signals from video control inputs.
Video setup level (the difference between video black
and video blank) may be programmed for 0,10, or 20
IRE units, depending on the condition of the Setup
Select control.

o
,...
o
v
('I)

~J:

The HDAC34010 utilizes a partially segmented approach whereby the upper 2 MSBs (Most Significant
Bits) are decoded into a parallel code which drive individual and identical current switches. The advantage
of this approach is that currents are added sequentially as codes increase, thereby eliminating the switching in and out of currents (as with straight binaryweighted DACs). This technique reduces glitching and
Improves linearity and other performance character-

II
I

FUNCTIONAL DIAGRAM

SYNC (R.G.BI

B~~~

6

REFWH

RED _--:"~_.J'o"...1
DATA _....:jI4'--_...........

-""""'4

GREEN
>/--...J'oo...
DATA - - 1 ' - - . . , /

BLUE -"""'-4~--"..
DATA ---'J'---~

>--_-+-RED
7111

> - t - o p - - + GREEN
7111

~.j---"'BLUE
750

CLOCK _ _ _ _ _ _....J

Honeywell

3-31

The A, G, and B analog outputs are designed to directly
drive a 75 Ohm transmission system as shown. The
source impedances of the HDAC34010's AGB outputs
are factory·trimmed to 75 Ohms +1- 5%, thus
eliminating the need for an external source·
termination resistor. The AGB load impedance (Al)
must be 75 Ohms to attain standard AS·343·A video
levels. Any deviation from this Impedance will affect
the resulting video output levels proportionally. As with
the data Interface, It is important that the analog
transmission lines have matched impedance
throughout, including connectors and transitions bet·
ween printed wiring and coaxial cable. The comblna·
tlon of matched source termination resistor As and
load terminator Al minimizes reflections of both for·
ward and reverse travelling waves In the analog
transmission system. The return path for analog out·
put current is DAC RTN, which is connected Internally
to the source·termlnatlon resistors, As.

APPLICATIONS CIRCUIT DISCRIPTION
A typical Interface olrcult using the HDAC34010 in an
AGB color raster application Is shown in Figure 1 AlB.
Although the HDAC34010 requires few external com·
ponents and Is extremely easy to use, there are
several considerations that should be noted to achieve
best performance. The very high operating speeds of
the HDAC34010 require good circuit layout, decoup·
ling of supplies, and proper design of transmission
lines.

I
!

Video input data and controls may be directly con·
nected to the HDAC34010. Note that all ECl Inputs are
terminated as close to the device as possible to
reduce ringing, crosstalk and reflections. A conve·
nlent and commonly used microstrip impedance is
about 130 Ohms, wtiich is easily terminated using a
330 Ohm resistor to VEE and 220 Ohm resistor to
Ground. This arrangement gives a Thevenin
equivalent termination of 130 Ohms to - 2 Volts
without the need for a 2 Volt supply. Standard SIP
(Single Inllne Package) 220/330 resistor n.etworks are
available for this purpose.

No external reference Is required for operation of the
HDAC34010, as this function Is provided Internally.
The Internal reference Is a bandgap type and is
suitable for operation over extended temperature
ranges.
The HDAC34010 operates from a single standard
- 5.2 Volt supply. Proper bypassing of the supplies will
augment the HDAC34010's Inherent supply noise reo
jectlon characteristics. As shown, a large value Tan·
talum capacitor In parallel with smaller ceramic
capacitors Is recommended for best performance.
The small·valued capacitors should be connected as
close to the device package as possible, whereas the
tantalum capacitor may be placed up to a few Inches
away.

It Is recommended that the stripllne or microstrip
techniques be used for all ECl interface. Printed clr·
cult wiring of known impedance over a solid ground
plane Is recommended. The ground plane shoUld be
constructed such that analog and digital ground cur·
rents are Isolated as much as possible. The
HDAC34010 provides separate digital and analog
ground connections to simplify grounding layout.

FIGURE 1A

HDAC34010 TYPICAL INTERFACE CIRCUIT
CLOCK

OE.
PIXEL
DATA
ON

I

>---;rT-.....~~n::''1
7
8

10

8D.

PIXEL
DATA

•

IN

8D1

OSY

INPUTS

-----~

•

IN

VIDEO

I

OD1

PIXEL
DATA

CONTROL

VIDEO DISPLAY

0.'
0.3
0.2

GREEN

BLUE

,.-----------..

.

GSYNC
BSYNC

BLANK
BRIGHT
AEFWH

12
1
14
15

8
11

18
"
•

21

25

L.....,:g,~~~'!:c~ NOT CONNECTED .. 10lRE
L .. FERRITE BEAD INDUCTOR
FAIR·RITE PIN 274300111
OR SIMILAR

AGND

3·32

-5.2V

--w--- ..

Eel TERMINATION

Honeywell

FIGURE 1B

TYPICAL RGB GRAPHICS SYSTEM

.-- --- ---- ---R,G,.1IONfTOIII

I

COAX

,I

RID

4

CRT

HDAC34010

."IGHT
CLOC.
I

I
II
II

II

II
I'

I 1_ _ _ _ _ _ _ _ _ _ !Yf!.C _ _ _ _ _ _ _ _ _ _ _ _ _ I I

......

--------------------------~

I

lUI

The timing diagram for the HDAC34010 is shown In
Figure 2. Data to all three DACs (Red, Green, and Blue) Is
simultaneously entered on the rising edge of the clock.
Data must be valid for a setup time of ts before, and for a
hold time of tH after the rising edge of the clock, In order
to be correctly entered. The DAC outputs will change In
accordance to the clocked input data after a delay time
of to. The settling time Is specified as the time from when
the DAC output Is no longer within Yz LSB of the previous
value until It is within Yz LSB of the new value.
The video control inputs cause the DAC outputs to
change directly, without regard to the clock input. All
video controls (Sync, Blank, Bright and Reference White)
are active-Low (negative true) logic. Figure 3 illustrates
the operation of Sync and Blank inputs and the resulting
video output signal. As shown, both Sync and Blank must
be Low to achieve the proper video Sync level. The video
control input hierarchy is given in Table 1, with typical
output levels for a setup level of 10 IRE.
Setup level is the difference between video Blank and
Black levels. The HDAC34010 supports setups of 0, 10.
and 20 IRE, which are programmed by connecting the
Setup select input to ground (OV), not connected, or to VEE
(- 5.2V), respectively. For most applications the 10 IRE
option is suitable.

Honeywell

The Reference White input forces the DAC outputs to an
all "1"s level, which Is video "white" in most systems.
This Is especially useful for clearing the display screen to
white during system reset or power-up. The Bright Input
adds 10% of full-scale video to the present video level.
The Bright feature Is commonly used for highlighting cursors Or creating overlays of video Information. Sync,
Blank and Reference White override the RGB data Inputs, while Bright may be applied to any video level.

FIGURE 2

TIMING DIAGRAM

-1.29V

-1.29V

~'~+~UTI------+--I-+--+----OV
± v~ lSB

3-33

Table 1 Video Control Operation (Output values for Setup
standard load)
Sync

Blank

0

0
0

Ref WhIte

Bright

Dlt.lnput

OutM

Out (IRE)

XXXX

-1.028
-0.742

-40
0

1
0

xxxx

-0.071
0.0

84
94

Normal Whlta Level
Enhancad Whlta Level

1
0

1111
1111
0000

-0.071
0.0
-0.671

84
94
10

0000

-0.&00

20

Normal Whlta Level
Enhancad White Level
Normal Black Level
Enhancad Black Level

xxxx
0
0

=10 IRE and7S Ohm

XXXX

0

Deacrlptlon
Sync Level
Blank Level

Note,:
1. All Video Controls are active-Low (negative true) logic.
2. Sync and Blank output levels are dependent on setup level selected. Values Indicated are for setup
connected).

= 10 IRE (setup select left un-

3. Sync level requires that both Sync and Blank = O.
4. 140 IRE

= 1.00 Volts.

5. All control values are subject to tolerance of ± 2% Gray Scale.

Setup Select
Setup Control Input

Setup Level

oVolts (GND)
Not Connectad
- 5.2 Volls (VeE)

OIRE
lOIRE
20 IRE

FIGURE 3 VIDEO OUTPUT WAVEFORM FOR STANDARD LOAD & 10 IRE SETUP
DESCRIFflON

NORMAL WHITE

BlACK LEVEL

BLANKLEVEL ___

-

-

-

-

-

-

--

'RE

-71

84

-671

'0

-742

SYNC lEVEL ____

BLANK INPUT

SYNC INPUT

3-34

.

mV

-40

-1.2W

-1.29V

Honeywell

FIGURE 4

EQUIVALENT INPUT CIRCUIT, DATA, CLOCK & CONTROL

....oo

DV

"it

----~---1~------------------DGND

(t)

~
C

J:

Eel
IN

II

5DK

~ IBIAS
___~_ _ _..-__-....;5....;.2;.;,V_ _ VEE

FIGURE 5

DAC OUTPUT CIRCUIT

A,G,B
OUT

•••

- - -.......-----flf----~~- VEE

Honeywell

3·35

....oo

~

FIGURE6B TEST LOAD

FIGURE 6A STANDARD LOAD
HDAC34010

~

VIDIOOtIPLAY

1---------.-I
I
I
I

J:

I

7111

7111

".

7IQ

".
710

I
I

I
I
I

711l

".

I
I
I __________ I
1-

PIN FUNCTIONS
PIN ASSIGNMENTS

DGND
RD4

RED
2

27

GREEN

NAME

FUNCTION

DGND

Digital Ground
R Data Bit 4 (LSB)
R Data Bit 3
R Data Bit 2
R Data Bit 1 (MSB)
Red Composite Sync Input
G Data Bit 4 (LSB)
G Data Bit 3
G Data. Bit 2
G Data Bit 1 (MSB)
Green Composite Sync Input
B Data Bit 4 (LSB)
B Data Bit 3
B Data Bit 2
B Data Bit 1 (MSB)
Blue Composite Sync Input
Negative Supply Voltage Input ( - 5.2V)
Video Blank Input
+ 10% Bright Input
Conversion Clock Input
Reference White Input
Analog Ground
Digital Ground
DAC Return
Video Set-up Select
Blue DAC Video Output
Green DAC Video Output
Red DAC Video Output

RD4
RD3
RD2

RDl
RED SYNC
GD4

RD3

3

26

BLUE

RD2

4

25

SET-UP

GD3

(MSB) RDl

5

24

DAC RTN

GD2

RED SYNC

6

23

DGND

GDl

GD4

7

22

AGND

GD3

8

21

REFWH

GRN SYNC
BD4

GD2

9

20

CLOCK

BD3
BD2

(MSB) GDl

10

19

BRT

GRN SYNC

11

18

BLANK

BLUE SYNC

BD4

12

17

VEE

VEE

BD3

13

16

BLUE SYNC

BD2

14

15

BDl (MSB)

BLANK
BRT
CLOCK
REFWH

28 LEAD DIP

BDl

AGND
DGND

* *For Ordering Information See Section 1.
3-36

DAC RTN
SET-UP
BLUE
GREEN
RED

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HDAC34020

TRIPLE 4-8IT, HIGH SPEED RASTER D/A CONVERTER
PRELIMINARY INFORMATION
FEATURES

APPLICATIONS

• 100 MWPS Conversion Rate
• Complete RGB D/A Solution

•
•
•
•
•
•

• RS·343·A Compatible
• Video Controls: Sync, Blank, Bright and
Reference White
• Registered for Low Glitch
• Standard + 5, - 5.2V Supplies
• On·chip Bandgap Reference
• TIL Compatible
• Immune to Power·On Latchup

The HDAC34020 is a monolithic, triple 4·bit raster
dlgltal·to·analog (D/A) converter, complete with
special video controls, on·chip reference, registers,
and precision output termination. Only one device is
required for a complete RGB D/A system.
Four special video controls (Sync, Blank, + 10%
Bright and Reference White) allow full reconstruction
of RS·343·A compatible video signals from composite
inputs. All data and control Inputs are TIL compatible.

RGB Color Graphics
CAD/CAE Workstations
Instrumentation Displays
Medical Electronics: CAT, PET, NMR Displays
Business Computer Graphics
CRT Terminals

The HDAC34020 will directly drive a 75 Ohm coaxial
cable and monitor termination to standard video
levels.
The gain and output termination of each D/A Is
precisely adjusted using a proprietary trimming pro·
cedure. The HDAC34020 is fabricated using an ad·
vanced VLSI bipolar process for excellent perfor·
mance, low power consumption, and high reliability in
a choice of convenient packages.

BLOCK DIAGRAM

6

SYNC (R.G.BI

B~:~
REFWH

RED=~~::::::>I
DATA

GREEN
DATA

==4t::.~>1

BLUEi-=::Jt=:::>I
DATA_

~-. . RED

>-+-_ GREEN

>-1-..

BWE
DAC

CLCCK----.....J

Honeywell

RTN

3·37

D.

Absolute Maximum Ratings (Beyond which the useful life will be Impaired)l
Supply Voltages

Temperature

VEE(measuredtoOGNO) ............ -7.0 to 0.5V
Vee (measured to 0GN D), ......... + 7.0 to - 0.5V
AG NO (measured to 0 GNO) ........... -'05to05V
.
.

Operating,ambient .............. -60 to
junction .....................
Lead,soldering(10seconds) ............ "
Storage ...................... -60 to

+140°C
+ 175°C
+ 300°C
+ 150°C

Outputs
Analog Output (R, G and B), applied voltage (measured to
~NO) .......................... - 3.0 to 3.0V
Analog Output (R, G and B), applied current 2 ..... 60 mA
Output Short CircuitDuration ............. Unlimited

Notes:
1. Operation at any Absolute Maximum Ratings is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications.

COMMERCIAL TEMPERATURE RANGE
D/C PARAMETER

TEST
CONDITIONS1

MIN

TYP

MAX

UNITS

-4.75

-5.2

-5.5

V

4.75

5.0

5.25

V

STATIC CHARACTISTICS
= 5.2V, fCLOCK = 200 MHz, Test Load Figure 6 unless otherwise specified

VEE

VEE

Negative Supply Voltage
(Measured to 0GNO)

Vee

Positive Supply Voltage
(Measured to 0GNO)

lEE

Negative Supply Current

-345

-385

mA

ICC

Positive Supply Current

26

40

mA

°GNO"
AGNO

Ground Voltage
Differential

0.0

+0.1

V

CI

Input Capacitance, Clock
Data and Controls

3

5

pF

0.5

V

75

79

Ohms

15

20

pF

-0.1

VOC

Compliance Voltage

Note 2

-2

RO

Output Resistance

Note 2

71

Co

Output Capacitance

Note 2

10

Maximum Output Current Note 2

IlL

Input Current, Logic
LOW, Data and Controls

IIH

Input Current, Logic
HIGH, Data and Controls

28

30

mA

-1.30

-0.5

mA

0

100

p.A

Notes:

1. Test load given in Figure 68

3·38

2. Specification applies to each R. G and 8 DAC.

Honeywell

AlC PARAMETER

TEST
CONDITIONS'

MIN

TYP

MAX

UNITS

DYNAMIC CHARACTISTICS
VEE

= 5.2V, fCLOCK = 200 MHz, Test Load Figure 6 unless otherwise specified

FS

Maximum Conversion
Rate

tD

Clock to Output Delay

tST

Settling Time

tR

Rise Time

SR

Slew Rate

tpWL

Note 2

100

125

± Y2 LSB to ± '12
LSB3

MWPS

4

5

ns

3

4

ns

2.5

ns

10% to 90% of
Gray Scale'
200

V/p.s

Clock Pulse Width, LOW1

4

ns

tpWH

Clock Pulse Width, HIGH

4

ns

ts

Setup Time, Data and
Controls

3

2

ns

tHL

Hold Time, Data and
Controls

2

1

ns

Notes:
1. Test load given in Figure 6B. Specification applies to each R, G and B DAC.

= MegaWords Per Second. Setting time from 50 % paint to ± 'I. LSB is 3.5ns Maximum.
± 'I. LSB = ± 3.2 % of Gray Scale.
Gray Scale =Ivideo white level· video black level I = 600mv (nominal).

2. MWPS
3.
4.

5. The minimum specified conversion rate is given in the Dynamic Characteristics section. The sum of tPWL and tPWH must always equal or
exceed the minimum conversion cycle time.

DIC PARAMETER

TEST
CONDITIONS'

MIN

TYP

MAX

UNITS

SYSTEM PERFORMANCE
= 5.2V, fCLOCK = 200 MHz, Test Load Figure 6 unless otherwise specified

VEE

Linearity Error
Integral, Terminal Based

Note 2, 3

± 1.6

±3.2

%G.S.

ELD

Linearity Error,
Differential

Note 2, 4

±0.4

±0.8

%G.S.

IOF

Output Offset Current

±10

pA

±1

G.S.

±0.02

%G.src

ELI

DATA = SYNC =
BLANK = 1
REF WH = BRT = 0

EG

Absolute Gain Error

TCG

Gain Error Tempco

PSRR

Power Supply
Rejection Ratio

Supply to OutputS

Power Supply
Sensitivity

Supply to Output

PSS

Honeywell

±0.01
22

28

5

db
10

mVIV

3·39

DIC PARAMETER

EST
.
ONDITIONS1

MIN

TYP

MAX

UNITS

SYSTEM PERFORMANCE
VEE = 5.2V, 'CLOCK = 200 MHz, Test Load Figure 6 unless otherwise specified
GV

Peak Glitch Voltage

Note 6

2

5

mV

GE

Peak Glitch Area
("Energy")

Note 7

4

10

picoVolt-seconds

FTC

Feedthrough, Clock

-50

-45

dB

FTO

Feedthrough, Data

-70

-65

dB

VIL

Input Voltage, Logic LOW

VIH

Input Voltage, Logic HIGI-

TA

Ambient Temperature 2

TC

Case Temperature 2

= Constant"
Clock = Constant"
Data

0.8

V
2.4

V

0

70

·C

0

125

·C

Notes:
1. Standard test load given in Figure 6. Specification applies to each R, G, and B DAC.
2. %G.S. = Percent Gray Scale, where G.S. = Ivideo white level-video black levelJ = 600mv (nominal).
3. ± 3.2 % G.S. = ± 1/2 LSB (Least Significant Bit).

4. ± 0.8 % G.S. = ± 1/8 LSB (Least Significant Bit).
5. 20kHz, 600mV pop ripple superimposed on VEE or Vcr;; dB reiative to full G.S. = OdB.
6. Peak Glitch Voltage is the maximum voltage deviation from ideal voltage during the glitch period.
7. Glitch Area (voltage x time) is sometimes referred to as an "energy", although this is not dimensionally correct. The Peak Glitch Area is
the maximum area deviation from the ideal output. Since glitches are typically "doublets" of symmetric positive and negative excursions, the average glitch area approaches zero.

8. dB relative to full G.S. = OdB, 300M Hz bandwidth limit.
9. 500 LFPM moving air required above TA = SO'C; 8CA = 30' CNoI Typical at 500 LFPM.

ELECTRICAL CHARACTERISTICS TESTING

TEST LEVEL TEST PROCEDURE

All electrical characteristics are subject to the following conditions:
All parameters having Min.lMax. specifications are
guaranteed. The Test Level column indicates the speCific
device testing actually performed during production and
Quality Assurance inspection. Any blank sections in the data
columns indicates that the specification is not tested at the
specified conditions.
Unless otherwise noted, all tests are pulsed tests, therefore
Tj = Tc = Ta'

3·40

100% production tested at the speCified
temperature.
ii

100% production tested at Ta =2S o C, and
sample tested at specified temperature.

ill

QA sample tested only at specified
temperatures

iV

Parameter is guaranteed (but not tested) by
design and characterization data.

V

Parameter is a typical value for information
purposes only.

Honeywell

GENERAL INFORMATION

The video control inputs (Sync, Blank, Bright and
Reference White) are used for reconstruction of RS343-A compatible signals from video control inputs.
Video setup level (the difference between video black
and video blank) may be programmed for 0, 10, or 20
IRE units, depending on the condition of the Setup
Select control.

The HDAC34020 is especially suited for Red-GreenBlue (RGB) color raster applications. The HDAC34020
comprises three complete 4-bit digital-to-analog converters (DACs), precision bandgap reference, input
data registers, decoding logic, video controls, and 75
Ohm source output termination as shown in the Functional Diagram. Each DAC has independent data and
control inputs, with the exception of video Blank,
Bright, and Reference White, which are common to all
three converters. Parallel data input registers are provided for each DAC. A single Clock input synchronizes
the video data entry and conversion cycle for all three
converters. All data, clock, and control inputs of the
HDAC34020 are compatible with standard Transistor
-Transistor Logic (TIL).

The HDAC34020 utilizes a partially segmented approach whereby the upper 2 MSBs (Most Significant
Bits) are decoded into a parallel code which drive individual and identical current switches. The advantage
of this approach is that currents are added sequentially as codes increase, thereby eliminating the switching in and out of currents (as with straight binaryweighted DACs). This technique reduces glitching and
improves linearity and other performance
characteristics.

FUNCTIONAL DIAGRAM

HDAC34020
CLOCK

RED
PrxEL:=¥~~~
DATA

>---t--t---- RED

IN

>-+t+-t----GREEN
DAC

RTN

>-+-t+-t----"'UE

VIDEO:~~:::::)t

CONTROL

INPUTS

-INDICATES TRIM

Honeywell

3-41

APPLICATIONS CIRCUIT DISCRIPTION

must be 75 Ohms to attain standard RS-343-A video
levels. Any deviation from this impedance will affect
the resulting video output levels proportionally. As with
the data interface, it is important that the analog
transmission lines have matched impedance
throughout, including connectors and transitions between printed wiring and coaxial cable. The combination of matched source termination resistor Rs and
ioad terminator Rl minimizes reflections of both forward and reverse travelling waves in the analog
transmission system. The return path for analog output current is DAC RTN, which is connected internally
to the source-termination resistors, Rs.

A typical interface circuit using the HDAC34020 in an
RGB color raster application is shown in Figure 1 AlB.
Although the HDAC34020 requires few external components and Is extremely easy to use, there are
several considerations that should be noted to achieve
best performance. The very high operating speeds of
the HDAC34020 require good circuit layout, decoupling of supplies, and proper design of transmission
lines.

TIL video input data and controls may be directly connected to the HDAC34020. It is recommended that
stripllne or microstrip techniques be used for all TIL interface. Printed circuit wiring of known impedance
over a solid ground plane is recommended. The
ground plane should be constructed such that analog
and digital ground currents are Isolated as much as
possible. The HDAC34020 provides separate digital
and analog ground connections to simplify grounding
layout.

No external reference is required for operation of the
HDAC34020, as this function Is provided internally.
The internal reference Is a bandgap type and is
suitable for operation over extended temperature
ranges.

The R, G, and B analog outputs are deSigned to directly
drive a 75 Ohm transmission system as shown. The
source impedances of the HDAC34020's RGB outputs
are factory-trimmed to 75 Ohms ± 5 %, thus
eliminating the need for an externai sourcetermination resistor. The RGB load impedance (Rl)

FIGURE 1A

The HDAC34020 operates from standard + 5 and
- 5.2 Volt supplies. Proper bypassing of the supplies
will augment the HDAC34020's inherent supply noise
rejection characteristics. As shown, a large value Tantalum capacitor in parallel with smaller ceramic
capacitors is recommended for best performance.
The small-valued capacitors should be connected as
close to the device package as possible, whereas the
Tantalum capaCitor may be placed up to a few Inches
away.

HDAC34020 TYPICAL INTERFACE CIRCUIT

CLOCK

RED
PIXEL

DATA
IN
OAEEN
PIXEL
DATA

...

D"
.D3

....,

• DI

BLUE

..,

DATA

IN

VIDEO DISPLAV

I

R"
ROJ
RD'
RDI

IN
PIXEL

,.----------_....-_.....

.

D3

7

•
,.•
.."
1

16

N
VIDEO
CONTROL
INPUTS

OSYN

11

lUll HT
REFWH

"
"

•N
BLANK

Vee
+5V

16
1

'''''r

* INDICATES
TRIM

"

!....-i:~~i1';!~~T;-

NOT CONNECTED - 10lAE

L • FEFlFlITE BEAD INDUCTOR
FAIR·RITE PIN 27.300111
OR SIMILAR
A GND

3-42

DeND

- UV

Honeywell

FIGURE 18

TYPICAL RGB GRAPHICS SYSTEM
IUI,-MONITOR

.....

,,.--------- -----,,,
,,,
,
,

HD

I

......

HDAC34020

.IIT

_1fT

,, .............
II
II

,.--

II
II

~I:::::::::: .......
::::::::: :=::: :1_:

The timing diagram for the HDAC34020 is shown in
Figure 2. Data to all three DACs (Red, Green, and Blue)
is simultaneously entered on the rising edge of the
clock. Data must be valid for a setup time of t5 before,
and for a hold time of tH after the rising edge of the
clock, In order to be correctly entered. The DAC outputs will change in accordance to the clocked input
data after a delay time of to. The settling time is
specified as the time from when the DAC output is no
longer within Y2 LSB of the previous value until it is
within Y2 LSB of the new value.

The Reference White input forces the DAC outputs to
an all "1"s level, which is video "white" in most
systems. This Is especially useful for clearing the
display screen to white during system reset or powerup. The Bright input adds 10% of full-scale video to the
present video level. The Bright feature is commonly
used for highlighting cursors or creating overlays of
video information. Sync, Blank and Reference White
override the RGB data inputs, while Bright may be applied to any video level.

FIGURE 2

TIMING DIAGRAM

The video control inputs cause the DAC outputs to
change directly, without regard to the clock input. All
video controls (Sync, Blank, Bright and Reference
White) are active-Low (negative true) logic. Figure 3 illustrates the operation of Sync and Blank inputs and
the resulting video output signal. As shown, both Sync
and Blank must be Low to achieve the proper video
Sync level. The video control input hierarchy is given in
Table 1, with typical output levels for a setup level of 10
IRE.
Setup level is the difference between video Blank and
Black levels. The HDAC34020 supports setups of 0,
10, and 20 IRE, which are programmed by connecting
the Setup select input to ground (OV), not connected,
or to Vee ( - 5.2V), respectively. For most applications
the 10 IRE option is suitable.

~~+~UT·I-------1--+-+-+----0V

r;;-;:;-lSB

Honeywell

3·43

Table 1 Video Control Operation (Output values for Setup = 10 IRE and 75 Ohm
standard load)
Sync

Blank

0

Ref White

Data Input

Out (V)

Out (IRE)

XXXX
XXXX

-1.028
-0.742

-40
0

1
0

XXXX
XXXX

-0.071
0.0

84
94

Normal White Level
Enhanced White Level

1
0

1111
1111
0000
0000

-0.071
0.0
-0.671
-0.600

84
94
10
20

Normal White Level
Enhanced WMe Level
Normal Black Level
Enhanced Black Level

Bright

0
0
0
0

0

Description
Sync.Level
Blank Level

Notes:
1. All Video Controls are active-Low (negative true) logic.
2. Sync and Blank output levels are dependent on setup level selected. Values indicated are for setup

connected).

= lOIRE (setup select left un·

3. Sync level requires that both Sync and Blank = O.
4. 140 IRE

= 1.00 Volts.

5. All control values are subject to tolerance of ± 2% Gray Scale.

Setup Select
Setup Level

Setup Control Input

oVolts (GND)

OIRE
lOIRE
20 IRE

Not Connected
-5.2VoIIS(VEE)

FIGURE 3 VIDEO OUTPUT WAVEFORM FOR STANDARD LOAD & 10 IRE SETUP
IRE

"

-671

10

-742

-40

SYNC LEVEL

V"
BLANK INPUT

----- -

VIL
V"

SYNC INPUT
VIL

3-44

HoneyWell

FIGURE 4

EQUIVALENT INPUT CIRCUIT, DATA, CLOCK & CONTROL

+5V

--,.--t------'---

VCC

6k

TIL
IN

'SCHOTIKY

FIGURE 5

DAC OUTPUT CIRCUIT

R,G,B
OUT
7SQ
RS
DAC

RTN

---~---"'r-----4---VEE

Honeywell

3·45

FIGURE 6A

FIGURE 68 TEST LOAD

STANDARD LOAD

HDAC34020
VtDEODISPUY

1----------I
I
I

I
I

,m

,50

...

...".
...
COAX

I
I
I

'IG

".

I
I
I
I
I
1______ - - - - -

PIN FUNCTIONS

PIN ASSIGNMENTS

vcc

RED

NAME

FUNCTION

vee

Positive Supply Voltage Input (+ 5V)
R Data Bit 4 (LSB)
R Data Bit 3
R Data Bit 2
R Data Bit 1 (MSB)
Red Composite Sync Input
G Data Bit 4 (LSB)
G Data Bit 3
G Data Bit 2
G Data Bit 1 (MSB)
Green Composite Sync Input
B Data Bit 4 (LSB)
B Data Bit 3
B Data Bit 2
B Data Bit 1 (MSB)
Blue Composite Sync Input
Negative Supply Voltage Input ( - 5.2V)
Video Blank Input
+ 10% Bright Input
Conversion Clock Input
Reference White Input
Analog Ground
Digital Ground
DAC Return
Video Set-up Select
Blue DAC Video Output
Green DAC Video Output
Red DAC Video Output

RD4
RD3
RD2

RD4

2

27

GREEN

RD3

3

26

BLUE

RD2

4

25

SET-UP

RDl

(MSB) RD1

5

24

DAC RTN

RED SYNC

6

GD4

7

22

AGND

8

21

REFWH

RED SYNC
GD4
GD3
GD2
GD1
GRN SYNC

GD3

DGND

GD2

9

(MSB) GD1

10

BRT

BD4

GRN SYNC

11

BLANK

BD3

BD4

12

VEE

BD3

13

BLUE SYNC

BD2
BDl

BD2

14

BD1 (MSB)

CLOCK

28 LEAD DIP

BLUE SYNC
VEE

BLANK
BRT
CLOCK
REFWH
AGND
DGND

* *For Ordering Information See Section 1_

3-46

DAC RTN
SET-UP
BLUE
GREEN
RED

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HDAC50500

12-BIT MONOLITHIC MDAC WITH FULL flP INTERFACE
ADVANCE INFORMATION
FEATURES:

APPLICATIONS:

• Directly Interfaces to Intel and Motorola 8-Bit Microprocessors Without Additional Glue Logic
• Input Data Latches
• 12-Bit Linearity ± 1/2 LSB (End Point Over
Temperature Range)
• SOOns Output Settling Time
• 4 Quadrant Multiplication
• Single Supply Operation

•
•
•
•

Industrial Automation
Process Control
Bus Structured Instrumentation
Microprocessor Controlled Gain/Function Circuits

GENERAL DESCRIPTION
The HDACSOSOO is a 12-bit multiplying digital-to-analog
converter that will interface directly to most 8-bit
microprocessors with no additional glue logic required.
Both Motorola's MPX'ed and non-MPX'ed bus formats as
well as Intel's MPX'ed bus format are supported.
Performance specifications of ±1/2 LSB maximum
nonlinearity, ±1/2 LSB maximum gain error and SOOns
typical output settling time (AIG grade) are the best in the

industry!
Additionally, timing speCifications are the
fastest currently available thus allowing more effiCient
usage of today's faster microprocessors.
This part is manufactured using Honeywell's Bipolar
Enhanced CMOS (BEMOS) process. This process
allows the combination of dense high speed digital logic
with precision analog circuitry, all on a single monolithic
Chip.

BLOCK DIAGRAM

Honeywell

3·47

810
o

SPECIFICATIONS

(Vee

=5V,

VREF

=10V)

Over Temperature Range Specified Below. Unless Otherwise Indicated

10

~J:

Parameter

Test
Conditions

Test
HDAC50500AlG HDACS0500A HDAC50500B
Level (1) Min Nom Max Min Nom Max Min Nom Max

Units

Relative Accuracy

I

-1/2

+1/2

-1/2

+1/2

-1

+1

LSB

Differential Nonlinearity

I

-1/2

+1/2

-112

+1/2

-1

+1

LSB

25°C

I

-1/2

+1/2

-2

+2

-3

+3

LSB

Tmin-Tmax

I

-1.5

+1.5

-3

+3

-4

+4

LSB

Output Settling Time

oun Load
... 1000+ 13pF

II

Output Capacitance
onOUT1

Inputs Low
Inputs High

II
II

Gain Error:

0.5

0.5
30
75

0.5

IJ.S
30
75

30
75

pF
pF

toS: Data Set-up Time

I

60

60

60

ns

tOH: Data Hold Time

I

10

10

10

ns

I

10

10

10

ns

I

20

20

20

ns

Address Hold Time
.

Address Set-Up Time

(1) Test Procedure: 1- Production tested at the specified conditions; 11- Sample tested to ensure compliance.

* *For Ordering Information See Section 1.
3-48

Hon~ywell

SIGNAL
PROCESSING
TECHNOLOGIES

HDAC50600

14-BIT VOLTAGE-OUTPUT DIGITAL TO ANALOG CONVERTER
PRELIMINARY INFORMATION
FEATURES:

APPLICATIONS:

• Fast Voltage Settling Time of
7S0 nS (Typical) to O.S LSB
• On-Chip Reference Buffer
• Single Supply Operation
• On-Chip Application Resistors to Support Output
Gain Selection
• Low Power Dissipation of 1S mW (Typical)
• 1/2 LSB Maximum Differential Nonlinearity Over
Temperature
• High-Speed Microprocessor Compatible Interfacing

• IlP Controlled Instruments
• Automatic Test Equipment
• Data Acquisition and Control Systems
• Frequency Synthesizers
• Battery Powered Systems
• High Speed AID Converters

11

GENERAL DESCRIPTION
The HDACS0600 is a 14-bit voltage-output digital to
analog converter.
This high-performance monolithic
device provides fast output voltage settling, single
supply operation, and low power dissipation. Unique onchip functions include an input reference buffer and
precision application resistors used to support output
voltage scaling.
Unlike current-output devices, this
voltage-output DAC simplifies the task of output
buffering.
The device input accepts full 14-bit wide parallel data
which makes the HDACS0600 ideal for 16-bit bus

architectures. Data loading is controlled by standard CS
and INR Signals which simplify microprocessor interfacing.
High-speed microprocessors, such as Intel's 80386 or
Motorola's 68020, are supported by the 100 nS
(minimum) write pulse width timing. All logic input levels
are TTL and S volt CMOS compatible.
The HDACS0600 is manufactured on Honeywell's Bipolar
Enhanced CMOS (BEMOS) process. This process is
optimized to .allow the combination of dense, high-speed
digital logic with precision analog circuitry on a single Chip.

BLOCK DIAGRAM
Vee

BIPOLAR
OFFSET

Honeywell

Your

+lOV
REF

R

+5V
REF

RCOM

DBQi

tR i R

081

DB2

AQND VDD

D83

DB4

Ci

WR

D813 D812 DI11

0818

DBS

DB6

DB7

DGND

DBS

DBI

3·49

o
o
co
o

10

~

J:

ABSOLUTE MAXIMUM RATINGS (Beyond Which Damage May Occur) 25°C (1)
Output
VOUTto DGND -0.3 to vee

Supply Votages
Positive Supply Votage (Vee to AGND) +7
Positive Supply Voltage (VDD to DGND) +7
Ground Voltage Differential (AGND to DGND)
-0.3 to 1V
vee to VDD Differential-O.S to +O.SV

Temperature
Temperature, ambient -60 to +1400e
+lS00e
junction
Lead Temperature (soldering 10 seconds) +3000e
Storage Temperature -65 to +lS00e

Input Voltages
Digital Inputs to DGND -0.3 to VDD+0.3V
Pins 23-26 to DGND ± 2SV
Pins 2,3 to AGND -0.3 to +25V
(1) Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications.

ELECTRICAL SPECIFICATIONS
All specifications Tmin to Tmax unless otherwise noted.
VDD = vee = SV; VREF = 1OV; AGND = DGND = OV unless otherwise noted.
DC Parameters

Test
Conditions

Test
Level (1)

HDAC50600A
Min Typ Max

HDAC50600B
Min Typ Max

Units

ACCURACY
Resolution

I

14

14

Bits

Relative Accuracy

I

±112

±1

LSB

Differential Linearity Error

I
I

±112

±1

LSB

Offset Error

+3

+4

LSB

Gain Error

I

±4

±S

LSB

Offset Error Tempco

II

±2

±2

ppml"C

Gain Error Tempco

II

±2.S

±S

ppml"C

I

±112

±1/2

LSB

16

kn

Power Supply Rejection
(.1. Gain/a Vce)

vee=
SV±5%

Application Resistor Value
(R)

II

Application Resistor Matching Error (S/3R, S/2R to R)

I

±.OS

±.OS

%

I

1

1

mA

II

10

10

10

13

16

10

13

REFERENCE INPUTS
liN (Input Current)
CIN (Input Capacitance)

+IOV REFor
+SVREF
Input
+IOV REFor
+SVREF
Input

pF

(I) Test Procedure: 1- Production tested at the specified condkions
II -Guaranteed by design and sampled characterization data.

3-50

Honeywell

ELECTRICAL SPECIFICATIONS

o
o
<0
o

All specifications Tmin to Tmax unless otherwise noted.
VDD =VCC =5V; VREF =10V; AGND =DGND =OV unless otherwise noted.
DC Parameters

Test
Conditions

Test
Level (1)

LO

HDAC50600A
Min Typ Max

HDAC50600B
Min Typ Max

Units

~
C
:::c

LOGIC INPUTS (Pins DBO - DB13. WR. CS)
I

VIH (High Input Voltage)
VIL (Low Input Voltage)

2.4

Volts

2.4

I

0.8

0.8

Volts

liN Input Current)

VIN=O or 5V

I

1

1

IlA

CIN (Input Capacitance)

VIN=O or 5V

II

10

10

pF

8.5

Kn

ANALOG OUTPUTS (Pins VOUT)
ROUT (Output Resistance)

080-0813
Are Zero

I

4.5

6.5

Output Resistance Tempco

II

-300

COUT (Output Capacitance)

II

10
3

Output Voltage Swings

RL~lMQ

I

8.5

4.5

6.5

ppm/oC

-300
15

10

15

pF
Volts

.5.25 4.75

5.25

Volts

3

POWER SUPPLY
I

VDD. VCC Range
IDD

IDD

4.75

All Digital inputs
VILorVIH

I

2

2

mA

All Digital inputs
Dor5V

I

100

100

IlA

6

mA

ICC

3

I
AC Parameters

Test
Conditions

Test
Level (1)

6

3

HDAC50600A
Min Typ Max

HDAC50600B
Min Typ Max

Units

DYNAMIC PERFORMANCE
Output Voltage
Settling Time

Input Logic
Levels D to 5V

II

0.75

0.75

I!S

Digital to Analog
Glitch Impulse

II

20

20

nV-Sec

Output Voltage Noise Density

II

20

20

nV/"VHz

TIMING CHARACTERISTICS
tCS (Chip Select to
Write Setup Time)

II

0

0

ns

tCH (Chip Select to
Write Hold Time)

II

0

0

ns

tWR (WR Pulse Width)

II

100

100

ns

tDS ( Data Setup Time)

II

80

80

ns

10

ns

tDH ( Data Hold Time)

II

10

(1) Test Procedure: I - Production tested at the specified condttions
II- Guaranteed by design and sampled characterization data.

Honeywell

3-51

II

o
o

TIMING DIAGRAM

810

MODE SELECTION
. Write Mode:

~
C

OS andWR low: OAC responds to dati inputs OBO-OB13.

:t

HOLOMODE:
Either CS or WR high: data inputsDBO-DB13 are locked out,
DAC holds last data present when VilA or OS assumes high
state.

TERMINOLOGY

GENERAL CIRCUIT DESCRIPTION

Relative Accuracy

COnversion Section

Relative accuracy, also known as endpoint nonlinearity,
is a measure of the maximum deviation from a straight line
passing though the endpoints of the DAC transfer
function. It is measured after adjusting for zero error and
full-scale error and is expressed in % of full scale range or
(sub)multiples of 1 LSB.
Differential Nonlinearity

The HDACS0600 uses a modified R-2R resistor ladder
network for digital-to-analog conversion. A functional
diagram of this internal network is shown in Figure 2. To
ensure a low Differential Linearity Error, the three most
significant bits of the DAC use a segmented architecture,
while the remaining eleven bits Use the classical R-2R
structure. Laser trimmed thin-film resistors assure high
accuracy and stability over time and temperature.

Differential nonlinearity is the difference between the
measured change and the ideal 1 L8B change between
any two adjacent codes.
A specified differential
nonlinearity of 1 L8B (max) over the operating
temperature range ensures monotonicity.

Position of internal switches 80-817 determine the DAC
output voltage and are controlled by the DAC input code
DBO-DB13. The internal Vref node is maintained at 3
Volts. by the reference buffer which provides a DAC
output range of 0 to 3 Volts.

GalnE~r

Reference Buffer

Gain error, also known as full-scale error, is a measure of
the deviation of the actual DAC full-scale output from the
ideal full-scale output. For the HDACS0600, ideal fullscale output is (16383/16384)o3V + (Offset Error). Gain
error and offset error are adjustable to zero using
external trims as shown in Figure S.

The internal Vref node is driven by the on-Chip
Reference Buffer as illustrated in the block diagram. By
using internal buffering, the DAC's settling time is
minimized and less constraint is placed on the external
reference. The on-Chip reference buffer also simplifies
the bipolar output option covered later in this section.

Output VoHage Settling Time

Reference Input Voltage DIvider

Time required for Vout to settle to within 1/2 L8B for a
given digital stimulus, ie., zero to full-scale.

The HDACS0600 can use either a S or 10 Volt reference
using input pins +SV REF or +10V REF, respectively.
The unused reference pin must be tied to AGND. The
input reference voltage is divided down internally to
provide an internal reference voltage of 3 Volts. Gain
matching between the two references is ensured by thin
film laser trimming.

Dig Hal to Analog GIHch Impulse
This is a measure of the amount of charge injected from
the digital inputs to Vout when the input changes state.
It is specified as the area of the glitch in nV-secs. The
digital input is toggled between 01 1111 1111 1111 and
10 0000 0000 0000 with Vref at 3 Volts.

3-52

Honeywell

Internal Application Resistors
The Vout pin provides an output signal ranging from 0 to
3 Volts with an output impedance of 6.5 k.Q typical. In
many applications, output buffering and gain are
desirable to increase the output voltage range. The
HDAC50600 contains trimmed thin-film application
resistors for use with an external op amp. These can be
configured to provide output ranges of 0 to 10 Volts or -5
to +5 Volts.
Figure 3 shows how to connect the external op amp. As
shown in the table of Figure 3, pin R is connected to
analog ground to provide a 0 to 10 Volt unipolar output.
In this configuration, the op amp is connected as a noninverting amplifier with a gain of 10/3.
Pin R is connected to pin BIP OFF (bipolar offset) to
provide a -5 to +5 Volt bipolar output range. BIP OFF is
internally connected to the Reference Buffer output.
The op amp in the bipolar output mode is configured so
that:
VBUFF-OUT = (1 0/3) (Vout) - (5/3)(Vref)
No attempt should be made to use the BIP OFF output
as a reference source for other external devices.
Additional loading of this pin may degrade device
performance.

Unlike a current-output type DAC, the input offset
voltage of the external op amp will not cause a nonlinearity over the output range. Because of ,the constant
output impedance of the HDAC50600, output offset will
remain constant over the output range. Output offset
adjustment therefore is only required in those
applications requiring absolute accuracy.

Data is loaded into the HDAC50600 with a single 14-bit
wide data word on pins DBO-DB13, where DBO is the
least significant bit (LSB). Pins
and WR control the
loading of the DAC input register. When both CS and
WR are logic low, the input latches are transparent. If
either CS or WR (or both) goes to logic high, the DAC
data register is latched and Vout retains its present value.
The timing relationship of WR, CS and input data is
shown in the the Write Timing Diagram of Figure 1. Pins
WR and CS may be used interchangeably.

~

0cc(

J:

es

The input logic scheme of the HDAC50600 is designed
for direct interface and control by a 16-bit
microprocessor. Since the device is designed for write
pulse widths as short as 100 ns, it is compatible with the
latest high-speed general purpose microprocessors
such as Motorola's 68000 or 68020 or Intel's 80286 or
80386. Typical microprocessor interfacing is shown in
Figure 4.

DB11

DB12

DB13
(MSB)

3 TO 7 DECODER

---.----T---T---,----T---r--- -------..,I

i

VREF o-------------~----~7r_~~------_r._----~----~--~
AGNDo-----~----~+4----~>~~~----~~+_--~~----y~~

2R

v---~----~----~~-+------~

Honeywell

CO

Input Logic and Interfacing

Figure 2. Equivalent Resistor Network for the HDAC50600 DAC Circuitry
DBO • • • • DB10
(LSB)

g

vOUT

3-53

II
.

.

o
o
CO
o

10

~J:

APPLICATION HINTS
External Operational Amplifier Selection
When application of the HDAC50600 requires an
external op amp for output signal gain or buffering,
selection of the op amp type can involve trade-offs
between cost, accuracy, and speed. As an example,
consider the circuit of Figure 3. In this application, the
amplifier is configured for a non-inverting gain of 10/3 to
provide a 10 Volt output swing. To contribute less than
114 LSB linearity error at Vbuff-out, the op amp's largesignal open loop voltage gain (Avo I) must be 250 V/mV
(10S dB) minimum. Input offset drift over temperature,
which is also multiplied by 10/3, will also effect Vbuff-out
accuracy. For the circuit of Figure 3, an error of less than
1/4 LSB over a 50°C temperature change will be
maintained with an op amp having a tNos/°C of 3 IlVloC
maximum; fora 100°C change, 1.5 IlV/oC maximum is
required.
The slew rate and bandwidth requirement will vary
depending on application. Fast op amps, such as the
OP17 at 60 V/!lS slew rate and 30 MHz bandwidth, will
provide a very fast settling time so that the output Vbuffout in Figure 3 can approach the 750ns settling time of
the HDAC50600.
Input noise, like input offset, is
multiplied by the non-inverting gain of the circuit (noise
gain). Most modern high-accuracy op amps which
provide suitable gain also have sufficiently low input
noise. Proper op amp decoupling and good layout
techniques are also essential to maintain low input noise.
Good op amp choices for high gain accuracy include the
OP-43, OP-77, and the LT1001-LT100S.
For high
accuracy and high speed the OP-27 or the still faster OP37 are good choices.

sheet to minimize temperature drift. Range of offset
adjustment using this procedure will typically be ±5 mY.
A thermally stable mUlti-turn potentiometer should be
used for Ros.
Full-scale adjustment is provided by external resistor Ra
and potentiometer Rc. Ra and Rc add to the the total
input and feedback resistance provided by the internal
application resistors and allow a ±10 LSB adjustment
range.
Like Ros, Ra and Rc should have low
temperature coefficients with the latter being a mUlti-turn
potentiometer. Rb is not used and can be omitted for
unipolar operation.

Figure 3. Connection Diagram of
External Operational Amplifier Utilizing
Internal Application ReSistors
HDAC50600

VOUT
VBUFF.OUT

512 R

23

L.....W~-'R~~26'-1

REFERENCE
BUFFER

ANALOG
GROUND

Vx

I

>-~__..:::B!!..IP=OF",-F-¢ t _ ~

Vx

CONNECTION

ANALOG GROUND
PINBIP OFF

V BUFF.OUT

RANGE

O+.10V (UNIPOLAR)
-5 .. +5V (BIPOLAR)

Offset and Full Scale Trim Adjustments
Although the application resistor ratios are matched to
better than ±0.05%, this error combined with the DAC's
offset and gain errors are important to consider when
utilizing the circuit of Figure 3. With the addition of
external trim resistors as shown in Figure 5, offset and
gain errors can be eliminated. The values of Ra, Rb and
Rc as shown will work for both the HDAC50600A and
HDAC50600B grades.
Calibration for 0-1 0 Volt Unipolar Output Operation
When using the 0 - 10 Volt unipolar output circuit option
of Figure 5, the Zero setting (offset) is accomplished by
adjustment of potentiometer Ros. Ros performs internal
nulling of the op amp .. The value and connection of Ros
should be as specified in the op amp manufacturer's data

3-54

Figure 4. Typical Microprocessor
Interface (Simplified)

Wl'II>---------oIiiffi

HDACS0600

,.-----'l.IOB13
...--_.:..:.14-,) OBO

OATABUS

Honeywell

The procedure for trim adjustment using the 0-10 Volt
unipolar circuit option of Figure 5 is as follows:

The procedure for trim adjustment using the ±5 Volt
bipolar circuit option of Figure 5 is as follows:

o
o
oIt)

<0

1) Set zero value: With [00 0000 0000 0000] in the
input register, adjust potentiometer Ros to obtain
0.0000 Volts at Vbuff-out.
(0.00061 V equals 1 LSB)
2) Set full scale value: With [11 1111 1111 1111] in the
input register, adjust potentiometer Rc to obtain the
correct Full-scale output minus 1 LSB which is 9.99939
Volts.
([Full-scale output] '" [(16383/16384)·10V] + [Zero
output])
Calibration for ±5 Volt Bipolar Output Operation
For the ±5 Volt bipolar output circuit option of Figure 5,
Zero output occurs at - 5 Volts. By use of the application
resistors connected as shown, the Zero output is
derived by multiplying the 3 Volt reference at pin BIP
OFF by -5/3. Zero output at Vbuff-out is adjusted by
potentiometer Rb which changes the -5/3 gain.
Potentiometer Ros is optional and should only be used
with op amps that are not internally trimmed. When Ros
is used, the op amp offset is adjusted first. As in the
bipolar circuit option, potentiometer Rc is used to adjust
full-scale value.

1) Zero the input offset voltage to the op amp. Do this
by writing [00 0000 0000 0000] into the input register
and shorting the inverting and non-inverting op amp
inputs to ground. Adjust Ros until Vbuff-out is as near to
o Volts as possible. Delete this step if resistor Ros is not
used.
(1) Set Zero value:
With [00 0000 0000 0000] in the
input register, adjust potentiometer Rb to obtain a
-5.0000 Volt output at Vbuff-out. (0.00061 V equals 1
LSB)
2) Set full scale value: With [11 1111 1111 1111] in the
input register, adjust potentiometer Rc to obtain the
correct Full-scale output minus 1 LSB which is 4.99939
Volts. [Full-scale output] '" [(16383/16384)·10V] + [Zero
output])

Die Plot

136 x 172 mils

Figure 5. Modification of Figure 3
Showing Use of External Trim
Resistors

o

Res (1)

HDAC50600

rill

M

DBO

III

DBt

lID

,

DB2


~
J:

APPLICATION HINTS
External Operational Amplifier Selection
When application of the HDAC50800 requires an
external op amp for output signal gain or buffering,
selection of the op amp type can involve trade-ofts
between cost, accuracy, and speed. As an example,
consider the circuit of Figure 3. In this application, if R is
tied to AGND, the amplifier is configured for a noninverting gain of 10/3 to provide a 10 Volt output swing.
To contribute less than 1/4 LSB linearity error at Vbuffout, the op amp's large-signal open loop voltage gain
(Avol) must be 250 V/mV (108 dB) minimum. Input offset
drift over temperature, which is also multiplied by 10/3,
will also effect Vbuff-out accuracy. For the circuit of
Figure 3, an error of less than 1/4 LSB over a 50°C
temperature change will be maintained with an op amp
having a IlVosl°C of 3 /lVrC maximum; for a 100°C
change, 1.5/lV/oC maximum is required.
The slew rate and bandwidth requirement will vary
depending on application. Fast op amps, such as the
OP17 at 60 V/1J.5 slew rate and 30 MHz bandwidth, will
provide a very fast settling time so that the output Vbuffout in Figure 3 can approach the 750ns settling time of
the HDAC50800.
Input noise, like input offset, is
multiplied by the non-inverting gain of the circuit (noise
gain). Most modern high-accuracy op amps which
provide suitable gain also have sufficiently low input
noise. Proper op amp decqupling and good layout
techniques are also essential to maintain low input noise.
Good op amp choices for high gain accuracy include the
OP-43, OP-77, and the LT1 001-LT1 008.
For high
accuracy and high speed the OP-27 or the still faster OP37 are good choices.

should be as specified in the op amp manufacturer's data
sheet to minimize temperature drift. Range of offset
adjustment using this procedure will typically be ±5 mY.
A thermally stable mufti-turn potentiometer should be
used for Ros.
Full-scale adjustment is provided by external resistor Ra
and potentiometer Rc. Ra and Rc add to the the total
input and feedback resistance provided by the internal
application resistors and allow a ±10 LSB adjustment
range.
Like Ros, Ra and Rc should have low
temperature coefficients with the latter being a multi-turn
potentiometer. Rb is not used and can be omitted for
unipolar operation.

Figure 3. Connection Diagram of
External Operational Amplifier Utilizing
Internal Application Resistors

HDAC50800

_____r---v V BUFF.oUT

512 R

19
ANALOG
GROUND

\. -

-

- -. -

- ..... - 1"'"" -. -

- -.- -

-

---•. ."

- -.- - -,.-.-.- I vBUFF.oUT-.-.-RANGE
_.\ ANALOG GROUND i o· .....10V (UNIPOLAR)
\ VX CONNECTION

'-,

,1. .. PIN
BlP OFF
_ . ___ ._ .. _ _

..~.-.-.-.- ..

I -5 .. +5V (BIPOLAR)

I

~

"_ _ ..... _. _ _ _ _ _ ._ ... _

~

i

Offset and Full Scale Trim Adjustments
Although the application resistor ratios are matched to
better than ±0.05%, this error combined with the DAC's
offset and gain errors arll important to consider when
utilizing the circuit of Figure 3. With the addition of
external trim resistors as shown in Figure 5, offset and
gain errors can be eliminated. The values of Ra, Rb and
Rc as shown will work for both the HDAC50800A and
HDAC50800B grades.

Figure 4. Typical Microprocessor
Interface (Simplified)

Calibration for 0-1 0 Volt Unipolar Output Operation
When using the 0 - 10 Volt unipolar output circuit option
of Figure 5, the Zero setting (offset) is accomplished by
adjustment of potentiometer Ros. Ros performs internal
nulling of the op amp. The value and connection of Ros

3-64

Honeywell

The procedure for trim adjustment using the 0-10 VoH
unipolar circuit option of Figure 5 is as follows:

The procedure for trim adjustment using the ±5 VoH
bipolar circuit option of Figure 5 is as follows:

1) Set zero value: With [00 0000 0000 0000) in the
input register, adjust potentiometer Ros to obtain
0.0000 Volts at Vbuff-out.
(0.00061 V equals 1 LSB)

1) Zero the input offset voltage to the op amp. Do this
by writing [00 0000 0000 0000) into the input register
and shorting the inverting and non-inverting op amp
inputs to ground. Adjust Ros until Vbuff-out is as near to
oVolts as possible. Delete this step if resistor Ros is not
used.

2) Set full scale value: With [11111111111111)inthe
input register, adjust potentiometer Rc to obtain the
correct Full-scale output minus 1 LSB which is 9.99939
Volts.
([Full-scale output) = [(16383/16384)010V) + [Zero
output))
Calibration for±5 Volt Bipolar Output Operation
For the ±5 Volt bipolar output circuit option of Figure 5,
Zero output occurs at - 5 Volts. By use of the application
resistors connected as shown, the Zero output is
derived by multiplying the 3 Volt reference at pin
BIPOLAR OFFSET by -5/3. Zero output at Vbuff-out is
adjusted by potentiometer Rb which changes the -5/3
gain. Potentiometer Ros is optional and should only be
used with op amps that are not internally trimmed. When
Ros is used, the op amp offset is adjusted first. As in the
bipolar circuit option, potentiometer Rc is used to adjust
full-scale value.

1) Set Zero value: With [00 0000 0000 0000) in the
input register, adjust potentiometer Rb to obtain a 5.0000 Volt output at Vbuff-out.
(0.00061 V equals 1 LSB)
2) Set full scale value: With [11 1111 1111 1111) in the
input register, adjust potentiometer Rc to obtain the
correct Full-scale output minus 1 LSB which is 4.99939
Volts.
[Full-scale output) = [(16383/16384)010V) + [Zero
output))

Die Plot
136

x 172 mils
IW

~

IL
W

II:

Figure 5. Modification of Figure 3
Showing Use of External Trim
Resistors

IL
W

II:

>
co

0

II:

:s0
g,

iii+

...

!ill

m Il]

ID

8

>

o

ROS (1)

III

m

..
rnl
iil

HADC50800

R

REFERENCE
BUFFER

BIPOFF

OBI

Bl

DB2

lEI

DB3

lEI

DB4

IE!

DB5

Bl

I

Vx CONNECTION

V BUFF-oUT

ANALOG GROUND
RB

O..... 10V (UNIPOLAR)
-5 _5V (BIPOLAR)

ReoM
5/3 R
5/2 R
AGND

0

1

75 n

RANGE

!~l ~ ~sl~8:n~~~WD B':~~~Jo~:E~~~~~
ELUMINATED IN UNIPOLAR 0 PERATION.

Honeywell

1m

22

R B (2)

NOTES:

DBO

R

V

ANALOG
GROUND

m

.
ID
C

Bl
0

o

o

!ill
~

c(

V DD

Il]

.
c(

3-65

o
o
co
o
It)

~

C
:I:

0
0
0

Burn-In Configuration

IX)

It)

~
c
X

·.10V

son

BIPOLAR
OFFSET

Vee

+10V REF

V OUT
R

+5V REF

DATA

.5.25 V
112 wall

DBO

RCOM

DB1

!R

DB2

fR

DB3

AGND

DB4

V DD

DB5

CS

DB8

WR

WFi

DB7

AO

DOND

A1

A1

SOO kHz

AO

= 1.0 lIS ± ZOO ns
= Ids = 1.5 lIS ± 200 ns
tah = Idh = 0.5 lIS ± 200 na

twr
.....- + - - - - 5 . 2 5 V
A1

········0 V
DATA

Idh-..

LOAD
LOW
BYTE

3·66

LOAD
HIGH
BYTE

las

~

LOAD
DAC

LOAD
LOW
BYTE

LOAD
HIGH
BYTE

LOAD
DAC

Honeywell

BIPOLAR
OFFSET

•

VOUT

+SV REF

R

DBO

R eOM

DB1

0
0

E.R
3

0

.§..R
2

U

AGND

C

V DD

DB3

CO
to

c:(

DB4

ex>

0
LO

PIN

PIN NAME

FUNCTION

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

BIPOLAR OFFSET
+10V REF
+5V REF
DBO
DBl
DB2
DB3
DB4
DB5
DB6
DB7
DGND
A1
AO

VREF OUTPUT FOR BIPOLAR OPERATION
INPUT FOR 10V REFERENCE VOLTAGE
INPUT FOR 5V REFERENCE VOLTAGE
INPUT DATA BIT 0 (LSB) OR 8
INPUT DATA BIT lOR 9
INPUT DATA BIT 2 OR 10
INPUTDATABIT3 OR 11
INPUT DATA BIT 4 OR 12
INPUTDATABIT5 OR 13 (MSB)
INPUT DATA BIT 6
INPUTDATABIT7
DIGITAL GROUND
INPUT ADDRESS LINE A1
INPUT ADDRESS LINE AO
DATA WRITE
CHIP SELECT
DIGITAL POSITIVE POWER SUPPLY
ANALOG GROUND
APPLICATION RESISTOR NETWORK
APPLICATION RESISTOR NETWORK
APPLICATION RESISTOR NETWORK
APPLICATION RESISTOR NETWORK
ANALOG VOLTAGE OUTPUT
ANALOG POSITIVE POWER SUPPLY

()

Vee

+10V REF

DB2

0
0

Pin Functions

Pin Assignment

::J:

DBS

cs

DB6

WR

DB7

AO

DGND

A1

Wli

cs

VDD
AGND
512 R
513 R
ReOM
R
VOUT
Vcc

* * For Ordering Information See Section 1.

Honeywell

3-67

«0

J:

EI

NOTES:

3-68

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HDAC51400

a-BIT, ULTRA HIGH SPEED D/A CONVERTER

FEATURES

APPLICATIONS

• 400 MWPS Nominal Conversion Rate
• RS-343-A Compatible
• Complete Video Controls: Sync,
Blank, Bright and Reference White
(Force High)
• 10KH, 100K ECl Compatible
• Single Power Supply
• Stable On-chip Bandgap Reference
• Registered Data And Video Controls
• Differential Current Outputs
• 50 and 75 Ohm Output Drive

• Raster Graphics
• High Resolution Color or Monochrome
Displays to 2K x 2K Pixels
• Medical Electronics: CAT, PET, MR Imaging
Displays
• CAD/CAE Workstations
• Solids Modeling
• General Purpose High-Speed D/A
Conversion
• Digital Synthesizers
• Automated Test Equipment
• Digital Transmitters/Modulators

GENERAL DESCRIPTION
The HDAC51400 is a monolithic a-bit digital-to-analog
converter capable of accepting video data at 400
MWPS. Complete with video controls (Sync, Blank,
Reference White [Force High], Bright) the HDAC51400
directly drives doubly-terminated 50 or 75 Ohm loads
to standard composite video levels. Standard set-up

level is 7.5 IRE. The HDAC51400 includes an internal
precision bandgap reference which can drive two
other 51400s in an RGB graphics system. The
HDAC51400 contains data and control input registers,
video control logic, reference, and current switches in
24 Lead CERDIP, or ceramic sidebrazed DIP.

BLOCK DIAGRAM
VIDEO
CONTROLS

OUTPUT
CURRENT
SWITCHES

I'EEDTMROUQH
CONVERT

'SET
REF.N

REF OUT

Honeywell

3-69

II
I

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)120 0 C
Temperature

Supply Voltages
VEEO(measuredto\!cco) .......... -7.0toO.5V
VEEA (measuredtoVCCN' .......... -7.0toO.5V
VCCA (measured to VCCO) .......... - 0.5to 0.5V

Operating, Ambient ....... , ..... - 60 to +
Junction ................. ; . +
Lead, Soldering(10 seconds) ............ +
Storage ...................... - 60 to +

140°C
175°C
300°C
150 o,C

Input Voltages
CONY, Data, and Controls .......... VEEO toO.5V
(measured to VCCO)
REF + (measured to VCCA) .......... VEEA to 0.5V
REF -(measured to VCCA) .......... VEEA to 0.5V

Notes:
1. Operation at any Absolute Maximum Ratings is not implied. See Operating Conditions for proper nominal applied conditions in typical applications.

PARAMETER

DC ELECTRICAL CHARACTISTICS

TEST
CONDITIONS

TEST
LEVEL MIN

TYP

MAX

UNITS

v(X;A = vCCD = D.DV. v EEA = vEED = -5.2V ±O.3V. TA = 25"C.I SET

ELI

Integral Linearity Error

ELO

Oifferential Linearity Error

EG

Gain Error

TCG

Gain Error Tempco

150

TCB

Bandgap Tempco

100

PPM/oC

-1.2

V

1.0mA< ISET< 1.8mA
1.0mA< ISET< 1.8mA

I

= 1.1D5mA

I
III

-0.2

+0.2

-Y2

+Y2

-0;2

+0.2

- Y2

+Y2

% Full Scale
LSB

+5

% Full Scale

-5

% Full Scale
LSB

PPM/oC

VREF- Reference Voltage
(measured to VCCA)
OUT
IREF- Reference Output Current
OUT
CREF Input Capacitance, ISET' REF IN

V

VOCP Compliance Voltage, + Output

I

-1.5

+3

V

VOCN Compliance Voltage, - Output

I

-1.5

+3

V

ROUT Equivalent Output Resistance

I

20

COUT Output CapaCitance

V

on
= on

-50

pA
pF

5

KOhm
pF

9

Maximum Current, + Output

RL =

V

45

mA

ION

Maximum Current, - Output

RL

V

45

mA

lOS
VIH

Output Offset Current

I

Y2

LSB

Input Voltage, Logic HIGH

I

VIL

Input Voltage, Logic LOW

I

-1.0

I

-0.5,

lOp

VICM Convert Voltage,
Common Mode Range

3·70

-1.4

V
V

-2.5

V

Honeywell

PARAMETER

DC ELECTRICALCHARACTISTICS

TEST
CONDITIONS

TEST
LEVEL MIN

TYP

MAX

o
o
-t
.It)

UNITS

vCCA =vCCD =o.OV,VEEA =VEED = -S.2V ±0.3V,TA = 25°C,ISET =1.105mA

~
::I:

VIDF Convert Voltage, Differential
Input Current, Logic LOW,
IlL
Data and Controls
IIH

IV

Input Current, Logic HIGH,
Data and Controls

IIC

Input Current, Convert

CI

Input Capacitance,
Data and Controls

V

PSR

Power Supply Sensitivity

I

lEE

Supply Current
RL = 37.50
RL = 250

PARAMETER

TEST
CONDITIONS

DYNAMIC CHARACTERISTICS RL

V

pA

10

120

pA

2

60

pA
pF

3

+ 120

-120

I

ISET Reference Input Current

1.2
120

0.4

175

200

1.105
1.658

TEST
LEVEL MIN

TYP

mA
mA
mA

MAX

UNITS

= 37.S0hms, cL = 5pF (unless otherwise specified), TA =25°C, ISET = 1.105 mA

FS

Maximum Conversion Rate

tRI

Rise Time

10% to 90% G.S.

I

900

ps

tRI

Rise Time

10% to 90% G.S.
RL 25 Ohms Total

I

600

ps

tSI

Current Settling Time,
Clocked Mode

To 0.2%

IV

4

ns

tSI

Current Settling Time,
Clocked Mode

To 0.2%
RL 25 Ohms Total

IV

3

ns

I

=

=

385

400

MWPS

tDSC Clock to Ouptut Delay,
Clocked Mode

I

4

ns

tDST Data to Output Delay,
Transparent Mode

I

6

ns

tpWL Convert Pulse Width,
LOW

I

1.25

ns

tpWH Convert Pulse Width,
HIGH

I

1.25

ns

BWREFReference Bandwidth,
-3dB

V

1.25

MHz

Honeywell

E1

pAJV

0.7

3-71

§....

PARAMETER

TEST
CONDITIONS

TEST
LEVEL MIN

TYP

MAX

UNITS

10

~

DYNAMIC CHARACTERISTICS RL = 37.S Ohms, CL = SpF(unless otherwise specified), TA = 2soC.ISET = 1.105 mA

:I:
Glitch Energy

Area = 112 VT

V

10

pV-s

1

ns

-200

ps

ts

Set-up Time, Data and
Controls

I

tH

Hold Time, Data and
Controls

I

0

SR

Slew Rate

I

700

FTC

Clock Feedthrough

20% to 80% G.S.

ELECTRICAL CHARACTERISTICS TESTING

I

-48

Unless otherwise noted, all tests are pulsed tests, therefore
Tc
Ta·
Tj

=

dB

TEST LEVEL TEST PROCEDURE

All electrical characteristics are subject to the following conditions:
All parameters having Min.lMax. specifications are
guaranteed. The Test Level column indicates the specific
device testing actually performed during production ana
Quality Assurance inspection. Any blank sections In the data
columns indicates that the specification is not tested at the
specified conditions.

V/p.S

100% production tested at the specified
temperature.

II

100% production tested at Ta =25°C, and
sample tested at speCified temperature.

III

QA sample tested
temperatures

IV

Parameter is guaranteed (but not tested) by
design and characterization data.

V

Parameter is a typical value for information
purposes only.

=

only

at

specified

APPLICATION INFORMATION
The HDAC51400 is a high speed video Digital-toAnalog converter capable of up to a 400 MWPS conversion rate. This makes the device suitable for driving
2048 X 2048 pixel displays at 60 to 90 Hz update rates.
In addition, the HDAC51400 includes an internal bandgap reference which may be used to drive two other
HDAC51400s if desired.
The HDAC51400 has 10KH and lOOK ECL logic level
compatible video control and data inputs. The complementary analog output currents produced by the
devices are proportional to the product of the digital
control and data inputs in conjunction with the analog
reference current. The HDAC51400 is segmented so
that the four MSBs of the input data are separated into
a parallel "thermometer" code. From here, fifteen
current sinks, which are identical, are driven to
fabricate sixteen coarse output levels. The remaining
four LSBs drive four binary weighted current switches.

3·72

The MSB currents are then summed with the LSBs,
which provide a one-sixteenth of full scale contribution, to provide the 256 distinct analog output levels.
The video control inputs drive weighted current sinks
which are added to the output current to produce composite video output levels. These controls, Sync,
Blank, Reference White (Force High), and Bright are
needed in video applications.
Another feature that similar video D/A converters do
not have is the Feedthrough Control. This pin allows
registered or unregistered operation between the
video control inputs and data. In the registered mode,
the composite functions are latched to the pixel data to
prevent screen-edge distortions generally found on
unregistered "VIDEO DACs".

Honeywell

FUNCTIONAL DIAGRAM

J

DECODING

'8
COMPOSITE

VIDEO
CONTROLS

CONY

CONY

CURRENT

SOURCES a
SWITCHES

/
'4

•

LOGIC
DATA
REOISTERS

,

r+"

II~NO

A
-

+

'--

t
I

OUT

CURRENT
SOURCE

FEEDTHROUOH

BANDGAP
REFERENCE

OUT

~

/
'2

--- -

- -

REF.CJUT

SET

II

REF·IN

TYPICAL INTERFACE CIRCUIT
GENERAL

OUTPUT CONSIDERATIONS

A typical interface circuit using the HDAC51400 in a
color raster application is shown in Figure 2. The
HDAC51400 requires few external components and is
extremely easy to use. The very high operating speed
of the HDAC51400 requires good circuit layout,
decoupling of supplies, and proper design of transmission lines. The following are several considerations
that should be noted to achieve best performance.

The analog outputs are designed to directly drive a
doubly terminated 50 or 75 Ohm transmission system
as shown. The source impedances of the HDAC51400
outputs are high impedance current sinks. The load
impedance (RL) must be 25 or 37.5 Ohms to attain
standard RS-343-A video levels. Any deviation from
this impedance will affect the resulting video output
levels proportionally. As with the data interface, it is
important that the analog transmission lines have
matched impedance throughout, including connectors
and transitions between printed wiring and coaxial
cable. The combination of matched source termination resistor Rs and load terminator RL minimizes
reflections of both forward and reverse traveling
waves in the analog transmission system. The return
path for analog output current is Vr= which is connected to the source termination resistor Rs.

INPUT CONSIDERATIONS

Video input data and controls may be directly connected to the HDAC51400. Note that all ECl inputs are
terminated as close to the device as possible to
reduce ringing, crosstalk and reflections. A convenient and commonly used microstrip impedance is
about 130 Ohms, which is easily terminated using a
330 Ohm resistor to VEE and a 220 Ohm resistor to
Ground. This arrangement gives a Thevenin
equivalent termination of 130 Ohms to - 2 Volts
wittlout the need for a - 2 Volt supply. Standard SIP
(Single Inline Package) 220/330 resistor networks are
available for this purpose.

FIGURE 1

TIMING DIAGRAM

It is recommended that stripline or microstrip techniques be used for all ECl interface. Printed circuit
wiring of known impedance over a solid ground plane
is recommended. The ground plane should be constructed such that analog and digital ground currents
are isolated as much as possible. The HDAC51400
provides separate digital and analog ground connections to simplify ground layout.
tSl

OUT +

'ttL"

Honeywell

3·73

0

FIGURE 2

TYPICAL INTERFACE CIRCUIT

~
.,...
10

,.•

FT

SiC .

VIDEO • {
CONTROL
INPUTS

BLANK
BRT
SYNC

II
I

,

D'
D'

",

","sn

DATA

24

23
MS

19 OUT

+

"21

D7

NOmo

.,

CLOCK {

",

I

LSB 00

INPUTS

1KU

VIDEO MONITOR

I

"

13

::I:

-{

1"--------------.,

11

1.Y- _ -1..IVFORLMU8
2.V+ -1.2Y

",

V+

1KIl

'SET

REFIN

"

15

, I... ]

[

"VOUT+ _K

-

DI."AL
]
INPUT
CODE
...
--)1111'1'

", + U I.E (8!TUP LEVELl

RL +7.IIAEIIETUPLEVI!L)

K - 21.1 ForVIYNC
K _11S.13'1IF.Ya.s.
7. L • FeRRIT! .~D INDUCTOR
FA''''RITE PIN 2174301111
OFl8lMlLAR

lREMOVE FOR
EXTERNAL
REFERENCE)

8. ALL REFERENCE RESISTORS'" W 1%
METAL filM POWER 8UPPt.V DECOUPUNG

*AN EXTERNAL AEFERENCE CAN BE USED

SOY CERAMIC DtsC.

..

OR THE REFERENCE FROM THE REF OUT

PIN ON THE HDACS1401 CAN DRIVE
THREE HOAC51400..

MASTER RfFERENCE
TO OTHER QAes

II

- Eel TERMINATION

10. TO POWER SUPPLY

-s.2V

-s.2Y

O··OUND
VCCD

VCCA

(DOND'

(AONr.I"

POWER CONSIDERATIONS

REFERENCE CONSIDERATIONS

The HDAC51400 operates from a single standard
- 5.2 Volt supply. Proper bypassing of the supplies will
augment the HDAC51400's inherent supply noise rejection characteristics.As shown in Figure 2, a large
tantalum capacitor in parallel with smaller ceramic
capacitors is recommended for best performance.
The small;valued capacitors should be connected as
close to the device package as possible, whereas the
tantalum capacitor may be placed up to a few inches
away.

The HDAC51400 has two reference inputs: REF IN
and ISET and one reference output REF· OUT. The input pins are connected to the inverting and noninverting inputs of an Internal amplifier that serves as a
reference buffer.

The HDAC51400 operates with separate analog (VEEA)
and digital (VEED) power supplies to establish high noise
immunity. Both supplies can eventually be connected
to the same power source, but they should be individually decoupled as mentioned previously. The
digital supply has a'separate grounct'return which is
VCCD. The analog supply return is VCCA. All power and
ground pins must be connected in any application. If a
+ 5V power source Is required, the ground pins VCCD
and VCCA become the positive supply pins while VEED
and VEEA become the ground returns. The relative
polarities of the other voltages on inputs and outputs
must be maintained.
.

Since the analog output currents are proportional to
the digital input data and the reference current (lsET),
the full-scale output may be adjusted by varying the
reference current. lSET is controlled through the (lSET) input on the HDAC51400. A method and equations to set
ISET is shown in Figure 2. The HDAC51400. can use an
external negative voltage reference. The external
reference must be stable to achieve a satisfactory output and the REF - IN pin should be driven through a
resistor to minimize offsets caused by bias current.
The value for ISET can be varied with the 500 to 1K Ohm
trimmer to change the full scale output. A double 50
Ohm load (25 Ohm) can be driven if ISET is Increased by
50% above for doubly terminated 75 Ohm video applications.

3·74

The output of the buffer amplifier is the reference for
the current sinks. The amplifier feedback loop is connected around one of the current sinks to achieve better accuracy (see Figure 5).

Honeywell

DATA INPUTS AND VIDEO CONTROLS

The HDAC51400 has standard single-ended data inputs. The inputs are registered to produce the lowest
differential data propagation delay (skew) minimizing
glitching. There are also four video control inputs to
generate composite video outputs. These are Sync,
Blank, Bright and Reference White or Force High. Also
provided is the Feedthrough control as mentioned
earlier. The controls and data inputs are all 10KH and
100K ECl compatible. In addition, all have internal
pulldown resistors to leave them at a logic low so the
pins are inactive when not used. This is useful if the
devices are applied as standard DACs without the
need for video controls or if less than a-bits are used.
The HDAC51400 is usually configured in the synchronous mode. In this mode, the controls and data
are synchronized to prevent pixel dropout. This
reduces screen-edge distortions and provides the
lowest output noise while maintaining the highest conversion rate. By leaving the Feedthrough (FT) control
open (low), each rising edge of the convert (CONV)
clock latches decoded data and control values into a
D-type internal register. The registered data is then
converted into the appropriate analog output by the
switched current sinks. When FT is tied high, the control inputs asynchronously tracks the input data and
video controls. Feedthrough itself is asynchronous
and usually used as a DC control.
The controls and data have to be present at the input
pins for a set-up time of ts before, and a hold time of tH
after the rising edge of the clock (CONV) in order to be
synchronously registered. The set-up and hold times
are not important in the asynchronous mode. The
minimum pulse widths high (tPWH) and low (tPWL) as well
as settling time become the limiting factors (see
Figure 1).
The video controls produce the output levels needed
for horizontal blanking, frame synchronization, etc., to
be compatible with video system standards as
described in RS-343-A. Table 1 shows the video control effects on the analog output. Internal logic governs

Table 1

Blank, Sync and Force High so that they override the
data inputs as needed in video applications. Sync overrides both the data and other controls to produce full
negative video output (Figure 4).
Reference white video level output is provided by
Force High, which drives the internal digital data to full
scale output or 100 IRE units. Bright gives an additional 10% of full scale value to the output level. This
function can be used in graphic displays for
highlighting menus, cursors or warning messages.
Again, if the devices are used in non-video applications, the video controls can be left open.

Ref
White

Blank

1
0

x

0
0

0
0

0
0

0
0

o
o

0
0

0
0

o
o

1

Honeywell

x
x

Bright

Data
Input

x

x

X

10

~::c

CONVERT CLOCK

For best performance, the clock should be ECl driven,
differentially, by utilizing CONY and CONY (Figure 3).
By driving the clock this way, clock noise and power
supply/output intermodulation will be minimized. The
rising edge of the clock synchronizes the data and
control inputs to the HDAC51400. Since the actual
switching threshold of CONY is determined by CONY,
the clock can be driven single-ended by connecting a
bias voltage to CONY. The switching threshold of
CONY is set by this bias voltage.
ANALOG OUTPUTS

The HDAC51400 has two analog outputs that are high
impedance, complementary current sinks. The outputs vary in proportion to the input data, controls and
reference current values so that the full scale output
can be changed by setting ISET as mentioned earlier.
In video applications, the outputs can drive a doubly
terminated 50 or 75 Ohm load to standard video levels.
In the standard configuration of Figure 7, the output
voltage is the product of the output current and load
impedance and is between 0 and - 1.07V. The OUT output (Figure 4) will provide a video output waveform
with the SYNC pulse bottom at the - 1.07V level. The
OUT + is inverted with SYNC up.

Video Control Operation

Sync

o
o
"lit
.....

Out- (mA)

X

28.57
20.83

Out- (V)
-1.071
-0.781

Out- (IRE)
Description
-40
Sync Level
Blank Level
0

1
0

X
X

0.00
1.95

0.000
-0.073

110
100

Enhanced High Level
Normal High Level

0
0

000 ...
111...

19.40
1.95

-0.728
- 0.073

7.5
100

Normal Low Level
Normal High Level

000 ...
111...

17.44
0.00

-0.654
0.000

17.5
110

Enhanced Low Level
Enhanced High Level

3-75

I

FIGURE 3

CONVert, CONVert SWITCHING LEVELS

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ O.OV

,_---'11.'--------------------

V1CM MIN

_ _ _ _ _ _ _ _ _ _ _ _ _ _ -1.3V

VICMMAX _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _'"'

FIGURE 4

, _ _ _ _ CONY

~

"'-_ _ _p

_ _ _ _ CONY

VIDEO OUTPUT WAVEFORM FOR STANDARD LOAD

....!.!!L ....!!!l!..
110

0

100

-73

7.5

-723

o

-n1

-t--------------------~~--~-.--.--.--.--~J-.--.--.-~

-1071

-t-----,--,--,--,--,--,----,--,---'--.;;;;;;...........I.--.--.--.--.---I

-40

3.76Honeywell

FIGURE 5

EQUIVALENT INPUT CIRCUITS-DATA, CLOCK, CONTROLS AND REFERENCE
- -....- -....-

....."""1r-"oND

o
o
~
.,...
It,)

~

REF 'N 0-+_--;-1

::I:
CoNvo----i

'SET

0-+-....-1

DATA
CONTROLS

v

SOKa

Cc»W0-------t---~

REFERENCE
SEGMENT
SWITCH

I BIAS

-

FIGURE6

.....- -.....- -. . .-

....-

. . .- V EEA

II

DAC OUTPUT CIRCUIT
CURRENT
SINK.1

CURRENT
SINK IN

p---------------

r----_+~_t_-_1~---+_~OUT+

r---t-~t--_+-_.--~-oO~-

.....o--+....----+-!----,

'SET

'SET

REF 'N 0-;--1

~

FIGURE 7A

__________ ..

...----VE~

L ___ ...
LT---~~-------

STANDARD LOAD
V'DEO

r----------,
MONITOR

I
I
II

I
I
II

7S0COA)(

1/::

~~~1r-~~~~~~
'

RL
750

I
;

FIGURE 76

TEST LOAD

OUT+
OUT-

VIDEO OUT
Oto-1VOLT
RL
37.50

I
I
II .............i

HOAC51400

,

'-----'

L~~1r-~~~~~~~i--oINVERSE
VIDEO

Honeywell

3-77

FIGURE8

TYPICAL RBG GRAPHICS SYSTEM

SINGLE GAIN CONTROL

HDAC51400
(SLAVE)

HDAC51400
. (SLAVE)

R1
1501'1

R2

2501l

t

t

'SET
REF'N

'SET

REF'N

t

'SET

'SET

'SET

REF'N

'SET

330Il

3301'1

INDIVIDUAL GAIN CONTROL

HDAC51400
(MASTER)

'SET
R1
5001l

R2
7SOll

REF
'REF

HDAC51400
(SLAVE)

HDAC51400
(SLAVE)

OUT

'SET

500ll

7SOll

'SET

'SET
50011

1KIl
~

REF'N

REF'N

7SOll

-

1KIl

'SET

TYPICAL RGB GRAPHICS SYSTEM
In an RGB graphics system, the color displayed is
determined by the combined intensities of the red,
green and blue (RGB) D/A converter outputs. A change
in gain or offset in any of the RGB outputs will affect
the apparent hue displayed on the CRT screen.

The HDAC51400 contains an internal precision bandgap reference which completely eliminates the need
for an external reference. The reference can supply up
to 50~ to an external load. This can accommodate
three DAC reference inputs.

Thus, it is very important that the outputs of the D/A
converters track each other over a wide range of
operating conditions. Since the D/A output is proportional to the product of the reference and digital input
code, a common reference should be used to drive all
three D/As in an RGB system to minimize RGB DAC-toDAC mismatch. ThiS may also eliminate the need for
individual calibration of each DAC during production
assembly.

The circuits shown in Figure 8 illustrate how a single
HDAC51400 may be used as a master reference in a
system with multiple DACs (such as RGB). The other
DACs are simply slaved from the HDAC51400's
reference output.

3-78

Honeywell

FIGURE 9

BURN·IN CIRCUIT
-uv

LmL ....

IIIAX_

-...

5.20

••
IIIAX',-

••

-u

••

C-_••
78

•

CLOC

-••

PIN ASSIGNMENTS

---

.....

.8

'5

",

....

••

IIIAX',-

II

!

17.'

~

~

.............
-t., ....

AU",_

CLOCK-

DIP

-u_
.-.

PIN FUNCTIONS HDAC51400

04

05
06
07

NAME

FUNCTION

03
02
01
DO
VEEO
CONV
CONV

Data Bit 3
Data Bit 2
Data Bit 1
Data Bit 0 (LSB)
Digital Negative Supply
Convert Clock Input
Convert Clock Input Campl,ment
Register Feedthrough Control
Digital Positive Supply
Data Force High Central
Video Blank Input
Video Bright Input
Video SYNC Input
Reference Output
Reference Input
Reference Current
Analog Positive Supply
Output Current Negall"1'
Output Current Posltlv,
Analog Negative Supply
Data Bit 7 (MSB)
Data Bit 6
Data Bit 5
Data Bit 4

VElA

FT

DUT+

Voco
FH
BLANK
BRT
SYNC
REF OUT
REF IN
ISET
VCCA
OUTOUT+
VEEA
07
06
05
04

ISET

REF IN
REF OUT
BRT
24 LEAD DIP

* *For Ordering Information See Section 1.

Honeywell

Iii ,iilii "
;,

pi

;

I

r,

NOTES:

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES
a-BIT, 250 MWPS MULTIPLEXED VIDEO DAe

HDAC51600

PRELIMINARY INFORMATION
FEATURES:

APPLICATIONS:

·5:1 OR 4:1 Data Multiplexer
• 250 MWPS Conversion Rate
• TTL Compatible Data I/O
• On-Chip Bandgap Reference
• RS-343-A Compatible Video levels

• Digital Video Signal Processing
• High Resolution Color or Monochrome Displays
• Medical Elecronics: CAT, PET, MR Imaging Displays
• CAD/CAE Workstations
• Waveform Generation

GENERAL DESCRIPTION
provided for synchronization with external circuitry. The
video control inputs (SYNC, BLANK, BRighT, and Force
High) are fully synchronous with the pixel data at either
the input clock or divided clock rate. The DAC has a
differential output that can directly drive doubly
terminated 50 or 75 Ohm loads to standard RS-343-A
levels. The standard set-up level is 7.5 IRE.

The HDAC51600 is a monolithic high-speed video DAC
with a multiplexed data interface, and an internal voltage
reference.
All digital inputs and outputs are TTL
compatible except the input clock, which is ECl
compatible for high speed. The multiplexer is selectable
asa divide by 4 or 5, and the multiplexed data is available
through an output port. A divided clock output is

BLOCK DIAGRAM
OIVCLK
(TTL)

OE
(TTL)

DOur
(TTL) 0.7

OAO-7
OBO·7

5:1
MUX

OCO·7
000·7

OUT+
OUT-

OEO-7
REFIN

i'iESei' (TTL)

ISET
ECLK.

ECtR

01V4.rnv5 (TTL)

TIMING
LOGIC

SYNeN~
(TTL)

REF OUT
vee (+5V)
OGNO
AGNO

SYNC. BLANK.
BRT. FH (TTL)

REG
(4)

VEEA (·5.2V)
VEEO (·5.2V)

Honeywell

3-81

o
o
<0
,..
10

~J:

ABSOLUTE MAXIMUM RATINGS 25°C (1)
Supply Voltages

Output

PQsitive Supply Vo~age (VCC to GND) ...................+6.0 to - 0.5V
Negative Supply Voltage (VEE to GND)................. - 6.0 to +5.0V
Vo~age Differential (DGND to AGND, .•....•...•.•.•••• - 0.5 to +0.'5V
VEED to VEEA)

Applied Voltage ..............................:........•• VEE - 0.5 to VCC +0.5

Tempenlture
Operating Temperature, junction .......•...........•.....•...•.... ,. +175°C
lead Temperature (soldering 10 seconds) ...•..••.•...••...... +300°C
Storage Temperature ........................................... - 65 to +150°C

Input Voltages
Data, Controls (TTl, measured to DGND) .............. - 0.5 to VCC
EClK, EctR (ECl, measured to DGND) ................. - 0.5 to VEE

(1) Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications.
.

ELECTRICAL SPECIFICATIONS (1)
Figure 3. VCC= SV, VEEA= VEEO= -S.2V, AGNO= OGNO= O.OV, TA= 2SoC, ISET= 1.1 OSmA, unless otherwise
specified.
Room
Hot
Cold
DC Electrical
Test
Test
+25°C
+70°C
O°C
Conditions Level (1) MIN TYP MAX MIN MAX
Parameters
MIN MAX

Units

DAC CHARACTERISTICS
I

Resolution
Integral Linearity, Gray Scale

1.2mASISET
~1.8mA

Integral Linearity Tempco
Differential Linearity, Gray
Scale

±0.1

+0.2

-1/2

±1/4

±112

V
1.2mASISET
~1.8mA

Differential Linearity Tempco
Gain Error, Gray Scale

I

8
-0.2

I

TBD

I

Gain Error Tempco

V

Offset Current, Outputs, lOS

I

Gray Scale Current, Outputs,
IGS

V

Gray Scale Voltage:, Outputs,
VGS

Bits
%G.S.
LSB
ppmfOC

-0.2

±0.1

+0.2

%(3.8.

-112

±1/4

±112

LSB

V
(Excluding
Reference)

8

ppm/oC

TBD
-S

+5

%G.S.
ppm/oC

±150
S

15

I!A

16.7

17.6

18.5

mA

V

629

661

694

mV

SYNC Voltage, Outputs

I

260

286

314

mV

Blank Voltage, Outputs

I

48

54

59

mV

BRighT Voltage, Outputs

I

64

71

79

mV

3-82

Honeywell

ELECTRICAL SPECIFICATIONS (Cont'd)

o
o

CD

DC Electrical
Parameters

Test
Conditions

Test
Level (1)

Room
+25°C
MIN TYP MAX

Hot
+70 oC
MIN MAX

Cold
O°C
MIN MAX

45

45

45

Units

DAC CHARACTERISTICS (Cont'd)
ISETis
Maximum Allowable Current,
User Defined
Outputs

IV

Compliance Voltage,
Outputs

V

-1.5
20

Output Resistance

RL=oo

I

Output Capacitance

CL=O

IV

Power Supply Sensitivity

LlIGS

:wEEA

+1.5

mA

V

KQ
10

13

pF

±120

I

j.iAJV

REFERENCE CHARACTERISTICS
Bandgap Voltage

IREF

=-50~A

Bandgap Output Current,
IREF
Bandgap Tempco

1.17

1.29

IREF=-10~

LlVREFI
LlVEEA

~

±100

V
IV

V

-50

I

Common Mode Range
REF IN, ISET Pins
Bandgap Power Supply
Sensitivity

I

-2.45

ppm/oC
-0.275

V

V

TBD

dB

input Capacitance
REF IN, ISET Pins

V

5

pF

Input Current, REF IN

IV

3

Input Current, ISET

IV

~

15
1.80

1.80

mA

DIGITAL LOGIC CHARACTERISTICS
input Voltage, Logic Low,
TIL

I

Input Voltage, Logic High,
TIL

I

Input Current, Logic Low,
TIL

I

Honeywell

,

0.8

V

V

2.0

- 500

~

3-83

II

o
o
<0
,....

ELECTRICAL SPECIFICATIONS (Cont'd)

to

~J:

DC Electrical
Parameters

Test
Conditions

Test
Level (1)

Room
+25°C
MIN TYP MAX

Hot
+70°C
MIN MAX

Cold
O°C
MIN MAX

Units

DIGITAL LOGIC CHARACTERISTICS
Input Current, Logic High,
TTL

I

-500

IlA

Differential Range, ECLK,
ECLK, VIDF

See Fig. 5

IV

0.35

1.65

V

Common Mode Range, ECLK,
ECLK, VICM

See Fig. 5

IV

- 0.5

-2.5

V

Input Current, ECLK, ECLK

I

5

60

IlA

Input Capacitance, ECLK,
ECLK

V

5

10

pF

Output Voltage, Logic Low,
DOUT, DIVCLK

I

0.4

V

Output Voltage, Logic High,
DOUT, DIVCLK

I

Output Current, DIVCLK

I

16

mA

Output Current, DOUT

I

TBD

mA

2.4

V

POWER SUPPLY CHARACTERISTICS
Supply Voltage, VCC

IV

4.5

5.5

V

Supply Voltage, VEEA, VEED

IV

- 5.5

- 4.5

V

Supply Current, ICC

I

95

115

mA

Supply Current, IEEA

I

- 50

- 60

mA

Supply Current, IEED

I

-395

- 475

mA

+0.1

V

Differential Voltage, AGND
to DGND, VEEA to VEED

AC t;lectrlcal
Parameters

Maximum Conversion Rate

3-84

IV

Test
Conditions

Test
Level (1)

I

- 0.1

Room
+25°C
MIN TYP MAX

165

250

Hot
+70°C
MIN MAX

Cold
O°C
MIN MAX

Units

MWPS

Honeywell

ELECTRICAL SPECIFICATIONS (Cont'd)
AC Electrical
Parameters

Test
Conditions

o
o

Test
Level (1)

Room
+25°C
MIN TVP MAX

Hot
+70°C
MIN MAX

Cold
O°C
MIN MAX

co
.,..
10

Units

C
J:

DAC CHARACTERISTICS (See Timing Diagrams)
Rise/Fall Times, Outputs

10-90% G.S.
ISET=1.65mA
RL=25Q

I

Rise/Fall Times, Outputs

10-90% G.S.

IV

Slew Rate, Outputs

I

1

ns

1.5

ns

525

VlIlS

Settling Time, Outputs

Full Scale Tran
sition to 0.2%

V

4

ns

Settling Time, Outputs

Full Scale Transition to 0.8%

V

3

ns

ECLK to Output Delay

I

TBD

5

ns

Clock to Output Latency,
Data, Video Controls

I

2

2

Cycles

Feedthrough, Clock,
Data, Controls

I

TBD

dB

Peak Glitch, VGL

1 LSB Transition at midscale

V

2.8

Glitch (1/2 VGL X Time)

1 LSB Transition at midscale

V

3

pV-s

V

1

MHz

mV

REFERENCE CHARACTERISTICS
Amplifier Bandwidth, - 3dB

DIGITAL LOGIC CHARACTERISTICS (See Timing Diagrams)
Maximum Clock Period

I

6

4

ns

Pulse Width, High
ECLK, ECLK, TPWH

I

2.5

2

ns

Pulse Width, Low
ECLK, ECLK, TPWH

I

2.5

2

ns

Set-Up Time, Data to
DIVCLK, TSD

I

10

6.5

ns

Honeywell

~

3-85

o
o
co
,....

ELECTRICAL SPECIFICATIONS (Cont'd)
..

AC Electrical
Parameters

lO

~J:

Test
Conditions

Hold Time, Controls to
DIVCLK, THV

Test
Level (1)

Room
+25°C
MIN TYP MAX

Hot
+70°C
MIN MAX

Cold
O°C
MIN MAX

Units

I

0

- 3.5

ns

Set-Up Time, ControJs
to ECLK, TSV

SYNCN/
SYNC1 = 0

I

10

6.5

ns

Hold Time, Controls to
DIVCLK, THV

SYNCN/
SYNC1 =0

I

0

-3.5

ns

Set-Up Time, Controls
to ECLK, TSV

SYNCN/
SYNC1 = 0

I

4

1.75

ns

Hold Time, Controls to
ECLK,THV

SYNCN/
SYNC1 = 0

I

3

0.75

ns

Output Data Rate

IV

Output Delay, ECLK to
DIVCLK, Rise/Fall, TDDC

I

6.0/
12.0

ns

Output Delay, ECLK to Data
Out, Rise/Fall, TDDM

I

6.0/
12.0

ns

Set-Up Time, RESET to
ECLK, TSR

I

1

ns

60

4

MWPS

(1) All electrical characteristics are subject to the following conditions:
All parameters having min/max specifications are guaranteed. The Test Lellel Column indicates the specific device
testing actually performed during production and Quality Assurance inspection. Any blank sections in the data
columns indicates that the specification is not tested at the specified condition. Unless otherwise noted, all tests
performed after a three minute power soak.
Test Levell - 100% production tested at the specified temperatures.
Test Level 11-1 00% production tested at Ta=25°C and sample tested atthe specified temperatures.
Test Level 111- QA sample tested only at the specified temperatures.
Test Level IV - Parameter is guaranteed (but not tested) by design and characterization data.
Test Level V - Parameter is a typical value for information purposes only.

3·86

Honeywell

FUNCTIONAL DESCRIPTION
The HDAC51600 is a 250 MWPS raster graphics
subsystem that includes an 8-bit DAC with precision
bandgap reference, 5:1 or 4:1 selectable multiplexer,
MUX output port, and MUX timing logic; The DAC will
directly drive doubly-terminated 50 or 75 Ohm loads to
standard RS-343-A I.evels.
All digital inputs and outputs are TIL compatible, except
ECLK, which is ECL compatible. This allows the pixel
data to be run at 50 MWPS data rates requiring only one
high speed differential ECL clock. A reset input (RESET)
and divided clock output (DIVCLK) are provided for
synchronizing external circuitry. Video control inputs are
fully synchronous with the pixel inputs. A MUX data
output provides the multiplexed pixel data for reading at
the DOUT port.

DlV4/DIV5 AND SYNCN/SYNC1
CONTROLS
Two control lines (DIV4/DIV5 and SYNCN/SYNC1)
determine which of four operating modes is to be
selected: 5:1 or 4:1 MUX with either ECLK or DIVCLK
timing for the video controls. These control lines should
not be dynamically switched, as this will upset the internal
state machine.

5:1 MUX
With DIV4/DIV5=0 and SYNCN/SYNC1=1 (Mode A; see
Timing Diagram A), the IC operates in a 5:1 MUX mode.
The five data words and video controls (SYNC, BLANK,
BRighT, and Force High) are latched on the rising edge
of DIVCLK. If any video controls are asserted they remain
active for a full DIVCLK period (five ECLK cycles).
In Mode B, with SYNCN/SYNC1=0 (see Timing Diagram
B), the five data words are latched as in Mode A, but the
video controls are latched on the rising edge of ECLK. If
any video controls are asserted they will remain active for
one full ECLK cycle.

4:1 MUX
With DIV4/DIV5=1 and SYNCN/SYNC1=1 (Mode C; see
Timing Diagram C), the IC operates in a 4:1 MUX mode.
The four data words A-D and all video controls are latched
on the rising edge of DIVCLK. If any video controls are
asserted, they remain active for a full DIVCLK cycle (four
ECLK cycles).

the video controls are latched on the rising edge of
ECLK. If any video controls are asserted, they remain
valid forone full ECLKcycle.

LO

DATA MUX OUTPUT
The data words are seguenced through the MUX in order
A-E (A-D for DIV4IDIV5=1) and appear at the DOUT port
with one clock cycle latency. The DOUT port is limited to
data rates of :0;60 MWPS.

~::r:

RESET CONTROL
For synchronizing multiple DACs in a system, a reset
function is provided. Timing Diagrams E and F illustrate
the operation of this function. When RESET is asserted
low, the MUX will continue to run until the internal state
machine reaches State B. Once it reaches State B, Word
later
B will appear at the DAC outputs two clock eycl
and remain for subsequent clock cycles. If RE ET is
applied to multiple DACs in a system, all DACs will be
stopped in State B, thus synchronizing them. When
RESET goes high, all DACs will cycle through the
remaining latched words (C, D, E; DIV4iiJ'j'i75=0 and C, D;
DIV4/DIV5=1) and a new set of data words will be latched
on the next rising edge of DIVCLK.

S

VIDEO CONTROLS
Modes Band D (Timing Diagrams B and D) allow for video
controls to be asserted on any pixel boundary while
Modes A and C (Timing Diagrams A and C) only allow for
the video controls to be asserted at Pixel A for a full
DIVCLKcycle.

DAC
The DAC provides 256 shades of gray for displaying
video information. SYNC, BLANK, BRighT and Force
High are proportional to the DAC gray scale voltage and
provide RS-343-A compatible levels when adjusted as
shown in Table 1 and Figure 1. Out- is standard video
(SYNC down) with negative true logic; all zeroes equal full
scale (BLACK). Out+ is inverse video (SYNC up) with
positive true logic; all ones equal full scale. Bit 0 of each
word is the LSB. The DAC can drive doubly terminated
50 or 75 Ohm loads to RS-343-A levels.

In Mode D, with SYNCN/SYNC1=0 (see Timing Diagram
D), the four data words A-D are latched as in Mode C, but

Honeywell

o
o
co
,...

3-87

II

o
o
co
,...

TIMING DIAGRAM A. 5:1 MUX, 5 PIXEL VIDEO CONTROLS (1)

10

~
o

l:

ECLK

DIVCLK

DATA AND VIDEO
CONTROLS IN

'VIDEO
CONTROLS OUT

I

DOUT 0.7

f

1
DAcOUT

I

hA~r-X.J .X--l04 ----h'at ----h.0J --hI
'i

-J.

--+----+----+---+1

I

x

~

X

X

i !

I

I

I

I

I

'INTERNAL SIGNAL

(1) DIV4/DIV5 = 0; SYNCN/SYNC1 = 1
All logic levels measured with respect to +1.4 TIL threshold with the exception of ECLK, which is measured at O.OV
differential.

3·88

Honeywell

TIMING DIAGRAM B. 5:1 MUX,1 PIXEL VIDEO CONTROLS (1)

Ipwh

ECLK

VIDEO
CONTROLS IN

'VIDEO
CONTROLS OUT

i

I

Ii.!

(VN)

I II

i

I I I I I

i

!

,

,

i\

!

!

~:r~~!'4+

.1 ~

i

i

1

Iddc

I Ii1~~1

DIVCLK

Iii

~~~
i

i

DOUT 0-7

hJ

Ir
,.'!-,,,j
~ C~~~DO+
i

DATA IN

,
i

Ipwl

i

i

_-+-____

:i-i_ _ _

.j
DACOUT

'INTERNAL SIGNAL

I
I

~

i !

I

,

i

I
I

I

-J.

I
I

Idsc

C

i i i

D Of

Iii
I

I

I

I

~l
!
I
!
:,;
~!-.JX AO~ X ouf X o~ X
X
B

I

I

E O+T

X

!i

!

i

I

(1) DIV4/DIV5 =0; SYNCN/SYNC1 =0
All logic levels measured with respect to +1.4TIL threshold with the exception of ECLK, which is measured at O.OV
differ,ential.

Honeywell

..3-89

II

fIM."'a DIAGRAM C.

4:1 MUX, 4 PIXEL VIDEO CONTROLS (1)

, r'

DIV¢LK

~i

ru~VLli

! ! ! !

~*~~~

"'11010

CONTRO!.S OUT

hI

! /:

! \

'1$cI II h d ! !

m~ l_oml~41 I~
I

I

I

I

I

X

+ .+

I -J.

X

I

X

c~ X ,~
/

X

i

I

DACOU't

'INTERNAL SIGNAL

........

-

(1) Olv4IbIV5= 1;SYNCN/SYNC1 = 1

All lOgic levels measured with respect to +1.4TIL threshold with the exception of ECLK, which is measured at O.OV
differential.
.

a-go1 r

(WI:'

,I

Honeywell
t

TIMING DIAGRAM D. 4:1 MUX,1 PIXEL VIDEO CONTROLS (1)

ECLK

VIDEO
CONTROLS IN

II

"VIDEO
CONTROLS OUT

I

DIVCLK

DATA IN

DOUT 0.7

DACOUT

"INTERNAL SIGNAL

(1) DIV4IDIV5=1;SYNCN/SYNC1 =0

All logic levels measured with respect to +1.4TTL threshold with the exception of ECLK, which is measured at O.OV
differential.

Honeywell

3·91

TIMING DIAGRAM E. 5:1 MUX (1)

Ea..

DlVC:UC

(1) DIV4/r51%=O
All logic levels measured with respect to +1.4TTL threshold with the exception of ECLK, which is measured at O.OV
differential.

TIMING DIAGRAM F. 4:1 MUX (2)

Eeu<

~T---+---r--;---~--+-;

DIYCIJ(

---;-----'!

DOur

DAC

OUT

(2) DIV4/DIV5 = 1
All logic levels measured with respect to +1.4TTL threshold with the exception of ECLK, which is measured at O.OV
differential.

Honeywell

TABLE 1. VIDEO CONTROL OPERATION

o
o

<0
or-

10

~

BLANK

SYNC

FORCE
HIGH

BRIGHT

DATA
INPUT

::r:
OUT· (mA)

OUT+(mA)

OUT+,' (IRE)

DESCRIPTION

1

X

X

X

X

28.56

0

-40

0

1

X

X

20.96

7.60

0

0

0

1

1

X
X

0.00

28.56

110

BRIGHT

0

0

1

0

X

1.89

26.67

100

NORMAL WHITE LEVEL

0

0

0

0

000 ...

19.52

9.03

7.5

NORMAL BLACK LEVEL

SYNC LEVEL
BLANK LEVEL

NORMAL WHITE LEVEL

0

0

0

0

111...

1.89

26.67

100

0

0

0

1

000 ...

17.63

10.93

17.5

ENHANCED BLACK LEVEL

0

0

0

1

111...

0.00

28.56

110

BRIGHT

ISET = 1.1 OSmA; RL=37.SQ; Adjusted for gain and offset.

FIGURE 1. VIDEO OUTPUT WAVEFORM FOR STANDARD LOAD

OUT-

JB.e.

OUT+

IIN.

JB.e.

110
100

----r-------------------------

-71

256 "GRAY
LEVELS"

7.5

-786

-40

-1071

100

-1000

7.5

-339

VIDEO

J __________

-732

0

-1071

-40

ISET

= 1.105mA; RL-37.50;

Honeywell

IIN.

110

-285

0

Adjusled for gain and offset

3-93

II

o
o
CO
,...
It)

~
C
:J:

TYPICAL APPLICATIONS

system with multiple DACs. (such as RGB). The other
DACs are simply slaved fromthe reference output.

Figure 2 illustrates a typical application circuit for a single
HDAC51600. It shows how to terminate the DAC for
either 50 or 75 Ohm loads. The DAC outputs are
proportional to the reference voltage (internal or
external) divideq by the sum of R1 and R2. The
equation for the DAC gray scale output voltage is:

VOUT (G.S.)

a

VREF
oc TR1 + R2

(15.9375) RL,

where

VREF is the reference voltage,
TRt is the active portion of resistor R1,
RL is the load resistance (A3I1R4).

oc

RGB GRAPHICS APPLICATION
The circuits shown in Figure 4 illustrate how a single
HDAC51600 may be used as a master reference in a

In an RGB graphics system, the color displayed is
determined by the ",combined intensities of the red,
green and blue (RGB) D/A converter outputs. A change
in gain or offset in any of the RGB outputs will affect the
apparent hue displayed on the CRT screen.
Thus, it is very important that the outputs of theD/A
converters track each other over a wide range of
operating conditions.
Since the D/A output is
proportic)nal to the product of the reference and digital
input code, a common reference can be used to drive all
three D/As in an RGB system to minimize RBG DAC to
DAC mismatch.
This may also eliminate the need for individual calibration
of each DAC during production assembly.
The
HDAC51600 contains an internal precision bandgap
reference which completely eliminates the need for an
external reference. The reference can supply enough
current to drive two other HDAC51600s.

Honeywell

FIGURE 2. TYPICAL APPLICATION CIRCUIT

o
o

....

<0

(ITL)

(ITL)

(ITL)

DlVCLK

OE

DOur

10

VIDEO MONITOR

.------,
I

DATA IN (ITL)
DA
DB
DC
DD
DE

SYNc:taVIi!!i

NOTES:
1. ALL REFERENCE RESISTORS
1/8W 1% METAL ALM
POWER SUPPLY DECOUPUNG
SOV CERAMC DISC

2. ~
3.

t)
-=
DGND

.

* REFERENCE
0P110NAL EXTERNAL

-----------

= ECL TERMINATION

...:----GROUND
CONNECTED
TO POWER
SUPPLY
AGND

*AN EXTERNAL REFERENCE CAN BE

IlASTER
REFERENCE
TOomER DACe

VCC
(+5VJ

VEED
(.5.2V)

USED OR THE REFERENCE FROM
THE REF our PIN CAN DRIVE TWO
ADDITIONAL HDACeI180o•.

VEEA
(·5.2V)

FIGURE 3. TEST LOADS

DIVCLKlDOUT LOAD

DACLOAD
OUTPur

----r--VCC
RL

CL
dpl
Dur

0--1'---K.

!---~

CL

~

DOur

CL.

15pF

TaD

RL.

28IJ.()

TBD

RL
37.sn

D • INl16 OR EQUIVALENT

DGND

Honeywell

3·95

~:::c

o
o
<0
,..

FIGURE 4. TYPICAL RGB GRAPHICS SYSTEM

10

~::I:

SINGLE GAIN CONTROL

t

DAC
REF IN

ISET

REF IN

t

t

ISET

ISET

ISET=

SLAVE

DAC
ISET

ISET

Rt
2000

SLAVE

ISET

t.2V
3(oJ (Rt) + R2)

INDIVIDUAL GAIN CONTROL

MASTER

SLAVE

SLAVE

DAC

DAC

DAC

ISET

ISET
Rl

Rt

soon

ISET=

3·96

SOM

7500

REF IN

ISET

REF IN

Rt

7500

SOOn

7SM

1.2V
ocT(Rl)

+

R2

Honeywell

FIGURE 5. ECLK, ECLK SWITCHING LEVELS

o
o

<0

.,....

O.OV

~

VIDF
_---"1~X

~~~:---------------------------

LO

~J:

VICM MIN

~ -------'~,,-'>. .~, ---------------. ·1.3V

"" ""

VICM MAX _______________

~~~~'---~Xl____ :

FIGURE 6. EQUIVALENT INPUT CIRCUITS-CLOCK, REFERENCE, DATA AND
CONTROLS

REFERENCE

CLOCK

DATA AND CONTROLS

IBIAS

VCC

REF IN

ISET

I
0-----.-8.2K

o----t-{
DATA AND
CONTROLS o---"II~-'--lO-~

o--.--{

REFERENCE
SEGMENT
SWITCH

ECLK

ISEG

rcrK o----!---+---'
_

-",_~_VEED

_--_-..--....--.>----

VEEA

DGND

o----+--~

_

FIGURE 7. EQUIVALENT DAC OUTPUT CIRCUIT
CURRENT SINK 11

...-----!---'1

ISET

CURRENT SINK IN
-!-~~---+---o

OUT+

O--..--.......----r---,

REF IN

Honeywell

3·97

0
0

PACKAGING INFORMATION

co

....

TOP VIEW

10

~
0

COLUMN

:::t:
B

C

D

E

F

0

0

0

0

0

0

0

DE7

DES

DE3

DE1

DDD

DD2

DD3

A

11

1D

0
ECLK

9

0
SYNCNI
SYNC1

8

7

0
DE6

G

H

J

0

0

DD5

DD6

0

0

0

0

0

0

0

DE4

DE2

DED

DD1

DD4

DD7

DC1

0
~

5

3

0
DC3

0
DC4

0

0

DCS

DC8

ECt:'R

0

0

0

0

DB1

DB2

0
0

Q.-

0
DB3

0

0
DB6

0
DBD

0
DB4

0
DB5

0

0

0

0

DGND

VEED

DA6

DB7

0
0
0

3·98

DC2

0

I SET

PIN 1

DCO

DC7

VEED
2

0

0

DIVCLK VCC
4

0

0

YNC DIV4/DIV5

==
~

L

FH

BRIGHT BLANK
6

K

REF
OUT

0
REF·IN

0
DGND

0
AGND

0

0

DA4

DA7

0

0

0

0

0

0

0

0

OUT+

AGND

DMD

DM3

DM5

DM7

DAD

DA2

DA5

0

0

0

0

0

DM4

DM6

OE

DA1

DA3

0
OUT·

0
VEEA

0

0

DM1

DM2

0

Honeywell

PACKAGING INFORMATION (Cont'd)

0
0

CD
.....

1.0

0
Column Row
A

Pin Nama
REF OUT

Function

Column Row Pin Nama

«C

Function

J:

REFERENCE OUTPUT

F

10
11

A

2

ISET

ISET REFERENCE CURRENT SET

F

A

3

VEED

NEGATIVE DIGITAL SUPPLY (-5.2V)

G

DD1

INPUT DATA WORD D, BIT 1

DD2

INPUT DATA WORDD,BIT2

DOUT4

MUX DATA OUT, BIT 4

A

4

DGND

DIGITAL GROUND (OV)

G

2

D0UT5

MUXDATADOUT,BIT5

A

5

DIVClK

DIVIDED CLOCK OUTPUT

G

10

DD4

INPUT DATA WORD D, BIT 4

A

6

SYNC

VIDEO SYNC INPUT

G

11

DD3

INPUT DATA WORD D, BIT3

A

7

BRIGHT

VIDEO BRIGHT INPUT

H

DOUT6

MUXDATAOUT,BITS

FORCE D/A DATA HIGH INPUT

H

2

DOUT7

MUX DATA OUT, BIT7 (MSB)

H

10

DD7

INPUT DATA WORD D, BIT7 (MSB)

11

A

8

FH

A

9

SYNCN/SYNC1 VIDEO CONTROLS SYNC MODE

A

10

EClK

ECl CLOCK INPUT

H

A

11

DE7

INPUT DATAWORDE,BIT7 (MSB)

J

B

1

AGND

ANALOG GROUND (OV)

J

B

2

DGND

DIGITAL GROUND (OV)

J

B

3

REF IN

REFERENCE INPUT

J

B

4

VEED

NEGATIVE DIGITAL SUPPLY (-S.2V)

K

B

S

VCC

POSITIVE DIGITAL SUPPLY (+S.OV)

K

B

6

DIV4IDIVS

DIVIDE SELECT 4 OR S (S ACTIVE lOW)

B

7

BLANK

B

8

EClK

DDS

INPUT DATA WORD D, BIT S

OE

MUX OUT ENABLE, ACTIVE lOW

2

DAO

INPUT DATA WORD A, BITO(lSB)

10

DC1

INPUT DATA WORD C, BIT 1

11

DDe

INPUT DATA WORD D, BITS

DA1

INPUT DATA WORDA,BIT1

2

DA2

INPUT DATA WORD A, BIT 2

K

3

DM

INPUTDATAWORDA,BIT4

VIDEO BLANK INPUT

K

4

DAB

INPUT DATA WORDA,BIT6

ECl CLOCK INPUT, COMPLEMENT

K

S

DBS

INPUT DATA WORD B, BIT S

B

9

RESET

RESET CONTROL, ACTIVE lOW

K

S

DB3

INPUT DATA WORD B, BIT 3

B

10

DES

INPUT DATA WORDE,BITS

K

7

DB1

INPUT DATA WORD B, BIT 1

B

11

DES

INPUT DATA WORD E, BIT S

K

8

DC7

INPUT DATA WORDC, BIT7 (MSB)

OUT-

DAC OUTPUT, SYNC DOWN

K

9

DCS

INPUT DATA WORDC, BITS

DAC OUTPUT COMPLEMENT, SYNC UP

K

10

DC3

INPUT DATA WORD C, BIT3

11

C
C

2

OUT+

C

10

DE4

INPUT DATA WORD E, BIT 4

K

C

11

DE3

INPUT DATA WORD E, BIT3

l

VEEA

NEGATIVE ANALOG SUPPLY (-S.2V)

l

D

DCO

INPUT DATA WORD C, BIT 0 (lSB)

DA3

INPUT DATA WORD A, BIT 3

2

DAS

INPUT DATA WORD A, BIT S
INPUT DATA WORD A, BIT7 (MSB)

D

2

AGND

ANALOG GROUND (OV)

l

3

DA7

D

10

DE2

INPUT DATA WORD E,BIT2

l

4

DB7

INPUT DATA WORD B, BIT7 (MSB)

D

11

DE1

INPUT DATA WORD E, BIT 1

l

S

DBS

INPUT DATA WORD B, BIT S

DOUT1

MJXDATAOUT,BIT1

l

6

DB4

INPUT DATA WORD B, BIT 4

E

2

DOUTO

MUXDATAOUT, BIT 0 (lSB)

l

7

DB2

INPUT DATA WORD B, BIT 2

E

10

DEO

INPUT DATA WORD E, BIT 0 (lSB)

l

8

DBO

INPUT DATA WORD B, BIT 0 (lSB)

E

11

000

INPUT DATA WORDD, BITO(lSB)

l

9

DC6

INPUT DATA WORD C, BIT 6

DOUT2

MUXDATAOUT,BIT2

l

10

DC4

INPUT DATA WORD C, BIT 4

DOUT3

MUXDATAOUT,BIT3

l

11

DC2

INPUT DATA WORD C, BIT 2

E

F
F

2

* * For Ordering Information See Section 1.

Honeywell

3·99

II

NOTES:

3·100

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HDAC52160

16-BIT VOLTAGE-OUTPUT DIGITAL TO ANALOG CONVERTER
ADVANCE INFORMATION

FEATURES:

APPLICATIONS:

• 16-Bit Accuracy
• On-Chip Band-Gap Voltage Reference
• On-Chip Application Resistors for Gain Selection
• Settling Time of 100 nS Typical to 16-Bit Accuracy
• -55 to +125°C Operating Temperature
• TTL Input Compatible

• Automatic Test Equipment
• Digital AHenuators
• Digital Communication Equipment
• Vector Stroke Video Imaging

II

GENERAL DESCRIPTION
The HDAC52160 is a 16-bit voltage-output digitalto analog
converter. This high-performance monolithic device offers
the highest speed/power ratio in the industry. Unique onchip functions include a band-gap voHage reference and
precision application resistors used to support output voltage scaling. Unlike current-output devices, this voHageoutput DAC simplifies the task of output buffering.
Several output voltage ranges are available depending on
external interconnection of pins lOS, BPO, 5V FSR, and
10V FSR. With respect to an all O's or all 1's input, these

ranges are +10to OV, +5toOV, +5 to -5V, +2.5to-2.5V, +15
to +5Vor +7.5 to +2.5V.
The HDAC52160 operates with separate ±15V analog
supplies and a +5V digital supply to provide maximum noise
immunity. All logic input levels are TTL and 5 volt CMOS
compatible. The device is manufactured on Honeywell's
Advanced Bipolar Linear process. This process process
allow the combination of dense, high-speed digital logic with
precision analog circuitry on a single chip.

BLOCK DIAGRAM

VCC
(+lSV)

REF
OUT

GAIN
CNTRL

DAC
RTN
B

REF
IN

DAC
RTN
A

DAC
RTN
SENSE

DACOUT
BIPOLAR
OFFSET

SV FSR

10V FSR

VEE1, VEEZ
(·lSV)

BANDGAP
VREF

OUTPUT
CURRENT
OFFSET

VEE
AGND

Honeywell

DGND

COMP

SW
REF

DIS
(MSB)

D14

DO
(LSB)

3-101

g
....
~

~

J:

SPECIFICATIONS
Typical at +25°e,VDD = +5V, VEE1 = VEE2 = -15V, vee = +15V, Unless otherwise specified.
Test
Test
Conditions Level (1)

Parameter

HDAC52160
Min Typ Max

Resolution

Units

16

Integral Linearity

LSI3

±1

LSB

Differential Linearity Error
Gain Error

Bits

± 112

% of Full Seale

± 0.01

Gain Error Tempeo

± 15

Offset Error

±1

mV

1

mA

Reference Input Current
VIH (Logic High Input Voltage

ppm/oC

V

2.4

VIL (Logic Low Input Voltage)

0.8

V

Output Voltage Settling Time

100

nsec

Total Power Dissipation

750

mW

(1) Test Procedure: I - Production tested at the specified conditions; II - Sample tested to ensure compliance.

PINOUT

HDAC52160

Q
Q

Q

>

CI

Z

Q

()
()

>

lW

I-

II.
II.

()

til

0
lZ

w

::)

0

eC

III
Z

()

Z

I-

a:
()
c·
Q

a:
a:
::)
()

W
W

>

II.

Q

.a:

CI

W

~

til

z

.c

....
a: !
lZ

0
Z

:cCI

II.

W

a:

l-

::)

o.
II.

W

a:

II.

:IE
0

()

Iiitil
II.
II.

0

a:

C
....
0

II.

iii

.. .
w

W

>

w

W

>

c
Z

I-

a:

()

C

e

w

til

Z
W

()

Z

til

Z

I-

a:
cQ

()

I::)

II.
I::)

0

* *For Ordering Information See Section 1.
3·102

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HDAC7541Z

CMOS, 12 BIT MONOLITHIC MULTIPLYING CAC
PRELIMINARY INFORMATION

FEATURES

APPLICATIONS

• Improved Version of the AD7541 A
• Low Output Capacitance « 75 pf.)
• Maximum Gain Error < 2 LSB (all grades)
·12 Bit Linearity Over Temperature
• Settling Time = 500 nsecs.
• +5V to + 15V operation

• Gain Control Circuits
• Programmable Gain Amplifiers
• Programmble Filters
• Function Generators
• DigHal/Synchro Converters
• Dig Hally Controlled Attenuation

GENERAL DESCRIPTION
The HDAC7541Z is a monolithic, low cost 12 bit digital to
analog converter (DAC). It is compatible with the industry
standard 7541 A but with significant performance
improvements in speed and gain accuracy.
The
HDAC7541 Z is fabricated in a 3 micron, polysilicon gate

CMOS process. The excellent linearity and gain accuracy
are achieved through the use of laser-trimmed thin film
resistors. Latch-up immunity is insured by the use of an
epi process base. This eliminates the need for external
Schottky clamping diodes.

BLOCK DIAGRAM
VREF-IN

R

R

18

17

.---!---o

~~~~;4-

R feedback

__~__~~~~~______~~__-+~~__+-+--+__~OUT1

~--~~--~~~~--~--------~~---r~---r----t--oOUT2

2

SWITCHES

14
MSB

Honeywell

BIT 2

BIT 10

BIT 11

GND

3-103

II

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 250C
Outputs
Vpin1. Vpin2 to GND........ ~ .........................-0.3V.VDD

Supply VoHages
VDD(pin 16)toGND...........................................+17V
VREF (pin 17) to GND: ........................................±25V

Temperature
Operating Temperature. ambient........... -55 to +1250C
junction......................+1500C
Lead Temperature. (soldering 10 seconds) ...... +300 oC
Storage Temperature ..............................-65 to +1500C
Power Dissipation (Any Package) to +750C...... 450mW
Derates above +750C......................................6mW;oC

Input Voltages
Vfeedback (pin 18) to GND ..................................±25V
Digital Input Voltage to GND (pins4-15) ..... -0.3V. VDD

Notes:
1.
Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal
applied conditions in typical applications. Excessive exposure to absolute maximum ratings may effect device
reliability.
CAUTION - ESD SENSITIVE DEVICE: The logic and analog ports of this device have special circuits to protect it
against ESD damage. Although this protection should prevent permanent damage to the inputs. care should
be taken in handling.
VDD

=15 volts; VREF =+1 Ovolts; VPIN1 =VpIN2 =0 volts; T=25°C unless otherwise noted

PARAMETER

TEST

TEST

HDAC7541ZA

HDAC7541ZB

CONDITIONS

LEVEL

MIN NOM MAX

MIN NOM MAX

UNITS

DC ELECTRICAL CHARACTERISTICS
Accuracy
Resolution

I

-

12

-

-

12

-

bits

Relative Accuracy

Tmin-Tmax

I

-1/2

±1/4

+1/2

-1

+1

LSB

Differential Nonlinearity

Tmin-Tmax

I

-1/2

±1/4

+1/2

-1

+1

LSB

Gain Error

Using Internal
Rfeedback
25°C

I

1.75

LSB

Tmin-Tmax

I

Tmin-Tmax

II

-

3

25·C
0-70·0/-25 to +85·C
-55 to + 125·0
All digital inputs at OV

I
I
I

-5
-10
-200

Gain Temperature
Coefficient

-

.75

-

2.0

-

-

0.3

3

-

0.3

3 LSB
ppml°C

Output Leakage

Pin 1

3·104

+5
+10
+200

-5
-10
-200

+5
+10
+200

nA

Honeywell

VDD = 15 volts; VREF = +1Ovolts; VpIN1 = VpIN2 = 0 voHs; T= 25°C unless otherwise noted

PARAMETER

TEST

TEST

CONDITIONS

LEVEL

HDAC7541ZA

HDAC7541ZB

MIN NOM MAX

MIN

NOM MAX

UNITS

DC ELECTRICAL CHARACTERISTICS
Output Leakage
25·C
Pin2

Reference Input Resistence

Digital Inputs

0-70·C/-25 to +85·C
-55 to + 125·C

All digital inputs at
VOO
Pin 17toGND
+25°C
Temp. Coefficient

I
I
I

I

-5
-10
-200

7

II

+5 -5
+10 -10
+200 -200

12.5
-180

18

7

+5
+10
+200

12.5
-180

18

nA

KQ

ppml°C

Tmin-Tmax

VIH (High Input VoHage)

I

VIL (Low Input VoHage)

I

0.8

0.8

liN (Input Current)

I

1

1

IJA

II

8

8

pF

2.4

2.4

Volts
Volts
-

CIN (Input Capacitance)

VIN = oVolts

Power Supply
I

VDDRange
IDD

PSRR

25·C
Tmin-Tmax I Digital
Inputs at VIL or GND
25·C
Tmin-Tmax I Digital
Inputs at VDD or VIH
IlVDD= ±5%

+5

+15

+16

+5

+15

+16

VoHs

I
I

1
1

1
1

mA
mA

I
I

3
4

3
4

rnA

I

-

±.001

II

-

50

100

-

50

II

-

200

400

-

200

±.005

-

±.001

±.005

mA
(Ilgain%)
(IlVDD%)

AC ELECTRICAL CHARACTERISTICS
From Digttallnput to
Propagation Delay

90% of Output Final

Value; Note 3
Digital to Analog Glitch Impulse

Honeywell

VREF = OV; Note 2

100

nsecs

400 nY-sec

3-105

VDD = 15 volts; VREF'= +10volts; VpIN1 = VpIN2 = ovolts; T= 250C unless otherwise noted
PARAMETER

TEST

TEST

CONDITIONS

LEVEL

HDAC7541ZA

HDAC7541ZB

MIN NOM MAX

MIN NOM MAX

UNITS

-

0.3

0.5

-

0.3

0.5

mV(p-p)

-

0.5

1.0

-

0.5

1.0

llSec

48

75

48

75

pF

15

25

15

25

pF

19

30

19

30

pF

38

65

38

65

pF

AC ELECTRICAL CHARACTERISTICS
Multiplying Feedthrough Error

VREFtoVOUT
VREF=±10Volts
10KHz Sinewave

Output Current Settling Time

To 0.01 % of full
scale; Notes 2 & 3

Output Capacitance
COUT1
COUT2
COUT1
COUT2

"
"

Tmin-Tmax
Pin1 ; Digital Inputs
=VIH
Pin2; Digital Inputs
=VIH
Pin1 ; Digital Inputs
=VIL
Pin2; Digital Inputs
=VIL

"
"
"
"

Note 2: Digital inputs change from OV to VDD or VDD to OV.
Note3: OUT110ad: 1000+ 13pf.
Voltage outputs derived using HOS-50 amplifier.

ELECTRICAL CHARACTERISTICS TESTING

TEST LEVEL

Production tested.

All electrical characteristics that follow are subject to the
following conditions:
All parameters having Min.lMax. specifications are
guaranteed. The Test Level column indicates the specHic
device testing actually performed during production and
Quality Assurance inspection. Any blank sections in the
data columns indicates that the specification Is not tested
at the specified condition.

TEST PROCEPURE

"

Parameter is guaranteed by sample testing.

Unless otherwise noted, all tests are pulsed tests, therefore
Tj = Tc· Ta.

3·106

Honeywell

N

."it

TYPICAL PERFORMANCE OVER VOO

It)

r--

(,)

«
c

NONLINEARITY vs.
SUPPLY VOLTAGE
N
0
N
L
I
N
E
A
R
I
T
Y
(LSB)

1.25

J:

= +25°C
V REF =+10V
TA

1.00
0.75

D

0.50
0.25
0
0

5

10

15

VOO (VOLTS)

GAIN ERROR vs.
SUPPLY VOLTAGE
G
A
I
N
E
R
R

1.0
0.8

= +25°C
V REF =+10V
TA

0.6
0.4

0
R
(LSB)

0.2
0
0

5

10

15

VOO (VOLTS)

Honeywell

3-107

TERMINOLOGY
RELATIVE ACCURACY

measured from the time a digital input changes to the
point at which the analog output at OUT1 reaches 90%
of its final value.
DIGITAL TO ANALOG GLITCH IMPULSE

Relative accuracy or endpoint nonlinearity is a measure
of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is
measured after adjusting for zero and full scale and is
expressed in % of full scale range or (sub)multiples of
1LSB.

This is a measure of the amount of charge injected from
the digital inputs to the analog outputs when the inputs
change state. It is usually specified as the area of the
glHch in nV-secs and is measuredwHh VREF= GND.

DIFFERENTIAL NONLINEARITY

CIRCUIT DESCRIPTION

Differential nonlinearity is the difference between the
measured change and the ideal 1 LSB change between
any two adjacent codes. A specified differential nonlinearity of 1LSB (max) over the operating temperature
range ensures monotonicity.

The HADC7541Z operation is best understood from the
simplified circuit description in Figure 1. The input VREF
is applied to an R-2R ladder network. The R-2R network
divides the VREF input by 2 at each stage to produce
currents in the 2R legs which decrease by a factor of 2
moving toward the LSB end of the ladder.

GAIN ERROR
Gain error or full-scale error is a measure of the output
error between an ideal DAC and the actual device
output. For the HDAC7541Z ideal full-scale output is
-(4095)/(4096),(VREF). Gain error is adjustable to zero
using extemal trims as shown in Figures 4 and 5.

The switches on each 2R leg allow this current to be
routed to analog ground or through the feedback
resistor of the external op-amp on OUT1. This op-amp
resistor converts the current to a voHage again. The sum
of the selected leg currents forced through Rfeedback
determines the output voltage by the equation in Figure
1.

OUTPUT LEAKAGE CURRENT
Current which appears at OUT1 with the DAC loaded to
all O's or at OUT2 wHh the DAC loaded to all 1'so
MULTIPLYING FEEDTHROUGH ERROR
AC error due to capacitive feedthrough from the VREF
terminal to OUT1 wHh the DAC loaded to all O's.
OUTPUT CURRENT SETTLING TIME
Time required for the output of the DAC to settle to
within 1/2LSB for a given digital input stimulus, i.e., 0 to
Full Scale.
PROPAGATION DELAY

The op-amp on OUT1 creates a vi.rtual ground point on
OUT1 such that the voltage on the 2R legs is ground no
matter which positions the current steering· switches are
in. This makes the input resistance seen by VREF a
constant R Ohms.
The HDAC7541Z uses a modification of this R-2R ladder
which has the largest 3 bits' current provided by equally
weighted resistors rather than binary scaled resistors.
This "segmentation" technique improves the linearity
and gain accuracy of the HDAC7541Z and lowers the
glitch energy during code transitions. This internal
structure, however, does not change the way the output
code is selected by the user. Therefore, the simplified
schematic in Figure 1 is suitable for understanding the
operation of the HDAC7541Z.

This is a measure of the internal delay of the circuit and is

3-108

Honeywell

EQUIVALENT CIRCUIT ANALYSIS
The equivalent output circuit of the HDAC7541Z is the
key to understanding offset, linearity and settling time.
Figures 2 and 3 illustrate these effects.
In Figure 2, the equivalent unipolar operation is
illustrated with an external op-amp and all switches LOW
to route all current to OUT2. The current from OUT2 is
composed of (4095/4096)-th's of the input current at pin
17 plus parasitic leakage currents of the switches. These
leakage currents are due to both junction and surface
leakage on the MOS switches. 1/4096-th of the input
current passes to the ground through the ladder terminal
2R resistor. OUT1 DC current is due only to switch
leakage.
Figure 3 shows the same equivalent circuit when all
switches are HIGH thereby routing all current to OUT1.
The conditions are symmetrical in this case to Figure 2.
The main effect of switch leakages in either case is an
offset voltage from the DAC when used in voltage output
mode as shown in Figures 2 and 3.
The output resistance seen at the input terminals of the
op-amp varies with the code chosen. Between Figures 2
and 3, resistance at each op-amp input can change from
10K Ohms to an open for extremes in code. This causes
the gain of the offsets (due to either leakage currents of
the DAC or op-amp offset) to be code dependent. For
example, the gain of offsets of the op-amp under these
extreme cases is given below:

voltage. In this DAC, this non-linearity is equal to the
offset itself. Thus, the total offset voltage of the op-amp
plus leakage induced offset of the DAC and op-amp
must be kept to less than 1 LSB to prevent degradation
to the DAC linearity performance.
The dynamic output impedance of OUT1 and OUT2 is
composed of the DAC switch capacitances to ground.
OUT2 has the capacitance of the OFF switches while
OUT1 has switch capacitance for ON switches.
The capacitance on OUT1 creates a feedback pole in the
voltage output operation mode (Figures 2 and 3).
Instability of the output amplifier can occur due to the
presence of this pole. This pole's instability effect is
typically compensated by the use of a feedback capacitorC1 (Figures 4 and 5). Although all R-2R DAC's have the
need for this type of compensation, the HDAC7541Z
maintains faster settling times when used in the voltage
output mode.
This is due to the lower output
capacitance ofthe HDAC7541Z.
The choice of compensation capacitor is bounded by
three limits:
o C1 along with Rfeedback determines the settling time
of the output voltage from the op-amp; therefore C1
should be as small as possible for minimum settling time.
o The pole defined by C1 and Rfeedback should be
smaller than secondary poles in the op-amp - as a rule of
thumb, about one half of the op-amp's gain-bandwidth.
o Settling time is proportionalto ~ COUT1 + C1. 1

Offset gain = 1 + Rfeedback"RDAC
With all code bits LOW:
RDAC» Rfeedback; offset gain = 1

For an OP-27 used as an output op-amp with 8 MHz
gain-bandwidth, the choice of C1 would be:
(201toC1oRfeedbackr1

With all code bits HIGH:
RDAC =10K Ohms; offset gain =2
Thus, the offset is not amplified by a constant gain over
the range of code input. This variation in offset gain is
seen as a non-linearity in the voltage output over the full
scale output. The magnitude of non-linearity is the difference in the gains at code extremes times the offset

Honeywell

= 4MHzor C1 = 4pf.

Fast settling time with small amounts of ringing are
obtained when the small values of C1 (given by the criteria above) are as close as possible to the DAC output
capacitance. The HDAC7541Z 's low output capacitance
comes much closer to fulfilling this goal than most other
7541 compatible DAC's. Thus, faster, more well controlled settling is seen with the HDAC7541Z.

3-109

II

ANALOG/DIGITAL DIVISION

The transfer function for the HDAC7541Z connected in
the multplying mode as shown in Figure 1 is:

FIGURE. 1
SIMPLIFIED, TYPICAL INTERFACE CIRCUIT

VO=-VIN. ( A1 +A2 +A3+··· .... ··· A 12

2122 23

212

)

where Ax assume a value of 1 for a "HIGH" bit and ofor a
"LOW'bit.
R

R

R

2R

GND

FIGURE 3
HDAC7541Z DAC EQUIVALENT CIRCUIT
ALL DIGITAL INPUTS HIGH

3·110

Honeywell

UNIPOLAR BINARY OPERATION·

2 QUADRANT MULTIPLICATION

BIPOLAR OPERATION·
4 QUADRANT MULTIPLICATION

Figure 4 illustrates the use of the HDAC7541Z in a
unipolar (or 2 quadrant multiplication) mode. The VREF
is applied from pin 17 to ground voltage or an input
current can be applied to pin 17. Positive or negative
voltages/current can be applied. The input is multiplied
by (-1) times the DAC code scaling.

The use of the HDAC7541Z in a bipolar (or 4 quadrant
multiplication) mode is illustrated in Figure 5. The VREF
is applied from pin 17 to ground voltage or an input
current can be applied to pin 17. Positive or negative
voltages/current can be applied. The output is either +1
or -1 times the code scaling of the DAC. The polarity is
selected by the MSB of the DAC input code.

R1 can be used to provide full scale output trimming
capability. The adjustment is made by selecting code
1111 1111 1111 and changing R1 for (4095/4096) of
the VREF voltage out.
If the source of VREF is
adjustable, VREF could be directly adjusted for full scale
calibration.

Amplifier A1's output is subtracted from 1/2 the value of
VREF to produce a maximum output which is half of
VREF in either polarity (see Table 3 for the exact scaling).
The MSB of the DAC selects the polarity of the output.

The output capacitance of OUT1 must be compensated
as described in Equivalent Circuit Analysis by the use of
C1 in the feedback path. This cancels the feedback pole
caused by OUT1 's capacitance.
The op-amp used with the HDAC7541Z should be
selected for low offset voltage and low bias currents to
reduce offset and linearity errors as described in
Equivalent Circuit Analysis. The op-amp's bias currents
appear as errors in the same fashion as the DAC's
leakage currents. The op-amp offset voltage should be
less than approximately 10% of an LSB (of the output full
scale voltage). This is due to the fact that the offset
effect is code dependant and contributes to the
nonlinearity in proportion to its size with respect to full
scale output voltage.

Full scale calibration of the output can be made by
adjusting R5 or the VREF source itself. Calibration of the
zero output at code 1000 0000 0000 is made by
adjusting R1. It is key that R3, R4 and R5 track one
another for the stability of the summation made at A2.
Failure of these resistors to track will result in both gain
and offset drift over temperature even though calibration
is done at room temperature.
As with unipolar operation, C1 is needed to compensate
the OUT1 capacitance. A1 must be selected for low
offset voltage and bias current to mInimize nonlinearity
and offset errors.

R2*

BIT 1 • BIT 12
*REFER TO TABLE 1.
FIGURE 4 UNIPOLAR BINARY OPERATION

Honeywell

3-111

II

R2"

VDD

R3

10K
R6

VOUT

SK

BIT 1· BIT 12
"FOR VALUES OF R1
AND R2 SEE TABLE 1.

FIGURE 5: BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)

TRIM
RESISTOR
"A" grades

"B" grades

R1

20n

100n

R2

6.8n

33n

TABLE I: RECOMMENDED TRIM RESISTOR VALUES VS. GRADES

BINARY NUMBER IN
DAC
MSB
LSB
1111
1000
0000
0000

1111
0000
0000
0000

ANALOG OUTPUT, VOUT

BINARY NUMBER IN
DAC
MSB
LSB

ANALOG OUTPUT, VOUT

1111

,V ,N

(~)
40116

1111

1111

1111

0000

,V ,N

( !!.!!.)
•·1/2 V IN
40116

1000

0000

0001

1000

0000

0000

OV

0111

1111

1111

,V ,N

0000

0000

0000

,V ,N

0001
0000

'V ,N

+V'N

(~)
2048

+V'N

(20~8

)

CO!6 )

oVolts

LO!8 )

TABLE II: UNIPOLAR BINARY CODE TABLE
FOR CIRCUIT OF FIGURE 4

3·112

( 2048 )

204s

TABLE III: BIPOLAR CODE TABLE
FOR CIRCUIT OF FIGURE 5

Honeywell

N
..~

10

OUT1
OUT2
GND
BIT 1 (MSB)
BIT2
BIT3
BIT4
BIT5
BIT6

I1
I2
I3
I4
I5
I6
I7
I8
I

•

18
17
16
N
,...

15

'lilt

It)

.....

14

C
J:

13

I BIT 10

12

I
I BIT 8
I BIT7

11
10

9

~
c

I Rfeedback
I VREF-IN
I VDD (+)
I BIT 12 (LSB)
I BIT 11

0

 - - - - . - - _...._._--~-_._.A,N.,...,...-w...--....,

,
~_ack

,

'OUT

R external

'OUT1

L3~;:~C~~~
I

Dell
(MSB)

DB~O

Dds

,,

,

DB2

DBI

Dllo

(LSB)

~---------------------------------------.
FIGURE 1 SIMPLIFIED HDAC7545A DAC CIRCUITRY
(WITH EXTERNAL OP AMP)

3-124

Honeywell

uses a modified R-2R ladder technique that provides
for superior linearity over similar devices which use the
basic R-2R ladder.
A basic R-2R ladder portion is used within the
HDAC7545A for the nine least-significant bits (bits 08). This ladder portion successively divides the
(remaining) VREF input to produce a binary weighted
nine-stage current division. In other words, in moving
from left to right, each 2R resistor leg has half the
current flow of the previous leg.
Double-pole
switches within each leg are controlled by the
respective input data bit. The switch routes the bitweighted current of the leg to either analog ground or
to the output (pin OUT1). OUT1 is a virtual ground by
means of the external active circuitry. Hence, with
every switch in either position, the R-2R ladder
resistive integrity is maintained. Input resistance of
pin VREF is kept constant.
Modification of the basic R-2R ladder structure occurs
in the 3 most-significant bits. Here, the switches of
seven equally weighted current dividers are
controlled by bits 9-11 via a logic decoder. Although
more complex, this method provides increased
accuracy. Application of the HDAC7545A is identical
to similar devices that use an unmodified R-2R ladder
network.
The DAC output current is converted to a voltage by
the feedback resistance composed of the external
resistor of Figure 1 in series with internal resistor
Rfeedback'
The operational amplifier provides a
buffered VOUT, and in combination with the feedback
resistance, maintains OUT1 at virtual ground. The
transfer function of Figure 2 shows the relationship of
VOUT for an equivalent R-2R resistor network, shown
in the same figure. A more detailed understanding of
the circuit operation and performance aspects are
found in the following Equivalent Circuit Analysis
section.

2R

2R

2R

2R

EQUIVALENT CIRCUIT ANALYSIS

The equivalent output circuit of the HDAC7545A is
the key to understanding offset, linearity and settling
time. Figures 3 and 4 illustrate these effects.
In Figure 3, the equivalent unipolar operation is
illustrated with an external op-amp and all switches
LOW to route all current to pin OUT2. OUT2 is
internally connected to AGND in packaged versions of
the HDAC7545A.
The current from OUT2 is
composed of (4095/4096)-th's of the input current at
pin VREF plus parasitic leakage currents of the
switches. These leakage currents are due to both
junction and surface leakage on the MOS switches.
1/4096-th of the input current passes to the ground
through the ladder terminal 2R resistor. OUT1 DC
current is due only to switch leakage.
Figure 4 shows the same equivalent circuit when all
switches are HIGH thereby routing all current to OUT1.
The conditions are symmetrical in this case to Figure
3.
The main effect of switch leakages in either case is an
offset voltage from the DAC when used in voltage
output mode as shown in Figures 3 and 4.
The output resistance seen at the input terminals of
the op-amp varies with the code chosen. Between
Figures 3 and 4, resistance at each op-amp input can
change from 10K Ohms to an open for extremes in
code. This causes the gain of the offsets (due to
either leakage currents of the DAC or op-amp offset)
to be code dependent. For example, the gain of
offsets of the op-amp under these extreme cases is
given below: (next page)

The transfer function for the
equivalent network shown is:

2R

VOUT=-VREF.

,
<>

BIT 11 (MSB)
I

vour

c\

BIT 13

All

... ()

-..- -

..
()

BIT g
BIT 0 (LSB)
A g ' • • • Ao

(&121 +&0.+".&2...\
22
21?)

where Ax assumes a value of 1
for a "HIGH" bit and 0 for a
"LOW"bit.

1- _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ,

FIGURE 2 EQUIVALENT R-2R RESISTOR NETWORK FOR THE HDAC7545A DAC CIRCUITRY

(WITH EXTERNAL OP AMP)

Honeywell

3-125

II

FIGURE 3

HDAC7545A DAC EQUIVALENT CIRCUIT
.

ALL DIGITALINPUTSLOW
(WITH EXTERNAL OP AMP)

YREF
R
O---~--~-----T------r---~--~

R,eedbo""
YREF

FIGURE 4

HDAC7545A DAC EQUIVALENT CIRCUIT

R

_
'REF

ALL DIGITAL INPUTS HIGH
(WITH EXTERNAL OP AMP)

f
Offset gain = 1 + RfeedbacWRDAC
With all code bits LOW:
RDAC » Rfeedback; offset gain =1
With all code bits HIGH:
RDAC = Rfeedback; offset gain = 2
Thus, the offset is not amplified by a constant gain
over the range of code inputs. This variation in offset
gain is seen as a non-linearity in the voHage output
over the full scale output. The magnitude of nonlinearity is the difference in the gains at code
extremes times the offset voltage. In this DAC, the
non-linearity is equal to the offset itself. Thus, the
total offset voltage of the op-amp plus leakage
induced offset of the DAC and op-amp must be kept
to less than 1 LSB to prevent degradation to the DAC
linearity performance.
The dynamic output impedance of OUT1 and OUT2 is
composed of the DAC switch capacitances to ground.
OUT2 has the capacitance of the OFF switches while
OUT1 has switch capacitance for ON switches.
The capacitance on.OUT1 creates a feedback pole in
the voltage output operation mode (Figures 3 and 4).
Instability of the output amplifier can occur due to the
presence of this pole. This pole's instability effect is
typically compensated by the use of. a feedbllck
capacitor - C1 (Figures 6 and 7). Although all R-2R
DAC's have the need for this type of compensation,

3-126

the HDAC7545A maintains faster settling times when
used in the voHage output mode. This is due to the
lower output capacitance of the HDAC7545A.
The choice of compensation capacitor is bounded by
three limits:
o C1 along with Rfeedback determines the settling
time of the output voltage from the op-amp; therefore
C1 should be as small as possible for minimum settling
time.
o The pole defined by C1 and Rfeedback should be
smaller than secondary poles in the op-amp - as a rule
of thumb, about
one half of the op-amp's gainbandwidth.
o Settling time is proportional to VCOUT1 + C1 ~
For an OP-27 used as an output op-amp with an 8
MHz gain-bandwidth, the choice of C1 would be:
(2oxoC1oRfeedbackl-1 = 4MHz,
or C1 .. ·4 pf
(Rfeedback '" 12.5 Kn)
Fast settling time with small amounts of ringing are
obtained when the small values of C1 (given by the
criteria above) are as close as possible to the DAC
output capacitance. The HDAC7545A 's low output
capacitance comes much closer to fulfilling this goal
than most other 7545 compatible DAC's. Thus,
faster, more well controlled settling is obtained with
the HDAC7545A.

Honeywell

DATA BUS

DATA BUS

• no.
Doccdod Add.... for tho HlAC7545A
til • Doccdod addr... for tho latch

• tlO. Docoded Add.... forthe HlAC7545A

MULTIPLEXED BUS ARCHITECTURE

SEPARATE ADDRESS/DATA BUS ARCHITECTURE

FIGURE 5 TYPICAL MICROPROCESSOR BUS INTERFACES FOR HDAC7545A

INTERFACE LOGIC
The HDAC7545A is designed to allow control of the
output via a parallel microprocessor bus "0. This
section describes operation of the interface controls
to accomplish this.
A typical parallel bus I/O configuration is shown in
figure 5 . The microprocessor provides the DAC code
as well as all control signals to load the code and
update the analog output.
During loading the
HDAC7545A accepts the DAC input code in a 12 bit
word.

the VREF voltage out. If the source of VREF is
adjustable, VREF could be directly adjusted for full
scale calibration (refer to table II).
The output capacitance of OUT1 must be
compensated as described in Equivalent Circuit
Analysis by the use of C1 in the feedback path. This
cancels the feedback pole caused by OUT1's
capacitance.

VDD

R2'

When the CS pin is at logic "0", the input register of
the HDAC7545A is enabled. The WR input actually
stobes the input data from the parallel bus into the
HDAC7545A data register. This occurs on the falling
edge of this WR pulse. The Write Timing Diagram of
page 4 defines the minimum set-up and hold times
required by the control lines to successfully transfer
data in this fashion.

V!-U

UNIPOLAR BINARY OPERATION·
2 QUADRANT MULTIPLICATION

FIGURE 6 UNIPOLAR BINARY OPERATION

Figure 6 illustrates the use of the HDAC7545A in a
unipolar (or 2 quadrant multiplication) mode. The
VREF is applied from pin 19 to ground voltage or an
input current can be applied to pin 19. Positive or
negative voltages/currents can be applied. The input
is multiplied by (-1) times the DAC code scaling.

The op-amp used with the HDAC7545A should be
selected for low offset voltage and low bias currents to
reduce offset and linearity errors as described in
Equivalent Circuit AnalysiS.
The op-amp's bias
currents appear as errors in the same fashion as the
DAC's leakage currents. The op-amp offset voltage
should be less than approximately 10% of an LSB (of
the output full scale voltage). This is due to the fact
that the offset effect is code dependant and
contributes to the nonlinearity in proportion to its size
with respect to full scale output voltage.

R1 can be used to provide full scale output trimming
capability. The adjustment is made by selecting code
1111 1111 1111 and changing R1 for (4095/4096) of

Honeywell

Rl'

'REFER TD TABLE 1.

3-127

BIPOLAR OPERATION·
4 QUADRANT MULTIPLICATION
The use of the HDAC7545A in a bipolar (or 4
quadrant multiplication) mode is illustrated in Figure 7.
The VREF is applied from pin 19 to ground voltage or
an input current can be applied to pin 19. Positive or
negative voltages/currents can be applied.
The
output is either +1 or -1 times the code scaling of the
DAC. The polarity is selected by the MSB of the DAC
input code.

Full scale calibration of the output can be made by
adjusting R5 or the VREF source itself. Calibration of
the zero output at code 1000 0000 0000 is made by
adjusting R1. It is key that R3, R4 and R5 track one
another for the stability of the summation made at A2.
Failure of these resistors to track will result in both gain
and offset drift over temperature even though
calibration is done at room temperature.

Amplifier A1's output is subtracted from 1/2 the value
of VREF to produce a maximum output which is haH of
VREF in either polarity (see Table 3 for the exact
scaling). The MSB of the DAC selects the polarity of
the output.

As with unipolar operation, C1 is needed to
compensate for OUT1 capacitance. A1 must be
selected for low offset voltage and bias current to
minimize nonlinearity and offset errors.

TRIM
RESISTOR

"A" grades "8" grades
200

1000

R2

s.an

330

• REFER TO TABLE 1.

BIT 1 • BIT 12

TABLE I
RECOMMENDED TRIM RESISTANCE

FIGURE 7 BIPOLAR OPERATION

BINARY NUMBER IN
DAC
LSB

R1

ANALOG OUTPUT, V OUT

MSB

BINARY NUMBER IN
DAC
LSB
MSB

ANALOG OUTPUT, V OUT

111'

1111

1111

-v IN (~)
4096

1'11

1111

1111

+VIN

1000

0000

0000

-v IN (:::) =-11l! V IN

1000

0000

0001

+VIN (_1_)

0000

0000

0001

.V IN

1000

0000

0000

ov

0000

0000

0000

OVolt1

011'

11'1

'1'1

.V IN (_1_)

0000

0000

0000

.V IN

(4~ )

(~)
2048

2048

2048

TABLE II
UNIPOLAR BINARY CODE
FOR CIRCUIT OF FIGURE 6

3-128

(~)
2048

TABLE III
BIPOLAR CODE
FOR CIRCUIT OF FIGURE 7

Honeywell

OUTI

•

R feedback

AGND
DGND

VDD
WIf

DB10

C1"

~

DB9

~

DBO (LSB)

DB8

::J:

DBI

Q

DB7

DB2

DB6

DB3

DBS

DB4

FUNCTION

1

OUTl
AGND
DGND
OBll
DB10
DB9
DBa
DB7
OBS
DB5
DB4
DB3
DB2
DBl
DBO

ANALOG CURRENT OUTPUT
ANALOG GROUND
DIGITAL LOGIC GROUND
INPUT DATA BIT 11 (MSB)
INPUTDATABIT10
INPUT DATA BIT 9
INPUTDATABIT8
INPUTDATABIT7
INPUT DATA BIT6
INPUT DATA BIT 5
INPUTDATABIT4
INPUT DATA BIT3
INPUT DATA BIT2
INPUTDATABITl
INPUT DATA BITO (LSB)
CHIP SELECT
DATA WRITE
POSITIVE POWER SUPPLY
REFERENCE INPUT VOLTAGE
INTERNAL FEEDBACK RESISTOR

3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

00(
It)

PIN NAME

2

VREF

(MSB) DBll

PIN

OS

WR
VDD
VREF
Rfeedback

HDAC7545A PIN FUNCTIONS

HDAC7545A PIN ASSIGNMENT
(TOP VIEW)

2

2

=
3

~

4

II!!

19 18

1

ID

mil mil

ID
fill

17

IIJII

N/C
NC
16

1m

5

fill

IiiiiiI

6

II!!

m

NlC
15

!!ill

N/C

N/C

II!!

IIJII

m m

m

!!ill

I!I!il

7

8

9 10 11 12 13 14

1m

IIliI

!!ill

N/C = No Connection.

HDAC7545A DIE PLOT
BONDING PAD LOCATION

Die Size 130 x 106 mils

* *For Ordering Information See Section 1.

Honeywell

3-129

NOTES:

3-130

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HDAC97000

8-BIT, HIGH SPEED RASTER D/A CONVERTER
FEATURES:

APPLICATIONS:

• 200 MWPS Conversion Rate
• Pln·Compatlble with AD9700 with Improved
Performance

• Color or Monochrome Displays
• High Resolution Raster Graphics
• Medical Electronics: CAT, PET, MR Imaging
Displays
• CRT Terminals
• CAD/CAE Workstations
• Solids Modeling
• General Purpose High·Speed D/A Conversion

• RS·343·A Compatible
• Complete Video Controls: Sync, Blank, Bright
and Reference White
• ECl Compatible
• Single Power Supply
• Stable On·Chip Bandgap Reference

GENERAL DESCRIPTION
The HDAC97000 is a fully monolithic B·bit video digital·
to·analog converter specifically designed for raster
graphic display applications. The HDAC97000 is com·
plete with an B·bit D/A converter, special video con·
trois, on·chlp bandgap reference and data registers.
Four unregistered video controls (Sync, Blank, + 10%
Bright and Reference White) allow full reconstruction
of RS·343·A compatible video signals from composite
inputs. All data and control inputs are compatible with
standard ECL.

The HDAC97000 will directly drive a doubly·
terminated 75 Ohm transmission line to standard
video levels.
The precision internal reference Is a bandgap type,
suitable for stable operation over wide temperature
ranges. The HDAC97000 is fabricated using an ad·
vanced VLSI Bipolar process for excellent perfor·
mance, low power consumption, and high reliability in
a choice of convenient packages.

BLOCK DIAGRAM
SYNC
BLANK
BRIGHT
REFWH

VIDEO CONTROL
LOGIC

) - _.... ANALOG
OUTPUT
VIDEO
DATA

CLOCK

GLITCH
ADJUST

Honeywell

SET·UP

ISET

3·131

o
o
o
.....

ABSOLUTE MAXIMUM RATINGS
Supply Voltagel

m

VEE ............................................................... " .................... .,. 7.0 to 0.5V

~

Input Voltagll
Clock, Data and Controls (measured to GND) ...................................................... VEE to 0.5V

::I:

Output
Analog Output applied voltage (measured to GND) ................................................. - 3.0 to 3.0V
Analog Output applied current' ..................................................................... 60mA
Output Short Circuit Duration. . . . . . .. . .......................................................... Unlimited

Temperatura
Operating, ambient .......... " ....... '" ................................................ -60to + 140·C
junction ............................................................................ + 1.75·C
Lead,soldering(10seconds) .................................................................... +300·C
Storage ............................................................................... -6010 +150OC

Not••:
1. Operation at any Absolute Maximum Rating Is not Implied. See Electrical Specifications for proper nominal applied
conditions In typical applications.
2. Current Is specified as positive conventional current flowing into the device.

ELECTRICAL SPECIFICATIONS
PARAMETER

TEST
CONDITIONS

TEST
LEVEL

DC ELECTRICAL CHARACTERISTICS vCCA = O.OV, VEEA = vEED
lEE

Supply Current

I

Cln

Input Capacitance
Clock, Data & Controls

V

Voc

Output Compliance Voltage

V

CO UT Output Capacitance

V
IREF = MAX

TYP

MAX

UNITS

= -5.2V :to.3V, TA = -2510 +85·C*,CC = OpF.
-155 -170
3
-2
560

ROUT Equivalent Output Resistance

lOUT Maximum Output Current

MIN

800

pF
+0.5

V

1040

Ohms
pF

15

IV

mA

-30

mA

IlL

Input Current, Logic
LOW, Data & Controls

I

70

120

!IA

IIH

Input Current, Logic
HIGH, Data & Controls

I

90

150

!IA

IL

Linearity Error,
Integral, Terminal Based

Notes 2,3

I

±0.19

% Gray Scale

DNL

Linearity Error
Differential

Notes 2,4

I

±0.19

% Gray Scale

lOS

Output Offset Current

Data = Sync =
Blank = 1,
Bright
0

I

-1

-8

!IA

=

3-132

Honeywell

PARAMETER

TEST
CONDITIONS

TEST
LEVEL

MIN

TYP

MAX

UNITS

o
o
or....

m

DC ELECTRICAL CHARACTERISTICS vCCA =O.OV, VEEA = VEEO = -S.2V ±O.3V, TA = -2S to
VOS

Output Offset Voltage

I

-37 -300

EG

Absolute Gain Error

I

±5

TCG

Gain Error Tempco

PSS

Power Supply
Sensitivity

VEE

Supply Voltage

V,L

Input Voltage, Logic LOW

I

V,H

Input Voltage, Logic HIGH

I

+8SOC·, Cc

I

-4.75 -5.2

p.V

% GrayScale

.005

%N

-5.5

V

-1.70

V

8

Bits

LSB WEIGHT (voltage) 5

2.5

mV

LSB WEIGHT (current)5

66.67

p.A

Oto 17
637.5
±0.19
±0.19
Guaranteed
0.4

TEMPERATURE COEFFICIENTS
Linearity
Zero Offset
Gain Error
DATA INPUTS
[Complementary Binary (CBN)]
Logic Compatibility
Logic Voltage Levels "1"
(Positive Logic) "0"
Input Capacitance
Input Resistance
REFERENCE WHITE, COMPOSITE
SYNC, BLANKING AND 10%
BRIGHT INPUTS
Logic Compatibility
Logic Voltage Levels "1"
(Positive Logic) "0"
Input Capacitance
Input Resistance

Honeywell

II

V

-0.90

RESOLUTION (full scale)

GRAY SCALE OUTPUT
Current
Voltage
Linearity, Differential
linearity, Integral
Monotonicity
Zero Offset (Initial)

mA
mV
% GrayScale
% GrayScale
mV
ppm/oC
ppm/oC
ppm/oC

30
12
50

ECL

-0.9
-1.7
to VEE
to VEE

5
50

V
V
pF
KG

ECL

-0.9
-1.7
to VEE
to VEE

5
50

~

J:

ppm/oC

50
Supply to Output

= OpF.

V
V
pF
KG

3-133

PARAMETER

TEST
LEVEL

TEST
CONDITIONS

DC ELECTRICAL CHARACTERISTICS vCCA = O.OV, v EEA = VEED =

MIN

TYP

MAX

-.5.2V ±O.3V, TA = -2510 +85°C*,CC

SET-UP CONTROL 5,6
Ground
Open

-53.6

1K Ohm to - 5.2 Supply

-71.4

-5.2V

-142.9

OUTPUT-COMPOSITE SYNC 5, 6
Current
Voltage
OUTPUT-10% BRIGHT5,7
Current
Voltage
OUTPUT-COMPOSITE BLANKING 5,6
Current

Oor
-7.6
o or
-286

mA
(±5%)
mV
±5%)

o or
-1.9
oor
-71

mA
(±5%)
mV
(±5%)

o and
-1.43
-1,90
or
-3.81
o and
-53.6
-71
or
-142.9

Voltage

POWER REQUIREMENTS
Current Consuption ( - 5.2V)
Power Dissipation
Power Supply Rejection

mA
(±5%)

mV
(±5%)

140
728
.025/.25

-25
-55

= OpF.

mV(O IRE
Units)
mV(7.5IRE
Units)
mV (10 IRE
Units)
mV(20 IRE
Units

0

TEMPERATURE RANGE
Operating (Ambient)
Storage

UNITS

mA
mW
% Gray Scalel
V
+85
+150

·C
·C

DC ELECTRICAL CHARACTERISTICS NOTES
*(JCA = 30·CIW typical at 500 LFPM.
1. The sum of tpWL and tpWH must always equal or exceed the minimum conversion cycle time.
2. Gray Scale
Video White Level - Video Black Level
643mV (nominal)
3. ± % Gray Scale
LSB (Least Significant Bit).
4. ± % Gray Scale
LSB (Least Significant Bit).
5. 90 IRE Full Gray Scale.
6. Relative to Black.
7. Reference White, Composite Sync, and Composite Blanking are enabled with logic "0"; 10% Bright is enabled
with logic "1". Composite Sync or Composite Blanking control signals reset Input registers.

=

=

=

=

3·134

Honeywell

ELECTRICAL SPECIFICATIONS

PARAMETER

o
o
o.....
0)
TEST
CONDITIONS

TEST
LEVEL

MIN

AC ELECTRICAL CHARACTERISTICS RL = 37.5 Ohms. CL = 5PFTA = 2510
F

Maximum Conversion Rate

Td

Clock to Output Delay

tst

Settling Time

± Y2 LSB
± 0.2% Gray Scale3

t r, tf

Rise/Fall Time

10% to 90% of
Gray Scale3

SR

Slew Rate

Note 2

TVP

MAX

UNITS

+85°C'

200

MWPS
4.0

300

450

ns
10

ns

1.75

ns

Vlp.s

tpWL Clock Pulse Width, LOW'

2.0

ns

tpWH Clock Pulse Width, HIGH

2.0

ns

ts

Hold Time, Data and Controls

2.5

tH

Hold Time, Data and Controls

0

PSRR Power Supply
Rejection Ratio

Supply to Output'

GE

Peak Glitch Area
("Energy")

Notes 5,6

FTC

Feedthrough, Clock

Data = Constant 7

FTD

Feedthrough, Data

Clock = Constant

SPEED PERFORMANCEGRAY SCALE OUTPUT
Settling Time (Voltage Max.)
Slew Rate
Update Rate
Rise Time
Glitch Energy
STOBE INPUT
Logie Compatibility
Logic Voltage Levels "1"
(Positive Logie) "0"
Set-up Time (Data)
Hold Time (Data)
Propagation Delay

Honeywell

Logic Loading
5pF and 50kO
To -5.2V

1.5

ns

-0.5

ns

-22
V

dB
35

-22

pico-VoltSeconds
dB
dB

7

10

ns (to 0.4% of
GrayScale)

400
200
1.5
50

V/p.s

ECL
-0.9
-1.7
1.5
0
4

MWPS
ns
pV-s

V
V
ns
ns
ns

3-135

~

J:

PARAMETER

TEST
CONDITIONS

AC ELECTRICAL CHARACTERISTICS RL
SPEED PERFORMANCECONTROL INPUTS
Composite Sync
Composite Blank
Reference White
Reference Biack
10% Bright

TEST
LEVEL

MIN

TYP

MAX

UNITS

= 37.5 Ohms, CL =5pF TA = 25 to + 85°C·

Settling Time
To 10% of
Final Value

10
10
10
10
10

ns
ns
ns
ns
ns

AC ELECTRICAL CHARACTERISTICS NOTES

=

*8CA
30·CIW typical at 500 LFPM.
1. The sum of tpWL and tpWH must always equal or exceed the minimum conversion cycle time.
2. MWPS-MegaWords Per Second ... MHz.
3. Gray Scale = Video White Level - Video Biack Level = 643 mV (nominal).
4. 20 KHz, 600mV pop ripple superimposed on VEE: dB relative to full Gray Scale
OdB.
5. Glitch can be further reduced by trimming Glitch Adjust.
6. Glitch Area (voltage time) Is sometimes referred to as an "energy", although this is not dimensionally correct. The
Peak Glitch Area is the maximum area deviation from the ideal output. Since glitches are typically "doublets" of
symmetric positive and negative excursions, the average glitch area approches zero.
7. dB relative to full Gray Scale
OdB, 300 MHz bandwidth limit.

=

=

ELECTRICAL CHARACTERISTICS TESTING

TEST LEVEL TEST PROCEDURE

All electrical characteristics are subject to the following conditions:
All parameters having Mln.lMax. specifications are
guaranteed. The Test Level column indicates the specific
device testing actually performed during production ,and
Quality Assurance Inspection. Any blank sections In the data
columns Indicates that the specification Is not tested at the
specified conditions.
Unless otherwise noted, all tests are pulsed tests, therefore
Tj = Tc = Ta.

100% production tested at the specified
temperature.
II

100% production tested at Ta = 25°C, and
sample tested at specified temperature.

III

QA sample tested only at specified
temperatures.

IV

Parameter Is guaranteed (but not tested) by
design and characterization data.

V

Paramater Is a typical value for Information
purposes only.

HDAC97000 VIDEO DAC CHARACTERISTICS
COMPOSITE VIDEO SIGNAL
256 gray levels plus Sync, Blank, Bright end Reference White

STEP SIZE
2.5mV
GRAYSCALE RANGE
0.6375 V Peak to Peak

3-136

HoneyWell

HDAC97000 VIDEO DAC CHARACTERISTICS
REFERENCE WHITE LEVEL
+ 100 IRE Units (+ 0.714V) relative to Blanking Level with standard set·up,
(+ 0.6375V relative to Reference Black)
DIGITAL INPUT FOR REFERENCE WHITE
All ones (11111111)

REFERENCE WHITE CONTROLS - PIN 16
Logic "0" overrides Video Input Word and drives to Reference White Level
REFERENCE BLACK LEVEL
- 0.7085 Absolute
+ 10 IRE Units (+ 71mV) relative to Blanking Level with standard set-up
DITIGAL INPUT FOR REFERENCE BLACK
All zeros (00000000)
SET-UP CONTROL
User Programmable In four levels to set Blanking Level (relative to Reference Black)

!!!Y1.
2.
3.
4.

Input Grounded
Input Open
Input 1K Ohm to - 5.2V
Input to - 5.2V

O
-53.6
-71.4
-142.9

IRE Units

o
7.5
10 (Standard Set-up)
20

COMPOSITE BLANKING LEVEL (with standard set-up)
- 0.785V Absolute
-10 IRE Units (-71mV) relative to Reference Black
COMPOSITE BLANKING CONTROL· PIN 18
logic "0" overrides Video Input Word and drives output negative by the
amount of set·up voltage relative to the Reference Black Level
COMPOSITE SYNC LEVEL
-1.071V absolute with standard set-up
- 40 IRE Units ( - 0.286V) relative to Blanking Level
COMPOSITE SYNC CONTROL - PIN 17
logic "0" overrides Video Input Word. and drives output 0.286V negative
relative to the Reference Black Level (relative values of Blank and Sync
Levels sum together with both active)
10% BRIGHT LEVEL
OVAbsolute
All levels are shifted down by 71mV when the 10% Bright Control Is used
10% BRIGHT LEVEL - PIN 19
Logic "0" causes output to go positive by 71mV relative to Reference White
Level
STROBE INPUT - PIN 11
logic "0" to "1 " transition clocks input register - Input data held by
latch, slave latch tracks master latch data
logic "1" to "0" transition· slave latch holds previous data, master
latch tracks Input

Honeywell

3·137

APPLICATION INFORMATION
The HDAC97000 is a fully monolithic 8·blt video D/A
Converter for graphic display applications. It has com·
plete composite controls including Sync, Blank,
Reference White, Set·up and 10% Bright, and will
directly drive a 75 Ohm load to RS·343·A video levels.
All data and control inputs are compatible with stand·
ard ECL. The HDAC97000 is packaged in a 22 lead
dual·in·line package and is pin·compatible with the
Analog Devices AD9700.

Video set·up level (the difference between video black
and video blank) may be programmed for 0, 7.5, 10, or
20 IRE units, depending on the condition of the Set·up
Select control.
The HDAC97000 uses a fully binary weighted ap·
proach utilizing current switches to implement the
DAC. The upper 3 bits are segmented with inter·
digitated current sources for good matching and bet·
ter linearity. Each data pin has latches for deskewing
input data if the data arrives at different times. This
prevents glitches from occurring at the output.

The video control inputs (Sync, Blank, Bright and
Reference White) are used for reconstruction of RS·
343·A compatible signals from video control inputs.

FUNCTIONAL DIAGRAM

10%IRIGHT
CQIIIII'I.ISITE ILANK
COMPOSITE SYNC
REF WHITE

{

IMSBl D1

VIDEO
DATA

~

D3

D4
DB
DI
D7
ILllIlI D.

1.
1.
17
11

VIDEO CONTROL
LOGIC

J

11

3
4
5
I
7

.

II:

'r-!

i

••

II:

10

CLOCK 11

DlA
CONVERTER

20

1122
VCCD

21

ANALOG
OUTPUT

lOOn

T
REFERENCE

21

13

15

GLITCH SET·UP COMP
ADJUST

I

12

14
ISET

TYPICAL INTERFACE CIRCUIT
A typical interface circuit using the HDAC97000 in a
color raster application is shown in· Figure 2. Although
the HDAC97000 requires few external components
and Is extremely easy to use, there are several con·
slderatlons that should be noted to achieve best per·
formance. The very high operating speeds of the
HDAC97000 require good circuit layout, decoupling of
supplies, and proper design of transmission lines.
Video input data and controls may be directly con·
nected to the HDAC97000. Note that all ECL inputs are
terminated as close to the device as possible to
reduce ringing, crosstalk and reflections. A con·
venient and commonly used mlcrostrlp impedance is
about 130 Ohms, which Is easily terminated using a

3·138

330 Ohm resistor to Vee and a 220 Ohm resistor to
Ground. This arrangement gives a Thevenin
equivalent termination of 130 Ohms to - 2 Volts
without the need for a 2 Volt supply. Standard SIP
(Single Inline Package) 220/330 resistor networks are
available for this purpose.
It is recommended that the strlpline or microstrip
techniques be used for all ECL Interface. Printed circuit wiring of known impedance over a solid ground
plane is recommended. The ground plane should be
constructed such that analog and digital ground currents are isolated as much as possible. The
HDAC97000 provides separate digital and analog Vee
connections to simplify grounding layout.

Honeywell

The analog output and ISET pin are configured so the
device can directly drive a 37.5 Ohm impedance
system as shown. The source impedance of the
HDAC97000 output is 800 Ohms ± 30%, thus
needing an external source-termination resistor to
drive a 75 Ohm transmission line. The load resistor (Rl)
must be 82.8 Ohms to attain standard RS-343-A video
levels. Any deviation from this impedance will affect
the resulting video output levels proportionally. As with
the data interface, it Is important that the analog
transmission line has a matched impedance throughout, including connectors and transitions between
printed wiring and coaxial cable. The combination of
source termination resistor Rs, load resistor Rl and
load terminator RT minimizes reflections of both forward and reverse travelling waves in the analog
transmission system. The return path for analog output current is Vrx:A, which is connected internally to the
source-termination resistor, Rs.
No external reference is required for operation of the
HDAC97000, as this function is provided internally.
The internal reference is a bandgap type and is
suitable for operation over· extended temperature
ranges.
The HDAC97000 operates from a single standard + 5
Volt or - 5.2 Volt supply. Proper bypassing of the supplies will augment the HDAC97000's inherent supply
noise rejection characteristics. As shown, a large tantalum capacitor in parallel with smaller ceramic
capacitors is recommended for best performance.
The small-valued capacitors should be connected as
close to the device package as possible, whereas the
tantalum capacitor may be placed up to a few inches
away. Additional decoupling can be accomplished by
plaCing a .D1I'F between the compensation pin (15)
and Vrx:A. This pin connects internally to the DAC
reference, which provides the DAC DC bias.

The timing diagram for the HDAC97000 is shown in
Figure 1. Data to the DAC is simultaneously entered on
the rising edge of the clock. Data must be valid for a
set-up time of ts before, and for a hold time of tH after
the riSing edge of the clock, in order to be correctly
entered. The DAC outputs will change in accordance
to the clocked input data after a delay time of to. The
settling time is specified as the time from when the
DAC output is no longer within Yz LSB of the previous
value until it is within Yz LSB of the new value.
The video control inputs cause the DAC output to
change directly, without regard to the clock Input. All
video controls (Sync, Blank, Bright and Reference
White) are active-Low (negative true) logic. Figure 3 illustrates the operation of Sync and Blank inputs and
the resulting video output signal. As shown, both Sync
and Blank must be Low to achieve the proper video
Sync level. The video control input hierarchy is given In
Table 1, with typical output levels for a set-up level of
10 IRE.
Set-up level is the difference between video Blank and
Black levels. The HDAC97000 supports set-ups of 0,
7.5, 10, and 20 IRE, which are programmed by connecting the Set-up select input to ground (OV), not connected, to VEE through a 1K Ohm resistor, or to VEE
(- 5.2V), respectively. For most applications the 7.5
IRE option is suitable.
The Reference White Input forces the DAC outputs to
an all "1"s level, which is video "white" in most
systems. This is especially useful for clearing the
display screen to white during system reset or powerup. The Bright input adds 10% of full-scale video to the
present video level. The Bright feature is commonly
used for highlighting cursors or creating overlays of
video information. Sync, Blank and Reference White
override the data inputs, while Bright may be applied to
any video level.

FIGURE 1 TIMING DIAGRAM

VIH

CLOCK

DATA IN

OUTPUT

Imi1~

VI.
VI.

i------I--+-t-r---.~

Honeywell

...

3-139

o
o
o

"-

CD

~

:r:

II

SETTING OUTPUT DRIVE CAPABILITY
The current set pin (pin 14) adjusts the full-scale output
current of the HDAC97000. The resistor designated RSET '
which governs the current into pin 14, can be calculated in
relation to DAC output current as follows:
Equation 1: RSET =

~[

:J

1.23V
22.59l!oUTO.S/RLOAD ~

Here, 1.23V is the internal reference voltage, VOUTO.S. is the
DAC gray scale output voltage and RLOAD is the total load
resistance on the analog output. In raster scan video applications, RLOAD could be equivalent to the load in Figure 2.
This would be the internal DAC output resistance in parallel
with the output load and cable terminating resistor. If the
device is being used in raster scan applications, the total
output voltage is the gray scale current plus the video
function currents. The value of RSET using the total current
(or voltage) can be calculated with equation 2:
Equation 2: RSET

=

140 + B ~ 1.23V
22.59 lVou/R LOAD

J

where B is equal to the value of the setup (BLANK) level (0,
7.5, 10 or20). The total output voltage capability is 1.13V,
which is more than adequate for composite video waveforms.

In other applications where lighter loads are used, RSET
can be increased, thus decreasing power dissipation
since the output current Is decreased. Figure 7 shows
an example where this applies if a large output voltage
or current swing is not needed.

GLITCH ADJUST AND COMPENSATION
Glitch adjust and compensation are optional functions
that can be used to improve dynamic ·performance.
Glitch adjust is an external adjustment of the logic
threshhold in the DAC switches to skew the speed In
order to get an output glitch energy below the data
sheet specification. This can be done with a resistive
pot in conjunction with pin 20 and VEE as shown in
Figure 2. Adjust the pot for minimum output glitch
when the input code is toggling between 01111111
and 10000000; the code transition which normally
causes the largest glitch.
Compensation is accomplished by connecting a .01J.'F
capacitor to pin 15. Actually this is a decoupling
capacitor connected internally to the DAC biasing net·
work. It adds more decoupling as needed if operating
with a noisy supply or environment as well as decoupling internal switching noise. This is different than the
AD9700, which uses the capacitor to externally compensate the voltage reference buffer amplifier. The
amplifier in theHDAC97000 is internally compensated
and therefore the compensation pin is used for the optional decoupling function.

FIGURE 2 HDAC97000 TYPICAL INTERFACE CIRCUIT

VIDEO DISPLAY

r----'

...
"r

I

'-----

"uT-.
'10uy

I_.!-!!V-\
\'out"'"

.LOAD· .. U'\II"" ....eo

I~
_.

\

:.: ,

Inltllt ......
.....

• INDtCA1D 0fITI0NM. FUNCftONa

__w_.

EeL lIfI......TION

+-

VCCo\

-!-Vcc•

3-140

Honeywell

Table 1

= 10 IRE and 75 Ohm

Video Control Operation (Output values for Set·up
standard load)1

0
0

0
,....
Sync"'

Blank'

0

0
0

Ref White

0
0

0)

Data Input

Out (V)'.

Out (IRE)'

XXXXXXXX
XXXXXXXX

-1.071
-0.785

-40
0

Sync Level
Blank Level

1
0

XXXXXXXX
XXXXXXXX

-0.071
0.0

100
110

Normal White Level
Enhanced White Level

1
0
1
0

11111111
11111111
00000000
00000000

-0.071
0.0
-0.7085
-0.6375

100
110
10
20

Normal White Level
Enhanced White Level
Normal Black Level
Enhanced Black Level

Bright

Description

~

C

:z:

Note.:
1. All Video Controls are active· Low (negative true) logic.
2. Sync and Blank output levels are dependent on set· up level selected. Values indicated are set·up 10 IRE set·up select
connected through a 1K Ohm resistor to VEE.
3. Sync level requires that both Sync and Blank = O.
4. 140 IRE
1.00 Volt.
5. All control values are subject to tolerance of ± 5% Gray Scale.
6. Analog output values shown are based on a step size of 2.SmV per LSB (used for ease of calibration). This causes the
Gray Scale output to be 637.SmV rather than 643mV in the idealized video output waveform. Both values
are within the tolerances of RS·343·A.

=

=

Table 2

Set·up Select

Set·up Control Input

Set·up Level

oVolts (GND)

o IRE
7.5 IRE
tOIRE
20 IRE

Not Connected
1K Ohm to - 5.2V (VEE)
- 5.2 Volts (VEE)

FIGURE 3

VIDEO OUTPUT WAVEFORM FOR STANDARD LOAD & 10 IRE SET·UP

.'JOY

Honeywell

3·141

II

8
o

FIGURE 4

EQUIVALENT INPUT CIRCUIT, DATA, CLOCK; & CONTROL

.....

0>

- - -......-

~J:

......- - - - - VCCD

ECL

IN

SOK

----'----+-------

FIGURE 5

VEE

DAC OUTPUT CIRCUIT

ANALOG
OUTPUT

---+--+---i~--I---+--VCCD

•••

3·142

Honeywell

FIGURE 6 STANDARD LOAD

HDAC97000

VIDEO DISPLAY

r-----...,I

I
I
I
I

r_...,r-fO~UT~P,UT~~L~~~)

I
I
I

OUTPUT
OT~ 1V I
VIDEO

I
I
I
I
I
I
I
IL _ _ _ _ _ ...JI

II

HDAC97000 AS A STANDARD D/A CONVERTER
The HDAC97000 is primarily designed to be used in
composite video applications, but with its inherent
speed, it can also be utilized in other applications requiring up to 200 MegaWords Per Second update rate.
When implemented as a standard DAC, some of the
video control inputs should be connected to ground
through a diode as indicated in Figure 7 (opposite
page). Composite Sync and Biank as well as
Reference White are connected in this manner (pin 16,
17 and 18). The set-up pin (21) is tied directly to ground
and the 10% Bright pin (19) is left open. If a-bits of
resolution are not necessary, the unused Inputs should
be tied to ground through a diode to prevent an output
offset voltage.

HDAC97000 IN A SINGLE + 5V TTL LOGIC SYSTEM
The HDAC97000 is primarily designed for ECL logic
systems which perform better in high-speed applications, but the DAC can be configured for TIL levels as
shown In Figure 8 (opposite page). It can be used In
systems that only have a + 5V power supply available
for the DAC. If any of the data inputs, Composite Blank
and Sync or Reference White are not used, they
should still be tied up to + 5V as shown. If the 10%
Bright is not used, it should be grounded or left open.
Also, note the different set-up conditions as well as the
pull-ups on the output.

Honeywell

3·143

o
o

FIGURE 7 STANDARD D/A CONVERTER

o
.....

0)

~
C
J:

L,

-(':'5rDUCTOR

- . - . ICL TlIllIHATJON

LI·=~:,:.)

FIGURE 8 TTL·COMPATIBLE HDAC97000

VIDEO DISPLAY

,..----,

I
I'- ____ ..1I

L'-(=.=::r

DCmOl

Lt-a:Ec:J

,j. ••-

"' .....
3·144

Honeywell

PIN ASSIGNMENTS

0
0
0

.....
0)

~
C

VCCO

::I:

SET·UP
OLAOJ

02

10%BRIOHT

03

COMP BLANK

04

COMP SYNC

05

REFWH

08

COMP

07

'SET

08

OUT

CLOCK

VCCA

PIN FUNCTIONS
NAME

FUNCTION

VCCD
VEE

Positive Digital Supply
Negative Supply Voltage
Data Input Bit 1 (MSB)
Data Input Bit 2
Data Input Bit 3
Data Input Bit 4
Data Input Bit 5
Data Input Bit 6
Data Input Bit 7
Data Input Bit 8 (LSB)
Conversion Clock Input
Analog Video Output
Reference Current Set
Decoupling Capacitor Connection
Reference White Input
Composite Video Sync Input
Composite Video Blank Input
+ 10% Bright Input
Glitch Adjust Connection
Video Set·Up Select
Positive Analog Supply

D1
D2
D3
D4

D5
D6
D7
D8

CLOCK
OUT
ISET
COMP
REFWH
COMPSYNC
COMP BLANK
10% BRIGHT
GLADJ
SET·UP
VCCA

* *For Ordering Information See Section 1.

Honeywell

3·145

NOTES:

3·146

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES
HIGH SPEED a-BIT VIDEO DAC WITH 512 X a MEMORY

HDAM51100

PRELIMINARY INFORMATION

FEATURES

APPLICATIONS

oLarge 512 X 8 Lookup Table
0125 MWPS Conversion Rate
oFully Parallel Bidirectional Data I/O
oDAC Output Rise/Fall Time <1 ns
oSingle Power Supply
oRS-343-A Compatible Video Levels

oHigh Resolution Color or Monochrome Displays
oCAT, PET, MR Imaging Displays
°CAD/CAE Workstations
oHigh-Speed D/A Conversion
oWaveform Generators
oAutomated Test Equipment
oECM

GENERAL DESCRIPTION
The HDAM51100 is a monolithic high performance a-bit
digital to analog converter that includes a 512 X a RAM
(color lookup palette), a precision bandgap reference,
registers, bus interface logic, parallel bidirectional data
I/O, and is capable of directly driving doubly-terminated
50 or 75 Ohm loads to RS-343-A video levels. The onchip memory allows 512 of the 16.7 million possible

colors to be simultaneously displayed in an RGB format.
The complete palette can be updated with a new set of
512 colors during the vertical retrace interval, even at 7090Hz refresh rates. The memory data is available on the
bidirectional data I/O port. Video controls are fully synchronous with the pixel data. SYNC and BRIGHT controls
are available as an option. The standard set-up level is
DIRE with 7.5 IRE available as an option.

BLOCK DIAGRAM

CONY
OUT +

BLANK
DAC
OUT-

ISET
AD-AS PIXEL ADDRESS

9

REF~N

REF-OUT
FEEDTHROUGH

RiW
Dl - D8 DATA VO

8

WRITE

COMPENSATION

READ

OEliE

Honeywell

3-147

8
.....
.....

10

~

:I:

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25°C
Supply Voltages
Positive Supply Voltage (VCC to VEE) ............+6.0 to -0.5V
Negative Supply Voltage (VEE to VCC) ..........-6.0 to +0.5V
Ground Voltage Differential (VCCA to VCCD).+0.5 to -0.5V
VEEA to VEED Differential..............................+O.5 to -0.5V
Input Voltages
Data. Controls (ECl. measured to VCCD) .....+0.5 to VEED

Output
Applied Voltage .................VEE-0.5V to VCC + 3.5V
Temperature
Temperature. ambient........................-60 to +1400C
junction .............................+1500C
lead Temperature (soldering 10 seconds) ..+3000C
Storage Temperature .........................-65 to +1500C

Notes:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications.

ELECTRICAL CHARACTERISTICS
COMMERCIAL TEMPERATURE RANGE
Fig. 1. VCCA. VCCD - o.OV. VEEA - VEED - -S.2± O.3V. TA = 2S·C. CC = OpF. ISET = 1.792mA. unless otherwise specified.
DC ELECTRICAL
CHARACTERISTICS

TEST
CONDITIONS

TEST
LEVEL

ROOM
+25·C
MIN TYPMAX

HOT
+70·C
MIN MAX

COLD
O·C
MIN MAX

UNITS

DAC CHARACTERISTICS
Resolution
Integral Linearity

1.2111M1SET
~1.8mA

1.2111M1SET
S1.8mA

Differential Linearity Tempco
Gain Error

8

I

-0.2 ±0.1 +0.2

0/0 Grey Scale

-112 ±1/4 +112

LSB

V

Integral Linearity Tempco
Differential Linearity

8

I

I

ppml"C
-0.2 ±0.1 +0.2

0/0 GreyScaIe

-112 ±1/4 +112

LSB

V
(Excluding
Reference)

I

Bits

ppm/°C
-5

+5

Gain Error Tempco

V

±150

Offset Current. Outputs. lOS

I

5

0/0 GreyScaIe

ppml"C
15

IJA

Full Scale Current. OUtputs. IFS

Adjusted for
Gain and Offset

I

28.56

mA

Blank Current. Out +

Adjusted for
Gain and Offset

I

0

mA

3·148

Honeywell

ELECTRICAL CHARACTERISTICS
COMMERCIAL TEMPERATURE RANGE
Fig. 1, VCCA = VCCO = O.OV, VEEA = VEEO = -S.2± O.3V, TA = 25°C, CC • OpF. ISET - 1.792mA, unless otherwise specified.

TEST
LEVEL

ROOM
+25°C
MIN TYPMAX

Adjusted for
Gain and Offset

I

28.56

ISETis
User Defined

IV

DC ELECTRICAL
CHARACTERISTICS

TEST
CONDmONS

HOT
+70°C
MIN MAX

COLD
O°C
MIN MAX

UNITS

DAC CHARACTERISTICS (Cont_)
Blank Current, Out Maximum Allowable Current,
Outputs
Compliance Voltage, Outputs

-1.5
20

RL=oo

I

Output Capacitance

CL=O

V

dlFS
dVEE

I

IREF =- 50j.iA

I

Power Supply Sensitivity

30

IV

Output Resistance

rnA
30

+1.5

rnA
V

Kn
10

pF
±120

JJAIV

1.29

V

REFERENCE CHARACTERISTICS
Bandgap Voltage
Bandgap Output Current, IREF
Bandgap Tempco
Common Mode Range
REF IN,ISET Pins

1.17

I

IREF=-101lA

V

VCCA=O
VEEA=-5.2

IV

50

j.iA

±100
-2.45

ppmfOC

-0.275

V

Input Capacitance
REF IN, ISET Pins

V

5

pF

Input Current, REF IN

V

3

j.iA

Input Current, ISET

IV

1.80

1.80

rnA

DIGITAL CONTROL CHARACTERISTICS
Input Voltage, Logic Low
Address, Controls, Data

MECL 1OK/1 OKH
Compatible

II

-1.95

-1.63 -1.95

-1.60 -1.95

-1.63 V

Input Voltage, Logic High
Address, Controls, Data

MECL 10K/10KH
Compatible

II

-0.98

-0.81 -0.92

-0.74 -1.02

-0.84 V

Honeywell

3-149

II

o
....o

....

'"

~

:t:

ELECTRICAL CHARACTERISTICS
COMMERCIAL TEMPERATURE RAN.GE
Fig. 1, VCCA .. VCCD .. O.OV, VEEA - VEED .. -5.2± O.3V, TA" 25·C, CC .. OpF. ISET" 1.792mA, unless otherwise specified.

DC ELECTRICAL
CHARACTERISTICS

TEST
CONDITIONS

TEST
LEVEL

ROOM
+25·C
MIN TYPMAX.

HOT
+70·C
MIN MAX

COLD
O·C
MIN MAX

UNITS.

DIGITAL CONTROL CHARACTERISTICS (Contd.)
Input Current, Logic Low
Address, Controls, Data

I

60

JJA

Input Current, Logie High
Address, Controls, Data

I

120

JJA

Input Resistance,
Address, Controls, Data

V

50

KQ

Input Capacitance,
Address, Controls

V

3

pF

Input Capacitance,
Data

V

5

pF

Differential Range,
CONVert, CONVert
Common Mode Range, VCCM
CONVert, CONVert
Input Current,
CONVert, CONVert

toVEED

MECL 101<11 OKH
Compatible

I

0.4

VCCD=O
VEED=-5.2

I

-2.45

V=VCCM

I

Input Capacitance,
CONVert, CONVert

1.2

V

-0.5

V

60

V

JJA
pF

3

Output Voltage, Logic Low
Data

-1.95

-1.63 -1.95

-1.60 -1.95

-1.63 V

Output Voltage, Logic High
Data

-0.98

-0.81 -0.92

-0.74 -1.02

-0.84 V

Output Current
Data

IV

11

11

11

mA

POWER SUPPLY CHARACTERISTICS
Supply Current, IEEA

I

56

60

mA

Supply Current,lEED

I

660

790

mA

Differential Voltage
VCCA to VCCD, VEEA to VEED

IV

-0.1

+0.1

V

.....

3-150

Honeywell

ELECTRICAL CHARACTERISTICS

o
o..-

COMMERCIAL TEMPERATURE RANGE
Fig. 1, VCCA-VCCD- O.OV, VEEA.VEED--S.2±0.3V, TA_25°C, CC-OpF. ISET_1.792mA, unlessolherwisespecified.

AC ELECTRICAL
CHARACTERlSllCS

TEST
CONDIllONS

TEST
LEVEL

ROOM
+25°C
MIN TYPMAX

HOT
+70°C
MIN MAX

COLD
DoC
MIN MAX

LO

~

::I:
UNITS

DAC CHARACTERISTICS (SEE TIMING DIAGRAMS A, D)

I

Maximum Update Rate, FS
Rise/Fall Times, Outputs
Rise/Fall Times, Outputs

10% to 90% G.S.
10% 10 90% G.S.
Rl-37.sn

Slew Rate, Outputs

125

MHz

I
IV
I

1

ns

1.5

ns

525

V/IlS
-

Settling Time, Clocked Mode,
Outputs, TSI

Full Scale Transilion 10 0.2%

Settling Time, Clocked Mode,
Outputs

Full Scale Transilion 10 0.8%

Settling Time, Clocked Mode,
Outputs

Full Scale Transllion 10 3.2%

3.0

ns

IV

2.2

ns

IV

1.6

ns

4.25

ns

Clock to Output Delay,
TDOC

I

3.25

Clock to Output Latency
Clocked Mode

I

2

2

cycles

Blank to Output latency
Clocked Mode

I

2

2

cycles

Address OUtput Delay,
Transparent Mode, TOOT

V

Feed Through,
Clock, Controls, Data

I

18.5

ns
-42

dB

Peak Glitch, VGl

1 lSB Transition
at midscale

V

2.8

mV

Glitch Energy (112 VGl & Time)

1 lSB Transition
at midscale

V

3

pV-s

REFERENCE CHARACTERISTICS

Amplifier Bandwidth, -3dB

Honeywell

3-151

g

J:LECTRICAL CHARACTERISTICS
COMMERCIAL TEMPERATURE RANGE
Fig. 1, VCCA. VCCD. O.OV, VEEA .. VEED. -S.2± O.3V, TA .. 25·C, cc. OpF. ISET. 1.792mA, unless otherwise specified.

AC ELECTRICAL
CHARACTERISTICS

TEST
CONDITlONS

TEST
LEVEL

ROOM
+25·C
MIN TYPMAX

HOT
+70·C
MIN MAX

COLD
O·C
MIN MAX

UNITS

DIGITAL CONTROL CHARACTERISTICS (See Timing Diagrams A, B, C)

Maximum Clock Cycle
CONVert, CONVert, 1/FS

I

8

ns

Pulse. Width, High
CONVert, CONVert, TPWH

2.5

ns

Pulse Width, Low
CONVert, CONVert, TPWL

2.5

ns

Set-upTime,
Address, Controls, TSAC

I

2.5

ns

Hold Time,
Address, Controls, THAC

I

1

ns

Set-up Time, Write,
Address Latched to R1W, TSCW

I

8

ns

Hold Time, Write,
Address Latched to R1W, THCW

1

ns

Pulse Width, Write,
R/W,TPWW

5.5

ns

Set-up Timel-Write,
WREN to R1W, TSEW

IV

0

ns

Hold Time, Write,
WREN to R1W, THEW

IV

0

ns

Set-up Time, Write,
Data to RIW Low, TSDW

2.5

ns

Hold Time, Write,
Data to R/WHigh, THDW

1

ns

Set-up Time, Write,
oEiiE Low to Data, TSID

IV

2.5

ns

Set-up Time, Read,
R1W, WREN High to Clock, TSR

IV

2.5

ns

Set-up Time, Read,
OElIE High to Clock, TSO

IV

2.5

ns

Data Delay, Read,
Clock to Data, TOO

IV

3-152

12

ns

Honeywell

ELECTRICAL CHARACTERISTICS TESTING

TEST LEVEL

All electrical characteristics are subjact to the following
conditions:
All parameters having Min.lMax. specifications are
guaranteed. The Test Level column indicates the specific
device testing actually performed during production and
Quality Assurance inspection. Any blank sections in the
data columns indicates that the specification is not tested
at the specified condition.
Unless otherwise noted, all tests performed after a 3 minute
power soak.

Honeywell

o

TEST PROCEDURE

......o
~
:::t

10

100% production tested at the
specified temperatures.

=

"

100% production tested at Ta
25°C, and sample tested at the
specified temperatures.

III

QA sample tested only at the
specified temperatures.

IV

Parameter is guaranteed (but not
tested) by design and characterizationdata.

V

Parameter is a typical value for
information purposes only.

II

3-153

8...

...

10

~

:t:

FUNCTIONAL DESCRIPTION
The HDAM51100 Is a 125 MWPS raster graphics subsystem that includes a 512 X S color lookup palette, S-bit
DAC, a precision bandgap reference, registers, bus interface logic and a parallel bidirectional data I/O port. Refer
to Timing Diagrams for system timing.

COLOR LOOKUP TABLE

prove performance and reduce the number of necessary
extemal components .

DAC
The DAC differential outputs provide R3-343-A compatible video levels for 1.1 rnAs;ISETs1.SmA and a load of
25 tq 37.5 Ohms. OUT- provides standard video levels
(blank down) and OUT+ provides inverse video (blank
up) with respect to VCCA.

Pixel color data is applied to the RAM address register
through the address lines AO-AS. This address is used to
"lookup" one of the possible 512 Intensities stored in the
RAM through the bidirectional data port, lines D1-DS.
The address register is latched on the rising edge of
CONVert (the falling edge of CONVert). The addressed
intensity data from the RAM is latched into the data
register on the next rising edge and latched into the DAC
register on the next rising clock edge, which applies it to
the DAC output. This results in the RAM data appearing
at the DAC output two clock cycles after it is latched into
the address register. If the Feedthrough (FT) control is
asserted, the address is applied to the RAM and the
intensity is applied to the DAC asynchronously with
respect to CONVert. In either case, reading data out of
the RAM requires that the Read/Write (RIW) or Write
Enable (WREN) pin be asserted high.

The HDAM51100 Is compatable with ECl logic when
powered by a -5.2V supply.

DATA 1/0

TYPICAL APPLICATION CIRCUIT

When the Output Enablellnput Enable (OEliE) pin, the
RfW pin and the WREN pin are asserted low, the S-bit
intensity word applied to the S-bit data I/O bus (D1 is the
MSB) is written into the RAM at the address latched into
address register from the address bus, pins AO-AS.

Figure 1 Illustrates a typical application circuit for a single
HDAM51100. This circuit shows how to terminate the
video DAC's output using either a 50 or a 75 Ohm load
and how to set the voltage reference. The internal bandgap reference or an external reference voltage can be
used.

When the oEliE pin and the RiW or WREN pin are
asserted high, the S-bit intensity word from the RAM at
the address latched into the address register appears on
the S-bit data I/O bus and is available to be read by
circuitry external to the chip. The data I/O bus can drive
ECl loads of 1200 to -2V.

VIDEP CONTROL
The BLANK control, when asserted high, forces the DAC
output to the blank (OIRE, black) level irrespective of the
digital word applied to the DAC (Refer to Figure 2). It has
the same latency as the lookup table data.

VOLTAGE REFERENCE
A precision bandgap voltage reference capable of driving
two additional HDAM51100's is included on chip to im-

3·154

OUT- is negative true logic; full scale output for ail zeros
from the RAM. OUT+ is positive true logic; full scale for all
ones from the RAM. Refer to Figure 2 for a description of
data and video controls.
Glitches are a major problem in high speed raster
graphics applications. The DAC in the HDAM51100 is
designed to minimize any differences in switching times
of the different bits. Registering the data prior to applying it to the DAC insures that all of the data bits arrive at
the same time further reducing the possibility of glitches.

LOGIC LEVELS

The output of the DAC is proportional to the reference
voltage divided by the sum of resistors R1 and R2. The
equation for the DAC full scale voltage is:
VOUT (F.S.) =

VREF

(15.9375) Rl where:

ex TRl +R2
VREF is the reference voltage

ex TR1 is the useable portion of R1
Rl is the total load on the output
OUT- is negative true logic; full scale output for all zeros
input. OUT+ is the opposite; full scale output for all ones
input.

Honeywell

In a multiple DAC application such as an RGB graphics
system, the color displayed is determined by the
combined intensities of the red, green and blue (RGB)
DAC outputs. A change in gain or an offset in any of the
RGB outputs will affect the apparent hue displayed on
the CRT screen. For this reason, it is important for the
outputs of all three DAC's to track each other over the
entire range of operating conditions. Since the DAC
output is portional to the reference current (ISET) and
the digital input code, using a single reference to drive all
three DACs will minimize any mismatch between them
even if the reference drifts.
Figure 3 illustrates a circuit that slaves all three DACs from
the reference of the "master" DAC. All of the DAC's have
a common reference adjustment. This is the simplest
reference arrangement and eliminates the need for
individual calibration of each DAC during production
assembly. The HDAM51100 contains an internal
prElcision bandgap reference which completely
eliminates the need for an external reference in most
applications. The reference output on a HDAM51100

can supply enough current to drive itself and two
additional HDAM511 OO's.
Figure 4 is a variation on Figure 3 in which one common
reference is used but each DAC has it's own individual
adjustment.

As with any high performance, high frequency device,
care must be taken when laying out the connecting
circuitry. All leads must be kept as short as possible.
Power supply decoupling must occur at the IC pins using
low inductance ceramic capacitors. Care must be taken to
isolate the analog and digital grounds. If the DAC output
or data and control lines are routed any appreciable
distance on the PC board, transmission line techniques
such as stripline or microstrip should be used. Place the
three parts near each other, as well as the reference
adjustment circuitry, on the board to minimize mismatch
due to thermal gradients.

1/FS

CONY

THAC

AO -AS

~mAC
-------'f!, ~-----TSAC

BLANK

~~TDOC

~X==XX)
DATA
DATA
BLANK
DATA

DAC
OUTPUTS

(ADDO)

(ADD1)

(ADD3)

INPUTS - DON'T CARE
OUTPUTS - UNDEFINED

TIMING DIAGRAM A • DAC READ

Honeywell

~J:

If it is desire able to use an external reference, the
HDAM51100 can easily accomodate this as shown in
Figure 5.

TIMING DIAGRAMS

TSAC~

o

....o....
10

3-155

II

0

0
,..
,..
10

CONV

0
:J:

BLANK

:E
c(

~
TSAC

I

I

~ ~

:

~~~H~C

rro~

AD-A8

ADDD

ADD1

I
I
I

ADD2

I

TSCW

RiW
WREN

,

•
•,

,

,

TS~'-I-t__i;.-.--_--L.-_

01 - 08

TSO~ ~-1

tt

THOW

'f/J--~

(IN)
DATA
(ADD1)

:

DATA
(ADD2)

OE/ie

DAC
OUTPUTS
BLANK
NOTE: MULTIPLE CONVERT PULSES ARE ALLOWABLE
DURING WRITE CYCLES IF ADDRESS AND DATA ARE
UNCHANGED.

~
~

INPUTS - DON'T CARE
OUTPUTS - UNDEFINED

TIMING DIAGRAM B - RAM WRITE

3·156

Honeywell

0
0

......
It)

CONY

~

c(

C
::I:
AD·AS
AD,D1

ADD2

ADD3

ADD4

,
I

RiW and/or
WREN

oEliE
01·08
(OUT)

jr=TSR

I
I

jr=

I

TSO!

:~----x
~
: DATA
I ADDD

DAC
OUTPUTS

DATA
: ADD1
I

: 1t
1t

~W&
I
I

TSAC

BLANK

E1

C
DATA
ADD2

DATA
ADD3

TDOC

X

DATA
ADDD

BLANK

TIMING DIAGRAM C - RAM READ

CONY

±112 LSB
DAC
OUTPUTS

±112 LSB

~

TOOT

AO.A8~~TIMING DIAGRAM D - DAC

INPUTS • DONT CARE
OUTPUTS • UNDEFINED

Honeywell

3·157

0
0

........

I()

~

~

VIDEO MONrrOR
,

J:

RS343A LEVELS

I

~-F=---,-~~~~I- :

BLANK

I

4_ _ _ _ _ _ _ _ ,
AO-AB
PIXEL ADDRESS

-+--ISET
H2. ?SOQ

FEEDntROUGH
R1

D1 .. 08 DATA 110

(01 • MSB)

COMPENSATION

TO

OUTPUT ENABLE

PAC TEST LQAg

NOTES:
1. ISET.

VREf

( WHERE ( aT) R1 IS)
THE EFFECTIVE

( aT) R1 + R2

PORTION OF R1

2. RL.R311A4

:;:~Pr.\\

}
-

118W 1% METAL FILM

0.1.,

184

.

3. AU REFERENCE RESISTORS

\0

VEEA

DATA

312

4. POWER SUPPLY DECOUPLlNQ

SOY CERAMIC

VEED

FIGURE 1: TYPICAL APPLICATIONS CIRCUIT
OUT-

OUT+

~

!B&.

100

o

o

100

OUTBLANK

RAM DATA
X

OUT+

(mA)

(V)

(IRE)

(mA)

(V)

(IRE)

BLANK

19.04

-0.714

0

0

0

0

DESCRIPTION

0

000...

BLACK

19.04

-0.714

0

0

0

0

0

111 ...

WHITE

0

0

100

19.04

-0.714

100

Note: ISET = 1.792 rnA, RL= 250, Adjusted For Gain and Offset

FIGURE 2: VIDEO OUTPUT WAVEFORM FOR STANDARD LOAD

3-158

Honeywell

HDAM51100 #1

MASTER DAC

t

ISET

3(IS~

R2

2500

(ISET)

2000

=

10T POT

R1

I

1.2V
3(--_-+-_~_~

VEEA

"
"
"
"
"
- - 11___ I, _ _ _ _ _ _ _ _ I
"

,
'VEEA

COMP

FIGURE 8: EQUIVALENT CIRCUITS - DAC AND REFERENCE AMPLIFIER

Honeywell

3-161

o

o
....
....

It)

~

J:

COLUMN

ROW

PIN NAME

COLUMN

ROW

PIN NAME

A
A
A
A
A
A
A
A
A

1

VCCD

E
E
E

2
8

A3
VEED
VEEA

F
F
F
F

1
2
8

9

G
G
G
G

8
9

2

VEED
D8(LSB)

3
4

5

D8
OS

6
7
8

D4

03

9

Dl(MSB)

B
B
B
B

1
2
8
9

VCCD

C
C
C
C

8
9

VEED

D2
VCCD
IVJ
VCCD

1

2

D
D
D

1

A2
Al

9

E

1

A4

AS

A7
VEED
VCCA
OUT+

1

1

AS

2
8

CONY
COMP
·VCCA

9

J
J
J
J
J
J
J
J
J

AiW - DATA REAOI
WRITE SELECT
WREN-DATA WRITE
ENABLE

8

AS
OUT·VCCA

2

H
H
H
H

VCCD
OEiiE - DATA INPUTI
OUTPUT SELECT

2

D

9

D7

2

VEED
CONY

3

FT

4

VCCO
BLANK
·VCCA
REFOUT
REFIN
ISET

1

5
6
7
8
9

HDAM51100 PACKAGING INFORMATION
46 PIN GRID ARRAY
9

8

7

6

5

4

3

PIN 1IDENT_

2

0 0 0 0 0 0 0 0
01
03
04
05
06
07
OS VEEO VCCO
LSB
0 0
0 0
VCCO 02
VEEO VCCO
---------0_ 0
0 0

OElIE VCCO

I
I

VCCO

0

'?m

--

·NO INTERNAl CONNECTION - CONNECT TO
VCCA FOR INTERELECTRODE SHIELDING

C
D

A1

I

NOTES:

B

AO

0
A2
0 0
0 0
VEEA VEEO
A3
A4
0 0
0 0
·VCCA OUTA6
A5
.... -- ...... _.........
0 0
0 0
OUT+·VCCA
VEEO A7
0 0
0 0
·VCCA COMP
·VCCA BLANK
CONV AS
0 0 0 0 0 0 0 0 0
ISET REFIN REFOUT
VCCO FT roFroVEEO
£EN

A

E
F

G

H
J

Bottom View

* *For Ordering Information See Section 1.
3-162

Honeywell

SELECTION GUIDE, CROSS REFERENCE
ORDERING INFORMATION

ANALOG TO DIGITAL CONVERTERS

DIGITAL TO ANALOG CONVERTERS

P

INSTRUMENTATION AMPLIFIERS

I

a

SPECIAL FUNCTIONS

!

Honeywell

EVALUATION BOARDS

I

APPLICATIONS INFORMATION

1:1

QUALITY ASSURANCE

El

PACKAGE OUTLINES

1[':

SALES OFFICES AND
REPRESENTATIVES

III
4-1

4-2

.Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HCMP96850

SINGLE ULTRA FAST VOLTAGE COMPARATOR

APPLICATIONS

FEATURES
•
•
•
•
•
•

Propagation Delay < 2.5ns
Propagation Delay Skew < 300ps
100MHz Minimum Tracking Bandwidth
Low Offset ± 1mV
Low Feedthrough
Latch Control

The HCMP96850 is a single. very high speed,
monolithic comparator. It is pin-compatible with. and
has improved performance over Plessey's SP9685
and AMD's AM6685. The HCMP96850 is designed for
use in Automatic Test Equipment (ATE). high speed instrumentation. and other high speed comparator applications.

•
•
•
•
•
•

High Speed Instrumentation, ATE
High Speed Timing
Window Comparators
Line Receivers
NO Conversion
Threshold Detection

Improvements over other sources include reduced
power consumption. reduced propagation delays, and
higher input impedance.
The HCMP96850 is available in 16 Lead DIP, or in die
form.

BLOCK DIAGRAM

HCMP96850 HIGH SPEED COMPARATOR

6

Honeywell

LATCH ENABLE

4-3

II

oIt)
co
co

0)

Do

::E

o

J:

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25°C
Supply Voltage.
PositiveSupplyVoltage (Vee measured to GND) , ' ..... .
............................. -0.5to +6.0V
Negative Supply Voltage (Vedo GND) ... - 6.0 to + 0.5V
Ground Voltage Differential ........... -0.5 to + O.SV

Output
Output Current ............................ 30mA
Temperature
OperatingTemperature,amb.ient ..... -55to + 125°q
junctiOn ............ + 150°C
Lead Temperature, (soldering 60 seconds) .... + 300°C
Storage Temperature .............. -65to + 150·C

Input Voltages
Input Voltage ...................... - 4.0 to + 4.0V
Differential Input Voltage ............. - 5.0 to + 5.0V
Input Voltage, Latch Controls .............. Vee to 0.5V
Notes:
1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied condltlqns In
typical applications.

TEST
CONDITIONS

PARAMETER

MIN

TYP

MAX

UNITS

DC ELECTRICAL CHARACTERISTICS

= - 5.2V ±
= o Ohms
= o Ohms,

TA = 25°C, VCC = + 5.0V ± .25V, VEE
VOS

Input Offset Voltage

RS

VOS

Input Offset Voltage

RS
TMIN 

RS

QOUTPUT

000
RS

500

aOUTPUT
QND!

RT

RT

1000

RL

RT

RT
(IOn)

VL

T

-

.1"'

LATCH ENABLE

*
-_ICf----- • ECl TERMINATION.

4·8

Honeywell

The timing diagram for the comparator is shown in
Figure 2. The latch enable (LE) pulse is shown at the
top. If LE is high In the HCMP96850, the comparator
tracks the input difference voltage. When LE is driven
low the comparator outputs are latched into their existing logic states.

enable falling edge and held for time tH after the falling
edge for the comparator to accept data. After tH, the
output ignores the input status until the latch is strobed
again. A minimum latch pulse width of tpL is needed for
strobe operation, and the output transitions occur
after a time of tPLOH or tpLOL.

The leading edge of the input signal (which consists of
10mV overdrive) changes the comparator output after
a time of tpdL or tpdH (0 or 0). The input signal must be
maintained for a time ts (set-up time) before the latch

Unused outputs must be terminated with 50 Ohms to
ground while unused latch enable pins should be connected directly to ground.

FIGURE 2

o

10

CO
CO

m
D..
:E
o
:r:

TIMING DIAGRAM
COMPARE

D

- - - - - - - - - - - - - - - - - Vos

J

'

'''0.

·-----------1~-----~-----____f_-----~-----,j
,

'".

.'

'.

',LOL

.-----------i------~------i------~---------VIN = 100mV, VOD

= 10mV

The set·up and hold time. are a measure 01 the time required lor an Input signal to propagate through the IIrst
.tage ot the comparator to reach the latching circuitry. Input Signal changes occurring betore ts will be
detected and held; those occurring alter th will not be detected. Changes between ts and th mayor may not
be detectad.

SWITCHING TERMS (refer to Figure 2)
tpdH

INPUT TO OUTPUT HIGH DELAY - The propagation
delay measured Irom the time the Input signal
crosses the Input ollset voltage to the 50 % point 01
an output LOW to HIGH transition.

MINIMUM HOLD TIME - The minimum time alter the
negative transition 01 the Latch Enable signal that the
Input signal must remain unchanged In order to be
acquired and held at the outputs.

INPUT TO OUTPUT LOW DELAY· The propagation
delay measured Irom the time the input signal
crosses the Input ollset voltage to the 50% point 01
an output HIGH to LOW transition.

MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire and hold an Input signal
change.

LATCH ENABLE TO OUTPUT HtGH DELAY - The pro·
pagation delay measured Irom the 50% point 01 the
Latch Enable signal LOW to HIGH transition to the
50% point 01 an output LOW to HIGH transition.

DIFFERENTIAL PROPAGATION DELAY (SKEW) INPUT TO OUTPUT· The delay or skew between comparators.

LATCH ENABLE TO OUTPUT LOW DELAY· The pro·
pagation delay measured from the 50% point 01 the
Latch Enable signal LOW to HIGH transition to the
50% point 01 an output HIGH to LOW transition.

ts

tpLOL·tpLOH DIFFERENTIAL PROPAGATION DELAY (SKEW)
LATCH TO OUTPUT· The skew from one comparator
to another.
VOD

VOLTAGE OVERDRIVE.

MINIMUM SET·UP TIME· The minimum time belore
the negative tranSition 01 the Latch Enable signal that
an Input signal change must be present In order to be
acquired and held at the outputs.

Honeywell

4-9

FIGURE 3

EQUIVALENT INPUT CIRCUIT

eN
1p'

"N

VN o---~~4---+-~

"'n

~ o---~~N-~-------+------~----+-~
..,n
v.. o----------------+------+-----~--,
V"

o--------------f-:!----+:!----I

Vo

o-------------~-----+-----~----~~~

(-uV)

FIGURE 4

v....

FIGURE 5A

OUTPUT CIRCUIT

0

TEST LOAD

RZ
III'

,~!

&on

VpO
(-4.oY)

INPUT1

FIGURE 58

INI'UU

AC TEST FIXTURE

,......
Voc

,.-------.,
I

I

~~-----~~~~~~~.
I

~~----~-+-~~~~~~­
I
I
I

T,·lIJF

I
I

"n

i~HO
IL.. ______ _

NOTES: 1. ALL INC. SIMI RIGID COAX SHIELD ARE GROUNDED.
2. ALLAEstlroR81%(IOg • ..,..0),

a

e.

KEEP ALL LEADS AS SHOfIT AS PO$Sl8LE WITH ELEC-

TRtCAL LENGTHS L1 • L2 + LI.
O.U.T. pwas INTO A l ' PIN HtoM FREQUENCY PIN

SOCKET.

&. MONITOR INPUT IMPEDANCE 100 TO GND.
I. 8E.' RIOlO COAX SHIELD SHOULD IE CONNECTED AS

CLOSE TO THE DEVICE AS POS1H8LE.

4-10

HoneyWell

FIGURE 6

HCMP96850 WITH HYSTERESIS

o

10

c:o
co
0)
a..

,,,riI

~

o

~
v,. ",.---.::o~-+-l

J:

",

OOUTPI)T

",
QOUTI'UT
D
'--_-t-••...:.
.--,

"L

,oon
VL

T""

D

HYSTERESIS IS OBTAINED BY APPLYING
A DC BIAS TO THE LE PIN

VH

= -S.2V
= -1.3V:l:l00mV

VLE

PIN ASSIGNMENTS

TOP VIEW

PIN FUNCTIONS

NAME

FUNCTION

GNDl

Circuit Ground
Positive Supply Voltage
Non-Inverting Input
Inverting Input
No Connection
Latch Enable
Negative Supply Voltage
Output
Inverted Output
Output Ground

vee

+IN
-IN
N/C

LE
VEE
QOUT
QOUT

GND2

18 LEAD CERDIP

* *For Ordering Information See Section 1.

Honeywell

4-11

NOTES:

4·12

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HCMP96870A

DUAL ULTRA FAST VOLTAGE COMPARATOR

APPLICATIONS

FEATURES
•
•
•
•
•
•

Propagation Delay < 2.3ns
Propagation Delay Skew < 300ps
300MHz Minimum Tracking Bandwidth
Low Offset ± 1mV
Low Feedthrough and Crosstalk
Differential Latch Control - Dual Version

The HCMP96870A is a dual, very high speed
monolithic comparators. It Is pin-compatible with, and
has Improved performance over Plessey's SP9687
and AMO's AM6687. The HCMP96870 is designed for
use In Automatic Test Equipment (ATE), high speed in·
strumentation, and other high speed comparator ap·
pllcations.

•
•
•
•
•
•

High Speed Instrumentation, ATE
High Speed Timing
Window Comparators
Line Receivers
AlD Conversion
Threshold Detection

Improvements over other sources include reduced
power consumption, reduced propagation delays, and
higher input impedance.
The HCMP96870A is available in 16 Lead CEROIP, 20
Contact Leadless Chip Carriers (LCC), or In die form.

BLOCK DIAGRAM
HCMP98870 DUAL HIGH SPEED COMPARATOR

INVERTING
INPUT

LATCH ENABLE

aOUTPUT

LATCH ENABLE

a OUTPUT

-s.2Y
+sv

QOUTPUT

LATCH ENABLE
INVERTING
INPUT

Honeywell

4·13

a

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 25°C
Supply Voltage.
Positive Supply Voltage (Vee measured to GND) ....... .
............................. -0.5to +6.0V
NegativeSupplyVoltage(VeetoGND) ... -6.0to +0.5V
Ground Voltage Differential ........... - 0.5 to + 0.5V

Output
Output Current ............................ 30mA
Temperature
Operating Temperature, ambient ..... - 55 to
junction ............
Lead Temperature, (soldering 60 seconds) ....
Storage Temperature .............. - 65 to

Input Voltage.
Input Voltage ...................... - 4.0 to + 4.0V
Differential Input Voltage ............. - 5.0 to + 5.0V
Input Voltage, Latch Controls .............. Vee to 0.5V
Not••:

+ 125°C
+ 150°C
+ 300°C
+ 150°C

1. Operation at any Absolute Maximum Rating Is not Implied. See Electrical Specifications for proper nominal applied conditions In
typical applications.

TEST
CONDITIONS

PARAMETER

MIN

DC ELECTRICAL CHARACTERISTICS
TA

= 25°C, VCC = + 5.0V ±

.25V, VEE

= - 5.2V ±

.3V, RL

-3

+3

RS = 0 Ohms,
TMIN < TA <
TMAX2

IV

-3.5

+3.5

RS =

VOS

Input Offset Voltage

D.VOSID.T Offset Voltage Tempco

IBIAS

Input Bias Current

lOS

Input Offset Current

lOS

Input Offset Current

TMIN < TA
TMAX2

TMIN < TA
TMAX2

<

UNITS

= 50 Ohms (Unless otherwise specified)

o Ohms

VOS

Input Bias Current

MAX

I

Input Offset Voltage

IBIAS

TYP

V

4

I

4

IV

7

mV

mV
p.VloC

±20

pA

p.A

I

-1.0

+ 1.0

p.A

IV

-1.3

+ 1.3

p.A

<

ICC

Positive Supply Current

I

3.3

5

rnA

lEE

Negative Supply Current

I

13.5

18

mA

VCM

Common Mode Range

I

+2.5

V

AVOL

Open Loop Gain

V

4000

VN

RIN

Input Resistance

V

60

KOhms

CIN

Input Capacitance

V

3

pF

CIN

Input Capacitance

V

1

pF

PSS

Power Supply Sensitivity

I

70

dB

CMRR

Common Mode Rejection
Ratio

I

80

dB

Power Dissipation

I

Po

(LCC Package)

Dual

-2.5

250

mW

OUTPUT lOGIC lEVELS (ECl 10KH Compatible)
VOH

Output High

50 Ohms to - 2V

I

-.98

-.81

V

VOL

Output Low

50 Ohms to - 2V

I

-1.95

-1.63

V

4·14

Honeywell

«

INDUSTRIAL TEMPERATURE RANGE
TEST
CONDITIONS

PARAMETER

AC ELECTRICAL CHARACTERISTICS
TA25 ·C, VCC

= + 5.0V ±

.25V, VEE

tp

Propagation Delay

ts

Latch Set-up Time

tp(E)

Latch to Output Delay

tpW(E)

Latch Pulse Width

tH(E)

Latch Hold Time

tr

Rise Time

tf

Fall Time

fc

Min Clock Rate

= - 5.2V ±

.3V, RL

MIN

,...o
TYP

MAX

UNITS

I

2.0

2.3

o

::I:

ns

0.6

ns

3

ns

2

ns

0.5

ns

20% to 80%

1.2

ns

20% to 80%

1.2

ns

300

MHz

50mVO.D.

Notes:
1. 100mV Input step.

D

2. Temperature Range - 25 to + 85·C

MILITARY TEMPERATURE RANGE
PARAMETER

TEST
CONDITIONS

MIN

TYP

MAX

UNITS

DC ELECTRICAL CHARACTERISTICS
TA = 25·C, VCC = + 5.0V ± .25V, VEE = - 5.2V ± .3V, RL = 50 Ohms (Unless otherwise specified)
VOS

Input Offset Voltage

VOS

Input Offset Voltage

RS = 0 Ohms

I

-3

+3

mV

I

-4

+4

mV

RS = 0 Ohms,
TMIN
~r1'

QOUTPUT

A

..0

".

"0

QOUTPUT
GND,

"T

1DOO

"L

VL

LATCH ENAILE

"s

T

.1"'

"r

(500)

"-

LATCH ENABLE

*

- _ M f - - - • Eel TERMINATION.

4·18

HoneyWell

The timing diagram for the comparator Is shown In
Figure 2. The latch enable (LE) pulse Is shown at the
top. If LE Is high and LE low in the HCMP96870A, the
comparator tracks the input difference voltage. When
LE Is driven low and LE high the comparator outputs
are latched Into their existing logic states.

enable failing edge and LE rising edge and held for
time tH after the failing edge for the comparator to ac·
cept data. After tH, the output Ignores the Input status
until the latch Is strobed again. A minimum latch pulse
width of tpL Is needed for strobe operation, and the out·
put transitions occur after a time of tpLOll or tpLOl.

The leading edge of the input signal (whiCh consists of
10mV overdrive) changes the comparator output after
a time of tpdL or tpdH (0 or 0). The input signal must be
maintained for a time ts (set-up time) before the latch

Unused outputs must be terminated with 50 Ohms to
ground while unused latch enable pins should be con·
nected directly to ground.

FIGURE 2

TIMING DIAGRAM
COMPARE

- - -_ _ _ _ _ _ _ _ _ _ ..

5G~

D

- - - - - - - - - - - - - - - - - . Yo.

VIN

= 100mV,

VOD = 10mV

The .el·up Ind hold tim.. Ire I measure ollhl time required lor an Input .Ignilio propagate through thl first
.tage ollhe comparltor to reich Ihi Illchlng circuitry. Inpul .Ignal chlnge. occun1ng before t. will be
deteoted and hlld; lhose occun1n~fler Ih will not be delected. Change. betw"n I. and th mayor may nol
be delected. (LE I. the Inverse 01 LE~

SWITCHING TERMS (refer to Figure 2)
tpdH

INPUT TO OUTPUT HIGH DELAY - The propagallon
delay measured from the time the Input signal
crosses the Input ollset voltage to the 50% point of
an outpUI LOW to HIGH transition.

MINIMUM HOLD TIME - The minimum time aller Ihe
negativetransilion 01 the Latch Enable signal that the
Input Signal must remain unchanged In order to be
acquired and held at the outputs.

INPUT TO OUTPUT LOW DELAY - The propagation
delay measured from the time the Input signal
crosses the Input ollset voltage to the 50% point 01
an outpul HIGH 10 LOW transition.

MINIMUM LATCH ENABLE PULSE WIDTH - The
minimum time that the Latch Enable signal must be
HIGH in order to acquire and hold an input signal
change.

LATCH ENABLE TO OUTPUT HIGH DELAY - The propagation dalay measured Irom the 50% potnt 01 the
Latch Enable signal LOW to HIGH transition to the
50% point of an output LOW to HIGH transition.

DIFFERENTIAL PROPAGATION DELAY (SKEW) INPUT TO OUTPUT - The delay or skew between c0mparators.

LATCH ENABLE TO OUTPUT LOW DELAY - The propagation dalay measured lrom the 50% potnt 01 the
Latch Enable signal LOW to HIGH transition to the
50% point 01 an output HIGH to LOW transition.

ts

VOD

VOLTAGE OVERDRIVE.

MINIMUM SET-UP TtME - The minimum time belore
the negative Iransltlon 01 the Latch Enable Signal that
an Input signal change must be present In ordar to be
acquired and held at the outputs.

···Honeywell
• t

tpLOL-tpLOH DIFFERENTIAL PROPAGATION DELAY (SKEW)
LATCH TO OUTPUT -The akew lrom one comparator
to another.

.

4·19

· FIGURE 3

EQUIVALENT INPUT CIRCUIT

.... O---~-"""-_"""_""""--_--9-'--'

~+IYI

.....

..

•• D--"""'"-+-~-l
....

....

~-+--<)Y

".

\o--~*~.~----r---r---+_~
.qo--------r---l---+_~
·~o-------_4~-_+~-4

I_::D-------......- -......--J----~...J
FIGURE 4

.

FIGURE 5A

OUTPUT CIRCUIT

TEST LOAD

liz

GOU11'U'

QOUTPUT

INPUT!

FIGURE 58

."'UTI

AC TEST FIXTURE

..'"...,
~-------

I

.

~-----~~~~!~+

""
I
~~--~_~~~v~-

,,
,

..

,, ,
I
, '-------"!oF

tM

'AHT.

-'fi -

4-20

MOTU: 1. AU. 8JIC i .... RIGID COAX 1M. . MI GROUNDiD.
L ALL ....I1OU'... (IOll. 41.10).
I. _ . AlL UADI AlIHCNIT _ POUIILI WfTH ILECo
1tICM. LDIQ1'H8 L' II! U of La.
.. D.U.t. PLUQ8 INTO •
PIfI HIGH I'tIIQU!ItCy Nt

t.

IOCIIIT•
.. ~"UT"NDrMCSIOO: TOOl.
L . . . NCIID COAX IHlI\D IMOULD HCONNiCTID,.
CLDllTO TMI DIVICI! UPOIIIIL£

Honeywell

FIGURE 6

HCMP96870A WITH HYSTERESIS

,,,riI
f
"s

"s

Y", <>-!--t-------+..q

UND,

"r

..n

QOUTPUT

'----t--'---,

"r

"L

".n

"r

,.."r'"

T"'"

II,'

HYSTERESIS IS OBTAINED BY APPLYING
A DC BIAS TO THE LE PIN
VH

= -S.2V

"

VLE .. -1.3V :t:100mV. Vii" -1.3V

PIN ASSIGNMENTS

PIN FUNCTIONS

TOP VIEW

°A

'

GND A

l

'4

GND.

LEA'
LEA

•

-INA'

18 LEAD DIP
TOP VIEW

.de

OC

~

0"'10·

NAME

FUNCTION

OA
OA
GNDA
LEA
LEA
VEE
-INA
+INA
+INB
-INB

Output A
Inverted Output A
Ground A
Latch Enable A
Inverted Latch Enable A
Negative Supply Voltage
Inverting Input A
Non-Inverting Input A
Non-Inverting Input B
Inverting Input B
Positive Supply Voltage
Inverted Latch Enable B
Latch Enable B
Ground B
Inverted Output B
Output B

vec

LEB
LEB
GNDB
OB
OB

20 LEAD CERAMIC LCC

* *For Ordering Information See Section 1.

Honeywell

4-21

NOTES:

4·22

. Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES
DUAL HIGH SPEED, WIDE VOLTAGE RANGE COMPARATOR

HCMP96900

PRELIMINARY INFORMATION
FEATURES:

APPLICATIONS:

• Wide Input Range -STo +13V
• Input Protected to 1V Above Supplies
• Constant Propagation Delays
• High Speed - 4.2ns Propagation Delay
• Constant Input Current

• ATE Pin Receivers
• Timing Ramp Generators
• Line Receivers
• High Speed Window Detectors

GENERAL DESCRIPTION
The HCMP96900 is a dual, high speed, wide common
mode voltage comparator. It is designed for applications
measuring critical timing parameters where wide common
mode input voltages are required. Propagation delays
are constant for varying input slew rates, common mode
voltage, overdrive or polarity. Input protection is provided
to one volt in excess of the power supplies to ease
design of input protection circuitry.

For many applications, the comparator allows the
designer to input signals directly into the comparator
without the need for either very high speed voltage
dividers or buffers. Therefore, designs are easy to
protect, high in reliability, and lower in power and space
than previous high speed comparators. The device is
available in an 1S-pin ceramic sidebrazed dip, 20 lead
LCC or in die form.

BLOCK DIAGRAM

.VIN1

V01

·VIN1

Y01

VCC1

VEE
VCC2

.VIN2

V02

·VIN2

Y02

Honeywell

4-23

D
:;

i:.•.

o
o
m
co
m
a..
:E

o

J:

ABSOLUTE MAXIMUM RATINGS 25°C (1)
Differential Supply Voltage ................................24V
Input Voltage Range ..........VEE -1.0Vto VCC +1.0V
Power Dissipation ....................................... 800mW
Differential Input Voltage ..............................±24.0V
Output Current... ...........................................40mA
(1) Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied conditions in
typical applications.
Operating Temperature Range ............. -2S to +8SoC
Positive Supply Voltage ..............................+18.0V
Negative Supply Voltage ..............................-13.0V

ELECTRICAL SPECIFICATIONS
Industrial Temperature Range
Vee =+12.0V Vee = -7.0V unless otherwise specified.
DC Electrical
Characteristics

Test
Conditions

Input Offset Voltage

Test
Level (1)

Hot +85°C
Room +25°C
Min Typ Max Min Typ Max
-3.0 ±O.S +3.0

t"VOSlt"T

20

Input Offset Current

VIN = O.OV
VIN = O.OV

8

1.0
20

t"IBIASIt"VIN

-2V 
CO
0>
Q.

'------------50%
tpLOL

\"-----------50%
~----------_r----..J

VIN =100mV, VOD = 10mV

The set-up and hold limes are a measure of the time required for an input signal to propagate through the first stage of the
comparator to reach the latching circuitry, input signals occurini£.efore ts will be detected and held; those occuring after th will not
be detected. Changes between ts and th may not be detected (LE is the inverse of LE).

SWITCHING TERMS
tpdH -INPUTTO OUTPUT HIGH DELAY
The propagation delay measured from the time the
imput signal crossed the input offset voltage to the 50%
point of an output LOW to HIGH transistion.
tpdL -INPUTTO OUTPUT LOW DELAY
The propagation delay measured from the time the imput
signal crosses the tmput offset voltage to the 50% point
of an output HIGH to LOW transistion.
tpLOH - LATCH ENABLE TO OUTPUT HIGH DELAY
The propagation delay measured from the 59% point of
the Latch Enable signal Low to HIGH trans~ion to 50%
point of an output LOW to HIGH transistion.
tpLOL -LATCH ENABLE TO OUTPUT LOW DELAY
The propagation delay measured from the 50% point of
the Latch Enable signal LOW to HIGH transition to the
50% point of an output HIGH to LOW trans~ion.
Is - MIMINUN SET-UPTIME
The minimum time before the negative transistion of the
Latch Enable signal that an input signal change must be
present in order to be acquired and held at the outputs.

Honeywell

th -MINIMUM HOLD TIME
The minimum time after the negative trans~ion of the
Latch Enable signal that the input signal must remain
unchanged in order to be acquired and ~eld at the
outputs.
tpL - MINIMUM LATCH ENABLE PULSE WIDTH
The minimum time that the Latch Enable signal must be
HIGH in orderto acquire and hold an imput signal
change.
tpdL -tpdH - DIFFERENTIAL PROPAGATION DELAY
(SKEW) INPUTTO OUTPUT
The delay or skew between comparators.
tpLOL- tpLOH - DIFFERENTIAL PROPAGATION
DELAY (SKEW) LATCH TO OUTPUT The skew from
one comparator to another
VOD- VOLTAGE OVERDRIVE

4-27

D

o
o0)

FIGURE 2. HCMP96900 SUPPLY VOLTAGES INPUT VOLTAGE RANGE
15

8a.
:::e

oJ:

10
~OOO.O.OO • • • OO • • OO.O.O.OOOOOO.OOOOOOO.D

t

w
CJ
C

...0

Common Mode Input
Range (Minimum Suppllee)

S

l-

>

+

...>-

• • • • • D.O. 00 D • • 000 000 • • 000 • • • • • • • • • • • •

II.
II.

Common Mode
Input Range
(Maximum Supplies)

OO.~:lIf----'--

0

~

II)

-3.3

.a

-10

-15

FIGURE 3. HCMP96900 VIN VERSUS IB (Common Mode)

9.0

/
/
/

V
./

1{
!i!!

1 00 dB (G=1000)
Low Input Voltage Drift: 2.0 J!VFC
Low Noise: 9 nV/vHz (@1 kHz, G=1000)
Single Resistor Gain Programmable 1--+-''---<>OUTPUT

0=100

G=1D
RG2

20Kn

20Kn

>-+--'l/ll'v---t>--'I/IIIr---I-"~REFERENCE

+INPUT

Honeywell

5-5

SPECIFICATIONS

PARAMETER

TEST
CONDITIONS

HlNA524A

HINA524B

HlNA524C

MIN TYPMAX

MIN TYPMAX

MIN TYPMAX

UNITS

Vs =±15 V, RL = 2 Kil, OverTemperature Range Specified Below,
Unless Otherwise Indicated

ELECTRICAL CHARACTERISTICS
Gain Error

TEST
LEVEL

G=1
TA =25°C

I

±.O2

±.O3

±.O5 %

'.

Gain Temperature Coefficient

G=1

I

±5

±5

Nonlinearity

G=1

I

±.OO3

±.003

TA=25°C

I

±25

±75

I

±.50

±.75

TA=25°C

I

±15

±25

G= 1000

I

120

120

110

dB

G=1

I

±10

±10

±10

Volts

G=1000

I

Input Offset Voltage
Input Offset Voltage Temp. Co.
Input Bias Current
Common Mode Rejection
Unear Differential Input Voltage
Range
Unear Common Mode Input
Voltage Range
Output Voltage

I

±12
±10

±5 ppml"C

±.005 %
±200 j.lV
±2 j.lVrC
±50 nA

±12
±10

TEST LEVEL

±12 Volts
±10

Volts

TEST PROCEDURE
Production tested at the
specified conditions.

•

* *For Ordering Information See Section 1.
5·6

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HINA624

PRECISION INSTRUMENTATION AMPLIFIER
ADVANCE INFORMATION

FEATURES:

APPLICATIONS:

•
•
•
•
•
•

• Data Acquisition System Amplifiers
• Signal Conditioning
• Medical Instrumentation

Direct Replacement for AD624
Low Nonlinearity: 0.001% (G=1)
HighCMRR:>130dB(G>500)
Low Input Offset Voltage: 251lV
Low RTI Noise: 4 nVNHz (@1 kHz, G=1000)
Gain Bandwidth: 25 MHz (G = 1000)

GENERAL DESCRIPTION
The HINA624 from Honeywell is a highly accurate,
precision instrumentation amplifier deSigned for data
acquisition applications where low noise and very high
DC performance is required. Features such as maximum
Nonlinearity of .001 % (G = 1), Gain Temperature
Coefficient of 5 ppmrc, and Input Offset Voltage Drift of
.251lVrC make the HINA624 the ideal choice for use in
high resolution data acquisition systems.

gain values can also be be achieved by pin strapping.
Any arbitrary gain value of 1--+,_OUTPUT
121.30

RQ2

+ INPUT

Honeywell

5-7

II"

SPECIFICATIONS
"

PARAMETER

TEST
CONDITIONS

G=1
TA= 25 °C

HINA624C
UNITS

I

±.02

±.03

±.05 %

G=1

I

±5

±5

NonlinearHy

G=1

I

±.001

±.003

±.005 %

TA=25°C

I

±25

±75

±200 ~V

I

±.25

±.5

TA=25°C

I

±15

±25

G=1000

I

130

120

110

dB

G=1

I

±10

±10

±10

Volts

G= 1000

I

Input Offset VoRage Temp. Co.
Input Bias Current

I,

HlNA624B

MIN TYPUAX MIN TYPMAX

Gain Temperature Coefficient

Input Offset VoRage

I

HINA624A
UIN TYP~AX

VS=±15V, RL =2KO, OverTemperature Range Specified Below,
Unless Otherwise Indicated

ELECTRICAL CHARACTERISTICS
Gain Error

TEST
" LEVEL

Common Mode Rejection
Linear Differential Input Voltage
Range
Linear Common Mode Input
Voltage Range
Output Voltage

I

±12
±10

±5 ppml"C

±2

±50 nA

±12
±10

TEST LEVEL

~VfOC

±12 Volts
±10

Volts

TEST PROCEDURE
Production tested at the
specified conditions.

* *For Ordering Information See Section 1.

5-8

Honeywell

SELECTION GUIDE, CROSS REFERENCE
ORDERING INFORMATION

ANALOG TO DIGITAL CONVERTERS

DIGITAL TO ANALOG CONVERTERS

COMPARATORS

INSTRUMENTATION AMPLIFIERS

EVALUATION BOARDS

APPLICATIONS INFORMATION

QUALITY ASSURANCE

PACKAGE OUTLINES

SALES OFFICES AND
REPRESENTATIVES

Honeywell

6-1

6·2

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

HTHA27140

16-BIT ACCURATE, MONOLITHIC TRACK AND HOLD AMPLIFIER
ADVANCE INFORMATION
FEATURES

APPLICATIONS

• 5J,LS ACQUISITION TIME

• Sonar
• DigHal Scales
• Instrumentation
• Communications
• DSP Interface
• Acoustic Analysis
• Use With HADC78160 16-bit AID Converter

• Low Power - 300mW
• Internal Hold Capacitor
• 16-bH Accuracy
• ±5V analog input
• Linearity - 0.0008%

GENERAL DESCRIPTION
The HTHA27140 is a 16-bH accurate, monolithic trackand-hold amplifier capable of acquiring ±5V analog
signals wHhin 5uS yet only consuming 300mW of power.
Included on-chip are two internal hold capacitors that
keep the track-to-hold settling time down to 300nS. The
part has the highest speed and accuracy for the power In
the industry.
There is a track-and-hold control pin and an output sense
pin connected to the inverting input of the preamp stage.
Separate analog and digital ground pins are provided

to achieve 16-bH accuracy in board layout, and to be
compatible with other components that require separate
ground planes. The HTHA27140 is optimized to be used
with the HADC78160 16-bit AID converter to increase
the AID analog input frequency range. The device is
manufactured on Honeywell SPTs small geometry bipolar
process, and military and industrial temperature grades
are available.
The part is packaged in a 14 Lead Ceramic DIP and
operates on ±15V power supplies.

BLOCK DIAGRAM

Honeywell

6-3

ELECTRICAL SPECIFICATIONS
MILITARY TEMPERATURE RANGE
@ 25°C case temperature and nominal supplies.

ELECTRICAL
PARAMETERS

TEST
CONDITIONS

TEST

ROOM
+25oC
LEVEL
MIN TYP MAX

COLD
HOT
.-SSOC
+1250C
MIN MAX MIN
MAX

UNITS

STATIC PARAMETERS
Power Dissipation
Gain

300

mW

1±O.O1%

VN

Gain Temperature Coefficient

0.1

PPM/oC

Offset

1.0
0.5

mV

1.0

mV

Offset Temperature Coefficient

Full Scale Range

Pedestal

PPM/oC

Pedestal Temp. Coefficient

Full Scale Range

0.1

PPMrC

Linearity

Full Scale Range

10

PPM

Input Impedance

5

KO

Logic Loading

1

LSTTL

VoHage Range

±5

V

1OV step to 0.0008%

5.0

~

Track to Hold

300

nS

Bandwidth

4.0

MHz

Slew Rate

3.0

VI~

DYNAMIC PARAMETERS
Acquisition Time
Settling Time

Noise

15.0

nVlvHz

TEST LEVELS: 1- Production tested at the specified conditions; " - Sample tested to ensure compliance.

* *For Ordering Information See Section 1.
6-4

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES
PROGRAMMABLE 7TH ORDER LOW PASS ACTIVE FILTER

HSCF24040

PRELIMINARY INFORMATION

FEATURES

APPLICATIONS

• 85 dB Dynamic Range
• Cut Off Frequency (/c) up to 20KHz
• On-Chip Anti-Aliasing Protection
• Programmable Bandedge Frequency for both RC
and Switched Capacitor FiHer
·S/H Output
• Microprocessor Compatible
• 7th Order Ladder FiHerwith Cosine PrefiHering Stage
• Stopband Attenuation> 76 dB at 3 Ic
• Programmable DC Gains of 1, 2, 4, 8
• On-Chip Oscillator (External Crystal)

• Anti-Alias FiHering
• Test Equipment/Instrumentation
• Spectrum Analyzers
• Medical Telemetry/FiHering
• Speech Analysis and Synthesis
• Data Acquisition Systems
• Computer Controlled Test Systems

GENERAL DESCRIPTION
The HSCF24040 is a monofithic 7th order active filter
system. It is manufactured using Honeywell's state-ofthe-art BEMOS process which allows the fabrication of
low power CMOS logic, linear CMOS circuits, bipolar
linear circuitry and thin film resistors on a single chip. The
HSCF24040 is designed using switched-capacitor techniques which allows easy programming of the filter cut-off
frequency.
The HSCF24040 contains a fully differential, 7-pole,
lowpass switched-capacitor filter (SCF) which is designed
to provide an accurate, programmable passband for fixed
or dynamic applications. The switched-capacitor filter section is preceeded by a 3-pole active RC filter (RCF)

with a programmable bandedge. Together, the RCF and
SCF provide greater than 76 dB ·of anti-aliasing protection. The last stage of the SC filter contains a programmable decimator that reduces the sample rate at
SCOUT. This insures that the hold period of the sampled and held output is long enough to perform an AID
conversion or be re-sampled by an external S/H.
The topology and layout of the HSCF24040 is sufficiently flexible to allow customization of the filter function
and/or logic. The HSCF24040 is packaged in a 32 pin
DIP, operates on a +/- 5V supply voltage and is offered in
commercial and military temperature ranges.

BLOCK DIAGRAM
Ci WA

es AS AD

DO-D7 0,.(12 CLKlN

X,

X2

PO
Vee

Vss
L,----,J I ....:===~+~ONe
tCLKOUT

SCOUT

ReiN

ReoUT

Honeywell

SCIN

AAlliIf

6-5

ABSOLUTE MAXIMUM RATINGS (Beyond which damage may occur)1 2SoC

Temperature
Operating Temperature, ambient... ........-55 to +125°C
junction ......................+17SOC
Lead Temperature, (soldering 10 seconds) ..... +3000C
Storage Temperature .............................-65 to +150oC

Supply Voltages
Positive Supply Voltage (VDDto GND) ..............Oto +7V
Negative Supply Voltage (VSS to GN D) .............0 to -7V
Input Voltages
Digital Input VoltageL
All Exce.ELCLKIN, CS ......................-O.3to VDD+O.3V
CLKIN, CS ...............................VSS-0.3 to VDD+0.3V
Notes:

1. Operation at any Absolute Maximum Rating is not implied. See Electrical Specifications for proper nominal applied
conditions in typical applications. Excessive exposure to absolute maximum ratings may effect device reliability.
2. The XTAL oscillator must not be enabled unless the external crystal is connected between pins X1 and X2.
VDD = +5.0V, VSS = -5.0V, +25°C (Unless Otherwise Specified)
TEST

TEST
LEVEL

MIN

TYP

VDD

I

4.75

VSS

I

-5.25

PARAMETER

CONDITIONS

MAX

UNITS

5.0

5.25

Volts

-5.0

-4.75

Volts

DC ELECTRICAL CHARACTERISTICS

IDD

VDD = 5V, VSS - -5V

I

15

rnA

ISS

VDD .. 5V, VSS =-5V

I

-15

rnA

Power Dissipation

VDD - 5V, VSS. -5V

I

. l50

mW

Gain=1 VN

I

±O.1

Gain Tolerance
Gain
Offset Voltage

Gain = 1 VN

Power Down/Power Dissipation

%

I

Programmable 1, 2, 4, 8

I

5

mV

I

15

mW

4

MHz

VoltsNolts

AC ELECTRICAL CHARACTERISTICS
RC FILTER & SC FILTER
Input CLK Frequency
Cut-off Frequency Range
Input Signal Level

6-6

I

Ic

1
78

I

20,000

±3

Hz
Volts

Honeywell

VDD = +5.0V. VSS = -5.0V. +25°C (Unless Otherwise Specified)
TEST
PARAMETER

CONDITIONS

TEST
LEVEL

o
"'It
o
"'It

MIN

TYP

MAX

UNITS

~

AC ELECTRICAL CHARACTERISTICS
Output Voltage Swing

ZL = 5KDJI50pF

I

Output Current Drive

RCOUT & SCOUT

I

Pass Band Ripple
Bandedge Tolerance
Filter Response
(Relative to DC Gain)

I

fc=( -0.1) dB freq
Ot01.0fc

"
I

±3

Volts

rnA

0.6
-0.1

+0.1

%

fc±0.5
-0.1

dB

+0.1

dB

1.5fc

I

-30

dB

2.0fc

I

-52

dB

~.Ofc

I

-76

dB

I

Dynamic Range
Wideband Noise

SCF BW = 20 kH~
RCF BW = 80 kHz
Magnitude of
Harmonic

dB

85

"

100

~Vrms

I

-72

dB

I

0.05

%

50

dB

35

dB

RC FILTER

"
"

DC Gain

I

Bandedge Tolerance

I

Harmonic Distortion

THO
PSRR: In-Band
High Frequency Aliasing

Cut-off Frequency Range
Filter Response

-0.1

+0.1
fc(RCF)

7

'1

%
%

fc(RCF)

I

fc(RCF)/4

I

-0.05

dB

fc(RCF)

I

-3.45

dB

17 fc(RCF)

I

-76

dB

See Note 2

I

80

KHz

CLOCK
Internal OSCillator Frequency

Honeywell

C\I

11.

1

4

MHz

6-7

VDD = +5.0V. VSS = -5.0V. +2O"C (Unless OJl1erwise Specified)
TEST

TEST
LEVEL

MIN

Input Higl1 Voltage

I

2.0

VDD

Volts

Input Low Voltage

I

0.0

0.8

Volts

Input Leakage Current

I

Input Capacitance

"

PARAMETER

CONDITIONS

TVP

MAX

UNITS

ELECTRICAL CHARACTERISTICS
DIGITAL ELECTRICAL
PARAMETERS

1

I1A

10

pF

TIMING CHARACTERISTICS (See Timing Diagrams)

J.LP INTERFACE TIMING
CSHoldTime

t5

I

10

nsec

Data Hold Time

t4

I

10

nsec

Data Set-upTime

t3

I

100

nsec

Address Hold Time

t2

I

10

nsec

Address Set-up Time

t1

I

20

nsec

SyncB Delay Time

t8

I

25

nsec

SyncB Set-up Time

t9

I

25

nsec

CLKIN to CLKOUT Delay

t6

I

10

nsec

CLKIN to CN\iRi" Delay

t7

I

20

nsec

SCOUT
SVNCHRONIZATION
TIMING

6-8

Honeywell

TIMING DIAGRAMS
MICROPROCESSOR INTERFACE TIMING
ADDRESS
AO

DATA

t1

00·07, G1·G2
t3

t2

t4

~
AS

OS

WR

t5

CS

SCOUT SYNCHRONIZATION TIMING

ClKIN

ClKOUT

TEST LEVEL CODES
ELECTRICAL CHARACTERISTICS TESTING

TEST LEVEL

All electrical characteristics that follow are subject to the
following conditions:
All parameters having Min.lMax. specifications are guaranteed. The Test Level column indicates the specific device testing actually performed during production and Quality Assurance inspection. Any blank sections in the data columns indicates that the specification is not tested at the specified condition.

TEST pRocepURE
Production tested at the specified
temperatures.

II

Parameter is guaranteed by design
and sampled characterization data.

Unless otherwise noted, all tests are pulsed tests, therefore Tj
= Tc= Ta.

Honeywell

6·9

o
~
o
~

N
LL

o

~

GENERAL DESCRIPTION
SCFILTER

ACTIVE RC FILTER

SC filters are sampled data filters that provide extremely
accurate and stable responses. This is because their internal "time CQnstants" (Jepend only upon the switching
frequency and the ratios of monolithic capacitors. The
switching frequency Is normally derived from a crystal controlled oscillator and Is thus, extremely precise. On-chip
capacitor ratios are accurate to within approximately
0.1%. Therefore, high order sharp rolloff filters can be
manufactured that require no post production trimming.
Since the filter bandedge can be programme.d by varying
the frequency of the clock that controls the filter's
switches, the filter bandedge can be made to track the
sample rate of an external AID converter. The filter in the
HSCF24040 has 7 poles (Chebyshev approximation) to
insure a minimum loss of 76c1B at 3 times the bandedge
so that the system AID can sample as low as 4 times the
bandedge (see Figure 1). The SC filter has a differential
signal path to improve its PSRR, distortion, and dynamic
range. Through digital programming, bandedges of up
to 20KHz and DC gains of 1, 2, 4 or 8 can be achieved.

Although the SC filter Is programmable and offers
excellent performance, It does have one major drawback.
Because iUs a sampled data filter, It can fold or alias outof-band energy into the desired passband in much the
same way as the external AID. Therefore, a continuoustime filter is required in front of the SC filter to provide
aliasing protection. We are, however, aided by the fact
that the filter sampling rate is many times greater than the
bandedge frequency (50 times in this case). Thus, a low
order, active RC filter with a bandedge accuracy of only
5% will suffice. This concept is illustrated in Figure 2.
The bandedge for this RC filter must be programmable to
Insure sufficient rejection of the SC filter images located
at multiples of the SC filter rate. Eight different RC filter
bandedges spanning a 12-to-1 range are available on
the HSCF24040. The programmability is achieved by
switching different resistor and capacitor values into the
filter. A single RC filter bandwith setting (3dB) of f c(RCF)
will provide 76c1B of anti-aliasing protection for SC filter
bandwidths ranging from fdRCF)/5.71 to fdRCF)/4.

ANTI-ALIASING

INPUT
SIGNAL

AID

FilTER

RC
FILTER
GAIN

Odb

elK
fl(AlD)
I
I
I
I

Signall In this range will
be aliased Into the
baseband.

t---~

Odb
A-A

FILTER

I
I

I
I

I

I

-76db

I
I

fc

f I (AID)

sc

-

FILTER
GAIN

,,,
,

rI

frequency

I

I S (8C).5010

21 8 (8C) .. 100

Since the filter loss is greater than 76 dB, any .aliased
signals will be below the 12 bit level.

Note: The RC filter should provide > 76 dB of loss for
several different SC filter sample rates f s (SC).

FIGURE 1 - REQUIREMENTS FOR AN
ANTI-ALIASING FILTER PRIOR TO AID
CONVERSION

FIGURE 2 - RC FILTER PROVIDES
ANTI-ALIASING FOR SC FILTER

6-10

Honeywell

The topology of the RC fiiter has been chosen so that
the DC gain and the pole O's rely on ratio matching of the
on-chip resistors and capacitors. The RC filter bandedge
is laser trimmed for high accuracy during the manufacturing process.
DECIMATOR

The decimator block samples the differential output of
the SC filter and converts it to a single ended Signal. The
decimator also provides a sample-and-hold output
(SCOUT) at a programmable sample rate of 25fc,
12.5fc, 6.25fc, or 4.167fc, where fc is the SC filter
bandwidth. By choosing the proper decimation rate, the
hold time at SCOUT will be sufficiently long to allow an
NO conversion to take place. (An external sample and
hold may be required for hold times longer than 100fJ.sec
to prevent more than 1/2 LSB of droop for a 12-bit NO
converter).
The CNVRT output is an active low digital output that
indicates when the SCOUT output is valid~ing a
falling edge to the ~ input initiates the C1iJVRT pulse
on the next rising egge
CLKOUT. The use of the
decimator block with YN and CNVRT insures a proper
timing interface between SCOUT and an external NO
converter or sample and hold and eliminates the need for
a smoothing fiiter at the SCOUT output.

gt

PROGRAMMABILITY

The chip contains an 8-bit and a 2-bit data register. Oata
in the 8-bit register controls the SC filter bandedge, RC

Honeywell

filter bandedge, and the deCimation rate. (A programmable divide down chain generates the SC filter clocks
from the master clock. A similar divide down chain determines the decimation rate from the SC filter clocks).
Oata in the 2-bit register controls the programmable O.C.
gain of the SC filter. The truth tables for both registers
are shown in Table 1.
The SC filter's bandedge is programmed by selecting
one of the divide down ratios shown in Table 1. This ratio
is divided into the master clock frequency to arrive at the
filter cutoff frequency. As an example, assuming a typical
master clock frequency of 4 MHz and a divide down ratio
of 400 (00, 01, 02=001), the filter's bandedge would be
10kHz. Alternately, selecting a divide down ratio of 3200
(00, 01, 02 = 100) would provide a fiiter bandedge of
1250Hz. With a constant master clock frequency, up to
seven (7) different discrete SC filter bandedges can be
obtained. An infinite number of different bandedges can
be derived by varying both the divide down ratios and
the master clock frequency. This provides the ultimate
level in programming flexibility.
The five control signals AO, AS, WR, CS, and OS allow
the user to directly interface to 8-bit microprocessors
without additional glue logic. Both Motorola's MPX'ed
and non-MPX'ed bus formats as well as Intel's MPX'ed
bus format is supported. Interface connections for both
the Intel and Motorola 8-bit microprocessors are shown in
Table 2. In addition to the data-latch format, the 00-07
and G1-G2 inputs can be hardwired for direct
pro9..@.mming without the need for a latch signal by tying
the CS" inputto VSS.

6-11

~

TABLE 1· PROGRAMMABLE FEATURES
BCE BANpEDGE

~

N
LL

B"E:kIa allll

~

8.0KHz
56KHz
40KHz
28KHz
20KHz
14KHz
10KHz
7KHz

DZ

~

~

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

p"

pc GAIN
GAIN

a!

G2

1
2
4
8

1
1
0
0

1
0
1
0

PECIMAIQB SAMeLE BATE

"LQCIS IQ SCE IAH!2E!2GE
PllllPE PQWtj BAIIQ

felKI fC

D2

D1

.D2.

fS/HI

200
400
800
1,600
3,200
6,400
12,800

0
0
0
0
1
1
1

0
0
1
1
0
0
1

0
1
0
1
0
1
X

25.000
12.500
6.250
4.167

fe

.oa

W

0
0
1
1

0
1
0
1

fe = 0.1 db Bandwidth of the SC filter.
felK = Master clock frequency at CLKOUT.
fSIH = Sample rate at SCOUT output.

TABLE 2· MICROPROCESSOR INTERFACE CONNECTIONS
HSCF24040

INTEL (MPX'EO)
8088,8085,8051

CS

Generated from AS-A15

MOTOROLA (MPX'EO)
6801,6803
Generated from AS-A15

MOTOROLA (NON-MPX'EO)
6800,6801,6802,6809
Generated from AO-A 15

OS

VOOSupply

E

E

WR

WR

R/WR

RlWR

AO

AOi

AOi

Ai

AS

ALE

AS

VOOSupply

00-07

AOO-A07

AOO-A07

00-07

G1-G2

AOi

AOi

Oi

Note: Tying CS to the VSS supply disables the microprocessor inlerface and
allows DO-07, G1-G2 to be programmed directly without the need for a latch signal.

6-12

Honeywell

OSCILLATOR

TYPICAL APPLICATION CIRCUIT

The HSCF24040 provides an on-Chip oscillator (extemal
crystal) for applications where a system clock is not
available. The user has a choice of either the clock
driven or the oscillator mode. The oscillator mode is
enabled by tying the ClKIN input to VSS.

Figure 3 illustrates how the HSCF24040 might be used
for smoothing the output from a D/A converter. In this
case, the D/A output is fed into the SCIN input .QLthe
device. The SCIN input is enabled by tying AAISM to
ground. The SCOUT output is fed externally into the
RCIN input. The smoothed output is finally brought offchip via the RCOUT pin. (Note that the smoothed output
will not correct for the inherent sin (X)/(X) droop of the
original D/A converter output).

o

HSCF24040

RCIN
SCOUT

RCOUT
SMOOTHED
OUTPUT

SCIN

ClKIN
, - - - - - -......- - - - - SYSTEM CLOCK
D/A
CONVERTER

DATA IN
10001
10010
10011

FIGURE 3 • THE HSCF24040 AS A
SMOOTHING FILTER FOR A D/A
CONVERTER

Honeywell

6-13

"It

0
~

LL

~
::I:

TYPICAL APPLlCAnON CIRCUIT
Tbe HSCF24040 can be used as the band limiting filter
for a 12-bit data acquisition system as shown in Figure 4.
The basic function of the device is to band limit the input
signal so that unwanted out-of-band signals are not
aliased (folded) into the desired passband. The input signal enters the HSCF24040 through RCIN and is processed by the. RC filter. The signal.is.then processed by the
switched-capacitor filter and finally the decimator to facilitate its interface with the AID converter. Figure 1
shows that for a 12-bit system the filter must provide at
least 76dB of loss at the frequency Is-/c (where Is is
the sampling rate of the AID converter and Ic is the
desired channel bandwidth).

In many applications the user may want a
programmable channel bandwidth. An instrument
that records signals that range from 100Hz to
20kHz would require that the AID sample rate be
variable. Figure 1 shows that the required filter
bandwidth is directly proportional to the sample rate
of the AID converter. The filtering necessary for
multiple sampling rates can be accomplished by
using the programmable bandwidth capability of the
HSCF24040 to adjust the desired filter response to
the sample rate. This eliminates the need for a
parallel bank of fixed bandwidth anti-aliasing filters,
one for each sample rate.

r r

AS-A15
ALE

JtIIEI.....Jif
8051
8085
8088

VDD

'Wii

1m"
ADOAD7

VDD

0

XTAL
8
AD

AS

CS

DS

Xl

X2

PO

8
CLK~N

DO-D7

VSS

01-02
HSCF24040

CLKOUT
SYNC
RCIN

AAISM
RCOUT

SCIN

VDD

GND

DATA OUT

VSS

FIGURE 4 • THE HSCF24040 AS AN ANTI-ALIASING
FILTER IN A 12·BIT DATA ACQUISITION SYSTEM

6-14

Honeywell

PIN ASSIGNMENT HSCF24040

VSS

AO

CS

AS

G1

AAiSM

G2

OS

05

N/C

06

WR

07

SCIN
RCIN

01
02
03
N/C

04
SYNC
ClKOUT
VOO

0...,.
0...,.

NAME

FUNCTION

VSS

Negative supply voltage

Os

Chip select; active low

G1-G2

The digital inputs thatconlrOlthe DC gain of the
SCfilter

00-07

The digital inputs IhatconlrOlthe RC filter bandedge,
SC filter bandedge, and SC filter decimation rate

SYNc

This digital Input conlrOls the sampling instant for
the SC filter decimated output; active low

CLKOUT

Master clock output capable of driving 1 stendard
TTL load. It is a buffered version of either CLKIN
or the internally generated crystal oscillator output.

VOO

Positive supply voltage

CNvR'f

This digital output indicates that the SCOUT output
has settled and can now be converted or sampled
(drive capability is 1 standard TTL load); active low

X1-X2

An external crystal is connected between these
pins 10 generate an accurate clock for chip operation

CLKIN

The master clock input. Forcing CLKIN to vss
enables the on-chip oscillator (external crystal).

GNO

Ground

SCOUT

SC filter output

PiS

This digital input is used to power down the
analog circuitry; active low

RCOUT

RC filter output

RCIN

RC filter input

SCIN

SC filter input (only valid when AAlSM is forced low)

WR

Write slrObe; active low

OS

DataslrObe

AAlSM

This digital input conlrOls whether the input to the
SC filter comes from RCOUT or SCIN

AS

Address slrObe

AO

Register address select

C\I

u.

TOP VIEW

00

PIN FUNCTIONS HSCF24040

RCOUT
JStf
SCOUT
GNO
ClKIN
X1
X2
CNVRT

~
::I:

II

* *For Ordering Information See Section 1.

Honeywell

6-15

NOTES:

6·16

Honeywell

SELECTION GUIDE, CROSS REFERENCE
ORDERING INFORMATION

ANALOG TO DIGITAL CONVERTERS

DIGITAL TO ANALOG CONVERTERS

COMPARATORS

INSTRUMENTATION AMPLIFIERS

SPECIAL FUNCTIONS

APPLICATIONS INFORMATION

QUALITY ASSURANCE

PACKAGE OUTLINES

SALES OFFICES AND
REPRESENTATIVES

.Honeywell

7-1

7-2

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

EB100 EVALUATION BOARD

FEATURES

APPLICATIONS

• 150 MSPS MINIMUM CONVERSION RATE
• 70 MHz Full Scale input Bandwidth
'1/2 LSB Integral Linearity (Adjustable)
• Low Clock Duty Cycle Sensitivity (Adjustable)
• Preamp Comparator DesignlOptionallnput Buffer
• Clock produced from any signal generator
• Improved Output Drive (Doubly-Terminated SOQ)
• Optional clock divider board provided

• Evaluation of HADC771 00 AID Converter
• Evaluation of HDAC10181/S1400 D/AConverters
• High Definition Video
• Digital Oscilliscopes
• Transient Capture
• Radar, EW
• Direct RF Down-conversion
• Medical Electronics: U~rasound, CAT Instrumentation

GENERAL DESCRIPTION
The EB100 Evaluation Board is intended to show the
performance of Honeywell Inc.'s Signal Processing
Technologies HADC77100NB flash ND converter and
the HDAC10181NB or HDACS4100 Ultra High Speed
D/A converters. The board provides for either the ADC
or DAC to be tested together or separately. Included on
the unit are two 100K ECL multiplexers for data routing
between the AID and DIA or on and off the board as
shown in the block diagram below.
The HADC77100NB is a monolithic flash ND converter
capable of digitizing a 2 Volt analog input signal with full
scale frequency components to 70 MHz into 8-bit digital
words at a minimum 1S0 MSPS update rate. For most
applications, no external sample-and-hold is required for
accurate conversion due to the device's wide bandwidth.
The HDACS1400 and HDAC10181A1B are monolithic 8bit D/A converters capable of converting data at rates of
400, 27S, and 16S MWPS respectively. The parts have

BLOCK DIAGRAM

optional video controls and can directly drive doublyterminated SO or 7SQ loads to standard composite video
levels. The DACs have an internal reference to supply
themselves and the HADC77100 with a stable voltage
reference and gain control for different output voltage
swings.
The HCMP96870 is a high speed differential voltage
comparator used to generate an ECL compatible clock
signal from any type signal generator.
The board is in Eurocard format with a 64-pin dual height
DIN connector for digital data. The analog inputs, outputs and clock input are standard SOQ BNC connectors.
Tektronix high impedance probe jacks are provided to
monitor the clock lines. Standard -S.2V, +SV, and ±12 to
±1S Vo~ power supplies are required for operation of
the EB100, with nominal power dissipation of less than
10 Watts. The board comes fully assembled, calibrated
and tested. An optional input buffer board is available for
high performance applications and is explained in more
detail on the following pages.

REFEAENCE AND
UNEARITY ADJUST

REFERENCE OUTPUT

FtOO155

M:.~~r::~R

8

8

HDAC10tS1NB

DIffERENTIAl OR
SINGlE ENDED
OUTPUT

OR
HDACSI400

8
iliA

IN

* *For Ordering Information See Section 1.

Honeywell

7-3

II

7-4

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

EB101 EVALUATION BOARD

FEATURES

APPLICATIONS

0150 MSPS MINIMUM CONVERSION RATE
070 MHz Full Scale input Bandwidth
o 1/2 lSB Integral Linearity (Adjustable with three
reference ladder taps)
o low Clock Duty Cycle Sensitivity (Adjustable)
o Preamp Comparator DesignlOptionallnput Buffer
o ECl clock produced from any signal generator
o Improved D/A Output Drive, Doubly-Terminated SOQ

Evaluation of HADC77200 AID Converter
Evaluation of HDAC1 0181/S1400 D/A Converters
o High Definition Video
o Digital Oscilliscopes
o Transient Capture
o Radar,EW
o Direct RF Down-conversion
o Medical Electronics: Ultrasound, CAT Instrumentation
o
o

GENERAL DESCRIPTION
The EB101 Evaluation Board is intended to show the
performance of Honeywell Inc.'s Signal Processing
Technologies HADC77200AlB flash AID converter and
the HDAC10181A1B or HDACS4100 Ultra High Speed
D/A converters. The board provides for either the ADC
or DAC to be tested together or separately. Included on
the unit are two 100K ECl multiplexers for data routing
between the AID and D/A or on and off the board as
shown in the block diagram below.
The HADC77200AlB is a monolithic flash AID converter
capable of digitizing a 2 Volt analog input signal with full
scale frequency components to 70 MHz into 8-bit digital
words at a minimum 1S0 MSPS update rate. For most
applications, no external sample-and-hold is required for
accurate conversion due to the device's wide bandwidth.
The HDACS1400 and HDAC10181A1B are monolithic 8bit D/A converters capable of converting data at rates of
400, 27S, and 16S MWPS respectively. The parts have

BLOCK DIAGRAM

optional video controls and can directly drive doublyterminated SO or 7SQ loads to standard composite video
levels. The DACs have an internal reference to supply
themselves and the HADC77200 with a stable voltage
reference and gain control for different output voltage
swings.
The HCMP96870 is a high speed dual differential voltage comparator used to generate an ECl compatible
clock signal from any type signal generator.
The board is in Eurocard format with a 64-pin dual height
DIN connector for digital data. The analog inputs, outputs and clock input are standard SOQ BNC connectors.
Tektronix high impedance probe jacks are provided to
monitor the clock lines. Standard -S.2V, +SV, and ±12 to
±15 Volt power supplies are required for operation of
the EB1 01, with nominal power dissipation of less than
11 Watts. The board comes fully assembled, calibrated
and tested. An optional input buffer board is available for
high performance applications and is explained in more
detail on the following pages.

REFERENCE AND
LINEARITY ADJUST

REFERENCE OUTPUT

.----'---.

F100156
HAQC77200

REGISTERI
WLTIPLEXER

HDAC10181AIB
OR

HDAC51400

DIFFERENTIAL OR
SINGLE ENDED
OUTPUT

OPTIONAL ANALOG
INPUT OR SE"'N;;;.:SE'--_-,

ANAlOG

INPUT

AJD

DlA

OUT

IN

* * For Ordering Information See Section 1.

Honeywell

7-5

II.

7·6

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

EB102 EVALUATION BOARD

FEATURES

APPLICATIONS

• USE WITH EB100/101 EVALUATION
BOARDS

• Evaluation of HADC771 00/200 NO Converters
• High Definition Video
• Digital Oscilliscopes
• Transient Capture
• Radar,EW
• Direct RF Down-conversion
• Medical Electronics: Ultrasound, CAT Instrumentation

• 70 MHz Full Scale input Bandwidth driving the
converters
• Up to ±1 OOmA Drive current
• Low Distortion
• 15nS Settling Time

GENERAL DESCRIPTION
The EB102 is intended to demonstrate the high
performance achievable with the HADC771 00/200
flash NO converters. The EB102 is a very low
distortion, 70MHz buffer amplifier board. It provides
for higher frequency operation than the buffer on the
EB100 or EB101 evaluation boards. Included on the
unit is either the Comlinear CLC221 Operational
Amplifier or CLC231 Buffer-Amplifier as shown in the
circuit diagram below.
The two versions are identical but are jumpered to
provide for the different amplifier pinouts. The
CLC221 version has the advantage of being
configured up to a gain of 50 as required, and has

slightly better harmonic distortion specifications. The
CLC231 version has a much higher output drive capability and faster settling time.
The EB102 analog input and output are standard 50n
BNC connectors. Standard ±12 to ±15 Volt power
supplies are required for operation. The board comes
fully assembled, calibrated and tested.
The HADC77100/200 is a monolithic flash NO
converter capable of digitizing a 2 Volt analog input
signal with full scale frequency components from 50
up to 70 MHz into 8-bit digital words at a 150 MSPS
update rate.

BLOCK DIAGRAM

:................................... :;.;Pc;.;,--..; .................................... ..

a
ON IOARD
BUFFER

: AtuUST

EB102 BUFFER BOARD

.J. ...... -

~

..........'"

EB1001101
EVALUATION BOARD

L· AF bcIad IndUClor (pAIFI·RITE pm 2743001111/2)
ForFlFlraqlJlnCf'lII:lIIngonltlelUJlPlrplnland
bII.... AGNDMCI DGND.

AlBNCCUIII8ClIors . . lICKl
TROMPETER C8J2o

* *For Ordering Information See Section 1.

Honeywell

7-7

7·8

SIGNAL
PROCESSING
TECHNOLOGIES

EB103 EVALUATION BOARD

FEATURES

APPLICATIONS

• 400 MSPS NOMINAL CONVERSION RATE
• 100 to 150 MHz Full Scale input Bandwidth
'112 lSB Integral Linearity (Adjustable with three
reference ladder taps)
• Preamp Comparator DesignlOptionallnput Buffer
• ECl Timing skew clock generator
• Improved D/A Output Drive, Doubly-Terminated 50n

• Evaluation of HADC77200/300 AID Converters
• Evaluation of HDAC51400 D/A Converter
• Digital Oscilliscopes
• Transient Capture
• Radar, EW
• Direct RF Down-conversion
• Medical Electronics: Ultrasound, CAT Instrumentation

GENERAL DESCRIPTION
The EB103 evaluation board is intended to show the performance of the HADC77200 or HADC77300 flash AID
converters in a ping-ponged mode, and the HDAC54100
Ultra High Speed D/A converter for reconstruction. Included on the unit are two 100K ECl multiplexers for
combining the ping-ponged AID converters' 16 bits of
output data into S bits at twice the speed. The high speed
data is routed between the AID and 01A, and also off the
board as full speed or as divided down data ( external clock)
for slower speed FFT measurements. This is shown in the
block diagram below.
The HADC77200 is a monolithic, S-bit flash AID converter
capable of digitizing a 2 Volt analog input signal with full
scale frequency components to 100 MHz at a 150 MSPS
update rate. For most applications, no extemal sampleand-hold is required for accurate conversion due to the
device's wide bandwidth.

The HADC77300 is identical to the HADC77200 except
that the analog input is 150M Hz with a 2S0 MSPS clock rate
and a corresponding increase in power dissipation.
The HDACS1400 is a monolithic S-bit D/A converter capable of converting data at rates of 400 MWPS. The part
has optional video controls and can directly drive doublyterminated SO or 7Sn loads to standard composite video
levels. The DAC has an internal reference to supply itseH
and the two HADC77200/300 with a stable voltage reference. It also has gain control to provide different output
voltage swings so it can be used as a standard voltage
output DAC.
The HCMP96870A is a dual high speed differential voltage
comparator used to generate an adjustable ECl compatible clock signal for timing skew between the two AID
converters and D/A converter.

BLOCK DIAGRAM
REFERENCE AND
LINEARITY ADJUST

INPUT
BUFFER!

REFERENCE OUTPUT

HDAC51400
8-81T DtA CCNVERTER

DIFFE~~NTIAL
SINGLE ENDED
ANALOG OUTPUT

UEVEL

SHIFTER

TWO·Fl00151
OUTPUT LATCHES

* *For Ordering Information See Section 1.

Honeywell

7-9

II

7·10

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

EB104 EVALUATION BOARD

FEATURES:

APPLICATIONS:

• Provides operating environment for HADC574Z or
HADC674Z and HDAC7545A Devices
• Fully Demonstrates Device Function and Resolution
• Eliminates Noisy Breadboard Evaluation Circuitry
• Buffered AID and D/A Conversion Data Buses
• Includes SamplelHold Amp and Output Op Amp IC's
• Unipolar or Bipolar Operation

•
•
•
•
•
•

Evaluation/Comparison of HADC574/674Z Converters
Evaluation/Comparison of HDAC7545A Converters
System Development
Data Acquision Systems
Bus Structured Instrumentation
Process Control Systems

GENERAL DESCRIPTION
The EB104 Evaluation Board fully demonstrates the
capabilities of Honeywell's HADC574/674Z and
HDAC7545A 12-bit data conversion products. All of the
basic power supply connections, controls lines and
external components are included. The board can
operate in an analog input/output fashion utilizing both
AID and D/A devices, or the devices can be operated
separately. Unlike most laboratory breadboarding, the
ground-planed PC board provides the necessary lownoise evironment essential for 12-bit resolution. The
board makes full use of connectors to allow easy hookup
and operation.

DlA INPUT wonD

Other support provided on the EB104 includes an input
sample/hold amplifier, output operational amplifiers and
potentiometers for offset and gain adjustments.
Customization and function selections are performed by
jumper pins. When considering the HADC574/674Z or
HDAC7545A for system deSign, the EB104 Evaluation
Board provides a flexible, high performance evaluation
vehicle.
The EB104 is supplied with an HADC574ZBCJ and an
HDAC7545AACD. It will support all 574/674 and 7545
type devices.

II

AID OUTPUT wonD

12

.-----------------. DIGITAL CONTROL AND STATUS LINES

FIGURE 1

.---------------.

EB104 BLOCK DIAGRAM

* *For Ordering Information See Section 1.

Honeywell

7-11

7·12

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

EB105 EVALUATION BOARD

FEATURES

APPLICATIONS

• Complete With Socketed HSCF24040ACD Device
• Demonstrates HSCF24040 Performance and
Capabilities
• Toggle Switches for On-Board Control and
Programming
• Connectors Allow Easy Interfacing of External Control,
Programming, and Analog Signals
• Crystal Time Base
• Leaded Power Supply Connector

• HSCF24040 Evaluation
• Prototype System Development
• Programmable General-Purpose Subassembly

GENERAL DESCRIPTION
The EB1 05 Evaluation Board allows full exercise of the
Honeywell HSCF24040 Programmable 7th Order Low
Pass Active Filter. Unlike a handwired breadboard, this
ground-planed, printed circuit board provides a high
performance, noise-free environment. It provides full
demonstration and evaluation of the superb
HSCF24040 dynamic characteristics. Programming
and control of the device is convenienlly enabled by onboard toggle switches. Alternately, programming and
control can be accomplished though the on-board ribbon cable connector. This option allows software control which can aid in system development.
By making full use of the HSCF24040, the EB105 provides an analog input and output for both the RC and

switched-capacitor filters. Both of these low-pass filters
are fully programmable. Analog interfacing is accomplished with on-board BNC connectors to minimize noise
and digital signal coupling. The EB 105 also makes use
of separate analog and digital supply grounds to further
minimize digital coupling.
A clock crystal is supplied on the board which utilizes the
HSCF24040 crystal oscillator feature. An external time
base can be used optionally. BNC connectors are
provided for external clock input and clock output, for the
CONVERT output and the SYNC control line. Use of
BNC connectors on these active digital lines assure a
minimum of digital to analog coupling.

FIGURE 1 EB105 BOARD FEATURES
ACTIVE DIGITAL
SIGNAL INTERFACING

.:<>:: .: :.: : :\:. 'r.~; ~~ ,~~: ~;~~i:

. : :; : :".
•

.·~l~~MlM~9·~ <

. . . .,. . . .~.~.~ F:~·~~·~···········I·····.·~····.··~•. . •.~.•.•.•. ~ . . .

RIBBON CABLE
CONNECTOR FOR
EXTERNAL LOGIC
CONTROL

TOGG LE SWITCHES
FOR MANUAL LOGIC
CONTROL

· i ·.• •·..i~M~&>~.
POWER
CONNECTOR

~
ANALOG SIGNAL
INTERFACING

* *For Ordering Information See Section 1.

Honeywell

7-13

7·14

Honeywell

SELECTION GUIDE, CROSS REFERENCE
ORDERING INFORMATION

ANALOG TO DIGITAL CONVERTERS

DIGITAL TO ANALOG CONVERTERS

COMPARATORS

INSTRUMENTATION AMPLIFIERS

SPECIAL FUNCTIONS

EVALUATION BOARDS

QUALITY ASSURANCE

PACKAGE OUTLINES

SALES OFFICES AND
REPRESENTATIVES

Honeywell

8·1

8·2

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

EB100 EVALUATION BOARD a-BIT, 150 MSPS FLASH AID CONVERTER
AND a-BIT, 165 TO 400 MWPS RASTER D/A CONVERTER WITH REFERENCE
by Tom DeLurio Senior Applications Engineer
FEATURES

APPLICATIONS

·150 MSPS MINIMUM CONVERSION RATE
·70 MHz Full Scale input Bandwidth
·1/2 lSB Integral Linearity (Adjustable)
• low Clock Duty Cycle Sensitivity (Adjustable)
• Preamp Comparator DesignlOptionallnput Buffer
• Clock produced from any signal generator
• Improved Output Drive (Doubly-Terminated 500)
• Optional clock divider board provided

• Evaluation of HADcn1 00 AID Converter
• Evaluation of HDAC1 0181/51400 DIA Converters
• High Definition Video
• Digital Oscilliscopes
• Transient Capture
• Radar,EW
• Direct RF Down-conversion
• Medical Electronics: Ultrasound, CAT Instrumentation

GENERAL DESCRIPTION
The EB100 Evaluation Board is intended to show the
performance of Honeywell Inc.'s Signal Processing
Technologies HADC77100AlB flash AID converter and
the HDAC10181A1B or HDAC54100 Ultra High Speed
D/A converters. The board provides for either the ADC
or DAC to be tested together or separately. Included on
the unit are two 100KECl multiplexers for data routing
between the AID and D/A or on and off the board as
shown in the block diagram below.
The HADC77100AlB is a monolithic flash AID converter
capable of digitizing a 2 Volt analog input signal with full
scale frequency components to 70 MHz into 8-bit digital
words at a minimum 150 MSPS update rate. For most
applications, no external sample-and-hold is required for
accurate conversion due to the device's wide bandwidth.
The HDAC51400 and HDAC10181A1B are monolithic 8bit D/A converters capable of converting data at rates of
400,275, and 165 MWPS respectively. The parts have

BLOCK DIAGRAM

optional video controls and can directly drive doublyterminated 50 or 750 loads to standard composite video
levels. The DACs have an internal reference to supply
themselves and the HADC77100 with a stable voltage
reference and gain control for different output voltage
swings.
The HCMP96870 is a high speed differential voltage
comparator used to generate an ECl compatible clock
signal from any type signal generator.
The board is in Eurocard format with a 64-pin dual height
DIN connector for digital data. The analog inputs, outputs and clock input are standard 500 BNC connectors.
Tektronix high impedance probe jacks are provided to
monitor the clock lines. Standard -5.2V, +5V, and ±12 to
±15 Volt power supplies are required for operation of
the EB100, with nominal power dissipation of less than
10 Watts. The board comes fully assembled, calibrated
and tested. An optional input buffer board is available for
high performance applications and is explained in more
detail on the following pages.

AEFERENCEAND

UNEAATY AlWST

DlFFERENnALOR
HDAC10l'IA18
OR
HDAC51400

Honeywell

8INGI.E ENDED
OUTPUT

8-3

II

GENERAL INFORMATION

o

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Z
c(

The EB100 evaluation board is a fully assembled and
tested circuit board designed to aid in the evaluation of
Honeywell's HAPC77100 '8-bit AID converter, HDAC10181/54100 8-bit 0/1\ converters "and HCMP96870
dual comparator. T\1e bQard ,conta,ins circuitryfoi' buffering the' input "signals, bene rating reference voltages,
dividing the DAC and multiplexer clocks, routing input 1
output data, and generating ECl level differential clock
signals from any signal generator. All digital inputs and
outputs are 10KH and 1POK ,ECl compatible and provisions are made'forgain, offset and linearity adjustments. The board requires -5.2, +5 and ±12 to ±15 Volt
supplies.
The EB100 evaluation board consists of seven functional sections that include an analog input buffer, AID
converter, inpuVoutput multiplexer and data latches, D/A
converter, reference' voltage generator, ECl clock generator, and ECl clock divider. The analog and digital
grounds are separated on the board for better system
grounding characteristics.
There are numerous jumper options available to switch
sections in or out of the system to suit individual needs.
The clock divider circuitry is on a separate board that
plugs into the main board to provide divide by 2 or 4 for
the multiplexer and DAC. The jumper options will be
discussed in more detail in the following sections. In
addition, 90MHz low pass input and output filters are on
board.

ON BOARD ANALOG INPUT BUFFER

OPTIONAL ANALOG INPUT aUfF,ER BOARD·
EB102
"
,

An alternate and higher performance input buffer is
available as an option and sold separately. The EB102 is
intended for users operating at the top end of the input
bandwidth range of the HADC77100. The reason for a
separate board is that the amplifiers utilized are quite a bit
more expensive then the "on-board" buffer. But, with
the added expense, increased input bandwidth with less
harmonic distortion is realized.
There are two ,versions of the EB102 buffer board, one
with a wideband op-amp (ClC221,) and one with a
wideband buffer amplifier (ClC231). Both versions are
identical but are jumpered to provide for the different
amplifier pinouts (See Figure 1A). The ClC221 version
has the advantage of being configured up to a gain of 50
as required, and has slightly better harmonic distortion
specifications. The ClC231 version has the advantage
of a much higher output drive current and better settling
time.
The Following table shows a breakdown of some of the
more important specifications:
TABLE 1· COMPARISON Of COMllNEAR
ClC221/a1 AMPLIFIERS

SPECIFICATION,

ClC221

ClC231

Gain Range

±1 to 50

±1 t05

Output (V, mAl

±12,500

±11,100

6500

3000

-3dB Bandwidth (Av=2)

275MHz

165MHz

Settling Time (nsec, %)

15,0.1
18,0.02

12,0.1
15,0.05

-58
-62

-55
-59

This section consists ofa 90MHz low pass filter, HA2539
high frequency op-amp; and a 2N5836 rf transistor. The
input impedance is 500 and the gain is set at2X so that a
1 Volt input can be applied. Compensation components
are provided and can be adjusted for the desired
frequenCY range needed. The compensation is factory
adjusted for 50MHz bandwidth operation. The bandwidth of the ,buffer amplifier can be increased by decreasing the gain to lX. The BNC connector shown in
the schematics and layout near the output of the buffer
can be used for monitoring the buffer output and input
to the HADC77100. The BNC should be connected to a
500 terminated oscilliscope and will provide a 10X attenuated signal.

100K ECl CLOCK GENERATOR

The positive input to the HA2539 is tied to an offset
adjust to center the input signal to the HADC77100
around -tv , which is needed if a 2Vp-p input Signal is
applied. The input buffer can be bypassed by, removing
the 6.80 resistor at the emitter of the 2N5836 and the
4500 resistor between the BNC' cOnnector and the
HADC771 00. Bypass the 4500 resistor with a jumper
wire and the HADC77100 can now be driven directly.
The input impedance is 4KO in parallel with a 56pF
distributed capacitance.

The ECl clock section consists of an HCMP96870 dual
comparator, duty cycle and hysteresis adjust, F100131
triple 0 flip-flop and several jumper options. Any type
high frequency signal generator can be connected to
the BNC input to the comparjitors. Both inputs to the
dual comparators are connected to the BNC. There are
four outputs which generate differential 100K ECl clock
signals. One set goes directly to the HADC77100 while
the other two can go to the F100155 multiplexers and
HDAC1 0181/51400 orto the clock divider circuitry.

8-4

Slew Rate (V/lJSec)

Harmonic(dBc)
Distortion

Second
Third

Hopeywell

FIGURE 1A - DETAilED SCHEMATIC OF THE
EB102 BUFFER BOARD USING THE
COMllNEAR ClC221/31 AMPLIFIERS

lN4001

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;

FEMALE·Te-FEMALE
5('Q BNC CONNECTOR

................................................................

El0

ON BOARD
BUFFER

EB1 00/1 01
EVALUATION BOARD

-!-

t.

Digital Ground
Analog Ground

L· RF bead inductor (FAiR·RiTE p11274300111112)
For RF frequency filtering on the supply pins and
between AGND and DGND.

All BNC connectors are 500.
TROMPETER CBJ20

The threshold input to the HCMP96870 comparators are
connected together to a pot to adjust the duty cycle of
the clock. The latch enable pins are also connected
together to a pot to adjust hysteresis.
100K ECl CLOCK DIVIDER

The clock divider section is shown below in Figure 1B
and consists of a triple D type flip-flop, which if jumpered
as shown, will provide divided down clock outputs. The
clock divider can be bypassed to provide a full frequency
clock. The divider is provided to make it easier to monitor
the HADC77100 output with a low frequency logic
analyzer and to provide the DAC with a reduced
sampling rate. When switching between divide by 2 or 4,
the unused outputs "a" and "a" must be terminated.
The board is initially set in the divide by 4 mode.
Furthermore, the jumpers on the clock lines to the
multiplexer and DAC must be removed.

-S.2V

-No- i& a 1300 (220030)
Eel Terminaticn

FIGURE 1B -100K ECl CLOCK DIVIDER

Honeywell

8-5

REFERENCE VOLTAGE GENERATOR

o
o....

~

The reference voltage for the HADC771 00 and HDAC10181/51400 is internally generated by the D/A
converter voltage reference of approximately 1.2Volts.
The AID converters 2Volt reference, 1Volt midtap and
ground are controlled by the PMI quad op-amp OP-11.
The magnitude of each setting is further adjusted with
potentiometer R26, R25, and R32 as shown in the
detailed schematic and board layout.

TABLE 2 - OUTPUT LOGIC CODING
MINV
LlNV

0
0

0
1

1
0

OV

111 ... 11
111 ... 10

100...00
100...01

011 ..• 11
011 .. :10

000 ...00
000 ...01

100...00
011 ... 11

111 ... 11
000 ...00

000 ...00
111 ... 11

011 ... 11
100...00

000...01
000 ...00

011 ... 10
011... 11

100...01
100...00

111 ... 10
111 ... 11

VIN

INPUT/OUTPUT REGISTER AND MULTIPLEXER
The multiplexer section consists of two F100155 which
select between external 8-bit digital data from the 64-pin
DIN connector or data from the output of the HADC77100. The choice is controlled by tying the SELECT
pins to either an ECl high for external data or an ECl low
for HADC77100 data. This data is then fed to the
HDAC10.181/51400 on the "Q" outputs of the F100155
and the "Q" outputs are tied to the external connector.

-2V

1: VIH. VOH
0: VIL. VOL

TABLE 2A - POTENTIOMETER AND
CAPACITOR ADJUSTMENTS

AID CONVERTER SECTION
Both input pins to the HADC77100 are tied together to
be either fed by the input buffer or by an external
source. The MINV and L1NV inputs are left open and tied
internally to an ECl low. Diodes are provided to tie them
high and change the output logic. The connection
choices for determining the output logic are in Table 2.

NO.

FUNCTION

R26

Pot for adjusting gain to produce a 2V reference
vokage for the VRS pin on the HADC771 00 from
the1.2V reference voltage supplied by the
HDAC10181151400.

R25

Pot for setting the linear~y adjustment or midtap pin
(VRM", 1V) on the HADC771 00.

R32

Pot for setting the top point (VRT) on the reference
vokage ladder. Nominally set at 50mV below AGND.

R36

Pot for adjusting output current drive from the
HDAC1 0181151400 (See data sheets).
Vout+=25.6(digital code X Iset)lRl

R5

Pot for setting the HCMP96870 comparator threshold voltage to adjust the ECl clock duty cycle.

R4

Pot for adjusting comparator hysteresis.

R23

Pot for adjusting upto a 2Voffset voltage at the
buffer output for driving the HADC771 00.

R22

Pot for adjusting compensation forthe buffer. This
has been set for a flat response. The frequency
range can be increased at the expense of gain
peaking and phase margin reduction by
.decreasing the potentiometer resistor value.

0/A CONVERTER SECTION

The D/A converter section contains jumpers to use
either the HDAC10181 or HDAC51400. The primary
difference in the two parts is the reference voltage
connections. These differences are shown in the detailed schematic in Figure 2. All EB100 boards and
jumpers will be connected for the HDAC10181A part. If
an HDAC51400 is indicated when the board is ordered
(See last page), the board jumpers must be configured
as shown in Figure 4A and 4B by the user.
The output current magnitude for the HDAC10181/
51400 is controlled by a potentiometer (R36) through
the DAC's Iset control pin. In addition, two 90. MHz low
pass filters are provided at both out- and out+ output
pins as well as 50n terminating resistors. The terminating
resistors can be changed to 75n if desired. Keep in
mind that the transmission line must be terminated at the
receiving end with the same value resistor. The video
and feedthrough controls are routed to the 64-pin DIN
connector and are normally disabled.

C25

C44

8-6

"lead" Capacitor for controlling gain peaking in the
input buffer. Used in conjunction with Pot R22 and
Cap 044 for the HA2539.
"lag-lead" compenstion capacitor used with R22.

Honeywell

POWER SUPPLV CONNECTIONS

TABLE 3 - POWER DISSIPATION

Power to the EB100 is supplied through a six pin Molex
type connector. The supply lines are color coded as
shown in Figure1 C. Connect the wire end of the power
supply harness to power supplies as shown by Figure
1C and the silk screen near the mating connector on the
PC board itself. The power harness is attached to the
board with the bevelled edges and hollow connector
alligned to the mating connector.

EB100 WITH CLOCK DIVIDER, ±15V

o

The power requirements for the EB100 at different
supplies and with or without the clock divider board is
shown in Table 3. When powering up the board, check
to see if the current draw from each supply is equivalent
to the numbers in the table. If there is a large difference,
then recheck your connections. Supply protection
diodes are on the board for any reverse polarity
connection, but over-voltage protection is not provided

Voltage

Current

Power

+1SV

.145A

2.17SW

-1SV

.148A

2.220W

+SV

.006A

0.030W

-S.2V

1.39A

7.228W

....o
~

11.653W
EB100 W/O CLOCK DIVIDER, ±12V

DO NOT TURN ON THE POWER UNTIL ALL
LEADS ARE CONNECTED TO THE SUPPLIES
AND THE HARNESS IS ON THE BOARD!!

Voltage

Current

Power

+12V

.119A

1.428W

-12V

.123A

1.476W

+SV

.006A

0.030W

-5.2V

1.27A

6.604W
9.S38W

BLACK DGND

BLACK AGND

4
WHITE -5.2V

WHITE +5V

2

5

RED -12V

RED +12V

3

6
TOP

@@
@
@
BOTTOM
FIGURE 1C - POWER SUPPLY HARNESS CONFIGURATION

Honeywell

8-7

and harmonics for a particular application. Mini-Circuits
Inc. ( see below) supplies a range of low pass filters that
fit into the same position as the 90MHz filters on the
EB100 Evaluation board.

ANTI-ALIASING AND CLOCK NOISE FILTERS

o
o
.....

~

The input to the EB100 buffer circuitry and the differential outputs from the D/A converter are provided
with high frequency noise filters. The three filters are
90MHz low pass and are intended to be used with the
full analog input frequency and full clock sampling rate of
the HADC77100 AID converter. If lower frequencies are
used, the filters should be changed to filter clock noise

Also, adjustment of the clock duty cycle with potentiometer R5 will lower the overall noise floor by controlling
the setup and hold time of the digital data for the
muftiplexers (F100155) and DAC (HDAC10181).

Low Pass
Typical Frequency Response

DC

0.9

1

1.35

1.75

3

Frequency X feo

RLO.OOdBm ....
ATTEN10dB
10.00 dB IDIV

.. MKR #1 FRQ 7.83 MHz .
-55.74dBm

MARKER
7.83 MHz
-55.74dBm
1

CENTER 17.46 MHz
AB 300 KHz
VB 300 KHz

SPAN 32.78 MHz
·ST 50.00 msec

DAC OUTPUT SPECTRUM ANALYSIS OF A 10MHz INPUT FUNDAMENTAL
WITH 10.7MHz (PLP-10.7) INPUT/OUTPUT LOW PASS FILTERS AND 100MHz CLOCK RATE

8-8

Honeywell

PLP
caseA01

PASSBAND, MHz

feo,MHz

STOP BAND, MHz

VSWR,

MODEL

(loss < 1dB)

(loss3dB)

(loss> 2OdB) (loss> 40dB)

Passband Stopband

NO.

Min.

Nom.

Max.

Min.

Typ.

Typ.

PLp·10.7

DC-11

14

19

24

200

1.7

1.7

PLp·50

DC-48

55

70

90

200

1.7

17

PLp·70

DC-60

67

90

117

300

1.7

17

PLp·l00

DC-98

108

146

189

400

1.7

17

Case no.

A01

A

Max.

A

B

C

D

F

E

G

H

J

K

.770

.800

.385

.400

.370

.400

.200

.20

.14

.031

19.56

20.32

9.78

10.16

9.40

10.16

5.08

5.08

3.56

.79

lETTER M OVER PIN 2
MCl

TOP VIEW

KDIA.
TYP.

!

g

G

F

2

4

f 14--~

-

6

A
B

8

==1

NOTE: BLACK BEAD INDICATES
PIN 1. PIN NUMBERS DO NOT
APPEAR ON UNIT. FOR
REFERENCE ONLY.

~

-f-

---

II

.!!.
H

PIN CONNECTIONS
SEE CASE STYLE OUTLINE DRAWING
GROUND
2,3,4,5,6,7

Honeywell

8·9

AN100

~

To Power Bus

o

FIGURE 2 - DETAILED SCHEMATIC OF EB100, REVISION C

To ~itaI Ground Plane
1N4001

~tpF

1N4001

To Analog Ground Plan_

L

To Power Bus

=
=

e

1-

if~QQ

. . . is

i

5--

CUIII

LlsanECLIow r15.1K1l

-t

.,3Dn (22033O)-t-+

ECL TermI_

-!-

*

-5.2V

22QQ
Hisan Eel high

i

lN9l'

Digital Ground
Analog GlUUnd

L - RF bead inductor (FAIR-RITE pin 274300111112)
For RF frequency fitering on the supply pins and
between AGND and OGNO.

FIGURE 3 - TIMING DIAGRAM

o
o,...

~
elK

DATA LATCHED ON
77100
N

77100 DATA OUT

,,,

,,

ClK TO EON 100155

100155 OUPUT TO
10181/54100

~

,
TRANSPARENT:

TRANSPARENT:
LATCHED

DATA VALID
AT 100155

I
N-1

I,,

DATA lATCHED ON
77100
N+1

lATCHED

DATA VALID
AT 100155

LATCHED

N

L

DATA VALID
AT 100155 N+1

100155 OUTPUT
CONDITION TO
10181/54100

10181/54100
ANALOG OUTPUT

Honeywell

8·11

Figure 3 Continued 10181/51400 Timing Diagram

o
o

~

~

~-----------------+----~----------------------------1.3V ----tf--~:....---4----+----4_~___1If_--~f_--~~---CONY

OUT+

YlLSB

8·12

Honeywell

o
o
,...

~

4.600

7.000----------------------~

o

n0 °
l~lD +Do
+5 +12

+

DGND

AGN't:::!i5.2

...

o

-12

~

g+

o~

+

:. 0

a:::NEYWELL

0

°

SPT

DO

000

...

~.

!\IX: IN

iOoD 0o 0 00
O
o0

C25EJ

...

0

a

,.

DO
...

~lOO. 0oC4b~
1123

DO

DO
0

+

...

00

.,

..

I~·

f

I

100155

-

1126'

I

CII

D

2...

0

1125

00 0

o

,.
_

R

• g
A

R
D

8

N

N
E

HLlI'C10181

=~<1400

0 """"'""...
_c::::::J

~~---I 0... BOO 0000 c:::J
~
om",

2N5836

2539

112(:)

Hl\OC77100

[] c::::a

o

o~

R36

...

~
~

00

~

0a!- 0

EB100 REVc

FIGURE 4A· MAIN BOARD LAYOUT AND COMPONENT POSITION
(Not To Scale)

Honeywell

8·13

o
o.,...

~

HDAC1 0181 AlB
JUMPER
SETTINGS

..

JUMPER
SETTINGS

~~
010

I

~
--c:::J-.

--c=l-

I

I

HDAC51400

I

""0

r-

""0
I

.....

010

""0

r-

""0
I

.....

0
0

0
0

EDGE OF THE PC BOARD

EDGE OF THE PC BOARD

FIGURE 4B • JUMPER POSITION AND CONNECTIONS FOR EITHER THE
HDAC10181A1B OR HDAC51400

(Not To Scale)

8·14

Honeywell

o
o

~

2.000

3.000

o
DCLK
DCLK

-5.2

CLK

FIGURE 5 - CLOCK DIVIDER BOARD LAYOUT AND COMPONENT POSITION
(Not To Scale)

Honeywell

8-15

EB100 REVISION C PARTS LIST

PARTS LIST

o

....o

~

NO•

DESCRIPnON

QTY.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

FERRITE BEAD
DIODE
TRANSISTOR
I.C.
I.C.
I.C.
I.C.
I.C.
I.C.
FILTER
RESISTOR
RESISTOR
RESISTOR
RESISToR
SIP RESISTOR PACK
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
POTENTIOMETER

11
4
1
1
1
2
1
1
1
3
1
1
1
7
5
4
4
2
3
3
1
1
1
1
2

26
27
28
29
30
31
32
33

POTENTIOMETER
CONNECTOR, DIN
CONNECTOR
CAPACITOR, CHIP
CAPACITOR
CAPACITOR
CAPACITOR, ADJ
CONNECTOR, BNC
TEST POINTS
PIN RECEPTACLE
PIN SOCKET
SOCKET, 24PIN
PRINTED CIRCUIT BOARD

6
1
1
16
10
29
2
5
2
42
9
1
1

34

35
36
37
38

MANUFACTURER I PART NO.
FAIR-RITE CORP.-2743001111
lN4001
MOTOROLA-2N5836
HONEYWELL-HDAC10181A1BORHDAC51400
HONEYWELL-HCMP96870
FAIRCHILD-Fl00155
PMI-OP-ll
HONEVWELL-HADC77100B
HARRIS-HA2539
MINI-CIRCUITS-PLP-l00
2400, '2!N
560,lI'2!N
6.80,l18w
10Kn,l/8w
22013300
22On,l/Sw
33On,l/Sw
7500. 1/8w
500,l/8w
4700,l/8w
10n,l/8w
15.10,l/8w
5kn,l/8w
1.5kn,l18w
BOURNS-1Kn, 3329-H-l02 & MOUSER-ME3234290W-lkn
BOURNS-l0Kn,3329-H-l03
BELL IND.-905-72184C
MOLEX-09-18-5069
JOHANSON-47pf 500R15N47OJP4
SPRAGUE-lufTANT,35V
SPC TECHNOLOGY-O.lld
JOHANSON-47pF-9629
TRUMPETER-CBJ20, son
TEKTRONIX 131-2766-01,136-0352-02
MILL MAX-0552-1-15-15-11-27-10-O
SAMTEC-SL-132-G-12
SAMTEC-IC0-624-NGT
HONEVWELL-EB100

EB100 CLOCK DIVIDER BOARD
NO.
39
40
41
42
43
44
45
46

8-16

DESCRlPnON
Fl00131
CAPACITOR
TEST POINTS
RESISTOR
RESISTOR
RESISTOR
CAPACITOR
TEST POINTS

QTY.
1
2
2
6
4
4
1
2

MANUFACTURER I PART NO.
FAIRCHILD TRIPLE D-TYPE FLIP-FLOP
.111F
TEKTRONIX 131-2786-01, 136-0352-02
lKn,l18w5%
22Oo.l18w 5%
3300,l/8w5%
JOHANSON-47pF CHIP
COMPONENTSCORP.-TP-l02

Honeywell

EB102 REVISION B PARTS LIST

o
o.....

PARTS LIST
NO.

REF. DESIG.

1

C1,3,5,B, 12, 13, 15

2

C2,4,7,14

3

C10, 11, (NOTE 3)

4

DESCRIP110N

OTY.

~

MANUFACTURER 1 PART NO.

CAPACITOR, .1111 - 50V

AVXI SR205E104MAA

4

CAPACITOR, 47pl - CHIP

JOHANSON 1500R15N47OJP4

2

CAPACITOR, SEALTRIM 5-20pf

JOHANSON 19629

CR1,2

2

DIODE, 1N4001

5

E1,2

2

JUMPER PINS (HEADER STRIP)

6

FL1

1

FILTER, 90MHz LOWPASS

MINICIRCUITS 1PLP-1 00

7

J1,2 (NOTE4)

2

RECEPTACLE, BNC

TRUMPETER I CBJ20

B

L1,2

2

RFBEAD

FAIR-RITE 1274300111112

7

CYPRESS ITSW-1-36-07-T-S

P1

1

PLUG

MOLEX 109-1B-S031

10

R1,2

2

RESISTOR, 10K OHM

HAMILTON I AVNET 1CF1/B-1OK-S%-T/R

9
11

R4,12

2

RESISTOR, 33 OHM

HAMILTON I AVNET I CF1/B-33-5%-TIR

12

R5

1

RESISTOR, 2SK OHM

HAMILTON I AVNET 1 CF1/B-25K-S'-o-TIR

13

R7(NOTE 1)

1

RESISTOR,1.5KOHM

HAMILTON I AVNET ICF1/B-1.SK-5%-TIR

14

R7, B (NOTE 2)

2

RESISTOR, 250 OHM

HAMILTON I AVNET I CF1/B-250-5%-T/R

1S

R9

1

RESISTOR,1500HM

HAMILTON I AVNET ICF1/B-150-5%-T/R

16

R10

1

RESISTOR, 51 OHM

HAMILTON 1AVNET I CF1/B-51-5%-TIR

17

R3

1

POTENTIOMETER,10KOHM

BOURNS 13339-1-103

1B

RS,11

2

POTENTIOMETER, 1M OHM

BOURNS 13339-1-1 OS

19

CS,9

2

CAPACITOR, 111fTANT, 35V

SPRAGUE 119S DI05X9035HAI

20

U1 (NOTE 1)

1

I.C.,OP-AMP

COMLINEAR I CLC221 A1

21

U1 (NOTE 2)

1

I.C., BUFF-AMP

COMLINEAR I CLC231 A1

22

PCB1

1

PRINTED CIRCUIT BOARD

HONEYWELL I EB 102 REV. B

II

NOTES:
1) USE ITEM NO. 13 WITH ITEM NO. 20 AND JUMPER E1, 2.
2) USE ITEM NO. 14 WITH ITEM NO. 21.
3) USE C1 0 WITH ITEM NO. 21 ONLY.
4) J21S MOUNTED ON THE BACKSIDE OF PCB1.

Honeywell

8-17

g.,...

•

~

.....
o

[!]..,

•

0

•

\
• .J ••• ~
~.-~
~

~....,

o

[!]O

........
0"
00

0

.____

--...

~ ,.,

!:e~ S

K

O~

PI

FLI

PCBI

FIGURE 6· EB102 BUFFER BOARD LAYOUT AND COMPONENT POSITION

(Not To Scale)

8·18

Honeywell

--------------------------------------------------------------------------------SET-UP PROCEDURE FOR THE EB100 DEMONSTRATION BOARD

The following setup procedure is completed at Honeywell before the EB100 board is shipped to the customer.
It is not necessary for the user to perform this exercise,
but it is included for informational purposes.
The EB100 demonstration board is accompanied with a
literature package containing the "AN100 APPLICATION
NOTE" , the "HADC771 00", "HDAC51400", "HDAC10181", and "HCMP96870· data sheets, and an
applications department business card. Also, a power
harness, and a capacitor alignment tool are included. If
there are any questions, please call the applications
engineer on the card.
STEP 1
Connect the wire end of the power supply harness to
power supplies as shown in Figure 1C. The power
harness should be connected to the board with the
bevelled edges and hollow connector alligned for
correct operation.
DO NOT TURN ON THE POWER UNTIL ALL
LEADS ARE CONNECTED TO THE SUPPLIES
AND THE HARNESS IS ON THE BOARD!!

o
....o

z

c(

Table 3 (page 6) shows the power requirements for the
EB100. Use the current gauges on the power supply or a
DMM in line with the power lines and set on current (I).
these current values will vary somewhat until all the
potentiometers are adjusted. When powering up the
board, check to see if the current draw from each supply
is equivalent to the numbers in the table. If there is a large
difference, then recheck your connections. Supply protection diodes are on the board for any reverse polarity
connection, but over-voltage protection is not provided.

STEP 2
Refer to Figure 2 and 4 on the previous pages. Place a
DMM probe (set to voHage selection) on the black
jumpers at the input to the HADC77100 (E14). This
should read -Wand is adjusted by turning potentiometer R23 (See Table 2A).
STEP 3
Again, refer to Figures 2 and 4 on the previous pages
and Table S on this page. Place a DMM probe (set to
voltage selection) on pin 3 of the OP11 and read
approximately -1.2V. If it does not then check to see if
the black jumpers for the HDAC10181/S1400 are set up

TABLE 5· EQUIPMENT LIST
2 - SIGNAL GENERATORS CAPABLE OF PRODUCING 1MHZ AND 20MHZ SINEWAVES AT UP TO Wp-p
OUTPUTLEVELS INTO son. H.P. 8656A OR EQUIVALENT.
1 - OSCILLISCOPE, EITHER H.P. DIGITIZING OSCILLISCOPE MODEL 541 000 OR EQUIVALENT OR
TEKTRONIX MODEL 2465.
1 - DIGITAL MULTIMETER(DMM), KEITHLEY 197 OR EQUIVALENT.
4 - POWER SUPPLIES CAPABLE OF PRODUCING THE POWER LISTED IN TABLE 1. 2 LAMBDA
LPT-7202-FM OR EQUIVALENT.
S - son COAX CABLES (RGS8) WITH BNC TYPE CONNECTORS.
1 - HIGH IMPEDANCE PROBE (1 Mn) - TEKTRONIX OR H.P.

Honeywell

8-19

II

o
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~

for the right part (see Figure 4B). Next set the probe on
pin 1 of the OP11. This should read -2V and is adjusted
by turning potel)tiometer R26. Now set the probe on pin
7 of the OP11. This should read approximately -1 V and
is adjusted by potentiometer R35; Pin ·8 of the OP11
should read approximately -50mV and is adjusted by
potentiometer R32.
STEP 4
Refer to Figures 2 and 4. Attach a son BNC cable to the
"ClK IN" BNC connector. Attach the other end to a
sinewave .or signEiI generator set at 20MHz frequency
and 1Vp-p amplitude (if 1Vp-p is not available, amplitudes down to 100mVp-p are acceptable). Put a
Tektronix or H.P. high impedance probe in one or both
of the probe jacks immediately below the HCMP96870
comparator. Adjust potentiometer R5 to achieve a 50%
duty cycle square wave (both "high" and "low· states are
the same length). Adjust potentiometer R4 if no
waveform is present and/or to get rid of any jitter in the
square wave (this is a hysteresis adjustment). The
square wave amplitude should be approximately
900mVp-p and look like Figure 7 below.

-100.000 nsec
Ch. 2
Timebase
Ch. 2 Parameters
Rise Time
Freq.
..
+ Width
..
Overshoot ..

STEP 5
Refer to Figure 2 and 4. Attach a 50n coax cable to the
BNC connector marked "BUFFER IN". Use a second
sinewave or signal generator set at 1 MHz frequency and
1Vp-p amplitude (See Figure 8). Attach another cable to
the BNC connector "AID IN I BUFFER OUT" and to an
oscilliscope set· at 50n input impedance. A 200mVp-p
amplitude signal swinging around -100mVdc should
apear at a 1MHz frequency (See Figure 9). If oscillation is
evident (erratic signal amplitude or wrong frequency),
potentiometer and capacitor C44 must be adjusted as
well as capacitor C25. Adjust capacitor C25 first to
minimize the oscillation. if this does not work, set it at the
lowest amplitude oscillation and adjust potentiometer
R22. Adjust potentiometer R22 to midtum and then
adjust capacitor C44 until the oscillation stops. See
Figures 10, 11, and 12.

0.00000 sec
200.0 mvolts I div
20.0 nsec I div
1.670 nsec
20.1532 MHz
24.940 nsec
6.249 mvolts

100.000 nsec
Offset
Delay
P-PVolts
Fal/Time
Period
-Width

Preshoot

..
..
..
..
..
..

-1.330 volts
0.00000 sec
968.7 mvolts
2.910nsec
49.620 nsec
24.680 nsec
43.75 mvolts

Trigger mode: Edge
On Pos. Edge on Chan2
Trigger Levels
Chan2
=
-1.180 volts
Holdoff
.. 70.000 nsees

FIGURE 7 - CLOCK OUTPUT AT THE TEKTRONIX PROBE JACKS

8-20

.Honeywell

o
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~

FIGURE 8 • INPUT
SIGNAL TO THE BOARD
(50nINPUT
IMPEDANCE)

..

'j'

····················:1:······· .. ··············;.;1···..
:........................ , ........................ , .......... :1 ............. , ..........

-1.00000 usee
Ch. 1
Timebase
Ch. 1 Parameters
Rise lime
Freq.
+ Width
Overshoot

+

.

!

········;·············:··,·····················1······............•.....

.. L. .......i.............i........................,......................,!
1.00000 usee
Offset
0.000 votts
Delay
0.00000 sec
P-PVolts
1.062 volts
289.320 nsee
Fall Time
Period
999.860 nsee
-Width
502.340 nsee
6.249 mvolts
Preshoot

0.00000 sec
200.0 mvo~s I div
200 nsee I div
289.640 nsee
1.00014 MHz
497.520 nsee
6.249 mvoks

Trigger mode: Edge
On Pos. Edge on Chan1
Trigger Levels
Chan1
0.000 votts
Holdoff
70.000 nsecs
...•..,-;"...................... '1'...................... -:-.........j ............. !' ...................... "!'............. ,.. ,,,."'!

...

.

.

.

.

j

.i.

J
.. ·,···· ...... ··············:·· .. ············ .. ··· .. ·1

FIGURE 9· OUTPUT
SIGNAL FROM THE
"BUFFER OUT" BNC
CONNECTOR
(son IMPEDANCE)

. . . ·. . ·. >k. . ·:. . . . . . . i. ·. ·. . ·. ·. . . . . i. . . . . . . . . . . . !
,

i..............·........

r. ·. . ·.

II

+

!..................................................... ,.: ..:::.. :........:....:::":.:.::::'.:':::::..J::::::. :r."::::::J:::'' ::':' :' ::.:::-.I:::::::"::".:::'::.J

-1.00000 usee
Ch. 1
Timebase
Ch. 1 Parameters
Rise lime
Freq.
+ Width
Overshoot

0.00000 sec
50.00 mvo~s I div
200 nsee I div
294.080 nsec
997.904 KHz
499.810 nsee
1.562 mvoks

Offset
Delay
P-PVotts
Fall Time
Period
-Width
Preshoot

1.00000 usee
-100.0 mvolts
0.00000 sec
200.0 mvolts
289.910 nsee
1.00210 usee
502.290 nsee
1.562 mvolts

Trigger mode: Edge
On Pos. Edgeon Chan1
Trigger Levels
Chan1
-100.0 mvotts
Holdoff
70.000 nsecs

Honeywell

8-21

o
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~

FIGURE 10OSCILLATIONS ARE
APPARENT AND
ADJUSTMENT IS
NECESSARY

Ch.1
Ch.2
Timebase

2.50000 usee

0.00000 see

-2.50000 usee
200.0 mvofts ! div
40.00 mvofts I div
500 nsee! div

Offset
Offset
Delay

0.000 volts
-102.0 mvolts
0.00000 see

Offset
Offset
Delay

0.000 volts
-102.0 mvolts
0.00000 see

Trigger mode: Edge
On Pos. Edge on Chan1
Trigger Levels
Chan1
0.000 volts
Holdoff
70.000 nsees

FIGURE11-THE
OSCILLATIONS ARE
DECREASING AND THE
BOTTOM WAVEFORM IS
STARTING TO
APPROACH THE SAME
SHAPE AS THE TOP
WAVEFORM

-2.50000 usee
Ch.1
Ch.2
Timebase

2.50000 usee

0.00000 see
200.0 mvofts! div
40.00 mvofts! div
500 nsee! div

Trigger mode: Edge
On Pos. Edge on Chan1
Trigger Levels
0.000 volts
Chan1
Holdoff
70.000 nsees

8-22

.Honeywell

o

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z

FIGURE12OSCILLATION HAS
STOPPED AND THE

«

BOTTOM WAVE-FORM IS

THE SAME SHAPE AS
THE TOP WAVEFORM
BUT IS INVERTED

-2.S0000 usee

0.00000 see

Ch. 1
Ch. 2
Timebase
Ch. 1 Parameters
Rise Time
Freq.
+ Width
Overshoot

2.S0000 usee

200.0 mvolts I div
40.00 mvolts I div
SOO nsee I div

Offset
Offl$el
Delay
P-PVolts
Fall Time
Period
- Width
Preshaot

290.790 nsee
999.990 KHz
SOO.180 nsee
0.000 volts

0.000 volts
-102.0mvolts
0.00000 sec
665.6mvolts
291.830 nsee
1.00001 usee
499.830 nsee
0.000 volts

FIGURE 13 - OUTPUT
WAVEFORMS FROM
"OUT-" AND "OUT+"
WITHOUT THE CLOCK
DIVIDER BOARD
INSERTED AND THE
CLOCK JUMPERS

CONNECTED AS SHOWN
IN THE TOP OF FIGURE 4
I

!

I

I

!

------r-

-1.00000 usee
Ch. 1
Ch. 2
Timebase
Ch,'1 Parameters
Rise Time
Freq.
+ Width
Overshoot

.1.

1. . . . . . . . . . .

1........................1........................1. ..........1............1__..................

I

i

I

0.00000 see
400.0 mvolts I div
400.0 mvolts I div
200 nsee I div
290.470 nsee
1.00264 MHz
499.2S0 nsee
6.249 mvolts

!'--r-

!

:1:.......................1............ _..........1...........:............1........................1........................1

1.00000 usee
Offset
Offset
Delay
P-PVolts
Fall Time
Period
-Width
Prashoot

-964.0 mvolts
-S44.0 mvolts
0.00000 sec
912.Smvolts
297.770 nsee
997.370 nsee
498.120 nsee
6.249 mvolts

Trigger mode: Edge
On Neg. Edge on Chan1
Trigger Levels
Chan1
-964.0 mvoits
Holdoff
70.000 nsees

Honeywell

8-23

EI

STEP 6

o
o....

~

This measurement is done without the clock divider
board connected and clock jumpers inserted as shown
in the top of Figure 4. Again referring to Figures 2 an 4,
attach a 50n coax cable to the BNC connector marked
"OUT-" and another cable to "OUT+". Attach the other
end to an oscilliscope set to 50n input impedance. The
outputs should be the opposite of each other and at
approximately a 900mV amplitude. Adjust potentiometer

FIGURE 14· "OUT·" AND
"OUT+" WITH THE
CLOCK DIVIDER BOARD
INSERTED AND SET AT
+2 MODE

R36 to achieve this level. Do not adjust too far or the
signal will start deteriorating. See Figure 13. After completing step 6, remove one end of each "clock jumper"
wire and leave the other end soldered to the board.
STEP 7
Insert the clock divider board and connect the shorting
jumpers to the posts in the +2 configuration and
compare to the waveform in Figure 14.

~!~~tW+~tt~
~1:i1~:E~ri-~~~_:~f~
-1.00000 usee

Ch. 1
a
Ch. 2
•
Timebase
•
Ch. 1 Parameters
Rise Time
..
Freq.
+ Width
•
Overshoot

0.00000 sec

400.0 mvolts I div
400.0 mvolts I div
200 nsec I div
.
201.240nsec
1.00255 MHz
499.050 nsec
100.0 mvolts

1.00000 usee

Offset
Offset
Delay
P-PVolts
Fall Time
Period
-Width
Preshoot

-936.0 mvolts
-576.0 mvolts
0.00000 see
912.5 mvolts
201.350 nsee
997.460 nsee
498.410 nsee
100.0 mvolts

Trigger mode: Edge
On Neg. Edge on Chan1
Trigger Levels
Chan1
-936.0 mvolts
Holdoff
70.000 nsees

8-24

Honeywell

STEP 8
Insert the clock divider board and connect the shorting
jumpers to the posts in the +4 configuration and
compare to the waveform in Figure 15.

o
o
.....
Z



:;

II:

II

1E·09

II:

FFTTESTING:
Discrete Fourier Transform testing can be used to
evaluate the dynamic performance of an ADC for Signalto-Noise Ratio (SNR) and Harmonic distortion.
Honeywell defines Total Harmonic Distortion (THO) as
the sum of the second through the ninth (though it is
usually dominated by 2nd and 3rd) harmoniCS, and
SNR is any remaining Signal. The sum of these two
parameters is the Total Dynamic Error and it is this value
that can be used to calculate sine wave curve fit.
These parameters are excellent indicators of flash
converter performance. Signal-to-Noise Ratio is one
test that needs to be carefully watched because if
there are any glitches in the data the repeatability of the
test is poor. This test can be used with confidence

Honeywell

"'..:
0..

1E.10

1E·11

1E·12
1 E+04

1 E+05

1 E+06

1 E+07

1 E+08

1 E+09

FREQUENCY (HZ)
•

4·BIT5

A 10·BIT5

-

6·BIT5



X

12.BIT5

e 14·BIT5

8·BIT5

t A= _ _
1_
2N21Yf
N = Number of Bn.

Figure 8. Aperture Jitter Vs. Frequency
for Sine Waves

8-35

,..
o,..

~

speed converters, for sinusoidal frequencies.. The
aperture width is an integration period and the signal
will be integrated over its period. This would only
cause a filtering effect, assuming that the aperture itself
is well behaved.

Note that these voHage values will work well for any
ECl flash converter with an input that swings below
ground.

An example to determine the maximum aperture jitter
using an 8-bit flash converter: If the signal that is to be
measured is known not to contain any sinusoidal
frequencies above 10MHz, then from the graph in
Figure 8, it can be determined that to assure less than
8 bits of error due to aperture jitter alone, the ADC must
have an aperture jitter of less than 70ps. Most data
sheets do not state aperture jitter, so to be safe the
designer may wish to use a sample and hold. It may be
difficult to find sample and holds that sample that fast
Since aperture times for ADCs are usually not
specified, though for flash converters they can be very
good, it is possible to add a sample and hold to the
circuit and decrease the system performance.

Measure V2 and calculate T2'

At ECLIogicthreshold, Vi = -1.3V,

Where T1 ,;, arcsin (( V1 - Vollse! )/Ao)
00

ForVrb = -2.00VandVrt=0.Ov,
V2=2.0 ((Code No.l256)-1)
And T2 = 1/w arcsin ((V2 - Voffset)1Ao)
Aperture delay = T2 - T1
VlN

FLASH

CONVERTER

Aperture width and jitter are very difficuH to measure
because of the extremely small time periods that are in
the range of picoseconds to tens of picoseconds.
Another problem is that they are not absolute
numbers, but are random and are usually calculated
based on statistical data. However, these values are
needed to make intelligent design decisions,
especially in sample and hold selection. These values
are on the Honeywell SPT flash converter data sheets
as typical values that have been based on both
computer design simulations and verified by
characterization of samples. Aperture delay is the time
from the clock edge to the time that the sample is
taken. Aperture jitter is the time variation in the point
that the sample is taken.
Aperture delay is the delay from the time the clock is
strobed until the sample is taken. Figure 9 shows a
circuit based on driving both the clock input and the
analog input with the same sine wave. This technique
can accurately and easily measure aperture delay. It
can also be used in a system to align several different
channels in time. When using this technique be sure
to use differential signals to the clock or errors may
result
Example using the HADC771 00:
Yin = Voffset +

Ao

Choose fin = 30 MHz

Ao= .75
Voffset = -1.25V

8-36

sinwt

eLK

T..tett·up

ov _

~. ~

=-

.... -

I

I

i~

--Jf- -:--.
- -- -T.stSI",al

Figure 9. Aperture Delay Measurement

LINEARITY
Honeywell specifies both integral and differential
linearities of the flash converters.
Differential
nonlinearity is specified from an ideal 1 LSB code
width. Therefore, for a device that is specified ±1/2
LSB every code will have widths between 1/2 LSB
and 1 1/2 LSBs wide. A device specified ±314 LSB
could have code widths from 1/4 lSB to I 3/4 lSBs
wide. To have missing codes the device would need
to be specified -1 lSB or greater.
Honeywell has demonstrated the capability of producing flash converters with differential linearity in excess
of 9 bits without any type of trimming. The 10"bit converter is capable of being trimmed because a 10-bit
converter has four times the number of compar-ators
as an 8-bit flash converter. An offset error of only 2mV
in any single comparator could destroy the linearity of

Honeywell

the converter. Trimming is in the form of four aluminum
links that can be laser cut to select different resistors
that will alter the comparator offsets. This method of
trimming was chosen because no active or current
carrying structure is altered. It is either in the circuit or it
is completely deleted. This assures that there is no
affect on either long-term stability, reliability, or on
temperature performance.
Absolute linearity of converters can be adjusted by the
use of external taps. The 10-bit converter can be
adjusted by the use of seven external taps, and for the
8-bit converters either one or three taps are available
(see Figure 7). These taps can be used to cancel the
effect of the bias currents of each preamplifier (see
Figure 10). If each wafer had exactly the same betas
and absolute bias current, the ladder could be
designed to compensate for the bias currents. This
would imply that bias currents on each preamplifier
could be the same, not only from device to device, but
also from Chip to Chip. Honeywell's designs correct for
these first order effects. These effects would appear
as bows (see Figures 11 ~ & 11 B) in the linearity curve
caused by bias currents. Honeywell's correction works
very well so that at the 8-bit level this typical center tap
offset is less than a millivolt. So taps are not required to
maintain 8-bit linearity at room temperature.
External taps, for the 8-bit converters have half or
quarter scale connections and the 10-bit converter has
taps placed at eighth scale intervals to allow the user to
force the ladder.
Externally altering the ladder's
linearity, if required, is low in cost and can also be used
to change the dynamic range of the converter.
Honeywell recommends the use of the PMI OP9 or
OP11 quad op amps to force the ladder. These op
amps have the required low offset voltage and drift.
The dynamic range of the HADC77200 can be
increased by using external ladder taps to bend the
ladder and create a piecewise approximation of a curve
(Figure 12). There are two primary considerations for
this application. The first is to assure that the low end
of the scale has no missing codes due to comparator
offsets. The second consideration is to assure the
maximum ladder current specification is not exceeded.
In normal applications the ladder is referenced to a -2.0
Volt full scale. This results in an LSB of 7.8mV.
Therefore a part that is ±1/2 LSB linear will have
comparator offsets of less than half this value or 4mV.
The 100 Ohm ladder will have 20mA through it, which
is close to its maximum rated current of 25mA.
If a device was to be screened to be ±1/4 LSB then a
2mV LSB would be possible for the linearity point of
view.

Honeywell

So lets start with a 2mV LSB and geometrically
progress, doubling the LSB weight at a quarter, half
and three quarters scales, the points available on the
HADC77200. This would result in --128mV, -384mV
and -896mV taps respectively. Full scale would be at-1.920V. Current in the ladder can now be calculated
to be (1920-896mV)/25 Ohms = 41mA. This does
exceed the maximum ladder current at 25 mA. But if
the device is operated at room temperature there
should be little effect on the devices life. Starting with
a 39% lower LSB weight will soohe power problem but
initial accuracy would not be good enough to
guarantee no missing codes.

.,....
o
.,....

z
«

The above application has the ability to resolve 2mV
out of a possible 1960mV or 59.8dB of dynamic range.
If the 25mA speCification for the ladder is not to be
exceeded then the weight of an LSB cannot exceed
9.8mV. Because of comparator offsets in our process
a,n LSB should not be less than 2mV. A geometric
progression where each LSB value changes at the
quarter scale points by a factor of 1.7 times the
previous LSB value could be used. The results would
be within the above constraints of an LSB being
between 2mV and 9.8mV. The taps would then be at128mV, -345.6mV, -715.5mV and full scale would be
at -1.3444V. Dynamic range would be 56.6dB.

-,....

R1024

~

R1023

-

.2
I
N

UNEARITY DUE TO BIAS

I

IDEAL LINEARITY

N

P .1

P .1

U

U

T

T

v

v 0
o

0

L

o

T

L

~

T
A.l

-1

E

G

E

286

·2

288

512
BIT NUMBER

768

Figure 11 B. Corrected Ladder 10-Blt Flash
ADC

The coding of the flash converter is such that Vrt is full
scale. It may therefore be easier to start with the 2mV
step in the portion of the ladder between Vrb and Vr1.
The concept is the same only the taps would be
switched.
Because of their very low impedance the reference
ladders of flash converters have very high bandwidths.
This can be used to dynamically scale the input at very
high switching speeds. There is a penalty paid in the
SNR and accuracy, but this may be less than that of
using a programmable gain amplifier. It is not recommended to go below 500mV full scale range. This will
give a range changing ability of 4 to 1 when a -2.0V
reference is used.

0.0
128
345.6
715.5
1344.4
2.00
3.4
5.78
9.83
56.6
25

2.0

~
mV
mV
mV
mV
mV
mV
mV
mV
mV
dB
mA

INCREASING DYNAMIC RANGE
The dynamic range of a system can be increased by
stacking ADCs in groups of two or four. Prior to the
HADC77100, this was a very difficult task due to two

8·38

sources of error. The first error source was the static
errors of the ADCs with their linearity equal to their
number of bits yields greater resolution, but there is
still only the accuracy of the original converters plus
other errors due to offsets and differences in gain.
The accuracy of the ADCs should be at least 9 bits
accurate to form a 9-bit accurate 9-bit system. The
second error source was due to dynamic currents
flowing from the input of one converter and
perturbating the input of the other device(s).

R

SUMMARY OF RESULTS
0.0
128
384
896
1920
2.0
4.0
8.0
16.0
59.8
40

1023

T68

UNEAAlTY CUAYI: WITH TAPS FORCED TO WITHIN .5mV OF IDEAL

Figure 11A.Ladder Bow 10-Bit Flash ADC

Vrt
Vr3
Vr2
Vr1
Vrb
LSB1
LSB2
LSB3
LSB4
Dyn Range
Max Current

51>
BIT NUMBER

1023

1.5

E
R
E
N

i

1.0

v

o
L

!

0.5

G
E .25
.12

o
.50
SCALI:

HSB:

6!3:~

,,2mY

•75

Dynamic Range

=

F.S.

~c:::; =66dB

Figure 12.

Honeywell

Figure 13 shows an example of two 2-bit ADCs
connected to form a 3-bi! ADC. This example does no!
show the logic required to change the output code
from all ones to all zeros when the overrange bit goes
high. An alternative method of implementing this data
conversion is to connect the overrange bit (NOTE:
OVR goes True if Yin is greater than Vrt minus the
offsets) to the MINV and LlNV bits of each converter.
The individual bits can then be wire ORed together
and no additional logic is required. The delay of 6ns
from INV to data out must be taken into account when
setting up the timing for this method. Implementing
this circuit with N-bits is identical to the 3-bit example.
This stacking of ADCs has no adverse affect on the
data throughput; only data output delay is affected.
This method of combining ADCs does increase the
input capacitance and this must be accounted for in
selecting the input amplifier.
Stacking four ADCs is also possible. In this circuit, logic
would have to be implemented to control the data from
the overrange bits to the outputs. This circuit may
have an additional clock delay to the output.
SPT can custom manufacture any of the HADC77100
family for use in stacked applications. These ADCs
would then have the correct logic coding at the
outputs so that additional logic and their associated
delays would not be present.

INCREASING SAMPLE RATE
The sample rate of a system can often be increased by
combining two flash ADCs with their clocks connected
out of phase (this is known as ping-ponging) as shown
in Figure 14. This technique works especially well with
the HADC77100 because of several of its performance
parameters. First, the greatly reduced kick-back allows
both converters to be driven from the same buffer or
amplifier without one converter affecting the other.
This eliminates any problems that may arise from different frequency responses of separate amplifiers. Other
advantages are that the excellent linearity of the
HADC77100 or HADC77200 will enable the design of
a true 8-bit system with sample rates of over 250M Hz.
The data would then be available on two separate
busses, a useful feature for data rates in excess of
100MHz. By using the HADC77200 data could be easily clocked into memory or onto the data bus by using
the Data Ready output.
The best advantage to using Honeywell flash
converters in these applications is that they only
require a single clock that has an ideal 50% duty cycle.
This eases deSign by eliminating the need for delay
lines in generating the timing signals.

VFS. Vraf

OVRUA··

0
0
0
0
1

§
.llmI..

MSS··A··

0
0
1
1
0

LSSUA··

0
1
0
1
0

VOLTS

-2.00
-1.75
-1.50
-1.25
>-1.00

EI

li!

2

is

8

....
.

w

CONVERTER B

OVRUS U

:l!
0

E
~

ANALOG
INPUT

Honeywell

(N + 1).BIT

OUTPUT

0
0
0
0
1

MSSUS··

0
0
1
1
0

LSBUSU

0
1
0
1
0

VOLTS

-1.00
-.75
·.50
-.25
>0.0

Figure 13. Stacking Two ADC's to Double Dynamic Range

8-39

DATE OUT "A"

,fa

,...
o
,...

~

I

I

HADC77100

ANALOG1N

C1.K

o.OV

cue

·I.OV
·Z.OV

I

V.. VRT V... VR.

HADC77100

fa

I

DATA OUT "S"

Figure 14. Ping Pong 2 ADC's for 2X Sample Rate

8·40

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES
EB101 EVALUATION BOARDs-BIT, 150 MSPS FLASH AID CONVERTER
AND S-BIT, 165 TO 400 MWPS RASTER D/A CONVERTER WITH REFERENCE
by Tom DeLurio Senior Applications Engineer
FEATURES

APPLICATIONS

0150 MSPS MINIMUM CONVERSION RATE·
070 MHz Full Scale input Bandwidth
o 1/2 lSB Integral Linearity (Adjustable with three
reference ladder taps)
o low Clock Duty Cycle Sensitivity (Adjustable)
o Preamp Comparator DesigntOptionallnput Buffer
o ECl clock produced from any signal generator
o Improved D/A Output Drive, Doubly-Terminated son

Evaluation of HADC77200 AID Converter
Evaluation of HDAC1 0181/S1400 D/A Converters
o High Definition Video
o Digital Oscilliscopes
o Transient Capture
o Radar,EW
o Direct RF Down-conversion
o Medical Electronics: Ultrasound, CAT Instrumentation
o

o

GENERAL DESCRIPTION
The EB101 Evaluation Board is intended to show the
performance of Honeywell Inc.'s Signal Processing
Technologies HADC77200AlB flash AID converter and
the HDAC10181A1B or HDACS4100 Ultra High Speed
D/A converters. The board provides for either the ADC
or DAC to be tested together or separately. Included on
the unit are two 100K ECl multiplexers for data routing
between the AID and D/A or on and off the board as
shown in the block diagram below.
The HADC77200AlB is a monolithic flash AID converter
capable of digitizing a 2 Volt analog input signal with full
scale frequency components to 70 MHz into 8-bit digital
words at a minimum 150 MSPS update rate. For most
applications, no external sample-and-hold is required for
accurate conversion due to the device's wide bandwidth.
The HDACS1400 and HDAC10181A1B are monolithic 8bit D/A converters capable of converting data at rates of
400, 27S, and 165 MWPS respectively. The parts have

BLOCK DIAGRAM

optional video controls and can directly drive doublyterminated SO or 7Sn loads to standard composite video
levels. The DACs have an internal reference to supply
themselves and the HADC77200 with a stable voltage
reference and gain control for different output voltage
swings.
The HCMP96870 is a high speed dual differential voltage comparator used to generate an ECl compatible
clock signal from any type signal generator.
The board is in Eurocard format with a 54-pin dual height
DIN connector for digital data. The analog inputs, outputs and clock input are standard son BNC connectors.
Tektronix high impedance probe jacks are provided to
monitor the clock lines. Standard -S.2V, +SV, and ±12 to
±1S Volt power supplies are required for operation of
the EB101, with nominal power dissipation of less than
11 Watts. The board comes fully assembled, calibrated
and tested. An optional input buffer board is available for
high performance applications and is explained in more
detail on the following pages.

REfERENCE AND

fUiFEAEHCE OU~TPU.::.:.T.J....-..,

LIHfARITYAD.IUsr

F1001"
REGISTERI

""LTIPLEXEA

HDACt011tAoe
OR
HDACi1400

DlFFeAENTIALOR
81NQLEENOEO

OUTPUT

• •
MJ
OUT

Honeywell

...
IN

8-41

GENERAL INFORMATION
C\I

o
.....
~

The EB101 evaluation board is a fully assembled and
tested circuit board designed to aid in the evaluation of
Honeywell's HADC77200 8-bit AID converter, HDAC10181/541008-bit D/A converters and HCMP96870
dual comparator. The board contains circuitry for buffering the input signals, generating .reference voltages,
dividing the DAC and multiplexer clocks, routing input I
output data, and generating ECl level differential clock
signals from any signal generator. All digital inputs and
outputs are 10KH and 100K ECl compatible and provisions are made for gain, offset and linearity adjustments. The board requires -5.2, +5 and ±12 to ±15 Volt
supplies.
The EB101 evaluation board consists of seven functional sections that include an analog input buffer, AID
converter, inpuUoutput multiplexer and data latches, D/A
converter, reference voltage generator, ECl clock generator, and ECl clock divider. The analog and digital
grounds are separated on the board for better system
grounding characteristics.
There are numerous jumper options available to switch
sections in or out of the system to suit individual needs.
The clock divider circuitry is on a separate board that
plugs into the main board to provide divide by 2 or 4 for
the multiplexer and DAC. The jumper options will be
discussed in more detail in the following sections. In
addition, 90MHz low pass input and output filters are on
board.

ON BOARD ANALOG INPUT BUFFER

OPTIONAL ANALOG INPUT BUFFER BOARD·
EB102
An alternate and higher performance input buffer is
available as an option and sold separately. The EB102 is
intended for users operating at the top end of the input
bandwidth range of the HADC77200. The reason for a
separate board is that the amplifiers utilized are quite a bit
more expensive then the "on-board" buffer. But, with
the added expense, increased input bandwidth with less
harmonic distortion is realized.
There are two versions of the EB102 buffer board, one
with a wideband op-amp (ClC221) and one with a
wideband buffer amplifier (ClC231). Both versions are
identical but are jumpered to provide for the different
amplifier pinouts (See FigtJf'e 1A). The ClC221 version
has the advantage of being configured up to a gain of 50
as required, and has slightly better harmonic distortion
specifications. The ClC231 version has the advantage
of a much higher output drive current and better settling
time.
The Following table shows a breakdown of some of the
more important specifications:
TABLE 1 • COMPARISON OF COMllNEAR
ClC221/31 AMPLIFIERS
SPECIFICATION

ClC221

ClC231

Gain Range

±1 to 50

±1 t05

Output (V, mAl

±12,500

±11,100

6500

3000

-3dB Bandwidth (Av=2)

275M Hz

165MHz

Settling Time (nsec, %)

15,0.1
18,0.02

12,0.1
15,0.05

-58

-55
-59

This section consists of a 90MHz low pass filter, HA2539
high frequency op-amp, and a 2N5836 rf transistor. The
input impedance is 500 and the gain is set at 2X so that a
1 Volt input can be applied. Compensation components
are provided and can be adjusted for the desired
frequency range needed. The compensation is factory
adjusted for 50MHz bandwidth operation. The. bandwidth of the buffer amplifier can be increased by decreasing the gain to 1X by changing the 1.5kO feedback
resistor to 7500. The BNC· connector shown in the
schematics and layout near the output of the buffer can
be used for monitoring the buffer output and input to the
HADC77200. The BNC should be connected to a 500
terminated oscilliscope and will provide a 10X attenuated
signal.

100K ECl CLOCK GENERATOR

The positive input to the HA2539 is tied to an offset
adjust to center the input signal to the HADC77200
around -W , which is needed if a 2Vp-p input signal is
applied. The input buffer can be bypassed by removing
the 6.80 resistor at the emitter of the 2N5836 and the
4500 resistor between the BNC connector and the
HADC77200. Bypass the 4500 resistor with a jumper
wire and the HADC77200 can now be driven directly.
The input impedance is 4KO in· parallel with a 56pF
distributed capacitance.

The ECl clock section consists of an HCMP96870 dual
comparator, duty cycle and hysteresis adjust, F100131
triple 0 flip-flop and several jumper options. Any type
high frequency signal generator can be connected to
the BNC input to the comparators. Both inputs to the
dual comparators are connected to the BNC. There are
four outputs which generate differential 100K ECl clock
signals. One set goes directly to the HADC77200 while
the other two can go to the F100155 multiplexers and
HDAC10181/51400 or to the clock divider circuitry.

8-42

Slew Rate (V/J.l.Sec)

Harmonic(dBc)
Distortion

Second
Third

-62

Honeywell

FIGURE 1A· DETAilED SCHEMATIC OF THE
EB102 BUFFER BOARD USING THE
COMllNEAR ClC221131 AMPLIFIERS

1N4001

;

FEMALE·T().FEMALE
5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ,

•• , .

.
.
.
.
... , ..............................................
.

CENTER 16.75 MHz
AB 300 KHz
VB 300 KHz

SPAN 30.07 MHz
·ST 50.00 msec

DAC OUTPUT SPECTRUM ANALYSIS OF A 10MHz INPUT FUNDAMENTAL
WITH A 10.7MHz (PLP'10.7) OUTPUT LOW PASS FILTER AND 100MHz CLOCK RATE

8·46

Honeywell

PLP
oaseA01

PASSBAND, MHz

lco,MHz

STOP BAND, MHz

VSWR,

MODEL

(loss < 1dB)

(loss3dB)

(loss> 2OdB) (loss> 4OdB)

Passband Stopband

NO.

Min.

Nom.

Min.

Typ.

Typ.
1.7

PLP-l0.7

00-11

14

19

24

200

1.7

PLP-50

00-48

55

70

90

200

1.7

17

PLP-70

00.00

67

90

117

300

1.7

17

PLP-l00

00-98

108

146

189

400

1.7

17

Oaseno.

A01

A

Max.

Max.

A

B

0

0

F

E

G

H

J

K

.770

.800

.385

.400

.370

.400

.200

.20

.14

.031

19.56

20.32

9.78

10.16

9.40

10.16

5.08

5.08

3.56

.79

lETTER M OVER PIN 2
MCl

TOP VIEW

KDIA.
TYP.

~G~

i

--

~-

F

f ~I+-_

!

A
B

NOTE: BLACK BEAD INDICATES
PIN 1. PIN NUMBERS DO NOT
APPEAR ON UNIT. FOR
REFERENCE ONLY.

~

PIN CONNECTIONS
SEE CASE STYLE OUTLINE DRAWING
GROUND

2,3,4,5,6,7

Honeywell

8-47

AN102
(J)
To Power Bus

""

. .y

(J)

FIGURE 2 - DETAILED SCHEMATIC OF EB101, REVISION C

To DigftaJ Ground Plane

ToPOW8IBus

=
=
=

1-

if~
-t122M

D5.,K1l

. . . l8al3QQ (220030)
ECL TennlnatlOO"-'

,J".

Digital Ground

oJ,

Analog Ground

~

AN BNC connectors . . son
TROMPETER CBJ20

.i
-5.'ZV

LisanECLIow

Hlaan ECL high

-

lN9l'

L- RF _ _ (FAIR-RITE 1"11274300111112)
For RF frequency _119 0I11f1o SUflPII' pi.. and
_
AGND and DGND_

FIGURE 3· TIMING DIAGRAM

CLK

DATA LATCHED ON
7:200 OUTPUT PINS N

HADC77200
OUTPUT DATA

CLKTO EAND EON
THE F100155 AND THE
F1 00155 RESPONSE

F1 00155 OUPUT TO
HDAC10181/54100

LATCHED

TRANSPARENT

DATA VALID
AT 100155 OUTPUT N-1

DATA LATCHED ON
77200 OUTPUT PINS N+ 1

LATCHED

DATA VALID
AT 100155 OUTPUT

TRANSPARENT

N

LATCHED

DATA VALID
AT 100155 OUTPUT N+1

F100155 OUTPUT
CONDITION TO THE
HDAC10181/54100

HDAC10181/54100
ANALOG OUTPUT

Honeywell

8-49

~

,..

FIGURE 3 CONTINUED 10181151400 TIMING DIAGRAM

~

OV-----------------r----~---------------------------

CONY

-1.3V ---tE---'"*----"*----+---*""-~f_--____if_-_il:_-CONY

OV
-1.3V -

f,:------~----~f----I.

~
~

DATA CONTROL
INPUTS

OUT+
Y,LSB

8·50

Honeywell

-

CLOCK JUMPERS

0--'0

0"'-0
-;,-

C\I

o
,...

~

4.600

7.000

D

~:~

DIN

n ""'" .....
'""
UC
.1

I

E
U
R

...

•

oC
A

R

-~ ~
•

R

~

OOUT+
FIGURE 4A - MAIN BOARD LAYOUT AND COMPONENT POSITION

(NotTo Scale)

.Honeywell

8·51

HDAC1 0181 AlB

I

JUMPER
SETTINGS

JUMPER
SETTINGS

~~
010

I

~
---c:::t-

-c:::::J-

I

HDAC51400

"'1J

I

"'1J
I

.....

0
0

EDGE OF THE PC BOARD

I

0210

"'1J

I

"'1J
I

.....
0
0

EDGE OF THE PC BOARD

FIGURE 4B • JUMPER POSITION AND CONNECTIONS FOR EITHER THE
HDAC10181A1B OR HDAC51400
(Not To Scale)

8·52

Honeywell

2.000

3.000

-5.2

elK
100131

FIGURE 5 - CLOCK DIVIDER BOARD LAYOUT AND COMPONENT POSITION
(NotTo Scale)

Honeywell

8·53

EB101 REVISION C PARTS LIST
PARTS LIST

'"o,...

NO.

~

1
2
3
4
5
6
7
8
9.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42

QTY.

OESCRIPnON
FERRITE BEAD
DIODE
DIODE
TRANSISTOR
I.C.
I.C.
I.C.
I.C.
I.C.
I.C.
FILTER
RESISTOR
RESISTOR
RESISTOR
RESISTOR
SIP RESISTOR PACK
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
RESISTOR
POTENTIOMETER

11
4
3
1
1
1
2
2
1
3
1
1
1
11
5
4
4
2
3
3
1
1
1
1
2

POTENTIOMETER
CONNECTOR. DIN
CONNECTOR
CAPACITOR, CHIP
CAPACITOR
CAPACITOR
CAPACITOR, ADJ
CONNECTOR, BNC
TEST POINTS
PIN RECEPTACLE
PIN SOCKET
SOCKET, 24PIN
PRINTED CIRCUIT BOARD
TEST POINTS
CAPACITOR
JUMPER PINS

8
1
1
16
10
29
1
5
2
42
9
1
1
2
2
18

j

MANUFA

II

.0

00

G. AGd.-o

00

~VIE

00

AN103

TABLE 4 • POWER DISSIPATION

POWER SUPPLY CONNECTIONS

EB103A

Power to the EB103 is supplied through a nine pin Molex
type connector. The supply lines are color coded as shown
in Flgure5. Connect the wire end of the power supply
harness to power supplies as shown by Figure 5 and the
silk screen near the mating connector on the PC board
itself. The power harness is attached to the board with the
bevelled edges and hollow connector alligned to the mating
connector.
The power requirements forthe EB1 03 at different supplies
is shown in Table 4. When powering up the board, check
to see if the current draw from each supply is equivalent to
the numbers in the table. If there is a large difference, then
recheck your connections. SyP$)ly protect jon diodes are on
the board for any reverse polarity connection byt oyer¥OHage protection is not provided

Current

Power

+15V

.065A

.975W

-15V

.061A

.915W

+5V

.013A

.065W

-5.2V (DVEE)

4.5A

23.4W

-5.2V (AVEE)

.878A

4.56W

Voltage

29.9W

DO NOT TURN ON THE POWER UNTIL ALL
LEADS ARE CONNECTED TO THE SUPPUES
AND THE HARNESS IS ON THE BOARD!!

BLACK DGND

BLACK DGND
WHITE +5V

WHITE -5.2V (DVEE)

RED -15V

BLACK AGND

2
RED +15V

WHITE -5.2V (AVEE)

3
BLACK DGND

@@@

@@@
@@@
BOTTOM

FIGURE 6 • POWER SUPPLY HARNESS CONFIGURATION

8-76

Honeywell

FIGURE 7 - TIMING DIAGRAMS

EB103 TIMING
DIAGRAM
ClK TO #1
HADC77200/300
ClK TO #2
HADC77200/300
td

#1
HADC77200
OUTPUT DATA

DATA lATCHED ON
77200 OUTPUT PINS
" N

DATA lATCHED ON
77200 OUTPUT PINS

N+1

: :
: :

~

i

i!
: :
~ !

#2
HADC77200
OUTPUT DATA

DATi\'lATCHED bN
77200 OUTPUT PINS
,N

DATA lATCHED ON
77200 OUTPUT PINS
N+1

: :

i: i:

DATA READY (DREAD)
TO SELECT ON THE
F100155 AND THE
RESPONSE
F100155 OUTPUT
CONDITION TO THE
HDAC54100

ClK TO HDAC51400
HDAC51400
ANALOG OUTPUT

EI

tPWH

~--------------;-----+---------------------------

HDAC51400
TIMING DIAGRAM

·,.3V --~F.---",*----*-----:IIE----7f.----:N'----*----*""---CONV

·
".3V

E_IS~

~

DATA CONTROL INPUTS

lOST

~'-------

•

lOSe

------

I"" rv-V'-.. . . . . . .

t

-

-

OUT·

OUT.

1J2LSB

Honeywell

---

lSI

8·77

PASSBAND,MHz

leo, MHz

MODEL

(loss < ldB)

(loss3dB)

NO.

Min.

Nom.

Max.

VSWR,

(loss> 4OdB)

Passband Stopband

Max.

Min.

Typ.

Typ.

PLP-l0.7

DC-II

14

19

24

200

1.7

1.7

PLP-50

DC-48

55

70

90

200

1.7

17

PLP-70

DC-60

87

90

117

300

1.7

17

PLP-l00

DC-98

108

146

189

400

1.7

17

PLP-l50

DC-l40

155

210

300

800

1.7

17

PLP-200

DC-l90

210

290

390

800

1.7

17

Case no.

A01

A

STOP BAND, MHz
(loss> 2OdB)

A

B

C

D

E

H

G

F

J

K

.770

.800

.385

.400

.a70

.400

.200

.20

.14

.031

19.56

20.32

9.78

10.18

9.40

10.16

5.08

5.08

3.56

.79

lETTER M OVER PIN 2
Mel

TOP VIEW

K DIA.
TYP.

!

E

--r

G

F
2

4

6
A

i

8

~

NOTE: BLACK BEAD INDICATES
PIN 1. PIN NUMBERS DO NOT
APPEAR ON UNIT. FOR
REFERENCE ONLY.

~

--r

J

it

PIN CONNECTIONS
SEE CASE STYLE OUTLINE DRAWING
GROUND

2, 3, 4, 5, 6, 7

FIGURE 8 - LOW PASS FILTERS

8-78

Honeywell

PIN FUNCTIONS HADC77200/300
FUNCTION

NAME

FUNCTION

NAME

('I)

DRINV

Data Ready Inverse

CLK

Inverse ECL Clock Input Pin

0

LlNV

DO through D7 Output
Inversion Control Pin

CLK

ECL Clock Input Pin

- MUXlBUFF

!..21

SECTION

-20
'19
18

~'7

DO T

/

16

Free-Running Operation

By connecting the STATUS output of Jack J2 to the
RIC input of Jack J2, the HADC574/674Z self
triggers. That is, at the end of a conversion , when
STATUS goes to logic low, this automaticly triggers
the device for another conversion. Figure 5 shows
the resultant wave form of the STATUS line when
using the HADC574Z. The HADC674Z gives similar
results except that conversion time is 15 jlS
maximum. Note that the <200 nS STATUS logic low
time is not sufficiently long enough for an external
sample/hold amp control.
The EB104 is preconfigured for free-running operation.

FIGURE 6
WIRING DIAGRAM OF D/A SECTION
OUTPUT

JUMPER
POSTS
E19-E20
E21-E22
E23-E24
E25-E26

OUTPUT FORMAT
*12BITS

8-BITS

OPEN
OPEN
OPEN
OPEN

CLOSED
CLOSED
CLOSED
CLOSED

* EB104 AS DELIVERED

TABLE 6
JUMPER POSTS SELECTION
FOR OUTPUT MODE PROGRAMMING

Honeywell

8-95

z
«

calibration

<0

....o

~

The HADC5741674Z is manufactured to have only a
few LSB'sof zero offset and a fraction of a percentage
of full scale error, depending on grade. In addition,
inaccuracies in the StH amp, if used, will contribute to
the inaccuracy of the AID Conversion Section. The
EB104 includes trim potentiometers for zero and full
scale adjustment to compensate for these errors
which are pre-adjusted for the pre-configured
operation. Shipping may effect the adjustments and
alter the calibration. Re-calibration will be needed
when the input range is changed, when the StH amp
utilization is changed, or when .any components are
replaced in this section.
Calibration involves the adjustment of the devices
offset and gain. Adjustment is made so that the
output of "zero" (0000 0000 0000) and "full scale"
(1111 1111 1111) code values are received when the
analog input's negative-most and positive-most
values are input. In practice, accurate calibration is
acheived by calibrating the "zero" point with an analog
input voltage the equivalent of 1t2 LSB above the
desired zero setting; the zero trimming is then set
between the 0000 0000 0000 and 0000 0000 0001
output transition.
Full scale calibration is then
acheived similarly with an analog input 1t2 LSB below
the maximum range; the gain trimming is then set
between the 1111 1111 1111 and 1111 1111 1110
output transitions.

INPUT RANGE
saECTED
·0·10V
0-20 V
±5V
±10V

'ZERO"
CALIBRATION
VOLTAGE
1.22 mV
2.44mV
·4.9988 V
·9.9976 V

'ZERO"
TRIM
POTENTIOMETER
R6
R6
R3
R3

"FULL SCALE"
CALIBRATION
VOLTAGE
9.9963 V
19.9927 V
4.9963 V
9.9927 V

• EB104 RANGE AS DELIVERED

TABLE 7
HADC574Z CALIBRATION VOLTAGES
5) Connect logic monitor to AID data output jack J3.
(This can be accomplished with a logic analyzer
connected to Jack J3 or by determining the logic
value of each pin with a voltmeter or oscilloscope.)
6)
Set voltage source to zero calibration value.
indicated by Table 7.
7) Adjust zero trim potentiometer indicated by Table
7. Set to point where flickering occures between
0000 0000 0000 and 0000 0000 0001; both codes
should occure equally. (If using a scope or volt meter,
monitor pin BO of Jack J3, the LSB; ensure pin B2B11 are still zero and not fUckering.)
8) Set voltage source to full scale calibration value
indicated by Table 7.

To calibrate the AID section of the EB104 using the
approach described above, use the following
procedure:

9) Adjust gain trim potentiometer R2. Set to point
where flickering occures between 1111 1111 1111
and 1111 1111 1110; again equal occurences of
code should exist.

1) Select StH amp utilization and input range mode.

The AID section is now calibrated and ready for use.

2) Apply power supplies.

Component Selection

3) If using StH amp, adjust zero offset trim of StH amp
if not already done.

The EB104 can be used for the evaluation and
comparison of similar component types. In addition to
the hold capacitor discussed earlier, both the external
StH amp and HADC574t674Z can be replaced with
other devices. The HA2425 supplied on the board
can be replaced with an HA2420, AD583, SMP-81, or
SHM-IC-1. The HADC574t674Z can also be replaced
with alternate pin compatible devices for evaluation
and comparison purposes. Athough pin 11 of the
HADC574t674Z is not internally connected, -15 volts
is supplied to the socket pad for the VEE requirement
of alternate, pin compatible devices from other
manufacturers.

4) Apply an accurate programmable voltage source to
EB1 04 Analog Input (Jack J5).
(A suitable method to accomplish this is with a variable
power supply in parallel with a digital voltmeter.
Voltage setting should be accurate to within 0.5 mV,
which is about 1t4 LSB in the 0-10 or ±5 volt range. A
potentiometer maybe required to divide and trim the
input reference voltage. Noise should .also be kept
low, less than 1 mV if possible. Accuracy of voltage
source and level of noise will affect acheivable
calibration.)

8-96

Honeywell

MULTIPLIER/BUFFER SECTION
This section drives bolth the DigitaVAnalog
Conversion Section and Data Output Jack J4. Input
into this section is selectable from either the
Analog/Digital Converstion Section or Data Input Jack
J3. This allows the Analog/Digital and Digital/Analog
Conversion Sections to be linked and operated
together or operated separately. Digital code can be
output from the HADC574/674Z through Jack J4, or
data can be input directly to the HDAC7545A. All data
input or output from this section is buffered. A block
diagram of the Multiplier/Buffer Section is shown in
Figure 7.

OPERATION
With a logic low into the SELECT input of Control Line
Jack J2, the HADC574/674Z output data is selected;
a logic high selects the data input into Jack J3. The
STROBE input allows input data to be transferred with
a logic low condition, and blocks data transfer with a
logic high condition. This is shown in Table 8,
Multiplexer/Buffer Section Logic Control. A Berg
jumper can be used at Jack J2 to tie either the
SELECT or STROBE input low (ground).
The Multiplexer/Buffer Section consists of three
74LS157 devices each of which is a quadruple 2-line-

INPUTS
SELECT

STROBE

H
L
L

X
H
L

co

OUTPUT
(12 BITS)

....o

~

ALL OUTPUTS LOGIC LOW
DATA INPUT JACK J2 SELECTED
"AID CONVERTER OUTPUT SELECTED

'JUMPERED CONDITION AS DELIVERED

TABLE 8
MULTIPLEXER/BUFFER SECTION LOGIC
CONTROL
to-1-line data selector/multiplexer. The Strobe inputs
and Select inputs of the three devices are tied
together and controlled by the STROBE and SELECT
Device compensation is
input pins of Jack J2.
achieved with a Q-Pak™ chip capacitor under each
device. Pinout of the 74LS157 and it's logic truth
table is shown in the appendix.

Device Selection
The CMOS equivalent of the 74LS157 can be used in
place of the bipolar devices. This will provide the
advantage of reduced power supply current, but
output drive will be reduced.

DATA INPUT JACK J3

AID
CONVERSION
..,.c----,
SECTION

FIGURE 7
MULTIPLEXER/BUFFER SECTION BLOCK DIAGRAM

Honeywell

8-97

DIGITAUANALOG CONVERSION SECTION
<0

o
,..

~

The heart Of this section is the HDAC7545A current
output digital-to-analog converter.
Parallel code
received from the Buffer-Multiplexer section is input
into it's internal input register and can be latched. The
HOA7545Aoutputs a signal current corresponding to
the 12-bitcode residing in the input register. . The
analog current output of the OAC is converted to a
voltage by the external op amp(s) in combination with
internal resistor Rfeedback.
DATA INPUT AND LOGIC CONTROL

es

Input logic pins
and WR control HOAC7545A
operation and are available on the EB104 at the
Control Line Jack J4. Pins ~ and WR control the
loading of the input register; when both pins are low,
data at the input logic pins OBO-OB11 is transferred
into the input register. When ~ and/or WR goes
high, the input register is locked and retains the last
code condition.
C;S and ~ can be tied low
(grounded with Berg jumpers at J4) so that all input
codes are immediately converted; this is not a good
approach if a smooth continuous output is desired.
Commonly, and by pin definition, pin ~ is used for
chip selection and WR for writing data into the input
register.

The simplest method for loading the HOAC7545A on
the EB104 is to ground ~ with a Berg jumper.
Loading the input register is accomplished with a
negative pulse Qn WR (100 nS minimum).
In th_9 pre-configured hook up of the EB104, pin ~ Is
Jumpered to ground and pin WR is connected to the
STATUS output of the HAOC574Z which is in free-run
operation. As shown in Figure 9, the typical timing .of
the HAOC574Z and HOAC7545A allows this
configuration to function.
Output data from the
HAOC574Z is transferred to the HOAC7545A via the
Multiplexer/Buffer section.
HADC574Z'S STATUS OUTPUTI
HDAC7545A'S V'IIfINPUT

~ <200na
DATA

HADC574Z'S DATA-OUTPUTS!
HDAC7545A'S DATA INPUTS

,U

l

~
I-

~

300-1000 nS
~>25nS

574 CONVERSION
CYCLE (25 fIB MAX)

FIGURE 9
TIMING RELATIONSHIP BETWEEN
HADC574Z AND HDAC7545A
IN PRE-CONFIGURED OPERATION

R11
2DK
1%

'---------·~2~D~R1~O~~------._----------+_----------_,

,

.--+-.AI\,....-..o

R FEEDBACK ..,

VREF
R16 1M

VREFFROM

AID SEClION

OUT1

0'1!...-~-I

HDAC7545A

E3

33

DIA DATA
FROM BUFF/MUX

12

,
,

'----...,7~t--_~O

DBD·DB11

OFFSET

ADJUST

NOTES: ALL RESISTOR VALUES IN OHMS
1% RESISTORS 50 PPIN"C
R9 AND R18 100 PPMI'C

+15V @E~II@D-~ ·15V

FIGURES
SIMPLIFIED WIRING DIAGRAM
OF DIGITAUANALOG CONVERSION SECTON

8-98

Honeywell

OUTPUT MODE SELECTION
Berg jumpers allow the selection of either a unipolar or
bipolar voltage output from the Digital/Analog
Conversion Section. In unipolar operation, a single
op amp (U7) is used in an inverted unity gain
configuration to provide an inverted 0 to -10 volt
output, corresponding to full scale input codes 0000
In
0000 0000 to 1111 1111 1111, respectively.
bipolar operation, both op amps (U6 and U7) are used
to provide a non-inverted -10 to 10 volt output,
corresponding to codes 0000 0000 0000 to 1111
1111' 1111; 0 volts results from code 1000 0000
0000. The jumper configuration for output mode
selection is summarized in Table 9.

D/A SECTION OUTPUT RANGE
JUMPER
POSTS
E30-E31
E32-E34
E33-E35

-10TOOV
(UNIPOLAR)

-10TO+10V
'(BIPOLAR)

OPEN
CLOSED
OPEN

CLOSED
OPEN
CLOSED

, EB104 RANGE AS DELIVERED

Calibration Procedure
During calibration, all voltage measurements are taken
from the Analog Output Jack J6. For a more accurate
calibration, output noise is reduced by disabling the
HAD574/674Z and forcing the input conditions
through Data Input Jack J3; On Jack J2, jumper pins
CE and SELECT to ground which will disable the
HADC574/674Z and select input data from Jack J3.
Also jumper pins WR and CS on Jack J2 to ground
which will result in continuous conversion.
Unipolar Output Mode Calibration
1) Ensure EB1 04 is configured for Unipolar Output
Mode.
2) Input 0000 0000 0000 into Jack J3.
3) Adjust offset trim potentiometer R15 until 0 Volts is
obtained. (2.44 mV represents 1 LSB error)
4) Input 111111111111 into Jack J3.
5) Adjust Vref gain adjustment R9 until-1 0 Volts is
obtained.
This completes the calibration for unipolar output
operation.
Bipolar Output Mode Calibration

TABLE 9
EB104 ANALOG OUTPUT RANGE OPTIONS
AND JUMPER POST PROGRAMMING

CALIBRATION
The EB104 is delivered pre-calibrated and ready to
operate. However, due to vibration during shipment,
recalibration may be necessary in order to obtain the
1/2 LSB accuracy achievable with the HDAC7545A.
Calibration will again be necessary following any
component replacement in the Digital/Analog
Conversion Section with few exceptions, and also
when changing between unipolar and bipolar modes.
As discussed later in the Trim and Gain Component
section, the gain determining resistors used for
bipolar operation are of a readily-available 1% accuracy
variety. This can represent a 2% gain inaccuracy or an
80 LSB error (out of 4096 LSB's total). Therefore,
when adjusting the trimming for a fraction of an LSB,
the adjustment is "touchy" and can drift an entire LSB
over an ambient temperature change of several
degrees Celsius. Refer to the Component Selection
section if additional temperature stability is desired.

Honeywell

1) Perform steps 1 through 3 of Unipolar Output
Mode Calibration
2) Disconnect Jumpers E33-E35 and E34-E35;
Connect E30-E31.
3) Short pins 2 and 3 of U6 to ground.
4) Adjust offset trim potentiometer R8 until 0 volts is
obtained; due to the high gainofthe amplifier, it will
be nearly impossible to actually obtain 0 volts;
adjusting R8 so that the output polarity just
changes is sufficient.
5) Connect Jumper E33-E35.
6) Input 0000 0000 0000 into Jack J3.
7) Adjust gain trim potentiometer R16 until-1 0 Volts is
obtained. (4.88 mV represents 1 LSB error)
8) Input 1111 1111 1111 into Jack J3.
9) Adjust Vref trim potentiometer R9 until +10 Volts is
obtained.
10) Repeat steps 6 though 9 and readjust if
necessary.
This completes the calibration for bipolar output
operation.

8·99

co

a
,..
z

«

D/A SECTION COMPONENT SELECTION

unipolar output operation, bipolar output operation
gain error also needs to be considered.

Output and Trim Resistors
<0

o
,..
~

In conjunction with external op amp U7, the
resistance of Rfeedback in series with R10 is used to
convert the DAC output current to a voltage.
Additionally, in bipolar output mode a summation
circuit composed of op amp US and external resistors
is used to combine Vref with the generated output
voltage. Trim resistors are included to adjust for offset
and full scale errors in the HDAC7545A, the Vref
error, and in bipolar output mode, the resistor ratio
error of the gain stage incorporating op amp US. The
component selection for unipolar output mode will be
discussed first.
The worst-case gain error tolerance of the lowestgrade HDAC7545A is ±4 LSB or approximately
±0.1%. The maximum error of the Vref, derived from
the HADC574, is approximately ±0.1%. Therefore,
when using unipolar output mode, the gain
adjustment will need to be ±O.2% to cover worst case
error.
In the HDAC7545A, the resistance of
Rfeedback and the resistance into VREF is typically
12.5 Kn but can be as high as 18 Kn. For trim
purposes, R10 adds to Rfeedback and R9
(potentiometer) adds to the input resistance of Vref.
Working out the gain equation using 18 Kn as internal
resistance (worse case) it is found that R10 needs to
be 3S n minimum and R9 twice the R10 value
(minimum) to provide the needed ±O.2% adjustment.
The best control of adjustment and stability for
unipolar output operation is achieved by using the
resistance values derived above. Even lower values
can be used if a better grade HDAC7545A is used
and/or VREF voltage is better controlled. Actual
values used on the EB104 are larger: R10 is 301 n
and R9 Is 0 to 1000 n. These increased values are
necessary to allow calibration in bipolar mode as
discussed below.
In bipolar mode, the gain stage consisting of op amp
US is configured to gain and sum Vref and the
unipolar output of the DAC; (-1)o(Vref)+(-2)o(Unipolar
Out). (Recall that the unipolar output is inverted.)
When 0000 0000 0000 is input, the unipolar output is
zero and contributes nothing; the output is therefore
(-10V)+(-2)o(0)=-10 Volts When 1111 1111 1111 is
input, the output is (-10V)+(-2)o(-10V)=+10 Volts.
The accuracy of the (-1) and (-2) gains directly affect
final accuracy. In addition to the errors discussed in

8-100

Because of relative ease of availability and to therefore
demonstrate a practical Circuit, the EB104 Is supplied
with fixed gain resistors of 1 % accuracy. Therefore,
±2"k worst case gain inaccuracies can be expected.
The gain adjustment of the (-2)o(Vref) product is first
considered. To allow calibration over the maximum
±2"k error range, R1S (feedback reSistance) consists
of a 21 Kn (1%) resistor in parallel with a 1 Mn
potentiometer; R11 (input resistance) consists of a 20
Kn (1%) resistor. Working out the gain equations
with nominal resistance values, this allows a gain
adjustment from -00 to +2.8% over unity. Considering
worst-case resistor values, this leaves 0.8% for
compensation of Vref error.
The gain of the (-1)o(Unipolar Out) product is next
considered. This product, again due to the summing
amp resistor tolerances, can also vary ±2"/o; this is due
to the the 1% tolerance of R12 combined with the
trimmed R1S. The Error is compensated by the same
adjustment made in unipolar operation; by adjustment
of R9 to change the HDAC7545A output gain.
However, the 0.2% adjustment allowed earlier needs
to be increased to ±2% to compensate for summing
amp gain error. By working out the gain equations, it is
found that increasing R9 to 3S0 ohms and R9 to about
720 provides the desired range. Practically, however,
due to typical values of HDAC7545A Vref and
Rfeedback resistance and available resistance values,
component values of 301 nand 1 Kn were chosen
for R10 and R9, respectively.
Temperature coefficient of the chosen gain
determining resistors is 50 ppm and 100 ppm for the
fixed resistors and potentiometers, respectively.
These, again are readily available values. If the
components did drift in opposite directions,
calculation shows that 1 LSB error would be imposed
with less that 3°C change; practically, however, similar
components typically track each other and
insignificant change will be noted in the laboratory
environment.
Further stability of the DigitaVAnalog section can be
attained by using fixed resistors with lower accuracy
tolerance and lower temperature coefficient. The
better accuracy will reduce the adjustability needed for
the HADC7545A adjustment; this will then reduce the
inaccuracies contributed by the external resistance
due to internaVexternal resistor temperature
differences and temperature coefficient differences.

Honeywell

Other 7545-Type Devices
Any competing 7545A device may be inserted in
place of the HDAC7545A for evaluation.
Note,
however, that output compensation capacitor C20 will
need be increased to the value specified by the
manufacturer. Having a very uniquely low output
capacitance, the HDAC7545A requires only 15 pF
compensation and has a very fast settling time.

OFFSET
TRIM POT
VOLTAGE

USED
FOR
OPAMPS:

E28-E29

-15 V

AD544

E27-E28

+15V

LF1551sn
OP07
·OP17

JUMPER
POSTS

OpAmps
The high slew rate OP-17 was chosen for the EB104
to demonstrate the fast settling time of the
HDAC7545A. Many other popular op amp types,
having the same pin out, can be used instead. Some
of these op amps require the opposite voltage polarity
on the offset trim potentiometer wiper. The EB104
has Berg jumper posts that allow this polarity change.
Please refer to Table 10 for the jumper poSition for
several popular op amps.

<0

o

~

Z
-

B3

__

C;:~~

'~rf:

~ f:~f

c~:t

u~.

i-.,

~

.ISV
C17

~~

~TO

B,

.n

Ell (ABOVE)

VREF

NOTES:
el)
(2)

(3)
(4)

US-US DECOUPUNGI CAPAQTORS MOUNTED BENEATI-I Ie CO-PAK 1M ).
PINOUTS OF JACKS AND IC"S (J1...r.. U1-U8) SHOWN FROM TOP VlEW.
ALL CAPACITANCES IN uF UNLESS OTHERWISE INDICATED.
£38 AND ES7 USED AS LOGIC HIGH JUMPER POSYS FOR JACK 012.

(5) R. AND R16 TEMP

co

100 PPM; Ala. R11, R12 AND R17 TEMP

co so

PPM.

DIAGRAM

Honeywell

8-103

~LRIBBON

r-ICO-N-TR-O-L-&-S-TA-TU-S-L-O-GI-Cr"'1
J2

1

CONNECTORS----.

D/A INPUT DATA

I

=1==A:tn:=:OIl:::TP:IIT:=:DA:TA===
J4

J3

E371!E1E36

fA!DCoNVERSiiiN

SEcTiON -

-

-

-

-C;- -

cB

J5

IG

~

.

~

€V

R2C8~

Q

o
-8- - ---

~~~~
tilE29

POT.

I

J6

L

I

CJ

__RI4_

~~

Eta

•• E24

8

E5E6

1
1 ~

:?
II

9

R6
_R7_ _

RI5

U4

VS

74lS157

L.
_ _ _ _....J

C22
D/A CONVERSION SECTION

_

I
I
I
I
I
I
I
I

---1

I
I

CR2

---

!

---+I - -~

ces
[ POT.IR9
V6
RIO
va
?OP.17! cfiV7
CI9 RIIB C20
:
HOAC7545A
0
L
~ ?op.171 0
~
OT.

74LS157

L 74lS157

:~~t

~

?

I

N

•• E26 R5

"MuimLEXERI ~
BUFFER
.--_113_--, SECTION

ESE..

~

~

E21. • E22

r.r:lEI6
O EI7[I[!]
E2

CI5

C9

POT'~20
~

EIS

I
I

~

VI

R40
CI4

ANALOG
OUTPUT
(BOTTOM)

I

V2

ANALOG INPUT
{BOTTOMSIDE MOUNTED}

EIir-FlEI2
EI3!!EIEI4
OCI2

T - - -

nr&

I

-.J

LEW 4/87

FIGURE 12
EB104 BOARD LAYOUT

Top View, Actual Size

8·104

Honeywell

.lLL. .L. .

r...... ......... ......... ......... ......... ............ ............ ............ .......... ............ ........... ........... ........ .....,
CONTROL LINE JACK J2

",

..
"/H

12

/I -CS

Ao

-

RIC

CE

-

STS WR

t••••••O••• J2••••Q••••Q ••• R.••• R. ••• R.

.R.

t...t}..

CiiSELECT
STROBE
P.

:
'

~UltiPleXerl

L.::

CD

...

o

Buffer Control

~

} D/A Converter Control

w"" C,,,",

'--_ _ _ _ _ } AII"'..

Sample/Hold Amplifier Control
StH Input: "0· Allows s/H amp to track analog Input; "1" holds value
1218 Input: "0" for B·bit output format; "1" for 12·blt output format
~ (Chip Select Bar) Input: "0" enables chip operation; "1" prevents operation
Ao Input: "0" selects 12·blt data conversion; "1" selects B·blt data conversion
RIC (Read/Convert Bar) Input: "0" Initiates conversion cycle;
"1" Enables data output
CE (Chip Enable) Input: "0" prevents AID operation; "1" enables operation
STS (Status) Output: AID status output; outputs "1" while converting

WR (Write Bar) Input:

"0" loads DAC Input register; "1" locks register data

~ (Chip Select Bar) Input: ·0" enables Input register; "1· disables

STROBE Input: "0" enables data transfer; "1" results In all J4 outputs as "0"
SELECT Input: "0· selects AID output data; "1" selects J3 Input data
(Note "0" Indicates a logic low condition, "1" Indicates a logic high condition)

-

....................................................................... ..............................................................

_

DATA INPUT JACK J3

t

'Bll BID

B8

B8

B7

B8

B5

B4

B3

B2

Bl

BO

l •.R.•••.R.•••!L•• P••••P••• _9_._.0••• _0._ ••Q••••Q.__ .Q•••_Q •••

~----------~

'--

Alternate input data source for D/A Conversion.
BO Is LSB, B11 Is MSB

II

r'" ........ ......... ........... ............ ............ .......... ............ ............ ........... ......... -_...... ... .....
DATA OUTPUT JACK J4

iBll BID

B8

B8

B7

B8

as

B4

B3

B2

Bl

BO

t ••Q••••Q •••R. ••• R. •••.R.•••.R.•••!L•• P•••• P._._P••••!!•••.I!._••

!

I

_.I

V
'----------------------~
Buffered output data from AID Converter.
BO Is LSB, B11 Is MSB

FIGURE 13
RIBBON CABLE CONNECTORS
PIN FUNCTION SUMMARY

Honeywell

8·105

OPTION AND ADJUSTMENT SUMMARY
<0

o
,..

~
SamplelHold Utilization Options

S/H Amp in Analog Path: E12-E14, E15-E16
S/HAmpBypassed: E11-E13, E17-E18
Sample/Hold Control Options

SlH Amp Controlled by J2 Pin: (E36, E37 Open)
SlH Amp Controlled by HADC574Z Status Output:
E1·E2
HADC574Z Input Range Options

10 VoH Input Range: E23-E24
20 VoH Input Range: E2S-E26
HADC574Z Unipolar/Bipolar Input Options

AID COnversion Section

R4: SlH Amp Offset Adjustment
R2: Gain Adjustment Of AID Conversion, Unipolar
and Bipolar Modes (Same as R2 in HADC574Z data
sheet, figures 11 and 12)
R3: Offset (Zero) Adjustment of AID Conversion,
Unipolar Mode Only (Same as R1 in HADC574Z
data sheet, figure 11)
RS: Offset (Zero) Adjustment of AID Conversion,
Bipolar Mode Only (Same as R1 in HADC574Z
data sheet, figure 12)
D/A Conversion Section

R8: Offset (Zero) Adjustment of Op Amp U6

Unipolar Input Conditions: E21-E22
Bipolar Input Conditions: E19-E20

R15: Offset (Zero) Adjustment of Op Amp U7

HADC574Z Output Fonnat Options

R16: Full Scale Output Trim for use in Bipolar
Mode

12-Bit Output: (E3 Through E10 Left Open)
8-BitOutput: E3-E5, E4-E6, E7-E9, E8-E10
HDAC7545A Output Format Options

R9: (Optional ReSistor, Board Delivered With Pins
Jumpered) VREF Trim for D/A Conversion
Adjustment; Used to Trim Full Scale Output in
Unipolar Mode, or Zero Output in Bipolar Mode.

Unipolar Output: E32-E34
Bipolar Output: E30-E31, E33-E35
TABLE 11
JUMPER CONFIGURATION SUMMARY

TABLE 12
TRIM POTENTIOMETER SUMMARY

Operation of the EB 104 is taylored by positioning the
Berg-type connectors between the appropriate pin
pairs. This table shows a summary of the possible
options and the corresponding jumper connections.
In each case, it is imperative that one option is
selected, but one only. For the jumper post locations
refer to Figure 12 or the PC board.

Multi-turn potentiometers are supplied on the EBt 04
to allow fine adjustment of various analog conditions.
Although the EBt 04 Is calibrated during manufacture
to allow functionality, some adjustment may be
necessary to obtain desired results.

8·106

Honeywell

MSB
STS DB11 DB10 DB9 DBB DB7 DBB DB5 DB4 DB3

LSB
DB2 DB1

DBa DGND

co

o,..

~

VLOGIC 1218 CS

Ao

RIC

CE

VCC REF AGND REF VEE BIP 10V
OllT
IN
OFF IN

20V
IN

PIN

PIN NAME

FUNCTION

1
2
3
4
5
6
7
8
9
10
11
12
13

YMr
e§

LOGIC SUPPLY VOLTAGE, +5V
DATA MODE SELECT INPUT
CHIP SELECTINPUT
BYTE ADDRESSISHORT CYCLE INPUT
READ/CONVERT INPUT
CHIP ENABLE INPUT
ANALOG POSITIVE SUPPLY, +15
REFERENCE OUTPUT, +10V
ANALOG GROUND
REFERENCE INPUT
NO CONNECTION
BIPOLAR OFFSET
10 VOLT ANALOG INPUT
20V ANALOG INPUT
DIGITAL GROUND
DIGIAL DATA OUTPUT
STATUS OUTPUT

14

15
16-27
28

IC

Ao

RIC'

CE
VCC
REF OUT
AGND
REFIN
N.C.
BIPOFF
10VIN
20VIN
DGND
DBO-DBll
STS

II
I

FIGURE 14
HADC574Z PIN ASSIGNMENT

Honeywell

8·107

(LSB)

R feedback

VREF

'tOO

DBO

DBt

DB2

DB3

DB4

DBS

DB7

DB6

DB5

CD

o.....

~

B
I
T

12 BIT MDAC

R
E
G

OUTl

AGND

DGND

DBll

DB10

DB9

(MSB)

PIN

PIN NAME

FUNCTION

1
2

OUT1
AGND
DGND
DBO-DB11

ANALOG CURRENT OUTPUT
ANALOG GROUND
DIGITAL LOGIC GROUND
OUTPUT DATA BITS
CHIP SELECT
DATA WRITE
POSITIVE POWER SUPPLY
REFERENCE INPUT VOLTAGE
INTERNAL FEEDBACK RESISTOR

3
4-15

16
17
18
19
20

os

WR

VDD
VREF
Rfeedback

FIGURE 15
HDAC7545A PIN ASSIGNMENT

Honeywell

-VIN

s/H (SAMPLElHOLD)

+VIN

GND

0

OFFSET ADJ.

N.C.

<

OFFSET ADJ.

HOLD CAP

co
'r"'

Z

N.C.
N.C.
VOUT

FIGURE 16
HA2425 SAMPLE/HOLD AMP PIN OUT

TOP VIEW

vee

SELECT

STROBE
4A
4B
4Y

3A
2Y

3B

GND

II
OUTPUT

INPUTS
STROBE SELECT

A

B

Y

X
X
X

L
L

H

X

X

L
L
L
L

L
L

L

H
H

H

X
X

L

H

H
L

H

FIGURE 17
74LS1572-T0-1 MULTIPLEXER/SELECTOR PIN OUT
AND LOGIC TRUTH TABLE

PIN OUT FROM TOP VIEW

Honeywell

8-109

<0

o.....
Z

-:::L-

J

L<>-:::L-

:

'r
AS

z

DS

!!J;;

Cs

WR21

WR

8

!
~

.AN'\

RClN25
RCOUT

RI

S.

Hie 21

r

24

PO ..

ffiz
~~~

51&

~Q

~~'~ DNr~F

+5V~

CLKOUT

16 VDD

I

CONFIG

SELECT

SClN ..

SYNC

15

D1

..

30

1304
14

I

,.

BWIG~

12 NiC

I DO

E
0

:J:

• DO

, . D2

~

RIO,
111

DS 21

800
I D1

D7

513
REGISTER
SELECT

.SV
515

514

AS 31

AAJSii

,

d.

~:

AD"

2CS

III0

i

••
-.V

3 .,

o.
I

R•

lOuF Tanlalum

TO.1UF

;,
;

C1

.'V

•• v

SV

~

.05

:

·h

SW10

'\

OP

~ -Lf'-'-~~~T
,.R.

0

~

PROGRAM

So IN
JI.
BNe

02

C')

:0

:too

s:

I

R13

"" IN
JI

51( {OPTIONAL}

BNe

03
CLKOUT

511

J4
BNe

o.

Ro OUT
,J8
BNe

,.
R1

SYNC
J5
BNe

.sv

.Hi

POWER PlUG

+5VD+--r<>

o-t----+o

+5V

AGND

cp
~

~

co

II

AN109

m
o

...
~

CLK IN

o

CLKOUT

8

04

fiji

03

SYNC

...

00

07

00

'"
(0 "'' 'E- EJ
N

Jl

'"

N

...

'"'" "'" '"'"

U1

JS

I

8+ Cl

I

"

DECIMATION
RATE

I

06 Dli

I

I

I

SCF BW

RCF BW

rn
G2

GI

'"

- o

...'"

0

I
DC GAIN

I

NONE
(/I

i4

.--C2--Ul----I~m~~ ~:E:B~a ~AAar;lar;l
LJ
LJ CJ tJ

~v

GAIN

1..-_ _ _ _ _ _ _......1

C":"") XI

DIRECTMAN
PROGRAM

SM

REGISTER
SELECT

CONFIG LATCH
SELECT DATA

CSc:::>OC6

ON~~

POWERO ~
DOWN
'"
OFF

0 5 f0 58 oE)
Se OUT

ReOUT

Re IN

SelN

FIGURE 4
EB105 BOARD LAYOUT
Top View

8·120

Honeywell

TABLE 1 EB105 TOGGLE SWITCH SUMMARY (PART 1)
Switches S1 to S10: Register State Operators
0>

Position of each switch (up or down) determines the logic state of the corresponding input register upon loading.
Each switch is disconnected when in the center position which allows programming though jack J1.
Type: Double Pole, Single Throw, 3 Position
Positions;
UP: Loads Logic 1 State
CENTER: Disconnects switch, allows programming though Jack J1
DOWN: Loads Logic 0 State
S1: Decimator Sample Rate Bit D4
S2: Decimator Sample Rate Bit D3
S3: Clock to SCF Bandedge Divide Down Ratio Bit D2
S4: Clock to SCF Bandedge Divide Down Ratio Bit D1
S5: Clock to SCF Bandedge Divide Down Ratio Bit DO
S6: RC Filter Bandedge Bit D7
S7: RC Filter Bandedge Bit D6
S8: RC Filter Bandedge Bit D5
S9: DC Gain Bit G2
S10: DC Gain Bit G1
Switch S11: "XTAL OSC CONTROL", Crystal OSCillator Control Switch
This switch enables and disables the HSCF24040 crystal oscillator function. It is directly connected to pin
CLKIN and jack J3. When it is down in the "OFF" position it allows a clock input into jack J3 to serve as the HSCF24040
time base. When it is in the up "ON" position pin CLKIN is tied low to -5V and the internal crystal oscillator serves as
the time base.
Type: Single Pole, Single Throw
Positions;
UP: "ON" which enable the internal clock
DOWN: "OFF" which disables the internal clock and allows operation by the external clock
Switch S12: Direct Program Switch
Direct program mode causes the data registers for DO-D7, G1 and G2 to act transparent. When switch S12 is
up in the "DP" or direct program position, CS is pulled to VSS (-5V) by R6. This disables the AO, AS, WR, and DS inputs
and places the HSCF24040 in the direct program mode. When switch S12 in down in the "MAN" or manual position,
input register 10adin.9..!.s controlle~ switch S15; switch S13 must be in the "BW" or "GAIN" position. Note that data
latch control inputs CS, AO, AS, WR, and DS can be driven from jack J1 when S12 is in the "DP" pOSition and S13 is
in the open (center) position.
Type: Single Pole, Double Throw
Positions:
UP: "DP" Direct Program mode, DO-D7, G1, G2 latches transparent (switch open)
DOWN: "MAN" Manual mode, loading controlled by S15 (switch closes)

Honeywell

8-121

o....

z
«

TABLE 1 EB105 TOGGLE SWITCHSUMMARV (PART 2)
0)

o
.,...

~

Switch S13: Register Select Switch
This switch, which is tied directly to pin AO, selects eitherthe 00-07 registers or G1, G2 registers during manual
loading. When inthe ''GAIN'' (down) position, it sets pin AO to logic 0 which allows access to register bits G1 and G2.
When in the "BW' (up) position, it sets pin AO to logic 1 which allows access to register DO through 07. With switch S13
in the center poSition, it is disconnected and allows control of pin AO though Jack J1. The purpose of the AO pin is to
allow use of an 8-bit bus to write all ten registers. The data into pin AO can be latched by a 1 to 0 logic transition on
pin AS; pin AS is pulled high by resistor R9 and can be pUlled low by pin AS of jack J1 ..
Type: Double Pole, Single Throw, 3 Position
Positions:
UP: "BW", Bits 00-07 Latch Access
CENTER: Switch Open (Control enabled by jack J1)
DOWN: ''GAIN", Bits G1, G2 Latch Access
Switch S14, "CONFIG SELECT", Filter Configuration Selection
This switch controls the logic state of HSCF24040 pin AAlSM which internally determines the analog input to
the switched-capacitor filter. In the up "AA" position logic state 1 is forced which establishes the RC filter output as the
SCF input. In the down "SM" position logic state 0 is forced which establishes the SclN analog input as the input to the
SCF. This switch does not have a corresponding function on Jack J1.
Type: Single Pole, Single Throw
Positions;
UP:"AA" RC filter output is SCF input (Logic 1)
DOWN: "SM" Analog input SclN is SCF input (Logic 0)
Switch S15, "LATCH DATA" Data Strobe Control Switch
Pushing this momentary-contact switch up into the "L" (Latch) position loads the input registers by pulling the
OS inpu~ to ground. Concurrently, switch S12 must be in the "MAN" (DOWN) position or pins WR and CS must be pulled
low at jack J1.
Type: Single Pole, Single Throw, Momentary Contact
Positions;
UP: ''L" Latches register data (OS - logic 0), Momentary Contact
DOWN: Inactive (OS = I<;>gic 1)
Switch 16: Power Down Switch
This switch is used to disable the analog circuitry of the HSCF24040 thus conserving power. Along with pullup
resistor R12, it controls the logic state of pin PD.
Type: Single Pole, Single Throw
Positions;
UP: ''ON" Device Fully Functional (PO = logic 1)
DOWN "OFF" Analog Portion Disabled (PO = logic 0)

8-122

Honeywell

TABLE 2 EB105 BNC CONNECTOR SUMMARY
Jack J2: "CNVRT", External A/D Converter Control Output Pin
This active low output signal is used to indicate when the Sc OUT output is valid, i.e., when the decimator output
has settled. It is used to trigger an external AID converter or sample/hold amplifier. This jack is directly connected to the
CNVRT pin of the HSCF24040.
Jack J3: "ClK IN", External Clock Input
This input jack is used to drive the HSCF24040 with an external clock. Switch S11 must be in the OFF position
for this input to function. This jack is connected directly to the ClKIN pin of the HSCF24040.
Jack J4: "ClK OUT", Device Clock Output
This output jack provides a buffered version of either ClKIN or the internally generated crystal oscillator output.
It is connected directly to pin CLKOUT of the HSCF24040.
Jack J5: "SYNC", Declmator Sampling Sync Input
This active low input jack controls the sampling instant for the decimator output. Applying a falling edge to the
SYNC input initiates the CNVRT pulse on the next rising edge of CLKOUT. This jack is connected directly to pin SYNC
of the HSCF24040.
Jack J7: "Sc OUT", Switched-Capacitor Filter Output
This jack is the analog output of the switched-capacitor filter after passing through the decimator. It is directly
connected to the pin SCOUT of the HSCF24040. Optional load resistor R13 can be added on the EB105 board.
Jack J8: "Rc OUT", RC Filter Output
This jack is the analog output of the RC filter and is connected directly to pin RCOUTofthe HSCF24040. Optional
load resistor R 14 can be added on the EB 105 board.

Jack J9: "Rc IN", RC Filter Input
This jack is the analog input to the RC filter and is connected directly to pin RCIN of the HSCF24040.
Jack J10: "Sc IN", Switched-Capacitor Filter Input
This jack is the analog input to the Switched-capacitor filter and is directly connected to pin SCIN of the
HSCF24040. This pin is internally enabled only when switch S14 "CONFIG SELECT" is down in the "SM" position.

..........

,.....· · · · · · · · · · · I
DGNO

.... M('I .... Or--COII)('I ....

QQQQQQQQCICI

DGND

FIGURE 5
RIBBON CABLE CONNECTOR JACK J1
PIN FUNCTION SUMMARY

* *For Ordering Information See Section 1.

Honeywell

8-123

II
I

NOTES:

8·124

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

USING ECl DACs WITH TTL lOGIC
by Tom DeLurlo and Russ Moen

High speed Digital-to-Analog converters are primarily designed to perform in 10K or 1OOK ECl systems because of
the inherent speed and low noise that is characteristic of
this logic group. Unfortunately, a large number of designers, are either using high speed TTL logic with the DAC or
are stuck in a +SV only environment and using pseudo ECl
levels. This Application Brief will address these issues and
offer solutions to overcome the perceived incompatibility
between -S.2V operation and +SV operation.
Although the majority of Honeywell Signal processing
Technologies' High speed DACs are optimized for ECl
input levels, TTL levels can be utilized by pulling up the
input pinsto +SV. Additionally, the Vcc orGround pins must
also be pulled upto +SVandthe Vee pins aretiedto ground.
And, by adding optional input voltage divider resistors,
decreased noise can be realized by attenuating switching
levels.
In a pseudo ECl system where the preceding DAC logic or
memory is EClbut is pulled upto +SV, all that needs to be
done is to pull the DAC up to the same level by shifting the
ground or Vcc and Vee pins. Also, in most cases, analog
output level shifting is required to bring the output down to
ground potential. This is not necessary if driving an AC
coupled load.
Honeywell SPT makes a variety of different ECl compatible DACs which have different types of output structures,
but similar inputs. Therefore, if needed, all the circuits will
have the same input level shifting but different output
circuits.
The first device, the HDAC97000, is an B-bit Video DAC
that operates at 200MWPS. It has an BOOO output source
resistor and standard ECl input pins. The circuit in Figure
1 shows how to attenuate and pull up the input and video
control pins for TTL levels using resistors R1 and R2. R1 is
for input attenuation and R2 is the pull-up resistor for each
input and control pin. The associated gain setting, setup,
and glitch adjust function inputs are the same as before but
just shifted up to accommodate a +5V environment. The
analog output is then level shifted down to ground and
resistor values are determined by the following equations:
Gain Setting
R01 = (V-V,)R,
V3MAX

Honeywell

Where V3MAX = Maximum output voltage.
RSET = K(383/64) R01
Where K= 180/go for 20lRE Setup
= 18O/go for 10lRE
= '47.5/go for 7.SIRE
= '40/go for OIRE
V,-Va (a,) :s; R02 :S; V,-Va (a,)
1/2 IDAC MAX
V-~,
10 0,
Example
For
V3= 0 to +1.071V (0 to 1S0IRE), 1/2IDACMAX '" 1BmA,
Blank = 10lRE, Vi = 3. nv '" V2, Rl = 37.S0
Ro, = ( SV - 3.nV) 37.S = 430, 1/BW
1.071V
RSET ='8O/go (3 63/64 ) 430 =2120, 1/BW
DAC Midscale ",1BmA
R02~

3.nV - .7SV (a, Vba)
18mA

~

16BO, 1/BW

II

R02 :S; 3.77V - .7SV :s; 1,OS6O, 1/BW
5 - 3.77
10(43)
A practical method for setting up the circuit is as follows:
1. With loAC 0"' = OmA, adjust Ro, for desired full scale
voltage at V3'
2. loACou, = IMAx' adjust RSET for desired minimum voHage at
V3•
3. IDAcou, = 1/2 Gray Scale, adjust R02 for V, =V2.
( Readjust R01 and RSET In steps 1 and 2 )
It is important that all +5V supplies be adequately bypassed
as shown in Figure 1 for input, output and power pins.

8-125

FIGURE 1 • HDAC97000 IN A TTL ENVIRONMENT.

o
o
,...

~

CONTROLS
VIDEO

[~~~~~!!~~§~~
RL2

RI

VIDEO {
DATA

CLOCK
INPUT

01 • 2N3227

02 • 2N420t

RI

R1 iii 3300.... tor Input attenuation
HI • lIOn • lor 7TL 11.11 pullup

R2

• INDICATES OpnONAL
FUNCnONS

~AQND

1...

L = FERRITE BEAD INDUCTOR
(FAIR·RITE PIN • 274300112)

The next devices are 8-bit High speed DACs that operate
from 165, 275, and up to 400MWPS. They are respectively
the HDAC10180, HDAC10181, and the HDAC51400.
Each part has the same output current structures but have
different voltage reference configurations. The
HDAC10180 does not have an internal voltage reference
and needs an external reference as shown in Figure 2. If
two or more DACs are used as in an RGB monitor application, the HDAC10180s can use the reference from one
HDAC10181. The HDAC51400 has a reference on board
but has a separate reference out pin, whereas the
HDAC10181 shares its' reference out with the reference
input pin.
There are numerous ways to level shift the output from
these devices to ground reference, but the circuit in Figure
2 takes advantage of the differential current output pins
(OUT+ and OUT-). The equations for choosing resistor
values are as follows:

8-126

DOND

Forthe LM113 or HDAC10181/51400 Reference Voltage
V+ = +1.2V
ISET =

-:-=--:::V-...:+--::,(ocT) R, + R2

ocT is the number of turns
on potentiometer R1.

RL = R311R4

~. ~2+:~.V~». V~

The current in 02

VOul (F.S.) = 15.9375 ( IBET) RL + 7.51RE
Where Full Scale .. 650mV and 7.51RE .. 54mV.
7.51RE Is the monitor dc setup level and is standard on
the HDAC10180/81/51400 Video DAC series.

Honeywell

FIGURE 2 - HDAC10180/81 AND HDAC51400 IN A TTL ENVIRONMENT.

HDAC10180/81

_L~--,·nIY
DIGITAL
.IV

;~'~~

1~;J!l_I= RB~~:~~~~~~:~~~~~
~~

10K

Ef,l~~I:VCCD

....
VEED I

II]

«

\

CC~

3100
RB

o
o....

_L_
J"'\rv-"'---__
~ +5V ANALOG

.01J.LF

SUPPLY
BYPASS'

L

:

=-

~~I~AGND ~DGND

COMP VEU
16
20

SUPPLY

"¥PASS

VCCA
17

R7

18

RI
SlO

11

47pF

1....
~

DGND

AGND

~~~~: {=~~::======~::;:ltt:;:::;:;:::::::::::::::::::~J
R7 lIDO
Il·,JOT

U~~
t=BYPASS
.,V
ANALOG
1 AN EXTERNAL REFERENCE OR
REFERENCE OUTPUT (PIN 14)
ON A HDAC10181 or PIN lION
THE HDACSI4DO CAN BE
USED TO DRIVE UP TO TWO
HDAC10180'S OR HDACI'400••

l-l~F
RE~>

I

ISET..!:'V........t-_.....
.... 11
14

•_ _ _ _ _ _ •
I

,

1KO I

BUFF~

~~;

l /' __
I\.

l.

~~~~'0'81

LII113J313 I

~

RI
1800

......_ - I

BANDGAP

•
·-----i-t11••ltr-...,.:l"'\-L!R"..~F~E~RE~NC~E.J
• OPTIONAL 1 •
'\
...
EXTERNAL
I I~~~::::::~~~E::::::::::::::J
: REFERENCE
.....
'/
• - - - - - -:

IREF

.~.

HDAC51400

ONLY

HDAC10181/51400
ONLY

Q1 z Q2 = 2N4209 for HDAC1 0180/81 B
Q1 .. Q2. 2N5583 for HDAC10180/81A
Q1 .. Q2 .. 2N5583 for HDAC51400

II

Honeywell

8-127

NOTES:

i

I: .

8·128

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

EXTERNAL SYNC CIRCUIT FOR VIDEO DACs
by Tom DeLurio and Russ Moen

High speed Digital-to-Analog converters and multifunction
DACs with memory or multiplexers do not always have on
board video SYNC pulse control inputs. This Application
Brief will offer solutions to overcome the absence of video
sync control pins. If needed, the circuits can equally be
used for blank or 10% bright funtions as well.
Although the majority of Honeywell Signal processing
Technologies' High speed DACs have video sync control
inputs, some do not. Since most of SPTs DAC products are
current output type devices, the sync pulse can be added
directly to the output pins. One option is shown in Figure 1
using the HDAM51100 DAC with memory. This device
does not have on-board sync control.

The sync pulse level is generated using an ECl type flipflop that is clocked in phase with the DAC clock to drive a
matched transistor pair. Three flip-flops can be used in
series to match the clock latency ofthe HDAM511 00 orthe
time can be compensated for in software.
Another option is shown in Figure 2. Here, the sync circuit
takes advantage of the voltage reference available from
the DACs reference output pins. This circuit is more accurate and stable then the previous one but uses more components.

VCCA (GND)

01 A Converter
HOAM51100
SYNC
CLK

D

TO MONITOR

Q 1---tP----i

VO (sync)

= -286 mV

"is" 1-+--....----::1=-=;----'

10 (sync)

= --=

FF
CLK

·286mV
37.5

Ib

7.63 mA

= VR1
RI

R2

VR1
VEED

VEEA

R2, R3

= Motorola MD918
= ECL loads for Flip-Flop.

R1, RL

same resistor type If possible

FF

Requires three to match HDAM511 00 part
latency or compensate In software. Other
CACs will vary (see data sheet).

Q1,Q2

=VEEA·Vbe1

- VQ ( .. 1 .. )

VR1" 5.2V· .83· 875

=3.5V

3.5 V
R1" - 4580
7.63 mA

=

FIGURE 1 • Video DACs with external SYNC control.

Honeywell

8-129

,...
o
,...

~

VCCA
(GND)

01 A Converter

>------.....- - l l - - - . To Monitor
Sync D

VCCA
(GND)

Ol--I--l
FF

R1
162,Cl
1/8W

CLK CLK QI--~-e---I------I
VO (Sync)
10 (Sync)

= - 286mV
= -lli!!!.Y... = 7.63mA
37.S,Cl

I" IR3 .. IR1
V Ref Out
(from DAC)

01,02,03,04 = Motorola MP0918.
R4, RS, = ECL loads for Flip-Flop.
R1, R2, R3, RL = Same relstor type If possible.
A1 = LM11CL.
FF = Requires three Flip-Flops to match part latency or
compensate for In software.

R1
R3
162,Cl
1/8W

= V REF OUT
7.63mA
R1 nominally 162 ,Cl
may require adjustment
for variations of Ref Out
If desired.

FIGURE 2 • Video DACs with external SYNC control using Internal voltage reference.

8-130

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES

CHARGE SCALING DATA CONVERTERS
PAUL M. BROWN
High quality polysilicon MOS capacitors, inherent in
Honeywell's CMOS process, have made it possible to
replace the traditional data conversion technique of
current scaling with charge scaling. This technique relies
on carefully matched capacitors instead of matched
resistors and current sources to accomplish digital to
analog conversion. The advantages of this approach
include ease of manufacture, low power consumption
and an inherent sample-and-hold function that
substantially improves analog-to-digital converter
performance yet adds no extra components. This
application brief will discuss the basic charge scaling DAC
(digital-to-analog converter), how it functions and how it
is used in The HADC574Z and the HADC674Z to
achieve the "buih in" sample-and-hold function.

Charge scaling DAC's produce an analog output vohage
by distributing charge in an array of binary weighted
capacitors. The weighting of the capacitive divider is
determined by the incomming digital code. Figure 1
illustrates a basic capacitive divider circuit. This circuit
functions in two steps. In step 1, switch Sa is closed and
switch Sb is connected to ground, discharging both Csel
and Cb. In step 2, Sa is opened and Sb is connected to
the reference vohage Vref. Due to the relative values of
Cb and Csel and the charge distribution between them,
Vref is divided between the two capacitors such that
Vout =Vref X CseV(Cb+Csel).
Figure 2 illustrates how a capacitive DAC is implemented
using the above approach. Csel is the sum of all
capacitors selected by the data bits to be connected to
Vref and Cb is the balance of all other capacitors,
including the termination capacitance, that remain
connected to ground.

Figure 1. Simple Capacitive Divider
+
Sa

The total DAC ca~acitance, Ctot = C + C/2 + C/4 + C/8
+..... +C/2 N-1 +C/2 -1 =2C
Ctot = Csel + Cb
The total selected cafacitance, Csel = b1 C + b2C/2 =
b3C/4 + ..... + bNC/2N• (where b1 ... bN = 1 or 0 )

Vout

=Vref

Vout =Vref X CseVCtot

Csel
Cb + Csel

Figure 2. Capacitor DAC

..
1c I£. 1·~
£.

II

__4>--....----<11>---0 +

2

S1

Vout
Sa

4

S3

S2

j±-ss :
: ss-:,

~-----------o

Honeywell

,, b3

Vref

+

' bN

,

,

Data

Dala

Data

Dala

BII
1
MSB

Bit
2

Bit
3

Bit
N
LSB

8-131

The HADC574Z1674Z use the DAC in a slightly different
manner (see figure 3). The DAC output is connected to
one input of a comparator and a reference voHage is
applied to the other comparator input. The conversion
cycle begins witll a "reset". The pAC is first "zeroed" to
the analog input voltage with switch S1 closed. Next, S1
opens and the SAR (successive approximation register),
under control of the comparator, sets the appropriate
data bits to either Vref or ground to balance the
comparator inputs. The significance of this is that the
input voltage is sampled only during the "reset" period.
AHhough there is no sample-and-hold circuit in the
classical sense, the sampling. nature of the capacitive
DAC makes the HADC574Z1674Z appear to have a built
in sample-and-hold.

Let l:N .. Verr, Vp - Vinl2 and ~T - The time during which
unwanted voHage changes can occur· on the input
signal.
This can be rewritten as:
VfS/2N+1 ~7dViMT
or
f max ~Vfs/('ltVin~T)2N+1
Let Vfs = Vin= 20V
AD574
~T = conversion time

This sample-and-hold action substantially increases the
signal bandwidth of the HADC574Z1674Z over that of
similar competing devices.

= 25~ typical

fmax ~20V/['It(20V)(25~)(213))=1.55Hz
HADC574Z

EXAMPLE:
~T = 20 ns typical

Assuming a sinusoidal Signal, maximum slew rate, Sr =
27dVp (Vp = peak voltage)
For an N-bit converter to maintain +1-112 LSB accuracy:
Verr ;5; Vfs/2N+1 (where Verr is the allowable error
voHage and Vfs is the full scale voltage)

(specified aperture uncertainty time)

fmax ~20V/['It(20v)(20 ns)(2 13)) = 1.94kHz
The
HADC574Z
has
over
a
1250:1
Improvement In analog bandwidth with NO
ADDITIONAL COMPONENTSI

Sr=~VI AT=27dVp

Figure 3. HDAC574/675 DAC Configuration

1 I
C

C
2

S1

C
2 N·1

C
4

Vref1

Analog
Input

b1

b2

b3

VOLTAGE
REFERENCE

bN

SAR
Comparator

8-132

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES
HADC574Z AND HADC674Z ANALOG INPUT STRUCTURE
Craig Wiley

The capacitive DAC circuitry in the HADC574/674Z
provides lower power dissipation, improved accuracy,
and an inherent samplelhold function as compared to
the traditional R-2R ladder DAC approach used in similar devices. In many applications this inherent sample/
hold function can eliminate the need for an external
sample/hold amplifier and provide superior performance. Additionally, it reduces the dependance on signal
source characteristics during conversion eliminating the
need for signal buffering. The sample/hold function of
the HADC574/674Z can reduce the external circuitry
requirements of data acquisition systems when used
properly. This application brief will discuss the application, advantages and limitations of the HADC574/674Z
analog input structure.
CONVERSION EVENTS

Operation of the HADC574/674Z can be broken into two
basic events. The first event is referred to as the sample
period and begins upon an initiation of conversion.
During the sample period a capacitor array within the
device is connected to the analog input and is allowed to
charge to the external signal voltage. The second event,
longer by comparison, is the successive-approximation
operation utilizing the CDAC. During the conversion
period, the intemal sample capacitance is switched from
the input to the internal CDAC circuitry. As shown in the
simplified circuit equivalent of Figure 1, SW1 is used to
transfer the capacitance Cs from the input to the CDAC
circuitry. Actually, SW1 consists of several parallel
MOSFET switches and Cs is a capacitor array that
performs the CDAC function. Please referto application
brief AB1 02 for more information on charge scaling data
converters.
Conversion event timing of the HADC574/674Z devices
is determined by an internal clock. By virtue of the
differences between internal clock frequency, the
HADC674Z exhibits a shorter total conversion time
compared to the HADC574Z. This also results in a
different sample period between the two devices which
requires application considerations. Figure 2 shows the
conversion event timing (minimum-maximum values) of
both devices. For additional timing information please
refer to the device data sheet.

Honeywell

7.5 k

SW1

--~r--7"".5~.-5-k~"1--III"'L. TO CDAC

10V IN ...

i

i

"'=I"

"';;r

T25

PF

"="

10 VOLT INPUT RANGE

--VVv-l-t---"",\-LcsT25
- 15 k

SW1

20V IN ...

TO CDAC

5k

PF

20 VOLT INPUT RANGE

FIGURE 1
SIMPLIFIED INPUT CIRCUIT
OF HADC574/674Z

Typical values shown

Compared to similar devices, the HADC574/674Z
places less demand on the signal source stability and
output characteristics. In the similar devices, the R-2R
DAC is connected to the external signal source during
the successive-approximation conversion operation.
During the conversion, the signal source must remain
stable to within a tolerable bit accuracy. Low output
impedance and close proximity of the source are normally necessary to allow quick response to the changing
DAC load. These requirements are normally met with a
sample/hold or buffer amp. When using the HADC574/
674Z's, however, direct connection can frequently be
made to the voltage source without performance degradation.

8·133

'STATUS' OUTPUT

('I)

o
,...

~

~

L
174; 1.8·3.0 u.
874: 1.0·1.1 u.

SAMPLE PERIOD
CONVERSION
PERIOD
TOTAL CONVERSION
TIME

t

t

END OF
CONVERSION

INITIATION OF
CONVERSION

FIGURE 2
CONVERSION EVENT TIMING
OF HADC574/674Z

DC INPUT CHARACTERISTICS
The intemal input scaling resistors in the HADC574/674Z
have different impedance characteristicsforthe 1OV IN and
20V IN analog input pins. The input resistance range of
these pins is shown in Figure 3. When using a high signal
source impedance, the attenuation caused by the internal
input resistance must be considered, Forexample, a signal
source with an output resistance of 5 kO driving the 1OV IN
pin, which has a 5 k!l typical input resistance, would
appear to have only half the signal value. Some ofthis error
can by compensated by the external trim network (see data
sheet), but drift can result due to thermal coefficient differences between the external and internal resistances. It is
therefore important to keep the source impedance as low
as possible.

DYNAMIC INPUT CHARACTERISTICS
Input Settling

Although Jhe samplelhold function of the HAC574/674Z
provides utility, dynamically it Is of modest performance
when compared to dedicated sample/hold amplifiers. It
can, however, provide superior noise immunity when
sampling lower frequencies (below 5 kHz).
Figure 4 shows the electrical equivalent of the internal
sample circuitry as it appears to Cs. The equivalent
resistance using either input pin (1 OV IN or 20V IN) is equal,
assuming zero source resistance. Figure 4 provides a
usable first order approximation and ignores all other parasitic effects. The 4 k!l resistance includes the resistance of
SW1; in applications with high source resistance, source
resistance effects should also be included. Charge resistance can be calculated from the circuits of Figure 1.
In Figure 4, the voltage across Cs over time is defined by:

eC

E=

1 -

e

-tlRC

where: ec = Voltage of Cs; E = Signal Voltage;
t = time; R,C = Component Values of Figure 4.
To express Equation 1 in terms of time (t) to obtain a
required charge voltage (ed' we can rewrite equation 1 as:

ec

t = -RC /n (1 - E )

HADC574/674Z
3.75·6.25 k

10V IN

16 - 25 k
20V IN

FIGURE 3
DC INPUT CHARACTERISTICS
OF HADC574/674Z

8·134

(equation 1)

(equation 2)

The design of a data acquisition system using the
HADC574/674Z must take into account the total system
settling time and the effect upon ec ' the captured signal
voltage sample. The desired settling value of ec must occur
within the sample period of the device. Using equation 1, a
full-scale step input will settle to within 1/2 LSB of final value
in 0.9 J,Ls. (For this calculation, (eC/E) = (4095.5/4096)).
Using equation 2,the final value is within 1/5 LSB after 1 J.LS.
Therefore, even when using the HADC674Z which has
minimum sample period of 1J.LS, the pole introduced by the
internal charge circuit is negligible.
Because this dynamically-limited sample/hold amplifier
acts like a low-pass filter, it exhibits good noise immunity.
An external sample/hold will usually be more susceptible to
circuit noise. Even with an external sample/hold amplifier,
the HADC574/674Z typically exhibits less input noise than
similar 574/674 devices. Room temperature characterization shows that typical· equivalent input noise of the
HADC574/674Z is 1/5 LSB or 50 J,LV.

Honeywell

Dynamic Sampling Error
4k

The bandwidth limitations of the HADC574/674Z's
sample/hold feature are more apparent when performing dynamic sampling, that is, sampling of an active
signal. For an AC signal voltage, the circuit of Figure 4
is low pass, phase-lag network. The transfer function of
Figure 4 can be expressed as:
E
ec = 1 + jwRC

(Equation 3)

where: w = 2pf
The sample circuit equivalent, shown in Figure 4, can be
viewed as a single-pole low-pass filter with a half power
point at 1.6 MHz. Using equation 3, the 1/2 LSB
magnitude attenuation of a full scale signal occurs at 25
kHz. At 10kHz, the attenuation is only 0.08 LSB. As
discussed in the following section, since 5 kHz is about
the maximum usable range, the low-pass magnitude
degradation imposes insignificant error.
Phase distortion in the input network is an important
error to consider in dynamic sampling applications. As
signal frequency goes up, higher reactance of the
sample capacitor causes an increase in phase shift.
Thus, a sampled waveform at one frequency appears to
be delayed in time relative to a lower frequency. Phase
shifting between frequencies is illustrated in Figure 5.
Using equation 3 above, It can be determined that a fullscale sinusoidal signal is allowed a maximum frequency
of 195 Hz if an amplitude errorof 1/2 LSB (&V) maximum
is allowed considering the phase shift in the time domain
,UID. Most analog data, however, is in the form of a
complex waveform which consists of several fundamental frequencies. Sampling of a complex waveform with
excessively high frequency components will result in a
distorted digital representation.

10VIN
OR
20V IN

E

TYPICAL

~25PF
c J

TYPICAL

FIGURE 4
EQUIVALENT DYNAMIC CIRCUIT
OF HADC574f674Z

kHz for a full-scale sinusoidal signal. Exceeding the slew
rate limitation during the sample period will result in an all
"1" output for a positive-going input and an all "0" output
for a negative-going input.
As described in the HADC574Z and HADC674Z data
sheets, aperture jitter also places a limitation on the
maximum usable input frequency. The specified 20 ns
typical aperture jitter accounts for worst case changes in
ambient temperature and power supply voltages. In
application, however, sample-te-sample jitter typically
less than 5 ns. Discrete-Fourier-transform (OFT) characterization ofthe HADC574Z has showed thatthe widebandwidth signal-to-noise ratio is approximately 72 dB
down from the fundamental when using full-scale singletone sinusoidal test signals up to 8 kHz. Above this
frequency, the slew rate limitation described above
greatly degradates the performance. Both the minimum
aperture jitter and excellent linearity typically found with
the HADC574/674Z provide a low dynamic distortion
level which approaches ideal performance limited by 12bit quantization error alone.

II

Non-Apparent Dynamic Factors

Present architecture olthe HADC574/674Z results in an
inherent input slew rate limitation during the sample
period described earlier. Slew rate adversely affects the
switches composing SW1 in Figure 1. Problems will
generally be found with slew rates above 0.25 V/~s into
the 10V IN pin or 0.5 V/~s into the 20V IN pin. This
corresponds to full-scale sinusoidal signal of 8 kHz into
either pin. To avoid problems over all operating conditions, the maximum slew rate should be conservatively
limited to 0.16~V/s into 10V INorO.32~V/sont020V IN.
This places the conservative input frequency limit at 5

'Honeywell

:

I

--~

HIGH FREQUENCY SIGNAL

APPARENT PHASE SHIFTED
HIGH FREQUENCY SIGNAL
RELATIVE TO
LOW FREQUENCY SIGNAL

FIGURE 5
EFFECTS OF PHASE DISTORTION
THROUGH INPUT NETWORK

8-135

CONCLUSION

The analog input structure of the HADC5741674Z provides superior performance to that of similar 5741674
devices. In addition, the inherent sample/hold function
can eliminate the need of an external samplelhold or
buffer amplifier. Because of it's dynamic limitations, use
of the internal sample/hold function is limited to lowerfrequency « 5 kHz) data-acquisition applications.
Systems requiring temporal (phase) accuracy during
dynamic sampling or that will sample signals over 5 kHz
should use an external sample/hold amplifier.

8·136

Honeywell

SIGNAL
PROCESSING
TECHNOLOGIES
TESTING THE HADC574Z AND HADC674Z ON THE LTS2020
Craig Wiley

Minor modifications of test hardware and software are
needed in order to successfully test the Honeywell SPT
HADC574Z or HADC674Z devices on the LTS2020
tester. The LTS2020 is a low-cost integrated circuit test
system built by Analog Devices Incorporated and is
commonly used as an Incoming Inspection test station.
The HADC574/674Z devices offer enhanced performance but have slight differences in test requirements
compared to 574/674 devices available from other
manufacturers. Hardware modifications required forthe
HADC574/674Z will not effect the testing of similar pincompatible devices.

This modification on the LTS0620 socket adapter involves changing relay K2 and making the appropriate
wiring modifications. Using the LTS0620 schematic nomenclature, Figure 3 shows the board, as-is, and Figure
4 shows the modified version. For relay K2, a Coto 221105 is used to replace the existing Coto 2900-0017. The
modification will provide a suitable range switching technique for the HADC574/674Z as well as all pin-compatible574/674devices. No software changes are required
for this modification.

OTHER 5741874

~':I'Ou,r :~~~:~--lr-__~.O,,-V"'"INo-__.....
~

__

TESTERINPUT
SELECTION SWITCH

10VIN

DEVICES
(OUT)

?

~

alP OFF¢--A(V~?_",

FIGURE 1
L TS2020 INPUT RANGE SWITCHING
TECHNIQUE
Input structure of device shown is of 5741674 devices

20Y IN

~':I'c:'J :~~m-""'-----""'-""":;10:':'V..!!:IN,?--'I1I'r-]J
sEI~m~~~~+CH
(MODIFIED)

alP

HADC574/674Z
DEVICES
(OUT)

OFFo--'W~j_...

FIGURE2
MODIFIED L TS2020 INPUT RANGE
SWITCHING TECHNIQUE
Input structure of device shown is of HADC5741674Z

SOFTWARE MODIFICATIONS

The hardware modification involves a minor change to
the LTS0620 socket adapter which fits into the
LTS2200-ADC family board. The socket adapter, as-is,
takes advantage of the input structure common to 574/
674 devices by other manufacturers. A single-pole relay
is used to switch between to 20V IN and 10V IN pins of
the device. This relay configuration is illustrated in
Figure 1. The HADC574/674Z devices, due to the more
accurate input architecture, will not function properly
with this simplified switching scheme and instead requires a double pole relay as shown in Figure 2.

Testing of HADC574/674Z devices require some software changes since the LTS2020 574/674 test software
is written for the similar bipolar devices. First, since
HADC574/674Z devices use the BEMOS process, the
limits for the power supply current tests need to be
lowered. Second, since HADC574/674Z devices do not
use a -15 Volt supply (VEE pin is not intemally connected) the -15 Volt tests need to be bypassed. And last,
because of the internal sample/hold function, the ratio
between the 8-bit and 12-bit conversion times differs
from similar 574/674 devices (although they still comply
with the specifications).

Honeywell

EI'
••

HARDWARE MODIFICATION

8-137

"

P1·7 - - - - - - '
P1· •

14
"
...----_/

14
P1·7
DUT

DUT

15 [----!<:::__-l.

P1-'

13

~~~-~~-_o13

IMI
4f1T
+5V

+5V

P2·44

P2·44

FIGURE 3
UNMODIFIED L TS0620 WIRING AS
REPRESENTED BY FIGURE 1

FIGURE 4
MODIFIED L TS0620 WIRING AS
REPRESENTED BY FIGURE 2

The test programs available forthe LTS2020 tester are the
AD574_HG for testing 574 devices and the AD674_HG for
testing 674 devices. The modifications of these programs
for successful testing of the HADC574Z and HADC674Z
devices are listed below. These modified test programs will
not be suitable for testing similar 574/674 devices and
should therefore be given new names avoid confusion.

AD574_HG and AD674_HG Test Program
Changes:

(Comments:)

1) Line 310, change LL (Lower Limit) to -0.1and UL
(Upper Limit) to +3 (mA)

(New +5 Volt supply c ment limits)

2) Line 340, change LL to 0 and UL to 10 (mA)

(New + 15 Volt supply current limits)

3) Add line 355 "GOTO 380·

(Skips -15 Volt supply test since this pin is unconnected)

4) Line 86, change "E" conversion faetorto 0.75.

(New 8-bit conversion time limit)

5) Add line 1005 "GOTO 1060".

(Skips -15 Volt pin PSSR test)

8-138

Honeywell

SELECTION GUIDE, CROSS REFERENCE
ORDERING INFORMATION

II

ANALOG TO DIGITAL CONVERTERS

II

DIGITAL TO ANALOG CONVERTERS

COMPARATORS

INSTRUMENTATION AMPLIFIERS

II
.i

SPECIAL FUNCTIONS

EVALUATION BOARDS

APPLICATIONS INFORMATION

PACKAGE OUTLINES

SALES OFFICES AND
REPRESENTATIVES

Honeywell

9-1

Quality Assurance
Quality and reliability of electronic components are
critical issues at Honeywell Signal Processing
Technologies. Customers integrate large portions of
their finished products into silicon using SPT's complex high performance integrated circuits. The quality
and reliability of the. end. products therefore, depend
heavily upon the integrated circuits they contain.
Realizing the intimate. relationship between its
customers' success and its own, SPT has put into
place a' continually improving quality assurance
system that makes its products among the highest
quality and most reliable components available.
Quality and reliability, frequently thought to be
synonymous, have quite different meanings. Quality
implies that a device initially conforms to a given set of
performance criteria. Reliability implies that a device
continuously meets a .given set of performance
criteria. Figure 1 illustrates the traditional "Bathtub"
Failure Rate Curve. A given sample of unscreened
devices that initially meet their published specifications (high quality) will tend to have a relatively high initial failure rate (infant mortality) due to parameter drift
or manufacturing defects that have gone undetected
during the manufacturing process (low reliability). The
failure rate during the "normal life" period is affected
by devices with latent failure mechanisms that normally exhibit themselves during the infant mortality period
and some devices that prematurely "wear out".
Failure during the "wear out" period is caused by
metal migration, long term drifts, corrosion and
package failure. SPT insures the high quality of its product with rigorous 100% electrical testing. Product
reliability is designed in and insured through comprehensive QA (Quality Assurance) monitoring throughout
the manufacturing process and screening of the final
product.
Screening operations are designed to "weed out"
potential infant mortality failures before they are ship·
ped to customers. The screening procedures that SPT
uses are described below with the failure mechanisms
they are designed to catch.

Stabilization

The devices are heated to 150·C in an oven for 24
hours without electrical stress. This procedure is used
as a preconditioning for subsequent testing.
Temperature Cycling

The devices are cooled to - 55·C for 10 minutes then
elevated to + 150·C for 10 minutes with a 5 minute
transfer time in-between. This procedure is carried out
10 times. Variations in physical dimensions of defective packages can cause loss of package integrity,
cracking of passivation on the die, and changes in
operating characteristics due to mechanical stress.
This test is performed without electrical stress.
Constant Acceleration

The monolithic devices are subjected to 30,000 gs for
1 minute in the Y1 plane. This test is performed without
electrical stress and can uncover mechanical weakness that was not detected by temperature cycling.
Gold wire bonds are effectively tested for integrity in
cavity packages (packages in which the bond wires
are not encapsulated). The test is not as conclusive for
aluminum wires (due to their lighter weight). Cracked
die, weak die bonds, poor lid seals and improperly
dressed bonding wires can also be detected during
this test.
Hermetic Seal

Fine Leak
The units are placed in a helium filled vessel under 60
psig for at least 1 hour. Helium will enter the die cavity
through any cracks or pin holes. The devices are
removed and placed into the test chamber of a mass
spectrometer leak detector. Any helium that entered
the package during the previous procedure will be
drawn out by the vacuum In the test chamber. The leak
rate is measured by the spectrometer. An alternative
method with equal or greater sensitivity using Krypton
gas may be substituted for this test.

Pre-seal Visual

Wire bonding, die bonding, package, package leads
and die are visually inspected using both a high and
low power microscope. Many of the defects detectable during this inspection such as defective wire
bonds, contamination, scratched metalization or other
defects on the die contribute to infant mortality. This
inspection is performed just prior to sealing the
device.
Bond Strength

This sample test verifies the mechanical strength of
the wire bono, Metalization and interconnection
failures (typically opens or shorts) account for nearly
half of IC failures.

9-2

Gross Leak
After the completion of the fine leak test (if applicable),
the gross leak test is performed to test for leaks
greater than 10 -3 ATM CC/sec. The devices are
placed in a vacuum/pressure chamber at 5 torr for 1
hour. Before breaking the vacuum the units are
covered with liquid FC-72. The pressure is then raised
to 60 psig for two hours. The devices are removed
from the vacuum/pressure vessel and submerged 2 in.
in FC-43, heated to 125 ·C, for 30 seconds and visually
checked for bubbles.
These tests evaluate package integrity and detect
devices that might fail when exposed to an environment containing moisture or gaseous contaminants.

Honeywell

Pre Burn·ln Electrical Test

Post Burn·ln Electrical Test

Devices are tested 100 % at 25°C for DC parameters
(AC parameters and temperature extremes as reo
quired) to detect any electrical anomalies induced by
the previous mechanical and thermal stresses.
Serialized devices that will be burned-in may have
some parameters logged at this pOint to test for
parameter drift after burn-in is completed.

Devices are tested 100 % at 25°C for DC parameters
(AC parameters and temperature extremes as required) to insure that after all applicable screening the
devices perform as specified.

External Visual
This final optical inspection insures that the packages
and leads appear defect free.

Burn·ln
Burn-in is performed for a specified number of hours at
125°C with the device electrically stressed. This procedure eliminates devices with parameters that are
marginal or have latent defects. Intermittent shorts
caused by pinholes in the passivation will tend to
become permanently shorted. Metal that is almost
discontinuous due to scratches or cracks will tend to
open. Corrosion and contamination on the die will tend
to impact the circuit performance and will be detectable during the post burn-in electrical testing.

Figure 2 summarizes the screening procedure and the
failure mechanisms they are designed to detect.
Figure 3 Quality Flow Diagrams illustrate the standard
processing for SPT's various product grades. Special
quality flows can be tailored to specific customer
needs.

FIGURE 1: "BATHTUB" FAILURE·RATE CURVE
FAILURE
RATE

o

6 MONTHS

INFANT
MORTALITY

Honeywell

10·20
YEARS

NORMAL
LIFE

WEAR
OUT

9·3

IN·LINE MANUFACTURING FLOW CHART
FOR HERMETIC CAVITY TYPE PACKAGES

INDUSTRIAL

COMMERCIAL
100% ELECTRICAL
SAMPLE VISUAL

WAFER INCOMING

100% ELECTRICAL
SAMPLE VISUAL

100% ELECTRICAL

WAFER SORT

100% ELECTRICAL

SAMPLE

SAMPLE

SAMPLE (COMMERCIAL CRITERIA)

PRE.SEAL VISUAL

MTD 2010 CONDITON C

SAMPLE

BOND STRENGTH

SAMPLE

MIL·STD883

SEAL

MIL·STD883

100%

STABILIZATION BAKE

100%

100%

TEMPERATURE CYCLE

100%

OPTIONAL

CONSTANT ACCELERATION

OPTIONAL

SAMPLE·GROSS LEAK

HERMETIC SEAL

SAMPLE·MTD 1014 CONDITION A, B, C

OPTIONAL

SERIALIZATION

OPTIONAL

2SoC -100% DC AND AC

OPTIONAL· 48 H RS

2SoC -100% DC AND SAMPLE AC

SAMPLE·MTD 5005 GROUP A

SAMPLE

9·4

DIE VISUAL

PRE BURN·IN ELECTRICAL

BURN·IN

POST BURN·IN ELECTRICAL

QUALITY CONFORMANCE

EXTERNAL VISUAL

2SoC -100% DC AND AC

OPTIONAL 188 HRS
2So -100% DCANDSAMPLEAC
- 251 + 8SOC SAMPLE DC

SAMPLE·MTD 5005 GROUP A, B

SAMpLE·MTD 2009

Honeywell

IN·LINE MANUFACTURING FLOW CHART
FOR HERMETIC CAVITY TYPE PACKAGES

883 RevC

HIGH·REL
100% ELECTRICAL
100% VISUAL

WAFER INCOMING

100% ELECTRICAL
100% VISUAL

100% ELECTRICAL

WAFER SORT

100% ELECTRICAL

100% MIL·STD·883C
MTD 2010.7

DIE VISUAL

100% MIL·STD·883C
MTD 2010.7

MTD 2010 CONDITION B

PRE·SEAL VISUAL

MTD 2010 CONDITION B

MTD 2011 CONDITON B

BOND STRENGTH

MTD 2011 CONDITION B

MIL·STD 883

SEAL

MIL·STD 883

MTD 1008 CONDITION C

STABILIZATION BAKE

MTD 1008 CONDITION C

MTD 1010 CONDITION C

TEMPERATURE CYCLE

MTD 1010 CONDITION C

MTD 2001 CONDITION E

CONSTANT ACCELERATION

MTD 2001 CONDITION E

MTD 1014 CONDITION A,B,C

HERMETIC SEAL

MTD 1014 CONDITION A,B,C

OPTIONAL

SERIALIZATION

YES

-55°C, +25°C,

+ 125°C

-100% DC
25"C -100% AC
MTD 1015 CONDITIONS A,B,C,D,E,F

PRE BURN·IN ELECTRICAL

BURN·IN

25"C -100% DC AND AC

MTD1015 CONDITIONS A,B,C,D,E,F

-55°C, +25°C, +125°C
-100% DC
25"C -100% AC
MTD 5005 GROUP A, B

lOX MAG MTD 2009

NOTE:
GROUP
GROUP
GROUP
GROUP

A:
B:
C:
D:

POST BURN·IN ELECTRICAL

QUALITY CONFORMANCE

EXTERNAL VISUAL

PER SLASH SHEET

MTD 5005 GROUP A, B, C, 0

MTD 2009 - 100%

ELECTRICAL CHARACTERISTICS
PACKAGE ORIENTED TESTS
LIFE TESTS - PERIODIC CONFORMANCE
ENVIRONMENTAL TESTS - PERIODIC CONFORMANCE

Honeywell

9·5

FIGURE 2: FAILURE DETECTION SUMMARY

FAILURE MECHANISM DETECTED
process
related

die
bonds

passivation
failure

thermal
stress

defective
package

electrical
failure

Procedure
Pre·8eal Visual

r/

Bond Strength

r/

r/

Stabilization Bake

r/

r/

Temperature Cycle

r/

r/

Constant Acceleration

r/

r/

r/

r/

r/

r/

r/

r/

r/

r/

r/

v"

r/

Leak Te.t

r/

v"

Pre Burn·ln Electrical

r/

Burn·ln

r/

v"

r/

r/

r/

Post Bum·ln Electrical

v"
v"

External Visual

r/

FIGURE 3: QUALITY FLOW DIAGRAMS
IN·LlNE FLOW CHART FOR TRANSFER MOLDED
(PLASTIC) AND NON·HERMETIC CAVITY TYPE PACKAGES

COMMERCIAL
SAMPLE

25°C·100% DC AND AC

OPTIONAL
25°C·100% DC AND
SAMPLEAC
SAMPLE VISUAL
CHECK DOCUMENTATION

9·6

INDUSTRIAL
PRE·SEAL VISUAL
PRE·BURN·IN
ELECTRICAL

BURN·IN

POST BII ELECTRICAL

PLANT CLEARANCE

100% (COMMERCIAL CRITERIA)

25°C·100% DC AND AC

OPTIONAL
25°C·100% DC AND SAMPLE AC
-251+85°C - SAMPLE DC
SAMPLE VISUAL
CHECK DOCUMENTATION

Honeywell

SELECTION GUIDE, CROSS REFERENCE
ORDERING INFORMATION

ANALOG TO DIGITAL CONVERTERS

DIGITAL TO ANALOG CONVERTERS

COMPARATORS

INSTRUMENTATION AMPLIFIERS

SPECIAL FUNCTIONS

EVALUATION BOARDS

APPLICATIONS INFORMATION

QUALITY ASSURANCE

SALES OFFICES AND
REPRESENTATIVES

Honeywell

10-1

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SIGNAL
PROCESSING
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0.808 (15.4)

0.58 (14.74)

~

0.008 (0.203)

I

0175
0.125 (3.18)

2~L~~D~DU~A~L~IN~-L~IN~E~-;;;;---------

+.L. J. L. .L . : : :D.D .D.Ol: _: ~:r- ·

CBDIP

38.1 Max

··r--~--I'''
Max

~

0.32 Max

26X
2~LEAD

DUAL IN

0.32 Max

2.16

Honeyw;i.

10-13

32 LEAD SIDEBRAZED

0.60 (15.24)
0.566 (14.43)

~-n-r-r-nI..;=;-r;--;'i""'Fi""'ih-rr-r.,.~~
I
-*- I.
1.628 (41.36)
1.57 (39.90)

~~
~~~I-

MAX

0.065 (1.66) 0.02 (0.508)
0.038 (0.965) 0.015 (0.381)

0.12 (3.05)
0.06 (1.53)

•

~~

0.105 (2.67)
0.095 (2.42)

..===;:;--.L

~.012
+
~.008

II
~

L

I

0.175 (4.45)
0.125 (3.18)

r

0.606 (15.4)
0.58 (14.74)

I

.I

(0.305)
(0.203)

32 LEAD CERDIP

I.

1.690 (42.90) MAX

·1

==~~
0.125
(3.175)
MIN

48 LEAD SIDEBRAZED

I'

I

IAlO:t 0.1114

-------+1

TH. METAUZED ..... ,.
CONNECTED TO DIE An"eN

PAD AND lEAL RM

I

. .
~

Ici

o

~

°
~

PIN NO.1

INDEX MARK
,lOOtD.01
~TAND Off)

CAT

O,1oo:t.0.G10

10-14

Honeywell

42 LEAD SIDEBRAZED

[... ..
~

!

;

II

•.•~ ......

20 PIN LCC

) - t - - - - +-----1f<

'/

46 PIN PGA
.050 DtA. ± .005

;;:.1.181 ± .012

(45 PLCS)

-1

PIN 1IDENT.

0
0
0
0
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g 0
:;:

~

0
0
0
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0
0 0
0 0

0 0 0 0 0 0
0
0
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0

._---------

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0
0
0
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0
0
0

sa.

&.

0 0
.100TYP

.&.

72 PIN PGA

.&.

I.

11109

!:~~:
8

7

8

J

SQ.

5

0.47

t.ooa

4~

0000000000

A

O@OOOOOOO@OB

00
00
00
00
00
00
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00
00
00

TO' VIEW

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K

000000000
NOTES:

,. Cavity down.
2. 100 mil pin .paclng

.100 t.OO'

-I :t.ooa
1+
.080

* * For Ordering Information See Section 1.

Honeywell

10-15

NOTES:

10-16

Honeywell

SELECTION GUIDE, CROSS REFERENCE
ORDERING INFORMATION

ANALOG TO DIGITAL CONVERTERS

DIGITAL TO ANALOG CONVERTERS

COMPARATORS

INSTRUMENTATION AMPLIFIERS

SPECIAL FUNCTIONS

EVALUATION BOARDS

APPLICATIONS INFORMATION

QUALITY ASSURANCE

PACKAGE OUTLINES

Honeywell

11·1

AREA SALES MANAGERS
WESTERN AREA

SOUTH CENTRAL AREA

Honeywell Inc. SPT
721 S. Parker, Bldg. C
Orange, CA 92668
(714) 953·4886
FAX: (714) 953·7204
Telex: 290651

Honeywell Inc. SPT
P.O. Box 467639
Atlanta, GA 30346
(404) 392·1399
FAX: (404) 392·9772

EASTERN AREA

CENTRAL AREA

Honeywell Inc. SPT
6 Misty Ridge Circle
Kinnelon, NJ 07405
(201) 492·0113
FAX: (201) 492·0210

Honeywell Inc. SPT
1 S. 376 Summit Avenue, Court A
Oakbrook Terrace, IL 60181
(312) 916·1826
FAX: (312) 916-1828

DOMESTIC REPRESENTATIVES
ALABAMA
Rep. Inc.
11535 Gilleland Read
P.O. Box 4889 (35815)
Huntsville, AL 35803
(205) 881-9270
(800) 633-2050
TWX 810-776-2102
EasyUnk 62608310
FAX 205-882-6692

ARIZONA
Electronic Development
& Sales, Inc.
2105 South 48th Street,
SUite 107
Tempe, AZ 85282
(602) 438-1647
TWX 510-600-4993
FAX (602) 438-1569

GEORGIA
8cottGouid
753 Sants Roslts
Solana Beach, CA 92075
(619) 755-0824

COLORADO
Luscombe Engineering
Company
616 Klmbark Street
Longmont, CO 80501
(303) 772-3342
FAX (303) 772-8783

CONNECTICUT

Rep, Inc.
1944 Northlake Parkway
Suite 1
Tucker, GA 30084
(404) 938-4358
TWX 810-766-0822
EasyUnk 62657560
FAX (404) 938-0914

ILLINOIS
(NORTHERN)
Heartland Technical
Marketing, Inc.
3315 W. Algonquin Rd.
Roiling Meadows, IL 60008
(312) 577-9222
FAX (312) 577-0325
Telex (312) 577-0329)

(see Texss)

Astrorep of New
England
3 Barnard Lane
P.O. Box 7220
Bioomfteld, CT 06002
(203) 243-3122
FAX (203) 243-8280
Telex 882486

CALIFORNIA

DELAWARE

INDIANA

Emerging Technology
Sales
2030 Fortune DrIve
Suite B
San Jose, CA 95131
(408) 433-9366
Telex 757199
FAX (408) 434-6730

(See Southem New Jersey)

Areta Sales Inc.
2260 Lake Ave.
Suite 250
Fort Wayne, IN 46805
Phone: (219) 423-1478

ARKANSAS

Emerging Technology
Sales
6523 Brome Court
Orangevela, CA 95662
(916) 988-4387
FAX (916) 988-3299
SCCubed
468 Pennsfield Place
SUite lOlA
Thousand Deks, CA 91360
(806) 496-7307
FAX (805) 495-3601
SCCubed
17862 17th Street
SUite 207
Tustin, CA 92680
(714) 731-9206
FAX (714) 731-7801

11·2

FLORIDA
(WESTERN)
Perrott Associates
473 East Shore Drive
Clearwater, FL 3351 5
(813) 443-5214
TWX 810-866-0328
FAX (813) 443-7629

(SOUTHERN)
PBII'ott Associates
9639 Oregon Road
Boca Raton, FL 33434
(305) 792-2211
TWX 510-955-9831
FAX (305) 488-9073

(CENTRAL)
Perrott Associates
7725 N, Orange
Blossom Trall
Orlando, FL32810
(305) 298-7748
TWX 810-850-0254
FAX (305) 299-1807

ILLINOIS
(SOUTHERN)
(see Missouri)

Arete Sales Inc.
918 Fry Road
Greenwood, IN 46142
Phone: (317) 882-4407

IOWA
S & 0 Sales Inc.
3226 Center Point Rd. N.E.
SUite 205
Cedar Rapids, IA 62402
Phone: (319) 383-7323
FAX (319) 363-7331
TWX 910-525-1317

KANSAS
Design Solutions Inc.
10000 W. 75th Street
SUite 200
Shawnee Mission, KS
66204
(913) 877-4747

Honeywell

DOMESTIC REPRESENTATIVES
KENTUCKY
(EASTERN)

NEW JERSEY
(NORTHERN)

(see Ohio)

Comp·Tech Sales
208 Boulevard
SuIteE
Hubrouck Heights. NJ 07604
(201) 288·7400
FAX (201) 288·7583
TWX 710·990·6118

KENTUCKY
(WESTERN)
(see Indiana (Southern])

LOUISIANA
(see Texas)

MAINE
(see MaBSachusetts)

MARYLAND
Rep·lron. Inc.6528 WetBl100 Rd.
Balttmore. MD 21227
(301) 799·7490
FAX (301) 796·1948

MASSACHUSEnS
CompeB8 Technology.
Inc.
300 Wildwood Street
Woburn. MA 01801
(617) 933·3336
FAX (617) 932·3354

MICHIGAN
Greiner Associates
15324 E. Jefferson Ave.
Grosse Pointe Park. MI 48230
(313) 499·0188
FAX (313) 499·0665
Telex 62705450

MINNESOTA
Mel Foster Technical
Sales. Inc.
7611 Wuhlngton Ave .• South
P.o. Box 35216
Edina. MN 55635
(612) 941·9790
TWX 910·576·2746
FAX (612) 944·0634

MISSISSIPPI
(see.Alabama)

MISSOURI
Design Solutions Inc.
12173 Prichard Farm Rd.
SI. louis. MO 63043
(314) 739·3630
MCI6501813164

MONTANA
(see Colorado)

NEBRASKA
(see KsnSBB)
(call SPT direct)

NEW HAMPSHIRE
(see Massachusetts)

Honeywell

OREGON

Rlvco January. Inc.
78 S. Trooper Rd.
Morristown. PA 19403
(215) 631-1414
FAX (215) 631-1640
TWX (510) 660·2406

Northwest Marketing
Associates
6975 S.W. Sandburg Road
Suite 330
Portland. OR 97223
(503) 620·0441
TWX 910·464·5157
NWMARKPTL
FAX (503) 684·2541

NEW MEXICO
(EI Paso, TX)

PENNSYLVANIA
(WESTERN)

Nelco Eleclronlx
4801 General Bradley. N.E.
Albuquerque. NM 87111
(505) 293·1399
FAX (505) 292·3247

(see Ohio)

NEW JERSEY
(SOUTHERN)

NEW YORK
(UPSTATE)
Elcom Sales Inc.
400 Whitney Road
Rochester. NY 14625
P.O. Box 25112
(716) 385·1400
FAX (716) 248·8531
TWX (510) 254·2627
Elcom Sales Inc.
2·4 Fennell SI.
P.O. Box 836
Skaneateles. NY 13152
(315) 685·8245
FAX (315) 685·6273

NEW YORK
(METRO)
Comp-Tech Sales
P.O. Box 237
New Hyde Park. NY 11040
(516) 593·2628
FAX (201) 288·7583

NORTH CAROLINA
Rep. Inc.
2500 Gateway Center Blvd.
Suite 400
MorriSVille. NC 27560
(919) 469·9997
EBSyUnk 62637570
FAX (919) 481·3879

NORTH DAKOTA
(see Minnesota)

NEVADA

OKLAHOMA
West Associates
9717 E. 42nd '125
Tulse. OK 74146
(918) 665·3465
TWX 910·997·1096
FAX (918) 663·1762

OHIO
Meta Technical Sales
Inc.
264 E. GarfIeld Rd.
Aurora. OH 44202
(216) 562·8772
FAX (216) 562·7129

PENNSYLVANIA
(EASTERN)
(see Southern New Jersey)

RHODE ISLAND
(see Massachusetts)

SOUTH CAROLINA
Rep. Inc.
6407 idlewild Road
Suite 425
Charlotte. NC 28202
(704) 563·5554
Telex 821765
EuyUnk 62637570
FAX (704) 535·7507

SOUTH DAKOTA
(see Minnesote)

TENNESSEE
Rep. Inc.
P.O. Box 728
113 South Branner Street
Jefferson City. TN 37760
(615) 475·9012
TWX 810·570·4203
EBSyUnk 62657620

TEXAS
West Associates
801 E. Campbell Rd. '350
Richardson. TX 75081
(214) 680·2800
Telex 910·997·0805
FAX (214) 699·0330

TEXAS
(AUSTIN)
West Associates
8000 Centre Park Dr. '250
Austin. TX 78754
(512) 339·6886
TWX 910·997·1041
FAX (512) 339·8951

11·3

III

DOMESTIC REPRESENTATIVES
TEXAS
(HOUSTON)

west Associates

4615 Southwest Frwy. 1720
Houston, TX 77027
(713) 62'1-5983
TXW 910-997-1030
FAX (713) 621-5895

UTAH
Luscombe Engineering Company
47 W. 200 South
Suite 326
Salt Lake City, UT 84101
(801) 532-4118 .

VERMONT

WASHINGTON D.C.

(see Msssechusetts)

(see Maryland)

VIRGINIA

WEST VIRGINIA

(see Maryland)

(see Ohio)

WASHINGTON

WISCONSIN

Northwest Marketing
Associates
12835 Bell-Red Road
Suite 330N
Bellevue, WA 98005
(206) 455-5846
FAX (206) 451-1130
TWX 910-443-2445,
NWMARKBVUE

Heartland Technical
Marketing, Inc.
3846 W. Wisconsin Avenue
Milwaukee, WI 53208
Phone (414) 931-0606

WYOMING
(see Colorado)

INTERNATIONAL REPRESENTATIVES
AUSTRALIA
TO BE DETERMINED

AUSTRIA
Bacher Electronics
Gesellschaft m.b.H.
BURO
Meldllnger Hauptstrabe 78
A·1120Wien
AUSTRIA
43-222-635646
FAX (43) 222-834276
Telex 847-131532

BELGIUM
Trade Mark Electronics (TME)
Bisschoppenhoffaan 357-359
2100 Antwerpen (Deuren)
BELGIUM
32-3-3251910
FAX (32) 3-3259542
Telex (846) 72713 TMEBEL B

DENMARK
Dltz Schweitzer
Vallensbaekvej 41
DK-2800 Glostrup
DENMARK
45-2-453044
FAX (45) 2·459206
Telex (855) -33257 SCHWEI OK

ENGLAND
Ambar Cascom Ltd.
Rabana Close
Aylesbury, Bucks. HP19 3RS
ENGLAND
0296434141
FAX (44) 296·29670
Telex 837427

FINLAND
OY Fintronic AB
Melkonketu 24A
SF0021 0 Helsinki
FINLAND
358-0-6926022
FAX (358) 0-674886
Telex 857·124224

11·4

FRANCE

SPAIN

Radio Equipements Antares (REA)
90, Rue de Vllliers
92300 LEVALLOI8-PERRET
FRANCE
33·1·47581111
FAX (33) 1-47587913
Telex (842) 620630

Selco
Paseo de la Habana 1 90-bajo
28036 Madrid
SPAIN
34·1·4054213,4094634
FAX (34) 1·2592284
Telex (831) 45458 (EPAP-E)

MICROEL
Av. de la Baltique
ZA de Courtsboeuf - B.P.3
91941 LES ULiS CEDEX
FRANCE
331-1-69070824
FAX (33) 1-69071723
Telex 692493F

SWEDEN

GERMANY
Kontron Halblelter GmBH
Breslauer Strasse 1 6
0·8057 Echlng b. Munchen
WEST GERMANY
49-89·31901381
FAX (49) 89-31901499
Telex (841) 5212467Z KHL 0

HOLLAND
Techmation Electronics B. V.
Bemhardstraat 11
417 5 Ed Haaften
Postbua 9, 1 75 ZG Haaften
HOLLAND
31-41-892222
FAX (31) 41·891872
Telex (844) -50423 TME NL

ISRAEL
Trltech Limited
5 Haarad Street
P.O. Box 53200
Tel-Aviv 61531
ISRAEL
972·3·498802
FAX (972) 3-497816
Telex (922) - 379123

ITALY
Silverstar
Via del Gracchl 20
20146 Milano
ITALY
39-2-4996
FAX (39) 2-435594
Telex 843·332189

Setron Sweden AB
Nora Torg 5
P.O. Box 2001
S-18202 Danderyd
Stockholm
SWEDEN
46-8-7530055
FAX (46) 8-7555594
Telex (854) 15339

SWITZERLAND
AnatecAG
Baarerstrasse 112
CH·6302Zug
SWITZERLAND
41-42-315477
FAX (41) 42-315647
Telex (645) -865299 ANA CH

JAPAN
Nippon Imex Corporation
Takeuchi Bldg. 4F
1-37-19 Metsubara
Setsgaya-Ku, Tokyo
156 JAPAN
81-3-321·4415
FAX (81) 3-325-0021
Telex (781) ·J23444 NIMEXCO

TAIWAN
Helm Engineering & Trading Co.
4F. 858, Tun HUB South Road
P.O. Box 13·192 Taipei
TAIWAN, R.O.C.
886·2-709-1888
FAX (886) 2·706-0465
Telex 28204 Helmtra
U.S. Contact: Jerry Shih
Supreme Co.

FAX (408) 262·8268

Honeywell

IJ

II

II

a

If

~ PLEASE 'NO-TE:

~

II

After March 1, 1988 Area Code ,
,
~
and Prefix will change to
(119) 540-(Last 4 digits)
jj
~
!!

"~

il~ll~

~~I

-

1IfIB:.·.I:t ~~=
, .......... 1Eo'

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~

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