1988_Samsung_Linear_IC_Data_Book_Vol_2 1988 Samsung Linear IC Data Book Vol 2

User Manual: 1988_Samsung_Linear_IC_Data_Book_Vol_2

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c8 SAMSUNO ·

Linear Ie k (VOL. 2)
Data Boo

1988
• Telecom
• Industrial
• Data Converter

Copyright 1987 by Samsung Semiconductor
All rights reserved. No part of this publication may be reproduced, stored in a retrieval
system, or transmitted in any form or by any means, electronic, mechanical, photo
copying, recording, or otherwise, without the prior written permission of Samsung
Semiconductor.
The information contained herein is subject to change without notice. Samsung
assumes no responsibility for the use of any circuitry other than circuitry embodied in
a Samsung product.
No other circuit patent licenses are implied.

SAMSUNG SEMICONDUCTOR
DATA BOOK LIST
I. Semiconductor Product Guide
II. Transistor Data Book
III. Linear IC Data Book
IV. MOS Product Data Book
V. High Performance CMOS Logic Data Book
. VI. MOS Memory Data Book
VII. SFET Data Book

LINEAR Ie DATA BOOK
VOLUME 1.
AUDIO ICs
VIDEO ICs

VOLUME 2.
TELECOM ICs
VOLTAGE REGURATORs
VOLTAGE REFERENCEs
OPERATIONAL AMPLIFIERs
COMPARATORs
TIMERs
. DATA CONVERTER ICs
MISCELLANEOUS ICs

TABLE OF CONTENTS
(VOLUME 2)
I. QUALITY AND RELIABILITY ........................................................ 19
II. PRODUCT GUIDE ............................................................................... 49
1. Function Guide ....................................................................................... 51
2. Cross Reference Guide ........................................................................... 60 .
3. Ordering Information ...........•.................................................................. 66

III. TELECOMMUNICATION ICs, ......................................................... 67
IV. INDUSTRIAL ICs ...............................................................................
1.
2.
3.
4.
5.

Voltage Regulators ...............................................................................
Voltage References ..............................................................................
Operational Amplifiers.•.........................................................................
Comparators ............... :........................................... :..............................
Timers ......................... :..........................................................................

275
277
393
407
468
496

V. DATA CONVERTER ICs .................. ~ ............................................ 519
VI. MISCELLANEOUS ICs ..........................................................:........ 593
VII. PACKAGE DIMENSIONS ............................................................. 617
VIII. SALES OFFICES and MANUFACTURER'S'
REPRESENTATIVES ;....................................................................... 629

(VOLUME 1) .
I. QUALITY AND RELIABILITY
II. PRODUCT GUIDE
1. Function Guide
2. Cross Reference Guide
3. Ordering Infonnation .

III. AUDIO ICs
IV. VIDEO ICs
V. MISCELLANEOUS ICs
VI. PACKAGE DIMENSIONS
VII. SALES OFFICES and MANUFACTURER'S
REPRESENTATIVES

ALPHANUMERIC INDEX
Device
KA33V
KA201A
KA301A
KA319
KA336-5_0
KA350
KA361
KA385-1.2
KA431
KA710C
KA733C
KA1222
KA2101
KA2102A
KA2103L
KA21 04
KA2105
KA2106
KA21 07
KA2130A
KA2131
KA2133
KA2134
KA2135
KA2136
KA2137
KA2153
KA2154
KA2181
KA2182
KA2183
KA2201B
KA2201/N
KA2206
KA22062
KA2209
KA2210
KA2211
KA2212
KA2213
KA22131
KA22135
KA2214
KA2220
KA2221
KA22211
KA2223
KA22233
KA22235
KA2224

Function
Silicon Monolithic Bipolar Integrated Circuit Voltage
Stabilizer for Electronic Tuner
Single Operational Amplifier
Single Operational Amplifier
Dual High Speed Voltage Comparator
Voltage Reference Diode
3 AMP Adjustable Positive Voltage Regulator
High Speed Voltage Comparator
Micropower Voltage Reference Diode
Programmable Precision Reference
High Speed Voltage Comparator
Differential Video Amplifier
Dual Low Noise Equalizer AMP
TV Sound IF AMP
TV Sound System
Sound Mute System for TV
Auto Power off and Sound Mute System for TV
Limiter AMP and Detector for a TV SIF
Dual Sound Multiplex for a TV SIF
DC Volume, Tone Control Circuit
TV Vertical Deflection System
TV Vertical Output Circuit
1 Chip Deflection System
Color TV Deflection Signal Processing IC
Horizontal Signal Processing IC
Low Noise TV Vertical Deflection System
TV Horizontal Processor
Video-Chroma Deflection System for a Color TV
Video-Chroma Deflection System for a Color TV
Remote Control Pre-AMP
Remote Control Pre-AMP
Remote Control Pre-AMP
0.5W Audio Power AMP
1.2W Audio Power AMP
2.3W Dual Audio Power AMP
4.5W Dual Power AMP
Dual Low Voltage Power AMP
5.5W Dual Power AMP
5.8W Dual Power AMP
0.5W Audio Power AMP
One Chip Tape Recorder System
Dual Pre-Power AMP for Auto Reverse
Dual Pre-Power AMP and DC Motor Speed Controller
1W Dual Power AMP
Equalizer AMP with ALC
Dual Low Noise Equalizer AMP
Dual Low Noise Equalizer AMP
5 Band Graphic Equalizer AMP
3 Band Dual Graphic Equalizer AMP
5 Band Graphic Equalizer AMP
Dual Equalizer AMP with ALC

Package
TO-92

8 DIP/8 SOP
8 DIP/8 SOP
14 DIP/14 SOP
TO-92
TO-3P
14 DIP/14 SOP
TO-92
TO-9218 DIP/8 SOP
14 DIP/14 SOP
14 DIP/14 SOP
8 SIP
14 DIP
14 DIP HIS
8 SIP
9 SIP
9 SIP
16 DIP
12 SIP
10 SIP HIS
10 SIP HIS
16 DIP HIS
18 DIP
12 SIP
12 ZDIP/F
16 DIP
42 DIP
42 DIP
8 SIP
8 SIP
8 SIP
8 DIP
8 DIP
12DIP/F
12 SIP HIS
8 DIP
12 SIP HIS
12 SIP HIS
9 SIP
14 DIP HIS
24 SOP
22 SDIP
14 DIP HIS
9 SIP
8 SIP
8 SIP
16 DIP
22 DIP
18 ZIP
14 DIP

Page
595
407
407
468
393
277
472
397
401
474
412
Vol.1 .
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1

ALPHANUMERIC INDEX
Device
KA22241
KA22251D
KA22261
KA2230
KA22421/D
KA22424
KA2243
KA2244
KA22441
KA2245
KA22461
'KA2247
KA22471
KA2248A/D
KA2249/D
KA2261
, KA2262
KA2263
KA2264/D
KA2265
, KA22682
KA2268N
KA2281
KA2283
KA2284
KA2285
KA2286
KA2287
KA2288
KA2303
KA23Q4
KA2401
KA2402
KA2404
KA2407
KA241 0
KA2411
KA2412A
KA2413
KA2418
KA2419
KA2425A/B
KA2580A
KA2588A
KA2605
KA2606
KA2615
KA2616

(Continued)
Function

Dual Equalizer AMP with ALC
Dual Pre-AMP for 3V Using
Dual Equalizer AMP with REC AMP
9-Program Music Selector
AM 1 Chip Radio
AM/FM 1 Chip Radio
AM/FM I F System
FM IF System for Car Radio
FM IF System for Car Stereo
FM IF System for Car Radio,
'
Electronic ,Tuning AM Radio Receiver for Car Stereo
FM IF/AM Tuner System
FM IF/AM Tuner System
3V FM IF/AM Tuner System
FM Front End for Portable Radio
FM Stereo Multiplex Decoder
FM Stereo Multiplex Decoder for Car Stereo
FM Stereo Multiplex Decoder
FM Stereo Multiplex Decoder
VCO Non-Adjusting FM Stereo Multiplex Decoder
1 Chip TV MPX Demodulator
1 Chip TV Sound MPX
5 DOT Dual LED Level Meter Driver
5 DOT Dual LED Level Meter Driver
5 DOT LED Level Meter Driver
5 DOT LED Level Meter Driver
5 DOT LED Linear Level Meter Driver
5 DOT LED Linear Levei Meter Driver
7 DOT LED Level Meter Driver
Toy Radio COntrol Actuator
Toy Radio Control Actuator
DC Motor Speed Controller
Low Voltage DC Motor Speed Controller
DC Motor Speed Controller
DC Motor Speed Controller
Tone Ringer
. Tone Ringer
Telephone Speech Circuits
Dual Tone Multi Frequency Generator
Tone Ringer with Bridge Diode
Tone Ringer with Bridge Diode
Telephone Speech Network with Dialer Inteiiace
8-Channel Source Drivers
8-Channel Source Drivers
SYNC Separator
SYNC Separator
LED and Lamp Driver
LED and Lamp Driver

Page

Package
9 SIP
16· DIP/16 SOP
16 DIP
22 DIP
16 DIP/16 SOP
16 DIP
16 DIP
9 SIP
16 ZIP
7 SIP
19 ZIP
16 DIP
16 DIP'
16 DIP/16 SOP
7 SIP/8 SOP
16 DIP
16 ZIP
9 SIP
9 SIP/16 SOP
16 DIP
28 DIP
28 DIP
16DIP
16 DIP
9 SIP
9SIP
9 SIP
9 SIP
16 DIP
9 SIP
9 SIP
8 DIP
8 DIP
TO-92L
' TO-126
8 DIP
8 DIP
14 DIP
16 DIP
8 DIP
8 DIP
18 DIP
18 DIP
20 DIP
9 SIP
9 SIP
9 SIP,
9 SIP

-

Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol: 1
69
69
75
83
108
108
122
599
599
Vol. 1
Vol. 1
Vol. 1
Vol. 1

ALPHANUMERIC INDEX
Device
KA2617
KA2618
KA2651
KA2803
KA2804
KA2911
KA2912
KA2913A
KA2914A
KA2915
KA2916
KA2917
KA2918
KA2919
KA2944
KA2945
KA2983
KA2988
KA6101
KA6102
KA3524
KA78540
KA78TXX
KA8301
KA8302
KA8401
KA9256
KAD0808
KAD0809
KAD0820A/B
KDA0800
KDA0801
KDA0802
KF351
KS555
KS555H
KS556'
KS5803A1B
KS5805A1B
KS5808
KS5812
KS5819
KS5820
KS5821
KS5824
KS7126
KS25C02

(Continued)
Function

LED and Lamp Driver
LED and Lamp Driver
Fluorescent Display Drivers
Low Power Consumption Earth Leakage ,Detector
Zero Voltage Switch
Video IF System for Color TV
Video IF Processor for BIW TV
Video and Sound IF AMP for Monochrome TV Receivers
Video IF +'SIF System
TV VIF & SIF & Deflection System
Video IF System for Color TV
Video and Sound IF AMP for Monochrome TV Receivers
Video IF + SIF System
VIF + SIF System for Color TV
Write & Read AMP
Video AMP
Switch less Recording/Play Back AMP
Chroma Signal Processor
Analog Interface Circuit for Teletex 'System
Analog Interface Circuit for'Teletex System
Regulator Pulse Width Modulator
Switching Regulator
3A Positive Voltage Regulator
Driver for VTR
Servo Control AMP
VTR Audio Switchless Recording/Play Back AMP
Dual Power Operational Amplifier '
8 Bit I'p·Compatible AID Converter with 8·Channel
Multiplexer
8 Bit I'p·Compatible AID Converter. with 8·Channel
Multiplexer
8 Bit High Speed I'P Compatible AID Converter with
Track/Hold Function
8 Bit D/A Converter
8 Bit D/A Converter
8 Bit D/A Converter
Single Operating Amplifier
CMOl3 Timer
CMOS Timer
CMOS Timer
Remote Control Transmitter
Telephone Pulse Dialer with Redial
Dual Tone Multi Frequency Dialer
Quad Universial Asychronous Receiver and Transmitter
Tone/Pulse Dialer with Redial
Tone/Pulse Dialer with Redial
Tone/Pulse Dialer with Redial
Universial Asychronous Receiver and Transmitter
3 1/2 Digit AID Conve,rter
8 Bit CMOS Successive Approximation Register

Package
9 SIP
9 SIP
18 DIP
8 DIP
8 DIP
16 DIP
14 DIP HIS
16 DIP
24 DIP
28 DIP
16 DIP
16 DIP
24 DIP
30 SSD
28 DIP
28 DIP
18 DIP
28 DIP
18'DIP
18 DIP
16 DIP
16 DIP
TO·220
10 SIP HIS
12 SIP
24 ZIP
10 SIP HIS

Page
Vol. 1
Vol. 1
604
607
610
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
,Vol. 1
285
306
312
Vol. 1
Vol. 1
Vol. 1
419

28 DIP

549

28 DIP

549

20 DIP

560

16 DIP
16 DIP
16 DIP
8 DIP/8 SOP
8 DIP/8 SOP
8 DIP/8 SOP
14 DIP/14 SOP
' 16 DIP/20 SOP
18'DIP
16 DIP
40 DIP
22 DIP/SDIP
18 DIP
22DIP/SDIP
24 DIP
40 DIP
16 DIP/24 SDIP

580
580
580
421
496
501
505
Vol. 1
130
146
152
162
172
162
180
568

586

;

ALPHANUMERIC INDEX
Device
KS25C03
KS25C04
KSV3100A
. KSV3110
KSV3208
KT3040J
KT3054J
KT3064J
KT5116J
LM211
LM224/A
LM239/A
LM248
LM2581~

LM293/A
LM311
LM317
LM323
LM324/A
LM339/A
LM348·
LM3581A/S
LM3861S/D
LM393/A1S
LM567C
LM567L
LM723
LM741C/ElI
LM2901
LM2902
LM2903
LM2904
LM3302
MC14581C/SII
MC1488
MC1489/A
MC3303
MC3361
MC3403

MC45581C/A/SII
MC78XX
MC78LXX
MC78MXX
MC79XX
MC79MXX
NE555
NE556
NE558

(Continued)

Function
8 Bit CMOS Successive Approximation Register
12 Bit CMOS Successive Approximation Register
H,igh-Speed AlD-DA Converter
High-Speed AlD-DA Converter
High-Speed AID Converter
PCM Monolithic Filter
COMBO CODEC
COMBO CODEC
wLaw Companding CODEC
Voltage Comparator
Quad Operational AmplHier
Quad Differential Comparator
Quad Operational Amplifier
Dual Operational Amplifier
Dual Differential Comparator
Voltage Comparator
3-Terminal Positive Adjustable Regulator
3-Terminal Positive Voltage Regulator
Quad Operational Amplifier
Quad Differential Comparator
Quad Operational Amplifier
Dual Operational Amplifier
Low Voltage Audio Power AMP
Dual Differential Comparator
Tone Decoder
Micropower Tone Decoder
Precision Voltage Regulator
Single qperationai Amplifier,
Quad Differential Comparator
Quad Operational Amplifier
Dual Differential Comparator
Dual Operational Amplifier
Quad Differential Comparator
Dual Operational Amplifier
Quad Line Driver
Quad Line Receiver
Quad Operational Amplifier
Low Power Narrow Band FMIF
Quad Operational Amplifier
Dual Operational Amplifier
3-Terminal 1A Positive Voltage Regulator
3-Terminal Positive Voltage Regulator
3-Terminal 0.5A Positive Voltage Regulator
3-Terminal Negative Voltage Regulator
3-Terminal 0.5A Negative'Voltage Regulator
Timer
Dual Timer
Quad Timer

Package

Page

16 DIP/24SDIP
24DIP/24SDIP
40 DIP
40 DIP
28 DIP
16 CERDIP
16 CERDIP
20 CERDIP
16 CERDIP
8 DIP/8 SOP
14 DIP/14 SOP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8 SOP/9 SIP
8 DIP/8 SOP
8 DIP/8 SOP
TO-220
TO-3P
14 DIP/14 SOP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8, SOP/9 SIP
9 SIP/8 DIP/8 SOP
8 DIP/8 SOP
8 DIP/S SOP
8 DIPj8 SOP
14 DIP/14 SOP
8 DIP/8 SOP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8 SOP.
8 DIP/8 SOP/9 SIP
14 DIP/14 SOP
8 DIP/8 SOP/9 SIP
14 DIPI14 SOP
14 DIP/14 SOP
14 DIPI14 SOP
16 DIP/16 SOP
14 DIP/14 SOP
8 DIP/8 SOP/9 SIP
TO-220
TO-92
TO-220
TO-220
TO-220
8 DIP/8 SOP
14 DIP/14 SOP
16 DIP/16 SOP

586
586
521
531
541
191
200
214
226
476
423
481
432
438
489
476
291
296
423
481
432
438
613
489
239
247

300
446
481
423
489
438
481
452
257
264
456
270
456
463
323
353
364
377
387
509
513
516

PRODUCT INDEX
1. Audio Application
Device
KA1222
KA2201B
KA2201lN
KA2206
KA22062
·KA2209
KA221 0
KA2211
KA2212
KA2213
KA22131
KA22135
KA2214
KA2220
KA2221
KA22211
KA2223
KA22233
KA22235
KA2224
KA22241
KA2225/D
KA22261
KA2230
KA22421/D
KA22424
KA2243
KA2244
KA22441
KA2245
KA22461
KA2247
KA22471
KA2248A1D
KA2249/D
KA2261
KA2262
KA2263
KA2264/D
KA2265
. KA2281
KA2283
KA2284
KA2285
KA2286
KA2287
KA2288
LM386/S/D
KA2303
KA2304
KA2401

. Function
Dual Low Noise Equalizer AMP
O.5W Audio Power AMP
1.2W Audio Power AMP
2.3W Dual Audio Power AMP
4.5W Dual Power AMP
Dual Low Voltage Power AMP
5.5W Dual Power AMP
5.8W Dual Power AMP
O.5W Audio Power AMP
One Chip Tape Recorder System
Dual Pre·Power AMP for Auto Reverse
Dual Pre·Power AMP and DC Motor Speed Controller
1W Dual Power AMP
Equalizer AMP with ALC
Dual Low Noise Equalizer AMP
Dual Low Noise Equalizer AMP
5 Band Graphic Equalizer AMP
3 Band Dual Graphic Equalizer AMP
5 Band Graphic Equalizer AMP
Dual Equalizer AMP with ALC
Dual Equalizer AMP with ALC
Dual Pre·AMP for 3V Using
Dual Equalizer AMP with REC AMP
9-Program Music Selector
AM 1 Chip Radio
AM/FM 1 Chip Radio
AM/FM IF System
FM IF System for Car Radio
FM IF System for Car Stereo
FM IF System for Car Radio
Electronic Tuning AM Radio Receiver for Car Stereo
FM IF/AM Tuner System
FM IF/AM Tuner System
3V FM IF/AM Tuner System
FM Front End for Portable Radio
FM Stereo Multiplex Decoder
FM Stereo Multiplex Decoder for Car Stereo
FM Stereo Multiplex Decoder
FM Stereo Multiplex Decoder
VCO Non-Adjusting FM Stereo Multiplex Decoder
5 DOT Dual LED Level Meter Driver
5 DOT Dual LED Level Meter Driver
.5 DOT LED Level Meter Driver
5 DOT LED Level Meter Driver
5 DOT LED Linear Level Meter Driver
5 DOT LED Linear Level Meter Driver
7 DOT LED Level Meter Driver
Low Voltage Audio Power AMP
Toy Radio Control Actuator
Toy Radio Control Actuator
DC Motor Speed Controller

Package

Page

8 SIP
8 DIP
8 DIP
12DIP/F
12 SIP HIS
8 DIP
12 SIP HIS
12 SIP HIS
9 SIP
14 DIP HIS
24 SOP
22 SDIP
.14 DIP HIS
9 SIP
8 SIP
8 SIP
16 DIP
22 DIP
18 ZIP
14 DIP
9 SIP
16 DIP/16 SOP
16 DIP
22 DIP
16 DIP/16 SOP
16 DIP
16 DIP
9SIP
16 ZIP
.7 SIP
19 ZIP
16 DIP
16 DIP
16 DIP/16 SOP
7 SIP/8 SOP
16 DIP
16 ZIP
9 SIP
9 SIP/16 SOP
16 DIP
16 DIP
16 DIP
9 SIP
9 SIP
9 SIP
9SIP
16 DIP
9 SIP/8 DIP/8 SOP
9 SIP
9 SIP
8 DIP

Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
613
Vol. 1
Vol. 1
Vol. 1

PRODUCT INDEX

(Continued)

1. Audio Appllcatlori

(Continued)

Device
KA2402
KA2404
KA2407

Function
Low Voltage DC Motor Speed Controller
DC Motor Speed Controller
DC Motor Speed Controller

Package
8 DIP
TO-92L
TO-126

Page
Vol. 1
Vol. 1
Vol. 1

2. Video Application
Device
KA2101
KA2102A
KA2103L
KA21 04
KA2105
KA2106
KA2107
KA2130A
KA2131
KA2133
KA2134
KA2135
KA2136
KA2137
KA2153
KA2154
KA2181
KA2182
KA2183
KA22682
KA2268N

KA2605
KA2606
KA2615
KA2616
KA2617
KA2618
KA2911
KA2912
KA2913A
KA29l4A
KA2915
KA2916
KA2917
KA2918
KA2919
KA2944
KA2945
KA2983
KA2988
KA6101,
KA6102
KA8301
KA8302
KA8401
KS5803A/B

Function
TV Sound IF AMP
TV Sound System
Sound Mute System for TV
Auto Power off and Sound Mute System for TV
limiter AMP and Detector for a TV SIF
Dual Sound Multiplex for a TV SIF
DC Volume, Tone Control Circuit
TV Vertical Deflection System
TV Vertical Output Circuit
1 Chip Deflection System
Color TV Deflection Signal Processing IC
Horizontal Signal Processing IC
Low Noise TV Vertical Deflection System
TV HOrizontal Processor
Video-Chroma Deflection System for a Color TV
Video-Chroma Deflection System for a Color TV
Remote Control Pre-AMP
Remote Control Pre-AMP
j'\emote Control Pre-AMP
1 Chip TV MPX Demodulator
1 Chip TV Sound MPX
SYNC Separator
SYNC Separator
LED and Lamp Driver
LED and Lamp Driver
LED and Lamp Driver
LED and Lamp Driver
Video IF System for Color TV
Video I F Processor for BIW TV
Video and Sound IF AMP for Monochrome TV Receivers
Video IF + SIF System
TV VIF & SIF & Deflection System
Video IF System for Color TV
Video and Sound IF AMP for Monochrome TV Receivers
Video IF+SIF System
VIF + SIF System for Color TV
Write & Read AMP
Video AMP
Swltchless Recording/Play Back AMP
Chroma Signal Processor
Analog Interface Circuit for Teletex System
Analog Interface Circuit for Teletex System
Driver for VTR
Servo Control AMP
VTR Audio Swltchless Recordlng/Play Back AMP
Remote Control Transmitter

Package
14 DIP
14 DIP HIS
8 SIP
9 SIP
9 SIP
16 DIP
12 SIP
10 SIP HIS
10 SIP HIS
16 DIP HIS
18 DIP
12 SIP
12 ZDIP/F
16 DIP
42 DIP
42 DIP
8 SIP
8SIP
8 SIP
28 DIP
28 DIP
9 SIP
9SIP
9 SIP
9 SIP
9SIP
9 SIP
16 DIP
14 DIP HIS
16 DIP
24 DIP
28 DIP
16 DIP
16 DIP
24 DIP
30 SSD
28 DIP
28 DIP
18 DIP
28 DIP
18 DIP
18 DIP
10 SIP HIS
12 SIP
24 ZIP
16 DIP/20 SOP

Page
Vol. 1
Vol. 1
VOl:, 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol.,l
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1
Vol. 1

PRODUCT INDEX

(Continued)

3. Telecommunication Application
Function.

Device
KA241 0
KA2411
KA2412A
KA2413
KA2418
KA2419
KA2425A/B
KS5805A/B
KS5808
KS5812
KS5819
KS5820
KS5821
KS5824
KT3040J
KT3054J
KT3064J
KT5116J
LM567C
LM567L
MC1488
MC1489/A
MC3361
KA2580A
KA2588A
KA2651

Package

Tone· Ringer
Tone Ringer
Telephone Speech Circuits
Dual Tone Multi Frequency Generator
Tone Ringer with Bridge Diode
.
Tone ·Rlnger with Bridge Diode
Telephone Speech Network with Dialer Interface
Telephone Pulse Dialer with Redial
Dual Tone Multi Frequency Dialer
Quad Universial Asychronous Receiver and Transmitter
Tone/Pulse Dialer with Redial
Tone/Pulse Dialer with Redial
Tone/Pulse Dialer with Redial
Universlal Asychronous Receiver and Transmitter
PCM Monolithic Filter
COMBO CODEC
COMBO CODEC
,.-Law Companding CODEC
Tone Decoder
Mlcropower Tone Decoder
Quad Line Driver
Quad Line Receiver
Low Power Narrow Band FM IF
8-Channel Source Drivers
8-Channel Source Drivers
Fluorescent Display Drivers

-

8 DIP
8 DIP
14 DIP
16 DIP
8 DIP
8 DIP
18 DIP
18 DIP
16 DIP
40 DIP
22 DIP/SDIP
18 DIP
22DIP/SDIP
24 DIP
16 CERDIP
16 CERDIP
20 CERDIP
16 CERDIP
8 DIP/8 SOP
8 DIP/8 SOP
14 DIP/14 SOP
14 DIP/14 SOP
16 DIP/16 SOP
18 DIP
20 DIP
18 DIP

Page
69
69
75
83
108
108
112
130
146
152
162
172
162
180
19'
200 .
214
226
239
247
257
264
270
599
599
604

4. Industrial Application
Device
KA201A
KA301A
KA319
KA336-5.0
KA350
KA361
KA385-1.2
KA431
KA710C
KA733C
KA3524
KA9256
KF351·
KS555
KS555H
KS556
LM211

Function
Single Operational Amplifier
Single Operational Amplifier
Dual High Speed Voltage Comparator
Voltage Reference Diode
3 AMP Adjustable Positive Voltage Regulator
High Speed Voltage Comparator
Micropower Voltage Reference· Diode
Programmable Precision Reference
High Speed Voltage Comparator
Differential Video Amplifier
Regulator Pulse Width Modulator
Dual Polt'l(er Operational Amplifier
Single Operating Amplifier
CMOS Timer
CMOS Timer
CMOS Timer
Voltage Comparator

Package

Page

8 DIP/8 SOP
8 DIP/8 SOP
14 DIP/14 SOP
TO·92
TO·3P
14 DIP/14 SOP
TO·92
TO·9218 DIP/S SOP
14 DIP/14 SOP
14 DIP/14 SOP
16 DIP
10 SIP H/S
8DIP/8·S0P
8 DIP/8 SOP
8 DIP/S SOP
14 DIP/14 SOP
8 DIP/8 SOP

407
407
463
393
277
472
397
401
474
412
285
419
421
496
501
505
476

PRODUCT INDEX
Industrial Application

(Continued)
(Continued)

Device
LM224/A
LM239/A
LM248
LM258/A
LM293/A
LM311
LM317
LM323
LM324/A
LM339/A
LM348
LM3581A/S
LM3931A1S
LM723
LM741C/ElI
LM2901
LM2902
LM2903
LM2904
LM3302
MC14581C/SII
MC3303
MC3403
MC45581CIAISIl
MC78XX
MC78LXX
MC78MXX
MC79XX
MC79MXX
KA78540
KA78TXX
NE555
NE556
NE558
KA2803
KA2804
KA33V

Function
Quad Operational Amplifier
Quad Differential Comparator
Quad Operational Amplifier
JDual Operational Amplifier
Dual Differential Comparator
Voltage Comparator
3-Terminal Positive Adjustable Regulator
3-Terminal Positive Voltage Regulator
Quad Operational Amplifier
. Quad Differential Comparator
Quad Operational Amplifier
Dual Operational Amplifier
Dual Differential Comparator
Precision Voltage Regulator
Single Operational Amplifier
Quad Differential Comparator
Quad Operational Amplifier
Dual Differential Comparator
iDual Operational Amplifier
Quad Differential Comparator
Dual Operational Amplifier
Quad Operational Amplifier
Quad Operational Amplifier
Dual Operational Amplifier
3-Terminal 1A Positive Voltage Regulator
3-Terminal Positive Voltage Rllgulator
3-Terminal 0.5A Positive Voltage Regulator
3-Terminal Negative Voltage Regulator
3-Terminal 0.5A Negative Voltage Regulator
Switching Regulator
3A Positive Voltage Regulator
Timer
Dual Timer
Quad Timer
Low Power Consumption Earth Leakage Detector
Zero Voltage Switch
Silicon Monolithic Bipolar Integrated Circuit Voltage
Stabilizer for Electronic Tuner

Package

Page

14 DIP/14 SOP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8 SOP/9 SIP
·8 DIP/8 SOP
8 DIP/8 SOP
TO-220
TO-3P
14 DIP/14 SOP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8 SOP/9 SIP
8 DIP/8 SOP
14 DIP/14 SOP
8 DIP/8 SOP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8 SOP
8 DIP/8 SOP/9 SIR
14 DIP/14 SOP' .
8 DIP/8 SOP/9 SIP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8 SOP/9 SIP
TO-220
TO-92
TO-220
TO-220
TO-220
16 DIP
TO-220
8 DIP/8 SOP
14 DIP/14 SOP
16 DIP/16 SOP
8 DIP
8 DIP
TO-92

423
481
432
438
489
476
291
296
423
481
432
438
489
300
446
481
423
489
438
481
452
456
·456
463
323
353
364
377
387
306
312
509
513
516
607
610
295

Package

Page

5. Data Converter Application
Device
KSV3100A
KSV3110
KSV3208
KAD0808
KAD0809
KAD0820A/B
KDA0800
KDA0801
KDA0802
KS25C02
KS25C03
KS25C04
KS7126

Function
High-Speed A/D-DA Converter
High-Speed AlD-DA Converter
High-Speed AID Converter
8 Bit I-'p-Compatible AID Converter with 8-Channel
Multiplexer
8 Bit I-'p-Compatible AID Converter with 8-Channel
Multiplexer
8,Bit High Speed I-'P Compatible AID Converter with
Track/Hold Function
8 Bit D/A Converter
8 Bit D/A Converter
8 Bit D/A Converter
8 Bit CMOS Successive Approximation Register
8 Bit CMOS Successive Approximation Register
12 Bit CMOS Successive Approximation Register
3 1/2 Digit AID Converter

40 DIP
40 DIP
28 DIP

521
531
541

28 DIP

549

28 DIP

549

20 DIP

560

16 DIP
16 DIP
16 DIP
16 DIP
16 DIP
24SDIP
40 OIP

580
580
580
586
586
586
568

•

.

QUALITY & RELIABILITY
"

;:

,1,'1

;~

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.:

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,,',

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,',

'

QUALITY and RELIABILITY
INTRODUCTION
Samsung's linear IG products are among the most reliable in the industry. Samsung has always made a commit·
ment to achieve the highest possible quality, reliability, and customer satisfaction with its products.
Extensive qualification, monitor and outgoing programs are used to scrutinize product quality and reliability.
·Stringent controls are applied to every wafer fabrication and assembly lot to achieve reproducibility, and therefore
maintain product reliability.
In this chapter, the quality and reliability programs established at Samsung will be discussed. In addition, a description
of reliability theory, reliability tests and various support efforts provides a broad framework from which to compre·
hend Samsung quality and reliability.
.
To better understand the Quality Department's role in product develoment and manufacturing, Ii detailed diagram
is listed below. As can be noted, Quality Engineering is involved in all phases, save that of initial product planning.

STEP

~
z

SALES

1

1

SPEC. REVIEW

:II!

~

.....a:

DESIGN

1
1

I

DESIGN REVIEW
1

z

PRODUCTION
CONTROL

PRODUCTION

I

COUNCIL FOR 'DEVELOPMENT

I
I

Cl

II.

OC/OA

1

MARKET SURVEY

I

~

"-

PROCESS ENG'S

QUALIFICATION FOR RAW MATERIAL

1

1

l

m

Q

I

TRIAL MFG

I'

EVALUATION & QUALIFICATION

1

z

~

STANDARDIZATION

1

~
~

APPROVAL

1

·II-----------------------l

"III
a:
"-

QUALIFICATION

1
1

I

z

S
u

MASS PRODUCTION

0

I~=P=R=O=C~==S=M=O=N=IT=OR==~~

"-

1

c·

I

CI

a:

:g
:II!

I
Iii

":II!a:

1

1

I

RELIABILITY TEST
LOT ACCEPTANCE TEST

FAILURE ANALYSIS

CLAIM

J

INCOMING INSP.

PROCESS CONTROL

:>

P.P

1

INITIATE CORRECTIVE ACTION

I

SHIPPING

1

CUSTOMER

1

C

Figure 1. Quality Assurance During

c8

SAMSUNG SEMICONDUCTOR

Develop~ent

21

I

QUALITY and RELIABILITY
QUALITY AND RELIABILITY PROGRAM
Since Samsung manufactures many different products using a variety of fab and assembly technologies, close
attention must be paid to avariety of (potential) reliability hazards. The Samsung quality and reliability department
has established a variety of procedures and programs to assess, understand, control, and eliminate reliability
problems.
The major categories of reliability program management are: '
a. Qualification program
b. Monitor program
c. Outgoing quality program

QUALIFICATION PROGRAM
Samsung' qualification procedures are used mainly to confirm the major characteristics and reliability attributes
of new technologies or products for introduction to Samsung manufacturing. The program is also utilited to
evaluate changes to existing technologies or raw materials. The purpose of this program is to simulate all relevant
user conditions, via accelerated and standard methods, prior to product shipment. The stresses used for qualification are detailed in following sections.

MONITOR PROGRAM
Twice per year, devices duplicate their qualification tests to obtain long-term reliability data for Linear ICs.
In this way historical data is collected and analyzed over all part types and thus assures the customer of ongoing
device quality.
These results are summarized in reliability reports issued periodically by Samsung Semiconductor.

OUTGOING QUALITY PROGRAM
All wafer lots are required to pass a "QC-reliability-gate" prior to product shipment. The purpose is to track "Lot·
by-lot" quality and reliability to catch any potential product anomaly at the factory site.
The customer can then expect only quality material to be delivered, from Samsung. Any lot that fails the procedure
l,isted below is scrutinized heavily, to make sure that corrective action takes place immediately.
By paying such close attention to every lot, product costs are kept at a minimum. Samsung's customer return rate
is extremely low, which is where our tough outgoing policy is most powerful. Such a tight clamp to protect our
customers is how we can assure that all Samsung's products are released with the highest confidence level possible.

HOPL 168HR
PCT 48HR
REJECT

(Corrective Action Required)

WAREHOUSE INCOMING INSPECTION

Figure 2. Linear Ie Outgoing Flow

c8

SAMSUNG SEMICONDUcroR

22

QUALITY and RELIABILITY
RELIABILITY TESTS
Samsung has established a comprehensive reliability program to monitor and ensure the ongoing reliability of the
linear IC family. This program involves not only reliability data collection and analysis on existing parts, but also
rigorous in-line quality controls for all products.
Listed below are details of tests performed to ensure that manufactured product continues to meet Samsung's
stringent quality standards. In line quality controls are reviewed extensively in later sections.
The tests run by the quality department are accelerated tests, serving to model "real world" applications through
boosted temperature, voltage, and/or humidities. Accelerated conditions are used to derive device knowledge through
means quicker than that of typical application situtations. These accelerated conditions are then used to assess
differing failure rate mechanisms that correlate directly with ambient conditions. Following are summaries of various
stresses (and their conditions) run by Samsung on linear IC products.

HIGH TEMPERATURE OPERATING LIFE TEST (HOPL)
(TJ=125°C, Vee = Vee max, static)
High temperature operating life test is performed·to measure actual field reliability. Life tests of l000HR to 2000HR
durations are used to accelerate failure mechanisms by operating the device at an elevated ambient temperature
(125°C). Data obtained from this test are used to predict product infant mortality, early life, and random failure
rates. Data are translated to standard operating temperatures via failure analysis to determine the activation
energy of each of the observed failures, using the Arrhenius relationship as previously discussed.

WET HIGH TEMPERATURE OPERATING LIFE TEST (WHOPL)
(Ta=85°C, R.H.=81%, Vee = Vee opt, statiC)
Wet high temperature operating life test is performed to evaluate the moisture resistanr.e characteristics of plastiC
encapsulated componenots. Long time testing is performed under static bias conditions at 85°C/81 percent relative
humidity with nominal voltages. To maximize metal corroSion, the biasing configuration utilizes low power levels.

INTERMITTENT OPERATING LIFE (IOPL)
(Pmax, 25°C, 2min on/2 min off)
This test is normally applied to scrutinize die bond thermal fatigue. A stressed device undergoes an "ON" cycle,
where there is thermal heating due to power dissipation, and an "OFF" cycle, where there is thermal cooling due
to lack of inputted power. Die attach (between die and package) and bond attach (between wire and die) are the
critical areas of concern.

HIGH TEMPERATURE STORAGE TEST (HTS)
(Ta = 125°C, UNBIASED)
High temperature storage is a test in which devices are subjected to elevated temperatures with no applied bias.
The test is used to detect mechanical instabilities such as bond integrity, and process wearout mechanisms.

PRESSURE COOKER TEST (PCT)
(121°C, 15PSIG, 100% R.H., UNBIASED)
The pressure cooker test checks for resistance to moisture penetration. A highly pressurized vessel is used to
force water (thereby promoting corrosion) into packaged devices located within the vessel.

TEMPERATURE CYCLING (TIC)
(-65°C to + 150°C, AIR, UNBIASED)
This stess uses a chamber with alternating temperatures of - 65°C and + 150°C (air ambient) to thermally cycle
devices within it. No bias is applied. The cycling checks for mechanical integrity of the packaged device, in
particular bond wires and die attach, along with metallpolysilicon microcracks.

THERMAL SHOCK (TIS)
(-65°C to + 150°C, LIQUID, UNBIASED)
This stress uses a chamber with alternting temperatures of - 65°C to + 150°C (liquid ambient) to thermally cycle
devices within it. No bias is applied. The cycling is very rapid, and primarily checks for die/package compatibility.

c8

SAMSUNG SEMICONDUCTOR

23

I

. QUALITY and RELIABILITY

RELIABILITY TEST RESULTS·
This section is divided into two parts-actual and predicted test results. Actual test results are those derived via
accelerated stressing done by the
department. Predicted results are calculated by taking actual test results
and derating them using statistical and mathematical models to determine device performance in "real-time" user
conditions.

ac

ACTUAL TEST RESULTS
Stress

Conditions

HOPL

Tj = 125°C
. Vcc = Vee max

(KA2102A)
Number of
Devices

Number of Device
Hours/Cycles

Number of
Failures

% Failures per
l000HRS (Cycles)
(60% UCL)

100

100,000

0

0.91%/1K HR

WHOPL

85° C/81 % R.H.
Vcc = Vee opt

100

100,000

0

0.91%I1K HR

·IOPL

Ta=25°C
Vee = Vee max

100

100,000

0

0.91%/1K HR

HTS

Ta= 125°C
Unbiased.

100

100,000

0

0.91%/1K HR

PCT

121°C
15 PSIG

100

16,800

0

5.4 %/1K HR

TIC

-65°C to 150°C
Air to Air

100

10,000

0

9.1 %/1K CL

TIS

:... 65°C to 150°C
Liquid to Liquid

100

10,000

0

9.1 %/1K CL

PREDICTED .TEST RESULTS
The Arrhenius equation, which is reviewed in another seotion of this chapter, can be applied to derive typical "userconditio(l" device failure rates.
STESS: HOPL
100,000 Device Hours at 125°C
Average Activation Energy: 1.(> eV.
De-Rating to User Conditions Yields:
55°C Operation

70°C Operation
Equivalent
Device Hours

% Failures Per
1000 Hours
(60% UCL)

"FITs

""MTBF.
(Years)

Equivalent
Device Hours

% Failures Per
1000 Hours
(600% UCL)·

"FITs

""MTBF
(Years)

10.7 x 1()6

0.0084

84

1359

50.4 x 106

0.0018

18

6342

• FIT

: Failure in time or failure unit. Represents
the number of failures expected for 109 (one
billion) device hours.
•• MTBF: Mean time between failures.

c8

SAMSUNG SEMICONDUCTOR

24

QUALITY and RELIABILITY
RELIABILITY AND PREDICTION THEORY
RELIABILITY
Reliability can be loosely characterized as long term product quality.
There are two types of reliability tests: those performed during design and development, and those carried out
in production. The first type is usually performed on a limited sample, but for long periods or under very accelerated
conditions to investigate wearout mechanisms and determine tolerances and limits in the design process. The
second type of tests is performed periodically during production to check, maintain, and improve the assured quality
and reliability levels. All reliability tests performed' by Samsung are under conditions more severe than those
encountered in the field, and although accelerated, are chosen to simulate stresses that devices will be subjected
to in actual operation. Care is taken to ensure that the failure modes and mechanisms are unchanged.

FUNDAMENTALS
'A semiconductor device is very dependent on its conditions of use (e.g., junction temperature, ambient temperature, voltage, current, etc.). Therefore, to predict failure rates, accelerated reliability testing is generally used. In
accelerated testing, special stress conditions are considered as parametrically related to actual failure modes.
Actual operating life time is predicted using this method. Through accelerated stresses, component failure rates
are ascertained in terms of how many devices (in percent) are expected to fail for every 10pD hours of operation.
A typical failure rate versus time of activity graph is shown below (the so-called "bath tub curve")
(t)

Reduction due to
Failure ...._......l. . ._ _ _ _ _-,:-_ _ _ _....",,_-,-_ _ preventive maintenance
rate
m 1

=

S

" .. '

Specified
Failure Rate

emlcond- - - oct
(m:::: o.5_o%feVlces

Initial
Random Failure period
Failure period

Wear-Out Failure period

Figure 3_ Failure Rate Curve ("Bath Tub Curve")

During their initial time period, products are affected by "infant mortality," intrinsic to all semiconductor technologies.
End users are ,very sensitive to this parameter, which causes early assembly/operation .failures in their own
system. Perl~dically, Samsung reviews and publishes life time resultll. The goal is a steady shift of the limits as
shown below.

=~;:m

\1'":

J
---,Ir-/::,.-t-----/

I

I

I

I

!---t

/::,.:

failure rate

--TIME

Figure 4. Failure Rate

c8

SAMSUNG SEMICONPUCTOR

25

QUALITY and RELIABILITY
ACCELERATED HUMIDITY TESTS
To evaluate the reliability of products assembled in plastic packages, Samsung performs accelerated humidity
stressing, such as the Pressure Cooker, Test (PCT) and Wet High Temperature Operating Life Test (WHOPL).
Figure 5 shows some results obtained with these tests, which illustrate the improvements in recent years. These
'improvements result mainly from the intro.Quction of purer molding reSins, new process methods, and improved
cleanliness.
10- 5

--

~ VI
I

R-

-.10- 6

~

5

ff.~

~

~10- 7

::

fi:

1/:"

t;0

~

R:
W

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ao

100

ILj
"R:~

10- 8

~~'

~

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[@

'I. 'ff. rl

5

~'S.

5

rl
10-

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,,'":1

5

• 25

40

.,

~

60

125 150

1ao 1200 Til C)

Figure 5. Improvement In Humidity Reliability

ACCELERATED TEMPERATURE TESTS
Accelerated temperature tests are carried out at temperatures ranging from 75°C to 200°C for up to 2000 hours.
These tests allow Samsung to evaluate reliability rapidly and economically, as failure rates are strongly dependent
on temperature.
The validity of these tests is demonstrated by the good correlation betw~n data collected in the field and laboratory
results obtained using the Arrhenius model. Figure 6 shows the relationship between failure rates and temperatures
obtained with this model.

11eac

,,

99.9
,99

90

1982
1985

~

L

If

1988

L

V.....-: iI'

0,1
10

10'

HOURS

Figure 6. Failure Rate Versus Temperature

c8

SAMSUNG SEMICONDUCTOR

26

QUALITY and RELIABILITY
FUNDAMENTAL THEORY FOR ACCELERATED TESTING
Accelerated life testing is powerful because of its strong relation to failure physics. The Arrhenius model, which
is generally used for failure modelling, is explained below.

1. Arrhenius model
This model can be applied to accelerated Operating Life Tests and uses absolute (Kelvin) temperatures.
L = A + EalK·Tj
L : Lifetime
A : Constant
Ea : Activation Energy
K : Boltzman's constant
Tj : Absolute Junction temperature
If Lifetimes L1 and L2 correspond to Temperatures T1 and T2:
L1 = L2 exp

Ea

1

K (1'1 -

1
T2 )

Lifetime(L)

Temperature 11T (OK-1)
Actual junction temperature should always be used, and can be computed using the following relationship.
Tj=Ta+(Px Bja)
Where Tj = Junction temperature
Ta = Ambient temperature
, P = Actual power consumption
Bja=Junction to Ambient thermal resistance (typica"y 100 degrees celsius/watt for a 16-Pin PDIP).
2. Activation Energy Estimate
Clearly the choice of an appropriate activation energy, Ea, is of paramount importance. The different mechanisms
which could lead to circuit failure are characterized by specific activation energies whose values are published
in the literature, The Arrhenius equation describes the rate of many processes. responsible for the degradation
and failure of electronic components. It follows that the transition of an item from an initially stable condition to
a defined degraded state occurs by a thermally activated mechanism. The time for this transition is given by an
equation of the form:
MTBF = B EXP (EalKT)
MTBF = Mean time between failures
B
= Temperature-independent constant
MTBF can be defined as the time to suffer a device degradation. The dramatic effect of the choice of the Ea va!ue
can be seen by plotting the MTBF equation. The acceleration effect for a 125°C device junction stress with respect
to 70°C actual device junction operation is equal to 1000 for Ea=1eV and 7 for Ea=0.3eV.

c8

SAMSUNG SEMICONDUCTOR

27

I

. QUALITY and RELIABIUTY

Some words of caution are needed about published values of Ea:
A. They are often related to high-temp tests where a single Ea (with high value) mechanism has become dominant.
B. They are specifically related to the devices produced by that supplier (and to Its technology) fo~ a given period
of time
..
C. They could be modified by the mutual action of other stresses (voltage, mechanical, etc.)
D. Field device-application conditlon(s) should be considered.

(Activation energy for each failure mode)
THE CORRECT PROCEDURE
Failure Mechanism

Ea

Contamination
Polarization
Aluminum Migration
Trapping
Oxide Breakdown
Silicon Defects

1-1.4 eV
1 eV
0.5 -1 eV
1 eV
0.3 eV
0.3-0.5 eV

. ACCELERATED TEST

I

CALCULATED AT TEST CONDITIONS
AND WITH A CERiAiN CONFIDENCE
LEVEL
FAILURE ANALYSIS

I

CHOICE OF Ea---CALCULATED AT OTHER
TEMPERATURES
Time

1.4 e"r -leV

1()6

/

1()6
l;

~c

104

~
~

1()3

0.8e~

/
./

./
.O.5~

0

""
-<

102

10'

l()1l

V

J

II

. 250

'/

/

./

./

./

....

~

200 175 150125.

100

0.4 eY:lii!!
0.3eV-

",

75

50

T("C)

Junction 1;emperature

Figure 7. Life Hours

c8

SAMSUNG SEMICONDUCTOR

28

QUALITY and RELIABILITY
Failure Rate Prediction
AccEllerated testing defines the failure rate of products. By derating the data at different conditions, the life
expectancy at actual operating conditions can be predicted. In its simplest form the failure rate (at a given temperatlJre)
is:
N
FR=1)H
Where FR
N

=Failure Rate
=Number of failures

o = Number of components
H = Number of testing hours

If we intend to determine the FR at different temperatures, an acceleration factor must be considered. Some failure
modes are accelerated via temperature stressing based upon the accelerations of the Arrhenius Law.
For two different temperatures:
FR (T1) = FR (T2) exp

Ea

1

If ( T2

1
- T1 )

FR (T1) is a point estimate, but to evaluate this data for an interval estimate, we generally use a X2 (chi square)
.
distribution. An example follows:
Failure Rate Elaluation
Unit: %/1000HR
Dev. x Hours
at 125°C

Fail

1.7x1OS

2

Failure Rate at 60% Confidence Level
Point Estimate
0.18

I
I

85·C
0.0068

I
I

70·C
0.0018

I
I

55·C
0.00036

The activation energy, from analYSis, was chosen as 1.0 eV based upon test results. The failure rate at the lower
operating temperature can be extrapolated by an Arrhenius plot.
.

c8

SAMSUNG SEMICONDUCTOR

29

I

QUALITY and RELIABILITY
PROCESS CONTROL
GENERAL PROCESS CONTROL
.

'

,

.

The general process flow in Samsung is shown in Figure 8. This illustration contains the standard process flow
from incoming parts and materials to customer shipment.

Acceptance inspection (according to acceptance inspection plan)
Process quality control
• Check of each condition by process quality control procedures
• Process insPection
• Lot control
• Equipment calibration and maintenance
100% Electrical Die Sorting
Process Quality Control and screening of infant mortality defects
• Mechanical screen
• Thermal shock
• Burn·in
100% package sorting of electrical characteristics and marking
Reliability monitoring
1. PRT (Process Reliability Testing)
2. DRT (Device Reliability Testing)
• High Temperature Operating Life Test
• Environmental test
• Life Test
Finished Goods
Incoming
Inspection

Sampling Inspection
• Dimensions
• Visual
• Electrical characteristics
• Periodic calibration of measuring equipment
Stock control
• Age control
Sampling Inspection (when applicable)

Shipment
Figure 8. General Process Flow CharI

c8

SAMSUNG SEMICONDUCTOR

30

QUALITY and RELIABILITY
WAFER FABRICATION
Process Controls
The Quality Control program utilizes the following methods of control to achieve its previously stated objectives:
process audits, environmental monitors, process monitors, lot acceptance inspections, and process integrity audits.
Definitions
The essential method of the Quality Control Program is 'defined as follows:
1. Process Audit-Performed on all operations critical to product quality and reliability.
2_ Environmental Monitor-Monitors concerning the process environment, i.e., water purity, temperature, humidity,
particle counts.
3. Process Monitor-Periodic inspection at designated process steps' for verification of manufacturing inspection
and maintenance of process average. These inspections provide both attribute and variable data.
4. Lot Acceptance-Lot-by-Iot sampling. This sampling method is reserved for those operations deemed as critical,
and require special attention.
Environmental Monitor
Spec_ Limit

Control Item

Process
Clean Room

•
•
•
•

0.1. Water

• Particle
• Bacteria
• Resistivity

Temperature
Humidity
Particle
Air Velocity

•
•
•
•

Individual
Individual
Individual
Individual

Insp_ Frequency
24
24
24
24

Spec.
Spec.
Spec.
Spec.

• 5 ea/50ml (0.81')
• 50 colonies/100m I (0.451')
• Main (Line): More than
16 Mohm-cm
• Using pOint: More than
14 Mohm-cm

Hrs.
Hrs.
Hrs .
Hrs.

24 Hrs.
Weekly
24 Hrs.
24 Hrs.

• Instruments
• FMS (Facility Monitoring System) HIAc/ROYCO
• CPM (Central Particle Monitoring System-Dan Scientific)
• Liquid Dust Counter Etch Rate
• Filtration System for Bacterial check
• Air Particle counter
• Air Velocity meter
Process Monitor

Photo

•
•
•
•
•
•

Etch

• Etchant Temp.
• Etch Rate
• Spin Dry~r N2 Flow
RPM
• Hard Bake Temp ..
N2 Flow

c8

Spec_ Limit

Control Item

Process

Aligner N2 Flow Rate
Aligner Vacuum
Aligner Air
Aligner Pressure
Aligner Intensity
Coater Soft Bake
Temperature
Vacuum

SAMSUNG SEMICONDUCTOR

Insp_ Frequency

•
•
•
•
•
•
•
•

Individual
Individual
Individual
Individual
Individual
Individual
Individual
Individual

Spec.
Spec.
Spec.
Spec .
Spec.
Spec.
Spec.
Spec.

Once/Shift
Once/Shift
Once/Shift
Once/Shift
Once/Shift
Once/Shift
Once/Shift
Once/Shift

•
•
•
•
•
•

Individual
Individual
Individual
Individual
Individual
Individual

Spec.
Spec.
Spec.
Spec.
Spec.
Spec.

Once/Shift
Once/Shift
Once/Shift
Once/Shift
Once/Shift
Once/Shift

31

I

QUALITY and RELIABILITY
Process Monitor (Continued)
Control Item

Spec. Limit

Insp. Frequency

Thin Film

• Cooling Water Temp.
• .Thickness

·26±3°C
., Individual Spec.

Once/Shift
Once/Shift

CVD

• Pin Hole
• Thickness

• Individual Spec.
• Individual Spec.

Once/Shift
Once/Shift

Diffusion

• Tube Temp.
• C·V Plot Run
Tube
• Sheet Resistance
• Thickness

•
•
•
•
•

Once/Shift
Once/Shift
Oncel1Odays
Once/Shift
Once/Shift

Process

Individual
Individual
Individual
Individual
Individual

Spec.
Spec.
Spec.
Spec.
Spec.

Raw Material Incoming Inspection
1. Mask Inspection
, Defect Detection

Registration

Critical
Dimension

• Pinhole & Clear-extension
• Opaque Projections &
SpOtS
• Scratch/Particle/Stain
• Substrate Crack/Glass·chip
• Others
• Run·out
(X-Y Coordinate)
• Orthogonality
• Drop-in Accuracy
• Die Fit/Rotation
• Critical Dimension

All Masks

.'

• Defect Size::s;1.5,.m
• Defect Density
::s;O.124EA1cm 2

±O.75,.m

20%
'. All New Masks

AI,I Masks

±O.75,.m
±O.50,.m'
±O.50,.m
Purchasing Spec.

• Instrument
• Auto mask Inspection system for defect-detection (NJS 5MD-44)
• Comparator for registration (MVG 7X7)
• Automatic IInewidth measuring system for CD (MPV-CD)
2. Wafer Inspection
Purpose

Insp. Items

Sample

Structural

• Crystal'lographic; Defect

All Lots

• Sirtl Etch

Electrical

• Resistivity
• Conductivity

All Lots

• Monitor Water

Dimensional

•
•
•
•

Thickness
Diameter
Orientation
Flatness

All Lots

TTV, NTV, Epi-thickness

Visual

• Surface Quality
• Cleanliness

Remarlts

TIR (FPD)
Local Slope
All Lots

Purchasing Spec.

• Instrument,
• 4 point probe for resistivity (Kokusai VR40A, Tencor sonogage, ASM 4FPP)
• Flatness measuring system (Siltec)
• Epi. layer thickness gauge (Digilab FTG-12, Qualimatic S-1OO)
• Automatic Surface Insp. System (Aeronca Wis-150)
• Non-contact thickness gauge (ADE6034) ,

c8

SAMSUNG SEMICONDUCTOR

32

QUALITY and RELIABILITY
In·Process Quality Inspection (FAB)
1. Manufacturing Section

Process Step

Frequency

Process Control Insp.

Oxidation

Oxide Thickness

All Lots

Diffusion

Oxide Thickness
Sheet Resistance
Visual

All Lots
All Lots
All Lots

Photo

Critical Dimension
Visual
Mask Clean Inspection

All Lots (MaS)
All Lots
All Masks with Spot Light (MaS)
or Microscope (BIP)

Etch

Critical Dimension
Visual

All Lots
All Wafers

Thin Film

Metal Thickness
Visual

All Lots
All Lots

Ion Implant

Sheet Resistance

All Lots (Test Wafer)

Low Temp.
Oxide

Thickness

All Lots

Visual

All Lots

E·Test

Electrical

Fab. Out

Visual

~haracteristics

All Lots
All Wafers

2. FAB, QC Monitor/Gate

Process Step

FAB, QC Insp.

Frequency

Oxidation

Oxide Thickness
C·V Test on Tubes
Visual

Once/Shift
Once/10 Days and After CLN
Once/Shift

Diffusion

Oxide Thickness
C·V Test on Tubes
Visual

Once/Shift
Once/10 Days and After CLN
Once/Shift

Photo

Critical Dimension
Visual
Mask CLN Inspection

All Lots (MaS)
Once/Shift
All Masks After 10 Times Use

Etch

Critical Dimension
Visual

All Lots (MaS)
All Lots

Thin Film

C·V Test on Tubes
on Lots
Reflectivity

Once/10 Days and After CLN
Once/Shift
Once/Shift

Low Temp.
Oxide

Refractive Index,
Wt% of Phosphorus
Visual

1 Test Wafer/Lot
1 Test Wafer/Lot
1 Test Wafer/Lot

E·Test

Measuring Data

All Lots

Calibration

Instrument for Thickness
and C.D. Measuring

Once/week

c8.SAMSUNG SEMICONDUCTOR

33

.QUALITY and RELIABILITY
3. Photo/Etch process quality control

Process Flow

Process Step

ac Monitor/Gate

Prebake

Oven PM, Temperature
Time

Photo Resist {PRJ
-spin

Thickness Machine PM

Soft Bake

Oven PM, Temperature
Time

Temp. N2 Flow Rate

Align/Expose

Light Uniformity
Alignment, Focus Test
Mask Clean Inspection
Mask Clean Exposure
Light Intensity

Ught Intensity
Mask Clean Insp.

Develop

.

MFG. Control Item

. Equipment PM
Solution Control

Develop
Check

Oven Particle Temp.
N2 Flow Rate

Vacuum

PRIC.D.'S Alignment
Particles
Mask and Resist Defects

QC Inspection

Critical Dimension (CD)

Hard Bake

Oven PM, Temperature
Time

Temp.
N2 Flow Rate

Etch

Etch rate, Equipment
PM & Settings, Etch
Time to Clear

Etchant Temp.
Etch Rate

Inspection

Over/Under

PR Strip

Machine·PM

Final Check

C.D.'S Over and under
Etch, Particles;
PR Residue, Defects,
Scratches

QC Inspection

Same as Final Check,
However, More Intense
on limited Sample
Basis. (AQL 6.5%)

Note: PM represents Preventive Maintenance
4. Reliability·related Interlayer Dielectric, Metallization, and Passivation Process Quality Control Monitor

Item
Wt% Phosphorus Content of the Dielectric Glass

1/Shift

Metallization Interconnect

1/Month

AI Step Coverage

1/Month

Metallization Reflectivity

c8

Frequency

1/Shift

Passivation Thickness and Composition

1/Shift

Thin Film Defect Density

1/Shift

SAMSUNG SEMICONDUCTOR

34

QUALITY and RELIABILITY
Figure 9. General Wafer Fabrication Flow
Process Step

Process Flow

Major Control Item

I

Wafer and Mask
Input

Starting Material
Incoming Inspection

Mask: (See mask Inspection)
Wafer: (See wafer Inspection)

Wafer Sorting and
Labelling·

Resistivity

Initial Oxidation

Oxide Thickness

Photo

• (See manufacturing section)
• (See FAB, QC Monitor/gate)

Inspection

• Critical Dimension
• Visual/Mech - Major: AQL 1.0%
- Minor: AQL 6.5%

QC Gate

• Critical Dimension

Etch

• (See manufacturing section)
• (See FAB, QC Monitor/gate)

Inspection

• Critical Dimension
• Visual/Mech - Major: AQL 1.0%
- Minor: AQL 6.5%

QC.Gate

• Critical Dimension
• Visual/Mech

Diffusion
Metalizatlon

• (See in·process Quality Inspection)

E·test

• Electrical Characteristics

Diff'n
Metal

9

ciS SAMSUNG SEMICONDUCTOR

35

QUALITY and RELIABILITY
Figure 9. General Wafer Fabrication Flow (Continued)
Process Flow

<>

/

Process Step

Major Control Item

OC Gate

• Electrical Characteristics

Back-Lap

• Thickness

Back Side Evaporation

• Thickness, Time
Evaporation Rate

Final Inspection

• All Wafers Screened
(Visual/Mech)

OC Fab. Final Gate

• Visual/Mech.
- Major: AOL 1.0%
- Minor: AOL 6.5%

'

EDS
(Electrical Die Sorting)

OC Gate

• Function Monitor

Sawing
"

Inspection

• Chip Screen

OC Final Inspection

•
•
•
•

AOL 1.0%
Fab. Defect
Test Defect
Sawing Defect

Die Attach

c8

SAMSUNG SEMICONDUCTOR

36

QUALITY and RELIABILITY
ASSEMBLY
The process control and inspection points of the assembly operation are explained and listed below:
1. Die Inspection:
Following 100% inspection by manufacturing, in-process Quality Control samples each lot according to internal
or customer specifications and standards.
2. Die Attach Inspection:
Visual inspection of samples is done periodically on a machine/operator basis. Die Attach techniques are monitored
and temperatures are verified.
3. Die Shear Strength:
Following Die Attach, Die Shear Strength testing is performed periodically on a machine/operator basis. Either
manual or automatic die attach is used.

DIE ADHESIVE THICKNESS MONITOR RESULTS. (JEOL SEM, JSM IC845)
4. Wire Bond Inspection:
Visual inspection of samples is complemented by a wire pull test done periodically during each shift. These
checks are also done on a machine/operator basis and XR data is maintained.
5. Pre-SeaIfPre-Encapsulation Inspection:
Following 100% inspection of each lot, samples are taken on a lot acceptance basis and are inspected
according to internal or customer criteria.

WIRE LOOP MONITOR RESULTS.

ciS

SAMSUNG SEMICONDUCTOR

CROSS SECTION INSPECTION FOR BALL BOND.

37

I

QUALITY and RELIABILITY
6. Seal Inspection:
Periodic monitoring of the sealing operation checks the critical temperature profile of the sealing oven for both
glass and metal seals.·
7. Post·Seal Inspection:
Subsequent to a 100% visual inspection, In-Process Quality Control samples each for conformance to visual
criteria.
'

X-RAY MONITOR RESULT.'tPHILIPS MG161)
8. General Assembly Flow is shown in Figure 11.
Sampling Plans
1. Sampling plans are based on an AQL (Acceptable Quality Level) c,oncept and are determined by internal or by
customer specifications.
2. Raw Material Incoming Inspection. (continued)
Material

\

Inspection liem

Lead Frame

1)
2)
3)
4)

Wafer

1) Visual Inspection

AQL 0.65%

1) Visual Inspection
2) Bond Pull Strength Test
3) Bondability Test

n:5, C=O
n: 13, C=O
Critical Defect: 0.65%
Major Defect: 1.0%
Minor Defect: 1.5%
n: 5, C=O

AulAI
Wire

Vjs,ual Inspection
Dimension Inspection
Function Test
Work Test

\

4) Chemical Composition Analysis
1) Visual Inspection.
,2) Moldability Test
Molding Compound
3) Chemical Composition Analysis

c8

Acceptable Quality Level

SAMSUNG SEMICONDUCTOR

LTPD
LTPD
LTPD
LTPD

10%,
20%,
20%,
20%,

C=2
C=O
C=O
C=O

,

n: 5, C=O
Critical Defect: 0.15%
Major Defect: 1.0%
Minor Defect: 1.5%
n: 5, C=O

38

QUALITY and RELIABILITY

I
MOLDING COMPOUND INCOMING INSPECTION
(THERMAL ANALYSER, DUPONT 9900)
(Continued)

Material

Inspection Item
Visual Inspection
Dimension Inspection
Electro-Static Inspection
Hardness Test

Packing Tube
& Pin

1)
2)
3)
4)

Solder

1) Visual Inspection
2) Weight Inspection
3) Chemical Composition Analysis

LTPD 20% C=O
LTPD 20% C=O
LTPD 20% C=O

Flux

1) Acidity Test
2) Specific Gravity Test
3) Chemical Composition AnalYSis

LTPD 20% C=O
LTPD 20% C=O
LTPD 20% C='U

Solder Preform

1) Visual Inspection
2) Work Test
3) Chemical Composition Analysis'

AOL 1.0%
AOL 1.0%
AOL 1.0%

Coating Resin

1) Visual Inspection
2) Work Test
3) Chemical Composition Analysis

AOL 1.0%
AOL 1.0%
AOL 1.0%

1) Work Test

2) Mark Permanencx Test

Critical Defect: 0.15%
Major Defect: 1.0%
Minor Defect: 1.5%
n: 5, C=O

Chip Carrier

1)
2)
3)
4)

Visual Inspection
Dimension Inspection
Electro-Static Inspection
Hardness Test

LTPD 15% C=2
LTPD 15% C=O
n: 5, C=O
n: 5, C=O

Vinyl Pack

1) Visual Inspection
2) Work Test
3) Electro-Static Inspection

LTPD 20% C=O
LTPD 20% C;=O
LTPD 15% C=O

Ag Epoxy

1) Work Test
2) Chemical Composition Analysis

n:8, C=·O
n:8, C=O

Letter Marking

1) Visual Inspection
2) Work Test

Spare Parts
& Others

1) Dimension Inspection
2) Visual Inspection

Marking Ink

..

c8

Acceptable Quality Level

SAMSUNG SEMICONDUCTOR

LTPD 15%, C=2
LTPD 15% C=2
n: 5, C=O
n: 5, C=O

n:5, C=O
n:5, C=O

39

QUALITY and RELIABILITY
3. In·Process Quality Inspection'
A. Assembly Lot Acceptance Inspection
(1) Acceptance quality level for wire bond gate inspection

Defect Class

Inspection level

Critical Defect

AQL 0.65%

Major Defect

AQL 1.0%

Minor Defect

AQL 1.5%

Type 01 Defect
- Missing Metal
- Chip Crack '
- No Probe
- Epoxy on Die
- Mixed Device
- Wrong Bond
- Missing Bond

-

Diffusion Defect
Ink Die
Exposed Contact
Bond Short
Die Lift
Broken Wire

-

Metal Missing
Metal Adhesion
Pad Metal Discolored
Tilted Die
Die Orientation
Partial Bond

-

Oxide Defect
Probe Damage
Metal Corrosion
Incomplete Wetting
Weakened Wire

-

Adjacent Die
Passivation Glass
Die Attach Defect
Wire Loop Height
Extra Wire

-

Contamination
Ball Size
Wire Clearance
Bond Deformation

(2) Acceptance quality level for Mold/Trim gate inspection

Defect Class

Inspection Level

Kind of Delect

Critical Defect

AQL 0.15%

-

Incomplete Mold
Void, Broken Package
Misalignment

-

Deformatior)
No Plating
Broken Lead

Major Defect

AQL 0.4%

-

Ejector Pin Defect
Package Burr
Flash on Lead

-

Crack, Lead Burr
Rough Surface
Squashed Lead,

Lead Contamination
Poor Plating
Package Contamination

Bent Lead

AQL 0.65%

-

-

Minor Defect

B. In·process monitor inspection

Inspection Item

Frequency

ReJerence

• Die Shear Test
• Bond Strength Test
• Solderability Test
.' Mark Permanency Test
• Lead Integrity Test
• In·Process Monitor
Inspection for Product
• X·Ray Monitor
Inspection for Molding
• Monitor Inspection
for Production Equipment

Each Lot
Each Lot
Weekly
Weekly
Weekly
4 Times/Shift/Each Process'

MIL·STD·883C, 2019·2
MIL·STD·883C, 20114
MIL·STD·883C, 2003·3
MIL·STD·883C, 2015·4
MIL·STD·883C, 2004·4
Identify for Each -ontrol Limit

2 Times/Shift/Mold Press

Identify for Each Control Limit

2 Times/Shift/Each Unit of
Equipment

Identify for Each Control Limit

cIS

SAMSUNG

~EMICONDUCTOR

40

QUALITY and RELIABILITY
4. Outgoing quality inspection plan (LTPD)

Defect Class
Critical Defect
electrical
visual
Major

Minor

c8

Discrete

LSI

Kind of Defect

1%

2%

Open, short
Wrong configuration, no marking

Defect
electrical
visual

1.5%

3%

Items which affect reliability most strongly

Defect
electrical
visual

2%

5%

Items which minimally or do
not affect rei iabil ity at all
(cosmetic, appearance, etc.)

SAMSUNG SEMICONDUCTOR

I

41

QUALITY and RELIABILITY
Figure 10. \leneral Assembly Flow
Process· Flow

Process Step

Major Control Item

Wafer
Wafer Incoming
Inspection

Q.C. Wafer Incoming Inspection AQL 4_0%

Tape Mount
Sawing Q.C. Monitor

Q.C. Monitoring:
- Chip-out
- Crack
- Sawing-speed
- 0.1. Purity

-

Visual Inspection

100% Screen:
- FAB Defect
- EDS Test Defect
- Sawing & Scratch Defect

Q.C. Gate

1st AQL 1.0%
Reinspection AQL: 0.65%

Scratch
Sawing Discoloration
Cut Count
CO2 Bubble Purity

Lead Frame (UF)
Lead Frame Incoming

R>
~l
c8

*Q.C.UF Incoming Inspection
1. Acceptance Quality Level
- Dimension LTPD 20%, C=O
- Visual & Mechanical: LTPD 10%, C=2
- Functional Work Test: LTPD 10%, (:;=2

Die Attach (D/A)
Q.C. Monitor

*Q.C.D/A Monitor Inspection
1. Bond force
2. Frequency: 4 Times/Station/Shift
3. Sample: 24 ea Time
4. Acceptance Criteria
Defect

Acceptance

Critical

0

Reject
1

Major

1

2

Cure

SAMSUNG SEMICONDUCTOR

42

QUALITY and RELIABILITY
. Figure 10. General Assembly Flow (Continued)
Process Flow

Process Slep
Q.C. Monitor

<>

Major Conlrol Ilem

I

'Q.C. Cure Monitor Inspection
1. Control Item
- Temperature
- In/out Time
2. Frequency
- 1 Time/Shift

Au Wire
Bonding Wire
Incoming Inspection

r

'Q.C Au Wire Incoming Inspection
1. Visual Inspection: N 5, C = 0
2. Bond Pull Test Strength Test: N = 13, C = 0
3. Bondability Test
- Critical Defect: AQL 0.65%
- Major Defect: AQL 1.0%
- Minor Defect: AQL 1.5%

=

Wire Bonding (W/B)

100% Visual
Inspection

Q.C. Monitor

'Q.C. W/B Monitor Inspection
1. Frequency: 6 Times/Mach/Shift

.Q.C. Gate

1. Q.C. Acceptance Quality Level
- Critical Defect: AQL 0.65%
- Major Defect: AQL 1.0%
- Minor Defect: AQL 1.5%

Mold Compound
Incoming Inspection
Mold

'Moldability Test
- Critical Defect: AQL 0.15%
- Major Defect: AQL 1.0%
- Minor Defect: AQL 1.5%

Mold
Q.C. Monitor

c8

SAMSUNG SEMICONDUCTOR

'Q.C. Mold Monitor Inspection
1. In·Process Monitor Inspection
- Frequncy: 4 Times/Station/Shift
- Sample: 200 UnitslTime
2. Acceptance Quality Level
- Critical Defect: AQL 0.25%
- Major Defect: AQL 0.4%

43

QUALITY and RELIABILITY
Figure 10. General Assembly Flow (Continued)
Process Flow

n
6
6
}-

Process Step

Major. Control Item

Cure
a.c. Monitor

'a.c. Cure Monitor Inspection
1. Control Item
- Temperature
- In/out Time
2. Frequency
- 1 Time/shift

Deflash
a.c. Monitor

'a.c. Deflash Monitor Inspection
1. Control Item
'- Pressure
- Belt Speed
~ Visu"aliMechanical Inspection
2. Frequency: 4 Times/Mach/Shift
3. Identify each Defect Control Limit

TRIM/BEND

a.c. Monitor

'a.c. Trim/Bend Monitor Inspection
1. Visual Inspection
2. Frequency: 4 Times/Station/Shift

Solder

100% Visual Inspection

a.c. Monitor

'a.c. Solder Monitor Inspection
1. Frequency: 4 Times/Mach/Shift
2. Criteria
- Critical Defect: AaL 0.65%
- Major Defect: AaL 1.0%

a.c. Gate

'a.c. Mold Gate
- Acceptance Criteria
Critical Defect: AaL 0.15%
Major Defect: AaL 0.4%
Minor Defect: AaL 0.65%

Test

100% Electrical Test

a.c. Monitor

Correlation Sample Reading for Initial
Device Test

Mark

100% Visual Inspection

I

"91

c8 SAMS~NG

SEMICONDUCTOR

44

QUALITY and RELIABILITY

Figure 10. General Assembly Flow (Continued)
Process Flow

0
0

Process Step
PRT Monitoring
(Process Reliability
Testing)

1. PRT
- HOPL (168 HRS), PCT (48 HRS)
- Other (when applicable)
2. Acceptance Criteria: LTPD 10%

Q.C. Monitor

"Q.C. Marking Monitor Inspection
- Frequency: 4 Times/Station/Shift
- Sample: 24 UnitslTime
- Identify for Each C.L.
- Acceptance Criteria

I

I

0

I

I

Major Control Item

Defect

Acceptance

Critical

0

1

Major

1

2

Q.C. Gate

"Q.C. Final Acceptance Level
- Critical Defect: AQL 0.15%
- Major Defect: AQL 0.4%
- Minor Defect: AQL 0.65%

Q.A. Gate

"Q.C. Incoming Inspection
1. Critical Defect:
- Electrical Test: LTPD
- Visual Test:
LTPD
2. Major Defect:
- Electrical Test: LTPD
- Visual Test:
LTPD
3. Minor Defect:
- Electrical Test: LTPD
- Visual Test:
LTPD

Reject

2% (N=116; C=O)
2% (N=116, C=O)
3% (N = 116, C = 1)
3% (N=116, C=1)
5% (N=116, C=2)
5% (N=116, C=2)

Stock

"Age Control

Q.A. Gate

"Q.A. Outgoing Inspection
1. Quantity
2. Customer
3. Packing
4. Sampling Inspection (when applicable) .
- Sampling plan is same as incoming
Inspection

. Shipment

c8

SAMSUNG SEMICONDUCTOR

45

QUALITY and RELIABILITY·
SST's BEST PROGRAM
The SST Best Program has been designed to offer the customer an alternative to standard off-the-shelf plastic
encapsulated LINEAR circuits. The Best Program will significantly reduce incoming inspection requirements as
well as early device failures (infant mortalify). These results are achieved by a tightened AQL inspection plan and
a burn-in of each unit for 160 + 8, - 0 hours at 125°C or equivalent conditions established from a time/temperature
regression curve. The AQL Plan. Acceptable Quality Levels (AQL) are a measure of the ql\ality of outgoing LINEAR circuits. These
levels are established by the manufacturer to show the process percent defective being produced and to ensure
that the customer is receiving material tl:1at meets his requirements. The SST Best Program has tightened these
AQL levels to a point at which incoming inspection by the customer is no longer a necessity. Best product quality
is monitored significantly more closely than standard product; those lots which fall the AQL level are 100% reworked before resubmission to the AQL gate.
The Reliability Plan. Reliability is the statistical probability that a product will give satisfactory performance for
a specified period of time when used under specified conditions. A typical rate curve is shown below:

INFANT
MORTALITY

w

~
w

a:

::::I
...J

RANDOM FAILURES AT A
LOW CONSTANT FAILURE RATE

~
I
I

o

I
BURNINI
PERIOD I

- OPERATING L l F E - - - -

Reliability theory assumes that devices fail according to the above curve. When a group of devices is manufac·
tured a small portion of the units will be inherently weaker than the average. These weak units will probably fail
during the first few hours of operation-hence the term "infant mortali!y." If the units are burned-in however, thereby
allowing the weak units to fail, there is a much lower probability that those finally put into system use will fail.
The SST Best Row. in order to achieve an extremely high quality unit and reduce infant mortality failures the following
flow has been established:

c8

SAMSUNG SEMICONDUCTOR

46

QUALITY and RELIABILITY

Process Flow
FLOW CHART

I

I

I

I

1

. 1

I

I

I
I

§

c8

II

DESCRIPTION

I
I

WAFER FABRICATION
LINEAR PROCESS
CV PLOTS
OXIDE THICKNESS MEASUREMENTS
OPTICAL INSPECTIONS
SEM ANALYSIS
ENCAPSULATION
MOLDING COMPOUND ULTRA PURE FOR LINEAR
APPLICATIONS
POST MOLD BAKE
6 HOURS AT 175 DEG. C .
CURES PLASTIC
STRESSES ALL WIRE BONDS AND DIE
O/S FUNCTIONAL ELECTRICAL
100% TESTING
OPENS/SHORTS AND INTERMITTENTS REMOVE
HIGH TEMPERATURE BURN-IN
160 HOURS AT 125 DEG. C. OR EQUIVALENT
CONDITIONS ESTABLISHED FROM A TIME/
TEMPERATURE REGRESSION CURVE. 0.96 eV
FULL FUNCTIONAL AND PARAMETRIC
ELECTRICAL TESTING
100% ELECTRICAL TESTING AC, DC
88 DEG. C.
TIGHT AQL SAMPLING PLAN
ELECTRICAL-0.05% AQL AT 88 DEG. C.
MECHANICAL-O.o1% AQL CRITICAL & MAJOR
SHIP UNITS

SAMSUNG SEMICONDU~R

47

NOTE

LINEAR ICs

FUNCTION GUIDE

1. TELECOMMUNICATION APPLICATION
Application

Tone Ringer

Tone Ringer
with
Bridge

Type
KA241 0
KA2411

tKA2418

Package

8 DIP

8 DIP

Rectifier

KS5808

PULSE Dialer

DTMF/Pulse
Switchable
Dialer

KS5805A/B

Protect against over voltage
Low current consumption
Allow the parallel operation of 4 devices
Built-in hysteresis
External components are minimized
High output voltage
Included bridge diode

16 DIP

16 DIP

Wide operating line voltage and current range
Short start 'up time
External components are minimized
Internal protection of all inputs

18 DIP

KS5805A: Pin 2; Vref
KS5805B: Pin 2; Tone output
RC oscillator used as frequency reference
Pulse output: "0" true,
Mute output: "0" true

tKS58A/B/C/D19

22 DIP

tKS58A/B20

18 DIP

ttKS58A1B/CID21

Adjustable warbling and 2 frequency tone
External triggering or ringer disable (KA2410)
Adjustable supply initiating current (KA2411)
Built-in hysteresis

Direct telephone line operation
Standard 2 of 8 key board use
Tone output: Bipolar output
Mute output: N-CH open drain

DTMF Dialer
tKA2413

Circuit Function

22 DIP

Tone/pulse switchable dialing, touch key or slide switch
32 digit redialing & PABX auto pause time
Make/break ratio pin selectable
KS5821 (Telephone lock function)

t New Product
tt Under Development

c8

SAMSUNG SEMICONDUCTOR

51

LINEAR ICs

FUNCTION GUIDE

TELECOMMUNICATION APPLICATION
Application
DTMF/Pulse
Switchable
with 10 No.
Memory
Speech Network

Low Voltage
Speech Network
with Dialer Interface

Tone, Decoder

Type

Package

Circuit Function

18 DIP

10 No. x 18 digit memory including a redial memory
Including PABX auto pause time
10 pps/20 pps pin selectable
Make/break ratio: 40%/60%

14 Dip

Transmit/Receiver amplifier
Side tone control
On chip regulator

tKA2425A/B

18 DIP

Low Voltage Operation (1.5V)
Tx, Rx & side tone gain set by external resistors
Loop length equalization for Tx, Rx & sidetone
Provides regulated voltage for CMOS dialer
DTMF level adjustable with a singre resistor
A: Mute active low B: Mute active high

LM567C/L

8 DIP
8 SOP

Touch tone decoding
Sequential tone decoding
Commu"nication paging'
High stable center frequency
LM567L: Micropower (4mW at 5V) dissipation

16 DIP
16 SOP

Small current dissipation (Typ. 3.5mA: Vee 4.0V)
Excellent input sensitivity
Minimum number of external parts required
Used to cordless telephone parts required
Work from 1.8V to 7.0V

ttKS5823

KA2412A

"

FM IF Amplifier

(Continued)

MC3361

,

w255 companding law
wLaw Codec

Codec Filter

wLaw Combo
Codec

tKT5116J

16 DIP

tKT3040J

16 DIP

ttKT3054J

16 DIP

ttKT3064J

20 DIP

± 5V operation
Synchronous or Asynchronous'operation
On-chip sample and hold.

Exceeds' all D3/D4 and CCITT spec.
± 5V operation
Law power consumption
20dB gain adjust range
Sin X/X correction in receive filter
TTL and CMOS compatible logic
Exceeds all 03/04 and CCITT spec.
Complete CODEC and filtering system including
± 5V operation
Low power consumption
TTL and CMOS compatible logic
Receive push-pull power amp (KT3064)

t New Product
tt Under Development

c8

SAMSUNG SEMICONDUCTOR

52

LINEAR ICs

FUNCTION GUIDE

TELECOMMUNICATION APPLICATION
Application

Line Driver

Li ne Receiver

Fluorescent
Display Driver

8-Channel
Source Driver

Universial
Asynchronous
Receiver and
Transmitter (UART)

Type

MC1488

MC1489/A

(Continued)

Package

Circuit Function

14 DIP
14 SOP

Conformance EIA standard No. RS-232C & V28 (CCITI)
Quad line driver
Interface between data terminal equipment (DTE) and
data communication equipment (DCE)
Current limited output: ± 10mA typo
Power-off source impedance 300 ohms min.
Compatible with DTL and TTL, HCTLS families
Flexible operating supply range

14 DIP
14 SOP

Conformance EIA standard No. RS-232C & V-28 (CCITI)
Quad line receiver
Interface between data terminal equipment (DTE) and
data communication equipment (DCE)
Input signal range ± 30 volts
Input threshold hysteresis built in
Response control
a) Logic threshold shifting
b) Input noise filtering

18 DIP

Consisting of 8 NPN darlington output stages and
associated common-emitter input stages
Digit or segment drivers
Low input current, internal output pull-down resistors
High output breakdown voltage
Single or split supply operation

KA2580A

18 DIP

TTL, CMOS, PMOS, NMOS compatible
High output current ratings
Internal transient suppression
Efficient input/output pin structure
Low voltage LEDs and incandescent lamp

KA2588A

20 DIP

ttKA2651

ttKS5824
tKS5812

24 DIP
4n DIP

KA2588A: Separated logic and driver supply line
The data formatting and control to interface serial
asynchromous data communications between main
system and subsystems.
Low power, high speed CMOS process
Serial/parallel conversi?n of data 8 and 9 bit
transmission
Programmable control register
Optional .,. 1, .,. 16, and .,. 64 clock modes
Peripheral/modem control functions
Double buffered
Included 4 UART in one chip (KS5812)

t New Product
tt Under Development

c8

SAMSUNG SEMICONDUCTOR

53

LINEAR ICs

FUNCTION GUIDE

2. VOLTAGE REGULATOR
A. 3-Tenninal Fixed Positive Voltage Regulator
- Type

Function

High output. MC78XX
Current
series
(lo =1A)
Medium·
output
current
(/s=500mA)

MC78MXXC
AC Series

Low
Output
Current
(l o =100mA)

3A Output
Current

MC78LXXAC
series

tKA78TXX
Series

3A, 5V
Positive
Regulator

B.

3~Tenninal

Function
High output
Current
(/0=1A)

LM323

Package

Application

Features

TO-220

Maximum output current 1A
5V, 6V, 8V, 8.5V, 9V, 10V
External components are minimized
11V, 12V, 15V, 18V
Internal protection circuit fo~ output short and 24V fixed
output voltage
Positive voltage regulator
Variable application control

TO-220

5", 6V, 8V, 10V,
Maximum output current 500mA
Extemal c.omponen-ts are minimized
12V, 15V, 18V
Internal protection circuit for output short and 24V fixed
_POSitive voltage ;egulator
output voltage
Variable application circuit

TO-92

Output current in excess of 100mA
External componerit minimized
Internal protection circuit for
output short .
Positive voltage .regulator
Variable application circuit

TO-220

Maximum output. current 3A
5V, 6V, 8V, 12V
No external components required
15V, 18V, 24VInternal protection circuit for output short fixed output
Power dissipation: 25W
voltage

TO-39

Maximum output current 3A
Intemal current and thermal limiting.
Positive voltage regulator

2.6V, 5V, 6.2V;
8V, 8.2V, 9V, 12V,
15V, 18V arid 24V
fixed output
voltage

5V

Fixed Negative Voltage Regulator
Type

MC79XXC
series

Package

Application

Features

TO-220

TO:220

Oiltput't:urrent in excess of 500mA
Internal overload protection Internal short circuit current
limiting

-2V, -5V, -6V, -8V,
-10V, -12V, -15V,
-18V and 24V fixed
output voltage -

TO-92

Output current In excess of 100mA
Internal short circuit current limiting
External component minimized

-5V, -12V, -15V,
-18V and - 24V fixed
output voltage

,
Medium
Output
Current
(10 = 500mA)

MC79MXXC
Series

Low Output
ttMC79LXXAC
Current
(/0=100mA)

-2V, -5V, -6V,
-8V, -10V, -12V,
-15V, -18V, and
-24V, fixed
output voltage

Output current in excess of 1A .
Internal thermal overload protection
Internal short circuit current
limiting

- t New Product

. tt Under Development

c8

SAMSUNG SEMICONDUCTOR:

~4

LINEAR ICs

FUNCTION GUIDE

C. Precision Voltage Regulator
Function

Type

Package

Application

Features

Precision
Regulator

LM723

14 DIP

Positive or negative supply operation
Output voltage
Series, shunt, switching or floating
adiustable
operation
from 2 to 37V
0.01 % line and load regulation
Output current to 150mA without external
pass transistor

33V
Regulator

KA33V

ITO-92

Low temperature coefficient
Low dymic resistance

Electronic tuning
system

Output current in excess of 1.5A
Output adjustable from 1.2V to 37V
Internal short circuit current limiting

Floating operation for
high voltage operation
Eliminates stocking
many fixed voltage

ttLM317

Adjustable
Regulator

ttKA337

ttKA350

TO-220

TO-220

TO-3P

,

Adjustable 3-terminal negative
vqltage regulator
Line regulation typically 0.01 %/V
Load regulation typically 0.3%
Internal thermal overload protection
1.5A output current

Output voltage
adjustable from
-1.2V to -37V

Adjustable 3-terminal positive
voltage regulator
3A output current
Guaranteed, thermal regulation

Output voltage
adjustable from
1.2V to 25V

I

D. Switching Voltage Regulator
Function

Type

Package

Adjustable
1.25V'to
40V

KA78S40

16 DIP
tt16 SOP

PWM
100KHz

tKA3524

16 DIP

Features
Peak output current of 1.5A
without ex~ernal transistor
BOdB line and load regulation
, Operation from 2.5V to 40V
PWM power control circuitry
Frequency adjustable to greater than
100KHz
Total supply current is less than 10mA
Single ended or push·pull output

Application
Step-down converter
Step-up converter
Inverter
Switching regulator
Trans DC-DC converter
Inverting v~ltage
regulator

.

3 PRECISION VOLTAGE REFERENCE
Function

Type

Package

' Features
Programmable output voltage from
Vref to 36V
Voltage reference tolerance: ± 1.0%
Low output noise voltage

Switching regulator
Constant current
source
Constant current sink

Application'

Adjustable
Reference

KA431

TO-92
t8 DIP
t8 SOP,

5V
Reference

tKA336

TO-92

Adjustable 4V to 6V
Low temperature coefficient
0.60 dynamic impedance
Fast Turn-on

Adjustable shunt
regulator
Precision power
regulator

1.235V
Reference

KA385

TO·92

Low temperature coefficient
operating current of 10ILA to 20mA
10 dynamic impedance

Micropower
reference

c8

SAMSUNG SEMICONDUCTOR

5,5

LINEAR ICs

FUNCTION GUIDE

4. OPERATIONAL AMPLIFIER
Function

Type

•

Comparator, DC amp,
Multivibrator, 'Summing
amp, Integrator or differentiator Narrow band or BPF

8 DIP
8 SOP

Slew·rate of 10V/p,s as a summing
amplifier
External frequency compensation

Variable capacitance
Multiplier
Sine wave oscillator

ttKF351

8 DIP
8 SOP

JFET input
Low input bias current
High slew rate 13V/p,s
Wide gain bandwidth

High speed intergrators
Fast D/A converters
Sample arid hold c1rcuits

KA733

14 DIP
14 SOP

120MHz band width
Selectable gains of 10, 100, 400
No frequency compansation

Disk file memories
Magnetic tape systems
Wide band video amplifiers

MC4558
MC1458

8 DIP
8 SOP

Internal frequency compensation
Low noise operation

Phone pre-amplifier
Tape playback amplifier
Schmitt trigger,

OPAMP

LM358/A
LM258/A
LM2904

tKA9256

Quad
OPAMP

t
tt

Application

Internal frequency compensation
Short circuit protection

KA301A

Dual
OPAMP

Features

8 DIP
8 SOP

LM741

r·

Package

8 DIP
t8 SOP

Internal frequency compensation
for unit gain
Large DC voltage gain
Wide power supply range

Internal current limiting: Isc = 350mA
. 10 SIP HIS Internal frequency compensation
Minimal cross over distortion'

DC summing amplifier
Power amplification
RC active bandpass filter
Compatible with all forms
of logic
High power amplifier
CD driver

LM324/A
LM224/A
LM2902

14 DIP.
14 SOP

Internal frequency compensation
Wide supply voltage range
Single supply: DC 3V - 30V
Dual .supply: DC ± 1.5V - ± 15V

Audio power booster
DC amp, Multivibrator
Switch, Comparator
Schmitt trigger

LM348
LM248

14 DIP
14 SOP

Each amplifier is functionally
equivalent to the LM741
Pin compatible with LM324
Short circuit protection

Comparator with
hysteresis
Voltage reference

MC3403
tMC3303

14 DIP
14 SOP

Class AB output stage for minimal
crossover distortion
Single or split supply operation
Internal frequency compensation

Comparator with
hysteresis
Bi-Quad filter

New Product
Under Development

c8

SAMSUNG SEMICONDUCTOR

56

FUNCTION GUIDE

LINEAR ICs

5. VOLTAGE COMPARATOR
Function

Type

ILM311
tLM211

Single
Comparator

ttKA361
ttKA261

KA710C

Dual
Comparato"r

LM393/A
LM2903
LM293

KA319
KA219

Quad
Comparator

LM339/A
LM2901
LM239
LM3302

Package

Features

Application

8 DIP
t8 SOP

Operates from single 5V supply
Maximum input current: 250nA
Maximum offset current: 50nA
Differential input voltage range: ± 30V
Power consumption: 135mW at + 15V

Multivibrator output is
compatible with DTL and
as well as MOS circuits
voltage controlled
oscillator

14 DIP

independent strobes
Guaranteed high speed: 20nS max.
Complementary TTL outputs

High speed analog
to digital converter
Zero-crossi ng detectors

Low offset and thermal drift
Compatible with practically
all types of integrated logic

Interface between
logic types
Level detector
with lamp

14 DIP
t14 SOP

8 DIP
8 SOP

14 DIP
t14 SOP

14 DIP
14 SOP

High precision comparators
Reduced Vos drift over temperature
Eliminates need for dual supply
Allows sensing near ground
Compatible with all forms of logic
Power drain suitable for battery
operation
Low input biasing current: 25nA
Low output saturation voltage 250mV
at 4mA

Output voltage compatible
with TTL, DTL, ECL and
CMOS logic system
Basic comparator
Pulse generator
MOS clock driver

Two indepentent comparators
Operates from a single 5V
High common mode slew rate

Relay driver
Window detector

Wide single supply voltage
range or dual supplies
Very low supply current drain
(0.8mA)-independent of supply
voltage (2mW/Comparator at + 5V DC)
Low input biasing current: 25nA
Input common-mode voltage range
includes GND
Low output saturation volti!lge 250mV
at 4mA

Compatible with all forms
of logic
Bi-stable multivibrator
One-shot multivibrator
Time deiilY generator
Square wave oscillator
Pulse generator
Limit comparator
Crystal controlled
oscillatgor

t New Product
tt Under Development

c8

SAMSUNG SEMICONDUCTOR

57

II

LINEAR ICs

FUNCTION GUIDE

6. TIMER
Func;tlon

Single
Timer

Dual
Timer

Quad
Timer

Type

Package

NE555

8 DIP
t8 SOP

Maximum operating
frequency: 500KHz
Adjustable ~uty cycle

KS555
tKS555H

8 DIP
t8S0P

Low power consumption by using
CMOS process
High speed operation
Wide operation supply voltage:
2 to 18 volts
Pin compatible. with NE555

NE556

14 DIP
t14 SOP

TTL Compatible
Dual NE555

Time delay generation

14 DIP
t14 SOP

Low· power consumption
by using C-MOS process
Pin compatible with NE556

Time delay' generation

tKS556

tNE558

16 DIP

Wide supply voltage range:
4.5 to·.16V
100mA output current per section
Time period equal RC

Quad monostable
Sequential timing
Precision timing

Features

Application
PreCision timing
Pulse generator

Precision timing
Pulse generator

7. DATA CONVERTER les
Functions
A/D,D/A
Converter

Type

Package

tKSV3100A

40 DIP

High speed 8-bit AID and 10-bit D/A
Image processing
converter on the single chip construction Video/Graphics

ttKSV311Q

40 DIP

Enhanced version of KSV3100A

ttKSV3208

28. DIP

High speed 8,bit AID converter

28 DIP

8-bit I'P-compatible AID converter with
8-channel multiplexer linearity error
KAD0808: ± 1/2 LSB
KAD0809: ± 1 LSB

tKAD0808/9

AID
Converter

ttKAD0820AiB

DMM A/D

tKS7126

S.A.A.

c8

Image processing
Video/G raphics

General purpose and
I'P-interface system

8 bit I'P-conipatible AID converter with
Track/Hold function linearity
KAD0820A: ± 1/2 LSB
KAD0820B: ± 1 LSB

40 DIP

3-1/2 digit LCD driver AID converter

Digital multi-meter

High speed quad 4-bit DIA converter

Video/Graphics
General purpose and
I'P-interface system

ttKDAOadO

16 DIP

8-bit D/A converter

ttKDA0808

16 DIP

8-bit D/A converter

ttKS25C02
ttKS25C03

16 DIP

8-bit CMOS successilie
registers

ttKS25C04

24 SDIP

12-bit CMOS successive approximation
registers

t New Product

Applications

20 DIP

ttKSV3404

D/A
Converter

Features

app~oximation

SAR of AID converter

tt Under Development

SAMSUNG SEMICONDUcroR

58

FUNCTION GUIDE.

LINEAR ICs
8. MISCELLANEOUS ICs
Function

Toy Radio
Control
Actuator

DC Motor
Speed
Controller

Earth
Leakage
Detector

Zero
Voltage
Switch

Type

Package

KA2303

9SIP

tKA2304

9SIP

Features

Application

High gain amplifier, Peak detector, 3 Function
T flip-flop, comparator with
hysteresis, regulator, motor driver 2 Function

ttKA2307

16 DIP

Receiver

5 Function

ttKA2308

14 DIP

Transmitter

5 Function

KA2401

8 DIP

KA2404

TO-92L

Stable voltage reference
VreI = 1.27V (Typ.)

Vcc =4-12V

KA2402

8 DIP

Stable current source

Vcc =1.8-8V

Stable voltage reference
VreI = 1.0V (Typ.)

Vee = 3.5-14.4V

I

tKA2407

TO-126

KA2803

8 DIP

Low power consumption
High noise immunity
Few external components

Earth leakage detector

8 DIP

Easy operation either through
the AC line or a DC supply
Supply. voltage control
External component are
minimized
Negative output current pulse up
to 250mA (short circuit protection)

ON, OFF temperature control
Time proportional
temperature control

KA2804

t New Product
tt Under Development

c8

SAMSUNG SEMICONDUCTOR

59

CROSS REFERENCE GUIDE

LINEAR ICs
1; TELECOMMUNICATION ICs
A. Dialer
Application
Pulse Dialer

DTMF Dialer

UMC

SHARP

SAMSUNG

MOSTEK

KS5805A
KS5805B

*MK50992
*MK50993

·S2560A/B

*T40992
*T40993

*LR40992
*LA40993

KS5808
KA2413

'MK5089
*PBD3535
(RIFA)

'S25089

'UM95089
UM95087

'LA4089
LA4087

AMI

Othel'$

'SBA5089
SBA5091
SBA5099

MK5370

*UM91230
'UM91210

LR48081
LR48082

*S7230A/B
• LC7360

ttKS5823

. MK5380
MK5375/6

UM91250
UM91260

LR4803

PCD3315

SAMSUNG

MOTOROLA

MITEL

CHERRY

Tone/Pulse
Switchable with
Redial Memory

tKS5819
tKS5820
ttKS5821

Tone/Pulse
Switch able with
10 No. Memory

B. Tone Ringer
Application
Tone Ringer
1 Chip Tone Ringer

C.~peech

SGS

Others

KA241 0

*ML8204

'CS8204

*TA31001

KA2411

'ML8205

*CS8205

*TA31002

Others

tKA2418

MC34012/7

• LS1240

Network

Application

SAMSUNG

SGS

RIFA

ITT

ERSO

Subset Amplifier

KA2412A

Speech Network
with Dialer
Interface

tKA2425A
tKA2425B

• LS285/A

PBL3726

TEA1045

*CIC9185

LS356

PBL3781

*MC34014
(MOTOROLA)

D. Tone Decoder
Application
Tone Decoder

SAMSUNG

NATIONAL

SHARP

SIGNETICS

Others

LM567

*LM567

*IR3N05

'NE567

*XR567 (EXAR)

LM567L

*XAL567 (EXAR)

t New Product
tt Under Development

c8

SAMSUNG SEMICONDUCTOR

60

LINEAR ICs

CROSS REFERENCE GUIDE

E. FM IF Amplifier
Application

SAMSUNG

MOTOROLA

SHARP

SPRAGUE

Others

FM IF Amplifier

MC3361

" MC3361

IR3N06

ULN3859

"LM3361

I

F. Codec, Codec Filter, Combo Codec
Application

SAMSUNG

. wLaw Codec

tKT5116J

Codec Filter

N/S

FAIRCHILD

SGS

*TP5116

*/LA5116

*M5116

2910

*/LA5912

*M5912

*2912

Others

tKT3040J

*TP3040

wLaw Combo Codec

ttKT3064J

*TP3064

2913

wLaw Combo Codec

ttKT3054J

" TP3054

*2916

*MK5116
*ETC5040
MC14400·5

*ETC5064

EXAR

SIGNETICS

G. Interfaces
Application
Line Driver
Line Receiver

SAMSUNG

MOTOROLA

FAIRCHILD

TI

N/S

MC1488

*MC1488

*/LA1488

"SN75188

*DS1488

*XR1488

*MC1488

MC1489

*MC1489

*/LA1489

*SN75189

*DS1489

XR1489

*MC1489

MC1489A

* MC1489A

*/LA1489A

* DS1489A

*XR1489A

*SN75189A

* MC1489A

H. Driver
. Application
Fluorescent Display Driver
8CH Source Driver

SAMSUNG
ttKA2651

Others

SPRAGUE
*UCN5815A

KA2580A

*UDN2580A

KA2588A

*UDN2588A

I. UART
Application
_ Single UART
Quad UART

SAMSUNG
ttKS5824

HITACHI
. *HD6350

MOTOROLA

Others

* MC6850

tKS5812

t New Product
tt Under Development
* Direct Replacement

c8

SAMSUNG SEMICONDUCTOR

61

CROSS REFERENCE GUIDE

LINEAR ICs
2. VOLTAGE REGULATOR
A. 3-Terminal Fixed Positive Voltage Regulator
Description

MC78XXAC/C
Series
(lo=1A)

MC78MXXC
Series
(lo=0.5A)

MC78LXXAC
(lo=0.1A)

SAMSUNG

FAIRCHILD

MC7805AC/C
MC7806AC/C
MC7808AC/C
MC7885AC/C
MC7809AC/C
MC7810AC/C
MC7Q11AC/C
MC7812AC/C
MC7815AC/C
MC7818AC/C
MC7824AC/C .

MC7805AC/C
MC7806AC/C
MC7808AC/C

I'A7805
I'A7806
I'A7808
I'A7885

MC7812AC/C
MC7815AC/C
MC7818AC/C
MC7824AC/C

,.A7812
I'A7815
I'A7818
I'A7824

I'PC7812
I'PC7815
I'PC7818
I'PC7824

MC78M05C
MC78M06C
MC78M08C
MC78M10C
MC78M12C
MC78M15C
MC78M18C
MC78M24C

MC78M05C
MC78M06C
MC78M08C

,.A78M05C
I'A78M06C
I'A78M08C

I'PC78M05

MC78M12C
MC78M15C
MC78M18C
MC78M24C

,.A78M12C
,.A78M15C

MC78L05AC

I'A78L05AC
I'A78L62AC

MC78L26AC
MC78L05AC
MC78L62AC
MC78L08AC
MC78L82AC
MC78L09AC
MC78L12AC
MC78L15AC
MC78L18AC

I'PC7808

Package

AN7805
AN7806
AN7808

I'A78M24

I'PC78M08
I'PC78M10
I'PC78M12
I'PC78M15
I'PC78M18
I'PC78M24

AN7812
. AN7815
AN7818
AN 7824
AN 78M05
AN78M06
AN78M08
AN78M10
AN78M12
AN38M15
AN78M18
AN78M24

TO-22O

MC78L05AC

~C78L24AC'

KA78TXXAC/C
Series
(10 = 3A)

KA78T05AC/C
KA78T06C
.KA78TOBC
KA78T12AC/C
KA78T15AClC
KA78T18C
KA78T24C

MC78T05AClC
MC78T06C
MC78T08C
MC78T12AC/C
MC78T15AC/C
MC78T18C
MC78T24C

LM323
(10 3A)

LM323
(TO-3P)

LM323
(T0-3/T0-220)

c8

I'PC7805

MATSUSHITA

T0-22O

MC78L12AC
MC78L15AC
MC78L18AC
MC7.8L24AC

=

NEC

MOTOROLA

SAMSUNG SEMICONDUCTOR

I'A78L82AC
I'A78L09AC
,.A78L12AC
I'A78L15AC

TO-92

TO-220

SH323
(TO-3)

62

LINEAR ICs

CROSS REFERENCE GUIDE

B. 3·Terminal Fixed Negative Voltage Regulator
Description

SAMSUNG

MC79XXC
Series
(10= 1A)

MC7902C
MC7905C
MC7906C
MC7908C
MC7910C
MC7912C
MC7915C
MC7918C
MC7924C

MC79MXXC
(l o =0.5A)

MC79M02C
MC79M05C
MC79M06C
MC79M08C
MC79M10C
MC79M12C
MC79M15L
MC79M18C
MC79M24C

ttMC79LXXAC
(l o =0.1A)

MC79L05AC
MC79L12AC
MC79L15AC
MC79L18AC
MC79L24AC

MOTOROLA

FAIRCHILD

MC7905C
MC7906C
MC7908C

,.A7905·

,.PC7905

,.A7908

,.PC7908

AN7905
AN7906
AN7908

MC7912C
MC7915C
MC7918C
MC7924C

,.A7912
,.A7915

,.PC79t2
,.PC7915
,.PC7918
,.PC7924

AN7912
AN7915
AN7918
AN 7924

MC79M05C

,.A79M05

NEC

MATSUSHITA

Package

·TO-220.

,.A79M08
TO-22O
MC79M12
MC79M15

,.A79M12
,.A79M15

MC79L05AC
MC79L12AC
MC79L15AC
MC79L18AC
MC79L24AC

TO-92

c. Precision Voltage Regulator
Description
Adjustable
Voltage
Adjustable
Voltage

SAMSUNG

MOTOROLA

FAIRCHILD

N/S

NEC

Package

MC1723

p.A723

LM723

14 DIP

ttLM317

LM317

,.A317

LM317

TO-220

ttKA337

LM337

LM337

LM337

TO-220

ttKA350

LM350

LM350

LM350

TO-220

,.PC574

TO-92

LM723

33V Regulator

KA33V

D•.Switching Voltage Regulator
Qescription
Adjustable
1.25V to 40V
(fo = 100KHz)
PWM 100KHz

SAMSUNG

,.A78S40

MOTOROLA

FAIRCHILD

,.A78S40

,.A78S40

tKA3524

N/S

TI

Package

16 DIP
LM3524

SG3524

16 DIP.

t New Product
tt Under Development

c8

SAMSUNG SEMICONDUCTOR

63

II

CROSS REFERENCE GUIDE

LINEAR ICs
3~_

PRECISION VOLTAGE REFERENCE
Description

Adjustable
Reference
(2.5V-36V)
5V Reference-· 1.235V
Reference

SAM$UNG
KA431

MOTOROLA

FAIRCHILD

TL431

",A431

tKA336
ttKA385

LM385

TI

N/S
TL431

Package
TO-92
t8 DIP
t8 SOP

LM336

TO-92

LM385

TO-92

4. OPERATIONAL AMPLIFIER
Description

SAMSUNG

MOTOROLA

NATIONAL

Single OP Amp

LM741
KA301/A
KA733C
ttKF351

MC1741
LM301/A
MC1733C
LF351

LM741 LM301/A
LM733C
LF351

LM358/A
LM258JA
LM2904
MC1458
MC4558
tKA9256

LM358JA
L.M258
LM2904
MC1458
MC4558

LM358JA
LM258JA
LM2904
LM1458

lM324JA
lM224JA
LM2902
lM348
LM248
MC3403
ttMC3303

LM324JA
LM224
lM2902
lM348
LM248
MC3403
MC3303

lM324JA
lM224JA
lM2902
LM348
lM248

Dual OP Amp

Quad OP Amp

FAIRCHILD

MATSUSHITA

",A741
",A301/A
-",A733C

,..A1458
",A4558
,..A324
",A224
",A2902
,..A348
,..A248
,..A3403
,..A3303

Others

",PC301C

AN6562

TA75358

AN4558

NJM4558
"TA7256

AN6564

TA75324

NJM3403A

5. VOLTAGE COMPARATOR
Description

SAMSUNG

MOTOROLA

NATIONAL

FAIRCHILD

LM311
LM211

lM311
LM211
lM361
LM261
LM710

LM311

LM311
LM211

Single Comparator

lM311
LM211
tKA361
ttKA261
tKA7.10C

,..A710C

JZA710C

Dual Comparator

LM393JA
LM2903
lM293
KA319
ttKA219

LM393JA
LM2903
lM293

LM393JA
LM2903
LM293
LM319
LM219

LM339JA
LM2901
lM239
LM3302

lM339JA
LM2901
LM239

Quad Comparator-

c8

SAMSUNG SEMICONDUCTOR

LM339JA
LM2901
LM239
LM3302

,..A339
",A2901
",A239
,..A3302

TI

Others
LM311

lM393JA
lM2903
LM293
LM319
LM219

TA75393
AN6914

LM339
LM2901
LM239
LM3302

TA75339
AN6912

NJM319

64

CROSS REFERENCE GUIDE

LINEAR ICs
6. TIMER
Description

SAMSUNG
NE555
tKS555H
KS555

Single Timer

Dual Timer

NE556
tKS556

Quad Timer

tNE558

TI

MOTOROLA

NATIONAL

SIGNETICS

MC1455

LM555

NE555

NE555
TLC555

LM556

NE556

NE556
TLC556

Others
TA75555
ICM7555
ICM7556

I

NE558

7. DATA CONVERTER ICs
Application

SAMSUNG

NATIONAL

TI

INTERSIL

ITT
UVC31 00
UVC3100

tKSV3100A

A/D·D/A Converter

KSV3100A
up·date version

ttKSV3110
High-Speed 8·Bit AID
8·Bit AID Converter

ttKSV3208
tKAD0808l9 A DC0808/9
ttKAD0820

ADC0808J9
ADC82A

ADC0820

TSC7126
ICL7126

KS7126

3·1/2 DMM AID
4·Bit Triple
D/A Converter

Others

ttKSV3404

8·Blt D/A Converter

SAR.

ttKDA0800

DAC0800

ttKDA0808

DAC0808

ttKS25C02

OM 2502

ttKS2503

DM2503

ttKS2504

DM2004

DAC82
DAC08
MC1408

AD1408

8. MISCELLANEOUS ICs
Application

SAMSUNG

Toy Radio
Control Actuator

SEGNETICS NATIONAL MITSUBISHI

NEC

KA2303

3 Function

tKA2304

2 Function
5 Function .(RX)

ttKA2307

5 Function (TX)

ttKA2308
KA2401
DC Motor Speed
Controller

AN6612

KA2404

AN6610

ttKA2407

*AN6651

KA2803

Zero Voltage SW

KA2804

c8

",PC1470H

tKA2402

Earth Leakage
Detector"

t New Product

Others

tt Under Development

LM1851

*LA5521D
",PC147QH

·M54123

A7390
*",PC1701C

* Direct Replacement

SAMSUNG SEMICONDUCTOR

65

LINEAR ICs

3100A

KSV

ORDERING INFORMATION

C

N

A+

T
~

BURN-IN (OPTIONAL)
(SEE BURN-IN PR~GRAM) .
PACKAGE TVP,E

L-----------------TEMPERATURERANGE

'---------------------------DEVICE NUMBER AND SUFFI~ (OPTIONAL)
A: IMPROVED VERSION
'------------------------------------ DEVICE FAMILY

TEMPERATURE RANGE
BLANK

SEE INDIVJDUAL S'PEC

PACKAGE TYPE
CODE

C

COMMERCIAL 0 - + 70°C

D

I

INDUSTRIAL - 25 - + 85°C
-40-+!WC

N

M

MILITARY -55 -+125°C

J
S

0
E
B
P

INTEGRATED CIRCUIT
KA

LINEAR IC

KS

CMOS IC

KT

TELECOM IC

LM

NATIONAL

MC

MOTOROLA

NE

S[GNETICS

KSV

A/D-DIA CONVERTER

KAD

AID CONVERTER

KDA

D/A CONVERTER

c8

SAMSUNG. SEMICONDUCTO~

W
U
L
PL
M
H
Z
V
A
T
X
G

PKG.TYPE
SOIC
CERAMIC DIP
PLASTIC DIP (300/600 mil)
SIP
FOP
SD (400 mil)
SSD (Skinny Shrink DIP)
(400 mil. Small Pitch)
SHD (Shrink DIP)
(300 mil. Small Pitch)
ZIP
PGA
LCC
PLCC
TO-3
TO-3P
TO-92
TO-92L
TO-126
TO-220
TO-247
BARE CHIP

66

,/

"~t,:;,?'hl~rP\i~~0~ :~,"/;; ,
ft

PRODUCT INDEX

(Continued)

3. Telecommunication Application
Device
KA2410
KA2411
. KA2412A
KA2413
KA2418
KA2419
KA2425A1B
KS5805A1B
KS5808
KS5812
KS5819
KS5820
KS5821
KS5824
KT3040J
KT3054J
KT3064J
KT5116J
LM587C
LM587L
MC1488
MC1489/A
MC3361
KA2580A
KA2588A
KA2651

Function
Tone Ringer
Tone Ringer
Telephone Speech ·Circuits
Dual Tone Multi Freque~cy Generator
Tone Ringer with Bridge Diode
Tone Ringer with Bridge Diode
Telephone Speech Network with Dialer Interface
Telephone Pulse Dialer with Redial
Dual Tone Multi Frequency Dialer
Quad Universial Asychronous Receiver and Transmitter
Tone/Pulse Dialer with Redial
Tone/Pulse Dialer with Redial
Tone/Pulse Dialer with Redial
Universial Asychronous Receiver and Transmitter
PCM Monolithic Filter
COMBO CODEC
COMBO CODEC
,...Law Companding CQDEC
Tone Decoder
Micropower Tone Decoder
Quad Line Driver
Quad Line Receiver
. Low Power Narrow Band FM IF
8-Channel Source Drivers
8-Channel Source Drivers
Fluorescent Display Drivers

Package
8 DIP
8 DIP
14 DIP
16 DIP
8 DIP
8 DIP
18 DIp·
18 DIP
16 DIP
40 DIP
22 DIP/SDIP
18 DIP
22 DIP/SDIP .
24 DIP
16 CERDIP
16 CERDIP
20 CERDIP
16 CERDIP
8 DIP/8 SOP
8 DIP/8 SOP
14 DIP/14 SOP
14 DIP/14 SOP
16 DIP/16 SOP
18 DIP
20 DIP
18 DIP

Page
69
69
75

83
108
108
112
130
146
152
162
172
162
. 180
191

200
214
226
239
247
257

264
270
599
599

604

LINEAR INTEGRATED CIRCUIT

KA24101KA2411
TONE RINGER

The KA2410iKA2411 is a bipolar integrated circuit designed for telephone
bell replacement.

8 DIP

.FUNCTIONS
• Two oscillators
• Output amplifier
• Power supply control circuit

FEATURES
•
•
•
•
•
•

Designed for telephone bell replacement
Low current drain.
Small size 'MINI DIP' package.
Adjustable 2-frequency tone.
Adjustable _rbling rate. •
Built-In hysteresis prevents false triggering and rotary dial
'CHIRPS'
Extension tone ringer modules
Alarms or other alerting devices.
External triggering or ringer disable (KA2410).
Adjustable for reduced supply initiation current (KA2411)

•
•
•
•

APPLICATION CIRCUIT 1·(KA2410)
o--t bC:T'1."".,.,..---,
.

O.9~F

100K-200K ohm

C.

22,.FI35V

R2
165K±1%
C2
o.47pF±5%

Note: 1. Output amplifier
2. High frequency oscillator.
3. Low frequency oscillator
4. Hysteresis regulator
Fig. 1

c8

SAMSUNG SEMICONDUCTOR

69

LINEAR INTEGRATED CIRCUIT

KA2410/KA2411
ABSOLUTE MAXIMUM RATINGS (Ta
Characteristic
Supply Voltage
Power Dissipation
Operating Temperature
Storage Temperature

=25°C)

Symbol'

Value

Unit
V

30
400
-45 to 65
-65to 150

Vee
Po
Top'
TS!lI

rrm
°C
DC·

=

ELECTRICAL CHARACTERISTICS (Ta 25°C)
(All voltage referenced to GND unless otherwise specified)
Characteristic

Symbol

Test Condition

Min

Typ

Max

Unit

29.0

V

Operating Supply Voltage

Vee

Initiation Supply Voltage l

VSI

See Fig. 2

17

19

21

V

Initiation Supply Current l

lSI

KA2411-6.8K-Pin 2 to GND

1.4

2.5

4.2

mA

Sustaining Voltage2

Vsus

See Fig. 2

9.7

11.0

12.0

V

Sustaining Current2

Isus

No Load Vee=Vsus, See Fig. 2

0.7

1.4

2.5

mA

Trigger Voltage3

VTA

KA2410 Only Vee =15V

9.0

Trigger Current3

ITA

KA24100nly

Disable Voltage'

VDlS

KA24100nly

Disable Current'

lOIs

KA24100nly

-40

-50

Output Voltage High

VOH

Vee=21V, la=-15mA
Pin 6=6V, Pin 7=GND

17.0

19.0

Output Voltage LOw

VOl

Vee=21V,la=15mA
Pin 6=GND, p'in 7=6V

liN (Pin 3)
liN (Pin 7)
High Frequency 1
High Frequency 2
Low Frequency

fHl
fH2
fL

10.5

12.0

V

20.0

10005

pA

0.5

V

pA
21.0

V

1.6

V

Pin 3=6V, Pin 4=GND
Pin 7=6V, Pin 6=GND

-

-

500

-

500

nA
nA

R3=191K,C3=68oopF
R3=191K,C3=6800pF
R2 =165K, C2 =0.47"F

461
.576
9.0

512
640
10

563
704
11.0

Hz
Hz
Hz

• NOTE (see electrical characteristics sheet)
1. Initiation supply voltage (Vs~~ is the supply voltage required to start the tone ringer oscillating.
2. Sustaining voltage (Vsus) is the supply voltage required to maintain oscillation.
3. VTA and irA are the conditidhs applied to trigger in to start oscillation for Vsus ~Vee ~VSI
4. VOIS and lOIS are the conditions applied to trigger in to inhibit oscillation for VSI~Vee
5. Trigger current must be limited to this value externally.

c8

SAMSUNG SEMICONDUCTOR

10

LINEAR INTEGRATED CIRCUIT

KA2410/KA2411

CIRCUIT CURRENT-5UPPLY VOLTAGE (No Load)

4.0

3.5

~3.0
B

12.5

.iI

;t2.o

V

S
.II ,.5

i-'"

~

II

,.0
0.5

10

14

18

Vee (V), Supply

22

26

30

34

"""ge

Fig. 2

APPLICATION NOTE
The application circuit illustrates the use of the KA2410/KA2411 devices in typical telephone or extension tone ringer
application.
The AC ringer signal voltage appears across the TIP and RING inputs of the circuit and is attenuated by capacitor C, and
resistor R,.
C, also provides isolation from DC voltages (48V) on the exchange line.
After full wave rectification by the bridge diode, the waveform is filtered by capacitor C4 to provide a DC supply for the tone
ringer Chip.
As this voltage exceeds the initiation voltage (Vsl),osciliation starts.
With the components shown, the output frequency chops between 512 (f~,) and 640Hz·(fh2) at a 10Hz (fl ) rate.
The loudspeaker load is coupled through a 13000 to 80 transformer.
The output coupling capacitor Cs is required with transformer coupled loads.
When driving a piezo-ceramic transducer type load, the coupling C 5 and transformer (13000: 80) are not required.
However, a current limiting resistor is required.
The low frequency oscillator oscillates at a rate (fl ) controlled by an external resistor (R2) and capacitor (C2).
The frequency can be determined using the relation fl =111.289 R2 • C2. The high frequency oscillates at a fH" fH2 controlled
by an external resistor (R3) and capacitor (C3). The frequency can be determined using the relation fHI=111.504 R3. C 3.
fH2=1/1.203 R3 , C 3 •
.
Pin 2 of the KA2411 allows connection of an ex~ernal resistor RSl , which is used to program the slope of the supply current vs supply voltage characteristics (see Fig 4); and hence the supply current up to the initiation voltage (Vsi). This initiation voltage remains constant independent of Rsl .
The supply current drawn prior to triggering varies inversely with RSl.· decreasing for increasing value of resistance. Thus,
increasing the value of RSl• will decrease the amount of AC ringing current required to trigger the device. As such, longer
sucribser loopS are possible since less voltage is dropped per unit length of loop wire due to the lower current level. RSl
can also be used to compensated for smaller AC coupling capacitors (Cs on Fig 3) (higher impedance) to the line which can
be used to alter the ringer equivalence number of a tone ringer circuit.
The graph in Fig. 4 illustrates the variation of supply current with supply voltage ofthe KA2411. Three curves are drawn to
show the variation of i~itiation current with Rsl . Curve B (RSl =6.81<) shows the I-V characteristic for the KA2411 tone ringer.
Curve A is a plot with RSl <6.8KO and shows an increase in the current drawn up to the initiation voltage Vsi. The W charac,
teristic after initiation remains unchanged. Curve C iIIurates the effect of increasing RSL above 6.8K Initiation current decreases
but again current after triggering is unchanged.

c8

SAMSUNG SEMICONDUCTOR

71

LINEAR INTEGRATED CIRCUIT

KA2410/KA2411
APPLICAnQN CIRCUIT 2 (KA2411)

8 I------U-_.__----.
101(0

VOL

...---+---+------0----1

2

KA2411

2'JV

Ro--+----'
RSL

c.

Fig. 3

LINEAR INTEGRATED CIRCUIT
KA2411 Supply Current (No Load) Vs. Supply Voltage

1-1-

--

----

,

--

,-

-

75

as

.. A)R".SKO

I
I

2.5

8) R,.-&

1.1;

o.s

iKcr.-1/

C)R... 'Sko

~

~
i41i~

)

•

:

,

I ~,

,
,

•

;"'1-

610141822263034
Supply

_go (V)

Fig. 4,

,c8

Sj'MSUNG SEMICONDUCTOR

,72

LINEAR INTEGRATED CIRCUIT

KA2410/KA2411
EQUIVALENT CIRCUIT
(Pin 2 Input)

INHIBITING OSCILLATION
+Vcc

KA2410

Pin 2

R

O >Zt.); the main part is sent to the line Via R6.
The imPedance At. is defined as.fu
1..3

V

(R6+Ze)II(R5+Zt.)
(~
R= ~+(R6+ZB)II(R5+Zt.) R6+Zt

To reduce the receiving input Signal,

also, In order to reduce power loss in R5 & Ze and to transfer the maximum power to the line via R6.
R5+ZB> >R6+ZL
R6+ZM=ZL

c8

SAMSUNG SEMICONDUCTOR

81

LINEAR INTEGRATED CIRCUIT

KA2412A

Then the line impedance ZL grows lrom SOO ohm up to 900 ohm when the line length Increases. '
The voltage driven to the line is
ZL
x'"
V L - RS+Zu +4 _IT
In order to maximize sending Gain
ZL»RS
Therefore, in the case 01 the KA2412 test circuit:
RS= 75, ZM =S.8K111, ZL =SOO

·VL ..

4
Z xZuh=28S.82h
Zu+R8+ L

• In receiving mode:
'
,
The J!C signal coming from the line is sensed across the secon 600mV and < 3.0 VOlt).

9

,DP*

Depressed Pushbutton (Output) - Normally low: A Logic "1" indicates one and only one,
button of the DTMF keypad is depressed.

10

m*

Tone output (Input)
disabled.

1.1

MS*

' Mute/Single tone (Output) - A Logic "1" indicates a'row and/or column tone is being
generated. A Logic "0" indicates tone generator is disabled.

12

A+*

MPU Power Supply (input) - Enables pullups 'on the microprocessor section outputs,
Additionally, this voltage will power the entire circuit (except tone Ringer) in the absence of
voltage at V--,

13

110*

Input/Output - Serial Input or Output data (determined by DO input) to or from the
microprocessor for storing or retrieving telephone numbers. Guaranteed to be a Logic "1"
on powerup if 00= Logic "0".

14

00*

Data Direction (Input) - Determines direction of data flow through 110 pin. As a Logic "1",
I/O is an input to the DTMF generator. As a Logic "0". I/O outputs keypad entires to the
microprocessor.

ES**

Sidetorie Equalization terminal connects an external resistor between the junction of RS, R9
and V-, At loop currents greater than the equalization threshold this resistor is switched in
to reduce the sidetone level.

CL*

Clock (Input) - Serially shifts data in or out of 110 pin. Data is transferred on negative edge
typically at 20kHz.

EV**

Voice equalization terminal connecis an external resistor between V+ and V-, for loop length
equalization. At loop currents greater than the equalization threshold this resistor is switched
in by the equalization circuit to reduce the transmit and receive gains.

16,17

CR1,CR2

Ceramic Resonator oscillator input and feedback terminals, respectively. The DTMF dialer
is intended to operate with a 500kHz ceramic resonator from which row and coJumn tones
are synthesized.

28

CAL

Amplitude CALibration terniinal for DTMF dialer. Resistor R14 from the CAL pin to V controls the DTMF output signal level at Tip and Ring.

35

FB

Feed Back terminal for DTMF output. Capacitor C14 connected from FB to V+ provides ac
. feedback to reduce the output impedance to Tip and Ring when tone dialing.

29

VR

Voltage Regulator output terminal. VR is the output of a 1.1 volt voltage regulator which
supplies power to the,speech network amplifiers and DTMF generator during signaling. To
improve regulator efficiency at low lin!l,current conditions, an external PNP pass-transistor
T1 is used in the regulator circuit. Capacitor C9 frequency compensates the VR regulator
to prevent o s c i l l a t i o n . '

33

BP

Base of a PNP Pass-transistor. Under long-loop conditions where low line voltages would
cause VR to fall below 1.1-volts, BP drives the PNP transistor T1 into saturation, thereby ,
minimizing the voltage drop across the pass transitor. At line voltages which maintain VA'
above. 1.1 volts, BP biases T1 in the linear region thereby regulating the VR voltage. Transistor
T1 also couples the ac speech signals from the transmit amplifier to Tip anti Ring at V+.

15

*KA2417 only

c8

When a Logic "1", disables the DTMF generator. Keypad is not

**KA2414 only

SAMSUNG SE~ICONDUCTOR

94

KA2414/KA2417 (DELETION) LlNEARII2L INTEGRATED CIRCUIT
PIN DESCRIPTION (Continued)
(See Fig. 12 for external component identifications.)
Pin

Designation

Function

34

V+

The more positive input to the regulator, speech, andDTMF sections connected to Tip and Ring
through the polarity guard diode bridge.

30

V-

The dc common (more negative input) connected to Tip and Ring through the polarity guard
bridge. ,

32

LR

DC Load Resistor, ResiStor R4 from LR to V- determines the dc input resistance at Tip and Ring.
This resistor is external not only to enable programming the dc resistance but also to avoid high
on-chip power dissipation with short telephone lines. It acts as a shunt load conducting the excess
dc line current. At low line voltages « 3.0 volts), no current flows through LA.

31

LC

DC Load CapaCitor. CapaCitor C11 from LC to V- forms a low-pass filter which prevents the resistor at LR from loading ac speech and DTMF signals.

20

MIC

Microphone negative supply terminal. The dc current from the electret microphone is returned
to V- through the MIC terminal which is connected to the collector of an on-chip NPN transistor. The base of this transistor is controlled either internally by the mute signal from the DTMF
generator, or externally by the logic input pin MM.

18

MM

Microphone Mute. The MM pin proVides a means to mute the microphone and transmit
amplifier in response to a digital control signal. When this pin is connected to a Logic "1" '
(> 2.0V) the microphone dc'return path through the MIC terminal is disabled.

22

TXI

Transmit amplifier Input. TXI is the input to the transmit amplifier from an electret microphone.
AC coupling c Rinp

I

TRC
Piem.
Tone

Ringer

Fig. 7

MICROPROCESSOR INTERFACE (KA2417 ONLy)
The MPU interface connects the keypad and OTMF sections of the ETC to a microprocessor for storing and retrieving
numbers to be dialed. Figure 8 shows the major blocks of the MPU interface section and the interconnections between the
keypad interface, OTMF generator and microprocessor. Each button of a 12 or 16 number keypad is represented by a fourbit code (Figure 9). This four-bit code is used to load the programmable counters to generate the appropriate rr:JN and column
tones. The code is transferred serially to or from the microprocessor when the shift register is clocked by the microproces- .
sor. Data is transferred through the 110 terminal, and the direction of data flow is determined by the Data Direction (~O) input
terminal. In the manual dialing mode, DO is a logic "0" and the four-bit code from the keypad is fed to the OTMF generator
by the digital multiplexer and also output on the 1/0 terminal through the four-bit shift register. The data sequence on the
1/0 terl)1inal is 83, 82, 81, 80 aQd is transferred on the negative edge of the clock input (CL). In this mode the shift register
load enable circuit cycles the register between the load and read modes such that multiple read cycles may be run for a singlekey closure. Six complete clock cycles are required to output data from the ETC and reload the register for a second look.
In the automatic dialing mode, DO is a Logic "1" and the four-bit code is serially entered in the sequence 83, 82, 81, 80
into the four-bit shift register. Thus, only four clock cycles are required to transfer a number into the ETC. The keypad is disabled in this mode. A Logic "1" on the Tone Output (TO) will disable tone outputs until valid data from the microprocessor
is in place. Subsequently 10 is switched to a Logie "0" to enable the OTMF generator. Figures10 and 11show the timing waveforms for the manual and automatic dialing modes and Table 2 specifies timing limitations.
The keypad decoder's exclusive OR circuit generates the OP and MS output signals. The OP output indicates (when at
a logic "1 ") t~at one, and only one, key is depressed, thereby indicating valid data is available to the MPU. The OP output
can additionally be used to initiate a data transfer sequence to the microprocessor. The MS output (when at a Logic "1") indicates the OTMF generator is enabled and the speech network is muted.
Pin A+ is to be connected to a source of 2.5 to 10 volts (generally from the microprocessor circuit) to enable the pullup
circuits on the microprocessor intel'fitce outputs (OP, MS, 1/0). Additionally, this voltage will pOwer the entire Circuitry (except
Tone Ringer) in the absence of voltage at V+. This permits use ofthe transmit and receive amplifiers, keypad interface, and
OTMF generator for non-typical telephone functions.

c8

SAMSUNG SEMICONDUCTOR

99

KA24141KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT
MICROPROCESSOR INTERFACE BLOCK DIAGRAM (KA2417 ONLY)

r-----------~~~~~ID
Excluslve-OA

8

}-=---,

DP
MS

8

Keypad

Keypad

Decoder 1---.:~r---'-'-""1

1-+""+'-I-..A'Comparators

Shift

~":~sterl--_---I
Enable

Fig.S

MPU INTERFACE CODES

[Q

0
~

0

0

0

0

0

0

0

[] 0

0
0

~

G

I

I

I

I

C1

C2

Cs

C4

Key
~

1
2

-

-

Row

Column

Code (B3 - BO)

1
1
1
2
2
2
3
3
3
4
1
2
3

1
2

1111
'0111
1011
1101
0101
1001
1110
0110 '
1010
0100
0011
0001
0010
0000
1100
1000

A1

3

A2

4

5
6
As

7
S
9
0
A
B
C
0

f- A4

*

#

.'

4
4
4

3
1'
2

3
1
2

3
2
4
4
4
4
1

3

Fig. 9

c8

,

,

sAMSUNG SEMICONDUCTOR

100

KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT
OUTPUT DATA CYCLE FROM KA2417

NOTE:
00

-

'ro may be low (Tone generator enabled) if desired.

~____t~~
__D_ep___se_d_________________________~
__
R_ele_as_ed-rl_

11111////1

1O~

MS~_ _~_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~

DP

_.

I

L

_ _ _ _ _ _--!tOPCl

H

CL

Fig. 10
INPUT DATA CYCLE TO KA2417
00

.--J

Tone generation interval

~1·__~loo_o_o________~~~

roJ

W~------~W

!

L

,

MS~
DP

_
CL

I
I

I

H

tOOCl

I--i tCllO

tH

f--+-l tl

---11.IlnfL...,~J1Jl.1UL
tos --II-- H tOH

IK)~~~
1st Digit

2nd Digit

3rd Digit

Fig. 11

c8

SAr-tSUNG SEMICONDUCTOR

101

· KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT

TABLE 1 - FREQUENCY SYNTttEStZER ERRORS

DTMF
Standard
(Hz)

Tone Output
Frequency with
500KHz Oscillator

697
770
852
941
1209
1336
1477
1633

696.4
769.2
'853.2
939.8
1207.7
1336.9
1479.3
1634.0

Row 1
Row 2
Row 3
Row 4
Column 1
Column 2
Column 3
Column 4

% Deviation
from Standard
-0.086
-0.104
+0.141
-0.128
-~.108

+0.067
+0.156
+0.061

TABLE 2 - TIMING LIMITATIONS

Symbol

Min

Typ Max

Unit

Ref

fel

Clock Frequency

0

t,:,

Clock High Time

15

p.S

10, 11

tl

Clock Low Time

15

p.S

10,11

t r, tf

Clock, Rise, Fall Time
Clock Transition to
Data Valid
Time from DPHigh
to CL Low
Time from DO High
toCLLow
Data Set-up Time
Data Hold Time
Time from cL Low
Low
Time from TO High
to DO High

toy
tOPCl
tOOCl
tos
tOH
tclTO
tTOOO

c8

Parameter

toro

SAMSUNG SEMICONDUC1"()R

20

30.

kHz
Figs.
Figs.

2.0

p.S

10

p.S

Fig. 10

20

p.S

Fig. 10

20

p.S

Fig. 11

10
10

p.S

"s

Fig. 11
Fig. 11

10

"s

Fig. 11

20

"s

Fig. 11

102

KA2414/KA2417 (DELETION) LlNEARII2L INTEGRATED CIRCUIT
APPLICATIONS INFORMATION
Fig 12 specifies a typical application circuit for the KA2414 and KA2417.
Complete listing of external components are provided at the end of this section along with nominal component values.
The hook switch and polarity guard bridge configuration in Fig. 12 is one of several options. If two bridges are used, one
for the tone ringer and the other for speech and dialer circuits, then the hook switch can be simplified. Component values
should be varied to optimize telephone performance parameters for each application. The relationships between the application circuit components and certain telephone parameters ,are briefly described in the following:

On-Hook Input Impedance.
R1, C15, and Z3' are significant components for on-hook impedance. C15 dominates at low f~uencies, R1 at high
frequencies and Z3 provides the non-linearity required for 2.5V and 10V impedance signature tests. C15 must generally
be s1.01'F to satisfy 5.0Hz impedance specifications. (EIA RS-470)

Tone Ringer Output Frequencies
R3 and C13 control the frequency (fo) of a relaxation oscillator.
Typically fo= (R3 C13 + S.OpS) -1. The output tone frequencies are fof10 and fo/8. The warble rate is fo/64O. The tone ringer
will operate with fo from 1.0KHz to 10KHz. R3 should be limited to values between 150K and 300K.

Tone Ringer Input Threshold
After R1, C15. and Z3 are chosen to satisfy on-hook impedance specifications, R2 is chosen for the desired ring start
threshold.
Increasing R2 reduces the ac input voltage required to activate the tone ringer output. R2 should be limited to values between
O.8K and 2.0KO.

Off-Hook DC Resistance
R4 conducts the dc line current in excess of the speech and dialer bias current. Increasing R4 increases the input resistance
of the telephone for line currents above 10mA. R4 should be selected between 300 and 1200.

Off-Hook AC Impedance
The ac input impedance is equal to the receive amplifier load impedance (at RXO) divided by the receive amplifier gain
(voltage gain from V+ to RXO). Increasing the impedance of the receiver increases the impedance of the telephone.
Increasing the gain of the receiver amplifier decreases the impedance of the telephone.

DTMF Output Amplitude
R14 controls the amplitude of the row and column DTMF tones. Decreasing R14 increases the level of tones generated
at V+. The ratio of row and column tone amplitudes is internally fixed. R14 should be greater than 200to avoid excessive
current in the DTMF output Amplifier.

Transmit Output Level '
R10 controls the maximum signal amplitude produced at V+ by the transmit amplifier. Decreasing R10 increases the transmit
output signal at V+. R10 should be greater than 2200 to limit current in the transmit amplifier output.

c8

SAMSUNG SEMICONDUCTOR

103

II

KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT
Transmit Gain
The gain from the microphone to the telephone line varies directly with R11. Increasing R11 increases the signal applied
to R10 and the ac current driven through R10 to the telephone line. The closed loop-gain from the mi,crophone to the TXO
terminal should be greater than 10 to prevent transmit amplifier oscillations.
Note: Adjustments to transmit level and gain are complicated by the addition of receiver sidetone current to the transmit
amplifier output current at V+. Normally the sidetone current from the receiver will increase the transmit signal (ifthe
current in the receiver is in phase with that in R10). Thus the transmit gain and sidetone levels cannot be adjusted
independently.

Receiver Gain
Feedback resistor R6 adjusts the gain at the receiver amplifier. Increasing R6 increases the receiver' amplifier gain.

Sidetone Level
'Sidetone reduction is achieved by the cancellation of receiver'amplifier input signals from ~9 and R5. R8, R15, and C6
determine the phase of the sidetone balance signal in R9. The ac voltage at the junction of R8 and R9 should be 1800 out
of phase with the voltage at V+. R91s selected such that the signal current in R9 is slightly greater than that in R5. This insures
that the sidetone current in the receiver adds to the transmit amplifier output current.

Microprocessor Interface (KA2417 Only)
The six microprocessor interface lines (DP, TO, MS, DO, 1/0, and cr.) can be connected directly to a port, as shown in
Figure 13. The DP line (Depressed Pushbutton) is also connected to an interrupt line to signal the microprocessor to begin a read data sequence when storing a number into memory. The KA2417 clock speed requirement is slow enough
(typically 20kHz) so that it is not necessary to divide down the processor's system clock, but rather a port output can be
toggled. This facilitates synchronizing the clock and data transfer, eliminating the need for hardware,to generate the clock.
The DO pin must be maintained at a Logic "0" when the microprocessor section is not in, use, so as tei permit normal
operation of the keypad.
When the microprocessor interface section is not in use, the supply voltage at Pin 12 (A+) may be disconnected to conserve power. Normally the speech circuitry is powered by the voltage supplied at the V+ terminal (Pin 34) from the telephone
lines. During this time, A+ powers only the active pullups on the three microprocessor outputs (DP, MS, and VOl. When
the telephone is "on-hook," and V+ falls below 0.6cvolts, power is then supplied to the telephone speech and dialer circuitry
from A+. Powering the circuit from the A+ pin permits communication with a micrpprocessor, andlor use of the transmit
and receiver amplifiers" while the telephone is "on-hook."

Equalization of Speech Network (KA2414 Only)
Resistors R17 and R18 are'switched into the circuit when the voltage at the LR terminal exceeds the equalization threshold
voltage (iypically 1.65V). R17 reduces the transmit and receive gains for loop currents greater than the threshold (short loops)
by attenuating signals at tip and ring. R18 reduces the sidetone level which would otherwise increase when R17 is switched
,
into the circuit. The voltage VLR at LR terminal is given by
VLR =(lL-ls)xR4.
where IL =Ioop current
Is=dummy load current (6.0 mA)+speech network current (4.0 mAl.
Thus resistor R4 is selected to activate the equalization circuit at the desired loop current, However, R4 must be selected keeping in mind the fact that it also controls the dc resistance of the telephone. CapaCitors C18 and C19 prevent dc current
flow into the EV and ES terminals. This reduces cliCks alld also prevents changes in the dc characteristic of the telephone
when the EV andES terminals are switched to low impedance.

i8

SAMSUNG SEMICONDUCTOR

104

KA2414/KA2417 (DELETION) LlNEARlI2L INTEGRATED CIRCUIT
APPLICATION CIRCUIT 1
DTMF Pad
Row-Column Switch Clolsure

4
7

5
8
S2

I

SI, S2, controlled
by hook switch; Illustrated
in "on-hook"

condition.

Rt8

RING

C17

Electret
Microphone
'Rx used with
2-terminal mike only_

APPLICATION CIRCUIT 2

Fig_ 12

DTMF Pad
Row-Column Switch Clolsure

SI, S2, controlled
by hook switch; Illustrated
in "on-hook"

condition.

MC6800
System

vss

'Rx used with
2-termlnal mike only.

Fig_ 13

c8

SAMSUNG SEMICONDUCTOR

105

KA2414/KA2417 (DELETION) LlNEARII2L INTEGRATED CIRCUIT

EXTERNAL ,COMPONENTS
(Component labels referenced to Fig. 12, Fig. 13)
Capacitors

Nominal value

I

Description'

C1

1.0"F,1OV

Tone ringer filter capacitor: integrates the voltage from current sense resistor R2
at the input of the threshold detector.

C2

4.7"F,25V

Tone ringer input capacitor: filters the rectified tone ringer input signal to smooth
the supply potential for oscillator and output buffer.

C3

1.0"F,3.OV

Transmit limiter'low-pass filter capaqitor: controls attack and decay time oftransmit
peak limiter.

C4,C5

O.1/IF

Transmit amplifier input capacitors: prevent dc current flow into TXL pin and
attenuates low-frequency noise on microphone lead.

C6

O.05"F

Sidetone network capacitor: provides phase-shift in sidetone path to match that
caused by telephone line reactance.

C7,C8

O.05"F

Receiver amplifier input capacitors: prevent dc current flow into FM terminal and
attneuates low frequency noise on the telephone line.

C9

2.2"F,3.0V

VR regulator capacitor: frequency compensates the VR regulator to prevent
oscillation.

C10

O.Q1,.F

Receiver amplifier output capacitor: frequency compensates the receiver amplifier
to prevent oscillation.

C11

O.1,.F

DC load filter capacitor: prevents the dc load circuit from a:ttenuating ac signals
onV+.

C12

O.01,.F

Telephone line by pass capacitor: terminates telephone line for high frequency
signals and preVents oscillation in the VR regulator.

C13

620pF

Tone ringer oscillator capacitor: determines clock frequency for tone and warble
frequency synthesizers.

C14

O.1,.F

DTMF output feed back capacitor: ac couples feed back around the DTMF output
amplifier which reduces output impedance.

C15

1.0"F, 250vac
NoncPoiarized

tone ringer line capacitor; ac couples the tone ringer to the telephone line partially
------{,5
NON INVERTING
OllTPUT
OUTPUT
AMP

~------------------------------------~3~----------------~4~------------~--------------------____------------~
GND

SWEEP RATE '
CONTROL CAPACllOR

OUTPUT FREQUENCY
CONTROL RESISlOR

Fig. 1

c8

SAMSUNG SEMICONDUCTOR

108

KA2418

LINEAR INTEGRATED CIRCUIT

=

ABSOLUTE MAXIMUM RATINGS (Ta 25°C)
Characteristic
Calling Voltage (f=50Hz) Continuous
Calling Voltage (f=50Hz)
5 Sec ON/10 Sec OFF
Supply Current
Operating Temeprature
Storage and Junction Temeprature

Value

Unit

VAB

90

Vrms

VAe

110

Vrms

Icc
Top
TSIg

22
-20- + 70
-65-+150

mA
°C
°C

Symbol

ELECTRICAL CHARACTERISTICS
(T. = 25°C unless otherwise specified)
Characteristic

Symbol

Supply Voltage

Vee

Current Consumption without Load

Ie

Activiation Voltage

VON

Activiation Voltage Range

VONR

Sustaining Voltage

VOFF

Differential Resistance in
Off Condition

Ro

Output Voltage Swing

VOUT ,

Short Circuit Current

Test Condition

Min

Typ

Max
26

V

1.5

1.8

mA

12.2

13

V·

8

10

V

8

8.8

V

Vs=8.8 to 26V

RA=1kll

6.4

lOUT

Unit

kll
Vcc-3

V

35

mA

AC OPERATION
Characteristic

Symbol

Output Frequencies
fOUT'
fouT2

Test Condition
Vee =26V, R, =14kll
Vce=OV
Vcc=6V

fouT' Range

R, =27kll to 1.7kll

Sweep Frequency

R,=14kll,C,=100nF

c8

SAMSUNG SEMICONDUCTOR

Min

lYP

Max

Hz'
Hz

1,900
1,300
0.1

15
10

Unit

KHz
Hz

109

LINEAR INTEGRATED CIRCUIT

KA2418
TEST AND APPLICATION CIRCUIT

r------------------~w_-__,

I

R.

I

1"F, 25(11//>C

TIP

O.22,.F

1 2.2KO

.----"1'"-----U------l
C2

I

R2

I

I

10K~

10K

6

8

I
I

I
I
I

I

VAS TEL LINE

I
I

Vour
4

I

~i~
I

I

Cl
100nF

RING

I

R,

I

12Kll

I
I

I

'-______
h

. 2.67-10"
= R,(KO)

I
....------------..J

--'_~--_---_+_-----

12=

1000
C,(nF)

~h

fsweep=·--

7

Fig. 2

DESCRIPTION
The KA2418 tone ringer derive its powen supply by rectifying the AC ringing signal. It uses this power to activate two tone
generators. The two tone fraquencies generated ara switched by an internal oscillator in a fast· sequence and made audible
across an output amplifier in the loudspeaker; both tone fnequencies and the switching frequency can be externally adjusted.
The device can drive either dineclly a piezo ceramic converter (buzzer) or small loudspeaker. In case of using a loudspeaker,
a transfonmer is needed.
An internal shunt voltage Regulator provides DC voltage to output stage, low fraquency oscillator, an High fnequency oscillator. To protect the IC from telephone line transients, a zener Diode· is included.

EXTERNAL CC;>MPONENTS (refer to test circuit)
R, : Output fnequency control nesistor
C, : Sweep nate control capacitor
R2 : Line input rasistor. R~ffects the tone ringer·input impedance. It also influences ringing threshold voltage and
limits currant from line transients.
.
C2 : Line input capacitor. C2AC couples the tone ringer to the telephone line and controls ringer input impedance at
low fnequencies.
C3 : Ringer supply capacitor, C3 filters supply voltage for the tone generating circuits.
R. : Activation voltage adjustable resistor

c8 SAMSU~G

SEMICONDUCTOR

110

KA2420 (DELETION)

LINEAR INTEGRATED CIRCUIT

VOICE SWITCHED SPEAKER-PHONE
28 DIP

The KA2420 speaker phone chip includes amplifiers, attenuators, and
control functions necessary to design a high quality speaker phone
system. It also includes a.microphone amplifier and audio power
amplifier for speaker, background sound level monitoring system, attenuation control svstem, and the necessary regulated voHages for
internal and the external circuits. This will permit operation from the
mains with no additional power supply required.
The chip select pin will facilitate power down 'when the chip is not
selected. The volume control may be implemented by using an external
potentiometer. The KA2420 can be used in a wide variety of applications
such as; intrecom systems, business, automotive or household
telephones.

28 SOP~

FEATURES
•
•
•
,•

•
•
•
•

Level detection and attenuation controls on single chip
Monitoring for background noise level with large time constant
On-chip regulation for supply and reference' voltages
Wide range of operation due to signal compression
Very low output power (10mW typ.) with peak limiting for minimizing distortion
Chip Select allowing standby mode of operation
ORDERING INFORMATION
Volume can be controlled linearly
28 pin' plastic DIP & SOP package
Device
Package Operating Temperature

BLOCK DIAGRAM

KA2420N

28 DIP

KA2420D

28 SOP

-20_+60°C

r--------------------,I

I

TRANSMIT CHANNEL

I

SPEAKER I

~I~-R...E-C-EI-VE-C-H-A-N-NE 1.6V), the chip is in the standby mode drawing O.5mA. An open CS pin is a logic "0 ". Input
impedance is nominally 140KO. The input voltage should not exceed 11V.

19

SKI

Input to the speaker amplifier. Input impedance is nominally 20KO.

Vee

A 5.4V regulated output which powers all circuits except the speaker amplifier output stage. Vee
can be used to power external circuitry such as a microprocessor (3.0mA max.). A filter capaCitor
is required. The KA2420 can be powered by a separate regulated supply by connecting V+ and
Vee to a voltage between 4.5V and 6.5V while maintaining CS at a logic "1".

20

c8

SAMSUNG SEMICONDUCTOR

112

KA2420 (DELETION)
PIN DESCRIPTION

LINEAR INTEGRATED CIRCUIT

(Continued)
Description

Pin

Name

21

VB

An output voltage equal to approximately Vcc12 which serves as an analog ground for the
speakerphone system. Up to l.5mA of external load current may be sourced from VB. Output
impedance is 2500. A filter capacitor is required.

22

Gnd

Ground pin for the IC (except the speaker amplifier)

23

XDC

Transmit detector output. A resistor and capacitor at this pin hold the system in the transmit mode
during pauses between words or phrases. When the XDC pin vohage decays to ground. the
attenuators switch from the transmit mode to the idle mode. The internal resistor at XDC is
•
nominally 2.6KO (see Fig. 1)

24

VLC

Volume control input. Connecting this pin to the slider of a variable resistor provides receiVe mode
volume control. The VLC pin voltage should be less than or equal to VB.

25

ACF

Attenuator control filter. A capacitor connected to this pin reduces noise transients as the
attenuator control switches levels of attenuation.

26

RXO

Output of the receive attenuator. Normally this pin is ac coupled to the input of the speaker
amplifier.

27

RXI

Input of the receive attenuator. Input resistance is nominally 5.oKO.

RRX

A resistor to ground determines the nominal gain of the receive attenuator. The receive channel
.
gain is directly proportional to the RRX resistance.

28

ABSOLUTE MAXIMUM RATINGS (Voltages referred to Pin 22, T.=2S0C)
Ch~racteristic

Value

Unit

Speaker Amp Ground (Pin 14)
V + Terminal Voltage (Pin 16)
CS (Pin 18)
VLC (Pin 24)
Storage Temperature

+3.0. -1.0
+12. -1.0
+12. -1.0
Vee. -1.0
-65-150

V
V
V
V
·C

"Maximum Ratings" ~re those values Ileyond which the safety of the device cannot be guarariteed. They are not meant
to imply that the devices should be operated at these limits. The "Electrical Characteristics" tables provide conditions
for actual device operation.

RECOMMENDED OPERATING CONDITIONS
Characteristi~

Value

Unit

O-S.O

mVrrns

Speaker Amp Ground (Pin 14)

-10-10

mV

V+ Terminal Voltage (Pin 16)

+6.0-11

V

Microphone Signal (Pin 9)

CS(Pin 18)

0-11

V

lee (Pin 20)

0-3.0

mA

0.5SVB-VB

V

Receive Signal (Pin 27)

0-2S0

mVrrns

Ambient Temperature

-20:"'6(l

OC

VLC(Pin24)

c8

SAMSUNG SEMICONDUCTOR

113

.

.

KA2420.(DELETION)

.

.

LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Refer-to Fig. 1)
Characteristic

Symbol

Test Condition

Min

lYP

Max

Unit

9.0
800

mA

SUPPLY VOLTAGE
V+ Supply Current

Iv +

V+=11V, Pin 18=0.7V .
V+=11V, Pin 18=1.6V

Vee Voltage

Vee

V+=7.5V

Vcc Line Regulation

IlVC9

4.9

Ji'..

5.4

5.9

V

6!5V

:D

Z

-t

m

C)

~
~

m

c

-o.
0

:D

......
......

0>

Fig. 1

·1 §i

KA2420 (DELETION)

LINEAR INTEGRATED CIRCUIT

TRANSMIT ATTENUATOR Vs RTX

-10

JaxGl.n

-~

+10

+10

....... <:.6·~l
i'..

....

-20

~-30

r--.,

"lr-..

1

MaJG~innU
- - &V8cf.l50mV

-20

e

/,'

\
I""

-10
"

~

Max Attenuation
&V8cf·l50mV

-40

/

~

-30

~
./ ~Max Attenuation

-40

~

-50

-60

RECEIVE ATTENUATOR Vs RRX

RJ.JK

f-vLf"la

I'

-70

-50

"

'

r-- RR• 3OK
VLC·VB

RRX(OHMS)

Fig. 3

Fig. 2

GAIN AND ATTENUATION
Vs RESISTOR RATIOS

-10

-20

JRX~l~K

VB

+5 t--RTX.91K
RR·3OK

l""'r--.

l/~

f8

-60

-15

i, ~

(ID(

"

~

,

./

40

/"

/

:

-.l

I
DB

~

1.0

/

"'

~

I--......

L

"

60
80
100
&YacI (MILUVOLTS)
Fig. a

,......

J

~~

/
/

200

V

f'..

RR=3OK
RTX-91K
RRX.18K

-25

c8

,

Level

LOG AMP TRANSFER CHARACTERISTICS

GRX . / "

-20

-35

,

0.4
D.6
. YLCIV.

0.2

i

"-

-15

-30

r\
Minimum

:-- Recommended

250

-5

18

:

1,\

Fig. 5

.

-10 f--

JL

~

-40
10

5.0

ATTENUATOR GAIN Va aYacf

+5

V

v:

VLC.va

1.0
RATIO
Fig. 4

.i.

: I\.

-35

1
0.5

V
GRy'"

Li,

-30

I 1111
0.1

,,
,

:

i)

ATX vs. RTXlRR
&V8cf·150mV

ARX vs. ARXIRR
&V8cf·6.0mV

\

-20

~

I<'

-50

:

Receive

I"roo...

-40

!
GTX

-10 t - - Modo

i)(

-30

r-..

-5 t--LCUi1

V

&V8cf-l50mV

'II

ATTENUATOR GAIN Vs VLC

~T) R~x/bR

r-- ..:1Vacf= 6.0mV

~::~ RRXlRR~

lOOK

10K

lK

1M

RTX(OHMS)

+10

II

Usable Range -

-70

lOOK

10K

.,

&V8cf-6.OmV

-80

50 -

f'-

120

INPUT~

CURRENT
(RLI, TLI. XOI)

~
140

SAMSUNG SEMICONDUCTOR

0

180

I Vi

-20

+

(RLO. TLO, CP2)-

OUTPUT,

I I VOLjE

-40
-80
DC INPUT CURRENT (foA)
Fig. 7

-80

117

KA2420 (DELETION)

LINEAR INTEGRATED CIRCUIT
SPEAKER AMP OUTPUT
Va SUPPLY VOLTAGE

,.

LOG AMP TRANSFER CHARACI'ERISTICS

".,.. ~

120

/

I-I--+-+-

/ .V

2D

0

I

No load
250 Load

I

'/

/

VL
30

V

k":

--

.

4.05.06.07DS.o
V+ (VOLTS)
fig. I

'~r

,
t--

9.\..1011

RESPONSE AT CP2 AND CPt
600

-

I ",vepl (Pin 1'1)

500

./

,...

-~...-

~

/

V
/

I
I
100

fl

AVCP2(Pin 12)

V

0

1O!J
150
YMCO (rrN RMS)
Fig. 1.

200

TRANSMIT DETECTOR OPERATION

Inpu~i:~1111111~1111111111111111111111111111111111~I---~m~llilllllllllllllllll~

J

1 .
CP2 (Pin 12) .1

.

I.

..IV,

Solid

~~~~~Pl

Don.dLine=.
Noninverting

\

. Cit
dV ~ c(~'ZV/s.ec)
10pA

(~200mV)

.

r-r--------------

I

~~~~~rT~;~~'t __ ~

~

~.

.

I·

:1' 2.7xav,

r

36rnV

7

Slope = O.5V/sec

I
4 Volts

XDC (Pin 23) ,~

c8

SAMSUNG SEMICONDUCTOR

NOTE: Above values are typical based
Fig. 11

on components shown in Fig. 1.

118

LINEAR INTEGRATED CIRCUIT

KA2420 (DELETION)

SUPPLY CURRENT Vs SUPPLY VOLTAGE
Vs SPEAKER POWER

SUPPLY CURRENT Vs SUPPLY VOLTAGE

ao

35

71J

/

6.0

V1

100.1-

\

30

'I

5.0

'i+

I
8Oi-

I

OS=o

5OJ-

25
VSKOa OVrms

~

.§.

4.0

..!

..!

20

3.0

~

20rriW . ---

I

21J
,A

15
1.0

./ :...t

CS=1

I
4.0

5.0

6.0

71J 8.0 9.0
V+(VOLTS)
Fig. 12

10

6IJi

./

10

11

10rriW,

41J

6.0

5.0

7.0 6.0 9.0
V+(VOLTS)
Fig. 13

10

11

SUPPLY CURRENT Vs SUPPLY
VOLTAGE (see Fig. 14)
25

i
i

ALTERNATE POWER SUPPLY CONFIGURATION

,i-,

20

-cs

Vee

16

22

.

V+

iI

,,,
,
,,
,

I

i
,
,,

I

Vs

1i7

,/

(Regu lated supply)

Zl1000.F
Fig. 14

5.0

r.'7
o

~

4.0

SWITCHING TIME

I
I
II

,'

I

,,

10

Is

J-------!

Operating Range ...

,
,,

15
20

Allowahle

,,

KA2420

18

I
I
I

L--- V-

.......-;

,
,,

/

,/

i

,

:
,,,
I

I
I
I

5.0

61J
V.(VOLTS)
Fig. 15

7.0

6.0

The switching times of the speakerphone depends on the external components and the instantanious operating conditions
at the time when a change takes place. For example, the switching time for changing between transmit ~nd receive modes
is much longer than that from idle to transmit.
The components connected at pin 5 "transimit turn-on': pin 6 "transmit-turn-off': pin 7 '~receive-turn-on" and pin 8 "receiveturn·off" have major influence on the timing between the transmit and receive modes. The Tx·Rx comparator compares
the relative and not the absolute values so the above referenced four timing functions interact with each other. The timing
from transmit to idle is affected by the components at pins 11, 12, 13 and 23. The timing from idle to transmit is faster and
hence the components have no major influence on it.

c8SAMSUNG SEMICONDUCTOR

119

I

LINEAR INTEGRATED CIRCUIT

KA2420 (DELETION)

The table below indicates the degree of influence of various components on the switching time, including the volume
cont.rol;
Additionally, the following should be noted:
1) The RCs at'Pin 5 and Pin 7 affect the sensitivity of the respective log amplifiers, or how loud the speech must be for
gain control of the speakerphone circuit.
2) The RC at Pin 13 controls the sensitivity of the transmit detector circuit.
3) The switching speed and the relative response to transmit signal are affected by the volume control, in manner as follows:
When the \/OIume control reduces, the signal at TXO increases, and consequently the signal to the TLI pin in the receive
mode circuit.
Components
RC at Pin 5
RC at Pin 6
AC at Pin 7
AC at Pin 8
AC at Pin 11
C at Pin 12
AC at Pin 13
AC at Pin 23
V at Pin 24
C at Pin 25

I
I

Tx to Rx

Rxto1X

,

high
medium
medium
high
low
low
low
low
medium
medium

medium
high
high
medium
no influence
no inlluence
no influence
no influence
no influence
medium

I

Txtoldle
no influence
. no influence
no influence
noinlluence
medium
high
low
high
·noinlluence
low

. Switching response times for the circuit of Fig. 1 are shown in the photographs of Fig. 16 and Fig. 17.
In Fig. 16, the circuit is supplied a continuous receive signal of 1.1mVp.p at AXI as shownTrace #3. Mel as shown. Trace
#1 openites a repetitiVe signal of 7.2rriVp.p for 120msec, and repeated every 1sec. Trace #2 is the TXO output being about
650mVp.p at its maximum. Trace #4 is the RXO output being about 2.2mVp.p at its maximum.
The switching time from the receive mode to transmit mode is about 40msec required for TXO to turn on, and for RXO
to tum off. After the signal at MCI is turned off, the switching time back to the receive mode is about 210msec.
In Fig. 17 a continuous signal of 7.6rriVp.p is supplied to MCI as shown Trace #1, and a repetitive burst signal of 100rriVp.p
is supplied to AXI as shown Trace #3 for 12Omsec;and repeated every 1sec. Trac~ #2 is the TXO output and is about
9OrriVp.p at its, maximum, and Trace #4 shows the AXO outpufbeing about 150rriVp.p at its maximum, In this sequence, the
circuit switches between the idle mode\and the receive mode. The required 'switching time from idle to receive modeS is
about 70msec as shown in the first part of Trace #2 and Trace #4. After the receive signal is turned off, the switching time
back to the idle mode is about 100msec.
All of above mentioned switching times can change significantly not only by varying the external components but also
by varying the amplitude of input signals.
.

IDLE-RECEIVE SWITCHING

TRANSMIT-RECEIVE SWITCHING
Burst Input @ MCI

2

Oulpul @ TJ(O

3

Inpul@RXI

4

Output@RXO

Inpul@ Mel
OUlpul@TXO

2

Bursllnput @ RXI

OUlpUI- RXO
Time Base=30msJOiv

Fig. 16

c8

SAMSUNG SEMICONDUCTOR

Fig. 17

120

LINEAR INTEGRATED CIRCUIT

KA2420 (DELETION)

BASIC LINE POWERED SPEAKERPHONE
S1

.----------..----+__
'--_---'1-:...-

56K

".._~_

rTXIIDLE

..J Ax

_ _--. _"

rTx

:..J Idle

Compartors A & B=LM393 (Dual)
Fig. 19

qs'SAMSUNG SEMICONDUCTOR

121

KA2425A1B

"

LINEAR INTEGRATED CIRCUIT

TELEPHONE SPEECH NETWORK WITH
DIALER INTERFACE

18 DIP

The KA2425AiB is a Telephone Speech Network Integrated Circuit.
which Incorporates adjustable transmit, receive, and sldetone functions,
a dc loop interface Circuit, tone dialer Interface, and a regulated output
voltage for a pulse/tone dialer. Also included is an equalization amp
which compensates gains for line length variations. The conversion from
2 to 4 wire Is accomplished with a supply voltage as low as 1.5 volts.

FEATURES
• Transmit, Receive, and Sidetone Gain Set by External Resistors
• Loop Length Equalization for Transmit, Receive, and Sidetone
Functions
• Low Voltage Operates Down to 1.5 volts (V+) in Speech Mode
• Provides Regulated Voltage for CMOS Dialer
• MUTE: KA2425A, MUTE: KA2425B
• DTMF Output Level Adjustable with Single Resistor
• Compatible with 2·Termlnal Electric Microphones (ECM)
• Compatible with Receiver Impedance. of 1500 and Higher

BLOCK DIAGRAM
Tip

.-----}

~~elver

Ring 0 - - - - '
(Mute)

voo
Regulator

Mute
Logic

DTMF
Driver

DTMF
Input

c8

To
Dialer
Circuit

SAMSUNG SEMICONDUCTOR·

•

From
Microphone

Mute
Input

PulseiTone
Select

122

KA2425A1B

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
(Voltage referred to V-, Ta=25·C) (see Note 1.)
Characteristic

Value

V+ Voltage
Voo (externally applied, V + =0)

Unit

-1.0, +18

Vdc

-1.0 +6

Vdc

VLR

- 1.0, V + - 3.0

Vd

MT, MS Inputs

-1.0, Voo

+1.0

Vdc

Storage Temperature

. -65, +150

·C

Note 1: . Devices should not be operated at these values. The "Recommended Operating Conditions" provide
conditions for actual device operation:

RECOMMENDED OPERATING CONDITIONS
Characteristic
V + Voltage (Speech Mode)
(Tone Dialing Mode)

Value

Unit

+1.5 to +15
+3.3 to + 15

Vdc
Vdc

o to

Irxo (Instantaneous)
Ambient Temperature

ELECTRICAL CHARACTERJSTICS
Characteristic

10

mA
·C

-20 to +60

Symbol

(Refer to Figure 1) (Ta=25·C)
Test Conditions

Min

Typ

Max

Unit

IL= 2O rn A
IL=30mA
IL= 120mA
IL=20mA
IL=30mA

2.6
3.0
7.0
4.1
4.6

3.2
3.7
8.2
4.9
5.4

3.8
4.4
9.5
5.7
6.2

V+=1.7V
V + = 12V
V + = 12V

4.5
5.5
6.0

7.1
8.4
8.8

9.0
12.5
14.0

V+ -VLR
V+ -VLR

-

2.7
4.3

-

36

57

94

KG

LINE INTERFACE
V+Voltage
Speech/Pulse Mode
Speech/Pulse Mode
Speech/Pulse Mode
Tone Mode.
Tone Mode

V+

V +Current (Pin 12 Grounded)
Speech Mode
Speech/Pulse Modes
Tone Mode

1+

LR Level Shift
Speech/Pulse Mode
Tone Mod.e
LC Terminal Resistance.

Vdc

mA

6.VLR

RLe

VdC

VOLTAGE REGULATORS
VR Voltage
Load Regulation
Line Regulation

VR
6.VRLO
6.VRLN

(V+=1.7V)
OmA100KO. Signals from
the line and sidetone amplifier are summed at RXI.

8

RXO

Receive amplifier output. RXO is biased by a 2.5mA current source.
Feedback maintains the DC bias voltage at:::: O.65V. Increasing R4
(between RXO and RXI) will increase the receive gain. C4 stabilizes
. the amplifier. C3 couples the signals to the receiver. The 2.5mA
current source is reduced to O.4mA when dialing.

9

RMT

Receiver Mute. The AC receiver current is retumed to V - through
an open collector NPN transistor and a parallel 10KO resistor. The
base of the NPN is controlled by'an internal mute signal. During
dialing the tr.ansistor is off, lel!ving the 10KO resistor in series with
the receiver.

10

V-

Negative supply. The most negative input connected to Tip and Ring
, through the polarity guard diode bridge.

11

VR

Regulated voltage output. The VR voltage is regulated at 1.2V and
biases the microphone ,and the speech circuits. An internal series
pass 'PNP' transistor allows for regulation with a line voltage as low
as 1:5V. Capacitor Cs stabilizes the regulator.

12

LC

DC load capacitor. An external capacitor C7 and an internal resistor
form a low pass filter between V + and LR to prevent AC signals
from being loaded by the DC load resistor R5• Forcing LC to V - will
turn off the DC load current and increase the V + voltage.

,
,

Description

Name

SAMSUNG SEMICONDUCTOR

126

KA2425A1B

LINEAR INTEGRATED CIRCUIT

PIN DESCRIPTION

(See Fig. 1) (Continued)

Pin No.

Name

Description

13

LR

DC load resistor. Resistor R5 from LR to V - determines the DC
resistance of the telephone, and removes power dissipation from the
chip. The LR pin Is biased 2.8 volts below the V + voltage (4.5 volts
in the tone dialing mode)

14

V+

Positive supply. V + Is the positive line vol1age (from Tip & Ring)
through the polarity guard bridge. All sections Qf the KA2425A/B are
powered by V + .

15

Voo

Voo regulator. Voo Is the output of a shunt type regulator with a
nominal voltage of 3.3V. The nominal output current is Increased
from 550I'A to 2mA when dialing. Capacitor Cg stabilizes the
regulator and sustains the Voo voltage during pulse dialing.

~6

TI

Tone input. The DTMF signal from a dialer circuit Is input at TI
through an external resistor R7. The current at TI is amplified to drive
the line at V +. Increasing R7 will reduce the DTMF output levels.
The Input Impedance at TI is nominall 1.25KO.

17

MS

Mode select. This pin is connected through an internal 6OOKO
resistor to base of an NPN transistor. A logic "1" (>2.0V) selects
the pulse dialing mode. A logic "0" «0.3V) selects the tone dialing
mode.

18

Ml

Mute input for KA2425A. MT is connected through an internal 100KO
resistor to the base of a PNP transistor, with the emitter at Voo. A
logic "0" «1.0V) will mute the network for either pulse or tone
dialing. A logic "1" (>Voo -0.3V) puts the KA2425A into the speech
mode.

MT

c8

II

Mute input for KA2425B. MT Is connected through an internal 5OKO
to the base of a NPN transistor, with the collector to the base of a
PNP transistor. A logic "1" (>Voo-0.3V) will mute the network for
. either pulse or tone dialing. A logic "0" « 1.0V) puts the KA2425B
into the speech mode.

sAMSUNG SEMICONDUCTOR

127

LINEAR INTEGRATED CIRCUIT

KA2425A1B
Fig. 1 Test Circuit

'Tip

0-------_

C8
2.0

~

Rlngo-----------

Rl

lOOK

R7
22K

DTMF Input >-.J\I\/v----J

Voo

Voo

Output---~-{15}---1r-----.J

C9

o.l;h

Mute>-----'~

Pulse/Tone

Select

c8

SAMSUNG SEMICONDUCTOR

128

KA2425A/B

LINEAR INTEGRATED CIRCUIT

Fig. 2 DTMF Driver Test
22K
v+

TI
400mVrms
1.0KHz

,+;

0.02

KA2425A1B

Iloop

LR

M'f
.:.1.0V
MS

1

LC

V-

47

I

Fig. 3 Transmit and Sidetone Level Test
0.05
VR

TXI

'---II1II11---1 EQ
Txe
v+

III

<
..,

8.2K

('II

~

LR

lo:

LC

c(

Voo

Mf
v-

Fig. 4 AC Impedance, Receive and Sidetone Cancellation Test
150K
v+
8.2K
STA

V+

0.05
RXI
33K
Rxe
10

'~f·~l
c8

SAMSUNG SEMICONDUCTOR

III

LR

..,<
~

lo:

f'

47

('II

0.2

hoop

6000
250mVrms (VS)
1,OKHz

129

CMOS INTEGRATED CIRCUIT

KS5805A1KS5805B

TELEPHONE PUlSE DIALER WITH REDIAL
The KS5805AJB is a monolithic CMOS integrated circuit and provide!j
all the features required for implementing a pulse dialer with redial.

18 DIP
I

FUNCTIONS
•
•
•
•
•
•
•
•

Muie output logic "0"
Pulse output logic "0"
RC oscillation for reference frequency
Designed to operate directly from the telephone line
Used CMOS technology for low voltage, low power operation
PoWer up clear circuitry
KS580SA pin 2: V REF
KS5805B pin 2: Tone out

FEATURES
• Uses either a standard 2 of 7 matrix keyboard with negative true
common or the inexpensive form A·type keyboard
• Make/Break ratio can be selected
.• Redial with· or ff
• Continuous MUTE
.
• Tone signal output or on-chip reference Voltage by bonding option
on chip
• 10 ppS/20 pps can be selected

. TEST CIRCUIT
GND

vee
vee~~--------------------------~--------~--------,

1Mil

KS5805 AlB

66% Break
20pps

Fig. 1

c8

SAMSUNG SEMICONDUCTOR

10pps

130

CMOS INTEGRATED CIRCUIT

KSS80SAlKSs80SB

ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Characteristic
DC Supply Voltage
Voltage on Any Pin
Power Dissipation
Operating Temperature
Storage Temperature

Symbol
Vee
Y'N
Po
Topr
Tstg

value

Unit

6.2
Vee +0.3. Gnd-0..3
SOO.O
-30-+60
-6S-+1S0

V
V
mW

"C
°C

II

DC ELECTRICAL CHARACTERISTICS
(T. =2SoC unless otherwise specified)
Characteristic

Symbol

Test Conditions

Min

Typ

2.S

Max

Unit
V

Supply Voltage

Vee

Key Contact Resistance

RKI

1

KP

Keyboard Capacitance

CKI

30

pF

Key Input Voltage

K'H
K'l

2 of 7 input
mode

'6.01

0.8Vee

Vee

Gnd

O.2Vce

V

Key Pull-Up Resistance

K,Au

Vcc =6.0V

100

KO

Key Pull-Down Resistance

K'AD

V'N=4.8V

4.0

KO

Mute Sink Current

1M

Vee=2.SV
Vo=O.SV

Pulse Output Sink Current

Ip

Vce=2.SV
Vo=O.SV

Tone Output Sink Current

Irl

Vec=2.SV
Vo=O.SV

Tone Output Source Current

IrH

Vce=2.SV
Vo=O.SV

Memory Retention Current
Operating Current

3

2S0

JA

4

.2S0

JA

All outputs under
no load

100
0.001

IAEF

Vec-VAEF=6.0V

4

-

..

. lop

VAEF Output Source Current
Note 1)
2)
3)
4)
S)
6)

mA

1.0

0.7

Vcc =6.0V
Vo=6.0V

1

2

IMA

IlKG .

1

p.A

SOO

All outputs under
no load

Mute or Pulse Off Lelikage

Notes

1.0

7.0

p.A
1S0
1.0

6

p.A

JA

2,3

mA

S

Applies to key input pin. (R,-R•• C,-C 3)
Applies to MUTE output in.
Applies to J50rsE output pin.
Applies to TONE pin (KSS80S8)
Applies to VAEF pin (KSS80SA)
Current necessary for memory to be maintailled. All outputs unloaded .

• Typical values l!.re to be used as a design aid are not subject to production testing.

131

KS5805AIKS5805B

CMOS INTEGRATED CIRCUIT

=

AC ELECTRICAL CHARACTERISTICS (Ta 25°C)
Charactistic

Symbol

1\'p

Min

Max

Unit

Notes

Oscilator Frequency

Fose

4

KHz

1

Key Input Debounce Time

Toe

10

ms

3,4

Key Down Time for Valid Entry

TKO

40

ms

4,5

Key Down Time During
Two-Key Roll Over

tKR

5

ms

4

Oscillator Stat-Up Time (Vee =2.5V)

tos

1

Mute Valid After Last Outpulse

tMO

5

ms

3,4

Pulse Output Pulse Rate

PR

10

PPS

2

On-Hook Time Required to
Clear Memory

IoH

ms

4

Pre-Digital Pause

Tpop

800

ms

3,4

Inter-Digital Pause

T,op

800

ms

3,4

Frequency Stability .
Vee=2.5-3.5V

Af

±4

%

Frequency Stability Vee =3.5 - 6.0V

Af

±4

olb

Tone Output Frequency

FlONE

1

KHz

Note: 1)
2)
3)
4)
5)
6)

300

ms

4,6

Rs=2MO, R=220KO, C=390pF.
If pin 10 is tied to Vee, the output pulse rate will be 20pps.
If the 20pps option is selected, the time will be 1/2 these shown.
These times are directly proportional to the oscillator frequency.
Debounce plus oscillator start-up time s 40ms.
If the 20pps option is selected, the tone output frequency will be 2KHz. (KS5805B ONLY)

. PIN CONNECTIONS·
Pin 1: Vee
Pin 2: Vref (KS5805A)/Pacifier tone (KS5805B)
Pin 3: Column 1
Pin 4: Column 2
Pin 5: Column 3
Pin6:GND
Pin 7: RC Oscillator
Pin 8: RC Oscillator
Pin 9: RC Oscillator

c8

SAMSUNG SEMICONDUCTOR

Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin

10:
11:
12:
13:
14:
15:
16:
17:
18:

10/20pps Select
Make/Break Select
Mute Output
ROW 4
ROW 3
ROW 2
ROW 1
On-Hook/Test
Pulse Output

132

CMOS INTEGRATED CIRCUIT

KS5805AIKS5805B
TIMING CHARACTERISTICS
Digit

Key Input

Digit

Redial

----~L2-Jr-----,~r-------------,~r--~--------------

Tone output

nnnn

-

Column scan

.-

(only KSS80SB)

. ---utrUlIUl- -soo'H;-----.IUl.J""LJlf -------:------uu----

Row scan

~-----------lIlfL..IlIl----------W-

o_n.HOOk input

~

MUTE output

_--l-!i---1!H!

r

1,

r

"'~.
PULSE output --I~-II-i!--~/
I
II'
I,

OSCoutput
(pin 8)

I
i
I

4KH

I I

~~l

II

Ii

II

---t ....... T08
I

i !I i

I

,I,
r+-H'fo------,
r---_,

I I

: I

~

I

I I

I

I:

II

1.r

1

I

.
I

'rin-----~*-- ______ L~+-~---------------------J.nr

110ms

On hook

r

n

I

TPDP 800ms

I

I

T8 1

TIOP

I!

I:

:

I

-t H- i ITMC':
--tl~rl I I

800ms
Normal dialing

l/PR

I ""

Off hook mode

I

:

I

II

Redial mode
Off hook mode

•

I

I
I

I

I.

:

I

I~
_

.

Test mode

Fig. 2

PIN DESCRIPTIONS
1. Vcc(Pin 1)
This is the positive supply pin. The voltage on this pin is measured relative to Pin 6 and is supplied from a 150pA current
source. This voltage muS! be regulated to less than 6.0 volts using on external form or regulation.

2. Tone signal outputNREF (Pin 2)
Tone signal out pin is CMOS comperementaly output and drive on external bipolar transistor. This pin generates a tone
signal when a key is depressed as its recognition. Tone signal frequency is 1KHz when 10pps pulse rate is selected. (the
frequency is 2KHz when 20pps pulse rate is selected). Only the pin 2 of KS5605A is VREF (on-chip reference voltage).

TYPICAL I-V CHARACTERISTICS
The VREF output provides a reference voltage that tracks internal
parameters of the KS5805A. VREF provides a negative voltage reference
to the Vee supply. Its magnitude will be approximately 0.6 volt greater
than the minimum operating voltage of each particular KS5805A

7.0
6.0
S.O

The typical application would be to connect the V REF pin to theGND pin
(Pin 6). The supply to the Vee pin (Pin 1) should then be regulated to
150pA (lop max). With this amount of supply current, operation of the
KS5805A is guaranteed.

IREF

MA

4.0
3.0

The internal circuit of the VREF function. is shown in Figure 3 with its
associated I-V characteristic.

2.0
VREF

1.0

vee

c8

1.0
-VREF

2.0

3.0

4.0
5.0
VOLTS

SAMSUNG SEMICONDUCTOR

Fig. 3

133

CMOS INTEGRATED CIRCUIT

KS5805A1KS5805B
3. Keyboard inputs (Pin 3, 4, 5, 13, 14, 15, 16,)

The KS5805AIB incorporates an innovative keyboard scheme that allows either the standard 2-of-7 keyboard with negative common or the inexpensive single contact (form A) keyboard to be used.
A valied key entry is defined by either a Single row being connected to a single column or GND being sjmutaneously
presented to both a Single row and column. When in the on-hook mode, the row and column inputs are held high and no
keyboard inputs are accepted.
When off-hook, the keyboard is completely static until the initial valid key input is sense<;l. The oscillator is,then enabled
and the rows and columns are alternateiy scanned (pulled high, then low) to verify the input is varied. The input must remain
valid continuously for 10msec of debounce time to be accepted .
• Form A type keyboard

• 2 of 7 keyboard (negative common)

------------~

COL

-.~----------

ROW '

G~'-----_______'·1.
~

COL

---------------ROW

• 2 of 7 keyboard

. - - - - - ".±~

COL

L-_______----A

••

~

• Electronic input

vcc

'H

- _.:.__-,-_-_-_..,_u

~-~-~-----.

____________
ROW

.vc_c____________,

~!?------------U

KEY BOARD CONFIGURATIONS

4. GND (Pin 6)

This is the negative supply pin and is connected to the common part in the general applications.

5. OSCILLATOR (Pins 7, 8, 9)
The KS5805AIB contains on-chip inverters to provide an oscillator which will operate with a minimum of external components.
FollOWing figure shOWS the on-Chip configuration with the necessary external components. Optimum stability occurs with
the ratio K=RsIR equal to 10.
'
The oscillator period is given by;
T=RC (1.386+(3.5KCs)IC-(±KI(K+1» In (K1(1.5K+0.5»
Where Cs is the stray capacitance on Pin 7.
Accuracy and stability will be enhanced with this capacitance minimized.

RS

+---U--------.-.1 8
C

KS5805 AlB

,R

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SAMSUNG SEMICONDUCTOR
,

I

134

KS5805AIKS5805B

CMOS INTEGRATED CIRCUIT

6. 20/10 pps (Pin 10)
Connecting this pin to GND (pin 6) will select an output pulse rate of 10pps.
Connecting the pin Vee (pin 1) will select an output pulse rate of 20pps.

7. MAKE/I;IREAK (Pin 11)
The MAKE/BREAK pin controls the MAKE/BREAK ratio of the pulse output. The MAKE/BREAK ratio is controlled by con·
necting Vee or GND to this pin as shown in the following table.

Input

Make

Break

vee (Pin 1)

34%

66%

(Pin 6)

40%

60%

GND

II

8. MUTE OUTPUT (Pin 12)
The mute oiJtput is an open-drain N-channel transistor designed to drive an external bipolar transistor.
This circuitry is usually used mute the receiver during outpulsing. As shown in Fig. 2 the KS5805 mute output turns on
(pulls to the VGNo-supply) at the beginning of the predigital pause and turns off (goes to an open circuit) following the last
break.
The delay from the end of the last break until the mute output turns off is mute overlap and is specified as tMO.

9. ON-HOOKITEST (Pin 17)
The "ON-HOOK" or "Test" input of the KS580SA/B has a 100K{J pull~up to the positive supply. A Vee input or allowing the
pin to float sets the circuit in its on-hook or test mode while a VGND input sets it in the off-hook or normal mode. When off-hook
the KS5805AIB will accept key inputs and outputs the digits in normal fashion .. Upon completion of the last digit, the oscillator
is disabled and the circuit stands by for additional inputs.
Switching the KS5805AIB to on-hook while it is outpulsing causes the remaining digits to be outpulsed at 100x the normal rate (M/B ratio is then 50/50).
.
This feature provides a means of rapidly testing the device and is also on efficient method by which the circuitry is reset.
When the outpulsing in this mode, which can take up to 300msec, is completed, the circuit is deactivated and will require
only the current necessary to sustain the memory and power-up-clear detect ·ci.rcuitry (refer to the electrical specifications).
Upon retuning off-hook, a negative transistion on the mute output will insure the speech network is connected to the line.
If the first key entry is either a • or #, the number sequence stored on-Chip will be outpulsed. Any other valid key entrieS will
clear the memory and outpulse the new number sequence.

10. PULSE OUTPUT (Pin 18)
The pulse output is an open drain N-channel transistor designed to drive on external bipolar transistor. These transistor
would normally be used to pulse the telephone line by disconnecting and connecting the network. The KS5805AIB pulse
output is an open circuit during make and pulls to the GND supply during break.

c8

SAMSUNG SEMICONDUCTOR

135

KS5806(DELETION)

. CMOS INTEGRATED CIRCUIT

TEN NUMBER REPERTORY DIALER
WITH PACIFIER TONE

18 DIP

The KS5806 is a monolithic integrated ten-number repertory dialer
manufactured using CMOS process. The circuit aCcepts keyboard inputs
and provides the pulse and mute logic levels required for loop disconnect signaling.

FEATURES
o Low-voltage (2
o

to 1OV) and low power operation

Low memory retention currant of 1II.

o Auto-dlals Ten 16 digit-numbers Including Last Number Dialed
o

o
o

o
o

o
o
o
o
o

(LND)
Pacifier Tone Output
Osclllstor Selectable In pulse mode (RC or ceramic resonator)
Stand-alone pulse dialer
PABX pause key Input
Last number dialed memory
Last number dialed may be copied Into any one of nine other
locations.
MakelBreak ratio Is pin selectabls in pulse mode
Uses slther the Inexpensive Form-A type keyboard or the stan.
dard 2·of·7 matrix keyboard with common Gnd
Optional use of 13th key Input to control repertory functions in
tone mode
/
Power up circuit Initializes RAM and logic
i

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SAMSUNG SEMICONDUCTOR

136

CMOS "INTEGRATED CIRCUIT

KS5806 (DELETION)
BLOCK DIAGRAM

vee

18 J5UiM!113 KEY
STATIC
CMOS
RAM

DIGITDEMUX

}---------------~10r_--------~

HKS

GND

PACIFIER
TONE

DESCRIPTION
The KS580S is a ten-number repertory dialer manufactured using silicon Gate CMOS process. Pin 2, the "Mode select"
input determines whether "signaling will be pulse or tone. The interpretation of several inputs and outputs is dependent upon
the mOde selected.
.
In the pulse mode the time base for the circuit is selectable between a ceramic resonator and RC oscillator. In tone mode
the circuit can· only use the RC oscillator. An on chip RAM is capable of storing ten 1S-digit telephone numbers including
the laSt number dialed.
When used in a PABX system, a pause (# key) may be stored in the number sequence. The repertory dialer will recognize
this pause when automatically dialing and stop until another key input is received.

ciS

SAMSUNG SEMICONDUCTOR

137

II

KS5806 (DELETION)

'CMOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)
Caracteristic
DC Supply Voltage
Maximum Power Dissipation (25°C)
Maximum Voltage on Any Pin
Operating Temperature
Storage Temperatu're

Symbol

Unit

value
10.5
500
Vee-l;O.3, GND-0.3
-30-60
-55-125

Vee
Po
Y,N
Topr

Tstg

.

V
mW
V
°C
°C

DC ELECTRICAL CHARACTERISTICS
(Ta =25°C)
Characteristic

Symbol

Test Conditions

Min

Typ

Max

Units

Supply Voltage'

Vee

10.0

'V

Operating Current (Tone)2

lop

Vee=2.5V

50

100

pA

Operating Current (Pulse)2

lop

Vee=2.5V

100

200

pA

Standby Current (Vee =2,5V)3

ISB

No load

1.0

2.0

pA

Memory Retention Current'

1.0

pA.

2.0

IMR

0.3

Memory Retention Voltage'

VMR

1.3

1.5

V

Mute Sink CUffent'

IML

0.5

2.0

mA
mA

Vee=2.5V, Vo=0.5V

Pulse Sink Current'

Ip

Vee=2.5V, Vo=0.5V

1.0

4.0

Pacifier Tone Source/Sink'

IPT

Source Vo =2.OV

200

500

Mute and Pulse leakageS

ILKG

Vo=10V

0.001

pA
1.0

pA.

Key Contact Resistance6

RKI

1.0

KG

Keyboard Capacitance 6

CKI

30

pF

"0" LOgic Level

K,L '

GND

0.2Vee

V

"I" Logic Level

K'H

0.8 Vee

Vee

Keyboard Pull Up7

KRu

Keyboard Pull Down 7

KRo

CNT Pull Up (Pin 11)8

ReNT

Tone mode only

V

100

KG

1.0

KG

100

KG

Notes:
1. The memory will be retained at a lower voltage level than that required for circuit operation. If either IMR or VMR is
maintained the memory contents will not be cleared.
2. Operating current with a valid key input at 2.5 volts.
3 .. Standby current on hook or off hook with all inputs unloaded.
4. For V+ =2.5, Sink Vo =0.5 Volts, Source Vo =2.0 volts.
5. Leakage with V+, Vo=10.0 Volts
6. Keyb9ard contact resistance and parasitic capacitance, maximum values.,
. _ .
7. Keyboard 110 pins will scan 250 Hz with oscillator enabled pulse mode and dunng DD I"'tone mode.
8. Tone mode only.

c8

SAMSUNG SEMICONDUCTOR

138

KS5806 (DELETION)

CMOS INTEGRATED CIRCUIT

AC ELECTRICAL CHARACTERISTICS (Ta=25°C)
Characteristic

Symbol

Min

Typ

Oscillator (Cer, Res)'

FCR

480

Oscillator (RC)2

FRe

8

Oscillator Stability"

tlFRc

Debounce Time4

Toe

Valid Key Down Time
Oscillator Start

-3

Unit

16

KHz

KHz

+3

%
mS

32
40

TKO

Up Time

Max

mS
8

Tos

mS

Key Rollover OVLP Time 5

TRoL

Pulse Rate

PR

10

Break Time (Pin 11 VedGND)

Te

60/68

mS

Predigital Pause Times

Tpop

170

mS

Mute Overlap Time

TMoL

2

mS

Tone Rate

TR

5

TPS
mS

4

mS
PPS

Pacifier ToneBurst Time7

TPT

28

Pacifier Tone Frequency·

FPT

500

Hz

Interdigital Pause Time

T,op

940

mS

Notes:
1. Ceramic Resonator should 'have the tOtlowing equivalent values: R<20 Ohms. RA >70k Ohms, Co < 500pF.
2. The RC values chosen determine frequency. The nominal frequency is 8kHz. To accelerate dialing the frequency may
be increased to twice the nominal value. This would double signalling rate and half most timing specifications.
3. Voltage range of 2.5 to 6.0 volts, over temperature, and unit to unit variations.
4. Key entry must be present after 32 ms to be valid.
5. Rollover is the time key inputs must be invalid for successive entries to be recognized.
6. Time from initial key input till first break or tone output.
7. Tone burst will terminate if key released before 28 ms.
8. This is a square wave output.

PIN CONNECTION
vee - -

1

- '-

MOOE--.

2

--HKS

COL1--

3

Ccii2'--

4

COi:3--

5

PUL5E113KEY

--R0W2
KS5800

--R0W3

--i'IOWI
OSC/RC--

7
11

- - MB/CNTI.

OSC
SELECT - -

c8

9

SAMSUNG SEMICONDUCTOR

- - PACIFIER lONE

139

CMOS INTEGRATED CIRCUIT

KS5806 (DELETION)
PIN DESCRIPTION
1.

VccCPln 1)

Pin 1 is the positive supply input to the part and is measured relative to GND (pin 6). The voltage on this pin should not
el«:eed 10 VoIIS. On chip Zener diodes will provide protection from supply transients In most applications. Alow voltage detect
circuit will perform a power up initialization whenever the supply voltage at thi!; pin falls below a level necessary to guarantee
proper circuit operation.

2. Mode (Pin 2)
The KS5806will function In either tone or pulse mode, dependent upon the logic level presented to pin 2. For pulse mode
operation, this pin must be tied to GND (pin 6). For tone mode, it should be tied to Vee (pin 1). The interpretation of pins
7,8;11,12, and 18 are dependent upon the mode selected.

3. Keyboard Inputs (Pins 3, 4, 5, 13, 14,

15; 16)

The KS5806 incorporates a keyboard scheme that allows either the standard 2-of-7 keyboard with negative common or
'
the inexpensive single-contact (Form A) keyboard to be used, as shown in Fig. 1.
A valid key entry is defined by either a single row being connected to single column or V - being simultaneously presented
to both a single row and column.
In the tone mode, the KS5806 features a bidirectional keyboard scheme. As the KS5806 passively monitors the key inputs
, (using the scan provided by the tone dialer), they are debounced, decoded, and stored in the on chip LND (last Number
Dialed) buffer. The keyboard inputs in tone mode are normally high impedance allowing the tone chip to scan the keyboard
lines and begin signaling immediately upon detecting a key entry. A command key entry disables the tone chip and scanning
is then controlled by the repertory dialer until the key is released. In tone mode auto- -10p.A

4.1
Voc·O.1

10H = - 400p.A

4.1

10H:!> -10p.A

Vee·0.1

IOH=1.6mA

-

0.8'

V

2.5

p.A

10

p.A

-

V

0.4

V

181

I

CMOS INTERGRATED CIRCUIT

KS5824
DC CHARACTERISTICS (Continued)
Characteristic
Output leakage
(Off State)

Cur~ent

C~nditlons

Symbol

Test

ILOH

VOH=VCC

CIN

VIN=OV, Ta=25°C,
f=1.0MHz

COUT

V,N =OV:Ta=25°C
f=1.0MHz

IRQ

Input Capacitance

Output Capacitance

RTS, Tx

Dat~

iRa

-

10

-

12.5

-

-

7.5

-

E= 1.0MHz

-

E= 1.5MHz
E=2.0MHz

E=1.0MHz

• Under transmitting and
receiving operation
• 500 kbps
• Data bus in Rm operation
Supply Current

E=1.5MHz
E=2.0MHz

• Chip is not selected
.500 kbps
• Under non transmitting
and receiving operation
• Input level (Except E)
VIH min = Vcc - 0.8V
VIL max = 0.8V

Icc

Typ Max Unit

,-

0 0 -0 7
E, Tx ClK, Rx ClK,
Rm, RS, Rx Data, CSo,
CS" CS2, CTS, DCD

Min

10
5.0

pA

pF

pF

3
4

-

5

-

200

-

-

250

-

-

300

mA

p.A

AC CHARACTERISTICS (Vcc=5.0V±5%,Vss =OV, Ta= -20-+75°C, unless otherwise noted.)
1. TIMING OF DATA TRANSMISSION
Characteristic

Symbol

Test Conditions

PWCL

Fig. 1

+1 Mode
Minimum Clock Pulse Width
,

+16, +64 Modes
+1 Mode
+16, +64 Modes

Clock Frequency

+1 Mode
+ 16, + 64 Modes

Min
,900

PWCH

Fig. 2

fc

600
900
600

ns
ns
ns
ns
KHz

800

KHz

-

600

ns

-

ns

1200

ns

trOD

Receive Data Setup Time

+1 Mode

tRoSU

Fig. 4

250

Receive Data Hold Time

+1 Mode

tRoH

Fig. 5

250

IRQ Release Time

tlR

Fig. 6

i1fS Delay Time

tRTS

Fig. 6

-

t" tl

500

Fig. 3

Except E

Unit

-

Clock-to-Data Delay for Transmitter

Rise Time and Fall Time

Max

ns

560

ns

1000'

ns

• 1.0p.s or 1Q% of the pulse width, whichever is smaller.

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SAMSUNG SEMICONDUCTOR

182

KS5824

CMOS INTERGRATED CIRCUIT

2. BUS TIMING CHARACTERISTICS
1) READ
Characteristic

Symbol

Test Conditions

Min

Max

Unit

-

ns

Enable Cycle Time

teycE

Fig. 7

Enable :'High" Pulse Width

PweH

Fig. 7

1000
450

Enable "Low" Pulse Width

PWEL

Fig. 7

430

Setup Time, Address and 'Rm Valid
to Enable Positive Transition

tAS

Fig. 7

80

ns
ns
ns

I

Data Delay Time

tOOR

Fig. 7

-

tli

Fig. 7

20

290
100

ns

Data Hold Time
Address Hold Time

tAH

Fig. 7

10

-

ns

te" te,

Fig. 7

-

25

ns

Symbol

Test Conditions

Min

Max

Unit

·Enable Cycle Time

teyeE

Fig. 8

1000

PWEH

Fig. 8

-

ns

Enable "High" Pulse Width
Enable "Low" Pulse Width

""""'

ns
ns

ns

Rise and Fall Time for Enable Input

ns

2) WRITE

Characteristic

PWEL

Fig. 8

450
430

Setup Time, Address and RIW
Valid to Enable Positive Transition

tAS

Fig. 8

80

Data Setup Time

tosw

Fig. 8

165

Data Hold Time

tH

Fig. 8

tAH

Fig. 8

10
10

-

tE" te,

Fig. 8

-

25

Address Hold Time
Rise and Fall Time for Enable Input

PWCL

Tx ClK
OA
Ax ClK

Tx elK
OA
Ax ClK

ns

ns
ns
ns

2.2V

o.sv
PWCH

• Tx elK Is V'H=2.0V

Fig. 1 Clock Pulse Width, "Low" State

Fig. 2 Clock Pulse Width, "High" State

Tx elK
Ax DATA

Vcc-2.0V
O.4V

Fig. 3 Transmit Data Output Delay

c8

SAMSUNG SEMICONDUCTOR

Ax elK _ _ _-'I

Fig. 4 Receive Data Setup Time (+ 1 Mode)

183

·KS5824

CMOS INTERGRATED CIRCUIT

ENABLE

Rx ClK

Vcc- 2.OV
O.4V

.

i----tcycE----I

ENABLE

RS.CS.RIW

-FV;;

iRCl _ _ _ _ _ _ _ _ _ _ _ _~/:...2.0V

Fig. 5 Receive Data Hold Time ( ... 1 Mode)

•. (1) i'RCi Release Time applied to Rx Data Register
read operation.
(2) IRQ Release Time applied to Tx Data Register
write ope~ation
(3) IRQ Release Time applied to control Register
write TIl: = 0, RIE = 0 operation.
•• IRQ Release Time applied to Rx Data Register
read operation right after read status register,
when IRQ is asserted by DCD rising edge.
Note: Note that following take place when IRQ is
asserted by the detection of transmit data register
empty status. IRQ is released to "High"
asynchronously with E signal when CTS goes
"High". (Refer to Figure 14)

DATA BUS

Fig. 6

Fig. 7 Bus Read Timing Characteristics
(Read information from UARn

lOAD A
(00-07.

f----tcycE - - - - - I
PWEH

m

Delay and

i1m

Release Time

(~~=1\Y)'5.0V

RiS. Tx DATA)
RL

=2.4KIl

3KIl

TEST POINT
TEST POINT

c

c= 130pF for 00-07
= 30pF for FITS and.IlLData
R 10KIl for 00-07. RTS and Tx Data
All diodes are lS2074@or Equivalent.

r"

=

Fig. 8 Bus Write Timing Characteristics
(Write information into UARn

c8SAMSUNG SEMICONDUCTOR

Fig. 9 Bus Timing Test Loads

184

KS5824

CMOS INTERGRATED CIRCUIT

START BIT

DO

01

02

f----------

03

04

05

06

PARITY
BIT

STOP
BIT

STOP
BIT

II

CHARACTER TIME @10CPS (11 BITS) 1 0 0 m s e c - - - - - - - - - - - i

Fig. 10 110 Baud Serial ASCII Data Timing

TRANSMIT
CLOCK 4
ENABLE 14

READIWRITE
CHIP SELECT 0
CHIP SELECT 1
CHIP SELECT 2

13
8
10
9

REGISTER SELECT 11-

CHIP
SELECT
AND
READI
WRITE
CONTROL

TRANSMIT
DATA
REGISTER

6 TRANSMIT
DATA

·24 CLEAR
TO SEND

DO

22

01

21

02

20

03

19

04

18

05

17

06

16

07

15

STATUS
REGISTER
7 INTERRUPT
REQUEST

DATA BUS
BUFFERS

23 DATA
CARRIER
DETECT
5 REQUEST
TO SEND
. CONTROL
REGISTER

RECEIVE·
DATA
REGISTER

Vcc=Pin 12
Vss=Pin 1

RECEIVE
CLOCK 3

RECEIVE
SHIFT
REGISTER

1------+-- 2 ~!~!IVE

-------------------t....::.~.:...J
Fig. 11 Expanded Block Diagram

c8

,

SAM$UNG SEMICONDUCTOR

185

KS5824

CMOS INTERGRATED CIRCUIT

DEVICE OPERATION

transmitted (because of double buffering). The second
character will be automatically transferred into the Shift
Register when ·the first character transmission is
completed. This sequence continues until all the
characters have been transmitted.

At the bus interfl[lCe, the UART appears as two
addressable memory locations. Internally, there are four
registers: two read-only and two write-only registers. The
read-only registers are Status and Receive Data; the
write-only registers are Control and Transmit Data. The
serial interface consists of serial input and output lines
with independent clocks, and three peripheral/modem
control lines.

POWER ON/MASTER RESET
The master reset (CRO, CR1) should be set during
system initialization to insure the reset condition and
prepare for' programming the UART functional configuration when the communications channel is required.
During the first master reset, the IRQ and RTS outputs
are held at level 1. On all other master resets, the RTS
output can be programmed high or low with the IRQ
output held high. Control bits CR5 and CR6 should also
be programmed to define the state of RTS whenever
master reset is utilized. The UARTalso cQntains internal
power-on reset logic to detect the power line turn-on
transition and hold the chip in a reset state to prevent
'erroneous output transitions prior to initialization. This
circuitry depends on clean power turn-on tranSitions.
The power-on reset is released by means of the busprogrammed master reset which must be applied prior
to operating the UART. After master resetting the UART,
the programmable Control Register can be set for a
number of options such as variable clock divider ratios,
variable word length, one or two stop bits, parity (even,
odd, or none), etc.

TRANSMIT
A typical transmitting sequence consists of reading
the UART. Status Register either as a result of an
interrupt or in the UART's turn in a polling sequence.
A character may be written into the Transmit Data
Register if the status read operation has indicated that
the Transmit Data Register is empty. This character is
transferred to a Shift Register where it is serialized and
transmitted from the Transmit Data output preceded by
a start bit. and followed by one or two stop bits. Intemal
parity (odd or even) can be optionally added to the
character and will occur between the last data bit and
the first stop bit. After the first character is written in
the Data Register, the Status Register can be read again
to check for a Transmit Data Register Empty condition
and current peripheral status. If the register is empty,
another character can be loaded for transmission even
though the first character is in the process of being

c8

SAMSUNG SEMICONDUCTOR'

RECEIVE
Data is received from a peripheral by means of the
Receive Data input. A divide-by-one clock ratio is
provided for an extemally synchronized clock (to its data)
while the divid-by-16 and 64 ratios are provided for
internal synchronization. Bit synchronization in the
divide-by-16 and 64 modes is initiated by the detection
of B or 32 low samples on the receive .Iine in the divideby-16 and 64 modes respectively. False start bit deletion
capability insures that a full half bit of a start bit has
been received before the internal clock is synchronized
to the bit time. As a character is being received, parity
(odd or even) will be checked and the error indication
will be available in the Status Register along with
framing error, overrun error, and Receive Data Register
full. In a typical receiving sequence, the Status Register
is read to determine if a character has been received
from a peripheral. If the Receiver Data Register is full,
the character is placed on the B-bit UART bus when a
Read Data command is received from the MPU. When
parity has been selected for a 7-bit word (7 bits plus
parity), the receiver strips the parity bit (07 0) so that"
data alone ia transferred to the MPU. This feature
reduces MPU programming. The Status Register can
continue to be read to determine when another
character is available in the Receive Data Register. The
receiver is also double buffered so that a character can
be read from 'the data register as another character is
being received in the shift register. The above sequence
continues u'ntil all characters have been received.

=

INPUT/OUTPUT FUNCTIONS
UART INTERFACE SIGNALS FOR MPU
The KS5B24 interfaces to the MPU with an B-bit
bidirectional data bus, three chip select lines, a register
select line, an interrupt request line, read/write line, and
enable line. These signals permit the MPU to have
complete control over the KS5824.
UART Bidirectional Data (00-07) - The bidirectional
data lines (00-07) allow for data transfer between the
KS5B24 and the MPU. The data bus output drivers are
three-state devices that remain in the high-impedance
(off) state except wh~n the MPU performs an UART read
operation.

.186

KS5824

CMOS INTERGRATED CIRCUIT

UART Enable (E) - The Enable signal, E, is a highimpedance TTL-compatible input that enables the bus
input/output data buffers and clocks data to and from
the KS5824.

reading data or resetting the UART. Interrupts caused
by Overrun or loss of DCD are cleared by reading the
status register after the error condition has occurred and
then reading the Receive Data Register or resetting the
UART. The receiver interrupt is masked by resetting the
Receiver Interrupt Enable.

ReadlWrite (R/W) - The ReadlWrite line is a highimpedance input that is TTL compatible and is used to
control the direction of data flow through the UART's
input/output data bus interface. When ReadlWrite is high
(MPU Read cycle), KS5824 output drivers are tumed on
and a selected register is read. When it is low, the
KS5824 output drivers are turned off and the MPU writes
into a selected register. Therefore, the ReadlWrite signal
is used to select read-only or write-only registers within
the KS5824.
Chip Select (CSO, CS1, CS2) - These three highimpedance TTL-compatible input lines are used to
address the KS5824. The KS5824 is selected when CSO
and CS1 are high and CS2 is low. Transfers of ,data to
and from the KS5824, are then performed under the
, control of the Enable Signal, ReadlWrite, and Register
Select.
Register Select (RS) - The Register Select line is a
high-impedance input that is TTL compatible. A high
level is used to select the Transmit/Receive Data
Registers and a low level the Control/Status Registers.
The ReadlWrite signal line is used in conjunction with
Register Select to select the read-only or write-only
register in each register pair.
Interrupt Request (IRQ) - Interrupt Request is a TTLcompatible, open-drain (no internal pull up), active low
output that is used to interrupt the MPU. The IRQ output
remains low as long as the cause of the interrupt is
present and the appropriate interrupt enable within the
UART is set. The IRQ status bit, when high, indicates
the IRQ output is in the active state.
Interrupts result from conditions in both the
transmitter and receiver sections of the UART. The
transmitter section causes an interrupt when the
Transmitter Interrupt Enabled condition is selected
(CR5 o CR6), and the Transmit Data Register Empty
(TORE) status bit is high. The TORE status bit indicates
the current status of the Transmitter Data Register
except when inhibited by Clear-to-Send (CTS) being high
or the UART being maintained in the Reset condition.
The interrupt is cleared by writing data into the Transmit
Data Register. The interrupt is masked by disabling the
Transmitter Interrupt via CR5 or CR6 or by the loss of
CTS which inhibits the TORE status bit. The Receiver
section causes an interrupt when the Receiver Interrupt
, Enable is set and the Receive Data Register Full (RDRF)'
status bit is high, an Overrun has occurred, or Data
Carrier Detect (DCD) has gone high. An interrupt
resulting from the RDRF status bit can be cleared by

c8

SAMSUNG SEMICONDUCTOR

CLOCK INPUTS
Separate high-impedance TTL-compatible inputs are
provided for clocking of transmitted and received data.
Ciock frequencies of 1, 16, or 64 times the data rate may
be selected.
Transmit Clock (Tx ClK) -The Transmit Clock input
is used for the clocking of transmitted data. The
transmitter initiates data on the negative transition of
the clock.
Receive Clock (Rx ClK) - The Receive Clock input
is used for synchronization of received data (In the + 1
mode, the clock and data must be synchronized
extemally.) The receiver samples the data on the positive
trans,ition of the clock.

SERIAL INPUT/OUTPUT LINES
Receive Data (Rx Data) - The Receive Data line is
a high-impedance TTL-compatible input through which
data is received in a serial format. Synchronization with
a clock for detection of data Is accompiished internally
when clock rates of 16 or 64 times the bit rate are used.
Transmit Data (Tx Data) - The Transmit Data output
line transfers serial data to a modem or other peripheral.

PERIPHERAUMODEM CONTROL
The UART includes several functions that permit
limited control of a peripheral or modem. The functions
included are Clear-to-Send, Request-to-Send and Data
Carrier Detect.
Clear-ta-Sand (CTS) - This high-impedance TTLcompatible input provides automatic control of the
transmitting end of a communications link via the
modem Clear-to-Send active low output by inhibiting the
Transmit Data Register Empty (TORE) status bit.
Request:to-Sand (RTS) - The Request-to-Send output
enables the MPU to control a peripheral or modem via
the data bus. The FITS; output corresponds to the state
of the Control Register bits CR5 and CR6. When CR6 = 0
or both CR5 and CR6 1, the RTS output is low (the
active state). This output can also be used for Data
Terminal Ready (DTR).

=

187

II

KS5824

CMOS INTERGRATED CIRCUIT

Data Carrier Detect (!)CO) - This high-impedance
TIl-compatible input provides automatic control, such
as in the receiving end of a communications link by
means of a m9dem Data Carrier Detect output. The DCD '
input rnhibits and initializes the receiver section of the
UART when high. A low-to-high transition of the Data
Carrier Detect initiates an interrupt to the MPU to
indicate the occurrence of a loss of carrier when the
Receive Interrupt Enable bit is set. The Rx ClK must
be running for proper DCD operation.

character is being transmitted, then the transfer will take
place within 1-bit time of the training edge of the Write
command. If a character is being transmitted, the new
data character will commence as soon as the previous
character is complete. The transfer of data causes the
Transmit Data Register Empty (TORE) bit to indicate
empty.

RECEIVE DATA REGISTER (RDR)
Data is automatically transferred to the empty Receive
'Data Register (RDR) from the receiver deserializer (a
shift register) upon receiving a complete character. This
event causes the Receive Data Register Full bit (RDJ:lF)
in the status buffer to go high (full). Data may then be
read through the bus by addressing the UART and
selecting the Receive Data Register with RS and RIW
high when the UART is enabled. The non-destructive
read cycle causes the RDRF bit to be cleared to empty
although the data is retained in the RDA. The status is
maintained by RDRF as to whether or not the data is
current. When the Receive Data, Register is full, the '
automatic transfer of data from the Receiver Shift
Register to the Data Register is inhibited and the RDR
contents remain valid with its current status stored in
the Status Register.

UART REGISTERS
The expanded block diagram for the UART indicateS
the Internal registers on the chip that are used for the
status, control, receiving, and'transmitting of data ThEi
content of each of the registers is summarized in Table

1.

TRANSMIT DATA REGISTER (TOR)
Data is written in the Transmit Data Register during
the negative transition of the enable (E) when the UART
has been addressed with RS high and RiW low. Writing
data into the register caul$es the Transmit Data Register
Empty bit in the Status Register to go low. Data can then
I:;le transmitted. If the transmitter is idling and no

DEFINITION OF UART REGISTER CONTENTS
Buffer Address
RS. RiW
Transmit
Data
Register

RS. RIW
Receive
Data
Register

(Write Only)

0

Data
Bus
Line
Number

RS.

iWi

RS.

RiW

Control
Register

Status
Register

(Read Only)

(Write Only)

(Read Only)

Data Bit 0'

Data Bit 0

Counter Divide
Select ,1 (CR1)

Receive Data Register
Full (RDRF)

1

Data Bit 1

Data Bit 1

Counter Divide
Select 2 (CR1)

Transmit Data Register
Empty (TORE)

2

Data Bit 2

Data Bit 2

Word Select 1
(CR2)

Data Carrier Detect
(DCD)

3

Data Bit 3

Data Bit 3,

Word Select 2
(CR3)

Clear-to-Send
(CTS)

4

Data Bit 4

Data Bit 4

Word Select 3
(CR4)

Framing Error
(FE)

5

Data Bit 5

Data Bit 5

Transmit Control 1
(CR5)

Receiver Overrun
(OVRN)

6

Data Bit 6

Data

Bit 6

Transmit Control 2
(CR6)

Parity Error (PE)

7

Data Bit 7'"

Receive Interrupt
Enable (CR7)

Interrupt Request
(IRQ)

Data Bit 7"

• leadmg bit = lSB = Bit 0
" Data bit will be zero in 7 bit plus parity modes
, •• Data bit is "don't care" in 7 bit plus parity modes.

c8

SAMSUNG SEMICONDUCTOR

188

KS5824

CMOS INTERGRATED CIRCUIT

CONTROL REGISTER
The UART Control Register consists of eight bits of
write-only buffer that are selected when RS and R/W are
low. This register controls the function of the receiver,
transmitter, interrupt enables, and the Request-to-Send
peripheral/modem control output.
Counter Divide Select Bits (CRG and CR1) - The
Counter Divide Select Bits (CRO and CR1) determine the
divide ratios utilized in both the transmitter and receiver
sections of the UART. Additionally, these bits are used
to provide a master reset for the UART which clears the
Status Register (except for external conditions on CTS
and DC D) and initializes both the receiver and
transmitter. Master reset does not affect other Control
Register bits. Note that after power-on or a power
fail/restart, these bits must be set high to reset the
UART. After resetting, the clock divide ratio may be
selected. These counter select bits provide for the
follo~ing clock divide ratios:
CR1

CRO

Function

0
0
1
1

0
1
0
1

+1
+16
+64
Master Reset

Word Select Bits (CR2, CR3, and CR4) - The Word
Select bits are used to select word length, parity, and
the number of stop bits. The encoding format is as
follows;
Function

CR4 CR3 CR2

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

7
7
7
7
8
8
8
8

Bits + Even Parity + 2 Stop Bits
Bits + Odd Parity + 2 Stop Bits
Bits + Even Parity + 1 Stop Bit
Bits Odd Parity +1 Stop Bit
Bits + 2 Stop Bits
Bits + 1 Stop Bit
Bits + Even Parity + 1 Stop Bit
Bits + Odd Parity + 1 Stop Bit·

+.

Word length, Parity Select, and Stop Bit changes are
not buffered and therefore become effective
immediately.
Transmitter Control Bits (CRS and CR6) - Two
Transmitter Control bits provide for the control of the
interrupt from the Transmit Data Register Empty
condition, the Request-to-Send (RTS) output, and the·
transmission of a Break level (space). The following
encoding format is used: .

c8

SAMSUNG SEMICONDUCTOR

CR6

CRS

0

0

0

1

1

0

1

1

Function

=
=
=
=

RTS low, Transmitting interrupt
Disabled.
RTS low, Transmitting Interrupt
Enabled.
RTS high, Transmitting Interrupt
Disabled.
RTS low, Transmits Break level on
the Transmit Data Output.
Transmitting Interrupt Disabled.

Receive Interrupt Enable Bit (CR7) - The following
interrupts will be enabled by a high level in bit position
7 of the Control Register (CR?): Receive Data Register
Full Overrun or a low·to-high transition on the Data
Carrier Detect (DCD) signal line.

STATUS REGISTER
Information on the status of the UART is available to
the MPU by reading the UART Status Register. This readonly register is selected when RS is low and RiW
is high. Information stored in this register indicates the
status of the Transmit Data Register, the Receive Data
Register and error logic, and the peripheral/modem
status inputs of the UART.
Receive Data Register Full (RDRF), Bit 0 - Receive
Data Register Full indicates that received data has been
transferred to the Receive Data Register. RDRF is
cleared after an MPU read of the Receive Data. Register
or by a master reset. The cleared or empty state
indicates that the contents of the Receive Data Register
are not current. Data Carrier Detect being high also
causes RDRF to indicate empty.
Transmit Qata Register Empty (TORE), Bit 1 - The
Transmit Data Register Empty bit being set high
indicates that the Transmit Data Register contents have
been transferred and that new data may be entered. The
low state indicates that the register is full and that
transmission of a new character has not begun since
the last write data command.
Data Carrler'Detect (DCD), Bit 2 - The Data Carrier
Detect bit will be high when the DCD input from a
modem has gone high to indicate that a carrier is not
present. This bit going high causes and Interrupt
Request to be generated when the Reoeive Interrupt
Enable is set. It remains high after the DCD input is
returned low until cleared by first reading the Status
Register and then the Data Register or until a master
reset occurs. If the DCD input remains high after read

189

II

<

KS5824

CMOS INTERGRATED CIRCUIT

status and read data or master reset has occurred, the
interrupt is cleared, the DCD status bit remains high and
will follow the DCD Input.

in succession without a read of the RDR having
occurred. The Overrun does not occur in the Status
Register until the valid character prior to Overrun has
been read. The RDRF bit remains set until the Overrun
is reset. Character synchronization is mai~tained during
the Overrun condition. The Overrun indication is reset
after the reading of data from the Receive Data Register
or by a Master Reset.

Clear·to-5end"(CTS), Bit 3 - The Clear·to-Send bit
indicates the state of the Clear·to-Send input from a
modem. A low CfS indicates that there is a Clear·toSend from the mod~m. In the high state, the Transmit
Qata Register Empty bit Is inhibited and the Clear·toSend status bit will be high. Master reset does not affect
the Clear·to-Send status bit.
Framing Error (FE), Bit 4 - Framing error Indicates
that the received character is Improperly' framed by a
start and a stop bit and is detected by the absence of
the first stop bit. This error indlcate"s a synchronization
error, faulty transmission, or a break condition. The
framing error flag Is set or reset during the receive data
transfer time. Therefore, this error indicator is present
throughout the time that the associated character is
available.
Receiver Overrun (OVRN), Bit 5 - Overrun is an error
flag the indicates that one or more characters in the data
stream were lost. That is, a character or a number of
characters were received but not read from the Receive
Data Register (RDR) prior to subsequent characters
being received. The overrun condition begins at the"
midpoint of the last bit of the second character received

c8

SAMSUNG SEMICONDUCTOR

Parity Error(PE), Bit 6 - The parity error flag indicates
that the number of highs (ones) in the character does
not agree with the preselected odd or even parity. Odd
parity is defined to be when the total number of ones
is odd. The parity error indication will be present as long
as the data character Is in the RDR. If no parity is
selected, then both the transmitter parity generator
output and the receiver parity check results are
inhibited.
Interrupt Request (IRQ), Bit 7 - The IRQ bit indicates
the state of the IRQ output. Any interrupt condition with
its applicable enable will be indicated in this status bit.
Anytime the IRQ output is low the IRQ bit will be high
to indicate the interrupt or service request status. IRQ
is cleared by a read operation to the Receive Qata
Register or a write operation to the Transmit Data
Register.

190

KT3040J

CMOS INTEGRATED CIRCUIT

PCM MONOLITHIC FILTER.
The KT3040J filter is a monolithic circuit containing both transmit and
receive filters specifically designed for PCM CODEC filtering applications
in 8KHz sampled systems ..

16 CERDIP

The filter is manufactured using double-poly Si-Gate CMOS
technology. Switched capacitor integrators are used to simulate classical
LC ladder filters which exhibit low component sensitivity.
Transmit Filter Stage
The transmit filter is a fifth order elliptic low pass filter in series with
a fourth order Chebyshev high pass filter. It provides a flat response in
the passband and rejection of signals below 200Hz and above 3.4KHz.

II

Receive Filter Stage
The receive filter is a fifth order elliptic lowpass filter designed to
reconstruct the voice signal from the decoded/demultiplexed signal
which, as a result of the sampling process, is a stair-step signal havirig
the inherent sin XiX frequency response. The receive filter approximates
the function required to compensate for the degraded frequency
response and restore the flat passband response.

FEATURES
• Exceeds all 03/04 and CCITT specifications
• + 5V, - 5V power supplies
'
• Low power consumption: 45mW (0 dBmO into 6000)
30mW (power amps disabled)
• Power down mode: 0_5mW
• 20 dB gain adjust range
• No extemal anti-aliasing components
• Sin xix correction In receive filter
• 5OI6OHz rejection in transmit filter
• TTL and CMOS compatible logic
• All inputs protected against static discharge due to handling

c8

SAMSUNG SEMICONDUCT()R

191

CMOS INTEGRATED CIRCUIT

KT3040J
BLOCK DIAGRAM
PDN

GNDA

' GNDD

PWRI

Vee

CLK
CLKO

VFXO

GSx

Fig. 1

PIN CONFIGURATION
GNDA
CLKO

PDN

KT3040J

~~

VFRI

9J

Vee

ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Supply Voltages

Vs

±7

V

Power Dissipation

Po

1

W/PKG

Input Voltage

VIN

±7

V

Continuous

sec

+ 125
-65 to + 150

·C

Chllracterlstlcs

Output Short-Circuit Duration

Ts.e OUT

Operating Temperature Range

Ta

Storage Temperature

T.'g
TL

Lead Temperature (Soldering 10 seconds)

c8

SAMSUNG SEMICONDUCTOR

-25 to

300

Unit

·C
·C

192

CMOS INTEGRATED CIRCUIT

KT3040J
DC ELECTRICAL CHARACTERISTICS

(Unless otherwise noted, Ta = O·C to 70·C, Vee = + 5.0V ± 5%, Vee = - 5.0V ± 5%, clock frequency is 2.048MHz.
Typical parameters are specified at Ta= 25·C, Vee = +5.0V, Vee = - 5.0V, digital interface voltages measured with
respect to digital ground, GNDD. Analog voltages measured with respect to analog ground, GNDA.)
Characteristic

Synibol

Test Condition

Min

Typ

Max

Unit

Power Dissipation
Vee Standby Current

leeo

PDN=Voo

400

".A

Vee Standby Current

leBO

PDN=Voo

400

p.A

Vee Operating Current

leel

PWRI = Vee, Power Amp
Inactive

3.0

.4.0

mA

Vee Operating Current

'l ee1

PWRI = Vee, Power Amp
Inactive

3.0

4.0

mA

Vee Operating Current

lee2

(Note 1)

4.6

6.4

mA

Vee Operating Current

leB2

(Note 1)

4.6

6.4

mA

Input Current, CLK

liNe

VeeSVINSVee

-10

10

".A

Input Current, PDN

IINP

VeeSVINSVee

-100

Input Current, CLKO

IINo

VeeSVINSVee - 0.5V

-10

-0.1

".A

0.8

V

Vee

V

Digital Interface

Input Low Voltage, CLK, PDN

".A

Vil

0

Input High Voltage, CLK, PDN

VIH

2.2

Input Low Voltage, CLKO

VllO

Vee

Input Intermediate Voltage, CLKO

VIIO

-0.8

0,8

V

Input High Voltage, CLKO

VIHO

Vee·0.5

Vee

V

VeeSVFxlSVee

-100

100

VeeSVFxlSVee

10

Vee+ 0.5 '

V

Transmit Input OP Amp
Input Leakage Current, VFXI

lexl

Input ReSistance, VFXI

Rixi

Input Offset Voltage, VFXI

VOSXI

Common Mode Range, VFXI

VCM

Common Mode Rejection Ratio

CMRR

Power Supply Rejection of Vee or Vee

PSRR

Open Loop Output Resistance, ·Gsx

-2.5VSVINS +2.5V

-2.5VsVINS +2.5V

-20

20

-2.5

2.5

80

Minimum Load ReSistance, Gsx

Rl

Maximum Load Capacitance, Gsx

Cl
±2.5

Open Loop Voltage Gain, Gsx

Avol

Rl~10K

5\000.

c8

Fc

SAMSUNG SEMICONDUCTOR

KIl
100

Rl~10K

Open Loop Unity Gain Bandwidth, Gsx

KIl

10

VOXI

V

dB
1

Output Voltage Swing, Gsx

mV

dB

60

ROl

nA
Mil

pF
V
VN

2

MHz

193

I

KT3040J

CMOS INTEGRATED CIRCUIT

AC ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, Ta = 25°C. All parameters are specified for a signal level of OdBmO at 1KHz. The
OdBmO level is assumed to be 1.54 Vrms measured at the output, of the transmit or receive filter.)
Symbol

Characterlst.ic

Min

Test Condition

Typ

Max

Unit

TRANSMIT FILTER (Transmit filter input OP amp set to the non-Inverting unity gain mode,
with V,xl-1.09 Vrme unless otherwise noted.)
Minimum Load Resistance, V,xo

RLX

Load Capacitance, V,xo

CLX

Output Resistance, V,xo

- 2.5V < VOUT <2.5V

3

KO

-3.2VO,1~F

I

600

I

8
VFXI

VFXO

I

DIGITAl.
OUTPUT

50K

I

KT5116

KT3040J

I
I
I

GNDA
PWAO-

I
I
I

VFA1
60011

I

10

12

13
VFAO
O,1~F

I

50K

DIGITAL
INPUT

L-------'--~

Fig. 2
Note 1: Transmit voltage gain
Note 2: Receive Gai n

=R';2 R2 x v'2 (The filter itself introduces a 3dB gain), (R, + R2~ HiK)

=R3+R4R4 (R3 + R4 ~ 10K)

Note 3: In the configuration shown, the receive filter amplifiers will drive a 6000 T to R tennination to a maximum
signal level of B.5dBm. An alternative arrangement, using a transformer winding ratio equivalent to 1.414:1
and 3000 lesistor, Rs, will provide a maximum signal level of 10.1dBm across a 6000 termination
impedance.

Gain Adjust
Fig. 2 shows the signal path interconnections between the KT3040 and KT5116 single-channel CODEC. The trans!11it
RC coupling components have been chosen both for minimum passband droop and to present the correct impedance
to the CODEC during sampling.
'
. Optimum noise and distortion perfonnance will be obtained from the KT3040 filter when operated with system
peak overload voltages of ±2.5 to ±3.2V at VFXO and VFAO• When interfacing to a PCM CODEC with a peak
'
overload voltage outside this range, further gain or attenuation may be required.
For example, the KT3040 filter can be used with the KT3000 series CODEC which has a 5.5V peak overload voltage.
A gain stage following the transmit filter output and an attenuation stage following the CODEC output are required.

Board Layout
Care must be taken in PCB,layout to minimize power supply and ground noise. Analog ground (GNDA) of each filter
should be connected to digital ground (GNDD) at a single point, which should be bypassed to both power supplies.
Further power supply decoupling adjacent to each filter and CODEC is recommended. Ground loops should be
avoided, both between GNDA and GNPD a~d between the 'GNDA traces of adjacent filters and CODECs.

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199

I

KT3054J
COMBO CODEC·

CMOS INTEGRATED CIRCUIT

18 CERDIP

The KT3054 consists of ,..Iaw· monolithic PCM
CODEC/FILTERS utilizing the AID and DIA conversion
and a serial PCM interface. The devices are fabricated
using double-poly CMOS process C/£-process). The
encode portion of each device consists of an input
gain adjust amplifier, an active RC prefilter which
eliminatesNery high frequency noise prior to entering
a switched-capacitor band-pass filter that rejects
signals below 200Hz and above 3.400Hz.
Also Included are auto-zero circuitry and a companding
coder which samples the filtered signal and encodes
it in the companded ,..Iaw PCM format. The decode
portion of each device consists of an expanding
decoder, which reconstructs the analog signal from
the companded ,..Iaw code. a low-pass filter which
corrects for the sin xix response of the decoder output
and rejects signals above 3,400Hz and is followed by
a single-ended power amplifier capable of driving low
impedance loads.
The devices require two 1.536MHz. 1.544MHz or
2.048MHz transmit and receive master clocks, which
may be asynchronous; transmit and receive bit clocks,
which may vary from 64KHz to 2.048MHz; and transmit
and receive frame sync pulses. The timing of the frame
sync pulses and PCM data is compatible with both
industry standard formats ..

FEATURES
• Complete CODEC and filtering system (COMBO)
Including;.
-:- Transmit high-Pass and low-pass filtering
- Receive low-pass filter with sin xix correction
- ,..Iaw compatible COder and DECoder.
- Internal precision voltage reference
- Active RC noise filters
- Serial I/O interface
- Internal auto-zero circuitry
• ,..Iaw without signaling
• Meets or exceeds all DJD. and CCITT
specifications
.
• Low operating power: typically 60mW
• Power-down standby mode: typically 3mW .
• Automatic power-down
• :!: 5V operetlon
• TTL or CMOS compatible digital interfaces
• Maximizes line interface card circuit density

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CMOS INTEGRATED CIRCUIT

KT3054J
BLOCK DIAGRAMS
R2

R1

ANALOG IN

II
TIMING AND
CONTROL

+5V

-5V

,--'

a:w

:0::",
--':0::
0--,
60dB

2'

pF

MHz
mV
V

Common-Mode Rejection Ratio

CMRRXA DC Test

60

dB

Power Supply Rejection Ratio

PSRRXA DC Test

60

dB

Analog Interface with Receive Filter
Out out Resistance

RoRF

.Load Resistance

RLRF

Load Capacitance

CLRF

Output DC Offset Voltage

Pin VFRO
VFRO= ±2.5V

1

3

600
500

VOSRO,

0
0,

pF

200 . mV

-200

Power Dissipation
Power-Down Current

·lccO

No Load

0.5

1.5

mA

Power-Down Current

leeO

No Load

0.05

0.3

mA

Active Current

Icc1

No Load

6.0

9.0

rnA

Active Current

lee1

No Load

6.0

9.0

rnA

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CMOS INTEGRATED CIRCUIT

KT3054J
TIMING CHARACTERISTICS
Characteristic
Frequency of Master Clocks

Symbol

Test Condition

l/tPM

Depends on the device used and the
BClK~ClKSEl Pin.
MClKx and MClKR

Min

Typ

Max

1.536
1.544
2.048

Unit
MHz
MHz
MHz

Width of Master Clock High

tWMH

MClKx and MClKR

. 160

ns

Width of Master Clock low

. tWML

MClKx and MClKR.

160

ns

Rise Time of Master Clock

tRM

MCLKx and MClKR

50

ns

Fall Time of Master Clock

tFM

MClKx and MClKR

50

ns

Set-Up Time from BClKx High
(and FSx in long Frame Sync
Mode) to MClKx Falling Edge
Period of Bit Clock

tSSFM

First bit clock after the leading
edge of FSx

tps

100
485

ns
488

15,725

ns

Width of Bit Clock High

tWSH

VIH=2.2V

160

Width of Bit Clock low

tWBL

V1L =0.6V

160

ns

Rise Time of Bit Clock

tRS

tps = 488ns

50

ns

Fall Time of Bit Clock

tFS

tps =488ns

50

ns

Holding Time from Bit Clock
low to Frame Sync

tHsFL

long frame only

0

ns

Holding Time from Bit Clock .
High to Frame Sync

tHOLD

Short frame only

0

ns

Set-Up Time from Frame Sync
to Bit Clock low

tSFS

long frame only

80

ns

Delay Time from BClKx High
10 Dala Valid

tDSD

load = 150pF plus 2 lSTTl loads

0

load = 150pF plus 2 lSTTl loads

ns

180

ils

140

ns

50

165

ns

20

165

ns

Delay Time to TSx low

tXDP

Delay Time from BClKx low to
Data Oulpul Disabled

IDzc

Delay Time to Valid Data from
FSx or BClKx,Whlchever
Comes later

IDzF

Set-Up Time from DR Valid to
BClKRIX low

tSDS

50

ns

Hold Time from BClKRIX low to
DR Jnvalid

IHsD

50

ns

Delay Time from BClKRIX low
10 SIGR Valid
Set-Up Time from FSXlR 10
BClKXIR low .

.c8

tOFSSG
ISF

SAMSUNG SEMICONDUCTOR

CL=OpF 10 150pF

load = 50pF plus 2 lSTTl loads
Short frame sync pulse (lor 2 bit
clock periods long) (Note 1) ,

I

50

300

ns
ns

203

I

CMOS INTEGRATED CIRCUIT

KT3054J
TIMING CHARACTERISTICS
Characteristic

(Continued)

Symbol

Test Condition

Min

Typ

Max

Unit

Hold Time from BCLKXIR Low
to FSXlR Low

tHF

Short frame sync pulse (1 or 2 bit
clock periods long) (Note 1)

100

ns

Hold Time from 3rd Period of
Bit Clock Low to Frame Sync
(FSx or FS R)

tHBFI

Long frame sync pulse (from 3 to
8 bit clock periods long)

100

ns

Minimum Width of the Frame
Sync Pulse (Low Level)

tWFL

64K bitls operating mode

160

ns

Note 1: For short frame sync timing. FSx and FSR must go high while their respective bit clocks are high.

TIMING DIAGRAM
TSx

-:--------t\

MCLKR
MCLKx

BCLKX

FSx _ _ _ _--'T

SIGx

Dx---------~

tSDB

tHBD

tHBD

Fig. 2. Short Frame Sync Timing

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CMOS INTEGRATED CIRCUIT

KT3054J
TIMING DIAGRAM

FSX

(Continued)

----=

f--------tSSFB+-------i

I

tHBSF

SFX __________~~+---S-I-G-N-A-Ll-N-G-F-R-A-M-E--~--------------------~--------____~+_--~--~------

----- ,---,

\

\

tSSFF
f------++---tSSFB--------i

SFR

SIGNALING FRAME

----------------------~------_H--------------------~--+_------tSDB

tHBD

tHBD

SIGR.

------------------------------------------------------------------------~~----Fig. 3 Long Frame Sync Timing

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CMOS INTEGRATED CIRCUIT

·KT3054J
TRANSMISSION CHARACTERISTICS

(Unless otherwise specifiEld: Ta=O·C to 70·C, Vcc=5V±5%, Vaa= -5V±5%, GNDA=OV, f=1.02KHz,
VIN = OdBmO, transmit Input amplifier connected for unity:galn non-inverting.)
.

Characteristic

Min

Typ

Max

Unit

Symbol

Test Condition

AL

Nominal OdBmO level is 4dBm (6000)
OdBmO·

1.2276

Vrms

.2.501

VPK

Amplitude Response
Absolute Levels
Max Overload Level

tMAX

Max overload level (3.17dBmO)

Transmit Gain, Absolute

GXA

Ta=25·C, Vcc =5V, Vaa = -5V·
Input at GSx = OdBmO at 1Q20Hz

Transmit Gain, Relative to GXA

GXR

f=16Hz
f=50Hz
f=60Hz
f=200Hz
f = 300Hz - 3000Hz
f=33OOHz
f=3400Hz
f=4000Hz
f = 4600Hz and up, measure
response. from OHz to 4000Hz

Absolute Transmit Gain Variation
with Temperature

GXAT

Absolute Transmit Gain Variation
with Supply Voltage

GXAV

Transmit Gain Variations with .
Level

Sinusoidal test method
Reference level = -10dBmO
GXRL · VFxl + = - 4OdBmO to + 3dBmO
VFxl + = -5OdBmOto -40 dBmO
VFxl + = - 55dBmO to - 5OdBmO

Receive Gain, Absolute

GRA

Ta=25·C, Vcc =5V, Vea= -5V
Input = Digital code sequence for
OdBmO signal at 1020Hz

Receive Gain, Re·lative to GRA

GRR

f = OHz to 3000Hz
f=33OOHz
f=3400Hz
f=4000Hz

Absolute Receive Gain Variation
with Temperature

GRAT

Absolute Receive Gain Varlation
with Supply Voltage

GRAv

Re.ceive Gain Variations with
Level

GRRl

Receive Output Drive Level

VRO

c8

-0.15

0.15

dB

-40
-30
-26
-0.1
0.15
0.05
0
-14
-32

dB
dB
dB
dB
dB
dB
dB
dB
dB

Ta = O·C to 70·C

±0.1

dB

Vcc=5V±5%, Vaa= -5V±5%

±0.05

dB

-0.2
-0.4
-1.2

0.2
0.4
1.2

dB
dB
dB

-0.15

0.15

dB

-0.15
-0.35
-0.7

0.15
0.05
0
-14

dB
dB
dB
dB

Ta = O·C to 70·C

±0.1

dB

Vcc=5V±5%, Vea= -5V±5%

±0.05

dB

0.2
0.4
1.2

dB
dB
dB

2.5

V

-1.8
-0.15
-0.35
-0.7

. Sinusoidal test method; reference
input PCM code corresponds to an
Ideally encoded-10dBmO signal
PCM level = - 40dBmO to + 3 dBmO -0.2
PCM level = -5OdBmO to -40dBmO -0.4
PCM level = - 55dBmO to - 5OdBmO -1.2
Rl =6001l

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CMOS INTEGRATED CIRCUIT

KT3054J
TRANSMISSION CHARACTERISTICS
Characteristic

(Continued)

Symbol

Test Condition

Min

Typ

Max

Unit

Envelope Delay Distortion with Frequency
Transmit Delay, Absolute

OleA

f= 1600Hz

290

315

ILs

Transmit Delay, Relative to DXA

DXR

f = 500Hz - 600Hz
f = 600Hz - 600Hz
f = 800Hz - 1000Hz
f = 1000Hz -1600Hz
f = 1600Hz - 2600Hz
f = 2600Hz - 2800Hz
f 2800Hz - 3000Hz

195
120
50
20
55
80
130

220
145
75
40
75
105
155

ILS
ILs
ILS
ILS
ILs ILs
ILS

Receive Delay, Absolute

ORA

f= 1600Hz

180

200

ILs

ORR

f = 500Hz - 1000Hz
f = 1000Hz - 1600Hz
f = 1600Hz - 2600Hz
f = 2600Hz - 2800Hz
f = 2800Hz - 3000Hz

90·
125
175

ILS
ILs
ILS
ILs
ILs

Transmit Noise, C Message
Weighted

Nxe

VFxl+ =OV

12

15

d8rnCD

Receive Noise, C Message
Weighted

NRC

PCM code equals alternating
positive and negative zero

8

11

dBrnCD

Noise, Single Frequency

NRS

f=OKHz to 100KHz, loop around
measurement, VFxl + = OVrms

=

Receive Delay, Relative to ORA

-40
-30

-25
-20
70 100
145

Noise

Positive Power Supply Rejection,
. Transmit

PPSRx

VFxl + = OV,rms,
Vee = 5.0Voe + 100mVrms
f = OKHz - 50KHz

Negative Power Supply Rejection,
Transmit

VFxl + = OVrms,
NPSRx Vee = - 5.0Voe + 100mVrms
f = OKHz - 50KHz

Positive Power Supply Rejection,
Receive

PCM code equals positive zero
Vee = 5.0Voc + 100mVrms
PPSRR f = OHz - 4000Hz
f = 4KHz - 25KHz
f == 25KHz - 50KHz

Negative Power Supply Rejection,
Receive

PCM code equals positive zero
Vee= -5.0Voc + 100mVrms
NPSRR f = OHz -:- 4000Hz
f = 4KHz - 25KHz
,
f = 25KHz - 50KHz

c8

SAMSUNG SEMICONDUCTOR

-53 dBmO
40

dBC

40

dBC

40
40
36

dBC
dB
dB

40
40

dBC
dB
dB

36

207

CMOS INTEGRATED CIRCUIT

KT3054J
TRANSMISSION CHARACTERISTICS
Characteristic

(Continued)

Symbol

Spurious Out-of-Band Signals
at the Channel Output

Test Condition

Min

Typ

. Loop around measurement, OdBmO,
300Hz - 3400Hz input applied to
VFxl + , Measure individual image
SOS
signals at VFRO
4600Hz - 7600Hz
7600Hz - 8400Hz
8400Hz -100,OOOHz'

Max

Unit

-32
-40
-32

dB
dB
dB

Distortion
Signal to 'Total Distortion

STDx

Sinusoidal test method

Transmit or Receive
Half-Channel

STDR

Level = 3.0dBmO
=OdBmO to 130dBmO
= -40dBmO XMT
RCV
'" - 55dBmO XMT
RCV

Single Frequency Distortion,
Transmit

SFDx

-46

dB

Single Frequency Distortion,
Receive

SFDR

-46

dB

Intermodulation Distortion

IMD

Loop around measurement,
VFx + = -4dBmO to -21dBmO, two
frequencies in the range
300Hz - 3400Hz

-41

dB

Transmit to Receive Crosstalk,
OdBmO Transmit Level

CTX.R

f = 300Hz - 3400Hz
DR = Steady PCM code

-90

-75

dB

Receive to Transmit Crosstalk,
OdBmO Receive Level

CTR-x

f = 300Hz - 3400Hz, VFxl = OV

-90

-70
(Note 1)

dB

33
36
29
30
14
15

dBC
dBC
dBC
dBC
dBC
dBC

Crosstalk

Note 1. CTR.X is measured with a - 4OdBmO activating signal applied at VFxl +

ENCODING FORMAT AT DxOUTPUT
V1N (at GSx) =

c8

+ Full -

Scale

10000000

V1N (at GSx) = OV

11111111
01111111

V1N (at GSx) = - Full - Scale.

00000000

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CMOS INTEGRATED CIRCUIT

KT3054J
PIN DESCRIPTION
Pin No.

Symbol

Description .
Negative power supply pin. Vee

= -5V

1

Vee

2

GNDA

Analog ground. All signals are referenced to this pin.

3

VFRO

Analog output of the receive filter.

4

Vee

Positive power. supply pin. Vee

5

FSR

Receive frame sync pulse which enables BClKR to shift PCM data
into DR. FSR is an 8KHz pulse train.

6

DR

Receive data input. PCM data is shifted into DR following the FSR
leading edge.

± 5%.

I

The bit clock which shifts data into DR after the FSR leading edge.
Many vary from 64KHz to 2.048MHz. Alternatively, may be a: logic
input which selects either 1.536MHzl1.544MHz or 2.048MHz for
master clock in synchronous mode and BClKx is used for both
·transmit and receive directions.

BClKR/

7

= + 5V

±5%.

CLI~SEl

8

MClKR/
PDN

Receive master clock. Must be 1.536MHz, 1.544MHz or 2.048MHz.
May be asynchronous with MClKx, but should be synchronous with
MClKx for best performance. When MClKRis connected continously
low, MClKR is selected for all internal timing. When MClKR is
connected continuously high the device is powered down.

9

MClKx

Transmit master clock. Must be 1.536MHz, 1.544MHz or 2.048MHz.
Maybe asynchronous with MClKR.

10

BClKx

The bit clock which shifts out the PCM data on Dx. May vary from
64KHz to 2.048MHz, but must be synchronous with MClKx.

11

Dx

The TRI·STATE PCM data output which is enabled by FSx.

12

FSx

Transmit frame sync pulse input which enables BClKx to shift
out the PCM data on Dx. FSx·is an 8KHz pulse train.

13

TSx

Open drain ouptut which pulses low during the encoder time slot.

14

GSx

Analog output of the transmit input amplifier.
Used to externally !iet again.

15

VFxl-

Inverting input of the transmit input amplifier.

16

VFxl+

Non·inverting input of the trans.mitinput amplifier.

,

PIN CONNECTION
VFx'+
VFx'GSx
TSx

KT3054J
DR

FSx

6

BCLKRI
CLKSEL

BCLKx

MCLKRI

PDN

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KT3054J

CMOS INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION
POWER·UP
When power is first applied, power-on reset circuitry initializes the COMBO and places it into the power-down mode.
All non-essential circuits are deactivated and the Ox and VFRO outputs are put in high impedance states. To powerup the device, a logical low level or clock must be applied to the MCLKFJPDN pin and FSx and/or FSRpulses must
be 'present. Thus, 2 power-down control modes are available. The first is to pull the MCLKFJPDN pin high; the
alternative is to hold both FSx and FSR inputs continuously low-the device will power-down approximately 2ms
after the last FSx or FSR pulse. Power-up will occur on the first FSx or FSR pulse. The TRI-STATE PCM data
output, Dx, will remain in the high impedance state until the second FSx pulse.

SYNCHRONOUS OPERATION
For synchronous operation, the same master clock and bit clock should be used for both the transmit and receive
directions. In this mode, a clock must be applied to MCLKx and the MCLKFJPDN pin can be used as a power-down
control. A low level on MCLKR/PDN powers up the device and a high level powers down the device. In either case,
MCLKx will be selected as the master clock for both the transmit and receive circuits. A bit clock must also be
applied to BCLKx and the BCLKFJCLKSEL can be used to select the proper internal divider for a master clock of
1.536MHz, 1.544MHz or 2.048MHz. For 1.544MHz operation, the device automatically compensates for the 193rd
clock pulse each frame.
With a fixed level on the BcLKFJCLKSEL pin, BCLKx will be selected as the bit clock for both the transmit and
receive directions. In this synchronous mode, the bit clock, BCLKx, may be from 64KHz to 2.048MHz, but must
be synchronous with MCLKx.
Each FSx pulse begins the encoding cycle and the PCM data from the previous encode cycle .is shifted out of
the enabled Dx output on the positive edge of BCLKx. After 8 bit clock periods, the TRI·STATE Dx output is retumed
to a high impedance state. With an FSRpulse, PCM data is latched via the DR Input on the negative edge of BCLKx
(or BCLKR if running). FSx and FSR must be synchronous with MCLKXlR .

TABLE 1. Selection of Master Clock Frequencies
BCLKR/CLKSEL

Master Clock Frequency Selected

Clocked,

1.536MHz or 1.544MHz

0

2.048MHz

1 (or Open Circuit)

1.536MHz or 1.544MHz

ASYNCHRONOUS OPERATION
For asynchronous operation, separate transmit and receive clocks may be applied .. MCLKx and MCLKR must be
1.536MHz, 1.544MHz for the KT3054, and need not be synchronous. For best transmission performance, however,
MCLKR should be synchronous with MCLKx, which is easily achieved by applying only static logic levels to the
MCLKFJPDN pin. This will automatically connect MCLKx to all internal MCLKR functions (see Pin Description). For
1.544MHz operation, the device automatically compensates fo~ the 193rd clock pulse each frame. FSx starts each
encoding cycle and must be synchronous with MCLKx and BCLKx. FSR starts each decoding cycle and must be
synchronous with BCLKR. BCLKRmust be a clock, the logic levels shown in Table 1 are not valid in asynchropous
.
mode. BCLKx and BCLKR may operate from 64KHz to 2.048MHz.

SHORT FRAME SYNC OPERATION
The COMBO can utilize a long frame sync pulse. Upon power initialization, the device assumes a short frame mode.
In this mode, both frame sync pulses, FSx and FSR, must be one bit clock period long, ""ith timing relationships
specified in Figure 2. With FSx high during a falling edge of BCLKx, the next rising edge of BCLKx enables the
Ox TRI-STATE output buffer, which will output the sign bit. The following seven rising edges clock out the
remainirig seven bits, and the next falling edge c;lisables the Dx Ol,ltput. With FSR high during a falling edge of
BCLKR(BCLKx In synch~onous mode), the next falling edge of BCLKR latches in the sign bit. The following seven
falling edges latgch in the seven remaining bits. All four devices may utilize the short frame sync pulse in synchronous
or asynchronous operating mode.
'

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KT3054J

CMOS INTEGRATED CIRCUIT

LONG FRAME SYNC OPERATION
To use the frame mode, both the frame sync pulses, FSx and FSR, must be three or more bit clock periods
long, with timing relationships specified in Figure 3. Based on the transmit frame sync, FSx, the COMBO will
sense whether short or long frame sync pulses are being used. For 64KHz operation, the frame sync pulse
must be kept low for a minimum of 160ns. The Dx TRI-STATE output buffer is enabled with the rising edge of FSx
or the rising edge of BClKx, whichever comes later, and the first bit clocked out is the sign bit. The following
seven BClKx rising edges clock out the remaining seven bits. The Dx output is disabled by the falling BClKx edge
following the eighth rising edge, or by FSx going low, whichever comes later. A rising edge on the receive frame
sync pulse, FSR, will cause the PCM data at DA to be latched in on the next eight falling edges of BClKR (BClKx
in synchronous mode). All four devices may utilize the long frame sync pulse in synchronous or asynchronous mode.

RECEIVE SECTION
The receive section consists of an expanding DAC which drives a fifth order switched-capacitor low pass filter
clocked at 256KHz. The decoder is A-law or wlaw (KT3054) and the 5th order low pass filter corrects for the sin x/x
attenuation due to the 8KHz sample/hold. The filter is then followed by a 2nd order RC active post-filter/power
amplifier capable of driving a 6000 load to a level of 7.2dBm. The receive section is unity-gain. Upon the
occurrence of FSR; the data at the DR input is clocked in on the falling edge of the next eight BClKA (BClKx)
periods. At the end of the decoder time slot, the decoding cycle begins, and 10l-ls later the decoder DAC output
is updated. The total decoder delay is -10l-ls (decoder update) plus 110l-ls (filter delay) plus 62.51-1s (1/2 frame), which
gives approximately 180l-Is.

TRANSMIT SECTION
The transmit section input is an operational amplifier with provision for gain adjustment using two external
resistors, see Figure 4. The low noise and wide bandwidth allow gains in excess of 20dB across the audio
passband to be realized. The op amp drives a unity-gain filter consisting of RC active pre-filter, followed by an eighth
order switched-capacitor bandpass filter clocked at 256KHz. The output of this filter directly drives the encoder
sample-and-hold circuit. The AID is of companding type according to wlaw (KT3054) or A-law coding conventions. A
precision voltage reference is trimmed in manufacturing to provide an input overload (tMAxl of nominally 2.5V peak
(see table of Transmission Characteristics). The FSx frame sync pulse controls the sampling of the filter output,
and then the successive-approximation encoding cycle begins. The 8-bit code is then loaded into a buffer and shifted
out through Dx at the next FSx pulse. The total encoding delay will be approximately 1651-1s (due to the transmit
filter) plus 1251-1s (due to encoding delay), which totals 290l-Is. Any offset voltage due to the filters or comparator
is cancelled by sign bit integration.

APPLICATION INFORMATION
POWER SUPPLIES
In applications where the printed circuit board may be plugged into a "hot" socket with power and clocks already
present, an extra long ground pin in the connector should be used.
All ground connections to each device should meet at a common point as close as possible to the GNDA pin.
This minimizes the interaction of ground return currents flowing through a common bus impedance. 0.11-1F supply
decoupling capacitors should be connected from this common ground point to Vee and Vee.
For best performance, the ground point of each CODEC/FllTER on a card should be connected to a common card
ground in star formation, rather than via a ground bus.
This common ground point should be decoupled to Vee and Vee with 10l-lF capacitors.

RECEIVE GAIN ADJUSTMENT
For applications where CO DEC/filter receive output must drive a 6000 load, but a peak swing lower than ± 2.5V
is required, the receive gain can be easily adjusted by inl?erting a matched T-pad or r-pad at the output. Table"
lists the required resistor values for 6000 terminations. As these are generally non-standard values, the equations
can be used to compute the attenuation of the closest practical set of resistors. It may be necessary to use
unequal values for the R1 or R4 arms of the. attenuators to achieve a precise attenuation. Generally it is tolerable
to allow a small deviation of the input impedance from nominal while still maintaining a good return loss. For
example a 30dB return loss against 6000 is obtained if the output impedance of the attenuator is in the range 2820
to to 3100 (assuming a perfect transformer).

c8

SAMSUNG SEMICONDUCTOR

211

I

CMOS INTEGRATED CIRCUIT

KT3054J

T-Pad Attenuator

'/I"-Pad Attenuator

r-------..,
3001

I

R3

~
l

R4

R4

IZ2

300

1:,.[2,2U600

r-------...,
R1
111
I

I
I
I

Z1!

I
I

1

I
IL.. ___ _

N +1
N
= Z1 (W-1)-~
(N2-1)
N
R2 = z,J Z1'Z2 (w=-:1)
2

R1

.
Where: N
and

I POWER IN
='\1 POWER OUT

s=~

=

Also: Z
.JZsc,-Zoc
.
Where Zsc, = impedance with short circuit termination.
and Zoe = impedance with open circuit termination
TABLE II. Attenuator Table for Z1

c8

SAMSUNG

= Z2 = 3000 (All

Values in 11)

dB

R1

R2

R3

R4

0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2
3
4
5
6
7
8
9
10
11
12
13
14
.15
16
18
20

1.7
3.5
5.2
6.9
8.5
10.4
12.1
13.8
15.5
17.3
34.4
51.3
68
84
100
115
379
143
156
168
180
190
200
210
218
233
246

26K
.13K
8.7K
6.5K
5.2K
4.4K
3.7K
3.3K
2.9K
2.61
1.3K
850
650
494
402
380
284
244
211
184
161
142
125 .
110

3.5
6.9
10.4
13.8
17.3
21.3
24.2
27.7
31.1
34.6
70
107
144
183
224
269
317
370
427
490
550
635
720
816
924
1.17K
1.5K

52K
26K
17.4K
13K
10.5K
8.7K
7.5K
6.5K
5.8K
5.2K
2.6K
1.8K
1.3K
1.1K
900
785
698
630
527
535

SEMICON~UCrOR

98

77
61

500

473
450
430
413
386
366

212

CMOS INTEGRATED CIRCUIT

KT3054J
APPLICATION CIRCUITS

-5V
TO SllC

Vee

VFxl+

GNDA

VFxl GSx

Vee

ANALOG
INTERFACE

KT3054J

VFRO

------ FROM TSAC'

FROM SLiC

---------FSx

FSR

______ 1
FROM TSAC

5V OR GNDA
PDN

I

I

DIGITAL
Ox INTERFACE

DR
BClKR/ClKSEl

BClKx

MClKR/PDN

MClKx

Note: XMIT gain = 20 x log(R1

:t2),

(R1

BClKx (2.048MHzl1.544MHz)

+ R2) > 10KO.

Fig. 4

c8

SAMSUNG SEMICONDUCTOR

213

CMOS INTEGRATED CIRCUIT

KT3064J
COMBO CODEC

20 CERDIP

The KT3064 Vt-Iaw), is monolithic PCM CODECI
FILTERS utilizing the AID and D/A conversion, a serial
PCM interface. The devices are fabricated using
double-poly CMOS process. The device feature an
additional receive power amplifierto'provide push-pull
balanced output drive capability. The receive gain can
be adjusted by means of two external resistors for an
output level of up to ± 6.6V across a balanced 6000
load. The Analog Loopback switch and TSx output is
also included.

FEATURES
• wlaw compatible
• Meets or exceeds all D3JD4 and CCITT
specifications
• :!: 5V operation
• Low operating power: typically 7,OmW
• Active RC noise filters
• Power-down standby mode: typically 3mW
• Automatic power-down
• Transmit high-pass and low-pass filtering
• Internal precision voltage reference
• Serial I/O interface
• Internal auto-zero circuitry
• TTL or CMOS compatible digital interfa,ce
• Maximizes line interface card circuit density

BLOCK DIAGRAM
R2

c8

SAMSUNG SEMICONDUCTOR

214

CMOS INTEGRATED CIRCUIT

KT3064J
ABSOLUTE MAXIMUM RATINGS
Characteristic

Value

Unit

Vee

7

V

Vee

-7

V
V

Symbol

Vee to GNDA
Vae to GNDA
Voltage at Any Analog Input or Output

Analoge 1/0

Vee+0.3 to VeB -0.3

Voltage. at Any Digital Input or Output

Digital 1/0

Vee+0.3 to GNDA-0.3

V

Ta

-25-+125

·C

Storage Temperature Range

T.

-65-+150

·C

Lead Temperature Soldering, 10 secs)

TL

300

·C

Operating Temperature Range

I

ELECTRICAL CHARACTERISTICS
(Unless otherwise noted: Vee=5.0V±5%, Vee= -5V±5%, GNDA=OV, Ta=O·C to 70·C; typical characteristics
specified at Vee = 5.0V, Ta = 25°C; ali signals are referenced to GNDA)
Characteristic

Symbol

Test Condition

Min

Typ

. Max

Unit

Power Dissipation

Active Current

led1

Power amplifiers active, VPI = OV

7.0

10.0.

mA

Active Current

lee1

Power amplifiers active, VPI = OV

7.0

10.0

mA

Power'Down Current

leeo

0.5

1.5 .

mA

leBo

0.05

0.3

mA

Power·Down Current
Digital Interface

Input Low Current

hL

GNDAsV1NSV1L, Ali digital inputs

-10

10

p.A

Input High Current

I'H

V'HSV'NSVee

-10

10

p.A

Output Current in High
Impedance State (TRI·STATE)

loz

Ox, GNDASVoSVee

-10

10

p.A

Input Low Voltage

V'L

0.6

V

Input High Voltage

V'H

2.2

Output Low Voltage

VOL

Dx,IL=3.2mA
SIG R, IL = 1.0mA
Tsx, IL=3.2mA, Open Drain

Output High Voltage

VOH

Ox, IH = - 3.2mA
SIG R, IH = - 1.0mA

V
0.4
0.4
0.4

2.4
·2.4

V

V

Analog Interface with Transmit Input Amplifier

Input Leakage Current

I,XA

- 2.5V sV S + 2.5V, VFxl + or VFxl-

Input Resistance

R,XA

- 2.5V sV S + 2.5V, VFxl

Output Resistance

RoXA

Closed loop, unity gain

Load Resistance

RLXA

GSx

Load Capacitance

CLXA

GSx

Output Dynamic Range

VoXA

GSx, RL~ 10KO

ciS

SAMSUNG SEMICONDUCTOR

+ or VFxl-

-200

200

10
1

3

10

MO
KO

50

±2.B

nA
MO

pF
V

215

CMOS INTEGRATED CIRCUIT

KT3064J
ELECTRICAL CHARACTERISTICS
, Characteristic
Voltage Gain

(Continued)
Test Conditions

Symbol
Av'XA

Unit-Gain Bandwidth

FuXA

Offset Voltage

ViJsXA

Common-Mode Voltage

VeMXA

Min

Typ

Max

5000

VFxl + to GSx

1
CMRRXA>60dB

Unit

VIV
2

MHz

-20

20

-2.5

2.5

mV
V

Common-Mode Rejection Ratio CMRRXA DC Test

60

dB

Power Supply Rejection Ratio

60

dB

PSRRXA DC Test

Analog Interface with Receive Filter (All Devices)
Output Resistance
Output DC Offset Voltage

RoRF
VOSRO

1

Pin VFRO
Measure from VFRO to GNDA

load Resistance

RLRF

VFRO= ±2.5V

load Capacitance

CLAF

Connect from VFRO'to GND A

-200

3

0

200

mV

10

KO
25

pF

Analog Interface with Power Amplifiers (All Devices)
Input Leakage Current

IPI

-1.0V:s;VPI:s;1.0V:s;VPI:s;1.0V

Input Resistance

RIPI

-1.0V :s;VPI:s; 1.0V

Input Offset Voltage

Vias

,

Output Resistance
Unit-Gain Bandwidth

ROP
Fe
CLP

nA
MO

-25

25
1

KHz
100
500
1000

VPO+ or
VPO- to
GNDA

mV

0

400

Open loop (VPO - )
RL = 6000
Rl = 3000

100

10

Inverting unity gain at
VPO+ or VPORL~15000

load Capacitance

-100

pF
pF
pF

Gain from VPO - to VPO +

GA p +

RL::: 3000 VPO + to GNDA level at
VPO-::: -1.77Vrms (+3dBmo)

Power Supply Rejection of
Vee or VBB

PSRR p

VPO - connected to. VPI
OKHz-4KHz
OKHz-50KHz

Frequency of Master Clock

IltpM

Depends on the device used and
the BClKR/ClKSEl Pin
MClKx and MClKA

Width of Master Clock High

tWMH

MClKx and MClKR

160

Width of Master Clock low

tWML

MClKx and MClKR

160

Rise Time of Master Cl:ock

tRM

MClKx and MClKR

50

ns

Fall Time of Master Clock

tFM

MClKx and MClKR

50

ns

Set-Up Time from BCLKx High
(and FSx in long Frame Sync'
Mode) to MClKx Falling Edge
Period of Bit Clock

tSBFM

First bit clock after the leading
edge of FSx

tps

VIV

-1

60

dB
dB

36
1.536
1.544
'2.048

.

ns
ns

ns

100
485

MHz
MHz
MHz

488

15,725

ns

Width of Bit Clock High

tWBH

V'H= 2.2V

160

ns

Width of Bit Clock low

tWBl

Vll:::0.6V

160

ns

Rise Time of Bit Clock

tRB

tPB= 460ns

50

ns

Fall Time of Bit Clock

tF8

tPB= 488ns

50

ns

c8

SAMSUNG SEMICONDUCTOR

216

KT3064J

CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
Characteristic

(Continued)

Symbol

Test Conditions

Min

Typ

Max

Unit

Holding Time from Bit Clock
Low to Frame Sync

tHBF

Long frame only

0

ns

Holding Time from Bit Clock
High to Frame Sync

tHOLO

Short frame only

0

ns

Set-Up Time for Frame Sync
to Bit Clock Low

tSFB

Long Frame Only

80

ris

Delay Time. from BCLKx High
to Data Valid

tOBo

Load = 150pF plus 2 LSTIL loads

0

Delay Time to TSx Low

txop

Load = 150pF plus 2 LSTIL loads

Delay Time from BCLKx Low
to Data Output Disabled

tOEe

Delay Time to Valid Data from
FSx or BCLKx,
whichever Comes Later

tOZF

Set-Up Time from DR Valid to
BCLKRIX Low

tSOB

50

ns

Hold Time from BCLKR/x Low
to DR Invalid

IHBO

50

ns

Delay Time from BCLKRIX Low
to SIGR Valid

tOFSSF

Set-Up Time from FSX1R to
BCLKXlR Low

CL=OpF to 150pF

180

ns

140

ns

50

165

ns

. 20

165

ns

Load = 50pF plus 2 LSTIL loads

300

ns

tSF

Short frame sync pulse
(1 or 2 bit clock periods 10ng)(Note 1)

50

ns

Hold Time from BCLKx1R Low
. to FSXlR Low

tHF

Short frame sym; pulse
(1 or 2 bit clock periods 10ng)(Note 1)

100

ns

Hold Time from 3rd Period of
Bit Clock low to Frame Sync
(FSx of FSR)

tHBFI

Long frame sync pulse
(from 3.to 8 bit clock periods long)

100

ns

Minimum Width of the Frame .
Sync Pulse (Low Level)

tWFL

64K bitls operating mode

160

ns

Note 1: For short frame sync timing, FSx and FSR must go high while their respective bit Clocks are high.

PIN CONFIGURATION

.

.,

>

+

0

Il.

>

c8

+

I

J'
>

J'
>

«

0
Z

(!)

I

0

Il.

>

SAMSUNG SEMICONDUCTOR

::

'..J

:::;;

u

0:

>

0

a:

IL

>

u
<)

>

a:

(/)

IL

a:
0

~

..J

In

Ii:

"

U

z

0

..J

Il.

In

"U:::;;

u

Ii:

..J

217

II

CMOS INTEGRATED CIRCUIT

KT3064J
TIMING DIAGRAM

MClKx
MClKA

BlCKx

FSx

loze
Ox

BClKA

Fig. 2. Short Frame Sync Timing

MClKX
MClKA

BClKx

FSX

Ox

BClKA

FSR

----J["

Fig. 3 Long Frame Sync Timing

c8

SAMSUNG SEMICONDUCTOR

218

CMOS INTEGRATED CIRCUIT

KT3064J
PIN DESCRIPTION
Pin

c8

Name

Function

1

VPO+

2

GNOA

Analog ground. All signals are referenced to this pin.

3

vpo-

The inverted output of the receive power amplifier.

4

VPI

5

VFAO

6

Vee'

Positive power supply pin Vee

7

FSA

Receive frame sync pulse which enables BClKA to shift PCM data into
OA, FS A is an BKHz pulse train. (refer to Fig 2 and 3 for timing details)

B

OA

Receive data input. PCM data is shifted into OA following the FSA
leading edge.

9

BClKFJ
ClKSEl

10

MClKAI
PON

Receive master clock. Must be 1.536MHz or 2.04BMHz. May be
asynchronous with MClKx, but should be synchronous with MClKx
for best performance. When MClKA is connected continuously low,
MClKx is selected for ,all internal timing. When MClKA is connected
continuously high, the device is powered down.

11

MClKx

Transmit master clock. Must be 1.536MHz, 1.544MHz or 2.04BMHz.
May be asyncl"jronous with MClKA,

12

BClKx

The bit clock which shifts out the PCM data on Ox. May vary from
64KHz to 2.04BMHz, but must be synchronous with MClKx.

13

Ox

The TRI-STATE PCM data output which is enabled by FSx.

14

FSx

Transmit frame sync pulse input which enables BClKx to shift out the
PCM data a on Ox, FSx is an BKHz pulse train. (refer to Fig 2, 3)

1,5

TSx

The non-inverted output of the receive power amplifier.

Inverting input to the receive power amplifier.
Also powers down both amplifiers when connected to Vee.
Analog output of 'the receive filter.

II

= +5V±5%.

The bit clo.ck which shifts data into OA after the FSA leading edge.
,May vary from 64KHz to 2.04BMHz. Alternatively, may be a logic input
which selects either 1.536MHzl1.544MHz or 2.04BMHz for master clock
in synchronous mode and BClKx is used for both transmit and receive
directions. (see Table 1)

Open drain output which pulses low during

t~e

encoder time slot.

'Analog loopback control inpu!. Must be set to logic '0' for normal
operation. When pulled to logic '1', the transmit filter input is dis
connected from the output of the preamplifier and connected to the
VPO+ output of the receive power, amplifier.

16

ANlB

17

GSx

Analog output of the transmit input amplifier.
Used to externally set again.

1B

VFxl-

Inverting input of the transmit input amplifier.

19

YFxl+

Non-inverting input of the transmit input amplifier.

20

Vee

Negative power supply pin Vee::: - 5V ± 5%.

SAMSUNG SEMICONDUCTOR

219

CMOS INTEGRATED CIRCUIT

KT3064J
.FUNCTIONAL DESCRIPTION
POWER·UP

When. power is first applied, power-on reset circuitry initializes the COMBO and places it into the power-down mode.
All non-essential circuits are deactivated and the Ox, VFRO, VPO - and VPO + outputs are put in high impedance
states. To power-up the device, a logical low level or clock must be applied to the MCli

Il!
co

+0.5

CO

I

:!!

4~

40 ..:;....

40

30

20 r-

~

39~5116

~
Iz
:c

~4

:k

g
z~

Ii

~ANNEL
f-

~"23
22~5-

"

JANK
SPECIFICATIONS _ _

+30

-10

-30 -40 -50
INPUT LEVEL - dBmO

-0.1

-0.1

0..1 _

~~5

-0.05

-,

-1

-0.5.1
03

-2 _~HANNEL BANK

I

-3

-20

r
-0.1

SPECIFICATIONS

I I

10

+1

-4
+10

-60

I
-w

-3

-20

-30

-40

-50

I
-80

-70

INPUT LEVEL - dBmO

Fig. 5

FIg. •

AID, D/A CONVERSION TIMING
f--------------~125~oec---------------i

SAMPLE AND HOLD
SAMPLE TIME

::: 32 MASTER CLOCKS·
ENABLE SAR
SAR REQUIRES

::: 128 MASTER CLOCKS

_____--J/
________________

~

RCV SYNC

\~<------------------------J;lANALOGOUTPUTUPDATED

__________

Fig. 6

DATA INPUT/OUTPUT TIMING
1-_2OO_n_O_-I REQUIRED FOR DATA TO TRANSFER

KT5116

FROM MASTER TO SLAVE

XMIT
INTERNAL
CLOCK

DIGITAL
OUT
XMIT SYNC
)(VALID DATA
XMIT CLOCK

------------------'

RCV
INTERNAL
CLOCK

REQUIRED TO TRANSFER DATA
FROM MASTER TO SLAVE

200n

DIGITAL
IN
RCV SYNC

SOns REQUIRED TO LOAD MASTER

RCV CLOCK

VALID INCOMING DATA

. Fig. 7

c8

SAMSUNG SEMICONDUCTOR

234

KT5116J

CMOS INTEGRATED CIRCUIT

KT5116 AID CONVERTER (p.·Law Encoder) TRANSFER CHARACTERISTIC
11111111

-"".....

11110000
11100000

/

1101 0000

..-

l/

I

11000000
10110000

~

5

10100000

oooo}

10010000

II

1000
--' 0000 0000

0--

~

00010000

13

00100000

Ci

0011 0000
0100 0000

j

01010000

,

01100000
01110000
01111111

-

~

V-

./

~

- VREF

0

2

+ VREF

-2-

+VREF

Fig. 8 ANALOG INPUT (VOLTS)

-

D/A CONVERTER (p.·Law Decoder) TRANSFER CHARACTERISTIC
01111111

.........

0111 0000

.......

01100000

~

,

\.

01010000
0100 0000
0011 0000
00100000
00010000

10010000
10100000
1011 0000

,

1100 0000

\

1101 0000
11100000

r"

11110000

~ i"--

11111111
-VREF

- VREF

-2-

0

+ VREF

2

+VREF

Fig. 9 ANALOG OUTPUT (VOLTS)

c8

SAMSUNG SEMICONDUCTOR

235

CMOS INTEGRATED CIRCUIT

KT5116J

64KHz OPERATION, TRANSMITTER SECTION TIMING
1---------------125~.~c

----:-----------1

XMITSYNC
1 MASTER
CLOCK
PERIOD
(MIN)

Fig. 10 PCM DATA PRESENT
Note: All rise and fail iimes are measured from O.4V and 2.4V. All delay times are measured from 1.4V.

64KHz OPERATION, RECEIVER SECTION TIMING
125~.ec------------~--1
.

-1

17 MASTER

.

CLOCK'
PERIODS
(MIN)

tRDS

~ALI fiR,,f;J/ilFlIQ!ifilil.Q/'ifll'.QfiIi!0r,:JlFfl\CJrlli!iJ,QfilW.CJrl

.fi::1:1t:j~ff11:i E7v:t1i~v:t:IJ EJVJ.'t:J ~tJ':ff:J ~tN:Je3~ ~\f11:J~ \

Fig. 11
Note: All. rise and fall times are measured from O.4V and 2.4V. All delay times are measured from 1.4V.

PCM SYSTEM BLOCK DIAGRAM
KT5116
GAIN ADJUST'

8

BAND
PASS
FILTER'

TRANSMITIER .
(AID)

DIGITAL
MUX

. DIGITAL
TRUNK

FROM
{
OTHER
CHANNELS.

2 WIRE CABLE

I
I
I
I
I

I
I

---~----

13
LOW
PASS
FILTER

I

I

LL~~~~~~~~ __ _

c8

SAMSUNG SEMICONDUCTOR

RECEIVER
(DIA)

12
DIGITAL
DEMUX

DIGITAL
TRUNK

TO
{
OTHER
CHANNELS

236 .

KT5116J

CMOS INTEGRATED CIRCUIT

SYSTEM CHARACTERISTICS TEST CONFIGURATION

r-----------,
I

I
I
I

I

IDEAL DECODER

I
I
1.004KHz
SIGNAL
SOURCE

I

I----ilf---{
I

I

I

I
J

I

I

SYSTEM

I

I
I

II

IL _ _ _ _ _ _ _ _ _ _ _ .,
I

J

I
I
I

ENCODER ONLY

J

NOUT
HP3551A

1.004KHz
NOTCH

I
FILTER

FILTER

I
.
L ______________

~

_______ I
~

SOUT+NoUT

Fig. 12
Note: The ideal decoder consists of a digital decomponder and a 13·bit precision DAC.

PERFORMANCE EVALUATION
The equipment connections shOwn in Figure 12 can be used to evaluate tlie performance of the KT5116.
An analog signal provided by the HP3551 a transmission test set is connected to the Analog Input (Pin 1) of the
KT5116. The Digital Output of the CODeC is tied back to the Digital Input and the Analog Output is fed through
a lOW-pass filter to the HP3551A.
Remaining pins of the KT5116 are connected as follows:
1. RCV SYNC is tied to XMIT SYNC.
2. XMIT CLOCK is tied to Master CLOCK. The signal is inverted and tied to RCV clock.
The following timing signals are required:
1. Master CLOCK=2.048MHz
2. XMIT SYNC repetition rate=8KHz
3. XMIT SYNC width=8 XMIT CLOCK periods.
when all the above requirements are met, the set-up of Figure 12 permits the measurement of synchronous system
performance over a wide range of Analog Inputs.
The data register and ideal decoder provide a means of checking the encoder portion of the KT5116 independently
of .the decoder section. To test the system in the asynchronous mode, Master CLOCK should be separated from
RCV CLOCK. XMIT CLOCK and RCV CLOCK are separated also separated.

c8

SAMSUNG S.EMICONDUCTOR

237

CMOS INTEGRATED CIRCUIT

KT5116J

ANALOG INPUT

DEMO SET CIRCUIT DIAGRAM

ANALOG OUTPUT

POWER
AMP

R3

2.048MHz

r----IO~~
R6

10MD

'NON
·POLARIZED
2.048MHz

128KHz

5V

2KII±1'10

• Power Supply Ripple Rejection
C7

+5V

C6

C5

C4

0---1I--I--I~-Ic.-lI-.05-~-F-x-4-l'" .05~F
C3

GNDDo--~-~-~--4

GNDAo---------4----~--,
C2

.05~F

-5Vo--------~-----

NOTE: All unused input connected to GNDD or Vee, only in HeT series.

c8

SAMSUNG SEMICONDUCTOR

238

LM567C

LINEAR INTEGRATED aRCUIT

TONE DECODER

8 DIP

The LM567C is a monolithic phase locked loop system designed to pr0vide a saturated transistor switch to GND. when an input signal is present
within the passband. External components are used to independently
set center frequency bandwidth and output delay.

FEATURES
•
•
•
•
•
•

Wide frequency range (O.01Hz - 500kHz).
Bandwidth adJustabl, from 0 to 14%
logic compatible output wHh 100mA current sinking capability.
Inherant Immunity to fal.. 81gna18.
High rejection of out..of.band slgnal8 and nolae.
Frequency range adjustable over 20:1 range by an external
re8lstor.

8 SOP

II

APPLICATIONS
•
•
•
•
•
•
•

Touch Tone Decoder
Wireless Intercom.
Communications paging deco,ders
Frequency monitoring and control.
Ultrasonic controls (remote TV etc.)
Carrier current remote controls.
Precision oscillator.

ORDERING INFORMATION
Device

Package

LM567CN

8 DIP

LM567CD

8 SOP

Operating Temperature
0- +70·C

SCHEMATIC DIAGRAM

c8

SAMSUNG SEMICONDUCI'OR

239

LINEAR INTEGRATED CIRCUIT

LM567C

=

ABSOLUTE MAXIMUM RATINGS (Ta 25°C)
Characteristic
Operating Voltage
Input Voltage
Output Voltage
IPower Dissipatlon
Operating Temperature
Storage Temperature

Symbol

value

Unit

10
-10 -Vee +0.5
15
300
0-+70
-65-+150

V
V
V
mW

'J

Vcc
V1N
Vo

Pd
Topr
Tstg

"C
°C

ELECTRICAL CHARACTERISTICS
Nee =5JJV. T... 25°C unless other wise specified)

Characteristic

Symbol

Operating Voltage Range
Supply Current Quiescent
Supply Current Activated
Quiescent Power Dissipation

Vcc
Icc-1
Icc-2

Highest Center Frequency
Center Frequency Stability
Center Frequency Shift
With Supply Voltage

HFO
Fse
Fcs

Largest Detection Bandwidth
Largest Detection B.W Skew
Largest Detection Bandwidth
Variation With Supply Voltage
Largest Detection Bandwidth
Variation With Temperature

B.W

Typ

Max

Unit

.4.75

5.0
7
12
35

9.0
10
15

V
. mA
mA
mW

100

500
35±60
0.7

2

KHz
ppmfOC
%N

14
2
±1

18
3
±5

%offo
OAl of fo
oAlN

RL=20K

RL=20K
OOC to 700C

10

B.Ws
. B.Wv

4.75-6.75V

B.Wt

Input Resistance

RIN
V1N-1

Fastest On-Off Cycling Rate
Output Leakage Current

Min

POD

Smallest Detectable
Input Voltage
Largest No Output
Input Voltage
Greatest Simultaneous
Outband Signal To Inband
Signal Ratio
Minimum InPllt Signal to
Wideband Noise Ratio .

Test Conditions

20
IL =100mA. fi=fo

V1N-2
S1/Sd

S2/Sd
.. FoUT
leo

20
10

RL=20k
V IN =300mVRMS
fi=fo=100KHz
fi 1 =140KHz
fi 2 =60KHz
RL=20K
V1N =25mVRMS

mVrms
mVrms

+6

dB

-6

dB

f0/20
0.01

Output Saturaton Voltage

IL =30mA. V1N =25mVrms
It =100mA. V1N =25mVrms

0.2
0.6

Output Fall Time
Output Rise Time

TF
TR

RL=50
RL=50

30
150

SAMSUNG SEMICONDUCTOR

Kohm
25

15

VSIQ'"1
VSIQ'"2

c8

%fOC

±0..1

25

pA

0.4

V
V

1.0

nS
nS

240

LM567C

LINEAR .INTEGRATED CIRCUIT

CIRCUIT DESCRIPTION

BLOCK DIAGRAM

The LM567C monolithic tone decoder consists of a phase detector, low
pass filter, and current controlled oscillator which comprise the basic
Output 1
Filter
phase-locked loop, plus an additional low pass filter and quadrature
detector enabling detection on in-band signals. The device has a
low Pass
normally high open collector output capable of sinking 100 mAo
Loop Fitte, 2
The input signal is applied to Pin 3 (20 kO nominal input reSistance). Free
running frequency is controlled by an RC network at Pins 5 and 6 and
can typically reach 500 kHz. A capacitor on Pin 1 serves as the output
filter and eliminates out-of-band triggering. PLL filtering is accomplished
with 'a capacitor on Pin 2; bandwidth and skew are also dependant upon
the circuitry here. Bandwidth is adjustable from 0% to 14% of the center
frequency. Pin 41s +Vcc (4.75 to 9V nominal, 10V maximum); Pin 7 is
ground; and Pin 8 is open collector output, pulling loW when an in-band
signal triggers the device.

I

Fig. 1

DEFINITION OF LM567C PARAMETERS
CENTER FREQUENCY fo
fo is the free-running frequency of the C L controlled oscillator with no input signal. It is determined by resistor R, between
pins 5 and 6, and capacitor C, from pin 6 to ground fo can be approximated by
fo=_1_

R,C,

where R, is in ohms and C, is in farads.

LARGEST DETECTION BANDWIDTH
The largest detection bandwidth is the largest frequency range within Which an input signal above the threshold voltage will cause a logical zero state at the output. The maximum detection bandwidth corresponds to the lock range of the PLL.

DETECTION BANDWIDTH (BW)
The detection bandwidth is the frequency range centered about fo, within which an input signal larger than the threshold
voltag/il (typically 20mVrms) will cause a logic zero state at the output. The detection bandwidth corresponds to the 'capture
range of the PLL and is determined by the low-pass bandwidth filter. The bandwidth of the filter, as a percent of fo, can
be determined by the approximation

where V; is the input signal in volts, rms, and C~ is the capaCitance at pin 2 in I'F.

DETECTION BAND SKEW
The detection band skew is a measure of how accurately the largest detection band is centered about the center frequency,

fo. It is defined as (fmax +fm;n -2fo)lIo, where fmax and Im;n are the frequencies corresponding to the edges of the detection
band. If necessary, the detection band skew can be reduced to zero by an optional centering adjustment.

c8SAMSUNG SEMICONDUCTOR

241

LINEAR INTEGRATED CIRCUIT

LMS67C
PIN DESCRIPTION
OUTPUT FILTER -

C3 (Pin 1)

Capacitor C3 connected from pin 1 to ground forms a simple low-pass post detection filter to eliminate spurious outputs
due to out-of-band signals. The time constant of the filter can be expressed as T3 =R3C3, where R3 (4.7kG) is the internal
impedance at pin 1.
The precise value of G3 is not entical for most applications. To eliminate the possibility of false triggering by spurious
signals, it is recommended that C3 be 2: 2 C2, where C2 is the loop filter capacitance at pin 2.
If the value of C3 becomes too large, the turn-on qr turn-off time of the output stage will be delayed until the voltage
change across C3 reaches the threshold voltage. In certain applications, the delay may be desirable as a means of
suppressing spurious outputs. Conversely, if the value of C3 is too small, the beat rate at the output of the quadrature detec.
tor may cause a false logic level change at the output. (Pin 8)
The average voltage (during lock) at pin 1 is a function of the inband input amplitude in accordance with the given transfer
characteristic.

LOOP FILTER -

C2 (Pin 2)

Capacitor C2 connected from pin 2 to ground serves as a single pole, low-pass filter for the PLL portion of the LM567C
.
The filter time constant is given by T2 =R2C2, where R2 (10 kG) is the impedance at pin 2.
The selection of C2 is determined by the detection bandwidth requirements. For additional information see section on
"Definition of LM567C Parameters".
The voltage at pin 2, the phase detector output, is a linear function of frequency over the range of 0.95 to 1.05 fa, with
a slope of approximately 20 mVl% frequency deviation.

INPUT (Pin 3)
The input signal is applied to pin 3 through a coupling capacitor. This terminal is internally biased at a dc level 2 volts
above ground, and has an input impedance level of approximately 20 kG

TIMING RESISTOR Rl AND CAPACITOR C1 (Pins 5 and 6)
. The center frequency of the decoder is set by resistor R, between pins 5 and 6, and capacitor C, from 'pin 6 to ground,
as shown in Figure 3.
.pin 5 is the oscillator squarewave output which has a magnitude of approximately Vee - 1.4V and an average dc level
of Vee/2. A 1 kG load may be driven from this point. The voltage at pin 6 is an exponential triangle waveform with a peakto-peak amplitude of 1 volt and an average dc level of Vecl2. Only high impedance loads should be connected to pin 6
avoid disturbi.ng the temperature stability or duty cycle of the oscillator.
.

LOGIC OUTPUT (Pin 8)
Terminal 8 provides a binary logic output when an input signal is present within the pass-band of the decodef. The logic
output is an uncommitted, "base-collector" power transistor capable of switching high CJrrent loads. The current level at
the output is determined by an external load resistor, RL , connected from pin 8 to the positive supply.
When an in'band signal is present, the output transistor at pin 8 saturates with a collector voltage less than 1 volt (typically
0.6V) at full rated current of 100 mAo If large output voltage swings are needed, Rl can be connected to a supply voltage,
V+, higher than the Vee supply. For safe operation, V+ :s; 20 volts.

c8

SAMSUNG SEMICONDUCTOR

242

LM567C

LINEAR INTEGRATED CIRCUIT

OPERATING INSTRUCTIONS
SELECTION OF EXTERNAL COMPONENTS
A typical connection diagram for the LM567C is shown in Figure 3. For most applications, the following procedure will
be sufficient for determination of the external components At, Ct, C2 , and C3 •
1. At and Ct should be selected for the desired center frequency by the expression fa =l/AtCt. For optimum temperature
stability, At should be selected such that 2kO, and the AtC t product should have sufficient stability over the projected
operating temperature range.
2. Low-pass capacitor, C 2 , can be determined from the Bandwidth versus Input Signal Amplitude graph of Figure 7.
One approach is to select an area of operation from the graph, and then adjust the input level and value of C2 accordingly. Or, if the input amplitude variation is known, the required foC2 product can be found to give the desired bandwidth.
Constant bandwidth operation requires V,>200mV rms. Then, as noted on the graph, bandwidth will be controlled
solely by the foC2 product.
3. Capacitor C 3 sets the band edge of the low-pass filter which attenuates frequencies outside of the detection band and
thereby eliminales spurious outputs. If C3 is too small, frequencies adjacent to the detection band may switch the output
stage off and on at the beat frequency, or the output may pulse off and on during the turn-on transient. a typical
.
minimum value of C 3 is 2 C2 •
Conversely, if C3 is too large, turn-on and turn-off of the output stage will be delayed until the voltage across C3 passes
the threshold value.

PRINCIPLE OF OPERATION
The LM567C is a frequency selective tone decoder system based on the phase-locked loop (PLL) principle. the system
is comprised of a phase-locked loop, a quadrature AM detector, a voltage comparator, and an output logic driver. The four
sections are internally interconnected as shown in Figure 1.
When an· input tone is present within the pass-band of the circuit, the PLL synchronizes or "locks" on the input signal.
The quadrature detector serves as a lock indicator: when the PLL is locked on an input signal, the dc v'oltage at the output of
the detector is shifted. This dc level shift is then converted to an output logic pulse by the amplifier and logic driver. The
logic driver is a "bare collector" transistor stage capable of switching 100 mA loads.
The logic output at pin 8 is normally in a "high" state, until a tone that is within the capture range of the decoder is present
at the input. When the decoder is locked on an input signal, the logic output at pin 8 goes to a "low" state.
The center frequency of the detector is set by the free-running frequency of the current-controlled oscillator in the PLL.
This free-running frequency, fa, is determined by the selection of At and C t connected to pins 5 and 6, as shown in
Figure 3. The detection bandwidth is determined by the size of the PLL filter capacitor, C2; and the output response speed
is controlled by the output filter capacitor, C3

c8

SAMSUNG SEMICONDUCTOR

243

II

LINEAR INTEGRATED CIRCUIT

LM567C
TYPICAL CHARACTERISTICS (Fig. 2)

TYP. BW YS T~PERATURE

CENTER FREQ. YS TEMPERATURE

14

-

12

8

.....

6_

.....;

4_

r--..

2

-is

0

7&

25

-

100

TEIIPEIW'UIII rei

BW YS CENTER FREQUENCY

.........

o
10

12

14

100

18

aw~allO)

11(

--lIII0
101(

CURRENT DRAIN VB.

BW (Ca. C3 CHARCt)

~
~~

~ t':

""

1001<

111

w::c

I

JI

f'\ t\ea

~ ["-....
f'\ 1'-1"--l"'- t-

2"

c8

4

10

12

14

SAMSUNG SEMICONDUCTOR

18

244

LMS67C'

LINEAR INTEGRATED CIRCUIT
OUTPUT SATURATION VOLTAGE
VB AMBIENT TEMPERATURE

OPERATING CYCLE VB BANDWIDTH
1000
500

"-

"\A
"\

50

"

v~.5v,L~

-t-

1.0

~-

1 _ -- - ' -

D.8

II: Bandwidth IImII8d bV c.- B: BandWidth Ilmllod bV
external resistor
(MInimum Ca)

~ r--

f\.

~r'\ ~

" t\..

"-

20
10

I'\.
0,2

"'

10

50

20

---,...
, -25

100

L_100mA

V

IL_30mA

25

/

50

---

75

II

/"
100

BANDWIDTH ("C)

BANDWIDTH (1Ma 01 10)

AC TEST CIRCUIT
+5V

LM567C

Yin

+5V

fi=100KHz
Note: Adjust for fo=1OOKHz
Fig. 2

c8

SAMSUNG SEMICONDUCTOR

245

(d) Frequency Doubler

AL

8
6

3

5

lSL
AL

./

c8

Al =6.8K to 15K
R2-4.7K
A3=20K

SAMSUNG SEMICONDUCTOR

'C2~

10

~Cl

246

LM567L

LINEAR INTEGRATED CIRCUIT

MICROPOWER TONE DECODER
8 DIP

The LM567L is a micropower phase-locked loop (PLL) circuit designed
for general purpose tone and frequency decoding. In applications requiring very low power dissipation, the LM567L can replace the popular 567 type decoder with only minor component valu~ changes. The
LM567L offers approximately 1I1Oth the power dissipation of the conventional567 type tone decoder, without sacrificing its key features such as
the oscillator stability, frequency selectivity, and detection threshold.
Typical quiescent power dissipation is less than 4mW at 5 volts.

8 SOP

I

FEATURES
• Very low power dissipation (4mW at 5V)
..
•
•
•
•
•
•

Bandwidth adjustable from 0 to 14% of fo
Logic compatible output with 10mA current sinking capability.
Highly stable center frequency_
Center frequency adjustable from 0.01 Hz to 60KHz.
Inherent immunity to false signals.
High rejection of out-of-band signals and noise.
Frequency range adjustable over 20:1 range by external resistor.

APPLICATIONS
• BaHery-oPllrated tone detection • Touch-tone decoding
• Sequential tone decoding
• Communications paging
• Ultrasonic remote-control
• Telemetric decoding

ORDERING INFORMATION
Device

Package

LM567LN

8 DIP

LM567LD

8 SOP

Operating Temperature
0-+ 70·C

SCHEMATIC DIAGRAM

·c8

SAMSUNG SEMICONDUCTOR

247

LINEAR INTEGRATED CIRCUIT

LMS67L

=

, ABSOLUTE MAXIMUM RATINGS (Ta 25°C)
Characteristic

' value

Symbol

Power Supply
Power Dissipation
Plastic Package
Derate Above +25°C
Operating Temperature
Storage Temperature

Unit

Vee

10

V

Pd

300
2.5
0- +70
-65 - +150

mW
mWfOC
°C
°C

Topr'
Tstg

ELECTRICAL CHARACTERISTICS
(Vee = +5V, T. = 25°C, unless otherwise specilied.)
Characteristic

Symbol

Supply Voltage Range

Vee

Supply Current/Quiescent

Icc>,

Supply Current/Activated

leC>2

Highest Center Frequency

Hlo

Te,st Conditions

Min

Typ

Max

Unit

8.0

V

0.6

1.0

0.8

1.4

mA
mA

4.75
RL=20KO,
' RL =20KO, V'N =300mV, I, =10
R1=3KO- 5KO

10

60

KHz

-150

ppml°C

Center Frequency Drift
Temperature
0200mVrms. Then, as noted on the graph, bandwidth will be
.
controlled solely by the fa C2 product.
3. Capacitor C3 sets the band edge of the low-pass filter which attenuates frequencies outside of the detection band
and thereby eliminates spurious outputs. If C3 is too small, frequencies adjacent to the detection band may switch
the output stage off and on at the beat frequency, or the output may pulse off and on during the turn-on transient.
A typical minimum value for C3 is 2 C2.
Conversely, if C3 is too large, turn-on and turn-off of the output stage will be delayed until the voltage across C3
passes the threshold value.

PRECAUTIONS
1. The LM567L will lock on signals near (2n+l) fa and produce an output for signals near (4n+ 1) fa, for n=O, I, 2 etc.
Signals at 5 fa and 9 fa can cause an unwanted output and should, therefore, be attenuated before reaching the input
of the circuit.
.
2. Operating the LM567L in a reduced bandwidth mode of operation at input levels less than.200mVrms results in
maximum immunity to noise and out-band signals. Decreased loop damping, however, causes the worst-case lock-up .
time to increase, as shown by the graph of Fig 13.

c8

SAMSUNG SEMICONDUCTOR'

252

LM567L

LINEAR INTEGRATED CIRCUIT

3.

Bandwidth variations due to changes in the in-band signal amplitude can be eliminated by operating the LM567L
in the high input level mode, above 200mV. The input stage is then limiting, however, so that out-band signals or high
noise levels can cause an apparent bandwidth reduction as the in-band signal is suppressed. In addition, the limited
input stage will create in-band components from subharmonic signals so that the circuit becomes sensitive to signals at fo/3, f0l5 etc.
4. Care should be exerc'ised in lead routing and lead lengths should be kept as short as possible. Power supply leads
should be properly bypassed close to the integrated circuit and grounding paths should be carefully determined to
avoid ground loops and undesirable voltage variations. In addition, circuits requiring heavy load currents should be
provided by a separate power supply, or filter capacitors increased to minimize supply voltage variations.

OPTIONAL CONTROLS
PROGRAMMING
Varying the value of resistor R1 and/or capaCitor C1 will change the center frequency. The value of R1 can be changed
either mechanically or by solid state switches. Additional C1 capacitors can be added by grounding them through saturated
npn transistors.

SPEED OF RESPONSE
The minimum lock-up time is inversely related to the loop frequency. As the natural loop frequency is lowered, the turn-on
transients becomes greater. Thus maximum operating speed is obtained when the value of capaCitor C2 is minimum. At
the instant an input Signal is applied, its phase may drive the oscillator away from the incoming frequency rather than toward
it. Under this condition, the lock-up transient is in a worst case situation, and the minimum theoretical lock-up time will not
be achievable.
The follOWing expressions yield the values of C2 and C3, in microfarads, which allow the maximum operating speeds
for various center frequencies where fa is Hz.
13
C2= - ,
fa

26
C3=

fa

Jl.F

The minimum rate that digital information may be detected without losing information due to turn-on transient or output
. chatter is about 10 cycles/bit, which corresponds to an information transfer rate of f0/10 baud. In situations where minimum
turn-off is of less importance than fast turn-on, the optional sensitivity adjustment circuit of Fig 5 can be used to bring
the quiescent C3 voltage closer to the threshold Voltage. Sensitivity to beat frequenCies, noise, and extraneous signals,
however, will be increased.

+V
+V

a1I
LM567L

1

R

DECREASE
SNESITIVITY
RA

LM567L

LM567L

1-'-'-1'-~~-~:
5DK

C3

DECREASE
SENSITIVITY

, .

INCREASE
SENSITIVITY

INCREASE
SENSITIVITY
SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
(OPTIONAL)

Fig. 5. Adjustable Sensitivity Connections

ciS

SAMSUNG SEMICONDUcroR

253

I

LM567L

LINEAR INTEGRATED CIRCUIT

CHATTER
When the value of C3 is small, the lock· transient and ac components at the lock detector output may cause the output
stage to move through its threshold more than once, resulting in output chatter.
Although some loads, such as lamps and relays will not respond to chatter, logic may interpret chatter as a series of output
signals. Chatter can be eliminated by feeding a portion of the output back to the input (Pin 1) or, by increasing the size of
capacitor C3. Generally, the feedback method is preferred since keeping C3 small will enable faster operation. Three
. alternate schemes for chatter prevention are shown in Fig 6. Generally, it is only necessary to assure that the feedback time
constant does not get so large that it prevents operation at the highest anticipated speed.
+v

+V

RL

LM567L

+v

i~~·'"

RL

LM567L
C1

8

~C3

RI'
100K

1

~C3

+V

R

10~K

RL

LM567L r8--t~-'

Fig. 6. Methods of Reducing Chatter

SKEW ADJUSTMENT
The circuits shown in Fig 7 can be used to change the position of the detection band (capture range) within the largest
detection band (lock range). By moving the detection band to either edge of the lock range, input signal variations will expand
the detection band in one direction only, since R3 also has a slight effect on the duty cycle, this approach may be useful to
obtain a precise duty cycle when the circuit is used as an oscillator.

IL~_I'

+V

+V

L
--. 1

LOWERSfo
R2

R1

LM567L

LM567L

51(

50K
lC2

RAISES 10
A3
1.0K

RAISESfo
SILICON
DIODES FOR
TEMPERATURE
COMPENSATION
(OPTIONAL)

<

Fig. 7. Detection Band Skew Adjustment

.c8

SAMSUNG

SEMICONDU~R

254

LM567L

LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS
FIG 8. SUPPLY CURRENT
V. SUPPLY VOLTAGE

FIG 9. LARGEST DETECTION BANDWIDTH
V. OPERATING FREQUENCY

3. 0

15

1'\
"'-

2.5
NO LOAD "ON"

~

I 2. 0

i!§'

u

~

V

1. 5

,//"

~

II:
i

CURREN~

°vV

1.

/V

II

~SCENT CURRENT

o.

5 --

o

•

10

100Hz

10Hz

SUPPLY VOLTAGE - VOLTS

1KHz

10KHz

100KHz

CENTER FREQUENCY

FIG 10. DETECTION BANDWIDTH
V. A FUNCTION OF C2 AND C3

FIG 11. BANDWIDTH Vs INPUT SIGNAL
AMPLITUDE (C2 IN ~F)

2W~--~~~~---+---+---r---r--~

C3
C2

16

10

BANDWIDTH - % OF to

FIG 12. BANDWIDTH VARIATION
WITH TEMPERATURE
1.
400

12.5
12

200

10

100

i!:
"

I

8

75

6
5.0

2.5

•
rOWTTH
2

AT!25 0 C

o
-75

c8

-50

-25

1'\

300

:2

t

25
50
TEMPERATURE,oC

14

16

FIG 13. GREATEST NUMBER OF
CYCLES BEFORE OUTPUT

15.0

~ 10.0

12

BANDWIDTH - % of to

- -r--

50

---t---

30

75

100

SAMSUNG SEMICONDUCTOR

125

1'\

l:\. '"

I

BANDWIDTH UMITED BY C2

'\l\.

~

"I

40

BANDWIDTH LIMITED BY

EXTESNAL RESISTOR-

I'Vt l 11
MuM

20
10
1

3 • 5

~
10

2J

20

1

30 4050

100

BANDWIDTH", 0110)

255

LM567L

LINEAR INTEGRATED CIRCUIT
FIG 15. TYPICAL CENTER FREQUENCY DRIFT
WITH TEMPERATURE(V cc 5V,Rl 80kIJ,fo 1KHz)

FIG 14. POWER SUPPLY DEPENDENCE'
OF CENTER FREQUENCY

=

1.2
1.1
1.0

0.9

5'

I

0.8

I

f------

il

I

=

I

1-

..........

'\

100

Ii

0.7

I 0.6

~

=

100

0.5

~

0.4

~ -200

1/

IE

~-309

I

0.3
0.2

f\

\

d
·w

-400

0:1

o
0.1

2

0.2 0.3 0.4 0.5

3

45

10

-500
-25.

o·

25

50

75

TEMPERATURE, ·C

CENTER FREQUENCY - KHz

FIG 16. TYPICAL FREQUENCY DRIFT
AS A FUNCTION OF TEMPERATURE

cti:
r--fo_1KHz

"""';;;:::

f'\ "'\I\.

\

V+=5V

-4
-25

c8

25
TEMPERATURE, ·C I

50

SAMSUNG SEMICONDUCTO!=I.

75

256

MC1488

LINEAR INTEGRATED CIRCUIT

QUAD LINE DRIVER
The MC1488 is a monolithic quad line driver designed to interface data
terminal equipment with data communications equipmen,t in conformance with the specifications of EIA Standard No. RS-232C.

FEATURES
Current Limited Output: ± 10mA typ
Power-Off Source Impedance: 300 Ohms (min)
Simple Slew Rate Control with External Capacitor
Flexible Operating Supply Range
Compatible with OTL and TTL, HCTLS Families

•
•
•
•
•

SCHEMATIC DIAGRAM

I

(1/4 of Circuit Shown)

vee 14

300
OUTPUT
PIN 6,8,11 or3

GND7

ORDERING INFORMATION
Device

Package

MC1488N

14 DIP

MC1488D

14 SOP

Operating Temperature
0-

+ 70·C

J
10K
70

VEE 1

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C unless otherwise noted)
Characteristic

~

Symbol

value

Unit

Power Supply Voltage

Vee
VEE

+15
-15

VDe

.

Input Voltage Range

V'R

-15sV,R s7.0

Voc

Output Signal Voltage

VD

::1:15

Voc

Power Dissipation

Po

1000

mW'

1/RllJA

6.7

mWJOC

Ta

0-+70

°C

Tstg

-65-+150

°C

Derate Above Ta = + 25°C
Operating Temperature Range
Storage Temperature Range

c8

SAMSUNG SEMICONDUCTOR

257

LINEAR INTEGRATED CIRCUIT

MC1488
ELECTRICAL CHARACTERISTICS
(Vcc~9.0±1%V, VEE~-9.0

± 1%V, Ta~0-70°C unless otherwise noted)

Characteristic

Symbol

Input Current 1

I'L

Input Current 2

I'H

Test Conditions

Min

' Low Logic State (V'L ~O)

Unit

Fig

1.0

1.6

mA

1

10

/LA

1

V

2

V

2

(V'H~5.0V)

VOH

V'L ~0.8V, RL ~3.0K(l
Vee~13.2V, VEE~-13.2V

V'H~1.9V, RL~3.0K(l
Vee~9.0V, VEE~-9.0V

Output Voltage-Low Logic State

Max

High Logic State
V'L ~0.8V, RL ~3.0K(l
Vce~9.0V, VEE~ -9:0V

Output Voltage-High Logic State

Typ

VOL

V,~~1.9V, RL~3.0K(l
Vee~13.2V, VEE~-13.2V

6

7

9

10.5

-6

-7

-9

-10.5

Output Short Circuit .current

108+

Positive

6

10

12

mA

3

Output Short Circuit Current

108-

Negative

-6

-10

-12

mA

3

Output Resistance

Ro

Vee~VEE~O, Vo~

Positive Supply Cur~ent(RL=oo)

lee

±2.0V

300

!l

V'H~1.9V, Vee~+9.0V

15

V'L~0.8V, Vcc~

4.5

6

V'H~1,9V, Vce~+12V

19

25

V'L=0.8V, Vce=+12V

5.5

7

+9.0V

20

12

V'L=0.8V, Vee=+15V
-13

V'H=1.9V, VEE=-9.0V

-17

Power Consumption

-18

V'H=1.9V, VEE =-12V

Pe

mA

-15

p.A

-23

mA

-15

p.A

V'L =0.8V, VEE = -9.0V
lEE

5

34

V'H= 1.9V, Vee = + 15V

Negative Supply Curren't (RL=QO)

mA

V'L=0.8V, VEE = -12V
V'H=1.9V, VEE =-15V

-34

mA

V'L=0.8V, VEE =-15V

-2.5

mA

Vee~9.0V,

333

VEE=-9.0V

Vee = 12V, VEE,," -12V

5

mW

576

* MaximLim packa'ge power dissipation may be exceeded if all outputs are shorted simultaneously.

SWITCHING CHARACTERISTICS
(Vee=9.0±1%V, VEE =-9±1%V, Ta=0-25°C)
Characteristic

Typ

Max

Unit

Fig

ZL =3.0K and 15pF

275

350

nS

6

ZL =3.0K and 15pF

45

75

nS

6

ZL =3.0K and 15pF

55

100

nS

6

ZL =3.0K and 15pF

110

175

nS

6

Symbol

Test Conditions

Propagation' Delay Time

tpLH

Fall Time

tTHL
trLH

Rise Time
Propugation Delay Time

c8

tpHL

SAMSUNG SEMICONDUCTOR

Min

258

MC1488

LINEAR INTEGRATED CIRCUIT

DC TEST CIRCUIT
FIGURE 1 INPUT CURRENT

FIGURE 2 OUTPUT VOLTAGE

+1.9V

J
3K
VIL

1

+5V

FIGURE 3 OUTPUT SHORT CIRCUIT CURRENT
Vee

FIGURE 4 OUTPUT RESISTANCE (POWER OFF)

VEE

+1.9V

L

vee
±2Vdc
±6mAMax

ciS

SAMSUNG SEMICONDUCTOR

259

II

LINEAR INTEGRATED CIRCUIT

MC1488

FIGURE 5 POWER SUPPLY CURRENTS

+1.9V

J

MC1488

VIL
+0.8V

Vee

FIGURE 6 SWITCHING RESPON~E

-"':""""'-i------'OVO

VINO~-D---1--3K

15PF

vo----tTHL and ItTLH Measured 10% to 90%

c8

SAMSUNG .SEMICONDUCTOR .

260

LINEAR INTEGRATED CIRCUIT

MC1488
TYPICAL PERFORMANCE CHARACTERISTICS
FIGURE 7 - TRANSFER CHARACTERISTICS
V. POWER-SUPPLY VOLTAGE

FIGURE 8 - SHORT CIRCUIT OUTPUT CURRENT
V. TEMPERATURE

+12
+9.0

r-

V"'r'r-r

+6D

- - -- - -

Vcc=6V, VEE'''''-6V

f-- r-

--

--

Vcc-9V, VEE--9V

r-- -

II

V'~VO
3K

-9D
-12~

o

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8 2.0

__~__~__~~__L -__L-__L -__~

-55

+125

T, TEMl>ERATURE ("ell

FIGURe 9 - OUTPUT SLEW RATE V. LOAD
- CAPACITANCE

1000____.
__
i

+75

+25

V", INPUT VOLTAGE (V)

FIGURE 10 - OUTPUT VOLTAGE
AND CURRENT LIMITING CHARACTERISTICS

10 _ __
-

~
w

Iii
II:

~~
5 ===
~ _ V~I,'I~II
r
10

m

IIIWI!

IIIII

10

to L--J....l.1J..Lll1111JJ..-.J-J
1111..LU1.lJJL----L.J..LLllJJl------,-J---LJ--WJlI
to
10
10DOQ
1,000
_1>., CAPACITANCE (pF)

-16 -12

-8.0

-4.0

+4.0

+8.0

+12

+16

Vo, OUTPUT VOLTAIlE'(V)

FIGURE 11 - MAXIMUM OPEATING TEMPERATURE
V. POWER SUPPLY VOLTAGE

,.

"

14

~

12

I

~ 10

Vee'

ian

.&;3

~

6.0

iii

4_0

i

2D

>

........

3K

ti

OJ

Hi

""

.~
T

,

I

-55

I

+25

+75

+125

T, TEMPERATURE ("ell

c8

SAMSUNG SEMICONDUCTOR

261

. LINEAR INTEGRATED CIRCUIT

MC1488
APPLICATION INFORMATION

The Electronic Industries Association (EIA) RS232C specification detail the requirements for the interface between data
processing equipment and data communications equipment. This standard specifies not only the number and type of interface
leads, but also the voltage levels to be used. The MCl488 quad driver and its companion circuit; the MC1489/A quad receiver,
provide a complete interface system between DTL or TTL logic levels and the RS232C defined levels. The RS232C requirements as applied to drivers are discussed herein .
• The required driver voltages are defined as between 5 and 15-volts in magnitude and are positive for a logic "0" and negative
for a logic "1". These voltages are so defined when the drivers are terminated with a 3000 to 7000-ohm resistor. The MC1488
meets this voltage requirement by converting a DTUTTL logic level into RS232C levels with one stage of inve~ion.
The RS232C specification further requires that during transitions, the driver output slew rate must not exceed 30 volts per
microsecond. The inherent slew rate of the MC1488 is much too fast for ~his requirement. The current limited output of the
FIGURE 12 - SLEW RATE Vs CAPACITANCE
FORlsc=10mA
1000 _

_

100
._.

l

w

Ii
a:

~

OJ

10

C, CAPACITANCE (PF)

device can be used to control this slew rate by connecting a capacitor to each driver output. The required capacitor can be
easily determined by using the relationship C=los x tSf/AV from which Figure 12 is derived. Accordingly, a 33O-pF capacitor on each output will guarantee a worst case slew rate or 30 volts per microsecond.
The interface driver is also required to withstand an accidental short to any other conductor in an interconnecting cable.
The worst possible signal on any conductor would be another driver using a plus or minus 15-volt, 500-mA source. The MCl488
, is designed to indefinitely withstand such a short to all four outputs in a package as long as the power-supply voltages are
greater than 9.0 volts (Le., Vcc~9.0 V:VEE~-9.0V). In some power-supply deSigns, a loss of system power causes a low
impedance on the power-supply outputs. When this occurs, a low impedance to ground would exist at the power inputs to
the MC1488 effectively shorting the 3OO-ohm output resistors to ground. If all four outputs were then shorted to plus or minus
15' volts, the power dissipation in these resistors would be excessive. Therefore, if the system is designed to permit low
o-....-""'T"----~-~ - ,- -----'1"'----

¢M

~

: MCl48s-1

: r--,

I

I

I

o-:-1 __,P-:-<>
o-+-{-~I_-o

o-t-i .._~

1

o-~--r ••-.,

:

o-~--r""

!

o-~- {. __,P-t--o

Fig. 13 - Power supply protection to
meet power-off fault conditions

o-i-.L_}>I-o
" ' __ r ___ J

VEE

1

7.~

+,

O-M--':":-'-~-----'-'-'-+--------:~.!-..L- ----

c8

SAMSUNG SEMICONDUCTOR

262

LINEAR INTEGRATED CIRCUIT

MC1488

impedances to ground at the power-supplies of the drivers, a diode should be placed in each power-supply lead to prevent
overheating in this fault condition. These two diodes, as shown in Figure 8, could be used to decouple all the driver packages in a system. (These same diodes will allow the MC1488 to withstand momentary shorts to the i25-volt limits specified
in the earlier Standard RS232B.) The addition of the diodes also permits the MC1488 to withstand faults with power-supplies
of less than the 9.0 volts stated above.
The maximum short-circuit current allowable under fault conditions is more than guaranteed by the previously mentioned
10mA output current limiting.

Other Applications
The MC1488 is an extremely versatile line driver with a myriad of possible applications. Several features of the drivers
enhance this versatility:
1. Output Current Limiting - this enables the circuit designer to define the output voltage levels independent of power'supplies and can be accomplished by diode clamping of the output pins. Figure 14 shows the MC1488 used as a DTL to MOS
translator where the high-level voltage output is clamped one diode above ground. The resistor divider shown is used to reduce
the output voltage below the 300mV above ground MOS input level limit.
2. Power-Supply Range - as can be seen from the schematic drawing of the drivers, the positive and negative driving
elements of the device are essentially independent and do not require matching power-supplies. In fact, the positive sup-.
ply can vary from a minimum seven volts (required for driving the negative pulldown section) to the maximum specified 15
volts. The negative supply can vary from approximately -2.5 volts to the minimum specified the positive or negative supplies as long as the current output limits are not exceeded. The combination of the current-limiting and supply-voltage features allow a wide combination of possible outputs within the same quad package. Thus if only a portion of the four drivers
are used for driving RS232C lines, the remainder could be used for DTL to MOS or even DTL to DTL translation.Figure 15
shows one such combination.
FIGURE 14DTLITTL-TO-MOS TRANSLATOR

FIGURE 15 LOGIC TRANSLATOR APPLICATIONS

+12V

IJTL
MOSOUTPUT
(WITH VsS~GND)

DTL
TTL
INPUT

lK
10K

DTL
NAND ......... I - l -.....J:H--<,......---,>----'-f'--O DTL OUTPUT
GATE
-O.7V 10 +5.7V
INPUT
CTL
M.HTL
INPUT

-12V

-12V

D--+-o--,..---r--O RTL OUTPUT
-O.7V to +3.7V

INPUT

DTL
MOS
INPUT

TYPICAL APPLICATION
+12V
LINE DRIVER
MC1488

INTERCONNECTING. LINE RECEIVER
CABLE
MC1489

-12V

PIN CONNECTIONS

...r--'~...r--,0- TTLlDTL

TTLlDTL -I

-L __ /

"1- __ "

I

I

I-I

I

I

I

--l
I

I

INTERCONNECTING
CABLE

c8

SAMSUNG SEMICONDUCTOR

263

II

MC1489/MC1489A

LINEAR INTEGRATED CIRCUIT

QUAD LINE RECEIVER
'14 DIP

The MC1489 monolithic quad line receivers are designed to interface
data terminal equipment with data communications equipment in conformance with the specifications of EIA Standard No. RS-232C.

FEATURES
• Input Resistance - 3.0KO to 7.0KO
• Input Signal Range - ± 30 Volts
• Response Control
a) Logic Threshold Shifting
b) Input Noise Filtering
• Input Threshold Hysteresis Built in

14

SOP

SCHEMATIC DIAGRAM
(1/4 OF CIRCUIT SHOWN)

r---....-~--Ov~

14
9K

1.6K

ORDERING INFORMATION

RESPONSE
RF
CONTR0lO---_p----...."N\,....-+---;
Pins 2, 5, 9, 12

Device
MC1489N
OUTPUT
Pins3,S,8,n

3.55K

INPUT
Pins 1, 4, 10, 13

MC1489AN
MC1489D
MC1489AD

Package Operating Temperature
14 DIP

0-+ 7Q·C
14 SOP

10K

7

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)
Characteristic
~er

Supply Voltage

Symbol

Value

Unit

Vee

.10

Voc

Input Voltage Range

V'R

±30

Voe

Output Load Current

IL

20

mA

Po
1/IJJA

1000
6.7

mW
mWI"C

T.

Oto +70

°C

Power Dissipation
Derate Above T. = + 25"C
Operating Temperature
Storage Temperature

ciS

SAMS,-!NG SEMICONDUCTOR'

Tstg

-65 to +150

°C

264

LINEAR INTEGRATED CIRCUITS

MC1489/MC1489A
ELECTRICAL CHARACTERISTICS
(Vee =5.0± 10%V, Ta =0 _70°C unless otherwise noted)

Characteristic

Test Conditions

.Symbol

Positive Input Current

Min

V,H =25Vdc

3.6

V,H =3.0Vdc

0.43

r---'

I'H

-3.6

r-'

I'L

Input Turn-On Thereshold Voltage
MC1489
MC1489A

""

..

1.0
1.75

_--- r----

Ta=25°C, VOH 2: 2.5V,
ic=O.5mA

. Output Voltage High

VOH

V,H =0.75V,IL=-0.5mA
Input Open, IL = - 0.5mA

Output Voltage Low

VOL

V,L =3.0V,IL=10mA

Output Short Circuit Current

8.3
mA

~--.

~--

-8.3

mA

Ta=25°C, VOL s 0.45V

V'L

Input Turn-Off Threshold Voltage

--

Unit

-0.43

V'L = -3.0Vdc

V,H
..

1----

Max

"- - - -1 - - -f----

V,L =-25Vdc

Negative Input Current-

TYP

1.5
2.25

Vdc

1.25

Vdc

4.0
4.0

5.0
5.0

Vdc

1.95

--

0.75
2.5
2.5

los

Power Supply Current

lee

All gates "on", lOUT =OmA,
V'H=5.0V

Power Consumption

Pe

V'H=5.0V

I--.

0.2

0.45

Vdc

-3.0

-4.0

mA

16

26

mA

80

130

mW

TYP

Max

Unit

25
120
25
10

85
175
50
20

nS
nS
nS
nS'

SWITCHING CHARACTERISTICS
(Vee=5.0±1%V, Ta =25°C, See Fig. 1)

Characteristic
Propagation Delay Time
Rise Time
Propagation Delay Time
Fall Time

Symbol

Test Conditions

Min

RL=3.9KO
RL=3.9KO
RL=3900
RL=3900

tpLH
IrLH
tpHL
IrHL

TYPICAL APPLICATION
PIN CONNECTIONS
LINE DRIVER
MC1488

INTERC0NNEcriNG

LINE RECEIVER
MC1489

...r---~--""t
TTLlDTL-=!. __

~>

~

L-/

... __ ..~ TTLlDTL

InputA 1
Response
ControlA 2
12 Response
Control 0

I

I

I

--;

!

:

I

r--

I

I

INTERCONNEcrlNG
CABLE

c8 SAMSUN~

SEMICONDUCTOR

Response
ControlB

Inpu1C

9 Response
Comrol C
Ground 7

8 OutputC

265

II

MC1489/MC1489A

LINEAR INTEGRATED CIRCUIT

TEST CIRCUIT
SWITCHING RESPO~SE

Fig 1 -

Fig 2 -

RESPONSE CONTROL NODE
VR

R
~----~----~~----VO

Vln

~
O%

Vin

+3V

Jr

C~

CL

RESPONSE NODE

Von --~1/4-:--1

50%

tPHL

_ _ . - - - - - - - . Vo

MCI489A

tPlH

ITLH and ITHL

vo

C; capacitor is for noise filtering
R. relstor Is for threshold shifting

measured

10%-90%

. CL _15pF=total parasitic capacitance, which includes
probe and wiring capacitances ,

TYPICAL PERFORMANCE CHARACTERISTICS
(Vcc=5.0 Vdc Ta = + 25°C unless otherwise noted)

Fig. 4 - TYPICAL TURN-ON THRESHOLD V.
CAPACITANCE FROM RESPONSE CONTROL PIN 10
GND

Fig. 3 - TYPICAL TURN-ON THRESHOLD V.
CAPACITANCE FROM RESPONSE CONTROL PIN 10
GND

MC1489

~

• I------'\---+---+-----'lrl-------\

~

i3~~~~~r+--~

IL-~--=:::~~
10

100

1000

PW, INPUT PULSE WIDTH (..,

c8

SAMSUNG SEMICONDUCTOR

10.000

10

100

1000

10,000

PW, INPUT PULSE WIDTH (nl,

266

LINEAR INTEGRATED CIRCUIT

MC1489/MC1489A

MC1489 INPUT THRESHOLD
VOLTAGE ADJUSTMENT

Fig. 6 Fig. 5 -INPUT CURRENT
+10

6.0

+8.0
5D

+6.0

./

V

1./

/'

AT

AT

5K

13K

AT

AT

~

11K

V"

V,h

v"

+5V

+5V

-5V

YEO
AT

if, VIII

./

/'

-6D

Y

-6.0

-

'-

L-

VILH

:::

V,HL

~

-10
-25-20

-15

-10
VIN,

-5.0

0

+5.0

+10 +15

+20 +25

-3.0 -2.0 -1.0

INPUT VOLTAGE (V)

Fig. 7 - MC1489A INPUT THRESHOLD
VOLTAGE ADJUSTMENT

-

2.
22

5D

...

iw
A,

AT

5K

~r·

11K

v"

V"

+5V

-5V

AT

V"

~
g
0

20
18
16

,.

6X

12

II:

10

....
....
:J

DB

[3
X

-

0-

V,LH

-30 -20 -10

0

=

V'Hl

+3.0 +2.0 +10

Fig. 8 - INPUT THRESHOLD VOLTAGE
VB. TEMPERATURE

8.0

AT

0

VI, INPUT VOLTAGEi(V)

--r--

MC1489A V,LH

r-- - I -

-

~VIt-l

r--

MC1489V,LH

MC1489A VlI..H

il! 0.6

ii

I--

> 0.4
0.2

+10 +20 +30 +40

-60

VI, INPUT VOLTAGE (V)

+120
T, TEMPERATURE (Ge)

Fig. 9 -INPUT THRESHOLD VB.
POWER SUPPLY VOLTAGE
2.0

V,HLM 1489A

V,HL MC1489
V,LH MC1489
VllH

MC1489A

,.

o

o

'D

c8

12

6.0

Vee POWER SUPPLY VOLTAGE

M

SAMSUNG SEMICONDUCTOR

267

MC14891MC1489A

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION
General Information
The Electronic Industries Association (EIA) has released the R8-232C specification detailing the requirements for the interface between data processing equipment and data communications equipment. This standard specifies not only the number
and type of interface leads, but also the voltage levels to be used. The MC1488 quad driver and its companion circuit, the
MC1489 quad receiver, provide a complete interface system between OfL or TTL logic levels and the R8-232C defined levels.
The RS-232C requirements as applied to receivers are discussed herein.'
.
The required 'input impedance is defined as between,30oo ohms and 7000 ohms for input voltages between 3.0 and 25
volts in magnitude; and any voltage on the receiver input in an open circuit condition must be le,ss than 2.0 volts in magnitude. The MC1489 circuits meet these requirements with a maximum open circuits meet these requirements with a maximum open circuit voltage of one VeE.
The receiver shall detect a voltage between -3.0 and -25 volts as a Logic "1" and inputs between +3.0 and +25 volts
as a Logic "0". On some interchange leads, an open circuit of power "OFF" condition (300 ohms or more to ground) shall
be decoded as an "OFF" condition or Logic "1". For this reason, the input hystereSiS thresholds ofthe MC1489 circuits are
all above ground. Thus an open or grounded input will cause the same output as a negative or Logic "1" input.

Device Characteristics
The MC1489 interface receivers have internal feedback from the second stage to the input stage providing input hysteresis for noise rejection. The MC1489 input has typical turn-on voltage of 1.25 volts and turn-off of 1.0 volt for typical hysteresis of 250mV. The MC1489A has typical turn-on of 1.95 volts and turn.-off of 0.8 volt for typically t 15 volts of hysteresis.
'Each receiver section has an external response control node in addition to the input and output pins, thereby allowing the
designer to vary the input threshold voltage levels. A resistor can be connected between this node and an external powersupply. Figures 2, 6 1and 7 illustrate the input threshold voltage shift possible through this technique.
This response node can also be used for the filterin!) of high-frequency, high-energy noise pulses. Figures 3 and' 4 show
typical noise-pulse rejection for external capacitors of various sizes.
These two operations on the response node can be combined or used individually for many combinations of interfacing
applications. The MC1489 circuits are particularly useful for interfacing between MOS circuits and OfLffTL logic systems.
In this application, the input threshold voltages are adjusted (with the appropriate supply and resistor ,values) to fall in the
center of the MOS voltage logic levels. (See Figure 9).
The response node may alSo be used as the receill6r input as long as the designer realizes that he may not drive this node
with a low impedance source to a voltage greater than one diode above ground or less than one diode below ground. This
feature is demonstrated in Figure10 where two receivers are slaved to the same line that must still meet the RS-232C
impedance requirement.

c8

SAMSUNG SEMICONDUCTOR

268

MC1489/MC1489A

LINEAR INTEGRATED CIRCUIT

Fig. 10 - TYPICAL TRANSLATOR APPLICATION - MOS TO DTL OR TTL

+5Vdc

.

r---...\

R

--1L. ___..."
OTL or TIL
r .. - .....

---l

,

II

+svdclrh'

Fig. 11'- TYPICAL PARALLELING OF TWO MC1489/A RECEIVERS TO MEET RS-232C

Vcc
RESPONSE CONTROL PIN"

r- - ---------- - - --I

i

1/2 MC1489

. . . . .-t<'

IN'~PU~T~_;'8:,:K~.Li-'----~+-H_

OUTPUT

vcco--+----------,
OUTPUT
INPUT

8K

RESPONSE CONTROL PIN

J
I

I
I
I
IL _______________________ JI

ciS SAMSUNG SEMICONDUCTOR

269

LINEAR INTEGRATED. CIRCUIT

MC3361

16 DIP

LOW POWER NARROW BAND FM IF
The MC3361 is designed for use in FM dual conversion communication
equipment. It contains a complete narrow band FM demodulation system
operable to less than 2.SV supply voltage.
.

FEATURES
16 SOP

• Includes: Oscillator, Mixer, limiting Amp, Quadrature Discriml·
nator, Active Filter, Squelch, Scan Control, and'Mute Switch
• Stable operation with wide supply voltage (2.5V to 7.0V)
• Low drain current (4.0mA "lYP. at Vcc =4.0V)
• Excellent Input Sensitivity
(-3dB limiting, 2.0"Vrms "lYp.)
• Minimum number of external parts required.

ORDERING INFORMATION
BLOCK DIAGRAM

Device

Package

MC3361N

16 DIP

MC3361D

16 SOP

Operating Temperature
-20

-+ 10·C

SQUELCH TRIGGER WITH
HYSTERESIS

·DEMODUlAlOR

Fig. 1

c8

SAMSUNG SEMICONDUCTOR

270

MC3361

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta =25°C)
Characteristic
Supply Voltage
Detector Input Voltage
Input Voltage (Vcc;;,4.0V)
Mute Function
Operating Temperature
Storage Temperature

value

Unit

10
1.0
1.0
-0.5- +5.0
-20- +70
-65- + 150

V
Vp.. p
Vrms
Vpeak
°C
°C

Symbol
Vcc
Vo
V'6
V'4
Top.
TSIg

II

ELECTRICAL CHARACTERISTICS
(Vee =4.0V, fo=10.7MHz, .:If= ± 3KHz, fmod =1KHz, Ta =25°C, Unless Otherwise Specified)

Characteristic

Symbol

Test Conditions

Min

Typ

Max

Unit

lee

Squelch Off
Squelch On

4.0
6.0

mA

Input Limiting Voltage

V,NL

-3dB Limiting

2.0

/LV

Detector Output Voltage

V7

2.0

V

Detector Output Impedance

Zoo

400

ohm

Recovered Audio Output Voltage

Vo

V,N =10mV

100

150

mVrms

Filter Gain

AVF

f= 10KHz, V,N:= 5mV

40

48

dB

Filter Output Voltage

VOF

1.5

V

Trigger Hysteresis

VTH

50

mV

Mute Function Low

ROL

·10

ohm

Mute Function High

ROH

10

Mohm

Scan Function Low

V'31

Mute Off (V'2= 2V)

Scan Function High

V'3H

Mute On (V'2=GND)

Mixer Conversion Gain

AVM

24

dB

Mixer Input Resistance

R,

3.3

Kohm

Mixer Input CapaCitance

C,

2.2

pF

Circuit Current

c8

SAMSUNG SEMICONDUCTOR

0.5

V
V

3.0

271

LINEAR INTEGRATED CIRCUIT

MC3361
PIN CONNECTIONS
Pin 1: Oscillator
Pin 3: Mixer Output
Pin 5: Limiter Input
Pin 7: Limiter Output
Pin 9: Recovered Audio Output
Pin 11: Filter Output
Pin 13: Scan Control
Pin 15: GND

Pin 2: Oscillator
Pin 4: Vcc
Pin 6: Decoupling
Pin 8: Quad Coil
Pin 10: Filter Input
Pin 12: Squelch In
Pin 14: Mute
Pin 16: Mixer Input

'rEST CIRCUIT
vee

1--;---<> MIXER INPUT

MURATA
CFU
4550

1 - - - - - - < > AUDIO MUTE
1 - - - - - - - 0 SCAN CONTROL
MC3361
l - - - - - - < > SQUELCH IN

~--'-tt---o

FILTER OUT

)-+--'II\f¥-'-H--O FILTER IN

1-"""'~1"""---o AF OUTPUT

Quad coil
Tokotype
RMC-2A6597HM

Fig, 2

c8

SAMSUNG SEM,ICONDUCTOR

272

MC3361

LINEAR INTEGRATED CIRCUIT

CIRCUIT DESCRIPTION (see block diagram)

Th~ MC3361 functions include an Oscillator, Mixer, FM IF limiting amplifier, FM demodulator, OP-amp, Scan control and
Mute switch.
The mixer combines the crystal controlled oscillator to convert the input frequency from 10.7MHz to an intermediate frequency of 455KHz, where, after external bandpass filtering, most of the amplification is done. A conventional quadrature
detector is used to demodulate the FM signal. The a of the quad coil, which is determined by the external resistor placed
across it, has multiple affects on the audio output. Increasing the a increases output level because of nonlinearities in the'
tank phase characteristic.
After detection and de-emphasis, the audio output at pin 9 is partially filtered, then buffered by an emitter follower. The
signal still requires voiume control and further amplification before driving loudspeaker.
The op amp inverting input (pin 10) which is internally referenced to 0.7V, receives DC bias from the output of pin 11 through
the external feedback network. It is normally utilized as either a bandpass filter to extrect a specific frequency from th audio
output, such as a ring or dial-tone, or as a highpass filter to detect noise due to no input at the mixer. This information is applied
to pin 12. An external poSitive bias to pin 12 sets up the squelch trigger circuit such that pin 13 is low and the audio mute
(pin 14) is open circuit. If pin 12 is pulled down to 0.5Vdc by the nQise or tone detector, pin 13 will rise to approximately 0.5Vdc
below Vee and pin 14 is internally short circuited to ground. There is 50mV of hysteresis at pin 112 to prevent jitter.;Audio
muting is accomplished by connecting pin 14 to a high-impedance ground-reference'point in the audio path between pin 9
and the audio amplifier.

c8

SAMSUNG SEMICONDUCTOR

273

II

NOTE

,>."

-~, ~ k'

Voltage Regulator
Device

Function
3 AMP Adjustable Positive Voltage Regulator' '
Regulator Pulse Width Modulator
3·Terrninal Positive Adjustable Regulator
3-Terminal Positive Voltage Regulator
Precision Voltage Regulator
Switching Regulator,
3A Positive Voltage Regulator
3·Terrnihal 1A Positive Voltage'Regulator
3·Terrninal Positive Voltage Regulator
3-Terminal 0.5A Positive Voltage Regulator
3·Terrnlnal Negative V.olt;lge Regulator
3·Terrninal 0.5A 'Negative Voltage Regulator

KA350
KA3524 '
LM317
LM323
LM723
KA78540
KA78TXX
MC78XX
~C78LXX

MC78MXX
MC79XX
MC79MXX

Package
TO-3P
16 DIP
TO·220
14 DIP/14 SOP
14 DIP(14 SOP
16 ,DIP
TO·22O
TO·22O
TO·92
TO·22O
TO·22O
TO·220

Page
277
285
291
423 '

300
306
312
323
353
364
377
387

, Voltage ,Reference
KA336·5.0
KA385-1.2
KA431

•

Voltage Reference Diode
Micropower Voltage Reference Diode
Programmable Precision Reference

TO·92
TO·92
TO·9218 DIP/8 SOP

393
397
401

8 DIP/8 SOP
8 DIP/8 SOP
14 DIP/14 SOP
10 SIP HIS
8 DIP/8 SOP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8 SOP/9 SIP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8 SOP/9 SIP
8 DIP/8 SOP
14 DIP/14 SOP
8 DIP/8 SOP/9 SIP
8 DIP/8 SOP/9 SIP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8 SOP/9 SIP

407
407
412
419
421
423
432
438
423
432
438 '
446
423
438
452
456
456
463

Operational Amplifier
KA201 A
KA301A
KA733C
KA9256
KF351
, LM224/A
L"M248
LM2581A
LM324/A
LM348
LM3581A/S
LM741C/ElI
.LM2902
LM2904
MC14581C/S/I
MC3303
MC3403
MC4558C/AC/I

Single Operational Amplifier
Single Operational Amplifier
Differential Video Amplifier
Dual Power Operational Amplifier
Single Operational Amplifier
Quad Operational Amplifier
Quad Operational Amplifier'
Quad Operational Amplifier
Dual Operational Amplifier
Dual Operational Amplifier
Quad Operational Amplifier
Single Operational Amplifier
Quad Operational Amplifier
Dual Operational Amplifier
Dual Operational Amplifier
Quad Operational Amplifier
quad Operational' Amplifier
Dual Operational Amplifier

Voltage Comparator
, KA319
KA3.61
KAnOC
LM211
LM239/A
LM293/A
LM311
LM339/A
LM3931A1S
LM2901
LM2903
LM3302

Dual High Speed Voltage Comparator
High Speed Voltage Comparator
High Speed Voltage Comparator
Voltage Comparator
Quad Differential Comparator
Dual Differential Comparator
Voltage Comparato!
Quad Differential Comparator
Dual Differential Comparator
Quad Differential Comparator
Dual Differential Cpmparator
Quad Differential Comparator

' 14 DIP/14 SOP
14 DIP/14 SOP
14 DIP/14 SOP
8 DIP/8 SOP
14 DIP/14 SOP
8 DIPI8 SOP
·8 DIP/S SOP
14 DIP/14, SOP
8 DIP/8 SOP
14 DIP/14 SOP
S DIP/S SOP
14 DIP/14 SOP

468
472
474
476
481
489
476,
481
489
481
489
481

CMOS Timer
CMOS Timer
CMOS Timer
Timer
Dual Timer
Dual Timer

-8 DIP/8 SOP
8 DIP/8 SOP
14 DIP/14 SOP
8 DIP/8 SOP
14 DIP/14 SOP
16 DIP/16 SOP

496
501
505

Timer'
KS555
KS555H
KS556
NE555
.NE556
NE558

509
513
516

.LINEAR INTEGRATED CIRCUIT

KA350

3 AMP ADJUSTABLE POSITIVE VOLTAGE
REGULATOR

1"O-3P

The KA350 is adjustable 3-terminal positive voltage regulator capable
of supplying in excess of 3.0A over an output voltage range of 1.2V to 33V.
This voltage regulator is exceptionally easy to use and require only two
external resistors to set the output voltage. Further, they employ internal
current limiting, thermal shutdown and safe area compensation, making
them essentially blow-out proof. All overload protection circuitry remains
fully functional even if the adjustment terminal is accidentally
disconnected.

FEATURES
•
•
•
•
•
•
•
•
•
•

Output adjustable between 1_2V and 33V
Guranteed 3A output current
Intemal thermal overload protection
Load regulation typically 0-1 %
Line regulation typically O_005%N
Intemal short-circuit current limiting constant
with temperature.,
.
Output transistor safe-area compensation
Floating operation for high voltage application
Standard 3-lead transistor package
Eliminates stoc~ing many fixed voltages

1: Ad)

II

2: Output 3: Input

ORDERING INFORMATION
Operating Temperature

o -J25~C

BLOCK DIAGRAM

VOLTAGE
REFERENCE

ADJ

c8 ~AM~UNG

SEMICONDUCTOR

PROTECTION
CIRCUITRY

OUT

277

KA350

LINEAR INTEGRATED CIRCUIT

, ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Input-Output Voltage Differential

V,-Vo

35

Vee

Soldering Lead Temperature
(10 Seconds)

T 'ead

300

°C

Power Dissipation

Po

Internally limited

Operating Temperature Range

TI

0- + 125

°C

T.,g

-65-+150

°C

Storage Temperature Range

ELECTRICAL CHARACTERISTICS
(V , - Vo = 5V, 10 = 1.5A, T, = aoc to 125°C; Pmax , unless otherwise speCified)
Characteristic

Test Conditions

,Symbol

Line Regulation

6Vo

Ta=25°C,3V-s.V,-Vo-s.35V
(Note 1)

Load Regulation

6Vo

Ta=25°C,10mA-s.lo-s.3A
Vo-s.5V (Note 1)
Vo~5V (Note 1)

Adjustment Pin Current

lad!

Adjustment Pin Current Change

61",,;

3V-s.V, -Vo -s.35V,
10mA-s.IL-s.3A, PO-s.PMAX

Thermal Regulation

VTAG

Pulse";20mS, Ta=25°C

Reference Voltage

' VAEF

Line Regulation
Load Regulation

3V-s.V, -Vo -s.35V,10mA-s.lo-s.3A

6Vo

3.0V-s.V,- Vo-s.35V

6Vo

10mA -s.lo-s.3.QA
Vo-s.5.0V

Min

1.2

Vo~5.0V

Temperature Stability

Ts

Maximum Output Current

IMAx

, Minimum Load Current
to Maintain Regulation

ILMIN

RMS Noise, % of Vo
Ripple Rejection
Long-Term Stability

Tj=O°C to 125°C

,

Max

Unit

0.005

0.03

%N

5
0.1

25
0.5

mV
%N~

tJA,

50

100

0.2

5.0

0.002

"A

%IW

1.25

1.30

V

0.02

0.07

%N

20
0.3

70
1.5

mV
%\(0

1.0

%Vo

V, -Vo::;10V, PO-s.PMAX

3.0

4.5

A

V, -Vo=30V, PO-s.PMAX, Ta=25°C

0.25

1.0

A

3.5

V,-Vo=35V

VN

10Hz-s.f-s.10KHz, Ta=25°C

RR

Vo =10V, f=120Hz,
without CAOJ
CAOJ = 10"F

S

Typ

Tj =125°C

66

10

mA

0.003

%Vo

65

dB
dB

80
0.3

1

%

Note 1: Regul'ation is measured at constant junction temperature. Changes in output voltage due to heating effects
must be taken into account separately. Pulse testing with low duty cycle is used.

ciS

SAMSUNG SEMICONDUCTOR

278

KA3S0

LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTIC
0.4

tw

"

0.2

i

r"",,-

-

t-5OOmA-

w

...!i;.!:5A

~-O.2
g

T,=25:'(;'-

\

~~

!;-O.4

~

\

05- 0.6

>


1

Fig. 28

284

LINEAR INTEGRATED CIRCUIT

KA3524

REGULATOR PULSE WIDTH MODULATOR
16 DIP

The KA3524 regulating pulse width modulator contains all of the
control circuitry necessary to implement switching regulators of either
polarity, transformer coupled DC to DC converters, transformerless
polarity converters and voltage doublers, as well as other power control
applications. This device includes a 5V voltage regulator capable of
supplying up to 50mA to external circuitry, a control amplifier, an
oscillator(a pulse width modulator, a phase splitting flip-flop, dual
alternating output switch transistors, and current limiting and shut-down
circuitry. Both the regulator output transistor"and each output switch
are internally current limiting and, to limit junction temperature, an
internal thermal shutdown 'circuit is employed.

FEATURES
• Complete PWM power control circuitry
• Frequency adjustable to greater than 100KHz
• 2% frequency stability with temperature
• Total quiescent current less than 10mA
• Dual alternating output switchs for both push-pull or slngle-ended
applications
• Current limit amplifier provides external component protection
• On-chip protection against excessive junction temperllture and
output current
• SV, SOmA linear regulator output available to user
ORDERING

I
INFORMATION
Operetlng Temperature

BLOCK D.IAGRAM

0-70·C
OSCILLATOR
OUTPUT

CURRENT
LIMIT

GROUND
(SUBSTRATE)

Fig_ 1

c8

SAMSUNG SEMICONDUCTOR

285

KA3524

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Input Voltage
Reference Output Current
Output Current (Each Output)
Oscillator Changing Currerit (pin 6 or 7)
Lead Temperature (Soldering, 10 sec)
Power Dissipation
Operating Temperature
Storage Temperature .

VIN
lrel

40
50
100
5
300'
1000
0-+70
-65-+150

V
mA
mA
mA
·C
mW
·C
·C

10
Ic~arge

Tlead
Po
Topr
Tstg

ELECTRICAL CHARACTERISTICS
(YIN = 20V, f = 20KHz, Ta = 0 to 70·C unless otherwise specified)
Symbol

Characteristic
REFERENCE SECTION

Test Conditions

Max

Unit

5.0

5.4

V

Min Typ

.

Output Voltage

Vref

4.6

Line Regulation

Vlln•

VIN =8-40V

10

30

mV

Load Regulation

VIOad

IL =0-20mA

20

50

mV

Ripple Rejection

VRR

f = 120Hz, Ta= 25·C

66

dB

Short-Circuit Output Current

Isc

Vrel=O, Ta=25·C

100

mA

Temperature Stability

0.3
Ta=25·C

Long Term Stability

1

%

20

mV/Khr

350

KHz

OSCILLATOR SECTION
Maximum Frequency

fMAX

Initial Accuracy

CT = 0.001ILF, RT = 2KD .
RT and CT constant

%

5

. VIN =8-40V, Ta=25·C

Frequency Change with Voltage

6f

1

Frequency Change with Temperature

6f

Over operating temperature range

%

2

Output Amplitude (Pin 3)

VA3

Ta=25·C

3.5

%
V

. Output Pulse Width (Pin 3)

V3PW

CT=0.01ILF, Ta=25·C

0.5

ILs

Input Offset Voltage

VIO

VCM=2.5V

2

10

Input Bias Current

liB

VCM=2.5V

2

10

ERROR AMPLIFIER SECTION

Open Loop Voltage Gain
Common·Mode Input Voltage Range
Common·Mode Rejection Ratio
Small Signal Bandwidth
Output Voltage Swing

c8

60

Avo
VCR

Ta=25·C

CMRR

Ta=25·C

BW

Av=OdB, Ta=25·C

Vosw

Ta=25·C

SAMSUNG SEMICONDUCTOR

80

1.8

~

dB
3.4

70

V
dB
MHz

3
0.5

mV

3.8

V

286

KA3524

LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS (Continued)
(V,N=20V, f=20KHz, Ta=0-70°C unless otherwise specified)
Characteristic

Symbol

Test Conditions

Min Typ

Max

Unit

COMPARATOR SECTION
Maximum Duty Cycle

DCm..

% Each output on

Input Threshold (Pin 9)

VTH ,

Zero duty cycle

1

Input Threshold (Pin 9)

VTH2

Maximum duty cycle

3.5

V

1

,.A

Input Bias Current

45

Ie

%
V

CURRENT LIMITING SECTION
'Sense Voltage

V(Pin 2) - V(Pin 1)~50mV
Pin 9=2V, Ta=25°C

Vsense

180

Sense Voltage T.C.

200

220

mV/oC

0.2

Common-Mode Current

0.7

mV

1

V

,0.1

50

,.A

1

2

V

OUTPUT SECTION (EACH OUTPUT)
Collector-Emitter Voltage

VCEO

Collector Leakage Current

ILKQ

VcE =40V

Saturation Voltage

VSAT

IC=50mA

40

Emitter Output Voltage

VE

V'N =20V,

Rise Time (10% to 90%)

tr

Fall Time (90% to 10%)

tf

ISTD

Total Standby Current

17

V

18

V

RC=2KIl, Ta=25°C

0.2

,.s

RC=2KIl, Ta=25°C

0.1

,.s

V'N=40V, PINS 1, 4, 7, 8,11
and 14 are grounded, Pin 2=2V
All other inputs and
outputs open

5

10

mA

APPLICATION INFORMATION
Voltage Reference
An internal series regulator provides a nominal 5 volt output which is used both to generate a reference voltage
and is the regulated source for all the internal timing and controlling circuitry. This regulator may be bypassed
for operation from a fixed 5 volt supply by connecting pins 15 and 16 together to the input voltage. In this configuration,
thE> maximum input voltage is 6.0 volts.
This reference regulator may be used as a 5 volt source for other circuitry. It will provide up to 50mA of current
itself and can easily be expanded to higher current with an external PNP as' shown in Figure 2.
EXPANDED REFERENCE CURRENT CAPABILITY

VREF

+

10~J ~E~~~~~G ON

CHOICE FOR 0,

GNDo---------------+-------~-o

Fig. 2

i8

SAMSUNG SEMICONDUCTOR

287

II

LINEAR INTEGRATED CIRCUIT

KA3524
Oscillator

The oscillator in the KA3524 uses an external resistor (RT) to establish a constant charging c;urr!!nt into an external
capacitor (CT). While this uses more current than a series connected RC, it provides a linear ramp voltage on the
capacitor which ,is also used as a reference for the comparator. The charging current is equal to 3.6V + RT and
should be kept within the range of approximately 30~ to 2mA, i.e., 1.SK-1rr","'-..---~-o Vo = 5V
SA/SB

1
IMAx=Rs
Isc =

As
VTH

VOR2
VTH + R, + R2
where

VTH =200mV
+

Foldback current limiting can be used to reduce
power dissipation under shorted output conditions
Fig. 5

c8

SAMSUNG SEMICONDUCTOR

289

II

KA3524

LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS
OUTPUT STAGE DEAD TIME AS A FUNCTION
OF THE TIMING CAPACITOR VALUE

OSCILLATOR PERIOD AS A FUNCTION OF R., AND Or

,0

III

8

5

I

~ 2

/

~

" 1.0

~

/'

V

_V/"

~

§ 0.5
0.3

.001

.002

.005

.01

.02

10

.05

TIMING CAPACITOR VALUE(C,~.F

20

50

100

200

500 lmS 2mS

OSCILLATOR PERIOD·,.s

Fig••

Fig. 7

AMPLIFIES OPEN·LOOP GAIN AS A FUNCTION
OF FREQUENCY AND LOADING ON PIN 9

80

RL_30m["
RL =1MO

RL=300KO

"'"

.....

RL=100KO

'"'""\

R..=30Kll

20

R,=RESISTANCE FROM PIN 9 TO GROUND

10

100

lK

10K

lOOK

FREOUENCY (liz)
Fig. 8

c8

""

1M

SAMSUNG SEM.ICONDUCTOR

10M

290

LM317

. LINEAR INTEGRATED CIRCUIT

3-TERMINAL POSITIVE ADJUSTABLE
REGULATOR

TQ.220

The LM317 is a 3-terminal adjustable positive voltage regulator capable
of supplying in excess of 1.SA over an output voltage range of 1.2V to
37V. This voltage regulator is exceptionally easy to use and requires
only two external resistors to set the output voltage. Further, it employs
internal current-limiting, thermal-shutdown and safe area compensation,
making it essentially blow-out proof. The LM317 serves a wide
variety of applications including local, on-card regulation. This device
also makes an especially simple adjustable switching regulator, and a
programmable output regulator, or by connecting a fixed resistor between the adjustment and output, the· LM317 can be used as a precision current regulator.

II

FEATURE
•
•
•
•

Output current In excess of 1.SA
Output adjustable between 1.2V and-37V
Internal thermal·overload protection
Internal short·clrcult current·limiting constant with
temperature
~ Output transistor safe·area compensation
• Floating operation for high·voltage applications
• Standard 3·pin transistor packages

1: Adj 2: Output 3: Input

ORDERING INFORMATION
Operating Temperature
Q-12S0C

SCHEMATIC DIAGRAM
3

............-------------r-----r----,...-.Q.v'N

'---~--~---1---...--

Rll

c8

SAMSUNG SEMICONDUCTOR

291

LM317

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Symbol

Value

Unit

'VIN-VOUT
TIOad
Po
Tj
T.tg

40
230
Internally limited
to +125
-65 to +150

Voc
°C

Characteristic
Input-Output. Voltage Differential
Lead Temperature
Power Dissipation
Operating Temperature Range
Storage Temperature Range

-

o

°C
°C

ELECTRICAL CHARACTERISTICS
(VIN-VOUT=5V, IOUT=0_5A, 0·CsT(:i;;125°C, Imax =1 ..5A, Pmax =2QW, unless otherwise specified)
Characteristic

Line Regulation

Symbol

/,;Vo

Test Conditions

Typ

Max

Unit

Ta=25°C
3V S,VIN - VouTs,40V

0.01

0.0,4

%N

3V SVIN - VouT s40V

0.02

0.07

%N

5
0.1

25
0.5

mV
,%Vo

20
0.3

70
1.5

mV
%Vo

50

100

p.A

0.2

5

",A

1.25

1.30

V

Min

Ta= 25°C, 10mAslouTs,IMAX
VoUT s,5V
Load Regulation

/,;Vo

VouT~5V

10mAs,louTS IMAx
VoUT s,5V
VouT~5V

Adjustable Pin Current
Adjustable Pin Current Change

Reference Voltage
Temperature Stability

lAo.
2.5V S,VIN - VoUT s,40V
10mAs, louTs, IMAx
PSPMAX

/';IAo.

• 3V SVIN - VoUTs40V
10mAs, louTs, IMAX
POS,PMAX

VREF

0:7

Ts

Minimum Load Current to
Maintain Regulation

IL(min)

Maximum Output Current

IMAx

RMS NOise, % of VOUT
Ripple Rejection

Long-TermStability, Tj = Thigh
Thermal Resistance Junction to Case

c8

1.20

VIN-VOUTS15V, POSPMAX
VIN - VOUT = 40V, POS,PMAX

eN

Ta=25°C,10Hzs,fs,10KHz

RR

VouT=10V, f=120Hz
without CAo.
CAOJ = 10p.F

S
Rs\Jc

SAMSUNG SEMICONDUCTOR

"

3.5

VIN-VOUT=40V

Ta=25°C for end pOint
measurements

1.5
0.15

66

%Vo
10

mA

2.2
0.4

A

0.003

%Vo

65

dB

80
0.3
5

l'

%1KHRS
°CIW

292

LM317

. LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS
LOAD REGULATION

ADJUSTMENT CURRENT
80

- --k -O.5A

t--..

/

1c=1~

---

~

VIN=15V
Vwr=1OV

-0.8

-1.0

~

I---"

o

25

50

75

~

100

125

o

25

DROPOUT VOLTAGE

50

75

125

100

TEMPERATURE ("C)
fig. 2

TEMPERATURE ("C)
fig. 1

TEMPERATURE STABILITY
1,260

6VQIf=100mV

£~5~---+----~----~---+--~

I~ -----r----t---~~::~::~~~~
Ii
1.5

50

100

75

.

>1.240

. 1.0 L-__--L____...1...____L -__-L__- - I

25

1,230

1,2Z

125

a

RIPPLE REJECTION

o

25

50
75
TEMPERATURE l°c)
fig. 4

100

125

RIPPLE REJECTION

l00r----,----,-----,----,----,

I

Il =5OOmA

t---------t------t-----j-- VIN = 15V

c..,,=lo,.F

Vwr

eo

80

.~

"- r-....

.........

I

TEMPERATURE ,0Cl
fig.

100

- r--.

1,250

~cl

~--~-_=+=-j.,l;=-i!OO""!------:

o

£

·1

t------:A="""~

=10Y

Tj = 25°C

I

~ ~O

I t------t------t------'1~~._t_------J
50

i
f-- V.. -Vaur:5V

40

1----+----+----1I-~rl_~~

zl----+----+----1I---~.-~

Io.~-

1= 120Hz
Tp_as-C

o

o

I

I
m

~

Z

25

~

OUTPUT VOLTAGE (VI
fig. I

ciS

SAMSlJNG SEMICONDUCTOR

~

o1~0-----,,~oo-----:',K:----...J,O':-:K---::,OOK=--~,M
FREQUENCY (IbI
fig. •

293

LM317

LINEAR INTEGRATED CIRCUIT
-OUTPUT IMPEDANCE

RIPPLE REJECTION
10'

100

e V . 15V
!==V"",=lOV

.... ~

80

r-

~~

IIi
I

f'...CAD.J=10p,'F

III

t--

/

T.=25°C

~CADJ=O

20

V

t-- 1L =500mA
l()O

V

C.r.DJ=o/

10- 1

,./
10- 2

/

/c... =10,F

V1N =15V
Voor=1OV
f= 120Hz

T. = 25°C

o

lllU

10- 3

0.1

0.01

1

10

10

lK

100

OUTPUT CURRENT (A)
FIg. 7

10K

lOOK

1M

FREQUENCY (Hz)
fig. 8

LOAD TRANSIENT RESPONSE

LINE TRANSIENT RESPONSE
1.5

i

I
I
C -1"F; C = 10"F

~€ 1.0

gz

~ ~ 0.5

o

CI

0

lit

~\

L

CL=O; CADJ=O

-0.5

...

ADJ

rr

-1

Vour:::: 1OV
-1.0

-2

r-- Tk=50mA
=25·C
1

10

c8

20
TIME!..)
FIg. 8

30

SAMSUNG SEMICONDUcrOR

1,5

iil

1.0

~

0.5

CL = 11'F; CAD.!

=1O/A.F

1\

VIN= 15V
VOUT=10V _
INL=50mA

\J

-3

!E

~,=0;1... =d~

T.=25·C

1
L

1\

II

\

10

20

30

TIME (oS)
Fig. 10

294

LM317

LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATIONS
AC Voltage Regulator

Current Limited 6V Charger

VIN

120

9V TO 60V
6Vp-p

~

.

'L..J

II

• Sets peak current (0.6A for 10)
•• The 1000,.F is recommended to filter out
input transients

Fig. 11
12V Battery Charger

Fig. 12

R2
• Rs-sets output impedance of charg~r louT Rs (1 + R1)
Use of Rs allows low charging rates with fully
charged battery.

=

Fig. 13

c8

SAMSUNG SEMICONDUCTOR

295

LM323
3~TERMINAL

LINEAR INTEGRATED CIRCUIT
POSITIVE VOLTAGE REGULATOR
T(I.3I'

The LM323 is a three-terminal positive regulator with a preset 5Voutput
and a load driving capability of 3 Amps.
New circuit design and processing techniques are used to provide the
high output current without sacrificing the regulation characteristics of
lower current devices.
.

FEATURES
•
•
•
•

3 Amp output current
Intemal current and thermal limiting
0.010 typical output Impedance
7.5 minimum Input voltage

1: Input 2: GND 3: Output

ORDERING INFORMATION
Operating Temperature

SCHEMATIC DIAGRAM'

0-125°C

INPUT

j

1

t-

REFERENCE
VOLTAGE

OUTPUT

-r-<>3

SOA
PROTECTOR

CURRENT
GENERATOR

STARTING
CIRCUIT

SERIES
PASS
ELEMENT

ERROR
AMPLIFIER

I
THERMAL
PROTECTION

'[

I---

GND

2

Fig. 1

c8

SAMSUNG SEMICONDUCTOR

, 296

LINEAR INTEGRATED CIRCUIT

LM323
. ABSOLUTE MAXIMUM RATINGS
Characteristic
Input Voltage
Operating Temperature Range
Storage Temperature Range

Symbol
Vc
Top,
TS1g

Value

Unit

20
0- +125
-65- +150

V
°C
°C

ELECTRICAL CHARACTERISTICS

Characteristic

Output Voltage

Symbol

Vo

Test Conditions

Min

Typ

Max

TJ-25°C
VIN = 7.5V, loUT=O

4.8

5

5.2V

7.6VsVIN s15V
OsIOUTs3A, Ps30W

4.75

Unit

5.25

V

5

25

rmJ

25

100

rmJ

20

mA

Line Regulation

I1Vo

TJ=25OC
7.5VsVIN s15V

Load Regulation

I1Vo

TJ =25°C, VIN
Os louTs3A

Quiescent Current

Id

7.5VsVIN s15V
OslouTs3A

12

Output Noise Voltage

VN

TJ=25OC,
10Hz s f s 100KHz

40

Short Circuit Current

TJ =25"C, VIN=15V

3

A

lac

TJ=25OC, VIN =7.5V

4

A

3

OCIW

Thermal Resistance
Junction to Case

c8

eJC

SAMSUNG SEMICONDUCTOR

=7.5V

p.Vrmo

297

I

LINEAR .INTEGRATED CIRCUIT.

LM323
Fig. 2

Fig. 3

MAXIMUM AIIEfIAGE POWER OISSIPATION

OUTPUT IMPEDANCE

10'

==\).:'~

cl.,,1'I~

t

---r~:,,~

-~

.

r--

V1N -

/

1

.
'0

......

......
,

,

10K

100K

1M

FREQUENCY (HzI

Fig. 5 SHORT CIRCUIT CURRENT

PEAK _1LABi.E OUTPUT CURRENT

,.1....,

'K

'00

T.-_ENT~("CI

Fig. 4.

'DINTALUM

~

r-YIN-15V
I
(THE~IAAL EFFECI)

Tj-,26OC

T,_,25"C ~

............

o

~ ~.......

,

~

o
10

6 .

15

5

20

Fig. 6
80

7

VlN.,ovT
IL-O,

-

~N-1(JY,k.':;--

J

20

INPUT 1IOLTAGE (Y)

Fig. 7

RIPPLE REJECTION

/

'6

10

....UTVOLTAIII!(Y)

.....
"

---

OROPOUT VOLTAGE

25

CL.lo,.F

I

-"LUM
saUD

\

~ ~ ::- .......

Il-3A

!

.........

(THERMAL EFFECI)

1\

1\

IL-1A

E3;;: :::::

CL.,Y
o

20

1

10

100

lK

10K

100K

1M

-75 -SO

-25

0

25

50

75

100

125 160

JUNCI'ION TEMPERATURE ("CI

c8

SAMSUNG

SEMIC()ND~CTOR

298

LINEAR INTEGRATED CIRCUIT

LM323
Fig. 8
75

OUTPUT VOLTAGE

5.15

~

50

Fig. 9

LINE TRANSIENT RESPONSE

IL01501
CL o o.1,F

5.10

TI_ZSC'C

\

I.......

V

I--

VI.JJV
IL_2Or'nA:

....

-r-. ........

/

-75 -50

-25

0

25

50

75

........ ~

100

I

125 150

TEMPERATURE rei

TIllE"",

Fig. 10 QUIESCENT CURRENT

Fig. 11 LOAD TRANSIENT RESPONSE

14

1°55"C
12

/

r

025'C

I

1)0125'C
--!CL 0 1o,.F
SiiLIO 1l\N'1lWJM

I,
/

o

~
~,

V1N_10\f
1)025'C

I/CL o o.1,F

I

J

o

12

18

20

INPUf VllLU. (VI

Fig. 12

o
TIlE"",

OUTPUTNOISEVOLTAGE

1D

.........

01
10

100

1K

10K

FREQUENCY (Hz)

c8

SAMSUNG SEMICONDUCTOR

299

LINEAR INTEGRATED CIRCUIT,

LM723
PRECISION VOLTAGE REGULATOR

14 DIP

The LM723 is a monolithic integrated circuit voltage regulator featuring
high ripple rejection, excellent output and load regulation, excellent
temperature stability, and low standby current.

FEAT,URES
•
•
•
•

Poslt,ive or Negative Supply Operation.
0.01 % line and load regulation
Output voltage adjustable from 2 to 37 volts.
Output current to 150mA without extemal pass transistor

BLOCK DIAGRAM

14 SOP

•

FREQUENCY
COM PENS
11
Vc

TEMP,'
COM PENS
ZENER

~~

ORDERING INFORMATION

0.. Ii;
Ulr;;

wz
a:~
~I-

10

+----t-OVo

Vre ,

Fig. 1 '

3

1

Device

Package

LM723CN

14 DIP

LM723CD

14 SOP

LM7231N

14 DIP

LM7231D

14 SOP

Operating Temperatura
O-+70·C

-25-+85°C

9

_ Vec NON
CURRENT CURRENT Vz
·INVERT
LIMIT SENSE
INPUT
+Vcc

.vc

OUTPUT

Vz
FREQUENCY
COMPENSATION
CURRENT
LIMIT
CURRENT
SENSE

Vre,

NON - Vee INVERtING
INVERTING
INPUT
INPUT
'

Fig. 2

c8

SAMSUNG SEMICONDUCTOR

300

LM723

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Pulse Voltage from V + to V - (50ms)
Conti nus Voltage from V + to V Input-Ou.tput Voltage Differential
Maximl!m Output Current
Differentia) Input Voltage
Voltage Between Non-Inverting Input and VCurrent from Vz
Current from VREF
Power Dissipation
LM7231
Operating Temperature Range
LM723C
Storage Temperature Range

VIN(P)
VIN
VIN-VO
10
VID
VIE
Iz
"IREF
Po

50
40
40
150
±5
8
25
15
1000

Vpeak
V
V
mA
V
V
mA
mA
mW
·C
·C
°C

Top,
T" g

~25-+85

0-+70
-65-+150

I

ELECTRICAL CHARACTERISTICS
(unless otherwise specified, Ta=25·C, VI =Vee =Ve=12V, Vo = +5V, IL=1.0mA, Rsc=O, CI=100pF,
Cref=O and devider impedance as seen by error Amplifier:s10KIl connected as shown in figure3)

Characteristic

Line Regulation

Symbol

6V o

Test Conditions

LM7231/LM723C

Min

VI =12V to 15V
VI = 12V to 40V

6Vo

Ripple Rejection

RR

Average Temperature Coefficient of
Output Voltage
Short Circuit Current Limit
Reference Voltage
Output Noise Voltage
Long-term Stability

0.03

f = 100Hz to 10KHz, CREF = 0

74

f = 100Hz to 10KHz, CREF = 5/4F

86

TMIN:sTA:sTMAl'

Ise

Rse =101l, Vo=O

VREF

%

0.2
0.6

65
6.80

f = 100Hz to 10KHz, CREF = 0
f - 100Hz to 10KHz, CREF - 5/4F

7.15

. %/·C
mA

7.50

20

V
/4V rrns

2.5
0.1

VolT

%

dB

0.003 0.Q15

%/1000HR
4.0

mA

40

V

2.0

37

V

3.0

38

V

10

Input Voltage Range

VI

9.5

Output Voltage Range

Vo

Input-Output Voltage Differential

Vo

c8

0.1
0.5

Unit

0.3

Standby Current Drain

• Note: TMIN = O°C for LM723C
= -25°C for LM7231

0.Q1
0.1

TMIN:sTA:sTMAX
10= 1 to 50mA

6Vo/6T

VN

Max

TMIN:sTA:sTMAX
VI =12V to 15V
10= 1mA to 50mA

Load Regulation

Typ

IL=O, VIN =30V

2.3

TMAX = 70°C for LM723C
:; 85°C for LM7231

SAMSUNG SEMICONDUCTOR

301

LM723

LINEAR INTEGRATED· CIRCUIT

Table 1 - Resistor values (KO) for standard output VOltage

Output
Voltage

Applicable
Figures

+3
+5
+6
+9
+12
+15
+28

3,6
3,6
3,6
4,6
4,6
4,6
4,6

Fixed Output Output Adjustable
:i:5%
:i:10%
R,

Ra

R,

P,

Ra

4.12
2.15
1.15
1.87
4.87
7.87
21

3.01
4.99
6.04
7.15
7.15
7.15
7.15

1.8
0.75
0.5
0.75
2
3.3
5.6

0.5
0.5
0.5
1
2
1
1

1.2
2.2
2.7
2.7
3
3
2

Applicable
Figures

Output
Voltage

Fixed Output Output Adjustable
:i:5%
:i: 101141
R,

-6"
-9
-12
-15
-28

5
5
5
5
5

3.57
3.48
3.57
3.65
3.57

'~

2.43
5.36
8.45
11.5
24.3

R,

P,

Ra

1.2
1.2
1.2
1.2
1.2

0.5
0.5
0.5
0.5
0.5

0.75
2
3.3
'4.3
10

Note: *Vee must be connected to a +:r.I or greater supply.

Table II - Formulae for Intermediate output voltages
Outputs from + 2 to + 7 volts
Fig. 3

Vo"[V""X~1

Foldback Current Limiting
Vo ~ + VSENSE (As + ~) I
Aae ~
Aoc ~

A, + R:!

ISHORTCKT

Outputs from + 7 to + 37 volts
Fig. 4,6
Vo =

c8

IV"" x A,+A2 )
A2

Current Limiting

IKNEE _ [

= [VSENSE x ~+~l

Roc

ILiMIT

= VSENSE
Aae

R.

Output from - 6 to - 250 volts
Ag.5
Vo"

[~""x·A'~A21;~

..

SAMSUNG SEMiCoNDUCTOR

,

'"

~

302

LM723

LINEAR INTEGRATED CIRCUIT

APPLICATION INFORMATION
Basic low voltage regulator (Vo .. 2 to 7V)

Basic high voltage regulator (vo,. 7 to 37V)

+

~r
Fig. 3

I

Fig. 4

Note: R3=R1 0 R21(R1+R2) for ninlmum tamperalur8 drift.
Note: R1 o R2/(R1+R2)for minimum temperature drift.
R3 may be eliminated for minimum component count.
R3 may be eliminated for minimum component count.

'JYpIca1 performance
Regulated Output 'obltage .......................................... SV
Line Regulation (4VI=3V) ..................................... O.5mV
Load Regulation (4Io .. S0mA) ................................ 1.5mV

Negative voltage regulator
VI

~ical

performance
Regulated Output 'obltage............................ :............ 1SV
Line Regulation (4Vi=3V) ..................................... 1.5mV
Load Regulation (4Io-50mA) ................................ 4.5mV

FosItive voltage regulator
(Extenal NPNPass Transistor)

Fig. 5

Fig. 6

lYPIcal performance
•
Regulated output 'obltage ................................. :.......-1SV
Line Regulation (4VI-3V) ........................................ 1mV
Load Regulation (4Io-100mA) ................................. 2mV

c8

SAMSUNG SEMICONDUCTOR

~ical performance
Regulated Output Voltage ...................................... +1SV
.Line Regulation (4VI =3V) ..................................... 1.5mV
Load Regulation (4Io=1A) ...................................... 1SmV

303

LM723

LINEAR INTEGRATED QRCUIT

Maximum output current va. voltage drop

Current limiting cheracterl8llcs

(

v.

(y)

U

I,

111.1211

f - - RSC.101l

~ r-~ g

.• ••

8

2r---+-~+++H~---r-+~bH+H

• {!

I2

2r---+-~+++H~---r-+~~+H

"~--~2~-4~~8~8~~~--~2~~4~8~8

0

. 'Fig. 7
vw. (y)
Current limiting characterl8llca va. .
junction temperature
........
f-0.7

10
lmAI

~

•

80

.~

--t--'

......

CUmlnt

I-- 00;;;;;; Rae-lOll
I

,

,

I

,

I

-•

--

i'.

~
Ii:

;

I

I
U

, --

t---. t-..

,
(

120

~)

1

T••ooo

r-. ~

.........

~R

r::::: ~ _

-0.'

Ta.25OC

!

80
-G.2

40

I

(

0

i

I

I,

t

IolmAI

AVtN•

CUmlnt

f - - r--Rae-i

80

Fig. 8
Load regulation cherecterl8llc8 without
current limiting

180

~" -.....;: ~

40

-u

• FIg. 9 80
...
TJ('C)
Load regulation charac:terlsllcs with
current limiting
.

I

I

;

I

i

i

i
I

,i

I

!

!
I
•
~g. 1(/'1
.80
1o(mAI
Load regulation cIIerecterIatIc with
current limiting
I

o

4.VeN.
~)

o

..... ""-

-II1II

~~

1- -:-

......;

-

~ r--..

-0.1

Ta.25"C_

...... ~

o

VO.5V111.1211
Rae.101l

....... ~
~

-0.1

'\

,

T._'~ ~

\ '\

-0.15

VO.5V
i-- r-- VI.I211
Rae.101l
-0.2

.~

-o.a
Ta.l25"C
Ta.

-lUll

o

5

10

15

•

Fig. 11

cB

SAMSUNG SEMICONDUCTOR

-

-G.4

o

•

40

\
\

~
80

80

,,(mAl

Fig. 12

304

LM723

LINEAR INTEGRATED CIRCUIT
LIne regulation - voltage drop

Load regulation - voltage drop

lNoN.
~)

VO-5V

0..

Rsc-O

10=lmAto~A_

"Vi-~

--r-

o

0.1

-

'-

1 1-

V1_12V

VO-5V
RSC-O
IO-lmA

0.2

V

~

........

-1.1

........

..

-u

1

111

IS

35

Vi.., (VI

5

15

25

Fig. 13

l1li

YIe(VI

Fig. 14

Line transient response

Quiescent drain current va. Input voltage
IN.
(M/)

Id

(rnA)

I~PUt~

VOJViiiI I-10-0

4

IN,
(VI

I
II

4

2

o

2

./

2

ra-O'C
ra-25"C
ra-7O"C

-::::: ::::::

/'

V

o

~~

I'

-

........

........

-

Out ullmltage

V

V1-12V

--J VO
- 5V
lO_lmA

-2

:RSC-O

,

o

I

I

10

20

30

15

5

Fig. 15

Outp.lt Impedance va. frequency

Load transient response
IN.
(M/)

4

o

!\

II
~

.J

-II

ri

o
-5

till

~

II-

'- r- ~

10-_

Output~

V1-12V

RSC-O

IO-SOmA

C~-;

1
8

e

CO-l

2

\

V

0.1

•e

V

4
I

!

2

,
l!II

iii

t'-l

l1li1

100

Fig. 17

c8

VO-5V

4

VO 5V
'RSC.Q

!

(

4

~,jVl-l2V
.
-4

Ao

ILoadCU~

• II~r

t'-l

25

Fig. 16

SAMSUNG SEMICONDUCIOR

11(

1CIK

-

'(Hz)

Fig. 18

305

I

LINEAR INTEGRATED CIRCUIT

KA78S40

SWITCHING REGULATOR
16 DIP

The KA78S40 is a monolithic switching regulator sub·
system consisting of all the active building blocks
necessary for switching regulator systems.

FUNCTIONS·
• High-currenl,. high·voltage output switch a power tran·
sistor and a diode
• A temperature compensated voltage reference
• A comparator
.
• A duty cycle controllable oscillator with an active cur·
rent limit circuit
• Independent operational amplifier.

FEATURES
•
•
•
.;
•
•
•

Step·up, step-down or inverting switching regulators
Output current to 1.5A without external transistors
Output adjustable from 1.3 to 40V
Operation from 2.5 to 40V Input
SOdB line and load regulation
Low standby current drain
High gain, high current Indepenclfmt OP Amp.

ORDERING INFORMATION
Operating Temperature

0-70·C

BLOCK DIAGRAM
COMPARATOR
NON-INVERTING
INPUT

COMPARATOR
INVERTING
INPUT

GND

TIMING
CAPACITOR

IpK

SENSE

DRIVER
COLLECTOR

SWITCH
COLLECTOR

r-----~9r-----~

'------qR
R1

REF;ERENCE
VOLTAGE

INVERTING·
INPUT

. NONINVERTING
INPUT

OP AMP
SUPPLY

OP AMP .
OUTPUT

SWITCH
EMITIER

ANODE·

CATHODE

Fig. 1

----

c8SAMSUNG SEMICONDUCTOR

306
/

LINEAR INTEGRATED CIRCUIT

KA78S40

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Characteristic

Symbol

Value

Unit
V

Power Supply Voltage

Vex;

40

OP Amp Power Supply Voltage

VOP

40

V

Common Mode Input Voltage Range.

VICIA

-0.3 - Vex;

V

Differential Input Voltage Range (Note)

VID

-30-30

V

Output Short Circuit Duration (OP Amp)

Isc

Continuous

Current from VREF

IREF

10

mA

Voltage from Switch. Collector to GND

VCG

40

V

Voltage from Switch Emitter to GND

VEG

40

V

'Voltage from Switch Collector to Emitter

VCE

40

V

'. VOG

40

V

VOltage from Power Diode to GND

II

Reverse Power Diode Voltage

VOR

40

V

Current Through Power Switch

Isw

1.5

A

Current Through Power Diode

10

1.5

A

Power Dissipation

Po

1500

mW

Lead Temperature (Soldering for 10 Sec)

TIOad

260

·C

Operating Temperature Range

Too,

Storage Temperature Range

T.'g

0

-65

·C

+70

·C

+150

NOTE: For supply voltage less than 3OV, the absolute maximum voltage is equal to the supply voltage.

ELECTRICAL CHARACTERISTICS
(Vcc=5.0V, VOP Amo= 5.0V, 0·
I

iil1,210

>

I

1,208

1,208
1,204

II

1,202

0.47
1

\

1,218

100

10

1,200

1000

75

100

12E

400

J

Tl=25"c

50

Fig. 8, V_ V. VIN

Fig. 7. Idlscharge V. VIN
250

25

-25

-50

T,I=25'b

/
/'"

350

./

-

=e

. . .V

I

1300

V

>

~~

--

250

150

o

200
10

30

20

40

50

o

10

20

30

40

50

VIN-V

.c8

SAMSUNG SEMICONDUCTOR

311

KA78TXXC/KA78TXXAC SERIES

LINEAR INTEGRATED CIRCUIT
T()'220

3A POSIT.IVE VOLTAGE REGULATOR
This family of fixed voltage regulators are monolithic integrated
c"ircuits capable of driving loads in excess of, 3.0 amperes. These threeterminal regulators employ Internal current limiting, thermal shutdown,
and safe-area compensation. Devices are available with improved
specifications, including a 2% output voltage tolerance on IA- suffix 5,
12 and 15 volts device types.
Although designed primarily as fixed voltage regulators, these devices
can be 'Used with external components to obtain adjustable voltages
and currents.

FEATURES
•
•
•
•
•
•

Output current In excess of 3_0 ampere
Output transistor safe-area compensation
Power dissipation: 25W (To-220)
Internal short-circuit current limiting
Internal thermal overload protection
Output voltage offered in 2% and 4% tolerance
(2% regulators are available in 5, 12 and 15 volt devices)
• No external components required
• Thermal regulation Is specified
• Output voltage of 5; 6; 8; 12; 15; 18; 24V

1: Input 2: GND 3: Output

ORDERING INFORMATION
Device
KA78TXXCT
KA78TXXACT
KA78TXXCH
KA78TXXACH

BLOCK DIAGRAM

Package Operating Temperature
TO-220

o-125°C
TO-3P

INPUT

I

1

I

STARTING
CIRCUIT

j--

REFERENCE
VOLTAGE

r-~UT
3

,SOA
PROTECTOR

CURRENT
GENERATOR

I

SERIES
PASS
ELEMENT

I

ERROR
AMPLIFIER

I

"

THERMAL
PROTECTION

I

-

GND

2

'cR

SAMSUNG SEMICONDUCTOR

312

LINEAR INTEGRATED CIRCUIT

KA78TXXC/KA78TXXAC SERIES
ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Input Voltage (5.0V -12V)
(15V -24V)

V'N

35
40

Voc
Voc

Power Dissipation

Po

Internally limited

Thermal Resistance, Junction to Air
Tc=25°C

9 JA

65

°C/W

Thermal Resistance, Junction to Case

9 JC

2.5

°C/W

Operating ·Temperature Range

o to

Top.

Storage Temperature Range

+125

°C

-65 to + 150

TS'g

°C

II

KA78T05C, KA78T05AC ELECTRICAL CHARACTERISTICS
(V,N=10V, 10=3.0A, T,=O°C to 125°C, PoSPmax, unless otherwise specified) .

Characteristic

Symbol

KA78T05AC

Test Conditions

KA78T05C

Min Typ Max Min Typ Max

5mAs los3.0A, Tj = 25°C
5mAslos3A;
7.3VocsV'Ns20Voc,5mAslos2A

4.9

5

5.1

4.8

5

5.2 4.75 5.0 5.25

Output Vortage

Vo

Line Regulation

6Vo

7.2VocSV'NS35Voc, 10=5mA, Tj =25°C
7.2VocSV'NS35V, 10= 1.0A, Tj = 25°C
7.5V sV,Ns20V, 10 = 2.0A
8.0VSV'NS12V,lo=3.0A

3.0

10

Load Regulation

6Vo

5niASloS3.0A, T, = 25°C
5mAsloS3.0A

10
15

25
50

4.8

5.0

3.0

I

Unit

5.2
Voc

25

mV

10 30
15. 80

mV
mV

Thermal Regulation

Regthe

Pulse = 10mS, P = 20W,
Ta=25°C

Quiescent Current

I.

5mAslos3A, TJ= 25°C
5mAslos3A

Quiescent Current
Change

61d

7.2VSV'NS35V, 10 = 5mA,
Tj = 25°C;
7.5VSV'Ns20V,lo=2A;
5mAslos3A

Ripple Rejection

RR

8VSV'NS18V, f=120Hz, 10=2.0A

Dropout Voltage

Vo

10 = 3A, T,=25°C

Output Noise Voltage

VN

10HzSfS100KHz, Tj =25°C

10

10

ILVNo

Output Resistance

Ro

f::;;1.0KHz

2.0

2.0

mil

Short Circuit Current
Limit

Isc

V'N=35V, Tj =25°C

1.5

Peak Output Current

lpeak

TJ=25°C

5.0

5.0

A

0.2

0.2

mV/oC

Average Temperature
Coefficient of
Output Volt~ge

.c8

6Vol6T 10 = 5.0mA

SAMSUNG SEMICONDUCTOR

0.001 0.01

.
68

0.002 0.03 %VoIW

3.5
4.0

5.0
6.0

3.5
4.0

5.0
6.0

mA
mA

0.1

0.5

0.1

0.8

mA

2.5

Voc

75
2.2

65
2.5

2.5

75
2.2

1.5

dB

2.5

A

313

KA78TXXC/KA78TXXAC SERIES

LINEAR INTEGRATED CIRCUIT

KA78T06C ELECTRICAL CHARACTERISTICS
(VIN=11V, lo=3.0V, Tj=O°C to 125°C, PoSPmax, unless otherwise specified)

Characteristic

Output VdltalJe

Symbol

Vo

5.0mAslos3A, Tj = +25°C
5.0mAslos3A;
8.3VSVINs21V,5mAslos2A

Line Regulation

tJ.Vo

8.25VsVINS35V lo=5.0mA, Tj= +25°C;
8.25VSVINS35V lo=1.0A, Tj = +25°C;
8.6VSVINS21V lo=2.0A
9.0VSVINS13V lo=3.0A

Load Regulation

tJ.Vo

5mAslos3A, Tj = +25°.C
5mAs los3A

Thermal Regulation
Quiescent Current

Regthe
Id

KA78T06C

Test Conditions

Min

Typ

Max

5.75
5.7

6.0
6.0

6.25
6.3

4.0

30

10
15

80

Unit

V

mV

30

mV

0.002

0.03

OfoV"JW

5mAslos:3A, Tj :; +25°C
5mAslos3A

3.5
4.0

5.0
6.0

mA

8.25VSV1N S35V, lo=5mA, Tj = + 25°C;
8.6VSVINS21V,lo:;2A;
5mAs los3.0A

0.1

0.8

Pulse=10mS, P=20W, Ta=25°C

Quiescent 'Current Change

tJ.ld

Ripple Rejection

RR

9VSV1N S19V, f=120Hz, lo=2A

Dropout Voltage

Vo

lo=3A, Tj = +25°C

2.2

Output Noise Voltage

VN

10HzSfS100KHz, Tj = +25°C

10

,.VNo

Output Resistance

Ro

f= 1.0KHz

2.0

mO

Short Circuit Current Limit

Isc

Peak Output Current

lpeak

Average Temperature
Cofficient of Output
Voltage

6VoItJ.T

.c8

mA
61

71

dB
2.5

V1N = 35V, Tj = + 25°C

1.5

Tj = +25°C

5.0

A

0.3

mV/oC

Jo=5.0mA

SAMSUNG SEMICONDUCTOR . .

2.5

V

A

,

314

KA78TXXC/KA78TXXAC SERIES

LINEAR INTEGRATED CIRCUIT

KA78T08C ELECTRICAL CHARACTERISTICS
(V1N =14V, 10 = 3.0V, Tj=O°C to 125°C, PosPmax, unless otherwise specified)

Characteristic

Output Voltage

Symbol

Vo

Test Conditions

Max

7.7

8.0

8.3

7.6

8.0

8.4

4.0

35

10
15

30
80

mV

0.002

0.03

OfoVJW

5mAslos3A, T1= +25°C
5mAs los3A .

3.5
4.0

5.0
6.0

mA

0.1

0.8

5.0mAslos3A, Tj = +25°C
5.0mAslos3A; I
10.4VsVu·.rs23V,5mAslos2A

Line Regulation

I::.Vo

Load Regulation

I::.Vo

5mAslos3A, Tj = +25°C
5mAslos3A

Quiescent Current

Regthe

I.

Unit

Typ

10.:,wsV1N s35V, lo=5mA, Tj = +25°C
10.3VSV1N S35V, lo=1.0A, TI = +25°C
10.7VSVINS23V,lo=2.0A
l1VSV1N S17V, 10 = 3.0A

Therrnal Regulation

KA78T08C
Min

mV

Pulse=10mS, P=20W, Ta=25°C

QuieScent Current Change

1::.1.

10.3VsV1N S35V, 10 = 5mA, TI = + 25°C
10.7VsVINS23V,lo=2A
5mAs los3A

Voc

mA

Ripple Rejection

RR

l1VsVINs21V, f=120Hz, 10=2A

Dropout Voltage

Vo

lo=3A, TI = +25°C

Output Noise Voltage

VN

10HzSfsl00KHz, TI = +25°C

10

Output Resistance

R9

f= 1.0KHz

2.0

Short Circuit Current Limit

Isc

V1N =35V, TI = +25°C

1.5

Tj = +25°C

5.0

A

0.3

mV/oC

Peak Output Current
Average Temperature
Cofficient of Output
Voltage

1-

. I::.Vo/I::.T 10=5.0mA

ciS SAMSUNG SEMICO~DUCTOR

61

71
2.2

dB
2.5

Vrx;
p.VlVo
mO

2.5

A

315

I

KA78TXXC/KA78TXXAC SERIES

LINEAR INTEGRATED CIRCUIT

KA78T12C, KA78T12AC ELECTRICAL CHARACTERISTICS
(VIN = 19V, 10 = 3.0A, T, = O°C to 125°C, PoS Pm.,., unless otherwise noted)

Characteristic

Output Voltage

Test Conditions

Symbol

Vo

KA78T12AC
Min

Typ

11.75
5mAslos3A, Tj = 25°C .
5mAslos3A; 5mAslos2A, 14.5VsVINs27V 11.5

12
12
6.0

10
15

Line Regulation

£::"Vo

14.5VocSVINs35Voc, 10 = 5mA, Tj = + 25°C;
14.5VocsVINs35Voc, 10 = 1.0A, Tj = + 25°C;
14.9Voc SV,N s27Voc, 10 = 2.0A;
16VoeSVINS22Voe, 10 = 3.0A

Load Regulation

£::"Vo

5mAslos3A, Tj = +25°C
5mAs los3A

KA78T12C

Max Min Typ Max
12.25 11.5
12.5 11.4
18

12
12

12.5
12.6

6.0

45

Unit

Voe

mV

25
50

10
15

0.001 0.01

30

80

Thermal Regulation

Regth Pulse=10mS, P=20W, Ta=25°C

Quiescent Current

Id

5mAslos3A, Tj = + 25°C
5mA,sIos3A

3.5
4.0

5.0
6.0

3.5
4.0

5.0
6.0

Quiescent Current
Change

14.5VoeSVINS35Voe, 10 = 5mA, TI =25°C;
14.9Voc S VIN S 27Voc, 10 = 2A;
5.0mAs los3.0A

0.1

0.5

0.1

0.8

£::"Id

Ripple Rejection

RR

15Voc SVIN s25Voc,
f = 120Hz, 10 = 2.0A

mV

0.002 0.03 %VJW
mA

rnA

61

67

57

67

dB

Dropout Voltage

Vo

10 = 3A, Tj = +25°C

2.2

Output Noise Voltage

VN

10Hzsfsl00KHz, Tj = +25°C

10

10

p.VNo

Output Resistance

Ro

f = 1.0KHz

2.0

2.0

mil

Short Circuit Current
Limit

Ise

VIN =35V, T, = +25°C

1.5

Peak Output Current

Ipeak

TI = +25°C

5.0

5.0

A

0.5

0.5

mV/oC

Average Temperature
Coefficient of
£::,.VoI£::,.T 10 = 5.0mA
Output Voltage

c8

SAMSUNG SEMICONDUCTOR

2.5

2.5

2.2

1.5

2.5

2.5

Voc

A

316

KA78TXXC/KA78TXXAC SERIES

LINEAR INTEGRATED CIRCUIT

KA78T15C, KA78T15AC ELECTRICAL CHARACTERISTICS
(V'N = 23V, 10 = 3.0A, TI = O°C to 125°C, PoS Pmax , unless otherwise noted)

Characteristic

Symbol

Test CondItions

5mAslos3A, T,= +25°C
5mAs los3A;
17.5Voc sV'NS30V DC, 5mAs los2A

KA78T15AC

KA78T15C

Min Typ Max Min

Unit

Typ

Max

14.7

15

15.3 14.4

15

15.6

14.4

15

15.6 14.25

15

15.75

22

7.5

55

25
50

10
15

80

Output Voltage

Vo

Line Regulation

t:.Vo

17.6VSV'NS40V, 10=5mA, TI = +25°C
17.6V SV'Ns40V, 10 = lA, T, = + 25°C;
18VSV'Ns30V,lo=2.0A;
20V S V'N S 26V, 10 = 3.0A

7.5

load Regulation

t:.Vo

5mAslos3A, T,= +25°C
5mAslos3A

10
15

0.001 0.Q1

30

VDC

mV

mV

Thermal Regulation

Regth Pulse=10mS, P=20W, Ta=25°C

Quiescent Current

Id

5mAslos3A, T,= +25°C
5mAs los3A

3.5
4.0

5.0
6.0

3.5
4.0

5.0
6.0

mA

Quiescent Current
Change

t:.ld

17.6VSV'NS40V, 10=5mA, T,= +25°C;
18VsV'Ns30V,lo=2A;
5mAs los3A

0.1

0.5

0.1

0.8

mA

Ripple Rejection

RR

18.5V DC S V'N S 28.5V DC,
f = 120Hz, 10 = 2.0A

60

65

0.002 0.03 %VofW

55

65

dB

Vpc

Dropout Voltage

V6

10=3A, T;= +25°C

2.2

Output Noise Voltage

VN

10Hzsfsl00KHz, TI = + 25°C

10

10

p.vNo

2.0

mO

2.5

2.2

2.5

Output Resistance

Ro

f = 1.0KHz

2.0

Short Circui,t Current
Limit

Isc

V,N=40V, T,= +25°C

1.0

Peak Output Current

lpeak

1',= +25°C

5.0

5.0

A

0.6

0.6

mVloC

Average Temperature
Coefficient of
Output Voltage

c8

t:.Volt:.T 10 = 5.0mA

SAMSUNG SEMICONDUCTOR

2.0

1.0

2.0

A

317

I

KA78TXXC/KA78TXXAC SERIES

LINEAR INTEGRATED CIRCUIT

KA78T18C ELECTRICAL CHARACTERISTICS
(VIN= 27V, 10 = 3.0V, TJ=O°C to 125°C, PosPmax, unless otherwise specified)

Characteristic

Symbol

Test Conditions
5.0mAslos3A, T;= +25°C
5.0mAslos3A;
2O.6VSVINs33V,5mAslos2A

KA78T18C
Min

Typ

Max

17.3

18

. 18.7

17.1

18

18.9

80

Output Voltage

Vo

l'1Vo

2O.7VsV1N S40V, 10=5mA, TJ= + 25°C;
2O.7VsV1N:S!40V, 10=1A, TJ= +2SoC;
21.2VsVINS~V, 10=2.0A
24VSV1N S30V,lo=3A

9.0

Line Regulation

Load Regulation

l'1Vo

5mAslos3A, T; = + 2SoC
SmAslos3A

10
1S

Thermal Regulation

Regthe

30
80

0.002· 0.03

Pulse=10mS, P=20W, Ta=2SoC

3.S
4.0

S.O
6.0

0.1

0.8

Id

Quiescent Current
Change

l'1ld

2O.7VSV1N S40V, 10=SmA, TJ= +2SoC;
21.2VsVINS33V,lo=2.oA;
SmAslos3.0A

Ripple Rejection

Vric

mV

SmAslos3A, TJ= + 2SoC
SmAslos3A

Quiescent Current

Unit

mV
OfoVJW
mA

mA

RR

22VSV1N S32V, f=120Hz, 10=2.0A

Dropout Voltage

Vo

10=3A, TJ= +2SoC

2.2

Output Noise Voltage

VN

10Hzsfs100KHz, TJ= +2SoC

10

,.VNo
mO

54

dB

64
2.S.

Voc

Output Resistance

Ro

f = 1.0KHz

2.0

Output Circuit Current
Limit

Isc

V1N =40V, T;= +2SoC

1.0·

Peak Output Current

lpeak

TJ= +2SoC

S.O

A

0.7

mV'oC

Average Temperature
Coefficient of
Output Voltage

c8

l'1Vol!::..T 10 = S.OmA

$AMSUNG SEMICONDUCTOR

2.0

A

318

.'
KA78TXXC/KA78TXXAC SERIES

LINEAR INTEGRATED CIRCUIT

KA78T24C ELECTRICAL CHARACTERISTICS
(VIN =33V, 10 = 3.0A, T)=O°C to 125°C, PosPmax, unless otherwise specified)

Characteristic

Output

Volt~e

Symbol

Vo

Test Conditions
5.0mAslos3A, Ti= +25°C
5.0mAslos3A;
27.3VsVINs39V,5mAslos2A

KA78T24C
Min

Typ

Max

23

24

25

22.8

24

25.2

90

f::,Vo

27VSVINS40V, 10=5mA, Ti= + 25°C;
27VSVIN S40V, 10=1.0A, T)= +25°C;
27.5VSVINS39V, 10 = 2.0A;
30VSVIN S36V, 10 = 3.0A

12

Line Regulation

Load Regulation

f::,Vo

5mAslos3A, Ti= +25°C
5mAslos3A

10
15

80

Thermal Regulation

Regthe

Unit

Vee

mV

Pulse=10mS, P=20W, Ta=2SoC

30

mV

0.002

0.03

%Vo/W

5mAslos3A, T)= +25°C
5mAslos3A

3.5
4.0

5.0
6.0

mA

27VsVI~S.40V,

0.1

0.8

Quiescent Current

Id

Quiescent Current
Change

f::,l d

10=SmA, Ti= +25°C;
27.5VSVINS39V,lo=2A;
SmAslos3A

Ripple Rejection

RR

28VSVIN S38V, f=120Hz, 10=2.0A

mA
51

61

dB

Dropout Voltage

Ve

10 = 3A, Ti= +25°C

2.2

Output Noise yoltage

VN

10Hzsfs100KHz, Ti= +25°C

10

p.VlVo

Output Resistance

Ro

f=1.0KHz

2.0

ma

Short Circuit Current
Limit

Isc '

VIN =40V, T)= +2SoC

1.0

Peak Output Current

lpeak

TI = +2SoC

5.0

A

Average Temperature
Coefficient of
Output Voltage

f::,Vo/f::,T

10 = 5.0mA

1.0

mV/oC

c8

SAMSUNG SEMICONDUCTOR

2.5

2.0

Vee

A

319

II

KA78TXXC/KA78TXXAC SERIES

LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS
Fig. 1 TEMPERATURE STABILITY

Fig. 2 OUTPUT IMPEDANCE

1.02

10"

v:,-Vo.\ov

w

lOUT

~

Vo=5.0V

= mOmA -

1I---~T:~'~~
Co=O
TJ -25°C

~ 1.00 .--. !'-"
S

~

1/

':""

f'.. !"'....

I

I

J

oz

0.98
-10

30

10- 4

70

110

150

10

100

TJ • JUNCTION ~EMPERATURE (0C)

Fig. 3 RIPPLE REJECTION V, FREQUENCY

r-

iii

lOUT

=3.0A

~
60

w

'"
a:

r

-

\

Vo =5.0V
V1N =10V
Co=O
. TJ =25°C

40

20
1.0

10

100

1K

80

~

Ul
a:

~

\

10K

60
Vo=5.0V
VIN= 10V

ii:

'"
a:

1

lOOK

rCo=O
f=120Hz
TJ=25°C

40

30
1M

10M

0.01

100M

f, FREQUENCY (Hz)

Fig. 5 QUIESCENT CURRENT V, INPUT VOLTAGE

0.1

1.0

10

Fig. 6 QUIESCENT CURRENT V. OUTPUT CURRENT
5.0

TJ -25°C- j-----

f
II

3.0

g

...z

w
a:
a:

4.0

C
g

TJ=25°C

!

:>

2.0

[fi
0

.l 1.0

...0z

I

w

0

5

w

0

In
W

I
I

2.0

5
0

VIN-VO= 5.0V

.l
1.0

Vo =5.0V

i<>rrT

V

10

20

30

VIM! INPUT VOLTAGE (V1IJ

c8

III

JOUT, OUTPUT CURRENT (A)

4.0

...0z

100M

z

11

C

10M

Q

1

w

~

:!1.

~

0

ii:

1M

!oo;=JmA I

z

.

tOOK

100

:!1.

Ul
a:

10K

Fig. 4 RIPPLE REJECTION V, OUTPUT CURRENT

100

iii 80

1K

I, FREQUENCY (Hz)

SAMSUNG SEMICONDUCTOR

ill
III

A-

40

0.01

0.1

1.0

fo~, OUTPUT CURRENT

10

(A)

320

KA78TXXC/KA78TXXAC SERIES

LINEAR INTEGRATED CIRCUIT

Fig. 7 DROPOUT VOLTAGE

Fig. 8 PEAK OUl'PUT CURRENT
B.O

~ 2.5

~.

~

loor=3.0A

~ 2.0

...g
.."
..."

-

-

,... r- ~

6.0

Z

is

IU

IU

r- t--

~>

1.5

Ie
~

-

t--

r- r-..
r- t-- ~ r-r010UT=1.0A_

O"",

=0:;;::--

1.0

'""'-

II"" r-

(J

4.0

'\ ~

.......

"

0

.

'"
J 2.0

~

""'~~
1"'-"

"~

.;r

.j
o

oj

0.5

150

30
70
110
T,. JUNCTION TEMPERATURE ('C)

Fig. 9 LINE TRANSIENT RESPONSE

~

0.6

~~

Vo=5.0V
10IJT=150mA

~Z

0.4

00=0

5!;i

0.2

I, ,I

1

_

TVJ =25·0

"0

10

I

40

.. I

r-~o=5.OV
V,N =10V

n

00=0
r-i-,=25'C

\

r

1\

<1<>

30

Fig. 10 LOAD TRANSIENT RESPONSE

O.B

.jiii

J.
0

Vw-V.. INPUT.()UTPUT VOLTAGE (V.,)

IU

0

I
TJ =125 G C

0
10

CO.

TJ=oec TJ=25°C

IV

-0.2
-·0.4
IU

"~

-0.6

g

..

~

~IU
;r"

J~

1

1.0

II

II

0.5

<16
10

20

30

40

t, TIME",")

~

TIME",")

'"

Fig. 11 MAXIMUM AVERAGE POWER DISSIPATION
40

MAXIMUM AMBIENT
TEMPERATURE

50
75
TA• AMBIENT TEMPERATURE (Oe)

c8

SAMSUNG SEMICONDUCTOR

321

LINEAR INTEGRATED CIRCUIT

KA78TXXC/KA78TXXAC SERIES
APPLICATION INFORMATIONS

The KA78TOO,A Series of fixed voltage regulators are designed with Thermal Overload Protection that shuts down
t~e circuit when subjected to an excessive power overload condition, Internal Short·Circuit Protection that limits

the maximum current the circuit will pass, and Output Transistor Safe·Area Compensation that reduces the output
,
short:circuit current as the voltage across the pass transistor is increased.
In many low current applications, compensation capacitors are not required. However, it is recommended that
the reg),Jlator input be bypassed with a capacitor If the regulator is connected to the power supply filter with long
wire lengths, or if the output load capacitance is large. An input bypass capacitor should be selected to provided
good high·frequency characteristics to insure stable operation under all load conditions. A O:33"F or larger tantalum,
mylar, or other capacitor having low internal impedance at high frequencies should be chosen. The bypass capacitor
should be mounted with the shortest possible leads directly across the regulator's "nput terminals. Normally good
construction techniques should be used to minimize ground loops and lead resistance drops since the regulator
has no external sense lead.
'
Fig. 13-ADJUSTABLE OUTPUT REGULATOR

Fig. 12-CURRENT REGULATOR

Input
Constant
'------''--oCurrent to
t;: Grounded Load

R

Output

The KA78T05 regulator can also be used as a current
source when connected as above. In order to minimize
dissipation, the KA78T05 is chosen in this application.
Resistor R determines the current as follows:

6I B=0.7mA over line, load and temperature Changes
IB=3.5mA
For example, a 2·ampere current source would require
R to be a 2.5 ohm, 15W resistor and the output voltage
compliance would be the input voltage less 7.5 volts.
Fig. 14-CURRENT BOOST REGULATOR
2N4398 pr Equiv..
Input

10K,

Vo, 8.0V to 20V
V1N - Vo~2.5V
The addition of an operational amplifier allows
adjustment to higher or intermediate values while
retaining regulation characteristics. The, minimum
voltage obtainable with this arrangement is 3.0 volts
greater than the regulator voltage.
Fig. 1S-CURRENT BOOST WITH SHORT·
CIRCUIT PROTECTION

Input ~---.-~_'t-£

R

J
xx = 2 digits of type

number indicating voltage.

The KA78TOO,A series can be current boosted with a
PNP transistor. The 2N4398 provides current to 15
amperes. Resistor R in conjunction with the VBE of
the PNP determines when the pass transistor begins
conducting; this circuit is not short-circuit proof. Input·
output differential voltage minimum is increased by
the VBE of the pass transistor.

c8

SAMSUNG SEMICONDUCTOR

1.0"F

XX = 2 digits of type number indicating voltage.
The ,circuit of Figure 18 can be modified to provide
supply protection against short circuits by adding a
short·circuit sense resistor, Rsc, and an additional
PNPtransistor. The current sensing PNP must be able
to handle the short-circuit current of the three·terminal
regulator: Therefore, an eight·ampere power transistor
is specified.

322

MC78XXJMC78XXA

LINEAR INTEGRATED CIRCUIT
-------------,

3-TERMINAL 1A POSITIVE
VOLTAGE REGULATORS

TO-220

The MC78XX/MC78XXA series of three·terminal positive regulators are
available in TO·220 package and with several fixed output voltages,
making it useful in a wide range of applications. These Regulators can
provide local oncard regulation, eliminating the distribution problems
associated with single pOint regulation. Each type employs internal
current limiting, thermal shut-down and safe area protection, making
it essentially indestructible. If adequate heat sinking is provided, they
'can deliver over 1A output current. Although designed.primarily as fixed
voltage regulators, these devices can be used with external components
to obtain adjustable voltages and currents.

FEATURES
•
•
•
•
•

Output Current up to 1.5A
Output voltages of 5; 6; 8; 8.5; 9; 10; 11; 12; 15; 18; 24V
Thermal Overload Protection
Short Circuit Protection
Output Transistor SOA P~ctlon

Input
L -_ _1:
_
_

ORDERING INFORMATION
Device

BLOCK DIAGRAM

Package OPerating Temperature .

MC78XXIT

TO·22O

MC78XXCT

TO·22O

MC78XXACT

TO·220

IN PUT
1

I
CURRENT
GENERATOR

SllIRTING
CIRCUIT

-

ERROR
AMPLIFIER

- 40°C - + 125°C
O°C _+125°C

SERIES
PASS
ELEMENT

OUTPUT

3

...... ~

SOA
PROTECTION

REFERENCE
VOLTAGE

II

2: GND 3: Output

1

THERMAL
'PROTECTION

I

I---

GN o
2

Fig. 1

c8

SAMSUNG S.EMICONDUCTOR

323 .

MC78XX/MC78XXA

LINEAR INTEGRATED CIRCUIT

SCHEMATIC DIAGRAM
.---.------?-----?--~-_,_--_r_--oIN

>-~-~-+---4--~-_oOUT

.

R20

R19

Fig. 2

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Input Voltage (for Vo=5V to 18V)
. (for Vo = 24V)
Thermal Resistance Junction-Cases
Thermal Resistance Junction-Air
Operating Temperature Range MC78XXI
MC78XXC/AC
Storage Temperature Range

Vi
Vi

35
40
5
65
-40-+125
0-+ 125
-65- +150

V
V
'CIW
·CIW
·C
·C
·C

c8

SAMSUNG SEMICONDUCTOR

9 JC
9JA

Topr
Tstg

324

LINEAR INTEGRATED CIRCUIT

MC78XX1MC78XXA

ELECTRICAL CHARACTERISTICS MC7805
(Refer to test circuit, Tm'n<, 10 = 500mA, V, = 23V, C, = 0.33/LF, Co = 0.1/LF, unless otherwise specified)

Characteristic

Symbol

Test Conditions

Vo

5.0mA:s 10:S 1.0A, PD:s 15W
V, = 17.5V to 30V
V, = 18.5V to 30V

T, =25°C
Output Voltage

Line Regulation

Load Regulation
Quiescent Current

/,;V o

Tj =25°C

/,;V o

T,=25°C

MC78151
Typ

Max Min

Typ

Max

14.4

15

15.6 14.4

15

15.6

14.25

15

15.75

14.25

15

15.75

V, = 17.5 to 30V

11

300

11

300

V, =20 to 26V

3

150

3

150

10 = 5.0mA to 1.5A

12

300

12

300

10 = 250mA to 750rriA

4

150

4

150

8

4.4

4.4

10=5mA to 1.0A
Quiescent Current Change

/';Id

0.5

Output Noise Voltage
Ripple
Rejection

/,;VJ/,;T
. VN

8

mV

mV
mA

0.5

V, = 17.5V to 30V

1.0

V, = 18.5V to 30V
Output Voltage Drift

Unit

V

TJ=25°C

Id

MC7815C

Min

mA

1.0

10=5mA

-1

-1

mV'oC

f = 10Hz to 100KHz Tj = 25°C

90

90

/LV

70

dB

RR

f = 120Hz
V, = 18.5V to 28.5V

Dropout Voltage

VD

10 = 1A, Tj = 25°C

2

2

V

Output Resistance

Ro

f=1KHz

19

19

m{J

Short Circuit Currel)t

Isc

V, = 35V, Tj = 25°C

230

230

mA

Peak Current

Ipeak

Tj =25°C

2.2

2.2

A

54

70

54

• Tmln< = 125°C
MC78XXC, Tmln=O°C, Tma><=125°C
• Load and line regulation are specified at constant junction temperature changes in Vo due to heating
effects must be taken into account separately pulse testing with low duty is used.

c8

SAMSUNG SEMICONDUCTOR

333

I

MC78XX1MC78XXA

LINEAR INTEGRATED CIRCUIT

'ELECTRICAL CHARACTERISTICS MC7818
(Refer to' test circuit, Tminc, 10 = 5OOmA, Vi = 27V, Ci = O.33I'F, Co = 0.1I'F, unless otherwise specified)

Characteristic

Symbol

Test Conditions
Tj =25°C

Output Voltage

Vo

5.0mAslos1.0A, Pos15W
Vi = 21V to 33V
Vi = 22V to 33V

Line Regulation

D.Vo

TJ=25°C

Load Regulation

'D.Vo

TJ=25°C

Quiescent Current

Id

MC78181

17.3

18

D.ld

Output Noise Volt~ge

18

18.7

17.1

18

18.9

18

18.9

Vi ';'21 to 33V

15

360

15

360

Vi =24 to 30V

5

180

5

180

17.1

10 = 5mA to 1.5A

12

360

12

360

10 = 250mA to 750mA

4.0

180

4.0

180

TJ;"25~C

4.3

'8

4.3

0.5

8

'mV'

mV
rnA

0.5
1

Vi = 21V to 33V

rnA

1

Vi = 22V to 33V
, Output Voltage Drift

18.7 17.3

Unit

V,

10 = 5mA to 1A
Quiescent Current Change

MC7818C

Min Typ Max Min Typ Max

D.VJD.T

10=5mA

-1

-1

mV/oC

110

110

I'V

69

dB

VN

f = 10Hz to 100KHz TJ= 25°C

Ripple
Rejection

RR

f = 120Hz
Vi = 22V to 32V

Dr9poilt Voltage

Vo

10=1A, TJ=25°C

2

2

V

Output Resistance

Ro

f=1KHz

22

22

mO

Isc

Vi = 35V, TJ=25°C

200

200

rnA

TJ=25°C

2.2

2.2

A

53

69

53

~-~------~-

Short Circuit Current

--

Peak Current

' lpeak

• Tmin 125°C C'N -0.331'F CO~T -0 1/lF unless otherwise specified (Note 1)
Characteristic
Output Voltage

Symbol
Vo

Test Conditions

c.Vo

T j =25°C

Load Regulation

c.Vo

T j =25°C

I
I

Max

Unit

4.S

5.0

5.2

V

7VSV'NS20V

55

150

mV

SVsV,Ns20V

45

100

mV

lmAslouT sl00mA

11

60

mV

lmAsiouT s40mA

5.0

30

mV

"NsV,Ns2W

lmAslouTs40mA

4.75

5.25

V

Vo

7VSV'NSVmax
(Note 2)

lmAslouTs70mA

4.75

5.25

V

5.5

mA

Id

T j =25°C

with line

c.ld

SVsV,Ns20V

1.5

mA

with load

c.ld

lmA s louT s40mA

0.1

mA

VN

T.=25°C,10Hzsfsl00KHz

Quiescent Current
Quiescent Current
Change

Typ

Tj =25°C

line Regulation

Output Voltage

Min

Output Noise Voltage
Temperature Coefficient of V OUT

c.Vo

2.0

louT=5mA

40

I'V

-0.65

mV/oC

49

dB

c.T
Ripple Rejection

RR

f=l20Hz.8VsV,Nsl8V, Tj=25°C

Dropout Voltage

Vo

TJ=25°C

1.7

V

Peak Output/Short-Circuit Current

Isc

TJ=25°C

140

mA

41

MC78L62AC ELECTRICAL CHARACTERISTICS
ooc sTj s 125°C. C'N =0.33I'F, COUT =0.1~, unless otherwise specified. (Note 1)

V'N =12V, IQuT =4OmA,

Characteristic

Symbol

Test Conditions

Output Voltage

Vo

T j =25°C

line Regulation

c.Vo

Tj =25°C

c.Vo

TJ =25OC

Load Regulation

Min

"lYP

5.95

I

Max

Unit

6.2

6.45

V

S.5VSV'NS2OV

65

175

mV

9VSV'NS20V

55

125

mV

lmAs loUTs l00mA

13

SO

mV

lmAs lOUT s40mA

6.0

40

mV

8.5VsV,Ns2rN lmAslouTs40mA

5.90

6.5

V

5.90

6.5

V

5.5

mA

Output Voltage

Vo

8.5VSV'NSVmax
lmAslouT s70mA
(Note 2)

Quiescent Current

Id'

T j =25°C

c.ld

SVsV,Ns20V

1.5

mA

c.ld

lmA s loUT s40mA

0.1

mA

VN

T.=25OC,10Hzsfsl00KHz

Quiescent Current
Change

I with line
I with load

Output Noise Voltage
Temperature Coefficient of VOUT

c.Vo
c.T

2.0

IOUT=5mA

I'V

-0.75

mV/oC

46

dB

Ripple Rejection

RR

f=120Hz.lrNsV,Ns20V, Tj=25OC

Dropout Voltage

Vo

TJ =25°C

1.7

V

Peak Output/Short-Circuit Current

Isc

TJ =25OC

140

mA

c8

SAMSUNG SEMICONDUCTOR

40

50

355

II

LINEAR INTEGRATED CIRCUIT

MC78LXXAC SERIES

MC78LOSAC ELECTRICAL CHARACTERISTICS
VIN =14V, lOUT =40mA, O°C sTj s 125°C, CIN =0.33/LF. COUT =O.lpF, ..unless otherwise specified. (Note 1)
.I,t

Characteristic
Output Voltage

Symbol
T1=25°C

Vo

!:No

Line Regulation

Load Regulation

Test Conditions

T j =25°C

lYP

7.7

Max

Unit

8.0

8.3

V

10.5 s VIN s 23V

80

17.5

mV

llVsVIN s23V

70

125

mV

lmAs louTsl00mA

15

80

mV

1mAs lOUT s 40mA

8.0

40

mV

AVo

T1=25°C

lmA s louT s40mA

7.6

8.4

V

Vo

10.5V S VIN s V maX
lmA s lOUTS 70mA
(Note 2)

7.6

8.4

V

Id

T j =25°C

10.5V S VIN s 23V
Output Voltage

Min

5.5

mA

Aid

l1V s VIN s 23V

1.5

mA

Aid

1mA s lOUT s40mA

0.1

mA

Output Noise Voltage

VN

T. = 25°C, 10Hzsfs 100KHz

Temperature Coefficient of VOUT

AVo
AT

louT=5mA

Quiescent Current
Quiescent Current
Change

I with line
I with load

2.0

60

/LV

-0.8

mVI"C

Ripple Rejection

RR

f=120Hz, l1V:sVIN:s21V, TJ=25°C

45

dB

Dropout Voltage

Vo

Tj=25°C

1.7

V

Peak Output/Short-Circuit
Current

Iso

Tj = 25°C

140

mA

39

MC78L82AC ELECTRICAL CHARACTERISTICS
VIN =14V, lOUT =40mA, OOC sTj s 125°C, CIN =0.33/LF, COUT =O.lpF, unless otherwise specified. (Note 1)
Characteristic
Output Voltage

Symbol
Vo

Line Regulation

AVo

Min

lYP

Max

7.87

8.2

8.53

V

80

175

mV

.12V sVIN s23V

70

125

mV

lmAsiouT sl00mA

15

80

mV

lmAs lOUT s40mA

8.0

40

mV

Test Conditions
T1=25°C
T1=25°C

l1V s VIN s 23V

Unit

Load Regulation

AVo

T j =25°C

l1VsVIN s23V lmAslouTs40mA

7.8

8.6

V

Output Voltage

Vo

l1V"VIN "Vm..
(Note 2)

7.8

8.6

V

Quiescent Current
Quiescent Current
Change

I with line
I with load

Output Noise Voltage
Temperature Coefficient of VOUT

lmAslouT s70mA

I.

T1=25°C

5.5

mA

Aid

12V :S VIN:s 23V

1.5

mA

Ald'

lmAs louTs40mA

0.1

mA

VN

T.=25°C,10Hzsfsl00KHz

AVo

2.0

louT=5mA

60

/LV

-0.8

mV/oC

45

dB

AT
Ripple Rejection

RR

f=I20Hz, 12VsVIN S22V, Tj=25°C

Dropout Voltage

Vo

T1=25°C

1.7

V

Isc

T j =25°C

.140

mA

Peak Output/Short-Circuit Current

c8

SAMSUNG SEMICONDUCTOR

39

356

· MC78LXXAC SERIES

LINEAR INTEGRATED CIRCUIT

MC78L09AC ELECTRICAL CHARACTERISTICS

-

Y,N =15V, lOUT =40mA, O·C:5Tj < 125OC, C,N =0.33/LF, COUT =0.1pF, unless otherwise specified. (Note 1)
Characteristic
Output Voltage

Vo

!!.VO

Line Regulation
Load Regulation

!!.Vo

Output Voltage

I
I

Test Conditions
Tj =25·C
Tj =25·C

Tj =25·C

Min

l\'p

Max

8.64

Unit

9.0

9.36

V

11.5V:5 V,N :5 24V

90

200

mV

13V:5 V,N :5 24V

1100

1150

lmv

1mAsipuTs100mA

20

90

mV

45

mV

11.5VsV,N s24V 1mA s lOUT s40mA

8.55

9.45

V

Vo

11.5V s Y,N S Vm.,
1mAslouT :570mA
(Note 2)

8.55

9.45

V

6.0

mA

1.5

mA

0.1

mA

10

1mAslouT :540mA

Id

Tj =25°C

with line

!!.Id

13V sV,NS24V

with load

Quiescent Current
Quiescent Current
Change

Symbol

2.1

!!.Id

1mA:5louT :540mA

Output Noise Voltage

VN

T.=25°C,10Hz:5f:5100KHz

Temperature Coefficient of VOUT

!!.Vo
!!.T

louT=5mA

Ripple Rejection

70

/LV

-0.9

mV/oC

RR

f =120Hz, 12V SV,N S22V, TI = 25°C

44

dB

Dropout Voltage

Vo

Tj =25°C·

1.7

V

Peak OutpuUShort-Circuit Current

Isc

Tj =25OC

140

mA

38

MC78L12AC ELECTRICAL CHARACTERISTICS
Y,N = 19V, lOUT = 40mA, 0·C:5Tj:5125°C, C,N =0.33/LF, CouT =0.1/LF, unless otherwise specified. (Note 1)
Characteristic·
Output Voltage

Vo

Line Regulation

!!.Vo

Load Regulation

!!.Vo

Output Voltage

Vo

Quiescent Current
Quiescent Current
Change

Symbol

I
I

with line
with load

Test Conditions

T1=25°C

Tv.p

Max

Unit

12

12.5

V

14.5V :5 V,N :5 27V

120

250

mV

16V:5 V,N :5 27V

100

200

mV

20

100

11.5

Tj =25°C
Tj =25°C

'Min

1mAslouT s100mA
1mAs·louT :540mA

10

50

mV
I

mV

14.5VSV,N S27V 1mAslouTs40mA

11.4

12.6

V

14.5V S Y,N S Vmax
1mAsloul:570mA
(Note 2)

11.4

12.6

V

6.0

mA

Id

Tj =25°C

!!.Id

16V:5 V,N :5 27V

1.5

mA

0.1

mA

2.1

!!.Id

1mA:5louT :540mA

Output Noise Voltage

VN

T.=25°C,10Hz:5f:5100KHz

Temperature Coefficient of VOUT

!!.Vo
!!.T

louT=5mA

Ripple Rejection

RR

f=120Hz, 15VsV,N :525V, Tj=25°C

Dropout Voltage

Yo·

Tj =25OC

1.7

V

Isc

Tj =25°C

140

mA

Peak OutpuUShort-Circuit Current

c8

SAMSUNG

~EMICONDticroR

37

80

/LV

-1.0

mV/oC

42

dB

357

I

MC78LXXAC SERIES

LINEAR INJEGRATED CIRCUIT

MC78L15AC ELECTRICAL CHARACTERISTICS
V'N =2311, lOUT =40mA, OOC sTj s 125°C, C'N =0.33"F, CouT =0.1jLF, unless otherwise specified. (Note 1)
Characteristic
. Output Voltage

Symbol
Vo

Line Regulation

tNo

Load Regulation

t:.vo

Test Conditions
T1",25OC
T1=25°C
T1=25°C
17.5VsV,Ns3OV

Output Voltage

Min
14.4

Typ

Max

Unit

15

15.6

V

17.5V s V'N s 30V

130

300

mV

20VsV,Ns3OV

110

250

nV

lmAslouTsl00mA

25

150

mV

75

mV

14.25

12

15.75

V

14.25

15.75

V

6.0

mA

lmAs louT s40mA
lmAslouTs40mA

Vo

17.5VsV,NsVm• x
lmAsloUTs70mA
(Note 2)

Id

T1=25°C

with line

.o.ld

20VsV,Ns3OV

1.5

mA

with load.

.o.ld

1mA s lOUT s40mA

0.1

mA

Output Noise Voltage

VN

T.=25°C,10Hzsfsl00KHz

Temperature Coefficient of VOUT

.o.Vo
.o.T

louT=5mA

Ripple Rejection

RR

f=l20Hz, 18.5VsV,Ns28.5V, Tj=25OC

Dropout VoJtage

Vo

T1=25°C

1.7

V

Peak OutpuUShort-Circuit Current

Isc

T1=25°C

140

mA

Quiescent Current
Quiescent Current
Change

I
I

2.2

34

90

"V

-1.3

mVloC

39

dB

MC78L18AC ELECTRICAL CHARACTERISTICS
V'N =27V, lOUT =40mA, OOC sTj s 125°C, C'N =0.33"F, COUT =0.1 JLF, unless otherwise specified. (Note 1)
Characteristic

Symbol

Output Voltage

Vo

T1=25°C

Line Regulation

.o.Vo

T1=25°C

Load Regulation

.o.Vo

T1=25OC

Output Voltage

Vo

Min

lYP

Max

Unit

17.3

18

18.7

V

21V s V'N s 3311

145

300

mV

22VsV'NS33V

135

250

mV

lmAslouT:5;I00mA

30

170

mV

lmAs lOUT s40mA

15

85

mV

Test Conditions

21VSV'NS33V lmAslouTs40mA

17.1

18.9

V

21VsV,NsVmax
(Note 2)

17.1

18.9

V

lmAs louTs 70mA

Id

Tj =25OC

6.0

mA

with line

.o.ld

21VsV'NS33V

1.5

mA

I with load

.1.ld

1mA s l~uTs4OmA

0.1

mA

Output Noise Voltage

VN

T.=25°C,10Hzsfs100KHz

150

"V

Temperature Coefficient of VOUT

.1.Vo
.1.T

louT=5mA

-1.8

mV/oC

Ripple Rejection

RR

f=l20Hz, 23VSV'N s 3311, Tj=25OC

48

dB

Dropout Voltage

Vo

T1=25OC

1.7

V

Peak OutpuUShort-Circuit Current

Isc

T1=25OC

140

mA

Quiescent Current
Quiescent Current
Change

c8

I

SAMSUNG SEMICONDUCTOR

2.2

34

358

MC78LXXAC SERIES

LINEAR INTEGRATED CIRCUIT

MC78L24AC ELECTRICAL CHARACTERISTICS
V'N= 33V, louT=40mA, O°CsTjs 125°C, C'N=0.33/LF, CouT =0.1/LF, unless otherwise specified. (Note 1)
Characteristic
Output Voltage

Vo

Line Regulation

liNo

Load Regulation

t.Vo

Output Voltage

Vo

I
I

Test Conditions
Tj =25OC
T j =25°C

T j =25°C

Min
23

Typ

Max

Unit

24

25

V

27VsV'NS38V

160

300

mV

28VsV'NS38V

150

250

mV

1mAsiouT s100mA

40

200

mV

1mAsiouT s40mA

20

100

mV

'ZNSV'NS'JW 1mAslouTs40mA

22.8

25.2

V

'lNSV'NSVmax
(Note 2)

22.8

25.2

V

1mAslouT s70mA

Id

'TJ =25°C

with line

t.ld

28VsV'NS38V

with load

t.ld

1mAs louTs40mA

VN

T.=25°C,10Hzsfs100KHz

200

/LV

louT=5mA

-2.0

mV/oC

45

dB

Quiescent Current
Quiescent Current
Change

Symbol

Output Noise Voltage
Temperature Coefficient of VOUT

t.Vo
t.T

2.2

6.0

mA

1.5

mA

0.1

mA

Ripple Rejection

RR

f=120Hz, 28VsV'NS38V, Tj=25°C

Dropout Voltage

Vo

Tj =25°C

1.7

V

Peak Output/Short-Circuit Current

lse

TJ =25°C

140

mA

34

Notes
1. The maximum steady state usable output current and input voltage are very dependent on the heat sinking and/or
lead length of the package. The date above represent pulse test conditions with junction temperatures as indicated at
the initiation of tests.
2. Power dissipation sO.75W.

c8

SAMSUNG SEMICONDUCTOR

359

MC78LXXAC SERIES

LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS
Fig. 1 QUIESCENT CURRENT va A
FUNCTION OF INPUT VOLTAGE

Fig. 2 DROPOUT VOLTAGE ¥sA
FUNCTION 0 FJUNCTION TEMPERATURE
,2.5

71J

MC7ILOYC

MC7ILOYC

so

I
r-- ;;;;;::: ~r"1JmA

i'--

- --

--

I - --.;

I-

1our01lJmA
~
t--

i--

. . . . 1-

21J - h

so

AVo,JT_&MIOFVOUT

-_. -- r- r-- r- -

-

10
15
20
1..-uT WlLT_- V

25

30

~

41J

las

I~

VooT_5V

~~

I:

10UT 0

"- ..........

V1Ho1OV

f-- r-VCUToSV

Iii
25

10

75

"1\

100

80

-

•

J
2.0

1211

41J
SO
INPUTWIL_- V

I

VIN-Wto1BV

SO

10

Fig. 6 UNE TRANSIENT RESPONSE
20

400

I!

INPUT YOI.1l\GE

MC7BL

·v"",_5V

,

21J

Fig. 5 RIPPLE REJECTION va A
FUNCTION OF FREQUENCY

IIIIII II

1IJmA2101If.,l,,,,,
/.~

_~RE_'C

100

125

.J~

6.

.........

100

Fig. 4 'DROPOUT CHARACTERISTICS

T,025'C

........

2.8

~

so

J.J

f': I'.....

~

JUNCrlON TEMPERATURE - 'C

Fig. 3 QUIESCENT CURRENT va A
FUNCTION OF TEMPERATURE
4.2

l"""-

DROPOUT CONDmON

VOOT.5IN
IL_4QmA
01)0

IIJ -11 11
o

-

15

MC7ILOYC

10UT-4OmA
T,025'C

III

-

80

i

40

I
I\,

OUTPUTVOIJl\GE
DEVlImON

iI!
20

r--,L"00mA15W
V, = -8to -20V
V,= -7to
-25V

100

V, = -8to
-12V

50

rrW
TJ=25°C
10 =250 to 750mA

I.

Quiescent Current Change

61d

V

1Q()

6Vo

Quiescent Current

Unit

mV

T,=25°C

Tj =25°C
lo=5mA to 1.5A
Load Regulation

Max

50

T,=25°C

3

6

mA

0.5

lo=5mAto 1A

1.3

V,= -8to -25V

mA

Output Voltage Drift

6Vo
6T

lo=5mA

-0.4

rrWfOC

Output Noise Voltage

VN

f = 10Hz to 100KHz
TJ=25°C

100

/LV

Ripple Rejection

RR

f=120Hz
6V,=10V

60

dB

Dropout Voltage

Va

TJ=25°C
lo=1A

2

V

Short Circuit Current

loe

TJ=25°C

2.1

A

Peak Current

I peak

TJ=25OC

2.5

A

c8

SAMSUNG SEMICONDUCTOR

54

379

II

MC79XX SERIES

LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7906C
(C,=2.2/LF, Co=1/LF, TJ=O to 125·C, 10=500mA, Vi =11V, unless otherwise specified)

Characteristic

Symbol

,
Output Voltage

Line Regulation

Load Regulation

Vo

/',Vo

Test Conditions

Min

Typ

Max

TJ=25°C

-5.75

-6

-6.25

-5.7

-6

-6.3

10=5mA to 1A, Po:s15W
V,= -9to -21V
Vi= -8 to
-25V

. 120

V,= -9to
-13V

60

Tj =25°C
10=5mA to 1.5A

120
mV

T,=25°C
10 =250 to 750mA
Quiescent Current

Id

Quiescent Current Change

/',Id

V

mV

Tj =25°C

/',Vo

Unit

60
3

T,=25°C

6

lo=5mAto 1A

0.5

V,= -9to -25V

1.3

/',Vo

mA

mA

Output Voltage Drift

--z:r

Output Noise Voltage

VN

f = 10Hz to 100KHz
TJ =25°C

Ripple Rejection

RR

f=120Hz
/',V,=10V

Dropout Voltage

VD

TJ =25°C
lo=1A

Short Circuit Current

Iso

T j =25·C

1.8

A

Peak Current

lpeak

TJ =25°C

2.5

A

·cR

SAMSUNG SEMICONDUCTOR

-0.5

1.=5mA

. 130
54

mVI"C
/LV

60

dB

2

V

380

LINEAR INTEGRATED CIRCUIT

MC79XX SERIES

. ELECTRICAL CHARACTERISTICS MC7908C
(C, = 2.2/LF, Co = l/LF, TJ= 0 to 125°C, 10 = 500mA, V, = 14V, unless otherWise specified)

Characteristic

Symbol

Test Conditions
TJ=25°C

Output Voltage

Vo

10=5mAto lA, Pos15W
V,= -11.5to -23V

Min

lYP

Max

-7.7

-8

-8.3

-7.6

-8

-8.4

/;,Vo

Ti=25°C

160
mV

V,=-llto
-17V

80

TJ",25°C
10 =5mA to 1.5A
Load Regulation

160

/;,Vo

I.

Quiescent Current Change

/;,1.

80

3

TJ=25°C

1

V, = - 11.5 to - 25V
/;,Vo

6T

Output Noise Voltage

6

mA

0.5

10=5mAto lA

Output Voltage Drift

II

mV
TJ=25°C
10 =250 to 750mA

Quiescent Current

V

I

V,= -10.5to
-25V
Line Regulation

Unit

mA

10=5mA

-0.6

mVfOc

VN

f = 10Hz to 100KHz
TJ=25°C

175

/LV

Ripple Rejection

RR

f=120Hz
/;,V,=10V

60

dB

Dropout Voltage

VD

TJ=25°C
10=lA

Short Circuit Current

Ise

Peak Current

Ipeak

ciS

54

2

V

TJ=25°C

1.5

A

TJ=25°C

2.5

A

SAMSUNG SEMICONDUCTOR

381

LINEAR INTEGRATED CIRCUIT

MC79XX SERIES

ELECTRICAL CHARACTERISTICS MC7912C
(CI =2.2,.F, Co = l,.F" Tj =0 to 125°C, 1.=500mA, Vi ';'18V, unless otherwlse'specified)

Characteristic

Outpu1 Voltage

Line Regulation

Load Regulation

Quiescent Current

Symbol

V.

/::,.V.

Test Conditions

Min

'iYP

Max

Tj=25°C

-11.5

-12

-12.5

-11.4

-12

-12.6

1.=5mA to lA, P.s15W
VI= -15.5to -27V
Vi= -14.5to
-30V

240

Vi= -16to
-22V

120

I

Tj =25°C
1.=5mA to 1.5A

240

TJ =25°C
I. =250 to 750mA

120

rrW

3

Tj =25°C

6

mA

0.5

I. ,.5mA to lA
, Quiescent Current Change

V

mV

Tj = 25°C

/::,.V.

Id

Unit

/::"Id

1

VIZ -15to -30V

mA

Output Voltage Drift

/::,.V.
/::,.T

1... 5mA

-0.8

rrWf'C

Output Noise Vohage

VN

f = 10Hz to 100KHz
Tj ",,25°C

200

,.V

Ripple Rejection

RR

f=120Hz
/::,.VI=10V

60

dB

Dropout. Voltage

Vo

Tj =25°C
1.-1A

2

V

Short Circuit Current

I""

Tj ';'25°C

1.5

A

Peak Current

lpeak

Tj =25°C

2.5

A

c8

SAMSUNG SEMICONDUCTOR

54

382

LINEAR INTEGRATED CIRCUIT

MC79XX SERIES

ELECTRICAL CHARACTERISTICS MC7915C
(C, = 2.2/.1F, Co = 1/.1F, T, = 0 to 125°C, 10 = 5OOmA,
Symbol

Characteristic

v, = 23V, unless otherwise specified)

Test Conditions
TJ =25"C

Output Voltage

Vo

Line Regulation

6.Vo

Load Regulation

10=5mA to 1A, PoS15W
V,=-18to -30V

Min

~p

-'14.4

-15

-15.6

-14.25

-15

-15.75.

Max

V,= -17.5to
-30V

300

V,: -20to
-26V

150

I.

Quiescent Current Change

6.1.

V

mV

Tj =25°C

TJ =25°C
lo=5mA to 1.5A

300

Tj =25"C
10 =250 to 750mA

150

I

rrt./

6.Vo

Quiescent Current

Unit

3

TJ =25°C

6

mA

0.5

lo=5mAto 1A

1

V, = -18.5to -30V

mA

Output Voltage Drift

6.Vo
6.T .

lo=5mA

-0.9

rrt.//"C

Output Noise-Voltage

VN

f = 10Hz to 100KHz
Tj =25°C

250

/.IV

RR

f=120Hz
6.V, =10V

60

dB

Vo

Tj =25°C
lo=1A

2

V

Short Circuit Current

I..

Tj =25°C

1.3

A

Peak Current

lpeak

TJ =25"C

2.2

A

,

Ripple Rejection

Dropout Voltage

c8

SAMSUNG

SE~IC9NDUCTOR

54

383

MC79XX SERIES

LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS MC7918C
(C,=2.2,..F, Co ·=1,..F, TJ=O to 12S0C, 10=500mA, V,=27V, unless otherwise specified)

Characteristic

Output Voltage

Symbol

Vo

Test Conditions

Min

Typ

Max

TJ=25°C

-17.3

-18

-18.7

-17.1

-18

-18.9

10=5mA to 1A, PoS 15W
V,= -22.5 to -33V

Load Regulation

Quiescent Current

/',Vo

/',Vo

Id

. 360

V;= -21 to
.
-33V
TJ=25°CrV;= -24to
-30V

I
mV

I

180
._-

TJ =2SoC
lo=SmAt01.5A

360

TJ=25°C
10 =250 to 750mA

180

mV

3

T,=25°C

/',Id

1

V,= -22to -33V
Output Voltage Drift

/',Vo
/',T

6

mA

O.S

10=5mAto 1A
Quiescent Current Change

V

I

.1

Line Regulation

Unit

lo=5mA

mA

-1

mVI"C

300

,..V

----

Output Noise Voltage

V N'

f = 10Hz to 100KHz
TJ =2SoC

Ripple Rejection

RR

f=120Hz
/',V,=10V

54

60

dB
-----

Dropout Voltage

VD

TJ =25°C
lo=1A

Short Circuit Current

loe

T,=2SoC

Ipeak

TJ7 25°C

Peak Current

c8

- - f--

SAMSUNG SEMICONDUCTOR

2

V

1.1

A

2.2

A

384

LINEAR INTEGRATED CIRCUIT

MC79XX SERIES

ELECTRICAL CHARACTERISTICS MC7924C
(C,=2.2/LF, Co=1/LF, TJ=O to 125°C, 10=500rnA, V,=33V, unl.ess otherwise specified)
CharaCteristic

Output Voltage

Symbol

Vo

--

Max

Test Conditions

Min

Typ

TJ=25°C

-23

-24

-25

-22.8

-24

-25.2

r---

10= 5rnA to 1AJPo:!>15W
V,= -27to -38V

Unit

V

-

Line Regulation

6Vo

TJ=25°C

_.

V,= -27to
-38V

480

V,= -30to
-36V

240

rnV
- - f---.

load Regulation

Quiescent Current

Quiescent Current Chang,e

TJ=25°C
10 =5mA to 1.5A

480

TJ=25°C
10 =250 to 750mA

240
3

TJ=25°C

10

610

1---

6Vo ,

LS:T

6

rnA

0.5

10=5mAto 1A

1

V,= -27to -38V
Output Voltage Drift

mA

I

10=5mA

-1

mV/oC

400

/LV

60

dB

Output Noise Voltage

VN

f = 10Hz to 100KHz
TJ=25°C

Ripple Rejection

RR

f=120Hz
6V,=10V

Dropout Voltage

VD

TJ=25°C
10=lA

2

V

Short Circuit Current

Iso

TJ=25'C

1.1

A

Peak Current

Jpeak

TJ=25°C

2.2

A

c8

I

mV

6Vo

SAMSUNG SEMICONDUCTOR

54

385

LINEAR INTEGRATED CIRCUIT

MC79XX SERIES
APPLICATION INFORMATION
Fig. 1 -:- Fixed output regulator

Note.:

~~-O-Vo

Fig. 3 - Circuit for increasing output voltage

Fig. 2 - Split power supply (±1SVl1A)

+2fN

.

(1) To specify an output voltage, substitute voltage value for
"XXC".
(2) Required for stability. For value given, capacitor must be solid
tantalum. If aluminium electrolitics are used, at least ten times
value shown should be selected. CI is required if regulator is
located an appreciable distance from power supply filter.
(3) To improve'transient response. If large capacitors are used, a
high current diode from input to output (1N4001 or similar)
should be introduced to protect the device from momentary input short ~ircuit.

0--.,.--1

-2fN

-15V
R1+R2

."!i2"

• Against potential latch-up problems.

Vo-VXX'
VXXIR2 > 31d

• C3 optional for impi'Oved transient response and
ripple rejection.

Fig. 4:"" High current negative regulator (-SVI4A with
SA current limiting)

-lOll

Fig. S - Typical ECl system power supply (-S.2VI4A)

-12\1

• Optional dropping resistor to reduce the power
dissipated in the boost transistor.
.

c8

SAMSUNG SEMICONDUCTOR

386

MC79XX SERIES

LINEAR INTEGRATED CIRCUIT

3-TERMINAL O.SA NEGATIVE
VOLTAGE REGULATOR

TO-220

The MC79MXXlseries of 3-Terminal medium current negative voltage
regulators are monolithic integrated circuits designed as fixed voltage
regulators. These regulators employ internal current limiting, thermal
shutdown and safe-area compensation making them essentially indestructible. If adequate heat sinking is prOVided, they can deliver up to
500mA output current. They are intended as fixed voltage regulators in
a wide range of applications including local (on-card) regulation for elimination of noise and distribution problems associated with single point
regulation. In addition to use as fixed voltage regulators, these devices
can be used with external components to obtain adjustable output
voltages and currents.

I

FEATURES
•
•
•
•
•
.•

Output current In excess of O.SA
Internal thermal-overload protection
Internal short circuit current limiting
Output trenslstor safe-area compensation
Available In JEDEC TO·220
Output voltages of - 5V, - 6V, - 8V, -12V,
-15V, -18V, - 24V

1: GND 2: Inpul 3: Oulpul

ORDERING INFORMATION
Operating Temperature

o -125°C

SCHEMATHIC DIAGRAM
Rll

R14

R12

R15,

R16
r---~------+-OOUT

R23
L---~--~--~~----~~------------~~~------

c8

SAMSUNG SEMICONDUCTOR

________ __ ____________
~

~

~~IN

387

MC79MXX. SERIES

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Input Voltage (for Vo = - 5V to - 1.8V)
(for Vo=24V)
Thermal Resistance
Junction-Case
Junction-Air
Operating Temperature Range
Storage Temperature Range

VI
VI

9 Jc

value

Unit

-35

V
V

-40
5
65
0-+125
-65-+150

·

9JA

Top.
Tsig

°CIW
OCIW

OC
°C

TYPICAL APPLICATION
Bypass capacitors are recommended for stable operation of the
MC79MXXC series of regulators over the input voltage and output
current ranges. Output bypass capacitors will improve the transient
response of the regulator.
.
The bypass capacitors, (2,..F on the input, 1,..F on the output) should be
ceramic or solid tantalum which have good high frequency characteristics. If aluminum electrolytiqs are used, their values should be 1O,..F or
larger. The bypass capacitors should be mounted with the shortest leads,
and if possible, directly across the regulator terminals.

Fixed Output Regulator

VIN

--...----1
2.0~F

ciS SA~SUNG SEMICONDUCTOR

I - -......--VOUT
l.o~F

388

LINEAR INTEGRATED CIRCUIT

MC79XX SERIES

ELECTRICAL CHARACTERISTICS MC79M05C
(Refer to test circuit, O°C

ELECTRICAL CHARACTERISTICS
(Ta = 25·C, unless otherwise noted)

Characteristic

Symbol

Test Conditions

Min

Typ

Max

1.205

1.235

1.260

V

8

15

".A

0·CsTas70·C,lm;ns IRs1mA
0·CsTas70·C, 1mAsIRs20mA

1.5
25

mV
mV

Im;nSIRS 1mA
.1mAslRs20mA

1
20

mV

Reverse Breakdown Voltage

VR

Im'nSIRs20mA

Minimum Operating Current

Imin

O·C sTas 70·C

Reverse Breakdown Voltage
Change with Current

l::,vR

Reverse Dynamic Impedance

ZD

>

Average Temperature
Coefficient

Unit

0·CsTas70·C, IR = 100".A

0.4

1.5

0

IR = 100".A

0.4

1

0

0·CsTas70·C, 10p.AsiRs20mA

20

ppm/·C

Wide Band Noise (RMS)

EN

IR=100".A,10HzSfS10KHz
0·CsTas70·C

60

".V

long Term Stability

S

IR = 100".A

20

ppm/KHR

c8

SAMSUNG SEMICONDUCTOR

398

KA38S·1.2

LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS
TEMPERATURE DRIFT

REVERSE DYNAMIC IMPEDANCE
10K

T,,=25-C

-

IA=100~

1K

~

/

l/
25

B5

45

B5

/

o. 1

. 10

1K

100

10K

1M

100K

TEMPERATURE ('c)
Fig. 1

FREQUENCY(IIzj

NOISE VOLTAGE

FILTERED OUTPUT. NOISE

Fig. 2

~

1.~1(!o~~
eoo

60

r--...
r--""

111111

111111

SINGLE POLE LOW PASS

/'
ioo"

V

200

1\
10

1K

100

10K

FREQUENCY (Hz)
Fig. 3

KHARP CUTOFF FILTER

~ioo"
100K

11111111

0
100

1K

10K

100K

CUTOFF FREQUENCY (Hz)
Fig. 4

ReSPONSE TIME

/

OUTPUT

~
10

INPUT

200

400

eoo

TIME",")

Fla.5

ciS

SAMSUNG SEMICONDUCTOR

399

LINEAR INTEGRATED CIRCUIT

KA38S·1.2
STANDARD APPLICATIONS
MICROPOWER REFERENCE FROM 9V
BATTERY

REFERENCE FROM.1.SV BATTERY
1.5V

9V

500K
1.2V
1.2V

KA385-1.2

KA385-1.2

c8

SAMSUNG SEMICONDUCTOR

400

KA431

LINEAR INTEGRATED CIRCUIT

PROGRAMMABLE PRECISION REFERENCES
. The KA431 is a three-terminal adjustable regulator series with
guaranteed thermal stability over applicable temperature ranges. The
output voltage may be set to any value between Vre, (approximately 2.5
volts) and 36 volts with two exterrial resistors. These devices have a
typical dynamic output impedance of 0.20. Active output circuitry
provid~ a very sharp turn-on characteristic, making these devices
excellent replancement for zener diodes in many applications .

1: Ref. 2: Anode 3: Cathode
8 DIP

. FEATURES
•
•
•
•
•

Programmable output voltage to 36 volts
Low dynamic output impedance 0.20 typical
Sink current capability of 1.0 to 100mA
Equivalent full-range temperature coefficient of 50ppm/o C typical
Temperature compensated for operation over full rated operating
temperature range
• Low output noise voltage

8 SOP

1: Cathode 6: Anode 8: Ref.
2, 3, 4, 7: N.C.

1: Cathode 2, 3, 6, 7: Anode 8: Ref.
4,5: N.C.

BLOCK DIAGRAM

ORDERING INFORMATION

i --- -------,

REFERENCE

I
I

CATHODE

Device

I

f

ATHODE(K)

REFERENCE (R) 0 .

Operating Temperature Package

KA431CZ

0-+ 70·C

KA431CN

0-+ 70·C

TO-92
8 DIP

KA431 CD

0-+70·C

8 SOP

KA4311Z

-40-+85·C

TO-92

KA431 IN

-40-+85·C

8 DIP

ANODE (A)

SCHEMATIC DIAGRAM
CATHODE

02

ANODE

cIS SAMSUNG SEMICONDUCTOR

401

I

LINEAR INTEGRATED CIRCUIT

KA431
ABSOLUTE MAXIMUM RATINGS

(Operating temperature range applies unless otherwise specified.)
Characteristic
Cathode Voltage
Cathode Current Range (Continuous)
Reference Input Current Range
Power Dissipation
D, Z Suffix Package
N Suffix Package
Operating Temperature
KA431CZ, KA431CN, KA431CD
, KA4311Z, KA4311N
Operating Junction Temperature
Storage Temperature Range

Symbol

Value

Unit

VKA
IK
're,
Po

37
-100-+150
0.05 - + 10

V
rnA
mA

770
1000

,mW
mW

0-+70
-40-+85
150
-65-+150

·C
·C
·C
·C

Topr

Tj
T.tg

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbol

Min

VKA
IK

Vre,
1.0

Cathode Voltage
Cathode Current

ELECTRICAL CHARACTERISTICS
Characteristic

Reference Input Voltage
Deviation of Reference Input
Voltage Over Temperature 1
Ratio of Change in Reference
Input Voltage to the Change
in Cathode Voltage

Symbol

Vref

Vref(dev)

Typ

Max

Unit

36
100

V
mA

(Ta=25·C, unless'otherwise specified)
Min

Typ

Max

Ta=25·C

2.440

2.495

2.550

Ta=O·C
to 70·C

2.423

Test Conditions
VKA = Vref
IK=10mA

VKA=V re" ' K=10mA
Ta=O·C to 70·C

2.567
8

17

VKA=Vre,
to 10V

-1.4

-2.7

VKA = 10V
to 36V

-1.0

-2.0

Ta=25·C

1.8

4.0

Unit

·T/C

V

1

mV

1

mVN

2

p.A

2

Vref
VKA

1i<=10mA

Reference Input Current

Iref

IK= 10mA
R1 = 10KO
R2=oo

Reference Input Current
Deviation Over Temperature
Range

lref

IK = 10mA, .R1 = 10KO
R2=oo
Ta = O·C to 70·C

0.4

1.2

p.A

2

-

Ta=O·C
to 70·C

5.2

Minimum Cathode Current
for Regulation

IKmin

VKA=V re,

0.5

1.0

mA

1

Off-State Cathode 'Current

IKoff

VKA =36V, Vref=OV

2.6

1000

nA

3

ZKA

VKA=Vref
IK= 1.0 to 100mA
fS1.0KHz

0.22

0.5

0

1

Dynamic Impedance 2,
• Test Circuit

c8

SAMSUNG SEMICONDUCTOR

402

LINEAR INTEGRATED CIRCUIT

KA431

Note: 1. The deviation parameters VrelldOv) and Ire~dOY) are defined as the differences between the maximum and
minimum values obtained over the rated temperature range. The equivalent full-range temperature coefficient
of the reference input voltage, aVrel, is defined as:

'~-I

Max VTOI Min V,"I 6 TA Vre~dev)

aVrel

(

~

( °e) =

Vref!d~1

Vrel @25°e
6TA

L=±
I
I

) x 10"

where 6 TA is the rated operating free-air temperature range of the device.
aVrel can be positive or negative depending on whether minimum Vrel or maximum Vre" respectively, occurs
at the lower temperature
Example: Max V..,=2500mV@30oe, Min V..,=2492mV@Ooe, V..,=2495mV@25°e, 6 TA=70oe forKA431e

aV re,

8mV
(2495rTiV) x 10"
°
700C
= 46ppml e

II

Because minimum Vre, occurs at the lower temperature, the coefficient is positive.
2. The dynamiC impedance is defined as:
ZKA

When the device is operated with two external resistors (see Figure 2), the total dynamic impedance of
the circuit is given by:
Z'

_ 6V _
. - 61 -

TEST CIRCUIT
Fig. 1 Test Circuit for VKA=Vre,
INPUT o---'\j"""'~p----o VKA

Fig. 2 Test Circuit for VKA~Vre'
INPUT

o-~Wo~-.-----O

VKA

Rl

KA431

R2

Vref

VKA

=Vre t

i

'"

30

35

2O~t+~m-~~~-+~#m~t+~

40

f-frequency-Hz
FIGURE 7

SMALL SIGNAL VOLTAGE AMPLIFICATION
VS FREQUENCY

DYNAMIC IMPEDANCE VS FREQUENCY
100
70

1
2
V..-~VoI""-V
FIGURE 6

I\,

I

1-

r

70
T,,=25°0
11(=10mA

T,,=25°0
IK=1mA to 100mA

20

60

.......

II'

10

IJ""~

7

1\1'1
0.7
0.4

0.2
0.1

-10
lK

10k

lOOK
f-Fraquency-Hz
FIGURE 8

1M

ciS SAMSUNG SEMICONDUCTOR

10M

lK

10K

,"

lOOK
1M
f-Fraquenc:y-Hz
FIGURE.

10M

404

KA431

LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS

(Continued)

PULSE RESPONSE
T.=i2S0C
LT

UTPUT

1

2

V

II

1

t-Time-us
FIGURE 10

TYPICAL APPLICATIONS
FIGURE ll-SHUNT REGULATOR

v+

FIGURE l2-SINGLE-SUPPLY COMPARATOR WITH
TEMPERATURE-COMPENSATED THRESHOLD

Q-Jw.-~--~---,.-OVOUT

V+

~--oOUTPUT

INPUT o--w..H~
V(lh}= 2.5V

Von=2V
Voff=V+

KA431

o---~-+------o

FIGURE.13-SERIES REGULATOR
V+O-~---------~

FIGURE l4-0UTPUT CONTROL
OF A THREE-TERMINAL
FIXED REGULATOR

GND

FIGURE l5-HIGHER-CURRENT
SHUNT REGULATOR

V+D-------.,
...-~_oVoul

KA431

c8

SAMSUNG SEMICONDUCTOR

405

LINEAR INTEGRATED CIRCUIT

KA431
TYPICAL APPLICATIONS

(Continued)

FIGURE 16-CROW BAR

FIGURE 17-0VER·VOLTAGE/UNDER·VOLTAGE
PROTECTION CIRCUIT

V+

KA431

v +o-~--~:-1'-----,

OUTPUT ON
WHEN
LOW,
HIGH
LlMITV re f

Low limit = Vref (1 +

~~~) + V,BE

High limit = V,.d1 + ~~~)

FIGURE 18-VOLTAGE MONITOR

R2A

FIGURE 19-DELAY TIMER

KA431

KA431

..
(1 R1B)
Lo w l,m,t=Vref
+R2B

V+
Delay=R·C·ln (V+)-V,ef

High limit = V,.d1 + ~~~)

FIGURE 20-CURRENT LIMITER OR
CURRENT SOURCE

FIGURE 21-CONSl'ANT·CURRENT SINK
Vi-

lout

V+

KA431
Vref
lout= RCL,

c8

SAMSUNG SEMICONDUCTOR

Vref

lout=rs

406.

LINEAR INTEGRATED CIRCUIT

KA201A1KA301A
SINGLE OPERATIONAL AMPLIFIER

8 DIP

The KA201A and KA301A are general-purpose operational amplifiers
which are externally phase compensated, permit a choice of operation
for optimum high-frequency performance at a selected gai,n: unity-gain
compensation can be obtained with a single 30pF capacitor,

FEATURES
•
•
•
•

8 SOP

Unlty-gain phase compensation with a single 30pF
Short-circuit protection and latch-free operation
Slew rate of 10Vlp.s as a summing amplifier
Class AB output provides excellent linearity

BLOCK DIAGRAM
NULUCOMPENSATION

I

I

ORDERING INFORMATION
Device

8 COMPENSATION

KA201AN
KA301AN
KA201AD
5 OFFSET NULL

KA301AD

Package
S DIP

ssop

Operating Temperature
-25·C -

+S5·C

O·C - 70·C
-25·C O·C -

+S5·C
+ 70·C

COMP,
NULL COMP,

SCHEMATIC DIAGRAM
----~--~VCC

INVERTING
INPUT - O - - - , - - - i - - - - - t - - - {
NON·INVERTING
INPUT + O-~--+-----I

Rll
25!l

'---j----<> OUTPUT

L--+-~~-L-~-+--------~------+--+-~---oVEE

OFFSET NULL

c8

SAMSUNG ,SEMICONDUCTOR

407

KA201A1KA301A

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

KA201A

KA301A

Unit

Supply Voltage
Differential Input Voltage
Input Voltage
Output Short Circuit Duration
Power Dissipation
Operating Temperature Range
Storage Temperature Range

Vs
Vto
V,

±22
±30
±15
Continuous
500
-25-+85
-65 - +150

±18
±30
±15
Continuous
500
0-+70
-65 - +150

V
V
V

Po
Top,
T stg

mW
·C
·C

ELECTRICAL CHARACTERISTICS
(- 25·CsTas + 85·C for the KA201A, O·CsTas + 70·C for the KA301A, unless otherwise specified)

Characteristic

Input Offset Voltage

Symbol

V,O

Test Conditions
Rss50KO

Typ Max Min
0.7

1.5

1,0

30

1'8

Is

3

70

75

1.8

3.0

1.2

2.5

50

Tamin,STa::sTamax

25

Av

Average Temperature
Coefficient of Input
Offset Voltage

1':,v,olf:,T TaminSTaSTama><

Average Temperature
Coefficient of Input
Offset Current

f:,1,oIf:, T

Input Voltage Range

VieR

160

mV

10

mV

50

nA

70

nA

250

nA
nA
mA

1.8

Vee = ± 15V, RL~2KO, Vo = ± 10V

Unit

7.5

300

Vs=±15V
Vs= ±20V, Ta=Tam..

Large Signal Voltage Gain

10

100

TamlnSTaS Tama><
Vs= ±20V

Supply Current

2.0

20

TaminSTaSTamax
Input Bias Current

2.0

Typ Max

3

T aminSTaSTama><
Input Offset Current

KA301A

KA201A
Min

3.0

mA
mA

25

V/mV

160

15

V/mV

3.0

15

6.0

30

,.V/·C

25·CS TaS Tamax

0.01

0.1

0.01

0.3

nArC

T aminSTaS25·C

0.02

0.2

0.02

0.6

nAl·C

Vs= ±20V

TaminSTaSTamax

Vs=±15V

TamlnSTaSTama><

±15

V
±12

V

Common-Mode Rejection
Ratio

CMRR

RsS50KO

TaminSTaSTamax

80

96

70

90

dB

Power Supp,ly Rejection
Ratio

PSRR

Rss50KO

TamlnSTaS Tamax

80

96

70

96

dB

Output Voltage Swing

Your

Input Resistance

R,

Slew Rate

SR

c8

Vs=±15V

SAMSUNG SEMICONDUCTOR'" '

RL=10KO

±12 ±14

±12 ±14

RL=2.0KO

±10 ±13

±10 ±13

1.5

0.5

4.0
0.5

V
V

2.0

MO

0.5

V/,.s

408

KA201A1KA301 A

LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS
SUPPLY CURRENT

VOLTAGE GAIN
120

2.5

2.0

,....
.-. ~

5

-

Ta=25-C

'110

--

0

I-- ~

90

o.5

10

15

10

20

SUPPLY VOLTAGE (%V)
FIg. 1

--

- -

15

II

20

SUPPLY VOLTAGE (%V)
Fig. 2

CURRENT, LIMITING

15

Ta=2S"C

COMMON MODE REJECTION
120

VS~ ±15V

-....

'\

100

Ta=25"C

80

-~

I
R,= 11<0
Ta=25°C

~ l!

VCM'5. ± lOV

60

40

"

>-.

VCM::S;::tW

I

20

10

15

25

20

OUTPUT CURRENT

30

«::t mAl

10

100

1K

10K

100K

1M

FREQUENCY (Hz)
Fig. 4

Fig. 3

POWER SUPPLY REJECTION

100

,

l'.

"'

C1=30pF
Ta=25"C_

"'\

~

"\

~'\

I"'\.'\:~
,"'~

~J-

~~<.

~

~J-

""

~

~

0
10

100

1K

10K

100K

"'

~
I000o

1M

10M

FREQUENCY (Hz)
Fig. 5

c8

SAMSUNG SEMICONDUCTOR

409

KA201 AlKA301 A

LINEAR INTEGRATED CIRCUIT
. OPEN LOOP FREQUENCY RESPONSE,

SINGLE POLE COMPENSATION
120

T8=~·C

100

INPUT

~

"

eo

> - - - 4 - - 0 v""

II,

iii:

II

z eo

".
C

!II

v'Tsv-

~

.0

~C1~ ~=3PF

~

PHjE

~r'\.

r'\.

~

20

225

SINGLE POLE
FIg. •

~

""-

~AIN

GAlj\

-20
10

100

1K

10K

100K

1M

10M

FREQUENCY (HII
FIg. 7

VOLTAGE FOLLOWER PULSE RESPONSE

LARGE SIGNAL FREoUENCY RESPONSE
16

10

T~=~·b

r=~Tc

Vs= ±15V

V.=::t15V

-

12
C1=3pF

~

I."

1\

1\

0

>

SINGLE POLE

~
1K

10K

100K

1M

1\

I

-2

1\
\

-6

SI~~LE iLE

-. - -- --

-10
10

10M

20

30

.0

120

R,

"

100

-V~o-_-L--l

>--+-OV""
z

eo

"'

.0

~

c,iit/,ft

\

1\

~
20
Ta=25-C
Vs = ±15V
C1=30pF
C2=jF
10

"

f'\

-20
1

100

lK

10K

FREQUENCY (HII
FIg. 11

SAMSUNG SEMICONDUCTOR

225

GA~

Cs=3OpF
Cs=1QC,

""" 10

~POLE

'\ ",ASEI'- J

eo
iii:
S

;

c8

eo

OPEN LOOP FREQUENCY RESPONSE

TWO POLE COMPENSATION

+V~o-<_---I

70

Flg.8

FIg. '.

II,

eo

50

TIMEfpa)

FREQUENCY (HII

INPUT

7

IJOUTPUT

-8

.....

~~

o

~

\

e

C1=3OpF

-- -

INPUT '

100K

1M

10M

410

KA201A1KA301A

LINEAR INTEGRATED CIRCUIT

LARGE SIGNAL FREQUENCY RESPONSE
18

VOLTAGE FOLLOWER PULSE RESPONSE
10

J,J±I,~
Ta=25-C
Cl=3O!>F
C2=3OOpF

1\

12

1\

J

~

1

IE

!i!

1\
~

OUTPUT

\
\

w

"~

-2
-4

--

-6

Ta=25-C
Vs = ±15V
Cl=3O!>F

rjpF

-6

~
lK

I-----

.1 .

-~.

INPUT

\

i"

TWO'~L~

\

JoJLE_

-10
10203040

1M

lOOK

80807080

FREQUENCY (HI!
FIg. 12

TIllE"",)

FEEDFORWARD COMPENSATION

OPEN LOOP FREQUENCY RESPONSE

FIg. 11

120
C,
100

-

""

80

" "\

Iii
:g,

R,
INPUT

V"",

~

'"
~
0

~15V

Va=
T.=25·C _

r-....

80

w

R,

180

~

40

135

PHASE/--

~

'V

90

'\

>

20

C,

225

45

~IN

FEED FORWARD

<4= 2'1'f:R2
fo=3MHz

'"

FIg. 14
-20
10

100

lK

10K

lOOK

1M

10M

100M

FREQUENCY (HI!
FIg. 15

INVERTER PULSE RESPOSE

LARGE SIGNAL FREQUENCY RESPONSE
18

12

~.~~!d

nrn

\
\

lOOK

1\

'""

-8

1M

SAMSUNG SEMICONDUCTOR

-

- --- -- -- -- I

JPUT

-

INPUT

-FEE~F0'rARDI

-6

r--..

FREQUENCY (HI!
FIg. 11

c8

1\

~

FEED FORWARD

~

o

10

-- - --

.

T8=25-C
1'= ±1'5V

-10
10M

1020304080807080

TIllE .....
FIg. 17

411

LINEAR INTEGRATED CIRCUIT

KA733C
.DIFFERENTIAL VIDEO AMPLIFIER

14 QIP

The KA733C is a monolithic differential input, differential output,
wideband video amplifier.
The use of internal series-shunt feedback gives wide bandwidth with
low phase distortion and high gain stability. The KA733C offers fixed
gains 10,100,400 without external components, and adjustable gains from
10 to 400 by use of an external resistor.
The KA733C is intended for use as a high performance video and pluse
amplifier in communications, magnetic memories, displays and video
recorder systems. .

14 SOP

FEATURES
•
•
•
•

120MHz bandwidth
250KO input resistance
Selectable gains of 10,100,400
No frequency compensation required

BLOCK DIAGRAM
ORDERING INFORMATION
G2A GAIN
12 SELECT

G28 GAIN
SELECT
G'8 GAINT
SELECT

11

~~~~;~N

Device

Package

KA733CN

14 DIP

KA733CD

14 SOP

Operating Temperature
0-+70·C

SCHEMATIC DIAGRAM

INPUT2

o--~-t===E~~=tt1:=+::::::!J

INPUT1
L--+----"."..-~----+---o OUTPUT1

GAIN SELECT

7K
G2B

L---r--"M~+-----1~--o

OUTPUT2

. GAIN SELECT {
G1B

400
VEe

c8

SAMSUNG SEMICONDUCTOR

412

LINEAR INTEGRATED CIRCUIT

KA733C
ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Differential Input Voltage
Common mode input Voltage
Power Supply Voltage
Output Current
Power Dissipation
Operating Temperature Range
Storage Temperature Range

V ,O
V,
Vs
10
Po
Top,
T stg

±5
±6
±B
10
500
0-+70
-65- + 150

V
V
V
mA
mW
·C
·C

ELECTRICAL CHARACTERISTICS
(Vcc= +6V, VEE = -6V, Ta=25·C, unless otherwise specified)
Characteristic
Differential Voltage Gain
Gain 1 (Note 1)
Gain 2 ( " 2)
Gain 3 ( " 3)
Bandwidth
Gain 1 (
Gain 2 (
Gain 3 (
Rise Time
Gain 1 (
Gain 2 (
Gain 3 (

"
"
"

··
·
··
·
··
·

Test
Figure

Symbol

Av

1

2

BW

1)
2)
3)

2·

. Input Resistance
Gain 1 (
1)
Gain 2 (
2)
Gain 3 (
3)

RL = 2KIl, YOU! = 3V p.p

Min

Typ

Max

Unit

250

400
100
10

600
120
12

VIV

80
8

1)
2)
3)

Propagation Delay
Gain 1 (
1)
Gain 2 (
2)
Gain 3 (
3)

Test Conditions

Rs = 501l

40
90
120

t,

Rs = 501l
Your = 1Vp.p

10.5
4.5
2.5

12

ns

2

tpd

Rs = 501l
Vour = 1Vp.p

7.5
6.0
3.6

10

ns

3

Ri

VooS1V

10

MHz

4.0
30
250

KIl

Input Offset Current

1'0

0.4

5

Jl.A

Input Bias Current

liB

9

30

Jl.A

Input Voltage Range
Common Mode Rejection Ratio
Gain 2
Gain 2
Power Supply Rejection Ratio
Gain 2
Output Offset Voltage
Gain 1
Gain 2 and 3

V

V'CR

4

CMRR

VOM= ±1V, fS100KHz
VCM = ±1V, f=5MHz

60

86
60

dB
dB

1

PSRR

6Vs= ±0.5V

50

70

dB

1

Voo

Input CapaCitance

c8

±1

1

SAMSUNG SEMICONDUCTOR

RL=oo

0.6
0.35

Gain 2

2.0

1.5
l.5

V
V
pF

413

I

KA733C

LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTIC
Characteristic

(COntinued)

Test
Symbol
Figure

Test Conditions

Min

Typ Max Unit

Output Common Mode Voltage

1

VOCM

RL=OO

2.4

2.9'

Output Voltage Swing

1

VOUT

RL=2KO

3.0

4.0

V

2.5

3.6

mA

Output Sink Current
Power Supply Current

ISink
1

Is

RL=OO

18

Ro'

Output Resistance .

3.4

24

20

V

mA
()

ELECTRICAL CHARACTERISTICS
The following specifications apply over the range of 0·CsTas70·C Vee = +6V, Vee = -6V

Characteristic
Differential Voltage Gain
Gain 1 (Note 1)
Gain 2 (Note 2)
Gain 3 (Note 3)

Test
Symbol
Figure

1

Av

Input Bias Current

Test Conditions

RL=2KO
Vout =3Vp-p

Min

:ryp Max

Unit

250

600
120
12

VN

80
80

liB

Input Offset Current

110

40

p.A

6.0

p.A·

Input Voltage Range

1

ViCR

±1.0

V

Input Impedance (Gain 2)

3

Ri

8.0

,KO

Common Mode Rejection Ratio
Gain 2 (Note 2)

4

CMRR

50

dB

Power Supply Rejection Ratio
Gain 2 (Note 2)

1

PSRR

50

dB

1

Voo

1

VoP

2.8

Islnk

2.5

Output Offset Voltage
Gain 1 (Note 1)
Gain 2 and Gain 3 (Note 2, 3)
Output Voltage Swing
Output Sink Current
Power Supply Current

VCM = ±1V, fS100KHz
~,.vee=

±0.5V
/';Vee= ±0.5V

Is

1.5
1.5

V
V
mA

27

mA

Notes 1. Gain select pins G'A and G'B connected together.
2. Gain select pins G2A and G2B connected together.
3. All gain select pins open.

c8

SAMSUNG SEMICONDUCTOR

414

KA733C

LINEAR INTEGRATED CIRCUIT

PARAMETER MEASUREMENT INFORMATION
TEST CIRCUITS

VOD

2KO

1KO

Fig. 1

o

[

V

Fig. 2

II

500

vool

~2~

500
VIC

1KO

Fig. 4

Fig. 3

VO D

2KO

2A

VOLTAGE AMPLIFICATION ADJUSMENT
Fig. 5

c8

SAMSUNG SEMICO~DUCTOR

Fig. 6

415

KA733C

LINEAR INTEGRATED CIRCUIT

. TYPICAL PERFORMANCE CHARACTERISTICS
PHASE SHIFT va FREQUENCY

-5

IfB

e.

"

,

.......

'~

-10

~t'-

N

1\

~\

GAIN 2

1'..

,

~:~:S~6-

~

I"

-15

i

-

-50

~

ill1&1

PHASE SHIFT va FREQUENCY
0

:

"

1\\

~\:l'jj

'1'.

-20

-300
-25

.,

~\ GAIN
,

2

GAIN 1

-350

o

i:~~~~-

10

10

FREQUENCY (MHz)

1000

50
100
FREQUENCY (MHz)

Fig. 7

Fig. 8

VOLTAGE GAIN va FREQUENCY

PULSE RESPONSE
1.6

60

1.4
50

GAIN 1

,

iii"

.....

ll-

z

~

40
GAIN 2

w

"~

30

w

20

..

~.
i..I\~

GAIN 3

Z

...
"illz

~
w

Vs= ±6V

Ta=25°C

::'"

~

w
III

1.2

10

10

50

Gi

"c!:;
~

0.6

lN3

GAIN2

"....

r/

I

::>

~

::>
0

0.4
0.2

j
. -0.2

100

500

-0.4
-15 -10

1000

-5

0

10

PULSE RESPONSE

I

1.4
1.2

~

0.4

0

1

1

Ilf
JI

GAIN 2

Ta=25"C-

5

~

0.6

10

30

35

~

0.4

15

20

1
25

I.

~AIN J Vs= ±6V

~I¥

-1

~

Ta=7O".)Ta=85"C-

25 "Ct-i,=1j -

Ta=25°C

,

O.2

RL =1KO

I

-10 -5

Ta=O·C

1.0

w
~ 0.8

Vs = ±3V

-0.2

c8

~

r·="'t

V

II

0.2

-0.4
-15

1.2

Vs= ±BV

0.6

25

TEMPERATURE

1.4

1

~ 1.0

~

v.

1.6

1.6

0.6

20

Fig. 10

PULSE REsPONSE va SUPPLY VOLTAGE

w

15

TlME(na)

FIg. 9

"...

RL =1KO

/

FREQUENCY (MHz)

~

~:::S~~-

/GAIN1

I-

~

6

1.0
0.8

2

30

35

-0.4
-15 -10

-5

10

TIME(na)

TIME·(na)

Fig. 11

FIg. 12

SAMSUNG SEMICONDUCTOR

15

25

30

35

416

KA733C

LINEAR INTEGRATED CIRCUIT
COMMON MODE REJECTION RATIO
va FREQUENCY

100

III
III

90

iii
lit

2

"~

80

~:~:5~~-

......... 1'80

"iii

50

III

~

r-.. r-.....

i

:I

8

8~

5.0

I"

4.0

~

3.0

w

r-...

II:

i

6.0

GAIN 2

~

70

z

§z

OUTPUT VOLTAGE SWING va FREQUENCY
1.0

~
!;

....."

30

Va= :t6V

Ta=2S·CRL =1KO

'\

1\

2.0

\

0

20

1.0
10

o
10K

lOOK

1M

10M

1

100M

10

FREQUENCY (Hili

50
FREQUENCY

fig. 13

100

500

FIg..14

VOLTAGE GAIN va SUPPLY VOLTAGE

DIFFERENTIAL OVERDRIVE RECOVERY TIME

I.'

10

T~=251c

1.3
80

iw
1;:

w

~

~

II:

30

"

~

o

./

o

"
"~

~

w

/

/

10

~

1.1

w 1.0
"GAIN3

'/

20

./

1.2

V

Va = ±6V
Ta=2SoC
-GAIN 2

i

II:

/

/

50

~

~

0.9
0.8

S
w 0.1
0.6
0.5

20

40

60

80

100 120

/

140

160

180 200
SUPPLY VOLTAGE (±Y)

I.

fig. 18

GAIN va FREQUENCY V8 SUPPLY VOLTAGE

7.0

80
50

6.0

iii

~:::5~~-

5.0

....."

4.0

~

~
!:i
~

I'

3.0

GAIN2

~

2.0

V

1.0

i--"'"

0
10

50

'"

100

~

30

"w
"w

20

~

10

,~

, Vytr

1\\ V•.=.±.8V-

!

\

Vr(i

-10
200

500

lK

SK

LOAD RESISTANCE (0)
fig. 17

SAMSUNG SEMICONDUCTOR

10K

-

Ta=25°C

Z

0

c8

lit

w

w

~
!;

V

,//

/

OUTPUT VOLTAGE SWING
V8 LOAD RESISTANCE

I.
~

..-r-

/

0.4

fig.

8

-

V

GAI~

II:

V

..-

~

DIFFERENTIAL INPUT VOLTAGE (my)

~

II

1000

IMHIII

1

10

100

500 1000

FREQUENCY (II"",

fig. 11

417

KA733C

LINEAR INTEGRATED CIRCUIT
SUPPLY CURReNT va TEMPERATURE

SUPPLY CURRENT va SUPPLY VOLTAGE

21

28

Losie-

I

20
2.

~

!iw
a:
a:

i!

..."
~

OJ

~V

19

/

r--.. ........

18

/

....... V,: .6V

17

'r-

16

V

12

L~

8

-60

-20

20

60
TEMPERATURE (0C)
Fig.

100

140

3
SUPPLY VOLTAGE (±Yl
Fig. 20

1.

VOLTAGE GAIN va

lL'

V

15

,.

V

R.o.

1000

"

~:~:5~6I

".... ~
["'...

1"'-1'
10
10

100

R...J (Il)

'"

""'" 10K

Fig. 21

c8 SAMSU~G SEMICONDUCTO~

418

KA9256 .

LINEAR INTERGRATED CIRCUIT

DUAL POWER OPERATIONAL AMPLIFIER
10 SIP

The KA9256 is a dual power operational amplifier and it is output
maximum current is 1.0A CVs= ± 15V). It can·be used in arm driver for
player, driver for brush motors forward and reverse rotation control and CD
output drive·r for hole motor.

FEATURES
•
•
•
•

lriteral current limiting: Isc = 350mA (Rsc = 2.20)
High output current: I. = SOOmA max
10 SIP HIS package
Internal phase compensated

II

BLOCK DIAGRAM
~----

ORDERING INFORMATION
Operating Temperature
'W
III
15
III
>

~0

>

'Z

,

;;

'Z_ tll

;;
+

>

'";;z ;;'" '"0 '"
Z

+

,

0-

W

::J

III

15

>

0
0

-20 - + 70·C

>

III

>

SCHEMATIC DIAGRAM
SENSE
r---------~--~~--~------_r----------~------lr~VCC

INVERTING
INPUT
NON·INVERTING 0---+------+--INPUT
t----+--t-i

c8

SAMSUNG SEMICONDUCTOR

,r--------t-------+--oOUTPUT

419

LINEAR INTERGRATED CIRCUIT

KA925()
ABSOLUTE MAXIMUM RATINGS
Characteristics

Symbol

Value

Unit

Supply Voltage
Output Current
Power Dissipation
Operating Temperature Range
Storage Temperature Range

Vs

±18
1.0
12.5
-20-+70
-65 -+ 150

V
A
W
,oC

10
Po
Top,
T.tg

°C

ELECTRICAL CHARACTERISTICS'
(Vee = + 15V, Vee = -15V, Ta= 25°C, unless otherwise specified)

Characteristic

Symbol

Test Conditions

Min

Typ

Max

Unit

Input Offset Voltage

VtO

2

6

mV

Input Offset Current

Ito

10

200

nA

ItB

100

700

nA

10

20

mA

Input. Bias Current
Supply Current
Output Voltage Swing
Large Signal Voltage Gain
Input Voltage Range

Is
VOUT

RL =330

±12

Av

±13

V

100

dB

VieR

±12

±14

V

Common Mode Rejection Ratio

CMRR

70

90

dB

Power Supply Rejection Ratio

PSRR'

50

150

p.v1V

Bandwidth

BW

Slew Rate

SR '

Limiting Current

los

Rsc= 2.20

0.35

A

Cross Talk

CT

RL = 330, Vo = 1Vp-p

60

dB

c8

Av=1, RL=330, R=100, C=0.1,..F

SAMSUNG SEMICONDUCTOR

1.0,

MHz

0.1!;i ,

V/,..s

420

KF351

LINEAR INTERGRATED CIRCUIT
8 DIP

SINGLE OPERATIONAL AMPLIFIER
The KF351 is JFET input operational amplifier with an internally
trimmed input offset voltage. The JFET input device provides wide
bandWidth, low input bias currents and offset currents.

FEATURES
•
•
•
•
•
•

Internally trimmed offset voltage: 10mV
Low input bias current: SOpA
Wide gain bandwidth: 4MHz
High slew rate: 13V/I's
Low supply current: 1.8mA
High input Impedance: 1012{}

BLOCK DIAGRAM.

8 SOP

II

ORDERING INFORMATION

OFFSET
NULL

Device

Package

Operating Temperature

KF351N

a DIP
a SOP

0-+ 70·e

KF351D

5 OFFSET
NULL

SCHEMATIC DIAGRAM
vcco---------~--------------~--~----~~-------------------

R5

INPUT(-)

OUTPUT
R6

-VEEo---+----+--~--------~---+--~----~--~~~--------~--~

c8

SAMSUNG SEMICONDUCTOR

421

KF351

LINEAR INTERGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Characteristics

Symbol

Value

Unit

Vs

±18
±30
±15
Continuous
500
0-+70
-65 -+ 150

'V
V
V

'Power Supply Voltage
Differential Input Voltage
Input Voltage Range
Output Short Circuit Duration
Power Dissipation
Operating Temperature Range
Storage Temperature Range

vlO
VI
Po
Top'
Tsig

mV
·C
·C

'ELECTRICAL CHARACTERISTICS
(Vee = + 15V, VeE = -15V, Ta= 25·C, unless otherwise specified)
Characteristic
Input Offset Voltage
Input Offset Voltage Drift
Input Offset Current

Symbol
VIO

Test Conditions
Rs=10K

t:"vlol£:;. T Rs=10K

, I O·C:sTa:s + 70·C
I O·C:sTa:s + 70·C

Typ

Max

5.0

10
13

10
25

ho

Input Bias Current

liS

Input Resistance

Ri

I O·C:sTa:s + 70·C
50

J O·C:sTa:s + 70·C
Vo= ±10V
RL=2Kll

Output Voltage Swing

VOUT

RL=10Kll

Input Voltage Range

VieR

25

,I O:sTa:s + 70·C

V

Rs:s10Kll

70 '

100
1.8

GBW

SAMSUNG SEMICONDUCTOR

VlmV

dB

PSRR

Av =1

II

+15

Power Supply Rejection Ratio

c8

nA

± 13.5
100

SR

pA

8

± 11
'70

Slew Rate

nA

200

±12

Rs:s10Kll

Gain-Bandwidth Product

pA

4

15

CMRR

Is

mV

100

100

C?mmon Mode Rejection Ratio
Power Supply Current

Unit

,.V/·C

1012

Av

Large Signal Voltage Gain

Min

V

dB
3.4

mA

13

V/,.s

4

MHz

422

LM2241A, LM3241A, LM2902

LINEAR INTEGRATED CIRCUIT

QUAD OPERATIONAL AMPLIFIERS

I~-----'--

The LM224 series consists of four independent, high gain, internally
frequency compensated operational amplifiers which were deSigned
specifically to operate from -a single power supply over a wide range
of voltage.
Operation from split power supplies is also possible and the low power
supply current drain is independent of the magnitude of the power supply
voltage.
Application areas include transducer amplifier, DC gain blocks and all
the conventional OP amp circuits which now can be easily implemented
in single power supply systems.

I

--------- -

14 DIP

14 SOP

FEATURES
• Internally frequency compensated for unity gain
• Large DC voltage gain: 100dB
• Wide power supply range: LM224/A, LM324/A: 3V - 32V (or :t 1.SV -16V)
LM2902: 3V - 26V (or ± 1.SV - 13V)
• Input common-mode voltage range includes ground
• Large output voltage swing: OV DC to Vcc-1.SV DC
• Power drain suitable for battery operation.

BLOCK DIAGRAM
OUT1

•

__J

ORDERING INFORMATION
OUT4

Device

Package

LM324N
LM324AN

14 DIP

LM324D
LM324AD

14 SOP

LM224N
LM,224AN

14 DIP

LM224D
LM224AD

14 SOP

;LM2902N

14 DIP

LM2902D

14 SOP

Operating Temperature

IN4 (-)
IN4 (+)

IN3 (+)

SCHEMATIC DIAGRAM (One Section Only)

INPUT

0-+70°C

-25-+85°C

-40- +85°C

R2
"-"""'-------i-oOUT

c8SAMSUNG SEMICONDUCTOR

423

II

-tM2241A, LM3241A, LM2902

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

LM224/LM224A

LM324/LM324A

LM2902

Unit

Power Supply Voltage
Differential I nput Voltage
Input Voltage
Output Short Circuit to GND
Vcc:s15V Ta=25·C (One Amp)
Power Dissipation
Operating Temperature Range
- Storage Temperature Range

Vs
v,o
V,

± 18 or 32
32
-0.3 to +32

± 18 or 32
32
-0.3 to +32

± 13 or 26
26
-0.3 to +26

V
V
V

Continuous

Continuous

Continuous

Po
Topr

T stg

570
-25- +85
-65-+150

570
0-+70
-65:- + 150

mW
·C
·C

570
-40- +85
-65 - +150

ELECTRICAL CHARACTERISTICS .
(Vcc=5.0V, Vee=GND, Ta=25·C, unless otherwise specified)
LM324

LM224

LM2902

Characteristic

Symbol

Test Conditions

Input Offset Voltage

V,o

VeM=OV to Vcc-l.5V
Vo=l.4V, Rs=OO

Input -Offset Current

1'0

3

30

5

50

I'B

45

150

45

250

Input Bias Current
Input -Common-Mode
Voltage Range

V,eR

Supply Current

lee

Large Signal
Voltage Gain
Output Voltage Swing

Ay
VOUT

Vee=3OV
(Vee = 26V for LM2902)

Min Typ Max Min Typ Max Min Typ Max
2.0

Vcc
-1.5

0

RL=OO Vee =3OV(ali Amps)
(Voc=26V for LM2OO2)

1.5

RL =00 Vee =5V(all Amps)

0.7 -1.2

Vee = 15V,

RL~2KO

RL = 2KO(LM2~2, RL~ 10KO)

CMRR

70

Power Supply
Rejection Ratio

PSRR

65 100

Channel Separation

CS
los

Output Current

c8

85

65

5

50

nA

45

250

nA

Vcc
-1.5

V

0
3

1.5

3

mA

0.7

1.2

0.7

1.2

mA

Vee
-1_5
70

Vee
-1.5

0
50

70

dB

120
60

40

V
dB

50 100

120
40

V/mV

100

65 100

60

mV

1.5

0

120

40

Vcr.
-1.5

7.0

2.0

dB

60

mA

Isource

V'n+ =lV, Vin - =OV
Vee=15V

20

40

20

40

20

40

mA

ISlnk

V'n+ =OV, Vin _ = lV
Vee =15V

10

20

10

20

10

20

mA

Vin + =OV, Vin _ = lV
Vo=200mV

12

50

12

50

f--------------

Differential Input
Voltage

f = 1KHz to 20KHz

0

7.0

25 100
Vee
-1.5

0

2.0

3

50 100

Common-Mode
Rejection Ratio

Short Circuit to GND

5.0

Unit

V,o

SAMSUNG SEMICONDUCTOR

Vee

,.A
Vee

Vee

V

424

LM2241A, LM3241A, LM2902

LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vee = 5.0V. VEE = GND. unless otherwise specified)
The following specification apply over the range of -25·CsTas + 85·C for the LM224; and the O·CsTas + 70·C
for the LM324; and the -40·CsTas +85·C for the LM2902·

Characteristic

Symbol

Test Conditions

Input Offset Voltage

V,O

VeM=OV to Vee·1.5V
Vo=1.4V. Rs=OO

Input Offset Voltage
Drift

6 Viol 6 T

Input Offset Current

1'0

Input Offset Current
Drift

61 ,01!\T

Input Bias Current
Input Common·Mode
Voltage Range

LM224

Min Typ Max Min Typ Max Min Typ Max
7.0

0

Large Signal Voltage
Gain

Av

Vee = 15V. RL~2.0KO
(for large Vo swing)

25

Output Voltage Swing

VOH
VOL

nA
pA/·C

10

300

500

500

nA

Vee
·2.0

Vee
·2.0

Vee
·2.0

V

'.
28
5

mV

/lV/·C
200

10

Unit

0

15

15
26
27

20

0

28
5

22
23
20

V/mV

24
5 100

V
V
mV

lsource

V.n+ = 1V. Vm =OV
Vee =15V

10

20

10

20

10

20

mA

ISink

V.n+ =OV V.n_ = 1V
Vee = 15V

10

15

5

8

5

8

mA

Output Current

c8

IRL -2KO 26
Vee = 30V
Vcc = 26V for 2902IRL= 10KO 27
Vcc=5V RLS10KO

7.0
150

10

VieR

10.0

7.0
100

vee=30V
(Vee =26V for LM2902)

Differential Input
Voltage

9.0

7.0

liB

--

LM2902

LM324

V'c

SAMSUNG SEMICONDUCTOR

'V ee

Vee

Vee

V

425

II

LM224/A, LM3241A, LM2902

LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vcc=5.0V, VEE=GND, Ta=25°C, unless otherwise specified) -

LM224A

Test Conditions

Input Offset Voltage

V'O

VCM=OV to Vcc·1.5V
Vo=1.4V Rs=O

Input Offset Current

1'0

2

15

5

30

nA

Input Bias Current -

I,e

40

80

45

100

nA

Vec
·1.5

V

Inp!Jt Comm·Mode
Voltage Range

V'CR

Min Typ

Supply Current (All Amps)

Icc

1.0

Vcc = 30V

RL=oo Vcc=5V

Large Signal Voltage Gain

--~--~-

Av

Vec= 15V RL-+--oVOUT

VOUT
RL

100KO
looKO

Vee

o...f1.I1....

00
AV=l+~

V

Rl
Av=ll ,

Bi·Quad Filter

Fig. 15

Fig. 16
R
R

C

looK!I

looKIl

O _BW

- to

where
TBP=Center frequency gain
TN == Bandpass notch gain

Rl
R2=Tsp
R3=TNR2
Cl =10C
Example: to = 1000Hz
BW=100Hz
Tsp=l
TN=l
R=lS0KIl
Rl=l.SMIl
R2=1,SMIl
R3= 1,6MIl
C=O.Ol"F
1

to=2rRC
Rl =OR

R3

R2
Cl

>--+--I/---<> ~~i~~T
Fig. 17

c8

SAMSUNG SEMICONDUCTOR

431

LM2481LM348

LINEAR INTEGRATED CIRCUIT

QUAD OPERATIONAL AMPLIFIERS
The LM2481LM348 is-' a true quad LM741. It consists of four
independent, high-gain, internally compensated, low-power operational
amplifiers which have been designed to provide' functional
characteristics identical to those of the familiar LM741 operational
amplifier. In addition the total supply current for all four amplifiers is
. comparable to the supply current of a single LM741 type OP Amp.
Other featur.es include input offset currents and input bias current which
are much less than those of a !ltandard LM741. Also, excellent isolation
between amplifiers has been achieved by independently biasing each
amplifier and using layout techniques which minimize thermal coupling.

14 DIP

14 SOP

FEATURES
•
•
•
•
•
•
•
•
•
•

LM741 OP Amp operating characteristics
Low supply current drain
Class AB output stage-no crossover distortion
PJn compatible with the LM324 & MC3403'
Low Input offset voltage-1mV Typ.
Low input offset current-4nA Typ.
Low Input bias current·30nA Typ.
Gain bandwidth product for LM348 (unity galn)-1.0MHz Typ.
Channel seperatlon 120dB
Overload protection for outputs

BLOCK DIAGRAM

ORDERING INFORMATION
Device

Package

IN4 (-}

LM348N

14 DIP

IN4 (+)

LM348D

14 SOP

OUT4

IN3 (+)

LM248N

14 DIP

LM248D'

14 SOP

Operating Temperature
0- +70'C
-25-+85'C

IN3 (-)
OUT3

SCHEMATIC DIAGRAM

(One Section Only)

r-~----------~--~~--------~~----------~-ovcc

NON INVERTING
INPUT
R9

INVE~J~~~ o---+--+-+--:-+-----'

'----''WY-+--te-_te_------t----

.."ill

0~

__

~

__- 4__

o.

~

____

10

Fig. 1

~

__

~

__

15

10

o

~

20

V
o

5

L·

..

15

20

SINK CURRENT LIMIT
-1

r
Vs '" ±15

51.

r
Vs= ±15V

T._25"C

T.=25"C

1\,

0

1\

0

o

5

Fig. 3'

10

15

20

\
\

--- ~ i'-...

1,\

5

0
25

30

5

10

Fig. 4

OUTPUT SOURCE CURRENT (mAl

OUTPUT IMPEDANCE

15

20

25

30

OUTPUT SINK CURRENT (mAl

COMMON-MODE REJECTION RATIO

lk

120
FV,=±15
!==T.=25·C

VS =I±15V

T.-25·C
100

k/'"
A,=

eo

A
~

~~

1

I

,;..t!

I

~~

=
=7-

.,7

-7

60

~

~

40

20

/

, o. 1
100

lk

Fig. 5

10k

lOOk

FREQUENCY (Hzl

SAMSUNG SEMICONDUCTOR

1M

"

~

;";'-1

./

c8

25

SUPPLY VOLTAGE (± V)

SOURCE CURRENT LIMIT
5

~

10

Fig. 2

SUPPLY VOLTAGE (± V)

V

/

100

lk

Fig. 8

10k

~

lOOk

FREQU~ (Hz)

434

LM2481LM348

LINEAR INTEGRATED CIRCUIT
BODE PLOT

OPEN LOOP FREQUENCY RESPONSE
110

VsJ±15~-

"

90

20

T.-25°C.

I'-

70

r\.

Ii
l!.
!! 50

i

""
""

30

3 -10

100

lk

Fig. 7

10k

-35

Jo

/

\

/
i
~ -10
i

Av=1
Vs - t15V
RL 0!!2k

/

,

10

-10

I

FREQUENCY (MHz)

A~-1
.I.
v,- ±15V-

J
o

100

I

T.=25°C

1\
\

I

0

\

II

I

II

\

0

'f

"IN

10

\

20

'\

10

Fig. 8

\

II

~

\

SMALL SIGNAL PULSE RESPONSE

,

T.-25°C

\

0.1

LARGE SIGNAL PULSE RESPONSE

10

,GAiN

2k

-

-30

1M

FREQUENCY (Hz)

+

-25 - I

"

\

. 1k

-20

lOOk

70

-rn

-15

-10

10

80

'"~

-5

!!

r\.

10

90

T•• 25·C

"r-.. ....

I'-

3

100

LLk)

II
~
........... -..... JHls~
10

15

v"

100
0
-100

-10

40

80

Fig. 9

160

120

2

200

Fig. 10

TIME (PS)

UNDISTORTED OUTPUT VOLTAGE SWING
32

INVERTING LARGE SIGNAL PULSE RESPONSE

vs~ ~1~J

R'=f~

....

3
TIME(",,)

J

o

10V

I
II

T.=25°C
Av ·1
<1%DIST

V,I.±1JvR,=2k I
A'=-1~_

I\.

T.-25·C

\

J
i

a-

\.

\

\

II

10

\

\.
10

"IN

"-10

o

100

1k

Fig. 11

c8

10k
FREQUENCY (Hz)

SAMSUNG SEMICONDUCTOR

100k

o

20

40

60

80

Fig. 12

100

120 140

180

180

200

TIME ws)

435

LINEAR INTEGRATED CIRCUIT

LM248/LM348

POSITIVE COMMON·MODE INPUT
VOLTAGE LIMIT

INPUT NOISE VOLTAGE AND NOISE CURRENT
160

v!_L~t

T.",,25°C

140

(6

20

1.2

i

~

I

1\

1.0 ;
0.8

~

0.6
0.4

!

~

.!i!

15

:>
Q,

iI

I!I

§ ~

0.2

~
:E

0
:E
:E

10

8
!l!
i=

~

Q,

o
10

100

Fig. 13

0
10k

lk
FREQUENCY (Hz).

.

J

I

-2SoC::s;Ta::s; +85°C

w

MEAN NOISE CURRENT

20

I§.
u

MEAN NOISE VOLTAGE

I

~
!::

1.4

5

/

/

5

Fig. 14

/
10

/

/

15

1/

20

POSITIVE SUPPLY VOLTAGE (V)

NEGATIVE COMMON - MODE INPUT
VOLTAGE LIMIT
.

Fig. 15

c8

NEGATIVE SUPPLY VOLTS (V)

SAMSUNG SEMICQNDUcroR

436

LINEAR INTEGRATED CIRCUIT

LM2481LM348
TYPICAL APPLICATIONS
Function Generator
TRIANGLE WAVE
OUTPUT

R2

VREF

>-+----<0 SQUARE WAVE OUTPUT
1= Rl +R3
4CRIRI
II R3= R2Rl
R2+Rl

I

Fig. 16

Bi·Quad Filter
R
R

C

Cl

Y,N

100Ka

R2

o--U-.--'li"ltr--+---I

VREF'

l00Ka

Rl

VREF

R3

R2
Cl

>--+---11---0 NOTCH OUTPUT
Q=BW
10
VREF

where
TSp = Center frequency gain
TN = Bandpass notch gain

1
10 = 27RC
Rl =QR

Rl
R2 = TBP
R3=TNR2
Cl=10C

Example: 10 = 1000Hz
BW=I00Hz
Tsp=1
TN=1
R = 160Ka
Rl=I.6MIl
R2=1.6MIl
R3= 1.6Ma
C=O.Q1~F

Fig. 17

c8

SAMSUNG SEMICONDUCTOR

437

LM2581A, LM358/A, LM2904

LINEAR INTEGRATED'CIRCUIT .

QUAD OPERATIONAL AMPLIFIERS

8 DIP

The LM258 series consists of four independent, high gain, internally
frequency compensated op~rational amplifiers which ·were deSigned
speCifically to operate from a single power supply over a wide range
of voltage.
\
Operation from split power supplies is also possible and the low power
supply 9urrent drain is independent of the magnitude of the power supply
voltage,
Application areas include transducer ampliti.er, DC gain blocks and all
the conventional OP amp circuits which now can be easily Implemerl'ted
In single power supply systems.

a SOP

FEATURES.
• Internally frequency compensated
• Large DC voltage gain: 100dB
• Wide power supply renge: LM258JA, LM358IA: 3V - 32V
(or ±1.5V-16V)
LM2904: 3V - 26V (or ± 1.5V - 13V)
• Input common·mode voltage range Includes ground
• Large output· voltage swing: OV DC to Vee - 1.5V DC
• Power drain suitable for battery operation.

9 SIP

BLOCK DIAGRAM

;::

::>
0

SCHEMATIC DIAGRAM (One section only)
VCC~--~~--------~--~~r-----~,

c8 SA~SUNG

SEMICONDUCTOR

I
+
~ ~

ORDERIN'G INFORMATION
Device

Package

LM358N
LM358AN

8 DIP

LM358S

9 SIP

LM358D
LM358AD

8 SOP

LM258N'
LM258AN

8 DIP

LM258S

9SIP

LM258D
LM258AD

8 SOP

LM2904N

8 DIP

LM2904D

8 SOP

Operating Temperatur

O-+70·C

-25-+85·C

-40-+85·C

438

LINEAR INTEGRATED CIRCUIT

LM258/A, LM358IA, LM2904
ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

LM2581LM258A

LM3581LM358A

LM2904

Unit

Power Supply Voltage
Differential Input Voltage
Input Voltage
Output Short Circuit to GND
VeeS15V Ta=25·C (One Amp)
Operating Temperature Range
Storage Temperature Range

Vs
VIO
VI

± 16 or 32
±32
-0.3 to +32

± 16 or 32
±32
-0.3 to +32

±13 or 26
±26
-0.3 to +26

V
V
V

Continuous

Continuous

Conti'nuous

0-+70
-65 - +150

-40-+85
-65-+150

-25-+85
-65-+150

Topr
Tstg

·C
·C

I

ELECTRICAL CHARACTERISTICS
(Vee = 5.0V, Vee=GND, Ta=25·C, unless otherwise specified)

Characteristic

Symbol

Test Conditions

Input Offset Voltage

VIO

VeM=OV to Vee-1.5V
Vo= 1.4V, Rs=OO

Input Offset Current

110

Input Bias Current

liB

Input Common-Mode
Voltage Range

VieR

Supply Current

lee

Large Signal
Voltage Gain

Av

Output Voltage Swing
Common-Mode
~ejection Ratio

-

Power Supply
Rejection Ratio

VOUT

c8

±5 ±50

±5 ±5O

nA

45

45

nA

150
Vee
-1.5

0

250
Vee
·1.5

0

250

Vee .
V
-1.5

0

Rl=oo Vcc= 3OV(LM2902, Vcc =26V)

1.0

2.0

1.0

2.0

1.0

2.0

rnA

Rl =00 over full temperature range

0.7

1.2.

0.7

1.2

0.7

1.2

rnA

Vee = 15V,

RL~2KO

RL = 2KO(LM2904,

RL~ 10KO)

50 100

f = 1KHz to 20KHz

25 100
Vee
-1.5

0

65 100

los

Differential Input
Voltage

±3 ±30

PSRR
CS

Unit

±2.0 ±7.0 mV

70

Channel Separation

LM2904

±2.0 :t7.0

45
Vee = 30V
(LM2904, Vee = 26V)

LM358

±2.0 ±5.0

CMRR

Short Circuit to GND

Output Current

LM258

Min Typ Max Min Typ Max Min Typ Max

70

40

V

70

dB

50 100

dB

120
60

V/mV.
Vee
-1.5

0
50

65 100

120
40

Vee
-1.5

0

65

85

100

120
60

40

dB

60

rnA

lsource

Vln +=1V, Vln_=OV
Vee =15V

20

40

20

40

20

40

rnA

ISlnk

Vln + =OV, Vln _ = 1V
Vee =15V

10

20

10

20

10

20

rnA

Vln+ = OV, Vln _ = 1V
Vo=2oomV

12

50

12

50

VIC

SAMSUNG SEMICONDUCTOR.

.Vee

p.A
Vee

Vee

V

439

LM2581A, LM358/A, LM2904

LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(Vee = 5.0V, VEE = GND, unless otherwise specified)
The following specification apply over the range of - 25·CsTas + 85·C for the LM258; and the O·CsTas + 70·C
for the LM358; and the -40·CsTas +85·C for the LM2904

~ymbol

Test Conditions

Input Offset Voltage

VIO

VCM=OV to Vcc-1.5V
Vo=1.4V, Rs=O

Input Offset Voltage
Drift

6V loI6T·

Input Offset Current

110

Input Offset Current
Drift

61 10/6T

Characteristic

Input Bias Current

VICR

Large Signal Voltage
Gain

Av
VOH
VOL

:!:9.0

7.0

Rs=OD

RL~2.0KD

/LV/·C

±45 ±200
10

10
40 500

40 500

Vcc
-2.0

Vcc
-2.0

Vcc
-2.0

25

0
15

28
5

25
27
20

0

22
23
20

nA
V
V/mV

15

28
5

nA
pA/·C

40 300
0

IR =2KD 26
VCC= 30V
Vee=26V for 2904IRL= 10KD 27
Vce=5V RLS10KD

7.0

:!:150

10

Vee = 15V,

:!:10.0 mV

7.0

:!:100

VCC= 30V
(LM2904, Vee = 26V)

LM2904

V

24
5 100

mV

lsource

V;n+ = 1V, V,n=OV
Vee = 15V

10

20

10

20

10

20

rnA

ISink

V;n+ = OV V;n_ = 1V
Vee = 15V

5

8

5

8

5

8

rnA

Output Current

c8

LM358

:!:7.0

liB

Input Common-Mode
Voltage Range

Output Voltage Swing

LM258

Min Typ Max Min Typ Max Min Typ Max

SAMSUNG SEMICONDUCTOR

440

LINEAR INTEGRATED CIRCUIT

LM258/A, LM358/A, LM2904
ELECTRICAL CHARACTERISTICS

(Vcc=5.0V, VEE=GND, Ta=25°C, unless otherwise specified)

Characteristic

Symbol

Test Conditions

Input Offset Voltage

V,o

VCM=OV to Vcc·1.5V
Vo=1.4V Rs=O

Input Offset Current

LM358A

LM258A
Min

Typ

Max

1.0

3.0

Min

Typ

Max

2.0

3.0

mV

1'0

2

15

5

30

nA

Input Bias Current

I'B

40

80

45

100

nA •

Input Comm-Mode
Voltage Range

V,CR

Supply Current
Large Signal Voltage Gain
Output Voltage Swing

lee

Vcc = 30V

Vcc
·1.5

0

Vee
·1.5

0

RL =00 Vee = 30V

1.0

2.0

1.0

2.0

Rl :ooover full temperature range

0.7

1.2

0.7

1.2

Av
VOUT

Vee = 15V RL

1

Ta=O°C to +85°:""-

40

V

!

II

I
10

20

30

10

20

SUPPLY VOLTAGE (V)

30

SUPPLY VOLTAGE (V)

OPEN LOOP FREQUENCY RESPONSE

LARGE SIGNAL FREQUENCY RESPONSE

f~"

Vee 100KD

lOMo

,20

40

~

I-

V"

'"

V''!

112 Vee

~

~

V.. -10to 15V AND'

!J{;

1K

r....

~

10K

lOOK

FREQUENCY

r--..

o

1M

lK

I (Hz)

10K

(n

100K

FREQUENCY

OUTPUT CURRENT SOURCE

(n

OUTPUT SINK CURRENT
Vee

'~'

'~:/,-

-

,......1/

4

t-

1
1

.
1
0JlD1

J

/ '/J

/

0.1

10

100

QUTPUT SOURCE CURRENT (mAl

c8

SAMSUNG SEMICONDUCTOR

I--V+-+5VOC

V+-+15\1tJc

I--V+-+3OVDC
ITa= +25°C

1

II
0D1

J

Vo

1

3

~o

112Vcc

\.
"~

100

[r--

I 11
~~5~:h~~85,d

I -25'C.:Ta.:+85'C

10 ,

lKO

0D1
0JlD1

'/

r//
0D1

I
!

0.1

10

OUTPUT SINK CURRENT (mAl

.443

LM258/A, LM358/A, LM2904

LINEAR INTEGRATED CIRCUIT
COMMON·MODE REJECTION RATIO

INPUT COMMON·MODE VOLTAGE RANGE

v ,r
Ne~~E

,r

,r

V

,r V
,r
1/ ,r

V

POSm~

V

V
II'"

120

~

100

~

SO

I

r-

SO r--r-

i~

1/ V
1/ V

Y

-

+ 7.5V 100KD

r--r- f-r- -

looo1 ... ~\

I-r- - +
20 I-r- ...':!w

,r

V

o
10
SUPPLY VOLTAGE (y)

c8

ii

SAMSUNG SEMICONDUCTOR

1000

l00KiJi

f-r- 100

lK

I, .

1
10K

Yo- -1-1-

-- - I lOOK

FREQUENCYCI)

444

LINEAR INTEGRATED CIRCUIT

LM258IA, LM358IA, LM2904
TYPICAL APPLICATIONS

(Vee

=5.0V)

Voltage Reference

Non-Inverting DC Gain

Vee

+5V

_____ _

+Vo

RI

II

Pulse Generator

AC Coupled Non-Inverting Amplifier

Rl

R2

>--f--,-Q 1I0UT

f\f\

V

2 V p•p

AV=II

Bi-Quad Filter
R

R
lOOK!!

C

_BW
- 10
where
TBP=Cenler Irequency gain·
TN = Bandpass notch gain
Q

C
Cl

VIN

F.l2

o---f I---<~~Ir--+--I

100KO
100KIl

I
10= 2 ..RC
Rl =QR
•

R3
VREF

R2

c8

SAMSUNG SEMICONDUCTOR

Rl
R2=TBP
R3=TNR2
Cl=10C
Example: 10 = 1000Hz
BW=100Hz
TBP=1
TN=1
R=160KIl
Rl=I.6M!I
R2=1.6MIl
R3=1.6MIl
C=O.OlpF

445

LM741 C/LM741'E1LM7411

LINEAR INTEGRATED CIRCUIT
8 DIP

SI~GLE OPERATIONAL AMPLI~IERS .. '
The LM741 series are general purpose operational amplifiers which
feature improved performance over industry standards like the LM709. '
It Is intended for a wide range of analog applications.
The high gain and wide range of operating voltage provide superior
performance in Intergrator, summing amplifier, and general feedback
applications.

8 SOP

FEATURES
•
•
•
•
•

Short circuit protection
Excellent temperature stability
Internal frequency compensation
High Input voltage range
Null of offset

ORDERING INFORMATION

BLOCK DIAGRAM
OFFSET
NULL

OFFSET
NULL

Device

Package

LM741EN
LM741CN

8 DIP

LM741ED
LM741CD

8 SOP

Operating Temperature

0- +70·C

LM7411N

8 DIP

LM7411D

8S0P

-40- +85·C

SCHEMATIC DIAGRAM
'INVERTING INPUT

5

c8

OFFSET NULL

SAMSUNG SEMICONDUCTOR

446

LINEAR INTEGRATED CIRCUIT

LM741C/LM741 ElLM741I·

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Characteristic

Symbol

LM741C

LM741E

LM741 I

Unit

Power Supply Voltage
Differential Input Voltage
Input Voltage
Output Short Circuit Duration
Power Dissipation
Operating Temperature Range
Storage Temperature Range

Vs
VIO
VI

±18
±30
±15
Indefinite

±22
±30
±15
Indefinite
500
0-+701
-65-+150

±18
±30
±15
Indefinite

V
V
V

500

mW
.0C
°C

500

Po
Topr
Tstg

0-+701
-65 -+.150

-40- +85
-65-+150

ELECTRICAL CHARACTERISTICS
(Vcc =15V, VEE= -15V, Ta=25°C, unless otherwise specified)

Characteristic

Test Conditions

Symbol

LM741C/LM741I

LM741E
Min

Typ Max Min

Typ Max
2.0

RsS10KD

6.0

Input Offset Voltage

VIO

Input Offset Voltage
Adjustment Range

VIOR

Input Offset Current

110

3.0

30

20

200

Input Bias Current

liB

30

80

80

500

Input Resistance·

RI

Input Voltage Range

Large Signal Voltage Gain

Output Short Circuit Current

RL~2KO

c8

Vs= ±20V,
Vo=±15V

0.3

±12 ±13

±16

RL>2KO

±15

25

RL~10KO

nA
nA
MO
V

25

35

mA

V

±10 ±13

.

Rss10KO, VCM = ±12V
Rss50KO, VCM = ± 12V

80

95

Vs = ±20V to Vs = ±5V
RsS500

80

96

SAMSUNG SEMICONDUCTOR

mV

200

±12 ±14

Vs= ±15V to Vs = ±5V
RsS10KD

mV

V/mV
20

HL~10KO

RL~2KO

2.0

50

10

VOUT

PSRR

6.0

Vs=±15V,
Vo= ±10V

los

Common MOQe Rejection Ratio CMRR

±15

±12 ±13

Vs=±15V

Power Supply Rejection Ratio

1.0

Vs= ±20V

VICR

Av

3.0

±10

Vs= ±20V

Vs= ±20V
Output Voltage Swing

0.8

RsS500

Unit

70

90

77

96

dB

dB

447

II

LM741 C/LM741 ElLM7411

LINEAR INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
Characteristic
Transient
Response

I

I

Symbol

Rise Time

t,

Overshoot

OS

Bandwidth

BW

Slew Rate

SR

Supply Current
Power Consump.tion

(Continued)

Test Conditions

LM741E

LM741C/LM741I

Typ

Max Min

Typ

0.25

0.8

0.3

6.0

20

5

%
MHz

Min

Unity Gain

Unity Gain

0.43

1.5

1.0

0.3

0:7.

0.5

RL=co !l

Is

80

Vs= ±20V

Pc

Unit
p's

V/p.s

1.7

2.8

mA

50

85

mW

150

Vs= ±15V

Max

ELECTRICAL CHARACTERISTICS
(- 25·C:sTa:s85·C for the LM7411, 0·C:sTa:s70·C for the LM741C, LM741 E, Vee =
otherwise specified)

Characteristic

Input Offset Voltage
Input Offset Voltage Drift
Input Offset Current .
Input Offset Current Drift

VOUT
Vs=±15V

±16

.

±15

RL~2KO

40

Rs:s10KO, VCM = ± 12V
Rs:s50KO, VCM = ± 12V

80

95

Vs= ±20V Rs:s500
to±5V Rs:s10KO

86

96

RL~2KO

SAMSUNG SEMICONDUCTOR

nA
V

V

±10 ±13'
10

mA
70

90

77

96

dB
dB

32

Vs=±15V,
Vo = ±10V
Vs= ± 15,
Vo=2V

.c8

±12 ±14

RL~2KO

Vs= ±20V,
Vo= ±15V
Av

0.8
±12 ±13

RL~10KO

los

nA

MO

±12 ±13
RL~ 10Kfr

mV

nA/oC

0.5

VICR
Vs= ±20V

Large Signal Voltage Gain

300

0.21
Vs = ±20V

Unit

p.V/·C

15
70

PSRR

Max

7.5

0.5

Common Mode Rejection Ratio CMRR

Typ

4.0

110

Ri

Power Supply Rejection Ratio

LM741C/LM741I
Max Min

t,lldt, T
liS

Output Short Circuit Current .

I Typ

VeE = -15V, unless

Rs:s10KO

t,Vldt, T

Input Bias Current

Output Voltage Swing

LM141E
Min

Rs:s500

VIO

Input Resistance
Input Voltage Range

Test Conditions

Symbol

+ 15V,

15

V/mV

10

448

LM741C/LM741 ElLM741I

LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS
INPUT OFFSET CURRENT .. SUPPLY VOLTAGE

POWER CONSUMPTION va SUPPLY VOLTAGE

5.0

100

Ta=L.c

TaJ25 c0

80

i

4.0

i
Iii

~

3.0

/

r--

~

V

~

35 2.0

./

20

10

5

10

20

15

OPEN LOOP VOLTAGE GAIN VI FREQUENCY

OPEN LOOP PHASE RESPONSE .. FREQUENCY
0

'"

10'

z

10'
10'

0

>

I"

10'
'0'

10

100

-45

~:~':S!~V-

'"I"I"

101K

10K

lOOK

i

"9.- 90

1\

1M

I--r-

28

-180
10M

10

V

1K

10K

lOOK

1M

10M

OUTPUT VOLTAGE SWING .. FREQUENCY

i:::S!~V-

36I--H++-+--+-t-t+++H++-:i-tit-l
!E32I--H++-+--+-t-t++-+-H+-+--:i-tit-l
"! 28 I-++++-+--H++-+-+-t++-+--+tit-l
~

~

20

~ 24 f---+-+tt---t--t-t-tt---tt----t-ttt-~:·:~!~V I

S

18

§

20 f--t-+t+-+-+-+++--+--\-t
\-+tHr-t--HH---t

I'!~

12r-t-+t+-+-+-+++--+-~~---t----t-~-1

...

8 1--t+H-t-+-+++-~+f\j--+-t-~-i

~ 161--t+H-t-+-+++-~\~~-t--t-~-i

~

;S

...

18

I'!

14

~

12

~

I

1

;S

II

10

I
0.1

0.2

o.s

1.0

2.0

5.0

LOAD RESISTANCE \KClI
FIg. 5

c8

100

j.--"'"

...... j..-"'"

II

f'

--135

OUTPUT VOLTAGE SWING .. LOAD RESISTANCI'

22

1\

Va= :!::15V

Ta=25-C

FREQUENCY (Hz)
Fig. 4

28
IE 24

1\

~

FREQUENCY (HI)
FIg. 3

I

I

20

SUPPLY VOLTAGE (V)
FIg. 2

h
10'

~

15

SUPPLY VOLTAGE (V)
Fig. 1

10'

.."3

V

V

1.0

L

V

L

i

/

SAMSUNG SEMICONDUCTOR

10

Ol=OO~~-l=K~~L,=~~-ll~l=OOK="~--~lM.
FREQUENCY (HI)
FIg. I

449

LM741C/LM741 ElLM741I

LINEAR INTEGRATED CIRCUIT
INPUT RESISTANCE AND INPUT CAPACITANCE
va FREQUENCY

OUTPUT RESISTANCE va FRE.QUENCY
600

100 .

10M

R,.

r-

500

~:~:5~~V
-

-.

s:

'"1\

lto<

1

I

h

a:

II
~

100

!;

~100K

C"

10K

1

100

1K

10K

lOOK

0.1

lK

100

1M

INPUT BIAS CURRENT vs AMBIENT
'TEMPERATURE

INPUT RESISTANCE vs AMBIEIIIT TEMPERATURE
10

-----

7.0
80

.!i~l

1
a:
a:

80

U

i

- -Vs= ::I::15V

40

r-- r-

!;
!

20

o

r--

1M

FREQUENCY (Hz)
Fig••

100

..
"
..;II
.

lOOK

10K

FREQUENCY (Hz)
Flg.7

!Z

1

f--~

5.0

--

.....-

Vs=±15V~

3.0

a:

.
!;

!

2.0

1.0

o

10

20

30

40

50

so

o

70

10

20

30

40

50

60

70

TEMPERATURE (.C)

TEMPERATURE (.C)

Flg.l0

FIg. 8

POWER CONSUMPTION vs AMBIENT
TEMPERATURE

INPUT OFFSET CURRENT va AMBIEIljT
TEMPERATURE
100

I.

~

.

. Vs= ±20V -

r---.....

.......

90

Ii

r--....

.......

--

.sz
0

~ so

........

lI!

"

II)

...8~
.
a:

---

--

Va= ::t:15V

r-- r- io-.

70

60

o

o

50
10

20

30

40

50

80

TEMPERATURE (.C)
Fig. 11

c8

SAMSUNG SEMICONDUCTOR

70

o

10

20

30

40

50

60

70

TEMPERATURE (.C)
Flg.12

450

LM741C/LM741 ElLM741I

LINEAR INTEGRATED CIRCUIT

OUTPUT SHORT CIRCUIT CURRENT
va AMBIENT TEMPERATURE

TRANSIENT RESPONSE
28

30

24

28

~.

ii

28

r-....

20

1'000..

II:
II:

"ut:

~

Ii:

. . r----..

24

90%/

J
I
II

.......

f'... i'.....

22

0

""""

:z:

In

20

I-\.

Va= ±15V_

Ta=2SoC
Rl=2Kn
C'=JlOPF-

10%

I----'

RISETIr

II

18
01020

40

30

50

0.5

6070

TEMPERATURE (0C)
Fig. 13
VOLTAGE FOLLOWER LARGE SIGNAL
PULSE RESPONSE

1.5

2.0

2.5

Fig. 14

COMMON MODE REJECTION RATIO
.s FREQUENCY
100

10

..1

90

!

Vs= ±15V_
Ta=2S"C

-- -

I'
I j\
INPUT I.
\

VOUTPUT

j

II

I
I

1-

f-

" "-

iiJ

3!.
Q

80

iz

70

~

60

Ul
II:

50

u
w

I

i:~:5!~V

1\

--

"

40

z

30

0
::IE

~

0
::IE
::IE
0

\

u

-

['I..

"- 1\
"-

W

-8

20
10

-10
•

20

30

~

50

60

70

OUTPUT VOLTAGE (V) TIME fl..)
FIg.1S

c8

1.0
TIME fl. ••

SAMSUNG SEMICONDUCTOR

60

90

10

,00

1K

10K

lOOK

1M

10M

FREQUENCY (Hz)
fig. 16

451

MC14581MC1458C/MC14581

LINEAR INTERGRATED CIRCUIT

DUAL OPERATIONAL AMPLIFIERS

a DIP

The MC1458 series is a dual general purpose operational amplifier.
The MC1458 series is a short circuit protected and require no external
components for frequency compensation.
High common mode voltage range and absence of "latch up" make the
MC1458 ideal for use as voltage followers.
The high gain and wide range of operating voltage provides superior
performance in intergrator, summing amplifier and general feedback
applications.

a SOP

FEATURES
•
•
•
•
•

Interal frequency compensation
Short circuit protection
Large common mode and differential voltage range
No latch up
Low power consumption

9 SIP

BLOCK DIAGRAM

;:

:>
0

I

+

~

~

w
w

>

+

'":i!::

ORDERING INFORMATION
Device

Package Operating Temperature

MC1458CN
MC1458N

8 DIP

MC1458S

9 SIP

MC1458D
MC1458CD

8 SOP

MC1458IN

8 DIP

MC1458ID

8 SOP

ciS

o -+70·C
O-+70·C
-25-+85·C

SAMSUNG SEMICONDUCTOR

452

MC14581MC1458C/MC14581

LINEAR INTERGRATED CIRCUIT

SCHEMATIC DIAGRAM
r-t------?---~----VCC

R6

OU,PUT
R7

II
VEE

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Power Supply Voltage
Inp'lt Differential Voltage
Input Voltage
Operating Temperature Range MC14581
MC14581C
Storage Temperature Range

Vs
VID
V,

±18
±30
±15
-25- +85
0-+70
-65-+150

V
V
V
·C
·C
·C

c8

SAMSUNG SEMICONDUCTOR

Topr

Tstg

453

MC14581MC1458C/MC14581

LINEAR INTERGRATED .cIRCUIT

ELECTRICAL CHARACTERISTICS
(Vs = ± 15V, Ta = 25°C, unless otherwise specified)

Characteristic

Symbol

Test Conditions

Input Offset Voltage

V,o

RsSl0KO

Input Offset Current
Input Bias Current

1'0
I,s

Large Signal Voltage Gain

Av

--

---

Input Voltage Range
Input Resistance

MC1458C

MC14581MC14581

Min Typ Max Min Typ Max

Vo = ± 10V, RL~2"OKO

20

2.0

6.0

2.0

10

mV

20

200

20

300

nA

80

500

80

700

100

20

±12 ±13

V'CR
R,

Unit

0.3

1.0

90

nA
V/mV

100.

V

± 11 ±13
1.0

MO

90

dB

--~--~.

Common Mode Rejection Ratio CMRR

Rssl0KO

70

Power Supply Rejection Ratio

Rssl0Kil

77

---

Supply Current (Both Amplifier)
-----_.-

Outp'ut Voltage Swing
Output Short Circuit Current
-'-

Power Consumption

PSRR

VOUT

77

90
2.3

Is

60

dB

90

5.6

2.3

8:0

RL=10KO

±12 ±14

± 11 ±14

RL=2KO

±10 ±13

±9 ±13

20

los

V

20
170

mA

mA

Pc

Vo=OV

70

70

240

t,
OS
SR

V,=20mV, RL~2KO, CLS100pF
V,=20mV, RL~2KO, CLS100pF
V,=10V, RL~2KO, CLsl00pF

0.3
15
0.8

0.3
15
0.8

MC1458/MC14581

MC1458C

mA

---~---

Transient Response (Unity Gain)
Rise Time
Overshoot
Slew Rate

p,s

-%
V/p,s

ELECTRICAL CHARACTERISTiCS
(TamonSTaSTamax, Vs = ± 15V, unless otherwise specified)

Characteristic

Symbol

Test Conditions

Input Offset Voltage

V,o

RsSl0KO

7.5

12

mV

Input Offset Current

---------

1'0

300

400

nA

In"put Bias Current

I,s

800

1000

Large Signal Voltage Gain

Av

Vo ~ ± 10V, RL~2.0K

15,

Common Mode Rejection Ratio

CMRR

Rssl0K

70.

90

70

90

dB

Power Supply Rejection Ratio

PSRR

Rssl0K

77

90

77

90

dB

RL= 10K.

±12

±14

± 11

±14

RL=2K

±10

±13

±9

±13

--------

--

Output Voltage Swing

VOUT

---------

Input Voltage Range

V'CR

Min

±12

Typ

Max

Min

Typ

15

±12

Max

Unit

nA
V/mV

V
V

* Tamm:sTa:s:Tamax

MC14581: Tam'n = - 25·C, Tamax = + 85°C
MC45581C: Tamon = O·C, Tamax = 70·C

c8

SAMSUNG SEMICONDUCTOR

454

LINEAR INTEGRATED CIRCUIT

MC1458/MC1458C/MC14581

TYPICAL PERFORMANCE CHARACTERISTICS
OPEN·LOOP VOLTAGE GAIN.8 POWER
SUPPLY VOLTAGES

OPEN·LooP FREQUENCY RESPONSE

120

120

115

100

I: 110

!.
5l
!:i
Ii!

105

Ie

a

,......V""

100

95
....g
z

-

"-

eo

/

90

85

eo

9.0

6.0

30

18

10

21

100

POWER SUPPLY 'VOLTAGE (V)

32

32

28

28

'"

~

20 r-

~

16

w

---

--

~

I I I I

i!

8

II.

12

./

\

4.0

r-j1iITiSurl'iiTr5i
1K
100
°10

i'

10K

FREQUENCY ,Hz)

Fig. 3

c8 SAMS~NG

SEMICONDUCTOR

lOOK

U±112l

V

16

12

AL=2K

I

10M

IILI

l-

I-

VOl:rAGE FOLLOWER

1M

Vs = ±15V

~ 20
g~

\

8.0

lOOK

24

Ii!
~

10K

OUTPUT VOLTAGE SWING '8 LOAD
RESISTANCE

POWER BANDWIDTH
(LARGE SIGNAL SWING va FREQUENCy)

24

1K

FREQUENCY (Hz)
Fig. 2

Fig. 1

"1

1\

-20

15

12

'"I'" I'"
~

20

°

100

/~
10KI
11rr

THOr°'l'
200

500

IIIII
1K

+

9.1K

Vo

R,

i

2K

III
5K

10K

LOAD RESISTANCE (0)
Fig. 4

455

LINEAR INTEGRATED CIRCUIT

MC3303IMC3403
QUAD OPERATIONAL AMPLIFIER

14 DIP

The MC3303 series is a monolithic Quad operational amplifier
consisting of four independent amplifiers. The device has high
gain, intemally frequency, compensated operational amplifiers
designed to operate from a single power supply or dual power
supplies over a wide range of voltages. The common made input
range includes the negative supply, thereby eliminating the
necessity for external biasing components in many applications.

FEATURES

1450P

• Output voltage can swing to GND or negative supply
• Wide power supply range;
Single supply of 3.0V to 36V
Dual supply of % 1.SV to % 18V
• Electrical characteristics similar to the popular LM741
• CLASS AS output stage for minimal crossover distortion
• Short circuit protected output.

BLOCK DIAGRAM·

ORDERING INFORMATION
Device'

Package

Operating Temperature

MC3303N

14 DIP

-40-+85·C

MC3403N

14 DIP

MC3403D

14 SOP

O-+70·C

SCHEMATHIC DIAGRAM
OUTPUT

r---------~--------~--~~----~--~~----~--ov~

NON·
INVERTING 0--+----------+-+----,
INPUT
"

INVERTING
INPUT

VEE or
~~~~--~~+-~~_+~--_+--_ _~~_ _~~~----~~_ _~~GND

c8

SAMSUNG SEMICONDUCTOR

456

MC3303IMC3403

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Vs
VIO
Vi

:1:18 or 36
:1:36
:1:18
Continuous
670
-40-+85
0-+70
-65-+150

V
V
V

Supply Voltage
Differential Input Voltage
Input Voltage
Output Short Circuit Duration
Power DisSipation
Operating Temperature MC3303 .
MC3403
Storage Temperature

Po
Top.
T.lg

mW
·C
·C
·C

ELECTRICAL CHARACTERISTICS
(Vee = + 15\1, VEE = -15V for MC3403, Vee = + 14V, VEE = GND for MC3303, Ta=25·C, unless otherwise specified)

Characteristic

Input Offset Voltage

Symbol

Test Conditions

MC3303
Min

VIO

Max Min

Typ Max

2.0

8.0

2.0

30

110

Input Bias Current

0.2
liB

Av

Input Impedance

Ri

Vo= :I: 10V
RL =2KO

RL =10KO
Output Voltage Swing

VOUT

RL =2KO
RL =2KO

Input Common Mode
Voltage Range

Common Mode Rejection
CMRR
Ratio
.

Rs:sl0KO

Power Supply Gurrent

Is

Vo=O, RL=OO

Output Short Circuit
Current

los

Each amplifier

PSRR+

Negative Supply
Rejection Ratio

PSRR-

Average Temperature
Coefficient of Input
Offset Current

t-liJt-T

c8

200

SAMSUNG SEMICONDUCTOR

0.2

200

1

12

12.5

:1:12 :1:13.5

0.3

10

12

:1:10 :1:13

Tamin:sT.:sT.max :1:10

Unit

mV

nA

,.A
VlmV

15

0.3

70

0.5
0.8

20

15

50
200

0.5

1.0

MO

V

:1:10

12V- 12.5VVEE VEE

VieR

Positive ·Supply
Rejection Ratio

20
ITamin:sT.:sTamax

30

1.0

ITam.. :sT.:sTamax
Large Signal Voltage
Gain

75
250

ITamin:S T.:s Tamax

10
12

10

ITamin:sT.:sT.max
Input Offset Current

MC3403

Typ

13V- 13.5VVEE VEE

90
2.8

70
7.0

V

90
2.8

dB
7.0

mA

:1:10 :1:30 :1:45 :1:10 :1:20 :1:45 mA
30

50

150

30

150 ,..VIV

30

150 ,..VIV

50

pAl"C

457

II

LINEAR INTEGRATED CIRCUIT

MC3303IMC3403
ELECTRICAL CHARACTERISTICS

(Continued) .
IYcc= + 15V, Vee = -15V for MC3403, Vee = +14V, Vee=GND for MC3303, unless otherwise specified)
MC3303
Characteristic

Symbol

Test Conditions

Min

Input Offset Voltage Drift /:; Vi.}/:; T
GBW Av=1, RL=2KO, Vo=20V!>p, THD=5%

Power Bandwidth

Typ

MC3403
Max Min

Typ

Max

Unit

/LV/'C

10

10

9.0

9.0

KHz

1.0

MHz

VI/Ls

Small SIgnal Bandwidth

BW

Av = 1, RL = 10KIl, Vo = 50mV

1.0

Slew Rate

SR

Av=1, VIN= -10V to +10V

0.6

0.6

Rise Time

. tr

Av;::1, RL=10KIl, Vo=50mV

0.35

0.35

/Ls

Fall Time

tf

Av =1, RL=10KIl, Vo=50mV

0.35

0.35

Over Shoot

OS

Av = 1, RL = 10KIl, Vo = 50mV

20

20

/L s
%

Phase Margin

!lim

Av = 1, RL = 2KIl, CL = 200pF

60

60

Degrees

Crossover Distortion

CD

VIN =30mVp-p, Vo=2.0Vp-p, f=10KHz

1.0

1.0

%

• Tamin

"

TUJ.b! i

IIIII

itt-' -

25

I

1.0k

10k

j

ii

I

~
-t't '+~!
~--

-~!

-5.0

j f[

if

! , II
III: -" rT .

\

I-

Fig. 4. Output Voltage V. Supply Voltage

'

•.

IlrlOOk

~!I

U

1.0M

FREQUENCY":'Hz

FIg_
..

~.

Input Bias Voltage V. Temperature

M

M

ro

U

M

V+ AND vPOWER SUPPLY VOLTAOES-V

ffi

ffi

20

Fig. 6. Input Blae Current V. Supply Voltage

_--

- - - - "1-.--\--+-.. 300 - - -

._--

1 -- -- - - I - -

.- - - - - - . - . - - -

I --- c-- ~ ----

B ~~~~~~~~~--~-.~--~
o~
1--1-- -,I__~--+r-..
--,1~~~~.4-~

iz
-

f----t--t--+--

~-

1--1-- -- . --

100f-+---+-~--1----·

--+-- -- --- --

f---4---+~f--+-+-+---l--.--

OL-~-L~L-~-L~

-75 -55 -35 -15

5.0

25

__L-~-L~

45

65

SAMSUNG

170 ....

i

-t

- - j -_-.l-_...,....~I

B

..~S
~

160

--

85

. TEMPERATURE-oC'

.c8

--

':lI

S~MICONDUcrOR

105 125

160L-~-L~

o u

U

__~-L~__L-~-L~

M

M
ro U
V+ ANDV-

M

ffi

ffi

20

POWER BUPPLY VOLTAGES-V

459

LINEAR INTEGRATED CIRCUIT

MC3303IMC3403.
TYPICAL APPLICATIONS
Fig. 7. Multiple feedback bandpass filter

Fig. 8. Weln bridge oscillator
5OkO
r---""'''''''--~r---o Your

... I
10

Yin 0

ft'f

RI

R3
C
;'
C2

R2

C

I

R

10 = center frequency

10= 2 RC 10rlo=1 kHz
..
R=16 kll
C=O.OI pF

BW = Bandwidth
R In kO
C In pF

Fig. 9. Comparator with hysterasis

10
a = BW

<.)
<.)

>

ORDERING INFORMATION
Device

Package Operating Temperature

MC455SIN

S DIP

MC4558ID

S SOP

MC4558ACN
MC455SACD
MC455SCN
MC455SCD
MC4558S

S DIP
SSOP
S DIP
SSOP
9 SIP

c8

-40- +S5·C

0- + 70·C

SAMSUNG SEMICONDUCTOR

463

MC4558C/AC/I

LINEAR INTEGRATED CIRCUIT

SCHEMATIC DIAGRAM (One Section Only)
v~o-----~----~~--------~----~----~-,

INPUT

+ 0--+------+----'

'---+---1--+-0 OUT

ABSOLUTE MAXIMUM RATINGS.
Symbol

Value

Unit

Power Supply Voltage MC4558ACI MC4558C

Vs

±22
±18

V
V

Characteristic

MC45581

Differential Input Voltage

vlO

%30

V

Input Voltage

VI

Power Dissipation

Po

±15
·400

mW

Topr

-40-+85
0-70

·C
·C

Tstg

-65-+150

·C

Operating Temperature Range MC45581

MC4558AC/MC4558C
Storage Temperature Range

c8

SAMSUNG SEMICONDUcroR

V

464

LINEAR INTEGRATED CIRCUIT

MC4558C/AC/I
ELECTRICAL CHARACTERISTICS

(Vee = 15V, VEE = - 15V, Ta= 25·C, unless otherwise speCified)

Characteristic

Symbol

Input Offset Voltage

V,O

MC4558I/MC4558AC

Test conditions

Min

Rss10KO
TaminST.STam ..

Input Offset Current

Input Bias Current

Large Signal
Voltage Gain
Common Mode Input
Voltage Range

1,0

liB

Vo = ± 10V

Av
V,CR

,

CMRR Rss10KO

Supply Voltage
Rejection Ratio

PSRR' RsS10KO

1

6

Is

300

T.=Tamln

85

500

300

Pc
V, = 10V, RL~2KO
CLS100pF

Slew Rate

SR

Rise Time

tr

V, = 20m V,
CLS100pF

RL~2KO,

Overshoot

OS

Vi =2OmV,
CLs100pF

RL~2KO,

20

80

500

30

500

800

T.=Tamln

300

1500

800

50
TamlnSTaSTam...

200

80

20

25
±13

±12

±13

70

90

70

90

200

76
76

90

90

76

90

90

76

90

±12

±14

±12 ±14

±10

±13

±10 ±13
5.0

2.3

dB
dB
V
5.6

4.5

5.0

T.=Tamln

6.0

6.7
70

mA

170

T.=Tamax

135

150

T.=Tamln

180

200

1.0

nA

V

Ta=Tam ...

150

nA

V/mV

±12 ±13
70

mV

500

15

±12

Unit

200

Ta=Tamax

70
Power Consumption
(Both Amplifiers)

6
7.5

200

2.3
Supply Current
(Both Amplifiers)

2

200

TaminST..STamax

RL~2KO

5

20

TaminSTaSTam..

RL~10KO

1

70

TaminST.STamax

Vour

MC4558C

Max Min Typ Max

T.=Tam..

TaminST.STamax

Common Mode
Rejection Ratio

Output Voltage Swing

RL~2.0KO

Typ

mV

V/p.s

.1.0
0.3

0.3

p's

15

15

%

• MC45581: T amin = - 40·C, Tamax = + 85·C
MC4558AC/MC4558C: Tamin = O·C, Tamax = + 70·C

c8

SAMSUNG SEMICONDUCTOR

465

I

LINEAR INTEGRATED CIRCUIT

MC4558C/AC/I

TYPICAL PERFO.RMANCE CHARACTERISTICS
RMS NOISE Vs SOURCE RESISTANCE

BURST NOISE Vs SOURCE RESISTANCE
1000
1,OHz

~
o

10

100

l.oK

10K

1001<

_

Fig. 1 SOURCE REBI8TAHCI! (II)

Fig.2 SOURCE_ (II)

OUTPUT NOISE V. SOURCE RESISTANCE
10

140

1=
1=

f=f-

.i

SPECI"RAL NOISE DENSITY

F

120

.

lD

\

...

y.

\

I

I

I

.l~l..

.........

V
u

40

oi

1

,
G.01

10

100

. l.oK

10K

100K

l.oM

o

10

100

FIg.3 SOUIICE-.va (II)

l.oK

10K

FIg.4FMGUINCYIHII

PHASE MARGIN V. FREQUENCY

OPEN LOOP FREQUENCY RESPONSE

._-

180
+1«)

.-"""'-

,

fOO

1.

100

1+

80

l\.

. l+4C)

~

I\..

'1\.

+20

40

"\

o

--

20

I
lD

10

100

I"'

l.OK 10K 100K 1.I1M _

1'lg.5FMGUINCYIHII

c8

,

\

~

I\..

~+80

-20

'" \

180

SAMSUNG SEMICONDUCTOR

o lD

10

i

1\ u ItTyliAIN
.\

I

I

,

100 1.OK 10K 100K 1.oM _

Flg.S - I I 1 I I

466

MC4558C/AC/I

LINEAR INTEGRATED CIRCUIT

POSITIVE OUTPUT VOLTAGE SWING
Vs LOAD RESISTANCE
15

NEGATIVE OUTPUT VOLTAGE SWING
Vs LOAD RESISTANCE
15

±15V SUPPLIES

/'

13

III~

13

I' ± 15V SUPPLIES
±12V

'±12V

V

!

11

V

Ii

W 9.0

~

II

3.0

1.0

g

"o~

±6V

J.~

"

~

±'iN

~

~
100

500 1.oK 2.oK

Fig. 7

7.0

10K 20K • 5OK100K

±6V

5.0

-

/I

1.0
100

±:w

I
500

Fig. 8

LOAD RESISTANCE (II)

--

I

3_0

±:w

±9V

V

II
10K

1DK 2.oK

LOAD RESISTANCE

20K

I

SOK100K

(II)

POWER BANDWIDTH
(LARGE SIGNAL SWING VERSUS FREQUENCY)
28

24

1
;e

i

~

i

TRANSIENT RESPONSE TEST CIRCUIT

20

18

>-o-+---~

__ ThSoo~
(Output)

RL

12

CL

§
f. e.o

\
10

100

Fig. 9

c8

loOK

10K

lOOK

FREQUENCY(Hz}

SA.MSUNG SEMICONDUCTOR

100M

Fig. 10

467

KA319

LINEAR INTERGRATED CIRCUIT

DUAL HIGH SPEED VOLTAGE COMPABATOR

14 DIP

The KA319 is a dual high speed voltage comparator desigfled to
operate from a single + SV supply up to ± 1SV dual supplies.
Open collector of the output stage makes the KA319 compatible with
RTl, DTl and TTL as well as capable of driving lamps and relays at
currents up to 2SmA. Typical response time of 80ns with ± 1SV power
supplies makes the KA319 ideal for application in fast AID converts, level
shifters, oscillaters, and multivibrators.
14 SOP

FEATURES
•
•
•
•
•
•
•

Operates form a single 5V supply
Typically 80ns response time at ± 15V
Open collector outputs: up to + 35V
High output drive current: 25mA
Inputs and outputs can be isolated from system ground
Minimum fan·out of 2 (each side)
Two' independent compators

BLOCK DIAGRAM

ORDERING INFORMATION
Device

Package

KA319N

14 DIP

KA319D

14 SOP

Operating Temperature
0- + 70·e

SCHEMATIC DIAGRAM
'-~~~--~----~--~-----4~--~-4~----------~----ovcc

1-+---+--~-oOUTPUT

c8

SAMSUNG SEMICONDUCTOR

468

KA319

LINEAR INTERGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Supply Voltage
Output to Negative Supply Voltage
Ground to Negative Supply Voltage
Ground to Positive Supply Voltage
Differential Input Voltage
Input Voltage
Output Short Circuit Duration
Power Dissipation
Operating Temperature Range
Storage Temperature Range

Vs
Vo-VEE
GND-VEE
GND-Vcc
V,D
V,

36
36
25
18
±5
±15
10
500
0-+70
-65-+150

V
V
V
V
V
V
sec
mW
·C
·C

PD
Topr

Tstg

II

ELECTRICAL CHARACTERISTICS
(Vcc= +15V, VEE = -15V, Ta=25·C, unless otherwise specified)

Characteristic

Symbol

Input Offset Voltage (Note 1)

V,O

Input Offset Current (Note 1)

Input Bias Current

Test Conditions
Rss5K

Min

Typ

Max

2.0

8.0
10

TammSTaSTamax
80

1'0

250
liB

Voltage G'ain

Av

Response Time (Note 2)

t,

200
300

TamlnSTaS Tamax

1000
1200

TamlnSTaS Tamax
8

40

V,nS - 10mV, lout = 25mA
Saturation Voltage

VOL

VEE = 0, V,NS -10mV,
ISINKs3.2mA
Tamin.:STa:sTamax

Output Leakage Current

10L

V,"~10mV,

Vcc~4.5V,

Vout = 35V

nA
nA

ns

0.75

1.5

V

0.3

0.4

V

0.2

2

p.A

±13

Vs= ± 15V

mV

V/mV

80

Vs= ±15V

Unit

Input Voltage Range

V'CR

Differential Input Voltage

VID

Positive Supply Current

Iccl

Vcc =5V, VEE=OV

Positive Supply Current

Icc2

Vs=±15V

8

12.5

mA

Negative Supply Current

lEE

Vs= ± 15V

3

5

mA

TaminSTa:s Tamax

Vcc =5V, VEE=OV

1

3
±5
4.3

V
V
mA

Note: 1. The offset voltage and offset currents given are the maximum values required to drive the output within
a volt of either supply with a 1mA load. Thus, these parameters define an error band arid take into account
the worst case effects of voltage gain and input impeance.
2. The response time specified is for a 100mV input step with 5mV overdrive.
3. TamlnSTaSTamax
KA319: Tamm=O·C, Tamax =70·C

c8

SAMSUNG SEMICONDUCTOR

469

KA319

LINEAR INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS
INPUT CURRENTS va TEMPERATURE
300

250

'.

r- I--

vsJ

SUPPLY CURRENTS va TEMPERATURE
12

:15V
10

BIAS

C·

.s....

1000-

POSITIVE SUPPLY, Vs = ± 15V

8.0

zw

a:
a:

6.0

is

...
..."
~

100

50

-

o

POSITIVE SUPPLY, Voc=5.QV, V£E=O
4.0

NEGATIVE SUPPLY Y. Vs= ± 15V
2.0

OFFSET

10

20

30
40
50
TEMPERATURE (0C)
Fig. 1

60

10

10

LJ6V

Va:::. ±15V

IE

r-~1,.=1.4KD

%

25

~
0

20

."
....

15

0

10

"

5.0

o

I

-0.6

-0.2

6.0

:E

5.0

~

.5
....

"0

3.0
2.0

20mV
1.0

>

6.0

~"
!i!
5
....
i!

5.0

r,

.

4.0
20mV
3.0
2.0
1.0

!>

1.'00
w

g"j!

-

I

/

....

2.0

\

2.OmV

\.

i!

1.0

o
0.2

0.8

50

1.0

100

150

350

---

Va= ±15V
I-To=ZS·C

V'S= ±15V

300

RI.=5000

V++=5.0V

/ f·o~v
1/

300

Fig. 4

I. .

j2.0mV

250

INPUT CHARACTERISTICS va DIFFERENTIAL
INPUT VOLTAGE
400

V

200

TIME (na)

T.=25·C

i

!Zw
a:
a:

"u
~

It-JI

.5

ZOO

100

i!!

50
MAXIMUM DIFF~rNT'iL
iNPUT VOLTAGE

~

i!!

-100
50

100

150

200

250

300

TIME(na)
Fig. 5

c8

I

3.0 ~

RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES
w

\5.OmV

V+ =5.OV

Ta=25°C

\

DIFFERENTIAL INPUT VOLTAGE (mVI
Fig. 3

:E

10

~:~::, -

" r-...
\ \ \
\ \
\.

1\

> 4.0

'0

I

-1.0

5.0

~

'/

-- -- -- --lJ.

6.0

"~

4.0 ~

'/

>.

....

:E

1.0

V+ =5.0V

/ /'

w

8.0

0

. I

/

%

!2

60

50

w

/

30

40

RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES

40

Ta=25 D C

30

TEMPEAATUIIE (0C)
Flg.Z

TRANSFER FUNCTION

35

20

SAMSUNG SEMICONDUCTOR

350

:',0

-8.0

-2.0

2.0

6.0

10

DIFFERENTIAL INPUT VOLTAGE (V)

Fig. 8

470

KA319

LINEAR INTEGRATED CIRCUIT
RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES

.."£
~
!i!

~

0

..
~
..g

6.0
5.0

4.0

\' \

2.0

V+=5.OV
Ta=25"C -

\\ \
\ \

3.0

20mV

1.0

£

~:~~v_

~

0

\ 5.0mV\ 2.0mV

I\,

RESPONSE TIME FOR VARIOUS
INPUT OVERDRIVES
6.0
5.0

2.0
1.0

\..

/
1/1

20mV
3.0

I

.I.

Z

fl

4.0

Vs =5.OV
RL,='5000

12.0mV

V+ =5.OV
Ta=25"C

'/S.Omv

II

.."~

~-50

!i!

i-

1OO

!!

50

100

150

200

250

300

350

50

100

OUTPUT SATURATION VOLTAGE
va OUTPUT VOLTAGE
25

i..
iii
a:

15

a:
::>
u

~

10

0

J

5.0

/
V

300

I

350

SUPPLY CURRENT va SUPPLY VOLTAGE

Ta=~5"C

/

:c

B.O

Ii
::!a:

6.0

S

,.u

,/

./
,/' ~ITIVE SUPPlY

V

~

,.II:
til

'.0

2.0

5.0mr

V

./

- -~

i""'"

./
0.4

250

10

/V.=±15V
'~IUT OVERDriVE =
0.2

200

12

T~=25"C

/

20

150

TIME(ns)
fig. I

TIME(..)
Fig. 7

0.6

0.6

1.0

5.0

OUTPUT VOLTAGE (V)
fig. 9

NEGATIVE SUPPLY

10

15

SUPPLY VOLTAGE (+ V)
Fig. 10

OUTPUT LIMITING CHARACTERISTICS
va OUTPUT VOLTAGE
120 r----,---. .---,.---,--r----".2

100

i

1--H\---1--+--t---t---j 1.0
!:

Ii
::!a:

80 1--+-t-~~--t--+-~I---iOBz

u

so h/-t---t--~t--~FOo.:=--t-----l

0.6

40

H--j----:;..-r--t---t---t---j

0.4

20

I+-F-t----t---t---t---f----j

0.2

::>

,.I:

i

;;

~

~

'"

Ii!

2~

0

i

L-_~

__

~_~

__

~

__

~_-JO

5.0
10
OUTPUT. VOLTAGE (V)
fig. 11

c8

SAMSUNG SEMICONDUCTOR

15

471

KA361

LINEAR INTEGRATED CIRCUIT
14 DIP

HIGH SPEED VOLTAGE COMPARATOR
The KA361 is a very high speed differential input; complementary TIL
output voltage comparator. Applications involve high speed AJD converts
and zero·crossing detectors in disc file systems. .

FEATURES
1480P

• Complementary TIL outputs
• Independent strobes
• High speed: 20ns (max)
• Operates from OP amp supplies: :!: 15V
• Low input offset voltage
• Versatile supply voltage range

BLOCK DIAGRAM

SCHEMATIC DIAGRAM
. STROBE1

,---~+;::=:;=;==+=:8vcc

OUTPun

~----1f-OGND

ORDERING INFORMATION
Device

Package

KA361N

14 DIP

KA361D

14 SOP

Operating Temperature
OUTPUT2

O-+70·C

OPERATING CONDITIONS
Supply Voltage

c8

Min

Typ

Max

Unit

V
V
V

V+

5

15

VVee

-6

-15

4.75

5.25

SAMSUNG SEMICONDUCTOR

v-O-~--+~-~-----~~

472

KA361

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Positive Supply Voltage
Negative Supply Voltage
Gate Supply Voltage
Output Voltage
Differential Input VoltagEl
Input Voltage Range
Power Dissipation
Operating Temperature Range
Storage Temperature Range

V+
VVee
Your
V'D
V,
PD

+16
-16
+7
+7
±5
±6
600
0-+70
-65-+150

V
V
V
V
V
V
mW
·C
·C

Topr

Tstg

ELECTRICAL CHARACTERISTICS
(V+ = +10V, Vee = +5V,V- = -10V, Ta=25·C, unless otherwise specified)
Characteristic

Symbol

Test Conditions

Min Typ Max

Unit

0·C::s;Ta::S;70·C

Input Offset Voltage

V'O

1

5

mV

Input Bias Current

I,s

10

30

p.A

Input Offset Current

1'0

2

5

Voltage Gain

Av

3

Vim V

Input Resistance

R,

20

KO

f=1KHz

Logical "1" Output Voltage

VOH

Vee = 4. 75V, I.ourco = - 5mA

Logical "0" Output Voltage

VOL

Vcc = 4. 75V, I.'nk = 6.4mA

0.4

V

l.tH

Vcc=5.25V, V.trobo =2.4V

200

p.A

-1.6

mA

0.8

V

-55

mA

Strobe Input "1" Current

"-

2.4

Strobe Input "0" Current

Istl

Vee = 5.25V, V.trobe = 0.4V

Strobe Input "0" Voltage .

V.tl

Vee = 4.75V

V.tH

Vee = 4.75V

2
18

Strobe Input "1" Voltage

3.3

p.A

V

V

Output Short Circuit Current

los

Vee=5.25V, Vour=OV, V+ =10V, V- = -10V

Supply Current

1+

Vee = 5.25V, Tam,n::s;T.::s;Tamax

5

mA

Supply Current

1-

Vee = 5.25V, Tamm::s;Ta::s;Tamax

10

mA

Supply Current

Icc

Vee = 5.25V, Tamm::s;T.::s;Tamax

20

mA

Propagation Delay Time

tpd (0)

V'N = 50mV overdrive

14

20

ns

Propagation Delay Time

tpd (1)

V'N = 50mV overdrive

14

20

ns

td

V'N = 50mV overdrive

2

5

ns
ns
ns

Delay Between Output A and B
Strobe Delay Time (tpd (0))

td

V'N = 50mV overdrive

8

Strobe Delay Time (tpd (1))

td

V'N = 50mV overdrive

8

c8

SAMSUNG SEMICONDUCTOR

473

II

KA710C

LINEAR INTERGRATED CIRCUIT

HIGH SPEED VOLTAGE COMPARATOR
14 DIP

The KA710C is a h'igh speed voltage comparator intended for· use as
an accurate, low-level digital level sensor or as a replacement for
operational amplifiers in comparator applications where speed is of
prime importance.
The output of the comparator is compatible with all intergrated logic
forms.
The K,l\710C is useful as pulse height disciminators, a variable threshold
schmitt trigger, voltage comparators in high-speed AID converters, a
memory sense amplifier or a high noise immunity line receiver.

14 SOP

FEATURES

41#

• Low offset voltage: SmV
• High gain: 1000 (Min)
• High speed: 40ns Typ

1

BLOCK DIAGRAM

ORDERING INFORMATION
Device

Package

KA710CN

14 DIP

KA710CD

14 SOP

Operating Temperature
0- + 70·C·

SCHEMATIC DIAGRAM
r-------------------------------~------OVcc

UK

2.BK

500

3.9K

INVERTING INPUT
NON·INVERTING INPUT

C>-----k__--....__~..l
C>----------+--------l

~------r--+------oOUTPUT

1.7K

GND

c8

SAM'SUNG SEMICONDU~OR

474

LINEAR INTERGRATED CIRCUIT

KA710C
ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Positive Supply Voltage
Negative Supply Voltage
Peak Output Current
Output Short Circuit Duration
Differential Input Voltage
Input Voltage
Power Dissipation
Operating Temperature Range
Storage Temperature Range

Vee
VEE
Ipeak

+14
-7
10
10
±5
±7
200
0-+70
-65-+150

V
V

VIO
VI
Po
Topr

Tslg

mA
Sec.
V
V

mW
·C
·C

ELECTRICAL CHARACTERISTICS
(Vee= +12V, VEE = -6V, Ta=25·C, unless otherwise specified)

Characteristic

Symbol
VIO

Input Offset Current

110

Input Bais Current

he

Large Signal Voltage Gain

Min

Rs;:s2000

Input Offset Voltage

Input Voltage Range

Test Conditions

Common Mode· Rejection Ratio

CMRR

Max

1.6

5.0

I 0;:sTa;:s70·C

6.5
1.8

Vour=1.4V

I 0;:sTa;:s70·C
I Ta=
Vee= -7.0V
Rs;:s2000

5.0
7.5

O·C
1000

Av
VieR

Typ

16

25

25

40

mV

p.A

p.A

1500

VN

98

dB

±5.0
70

Unit

V

Differential Input Voltage Range

VIOR

Output Voltage (High)

VOH

VIN 0!::5mV,016V

OUTPUT Voor.4OV
........

,

,.

~

",..

~

I - - - - iNPUTVti .tN

10-"

I--"""
26

---

""

45
55
TEllPEMrURE (.C)

65

7S

fig. •

c8

SAMSUNG SEMICONDUCTOR

479

LINEAR INTEGRATED CIRCUIT

LM211/LM311
TYPICAL APPLICATIONS
Switching Power Amplifier

,-----------~--------------~----------~-------------O~e

R1

01
2N6125

620

R12

02
2N6125
OUTPUT----'----4

620

R13
RS
510

R4

300K
Rs
39K

R9

R14
510

39K

15K
Rs
INPUT

REFERENCE
R7
15K

Fig.1·

Relay Driver with Strobe

Digital Transmission Isolator

V+

Vee

TTL STROBE

Fig. 2

c8

SAMSUNG SEMICONDUCroR

Fig. 3

480

LM239/A, LM339/A, LM2901, LM3302 LINEAR INTEGRATED CIRCUIT
QUAD DIFFERENTIAL COMPARATOR
The LM239 series consists of four independent voltage comparators
that one designed to operate from single power supply over a wide range
'of voltage.

14 DIP

'FEATURES
• Single or dual supply operation
• Wide range of supply voltages LM239/A, LM339/A: 2 - 36V
(or::t:1-::t:18V)
LM2901 , LM3302: 2 - 28V
(or ::t:1- ::t:14V)
• Low supply current drain SOOpA lYJI.
• Open collector outputs for wired and connectors
• Low input bias current 25nA l\'p.'
• Low input offset currant ::t: SnA Typ.
• Low Input offset voltage ::t: 2mV Typ.
• ,Common mode input Yoltage range includes ground.
• Low output saturation IIOItage
• Output compatible with TTL, DTL and MOS logic
system

BLOCK DIAGRAM

c8

SAMSUNG SEMICONDUCTOR

14 SOP

I
ORDERING INFORMATION
Device

Package

LM239N
LM239AN

14 DIP

LM239D
LM239AD

14 SOP

LM339N
LM339AN

14 DIP

LM339D
LM339AD

14 SOP

LM2901N
LM2901D
LM3302N

14 DIP
14 SOP
14 DIP

Operating Temperature

-25-+85°e

0-70 o e

-45-+85°e

481

. LM239/A, LM~/A, LM2901, LM3302 LINEAR INTEGRATED CIRCUIT
SCHEMATIC DIAGRAM
r-_-----'-_ _ _~-----<>vcc
(OR

Vcc+)

NON INVERTING o---~--r
INPUT

r---~OUTPUT

INVERTING 0-------+---+------'
INPUT

L-_~_ _ _ _ _ _~~~_--oGNO

(OR
VCC-)

ABSOLUTE MAXIMUM RATINGS

.

c8

Characteristic

Symbol·

Value

Unit

Power Supply Voltage
Power Supply Voltage Only LM3302
Differential Input Voltage
Differential Input Voltage Only LM3302
Input Voltage
Input Voltage Only LM3302
Output Short Circuit to GND
Power Dissipation
Operating Temperature LM239/LM239A
LM339/LM339A
LM2901/LM3302
Storage Temperature.

Vs
Vs
VID
VID
V,
V,

± 18 or 36
± 14 or 28

V
V

36
28
-0.3 to +36
-0.3 to +28
Continuous
570
-25- +85
0-+70
-40- +85
-65-+150

it

SAMSUNG SEMICONDUCTOR

PD
Topr

Ts1g

V
V
V
mW
·C

·C
·C
·C

482

LM239/A, LM339/A, LM2901, LM3302 LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS
Characteristics

Input Offset Voltage

Symbol

V,O

Input Offset Current

(Vee = 5V, Ta = 25·C, unless otherwise specified)

LM239A1LM339A LM239/LM339

Test Condition
VeM=OV to Vcc-1.5V
Vo;::1.4V, Rs=O

1'0

Min T.yp Max. Min Typ Max
z1

Input Common Mode
Voltage Range

VieR

±5 z50

z5 z50

Z 150

Supply Current

Icc

tRES

Response Time

tREs
'

Output Saturation Voltage

Output Leakage Current

Sink

Vsa;

Ileak

Vee-2

0

Vee-2

2.5

Y'N = TTL Logic Swing
V",,=1.4V, VRL =5V, RL=5.1KO

Output Sink Current

0

2.0

V'N-~1V, V,N + =OV

l"nk=4mA
V,n - =0
Y'n = 1V

,

V.O = 5V

2.0
2.5

mA
V/mV

300

300

ns

6

6

16

1.3

/LS

16

mA

250 400

250 400

700

700

TamlnSTaSTamax

Vo=30V

0.8
1.0

V

200

1.3

V,N + =OV, Vos1.5V

nA

50 200

VRL =5V, RL=5.1KO
V'N-~1V,

nA

400
Vcc·lo5

1.0

Vee = 15V, RL~15KO (for large SWiAg)

250

Vcc·lo5 0

0.8

AVOL

25

0

RL=oo Vee =36V

Large Signal Response
Time

Voltage Gain

250

RL=OO ,

mV

z 150

400

Tamln::;TaSTamax

TamtgSTaSTamax

z5
±9.0

Tamln::;Ta::;Tainax

Ie

z1

±4.0

TamlnSTaSTamax

25
Input Bias Current

z2

Unit

0.1

0.1
1.0

mV
nA

1.0

/LA

• TamlnSTaST amax
LM239/LM239A: Tamln= -25·C, Tamax= +85·C
LM339/LM339A: Tamln = O·C, Tamax = + 70·C
LM2901/LM3302: Tamln= -40·C, Tamax= +85·C

c8

SAMSUNG SEMICONDUCTOR

483

I

LM239/A,LM339/A,LM2901,LM3302
ELECTRICAL CHARACTERISTICS
Characteristics

LINEAR INTEGRATED CIRCUIT

IYcc= 5V, Ta=25°C, unless otherwise specified)

. Test Condition

Symbol

LM2901

LM3302

Min Typ Max Min Typ Max
±2

±7

±3 ±20

9

±15

±40

±5 ±50

±3 ±100

I Tamin

Ts=O'C

40

Ta-+~

u

.
!;

Ta-+70"C-

;!!

20

20
30
SUPPl.Y VOLTAGE (V)

10

OUTPUT SATURATION VOLTAGE

OUT OF
SATURATION

/

V

~

V

IN~T O~ERD~IVE

I
I

•

>

3

!! ~-

E

<

I
1+5VI

>

~-VIN

r--

Ta= + 25°C

1

,~

5~±-

+

2

r.

r--

0

~ 0
~ -50
~-.100

/
0.001

II

30

RESPONSE TIME

/"

l/

20
SUPPLY VOLTAGE

w

l/

~

;!!

0.1

0.01

0.5

10

OUTPUT SINK CURRENT (mA)

1.5
TIME (,.a)

RESPONSE TIME

! INPlkov~RDR~VE

~

•

100mV

3

~

I
I I
IJ ~

2

1
0

5mV

/iomv

~

~

V.

+

0

o

0.5

1

1.5

V""

I

TIME (,--t--OVo

Vo
+VIN o-~~~IY
10K!!,

Fig. 7

Fig. 6

Inverting comparator with,Hysteresis

+VIN 0----1'"

3KII

>--+--0 Vo
1M!!

c8 SA~SUNG

SEMICONDUcroR

486

LM239/A, LM339/A, LM2901, LM3302
Driving C/MDS

LINEAR INTEGRATED CIRCUIT
Driving TTL

5V

5V

Fig. 10

Fig. 9
AND gate

I

DR gate
15V

1!'>V

3K!l

3K!l

3x100K!l -=#No~-P......
Ao-_~:":"",,

A

B o-_II"Ir--;'-....-l1:V"

B

+1~C
o "0" "1"

~~c

0---1;-'--,

o--"""'_+-'--v

A+B+C

"0" "1"

Fig. 11

Fig. 12

Large fan-in AND gate

Squarewave oscillator

15V
15V

100KO

4.3K!l

3K!l

Vo ..fLJ±Vcc

O~
"0" "1"

~-+---c;;I

A·B·C·D
15V

Fig. 13

c8

SAMSUNG SEMICONDUCTOR

f=100KHz

0--,.,..,-+--'---'
Fig. 14

487

LM239/A, LM339/A, LM2901, LM3302

LINEAR INTEGRATED CIRCUIT

ORlng the outputs

Peak auqio level display

15V
02

5.fN

3Kn

>--+--oVo

Rl0
6BOll
IN

lKIl
01

112
LM239

Rll

BBOIl

>------'6BOU
R12
13
-10 dB (0.6V)

R2

Fig. 16

Fig. 15

Zero crossing detector (split supplies)

Zero crossing detector (single supply)

VINmln ",,04V peak for 1% 'phase distortion (.10 fJ)

15V

+vcc
R4

B.2KII

6BKU

Rl

R2

220
KIl

10KIl

>,,-1-0Vo

01

Fig. 1,8
D1 prevents input from going negative by more than O.6V:
R1+R2=R3
..
R3 .;; R5/10 for smaller error in zero crossing

c8

SAMSUNG SEMICONDUCTOR

488

LM2931A, .LM3931A, LM2903

LINEAR INTEGRATED CIRCUIT

DUAL DIFFERENTIAL COMPARATOR
8 DIP

The LM293 series consists of two independent voltage comparators
that one designed to operate from a single power supply over a wide
range of voltage.

FEATURES
•
•
•
•
•
•
•
•

8 SOP

Single Supply Operation: 2V to 36V
Dual Supply Operation: :t 1V to :t 18V
Allow Comparison of Voltages Near Ground Potential
Low Current Drain 800J.unt (1 to 10mV) of positive feedback (hysteresis) cauSes such a rapid transition that oscillations due to stray feedback are not possible.
If is good design practice to ground all unused pins.
The differential input voltage may be larger than positive supply withoUt damaging the device. Note that voltages more negative
than -0.3V should not used: an input clamping diode can be used as protection.
The output of the LM239 series is the uncommitted collector of a NPN transistor with grounded emitter. The allows
the device to be used like any open·collector gate providing the OR-wide facility.
The output sink current capability is approximately 16mA; if this limit is exceeded, the output transistor will come out of saturation and the output voltate will rise very rapidly.
Under this limit, the output saturation voltage is limited by the approximatively 600 r... of the output transistor.

TYPICAL APPLICATIONS
Basic comparator

(Vee =

+ 15V)
Inverting comparator with
Hysteresis

Non-inverting comparator with Hysteresis

+vcc

+vcc

+VAEF

3KII

>-4-0

vo

+VIN

3K!I
10KII

+VIN

+v

3KII

1M1l
1MII

Fig. 3

Fig. 4

Driving C-MOS
+5V

Fig. 6

c8

SAMSUNG

S~MICONDUcroR

1MII

Fig. 5

Driving TTL
+5V

Fig. 7

494

LINEAR INTEGRATED CIRCUIT

LM293/A, LM393/A, LM2903
APPLICATION INFORMATION (continued)
AND gate

OR gate
+V..

+vcc

3K{!

3KIl
3x100KIl

A 0---4\,,.,,,,...,

>--4--oA·B·C

A 0--410__--,
B

Bo---4\,"""'~----~~~

n-_ _

-+----~-I,...,

C 0-_ _-'

+V.. C 0---4\,"""'~

+~
o "0" "1"

oS

"0" "1"

Large fan·in AND gate

Squarewave oscillator

+Vre

A-BOO

+Vcc-ro --J A,o--N-~-=':::.:..::.t·!.o"
''0''

II

Fig. 9

Fig. 8

"l"IB o---M~
Co---M~

oo--M..::..:..J
Fig. 11
One-shot multivibrator

Pulse generator

+Vre
15K!!
R1

D1

1M1l

1N914

R2

D2

10KII

-.::;...:: V+

1ms

1N914

:J

">4--ovo

10

C
11

Vo

Fig. 12

c8

SAMSUNG SEMICONDUCTOR

Fig. 13

495

KS555

CMOS INTEGRATED CIRCUIT

CMOS TIMER
8 DIP

The KS555 is CMOS RC ·timer providing significantly improved performance over the standard NE555,While at the same time being direct
replacements for those devices in most applications. Improved
parameters include low supply current, wide operating supply voltage
range, low THRESHOLD, TRIGGER and RESET currents, no crowbarring of the supply current during output transitions, higher frequency
performance and no requirement to decouple CONTROL VOLTAGE for
stable operation.
Specifically, the KS555 is stable controller capable of producing accurate
time delays or frequencies. In the one shot mode, the pulse width of each
circuit is precisely controlled by one external resistor and capacitor. For
astable operation as an oscillator, the free running frequency and the duty
cycle are both accurately controlled by two external resistors and one
capacitor. Unlike the regular bipolar 555 device, the CONTROL
VOLTAGE terminal need not be decoupled with a capacitor. The circuit
is triggered and reset on falling (negative) waveforms, and the output
inverter can source or sink currents large enough to drive TTL loads, or
provide minimal offsets to drive CMOS loads.

FEATURES
•
•
•
•
•
•

8 SOP

APPLICATIONS

Exact equivalent in most cases for NE555.
• P.recision Timing
Low Supply Current: 80pA Typ.
• Pulse Generation
Extremely low trigger, threshold and. reset current: 20pA Typ.
• Sequential Timing
High speed operation: 500KHz
• Time Delay Generation
Wide operation supply voltage range: 2 to 18 Volts
• Pulse Width Modulation
Normal reset function: No crowbarring of supply during output
• Pulse Position Modulation
transition.
• Missing Pulse Detector
Timing from microseconds through hours
Operates In both astable and monostable modes
ORDERING INFORMATION
Adjustable duty cycle
Device
Package Operating Temperature
High output source/sink driver can drive TTL/CMOS

•
.•
•
•
• Highly immunized to static charge

KS555N

8 DIP

-20 _ +85°C

SCHEMATIC DI.rA::G-:R:A~M~-.,..._--.,_ _ _..,'=K=S5~55=D==8:;S=O=P======::;:===o;~
,
vee
8

THRESHOLD

0-----1
6

CONTROL VOLTAGE

OUTPUT

GN[

.c8

SAMSUNG SEMICONDUCTOR

496

CMOS INTEGRATED CIRCUIT

KS555

BLOCK DIAGRAM
vee
R
THRESHOLD
6

10-----...-------1

~-___._--I

">0.------1') OUTPUT
3

CONTROL
VOLTAGE

JI;lISCHARGE

R

2o-------~------~

TRIGGER

I

GNJ1

COMPARATOR

R

B

GND

1

This block diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs.
R= 100K{J±20% Typ.
.

TRUTH TABLE
Threshold
Voltage

Trigger
Voltage

Don't Care

Don't Care

-- ----------

>2/3 (Vee)

---

----------

Discharge
Switch

Low

Low

On

High

Low

High

Stable

On
f------- - - - Stable

High

High

Off

-

1/3(Vee) - 2/3(Vee)
< 1/3(Vee) - 2/3(Vee) >_________
c---'.
Don't Care
< 1/3 (Vee)
--.-----~------

Output

-------

> 113 (Vee)
----~----

Reset

- - - - - - ' - f---

'-

Note: RESET will dominate all other input.TRIGGER will dominate over THRESHOLD.

ABSOLUTE MAXIMUM RATINGS
Characteristic
Supply Voltage
Input Voltage
(Trigger, Control Voltage,
Threshold and Reset)
Output Current
Power Dissipation
Operating Temperature Range
Storage Temperature Range

Symbol
Vee
VIN

lOUT

Po
Topr
T.tg

(Note 1)
Value
18
-0.3 - Vee +0.3

100
200
-20 - +85
-65 - +150

Unit
V

V

mA
mW
°C
DC

Note 1: Stresses above those listed under absolute maximum rating may cause permanent damage to the device.

c8

SAMSUNG SEMICONDUcroR

497

KS555.

CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
(T. = 25°C. Vee =2 to 15 Volts unless otherwise specified)

Characteristic
Supply Voltage Range

Symbol
Vee

Supply Current

Icc

Timing Error

MT

I~itial Accuracy
Drift With Temperature

Drift With Supply Voltage

1\'p

Max
18

V

Vec=2V

60

200

pA

Vc;e=18V

120

300

pA

R.= Rb = 1KO to 100KO
C=0.1/LF.
5Y :sVee:S 15V

2.0

5.0

Test Conditions
-20°C -----{]I

DlACLOCK

+5V

~--t!~---=----qL___lP"-~+:!t;-----II--~..JA/D IN
o.47~F

",.

KEY PULSE

KSV3100A
-5V »-·4J"'~/yr---'4J/~Ifr---'\I""'¥-A...910
lK
560

...sitive supply pin for the analog part of the AID converter.

Pin 37

Ground of Reference Voltage AID Converter
.To this pin must be connected the ground end of the decoupling which is at pin 25.

Pin 36

External Analog Input
The diagram of this Input is shown in Fig. 10. Pin 38 serves for feeding an external analog
signal Into the output amplifier of the KSV3100A instead of the D/A-converted signal
orlginatirig from pin 4, to 13.

Pin 39

Output Signal Switchover Input
This pin whose diagram is shown in Fig. 5, is intended for enabling the external analog
signal fed to pin 38.

Pin 40

No Connection

c8

SAMSUNG

SEMICO~DUCTOR

528

KSV3100A

LINEAR INTEGRATED CIRCUIT

APPENDIX: APPLICATION CIRCUITS
KSV3100~

DC Coupled
Video Signal

Fig. 11: Operation without clamping of the input signal'
Pin 20 (peak clamping enable input) should be opened, while pin 23 (clamping pulse input) remains at OV. The input
signal is applied to the analog input, pin 21, without coupling capacitor such that it lies between 0 and + 2V.

KSV3100A
Keyed

Clamping
___ ___ J

O.47W

+

Video Signal

]on

-5V

Fig. 12: Operation with peak clamping
The input signal is clamped automatically to the negative peak value. Pin 20 is connected to + 5V via a 391<0 resistor,
and pin 22 (clamping level input) is connected, as desired, to zero or a voltage between -1 and + 2V. The input
signal is fed to pin 21 by way of a coupling capacitor, and no key pulse (clamping pulse) is needed.

c8SAMSUNG SEMICONDUCTOR

529

II

KSV3100A

LINEAR INTEGRATED CIRCUIT

KSV3100A
Keyed

Clamping

!ideo Signal

~

...---

+5V

1K

910
.

-5V

Fig. 13: Operation with keyed clamping
The input signal is applied to pin 21 through a coupling capacitor. Pin 20 must not be connected. While the input
signal is at the desired clamping level, an high-level is applied at the clamping pulse input, pin 23. By this means
the clamping switch in the KSV3100A connects the input with the clamping level at pin 22 and recharges the coupling
capacitor accordingly. The clamping level can be set to zero or, by means of an external voltage devider, to any
desired value between - 1 and + 2V~

c8

SAMSUNG SEMICONDUCTOR

.530

PRELIMINARY

KSV3110

LINEAR INTEGRATED CIRCUIT

HIGH·SPEED AJD·D/A CONVERTER
Samsung KSV3110, VLSI circuit in CI (Collector Implanted) technology
consists of a high-speed flash-type 8-bit AID converter and a high-speed
low-glitch 10-bit D/A converter designed as an weighted current
sources. Also, the various auxiliary circuits, as reference voltage
voltqge sources, pre-amplifier, input clamping circuit and feed-in output
amplifier are integrated on the single chip.

40 DIP

KSV3110 has been developed for use in all applications which call for
a high-speed A/D-D/A converter.
For instance, this VLSI circuit can be used to advantage to decode
television signals in Pay.:nt converters or for MAC converters used in
direct satellite broadcast.
Other promising applications can be seen in industrial electroniCS, e.g.
in conjunction with sign!!1 processing.
Although KSV311 0 was initially designed as high-speed codecs for the
video range, it can be used with equal benefits for lower frequencies,
even down to zero.

BLOCK DIAGRAM
KSV3110

Fig. 1

The auxiliary circuits contained on-chip provide versatile potential applications needing a minimum of external components.
For example, an impedance converter is connected upstream of the AID converter to provide a high-impedance signal input,
in spite of the high input capacitance of the AID converter. The reference voHage for the AID converter is generated on-chip,
but both the ground of the Circuit and the reference voHage are led to pins, so that an external filter capacitor may be connected.
Further, the input is equipped with switches which optionally provide operation with keyed clamping or peak clamping or
wijhout clamping. Also the D/A converter's reference voltage is generated on-chip, and a gated amplifier is arranged at the
output of the D/A converter so that an external analog signal can be fed-in instead of the signal delivered by the D/A converter.
. Separate clock inputs are provided for the AID converter and the D/A converter thus enabling the application of time
compression procedures.
All inputs and outputs are TIL compatible.

c8

SAMSUNG SEMICONDUCTOR

531

PRELIMINARY

KSV3110

LINEAR INTEGRATED CIRCUIT

PIN DESCRIPTION
Pin No.

Description

Pin No.

1
2
3
4
5.
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

Analog Output D/A Converter
- 5V Supply D/A-Analog
- 5V Supply D/A Converter-Digital
Digital Input Bit 9 (MSB)
Digital Input Bit 8
Digital Input Bit 7
Digital Input Bit 6
Digital Input Bit 5
Digital Input Bit 4
Digital Input Bit 3
Digital Input Bit 2
Digital Input Bit 1
Digital Input Bit 0 (LSB)
+ 5V Supply D/A Converter-Analog-Digital
Clock Input D/A Converter
GND DIA Conv. & Clock AID Converter
-5V Supply AID Converter-Analog
Clock Input AID Converter
+5V Supply AID Converter
Peak Clamping Enable·lnput

21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

Description
Analog Input AID Converter
Clamping Level Input
Clamping Pulse Input
Analog Ground AID Converter
Reference Voltage AID Converter
+5V Supply AID Converter-Digital
Digital Output Bit 7 (MSB)
Digital Output Bit 6
Digital Output Bit 5
Digital Output Bit 4 .
Digital Output Bit 3
Digital Output Bit 2
Digital Output Bit 1
Digital Output Bit 0 (LSB)
Digital Ground AID Converter
+5V Supply AID Converter-Analog
GND of Ref. Voltage AID Converter
External Analog Input
Output Signal Switchover Input
+ 5V Supply D/A-Analog

RECOMMENDED OPERATING CIRCUIT
o~OUT~--------------dml1~~~~~--------~+5V
-5v~--------~11

EXT. SIGNAL
D----_~+5V

~AGNo

D/AIN

,t,

LlGNo

o~CWCKr-~>--------------a1

AID CLOCK
+5V

______~~--~+l·~---------t~----~~-'AlOIN
:::~~~----~------~
39K
0.47.F
KEY PULSE

KSV3110

-5V~+5V
910

1K

560

Fig. 2

c8

SAMSUNG SEMICONDUCTOR

532

PRELIMINARY

LINEAR INTEGRATED CIRCUIT

KSV3110

ABSOLUTE MAXIMUM RATINGS
Characteristics

Symbol

Value

Unit

Vee
VEE
V,
V,

6
-6

V
V
V
V
mA
DC
DC

Positive Supply Voltage
Negative Supply Voltage
Input Voltages (Digital)
Input Voltages (Analog)
Output Current Pin 2
Ambient Operating Temperature Range
Storage Temperature Range

-0.51-1 Vee +0.5
-0.51- 1Vee +0.5
±10
0-+70
-40 - +125

10
T.
Tstg

RECOMMENDED OPERATING CONDITIONS
Characteristics
Positive Supply Voltage
Negative Supply Voltage
AID Converter
Analog Input Voltage
Input Frequency, Analog Input
Clock Amplitude
Conversion Rate
Clock High Time (See Fig. 3)
Clock Low Time (See Fig. 3)
AID Output Voltage
Clamping Level
Clamping Pulse
Activation of Peak Clamping
D/A Converter
Clock Amplitude
Conversion Rate
Digital Input Voltage
Analog Input Voltage at Pin 38
Output Signal Switch Over Input
for the D/A Conver:ter Out
for the Ext. Signal (from Pin 38) Out

Symbol

Min

Typ

Max

Unit

Vee
VEE

4.75
-4.75

5
-5

5.25
-5.25

V
V

V,
f,
V18H

V'8L
f'8
tH
tL
VOH
VOL
V22
V23H
V23L

-

0

-

-

2
f o,l2
Vee
0.8
20

I

V

-

2.0
0
0
15
35
2.4
Vee
0.4
0
-1
+2
2.0
Vee
0.8
0
Resistor of 20 to 6OKO
from Pin 20 to + 5V

V
V
MSPS·
ns
ns
V
V
V
V
V

-

Vee
0.8
20
Vee
0.8
+3

V
V
MSPS·
V
V
V

0.8
Vee

V
V

V'5H
V'5L
f'5
V,H
V,L
Vas

2.0
0
0
2.0
0
-1

V39
V39

0
2

-

-

• MSPS (Mega Sample Per Second)

c8

SAMSUNG SEMICONDUCI*OR

533

PRELIMINARY

)

LINEAR INTEGRATED CIRCUIT

KSV3110
ELECTRICAL CHARACTERISTICS
Characteristic
Current Consumption

(Vee =5V, V EE = -5V, f,5=20MHz, f,s=20MHz, Ta=25°Cj

Symbol

Min

Typ

Max

Icc

-

90
-80

120
-110

-

1.2

lEE

Power. Dissipation

PTOT

Total Transter Time A/D·D/A

trOT

AID

. Unit
mA
mA

W

-

See Fig. 3

Converter

. Input Current Pin 21
Input Capacitance Pin 21

I,
C,

-

2
10

-

p.A

MO
MHz

pF

Input Impedance Pin 21

3dB Bandwidth of the Input Amp.

-

-

Keyed Clamping Active Level

V23

2.0

-

Vee

V

RON

-

300

-

Ohm

-

200

-

p.A

at f=1KHz.

2,

at f=10MHz

2,

. On Resistance of the Clamping Switch
Between Pin' 21 and 22
Input Current of the Clamping Level
Input Pin 22

122 .

Aperture Delay ( ® in Fig. 3)

tAD

Digital Output Delay ( ® in Fig. 3)

tov

Transfer Time ( ® in Fig. 3)

tw

Differential Non·Linearity

100
50

-

20

-

10

ns

18

-

ns

One clock period

Code of the Digital Output Signal

-

Output CODE at the Input
with V2; =OV
with V2, = Vre,

-

Internal Reference Voltage

V25

1.8

2.0

2.2

20

-

15
2

-

Absolute Non-Linearity
Number of Bits

KO

See "Ordering Information"

-

1

.-

8

-

%

Binary

-

00000000
11111111

V

D/A Converter
Output Impedance Pin 2
Input Current Pin 38

110

0

p.A·

Internal Reference Voltage

Vre,

1.8

2.0

2.2

V

Input Resister Hold Time ( (fJ in Fig. 3)

t'H

6.0

t'H

20

-

ns

Input Resister Setup Time (ill in Fig. 3)

-

Differential Non-Linearity

See "Ordering Information"

-

-

%

Code of the Digital Input Signal

-

Output Signal at the Input
with 00000 00000
with 1 1 1 1 1 1 1 1 1 1

V2
V2

-

Absolute Non-Linearity
Number of Bits

c8

SAMSUNG SEMICONDUCTOR.

1

-

10

-'-

Binary
0
2

-

ns

V
V

534

PRELIMINARY

KSV3110

LINEAR INTEGRATED CIRCUIT

ORDERING INFORMATION
KSV3110 has four kind of version according to the accuracy bit (so called 'Precision') of D/A Converter, and their marking
specifications are as follow;

Device

Package

Temperature Range

DIA Converter

AID Converter

Accurary Bit

Dltt, Nonlinearity

KSV,3110CN-10

10 bit

± 1/2 LSB

KSV3110CN·9

9 bit'

±1 LSB

8 bit

±2 LSB

7 but

±4 LSB

KSV3110CN-8

40 DIP

0- +70·C

KSV3110CN·7

Dltt. Nonlinearity

±1/2 LSB

• The accuracy of A/D Converter can be guaranteed as '8 bit' (differential nonlinearity = ± 1/2 LSB) regardless of the
D/A Converter's accuracy.

TIMING. DIAGRAM

II

Clock ADC

AID

Converter
Analog
Input

Data Qut

Clock DAC

DIA
Converter

Data In

CD Sample
CD Aperture Delay
® Digital Output Delay
® Data Valid (after Sample CD)
® Transfer Time AID
® Total Transfer Time AID·
D/A with Common Clock

CD Input Register Hold Time
® Input Register Setup Time

Analog Qutpu.t

Fig. 3

c8

SAMSUNG SEMICQNDUcroR

535·

PRELIMINARY

LINEAR INTEGRATED CIRCUIT

KSV3110

INNER CONFIGURATION OF THE CONNECTION PINS
The following figures schematically show the circuitry at the various pins.

+sv

+5V

x
x

_*"----+-_ -sv
-----+--f--.+-..,...O

Fig. 4: Pin 1, Output

-5V

200--_"'\1\1\.--.--;

Fig. ·5: Pins 4 to 13, 15, 18, 23 and 39, Inputs
22G--+--.r--4----j-- -t-------'

x

Fig. 6: Pins 20 and 22, Inputs

+sv

Fig. 7: Pin 21, Input
+SV

x

---~-~~+-~-o

_ _ _ _ _ _ _ _-+-_-sv
Fig. 8: Pin 25, Reference Voltage Pin

ciS

SAMSUNG SEMICONDUCTOR

--+-~--+-4--0

_ _ _-\-_ _ _~~-5V

Fig. 9: Pins 27 to 34, Outputs

536

PRELIMINARY

KSV3110

LINEAR INTEGRATED CIRCUIT

x

Fig. 10: Pin 38, Input
x =protection diode

DESCRIPTION OF THE CONNECTIONS AND THE SIGNALS
Pin No.

Description

Pin 1

Analog Output D/A Converter
This pin whose diagram is shown in Fig. 4, is the output for the processed analog signal
either originating fro,!, the D/A converter or from the external.analog input pin 38.

Pin 2

- 5 Volt Supply D/A Converter, Analog
This pin gets the negative supply for the analog part of the D/A converter

Pin 3

- 5 Volt Supply D/A Convetter, Digital
This pin gets the negative supply for the digital part of the D/A converter.

Pin 4to 13

Digital Inputs Bit 9 to Bit 0
This diagram of these pins i~ shown in Fig. 5. They are the inputs of the D/A converter and
not·used inputs should be connected to the ground.

Pin 14

+5 Volt Supply D/A Converter, Digital
This pin gets the poSitive supply for the digital part of the D/A converter.

Pin 15

Clock Input D/A Converter
This pin whose diagram is shown in Fig. 5 must be supplied with the clock signal for the
D/A converter.

Pin 16

Ground D/A Converter and Clock AID Converter
This pin serves as ground pin for the D/A converter and for the clock of the AID converter.

Pin 17

-5 Volt Supply AID Converter, Analog
This pin is the negative supply pin for the analog part of the AID converter.

Pin 18

Clock Input AID Converter
The diagram of this pin is shown in Fig. 5. Pin 18 is supplied with the ciock of the AID
converter.

Pin 19

+5 Volt Supply AID Converter
Via this pin the AID converter gets its positive supply.

Pin 20

Peak Clamping Enable Input
Via pin 20 whose diagram is shown in Fig. 6, the peak clamping facility can be enabled.

c8SAMSUNG SEMICONDUCTOR

537

II

PRELIMINARY

LINEAR INTEGRATED CIRCUIT

KSV3110

DESCRIPTION OF THE CONNECTIONS AND THE SIGNALS (Continued)
Pin No.

Description

Pin 21

Analog Input AID Converter
Fig. 7 is the diagram of this input. To pin 21 is applied the analog signal to be converted
into digital.

Pin 22

Clamping Level Input
Via this pin whose diagram is shown in Fig. 6, the input of the AID converter is supplied
with the desired clamping level.

. Pin 23

Clamping Pulse Input
Fig. 5 is the diagram of this input. Pin 23 must be supplied with the key pulse if keyed
clamping is required.
.

Pin 24

Analog Ground AID Converter
This pin serves as ground pin for the analog part of the AID converter.

Pin 25

Reference Voltage AID Converter
This pin whose diagram is shown in Fig. 8, is intended for connecting a decoupling
capacitor to the AID converter's refe(ence voltage, the otlier end of this capacitor to pin ~.

Pin 26

+5 Volt Supply AID Converter, Digital
This pin is the positive supply pin for the digital part of the AID converter.

Pin 27 to 34

Digital Outputs Bit 7 to Bit 0
Fig. 9 shows the diagram of these outputs which supply the digitized analog signal in
parallel 8-bit code.

Pin 35

Digital Ground AID Converter
This pin is the ground connection for the digital part of the AID converter.

Pin 36

+5 Volt Supply AID Converter, Analog
This pin is the positive supply pin for the analog part of the AID converter.

Pin 37

Ground of Reference Voltage AID Converter
To this pin must be connected the ground end of the decoupling which is at pin 25.

Pin 38

External Analog Input
The diagram of this input is shown in Fig. 10. Pin 38 serves for feeding an external analog
signal into the output amplifier of the KSV3110 instead of the D/A-converted signal
originating from pin 4 to 13.

Pin 39

·Output Signal Switchover Input
This pin whose diagram is shown in Fig. 5, is intended for enabling the external analog
signal fed to pin 38.

Pin 40

c8

+ 5 Volt

Supply D/A Converter, Analog
This pin is the negative supply pin for the analog parts of the D/A converter

SAMSUNG SEMICONDUCTOR

538

PRELIMINARY

KSV3110

LINEAR INTEGRATED CIRCUIT

APPENDIX: APPLICATION CIRCUITS
KSV3110
Keyed
Clamping
______ J

OCCoupled
Video Signal

Fig. 11: Operation without clamping of the input signal
Pin 20 (peak clamping enable input) should be opened, while pin 23 (clamping pulse input) remains at OV. The input
signal is applied to the analog input, pin 21, without coupling capacitor such that it lies between 0 and + 2V.

KSV3110

+5V

}on

-5V

Fig. 12: Operation with peak clamping
The input signal is clamped automatically to the negative peak value. Pin 20 is connected to + 5V via a 391<0 resistor,
and pin 22 (clamping level input) is connected, as deSired, to zero or a voltage between -1 and + 2V. The input
signal is fed to pin 21 by way of a coupling capacitor, and no key pulse (clamping pulse) is needed.

c8

SAMSUNG SEMICONDUCTOR

539

II

PRELIMINARY

KSV3110

LINEAR INTEGRATED CIRCUIT

KSV3110
Keyed
Clamping

(ideo Signal

60
[

f----

+SV

1K

910

-SV

Fig. 13:.0peralion wilh keyed clamping
The input signal is applied 10 pin 21 through a coupling capacitor. Pin 20 must not be connected. While the input
signal is at the desired clamping level, an high-level is applied at the clamping pulse input, pin 23. By this means
the clamping switch in the KSV311 0 connects the input with the clamping level at pin 22 and recharges the-coupling
capacitor accordingly. The clamping level can be sel to zero or, by means of an external voltage devider, to any
desired value between ~ 1 and + 2V.

c8

SAMSUNG SEMICONDUCTOR

540

PRELIMINARY

KSV3208

LINEAR INTEGRATED CIRCUIT

HIGH·SPEED AID CONVERTER

28 DIP

Samsung KSV3208, VLSI circuit in CI (Collector Implanted) technology,
consists of a high-speed flash-type 8-bit AID converter. Also, the various
auxiliary circuits, as reference voltage sources, pre-amplifier, input
.
clamping circuits are integrated on the single chip.
KSV3208 has been developed for use'in all applications which call for
a high-speed AID converter.
For instance, this VLSI circuit can be used to advantage to decode
television signals in Pay-TV converters or for MAC converters used in
,
direct satellite broadcast.'
Other promising applications can be seen in industrial electronics, e.g.
in conjunction with signal processing.
Although KSV3208 was initially designed as high-speed converter for
video frequency 'range, it can be used with equal benefits for lower
frequencies, even down to zero.

ORDERING INFORMATION

II

BLOCK DIAGRAM

Voltage
Reference

KSV;i208

Flash
AID

VIDEO
SIGNAL

Converter

8 Bits

Clock

~----~--------------~17~------------~------------~

Fig. 1
The auxiliary circuits contained on-chip provide versatile potential applications needing a minimum of external
components. For example, an impedance converter is connected upstream of the AID converter to provide a highimpedance signal input in spite of the high input capacitance of the AID converter. The reference voltage for the
AID converter is generated on-chip, but both the ground of the circuit and the reference voltage are fed to pins,
so that an external filter capaCitor may be connected.
Further, the input is equipped with switches which optionally provide operation with keyed clamping of peak
clamping or without clamping.
All inputs and outputs are TTL compatible.

c8

SAMSUNG SEMICONDUCTOR

541

PRELIMINARY

KSV3208

LINEAR INTEGRATED CIRCUIT

PIN DESCRIPTION
Pin No.

Description

1

GND of Reference Resistor String
+ 5V Supply of ECl Logic Part, Digital
GND of ECl to TIL Translator Part, Digital
Digital Output Bit 0 (lSB)
Digital Output Bit 1
Digital Output Bit 2
Digital Output Bit 3
Digital OutPlJt Bit 4
Digital Output Bit 5
Digital Output Bit 6
Digital Output Bit 7 (MSB)
+ 5V Supply of TIL Output Part, Digital
No Connection
GND of ECl logic Part, Digital
GND of Input Stage, Analog
+ VREF , Reference Voltage Point of Resistor String
Clock Input
No Connection
+ 5V Supply of Input Stage, Analog
- 5V Input Stage, Analog
Clamping Pulse Input
Clamping level Input
Analog Signal Input
Peak Clamp Enable Input
No Connection
No Connection
GND of ECl Clock Part, Digital
- 5V Supply of ECl logic Part, Digital

2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

.

R.ECOMMENDED OPERATING CIRCtJlT
28[J----------5V

- - - - - -........--5V

Fig. 5: Pin 16, Reference Voltage

Fig. 4: Pin 4 to 11, Outputs
---~-r---r---.---+5V

--------,..---.------.-+5V

22

x

o---+---r--+---+-+-~--'

'--+-_ _ _+-_~~nA~:ING

--~__+-4---0

x
--+-------'----5V

Fig. 6: Pin 17, 21 Input
--+----+------~_'____''__

- - - - - - r - - - r - - - + 5V
CLAMPING

_ _ 5V

Fig. 7 Pins 22 and 24, Inputs
x: Protection Diode

PIN 23 0--.--+--1

4--+--~-+---O

-~--~--'--------5V

Fig. 8: Pin 23, Input

c8

SAMSUNG SEMICONDUCTOR

545

II

PRELIMINARY

LINEAR INTEGRATED CIRCUIT

KSV3208

DESCRIPTION OF THE CONNECTIONS AND THE SIGNALS
Pin No.
Pin 1

Pin 2
Pin 3

Pin 4 to Pin 11

Pin 12

Description
GND of Reference Resistor String
This pin must be connected to the ground of the decoupling capacitor
whitch is at pin 16.
+ 5 Volt Supply of ECl logic Part, Digital
This pin is the positive supply pin for the ECl logic part.
Digital Ground of ECl to TTL Translator Pat1.
This pin is the digital ground connection for the TTL output stage
where ECl level is translated to TTL level.
Digital Outputs Bit 0 to Bit 7.
Fig. 4 shows the diagram of there outputs which supply the digitized
analog signal in parallel 8·bit code.

+ 5 Volt Supply off TTL Output Part, Digital
This pin is the digital positive supply pin for the TTL output stage
, where ECl level Is translated to TTL level.

Pin 14

Digital GND of ECl logic Part
This pin serves as the digital ground for the ECl logic part.

Pin 15

Analog GND of Input Stage
This pin serves as the analog ground for the input stage;
buffer amp, bandgap reference, clamp block.

Pin 16

+ VAEF, Reference Voltage Point of Resistor String
Tl)is pin whose diagram is shown Is Fig. 5, is intended for connecting a
decoupling capacitor to the AID converter's reference voltage. The other end
of this capacitor is connected to pin 1. (GND 9f Ref.erence Resistor String).

Pin 17

Clock Input
The diagram of this pin is shown in Fig. 6.
Pin 17 is supplied with the clock of AID converter.

Pin 1·9

+ 5 Volt Supply of Input Stage, Analog
This pin ,is the analog positive supply pin for the input stage;
bandgap reference.

Pin 20

Pin 21

Pin 22

Piri'23

-5 Volt Supply of Input Stage, Analog
This pin 'is the analog negative supply pin for the input stage;
buffer amp, bandgap reference, clamp block.
Clamping Pulse Input
Fig. 6 is diagram of this pin. Pin 21 must be supplied with the key pulse
if keyed clamping ,is required.
Clamping level Input
Via this pi!) whose diagram is shown is Fig. 7, the input of the AID
converter is· supplied with the desired clamping level.
Analog Signal Input
Fig. 8 is the diagram of this input. To pin 23 is applied the analog signal
to be converted into digital.

Pin 24

Peak Clamp Enable Input
Via pin 24 whose diagram is shown in Fig. 7, 'the peak clamping facilities
"
can be enable.

Pin 27

Digital GND of ECl Clock Part
This pin serves as the digital ground for the ECl clock block.

Pin 28

- 5 Volt Supply of ECl logic Part, Digital
This pin is the digital negative supply for the ECl logic part.

c8 SAMSU~G

SEMICONDUCTOR

546

PRELIMINARY

KSV3208

LINEAR INTEGRATED CIRCUIT

APPENDIX: APPLICATION CIRCUITS

Keyed
Clamping

Voltage
I

Reference

I

_.J

Flash
AID

DC COUPLED

Converter
8 Bits

Video Signal·

Fig. 9: Operation without clamping of the input signal
Pin 24 (peak clamping enable input) should be opened, while pin 21 (clamping pulse input) remains at OV.
The input signal is applied to the analog input, pin 23, without coupling capacitor such that it lies between
o and +2V

Keyed
r-+-_c_la_mping

Voltage

Reference

_...1

O.47~

+

Flash
AID

Converter
8 Bits

+5V

r

10n

-5V

Fig. 10: Operation with peak clamping
The input signal is clamped automatically to the negative peak value. Pin 24 is connected to + 5V via a
39Kohm resistor and pin 22 (clamping level input) is connected, as desired, to zero or a voltage betgween
-1 and + 2V. The input signal is fed to pin 23 by way of a coupling capacitor, and no key pulse (clamping
pulse) is needed.

c8

SAMSUNG SEMICONDUCTOR

547

I

PRELIMINARY
LINEAR INTEGRATED CIRCUIT

KSV3208

Keyed
Clamping

I
I
I

Vollage
. Reference

__ JI

Flash

AID
Converter
8 Bils

-5V

Fig. 11: Operation with keyed clamping
The input signal is applied to pin 23 through a coupling capacitor. Pin 24 must not be connected. While
the input signal is at the desired clamping level, an high-level is applied at the clamping pulse input, pin
21. By this means the clamping switch in the KSV3208 connects the input with the clamping level at pin
22 and recharges the coupling capaCitor accordingly. The clamping level can be set to zero
by means
of an external voltage devider, to any desired value between -1 and + 2V.

or,

c8

SAMSUNG SEMICONDUCTOR

548

KAD0808/KAD0809

CMOS INTEGRATED CIRCUIT

. 8·BIT I'P·COMPATIBLE AID CONVERTERS
WITH 8·CHANNEL MULTIPLEXER

28 DlP

The KAD0808/KAD0809 Analog to Digital converter is a monolithic
CMOS device with an 8-bit resolution, 8-channel input multiplexer and
microprocessor compatible control logic. It uses successive
approximation as the conversion technique.
The design of the KAD0808/KAD0809 has been optimized by
incorporating the most desirable aspects of several AID conversion
techniques. The KAD0808/KAD0809 offers high speed, high accuracy,
minimal temperature dependence, excellent long-term accuracy and
repeatability, and consumes minimal power.

FEATURES
Total unadjusted error- :!: 1/2 LSB or :!: 1 LSB
Resolution-8-bits
Conversion time-1001'S
No missing codes
Latched TRI-STATE output·
Easy interface to all microprocessors, or operates "stand alone"
Single supply-S VDe
.
8-channel multiplexer with latched control logic'
Outputs meet TTL voltage level specifications
OV to SV analog input voltage range with
ORDERING INFORMATION
single SV supply
• No zero or full-scale adjust required
Device
Package Temperature Range Dlff. Nonlinearity
• Standard 28·pin DIP package
KAD0808IN
:!:1/2 LSB
28 DI~ - 40·C - + 85·C
KAD0809IN
:!:3/4 LSB

•
•
•
•
•
•
•
•
•
•

BLOCK DIAGRAM

r:-------

I 8·BIT AID

,----'---

'i==:;---O

I

I-

I
I
I

8· ANALOG
INPUTS

30BIT
{
ADDRESS 0ADDRESS
LATCH ENABLE
(ALE)

8 CHANNELS
I
MULTIPLEXING
/----f-l
ANALOG
SWITCHES

ADDRESS
LATCH AND
DECODER

11

I
IL. _ _ _ _ _ _ _ _ _ _ ...JI

Vee GND REF(+)

=8

END OF CONVERSION
(EOC)

SAMSUNG SEMICONDUCTOR

REF(-)

OUTPUT (OE)
ENABLE

549

I

KAD0808IKAD0809
ABSOLUTE MAXIMUM

CMOS INTEGRATED CIRCUIT
RATINGS(Note·1 & 2)

Characteristic

Symbol

Supply Voltage (Note 3)
Voltage at Any Pin Except Control Inputs
Voltage at Control Inputs
Package Dissipation at Ta= 25·C
Operating Temperature
Storage Temperature Range

Vee
V,
V,
Po
Top,
T.tg

Value

Unit

6.5
-0.3V - (Vcc+0.3V)
-0.3V - +15V
875
- 40·C - + 85·C
-65·C - + 125·C

V
V
V
mW
·C .
·C

ELECTRICAL CHARACTERISTICS
Converter Specifications: Vee=5 VOC=V ..fl +), V..fl_)=GND, Tf =T,=20ns and IClK = 640KHz unless otherwise
stated.
Characteristic

Symbol

KAD0808
Total Unadjusted Error
(Note 5)

25·C
-40·C - 85·C

KAD0809
. Total Unadjusted Error
(Note 5)
Input Resistance
Analog Input Voltage Range
Comparator Input Current

'rest Conditions·

O·C - 70·C
-40·C. - 85·C

Min

:ryp

Max

Unit

-

±1/2
±3/4

LSB
LSB

±1

LSB

-

-

+12.
- 4

LSB

1.0

2.5

Rref

From. Rel( + ) to Ref( -)

Y'n

(Note 4) V( +) or V(-)

GND-0.10

Ion

Ic = 640KHz, (Note 6)

-2

-

-

-

KG

Vee +0.10

V

±0.5

2

p.A

10

200

nA

-10

-

nA

-

Vcc

V

0.4

V

0.3

3.0

mA

Vee

V

0.45

V

Analog Multiplexer
OFF Channel Leakage Current

10FFI+)

Vcc =5V, V,N =5V,.
Ta=25·C

OFF Channel Leakage Current

10FF(_)

Vee = 5V, Y,N = 0,
Ta=25·C

-200

Control Inputs
Vee- 1.5

Logical "1" Input Voltage

V,H

Logical "0" Input Voltage

V,l

Supply Current

Icc

fClK = 640KHz

Logical "1" Output Voltage

VOH

10= -360p.A

Logical "0" Output Voltage

VOL

lo=1.6mA

0

VOUT(O)

lo=1.2mA

0

Logical "0" Output Voltage EOC
TRI-STATE Output Current

c8

lOUT

SAMSUNG SEMICONDUcrOR

0

.Vo=5V
Vo=O

Vee-0.4

-3

-

0.45

V

3

p.A
p.A

-

550

CMOS INTEGRATED CIRCUIT

KAD0808/KAD0809
ELECTRICAL CHARACTERISTICS

Timing Specifications VCC=V re'I+I=5V, Vre'I_I=GND, t,=t,=20ns and Ta=25"C unless otherwise noted.
Characteristic

Symbol

Test Conditions

Min

Typ

Ma~

Unit

100

200

ns

100

200

ns

25

50

ns

Minimum Start Pulse Width

tws

(Figure 5)

Minimum ALE Pulse Width

tWAlE

(Figure 5)

Minimum Address Set-Up Time

t.

(Figure 5)

-

Minimum Address Hold Time

t.

(Figure 5)

-

25

50

ns

Analog MUX Delay Time
From ALE

td

Rs = on (Figure 5)

-

1

2.5

",S

125

250,

ns

125

250

ns

f c = 640KHz, (Figure 5)

90

100

116

",S

10

640

1280

KHz

-

10

15

pF

10

15

pF

OE Control to

a Logic State

OE Control to Hi-Z

tH10 tHO

Cl = 50pF, Rl= 10K (Figure 8)

t'H, tOH

Cl = 10pF, Rl = 10K (Figure 8)

Conversion Time

tCON

Clock Frequency

felK

Input Capacitance

C'N

At Control Inputs

TRI-STATE Output Capacitance

COUT

At TRI-STATE Outputs

Note 1:
Note 2:
Note 3:
Note 4:

Absolute maximum ratings are those values beyond which the life of the device may be impaired.
All voltages are measured with respect to GND, unless otherwise specified.
A zener diode exists, Internally, from Vee to GND and has a typical breakdown voltage of 7 Voe.
Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages
one diode drop below ground or one diode drop greater than the Vee supply. The spec allows 100mV
forward bias of either diode. This means that as long as the analog V,N does not exceed the supply voltage
by more than 100mV, the output code Will, be correct. To achieve an absolute OVoe to 5V oc input voltage
range will therefore require a minimum supply voltage 4.900 Voe over temperature variations, initial
tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, linearity,:and multiplexer errors. See Figure 3. None 'of those
AIDs requires a zero or full-scale adjust. However, if an all zero code is desired for an analog input other
than O.OV, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference voltages
can be adjusted to achieve this. See Figure 13.
'
Nole 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current
varies directly with clock frequency and lias little temperature dependence (Figure 6).

c8

SAMSUNG SEMICONDUCTOR

551

I

KAD0808lKAD0809

CMOS INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION
Multiplexer. The device contains an a·channel single·
ended analog signal multiplexer. A particular input
channel is selected by using the address decoder.
Table 1 shows the input states for the address lines
to select any channel. The address is latched into
the decoder on the low·to·high transition of the address
latch enable signal.

Address Line

Selected
Analog Channel

C

B

A

INO
IN1
IN2
IN3
IN4
INS
IN6
IN7

L
L
L
L
H
H
H
H

L
L
H
H
L
L
H
H

L
H
L
H
L
H
L
H

CONVERTER CHARACTERISTICS

The Converter
The heart of this single chip data acquisition system is its a·bit analog-to-digitlll converter. The converter is designed
to give fast, accurate, and repeatable conversions over a wide range of temperatures. The converter is partitioned
into 3 major sections: the 256R ladder network, the successive approximation register, and the comparator. The
'
converter's digital outputs are positive true.
The 256R ladder network approach (Figure 1) was chosen over the conventional R/2R ladder because of its
inherent monotonicity, which guarantees no missing digital codes. Monotonicity is particularly important in closed
loop feedback control systems. A non-monotonic relationship can cause oscillations that will be cata!!trophic for
the system. Additionally, the 256R network does not cause load variations on the reference voltage.
The bottom resistor and the top resistor of the ladder network in Figure 1 are not the same value as the remainder
of the network. The difference in these resistors causes the output characteristic to be symmetrical with the zero
and full·scale pOints of the transfer curve. The first output transition occurs wh'en the analQg signal has reached
+ 1/2 LSB and succeeding output transitions occur every 1 LSB later up to full-scale.
The successive approximation register (SAR) performs a iterations to approximate the input voltage. For any SAR
type converter, n-iterations are required for an n-bit converter. Figure 2 shows a typical example of a 3-bit
converter. In the KADOaOa, KADOa09 the approximation technique is extended to a bits using the 256R network.

~

CONTROLS FROM S.A,A.
______~A~______~\

REF(+)

.

: 256R

TO
COMPARATOR
INPUT

R

R

112~~
REF(-)

Fig_ 1 Resistor Ladder and Switch Tree

c8 SA~SUNG

SEMICONDUCTOR

552

KAD0808/KAD0809

CMOS INTEGRATED CIRCUIT

FUNCTIONAL DESCRIPTION

(Continued)-

The AID converter's successive approximation register (SAR) is reset on the positive edge of the start conversion
(SC) pulse. The conversion is begun on the falling edge of the start conversion pulse. A conversion in process
will be interrupted by receipt of a new start conversion pulse. Continuous conversion may be accomplished by
tying the end-of-conversion (EOC) output to the SC input. If used in this mode, an external start conversion pulse
should be applied after power up. End-of-conversion will go low between 0 and 8 clock pulses after the rising edge
of start conversion.
The most important section of the AID converter is the comparator. It is this section which Is responsible for the
ultimate accuracy of the entire converter. It is also the comparator drift which has the greatest influence on the
repeatability of the device. A chopper-stabilized comparator provides the most effective method of satisfying all
the converter requirements.
The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed throught
a high gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier
since the drift is a DC component which is not passed by the AC amplifier. This makes the entire AID converter
extremely insensitive to temperature, long term drift and input offset errors.
Figure 4 shows a typical error curve for the KAD0808.

111

w

o

I-- FULL-SCALE

111

ERROR

110

-. J

110

w

8

101

S
'3 100
~

=112 LSB

101

Q

TOTAL
~
UNADJUSTED ~.
ERROR

i

~ 100

011

'3011

~ 010

~ 010

o

INFINITE RESOLUTION
PERFECT CONVERTER

+ 112 LSB

o

001

-1/2 LSB
-QUANTIZATION
ERROR

001

000

V,N
0/8 1/8 2/8 3/8 4/8 5/8 6/8 7/8

V,N AS FRACTION OF FULL·SCALE

Fig. 2 3-Blt AID Transfer Curve

000 " - ' - - - - - - - - - - - - V , N
0/8 1/8 218 3/8 4/8 5/8 618 7/8
V,N AS FRACTION OF FULL-SCALE

Flg_ 3 3-Blt AID Absolute Accuracy Curve

REFERENCE LINE

_

QUAN;~~~~

{IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII111111111111111111111111111111111111111111111111111111111111111111111111

INPUT OV
VOLTAGE

-

FULL
SCALE

Flg_ 4 Typical Error Curve

c8

SAMSUNG SEMICONDUCTOR

553

I

KAD0808IKAD0809

CMOS INTEGRATED CIRCUIT

PIN CONFIGURATION
Dual-In-Line Package
IN2
INl
INO
ADD A
ADD B
ADDC

2-'
OUTPUT
ENABLE

KAD0808
KAD0809

ALE
2-' MSB

2-'
2- 3

2-'
2- 8 LSB
REF(-)

2-'
TOP VIEW

TIMING DIAGRAM
CLOCK

50%

START

ALE

,--,

50%

~

\

5O'lor~

----'

twALE

"
•

-~ ~LE ADDRESS

ADDRESS 5O'~
ts -

ANALOG
INPUT

50%

f--

\
th

V

-

Sl/:..,
LSB

COMPARATOR'
INPUT
(INTERNAL MODE)

I
f--

I

td---j

OUTPUT
ENABLE
EOC

OUTPUT

V

STABLE

/

\

-

tEoe

j

L

/50%
tCON

I

-------:...------.!~!:~!!.:.-----------------_{..._____.JL
r
Fig_ 5

c8

SAMSUNG SEMICONDUCTOR .

554

KAD0808/KAD0809

CMOS INTEGRATED CIRCUIT

TYPICAL PERFORMANCE CHARACTERISTICS
1.5...---,..-----,-,..---,..------..

•.S

~
~

f---f---f--nf--;.t7q£'__j

.f-----f---~~----r---'__j

I-O'51-~';£Hf.L--r-----r------l

°OL---,.~~-~2~~--~3.=75--~

3.75

V.dVl

Fig. 6 Comparator liN

VS

Fig. 7 Multiplexer RON vs VIN (Vee = VAEF = SV)

VIN (Vee = VAEF = SV)

TRI·STATE TEST CIRCUITS AND TIMING DIAGRAMS
Vee

1'1....._ __

Vee
OUTPUT

ENABLE

1--...-----<>

GND--~~'-----

VOH~%
OUTPUT

~

GND------------~

90%
50%
10%

IH'!,

___....J/5O%

IOH,IHO
Vee

Vee
10K

OUTPUT

GND----~-----

ENABLE

vee=5CoH
OUTPUT
VOL

10%

IHO\!

\1..

:50_'%1_ _

Fig. 8

c8

SAMSUNG SEMICONDUCTOR

555

II

KAD0808/KAOoa09

CMOS INTEGRATED CIRCUIT

APPLICATIONS INFORMATION
OPERATION
1.0 Ratiometric Conversion
The KAD0808, KAD0809 is designed as a complete Data Acquisition System (DAS) for ratiometric conversion
systems. In ratiometric systems, the physical variable being measured is expressed as a percentage of full-scale
which is not necessarily related to an absolute standard. The voltage input to the KAD0808 is expressed by the
equation.

V,N

'

=

Ox

V's - Vz Dmax-Dmin
Y'N Input voltage into the KAD0808
V's Full-scale voltage

=
=

Vz = Zero voltage
Ox = Data pOint being measured
Dmax = Maximum data limit
Dmin = Minimum da~a limit

A good example of a ratiometric transducer is a potentiometer used as a position sensor. The position of the wiper
is directly proportional to the output voltage which is a ratio of the full-scale voltage across it. Since the data is
represented as a proportion of full-scale, reference requirements are greatly reduced, eliminating a large source
of error and cost for many applications. A major advantage of the KAD0808. KAD0809 is that the input voltage
range is equal to the supply range so the transducers can be connect!!d directly across the supply and thier
outputs connected directly into the multiplexer inputs, (Figure 9).
Ratiometric transducers such as potentiometers, strain gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however, many types of measurements must be referr!!d to an
absolute standard such as voltage or current. This means a system reference must be used which relates the fullscale voltage to the standard volt. For example, if Vee VAEF 5.12V, then the full-scale range is divided into 256
standard steps. The smallest standard step is a LSB which is then 20mV.

=

=

2.0 Resistor Ladder Limitations
The voltages from the resistor ladder are compared to the selected into 8 times in a conversion. These voltages
are coupled to the comparator via an analog·switch tree which is referenced to the supply. The voltages at the
top, cente'r and bottom of the ladder must be controlled to maintain proper operation.
The top of the ladder, Ref( +), should not be .more positive than th~ supply, and the bottom of the ladder, Ref( -),
should not be more negative than ground. The center of the ladder voltage must also be near the center of the
supply because the analog switch tree changes from N-channel switches to P-channel switches. These limitations
are automatically satisfied in ratiometric systems and can be easily met in ground referenced systems.
Figure 10 shows a ground referenced system with a separate supply and reference. In this system, the supply must
be trimmed to match the reference voltage. For instance, if a 5.12V is used, the supply should be adjusted to the
same voltage within O.1V.

r-----~------~----~~vee

REF(+)

~

.

MSS

-----I------+-------I'n7
QOUT

DIGITAL OUTPUT
PROPORTIONAL
TO ANALOG INPUT

=

=
=

QOUT ...YttL .Ylli..
V AEF Vee
4.5V s,Vcc V AEF s,5.5V
• Ratiometric transducers

Fig_ 9 Ratiometric Conversion System

c8

SAMSUNG SEMICONDUCTOR

556

CMOS INTEGRATED CIRCUIT

KADOS08/KAD0809
APPLICATIONS INFORMATION

(Continued)

The KAD0808 needs less than a milliamp of supply current so developing the supply from the reference is readily
accomplished. In Figure 11 a ground referenced system is shown which generates the supply from the reference.
The buffer shown can be an op amp of sufficient drive to supply the milliamp of supply current and the desired
bus drive, or if a capacitive bus is driven by the outputs a large capacitor will supply the transient supply current
as seen in Figure 12. The KA301A is overcompensated to insure stability when loaded by the 10",F output capacitor.
The top and bottom ladder voltages cannot exceed Vee and ground, respectively, but they can be symmetrically
less than Vee and greater than ground. The center of the ladder voltage should always be near the center of the
supply. Sensitivity of the converter can be increased, (I.e., size of the LSB steps decreased) by using a symmetrical
reference system. In Figure 13, a 2.5V reference is symmetrically centered about Vcd2 since the same current flows
in identical resistors. This system with a 2.5V reference allows the LSB bit to be half the size of a 5V reference system.

I - - - - - - - - - l Vee

II

MSB
~---'-I REF( +)

DIGITAL OUTPUT
REFERENCED
TO GROUND

QOUT

InO
REF(-)

LSB

~
VAEF
4.5V SVee = VAEFS5.5V
QOUT=

L-------I GND
KADOB08

Fig. 10 Ground Referenced Conversion System USing Trimmed Supply

Vee
MSB

1-~>--------,.--1REF( +)

OOUT

In7

DIGITAL OUTPUT
REFERENCE'D
TO GROUND

InO
REF(-)

LSB

L-----------~__1GND

KAD0808

VIN

QOUT = VAEF
4.5V SVCC

=VAEFS5.5V

Fig. 11 Ground Referenced Conversion System with Reference Generating Vee Supply

c8

SAMSUNG SEMICONDUCTOR

557

KAD0808JKAD0809 .

CMOS INTEGRATED CIRCUIT
10-15 Voe
1K

,

\.

Vee
>----,~~--REF( +)

Fig. 12 Typical Reference ,and Supply Circuit
5V

DIGITAL OUTPUT
,PROPORTIONAL
TO ANALOG INPUT
1.25V:sVIN:s3.75V

2.5V REFERENCE

RA=Rs
• Aatiometrlc transducers

Fig. 13 Symmetrically Centered Reference
3.0 Converter Equations
The transition between adjacent codes Nand N + 1 is givn l:1y:

N

1

VIN = ((VREF(+)- VREF(_) [256 + 512' ± VTUEI + VREFH
The center of an output code N is given by:

N"

.

VIN{(VREF(+) - VREF(-~[256' ± VTUEI + VREFI-)
The output code N for an arbitrary input are the Integers within the range:.
N = V VIN ,- V~FH x 256 ± Absolute Accuracy
REF(+)- REF(-)
Where: VIN = Voltage at comparator input
VREF(+) = Voltage at Ref(+)
VREFI-) = Voltage at Ref( -)
VTuE=Total unadjusted error voltage (typically VREF(+)+512)

.c8

SAMSUNG SEMICONDUCTOR

558

KAD0808IKAD0809

CMOS INTEGRATED CIRCUIT

4.0 Analog Comparator Inputs
The dynamic comparator input current is caused by the pariodic switching of on·chip stray capacitances. These
are connected alternately to the output of the resistor ladder/switch tree network and to the comparator input as
part of the operation of the chopper stabilized comparatdr.
The average value oJ the comparator input current varies directly with clock frequency and with VIN as shown in
Figure 6.
If no filter capacitors are used at the analog inputs and the signal source impedances are low, the comparator
input current should not introduced converter errors, as the transient created by the capacitance discharge will
die out before the comparator output is strobed.

If input filter capacitors are desired for noise reduction and signal conditioning they will tend to average o4,t the
dynamic comparator input current. I will then take on the characteristics of a DC bias current whose effect can
be predicted conventionally.

TYPICAL APPLICATION

II

INTERRUPT
eLK
ADDRESS
DEcoDe
(AD4 - AD15)'

VREF(+)

OE
EOC I---~~---INTERRUPT

VREF(-)

START
ALE

2- 1

DB7

2-'
2- 3

DBS

2-'

DB4
DB3

DB5

A KADOBOB 2-'
B KADOB09 2-'

C

DB2

2- 7
2- 8

DBl
DBO

5V SUPPLY

GROUND

J

Vee
GND

MSB

LSB

VINB}
0-5V
ANALOG INPUT
RANGE

V'Nl
•

Addre~s

latches needed for 8085 and SC/MP interfacing the KAD080B to a microprocessor

MICROPROCESSOR INTERFACE TABLE
Processor
8080'
8085
Z..8Q
SC/MP
6800

c8

Read

Write

Interrupt "(Comment)

MEMR
RD
RD
NRDS"
VMA- !Il2-RlW

MEMW
WR
WR
NWDS
VMA-91-RIW

INTR (Thru RST Circuit)
INTR (Thru RST Circuit)
INT (Thru RST Circuit, Mode 0)
SA (Thru Sense A)
IRQA or'i"RQB (Thru PIA)

SAMSUNG SE,..ICONDUCTOR

559

PRELIMINARY

CMOS INTEGRATED CIRCUIT

KAD0820AlB

8·BIT HIGH SPEED j.tP·COMPATIBLE AID
CONVERTER WITH TRACK/HOLD FUNCTION

20 DIP

By using a half-flash conversion technique, the 8-bit
KAD0820A/B CMOS AID offers a 1.51's conversion time
and dissipates only 75mW of power. The half-flash
technique consists of 32 comparators, a most
,significant 4-bit ADC and a least significant 4-bit ADC.
The input to the KAD0820A/B is tracked and held by the
input sampling circuitry eliminating the need for an
extemal sample-and-hold for signals moving at less than
100mV/l's.
For ease of interface to microprocessors, the
KAD0820A/B has been designed to appear as a memory
location or 1/0 port with'out the need for external
interfacing logic.

FEATURES
•
•
•
•
•

Built-In track-and-hold function
No missing codes
No external clocking
Single supply + 5Voc
Easy interface to all microprocessors, or operates
sta~d-alone

• Latched TRI-STATE output
• Logic inputs and outputs meet both CMOS and TTL
voltage level specifications
• Operates ratiometrically or with any reference
ORDERING INFORMATION
value equal to or less than Vcc
• OV to 5V analog input voltage range with single
Device
Package Temperature Range Diff. Nonlinearity
5V supply
KAD0820AIN
:!: 1/2 LSB
• No zero or full·scale adju~t required
20 DIP - 40·C - + 85·C
• Overflow output available for cascading
KAD0820BIN
:!:1 LSB
• 0.3 n standard width 20·pin DIP

BLOCK DIAGRAMS
VREF(+)

OFL

4.BIT OFL
FLASH
ADC
(4 MSBs)

DB?
DB6
DB5,
DB4

VREF(-)

OUTPUT
LATCH
AND
TRI-5TATE
BUFFERS

4'BIT DAC

VREF(+

16
VREF(-)

DB3

4-BIT
FLASt4
ADC
(4 LSBs)

DB2
DB1
DBO

INT

MODE

WR/RDY

CS

Rp

Fig. 1

c8

SAMSUNG SEMICONDUCTOR

560

PRELIMINARY

CMOS INTEGRATED CIRCUIT

KAD0820AlB

ABSOLUTE MAXIMUM RATINGS (Note 1 & 2)
Characteristic

Symbol

Value

Unit

Vee
Po
VI
VI
Topr
T.tg

10
875
-0.2 - Vee+0.2
-0.2 - Vee+0.2
-40 - +85
-65-+150

V
mW
V
V
·C
·C

Supply Voltage
Package Dissipation at Ta= 25·C
Logic Control Inputs
Voltage at Other Inputs and Output
Operating Temperature Range
Storage Temperature Ral)ge

ELECTRICAL CHARACTERISTICS
The following specifications apply for RD mode (pin 7= 0), Vee = + 5V, VREF(+l= +5V, and VREF(-l= GND, Ta=2S·C
unless otherwise specified.
.

Characteristic

Symbol

Test Conditions

Resolution
Total Unadjusted Error
'. (Note 3)
Reference
Resistance

INL

KAD0820A
KAD0820B

RRE~

Min

Typ

Max

Unit

-

8

8

Bits

± 1/2
±1

±1I2
±1

LSB
LSB

1.4

2.3

5.3

KI'l

Maximum VREF(+l
Input Voltage

VREF(+lmax

-

Vee

Vee

V

Minimum VREF(-l
Input Voltage

VREF(-lmln

-

GND

GND

V

Minimum VREF(+l
Input Voltage

VREF(+)mln

-

VREF(-l

VREF(-l

V

Maximum V REFH
Input Voltage

VREF(-lmax

-

VREF(+l

VREF(+l

V

Vee+0.1

V

0.3
-0.3

3
-3

p.A

± 1116

±1/4

LSB

VIN Input
Voltage

VIN

Maximum Analog
Input Leakage Current

IL

Power Supply
Sensitivity

Is

ciS

GND'().1
e5=Vee
VIN = Vee
VIN=GND

-

Vee=5V±5%

-

SAMSUNG SEMICONDUCTOR

-

p.A

561

I

PRELIMINARY

CMOS INTEGRATED CIRCUIT

KAD0820AlB
DC ELECTRICAL CHARACTERISTICS

The following specifications aPply for Vee = 5V, Ta = 25°C unless otherwise specified.
Characteristic

Symbol

Logical "1" Input Voltage

Logical "0" Input Voltage

Min

Typ

Max

CS, WR, RO

2.0

V

3.5

-

Vce

Mode

Vce

V

0.8

V

1.5

V

0.1
0.1
50

1
1
170

/lA
/lA
/lA

0.1

1

!lA

2.4

2.8

V

4.5

4.6

V

0.34

0.4

V

Test Conditions

VINI,)

Vee = 5.25V

VINIO)

Vce=4.75V

CS, WR, RO

0

Mode

0

Logical "1" Input Current

IIN(1)

VINI,) = 5V; CS, RO
VIN(1)=5V; WR
VINI,) = 5V; Mode

Logical "0" Input Current

VINIO)

VINlo) = OV;
Mode

es,

-

-

RO, WR,

Logical "1" Output Voltage

VOUTI')

Vce=4.75V, lOUT = -360/lA;
OBO-OB7, OFL, INT
Vee = 4.75V, louT =' -10/lA;
OBO - OB7, OFL, INT

Logical "0" Output Voltage

VOUTIO)

Vee = 4. 75V, louT = 1.8mA;
OBO - OB7, OFL, INT, ROY

TRI-STATE Output Current

louT

VouT =5V; OBO- OB7, ROY
VOUT=OV; OBO- OB7, ROY

-

ISOURCE

VOUT=OV; OBO-DB7, OFL
INT

ISINK

VOUT = 5V; OBO - DB7, 'OFL,
INT, RDY

Output Source Current
Output Sink Current
Supply Current

0.1
-0.1

1
-1

/lA
/lA

-7.2
-5.3

-12

mA
mA

8.4

14

-

_.

7.5

13

mA

CS=WR=RD=O

Icc

Units

-9

mA

AC ELECTRICAL CHARACTERISTICS The following specifications apply for Vee =5V,
t r =t,=20ns, VREFI +)=5V, VREFI-I=GND and Ta=25°C unless otherwise specified.
Characteristic

Symbol

Test Conditions

Conversion Time for RD Mode

tCAD

Pin 7 = 0, (Figure 2)

Access Time (Delay from Falling
Edge of RD to Output Valid)

tAeeo

Pin 7 = 0, (Figure 2)

Conversion Time for
WR-RD Mode
Write Time

c8

Pin 7 = Vec; tWA = 600ns,
tRD = 600ns; (Figures 3a and 3b)

tWR

Pin 7 = Vee; (Figures 3a and 3b)
(Note 4) See Graph

tRD

Pin 7 = Vce; (Figures 3a and 3b)
(Note 4) See Graph

Min
Max

Read Time

tewR.AD

Min

SAMSUNG SEMICONDUCTOR

Min

Typ

Max

Unit

-

1.6

2.5

/ls

tCRD +20

t~AD + 50

ns

1.52

-

/lS

-

600

ns

50

-

/lS

-

600

ns

-

562

PRELIMINARY

KAD0820AlB

CMOS INTEGRATED CIRCUIT

AC ELECTRICAL CHARACTERISTICS

(Continued) The following specifications apply for
Vcc =5V, t,=t,=20ns, VREF(+)=5V, VREF(_)=OV and·Ta=25°C unless otherwise specified.

Characteristic

Access Time (Delay from Falling
Edge of FID to Output Valid)

Access Time (Delay from Falling
Edge of RD to Output Valid)
Internal Comparison Time
TRI-STATE Control (Delay from.
Rising Edge of RD to Hi-Z State)

Symbol

tACC'

tACC2

Test Conditions

t'H, tOH

-

190

280

ns

210

320

ns

-

70

120

ns

90

150

ns

Pin 7 = Vcc; (Figure 3b and 4)
CL=50pF

-

800

1300

ns

RL=1K, CL=10pF

-

100

200

ns

-

Pin 7=Vcc, tRo>t,; (Figure 3b)
CL= 15pF

Pin 7 = Vcc, CL= 50pF
tRO > t,; (Figure 3b)
tRotl)

ciS

SAMSUNG SEMICONDUCTOR,

Fig. 4 WR·RD Mode (Pin 7 is High)
Stand·Alone Operation

564

PRELIMINARY

KAD0820AlB

CMOS INTEGRATED CIRCUIT

TYPICAL APPLICATIONS
13
8
6

9

CS

VGep2...
0 - - . - - - - r - - - O 5V

RD
ROY
INT
DBO

en

:J

'"

DBl
DB2
DB3

VREF( + 11-'1;;.2- - - - - . - - o 5 V

DB4
DB5

.VREF(_1 11

. DB6
DB7
OFL

GND 10

8·Bit Resolution Configuration

CS

13

WR

Ft>
~

~

BO
Bl
B2

Cs

6 WR

r,;m
S-y
-

2 DBO
3 DB1
4DB2
5 DB3
14DB4
15 DB5
16 DB6

::
B5
B6
B7
B8
OFL

I

Vee 1To5V
VIN

MODE
VREF(+)

7

~
Jo.l

VREF(-) 11
JO.l

17 DB7
lK
18 OFL

.1.--

GND~
~:

5K

~ lK

13

Cs

6 WR

Vee 1fo5V
VIN

..-

-~

J

RD

2 DBO
3 DB1

4 DB2
5 DB3
14 DB4
15 DB5
16 DB6
17 DB7.
18 OFL

MODE r!;o5V
12
VREF(+)

VREF(-)

11

l~

fi7,

GND~

90Bit Resolution Configuration

c8

SAMSUNG SEMICONDUCTOR

565

PRELIMINARY

CMOS INTEGRATED CIRCUIT

KAD0820AlB
TYPICAL APPLICATIONS

(Continued)

25K

AM
CH1

-15V
40K

DBO TO DB?

Telecom AID Converter

Multiple Input Channels
1.2~s

VIN ..,

r-

(OVTO 5V)U

10 GND
13

WR

2

LSB 12

CS

1-'1-=-3_ _---1~-15V

JO.1~F

11
10

F---~---1~-

-15V

11 VREF(-)

KAD0820A
+5V

Vee
? MODE
12 VREF(+)

15

8

KDA0800

16
17

/----MIr--5V .
6

18 MSB 5
4

+15V

OV-5V

-15V

1.82K 1%

Fast Infinite Sample-and-Hold

c8

SAMSUNG SEMICOND~croA

566

db

ic:
en

~

Digital Waveform Recorder

."
A TO D
CONVERTERS

MEMORY

~

~

ADDRESS
COUNTERS

CONTROL LOGIC

~

i

~

KS74
1A HCT393

z

~

r-

l>

."
."

C)

r-

en

m

~

C

I
aJ

£

~

8
z

(5

c

;~~

c:

a

;, KS74

:a

k

I

HCT393

z

en
CS
EWR1
EWR2
RD1

RD, WR

00

;:l.
3"

c

CD

-9:

ERD1
RD2

CS ----t1l'~7AU,...T'l'7A

L- J!......... :'.!~. .::_I

T

ERD2

WR

TRIGGER LEVEL

5V

~~
oPl
cn~
-;e
Z;ti
-I~

o-M"'''H.~~~~~-----'

CLOCK INPUT (te)
(SAMPLING FREQUENCY = tcl3)

m""(

-1.3M samples/sec
e4K memory

G')

~

m
c
Q

~

c:

g:

=i

-..j

•

KS7126

CMOS INTEGRATED CIRCUIT

3 112 DIGIT AID CONVERTER

40 DIP ,

The single chip CMOS KS7126 incorporates all the active devices for a
3 112 digit analog-to-digital converter tadirectly drive an LCD display. The
internal oscillator, voltage reference and display segmentlbackplane
drivers simplify system integration, reduce board space requirements
and lower total cost. A low cost, high resolution-O.05%-indicating meter
requires only II display, four resistors, four capacitors and 9V battery.
The KS7126 dual slope conversion technique rejects interference signal
when the integration time is set to a multiple of the interference sighal
period. This is especially useful in industrial measurement environments
where SO, 60 and 40Hz line frequency signals are present. With an autozero error less than 10I'v, zero driflless than 1I'VJOC, input bias current
of 10pA max and rollOver error of less than one count, the KS7126 brings
exceptional value to the portable battery powered field.
In addition, the differential input and reference allows the measurement
on load cells, strain gauges and other bridge type transducers. The low '
power KS7126 can be used as a plug-in replacement for existing 7106
based systems by changing only the values of seven passive componel1t s.

FEATURES

ORDERING INFORMATION

•
•
•
•
•
•
•
•
•
•

Long Battery Life: 800 Hours TYpical
Auto-Zero Cycle
Guaranteed Zero Reading With Zero Input'
Low Noise: 151'Vp-p
High Resolution (0.05%) and Wide Dynamic Range (72dB)
LoW Input Leakage Current: 1pA TYpical, 10pA Maximum
Direct LCD Display Drive-No External Components
Precision Null Detection With True Polarity at Zero
High Impedance Differential Input
Convenient 9V Battery Operation With Low
Power Dlsslpatiom 500/lW TYpical, 900l'W Maximum
• Internal Clock Circuit
• Drop-In Replacement for TSC7126, ICL7126

Temperature Range

0- + 70·C

TYPICAL APPLICATIONS
• Thermometry
• Bridge Readouts (Strain Gauges, Load Cells, Null Detectors)
• Digital Meters
- Voltage/CurrentlOhmslPower
-pH
- Capacitancellnductance'
- Fluidlflow RatelViscosity/Level

c8

SAMSUNG SEMICONDUCTOR

•
•
•
•
•
•

Digital Scales
LVDT Indicators
Portable Instrumentation
Power Supply Readouts
Process Monitors
Photometers

568

KS7126

C.MOS INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Char.acterlstlc

Symbol

value

Unit

Vee
V,N
VREF
VCl
Pd
T,

15
Vee-VEE
Vee-VEE
Test-Vee
800
300

V
V
V
V
mW
°C
°C
.oC

Supply Voltage
Analog Input Voltage (Either Input) (1)
Reference Input Voltage (Either Input)
Clock Input
.
Power Dissipation
Lead Temperature (Soldering, 60 Sec)
Operating Temperature
Storage Temperature

0~+70

Topr

Tstg

-65-+160

I

ELECTRICAL CHARACTERISTICS
Characteristic

Symbol

Test Conditons
V,N=O.OV
Full scale = 200.0mV

-

V,N = 0, 0·C

I
u.

+u.

a:

a:
0

W

>

W

I

t:;

a:
0

g~

<:0
ZO
<0

+
z

:>

I

z

:>

.it

3 >'""

f-

W

:>

>

z

w

."

w

I-~I

1
& 8

:l

'"

C)

z

0.
III

21

:30.

'"~

KS7126

a
~

f1.

aJ

~

i
_-----'-___ ., __------'--_.,,~
8'
~

c8

SAMSUNG SEMICONDUCTOR

-

~

570

CMOS INTEGRATED CIRCUIT

KS7126
PIN DESCRIPTION
Pin Number
1

c8

Name
Vee

Description
Positive supply voltage.

2

D,

Activates the D section of the units display.

3

C,

Activates the C section of the units display.

4

B,

Activates the B section of the units display.

5

A,

Activates the A section of the units display.

6

F,

Activates the F section of the units display. '

7

G,

Activates the G section of the units display.

8

E,

Activates the E section of the units display.

9

D2

Activates the D section olthe tens display.

10

C2

Actatives the C section of the tens display.

11

B2

Activates the B section of the tens display.

12

A2

Activates the A section of the tens display.
Activates the F section of the tens display.

13

F2

14

E2

Activates the E section of the tens display.

15

D3

Activates the D section of the hundreds display.

16

B3

Activates the B section of the hundreds display.

17

F3

Activates the F section of the hundreds display.
Activates the E section of the hundreds display.

18

E3

19

AB.

Activates both halves of the 1 in the thousands display.

20

POL

Activates the negative polarity display.

21

BP

Backplane drive output

22

Go

Activates the G section of the hundreds display.

23

Aa

Activates the A section of the hundreds display.

24

C3

Activates the C section olthe hundreds display.

25

G2

Activates the G section of the tens display.

26

VEE

27

V'NT

28

V euFF

29

CAZ

II

Negative power supply voltage.
The integrating capacitor should be selected to give maximum voltage swing
that ensures component tolerance build up will not allow the integrator output
to saturate. When analog common is used as a reference and the conversion rate is 3 reading per second, a 0.047/LF capacitor may be used.
The capacitor must have a low dielectric constant to prevent roll-over errors.
See INTEGRATING CAPACITOR section for additional details.
Integration resistor connection. Use a 180KO fr a 200mV full-scale
range and a 1.8MO for"2V full-scale range.
The size of the auto-zero capacitor influences the system noise. Use a O.33/LF
capacitor for a 200mV full-scale, and 0.033/LF capacitor for a 2V full-scale.
See paragraph on AUTO-ZERO CAPACITOR for more details.

SAMSUNG SEMICONDUCTOR

571

KS7126

CMOS INTEGRATED CIRCUIT

PIN DESCRIPTION (Conti~ued)
Pin Number

Name

Description

30

V 1N -

The low input is connected to this pin.

31

V1N +

The high input signal is connected to this pin.

32

ANALOG
COMMON

This pin is primarily used to set the analog common-mode voltage for bat. tery operation or in sytem where the input signal is referenced to the poWer
supply. See paragraph for ANALOG COMMON for more details.
It also acts as a reference voltage source.
33

See pin 34

CAEF -

A 0.1pF-capacitor is used in most applications. If a large common mode vol34

tage exists (for example the V 1N pin is not at analog common), and

C AEF +

a 200mV scale is used, a 1.0"F is recommended and will hold the rollover
error to 0.5 COunt. .

35

See pin 36.

V AEF -

The analOg input required to 'generate a full-scale output (1.999 counts).,
36

Place 100mV between pins 35 and 36 for 199.9mV full-scale. Place 1.000 volt

V AEF +

between pins 35 and 36 for 2V full-scale. See paragraph on REFERENCE
VOLTAGE.
lamp test. When pulled high (to Vee) all segments will be turned ON and the

37

display should read -18~8. It may also be used as a negative supply for ex-

TEST

ternally generated decimal points. See paragraph under TEST for additional
informatiOn.
38

OSCa

See pin 40.

39

OSC.

See pin 40.
Pins 40, 39, 38 make up the oscillator section. For a 48KHz clock (3 read-

40

ings per second) connect pin 40 the junction of a 180KO resistor an

OSC,

a 50pF capaCitor. The 180K resistor is tied to pin 39 an the 50pF capaCitor

i

c8

SAMSUNG

is tied to pin 38.

SEMICONDU~OR

572

KS7126

CMOS INTEGRATED CIRCUIT

DETAILED DESCRIPTION
ANALOG SECTION
Fig. 3 shows the Block Diagram of the Analog Section for the KS7126. Each measurement cycle is divided into three phases.
They are (1) Auto-zero (A-Z), (2) Signal integrate (I NT) and (3) De-Integrate (DE).

TO DIGITAL SECTION

I

Fig. 3 Analog Section of KS7126

1_ Auto-zero phase
During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to
analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed
around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 101'V.

2. Signal integrate phase
During signal integrate, the auto-zero loop is opened. the internal short is removed, and the internal input high and low
are connected to the external pins. The converter then integrates the differential voltage between IN + and IN - for a fixed
time. This differential voltage can be within a wide common mode range; within one Volt of either supply. If, on the other hand,
the input signal has no return with respect to the converter power supply, IN- can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined.

3. De-integrate phase
. The final phase is de-integrate, or reference integrate: Input low is internally connected to analog COMMON and input high
is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be
connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return
to zero is proportional to the input signal. Specifically the digital reading displayed is 1000( ~ )
.
V REF

Differential Input
The input can accept differential voltages anywhere within the common mode range of the input amplifier; or specifically
from 0.5 Volts below the positive supply to 1.0 Volt above the negative supply. In this range the system has a CMRR of 86dB
typical. However, since the integrator also swings with the common ijlode voltage, care must be exercised to assure the integrator output does not saturate. A worst case condition would be large positive common-mode voltage with a near fullscale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has
been used up by the positive common mode voltage. For these critical applications the integrator swing can be reduced to
less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing within 0.3 Volts
of either supply without loss of linearity.
' .

a

c8

SAMSUNG SEMICONDUCTOR

573

KS7126

CMOS INTEGRATED CIRCUIT

Differential R.rence
The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of
common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on
its modes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called
up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal.
This difference in reference for (+) or (-) input voltage will give a,roll-over error How.ever, by selecting the reference capacitor large enpugh in comparision to the stray capacitance, this error can be held to less than 0.5 count for the worst case condition
(See component Value Section)

Vee
REF +

,

6.8 VOLT
ZENER

REF RS7126

vee

27KIl
200KO

KS7126
REF+

1'.2 REFERENCE

REFCOMMON

Fig. 4: Using. an External Reference
vee

1 - --l

vee

I

I
I

I
I

KS7126
BP 21

Vee

I
I
I
I

I
I

vee

TEST
37

KS7126
IDLeO
DECIMAL
POINT
GND
32

TEST 57

TO LLD
DECIMAL
POINT

DECIMAL
POINT
SELECT

L__

__J
GND

L - - - - - - - - o ~~~lANE

Figure 5: Simple Inverter for Fixed Decimal Point

Figure 6: ExclusiveOR Gate for Decimal Point

Analog Common
. This pin is included primarily to set the common mode voltage for battery operation or for any system where Ine input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8 Volts more negative
than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, the analog
COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener
to regulate ( < 7V), the COMMON voltage will have a low voltage coefficient (0.001%1%), low output impedance (=150),and
a temperature coefficient typically less than 80 ppml"C.
The limitations of the on-Chip reference should be also recognized, however. The reference temperature coefficient (TC)
can cause some degradation in performance. Temperature changes of 2 to SOC, typical for instruments, can give a scale factor
error of a count or more. Also the common voltage will have a poor voltage coefficient when the total supply voltage is less
than that which will cause the zener to regulate « 7V), These problems are eliminated if an external reference is used, as
shown in Fig. 4.
Analog COMMON Is also used as the Input low return during auto·zero and de·integrate. If IN- is different from analog
COMMON, a common mode voltage exists in the System and is taken care of by the excellent CMRR of the converter. However,
in some appncations IN - will be set at a fixed known voltage (power supply common for instance). In this application, analog
COMMON should be tied to the same point, thus remOVing the common mode voltage from the converter. The same holds
true for the reference voltage. If reference can be conveniently referenced to analog COMMON, it should be since this removes
tlie common mode voltage from the reference system.

c8SAMSUNG SEMICONDUCTOR

574

KS7126

CMOS INTEGRATED CIRCUIT

Within the IC, analog COMMON is tied to an N channel FET that can sink 100pA or more of current to hold the voltage
2.8 'volts below the positive supply (when a load is trying to pull the common line positive). However, there is only 1pA of source
current .. so COMMON may easily be tied to a more negative vQltage thus overriding the internal reference.

Test
The TEST pin serves two functions. It is coupled to the internally generated digital supply through a 500n resistor. Thus
it can be used as the negative supply for externally generated segment drivers such as decimal paints or any other presentation the user may want to include on the LCD display Fig. 5 and Fig. 6 show such an application. No more than a 1mA load
should be applied.
The second function is a "lamp test". When TEST is pulled high (to Vecl all segments will be turned on and the display
should read - 1888. The TEST pin will sink about 10mA under these conditions.
CAUTION: In the lamp test mode, the segments have a constant D-C voltage (no square-wave) and may burn the LCD
display if left in this mode for extended periods.

DIGITAL SECTION
Fig. 7 shows the digital section for the KS7126. An internal digital ground is generated from a 6 volt zener diode and a large
P channel source follower. This supply is made stiff to absorb the relative large capacitive current when the back plane (BP)
voltage is switched. The BP !requency is the clock frequency divided by 800. For three readings/second this is a 60Hz square
wave with a nominal amplitude of 5 volts. The segments are driven at the same frequency and amplitude and are in phase
with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. The polarity
indication is "ON" for negative analog inputs. If IN - and IN + are reversed, this indication can be reversed also, if desired.

--+---~---+--~~--~------------4-----~--~~rOTEST

*Three Inverters.
One Inverter shown for clanty.

------......-.1----0 VEE
OSCl

Fig. 7: Digital Section

c8

SAMSUNG SEMICONDUCTOR

575

II

CMOS INTEGRATED CIRCUIT

KS7126.
System Timing
Fig.
1:
2.
3.

8 shows the clocking arrangement used in the KS7126. Three basic clocking arrangements can be used.
An external oscillator connected to pin 40
A crystal between pins 39 and 40.
An R-C oscillator using all three pins

EXTERNAL
OSCILLATOR

Fig. 8: Clock Circuits
The oscillator frequency is divided by four before it clocks the decade counts. It is then futher divided to form the three
convert - cycle phases. These are signal iritegrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto - zero
(1000 to 3000 counts): For signals less than full scale, auto - zero gets the unused portion of reference de-integrate. This
makes a complete measure cycle of 4,000 (1 ,600 clock pulses) independent of input voltage. For three readings/second, an .
oscillator frequency of 48 KHz would be used.
To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequency .
of 60KHz, 48KHz, 33l bKHz, ·etc. should be selected. For 50Hz rejection, oscillator frequencies of 66lJ:,KHz, 50KHz, 40KHz,
etc. would be suitable. Note that 40KHz (2.5 readings/second) will reject both 50 and 60Hz (also 400 and 440Hz)

COMPONENT VALUE SELECTION
1. Integrating Resistor
Both the buffer amplifier and the integrator have a class A output Stage with 6 pA of quiescent c~rrent. They can supply -1 pA
of drive current with negligible non-linearity. The integrating resistor should be large enough to remain in this very linear region
over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2 Volt
full scale, 1.8MO is near optimum and similarly 180KO for.a 200.0mV scale.

2. Integrating Capacitor
The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance build-up will not
saturate the integral swing (approx. 0.3 Volt from either supply). When the analog COMMON is used as a reference, a nominal ±2 Volt full scale integrator swing is fine.For three readings/second (48KHz clock) nominal values for C'NT are 0.047!,F,
.' for 1/sec (16KHz) 0.15!,F of course, it different oscillator frequencies are used, these values should be changed in inverse
proportion to maintain the same output swing.
The integrating capacitor should have low dielectric absorption to prevent roll-over-errors. While other types may be adeqU!'te for this application, polypropylene capaCitors give undetectable errors at reasonable cost. At three readings/sec., a
7500 resistor should be placed in series with the integrating capaCitor, to compensate for comparator delay.

3. Auto·Zero Capacitor
The size of the auto-zero capaCitor has some influence on the noise of the system. For 200mV full scale where noise is
very important, a 0.32!,F capaCitor is recommended. On the 2 Volt scale, a 0.033!,F capacitor increases the speed of recovery from overload and is adequate for nOise on this scale.

4. Reference Capacitor
. A 0.1 ~ capacitor gives good results in most applications. However, where a large common mode voltage exists (i .e. the
REF - pin is not analog COMMON) and a 200mV scale is used, large value is required to prevent roll-over error. Generally 1.0!,F will hold the roll-over error to 0.5 count in this instance.

a

5. Oscillator Components
For all ranges of frequency a 50pF capacitor is recommended and the resistor is selected from the approximate equation f '" ~5 For 48KHz clock (3 readings/second) R=18KO
RC

c8

SAMSUNG SEMICONDUCTOR

576

KS7126

CMOS INTEGRATED CIRCUIT

TYPICAL APPLICATIONS
Ve_c______________~~--~----~----------------------------,
Scaie factor adjust
(Vref =100mV for fIC to RMS)
OSC,
OSC2
flClIN

KS7126
2.2MO

CREFANALOG COMMON
(OR COMMON)
VIN+
VIN-

CAZ
VeUFF

I

VINT

G,
Co

Go

Figure 9: AC to DC Converter with KS7126. Test is Used as a Common
Mode Reference' Level to Ensure Compatibility with Most Op·Amps.

To pin 1
Topinll
40

..

40

1801<0

Set Vref= 1.000V

'.r'
50pF
~

Do·lp1'

Vee
240KO

.01p1'

lMO

. 22.FII

... J.·...1...8MO
:;

•

~

F=
F=

\.1
lOKO

liMO

...

lMO

:p.o.,p1'!
KS7126

,

IN

..O~3,F

'i,'

0.047~F

O.lp1'

~~

+5V
6.8V

~

}TODISPLAY

}

IN

180KO

."

VEE

21

Set Vref=100.0mV

,i
50~F

F=

250Kll

KS7126

~ 750!l.

/

-5V

TO DISPLAY

f=
-

TO BACKlpLANE

21

f-----

TO BACKPLANE

Figure 11: KS7126 with Zener Diode Reference:
Figure 10: Recommended Values for2.000V Full-Scale,
Three Readings Per Second .

.c8

SAMSUNG SEMICONDUCTOR

577

KS7126

..

CMOS INTEGRATED CIRCUIT

Vee

To pi" 1

Vee
40

Fl

Sell!ref-l00.0mV

:~

50pF
24aKIl

po.l"F

+

KS7126

LJ_='""""""---<>--_-=+=c.:.O"'l"F=--_ _ _+-Q IN

'T

27K(J

--.o'I l2V

-

lMO

.01"F

-III

KS7126

IN

O.33.F..

...

d'

-=-9V

F
F

1=
21

Figure 12: KS7126 Using the Internal Reference. 200.0mV
Full-Scale, Three Readings Per Second, Floating Supply
Voltage (9V Battery).

IooKII
20K!l~r

}TODISPLA:
-

TO BACK PLANE

Figure 13: KS7126 Operated From Single +5V
Supply. An External Reference Must Be Used.

To pin 1

Vce--------------~

40
40
50pF

560KIl
l--_ _

~_

V
ee

TO pi" 1

SetV""-100.0mV

~---~~~~~~~~~Vec

TSC9491CJ

KSl726
KS7126
D-----'-=='---'-------~VEE

"Values depend on clock frqeucny. See figure 10,'12, 15.

Figure 14:. KS7126 Measuring Ratiometric Values of Quad
Load Cell. The Resistor Values Within the Bridge are
Determined by the Desired Sensitivity.

.c8

SAMSUNG SEMICONDUCTOR

Figure 15: KS7126 with an External Band-Gap
Reference (1.2V Typ) IN - is tied to Common.
Values Shown are for One Reading Per Second .

578

CMOS INTEGRATED CIRCUIT

KS7126

To pin 1
Vee--------------------____,

40
D----~I------' Scale factor adjust

SOpF 100KO/

KS7126

1MU

LJ------+-~--t-+\-I.----~

To logic
GND

Silicon NPN
MPS37040r
similar

o Rang<
U Range

1+~---Cl(1t:t-g20

KS74HCTL10
KS74HCTLS266

Figure 16: KS7126 Used as a Digital Centigrade
Thermometer. A Silicon Diode-Connected Transistor Has
a Temperature Coefficient of About 2mV/"C.

Figure 17: Circuit for Developing Underrange and Overrange
Signals from KS7126 Outputs.

To pin 1

Vee
40

S60KO
Set V,.f 1,OOOV

II

""SOpF

=0.1,,1'

'"

Vee

2S0KO

240KIl
.01,,1'

KS71 26

:;p

1MO
IN.

O.022'F-t~
1.SMU
0.1S.F

.} 10 DISPLAY

21""-

10 BACK PLANE

Figure 18: Recommended Component Values for 2.00V Full-Scale, One Reading Per Second.
·Values depend on clock frequency. See Figure 10, 12,15

c8

SAMSUNG SEMICONDUCTOR

579

I

KDAOSOO/KDAOS01/KDA0802

LINEAR INTEGRATED CIRCUIT

a·BIT DIA CONVERTER

16 DIP

The KDA0800 series are monolithic 8-bit high-speed current-output
digital-to-analog converters (DAC) featuring typical settling times of
100ns. When used as a multiplying DAC, monotonic performance over
a 40 to 1 reference current range is possible. The KDA0800 series also
features high compliance complementary current outputs to allow
differential output voltages of 20 Vp•p with simple resistor loads. the
reference-to-full-scale current matching of better than ± 1 LSB eliminates
the need for full-scale trims in most applications while the nonlinearities
of better than ± 0.1 % over temperature minimizes system error
accumulations.
The' noise immune inputs of the KDA,0800 series will accept TTL levels
with the logic threshold pin, VLC , potential allow direct interface to all
logic families. The performance and characteristics of the device are
essentially unchanged over the full ± 4.5V to ± 18V power supply range;
power dissipation is only 33mW with ± 5V supplies and is independent
of the logic input states.

ORDERING INFORMATION

FEATURES
•
•
•
•
•
•
•
•
•
•
•
•

Fast settling output time: 100ns
Full 'scale error: ± 1 LSB
Nonlinearity over'temperature: ± 0.1 %
Full scale current drift: ± 10 ppm/oC
High output compliance: -10V to + 18V
Complementary current outputs
Interface directly with TTL, CMOS, PMOS
and others
2 quadrant wide range multiplying capability
Wide power supply range: ± 4_5V to ± 18V
Low power consumption: 33mW at ± 5V
Low cost
Standard 16 DIP package

Device

Package Temperature Range

KDA0800CN

NonUnearity
±0.19%FS

KDA0801CN

16'DIP

0- +,70·C

KDA0802CN

±0.39%FS
±0.1%FS

BLOCK DIAGRAM
v+

COMP

,c8

VLC

B1 MSB

B2

B3

B4

85

B6

87

88 LS8

v-

SAMSUNG SEMICONDUCTOR

580

KDA0800/KDA0801fKDA0802

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Supply Voltage
Power Dissipation
Reference Input Differential Voltage (V·14 to V15)
Reference Input Common-Mode Range (V14, V15)
Reference Input Current
Logic Inputs
Operating Temperature
Storage Temperature

Vcc
Po
Y,N
Y'N
Ire'
Y'N
Topr
Tstg

± 18V or 36V
500mW.
V_ - V+
V_ - V+
5mA
V_ - V_+36V
DoC _ + 70°C
- 65°C - + 150°C

V
mW
V
V
rnA
V
°C
°C

ELECTRICAL CHARACTERISTICS
(Vs = ± 15V, Ire' = 2mA, Tm,nsTasTma>< unless otherwise specified. Output characteristics' refer to both lOUT and lOUT')

Characteristic

Symbol

Test Conditions

KDA0800
Min

Typ

Max

Unit

Resolution

8

8

8

Bits

Monotonicity .

8

8

8

Bits

Nonlinearity

Settling Time

ts

Propagation Delay
Each Bit
All Bits Switched

tPLH, tpHL

Full Scale Tempco

TCI Fs

KDA0802
KDA0800
KDA0801

-

-

±0.1
±0.19
±0.39

%FS

To ± 1/2 LSB, all bits switched
"ON" or "OFF", Ta=25°C

-

100

150

ns

Ta=25°C

-

35
35

60
60

ns
ns

±10

±50

ppm/DC

18

V

-

Output Voltage Compliance

Voc

Full scale current change
<1/2 LSB, ROUT >20MO Typ

Full Scale Current

IFS4

Vre,=10V, R14=5KO
R15=5KO, Ta=25°C

1.94

Full Scale Symmetry

IFss

IFs4 -IFs2

-

±1

±8.0

Zero Scale Current

Izs

-

0.2

2.0

p.A

0
0

2.0
2.0

2.1
4.2

rnA
rnA

0
2.0

-

0.8
Vcc

V
V

-2.0
0.002

-10
10

p.A
p.A

18

V

Output Current Range

IFsR

Logic Input Levels
Logic "0"
l,ogic "1"

V,L
V,H

Logic Input Current
Logic "0"
Logic "1"

I'L
I'H

Logic Input Swing
Logic Threshold Range

V's
VTHR

V- = -5V
V- = -8V to -18V
VLC=OV

Power Supply Sensitivity

1.99

2.04

rnA
p.A

-

V- = -15V

-10

Vs=±15V

-10

-

13.5

V

-

-1.0

p.A

p.A

dl/dt
PSSI Fs +

-

VLC=OV
-10VSV,N S +0.8V
2VSV,NS+18V

Reference Bias Current 1,5
Reference Input Slew Rate

-10

4.0
4.5VSV+ S18V

ciS SAMSUNG SEMICONDUCTOR

-

8.0

-

mA/p.s

0.0001

0.01

%/%

581

I

KDA0800/KDA0801/KDA0802

CMOS INTEGRATED CIRCUIT

ELECTRICAL CHARACTERISTICS
Characteristic

Symbol

PSSIFs -

(Continued)

Test Conditions
-4.5VsV-s18V
Ire. = 1rnA
.Vs= ±5V, Ire.=1rnA

1+
1Vs =5V, -15V, l,e.=2rnA

Vs= ±15V, l,e.=2rnA

1+
1Power Dissipation

±5V,lre.=1rnA
5V, -15V, Ire .=2rnA
± 15V, I,e' = 2rnA

Po

Unit

Typ.

Max

-

0.0001

0.01

%/%

2.3
-4.3

3.8
-5.8

rnA
rnA

-

2.4
-6.4

3.8
-7.8

rnA
rnA

-

2.5
-6.5

3.8
-7.8

rnA
rnA

-

33
108
135

48
136
'174

rnW
rnW
rnW

-

-

1+
1-

Power Supply Current .

KDA0800
Min

TYPICAL APPLICATIONS
MSS

LSS

B1 B2B3B4B5B6B7B8
Iref

10

+Vref --+Vref

LT----:r--T--i-:r==:y 10

+V

+ Vre, 255
IFs=~X256
10 + 1';;= IFs for all
logic states
For fixed reference, TTL operation,
typical values are:
Vre.= 10V
Rre.=5KO
R15= R,e'
Cc=O.Q1I'F
VLC=OV (Ground)

Fig. 1 Basic Positive Reference Operation

+ l,e.=2mA,--_ _ _"""""
KDA0800

_ - V,e' 255
IFs = ~ x 256

Fig. 2 Recommended Full Scale

c8

Adjustm~nt

SAMSUNG SEMICONDUCTOR

Circuit

Note: Rre; sets IFs: R15 is
for bias current cancellation

Fig. 3 Basic Negative Reference Operation

582

KDA0800/KDA0801/KDA0802
TYPICAL APPLICATIONS

LINEAR INTEGRATED CIRCUIT

(Continued).
MSB
LSB
B1B2B3B4B5B6B7B8

Eo

+ Ire f=2mA

B1 B2 B3 B4 B5 B6 B7 B8

10 mA

rc; mA

Eo

Eo

Full Scale
Full Scale - LSB
Half Scale + LSB

1
1
1

1
1
0

1
1
0

1
1
0

1
1
0

1
1
0

1
1
0

1
0
1

1.992
1.984
1.008

0.000
0.008
0.984

-9.960
-9.920
-5.040

0.000
-0.040
-4.920

Half Scale
Half Scale - LSB
Zero Scale + LSB
Zero Scale

1
0
0
O·

0
1
0
0

0
1
0
0

0
1
0
0

0
1
0
0

0
1
0
0

0
1
0
0

0
1
1
0

1.000
0.992
0.008
0.000

0.992
1.000
1.984
1.992

-5.000
-4.960
-0.040
0.000

-4.960
-5.000
-9.920
-9.960

I

Fig. 4 Basic Unipolar Negative Operation
10K

Iref

=2mAO------ 14

KDA0800

--.-

·I~r
-

10 2

Eo

10K

B1 B2 B3 B4 B5 B6 B7 B8
Pos. Full Scale
Pos. Full Scale - LSB
Zero Scale + LSB
Zero Scale
Zerc. Scale - LSB
Neg. Full Scale + LSB
Neg. Full Scale

1
1
0
0
1
0
0

1
1
1
1
0
0
0

1
1
0
0
1
0
0

1
1
0
0
1
0
0

1
1
0
0
1
0
0

1
1
0
0
1
0
0

1
1
0
0
1
0
0

1
0
1
0
1
1
0

Eo

Eo

-9.920
-9.840
-0.080
0.000
+0.080
+9.920
+ 10.000

+ 10.000
+9.920
+0.160
+0.080
0.000
-9.840
-9.920

Fig. 5 Basic Diploar Output Operation
RL'5K

104
KDA0800

102
If RL = At: within ± 0.05%, output is symmetrical
about ground
B1 B2 B3 B4 B5 B6 B7 B8
Pos. Full Scale
Pos. Full Scale - LSB
( + ) Zero Scale
( - ) Zero Scale
Neg. Full Scale + LSB
Neg. Full Scale

1
1
1
0
0
0

1
1
0
1
0
,0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
1
0
1
0
0

1
0
0
1
1
0

Eo
+9.920
+9.840
+0.04Q
-0.040
-9.840
-9.920

Fig. 6 Symmetrical Offset Binary Operation

c8

SAMSUNG SEMICONDUCTOR

583

KDAOSOO/KDA0801/KDA0802
TYPICAL APPLICATIONS

LINEAR INTEGRATED CIRCUIT

(Continued)
RL

KDA0800
KDA0800

For complementary output
(operation as negative logic DAC), connect
inverting input of op amp to r;; (pin 2),
connect 10 (pin 4) to ground.
Fig. 7 Positive Low Impedance Output Operation

VTH = VLe + 1.4V
15V CMOS, HTL, HNIL
VTH=7.6V
TTL, OTL

I

VTH":l.4V

I
I

12V TO 15V
}

15V

,ffiK

I

11:
9.1K

VLe

For complementary output
(operation as a negative logic DAC) connect
non-inverting input of op am to 10 (pin 2);
connect 10 (pin 2); connect 10 (pin 4) to ground.
Fig •. 8 Negative Low Impedance Output Operation

I

~
II

vLel

J l .
I

I 02V
,IZEN'ER

O.2K

o.,UF

--- --+-- -- ___ ~-----.L-_-_

5VeMOs
V1H =2.5V

I
I

I

10VeMos
VTH =5V

'I

i ~'0V i

KDA0800

VLe:

I

. I c:

I~
10;

6.2KO
VLe

1.0KEL,L
VTH = -1.29V

Typical values: RIN = 5K, + VIN = 10V

I
I,
I

1N4148

JO.'~F II

1KIJ
I
I
I
I
Do not exceed negative logic input range of DAC.
Fig. 9 Interfacing with Various Logic Families

(a)

lret~peak

negative swing of liN

, Fig. 10 Pulsed Reference Operation
(b)

+ Vral must be

above peak positive swing of VIN

Vref

j

Rrel

Irel

o--#W~--i

14
KDA0800

KDA0800

o--.,.,.,~-t'5
'=:-_ _ _ _ _..J Rrel=R,5
- - HIGH INPUT
IMPEDANC~

Fig. 11. Accommodating Bipdlar References

c8

SAMSUNG SEMICONDUCTOR

584

KDAOBOO/KDA0801/KDA0802
TYPICAL APPLICATIONS

CMOS INTEGRATED CIRCUIT

(Continued)

FO'R TURN "ON", VL = 2.7V VL
FOR TURN "OFF", VL=0.7V

SV

-C

0 .4V

VOUT
OV
1 x PROBE rOY
.....L....,-0.4V

KDAoaoo

R1S

;;w.

-1SV
TO D.U.T.

15

13

II
-1SV

Fig. 12 Settling Time Measurement
rSV

OV

.....J

STOP
CONVERSION

FREE RUN

SV

o-__~--,-16=-t
KS2SC02

°

.----+--'-1 GNDQ1

D ~------~-------------,

Q2Q3Q4QSQ6Q7

3 4 S 6 11 12 1314
LSBo---~

1SV

1SV
a·BIT DIGITAL
WORD

SV

; - - _ - - 0 ANALOG
INPUT

MSBo----r~+-+-r-~~

12 11 10 9

a 7 6 S

~R,,11'f__1'-l4 LSB B7 B6 BS B4 B3 B2 MSB _,,2=------<>---+-+-----'

.--_...-_ _ _
VROE_F

VR+

2.SK

KDAOSOO
R2

1S

100K

-1SV

Note. For 1 P.s conve'rsion time with a·bit resolution and 7·bit accuracy,
an KA361 comparator replaces the KA319 and the reference
current is doubled by reducing R1, R2 and R3 to 2.5KO and R4 to 2MO .
. Fig. 13 A Complete 2 p.S Conversion Time, 8·Bit AID Converter

c8

SAMSUNG SEMICOND.UCTOR

585

KS25C02lKS25C03/KS25C04

CMOS INTEGRATED CIRCUIT

8-81T AND 12·81T CMOS SUCCESSIVE
APPROXIMATION REGISTERS

18 DIP

These are a-bit and 12-bit CMOS registers designed for
use in successive approximati9n AID converters. They
contain all the logic and control circuits necessary in
combination with the AID converter to perform
successive approximation analog-to-digital conversions.
The KS25C02 has a bits with serial capability and is not
expandable. The KS25C03 has a bits and is expandable
without serial capability. The KS25C04 has 12 bits with
serial capability and expandibility.
Fabricated using a 2,..m, dual-layer metal CMOS process,
these parts deliver speeds and drive capability
equivalent to their TTL counterparts and yet maintain
CMOS power levels. The input and output voltage levels
allow direct interface with TTL, NMOS and CMOS
devices without any external components.
All inputs and outputs are protected from damage due
to static discharge by internal diode clamps to Vee and
ground.

FEATURES
• Complete logic for successive approximation AID
converters
• 8-bit and 12-blt registers
• Capable of short cycle or expanded operation
• Continuous or start-stop operation
• Compatible with DIA converters using any logic
code

ORDERING INFORMATION
Package Temperature Range

Device
KS25C021N

16 DIP

KS25C031N

16 DIP

KS25C041N

24SDIP

Registers
4 bit

- 40·C -

+ 85·C

a bit
12 bit

• Active low or active high logic outputs
• Use as general purpose serlal-to-parallel converter
or ring counter
• Low power consumption characteristics of CMOS
• Inputs and outputs interface directly with TTL,
NMOS and TTL devices_

PIN CONFIGURATIONS
(25C02)
DO
(25~03) 1

0

KS25C02
AND
KS25C03

c8

SAMSUNG SEMICONDUCTOR

KS25C04

586

CMOS INTEGRATED CIRCUIT·

KS25C02lKS25C03/KS25C04
LOGIC DIAGRAM
DO
(25C02.
25C04 07(11)

06(10)

ace

00

CP~·2
~.,

NOTE 1: Cell logic is repeated for register stages 05 to 01 KS25C02, KS25C03
2: Numbers in parenthesis are for KS25C04

II

TRUTH TABLE
Time

Inputs

Outputs'

tn

0

S

E2

003

07

Q6

QS

Q4

Q3

Q2

Q1

ao

ace

0
1
2
3
4
5
6
7

X

L
H
H
H
H
H
H
H
H
H

X
.X

X

X

X

X

X

X

X

X

X

X

L
L
L
L
L
L
L
L
L
L
L

X

L
07
07
07
07
07
07
07
07
07

H
L
06
06
06
06
06
06
06
06

H
H
L
05
05
05
05
05
05
05

H
H
H
L
04
04
04
04
04
04

H
H
H
H
L
03
03
03
03
03

H
H
H
H
H
L
02
02
02
02

H
H
H
H
H
H
L
01
01
01

H
H
H
H
H
H
H
L
00
00

H
H
H
H
H
H
H
.H
L
L

X

H

X

H

NC

NC

NC

NC

NC

NC

NC

8
9
10

07
06
05
04
03
02
01
00'

X
X
X

07
06
05
04
03
02
01
00

NC

NOTES:
1: Truth table for KS25C04 is extended to include 12 outputs.
2: Truth table for KS25C02 does not include E column or last line in truth table shown.
3: Truth table for KS25C03 does not include 00 column.
H = High Voltage Level
L = Low Voltage Level
X = Oon't Care
NC No Change

=

cIS SAMSUNG SEMICONDUCTOR

587

~

CMOS INTEGRATED CIRCUIT

KS25C02lKS25C03lKS25C04
ABSOLUTE MAXIMUM RATINGS
Characteristic

Symbol

Value

Unit

Supply Voltage
DC Input Diode Current
DC Output Diode Current
Continuous Output Current Per Pin
Continuous Current Through Vee or GND Pins
Power Dissipa,ion Per Package
Operating Temperature
Storage Temperature

Vee
ItK
10K

-0.5 - +7
±20
±20
±35
±125
500
0-+70
-55 -+125

V
mA
mA
mA
mA
mW
·C
·C

DC ELECTRICAL CHARACTERISTICS
Characteristic

" Symbol

10'
ICON
Po

Top,
TS'g

(Over Recommended Operating Conditions)
Test Conditions

Min

Typ

Operation Voltage

Vcc

4.5

5.0

High-Level Input Voltage

VIH

Vee = Min

2.0

Low-Level Input Voltage

VIL

Vee = Min

0

-

High-Level Output Voltage

VOH

Vcc = Min, VIN = VIH or VIL
10= -20p,A
10= -4mA

Vcc-0.1
2.4

Low-Level Output Voltage

VOL

Vee = Min, V'N = VIH or VIL
10 = 20p,A
10 = 9.6mA

0
0

Low-Level Input Current

IlL

Vcc = Max, VIL = 0.4V

High-Level Input Current

IIH

V~e = Max, VIH = 2.4V

Supply Current

Icc

Vee = Max, VIN = Vee or GND

AC ELECTRICAL CHARACTERISTICS

-

Max

Unit

5.5

V

Vee

V

0.8

V

-

Vee
Vee

V
V

-

0.1
0.4

V
V

0.5

" 1.0

p,A

0.5

1.0

p,A

1.0

10.0

p,A

(Over Recommended Operating Conditions), CL=15pF "
Min

Typ

Max

Unit

10

18

28

ns

-

15

24

ns"

10

20

38

ns

-

12

19

ns

ts(O)

-10

4

8

ns

Start Input Setup Time

ts(s)

0

5

10

ns

Minimum Low CP Width

tPWL

5

20

ns

Minimum High CP Width

tPWH

1.5

20

ns

Maximum Clock Frequency

fMAX

-

25

MHz

Characteristic

Symbol

Propagation Delay to a Logical "0"
from CP to any Output

tpDO

Propagation Delay to a Logical "0"
from E" to 07(011) Output "

tpDO

Propagation Delay.to a Logical "1"
from CP to Any Output

tpO"'

Propagation Delay to a Logical "1"
from E" to 07(011) Output

tpo,

Data Input Setup Time

c8

SAMSUNG SEMICONDUCTOR

Test Conditions

CP high, Slow,
kS25C03, KS25C04 only

CP high, Slow,
KS25C03, KS25C04 only

-

58a

KS25C02lKS25C03/KS25C04

CMOS INTEGRATED CIRCUIT

TIMING DIAGRAMS
KS25C02, KS25C03, KS25C04
CP
INPUTS

{

~

:

07-L____
06

~

____________________________

~

_____________________

-'-----'

05
04
03
OUTPUTS

02

II

01
00
Occ

l

DO

APPLICATION iNFORMATION
Operation

clock low-to-high transition in order to guarantee correct resetting. After the clock has gone high resetting
the register, the S signal must be removed. On the next
clock low-to-high transition tl:le data on the D input is
set into the 07(11) register bit and the 06(10) register
bit and 05(9) is set to a low. This operation is repeated
for each register bit in turn until the register has been
filled. When the data goes into 00, the Occ signal goes
low, and the register is inhibited from further change
until reset by a Start signal.

The registers consist of a set of master latches that act
as the control elements in the device and change state
on the input clock high-to-Iow transition and a set of
slave latches that hold the register data and change on
the input clock low-to-high transition. Externally the
device acts as a special purpose serial-lo-parallel converter that accepts data at the 0 input of the register
and sends the data to the appropriate slave latch to
appear at the register ,output and the DO output on the
KS25C02 and KS25C04 w!1en the clock goes from lowto-high. There are no restrictions on the data input; it
can change state at any time except during a short interval centered about the clock low-to-high transition.
At the same time that data enters the register bit the
next less significant bit register is set to a low ready
for the next iteration.

The KS25C02, KS25C03 and KS25C04 have a specially
tailored two-phase clock generator to provide nonoverlapping two-phase clock pulses (i.e., the clock
waveforms intersect below the thresholds of the gates
they drive). Thus, even at very slow dV/dt rates at the
clock input (such as from relatively weak comparator
outputs), improper logic operation will noi result.

The register is reset by holding the.S (Start) signal low
during the clock low-to-high transition. The register synchronously resets to the state 07(11) low, and all the
remaining register outputs high. The Occ (Conversion
Complete) signal is also set high at this time. The S
signal should not be brought back high until after the

All three registers can be operated with various logic
codes. Two's complement code is used by offsetting
the comparator 1/2 full range + 1/2 LSB and using the
complement of the MSB (07 or 011) with a binary DIA

.ciS SAMSUNG SEMICONDUCTOR

Logic Codes

589

I

CMOS INTEGRATED CIRCUIT

KS25C02lKS25C03lKS25C04
APPLICATION INFORMATION

(Continued)

converter. Offset binary is used in the same manner but
with the MSB (07 or (11). BCD D/A converters can be
used with the addition of illegal code suppression logic.

Active High or Active Low Logic .
The register can be used with either D/A converters that
require a low voltage level to turn on, or D/A converters
that require a high voltage level to turn the switch 'on.
I! D/A converters are used which turn on with a low logic
level, the resulting digital output from the register is
active low. That is, a logic "1" is represented as a low
voltage level. I! D/A converters are used that turn on with
a high logic level then the digital output is active high;
a logic "1" is represented as a high voltage level.

tion of ace and the appropriate register output.

Comparator Bias
To minimize the digital error below ± 1/2 LSB, the
comparator must be biased. If a D/A converter is used
which requires a low voltage level to turn on, the comparator should be biased + 1/2 LSB: I! the D/A converter
requires a high logic level to turn on, the .comparator
must be biased -1/2, LSB.

Definition of Terms
CP: The clock input of the register.

0: The serial data input of the register.
DO: The serial data out. (The D input delayed one bit).

Expand,d Operation
An active low enable 'input, E, on the KS25C03 and
KS25C04 allows registers to be connected together to
form a longer register by connecting the clock, D, and
S inputs in parallel and connecting the
output of
one register to the E input of the next less significant
register. When the start resets the register, the E signal
goes high, forcing the a7 (11) bit high and inhibiting the
register from accepting data until the previous register
is full and its
goes low. I! only one register is
used. the E input should be held at a low 10gic'Ievei.

ace

ace

E: The register enable. This input is used to expand the
length of the register and when high forces the 07 (11)
register output high and inhibits conversion. When not
used for expansion the enable is, held at a low logic level
(ground).
Q 1 1= 7(11)

to 0: The outputs of the register.

Q cc : The conversion complete output. This output re-

mains high during a conversion and goes low when a
conversion is complete.
,07(11): The true output of the MSB of the register.

Short Cycle
I! all bits are not required, the register may be truncated
and, conversion time saved by using a register output
going low rather than the ace signal to indicate the
end of conversion. I! the register is truncated and
operated in the continuous conversion mode, a lock-up
condition may occur on power turn-on. This condition
can be avoided by making the start input the OR func-

07(11): The complement output of the MSB of the
register.

S: The

start input. If the start input is held low for at
least a clock period the register will be reset to 07(11)
low and all the remaining outputs high. A start pulse
that is low for a shorter period of time can be used if
it meets the set-up time requirements of the S input.

TYPICAL APPLICATIONS
BCD ILLEGAL CODE SUPPRESSION
s

DO

Qcc
Q7Q6Q5Q4Q3Q2Q1QO

CLOCK CP

KS25C02

OIA CONVERTER

ACTIVE HIGH

c8

SAMSUNG SEMICONDUCTOR

o
CLOCK

CP

S

DO

KS25C02

Qcc
Q7Q6Q5Q4Q3Q2Q1QO

OIA CONVERTER

ACTIVE LOW

590

CMOS INTEGRATED CIRCUIT

·KS25C02lKS25C03/KS25C04
FAST PRECISION AID CONVERTER

.y.

BIPOLAR

100K

100

f;~~UNIPOLAR)
0

100

~+-

____

-15V

BIPOLAR OFF

~

____________________

~8__- - .

11
: } ANALOG INPUTS

R2

9.95K

100

15V

5V

1K

I

-15V

1 9
CONY COMP o---::---fCC
SERIAL OUT o----:'---i

11

DATA IN

14

START

CLOCK

INPUT RANGES
UNIPOLAR

o to 10
o to 5
o to 20

c8

BIPOLAR

CONNECT

EQUIV. DAC louT

±5
±2.5
±10

Input to A
Input to A
Input to B
B to DAC OUT

2.36KO
1.90KO
3.08KO

SAMSUNG SEMICONDUCTOR

591

KS25C02lKS25C03/KS25C04

CMOS INTEGRATED CIRCUIT

SWITCHING TIME WAVEFORMS'
AT LEAST

AT LEAST

CP

- - - - - r - - - - 1,5V

s
tSID) MIN

0

tpoo MAX

tpoo

MIN

tpDI MIN

1,5V

07(11)

tpDO MAX
tp01 MAX.

tpDO MIN

06(10)

-1,5V
tpD1 MIN

tpD1 MAX

DO
. KS25C02,
KS25C04

-1.5V
tpDO MIN

E
KS25C03,
KS25C04

07(11)

1J , , ,", . ~i
WAVEFORMS

--

c8

INPUTS

1.5V
ENABLE TO 07(11)'
CP=H
S=L

1.5V

OUTPUTS

--

Must be steady

Will be steady

~

May change from
H to L

Will be changing
from H to L

iZlT

May change from
LtoH

Will be changing
from L to H

5

Don't care: any
change permitted

Changing: state
unknown

SAMSUNG SEMICONDUCTOR

592

KA33V

LINEAR INTEGRATED CIRCUIT

SILICON MONOLITHIC BIPOLAR INTEGRATED
CIRCUIT VOLTAGE STABILIZAER FOR
ELECTRONIC TUNER

TQ.92

The KA33V is a monolithic integrated voltage stabilizer especially
designed as voltage supplier for electronic tuners.

FEATURES
• Low Temperature Coefficient
• Low Dynamic Resistance
• l\tplcal Reference Voltage of 33V

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Characteristic

Symbol

Value

Unit

10
200

mA
mW

Topr

-20-75

°C

Ts.g

-40-125

°C

1: Anode 2: Cathode

Zener Current
Power Dissipation (T. = 75°C)
Operating Ambient TemperatureRange
Storage Temperature Range

Iz
PD

II

ELECTRICAL CHARACTERISTICS (Ta =25°C)
Characteristic

Symbol

Stabilized Voltage
Stabili;:ed Voltage·Temperature Drift

Vz
6Vz/6T

Dynamic Resistance

rz

Test Conditions

Min

Typ

Max

31

Iz=5mA
Iz=5mA
T.=-20t075°C
Iz=5mA, f=1KHz

-1

35
0

1

10

25

Unit

V
mV/oC

SCHEMATIC DIAGRAM
2 Cathode

R4

~r 01

~

02

~,.. 03

~,.. 04

*05

r-. 03
R3

VOl!
/"

R2

.

~Rl

I.

"

01

.
1 Anode

c8

SAMSUNG SEMICONDUCTOR

595

KA33V

LINEAR INTEGRATED CIRCUIT

MEASURING CIRCUITS
Measuring Circuit for Stabilized Voltage Vz
---lz=5mA
.----~

A

~----~

______~________~

2

. V

KA33V

IIoR Meter

Measuring Circuit for Dynamic Resistance
IZ

Iz--

----lAC-To
. 5O~F

100

c
0.1,.1'

WI

EB

vz

o.smA

WI
rz= a.5mA

1--+-+--'" SmA

Iz

VV1

c8

SAMSUNG SEMICONDUCTOR

596

KA33V

LINEAR INTEGRATED CIRCUIT

TYPICAL APPLICATION
Ych

Zch

RI

C
Channel
setting
variable
resistor

15KI!

• to luning dlod88 (varaclor) In cue or Ych on

(1) UHF TUNER

TRI

TR2

-(

-(

TRI: RF AMP: KSC1393
KSC1070 (Under development)
TR2: osc: KSC1730
01·04: 18220 05: MIXER: 18818

~

II

OAFC
terminal

(2) VHF TUNER

-(
TR3
TR2

TR1: RM AMP: KSC1393
TR2: MIXER : KSC1394
TR3: osc
: KSC1730
.01,04: 182209
02, 03: 182207

cB

SAMSUNG SEMICONDUCTOR

~

0

AFC terminal

597

KA33V

LINEAR INTEGRATED CIRCUIT

POWER·TEMPERATURE DERATING CURVE

TYPICAL CHARACTERISTIC CURVES (Ta=25"C)
DYNAMIC RESISTANCE va.
ZENER CURRENT

ALLow\BLE DISSIPATION YS.
AMBIENT TE.MPERATURE
60
60

FR1AIR
40

I~

0

"I

,

\

I~

20

""

~

II

I
I

I",.-\--

'.1KHz

~

I'l

~

T.=+25'C

10
6
6

~

-

r-...

==

4

2

-20

25
50
T. - AMBIENT TEMPERATURE - ·C

75

2

4
6
. Iz -;- ZENER CURRENT -mA

10

STABILIZED VOLTAGE VARIATION

STABILIZED VOLTAGE TEMPERATURE
DRIFT va. ZENER CURRENT

va. TIME

FREE AIR

~Z~~~1V
1

0

,

1-0

-

IT'}
Iz==5mA XY-RECODER

1

2

1--. t - -

3

r--- r---

4

4
6
Iz - ZENER CURRENT - mA

10

~

____

~

_____ L_ _ _ __ L_ _ _ _

10

15

20304050 1

10 20

30

min.

STABILIZED VOLTAGE VARIATION It
SUPPLY VOLTAGE VARIATION YS.
ZENER CURRENT

-1DL-____

1 , . ·r"
TTlme

~

10
lz - ZENER CURRENT - rnA

c8

SAMSUNG SEMICONDUCTOR

598

LINEAR INTEGRATED CIRCUIT

KA2580A1KA2588A
8-CHANNEL SOURCE DRIVERS

18 DIP

These integrated circuits, rated for operation with output voltages of up
to 5fN and designed to link NMOS logic with high-current inductive loads,
will work with many combinations of logic-and load-voltage levels, meeting interfacll requirements beyond the capabilities of standard logic
buffers.
KA2580A is a high current source driver used to switch the ground ends
of loads that are directly connected to a negative supply. Typical loads
are telephone relays, PIN diodes, ·and LEOs.
KA2588A is a high-current source driver similar to KA258OA, has separated logic and driver supply lines. Its eight drivers can serve as an interface between positive logic (TTL, CMOS, MOS) or negative logic
(NMOS) and either negative or split-load supplies.

20 DIP

KA2580A is furnished in 18-pin dual in-line plastic package; KA2588A
is supplied in a 2O--pin dual in-line plastic package. All input connections
are on one side of the packages, output pins on the other, to simplify
printed wiring board layout.

FEATURES
•
•
•
•

TTL, CMOS, PMOS, NMOS Compatible
High Output Current Ratings
Intemallnlnslent Suppression
Efficient Input/Output Pin Structure

I

SCHEMATIC DIAGRAM

NC
SUBIVEE

SUB/VEE

KA21i8OA

c8

SAMSUNG SEMICONDUCTOR

KA2588A

599

LINEAR INTEGRATED CIRCUIT

KA258oA1KA2588A
ABSOLUTE MAXIMUM RATINGS
(T.=25°C, for Any One Driver unless otherwise noted)

Symbol

Characteristic

Output Voltage
Supply Voltage (ref, sub)
Supply Voltage (ref, sub, KA2588A)
Input Voltage (ref, Vs)
Total Current
Substrate Current
Power Dissipation (single output)
(total Package)'
Operating Temperature
Storage Temperature

Unit

value
50
50

Vee
Vs
Vee
VIN
lee+ls
ISUB
Pel

V
V
V

50

-30
-500
3.0
1.0
2.2
-20-+85
-65- +150

T.
lStg

V
mA
A
W
W
°C
°C

, Derate at the rate of 18mWI"C above 25°C

TYPICAL OPERATING VOLTAGE
Vs

VIN(on)

VIN (off)
-0.5V-

Vee

Vee (max)

DVCType

OV

NA

-50V

KA2580A

OV

-15V- -3.6V

+5V

OV- +l.4V

+4.5V;" +5V

NA
s5V

-45V
-45V

KA2580A
KA2588A

+12V

OV- +8.4V

+ 11.5V- + 12V

NA
s12V

-38V
-38V

KA2580A
KA2588A

+15V

OV- +11.4V

+ 14.5V - + l'5V

NA
s15V

-35V
-3SV

KA2580A
KA2588A

--

Notes
1) For simplicatlon, these devices are characterized to the above with specific voltages for inputs, 'logic supply (V.), load
, supply (VeEJ, and coliector supply (Vee).
'
2) Typical use of the KA2580A is with negative referenced logic. The more common application of the KA2588A is with positive
referenced logic supplies.'
'
3) In application, the devices are capable of operation over a wide range of logic and supply voltage levels.
,
4) The substrate must be tied to the most negative point In the external circuit to maintain Isolation drivers and ~o provide
for normal circuit operation.

,c8

SAMSUNG SEMICONDUCTOR

600

KA2580A1KA2588A

LINEAR INTEGRATED CIRCUIT

PARTIAL SCHEMATIC (KA2580A)

IN

o---llN_4-f
10K

'-----+-_OUT

+Vs

SUBJVee

SUB

ELECTRICAL CHARACTERISTICS (KA2580A)
(T. =2S0C, Vs -rN, Vee" -45V unless otherwise noted)
Characteristic

Output Leakage Current

Symbol

Icex

Output Sustaining Voltage
(Note 1, 2)

Vce (sus)

Output Saturation Voltage

Vce (sat)

Input Current

IIN'(on)
liN (off)

Input Voltage
(Note 4)

VIN(on)
VIN(off)

Clamp Diode Leakage Current

Max

Unit

vln=-o.sv,
VOUT -Vee - -SrN

SO

pA

VIN;" -0.4V,
VouT-Vee - -SOY
T.=70oC

100

pA

Test Conditions

VIN=-0.4V,loUT=-2SmA

Min

VIN=-2.4V,loUT=-100mA

1.8

V

VIN --3.rN,louT --22SmA

1.9

V

VIN --3.av, louT=-3S0mA

2.0

V

VIN--3.av,loUT=-3S0mA

-SOO

pA

VIN=-1SV,louT=-3S0mA

-2.1

mA

lOUT- -SOOpA, T.=70oC
(Note 3)

pA

-SO

louT=-100mA, Vce:S1.av

-2.4

V

louT--22SmA, Vce:s1.9V

-3.0

V

louT=-3S0mA, Vce:s2.OV

-3.6

V
pA

loUT=-500pA, T.=7QOC

I

V

3S

V

-0.2

IR

VR-SrN, T.-70oC

SO

Clamp Diode Forward Voltage

Vf

If-3S0mA

2.0

V

Input Capacitance

CIN

2S

pF

Turn-On Delay

tPHL

O.S VIN to O.S VOUT

S.O

,.S

Turn-Off Delay

tPLH

O.S VIN to O.S VOUT

5.0

,.8

Notes
1)
2)
3)
4)
5)

Pulsed test, tp:s300uS, duty cycle:s2%.
Negative current Is defined as coming out of specified device pin.
The lin (off) current limit guarantees against partial turn-on of the output.
The Yin (on) voltage limit guarantees a minimum output source per the specified conditions.
The substrate must always be tied to the most negative point and must be at least 4.rN below Ve.

c8

SAMSUNG SEMICONDUct'OR

601

KA2580AlKA2588A

LINEAR INTEGRATED CIRCUIT

PARTIAL SCHEMATIC (KA2588A)
+vs

vee

.7.2K
IN ........,.,.-+-t
10K

'------:t- OUT
SUB

.' ELECTRICAL CHARACTERISTICS (KA2588A)
(T.=25·C, Vs=Vee=5.0V, VEE =-40V unless otherwise noted)
Characteristic

Output Leakage Current
Output Sustaining Voltage
(Note 1, 2)

Output Saturation Voltage

Input Current

Symbol

Test Conditions

leEX

VCE (sus)

VeE (sat)

liN (on)

Unit

V,N 2: 4.5V, VOUT=VEE=-45V

50

pA

Y'N 2: 4.fN, VOUT =VEE = -45V
T.=70°C

100

pA

V'Nton)
V,N(of!)

35

V

Y'N =2.6V, louT = -100mA
Ref. Vee

1.8

V

V'N=2.0V,loUT= -225mA
Ref. Vce

1.9

V

Y'N "'1.4V, louT'" -350mA
Ref. Vce

2.0

V

V'N=1.4V,loUT=-350mA

-500

pA

Vs=15V, VEE =-30V,
Y'N =OV, lOUT'" -350mA

-2.1

mA

louT=-500pA, T.=70oC
(Note 3)

liN (off)

Input Voltage (Note 4)

Max

V'N2::4.6V,loUT=-25mA

Min

-50

pA

IOUT= -100mA, VcE s1.8V

2.6

IOUT=-225mA, Vces1.9V .

2.0

V

louT=-350mA, VeEs2.0V

1.4

V

VR=5QV, T.=7QOC

50

pA

If=350mA

2.0

V

25

pF

IOUT=-500pA, T,.,=7O"C

4.8

V

V

Clamp Diode Leakage Current

IR

Cla!11P Diode Forward Voltage

Vf

Input Capacitance

C,N

Tur'n-On Delay

tpHL

0.5 Y,N to 0.5 Vout

5.0

,.8

Turn-Off Delay

tPLH

0.5 Y'N to 0.5 Vout

5.0

,.S

;'

Notes
1)
2)
3)
4)
5)
6)

Pulsedtest,"tps300uS, dutycycles2%.
Negative current is defined as coming out of specified device pin.
The lin (off) current limit guarantees against partial turn-on of the output.
The Yin (on) yoltage limit guarantees a minimum output source per the specified conditions.
The substrate must always be tied to the most negative point and must be at least 4.0V below·V•.
Vee must never be more positive than Vs.

c8

SAM8UNG ~EMICONDUcroR

602

KA2580Al2588A

LINEAR INTEGRATED CIRCUIT

ALLOWABLE PEAK COLLECTOR CURRENT
AT 50·C AS A FUNCTION OF DUTY CYCLE

ALLOWABLE PEAK COLLECTOR CURRENT AT 7O·C AS
A FUNCTION OF DUTY CYCLE
500

I'

5l 450

I'

!(

!(

51450

400
1
z

~ 400

1!:

I:

!z35O

~ 200
~

150

f:

RECOMMENDED MAXIMUM OUTPUT CURRENT

I!!

B300

u

~250

=d

~

I

j
. NUMBER OF OUTPUTS
CONDUCTING
. SIMULTANEOUSLY

250

w

~

200 -

\ ~\ ~

I"\'0 ~ ~ r---...
~ ""'OUTP~ ~."'s
~~ t:--. ........... r..:::
r--r---- ;;;- ts

NUMBER OF
CONDUCTING

.

0-

KA2580A
KA25B8f

0L-.~'0~~20~~~~~~~~5~0~OO~~~~~OO~~9~0-'~00%
PER CENT DUTY CYCLE

r::
:;I

0

~ys=15V
KA2580A

3.......

.

~ 150 -SiMU~NEOUSLY

I I
__ Vs=15V

"

~

-

8

~

, KA2588A

o

10

20

30

40

50

60

70

80

90

100%

PERCENT DUTY CYCLE

TYPICAL APPLICATIONS
+12V

KA258BA

KA258BA

I

111

Vacuum Fluorescent Display Driver (Split Supply)

Telecommunicaiton Relay Driver (Positive Logic)

Telecommunication Relay Driver (Negative Logic)

c8

SAMSUNG SEMICONDUCTOR

•

603

KA2651

LINEAR INTEGRATED CIRCUIT.

FLUORESCENT DISPLAY DRIVERS

18 DIP

Consisting of eight NPN Darlington output stages and the associated common-emitter Input stages, these drivers are designed to Interface between low-level digital logic and vacuum fluorescent displays.
KA2651 is capable of driving the digits and/or segments of these displays and Is designed to permit all outputs to be activated simultaneously. Pull-down resistors are Incorporated into each output and no external components are required for most fluorescent display applications.

FEATURES
•
•
•
•
•

Digit or Segment Drivers
Low Input Current
Intemal Output Pull-Down Resistors
High Output Breakdown Voltage
Single or Split Supply Operation

BLOCK DIAGRAM

c8

SAMSUNG SEMICONDUCTOR

604

KA2651

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS
(Ta = 25·C, Voltage are with reference to ground unless otherwise noted)
Characteristic

Symbol

Value

Unit

Supply Voltage
Input Voltage
Output Current
Operating Temperature
Storage Temperature

Vee
VIN
lout
Ta
T.tg

65
20
-40
-20 +85
-65 + 150

V
V
rnA
·C
·C

RECOMMENDED OPERATING CONDITIONS
Characteristic

Symbol

Value

Unit

Supply Voltage

Vee

5.0-50

V

Input ON Voltage

VIN

2.4-15

Output ON Current"

loutON

V

-25

rnA

" Positive (negative) current Is defined as going into (coming out of) the specified device pin.

ELECTRICAL CHARACTERISTICS
(Ta = 25°C, Vee = 60V, VEE = OV unless otherwise noted.)
Characteristic

Symbol

Test Conditions

Min

Typ

Max

Unit

Output Leakage Current

louTLK

VIN =0.4V

15

p.A

Output OFF Voltage

VOUTOFF

VIN=0.4V

1.0

V

Output Pull·Down Current

louTPo

Input Open, VOUT = Vee

350

775

p.

Output ON Voltage

VOUTON

VIN = 2.4V lOUT = - 25mA

57

Input ON .Current
Supply Current

c8

liN
lee

SAMSUNG SEMICONDUCTOR

500

V

58

VIN=2.4V

120

225

poA

VIN=5.0V

p.A

375

650

All Inputs Open

10

100

p.A

All Inputs = 2.4V

5.5

8.0

mA

605

I

LINEAR INTEGRATED CIRCUIT

·KA2651
PARTIAL SCHEMATIC

,-------,.------.---0 Vee

10K

I NPUT o----'w..-----t-~--I

'----+--'-Q

OUTPUT

125K
GNDo-------~~--~----------~

(One Driver)

TYPICAL MULTIPLEXED FLUORESCENT DISPLAY
Vee
SEGMENT SELECT
KA2651

b-1

~
a-~
f-~

9-4

"

t;a

~

Fit

"::::

9

~

~

~~I-

ttt

r,)

FTIlr-

DIGIT SELECT
KA2651

o1 - 1
.'7
o2-~
o3 -- ~

-"

~ r-r-----~ r-r----F,3 r- f--------

4-~
5 -~

o6

·07

--~

. ~
·08 --~

9

--

'12
~

Vm

---------------------------

L!J r
T

-----

0

,------0

{"

Ff6 r-f-------

...fLoo

-----------

...,
"

18

F;7

I~ I~

I

~

~
~

c-~

.

Ff7

Ftt

e-~

d-~
d p-~

(

VBIAS

6
VFI

Ff& r--

. ciS SAMSUNG SEMICONDUCTOR

606

KA2803

LINEAR INTEGRATED CIRCUIT

LOW POWER CONSUMPTION EARTH
LEAKAGE DETECTOR

8 DIp·

The KA2803 is designed for use in earth leakage circuit interrupters, for
operation directly off the AC line in breakers. The input of the differential amplifier is connected to the secondary coil of ZCT (Zero Current
Transformer). The amplified output of differential amplifier is integrated
at external capacitor to gain adequate time delay that is specified in
KSC4613.
The level comparator generates high level when earth leakage current
is greater than some level.

FUNCTIONS
• Differential amplifier
• Level camparator
• Latch circuit

FEATURES
•
•
•
•
•
•
•
•
•

Low power consumption (P. =5mW, 100Vl200V)
Built-in voltage regulator
High gain differential amplifier (VT =13.5mV)
1mA output current pulse to trigger SCR'S
Low external part count, economic
Mini-dip package (8 Dip), high packing density
High noise immunity, large surge margin
Super temperature characteristic of input sensitivity
Wide operating temperature range (1. = -25°C - +80 0 C)

I

APPLICATION CIRCUIT
1. Full wave Application Circuit

2. Half wave Application Circuit
LOAD

LOACo

( ____ '[ _. _______.____________________ J

Fig. 1

.c8

SAMSUNG SEMICONDUCTOR

Fig. 2 .

607

LINEAR INTEGRATED CIRCUIT

KA2803'

. ABSOLUTE MAXIMUl\II RATINGS (Ta = 25°C)
Characteristic
Supply Voltage
Supply Current
Power Dissipation .
Lead Temperature (soldering 10 sec)
Operating Temperature
Storage Temperature

value

Unit'

20
8
300
260.
-25- +80
-65-+150

V
mA
mW
°C
°C
°C

Symbol
VccfVee
Is
Po
T'e'"
Topr
T.tg

ELECTRICAL CHARACTERISTICS (Ta =25°C)
Characteristic
Supply Current 1

Symbol
Is,

Trip Voltage

------

Test Conditions

Min

Vee =12V (-25°C)
VA.lJ, =3oomV (25°C)
(80°C)
Vee -16V (-25°C - 800C)
VA.lJ,=X

10

~p

Max

Unit

400

580
530.
480

pA
pA
pA

13.5

17

mVrms

Differential Amplifier Output
Current 1
- ,-_ ... _.._-

Iro,

Vee ... 16V (25°C)
VA.lJ,=30mV
Voo-1.2V

12

30

pA

Differential Amplifier Output
Current 2

ITo2

Vee-16V (25°C)
Voo-O.6V
VA~ V, short

17

37

pA

10

Vse-1.4V
Vos=O.6V
Vee .. 12V (-25°C)
(+25°C)
(+800C)

Latch on Voltage

Vocon

Vee .. 16V (25°C)

Latch Input Current

I",on

Vee =12V (25°C)

Output Low Current

10SL

Vec.12V (-25-8OOC)
VosL=O.2V

200

Dllf. Input Clamp Voltage
..

V'De
VSM

"DC -1oomA

0.4

2

V

ISM" 7mA (-25°C)

20

28

V

900

pA

_. - --- -----_.

Output Current
...

-200
-100
-75
0.7

pA
pA
pA

1.4

V

5

pA
pA

~

-

Maximum Current Voltage

Supply Current 2
.Latch Off Supply Voltage
Response Time

c8 SAMSU~~

(-25 - 800C)

IS2

VA.lJ,-X(25-800C)
vos-a.s

VooI'

VOl'" high (25°C)

7.0

Ton

Vee =16V (25°C)
VA.lJ,-O.3V

2

SEMICONDUCTOR

V
4

msse .

608

KA2803

LINEAR INTEGRATED CIRCUIT

APPLICATION NOTE·
(refer to full wave application circuit Fig. 1)
The Fig 1 shows the KA2803 connected in a typical leakage current detector system.
The power is applied to the Vee terminal (Pin 8) of the KA2803 directly from the power line.
The resistor Rs and capacitor Cs are chosen so that pin 8 voltage is at least 12V.
The value of Cs is recommended above 1pF at this time.
If the leakage current is at the load, it is detected by the zero current transformer (ZCT).
The output voltage signal of ZCT is amplified by the differential amplifier of the KA2803 internal circuit and appears as halfcycle sine wave signal referred to input signal at the output of the amplifier.
The amplifier closed loop gain is fixed about 1000 times with internal feedback resistor to compensate for zero current transformer (ZCT) Variations.
The resistor RL should be selected so that the breaker satisfies the required sensing current.
The protection resistor Rp is not usually used put when the high current is injected at the breaker, this resistor should be used
to protect the earth leakage detector IC the KA2803.
The range of Rp is from several hundred Il to several kll.
The capacitor C, is for the noise canceller and standard value of C, is 0.0471'F. Also the capacitor C 2 is noise canceller
capacitance but it is not usually used.
When high noise is only appeared at this system 0.0471'F capacitor may be connected between pin 6 and pin 7.
The amplified signal is finally appeared to the Pin 7 with pulse signal through the internal latch circuit of the KA2803.
This signal drivies the gate of the external SCR which energizes the trip coil which opens the circuit breaker.
The trip time of breaker is decided by the capacitor C3 and the mechanism breaker.
This capacitor should be selected under 1pF for the required the trip time.
The full wave bridge supplies power to the KA2803 during both the positive and negative half-cycles of the line voltage.
This allows the hot and neutral lines to be interchanged.
If your application want the detail information, request it on our application circuit designer of KA2803.

c8

SAMSUNG SEMICONDUCTOR

609

I

KA2804

LINEAR INTEGRATED CIRCUIT

ZERO VOLTAGE SWITCH
The KA2804 is a TRIAC controller providing a complete solution for temperature controlled electric panel heaters, cookers, film processing baths
etc.

8 DIP

Switching occurs at the zero voltage point in order to minimize radio frequency interference. The device is suitable for mains-on-line operation
- and requires minimal components.

FEATURES
• Easy operation either through the AC line or a DC supply.
• Supply voltage controL
• Very few-external components.
• Symmetrical burst control - No DC current compon,nts in the
load circuit.
• Negative output current pulse up to 250mA-short circuit pro/ tection.
• Reference voltage output.

BLOCK DIAGRAM

Vs

IS

1--~---~4' ~9.tt'::NV-

1 - - - - - - 1 3 I~XUT
GND

AC
VSYN
ISYN~
INP.UTo--"'4~----(1

RSVN

REFERENCE
VOLTAGE

Vo

c8

1---,( 1 06EwE
OUTPUT

Lo

SAMSUNG SEMICONDUCTOR

610

KA2804

LINEAR INTEGRATED CIRCUIT

ABSOLUTE MAXIMUM RATINGS (Ta=25°C)
Characteristic

Symbol

Value

Unit

Supply Voltage
Supply Current
Synchronous Current
Input Voltage
Power Dissipation
Junction Temperature
Operating Ambient Temperature
Storage Temperature

-Vs
-Is
IsvN
VI
Po
TJ
Top,
TSIg

8.2
40 (average)
5.0 (rms)

V
mA
mA
V
mW
°C
°C
°C

~IVsl

350
125
-20-+70
-65-+150

ELECTRICAL CHARACTERISTICS
(Vs=8.0V, VSVN =100 to 115V,ms, Ta =25°C, f=50/60Hz, unless otherwise specified)
Characteristic
Circuit Current
Supply Voltage 1

Test Conditions

Symbol

Min

Typ

Max

Unit

-I~

Pin 5, RSVN =56K

-

2.0

2.5

mA

-Vs 1

Pin 5, Is=2.5mA
RSVN =56K

7.2

-

8.4

V

-Vs2

Pin 5, Is=20mA
SVN=56K

R

7.2

8.6

~-

Synchronous Current

IsvN

Pin8

0.3

-

Output Pulse Width

Tp

Pin 6, RSVN =56K

-

200

-

Output Voltage

Vo

Pin 6, 10~200mA

4.2

5.2

-

V

Output Current

10

Pin 6, Ro~25

200

250

-

mA

Output Leakage Current

ILO

Pin6

-

2.0

pA

2.0

5.0

mV

0.5

1.0

pA

-

5.7

V

0.2

pA

3.6

-

V

Supply Voltage 2

Input Offset Voltage

VIO

Pin3,4

Input Bias Current

II

Pin 3, 4

-

-VICM

Pin 3, 4

0

Pin2

-

Common Mode Input
Voltage Range
Output Leakage Current
Reference Voltage

c8

kc
-VR

SAMSUNG SEMICONDUCTOR

Pin 1, IR~1uA

V
mA

,.s

611

I

LINEAR INTEGRATED CIRCUIT

KA2804

APPLICATIONS
ON-OFF TEMPERATURE CONTROL

fJC

.------4~--------------------------------

__~------------_.----_o10Wrms
SO/60Hz

NTC
Ro

7

56

KA2804

RH

VR

Rsyn
S6K

RH! HYSTERESIS VOLTAGE SET
Rs

6.8K
ZW

. TIME PROPORTIONAL TEMPERATURE CONTROL

AC

.-------------.....,----~--___.---------------------~--------------.,....--_o

100Vrms

SO/60Hz
39K

RT

RD

56

NTC

7
KA2804

Cl

Ci

..J

Rsyn
RT Cr TIMING PERIOD SET

c8

SAMSUNG SEMICONDUCTOR

Rs
6.8K
ZW

S6K.

612

LINEAR INTEGRATED CIRCUIT

LM386/S/D

LOW VOLTAGE AUDIO POWER AMPLIFIER
8 DIP

The LM386/SID is a power amplifier designed for use in low
voltage consumer applications. The gain is internally set to 20
to keep external part count low, but the addition of an external
r~sistor and capacitor between pins 1 and 8 will increase the
gain to any value up to 200.
The inputs are ground referenced while the output is automatically
biased to one half the supply voltage. The quiescent power drain is only
30 milliwatts when operating from a 6 volt supply, maldng the LM386 ideal
for battery operation.

8 SOP

FEATURES
• Battery operation.
• Minimum external parts.
• Wide supply voltage range: 4V -12V (LM386)
4V-9V (LM386S/D)
• Low quiescent current drain (4mA.)
• Voltage gains: 20 - 200.
• Ground referenced Input.
• Self-centering output quiescent voltage.
• Low distortion.
• 3 kinds of package types
LM386 (8 Dip), LM386S (9 Sip), LM386D (8 Sop)

9 SIP

ORDERING INFORMATION

SCHEMATIC DIAGRAMS
GAIN

SAMSUNG SEMICONDUCTOR

Package

LM386N

8 DIP

LM386S

9 SIP

LM386D

8 SOP

Operating Temperature

- 20·C -

+ 70·C

GAIN

+INPUT

c8

Device

o:

LEFT (LM386/D)
RIGHT (LM386S)

613

I

LINEAR INTEGRATED CIRCUIT

LM386IS/D
CONNECTION DIAGRAM
(LM386ID)

(LM386S)

lOP VIEW

GAIN

-IN

+IN

GND

Vo

Vee

BY PASS GAIN

Fig. 3

Fig. 2

ABSOLUTE MAXIMUM RATINGS (Ta = 25°C)
Characteristic

Symbol

Supply Voltage

Vee
LM386

Power Dissipation

Value

Unit

15

V

660

LM386S

Pd

500

mW

300

LM386D
V,
Topr
T"g

Input Voltage
Operating Temperature
Storage Temperature

±0.4
-20-+70
-40-+125

V
·C
~C

ELECTRICAL CHARACTERISTICS
(T.=25·C, Vcc =6V, RL = 80, f=1KHi, unless otherwise sp.eclfied)
Characteristic

Symbol

Quiescient Circuit Current

Icc

Output Power

Po

Voltage Gain (D·Type)

Av

Bandwidth (D·Type)

BW

Total Harmonic Distortion
(O·Type).

THD

Input Resistance

R,

Input Bias Current

Ib

c8

Min

Typ

Max

4

8

Vcc = 6V, THD=10%

250

325

mW

Vcc=f!V, THD=10%

500

700

mW

Test Conditions
V,=O

Pins 1 and 8 Open

26

10",F from Pin 1 to 8

46

Unit
mA

dB

Pins 1 and 8 Open

300

10",F from Pin 1 to 8

60

Po = 125mW, Pins 1 and 8 Open

0.2

%

50

KO

250

nA

Pins 1 and 8 Open

SAMSUNG SEMICONDUCTOR

KHz

.

614

)

LINEAR INTEGRATED CIRCUIT

LM3861S/D
TYPICAL APPLICATIONS (LM386ID)

Low Distortion Power Wienbridge Oscillator

Amplifier with Gain;:50 1(34' dB)

390

vee
,lice

1,2K

ELDEMA
CF·S·2158

,

311-15mA

I

Rl

I
I

=r=0'os"

RL

tm

10

Cl

I

1=

Fig. 4

Fig. 5

Square Wave Oscillator

1

2"C1 VR1R2
I:: 1KHzIAS SHOWN

Amplifier with Bass Boost

I

Vee

vee

1--"1

Vee

>.:,.:.tIHf-_-GVO
RL

250#

~----~--~,+~~r-~VO

1
I
I

..l. 0.o5#

RL

10

Fig. 7

Fig. 6
AM Radio Power AmpllTIer

81l
SPEAKER

Fig. 8

c8

SAM.SUNGSEM.ICONDUCTOR

615

LINEAR INTEGRATED CIRCUIT

LM386/S/D
TOTAL HARMONIC DISTORTION-OUTPUT POWER
10.

TOTAL HARMONIC DISTORTION-FREQUENCV
2.0

III

1.8

Vcc-6V

r-

RL-BO

1

I::

1. ,K Z

r:

~:
l
~ 0.4

1

0.1

0.001
~

A,.28dB

I

/

f-

II

1

--

"'-

20

50

100

200

~

20

1K

2K

51<

10K 20K

I'!;:!I

i

5

~

4

V1*O

_r-

it:
Il

I1

--~

~

500

QUIESCENT CIRCUIT CURRENT-stIPPLY VOLTAGE

1\

01.1.0

V

V

1"'- t--.

I (Hz), FREQUENCY

'i

<40

"
~
g 30

cc.••0)

(W): OUTPUT POWER

l,Hl~

60

:c

Po-126n'tN

0.

1.0

VOLTAGE GAIN-FREQUENCY
60

!

RL_80

0.. 2

I0.

I

Vcc_fN

-

.l!

10.

1
100

lK

10K

10

1M

lOOK

11

12

Vee (VI, SUPPLY VOLTAGE

I (Hz), FREQUENCY

OUTPUT VOLTAGE SWING-SUPPLY VOLTAGE

:FREQUENCY RESPONSE WITH BASS BOOST
''0
26

5

1/ 1\

4

J

r\

\

+f
1

1'-

9

............ .........

8
10

11

Vee (V), SUPPLY VOLTAGE

c8
I

SAMSUNG SEMICONDUcroR

12

7
20

50

100

200

500

1K

2K

5K

10K 20K

t(Hz), FREQUENCY

616

PACKAGE DIMENSIONS

TO·92

Unit mm

I

4.33
4.83
/

I

4.33
4.83

--,

4'~1
5.15
m
3.56

1.80
TYP

TO·3P

Unit: mm

1.95
2.20

TYP
19.75

37.66
38.68

o

1!.n""""F"'i""""'T"'F~-+3.27

3.53

I

/
4.12
5.01

2.39
TYP

Unit: mm
~

II

.

1.40

6.12
6.62

o

0

3.97
4.23
2.08
2.33

12.72
13.48

0.45
I

It-..j
I

c8

/

'\

TO·220

8.94
9.44

20.2~

13.00
14.02

3.00
TYP

1/J3.61
TYP...J

4.55
5.05

2.79
3.04
1.75
2.25

I!~I

g::

1.50TYP--!

3'46~n1'02 TYP

15.55
16.05

8.25
8.75

~
3.22

13.97
14.97

~Il

3.35
3.85

'.

II

~

3.96
.

I

"

"

------

0.56
I,
1.27TYP---jr---t--_-,:=2.5:;,:-4
I
TYP

0.88
1.14

5.59
6.10

I

-

2.16

1/J3.20

Unit: mm

I

I

~:::[

TQ.92L

10.87
TYP

1----;;.~45;:.p

-i I

0.55
0.71

SAMSUNG SEMICONDUCTOR

0.55

619

II

,

'

'"'PACKAGE DIMENSIONS

Unit: mm

7 SIP

21.59
22.10

21.59
22.10

0

6.68
7.18

~
TYP

~ --t~~
0.71

Unit: mm

8 SIP

1.27
1.78

3.30
3.81

~.~

6.09

--11

0.20
0.30

0

TYP
~

6.68
7.18

r- --II

3,30
~3.81
1.27
1.78

I
0.45
0.71

~.~

6.09

--11

0,20
0.30

c {~~~~3)]12,75
c:
_ 3,25

Unit: mm

9 SIP

10 SIP HIS

21.59
22.10

2.54

TYP

I

0,51

I~oo
7~,!

a
~-11 0.45
0.71

3.81
1.27
1.78

TYP

~.~

6.09
0.51

TYP

_11 0.20

1]2.75
3.25

c8

Unit: mm

SAMSUNG SEMICONDUCTOR

0.30

~
~
TYP

0.41
0.61

25.15
25.65

620

PACKAGE DIMENSIONS

Unit: mm

12 SIP HIS

Unit: mm

8 DIP

R1.78

TYP ~t±r------:br1

I

0.58
TYP

o

8.95
9.45

0-10·

I

.y~37

0

7.87

0.20
0.30

.

~
254

~~::::~:3CI3.25

L....~~~~:---~-111:-.l3.75
,29.35
.

TIP

29.85

Unit: mm

12 DIP HIS

0.51

L----~1.0=2

14 DIP

Unit: mm

~

I
]09
6.60

0

I

IL

0-10·

19.35
19.85

4.83
5.33

6.361
0.56

'~4.05
~ 4.55
2.92
_
3.42

I~I

1.02
1.52

dOI~
~

75

0.45

~1381
--L 4.31
/

~ ~
TYP

c8

0.36
0.56

I~

3.30
3.81
0.5.1
1.02

SAMSUNG SEMICONDUCTOR

2.92
3.43

0.51
1.02

621

I

PACKAGE DIMENSIONS

Unit mm

14 DIP HIS

16 DIP

Unit mm

0'-10·

:J-

~2.10

I

1--t-6::':.2~4 0.35
0.45

0-10·

I

II: : : : : : : ][~:~~

TYP [[E.37
7.87
5.74

19.15
19.65

;;;L,

r

~f1.52

~

l!Lt~71
-~
0.30

4.01
1r--_-==-..,_-+---+-4.51 ,
F+==Fr---f-3.83
4.33

0.51
R'0.79 1.02
TYP

Unit: mm

16 DIP HIS

~-1
7'07'

27.57

2.54

I I

~

c8

II

r- --;

4.85
5.35

0.36

'0.56

SAMSUNG SEMICONDUCTOR

~

r-------,-=-'-+'4.31

}~
~
~u ~U~Ui

2.92
3.43
0.51
1.02

Unit: mm

1,8 DIP

4.31
~'3"

.::-:::-=t~~.51
-L

TYP

0.56

1.02

622

,

.'

PACKAGE DIMENSIONS

20 DIP

.unit: mm

26.36
26.87

,

0-1'0·

"

J

II: :0: :::: : ~ ]I]::~ O~
~

I•

1.02
1.52

r
~0.~30-~
0.20

3.81
4.31

""'''''=='--'-2.92
3.43

24 DIP

I.

0.51
1.02

Unit: mm

I

31.37

Unit: mm

22 DIP

I

26.36
26.87

I

0-10·

L- .

G~::::::~][:
--11

1.02
1.52

m]:;
7

0.20

*"0.30~~

~3.81
4.31

II

254

TYP

II

n.,..

-----j~
0.56

24 SKINNY DIP

~

3.43_
0.51
_. _
_
1.02

Unit mm

0-10·

~:::
~~~:::
~
:~:~:
[::~~::::~:n~~n:
.
¥
7
.

1.02
1.52

,
~0.2~0_--.J-,

I~

,

~~
1.52

0.20
0.30

0.30

6iJOijQ~~ 4.57

VVVVVVVVVVVt
2.54
TYP

c8

II-

--11 o.J.1
0.3~ ~
3.43
5.07

0.51
1.02

SAMSUNG SEMICONDUCTOR

623

PACKAGI: DIMENSIONS

Unit: mm

28 DIP

I;~:~

Unit: mm

28SDIP

1-

I·

~~::::::::~]f~
~
II
7
1.02
1.52

0.20
0.30

5.15
5.65
2.92
3.43 1.27
1.77

0.51
1.02

Unit:·mm

30 SDIP

27.22

Unit: mm

40 DIP

0-10·

.-L

27.72

~

I

52.19
52.70

I

0-10·

l--

~::~::::::::::~::] !~~:~~ ~~~:~~
~~~~~~~~];a:~:
~~ ~
nnn

1.52

hooooonooooonoU
rrmn~

rrn VV11

5.15
5.65

~~ .~~
1~ 1.27
TYP
0.56 L-----:-;1.7=7

c8

.

0.30

SAMSUNG SEMICONDUCTOR

. II 1.02

111:52

0.20
0.30

~.

r--------,-+

5.07

~T2.92
I
r-- ----r---0:56 '---343
.
2.54
TYP

~u.JL·. 0.36

0.51
1.02

624

PACKAGE DIMENSIONS

Unit: mm

40 SDIP

36.04
36.54

rno:fD

mn

o

D0

h3.34·
~3.84

14.99
15.49

1I;:;crn"jj"'i'ffi"jiEi!:jffi~11n:;;:;rn1-n:;!1.02·

o.~o

1.52

0.20

7

Unit: mm

42 DIP

I ;;;gl· oJ:
[~:::::::::::~::U:~;
~~
¥

Ur

0.20
0.30

1. 52

4.57

~~~~~~~~IIt~

~TU ~

254
II
~ I--

Unit: mm

8 SOP

0.41
0.79

I 036
--j~

Unit: mm

14 SOP

0]
.

,37
4.62

o

W!ih
II

1.27
TYP

c8

,

,

i

i

--JI
0.36

051
1.47
1.73

3.43 0.51
1.02

~h-

0.20

I

'j

==----.-

~Tg:;~

6.10

~ 6.60

I

O~

0.36
0.51

--l~
1/

0.20

SAMSUNG SEMICONDUCTOR

~1.47
"
1.73
1.27
TYP

625

I

.PACKAGE DIMENSIONS

Unit: mm

16 SOP

~

0.10

0.41
0.79

1H-

0.2mi~lM!

~J1:~~ ~ it; ~:~
I~

. 0.35
0.51

Unit: mm

20 SOP

6.86
7.11

mT

~

I

~_ _ _f'i'i"'lill-L

-II

I

1.27
TYP

lil.47
1.73

I

24 SOP

Unit: mm

T
7.54
7.80

0.35

0.51

0.10
0.20

1.90

1.27
TYP

28 SOP

Unit: mm

0.41
0.79

. I '-II

0.20

W!Llr
..
--l

~I-- .
10:11

,

8.89
9.40

9.73
0.10 10.24
0.20

I 0.10
0.20

ciS SAMSUNG SEMICONDUCTOR

0.41

(.::~:: ::::;]
I

.I~'
0.51

I~0'79
7.54
7.79

0.10
0.20

10.18
10.69

~~
0.30

626

PACKAGE DIMENSIONS

Unit: mm

16 ZIP

Unit: mm

19 ZIP

24.15
24.65

~I

6.86
7.36

01

2i1J[
1.14

I

1~~~~~~~~n~~~~~~~~ g~

I

1--_~22~.65::-_--I 2.92
23.15

2.85

~f3.35
~OA1
0.61

TYP

T()'92

368

IT
0.31

-II

I

.

0.46

~
?<;A

TYP

2.85

~~
~~ _II
0.41
TYP
0.61

I

Unit: mm
458

(KA33V On Iy)

,,

"

-------1

14.58

2

ill
14.5

It~-

1.27

!\

3.56

'/

\ 1 2

11.02

IJ
3.60

1. Anode

c8

2. Cathode

SAMSUNG SEMICONDUCTOR

627

NOTE

•

SALES OFFICES/MANUFACTURER'S REPRESENTATIVES
1. U.S.A
SALES OFFICES
. CALIFORNIA
201 East Sandpoint
Suite 220 Santa Ana 92707
714-662-3406
2700 Augustine Drive
Suite 198 Santa Clara 95054
408-727-7433

ILLINOIS
901 Warrenville Rd.
Suite 120 UsIe, 60532-1359
312-852-2011

TEXAS
1 5851 Dallas Parkway
Suite 745
Dallas 75248-3307
214-239-0754

MASSACHUSETTS

NORTH CAROLINA

20 Burlington Mall Road
Suite 205 Burlington 01803
617 -273-4888

3200 Nothline Ave
Suite 501G
Forum VI Greensbor.o, 27408
919-294-5141

MANUFACTURER'S REPRESENTATIVES
ALABAMA

COLORADO

EMA

ELECTRODYNE

1200 Jordan Lane, Suite 4
Jordan Center
Huntsville 35805
205-536-3044

2620 S. Parker Road
Suite 11 0 Aurora 80014
303-695-8903

ARIZONA

CONNECTICUT

HAAS & ASSOC., INC.

PHOENIX SALES

7505 East Main
Suite 300
Scottsdale 85252
602-994-3813

257 Main Street
Torrington, 06790
203-476-7709

CALIFORNIA
SYN PAC
3945 Freedom Circle Suite 650
Santa Clara 95054
408-988-6988

WESTAR REP COMPANY
1 801 Parkcourt Place
Suite 1030 Santa Ana 92701
714-835-4711

QUEST-REP, INC.
San Diego, CA.
61 9-546-1 933

CANADA
TERRIER ELECTRONICS
145 The West Mall
Etobicoke, Ontario M9C tC2
416-622-7558

ciS

SAMSUNG SEMICONDUCTOR

II

GEORGIA
EMA
6695 Peachtree Industrial Boulevard
Suite 101 Atlanta 30360
404-448-1215

FLORIDA
MICRO ELECTRONIC COMPONENTS
989 Woodgade Dr
Palm Harbor, 33563
813-784-8561

ILLINOIS
IRI
8430 Gross POinte Road
Skokie 60076
312-967-8430

631

.

SALES OFFICES/MANUFACTURER'S REPRESENTATIVES

INDIANA

OHIO

STB & AssociATES

J.N. BAILEY & ASSOCIATES

3003 E. 96th $treet
Suite 102 Indianapolis 46240
311-844-9227

1 3071 Old Dayton Road
New Lebanon 45345
51>3-687-1325
1667 Devonshire Drive
Brunswick'44212
216-273-3798
2679 Indianola Avenue
Columbus 43202
614-262-7274

MICHIGAN
C.B. JENSEN & ASSOC.
2145 Crooks Road
Troy 48084
313-643-0506

MARYLAND
. ADVANCED TECHNOLOGY SALES
809 Hammonds Ferry
Lithicum 21 090
301-789-9360

MASSACHUSETTS
Contact local sales, office

MINNESOTA
COMSTRAND INC
2852 Anthong Lane South
Minneapolis, 55418
612-788-9234

NEW JERSEY
NECCO
2460 Lemoine Avenue
Ft. Lee 07024
201-4611-2789

NEW MEXICO
Contact local sales oIfie8
NORTH CAROLINA
Contact local sales office

OREGON
EARL & BROWN
7719 S. W. Capitol Highway
Portland 97219
603-245-2283

PENNSYL VANIA
RIVCO JANUARY, INC.
78 South Trooper Road
Norristown 1 9403
215-631-1414

SOUTH CAROLINA
EMA
210 W. Stone Avenue
Greenville, 29609
803-233-4637

TEXAS
VIELOCK ASSOCIATES
720 E. Park Boulevard
Suite 102 Plano 75074
2.14-881-1940

UTAH
ELECTRODYNE
2480 South Main Street
Suite 1 09 Salt Lake City 8411 5
801-486-3801

WISCONSIN
IRI
631 Mayfair
Milwaukee 53226
414-259-0965

WASHINGTON

NEW YORK

EARL & BROWN

NECCO

2447-A 15200 Avenue, N.E.
Redmond 98052
206-885-5064

2460 Lemoine Avenue
Ft. Lee 07024
201-4611-2789

.·cR

SAMSUNG SEMICONDUCTOR

632

SALES OFFICES/MANUFACTURER'S REPRESENTATIVES
2. EUROPE
W/GERMANY

·BYTECH LTD

SILCOM ELEKTRONICS

2 The Westem centre,
Western Road.
Bracknell Berkshire RG121RW.
Tel: Sales 0344 482211,
Accounts/Admin, 0344 424222
Tlx: 848215

Neusser Str. 336-338
D-4050 MOchengladbach
Tel: (02161) 60752
TIx:852189

MICRONETICS VERTRIEB5GESELLSCHAFT ELEKTRONISCHER
BAUELEMENTE and SYSTEME GmbH
Weil der Stadter StraBe 45
7253 Renningen 1
Tel: (07159) 6019
Tlx: 724708

RAPID SILICON
Rapid House Denmrak Street
High Wycombe Buckinghamshire HP 11 2 ER
Tel: 0494 26271;
Sales hot line; 0494 442266
Tlx: 837931
Fax: 0494 21860

STEATITE ELECTRONICS LTD.
Laatzener Str. 1 9
Postfach 721226
30000 Hannover 72
Tel: (0511) 865075
Tlx: 923509
Fax: 876004

ZEPHYR HOUSE WARING STREET.
WEST NORWOOD LONDON SE279 LH
Tel: (01) 670-8663
Tlx: 892425
HAGLEY HOUSE HAGLEY ROAD
EDGBASTON BIRMINGHAM B168CW
Tel: (021) 454-2655
TIx: 337046

ASTRONIC GmbH

SWEDEN

Winzerer Str. 47d
8000 MOnchen 40
Tel: (089) 309031
Tlx: 521687
Fax: (089) 3006001

NORDISK ELEKTRONIK AB

ING. THEO HENSKES GmbH

FRANCE
ASiAMOS
Batiment EVOLIC 1
155, Boulevard de Valmy
92705 Colombes, France
Tel: (1) 47601255
Tlx: 61 3890F
Fax: (1) 47601582

UNITED KINGDOM
KORD DISTRI.BUTION LTD.
Watchmoor Road, Cambertey
Surrey GU 153AC
Tel: 0276 685741
Tlx: 859919 KORDIS G.

c8

SAMSUNG SEMICONDUCTOR

Huvudstagatan 1 Box 1409
5-17127 Solna
Tel: (08) 7349770
Tlx: 10547
Fax: (08) 272204

I

. SWITZERLAND
PANATEL AG
Hardstra8e 72
. CH-5430 Wettingen Zurich
Tel: (056) 275275
Tlx: 58068
Fax: (056) 271924

FINLAND
INSTRUMENTARIUM ELEKTRONIIKKA
P.O. Box 64, Vitikka
SF-02631 Espoo, Helsinki
Finland
Tel: (358) 05284~0
Tlx: 124426
Fax: (358) 0524986

633

SALES OFFICEs/MANUFACTURER'S REPRESENTATIVES

AUSTRI~

ITALY

ABRAHAMCZIK + DEMEL
G••mbH • CO. KG

MOXEL S.P.A.

Eichenstra8e 58-64/1
A-1"120 Viema
Tel: (0222).857661
T1x: 134273
Fax: 833583

BELGIUM
NEWTEC INTERNATIONAL
Chaussee de Louvain 186
1940 WoIuwe-'St-Etlenne
Leuvensesteenweg 186
~ 940-Sint-Stevens-WoIuwe
Tel: (02) 7250900
Tlx: 25820
Fax: (02) 7250813 .

NETHERlANDS
BV HANDELMIJ. MALCHUS
Fokkerstraat 511-513
. Postbus 48
NL-3100 AA Schiedam
Tel: (010) 373777
Tlx: 21598

=8

SAMSUNG SEMICONDUCTOR

20092 Cinisello Balsamo (MI)
Via C. Frova. 34
Tel: (02) 612,,0521
Tlx: 352045
Fax: (02: 617.2582

DIS. EL S.R.L.
10148 Torino
Via Ala eli Stura 71/18
Tel: (220) 1522345
Tlx: 215118

SPAIN
SEMICONDUCTORES S.A.
'Ronda General Mitre, 240
Barcelona-6
Tel: (93) 2172340
T1x: 97787 SMCD E
, Fax: 2175698

SANTOS DEl VALLE, S.A.
GaIiIeo, 54, 56
28015 Madrid
Tel: (,,1) 446814H44
Tlx: 42615 LUSA E.

634

SALES OFFICES/MANUFACTURER'S REPRESENTATIVES
3. ASIA
HONG KONG

JAPAN

AV. CONCEPT .

ADO ELECTRONIC INDUSTRIAL CO., LTD.

Hunghom Commercial Centre,
Room 708, Tower A.·7/F
37-39, Ma Tau Wai Road
Hunghom, Kowloon, Hong Kong
Tel: 3-629325"'6, 3-347722"'3
T1x: 52362 ADVCC HX
Fax: 852-3-7234718

7th FL., SASAGE BLDG. 4-6 SOTOKANDA
2-CHOME CHIYODA-KU, TOKYO 101, JAPAN
Tel: 03-257-1618
Fax: 03-257-1579

PROTECH
FLAT 3 10lF WING SHING IND, BLDG
26 NGFONG ST, SANPOKONG
KOWLOON, Hong Kong
Tel: 3-255106
T1x: 38396 PTLD HX
Fax: 852-3-7988459

TRIATOMIC
1004 President Commercial Centre,
602-608, Nathan Road, K9wloon. Hong Kong
Tel· 3-880151"'2, 3-886184"'5
Tlx: 36631 TRIAT HX
Fax: 852-3-884026

MATSUDA
6/F CHUNG PAK Commercial BLDG

2 Cho Yuen SI. Yau Tong Bay
Kowloon, Hong Kong
Tel: 3-7276383
Tlx: 42349 MAZDA HX
Fax: 852-3-7989661

INTERCOM PO INC.
IHI 8LDG, 1:6-7, SHIBUYA, SHIBUYA-KU:
TOKYO 150 JAPAN
Tel: 03-406-5612
Fax: 03-409-4834

CHEMI·CON INTERNATIONAL CORP.
MITSUYA TORANOMON BLDG.
22-14, TORANOMON 1 CHOME
MINATO-KU TOKYO 105, JAPAN
Tel: 03-508-2841
Fax: 03-504-0566

TOMEN ELECTRONICS CORP.
1-1, USCHISAIWAI-CHO 2 CHOME
CHIYODA-KU TOKYO, 100
. Tel: 03-506-3473
Fax: 03-506-3497

DIA SEMICON SYSTEMS INC.
WACORE 64 1-37-8 SANGENJAYA
SETAGAYA-KU TOKYO 154 JAPAN
Tel: 03-487-0386
Fax: 03-487-8088

SINGAPORE

JERS

GEMINI ELECTRONICS PTE LTD.

Flat C-l, 13th Floor, Hoi Bun Industrial Bldg.
6 Wing Yip Street, Kwun Tong, Kowloon,
Hong Kong
Tel: 3-418311-8
Tlx: 55450 JERSE HX
Fax: 852-3-7598599

100, UPPER CROSS STREET
#09-08 OG BLDG. SINGAPORE 0105
·Tel: 65-5351777
Tlx: RS 42819
Fax: 65-5350348

TAIWAN
YOSUN INDUSTRIAL CORP.
MIN SHENG COMMERCIAL BUILDING
10F., No. 481, MIN-SHENG EAST RD.,
TAIPEI, TAIWAN, R.O.C.
Tel: 501-0700 (10 LINES)
Tlx: 26777 YOSUNIND
Fax: (02) 503-1278

II

INDIA
MURUGAPPA ELECTRONICS LTD.
PARRRY HOUSE' 3rd floor 43 Moore Street
MADRAS 600 001 India
Tel: 21019/31003
T1x: 041-8797 HIL IN.

KENTOP ELECTRONICS CO., LTD.
5F-3, 21st CENTURY BLDG.,
NO. 207, TUN-HWA N. RD., TAIPEI
Tel: (02) 716-1754, 716-1757
Fax: (02) 717-3014

c8

SAMSUNG SEMICONDUCTOR

635

SALES OFFICES/MANUFACTURER'S REPRESENTATIVES
4. KOREA
. NAEWAE ELECTRIC CO., LTO.
Room 403, 2200ng Sumln .Bldg,
. #16·1, Hangangro·2ka, Yongsanku,
Seoul Korea.
Tel: 701·7341"'5
Fax: 717·7246

SAMSUNG
LIGHT-ELECTRONICS CO., LTD.
149·Jang Sa Dong
Jongroku, Seoul Korea
Tel: 744·2110,269·618718
Fax: 744·4803

NEW CASTLE
SEMICONDUCTOR CO., LTD.
12.3·1, Joo Kyo Dong
Joongku, Seoal Korea
Tel: 274·3220, 3458

HANKOOK SEMICONDUCTOR
1131·9 Kurodong, Kuroku,
Seoul Korea
Tel: 868·0277"'9
Fax: 868·4604

SEGYUNG ELECTRONICS
182·2 Jang Sa Dong
Jongroku, Seoul Korea.
Tel: 272·6811 "'6
Fax: 273·6597

c8

SAMSUNG SEMICONDUCTOR

636

•• SAMSUNG
•••
•••
••

Semiconductor & Telecommunications
HEAD OFFICE :
9/10FL . SAMSUNG MAIN BLDG .
250, 2-KA , TAEPYUNG-RO,
CHUNG-KU , SEOUL , KOREA
CP .O BOX 8233

TELEX : KORSST K27970
TEL (SEOUL) 751-2114
FAX : 753-0967

BUCHEON PLANT:
82-3, DODANG-DONG ,
BUCHEON , KYUNGKI-DO , KOREA
CPO . BOX 5779 SEOUL 100

TELEX : KORSEM K28390
TEL (SEOUL) 741-0066 , 662-0066
FAX : 741-4273

KIHEUNG PLANT :
SAN #24 NONGSUH-RI , KIHEUNG-MYUN
YONGIN-GUN , KYUNGKI-DO, KOREA
C.P.O. BOX 37 SUWON

TELEX : KORSST K23813
TEL (SEOUL) 7410620/7
FAX 741-0628

GUMI BRANCH :
259, GONDAN-DONG, GUMI ,
KOREA

KYUNGSANGBU~DO,

TELEX : SSTGUMI K54371
TEL : (GUM I) 2-2570
FAX (GUMI) 52-7942

SAMSUNG SEMICONDUCTOR INC .:
3725 NORTH FIRST STREET
SANJOSE, CA 95134-1708, USA

TEL : (408) 434-5400
TELEX : 339544
FAX : (408) 434-5650

HONG KONG BRANCH :
13FL. BANK OF AMERICA TOWER
12 HARCOURT ROAD , HONG KONG

TEL : (5) 21-0307/9, 21-0300 , 23-7764
TELEX : 80303 SSTC HX
FAX: (5) 84-50787

TAWAN OFFICE :
RM 1102, I.T. BLDG , NO. 385
TUN-HWA S, RD , TAIPEI , TAIWAN

TEL : (2) 777-1044/5
FAX : (2) 777-3629

SAMSUNG JAPAN CO :
RM 3108, KASUMIGASEKI BLDG.
2-5, 3-C HOME KASUMIGASEKI
CHI YODA-KU , TOKYO , 100 JAPAN

TEL (03) 581 -1 816/7585
TELE X: J24244
FAX : (03) 581-7088

SAMSUNG SEMICONDUCTOR EUROPE GMBH:
WESTEND SAVIGNY ST RA SSE 5
6000 FRAN KFURT, MAIN1 , WIG

TEL : 001-496-975-6006-0
001-496-974-7898
TELEX : 4170878 SSTF D
FAX : 001-496-975-) 558

SAMSUNG (U .K.) LTD .:
6 FL. VIC TORIA HOUSE SOUTHAMPTON
ROW W.C. 1 LONDON . ENGLAND

TELEX : 297987 STARS LG
TEL: 831-6951/5
FAX : (01) 430-0096

PRINTED IN KOREA
APRIL , 1988



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