1988_TI_Telecommunications_Circuits_Data_Book 1988 TI Telecommunications Circuits Data Book
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-I!1TEXAS
INSTRUMENTS
Telecotntnunications
Circuits
Transmission, Switching, Subscriber,
and Transient Suppressors
989
198811989
Linear Products
General Information
Telecommunications Circuits
Designer's Information
Application Reports
Mechanical Data
-
Telecommunications Circuits
Data Book
~
TEXAS
INSTRUMENTS
--
IMPORTANT NOTICE
Texas Instruments (Til reserves the right to make changes to or to
discontinue any semiconductor product or service identified in this
publication without notice. TI advises its customers to obtain the latest
version of the relevant information to verify, before placing orders,
that the information being relied upon is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with TI's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
necessary to support this warranty. Unless mandated by government
requirements, specific testing of all parameters of each device is not
necessarily performed.
TI assumes no liability for TI applications assistance, customer product
design, software performance, or infringement of patents or services
described herein. Nor does TI warrant or represent that any license,
either express or implied, is granted under any patent right, copyright,
mask work right, or other intellectual property right of TI covering or
relating to any combination, machine, or process in which such
semiconductor products or services might be or are used.
Revised: June 1988
Copyright @ 1988. Texas Instruments Incorporated
INTRODUCTION
In just over 100 years, technical advances in the telecommunications industry have made the modern telephone
system one of the true wonders of the world. We can now communicate with any part of the world in a matter
of seconds. The modern telecommunication system uses digital-transmission techniques, microelectronics,
network transmission, and speech-signal processing. The system is controlled by the largest network of
interconnected and cooperating computers in the world. This system is on the leading edge of a
telecommunication revolution that is making the home and business environment very similar. Remote banking,
automated brokerage transactions, home-security monitoring from a distance, food preparation from the office,
and robot control will provide the home with technical capabilities similar to those experienced by industry.
Texas Instruments (TI), because of its broad base of reliable multipurpose integrated circuits, has become a
versatile and proven leader for components in the telecommunication industry. The TI capability in circuit design,
process technology, end automated manufacturing of telecommunications devices has provided the switching,
terminal, and transmission components required by the telecommunication industry. To integrate the analog,
digital logic, and memory function on one chip, TI has developed the TCM series of telecommunication integrated
circuits. TI uses the following processes and technologies:
1. Bipolar, MaS, and mixed (i.e., Bipolar and MaS on a single chip).
2. BIDFET'" process, which combines low-power logic with high-voltage circuits and requires fewer external
components because of its variable packing circuitry capability.
3. Silicon-Gate CMOS technology, which allows the interconnection of analog and digital on one chip.
New suface-mount packages (8 to 84 leads) used in the TCM series of integrated circuits include standard DIPs,
chip carriers, small outline plastic packages, and quadriform flat packages, which optimize board density with
minimum impact on power dissipation. Telecommunication test equipment with handlers and automated assembly
bonders strengthen the production capabilities to provide a lower cost to performance ratio. TI continues to
improve quality and reliability of telecommunication integrated circuits by improving materials, processes, test
methods, and test equipment. In addition, specifications and programs are continuously updated. Quality and
performance are monitored throughout all phases of manufacturing.
The telecommunication devices in this data book support central office products, subscriber circuits, transmission
circuits, modems, and the digital-signal processor requirements. The demand of the telecommunication industry
for growth products has made it practical to develop an entire wLaw Codec with filter on a single chip. This
chip will replace 50 general-purpose integrated circuits.
The rapid growth of the semiconductor content in the telephone system has dramatically altered the protection
required against such hazards as lightning and accidental connection to ac lines. Because of faster responses,
well defined voltage levels, and reliable operation, previous protection methods are no longer adequate. TI has
developed a transient suppressor (TISP) series of devices that provide shunt protection against transient voltages
(static, lightning), and protection against damage caused by induction or accidental connection to an ac source.
To achieve a high level of system integration and performance for digital signal processing applications, TI offers
the analog interface circuits combining high-resolution AID and D/A converters, programmable filters, digital
control and timing circuits, and programmable input amplifiers and multiplexers.
BIDFET is a trademark of Texas Instruments Incorporated.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75285
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The alphanumeric index in this data book provides a means of quickly locating the device type. The selection
guide includes a description of each device and contains information on key parameters and packaging. The
glossary describes the symbols, abbreviations, terms, and definitions used in this data book. The detailed data
sheets, quality and reliability assurance and the application reports complete the contents of the data book.
While this volume offers design and specification data only for Telecommunications components, complete
technical data for Analog Interface Circuits (AIC), Digital Signal Processing (TMS320 series), and all other TI
semiconductor products is available from your nearest TI Field Sales Office, local authorized TI distributor, or
by writing directly to:
Texas Instruments Incoroprated
LITERATURE RESPONSE CENTER
P.O. Box 809066
DALLAS, TEXAS 75380-9066
We sincerely feel that you will discover the new 1988 Telecommunications Circuits Data Book to be a significant
addition to your collection of technical literature.
vi
TEXAS ."
INSIRUMENlS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
General Information
1-1
Contents
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1-2
Page
Alphanumeric Index ..•.•..............•..............•...•..
Selection GUide .....•.......•..••...........•...•...••..•.•
Glossary ......................•....•.•.•.........•.......
1-3
1-5
1-11
ALPHANUMERIC INDEX
DEVICE
DS3680 ......................
TCM1501B: ...................
TCM1506B ....................
TCM1512B ....................
TCM1520A ...................
TCM1531 .....................
TCM1532 .....................
TCM1536 .....................
TCM1539 .....................
TCM2203 .....................
TCM2222 .....................
TCM2909 .....................
TCM2910A ...................
TCM2912C ...................
TCM2913 .....................
TCM2914 .....................
TCM2916 .....................
TCM2917 .....................
TCM29C13/TCM129C13 .........
TCM29C 14/TCM 129C 14 .........
TCM29C16/TCM129C16 .........
TCM29C17/TCM129C17 .........
TCM29C18/TCM129C18 .........
TCM29C19/TCM129C19 .........
TCM3105JE ...................
TCM3105JL ...................
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PAGE
2-3
2-13
2-13
2-13
2-7
2-13
2-13
2-13
2-13
2-21
2-29
2-37
2-37
2-57
2-71
2-71
2-71
2-71
2-93
2-93
2-93
2-93
2-115
2-115
2-129
2-129
DEVICE
TCM4204A ...................
TCM4205A ...................
TCM4207A ...................
TCM5087 .....................
TCM5089 .....................
TCM5092 .....................
TCM5094 .....................
TCM78808 ....................
TIL181 .......................
TISP1082 .....................
TISP2180 .....................
TISP2290 .....................
TISP3180 .....................
TISP3290 .....................
TISP4180 .....................
TISP4290 .....................
TISP7180 .....................
TISP7290 .....................
TISP8180 .....................
TISP8290 .....................
TISP9180 .....................
TlSP9290 .....................
TLC32040C ...................
TLC320401 ....................
TLC32041C ...................
TLC320411 ....................
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TeXAS 75265
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PAGE
2-141
2-141
2-141
2-161
2-167
2-173
2-179
2-185
2-205
2-209
2-215
2-215
2-219
2-219
2-223
2-223
2-227
2-227
2-231
2-231
2-235
2-235
2-237
2-237
2-237
2-237
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1-3
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1-4
SELECTION GUIDE
TELECOMMUNICATIONS
telecommunications circuits
DESCRIPTION
FUNCTION
TECHNOLOGY
SUPPLY
VOLTAGE
PRODUCT FEATURES
AMI or HDB3 encoding
Encoder/Decoder
NMOS
5V
AMIIHDB3
Transmission
TYPE
PKG
PAGE
c
TCM2222
16-Pin
2-29
-.;:
tV
J
Received signal
Zero to 3 MHz bit rate
Serial bipolar data rates
TCM2203
Equipment Line
Interface
Bipolar
5V
2B-Pin
...oE
diagnostics
up to 3 MHz
Low-Q clock extraction
o
2-21
J
Two ALBO taps with
42 dB range
.5
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...
CD
C
CD
Phase adjust for
recovered clock
CJ
Direct interface with
TCM2222
Provides wlaw
TCM2909
22-Pin
2-37
J.N
companding
Compatible with CCITT
recommendations
G.711 and G.712
Optional programmable
PCM
Interface
CODEC
NMOS
12 V.
±5 V
time-slot selection
Compatible with CCITT
recommendations
TCM2910A
24-Pin
2-37
J.N
G.711 and G.712
w255-Law encoding and8th-bit signaling
Optional programmable
time-slot selection
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012 •. DALLAS. TEXAS 76285
1-5
-
SELECTION GUIDE
telecommunications circuits (continued)
DESCRIPTION
FUNCTION
TECHNOLOGY
SUPPLY
VOLTAGE
Line Filter
PCM
Interface
NMOS
±5 V
PRODUCT FEATURES
TYPE
PKG
PAGE
High-pass transmit filter
for rejection of all lowfrequen"cy noise
6th-order low-pass
transmit filter
CCITT G. 172 compatible
AT&T D3/D4 compatible
Three-state PWRO + and
PWRO - outputs
TCM2912C
20-Pln
2-57
Synchronous, I'·Law,
A-Law coding
Variable data rate
Fixed data rate
1.536 MHz, 1.544 MHz,
2.048 MHz
Synchronousl
J
TCM2913
1-6
,.-Law, A-Law coding,
8th-bit signaling
Variable data rate
Fixed data rate
1.536 MHz, 1.544 MHz,
2.048 MHz
Synchronous, ,.-Law,
variable data rata
Fixed data rate
2.048 MHz MHz
Synchronous, A-law,
Variable data rate
Fixed data rate 2.048 MHz
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS. TEXAS 75286
2-71
J
TCM2914
24-Pln
J,
28-Pin
FN
2-71
TCM2916
16-Pin
2-71
asynchronous
COMBO
20-Pin
J
TCM2917
16-Pin
J
2-71
SELECTION GUIDE
telecommunications circuits (continued)
DESCRIPTION
PCM
Interface
Modem
FUNCTION
COM80
Bell 202/CCITT
V.23
TECHNOLOGY
CMOS
CMOS
SUPPLY
VOLTAGE
±5 V
5V
PRODUCT FEATURES
TYPE
PKG
PAGE
Synchronous, ,.-Lsw,
A-Lsw coding
Variable data rate
Fixed data rate
1.536 MHz, 1.544 MHz,
2.048 MHz
Svnchronous/
asynchronous
,..Lsw, A-Law coding,
8th-bit signaling
Variable data rate
Fixed data rate
1.536 MHz, 1.544 MHz,
2.048 MHz
Synchronous, ,..Law,
Variable data rate
Fixed data rate
2.046 MHz
Synchronous, A-Law,
Variable data rate
Fixed data rate
2.048 MHz
Low-cost speech band
OSP interface
,..Lsw encoding
Asvnchronous
Half-duplex operation up
to 1200 baud
Full-duplex operation
1200/150 baud,
reversible
TCM29C13
20-Pin
J,DW,
OY
2-93
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 85&012 • DALLAS. TEXAS 75285
TCM29C14
24-Pin
J,OW,
28-Pin
FN
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2-93
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TCM29C16
16-Pin
J,N
2-93
TCM29C17
16-Pin
J,N
2-93
TCM29C18
TCM29C19
16-Pin
2-115
TCM3105
16-Pin
J
N
2-129
1-7
SELECTION GUIDE
telecommunications circuits (continued)
DESCRIPTION
FUNCTION
TECHNOLOGY
SUPPLY
VOLTAGE
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Ringers
Telephone Tone
Ringer D.rivers
BIDFET
40-150
Vac
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Ring Detector
Tone Encoder
TTUMOS
Output
DTMF
Standard
BIDFET
CMOS
40-150
Vac
3.5-10 V
58 V
145V
Transient
Suppressor
Voltage
Suppressor
Bipolar
200 V
145V
200 V
1-8
PRODUCT FEATURES
TYPE
PKG
PAGE
Output Center Frequency
(Hz): 2000
Output Center Frequency
(Hz): 2000
Output Center Frequency
(Hz): 1250
Output Center Frequency
(Hz): 1250
Output Center Frequency
(Hz): 500
Output Center Frequency
(Hz): 500
Output Center Frequency
(Hz): 2000
TTUMOS output,
TCM1531
8-Pin
P
8-Pin
P
8-Pin
P
8-Pin
P
8-Pln
P
8-Pin
P
8-Pin
P
8-Pin
P
16-Pin
N
2-13
TCM15018
TCM1532
TCM1512B
TCM1536
TCM1506B
TCM1539
TCM1520A
transient protection
SPSTIDPST keyboard or
electronic input
Low impedance tone
output
Transmitter switch and
mute output DPST keyboard or electronic input
Keyboard active output
Breakover voltage to
common: 82 V max
Breakover voltage to
common: 180 V max
Breakover voltage to
common: 290 V max
Breakover voltage to
common: 180 V max
Breakover voltage to
common: 290 V max
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 86&012 • DALLAS, TEXAS 75286
TCM5087
TCM5089
TCM5092
16-Pin
N
TCM5094
2-13
2-13
2-13
2-13
2-13
2-13
2-7
2-161
2-167
: 2-173
2-179
TISP1082
T0220
2-209
TISP2180
T0220
2-215
TILSP2290
T0220
2-215
TISP3180
T0220
2-219
TISP3290
T0220
2-219
SELECTION GUIDE
telecommunications circuits (concluded)
DESCRIPTION
FUNCTION
TECHNOLOGY
SUPPLY
VOLTAGE
145 V
200 V
145 V
200 V
Transient
Suppressor
Voltage
Bipolar
145 V
Suppressor
200 V
145 V
200 V
Optocoupler
TTLCompatible
Bipolar
12 V
PRODUCT FEATURES
TYPE
PKG
PAGE
TISP4180
T0220
2-223
TISP4290
T0220
2-223
TISP7180
T0220
2-227
TISP7290
T0220
2-227
TISP8180
T0220
2-231
TISP8290
T0220
2-231
Breakover voltage to
TISP9180
T0220
2-235
common: 180 V max
Breakover voltage to
TISP9290
T0220
2-235
TIL181
6-Pin
CP-7
2-205
TCM4204A
24-Pin
2-141
TCM4205A
J
28-Pin
2-141
Breakover voltage to
common: 180 v max
Breakover voltage to
common: 290 V max
Breakover voltage to
common: 180 V max
Breakover voltage to
common: 290 V max
Breakover voltage to
common: 180 V max
Breakover voltage to
Peak high-voltage
isolation: 3_54 kV
Three selectable balance
.5
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C
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networks
TIL-
-
common: 290 V max
networks
Compatible
..Eo
Q)
common: 290 V max
Three selectable balance
Subscriber
Line Control
c
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Three auxiliary relay
CMOS
±5 V
outputs
Ground-start operation
TCM4207A
Flux-canceling option
Circuits
Two selectable balance
24-Pin
2-141
J
networks
Quad Telephone
Relay Driver
Converterl
Controller
Octal Receiverl
Transmitter
Bipolar
5 V,
-60 V
NMOS
5V
50~mA
output current
OS3680
14-Pin
2-3
TCM78808
O,J,N
68-Pin
2-185
capability
Programmable baud rates:
50 to 19,200
FN,
HA,HB
analog interface for digital signal processors
FUNCTION
TRANSFER
DYNAMIC
CHARACTERISTIC
RANGE
linear
14 Bits
High-Performance
Combo
RESOLUTION
14 Bits
SAMPLING
ON-BOARD
RATE
FILTERS
19.2 kHz
(Programmable)
Yes
(Programmable)
TYPE
PAGE
TLC32040 t
TLC32041 t
2-239
tTheTLC32040 and TLC32041 have two differential inputs for the 14 bit AID and a serial port input for the 14 bit D/A. The AID conversion
accuracy for this device is measured in terms of signal-ta-quantization distortion and also in LSB over certain converter ranges. Please
refer to the data sheet.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1-9
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1-10
GLOSSARY
ADC
Analog-to-digital converter. A converter that uniquely represents all analog input values within a specified
total input range by a limited number of digital output codes, each of which exclusively represents a fractional
part of the total analog input range.
Note: This quantization procedure introduces inherent errors of one-half LSB (least significant bit) in the
representation since, within this fractional range, only one analog value can be represented free
of error by a single digital output code.
AMI
Alternate Mark Inversion. A pseudoternary signal converting binary digits, in which successive "marks"
are normally of alternate positive and negative polarity but equal in amplitude and in which "space" is
of zero amplitude.
...
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Address
CD
The number dialed by a calling party that identifies the party called. Also a location or destination in a
computer program.
CJ
ALBO
Automatic Line Build Out. In digital transmission systems, a circuit that monitors the amplitude of the
received digital signal and, based on this information, automatically adjusts its gain and frequency response
to correct for the effects of the transmission line.
Aliasing
The occurrence of spurious frequencies in the output of a pulse-coded modulation (PCM) system or ADC
that were not present in the input due to foldover of higher frequencies.
Bell Tapping
The undesired activation of the ringer circuit of a telephone caused by dial pulses from a parallel telephone.
Also known as tinkling.
Bias (Asymmetrical) Distortion
Distortion affecting a binary modulation scheme whereby the actual mark or space has a longer or shorter
duration than the corresponding theoretical duration.
Bit Rate (BPS) Versus Baud Rate
For modems using voice grade telephone lines, the bit rate equals the data rate. The baud rate is the actual
number of times per second that the transmitted carrier is modulated or changes state.
BORSCHT
An acronym for the function that must be performed in the central office when digital voice transmission
occurs; Battery, Overvoltage, Ringing, Supervision, Coding, Hybrid, and Test.
Byte
A group of bits treated as a unit. Often equivalent to one alphabetic or numeric character.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75285
1-11
GLOSSARY
CCITT
International Telegraph and Telephone Consultative Committee. An international forum for establishing
communication system standards.
G) Central Office (COl
CD
::s
The switching equipment that provides local-exchange telephone service for a given geographical area'
and is designated by the first three digits of the telephone number.
CD
iS"
..3
Channel
0-
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An electronic communication path. In telecommunications, it is usually a voice bandwidth of 4,000 Hz .
Circuit
o·
::s
An interconnected group of electronic devices or, in telecommunications, the path connecting two or more
communications terminals.
C-Message Weighting
A noise weighting used to measure noise on a line that would be terminated by a 500-type telephone set
or similar instrument. The resulting noise reading is in dBrnC.
Codec
An assembly comprising an encoder and a decoder in the same unit. A device that produces a coded output
from an analog input, and vice versa.
Combo
A single-chip pulse-code-modulated encoder, decoder (PCM codec) and PCM line filter.
Common Battery
A system supplying direct current for the telephone set from the central office.
Compander
A contraction for a compressor-expander; a circuit that compresses the dynamic range of an input signal
and expands it back to almost the original form at the output.
Crossbar Switch
An electromechanical switching machine using a relay mechanism with horizontal and vertical input lines
(usually 10 to 20). Uses a contact matrix to connect any vertical to any horizontal.
Crosspoint
The element that actually performs the switching function in a telephone system. It may be mechanical
using metal contacts or solid state using integrated circuits.
Crosstalk
Undesired voice-band energy transfer from one circuit to another (usually adjacent).
Cutoff Frequency
The frequency above or below which signals are attenuated below a specified value by a circuit or network.
1-12
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TEXAS
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
GLOSSARY
DAC
Digital-to-analog converter. A converter that represents a limited number of different digital input codes
by a corresponding number of discrete analog output values.
Note: Examples of input code formats are straight binary, two's complement, and binary-coded decimal.
c
o
'+:;
Data
ca
..oE
--.
In telephone systems, any information other than human speech.
Dete Set
c
Telecommunications term for a modem.
ca
Decibel (dB)
Q)
A unit of measure of relative power, 10 log (P1 IP2). or voltage, 20 log (V1 IV21. in terms of the ratio of
two values.
C
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~
dBm
Decibels referenced to one milliwatt; used in communication work as a measure of absolute power values.
Zero dBm equals one milliwatt.
dBmO
Noise power referenced to or measured at a zero transmission level point (OTLP).
dBmOp
Noise power in dBmO, measured by a psophometer or noise measuring set having psophometric weighting.
dBrn
Decibels above reference noise. Rated noise power in dB referenced to one picowatt. Zero dBrn equals
-90 dBm.
dBrnC
Weighted noise power in dBrn, measured by a noise measuring set with C-message weighting.
dBrnCO
Noise power in dBrnC referenced to or measured at a zero transmission level point (OTLP).
dBW
Decibels referenced to one watt.
Decoder
Any device that modifies transmitted information to a form that can be understood by the receiver.
Demultiplexer
A circuit that distributes an input signal to a selected output line (with more than one output line available).
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1-13
GLOSSARY
Dial Pulsing
Transmission of address information by breaking a dc path; the number of breaks corresponds to the decimal
digit dialed.
G') DTMF
CD
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CD
Dual-Tone-Multi-Frequency. Use of two simultaneous voice-band tones for dialing.
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EIA
Electronic Industries Association. (2001 Eye Street, N.W., Washington, D.C. 20006)
Electromagnetic Spectrum
The total range of wavelengths or frequencies of electromagnetic radiation, extending from the longest
radio waves to the shortest known cosmic rays.
Encoder
Any device that modifies information into the desired pattern or form for a specific method of transmission.
ESS
Electronic Switching System. A telephone switching machine using electronics, often combined with
electromechanical crosspoints, and usually with a stored-program computer as the control element.
Exchange Area
The territory within which telephone service is provided for a basic charge. Also called the local calling area.
Equalization
The reduction of frequency distortion and/or phase distortion of a circuit by the introduction of networks
to compensate for the difference in attenuation, time delay, or both, at the various frequencies in the
transmission band.
FCC
Federal Communications Commission. A government agency that regulates and monitors the domestic
use of the electromagnetic spectrum for communications.
FCC Part 68
A government document describing the types of equipment that must be registered and the electrical and
mechanical standards to be met when connecting equipment to the public telephone network.
Fiber Optics
The process of transmitting infrared and visible light frequencies through a low-loss glass fiber with a
transmitting laser or LED.
FSK
Frequency-Shift Keying. A method of transmitting digital information that utilizes two tones; one
representing a high level, the other a low level.
1-14
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
GLOSSARY
Full Duplex
Simultaneous communication in both directions between two points.
..
Ground Start
t:
A method of signaling between two machines in which one machine grounds one side of the line and the
other machine detects the presence of the ground.
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HDB3
High-Density Bipolar Three-line code. See AMI.
Half-Duplex
A circuit that can carry information in both directions but not simultaneously.
Hybrid
In telecommunications, a circuit that divides a signal transmission channel into two channels (i.e., one
for each direction) or, conversely, combines two channels into one.
Instruction Code
Digital information that represents an instruction to be performed by a computer.
ISDN
Integrated Services Digital Network. A communication network capable of carrying digitized voice and
data multiplexed onto the public network.
Lineside
Refers to the portion of the central office that connects to the local loop.
Local Loop
The voice-band channel connecting the subscriber to the central office.
Longitudinal Balance
A measure of symmetry impedance of a balanced network. Improper longitudinal balance results in poor
common-mode rejection.
Loop Current
Flow of dc in the local loop. Indicates that a telephone is in use.
Loss
Attenuation of a signal due to any cause.
Mark
One of the two possible states of a binary information element. The closed circuit and idle state in a
teleprinter circuit. See Space.
MTS
Message Telephone Service. The official name for long distance or toll service.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 225012 • DALLAS. TEXAS 75265
1-15
GLOSSARY
Modem
A device to convert digital data into an analog signal and vice versa so that two electronic devices (e.g.,
a computer and a data terminal) may communicate over the telephone system. The word modem is a
contraction of modulator/demodulator.
G)
CD
:::J Multiplexer
CD
A device for accomplishing simultaneous transmission of two or more signals over a common transmission
medium.
!.
S'
.0-
Off-Hook
..s·
The condition that indicates the active state of a telephone circuit. The opposite condition is On-Hook.
3
I» PABX
Private Automated Branch Exchange. Small local automatic telephone office serving extensions in a business.
complex providing access to the public network.
:::J
Parallel Data
The transfer of data simultaneously over two or more wires or transmission links.
Parity
A bit that indicates whether the number of "ones" in a bit string is odd or even.
PBX
Private Branch Exchange. A telephone exchange serving an individual organization and having connection
to a public telephone exchange.
Period
The time between successive similar points of a repetitive signal.
Phase
The time or angle that a signal is delayed with respect to some reference position.
POTS
Plain Old Telephone Service. An acronym used by the telephone industry for conventional telephone service.
PSK
Phase Shift-Keyed modulation. A method of placing data of a carrier signal by modifying the phase of the
carrier wave.
Psophometric Weighting
A noise weighting recommended by the CCITI for use in a noise measuring set or psophometer.
PCM
Pulse-Coded Modulation. That form of modulation in which the modulating signal is sampled and then
quantized and coded, so that each element of information is represented in digital form by a serial bit stream.
1-16
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285
GLOSSARY
Quantizing Noise
An undesirable random signal caused by the error of approximation in a quantizing process. It may be
regarded as noise arising in the pulse-code modulation process due to the code-derived facsimile not exactly
matching the waveform of the original message.
c
o
'';:
Register
A storage element for one or more bits of digital information.
Ring
The alerting signal to the subscriber or terminal equipment. Also, the name for one conductor of the wire
pair comprising the local loop, designated by R.
as
..
..
E
....oc
'i
CI)
Ring Trip
C
During ring signaling, the detection of the off-hook condition and removal of the ring signal from the line
by the switch.
CI)
~
Serial Data
The transfer of data over a single wire in a sequential pattern.
Sidetone
That portion of the speaker's voice that is fed back to his receiver.
Simplex
A circuit that can carry information in only one direction (e.g., broadcasting.)
SLee
Subscriber Line Control Circuits. A family of CMOS LSI circuits which provide the hybrid, supervisor and
controlling functions in a single package.
sLie
Subscriber Line Interface Circuit. In digital transmission of voice, the circuit that performs some or all of
the interface functions at the central office. See BORSCHT.
Spece
One of the two possible states of a binary information element. The open-circuit or no-current state of
a teleprinter.
State
A condition of an electronic device, especially a computer, that is maintained until an internal or external
occurrence causes change.
S by S
Step-by-Step system. An electromechanical telephone switching system in which the switches are
controlled directly by digits dialed by the calling party.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
1-17
-GLOSSARY
Subscriber Loop
See Local Loop.
G)
CD
:::I
CD
i-
Supervision
The function of monitoring and controlling the status of a call.
TOM
-....
S'
o
3
Tip
C»
o·
:::I
Time Division Multiplexing. A communication system technique that separates information from channel
inputs and places them on a carrier in specific positions of time.
One conductor of the wire pair composing the local loop and designated by T. Usually the more positive
of the two conductors.
Toll Center
A major telephone distribution center that distributes calls from one major metropolitan area to another.
Transhybrid Loss
In a telphone hybrid, the measure of the isolation between the receive and transmit ports. It is also a measure
of the balance between the two matched windings of a hybrid transformer.
Transmission Link
The path over which information flows from sender to receiver.
Trunk
A transmission channel connecting two switching machines.
Trunkside
That portion of the central office that connects to trunks going to other switching offices.
Voice-Grade Line
A local loop, or trunk, having a bandpass of approximately 300 to 3,000 Hz.
Wideband Circuit
A transmission facility having a bandwidth greater than that of a voice-grade line.
1-18
..If
TEXAS
INSTRUMENlS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75286
Telecommunications Circuits
2-1
-t
CD
CD
(")
o
3
3
c
::::I
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::::I
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9...
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2-2
DS3680
QUAD TELEPHONE RELAY DRIVER
D2758, MARCH 1986
•
O. J OR N PACKAGE
(TOP VIEWI
Designed for - 52-V Battery Operation
•
50-mA Output Current Capability
•
Input Compatible with TTL and CMOS
•
High Common-Mode Input Voltage Range
•
Very Low Input Current
•
Fail-Safe Disconnect Feature
AMPL # 1 { IN +
IN -
BAT GND
OUTPUT AMPL # 1
AMPL # 2 { IN IN +
OUTPUT AMPL # 2
OUTPUT AMPL # 3
AMPL # 3 {IN +
OUTPUT AMPL # 4
INBAT NEG
AMPL #4 IN- """'-_ _..r- IN+ AMPL #4
•
Built-In Output Clamp Diode
•
Direct Replacement for National DS3680
and Fairchild I'A3680
f/)
.~
j
description
..
U
(.)
The OS3680 telephone relay driver is a monolithic integrated circuit designed to interface - 48-volt relay
systems to TTL or other systems in telephone applications. It is capable of sourcing up to 50 milliamperes
from standard - 52-volt battery power. To reduce the effects of noise and IR drop between logic ground
and battery ground, these drivers are designed to operate with a common-mode input range of ± 20 volts
referenced to battery ground. The common-mode input voltages for the four drivers can be different, so
a wide range of input elements can be accommodated. The high-impedance inputs are compatible with
positive TTL and CMOS levels or negative logic levels. A clamp network is included in the driver outputs
to limit high-voltage transients generated by the relay coil during switching. The complementary inputs
ensure that the driver output will be "off" as a fail-safe condition when either output is open.
f/)
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CtI
.2
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E
The OS3680 is characterized for operation from - 25°C to 85 DC.
o
symbol (each driver)
(.)
CI)
schematic diagram (each driver)
IN+
BATTERY GROUND
G)
15 kG
I-
NONINVERT*NG
INPUTIN+
+
INVERTING
INPUT IN-
OUTPUT
IN-
BATTERY NEGATIVE
OUTPUT
'----~~-
L -__~~~____~__________~~_BA
__TNEG
PRODUCTION DATA documents contain information
current 8S of publication date. Products conform to
specifications per the terms of Taxas Instruments
:::-::!:~~irv8i~r:1~1i ~!:~:~i:r lI~O::;:~~::S~S not
Copyright © 1986, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-3
DS3680
QUAD TELEPHONE RELAY DRIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range at BAT NEG, VB- ................................ -70 V to 0.5 V
Input voltage with respect to BAT GND . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .. - 70 V to 20 V.
Input voltage with respect to BAT NEG ................................. -0.5 V to 70 V
Differential input voltage, VID (see Note 2) ..................................... ± 20 V
Output current: resistive load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 100 mA
inductive load ............................................ "
- 50 mA
Inductive output load ........................................................ 5 H
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 3):
D package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 900 mW
J package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1025 mW
N package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1650 mW
Operating free-air temperature range .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 25°C to 85 °C
Storage temperature range ......................................... - 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J package ............. 300°C
N package ............ 260°C
-I
CD
i"
n
o
3
3
c:
NOTES:
~
n'
...0'
1. All voltages are with respect to the BAT GND terminal, unless otherwise specified.
2. Differential input voltages are at the noninverting input terminal IN + with respect to the inverting input terminal IN -.
3. For operation above 25°C free·air temperature, derate linearly at the rate of 7.2 mW/oC for the D package, B.2 mW/oC for
the J package, and 13.2 mW/oC for the N package.
D)
recommended operating conditions
~
rn
o
=r
n
c:
::+
rn
Supply voltage, VBInput voltage, either input
MIN
MAX
UNIT
-10
-60
V
-20 T
20
V
2
20
V
O.B
V
DC
High-level differential input voltage, VIDH
Low-level differential input voltage, VIDL
Operating
free~air
-20
temperature, TA
-25
85
tThe algebraic convention, in which the less positive (more negative) limit is designated minimum, is used in this data sheet for input voltage
levels.
electrical characteristics over recommended operating free-air temperature range, VB _ (unless otherwise noted)
PARAMETER
IIH
IlL
High·level input current (into IN +)
Low-level input current linto IN + )
VOl on ) On·state output voltage
1010ff) Off-state output current
TEST CONDITIONS
MIN
VID - 2 V
VID = 7 V
VID - 0.4 V
VID -
-7 V
=
50 mA,
10
Va
=
VB-
VID
=
2 V
IVID - O.B V
I Inputs open
Va = 0
10 - 50 mA
MAX
40
100
375
1000
0.01
5
UNIT
~A
~A
-1
-100
-1.6
-2.1
V
2
-2
100
-100
~A
·2
100
~
0.9
-0.9
1.2
-1.2
V
IR
Clamp diode reverse current
VOK
Output clamp voltage
IBlon)
On·5tate battery current
All drivers on
-2
-4.4
mA
IBloff) Off-state battery current
All drivers off
1
100
~A
10 -
-50 mA,
VB- - 0
*AII typical values are at T A = 25°C.
2-4
TVP*
- 52 V
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TeXAS 75265
DS3680
QUAD TELEPHONE RELAY DRIVER
switching characteristics VBPARAMETER
ton
Turn-on time
toff
Turn-off time
MIN
TEST CONDITIONS
VID = 3-V pulse.
L = 1 H.
TYP
RL = 1 kll.
See Figure 1
MAX
10
10
PARAMETER MEASUREMENT INFORMATION
BATGND
...
en
'3
VI----I
.
C3
CJ
-52 V
en
-52 V
c
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CO
FIGURE 1. GENERALIZED TEST CIRCUIT, EACH DRIVER
CJ
'c:::J
E
E
BAT GND
o
CJ
INPUT---I
CD
>----1II---OUTPUT
"i
RL = 1 kO
BAT NEG
I-
L=1H
-52 V
TEST CIRCUIT
INPUT ~_ _ _ _ _ _ _ _ _ _ _ _ _,
,I
1
OUTPUT
~ ton
- - - - - - +3V
~
I
I-
"':'--t-of-f-
0V
I
:;- ---- VO(on)
-25 V
-25 V
"'-52 V
VOLTAGE WAVEFORMS
FIGURE 2. SWITCHING CHARACTERISTICS. EACH DRIVER
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-5
DS3680
QUAD TELEPHONE RELAY DRIVER
TYPICAL APPLICATION DATA
52VBATTERY
+111-
~~----~ ~------.-----------~
(1)
(2)
(9) OS3680
BAT NEG
Klr
---L
---L
---L
---L
IN+ }
IN- AMPL#l
(4)
(3)
(5)
(6)
(8)
I
I
L ___ .J
(7)
IN+ }
AMPL#2
IN-
K26:""
IN+ }
AMPL#3
ININ+ }
IN- AMPL #it
K36:""
CONTROL
SIGNAL
SOURCE
K4r
Kl THRU K4
50·V RELAY COILS - 50 mA MAX
BATGNO
(14)
FIGURE 3. RELAY DRIVER
2·6
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM1520A
RING DETECTOR
02860, OCTOBER 1984-REVISEO JANUARY 1988
•
On-Chip 150-V Bridge Diode Configuration
•
Reliable BIDFETt Technology
•
High Standby Impedance , . . 1 MO Typ
•
Efficient High-Voltage Operation
•
Output Compatible with TTL. NMOS. and
CMOS
•
Built-In 5-V Series Regulator
•
Built-In Lightning and Transient Protection
D8
P PACKAGE
(TOP VIEWI
AC INPUT
INVERTING OUTPUT
COMMON
5-V OUTPUT
2
J
4
7
6
5
AC INPUT
COMMON
C FILTER
BELL TAPPING SENSE
TCM1520A APPLICATION
PHONE LINE
AC RING
SIGNAL
description
The TCM1520A is a monolithic ring detection
integrated circuit designed for use in isolated or
nonisolated telephone applications. The device
uses a modified form of the Texas Instruments
BIDFETt technology to combine low-voltage
CMOS and high-voltage bipolar input/output
circuitry. It features efficient high-voltage (40 V
to 150 V) operation with a typical current drain
of 1 mAo
fI
en
~
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(,)
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TCM1520A
en
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o
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ca
(,)
ELECTRONIC TELEPHONE
OR ACCESSORY
TTl
NMOS
CMOS
MICROPROCESSOR
During standby, the input impedance is
approximately 1 MO or greater, which will
prevent any interference with parallel "off-hook"
telephones transmitting DTMF or voice
frequencies. The device achieves such a high
input impedance with an on-chip series zener
diode that does not conduct until the voltage across Pins 1 and 8 exceeds 8 V. When the voltage across
Pins 1 and 8 exceeds 18 V, the internal switch is closed. which bypasses the 6.8-V zener diode and series
resistor. This allows more efficient power transfer to the load when the device is in the operating mode.
In the operating mode. the impedance of the device varies from 30 kO to 7 kO over the ring signal of 40 V
at 16 Hz to 150 V at 68 Hz and is reasonably independent of the output load.
"2
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In typical telephone applications, the TCM1520A is activated through the telephone line by a ring voltage
of 40 Vat 16 Hz to 150 Vat 68 Hz. The TCM1520A generates a signal suitable to drive an optocoupler
or TTL. NMOS, or CMOS logic. The 5-V Output (pin 4) may be used as a supply source for optocouplers
or low-power logic. This output is noninverting and will be at a high-level during ringing.
The TCM 1520A incorporates lightning and transient protection that is designed to suppress lightning strikes
of 1. 5-kV amplitude and 200 /Ls duration. The TCM 1520A also features built-in circuitry to avoid tapping
or false triggering due to transients.
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
tBIDFET - Bipolar, Double~Diffused. N~channel and P~channel MOS transistors on the s8me chip - patented process.
PRODUCTION DATA documlnts contain information
curron! a. of publication date. Product. conform to
specifications par the terms of Taxas Instruments
standard warranty. Production processing does not
nac8lllrily iRcluda tasting .f all parlmatars.
Copyright © 1983, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-7
TCM1520A
RING DETECTOR
functional block diagram
(11
r- - - - - - -
RlNGSiiiN"j;i-T VOLTAGE INPUT I
SECTION
I
AC INPUT
-I
I
I
()
I
o
3
3
c
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iMPEDANCe, 1
-HiGH INPUT
ANTI·TAPPING SECTION
I (51
I
I
2001"1
I
I
I
I
I
I
I
I
VREF
I
1-------- -----~------------~I
REGULATED
VOLTAGE
OUTPUT SECTION
(61 C FILTER
I
I
r~;;;;::;:-l----__~I~(4~1
(is'
o·...::J
5 V OUTPUT
I
18kl"l
.---"
(I)
(")
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I
1(21 INVERTING
~.
if
BELL TAPPING
SENSE
I
1A
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I
I
CD
CD
PROTECTION
SECTION 45 V
-
I
I
rTRANS.ENT- -
I
I
-
OUTPUT
L _______________________ _
(31
COMMON
(7)
COMMON
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Continuous supply voltage at pin 6 (see Note 1) .................................. 40 V
Continuous differential input voltage, VID (Pins 1 and 8) ............................ 40 V
Continuous output current, 10 .............................................. 12 mA
Continuous SCR on-state input current (see Note 2) ............................. 200 mA
SCR on-state input current, II/on) (duration s200l's) (see Note 2) .................. 900 mA
Continuous total dissipation (see Note 3) .................................... 1000 mW
Operating free-air temperature range .................................. - 20°C to 70 °C
Storage temperature range ........................................ - 40°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ..................... 260°C
NOTES: 1. All voltage values, unless otherwise noted, are with respect to pin 7.
2. SCR on·state input current is the current at the input when the SCR turns on.
3. For operation above 25'C free·air temperature, derate to 640 mW at 70'C at the rate of 8 mW'·C.
2-8
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
TCM1520A
RING DETECTOR
recommended operating conditions
MIN
NOM MAX
UNIT
High-level input voltage, VIH
40
V
Low-level input voltage, VIL
5
V
Operating free-air temperature, T A
0
70
°c
electrical characteristics over recommended operating free-air temperature range, RL ... open,
C(fltr) - 10 ",F (unless otherwise noted)
detector section
PARAMETER
TEST CONDITIONSt
V(BRICEX Collector-emitter
output breakdown voltage, Pin 2
Low-level output voltage, Pin 2
VOL
VT+
VTVhvs
Zlioffl
Positive-going
threshold voltage
Negative-going
threshold voltage
Hysteresis IVT + - VT-I
Standby input impedance
Vi
s 5 V (rmsl,
Vi - 25 V (rmsl,
10 = 5p.A
MIN TYP*
MAX
45
V
V
(3
7
V
(/)
11
10
V
o
Mil
f
Vid = 40 V,
f = 16 Hz
30
kll
Vid = 130 V,
f = 20 Hz
20
kll
Impedance when ringing
IlIonl
Vllonl
On-state input current, SCR'
See Note 4
On-state input voltage, SCA
Iitholdl
Vo
Input holding current, SCA
Output voltage, Pin 4
VI = 40 V,
Shunt voltage, Pin 6
11= 10 rnA
Operating current
VI = 40 V,
55
110
See Note 4
50
100
See Note 4
100
4.25
5.75
V
38
50
V
1.6
rnA
AL = 10 kll
Output open
..
25
Vi - 3 V,
Zring
(/)
V
18
s 20 kHz
...
·S
1
10 - 1.6 rnA
6
UNIT
rnA
V
p.A
1
(J
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Q)
Q)
~
switching characteristics at 25 °C operating free-air temperature, f - 20 Hz (unless otherwise noted)
PARAMETER
ton
Turn-on time
t(o/fl
Turn-off time
TEST CONDITIONS
MIN
TYP
MAX
100
VI = 40 V
VI - 40 V
175
VI = 60 V to 150 V
300
UNIT
ms
ms
t All characteristics are measured with a 2.2 kG resistor connected to pin 1 and a 0.47 JLF capacitor connected at pin 1 in series with
the input signal, unless otherwise noted.
All tvpical values are at T A = 25°C.
'This is the input current required to turn on the SCA.
NOTE 4: These parameters are measured using pulse techniques (t w :S 200 p.s, duty cycle :s 5%) with terminal pin 6 grounded.
*
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-9
TCM1520A
RING DETECTOR
PARAMETER MEASUREMENT INFORMATION
0.47 "F,
350 V
40 V TO 150 V {
(,mIl
'-----.J
----,
TCM1520A
5 V REG 1-'(4:::!1---.~_ OUTPUT
OUTPUT
10 kll
C1I AC
2.2 kll INPUT
VIC
(81 AC
INPUT
(61 C FILTER
10/,F,
50V
-t
CD
CD
n
FIGURE 1. SWITCHING TEST CIRCUIT
0
3
3
r:::
TYPICAL CHARACTERISTICS
j
(i'
CAPACITOR VOLTAGE (PIN 6)
Q)
vs
vs
0'
DC INPUT VOLTAGE (PINS 1 AND 8)
CAPACITOR VOLTAGE (PIN 6)
....
18
j
en
0
~'
n
r:::
;::;:'
en
OUTPUT VOLTAGE (PIN 4)
6
V
TA ='25°C
15
5
>
>
I 12
~
.e
.......
'u
u
COMPARATOR
SWITCH FIRES
9
V ~
I
/
o I~
8
V
10
V
12
14
16
18
VI - DC Input Voltage - V
4
~
3
~
o
2
/
~
o
.......1I
4
5
./
COMPARATOR
VWITrFIRr-
8
7
6
Capacitor Voltage - V
FIGURE 3
FIGURE 2
2-10
/
V
I
20
.~
/
';;
6.8·V ZENER DIODE
6 (-STARTS TO CONDU
3
I
t
1'1.
!
, °
TA=25 C
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 76265
9
10
TCM1520A
RING DETECTOR
TYPICAL APPLICATION DATA
TCM1520A
R1
Vi
{
40VT0150V.
16 Hz TO 68 Hz
= 2.2 kn (1)
VID
--.J
I
AC
TIL 181
5 V REG
OUTPUT
INPUT
}
18) AC
TO ISOLATEO
OUTPUT
INPUT
C1 = 0.47 /.IF
(6) CFILTER
R2 = 2.2 kn
COMMON
C2= 10/.lF.
50V
~
(3)
...
(7)
en
"S
FIGURE 4. ISOLATED CONFIGURATION
TCM1520A
::~~,:::; e·G : :~'
~
INPUT
5V REG (4)
OUTPUT
Vee
10kU
OUTPUT 1-'(",2),---+_ OUTPUT
(,)
en
c
o
".;:.
as
(,)
"2
C1 = 0.47 /.IF
(6)
..
C3
~
C FILTER
E
E
o(,)
COMMON
Q)
"i
FIGURE 5. NON ISOLATED CONFIGURATION
I-
NOTE: See Table 1 for component functions.
TABLE 1. COMPONENT FUNCTIONS
COMPONENT
FUNCTION
Rl
Limits current into SeR during high voltage transients and aids in dial pulse rejection.
R2
Limits current into lightwemitting diode.
Cl
C2
OPTOCOUPLER
Blocks dc battery voltage in standby and aids in filtering dial pulses. Smaller values of C 1
improve tapping immunity.
Stores energy from the ring signal to power the 5-V regulator.
Provides ground and transient isolation between the host system and the telephone line.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-11
-
-I
(1)
CD
o
3
3
(')
c:
::s
n'
r+
o·
Q)
::s
til
(")
:::;'
(')
c:
::;:
til
2-12
TCM1531. TCM1532. TCM1536. TCM1539
TCM1501B. TCM1506B. TCM1512B
TELEPHONE TONE RINGER DRIVERS
02940. MARCH 1986-REVISED APRIL 1987
•
Electronic Replacement for Electromechanical
Telephone Bell When Used with Transducer
•
Designed to Meet or Exceed FCC Part 68
Class B Ringer Requirements
•
Low-Cost External Component Requirements
•
Low External Component Count
•
High Standby Input Impedance . . . 1 Mil Typ
•
Low Ringer Equivalency Number ... < 1 Typ
•
Single-Ended High-Voltage Output Compatible
with Piezo Transducer or TransformerCoupled Speaker
•
Reliable BIDFETt Process Technology Provides
Efficient High-Voltage Operation
•
On-Chip High-Voltage Full-Wave Diode Bridge
Rectifier and Output Voltage Regulator
•
On-Chip Circuitry Provides Ring Rejection of
Rotary Dial Transients, Lightning, and Induced
High-Voltage Transients
P DUAL·IN-LiNE PACKAGE
(TOP VIEW)
AC (NPUT[]8 AC (NPUT
DRIVER OUTPUT 2
7 COMMON
ANTITAPPING IN 3
6
C FILTER
5
ANTITAPPING OUTI
OSCR 4
INTERNAL ZENER
BYPASSt
t Antitapping Output for TCM1531. TCM1532. TCM1536. and
TCM1539. Internal Zener Bypass for B~suffix versions.
en
'3
...
(,)
C3
•
On-Chip Thyristor Coupled with Additional
External Components Provides Enhanced
Rejection of Dial Pulses
TYPICAL CHARACTERISTICS
TELEPHONE TONE RINGER DRIVER FAMILY
PART NO.
TCM1531.
TCM1501B
TCM1532.
TCM1512B
•
OUTPUT
CENTER
FREQUENCY (Hz)
TCM15018, TCM1512B, and TCM1506B are
Improved Direct Replacements for TCM1501A,
TCM 1512A, and TCM 1506A, Respectively
Requires Only a Single-Value Oscillator
Resistor Which Eliminates Binning Codes of
the TCM15XXA Series
en
o
'';:::;
ca
(,)
'2
c
NOMINAL
•
EJI
...
TCM1536.
TCM1506B
TCM1539
2000
WARBLE
RATIO
(fH:fL)
8:7
NOMINAL
::::s
E
E
o(,)
WARBLE
FREQ.
(Hz)
7.8
Q)
Q)
1250
8:7
500
5:4
7.8
2000
5:4
31.2
I-
9.8
description
The TCM1531, TCM1532, TCM1536, TCM1539, TCM1501B, TCM1506B, and TCM1512B are monolithic
integrated circuit telephone tone ringer drivers that, when coupled with an appropriate transducer, replace
the electromechanical bell. These devices are designed, using BIDFETt technology, for use with either
a Piezo transducer or an inexpensive transformer-coupied speaker to produce a pleasing tone composed
of a high frequency (fH) alternating with a low frequency (fLl resulting in a warble frequency. Each device
is powered and activated by the telephone line ring voltage, which may vary from 40 volts to 150 volts
rms at frequencies from 15.3 hertz to 68 hertz.
During low voltage (off-hook) standby, typical input impedance is greater than 1 megohm; this prevents
interference with telephone DTMF or voice signals without the use of expensive mechanical switches.
This high standby impedance is achieved with an on-chip series zener diode that is activated by a differential
input voltage of typically 8.9 volts at pins 1 and 8. A voltage level of typically 17 volts differential at pins
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
tBIDFET - Bipolar, double-diffused. N-channel and P·channel. MOS transistors on the sarna chip-patented process.
PRODUCTION DATA d.oumonls •• nt.in information
current .s of publicatiDo data. Products conform to
.....1I1.ation. par tho terms .f T.... Instrum.""
=~r,"i~:I':.'l.i ~r::I:~:r :rlo::;:::~::.s not
Copyright © 1986, Texas Instruments Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-13
TCM1531, TCM1532, TCM1536, TCM1539
TCM1501B, TCM1506B, TCM1512B
TELEPHONE TONE RINGER DRIVERS
description (continued)
1 and 8 deactivates the internal zener diode, allowing for more efficient power transfer to the load when
the device is in the operating mode. During ringing, the impedance of the applied circuit (see Figures 4,
5 and 6) varies from 30 kilohms to 8 kilohms over the Class B ring signal, and is reasonably independent
of the output load.
These devices feature lightning and transient protection circuitry designed to withstand transients of
1.5 kilovolt for up to 200 microseconds duration when used with the proper external circuitry (see Figures 4
and 5). In addition, an on-chip thyristor coupled with an external resistor and capacitor circuit will reject
dial pulses from parallel telephones so that false ringing (tapping) will not occur (see Typical Application
Data).
The TCM1501 B, TCM1506B, and TCM1512B have a provision for bypassing the internal series diode with
one of lower voltage, thereby lowering the turn-on threshold of the device. If the antitapping thyristor
is used with these devices, an external zener diode must be added in series with pin 5.
-I
CD
CD
n
o
These telephone tone ringer drivers may be used in nontelephone communications applications. For example,
the devices can be used with a few external components to produce an inexpensive and highly efficient
alarm (see Figure 6).
3
3
c
~
functional block diagram
t=;"
...c)"
CI)
~
en
(")
~"
n
c
;:;'
en
,.-........-tr+-._---:.(6:::.) C FILTER
2 kll
AC INPUT(l)
(3) ANTITAPPING
AC INPUT",(8:.:..)+-..
1.6 kll
INPUT
8 kll
3 kll
L-__~~___________________e-~~(~7)COMMON
V---..:.;(5"') ANTITAPPING OUTt
.....________-tIIIt-6_.8__
L-_ _ _ _...1-_ _ _ _ _--'(~5) INTERNAL ZENER BYPAsst
tAntitapping output for TCM1531. TCM1532, TCM1536. and TCM1539. Internal Zener Bypass for B-suffix versions.
2-14
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 76265
TCM1531. TCM1532. TCM1536. TCM1539
TCM1501B. TCM1506B. TCM1512B
TELEPHONE TONE RINGER DRIVERS
absolute maximum ratings
Continuous peak-to-peak input voltage, pin 1 to pin 8 (see Note 1) . . . . . . . . . . . . . . . . . . .. 110 V
Continuous dc input voltage at pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 55 V
Negative dc voltage, any pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 1.2 V
Continuous output current, 10, at pin 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 mA
Continuous output current, pin 5 and pin 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 30 mA
Continuous SCR on-state input current, pin 1 to pin 8 ............................ 200 mA
SCR on-state input current, pin 1 to pin 8 (duration :s 2001's) ...................... 900 mA
Continuous total dissipation at (or below) 25°C free-air temperature (see Note 2) . . . . . .. 1000 mW
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 40°C to 85 °C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40°C to 125°C
NOTES:
1. For applications requiring ~ 38 Vrms, an external resistor and capacitor are required to prevent damage to the device (see
Note 3). Tip and ring may be connected interchangeably to either pin 1 or pin 8.
=
(3
MIN
MAX
40
150
V
120
-20
180
kO
70
°C
15.3 Hz to 68 Hz) Isee Note 3)
Resistor between OSCR and COMMON, Rose
Operating free-air temperature, T A
UNIT
U)
r:::
o
'';:
ca
NOTE 3: Input voltage is applied to pins 1 and 8 through a series 2.2 kO ± 10% resistor and a 0.47 I'F ± 10% capacitor Isee
Figures 4, 5, and 6).
electrical characteristics at 25 °C free-air temperature, RL = open, C(fltr)
otherwise noted), see Figure 2
10 "F, f = 20 Hz (unless
Ringing stop threshold voltage
Ringing start threshold voltage
TEST CONDITIONS
MIN
Pin 5 open,
RL - 4 kO
Pin 5 open,
RL
I
=
=4
RL = 4 kO
Antitapping thyristor activated
7
antitapping thyristor
Pin 3 input current required to
activate antitapping thyristor
Vi
=
=
3 V,
I ,,; 20 kHz
3 V,
I ,,; 20 kHz
0.1
Isee Note 5)
= 40 V,
= 15.3 Hz
Vi = 130V,
RL
=4
RL
Operating current
Pin 2 open,
VI
= 4 kO
= 40 v
Low-level input current
VI = 5 V
All pins open,
Vi
Impedance when ringing
SCR trigger voltage
MAX
19
28
V
40
V
15.3 Hz
Pin 5 open,
Vi
TYP
kO,
Pin 3 voltage required to activate
Standby input impedance
r:::
::l
E
E
o
CD
PARAMETER
Ringing start threshold rms voltage
,~
u
detector section
Ringing start threshold voltage
U)
'S
...u
2. For operation above 25°C free-air temperature, derate linearly at the rate of 8 mW/oC.
recommended operating conditions
RMS input voltage, VI II
PI
....
kO,
Ipin 1 to pin 8)
II ,,; 125 mA Isee Note 4)
SCR trigger current
All pins open,
Ipin 1 to pin 8)
VI ,,; 100 V Isee Note 4)
SeR input hold current
Isee Note 4)
11
V
40
V
1
V
0.2
mA
1
MO
10
kO
25
I
UNIT
Q)
I-
kO
22
1.3
20
mA
I'A
50
60
100
V
55
80
110
mA
10
mA
NOTES: 4. These parameters are measured using pulse techniques Itw ,,; 2001's, duty cycle ,,; 5%).
5. Pin 5 connected to pin 6, and pin 6 connected to pin 7 through a 100 n resistor.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-15
TCM1531, TCM1532, TCM1536, TCM1539
TCM15018, TCM15068; TCM15128
TELEPHONE TONE RINGER DRIVERS
electrical characteristics at 25°C free-air temperature, C(fltr) - 10 "F, f - 20 Hz (unless otherwise
noted), see Figure 2
output section
PARAMETER
TEST CONDITIONS
Output voltage, pin 2
CD
TYP
lo-2mA,
See Note 6
10
VI = 50 V,
Vi = 40 V,
lo=5mA,
IO=2mA,
See Note 6
44
8
Vi - 150V,
-t
MIN
VI = 17 V,
Output voltage, pin 6 (See Note 71
Vi = 150V,
lo=2mA.
f = 15.3 to 68 Hz
High-level output current
VI - 50 V,
VOH - 43 V
Low-level output current
VI - 50 V,
VOL - 1.5 V,
f - 16 Hz
f = 15.3 Hz
MAX
UNIT
V
40
55
See Note 6
V
15
mA
11
mA
n
NOTES: 6. Devices must be forced to the required output state by taking pin 4 to 8 V and toggling to 0 V as required. This stops the
on-chip oscillator.
7. Normal device operation requires that a capacitor ba connected from pin 6 to common (pin 71. A 10 p.f capacitor is recommended
for optimum antitapping vs turn-oft-time performance of the circuit. IncreaSing or decreasing the value of this capacitor will
respectively increase or decrease the antitapplng capabilities of the circuit.
C
oscillator section
CD
o
3
3
~
c:;"
...o·
I»
~
o
PARAMETER
TEST CONDITIONS
Output tone frequency
High tone frequencyl
Rosc = 160 kG ± 1%
Low tone frequency
n
Warble frequency
:+
o
Temperature coefficient
Rosc = 150 kG ± 1%
C
MAX
213311867
228311998
TCM1532, TCM1612B
123911085
133311167
142711249
TCM1536, TCM1506B
5161414
555.51445.5
5951477
206611653
222211778
237811903
TCM1531, TCM1501B
TCM1532, TCM1512B
7.8
TCM1536, TCM1506B
7.8
TCM1539
of frequency
2-16
TYP
198311736
TCM1539
(')
:::;.
MIN
TCM1531, TCM1501B
TA = -20°C to 70°C
9.8
TEXAS . "
POST OFFICE BOX 665012 • DAUAS. TEXAS 75265
Hz
Hz
31.2
±0.05
INSTRUMENTS
UNIT
%IOC
TCM1531, TCM1532, TCM1536, TCM1539
TCM1501B, TCM1506B, TCM1512B,
TELEPHONE TONE RINGER DRIVERS
PARAMETER MEASUREMENT INFORMATION
0.47 "F
~
(11
AC
INPUT
OUTPUT
121
TEST POINT
VI
VI
181
151
AC RETURN
NC
(31
141
NC
OSCR
C FILTER
161
Rose
10 "F
COMMON
..
en
..
'S
CJ
FIGURE 1. TEST CIRCUIT
(3
TYPICAL CHARACTERISTICS
c
o
en
',i:l
CO
CJ
N
'2
::t
I
>u
:::J
4k
E
E
o
c
•.,.,.
!
2k
140
•
!
•ct>
Dl
CJ
CD
1k
"i
I-
100~--~~~~~---L-L-L~~
10
20
40
70 100 200
400 700 1000
Rosc -Oscillator Reslstor-kll
FIGURE 2. OSCILLATOR RESISTOR vs OUTPUT AVERAGE FREQUENCY
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 656012 • DALlAS. TEXAS 7&266
2-17
TCM1531, TCM1532, TCM1536, TCM1539
TCM1501B, TCM1506B, TCM1512B
TELEPHONE TONE RINGER DRIVERS
TYPICAL APPLICATIONS
~~
TELEPHONE {
LINE
.
0.47 ~F
V.
i
(8)
0.1
AC
INPUT
OUTPUT
(2)
~F
If
1\
4000:80
IICtlJ
ACINPUT
(61 C FILTER
10 ~
100
~;:;: ~
-I
~
OSCR
COMMON
CD
Rose
1'7)
Ci"
(')
o
FIGURE 3. TELEPHONE APPLICATION-SPEAKER DRIVE
3
3
c
5"
CI)
.....
::::I
TEL~~:EONE
{~
0.47
Vi
(11~c;,UT
OUTPUTI-!(2::1-----.
~F
--"'--_ _·_..:.(8'"'1) AC INPUT
0"
PIEZO
TRANSDUCER
::::I
(I)
1 C FILTER
...-_ _--"(6""1
o::;"
10.F.
100 V
(')
(4) OSCR
c
::+
(I)
COMMON
Rose
FIGURE 4. TELEPHONE APPLICATION-PIEZO DRIVE
,n.
2.2.~O
TELEPHONE {
LINE
Vi
~
OUTPUT~(2~)-------,
(1) AC
INPUT
0.47.F
(8) AC
ANTITAPPING~(3::!.)_ _..,
INPUT
IN
PIEZO
TRANSDUCER
0.002·
0.022 ~Ft
,..-_ _--..:.:(6""1) C FILTER
ANTITAPPING~(5~)_ _.....
OUT
(4) OSCR
COMMON
Rose
100·
220 kOt
t Optimum values to be determined by specific antitapping requirements.
FIGURE 5. TELEPHONE APPLICATION. IMPROVED ANTITAPPING CIRCUIT
2-18
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM1531. TCM1532. TCM1536. TCM1539
TCM1501B. TCM1506B. TCM1512B
TELEPHONE TONE RINGER DRIVERS
TYPICAL APPLICATIONS
11O-:311..--"""'---11-'-'.!i ~~UT
11 1
:J
OUTPUTI-!12::.:1_ _ _ _ _ _--,
PIEZO
TRANSDUCER
'--_o-"t5'-_I:::S!j1 AC INPUT
C FILTERt"16::.1......- _ - ,
IRESETI
141 OSCR
COMMON
171
NC
Rose
U)
NC
,1::
:::J
...u
NC
U
U)
c
NC-Normally Closed
o
FIGURE 6. ALARM SYSTEM CONFIGURATION
'~
CO
u
'2
750 kll
I Mil
:::J
E
E
2.2 kO
...-"""""IIr---o + 5 V
o
u
------,I
'----eli-.....
4
......- _ 1
G)
Q)
I-
I
<:::>
I
I
Rose
150 kO
3.3 kll
I
I
~:!~SDUCER
I
IL _______ .JI
OPEN,COLLECTOR
TTL OR STTL
FIGURE 7. NONTELEPHONE APPLICATION
TELEPHONE
{
LINE
.....
121
!'"!,,
-. 0.4~j '" ~~UT
OUT1>UT
pF
1
lSI
ACINPUT
<:::>
PIEZO
TRANSOUCER
IN4002
I Mil
:t20%
S pF -:
100 V"
161 C FILTER
*I~~FV
:;;
Rose
~
OSCR
COMMON
1171
FIGURE 8. TELEPHONE APPLICATION-PIEZO DRIVE FAST RING SIGNAL CUTOFF
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-19
-
-4
CD
CD
n
o
3
3
r::::
:::l
(;'
Q)
r+
0'
:::l
C/I
(")
~'
n
r::::
;::;"
C/I
2-20
TCM2203
EQUIPMENT LINE INTERFACE
02861, AUGUST 1985-REVISED DECEMBER 1987
•
TCM2203
Transmits and Receives Sarlal Bipolar Data
at Up to 3 Mbit/s Using Two Twisted-Wire
Pairs,
J
DUAL·IN·LlNE PACKAGE
(TOP VIEW)
•
Low-Q Clock Extraction
•
Two ALBO (Automatic Line Build Out) Taps
with a Range of 42 dB
•
On-Chip Amplifier with 50-dB Open-Loop
Voltaga Amplification
•
Phase Adjustment for Recovered Clock
•
Direct Interface with the TCM2222
AMI/HDB3 (Alternate Mark Inversion/HighDensity Bipolar. Third Order)
Encoder/Decoder
•
•
TANK alP
PHASE ADJ 1
PHASE ADJ 2
GND
ALBa 1
BUF IN
BUF OUT
ALBa 2
C ALBa 1
C ALBa 2
PREAMP IN
PREAMP OUT
VCC
AMPL IN
Receive line Signal Loss Detection with
Mute Output
SLICER INSLICER REF
SLICER IN +
LINE OUT X
LINE OUT Y
RX D+ OUT
RX eLK OUT
RX D- OUT
TX DATA IN Y
TX DATA IN X
MUTE
TX CLK IN
NEG PEAK DETECT
pas PEAK DETECT
..
II)
..
C3
'S
U
II)
C
0
Bipolar Technology
'~
CO
u
description
'2
The TCM2203 is designed to perform the
interface function between the bipolar data
encoder/decoder (e.g .• TCM2222) and the line,
The TCM2203 consists of a receiver that
extracts clock information and reshapes the data
waveforms. and a transmitter that interfaces
bipolar data to the line, Detection of receive
signal loss is performed and a mute output is
available. Auto-adaptive slicing level ensures
excellent jitter and error performance,
:::J
E
E
0
u
Go)
Q)
....
The TCM2203 is characterized for operation
from OOC to 70°C.
PRODUCTION DATA docume.1s co.tei. i.formetio.
curre.t as of publicatio. date. Products co.form to
. specificatio.s per the terms of Texas I.struments
=~~i;;ai~r:I~'i ~r::\:~ti:; :.~O::;::::~:~~S not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 15265
Copyright @ 1985, Texas Instruments IncorpOrated
2-21
TCM2203
EQUIPMENT LINE INTERFACE
typical timing diagram
BINARY
PATTERN
0
0
0
0
0
0
0
AMI/HDB3
SIGNAL
0.24 V
POSITIVE DATA
SLICER REF
RESTORED INPUT
SIGNAL ON AMPL IN
-I
POSITIVE DATA
ii'
n
NEGATIVE DATA
NEGATIVE DATA
SLICER REF
CD
0
3
3
CURRENT PULSES
TO LC TANK
C
:::s
C:;'
C»
::::t,
RECOVERED
SINEWAVE FROM FILTER
0
:::s
en
RECOVERED CLOCK
FROM CLOCK BUFFER
(")
:::;'
n
POSITIVE LATCHED
DATA
C
::+
en
NEGATIVE LATCHED
DATA
NOTE: A low logic level on RX DATA OUT represents a received pulse, or a "mark." RX DATA OUT is latched on the falling edge of RX CK OUT,
and tracks the input signal when RX CK OUT is high.
absolute maximum ratings over free-air operating temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 15 V
Continuous total dissipation at 25 DC free-air temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 W
Operating free-air temperature range ........ . . . . . . . . . . . . . . . . . . . . . . . . . .. - 10 DC to 85°C
NOTE 1: Voltage is with respect to network ground.
recommended operating conditions
Supply voltage, VCC
Operating free·air temperature, T A
Vil
VIH
2-22
l TX Data in Y
I TX Data in X
I TX ClK in
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MIN
NOM
MAX
4.6
0
5.0
6.6
70
0.80
3.0
UNIT
V
·C
V
TCM2203
EQUIPMENT LINE INTERFACE
electrical characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted)
PARAMETER
SECTION
RX 0+ out
RX 0- out
VOH
TEST CONDITIONS
=
VCC
5 V.
IOH
= 40,..A
MIN
Typt
4.5
4.8
RX CLK out
TX Data in Y
IlL
IIH
TX Data in X
TX CLK in
On-state impedance
Off-state impedance
ALBO
Dynamic resistance matching error
VIL
=
Vp_p
0 V.
VIH
=
Input impedance
fa
Buffer
Voltage amplification
Input impedance
Output impedance
Pre-Amp
Open-loop voltage amplification
Preamplifier
=
=
VCC
25
11
0.11
0.15
10
20
40
4.5
40
5.3
60
42
50
46
7
4.5
40
11
5.3
= 480 mV
1 MHz
1 MHz
=
5 V.
VF
=
1 MHz
Unity-gain frequency
Input impedance
Voltage amplification (each output)
Capacitance-driving capability, peak detect pins
Input impedance
Voltage amplification
Phase slicer
amplilfier
Clock Slicer
Input-to-output delay
Peak-to-peak eye amplitude
Data slicing level
fa
=
1 MHz
fa = 2 MHz
fa = 2 MHz
fa = 2 MHz.
PHASE ADJ CAP
VCC
=
5 V
Data Slicer
Leakage
Low-level output voltage. VOL
Leakage
Low-level output voltage. VOL
Leakage
Low-level output voltage, VOL
Output rise time, tr
Output fall time. tf
=
Mute
VCC
RX 0+ OUT.
RX 0- OUT
VOH = 5 V
IOL = 2 mA
LINE OUT X.
LINE OUT Y
VOH = 5 V
IOL = 20 mA
Mute
Mute
LINE OUT X.
LINE OUT Y
VOH = 5 V
IOL = 1 mA
RL = 22011
RL = 22011
Supply current. ICC
11
kll
...
tn
100
=
75 pF
·S
(,)
.:
s
kll
11
6.0
(.)
dB
kll
tn
t:
11
dB
MHz
6.0
kll
dB
0.1
~F
o
~
CO
.~
t:
::::s
60
kll
dB
E
E
60
ns
(,)
480
mV
-a;
150
o
CD
I-
50%
Clock slicing level §
Negative-going threshold voltage
Positive-going threshold voltage
50
~A
2%
f - 1 MHz
fa
9
UNIT
V
±50
±50
5 V
Transconductance t (referenced to pin 14)
Output impedance
MAX
VCC
=
5 V
5 V
66%
3.3
3.5
V
,..A
V
0.9
50
1
50
1.1
~A
250
50
50
400
100
50
25
100
40
0.85
~A
V
mV
ns
ns
mA
t All typical values are at VCC = 5 V. TA = 25°C.
.
Transconductance is defined as the change in current for each diode string divided by the change in peak-to-peak voltage at pin 14.
§ Clock slicing level is the data level at which the TANK alP puts out a current pulse.
*
TEXAS ~
INSTRUMENTS
POST OFFICE
sox 655012
• DAllAS, TEXAS 75265
2-23
TCM2203
EQUIPMENT LINE INTERFACE
TYPICAL CHARACTERISTICS
EYE DIAGRAM REGULATION
(AT INPUT OF 6· dB AMPLIFIER)
1.5
Ii.
II.
1.25
~
::I
CD
CD
(')
o
3
3
c
.~
ii 0.75
e
.q:
e
..
~
i5
~
w
50
I
Vcc=5V
VCC=5V
45 I- RL = 1 Mil
~CL = 10 pF
III 40
TA = 25°C
~
I 35
.
~TA =70·C
,
~/TA=25C
..
~
-4
~I
TYPICAL PREAMPLIFIER VOLTAGE
AMPLIFICATION CHARACTERISTICS
0.5
~
~
30
fl
:E
ii 25
E
..'"
.q: 20
.,
0.25
TA=70·?
:::I
I
-10
r+
1\
c
·8
TA = 25·C):
n"
C»
"
S"
:::I
l!l 15
15
> 10
~
~
-20
-30 -40
-50
Line Attenuation - dB
5
o
-60
100 k
10 k
1k
10M
FIGURE 2
FIGURE 1
(II
1M
f - Frequency - Hz
(")
:::;"
PREAMPLIFIER OPEN·LOOP VOLTAGt: AMPLIFICATION
(')
c
::+
(II
vs
TYPICAL PREAMPLIFIER PHASE CHARACTERISTICS
180
VCC=s'"
r-...
160 RL = 1 Mil
140 CL = 10 pF
TA = 25·C
120
48
./
V
l-""
f\
\
100
I 80
..
f.
FREE·AIR TEMPERATURE
:Il
1\
60
40
20
f-VCC =5 V
f- VI = 3 mV (p.p)
f = 11.0241 MHz 1
o
-20
1k
10 k
100 k
1M
f - Frequency - Hz
10M
46
o
10
20
30
40 50
60
70
T A - Free·Air Temperature - ·C
FIGURE 4
FIGURE.3
2-24
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
80
TCM2203
EQUIPMENT LINE INTERFACE
ALBO DYNAMIC RESISTANCE (EACH STRINGI
vs
CURRENT
10 k
c:
I 1k
:lc
·i 100
..E
>
II
a:
.2
c
C
10
0.001
~I
"
VCC=5V
TA = 25°C
~
'" '"
~
0.1
0.01
Diode String Current - mA
'"
...
U)
.
C3
"S
u
..
U)
c
10
o
ca
FIGURE 5
u
"2
:::J
E
PRINCIPLES OF OPERATION
general
The TCM2203 is designed to form the interface between a bipolar decoder/encoder and the transmission
line. It is optimized for 1.536 MHz, 1.544 MHz, and 2.048 MHz operation, but is capable of operating
at 3.152 MHz and low frequency for special applications. The TCM2203 can be considered in two separate
parts, a transmitting section and a receiving section.
E
o
u
CD
"i
~
receiving section
This section performs three functions: signal restoration, clock recovery, and data slicing. It also detects
loss of incoming signal and flags this condition by taking the mute output high.
signal restoration
The incoming signal is typically very distorted and exhibits considerable intersymbol interference. The input
section must restore the signal to provide a clear eye diagram to the data and clock slicer. An amplifier
with open-loop voltage amplification of 50 dB with externally adjusted gain, together with the bode networks
and associated ALBO taps, give a dynamic range of up to 36 dB (6 dB to 42 dBI. This allows positioning
of the terminal at any line length (within the limits of ALBO dynamic rangel from repeater or like transmitter.
Equalization of the line characteristics is performed by a simple external series LC network buffered by
the 6-dB amplifier. The restored signal from the 6-dB phase splitter (controlled to 0.48 V peak-to-peakl
is sent to two peak detectors that store the peak values on external capacitors. The average peak values
are then summed to provide a signal level, which is compared to a Vee-derived reference to form an error
signal level. This error signal level controls the current in the ALBO strings. As ALBO string current increases,
the dynamic resistance of the string decreases and more signal is shunted to ground. In this way, automatic
gain control and automatic line build out are acheived. Typically, there is frequency response contouring
associated with the automatic gain control to compensate for the responses of different lengths of line.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 752&5
2-25
TCM2203
EQUIPMENT LINE INTERFACE
clock extraction
The received signal contains its own clock information, which must be extracted in the receive section.
An averaged peak input signal is derived from 'the sum of the positive and negative peak detectors. The
negative peak detector is actually the positive peak of AMPl IN inverted. Alternately, the peak average
sum is equal to the sum of the averaged absolute values of the negative and positive peaks. When the
negative or positive pulse at AMPl IN exceeds 66% of the averaged peak value, a current pulse occurs
at the TANK OIP output. These current pulses are filtered by a tuned-primary transformer-coupled circuit
to extract the clock and drive the slicer inputs. The slicer converts the sinewave into a binary square-wave
clock signal. The transformer-coupled tuned-primary circuit sets the clock extraction Q. The slicer is a highgain 60-dB comparator that minimizes conversion of amplitude modulation in the sine wave to phase
modulation in the recovered square wave clock.
-4
CD
data slicing
CD
The data comparators trigger whenever the signal goes above 50% of the average peak values from the
peak detectors. This data is then presented to the data latches and latched into the output buffers by
the falling edge of the recovered clock. When the RX elK OUT is high, RX D - OUT and RX D + OUT
track the comparators. The clock buffer trigger circuit can be externally phase adjusted with a 5-pF to
75-pF trim capacitor across PHASE ADJ 1 and PHASE ADJ 2 to set the falling edge exactly to the center
of the data pulses. This maximizes jitter acceptance and noise immunity.
n
o
3
3
r::::
::l
ri"
m
r+
0"
receive signal loss detection
The average peak data values are half-summed to give a dc value that is compared to an internal reference
relative to Vee. When the value falls below 33% of the nominal value after AlBO gain control, the MUTE
output goes high.
::l
(I)
o::;"
n
transmitting section
r::::
;:;."
(I)
2-26
The transmitting section gates the signals applied to TX DATA IN X and TX DATA IN Y with the signal
applied to TX elK IN. The gated signals are then applied to the line outputs. The line output pulse duration
is one-half of the bit period. The LINE OUT X and LINE OUT Y outputs are open-collector n-p-n transistors.
Each collector will sink 20 milliamperes when the appropriate TX DATA IN input and TX elK IN are at
low levels.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM2203
EQUIPMENT LINE INTERFACE
TYPICAL APPLICATION DATA
•..
,-;=-1>----,-1(:=2~31 RX D + OUT
1
U)
4J
I
"S
1
1
U
1
1
1
1
(3
U)
I
C
1
"~
o
p-_-f>--++1(:=2.:.:.11 RX D - OUT
CO
I
u
1
"2
L-i-----~~------------------~---~-~~~(1~8IMUTE
l40kO
6OkO
;:,
W ~
E
E
o
V re f2
(111
u
2kO
CD
(10
"'i
~
0.1 "F
10"F
1.2 kO
4300
191 1
I
430 0
270 "H
1
GND (41:
~:::;.,=~
;;,
6200
~
c:
~~TAINY(~
I
L ___________________________ J
vcc311tNEOUT
I
I
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-27
s:a.!nOJ!:l SUO!:a.eo!unwwoo9191
'"
N
00
m ....
etn
VCC
Ci!I:
47 II
:::a=::
i:CI
!ililW
1 kll
....
m
20kn
I
TCM2203
(1)
l.5kn
gJIICFl
1:1
l00pF
2l
II>
....
0.1 "F
!i:
~ .~.
~z
~~
~itI~
~z
~~
II>
..
~
'"
'"'"
N
SLICER REF
SLICER IN+
LINE OUT X
GND
ALBOl
LINE OUT Y
BUF IN
RXD+OUT
BUFOUT
;;C~
~~
/!('T'I
SLICER IN-
TANK OIP
(2) PHASE
ADJ 1
(3) PHASE
ADJ2
(4)
RXCLKOUT
RXD-OUT
ALB02
CALBO 1
TXDATAINY
CALB02
TX DATA INX
PREAMP IN
PREAMP OUT
AMPLIN
0.1"' ...
MUTE
(28)
I"'"'
iii
m
iii
~
....
m
=
""
n
):0
(27)
m
(26)
(25)
~
(24)
(;
"
TCM2222
(23)
(22)
(21)
Vss
(2) RXCKIN
NRZOUT
(3)
(20)
ii'XiiDii=
(4) TXHDB+
(19)
r
(5) TXHDB-
(18)
CONTROL
STATUS
1/0 PINS
"~"'E
NEG PEAK (16)
DETECT
POS PEAK (15)
DETECT
~
ZID
(7)
AIS
TXCKIN
NRZIN
AISINJ
OUTPUTS
(14)
}
(13)
n"}
(9)
VDD
~
(15)
HDB3/AMI (11)
(10)
ERROR
(8)
LOOPING
I"'"
(16)
iiXiiDii+
(1)
INPUTS
""
I"'"
B
is
z
CONTROL
STATUS
I/O PINS
c
~
5V
19.3kn
0.1 ~l00kn
pF
100knlo.l
pF
~
".
NOTE: Filter resistors are 1 %.
Filter capacitors are 5%.
t
TCM2222
AMI/HDB3 ENCODER/DECODER
02894. OCTOBER 1985-REVISED DECEMBER 1987
J PACKAGE
•
AMI or HBD3 Encoding of Binary Data
•
Simultaneous Decoding of Received AMI or
HDB3 Signal
•
Static Logic Allows Zero to 3-MHz Bit Rate
•
Seven Outputs for Received-Signal
Diagnostics
•
Reliable NMOS Technology
•
Single 5-V Supply
(TOP VIEWI
RXHDB+
RXCKIN
RXHDBTXHDB+
TXHDBZID
AIS
LOOPING
VSS
NRZOUT
TXCKIN
NRZIN
AIS INJ
AMIIHDB3
ERROR
VDD
...
description
U)
..
The TCM2222 performs three functions:
encoding, decoding, and signal monitoring.
"S
In the encoding section, a binary non-return-tozero (NRZ) signal is converted to a ternary signal
to improve its transmission characteristics. In the
decoding section, a received ternary signal is
independently converted into a binary form. In
the signal-monitoring section, the received
ternary signal in the decoder is checked for
various diagnostics, and errors that are found are
flagged.
(3
u
U)
C
o
+0
ca
u
"c:::J
E
E
o
The TCM2222 can be directly connected to the
TCM2203 line interface device to form a
complete equipment transmission interface.
u
Q)
"ii
The TCM2222 is characterized for operation
from OOC to 70°C.
'I-
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates ..
PRODUCTION DATA doc...o.ts conlli. informatio.
cunant ., of publication date. Products conform to
specificatianl Pili' th, tarms'of TaXI. Instruments
IUIldard W~"lnty. Production prOClllinll dDBS not
necessarily includa tasting of all par8I11at.~.
Copyright © 1985. Texas Instruments Incorporated
TEXAS . "
2-29
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS
7~2e5
TCM2222
AMI/HDB3 ENCODER/DECODER
functional block diagram
AIS INJ..:.(1;:;:2~)_ _
NRZ
IN~(1~3)1"""'1"""
e-__.-__~~~____~~____~~~~-+-+~
TXCKIN~(1~4~)____
-I
CD
ii'
n
o
3
~
(7) AIS
AMi/HDB3 (11)
CONTROL LOGIC, SWITCHING,
AND ERROR DETECTION
~
~"
(10) ERROR
LDDPING (B)
(6) ZID
r+
0"
~
(II
(')
::::;"
n
c
;:;'
(II
NRZOUT
RXCKN (2)
_ _ _ (3)
RXHDB--< 655012 • DALLAS. TEXAS 75265
UNIT
V
V
0
High-level input voltage
TA
MIN
V
0.8
V
70
°C
2-31
TCM2222
AMIIHDB3 ENCODER/DECODER
electrical characteristics over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
All outputs except
VOH High-level output voltage
VDO = 5 V,
IOH = -120 pA
VOO = 5 V,
IOH = - 40 pA
VOO = 5 V,
IOL = 2.4 mA
VOO = 5 V,
IOL = 2 mA
VOD = 6.5 V,
VIH = 2.4 V
VOO = 6.5 V.
VIL = 0.4 V
VDO = 5 V
'i'lrnDB'±
'i'irni5if.j:",
'i'i80
dB
;:::;.'
clock timing requirements over recommended ranges of operating conditions (see Note 12)
PARAMETER
MIN
Clock period for ClKX, ClKR (2.048-MHz systems)
tc(ClK)
t r , tf
Rise and fall times for CLKX, CLKR, and CLKC
tw(CLK)
Clock pulse duration for CLKX, CLKR, and CLKC
Clock duty cycle [tw(CLK)/tc(CLK)J for CLKX and CLKR
MAX
485
5
ns
30
215
45
UNIT
ns
ns
55
%
t Typical values are for T A = 25 DC and nominal power supply voltages.
9. With the test device acting as a decoder, a 200-mV peak-to-peak, 1,02 kHz signal is applied to the appropriate supply pin
NOTES:
and measurements are made at the remote encoder output with the decoder in idle-channel conditions.
10. With the test device acting as encoder and decoder, a 200-mV peak-to-peak, 1.02-kHz signal is applied to the appropriate
supply pin and measurements are made at the decoder output with the encoder in idle-channel conditions.
11. The analog input power is 0 d8mO at 1.02 kHz and the decoder is under idle-channel conditions. Measurement is made
at ANLG OUT.
12. All timing parameters are referenced to 2 V except tpd3 and tpd5. which reference a high-impedance state.
2-46
TEXAS . "
INSTRUMENTS
POST OFFiCe BOX 65!5012 • DALLAS. TEXAS 76265
TCM2909, TCM2910A
PCM WLAW COMPANDING CODECS
transmit timing requirements over recommended ranges of operating conditions (see Note 12)
PARAMETER
MIN
Analog input conversion time referenced to
tconvlX)
Frame sync delay time
tsulSIGX)
thISIGX)
Setu p time before Bit 7 falling edge
Hold time after Bit B falling edge
20
UNIT
time
20
leading edge of transmit time slot Isee Note 13)
tdIFSX)
MAX
slots
150
ns
0
ns
100
ns
receive timing requirements over recommended ranges of operating conditions (see Note 12)
PARAMETER
MIN
Analog output update from leading
tconvlR)
MAX
UNIT
150
slots
ns
tdIFSR)
Frame sync delay time
tsulPCM IN)
Receive data setup time
20
ns
thlPCM IN)
Receive data hold time
60
ns
20
..."Stn
time
71/16
edge of the channel time slot
...u
(3
tn
control (microcomputer operation) timing requirements over recommended ranges of operating
conditions
PARAMETER
tsulDC)
MIN
Control data setup time
100
Control data hold time
100
C
o
"';:
ca
cj
MAX
"~
E
propagation delay times over recommended ranges of operating conditions (see Note 12 and timing
diagrams)
PARAMETER
TEST CONDITIONS
MIN
MAX
E
UNIT
o
u
Q)
CD
From rising edge of transmit clock Bit 1
to Bit 1 data valid at PCM OUT
tpd1
CL
= Oto
100pF
50
1BO
ns
CL
= Oto
100pF
80
230
ns
CL
= O.
See Note 13
75
245
ns
CL
= Oto
100pF
30
220
ns
CL
= O.
See Note 13
70
225
ns
1000
ns
I-
Idata enable time on time-slot entry)
From falling edge of transmit clock Bit n
to Bit n + 1 data valid at PCM OUT
Idatavalid time)
tpd2
From falling edge of transmit clock 8it 8
to Bit 8 Hi-Z at PCM OUT
tpd3
/
Idata float time on time-slot exit)
From rising edge of transmit clock Bit 1
tpd4
to TSX active Ilow) Itime-slot enable time)
From falling edge of transmit clock Bit 8
tpd5
to
'i'SX inactive
Ihigh) Itime-slot disable time)
From falling edge of receive clock Bit 8
on signaling frames to updated
tpd6
signaling bit on SIGR output
Ireceive Signaling update time)
NOTES:
12. All timing parameters are referenced to 2 V except tpd3 and tpd5. which reference a high-impedance state.
13. The 20-time-slot minimum ensures that the complete AID conversion will take place under any combination of receive interrupt
of asynchronous operation of the codee. If only the transmit channel is operated, the AID conversion can be completed
in a minimum of 11 time slots.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS •.TEXAS 75265
2-47
TCM2909, TCM2910A
PCM WLAW COMPANDING CODECS
FSX INPUT
(NON SIGNALING FRAME~)
~
tcI(FSX)
----:.,.
FSX INPUT
(SIGNALING FRAMES)
FIGURE 18. TRANSMIT FRAME SYNCHRONIZATION TIMING
-I
(t
CLKX
tpd'----.I
CD
(')
PCMOUT
o
3
3
c
~
5·
I
I
--: I--tpd4
______________________________________________
~OU~UT
~
~
______~
SIGX INPUT _ _ _ _ _ _ _ _ _ _ _
D_O_N'T_CA_R_E_ _ _ _ _ _ _ _ _ _..If''--_ _ _,,'''~~~A:II;~I.:I_
....
o·
I»
FIGURE 1 b. TRANSMIT OUTPUT TIMING
~
en
~TIMESLOT'-------j
(")
~.
c
:+
en
I .r-ll-
C L K R .
-,J ttd~ \:l;
FSR INPUT
(NON SIGNALING FRAM~ ~
...• r:..: 1d(FSR)
r~~~~L~~G
FRAMES)
J
d(FSR)
-1
-...,
l-
'f-l~
!--tw(~LK)
I--tc(CLK,.j
tcI(FSR)
\~-----------------------------FIGURE 28. RECEIVE FRAME SYNCHRONIZATION TIMING
CLKR
PCM IN
SIGROU~UT ____________________________
VA_L_I_D____________________~~D
FIGURE 2b. RECEIVE INPUT TIMING
FIGURE 3. CONTROL TIMING
2-48
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 666012 • IlALLAS. TEXAS 75265
TCM2909, TCM2910A
PCM ,,"LAW COMPANDING CODECS
PARAMETER MEASUREMENT INFORMATION
ANALOG
SOURCE
ADRET2230
-
ANLG
IN
PCM
OUT
CODEC
(or equivalentl
-
PCM
IN
ANLG
OUT
[L
ANLG
PCM
IN
OUT
CODEC
ANLG
PCM
OUT
IN
r--
ANALOG
LEVEL METER
W&GPLM-95
(or equinlentl
W& G: WANDEL AND GOLTERMANN
...en
FIGURE 4. END-TO-END GAIN TEST CIRCUIT
.
'3
c
ANALOG
SOURCE
ADRET2230
I---
(or equivalentl
-
ANLG
IN
C3
PCM
f-OUT
CODEC
PCM
ANLG
IN
OUT
I-- f--
en
c
ANALOG
LEVEL METER
W&GPLM-96
o
'.j:;
CIS
(or equivolentl
c
'2
~
E
E
o
W & G: WANDEL AND GOLTERMANN
FIGURE 5. SELF-LOOP GAIN TEST CIRCUIT
ANALOG
SOURCE
ADRET2230
I--
ANLG
IN
PCM
OUT
-
IDEAL DECODER
W&G
PCD-64
ENCODER
1
(or equivalentl
(or equivalentl
CODEC
DIGITAL DATA
GENERATOR
W&GPCG·1
-
PCM
IN
ANALOG
LEVEL METER
W&GPLM-95
c
CD
'ii
I-
(or equivalent)
51
r
ANLG
OUT
DECODER
NOISE
(or equivalentl
NOISE LEVEL
METER
W & G PMD·1
(or equivalentl
W & G: WANDEL AND GOLTERMANN
FIGURE 6. TRANSMISSION PARAMETER TEST CIRCUIT
TEXAS •
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
2-49
TCM2909, TCM2910A
PCM WLAW COMPANDING CODECS
PARAMETER MEASUREMENT INFORMATION
40r----r----r---~----r_--~--_,r_--,_--_,r_--~
........
.................................................................
35~--~-----r..7.·~~,*-----r----+----~----+---~~----t
,. . . .:::c/
III
30~--~~~~~--+-----~---i-----r----+---~r----i
. .·····"'r' ./
"1
I
t
i5
I
25
."/'/'
, ~
'
Y'
20~~~-----+----~----r---~-----r----+---~r-----i
.......... TYPICAL. HALF CHANNEL
15~---+----
c
!i!'
en
+---~r----+-----r----1
- - - - MINIMUM. END·TO-END
- - MINIMUM END-TO·END. AT&T 03 CHANNEL BANK
101----+---- COMPATIBILITY SPECIFICATION (ISSUE 3, 10-771
5~---+----+---~-----r----r---~----+---~----~
O~--~----~
-45
-40
-35
__ ____ ____ __ ____ __ ____
~
-30
~
-25
~
-20
~
-15
~
-10
Input Level-dBmO
FIGURE 7. SIGNAL-TO-TOTAL DISTORTION RATIO
2-50
TEXAS
~
INSTRUMENTS
. POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
~
-5
~
o
TCM2909, TCM2910A
PCM ,,"LAW COMPANDING CODECS
PARAMETER MEASUREMENT INFORMATION
DIGITAL-TD-ANALOG TEST
DIGITAL DATA
GENERATOR
W& GPCG-1
(or equi....ntl
th
ANLG
IN
-
ANLG
OUT
-
IDEAL DECODER
W&G
PCD-64
(or equivalent)
CODEC
PCM
IN
o dBmO Code
PCM
OUT
-
at 1020 Hz
I/)
ANALOG-TO-DIGITAL TEST
ANALOG
SOURCE
ADRET2230
Cor equivalent)
ANALOG
LEVEL METER
W&GPLM-95
(or equivalent)
"~
..
C3
::::I
ANLG
IN
OdBmOCod.
at 1020 Hz
PCM
OUT
(J
-
fi)
c::::
CODEC
o
"';:;
DIGITAL DATA
GENERATOR
W&G PCG-1
(or equi."entl
ANLG
OUT
PCM
IN
11111111
Code
r--
ANALOG
LEVEL METER
W&GPLM-95
(or equivalent)
FIGURE 8_ CROSSTALK ATTENUATION TEST CIRCUIT
TABLE 2. ,..LAW DIGITAL WORD SEQUENCE FOR THE DIGITAL
MILLIWATT RESPONSE PER CCITT RECOMMENDATION G_711
:0
Z
1!
,;
::::I
E
W & G: WANDEL AND GOLTERMANN
!E
ca
"2
(J
1
2
3
4
5
6
7
8
1
0
0
0
0
1
1
1
1
2
0
0
0
0
0
0
0
0
3
0
0
0
0
0
0
0
0
Bit Numbe,
4
5
1
1
0
1
0
1
1
1
1
1
1
0
0
1
1
1
6
1
0
0
1
1
0
0
1
7
1
1
1
1
1
1
1
1
E
o
(J
Q)
Q)
I-
8
0
1
1
0
0
1
1
0
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-51
TCM2909, TCM2910A
PCM WLAW COMPANDING CODECS
TYPICAL APPLICATION INFORMATION
CODEC
FILTER
r------,
I
r------~---------,
I
C1
I
I
o
'IMI
CAPX1 :
l
I
I
CAPX21
AUTO ZERO
I
-I
+
CD
2mV
OFFSET
CD
(')
o
I
L _____ JI
3
3
A~G.!~ _ _
r::::
::::s
5·
...O·
I
I
I
I
I
J
FIGURE 9. ANALOG INTERFACE WITHOUT EXTERNAL AUTO ZERO
I»
r--------------,
FILTER
CODEC
r----'
o::::s
o
I
I
s..
o
I
::;.
(')
I
.
I
I
I
I
I
I
I
I
ENCODER
FILTER
I
C2
10.3"F
I
I
I
I
I
I
DECODER
FILTER
ANLGIN
t--+--........' - - - - - - - - < r O - - - - " " '...----t-----l....·
R1
150kO
..L
R3
470kO
.........,.,.,....-tAUTO ZERO
CAPX2
R2
3300
+
ANLG GND
L-_~_~
I
L ____ J
L _______
~.
_____
2mV
OFFSET
A:-C::N
': __
FIGURE 10. ANALOG INTERFACE WITH EXTERNAL AUTO ZERO
2-52
TEXAS •
INSTRUMENTS
POST OFFICE BOX' 655012 • DALLAS, TeXAS 15265
I
~
J
TCM2909, TCM2910A
PCM ,,"LAW COMPANDING CODECS
TYPICAL APPLICATION INFORMATION
LINE
INTERFACE
DIGITAL
INTERFACE
SIGR
TCM2910A
CLKC
}
FROM SYSTEM
CONTROL
DCU-+---+
ANALOG {
INPUT
GAIN ADJUSTMENT
}:;~MESYNC "3.....
U)
ELECTRONIC HYBRIOS
CLKXn,.....---+
FSR
POWER AMPLIFIER
~---+
AND BIT CLOCKS
C3
~---
TRANSFORMER {
HYBRIOS
(J
U)
c
o
"';:::
co
(J
PCM
HIGHWAY
LEGE NO
ANALOG OIGITAL
GROUND GROUND
~
~
VCC
L------------t-4-
"2
j
E
E
o
(J
CD
"'i
FIGURE 11. TCM2910A INTERFACE WITH TCM2912C FILTER
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
I-
2-53
TCM2909, TCM2910A
PCM !'"LAW COMPANDING CODECS
TABLE 3a. p.-LAW POSITIVE INPUT VALUES
Reproduced from CCITTt (Volume III - 2 on Line Transmission)
Recommendation G.711 on Pulse Code Modulation of Voice Frequencies
I
Segment
number
2
3
Number
of intervals
at segment
X interval
end
size
Value
4
7
8
Value
at decoder
Decoder
6
5
O1aracter signal
Decision
points
Decision
value
number n
value Xn
(see Note A)
8159
(I28)D
(8159)
(see Note 0)
Bit number
output
outputYn
value
(see Note C)
number
I 2345678
- ------- I10000000
12
-t
(1)
8
16 X 256
7I
I
I
CD
(')
113
I
I
I
I
o
4063
3
3
7
16 X 128
c
:::s
C;'
2015
6
....
C»
16 X 64
112
I
I
I
0'
991
406
1
I
(I)
5
16 X 32
(')
::;'
479
c
2015
II
I
I
81
1055
1 001 1 1 1 1
I
:+
(I)
4
16 X 16
65
.511
I
I
J
16
x8
48
I
I
I
I
2
16
x4
I I I 1 1
I
15 X 2
16
I
I
I
~
64
-
I
I
I
I
I
I
I
I
I
I
I
I
231
48
-
I
I
I
I
I
I
I
I
I
I
I
I
99
32
I
I
I
I
I
I
I
I
I
I
I
I
33
16
I
239
223
I
I
I
I
(see Note E)
I
95
I
I
I
I
(see Note E)
I
I
35
31
I
I
I
2
3
(see Note E)
I
I I 1 I I I I 0
1
I XI
-
I
I
I
1
I
495
(see Note E)
I I 1 0 1 1 1 1
31
I-
I
I
I
I
I
17
I
I
I
I
I
I
I
o1
I
103
I
80
I
I
I
I
I
I
(see Note E)
479
I
I
I
1023
I
I
33
32
I-
I
I I 0 I 1 I I 1
95
I
I
I
I
I
I
I
I I 0 0 1 I 1 1
223
96
I
I
I
I
I
I
991
I
I
49
2079
(see Note E)
I
I
I
I
I
I
I
I-
I
96
64
I
I
I
I
I
I
(see Note E)
1
(')
112
I
I
I
I
I
I
I
I
I
2143
80
4191
I
4319
1 0 1 0 1 1 1 1
:::s
I-
(see Note E)
9~
I
I
I
I
I
I
I
I
1 0001 I I 1
127
8031
I
I
I
I
I
I
7903
I
I
I
I
I
I
I
I
I
I
I
2
I
0
0
I
-
1 I 1 1 I I I I
0
0
NOTES: A. 8159 normalized value units correspond to the value of the on-chip voltage reference.
B. The PCM word on the highways is the same as the one shown in column 6.
C. The voltage output on the ANLG OUT lead is equal to the normalized value given in the table, augmented by an offset. The
offset value is approximately 15 mV.
D. X128 is a virtual decision value.
E. The PCM word correspondihg to positive input values between two successive decision values numbered nand n + 1 (see
column 41 is (255 - nl expressed as a binary number.
tThe International Telegraph and Telephone Consultative Committee. Published by the International Telecommunication Union,
Geneva. Switzerland.
2-54
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM2909, TCM2910A
PCM WLAW COMPANDING CODECS
TABLE 3b. ,..LAW NEGATIVE INPUT VALUES
Reproduced from CCITTt (Volume III - 2 on Line Transmission)
Recommendation G.711 on Pulse Code Modulation of Voice Frequencies
1
Segment
number
2
3
Value
Number
of intervals
at segment
X interval
size
end
points
4
5
6
Character signal
Decision
value
Decision
value Xn
number n
(see Note A)
7
8
Value
(see Note B)
at decoder
Decoder
output
Bit number
outputYn
(see Note C)
number
value
1 2 3 4 5 6 7 8
i
0
0
1
-1
2
-3
I
I
I
I
I
I
16
-31
0 1 1 1 1 1 1 0
1
15 X 2
-31
I
I
-35
I
I
17
I
I
16 X 4
-95
I
32
16 X 8
-223
16 X 16
-479
5
16 X 32
-991
-95
_103
I
I
I
I
I
I
48
-223
49
-239
I
I
I
I
64
-479
65
-511
I
I
I
I
I
-991
I
80
16 X 64
-2015
7
16 X 128
-4063
-2015
97
I
-2143
I
I
I
I
I
112
-4063
I
126
-4319
I
-7647
127
-7903
113
8
16 X 256
I I I 1 I I
(128)E
(
-
a
I
I
I I 1 I I
96
I
I
I
I
I
I
I
I- -4191
112
I
I
I
I
I
(see Note D)
000000
8159) -
-
r-
I
I
I
I
U
en
c
o
'.;:0
C'CI
CJ
'2
:J
E
E
o
CJ
Q)
Q)
~
80
I
I- -2079
I
0 0 1 11 1
I
I
I
I
I
I
I
I
I
I
I
(see Note D)
o0
I
I
I
I
I
I
o0
64
I- -1023
(see ~ote D)
I)
48
I
I
I
I
I
I
I
o
I
I
I
I
I
I
-495
I
I 0 I I I 1
32
I
I
I
I
I
I
I
I
o0
-231
I
I
I
(see Note D)
I
0000000 I
RI59
~
I
I
96
I
I
I
I
-1055
I
I
I
I
I
I
-99
I
I
(see NOIe 0)
o0
~
-
I
...'Sen
CJ
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
(see NOIe 0)
I
81
6
1
I
I
I
I
I
-
I
0 I 0 0 I I 1 I
4
-2
1
16
I
0 1 0 1 1 1 1 1
3
0
-33
(see Note 0)
I
33
r-
(see Note D)
0 I 1 0 1 1 1 1
2
0
0 1 1 1 1 1 1 1
1X1
I
I
I
I
-7775
126
-R031
127
NOTES: A .. 8159 normalized value units correspond to the value of the on-chip voltage reference.
8. The PCM word on the highways is the same as the one shown in column 6.
C. The voltage output on the ANLG OUT lead is equal to the normalized value given in the table, augmented by an offset. The
offset value is approximately 15 mY.
D. The PCM word corresponding to positive input values between two successive decision values numbered nand n + 1 (see
column 41 is (255 - nl expressed as a binary number.
E. X 128 is a virtual decision value.
tThe International Telegraph and Telephone Consultative Committee. Published by the International Telecommunication Union,
Geneva, Switzerland.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-55
-t
CD
CD
n
o
3
3
c:::
::s
c;'
g)
r+
0'
::s
(I)
Q
~
n
c:::
;::;.'
(I)
2-56
TCM2912C
PCM LINE FILTER
02788, SEPTEMBER 1983-REVISED OECEM8ER 1
•
J
High-Pass Transmit Filter for Rejection of All
Low-Frequency Noise:
16 Hz .....•.•..•.... 70 dB Typical
50 Hz •.............. 35 dB Typical
60 Hz ............... 30 dB Typical
•
6th-Order Low-Pass Transmit Filter for
Improved Performance
•
Low Standby Power Consumption
DUAL-IN-LiNE PACKAGE
(TOP VIEW}
ANLG IN+
ANlG INGSX
VFRO
PWRI
PWRO+
PWROVBB
VFXO
ANlG GND
ClKSEL
PDN
ClK
DGTl GND
VFRI
VCC
•
Improved Envelope Delay Characteristics
•
Excellent Power Supply Rejection Ratio
•
CCITT G.712 as well as AT&T 03/04
Compatible
'3
Co)
•
TTL- and CMOS-Compatible
(3
•
Reliable N-Channel MOS Process
•
Pin-For-Pin Functional Replacement for
Intel 2912A
J!!
.
tn
C
o
'';:;
«J
•
Improved Noise Performance
•
Three-State PWRO + and PWRO - Outputs
Co)
'2
:::s
E
E
oCo)
description
The TCM2912C is a monolithic integrated circuit designed to implement the transmit and receive signal
filters of a PCM line or trunk termination. The transmit and receive passband filter sections are implemented
using switched capacitor techniques.
CD
"i
I-
The TCM2912C is primarily used in telephone system applications for switching, transmission, and remote
concentration. The transmit section provides a high-pass filter to ensure rejection of all low-frequency noise
as well as the anti-aliasing function required for an 8 kHz sampling system, A sixth-order low-pass filter
is provided in the transmit section for improved performance. The receive section has a smoothing lowpass filter and sin xix correction required for interface with TCM2910A or TCM2911A codecs. The
TCM2912C eliminates high-frequency switching noise for direct interface with transformer or electronic
hybrids. The power-down mode (standby) can be directly controlled by TCM2910A or TCM2911A type
codecs. When the TCM2912C is in the power-down mode, all outputs are in a high-impedance state.
The -3 versions are identical to the standard versions except that gain relative to gain at 1 kHz is - 0.7 dBm
minimum.
The TCM2912C is characterized for operation from OOC to 70°C.
Caution, These devices have limited bUilt-in gate protection, The leads shouid be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates,
PRODUCTION DATA ........1111 ....1.1. I."'....ti••
••rren! II of p.WiClli•• date. P..d.......form to
.,..me.Ii... ,.. I~. II.... 0' T.... Instnrll...11
:=;ar.::I:Ji =~~:I: :.:=~
lilt
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Copyright @ 1983. Texas Instruments Incorporated
2-57
TCM2912C
PCM LINE FILTER
system block diagram
TRANSMIT SECTION
ANLG IN+ . ;.11.;.;1_ _-f
ANLGIN_~12~1____;~~
>-4H~
SC
3RD·ORDER
HIGH·PASS
FILTER
ANTIALIAS
LOW·PASS
FilTER
SC
6TH-ORDER
LOW-PASS
FILTER
SMOOTHING
lOW·PASS
FILTER
1161 VFXO
GSX~13~1___________~
SUPPORT SECTION
CLKSEl 1141
ClK 1121
2-PHASE
CLOCK
GENERATOR
RECEIVE SECTION
PWRO- .,;;17;..;,1...._
PWRO+~16~1
C
SMOOTHING
lOW·PASS
FILTER
_____________~
PWRI
-+
SC
SIN xIx
LOW·PASS
FilTER
f-+
2-POlE ACTIVE
PRE·FILTER
~ OIVFR
1141
VFRO
The TCM2912C system block diagram is divided into three sections: transmit, receive, and support. The
transmit section provides bandpass filtering to eliminate unwanted switching and low·frequency noise
signals. The receive section provides a 2·pole active pre·filter to filter out high· frequency components that
are present on the analog output of the codec. Since the filter is a sampled data system, the components
could alias down into the voice band and create low-frequency gain tracking and S/Q problems. Following
the pre-filter is a sixth-order low-pass filter that provides sin x/x correction for the codec. The receive section
provides sin x/x correction for the codec and elimination of high-frequency switching signals. The receive
section has optional output buffers. The support section provides clock generation.
2-58
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM2912C
PCM LINE FILTER
PIN
NAME
DESCRIPTION
NO.
Analog return common to the transmit and receive analog circuits. Not connected to DGTL GND internally.
ANlG GND
15
ANlG IN-
2
Inverting input of the gain adjustment operational amplifier on the transmit filter
ANlG IN+
1
Analog input of the transmit filter. The ANlG IN + signal comes from the 2- to 4-wire hybrid in the case
of a 2-wire line and goes through the high-pass filter and antiallasing filter before being sent to the codec
for encoding.
ClK
12
Clock input. Three clock frequencies can be used: 1.536 MHz, 1.544 MHz, or 2.048 MHz. Frequency is
selected by ClKSEl (pin 14).
ClKSEl
14
Clock frequency selection. Input must be connected to
Vss. Vee,
or ground to reflect the master clock
frequency at pin 12 (ClK). When tied to VBB, ClK is 1.536 MHz. When tied to ground, elK is 1.544 MHz.
When tied to VCC, ClK is 2.048 MHz.
DGTl GND
GSX
11
3
Digital ground return for internal clock generator.
Output of the gain adjustment operational amplifier on the transmit filter. Used for gain setting of the transmit
filter.
PDN
13
Control input for standby power-down mode. An internal pullup to 5 volts is provided for interface to the
5
High-impedance input to the power driver amplifiers on the receive side of interface to transformer hybrids.
When taken to the low level (tied to VSS), the power amplifiers are powered down.
PWRO-
7
Inverting side of power amplifiers. Power driver output capable of directly driving transformer hybrids.
PWRO+
6
Noninverting side of the power amplifiers. Power driver output capable of directly driving transformer hybrids.
VBB
8
- 5 V ± 5% referenced to ANlG GND
VCC
9
VFRI
10
fI)
U
fI)
c
o
"+I
CCI
CJ
codec PDN outputs.
PWRI
....
...CJ
"S
5 V ± 5% referenced to ANlG GND
"2
::s
E
E
oCJ
CD
"ii
t-
Analog input of the receive filter, interface to the codec analog output for PCM applications. The receive
filter provides the sin xix correction needed for sample-and-hold-type codec outputs to give unity gain. The
input voltage range is directly compatible with TCM2910A codecs.
VFRO
4
Analog output of the receive filter. Provides a direct interface to electronic hybrids. For a transformer hybrid
application, VFRO is tied to PWRI and a dual balanced output is provided on pins PWRO + and PWRO - .
VFXO
16
Analog output of the transmit filter. The output voltage range is directly compatible with the TCM2910A
codecs.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
2-59
TCM2912C
PCM LINE FILTER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ..................................... -0.3 V to 14 V
Output voltage, Vo all outputs (see Note 1) .............................. -0.3 V to 14 V
Output current, 10 (all outputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ± 50 mA
Continuous total dissipation at 25°C free-air temperature (see Note 2) ............... 1375 mW
Operating free-air temperature range ...................................... ODC to 70 DC
Storage temperature range ......................................... - 65 DC to 150 DC
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds ...................... 300 DC
NOTES:
-I
(1)
1. Voltage values are with respect to VBB.
2. For operation above 25·C free-air temperature, derate linearly to 880 mW at 70·C at the rate of 11 mWI ·C.
recommended operating conditions
Ci'
(')
o
3
3
c
::::s
c:;'
I»
MIN
NOM
MAX
VCC
Supply voltage (see Note 3)
4.75
5.25
V
VBB
Supply voltage (see Note 3)
-4.75
5
-5
-5.25
V
V)H
DGTL GND voltage with respect to ANLG GND
High-level input voltage
All inputs except CLKSEL
VIL
Low-level input voltage
...0"
0
All inputs except CLKSEL and PWRI
PWRI
(II
RL
(")
Load resistance
:;"
0.8
VBB
VCC-0.5
ANLG GND-0.5
For 1.544 MHz
For 1.536 MHz
::::s
At GSX. VFXO, or VFRO
VBB
10
At PWRO + or PWRO - (Single-ended)
300
At PWRO + and PWRO - (differential)
600
(')
C
CL
Load capacitance
(II
TA
V
VBB+0.5
VCC
0.8
V
VBB+0.5
kll
!l
At GSX, VFXO, or VFRO
;:+"
V
2.2
For 2.048 MHz
Clock select input voltage
UNIT
25
At PWRO + or PWRO - (Single-ended)
100
At PWRO + and PWRO- (differential)
200
Operating free-air temperature
70
0
pF
·C
NOTE 3: Voltages at analog inputs, analog outputs, VCC' and VBB terminals are with respect to the ANLG GND terminal. All other voltages
are referenced to the DGTL GND terminal unless otherwise noted.
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
digital interface
PARAMETER
II
2-60
Input current
TEST CONDITIONS
I PDN
I CLKSEL
VI - GND to Vec
VI = VBB to 2.2 V
LCLK
VI - 0.8 V to 2.2 V
MIN
MAX
UNIT
100
1
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
1
p.A
TCM2912C
PCM LINE FILTER
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(continued)
supply current
PARAMETER
ICC
Supply current
from VCC
Supply current
IBB
from VBB
MIN Typt
TEST CONDITIONS
Standby
PDN at 2.2 V
Operating
Power amplifiers active
PWRI at VBB
Standby
PDN = 2.2 V
Operating
Power amplifiers active
12
15
9
11
mA
-0.4
Power amplifiers inactive,
Operating
UNIT
0.4
Power amplifiers inactive,
Operating
MAX
PWRI at VBB
-12
-15
-9
-11
mA
...
'S
U)
transmit amplifier input
..
(J
TEST CONDITIONS
PARAMETER
Input leakage current at ANLG IN +. ANLG IN-
VI
=
MIN Typt
-2.2 V to 2.2 V
Input offset voltage at ANLG IN +, ANLG INCommon-mode rejection at ANLG IN +, ANLG IN
RL = 10 kll
VI - -1.6 V to 1.6 V (
Common-mode rejection at ANLG IN +, ANLG IN-
VI -
Output voltage swing at GSX
3 dBmO)
- 2.2 V to 2.2 V (0 dBmO!
DC open-loop voltage amplification at GSX
MAX
UNIT
±100
nA
±25
mV
U)
C
o
±2.5
V
60
dB
'~
,!::!
cj
60
90
dB
72
77
dB
1
Open-loop unity gain bandwidth at GSX
Input resistance at ANLG IN +, ANLG IN-
(3
MHz
10
Mil
CO
E
E
o
transmit filter
PARAMETER
TEST CONDITIONS
DC output offset voltage at VFXO
Output voltage swing at 1 kHz at VFXO
MIN Typt
ANLG IN + connected to ANLG GND,
Amplifiers at unity gain
RL", 10 kll
MAX
UNIT
±100
mV
±3.2
Q)
I-
V
1
Output resistance at VFXO
(J
Q)
2
II
receive filter
PARAMETER
TEST CONDITIONS
DC output offset voltage at VFRO
VFRI connected to ANLG GND
Output voltage swing at VFRO
RL
Input leakage current at VFRI
VI -
=
10 kll
MAX
UNIT
± 100
mV
1
~A
V
±3.2
- 3.2 V to 3.2 V
1
Input resistance at VFRI
Mil
1
Output resistance at VFRO
t All typical values are at VBB
MIN Typt
-5 V, VCC
5V,andTA
2
II
25°C.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-61
TCM2912C
PCM LINE FILTER
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(continued)
receive filter driver amplifier
PARAMETER
RL connected to ANLG GND
Differential output voltage
Balanced connection, RL connected
swing at PWRO +. PWRO-
between PWRO + and PWRO-
Input leakage current at PWRI
CD
(')
c
PWRO +. PWRO-
at PWRO +. PWRO-
(1)
o
3
3
Single ended connection,
De output offset voltage
-I
~
(I)
c
RL = 30011
±2.9
±2.5
RL - 20 kll
±6.4
RL = 1200 II
+5.B
RL=60011
MAX
V
+5
±50
±0.5
10
Output resistance at
10 slOmA.
Vo = -3 V to 3 V
UNIT
V
PWRI connected to ANLG GND
PARAMETER
...0"
::+
RL = 60011
VI = -3.2 V to 3.2 V
PWRO +, PWRO-
(i"
::;"
±3.2
mV
~A
Mil
1
2
MIN TVPt
MAX
II
power supply rejection (see Note 4)
I»
(')
RL = 10 kll
Input resistance at PWRI
~
(")
MIN TVPt
TEST CONDITIONS
Output voltage across RL at
TEST CONDITIONS
UNIT
SVRRl
Vee supply voltage rejection ratio
Transmit channel only
30
45
dB
SVRR2
VBB supply voltage rejection ratio
Transmit channel only
30
45
dB
SVRR3
Vee supply voltage rejection ratio
Receive channel only
30
45
dB
SVRR4
VBB supply voltage rejection ratio
Receive channel only
30
45
dB
t All
typical values are at VBB = -5 V, Vee = 5 V. end TA = 25°e.
NOTE 4: With the test device acting as a transmitter (or receiver), a 200-mV peak-to-peak 1.02-kHz signal is applied to the appropriate
supply pin and measurements are made at the VFXO (or VFRO) output with the receiver (or transmitter) and power amplifiers
in idle channel conditions.
(I)
2-62
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TeXAS 75265
TCM2912C
PCM LINE FILTER
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
(continued)
transmit filter transfer
PARAMETER
TEST CONDITIONS
MIN
16.67 Hz
50 Hz
Typt
MAX
-80
-60
-30
-25
60 Hz
-1.2
-0.125
300 Hz to 3 kHz
-0.125
0.125
3.3 kHz
-0.35
0.1
-0.1
Gain-setting operational
200 Hz
Gain relative to gain at
amplifier at unity gain,
1 kHz with O·dBmO input signal
O-dBmO reference measured
at VFXO (see Note 5)
3.4 kHz (TCM2912C-3)
3.4 kHz (TCM2912C)
-0.7
-1
Gain variation with temperature
Gain variation with supply voltage
Crosstalk attenuation, receive
to transmit at VFXO
f
1 kHz, RL = 10 kll
1 kHz, Signal level = 0 dBmO
1 kHz, Signal level
Supply variation
VFRI
=
=
=0
2.8
=
Dilferential envelope delay time
U)
u
dB
dBfoC
dBN
1 kHz,
70
80
dB
ANLG IN + connected to ANLG GND
I
=
=
1 kHz, Signal level
1 kHz, Signal level
=0
=3
-45
Gain setting operational amplifier at unity gain
4
6
4
6
60
100
80
150
=
1 kHz to 2.6 kHz
Absolute delay time
tAli typical values are at VBB = -5 V, VCC = 5 V, and TA = 25°C.
NOTE 5: A O-dBmO signal is equivalent to 1.1 V rms at ANLG IN + and 1.6 V rms output at VFXO.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
c
o
.;
ca
u
"2
-48
dBmO at VFXO
dBmO at VFXO
Gain setting operational amplifer at 20-dB gain
I
..
C3
"5
U)
Gain-setting operational amplilier at 20-dB gain
Total C-message noise at VFXO
3.2
0.04
± 5%
1.6 V rms, f
3
0.0008
dBmO,
ANLG IN - connected to GSX,
I
Single-frequency distortion products
=
=
=
....
-35
4.6 kHz and above
f
f
dBm
-0.1
-14
4 kHz
Absolute passband gain at VFXO
UNIT
dB
dBrnCO
~s
!,s
::::I
E
E
o
u
CD
'i)
t-
2-63
TCM2912C
PCM LINE FILTER
electrical characteristics over recommended ranges of supply voltage and operating fr. .alr temperature
(continued)
receive filter transfer
PARAMETER
•
TEST CONDITIONS
Gain relative to
1 kHz with 0 dBmO input signal
o dBmO measured at VFRO
Absolute passband gain at VFRO
f - 1 kHz, RL - 10 kD
f=1kHz,
Signal level = 0 dBmO
f=lkHz,
Signal level = 0 dBmO,
Supply variation = ± 5%
ANLG IN - connected to GSX,
ANLG IN+ at 1.1 V rms, f = 1 kHz,
VFRI connected to ANLG GND
f=lkHz,
Input signal = 0 dBmO
f = 1 kHz,
Input signal = 3 dBmO
Measured at VFRO
f = 1 kHz to 2.6 kHz
-I
CD
i"
C')
Gain variation with temparature
o
3
3
Gain variation with supply voltage
c
=
C:;'
..
Crosstalk attenuation, transmit to
receive at VFRO
CD
0'
o
=
Single-frequency distortion
products
~r
Total C-mesaage noise at VFRO
Differential envelope delay time
::+
o
Absolute delay time
C')
c
below 200 Hz
200 Hz
300 Hz to 3 kHz
3.3 kHz
3.4 kHz (TCM2912-3)
3.4 kHz (TCM2912)
4 kHz
4.6 kHz and above
I VFRO
I
PWRO-
tAli typical values are at VBB = -5 V, VCC = 5 V, and TA = 25°C
2-64
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 76265
MIN
TVPt
-0.2
-0.2
-0.126
-0.35
-0.7
-1
N!AX
0.126
0.126
0.126
0.03
-0.1
-0.1
-14
-36
0.2
-0.2
dBm
dB
dB/oC
0.0002
dBN
0.04
70
UNIT
76
dB
-46
-45
4
26
110
120
dB
6 dBrnCO
BO
,.s
140'
,.s
lBO
TCM2912C
PCM LINE FILTER
TRANSFER CHARACTERISTICS OF THE
TRANSMIT SECTION
+0.125 dB
300Hz
+0.125 dB
3000 Hz
o
+0.1 dB
3300 Hz
3400 Hz
-1
o
EXPANDED
SCALE
-1
II
U)
,1:::
.
U
:;,
3400 Hz
Co)
III
1
..
U)
...
c
:t
Ii
'
.j
Cl
o
m
,~
s
Ia:.
-20
·iCl
c:;,
E
E
oCo)
II)
-a;
....
Frequency-Hz
FIGURE 1
tApplies to the TCM2912C-3 only.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-65
TCM2912C
PCM LINE FILTER
TRANSFER CHARACTERISTICS OF THE
RECEIVE SECTION
, .....
+2
I
/ I
I
TYPICAL FILTER
/
TRANSFER FUNCTION - - - . , /
+1
0.125 dB
200 Hz
-I
0.125 dB
300 Hz
",/
,/
'I
I
I
I
!
EXPANDED
SCALE
0.125 dB
3000 Hz
0
CD
CD
(')
0
3
3
III
-1
i'
c:
~
5"
CI)
.....
N
:z:
...
0"
Ii
.~
0
CJ
S
~
(I)
0
I•
(')
·IiCJ
TYPICAL FILTER TRANSFER
FUNCTION WHEN MULTIPLIED BY
II! -10
::;"
c:
-14 dB
::;'
(I)
-20
SINx
WHICH IS THE--OUTPUT RESPONSE
x
-30
OF THE TCM2910A CODEC
WHERE x -
rl
8000
-40
-oo~-~---~----------~------------~~--~--~
100
1k
Frequency-Hz
FIGURE 2
t Applies
2-66
to the TCM2912C-3 only.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
10k
TCM2912C
PCM LINE FILTER
TYPICAL APPLICATION DATA
r--------I
-------Ir-- - - -TCM2912C
ANLGIN+
ANLGIN-
TCM2912C
"
VFRO
I
I
GSX
R2
I
...
Rl
I OUTPUT
I RESISTANCE
R1
I
I
I
I
IL ________ _
_-----------Z= LOAD
I
R2
...
U)
..
C3
"5
R2' Z
RT- R1 + - = 10k.!1
R2+Z
'GAIN = 1 (R2/R11
FIGURE 3. PASSBAND GAIN ADJUSTMENT
FIGURE 4. OUTPUT GAIN ADJUSTMENT FOR RECEIVE
FILTER IF DRIVER AMPLIFIER IS NOT USED.
VFRO
r-- -- --- ------TCM2912C
I
*R1
PWRI
I
I
CJ
U)
c
o
"';::;
ca
CJ
"2
:::J
OUTPUT
RESISTANCE
E
E
o
CJ
"R2
C\)
G)
t-
+
"GAIN SETTING RESISTORS
··SERIES LEAD RESISTOR
I
."._ _ _ _ _ _
L FILTER
_________
FIGURE 5. TYPICAL CONNECTION FOR OUTPUT DRIVER
AMPLIFIER WITH EXTERNAL GAIN ADJUST
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • OAlLAS, TEXAS 75265
2-67
TCM2912C
PCM LINE FILTER
TYPICAL CHARACTERISTICS
DEPARTURE FROM LINEAR PHASE
TCM2912C
TRANSMIT SECTION
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
c: 0.2
.!!!
0
IV
a: -0.2
-0.4
-0.6
-0.8
-1.0
-I
CD
CD
(')
~
o
3
3
.,
I:
:::s
c;"
Q)
r+
0"
:::s
en
-1.2
-1.4
-1.6
-1.8
(")
:::;;"
(')
I:
0.5
;:;'
en
1.5
2
2.5
3
Frequency-kHz
FIGURE 6
FROM: DIGITAL CHANNEL BANK REQUIREMENTS AND OBJECTIVES, AT&T, JUNE 1978, PUB 43801, PARAGRAPH 13.4.
2-68
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
DIGITAL
INTERFACE
SIGX------------------------------------------------------------------,
TCM2910A
SIGR-----------------~
CAPXl
}
FROM SYSTEM
CONTROL
CAPX2
ANLG
IN
VBB
ANALOG INPUT {
AUTO
ZERO
ANLG
GND
GAIN ADJUSTMENT
TO ELECTRONIC HYBRIDS
~
~
-
~
ilZ
~~
~ ;o~
~C:~
oS:
SIGR
FROM PCM
FRAME SYNC
AND BIT CLOCKS
POWER AMPLIFIER INPUT
-<
"tI
C')
l>
,~,,_U,,"
{
OUTPUT TO
I""
l>
"tI
"tI
I""
TRANSFORMER
HYBRIDS
~(Tl
~Z
-t
n
l>
-t
(5
VBB
~ Ul4r
2:
0
~
~
PCM
m
~
HIGHWAY
l>
-t
l>
LEGEND
ANALOG
GROUND
DIGITAL
GROUND
~
~
Vce
~
NOTE: CLK
~
1.544 MHz, with CLKSEL connected to ANLG GND.
'*
."
(")
:s::
r-
FIGURE 7. TCM2912C INTERFACE WITH TCM2910A CODEC
Texas Instruments reserves the right to make changes at any time in order to improve design and to supply the best product possible.
Texas Instruments assumes no responsibility for infringement of patents or rights of others based on Texas Instruments applications assistance or product
specifications, since TI does not possess full access to data concerning the use or applications of customer's products. TI also assumes no responsibility
for customer product designs.
N
en
(0
Telecommunications Circuits
--I
2(")
m:s::
"TIN
i==
-ImN
= (")
-
2-70
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
D2765, SEPTEMBER 1983-REVISED JUNE 1988
TCM2913
J DUAL-iN-LINE PACKAGE
(TOP ViEW)
NOT RECOMMENDED FOR NEW DESIGN
•
For New Design Refer to TCM29C13.
TCM29C14. TCM29C16. and TCM29C17.
VBB
PWRO+
PWROGSR
PDN
CLKSEL
DCLKR
PCM IN
FSR/TSRE
DGTL GND
FEATURE TABLE
FEATURE
2913
2914
2916
2917
X
X
Number of Pins:
24
20
16
wlaw/A-law Coding:
It-law
A-law
Data Timing Rates:
Variable Mode
64 kHz to 2,048 MHz
Fixed Mode
1,536 MHz
1_544 MHz
2,048 MHz
Loopback Test Capability
8th-Bit Signaling
X
X
X
X
X
X
X
X
X
X
X
X
X
VCC
GSX
ANLG INANLG IN+
ANLG GND
ASEL
TSX/DCLKX
PCM OUT
FSX/TSXE
CLKR/CLKX
...
U)
'S
X
X
TCM2914
JW DUAL-iN-LINE PACKAGE
(TOP ViEW)
C3
..
U)
X
VBB
PWRO+
PWROGSR
PDN
CLKSEL
ANLG LOOP
X
X
...
(,)
X
X
X
X
description
DCLKR
PCM IN
FSR/TSRE
DGTL GND
The TCM2913. TCM2914. TCM2916. and
TCM2917 are single-chip pulse-code-modulated
encoders and decoders (PCM codecs) and PCM
line filters, These devices provide all the
functions required to interface a full-duplex
(4-wire) voice telephone circuit with a timedivision-multiplexed (TDM) system, These
C
VCC
GSX
ANLG INANLG IN+
ANLG GND
NC
SIGX/ASEL
TSX/DCLKX
PCM OUT
FSX/TSXE
CLKX
CLKR
'
0
ca
(,)
'2
::::J
E
E
0
(,)
CD
'i)
I-
TCM2916, TCM2917
J DUAL-iN-LINE PACKAGE
(TOP ViEW)
VBB
PWRO+
PWROPDN
DCLKR
PCM IN
FSR/TSRE
DGTL GND
VCC
GSX
ANLG INANLG GND
TSX/OCLKX
PCM OUT
FSX/TSXE
CLKR/CLKX
Caution, These devices have limited built-in gate protection, The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates,
PRODUCTION DATA documenls contain information
current as of publication data. Products conform to
spacificatlons par the tarms of TaxIs Instruments
:'~~~:=i~ai~r:1~1i ~:g::i:; :I~O:~::~:~~ not
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright © 1983, Texes Instruments Incorporated
2-71
TCM2913. TCM2914. TCM2916. TCM2917
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
description (continued)
devices are intended to replace the TCM291 OA in tandem with the TCM2912C. Primary applications of
the devices include:
• Line Interface for Digital Transmission and Switching of T1 Carrier, PABX, and Central Office
Telephone Systems
• Subscriber Line Concentrators
• Digital Encryption Systems
• Digital Voice Band Data Storage Systems
• Digital Signal Processing
These devices are designed to perform the transmit encoding (AID conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. They
are intended to be used at the analog termination of a PCM line or trunk.
-I
CD
CD
(')
The TCM2913, TCM2914, TCM2916, and TCM2917 provide the bandpass filtering of the analog signals
prior to encoding and after decoding. These combination devices perform the encoding and decoding of
voice and call progress tones as well as the signaling and supervision information.
o
3
3
c
The TCM2913, TCM2914, TCM2916, and TCM2917 are characterized for operation from OOC to 70°C.
The TCM2913-3 version is identical to the standard version except that maximum encoder milliwatt
response and digital milliwatt response are ± 0.40 dBmO.
:::s
m
5'
...
0'
functional block diagram
:::s
(I)
TRANSMIT
SECTION
AUTO
ZERO
(")
::;'
(')
C
ANLGIN+
(I)
ANLG IN-
;:;"
GSX
SAMPLE
AND HOLD
ANDDAC
COMPARA·
TOR
SUCCESSIVE
APPROXI·
PCMOUT
TlX'IDCLKX
SIGX/ASEL
-.l-__-.J
ANALOG
TO DIGITALI-_ _ _ _ _ _ _......JL-_-+_ FSX/TSXE
CONTROL
CLKX
LOGIC
RECEIVE
SECTION
CLKSEL
PDN
ANLG Loopt
GSR
PCMIN
PWRO+-....._ - - - - .
DCLKR
PWRO-_.........--..::....J
L...--+-SIGRt
vee
tTCM2914 only
*TCM2913, TCM2916, and TCM2917 only
2-72
Vaa OGTL ANLG
FSRITSRE
GND GND
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75285
CLKRt
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
PIN
TCM2913
TCM2914
1
1
2
2
TCM291e
NAME
TCM2917
1
VBB
2
PWRO+
DESCRIPTION
Most negative supply voltage; input is - 5 V ± 5%.
Noninverting output of power amplifier. Can drive transformer hybrids or
high-impedance loads directly In either a differential or a single-ended
configuration.
3
3
4
4
3
PWRO-
Inverting output of power amplifier; functionally identical with and
complementary to PWRO + .
GSR
Input to the gain-setting network on the output power amplifier.
Transmission level can be adjusted over a 12-dB range depending upon
5
4
Pi5fii
Power-down select. The device is inactive with a TIL low-level input to
this pin and active with a TTL high-level input to the pin.
e
ClKSEl
6
ANlG lOOP
7
Clock frequency selection. Input must be connected to VBB, VCC, or
ground to reflect the master clock frequency. When tied to VBB, ClK is
2.048 MHz. When tied to ground, ClK is 1.544 MHz. When tied to VCC,
ClK is 1.536 MHz.
Provides loopback test capability. When this input is TTL high, PWRO +
is internally connected to ANlG IN.
SIGR
8
Signaling bit output, receive channel; in a fixed-data-rate mode, outputs
the logical state of the 8th bit (lSBI of the PCM word in the most recent
signaling frame.
7
9
5
DClKR
en
..
':;
the voltage at GSA.
5
fI
..
Selects fixed or variable data-rate operation. When this pin is connected
to VaB' the device operates in the fixed-data-rate mode. When DClKR
is not connected to VBB, the device operates in the variable-data-rate
mode, and DClKR becomes the receive data clock, which operates at
U
(3
en
C
o
'+:
as
u
'2
:::l
E
E
o
u
CD
'ii
~
frequencies from 64 kHz to 2.048 MHz.
8
10
6
PCM IN
7
FSRITSRE
Receive PCM input. PCM data is clocked in on this pin on eight consecutive
negative transitions of the receive data clock, which is ClKR in fixed-datarate timing and DClKR in variable-data-rate timing.
9
11
Frame synchronization clock input/time slot enable for receive channel.
In the fixed-data-rate mode, FSR distinguishes between signaling and nonsignaling frames by a
double~
or single-length pulse, respectively. In the
variable-data-rate mode, this signal must remain high for the duration of
the timeslot. The receive channel enters the standby state when FSR is
TIL low for 300 ms.
10
12
8
DGTl GND
Digital ground for all internal logic circuits. Not internally connected to
ANlG GND.
11
13
9
ClKR
Receive master clock and data clock for the fixed-data-rate mode. Receive
master clock only for variable-data-rate mode. ClKR and ClKX are
internally connected together for TCM2913, TCM2916, and TCM2917.
TEXAS ."
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS. TeXAS 76266
2-73
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE·CHIPPCM CODEC AND FILTER
PIN
TCM2913
TCM2914
11
14
TCM2916
NAME
DESCRIPTION
TCM2917
9
CLKX
Transmit master clock and data clock for the fixed-data-rate mode.
Transmit master clock only for variable data rate mode. CLKR and CLKX
are internally connected for the TCM2913, TCM2916, and TCM2917.
12
15
10
FSX/TSXE
Frame synchronization clock input/time-slot enable for transmit channel.
Operates independently of, but in an analagous manner to, FSR/TSRE.
The transmit channel enters the standby state when FSX is TTL low for
300 ms.
-4
13
16
11
PCM OUT
Transmit PCM output. PCM data is clocked out on this output on eight
consecutive positive transitions of the transmit data clock, which is CLKX
<11
CD
in fixed-data-rate timing and DCLKX in variable-data-rate timing.
(')
0
14
17
12
TSX/DCLKX
3
3
output to be used as an enable Signal for a three-state buffer. In the
variable-data rate mode, DCLKX becomes the transmit data clock, which
C
:::J
(')
Q)
r+
Transmit channel time slot strobe (output) or data clock (input) for the
transmit channel. In the fixed-data-rate mode, this pin is an open-drain
operates at TTL levels from 64 kHz to 2.048 MHz.
15
18
SIGX/ASEL
Used to select between A-law and Wlaw operation. When connected to
VBB, A~law is selected. When connected to Vee or ground, wlaw is
O·
selected. When not connected to VBB, it is a TTL-level input that is
:::J
transmitted as the eighth bit (LSB) of the PCM word during signaling frames
CI)
on the PCM OUT pin (TCM2914 only). SIGX/ASEL is internally connected
(")
:::;;.
to provide p.-Iaw operation for TCM2916 and A-law operation for
(')
TCM2917.
C
;::;:
16
20
13
ANLG GND
CI)
Analog ground return for alt internal voice circuits. Not internally connected
to DGTL GND.
17
21
ANLG IN+
18
22
14
ANLG IN-
19
23
15
GSX
Noninverting analog input to uncommitted transmit operational amplifier.
Internally connected to ANLG GND on TCM2916 and TCM2917.
Inverting analog input to uncommitted transmit operational amplifier.
Output terminal of internal uncommitted operational amplifier. Internally,
this is the voice signal input to the transmit filter.
20
2·74
24
16
VCC
Most positive supply voltage; input is 5 V ± 5%.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TEXAS 75265
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
absolute maximum ratings over operating free· air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .....................................
Output voltage, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Digital ground voltage ..............................................
-
e
'
..
. temperature ........... "
ontlnuous
tota I d'Isslpatlon
at (orb eIow ) 25 0 e f ree·alr
0.3
0.3
0.3
0.3
V
V
V
V
to
to
to
to
15
15
15
15
V
V
V
V
See
Dissipation
Rating
Table
Operating free-air temperature range (under bias) . . . . . . . . . . . . . . . . . . . . . . . . .. - 10 °e to 80 0 e
Storage temperature range ......................................... - 65 °e to 150 0 e
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or JW package ....... 300 0 e
...en
DISSIPATION RATING TABLE
DERATING
DERATE
ABOVE TA
PACKAGE
TA '" 25·C
POWER RATING
J
1375 mW
FACTOR
11.0 mW/oC
JW
1375 mW
no derating
25°C
..
'S
TA - BO·C
POWER RATING
(J
(3
en
t:
o
770mW
1375 mW
NOTE 1: Voltage values for maximum ratings are with respect to VBB.
'~
recommended operating conditions
CO
MIN
VCC
Supply voltage (see Note 2)
VBB
Supply voltage
VIH
VIL
Low-level input voltage, all inputs except CLKSEL
RL
Load resistance
CL
Load capacitance
TA
Operating free-air temperature
UNIT
4.75
5
5.25
V
-5
-5.25
V
V
0
High-level input voltage, all inputs except CLKSEL
input voltage
MAX
-4.75
DGTL GND voltage with respect to ANLG GND
Clock select
NOM
For 2.04B MHz
For 1.544 MHz
For 1.536 MHz
AtGSX
At PWRO + andlor PWRO-
2.2
V
O.B
V
VBB
0
VBB+O.5
0.5
V
Vee- O.5
10
Vee
100
0
:::s
E
E
o
(J
CI)
....Q)
0
50
At PWRO + andlor PWRO-
'2
kO
300
At GSX
(J
70
pF
°c
NOTE 2: Voltages at analog inputs and outputs, VCC, and VBa terminals are with respect to the ANLG GND terminal. All other voltages
are referenced to the DGTL GND terminal unless otherwise noted.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-75
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
electrical characteristics over recommended ranges of supply voltage and operating free·air temperature
supply current, fOCLK - 2.048 MHz, outputs not loaded
PARAMETER
TEST CONDITIONS
ICC
Standby
from VCC
= VIL after 300 ms
= VIL after 10 ""
FSX. FSR
Power-down
PDN
Operating
Supply current
IBB
MIN
Operating
Supply current
Standby
from VBB
FSX, FSR - VIL after 300 ms
Power-down
PDN
=
VIL after 10 ~s
Operating
Power dissipation
Standby
-4
FSX, FSR - VIL after 300 ms
Power down
PDN
(1)
CD
n
PARAMETER
~s
VOL
IIH
IlL
Ci
r+
0"
Co
::::J
TEST CONDITIONS
I PCM OUT
I SIGR
VOH High-level output voltage
c
::::J
5"
D)
o::::;"
VIL after 1 0
MAX
14
19
1.2
2.4
0.5
-18
1
-24
-1.2
-2.4
-0.5
-1
140
226
12
25
5
10.5
Typt
MAX
UNIT
mA
mA
mW
digital interface
o
3
3
til
=
Typt
IOH
IOH
Low·level output voltage at PCM OUT, TSX, SIGR
= -9.6 mA
= -1.2 mA
= 3.2 mA
High-level input current, any digital input
IOL
VI -2.2 V to VCC
Low-level input current. any digital input
VI
=
MIN
2.4
V
2.4
0 to 0.8 V
Input capacitance
Output capacitance
UNIT
5
0.4
V
10
~A
10
pA
pF
10
pF
5
transmit amplifier input
PARAMETER
n
c
;::;:
til
TEST CONDITIONS
Input current at ANLG IN +, ANLG IN-
VI
Input offset voltage at ANLG IN +, ANLG IN-
VI
Common-mode rejection at ANLG IN +, ANLG IN-
VI
=
=
=
MIN
TYpt
-2.17 Vto 2.17 V
~2.17
V to 2.17 V
- 2. 17 V to 2.17 V
Open-loop voltage amplification at GSX
MAX
nA
±25
mV
55
dB
5000
Open-loop unity-gain bandwidth at GSX
1
Input resistance at ANLG IN +, ANLG IN-
MHz
10
MO
receive filter output
PARAMETER
TEST CONDITIONS
Output offset voltage PWRO +, PWRO -Ising Ie-ended)
Relative to ANLG GND
Output resistance at PWRO +, PWROtAli typical values are at VBB
2-76
=
UNIT
±100
-5 V, VCC = 5 V, and TA
= 25°C.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MIN
Typt
120
MAX
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
gain and dynamic range. Vee = 5 V. VBB (see Notes 3. 4. and 5)
25°e (unless otherwise noted)
-5 V. TA
PARAMETER
TEST CONDITIONS
Encoder milliwatt response
Signal input = 1.064 V rms
(transmit gain tolerance)
Encoder milliwatt response variation with
TA = OOC to 70 oC,
temperature and supplies
Supplies = ± 5%
MIN
I Standard versions
I TCM2913-3
Output signal = 1 kHz
Digital milliwatt response variation with
TA = OOC to 70 D C,
temperature and supplies
Supplies = ± 5 %
Zero-transmission-Ievel
point, transmit channel
(0 dBmO)
Wlaw
A-law
,,-law
A-law
Zero-transmission-Ievel
pOint, receive channel
(0 dBmO)
Wlaw
A-law
wlaw
A-law
MAX
±O.lB ±0.40
±0.07
±0.08 ±0.18
Digital milliwatt response (receive tolerance gain) Signal input per CCITT G.7111 Standard versions
relative to zero-transmission level pOint
TYP
±0.08 ±0.18
I TCM2913-3
±O.lB ±0.40
±0.07
UNIT
dBmO
dB
dBmO
dB
2.76
RL = 600 II
CI)
2.79
RL = 600 II
...
5.76
(J
5.79
CI)
dBm
4
RL=90011
~
Co)
1.03
1
RL = 900 II
"~
dBm
C
o
4.03
"';:::;
NOTES: 3. Unless otherwise noted, the analog input is a O-dBmO, 1020-Hz sine wave, where 0 dBmO is defined as the zero-reference
pOint of the channel under test. This corresponds to an analog signal input of 1 .064 V rms, or an output of 1.503 V rms.
4. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a O-dBmO, 1020-Hz sine
wave through an ideal encoder.
5. Receive output is measured single-ended in the maximum-gain configuration. To set the output amplifier for maximum gain,
GSR is connected to PWRO - and the output is taken at PWRO +. All output levels are (sin xlix corrected.
gain tracking over recommended ranges of supply voltage and operating free-air temperature. reference
level - - 10 dBmO
PARAMETER
TEST CONDITIONS
-3 to -40 dBmO
Transmit gain tracking error, sinusoidal input
MAX
±0.5
-50to -55dBmO
+1.2
±0.5
-50 to -55 dBmO
±1.2
TEXAS ...,
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
o
Co)
CI)
Q)
I-
dB
±0.25
-40 to -50 dBmO
INSTRUMENTS
UNIT
~
E
E
±0.25
-40 to -50 dBmO
-3 to -40 dBmO
Receive gain tracking error, sinusoidal input
MIN
ca
c
"~
dB
2-77
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE·CHIP PCM CO DEC AND FILTER
noise over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
TEST CONDITIONS
ANLG IN+
ANLG IN-
Transmit noise, C·message weighted
Transmit noise, C-message weighted with eighth-bit
signaling (TCM2914 only)
Transmit noise, psophometrically weighted
Receive noise, C-message weighted quiet code
-4
CD
n
o
3
3
c
MIN
MAX
GND,
ANLG IN+
GND,
ANLG IN6th Irame signaling
ANLG IN + = ANLG GND,
ANLG IN- = GSX
PCM IN = 11111111 (Wlaw)
PCM IN = 10101010 (A-law)
bit toggled
measured at PWRO +
Input to PCM IN is zero code with sign bit
toggled at 1-kHz rate
Receive noise, psophometrically weighted
PCM - lowest positive decode level
Receive noise, C-message weighted sign
CD
= ANLG
= GSX
= ANLG
= GSX,
UNIT
15
dBrnCO
1B
dBrnCO
-75
dBmOp
11
dBrnCO
12
dBrnCO
-79
dBmOp
power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and
operating free-air temperature
::::I
PARAMETER
c:;"
I»
VCC supply voltage
r+
TEST CONDITIONS
rejection ratio.
0'
transmit channel
::::I
VBB supply voltage
en
f=30to50kHz
I=Oto30kHz
transmit channel
VCC supply voltage
n
c
::+
en
rejection ratio,
receive channel
(single-ended)
VBB supply voltage
rejection ratio,
receive channel
(single-ended)
1=30to50kHz
I
=
I
= Oto
supply signal
=
at PWRO+
Idle channel,
supply signal
30 kHz
=
-30
dB
-55
-20
200 mV p-p,
-20
200 mV p-p,
at PWRO+
ANLG IN + = 0 dBmO,
f = 1.02 kHz, unity gain,
PCM IN = lowest decode level
Crosstalk attenuation, transmit-ta-receive
(single-ended)
dB
-45
narrow-band, f measured
I = 30 to 50 kHz
UNIT
dB
narrow-band, f measured
30 to 50 kHz
MAX
-45
I measured at PCM OUT
Idle channel,
I=Oto30kHz
Typt
-30
I measured at PCM OUT
Idle channel,
supply signal = 200 mV p-p,
rejection ratio,
n
::;'
MIN
Idle channel,
supply signal = 200 mV p-p,
I=Oto30kHz
dB
-45
71
dB
71
dB
measured at PWRO +
PCM IN = 0 dBmO,
f = 1.02 kHz,
ANLG IN+ = ANLG GND,
measured at PCM OUT
Crosstalk attenuation, receive-to-transmit
(single-ended)
tAli typical values are at VBB
2-78
=
-5 V, VCC
=
5 V, and TA
=
25°C.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
distortion over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
ANlG IN+
Transmit signal to distortion ratio, sinusoidal
ANlG IN+
input (see Note 6)
ANlG IN+
ANlG IN+
Receive signal to distortion ratio, sinusoidal
ANlG IN+
input (see Note 6)
ANlG IN+
TEST CONDITIONS
MIN
= 0 to -30 dBmO
= -30 to -40dBmO
= -40 to -45 dBmO
= 0 to -30 dBmO
= -30 to -40 dBmO
= -40 to -45dBmO
36
Transmit single-frequency distortion products
AT&T Advisory #64 (3.8), Input signal
Receive single-frequency distortion products
AT&T Advisory #64 (3.8), Input signal
TYpt
MAX
30
dB
25
36
dB
30
25
=0
=0
dBmO
-46
dBmO
dBmO
-46
dBmO
CCITT G. 712 (7.1)
-35
Intermodulation distortion, end-ta-end
CCITT G.712 (7.2)
-49
Spurious out-af-band signals, end-ta-end
CCITT G.712 (6.1)
-25
CCITT G.712 (9)
Input to ANlG IN +
I
Transmit differential envelope delay time
I
relative to transmit absolute delay time
I
I
=
=
=
=
=
=
2.048 MHz,
245
1.02 kHz at 0 dBmO
500 Hz to 600 Hz
95
1000 Hz to 2600 Hz
45
I
I
relative to transmit absolute delay time
I
I
=
=
=
=
=
=
2.048 MHz,
500 Hz to 600 Hz
45
35
1000 Hz to 2600 Hz
2600 Hz to 2800 Hz
=
"S
~s
(3
~s
o
CJ
en
C
"';::
ca
190
600 Hz to 1000 Hz
5V,andTA
..
dBmO
105
2600 Hz to 2800 Hz
Digital input is DMW codes
Receive differential envelope delay time
...en
dBmO
170
600 Hz to 1000 Hz
Fixed data rate, IClKR
Receive absolute delay time to PWRO +
tAli typical values are atVBB = -5V,VCC
NOTE 6. CCITT G.712 - Method 2.
-40
Fixed data rate, ClKS
Transmit absolute delay time to PCM OUT
UNIT
CJ
~s
"2
:::J
E
E
o
~
85
110
CJ
CD
25°C.
""i
t-
transmit filter transfer over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1)
PARAMETER
TEST CONDITIONS
MIN
16.67 Hz
Input amplifier set for
Gain relative to gain
at 1.02 kHz
50 Hz
-25
60 Hz
-23
unity gain, Noninverting
200 Hz
maximum gain output,
300 Hz to 3 kHz
Input signal at ANlG IN
3.3 kHz
3.4 kHz
is 0 dBmO
MAX
-30
-1.8
0.125
-0.125
-0.35
0.125
0.03
-0.7
-0.1
4 kHz
-14
4.6 kHz and above
-32
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75266
UNIT
dB
2-79
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
receive filter transfer over recommended ranges of supply voltage and operating free-air temperature(see
Figure 2)
PARAMETER
Gain relative to gain at 1.02 kHz
-f
CD
CD
o
3
3
c
tclelKI
tr• tf
twlCLKI
twlDClKI
::I
(;'
r+
::I
MAX
0.125
0.125
0.125
0.03
-0.1
-14
-30
-0.5
-0.125
-0.35
-0.7
UNIT
dB
PARAMETER
Clock period for .ClKX. ClKR (2.048-MHz systems)
Rise and fail times for ClKX and CLKR
Pulse duration for ClKX and ClKR (see Note 7)
Pulse duration for DClK (fo_elK = 64 Hz to 2.04B MHz) (see Note 8)
Clock duty cycle (tw(ClKlitc(ClKll for ClKX and ClKR
MIN
488
5
220
220
45
Typt
MAX
30
50
55
UNIT
ns
ns
ns
ns
%
tAli typical values are at VBB = - 5 V. VCC = 5 V. and TA = 25 ·C.
D)
en
MIN
clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see timing diagrams)
n
S'
TEST CONDITIONS
Below 200 Hz
200 Hz
300 Hz to 3 kHz
Input signal at PCM IN Is 0 dBmO
3.3 kHz
3.4 kHz
4 kHz
4.6 kHz and above
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (sea timing diagrams)
n
:::;'
td(FSXI
n
c
ts\llSIGXL
th(SIGXI
r+
en
PARAMETER
Frame sync delay time
Setup time before Bit 7 falling edge (TCM2914 only)
Hold time after Bit 8 falling edge (TCM2914 only)
MIN
100
0
0
MAX
tclClKI-l00
UNIT
ns
ns
ns
propagation delay times over recommended ranges of operating conditions, fixed-data-rate mode
(see timing diagrams)
tpdl
tpd2
tpd3
tpd4
tpd5
tpd8
PARAMETER
From rising edge of trensmit clock to Bit 1 data valid at
PCM OUT (data enable tlma on time slot entry) (see Note 8)
From rising edge of transmit clock Bit n to Bit n + 1 data
valid at PCM OUT (data valid time)
From falling edge of transmit clock Bit 8 to Bit 8 Hi-Z at
PCM OUT (data float time on time slot exit) (see Note 8)
From rising edge of transmit clock Bit 1 to TSX active
(low) (time slot enable time)
From falling edge of transmit clock Bit 8 to TSX inactive
(high) (time slot disable time) (see Note 8)
From rising edge of channel time slot to SIGR update
(TCM2914onlyl
TEST CONDITIONS
MIN
MAX
UNIT
Cl = Oto 100 pF
0
145
ns
Cl = 0 to 100 pF
0
145
ns
60
215
ns
0
145
ns
60
190
ns
0
2
""
Cl = 0
Cl = 010 100 pF
Cl = 0
NOTES: 7. FSX CLK must be phase locked with the ClKX. FSR ClK must be phase locked with ClKR.
8. Timing parameter. t pdl.lpd3. and 1pd5 are referenced to the high-impedance state.
2-80
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 866012 • DALLAS. TexAS 7528&
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see timing diagrams)
PARAMETER
MIN
100
tdlFSRI
Frame sync delay time
tsu(PCM INI
thlPCM INI
Setup time before Bit 7 falling edge (TCM2914 onlyl
Hold time after Bit 8 falling edge (TCM2914 onlyl
MAX
UNIT
tc(CLKI-100
10
ns
ns
60
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see timing diagrams)
ldlTSDXI
td(FSXI
tc(DCLKXI
PARAMETER
Timeslot delay time from DCLKX (see Note 91
MIN
140
Frame sync delay time
Clock period for DCLKX
100
4BB
MAX
ld(DCLKXI-140
tc(CLKI-100
15620
UNIT
ns
ns
ns
propagation delay times over recommended ranges of operating conditions, variable-data-rate mode
(see Note 10 and timing diagrams)
tod7
t Dd8
t Dd9
tod10
PARAMETER
Data delay time from DCLKX
Data delay from timeslot enable to PCM OUT
TEST CONDITIONS
Data delay from time slot disable to PCM OUT
Data delay time from FSX
CL = Oto 100pF
CL = 0 to 100 pF
CL = 0 to 100 pF
MIN
0
0
0
td(TSDXI = 80 ns
0
MAX
100
50
80
140
UNIT
ns
ns
ns
ns
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see timing diagrams)
td(TSDFlL
ld(FSRI
tsulPCM IN)
th(PCM INI
tc(DCLKRI
tdlSERI
PARAMETER
Timeslot delay time from DCLKR (see Note 111
MIN
140
100
Frame sync delay time
Setup time before Bit 7 falling edge
MAX
UNIT
tdIOCLKRI-140
tc(CLKI-100
ns
ns
10
Hold time after Bit 8 falling edge
Clock period for DCLKR
Timeslot end receive time
60
488
0
ns
ns
15620
....en
"S
.
u
(3
en
c
o
"';:;
C1:S
u
"2
::::I
E
E
o
u
CD
G)
~
ns
ns
64-kilobit operation timing requirements over recommended ranges of supply voltage and operating
free-air temperature,varlable-data-rate mode
TEST CONDITIONS
MIN
Transmit frame sync minimum down time
FSX = TTL high for
remainder of frame
488
tFSLR
Receive frame sync minimum down time
FSR = TTL high for
remainder of frame
1952
tDCLK
Pulse duration data clock
PARAMETER
tFSLX
NOTES:
MAX
UNIT
ns
ns
10
~s
9. tFSLX minimum requirement overrides the td(TSDXI maximum requirement for 84-kHz operation.
10. Timing parameters tpd8 and tpd9 are referenced to a high-impedance state.
11. tFSLR minimum requirement overrides the td(TSDRI maximum requirement for 64-kHz operation.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS. TEXAS 16286
2-81
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
+0.03 dB
3300 Hz
'0
0
0
Ww
O..J
z<
fill
x
w
-1
-t
CD
(')
CD
0
3
3
C
:::J
(i'
..
e»
0'
...I
...Z
-1
III
0
N
~
I-
<
Z -10
-10
"
CI
0
l-
-20
:::J
-20
TYPICAL FILTER
TRANSFER FUNCTION
CII
(")
::;'
-30
(')
C
::+
CII
-40
-60
-50
FREQUENCY - Hz
FIGURE 1. TRANSFER CHARACTERISTICS OF THE TRANSMIT FILTER
2·82
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
+2
+2
+1
+1
+0.125 dB
200 Hz
+0.125 dB
300 Hz
EXPANDED
SCALE
3000 Hz
0
0
-0.5 dB
200 Hz
-0.125 dB
300Hz
....
tI)
'3
III
'i'
::...
•
-1
-1
...
(,)
(J
~
tI)
I0(
C
2
<
0
0
CI
CO
0
,2
I-
w
>
~
0(
....w
0
'+0
C
-10
-10
-20
-20
a:
2
<
:::s
E
E
0
CI
(,)
Q)
Q)
I-30
-30
-40
-40
_50L-~~~
100
____~~__~-L__L-'~-L~______-L__~-L~LL~-L~u-50
1k
FREQUENCY - Hz
10 k
NOTE: This is a typical transfer function of the receiver filter component.
FIGURE 2. TRANSFER CHARACTERISTIC OF THE RECEIVE FilTER
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-83
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
CLKX
tclIFSXI-.!,
FSX INPUT
INONSIGNALING
FRAMES)
FSX INPUT
ISIGNALING
FRAMES)
I
I+- -w
2
I
I
I
L
i ~ I+-'r
~I ..... tclIFSX) I
1
!4----*-"·eICLK)
~~
I
--'I i
~~------~I----------------------------------------------
J~
-w ......dIFSX)
l+-'dIFSX)
~I ..
\!
.
~11'_'__
_____________________________________________
FRAME SYNCHRONIZATION TIMING
-I
(1)
CLKX
CD
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3
3
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PCMOUT
I
I
'pd4 -tI
TSXOUTPUT
~
cr
o·
I
If-
~
--., 14- tpds
'~
V
__________________________________________~____~.
I II
'suISIGX)-.,
C\)
-.lM.-'h ISIGX)
SIGX INPUT --------------------O-O-N-'T-C-A-R-E------------------"''tj,,--VA-L-I-O-XOON'T CARE
r+
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OUTPUT TIMING
FIGURE 3. TRANSMIT TIMING (FIXED-DATA-RATEI
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CLKR
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'dIFSR)-+i1 if-
1
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I
FSR
INONSIGNALING
FRAMES)
FSR
ISIGNALING
FRAMES)
1
~~
--Ii
~
~
I
..., k-tcl
2
3
I
IFSR)
I
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I
M-',
4
S
I
·f.........
I
I
6
7
8
:
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I
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~
~'-------tl----------------------------------------------k-'dIFSRI
..., if-'dIFSR)
I
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_________________________________________
FRAME SYNCHRONIZATION TIMING
CLKR
PCMIN
E
SIGR OUTPUT _____________________________
V_A_L_IO___________________________
INPUT TIMING
FIGURE 4. RECEIVE TIMING (FIXED-DATA-RATEI
NOTES: A. Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high )evel is indicated and 0.8 V if the
low level is indicated.
B. BIT 1 = MSB = Sign Bit and is clocked in first on the PCM-IN pin or is clocked out first on the PCM-OUT pin.
BIT 8 = LSB = Least Significant Bit and is clocked in last on the PCM-IN pin or is clocked out last on the PCM-OUT pin.
2-84
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
I"
t;
FSX
DCLKX
~
I4----*- td(TSDX)
~ l.):--::l ,.......,
\
I r 1 1"L..J1
-r--
...I
~
TIMES LOT
2 \
I
~
,......., ~ r-', ,1"'"""'\ It-\
4 \
i 5 \t.......JI 6 \.........,I 7 ,' - - ', 8 .'---' I
...........11.........
~
'---'I
3
i4- t d ( F S X ) :
1
,,.....,,......,,.............L..
, I \ ' , ,~1 I~,......,
' I ' ,~, ,1"'"""""'\,......,
, , , ,~I'
, ,
~
CLKX
I L.l L.J W
LJ I '.......J L.J LJ L.J '......1 LJ ,......
tpd8-+j ~
.1 L
I .
~-, I
PCM OUT
t
-~~
I
j4--tpdl0
~~
Y.
BIT 1
BIT 2
I
BIT 3
--I ~
1- tpd9
X BIT 5 X
: : BIT 4
X
BIT 6
X BIT 8 )L-
BIT 7
o
+i'--
.
I.---.t-td{TSDR)
DCLKR
I
I
,4
J;....I
I
-+I ~td(FSR)
Po ,.., ,. . .,
I
,
I
1....1
\-J
Ij~!
,
,
\.....J
tsu(PSM IN)-+!
I
14-
,.......,
5,
,.......,
r.::-\
I 6,
\.......J
I
I
7,
\.....J
\-..I
I
8
i
,.....,
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I
I
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td(SER)....r
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3 •
i
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\..-J
I\.......J
I
CLKR
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FIGURE 5. TRANSMIT TIMING (VARIABLE-DATA· RATE)
FSR
....
...CJ
-3
CJ
n "
,....., " "
U'
I,....,
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f"""""\
\-J
\....J
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\.....J
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PCM IN
ij;CARE~Lrw\...-l-W\......l'"&'-_.1'(t/d\_J'«(~'\_.}(::Z1\_reL4'\-I~
BIT
1
BIT
2
BIT
3
BIT
4
BIT
5
BIT
6
BIT
7
BIT
8
NOTES: B. BIT 1 = MSB = Sign Bit and is clocked in first on the PCM-IN or is clocked out first on the PCM-OUT pin. BIT 8 = LSB = Least
Significant Bit and is clocked in last on the PCM·PIN or is clocked out last on the PCM-OUT pin.
C. All timing parameters referenced to VIH and VIL except tpd8 and tpd9. which are referenced to a high·impedance state.
FIGURE 6. RECEIVE TIMING (VARIABLE· DATA· RATE)
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2·85
TCM2913. TCM2914. TCM2916. TCM2917
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
GENERAL OPERATION
system reliability features
The TCM2913, TCM2914, TCM2916, or TCM2917 is powered up in four steps:
VCC and VBB supply voltages are applied.
All clocks are connected.
TTL high is applied to PDN.
FSX and/or FSR synchronization pulses are applied.
On the transmit channel, digital outputs PCM out and TSX are held in high-impedance state for approximately
four frames (500 liS) after power up or application of VBB or VCC. After this delay, PCM OUT, TSX, and
signaling are functional and will occur in the proper timeslot. The analog circuits on the transmit side require
approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time. Thus valid
digital information, such as for on/off hook detection, is available almost immediately, while analog
information is available after some delay.
-I
(1)
CD
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On the receive channel, the digital output SIGR is also held low for a maximum of four frames after power
up or application of VBB or VCC. SIGR will remain low until it is updated by a signalling frame.
To further enhance system reliability, PCM OUT and TSX will be placed in a high-impedance state
approximately 20 lis after an interruption of CLKX. SIGR will be held low approximately 20 liS after an
interruption of CLKR. These interruptions could possible occur with some kind of fault condition.
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power-down and standby operations
::s
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To minimize power consumption, a power-down mode and three standby modes are provided.
(')
For power down, an external TTL low signal is applied to the PDN pin. It is not sufficient to remove the
TTL high voltage to PDN. In the absence of a signal, the PDN pin floats to TTL high and the device remains
active. In the power-down mode, the average power consumption is reduced to an average of 5 mW.
:::;'
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The standby modes give the user the option of putting the entire device on standby, putting only the transmit
channel on standby, or putting only the receive channel on standby. To place the entire device on standby,
both FSX and FSR are held at TTL low. For transmit-only operation, FSX is high and FSR is held low. For
receive-only operation, FSR is high and FSX is held low. See Table 1 for power down and standby
procedures.
The first TSX pulse that occurs after power-up or removal from standby mode may not be exactly 8 data
bits long. In applications that require a valid first TSX, such as Digital Signal Processing, the TCM29C13,
TCM29C14, TCM29C16, and TCM29C17 are recommended.
TABLE 1. POWER DOWN AND STANDBY PROCEDURES
DEVICE
STATUS
Power down
Pi5iii
Entire device
on standby
FSX and FSR
are TTL low
FSX is TIL low
FSR is TIL high
Only transmit
on standby
Only receive
on standby
2-86
TYPICAL POWER
CONSUMPTION
PROCEDURE
= TTL low
FSR is TIL low
FSX is TTL high
5mW
12mW
70mW
110mW
DIGITAL OUTPUT STATUS
~ and PCM OUT are in a high-impedance state;
SIGR goes to TIL low within 10 "".
TSX and PCM OUT are in a high-impedance state;
SIGR goes to TIL low within 300 ms.'
'rnX and PCM OUT are placed in a high-impedance state
within 300 ms.
SIGR is placed in a high-impedance state
within 300 ms.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
fixed-data-rate timing (see Figure 7)
Fixed-data-rate timing is selected by connecting DCLKR to VSS, It uses master clocks CLKX and CLKR.
frame synchronizer clocks FSX and FSR, and output TSX. FSX and FSR are 8-kHz inputs that set the
sampling frequency and distinguish between signaling and nonsignaling frames by their pulse width. A
frame synchronization pulse one master clock wide designates a nonsignaling frame, while a double width
sync pulse enables the signaling function (TCM2914 only). Data is transmitted on the PCM OUT pin on
the first eight positive transitions of CLKX following the rising edge of FSX. Data is received on the PCM
IN pin on the first eight falling edges of CLKR following FSX. A digital-to-analog (D/A) conversion is performed
on the received digital word and the resulting analog sample is held on an internal sample-and-hold capacitor
until transferred to the receive filter.
•..
...
The clock selection pin (CLKSEL) is used to select the frequency of CLKX and CLKR (TMC2913 and
TCM2914 only). The TCM2913 and TCM2914 fixed data rate mode can operate with frequencies of
1.536 MHz, 1.544 MHz, or 2.048 MHz. The TCM2916 and TCM2917 fixed data rate mode operates at
2.048 MHz only.
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I+--- TS1X
OTHER
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CLKX~,n.rtrtJU1-Il.I
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2
3
4
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XMIT SIGNAL FRAME
U
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is
FSX..fI
"~
C
:::I
B7 B8 SIGX
PCMOUT
-
B1 B2 B3 B4 B5 B6 97 B8
--------------
B1 B2 B3 B4 B5
Tsx~~___________J~rl-------~f-~~
as
f
_____4~r_---
.J
SIGX
TS1 R
~
OTHER
192/193/256
I*--- TIMES LOTS --->I
\
CLKR~l
2 3 4 5 6 7 8 9 ~
192/193/256
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1
u
DON'T CARE
:=============~~===DON'T
==~=====:::ft:X=::=:==::-:'.::~:x:z:x:·=~CARE
VALID
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FSR
E
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o
-~-- - - - - - - - - - - - - :x~:J:Jac>C><=>C>c=~==
CD
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~
TS1 R - - - - 0 1
2
3
4
5
REC. SIGNAL FRAME
Sf
I~L-
_ _ _ _ _ _ _ __
SIGR
PCMIN-::>aaoaaac:x::x---------------~---
SIGR
B1B2B3 B4 B5Bs B7 BS
---------------~;---
It
H
(
PREVIOUS VALUE
NEW VALUE
FIGURE 7. SIGNALING TIMING (FIXED-DATA-RATE ONLY)
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-87
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
variabte data rate timing
Variable-data-rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway
rather than to VBB. It uses master clocks CLKX and CLKR, bit clocks DCLKX and DCLKR, and frame
synchronization clocks FSX and FSR.
Variable-data-rate timing allows for a flexible data frequency. The frequency ofthe bit clocks can be varied
from 64 kHz to 2.048 MHz. The bit clocks can be asynchronous in the TCM2914, but must be synchronous
in the TCM2913, TCM2916, and TCM2917. Master clocks in types TCM2913 and TCM2914 are restricted
to frequencies of operation of 1.536 MHz, 1.544 MHz, or 2.048 MHz as in the fixed-data-rate timing mode.
The master clock for the TCM291.6 and TCM2917 is restricted to 2.048 MHz.
While FSX/TSXE input is high, PCM data is transmitted from PCM OUT onto the highway on the next
eight consecutive positive transitions of DCLKX. Similarly, while the FSR/TSRE input is high, the PCM
word is received from the highway by PCM IN on the next eight consecutive negative transitions of DCLKR.
-I
CD
CD
The transmitted PCM word wilJ be repeated in all remaining timeslots in the 125 "'s frame as long as DCLKX
is pulsed and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM
highway more than once per frame, if desired, is available only with variable-data-rate timing. Signaling
is allowed only in the fixed-data-rate mode because the variable-data-rate mode provides no means with
which to specify a signaling frame.
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signaling
The TCM2914 (only) provides 8th-bit signaling in the fixed-data-rate timing mode. Transmit and receive
signaling frames are indapendent of each other and are .selected by a double-width frame sync pulse on
the appropriate channel. During a transmit signaling frame, the signal present on SIGX is substituted for
the 'least significant bit (LSB) of the encoded PCM word. In a receive signaling frame, the codec will decode
the seven most significant bits in accordance with CCITT G.733 recommendations, end output the logical
state of the LSB on the SIGR pin until it is updated in the next signaling frame. Timing relationships for
signaling operations are shown n Figure 9. The signaling path is used to transmit digital signaling information
such as ring control, rotary dial pulses, and off-hook and disconnect supervision. The voice path is used
to transmit prerecorded messages as well as the call progress tones; dial tone, ring-back tone, busy tone,
and re-order tone.
:::s
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en
asynchronous operation
The TCM2914 can be operated with asynchronous clocks in either the fixed- or variable-data-rate modes.
In order to avoid crosstalk problems associated with special interrupt circuits, the design of the TCM29,13
and TCM2914 includes separate digital-to-analog converters and voltage references on the transmit and
receive sides to allow completely independent operation of the two channels.
In either timing mode, the master cloCk, data clock, and timeslot strobe must be synchronized at the
beginning of each frame. Specifically, in the variable-data-rate mode the rising edge of CLKX must occur
within td(FSX) os before the rise of FSX, while the leading edge of DCLKX must occur within tTSDX ns
of the rise of FSX. CLKX and DCLKX are synchronized once per frame but may be of different frequencies.
The receive channel operates in a similar manner and is completely independent of the transmit timing
(see variable data rate timing diagrams). This approach requires the provision of two separate master clocks
but avoids the use of a synchronizer, which can cause intermittent data conversion errors.
2-88
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 76286
TCM2913. TCM2914. TCM2916. TCM2917
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
analog loopback
A distinctive feature of the TCM2914 is its analog loopback capability. With this feature, the user can
test the line circuit remotely by comparing the signals sent into the receive channel (PCM IN) with those
generated on the transmit channel (PCM OUT). The test is accomplished by sending a control signal that
internally connects the analog input and output ports. When ANLG LOOP is TIL high, the receive output
(PWRO +) is internally connected to ANLG IN +, GSR is internally connected to PWRO -, and ANLG INis internally connected to GSX (see Figure 8).
,-----------
- - ANW,
LOOP
I
I
I pCM
TRANSMIT
VOICE
+1'--+_
OUT
DIGITIZED
AID
PCM
LOOPBACK
RESPONSE
C
ca
,
I
PWRO- ; - - _..._ _ _ _ _~--~
I
____ _
..
(I)
o
CJ
PWRO+~'-__~__----------~~
I
IL
fI
____
DIGITIZED
PCM
TEST TONE
I
I
...1
FIGURE 8. TCM2914 ANALOG LOOPBACK CONFIGURATION
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Due to the difference in the transmit and receive transmission levels, a 0 dBmO code into PCM IN will
emerge from PCM OUT as a 3-dBmO code, an implicit gain of 3 dB. Because of this, the maximum signal
that can be tested by analog loopback is 0 dBmO.
precision voltage references
No external components are required with the TCM2913, TCM2914, TCM2916, and TCM2917 to provide
the voltage references. Voltage references that determine the gain and dynamic range characteristics of
the device are generated internally. A difference in subsurface charge density between two suitably
implanted MOS devices is used to derive a temperature- and bias-stable reference voltage. These references
are calibrated during the manufacturing process. Separate references are supplied to the transmit and receive
sections, and each is calibrated independently. Each reference value is then further trimmed in the gain
setting operational amplifiers to a final precision value. Manufacturing tolerances can be achieved of typically
±O.04 dB in absolute gain for each half channel, providing the user a significant margin to compensate
for error in other board components.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-89
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
conversion laws
The TCM2913 and TCM2914 provide pin-selectable Wlaw operation as specified by CCITT G.711
recommendation. A-law operation is selected when the ASEL pin is connected to VBB. Signaling is not
allowed during A-law operation. The TCM2916 is Wlaw only. The TCM2917 is A-law only.
•
The /L-Iaw operation is effectively selected by not selecting A-law operation. If the ASEL pin is connected
to VCC or GNO, the device is in /L-Iaw operation. If /L-Iaw operation is selected, SIGX is a TTL-level il)put
that can be used in the fixed data rate timing mode to modify the LSB of the PCM output in signaling frames.
transmit operation
transmit filter
-I
The input section provides gain adjustment in the passband by means of an on-chip uncommitted operational
amplifier. The load impedance to ground (ANLG GNOI at the amplifier output (GSXI must be greater than
10 kG in parallel with less than 50 pF. The input signal on the ANLG IN + pin can be either ac or dc coupled.
The input operational amplifier can also be used in the inverting mode or differential amplifier mode.
CD
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3
3
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A low-pass antialiasing section is included on the device. This section provides 35-dB attenuation at the
sampling frequency. No external components are required to provide the necessary antialiasing function
for the switched capacitor section of the transmit filter.
:::s
C:;'
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The passband section provides flatness and stopband attenuation that fulfills the AT&T 03/04 channel
bank transmission specification and CCITT recommendation G. 712. The TCM2913, TCM2914, TCM2916,
and TCM2917 specifications meet or exceed digital class 5 central office switching systems requirements.
til
A high-pass section configuration was chosen to reject low-frequency noise from 50- and 60-Hz power
lines, 17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency
noise. Even with the high rejection at these frequencies, the sharpness of the band edge gives low
attenuation at 200 Hz. This feature allows the use of low-cost transformer hybrids without external
components.
:::s
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::;'
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c
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til
encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal sample
and hold capacitor. The encoder performs an analog-to-digital conversion on a switched caP<:lcitor array.
Digital data representing the sample is transmitted on the first eight data clocks bits of the next frame.
The autozero circuit corrects for dc offset on the input signal to the encoder. The autozero circuit uses
the sign bit averaging technique. The sign bit from the encoder output is long-term averaged and subtracted
from the input to the encoder. All dc offset is removed from the encoder input waveform.
receive operation
decoding
The serial PCM word is received at the PCM IN pin on the first eight data clock bits of the frame. Oigital-toanalog conversion is performed and the corresponding analog sample is held on an internal sample-andhold capacitor. This sample is transferred to the receive filter.
receive filter
The receive section of the filter provides passband flatness and stopband rejection that fulfills both the
AT&T 03/04 specification and CCITT recommendation G. 712. The filter contains the required compensation
for the {sin xlIx response of such decoders.
2-90
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM2913, TCM2914, TCM2916, TCM2917
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
receive output power amplifiers
A balanced output amplifier is provided to allow maximum flexibility in output configuration. Either of the
two outputs can be used single-ended (i.e., referenced to ANLG GND) to drive single-ended loads.
Alternatively, the differential output will directly drive a bridged load. The output stage is capable of driving
loads as low as 300 ohms single-ended to a level of 12 dBm or 600 ohms differentially to a level of 15 dBm.
The receive channel transmission level may be adjusted between specified limits by manipulation of the
GSR input. GSR is internally connected to an analog gain-setting network. When GSR is connected to
PWRO -, the receive level is at maximum. When GSR is connected to PWRO +, the level is minimum.
The output transmission level is adjusted between 0 and - 12 dB as GSR is adjusted (with an adjustable
resistor) between PWRO + and PWRO - .
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions
(i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation
G.711).
...
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TYPICAL APPLICATION DATA
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output gain set design considerations (see Figure 9)
'';:;
PWRO + and PWRO - are low-impedance complementary outputs. The voltages at the nodes are:
VO+ at PWRO+
VO- at PWROVo = Vo + - Vo - (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to the GSR input.
A value greater than 10 kO and less than 100 kO for R1 + R2 is recommended because of the following:
The parallel combination of R1 + R2 and RL sets the total loading.
The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant
which has to be minimized to avoid inaccuracies.
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VA represents the maximum available digital milliwatt output response (VA = 3.06 V rms).
Vo = A,VA
+ (R1/R2)
Where A
4 + (R1/R2)
CD
RL
it
R1
~ .@
vo
I
PWRO+
TCM2913.
TCM2914,
TCM2916,
GSR
TCM2917
PCMIN
R2
v~_
®
PWRO-
DIGITAL~ ILLIWATT
SEOUEN CE PER
CCITT G.711
FIGURE 9. GAIN-SETTING CONFIGURATION
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-91
...
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2-92
TCM129C13. TCM129C14. TCM129C16. TCM129C17.
TCM29C13. TCM29C14. TCM29C16. TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
02765. APRIL 1986·-REVISED JUNE 1988
FEATURE TABLE
•
Replaces Use of TCM2910A in Tandem
with TCM2912C
•
Reliable Silicon-Gate CMOS Technology
•
Low Power Consumption:
Operating Mode ... 80 mW Typical
Power-Down Mode ... 5 mW Typical
129C13 129C14 129C16
29C13
29C14 29C16
FEATURE
129C17
29C17
Number of Pins:
•
Excellent Power Supply Rejection Ratio Over
Frequency Range of 0 to 50 kHz
X
X
X
X
p.-law/A-law Coding:
W1aw
X
X
A-law
X
X
X
X
X
X
X
X
X
X
X
X
Data Timing Rates:
•
No External Components Needed for
Sample, Hold, and Auto-Zero Functions
•
Precision Internal Voltage References
•
Direct Replacement for Intel 2913, 2914,
2916, and 2917
•
24
20
16
Variable Mode
64 kHz to 2.048 MHz
X
X
Fixed Mode
1.536 MHz
1.544 MHz
2.048 MHz
Loopback Test Capability
TCM29C13N-3 is Primarily Used for LowCost DSP Applications with TMS320CXX
..."Sen
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8th-Bit Signaling
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description
C'O
TheTCM129C13, TCM129C14, TCM129C16, TCM129C17, TCM29C13, TCM29C14, TCM29C16, and
TCM29C17 are single-chip pulse-code-modulated encoders and decoders (PCM codecs) and PCM line filters.
These devices provide all the functions required to interface a full-duplex (4-wire) voice telephone circuit
with a time-division-multiplexed (TOM) system. These devices are intended to replace the TCM2910A
in tandem with the TCM2912C. Primary applications of the devices include:
• Line Interface for Digital Transmission and Switching of T1 Carrier, PABX, and Central Office
Telephone Systems
• Subscriber Line Concentrators
• Digital Encryption Systems
• Digital Voice Band Data Storage Systems
• Digital Signal Processing
TCM129C13 ... OW. OV. J. OR N PACKAGE
TCM29C13 ... OW. OV. J. OR N PACKAGE
TCM29C13N-3 ... N PACKAGE
PWAOt
PWROGSR
1
4
Pi5N
CLKSEL
OCLKR
PCM IN
FSR/TSRE
DGTL GNO
9
11
C
:::I
E
E
o
(J
Q)
Qi
I-
TCM129C16. TCM129C17 ••. J OR N PACKAGE
TCM29C16. TCM29C17 ... J OR N PACKAGE
(TOP VIEWI
vee
"~
(TOPVIEWI
VCC
GSX
ANLG IN ANLG IN+
ANLG GNO
ASEL
TSX/OCLKX
PCM OUT
FSX/TSXE
CLKR/CLKX
TCM129C14 •.• OW OR JW PACKAGE
TCM29C14 ••. OW OR JW PACKAGE
(TOPVIEWI
vee
PWRO+
PWROGSR
PON
ANLG LOOP
SIGR
OCLKR
PCM IN
OGTL GNO
VCC
GSX
ANLG IN ..
ANLG IN+
ANLG GNO
NC
SIGX/ASEL
'fSX/OCLKX
PCM OUT
FSX/TSXE
CLKX
CLKR
PWRO+
PWRO
OCLKR
PCM IN
FSR/TSRE
OGTL GNO
VCC
GSX
ANLG INANLG GNO
TSX/OCLKX
FSX/TSn
CLKR/CLKX
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCTION DATA d••u.ents contein inlormatio.
currant as If puillication dlt8. Products conform to
:r.":~~:r~::rr.: .t~~.::::r.:'P:::':I~";':::·::
..Icllurily
inclu~e tasting of all parameters.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Copyright
© 1986, Texas Instruments Incorporated
2-93
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
description (continued)
These devices are designed to perform the transmit encoding (AID conversion) and receive decoding (O/A
conversion) as well as the transmit and receive filtering functions in a pulse-code-modulated system. They
are intended to be used at the analog termination of a PCM line or trunk.
The TCM129C13, TCM129C14, TCM129C16, TCM129C17, TCM29C13, TCM29C14, TCM29C16, and
TCM29C17 provide the bandpass filtering of the analog signals prior to encoding and after decoding. These
combination devices perform the encoding and decoding of voice and call progress tones as well as the
signaling and supervision information.
The TCM29C13N-3 is the same as the TCM29C13N except for certain parameters as indicated in the
specification section.
-f
The TCM129C13, TCM129C14, TCM129C16, and TCM129C17 are characterized for operation from
-40°C to 85°C. The TCM29C13, TCM29C14, TCM29C16, and TCM29C17 are characterized for
operation from OOC to 70°C.
CD
CD
(')
o
3
3
c
functional block diagram
TRANSMIT
SECTION
::s
(:r
I»
....
AUTO
ZERO
PCMOUT
0'
ANLGIN+
::s
COMPARA·
TOR
ANLGIN-
(I)
TSx/DCLKX
SIGX/ASEL
(')
GSX--r---;:::~::
~'
ANALOG
....5,
-+___+_FSX/TSXE
T~,!:~!~~LI-______________
(I)
LOGIC
CLKX
RECEIVE
SECTION
- - - - - ........LCLKSEL
iiDN
GSR
PWRO+
ANLG LOOPt
PCMIN
....,1-+_----,
DLCKR
PWRO- __1-+_----'
'----....,r- SIGRt
vee vaa
DGTL ANLG
GND GND
FSR/TSRE
CLKRt
tTCM129C14 and TCM29C14 only
*TCM129C13. TCM129C16. TCM129C17, TCM29C13. TCM29C16. and TCM29C17 only.
2-94
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
PIN
TCM129C16
TCM129C13
TCM129C14
TCM129C17
TCM29C13
TCM29C14
TCM29C16
DESCRIPTION
NAME
TCM29C17
VBB
2
2
2
PWRO+
Most negative supply voltage; input is - 5 V ± 5 %.
Noninverting output of power amplifier. Can drive transformer hybrids or
high~impedance
loads directly in either a differential or a single-ended
configuration.
3
3
3
PWRO-
Inverting output of power amplifier; functionally identical with and
complementary to PWRO
4
4
GSR
+.
In
Input to the gain-setting network on the output power amplifier.
Transmission level can be adjusted over a 12-dB range depending upon
the voltage at GSR.
5
5
4
PDN
CLKSEL
6
Power-down select. The device is inactive with a TTL low-level input to
Clock frequency selection. Input must be connected to Vss. VCC, or
ground to reflect the master clock frequency. When tied to Vas, CLK is
2.048 MHz. When tied to ground, ClK is 1.544 MHz. When tied to VCC,
ClK is 1.536 MHz.
7
ANlG lOOP
SIGR
Signaling bit output, receive channel; in a fixed-data-rate mode, outputs
the logical state of the 8th bit (lSB) of the PCM word in the most recent
signaling frame.
7
9
5
OCLKR
...
(,)
In
C
..;::.o
CO
.2
c
::::I
Provides loop back test capability. When this input is high, PWRO + is
internally connected to ANLG IN.
8
::::I
U
this pin and active with a TTL high-level input to the pin.
6
.~
Selects fixed or variable data-rate operation. When this pin is connected
E
E
o(,)
(1)
a;
I-
to Vas, the device operates in the fixed-data-rate mode. When DCLKR
is not connected to VaB, the device operates in the variable-data-rate
mode, and DCLKR becomes the receive data clock, which operates at
frequencies from 64 kHz to 2.048 MHz
8
10
6
PCM IN
Receive PCM input. PCM data is clocked in on this pin on eight consecutive
negative transitions of the receive data clock, which is CLKR in fixed-datarate timing and DCLKR in variable-data-rate timing.
9
11
7
FSR/TSRE
Frame synchronization clock input/time slot enable for receive channel.
In the fixed-data-rate mode, FSR distinguishes between signaling and nonsignaling frames by a double- or single-length pulse, respectively. In the
variable-data-rate mode, this signal must remain high for the duration of
the times lot. The receive channel enters the standby state when FSR is
TTL low for 300 ms.
10
12
8
DGTl GND
11
13
9
ClKR
Digital ground for aU internal logic circuits. Not internally connected to
ANlG GND.
Receive master clock and data clock for the fixed-data-rate mode. Receive
master clock only for variable-data-rate mode. CLKR and CLKX are
internally
connected together for
TCM 129C13,
TCM 129C 16,
TCM129C17, TCM29C13, TCM29C16, and TCM29C17.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TEXAS 75265
2-95
TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
PIN
TCM129C16
TCM129C13
TCM129C14
TCM129C17
TCM29C13
TCM29C14
TCM29C16
11
14
NAME
DESCRIPTION
TCM29C17
9
CLKX
Transmit master clock and data clock for the fixed-data-rate mode.
Transmit master clock only for variable data rate mode. CLKR and CLKX
are internally connected for the TCM129C13, TCM129C16, TCM129C17,
TCM29C13, TCM29C16, and TCM29C17.
12
15
10
FSXITSXE
Frame synchronization clock input/time-slot enable for transmit channel.
Operates independently of, but in an analagous manner to, FSRITSRE.
-I
The transmit channel enters the standby state when FSX is low for 300 ms.
(1)
CD
n
13
16
11
PCM OUT
consecutive positive transitions of the transmit data clock, which is CLKX
o
3
3
Transmit PCM output. PCM data is clocked out on this output on eight
in fixed-data-rate timing and DCLKX in variable-data-rate timing.
14
17
12
'fSX/DCLKX
Transmit channel time slot strobe (outputl or data clock (inputl for the
c
transmit channel. In the fixed-data-rate mode, this pin is an open-drain
....
operates at TTL levels from 64 kHz to 2.048 MHz .
:::s
5"
output to be used as an enable signal for a three-state buffer. In the
variable-data rate mode, DCLKX becomes the transmit data clock, which
D)
0"
:::s
15
18
SIGX/ASEL
Used to select between A-law and wlaw operation. When connected to
V8B, A-law is selected. When connected to VCC or ground, u-Iaw is
tn
selected. When not connected to VBB, it is a TTL-level input that is
(')
transmitted as the eighth bit (LSBI of the PCM word during signaling frames
:::;"
n
c
::+
on the PCM OUT pin (TCM129C14 and TCM29C14 onlyl. SIGX/ASEL
is internally connected to provide wlaw operation for TCM 129C 16 and
TCM29C16 and A-law operation for TCM129C17 and TCM29C17.
tn
16
20
13
ANLG GND
Analog ground return for all internal voice circuits. Not internally connected
to DGTL GND.
17
21
ANLG IN+
Noninverting analog input to uncommitted transmit operational amplifier.
Internally connected to ANLG GND on TCM129C16, TCM29C16,
TCM129C17, and TCM29C17.
18
22
14
ANLG IN-
19
23
15
GSX
Inverting analog input to uncommitted transmit operational amplifier.
Output terminal of internal uncommitted operational amplifier. Internally,
this is the voice signal input to the transmit filter.
20
2-96
24
16
VCC
Most positive supply voltage, input is 5 V ± 5 %.
TEXAS ."
INSfRUMENlS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) ..................................... -0.3 V to 15 V
Output voltage, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Input voltage, V, .................................................. -0.3 V to 15 V
Digital ground voltage .............................................. - 0.3 V to 15 V
Continuous total dissipation at (or below) 25°C free-air temperature ................ 1375 mW
Operating free-air temperature range: TCM 129C_ ........................ - 40°C to 85 °C
TCM29C_ ............................ OOC to 70°C
Storage temperature range ......................................... -- 65°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: OW, DY, or N package ... 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: J or JW package ....... 300°C
...
U)
NOTES: 1. Voltage values for maximum ratings are with respect to vaa.
..
'S
CJ
recommended operating conditions (see Note 2)
Vcc
Supply voltage (see Note 3)
Vaa
Supply voltage
DGTL GND voltage with respect to ANLG GND
High-level input voltage. all inputs except CLKSEL
VIH
VIL
RL
CL
TA
MIN
4.75
-4.75
Load capacitance
Oparating free-air temperature
MAX
5.25
5
-5 -5.25
0
Vaa
0
Vee- 0.5
AtGSX
At PWRO + andlor PWROAt GSX
AT PWRO+ andlor PWROTCMI29C_
VaB+0.5
0.5
V
VCC
kO
50
100
85
70
U)
C
o
'';;
as
CJ
'c:::s
E
E
pF
o
CJ
.!a
·C
I-
0
300
a
TCM29C
V
o.a
10
-40
UNIT
V
V
V
V
2.2
Low-level input voltage. all inputs except CLKSEL
For 2.04a MHz
Clock select
For 1.544 MHz
input voltage
For 1. 536 MHz
Load resistance
NOM
(3
CD
NOTES: 2. To avoid any possible damage and reliability problems to these CMOS devices when applying power. the following sequence
should be followed:
(I) Connect ground
(2) Connect the most negetive voltage
(3) Connect the most positive voltage
(4) Connect the input signals
When powering down the device, follow the above steps in reverse order. If the above procedure cannot be followed, connect
a diode between Vaa and digital ground, cathode to DGND. anode to Vaa.
3. Voltages at analog inputs and outputs, VCC, and Vaa terminals are with respect to tho ANLG GND terminal. All other voltages
are referenced to the DGTL GND terminal unless otherwise noted.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TeXAS 75265
2·97
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature
supply current. fDCLK - 2.048 MHz. outputs not loaded
PARAMETER*
Supply current
ICC from VCC
18B
-I
CD
(')
3
3
from VBB
Power
dissipation
CD
o
Supply current
Operating
Standby
FSX or FSR at VIL after 300 ms
Power-down PDlii VIL after 10 ""
Operating
Standby
FSX or FSR at VIL after 300 ms
Power-down PDlii VIL efter 10 ""
Operating
Standby
FSX or FSR at VIL after 300 ms
Power down PDlii VIL after 10 ""
PARAMETER
ri"
VOH High-level output voltage
r+
en
VOL
IIH
IlL
Ci
(")
Co
I»
s·
j
c
Typt
MAX
13
8
0.7
0.4
TYpt
MAX
7
0.5
0.3
-7
9
1
0.8
-9
-1
-8
-0.7
1.5
1
-13
-1.5
-0.4
-1
-0.5
-0.3
80
7
4
130
70
15
10
5
3
UNIT
mA
mA
-0.8
90
10
8
mW
digital interface
cj
~r
TCM29C_ _
TCM129C_ _
TEST CONDITIONS
TEST CONDITONS
I PCM out
I SiGR
IOH = -9.6 mA
IOH = -1.2 rnA
TCM129C_ _
Typt MAX
MIN
2.4
2.4
Low-level output voltage at PCM out. TSX. SIGR IOL - 3.2 rnA
High·level input current. any digital input
VI =2.2 V to VCC
Low-level input current, any digial input
VI = 0 to 0.8 V
Input capacitance
Output capacitance
TCM29C _ _
MIN
2.4
2.4
Typt
UNIT
V
0.5
12
5
5
MAX
0.4
10
12
10
5
10
10
5
V
p.A
p.A
pF
pF
transmit amplifier input
::;:
en
PARAMETER
Input current at ANLG IN +. ANLG IN-
TEST CONDITIONS
VI = -2.17 V to 2.17 V
VI = -2.17 V to 2.17 V
VI = -2.17 V to 2.17 V
Input offset voltage at ANLG IN +. ANLG INCommon-mode rejection at ANLG IN +. ANLG INOpen-loop voltage amplification at GSX
Open-loop unity-gain bandwidth at GSX
Input resistance at ANLG IN +. ANLG IN-
MIN
TYpt
MAX
±100
±25
55
5000
1
MHz
MO
10
receive filter output
PARAMETER
TEST CONDInONS
Output offsat voltage PWRO +. PWRO - (single-ended)
Relative to ANLG GND
Output resistance at PWRO +. PWROtAli typical values are at VBB = -5 V. VCC = 5 V. and TA = 25°C.
2-98
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
MIN
TVP
80
UNIT
nA
mV
dB
MAX
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
gain and dynamic range. Vee - 5 V. VBB Isee Notes 4. 5. and 6)
PARAMETER
TEST CONDITIONS
Encoder milliwatt response
I Standard version
= 1.068 V
= oDe to 70 oC,
Supplies = ± 5%
I
(transmit gain tolerance)
Signal input
TA
(nominal supplies and temperature)
Digital milliwatt response (receive
tolerance gain) relative to zerotransmission level point
Supplies
(0 dBmO)
,,-Iaw
A·law
Zero-transmission-Ievel
point, receive channel
(0 dBmO)
A-law
,,-Iaw
A-law
,,-Iaw
A-law
RL
=
= 900 0
RL
= 6000
=
±0.5
±O.OB
I
Standard version
±0.04
±0.2
±0.2
±0.5
UNIT
dBmO
dB
dBmO
ITCM29C13N-3
±0.08
dB
2.76
6000
RL
RL
1 kHz
MAX
±0.2
= oDe to 70°C,
= ± 5%
TA
with temperature and supplies
,,-Iaw
=
TYP
±0.04
±0.2
rms for A-law TCM29C13N-3
Signal input per CCITT G.711,
Output signal
Digital milliwatt response variation
point, transmit channel
MIN
Signal input - 1.064 V rms for ,..Iaw
Encoder milliwatt response
Zero-transmission-Ievel
-5 V. TA - 25 0 e lunless otherwise noted)
dBm
1.00
1.03
6. Receive output is measured single-ended in the maximum-gain configuration. To set the output amplifier for maximum gain,
GSR is connected to PWRO - and the output is taken at PWRO +. All output levels are (sin xlix corrected.
Transmit gain tracking error, sinusoidal input
3 to -40 dBmO
-40 to -50 dBmO
±0.25
-50 to -55 dBmO
± 1.2
3to -40dBmO
Receive gain tracking error. sinusoidal input
MAX
±0.5
±0.5
- 50 to - 55 dBmO
± 1.2
TEXAS •
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ca
to)
"2
:::::I
E
E
oto)
"'i
I-
UNIT
dB
±0.25
-40 to - 50 dBmO
INSTRUMENTS
o
".;0
Q)
gain tracking over recommended ranges of supply voltage and operating free-air temperature. reference
level - - 10 dBmO
MIN
(3
r::
dBm
4.03
TEST CONDITIONS
.
U)
5.76
5.79
4.00
NOTES: 4. Unless otherwise noted, the analog input is a O-dBmO, 1020-Hz sine wave, where 0 dBmO is defined as the zero-reference
point of the channel under test. This corresponds to an analog signal input of 1.064 V rms, or an output of 1.503 V rms.
5. The input amplifier is set for unity gain, noninverting. The digital input is a PCM bit stream generated by passing a O-dBmO,
1020-Hz sine wave through an ideal encoder.
PARAMETER
U)
to)
2.79
9000
...
"S
dB
2-99
TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
noise over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
TEST CONDITIONS
ANLG IN+
Transmit noise, C-message weighted
ANLG IN-
Transmit noise, C-message weighted with eighth-bit
signaling (TCM129C14 and TCM29C14 only)
ANLG IN+
ANLG IN-
= ANLG
= GSX
= ANLG
= GSX,
MIN
MAX
GND,
UNIT
15
dBrnCD
18
dBrnCD
-75
dBmDp
11
dBrnCO
12
dBmCO
-79
dBmOp
GND,
6th frame signaling
ANLG IN+
Transmit noise, psophometrically weighted
ANLG INPCM IN
Receive noise, C-message weighted quiet code
PCM IN
=
=
= ANLG
= GSX
GND,
11111111 (wlaw)
10101010 (A·law)
measured at PWRO +
Receive noise, C-message weighted sign
Input to PCM IN is zero code with sign bit
bit toggled
toggled at 1·kHz rate
Receive noise, psophometrically weighted
PCM
=
lowest positive decode level
power supply rejection and crosstalk attenuation over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER
V CC supply voltage
I
TEST CONDITIONS
=0
VeB supply voltage
f = 30 to 50 kHz
I
=0
I
=
I
=0
rejection ratio,
transmit channel
V CC supply voltage
rejection ratio,
receive channel
(single-ended)
VBB supply voltage
rejection ratio,
receive channel
(single-ended)
Typt
f
f
f
=
supply signal
=
=
200 mV Pop,
dB
-55
Idle channel,
to 30 kHz
supply signal
=
-20
200 mV Pop,
narrow-band, f measured
Idle channel,
supply signal
=
-20
200 mV Pop,
narrow-band, f measured
30 to 50 kHz
=
Crosstalk attenuation, transmit-to-receive
I
(single-ended)
PCM IN
~
0 dBmO,
1,02 kHz, unity gain,
=
dB
-45
at PWRO+
ANLG IN+
dB
-45
at PWRO+
to 30 kHz
--
-30
f measured at PCM OUT
30 to 50 kHz
=0
dB
Idle channel.
30 to 50 kHz
UNIT
--45
f measured at PCM OUT
to 30 kHz
MAX
-30
supply signal = 200 mV Pop,
rejection ratio,
transmit channel
MIN
Idle channel,
to 30 kHz
lowest decode level,
71
dB
71
dB
measured at PWRO +
peM IN - 0 dBmO,
Crosstalk attenuation, receive-to-transmit
I
(single-ended)
tAil typical values are at VBB
2-100
=
1,02 kHz,
Measured at PCM OUT
=
-5 V, VCC
=
5 V, and TA
=
25°C_
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
distortion over recommended ranges of supply voltage and operating free-air temperature
PARAMETER
TEST CONDITIONS
Transmit signal to distortion ratio, sinusoidal
input (CCITT G.712 - Method 2)
Receive signal to distortion ratio. sinusoidal
input (CCITI G.712 - Method 2)
ANLG IN+
=0
MIN
to -30 dBmO
ANLG IN+ = -30 to -40 dBmO
30
ANLG IN+ = -40 to -45 dBmO
25
ANLG IN+ = 0 to -30 dBmO
ANLG IN+ = -30 to -40 dBmO
36
ANLG IN+
=
AT&T Advisory #64 (3 ..8), Input signal
Receive single-frequency distortion products
AT&T Advisory #64
CCITT G.712 (7.1)
(~.~),
Input signal
MAX
dB
25
=0
=0
dBmO
-46
dBmO
dBmO
-46
dBmO
-35
Intermodulation distortion, end-ta-end
CCITI G.712 (7.2)
-49
Spurious out-af-band signals, end-te-end
CCITT G.712 (6.1)
-25
CCITT G.712 (9)
Transmit absolute delay time to PCM OUT
Transmit differential envelope delay time
relative to transmit absolute delay time
Receive absolute delay time to PWRO +
Fixed data rate, ICLKX
245
Input to ANLG IN + 1.02 kHz at 0 dBmO
= 500 Hz to 600 Hz
= 600 Hz to 1000 Hz
I = 1000 Hz to 2600 Hz
I = 2600 Hz to 2800 Hz
Fixed data rate, ICLKR =
170
I
95
I
relative to transmit absolute delay time
I
I
VCC
=
=
=
=
II)
..
C3
dBmO
(J
II)
c
o
~s
'';:
«I
105
(J
2.048 MHz,
190
500 Hz to 600 Hz
45
600 Hz to 1000 Hz
35
1000 Hz to 2600 Hz
,.s
'2
::s
E
,.s
85
110
2600 Hz to 2800 Hz
= 5 V, and TA
...
'S
dBmO
,.s
45
Digital input is DMW codes
I
= - 5 V,
2.04B MHz,
I
Receive differential envelope delay time
t All typical values are at VBB
-40
=
UNIT
dB
30
-40 to -45 dBmO
Transmit single-frequency distortion products
Typt
36
E
o
(J
CD
= 25°C.
"i
transmit filter transfer over recommended ranges of supply voltage and operating free-air temperature
(see Figure 1)
PARAMETER
TEST CONDITIONS
MIN
MAX
16.67 Hz
-30
50 Hz
-25
200 Hz
Gain relative to gain
gain, Noninverting maximum gain
300 Hz to 3 kHz
at 1:02 kHz
output, Input Signal at ANlG IN +
is 0 dBmO
-1.8
-0.125
-0.15
-0.35
0.15
3.3 kHz
3.4 kHz
-1
-0.1
4.6 kHz and above
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
dB
0.03
-14
4 kHz
3.4 kHz (TCM29CI3N·3 only)
UNIT
-23
60 Hz
Input amplifier set lor unity
....
-32
-1.4
-0.1
2·101
...
TCM129C13. TCM129C14. TCM129C16. TCM129Cl1
TCM29C13. TCM29C14. TCM29C16. TCM29Cl1
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
receive fllter transfer over recommended ranges of supply voltage and operating free-air temperature
(see Figure 2)
PARAMETER
TEST CONDITIONS
Below 200 Hz
Gain relative to gain
Input signal at PCM iN
at 1.02 kHz
isO dBmO
200 Hz
300 Hz to 3 kHz
3.3 kHz
3.4 kHz
4 kHz
4.6 kHz and above
3.4 kHz (TCM29C13N-3 only)
~
CD
(')
o
3
3c
=
5"
I»
....
MIN
MAX
0.15
-0.5
-0.15
-0.35
-1
0.15
0.15
0.03
-0.1
-14
UNIT
dB
-30
-0.1
-1.4
clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see timing diagrams)
tc{CLKI
tro tf
tw{ClKI
tw{DCLKI
PARAMETER
Clock period for ClKX. ClKR (2.048-MHz systems)
MIN
Rise and fell times for ClKX and CLKR
Pulse duration for ClKX and ClKR (see Note 7) .
Pulse duration for DClK (fDClK = 64 Hz to 2.048 MHz) (see Note 7)
5
220
220
45
Clock duty cycle [tw(ClK)/tc(ClK)l for ClKX and ClKR
=
=
=
Typt
MAX
488
UNIT
ns
50
30
ns
ns
ns
55
%
S"
t All typical values are at VBB
(I)
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature. fixed-data-rate mode (see timing diagrams)
=
(")
-5 V. VCC
::;"
a:
25'C.
PARAMETER
(')
c
5 V. and TA
MIN
100
td{FSXI
Frame sync delay time
tsYLSIGX)
th(SIGX)
Setup time before Bit 7 falling edge (TCM129C14 and TCM29C14 only)
Hold time after Bit 8 falling edge (TCM 129C 14 and TCM29C 14 only)
MAX
tc{ClK)- 100
0
UNIT
ns
ns
ns
0
propagation delay times over recommended ranges of operating conditions. fixed-data-rate mode
(see timing diagrams)
tpdl
PARAMETER
From rising edge of transmit clock to Bit 1 data valid at
PCM OUT (data enable time on time slot entry) (see Note 8)
From rising edge of transmit clock Bit n to Bit n + 1 data
valid at PCM OUT (data valid time)
TEST CONDITIONS
Cl
=0
tpd3
Cl
=0
tpd4
From rising edge of transmit clock Bit 1 to TSX active
(low) (time slot enable time)
Cl
=0
Cl
=0
tpd5
tpd6
From falling edge of transmit clock Bit 8 to TSX inactive
(high) (timeslot disable time) (see Note 8)
From rising edge of channel time slot to SIGR update
(TCM129C14 and TCM29C14 only)
MAX
0
145
ns
to 100 pF
0
145
ns
60
215
ns
0
145
ns
60
190
ns
0
2
~s
= Oto
From falling edge of transmit clock Bit 8 to Bit 8 Hi-Z at
PCM OUT (data float time on time slot exit) (see Note 8)
tpd2
MIN
100pF
Cl
to 100 pF
NOTES: 7. FSX ClK must be phase locked with the ClKX. FSR ClK must be phase locked with ClKR.
8. Timing parameters tpdl. tpd3. and tpd5 are referenced to the high-impedance state.
2-102
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
UNIT
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature. fixed-data-rate mode (see timing diagrams)
PARAMETER
tdlFSRI
tsulPCM INI
thlPCM INI
MIN
100
Frame sync delay time
Setup time before Bit 7 falling edge ITCM 129C 14 and TCM29C 14 onlyl
10
Hold time after Bit 8 falling edge ITCM 129C 14 and TCM29C 14 onlyl
60
MAX
IcICLKI- 100
UNIT
ns
ns
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature. variable-data-rate mode (see timing diagrams)
tdlTSDXI
tdlFSXI
tclDCLKXI
PARAMETER
Timeslot delay time from DCLKX Isee Note 91
Frame sync delay time
MIN
140
100
Clock period for DCLKX
488
UNIT
MAX
tdIDCLKXI-140
tc1CLKI-100
15620
•
...
'3
ns
ns
kHz
II)
...
(,)
propagation delay times over recommended ranges of operating conditions. variable-data-rate mode
(see Note 10 and timing diagrams)
(3
II)
I:
tod7
tpd8
tod9
todl0
PARAMETER
Data delay time from DCLKX
TEST CONDITIONS
CL - Oto 100 pF
CL = 0 to 100 pF
Data delay from timeslot enable to PCM OUT
Data delay from time slot disable to PCM OUT
Data delay time from FSX
CL
=0
MIN
0
MAX
100
0
0
50
80
0
140
to 100 pF
tdlTSDXI
=
80 ns
o
UNIT
ns
'';::
IV
(,)
ns
'c::::I
ns
ns
E
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature. variable-data-rate mode (see timing diagrams)
PARAMETER
ldlTSDRI
tdIFSR)
tsu(PCM INI
thlPCM INI
tcIDCLKR)
tlSERI
MIN
140
100
Timeslot delay time from DCLKR Isee Note 111
Frame sync delay time
Setup time before Bit 7 falling edge
Hold time after Bit 8 falling edge
MAX
UNIT
tdIDCLKRI-140
ns
ns
10
60
488
Data clock frequency
Timeslot end receive time
tclCLKI-loo
E
o
(,)
CD
"i
I-
ns
ns
15620
0
ns
ns
64-kilobit operation timing requirements over recommended ranges of supply voltage and operating
free-air temperature, variable-data-rate mode
PARAMETER
tFSLX
Transmit frame sync minimum down time
tFSLR
Receive frame sync minimum down time
tDCLK
Pulse duration, data clock
NOTES:
TEST CONDITIONS
FSX - TTL high for
remainder of frame
FSR = TTL high for
remainder of frame
MIN
MAX
488
UNIT
ns
1952
ns
10
pS
9. tFSLX minimum requirement overrides the tdlTSDXI maximum requirement for 64·kHz operation.
10. Timing parameters tpd8 and tpd9 are referenced to a high-impedance state.
11. tFSLR minimum requirement overrides the tdlTSDRI maximum requirement for 64-kHz operetion.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-103
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
ClK. ClKR. and ClKX Selection Requirements for DSP Based Applications
1) It should be noted that the ClKX. ClKR. ClK must be selected as follows:
CLKSEl PIN
CLK. ClKR. ClKX
IBETWEEN 1.0 MHz to 3.0 MHzl
-5 vt
= 1256) x IFrame Sync Frequency)
OV
= (193) x IFrame Sync Frequency)
+5 V
= 1192) x IFrame Sync Frequency)
DEVICE TYPE
TCM129C13/14/16/17
TCM29C13/14116/17
TCM 129C13114
TCM29C13/14
TCM129C13/14
TCM29C13/14
-t
CD
E.G.: For Frame Sync Frequency = 9.6 kHz
CD
(')
o
3
3
c
ClKSEl PIN
~
C:;"
a
S"
~
a"c
::;:
-5 vt
=2.4576 MHz
OV
= 1.8528 MHz
+5 V
= 1.8432 MHz
DEVICE TYPE
TCM129C13/14/16/17
TCM29C13114116117
TCM129C13/14
TCM29C13/14
TCM129C13114
TCM29C13/14
tClKSEl is internally set to -5 V for TCM129C16/17 and TCM29C16/17.
en
(')
ClK. ClKR. ClKX
IBETWEEN 1.0 MHz to 3.0 MHz)
2) Corner frequency at 8 kHz Frame Sync Frequency = 3kHz
Therefore. the corner frequency = (3/8) x (Frame Sync Frequency). (For nonstandard frame sync.)
en
2-104
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75266
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
+0.15 dB
300 Hz
+0.03 dB
3300 Hz
o
o
2
i= -20
-20
...
j:
«
..J
::::I
-10
-10
-20
-20
W
tn
0:
(")
Ci
Z
c:I
~.
n
C
=
tn
-30
-30
-30 dB
-40
-40
-50
100
lk
FREQUENCY - Hz
NOTE: This is a typical transfer function of the receive filter component.
FIGURE 2. TRANSFER CHARACTERISTIC OF THE RECEIVE FILTER
2·106
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • OALLAS, TEXAS 75285
-50
10 k
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
I
ClKX
I
I+I I
'dIFSX)...!
FSX INPUT
INONSIGNALING
~--M-'cIClK)
Fi'.~
I
i
~~-----I~---------------------------------------------
--'i
FRAMES)
FSX INPUT
ISIGNALING
I
2 I
L
: -.t 14- "
-+I ~ 'dIFSX) )
J~
!4-'dIFSX)
...........dIFSX)
"1 ...
\!
~~------------------------------------------------
FRAMES)
FRAME SYNCHRONIZATION TIMING
...
II)
ClKX
'S
u
~
C3
PCMOUT
I
If-
TSXOUTPUT
~
I
,~
II)
-+114- 'pd5
I
I,
c:
o
as
u
'2
::::I
E
E
o
','VI
__________________________________________~____~.
'SUISIGX)~ 14-
.JX"
SIGX INPUT ____________________O_O_N_.T_C_A_R_E__________________
'';:::;
-':l.-'h ISIGX)
VALID
X"DON"T CARE
OUTPUT TIMING
FIGURE 3. TRANSMIT TIMING (FIXED·DATA·RATEI
u
Q)
Cii
I-
TIMESlOT1~
ClKR
1
I
'dIFSR)-.i1
FSR
INONSIGNALING
FRAMES)
FSR
(SIGNALING
FRAMES)
14'
I
2
-.I 14-.
I
I
dIFSR)
I
3
4
I
-.ilf-.,
5
I
If -+I
I
6
7
8
I
14- !.-M-1w1~lK)
I
14
~ 'cIClK)
..Ii~~
I
'-----rlI _____________________
__
-+t
-'
l4-'dIFSR)
~
l4-'dIFSR)
\~I
________________________________________________
FRAME SYNCHRONIZATION TIMING
ClKR
PCMIN
SIGR OUTPUT
---------------------------------------------------------INPUT TIMING
FIGURE 4. RECEIVE TIMING (FIXED-DATA-RATEI
NOTE: Inputs and driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and O.S V if the low
level is indicated.
tSit 1 = MSB = SIGN BIT and is clocked in first on the PCM-IN pin or clocked out first on the PCM-OUT pin. BIT S = LSB = LEAST
SIGNIFICANT BIT and is clocked in last on the PCM-IN pin or is clocked out last on the PCM-OUT pin.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-107
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE"CHIP PCM CODEC AND FILTER
I"
t i!
FSX
...,' I
~
,
I
-rj
i4-tdIFSXI
-J
'--'
-+I
I+-
3
3
'--'
L
I r--
i-- t pd10
PCM OUT ~~ BIT l ' I
CD
(")
o
,.--,
,.........
,......;
rh. I,....,\ I,....,\ :~.~ !n ~ !r.~ !r.1OW:
I I'
'--'1'--'
.......
--II
CD
,.........
:
~\ I,....,\ :---\
:
.......
tpdB-+I
I
t.I
i.'~16'.
' 7'
' "' B '
,5,
"
~
.......,
'--'
,.........,.--,
\-".,I
r.J...J
1 \",
CLKX
~
"'3'
r44"
•
'--',2.'--', ,'--'I, •
r,i'
-.I
-I
LL
~tdITSDXI
.
DCLKX
~
TIMESLOT
BIT 2
X
BIT 3
t
.......
-
-
-
T
I
tpd7
i+- pd9
X BIT B' )L---.j
BIT 4
X
BIT 5
X
BIT 6
,
BIT 7
t
FIGURE 5. TRANSMIT TIMING (VARIABLE-OATA-RATEI
c
+I
:::J
g"
FSR
"I
r+
0"
~td(TSDRI
~
1""":""\
... I
:::J
en
DCLKR
'I
T'"t
I
-+I 14- tdlFSRI
c
CLKR
Po
r\
\-J,
r---\
,
\-JI
,
r\I
tsulPSM INI-liof
~
,6,\....J,
7,
'--'
I
,.....,
I
\....J
B
1
I r-!!
~
~
I.-- tlSERI
I
I ,.,
,..,
U'n \-Jn "
,\-J",....,\-Jn "\ - I'
\-I
'u'
r---\
~,.....!
,
\-I
~
,...-,
I
I
I
I
;::;:
en
,5,
o;....J
I
:::;"
(")
~
r:-\
r""l...
2,\..-JI 311'--', 4 i
I
\....J
\....1...1
(')
\r--
I
I
-.I ~ thlPCM INI
I
I
~DON'l''''/'r-v7P~.!?7/';--'J?J7),.~J-V7/,/)'!-V;'7;,r''-\J'7l')r--l'77/,/;
PCM IN
~CARE0,\"""""~,-"'W\_../"'(/d\_f~\.._J'W\"",...~\_",.((ZJ'\......J~
BIT
,t
BIT
BIT
BIT
BIT
BIT
BIT
BIT
2
3
4
5
6
7
Bt
NOTE: All timing parameters referenced to VIH and VIL except tpd8 and tpd9. which reference a high~impedance state.
FIGURE 6. RECEIVE TIMING IVARIABLE-OATA-RATEI
NOTE: All timing parameters, referenced to VIH and VIL except tpdS and t p d9, which reference a high-impedance state.
tSit 1 = MSB = SIGN BIT and is clocked in first on the PCM-IN pin or clocked out first on the PCM-OUT pin. SIT S = LSB
SIGNIFICANT BIT and is clocked in last on the PCM-IN pin or is clocked out last on the PCM-OUT pin.
2-108
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
=
LEAST
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
GENERAL OPERATION
system reliability features
TheTCM129C13, TCM129C14, TCM129C16, TCM129C17, TCM29C13, TCM29C14, TCM29C16, and
TCM29C17 are powered up in four steps:
VCC and VBB supply voltages are applied.
All clocks are connected.
TTL high is applied to PDN.
FSX and/or FSR synchronization pulses are applied.
On the transmit channel, digital outputs PCM OUT and TSX are held in high-impedance state for
approximately four frames (500 /LsI after power up or application of VBB or VCC. After this delay, PCM
OUT, TSX, and signaling are functional and will occur in the proper timeslot. The analog circuits on the
transmit side require approximately 60 ms to reach their equilibrium value due to the autozero circuit settling
time. Thus valid digital information, such as for on/off hook detection, is available almost immediately,
while analog information is available after some delay.
On the receive channel, the digital output SIGR is .also held low for a maximum of four frames after power
up or application of VBB or VCC. SIGR will remain low until it is updated by a signalling frame.
To further enhance system reliability, PCM OUT and TSX will be placed in a high-impedance state
approximately 20 /LS after an interruption of CLKX. SIGR will be held low approximately 20 /Ls after an
interruption of CLKR. These interruptions could possible occur with some kind of fault condition.
U)
,~
..
C3
::::I
(,)
U)
c
o
'';:
ca
(,)
To minimize power consumption, a power-down mode and three standby modes are provided.
'2
::::I
E
E
For power down, an external low signal is applied to the PDN pin. It is not sufficient to remove the high
voltage to PDN. In the absence of a signal, the PDN pin floats to high and the device remains active. In
the power-down mode, the average power consumption is reduced to an average of 5 mW.
Q)
power-down and standby operations
o(,)
CD
I-
The standby modes give the user the option of putting the entire device on standby, putting only the transmit
channel on standby, or putting only the receive channel on standby. To place the entire device on standby,
both FSX and FSR are held at low. For transmit-only operation, FSX is high and FSR is held low. For receiveonly operation, FSR is high and FSX is held low. See Table 1 for power down and standby procedures.
TABLE 1. POWER DOWN AND STANDBY PROCEDURES
DEVICE
STATUS
PROCEDURE
Power down
Pi5iii low
Entire device on standby
FSX and FSR
Only transmit on standby
are low
FSX is low
Only receive on standby
FSR is high
FSR is low
FSX is high
TYPICAL POWER
CONSUMPTION
3mW
3mW
40mW
30mW
TEXAS
DIGITAL OUTPUT STATUS
TSi( and PCM OUT are in a high-impedance state;
SIGR goes to low within lOps.
TSi( and PCM OUT are in a high-impedance state;
SIGR goes to low within 300 ms.
"fID'(' and PCM OUT are placed in a high-impedance
state within 300 ms.
SIGA is placed in 8 high-impedance state
within 300 ms.
~
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-109
TCM129C13,TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
fixed-data-rate timing (see Figure 7)
Fixed-data-rate timing is selected by connecting DCLKR to VBB. It uses master clocks CLKX and CLKR,
frame synchronizer clocks FSX and FSR, and output TSX. FSX and FSR are 8-kHz inputs that set the
sampling frequency and distinguish between signaling and nonsignaling frames by their pulse durations.
A frame synchronization pulse one master clock period long designates a nonsignaling frame, while a doublelength sync pulse enables the signaling function (TCM129C14 and TCM29C14 only). Data is transmitted
on the PCU OUT pin on the first eight positive transitions of CLKX following the rising edge of FSX. Data
is received on the PCM IN pin on the first eight falling edges of CLKR following FSX. A digital-to-analog
(D/A) conversion is.performed on the received digital word and the resulting analog sample is held on an
internal sample-and-hold capacitor until transferred to the receive filter.
The clock selection pin (CLKSEL) is used to select the frequency of CLKX and CLKR (TCM129C13,
TCM129C14, TCM29C13, and TCM29C14 only). The TCM129C13, TCM129C14, TCM29C13, and
TCM29C14 fixed-data-rate mode can operate with frequencies of 1.536 MHz, 1.544 MHz, or 2.048 MHz.
The TCM129C16, TCM129C17, TCM29C16, and TCM29C17 fixed data rate mode operates at 2.048 MHz
only.
-4
CD
CD
n
o
3
3
c
I"
12345678
1921193/256
n'
m
....
PCM OUT
12345
XMIT SIGNAL FRAME
B7 B8 SIGX
-~-- -
B1 B2 B3 B4 B5,Bs B7 B8
TS1X---..i
I~---------
fS
FSX.II
0'
::::s
1921193/256
r---TIMESLOTS~
CLKX~~
::::s
fA
OTHER
'I
j+----- TS1X
- - - ----- -- --------------
::X::>OCC>CX::x::x3<::::::=
B, B2 B3 B4 B5 as 1
TSX~~_______________J;_1Ir-----------~-----1J~--~____________~-~I.-------
Q
...
n
1
===============n:=== ==~=====~~.x=:=::==::::_:::::x~:x:~::::,....~=
DON'T CARE
c
;::;.'
SIGX
fA
DON'T CARE
i+----- TS1R
VALID
OTHER
1921193/256
i---TlMESLOTS-----oi
\
~
I"
CLKR~l
2 3 4 5 6 7 8 9 ~
1921193/256
1
TS1R---..i
2
3
4
5
REC. SIGNAL FRAME
Sf
FSR.II
I~---------SIGR
PCM IN
=::>ocx:x::x:::: -------------- -~ --B1 B2 B3 B4 B5 Bs B7 B8
SIGR
---------------'~;---
H
H
PREVIOUS VALUE
FIGURE 7. SIGNALING TIMING (FIXED-DATA-RATE ONLY)
2-110
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
(
NEW VALUE
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, TCM29C16, TCM29C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
variable data rate timing
Variable-data-rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway
rather than to VBB. It uses master clocks CLKX and CLKR, bit clocks DCLKX and DCLKR, and frame
synchronization clocks FSX and FSR.
Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied
from 64 kHz to 2.048 MHz. The bit clocks can be asynchronous in the TCM129C14 and TCM29C14,
but must be synchronous in the TCM129C13, TCM129C16, TCM129C17, TCM29C13, TCM29C16, and
TCM29C17. Master clocks in types TCM129C13, TCM129C14, TCM29C13, and TCM29C14 are restricted
to frequencies of operation of 1.536 MHz, 1.544 MHz, or 2.048 MHz as in the fixed-data-rate timing mode.
The master clock for the TCM129C16, TCM129C17, TCM29C16, and TCM29C17 is restricted to
2.048 MHz.
While FSX/TSXE input is high, PCM data is transmitted from PCM OUT onto the highway on the next
eight consecutive positive transitions of DCLKX. Similarly, while the FSR/TSRE input is high, the PCM
word is received from the highway by PCM IN on the next eight consecutive negative transitions of DCLKR.
The transmitted PCM word will be repeated in all remaining timeslots in the 125 p's frame as long as DCLKX
is pulsed and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM
highway more than once per frame, if desired, is available only with variable-data-rate timing. Signaling
is allowed only in the fixed-data-rate mode because the variable-data-rate mode provides no means with
which to specify a signaling frame.
II)
"~
j
(,)
...
CJ
II)
c
o
",j:;
ca
(,)
"c
signaling
j
The TCM29C14 (only) provides 8th-bit signaling in the fixed-data-rate timing mode. Transmit and receive
signaling frames are independent of each other and are selected by a double-width frame sync pulse on
the appropriate channel. During a transmit signaling frame, the signal present on SIGX is substituted for
the least significant bit (LSB) of the encoded PCM word. In a receive signaling frame, the codec will decode
the seven most significant bits in accordance with CCITT G. 733 recommendations, and output the logical
state of the LSB on the SIGR pin until it is updated in the next signaling frame. Timing relationships for
signaling operations are shown n Figure 9. The signaling path is used to transmit digital signaling information
such as ring control, rotary dial pulses, and off-hook and disconnect supervision. The voice path is used
to transmit prerecorded messages as well as the call progress tones; dial tone, ring-back tone, busy tone,
and re-order tone.
E
E
o
(,)
Q)
Gi
I-
asynchronous operation
The TCM129C14 and TCM29C14 can be operated with asynchronous clocks in either the fixed- or variabledata-rate modes. In order to avoid crosstalk problems associated with special interrupt circuits, the design
of the TCM129C13, TCM129C14, TCM29C13, and TCM29C14 includes separate digital-to-analog
converters and voltage references on the transmit and receive sides to allow completely independent
operation of the two channels.
In either timing mode, the master clock, data clock, and timeslot strobe must be synchronized at the
beginning of each frame. Specifically, in the variable-data-rate mode the rising edge of CLKX must occur
within td(FSX) ns before the rise of FSX, while the leading edge of DCLKX must occur within tTSDX ns
of the rise of FSX. CLKX and DCLKX are synchronized once per frame but may be of different frequencies.
The receive channel operates in a similar manner and is completely independent of the transmit timing
(see variable data rate timing diagrams). This approach requires the provision of two separate master clocks
but avoids the use of a synchronizer, which can cause intermittent data conversion errors.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-111
TCM129C13, TCM129C14, TCM129C16, TCM129C17
TCM29C13, TCM29C14, Tc1III29C16, TCM29C17
COMBINED SINGLE·CHIP PCM CODEC AND FILTER
analog loopback
A distinctive feature of the TCM129C14 and TCM29C14 is their analog loopback capability. With this
feature, the user can test the line circuit remotely by comparing the signals sent into the receive channel
(PCM IN) with those generated on the transmit channel (PCM OUT). The test is accomplished by sending
a control signal that internally connects the analog input and output ports. WhenANLG LOOP is TTL high,
the receive output (PWRO + ) is internally connected to ANLG IN + , GSR is internally connected to PWRO - ,
and ANLG IN - is internally connected to GSX (see Figure 8).
,--------- r-__-4___
G~SX
- - - - - - - - - - - ANLGI
LOOP I
I
I
IPCM
......
TRANSMIT -H~--+
VOICE
OUT
DIGITIZED
AID
PCM
LOOPBACK
RESPONSE
PWRO+~~_~
_______
I
IN
I PCM
~
PWRO-~---.--------. .---~~
I
I
IL _ _ _ _ _
I
DIGITIZED
I
I
I
.J
TEST TONE
PCM
FIGURE 8. TCM129C14 AND TCM29C14 ANALOG LOOPBACK CONFIGURATION
Due to the difference in the transmit and receive transmission levels, a 0 dBmO code into PCM IN will
emerge from PCM OUT as a 3-dBmO code, an implicit gain of 3 dB. Because of this, the maximum signal
that can be tested by analog loopback is 0 dBmO.
precision voltage references
No external components ara required with the devices to provide the voltage references. Voltage references
that determine the gain and dynamic range characteristics of the device are generated internally. A difference
in subsurface charge density between two suitably implanted MOS devices is used to derive a temperatureand bias-stable reference voltage. These references are calibrated during the manufacturing
process. Separate references are supplied to the trensmit and receive sections, and each is calibrated
independently. Each reference value is then further trimmed in the gain setting operational amplifiers to
a final precision value. Manufacturing tolerances can be achieved of typically ± 0.04 dB in absolute gain
for each half channel, providing the user a significant margin to compensate for error in other board
components.
2-112
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
conversion laws
The TCM129C13, TCM129C14, TCM29C13, and TCM29C14 provide pin-selectable wlaw operation as
specified by CCITT G. 711 recommendation. A-law operation is selected when the ASEL pin is connected
to VBB. Signaling is not allowed during A-law operation. The TCM 129C 16 and TCM29C 16 are wlaw only.
The TCM129C17 and TCM29C17 are A-law only.
The wlaw operation is effectively selected by not selecting A-law operation. If the ASEL pin is connected
to vCC or GNO, the device is in I'-Iaw operation. If wlaw operation is selected, SIGX is a TTL-level input
that can be used in the fixed data rate timing mode to modify the LSB of the PCM output is signaling frames.
transmit operation
transmit filter
The input section provides gain adjustment in the passband by means of an on-chip uncommitted operational
amplifier. the load impedance to ground (ANLG GNO) at the amplifier output (GSX) must be greater than
10 kO in parallel with less than 50 pF. The input signal on the ANLG IN + pin can be either ac or dc coupled.
The input operational amplifier can also be used in the inverting mode or differential amplifier mode.
A low-pass antialiasing section is included on the device. This section provides 35-dB attenuation at the
sampling frequency. No external components are required to provide the necessary antialiasing function
for the switched capacitor section of the transmit filter ..
The passband section provides flatness and stopband attenuation that fulfills the AT&T 03/04 channel
bank transmission specification and CCITT recommendation G. 71 2. The device specifications meet or
exceed digital class 5 central office switching systems requirements.
A high-pass section configuration was chosen to reject low-frequency noise from 50- and 60-Hz power
lines, 17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency
noise. Even with the high rejection at these frequencies, the sharpness of the band edge gives low
attenuation at 200 Hz. This feature allows the use of low-cost transformer hybrids without external
components.
encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal sample
and hold capacitor. The encoder performs an analog-to-digital conversion on a switched capacitor array.
Digital data representing the sample is transmitted on the first eight data clocks bits of the next frame.
The autozero circuit corrects for dc offset on the input signal to the encoder. The autozero circuit uses
the sign bit averaging technique. The sign bit from the encoder output is long-term averaged and subtracted
from the input to the encoder. All dc offset is removed from the encoder input waveform.
receive operation
decoding
The serial PCM word is received at the PCM IN pin on the first ight data clock bits of the frame. Oigital-toanalog conversion is performed and the corresponding analog sample is held on an internal sample-andhold capacitor. This sample is transferred to the receive filter.
receive filter
The receive section of the filter provides passband flatness and stopband rejection that fulfills both the
AT&T 03/04 specification and CCITT recommendation G. 712. The filter contains the required compensation
for the (sin xlIx response of such decoders.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TEXAS 75265
2-113
TCM129C13. TCM129C14. TCM129C16. TCM129C17
TCM29C13. TCM29C14. TCM29C16. TCM29C17
COMBINED SINGLE-CHIP PCM CODEC AND FILTER
receive output power amplifiers
A balanced output amplifier is provided to allow maximum flexibility in output configuration. Either of the
two outputs can be used single-ended (i.e., referenced· to ANlG GND) to drive single-ended loads.
Alternatively, the differential output will directly drive a bridged load. The output stage is capable of driving
loads as low as 300 ohms single-ended to a level of 12 dBm or 600 ohms differentially to a level of 15 dBm.
The receive channel transmission level may be adjusted between specified limits by manipulation of the
GSR input. GSR is internally connected to an analog gain-setting network. When GSR is connected to
PWRO -, the receive level is at maximum. When GSR is connected to PWRO +, the level is minimum.
The output transmission level is adjusted between 0 and -12 dB as GSR is adjusted (with an adjustable
resistor) between PWRO + and PWRO - .
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions
(i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation
G.711).
-I
CD
CD
n
o
3
3
cj
c:;Q)
TYPICAL APPLICATION DATA
output gain set design considerations (see Figure 9)
....
o·
j
til
(")
PWRO + and PWRO - are low-impedance complementary outputs. The voltages at the nodes are:.
VO+ at PWRO+
VO- at PWROVOD = Vo + - VO- (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap connected to the GSR input.
:::;.
A value greater than 10 kO and less than 100 kO for R 1 + R2 is recommended because of the following:
c
The parallel combination of R1 + R2 and Rl sets the total loading.
The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant
that has to be minimized to avoid inaccuracies.
n
;:+
til
VA represents the maximum available digital milliwatt output response (VA
VOD
~11
I
VOD
vt
..L
®
PWRO+
Rl
~
R2
®
GSR
TCM129C13
TCM129C14
TCM129C16
TCM129C17
TCM29C13
TCM29C14
TCM29C16 PCM IN
TCM29C17
PWRO-
FIGURE 9. GAIN-SETTING CONFIGURATION
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
J
DIGITAL MILLIWATT
SEaUEN CE PER
CCITT G.711
..,.
2-114
3.06 V rms).
A-VA
1 + (R1/R2)
4 + (R1/R2)
Where A
RL
=
TCM129C18; TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
D3036, AUGUST 1987 - REVISED JUNE 1988
•
Reliable Silicon-Gate CMOS Technology
•
low Power Consumption
Operating Mode .. _ 80 mW
Power-Down Mode ... 5 mW
,..Law Coding
N DUAL-IN-LiNE PACKAGE
(TOP VIEWI
•
Excellent Power Supply Rejection Ratio Over
Frequency Range of 0 to 50 kHz
•
No External Components Needed for
Sample. Hold. and Auto-Zero Functions
•
Precision Intarnal Voltage Refarences
•
Single Chip Contains AID. D/A. and
Associated Filters
VBB
PWRO+
PWROPDN
DCLKR
PCM IN
FSR/TSRE
DGTL GND
VCC
GSX
ANLGIN
ANLG GND
TSX/DCLKX
PCM OUT
FSX/TSXE
CLK
...
'S
(I)
..
C3
(J
FEATURE TABLE
18 Pins
,.-Low Coding
Variable Mode:
64 kHz to 2.048 MHz
Fixed Mode:
2.048 MHz (TCM129C18. TCM29C181.
1.538 MHz (TCM129C19. TCM29C191
8-Blt Resolution
12-Blt Dynamic Range
(I)
c:
o
'';:;
ca
'2
(J
::l
E
E
o
description
(J
Q)
The TCM129C18. TCM129C19. TCM29C18. and TCM29C19 are low-cost single-chip pulse-codemodulated encoders and decoders (PCM codecs) and PCM line filters. These devices incorporate both the
AID and DIA functions. an anti-aliasing filter (AID). and a smoothing filter (D/A). These devices are ideal
for use with the TMS320 family members. particularly those featuring a serial port such as the TMS32020.
TMS32011. and TMS320C25.
a;
I-
Primary applications of these devices include:
Digital Encryption Systems
Digital Voice-Band Data Storage Systems
Digital Signal Processing
These devices are designed to perform encoding of analog input signals (AID conversion) and decoding
of digital PCM signals (D/A conversion). They are useful for implementation in the analog interface of a
digital-signal processing system. Both devices also provide band-pass filtering of the analog signals prior
to encoding and smoothing after decoding.
The analog input is encoded into an 8-bit digital representation by use of the wlaw encoding scheme
(CCITT G.711) which equates to 12 bits of resolution for low amplitude signals. Similarly. the decoding
section converts 8-bit PCM data into an analog signal with 12 bits of dynamic range. The filter characteristics
(bandpass) for the encoder and decoder are determined by a single clock input (ClK). The filter roll-off
( - 3 dB) is derived by:
fco = k • fClK/256 for the TCM 129C18 and TCM29C18 or fco
TCM 129C 19 and TCM29C 19
= k • fCLK/192 for the
where k has a value of 0.44 for the high-frequency roll-off point. and a value of 0.019 for the low-frequency
roll-off point.
PRODUCTION DATA documonts contain information
cumat as of publication data. Products conform to
.pacifications par the terms of Taxas Instruments
::=~.I~:l::li ~~~:~i:: :.:o::::~~~~ not
Copyright © 1987, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-115
TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
description (continued)
The sampling rate of the ADC is determined by the Frame Sync Clock, FSX; the sampling rate of the DAC
is determined by the Frame Sync Clock, FSR. Once a conversion is initiated by FSX or FSR, data is clocked
in or out on the next consecutive eight clock pulses in the fixed data rate mode. Likewise, data may also
be transferred on the next eight consecutive clock pulses of the data clocks, DCLKX and DCLKR, in the
variable data rate mode. In the variable data rate mode, DCLKX and DCLKR are independent, but must
be in the range from fCLK/32 to fCLK.
The TCM 129C 18 and TCM 129C 19 are characterized for operation over the temperature range of - 40°C
to 85 °C. The TCM29C18 and TCM29C19 are characterized for operation over the temperature range of
ooC to 70°C.
-I
functional block diagram
CD
a;-
TRANSMIT
SECTION
n
o
3
3
s:::
SAMPLE
AND HOLD
ANlGIN
:s
c:r
r+
cr
:s
D)
AUTO
ZERO
SUCCESSIVE
APPROXIMATION
COMPARA·
TOR
PCMOUT
OUTPUT
REGISTER
"ftl(/OClKX
GSX-~-....._J
ANALOG
T~~~!~~l·~_ _ _ _ _ _ _ _~~_~FsxnSXE
(II
lOGIC
ClK
o
::;'
RECEIVE
SECTION
n
s:::
;:;:
(II
PCM IN
PWRO+
DClKR
PWRO-·
Vee
2-116
Vaa DGTL ANlG
GND GND
TEXAS
FSRnSRE
-II
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
NAME
PIN
ANLG IN
14
ANLG GND
13
CLK
9
DCLKR
5
DESCRIPTION
Inverting analog input to uncommitted transmit operational amplifier
Analog ground return for all voice circuits. Not internally connected to digital ground.
Master clock and data clock for the fixed data rate mode. Master (filter) clock only for variable data-rate mode.
This clock is used for both the transmit and receive sections.
When this pin is connected to VBB. the device operates in the fixed-data-rate mode. When DCLKR is not connected
to VBB. the device operates in the variable-data-rate mode and OCLKR becomes the receive data clock. which
operates at frequencies from 64 kHz to 2.04B MHz.
DGTL GND
B
Digital ground for all internal logic circuits. Not internally connected to analog ground.
FSR/TSRE
7
Frame sync clock input/time-slot enable for the receive channel. In the variable-data-rate-mode. this signal must
remain high for the duration of the time-slot. The receive channel enters the standby state when FSA is TTL low
for 30 ms.
FSX/TSXE
10
GSX
15
II)
Frame synchronization clock input/time-slot enable for transmit channel. Operates independently of. but in an
"~
::::I
analogous manner to FSA/TSAE. The transmit channel enters the standby state when FSX is low for 300 ms.
...
(,)
Output terminal of internal uncommitted operational amplifier. Internally, this is the voice signal input to the transmit
filter.
PCM IN
6
U
Receive PCM input. PCM data is clocked in on this pin on eight consecutive negative transitions of the receive
II)
data clock, which is CLKR in fixed-data-rate timing and DCLKA in variable-data-rate timing.
PCM OUT
PDN
11
4
c
o
Transmit PCM output. PCM data is clocked out of this output on eight consecutive positive transitions of the
transmit data clock, which is CLKX in fixed-data-rate timing and DCLKX in variable-data-rate timing.
".j:j
Power-Down Select. On the TCM129C18 and the TCM29C18, the device is inactive with a TTL low-level input
"~
'C"
and active with a TTL high-level input to the pin. On the TCM129C19 and the TCM29CI9. this pin must be
::::I
connected to a TTL high level.
PWAO+
2
PWAO-
3
E
Noninverting output of power amplifier can drive transformer hybrids or high-impedance loads directly in either
E
a differential or a single-ended configuration.
TSX/DCLKX
12
VBB
1
VCC
16
o
(,)
Inverting output of power amplifier, functionally identical to PWRO +
Transmit channel time slot strobe (output) or data clock (input). In the fixed-data-rate mode, this is an open-drain
Q)
output to be used as an enable signal for a three-state-buffer. In the variable-data-rate mode, DCLKX becomes
Q)
the transmit data clock, which operates at TTL levels from 64 kHz to 2.048 MHz.
I-
Negative supply voltage, - 5 V ± 5%.
Positive supply voltage, 5 V ± 5%.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Vee (see Note 1) .
. . . . . . . . . . . . . . . . . .. -0.3 to 15 V
Output voltage, VO.. .. . .. . .. . .
. ......... -0.3 to 15 V
Input voltage, digital inputs, VI ...
........
-0.3 to 15 V
........
-0.3 to 15 V
Digital ground voltage. . . . . . . . . .
-10 o e to 80°C
Operating free-air temperature range. . . . . . . . . . . . . .
Storage temperature range .............................
- 65°C to 1 50°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTE 1: Voltage values for maximum ratings are with respect to VBS.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 6550t2 • DALLAS. TEXAS 75265
2-117
TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
recommended operating conditions (see Note 2)
MIN
VCC
Supply voltage (see Note 3)
4.75
Vaa
Supply voltage
4.75
DGTL GND voltage with respect to ANLG GND
CD
(')
o
3
3
c
:::s
(;'
...0'
Q)
:::s
en
MAX
5.25
5
-5 -5.25
0
V,H
High-level input voltage, all inputs except ANLG IN
V,L
V,PP
Low-level input voltage, all inputs except ANLG IN
Peak-to-peak analog input voltage
RL
Load resistance
4.2
10
PWRO + andlor PWRO-
Load capacitance
TA
Operating free-sir temperature
300
PWRO + andlor PWRO-
100
TCM29C18 or TCM29C19
V
V
II
50
TCM129C18 or TCM129C19
V
kll
GSX
CL
V
V
0.8
GSX
UNIT
V
2.2
-I
CD
NOM
-40
85
70
0
pF
·C
NOTES: 2. To avoid any possible damage and reliability problems to these CMOS devices when applying p!'wer, the following sequence
should be followed:
11) Connect ground
(2) Connect the most negative voltage
13) Connect the most positive voltage
(4) Connect the input signals.
When powering down the device, follow the above steps in reverse order. If the above procedure cannot be followed, connect
a diode between Vaa and DGTL GND, cathode to DGTL GND, anode to Vaa .
3. Voltages at analog inputs and outputs, V CC and Vaa terminals are with respect to the ANLG GND terminal. All other voltages
are referenced to the DGTL GND terminal unless otherwise noted.
4. Analog input signals that exceed 4.2 V peak-to-peak may contribute to clipping and preclude correct AID conversion. The
digital code representing values higher than 4.200 V is 10000000. For values more negative than 4.200 V, the code is 0000000.
(')
~'
(')
C
;:;"
electrical characteristics over recommended ranges of supply voltage and operating freecair temperature
supply current. fdclk - 2.048 MHz. outputs not loaded
en
PARAMETER
ICC
Supply current
from VCC
Supply current
lee
from Vee
TEST CONDITIONS
TCM129CXX
MIN
operating
standby
FSX or FSR at V,L after 300 ms
power down
Pl5N at V,L
after 10 ~s
operating
standby
FSX or FSR at V,L after 300 ms
power down
PDN at V,L after
10 ~s
TCM29CXX
MAX
MIN
MAX
14
10
1.5
1.2
1.2
-14
1
-10
-1.5
-1.2
-1.2
-1
UNIT
rnA
rnA
digital interface
PARAMETER
TEST CONDITIONS
MIN
= -9.6 rnA
IOH = -0.1 rnA
IOL = 3.2 rnA
V, = 2.2 V to VCC
V, = 0 to 0.8 V
2.4
IOH
TVpt
VOH
High-level output voltage, PCM OUT
VOL
Low·level output voltage,
I'H
High-level input current, any digital input
"L
Ci
Input capacitance
5
Co
Output capacitance
5
Low·level input current, any digital input
t All typical values are at Vae
2-118
m
= - 5 V,
VCC
=
5 V, and T A
=
25 ·C.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MAX
UNIT
V
3.5
0.5
V
12
~A
12
~A
10
pF
10
pF
TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
transmit side (AID) characteristics
PARAMETER
TEST CONOITIONS
Input ollset current at ANLG IN
VI
Input offset voltage at ANLG IN
VI
Input bias current
VI
=
=
=
MIN
-2.17 V to 2.17 V
MAX
UNIT
±25
mV
±100
nA
1
-2.17 V to 2.17 V
-2.17 V to 2.17 V
Open-loop voltage amplification at GSX
pA
5000
Unity-gain bandwidth at GSX
MHz
1
Input resistance at ANLG IN
10
Gain tracking error with sinusoidal input
3 dBmO to -40 dBmO,
REF level
REF level
(see Notes 5, 6, and 7)
-40 dBmO to -50 dBmO,
Transmit gain tolerance
Vi
Noise
Ref max output level:
Supply voltage rejection ratio,
Typt
Vee
or
Ves
Crosstalk attenuation, transmit-ta-receive
(single-ended)
=
1.06 V,
=0
I
=
f
=
=
±2.5
0.95
200 Hz to 3 kHz
= 200 mV P-P
= 0 dBm, f = 1 kHz unity gain,
= lowest decode level,
idle channel, Supply signal
PCM IN
±0.5
-10 dBmO
1.02 kHz
to 30 kHz, (measured at PCM OUT)
ANLG IN
II
-10 dBmO
dB
1.19
Vrms
-70
dB
-20
..
en
·S
..
C3
dB
Co)
62
dB
measured at PWRO +
Signal-ta-distortion ratio, with
sinusoidal input (see Note 8)
Absolute delay time to PCM OUT
ANLG IN - 0 to -30 dBmO
ANLG IN
ANLG IN
=
=
27
-40 to -45 dBmO
22
Fixed data rate, FCLKX
input to ANLG IN
=
=
en
c
33
-30 to -40 dBmO
2.048 MHz,
CIS
245
1 kHz at 0 dB
o
.';:;
dB
Co)
·c::s
~s
E
receive side (D/A) characteristics (see Note 9)
PARAMETER
Output offset voltage PWRO + and PWRO(single-ended)
MIN
TEST CONDITIONS
Relative to ANLG GND
Output resistance at PWRO + and PWRO-
1
Gain tracking error with sinusoidal input
3 dBmO to -40 dBmO,
(see Notes 5, 6, and 7)
- 40 dBmO to - 50 dBmO, REF level
Receive gain tolerance
Vi
Noise
Ref max output level:
Supply voltage rejection ratio, VCC or VBB
(single-ended)
Crosstalk attenuation, receive-ta-transmit
(single-ended)
Signal-ta-distortion ratio, sinusoidal input
(see Note 8)
Absolute delay time to PWRO +
Typt
f
=
=0
REF level
f
1.06 V,
=
= - 10 dBmO
= - 10 dBmO
1.02 kHz
UNIT
±200
mV
o
Co)
II
G)
2
±0.5
±2.5
1.34
200 Hz to 3 kHz
E
MAX
Q)
I-
dB
1.69
Vrms
-70
dB
to 30 kHz, idle channel,
Supply signal
= 200 mV P-P,
-20
dB
60
dB
narrow band, frequency at PWRO +
= 0 dB,
= 1 kHz at PCM OUT
ANLGIN = 0 dBmO to - 30 dBmO
ANLG IN = - 30 dBmO to - 40 dBmO
ANLG IN = -40 dBmO to -45 dBmO
Fixed data rate, FCLKX = 2.048 MHz
PCM IN
Frequency
33
27
dB
22
190
~s
t All typical values are at VBB = - 5 V, VCC = 5 V, and T A = 25°C.
NOTES: 5. Unless otherwise noted, the analog input is a O-dBmO, 1020-Hz sine wave, where 0 dBmO is defined as the zero-reference
point of the channel under test. This corresponds to an analog signal input of 1.064 V rms, or an output of 1.503 V rms.
6. The input amplifier is set for unity gain. The digital input is a PCM bit stream generated by passing a O-dBmO, 1020-Hz sine
wave through an ideal encoder.
7. The TCM129C18, TCM129C19, TCM29C18, and TCM29C19 are internally connected to set PWRO+ and PWRO - to OdBm.
All output levels are (sin xlIx corrected.
8. CCITT G. 712 ~ Method 2.
9. The receive side (DIAl characteristics are referenced to a 600-0 termination.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-119
TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
propagation delay times over recommended ranges of operating conditions. fixed-date-rate mode (see
timing diagrams)
tpdl
tpd2
tpd3
tpd4
-I
CD
CD
n
o
3
3
c
:::J
5'
I»
0'
...
:::J
tn
(")
::;'
n
c
::;.'
tn
tpd5
PARAMETER
From rising edge of transmit clock to bit 1 data valid at
PCM OUT (data enable time on time slot entry)
From rising edge of transmit clock bit n to bit n + 1
data valid at PCM OUT (data valid time)
From falling edge of transmit clock bit 8 to bit 8 Hi-Z at
PCM OUT (data float time on time slot exit)
From rising edge of transmit clock bit 1 to TSX active (low)
(time slot enable time)
From falling edge of transmit clock bit 8 to TSX inactive (high)
TEST CONDITIONS
MIN
MAX
CL
= 0 to
100 pF
0
145
ns
CL
= 0 to
100 pF
0
145
ns
60
215
ns
0
145
ns
60
190
ns
CL
CL
=0
= Oto
CL
(timeslot disable time)
100pF
=0
UNIT
propagation delay times over recommended ranges of operating conditions. variable-data-rate mode
PARAMETER
tpd6
tpd7
From DCLKX
From time slot enable to PCM OUT
tod8
tpd9
From time slot disable to PCM OUT
From FSX
TEST CONDITIONS
MIN
MAX
= Oto 100pF
CL = Oto 100pF
CL = Oto 100pF
td(TSDX) = 140 ns
0
100
50
CL
0
0
0
80
140
UNIT
ns
ns
ns
ns
clock timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see timing diagrams)
tcICLK)
t r• tf
PARAMETER
Clock period for CLK. (2.048-MHz systems)
MIN
488
Rise and fall times for CLK
5
220
220
tw(CLK)
Pulse duration for CLK
twIDCLK)
Pulse duration for DCLK (fDCLK - 64 Hz to 2.048 MHz)
45
Clock duty cycle ltw(CLK)/tc(CLK)l for ·CLK
Typt
MAX
30
UNIT
ns
ns
ns
ns
50
55
%
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature. fixed-data-rate mode (see timing diagrams)
PARAMETER
Frame sync delay time
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature. fixed-data-rate mode (see timing diagrams)
PARAMETER
Frame sync delay time
2-120
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM129C18. TCM129C19. TCM29C18. TCM29C19
ANALOG INTERFACE FOR DSP
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature. variable-data-rate mode
MIN
MAX
UNIT
tdlTSDXI
Delay time, times lot from DCLKX Isee Note 101
140
twlDCLKXI -140
ns
tdlFSXI
Delay time, frame sync
100
ns
twlDCLKXI
Pulse duration, DCLKX
488
tcICLKI- 100
15620
PARAMETER
ns
receive timing requirements over recommended ranges of supply voltage and operating free-air
temperature. variable-data-rate mode
tdlTSDRI
Delay time, times lot from DCLKR Isee Note 111
PARAMETER
MIN
140
tdlFSRI
tsulPCM INI
Delay time, frame sync T CICLKI
100
....!b.lE£M IN)
twIDC"KRI
t(SER)
MAX
UNIT
twIDCLKRI- 140
tc1CLKI-100
ns
Setup time, before bit 7 falling edge
10
ns
ns
Hold time after bit 8 falling edge
60
ns
488
ns
Pulse duration, DCLKR
15620
en
'S
...
(,)
(3
en
ns
0
Time slot end receive time
64-kbit operation timing requirements over recommended ranges of supply voltage and operating free-air
temperature. variable-data-rate mode
PARAMETER
Transmit frame sync
tFSLX
minimum down time
Receive frame sync
tFSLR
twCLK
minimum down time
TEST CONDITIONS
FSX
=
FSR
= TTL
TTL high for remainder of frame
high for remainder of frame
MIN
MAX
ns
488
ns
1952
10
Pulse duration, data clock
NOTES: 10. tFSLX min requirement overrides the td(TSCDX) max requirement for 64-kHz operation.
11. tFSLR min requirement overrides the te(TSOR) max requirement for 54-kHz operation.
UNIT
~s
II
...
C
o
'';:
CO
(,)
'2
::::J
E
E
o(,)
Q)
Q)
I-
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-121
-
TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
0.2 dB
3300 Hz
0
0
c
Ww
c-'
z«
~!t
w
•
-1
-t
III
CD
X
CD
n
0
...I
p
:::;,
0
I-
C:i"
>
r+
0"
:::;,
en
(")
0
""
I-
I»
0
N
3
3
C
-1
«
z
-10
-10
Ci
CI
w
~
-20
-'
w
TYPICAL FILTER
TRANSFER FUNCTION
II:
Z
Ci
CI
-30
:;"
n
c
::+
en
-40
-50
-50
FREQUENCY - Hz
NOTE: This is a typical transfer function of the receiver filter component.
FIGURE 1. TRANSFER CHARACTERISTICS OF THE TRANSMIT FILTER
2-122
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM129C18. TCM129C19. TCM29C18. TCM29C19
ANALOG INTERFACE FOR DSP
+2
+2
+1
+1
0.5 dB
200 Hz
EXPANDED
SCALE
0.5 dB
300 Hz
0
0
...
U)
...I
01
...
-1
-1
:l!
I-
Z
0
0
ClI
C
0
".j:i
as
0
I-
CJ
w
>
...~w
CJ
U)
C
C
.
C3
"3
-10
-10
"2
:::s
E
E
ex:
z
c
0
ClI
-20
-20
CJ
Q)
-a;
I-30
-40
100
1k
FREQUENCY - Hz
NOTE: This is a typical transfer function of the receiver filter component.
FIGURE 2. TRANSFER CHARACTERISTIC OF THE RECEIVE FILTER
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-123
TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
ClK
'd{FSXI
FSXINPUT
-.1,
I
I+I
2
I
-""
"'l
L
~td{FSXI
I
I
~~~--~II~------------------------------------
-f.
~
1+---~-'c{ClKI
FRAME SYNCHRONIZATION TIMING
ClK
I
I
tpd'-r-+t
I ..k--_r--"\
-I
CD
PCM OUT
CD
C')
o
I
I
tpd4 --tI
3
3
TSXOUTPUT
~
If-
:+- tpd5
~~______________________________________________________--,JI
t:
OUTPUT TIMING
n'
FIGURE 3. TRANSMIT TIMING (FIXED-DATA-RATE)
:s
0)
r+
TIMESlOT1~
0'
:s
(I)
ClK
...n
1
'd{FSRI-+j
FSR INPUT
C')
t:
I
I+-
-.I 14-.
f \ .I
I
I
2
3
'I
I -.114--.,
4
5
I
'f
-+I
I
6
7
B
I
14-- ~tW{~lKI
d{FSRI,
I
I.
14
I
tot
'c{ClKI
FRAME SYNCHRONIZATION TIMING
;:+'
(I)
INPUT TIMING
FIGURE 4. RECEIVE TIMING (FIXED-DATA-RATE)
NOTES:
A. Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the
low level is indicated.
B. Bit 1 is the most significant bit (MSB) and is clocked in first on the PCM IN input or is clocked out first on the PCM OUT
output. Bit 8 is the least significant bit (LSB) and is clocked in last on the PCM IN input or is clocked out last on the PCM OUT
output.
2-124
-1!1
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
14------------...
TlMESLOT
t
I
\
I
~tdITSDXI
I.t:-i.
~
DCLKX
r
I
.,.-
-J
CLKX
,...-.
1 -.;
:
..........
,.........
J
2 \
1
,
,
~
I
5
'---'
,.........
~
I
~
,...-.
6 \
'--'
I
'--'
7 \
:
'--'
~
8 \
"I
'----'
,......
,....,
,......
~ ~ "--'1 '
, ,
, ', ,, ., ,, ., ,u ,
1 , I ',~I '"
~
~
~
~
~
_I L
I
.....L..
,~
\W
' "•
~
,.........
i
4 \
'---'I
hI ' ",. . . , ,. . ., ,. . . .
tpd7-+j
...J:""""'"
3 \
'--'
jf-tdIFSXI
~
PCMOUT
LL
I
'
11
FSX'r
~I~
14-
...
"S
U)
--. r-- tpd6
--I :ct:~:pdi
BIT2
X
BITa
l
t
BIU
X
BITS
X
BIT6
Y
BIT7
X
Pd8
BIT---: t t
c:::
o
+I
«I
"';:;
CO
u
'
"2
I.----.i-IdITSDRI
DCLKR
..,' Ii 1"J-.-j
1,.\......J,~\..-.I r-:"'1..
3aI\..-J•r :4\io;;......t_,,.......,
5,\..-J,~\......J~\.....J 8:H'r-2,
,
\..l.J
I
-.j
CLKR
rPo
6,
I
tdlFSRI
,
~
,
~
,.,
,
\....I
,",,\1
,
INI~ I+-
r--\
,
I
1
I+- 'ISERI
n n ",...," "
n ,'
'u'I,...,\.
\...J
\....J
\....J
\....J
,.,
'.l .'
~,......
,
,7'
I
1
tsulPCM
PCMIN
u
U)
FIGURE 5. TRANSMIT TIMING IVARIABLE-OATA-RATEI
FSR
..
C3
1"""'\
~
~
:J
E
E
o
u
CD
Q)
I-
I
-.I ~ 'hlPCM INI
~~~:~~C@;C;OC@J~OCOC'@C~
BIT
1
BIT
BIT
BIT
234
BIT
5
BIT
BIT
67
BIT
8
NOTE: All timing parameters referenced to VIH and VIL except tpd7 and tpd8. which reference a high-impedance state.
FIGURE 6. RECEIVE TIMING (VARIABLE-OATA-RATEI
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 15265
2-125
TCM129C18. TCM129C19. TCM29C18. TCM29C19
ANALOG INTERFACE FOR DSP
GENERAL OPERATION
system reliability features
The TCM129C18, TCM129C19, TCM29C18, and TCM29C19 are powered up in four steps:
VCC and VBB supply voltages are applied.
All clocks are connected.
TTL high is applied to PDN.
FSX andlor FSR synchronization pulses are applied.
On the transmit channel, digital outputs PCM OUT and TSX are held in high-impedance state for
approximately four frames (500 ,..sl after power up or application of VBB or VCC. After this delay, PCM OUT,
TSX, and signaling are functional and will occur in the proper timeslot. The analog circuits on the transmit
side require approximately 60 ms to reach their equilibrium value due to the autozero circuit settling time.
Thus valid digital information, such as for onloff hook detection, is available almost immediately, while
analog information is available aftar some delay.
To furthar enhance system reliability, PCM OUT and TSX will be placed in a high-impedance state
approximately 20 ,..s after an interruption of CLKX. These interruptions could possibly occur with some
kind of fault condition.
power-down and standby operations
To minimize power consumption, a power-down mode and three standby modes are provided.
For power down, an external TTL low signal is applied to the PDN pin. It is not sufficient to remove the
TTL high voltage to PDN. In the absence of a signal, the PDN pin floats to TTL high and the device remains
active. In the power-down mode, the average power consumption is reduced to an average of 5 mW.
The standby modes give the user the option of putting the entire device on standby, putting only the transmit
channel on standby, or putting only the receive channel on standby. To place the entire device on standby,
both FSX and FSR are held at TTL low. For transmit-only operation, FSX is high and FSR is held low. For
receive-only operation, FSR is high and FSX is held low. See Table 1 for power down and standby
procedures.
TABLE 1. POWER DOWN AND STANDBY PROCEDURES
DEVICE
STATUS
2-126
PROCEDURE
Power down
PI5N
Entire device
on standby
FSX and FSR
are TTL low
Onlv transmit
on standby
FSX is TTL low
Onlv receive
on standby
FSR is TIL low
FSX is TIL high
= TIL low
FSR is TIL high
TYPICAL POWER
DIGITAL OUTPUT STATUS
CONSUMPTION
5mW
12mW
70mW
m
m
and PCM OUT are in a high-impedance state
and PCM OUT are in a high-impedance state
T§l( and peM OUT are placed in a high-impedance state
within 300 ms.
110mW
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR DSP
fixed-data-rate timing (see Figure 3 and 4)
Fixed-data-rate timing is selected by connecting DClKR to VBB. It uses master clock ClK, frame
synchronizer clocks FSX and FSR, and output TSX. FSX and FSR are 8-kHz inputs that set the sampling
frequency. Data is transmitted on the PCM OUT pin on the first eight positive transitions of ClK following
the rising edge of FSX. Data is received on the PCM IN pin on the first eight falling edges of ClK following
FSX. A digital-to-analog (D/A) conversion is performed on the received digital word and the resulting analog
sample is held on an internal sample-and-hold capacitor until transferred to the receive filter.
The TCM129C18 and TCM29C18 operate at 2.048 MHz only. The TCM129C19 and TCM29C19 operate
at 1.536 MHz only.
variable data rate timing
Variable-data-rate timing is selected by connecting DClKR to the bit clock for the receive PCM highway
rather than to VBB. It uses master clock ClK, bit clocks DClKX and DClKR, and frame synchronization
clocks FSX and FSR.
Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied
from 64 kHz to 2.048 MHz. The bit clocks must be synchronous; however, tha master clock is restricted
to 2.048 MHz.
While FSX/TSXE input is high, PCM data is transmitted from PCM OUT onto the highway on the next
eight consecutive positive transitions of DClKX. Similarly, while the FSR/TSRE input is high, the PCM
word is received from the highway by PCM IN on the next eight consecutive negative transitions of DClKR.
The transmitted PCM word will be repeated in all remaining timeslots in the 125 /Ls frame as long as DClKX
is pulsed and FSX is held high. This feature, which allows the PCM word to be transmitted to the PCM
highway more than once per frame, if desired, is available only with variable-data-rate timing.
asynchronous operation
...'Sen
..
o
(J
en
o
c
"..;:::
co
(J
'2
::::I
E
E
o
(J
Q)
In either timing mode, the master clock, data clock, and timeslot strobe must be synchronized at the
beginning of each frame. Specifically, in the variable-data-rate mode the rising edge of ClK must occur
within td(FSX) ns before the rise of FSX, while the leading edge of DClKX must occur within tTSDX ns
of the rise of FSX. ClK and DClKX are synchronized once per frame but may be of different frequencies.
The receive channel operates in a similar manner and is completely independent of the transmit timing
(see variable data rate timing diagrams).
Q)
~
transmit operation
transmit filter
The input section provides gain adjustment in the passband by means of an on-chip uncommitted operational
amplifier. The load impedance to ground (ANlG GND) at the amplifier output (GSX) must be greater than
10 k!l in parallel with less than 50 pF. The input signal on the ANlG IN pin can be either ac or dc coupled.
A low-pass antialiasing section is included on the device. This section provides 35-dB attenuation at the
sampling frequency. No external components are required to provide the necessary anti aliasing function
for the switched capacitor section of the transmit filter.
The passband section provides flatness and stopband attenuation that fulfills the AT&T D3/D4 channel
bank transmission specification and CCITT recommendation G.712. The device specifications meet or
exceed digital class 5 central office switching systems requirements.
A high-pass section configuration was chosen to reject low-frequency noise from 50- and 60-Hz power
lines, 17-Hz European electric railroads, ringing frequencies and their harmonics, and other low-frequency
noise. Even with the high rejection at these frequencies, the sharpness of the band edge gives low
attenuation at 200 Hz. This feature allows the use of low-cost transformer hybrids without external
components.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-127
TCM129C18, TCM129C19, TCM29C18, TCM29C19
ANALOG INTERFACE FOR OSP
encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal sample
and hold capacitor. The encoder performs an analog-to-digital conversion on a switched capacitor array.
Digital data representing the sample is transmitted on the first eight data clock bits of the next frame.
The autozero circuit corrects for dc offset on the input signal to the encoder. The autozero circuit uses
the sign bit averaging technique. The sign bit from the encoder output is long-term averaged and subtracted
from the input to the encoder. All dc offset is removed from the encoder input waveform.
receive operation
decoding
-I
The serial PCM word is received at the PCM IN pin on the first eight data clock bits of the> frame.
Digital-to-analog conversion is performed and the corresponding analog sample is held on an internal
sample-and-hold capacitor. This sample is transferred to the receive filter.
CD
CD
n
o
3
receive filter
3
The receive section of the filter provides passband flatness and stopband rejection that fulfills both the
AT&T 03/04 specification and CCITT recommendation G. 712. The filter contains the required compensation
for the (sin x)/x response of such decoders.
c::
..
j
(lr
C»
S'
j
receive output power amplifiers
A balanced output amplifier is provided to allow maximum flexibility in output configuration. Either of the
two outputs can be used single-ended (i.e., referenced to ANLG GND) to drive single-ended loads.
Alternatively, the differential output will directly drive a bridged load. The output stage is capable of driving
loads as low as 300 ohms single-ended to a level of 12 dBm or 600 ohms differentially to a level of 15 dBm.
(I)
(')
a'c::
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions
(i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation
G.711 ).
;:;.'
(I)
output gain
The devices are internally connected to set the PWRO + and PWRO - to 0 dBm.
2-128
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM3105JE, TCM3105JL
FSK MODEM
NOVEMBER 1985-REVISED APRIL 1986
•
•
•
Transmit Modulation at 75. 150. 600. and
1200 Baud
•
Receive Demodulation at 5. 75. 150. 600.
and 1200 Baud
•
•
•
•
•
•
•
J DUAL-IN-LiNE PACKAGE
Single-Chip Frequency-Shift-Keylng (FSK)
Modem
(TOP VIEW)
VOO
ClK
COT
RXA
TRS
NC
RXB
RXO
Meets Both Bell 202 and CCITT V23
Specifications
Half-Duplex Operation Up to 1200 Baud
Transmit and Receive
OSC2
OSC1
TXO
TXR1
TXR2
TXA
COL
VSS
...
U)
NC - No internal connection
Full-Duplex Operation Up to 1200 Baud
Transmit and 150 Baud Recaive
'S
On-Chip Group Dalay Equalization and
Transmit/Receive Filtering
C3
...CJ
U)
c
Carrler-Detact-Lavel Adjustment and CarrierFall Output
o
'';:::
Singla 5-V Power Supply
ca
Low Power Consumption
'2
CJ
:::I
Reliable CMOS Silicon Gate Technology
E
E
Caution_ These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
o
CJ
G)
'G)
~
description
The TCM3105 is a single-chip asynchronous Frequency Shift Keying (FSK) voiceband modem that uses
silicon gate CMOS technology to implement a switched capacitor architecture. It is pin selectable (TXR1.
TXR2. and TRS inputs) for a wide range of transmit/receive baud rates and is compatible with the applicable
BELL 202 or CCITT V23 standards. Operation is fully reversible. thereby allowing both forward and
backward channels to be used simultaneously.
The transmitter is a programmable frequency synthesizer that provides two output frequencies (on TXA).
representing the 'marks' and 'spaces' of the digital signal present on the TXO input.
The receive section is responsible for the demodulation of the analog signal appearing at the RXA input
and is based on the principle of frequency-to-voltage conversion. This section contains a group delay
equalizer (to correct phase distortion). automatic gain control. carrier detect level adjustment. and bias
distortion adjustment. thereby optimizing performance and giving the lowest possible bit error rate.
Carrier-detect information is given to the system by means of the carrier-detect circuits. which set a flag
on the COT output if the level of received in-band energy falls below a value set on the COL input for
a specified minimum duration.
The TCM3105JE is characterized for operation from -40°C to 85°C. The TCM31 05JL is characterized
for operation from OOC to 70°C.
PRODUCTION DATA d••• m.RlI ••ntaln inf.rmati.n
cunllIt II of publicatiDn data. Pr.ducts •••form t •
.....IIi.lli... par the tar....f T.... Instrumlnts
:=H~·r::.7.; ~~::':I' :'1·;::::::18":." not
Copyright @ 1985, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-129
TCM31 D5JE. TCM31 D5JL
FSK MODEM
PIN FUNCTIONAL DESCRIPTION
PIN
NO.
1
2
DESCRIPTION
NAME
VDD
CLK
COT
RXA
Positive supply voltage
Output for a continuous clock signal at16 times the highest selected (transmit or receive) bit rate
Carrier-Detect Output. A low-level output indicates carrier failure
3
4
5
TRS
6
NC
No internal connection
7
RXB
Receive Bias Adjust for external adjustment of the decision threshold of the final comparator to minimize bias
8
RXD
9
10
VSS
COL
11
12
TXA
TXR2
13
14
TXRl
TXD
Receive Analog Input to which the received line signal must be ae coupled
Transmit/Receive Standard Select Input, which, with TXRl and TXR2, sets the standard bit rates and
mark/space frequencies
-t
CD
CD
n
o
3
3
c
:1
5"
...0"
distortion
en
Carrier Detect Level Adjust for external adjustment of carrier detect threshold
Transmit Analog Output for the modulated signal, which must be ac coupled
Bit Rate Select 2 input, which, along with TXRl and TRS, sets the bit rates and mark/space frequencies
Bit Rate Select 1 input, which, along with TXR2 and TRS, sets the bit rates and mark/space frequencies
Transmit Digital Input for input data to the transmitter in positive logic. The high logic level is a mark and the
low logic level is a space. The data can be accepted at any speed from zero to the selected speed and may be
totally asynchronous.
I»
:1
Receiver Digital Output for the demodulated received data in positive logic. The high logic level is a mark and
the low logic level is a space.
Most negative supply voltage (normally ground); connected to substrate
15
OSCI
16
OSC2
Oscillator connections. The crystal (typically 4.4336 MHz) is connected to these pins. If an external clock is
used, OSC2 is left open and the clock is connected to OSC 1.
(")
~r
c
;::;."
en
2-130
TEXAS . .
INSTRUMENTS
POST OFFice BOX 655012 • DALLAS. TEXAS 75285
TCM3105JE, TCM3105JL
FSK MODEM
functional block diagram
TRANSMIT
ANALOG
OUTPUT
TRANSMIT
DIGITAL
INPUT
RECEIVE
AD~~~~
RXB~(7~)~
__________________________________________________~
RECEIVE
COMPARATOR (8) RXD
ANALOG
~~;I~~~
OUTPUT
INPUT
...
CI)
"3
...
Co)
CARRIER-DETECT
CARRIER
COL .;.(1:.,:0;,:.)________________________-i DETECTOR
LEVEL
OUTPUT
ADJUST
CI)
OSCILLATOR JoSCl
CONNECTIONS ~SC2
(15)
(16)
(13)
BIT RATE fiXRl
SELECT
(3
't
XR2
TRANSMIT I TRS
RECEIVE
STANDARD SELECT
(12)
I OSCILLATOR
4.4336 MHz
c:
o
+:::
r--
ca
TIMING
AND
CONTROL
(2)
"~
CLK
CLOCK
c:
:l
E
(5)
E
o
Co)
II)
timing diagram
-;
I-
RXA
INPUT
(AMPLITUDE
OF RECEIVED
SIGNAL)
- - ON-OFF THRESHOLD
.
I
I
I
I
I
COT
OUTPUT
f4-----tf-
td(on-off)
I
td(off-on)~1
I
I
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS. TeXAS 75265
I
I
I
I
I
2-131
TCM3105JE, TCM3105JL
FSK MODEM
absolute maximum ratings over free-air operating temperature range (unless otherwise noted)
Supply voltage, Voo (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 10 V
Input voltage, VI (any input) . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . .. -0.3 to VOO
Operating free-air temperature range: TCM3105JE ........................ - 55°C to 85 °C
TCM3105JL ........................ -10°C to 70°C
Storage temperature range ......................................... - 55°C to 150°C
NOTE 1: All voltage values are with respect to Vss.
recommended operating conditions
TCM3105JE
-4
CD
CD
n
o
3
3
cj
(=r
MIN
NOM
Supply voltage, VOO
High-level input voltage, VIH
4
5
Low-level input voltage, VIL
Analog input level, peak-to-peak (ac coupled)
0
Clock frequency, f clock
Analog load impedance at TXA
Operating
free~air
temperature range, T A
2
4.4334
MIN
NOM
5.5
4
5
VOO
0.8
2
0.30
0.78
4.4336
4.4338
50
-40
D)
r+
o·
j
en
(')
=i.
n
C
~
2-132
TCM3105JL
MAX
TEXAS •
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
5.5
VOO
0.8
0
4.4334
MAX
0.30
0.78
4.4336
4.4338
0
V
V
V
V
MHz
kO
50
85
UNIT
70
·C
electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
VOH
RXO,COT, ClK
IOH ~ -100
Val
Low-level output voltage
RXO, COT, ClK
IOl - 1.6 rnA
TXA
VOO
V
DO
VOO
peak-to-peak
RXB
Adjust voltage
2l
!;l
-
~~
~~
~
~
m
N
Analog output dc ollset
TXA
Digital input current
TXO, TRS, TXR1, TXR2
Analog input current
RXA
Bias input current
RXB, COL
VOO ~ 5 V
..
'"m
TCM3105JE
Typt
MAX
2.4
Vss
MIN
2.4
VOO
0.4
Vss
2.3
1.4
1.55
1.4
1.9
2.1
~
~
1.9
2.3
V
2.1
2.7
3.1
2.3
2.7
3.1
3.3
3.9
2.8
3.3
3.9
±1
~A
±15
±15
~A
± 150
± 150
~A
±1
6
5
10
5
8
8
16
8
12
3
Ci
Input capacitance, all inputs
10
10
Co
Output capacitance, all inputs
I
10
10
1 MHz
5
3
VOO - 5.5 V
I ~ 1 MHz
5 V
Phase jitter
Bias distortion:t:
V
V
VOO/2
VOO
~
V
2.8
3 V
V
VOO
0.4
2.3
VI - 0 to VOO
UNIT
1.55
VOO/2
VI
TCM3105Jl
Typt
MAX
Supply current
100
~;cr;;l
;; c:~
("I"l
COL
- 4 V I R ~ 50 kll
-5V!l
'
Cl ~ 100 pF
- 5.5 V I
MIN
VOO ~ 4 V
~
i:iz
;1! s:
JLA
High-level output voltage
Analog output voltage level,
~
TEST CONDITIONS
rnA
pF
pF
200
200
±15%
±15%
~s
Carrier detect threshold, off-on §
-45.5
-43
-45_5
-43
dBrn
Carrier detect threshold, on-off§
-48
-45.5
-48
-45.5
dBrn
2.5
Carrier detect hysteresis
2.5
2.8
2.8
dBrn
tAli typical values are at VCC ~ 5 V, TA ~ 25°C.
+Blas distortion is the departure from a 50% duty cycle when a series of alternating mark and space tones is received.
§This is the threshold with the COL input properly adjusted.
switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
TEST CONDITIONS
PARAMETER
tdloff-onl
tdlon-otf)
Carrier detect off-to-on delay time
Carrier detect on-ta-off delay time
Transmit frequency deviation from assignment
(see Table 11
~
W
W
tAli typical values are at VCC
TCM3105JE
Typt
MIN
MAX
TCM3105Jl
Typt
MIN
MAX
RX
~
600 or 1200 b/s
12
25
12
25
RX
~
5, 75, or 150 b/s
48
80
48
80
RX - 600 or 1200 b/s
12
20
12
20
RX
48
75
48
75
~
5, 75, or 150 b/s
Iclock ~ 4.4336 MHz
±1
±1
-------
--------
UNIT
ms
-t
n
~
w
=
U'I
Co.
!"
ms
Hz
r;;-t
=-=n
~!
Q-
C=
mU'l
5 V, TA ~ 25°C.
~:=
Telecommunications Circuits
TCM31 D5JE. TCM31 D5JL
FSK MODEM
PRINCIPLES OF OPERATION
The TCM31 05 FSK modem is made up of four functional circuits. The circuits are the transmitter, the receiver,
a carrier detector, and control and timing (See Figure 1).
BIAS ADJUST
ANALOG INPUT
--f----,
n(7:!..)
RXB";"
RXA (4)
(10)
~
CD
o
3
3
~__-.:.:(3;:..) CDT
DETECT OUTPUT
--'--;_'::'::;:::':::'-.1
TXR1, TXR2, TRS
!211!:3:!.!)(~12~)!.!:(5~).r-Tii;';iG-l
MASTER CLOCK (INTERNAL)
n
DIGITAL OUTPUT
CDL
LEVEL ADJUST
DIGITAL INPUT
TXD ..;,11;,.;4,;.)__~
(8) RXD
~--~~
1-_.....:(=2):,. CLK
CLOCK OUTPUT
~__....;(..;..11;.;..) TXA
ANALOG OUTPUT
c
:::s
FIGURE 1. TCM3105 SYSTEM PARTITIONING
(Ii'
....
c)"
C»
transmitter
:::s
en
The transmitter comprises a phase coherent FSK modulator, a transmit filter, and a transmit amplifier.
The modulator is a programmable frequency synthesizer that drives the output frequencies by variable
division of the oscillator frequency (4.4336 MHz). The division ratio is set by the states of the
Transmit/Receive Standard input (TRS), the Bit Rate Select inputs (TXR1 and TXR2), and the Digital Data
input (TXD).
n
:::;"
n
c
;:;'"
A switched-capacitor low-pass filter limits the harmonics and noise outside the transmit band and the
characteristics of this filter are set by the frequency select inputs as previously described. The harmonics
introduced by the transmit filter clock are removed by a continuous low-pass filter.
en
The transmitter output level varies with power supply voltage and so must be compensated in the 2-wire
to 4-wire converter to give a constant output level to the line.
receiver
A continuous low-pass anti-aliasing filter is followed by the receive amplifier, which automatically controls
the gain to give a constant output level from the receive filter. The receive filter limits the bandwidth of
the signal presented to the demodulator, reducing out-of-band interference, and has very high rejection
of the transmit channel frequencies. These are typically present at much higher levels than the received
signal.
The group delay equalizer is a switched-capacitor network that compensates the delay introduced by the
receive filter and the network. The output from the equalizer is then limited to give an FSK modulated
squarewave that is presented to the demodulator.
The demodulator is an edge-triggered multivibrator that triggers off positive and negative gOing edges.
The output of the demodulator is, therefore, a stream of constant-length pulses at a frequency that is
double the frequency of the limited input signal. The dc component of this signal is proportional to the
received frequency and is extracted by a switched-capacitor, low-pass, post-demodulator filter.
The variation of dc level with received frequency is presented to a comparator that slices at a level externally
fixed by the RXB bias adjustment pin. This voltage depends on received bit rate and internal offsets. The
comparator output is then the received data at the RXD output.
2-134
TEXAS . "
INSTRUMENTS
POST OFFICE BOX $55012 • DALLAS, TEXAS 76266
TCM3105JE. TCM3105JL
FSK MODEM
carrier detect
The carrier detect circuits comprise an energy detector and digital delay. The energy detector compares
the total signal level at the output of the receive filter to an externally set threshold level on the COL input.
The comparator has a 2.5-dB hysteresis and a delay to allow for momentary signal loss and to prevent
oscillation. The output of the detector is available on the COT pin where a high level indicates that a carrier
is present. The data output is clamped to a MARK condition when the carrier detect output switches off
at the end of transmission.
control and timing
An on-chip oscillator runs from an external 4.4336-MHz crystal connected between the OSC1 and OSC2
pins or an external signal driving OSC1. A clock signal equal to 16 times the highest selected bit rate (transmit
or receive) is available on the ClK output.
The single-supply rail means that all analog functions are referenced to an internally generated reference.
All analog inputs and output must be ac coupled.
PI
...
U)
'S
u
~
C3
transmit and receive modes
U)
The various modes of operation of the TCM3105 are given in Table 1. The data convention is that a logic
high is a mark and a logic low is a space.
c
o
'.t=
ca
u
'2
~
E
E
ou
II)
'ii
t-
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-135
TCM3105JE, TCM3105JL
FSK MODEM
TABLE 1. MODES OF OPERATION
STANDARD
TRS
TXR1 TXR2
TRANSMITTED
BAUD RATE
RECEIVED
BAUD RATE
TRANSMIT
FREQUENCY
ASSIGNMENTS
RECEIVE
FREQUENCY
ASSIGNMENTS
(Hzl
(Hzl
l
l
l
1200
1200
H
l
l
1200
75
L
L
H
600
75
H
L
H
600
600
L
H
L
75
1200
H
H
l
75
600
L
H
H
75
75
5'
Q)
ru
L
L
1200
1200
:s
o
ru/8
L
H
1200
150
rulS
L
H
1200
5
ClK
H
l
150
1200
ClK
H
H
150
150
ClKt
Ht
Ht
Ht
It
Ht
5
1200
-I
CCITT
V.23
CD
CD
(")
o
3
3
c
:s
...S'
o
::;'
g
BEll 202
::+'
o
H
H
H
Transmit
Disabled
1,200
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
1300
2100
1300
2100
1300
1700
1300
1700
390
450
390
450
390
450
1200
2200
1200
2200
1200
2200
387
487
387
487
387
0
Transmit
Disabled
H = high level. L = low level
tin these modes. the modulation is controlled by the TRS and TXR2 pins. TXD is tied high.
2-136
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • OAUAS, TEXAS 76266
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
M
S
1300
2100
390
450
390
450
1300
1700
1300
2100
1300
1700
390
450
1200
2200
387
487
387
0
1200
2200
387
487
1200
2200
1200
2200
ClK
FREQUENCY
(kHzl
19.11
19.11
9.56
9.56
19.11
9.56
1.19
19.11
19.11
19.11
19.11
2.39
19.11
19.11
lCM31 D5JE, lCM31 D5JL
FSK MODEM
APPLICATION INFORMATION
VOO, VSS, OR ClK
(51
TRS
(11
VOO
VOO
HI--III-'(.;.ll"fl TXA
...
'5
U)
LINE
SIGNALING
LINE
TERMINATION
2-WIRE
TO
4-WIRE
CONVERTER
TCM31 05
FSKMOOEM
MICROPROCESSOR
RXO (81
...u
C3
U)
(41
I-I~II-"'I
c:
RXA
ClK
~(:::.21:.-......J
TXR1~(~13~I______~__~
TXR2f(~12~I______~__~
COTf(:::.31~-----.__--~
o
".Q
as
u
'2
:::J
E
E
o
u
G)
"i
I-
FIGURE 2_ TYPICAL SYSTEM CONFIGURATION
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-137
lCM3105JE. lCM3105JL
FSK MODEM
APPLICATION INFORMATION
~30PF
3OpF~
(151
OSCL
RECEIVE
DATA
(81
5V
RXB 1o'1_71_+< 100 kn
(141 TXD
TRANSMIT
DATA
TCM3105
111
VDD
5V
-I
RXD
(161
OSC2
5V
TXGAIN ADJ
100kn
CD
CD
g
3
3
c
::J
c:;'
....
C»
0'
CARRIER
DETECT
(B~?~~~E{
(31
T
E
R
(21
AND
STANDARDI
::J
(II
o:::;'
n
c
;:;'
(II
U1 = LM124
FIGURE 3. TELEPHONE LINE INTERFACE CIRCUIT
2-138
1:1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TeXAS 76285
TCM3105JE, TCM3105JL
FSK MODEM
APPLICATION INFORMATION
A
100 kll
ZlZT = 60011
[:
100 kll
ZT'
VDD
5V
100 kll
...
II)
(10 COL
5V
TCM3105
RECEIVE DATA
TRANSMIT DATA
STANDARD AND
BIT RATE
f
1;
{BI
47 kll
RXD
..
'S
(,)
(3
{141 TXD
II)
{131 TXR1
o
c:
{121 TXR2
{51 TRS
CARRIER DETECT
{31 COT
CLOCK
{21 ClK
'+0
ca
(,)
RXA ~(~41~'I-1_<'
100 kll
100 kll
Vss
U1 = %lM124
(91
'2
:::s
E
E
o(,)
Q)
FIGURE 4, SIMPLIFIED TELEPHONE LINE INTERFACE CIRCUIT
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • OAL.LAS. TEXAS 75265
CD
I-
2·139
-4
CD
CD
(')
o
3
3
cj
5'
...
I»
0'
j
en
(")
:::;'
(')
c
;:;:
en
2-140
TCM4204A. TCM4205A. TCM4207 A
SUBSCRIBER-LiNE-CONTROL CIRCUITS
NOVEMBER 1983-REVISED APRIL 1988
•
Per-Channel-Programmable Single-Chip
Subscriber-Line-Control Circuit (SLCC)
•
Programmable TX and RX Gain
•
Digital Inputs and Outputs are Compatible
with TTL Levels
•
± 5 V Power Supplies
•
Software-Selectable External Balance
Networks
•
On-Off Hook Detection, Ring Trip
•
TCM4205A Provides Control of the Three
Auxiliary Relays and Ground Start
Supervision
TCM4204A. TCM4207A ... J PACKAGE
(TOP VIEWI
VSS
RXO+
RXOANLG GND
BALOT
RXIN
CLKM
R/W
CE
DATA 1/0
AUX1
OGTL GND
4
VDD
TXOT
TXI+
TXITXFB
BALO
BAL1
BAL2/SUPOT*
SUPSUP+
RNGR
CLKS
fI)
,~
j
..
C3
U
*BAL2 for TCM4204A. SUPOl for lCM4207A
•
Serial Interface to Microprocessor
•
High-Reliability Silicon-Gate CMOS
Technology
•
TCM4207A Uses a Flux Canceling
Technique that Allows Use of a Smaller
Transformer
fI)
c:
TCM4205A ... J PACKAGE
o
(TOP VIEWI
description
The TCM4204A, TCM4205A, and TCM4207 A
are subscriber-line-control circuits (SLCC)
designed to provide all the functions of a
complete voice-band PCM channel when used
in conjunction with appropriate codec and filter
circuits. The TCM4205A enhancement of the
TCM4204A brings out two additional relay
control pins (AUX2) and (AUX31. an external
reference for ground-start applications (GS REF).
and a pin for control of an external power supply
(PWRU). The TCM4207A replaces BAL2 with a
filtered analog output (SUPOT) that can be used
in flux canceling applications.
VSS
RXO+
RXOANLG GND
BALOT
RXIN
CLKM
R/W
CE
DATA 1/0
AUX1
AUX2
AUX3
DGTL GND
'';;
CO
,~
VDO
TXOT
TXI+
TXITXFB
BALO
BAL1
BAL2
GS REF
SUPSUP+
PWRU
RNGR
CLKS
c:j
E
E
o
u
Q)
4)
I-
The primary applications for these devices include:
Transmission Systems and Switching Systems
2-Wire Interface
4-Wire Interface
Subscriber Line Concentrators
These devices are characterized for operation from O°C to 70°C.
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCTIOI DAIA d.c••lnts cantlin inf.rmatian
current .8 of publication datI. Products canfor. to
.pacifieoti... pol' the tsam••, loulln_mom
:'~~~~i~ai~:1~7i ~::\~~i:f :r:::~":t:~" not
Copyright © 1983, Texas Instruments Incorporated
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
2-141
TCM4204A, TCM4205A, TCM4207A
SUBSCRIBER-LiNE-CONTROL CIRCUITS
analog section
Separate Programmable Attenuators: 63 steps covering a 12.6-dB range in O.2-dB steps
6-dB Differential RX amplification for driving a 900-ohm load to a peak of 3.2 V
Software-selectable external balance networks. Electronic 2-wire to 4-wire conversion.
Software-controlled analog loop back
Separate RX and TX paths allow true 4-wire operation.
supervision
Normal loop-start and/or ground-start supervision
Ring trip supervision
Supervision function provided with minimal, low cost external components.
-f digital interface
CD
CD
Simple four-pin serial interface provides easy-to-use microprocessor interface.
Clocks can be any of the standard PCM clock frequencies.
Power fault detection lets user know when RAM has been affected by a supply fault.
n
o
3
3
software control
r::
Up to three external balance networks
Transmit and receive attenuators
Power down, standby, voice, or loopback modes of operation
Ring relay and up to three auxiliary relays.
::::I
C:;"
....
0)
0"
::::I
til
system block diagram
vss
(')
=i"
n
r::
::+
til
MICROPROCESSOR
CONTROL
BAL
SEL
TCM4204A
2-142
TEXAS ",
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75266
TCM4204A, TCM4205A, TCM4207 A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
functional block diagram (positive logic)
TCM4204A
ANlG
OND
Vss
Voo
DGTL
ONO
REFt
;X>---RXO+
RXIN
- - - - - - - - - 1 ATTE=~ATOR 1>-..-------...,
FROM
lTOB
elKS
~
CLOCK '·.2'
~L_C_'R_C_U_IT.....!-
DECODERS
:;>----RXO-
'-'.........f~. . . L------BALOT
...en
·S
(J
BALO
BAL'
BAL2 ITCM4204A. 4205A)
~
(3
en
c
TXFB------,
o
.~
TX1+
TXOT
TXI-
CO
(J
"2
::J
E
E
o
(J
Q)
, - - - - t - - - - + - - - t - - f - - - - - S U P O T ITCM4207A)
"i
I-
AUX1
AUX2 ITCM4205A)
AUX3 ITCM420SAI
ANGn
CENZ
CLKM
PWRU ITCM4205A1
REWZ
r--------==rIC~------------~BAL
, . -_ _':';AANDB
•
V
TO TX ATTENUATOR
TO RX ATTENUATOR
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-143
TCM4204A. TCM4206A. TCM4207 A
SUBSCRIBER·lINE·CONTROL CIRCUITS
NAME
ANlG GND
AUXI
AUX2
AUX3
BAlO
BAll
BAl2
BAlOT
-I
CD
TCM4204A
4
11
19
18
17
5
PIN
TCM4205A
4
11
12
13
23
22
21
5
TCM4207A
4
11
Latched digital outputs for relay control
19
18
A buffered form of the RX signal for application to the external balance
network
Chip enable. Activated by a logic low input.
Digital clock input that advances the pointer counter of the digital
storage unit (DSU) allowing the information in the DSU to be
accessed. When RiW and ~ are low. information on the
DATA I/O pin is latched into the DSU by the falling edge of ClKM.
A continuous clock input (from 1.536 to 2.048 MHz) used for internal
logic. This signal is not synchronous with any other signal.
CE
ClKM
9
7
9
7
9
7
ClKS
13
15
13
DATA I/O
10
10
10
DGTl GND
GS REF
PWRU
12
14
20
12
RNGR
14
16
14
RXIN
RXO+
RXO-
6
2
3
5
2
3
6
2
3
RiW
8
8
8
15
16
18
19
15
16
20
22
21
23
24
1
24
26
25
27
28
1
20
22
21
23
24
1
CD
::::J
c:r
I»
P+
0'
::::J
(I)
(')
17
=i'
n
c
;:+
(I)
SUP+
SUPSUPOT
TXFB
TXI+
TXITXOT
VDD
VSS
2-144
Analog input to balance network selection
5
n
o
3
3
c
DESCRIPTION
Analog ground
17
Digital data input/output. When CE is low and RiW is high. the
DATA I/O pin is in the output mode. When ~ is low and R/W is
low, the DATA I/O pin is in the input mode. When ~ is high. the
DATA I/O pin Is in the high-impedance state.
Digital ground
Analog reference voltage input used for ground stert supervision.
Decoded digital output of Mode Control used to control an external
power supply.
Latched digital output to control the ring relay. The output turns off
(low) when off-hook is detected. but the controller must program
the ring bit low to ensure that the output remains low.
Analog input to the receive section
Complementary analog output of the receive amplifier
Digital input control for the direction of response of the digital
storage unit. A logic high on RiW sets the DSU to transmit
information. A logic low on R/W enables the DSU to receive
information.
Differential analog supervision inputs. Inputs to SUP + and SUPare used to detect off-hook status during normal and ringing
supervision.
Filtered supervisory analog output
Feedback out of TX input amplifier
Analog differential Inputs to TX input amplifier
Analog output of TX output amplifier
Supply voltage {5 V ± 5'16}
Supply voltage (- 5 V ± 5%) referenced to ANlG GND
TEXAS
-II
INS1'RUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM4204A, TCM4205A, TCM4207 A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, Voo ....................................................... 6 V
Supply voltage, VSS ...................................................... - 6 V
Input/output voltage: digital ................................ VOO + 0.3 V to GNO - 0.3 V
analog. . ... .. .. . .. . .. . .. . . .. . ..... .. .. VOO+0.3 V to VSS-0.3 V
Operating free-air temperature range ..................................... OOC to 70°C
Storage temperature range ........................................ - 55°C to 125°C
recommended operating conditions
MIN
MAX
UNIT
Supply voltage, VDD (see Note 1)
4.75
5.25
V
Supply voltage, VSS (see Note 2)
-4.75
-5.25
V
CI)
,t:
V
..
C3
DC offset voltage at analog input to RX section (RXIN)
±25
mV
fn
DC offset voltage at transmit inputs (TXI + and TXI - )
±25
mV
low-level input voltage, Vil
DC voltage at either supervision input (SUP+ or SUP-)
O.B
V
±2.5
V
±3
SUPOT voltage
Load capacitance, CL
V
2.4
High-level input voltage, VIH
BAlOT, TXOT, SUPOT, TXFB
25
100
RXO+, RXO-
pF
100
kG
Rise time (any logic input), tr
100
ns
Fall time (any logic input). tf
100
ns
Load resistance, Rl
BAlOT, TXOT, SUPOT, TXFB
RXO+, RXO-
300
Clock frequency fClKS
1.536
0
Operating free-air temperature, T A
NOTES:
5
1. Reference is to DGTL GND and ANlG GND.
2. Reference is to ANlG GND.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
G
2.04B
70
MHz
°C
;j
(,)
C
o
'';:
CO
,~
C
;j
E
E
o(,)
Q)
Q)
t-
2-145
TCM4204A, TCM4205A, TCM4207 A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
static electrical characteristics over recommended operating free-air temperature range, Voo
Vss - - 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH High-level output voltage
VOL Low-level output voltage
10H
=
-0.4 mA
MIN
4.6
Typt
10L - 1.6 mA
MAX
= 5 V,
UNIT
V
0.4
V
8
V
Differential voltage between
VDO and VSS required to
initiate POR (power-on-reset)
Differential voltage between
SUP + and SUP - required to
initiate off-hook condition
-I
CD
(')
o
c
:::::I
5"
Q)
...0"
II
Input current, analog
TXI+,
TXI-,
BAL1.
BAL2
IIH
High-level input current
IlL
Low-level input current
10H High-level output current
(')
10L
:::;"
6
Voice mode, SUP- at OGTL GNO
OSU bit 23 high
Standby and power-down mode,
SUP- at DGTL GNO
-20
0
25
.20
50
100
mV
1
-1
VI
=
5V
VI
=
-5 V
1
~A
BALO,
:::::I
o
> 1 V/ms
SUP+, VI - 3 V
SUP- VI - -3 V
RXIN,
CD
3
3
dVoo/dt
Low-level output current
(')
VI = 5 V
VI - 0
digital
data
digital
data
TXOT
C
;:;'
Analog output
offset voltage
o
Receive output dc leakage
current (See Note 3)
100 Supply current
-1
TXF8
RXO+
RXO-
1
-1
VOH - 2.5
VOH = a (continuous)
VOL - 2.5 V
VOL = 5 V (continuous)
Loopback mode,
RXO + connected to RXO - through
a 600 II resistor
On hook, power-down mode
On hook, voice mode
Off hook, power-down mode
On hook, power-down mode
Supply current
1.6
mA
55
±50
±25
±75
Voice mode, RXIN at ANLG GNO
Voice mode, RXIN at ANLG GND
SUPOT SUP + and SUP - at ANLG GNO
Standby or power-down mode,
On hook, voice mode
Off hook, power-down mode
Off hook, voice mode
~
mA
TXI + ITXI- at ANLG GND
TXI + at ANLG GNO,TXI- tied to TXFB, Loopback mode
Off hook, voice mode
ISS
1.6
-10
~A
mV
±75
220
±20
~A
3
9
6
13
-3
-9
-6
-13
mA
mA
tAli typical values are at VOO = 5 V, VSS = -5 V, TA = 25°C.
NOTE 3: If used with a center-tapped transformer (with center tap connected to GNO), the output leakage current will increase.
2-146
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM4204A, TCM4205A, TCM4207A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
dynamic characteristics over recommended ranges of supply voltage and operating free-air temperature
(unless otherwise noted)
PARAMETER
TEST CONDITIONS
Input to RXIN
Receive output dynamic
range (RXO +. RXO - )
=
RL = 900 0 to ANLG GND. Receive channel
attenuator set to code 100111 (0 dB).
f
=
1.02 kHz
Input to RXIN Receive output dynamic
range (BALOT)
-75 dBm to 3 dBm.
-75 dBm to 3 dBm.
RL = 5 kO to ANLG GND. Receive channel
attenuator set to code 100111 (0 dB).
f
=
1.02 kHz
Loopback mode. Input
Transmit output dynamic
range (TXOT)
=
RL
75 dBm to 3 dBm.
attenuator set to code 111111 (0 dBI.
f
=
1.02 kHz
Input
=
= - 75 dBm to
3 dBm.
Transmit output dynamic
RL
range (TXFB)
amplifier set for unity gain, Transmit
Supervision output
dynamic range (SUPOT)
Frequency
response of
supervision
circuits
Ci
= -
5 kO to ANLG GND. Transmit channel
Input
5 kO to ANLG GND. Transmit input
attenuator set to 0 dB. f = 1.02 kHz
Input to SUP+ = 75 mV to 750 mV Irmsl.
SUP- at ANLG GND.
RL
=
100 kO to ANLG GND. 1
=
5 Hz
MIN
TVPt
-74
-75
to
to
3
3.1
-74
-75
to
to
3
3.1
-74
-75
to
to
3
3.1
-74
-75
to
to
3
3.1
to
to
6
6.2
Input to SUP+
fclock
= 2.048
=
-10 dBmO~.
....
"S
...
II)
dBm
(J
C3
II)
dBm
c
o
",t:;
&V
dBm
-30
-40
MHz
(J
"2
:l
E
E
dB
o(J
greater
Data
14
CE high
7.5
VDD - VSS switched from 10 V to 6 V
100
200
1
TXOT. BALOT.
TXFB
I-
ns
MO
10
=
50
-200 pA
SUPOT
RXO+. RXO-
CD
Gi
pF
100
Digital outputs
impedance
dBm
8
15 Hz to 65
capacitance All others
Output
dBm
-45
SUP- at ANLG GND.
66 Hz or
td(POR) Delay time to power-on reset
Input impedance.
Zi
(any input or 110)
Zo
UNIT
-14 -13.8
Otol0Hz
16.6 Hz
MAX
1
Voice mode. 10
=
-10 pA
1
3
0
kO
0
tAli typical values are at VDD = 5 V. VSS = -5 V. TA = 25°C.
~O dBmO is the zero-reference point of the channel under test. This corresponds to a voltage 01 1520 mV (rms) on inputs and outputs.
with attenuators set for 0 dB.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-147
TCM4204A, TCM4205A, TCM4207A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
ac characteristics - half channel t over recommended ranges of supply voltage and operating freeair temperature
PARAMETER
TEST CONOITIONS
50 Hz to 200 Hz
Frequency response
RL - 900 II to ANLG GND,
VI
= 0 dBmO,
= 1.020 kHz
-0.1
0.1
Ref
-0.05
0.05
RL
= 900 II to
-0.05
0.05
-0.1
0.1
-20, -30 dBmO
=
f
-40, -50 dBmO
Idle channel noise
= -
30 dBmO
-I
Total distortion
CD
(')
o
Total harmonic distortion
Vi - 3 dBmO, f - 1.020 kHz
Phase Delay time
1 kHz
c
Absolute delay time
::::I
rr
C»
....
0'
::::I
I RL
30 dBmO to - 40 dBmO
- 40 dBmO to - 50 dBmO
If
I
=
=
B
Departure from
linear phase
-45
1.020 kHz
Supply·voltage
sensitivity
U)
(see Note 4)
dB
dBrncO
dB
dB
20
1.B kHz
20
500 Hz to SOO Hz
30
SOO Hz to 1 kHz
20
1 kHz to 2.S kHz
10
1 kHz to 1.3 kHz
±0.05
1.3 kHz to 2.3 kHz
±0.05
+0.04
4 kHz to 50 kHz
~s
rad
-0.05
±0.1
VDD changing 200 mV POp
50 Hz to 4 kHz
~s
30
±0.1
2.7 kHz to 3.1 kHz
;:::;.'
dB
-40
-55
2.3 kHz to 2.7 kHz
::;'
UNIT
-50
900 II to ANLG GND
600 Hz to 1 kHz
C')
c
ANLG GND,
1.020 kHz
2.6 kHz to 2.8 kHz
U)
(')
Vi
Vi -
(carrier)
=
RL - 900 II to ANLG GND
Vi - 0 dBmO to
3
3
0.2
200 Hz to 300 Hz
Vi
CD
MAX
300 Hz to 4 kHz
Vi - 0, -10,
Level (gain) tracking
MIN
-0.2
-40
VSS changing 200 mV p.p
-40
VDD changing 200 mV Pop
-25
VSS changing 200 mV p.p
-25
dB
tTransmit channel is tested with input amplifier set for unity gain. Receive and transmit attenuators Bre set to 0 dB.
NOTE 4: The receiver supply-voltage sensitivity is the differential RXO + -to-RXO - noise referenced to supply noise. It is assumed that
the feed transformer will reject common-mode RXO + IRXO - noise and, therefore. the common-mode supply-voltage sensitivity
is not specified.
2-148
TEXAS •
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS. TEXAS 75265
TCM4204A. TCM4205A. TCM4207 A
SUBSCRIBER-LINE-CONTROL CIRCUITS
system characteristics over recommended ranges of supply voltage and operating free-air temperature
(see Figures 9 and 10)
PARAMETER
FREQUENCY RANGE
TEST CONOITIONS
MIN
MAX
200 Hz to 500 Hz
Return loss
500 Hz to 1 kHz
Isee Note 5)
1 kHz to 2.5 kHz
ZL
~
900
n +
2.2
-35
~F
-40
2.5 kHz to 3.4 kHz
500 Hz to 1 kHz
Isee Note 5)
1 kHz to 2.5 kHz
- 25
ZL
~.900
n +
2.2
-35
~F
-40
2.5 kHz to 3.4 kH
Isee Note 5)
dB
-35
60 Hz to 500 Hz
Longitudinal balance
dB
-35
200 Hz to 500 Hz
Transhyhrid loss
UNIT
-25
I/)
-66
500 Hz to 1 kHz
-50
2-wire to 4-wire
1 kHz to 4 kHz
200 Hz to 4 kHz
-58
"~
::::J
dB
...o
-60
4-wire to 2-wire
U
NOTE 5:
The return loss, the transhybrid loss, and the longitudinal balance are functions of external components, primarily the battery
feed transformer or its functional replacement. The SLCC will not materially change the return loss or the longitudinal balance.
The imbalance in trans hybrid loss caused by phase or gain errors in the SLCC will be less than those listed.
I/)
I:
o
",tj
SLCC - microprocessor timing requirements over recommended ranges of supply voltage and operating
free-air temperature
PARAMETER
ta
Access time from eEL
teICLK)
t,. tf
Clock period for CLKM
tv
Output data valid after CLKM
twICLKH)
MIN
MAX
140
2000
Rise and fall times for CLKM
E
ns
E
o
ns
5
ns
80
ns
oQ)
Pulse duration CLKM high
550
ns
Q;
300
ns
I-
twICLKL)
Pulse duration CLKM low
Internal read/write enable after CLKM
250
ns
tenIR/W)
Enable time, Input after R/wt
250
ns
tdislCE)
Disable time, output after eEt
180
ns
tsu1
Setup time, CLKMI before R/Wt
tsu2
tsu3
50
ns
Setup time, data before CLKMI Isee Note 6)
180
ns
Setup time, CEI before CLKMt Isee Notes 7 and 8)
180
Duty cycle, CLKM Isee Note 9)
6.
7.
8.
9.
I:
::::J
UNIT
tenlCLK)
NOTES:
CO
"~
10
The R/W input must be a logic low.
If the user is not interested in reading bit 0, tsu3 can be a minimum of 30 ns.
The R/W input must be a logiC high.
As long as the minimum high and low pulse durations are observed, the CLKM duty cycle is twICLKH)/[twICLKL)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
ns
90
%
+ tw ICLKH)].
2-149
TCM4204A, TCM4205A, TCM4207 A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
supervision timing characteristics over recommended ranges of operating conditions (see Figure 4)
normal loop supervision timing characteristics. fCLKS - 2.048 MHz
Typt
MAX
UNIT
tpHL
Propagation time high-to-Iow, hook status bit
Standby mode, SUP- = GND,
75
100
ms
tpLH
Propagation time low-to-high, hook status bit
SUP + changing from
60
100
ms
tpHL - tPLH
tnr
Differential propagation time
o V to
±20
ms
PARAMETER
TEST CONDITIONS
MIN
200 mV or from
200 mV to 0 V
Maximum noise rejection duration time
10
ms
ground key/ground start supervision timing characteristics (TCM4205A only)
PARAMETER
~
CD
CD
n
o
3
3
150
ms
tpLH
Propagation time low-to-high, ground start bit
Differential propagation time
150
ms
tpHL
tPLH
PARAMETER
Ring trip detect time
I»
ms
ms
I
TEST CONDITIONS
I
Standby mode, SUP- = GND,
SUP + changing from 0 V to 200 mV
MIN
Typt
MAX
55
100
UNIT
I
microprocessor internal polling timing requirement
::::I
PARAMETER
(I)
MIN
Microprocessor polling interval
(')
:;'
10
ring trip detection timing characteristic
(;'
n
c
::;
±20
Maximum noise rejection duration time
tnr
::::I
0'
UNIT
Propagation time high-to-Iow, ground start bit
c I
..
MAX
MIN
tpHL
MAX
100
tAli typical values are at VDD = 5 V, VSS = - 5 V, T A = 25 ·C.
PRINCIPLES OF OPERATION
(I)
mode control
The SLee can be forced into one of four modes by the microprocessor (see Figure 1 for mode states and
Table 1 for the recommended mode control sequence). The mode control functions are as follows:
Voice operation - All circuits powered up. PWRU output pin is set high.
Power down - Audio circuits are powered down. supervisory circuits are powered up, and the PWRU
output pin is set low.
Loopback - Normal balance circuit is interrupted allowing the transmit output to follow the receive
input. All other circuits are powered up.
Standby - Audio circuits are powered down. supervisory circuits are powered uP. and the PWRU output
pin is set high. The internal power-on reset (PaR) circuit sets the SLee to this mode at power up.
TABLE 1. RECOMMENDED MODE CONTROL SEQUENCE
BITS
A B
2-150
FUNCTION
L H
Power Down
L L
Standby
H L
Voice
H H
Loopback
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM4204A, TCM4205A, TCM4207 A
SUBSCRIBER-LiNE-CONTROL CIRCUITS
PRINCIPLES OF OPERATION
fI)
~
·S
...u
(3
fI)
C
o
'+:
ca
u
'2
FIGURE 1. MODE CONTROL STATE DIAGRAM
~
internal power-down states
The internal power down states are the standby mode and the power-down mode. The only difference
between the two states is the level of the PWRU output. In the standby mode, PWRU is set high and in
the power-down mode, PWRU is set low. The PWRU output can be used to control an external dc-to-dc
converter for floating constant-current-feed applications or to drive a status indicator.
E
E
o
u
Q)
...
Gi
standby mode
1. All analog functions except supervision and all logic functions except microprocessor interface and
registers are powered down.
2. PWRU output is set high.
power-down mode
1. All analog functions except supervision and all logic functions except microprocessor interface and
registers are powered down.
2. PWRU output is set low.
TEXAS " ,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-151
TCM4204A, TCM4205A, TCM4207 A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
PRINCIPLES OF OPERATION
digital control and microprocessor interface
The data storage unit contains 24 bits of R/W (Read/Write) and RO (Read Only) data. The R/W data is
used to control attenuation, balance, relay selection, and mode of operation. The RO data provides
supervisory status information.
The microprocessor uses the CE, DATA 1/0, RIW, and CLKM input lines to control and time access to
the data. When CE is toggled from high to low, the serial data sequence is started at bit 0 and the pointer
may be sequenced through the 24 data bits. The pointer is advanced by low-to-high transitions of CLKM.
In addition, CE enables the read and write functions. When CE is high, the DATA I/O pin is in the highimpedance state, and the CLKM and RIW inputs are ignored.
-I
CD
R/W determines whether DATA is an input or an output. When R/W is high, DATA 1/0 is an output and
can be read. When R/W is low, DATA I/O is an input and can be written.
o
3
3
c
CLKM has another important function. CLKM must be high for a minimum time defined by ten(CLK) to
write data to the DATA I/O pin. It is during this time that all the internal gates get set up to receive the
data latched in by the falling edge of CLKM.
CD
(')
:::J
n'
I»
microprocessor timing for read operation (see Figure 2)
...0'
During the read operation, CE goes low and sets the data storage unit (DSU) pointer to bit O. The setup
time (ta) must pass before bit 0 appears on the DATA I/O line. To advance the DSU pointer, a positive
transition of CLKM is needed. CLKM can be raised after the appropriate setup time (tsu3). The pointer
is then advanced to bit 1. Following this positive transition of CLKM, an internal setup time, ten(CLK),
must pass before the correct data from bit 1 appears on DATA I/O. Between this time and the next positive
transition of CLKM, the data at bit 1 can be read. The next transition of CLKM advances the pointer to
bit 2. Following the internal setup time, the data at bit 2 appears on the DATA I/O line. The time available
for reading bit 2 is determined, in this case, by CE also going high. The DATA I/O line now goes back
to the hig':! impedance state. The time required for this to occur is given by tdis(CE).
:::J
(I)
n
::;'
(')
C
;:::;'
(I)
microprocessor timing for write operation (see Figure 3)
In this case, we have to assume CE has been low for a long time if we are to look at the N clock edge
for CLKM. RIW starts out high and, after ten(CLK) elapses, goes low. DATA I/O starts out as an output,
while R/W is high, which is connected to bit N-1. When CLKM goes high, the pointer is advanced to bit N.
RtW can go low after ten(CLK). DATA I/O is converted to an input after ten(R/W. NOTE: In addition to
RtW being low, CLKM must be high during the time DATA I/O is changing from output to input. Following
this time, the data on DATA I/O is valid. CLKM can go low and clock the data into bit N after the minimum
setup time, (tsu2). The data just clocked in to bit N can be read if R/W is now raised. RtW can be raised
after (ts u 1). Following data valid time (tv), the data can be read at bit N.
2-152
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS, TEXAS 75265
TCM4204A, TCM4205A, TCM4207A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
PRINCIPLES OF OPERATION
TABLE 2. REGISTER MAP
BIT NUMBER
FUNCTION
0
On/Off Hook
DATA TYPE
RO
POWER ON RESET
X
1
Ground Start
RO
X
H
2
Power Fault
3
Ring Relay
R/W
R/W
4
AUX1 Relay
RiW
L
5
AUX2 Relay
R/W
L
L
6
AUX3 Relay
RiW
L
7
Mode Control A
RiW
L
8
Mode Control B
RiW
L
9
Rx Atten Bit 5 (MSB)
R/W
L
10
Rx Atten Bit 4
R/W
L
11
Rx Atten Bit 3
R/W
L
12
Rx Atten Bit 2
R/W
L
13
Rx Atten Bit 1
R/W
L
14
Rx Atten Bit 0 (LSB)
R/W
L
15
Tx Atten Bit 5 (MSB)
16
Tx Atten Bit 4
R/W
R/W
L
L
17
18
19
20
21
22
23
Tx Atten Bit 3
R/W
L
Tx Atten Bit 2
R/W
L
Tx Atten Bit 1
R/W
L
Tx Atten Bit 0 (LSB)
R/W
L
Balance Select A
R/W
L
Balance Select B
R/W
L
Supervisor Reset
R/W
L
U)
C
o
.,t::
CO
(,)
·2
~
E
E
o(,)
CD
"i
attenuator characteristics
I-
Both attenuators have identical characteristics but are separately controlled. The characteristics of the
attenuators are as follows:
1. 63 steps (reference Table 3)
2. Receiver range of 4.8 dB gain to -7.8 dB loss (differential)
3. Transmitter range of 0 dB to - 12.6 dB loss
4. Step size of 0.2 dB typical
5. The accuracy of any attenuator setting is ± 1 step size.
lead options
The TCM4204A (24-pin constant-voltage option) is designed to provide the minimum set of features required
by the largest proportion of world-wide needs. The TCM4204A has the following:
1. Three separate external balance networks
2. Two relay outputs (TTL); one output dedicated to ring and one auxiliary output.
The TCM4205A (28-pin ground-start option) has the following:
1. Three separate external balance networks
2. Four relay outputs (TTL); one dedicated to ring and three auxiliary outputs
3. An input to set the ground-start trip level.
The TCM4207 A (24-pin flux-canceling option) has the following:
1. Two separate external balance networks
2. Two relay outputs (TTL); one output dedicated to ring and one auxiliary output
3. One filtered analog output (16.6 Hz at ClKS = 2.048 MHz) that is an analog representation of the
dc voltage « 10 Hz) between the supervisory inputs.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-153
TCM4204A, TCM4205A, TCM4207 A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
TABLE 3. ATTENUATOR CODES
A TTENUATOR CODE
DECIMAL
BINARY
0
000000
1
000001
2
000010
3
000011
4
000100
5
000101
6
000110
7
000111
8
001000
001001
10
001010
11
001011
12
001100
13
001101
14
001110
15
001111
16
010000
17
010001
18
010010
1.
010011
20
010100
21
010101
22
010110
23
010111
24
011000
25
011001
26
011010
27
011011
28
011100
2.
011101
30
011110
31
011111
32
100000
33
100001
34
100010
35
100011
36
lQ0100
37
100101
38
100110
39
100111
40
101000
41
101001
42
101010
43
101011
44
101100
101101
45
46
101110
47
101111
48
110000
4.
110001
50
110010
51
110011
52
110100
53
110101
54
110110
55
110111
56
111000
57
111001
58
111010
59
111011
60
111100
61
111101
62
111110
63
111111
•
-I
CD
CD
n
o
3
3
c
j
5'
...
I»
0'
j
(/)
(")
...
n
c
;::;.'
(/)
tTransmit input amplifier set for unity gain.
2·154
TRANSMIT t
CHANNEL
RECEIVE
CHANNEL*
-12.6 dB
-7.B dB
-12.4 dB
-7.6 dB
-12.2d8
-7.4 dB
-12.0 dB
-7.2 dB
-11.8 dB
-11.6 dB
-7,0 dB
-11.4 dB
-6.8 dB
-6.6 dB
-11.2 dB
-11.0 dB
-6.4 dB
- 6.2 dB
-10.B dB
-10.6 dB
-6.0 dB
- 5.8 dB
-10.4 dB
- 5.6 dB
-10.2 dB
-10.0 dB
- 9.8 dB
-5.4 dB
- 5.2 dB
-9.6 dB
-4.8 dB
-9.4 dB
-4.6 dB
-5.0 dB
-9.2 dB
-9.0 dB
-4.4 dB
-8.B dB
-4.0 dB
-8.6 dB
-8.4 dB
-8.2 dB
-3.B dB
-3.6 dB
-4.2 dB
-8.0 dB
-3.4 dB
-3.2 dB
-7.B dB
-7.6 dB
-3.0 dB
-2.B dB
-7.4 dB
~2.S
dB
-7.2 dB
~ 7.0 dB
~2.4
dB
~S.S
-2.0 dB
-l.S dB
dS
-6.6 dB
-6.4 dB
-S.2 dB
-6.0 dB
- 5.8 dB
- 5.6 dB
- 5.4 dB
-5.2 dB
- 5.0 dB
-4.8 dB
~
2.2 dB
-1.6 dB
-1.4 dB
-1.2 dB
-1.0 dB
-O.S dB
-0.6 dB
-0.4 dB
-0.2 dB
0.0 dB
-4.6 dB
-4.4 dB
-4.2 dB
+0.2 dB
+0.4 dB
-4.0 dB
- 3.8 dB
+0.8 dB
+ 1.0 dB
-3.6 dB
-3.4 dB
- 3.2 dB
+1.2 dB
+ 1.4 dB
+ 1.6 dB
-3.0 dB
-2.8 dB
+1.8 dB
+2.0 dB
-2.6 dB
- 2.4 dB
+2.2 dB
+0.6 dB
+ 2.4 dB
- 2.2 dB
+2.6 dB
-2.0 dB
+2.8 dB
-1.8 dB
-1.6 dB
-1.4 dB
+3.0 dB
+3.2 dB
+ 3.4 dB
-1.2 dB
-1.0 dB
-0.8 dB
+3.6 dB
+3.8 dB
+4.0 dB
-0.6 dB
+4.2 dB
-0.4 dB
-0.2 dB
0.0 dB
+4.4 dB
+4.6 dB
+4.8 dB
~Output measured differentially across RXO + and RXO -.
~
TEXAS
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM4204A, TCM4205A, TCM4207 A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
PARAMETER MEASUREMENT INFORMATION
(SEE Nc;TE 10)
I4-- tsu3
.14
r
7~
see
CLKM
Note
I
1
H
R/W
~
tc{CLK)
\
"
.14
I+--tw{CLKH)
ta--l+---+l
tw{CLKL)---.,
1
I
i+-ten{CLK)-+i
I
~I -~--------)@XI
HIGHZ
DATA
{SEE NOTE 101
BIT 0
•
I I
I
I
I ----,I
I
BIT 1
I
, -------- I
I
I
I
----'-r ...
~tdis{CE)
l
BIT 2
'-v--I
V
'-.r-'
READ BIT 0
READ BIT 1
READ BIT 2
FIGURE 2. SLCC -
HIGHZ
(SEE NOTE
10)
CLKM
:-;+1
CI)
t:
o
.';:;
ca
CLOCK EDGE
~--------------------~~\.________________________~J
I
I
I
I
R/W
II
II
E
E
I+- t sul
1\"'--------__
Q)
I-
.1.1.
I
J_
1
1
I
14
I
.1
I
_________
___
~:
1
~
APPLY AND HOLD DATA
INPUT TO SLCC
~!~
,
I
\1
____
_
I
I+--tv--+j
tsu2-k---+j
FIGURE 3. SLCC -
t:
:;:,
(,)
G)
DATA-Q~~B:~)--8-----{
ten{R/W)
.2
o
:,'1- - - - - - - - - - - -
~
l+-ten{CLK)-+t
_
~
CI)
U
MICROPROCESSOR TIMING REQUIREMENTS FOR READ OPERATION
~N CLOCK EDGE
...
·S
(,)
L ________________________________________________________________________
H
CE
NOTES:
I,
\\.-4------
~
1
v
1/
READ DATA BACK THAT WAS
JUST WRITTEN
MICROPROCESSOR TIMING REQUIREMENTS FOR WRITE OPERATION
7. If the user is not interested in reading bit 0, tsu3 can be a minimum of 30 ns.
10. The DATA pin is an input. an output. or in a high·impedance state. When CE is low. the DATA pin will be either an input
or an output depending upon the condition of R/W. When R/W is high and CE is low. the DATA pin is an output that a
microprocessor can poll. When R/W is low and CE is low, the DATA pin is an input. Dashed lines on the DATA signal indicate
that the data on the DATA pin is coming from the SLCC. Solid lines on the DATA signal indicate that the data on the DATA
pin is coming from the system. Each time the CE input goes low, the bit pointer is reset to bit zero. All rise and fall times
are assumed to be 20 ns or less; therefore, timing requirements are shown referenced to 50% of the rising or falling slope
of the waveform. A write operation can only be performed when CLKM is high. When CLKM is low. only a read operation
can be performed.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-155
TCM4204A, TCM4205A,TCM4207 A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
PARAMETER MEASUREMENT INFORMATION
OV
~tnr
----.....:
TIP SENSE
VOLTAGE (DC PORTION)
:
OFF-HOOK BIT
OFF-HOOK DETECTION
-I
(1)
CD
TIP SENSE
VOLTAGE (DC PORTION}
n
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3
3
c
OV\
: '-_ _ _ _ _ _ _ _ _ _ _ _ _ __
~trt
j1 r - - - - - - - -
OFF-HOOK BIT
_ _--J
~
RING TRIP DETECTION
rf
D)
FIGURE 4. SUPERVISION TIMING WAVEFORMS
~
0"
~
en
TYPICAL APPLICATION DATA
o
::;"
n
c
;::;
en
CALLING PARTY
OFF-HOOK BIT
j--1 t'-J
--1
'1
••
t
U
rI
•I
2
~S
LJ
•
I-
3
•
·1-5 6 ·1
.,
1
CALLED PARTY
RING RELAY BIT
1
I
_ _-----'rl~1_
I
CALLED PARTY
OFF-HOOK BIT
----------------------------41) :
IL--.----
i H_4~~
I
7
1
2
3
4
5
6
OFF-HOOK
VOICE MODE SET UP BY MICROPROCESSOR
DIAL PULSE COLLECTION
VOICE (CONVERSATION)
ON-HOOK
MICROPROCESSOR DETECTS ON-HOOK BY READING
BIT "0" AND SET SYSTEM TO STANDBY MODE
7
8
9
89
5
MICROPROCESSOR ENABLES BIT "3" RING RELAY ON
MICROPROCESSOR DETECTS OFF-HOOK
BY READING BIT "0"
MICROPROCESSOR DISABLES BIT "3" AND
SETS THE SLCC TO VOICE MODE
FIGURE 5. MICROPROCESSOR INTERNAL POLLING (TYPICAL SEQUENCEI
2-156
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM4204A. TCM4205A. TCM4207 A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
TYPICAL APPLICATION DATA (see Notes 11 and 121
R
VDD
RXIN
U)
RXO+ DGTL GND
~
..
'S
ZT/2
ANLG GND
TEST
RELAY
()
RXO-
C3
CLKS
U)
DATA
0
"+0
C
CO
REWZ
TXI+
T
()
"2
CE
:::I
CLKM
RELAY
ZT'
R/9.6
R/9.6
Typically, R
DIGITAL
GROUND
~
600 kll
*
R/29.4
CD
...
G)
BAL1
BAL2
SUP+
LEGEND
()
BALD
SUP-
ANALOG
GROUND
E
E
0
BALOT
+5V
ZB
R/27.1
.".
FIGURE 6. TCM4204A. TCM4205A SLCC STANDARD SUBSCRIBER LINE
NOTES: 11. All resistors should have tolerances of ± 1 % or better.
12. If the battery-feed transformer is center tapped on the SLCC side, it is recommended that the center tap be left disconnected.
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-157
TCM4204A, TCM4205A, TCM4207A
SUBSCRIBER:LlNE·CONTROL CIRCUITS
TYPICAL APPLICATION DATA (see Notes 11 and 12)
100kll
-I
CD
CD
(')
o
3
-48 V
3
c
~
c;'
VDD
RXIN
RXO+ DGTL GND
...0'
C»
ANLG GND
RXO-
TEST
RELAY
~
tn
TXFB
CLKS
(')
a·c
TXI-
DATA
REWZ
::+
TXI+
T
tn
CE
CLKM
RING
RELAY
BAlOT
+5V
ZT'
R/9.6
BALD
R/9.6
BAll
SUP-
~
ANALOG
GROUND
~
SUP+
OIGITAL
GROUND
*
Rl29.4
ZB
R/27.1
-=
Typically, R = 600 kll
FIGURE 7. TCM4207A SLCC STANDARD SUBSCRIBER LINE
NOTES: 11. All r •• istor. should have tol.rances of ± 1 % or better.
12. If the battery-feed transformer is center tapped on the SLCC side, it is recommended that the center tap be left disconnected.
2-158
TEXAS .".
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM4204A. TCM4205A, TCM4207A
SUBSCRIBER·LlNE·CONTROL CIRCUITS
TYPICAL APPLICATION DATA (see Notes 11 and 121
RXO+
+
ANALOG
SIGNAL
PROCESSING
(ATTENUATORS, HYBRID)
..
fI)
ZB
.
'S(J
C3
fI)
c
TXOT
o
TX
FILTER
INPUT
RING
62.& kll
600kll
as
(J
'c
~
+5V
~
200ll
8V
'+0
E
SLCC
SUPERVISION
CIRCUIT
62.& kll
E
o()
600 kll
CD
G)
SUP+
~
::::: ~2.2"F
sup600 kll
600kll
200 II
TIP
~
22.1
kll
20.4 kll
':"
400ll
"="
FIGURE 8, INPUT/OUTPUT OFFSETS
NOTES: 11. All resistors should have tolerances of ± 1 % or better.
12. If the battery·feed transformer is center tapped on the SLCC side, it is recommended that the center tap be left disconnected.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-159
TCM4204A, TCM4205A, TCM4207A
SUBSCRIBER-LiNE-CONTROL CIRCUITS
RING
450n
ZT/2
900 n
SLCC
2.21lF
TIP
450n
ZB
VARYING
FREQUENCY
-f
CD
Ci'
(')
FIGURE 9. STRUCTURAL THL TEST CIRCUIT
o
3
3
c
5-
2.21lF
:::s
....
soon
0)
o·
:::s
TIP
til
(")
~.
RING
30Vrms
60Hz
2.21lF
c
;::;:
til
FIGURE 10. LONGITUDINAL REJECTION TEST CIRCUIT
-48V
lL
goon
SIGNAL LEVEL AT 900 n
6dBmo
OdBmo
-10dBmo
-20 dBmo
-30dBmo
-40dBmo
-60dBmo
-80dBmo
ACROSS 900 n
1.8 Vrms
0.95 Vrms
0.30 Vrms
95 mVrms
30 mVrms
9.5 mVrms
950llVrms
951lVrms
DIFFERENTIAL RMS
RXO+, RXO5.34 Vrms
2.68 Vrms
0.85 Vrms
0.27 Vrms
85 mVrms
27mVrms
2.7 mVrms
270llVrms
FIGURE 11. SIGNAL LEVELS. 2W SIDE
2-160
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
SINGLE ENDED
RXO+,RXO+3.78 Vpp
+1.89 Vpp
+0.60 Vpp
+189 mVpp
+60 mVpp
+18.9 mVpp
+1.89 mVpp
+1891'Vpp
TCM5087
TONE ENCODER
02650. NOVEMBER 1982-REVISEO OCTOBER 1984
•
Low-Cost TV Color-Burst Crystal Sine-Wave
Input Produces Highly Accurate and Stable
Tones
•
Device Powered Directly by Telephone or
Small Batteries
•
Keyboard or Electronic Input Capability
•
Dual-Tone and Single-Tone Capability
•
Minimal Standby Power Requirement
•
Total Harmonic Distortion Meets EIA
Standard RS-470
TONE OUT
SINGLE-TONE ENABLE
ROW 1
ROW 2
ROW 3
ROW 4
MUTE OUT
COL 4
Voo
XMITTER SW
COL 1
COL 2
COL 3
VSS
OSCIN
OSC OUT
...
u
...
o
(I)
·S
•
PEP3 Processing Available
•
Wide Supply-Voltage Range
•
Minimal Parts Required
•
Single-Tone Production Can be Inhibited
•
Auxiliary Switching Outputs: One Bipolar
Transistor and One CMOS Gate
•
N DUAL-IN-LiNE PACKAGE
(TOP VIEW)
(I)
C
o
.~
ca
u
'2
Designed to be Interchangeable with Mostek
MK5087
;:,
E
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
E
o
u
II)
CD
description
I-
The TCM5087 tone encoder is a CMOS integrated circuit designed specifically to generate the dial tones
used in dual-tone talephone dialing systems. It requires a sine-wave input normally supplied by a low-cost
TV color-burst crystal at 3.579545 MHz to generate eight different audio sinusoidal frequencies. With
this input the encoder generates dial tones that are very low in total harmonic distortion and comply with
standard Dual-Tone Multi-Frequency (DTMF) specifications without any need for frequency adjustment.
When generating a dual-tone signal, the encoder generates one column tone and one row tone and adds
them for its output. The table below presents the frequencies produced by the tone encoder with the
3.579545-MHz TV-crystal signal input. Any deviation in this frequency will be reflected in the frequency
output. The tolerance of the crystal is normally 0.02%.
DTMF
STANDARD
TONE
Row 1
Row 2
Row 3
Row 4
Column
Column
Column
Column
1
2
3
4
ENCODER
OUTPUT·
(Hz)
(Hz)
697
770
852
941
1209
1336
1477
1633
701.3
771.4
857.2
935.1
1215.9
1331.7
1471.9
1645
ERROR
FROM STANDARD·
(%)
+0.62
+0.19
+0.61
-0.63
+0.57
-0.32
-0.35
+0.73
'Usin9 an input Signal from a 3.579545-MHz crystal.
PRODUCTIDI DATA do...._ ooota.. i.fermati_.
_
II 01 pU/IcIti.. dlle. ProdUCII .......... ta
opociJitatia.. pIr In limo 01 THH IlIIIruOllntl
~war=i =:;":1' ~:::~~~.at
Copyright @ 1982, Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TeXAS 75265
2-161
TCM5087
TONE ENCODER
operation
keyboard and electronic inputs
The specific tone or tones generated are determined by inputs designated ROW 1 through ROW 4 and
COLUMN 1 through COLUMN 4. The inputs are normally received from a 2-of-8 OTMF (OPST) keyboard,
a Class A (SPST) keyboard, or an electronic circuit. Unlike dynamic or scanned inputs, the static inputs
of the TCM5087 do not generate noise. See function table for input and output description.
CLASS A KEYBOARD (SPST}
K~~~OLUMN
~
COLUMN
-I
+----A
---.
2-G-Cf.ll
DTMF
LEAVE
OPEN
ROW
CD
CD
n
o
3
3
c
This input inhibits the generation of single tones when taken low. All other chip functions remain unchanged.
If the input is high or left open, single-tone operation is enabled.
transmitter switch output
This output is at high impedance when one or more of the column inputs are active and is high when all
column inputs are inactive. The output is the emitter of a bipolar transistor whose collector is at VOO.
c;'
....
. L - - ROW
single-teme enable Input
:s
I»
S'
~
mute output
:s
(I)
(")
The mute output is high when one or more column inputs are active and is low when all column inputs
are inactive.
:::;' f~nctlonal block diagram
n
c
;::;:
(I)
~IN~(~1~
________________________
~~>-~~
________________________
VOO,-(l.!'L).........~~.VDD
CTRDIVK
ROW ,_(;:;'4:!-~f-+........------------------------+-
SV
620
5 V
330
Operating free-air temperature, T A
I--I
TEST CONOITIONS
Column or row input resistance
V
V
11
11
70
Single-tone-enable input resistance to VOO
2SoC
Mute output
VOO
output
VOO - 10 V,
VOL
Low-level output voltage, mute output
o
iOL
Off-state current transmitter switch output
IOOstby
Standby supply current with outputs unloaded
IOOop
=
Transmitter switch
0"
....
m
TA
VOO - 3 V,
VOO - 10 V,
VOH
High-level output voltage
MIN
TYP
MAX
10
c
::::J
5"
~r
c
::;:
V
11
-30
PARAMETER
o
3
3
o
UNIT
°C
electrical characteristics over operating free-air temperature range (unless otherwise noted)
n
::::J
MAX
Operating current
=
3.S V,
kll
20
10H - 0.2 rnA,
IOH - O.S rnA
10H
=
-1S rnA
10H -
- 40 rnA
VOO - 3 V,
10L -
VOO - 10 V,
VOO - 10V,
10L -
-0.2 rnA
O.S rnA
UNIT
100
kll
2
9
1.S
V
2.S
8
O.S
O.S
10
Vo - OV
VOO - 3.S V
0.25
100
VOO = 10 V
VOO - 3.5 V,
0.5
200
See Note 3
1
2
VOO -10V,
See Note 3
S
10
V
p.A
~A
rnA
o
operating characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted)
PARAMETER
Output rms voltage
TEST CONOITIONSt
I
I
Row tone
Column tone
RL
TA
= 330 11 to
= 25°C
Preemphasis (column tone to row tone)
Oual-tone output distortion (see Note 4)
1 kll,
MIN
TYP
MAX
317
400
SOO
396
SOO
630
1
2
3
-20
d8
-80
dBm
VOO '" 4 V
Quiescent tone-output power
Tone-output rise time (see Note 5)
3
5
UNIT
mV
dB
ms
tUnless otherwise noted, test conditions are: RL = 62011 lor VOO s S V or RL = 33011 lor VOO > S V. Crystal parameters are the
lollowing: I = 3.579545 MHz ±0.02%, RS < 10011, CL = 18 pF, CM = 0.02 pF, CH = S pF, LM = 96 mHo
NOTES: 3. Operating current is measured with all outputs unloaded, one row input connected to one column input, and normal oscillator
input.
4. Distortion is expressed as the ratio of total out-of-band power relative to the total fundamental power for the dual tone.
5. This is the time required for output to change from its quiescent value to 90% of its final rms value.
2-164
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM5087
TONE ENCODER
output waveforms
Typical row and column stairstep approximations of sinusoidal outputs are shown in Figures 1 and 2. The
row and column outputs are added together resulting in a typical dual-tone waveform as shown in Figure 3.
Spectral analysis of this dual-tone waveform shows that all harmonic and intermodulation distortions are
typically 30 dB below the strongest column-tone fundamental.
>
>
.~
:g
>
:!i!
~
"'
0
III
til
III
c:i
0
...
>
>
'S
...
(.)
U
0.2 ms/div
0.2 ms/div
0.2 ms/div
FIGURE 1
FIGURE 2
FIGURE 3
til
C
o
'+=I
CO
distortion considerations
,2
The following formula is used to calculate the total harmonic distortion of a single row or a single column:
c
::::I
THO = (
JV2f2
E
E
o(.)
+ V3f 2 + V4f 2 + V5f 2 + ... + vnf2)
x 100%
V1f
Q)
where V2f is the second harmonic of the fundamental frequency V1f waveform and so on. The dual-tone
total harmonic distortion is:
THO
=
(JV2R2
Q)
....
+ V3R 2 + ... + V nR2 + V2C 2 + ... V nC 2 ± VIM0 2 ) x 100%
JVFR2
+ VFC 2
where VFR and VFC are the row and column fundamental frequency waveforms, and V2R and V2C, etc.,
are the corresponding harmonics.
The total intermodulation distortion is:
A relatively simple method of distortion measurement uses a spectrum analyzer to relate the harmonics
to the fundamental frequency waveform. The tone encoder spectrum indicates the harmonics and
intermodulation distortion at least 30 dB down relative to the column tone.
Another method for distortion measurement of the dual-tone waveform is to compare the total power in
the fundamental frequencies with the total power in the various harmonics plus intermodulation on a signal
analyzer. The encoders provide an output distortion of - 20 dB maximum when operated between 3.5 volts
and 10 volts. If operated between 3 volts and 3.5 volts, some clipping occurs at the output causing the
distortion to exceed the - 20 dB level.
TEXAS
-1!1
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-165
TCM5087
TONE ENCODER
TYPICAL APPLICATIONS DATA
~
HKSW1
T
1
COLUMN l1li
••
~ ROW
CLASS A KEYBOARO (SPST)
,
--T.
r- L1------F'\'L
__~=::;-----
;-
A
(')
o
3
3c
R
~--+--1~---<'----~---<~~--~VDD
10
kll
K
(15)
C
D l
-.- ~
I
I
:
OSC (7)
INPUT
o
XTAL
~~-';'!(It
r+
o·:s
OSC (8)
OUTPUT
XTAL PARAMETERS:
(I)
MIC.
~r
TYPICAL VALUES
B
c
I
L. _______ ..1I
(I)
SIDETONE·BALANCE
NETWORK
~
C1 = 0.001 p.F
RL = 82 n (or 10 kn if optional tranistor is used)
CM=O.02pF
LM-96mH
CH =5pF
f = 3.579545 MHz
R'L = 150 n optional
D1, D2, D3,D4= 1N4004
D5 = 1N4743 (13 volt)
FIGURE 4. TYPICAL APPLICATION USING HYBRID COIL SIDETONE-BALANCE NETWORK,
ELECTRONIC SWITCHING, AND LOW-COST (CLASS AI KEYBOARD
2-166
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
I
---i
~~:ELE. COL 3 (9)
I
DISABLE COL 4 ________ ...1
..--_ _-'(:::2~) TRANSMITTER
II)
o
9
0
COL2~~-~
~_ _ _ _ _~(1~0~) ~~:E
GN
(Ii'
8
(5)
2.4 kll
:s
7
TCM50B9
TONE ENCODER
02651. NOVEMBER 1982 - REVISED OCTOBER 1984
•
Low-Cost TV Color-Burst Crystal Sine-Wave
Input Produces Highly Accurate and Stable
Tones
•
Device Powered Directly by Telephone or
Small Batteries
•
•
•
•
•
•
•
•
•
•
•
Keyboard or Electronic Input Capability
Dual-Tone and Single-Tone Capability
Minimal Standby Power Requirement
N PACKAGE
ITOPVIEWI
Voo
TONE ENABLE
COL 1
COL 2
COL 3
VSS
OSCINPUT
TONE OUTPUT
SINGLE-TONE ENABLE
ROW 1
ROW 2
ROW 3
FiOW4
~KE~Y:B~O~AR~O~A~C~TmIV~E
OSC OUTPUT L..C:...----:::r> COL 4
..
Total Harmonic Distortion Meets EIA
Standard RS-470
U)
·S
PEP3 Processing Available
CJ
~
Wide Supply-Voltage Range
(3
Minimal External Parts Required
U)
C
Single-Tone Production Can be Inhibited
o
.~
Separate Tone Enable Provided
ca
Auxiliary Switching Bipolar Transistor
Available
CJ
'2
;::,
E
Designed to be Interchangeable with Mostek
MK50B9
•
E
o
~ .. _~ Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
~ placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
CJ
Q)
1)
I-
description
The TCM5089 tone encoder is a CMOS integrated circuit designed specifically to generate the dial tones
used in dual-tone telephone dialing systems. It requires a sine-wave input normally supplied by a low-cost
TV color-burst crystal at 3.579545 MHz to generate eight different audio sinusoidal frequencies. With
this input the encoder generates dial tones that are very low in total harmonic distortion and comply with
standard Dual-Tone Multi-Frequency (DTMF) specifications without any need for frequency adjustment.
When generating a dual-tone signal, the encoder generates one column tone and one row tone and adds
them for its output. The table below presents the frequencies produced by the tone encoder with the
3.579545-MHz TV-crystal signal input. Any deviation in this frequency will be reflected in the frequency
output. The tolerance of the crystal is normally 0.02%.
TONE
Row 1
Row 2
Row 3
Row 4
Column
Column
Column
Column
1
2
3
4
DTMF
STANDARD
IHzl
697
770
852
941
1209
1336
1477
1633
ENCODER
OUTPUT"
IHzl
701.3
771.4
857.2
935.1
1215.9
1331.7
1471.9
1645
ERROR
FROM STANDARD"
1%1
+0.62
+0.19
+0.61
-0.63
+0.57
-0.32
-0.35
+0.73
'Using an input Signal from a 3.579545-MHz crystal.
PRODUCTIOI DATA ..........I1 .....in information
"l\1IIIt II ., p••lication dilL Prod.eII ••nto... t.
opocI1IcatIou plr the tarll. of T.... Inotrum.nII
~;"{.r:t':.J.; =:~ ~I-==" nil
Copyright @ 1982. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
2-167
TCM5089
TONE ENCODER
operation
keyboard and electronic Inputs
The specific tone or tones generated are determined by inputs designated ROW 1 through ROW 4 and
COLUMN 1 through COLUMN 4. These input levels are normally received from a 2-of-8 DTMF (DPST)
keyboard or from an electronic circuit. Unlike dynamic or scanned inputs, the static inputs of the TCM5089
do not generate any noise. See function table for input and output description.
2..,f-8 DTMF KEYBOARD (DPSTI
V"
t--"""-
r-"
~
"--ROW
single-tone enable input
This inhibits the generetion of single tones when taken low or left open. However, all other chip functions
remain unchanged. If the input is high, single-tone operation is enabled.
tone enable input
The tone enable input, when low,disables the tone output of the encoder. Other chip functions remain
unchanged.
keyboard active output
This output provides for switching of an external receiver, transmitter, or other functions. The output is
low whenever one or more column inputs are active and at a high impedance when all column inputs are
inactive.
functional block diagram
0~IN~7~
________________________~~>-~~________________________-=~~) O~OUT
VDD~I~1)~~~~----------~VDD
CTRDIV K
ROW1~1~14~)-+~~~________~________________r-~[K~1~J
ROW 2 (13)
ROW 3 (12)
1mW4 (11)
TONE ENABLE ...;1....
2)'---t++-r-________. .______- ,
[K=4640J
[K=41761
[K=36281
=1
SINGLE·
TONE
ENABLE
~~---------------tt
CTRDIV K
r
~
Vss
2-168
TEXAS . .
INSTRUMENTS
POST OFFICE BOX 655012 • DAlLAS. TeXAS- 75266
KEVBOARD ACTive
TCM5D89
TONE ENCODER
TONE ENCOOER FUNCTION TABLE
INPUT
COMBINATlONSt
TONE OUTPUT
PIN 2 OPEN *
PIN 20PEN*
PIN 15 at VOO*
PIN 15 at VSS*
0
OUTPUT
0
0
Hi-Z
Rowand column
Rowand column
0
L
column
0
0
L
Row
0
0
L
0
0
0
L
Column
0
0
L
CJ
0
0
0
L
en
o
'+0
co
(.)
o rows
o Columns
1 row
1 column
2
1
1
2
KEYBOARO ACTIVE
PIN 2 AT VSS*
or more rows
column
row
or more columns
2 or more rows
2 or more columns
...en
'S
(.)
o rows
1 column
o rows
2 or more columns
~
C
1 or more rows
0
o columns
Hi-Z
0
0
tAn inactive level can be produced by an open circuit. Under voltage~level control, row and column inputs will be active when low as
defined by VIL in recommended operating conditions.
tPin 15 is the single-tone enable input; Pin 2 is the tone-enable input.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage VOO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13.5 V
Input voltage range ......................................... -0.3 V to VOO + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VOO + 0.3 V
Continuous power dissipation at 25°C free-air temperature (see Note 2) ............. 1150 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -30°C to 70°C
Storage temperature range ......................................... - 55°C to 150°C
NOTES:
'2
::::s
E
E
o
(.)
Q)
"G)
I-
1. All voltage values are with respect to the VSS terminal.
2. For operation above 25°C see the Dissipation Derating Curve.
DISSIPATION DERATING CURVE
1200
==EI 1000
~
c
.2
:;;
"e"-
800
,.~
c
600
c3
400
..............
I'--.. I"--..
.......
is
~ .............
.~
,.E
E
'xIV
200
:iE
25
35
45
65
55
75
TA-Free·Air Temperature-OC
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
85
2-169
"TCM5089
TONE ENCODER
recommended operating conditions
MIN
Supply voltage, VOO
High-level input voltage, any input, VIH
low-level input voltage, any input, Vil
NOM
MAX
3
10
0.7 VOO
VOO
0.3 VOO
70
VSS
-30
Operating free-air temperature, TA
UNIT
V
V
V
·C
electrical characteristics over operating free-air temperature range (unless otherwise noted)
"~
C1>
CD-
C")
o
3
3
e
IOH
IOl
IOOstby
IOOop
PARAMETER
Input resistance, single-tone input to VSS
High-level output current, keyboard active output
low-level output current, keyboard active output
Standby pOWer supply current
Operating power supply current
~
~
o
o
a·'
e
=+'
"0
= 5 VT
= 0.5 VT
VOO = 10 V,
Vo
Vo
MIN
20
TYP MAX
kll
p.A
p.A
200
2
p.A
mA
-500
See Note 3
VOO - 3.5 V, See Note 4
UNIT
100
2
operating characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted)
n'
a0'
TEST CONDITIONS
TEST CONOITIONS*
PARAMETER
Output rms voltage
I Row tone
I Column tone
VOO
= 3.5 V, Rl = 10 kll
Preemphasis (column-tone to row-tone)
Dual-tone output distortion (see Note 5)
Rl - 10 kll
Quiescent tone-output power
Rl
MIN
TYP
235
275
2.4
VOO '" 3.5 V, Rl = 10 kll
= 10 kll
2.8
Tone-output rise time (see Note 6)
MAX
UNIT
365
516
mV
3
-20
d8
-80
5
dBm
ms
d8
tVo is the dc bias on the keyboard-active output.
*Crystal parameters are as follows: f = 3.579545 MHz ±0.02%, RS s 100 II, Cl = 18 pF, CM = 0.02 pF, and lM = 96 mHo
NOTES: 3. Standby power supply current is measured with no inputs activated.
4. Operating currem is measured with all outputs unloaded, one row Inut and one column input active, and normal oscillator input.
5. Distortion is expressed as the ,atio of total out-of-band power relative to the total fundamental power for the dual tone.
6. This is the time required for the output to change from its quiescent value to 90% of its final rms value.
2-170
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75286
TCM5089
TONE ENCODER
output waveforms
Typical row and column stairstep approximations of sinusoidal outputs are shown in Figures 1 and 2. The
row and column outputs are added together resulting in a typical dual-tone waveform as shown in Figure 3.
Spectral analysis of this dual-tone waveform shows that all harmonic and intermodulation distortions are
typically 30 dB below the strongest column-tone fundamental.
.?:
.?:
.?:
:e>
:e>
:e
<>
<>
<>
>
II!
II!
II!
U)
0.2 ms/div
0.2 mS/di.
0.2 ms/div
FIGURE 1
FIGURE 2
FIGURE 3
C
o
'';:
CO
u
distortion considerations
The following formula is used to calculate the total harmonic distortion of a single row or a single column:
~O=
(
,JV2f2
+ V3f 2 + V4f 2 + V5f 2 + ... + vnf2)
u
CD
where V2f is the second harmonic of the fundamental frequency V1f waveform and so on. The dual-tone
total harmonic distortion is:
\
j
E
E
o
x 100%
V1f
THO = (.JV 2R2
'2
Gi
I-
+ V3R 2 + ... + VnR2 + V2C 2 + ... VnC2 ± VIM0 2 ) x 100%
.JVFR2
+ VFC 2
where VFR and VFC are the row and column fundamental frequency waveforms, and V2R and V2C, etc.
are the corresponding harmonics.
The total intermodulation distortion is:
A relatively simple method of distortion measurement uses a spectrum analyzer to relate the harmonics
to the fundamental frequency waveform. The tone encoder spectrum indicates the harmonics and
intermodulation distortion at least 30 dB down relative to the column tone.
Another method for distortion measurement of the dual-tone waveform is to compare the total power in
the fundamental frequencies with the total power in the various harmonics plus intermodulation on a signal
analyzer. The encoders provide an output distortion of - 20 dB maximum when operated between 3.5 volts
and 10 volts. If operated between 3 volts and 3.5 volts, some clipping occurs at the output causing the
distortion to exceed the - 20 dB level.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
2-171
TCM5089
TONE ENCODER
APPLICATIONS INFORMATION
Vss
__+r_-~L1- - --F:b.1L_ _+==.---1"-"t-~r---":(i6} Vss TCM5~;W 1
C
-I
05
CD
(14)
2-OF-8
2
KEY:OA~!:
1--4-+-1---4
Vss
ROW 2 (13)
4
5
6
B:
Ri5W3 (12)
7
8
9
-c-l
I
CD
L2
n
RR
3
3
~R~_~_ _- ._ _~_-.~_. .~_+-~(l~) VOO
A
c::
j
r+
0'
00[2
I
(5)
OSC (7)
INPUT
.---l-.!..11~0~) =KE=Y--B~O-A""'R':':O
AC'fiiiE
GN
tn
I
I
I
:
COL3
I
COL 4 (9'- _ _ _ _ _ _ _ .J
I»
j
L.,....L_O_L...,....L_~ J
_
K
(i'
1--4-+-~---l
(16) TONE
OUTPUT
R
0
(")
o
XTAL
OSC
OUTPUT
=t'
n
c::
;::;.'
tn
COLUMN
A ______
ROW
2..,f8 OTMF KEYBOARD (OPST)
~
HKSWl
T
---L 1·1.---
XTAL PARAMETERS:
Vss
MIC.
B
CM = 0.02 pF
LM=96mH
CH = 5 pF
f - 3.579545 MHz
L ______ _
SIOETONE·BALANCE
NETWORK
TYPICAL VALUES
Cl = 0.001 ",F
RL = 120 n (or 10 kO if optional transistor is used)
R'L = 150 n optional
01,02,03,04 = lN4004
05-lN4743 (13 volt)
FIGURE 4. TYPICAL APPLICATION USING HYBRID COIL SIDETONE-BALANCE NETWORK,
ELECTRONIC SWITCHING, AND LOW-COST (CLASS AI KEYBOARD
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-172
TCM5092
TONE ENCODER
02662. NOVEMBER 1982 - REVISED APRIL 1988
•
Low-Cost TV Color-Burst Crystal Sina-Wave
Input Produces Highly Accurate and Stable
Tones
•
Device Powered Directly by Telephone or
Small Batteries
•
Keyboard or Electronic Input Capability
•
Dual-Tone and Single-Tone Capability
•
Minimal Standby Power Requirement
•
Total Harmonic Distortion Meets Industry
Standards
•
PEP3 Processing Available
N PACKAGE
(TOPYIEWI
Yoo
TONE OUTPUT
TONE ENABLE
SINGLE-TONE ENABLE
COL1
ROW1
COL2
ROW2
COL3
ROW3
VSS
ROW4
OSC INPUT
MUTE OUTPUT
OSC OUTPUT '-1..::_---"-..... COL4
II)
.~
.
C3
::::s
(,)
•
Wide Supply-Voltage Range
•
Minimal Parts Required
•
Single-Tone Production Can Be Inhibited
•
Auxiliary Switching Outputs: One Bipolar
Transistor and One CMOS Gate
•
Designed to be Interchangeable with Mostek
MK5092
II)
I:
o
'';::;
CO
,S:!
I:
::::s
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
E
E
o
(,)
CD
G)
description
t-
The TCM5092 tone encoder is a CMOS integrated circuit designed specifically to generate the dial tones
used in dual-tone telephone dialing systems. It requires a sine-wave input normally supplied by a low-cost
TV color-burst crystal at 3.579545 MHz to generate eight different audio sinusoidal frequencies. With
this input the encoder generates dial tones that are very low in total harmonic distortion and comply with
standard Dual-Tone Multi-Frequency (DTMF) specifications without any need for frequency adjustment.
When generating a dual-tone signal, the encoder generates one column tone and one row tone and adds
them for its output. The table below presents the frequencies produced by the tone encoder with the
3.579545-MHz TV-crystal signal input. Any deviation in this frequency will be reflected in the frequency
output. The tolerance of the crystal is normally 0.02%.
DTMF
STANDARD
(Hzl
TONE
697
770
Row 1
Row 2
Row 3
Row 4
Column 1
Column 2
Column 3
Column 4
852
941
1209
1336
1477
1633
ENCODER
OUTPUT"
(Hz)
701.3
771.4
857.2
935.1
1215.9
1331.7
1471.9
1645
ERROR
FROM STANDARD"
(%1
+0.62
+0.19
+0.61
-0.63
+0.57
-0.32
-0.35
+0.73
'Using an input signal from a 3.579545-MHz crystal.
PRODUCTION DATA d......... ","""il infarlllll...
••rrolt II of p.blleoll... doto. Produt:tI 00.10111 10
lpoclflcollo..... tho te....., T.... lnotru_
==i;":::::z. ~m::: :.r:::~:.~
III
Copyright @ 1982. Texas Instruments Incorporated
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 855012 • DALLAS, TEXAS 76265
2-173
TCM5092
TONE ENCODER
operation
keyboard and electronic inputs
The specific tone or tones generated are determined by inputs designated ROW1 through ROW4 and
COLUMN 1 through COLUMN 4. The inputs are normally received from a 2-of-8 DTMF (DPST) keyboard,
a Class A (SPST) keyboard, or an electronic circuit. Unlike dynamic or scanned inputs, the static inputs
of the TCM5092 do not generate any noise. See funCtion table for input and output description.
2..,f·8 DTMF KEYBOARD (DPSTI
CLASS A KEYBOARD (SPST)
~
COLUMN
+----A
~ ROW
LEAVE
OPEN
----G+---
(1)
""'"
CD
()
o
3
3
c
::l
single-tone enable Input
This input inhibits the generation of single tones when taken low. However. all other chip functions remain
unchanged. If the input is high, single-tone operation is enabled.
tone enable input
A low logic level at this input inhibits tone generation of the encoder. Other chip functions remain unchanged.
CI)
S·
COLUMN
- - - ROW
5"
pot.
~
mute output
::l
(I)
The mute output is high when any column input is active and is low when all column inputs are inactive.
(') functional block diagram
::;"
()
c
::+
(I)
O~IN~(~7--
__________________________~~~__~__________________________(~8)Lo~OUT
Voo~(""lI,--............._
voo
CTROIV K
ROW 1 ~(f.14::-)- + + H.....------------------------~I__cfIK-5104J
iiOv.i 2 (13)
IK=4640J
iiOv.i3~
l_~
iiOv.i 4 (11)
IK'3828J
EN
SINGLE·
TONE
..J.!:"-<~
____________""'"
ENABLE
CTROIV K
EN
COLUMN 1 "*!!--+4H++-----------------------------IIK.2944J
5)
I~:~::
COLUMN 4 (9)
~~~~~ ~
IK'21761
Vss ...ll!l6):.-~......._vss
2-174
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
TCM5092
TONE ENCODER
TONE ENCODER FUNCTION TABLE
INPUT
COMBINATIONSt
o rows
o columns
1 row
1 column
2 or more rows
1 column
1
2
2
2
row
or more columns
or more rows
or more columns
o rows
1 column
o rows
2 or more columns
, or more rows
o columns
TONE OUTPUT
MUTE OUTPUT
PIN 2 OPEN. *
PIN 16 OPEN*
PIN 2 OPEN. *
PIN 16 AT VSS*
PIN 2 AT VSS*
0
0
0
L
Rowand column
Rowand column
0
H
column
0
0
H
Row
0
0
H
0
0
0
H
Column
0
0
H
(3
0
0
0
H
II)
0
0
0
L
'';:;
....
II)
'S
...
(J
C
o
ca
tRow inputs will be active (on) when the input voltage is at a low (evel (VI :$ VILI. and column inputs are active at a high input level.
Under keyboard control, connecting a row input to a column input will activate both.
*Pin 15 is the single-tone enable input; pin 2 is the tone-enable input.
,~
C
:::J
E
E
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage VOO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13.5 V
Input voltage range ......................................... -0.3 V to VOO + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VOO + 0.3 V
Continuous power dissipation at 25°C free-air temperature (see Note 2) ............. 1150 mW
Operating free-air temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -30°C to 70°C
Storage temperature range ......................................... - 55°C to 150°C
o(J
Q)
...
"i
NOTES: 1. All voltage values are with respect to the VSS terminal.
2. For operation above 25°C free-air temperature, see the DisSipation Derating Curve.
DISSIPATION DERATING CURVE
1200
3:
fc
1000
i'-..
.2
:;;
a.
'iii
800
°
600
0
400
::J
........... ~
~ .............
is
"::J
...........
C
.~
CJ
E
E
::J
.~
200
:E
25
35
45
55
65
75
TA-free-Air Temperature-°c
TEXAS ."
INSTRUMENTS
POST OFFICE BOX,855012 • DALLAS, TEXAS 15285
85
2-175
TCM5092
TONE ENCODER
recommended operating conditions
MIN
Supply voltage, Voo
High-level input voltage, VIH
Low-level input voltage, VIL
NOM
10
Row inputs (off)
0.9 Voo
All other inputs
Column inputs (off)
All other inputs
0.7 Voo
Voo
Voo
0.1 Voo
0.3 Voo
1000
VSS
VSS
Contact resistance between row and column inputs
Voo
Voo
Tone-output load resistance, RL
<
~
5 V, VB = -1.5 vt
5 V, VB = -3.5 vt
620
330
-4
3
3
c
PARAMETER
Q)
c)"
::J
en
(')
TEST CONDITIONS
High-level output voltage, mute output
Voo - 3 V,
Voo=10V,
VOL
Low-level output voltage, mute output
Voo = 3 V,
Voo = 10 V,
II
Input current
VOH
::J
rr
....
V
V
0
0
70
°C
electrical characteristics over operating free-air temperature range (unless otherwise noted)
Ci'
(')
o
UNIT
V
0
-30
Operating free-air temperature, T A
CD
MAX
3.5
100 stby
Standby supply current
looop
Operating current
IOH - 0.2 rnA,
IOH = 0.5 rnA
IOL = -0.2 mA
Column
inputs
Voo = 3 V,
Voo = 10V,
IOL - -0.5 rnA
VI = 2.1 V
VI = 7 V
Row
input.
Voo = 3 V,
Voo = 10 V,
Voo = 10V,
VI - 0.9 V
VI = 3 V
See Note 3
Voo = 5 V,
See Note 4
TA = 25°C,
::;"
MIN
2
TVP
MAX
UNIT
V
9
0.5
0.5
130
545
-130
-545
V
pA
pA
200
pA
10
rnA
(')
C operating characteristics over recommended ranges of operating free-air temperature and supply voltage
;:;" (unless otherwise noted)
en
PARAMETER
Row tone
Output rms voltage
Column tone
Preemphasis (column tone to row tone)
Output distortion
Dual-tone
Quiescent tone output power
I
TEST CONDITIONS*
VB = 1.5 vt,
TA
VB - 3.5 vt,
TA
VB = 1.5 vt,
TA
VB = 3.5 vt,
TA
Voo = 10V,
Voo = 3.8 V,
Voo - 10 V,
Voo = 3.8 V,
25°C
25°C
25°C
25°C
MIN
422
441
528
551
1
Voo
~
5 V,
TA = 25°C,
See Note 5
8
Tone-output rise time (see Note 6)
=
=
Voo - 3.8 V,
Voo = 10 V,
VB-l.5V
VB = 3.5 vt
TVP MAX
531
555
664
UNIT
mV
693
3
-20
-80
5
5
dB
dB
dBm
ms
tVa is the negative dc bias applied to the tone output through RL.
*Unless otherwise noted, test conditions are: RL = 620 0 for Voo < 5 V or RL = 330 0 for Voo ~ 5 V. Crystal parameters are the
following: f = 3.579545 MHz ±0.02%, RS = 1000, CL = 18 pF, CH = 5 pF, CM = 0.02 pF, LM = 96 mHo
NOTES: 3. Standby supply current is measured with all outputs unloaded and no inputs activated.
4. Operating supply current Is measured with all outputs unloaded, one row input connected to one column input, and normal
oscillator input.
5. Distortion measurements are in terms of the total out-of-band power relative to the total column and row fundamental power.
6. This is the time required for output to change from its quiescent value to 90% of its final rms value.
2-176
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75285
TCM5092
TOlE EICODER
output waveforms
Typical row and column stairstep approximations of sinusoidal outputs are shown in Figures 1 and 2. The
row and column outputs are added together resulting in a typical dual-tone waveform as shown in Figure 3.
Spectral analysis of this dual-tone waveform shows that all harmonic and intermodulation distortions are
typically 30 dB below the strongest column-tone fundamental.
.!
.!
:!!
:!!
..
>
..>
"I
"I
fh
0.2 msldiv
0.2 ms/div
0.2 ms/div
FIGURE 1
FIGURE 2
FIGURE 3
C
o
",i:
ca
u
distortion considerations
"2
The following formula is used to calculate the total harmonic distortion of a single row or a single column:
THO
=(
.JV2f2
+
V3f 2
+
V4f 2 + V5f 2
V
1f
+ ... +
:::s
E
E
o
Vnf2)
x 100%
u
Q)
where V2f is the second harmonic of the fundamental frequency V1f waveform and so on. The dual-tone
total harmonic distortion is:
THO = (.JV2R2
+
V3R 2
+ ... +
VnR2
.JVFR2
+
+
V2C 2
+ ...
G)
I-
VnC 2 ± VIM02)x 100%
VFC 2
where VFR and VFC are the row and column fundamental frequency waveforms, and V2R and V2C, etc.,
are the corresponding harmonics.
The total intermodulation distortion is:
A relatively simple method of distortion measurement uses a spectrum analyzer to relate the harmonics
to the fundamental frequency waveform. The tone encoder spectrum indicates the harmonics and
intermodulation distortion at least 30 dB down relative to the column tone.
Another method for distortion measurement of the dual-tone waveform is to compare the total power in
the fundamental frequencies with the total power in the various harmonics plus intermodulation on a signal
analyzer. The encoders provide an output distortion of - 20 dB maximum when operated between 3.5 volts
and 10 volts. If operated between 3 volts and 3.5 volts, some clipping occurs at the output causing the
distortion to exceed the - 20 dB level.
TEXAS .."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
2-177
TCM5092
TONE ENCODER
APPLICATIONS INFORMATION
~
HK SW1
r-
L'---"
T--~~~
COLUMN
4
1
••
•
ROW
CLASS A KEYBOARO (SPSTI
CLASS A KEYBOARD
1r-"'T"'C::'lM""50r.9~2~
.-_--_-----(:::6!.1
Vss
_
(141
--.,
ROW 1
2
3
Ai
D5
1
,,~~--~
C
0_001 "F
RR
ROW 2 (13)
~-+---I--+--'"
4
5
6
B:
_
(12)
ROW3
(16) TONE
(11)
OUTPUT ROW4
12011
7
B
9
*
°
#
(3)
--~
C:
---I
D:
-.-"'
I
R
I
I
10k11
GN
L'(=.;51_____---'
COL 3.(151 SINGLE-TONE
(91
ENABLE COL 4 - - - - - - - OSC (7)
2_7
INPUT
(2) TONE
2_4k11
k11
ENABLE
XTAL
L---I-____~-----'--(1;.;0_'_l) MUTE
OUT
:
.J'
o
XTAL PARAMETERS:
CM = 0_02 pF
MIC_
B
D1. D2. D3. D4· 1N4004
LM
D5· 1N4743 (13 voltl
CH =5pF
c
96mH
f = 3_579545 MHz
1.- _ _ _ _ _ _ _ ..1
SIDETONE-BALANCE
NETWORK
FIGURE 4. TYPICAL APPLICATION USING HYBRID COIL SIDETONE-BALANCE NETWORK.
ELECTRONIC SWITCHING. AND LOW-COST (CLASS Al KEYBOARD
2-178
TEXAS .".
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TeXAS 75265
TCM5094
TONE ENCODER
03099. OCTOBER 1987-REVISED FEBRUARY 1988
•
Low-Cost TV Color-Burst Crystal Sine-Wave
Input Produces Highly Accurate and Stable
Tones
•
Device Powered Directly by Telephone or
Small Batteries
•
Keyboard or Electronic Input Capability
•
Dual-Tone and Single-Tone Capability
•
Minimal Standby Power Requirement
•
Total Harmonic Distortion Meets Industry
Standards
•
PEP3 Processing Available
•
Wide Supply-Voltage Range
•
Minimal Parts Required
•
Single-Tone Production Can Be Inhibited
N PACKAGE
ITOP VIEW)
TONE OUT
SINGLE-TONE ENABLE
ROW 1
ROW 2
ROW 3
ROW 4
MUTE OUT
COL 4
Voo
TONE ENABLE
COL 1
COL 2
COL 3
VSS
OSCIN
OSC OUT
....
II)
'S
(.)
C3
II)
c
o
•
Auxiliary Switching Outputs: One Bipolar
Transistor and One CMOS Gate
'';:;
&U
•
Mute Output Can Switch at VDD ~ 1.7 V
•
Designed to be Interchangeable with Mostek
MK5094
'2
j
E
E
o(.)
(.)
description
The TCM5094 tone encoder is a CMOS integrated circuit designed specifically to generate the dial tones
used in dual-tone telephone dialing systems. It requires a sine-wave input normally supplied by a low-cost
TV color-burst crystal at 3.579545 MHz to generate eight different audio sinusoidal frequencies. With
this input, the encoder generates dial tones that are very low in total harmonic distortion and comply with
standard Dual-Tone Multi-Frequency (DTMF) specifications without any need for frequency adjustment.
Q)
"i
I-
When generating a dual-tone signal, the encoder generates one column tone and one row tone and adds
them for its output. The table below presents the frequencies produced by the tone encoder with the
3.579545-MHz TV-crystal signal input. Any deviation in this frequency will be reflected in the frequency
output. The tolerance of the crystal is normally 0.02%.
TONE
DTMF
STANDARD
(Hz)
ENCODER
OUTPUT"
(Hz)
ERROR
FROM STANDARD"
(%)
697
770
701.3
+0.62
771.4
+0.19
Row 3
Row 4
Column 1
Column 2
852
941
1209
1336
857.2
935.1
+0.61
-0.63
1215.9
1331.7
Column 3
Column 4
1477
1471.9
+0.57
-0.32
-0.35
1633
1645
+0.73
Row 1
Row 2
'Using an input Signal from a 3.579545-MHz crystal.
Caution. These devices have limited built-in gate protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PRODUCTION DATA doc ••lntl.onhin imr••tion
••rrent II of publication dille. Prod.cIS conform to
lpooifioationB per th. tor... 0' TI..I Instrumentl
::'~=~~~'i~:I':!Ti ~1':I:r :.\,=::!'t!'~~ not
Copyright @ 1987. Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-179
TCM5094
TONE ENCODER
operation
keyboard and electronic inputs
The specific tone or tones generated are determined by inputs designated ROW 1 through ROW 4 and
COLUMN 1 through COLUMN 4. The inputs are normally received from a 2-of-8 DTMF (DPST) keyboard,
a Class A (SPST) keyboard, or an electronic circuit. Unlike dynamic or scanned inputs, the static inputs
of the TCM5094 do not generate any noise. See function table for input and output description.
CLASS A KEYBOARD (SPST)
2-of·8 DTMF KEYBOARD (DPST)
~
+-------A
-I
COLUMN
CD
Single-tone enable input
--t=:--+-
LEAVE
OPEN
CD
n
o
3
3
s::::
. L - - ROW
This input inhibits the generation of single tones when taken low. However, all other chip functions remain
unchanged. If the input is high or left open, single-tone operation is enabled.
tone-enable input
:::J
c;'
....
~
. L - - COLUMN
~ ROW
A low logic level at this input inhibits tone generation of the encoder. Other chip functions remain unchanged.
I»
0"
mute output
:::J
til
The mute output is high when any column input is active and is low when all column inputs are inactive.
The mute output operates with VDD as low as 1.7 V.
(")
::;" functional block diagram
n
s::::
;:;'
til
OOCIN~(~71~
__________________________~~~__~__________________________~(8~1 OOCOUT
VOO,-"..:,(1!...1...........~~. VOO
CTROIV K
iiOvi 1...,(::;14:f.1-++H~__________________________I--~[K=5104[
iiOvi 2 (131
[K-4640]
iiOvi3~
[_~
iiOvi 4
[K=3828]
(111
EN
S~~~~-~(~15~1________________+t
ENABLE
CTROIV K
EN
+
COLUMN 1...,(~31c-~H-+t------------------------------I[K=2944]
COLUMN 2 (41
[K=2688]
COLUMN 3 5
[K=2432]
COLUMN 4 (91
[K=2176]
Vss ...;(""61:-_........_
2-180
Vss
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS, TEXAS 75285
TCM5094
TONE ENCODER
TONE ENCODER FUNCTION TABLE
INPUT
COMBINATIONSt
o rows
o columns
1 row
1 column
2 or more rows
1 column
1 row
2 or more columns
2 or more rows
2 or more columns
o rows
1 column
o rows
2 or more columns
1 or more rows
o columns
TONE OUTPUT
MUTE OUTPUT
PIN 2 OPEN. *
PIN 20PEN.*
PIN 15 OPEN*
PIN 15 AT VSS*
0
0
0
L
Rowand column
Rowand column
0
H
Column
0
0
H
Row
0
0
H
0
0
0
H
Column
0
0
H
0
0
0
H
0
0
0
L
PIN 2 AT VSS*
II)
:!::
..
C3
::::J
(,)
.
II)
c
'
tRow inputs will be active (on) when the input voltage is at a low level (V, ::s VIL), and column inputs are active at a high input level.
Under keyboard control, connecting a row input to a column input will activate both.
*Pin 15 is the single-tone enable input; pin 2 is the tone enable input.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage VOO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13.5 V
Input voltage range ......................................... -0.3 V to VOO + 0.3 V
Output voltage range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to VOO + 0.3 V
Continuous power dissipation at 25°C free-air temperature (see Note 2) ............. 1150 mW
Operating free-air temperature range ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 30°C to 70 °C
Storage temperature range ......................................... - 55°C to 1 50°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 260°C
o
as
(,)
'2
::::J
E
E
o
(,)
Q)
Q)
I-
NOTES: 1. All voltage values are with respect to the VSS terminal.
2. For operation above 25 °C free~air temperature, see the Dissipation Derating Curve.
DISSIPATION DERATING CURVE
1200
3:
E 1000
I
c
~
.2
:g
"-
.~
800
0
:;
0
.,
::J
............
............ r--..
"'~
600
-........,.
.
C
C
°
400
'x
200
u
E
::J
E
~
25
35
45
55
65
75
TA-Free-Air Temperature-OC
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
85
2-181
TCM5094
TONE ENCODER
recommended operating conditions
MIN
Supply voltage, VOO
NOM
3.5
Row inputs (off)
High-level input voltage, VIH
0.9 VOO
0.7 VOO
All other inputs
Column inputs (off)
Low-level input voltage, VIL
VOO
VOO
0.1 VOO
0.3 VOO
1000
VSS
All other inputs
VSS
Contact resistance between row and column inputs
Tone-output load resistance, RL
<
I
VOO
5V
620
I
VOO '" 5 V
330
-30
Operating free-air temperature, T A
-I
CD
ar
n
o
PARAMETER
TEST CONOITIONS
VOH
:::J
VOL
Low-level output voltage, mute output
II
Input current
High-level output voltage, mute output
(;'
Column
Inputs
I»
1+
0'
:::J
(I)
(')
::;'
n
5.-
1+
(I)
70
UNIT
V
V
V
°
°
°C
electrical characteristics over recommended operating free-air temperature range (unless otherwise
noted)
3
3
c
MAX
10
IOOstbv
IOOop
VOO
VOO
VOO
=
=
=
=
1.7 V,
10 V,
1.7 V,
VOO
10 V,
VOO = 3 V,
VOO = 10 V,
VOO = 3 V,
VOO=10V,
Row
Inputs
Standby supply current
VOO = 10 V,
VOO - 5 V,
See Note 4
Operating current
MIN
= 0.2 rnA
IOH = 0.5 mA
IOL = -0.2 mA
MAX
1
9
IOH
V
0.5
IOL = -0.5 rnA
VI = 2.1 V
VI = 7 V
VI = O.g V
0.6
130
645
-130
VI = 3 V
See Note 3
-546
TA - 25°C,
UNIT
V
p.A
p.A
200
p.A
10
mA
operating characteristics over recommended ranges of operating free-air temperature and supply voltage
(unless otherwise noted)
TEST CONOITIONSt
PARAMETER
Row tone
Output rms voltage
Column tone
Preemphasis (column tone to row tone)
Output distortion
Oual-tone
VOO = 3.8 V,
VOO = 10 V,
RL = 3200,
RL = 3200,
TA = 25°C
TA = 25°C
VOO = 3.8 V,
RL = 3200,
TA = 25°C
TA = 25°C
VOO
= 10 V,
VOO '" 5 V,
= 3200,
TA = 25°C
TA = 25°C,
RL
See Note 5
Quiescent tone-output power
Tone-output rise time (see Note 6)
VOO
VOO
= 3.8 V
= 10 V
MIN
360
452
387
486
1
MAX
453
569
487
UNIT
mV
612
3
-20
-80
5
5
dB
dB
dBm
ms
°
tUn less otherwise noted, test conditions are: RL = 620 for VOO < 5 V or RL = 330 0 for VOO '" 5 V. Crystal parameters are the
following: f = 3.579545 MHz ±0.02%, RS < 100 0, CL = 18 pF, CH = 5 pF, CM = 0.02 pF, LM = 96 mHo
NOTES: 3. Standby supply current is measured with all outputs unloaded and no inputs activated.
4. Operating supply current is measured with all outputs unloaded, one row input connected to one column input, and normal
oscillator input.
5. Distortion measurements are in terms of the total out-of-band power relative to the total column and row fundamental power.
6. This is the time required for output to change from its quiescent value to 90% of its final rms value.
2-182
TEXAS •
INSfRUMENlS
POST. OFFICE BOX 655012 • DALLAS, TEXAS 76265
TCM5094
TONE ENCODER
output waveforms
Typical row and column stairstep approximations of sinusoidal outputs are shown in Figures 1 and 2. The
row and column outputs are added together resulting in a typical dual-tone waveform as shown in Figure 3.
Spectral analysis of this dual-tone waveform shows that all harmonic and intermodulation distortions are
typically 30 dB below the strongest column-tone fundamental.
.!
.f:
=l!
=l!
II!
o
II!
o
>
>
0.2 moldi.
0.2 msldi.
0.2 msldiv
FIGURE 1
FIGURE 2
FIGURE 3
en
c
o
.';:;
distortion considerations
The following formula is used to calculate the total harmonic distortion of a single row or a single column:
THO =
(
JV2f2 + V3f 2 + V4f 2 + V5f2 + ... + vnf2)
V
x 100%
1f
·c'U::::I"
E
E
o
u
Q)
where V2f is the second harmonic of the fundamental frequency V1f waveform and so on. The dual-tone
total harmonic distortion is:
"G)
I-
THO = (JV2R2 + V3R 2 + ... + V nR2 + V2C 2 + ... VnC 2 ± VIM0 2 ) x 100%
JVFR2
+
VFC 2
where VFR and VFC are the row and column fundamental frequency waveforms, and V2R and V2C, etc.,
are the corresponding harmonics.
The total intermodulation distortion is:
A relatively simple method of distortion measurement uses a spectrum analY2er to relate the harmonics
to the fundamental frequency waveform. The tone encoder spectrum indicates the harmonics and
intermodulation distortion at least 30 dB down relative to the column tone.
Another method for distortion measurement of the dual-tone waveform is to compare the total power in
the fundamental frequencies with the total power in the various harmonics plus intermodulation on a signal
analyzer. The encoders provide an output distortion of - 20 dB maximum when operated between 3.5 volts
and 10 volts. If operated between 3 volts and 3.5 volts, some clipping occurs at the output causing the
distortion to exceed the - 20 dB level.
TEXAS ,.,
INSfRUMENlS
POST OFFICE BOX 656012 • DALLAS. TeXAS 75266
2-183
TCM5094
TONE ENCODER
APPLICATIONS INFORMATION
1
~
HKSWl
-----Ll
F
COLUMN ..
••
• ROW
CLASS A KEYBOARD ISPSTI
CLASS A
r-~_....._ _...,;1","6){-T:::C::::M:::5~O:::9~4""
Vss
_
(14)
1
T
05
C
..of
RR
CD
A
n
o
3
3
c
R
I
I
I
(16)
120 n
,
I
I
K
110kn
::l
(;'
__
(12)
ROW 3
I
I
L2
GN
....m
0'
::l
:::;'
n
1--+-+--+--..
4
5
6
B:
--~
7
8
9
ROW 4 (11)
*
0
#
L..,o.......,.......1..,........
COL 1
B
I
II... _ _ _ _ _ _ _ .J
o
SIDE TONE-BALANCE
NETWORK
0:
-r
I
COL 2 ~'-----'
I
15)
I
COL 3
I
(15) SINGLE-TONE
(9)
ENABLE COL 4
-- -----OSC 171
2.7
INPUT
(2) TONE
2.4kH
kn
ENABLE
XTAL
'---+__.....___I:..;.l.;..O)'iMUTE
OUT
OSC
OUTPUT
XTAL PARAMETERS:
.J'
o
01.02.03.04 = lN4004
LM=96mH
05 = lN4743 113 volt)
CH = 5 pF
f = 3.579545 MHz
FIGURE 4. TYPICAL APPLICATION USING HYBRID COIL SIDETONE-BALANCE NETWORK,
ELECTRONIC SWITCHING, AND LOW-COST (CLASS AI KEYBOARD
2-184
C:
__ .J
I
CM = 0.02 pF
MIC.
c
;:;.'
b~~~UT
KEYBOARD
--.,
3
A:
I--+_+_~
(3)
o
("')
2
ROW 2 (13)
O.OOlIlF
I
CD
ROW 1
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
j
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
APRIL 1986-REVISED AUGUST 1987
•
•
•
•
•
•
•
•
•
•
•
FN. HA. OR HB PACKAGE
(TOP VIEW-LID UP FOR HA OR HBI
Eight Independent Full-Duplex Serial Data
Lines
Programmable Baud Rates Individually
Selectable for the Transmitter/Receiver of
Each Line (50 to 19.200 Baud)
9 8 7 6 5 4 3 2 1 686766 65 6463 62 61
DL7 10
DL6 11
DL5 12
DL4 13
ROY 14
RESET J15
Summary Registers Allow a Single Read to
Detect a Data Set Change or to Determine
the Cause of an Interrupt on Any Line
Triple Buffers for Each Receiver
60
59
58
57
56
55
54
53
52
51
50
49
VS§Q~16
CS 17
WR J18
NC ~19
NC 20
DS1 ~21
Device Scanner Mechanism Reports
Interrupt Requests Due to
Transmitter/Receiver Interrupts
Independently Programmable Lines for
Interrupt-Driven Operation
g24
VDD1
P26
iliQ
4!! IROTXRX
47 IROLN2
46 IROLN 1
45~ IROLNO
44 ( VDD2
~ 23
DLO~25
Modem Status Change Detection for Data
Set Ready (DSR) and Data Carrier Detect
(DCD) Signals
n2626~~~~~~~n~~~~a~
Programmable Interrupts for Modem Status
Changes
Synchronizes Critical Read-Only Registers
~ 22
DL3
DL2
DL1
NC
VSS1
CLK
MRESET
A5
A4
A3
DS2
A2
A1
AO
description
TI
HA
HB
FN
C
o
E
E
PACKAGE DESIGNATIONS
DESCRIPTION
Cerquad Gull-Wing
Cerquad Straight
Plastic PLCC
II)
·cu::3
NC - No internal connection
Direct Second Source to DEC DC349
(78808)
...
(3
ca
~C0
.... cca:::a:::CCI-I-Cca::o::oc .... >
Replaces Eight Signetics 2661 UARTs
II)
.~
°IOIOO_I_I
__ NININNM~IMMN
XWUXXUWXXWUXX
wxw
a~aoco~oo~coa
·s...u
ou
DEC
GA
FA
CD
G)
I-
The TCM78808 octal asynchronous receiver/transmitter is designed for the new generations of
asynchronous serial communications and for microcomputer systems. The device performs the basic
operations necessary for simultaneous reception and transmission of asynchronous messages on eight
independent lines.
On-chip baud rate generation allows the designer to select and program anyone of 16 rates between 50
and 19.200 baud. Baud rates are selectable for each receiver and transmitter. A built-in scanning mechanism
provides an alternative to the customary polling of status registers.
The TCM78808 functions as a serial-to-parallel. parallel-to-serial converter/controller. It can be programmed
by a microprocessor to provide different characteristics for each of its eight serial data lines (stop bits,
parity, character length, baud rates, etc.). Each individual serial line functions as a one-line UART-type device.
An integral interrupt scanner checks for device interrupt conditions on the eight lines of the TCM78808.
Its scanning algorithm is designed to give priority to receivers over transmitters. The scanner can also be
programmed to check for interrupts due to changes in modem control signals (DSR and DCD).
The TCM78808 contains two types of programmable registers: line specific and summary. The six linespecific registers provide independent control of each of the eight serial lines. Two summary registers
consolidate information about the current state of all eight lines and allow programs to service device
interrupts quickly and efficiently.
PRODUCTION DATA d•••menlleam;n inf.rmati..
....reat .. of pabliceti•• dote. Predicts .onform t.
-,flcetl... par tho torms of Te..s Instrumenll
=::i~·I~';
=:':: ~r::,.::~
not
Copyright © 1986, Texas Instruments Incorporated
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
2-185
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
Each of the eight serial data lines in the TCM78808 has a set of line-specific registers for buffering data
into and out of the line and for external control of line characteristics. The receiver buffer register comprises
a character assembly register plus a two-entry. first-in first-out (FIFO) buffer. The transmitter holding register
provides similar functions on the output side. Information about the current state of the given line is contained
in the (read-only) status register. Two mode registers control communications parameters. One mode register
handles stop bits. parity. character length. and modem control interrupt enable (MCIE). The second mode
register sets the incoming and outgoing baud rates. The command register controls various other functions
of the given line.
The TCM78808 has a pair of summary registers that provide the current status of all eight serial data
lines. This makes it possible to determine that line status has changed with a single read operation. The
(read-only) interrupt summary register indicates that an interrupt has occurred and contains both the line
number that generated the interrupt and the corresponding direction of flow (transmitter or receiver). With
both MCIEs set and receiver interrupt enabled. the interrupt summary register will respond to changes
in DSR or DCD. The data-set-change summary register monitors changes in DSR or DCD on a line-by-line
basis and indicates whether a modem status change has occurred on each data line subsequent to the
last time the corresponding bit was cleared.
~
CD
CD
n
o
3
3
c
The TCM78808 is characterized for operation from O°C to 70°C.
::::s
c;"
!
SIGNAL
AO THRU A5
DESCRIPTION
Address bits 0 through 5 select the internal registers in the TCM7BBOB.
ClK
Clock input for timing
::::s
CS
Chip Select. When low. activetes the TCM7BBOB to receive and transmit deta over data lines DlO through DL7.
o
DCOO THRU l5Ci57
Data-Set Carrier Detect inputs monitor data-set carrier detect signals from modems.
DlO THRU Dl7
Data Lines 0 through 7 receive and transmit the parallel data.
S'
o
~'
c
::;.'
o
im'. Dn
Data Strobes 1 and 2 receive timing informetion for deta transfers. The DSf and DS2 inputs must be connected
together.
~THRUi5SR7
Data Set Ready inputs monitor data-set-ready signals from modems.
jim:
Interrupt Request output requests a processor interrupt.
IROLNO THRU IROlN2
IROTXRX
Interrupt Request Line number outputs indicate the line number of the originating interrupt request.
Interrupt Request Transmit/Receive output indicates vvhether an interrupt request is for transmitting or receiving
MRESET
data.
Manufacturing Reset. For manufacturing use
RliV
Rrnn
RXDO THRU RXD7
TXDO THRU TXD7
Ready output indicates when the TCM7BBOB is ready to participate in data-transfer cycles.
Reset input initializes the internal logic.
Receive Data inputs accept asynchronous bitMserial data input streams.
VDDO THRU VDD2
Transmit Data output provides asynchronous bit-serial data output streams.
5-V nominal power supply
VSSO THRU VSS2
Ground reference
~
Write input specifies direction of data transfer on the DlO through DL7 lines.
2-186
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
TCM78808
OCTAL ASYNCHRONOUS RECEIVERITRANSMITTER
functional block diagram
Ri5V-_-Ir--,
TXDO
on--+~
RXDO
WIi--+~
DSRli
DCDO
DLO·DL7
M"
es--+~
TXDI
RXDI
iiRET'-~_ _
DSRI
DCI)f
TXD2
IRO-_-I---'
RXD2
DSli2
IROLNO·IROLN2
ireln
--1
IROTXRX--f--t_ _ _
TXD3
RXD3
~-~~-f-:A:DD:R:E:S:S-,
AO·AS
DECODE
LOGIC
DSR3
I-~,-I
DCD3
TXD4
RXD4
DSR4
DCi54
TXD5
RXD5
DSR5
CLK--'-'.,
DCii!
MRESET'--'-'-I
TXD6
RXD6
...en
..
'S
U
(3
en
C
0
'~
co
U
'2
::::I
E
E
0
U
CD
G)
I-
imi6
DCii6
TXD7
RXD7
DSR8
iiCi5i!
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-187
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
absolute maximum ratings over operating free-air temperature range
Supply voltage, VDD (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 7 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 5 V to 7 V
Input current, II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. - 30 mA to 5 mA
Operating free-air temperature range ...................................... OOC to 70°C
Storage temperature range ................................... ,..... - 65°C to 150°C
NOTE 1: All voltage values are with respect to VSS1 and VSS2.
recommended operating conditions
-t
(1)
CD
n
o
3
3
C
Supply voltage, VOO
High-level input voltage, VIH
UNIT
5.25
V
0.8
V
70
·C
V
0
electrical characteristics over recommended operating free-air temperature range, VDD - 5.25 V (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
UNIT
VOO = 4.75 V,
C\)
VOH
High-level output voltage
IOH for OLO thru OL7 = -1 rnA,
IOH for all other (except
:J
iRO
and
2.4
lil5V)
V
= -2 rnA
VOO = 4.75 V,
(I)
VOL
Low-level output voltage
IOL for OLO thru OL7 = 5.5 rnA,
0.4
V
10
-10
~A
IOl for all other = 3.5 rnA
:::;'
n
c
::+
(I)
MAX
5
2
Operating free~air temperature, T A
:J
(")
NOM
Low-level input voltage, VIL
n'
...0'
MIN
4.75
IIH
High-level input current
VI = 5.25 V
IlL
low-level input current
VI = 0
lost
I OLO-OL7
Short-circuit
outputs
output currenttl All other
_
__
except IRQ and ROY
IOZHt
IOZLt
Off-state output current,
high-level voltage applied
Off-state output current,
low-level voltage applied
Supply current
100
Ci
Input capacitance
Cio§
Input/output capacitance
VOO = 5.25 V
-50
-180
-30
-110
rnA
Vo = 2.4 V
-10
Vo = 0.4 V
10
~
240
rnA
4
pF
5
pF
VOO = 5 V,
TA = 25·C
-
t Not more than one output should be short circuited at a time, and the duration of the short should not exceed 1 second.
:t: All 3-state output drivers are wired in an 110 configuration. The parameters include the driver and receiver input currents.
§ This parameter includes the capacitive loads of the output driver and the receiver input.
2-188
~A
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
~
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
bus read and write timing requirements (see Figures 3 and 41
r-'.-----'
PA~~METER __.____ .. _____ ... _ _ _ r-!EST CO"NDITIO~~r_~-
_. __,____ .. _ _.._
W~...~igh
twl
Pulse duration, DS1/DS2 low
tw2
Pulse duration, DS1/DS2 high
~-
Pulse duration, ~/i5S2 low
WRlow
Setup time, A5-AO valid before
tsu2
Setup time,
t5u3
Setup time,
tsu4
Setup time,
thl
r--'-'-'-"
th2
th3
th4
tv
'--"- ..
..
-
Hold time, A5-AO valid after DSl and DS2
Hold time.
WJ!i
high or low after ~ and
Hold time, ~ high after
DS2
DS1 and DS2
Hold time, DL7-DLO valid after DSl and
Valid time, DL7-DLO after
D!IT and
MAX
10
450
D!IT and DS2
WR high before D!IT and i5S2
~ low before D!IT and i5S2
DL7-DLO valid before ~ and i5S2
tsu1
0.1 B
i5S2 high
DS2 high
0.13
UNIT
~s
ns
10
~
30
ns
30
ns
30
ns
0
ns
10
ns
10
ns
10
ns
30
ns
0
ns
...en
·S
...CJ
(3
en
write switching characteristics (see Figures 3 and 41
PARAMETER
ten
tdis
C
TEST CONDITIONS
Enable time
MIN
CL=150pF
Disable time
tpdl
Propagation delay time, from ~ low to
tpd2 t
Propagation delay time. from
CS high
tpd3
Propagation delay time, from
tpd4t
Propagation delay time, from
D!IT and i5S2 low to DL7-DLO
D!IT and i5S2 low to iRQ high
ROY
low
to ROY high
valid
MAX
UNIT
165
ns
CL = 50 pF
50
CL = 100 pF
60
CL-150pF
65
o
',t::
as
c
,~
ns
CL = 50 pF
90
ns
CL = 50 pF
210
ns
CL=150pF
165
ns
CL = 50 pF
635
ns
::l
E
E
o
CJ
Q)
"i
I-
t Total rise time is dependent upon internal delay plus the pull-up delay introduced by the external resistor being used. Parameter tpd2
is calculated from tpd2 = 500 RCL, and tpd4 is calculated from tpd4 = 75 + RCL where R = value of the resistor that connects to
CL in Figure 1.
write timing requirements (see Figure 51
PARAMETER
TEST CONDITIONS
fclock Clock frequency
Pulse duration, clock high or low
tw4
tw5
Pulse duration, RESET low
MIN
4.9
MAX
UNIT
MHz
95
ns
1
1'5
1
I's
250
ns
tw6
Pulse duration, DCD7-DCDO and DSR7-DSRO high or low
tw7
Pulse duration, TXD7-TXDO high or low
tsu5
Setup time, OS 1 and
th5
Hold time,
tdl
Delay time, IROLN2-IROLNO and IROTXRX valid to iRQ low
CL = 50 pF
100
ns
td2
Hold time, IROLN2-IROLNO and IROTXRX valid after iRQ high
CL = 50 pF
100
I's
DS1
and
i5S2 high before RESET
i5S2 high after RESET
low
..
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
900
ns
1
I's
2-189
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PARAMETER MEASUREMENT INFORMATION
. TEST
POINT
VDD
S1
FROM _ _--~~--_~--....- - - -..
OUTPUT
VDD
1 kll
-f
~
FROM
1 kll
OUT~T~~--~~---'~--~----·
r
CD
(')
o
3
3
c
:I
c:r
FIGURE 1. STANDARD OUTPUT LOAD CIRCUIT
'i
S1 closed: Pull-up
S2
S2 closed: Pull-down
S1 and S2 closed: Divider ..,.
FIGURE 2. 3-STATE OUTPUT LOAD CIRCUIT
Q)
o·
pot.
:I
(I)
(")
~.
AO-A5
c
::;."
(I)
~
:
tsu1~
--JA
l
VALID ADDRESS
I
"..
tll~'-
II ~---------------
II
tsu3~ I
II '1
I i.-.Lth3
I
I \11
I I(
I
I
tpd1~ I
II
I
I
I
I
'I
(4-tpd2-+1
----~I~I__I~(2VA~L~ID~D~A~T!A~O~UT!:~)r--------------II
I
ten-1;--+ll
tp
iRa
________________
-tt I4-th2
II
DLO-DL7
--IX\.______
II
II
i
~'-
I r++t-th1
It
I
II
tsu2~ I
WR _ _
"'" ~
I: _________
d3--t+-+1
II
I*-tv-+ll
k- tdi.-+I
---~:r-----'/I
(+-tpd4-+1
FIGURE 3. BUS READ CYCLE TIMING WAVEFORMS
2-190
TEXAS . "
'NSTRUMENlS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PARAMETER MEASUREMENT INFORMATION
t:144-----tw2------.t.~'-----
:\
I I4---tw3----tJ I
-J~
AO-A5 _ _ _
: : VALID ADDRESS
t.u1~ I
Wii ---~\ I I
-t'
tau2-+t ~
--~\
II
-tI
tsu3 14
.1 I
----~I--, I
I
I4[-th3
II
) I
I
tpdl--l.---.1
J4- th2
II !I~i- - - - - - - - - - - - II I I
II
I
~'---------'X'-------
I I+-'*--th1
I
I I ,,--------------II I
II
I
I:
i~-----------------
I
II
I
I I
14
':
~
I
i I4-th4--.1
I !+--t
ou4--.1
CJ
(3
c
o
"j;
CJ
------+1--'1:
:::::I
k-+l-tpd4
FIGURE 4_ BUS WRITE CYCLE TIMING WAVEFORMS
\___r -
I
I
.
"2
I
CLK~
U)
U)
tpd2
DL~DL7--------11~(:::]V~AL~ID~D~j~~A~INc:~)~------------------iiiQ
...
"S
E
E
o
CJ
CI)
Gi
I-
I
j4-tw4-+t
-------""""'X,.....---...;;;;=;.;.....--------X
~I------------t,~----om ---------fl--....,
fI~I----II----I
~I-------J
CLOCK
IROLN2-IROLNO.
IROTXRX
__
I.-td1-+t
I4-td2-.1
INTERRUPT
Iimf
~~----------------t
I
~
'4
liSf-DH
.,1
tw5
.,1\
II
/I
1414- - - -taus
~S
.1'4
EFFECT OF RESET ON DATA STROBE
~-IR957. ------""""'X,---':':'VA::':'L:::ID-:D::::CD=-.":'DS::R:-::D::':'A=:TA~-"'X,------------
DIlm-15lII7
TXDO-TXD1
I
I
1144-----t w6------.r.,
~----------
\~----~~
I
I
I4--tw7
~~----~,--I
., 14--tw7-------r
..
TRANSMIT DATA OUTPUT
FIGURE 5_ MISCELLANEOUS SIGNAL TIMING
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-191
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PARAMETER MEASUREMENT INFORMATION
f-----\-----2V
INPUT
INPUT
STROBE
- - 2 V
:~-----0.8V
Isu
,
CD
CD
n
o
3
3
__+,_
OUT·Of·PHASE
OUTPUT
, I+-+t-Ih
I+--+i-Ih
I 14-* Isu ,
---tof+I
~:~: )(
-t
-.r--:::::
~.- -
,
J:-----\-----0.8V
,
IpLH
X }== :.:
I
I
:
I
I
I
I
V
\
r
VO (2V)
-
.1 IPHL-I:.4--(.~1
14
IN·PHASE
OUTPUT
/
-----.J
SETUP AND HOLD
\LT-
Vo (0.8 V)
VO(2V)
Vo 10.8 V)
PROPAGATION DELAY
NOTE: tpd
c::
I
= tpLH or IPHL
FIGURE 6. VOLTAGE WAVEFORMS
j
(;'
Q)
....
PRINCIPLES OF OPERATION
0'
j
til
electrical operation
(")
data and address
n
c::
data lines (OL7 through OLO)
::;'
;:;:
These lines are used for the parallel transmission and reception of data between the CPU and the TCM78808.
The receivers are activated by the data strobe (OS 1. OS2) signal. The output drivers are active only when
the chip select (CS) signal is low (active). the data strobe (OS 1. OS2) signal goes low (active). and the
write (WR) signal is high (inactive). The drivers will become inactive (high impedance) within 50 ns when
one or more of the following occurs: the chip select (CS) signal goes high. the data strobe (OS 1. OS2)
goes high. or the write (WR) signal goes low.
til
address lines (A5 through AO)
These lines select which internal register is accessible through the data I/O lines (OL7 through OLD) when
the data strobe (OS1. OS2) and chip select (CS) signals are low. Table 1 lists the addresses corresponding
to each register. The receiver buffer and transmitter holding register for each line have the same address.
When the (WR) signal is high. the address accesses the receiver buffer register. When WR is low. it accesses
the transmitter holding register.
2-192
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
TABLE 1. TCM78808 REGISTERS ADDRESS SELECTION
ADDRESS LlNEt
READ/
AS
A4
A3
A2
Al
AO
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
L
L
L
H
H
L
H
L
H
L
L
L
L
L
L
L
L
L
L
L
H
H
L
L
H
H
L
L
L
H
H
H
L
L
L
H
H
H
H
H
L
L
H
H
H
L
L
H
L
L
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
L
L
L
H
H
H
L
L
H
H
H
H
H
H
H
H
H
H
X
X
tx
L
L
H
H
H
L
L
L
L
H
H
L
L
L
L
L
L
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
REGISTER
WRITE
Read
Line 0 Receiver Buffer
Write
Line 0 Transmitter Holding
Read
Read/Write
Read/Write
Read
Line 0 Status
Line 0 Mode Registers 1 and 2
Write
Read
ReadIWrite
Line 0 Command
Line 1 Receiver Buffer
Line 1 Transmitter Holding
Line 1 Status
Line 1 Mode Registers 1 and 2
H
L
ReadIWrite
Read
Line 2 Receiver Buffer
L
L
L
H
Write
Line 2 Transmitter Holding
H
H
L
L
H
Read
Read/Write
Read/Write
L
L
Read
Line
Line
Line
Line
Write
Line 3 Transmitter Holding
Read
Read/Write
Line 3 Status
Line 3 Mode Registers 1 and 2
Line 3 Command
Line 4 Receiver Buffer
Line 4 Transmitter Holding
L
L
H
Line 1 Command
2
2
2
3
Status
Mode Registers 1 and 2
Command
Receiver Buffer
H
H
L
L
H
L
L
Read/Write
Read
Write
H
L
H
Read
Read/Write
Read/Write
Line 4 Status
L
L
H
H
L
L
L
L
L
L
Read
Line 5 Receiver Buffer
Line 5 Transmitter Holding
H
H
L
L
H
L
L
L
L
L
H
H
H
L
H
L
L
L
H
L
L
L
H
H
H
L
L
L
H
H
H
L
H
H
H
X
H
H
H
X
X
X
L
L
L
H
H
L
L
L
L
L
H
H
L
L
L
H
H
L
L
L
Write
Line 4 Mode Registers 1 and 2
Line 4 Command
Read
Line 5 Status
ReadIWrite
Read/Write
Read
Line 5 Mode Registers 1 and 2
Line 5 Command
Line 6 Receiver Buffer
Write
Read
Read/Write
Line 6 Transmitter Holding
...
"S
U)
..
C3
u
U)
c
o
"+:
ca
U
"c::::I
E
E
o
u
Ci)
"i
....
Line 6 Status
Line 6 Mode Registers 1 and 2
H
L
L
Read/Write
Read
Line 6 Command
Write
Line 7 Transmitter Holding
H
L
H
Read
Read/Write
ReadIWrite
Line 7 Status
L
H
Read
Read
Line 7 Receiver Buffer
Line 7 Mode Registers 1 and 2
Line 7 Command
Interrupt Summary
Data Set Change Summary
= Either L or H
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-193
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
bus transaction control
chip select (es)
This signal, when low, permits data transfers through the DL7 through DLO lines to or from the internal
registers. Data transfer is controlled by the data strobe (DS 1, DS2) signal and the write (WR) signal.
data strobe (OS " OS2)
The data strobe inputs (DS 1 and DS2) must be connected together. This input receives timing information
for data transfers. During a write cycle, the CPU activates the data strobe signal when valid output data
is available and deactivates the data strobe signal before the data is removed. During a read cycle, the
CPU activates the data strobe signal, and the TCM78808 transfers the valid data.
-I
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3
3c
When the data strobe signal is high, the DL7 through DLO lines are in a high-impedance state.
write (WR)
The write (WR) signal specifies the direction of data transfer on the DL 7 through DLO pins by controlling
the direction of their transceivers. If the WR signal is low during a data transfer (with the CS, DS1, and
DS2 signals also low), the TCM78808 receives data from DL7 through DLO. If the WR signal is high during
a write data transfer, the TCM78808 drives data onto the DL7 through DLO lines.
::s
C:;'
....
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S'
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en
Interrupt request (IRQ)
The IRQ output is an active-low, open-drain output. The integral interrupt scanner drives the IRQ signal
low when it has detected an interrupt condition on one of the eight serial data lines.
(")
::::;'
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interrupt request transmit/receive (lRQTxRx)
::;.'
This signal indicates when the interrupt scanner stops and activates IRO because of a transmitter interrupt
condition (lRQTxRx = H) or because of a receiver interrupt condition (lROTxRx = L). The signal is valid
only while the IRO signal is low. The state of IROTxRx signal also appears as bit 0 of the interrupt summary
register.
en
interrupt request Nne number (IROLN2 through IROLNO)
These lines indicate the line number at which the TCM78808 interrupt scanner stopped and activated
the interrupt request (lRO) signal. The number on these lines is valid only while the IRO signal is low. Line
IROLN2 is the high-order bit, and the IROLNO line is the low-order bit.
The state of these signals also appears as bits in the interrupt summary register: IROLN2 as bit 3, IROLN1
as bit 2, and IROLNO as bit 1. Table 2 shows the line numbers corresponding to settings of IROLN2 through
IROLNO.
2-194
TEXAS ...,
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TeXAS 75265
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
TABLE 2. TCM78808 INTERRUPT REQUEST
LINE INDICATIONS
IRQLN2
IRQLN1
IROLNO
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
l
H
INTERRUPT REQUEST
LINE NUMBER
0
1
2
3
4
5
...
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6
'S
7
u
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serial data
CI)
transmit data (TXD7 through TXDO)
c:
These outputs transmit the asynchronous bit-serial data streams. They remain at a high level when no
data is being transmitted and at a low level when the TxBRK bit in the command register of the associated
line is set.
receive data (RXD7 through RXDO)
These lines accept asynchronous bit-serial data streams. The input signals must remain at the high level
for at least one-half bit time before a high-to-Iow transition is recognized. A high-to-Iow transition is required
to signal the beginning of a start bit and initiate data reception.
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modem signals
I-
data set ready (DSR7 through DSRO)
These eight inputs, one for each serial data line on the TCM78808, are typically connected via intervening
level converters to the data set ready outputs of modems. A TTL low at a DSR pin causes the DSR bit
(bit 7) in the status register of the corresponding line to be activated. A TTL high at a DSR pin causes
the DSR bit in the status register of the corresponding line to be inactive. A change of this input from
high to low or low to high causes the activation of the data set change (DSCHNG) bit that corresponds
to this line in the data set change summary register. Changes from one level to the other and back again
that occur within 1 p's may not be detected.
carrier detect (DCD7 through DCDO)
These eight inputs, one for each serial data line of the TCM78808, are typically connected through
intervening level converters to the received-line-signal-detect (also called carrier-detect) outputs of modems.
A TTL low at a DCD input causes the DCD bit of the corresponding line status register to be deactivated.
A change of this input from high to low or low to high causes the activation of the data-set-change
(DSCHNG) bit that corresponds to this line in the data-set-change summary register. Changes from one
level to the other and back again that occur within 1 P.s may not be detected.
TEXAS ..,
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-195
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
general control signals
I'8IIdy (ROY)
The ROY output is an open-drain output. Upon detecting a negative transition of CS, the TCM78808
activates the ROY signal to indicate readiness to take part in data transfer cycles. The ROY signal deactivates
on the trailing edge of es.
reset (RESET)
When the RESET input goes low, the tx07 through TxOO lines are low, and all internal status bits listed
in the Architecture Summary paragraph are cleared.
-I
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menufacturing reset (MRESET)
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o
This signal is for manufacturing use only. The input should be connected to ground for normal operation.
3
3
clock signals
§
clock input (eLK)
(;'
All baud rates and internal clocks are derived from this input. Normal operating frequency is 4.9152 MHz
±0.1%, and duty cycle is 50 ±5%.
!
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::::II
architecture summary
n
line-specific registers
tJ)
~.
Each of the eight serial data lines has a set of registers for buffering data into and out of the line and for
external control of the line characteristics. These registers are selected for access by setting the appropriate
address on lines A5 through AO. Lines A5 through A3 select one of the eight data lines. Lines A2 through
AO select the specific register for that line. Refer to Table 1 for the register address assignments.
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receiver buffer register
Each line receiver consists of a character-assemblY register and a two-entry FIFO that is the receiver buffer
register. When the RxEN bit in a line command register is set, received characters are moved automatically
into the line receiver buffer as soon as they have been deserialized from the associated communications
line. When there are characters in this FIFO, the RxROY bit is set in the status register for the line.
The activation of the RxROY signal for a line that already has the RxlE bit of its command register set
causes the interrupt scanner logic to stop and generate an interrupt condition (the IRQ signal is low). When
the receiver buffer is read, the interrupt condition is cleared (the IRQ signal is high), and the interrupt scanner
resumes operation.
If there is another entry in a line FIFO, the RxROY bit remains active. When the interrupt scanner reaches
this line again, the activation of RxROY causes the scanner to halt and generate another interrupt (IRQ
goes low).
The RESET signal clears the RxEN bit and initializes the receiver logic. The RxROY flag is cleared, and the
receiver buffer register outputs become undefined. Any data in the FIFO at that time is lost.
2-196
TEXAS
II
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TCM78BOB
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
transmittar holding register
Each line has a transmitter holding register that can be written to. When the TxEN bit in the line command
register is set and the serialization logic becomes idle, characters are automatically moved from the output
of this register into the transmitter serialization logic.
When this register is empty, the TxRDY bit in the line status register is set. If the transmitter interrupt
enable (TxIE) bit in the line command register is also set, the interrupt scanner logic halts and generates
an interrupt condition. If a character is then loaded into the register, the interrupt is cleared, and the scanner
resumes operation.
.
The RESET signal also initializes the transmitter logic. The TxRDY flag is cleared, and the transmitter holding
register contents are lost. The transmitter enable (TxEN) bit in the line command register is also cleared
by RESET. Software clearing of TxEN alone produces results different from the full RESET in that the
transmitter holding register contents are not lost. They are transmitted when TxEN is set again.
•..
en
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~
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en
status register
Each line has a read-only status register that provides information about the current state of the given
line. This register indicates the readiness of a line for transmission or reception of data and flags error
conditions in its bit fields. Figure 7 shows the format of the status register. Table 3 lists the flag bits in
each register.
7
6
5
4
3
2
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DSR
DCD-----'
FER _ _ _ _ _ _ _..J
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ORR----------..J
PER - - - - - - - - - - - - - '
TxEMT - - - - - - - - - - - - - - - - - - '
RxRDY -----------------------------'
TxRDY
______________________________________
--..J
FIGURE 7. TCM78808 STATUS REGISTERS (LINE 0 THROUGH 6) FORMAT
TEXAS ,.,
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
2-197
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
TABLE 3. TCM78808 STATUS REGISTERS (LINES 0 THROUGH 7) DESCRIPTION
BIT
7
6
5
4
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3
CD
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3
2
3
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0
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i5Sl! line.
DCD (Data Set Carrier Detect). This bit is the inverted state of the DCD line.
FER (Frame Error). Set when the received character currently displayed in the receiver buffer register was not framed by • stop
bit. Only the first stop bit is checked to determine that a framing error exists. Subsequent reading of the receiver buffer register
that indicates all zeros (including the parity bit, if any) can be interpreted as a Break condition. This bit is cleared by clearing
RxEN (bit 2) of the command register, by RESET, or by setting the reset error RERR (bit 4) of the command register.
ORR (Overrun error). Set when the character in the receiver buffer was not read before another character was received. Cleared
by clearing RxEN (bit 2) of the command register, by REm, or by setting reset error RERR (bit 4) of the command register.
PER (Parity Error). If parity is enabled and this bit is set, the received character in the receiver buffer register has an incorrect
parity bit. This bit is cleared by clearing RxEN (bit 2) of the command register, by ~, by setting reset error RERR (bit 2)
of the command register, or by reading the current character in the receiver buffer register.
TxEMT (Transmitter Empty). Set when the transmitter serialization logic for the associated line has completed transmission of
a character, and no new character has been loaded into the transmission holding register. Cleared by loading the transmitter
holding register, by clearing TxEN(O) of the command register, or by ~.
RxRDY (Receiver Buffer Ready). When set, a character has been loaded into the FIFO buffer from the deserializetion logic. Cleared
by reading the receiver buffer register, by clearing RxEN (bit 2) in the command register, or by 'RESET.
TxRDY (Transmitter Holding Register Ready). When set, this bit indicates that the transmitter holding register is empty. Cleared
when the program has loaded a character into the transmitter holding register, when the transmitter for this line is disabled by
clearing TxEN (bit 0) in the command register, or fIE!!rT. This· bit is initially set when the transmitter logic is enabled by the setting
of the TxEN (bit 0) and the transmitter holding register is empty. This bit is not set when the automatic echo or remote loopback
o::;'
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DESCRIPTION
~ (Data Set Ready). This bit is the inverted state of the
modes are programmed. Data can be overwritten if a consecutive write is performed while TxRDY is cleared.
mode registers 1 and 2
en
These read/write registers control the attributes (including parity, character length, and line speed) of the
communications line.
Each of the eight communications lines has two of these registers, both accessed by the same address
on A5 through AO. Successive access operations (either read or write, in any combination) altemate between
the two registers at that address by use of an internal pointer. The first operation addresses mode register 1.
The pointer is reset to point to mode register 1 by RESET or by a read of the command register for this
line. These registers should not be accessed by bit-oriented instructions that do read/modify/write cycles
such as the PDP-11 BIS, BIC, and BIT instructions.
Figure 8 shows the format of mode registers 1, and Table 4 describes the function of the register
information.
7
6
4
5
3
2
o
.
STOP
----.J
PAR CTRL --------~
CHARLENGTH---------------~
RSRV ------------------~
MCIE - - - - - - - - - - - - - - - - - - - - - - - - '
FIGURE 8. TCM78808 MODE REGISTERS 1 (LINE 0-6) FORMAT
2-198
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
TABLE 4. TCM78808 MODE REGISTERS 1 (LINES 0 THROUGH 6) DESCRIPTION
BIT
7,6
DESCRIPTION
STOP. These bits determine the number of stop bits that are appended to the transmitted characters as follows. These bits
are cleared by
5,4
3,2
iiESft'.
Bit 7
Bit 6
Stop Bits
L
L
H
L
H
L
Invalid
H
H
Ell
...
..
1.0
1.5
2.0
II)
PAR CTRL (Parity cantrall. These bits determine parity as follows and are cleared by ~. (X = either H or L)
Bit 5
Bit 4
H
L
H
H
'3
u
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Parity Type
Even
Odd
X
L
Disabled
CHAR LENGTH (Character length). These bits determine the length (excluding start bit. parity. and stop bits) of the characters
II)
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received and sent. Received characters of less than 8 bits are "right aligned" in the receiver buffer with unused high-order
'';:
bits equal to zero. Parity bits are not shown in the receiver buffer. The character length bits are cleared by iiESft'. The character
length bits ar. defined as follows:
1
0
Bit 3
Bit 2
Bit Length
L
L
H
H
L
5
6
7
H
L
H
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u
'2
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E
E
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8
CI)
RSRV. Reserved and cleared by~.
MCIE (Modem control interrupt enable). When set and RxlE Ibit 5) of the command register is set. the modem control interrupts
G)
~
are enabled. Refer to the interrupt Scanner and Interrupt Handling informstion. Cleared by ~.
Figure 9 shows the format of mode registers 2, and Table 5 indicates the baud rate selections of the register.
Bits 7 through 4 of mode register 2 control the transmitter baud rate. and bits 3 through 0 control the
receiver baud rate. These registers are cleared by RESET.
7
5
6
4
3
2
o
XMIT RATE - - - - - - - '
RECV RATE - - - - - - - - - - - - - - - - - - '
FIGURE 9. TCM78808 MODE REGISTERS 2 (LINE 0 THROUGH 6) FORMAT
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-199
TeM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
TABLE 5. TCM78808 MODE REGISTERS 2
(LINES 0 THROUGH 6) DESCRIPTION
BIT
7·0
DESCRIPTION
XMIT RATE/RECV RATE (Transmitter/Receiver Ratel. Selects the baud rate of the
transmitter (bits 7 through 4) and receiver (bits 3 through 0) as follows:
Nominal
Actual
Errort
Rate
Rate
(percent)
50
same
75
same
-
110
109.09
0.826
134.5
133.33
0.867
150
same
300
same
L
600
same
H
1200
same
-
L
1800
1745.45
3.03
L
H
2000
2021.05
1.05
L
H
L
2400
same
-
H
L
H
H
3600
3490.91
3.03
L
H
H
L
L
4800
same
-
H
H
H
L
H
7200
6981.81
3.03
L
H
H
H
L
9600
same
H
H
H
H
H
19200
same
-
Transmitter Bits
7
6
L
L
L
L
L
L
L
L
H
L
L
H
L
H
L
L
H
L
L
H
L
H
H
5·
S·
;:,
Receiver Bits
3
2
1
L
L
L
L
L
H
L
L
L
H
L
L
L
H
L
H
L
L
H
H
L
L
H
L
L
H
L
H
L
H
H
L
L
H
H
H
H
L
H
H
L
L
L
H
L
L
H
L
L
H
H
L
m
....
H
L
H
L
H
H
L
H
H
H
H
L
o
H
H
L
H
H
H
H
H
H
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3
3
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5
4
0
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t The frequency of the clock input (eLK) is 4.9152 MHz. The clock input may vary by 0.1 %. This
variance results in an error that must be added to the error listed in the error column.
command register
These read/write registers control various functions on the selected line. Figure 10 shows the format of
the command registers, and Table 6 describes the function of the register information.
7
5
6
4
3
2
o
..1
RxlE _ _ _ _ _ _ _
RERR - - - - - - - - - - - '
TxBRK - - - - - - - - - - - - - - - - '
RxEN ----------------~
TxlE _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.J
TxEN
-----------------------....1
FIGURE 10. TCM78808 COMMAND REGISTERS (LINE 0 THROUGH 6) FORMAT
2-200
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
TABLE 6. TCM78808 COMMAND REGISTERS CLINES 0 THROUGH 71 DESCRIPTION
BIT
DESCRIPTION
7,6
OPEA MODE IOperation Mode). These bits control the operating mode of the channel as follows. These bits are cleared by REm.
Bit 7
Bit 6
Operating Mode
L
L
Normal operation
4
L
H
Automatic echo
H
L
Local loopback
H
H
Remote loop back
AxlE (Aeceiver Interrupt Enable). When set, the AxRDY flag (bit 1) of the status register for this line will generate an interrupt.
REAA (Aeset Error). When set, this bit clears the framing error, overrun error, and parity error of the status register associated
3
with this line. This bit is cleared by ~. It is not self-clearing.
TxBRK (Transmit Break). When set, this bit forces the appropriate TxD7-TxDO line to the spacing state at the conclusion of
5
2
....
tI)
'S
~
the character presently being transmitted. When the program clears this bit, normal operation is restored, and any character
(3
pending in the transmitter holding register is moved into the serialization logic and transmitted. The minimum break length
obtainable is twice the character length plus 1 bit time. The maximum break length depends on the amount of time between
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o
the program setting and clearing this bit, but is an integral number of bit times. This bit is cleared by REm.
AxEN (Aeceiver Enable). When set, this bit enables the receiver logic. When cleared, it stops the assembling of the received
'~
as
character, clears all receiver error bits and the AxADY (bit 1) of the status register, clears any receiver interrupt conditions
associated with this line, and initializes all receiver logic. This bit is cleared by ~.
1
0
(,)
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TxlE (Transmit Interrupt Enable). When set, the state of the associated TxADY flag (bit 0) of the status register is made available
to the interrupt scanner logic. When the interrupt scanner logic scans this line, it datermines if the TxADY flag is set and,
E
E
if so, generates an interrupt.
TxEN (Transmitter Enable), When set, this bit enables the transmitter logic. When cleared, it inhibits the serialization of the
characters that follow, but the serialization of the current character is completed. It also clears the TxADY flag (bit 0) of the
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status register, clears any transmitter interrupt conditions associated with the transmitter holding register, and initializes all
CD
transmitter logic except that associated with the transmitter holding register. The character in the transmitter holding register
is retained so that XON/XOFF situations can be properly processed. This bit is cleared by RrnT.
I-
Bits 5 through 0 enable the line receiver and transmitter, enable handling of interrupts, initiate the
transmission of break characters, and reset error bits for the line. Refer to the "Interrupt Scanner and
Interrupt Handling" paragraphs for detailed interrupt information. Bits 7 and 6 control the operating mode
of the line. The four modes that can be set are normal operation, automatic echo, local loopback, and
remote loopback.
normal operation
The serial data received is assembled in the receiver logic and transferred in parallel to the receiver buffer
register. The RxEN bit must be set. Data to be transmitted is loaded in parallel into the transmitter holding
register, then automatically transferred into the transmitter logic and serialized for transmission. The TxEN
bit must be set.
automatic echo
The serial data received is assembled into parallel form in the receiver logic (the RxEN bit must be setl
and transferred to the receiver buffer register. Arriving serial data is also routed to the line's TxDn pin
for serial output. TxEN is ignored, and the transmitter logic is disabled. TxRDY flags and TxEMT indications
are cleared. No transmitter interrupts are generated.
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-201
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
/oca//oopback
The serial data from the RxDn input is ignored. and the receiver serial input receives data from the transmitter
serial output. That data is assembled into parallel form in the receiver logic (the RxEN bit must be set)
and transferred to the receiver buffer register where it can be read by the program. Data to be transmitted
to the receiver is loaded in parallel form into the transmitter holding register from which it is automatically
moved into the transmitter logic and serialized for transmission. The TxEN bit must be set. The transmission
goes only to the receiver serial input; the TxDn output is held high. As in normal operation. transmission
and reception baud rates are controlled by the transmitter speed and receiver speed entries in mode
register 2.
-t
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cr
remote /oopback
The serial data received on the RxDn line is returned to the TxDn line without further action. No data is
received or transmitted. The RxRDY. TxRDY. and TxEMT flags are disabled. The TxEN and RxEN bits of
the command register are held cleared. causing the transmitter and receiver logic to be disabled.
(')
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3
3
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summary registers
n"
I»
....
The TCM78808 contains two registers that summarize the current status of all eight serial data lines. making
it possible'to determine that a line status has changed with a a single read operation. These registers are
selected for access by setting the appropriate address on inputs A2 through AO. Because the registers
are shared by eight serial lines, the line-selection bits A5 through A3 are ignored when these registers
are accessed. Refer to "Interrupt Scanner and Interrupt Handling" for detailed interrupt information.
0"
:::s
en
(')
~"
interrupt summary register
c:
;::;.en
This read-only register indicates that a transmitter or receiver interrupt condition has occurred and indicates
the line number that generated the interrupt. Figure 11 shows the format of the interrupt summary register.
and Table 7 describes register information.
7
6
5
4
3
2
o
IRQ
RAZ------~
INT LINE N O - - - - - - - - - - - - - - - - . . 1
Tx/Rx-----------------------------------------~
FIGURE 11. TCM78808 INTERRUPT SUMMARY REGISTER FORMAT
2-202
TEXAS . "
INSTRUMENlS
POST OFFICE BOX 855012 • DALLAS, TeXAS 75265
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
TABLE 7. TCM78808 INTERRUPT SUMMARY REGISTER DESCRIPTION
. DESCRIPTION
BIT
IRQ !Interrupt Request). When set. this bit indicates that the interrupt scanner has found an interrupting condition among
7
6,5,4
3,2,1
t
the eight serial lines of the TCM78808. These conditions also result in activating the IRQ signal.
RAZ (Read as Zero). Not used
INT UNE NO !Interrupting Line Number). These bits indicate the line number upon which an interrupting condition was found.
These bits correspond to the IRQLN2·IRQLNO signals: bit 3 = IRQLN2. bit 2 = IRQLN1, and bit 1 = IRQLNO. See Table 2.
ot
t Bits
Tx/Rx (Transmit/Receive). This bit indicates whether the interrupting condition was caused by a transmitter (Tx/Rx = I)
or a receiver (Tx/Rx = 01. This bit corresponds to the IRQTxRx signal of the TCM78808 and is set when IRQTxRx Is set.
rn
'5
+J
..
3~O above represent the outputs of a free-running counter and are valid only when bit 7 is set.
7
5
6
3
4
2
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o
(3
rn
C
-
o
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ca
CJ
'2
---11
DSCHNG 7.0 _ _ _ _ _ _ _ _ _ _ _
FIGURE 12. TCM78808 DATA SET CHANGE SUMMARY REGISTER FORM
::I
When the MCIE bit in a line mode register 1 is set and RxlE is also set, the modem control interrupts are
enabled for that line. If DSCHNG for that line is then set, the interrupt scanner will halt and generate an
interrupt. The data set change summary register bits are cleared by writing a high into the bit position.
A program that uses this register should read and save a copy of its contents. The copy can then be written
back to the register to clear the bits that were set. The system interrupts should be disabled, and writeback
should directly follow the read operation.
E
E
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G)
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The RESET signal disables and initializes the data set change logic. When the RESET signal is high, future
changes in DSR and DCD ere reported as they occur.
interrupt scanner and interrupt handling
The interrupt scanner is a 4-bit counter that sequentially checks lines 0 through 7 for a receiver interrupt
(counter positions 0 through 7) and then checks the lines in the same order for a transmitter interrupt
(counter positions 8 through 15). If the scanner detects an interrupt condition, it stops, and the iRQ signal
goes low. An interrupt must be serviced by software, or no other interrupt request can be posted.
The scanner determines that a line has a receiver interrupt if the line receiver buffer is ready and receiver
interrupts are enabled for that line (RxRDY and RxlE = H) or if either of the line modem status signals
has changed state and both receiver and modem control interrupts are enabled for that line (DSCHNG,
RxIE, and MCIE all high).
The scanner determines that a line has a transmitter interrupt if the line's transmitter holding the register
is empty and transmitter interrupts are enabled for that line (TxRDY and TxlE both high).
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-203
TCM78808
OCTAL ASYNCHRONOUS RECEIVER/TRANSMITTER
PRINCIPLES OF OPERATION
When the scanner detects an interrupt, it reports the line number on the IRQ2-IRQO lines. The IRQTxRx
signal is high for a transmitter interrupt and is low for a receiver interrupt. The appropriate bits are also
updated in the interrupt summary register. The IRQ line goes high, and the scanner is restarted for each
of the following three types of interrupt conditions:
1. Reading the receiver buffer or resetting the RxlE bit of the interrupting line for the first type of
receiver interrupt previously described.
2. Resetting the MCIE, RxlE, or DSCHNG bit of the interrupting line for the second type of receiver
interrupt previously described.
3. Loading the transmitter holding register or resetting the TxlE bit of the interrupting line for transmitter
interrupts.
-I
CD
i"
If the scanner was originally stopped by a receiver interrupt condition, the scanner resumes sequential
operation from where it stopped, thus providing receivers with equal priority. If the scanner was stopped
by a transmitter condition, the scanner restarts from position 0 (line receiver), thus giving receivers priority
over transmitters.
(')
o
3
3
C
::l
n'
edge-triggered and level-triggered interrupt systems
CI)
g'::l
If the interrupt system of the TCM78808 is used only for generating interrupts for the RxRDY and/or TxRDY
flags, the IRQ line can be connected to a processor having either edge-triggered or level-triggered interrupt
capability. If the modem control interrupts are being used (MCIE in mode register 1 = 1), the IRQ line
can be connected only to a processor that uses level-triggered interrupts.
(II
(') modem handling
::;'
(')
C
::+
(II
The TxEMT (transmitter empty) bit of the status register is typically used to indicate when a program can
disable the transmission medium, as when deactivating the request-to-send line of a modem. A typical
program will load the last character for transmission and then monitor the TxEMT bit of the status register.
The setting of the TxEMT bit to indicate that transmission is complete may occur a substantial time after
the loading of the last character. After the last character is loaded, one character is in the transmitter holding
register, and one character is in the serialization logic. Therefore, it will be two character times before
the transmission process is completed. Waiting for the TxRDY signal to be set before monitoring the TxEMT
status shortens this by one character time because the TxRDY status bit indicates that there are no
characters in the transmitter holding register. The times involved are calculated by taking the reciprocal
of the baud rate being used, multiplying by the number of bits per character [a start bit - 5, 6, 7, or 8
data bits (plus parity bit if enabled) and 1, 1.5, or 2 stop bits], and multiplying by either two characters
or one depending on when TxEMT monitoring begins;
2-204
TEXAS
.Jf
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TIL181
OPTOCOUPLER
02906. OCTOBER 19B5- REVISED MARCH 1988
COMPATIBLE WITH STANDARD TTL INTEGRATED CIRCUITS
•
Gallium Arsenide Diode Infrared Source Optically Coupled to a Silicon N-P-N
Phototransistor
•
High Direct-Current Transfer Ratio
•
High-Voltage Electrical Isolation .
. 2.5 kV rms (3.535 kV peak)
•
Plastic Dual-In-Line Package
•
High-Speed Switching: tr - 2,..s Typ. tf - 2,..s Typ
•
UL Recognized -
•
Primarily Used with Telephone Ring Detector TCM1520A and Tone Drivers
TCM1501B. TCM1506B. TCM1512B. TCM1531. TCM1532. TCM1536.
and TCM1539
File # E65085
...
U)
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CJ
"~
(J
mechanical data
The package consists of a gallium arsenide infrared-emitting diode and an n-p-n silicon phototransistor
mounted on a 6-pin lead frame encapsulated within an electrically nonconductive plastic compound. The
case will withstand soldering temperature with no deformation and device performance characteristics
remain stable when operated in high-humidity conditions. Unit weight is approximately 0.52 grams.
E
~
CD ® CD
CU
.~
:::::J
o
CJ
CD
''''NoteBI~
I----~- ::g~ :~:~:g:
o
E
000
,NDEXDOT
C
.~
C
(O'370)~
9.40
8,38 fO.330)
1--____1--7,~:e~O:~~)~.P.
U)
Gi
I-
(See Note C)
5,4610.215)
~
L'O_"_'5_'_~--':-15f 786(~i.~g~sMAX
SEATING PLANE ___--2.-9-'2
1.
--O\V
\
~,
3.81 (0.150)
3.1710.125)
lJ Jl
----.J L
1,78 (0.0701
0,203 (0.0081
I
2.2910.0901
1,2710.0601
4 PLACES
,00
2.54 (0.100) T.P.
(See Note AI
NOTES:
1.01 10.040)
MIN
0.534(0.021)
0,381 (0.0151
6 PlACES
A. Leads are within 0,13 mm (0.005 inch) radius of true pOSition (T.P.) with maximum material
condition and unit installed.
B. Pin 1 identified by index dot.
C. Terminal connections:
1.
2.
3.
4.
5.
6.
Anode
Cathode
No internal connection
Emitter
Collector
Base
Infrared-emitting diode
Phototransistor
FALLS WITHIN JEDEC MD-OD1AM DIMENSIONS
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
PRODueno. DATA d...I1......ntain info,...tio.
••,rent .1 of publication dlllll. P,.da'" ........ to
.pacifioatio.. par th. t• ..,••f TIlUII I••tr.......
:;,=~rirr.f.!~~',J,; =~i:: 1Il"=,:9t::." 001
CP-7
Copyright © 1985, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-205
TIL 181
OPTOCOUPLER
absolute maximum ratings at 25°C free-air temperature (unless otherwise noted)
Input-to-output voltage ................................ . ± 2.5 kV rms (± 3.535 kV peak)
Collector-base voltage .............. .
70 V
Collector-emitter voltage (see Note 1)
.. 30 V
Emitter-collector voltage ....... .
7V
Emitter-base voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7V
Input-diode reverse voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3V
Input-diode continuous forward current at (or below) 25°C free-air temperature
(see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100 mA
Continuous power dissipation at (or below) 25 °C free-air temperature
Infrared-emitting diode (see Note 3) . . . . . . . . . . . . . . . . . . . . . .
1 50 mW
Phototransistor (see Note 4) ...........................
150 mW
Total, infrared-emitting diode plus phototransistor (see Note 5) . .
. . . . . . .. 250 mW
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 260°C
NOTES: 1.
2.
3.
4.
5.
This value applies when the base-emitter diode is open-circuited.
Derate linearly to 100°C free-air temperature at the rate of 1.33 mA/oC.
Derate linearly to lOOoe free-air temperature at the rate of 2 mW/oC.
Derate linearly to 10Qoe free-air temperature at the rate of 2 mW/oC.
Derate linearly to lOQoe free-air temperature at the rate of 3.33 mW/oC.
electrical characteristics at 25°C free-air temperature
PARAMETER
TEST CONDITIONS
VIBR)CBO Collector-base breakdown voltage
VIBR)CEO Collector-emitter breakdown voltage
VIBR)EBO
IR
1 rnA,
18 - 0,
10 ~A,
IC
IE
VR - 3 V
collector
Off-state
collector
current
= 0,
TYP
MAX
70
V
IF - 0
30
V
=0
7
IF
V
10
100
~A
IB
=0
5
rnA
IE
=
7
VCE
= 0.4
V,
IF
=
10 rnA,
VCB
= 0.4
V,
IF
=
16 rnA,
VCE
=
10 V,
IF
= 0,
~B = 0
1
50
VCB
=
10 V,
IF
= 0,
IE
=0
0.1
20
VCE
=
5 V,
Ie
=
10 rnA,
IF
=
0
= 16 rnA
= 5 rnA,
IF
=
10 rnA,
IB
=
0
Photodiode
operation
Phototransistor
operation
~A
IB - 0
VCE - 0.4 V,
operation
IF - 0.8 rnA,
UNIT
=0
IF
Phototransistor
0
20
p.A
nA
Photodiode
operation
Transistor static forward current
hFE
=
IE
Input diode static reverse current
current
ICloff)
IC -
MIN
= 0,
10 ~A,
Emitter-base breakdown voltage
On-state
IC(on)
=
IC
transfer ratio
VF
Input diode static forward voltage
IF
VCE(sat)
Collector-emitter saturation voltage
IC
'10
Input-to-output internal resistance
Vin-out -
Cio
Input-to-output capacitance
Yin-out
±500 V,
= 0,
See Note 6
f
=
200
550
1.2
1.4
V
0.25
0.4
V
1
1.3
pF
0
10"
1 MHz,
See Note 6
NOTE 6: These parameters are measured between both input-diode leads shorted together and all the phototransistor leads shorted together.
switching characteristics at 25°C free-air temperature
PARAMETER
tr
Rise time
tf
Fall time
tr
Rise time
tf
Fall time
2-206
Phototransistor operation
Photodiode operation
TEST CONDITIONS
MIN
=
IC(on) = 2 rnA,
VCC = 10 V,
See Test Circuit A of Figure 1
RL
VCC -
RL - 1 kO,
10 V,
IClon) - 20 p.A,
See Test Circuit B of Figure 1
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
1000,
TYP
MAX
2
10
2
10
UNIT
~s
1
1
~s
TlL181
OPTOCOUPLER
PARAMETER MEASUREMENT INFORMATION
Adjust amplitude of input pulse for:
IC(an) = 2 mA (Test Circuit A) or
IC(an) = 20 I"A (Test Circuit B)
INPUT
o~
47 n
INPUT
r--t'-iie'-''r-'lr-(See Note A)
r-l,,"""""_- OUTPUT
ISe.Note H)
RL
47 n
L
INPUT
(S•• Note AI
' - - - -....-~:~~: HI
= 100n
en
TEST CIRCUIT A
PHOTOTRANSISTOR OPERATION
.t:::
~
u
..
TEST CIRCUIT B
PHOTODIODE OPERATION
VOLTAGE WAVEFORMS
NOTES: A. The input waveform is supplied by a generator with the following characteristics: Zaut = 50 0, tr s 15 ns, duty cycle = 1 %,
tw = 100,"".
B. The output waveform is monitored on an oscilloscope with the following characteristics: tr :!S 12 ns, Rin ~ 1 MD, Cin :s 20 pF.
(3
en
c
o
.';::
CO
FIGURE 1. SWITCHING TIMES
u
·2
~
TYPICAL CHARACTERISTICS
12
600
18=0
TA = 25"C
11
10
IF =
1 mA
500
c(
1400
O.SmA
c3
300
~
200
E
~
j
100
o
o
2
4
6
8
S
IF=I SmA
---l
IF =8mA
IF -7 mA
/'
f
!;
u
7
r
0.8mA
0.7mA
~
1:;
0.4mA
0.3mA
0.2mA
12
10
..
8
i
!::
-
Q)
18=0
TA = 25"C-
V
8
1:
o
u
Go)
.- ~mA
{
I
0.6mA
0.5mA
!::
E
E
COLLECTOR CURRENT
vs
COLLECTOR-EMITTER VOLTAGE
COLLECTOR CURRENT
vs
COLLECTOR·EMITTER VOLTAGE
I-
IF'- 6 mA
I
6
IF - 5 mA
5
IF=4mA
4
3
IF~3mA-
2
IF l2 mA
IF -1 mA
o
o
VCE-Collector-Emitter Voltage-V
2
4
6
8
10
12
VCE-Collector-Emitter Voltage-V
FIGURE 3
FIGURE 2
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
2-207
Tll181
OPTOCOUPLER
TYPICAL CHARACTERISTICS
RELATIVE ON-STATE COLLECTOR CURRENT
PHOTOTRANSISTOR COLLECTOR CURRENT
vs
vs
INPUT DIODE FORWARD CURRENT
FREE-AIR TEMPERATURE
100
50 :VCE" 0.4 V
E
:18 0
I
E 20 -T, =25°C
f
10
!;
u
5
oU
«
~
.
-I 'is
U
2
1
CD
n 'w;~
0.5
CD
o
3
3
c
:::J
c;"
c:
i
. / I-"'"
1.2
:= 1.0
S
.~ 0.8
~
/
~
!
d~
~
J
0.01
0.1 0.2
0.5
1
2
5
10 20
50 100
:3
'<9
~of
0.4
0.2
-50
-25
o
25
50
75
100
TA-Free-Air Temperature-oC
IF-Input-Diode Forward Current-mA
en
""~o~
~~
"0
E 0.6
~
1: 0.02
ci"
:::J
18=0
..
0.2
0.1
JO.4V
VCE
"
~
~
.c 0.05
a.
....C»
1.4
~
FIGURE 4
FIGURE 5
(')
:::;'
NORMALIZED TRANSISTOR STATIC FORWARD
CURRENT TRANSFER RATIO
n
c
;:::;:'
en
NORMALIZED TRANSISTOR STATIC FORWARD
CURRENT TRANSFER RATIO
vs
w
vs
w
COLLECTOR CURRENT
u..
T 1.3
.~ 1.2
a: 1.1
~c:~ 1.0
VCE =i'i V
IF=O
TA = 25°C
~
0.9
1: 0.8
f
d
'"
./
1.6
~
1.4 -IF=O
i
V-
E
I-""
VCE ~5V
IC= 10mA
LV
1.2
a~ 1.0
1
1of
!]
0.5
" 0.4
~ 0.3
~ 0.2
_ 0.1
00.1
T
J
.......
0.7
'E 0.6
Z~
FREE-AIR TEMPERATURE
u..
4
0.4
10
40
~
~
0.8
0.6
/
V
V
V
/
0.4
-50
-25
o
25
50
75
TA-Free·Air Temperature-OC
Ic-Collector Current-mA
FIGURE 6
2-208
/'
FIGURE 7
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • OAUAS, TeXAS 75285
100
TISP1082
DUAL ASYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSOR
03089, DECEMBER 1987
FOR APPLICATIONS IN TELECOMMUNICATIONS EQUIPMENT
•
Breakover Voltage to Common , , . 82 V Max
•
Reference Voltage .•• 58 V Min
•
Surge Current 8120 pS •. , 150 A
•
Holding Current . . . 150 mA Min
description
The TISP1 082 is designed specifically for telephone line card protection against lightning and transients
induced by ac lines when A and B are connected to the TIP and RING circuits, These devices consist of
two asymmetrical suppressor sections that will suppress voltage transients between terminals A and C,
Band C, and A and B,
Negative transients are initially clipped by zener action until the voltage rises to the breakover level, which
causes the device to crowbar, The high crowbar holding current prevents de latchup as the transient
subsides, Positive transients are clipped by diode action. A to B characteristics are symmetrical, and the
crowbar action of the device suppresses transients.
These monolithic protection devices are fabricated in ion-implanted planar structures to ensure precise
and symmetrical breakover level.
U)
C
o
',t:;
m
,~
c
:::s
mechanical data
E
E
THE COMMON PIN IS IN ELECTRICAL CONTACT WITH THE MOUNTING PAD
o
'6,.' (0.650)
THIS PORTION OF LEADS
FREE OF FLASH
ALINE -+
C(COMMON, _
BLiNE -+
u
13,72 (0.54O}Glli6;OOiO:63Oi
12,70 (0.500)
r"'
Q)
'i)
6,86 (0.270)
5,84 (0.230)
I-
: 9 I~=:am)
1
~..j
JL
/.-
2,79 (0.110'
5'33 (0.190,
(:.210)
4,83
3,43 (0.135,
2,67 (0.105,
4,83 (0.190,
0,46 (0.018'
0,30 (0.012' ~
r==
3 LEADS
c--,
t~
+
5,33 (0.210,
4,83 (0.190,
f
,
(t.
-,
III-*-
1,40 (O.05JT
1,14 (0.045,
2,41 (0.095'
0,89 (0.035,
074 029' [
__---;-_.L,[ 4,19 (0.165,
I
I
CASE TEMPERATURE
MEASUREMENT POINT
1,53 (0.060,
1,14 (0.045,
I
3 LEADS
* r===r--f
2,79 (0.110,
2,28 (0.090'
I
L~EJ~,~~d
I
_..J
~~~ :~: :::: DIA
13,72 (0.540,
RAD 2 PLACES
B
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
DEVICE SCHEMATIC
Copyright @ 1987. Texas Instruments Incorporated
2-209
TISP1082
DUAL ASYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSOR
absolute maximum ratings at 25°C case temperature (unless otherwise noted)
Nonrepetitive peak on-state pulse current, 8/20 p.S (see Notes 1, 2, and 3) .............. 150 A
Nonrepetitive peak on-state current, tw = 10,.s, half sine-wave (see Notes 2 and 3) ......• 15 A
Peak rate of rise of on-state current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 250 AI,.s
Operating junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 50 De
Operating free-air temperature range ...................................... oDe to 70 De
Storage temperature range ......................................... - 40 De to 125 De
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 230 D e
-4
(1)
CD
n
o
3
3
NOTES: 1. The notation "8/20 p.a" refers to a waveshape having a rise time of 8 ,.s and a duration of 20 ,.s ending at 50% of the peak
value (see ANSI Standard C62.1).
2. Above 70 ·C, derate linearly to zero at 150·C case temperature.
3. This value applies when the case temperature is at (or below) 70 ·C. The surge may be repeated after the device has returned
to thermal equilibrium.
electrical characteristics for the A and B terminals t, T J - 25°C
TEST CONDITIONS
MIN
Vz
PARAMETER
Reference voltage
IZ=-lmA
-58
c
10
Off-state current
Vo = ±50 V
cr
C»
Coff
Off-state capacitance
~
...
S'
~
(I)
±10
,.A
1
5
pF
TYP
MAX
electrical characteristics for the A and C or the Band C terminals:!:, TJ - 25°C
PARAMETER
TEST CONDITIONS
Reference voltage
IZ
=
-1 rnA
n
::;.'
"'VZ
of reference voltage
V(BO)
Breakover voltage
See Note 5
I(BO)
Breakover current
See Note 5
VF
Forward voltage
(I)
UNIT
V
Vo = 0, f=lkHz,
See Note 4
Vz
c
MAX
t Polarity may be determined arbitrarily.
(")
:;'
TYP
MIN
-58
Temperature coefficient
VTM
Peak on-state voltage
IF - 5 A,
IT = -5 A,
IH
Holding current
See Note 5
dv/dt
V
%I·C
0.1
Critical rate of rise
-0.15
10
Off-state current
Vo = -50 V
Coff
Off-state capacitance
Vo - 0,
See Note 4
V
3
-3
V
-2.2
A
-150
-5
f-lkHz,
V
rnA
See Note 7
of off-state voltage
-82
-0.6
See Notes 5 and 6
See Notes 5 and 6
UNIT
300
kV/p.a
-10
"A
500
pF
t Polarity is determined at terminal A or B with respect to C.
NOTES: 4. These capacitance measurements employ a three-terminal capacitance bridge incorporating a guard circuit. The third terminal
and the mounting tab are connected to the guard terminal of the bridge.
5. These parameters must be measured using pulse techniques, tw = 100 ,.s, duty cycle :$2%.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts and located within
3,2 mm (0.125 inch) of the device body.
7. The critical dv/dt is measured using a linear rate of rise with the maximum voltage limited to 80% of Vz min.
thermal characteristics
PARAMETER
RoJC
R9JA
2-210
Junction-to-case thermal resistance
Junction-to-free-air thermal resistance
TEXAS •
INSTRUMENTS
POST OFFICE BOX 866012 !" DAUAS. TeXAS 76266
TISP10B2
DUAL ASYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSOR
PARAMETER MEASUREMENT INFORMATION
+1
- -~ - - - - -.- - - ----_t!
____ --~-------
I
II'
--t----------,I
,
I
I
I
IZ
I
VIBO) Vz
I
I
-V;_~--------~------_+--~~--r_------;_--------+_;_+V
,I
,
I
I
I
I
Vz VIBO)
I
I - - - - - - - ....... - - - - -
U)
..
C3
CJ
..
U)
c
'
----------t--
I
...
'5
IZ
I
I
'
o
&U
,2
c
:::s
E
E
o
-l'--,
- - - - - - - - ...... -----J
I
CJ
Q)
I
Q)
I-I
FIGURE 1. VOLTAGE-CURRENT CHARACTERISTICS FOR TERMINALS A AND Bt
t Polarity may be determined arbitrarily,
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
2-211
TISP1082
DUAL ASYMMETRICAL TRANSIENT
VOLTGE SUPPRESSOR
PARAMETER MEASUREMENT INFORMATION
+1
-I
CD
CD
n
o
3
3
VIBO) Vz
·-v--r-+---------+--------r--~--_+---------------------+V
Ir-------~------~--J_r
I
I
I
c
:::s
cr
I»
r+
I
I
S"
:::s
-----------t-I
IZ
I
1- ------ -+ - - - - -ltL-
(II
o
- - - - - - - ..... - - - - - t ; -
:::;"
n
I
I
c
;::;."
(II
-I
FIGURE 2. VOLTAGE-CURRENT CHARACTERISTICS FOR TERMINALS A AND C OR BAND C*
:t: Polarity is determined at terminal A or B with respect to C.
2-212
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
TISP1082
DUAL ASYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSOR
TYPICAL APPLICATION DATA
The breakover voltage represents the highest level of stress applied to the system being protected by the
suppressor. With an increase in ambient temperature, the reference voltage (the level at which transient voltage
clipping just begins) increases at typically O.09%/oC. Breakover current, however, decreases at typically
-O.06%/OC, but operating along the reference resistance line reduces its effect. The net result is that the
breakover voltage level is only slightly dependent on ambient temperature.
D-C lockup: The suppressor will remain in a crowbar condition as long as the line can supply a short-circuit
current greater than the holding current, IH. To prevent this from happening, the following conditions must
be obtained:
Vbattery
Rline
...
U)
< IH
"S
...
(.)
Continuous operation: Line short-circuits to external power supplies can result in overdissipation of the
suppressor. Conventional protection techniques such as the use of fuses or PTC thermistors should be used
to eliminate or reduce the fault current.
C3
U)
c
o
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I-
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-213
-t
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2-214
TISP2180, TISP2290
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
03201, DECEMBER 1987
FOR APPLICATIONS IN TELECOMMUNICATIONS EQUIPMENT
•
Breakover Voltage to Common
TISP2180 ..• 180 V Max
TISP2290 ... 290 V Max
•
Reference Voltage
TISP2180 ... 145 V Min
TISP2290 ... 200 V Min
•
Surge Current 8/20
•
Holding Current , . . 150 rnA Min
,",S •••
150 A
description
The TISP2000 series is designed specifically for telephone line card protection against lightning and
transients induced by ac lines when A and B are connected to the TIP and RING circuits. The TISP2180
and TISP2290 consist of two bidirectional suppressor sections connected to a common C terminal. They
will suppress voltage transients between terminals A and C, Band C, and A and B,
Transients are initially clipped by zener action until the voltage rises to the breakover level, which causes
the device to crowbar. The high crowbar holding current prevents de latchup as the transient subsides.
These monolithic protection devices are fabricated in ion-implanted planar structures to ensure precise
and symmetrical breakover control.
...'Sen
..
C3
(,)
en
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mechanical data
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ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
PRODUCTIOI DATA .......nts ..ntai. informati.n
•• rnlt ...f puIIlicati.n d.lI. Prod ......nf.rm t•
• pooifioati... Plr th. II.... of Ta,," Instr.mants
I
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3 LEADS
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DEVICE SCHEMATIC
Copyright @ 1987. Texas Instruments Incorporated
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-215
TlSP2180. TISP2290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
absolute maximum ratings at 25°C case temperature (unless otherwise notedl
Nonrepetitive peak on-state pulse current 8/20 p'S (see Notes 1. 2. and 3) . . . . . . . • . . . . . .. 150 A
Nonrepetitive peak on-state current. tw = 10 ms. half sine-wave (see Notes 2 and 3) . . . . . .. 15 A
Peak rate of rise of on-state current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 250 AIp.S
Operating junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 150°C
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°C
Storage temperature range ......................................... - 40°C to 150°C
Lead temperature 1.6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 230°C
NOTES: 1. The notation "S/20 p,s" refers to a waveshape having a rise time of S ~s and a duration of 20 ~s ending at 50% of the peak
value (see ANSI Standard C62.1).
2. Above 70°C, derate linearly to zero at 150°C case temperature.
3. This value applies when the case temperature is at (or below) 70°C. The surge may be repeated after the device has returned
to thermal equilibrium.
electrical characteristics for the A and B terminals t. TJ - 25°C
PARAMETER
Vz
Reference voltage
10
Off-state current
Off·state capacitance
Coff
TEST CONDITIONS
IZ = ±1 mA
Vo = ±50 V
f=lkHz,
Vo = 0,
MIN
TISP2180
TYP MAX
±145
See Note 4
MIN
TISP2290
TYP MAX
±200
40
±10
100
±10
100
40
UNIT
V
p.A
pF
electrical characteristics for the A and C or the Band C terminals t, TJ - 25°C
TEST CONDITIONS
PARAMETER
Vz
avz
V(BO)
IIBOI
VTM
IH
dv/dt
10
Coff
Reference voltage
Temperature coefficient
of reference voltage
Breakover voltage
Breakover currant
Peak on-state voltage
Holding current
Critical rate of rise
of off-state voltage
Off-state current
Off-state capacitance
IZ = ±1 rnA
MIN
TISP2180
TYP MAX
±145
TISP2290'
MIN
0.1
See Notes 5 and 6
±0.15
See Notes 5 and 6
±2.2
±0.6 ±0.15
±3
V
See Note 4
±290
±0.6
±3
5
5
±10
110
±10
200
±150
See Note 7
110
200
UNIT
'161°C
± 1.9
±150
Vo = ±50 V
Vo - 0, f-lkHz,
MAX
0.1
±lS0
See Note 5
IT=±5A,
See Note 5
TYP
±200
V
A
V
mA
kV/p,s
p.A
pF
tPolarity may be determined arbitrarily.
NOTES: 4. These capacitance measurements employ a three-terminal capacitance bridge incorporating a guard circuit. The third terminal
and the mounting tab are connected to the guard terminal of the bridge.
5. These parameters must be measured using pulse techniques, tw = 100 ~s, duty cycle s 2%.
6. These param",ters are measured with voltage-sensing contacts separate from the current-carrying contacts and located within
3,2 mm (0.125 inch) from the device body.
7. The critical dv/dt is measured using a linear rate of rise with the maximum voltage limited to SO% of Vz min.
thermal characteristics
MIN
R6JC
PARAMETER
Junction-to-case thermal resistance
R6JA
Junction-to-fre8-air thermal resistance
2-216
TYP
MAX
3.5
62.5
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75265
TISP2180, TISP2290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
PARAMETER MEASUREMENT INFORMATION
+1
i~
___________ .___________
,,:. - ] - - -- - - --- + ------ - --IH __
I
I
I
I
I
I
I
I
I
_-1________
IZ
I
I
VIBOI Vz
-V~4---------~------~--~--4-------~--------+-+-+V
Vz VIBOI
I
I
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---------+--
IZ
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I --- - -- -----4 ------ ---- ~r-
-----~-
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I-
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FIGURE 1. VOLTAGE-CURRENT CHARACTERISTICS FOR ANY PAIR OF TERMINALSt
tPolarity may be determined arbitrarily.
TEXAS •
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285
2-217
TISP2180, TISP2290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
TYPICAL APPLICATION DATA
The breakover voltage represents the highest level of stress applied to the system being protected by the
suppressor. With an increase in ambient temperature, the reference voltage (the level at which transient voltage
clipping just begins) increases at typically O.09%l o C. Breakover current, however, decreases at typically
-O.06%IOC, but operating along the reference resistance line reduces its effect. The net result is that the
breakover voltage level is only slightly dependent on ambient temperature.
--
O-C lockup: The suppressor will remain in a crowbar condition as long as the line can supply a short-circuit
current greater than the holding current, IH. To prevent this from happening, the following conditions must
be obtained.:
-I
Vbattery
Ci'
Rline
CD
n
o
3
3
c
<
IH
Continuous operation: Line short-circuits to external power supplies can result in overdissipation of the suppressor.
Conventional protection techniques such as the use of fuses or PTC thermistors should be used to eliminate
or reduce the fault current.
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2-218
TEXAS ."
INSTRUMENlS
'OST OFFICE BOX 855012 • DALLAS, TEXAS 75265
TISP3180. TlSP3290
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
03073, DECEMBER 1987
FOR APPLICATIONS IN TELECOMMUNICATIONS EQUIPMENT
•
Breakovar Voltage to Common
TISP3180 ... 180 V Max
TISP3290 ••• 290 V Max
•
Reference Voltage
TISP3180 ... 145 V Min
TISP3290 ... 200 V Min
•
Surge Current 8/20 ,., ... 150 A
•
Holding Current . . . 150 mA Min
description
The TlSP3000 series is designed specifically for telephone line card protection against lightning and
transients induced by ac power lines when A and B are connected to the TIP and RING circuits. The
TISP3180 and TISP3290 consist of two bidirectional suppressor sections connected to a common C
terminal. They will suppress voltage transients between terminals A and C, Band C, and A and B.
Transients are initially clipped by zener action until the voltage rises to the breakover level, which causes
the device to crowbar. The high crowbar holding current prevents dc latchup as the transient subsides.
These monolithic protection devices are fabricated in ion-implanted planar structures to ensure precise
and symmetrical breakover control.
...o
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..
CJ
(3
o
C
o
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mechanical data
as
c
.~
THE COMMON PIN IS IN ELECTRICAL CONTACT WITH THE MOUNTING PAD
:::J
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16,51 (0.650)
13,72 ( O S 4 O ) - n I ' 6 ' O O (0.630)
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THIS PORTION OF LEADS
FREE OF FLASH
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RAD 2 PLACES
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
PRODUCTIOI DATA doc".._ CGllllialnfonnatio.
••,"111 H of p""liclti•• dl1tl, Pradooll ••nfo,.. to
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.,oclflcati... PO' the torms .1 TI..I IlIItnIm_
=~~·{:''T.1i =:~':r
DIt
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
DEVICE SCHEMATIC
Copyright @ 1987. Texas Instruments Incorporated
2-219
TISP3180, TISP3290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
absolute maximum ratings at 25°C case temperature (unless otherwise noted)
Nonrepetitive peak on-state pulse current 8/20 ,.s (see Notes 1, 2, and 3) . . . . . . . . . . . . . .. 150 A
Nonrepetitive peak on-state current, tw = 10 ms, half sine-wave (see Notes 2 and 3) . . . . . .. 15 A
Peak rate of rise of on-state current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . •. 250 A/,.s
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 150 DC
Operating free-air temperature range ...................................... 0 0 (: to 70 0 e
Storage temperature range ......................................... - 40°C to 150°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 230°C
NOTES:
-I
CD
1. The notation "8/20 p.S" refers to a waveshape having a rise time of 8 /Ls and a duration of 20 /LS ending at 50% of the peak
value (see ANSI Standard C62.1).
2. Above 70·C, derate linearly to zero at 150·C case temperature.
3. This value applies when the case temperature is at (or below) 70 ·C. The surge may be repeated after the device has returned
to thermal equilibrium.
CD
g
3
3
c
:::s
(;'
...S'
S»
:::s
en
electrical characteristics for the A and B terminals t, TJ - 25°C
PARAMETER
Vz
Reference voltage
10
Off-state current
Coff
Off-state capacitance
TEST CONDITIONS
IZ = ±1 mA
Vo = ±50 V
f
Vo = 0,
TYP
TlSP3290
MAX
±290
MIN
TYP
MAX
±400
V
±10
= 1 kHz,
0.5
See Note 4
UNIT
±10
5
0.5
5
p.A
pF
electrical characteristics for the A and C or the Band C terminals t, TJ = 25°C
PARAMETER
(')
Reference voltage
TEST CONDITIONS
=
±1 mA
::;'
Vz
C
"VZ
en
V(80l
8reakover voltage
See Notes 5 and 6
1180l
Breakover current
See Note 5
VTM
IH
Peak on-state voltage
IT = ±5A,
See Note 5
()
::;'
TISP3180
MIN
IZ
TlSP3180
MIN
±145
TYP
dvldt
of reference voltage
Holding current
Critical rate of rise
of off-state voltage
±0.15
10
Off-state current
Vo
Off-state capacitance
Vo
TYP
±2.2
V
±290
V
±0.6
A
±3
±1.9
±3
±150
5
±10
250
V
mA
±10
105
%I·C
±180
5
See Note 4
UNIT
0.1
±150
= ±50 V
= 0, f = 1 kHz,
MAX
0.1
±0.6 ±0.15
See Note 7
Coif
MIN
±200
Temperature coefficient
See Notes 5 and 6
TISP3290
MAX
95
250
kV/p.S
p.A
pF
tPolarity may be determined arbitrarily.
NOTES: 4. These capacitance measurements employ a three-terminal capacitance bridge incorporating a guard circuit. The third terminal
and the mounting tab are connected to the guard terminal of the bridge.
5. These parameters must be measured using pulse techniques, tw = 100 p.s, duty cycle s 2%.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts and located within
3,2 mm (0.125 inch) from the device body.
7. The critical dvldt is measured using a linear rate of rise with the maximum voltage limited to 80% of Vz min.
thermal characteristics
PARAMETER
MIN
RgJC
Junction-to-case thermal resistance
RgJA
Junction-to-free-air thermal resistance
2-220
TYP
MAX
3.5
62.5
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS, TEXAS 75265
TISP3180, TISP3290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
PARAMETER MEASUREMENT INFORMATION
+1
, ,: _~i~-----------.----------t ____
+ _________ _
IH __
I
I
I
I
I
I
I
_..1________
IZ
I
I
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VIBOI Vz
-v;--r---------r-------+--~~--~------4_--------+_+_
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(,)
(3
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,~
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...
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IH
--I ~-- '00'
E
E
o(,)
G)
IT
'ii
t-
-I
FIGURE 1. VOLTAGE-CURRENT CHARACTERISTICS FOR ANY PAIR OF TERMINALSt
tPolarity may be determined arbitrarily.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75266
2-221
TISP3180, TISP3290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
TYPICAL APPLICATION DATA
The breakover voltage represents the highest level of stress applied to the system being protected by the
suppressor. With an increase in ambient temperature, the reference voltage (the level at which transient voltage
clipping just begins) increases at typically O.09%l o C. Breakover current, however, decreases at typically
-O.06%IOC, but operating along the reference resistance line reduces its effect. The net result is that the
breakover voltage level is only slightly dependent on ambient temperature.
O-C lockup: The suppressor will remain in a crowbar condition as long as the line can supply a short-circuit
current greater than the holding current, IH. To prevent this from happening, the following conditions must
be obtained.:
....
Vbattery
CD
Rline
(1)
n
o
3
3
c
< IH
Continuous operation: Line short-circuits to external power supplies can result in overdissipation of the suppressor.
Conventional protection techniques such as the use of fuses or PTC thermistors should be used to eliminate
or reduce the fault current.
>
:::s
n'
m
....
0'
:::s
(I)
o=i'
n
C
::+
(I)
2-222
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 76265
TlSP4180, TISP4290
SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
Ol070, DECEMBER 19B7
FOR APPLICATIONS IN TELECOMMUNICATIONS EQUIPMENT
•
Breakover Voltage to Common
TISP4180 ... 1BO V Max
TISP4290 ... 290 V Max
•
Reference Voltage
TISP4180 •.. 145 V Min
TISP4290 ... 200 V Min
•
Surge Current 8/20 ,.s .•. 150 A
•
Holding Current • . • 150 mA Min
description
The TISP4000 series is designed specifically for telephone line card protection against lightning and
transients induced by ac power lines. The TISP4180 and TISP4290 consist of a bidirectional suppressor
element connecting the A and B terminals. They will suppress interwire transients.
Transients are initially clipped by zener action until the voltage rises to the breakover level, which causes
the device to crowbar. The high crowbar holding current prevents dc latchup as the transient subsides.
These monolithic protection devices are fabricated in ion-implanted planar structures to ensure precise
and symmetrical breakover control.
...en
'S
..
u
(3
en
C
mechanical data
o
'';
CO
U
PIN A IS IN ELECTRICAL CONTACT WITH THE MOUNTING PAD
'C
~
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E
o
16,51 (O;650)
THIS PORTION OF LEADS
FREE OF FLASH
r
ll,72 ( o . 5 4 0 ) n ! 1 6 , O O (O.6l0)
12,70 (O.500)
6,86 (O.270)
5,84 (O.2l0)
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4,83 (O.lBO)
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r-::::
0,30 (O.012) ~
2 LEADS
A
t
0,89 (0.035)
o 74 (~.029) [
.'
r=-,
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III-*-
1.40(0.05~
2,9210.115)
2,41 10.095)
1.14 (O.045)
r--
CASE TEMPERATURE
MEASUREMENT POINT
1,53 (0.060)
1,14 (0.045)
2 LEADS
5,33 (0.210)
~
t
l14,73 (0.580)
13,72 (0.540)
j
4,09 (0.161) DIA
3,8l (0.151)
A
--..,
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,
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IL ______ J ,
B
DEVICE SCHEMATIC
RAD 2 PLACES
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
PRODUCTIO. DATA d••ullltIlI_lIi. illfe....tIo.
Ollnlllt II 01 puIIlicatio. dill. P.....CII ..."'''" t.
:c:=r::..rr':Ji~~":.:'.J:;~:"..:.."":
.......r1ly i...
lilting 01 .11 par• .,1IIn.
Copyright @ 1987. Texas InS1ruments Incorporated
TEXAS .."
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-223
TISP4180, TISP4290
SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
absolute maximum ratings at 25 °C case temperature (unless otherwise noted)
Nonrepetitive peak on-state pulse current 8/20 pS (see Notes 1, 2, and 3) . . . . . . . . . . . . . .. 150 A
Nonrepetitive peak on-state current, tw = 10 ms, half sine-wave (see Notes 2 and 3) . . . . . .. 15 A
Peak rate of rise of on-state current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 250 AIl's
Junction temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 150°C
Operating free-air temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. OOC to 70°C
Storage temperature range ..............•..........•............... -40°C to 125°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds ...................... 230°C
NOTES:
-t
CD
CD
(")
o
3
3
c
electrical characteristics t, TJ - 25°C
PARAMETER
Vz
::::I
...n'0'
CI)
::::I
en
(')
1. The notation "8/20 I'S" refers to a waveshape having a rise time of 8 1'8 and a duration of 201'8 ending at 50% of the peak
value (see ANSI Standard C62.1).
2. Above 70 ·C, derate linearly to zero at 150·C case temperature.
3. This value applies when the case temperature is at (or below) 70 ·C. The surge may be repeated after the device has returned
to thermal equilibrium.
Reference voltage
TEST CONDITIONS
IZ -
±1 mA
reference voltage
Breakover voltage
See Notes 4 and 6
I(BO~
Breakover current
See Note 4
VTM
Peak on-state voltage
IT
IH
Holding current
See Note 4
Critical rate of rise of
=
C
10
Off-state current
Vo -
Coff
Off-state capacitance
Vo = 0,
en
off-state voltage
See Notes 4 and 6
±2.2
±lBO
±290
±1.9
±3
110
UNIT
V
0.1
%I·C
V
±O.S
A
±3
V
±160
±50 V
See Note 7
MAX
0.1
±150
= 1 kHz,
TYP
±0.6 ±0.16
See Note 6
f
MIN
±200
±0.15
±6A,
TISP4290
MAX
±120
VIBO)
dvldt
;::;.'
TYP
Temperature coefficient of
"'VZ
:::;'
(")
TISP41SO
MIN
mA
5
5
±10
±10
pA
200
pF
200
110
t Polarity
kV/1'8
may be determined arbitrarily.
NOTES: 4. These capacitance measurements employ a three-terminal capacitance bridge incorporating a guard circuit. The third terminal
and the mounting tab are connected to the guard terminal of the bridge.
5. These parameters must be measured using pulse techniques, tw = 100 1'8, duty cycle s 2%.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts and located within
3,2 mm (0.125 inch) from the device body.
7. The critical dvldt is measured using a linear rate of rise with the maximum voltage limited to SO% of Vz min.
thermal characteristics
MIN
PARAMETER
Junction-to-case thermal resistance
R9JA
Junction-to-free-air thermal resistance
2-224
TVP
MAX
3.5
R9JC
62.6
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75265
TISP4180, TISP4290
SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
PARAMETER MEASUREMENT INFORMATION
+1
ij___________.___________
,,,:
-] - - - -- - --- + ------ - --- I
IH __
I
I
_-L________
IZ
I
I
I
I
I
...
fI)
I
"5
(,)
I
C3
I
...
fI)
I
I
I
:
---------t--
+0
IZ
I
I
I
c
o
------------.----------tr
- - - - - -t-- •
I
-----~---
'~~'
as
(,)
"2
:::I
E
E
o(,)
G)
Gi
I-I
FIGURE 1. VOLTAGE-CURRENT CHARACTERISTICSt
tPolarity may be determined arbitrarily.
TEXAS .."
INSTRUMENlS
POST OfFICE BOX 655012 • DALLAS. TEXAS 75265
2-225
TISP4180, TlSP4290
SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
TYPICAL APPLICATION DATA
The breakover voltage represents the highest level of stress applied to the system being protected by the
suppressor. With an increase in ambient temperature, the reference voltage (the level at which transient voltage
clipping just begins) increases at typically O.09%/oC. Breakover current, however, decreases at typically
-O.06%/OC, but operating along the reference resistance line reduces its effect. The net result is that the
breakover voltage level is only slightly dependent on ambient temperature.
O-C lockup: The suppressor will remain in a crowbar condition as long as the line can supply a short-circuit
current greater than the holding current, IH. To prevent this from happening, the following conditions must
be obtained.:
Vbattery
< IH
Rline
Continuous operation: Line short-circuits to external power supplies can result in overdissipation of the suppressor.
Conventional protection techniques such as the use of fuses or PTC thermistors should be used to eliminate
or reduce the fault current.
2-226
TEXAS ."
INSIRUMENTS
POST OFFICE BOX 855012 • DALlAS. TEXAS 76266
TlSP7180, TISP7290
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSOR
03063, DECEMBER 1987
FOR APPLICATIONS IN TELECOMMUNICATIONS EQUIPMENT
•
Breakover Voltage to Common
TISP7180 ... 180 V Max
TISP7290 ... 290 V Max
•
Surge Current 8/20
TISP7180 ... 100 A
TISP7290 ••. 150 A
,.5
•
Reference Voltage
TISP7180 •.• 145 V Min
TISP7290 ... 200 V Min
•
Holding Current • . . 150 mA Min
description
The TISP7000 series is designed specifically for telephone line card protection against lightning and
transients induced by ac power lines. The TISP7180 and TISP7290 consist of three bidirectional suppressor
sections that will suppress voltage transients between terminals A and C. Band C. and A and B.
Transients are initially clipped by zener action until the voltage rises to the breakover level. which causes
the device to crowbar. The high crowbar holding current prevents dc latchup as the transient subsides.
These monolithic protection devices are fabricated in ion-implanted planar structures to ensure precise
and symmetrical breakover control.
...
"S
U)
u
...
(3
U)
C
o
"';::
ca
mechanical data
u
Gni6.00
"2
;:,
THE COMMON PIN IS IN ELECTRICAL CONTACT WITH THE MOUNTING PAD
E
E
16,51 (0.6501
THIS PORTION OF LEADS
FREE OF FLASH
13,72 (0.5401
12,70 (0.5001
--fo---~.I
H
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C(COMMONI---+
g
3,30(0.'30I~
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(0.6301
ou
6,86 (0.2701
,101~'201
;l:fl
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4,83 (0.1901
3,43 (0.135)
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r
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3 LEADS
r==? _._,,---:.....!.--L
r=
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2," (0.0951
0,8910.0351
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f
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4,19 10.1651
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---'--,I
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1,1' (0.0451
I
3LEADS
I
+ r=y---
f
2,7910.1101
2.29 10.0901
L
14.73 10.5801
13,72 (0.540)
.,...,-lL.--'
~:~; :~: ~:~:
j
I
DIA
RAD 2 PLACES
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
I
I
_ _ _ _ _ .JI
B
DEVICE SCHEMATIC
Copyright @ 1987, Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75285
2-227
TISP7180. TlSP7290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
absolute maximum ratings at 25°C case temperature (unless otherwise noted)
Nonrepetitive peak on-state pulse current 8/20 p.s (see Notes 1, 2, and 3) . . . . . . . . . . . . . .. 150 A
Nonrepetitive peak on-state current, tw = 10 ms, half sine-wave (see Notes 2 and 3) . . . . . .. 15 A
Peak rate of rise of on-state current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 250 A/p.s
Junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 50°C
Operating free-air temperature range ...................................... ooe to 70°C
Storage temperature range ......................................... - 40°C to 1 50 DC
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds. . . . . . . . . . . . . . . . . . . . .. 230°C
NOTES:
-t
CD
CD
(')
o
3
3
1. The notation "S/20 p,s" refers to a waveshape having a rise time of S p,s and a duration of 20 p,s ending al 50% of the peak
value (see ANSI Standard C62.1).
2. Above 70°C, derate linearly to zero at 150°C case temperature.
3. This value applies when the case temperature is at (or below) 70°C. The surge may be repeated after the device has returned
to thermal equilibrium.
electrical characteristics for the A and B terminals t. T J - 25°C
PARAMETER
TEST CONDITIONS
c
Vz
Reference voltage
::;,
10
Off-state Current
Vo
c;"
m
....
Coff
Off-state capacitance
Vo
o·::;,
~r
c
::+
fI)
TYP
TISP7290
MAX
±145
±1 mA
= ±50 V
= 0,
f =
MIN
TVP
MAX
±200
V
±10
1 kHz,
See Note 4
40
UNIT
40
100
±10
~
100
pF
electrical characteristics for the A and C or the Band C terminals t. TJ - 25°C
PARAMETER
fI)
o
IZ -
TISP7180
MIN
Vz
OlVZ
Reference voltage
Temperature coefficient
TEST CONDITIONS
IZ
=
±1 mA
TYP
Breakover voltage
See Noles 5 and 6
Breakover current
See Note 5
VTM
IH
Peak on-state voltage
IT = ±5A,
See Note 5
Holding current
of off-state voltage
±0.15
See Notes 5 and 6
Off-state Current
Vo
Coff
Off-state capacitance
Vo
= ±50 V
= 0, f =
TYP
0.1
0.1
±IS0
±290
±2.2
±3
±1.9
A
V
±10
150
V
±3
5
±10
70
%/OC
mA
5
See Note 4
UNIT
±0.6
±150
±150
1 kHz,
MAX
V
±0.6 ±0.15
See Note 7
10
MIN
±200
of reference voltage
Critical rata of rise
TISP7290
MAX
±145
VIBOI
I(BO)
dv/dt
TlSP7180
MIN
70
150
kV/p,s
~
pF
t Polarity may be determined arbitrarily.
NOTES: 4. These capacitance measurements employ a three-terminal capacitance bridge incorporating a guard circuit., The third terminal
and the mounting tab are connected 10 the guard terminal of the bridge ..
5. These parameters must be measured using pulse techniques, tw = 100 P.s, duty cycle s 2%.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts and located within
3,2 mm (0.125 inch) from the device body.
7. The critical dvldt is measured using a linear rate of rise with the maximum voltage limited to SO% of Vz min.
thermal characteristics
MIN
PARAMETER
Junction-to-case thermal resistance
R9JA
Junction-to-free-air thermal resistance
2-228
TVP
MAX
3.5
R9JC
62.5
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 856012 • DALLAS. TEXAS 75286
TlSP7180, TlSP7290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
PARAMETER MEASUREMENT INFORMATION
+1
-~
IT
I
I(BOI
--
IH --
.
_L _________ +
_________ _
i-----------.----------I
I
I
I
I
I
I
I
I
I
_-L________
IZ
I
VIBO) Vz
-v;--r--------T-------T---1r--~------~--------+-~
I
I
CI)
..
C3
u
CI)
I
I
I
...
"S
c
o
I
---------r-
';i
IZ
I
I
-----------4----------J~--- IH
--- --- ----- ->- -- -
------! ~-- '''0'
ca
(,)
"2
:l
E
E
o
u
Q)
...
"i)
IT
-I
FIGURE 1. VOLTAGE-CURRENT CHARACTERISTICS FOR ANY PAIR OF TERMINALSt
t Polarity may be determined arbitrarily.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 76285
2-229
TISP7180. TISP7290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
TYPICAL APPLICATION DATA
The breakover voltage represents the highest level of stress applied to the system being protected by the
suppressor. With an increase in ambient temperature, the reference voltage (the level at which transient voltage
clipping just begins) increases at typically O.09%/oC. Breakover current, however, decreases at typically
-O.06%/OC, but operating along the reference resistance line reduces its effect. The net result is that the
breakover voltage level is only slightly dependent on ambient temperature.
O-C lockup: The suppressor will remain in a crowbar condition as long as the line can supply a short-circuit
current greater than the holding current, IH. To prevent this from happening, the following conditions must
be obtained.:
~
Vbattery
CD
Rline
CD
n
o
3
3
c
< IH
Continuous operation: Line short-circuits to external power supplies can result in overdissipation of the suppressor.
Conventional protection techniques such as the use of fuses or PTC thermistors should be used to eliminate
or reduce the fault current.
:J
c;"
I»
r+
0"
:J
o
o::;"
n
C
;::;."
o
2-230
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS, TEXAS 75265
TlSP8180, TISP8290
DUAL SYMMETRICAL TRANSIENT
VOLTAGE SUPPRESSORS
D3063. DECEMBER 1987
FOR APPLICATIONS IN TELECOMMUNICATIONS EQUIPMENT
•
Breakover Voltage to Common
TISP8180 ... 180 V Max
TISP8290 .•. 290 V Max
•
Reference Voltage
TISP8180 •.. 145 V Min
TISP8290 ..• 200 V Min
•
Surge Current 8/20 1'.
TISP8180 ... 100 A
TISP8290 ... 150 A
•
Holding Current . . . 150 rnA Min
description
The TISP8000 series is designed specifically for telephone line card protection against lightning and
transients, induced by ac lines when A and B are connected to the TIP and RING circuits. The TISP8180
and TlSP8290 consist of two bidirectional suppressor sections that will suppress voltage transients between
terminals A and C, Band C, and A and B.
Transients are initially clipped by zener action until the voltage rises to the breakover level, which causes
the device to crowbar. The high crowbar holding current prevents de latch up as the transient subsides.
These monolithic protection devices are fabricated in ion-implanted planar structures to ensure precise
and symmetrical breakover control.
EI
...
II)
..
'S
u
(3
II)
C
'.,
o
'CU
U
'c::s
mechanical data
E
E
THE COMMON PIN IS IN ELECTRICAL CONTACT WITH THE MOUNTING PAD
16,51 (0.6601
(0'5401~i6.OOTo:63Oi
o
13.72
12.70 (0.5001
THIS PORTION OF LEADS
FREE OF FLASH
CICO~M::~=:
r 'I
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G)
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5,84 (0.2301
G)
§ I ~~~~I
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t-
:
5.33
4.63 (!.2101
(0.1901
2.79 (0.1101
3.43 (0.1361
2.67 (0.1051
4,83 (0.1901
,[ 4.19 (0.1661
0.46 (0.0181
0,3il1D.D12i--.L.L
r:=
.
t~
Cl-'-I-'-*'-:---1..
3 LEADS
1.40 (0.05,;;jT
1,1410.0451
2.41 (0.0951
0.89 (0.0361
•
5.33 (0.2101
4.83 (0.1901
f
o7410291
•
[
f
2.79 (0.110)
i=
C
<
l>
2
(')
m
2
Coif
Reference voltage
Temperature coefficient
of reference voltage
Breakover voltage
Breakover current
Peak on·state voltage
Holding current
Critical rate of rise
of off·state voltage
Off·state current
Off·state capacitance
TEST CONDITIONS
Iz = ±1 mA
MIN
±145
TISPS1S0
TYP MAX
MIN
±200
TISPS290
TYP MAX
UNrr
0.1
%I·C
V
0.1
See Notes 5 and 6
See Note 5
IT = ±5 A, See Notes 5 and 6
See Note 5
±0.15
±150
±180
±0.6 ±0.15
±2.2
±3
±150
See Note 7
Vo = ±50 V
Vo = 0, f=lkHz,
See Note 4
70
±1.9
±290
±0.6
±3
6
6
±10
150
70
±10
150
V
A
V
mA
kV/"s
"A
pF
t Polarity may be determined arbitrarily.
NOTES: 4. These capacitance measurementa employ a three-terminal capacitance bridge incorporating a guard circuit. The third terminal
and the mounting tab are connected to the guard terminal of the bridge.
5. These parameters must be measured using pulse techniques, tw = 100 "s, duty cycle s 2%.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts and located within
3,2 mm (0.125 inch) from the device body.
7. The critical dvldt is measured using a linear rate of rise with the maximum voltaga limited to 80% of Vz min.
thermal characteristics
"T1
o:D
s:
MIN
PARAMETER
Junction-to-case thermal resistance
Junction-to-free-air thermal resistance
MAX
3.6
62.6
~
5
2
2-232
TYP
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 75285
TISP8180, TlSP8290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
PARAMETER MEASUREMENT INFORMATION
+1
~ -]---------+---------i~-----------.----------IH __
I
I
_.1.________
IZ
I
I
I
I
I
I
I
I
I
VIBOI Vz
-V~;---------T_------T_--~--~------~--------+_+_+V
Vz VIBOI
I
I
:
:
I
..
()
C3
U)
c
o
C\J
IZ
()
I
'2
- - - - -- - -t-fr-- "
I
-----~-
U)
'';::::
---------t--
I --- - ----- - -4-- - - - - ----
....
'S
~
E
E
~,
o
()
CD
"i
I-
IT
-I
FIGURE 1. VOLTAGE-CURRENT CHARACTERISTICS FOR ANY PAIR OF TERMINALSt
t Polarity may be determined arbitrarily.
2
o
~
c
<
l>
:2
off-state voltage
±0.15
See Notes 5 and 6
MIN
TVP
0.1
0.1
±IBO
±290
±2.2
±3
±150
± 1.9
%/OC
V
±0.6
A
±3
V
5
±10
See Note 4
UNIT
±150
5
f - 1 kHz,
MAX
V
±O.6 ±0.15
See Note 7
dvldt
TISP9290
MAX
±200
Temperature coefficient of
otVZ
(")
TVP
±145
IZ = ±1 mA
n'
f»
r+
TISP9180
MIN
110
200
110
kV/~
±10
~
200
pF
tPolarity may be determined arbitrarily.
NOTES: 4. These capacitance measurements employ a three-terminal capacitance bridge incorporating a guard circuit. The third terminal
and the mounting tab are connected to the guard terminal of the bridge.
5. These parameters must be measured using pulse techniques, tw = 100 ~s, duty cycle s 2%.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts and located within
3,2 mm (0.125 inch) from the device body.
7. The critical dvldt is measured using a linear rate of rise with tha maximum voltage limited to BO% of Vz min.
thermal characteristics
PARAMETER
A8JC
R9JA
MIN
MAX
62.5
(")
m
2
~
o
:0
s::
l>
:::!
o
2
2-236
TVP
3.6
Junction-to-case thermal resistance
Junction-to-free-air thermal resistance
TEXAS "
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TILSP9180, TlSP9290
DUAL SYMMETRICAL TRANSIENT VOLTAGE SUPPRESSORS
PARAMETER MEASUREMENT INFORMATION
+1
ti~-----------.----_-----____
"~ _~
IH __
+ _________ _
I
I
I
I
I
I
I
I
_-1________
IZ
I
I
I
...
U)
..
'5
(,)
(3
U)
I
I
r:::
o
I
:
'';::
---------t--
IZ
I
I
I
I -----------4----------J~---
---------+---
co
,~
r:::
::s
IH
--------i ~-- "'"
E
E
o(,)
CD
Q)
IT
....
-I
FIGURE 1. VOLTAGE-CURRENT CHARACTERISTICSt
tPolartty may be determined arbitrarily.
z
o-
....
o
~ZZi5i5
description
ID
(!l(!l
Q
..J..J
The TlC32040 and TLC32041 are complete
II:
ZZ
analog-to-digital and digital-to-analog input/
Q
««
~
output systems, each on a single monolithic
CMOS chip. This device integrates a bandpass
NU - Nonusable; no external connection should be made
switched-capacitor antialiasing input filter. a
to these pins.
14-bit-resolution A/D converter. four microprocessor-compatible serial port modes, a 14-bit-resolution D/A converter, and a low-pass switchedcapacitor output-reconstruction filter. The device offers numerous combinations of Master Clock input
frequencies and conversion/sampling rates, which can be changed via digital processor control.
Typical applications for this IC include modems (7.2-.8-,9.6-, 14.4-. and 19.2-kHz sampling rate). analog
interface for digital signal processors (DSPs), speech recognition/storage systems. industrial process control,
biomedical instrumentation, acoustical signal processing, spectral analysis. data acquisition. and
instrumentation recorders. Four serial modes. which allow direct interface to the TMS32011, TMS320C17.
TMS32020, and TMS320C25 digital signal processors, are provided. Also, when the transmit and receive
sections of the Analog Interface Circuit (AIC) are operating synchronously, it will interface to two SN74299
serial-to-parallel shift registers. These serial-to-parallel shift registers can then interface in parallel to the
Advanced LinCMOSTM is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA documants contain iofa,moti...
currant IS of publiCltion dlta. Prattucts conform to
.pecilieotions par tho tar..s of TO'1l Inll,u..1tI1I
:'~~~~~i~ai~:I~7.; ~'::I:~i:l' :'\":::~A!'~~ not
Copyright @ 1987. Texas Instruments Incorporated
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 665012 • DALLAS. TEXAS 76265
2-239
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
description (continued)
TMS32010, TMS320C15, other digital signal processors, or external FIFO circuitry. Output data pulses
are emitted to inform the processor that data transmission is complete or to allow the DSP to differentiate
between two transmitted bytes. A flexible control scheme is provided so that the functions of the IC can
be selected and adjusted coincidentally with signal processing via software control.
The antialiasing input filter comprises seventh-order and fourth-order CC-type (Chebyshev/elliptic
transitional) low-pass and high-pass filters, respectively, and a fourth-order equalizer. The input filter is
implemented in switched-capacitor technology and is preceded by a continuous time filter to eliminate
any possibility of aliasing caused by sampled data filtering. When no filtering is desired, the entire composite
filter can be switched out of the signal path. A selectable, auxiliary, differential analog input is provided
for applications where more than one analog input is required.
-t
CD
The A/D and D/A converters each have 14 bits of resolution with 10 bits of integral linearity guaranteed
over any 1O-bit range. The A/D and D/A architectures guarantee no missing codes and monotonic operation.
An internal voltage reference is provided on the TLC32040 to ease the design task and to provide complete
control over the performance of the IC. The internal voltage reference is brought out to a pin and is avai!able
to the designer. Separate analog and digital voltage supplies and grounds are provided to minimize noise
and ensure a wide dynamic range. Also, the analog circuit path contains only differential circuitry to keep
noise to an absolute minimum. The only exception is the DAC sample-and-hold, which utilizes pseudodifferential circuitry.
CD
C')
o
3
3
c:
::::I
,;"
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o·
::::I
The output-reconstruction filter is a seventh-order CC-type (Chebyshev/elliptic transitional low-pass filter
with a fourth-order equalizer) and is implemented in switched-capacitor technology. This filter is followed
by a continuous-time filter to eliminate images of the digitally encoded Signal.
n
The TLC320401 and TLC32041I are characterized for operation from -40°C to 85°C, and the TLC32040C
and TLC32041 C are characterized for operation from OOC to 70°C .
r+
t.n
...
C')
c:
;::j," functional block diagram
t.n
BANDPASS FILTER
SERIAL
PORT
IN+
IN-
,-
AUX IN+
AUX IN__
R~EI~S~TI~ _ _ _ _
J
-,
I
I
ONLY!
L.: _ _
:I
I
-.J
lOW·PASS FILTER
OUT + +-+-----1
OUT -
1f
+-r-----i
TRANSMIT SECTION
vcc+ vcc- ANLG DTGl VDD
GND GND (DIG!
2-240
TEXAS •
INSfRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TLC320401. TLC32040C
TLC320411. TLC32041C
ANALOG INTERFACE CIRCUITS
PRINCIPLES OF OPERATION
analog input
Two sets of analog inputs are provided. Normally, the IN + and IN - input set is used; however, the auxiliary
input set, AUX IN + and AUX IN -, can be used if a second input is required. Each input set can be operated
in either differential or single-ended modes, since sufficient common-mode range and rejection are provided.
The gain for the IN +, IN -, AUX IN +, and AUX IN - inputs can be programmed to be either 1, 2, or 4
(see Table 2). Either input circuit can be selected via software control. It is important to note that a wide
dynamic range is assured by the differential internal analog architecture and by the separate analog and
digital voltage supplies and grounds.
AID bandpass filter, AID bandpass filter clocking, and AID conversion timing
The AID bandpass filter can be selected or bypassed via software control. The frequency response of this
filter is presented in the following pages. This response results when the switched-capacitor filter clock
frequency is 288 kHz. Several possible options can be used to attain a 288-kHz switched-capacitor filter
clock. When the filter clock frequency is not 288 kHz, the filter transfer function is frequency-scaled by
the ratio of the actual clock frequency to 288 kHz. The low-frequency roll-off of the high-pass section
is 300 Hz. However, the high-pass section low-frequency roll-off can be changed to 200 Hz with a metalmask option.
The Internal Timing Configuration and AIC DX Data Word Format sections of this data sheet indicate the
many options for attaining a 288-kHz bandpass switciled-capacitor filter clock. These sections indicate
that the RX Counter A can be programmed to give a 288-kHz bandpass switched-capacitor filter clock
for several Master Clock input frequencies.
The AID conversion rate is then attained by frequency-dividing the 288-kHz bandpass switched-capacitor
filter clock with the RX Counter B. Thus, unwanted aliasing is prevented because the AID conversion rate
is an integral submultiple of the bandpass switched-capacitor filter sampling rate, and the two rates are
synchronously locked.
AID converter performance specifications
Fundamental performance specifications for the AID converter circuitry are presented in the AID converter
operating characteristics section of this data sheet. The realization of the AID converter circuitry with
switched-capacitor techniques provides an inherent sample-and-hold.
analog output
The analog output circuitry is an analog output power amplifier. Both non inverting and inverting amplifier
outputs are brought out of the IC. This amplifier can drive transformer hybrids or low-impedance loads
directly in either a differential or single-ended configuration.
DIA low-pass filter, DIA low-pass filter clocking, and DIA conversion timing
The frequency response of this filter is presented in the following pages. This response results when the
low-pass switched-capacitor filter clock frequency is 288 kHz. Like the AID filter, the transfer function
of this filter is frequency-scaled when the clock frequency is not 288 kHz. A continuous-time filter is provided
on the output of the DIA low-pass filter to greatly attenuate any switched-capacitor clock feedthrough.
The DIA conversion rate is then attained by frequency-dividing the 288-kHz switched-capacitor filter clock
with TX Counter B. Thus, unwanted aliasing is prevented because the DIA conversion rate is an integral
submultiple of the switched-capacitor low-pass filter sampling rate, and the two rates are synchronously
locked.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
2-241
TLC320401. TLC32040C
TLC320411. TLC32041C
ANALOG INTERFACE CIRCUITS
PRINCIPLES OF OPERATION (continued)
asynchronous versus synchronous operation
If the transmit section of the AIC (low-pass filter and DAC) and receive section (bandpass filter and ADC)
are operated asynchronously, the low-pass and band-pass filter clocks are independently generated from
the Master Clock signal. Also, the D/A and A/D conversion rates are independently determined. If the
transmit and receive sections are operated synchronously, the low-pass filter clock drives both low-pass
and bandpass filters. In synchronous operation, the A/D conversion timing is derived from, and is equal
to, the D/A conversion timing. (See description of the WORD/BYTE pin in the Pin Functional Description
Section.)
-I CIA
(I)
CD
Fundamental performance specifications for the D/A converter Circuitry are presented in the D/A converter
operating characteristics section of the data sheet. The 0/ A converter has a sample-and-hold that is realized
with a switched-capacitor ladder.
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3
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converter performance specifications
system frequency response correction
;::,
Sin x/x correction circuitry is performed in digital signal processor software. The system frequency response
can be corrected via DSP software to ± O. 1 dB accuracy to a band-edge of 3000 Hz for all sampling rates.
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~~:r~~~~:~t~~::::c:~:~s~~~~~~:s:~~~~~;~e~:~~!~a~~~;~~~~;~~~~~~:~~~~::~~!r:~ o;~~::::; Ja~!~:~
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only 1.1 % and 1.3% for sampling rates of 8 and 9.6 kHz, respectively (see the sin x/x Correction Section
for more details).
en
(')
::;' serial port
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The serial port has four possible modes that are described in detail in the Functional Pin Description Section.
These modes are briefly described below and in the Functional Description for Pin 13, WORD/BYTE.
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en
1. The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32011 and TMS320C17.
2. The transmit and receive sections are operated asynchronously, and the serial port interfaces
directly with the TMS32020 and the TMS320C25.
3. The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the TMS32011 and TMS320C 1 7.
4. The transmit and receive sections are operated synchronously, and the serial port interfaces directly
with the TMS32020, TMS320C25, or two SN74299 serial-to-parallel shift registers, which can
then interface in parallel to the TMS3201 0, TMS320C15, to any other digital signal processor,
or to external FIFO circuitry.
operation of TLC32040 with internal voltage reference
The internal reference of the TLC32040 eliminates the need for an external voltage reference and provides
overall circuit cost reduction. Thus, the internal reference eases the design task and provides complete
control over the performance of the IC. The internal reference is brought out to a pin and is available to
the designer. To keep the amount of noise on the reference signal to a minimum, an external capaCitor
may be connected between REF and ANLG GND.
2-242
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
TLC320401, TLC32040C
TLC320411, TLC32041C
ANALOG INTERFACE CIRCUITS
PRINCIPLES OF OPERATION (continued)
operation of TLC32040 or TLC32041 with external voltage reference
The REF pin may be driven from an external reference circuit if so desired. This external circuit must be
capable of supplying 250 p,A and must be adequately protected from noise such as crosstalk from the
analog input.
reset
A reset function is provided to initiate serial communications between the AIC and DSP and to allow fast,
cost-effective testing during manufacturing. The reset function will initialize all AIC registers, including
the control register. After a negative-going pulse on the RESET pin, the AIC will be initialized. This
initialization allows normal serial port communications activity to occur between AIC and DSP (see AIC DX
Data Word Format section).
....
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,:
loopback
U
This feature allows the user to test the circuit remotely. In loopback, the OUT + and OUT - pins are internally
connected to the IN + and IN - pins. Thus, the DAC bits (d15 to d2). which are transmitted to the DX
pin, can be compared with the ADC bits (d15 to d2), which are received from the DR pin. An ideal comparison
would be that the bits on the DR pin equal the bits on the DX pin. However, in practice there will be some
difference in these bits due to the ADC and DAC output offsets.
The loopback feature is implemented with digital signal processor control by transmitting the appropriate
serial port bit to the control register (see AIC Data Word Format section).
PIN
NAME
NO.
ANlG GND
17,18
AUX IN+
24
DESCRIPTION
I/O
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~
,~
C
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G)
Analog ground return for all internal analog circuits. Not internally connected to DGTl GND.
I
II)
Noninverting auxiliary analog input stage. This input can be switched into the bandpass filter and AID converter
I-
path via software control. If the appropriate bit in the Control register is a 1, the auxiliary inputs will replace
the IN + and IN - inputs. If the bit is a 0, the IN + and IN,- inputs will be used (see the
Ale ox
Data Word
Format section).
AUX IN-
23
I
Inverting auxiliary analog input (see the above AUX IN + pin description).
DGTl GND
DR
9
5
a
This pin is used to transmit the ADC output bits from the Ale to the TMS320 serial port. This transmission
OX
12
I
3
a
Digital ground for all internal logic circuits. Not internally connected to ANLG GND.
of bits from the AIC to the TMS320 serial port is synchronized with the SHIFT ClK signal.
This pin is used to receive the OAC input bits and timing and control information from the TMS320. This serial
transmission from the TMS320 serial port to the AIC is synchronized with the SHIFT ClK signal.
EODR
(See the WORD/BYTE pin description and the Serial Port Timing Diagram.) During the word-mode
timing, this signal is a low-going pulse that occurs immediately after the 16 bits of AID information have been
transmitted from the Ale to the TMS320 serial port. This Signal can be used to interrupt a microprocessor
upon completion of serial communications. Also, this signal can be used to strobe and enable external serialto-parallel shift registers, latches, or external FIFO RAM, and to facilitate parallel data bus communications
between the Ale and the serial-to-parallel shift registers. During the byte-mode timing, this signal goes low
after the first byte has been transmitted from the Ale to the TMS320 serial port and is kept low until the
second byte has been transmitted. The TMS32011 can use this low-going signal to differentiate between
the two bytes as to which is first and which is second.
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-243
TLC320401. TLC32040C
TLC320411. TLC32041C
ANALOG INTERFACE CIRCUITS
PIN
NAME
EODX
NO.
11
I/O
OESCRIPTION
0
(See the WORD/BYTE pin description and the Serial Port Timing Diagram.) During the word-mode
timing. this signal is a low-going pulse that occurs immediately after the 16 bits of D/A converter and control
or register information have been transmitted from the TMS320 serial port to the AIC. This signal can be used
to interrupt a microprocessor upon the completion of serial communications. Also. this signal can be used
to strobe and enable external serial-to-parallel shift registers, latches, or an external FIFO RAM, and to facilitate
parallel data-bus communications between the AIC and the serial-to-parallel shift registers. During the bytemode timing, this signal goes low after the first byte has been transmitted from the TMS320 serial port to
the AIC and is kept low until the second byte has been transmitted. The TMS32011 can use this low-going
signal to differentiate between the two bytes as to which is first and which is second.
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3
3
FSR
4
0
the AIC via the DR pin of the AIC. The most significant DR bit will be present on the DR pin before FSR goes
low. (See Serial Port Timing and Internal Timing Configuration Diagrams.)
FSX
14
0
the
~
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r+
0"
When this pin goes low, the TMS320 serial port will begin transmitting bits to the AIC via the
OX pin of the AIC. In all serial transmission modes, which are described in the WORD/BYTE pin description,
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In the serial transmission modes, which are described in the WORD/BYTE pin description, the FSR pin is held
low during bit transmission. When the F§R pin goes low, the TMS320 serial port will begin receiving bits from
FS'X
pin is held low during bit transmission (see Serial Port Timing and Internal Timing Configuration
Diagrams).
IN+
INMSTR CLK
Noninverting input to analog input amplifier stage
26
I
25
I
Inverting input to analog input amplifier stage
6
I
The Master Clock signal is used to derive all the key logic signals of the AIC, such as the Shift Clock, the
~
switched-capacitor filter clocks, and the A/D and D/A timing signals. The Internal Timing Configuration diagram
til
shows how these key signals are derived. The frequencies of these key signals are synchronous submultiples
(")
of the Master Clock frequency to eliminate unwanted aliasing when the sampled analog signals are transferred
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between the switched-capacitor filters and the AID and D/A converters (see the Internal Timing Configuration).
n
OUT+
22
0
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til
OUT-
21
0
c
Noninverting output of analog output power amplifier. Can drive transformer hybrids or high-impedance loads
directly in either a differential or a
REF
8
RESEi'
2
single~ended
configuration.
Inverting output of analog output power amplifier. Functionally identical with and complementary to OUT +.
I/O For the TLC32040, the internal voltage reference is brought out on this pin. For the TLC32040 and TLC32041,
an external voltage reference can be applied to this pin.
I
A reset function is provided to initialize the .TA, TA', TB, RA, RA', RB, and control registers. This
reset function initiates serial communications between the Ale and DSP. The reset function will initialize all
AIC registers including the control register. After a
negative~going
pulse on the RESET
pin, the Ale registers will be initialized to provide an 8-kHz data conversion rate for a 5.184-MHz master clock
input signal. The conversion rate adjust registers, TA' and RA', will be reset to 1. The CONTROL register bits
will be reset as follows (see AIC OX Data Word Format section).
d7
= 1, d6 =
1, d5
=
1, d4
= O,d3 = 0,
d2
=
1
This initialization allows normal serial-port communication to occur between Ale and DSP.
SHIFT CLK
10
0
The Shift Clock signal is obteined by dividing the Master Clock signal frequency by four. This signal is used
to clock the serial data transfers of the AIC, described in the WORD/llV'I'E pin description
below ·(see the Serial Port Timing and Internal Timing Configuration diagram).
VDD
7
Digital supply voltage, 5 V ± 5%
VCC+
20
Positive analog supply voltage, 5 V ± 5%
VCC
19
Negative analog supply voltage - 5 V ± 5%
2-244
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 656012 • DAllAS, TEXAS 75265
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
PIN
NAME
NO.
WORD/BYTE 13
1/0
DESCRIPTION
I
This pin, in conjunction with a bit in the CONTROL register, is used to establish one of four serial
modes. These four serial modes are described below.
Ale transmit and receive sections are operated asynchronously.
The following description applies when the AIC is configured to have asynchronous transmit and receive sections.
If the appropriate data bit in the Control register is a 0 (see the AIC OX Data Word Formatl. the transmit and
receive sections will be asynchronous.
L
Serial port directly interfaces with the serial port of the TMS32011 and communicates in two
a-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams).
1. The
FSX or
FSR pin is brought low.
2. One 8-bit byte is transmitted or one a-bit byte is received.
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3. The ~ or"EOl5Fl pin is brought low.
4. The
FSX or FSR
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pin emits a positive frame-sync pulse that is
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four Shift Clock cycles wide.
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5. One 8-bit byte is transmitted or one 8-bit byte is received.
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6. The EO OX or EO DR pin is brought high.
In
7. The FSX or FSR pin is brought high.
H
Serial port directly interfaces with the serial port of the TMS32020 and communicates in one
16-bit word. The operation sequence is as follows (see Serial Port Timing diagrams):
1. The
FSX or
FSR pin is brought low.
3. The FSX or FSR pin is brought high.
EOl5R pin
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2. One l6-bit word is transmitted or one 16-bit word is received.
4. The EOQ5( or
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emits a low-going pulse.
Ale transmit and receive sections are operated synchronously.
If the appropriate data bit in the Control register is a 1, the transmit and receive sections will be configured
to be synchronous. In this case, the bandpass switched-capacitor filter and the AID conversion timing will
be derived from the TX Counter A, TX Counter B, and TA, TA', and TB registers. rather than the RX Counter
A, RX Counter B, and RA, RA', and R8 registers. In this case. the AIC FSX and FSR timing will be identical
during primary data communication; however, FSR will not be asserted during secondary data communication
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since there is no new AID conversion result. The synchronous operation sequences are as follows (see Serial
Port Timing diagrams).
L
Serial port directly interfaces with the serial port of the TMS32011 and communicates in two
8-bit bytes. The operation sequence is as follows (see Serial Port Timing diagrams):
1. The FSX and FSR pins are brought low.
2. One a-bit byte is transmitted and one a-bit byte is received.
3. The EoDX and EODR pins are brought low.
4. The FSX and J!mi pins emit positive frame-sync pulses that are
four Shift Clock cycles wide.
5. One 8-bit byte is transmitted and one 8-bit byte is received.
6. The EODX and EODR pins are brought high.
7. The FSX and J!mi pins are brought high.
H
Serial port directly interfaces with the serial port of the TMS32020 and communicates in one
16-bit word. The operation sequence is as follows (see Serial Port Timing diagrams):
1. The
FSX and
FSR pins are brought low.
2. One l6-bit word is transmitted and one l6-bit word is received.
3. The
FSX and FSR pins are
brought high.
4. The EO OX or EoDR pins emit low-going pulses.
Since the transmit and receive sections of the AIC are now synchronous. the AIC serial port, with additional
NOR and AND gates. will interface to two SN74299 serial-to-parallel shift registers. Interfacing the AIC to
the SN74299 shift register allows the AIC to interface to an external FIFO RAM and facilitates parallel. data
bus communications between the AIC and the digital signal processor. The operation sequence is the same
as the above sequence (see Serial Port Timino diaorams).
TEXAS ~
INSTRUMENlS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-245
TLC320401, TLC32040C
TLC32041I, .TLC32041 C
ANALOG INTERFACE CIRCUITS
INTERNAL TIMING CONFIGURATION
r-----------,
- - - _____ ----.I
MASTER CLOCK
5.184 MHz 11)
10.388 MHz (2)
-I
CD
(')
CLOCK (1)
o
COMMERCIAL
EXTERNAL
FRONT-END
SHIFT CLOCK
1.296 MHz (1)
2.592 MHz (2)
DIVIDE BY 4
OPTIONAL EXTERNAL CIRCUITRY
FOR FULL-DUPLEX MODEMS
-:;S76kHz- --,
CD·
3
3
c
,
------,
LOW-PASS
SWITCHED
CAP FILTER
CLK - 268 kHz
SQUARE WAVE
DIVIDE BY 2
I
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I
F~~~~:'~ I
IL __________
FILTERSt
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TX COUNTER
TB-40; 7.2
TB- 38; 8.0
TB- 30; 9.8
TB-20; 14.4
TB-15; 19.2
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B
kHz
kHz
kHz
kHz
kHz
DIA
CONVERSION
FREQUENCY
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DIVIDE BY 2
BANDPASS
SWITCHED
CAP FILTER
eLK - 288 kHz
SQUARE WAVE
RX COUNTER B
RB-40; 7.2 kHz
RB-36; 8.0 kHz
RB-30; 9.6kHz
RB - 20; 14.4 kHz
RB-15; 19.2 kHz
AID
CONVERSION
FREQUENCY
(')
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(I)
________ J
L ____ _
SCF Clock Frequency =
Master Clock Frequency
2 x Contents of Counter A
NOTE; Frequency 1. 20.736 MHz. is used to show how 153.6 kHz (for a commercially available modem split-band filter clock). popular
speech and modem sampling signal frequencies. and an internal 288-kHz switched-capacitor filter clock can be derived synchronously
and as submultiples of the crystal oscillator frequency. Since these derived frequencies are synchronous submultiples of the crystal
frequency. aliasing does not occur as the sampled analog signal passes between the analog converter and switched-capacitor filter
stages. Frequency 2. 41.472 MHz. is used to show that the AIC can work with high-frequency signals. which are used by highspeed digital signal processors.
tSplit-band filtering can alternatively be performed after the analog input function via software in the TMS320.
*These control bits are described in the AIC OX Data Word Format section.
2-246
TEXAS
..If
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 15265
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
explanation of internal timing configuration
All of the internal timing of the AIC is derived from the high-frequency clock signal that drives the Master
Clock input pin. The Shift Clock signal, which strobes the serial port data between the AIC and DSP, is
derived by dividing the Master Clock input signal frequency by four.
SCF Clock Frequency
=
Conversion Frequency
Shift Clock Frequency =
Master Clock Frequency
2 x Contents of Counter A
SCF Clock Frequency
Contents of Counter B
...
'S
Master CLock Frquency
CI)
4
TX Counter A and TX Counter B, which are driven by the Master Clock signal, determine the D/A conversion
timing. Similarly, RX Counter A and RX Counter B determine the AID conversion timing. In order for the
switched-capacitor low-pass and bandpass filters to meet their transfer function specifications, the
frequency of the clock inputs of the switched-capacitor filters must be 288 kHz. If the frequencies of the
clock inputs are not 288 kHz, the filter transfer function frequencies are scaled by the ratios of the clock
frequencies to 288 kHz. Thus, to obtain the specified filter responses, the combination of Master Clock
frequency and TX Counter A and RX Counter A values must yield 288-kHz switched-capacitor clock signals.
These 288-kHz clock signals can then be divided by the TX Counter Band RX Counter B to establish the
D/A and AID conversion timings.
TX Counter A and TX Counter B are reloaded every D/A conversion period, while RX Counter A and RX
Counter B are reloaded every AID conversion period. The TX Counter Band RX Counter B are loaded with
the values in the TB and RB Registers, respectively. Via software control, the TX Counter A can be loaded
with either the TA Register, the TA Register less the TA' Register, or the TA Register plus the TA' Register.
By selecting the TA Register less the TA' Register option, the upcoming conversion timing will occur earlier
by an amount of time that equals T A' times the signal period of the Master Clock. By selecting the T A
Register plus the TA' Register option, the upcoming conversion timing will occur later by an amount of
time that equals TA' times the signal period of the Master Clock. Thus, the D/A conversion timing can
be advanced or retarded. An identical ability to alter the AID conversion timing is provided. In this case,
however, the RX Counter A can be programmed via software control with the RA Register, the RA Register
less the RA' Register, or the RA Register plus the RA' Register.
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The ability to advance or retard conversion timing is particularly useful for modem applications. This feature
allows controlled changes in the AID and D/A conversion timing. This feature can be used to enhance
signal-to-noise performance, to perform frequency-tracking functions, and to generate nonstandard modem
frequencies.
If the transmit and receive sections are configured to be synchronous (see WORD/BYTE pin description),
then both the low-pass and bandpass switched-capacitor filter clocks are derived from TX Counter A. Also,
both the D/A and AID conversion timing are derived from the TX Counter A and TX Counter B. When the
transmit and receive sections are configured to be synchronous, the RX Counter A, RX Counter B, RA
Register, RA' Register, and RB Registers are not used.
TEXAS •
INSfRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
2-247
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
AIC OR or OX word bit pattem
AID or D/A MSB,
1st bit sent
1 st bit sent. of 2nd byte
AID or D/A LSB
AIC OX data word format section
COMMENTS
d1SJd141d131d121d11 Id10Jd9 1d8ld7Jd6 IdS 1d4 Id21d11 dO
primary OX serial communication protocol
.... d15 (MSB) through d2 go to the D/A
-f
0
0
.... d15 (MSB) through d2 go to the D/A
values. The TX and RX Counter 8' s are loaded with TB and RB
-1
0
1
with the TBand RB register values. NOTE: dl =0, dO= 1 will cause
the next 01 A and AID conversion periods to be changed by the
addition of T A' and RA' Master Clock cycles, in which TA' and
RA' can be positive or negative or zero. Please refer to
:s
ri'
C»
Table 1. AIC Responses to Improper Conditions.
.... d15 (MSB) through d2 go to the D/A
-1
1
0
converter register
RA - RA' register values. The TX and RX Counter B's are loaded
the next 01 A and AID conversion periods to be changed by the
subtraction of TA'and RA'Master Clock cycles, in which TA'and
(")
RA' can be positive or negative or zero. Please refer to
:;'
Table 1. AIC Responses to Improper Conditions.
(")
C
The TX and RX Counter A's are loaded with the TA - TA' and
with the TB and RB register values. NOTE: dl = 1, dO=O will cause
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::;
The TX and RX Counter A's are loaded with the TA + T A' and
RA + RA' register values. The TX and RX Counter B's are loaded
converter register
o
3
3
c
...0'
The TX and RX Counter A's are loaded with the TA and RA register
register values.
CD
CD
(")
-1
converter register
.... d15 (MSB) through d2 go to the D/A
-1
U)
1
1
The TX and RX Counter A's are loaded with the TA and RA register
values. The TX and RX Counter B's are loaded with the TB and
converter register
RB register values. After a delay of four Shift Clock cycles, a
secondary transmission will immediately follow to program the AIC
to operate in the desired configuration.
NOTE: Setting the two least significant bits to 1 in the normal transmission of DAC information (Primary Communications) to the AIC
will initiate Secondary Communications upon completion of the Primary Communications.
m
Upon completion of the Primary Communication,
will remain high for four SHIFT CLOCK cycles and will then go low and initiate
the Secondary Communication. The timing specifications for the Primary and Secondary Communications are identical. In this manner,
the Secondary Communication, if initiated, is interleaved between successive Primary Communications. This interleaving prevents
the Secondary Communication from interfering with the Primary Communications and DAC timing, thus preventing the AIC from
skipping a DAC output. It is important to note that in the synchronous mode, FSR will not be asserted during Secondary
Communications.
2-248
TEXAS ."
INSTRUMENTS
POST OFFICe. BOX 655012 • DALLAS, TEXAS 75265
TLC320401. TLC32040C
TLC32041L TLC32041C
ANALOG INTERFACE CIRCUITS
secondary OX serial communication protocol
x x 1- to TA register -I x xl - to RA register - I
xl- to TA' register -I x 1- to RA' register
-I
-I
xl- to TB register -+ I x I +- to RB register
x x x x x x x x d7 d6 d5 d4 d3 d2
0
0
1
1
0
I
0
I
d13 and d6 are MSBs (unsigned binary)
d14 and d7 are 2's complement sign bits
d 14 and d7 are MSBs (unsigned binary)
= Oil deleteslinserts the bandpass filter
= Oil disableslenables the loopback function
= Oil disableslenables the AUX IN + and AUX IN - pins
= 011 asynchronouslsynchronous transmit and receive sections
= Oil gain control bits (see Gain Control Section)
d7 = Oil gain control bits (see Gain Control Section)
I 4 - - CONTROL --+ I
d2
REGISTER
d3
d4
d5
d6
...en
reset function
.
C3
"S
A reset function is provided to initiate serial communications between the AIC and DSP. The reset function
will initialize all AIC registers, including the control register. After power has been applied to the AIC, a
negative-going pulse on the RESET pin will initialize the AIC registers to provide an 8-kHz AID and
DIA conversion rate for a 5.184 MHz master clock input Signal. The AIC,excepting the CONTROL register,
will be initialized as follows (see AIC OX Data Word Format section):
en
r::::
o
"';:;
CO
C.)
INITIALIZED
REGISTER
VALUE (HEX)
REGISTER
TA
TA'
TB
RA
RA'
RB
C.)
"2
::::s
E
9
E
oC.)
1
24
9
1
24
G)
Q)
I-
The CONTROL register bits will be reset as follows (see AIC OX Data Word Format section):
d7
= 1, d6 = 1, d5 = 1, d4
= 0, d3 = 0, d2
=1
This initialization allows normal serial port communications to occur between AIC and DSP. If the transmit
and receive sections are configured to operate synchronously and the user wishes to program different
conversion rates, only the TA, TA', and TB register need to be programmed, since both transmit and receive
timing are synchronously derived from these registers (see the Pin Descriptions and AIC OX Word Format
sections).
The circuit shown below will provide a reset on power-up when power is applied in the sequence given
under Power-Up Sequence. The circuit depends on the power supplies' reaching their recommended values
a minimum of 800 ns before the capacitor charges to 0.8 V above DGTL GND.
TLC32040/TLC32041
vcc+
+5 V
200 kll
0.5,..F
L~v~c!:c.:-J---"'--
-5 v
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-249
TLC320401. TLC32040C
TLC320411. TLC32041C
ANALOG INTERFACE CIRCUITS.
power-up sequence
To ensure proper operation of the AIC, and as a safeguard against latch-up, it is recommmended that a
Schottky diode with a forward voltage less than or equal to 0.4 V be connected from VCC _to ANLG
GNO (see Figure 17). In the absence of such a diode, power should be applied in the following sequence:
ANLG GNO and OGTL GNO, VCC-, then VCC+ and VOO. Also, no input signal should be applied until
after power-up.
AIC responses to improper conditions
The AIC has provisions for responding to improper conditions. These improper conditions and the response
of the AIC to these conditions are, presented in Table 1 below.
-I AIC register constraints
CD
The following constraints are placed on the contents of the AIC registers:
CD
C')
1. T A register must be > 1.
2. TA' register can be either positive, negative, or zero.
3. RA register must be > 1.
4. RA' register can be either positive, negative, or zero.
5. (TA register ± TA' register) must be> 1.
6. (RA register ± RA' register) must be > 1.
7. TB register must be > 1 .
o
3
3
c
2_
...0C')
Q)
TABLE 1. AIC RESPONSES TO IMPROPER CONDITIONS
:s
tit
o
T A register
+ T A' register - 0 or 1
~
T A register - T A' register
c
T A register
tit
RA register
C')
AIC RESPONSE
IMPROPER CONDITION
=0
Reprogram TX Counter A with TA register value
or 1
+ T A' register < 0
MODULO 64 arithmetic is used to ensure that e positive value is loaded into the TX Counter A,
;::;.-
i.e .. TA register
+ RA' register = 0 or 1
RA register - RA' register
=0
+ TA' register + 40 HEX is loaded into TX Counter A
Reprogram RX Counter A with RA register value
or 1
RA register
+ RA' register - 0 or 1
MODULO 64 arithmetic is used to .ensure that a positive value is loaded into RX Counter A.
T A register
= 0 or 1
= 0 or 1
= 0 or 1
= 0 or 1
AIC is shut down
i.e .. RA register
RA register
TB register
RB register
+ RA' register + 40 HEX is loaded into RX Counter A
Reprogram TB register with 24 HEX
Reprogram RB register with 24 HEX
Ale and OSP cannot communicate
Hold last DAC output
improper operation due to conversion times being too close together
If the difference between two successive O/A conversion frame syncs is less that 1/19.2 kHz, the AIC
operates improperly. In this situation, the second 01 A conversion frame sync occurs too quickly and there
is not enough time for the ongoing conversion to be completed. This situation can occur if the A and B
registers are improperly programmed or if the A + A' register or A - A' register result is too small. When
incrementally adjusting the conversion period via the A + A' register options, the designer should be very
careful not to violate this requirement (see diagram below).
~~:~E~~
FSX
~
I
I
14--0NGOING CONVERSION-.t
t2 - t1 '" 1/19.2 kHz
2-250
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
asynchronous operation - more than one receive frame sync occurring between two transmit frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. The command to use the incremental conversion period adjust option is sent to the
AIC during a FSX frame sync. The ongoing conversion period is then adjusted. However, either Receive
Conversion Period A or B may be adjusted. For both transmit and receive conversion periods, the incremental
conversion period adjustment is performed near the end of the conversion period. Therefore, if there is
sufficient time between t1 and t2, the receive conversion period adjustment will be performed during Receive
Conversion Period A. Otherwise, the adjustment will be performed during Receive Conversion Period B.
The adjustment command only adjusts one transmit conversion period and one receive conversion period.
To adjust another pair of transmit and receive conversion periods, another command must be issued during
a subsequent FSX frame (see figure below).
en
,t::
:::J
u
...
(,)
U
I
o
I
en
1II"f-----TRANSMIT CONVERSION PERIOD-----~~I
c:::
o
'~
co
(,)
I
I
'2
I
!f--RECEIVE CONV.~RECEIVE CONV.--t
PERIOD A
PERIOD B
:::I
asynchronous operation - more than one transmit frame sync occurring between two receive frame
syncs
When incrementally adjusting the conversion period via the A + A' or A - A' register options, a specific
protocol is followed. For both transmit and receive conversion periods, the incremental conversion period
adjustment is performed near the end of the conversion period. The command to use the incremental
conversion period adjust options is sent to the AIC during a FSX frame sync. The ongoing transmit conversion
period is then adjusted. However, three possibilities exist for the receive conversion period adjustment
in the diagram as shown in the figure below. If the adjustment command is issued during Transmit
Conversion Period A. Receive Conversion Period A will be adjusted if there is sufficient time between t1
and t2. Or, if there is not sufficient time between t1 and t2, Receive Conversion Period B will be adjusted.
Or, the receive portion of an adjustment command may be ignored if the adjustment command is sent
during a receive conversion period, which is already being or will be adjusted due to a prior adjustment
command. For example, if adjustment commands are issued during Transmit Conversion Periods A, B,
and C, the first two commands may cause Receive Conversion Periods A and B to be adjusted, while the
third receive adjustment command is ignored. The third adjustment command is ignored since it was issued
during Receive Conversion Period B, which already will be adjusted via the Transmit Conversion Period B
adjustment command.
I
I
I
E
E
o(,)
Q)
-;
I-
I
j4-TRANSMIT CONV.*," TRANSMIT CONV.~TRANSMIT CONV.~
PERIOD A
PERIOD B
PERIOD C
t2
FSIiU
I
~RECEIVE CONVERSION PERIOD A
U
I
~
TEXAS
Lf
I
RECEIVE CONVERSION PERIOD B---~.~I
~
INSTRUMENlS
POST OFFICE BOX 665012. DALLAS, TEXAS 76265
2-251
TLC3204D1, TLC32040C
TLC3 20411, TLC3 2041 C
ANALOG INTERFACE CIRCUITS
asynchronous operation - more than one set of primary and secondary OX serial communication
occurring between two receive frame sync (see Ale ox Data Word Format section)
The T A, T A', TB, and control register information that is transmitted in the secondary communications
is always accepted and is applied during the ongoing transmit conversion period. If there is suf~icient time
between tl and t2, the TA, RA', and RB register information, which is sent during Transmit Conversion
Period A, will be applied to Receive Conversion Period A. Otherwise, this information will be applied during
Receive Conversion Period B. If RA, RA', and RB register information has already been received and is
being applied during an ongoing conversion period, any subsequent RA, RA', or RB information that is
received during this receive conversion period will be disregarded (see diagram below).
t,
PRIMARY
-I
CD
SECONOARY
PRIMARY
r----"'I
SECONOARY
PRIMARY
.-----,
SECONOARY
,-----,
CD
n
o
3
3c
TRANSMIT
TRANSMIT
I
TRANSMIT
I
M----CONVERSION-----IIjI-----CONVERSION----t"'
__----CONVERSION----1~~
PERIOO A
PERIOO B
PERIOO C
::s
c;'
U
...0'
D)
::s
I
en
PERIOD A
(")
::::;'
n
c
I
+- RECEIVE CONVERSION_~~It------- RECEIVE CONVERSION PERIOD B-----~~~
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC + (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Output voltage, Vo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. -0.3 V to 15 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. - 0.3 V to 15 V
Digital ground voltage .............................................. -0.3 V to 15 V
Operating free-air temperature range: TLC32040l, TLC32041I ................ -40°C to 85°C
TLC32040C, TLC32041C ................. ooC to 70°C
Storage temperature range ......................................... - 65°C to 150°C
Case temperature for 10 seconds: FN package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: N package ............ 260°C
::;'
en
NOTE 1: Voltage values for maximum ratings are with respect to
2-252
vee - .
TEXAS
~
INSTRUMENlS
POST OFFICE BOX 655012· DALLAS, TEXAS 75265
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
recommended operating conditions
PARAMETER
MIN
Supply voltage, Vcc + (see Note 2)
Supply voltage, VCC _ (see Note 2)
Digital supply voltage, VDD (see Note 2)
Digital ground voltage with respect to ANLG GND, DGTL GND
NOM
5
MAX
4.75
5.25
V
-4.75
-5
-5.25
V
5
5.25
V
4.75
0
Reference input voltage, Vreflextl (see Note 2)
High-level input voltage, V,H
Load resistance at OUT + and lor OUT -, RL
4
V
2
VOO+0.3
0.8
V
100
pF
MSTR CLK frequency Isee Note 41
0.075
Analog input amplifier common mode input voltage (see Note 5)
AID or D/A conversion rate
free~air
temperature, T A
ITLC32040l, TLC320411
I TLC32040C, TLC32041 C
-40
0
V
!l
300
Load capacitance at OUT + andlor OUT -, CL
Operating
V
2
-0.3
Low-level input voltage, VIL Isee Note 3)
UNIT
5
10.368
...en
MHz
±1.5
V
19.2
kHz
85
70
°c
·S
..
C3
CJ
en
NOTES: 2. Voltages at analog inputs and outputs, REF, VCC +, and VCC _, are with respect to the ANLG GND terminal. Voltages at
digital inputs and outputs and VDD are with respect to the DGTL GND terminal.
C
3. The algebraic convention, in which the least positive (most negative) value is designated minimum, is used in this data sheet
for logic voltage levels and temperature only.
4. The bandpass and low-pass switched-capacitor filter response specifications apply only when the switched-capacitor clock
frequency is 288 kHz. For switched-capacitor filter clocks at frequencies other than 288 kHz, the filter response is shifted
";:i
CO
U
by the ratio of switched-capacitor filter clock frequency to 288 kHz.
5. This range applies when liN + - IN -) or IAUX + - AUX --) equals ± 6 V.
0
·2
~
E
E
o
CJ
CD
.G)
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
2-253
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
electrical characteristics over recommended operating free-air temperature range, Vcc+ - 5 V,
Vcc- - -5 V, Voo - 5 V (unless otherwise noted)
total device, MSTR elK frequency - 5.184 MHz, outputs not loaded
PARAMETER
High-level output voltage
VDD = 4.75 V, IOH = -300 p.A
VOL
low-level output voltage
VDD = 4.75 V, IOl = 2 mA
ICC+
ICC-
Supply current from VCC +
Supply current from VCC-
IDD
Supply current from VDD
Vref
Internal reference output voltage
QVref
Ci"
(")
ro
o
3
3
c
:::s
5"
....
Q)
S"
:::s
en
.-"
o
~
Typt
MAX
2.4
V
fMSTR ClK - 10.368 MHz
3
reference voltage
Output resistance at REF
UNIT
0.4
V
25
-25
mA
7
mA
mA
3.2
V
100
ppm/·C
100
kll
receive amplifier input
Typt
MAX
AID converter offset error (filters bypassed)
10
50
mV
AID converter offset error (filters in)
10
50
mV
PARAMETER
CMRR
TEST CONDITIONS
Common-mode rejection ratio at IN +, IN - ,
MIN
See Note 6
or AUX+, AUXInput resistance at IN +, IN-
'I
or AUX IN+, AUX IN-, REF
UNIT
55
d8
100
kll
transmit filter output
PARAMETER
(")
C
MIN
Temperature coefficient of internal
-f
CD
TEST CONDITIONS
VOH
TEST CONDITIONS
MIN
Output offset voltage at OUT + or OUT VOO
en
YOM
YOM
(single-ended relative to ANlG GND)
Maximum peak output voltage swing across
Rl at OUT + or OUT - (single-ended)
Rl;;' 300 II,
Offset voltage = 0
Maximum peak output voltage swing between
Rl;;,60011
OUT + and OUT - (differential output)
t All typical values are at T A = 25 ·C.
NOTE 6: The test condition is a O-dBm, 1-kHz input signal with an 8-kHz conversion rate.
2-254
TEXAS
..If
INSTRUMENlS
POST OFFice BOX 655012 • DALLAS, TEXAS 15265
Typt
MAX
15
50
UNIT
mV
±3
V
±6
V
TLC320401. TLC32040C
TLC320411. TLC32041C
ANALOG INTERFACE CIRCUITS
electrical characteristics over recommended operating free-air temperature range,
vee- - -5 V, VDD - 5 V (unless otherwise noted)
Vee +
= 5
V,
specific modem specifications, SCF clock frequency - 288 kHz
MIN
Typt
Vin - - O. 1 dB to - 30 dB referred to V ref.
See Note 7
65
70
65
70
Vin = - O. 1 dB to - 30 dB referred to V ref.
See Note 7
60
65
60
65
Vin = -0 dB to -30 dB referred to Vref.
See Note 7
65
70
65
70
Vin = -0 dB to -30 dB relerred to Vrel.
See Note 7
60
60
65
65
PARAMETER
TEST CONDITIONS
Anenuation of second harmonic of
single-ended
AID input signal
Attenuation of third and higher
harmonics of AID input signal
differential
Attenuation of second harmonic of
single-ended
DIA input signal
differential
single-ended
differential
Attenuation of third and higher
single-ended
harmonics of D/A input signal
differential
MAX
UNIT
dB
dB
dB
dB
:::l
CJ
,!::
gain and dynamic range
PARAMETER
TEST CONDITIONS
Absolute transmit gain tracking error while transmitting
- 48 dB to 0 dB signal range
into 600
n (see
Note 81
MIN
(0 dB relative to V ref)
- 48 dB to 0 dB signal range
Absolute receive gain tracking error (see Note 8)
10 dB relative to Vrefl
Typt
MAX
UNIT
PARAMETER
TEST CONDITIONS
Idle channel. supply signal
Vee + or Vee _ supply voltage
f=Ot030kHz
rejection ratio, receive channel
I = 30 kHz to 50 kHz
Vec + or Vec _ supply voltage
f=Ot030kHz
MIN
dB
II)
±0.05 ±0.15
dB
'';;
CO
CJ
Typt
MAX
Idle channel. supply signal
f = 30 kHz to 50 kHz
transmit-to~receive
at OUT +
(single-ended)
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TeXAS 75265
'2
:::l
E
dB
Ci)
I-
CJ
CD
45
t All typical values are at T A = 25°C.
NOTES: 7. The test condition is a 1-kHz input signal with an 8-kHz conversion rate. The load impedance lor the DAC is 600
B. Gain tracking is relative to the absolute gain at 1-kHz and 0 dB (0 dB relative to V rell.
o
E
o
30
80
c
dB
45
at 200 mV pop measured
rejection ratio, transmit channel
UNIT
30
at 200 mV pop measured
at DR (ADC outputl
o
±0.05 ±0.15
power supply rejection and crosstalk attenuation
Isingle-ended)
Crosstalk attenuation,
II)
,t:::
dB
n.
2-255
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
delay distortion. SCF clock frequency - 288 kHz ± 2%. input (IN +
- IN -) is ± 3-V sinewave
Please refer to filter response graphs for delay distortion specifications.
bandpass filter transfer function with 300-Hz high-pass roll-off (see curves). SCF clock
frequency = 288 kHz ± 2%. input (IN + - IN -) is a ± 3-V sinewave (see Note 9)
PARAMETER
TEST CONDITIONS
MIN
MAX
-45
1= 100 Hz
I = 150 Hz
Gain relative to gain at 1 kHz
-t
CD
n
o
CD
PARAMETER
:::I
Gain relative to gain at 1 kHz
-33
-0.5
I = 4 kHz
0.5
-16
I '" 4.6 kHz
-60
TEST CONDITIONS
MIN
MAX
dB
-12
1=150Hz
Input signal reference is 0 dB
...
300 Hz s i s 3.4 kHz
UNIT
-37
I = 100 Hz
$I)
0'
:::I
300 Hz s i s 3.4 kHz
bandpass filter transfer function with 200-Hz high-pass roll-off (see curves). SCF clock
frequency" 288 kHz ± 2%. input (IN + - IN -) is a ± 3-V sinewave (see Note 9)
3
3
c
c;'
Input signal reference is 0 dB
UNIT
-0.5
I = 4 kHz
0.5
-16
I '" 4.6 kHz
-60
dB
low-pass filter transfer function. SCF clock frequency - 288 kHz ± 2% (see Note 9)
(I)
PARAMETER
(")
TEST CONDITIONS
I
::;'
n
c
;:;:
Gain relative to gain at 1 kHz
Output signal reference is 0 dB
(I)
s
3.4 kHz
MIN
MAX
-0.5
0.5
-6
f = 3.6 kHz
I = 4 kHz
-30
f '" 4.4 kHz
-60
UNIT
dB
serial port
PARAMETER
TEST CONDITIONS
-300 ~A
VOH
High·level output voltage
IOH -
VOL
Low-level output voltage
IOL = 2 rnA
II
Input current
MIN
TVPt
MAX
2.4
UNIT
V
CI
Input capacitance
15
Co
Output capacitance
15
0.4
V
±10
~A
pF
pF
t All typical values are at T A = 25°C.
NOTE 9: The above filter specifications are guaranteed lor a switched-capacitor Iilter clock range 01 288 kHz ± 2%. For switched-capacitor
filter clocks at frequencies oth,er than 288 kHz ± 2%, the filter response is shifted by the ratio of switched-capacitor filter clock
Irequency to 288 kHz.
2-256
TEXAS ~
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS, TeXAS 75265
TLC320401. TLC32040C
TLC320411. TLC32041 C
ANALOG INTERFACE CIRCUITS
operating characteristics over recommended operating free-air temperature range, Vcc+ = 5 V,
Vcc- - -5 V, Voo - 5 V
AID converter (2's complement output, 14-bit resolution)
PARAMETER
Integral nonlinearity. f
= 4.5
TEST CONDITIONS
kHz to 19.2 kHz
(See Note 10)
Conversion rate
Signal-ta-distortion ratio (Vin
- 18 dB to - 3 dB with gain
bit 1 thru bit 10
Sixteenth full scale
bit 2 thru bit 11
Eighth full scale
bit 3 thru bit 1 2
Quarter full scale
bit 4 thru bit 1 3
Half full scale
bit 5 thru bit 14
Full scale
MIN
TVpt
1
= -0.1 dB to -18dBor
= 4X. 0 dB relative to V ref)
1-kHz input signal with
an 8-kHz conversion
Equivalent input noise (relative to 600 C! at the AOC input)
MAX
±Y:t
±Y:z
±Y:z
±Y:z
±Y:z
bit 1
bit 2
bit 3
bit 4
bit 5
20
60
Inputs grounded
UNIT
kHz
65
dB
75
IlV rrns
II)
,~
..
C3
:::s
(.)
DIA converter (2's complement input, 14-bit resolution)
PARAMETER
TEST CONDITIONS
bit 1 thru bit 10
Integral linearity. f
= 4.5
kHz to 19.2 kHz
(See Note 10)
Signal-ta-distortion ratio (Vin
=
bit 2 thru bit 11
Eighth full scale
bit 3 thru bit 12
Quarter full scale
bit 4 thru bit 1 3
Half full scale
bit 5 thru bit 14
Full scale
-0.1 dB to -18 dB.
o dB relative to Vref)
MIN
TVpt
I-kHz input signal into 600 C!
with an 8-kHz conversion rate
MAX
±Y:z
±Y:z
±Y:z
±Y:z
±Y2
Sixteenth full scale
60
II)
s:::
o
'';:;
ca
,~
s:::
bit 1
bit 2
bit 3
bit 4
bit 5
65
1
Conversion time
UNIT
:::s
dB
20
E
E
o(.)
kHz
noise (measurement includes low-pass and bandpass switched-capacitor filters)
CD
TEST CONDITIONS
TVP
OX input = 00000000000000. constant input code
PARAMETER
I single-ended
I
Transmit noise
differential
UNIT
200
225
p,V rms
300
350
p.V rms
9
Receive noise (see Note 11)
300
Inputs grounded. gain = 1
"'i
MAX
....
dBrncO
350
9
/A-V rms
dBrncO
timing requirements
serial port recommended input signals
PARAMETER
tc(MCLK)
Master clock cycle time
trfMCLKl
Master clock rise time
Master clock fall time
Master clock duty cycle
tUMCLKl
REm pulse
MIN
42%
duration fsee Note 121
tsufOX)
OX setup time before SCLKI
thfDXl
OX hold time after SCLKI
MAX
UNIT
ns
95
10
ns
10
ns
58%
800
ns
20
ns
tcfSCLKl/2
ns
t All typical values are at T A = 25°C.
NOTES: 10. Integral linearity for the AID and DIA converters is guaranteed over the conversion frequency range of 4.5 kHz to 19.2 kHz.
Over this range the slew rates of the AID and DIA converters' sample~and~hold circuits are adequate to guarantee the above
integral linearitv specifications.
11. This noise is referred to the input with a buffer gain of one. If the buffer gain is two or four, the noise figure will be correspondingly
reduced. The noise is computed by statistically evaluating the digital output of the AID converter.
12. iiESE'i' pulse duration is the amount of time that the reset pin is held below 0.8 V after the power supplies have reached
their recommended values.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-257
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
operating characteristics over recommended operating free-air temperature range.
VCC- .. -5 V. VOO - 5 V (continued)
Vcc+ - 5 V.
serial port - AIC output signals
PARAMETER
MIN
Shift clock (SCLK) cycle time
MAX
380
UNIT
ns
t<;lSCLKL
tf(SCLK)
Shift clock (SCLK) fall time
50
ns
tr(SCLK)
Shift clock (SCLK) rise time
50
ns
Shift clock (SCLK) duty cycle
45
55
%
tdICH-FLl
Delay from SCLKi to FSRIFSXl
90
ns
td(CH-FHI
Delay from SCLKi to FSRIFSXt
90
ns
td(CH-DR)
DR valid after SCLKt
90
ns
tdw(CH-ELI
Delay from SCLKt to EODX/EODRl in word mode
90
ns
tdw(CH-EHI
Delay from SCLKt to EODXIEODRt in word mode
90
ns
tf(EODX)
EODX fall time
15
ns
tf(EODRI
EO DR fall time
15
ns
tdb(CH-EL)
Delay from SCLKt to EODXIEODRl in byte mode
100
ns
tdb(CH-EH)
Delay from SCLKt to EODXIEODRt in byte mode
100 '
ns
TABLE 2. GAIN CONTROL TABLE
(ANALOG INPUT SIGNAL REQUIRED FOR FULL-SCALE AID CONVERSION)
CONTROL REGISTER BITS
INPUT CONFIGURATIONS
d8
d7
Differential configuration
1
1
Analog input = IN+ - IN-
0
0
=
AID CONVERSION
RESULT
±6 V
full-scale
full-scale
1
0
±3 V
0
1
±1.5 V
full-scale
Single-ended configuration
1
1
±3 V
half-scale
Analog input = IN + - ANLG GND
0
1
0
±3 V
full-scale
0
1
±1.5 V
full-scale
=
AUX+ - AUX-
ANALOG INPUTt
AUX + - ANLG GND
0
t In this example, Vref is assumed to be 3 V. In order to minimize distortion, it is recommended that the analog input
not exceed 0,1 dB below full scale.
Rib
Rib
R
IN + -"No'-'-f
R
IN -
-"""..-.-1
J-,-....-
~
R
AUX IN + -"No............
TO MUX
Rfb - R for d6 - 1. d7 d6 - O. d7 Rib - 2R for d6 .. 1.d7
Rib - 4R for d8 - O. d7
1. d7 - 1
O. d7 - 0
- 1. d7 - 0
- O. d7 - 1
FIGURE 1. IN + AND IN - GAIN
CONTROL CIRCUITRY
2-258
TO MUX
Rib
Rfb
Rfb - Rlord6 d6 Rib - 2R for d6
Rib - 4R lor d6
~
R
AUX IN - - " " "...........
1
0
- 0
- 1
FIGURE 2. AUX + AND AUX - 'GAIN
CONTROL CIRCUITRY
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75285
TLC32040l, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
sin xIx correction section
The AIC does not have sin xIx correction circuitry after the digital-to-analog converter. Sin xIx correction
can be accomplished easily and efficiently in digital signal processor (DSP) software. Excellent correction
accuracy can be achieved to a band edge of 3000 Hz by using a first-order digital correction filter. The
results, which are shown below, are typical of the numerical correction accuracy that can be achieved
for sample rates of interest. The filter requires only seven instruction cycles per sample on the
TMS320 DSPs. With a 200-ns instruction cycle, nine instructions per sample represents an overhead factor
of 1.4% and 1.7% for sampling rates of 8000 Hz and 9600 Hz, respectively. This correction will add a
slight amount of group delay at the upper edge of the 300-3000-Hz band.
sin x/x roll-off for a zero-order hold function
The sin xIx roll-off for the AIC DAC zero-order hold function at a band-edge frequency of 3000 Hz for
the various sampling rates is shown in the table below.
TABLE 3. sin xIx ROLL-OFF
20 log .in
f. (Hz)
1r
II)
..
C3
CJ
II)
flf.
c
r f/f.
o
(f - 3000 Hz)
'';:;
ca
CJ
'2
(dB)
7200
8000
9600
14400
19200
...
'S
-2.64
-2.11
-1.44
-0.63
-0.35
:l
E
E
o
Note that the actual AIC sin xIx roll-off will be slightly less than the above figures, because the AIC has
less than a 100 percent duty cycle hold interval.
CJ
Q)
"i
I-
correction filter
To compensate for the sin xIx roll-off of the AIC, a first-order correction filter shown below, is recommended.
U(i+1)
t - - - - - - - - - - - - . - - - + V ( i + 1)
The difference equation for this correction filter is:
Yi+1 = p2(1-p1) (Ui+1)+p1 Yi
where the constant p1 determines the pole locations.
The resulting squared magnitude transfer function is:
IH(f)12 =
p22 (1-p1)2
1 - 2p1 cos(2 11" flfs) + p1 2
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 666012 • DALLAS, TEXAS 75265
2-259
TLC320401. TLC32040C
TLC320411. TLC32041C
ANALOG INTERFACE CIRCUITS
correction results
Table 4 below shows the optimum p values and the corresponding correction results for 8000 Hz and
9600 Hz sampling rates.
TABLE 4
11Hz)
300
600
900
1200
1500
1800
2100
2400
2700
3000
-t
CD
CD
(')
o
3
3
c:
;:,
(;'
C»
r+
S'
;:,
ERROR IdB)
ERROR IdB)
Is - 8000 Hz
pl - -0.14813
p2 - 0.9888
-0.099
-0.089
--0.054
-0.002
0.041
0.079
0.100
0.091
-0.043
-0.102
I. - 9600 Hz
pl - -0.1307
p2 = 0.9951
-0.043
-0.043
0
0
0
0.043
0.043
0.043
0
-0.043
TMS320 software requirements
en
The digital correction filter equation can be written in state variable form as follows:
(')
Y = klY +k2U
~'
a'
en
(')
where kl equals pl (from the preceding page), k2 equals (1-pl)p2 (from the preceding page), Y is the
filter state, and U is the next I/O sample. The coefficients k 1 and k2 must be represented as l6-bit integers.
The SACH instruction (with the proper shift) will yield the correct result. With the assumption that the
TMS320 processor page pointer and memory configuration are properly initialized, the equation can be
executed in seven instructions or seven cycles with the follOWing program:
ZAC
LT K2
MPY U
LTA Kl
MPY Y
APAC
SACH (dmal. (shift)
2-260
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
TlC320401, TlC32040C
TlC320411, TlC32041 C
ANALOG INTERFACE CIRCUITS
byte-mode timing
~,..tfISClK)
SHIFT ClK
tdICH-Fll~ ~
I
I
I
I
I
,
...., .. t'ISClK)
I
0.8
I
I
~ "'tdICH-FHI
V
I
~ It-tdICH-Fll
I
tdICH-FH~ ~
~I-C_ _ _~12 v
0.8
v\.~1---iJ,J-l-------fJI
I
I
I ...., ~ ~dICH-ORI
DR
r-
I'
I,.,'",..._ _ _ _ _ ___.1
I
:
_~0~1~5~~~~~~--~0~8-----~~~~0-1--00_+1--~
I
I
tsulOXI~
\0-
I
I
U)
~~~~~~I-~~O~O~N~'T~C~A~R~E----{J~)[~'~
~,J 09
OBI
07
06~
-1::
::--_________-I
____I.__t-fhIOX)
4j ~tdbICH-El)
tdbICH-EH~ ItEODR,Ea6X
:I-'--------'1~~0~.8~V~__________________~fl-l-----------'~
C3
word-mode timing
-CO
OX
I
I
-it--, ,
FSX, FSR
I
0.8 VI
I
II
I
I
,
08 V
I
I
tdCCH-FHI-.j ~
0.8 V\-"-________
-
V
~
i-oj
r--tdICH-ORI
:
~O~15~~~~~0~1~-=OO~:___~_____
tsulOXl-ol
I
!.--
..
U)
c::
o
-2
2V
I I
-+--+,
______-/:I-___________.jI.'1r::2-::--r---I i
---;1
OR ___
I
~
u
~tcISClK)
,
I
SHIFT ClK
::l
u
::l
E
E
o
u
CD
G)
I-
I
I
OX------~0~1~5Q(0~14~!0~1~3~~JC~0]11~
I
-41
I
I
tdwICH-El~ It- --.( It-tdwICH-EHI
I
jo--thlOX)
EOOX,EOOR------------------------~'~'----------0-.~V~2V
FIGURE 3, SERIAL PORT TIMING
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
2-261
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
nil
TMS32010
SN74lS299
J-: S1
om
-
AD/PAD
G1
A
A1/PA1
8
A2/PA2
C
V1
f-Vii I-
so
\
SN74lS299
QH'
' - - - 62
SO
ClK
61
00·07
\
\,
.~
SR
"- S1
00·015
WE
nC320401
TlC32041
A·H
pro
,(
ClK< f--
lIT
08·015
SN74lS138
00·015
ox
QH'
~
A·H
-
rCl:--
-U-&
SHIFT ClK
C1
SR
10
DR
~
./
ClK OUT
r--LJ
MSTR ClK
EmlX
INT
FIGURE 4, TMS32010·TLC32040/TLC32041 INTERFACE CIRCUIT
in instruction timing
ClK OUT
_---J
I
~I----------------------------
I
I
'-----111-1·
so,
I
I
G1
00·015
---------------------~~~~:I>----------------------------------(
VALID
)
out instruction timing
ClK OUT ______
SN74lS138 V1
SN74lS299 ClK
00·015
<
VALID
)
FIGURE 5, TMS32010·TLC32040/TLC32041 INTERFACE TIMING
2·262
TEXAS . "
·INSfRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75285
TLC320401, TLC32040C
TLC320411, TLC32041C
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AIC TRANSMIT CHANNEL FILTER
10
0.3
~a9riitud~
0
-10
CD
."
..
I
.t:
.'"
Group Delay
-30
See Note 8"
-40
-50
-60
-70
111
V-
1ft
1\
\
0.1
\
\..£ 1 \./
E
I
>
'ii
.
c
0.05
...
0
C1
...en
::I
2
'S
"
0.05 .~
IV
a;
a:
0.1
c-~See Note A
IV
r+-See Note C
-80
-90
/
~
1\
C
::I!
0.2
0.15
-20
."
::I
0.25
\
~
(3
en
0.15
C
o
'';:;
0.2
o
2
3
Normalized Frequency-kHz )(
4
CIS
5
Co)
SCF clock frequency
288 kHz
'2
~
NOTES: A. Maximum relative delay (0 Hz to 600 Hz) = 125 ~s.
B. Maximum relative delay (600 Hz to 3000 hz) = ± 50 ~s.
e. Absolute delay (600 Hz to 3000 Hz) = 700 ~s.
O. Test conditions are Vee +, Vee _, and VOO within recommended operating conditions, SeF clock f = 288 kHz ± 2%,
input
± 3-V sinewave, and T A
25
=
=
·e.
FIGURE 6
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLA,S, TeXAS 75265
E
E
o
u
CD
"i
....
2-263
TLC320401, TLC32040C
TLC320411, TLC32041C
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AIC RECEIVE CHANNEL FILTER (300 Hz)
10
0.35
See Note A
MagnitJde
0
0.3
0.25
-10
.\
-20
\
III
"I
-30
.Ec
-40
~
...
-I
CD
II
:E
CD
n
-60
o
-70
3
3
-90
0
:::I
...0'
I»
(')
::;'
n
c
::+
(I)
UV\
V
1\
3
Normalized Frequency-kHz )(
NOTES: A.
B.
C.
O.
2-264
0.05
0
0.05
.e
I
>-
~
Co
~
C1
.
..,.>
-III:
0.1
\
See Note C-,
2
0.1
,
1\
-80
(;'
:::I
,
\ /
0.15
!\
\
\-
Group Delay
LSee Note B
c
(I)
-50
0.2
0.15
4
5
SCF clock frequency
288 kHz
Maximum relative delay (200 Hz to 600 Hz) = 3350 ~s.
Maximum relative delay (600 Hz to 3000 Hz) = ± 50 ~s.
Absolute delay (600 Hz to 3000 Hz) = 1230 p.s
Test conditions are VCC +. VCC _. and VOO within recommended operating conditions. SCF clock f = 288 kHz ± 2%.
input = ± 3-V sinewave. and T A = 25°C.
FIGURE 7
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 76265
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AIC RECEIVE CHANNEL FILTER (200 Hz)
10
0
-10
...I
...
"!
0.3
Ma~nitu~e
Se~
0.25
Noie A
0.2
1\
-20
0.15
\
CD
-30
'"
II
::E
-50
-60
_roup Delay
l'
.., 1 I
r--t--See Nre
1
V
E
I
>
II
0.1
II
-40
VI
\
\
-70
0.05
0
0.05
"\ 0.1
Qj
Q
a.
...en
2"
·S
~
..,>
II
...
(,)
II
U
Qj
a::
en
See Note C
-90
0
C
0.15
-80
o
".;::
0.2
4
5
SCF clock frequency
Normalized Frequency-kHz x
288 kHz
2
~
(,)
3
NOTES: A. Maximum relative delay 1200 Hz to 600 Hzl = 3350 I'S.
B. Maximum relative delay (600 Hz to 3000 Hz) = ± 50 I's.
e. Absolute delay (600 Hz to 3000 Hz) = 1080 I's.
D. Test conditions are Vee +, Vee _, and VOO within recommended operating conditions, SeF clock f
input = ± 3-V sinewave, and T A = 25 ·e.
FIGURE 8
TEXAS ."
INSTRUMENlS
POST OFFICE BOX 656012 • OALLAS, TEXAS 75265
·c
~
E
E
=
288 kHz ± 2%,
o
(,)
CD
Q)
I-
2-265
TLC320401. TLC32040C
TLC320411. TLC32041 C
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
AID GAIN TRACKING
(GAIN RELATIVE TO GAIN
AT 0 dB INPUT SIGNAL)
AID SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL
80
70
GAIN I-4X
III
"I
-f
~
60
'ia:
c
0
.~
0
~ 30
~
3
3
C
:::J
0.4
f-"'-..
1/
40
III
0.2
"I
0.1
I
~ignal
I
8' kHz conversion rate.
-
....
0
c -0.1
0;
m
c
I- 1 kHz' input
0.3
GAIN - 1X-
/" , /
/"
50
CD
(')
0.5
1 kHz input signal with an
8 kHz conversion rate
.;
c:l -0.2
20
'"
-0.3
iii
10
C:;'
....
I»
-0.4
o
S'
-50
:::J
-40
-30
-20
-10
o
-0.5
-50
10
-40
Input Signal Relative to V ref - dB
(I)
FIGURE 9
("')
-30
-20
-10
o
10
Input Signal Relative to Vref-dB
FIGURE 10
::;'
(')
DIA GAIN TRACKING
vs
(GAIN RELATIVE TO GAIN
AT 0 dB INPUT SIGNAL)
DIA CONVERTER SIGNAL-TO-DISTORTION RATIO
vs
INPUT SIGNAL
C
;;'
(I)
100
1 kHz input signal into 600
{l
1.0
90 8 kHz conversion rate
!Ii! 80
-
I
.
70
c
60
.g
a:
of
.,,/
/
o 50
0.6
is 40
"
{l
--1----1
~--+---I----+---I----+----I
0.4 1----+---1---+--1---+---1
"I
0.2 1----+---1---+--1---+---1
0~--4_--~---4----+---4---~
~ - 0.2 1----+---1---4---1---+---1
0;-
m
30
c
'C11
'"
iii' 20
-0.4 1---+--1---4---1---+---1
-0.6 ~--+----+-----4--+---+---~
10
o
1 kHz input signal into 600
8 kHz conversion rate
III
f
",/
0;
-50
~-~--~---,---~---,--~
0.8
-0.8 f---4----I--+---l---f------l
-40
-30
-20
-10
0
Input Signal Relative to V ref - dB
10
-1
L - _ - L_ _L - _ - L_ _L-_-L_~
-50
-40
-30
-20
-10
o
10
Input Signal Relative to Vref-dB
FIGURE 11
FIGURE 12
NOTE: Test conditions are Vee +. Vee _. and VOD within recommended operating conditons. SeF clock f
TA
2-266
= 25°e.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012. DALLAS, TeXAS 75265
=
288 kHz + 2%. and
TLC320401, TLC32040C
TLC320411, TLC32041C
ANALOG INTERFACE CIRCUITS
TYPICAL CHARACTERISTICS
ATTENUATION OF SECOND HARMONIC OF AID INPUT
vs
INPUT SIGNAL
100
...I
UI
90
.~
80
0
ATTENUATION OF THIRD HARMONIC OF AID INPUT
vs
INPUT SIGNAL
100
1\
I "-"'-II
...UI
./
90
b
80
.,~
70
'c
i
...:z:c
70
u
50
~
50
40
'0
40
30
·8
30
V-
:z:
60
1 kHz input signal
8 kHz conversion rate
,
60
"E
.,
0
(/)
'0
c
'g
"c
J
20
!
10
1 kHz input signal.
S kHz conversion rate.
o
-50
-40
-30
-20
/ 1'--/
r--..
/"'\.
....
II)
..
'S
(,)
(3
II)
20
C
o
10
-10
o
o
-50
10
-40
-30
-20
-10
o
'';::
CO
10
(,)
'2
Input Signal Relative to V reI - dB
Input Signal Relative to V rel- dB
j
FIGURE 13
FIGURE 14
ATTENUATION OF SECOND HARMONIC OF DIA INPUT
vs
INPUT SIGNAL
ATTENUATION OF THIRD HARMONIC OF DIA INPUT
vs
INPUT SIGNAL
100
...
.4
UI
90
-
80
~
70
~
60
8
50
-g
J;
100
1 kHz input signal into 600 !l
8 kHz conversion rate
/'
-
...UII
90
0
70
:z:
60
.!:!
c
E
co
~
50
40
t-
'0
40
'0
.~c;
30
.~
30
"c
~
20
c
20
E
10
o
-50
-40
-30
-20
-10
o
10
/"
=
a;
-
10
o
-50
-40
-30
-20
-10
o
Input Signal Relative to V re l-d8
Input Signal Relative to Vrel-dB
FIGURE 15
FIGURE 16
NOTE: Test conditions are Vee +. Vee _. and VOO within recommended operating conditon •• SeF clock f = 288 kHz
TA
o
(,)
Q)
I-
1 kHz input signal into 600 !l
8 kHz conversion rate
80
E
E
10
+ 2%. and
25 o e.
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 665012. DALLAS, TEXAS 75265
2-267
TLC320401, TLC32040C
TLC320411, TLC32041 C
ANALOG INTERFACE CIRCUITS
TYPICAL APPLICATION INFORMATION
TMS32020/C25
TMS32020/C25
CLKOUT
MSTR CLK
FSX
FSX
ox
ox
FSR
FSR
DR
DR
CLKR
CLKX
vcc+
REF
ANLG GNO
I\C
+5 V
1
*c
BAT42tic
VCC-
SHIFT CLK
W
*
II
-5 V
+5V
VOO
;: ::;:0.1I'F
OGTL GNO
\7
~,
C - 0.2 I'F, CERAMIC
FIGURE 17, AIC INTERFACE TO THE TMS32020/C25 SHOWING DECOUPLING CAPACITORS
AND SCHOTTKY DIODEt
VCC
R
.....- - 4 > - - - - + - - - - 3 . 0 V OUTPUT
500 II
0.011'F
TL431~--'
2500 II
FOR:
VCC - 12 V, R - 7200 II
VCC - 10 V, R - 5600 II
VCC 5 V, R - 1600 IJ
FIGURE 18. EXTERNAL REFERENCE CIRCUIT FOR TLC32041
tThomson Semiconductors
2-268
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
Designer's Information
3-1
Contents
Page
Guidelines for Handling Electrostatic-Discharge Sensitive Devices
(ESDS) and Assemblies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Qualitv and Reliability Assurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
•
3-2
3-3
3-9
Guidelines for Handling
Electrostatic-Discharge Sensitive (ESDS) Devices and Assemblies t
1.0
SCOPE
1.1
This specification establishes the requirements for methods and materials used to protect electronic devices and
assemblies which are susceptible to damage or degradation from electrostatic discharge (ESD). The electrostatic
charges referred to in this specification are generated and stored on surfaces of ordinary plastics. most common
textile garments. ungrounded human bodies. and many other commonly used materials. not generally recognized
as being electrostatic generators. The passage of these charges'through an electrostatic-sensitive device may result
in catastrophic failure or performance degradation of the part.
1.2
The part types (packaged or unpackaged) for which these requirements are applicable include. but are not limited
to the following:
(a)
(b)
(c)
(d)
(e)
(f)
1.3
1.4
All metal-oxide semiconductor (MOS) devices. e.g .. CMOS. PMOS. etc.
Junction field-effect transistors (JFET)
Bipolar digital and linear circuits
Op Amps. monolithic microcircuits with MOS compensating networks. on-board MOS capacitors. or
other MOS elements
Hybrid microcircuits
Thin film passive devices.
Detinitions
1.3.1
Conductive material: Material having a maximum surface resistivity of lOS O/square.
1.3.2 Static dissipative material: Material having surface resistivity between 105 and 109 O/square.
1.3.3 Antistatic material: Material having a surface resistivity between 109 and 1014 O/square.
1.3.4 Electrostatic discharge (ESD): A transfer of electrostatic charge between bodies at different electrostatic
potentials caused by direct contact or induced by an electrostatic field.
Surface resistivity (generally called sheet resistance or sheet resistivity): The resistance between two
1.3.5
electrodes forming opposite sides of the square. It is measured in ohms per square. and the size of the
square is immaterial.
1.3.6 Volume resistivity: Also referred to as bulk resistivity. It is normally determined by measuring the
resistance (R) ofa square of material (surface resistivity) and multiplying this value by the thickness (T).
I .3.7 Ionizer: Equipment that generates positive and negative ions. either by electrostatic means or by means
of a radioactive energy source. in an airstream. that distributes a layer of low velocity ionized air over
a work area to neutralize static charges.
1.3.8 Close proximity: For the purpose of this specification 6 inches or less.
1.3.9 Magazine: A-frame slide pack or rail for dual-in-Iine or other semiconductor packages.
1.3.10 Static: Used in this document as a short form of electrostatic.
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Device Sensitivity per Test Circuit of Method 3015, MIL-STD-883 for ICs, or Method 1020, MIL-STD-750
for Discretes
1.4.1
Devices are categorized according to their susceptibility to damage resulting from electrostatic discharge
(ESD). and the type of packaging required to adequately protect them.
1.4.1.1 Device electrostatic sensitivity
Category
ESD Sensitivity (V)
20-2000
Minimum Protective Packaging
A conductive container or an
antistatic container within an
electrostatic field shielding barrier
> 2000
An antistatic container
tBased on TI's internal ESD specification and JEDEC publication No. 108. Distributor Requirements/or Halldlillg ElectrostaticDischarge SellSitil'e (ESDS) Devices.
3-3
1.4.2
1.4.3
2.0
APPLICABLE REFERENCE DOCUMENTS
2.1
2.2
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3.0
Category "I" devices are to be identified and labCled by the device manufacturer.
Devices are to be protected from ESD damage from receipt at incoming inspection through assembly,
test, and shipment of completed equipment.
The following reference documents of the latest issue in effect can provide additional information on ESD controls.
DOD-HDBK-263 Electrostatic Discharge Control Handbook for Protection
DOD-STD-1686 Electrostatic Discharge Control Program
EIA Interim Standard IS-5-A Packaging Materials Standards for ESD Sensitive Items
MIL-M-3851O Microcircuits, General Specification
MIL-STD-883 Test Methods and Procedures for Microelectronics
MIL-S-19491 Semiconductor Devices, Packaging of
MIL-M-55565 Microcircuits, Packaging of
NAVSEA SE 003-II-TRN-01O Electrostatic Discharge Training Manual
MIL-STD-750 Test Methods for Semiconductor Devices
TRS-3A EOS/ESD Technology Abstracts (RADC)
MIL-STD-129 Marking for Shipment and Storage
MIL-S-19500 General Specification for Semiconductor Devices
In case of conflict between requirements of this document and reference documents, this document shall have
precedence.
FACILITIES FOR STATIC-FREE WORK STATION
3.1
The minimum acceptable static-free work station shall consist of the work surface covered with a static dissipative
or conductive material attached to ground through a I MO ± 10% resistor and a grounding wrist strap with integral
I MO ± 10 % resistor for each operator. The air ionizer is recommended to provide max.imum effectiveness of
the static-free work station. If the air ionizer is not used, static dissipative or conductive smocks must be worn
by the operators. The static dissipative or conductive smocks will provide some additional protection but are not
equivalent to ionizers in improving the effectiveness of the static-free work station. If it is not possible to eliminate
insulator materials at the static-free work station, the ionizer must be utilized. If the wrist strap is connected to
the static dissipative mat, rather than directly to ground. it shall be connected to the same metallic button or contact
used to ground the mat. Ground shall utilize earth ground, refer to Figure I. Conductive floor tile or mats along
with conductive shoes or heel straps may be used in lieu of the conductive wrist straps for nonseated personnel
where the use of grounded wrist strap is hazardous or impractical. The Site Safety Engineer (or person designated
by the ESD Coordinator) must review and approve all electrical connections at the static-free work station prior
to its implementation.
3.1.1
Air ionizer: Table ionizers shall be positioned so that the devices at the static· free work stations are within
a 4-foot arc measured by a vertical line from the face of the ionizer and 45 degrees on each side of
this line. The ionizer shall be aimed at the devices and operator's hands rather than at the operator. Ceiling
ionizers shall be mounted within 6 feet of the work surface. Devices shall not be brought closer than
I foot from the emitting surface of an ionizer.
3.2
General Grounding Requirements are to be in Accordance with Table·1.
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Table I. General Grounding Requirements
Handling EquipmentlHandtools
Metal Pans of Fixtures and Tools
Handling Trays/Tubes
Plastic Racks/Bins
Table Tops/Floor Mats
Personnel
Treated or
Intrinsic Antistatic or
Conductive Material
X
"'With I OM ± 10'1 safety resistor (See Figure I)
3-4
Static Dissipative
Material
Grounded to
Common Point
X
X
X
X
X
X
X
X'
X Using Wrist Strap·
THIRD WIRE
ELECTRICAL
GROUND
1
PERSONNEL
GROUND STRAP
ESD PROTECTIVE
TRAYS. ETC.
TATIC DISSIPATIVE
WORK SURFACE'
\
f
R
CHAIR
WITH GROUND
(OPTIONAL)
R
ESD PROTECTIVE
FLOOR MAT
(OPTIONAL}
1== t-'Vvv-.--.....,> R
[
IONIZER
(RECOM·
MENDED)
11
OTHER
ElEe.
EQUIP.
1
'THE STATIC DISSIPATIVE WORK SURFACE IS RECOMMENDED.
HOWEVER. ACONDUCTIVE WORK SURFACE MAY BE USED IF IT CAl
BE MAINTAIIEO IM!l ± 1011 ABOVE GROUIO.
WORK BENCH
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All electrical equipment sitting on the static dissipative work surface must be hard grounded and must be isolated from the static dissipative
work surface.
.2
NOTE: Earth ground consists of a metal pipe or rod inserted at least three (3) feet into the earth. All static-free work stations in a single
building may utilize a single earth ground.
fI)
Figure I. Static-Free Work Station
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3.3
ESD Labels and Signs in Work Areas
3.3. I
3.3.2
ESD caution signs at work stations and work areas and labels on ESDS parts and containers shall be
consistent in color. symbols. and appropriate instructions.
Signs shall be posted at all work stations performing any handling operations with ESDS items. These
signs shall contain the following information. or its equivalent.
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CAUTION
STATIC CAN DAMAGE COMPONENTS
Do not handle ESDS items unless grounding wrist strap is properly
worn and grounded. Do not let clothing contact or come in close
prOldmity to ESDS items.
3.3.3
3.3.4
3.4
Labels shall be affixed to all containers containing ESDS items at a place readily visible and proper for
the intended purpose. Additionally. labels must be consistently placed on containers and packages at
a standard location to eliminate mishandling.
The use of ESD signs and labels. and their information content shall be the responsibility of the Area
Supervisor and the ESD Coordinator to assure consistency and compatibility throughout the ESDS device
routing.
Relative Humidity Control
3.4.1
3.4.2
Since relative humidity has a signiticant impact on the generation of static electricity. where possible.
the work area should be maintained within the following relative humidity range: 40%-60%.
Where it is possible to control the relative humidity. it should be set for some value within the above
range and maintained as closely as possible to avoid static voltage monitor variations.
3-5
4.0
PREPARATION FOR WORKING AT STATIC-FREE WORK STATION
4.1
A work station with a stalic dissipative work surface connected to ground through a I MO ± 10% resistor. a
grounding wrist strap with the ground wire connected to the grounding point of the static dissipative work surface
or equivalent footware and conductive flooring per paragraph 3.1. and an ionizer or a static dissipative or conductive
smock constitute a static-free work station (Figure I). An operator is properly grounded when the wrist strap
is in snug (no slack) contact with the bare skin. usually positioned on the left wrist for a right-handed operator.
The wrist strap. or equivalent footware per paragraph 3. I. must be worn the entire time an operator is at a staticfree work station.
CAUTION
Personnel shall never be attached to ground without the presence
of the 1.0 MO ± 10% series resistor in the ground wire.
4.2
4.3
4.4
4.5
4.6
5.0
If possible. operators should avoid touching leads or contacts even though grounded.
An operator's clothing should never make contact or come in close proximity with ESDS items. Operators must
be especially careful to prevent any ESDS items (being handled) from touching their clothing. If static dissipative
or conductive smocks are not used •. long sleeves must be rolled up or covered with antistatic sleeve protector
banded to the bare wrist which shall "cage" the sleeve at least as far up as the elbow. If static dissipative or
conductive smocks are used (in lieu of air ionizers). they must completely cover long sleeves. The smock
manufacturer's cleaning instructions must be followed.
Only cotton gloves. antistatic gloves. or antistatic finger cots (free of reactive elements such as chlorine. phosphorus.
etc.) may be used when handling ESDS items.
Any person not properly prepared. as outlined in paragraphs 4.3 and 4.4 while at or near the work station. shall
not touch or come in close proximity with any ESDS items.
It is the responsibility of the operator and the Area Supervisor to ensure that the static-free work area is clear
of unnecessary static hazards. including such personal items as plastic coated cups or wrappers. plastic cosmetic
bottles or boxes. combs. tissue boxes. cigarette packages. cellophane tape. and vinyl or plastic purses. All workrelated items. including information sheets. fluid containers. tools. and parts carriers must be those approved
by the distributor ESD Coordinator for use at the static-free work station.
GENERAL HANDLING PROCEDURES AND REQUIREMENTS
5.1
5.2
All ESDS items must be received in a closed antistatic/conductive container and must not be removed from the
container except at a static-free work station. All protective folders or envelopes holding documentation (lot travelers.
etc.) shall be made of nonstatic-generating material.
Each packing (outermost) container and package (internal or intermediate) shall have a brightly colored warning
label (black letters on a yellow background) attached. stating the following information or equivalent:
CAUTION
ELECTROSTATIC
SENSITIVE
DEVICES
DO NOT OPEN DR HANDLE
EXCEPTATA
STATIC-fREE WORKSTATION
The warning label shall be legible to normal vision at a distance of 3 feet.
5.3
5.4
5.5
5.6
3-6
ESDS items are to remain in their protective containers except when actually in work at the static-free station.
Before removing the items from their protective container. the operator should:
5.4.1
Place the container on the static dissipative work station surface (see para. 5.1)
5.4.2
Make sure the wrist strap fits snugly around the wrist and is electrically connected to the ground receptacle
on the static dissipative work surface. then touch hands to the static dissipative work surface.
All operations on the items should be performed with the items in contact with the static dissipative work surface
as much as possible. Do not allow conductive magazine to touch hard grounded test gear on the work surface.
In cases where it is impossible or impractical to ground the operator with a wrist strap. a conductive shoe strap
may be used along with conductive tile/mats. per paragraph 3. I.
5.7
When the operator moves from any other place to the static-free station. the start-up procedure shall be the same
as in paragraph 4.0.
5.8 The ionizer (if used) shall be in operation prior to presenting any ESDS items to the static-free station. and shall
be in operation during the entire time period the items are at the station.
5.9 "Plastic snow" polystyrene foam. "peanuts." or other high-dielectric materials shall never come in contact with
or be used around electrostatic sensitive items. unless they have been treated with an antistat (often resulting in
a pink color) as evidenced by the generation of less than ± 100 volts when rubbed vigorously against any insulator.
5.10 ESDS items shall not be transported or stored in trays. tote boxes. vials. or similar containers made of untreated
plastic material unless items are protectively packaged in conductive material.
6.0
PACKAGING REQUIREMENTS
6.1
6.2
6.3
7.0
Packaging of ESDS items is to be in accordance with section 1.4.1. Tape and plain plastic bags are prohibited
inside the minimum protective packaging per paragraph 1.4.1.1.
Outer and inner containers are to be marked as outlined in section 5.2.
Conductive magazines/boxes may be used in lieu of conductive bags.
SPECIFIC HANDLING PROCEDURES FOR ESDS ITEMS
7.1
Stockroom Operations
7.1.1
7.1.2
7.1.3
7.1.4
7.2
Packing Operations
7.2.1
7.2.2
7.2.3
8.0
Containers of ESDS items are not to be accepted into stock unless properly packaged and adequately
identified as containing ESDS items.
Items may be removed from the protective container (magazine/bag. etc.) for the purpose of subdividing
for order issue only by a properly grounded operator at an approved static-free station as defined in
sections 3.0 and 4.0.
All subdivided lots must be carefully repackaged in protective containers (magazine/bag. etc.) prior to
removal from the static-free work station and labeled to indicate that the packagers) contain ESDS items.
If it is suspected that a ESDS item is not adequately protected. do not transfer it to another container.
return it to the originator for disposition unless the originator is a Customer. In that case, the Distributor's
Representative should contact the Customer and negotiate an appropriate disposition.
It is the responsibility of the Stockroom Supervisor to ensure that all personnel assigned to this operation
are familiar with handling procedures as outlined in this specification. A copy of this specification, or
an in-house procedure meeting the requirements of this specification, is to be available in the vicinity
so that it is accessible to the operators. Stock handlers and all others who might have occasion to move
stock are to be instructed to avoid contact with unprotected ESDS items.
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ESDS items are not to be accepted into the packing area unless they are contained in a static-protected
bag or conductive container.
An ESDS item delivered to the packer within an approved container or bag and found to be in order
regarding identification shall be packed in the standard shipping carton or other regular packaging material.
Containers are to be labeled in accordance with section 5.2.
Any void-fillers shall be made of an approved material.
AUDIT PROVISIONS
8.1
ESD Coordinator: An ESD coordinator shall be appointed for each site to assure that the following requirements
are met.
8.2
Auditing
8.2. I
8.2.2
Each operation handling ESDS devices shall be audited a minimum of once each quarter for compliance
with all terms of this specification. Ground continuity and the presence of uncontrolled static voltages
(any voltage exceeding ± 100 V) are considered critical and shall be checked more frequently as specified
below.
Ground Continuity (minimum of once a week): Ground connections (grounding wrist strap, ground wires
on cords. etc.) shall be checked for electrical continuity. The presence of a 1 MO ± 10% resistor in
the ground connections between both the operator wrist straps to the work surface and the work surface
to ground connector must be verified.
3-7
8.2.3
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8.3
Grounded Conditions (minimum of once a week): A visual inspection shall be made to determine full
compliance with this specification at static-free work stations during handling of ESDS items, including
operator being grounded as required. ESDS items not being handled in unprotected or unauthorized areas,
and no static-generating materials (except as allowed by 3.1) at the static-free work station.
8.2 A
Sleeve Protectors (minimum of once a week): A visual check shall be made to determine that each operator
wearing loose-fitting or long-sleeved clothing either has sleeves properly rolled or covered with sleeve
protectors properly grounded to the bare skin at the wrist. Sleeve protectors are not required if static
dissipative or conductive smocks are used.
Static Voltage Levels (minimum of once a week): In addition to the visual inspections, an inspection
8.2.5
using an electrostatic voltmeter shall be made to check for uncontrolled electrostatic voltages (any voltage
exceeding ± 100 V) at or near electrostatic-controlled work stations. If static dissipative or conductive
smocks are used, they shall also be checked to the same level.
8.2.6
Conductive Floor Tiles (minimum of once a month): Conductive floors must have a resistance of not
less than 100 kr! from any point on the tile to earth ground. Also, resistance from any point-to-point
on the tile floor 3 feet apart shall be not less than 100 kr!. The test methods to be used are ASTM-F-150-72
and NFPA 99.
8.2.7
Conductive Floor Mats (minimum of once a week): Ground connection through a IMr! ± 10% safety
resistor shall be checked for continuity. Mat must be clean and free of tears or holes.
8.2.8
Ionizer operation (minimum of once a month): Air ionizers are to be checked for balanced ionization
in accordance with manufacturer's recommendations.
8.2.9
If a noncompliant condition is found, no additional parts may be processed through that area until the
noncompliant condition is corrected.
Records: Written records must be kept of all audits (paragraph 8.2) for at least I year.
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TRAINING
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9.2
It is the responsibility of the ESD coordinator to make sure that all personnel handling ESDS devices receive
ESD training initially and every 12 months thereatier to maintain proficiency. Training should include static
fundamentals, a review of applicable parts of this specification, and actual applications in the work area .
Training records shall be maintained for each individual. The records shall show dates of training and the topics
covered.
Quality and Reliability Assurance
Texas Instruments has improved the quality and reliability of integrated circuits
through routine updating of existing specifications and programs as well as
advancements in materials, processes, test equipment, and test methods. Since the
early sixties, these programs have provided cumulative improvements to increase
average outgoing quality (AOQ) and reliability by more than an order of magnitude.
Stringent performance and manufacturing standards are defined prior to product
design to assure leadership in the industry. In addition, the following product/process
qualifications and evaluations are performed to assure that these standards are met
on every device released to the market:
• Verification of manufacturability through testing of bar compatibility with piece
parts and automated assembly techniques and equipment
• Proof of process repeatability through definition of minimum acceptable
assembly and test yields
• Testing to data sheet limits through test program certification and guard bands
between probe, final test, and QRA final acceptance,
• Assurance of quality performance through a comprehensive statistical process
control program coupled with tight product acceptance standards
• Assessment of device reliability performance through an extensive reliability
test and qualification program.
Quality is
a product's degree of conformance to its specified parameters. It pertains to the
probability of defective units existing in a given lot when received by the user.
Although zero defects is a goal, the probability of some level of defective units
still exists in any lot of mass produced items. The number of defective units
received by the user is a function of the average outgoing quality (AOQ) achieved
by the supplier.
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Reliability is
a measurement of how well an initially good product will perform over time to
its specified characteristics. Semiconductor failures occur primarily during the
early-life phase of operation. A continually diminishing failure rate can be expected
until the wear-out phases is eventually reached. System reliability is improved
if these potential early-life failures are removed.
0
0
0
The following process flows for plastic and ceramic packages show the extensive
efforts used to maintain high quality and reliability standards for Telecommunication
products from Texas Instruments. These flows apply to TCM prefix devices only.
3-9
TELECOMMUNICATION PRODUCTS PROCESS FlOWt
PLASTIC PACKAGE
SILICON WAFERS
MULTIPROBE: CONTINUITY,
FUNCTIONALITY, DC PARAMETERS
LEAD FRAME
DIE SORT VISUAL
MOUNT
CURE
MOLD
COMPOUND
BOND
PREMOLD VISUAL
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VISUAL/MECHANICAL INSPECTION
PRODUCT ENHANCEMENT PROGRAM
PEP 3 TEST FLOW
25°C GUARDBANDED TEST:
CONTINUITY, FUNCTIONAL, PARAMETRIC
STANDARD COMMERCIAL PRODUCT
TEST FLOW
SELECTED HIGH-TEMPERATURE TEST:
CONTINUITY, FUNCTIONAL
BURN-IN 125°C/16B HOURS (OR EQUIVALENT),
0.96 eV ACTIVATION ENERGY
ELECTRICAL LOT
ACCEPTANCE: 25°C
25°C GUAROBANDED TEST:
CONTINUITY, FUNCTIONAL, PARAMETRIC
VISUAL/MECHANICAL
LOT ACCEPTANCE
HIGH TEMPERATURE TEST:
CONTINUITY, FUNCTIONAL
ELECTRICAL LOT
ACCEPTANCE: 25°C/HI TEMP
VISUAL/MECHANICAL
LOT ACCEPTANCE
___
~
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t Applies to TCM prefix devices only.
3-10
LEGEND
'V -MATERIAL INPUT
o
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-MANUFACTURING STEP
0-100% INSPECTION OR TEST
-QUALITY CONTROL MONITOR OR TEST
TELECOMMUNICATION PRODUCTS PROCESS FLOWt
CERAMIC PACKAGE
SILICON WAFERS
LEAD FRAME,
CERAMIC BASE
MULTIPROBE: CONTINUITY
FUNCTIONALITY, DC PARAMETERS
DIE SORT VISUAL
CERAMIC CAP
MOUNT/BOND
PRESEAL VISUAL
SEAL
QUALITY MONITOR
PRODUCT ENHANCEMENT PROGRAM
PEP 4 TEST FLOW
VISUAL/MECHANICAL INSPECTION
STANDARD COMMERCIAL PRODUCT
TEST FLOW
FINE/GROSS LEAK TEST
25°C GUARDBANDED TEST:
CONTINUITY, FUNCTIONAL, PARAMETRIC
25°C GUARDBANOED TEST:
CONTINUITY, FUNCTIONAL, PARAMETRIC
SELECTED HIGH-TEMPERATURE TEST:
CONTINUITY, FUNCTIONAL
BURN-IN, 125°C/16B HOURS (OR EQUIVALENT},
0.96 eV ACTIVATION ENERGY
SYMBOLIZE
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ELECTRICAL LOT
ACCEPTANCE: 25°C
HIGH TEMPERATURE TEST:
CONTINUITY, FUNCTIONAL
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LOT ACCEPTANCE
25°C GUARDBANDED TEST:
CONTINUITY, FUNCTIONAL, PARAMETRIC
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VISUAL/MECHANICAL
LOT ACCEPTANCE
SYMBOLIZE
FINE/GROSS LEAK
LOT ACCEPTANCE
_ _ _..- SHIP
ELECTRICAL LOT
ACCEPTANCE: 25°C/HI TEMP
VISUAL/MECHANICAL
LOT ACCEPTANCE
LEGEND
~
-MATERIAL INPUT
o -MANUFACTURING STEP
0-100% INSPECTION OR TEST
SHIP
o
-QUALITY CONTROL MONITOR OR TEST
t Applies to TCM prefix devices only.
3-11
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3-12
Application Reports
4-1
Contents
Page
FSK Modems ..............................•.............
TCM2203 Line Interface Circuits and
TCM2222 HDB3/AMI Encoder/Decoder ........................•
TISP Series Transient Suppressors ............................ .
Designing with the TCM1500 Be" Tone Ringer/Detector Family ...... .
Subscriber Line Control Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
•
4-2
4-3
4-21
4-37
4-73
4-101
FSK Modems
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TEXAS
INSTRUMENlS
4-3
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes in the
devices or the device specifications identified in this publication
without notice. TI advises its customers to obtain the latest version
of device specifications to verify, before placing orders, that the
information being relied upon by the customer is current.
TI warrants performance of its semiconductor products to current
specifications in accordance with Tl's standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems
such testing necessary to support this warranty. Unless mandated
by government requirements, specific testing of all parameters of each
device is not necessarily performed.
»
In the absence of written agreement to the contrary, TI assumes no
liability for TI applications assistance, customer's product design, or
infringement of patents or copyrights of third parties by or arising from
use of semiconductor devices described herein. Nor does TI warrant
or represent that any license, either express or implied, is granted
under any patent right, copyright, or other intellectual property right
of TI covering or relating to any combination, machine, or process in
which such semiconductor devices might be or are used.
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Copyright © 1986, Texas Instruments Incorporated
4-4
Contents
Page
Basic Principles of Modem Operation
4-7
Introduction to the TCM3105 .. . .. ,'
4-8
Modes of Operation of the TCM31 05 ... ,
4-9
Architectural Description of the TCM31 05
4-10
Transmitter .............. ,
4-12
Receiver . . . . . . ..... , . . , . . . . .
4-12
Carrier Detect ............... .
4-13
Timing and Control ... , , , .. .
4-13
Description of the Line Interface . ,. ".
4-13
FCC Registration . " "'"
Two-to-Four Wire Converter OperatIOn ........ , ..................... .
4-13
4-14
Description of the Carrier Detect Adjustment, , , ... " " ....'
4-16
Description of the Receive Bias Adjustment .. "
4-17
II
I/)
Output Jitter Measurement , , .... , " ,. .,
4-19
...0
Conclusion ................ " ........ " .. " . . . . . ... " " .. " ,
4-20
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4·5
List of Illustrations
Figure
1
2
3
4
5
6
7
8
9
10
•
Page
Typical Modem System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .
TCM3105 Pinout ...........................................
Bell 202 and CCITT V.23 Channel Assignments .................
TCM3105 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Simplified Two-to-Four Wire Converter ........................
CDL Bias Level vs Carrier Detect Threshold ................ " . .
RXB Bias Level vs RXD Bias Distortion. . . . . . . . . . . . . . . . . . . . . . . .
Loopback Circuit Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Jitter Timing Diagram .......................................
4-7
4-9
4-9
4-11
4-15
4-16
4-17
4-18
4-18
4-19
List of Tables
Table
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1
2
3
Pinout Description ..........................................
TCM3105 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.4336 MHz Crystal Manufacturers. . . . . . . . .. . . . . .. . . . . . . . . . . . .
4-8
4-10
4-13
Basic Principles of Modem Operation
A modem is a device that enables two digital electronic systems to communicate over
the telephone network. To accomplish this, the digital signals must be converted to analog
signals. The short pulses used by digital equipment contain high frequency components
that are not supported by the limited bandwidth of telephone networks (300 Hz - 3400 Hz).
There are two major schemes of modulation used in modems for telephone networks.
These are Frequency Shift Keying (FSK) and Phase Shift Keying (PSK). In FSK, serial
data is modulated so that a "mark" is represented by a sine wave of one frequency, and
a "space" is represented by a different frequency. In PSK, transitions in the digital bit stream
are represented as shifts in phase angle of a single carrier frequency. The FSK concept
is used by the TCM3105. The telephone network is a single-twisted pair of wires, usually
24 or 26 gauge. Two separate paths of communication are required by digital equipment
systems in order to communicate with each other. Each system must have transmit and
receive capability. This interface is supplied by the modem. Full duplex operation is the
simultaneous transmission and reception on a single pair of wires. A two-to-four-wire
converter, or hybrid as it is called in the telecommunications industry, is required (see
Figure 1). This device removes the transmitted data from the receive path so that transmitted
data does not interfere with valid received data.
II
II)
TRANSMIT
DIGITAL
c.
CD
a::
c
TRANSMIT
ANALOG
I
I---
MODULATOR
TWO-TO-FOUR
WIRE
CONVERTER
MODEM
RECEIVE
DIGITAL
't
o
: DEMODULATOR
RECEIVE
ANALOG
-
TIP
PHONE
LINE
INTERFACE
AND
ISOLATION
o
"+I
tV
RING
"~
Q.
PHONE
LINE
c.
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A
Y
Figure 1. Typical Modem System Configuration
The two-to-four-wire converter requires matching the ranges of telephone network
impedances. The impedance of the telephone network varies from line to line due to
manufacturing and installation tolerances of the communications hardware. It is difficult
to obtain good cancellation in a mass-produced piece of equipment.
Four separate frequencies, two transmit and two receive, are used to properly balance
the two-to-four-wire converter. This is to ensure that transmitted and received data do not
interfere with each other.
4-7
The TCM3105
The TCM3105 provides a majority of the functions required of a medium speed FSK
modem in a single 16-pin DIP. The device is manufuctured using silicon-gate complementary
MOS technology. The TCM3105 features single 5-V supply operation and typical power
consumption of approximately 40 mW. This makes the device ideally suited fur use in battery
operated equipment applications, as well as in standard applications. The TCM3105 device
pinout is shown in Figure 2. Refer to pin description listed in Thble 1 fur the function and
significance of each pin.
The TCM3105 is characterized fur operation from O"C to 7O"C (JL suffix) as well
as over the extended free-air temperature range of -4O"C to +85"C (IE suffix).
Table 1. Pinout Description
PIN
NAME
NO.
•
DESCRIPTION
COL
10
I
Carrier Detect Level-Sets the threshold level for the carrier detect
decision. Refer to Description of the Carrier Detect Adjustment
paragraph.
COT
3
0
Carrier Detect - A high logic level output indicates the presence of
a carrier at the RXA pin.
CLK
2
0
Clock - Continuous output clock signal at 16 times the highest
selected transmit or receive baud rate.
OSC1
OSC2
Oscillator 1 and 2 - Input connections for external 4.4336 MHz crystal.
See Table 2 for list of crystal manufacturers. If an external clock input
is provided, then the OSC1 pin is left open and the clock is connected
to the OSC2 pin.
15
16
RXA
4
I
Receive Analog - This input is referenced to an internal voltage and
must be ac coupled.
RXB
7
I
Receive Bias Adjust - This input sets the threshold level of the slicer
that allows the bias distortion on the RXD pin to be minimized. Refer
to Description of the Receive Bias Adjustment paragraph.
RXD
8
0
Receive Digital Output - Outputs the demodulated receive data in
positive logic, i.e., a mark is indicated by a high level and a space is
indicated by a low level. The RXD output pin will remain high if there
is no analog input on the RXA pin.
TRS
5
I
Transmit/Receive Standard Select Input - This pin along with TXR1
and TXR2 select the standard and mode to be used. See Table 1.
TXD
14
I
Transmit Digital - Digital input to the modulator in positive logic, i.e.,
a mark is indicated by a high level and a space is indicated by a low
level. The data can be accepted at any rate from zero up to the selected
baud rate and may be totally asynchronous.
TXR1
TXR2
13
12
I
I
Transmit Rate 1 and 2 - These signals along with TRS set the standard
and mode to be used. See Table 1.
VDD
4-8
I/O
1
Positive supply voltage -
5 volts nominal.
J DUAL-IN-LiNE PACKAGE
(TOP VIEW)
OSC2
OSC1
TXD
TXR1
TXR2
TXA
CDl
VSS
VDD
ClK
CDT
RXA
TRS
NC
RXB
RXD
NC-No internal connection
Figure 2. TCM310S Pinout
II
FREQUENCY -Hz
U)
(a) Bell 202 Channel Assignments
t=
o
'200 BAUD
c.
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600 BAUD
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FREQUENCY -Hz
(b) CCITT V.23 Channel Assignments
Figure 3. BeD 202 & CCITT V.23 Channel Assignments
Modes of Operation of the TCM310S
The TCM3105 is an FSK type modem that is designed to implement the Bell 202
and CCITT V.23 Standards (see Figure 3), which defme mark and space frequencies, and
the maximum data rate that can be transmitted for a given mark/space pair.
4-9
The TCM3105 can be placed into a given mode of operation by applying the proper
signals to the TRS (Transmit/Receive Status) and the TXR1 and TXR2 (Transmit Rates
1 and 2) input pins. The various modes of operation for the modems are summarized in
Table 2. The CLK signal pin operates at a clock frequency of 16 times that of the selected
receive or transmit bit rate, whichever is higher.
Table 2. TCM310S Modes of Operation
Standard
CCITT
V.23
II
BEll
202
TRS
TXR1
TXR2
Transmit
Bit Rate
(Bit/s)
Receive
Bit Rate
(Bit/s)
Transmit
Freq
(Hz)
Receive
Freq
(Hz)
Clock
(kHz)
0
0
0
1200
1200
M 1300
S 2100
M 1300
S 2100
19.11
1
0
0
1200
75
M 1300
S 2100
M 390
S 450
19.11
0
0
1
600
75
M 1300
S 1700
M 390
S 450
9.56
1
0
1
600
600
M 1300
S 1700
M 1300
S 1700
9.56
0
1
0
75
1200
M 390
S 450
M 1300
S 2100
19.11
1
1
0
75
600
M 390
S 450
M 1300
S 1700
9.56
0
1
1
75
75
0
0
1200
1200
1200
2200
M 390
S 450
M 1200
S 2200
1.19
ClK
M
S
M
S
ClK/8
0
1
1200
150
M 1200
S 2200
M 387
S 487
19.11
ClK/8
0
1
1200
5
M 1200
S 2200
M 387
S
0
19.11
ClK
1
0
150
1200
M 387
S 487
M 1200
S 2200
19.11
ClK
1
1
150
150
M 387
S 487
2.39
*
1
*
5
1200
M 387
S 487
M 387
0
S
M 1200
S 2200
19.11
1
1
1
Transmit
Disabled
M 1200
S 2200
19.11
Transmit
Disabled
1200
390
450
19.11
*In this mode, the modulation is controlled by the TRS and TXR2 inputs, TXD is set to 1.
If TRS
If TRS
=
=
ClK & TXR2
1 & TXR2
=
=
0, then TXA
1, then TXA
=
=
387 Hz
0 Hz
Architectural Description of the TCM3105
The modem has four main functional blocks: a transmitter, a receiver, a carrier
detector, and timing and control (see Figure 4).
4-10
TRANSMIT
DIGITAL
INPUT
RECEIVE
BIAS
ADJUST
TXD
~----~
(14)
FSK
MODULATOR
DIGITAL
TO ANALOG
CONVERTER
H
XMT
FILTER
H
RXB (7)
RECEIVE
ANALOG
INPUT
II
LOW·PASS
FILTER
RECEIVE
1COMPARATOR _I
AUTOMATIC
GAIN
CONTROL
(15)
OSCILLATOR JoSC1
(16)
CONNECTIONS l?SC2
CARRIER
DETECTOR
CARRIER
DETECT
DELAY
TIMING
AND
CONTROL
(13)
SELECT 'l.:!"XR2
II COMPARATOR ~ RXD
TRANSMIT
ANALOG
OUTPUT
RECEIVE
DIGITAL
OUTPUT
(3)
COT
CARRIER·
DETECT
OUTPUT
CLK
CLOCK
J OSCILLATOR
4.4336 MHz } -
BIT RATE fiXR1
TRANSMIT! TRS
RECEIVE
STANDARD SELECT
~TXA
OFFSET
COMPENSATION
I
CARRIER·DETECT
(10)
LEVEL
COL
ADJUST
FSK
LOW·PASS
FILTER
(12)
(5)
Figure 4. TCM310S Functional Block Diagram
f"
Application Reports
II
(2)
Transmitter
The transmitter consists of a phase-coherent FSK modulator with a transmit fIlter
and transmit amplifier. The modulator is a programmable frequency synthesizer that obtains
the required output frequencies for the modem by dividing the 4.4336 MHz master clock.
The division ratio is set by the states of the TXD (Transmit Digital), TXRl, TXR2 and
TRS inputs (see Table 2). The transmit fIlter consists of a switched-capacitor filter stage
and a continuous-time fIlter stage. The switched-capacitor fIlter samples at a rate dependent
upon the transmit frequency selected. This arrangement offers the optimum rejection of
out-of-band terms, regardless of the transmit frequency. The continuous-time filter is a
second-order Bessel function filter that rejects the clock feedtbrough from the switched
capacitor filter. The analog output (TXA) pin of the modem is dc biased at approximately
50% of the supply voltage and should be coupled to the two-to-four-wire converter. The
overall transmit gain is adjustable within the twooto-four-wire converter.
Receiver
The receiver section consists of an antialiasing prefIlter, receive amplifier, receive
filter, compromise line equalizer, limiter, demodulator. post demodulator fIlter, and slicer.
The antialiasing prefIlter is a continuous-time low-pass filter that prevents aliasing
of high frequency components and sets the band limits of the input signal.
•
The receive amplifier is part of the receive fIlter. The receive fIlter is an elliptic
switched-capacitor design, composed of three sections. The first section is a fIlter that has
a high discrimination against the transmit frequencies. The second section is a bandpass
fIlter that includes an automatic gain control function to regulate the amplitude of the signal
to the slicer. The last stage is a low-pass fIlter that attenuates high frequency interference.
Overall, the receive filter attenuates broadband interference and removes out-of-band energy
that would interfere with demodulation.
The compromise line equalizer is a switched-capacitor equalizer that compensates
for the group delay distortion of the receive filter and telephone network. The output of
the equalizer is converted to a square wave by a hard limiter.
The demodulator is a conventional monostable multi vibrator configured to trigger
on the rising and falling edges of the limiter output. The output of the demodulator is a
train of fixed-length pulses at a frequency equal to twice that of the received analog signal.
Thus, the dc component of this signal is proportional to the frequency of the received signal.
The post demodulator filter is a switched-capacitor low-pass filter that extracts the
dc component from the output of the demodulator.
The fmal stage of the receiver is a slicer that has an externally adjusted reference
voltage applied to the RXB (Receive Bias) pin. The RXB reference voltage is necessary
to compensate for offsets introduced in the switched-capacitor circuitry. The output of the.
slicer is the RXD (Receive Digital) pin. The RXB reference voltage need not be readjusted
when changing modes of operation, as the modem compensates internally
4-12
Carrier Detector
The carrier detector section consists of an in-band energy detector and a digital delay.
The energy detector measures the total energy level at the output of the receive filter and
compares this level to a bias level that is set at the CDL (Carrier Detect Level) output
pin. The CDT (Carrier Detect) pin is a logic high in the presence of a carrier.
A degree of protection against false output, due to brief signa1 dropouts, is present.
The energy detector is buffered by a short time delay qualifier before the carrier detect
signa1 is sent through to the CDT pin. In addition, the detector exhibits approximately
4 dB of hysteresis to prevent output oscillation.
Timing and Control
The timing is controlled by an externa1 4.4336 MHz crystal oscillator. Refer to
Thble 3 for a list of suggested crystal manufacturers. From this master frequency, the timing
section generates a11 the clock control signa1s and supplies the CLK output signal.
Table 3. 4.4336 MHz Crystal Manufacturers
Manufacturer
CL
Tolerance
Midland-Ross
PH. 414-763-3591
20 pF
±0.005%
@ 25°C
Stock Number C 1721 N
Part Number MPC 18
Requires a 27 pF capacitor from each leg to ground
CTS Knights
PH. 815-786-8411
20 pF
±0.005%
Part Number R 133 5-58A443361 9
Requires a 27 pF capacitor from each leg to ground
30 pF
±0.005%
Part Number L 01-0096-004433618
Requires a 50 pF capacitor from each leg to ground
15 pF
±0.005%
No Part Number Available
Requires a 1 5 pF capacitor from each leg to ground
Erie Frequency
Control
PH. 717-249-2232
Seiko Instruments
PH. 213-530-8777
Comments
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Description of the Interface Line
.2
C.
c.
FCC REGISTRATION
(J1
Application Reports
II
A
100 kll
TRANSMIT
---vvv---.....-t
ZT-600 Il
100 kll
[:
ZT'
5V
47kn
A
47kn
RECEIVE
100 kll
100 kll
U1 = %LM124
•
Figure 6. Simplified Two-to-Four Wire CODverter
Description of the Carrier Detect Adjustment
The threshold of the carrier detect circuitry in a modem can be adjusted by an external
voltage bias at the COL pin. The minimum detected level is set between the limits of -55
dBm to -35 dBm. A plot of the threshold versus the bias at the COL pin is shown in
Figure 7. The procedure for adjusting COL is as follows:
1. Apply 4 V to the COL pin.
2. Place the correct inputs to pins TXRl, TXR2, and TRS so that the TCM3105
is in the desired mode. Refer to Thble 2.
3. Apply an ac-coupled, sinusoidal signal to the RXA pin at a frequency between
the mark and space frequencies for the mode selected. 'The amplitude of this
signal is set to the lowest signal level that is desired for the modem to detect.
A nominal signal level is -44 dBm.
4. The CDI' pin should be low.
5. Decrease the voltage at the COL pin until the voltage at the CDI' pin becomes
high.
Note: The TCM3105 has a carrier detect delay of 20 ms to 80 ms depending on
the receive rate selected. A wait for this delay to time out is required before
the CDI' pin is monitored.
6. The carrier detect level adjustment is now set.
4-16
5
4
>I
13
....~
til
(II
i:i5 3
....o
VDD = 5 V
~
"
~~
~
Col
~
2
-35
-40
-45
-50
-55
Carrier Detect Threshold -dBm
Figure 7. CDL Bias Level vs Carrier Detect Threshold
Description of the Receive Bias Adjustment
II
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CI)
An adjustment of the bias voltage at the RXB pin is required to minimize the bias
distortion of the demodulated receive signal at the RXD pin. The bias voltage applied to
the RXB pin is used by the slicer to set an internal threshold. A plot of the bias distortion
of the RXD signal versus the bias level at the RXB pin is shown in Figure 8. The receive
bias can be adjusted by one of two methods.
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Method 1
.~
1. Apply the desired signals to pins TXRl, TXR2, and TRS to set the modem in the 1200
baud transmit/1200 baud receive half-duplex mode (for either CCITT V.23 or Bell 202
Standards) .
«
c.
c.
2. Set the modem in the loopback mode (as shown in Figure 9). The attenuator ensures
that the analog signal from the TXA pin to the RXB pin is less than 0.78 V peak to peak.
3. Apply a ground to VDD and a 600 Hz square wave to the TXD pin.
4. Monitor the RXD pin with an oscilloscope and adjust the voltage at the RXB pin until
the output signal at the RXD pin has a 50 % duty cycle.
4-17
3.4
I
VDD - 5 V
3.2
/
3.0
~
] 2.8
i
2.6
/
~
2.4
2.2
/
v
2.0
-20
/
,/
o
-10
V
/
+10
+20
RXD Bias Distortion - %
II
Figure 8. RXB Bias Level vs RXD Bias Distortion
-:;J;30 PF
3O PF-:;J;
TCM3106 1151
OSC1
0.11'F
TXA 1111
5V
100 kll
1161
OSC2
171
RXB
5V
VDD 111
5V
100 kll
1101 COL
SINGLE LEVEL
LESS THAN
0.7B Vpp
0.11'F
TRS
COT
CARRIER DETECT
CLOCK
121
CLK
RXD 1"18....;1.......---1
VSS
191
Figure 9. Loopback Circuit Diagram
4-18
Method 2
1. Apply the desired signals to pins TXR1, TXR2, and TRS to set the TCM3105 in any
proper mode.
2. Apply a signal with an amplitude of less than 0.78 V peak to peak to the RXA pin.
The frequency of the input signal should be exactly in the middle of the mark and space
frequencies for the mode selected.
For example, if the Bell 202 1200 baud receive mode is selected, the signal should then
have a frequency of 1700 Hz which is the center of the mark frequency of 1200 Hz and
the space frequency of 2200 Hz.
3. Apply 3.5 V to the RXB pin, and the RXD pin should exhibit a mark (or high).
Reduce the voltage at the RXB pin until RXD pin exhibits a low (space), then increase
the voltage at the RXB pin until the RXD pin exhibits a high (mark). The bias at the
RDX pin is now set.
Either method will correctly set the bias required for the RXB pin to minimize the bias
distortion. Once the adjustment has been set for one particular mode of operation, no
further adjustment should be necessary for the remaining modes. The bias distortion
should not vary with the baud rate.
Output Jitter Measurement
To measure the demodulated receive output data jitter at the RXD pin, it is necessary
to set the modem into a loopback mode (see Figure 9). Apply the proper signals to pins
TRS, TXR1, and TXR2 to place the modem in the 1200 baud transmit/1200 baud receive
half duplex mode (for either CCITT V.23 or Bell 202). Apply a ground to VDD and a
600 Hz square wave to the TXD pin. With an oscilloscope (set for leading edge triggered)
look at the signal at the RXD pin. It should appear as illustrated in Figure 10. The jitter
of the output is the difference between T max andT min.
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Notes: A. Section VII must be accomplished before the jitter measurement.
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B. 4.4336 MHz is from a 4.43361875 MHz crystal (European color burst crystal).
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U
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I
LINE
Figure 5. Transmit Timing Diagram
.....
fClK/2
log F
o
Frequency
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Figure 7. Line Build-Out Transfer Function
J
INCREASING
LINE
lENGTH
I
t"
J
...
Frequency
log (fl
Figure 6. Typical Transmission
Line Transfer Characteristics
The TCM2203 ALBO is based on the assumption that
the transmitted signal has a constant amplitude at the
transmitter and that the amplitude of the signal at the receiver
can be used to predict the transmission line transfer function.
CI)
t:
The information derived from the signal amplitude can then
be used to control the shape of the complimentary transfer
function used to restore the signal.
The TCM2203 ALBO system ( Figure 8) operates as
follows:
I. The received signal after passing through the
filter network is input to an amplifier and phase
splitter (pin 14). The phase splitter outputs are
peak detected and stored on two capacitors
(pins 15 & 16).
2. The stored peak values are averaged and the
resulting signal is fed to a transconductance
amplifier.
3. The output current from the transconductance
amplifier is fed to two diode strings. The diode
strings serve as variable dynamic resistances.
The diode string outputs (ALBOI & ALB02) are
used to control the transfer function ofthe filter
circuits.
4·27
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suodaH UO!l.e:>!ldd~
A
N
00
+5 V
+5 V
MUTE
11S1
1131
TCM2203
5V
-=
.ru-LI1.
>
CLOCK
COMPARATOR
RX
ClK
1221
lOUT
"l.r
+BP •
11231
~
TANK
RXO ...
OUT
PHASE
u
-=
"l.r
lG;]
-BP
RXO-
I~OUT
RX
1161
~
4BO mV p.p
Figure 8. Receiver Block Diagram
-
The TCM2203 receiver section provides two amplifiers
(6 dB fixed gain buffer and 48 dB adjustable gain
preamplifier) in addition to the two ALBO pins which can
be used to construct the signal restoration circuit.
Data Detection
The data detection circuit (see Figure 8) operates as
follows:
I. The signals from the phase splitter amplifier are
fed to two comparators.
2. The signals are compared to one-half of the
stored peak values. The comparator outputs are
then latched in two flip-flops using the extracted
clock signal.
3. The two flip-flop complements, (RXD + OUT
and RXD - OUT), are brought out on pins 23
and 2l.
The two data signals RXD + OUT and RXD - OUT
are sent with the recovered clock RX CLOCK OUT to a
transcoder for decoding and error detection.
Clock Recovery
The TCM2203 clock recovery circuit is a low-Q circuit
using a tuned LC network. The low Q circuit is used to
minimize false clocks due to noise. Clock recovery is
accomplished as follows:
I. The data signals from the phase splitter are
combined to produce a full wave rectified signal.
The rectified signal is compared to the clock
threshold which is two-thirds the average ofthe
stored peak signal values.
2. That portion of the pulse which exceeds the clock
threshold value is used to control a drive
transistor. The open collector of the drive
transistor (pin I) is connected to the primary of
the clock recovery transformer.
3. The output transistor injects current pulses into
the tuned primary circuit of the transformer. The
tuned primary extracts the clock term from the
current pulses.
4. The extracted clock signal is fed from the
transformer secondary to pins 26 & 28 of the
TCM2203. The sinewave is converted to a
square wave with a 60 dB gain comparator. A
phase-shifting capacitor connected to
pins 2 and 3 optimizes the clock phase relative
to the data.
5. The recovered clock is sent to the data detection
circuit flip-flops, then buffered, and output on
pin 22.
The eye diagram in Figure 9 indicates the signal
thresholds for data and clock decisions.
SYSTEM DESIGN
The TCM2203 is capable of working with different data
encoding formats and over a range of frequencies, however
circuit design and component selection must be based on
specific system parameters. The information in the following
sections is based on the T I Demonstration Circuit. Figure IO
is a block diagram showing the circuit consisting of two
stages of ALBO plus a fixed equalizer. Figure II is the circuit
schematic of the demonstration circuit. All of the circuit
references and reference designators in the .following
descriptions are from the schematic in Figure II. Table I,
T I Demo Parts list follows the schematic in Figure II.
Transmitter Circuit
The TCM2203 output drive transistors can sink 20 rnA
(loL> with a saturation voltage of I V (VOL). RI9 and CI4
provide a filter and current limit for the output drive. The
output transformer T2 is an AEI Magnetics Part
No. 327-0044. 4 This transformer has a 2.71: I turns ratio.
The transformer must have a secondary inductance of more
than 6 mH and a Q of less than 6, both measured at IMHz
in order to meet the output pulse requirements shown in
Figure 12. Pulse timing is a function of the transformer
design, reflected transmission line impedance, output driver
current and system clock. The pulse amplitude is a function
of the transformer turns ratio, output transistor saturation
voltage (VoL>, transmission line impedance, and power
supply voltage.
Receiver Circuit
The receiver design consists of the input transformer
and all of the filter components associated with signal
restoration. The transfer function of the restoration circuit
is the combination of two ALBO circuits, two amplifiers and
the equalizer. Figure 13 shows the transfer functions of the
Preamp, the equalizer, and a single ALBO stage at three
diffetent ALBO resistances (25 ohms, 430 ohms, and
10000 ohms).
The TCM2203 is a single supply voltage part and all
of the analog signal inputs are internally biased. Capacitors
must be used to couple the signals between the TCM2203
and the external filter components.
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1:1
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-,
(.....,
0.1
-;
TCM2203
Ul
VcC
R19
TRANSMIT
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II
LINE OUT X 1251 ___--...:_,.
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121. PHASE ADJ 1
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1
C8
+10.F
U3
1/674HC04
L..:=-=-==--il~.
0.11(
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100 pF
62 k
~
L3
150.H
R15
510
+5V~>::!oC231c2~CC
5
.l11l.! PREAMP IN
~ 11211 PREAMP OUT
__
'"
J78 Y I O O 1 1 . 0
+ V---0~:;:--~""""""
RET ---.....;
EQUALIZER
GND
~
1151
(161
.. I I
-'~ Jirl___
t-:c:--, ';,';
-
-;
R30
4.7 k
SLICER IN _ 1281
_
121
'1161
1261
SLICER IN + M
SLICER REF (27)
~.II~AMPLIN
R16
J7A
TANK DIP .111
~CAL802
0""" ~.~
NOTES: UNLESS OTHERWISE SPEC
1. All capacitors are .F
2. All resistors are ohms
Figure 11. TI Circuit Schematic
"r"~~
II " ~"'~
U
U_
M'"
'--M--200 ns MAX
100% -r----+-if-+_----_
90%
ojl~--~~~----------~~--------==::3:~-~-~-~-~-~-~-~-~-:7_-~-~-~'~h
-------------T-~
2.7 VZ, TISP2XXX and TISP3XXX Families . . . . . . . . . . .
/2 x V GEN > VZ, TISP1XXX Family . . . . . . . . . . . . . . . . . . . . . . .
ANALYSIS OF FUSE PROTECTED SYSTEMS . . . . . . . . . . . . . . . . .
ANALYSIS OF PTC PROTECTED SYSTEMS . . . . . . . . . . . . . . . . . .
4-64
4-64
4-65
4-66
4-66
4-66
4-68
SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-70
REFERENCES
4-71
List of Illustrations
Figure
III»
"C
'E.
cr
I»
r+
c)"
::s
::tI
~
..
"C
0
r+
(I)
4-40
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Title
Typical Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1\vo Transistor Analogy of the Thyristor . . . . . . . . . . . . . . . . . . . . . .
Circuit Analogy for Avalanche Conditions . . . . . . . . . . . . . . . . . . . . .
Circuit Analog for Breakover Conditions . . . . . . . . . . . . . . . . . . . . . .
Circuit Analog for Holding Current Condition . . . . . . . . . . . . . . . . . .
TISP1XXX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TISP2XXX AC, BC, and AB Characteristic . . . . . . . . . . . . . . . . . . . .
TISP3XXX Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery-Backed Ringing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ground-Backed Ringing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Balanced Ringing Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SLIC Only Protection Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TISP2290 Normalized Holding Current Versus Junction Temperature ...
AC Line Contact Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Protection Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typical Fusing Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PTC Resistance Versus Temperature . . . . . . . . . . . . . . . . . . . . . . . .
PTC AC Resistance Locus Versus Temperature . . . . . . . . . '.' ......
Voltage Generator Load Line and Waveforms . . . . . . . . . . . . . . . . . .
TISP2XXX and TISP3XXX AC Line Contact Conditions . . . . . . . . . .
TISP1XXX AC Line Contact Conditions . . . . . . . . . . . . . . . . . . . . .
RMS Current Versus Time for Fuse Protection . . . . . . . . . . . . . . . . .
RMS Current Versus Generator Resistance . . . . . . . . . . . . . . . . . . . .
RMS Current Versus PTC Resistance . . . . . . . . . . . . . . . . . . . . . . .
RMS Current Versus Average Suppressor Power . . . . . . . . . . . . . . . .
Page
4-42
4-43
4-44
4-45
4-46
4-47
4-48
4-49
4-51
4-52
4-53
4-54
4-56
4-58
4-58
4-59
4-60
4-61
4-62
4-65
4-66
4-67
4-68
4.:69
4-70
Introduction
The rapid growth of the semiconductor content in telephone systems has
dramatically altered the kind of protection required against such hazards as lightning
and accidental connection to ac lines. Protection methods developed for the previous
generation of exchange interfaces and subscriber sets are no longer adequate. New
protection devices must offer faster response, well defined voltage levels, reliable
operation, and no interference with normal system operation.
Texas Instruments has developed three families of transient suppressors that
cover the most common subscriber line interface circuit (SUC) configurations. These
bidirectional devices provide shunt protection against transient static voltages between
the wires of an exchange pair or from either wire to ground. In addition, they are
capable of providing protection against damage from induction from, or even accidental
connection to, some kinds of ac sources.
This report describes the important characteristics of the TISPIXXX,
TISP2XXX, and TISP3XXX families of transient suppressors, defines the dc
parameters, and discusses the various system stresses under ac line contact testing.
II
Basic Characteristics
en
t:
o
~
Construction
CD
a:
The successful and reliable operation of any protection system depends to a large
extent on the design and fabrication of the components used. The active part of the
TISP transient suppressor is a silicon chip structured with alternate layers of P and N
type material. The chip is fabricated using Texas Instruments Ion-Implanted Planar
(I2P) process which permits precise control of the electrical characteristics, extremely
stable parameters, and the monolithic integration of two bidirectional suppressors on a
single chip.
c
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er
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(1)
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The high thermal mass of the TO-220 package copper tab strongly contributes to
the device protection perfonnance with short- and medium-duration transients. Longterm transients, such as shorts to outside voltage supplies, can be protected against by
the use of fuses or positive temperature coefficient (PTC) thermistors to terminate or
reduce the fault current.
Under normal operating conditions, the TISP series presents negligible loading on
the telephone line due to its very low leakage planar construction and precise avalanche
voltage.
en
Equivalent Model
Each protector section consists of two opposing thyristors connected in parallel to
give bidirectional operation. It is sufficient to analyze only one thyristor in the
appropriate polarity as the two thyristors are almost symmetrical in structure. Figure 2
shows how the PNPN thyristor structure can be segmented into a PNP transistor, n,
and an NPN transistor, T1, with a common collector-base junction. Triggering occurs
by collector-base junction avalanche breakdown depicted in the equivalent circuit by
zener diode Zl and the normal slope resistance R2. The thyristor's P gate region is
shorted by the cathode metaJ].ization to produce a low-value resistance, the equivalent
shown as resistors R1 and R3 across the NPN transistor's base-emitter junction to give
the thyristor its high holding current.
4-42
I ANODE
IANODE
p
p
N
N
r-
N
~
N
P
p
r-
p
I"-
P
-
N
N
ICATHODE
ICATHO DE
(a) SIMPLIFIED STRUCTURE
(b) STRUCTURE COMPONENTS
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CATHODE--~------------J
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(c) CIRCUIT EQUIVALENT
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Figure 2. Two-Transistor Analog of the Thyristor
C.
Q.
c:r:
Model Analysis
1bis analysis is extremely simplistic and is only intended to provide an overview
of the device's operation to enable designers to estimate how it will interact with system
voltage and current conditions.
Definition of Symbols
VBEl
VBF2
Vz
al
a2
-
Transistor, Tl, base-emitter voltage
Transistor, T2, base-emitter voltage
Zener diode avalanche voltage
Transistor, Tl, alpha current gain
Transistor, T2, alpha current gain
4-43
Voltages Below Vz
As the voltage is increased from zero, the only current flowing will be due to
junction and surface leakage, which will be very small. Data sheet measurements of
leakage are performed at the typical dc voltage level of -50 V.
Avalanche Region
When the applied voltage exceeds Vz + VBE2, the thyristor will start to conduct.
The onset of the avalanche region is defined as the voltage developed across the
suppressor at a current level of 1 mA. At a current level of IX, the terminal voltage, VX,
in Figure 3 will be:
Vx
=
VBE2 + Vz + IX(R2 + R3)(1 - 0:2) + R3IX0:2
giving
Vx = VBE2 + Vz + IX[R3 + R2(1 - 0:2)]
Differentiating this with respect to IX gives the avalanche slope resistance, RA,
which is:
RA = R3 + R2(1 - 0:2)
R2
Z1
R1
R3
Figure 3. Circuit Analogy for Avalanche Condition
Experienced transistor users might have expected the PNP transistor, 1'2, to
avalanche initially at BVBE2 + BVCB02, breaking back to BVCEO as the current
increased. In practice, this effect is negligible, because to block in the negative direction
transistor 1'2 must be implemented with a low gain, a2, which results in the two
breakdown voltages being almost equal.
Breakover
The avalanche characteristic terminates with the regenerative tum-on of
transistors 11 and 1'2. This initiates when the voltage drop across resistors Rl and R3
in FJgure 4 reaches VBEI at a current level of IBO.
4-44
Thus:
giving
I
VBEl
BO - R3 + 0'2 Rl
VBO
T2
--1
I
I
I
. R2
I
)
t
__
I
Z1
R1
_JtN~.-
R3
...
T1
....
I
I
I
____ ...-_----..J
II
~
Figure 4. Circuit Analogy for Breakover Condition
II)
The breakover voltage level, VBO, will be the value of Vx when IX
Substituting and simplifying gives:
=
~
IBO.
VBEl [R3 + R2(l - 0'2)]
VBO = VBE2 + Vz +--=-='::~,------~--=:"='
R3 + 0'2Rl
The above equation predicts the voltage excursion from initial avalanche to
breakover will be:
VBEl[R3 + R2(l - 0'2)]
R3 + 0'2Rl
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When the suppressor triggers "on", its current will greatly increase, ensuring
that regeneration is maintained. Consider a voltage source, V S, and internal resistance,
RS, at breakover.
Vs
=
VBO + IBORS
Neglecting the thyristor "on" voltage drop, the crowbar current, ITM, will be:
ITM
=
Vs
RS
=
VBO
IBO + -RS4-45
This is the initial crowbar current. In cases where Vs is time variant, much
higher current values can be achieved later in the suppression cycle. The 5 A "on"
voltage level is specified as 3 V maximum for TISP series devices.
Regenerative Condition
After breakover has occurred, the transistors will remain in conduction until the
current drops to a critical value called the holding current, IH, whereupon regeneration
stops and the transistor pair delatches. If the system continues to supply current with
sufficient voltage compliance, the voltage will rise until it is limited by the avalanche
characteristic. The base current available to drive transistor T1 in Figure 5 is:
VBE1
0'2I H - R1 + R3
Rt
•
R3
Figure S. Circuit Analogy for Holding Current Condition
Its base current requirement to maintain regeneration is:
IH(1 - 0'2)(1 - 0'1)
0'1
When these two values are equal, regeneration is just maintained. Setting these
two equations equal and simplifying gives:
IH
= (R~!Ei3)
C~1 + ;2 -
1)
Because the alpha current gain of the NPN transistor, Tl, will be close to unity,
the holding current equation may be approximated to:
I
VBE1
H = (R1 + R3)0'2
Negative Voltages
Reverse voltages are blocked by the reverse biased base-emitter junction of PNP
transistor, T2, and the only current flowing will be due to junction and surface leakage.
4-46
The reverse breakdown voltage of the base-emitter junction is designed to be higher
than the breakover voltage so that the opposing thyristor limits the voltage in the
negative polanty.
Definition of DC Parameters
Device Characteristics
The two outer TO-220 package leads, each connected to a line wire, are termed A
and B. The center lead, termed C, is the ground connection. Thus, wire-to-ground
voltages are VAC and VBC, and the wire-to-wire voltage is VAB.
TISPIXXX
Figure 6(a) shows the wire-to-ground characteristics of the TISPIXXX family of
suppressors. For positive voltages, the devices have a forward biased diode
characteristic. The negative characteristic is that of a voltage-triggered thyristor. For this
report, the relevant measurement points on this characteristic are:
10 - The leakage current at the test voltage Vo
Vz - The initial clipping or avalanche voltage measured at 1 rnA.
IBO - The current level (pulsed) at which the device triggers to the "on"
state.
IH - The current at which the device triggers back to the "off''' state.
II
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ct
(a)
AC AND BC CHARACTERISTIC
Figure 6. TISPIXXX Characteristics
4-47
f~~ -1===~!-_~~==-1
I
I
1 mA
I
I
VaoVz
Vz Vao
I
I
I
I
I
I
------<4----1
-------~----,
IH
lao
(b) AD CHARACTERISTIC
Figure 6. TISPIXXX Characteristics
Figure 6(b) shows the wire-to-wire, symmetrical, voltage-triggered thyristor
characteristic of the TISP1XXX family. These devices start to clip wire-to-wire and
negative wire-to-ground voltages at VZ.
•
TISP2XXX
Figure 7 shows the symmetrical, voltage-triggered thyristor characteristic of the
TISP2XXX family of suppressors. At the current levels being considered, there is little
f~ 1~-':~~:::~~~-1
I
I
I
I
Vz vao
Figure 7. TISP2XXX AC, BC, and AB Characteristics
4-48
difference between the wire-to-ground and the wire-to-wire characteristics. Thus, these
devices start to clip both wire-to-ground and wire-to-wire voltages at VZ.
TISP3XXX
Figure 8(a) shows the wire-to-ground, symmetrical, voltage-triggered thyristor
characteristic of the TISP3XXX family of transient suppressors. In this respect, it is the
same as the TISP2XXX family. The difference between the two families occurs in the
II
(a) AC AND BC CHARACTERISTICS
U)
t=
oQ.
_t_I______
______ ~------+ _____ _
I
I
I
I
50V
IDt,:;=-=_~,....-_J
_--...&..--.. . .
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I
1 mA
2 VBO 2 Vz
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ID
50 V
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130 V and VZ(AB) >
200 V. Again, this is an application for the TISP3XXX series of devices.
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SWITCHING
RELAY
TISP3XXX
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INCOMING
LINE
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~RING
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GENERATOR
I
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'--SliC
IC
Figure 11. Balanced Ringing Circuit
4-53
Test Access
In fault finding and preventative maintenance operations, test signals are applied
to the line and SUC. If the applied voltage levels exceed normal telephone operation,
these levels would determine VZ. Extremely high levels of test signal to the line and
correspondingly high Vz requirements could lead to the loss of adequate SLIC
protection. In this situation, the transient suppressor should be connected to the SLIC
side of the test access relay so that Vz can be set by normal system operating levels and
SUC protection maintained.
Minor Transients
•
The pelVasive nature of the telephone network means the possibility of induced
transients is very high. While the energy levels of these may not be substantial, they can
cause the voltage to rise to a level which makes the suppressor clip. Pulse dialing
telephones, which periodically short the line, can, under certain conditions, also cause
suppressor clipping. This situation is aggravated by the increasing use of electronic
ringers, such as the TCM1506, whose antitapping function is achieved electronically
rather than by bell loading. Obviously, the interference level would be compounded if
breakover occurred. Under these conditions, a reasonable compromise is to make
IBO = IH for the minimum values .
SLIe Only Protection
Certain integrated SUC implementations utilize medium-voltage IC technology
and cannot be subjected to ringing voltage levels. This is not a major problem, as it. is
possible to configure the system to switch out the SUC during the ringing operation. In
this case, a transient suppressor on the line would not provide complete SUC
protection. Adequate protection can be achieved by the use of a TISP1XXX transient
suppressor connected directly across the SUC output. This configuration is shown in
Figure 12.
SWITCHING
RELAY
INCOMING
LINE
)
Figure 12. SLIC Only Protection Circuit
4-54
Typically, the supply lines to the IC are 0 V and battery. Sometimes, the battery
voltage may be boosted to comprehend long lines and an additional +5 V supply used
for logic interfacing. The TISP1XXX family of transient suppressors ensures the SLIC
is protected against positive voltages by having a forward biased diode characteristic in
this direction. In the negative direction, the value of Vz will be set by the SLIC output
swing which will be VBATM - VSAT, where VSAT is the saturation voltage of the IC's
driver stage. Using the previous values of voltage and temperature and assuming VSAT
= 2 V gives a 25°C value of Vz wire-to-ground of:
VBATM- VSAT
Vz = --...",,,,...----,,...,,
1 + TMIN - 25
1000
58 - 2
-15 - 25
1+
1000
~58V
In operation, both wires of the line will be negative and the wire-ta-wire voltage
magnitude will be less than the value of Vz calculated above.
Holding Current IH
Large single pulse transients will exercise the suppressor in the following manner.
When the transient's leading edge reaches the line card, it will override the existing
voltages until the suppressor starts to clip. In nondiode cases, once the current in the
suppressor exceeds lBO, the suppressor saturates, absorbing the transient current at
low voltage.
•
en
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o
As the transient current decays, the saturated suppressor will be left carrying
'.;:0
whatever current the system can provide. The worst case condition is for negative
transients when the suppressor could be left with the line dc feed current, Idc (in the
case of a positive transient current, negative dc feed current would actually help to
terminate the crowbar action of the suppressor). It is necessary that the suppressor
recover from this condition so that normal system operation is resumed. This can be
ensured by making Idc < IH over the system operating temperature range. Although
the junction temperature of the suppressor will rise as a result of the transient, it quickly
cools back to the system ambient due to the high thermal capacity of the TO-220 copper
tab.
,~
co
'i5..
Q.
100 rnA at 700C ambient, rather than an
iterated value. If the maximum value of Idc varies substantially with temperature, the
minimum holding current requirements should be quoted at several temperatures. This
should only be necessary in extreme cases as even the crudest semiconductor current
limit is -O.5%/"C and copper coils are -0.4%/"C.
When the suppressor unlatches, there is often sufficient transient energy left to
force the suppressor into its avalanche region until all the transient's energy is
dissipated. Under these conditions, it is desirable that IBO is comparable with IH,
otherwise there is not a stable dc operating locus and high level oscillations can occur
until the current falls below IBO value.
AC Line Contact Conditions
Design Considerations
There can be a great diversity in ac line contact specifications between the various
central office and PABX applications. In this introductory note, only the general
principles will be addressed rather than specific cases. The Texas Instruments
TISP1XXX, TISP2XXX, and TISP3XXX transient suppressor families provide
4-56
excellent peak voltage limitation due to their voltage-triggered crowbar action on the
low frequency test waveform. This action completely protects the following SLIC against
oveIVoltage. The major parameters of this oveIVoltage shunt protector will have been set
by normal exchange operation, SLIC voltage ratings, and lightning withstand
requirements. The ac line contact issues are mainly thermal, in particular, the package
dissipation capability.
In contrast, the series overcurrent protector has most of its major parameters
defined by normal exchange operation and the ac line contact conditions. It is necessary
to understand the interaction of the series and shunt protectors under ac line contact
conditions in order to determine the series protector specification. As the interaction
depends on the respective specifications, the development tends to be iterative.
Generally the loop will be:
1.
2.
3.
4.
Choose some appropriate initial values for the series protector.
Establish the ac voltage source and resistance values that the protection
network and the system can withstand without failure.
Compare these with required test levels.
Repeat the design exercise until the desired level of protection is achieved.
When failure occurs, even though it may be at test levels far beyond the
specification, it should be in a safe manner without creating fumes or flames. Shunt
protectors are expected to fail by shorting, and thereby continue to protect the SLIe. In
the Texas Instuments TO-220 packaged TISPXXXX transient suppressors, soldered
connections are made to the chip, thereby avoiding any possibility of bond wires fusing
and creating an open circuit. Consideration has also been given to the current carrying
capability of suppressor to SLIC PCB tracking to ensure this does not act as a fuse and
open circuit the shunt protection. Certain specifications will concede minor damage
during testing, provided it is easily repairable. Generally, this is to cover the use of series
fuses in the line for protection.
II
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a:
c:
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;
as
Configuration
.2
Q.
Q.
10 s) where the TISP TO-220 package-to-ambient thermal
time constant starts to dominate the maximum suppressor dissipation.
Pre Thermistors
Thermistor based protection systems are intended to recover once the overload is
removed. During the ac line contact condition, the rms current, IOEN, flowing through
a
(I)
t:
o
102
Co
CI)
a:::
s::
o
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co
.~
Q.
Co
«
10-3~----L-----~----~----~
10- 2
I1gure 16. Typical Fusing Characteristic
4-59
the thermistor causes heating. When the PTC temperature rises to a critical "switch"
temperature, its dynamic resistance starts to increase dramatically as shown in Figure 17
(often four to seven orders of magnitude) reducing IGEN. Finally, an eqUilibrium is
reached where the IGEN2 RPTC losses are just sufficient to maintain the temperature
which corresponds to that value of RPTG Depending on the overload current level, the
reaction time of the PTC can vary from less than a second to several minutes. When the
overload is removed, it may take several tens of seconds before the PTC resistance has
dropped sufficiently to allow normal system operation.
It is usual for the PTCs to be supplied in pairs with guarantees on matching with
age and overload for line balance considerations. It is important that the "switching"
temperature is considerably above the maximum exchange ambient temperature to
avoid premature "switching" and to lessen the effects of ambient temperature on the
overload conditions. Self-heating due to the line dc and voltage drop considerations,
leads to typical PTe 25"C resistance values from a few ohms to several hundred ohms.
Determination of the protection circuit operating point is complicated by the
PTC's nonlinear resistance-current characteristic, shown in Figure 18. Initially, as the
voltage applied to the PrC is gradually increased from zero, the PTC has a constant
resistance which is shown by the vertical portion of the characteristic. The linear
increase of current with increasing applied voltage continues until the PrC reaches its
"switching" temperature and the resistance starts to increase. When this starts to
happen, the current level, lMAX, is given by:
TEMPERATURE- DC
Figure 17. PTC Resistance Versus Temperature
4-60
TC - Tamb
RPTCamb x OPTC-amb
IMAX =
where:
TC = the "switching" temperature
T amb = the ambient temperature
RPTCamb = the initial PTC resistance
{JpJ'C-amb = the PTC's thermal resistance to ambient.
On reaching this condition, further increases in applied voltage result in
decreasing current (although the power dissipated by the PTC increases slightly). This
condition is shown by the sloping part of the characteristic in Figure 18. Very high
continuously applied voltages can cause excessive temperatures to occur. Under these
conditions, the PTC's resistance starts to decrease with further increases in voltage,
which leads to a rapid increase in dissipated power. Such situations are potentially
unstable and could lead to PTe failure.
Transient Suppressor
The major parameters of the TISP transient suppressors were discussed in the
first two sections of this report. The major device losses will be caused by operation in
the avalanche (zener) region and the saturated (on) condition. The TISP1XXX family
has a diode clipping characteristic for positive wire-to-ground voltages that maximizes
the positive half cycles in the series protector. This enhances the series protector
operation when compared with the symmetrical TISP2XXX and TISP3XXX families,
which will inhibit current flow until the avalanche level, VZ, is exceeded.
•
......
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Q)
a:
102
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10 1
,~
Q.
Q.
c(
I
I/)
:E
«
100
J!. 10- 1
10- 2
10- 3
100
Figure 18. PrC AC Resistance Locus Versus Temperature
4-61
As far as the transient suppressor heating is concerned, the junction temperature
rise will be governed by the chip's thermal capacity for periods below 10 ms, by the
substantial TO-220 copper-tab thermal capacity (about 1 JoulefC) for periods in the
10 s range, and finally by the junction-to-ambient thermal resistance over much longer
periods (typically 50°C/W without an external heatsink).
AC Generator
Test specifications generally call up single phase type voltage generators with 0 <
VGEN < 250 V (rms) and source impedances of 4 < RGEN < 2000 n. Worst case
short circuit current capability is in the range of 6 A to 15 A (rms).
Graphical Analysis
A first pass analysis of the system operating conditions can be made graphically.
This will establish the major system parameters and identify sets of conditions
warranting more intensive examination. The analysis is simplified by combining the
generator source resistance, RGEN, and the series protector resistance together as a
single resistance, RS. If fuse protection is used, the few extra ohms is only significant at
very low values of generator resistance (unless the fuse blows, of course). PTCs however,
can increase the net resistance, RS, considerably, sometimes to hundreds of kilohms
when heated. Figure 19.shows how the test generator can be considered as a load line, of
slope RS, drawn from a sinusoidally moving point on the horizontal axis of the
symmetrical suppressor characteristic, which corresponds to the instantaneous value of
generator voltage. For clarity, only the positive quadrant of the characteristic is shown.
Specific voltage levels A, B, C, and D are highlighted where the suppressor operation
changes or values are maximum.
ITMAX
tZ
w
a::
a::
:::l
(J
...
' ... ...
'''' ...
"'''', ...
----------~
--.........
--
c
VOLTAGE
Figure 19. Voltage Generator Load Line and Waveforms
4-62
The suppressor starts to clip, causing current flow, when the instantaneous value
of generator voltage, denoted by the lower case letters Vgen, reaches Vz at point A.
When point B is reached, breakover occurs and the instantaneous value of the
generator voltage, Vgen, is:
Vgen
=
VBO + IBO x RS
where VBO and IBO are the suppressor's breakover voltage and current.
For a given value of nns generator voltage, VGEN, the maximum value of source
resistance, RSCMAX, which will just initiate breakover is given by:
R
SCMAX=
VGEN
fi - VBO
IBO
In operation, as the suppressor warms up, the breakover current, IBO will
decrease, causing the critical value of source resistance, RSCMAX, to increase. This
can lead to situations where the suppressor initially only avalanches rather than
triggering due to RS > RSCMAX, resulting in a high suppressor power dissipation but
a low nns current. As the suppressor warms up, the decrease in breakover current,
lBO, allows the original value of source resistance to initiate triggering. The mean
dissipation in the suppressor then drops substantially but the rms current greatly
increases, enhancing the potential operation of the series protection. Because of this,
the possible nns current range is not a continous spectrum but has a gap between the
avalanche and the crowbar modes of operation. This aspect is further considered in the
Analysis of Fuse Protected Systems subsection.
a
(I)
1::
o
In the "on" condition for TISP2XXX and TISP3XXX devices and for the
TISPIXXX diode operation, the peak value of suppressor current, ITMAX, caused by
the peak value of generator voltage at C will be approximately given by:
lMAX = VGEN
Rs
Co
Q)
a::
c:
o
fi
.+1
ca
.2
Point D illustrates the condition where the load line intersects the avalanche
characteristic as the holding c!1rrent is reached and, once delatching occurs, the
suppressor clamps for the second time in that half cycle. If the "on" voltage of the
suppressor at the holding current, IH, is Vrn, then the critical value of source
resistance, RSZ, for this to happen is:
R
Q.
Co
«
_ Vz - VTH
SZIH
Usually, in practice, this condition only occurs over a narrow range of generator
values. More typically, the unlatching point is reached when the instantaneous
generator voltage is below the avalanche voltage, VZ, and hence a second period of
avalanche conduction does not occur.
4-63
RMS Generator Current
Because the protection system is nonlinear and temperature sensitive, the
calculation or measurement of rms current and power is not straightforward. Based on
the above analysis, it is possible to devise a simple computer simulation of the protection
system. This model can be used to establish the full range of operating conditions with
practical measurements as verification checks.
In the practical tests, true rms meters (rather than those types which scale peak or
mean values) should be used. They should have a wide frequency response and large
peak-to-rms capability to avoid overload inaccuracies. The rms current due to thermal
effects in the protection elements often rapidly changes with time, and some form of
data logging system greatly aids the analysis of the series element operating conditions.
Oscilloscopes which permit the multiplication of the instantaneous suppressor voltage
and current can be used to determine the dissipation levels. Accurate zeroing of the
signals is very important to avoid substantial errors because usually one large quantity is
multiplied by a much smaller one. In the avalanche region, dissipation can be the
product of a high voltage and a small current, while in the saturated condition, it is the
product of a low voltage and a typically high current.
System Effects of Generator Peak Voltage Amplitude
•
This subsection considers the system effects as the generator voltage amplitude is
varied from below the transient suppressor avalanche voltage, VZ, to the maximum
available. Only the wire-to-ground test condition will be discussed, but the same general
principles, appropriately modified to comprehend the suppressor A-B characteristics,
can be applied to the wire- to-wire situation. The discussion will concentrate on the
latest generation of "transformerless" SLIes because they are the most susceptible to
failure under ac line contact.
.Ji x VGEN < Vz, TISP2XXX and TISP3XXX Families
Under these conditions, the transient suppressor will not be exercised at all, but
the output stage of the SLIe may be, if connected to the line at that time. Although
many of the specifications are not definitive about the SLIC condition during this test, it
would be reasonable to examine the situation when the SLIC is in an active-state,
driving the appropriate line current into a simulated line impedance, to comprehend
any potential service problems.
The reaction of the SLIe to this condition strongly depends on the design
implementation. Often, there will be several feedback loops employed to stabilize
operating conditions and minimize dissipation. One scenario could be the SLIC control
system would interpret the ac line contact as a common mode signal, which it would try
to counter by driving an antiphase current.
Another possibility, particularly for unidirectional systems which do not have a
sink and source capability on each wire, is that the control loops would be totally
overloaded, leading to the output stage switching and driving high peak currents into
4-64
the test generator. Both these conditions could lead to abnormally high dissipation in
the
output section, leading to device failure. Obviously some form of thermal
shutdown incorporated in the
design would guard against this.
sue
sue
The average voltage from the generator is zero and some sue loops may treat
this test as a resistive load (= RS) to ground. This condition could then be reasonably
safe because wire shorts to ground obviously have to be considered in any sue design.
The performance of the system under these conditions is purely a function of the
sue implementation. It is doubtful that the SLIe will produce rms currents high
enough to cause the series protection to operate .
.J2 x VGEN < Vz TISPIXXX Family
The TISP1XXX family has a diode characteristic for positive voltages. Thus most
of the current from the generator during the positive half cycle will be shunted to
ground. If the
is capable of sinking current from the generator, the ac voltage from
the generator system will be displaced by a dc voltage of IUNE x ROEN in the
negative direction. Hence the positive voltage period will be made shorter than the
negative voltage period and the TISP1XXX diode will conduct for less than 1800 over a
complete cycle.
sue
sue
Similar comments on the
operation as in the previous subsection apply, but
in this case there is a real chance the series protection elements will operate for source
resistances under several hundred ohms, due to the higher rms current caused by the
diode clipping.
II
U)
~
o
Co
G)
a:
200 VI
c
o
o
'';:;
&U
.2
Q.
Co
«
o
0.5 AI
10 WI
o
Figure 20. TISP2XXX and TISP3XXX AC Line Contact Conditions
4-65
Vi x
VGEN > VZ, TISP2XXX and TISP3XXX Families
This situation will result in suppressor conduction if the SLIC is not active. As
discussed earlier the reaction of an active SLIe depends on the implementation, but
typically it can be expected to introduce asymmetry into the positive and negative
clipping of the ac waveform. For simplicity the following assumes the SLIC is inactive.
In this condition, Figure 20, the suppressor will definitely avalanche and
depending on the generator values, it may trigger "on" (See Graphical Analysis
subsection).
,fi x VGEN
> VZ, TISPIXXX Family
In this condition, Figure 21, the positive voltage excursion will be clipped as
before when the voltage was less than VZ. Also the suppressor will avalanche in the
negative direction and depending on the generator values, it may trigger "on" (See
Graphical Analysis subsection).
Analysis of Fuse Protected Systems
Figure 22 reproduces the fusing characteristic from Figure 16. In this example a
fuse resistance of 6 fl is assumed, a voltage generator range of 0 to 250 V rms, and
generator resistance of 4 fl and 2000 fl. The TISP transient suppressor rms current
capability will vary with the device type, dissipation mode, test generator, circuit
configuration used, temperature, and test time. Semiconductor ratings are usually well
controlled but obviously the quoted values will be worst case. The suppressor
dissipation curves shown dotted are based on a 150-V symmetrical type device. When
the source resistance, RS, is very low the main dissipation is from "on" condition
50 VI
0.5 AI
o
10 WI
Figure 21. TISPIXXX AC Line Contact Conditions
4-66
o
"C
"2-
rr
Dl
...O·
::::I
:a
CD
"C
o
~
(I)
guarantee fusing. Hence in the longer term (if the generator application is of a
continuous nature) then the suppressor could overheat and possibly fail. The time scale
for this to happen will be governed by the thermal package-to-ambient parameters and
the dissipation level. This creates the" ,
" shaped potential failure area in Figure 22
for periods greater than 10 s and the specified gerierator levels.
This has been a very simplistic analysis of the conditions. Fusing curves are often
based on dc tests, however, because the transient suppressor parameters are
temperature dependent (principally IBO and I H) and the rms system current will be
changing with time which will modify the fusing characteristic. In addition, fuses, being
thermal in nature, will tend to fail at specific points in the ac cycle (Reference 1).
Another factor neglected is whether the SLIC is shunting the suppressor and passing
additional current through the fuse.
Analysis of PTe Protected Systems
Figure 24 reproduces the PTC characteristic given in Figure 18. Also shown are
the rms currents which would flow when a 150-V symmetrical suppressor is used. Curves
are shown for minimum, 4 n, and maximum, 2000 n, generator resistance, RGEN and
for two suppressor junction temperatures. The reason for showing device curves for high
and low temperatures is that some idea of the working point trajectory can be gained.
4-68
102
SUPPRESSOR @ T jmax _
SUPPRESSOR @ 25 DC _
A
101
RpTC
RpTC @ 25 D C ___ .
c(
100
I
I/)
J
10- 1
10-3~--~----~----~----~--------~
100
103
RpTC-O
Figure 24. RMS CUITent Versus PTC Resistance
Initially, the 4-n generator resistance combines with the unheated 10-.0. PTC
resistance to give the working point A. As the PTC heats up due to the high current, a
stable working point is achieved at B. Initially, the suppressor heavily saturates but as
the resistance increases a temperature sensitive point is reached when saturation stops.
This condition is shown by the step in the suppressor's current characteristic. Although
the rms current drops considerably at this point, there is still thermal inequality in the
PTC for its dissipated power which is only removed when point B is reached.
II
U)
1::
o
Q.
CD
When the generator resistance is 2000 .0., the initial working point is D. This
condition is stable for the PTC but the suppressor power loss CUlVes, shown in Figure 25,
indicate excessive long term dissipation. As the suppressor warms up, breakover occurs,
and dissipation is reduced. A working point which is just stable occurs at C. In practice,
due to thermal capacity differences and thermal coupling, the final working point is
more likely to be at B.
IX
c
o
'';:::;
co
,2
Q.
Q.
ct
Although operating end points can be predicted using this method, computer
simulation or practical testing is necessary to ensure the devices do not fail during the
intermediate period.
4-69
SUPPRESSOR
0 T jmax _
0 25°C _
SUPPRESSOR
RPTC
10- 2
~_...a.
_ _-'-_--II 103
102
SUPPRESSOR DISSIPATION - W
Figure 25. RMS CUITent Versus Average Suppressor Power
•
Summary
The nsp transient suppressors provide telephone designers with a new costeffective way to protect the increasing number of semiconductors, particularly
integrated circuits, in their equipment. Specifications for the main dc parameters ID,
IH, lBO, and Vz can be determined from system parameters:
1. on-state and off-state line currents
2. on-state line current variation with temperature
3. maximum values of battery and ringing voltages
4. maximum value of test voltages
5. maximum negative voltage voltage of the SLIe.
The example values used in this report represent only typical system
requirements.
The basic evaluation techniques for ac line contact shown in this report will
identify critical areas for further study. The effects on the system of other shunt
elements have been ignored to simplify the presentation at the risk of inaccuracy at high
values of source resistance, RS. Some of the ac data used is not normally specified in this
form by the industry, although it is available in other forms. With the increasing
popularity of crowbar suppressors, it is hoped that manufacturers will start to provide
data in a form compatible with computer analysis· and design.
4-70
References
1.
2.
Electric Fuses, A. Wright & P. G. Newbery, Peter Peregrinus Ltd.
PTe Materials Technology, 1955-1980, B. M. Kulwicki, Advances in
Ceramics, Volume 1, Grain Boundary Phenomena in Electronic CeramiCs,
1981, The American Ceramic Society.
II
4-71
•
4-72
Designing with the
TCM1500 Bell Tone
Ringer/Detector Fatnily
..
U)
1::
o
Q.
CD
a:
c
o
';::
ca
,g
Q.
Q.
2
40V
16 Hz
O~
o
____
~
______
~
130 V
68Hz
______-L______
4
2
100 V
30Hz
~
______L -____
8
6
10
~~
12
____
~
14
limA)
•
la) OUTPUT VOLTAGE V5 WAD
30000
U)
25000
t:::
oQ.
40 V rms
Q)
a:
..
c
20000
'
o
ca
,g
9
!i
Q.
Q.
15000
ct
10000
6000
10
20
30
40
FREQUENCY 1Hz'
(b) OUTPUT OPEN
Figure 14. TCM1S10A Drive C8pability
4-87
Figure IS illustrates one example of how to interface
to the TCM I 520A when isolation is not required. The IO-ldl
resistor is required only if the oppusite sense of the output
signal is desired.
LEVELS
GND---------------,
I/O I-------...--~C::MOS=~--,
"p
LEVELS
1+5 VI
OR
LOGIC
+VESIGNAl
40V
TO
1SOV
AC
II
10"F
CF
sov
Figure 15. TCM1520A with Nonlsolated Supply
T
MODEM
DAA
"P/"C
R
+5V
2.2
kSl
0.47
~
1/4W
2.2k
"F
TCM1520A
8
6
7
Figure 16. Autoanswer Modem Application
4·88
Autoanswer MODEM
Figure 16 shows how the TCMI520A may be used to
design an autoanswer MODEM. The incoming ring signal
is detected by the TCMI520A which drives an optoisolator
to give a MOS/TTL compatible signal to the I'P. The I'P on
recognizing a valid ring signal gives an off-hook (OH) signal
to DAA (Direct Access Arrangement), thus answering the
"phone. " The transmitting device can now send the carrier
and start data transmission. The TCMI520A goes in the
standby mode offering a better than I-MO impedance to
signals below 5 V rms, thus offering no signal degradation
to transmit or receive audio signals.
TCM15Z0A as a Low Current Power Supply
The TCMI520A may also be used as an inexpensive
5-V power supply as shown in Figure 17. This circuit may
be plugged directly into a standard 110 V, 60 Hz wall outlet
and a regulated 5 V is available at pin 4. The current drive
capability in this configuration is dependent upon the series
limiting resistor. With a 6.S-kO resistor, as shown, the drive
capability is about 7 mA.
I'C Control of Ringer
Figure IS shows how a TCMI512B and a TCMI520A
may be used to detect a ring signal and then let a
microcomputer decide whether to ring the ringer or not. The
TCM I 520A is used to detect the presence of a ring signal.
The TCM1512B is used to drive the piezo transducer. The
ringer disable switch could be used to tell the microprocessor
whether to ring the ringer or start the tape recorder.
6.8 k!1 1 WATT"
1+5 V)
10V)
SYSTEM
110 V rms
60 Hz
II
.....
!/)
o
Co
Q)
a:
c:
o
'';:;
CO
CJ
"EXTERNAL RESISTOR MUST SUSTAIN
TRANSIENT WITHOUT BREAKING DOWN.
IVpk ..3000 V)
BYPASS
Figure 17. Small Current Power Supply
Q.
Co
«
+5V
RINGER
ENABLE/DIS.
1kSl
+
+5V
1/4W
2.2kSl
0.47,.F
T--t~_-t
2.2 kSl
IN
,.C
TCM1520A
OUT
R------I
OUT
"'"-:6~----::T--'
+12V
START
RECORDER
1/4W
2kSl
5
6
TCM1512B
7
4
•
ROSC
c:::s
~
PIEZO
Figure 18. Using TCMIS10A to Detect Ring Signal and pC to Drive TCMIS12B
4-90
APPENDIX A
Impedance vs Frequency Curves for Various Values of Capacitors
to Simulate Piezo Performance
30000
25000
20000
S
is!:
15000
II
10000
5000 L -______
~
______
~
______
~~
______
~
______
~
_______J
U)
10
20
30
40
50
60
t::
70
oQ.
FREQUENCY (Hz)
(a) VIN - 40 V rms
CD
a:
Figure A-I. TCMI50IB Using Capacitors to Simulate Piezo Performance
C
o
".j:i
CQ
"~
Q.
Q.
'2.
"0
c;'
...0'
C»
::s
20000
s
Ii
15000
::J2
CD
"0
......0
10000
(II
5000 ~------~~--------~------~~------~--------~--------~
30
10
40
50
60
70
20
FREQUENCY (Hz)
(e) VIN -
130 V r ....
Figure A-I. TCMISOIB Using Capacitors to Simulate Piezo Performance (Cont'd)
4-92
APPENDIX B
Kyocera Piezoelectric Acoustic Generator Specifications
Contact your local Kyocera International, Inc. representative for further details on their devices.
Headquarters: Kyocera International, Inc.
8611 Balboa Avenue
San Diego, CA 92123
(619) 279-8310
Texas:
Kyocera International, Inc.
13771 N. Central Expressway
Suite 733
Dallas, Texas 75243
(214) 234-2408
•
en
t:
o
Q.
Q)
IX:
..
I:
o
ca
.~
Q.
Q.
'0
"2c:;"
...0'
Ringing
This function supplies a ring signal to the subscriber device by switching a ring
generator onto the local loop. The signal is typically a 90 V rms sine wave at 20 Hz and
is gated for one second on with three seconds off.
C»
Test
::s
Testing involves the use of relays to provide access to the local· loop and to the
switching circuits in order to test the line.
:a
CD
'0
o
;::.
(I)
Low-Voltage Functions
Supervision
When the subscriber apparatus is taken off-hook, the local loop is closed and a dc
current is allowed to flow. The supervisor function monitors this loop current to determine
when the telephone goes OD- or off-hook. It is also used to perform dial-pulse accumulation
when rotary-dial telephones are used. Dial pulses are generated by opening and closing
the loop in rapid succession.
Codec and Filter
The Codec function is performed when an analog line is interfaced with a digital
trunk. Encoding is carried out on the analog signal from the loop, and decoding is performed
on the bit stream from the trunk. A voice-band filter (300 Hz to 3500 Hz) is used before
encoding"and after decoding.
4-106
Hybrid
The hybrid function separates the bidirectional voice signals from the two-wire loop
into distinct transmit and receive paths. This separation facilitates the use of analog repeater
amplifiers or digital processing circuits. The hybrid function is named for the specialized
transformer that has traditionally performed this two-wire to four-wire conversion.
Theory of Operation
Signaling
In addition to the supervision signaling previously described, two other types of
signaling are used: ring and dial pulse signaling.
Ring Signaling
A ring signal is initiated in the CO or PBX and is used to alert the subscriber to
an incoming call. The ring signal is injected onto the local loop by switching a ring generator
in series with the battery.
The ring signal in the United States is a sine wave ranging in frequency from
15.3 Hz to 68 Hz, and in amplitude from 40 V rms to 150 V rms. The signal is gated
on and off in a particular 'cadence.' A typical ring signal in the U.S. is 90 V rms at
20 Hz gated for one second on and three seconds off.
Dial-Pulse Signaling
Dial pulses are generated by making and breaking the subscriber loop in rapid
succession. Figure 2 shows loop current as a function of time during dialing. In the United
States, the recommended timing requirements for dial pulses are given by the Electronics
Industries Association RS-470 standard. This document specifies a pulse period from
91 to 125 ms, with a percent break between 58 and 64. Here, percent break is defined
as follows:
[(break duration)/(break duration + make duration)] X 100
CI)
1::
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IV
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4-107
O~ HOO~.
I
I
OFF HOOK-+- DIGIT "2"
I
DIALED
I
;. '--~"----i'
III
TIME
-
+- B:"~:EEEN
DIGITS
I
I
_
+I.o--___ DGT "S" _ _ _.........
01
.....
DIALED
I
I
- - - o f..t----;'
j-'
I"""
-
-
I
I
I"""
'..-
D~:!~I~N~I.....-_IF~I--I~T~~g,;;'I~ --jMAKE
INTERVAL
DURATION
" 91 ms
oS 125 ms
PULSE
PERIOD
91 ms oS PULSE PERIOD oS 125 ms
INTERDIGIT INTERVAL" 700 ms
58 oS PERCENT BREAK oS 64
Figure 2. Dial Pulse Timing Diagram
Device Description
II
The pin functions ofTl's three SLCCs are given in Table 1, and the functional block
diagram is shown in Figure 3. Each SLCC can be divided conceptually into digital, analog,
and supervisor functions.
Digital Functions
The heart of the digital section of the SLCC is a 24-bit data storage unit (DSU).
This DSU contains bits of read only and read/write data to provide hook status, relay
control, transmit and receive gain control, and line-balance selection.
The bits in the DSU are accessed through a single DATA pin. A low transition on
the chip enable input (CE) causes the DATA pin to change from a high impedance to
an active state, and sets the pointer/counter to bit O. The pointer is advanced by a positive
transition on the clock (CLKM) input. The read/write (R/W) input determines the direction
of information flow on the DATA pin. See the TCM4204A data sheet for a detailed timing
diagram.
Analog Functions
The analog functions consist of the receive and transmit signal paths, with attenuators,
and the hybrid function. The receive and transmit attenuators increase the versatility of
the SLCC. The receive path gain is variable from -7.8 dB to +4.8 dB in 0.2-dB increments.
The transmit path gain is variable from -12.6 dB to 0.0 dB in 0.2-dB increments.
4-108
Voo
Vss
ANLG
DGlL
GNO
GNO
REF1
.;><>---RXIN
------------1
r-
elKS ------'L_C_LO_C_K_
~ CIRCUIT ..'
RXO+
>----RXO-
DECODERS
> .....--------- BALOT
002'
LOOPBACK
FROM
SALO
BALANCE
SWITCH
BAL1
BAL2 (TCM4204A, 4205A)
TXFB-------,
TXI+
TXOT
TXI-
SUPOT (TCM4207AI
II
......
III
AUX1
AUX2 (TCM4205A)
AUX3 tlCM4205AI
RNGR
0
Q.
Q)
a:
I:
CENZ
ClKM
PWRU tTCM4205A)
REWZ
0
',j:
ca
.~
Q.
DATA
Q.
«
110
POWER
FAULT
BIT
.... V
--<;V
BAL
AANOB
TO TX ATTENUATOR
TO AX ATTENUATOR
Figure 3. Internal Configuration of the Subscriber Line Control Circuits
4109
Table 1. Pin Functional Description
NAME
ANlG GND
AUXl
PIN
TCM4204A
TCM4205A
4
4
11
11
11
AUX2
12
AUX3
13
BAlO
19
23
19
18
17
22
21
18
5
5
5
BAlOT
Analog ground
Latched digital outputs for relav control
BAll
BAl2
DESCRIPTION
TCM4207A
4
Analog input to balance network selection
A buffered form of the RX signal for application to the external balance
network
CE
9
9
9
Chip enable. Activated by a logic low input.
ClKM
7
7
7
Digital clock input that advances the pointer counter of the digital
storage unit (DSU) allowing the information in the OSU to be
accessed, When R/W and
CE
are low, information on the
DATA I/O pin is latched into the DSU by the falling edge of ClKM.
ClKS
13
15
13
A continuous clock input (from 1.536 to 2.048 MHz) used for internal
DATA I/O
10
10
10
Digital data input/output. When
logiC. This signal is not synchronous with any other signal.
ee is low and
DATA I/O pin is in the output mode. When
R/W is high, the
CE is
low, the DATA I/O pin is in the input mode. When
low and R/'ifJ is
CE is high, the
DATA I/O pin is in the high-impedance state,
DGTl GND
12
14
12
Digital ground
GS REF
20
Analog reference voltage input used for ground start supervision.
PWRU
17
Decoded digital output of Mode Control used to control an external
power supply.
II
RNGR
14
16
14
Latched digital output to control the ring relay. The output turns off
(low) when off-hook is detected. but the controller must program
the ring bit low to ensure that the output remains low.
RXIN
6
6
6
RXO+
RXO-
2
2
2
3
3
3
R/W
8
8
8
Analog input to the receive section
Complementary analog output of the receive amplifier
Digital input control for the direction of response of the digital
storage unit. A logic high on R/'W sets the DSU to transmit
information. A logic low on R/W enables the DSU to receive
information.
SUP+
15
18
15
SUP-
16
19
16
Differential analog supervision inputs. Inputs to SUP + and SUPare used to detect off-hook status during normal and ringing
supervision.
SUPOT
TXFB
17
Filtered supervisory analog output
20
21
Feedback out of TX input amplifier
24
TXI+
20
21
TXI-
22
26
22
TXOT
23
27
23
Analog output of TX output amplifier
VDD
24
28
24
Supply voltage 15 V ± 5 % I
VSS
1
1
1
25
Analog differential inputs to TX input amplifier
Supply voltage I - 5 V ± 5% I referenced to ANlG GND
Supervision Functions
Line supervision is performed using differential inputs SUP+ and SUP-. When loop
current flows, a voltage appears across the inputs from an external resistor network. The
low-pass filter (LPF) shown in Figure 3 is used when off-hook detection is required during
ringing. The LPF is a switched-capacitor filter, and its cutoff frequency is determined
by the frequency of the input CLKS. Figure 4 shows the filter characteristics as a function
of CLKS frequency. The LPF filters out the ac component from the supervision signal
to detect a valid off-hook condition during ringing. The output of the LPF is used to set
4-110
bit 0 (on/off-hook) of the DSU. By virtue of the CLKS input, the SLCC can be used with
any frequency ring generator. With the SLCC in the voice mode of operation, the LPF
is ignored. This condition allows dial pulses to pass undistorted to the DSU.
10
0
-10
III
'0
I
Z
~C(
-20
:;)
z
...
UI
-30
ClKS
~
~
-40
r.. -1.544
-2.048
~1.0
I~ .....
-50
MHz
MHz
MHz
~
-60
o
200
400
800
600
1000
FREQUENCY -Hz
I
10~----------T-----------T-----------~----------'
(/)
1::
o
Co
Q)
o+-----~~--+-----------+-----------+---------~
ex:
c:::
~
o
'';:::
-10+_----~~~+_----------+_----------+_--------~
ca
I
,~
z
~
-20+-----~~~~~~~~~----------~--------~
~
-30T-------~--~--~------+_----------+_--------~
:;)
ii
Co
~
-50+--4--+--4~+--4--+-~--+--+--+--+--+--+--+--+~
o
10
20
30
40
FREQUENCY -Hz
Figure 4, Filter Characteristics as a Function of eLKS Input
4-111
Functional Description
The three versions of the SLCC (TCM4204A, TCM4205A, TCM4207A) have some
functional differences. Each is designed to accommodate a different type of application,
as outlined below.
TCM4204A
The TCM4204A, a 24-pin device, is configured to operate in a standard loop-start
CO or PBX environment. It provides a ring relay output, plus one auxiliary output to control
the test relay. A provision for three balance networks allows the same card to operate
on virtually any length of line through a simple software manipulation.
TCM4205A
The TCM4205A is a 28-pin version of the SLCC and is ideal for ground-start
applications. It performs all those functions found in the TCM4204A, with the addition
of two extra relay outputs, a PWRU pin used to signal the power supply, and a GS REF
ground-start reference input.
TCM4207A
II
The TCM4207 A is identical to the TCM4204A aside from the addition of a supervisor
output, which replaces one of the line-balance networks. This supervisor output provides
a voltage that is proportional to the supervisor input-voltage. The output is used in driving
a flux-cancelling winding in the battery-feed transformer.
System Design
Supervision Circuit
A typical application of the TCM4204A in a ,loop-start system is shown in
Figure 5. In the normal (nonringing) state, the loop current (typically 20 rnA to 80 rnA)
flows through the path defined in Figure 6. The loop current causes an IR drop across
each of the 200-0 resistors, which shifts the voltage levels on the supervision inputs (SUP+
and SUP-). Figure 7 gives SUP+ and SUP- voltages as a function ofloop current. When
the differential voltage between the two exceeds the threshold, the SLCe responds by
setting the hook-status bit in the DSU to a logic high, indicating the off-hook condition.
4·112
VSS
VDD
LOCAL
LOOP
RING
l
RXO+
RXIN
r---<>ZT/2
450 D
ZL
TEST
RELAY
BALOT
RING
RELAY
-BALD
!ZT'
BAL IIBAL 1
SEL
BAL2
lJ]z.
RXO-
TIP
tt
TXOT
CLKS
MICROPROCESSOR
CONTROL
RELAY
DRIVER
BAL
SEL
Figure 5. Typical Loop Start Application for the TCM4204A
f"
w
Application Reports
II
RING
GENERATOR
R1
2000
+5 V IVOOI
•
IL
R2
1 rnO
R3
1 rnO
R4
102 kO
VBATT
ZL
SUP+
R7
R6
1 rnO 1 rnO
R10
4000
RING
RELAY
R5
107 kO
2000
R11
2.2/-1F
RS
36.5 kO
SUPR9
33.2 kO
•
Figure 6, Off-Hook Loop Current Path During Nonringing Condition
0.35
•
0.30
»
0.25
'C
'E.
(;'
...S'
Q)
::l
:XJ
CD
'C
0
......
(II
>I
0.20
W
C)
...«
0.15
cl
>
II:
0
0.10
III
:>II:
w
Q.
;:)
0.05
III
0
50
-0.05
IL - LOOP CURRENT -rnA
-0.10
Figure 7, Supervision Voltage vs Loop Current
4-114
A detailed diagram of the supervision circuitry of the SLCC is given in Figure 8.
The details of supervisor operation are as follows:
1. A differential voltage across the SUP + and SUP- inputs, referenced positive
on SUP+ is required to initiate the off-hook condition (bit 0 high) in the standby
or power-down mode.
2. Initial off-hook detection is always done in the standby or power-down mode.
3. The voltage across SUP+ and SUP- required for off-hook detection is 50 mY.
4. For rejection of the ring signal, the supervisor information is filtered with
a switched capacitor low-pass filter when not in the voice mode.
5. When the ring bit is set high, an off-hook detection causes the ring relay output
to go low; however, the ring bit must be reset to low by the controller before
the controller changes the SLCC to the voice mode.
6. The voltage on either SUP input should always be between -2 V and
+2.5 V. Outside this range, the supervision circuits become non-linear and
the SUP inputs may require significant current. For this reason it is
recommended that SUP + and SUP- both be near 0 V for no-loop current.
7. After initial off-hook detection, the SLCC should always be placed into the
voice mode.
8. When the SLCC is placed in the voice mode, on-hook is detected using a peakdetector circuit. The peak-detector samples and stores the peak value of the
SUP differential voltage. On-hook is detected when the SUP voltage falls below
half the stored voltage. This circuit provides the ability to detect dial pulses
and on-hook at the termination of a call.
9. The peak~detector circuit capacitor is discharged to 0 V whenever the SLCC
is placed in the ring mode or when the Supervisor reset bit is set to a high.
The Supervisor Reset should be used if off-hook is detected during standby
mode to eliminate any accumulated charge on the capacitor due to noise.
II
(/)
1::
o
Q.
Q)
a:
c
o
'';;
co
,~
c..
Q.
If the subscriber returns to on-hook status while the Supervisor Reset bit is being
used, then the SLCC cannot accurately detect the on-hook condition since, both the SUP
voltage and the peak detector are at 0 V. This inability can be prevented by providing
a dc bias-voltage in the reverse direction on the SUP + and SUP- inputs when no loop
current is flowing.
cd:
During pulse dialing, the loop current is pulsed off and on approximately ten times
per second. When the SLCC is in the voice mode (set through the microprocessor interface),
the supervisor information from SUP+ and SUP- is routed through apeak detector circuit,
bypassing the low-pass filter. The pulses toggle the hook status bit in the DSU as the loop
current is pulsed. The controlling microprocessor monitors this bit and counts the dial
pulses. Dial-pulse accumulation can be accomplished only in the voice mode, because
the low-pass filter will distort the dial pulses.
4-115
SlJodal:l
~
UO!le~!lddv
II
Cll
VDD
VOICE
MODE
PEAK DETECTOR
RING
RELAY
LATCH
AND
BIT 0
REF1----t
SUP+
A=2
LOW PASS
FILTER
SUP-
.,
GSREF----I
RING
SUPERVISOR
RESET
(BIT 231
Figure 8. Supervision Circuit Block Diagram
GROUND START
(BIT 21
Ring-trip is the supervisor function which involves detecting off-hook during the
ringing condition and resetting the ring relay. The SLCC must be in the standby or powerdown mode when the ring bit is set to allow the LPF to reject the ring signal from the
supervisor information.
When the ring relay is activated, the system is reconfigured as shown in Figure 9.
The off-hook dc current path has been traced to illustrate the ring-trip function. When
the telephone goes off-hook in the ringing condition, the IR drop across the 400-0 resistor
causes the potential at the SUP- input to drop below that at the SUP + input. The SLCC
automatically turns off the ring relay output when the hook status bit has been set. The
controller must then reset the ring bit as soon as an off-hook condition has been determined.
+5 V (VOO)
•
R1
2000
R2
R3
1 mO 1 mO
R5
107 kO
R4
102 kO
-48 V
VBATT
sup+
BATT
R6
R7
1 mO 1 mO
R10
I
I
2.2 ,..F
e---+-+ SUP-
R8
R9
36.5 kO
33.2 kO
II
4000
I/)
t::
o
I
c.
I
RING
RELAY
CI)
a:
c:
2000
R11
...co
.2
.~
Figure 9. Off-Hook Loop Current Path During Ringing Condition
c.
c.
'C
'E..
rr
£»
...0'
::::J
0.5
>I
I-
i
0.4
:;)
::a
CD
en
0.3
'C
0
...
~
(I)
0.2
0.1
0
10
20
30
40
IL -LOOP CURRENT -mA
Figure 12, SUPOT as a Function of Loop Current
4-122
50
0.1 J.lF
u----
SUPOT
220 mV Typ
R3
FLUX-CANCELLING
WINDING
-48 V
Figure 13. High-Impedance Drive Circuit for a Flux-Cancelling Winding
Increasing the gain of the op-amp circuit and adjusting R1 accordingly minimizes
the dissipation of power in Ql. The upper limit on R1 is determined by the maximum
current that must be provided, plus the dc resistance of the winding. At maximum current,
Q1 must remain out of saturation; that is, VCE > VCE(sat).
II
.......
II)
o
Q.
A design example is a flux-cancelling to subscriber-to-CO turns ratio of 5: 1: 1. From
Figure 12, notice that at 0 rnA loop current SUPOT is 0 V, and at 20 rnA loop current
SUPOT is 0.4 V. These points give a slope of (0.4 - 0)/(0.02 -0) = 20. Since only one
fifth the loop current is required, R1 is chosen as 20 x 5 = 100. The power dissipated
in Q1 is the following:
Pdiss = IC x VCE
= IC[48 - IC(R1 + RW)]
= IC[48 - RT X IC]; RT = R1
Q)
cc:
c
o
'oP
C\:I
.2
C.
Q.
«
+ RW
where RW is the dc resistance of the winding. The maximum power
dissipation occurs where the first derivative is 0:
dPdiss/dlC = 48 - 2RT x IC = 0
IC= 24/RT
Substituting this value into the power equation gives
Pdiss(max)= (24/RT)[48 - RT(24/RT)]
= 24/RT
= 576/RT.
4-123
The collector-to-emitter breakdown voltage of Q I must be considered. This transistor
must tolerate a VCEO of 48 V, and one possible component for this position is the
2N2905A.
The operational amplifier Al in the diagram can be any inexpensive circuit that will
operate from +5 V to -5 V, such as the MC1458 dual op-amp.
Figure 14 shows a TCM4207A application with the flux-cancelling drive circuit.
100 kO
R
VDD
•
~~~~~--~RXO+
»
ri-'vv~---tRXO-
TEST
RELAY
"C
"C
elKS
(i'
R
I»
r+
DATA
0'
::::s
::tI
RXIN
DGTL
GND
ANLG
GND
TXOT
R/W
T
CD
"C
..
I
I
0
r+
+5 V
RING
RELAY
en
R/9.4
R/9.S
~------------------~~~--~SUP
L-----------------~~~._----~SUP+
LEGEND
ANALOG
GROUND
DIGITAL
GROUND
~
tTypically. R
R/29.6
R/27.2
i.
=
1 mO
Figure 14, TCM4207A SLCC Standard Subscriber Line
4-124
-
Conclusion
The Subscriber Line Control Circuits from Texas Instruments offer all low-voltage
line-card functions on a single CMOS IC. This solution provides high performance while
using less board space than conventional solutions. The low power consumption (typically
75 mW) of the SLCC also gives it improved reliability over other solutions. For further
specifications of the TCM4204A series, refer to the data sheet elsewhere in this book.
II
(/)
1::
oQ.
CI)
ex:
c:
o
co
,2
Q.
c.
',tj
«
4·125
4-126
Contents
Page
Ordering Instructions . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mechanical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . _ . . . . .
C
...
ell
ell
5-2
5-3
5-5
ORDERING INSTRUCTIONS
Electrical characteristics presented in this data book, unless otherwise noted, apply for the circuit type(s)Usted
in the page heading regardless of package. The availability of a circuit function in a particular package is denoted
by an alphabetical reference above the pin-correction diagram(s). These alphabetical references refer to
mechanical outline drawings shown in this section.
Factory orders for circuits described in this data book should include a four-part type number as explained in
the following example.
EXAMPLE:
TCM
2222
J
-00
prefix------------------------------------------------JI'
MUST CONTAIN THREE OR FOUR LEITERS
TCM . . . . . . . . .. TI Telecommunication Products
TIL. . . . . . . . . . . . .. TI Optoelectronics Products
TISP. . . . . . . .. TI Transient Voltage Suppressors
TLC ..... TI Linear Silicon-Gate CMOS Products
Unique Circuit Description ------------------------------'
MUST CONTAIN THREE TO EIGHT CHARACTERS
(From Individual Data Sheets)
Examples:
181
2222
3180
32041C
29C13N-3
Package--------------------------------------J
MUST CONTAIN ONE OR TWO LEITERS
0, OW, DY, FN, HA, HB, J, JT, JW, KC, N, NT, NW, P
(From Pin-Connection Diagrams on Individual Data Sheet)
II
..
Instructions (Dash No.1 ------------------------'
MUST CONTAIN TWO NUMBERS
ca
ca
-00 No special Instructions
-10 Solder-dipped leads (N and NT packages only)
c
Circuits are shipped in one of the carriers below. Unless a specific method of shipment is specified by the customer
(with possible additional costs), circuits will be shipped on the most practical carrier.
(D,DW,DY,J,JT,JW,N,NT,NW,PI
-Slide Magazines
-A-Channel Plastic Tubing
- Barnes Carrier
-Sectioned Cardboard Box
-Individual Cardboard Box
Chip Carriers (FN)
-Anti-Static Plastic Tubing
Flat (HA, HB)
-Wells Carrier
TEXAS ~
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
Power Tab (KC)
-Sleeves
1!"2
ca
.c
(,)
CD
:i
5-3
II
3i:
CD
n
::T
C»
::s
c;"
!.
...c
C»
C»
5·4
MECHANICAL DATA
0008.0014. and 0016 plastic "small outline" packages
Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation, and
circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads
require no additional cleaning or processing when used in soldered assembly.
0008, 0014, ..d 0018
l18-pIn package ueed for Illustration)
f
~r-
I
5.80 10.2281
4.00 10.1571
'3.i1To':15oi
L-~:;::;:::;::;;::;::;:::::;:::;::;::;::~
i
1.75 10.G691
;:35To:ii531
7" NOM
4 PLACES
j
l
0.79 10.031 I
D.2ii'iii.iii11
0,457 (0.0181
0,35610.0141
1.12 10.G441
~
PIN SPACING
1.27 10.0501
(See No•• AI
~
DIM
A MIN
A MAX
8
14
18
4,80
(0.189)
6,00
(0.197)
8.55
(0.337)
8,74
(0.344)
9,80
(0.386)
10.00
(0.394)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A.
B.
C.
D.
LI
Leeds are within 0,25 (0.010) radius of true position at maximum material dimension.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,16 (0.006).
lead tips to be planar within ±0,051 (0.002) exclusive of solder.
TEXAS ..,
INSTRUMENTS
POST OFFICE BOX 855012 • DALLAS. TEXAS 75266
5-5
MECHANICAL DATA
DW016, DW020, DW024, and DW028 plastic "small outline" packages
Each of these "small outline" packages consists of a circuit mounted on a lead frame and encapsulated
within a plastic compound. The compound will withstand soldering temperature with no deformation, and
circuit performance characteristics will remain stable when operated in high-humidity conditions. Leads
require no additional cleaning or processing when used in soldered assembly.
DW016, DW020, DW024, and DW028
(20-pln package used for iDustretlonl
Ir~
~r20
10.1~
10.400)
7,55 10.2971
7~512.3' ~~~~~~~~~~~~~
,I
9,0 (0.3541
0,510.02))(
4s<'LC-~--'
11=-,
~1
r
~
40
,0
•
\ - 7 0 NOM
,PLACES
0,230 (0.0091
0,785 10.0311
1,27 (0.050)
~
~
II
~
DIM
A MIN
3:
CD
A MAX
CO)
::T
C»
:::s
tli'
!!.
..
c
C»
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5-6
Pjl
16
20
24
28 t
10.16
(0.4001
10.36
(0.408)
12.70
(0.5001
12.90
(0.508)
15.29
(0.6021
15.49
(0.610)
17.68
(0.696)
17.88
(0.704)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
tThe 2a-pin
NOTES: A.
B.
C.
D.
package drawing is presently classified as Advance Information.
Leads are within 0,25 (0.010) radius of true position at maximum material dimension.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0.15 (0.006) .
Lead tips to be plana, within ±O,051 (0.002) exclusi~e of solder.
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
OY020 plastic "small outline" package
This "small outline" package consists of a circuit mounted on a lead frame and encapsulated within a
plastic compound. The compound will withstand soldering temperature with no deformation, and circuit
performance characteristics will remain stable when operated in high-humidity conditions. Leads require
no additional cleaning or processing when used in soldered assembly.
OY020
r
8.69 10.3471
8.51 10.3351
r nn
r
2.39 10.0941
2.29 10.0901
12.96 10.6101-:-]
12.70 10.5001
[
11
g
7.60 10.2991
7.421C
1
10
0.41 10.0161
0.25 10.0101
(Sa. Note D)
~
-J
I L
-.I
3.56 10.1401 ~
3.0510.1201
+
*
0.9110.036Ij
0.7110.0281
I
1.-0.4910.0191
0.3510.0141
I
1.27 10.0501 TP
(See Note A)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A.
B.
C.
D.
Leads are within 0,25 (0.0101 radius of true position at maximum material dimension.
Body dimensions do not include mold flash or protrusion.
Mold flash or protrusion shall not exceed 0,15 (0.0061.
Formed leads to be planar within 0.10 (0.0041 exclusive of solder.
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
II
5-7
MECHANICAL DATA
FN020. FN028. FN044. FN068. and FN084 plastic chip carrier packages
Each of these chip carrier packages consists. of a circuit mounted on a lead frame and encapsulated within
an electrically nonconductive plastic compound. The compound withstands soldering temperatures with
no deformation, and circuit performance characteristics remain stable when the devices are operated in
high-humidity conditions. The packages are intended for surface mounting on solder lands on 1,27 (0.050)
centers. Leads require no additional cleaning or processing when used in soldered assembly.
FN020,FN028,FN044.FN068.andFN084
128·termlnal packaga uaad for illustration)
1
[~:::~:
122 (0 048)
1:07 (0:042) X45°
1,35 (0.053) X 450
.~
/
5
•
,," CO.'"
0
3
2
1
28
27
26
25
6
2.
7
23
~:.,
22
21
20
11
19
12
13
14
15
16
17
18
-- - -
,
'["'1'
I:
B
~__________ A_(S_H
__N_o_t._A_)__~..
OUTLINE
NO. OF
TERMINALS
MO·047AA
20
MO.(l47AB
28
MO.(l47AC
44
MO·047AE
68
MQ·047AF
B4
JEDEC
•
i:
CD
C")
:::r
I»
::s
5"
I!.
c
!!
I»
5-8
MAX
10.03
10.3951
12,57
{0.4851
17.65
{0.6951
25.27
{0.9951
30.35
11.1951
MIN
8.89
10.3501
11.43
{0.4501
16.51
{0.6501
24.13
{0.9501
29.21
(1.1501
:1'"
d
CO,""
":~:,::::UH"
(S•• Note B)
'. I
- ....···=·"~I
0.25 (0.010) R MAX
3 PLACES
SEATING PLANE
(S•• Note C)
C
B
A
MIN
9,78
10.3851
12.32
{0.4851
17.40
{0.6851
25.02
{0.9651
30.10
11.1851
2,79 (0.110)
2,41 (0.095)
0,94 (0.037) R
MAX
9,04
10.3561
11.58
{0.4561
16.66
{0.6581
24.33
{0.9681
29.41
11.1581
MIN
7,87
10.3101
10.41
{0.4101
15.48
10.6101
23.11
{0.9101
27.89
11.0BOI
MAX
8,38
{0.3301
10.92
10.4301
16.00
{0.6301
23.62
{0.9301
28.70
11.1301
0.81 (0.032) ~
0.66 (0.026)
~T
1.52 (0.060) MIN
Ii
I ~64(o.o25) MIN
0.51 (0.020) ..... I ~
0.36 (0.014) I
LEADDETAIi..
All dimensions and notes for the specified JEDEC outline apply.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Centerline of center pin each side is within 0.10 (0.004) of package centerline as determined by dimension B.
B. Location of each pin is within 0,127 (0.005) of true position with respect to center pin on each side.
C. The lead contact points are planar within 0,10 (0.004).
TEXAS ..,
INSlRUMENlS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
MECHANICAL DATA
HA06S quadrlform flat package
The 58-pin HA package is housed in a quadriform flat package. It is hermetically sealed with O.05-inchlead spacing configured with gull-wing bent leads for surface mounting capability.
HA06S
--T
1.2710.0501 TYP
0,64 (0.0251 R.
MINIMUM CLEAR
LEADFRAME ZONE
22.861 10.9001
3'051~'1201
MAX
5.0810.2001
=d~~~~~~~~~~~
4.3210.1701
I
I
1.06 10.040I-lo--+!
0.7610.0301
1.24 (0.049)
0.99 10.0391
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
•
....CISCIS
C
'is
()
'2
CIS
.c
()
Q)
:E
TEXAS ."
INSfRUMENlS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
5-9
MECHANICAL DATA
HB068 quadriform flat package
The 68-pin HB package is housed in a quadriform flat package. It is hermetically sealed with 0.05-inchlead spacing configured with straight leads for surface mounting capability.
HB068
--~1.270 10.051 TVP
[ 1.07 10.042) MAX
T~
~
114.3910.1731 MIN
o ••••
~
-*.
L
O•20 10.008)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
...C
I»
I»
5-10
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS, TEXAS 75265
MECHANICAL DATA
J014 ceramic dual-In-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7 ,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly.
J014
i:::::::
1----'9.94 (0.785)
19.18 (0.755)
I
j@@@@®cv@
0.63(0.025) A NOM
I
0
(O,;~ (0.290)
~--~~··6~.2~2~(~0.~2~~)
-1.8 :o~:SO)
~
lOS·
l4PlACES~\4~.: :~.~:
14 PLACES
(2)
0 0 ®®®®
-...f
~.
1,78 (0.0701 MAX 28 PLACES ~
SEATING PLANE
28PLACES
0,3010.0121~
O.20IO.G08\
28 PLACES
1,7810.0701
O"~I--u,
0,51(0.0201
0,41 (0.016'
28 PLACES
{See
PIN SPACING 2,54 (0.100) T.P.
{SOK' No.. A)
Notas 8 .. C)
~: :::~::
4 PLACES
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder·dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above the
seating plane.
II...
ca
ca
C
'ii
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'2
ca
.c
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G)
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 655012 • DAllAS, TEXAS 75265
5-15
MECHANICAL DATA
JT024 ceramic dual-In-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting-hole rows
on 7,62 (0.300) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or processing when used in soldered assembly.
JT024
r;;;:~:;@
.S.;;'-~:::::::::::I
ll\
7,B2 10.300)
000@®@000®@@
~
1
0.3810.0111
~24PLACES
1.27tO.05OINOMFiN
5... 10,200)
0,7610.030)
GLASS
SEALANT
SEATIN0t=pMAX
PLANE
24 PLACES
-11--
g,36tO.0141~\
,20 (O.OO8)
3,30 10.130)
MIN
2. PLACES
U
PIN sPACING 2," 10.100) T.P.
2.5410.100) MAX
4 PLACES
(See NotllAI
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longltudinsl position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dlpped leads are specified, dipped area of the lead extends from the lead tip to at leest 0,61 10.020) above the
seating plane.
5-16
TEXAS ."
INSlRUMENTS
POST OFFICE BOX 855012 • OAlLAS, TEXAS 76285
MECHANICAL DATA
JW024 ceramic dual-in-line package
This hermetically sealed dual-in-line package consists of a ceramic base, ceramic cap, and a lead frame.
Hermetic sealing is accomplished with glass. The package is intended for insertion in mounting.hole rows
on 15,24 (0.600) centers. Once the leads are compressed and inserted, sufficient tension is provided to
secure the package in the board during soldering. Tin-plated ("bright-dipped") leads require no additional
cleaning or procesing when used in soldered assembly.
JW024
I------~~~ ::~:: - - - - - - 1
@@@@@@)@@@@)@@
0.63 10.025) R
NOM
Falls Within JEDEC MO-015AA Dimensions
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal pOSition.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above the
seating plane.
5
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«I
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:IE
TEXAS
~
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
5-17
MECHANICAL DATA
N014 plastic dual-in-Ilne packaga
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation. and circuit
performance characteristics will remain stable when operated in high-humidity conditions. The packages
are intended for insertion in mounting-hole rows on 7.62 (0.300) centers (see Note AI. Once the leads
are compressed and inserted. sufficient tension is provided to secure the package in the board during
soldering. Leads require no additional cleaning or processing when used in soldered assembly.
N014
'!. 7.62. 0,25
14---*(0.300.0.010)
6,35.0.26
(0.250' 0.010)
IS•• Note. B and C)
Falls Within JEDEC TO-116 and EIA MO-001AA Dimensions
II
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin cemerline is located within 0,25 (0.010) of its true longitudinel position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads ere specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above the
seating plane.
c
At
CD
5-18
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 865012 • DALLAS. TEXAS 75285
MECHANICAL DATA
N016 plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
N018
7.62:t 0,25
(0.300' 0.0101
6,35
t.
0,25
(0.250' 0.0101
2.0 (0.0801 NOM
0,84 iO.033) MIN
IS"8 Notes B and C)
Parts may be supplied in accordance
with the alternate side view at the
ALTERNATE SIDE VIEW
option of TI plants located in Europe.
In this case, the overall length of the
package is 22,1 (0.870) max.
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.
II
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CO
CO
C
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CO
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()
CD
:E
TEXAS
II
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS. TEXAS 75265
5-19
MECHANICAL DATA
NO 18 plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
non conductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high~humidity conditions. The
package is intended for insertion in'mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
N018
7,62' 0;25
(O.JOO ' 0,010)
j 4 - - -.....t--6.99 (0.275) MAX
_ -L
2,03 fO OBO} NOM
L
0,25 (0 010) NOM
--1
-SEATING PLANE 5.08 10 'tOOl MAX
_
_\\-. 0,279 ± 0,076
~I
-*--1f
3,17 (0 125) MIN
-
(0 011:!. 0 003)
18 PLACES
(See Notes B and C)
t--1,78 (0.0701 MAX 18 PLACES
, 0 . 5MIN
110.0'Olmmwl
1,91 (0075)
0,23 (0.009)
4 PLACES
L
..j j. 0.89100351 MIN
18 PLACES
~
----..j
j.---O.457±O,076
(0 018 ± 0 003)
18 PLACES
(See Notes Band Cj
PIN SPACING 2,54 (0 laO) T P
(Sae Note Al
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES:
A, Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder·dipped leads.
C. When solder·dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.0201 above seating
plane.
c
D)
r+
D)
5-20
TEXAS . "
INSTRUMENTS
POST OFFICE BOX 655012 • DALLAS. TEXAS 75265
MECHANICAL DATA
N020 plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
N020
7,&2:!: 0,25
(0.300 ± 0.0101
2,0 10.0801 NOM
10----- ~::~~:~::::------ot
0,25 10.0101 NOM
-SEATING
20PLACES
PlANE'----If--,.-...,
--..\\t-::::bl::
20 PLACES
,Set Notes B end C)
J~ : ~ ::::!:
10-
•
4 PLACES
VIEW A
'em may be tuPPliad in accordance
with the alternate lid. view at the
s
option of TI. EufOp8an-menufaetu .....
parts may have pin 1 H shown in
view A. Alternate-side-viaw perts
manufactured outside of the USA
may have • m.ximum package length
of 26.7 11.0501.
'"
C
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.
TEXAS ."
INSTRUMENTS
POST OFFICE BOX 866012 • DAlLAS. TEXAS 75285
5-21
MECHANICAL DATA
N022 plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrica"y
nonconductive plastic compound. The compound wiil withstand soldering temperature lIVith no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 10,16 (0.4001 centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
N022
~------28.6 (1.120'
MAx----_1Of
EITHER
OR BOTH
INDEX MARKS
'i.
10.18
;t
0.26
(0.400 ± 0.0101
IS•• Note 8)
9,02 (0.356) MAX
~
'05~
~ 4- 90'
•
0.51 ( 0 . 0 2 0 ' . - - - - - - - - - - - - - - - - ,
5,08 (0.200)
~
-S~t!;!'EG--M-ltl-X--.,--.~
U
Ig:~~~ i g:~,--'\,,-
3,17 (O.1251
MIN
22 PlACES
ISee Note_ 8 and C)
1.78 (0.0701
MAX
22 PLACES
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified. dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.
c
.C»
r+
C»
5-22
1ExAs .."
INSTRUMENTS
POST OFFICE BOX 656012 • DAlLAS, TEXAS 75285
MECHANICAL DATA
N028 plastic dual-in-line package
This dual-in-Iine package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 15,24 (0.600) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
N028
1<------36.611.4401 M A X - - - - - - - \
(See Notes B and C)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified. dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
~
5
..
~
~
C
"ii
()
"2
~
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()
CD
::i!:
TEXAS .."
INSTRUMENTS
POST OFFICE BOX 656012 • DALLAS, TEXAS 75265
5-23
MECHANICAL DATA
NT024 plastic dual-in-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 7,62 (0.300) centers. Once the leeds are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
NOTE: For all except 24-pin packages, the letter N is used by itself since only the 24-pin package is available in more than one row-spacing.
For the 24-pin package, the 7,62 (0.300) version is designated NT; the 15,24 (0.600) version is designated NW. If no second
letter or row·spacing is specified, the package is assumed to have 15,24 (0.600) row-spacing.
NT024
31,S (1.250)
28.6 (1.125)
@@@@@@@0@@@@
Ii
Ii
7,62 ± 0,26
(0.300 ± 0.010)
7,1 (0.280) MAX
-1
106"
[V 90"
r
....,-
~,
.J...
";~::.==i:::::::::)
rl1 r----"m",,,,, """'''
0,38 (0.015)
-~""".- ''''~'''''
-<,.,."CAN,
~
24 PLACES --\r-0,36 (0.014)
0,25 (0.010)
24 PLACES
1_ Note. B
and CI
!
j
000000000@®®
1,14(0.045)
~
-oj
T
406(0.160)
3' 17 (0 125)
'
16 (0 085)
•
'
0,71 (0.02S)
4 PLACES
- ~
~
2
~ 1,14 (0.045) MIN
24 PLACES
I
--011---- 00,381
,533(0.021)
(0.015)
PIN SPACING 2,54 (0.100) T.P.
(See Note A)
24 PLACES
I_NotesS
and CI
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY.IN INCHES
NOTES: A. Each pin centerline is located within 0,25 (0.010) of its true longitudinel pOSition.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above the
seating plane.
cC»
;
5-24
TEXAS ."
INstRUMENTS
POST OFFICE BOX 856012 • DALLAS. TEXAS 76285
MECHANICAL DATA
NW024 plastic dual-In-line package
This dual-in-line package consists of a circuit mounted on a lead frame and encapsulated within an electrically
nonconductive plastic compound. The compound will withstand soldering temperature with no deformation,
and circuit performance characteristics will remain stable when operated in high-humidity conditions. The
package is intended for insertion in mounting-hole rows on 15,24 (0.600) centers. Once the leads are
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Leads require no additional cleaning or processing when used in soldered assembly.
NOTE: For all except 24-pin packages, the letter N is used by itself since only the 24-pin package is available in more than one row-spacing.
For the 24-pin package, the 7,62 (0.300) version is designated NT; the 15,24 (0.6001 version is designated NW. If no second
letter or row-spacing is specified, the package is assumed to have 15,24 (0.6001 row-spacing.
NW024
; - - - - - - 32.• 11.2901 MAX-------I
@@@@@@®®®@@@
u~:::~:::::::::]
CD000®®0®®@@@
-J
1,,78 (0.010) MAX 24 PLACES
24 PLACES
IS•• Not •• B and CJ
~____A_L_L_L_I_N_EA_R__D_IM__EN_S_(_O_N_S_A_R_E_I_N_M_I_L_LI_M_E_T_ER_S__A_N_D_P_A_R_E_N_T_H_ET_I_C_A_L_LY__IN__IN_C_H_E_S____~__________________~ ~
NOTES: A. Each pin centerline is located within 0,25 (0.0101 of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extends from the lead tip to at least 0,51 (0.020) above seating
plane.
TEXAS
,If
INSTRUMENTS
POST OFFICE BOX 86&012 • DALLAS. TEXAS 75285
5-25
MECHANICAL DATA
PO08 dual-in-line plastic package
This package consists of a circuit mounted on an S-pin lead frame and encapsulated within a plastic
compound. The compound will withstand soldering temperature with no deformation, and circuit
performance characteristics will remain stable when operated in high-humidity conditions. The package
is intended for insertion in mounting-hole rows on 7,62 (0.3001 centers (See Note AI. Once the leads arE!
compressed and inserted, sufficient tension is provided to secure the package in the board during soldering.
Solder-plated leads require no additional cleaning or processing when used in soldered assembly.
P008
00@0
.1....SEATING PLANE-i:-r-GAUGE PLANE
l L0,76 10.030)
"T
i.OOlO:OOiii
J~
..j I.- 0,467 ± 0,076
3.1710.125)1
I
MIN
~
.
2.54 10.100) T.P.
6 PLACES
0.28 ± 0.08
ll<--10.011 ± 0.003)
8 PLACES
fS.. Note. B end C)
lSee NOI8 A)
10.018 ± 0.003)
8 PLACES
(S.. Note. 8 and C)
ALL LINEAR DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES
i:
CD
n
=-
NOTES: A. Each pin centerline Is located within 0,25 (0.0101 of its true longitudinal position.
B. This dimension does not apply for solder-dipped leads.
C. When solder-dipped leads are specified, dipped area of the lead extenda from the lead tip to at least 0,51 (0.0201 above seating
plane.
D)
:=
iii"
!.
o
!
5-26
TEXAS ~
INSlRUMENlS
POST OFFICE BOX 855012 • DALLAS. TEXAS 76265
NOTES
NOTES
NOTES
NOTES
NOTES
NOTES
TI Sales Offices TI Distributors
ALABAMA: Huntsville (205) 837·7530.
ARIZONA: Phoenix (602) 995-1007;
Tucson (602) 624·3276
TI AUTHORIZED DISTRIBUTORS
Arrow/Kierulff Electronics Group
Arrow Canada (Canada)
Future Electronics (Canada)
GRS ElectroniCS Co., Inc.
Hall·Mark. Electronics
Marshall Industries
CALIFORNIA: Irvine (714) 660-1200,
Sacramento (91B) 929-0197;
~:~t~j~?a~~~!6~f~~o~~ggb;
Torrance (213) 217·7000;
Woodland Hills (SIB) 704-7759.
COLORADO: Aurora (303) 368·8000.
CONNECTICUT: Wallingford (203) 269-0074
FLORIDA: Altamonte Springs (305) 260·2116;
Ft. Lauderdale (305) 973-8502;
Tampa (813) 286-0420.
GEORGIA: Norcross (404) 662-7900.
ILLINOIS: Arlington Heights (312) 640-3000
INDIANA: Carmel (317) 573-6400;
Ft. Wayne (219) 424·5174
IOWA: Cedar Rapids (319) 395-9550.
Newark Electronics
Schweber Electronics
Time ElectroniCS
Wyle Laboratories
Zeus Components
- OBSOLETE PRODUCT ONLYRochester ElectroniCS, Inc.
Newburyport, Massachusetts
(617) 462·9332
KANSAS: Overland Park (913) 451·4511.
MARYLAND: Baltimore (301) 944-8600.
MASSACHUSETTS: Waltham (617) 895·9100.
~:~~~~~~Id:(~~)~~o7~4~~~~ (313) 553-1500;
MINNESOTA: Eden Prairie (612) 828-9300.
MISSOURI: St. Louis (314) 569-7600
NEW JERSEY: Iselin (201) 750-1050
NEW MEXICO: Albuquerque (505) 345-2555.
NEW YORK: East Syracuse (315) 463-9291,
Melville (516) 454-6600; Pittsford (716) 385-6770;
Poughkeepsie (914) 473-2900
NORTH CAROLINA: Charlo"e (704) 527-0930;
Raleigh (919) 876-2725.
OHIO: Beachwood (216) 464-6100;
Dayton (513) 258-3877.
OREGON: Beaverton (503) 643-6758.
PENNSYLVANIA: Blue Bell (215) 825-9500
PUERTO RICO: Hato Rey (809) 753-8700.
TENNESSEE: Johnson City (615) 461-2192.
TEXAS: Austin (512) 250-6769;
~~~~~ro~!3(5~~):~~;7~~~hardson
(214) 680-5082;
UTAH: Murray (801) 266-8972.
VIRGINIA: Fairfax (703) 849-1400.
WASHINGTON: Redmond (206) 881-3080.
WISCONSIN: Brookfield (414) 782-2899.
~~~!~~d ~~r.~~ta~~t(!~~)(~1~_~~:1 ~ 970;
St. Laurent, Quebec (514) 336-1860.
TI Regional
Technology Centers
CALIFORNIA: Irvine (714) 660-8140;
Santa Clara (408) 748-2220;
Torrance (213) 217-7019.
COLORADO: AUrora (303) 368-8000.
GEORGIA: Norcross (404) 662-7945.
ILLINOIS Arlington Heights (313) 640-2909.
MASSACHUSETTS: Waltham (617) 895-9196.
TEXAS: Rlcnardson (214) 680-5066.
ALABAMA: Arrow/Kierulfl (205) 837-6955,
Hall·Mark (205) 837-8700; Marshall (205) 881-9235,
Schweber (205) 895-0480
ARIZONA: Arrow/Klefulff (602) 437-0750;
Hall-Mark (602) 437-1200; Marshall (602) 496-0290;
Schweber (602) 997-4874; Wyle (602) 866-2888
CALIFORNIA: Los Angeles/Orange County:
Arrow/Kierulff (818) 701-7500, (714) 838-5422:
Hall·Mark (818) 716·7300, (714) 669-4100,
(213) 217-8400; Marshall (818) 407-0101, (818) 459-5500,
(714) 458-5395; Schweber (818) 999-4702:
(714) 863-0200, (213) 320-8090; Wyle (213) 322-9953,
~;:/a~~~ig?OHK1~~~k6t9~~~%~~8u~og14) 921 -9000;
Marshall (916) 635-9700; Schweber (916) 929-9732;
Wyle (916) 638-5282;
San Diego: ArrowlKierulft (619) 565-4800;
Hall-Mark (619) 268-1201; Marshall (619) 5"18·9600.
Schweber (619) 450-0454; Wyle (619) 565-9171,
San Francisco Bay Area; Arrow/Kierulff (408) 745-6600,
Hall-Mark (408) 432-0900; Marshall {408} 942-4600:
Schwebel (408) 432-7171, Wyle (408) 727-2500;
Zeus (408) 998-5121.
COLORADO: Arrow/Kierulff (303) 790-4444;
Hall-Mark (303) 790-1662; Marshall (303) 451-8383,
Schweber (303) 799-0258; Wyle (303) 457-9953.
CONNETICUT: Arrow/Kierulff (203) 265- 774 "
Hall-Mark (203) 269-0100; Marshall (203) 265-3822;
$chweber (203) 748-7080
FLORIDA: Ft. Lauderdale:
Arrow/Klerulff (305) 429-8200; Hall-Mark (305) 971-9280:
Marshall (305) 977-4880; Schweber (305) 977-7511,
Orlando: Arrow/Kierulff (305) 725-1480, (305) 682-6923,
Hall-Mark (305) 855-4020; Marshall (305) 767-8585;
Schweber (305) 331-7555; Zeus (305) 365-3000;
Tampa: Hall-Mark (813) 530-4543;
Marshall (813) 576-1399
GEORGIA: Arrow/Kierulff (404) 449-8252;
Hall-Mark (404) 447-8000; Marshall (404) 923-5750:
Schweber (404) 449-9170
ILLINOIS: Arrow/Kierulff (312) 250-0500;
Hall-Mark (312) 860-3800; Marshall (312) 490-0155,
Newark (312) 784-5100; Schweber (312) 364-3"150
INDIANA: Indianapolis:
Hall-Mark (317) 872-8875;
IOWA: Arrow/Klerulff (319) 395-"1230;
Schweber (319) 373-1417.
KANSAS: Kansas City: Arrow/Klerulff (913) 541-9542;
Hall·Mark (913) 888-4747; Marshall (913) 492-3121,
Schweber (913) 492-2922.
MARYLAND: Arrow/Kierulfl (301) 995-6002;
Hall-Mark (301) 988-9800; Marshall (301) 840-9450:
Schweber (301) 840-5900; Zeus (301) 997-1118.
MASSACHUSETTS Arrow/Kiefulff (617) 935-5134;
Hall-Mark (617) 667-0902, Marshall (617) 658-0Hl0
Schweber (617) 275-5100, (61"/) 657-0760:
Time (617) 532-6200, Zeus (617) 863-8800
MICHIGAN: Detroit: Arrow/K,erulff (313) 971-0220;
Marshall (313) 525-5850: Newark (313) 867·06(10;
Schweber (313) 525.8100;
Grand Rapids: Arrow/KierulH (616) 24:)·0912
NEW HAMPSHIRE: Arrow.rKlcruJff (603) 668-6968:
Schweber (603) 625-2250
NEW JERSEY; Arrow/Klerulff (201) 538-0900.
(609) 596-8000; GAS Electronics (609) 964-8560;
Hall·Mark (201) 575-4415, (609) 235-1900;
Marshall (201) 882-0320, (609) 234·9100;
Schweber (201) 227-7880
NEW MEXICO: Arrow/Klerulff (505) 243-4566
NEW YORK; Long Island:
Arrow/Klerulff (516) 231 -1000, Hall-Mark (516) 737··0600,
Marshall (516) 273-2424; Schweber (516) 334-7555.
Zeus (914) 937-7400;
Rochester: Arrow/Klerulff (716) 427-0300,
Hall·Mark (716) 244-9290, Marshe!1 (716) 235-7820;
Schweber (716) 424-2222'
Syracuse: Marshall (60l) 79B-1611
NORTH CAROLINA: Arrow/Klerulff (919) 876·3132,
(919) 725-8711; Hall-Mark (919) 872·0712;
Marshall (919) 878-9882; Schweber (919) 876-0000
OHIO: Cleveland: Arro ..... fKjerulff (:<'16) 248-3990;
Hall-Mark (216) 349-4632, Marshall (216) 248-1"188;
Schwebel (216) 464-2970;
Columbus: Arrow/Kierulf! (614) 436-0928;
Hall-Mark (614) 888-3313:
Dayton: Arrow/Klerulft (513) 435-5563;
Marshall (513) S98-4480; Schweber (513) 439-1800
OKLAHOMA: Arrow/Kierulfl (918) 252-7537;
Schweber (918) 622-8003.
OREGON: Anow/Kierulff (503) 645-6455;
Marshall (503) 644-5050, Wy!fJ (503) 640-6000
PENNSYLVANIA: Arrow/Klerulff (412) 86(;-iClOO,
~clh5l;~:;~~?g; ~4R1:0~~3.tr(~~iji ~j~J890~~-70:.J7
TEXAS: Austin: Armw/Klerulff (512) 1)35-4180;
Hall-Mark (512) 258-8848; Marshall (512) 837·1991;
SChweber (512) 339-0088; Wyle (512) 834-9957;
Dallas: Arrow/Kierulff (214) 380-6464;
Hall-Mark (214) 553-4300; Marshall (214) 233·5200;
Schweber 1214) 661-5010; Wyle (214) 235-9953;
Zeus (214) 783-7010;
Houston: Arrow/Kierulff (713) 530-4700,
Hall-Mark (713) 781-6100; Marshall (713) 895-9200;
Schweber (713) 784-3600; Wyle (713) 879-9953.
UTAH: ArrowJKlerulft (801) 973-6913;
Hall-Mark (801) 972-1008; Marshall (801) 485-1551;
Wyle (801) 974-9953.
WASHINGTON: Armw/Kierulff (206) 575-4420:
Marshall (206) 747-9100; Wyle (206} 453-8300.
WISCONSIN: Arrow/Kierulff (414j 792-0150;
Hall·Mark (414) 797-7844; Marshall (414) 797-8400;
Schweber (414) 784-9020.
CANADA: Calgary: Future (403) 235-5325;
Edmonton: Future (403) 438-2858;
Montreal: Arrow Canada (514) 735-5511,
Future (514) 694-7710,
Onawa: Arrow Canada (613) 226-6903;
Future (613) 820-8313,
Quebec City: Arrow Canada (418) 687-4231;
Toronto: Arrow Canada (416) 672,,1769;
Future (416) 638-4771;
Vancouver: Future (604) 294-1166;
Winnipeg: Future (204) 339-0554.
Customer
Response Center
CANADA: Nepean, Ontario (613) 726-1970.
TOLL FREE: (800) 232-3200
l!}
TEXAS
INSTRUMENTS
OUTSIDE USA:
995-6611
- 5:00 p.m. CST)
8U
TI Worldwide
Sales Offices
ALABAMA: Huntsville: 500 Wynn Drive, Suite 514,
Huntsville, AL 35805, (205) 837·7530.
ARIZONA: Phoenix: 8825 N. 23rd Ave., Phoenix,
~~~!~~~;~~~~~t'1~~~I~'~)~4~~W York Dr.,
Coraopolis: 420 Rouser Rd., 3 Airport Office Park.
Coraopolis, PA 15108, (412) 771·8550.
PUERTO RICO: Halo Rey: Mercant/l Plaza Bldg.,
Suite 505, Hato Rey, PR 00919, (809) 753·8700.
TEXAS: Austin: P.O. Box 2909, Austin, TX 78769,
(512) 250·7655; Richardson: 1001 E. Campbell Rd.,
Richardson, TX 75080,
~~~~ S:;~S;~~:~~o:7~6~, ~?fJr~7e:'~9!y·,
AZ 85021, (6021995·1007.
San Antonio: 1000 Central Parkway South,
San Antonio, TX'78232, (512) 496·1779.
CALIFORNIA: Inine: 17891 Cartwright Rd., Irvine,
CA 92714, (714) 660-8187; Sacramento: 1900 Point
West Way, Suite 111, Sacramento, CA 95815,
UTAH: Murray: 5201 South Green SE, Suite 200,
Murray, UT 84107. (801) 266·8972.
~~~~ ~~~~~'b~;o~b'~2~W. (~~e; 2~~a:O~~e.,
VIRGINIA: Fairfax: 2750 Prosperity, Fairfax, VA
22031, (703) 849-1400.
~~~nJ:?~~~i21~i~~~.~o~~ Knox St.,
WASHINGTON:, Redmond: 5010 148th NE, Bldg B.
Suite 107, Redmond, WA 98052, (206) 881·3080.
Santa Clara: 5353 8et~ Ross Dr., Santa Clara, CA
Woodland Hili.: 21220 Erwin St., Woodland Hills,
CA 91367, (8181 704·7759.
WISCONSIN: Brookflald: 450 N. Sunny Slope,
Suite 150, Brookfield, WI 53005, (414) 785-7140.
COLORADO: Aurora: 1400 S. Potomac Ave.,
Suite 101, Aurora, CO 80012, (303) 368-8000.
CANADA: Napean: 301 Moodie Drive, Mallorn
Canter, Nepean, Ontario, Canada, K2H9C4,
(613) 726·1970. Richmond Hili: 280 Centre St. E.,
Richmond Hill L4C1B1. Ontario. Canada
(416) 884·9181; St. Laurent: Ville SI. Laurent Quebec,
9460 Trans Canada Hwy., St. Laurent, Quebec,
Canada H4S1R7, (514) 335·8392.
CONNECTICUT: Wallingford: 9 Barnes Industrial
Park Rd., Barnes Industrial Par1t, Wallingford,
CT 06492, (2031 269-0074.
FLORIDA: Ft. Lauderda'a: 2765 N.W. 62nd St.,
Ft. Lauderdale, FL 33309, (305) 973·8502;
Maitland: 2601 Maitland Center Parkway,
Maitland. FL 32751, (305) 660-4600;
~=~:: ~~1831o:.(81n3~dI7g!622b~uite 101.
GEORGIA: Norcross: 5515 Spalding Drive, Norcross,
GA 30092, (4041662·7900
~r~il~~~~: ~:~~t-:'~LH:=:(i~~) ~40~~3~5.qUin,
~~~:a~~ (~~'::l:'~;~~~ Inwood
Dr., Ft. Wayne,
Indianapolis: 2346 S. Lynhurst, Suite J·400,
Indianapolis, IN 46241, (317) 248·8555.
IOWA: Cedar Rapids: 373 Collins Rd. NE, Suite 200,
Cedar Rapids. IA 52402, (319) 395·9550.
ARGENTINA: Texas Instruments Argentina
S.A.I.C.F.: Esmeralda 130, 15th Floor, 1035 Buenos
Alras, Argentina. 1 + 394·3008.
AUSTRALIA (I: NEW ZEALAND): Texas Instruments
Australia Ltd.: 6-10 Talavera Rd., North Ryde
(Sydney), New South Wales, Australia 2113,
2 + 887-1122; 5th Floor, 418 St. Kilda Road,
Melbourne, Victoria, Australia 3004, 3 + 267-4677;
~7~ ~~!f~~hWay, Elizabeth, South Australia 5112,
AUSTRIA: Texas Instruments Gas.m.b.H.:
Industriestrabe B/16, A·2345 BrunnlGebirge,
0·7
;
~~W:I~~~, DR=t~:a~u,ra, ~s:80ro~~~~~";
261 +35044.
HONG KONG (. PEOPLES REPUBLIC OF CHtNA~
Texas Instruments Asia Ltd., 8th Floor, World
Shipping Ctr.• Harbour City, 7 'Canton Rd., Kowloon,
Hong Kong, 3 + 722·1223.
IRELAND: Texas Instruments (Ireland) Limited:
Brewery Rd., Stillorgan, County Dublin, Eire,
1 831311.
ITALY: Texas Instruments Semleonduttori Italla Spa:
Vlale Della Seienze, 1,02015 Cittaducate (Rlet!),
Italy, 746 694.1; Via Salarla KM 24 Palazzo Cosma),
Monterotondo Scalo (Rome), Ital
i~~~~~:O:~'~:~~?~M~f
11 774545j Via J. Barou/ 6, 401
355851.
JAPAN: Texas Instruments Asia Ltd.: 4F Aoyama
~g~y~~d.Bip~1~o~IU~mfj b~~:'3ra~~nh~ttt,u,
Nissho Iwai Bldg., 30 Im~ashi 3- Chorne,
Higashi·ku, Osaka, Japan 541, 06·204·1881; Nagoya
Branch, 7F Dalnl Toyota West Bldg., 1()'27. Maiek!
4·Chome, Nakamur.ku Nagoya, Japan
450, 52-583-6691.
KOREA: Texas Instruments Supply Co.: 3rd Floor,
~gsng~o~~?~o~~~~'!".i~f.g&~angnam.ku,
MEXICO: Texas Instruments de Mexico SA: Mexico
City, AV Reforma No. 450 - 10th Floor, Mexico,
D.F., 06600, 5+514-3003.
MIDDLE EAST: Texas Instruments: No. 13, 1st Floor
~:ri:aB:'tra?~~~~~1~ ~~~ :7~}~~~~'
NETHERLANDS: Texas Instruments HC)lJand B.V.,
MARYLAND: Billimore: 1 Rutherford PI.,
7133 Rutherford Rd., Baltimore, MD 21207,
(301) 944-8600.
2236-846210.
MASSACHUSETTS: Waltham: 504 Totten Pond Rd.,
1130 Brussels, Belgium, 2/720.80.00.
~~:=~~r,eo~ol~~t~Uor:~~~ (~org~~:
~~~~~! ~~~I~tr80~~,I(~;~7~~~~. Mile Rd.,
BRAZIL: Texas Instruments Eleetronieos do Brasil
Ltda.: Rua Paes Leme, 524·7 Andar Pinheiros, 05424
Sao Paulo, Brazil, 0815-6166.
PHILIPPINES: Texas Instruments Asia Ltd.: 14th
MINNESOTA: Eden Pl'llirle: 11000 W. 78th St.,
Eden Prairla, MN 55344 (612) 828-9300.
DENMARK: Texas Instruments AlS, MairelundveJ
46E, OK·2730 Herlav, Denmark, 2 . 91 7400.
PORTUGAL: Texas Instruments Equlpamento
~i\~~~~~::"~~~1~3=~ard
FINLAND: Texas Instruments Finland OY;
Teollisuuskatu 19000511 Helsinki 51, Finland, (90)
701·3133.
Waltham, MA 02154, (6171895-9100.
Pkwy., Kansas
St. Louis: 11816
Drive, St. Louis,
MO 63146, (314) 569-7800.
~orman
NEW JERSEV: Iselin: 4B5E U.S. Route 1 South,
Parkway Towers, Iselin, NJ 08830 (201) 750·1050
NEW MEXICO: Albuquerque: 2820-0 Broadbent Pkwy
NE, Albuquerque, NM 87107, (505) 345·2555.
::r:J!!~~:l:~,r(~~~rk~::i9~ollamer
~~~;~~MdeTn~~:~ ~~~~i::~:s,~:R~:IS~U~ ~u~~e,
~6.97.12;
(71833·
PittSford. NY 14534, (716) 385-6770;
:~,re~~p(;I:~)3N3-~~~ Ad., Poughkeepsie,
Noilly Paradls-146 Rue Paradis, 13006 Marseille,
(91) 37·25-30.
~?J~2~:~~:(G9)e~1~:~: ~~~I::eug~:ag~~~e,
~~1~rtro~fo-;:e,~~f)n::~.,~~1::g~~~;~~red~~I~~~~::
MALAYSIA,
uments Asia ltd.: 12 Lorang
Kolam Ayer Induetrlal Estate,
747·2255.
SWEDEN: Texas Instruments Intemational Trade
Corporation (Sverigefillalen): Box 39103, 10054
Stockholm, Sweden, 8 - 235480.
SWITZERLAND: Texas Instruments, Inc., Reidstrasse
6, CH·8953 Dietikon (Zuerich) Switzerland,
1·7402220.
TAIWAN: Texas Instruments SuPPI~ Co.: Room 903,
~~rw~~ ~~~~I~edol6h~~~~2K~*5~1_::1.Taipe!,
NORTH CAROLINA: Charlotte: 8 Woodlawn Green,
Woodlawn Rd., Charlotte, NC 28210, (70~ 527·0930;
~~eJ,g~~~lg~:m5~ Blvd., Suite 1 ,AaJelgh.
OREGON: Buverton: 6700 SW 105th St., Suite 110,
Beaverton, OR 97005, (503) 643-6758.
+ tNDtA, tNDONESIA,
Lyon Sales Offl
3, Quai Kleber, 67055 Strasbourg Cedex,
OHIO: Beachwood: 23408 Commerce Park Rd.,
Beachwood, OH 44122, (216) 464-6100;
g~~~3~~(§f~i~~~7i124 Linden Ave., Dayton,
G~~~~~~~ (~~~ra'6aL~aaia~~:7~nf4.r~~~~,
2·948-1003.
~r~~~Jinre~~~8~~~c~el~P 67 8·10 Ave~ue
3)
PB106.
~:!ti~:te~~~~i:,d~hln~:rn:~g;~xr'
FRANCE: Texas Instruments France: Headquarters
and Prod. Plant, BP 05, 06270 Villeneuve-Loubet,
Dr., East
endicott: 112 Nanticoke Ave., P.O. Box 618, Endicott,
NY 13760, {60n 754·3900; Melville: 1 Huntington
~~~1~',1(5f6)1~~~;Pp?t.~:i~'1 MC:~~~~St.,
~u9d.g~~t~=a~~U~'~~M:~W. CB Amsterdam,
UNITED KINGDOM: Texas Instruments Limited:
..tf
TEXAS
INSTRUMENTS
~7=nstas:m:~~~~S~~~Ir:~o;';PC:dN~~
Stockport, SK4 2RT. England, 6' +442-7162 .
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~
TEXAS
INSTRUMENTS
Printed in U.S.A.
1
SCTD001A
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