1988_WSI_High_Performance_CMOS_Products 1988 WSI High Performance CMOS Products
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HIGH PERFORMANCE
CMOS PRODUCTS
DATA BOOK
1988
1988
WI; ;
WAFERSCALE INTEGRATION, INC
WaferScale Integration, Inc.
High Performance
CMOS Products
Databook
1988
Copyright © 1988 WaferScale Integration, Inc.
(All rights reserved.)
47280 Kato Road, Fremont, California 94538
415-656-5400 Facsimile: 415-657-8495 Telex: 289255
Printed in U.S.A.
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SHATTERING BARRIERS THAT LIMIT GROWTH
In its short history, WaferScale Integration, Inc. (WSI) has made commonplace the breaking of traditional
barriers that limit high-performance system evolution. Company "breakthroughs":
• First company to patent a self-aligned split-gate single transistor EPROM cell and place it in high volume
production.
• First company to produce a 55 ns 8K x 8 CMOS EPROM.
• First company to produce a 43 MHz 4-bit CMOS bit slice processor.
• First company to produce monolithic 16-bit and 32-bit CMOS bit slice processors, both as stand-alone
products and as cell library macros.
• First company to produce a 128K CMOS re-programmable non-volatile memory with bipolar PROM pinouts.
• First company to produce a 30 ns 16 x 16 CMOS Multiplier Accumulator.
• First company to produce a 55 ns x 16 (wordwide) CMOS EPROM.
• First company to produce 55 ns 32K x 8 CMOS EPROMs.
• First company to combine high-performance EPROM, SRAM and logic all on the same circuit.
• First company to have 33 re-programmable CMOS EPROM products compliant to MIL-STD-883C.
• First company to produce user-configurable high-performance CMOS re-programmable board-replacement
system controllers.
• First company to produce a family of 16K to 64K CMOS RPROMs™ with sub-35 ns access time.
• First company to produce address mappable memory circuits that combine EPROM, SRAM and logic.
As WSI moves into faster sub-micron CMOS technologies in 1988 and continues to develop new programmable solutions for higher performance system markets, additional barriers will continue to be broken in
our drive for leadership in high-performance next-generation programmable semiconductor products that
integrate both memory and logic. WSI thus enables its customers to achieve faster market entry, higher
performance systems and more easily producible end products.
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WAFERSCALE INTEGRA110N, INC
GENERAL INFORMATION
1
SECTION INDEX
GENERAL INFORMATION
Table of Contents ............................................................................ 1-1
Company Profile ............................................................................ 1-3
WSI Technology & Electronics Article ............................................................ 1-7
Product Summary ........................................................................... 1-11
Numerical Product Listing .................................................................... 1-15
Product Cross Reference ..................................................................... 1-19
Ordering Information ........................................................................ 1-21
For additional information,
call SOO-TEAM-WSI (SOO-S32-6974).
In California, call 415-656-5400.
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TABLE OF CONTENTS
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WAFERSCALE INTEGRATION, INC.
General Information
Table of Contents ........................................................................ 1-1
Company Profile ......................................................................... 1-3
WSI Technology & Electronics Article ........................................................ 1-7
Product Summary ....................................................................... 1-11
Numerical Product Listing ................................................................ 1-15
Product Cross Reference ................................................................. 1-19
Ordering Information ..................................................................... 1-21
Programmable Memory Products
PROM Memory:
WS57C191/291
WS57C191 B/291 B
WS57C45
WS57C43B
WS57C49
WS57C49B
2K
2K
2K
4K
8K
8K
x
x
x
x
x
x
8
8
8
8
8
8
CMOS PROM ................................................. 2-1
CMOS PROM ................................................. 2-5
Registered CMOS PROM ...................................... 2-9
CMOS PROM ................................................ 2-13
CMOS PROM ................................................ 2-17
CMOS PROM ................................................ 2-21
Re-Programmable Memory Products
RPROM Memory:
WS57C191/291
WS57C191 B/291 B
WS57C45
WS57C43
WS57C43B
WS57C49
WS57C49B
WS57C51
WS57C51B
2K x 8 CMOS RPROM ............................................... 3-1
2K x 8 CMOS RPROM ............................................... 3-5
2K x 8 Registered CMOS RPROM ...................................... 3-9
4K x 8 CMOS RPROM ............................................... 3-13
4K x 8 CMOS RPROM ............................................... 3-17
8K x 8 CMOS RPROM .............................................. 3-21
8K x 8 CMOS RPROM .............................................. 3-25
16K x 8 CMOS RPROM ............................................. 3-29
16K x 8 CMOS RPROM ............................................. 3-33
EPROM Memory (x8):
WS27C64F
WS57C64F
WS27C128F
WS57C128F
WS27C256F
WS57C256F (-55)
WS57C256F (-35)
WS27C256L
WS27C256F
WS27C512F
WS27C010L
WS57C010F
8K x 8 CMOS EPROM (Mil) .......................................... 3-37
8K x 8 CMOS EPROM ............................................... 3-41
16K x 8 CMOS EPROM (Mil) ......................................... 3-45
16K x 8 CMOS EPROM .............................................. 3-49
32K x 8 CMOS EPROM (Mil) ......................................... 3-53
32K x 8 CMOS EPROM ............................................. 3-57
32K x 8 CMOS EPROM .............................................. 3-61
32K x 8 CMOS EPROM ............................................. 3-65
32K x 8 CMOS EPROM ............................................. 3-69
64K x 8 CMOS EPROM .............................................. 3-73
128K x 8 CMOS EPROM ............................................. 3-77
128K x 8 CMOS EPROM ............................................. 3-83
1-1
D
Table of Contents
EPROM Memory (x16):
WS57C65
4K x 16 CMOS EPROM .............................................. 3-87
4K x 16 Muxed CMOS EPROM ........................................ 3-91
WS57C66
16K x 16 CMOS EPROM ............................................. 3-97
WS57C257
64K x 16 CMOS EPROM ............................................ 3-101
WS57C21OF
Mappable Memory Products:
WSMAP162/WSMAP161 MAp™ Memory .................................................... 3-105
WSMAP168 MAp™ Memory .............................................................. 3-115
CMOS Bit Slice Products
WS5901
WS59016
WS59032
WS5910AlB
WS59510
WS59520/521
WS59820
4-Bit CMOS Bit Slice Processor ......................................... 4-1
16-Bit CMOS Bit Slice Processor ........................................ 4-9
32-Bit CMOS Bit Slice Processor ....................................... 4-21
CMOS Microprogram Controller ........................................ 4-33
16 x 16 CMOS Multiplier Accumulator .................................. 4-43
Multilevel CMOS Pipeline Register ...................................... 4-51
Bi-Directional CMOS Bus Interface Register .............................. 4-55
Military Products ........................................................................... 5-1
The Shortest Path From System Concept to Market: WSI ASIC .................................... 6-1
User-Configurable Products ................................................................ 6-1
Microprogrammable Controller (PAC"") ....................................................... 6-2
Stand-Alone Microsequencer (SAMTM) ........................................................ 6-8
Cell-Based Custom Design Capability ....................................................... 6-11
Quality and Reliability ....................................................................... 7-1
Packaging ................................................................................. 8-1
Programmers/Programming
WSI Programming Algorithms .............................................................. 9-1
WSI MagicPro™ Engineering Programmer .................................................... 9-5
Data I/O Programming Support ............................................................. 9-7
Application Notes
001 EPROMs for Modern Times .......................................................... 10-1
002 Introduction to the WSI Family of Mappable Memory Products .............................. 10-5
Sales Representatives and Distributors . ....................................................... 11-1
1-2
iFEE
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COMPANY PROFILE
WAFERSCALE INTEGRA110N, INC.
INTRODUCTION
WaferScale Integration, Inc. (WSI) has achieved marked increases in sales of its programmable CMOS memory, logic
and semicustom products. These increased sales have resulted in a solid financial position including profitability.
WSI is leveraging its proprietary CMOS technology and circuit architectures with strategic alliances involved in
technology, manufacturing and distribution. This partnership structure has resulted in WSl's rapid emergence as the
leader in high-performance next-generation user-programmable semiconductor products integrating both memory
and logic.
WSI serves its customers with the industry's fastest family of non-volatile CMOS EPROM and RPROM™ memory
circuits, high-speed CMOS bit-slice processors and peripherals and programmable board-replacement cell-based
custom circuits. WSI continues to build on its unique technology by bringing to market fast new user-programmable
controllers and specialized memory products that combine high-performance EPROM, SRAM and logic on one circuit. WSI supports these new products with a complete system development environment including software assemblers,
simulators and utilities as well as the MagicPro™ programmer. These development tools are used by customer
design engineers during system development. Derived customer benefits from using the new user-programmable
products include faster time to market, higher levels of integration resulting in smaller, more efficient products and
higher system performance.
THE COMPANY
WSI was founded in August, 1983, to develop integrated circuit technologies and products tailored specifically to meet
the needs of high-performance systems developers. The company is headquartered in a 66,000 square foot facility
in Fremont, California and employs 100 people.
The company's leveraging of its partnerships with Sharp Corporation, GE Solid State, Altera Corporation, Intergraph
Corporation, and Kyocera Corporation enables WSI to invest its capital into advancing its technology, serving its
customers, and realigning products to match market shifts.
Sharp Corporation and GE Solid State have invested in WSI through equity positions, and both companies hold WSI
technology licenses. Altera Corporation and Intergraph Corporation are two additional strategic alliances involving
either equity and/or technology. The Kyocera alliance involves equity and distribution of WSI product in Japan.
In its first round of financing in February, 1984, the company secured $16.1 million in equity, equipment loans, leaselines,
and facilities leasehold improvements. Investments were received from private sources, venture capital groups, and
corporate investment funds.
After achieving significant milestones in its first year of operation, the company secured its second round of equity
financing in October, 1984, for $8.5 million. WSI completed its third round financing in January, 1986 raising an additional $13 million in equity and licensing of its CMOS and EPROM technology. All of WSl's previous institutional investors
participated in the third round.
A fourth round of finanCing with Kyocera Corporation as an added investor has been completed, exceeding $8 million.
This round brings the company's total financing to over $30 million. Corporate investors cornerstoned and contributed
over 60% of the fourth round.
MARKETING STRATEGY
Today's rapidly expanding systems markets demand semiconductor products that provide exceptionally high speed,
high reliability, high levels of integration, low power, a high electrostatic discharge protection, low to moderate cost,
and in the case of semicustom circuits, the ability to tailor or program the product to achieve unique customer defined
functions.
1-3
1
Company Profile
WSI focuses on high-performance markets that include telecommunications, minicomputers, local area networking,
digital signal processing, array processing, high resolution color graphics, and military avionics and communications.
The company's products are used where system designers are pushing the limits of system performance. These highspeed requirements often involve real time data manipulation and control.
Major market involvement of WSI's products presently include 55% office automation, 25% telecommunication, 15%
military, and 5% other. Marketing direction has been established to balance office automation, telecommunication,
and military to roughly 30% each by 1990.
To fulfill the needs of these markets, WSI has focused its attention on customer service. The company's productdevelopment teams rely heavily on first-hand input from its customer base regarding new products. WSI provides
extensive technical information to customers in the form of printed product data, application notes, and personal design
assistance. WSI is supplying an engineering programmer (dubbed "MagicPro" for Memory ~nd loGIC PROgrammer)
which will enable customer engineers to incorporate new WSI products into their designs without having to wait until
the algorithms are commercially published for production use.
WSI has a CBIC (Cell-Based-Integrated-Circuit) program through which customers can combine a variety of proven
macro-cell functions and produce a unique high-performance programmable integrated circuit tailored to exact customer
specifications.
SALES NETWORK
WSI's products are sold worldwide through a sales network that includes a combination of regional and direct sales
managers, manufacturers' representative companies, and component distributors.
WSI has direct sales offices in Boston, MA; Huntsville, AL; Philadelphia, PA; Los Angeles and Fremont, CA; and Chicago,
IL. Over 25 manufacturers' representative companies sell WSI products to major accounts on a nationwide basis.
WSl's U.S. distributors include Time Electronics, Wyle Laboratories, Pioneer Technologies, and Pioneer Standard.
WSI has expanded its sales coverage in Europe and Japan. The company's European sales representatives include
Tekelec Airtronic GmbH (Germany), Micro Call Ltd (England), REA (France), Silverstar (Italy), Traco AB (Sweden),
Bacher GmbH (Austria, Switzerland), OY Comdax AB (Finland), OTE AlS (Norway), Distributoren Interelko, AlS
(Denmark), Unitronics, S.A. (Spain), Inelco (Belgium and Luxembourg), Components & Systems Electronics B.V.
(Holland), and Vectronics (Israel). In the Orient, Kyocera Corporation recently has been named as a WSI sales representative for Japan along with Nippon Imex Corporation (Japan), Components Agent Ltd (Hong Kong), Sertec International, Inc. (Taiwan), and Eastern Electronics, Inc. (Korea).
MANUFACTURING STRATEGY
A key ingredient for success in leading-edge semiconductors is a world-class fabrication facility that ensures high
volume capacity and prompt delivery of highly reliable and high yielding VLSI circuits. To this end, WSI has licensed
its proprietary CMOS logic and EPROM process to Sharp Corporation of Osaka, Japan and GE Solid State in
Somerville, NJ.
WSI's semicustom and standard products are manufactured at Sharp's highly automated manufacturing facility where
it produces 5-inch wafers with 1.2 micron CMOS VLSI circuits in a Class 1 clean room environment. The Sharp facility
employs the most advanced manufacturing equipment available including ion implantation, reactive ion etch, and
wafer stepper lithographic systems.
The WSI-GE Solid State alliance provides WSI with a state-side second source. The GE Solid State Class 10 facility
in Findley, Ohio provides 1.0 micron CMOS circuits on 5-inch wafers, and includes wafer stepper lithography and
dry etch capability. As a self-contained unit, wafer fabrication, assembly, and test can all be performed at this facility.
The benefits derived from this WSI multi-fab strategy include product manufactured with very high quality, high wafer
yields which enable low customer prices, and on-time delivery to meet demanding customer schedules ... all at low
fixed cost to WSI.
1-4
Company Profile
PRODUCTS
WSI is the innovative leader in the high-speed EPROM arena. WSI began shipping the world's first CMOS 8K x 8
RPROM™ in the first quarter of 1986. RPROMs (UV erasable re-programmable PROMs) provide bipolar PROM pinout and matching speed as well as CMOS low-power operation.
In mid-1987, WSI introduced the world's fastest pair of 256K CMOS EPROMs using its newly patented, self-aligned
split gate EPROM technology. These EPROMs feature access times of just 55 ns and provide one- and two-chip
program-store solutions for 16- and 32-bit MPU and OSP applications.
In addition to producing the world's fastest family of CMOS EPROMs, WSI supplies very high-speed CMOS bit-slice
processors and peripheral circuits that operate faster than bipolar products while using only a small fraction of the power.
WSl's ability to combine EPROM, SRAM, and complex system logic functions on a single high-performance integrated
circuit is unique among semiconductor companies. Examples of this capability are seen in the Microprogrammable
Controller (PAC™) family, the MAp™ family of mappable memory products and the Stand-Alone Microsequencer
(SAMTM) series. This same capability is used to develop powerful cell-based semicustom circuits that are unique to
customer requirements. Are-programmable semicustom circuit provides flexibility in software, system configuration,
and commonality of use among many customer projects.
The WSI CMOS macro-block cell library provides VLSI EPROM and SRAM memory and logic cells. When coupled
with WSl's advanced CAD system, it enables WSI to build specially designed integrated circuits for its customers.
The use of pre-characterized and pre-proven macro cells greatly insures the early success of each project. By using
these powerful LSI functions, in addition to common logic elements, the cell library enables programmable subsystems
or even complete system designs to be integrated on a single piece of silicon.
The macro-block CMOS cell library contains a family of high-performance bit-slice processor cells (from 4-bit to 32-bit)
with better than bipolar LSI performance. Also included are bit-slice processor peripheral cells including microprogram
controllers, variable pipelines, FIFOs, multipliers, bus registers, and register files. The library also contains high-density,
very fast CMOS EPROM memory cell arrays, high-performance cell compilers for fast static RAM arrays, ROM arrays,
and PLA cell arrays. High-speed random logic cells, which are functionally compatible with the popular 7400/4000
series, are also included in the library.
Many of the macro-cells developed for the cell library are excellent as stand-alone standard products. By providing
these high-performance standard products, WSI can assist its customers in achieving enhanced system performance
either in discrete design configurations or as design aids in advance of a full semicustom solution.
QUALITY AND RELIABILITY
WSI has designed, developed and implemented a Quality and Reliability System whose mission is to continually produce Commercial and Military products that meet, and most often exceed, the customers' requirements.
WSI is deeply committed to product excellence. This begins with proper management attitude and direction and through
this focus the Quality and Reliability Program is able to operate efficiently. As a result, product quality becomes part
of each employee's responsibilities.
Quality and Reliability begin with the proper product and process designs and is supported by material and process
controls. Examples are products manufactured on an epitaxial silicon layer to reduce latch-up sensitivity, all pins are
designed to withstand >2,000 volts ESOS, numerous ground taps are used which increases product noise immunity,
metal traces are designed to carry a current density of >2.0 x 105 ampslcm 2 , top passivation extends over into the
scribe lane to seal the die edges, data retention is performed 100% on re-programmable products (TA = + 200°C,
T = 48 hours), automated die attach and bonding is used extensively, wafers are fabricated in a ~Class 10 clean
room, raw materials, chemicals and gases are inspected before use, and statistical controls are used to keep the
process on course.
Product and process introductions or changes are routinely evaluated for worthiness. Life Tests are conducted at
higher than typical stress levels (TA = +150°C, Vee = +6.5V) and even at these stress levels, WSI products have
demonstrated low failure rates (see the Quality and Reliability section in this databook).
1-5
0
Company Profile
WSI is active in Military programs and its Quality and Reliability System supports Compliant Non-Jan products. WSI
also supports DESC's (Defense Electronics Supply Center) Standardized Military Drawings (SMD) program. As of
February, 1988, WSI is on three SMDs, two are pending and more are in process. See the Military section in this
databook.
For additional information, call 800.:rEAM-WSI (800-832-6974). In California, call 415-656-5400.
LIFE SUPPORT POLICY:
WaferScale Integration, Inc. (WSI) products are not authorized for use as critical components in life support systems or devices without the express
written approval of the President of WSI. As used herein:
A) Life support devices or systems are devices or systems which 1) are intended for surgical implant into the body, or 2) support or sustain life
and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury or death to the user,
B) A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system or to affect its safety or effectiveness.
Information furnished herein by WaferScale Integration, Inc. (WSI) is believed to be accurate and reliable. However, no responsibility is assumed
for its use. WSI makes no representation that the use of its products or the interconnection of its circuits, as described herein, will not infringe
on existing patent rights. No patent liability shall be incurred by WSI for use of the circuits or devices described herein. WSI does not assume
any responsibility for use of any circuitry described, no circuit patent rights or licenses are granted or implied, and WSI reserves the right without
commitment, at any time without notice, to change said circuitry or specifications. The performance characteristics listed in this book result from
specific tests, correlated testing, guard banding, design and other practices common to the industry. Information contained herein supersedes
previously published specifications. Contact your WSI sales representative for specific testing details or latest information.
Products in this book may be covered by one or more of the following patents. Additional patents are pending.
USA: 4,328,565; 4,361,847; 4,409,723; 4,639,893; 4,649,520
West Germany: 3,103,160
Japan: 1,279,100
England: 2,073,484; 2,073,487
The following are trademarks of WaferScale Integration, Inc.: MagicPro'", RPROM™, PMD™, MAp™, PACASM™, PACSIM™, WSI T. , PAC",
WISPER™
PAL is a registered trademark of Monolithic Memories, Inc.
IBM is a trademark of International Business Machines Corporation.
SAM and SAM+PLUS are trademarks of Altera Corporation.
1·6
WAFERSCALE INTEGRA710N, INC.
WSICMOSTECHNOLOGY
D
Each generation of systems involved with data processing, digital communications, and real-time data analysis
and control historically require faster and more efficient system elements to accomplish greater productivity.
Issues of performance, reliability, integration, power and cost must be successfully addressed to insure
the successful development of highly competitive end products. WSI's CMOS technology forms the foundation on which successful, high-performance next-generation systems may be realized.
The basic WSI CMOS process is a 1.2 micron N-well epi technology with double poly and single metal.
This process enables the combining of non-volatile memory, static random access memory and logic functions all on the same low power circuit.
WSI's core EPROM technology begins with its patented self-aligned single transistor split-gate EPROM
cell (Patent Number #4,639,893). This advancement beyond the traditional "stacked gate" EPROM cell
provides much higher read current at comparable cell size. Proprietary EPROM array design enhancements
such as clocked differential sensing, address-transition detection and the use of low resistance tungsten
silicide in the second poly layer result in very high-speed memory products. Manufacturability is also improved as fewer EPROM cells are needed to complete a fast memory array, thus more conservative
photolithography may be used.
WSI's use of epi wafers and design innovations result in products that exhibit immunity to latch-Up and
provide ESD protection far in excess of that specified by MIL-STD-883C.
The WSI EPROM technology has proliferated into families of high-performance EPROMs, bipolar PROM
replacement products, user-configurable system products and cell-based custom capabilities described
in this databook. When the high-speed split-gate EPROM technology is combined with high-performance
cell-based logic functions, new user-configurable CMOS circuits such as the 20 MHz Microprogrammable
Controller (PAC™) series are realized. An additional family of 40 ns mappable (MAp™) memory products
combine EPROM, SRAM and logic on a single chip. WSI's fast CMOS logic has yielded a market leading
30 ns 16 x 16 CMOS Multiplier Accumulator and a 33 MHz 32-bit CMOS bit slice processor ... both the
fastest in their class.
WSl's ability to rapidly combine any of these completed or modified macro memory or logic functions into
a custom high-performance cell-based board-replacement circuit for special customer applications makes
WSI unique among semiconductor companies.
1-7
or density? DenSpeed
sity or speed? Thanks
WAFERSCALE'S 256·K
EPROM RUNS SUPERFAST
to WaferScale Integration
Inc., systems designers no
longer must compromise.
The Fremont, Calif., company has just unleashed a refined technology to whip up a scaled version of
pair of high-speed, 256- its proprietary split-gate EPROM cell. Just 6.5 fLm
Kbit ultraviolet-erasable on a side, the latest split-gate incarnation is
CMOS programmable read- roughly half the size of its predecessor. There's
only memories. With 50- to 55-ns access times, more to the new cell than just size, but the
they are the fastest nonvolatile memories on the company won't go any further than saying that
market at 256 Kbits and beyond-at least two to it adopted tungsten silicide.
three times quicker than comparably sized
The main problem with the traditonal stackedPROMS, and coming within range, at twice the gate cell, notes Boaz Eitan, manager of the PROM
density, of the largest commercial bipolar PROM program, is that it forces a tradeoff between the
[Electronics, Feb. 10, 1986, p.35]. And active necessarily high read current and efficient propower dissipation is a comfortable 325 milliwatts, grammability. "In traditional implementations, chip
just half that of its closest bipolar rival, sinking designers have had to make a choice," he says. "If
to 75 mW on standby.
they wanted speed, they had to implement a PROM
With their combination of speed and density, cell with three to four transistors, separating the
the word-wide 16-K-by-16-bit WS57C257 and byte- read, write, and select functions. If they wanted
wide 32-K-by-8-bit WS57C256F are tailored to density, all three functions could be incorporated
one- and two-chip program storage for 16- and into a single-stacked PROM cell, but only at consid32-bit microprocessors and digital signal process- erable sacrifice in speed."
ing. Conventionally, anywhere from 4 to 16 nonThe heart of the trouble lies in rapidly sensing
volatile memories are needed. Current plans call the word- and bit-line voltages after address defor the byte-wide memory to hit the streets in coding. "The bit-line capacitance plays a big part
July in standard 28-pin ceramic dual in-line pack- in the equation," explains Syed Ali, manager of
ages and 32-pin ceramic leadless chip carriers. memory design. "If the capacitance remains
The word-wide part will follow sometime in the fixed, a higher read current is needed to achieve
third quarter, in 40-pin Cerdips and 44-lead ce- greater speed. However, if the capacitance can
ramic leadless chip carriers. Both are priced at be lowered, the speed can be boosted without
$94 per unit in l00-unit sample quantities.
increasing the read current."
To achieve this unprecedented combination of
The split-gate structure weds the best of the
speed and density, engineers at WaferScale Inte- multiple-transistor and single-stacked cell apgration refined the company's process technol- proaches, requiring none of the compromises inogy and fine-tuned the circuit design. On the herent in either. It consists of a MOS transistor
process side, a slimmed-down, second-generation linked in series with a floating-gate transistor
1.2-J-Lm CMOS process, a scaled version of the that has been merged into a composite device
company's patented split-gate EPROM cell, and (see fig. 1). In this design, says Eitan, the second
tungsten silicide word lines were the keys to polysilicon layer acts as the control gate and
success. On the circuit-design side, clocked dif- directly covers part of the channel area. "This
ferential sensing and a novel precharge tech- eliminates drain turn-on and source-drain
nique, a special two-step ac signal scheme, and punchthrough, which adversely affects the stanaddress-transition detection were
the key developments. "These two
STACKED GATE
SPLIT GATE
devices disprove the traditional belief that you could have speed or
size, but not both, in your micro"
control store," says Jerry Banks,
l&mrO L
marketing manager for standard
POLYSILICON 1 11~~~~rING
POLYSILICON 1
products. "These large-architecture
CMOS EPROMs are ideally suited for
modems, real-time control, guidance systems, digital signal processing, and other real-time or complex processing applications."
lal
Ibl
WaferScale Integration first
boiled down its CMOS process-from 1, SPLITS. Unlike the stacked·gate transistor (a), the split-gate transistor (b) has a second poly
1.5 to 1.2 J-Lm-and then used the control gate that partly covers the channel, preventing drain turn·on and source-drain punchthrough.
....tM". . '.
1-8
I
2. DELAY KILLER. Tungsten-silicide deposition helps WaferScale's 256-Kbit EPROM achieve ils 45-ns access lime.
dard stacked-gate EPROM cell." As a result, bitline read currents in excess of 150 f.LA can be
achieved, compared with the 50 f.LA typical of
conventional stacked-gate cells, giving the speed
of the multiple-transistor EPROM cell without its
attendant die size.
The memory array (see fig. 2) is divided into
two planes, each consisting of two blocks separated by a mid-word-line repeater. Tungsten silicide is deposited over the second polysilicon layer to reduce word-line RC delays, further improving access time. With a resistance of only 3 n
per square .um, tungsten silicide helps reduce the
delay to 60% of that incurred with traditional
aluminum metallization. The 512 columns of the
array are divided into blocks of eight columns,
each block with its own dedicated source lines.
The higher bit-line voltage and read current
established by the split-gate structure allow the
company to employ a differential-sensing scheme
that does not require a separate bit line, thus
eliminating bit-line capacitance. In this scheme,
the sense amplifier is designed to work in conjunction with a trip inverter_ During precharge,
the outputs of the differential amplifier and the
inverter are precharged to the inverter trip
point, enabling the inverter to move rapidly in
either direction after a signal has been detected.
The relative difference in the rate of discharge
between the bit line and a column of reference
cells provides just enough differential voltage
for high-speed sensing.
To ensure that signal levels are high enough
for sensing-a key consideration in all memories,
as density increases and interconnects get longer-a two-step ac signal-development scheme has
been incorporated into the circuits. In the first
step of the proprietary approach, a small ac sig-
nal is generated by using a capacitor-imbalancing technique. This 1oo-mV signal is rapidly read
out by a differential sense amplifier. In the second step, the on-chip circuitry converts this signal to a 300-mv dc signal that is used to increase
programmed cell margins by as much as 25%.
As a result, says Eitan, the design senses bitline voltages more than five times faster than
previous devices. The scheme also makes for
fast programming_ Typically, it takes only 0.1 ms
to program a byte, compared with 1 ms for older
technologies.
Address-transition detection also contributes
to the improved access times. Normally associated with static random-access memories, it helps
precharge the bit lines and to equalize the gain
of the critical sense amplifiers. When an address
transition is detected, an enable pulse is generated that precharges the bit-lines and critical
sense-amplifier nodes_ This eliminates the setup
time normally encountered in PROMs. To further
reduce the precharge time, the bit-line voltage
swing is kept within narrow limits. More time is
saved by performing the address decoding in
parallel with the bit-line precharge, then ending
them simultaneously.
To keep power dissipation down, only 25% of
the cells in the array have access to the supply
voltage during a read_ This dramatically decreases the supply current to no more than 40
mA at 20 MHz, about half that of other designs_
WaferScale Integration is also using its highspeed process for a 64-Kbit PROM, the 8-K-by-8-bit
WS57C49B, a direct pin-for-pin replacement for a
bipolar PROM (called a reprogrammable ROM, or
RPROM)_ At 35 ns it matches most high-speed
CMOS SRAMs in access time. Another device for
which it is using the high-speed process is a pinfor-pin CMOS relacement for the Am27C51, a 128Kbit bipolar PROM from Advanced Micro Devices
Inc., Sunnyvale, Calif. The WS57C51 is a 16-K-by8-bit RPROM with an access time of only 55 ns
and a chip area of only 32,000 mils2, 60% smaller
than the AMD device.
The company is now working on its next-generation CMOS PROM process, which at 1.0 f.Lm will
enable it to build 64-Kbit memories that access in
only 25 ns and 128-Kbit and 256-Kbit devices that
access in 35 ns. The same process will also allow
WaferScale Integration to extend its speed challenge up into the megabit range. "There is nothing in our process that I can see that will preverrt
us from building 1-Mbit EPROMs with access times
as low as 55 ns," Ali says. -Bernard C. Cole
D
TECHNOLOGY TO WATCH is a regular feature of
Electronics that provides readers with exclu-
sive, in-depth reports on important technical
innovations from companies around the
world. It covers significant technology, processes, and developments incorporated in major
new products.
Reprinted from ELECTRONICS, July 9, 1997, oopyright 1987 by McGraw-Hili, Inc. with all rights reserved.
1-9
1-10
HIGH-PERFORMANCE
CMOS PRODUCT SUMMARY
WAFERSCALE INTEGRA nON, INC.
PART NUMBER
DESCRIPTION
SPEED
PACKAGE
D
One-Time Programmable (OTP) CMOS PROMs
WS57C191
2K x 8 CMOS PROM
45/55 ns
24 PDIP
WS57C1918
2K x 8 CMOS PROM
35/45 ns
24 PDIP
WS57C291
2K x 8 CMOS PROM
45/55 ns
24 PDIP
WS57C2918
2K x 8 CMOS PROM
35/45 ns
24 PDIP
WS57C45
2K x 8 Registered CMOS PROM
20/25/35 ns
24 PDIP
24 CERDIP
WS57C438
4K x 8 CMOS PROM
35/45 ns
24 PDIP
WS57C49
8K x 8 CMOS PROM
55/70 ns
24 PDIP
WS57C498
8K x 8 CMOS PROM
35/45 ns
24 PDIP
Re-Programmable CMOS PROMs (RPROMs)
WS57C191
2K x 8 CMOS RPROM™(1)
45/55 ns
24 CERDIP
28 CLLCC
WS57C1918
2K x 8 CMOS RPROM™(1)
35/45 ns
24 CERDIP
28 CLLCC
WS57C291
2K x 8 CMOS RPROM™(1)
45/55 ns
24 CERDIP
28 CLLCC
WS57C2918
2K x 8 CMOS RPROM™(1)
35/45 ns
24 CERDIP
28 CLLCC
WS57C45
2K x 8 CMOS Registered RPROM™(1)
20/25/35 ns
24 Flatpack
24 CERDIP
WS57C43
4K x 8 CMOS RPROM™(1)
55/70 ns
24 CERDIP
28 CLLCC
WS57C438
4K x 8 CMOS RPROM™(1)
35/45/55 ns
24 CERDIP
28 CLLCC
WS57C49
8K x 8 CMOS RPROM™(1)
55/70 ns
24 CERDIP
28 CLLCC
WS57C498
8K x 8 CMOS RPROM™(1)
35/45/55 ns
24 CERDIP
28 CLLCC
WS57C51
16K x 8 CMOS RPROM™(1)
70 ns
28 CERDIP
WS57C518
16K x 8 CMOS RPROM™(1)
40/45/55/70 ns
28 CERDIP
32 CLLCC
High-Speed Byte-Wide CMOS EPROMs
WS57C64F
8K x 8 CMOS High Speed EPROM
55/70 ns
28 CERDIP
32 CLLCC
WS57C128F
16K x 8 CMOS High Speed EPROM
55/70 ns
28 CERDIP
32 CLLCC
WS57C256F
32K x 8 CMOS High Speed EPROM
55/70 ns
28 CERDIP
32 CLLCC
1-11
Product Summary
PRODUCT SUMMARY (Continued)
PART NUMBER
DESCRIPTION
SPEED
PACKAGE
High-Speed Byte-Wide CMOS EPROMs (Continued)
WS57C256F
32K x 8 CMOS High Speed EPROM
35/45 ns
28 CERDIP
32 CLLCC
WS27C256L
32K x 8 CMOS High Speed LP EPROM
90/120 ns
28 CERDIP
28 PDIP
32 CLLCC
WS27C256F
32K x 8 CMOS High Speed LP EPROM
90/120 ns
28 CERDIP
32 CLLCC
WS27C512F
64K x 8 CMOS High Speed LP EPROM
70/90 ns
28 CERDIP
32 CLLCC
WS27C010L
128K x 8 CMOS High Speed LP EPROM
901120/150 ns
32 CERDIP
WS57C010F
128K x 8 CMOS High Speed EPROM
55/70 ns
32 CERDIP
Military Low Power CMOS EPROMs
WS27C64F
8K x 8 Military CMOS LP EPROM
901120/150 ns
28 CERDIP
32 CLLCC
WS27C128F
16K x 8 Military CMOS LP EPROM
90/120/150 ns
28 CERDIP
32 CLLCC
WS27C256F
32K x 8 Military CMOS LP EPROM
90/1201150 ns
28 CERDIP
32 CLLCC
High-Speed Word-Wide CMOS EPROMs
WS57C65
4K x 16 CMOS EPROM
55/70 ns
40 CERDIP
44 CLLCC
WS57C66
4K x 16 CMOS EPROM
(Multiplexed Address/Data)
55/70 ns
40 CERDIP
44 CLLCC
WS57C257
16K x 16 CMOS EPROM
55/70 ns
40 CERDIP
44 CLLCC
WS57C21OF
64K x 16 CMOS EPROM
55/70 ns
40 CERDIP
Mapped-Address Programmable Products
WSMAP162
128K EPROM/32K SRAM MAp™ Memory
40 ns
40 CERDIP
WSMAP161
128K EPROM/32K SRAM MAp™ Memory
40 ns
40 CERDIP
WSMAP168
128K EPROM/32K SRAM MAp™ Memory
40 ns
44 CPGA
44 CLLCC
44 PLDCC
CMOS Bit-Slice Processors and Peripherals
1-12
WS5901
4-Bit CMOS Bit-Slice Processor
C, 0
40 PDIP
WS59016
16-Bit CMOS Bit-Slice Processor
C, 0
64 SDBRZ DIP
68 PLDCC
68 CLDCC
WS59032
32-Bit CMOS Bit-Slice Processor
0, E
101 CPGA
WS5910A
12-Bit CMOS Variable Sequencer
A
40 CERDIP
40 PDIP
Product Summary
PRODUCT SUMMARY (Continued)
PART NUMBER
DESCRIPTION
SPEED
PACKAGE
CMOS Bit-Slice Processors and Peripherals (Continued)
WS5910B
12-Bit CMOS Variable Sequencer
B
40 CERDIP
40 PDIP
WS59520
CMOS Variable Pipeline Register
-
24 CERDIP
24 PDIP
WS59521
CMOS Variable Pipeline Register
-
24 CERDIP
24 PDIP
WS59510
CMOS 16-Bit Multiplier Accumulator
WS59820
CMOS Bi-Directional Bus Register
30/40/50 ns
68 PLDCC
68 CPGA
64 PDIP
23 ns
68 PLDCC
68 CPGA
D
Programmable Logic Products
WSPAC116
CMOS Programmable Stand-Alone
Controller
20 MHz
88 CPGA
WS444
CMOS Programmable Stand-Alone
Microsequencer (SAM)
32 MHz
24 CERDIP
WS448
CMOS Programmable Stand-Alone
Microsequencer (SAM)
32 MHz
24 CERDIP
NOTES: 1) RPROM™: Re-Programmable PROM
CMOS Replacement for Bipolar PROM's
2) LP EPROM: Low Power EPROM
1-13
1-14
HIGH-PERFORMANCE CMOS PRODUCTS
NUMERICAL LISTING
WAFERSCALE INTEGRA110N, INC.
PART NUMBER
DESCRIPTION
SPEED
PACKAGE
WS444
CMOS Programmable Stand-Alone
Microsequencer (SAM)
32 MHz
24 CERDIP
WS448
CMOS Programmable Stand-Alone
Microsequencer (SAM)
32 MHz
24 CERDIP
WS27C64F
8K x 8 Military CMOS LP EPROM
901120/150 ns
28 CERDIP
32 CLLCC
WS27C010L
128K x 8 CMOS High Speed LP EPROM
90/120/150 ns
32 CERDIP
WS27C128F
16K x 8 Military CMOS LP EPROM
901120/150 ns
28 CERDIP
32 CLLCC
WS27C256F
32K x 8 Military CMOS LP EPROM
901120/150 ns
28 CERDIP
32 CLLCC
WS27C256F
32K x 8 CMOS High Speed LP EPROM
90/120 ns
28 CERDIP
32 CLLCC
WS27C256L
32K x 8 CMOS High Speed LP EPROM
90/120 ns
28 CERDIP
28 PDIP
32 CLLCC
WS27C512F
64K x 8 CMOS High Speed LP EPROM
70/90 ns
28 CERDIP
32 CLLCC
WS57C43
4K x 8 CMOS RPROM™(1)
55/70 ns
24 CERDIP
28 CLLCC
WS57C43B
4K x 8 CMOS PROM
35/45 ns
24 PDIP
WS57C43B
4K x 8 CMOS RPROM™(1)
35/45/55 ns
24 CERDIP
28 CLLCC
WS57C45
2K x 8 CMOS Registered RPROM™(1)
20/25/35 ns
24 Flatpack
24 CERDIP
WS57C45
2K x 8 CMOS Registered PROM
20/25/35 ns
24 PDIP
24 CERDIP
WS57C49
8K x 8 CMOS PROM
55/70 ns
24 PDIP
WS57C49
8K x 8 CMOS RPROM™(1)
55/70 ns
24 CERDIP
28 CLLCC
WS57C49B
8K x 8 CMOS PROM
35/45 ns
24 PDIP
WS57C49B
8K x 8 CMOS RPROM™(1)
35/45/55 ns
24 CERDIP
28 CLLCC
WS57C51
16K x 8 CMOS RPROM™(1)
70 ns
28 CERDIP
WS57C51B
16K x 8 CMOS RPROM™(1)
40/45/55170 ns
28 CERDIP
32 CLLCC
WS57C64F
8K x 8 CMOS High Speed EPROM
55/70 ns
28 CERDIP
32 CLLCC
WS57C65
4K x 16 CMOS EPROM
55/70 ns
40 CERDIP
44 CLLCC
D
1-15
Numerical Listing
NUMERICAL LISTING (Continued)
PART NUMBER
DESCRIPTION
SPEED
PACKAGE
WS57C66
4K x 16 CMOS EPROM
(Multiplexed Address/Data)
55/70 ns
40 CERDIP
44 CLLCC
WS57C010F
128K x 8 CMOS High Speed EPROM
55/70 ns
32 CERDIP
WS57C128F
16K x 8 CMOS High Speed EPROM
55/70 ns
28 CERDIP
32 CLLCC
WS57C191
2K x 8 CMOS PROM
45/55 ns
24 PDIP
WS57C191
2K x 8 CMOS RPROM™(l)
45/55 ns
24 CERDIP
28 CLLCC
WS57C191B
2K x 8 CMOS PROM
35/45 ns
24 PDIP
WS57C191B
2K x 8 CMOS RPROM™(l)
35/45 ns
24 CERDIP
28 CLLCC
WS57C210F
64K x 16 CMOS EPROM
55/70 ns
40 CERDIP
WS57C256F
32K x 8 CMOS High Speed EPROM
55/70 ns
28 CERDIP
32 CLLCC
WS57C256F
32K x 8 CMOS High Speed EPROM
35/45 ns
28 CERDIP
32 CLLCC
WS57C257
16K x 16 CMOS EPROM
55170 ns
40 CERDIP
44 CLLCC
WS57C291
2K x 8 CMOS PROM
45/55 ns
24 PDIP
WS57C291
2K x 8 CMOS RPROM™(l)
45/55 ns
24 CERDIP
28 CLLCC
WS57C291B
2K x 8 CMOS PROM
35/45 ns
24 PDIP
WS57C291B
2K x 8 CMOS RPROM™(l)
35/45 ns
24 CERDIP
28 CLLCC
WS5901
4-Bit CMOS Bit-Slice Processor
C, D
40 PDIP
WS5910A
12-Bit CMOS Variable Sequencer
A
40 CERDIP
40 PDIP
WS5910B
12-Bit CMOS Variable Sequencer
B
40 CERDIP
40 PDIP
WS59016
16-Bit CMOS Bit-Slice Processor
C, D
WS59032
32-Bit CMOS Bit-Slice Processor
D, E
101 CPGA
30/40/50 ns
68 PLDCC
68 CPGA
64 PDIP
64 SDBRZ DIP
68 PLDCC
68 CLDCC
WS59510
CMOS 16-Bit Multiplier Accumulator
WS59520
CMOS Variable Pipeline Register
-
24 CERDIP
24 PDIP
WS59521
CMOS Variable Pipeline Register
-
24 CERDIP
24 PDIP
WS59820
CMOS Bi-Directional Bus Register
23 ns
68 PLDCC
68 CPGA
1-16
Numerical Listing
NUMERICAL LISTING (Continued)
DESCRIPTION
SPEED
WSMAP162
PART NUMBER
128K EPROM/32K SRAM MAp™ Memory
40 ns
40 CERDIP
PACKAGE
WSMAP161
128K EPROM/32K SRAM MAp™ Memory
40 ns
40 CERDIP
WSMAP168
128K EPROM/32K SRAM MAp™ Memory
40 ns
44 CPGA
44 CLLCC
WSPAC116
CMOS Programmable Stand-Alone
Controller
20 MHz
88 CPGA
o
NOTES: 1) RPROM™: Re-Programmable PROM
CMOS Replacement for Bipolar PROMs
2) LP EPROM: Low Power EPROM
1-17
1-18
-- ...---...
=' == -=: -====:
....
- ... - -
~~
CROSS REFERENCE
i-==i-F.= SF
-.-...-.-
!='
WAFERS(,ALE INTEGRATION, INC.
AMD
AM27S191
AM27PS191
AM27S291
AM27PS191
AM27S43
AM27PS43
AM27S49
AM27S49A
AM27S51
AM2901
AM2910A
AM29520
AM29521
AM29C101
AM29510
ATMEL
27HC64
27HC641
CYPRESS
CY7C291
CY7C292
CY7C264
CY7C901
CY7C910
CY7C9101
CY7C510
CY7C263
CY7C264
CY7C254
FAIRCHILD
93Z511
93Z565
29F01
29F10
WSI
WS57C191
WS57C191
WS57C291
WS57C291
WS57C43
WS57C43
WS57C49
WS57C49B
WS57C51 or WS57C51B
WS5901
WS5910A
WS59520
WS59521
WS59016'
WS59510
WSI
WS57C64F
WS57C49 or WS57C49B
WSI
WS57C191
WS57C291
WS57C49
WS5901
WS5910A
WS59016'
WS59510
WS57C49B
WS57C49B
WS57C51
WSI
WS57C191
WS57C49 or WS57C49B
WS5901
WS5910A
FUJITSU
MB7138
MB7138-SK
MB7142
MB7144
HARRIS
HM-76161
HM-76321
HM-76641
JOT
1DT39C01
1DT39C10
IDT49C401
IDT7210
LDI
L29C520
L29C521
MMI
63S1681
63S3281
NATIONAL
DM87S191
DM87S291
DM87S321
SIGNETICS
N82S191
N82S191_-3
N82S321
N82HS321
N82HS641
N27HC641
1.1.
TBP38S166_W
TBP38L166_W
TBP38SA166_W
TBP38S166_T
TBP38L166_T
TBP38SA166_T
MILITARY ONLY
AMD==== WSI
AM2764
AM27128
AM27256
• Functional Equivalent
WS27C64F
WS27C128F
WS27C256F
INTEL
M2764
M27128
M27256
M27C64
M27C128
M27C256
WSI
WS57C191
WS57C291
WS57C43
WS57C49
D
WSI
WS57C191
WS57C43
WS57C49 or WS57C49B
WSI
WS5901
WS5910A
WS59016*
WS59510
WSI
WS59520
WS59521
WSI
WS57C191
WS57C43 or WS57C43B**
WSI
WS57C191
WS57C291
WS57C43 or WS57C43B**
WSI
WS57C191
WS57C291
WS57C43
WS57C43 or WS57C43B"
WS57C49
WS57C49 or WS57C49B
WSI
WS57C191
WS57C191
WS57C191
WS57C291
WS57C291
WS57C291
WSI
WS27C64F
WS27C128F
WS27C256F
WS27C64F
WS27C128F
WS27C256F
"Available 01 'SS
1-19
1-20
ORDERING INFORMATION
WAFERSCALE INTEGRATION, INC.
HIGH-PERFORMANCE CMOS PRODUCTS
WS57C----'-,,-'
-
S
P
II
MP
L
Basic Part Number
Manufacturing Process:
(blank) = WSI Standard Commercial Product
Manufacturing Process
M
= Military Operating Range
-
Temperature: -55 to +125°C
Voltage: +5 Volts, ±10%
CB
= Commercial Burned-In (enhanced
commercial reliability)
MB
= MIL-STD-883C
Package:
A = Plastic Pin Grid Array
B = Ceramic SDBRZD DIP, 0.9"
C = CLLCC
o = CERDIp, 0.6"
F = Ceramic Flatpack
G = Ceramic Pin Grid Array
H = Ceramic Flatpack
J = PLDCC
K = CERDIp, 0.6"
L = CLDCC
M = Plastic DIP, 0.9"
P = Plastic DIP, 0.6"
S = Plastic DIP, 0.3"
T = CERDIp, 0.3"
W = Waffle Packed Dice
X = Ceramic Pin Grid Array
Y = CERDIp, 0.6"
Z = CLLCC
Window
No
No
Yes
Yes
Yes
No
No
No
No
No
No
No
No
Yes
Yes
No
No
Speed:
-35 = 35 ns
-55 = 55 ns
-70 = 70 ns
Etc.
1-21
1-22
WAFERSCALE INTEGRA110N, INC.
PROGRAMMABLE MEMORY PRODUCTS
2
SECTION INDEX
PROGRAMMABLE MEMORY PRODUCTS
PROM Memory:
WS57C1911291
WS57C191B/291B
WS57C45
WS57C43B
WS57C49
WS57C49B
2K
2K
2K
4K
8K
8K
x
x
x
x
x
x
8
8
8
8
8
8
CMOS PROM .................................................... 2-1
CMOS PROM .................................................... 2-5
Registered CMOS PROM ........................................... 2-9
CMOS PROM .................................................... 2-13
CMOS PROM .................................................... 2-17
CMOS PROM ................................................... 2-21
For additional information,
call 800-TEAM-WSI (800-832-6974).
In California, call 415-656-5400.
=1E1E~~
---r =: =:.= IE
WS57C1911291
~~~ ~ --------------------------------------------~~~~~~~~~~
PRELIMINARY
WAFERSCAlE INTEGRATION, INC.
2K X 8 CMOS PROM
KEY FEATURES
• Pin Compatible with AM27S191/291
and N82S191 Bipolar PROMs
• Immune to Latch-Up
• Fast Access Time
-
45 ns
• Low Power Consumption
-
225 mW Active Power
-
up to 200 rnA
• ESD Protection Exceeds 2000V
GENERAL DESCRIPTION
• Fast Programming
The WS57C191/291 is now available as a PROM. It utilizes the same design as the previously released RPROM™
from WSI. The difference is the PROM version is available in plastic packages and is not re-programmable. The plastic
packaging is ideal for high volume applications which require automatiC insertion. The plastic packaging also provides
an economic benefit when compared to a windowed cerdip package, For applications requiring reprogrammability,
contact your WSI sales representati.ve for information .on the WSI family of RPROMs.
The WS57C191/291 is a High Performance 16K-bit CMOS PROM. It is manufactured in an aclvanced CMOS EPROM
process which enables it to operate at bipolar speeds while consuming only 25% of the power of bipolar.
The WS57C191/291 's patented CMOS EPROM technology enables the entire memory array to be fully programmed
and erased prior to assembly. This capability ensures nearly 100% programming yield. Devices manufactured with
other types of technologies utilize varic)us types ofJuses wh.ich cannot be tested without permanently programming
the fuse. This results in a relatively high programming fallout at the packaged level.
Other testability features. were designed into the 57C1911291 whichenabte it to be tested for speed after assembly
without programming the memory array. This feature insures that the device will meet all A.C; as well as D.C. data
sheet parameters.
is
Another feature of theWS57c191/291 its uniquely designed output str~cture. When compared with other high speed
devices, the output structure of the WSs7C191/291 virtually eliminates the introduction of switch related noise into
the system environment.
.
The WS75C191/291 is configured in the standard Bipolar PROM pinout. The WS57C191 is offered in a 600 mil wide
Dip and the WS57C291 is offered in a 300 mil wide Dip.
PIN CONFIGURA T/ON
A7
Vee
A7
Vee
A,
A,
A,
A,
A,
A,
A,
A,
A,
A,.
A,
A,.
A3
CS1/v pp
A3
CS1/v pp
A2
CS2
A2
CS2
CS3
A,
CS3
A,
A.
07
A.
D.
0,
D.
0,
0,
O2
0,
O2
0,
GNO
03
GND
03
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C191/291-45
WS57C191/291-55
Address Access Time (Max)
45 ns
55 ns
Output Enable Time (Max)
20 ns
30 ns
2-1
WS57C1911291
·Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
ABSOLUTE MAXIMUM RA TINGS*
Storage Temperature .......... -65°C to +150°C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14.0V
ESD Protection ......................... >2000V
OPERATING RANGE
TEMPERATURE
Vcc
+5V + 5%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
=
=
VOL
Output Low Voltage
10L
VOH
Output High Voltage
IOH
ICCl
Vcc Active Current (CMOS)
Notes 1 and 3
ICC2
Vcc Active Current (TTL)
Notes 2 and 3
Input Load Current
VIN
Output Leakage Current
VOUT
1)
2)
CMOS inputs: GND ±
TTL inputs: V1L " O.BV,
O.3V or Vee
V 1H ;;, 2.0V.
±
O.3V.
3)
MAX
V
2.4
-4 rnA
A.C.
UNITS
0.4
I
I
Comm'l
20
Comm'l
25
= 5.5V or Gnd
= 5.5V or Gnd
III
ILO
NOTES:
MIN
16 rnA
-10
10
110
10
rnA
IlA
Power component adds 3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
WS57C191/291-45
SYMBOL
PARAMETER
MIN
MAX
WS57C191/291-55
MIN
MAX
45
Address to Output Delay
tACC
CS to Output Delay
tcs
20
30
Output Disable to Output Float
tDF
20
30
Address to Output Hold
tOH
UNITS
55
ns
0
0
TEST LOAD
AC READ TIMING DIAGRAM
(High Impedance Test Systems)
980
ADDRESSES~
..
2'01V~
VALID
~!
lACe
IOH
"l
Ics
OUTPUTS
2-2
"-"-
-
~
D.U.T.
I=
30pF
(INCWDING SCOPE
AND JIG
CAPACITANCE)
/
-
VALID
//
IOF
I--
TIMING LEVELS
Input Levels: 0 and 3V
Reference Levels: 1.SV
WS57C1911291
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA=25 ± 5°C, Vee=5.50V ± 5%, Vpp=13.5±O.5V)
PARAMETER
Input Leakage Current
Y,N =Vcc or Gnd
Vpp Supply Current During
Programming Pulse
SYMBOLS
MIN
MAX
UNIT
III
-10
10
tJ. A
60
mA
Vee Supply Current (Note 3)
Icc
V,L
-0.1
V,H
2.0
Ipp
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL = 16mA)
VOL
Output High Voltage During Verify
(IOH = -4mA)
VOH
25
mA
0.8
V
Vee +0.3
v
0.45
V
2.4
V
NOTE: 5) Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA=25 ± 5°C, Vee=5.50V ± 5%, Vpp= 13.5±O.5V)
SYMBOLS
t AS
PARAMETER
Address Setup Time
Chip Disable Setup Time
Data Set Up
Program Pulse Width (Note 6)
Data Hold Time
Chip Select Delay
Vpp Rise and Fall Time
tOF
tos
tpw
tOH
tcs
tRF
MIN
TYP
2
2
2
1
2
MAX
UNIT
30
ns
10
ms
30
ns
/lS
/ls
3
/ls
1
/ls
NOTE: 6) For programmers utilizing a one shot programming pulse, a 10 ms pulse width should be used.
PROGRAMMING WA VEFORM
ADDRESSES
V'H-~X
V,. ___-'
~
ADDRESS STABLE
_______________________
_
~IAS1
DATA
V'H~
v,.
__110'
DATA IN
~1
> <
DATA OUT
~~
Vpp
V'H
CS1/Vpp
V,.
CS2/CS3
2-3
WS57C1911291
PROGRAMMING
Upon delivery from WaferScale Integration, Inc., the
WS57C1911291 has a112048x8 bits in the "1:' or high state. "O's"
are loaded into. the WS57C191/291 through the procedure of
programming.
Programming is performed by raising Vce to 5.75V, disabling
the outputs, addressing the byte to be programmed, presenting the data to be programmed onto the data pins, and applying a 13.5V pulse to the CS1IVpp pin for 5 ms. The byte is
then verified by temoving the input data and reading the programmed byte as in the read operation. A 0.1 J.lF capacitor
between V pp and GND is needed to prevent excessive voltage
transients which could damage the device.
PROGRAMMERS
Data 110 Unipak 2 or 2B, familylpinout code 7B121; WSl's
MagicPro™ IBM PC Compatible Engineering Programmer.
ORDERING INFORMATION
2-4
PART NUMBER
SPEED
(ns)
WS57C191-45P
WS57C291-45S
WS57C191-55P
WS57C291-55S
45
45
55
55
PACKAGE
TYPE
24
24
24
24
Pin
Pin
Pin
Pin
PDIp,
PDIp,
PDIp,
PDIp,
0.6"
0.3"
0.6"
0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
P2
S1
P2
S1
Comm'l
Comm'l
Comm'l
Comm'l
Standard
Standard
Standard
Standard
===:=~
---- -
----- -
WS57C191B/291B
r __ .... ~~
___
""-P
~
_
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
2K
X
8 CMOS PROM
KEY FEATURES
• Ultra-Fast Access Time
-
• Pin Compatible with AM27S191/291
and N82S191 Bipolar PROMs
• Immune to Latch-Up
35 ns
• Low Power Consumption
-
-
225 mW Active Power
fI
up to 200 mA
ESD Protection Exceeds 2000V
• Plastic Dip Package
• Fast Programming
GENERAL DESCRIPTION
The WS57C191B/291B is an extremely HIGH PERFORMANCE 16K Electrically Programmable Read Only Memory.
It is specifically designed to replace bipolar PROMs in existing applications.
The WS57C191B/291B is manufactured using WSI's patented CMOS EPROM technology. As a result, the entire memory
array can be fully programmed and erased prior to assembly. This capability ensures nearly 100% programming yield.
Devices manufactured with other types of technologies utilize various types of fuses which cannot be tested without
permanently programming the fuse. This results in relatively high programming fallout when compared to a WSI PROM.
Other testability features were designed into the WS57C191B/291B which enable it to be tested for speed after assembly
without programming the memory array. This capability insures that the product will meet all A.C. as well as D.C.
data sheet parameters.
Another feature of the WS57C191B/291B is its uniquely designed output structure. When compared with other high
speed devices, the output structure of the WS57C191 B/291 B virtually eliminates the introduction of switch related noise
into the system environment.
The WS57C191B/291B is configured in the standard Bipolar PROM pinout. The WS57C191B is offered in a 600 mil
wide Dip and the WS57C291B is offered in a 300 mil wide Dip.
PIN CONFIGURATION
A7
24
Vee
A7
Vee
A.
23
As
A.
As
A.
22
A.
A.
A.
A.
21
A,.
A.
A,.
As
20
CS1IVpp
As
CS1'Vpp
A:z
19
CS_
A_
CS_
A,
18
CSs
A,
CSs
A.
17
07
Au
07
o.
16
o.
D.
o.
0,
15
O.
0,
D.
0_
14
D.
D_
O.
Os
GND
Os
GND
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C191 B/291 B-35
WS57C191B/291B-45
Address Access Time (Max)
45 ns
55 ns
Output Enable Time (Max)
20 ns
30 ns
2-5
WS57C191B1291B
*Notice: Stresses above those listed here may
cause permanent damage to the device. This is a
stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect device reliability.
ABSOWTE MAXIMUM RAT/NGS*
Storage Temperature .......... -65° to +150°C
Voltage on any pin with
respect to GND .............. -0.6V to +7V
Vpp with respect to GND ........ -0.6V to +14V
ESD Protection ...................... >2000V
OPERATING RANGE
TEMPERATURE
Vcc
+5V ± 5%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
Icc1
Vcc Active Current (CMOS)
Notes 1 and 3
Icc2
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN
ILO
Output Leakage Current
NOTES:
3)
UNITS
0.4
V
2.4
I
I
= 5.5V or Gnd
VO UT = 5.5V or Gnd
1) CMOS inputs: GND ± O.3V or Vee ± O.3V.
2) TIL inputs: V1L " O.BV, V1H " 2.0V.
MAX
MIN
= 16 mA
= -4 mA
Comm'l
30
Comm'l
40
-10
10
-10
10
mA
J.tA
A.C. Power component adds 3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
WS57C191 B/291 B-35 WS57C191 B/291 B-45
SYMBOL
PARAMETER
MIN
MAX
MAX
MIN
Address to Output Delay
tACC
35
45
CS to Output Delay
tcs
20
20
Output Disable to Output Float
tDF
20
20
Address to Output Hold
tOH
0
UNITS
ns
0
TEST LOAD
(High Impedance Test Systems)
AC READ TIMING DIAGRAM
98(1
ADDRESSES~
..
CS1/Vpp
VALID
.'
tACe
"J.
te.
OUTPUTS
2-6
"-"-
tOH
~
-
/
2.01V~
D.U.T.~ 30pF
I=-
TI M I NG LEVELS
-
VALID
L/
tD•
I-
Input Levels: 0 and 3V
Reference Levels: 1.5V
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
WS57C191B1291B
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee
PARAMETER
= 5.50V ± 5%, Vpp = 13.5 ± 0.5V)
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
VIN = Vee or Gnd
III
-10
10
J.tA
Vpp Supply Current During
Programming Pulse
Ipp
60
rnA
Vee Supply Current (Note 3)
lee
25
rnA
Input Low Level
VIL
-0.1
0.8
V
Input High Level
VIH
2.0
Vee +0.3
V
Output Low Voltage During Verify
(lOL = 16 rnA)
VOL
0.45
V
Output High Voltage During Verify
(lOH = -4 rnA)
VOH
2.4
V
NOTE: 4) V pp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA
= 25 ± 5°C, Vee = 5.50V ± 5%, Vpp = 13.5 ± 0.5V)
SYMBOLS
MIN
Address Setup Time
PARAMETER
tAS
2
Chip Disable Setup Time
tOF
2
Data Set Up
tos
Program Pulse Width (Note 5)
tpw
1
Data Hold Time
tOH
2
Chip Select Delay
tes
Vpp Rise and Fall Time
tRF
TYP
MAX
UNIT
J.tS
30
ns
J.ts
3
10
ms
J.tS
30
1
ns
J.ts
NOTE: 5) For programmers utilizing a one shot programming pulse. a 10 ms pulse width should be used.
PROGRAMMING WAVEFORM
ADDRESSES
VIH---""'X
ADDRESS
STABLE
V _ _ _J
' -_ _ _ _ _ _ _
___
_ _ _ _ _ _ _ _ _ _ _ _ __
,L
DATA :::
Vpp
r-
lAS
-1
~_ _ _ _ _D_AT._i\_IN_ _ _ _ _...;'>_<,__D_A_:rA_O_U_T__
1'-- r'"l
'"1
~~
V,H
CS1Npp
V,L
V,H
CS2/CS3
V,L
2·7
WS57C191B12918
PROGRAMMING
Upon delivery from WaferScale Integration, Inc., the
WS57C191B/291B has all2048x8 bits in the "1:' or high state.
"O's" are loaded into the WS57C191B1291B through the procedure of programming.
Programming is performed by raising Vee to 5.75V, disabling
the outputs, addressing the byte to be programmed, presenting
the data to be programmed onto the data pins, and applying
a 13.5V pulse to the CS1Npp pin for 5 ms. The byte is then
verified by removing the input data and reading the programmed byte as in the read operation. A 0.1 !iF capacitor
between Vpp and GND is needed to prevent excessive voltage
transients which could damage the device.
PROGRAMMERS
Data I/O Unipak 2 or 2B, family/pinout code 7B/21; WSl's
MagicPro™ IBM PC Compatible Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C1918-35P
WS57C2918-35S
WS57C1918-45P
WS57C2918-45S
2-8
SPEED
PACKAGE
TYPE
(ns)
35
35
45
45
24
24
24
24
Pin
Pin
Pin
Pin
PDIp,
PDIp,
PDIp,
PDIp,
0.6"
0.3"
0.6"
0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
P2
S1
P2
S1
Comm'l
Comm'l
Comm'l
Comm'l
Standard
Standard
Standard
Standard
II' ==:= ==iE
---_
... - -~--
---~
r
~~
-
~ _
.....
~.-
---~~
WS57C45
ADVANCE INFORMATION
WAFERSCALE INTEGRA noN, INC.
HIGH-SPEED 2K
8 REGISTERED CMOS PROM
X
KEY FEATURES
• Pin Compatible with AM27S45 and
CY7C245
• Ultra-Fast Access Time
-
20 ns Setup
10 ns Clock to Output
• Immune to Latch-Up
• Low Power Consumption
-
-
225 mW Active Power
up to 200 rnA
• ESC Protection Exceeds 2000V
• Fast Programming
• Programmable Synchronous or
Asynchronous Output Enable
• Programmable Asynchronous
Initialize Register
GENERAL DESCRIPTION
The WS57C45 is an extremely HIGH PERFORMANCE 16K Registered CMOS PROM. It is a direct drop-in replacement for such devices as the AM27S45 and CY7C245.
To meet the requirements of systems which execute and fetch instructions simultaneously, an 8-bit parallel data register
has been provided at the output which allows PROM data to be stored while other data is being addressed.
An asynchronous initialization feature has been provided which allows a user programmable 2049th word to be placed
on the outputs independent of the system clock. This feature can be used to force an initialize word or provide a
preset or clear function.
A further advantage of the WS57C45 over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
Unlike devices which cannot be erased, every WS57C45 is 100% tested with worst case test patterns, switching
characteristics, and functionality before assembly.
PIN CONFIGURATION
P Dip
CerDip
vee
vee
A.
At
INIT
INIT
OE/OEs
OE/OEs
CP
CP
0,
07
o.
o.
o.
o.
O.
O.
O.
o.
GND
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C45-20
WS57C45-25
WS57C45-35
Address Access Time (Max)
20 ns
25 ns
35 ns
Output Enable Time (Max)
10 ns
12 ns
15 ns
2-9
WS57C45
*Notiee: Stresses above those listed here may
cause permanent damage to the device. This is a
stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect device reliability.
ABSOLUTE MAXIMUM RATINGS·
Storage Temperature .......... -S5°C to +150°C
Voltage on any pin with
respect to GND ..................... -O.SV to +7V
VPP with respect to GND ........ -O.SV to +14.0V
ESD Protection ......................... >2000V
OPERATING RANGE
Range
Temperature
Vee
Comm'l.
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range. (See above)
SYMBOL
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL= 1SmA
VOH
Output High Voltage
IOH=-4mA
ICC1
Vcc Active Current (CMOS)
Notes 1 and 3
MIN
MAX
UNITS
0.4
V
ICC2
2.4
Notes 2 and 3
Vcc Active Current (TTL)
30
Comm'l.
Military
35
Comm'l.
40
40
Military
III
Input Load Current
VIN = 5.5V or Gnd
-10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
NOTES: 1) CMOS
inputs: GND ± O:JV or Vee ± 0.3V.
2) TTL inputs: V 1L .. O.BV, V 1H .. 2.OV.
3)
A.C.
Power component adds 3
mA
10
10
JlA
rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
Address Setup to Clock HIGH
SYMBOL
WS57C45-20
MIN
tSA
20
0
MAX
WS57C45-25
WS57C45-35
MIN
MIN
MAX
25
Address Hold From Clock HIGH
tHA
tco
Clock Pulse Width
t pwc
12
15
20
OEs Setup to Clock HIGH
tSOEs
10
12
15
tHOEs
5
5
5
OEs Hold From Clock HIGH
0
0
12
15
ns
20
Delay From INIT to Valid Output
tOI
INIT Recovery to Clock HIGH
tRI
15
15
20
tpWI
15
15
20
INIT Pulse Width
20
20
Active Output From Clock HIGH
t LZC
15
15
20
Inactive Output From Clock HIGH
tHZC
15
15
20
Active Output From OE LOW
t LZOE
15
15
20
Inactive Output From OE HIGH
t HZOE
15
15
20
2-10
UNITS
35
Clock HIGH to Valid Output
10
MAX
WS57C45
TEST LOAD (High Impedance Systems)
97.50
Input Levels: 0 and 3V
2.01V~
D.U.T.
I-=-
TIMING LEVELS
Reference Levels: 0.8 and 2.0V
30pF
(INCWDING SCOPE
AND JIG
CAPACITANCE)
AC READ TIMING DIAGRAM
Ao-A,o
OEs
______________~~~--+_~~~ll------------L.'-1
CP
t LZOE
PROGRAMMERS
Data I/O Unipak 2 or 2B; WSl's MagicPro™ IBM PC Compatible Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C45-20S
WS57C45-20K
WS57C45-25S
WS57C45-25K
WS57C45-25KMB
WS57C45-35S
WS57C45-35K
WS57C45-35KMB
PACKAGE
TYPE
SPEED
(ns)
20
20
25
25
25
35
35
35
24
24
24
24
24
24
24
24
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Plastic DIP, 0.3"
CERDIP, 0.3"
Plastic DIP, 0.3"
CERDIp, 0.3"
CERDIp, 0.3"
Plastic DIP, 0.3"
CERDIp, 0.3"
CERDIp, 0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
S1
K1
S1
K1
K1
S1
K1
K1
Comm'l
Comm'l
Comm'l
Comm'l
Military
Comm'l
Comm'l
Military
Standard
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
MIL-STD-883C
2·11
2-12
WS57C43B
ADVANCE INFORMATION
WAFERSCALE INlEGRATION, INC
4K X 8 CMOS PROM
KEY FEATURES
• Ultra-Fast Access Time
-
• Pin Compatible with AM27S43
and N82S321 Bipolar PROMs
• Immune to Latch-Up
35 ns
• Low Power Consumption
-
300 mW Active Power (20 MHz)
-
• Fast Programming
fJ
up to 200 mA
• Available in 300 Mil Dip
GE~~, ~sci:l1I1~ON
The WS57C43B is now available d ; l PfM;)M;:ft utiliiQt~~arncf,~ign as the previously released RPROM™ from
WSi. The difference is the PROMyMsiott'1s aVailablem plaStic pa.~Kages and is not re-programmable. The plastic
packaging is ideal for high volume I;jppt~tl~ns'~ip~~uire"lUtorriatic insertion. The pl~~ging also provides
an economic benefit when compared tcia';jVindOwecf cerdip packag~, f9fapp~tions ~ir,i,n~ reprogrammability,
contact your WSI sales representanVe for information on the WSI lMillY"ot RPfiilOMs.
ex'"
The WS57C43B is a High Performance 32K-bit-'PMOS PRQM;.!t is~'.~arru1a~urid in an ~vanced CMOS EPROM
process which enables it to:@llle~;,at bi~arhMleeds w~g~su~9,90,~ ~::oHhe'power of bipolar.
The WS57C43B~:~t~d ~o~~i!f~p~c~~IO!;lY ~nibies'tffe;eriti~n:;emory arrayt? beJ~~~Rgrammed and
erased prior to ~emb(~!fhi$: c"~en~e~npt!ly 100% programming X~~.ptvi¢!s manufactured with other
types of techn~:,util~;ijar;itiUs ty~ onuses which cannot be:m~ Wltt@Jt pei'~nently programming the
fuse. This resWW'in ;i'ftlcit!veIY'high programming falloutif'ihe plil.~aged leveC'.·. ,;",.,;
Other testabiliffeatures were deSi~G~th(i'WS57C4~~Ch'~hiib\~JYto ~itested;:for ~~~~d~fter assembly
without progral1)miU9-Jhe memory ari§'. T~ f~ure insutU;~:1he:iRrQC\lJct will meet all A.C. as well as D.C. data
;:'::::r,;i.~J;· ' " . ":"
sheet parame~'~r;~,:,;: ~~
The WS57C43E{~ cQj(jJi!nl:l';~:Jn the stafidard Bipotai PROM pinout which provides an easy upgrade path for systems
which are curr(tl.1ty l!~ing'f~olar PROMs. It also uses the same programming algorithm as its predecessor the
WS57C43.
:'7~;":;:
.
tET';5';f
PIN CONFIGURATION
As
As
A"
CS1/Vpp
CS1IVpp
es,
es,
es,
07
07
o.
O.
D.
0,
0,
D.
0,
0,
GNO
0,
0,
0,
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C43B-35
WS57C43B-45
WS57C43B-55
Address Access Time (Max)
35 ns
45 ns
55 ns
Output Enable Time (Max)
25 ns
20 ns
25 ns
2-13
WS57C438
·Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
ABSOWTE MAXIMUM RATINGS·
Storage Temperature .......... -65° to +150°C
Voltage on any pin with
respect to G NO .............. - 0.6V to + 7V
Vpp with respect to GND ........ -0.6V to +14V
ESD Protection ...................... >2000V
OPERATING RANGE
TEMPERATURE
Vcc
+5V ± 5%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
MAX
VOL
Output Low Voltage
IOL = 16 rnA
VOH
Output High Voltage
IOH = -4 rnA
lect
Vcc Active Current (CMOS)
Notes 1 and 3
ICC2
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
NOTES:
1) CMOS inputs: GND ± O.3V or Vee ± O.3V.
2) TTL inputs: V IL " O.BV, V IH ~ 2.0V.
UNITS
0.4
V
2.4
I
I
Comm'l
30
Comm'l
40
3) A.C. Power component adds 3
rnA
~
rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
WS57C43B-35
SYMBOL
Address to Output Delay
MIN
MAX
WS57C43B-45
MIN
MAX
WS57C43B-55
MIN
MAX
tACC
35
45
55
CS to Output Delay
tes
20
25
25
Output Disable to Output Float
tDF
20
25
25
Address to Output Hold
tOH
0
0
UNITS
ns
0
TEST LOAD
AC READ TIMING DIAGRAM
(High Impedance Test Systems)
980
ADDRESSES~
....
VALID
2'01V~
.'
tACe
D.u.T.
tOH
"J.
2-14
I-=-
30pF
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
/
Ics
OUTPUTS
~
I--
-
VALID
~
TIMING LEVELS
/J
tDF
f-
Input Levels: 0 and 3V
Reference Levels: 1.5V
WS57C438
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA=25 ± 5°C, Vee = 5.50V ± 5%, Vpp=13.5±0.5V)
PARAMETER
Input Leakage Current
V,N =Vcc or Gnd
Vpp Supply Current During
Programming Pulse
Ipp
Icc
V 1L
-0.1
VIH
2.0
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL = 16mA)
VOL
Output High Voltage During Verify
(loH = -4mA)
VOH
5)
-10
III
Vee Supply Current (Notes 2 and 3)
NOTES:
MIN.
SYMBOLS
MAX.
UNIT
10
/LA
60
mA
30
mA
0.8
V
Vee +0.3
v
0.45
V
V
2.4
Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA=25 ± 5°C, Vee = 5.50V ± 5%, Vpp= 13.5±0.5V)
SYMBOLS
PARAMETER
Address Setup Time
Chip Disable Setup Time
MIN.
t AS
tDF
t DS
tpw
Data Set Up
Program Pulse Width
Data Hold Time
Chip Select Delay
TYP.
2
1
2
tDH
3
UNIT
30
P.s
ns
10
P.s
ms
P.s
ns
P.s
30
tes
Vpp Rise and Fall Time
MAX.
2
tRF
1
NOTES: A single shot programming algorithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
V,H
ADDRESSES
X
- - -.....
V'L _ _ _oJ
DATA V
,H
V,L
ADDRESS STABLE
....- - - - - - - - - - - - - - - - - - - - - - - - -
~tAs1
~
DATA IN
»---«
~-------------
~1
,}
DATA OUT
Vpp
CS1/V pp
CS2
2·15
WS57C438
PROGRAMMING
Upon delivery from WaferScale Integration, Inc., the WS57C43B
has all 4096 x 8 bits in the "1," or high state. "O's" are loaded
into the WS57C43B through the procedure of programming.
grammed byte as in the read operation. A 0.1 ItF capacitor
between Vpp and GND is needed to prevent excessive voltage
transients which could damage the device.
Programming is performed by raising Vee to 5.5V, disabling
the outputs, addressing the byte to be programmed, presenting the data to be programmed onto the data pins, and applying a 13.5V pulse to the CS1N pp pin for 5 ms. The byte is then
verified by removing the input data and reading the pro-
PROGRAMMERS
Data 110 Unipak 2 or 2B, software version 11 or later, familyl
pinout code 7B/63; WSl's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C43B-35S
WS57C43B-35P
WS57C43B-45S
WS57C43B-45P
WS57C43B-55S
WS57C43B-55P
2-16
SPEED
PACKAGE
TYPE
(ns)
35
35
45
45
55
55
24
24
24
24
24
24
Pin
Pin
Pin
Pin
Pin
Pin
PDIP,
PDIp,
PDIp,
PDIp,
PDIp,
PDIp,
0.3"
0.6"
0.3"
0.6"
0.3"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
S1
P2
S1
P2
S1
P2
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Standard
Standard
Standard
Standard
Standard
Standard
WS57C49
WAFERSCALE INTEGRA TlON, INC.
BK X B CMOS PROM
KEY FEATURES
• Very-Fast Access Time
-
• Pin Compatible with AM27S49
and MB7144 Bipolar PROMs
55 ns
• Immune to Latch-Up
• Low Power Consumption
-
-
300 mW Active Power (Full Speed)
• Fast Programming
fJ
up to 200 mA
ESD Protection Exceeds 2000V
• Plastic Dip Package
GENERAL DESCRIPTION
The WS57C49 is an extremely HIGH PERFORMANCE 64K Electrically Programmable Read Only Memory. It is
specifically designed to replace bipolar PROMs in existing applications.
The WS57C49 is manufactured using WSI's patented CMOS EPROM technology. As a result, the entire memory array
can be fully programmed and erased prior to assembly. This capability ensures nearly 100% programming yield.
Devices manufactured with other types of technologies utilize various types of fuses which cannot be tested without
permanently programming the fuse. This results in relatively high programming fallout when compared to a WSI PROM.
Other testability features were designed into the WS57C49 which enable it to be tested for speed after assembly
without programming the memory array. This capability insures that the product will meet all A.C. as well as D.C.
data sheet parameters.
The WS57C49 is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for systems
which are currently using Bipolar PROMs.
PIN CONFIGURATION
A7
1.
vee
"-
2
As
A.
3
A.
A.
4
A.
5
A.
6
CS1IVpp
A11
A,
A,.
A.
07
·0.
0,
O.
TOP
A,.
20
GND
15
o.
o.
14
O.
16
10
03
PRODUCT SELECTION GUIDE
PARAMETER
WS57C49-55
WS57C49-70
Address Access Time (Max)
55 ns
70 ns
Output Enable Time (Max)
20 ns
25 ns
2-17
WS57C49
ABSOWTE MAXIMUM RATINGS·
*Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65° to +150°C
Voltage on any pin with
respect to GND .............. -0.6V to +7V
V pp with respect to GND ........ -0.6V to +14V
ESD Protection ...................... >2000V
OPERATING RANGE
TEMPERATURE
Vcc
+5V ± 5%
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range. (See Above)
PARAMETER
TEST CONDITIONS
MIN
MAX
0.4
VOL
Output Low Voltage
IOL = 16 mA
VOH
Output High Voltage
IOH = -4 mA
ICCl
Vcc Active Current (CMOS)
Notes 1 and 3
ICC2
V cc Active Current (TTL)
Notes 2 and 4
III
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
NOTES:
1) CMOS inputs: GND ± O.3V or Vee
2) TTL inputs: V1L .. O.BV, V 1H ,. 2.0V.
AC READ CHARACTERISTICS
PARAMETER
± O.3V.
3)
A.C.
UNITS
V
2.4
I
I
Comm'l
20
Comm'l
25
Power component adds 3
mA
IlA
rnA/MHz.
Over Operating Range. (See Above)
WS57C49-55
SYMBOL
Address to Output Delay
MIN
MAX
WS57C49-70
MIN
tACC
55
70
CS to Output Delay
tcs
20
25
Output Disable to Output Float
tOF
20
25
Address to Output Hold
tOH
10
UNITS
MAX
ns
10
TEST WAD
AC READ TIMING DIAGRAM
(High Impedance Test Systems)
98a
ADDRESSES~
....
2.01V~
VALID
~!
lACe
10H
leo
OUTPUTS
2-18
"-"-
-
I-
D.U.T~~30PF
I-=-
/
TIMING LEVELS
-
VALID
Input Levels: 0 and 3V
IDF
I-
Reference Levels: 1.5V
(INCWDING SCOPE
AND JIG
CAPACITANCE)
WS57C49
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.50V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN
MAX
UNIT
Input Leakage Current
VIN = Vee or Gnd
III
-10
10
IlA
Vpp Supply Current During
Programming Pulse
Ipp
60
mA
Vee Supply Current (Notes 2 and 3)
lee
25
mA
Input Low Level
V IL
-0.1
0.8
V
Input High Level
VIH
2.0
Vee +0.3
V
Output Low Voltage During Verify
(IOL = 16 mAl
VOL
0.45
V
Output High Voltage During Verify
(lOH = -4 mAl
VOH
2.4
V
NOTE: 4) Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.50V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN
t AS
2
Address Setup Time
Chip Disable Setup Time
tOF
Data Set Up
tos
2
Program Pulse Width
tpw
1
Data Hold Time
tOH
2
Chip Select Delay
tes
Vpp Rise and Fall Time
TYP
MAX
UNIT
30
ns
10
ms
IlS
IlS
3
IlS
30
ns
1
tRF
J.lS
NOTE: Single shot programming algorithms should use one 10 ms pulse per word.
PROGRAMMING WAVEFORM
V,H
X
ADDRESSES
V,L
DATA
IH
V
V,L
~IAS1
=> <
-- -loF
Vpp
V,H
CS1N pp
V,L
ADDRESS STABLE
I--
I
los
DATA
~
> <
IN
-~1
1~1~1
/ 1\
'RF
DATA OUT
- ~~
~
IRF
1--+
2-19
WS57C49
PROGRAMMING
Upon delivery from WaferScale Integration, Inc., the WS57C49
has all 8192x8 bits in the "1," or high state. "O's" are loaded
into the WS57C49 through the procedure of programming.
Programming is performed by raising Vee to 5.5V, disabling
the outputs, addressing the byte to be programmed, presenting
the data to be programmed onto the data pins, and applying
a 13.5V pulse to the CS1/v pp pin for 5 ms. The byte is then
verified by removing the input data and reading the pro-
grammed byte as in the read operation. A 0.1 I1F capacitor
between V pp and GND is needed to prevent excessive voltage
transients which could damage the device.
PROGRAMMERS
Data 110 Unipak 2 or 2B, software version 9 or later, familyl
pinout code 3C/01; WSI's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C49-55P
WS57C49-70P
2-20
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
55
70
24 Pin PDIp, 0.6"
24 Pin PDIp, 0.6"
P2
P2
Comm'l
Comm'l
Standard
Standard
SPEED
WS57C49B
ADVANCE INFORMATION
WAFERS(,ALE INTEGRA110N, INC.
BK
X
B CMOS PROM
KEY FEATURES
• Ultra-Fast Access Time
-
• Pin Compatible with AM27S49
and MB7144 Bipolar PROMs
• Immune to Latch-Up
35 ns
• Low Power Consumption
-
300 mW Active Power (20 MHz)
-
• Fast Programming
up to 200 mA
• Available in 300 Mil Dip
GENERAL DESCRIPTION
The WS57C49B is now available as a PROM. It utilizes thesamedesi9f\ as the previously released RPROM™ from
WSI. The difference is the PROM version is available in philSticpaCkaS&s and is not re-programmable. The plastic
packaging is ideal for high volume applicati()ns Which r$guireautoml:!itic insertion. The plastic packaging also provides an economic benefit when compl:!;redtoa winQowed6erdip pac~. For applications requiring reprogrammability,
contact your WSI sales representative forinformat.ion orfthe WSI family of RPROMs.
The WS57C49B is a High Performance 64K,bit CMOS PROM. It is manufactured in an I:!.
....'.
"."".'; .. , '. . '
.;.. .>
sheet parameters.
Another featurEl!of tile WSS7C49B isim uniqtlelydesigned,outPP~ striJetUre,~heJ1bompat,d with:QtfI.~r high-speed
devices, the output~ructure of the ~q?c:49B~rtually eliminal$$ tt;!eintll,lductionof sWitCh-related noise into the
;: ' , ; . ; '
system environmen"~ <>
The WS57C49Bi$ ctlriJigil~~ in the staMard BipOla~7PROM pinout which provides an easy upgrade path for systems
which are currently using Bipolar PROMs.
PIN CONFIGURATION
A,
Vee
A,
Vee
"-
As
A,
As
A,
A.
A,
A.
A.
A"
A.
A"
A,
CS1JV pp
A,
CS1IV pp
A.
cs.
A.
cs.
A,
CS,
A,
CS,
"-
0,
Ao
0,
00
0,
00
0,
0,
0,
0,
0,
O.
O.
O.
O.
GNO
0,
GND
0,
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C49B-35
WS57C49B-45
Address Access Time (Max)
35 ns
45 ns
Output Enable Time (Max)
20 ns
25 ns
2-21
WS57C49B
ABSOLUTE MAXIMUM RATINGS*
·Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65 C to +150 C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14.0V
ESD Protection ......................... >2000V
0
0
OPERATING RANGE
TEMPERATURE
Vcc
+5V ± 5%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL = 16 mA
VOH
Output High Voltage
IOH = -4 mA
MIN
MAX
I
Icc1
Vcc Active Current (CMOS)
Notes 1 and 3
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
1) CMOS inputs: GND ± O.3V or Vee ± O.3V.
2) TTL inputs: V1L '" O.BV, V1H ;. 2.0V.
3)
V
2.4
Icc2
NOTES:
UNITS
0.4
I
Comm'l
30
Comm'l
40
mA
JJA
A.C. Power component adds 3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
SYMBOL
WS57C49B-35
WS57C49B-45
MIN
MIN
MAX
MAX
Address to Output Delay
tACC
35
CS to Output Delay
tcs
20
20
Output Disable to Output Float
tOF
20
20
Address to Output Hold
tOH
0
UNITS
45
ns
0
TEST LOAD
AC READ TIMING DIAGRAM
ADDRESSES =:>f411
(High Impedance Test Systems)
:r
VALID
... '
lACe
CS
"J
teo
OUTPUTS
2-22
I--
98Q
2.01V~
tOH
~
D.U.T·~30PF
I-=-
(INCWDING SCOPE
AND JIG
CAPACITANCE)
/
-
TIMING LEVELS
VALID
tDF
I--
Input Levels: 0 and 3V
Reference Levels: 1.5V
WS57C49B
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA
= 25
PARAMETER
± 5°C, Vee
= 5.50V
± 5%, Vpp
SYMBOLS
Input Leakage Current
VIN = Vee or Gnd
III
Vpp Supply Current During
Programming Pulse
Vee Supply Current (Notes 2 and 3)
= 13.5
± 0.5V)
MIN.
MAX.
UNIT
-10
10
/lA
60
mA
Ipp
lee
VIL
35
mA
Input Low Level
-0.1
0.8
V
2.0
Vee+0.3
V
0.45
V
Input High Level
VIH
Output Low Voltage During Verify
(IOL = 16mA)
VOL
Output High Voltage During Verify
(IOH = -4mA)
VOH
2.4
V
NOTE: 5) Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN.
2
Address Setup Time
tAs
Chip Disable Setup Time
toF
Data Setup
Program Pulse Width
tos
tpw
2
1
Data Hold Time
tOH
2
Chip Select Delay
tcs
Vpp Rise and Fall Time
tRF
1
TYP.
3
MAX.
UNIT
30
/lS
ns
10
/lS
ms
30
/lS
ns
/ls
NOTE: A single shot programming algorithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
V'H---....
ADDRESS STABLE
2-23
WS57C498
PROGRAMMING
Upon delivery from WaferScale Integration, Inc., the WS57C49B
has all 8192 x 8 bits in the "1," or high state. "O's" are loaded
into the WS57C49B through the procedure of programming.
grammed byte as in the read operation. A 0.1 J.lF capacitor
between V pp and GND is needed to prevent excessive voltage
transients which could damage the device.
Programming is performed by raising Vee to 5.5V, disabling
the outputs, addressing the byte to be programmed, presenting the data to be programmed onto the data pins, and applying a 13.5V pulse to the CS1/vpp pin for 5 ms. The byte is then
verified by removing the input data and reading the pro-
Data I/O Unipak 2 or 2B, software version 9 or later, family/pinout
code 3C/ffl; WSl's MagicPro™ IBM PC Compatible Engineering Programmer.
PROGRAMMERS
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C49B-35S
WS57C49B-35P
WS57C49B-45S
WS57C49B-45P
35
35
45
45
2-24
PACKAGE
TYPE
24
24
24
24
Pin
Pin
Pin
Pin
POIp,
POIP,
POIp,
POIp,
0.3"
0.6"
0.3"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
S1
P2
S1
P2
Comm'l
Comm'l
Comm'l
Comm'l
Standard
Standard
Standard
Standard
WAFERSCALE INTEGRA 710N, INC
RE-PROGRAMMABLE MEMORY: PROOUCTS
3
SECTION INDEX
RE-PROGRAMMABLE MEMORY PRODUCTS
RPROM Memory:
WS57C191/291
WS57C191 B/291 B
WS57C45
WS57C43
WS57C43B
WS57C49
WS57C49B
WS57C51
WS57C51B
2K x 8 CMOS RPROM ................................................... 3-1
2K x 8 CMOS RPROM ................................................... 3-5
2K x 8 Registered CMOS RPROM .......................................... 3-9
4K x 8 CMOS RPROM .................................................. 3-13
4K x 8 CMOS RPROM .................................................. 3-17
8K x 8 CMOS RPROM .................................................. 3-21
8K x 8 CMOS RPROM .................................................. 3-25
16K x 8 CMOS RPROM ................................................. 3-29
16K x 8 CMOS RPROM ................................................. 3-33
EPROM Memory (x8):
WS27C64F
WS57C64F
WS27C128F
WS57C128F
WS27C256F
WS57C256F (-55)
WS57C256F (-35)
WS27C256L
WS27C256F
WS27C512F
WS27C010L
WS57C010F
8K x 8 CMOS EPROM (Mil) .............................................. 3-37
8K x 8 CMOS EPROM .................................................. 3-41
16K x 8 CMOS EPROM (Mil) ............................................. 3-45
16K x 8 CMOS EPROM ................................................. 3-49
32K x 8 CMOS EPROM (Mil) ............................................. 3-53
32K x 8 CMOS EPROM ................................................. 3-57
32K x 8 CMOS EPROM ................................................. 3-61
32K x 8 CMOS EPROM ................................................. 3-65
32K x 8 CMOS EPROM ................................................. 3-69
64K x 8 CMOS EPROM ................................................. 3-73
128K x 8 CMOS EPROM ................................................ 3-77
128K x 8 CMOS EPROM ................................................ 3-83
EPROM Memory (x16):
WS57C65
WS57C66
WS57C257
WS57C210F
4K x 16 CMOS EPROM ................................................. 3-87
4K x 16 Muxed CMOS EPROM ........................................... 3-91
16K x 16 CMOS EPROM ................................................ 3-97
64K x 16 CMOS EPROM ................................................ 3-101
Mappable Memory Products:
WSMAP1621WSMAP161 MAp™ Memory ....................................................... 3-105
WSMAP168 MAp™ Memory .................................................................. 3-115
For additional information,
call 800-TEAM-WSI (800-832-6974).
In California, call 415-656-5400.
-_-- -==
...-.. _- -. -
:r=:=:
~~
WS57C1911291
=:.......=-~=-ii-=
----~.-..
WAFERSrALE INTEGRATION. INC
HIGH SPEED 2K
x 8 CMOS RPROM™
KEY FEATURES
• Ultra-Fast Access Time
-
• Pin Compatible With AM27S191/291
and N82S191 Bipolar PROMs
45 ns
• Low Power Consumption
-
• Immune to Latch-Up
225 mW Active Power
-
up to 200 mA
• ESD Protection Exceeds 2000V
• Fast Programming
GENERAL DESCRIPTION
The WS57C191/291 is an extremely HIGH PERFORMANCE 16K UV Erasable Electrically Re-Programmable Read
Only Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM speeds
while consuming only 25% of the power of its Bipolar counterparts.
A further advantage of the WS57C191/291 over Bipolar PROM devices is the fact that it utilizes a proven EPROM
technology. This allows the entire memory array to be tested for switching characteristics and functionality after
assembly. Unlike devices which cannot be erased, every WS57C191/291 is 100% tested with worst case test patterns
both before and after assembly.
Another feature of the WS57C191/291 is its uniquely designed output structure. When compared with other high speed
devices, the output structure of the WS57C191/291 virtually eliminates the introduction of switch related noise into
the system environment.
The WS57C191/291 is configured in the standard Bipolar PROM pinout. The WS57C191 is offered in a 600 mil wide
Dip and the WS57C291 is offered in a 300 mil wide Dip. Both are offered in a Leadless Ceramic Chip Carrier.
PIN CONFIGURATION
A7
Vee
A7
A.
As
A.
As
A.
A.
A.
A.
A.
A.
A'D
A.
A'D
A3
A.
CS1N pp
A.
CSllVpp
A.
CS.
A.
cs.
A,
0
CS.
A,
CS 3
07
AD
07
00
0,
o.
o.
o.
o.
o.
o.
o.
O.
GND
03
AD
00
0,
GND
14' I 3 I 121 111 1281 -271 ~261
........... L .. J J .......... L ..
A.
-,
-.,
! ..
-.,
IJ
A,
-,
AD
~.J
! ..
-,
NC
~~
00
il'
_J
03
'- ~5
A,o
'"24
L.-
CS1/Vpp
ri3
'--
CS.
'L_
"22
r 21
L.
r20
riS
L_
L._
,...,,....,,.., r ' ,....,,....,,..,
CS3
NC
07
0.
1121 1131 1141 .151 116' 117' 118'
0,
TOP
r-
L.J
~..
0.
G
N
NC
0 3 0.
O.
0
PRODUCT SELECTION GUIDE
PARAMETER
WS57C191/291·45
WS57C191/291-55
Address Access Time (Max)
45 ns
55 ns
Output Enable Time (Max)
20 ns
30 ns
3-1
WS57C1911291
ABSOLUTE MAXIMUM RATINGS*
"Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65°C to +150°C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14.0V
ESD Protection ......................... >2000V
OPERA TING RANGE
Range
Temperature
Vcc
Comm'l.
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range. (See above)
SYMBOL
TEST CONDITIONS
PARAMETER
VOL
Output Low Voltage
IOL= 16mA
VOH
Output High Voltage
IOH=-4mA
Icc1
Vcc Active Current (CMOS)
Notes 1 and 3
MIN
MAX
UNITS
0.4
V
ICC2
2.4
Comm'l.
20
Military
30
Comm'l.
25
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
NOTES:
1)
2)
CMOS inputs: GND ± O::W or Vee ± O.3V.
TTL inputs: V1L .. O.av, V1H ,. 2.OV.
3)
Military
mA
35
p.A
A.C. Power component adds 3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
WS57C191/291-45
SYMBOL
MIN
WS57C191 1291-55
MIN
MAX
Address to Output Delay
tACC
45
55
CS to Output Delay
tcs
20
30
Output Disable to Output Float
tOF
20
30
Address to Output Hold
tOH
0
AC READ TIMING DIAGRAM
ADDRESSES
CS1Npp
=:>f...
OUTPUTS
UNITS
ns
0
TEST LOAD (High Impedance Systems)
98Q
VALID
... '
tACe
tOH
'\l.
~
:":~;~30PF
·
I=
(INCWDING SCOPE
AND JIG
CAPACITANCE)
/
Ie.
3-2
MAX
~
TIMING LEVELS
-
VALID
tDF
I--
Input Levels: 0 and
:w
Reference Levels: 1.5V
WS57C1911291
PROGRAMMING INFORMATION
DC CHARACTERISTICS
(TA=25 ± 5°C, Vee=5.50V ± 5%, Vpp= 13.5±0.5V)
PARAMETER
Input Leakage Current
V,N =Vcc or Gnd
Vpp Supply Current During
Programming Pulse
SYMBOLS
MIN
MAX
UNIT
III
-10
10
J-lA
60
mA
Vee Supply Current (Note 3)
Input Low Level
lec
V ,L
-0.1
Input High Level
V,H
2.0
Output Low Voltage During Verify
(loL = 16mA)
VOL
Output High Voltage During Verify
(IOH = -4mA)
VOH
Ipp
25
mA
0.8
V
Vee +0.3
v
0.45
V
2.4
V
NOTE: 5) Vpp must not be greater than 14 wits including overshoot.
AC CHARACTERISTICS
(TA=25 ± 5°C, Vee=5.50V ± 5%, Vpp= 13.5±0.5V)
PARAMETER
Address Setup Time
SYMBOLS
t AS
MIN
tOF
tos
tpw
2
Chip Disable Setup Time
Data Set Up
(Note 6)
Program Pulse Width
Data Hold Time
Chip Select Delay
tOH
tcs
tRF
V pp Rise and Fall Time
TYP
MAX
UNIT
30
f.ls
ns
10
f.ls
ms
30
f.ls
ns
2
3
1
2
1
f.ls
NOTE: 6) For programmers utilizing a one shot programming pulse. a 10 ms pulse width should be used.
PROGRAMMING WA VEFORM
X
VIH - - -......
ADDRESSES
V'L - - - - '
DATA :::
ADDRESS STABLE
,,------------------------
~tAs1
~_~
»---«
_ _ _D_AT._A_IN_ _ _ _ _....
~1
DATA OUT
~~
Vpp
CS2/CS3
3-3
WS57C1911291
PROGRAMMING
ERASURE
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C191/291 has all
2048 x 8 Bits in the "1," or high state. "O's" are loaded into
the WS57C191/291 through the procedure of programming.
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C191/291 to an ultra-violet
light source. A dosage of 15W-second/cm2 is required to completely erase a WS57C191/291.
Programming is performed by raising Vee to 5.75V, disabling
the outputs, addressing the byte to be programmed, presenting
the data to be programmed onto the data pins, and applying
a 13.5V pulse to the CS1Npp pin for 5 ms. The byte is then
verified by removing the input data and reading the programmed byte as in the read operation. A 0.1/1F capacitor
between Vpp and GND is needed to prevent excessive voltage
transients which could damage the device.
This dosage can be obtained by exposure to an ultra-violet lamp
(wavelength of 2537 Angstroms (A) ) with intensity of 12000/1
W/cm 2 for 15 to 20 minutes. The WS57C191/291 should be
about one inch from the source and all filters should be removed
from the UV light source prior to erasure.
PROGRAMMERS
Data 110 Unipak 2 or 2B, family/pinout code 7B/21; WSI's
MagicPro™ IBM PC Compatible Engineering Program.
It is important to note that the WS57C191/291 and similar
devices will erase with light sources having wavelengths shorter
than 4000A. Although erasure times will be much longer than
with UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C191/291 and exposure
to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
ORDERING INFORMATION
PART NUMBER
WS57C191-450
WS57C291-45T
WS57C191-550
WS57C291-55T
WS57C191-55CMB
WS57C191-550MB
WS57C291-55TMB
3-4
SPEED
PACKAGE
TYPE
(ns)
45
45
55
55
55
55
55
24
24
24
24
28
24
24
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
0.6"
0.3"
0.6"
0.3"
0.6"
0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
01
T1
01
T1
C1
01
T1
Comm'l
Comm'l
Comm'l
Comm'l
Military
Military
Military
Standard
Standard
Standard
Standard
MIL-STO-883C
MIL-STO-883C
MIL-STO-883C
:FEE , : - ----- - ~
WS57C1918/2918
=:"""Ii-ii=Ii-ii'= _E
~~.-r
PRELIMINARY
WAFERSCALE INTEGRA nON, INC.
HIGH SPEED 2K
X
8 CMOS RPROM™
KEY FEATURES
• Pin Compatible with AM27S191/291
and N82S191 Bipolar PROMs
• Immune to Latch-Up
• Ultra-Fast Access Time
-
35 ns
• Low Power Consumption
-
-
300 mW Active Power
• Fast Programming
up to 200 mA
• ESC Protection Exceeds 2000V
GENERAL DESCRIPTION
The WS57C191B/291B is an extremely HIGH PERFORMANCE 16K UV Erasable Electrically Re-Programmable Read
Only Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM speeds
while consuming only 25% of the power of its Bipolar counterparts.
A further advantage of the WS57C191B/291B over Bipolar PROM devices is the fact that it utilizes a proven EPROM
technology. This allows the entire memory array to be tested for switching characteristics and functionality after
assembly. Unlike devices which cannot be erased, every WS57C191B/291B is 100% tested with worst case test patterns
both before and after assembly.
The WS57C191B/291B is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for
systems which are currently using Bipolar PROMs.
PIN CONFIGURATION
A7
A7
Vee
A.
A,
A.
A,
A,
A.
A,
A.
A.
A.
A,o
A.
A,o
A,
A,
CS1IVpp
A,
CSlIVpp
A2
CS2
A2
CS2
A,
CS,
A,
CS,
AD
07
AD
07
00
0.
0.
0.
0,
0,
0,
0,
°2
0.
0.
°2
0,
GNO
GNO
• 4' • 3' • 2 I 11, '28, .271 .26'
L-..J .... ..J L..I I
A2
-,
I L...J L .....
'-..J
L.J
~.J
r-
I- ~5
-.,
! ..
-.,
ZJ
-,
CS1IVpp
r23
1--
CS2
-,
"2"2
L_
ri1
L_
NC
~:
li'
_J
.
00
A,
Ao
0,
! ..
!.J
~.,
r" ro.,,..,,,,,,...,
r20
r;;
L_
CS,
NC
°7
0.
112111311141.151116111711181
0,
TOP
r"""","'"
A,o
~i4
°2
G
N
0
NC
0,
0.
0,
PRODUCT SELECTION GUIDE
PARAMETER
WS57C191 8/291 8-35
WS57C191 8/291 8-45
Address Access Time (Max)
35 ns
45 ns
Output Enable Time (Max)
20 ns
20 ns
3-5
WS57C191B12918
ABSOLUTE MAXIMUM RATINGS"
-Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65°C to +150°C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14.0V
ESD Protection ......................... >2000V
OPERATING RANGE
Range
Temperature
Vee
Comm'l.
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range. (See above)
TEST CONDITIONS
PARAMETER
VOL
Output Low Voltage
IOL= 16mA
VOH
Output High Voltage
IOH=-4mA
Icc1
Vcc Active Current (CMOS)
Notes 1 and 3
MIN
MAX
UNITS
0.4
V
ICC2
2.4
30
Comm'l.
Military
35
Comm'l.
40
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
V1N = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
NOTES: 1) CMOS inputs: GND ± 0:311 or Vee ± 0.3\1.
2) TTL inputs: V1L .. O.av, V1H ~ 2.0V.
mA
40
Military
JJ.A
3) A.C. Power component adds 3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
WS57C191 B/291 B-35 WS57C191 B/291 B-45
SYMBOL
MIN
MIN
MAX
tACC
35
45
CS to Output Delay
tCE
20
20
Output Disable to Output Float
tOF
20
20
Address to Output Hold
tOH
Address to Output Delay
0
AC READ TIMING DIAGRAM
ADDRESSES~
...
OUTPUTS
UNITS
ns
0
TEST LOAD (High Impedance Systems)
9S0
VALtD
.,'
tACe
tcs
3-6
MAX
""
tOH
r--
-
/
2.0Wo----V--!
D.U.T·~30PF
I-=-
TIMING LEVELS
-
VALID
//
tOF
I-
Input Levels: 0 and W
Reference Levels: 1.5V
(INCWDING SCOPE
AND JIG
CAPACITANCE)
WS57C191B1291B
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA=25 ± 5°C, Vcc=5.50V ± 5%, Vpp= 13.5±0.5V)
PARAMETER
Input Leakage Current
V'N=Vcc orGnd
Vpp Supply Current During
Programming Pulse
SYMBOLS
MIN
MAX
UNIT
III
-10
10
}LA
60
mA
Vee Supply Current (Note 3)
Icc
V ,L
25
mA
-0.1
0.8
VIH
2.0
Vee +0.3
V
V
0.45
V
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL = 16mA)
Output High Voltage During Verify
(IOH = -4mA)
NOTES:
5) Vpp
Ipp
VOL
2.4
VOH
1.1
V
must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA=25 ± 5°C, Vee=5.50V ± 5%, Vpp= 13.5±0.5V)
PARAMETER
Address Setup Time
Chip Disable Setup Time
Data Set Up
Program Pulse Width (Note 6)
Data Hold Time
Chip Select Delay
Vpp Rise and Fall Time
SYMBOLS
t AS
MIN
2
tOF
tos
tpw
2
TYP
30
3
1
2
tOH
tcs
tRF
UNIT
p's
ns
p's
ms
p's
ns
p's
MAX
10
30
1
NOTES: 6) For programmers utilizing a one shot programming pulse, a 10ms pulse width should be used.
PROGRAMMING WA VEFORM
V,H - - - " '
ADDRESSES
DATA VIH
V,L
=>
ADDRESS STABLE
DATA IN
> <
~1
DATA OUT
~~
Vpp
V,H
CS1Npp
CS2/CS3
3-7
WS57C191B1291B
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C191B/291B has all
2048x8 bits in the "1," or high state. "O's" are loaded into the
WS57C191B/291B through the procedure of programming.
Programming is performed by raising Vee to 5.75V, disabling
the outputs, addressing the byte to be programmed, presenting the data to be programmed onto the data pins, and applying a 13.5V pulse to the CS1Npp pin for 5 ms. The byte is
then verified by removing the input data and reading the programmed byte as in the read operation. A 0.1 I1F capacitor
between Vpp and GND is needed to prevent excessive voltage
transients which could damage the device.
obtained by exposure to an ultra-violet lamp with wavelength
of 2537 Angstroms (A.) with intensity of 1200011 W/cm 2 for 15
or 20 minutes. The WS57C191B/291B should be about one inch
from the source and all filters should be removed from the UV
light source prior to erasure.
It is important to note that the WS57C191B/291B and similar
devices will erase with light sources having wavelengths shorter
than 4000A.. Although erasure times will be much longer than
with UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C191B/291B and exposure to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C191B/291B to an ultra-violet
light source. A dosage of 15W second/cm 2 is required to
completely erase a W557C191B/291B. This dosage can be
PROGRAMMERS
Data 110 Unipak 2 or 2B, software version 9 or later, familyl
pinout code 7B/21; WSI's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C191 B-35D
WS57C291 B-35T
WS57C191B-45CMB
WS57C191 B-45D
WS57C191B-45DMB
WS57C291B-45CMB
WS57C291 B-45T
WS59C291 B-45TMB
35
35
45
45
45
45
45
45
PACKAGE
TYPE
24
24
28
24
24
28
24
24
Pin CERDIp,
Pin CERDIp,
Pad CLLCC
Pin CERDIp,
Pin CERDIp,
Pad CLLCC
Pin CERDIp,
Pin CERDIp,
0.6"
0.3"
0.6"
0.6"
0.3"
0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
01
T1
C1
01
01
C1
T1
T1
Comm'l
Comm'l
Military
Comm'l
Military
Military
Comm'l
Military
Standard
Standard
MIL-STO-883C
Standard
MIL-STD-883C
MIL-STO-883C
Standard
MIL-STO-883C
===:=~
r.._ ____
_
--- -
------- --
WS57C45
-.-.~
ADVANCE INFORMATION
WAFERSCALE INTEGRA110N, INC.
HIGH-SPEED 2K x 8 REGISTERED CMOS RPROM™
KEY FEATURES
• Pin Compatible with AM27S45 and
CY7C245
• Ultra-Fast Access Time
-
20 ns Setup
10 ns Clock to Output
• Immune to Latch-Up
• Low Power Consumption
-
-
225 mW Active Power
up to 200 mA
• ESD Protection Exceeds 2000V
• Fast Programming
• Programmable Synchronous or
Asynchronous Output Enable
• Programmable Asynchronous
Initialize Register
GENERAL DESCRIPTION
The WS57C45 is an extremely HIGH PERFORMANCE 16K UV Erasable Registered CMOS RPROM. It is a direct
drop-in replacement for such devices as the AM27S45 and CY7C245.
To meet the requirements of systems which execute and fetch instructions simultaneously, an a-bit parallel data register
has been provided at the output which allows RPROM data to be stored while other data is being addressed.
An asynchronous initialization feature has been provided which allows a user programmable 2049th word to be placed
on the outputs independent of the system clock. This feature can be used to force an initialize word or provide a
preset or clear function.
A further advantage of the WS57C45 over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
This allows the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike
devices which cannot be erased, every WS57C45 is 100% tested with worst case test patterns both before and
after assembly.
PIN CONFIGURATION
Flatpack
CerDip
Vee
A7 ___
1
24
Vee
A.
A.C-
2
23
A.
As
A.
22
As
A,o
A,
4
21
A,o
A,
INIT
A,
5
20
A,
OEIOEs
A,
6
CP
A,
7
07
Ao
8
17
07
O.
00
9
16
O.
O.
0,
10
15
0.
0,
0,
11
14
0,
GND
12
13
03
0
19
18
INIT
OEIOEs
CP
TOP
PRODUCT SELECTION GUIDE
WS57C45-20
WS57C45-25
WS57C45-35
Address Access Time (Max)
PARAMETER
20 ns
25 ns
35 ns
Output Enable Time (Max)
10 ns
12 ns
15 ns
3-9
WS57C45
ABSOLUTE MAXIMUM RATINGS·
-Notice: Stresses above those listed here may
cause permanent damage to the device. This is a
stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposureto absolute
maximum rating conditions for extended periods of
time may affect device reliability.
Storage Temperature .......... -65°C to +150°C
Voltage on any pin with
respect to GND ...•.•............... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14.0V
ESD Protection ......................... >2000V
OPERATING RANGE
Range
Temperature
Vee
Comm'l.
0° to +70°C
+5V± 5%
Military
-55° to +125°C
+5V ± 10%
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range. (See above)
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL= 16mA
VOH
Output High Voltage
IOH=-4mA
ICCl
Vcc Active Current (CMOS)
Notes 1 and 3
MIN
MAX
UNITS
0.4
V
ICC2
2.4
Comm'l.
20
Military
30
Comm'l.
25
Vee Active Current (TTL)
Notes 2 and 4
ILl
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
NOTES:
CMOS inputs: GND ± O.3V or Vcc ± O.3V.
2) TTL inputs: VILS;O.8V, VIH<::2.0V.
1)
Military
mA
35
IJ.A
3) A.C. Power component adds 2 mAMHz.
4) A.C. Power component adds 3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
Address Setup to Clock HIGH
SYMBOL
WS57C45-20
WS57C45-25
WS57C45-35
MIN
MIN
MIN
MAX
M.AX
tSA
20
25
35
tHA
0
0
0
Clock Pulse Width
tco
tpwc
12
15
20
OEs Setup to Clock HIGH
tSOES
10
12
15
OEs Hold From Clock HIGH
tHOES
5
Address Hold From Clock HIGH
Clock HIGH to Valid Output
Delay From INIT to Valid Output
INIT Recovery to Clock HIGH
INIT Pulse Width
Active Output From Clock HIGH
12
5
20
tDI
tRI
15
15
15
15
Inactive Output From Clock HIGH
Active Output From OE LOW
t LZOE
Inactive Output From OE HIGH
tHzOE
..
UNITS
15
5
20
tPWI
tLZc
t HZC
3-10
10
MAX
ns
20
20
20
15
15
20
15
15
20
15
15
20
15
15
20
WS57C45
TEST LOAD (High
TIMING LEVELS
Impedance Systems)
97.5Q
Input Levels: 0 and 3V
2.01V~
D.U.T.
I-=-
Reference Levels: 0.8 and 2.0V
30pF
(INCWDING SCOPE
AND JIG
CAPACITANCE)
AC READ TIMING DIAGRAM
~~l·
__________________________ __ ____+-__
~
~~
~~~~OO~
______________
D
OEs _ _ _ _....LJUj
CP
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C45 to an ultra-violet light
source. A dosage of 15W second/cm2 is required to completely
erase a WS57C45. This dosage can be obtained by exposure
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 12000~ W/cm 2 for 15 to 20 minutes. The
WS57C45 should be about one inch from the source and all
filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS57C45 and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C45 and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
PROGRAMMERS
Data 1/0 Unipak 2 or 2B; WSI's MagicPro™ IBM PC Compatible Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C45-2OT
WS57C45-25FMB
WS57C45-25T
WS57C45-25TMB
WS57C45-35FMB
WS57C45-35T
WS57C45-35TMB
SPEED
PACKAGE
TYPE
(ns)
20
25
25
25
35
35
35
24
24
24
24
24
24
24
Pin
Pin
Pin
Pin
Pin
Pin
Pin
CERDIp,
Ceramic
CERDIp,
CERDIp,
Ceramic
CERDIp,
CERDIp,
0.3"
Flatpack
0.3"
0.3"
Flatpack
0.3"
0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
T1
F1
T1
T1
F1
T1
T1
Comm'l
Military
Comm'l
Military
Military
Comm'l
Military
Standard
MIL-STD-883C
Standard
MIL-STD-883C
MIL-STO-883C
Standard
MIL-STO-883C
3·11
3·12
WS57C43
WAFERSCALE INTEGRA1l0N, INC
HIGH SPEED 4K x 8 CMOS RPROM™
KEY FEATURES
• Pin Compatible with AM27S43,
MB7142 and 82S321 Bipolar PROMs
• Ultra-Fast Access Time
-
55 ns
• Low Power Consumption
-
• Immune to Latch-Up
225 mW Active Power
-
Up to 200 mA
• ESD Protection Exceeds 2000V
• Fast Programming
GENERAL DESCRIPTION
The WS57C43 is an extremely HIGH PERFORMANCE 32K UV Erasable Electrically Re-Programmable
Read Only Memory. It is manufactured in an advanced CMOS technology which allows it to operate at
Bipolar PROM speeds while consuming only 25% of the power of its Bipolar counterparts.
A further advantage of the WS57C43 over Bipolar PROM devices is the fact that it utilizes a proven
EPROM technology. This allows the entire memory array to be tested for switching characteristics and
functionality after assembly. Unlike devices which cannot be erased, every WS57C43 is 100% tested
with worst case test patterns both before and after assembly.
Another feature of the WS57C43 is its uniquely designed output structure. When compared with other
high speed devices, the output structure of the WS57C43 virtually eliminates the introduction of switch
related noise into the system environment.
The WS57C43 is configured in the standard Bipolar PROM pinout. Packaging options include both 300
and 600 mil wide Dips as well as a Leadless Chip Carrier.
PIN CONFIGURATION
As
A7
Vee
A.
A.
As
A.
A_
A_
A,.
A.
A.
CS1/Vpp
A.
A,
0
A.
A.
A11
A,
CS.
r 25
L_ A,.
..,
:!J
"24
L..
ri3
L.
! ...
"22 CS.
L.
! ...
. .,
-,
-,
9 •
NC
0,
o.
o.
~J
o.
0_
0.
il'
• J
GND
NC Vee A.
L.J
~ ....
A.
o.
A7
.,
07
A.
A.
14. I 3 I 121 11 I 1281 .271 ~261
... ...1 ... ...1 L .... 1 I ............. L ....
r 21
L.
• ...1
r20
L..
r;g
~.,~..,
r-,
,..,r,r""r., L.
CS1IVpp
A11
NC
07
0•
'12' 1131 '14' ,15' '16' 117' '18'
O.
0,
O.
TOP
G
N
D
Ne
0. 0_
0.
PRODUCT SELECTION GUIDE
WS57C43·55
WS57C43·70
Address Access Time (Max)
55ns
70ns
Output Enable Time (Max)
25ns
30ns
PARAMETER
3-13
WS57C43
ABSOLUTE MAXIMUM RATINGS"
"Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65° C to +150° C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14.0V
ESD Protection ......................... >2000V
OPERA TING RANGE
Range
Temperature
Vee
Comm'l.
0° to +70°C
+5V ± 5%
Military
-55° to+125°C
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range. (See above)
SYMBOL
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL= 16mA
VOH
Output High Voltage
IOH= -4mA
ICCl
Vcc Active Current (CMOS)
Notes 1 and 3
MIN
MAX
UNITS
0.4
V
ICC2
2.4
Comm'l.
20
Military
30
Comm'l.
25
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
NOTES: 1) CMOS inputs: GND ± Q,3V or Vee ± Q,3V,
2) TTL inputs: V1L " Q,aV, V1H '" 2,QV,
3)
Military
mA
35
JlA
A,C, Power component adds 3 rnA/MHz,
AC READ CHARACTERISTICS Over operating Range. (See above)
PARAMETER
WS57C43-55
MAX
MIN
SYMBOL
Address to Output Delay
t CS
55
25
Output Disable to Output Float
t DF
25
Address to Output Hold
t OH
t ACC
CS to Output Delay
0
WS57C43-70
MIN
MAX
70
30
30
UNITS
ns
0
TEST LOAD (High Impedance Systems)
AC READ TIMING DIAGRAM
980
ADDRESSES
~<-"4===tV.::AL;ID-===:::;~j1]('-----/
T·
'-1
t Aee
..
CS1--------------~,
_ _ _ __
tOH
_
I
:::~;,~
~30PF
I-=-
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
~r_-_+_--.//
tes
OUTPUTS
3-14
I-
----------~,E.,a~VA~L~IDdjz~tOF I--
TIMING LEVELS
Input Levels: 0 and 3V
Reference Levels: 1.5V
WS57C43
PROGRAMMING INFORMA TION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.50V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
Input Leakage Current
VIN = Vee or Gnd
SYMBOLS
MIN.
MAX.
UNIT
III
-10
10
IJ,A
60
mA
25
mA
Vpp Supply Current During
Programming Pulse
Ipp
Vee Supply Current (Notes 2 and 3)
lee
Input Low Level
Vil
-0.1
0.8
V
Input High Level
VIH
2.0
Vee +0.3
V
Output Low Voltage During Verify
(IOl = 16mA)
VOL
0.45
V
Output High Voltage During Verify
(IOH = -4mA)
VOH
2.4
V
NOTE: 5) Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.50V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN.
Address Setup Time
tAs
2
Chip Disable Setup Time
toF
Data Setup
tos
2
Program Pulse Width
MAX.
UNIT
IJ,S
30
ns
IJ,S
tpw
5
ms
Data Hold Time
toH
2
IJ,S
Chip Select Delay
tcs
Vpp Rise and Fall Time
tRF
30
ns
1
IJ,S
PROGRAMMING WA VEFORM
V,H
ADDRESSES
X
----..
V,L _ _ _oJ
DATA
,H
V
V,L
vpp
ADDRESS STABLE
....- - - - - - - - - - - - - - - - - - - - - - -
~tAS~
--........>---«
~
DATA
IN
> <
r~~ ~s~
DATA OUT
....
-------------
V,H
CS1N pp
V'L
V,H
CS.
V,L
3-15
WS57C43
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C43 has all 4096x8
bits in the "1:' or high state. "O's" are loaded into the WS57C43
through the procedure of programming.
Programming is performed by raising Vee to 5.75V, disabling
the outputs, addressing the byte to be programmed, presenting the data to be programmed onto the data pins, and applying a 13.5V pulse to the CS1/vpp pin for 5 ms. The byte is then
verified by removing the input data and reading the programmed byte as in the read operation. A 0.1 I-IF capacitor
between V pp and GND is needed to prevent excessive voltage
transients which could damage the device.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C43 to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS57C43. This dosage can be obtained by exposure
to an ultra-violet lamp with wavelength of 2537 Angstroms (A.)
with intensity of 120001-1 W/cm 2 for 15 to 20 minutes. The
WS57C43 should be about one inch from the source and all
filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS57C43 and similar devices
will erase with light sources having wavelengths shorter than
4000A.. Although erasure times will be much longer than with
UV sources at 2537A., the exposure to fluorescent light and
sunlight will eventually erase the WS57C43 and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
ORDERING INFORMATION
PART NUMBER
WS57C43-550
WS57C43-55T
WS57C43-70CMB
WS57C43-700
WS57C43-700M
WS57C43-700MB
WS57C43-7OT
WS57C43-7OTM
WS57C43-7OTMB
3-16
SPEED
PACKAGE
TYPE
(ns)
55
55
70
70
70
70
70
70
70
24
24
28
24
24
24
24
24
24
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
PACKAGE
DRAWING
0.6"
0.3"
0.6"
0.6"
0.6"
0.3"
0.3"
0.3"
01
T1
C1
01
01
01
T1
T1
T1
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
Comm'l
Comm'l
Military
Comm'l
Military
Military
Comm'l
Military
Military
Standard
Standard
MIL-STO-883C
Standard
Standard
MIL-STO-883C
Standard
Standard
MIL-STO-883C
== --== .:::...E:
--=r ...
---'iI_i-;
__
-i'= ==
---- ---...
~
WS57C43B
~~
PRELIMINARY
WAFERsrALE INTEGRA770N, INC.
HIGH SPEED 4K x 8 CMOS RPROM™
KEY FEATURES
• Pin Compatible with AM27S43 and
N82S321 Bipolar PROMs
• Immune to Latch-Up
• Ultra-Fast Access Time
-
35 ns
• Low Power Consumption
-
-
300 mW Active Power (20 MHz)
• Fast Programming
up to 200 mA
• Available in 300 Mil Dip
GENERAL DESCRIPTION
The WS57C43B is an extremely HIGH PERFORMANCE 32K UV Erasable Electrically Re-Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM speeds
while consuming only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C43B over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
This allows the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike
devices which cannot be erased, every WS57C43B is 100% tested with worst case test patterns both before and
after assembly.
The WS57C43B is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for systems
which are currently using Bipolar PROMs. It also uses the same programming algorithm as its predecessor the
WS57C43.
PIN CONFIGURATION
A7
Vee
A7
A.
A.
As
23
A.
As
A"
As
22
A.
A.
A,.
A.
21
A'D
A_
CS1Npp
A_
20
CS1Npp
A"
A.
A,
CS.
A,
Ao
07
AD
00
As
Vee
0
A.
A_
A.
19
A"
18
CS.
A,
17
07
AD
o.
00
16
o.
0,
Os
0,
15
Os
O.
0.
o.
14
O.
A.
GND
0_
GND
13
0_
NC
00
A.
A7
NC Vee A.
Ag
.41 1 3 I 121 111 12811271 _261
... ...1 ... ...1 L.J I I L.JL.J L.J
L.J
r 25
-,
~.J
~-
! ...
"24
L-
CS1Npp
!J
r23
~-
A"
-,
-,
-,
A,.
! ...
-,
!J
"22
L_ CS.
io'
_J
n'
_J
,..., ... .,,...,
riO
L_
r19
L_
r 21
L_
r-,
NC
07
o.
,..,r~,....,
1121 1131 1141 .151 11611171 1181
0,
0.
TOP
G
N
D
NC
0_
O.
Os
PRODUCT SELECTION GUIDE
PARAMETER
WS57C43B-35
WS57C43B-45
WS57C43B-55
Address Access Time (Max)
35 ns
45 ns
55 ns
Output Enable Time (Max)
20 ns
25 ns
25 ns
3-17
WS57C43B
ABSOLUTE MAXIMUM RA TINGS*
-Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65° C to +150° C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14:0V
ESD Protection ......................... >2000V
OPERATING RANGE
Range
Temperature
Vce
Comm'l.
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range. (See above)
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL= 16mA
VOH
Output High Voltage
IOH= -4mA
ICCl
Vcc Active Current (CMOS)
Notes 1 and 3
MIN
MAX
UNITS
0.4
V
ICC2
2.4
Comm'l.
30
Military
35
40
Comm'l.
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
NOTES: 1) CMOS inputs: GND ±
O.3V or Vee
2) TIL inputs: V 1L .. O.BV, V 1H ;lo 2.0V.
±
O.3V.
mA
40
Military
p.A
3) A.C. Power component adds 3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
WS57C43B-35
SYMBOL
MIN
MAX
WS57C43B-45
MIN
MAX
WS57C43B-55
MIN
MAX
Address to Output Delay
tACC
35
45
55
CS to Output Delay
tcs
20
25
25
Output Disable to Output Float
tDF
20
25
25
Address to Output Hold
tOH
0
0
UNITS
ns
0
TEST LOAD (High Impedance Systems)
AC READ TIMING DIAGRAM
980
ADDRESSES~
.
VALID
tI'
lACe
IOH
\J.
""
-
3-18
(INCWDING SCOPE
AND JIG
CAPACITANCE)
/
TIMING LEVELS
leo
OUTPUTS
:::~;~
~30PF
I-=-
-
VALID
//
IOF
i--
Input Levels: 0 and 3V
Reference Levels: 1.5V
WS57C43B
PROGRAMMING INFORMA TION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.50V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN.
MAX.
UNIT
III
-10
10
fJ.A
Input Leakage Current
VIN = Vee or Gnd
Vpp Supply Current During
Programming Pulse
Ipp
60
mA
Vee Supply Current (Notes 2 and 3)
Icc
30
mA
Input Low Level
VIL
-0.1
0.8
V
Input High Level
VIH
2.0
Vee +0.3
V
Output Low Voltage During Verify
(IOL = 16mA)
VOL
0.45
V
Output High Voltage During Verify
(IOH ~ -4mA)
VOH
2.4
II
V
NOTE: 5) Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN.
Address Setup Time
tAS
2
Chip Disable Setup Time
tOF
Data Setup
los
2
Program Pulse Width
tpw
1
2
Data Hold Time
tOH
Chip Select Delay
tes
Vpp Rise and Fall Time
tRF
TYP.
MAX.
UNIT
fJ.s
3
30
ns
10
fJ.S
ms
fJ.S
30
ns
1
fJ.s
NOTE: A single shot programming algorithm should use one 10ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
X
V,H - - -....
_
•
V ,L _ _ _J
....
DATA V,H
V,L
r-- --1---------------------~
>>----«
ADDRESS STABLE
t AS
DATA IN
_
DATA OUT
-~-----------.
~1
~~
Vpp
V,H
CS1Npp
V,L
I
tRF
tRF
V,H
Cs,
V,L
3·19
WS57C43B
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C43B has all4096x8
bits in the "1," or high state. "O's" are loaded into the
WS57C43B through the procedure of programming.
Programming is performed by raising Vee to 5.5V, disabling
the outputs, addressing the byte to be programmed, presenting the data to be programmed onto the data pins, and applying a 13.5V pulse to the CS1Npp pin for 5 ms. The byte is
then verified by removing the input data and reading the programmed byte as in the read operation. A 0.1 I1F capacitor
between Vp p and GND is needed to prevent excessive voltage
transients which could damage the device.
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intenSity of 1200011 W/cm 2 for 15 to 20 minutes. The
WS57C43B should be about one inch from the source and all
filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS57C43B and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A. the exposure to fluorescent light and
sunlight will eventually erase the WS57C43B and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C43B to an ultra-violet light
source. A dosage of 15W secondtcm 2 is required to completely
erase a WS57C43B. This dosage can be obtained by exposure
PROGRAMMERS
Data 110 Unipak 2 or 2B, software version 11 or later, familyl
pinout code 7B/63; WSl's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C43B-350
WS57C43B-35T
WS57C43B-45CMB
WS57C43B-450
WS57C43B-450MB
WS57C43B-45T
WS57C43B-45TMB
WS57C43B-55CMB
WS57C43B-550
WS57C43B-550MB
WS57C43B-55T
WS57C43B-55TMB
35
35
45
45
45
45
45
55
55
55
55
55
3-20
PACKAGE
TYPE
24
24
28
24
24
24
24
28
24
24
24
24
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
0.6"
0.3"
0.6"
0.6"
0.3"
0.3"
0.6"
0.6"
0.3"
0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
01
T1
C1
01
01
T1
T1
C1
01
01
T1
T1
Comm'l
Comm'l
Military
Comm'l
Military
Comm'l
Military
Military
Comm'l
Military
Comm'l
Military
Standard
Standard
MIL-STO-883C
Standard
MIL-STO-883C
Standard
MIL-STO-883C
MIL-STO-883C
Standard
MIL-STO-883C
Standard
MIL-STO-883C
WS57C49
WAFERSCALE INTEGRA 110N, INC.
HIGH SPEED BK x 8 CMOS RPROM™
KEY FEATURES
• Very-Fast Access Time
-
• Pin Compatible with AM27S49
and MB7144 Bipolar PROMs
55 ns
• Low Power Consumption
-
• Immune to Latch-Up
300 mW Active Power (Full Speed)
-
• Fast Programming
up to 200 rnA
• Commercial and Military Availability
GENERAL DESCRIPTION
The WS57C49 is an extremely HIGH PERFORMANCE 64K UV Erasable Electrically Re-Programmable Read Only
Memory. It is specifically designed to replace bipolar PROMs in existing applications.
An advantage of the WS57C49 over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
This allows the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike
devices which cannot be erased, every WS57C49 is 100% tested with worst case test patterns both before and after
assembly.
The WS57C49 is manufactured using WSl's patented CMOS EPROM technology which allows it to operate at Bipolar
PROM speeds while consuming only 25% of the power required by its Bipolar counterparts.
The WS57C49 is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for systems
which are currently using Bipolar PROMs.
PIN CONFIGURATION
A.
A7
Vee
A.
A.
As
A.
A.
A.
A,.
A,
A,
CS1/Vpp
A.
A"
A,
A,.
A,
A,.
A.
07
o.
o.
0,
0.
0.
0.
GND
0,
As
A7
NC Vee A.
As
14- I 3 I 121 111 1281.27t _26_
... oJ ... ..J L..J I I L-IL-I L..J
L.J
r
-,
~..1
25
L.
A,o
! ..
~2j
CS1IVpp
lJ
-,
! ..
f"23
L_
A"
22
L_
A,.
r 21
NC
~~
~~
0.
-.,
. .,
Ao
-.,
9 .
NC
~J
00
~J
r
L•
• .J
r-..,
r- .....
0,
0.
r., r'" r-,r-,,.."'I
°7
1121 1131 1141 -15' 11611171 118'
~
NC
0, 0.
0.
D
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C49-55
WS57C49-70
Address Access Time (Max)
55 ns
70 ns
Output Enable Time (Max)
20 ns
25 ns
3-21
WS57C49
ABSOLUTE MAXIMUM RATINGS*
·Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65° C to +150° C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14.0V
ESD Protection ......................... >2000V
OPERA TING RANGE
Range
Temperature
Vee
Comm'l.
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range. (See above)
SYMBOL
TEST CONDITIONS
PARAMETER
VOL
Output Low Voltage
IOL= 16mA
VOH
Output High Voltage
IOH= -4mA
ICC1
Vcc Active Current (CMOS)
Notes 1 and 3
MIN
MAX
UNITS
0.4
V
2.4
Comm'l.
20
Military
30
Comm'l.
25
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
ICC2
NOTES:
1) CMOS inputs: GND ± 0.31/ or Vee
2) TIL inputs: V1L ., O.BV, V 1H ~ 2.0V.
±
0.31/.
3)
AC Power
Military
mA
35
p,A
component adds 3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
WS57C49·55
SYMBOL
MIN
MAX
WS57C49·70
MIN
Address to Output Delay
tACC
55
70
CS to Output Delay
tcs
20
25
Output Disable to Output Float
tDF
20
25
Address to Output Hold
tOH
10
UNITS
MAX
ns
10
TEST LOAD
AC READ TIMING DIAGRAM
(High Impedance Test Systems)
980
ADDRESSES
~<-;==:t'l:;~L-;ID-==:::::;;;-:j:i]('-_ _ _ __
..
----J
T....
~
lACe
'-1
IOH
_
les
D.U.T.~ 30pF
I-=-
CS - - - - - - - - - . . , I
>1.1"--_+----"/
OUTPUTS
2.01V~
(INCWDING SCOPE
AND JIG.
CAPACITANCE)
~
---------~~~vA~L~ID11:t;~-
IOF
~
TIMING LEVELS
Input Levels: 0 and
:w
Reference Levels: 1.5V
3-22
WS57C49
PROGRAMMING INFORMA TION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN.
MAX.
UNIT
III
-10
10
p.A
60
mA
25
rnA
Input Leakage Current
V,N = Vee or Gnd
Vpp Supply Current During
Programming Pulse
Vee Supply Current (Note 3)
lee
Input Low Level
V,L
-0.1
0.8
V
Input High Level
V,H
2.0
Vee+0.3
V
Output Low Voltage During Verify
(IOL = 16mA)
VOL
0.45
V
Output High Voltage During Verify
(IOH = -4mA)
VOH
Ipp
2.4
V
NOTE: 5) Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA
= 25
± 5°C, Vee
PARAMETER
= 5.5V
± 5%, Vpp
SYMBOLS
MIN.
Address Setup Time
lAs
2
Chip Disable Setup Time
loF
Data Setup
los
tpw
2
Program Pulse Width
Data Hold Time
tOH
2
Chip Select Delay
tes
Vpp Rise and Fall Time
tRF
= 13.5
± 0.5V)
TYP.
MAX.
UNIT
30
P.s
ns
P.s
1
3
10
rns
30
P.s
ns
1
P.s
NOTE: A single shot programming algorithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
V,H
ADDRESSES
V'L
DATA VIH
V'L
X
ADDRESS STABLE
~IAS1
=> <
-- IOF --
los
V__
DATA IN
> <
'"1
DATA OUT
~~
V,H
CS/V __
V'L
3·23
WS57C49
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C49 has all 8192x8
bits in the "1," or high state. "O's" are loaded into the WS57C49
through the procedure of programming.
Programming is performed by raiSing Vee to 5.5V, disabling
the outputs, addressing the byte to be programmed, presenting the data to be programmed onto the data pins, and applying a 13.5V pulse to the CSNpp pin for 5 ms. The byte is then
verified by removing the input data and reading the programmed byte as in the read operation. A 0.1 I1F capacitor
between V pp and GND is needed to prevent excessive voltage
transients which could damage the device.
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 1200011 W/cm 2 for 15 to 20 minutes. The
WS57C49 should be about one inch from the source and all
filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS57C49 and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C49 and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C49 to an ultra-violet light
source. A dosage of 15W second/cm2 is required to completely
erase a WS57C49. This dosage can be obtained by exposure
PROGRAMMERS
Data 110 Unipak 2 or 2B, software version 9 or later, familyl
pinout code 3Clffl; WSl's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C49-55D
WS57C49-70CMB
WS57C49-700
WS57C49-700MB
3-24
SPEED
(ns)
55
70
70
70
PACKAGE
TYPE
24
28
24
24
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
Pin CEROIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
01
C1
01
01
Comm'l
Military
Comm'l
Military
Standard
MIL-STD-883C
Standard
MIL-STO-883C
iFEE ==:
--.. _--~
-
WS57C49B
_
.-r _
f
' -_
.-~:=
---~~
PRELIMINARY
WAFERSCALE INTEGRATION, INC.
HIGH SPEED BK x B CMOS RPROM™
KEY FEATURES
• Ultra-Fast Access Time
-
• Pin Compatible with AM27S49 and
MB7144 Bipolar PROMs
• Immune to Latch-Up
35 ns
• Low Power Consumption
-
300 mW Active Power (20 MHz)
-
Up to 200 mA
• ESD Protection Exceeds 2000V
• Fast Programming
GENERAL DESCRIPTION
The WS57C49B is an extremely HIGH PERFORMANCE 64K UV Erasable Electrically Re-Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM speeds
while consuming only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C49B over Bipolar PROM devices is the fact that it utilizes a proven EPROM technology.
This allows the entire memory array to be tested for switching characteristics and functionality after assembly. Unlike
devices which cannot be erased, every WS57C49B is 100% tested with worst case test patterns both before and
after assembly.
A unique feature of the WS57C49B is a designed-in output hold from address change. This allows the WS57C49B
to be run at a cycle time equal to the address access time. While addresses are changing, output data is held long
enough to be latched into external circuitry.
The WS57C49B is configured in the standard Bipolar PROM pinout which provides an easy upgrade path for systems
which are currently using Bipolar PROMs.
PIN CONFIGURATION
A7
Vee
A7
Vee
A.
A.
A.
As
A.
A"
A.
A.
A.
A.
A'D
A.
A'D
A3
A3
CS1N pp
A3
CS1/V pp
A.
Al1
A2
A,
A2
0
Al1
A,
A'2
AD
07
AD
07
00
0.
00
0.
0,
0.
0,
O.
0.
°2
O2
GND
03
14' I 3 I 121 111 1281 ~271 '26'
L....J 1....1 L ... I 1L. ... L....i L..J
A'2
O.
03
GND
A,
Ao
NC
00
.,
~...
r·
L.J
L~5 A'D
. .,
.!L..
-.,
ZJ
~~
CS1/Vpp
r 23
L_
Al1
! ...
'-22
L_
A'2
9 •
r 21
NC
~J
I..
rio
°7
• .J
r19
L_
0•
-,
-,
L.
• .J
;;,
... .., ... . . . r,
r..,r-..,r- ..... ,...,
1121 113' 114' 1151 116 1 1171 118'
0,
°2
G
N
NC
0 3 0.
0.
0
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C49B-35
WS57C49B-45
WS57C49B-55
Address Access Time (Max)
35 ns
45 ns
55 ns
Output Enable Time (Max)
20 ns
25 ns
25 ns
3-25
WS57C49B
ABSOLUTE MAXIMUM RATINGS·
-Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only.and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65°C to +150°C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14.0V
ESD Protection ......................... >2000V
OPERATING RANGE
Range
Temperature
Vec
Comm'l.
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range. (See above)
SYMBOL
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL= 16mA
VOH
Output High Voltage
IOH=-4mA
leel
Vcc Active Current (CMOS)
Notes 1 and 3
MIN
MAX
UNITS
0.4
V
2.4
Comm'l.
30
Military
35
40
40
Comm'l.
Vee Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
ICC2
NOTES:
1) CMOS inputs: GND ± O.3V or Vee
2) TTL inputs: V 1L .. O.BV, V1H ;. 2.0V.
± O.3V.
Military
mA
p.A
3) A.C. Power component adds 3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
WS57C49B-35
PARAMETER
SYMBOL
Address to Output Delay
MAX
MIN
WS57C49B-45
MIN
MAX
WS57C49B-55
MIN
tACC
35
45
55
CS to Output Delay
tcs
20
25
25
Output Disable to Output Float
tOF
20
25
25
Address to Output Hold
tOH
0
0
UNITS
MAX
ns
0
TEST LOAD
AC READ TIMING DIAGRAM
(High Impedance Test Systems)
980
ADDRESSES
~...
.'~
VALID
tACe
cs
\J.
3-26
tOH
I--
o----I\J"-i
D.U.T·~30PF
I-=-
(INCWDING SCOPE
AND JIG
CAPACITANCE)
/
tes
OUTPUTS
2.01V
~
-
TIMING LEVELS
VALID
tD•
f.--
Input Levels: 0 and ':N
Reference Levels: 1.5V
WS57C49B
PROGRAMMING INFORMA TION
DC CHARACTERISTICS (T A
= 25 ±
5°C, Vee
PARAMETER
= 5.50V ± 5%,
Vpp
= 13.5 ± 0.5V)
SYMBOLS
MIN.
MAX.
UNIT
III
-10
10
/J. A
60
mA
Input Leakage Current
VrN = Vee or Gnd
Vpp Supply Current During
Programming Pulse
Vee Supply Current (Notes 2 and 3)
Icc
35
mA
Input Low Level
Vrl
-0.1
0.8
V
Input High Level
VrH
2.0
Vee+0.3
V
Output Low Voltage During Verify
(IOl = 16mA)
VOL
0.45
V
Output High Voltage During Verify
(lOH = -4mA)
VOH
Ipp
2.4
V
NOTE: 5) Vpp must not be greater than 14 vorts including overshoot.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN.
Address Setup Time
tAS
2
Chip Disable Setup Time
IoF
Data Setup
los
2
Program Pulse Width
tpw
1
2
Data Hold Time
tOH
Chip Select Delay
tes
Vpp Rise and Fall Time
tRF
TYP.
3
MAX.
UNIT
30
/J.S
ns
10
/J.s
ms
/J.s
30
1
ns
/J.s
NOTES: A single shot programming algorithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
V,H
ADDRESSES
V,L
X
ADDRESS STABLE
~tAS1
DATA VIH
V,L
=> <
-- tOF --
' -_________D~_~_A_rN___________
~>----~~
~1
~~OUT
~~
Vpp
V,H
CSNpp
V,L
3-27
WS57C49B
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C49B has all 8192x8 .
bits in the "1:' or high state. "O's" are loaded into the
WS57C49B through the procedure of programming.
Programming is performed by raising Vee to 5.5V, disabling
the outputs, addressing the byte to be programmed, presenting the data to be programmed onto the data pins, and applying a 13.5V pulse to the CS1Npp pin for 5 ms. The byte is
then verified by removing the input data and reading the programmed byte as in the read operation. A 0.1 IlF capacitor
between Vpp and GND is needed to prevent excessive voltage
transients, which could damage the device.
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 120001l W/cm 2 for 15 to 20 minutes. The
WS57C49B should be about one inch from the source and all
filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS57C49B and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C49B and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C49B to an ultra-violet light
source. A dosage of 15W second/cm2 is required to completely
erase a WS57C49B. This dosage can be obtained by exposure
PROGRAMMERS
Data 1/0 Unipak 2 or 2B, software version 9 or later, familyl
pinout code 3C/01; WSl's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C49B-350
WS57C49B-35T
WS57C49B-45CMB
WS57C49B-450
WS57C49B-450MB
WS57C49B-45FMB
WS57C49B-45T
WS57C49B-45TMB
WS57C49B-55CMB
WS57C49B-550MB
WS57C49B-55FMB
WS57C49B-55T
WS57C49B-55TMB
3-28
SPEED
PACKAGE
TYPE
(ns)
35
35
45
45
45
45
45
45
55
55
55
55
55
24
24
28
24
24
24
24
24
28
24
24
24
24
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pin Flatpack
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CEROIp,
Pin Flatpack
Pin CEROIp,
Pin CEROIp,
PACKAGE
DRAWING
0.6"
0.3"
0.6"
0.6"
0.3"
0.3"
0.6"
0.3"
0.3"
01
T1
C1
01
01
F1
T1
T1
C1
01
F1
T1
T1
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
Comm'l
Comm'l
Military
Comm'l
Military
Military
Comm'l
Comm'l
Military
Military
Military
Comm'l
Military
Standard
Standard
MIL-STO-883C
Standard
MIL-STO-883C
MIL-STO-883C
Standard
M IL-STO-883C
MIL-STO-883C
MIL-STO-883C
MIL-STO-883C
Standard
MIL-STO-883C
iF===~
r====::=_
r
WS57C51
. . . ~...,==
~~~ ~
-----------------------------------------------------------------
WAFERS(,ALE INTEGRATION. INC
HIGH SPEED 16K x 8 CMOS RPROM™
KEY FEATURES
• Ultra-Fast Access Time
-
• Pin Compatible with AM27S51
70 ns
• Immune to Latch-Up
• Low Power Consumption
-
-
200 mW Active Power (10 MHz)
• Fast Programming
Up to 200 mA
• ESD Protection Exceeds 2000V
GENERAL DESCRIPTION
The WS57C51 is an extremely High Performance 128K UV Erasable electrically Re-Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM
speeds while consuming only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C51 over Bipolar PROM devices is the fact that it utilizes a proven EPROM
technology. This allows the entire memory array to be tested for switching characteristics and functionality after
assembly. Unlike devices which cannot be erased, every WS57C51 is 100% tested with worst case test patterns
both before and after assembly.
The WS57C51 provides a low power alternative to those designs which are committed to a bipolar PROM
footprint. It is a direct drop-in replacement for a bipolar PROM of the same architecture (16K x 8). No software,
hardware or layout changes need be performed.
The WS57C51 is configured in the standard Bipolar PROM pinout which provides an easy crossover path for
systems which are currently using Bipolar PROMs.
PIN CONFIGURATION
Vee
A"
An
A12
A"
A,
CS1Npp
A,
CS2
A,
CS3
A,
CS4
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C51-70
Address Access Time (Max)
70 ns
Output Enable Time (Max)
25 ns
3-29
W$57C51
ABSOLUTE MAXIMUM RA TINGS*
*Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65 C to +150° C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -O.6V to +14.0V
ESD Protection ......................... >2000V
0
OPERATING RANGE
TEMPERATURE
Vcc
+5V ± 5%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
VOL
Output Low Voltage
IOL = 16 mA
VOH
Output High Voltage
IOH = -4 mA
Icc1
Vcc Active Current (CMOS)
Notes 1 and 3
Icc2
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
VIN = 5.5V or Gnd
-10
10
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
-10
10
NOTES: 1) CMOS
inputs: GNO ± O.:W or Vee
2) TTL inputs: V1L ~ O.BV, V1H ;. 2.0V.
± O.:W.
3)
A.C.
UNITS
0.4
V
2.4
I
I
Comm'l
20 (Note 3)
Comm'l
25 (Note 3)
Power component adds 3
mA
!lA
rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
WS57C51-70
SYMBOL
PARAMETER
MIN
UNITS
MAX
Address to Output Delay
tACC
CS to Output Delay
tcs
70
25
Output Disable to Output Float
tOF
25
Address to Output Hold
tOH
ns
0
AC READ TIMING DIAGRAM
TEST LOAD (High
Impedance Systems)
98C!
ADDRESSES~
...
VALID
-.'
tACe
tOH
\J.
/
tcs
OUTPUTS
3·30
-
~
::~;~
<>------±
I=TIMING LEVELS
-
VALID
Input Levels: 0 and 3V
tOF
j.-
Reference Levels: 1.SV
30 pF
(INCWDING SCOPE
AND JIG
CAPACITANCE)
WS57C51
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN.
MAX.
UNIT
Input Leakage Current
VIN = Vee or Gnd
III
-10
10
p.A
Vpp Supply Current During
Programming Pulse
Ipp
60
rnA
Vee Supply Current (Notes 2 and 3)
Icc
25
rnA
Input Low Level
VIL
-0.1
0.8
V
Input High Level
VIH
2.0
Vee+0.3
V
Output Low Voltage During Verify
(IOL = 16mA)
VOL
0.45
V
Output High Voltage During Verify
(IOH = -4mA)
VOH
2.4
V
NOTE: 5) Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN.
Address Setup Time
lAs
2
Chip Disable Setup Time
tOF
Data Setup
tos
2
Program Pulse Width (Note 6)
tpw
1
2
Data Hold Time
tOH
Chip Select Delay
tes
Vpp Rise and Fall Time
tRF
TYP.
MAX.
UNIT
P.s
30
ns
10
ms
30
P.s
ns
P.s
3
1
P.s
NOTE: 6) 10 ms is the pulse width required for simple, one pulse only. programming routines.
PROGRAMMING WAVEFORM
V'H
X
ADDRESSES
V'L
DATA
V'H=>
V'L
-.
V••
IDF
ADDRESS STABLE
~IAS1
<
--..
DATA
IN
> <
'~1
DATA OUT
~~
V'H
CSllV ••
V'L
3-31
WS57C51
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C51 has all 16Kx8 bils
in the "1," or high state. "O's" are loaded into the WS57C51
through the procedure of programming.
Programming is performed by raising Vee to 5.75V, disabling
the outputs, addressing the byte to be programmed, presenting the data to be programmed onto the data pins, and applying a 13.5V pulse to the CS1Npp pin for 5 ms. The byte is
then verified by removing the input data and reading the programmed byte as in the read operation. A 0.1 ~F capacitor
between Vpp and GND is needed to prevent excessive voltage
transients, which could damage the device.
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 12000~ W/cm2 for 15 to 20 minutes. The
WS57C51 should be about one inch from the source and all
filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS57C51 and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C51 and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C51 to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS57C51. This dosage can be obtained by exposure
PROGRAMMERS
Data I/O Unipak 2B, software version 13 or later, family/pinout
code 7BI71; WSI's MagicPro™ IBM PC Compatible Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
WS57C51-700
70
24 Pin CERDIp, 0.6"
01
Comm'l
Standard
3-32
-iF====~~
------!::""=-F.:_=-;-=
==
---
~~
-
WS57C518
WAFERSCALE INTEGRA770N, INC.
HIGH SPEED 16K X 8 CMOS RPROM™
KEY FEA TURES
• Pin Compatible with AM27S51
• Ultra·Fast Access Time
-
40 ns
• Immune to Latch·Up
• Low Power Consumption
-
-
250 mW Active Power (10 MHz)
up to 200 mA
• ESD Protection Exceeds 2000V
• Fast Programming
GENERAL DESCRIPTION
The WS57C51 B is an extremely High Performance 128K UV Erasable electrically Re-Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar PROM
speeds while consuming only 25% of the power required by its Bipolar counterparts.
A further advantage of the WS57C51 B over Bipolar PROM devices is the fact that it utilizes a proven EPROM
technology. This allows the entire memory array to be tested for switching characteristics and functionality after
assembly. Unlike devices which cannot be erased, every WS57C51 B is 100% tested with worst case test patterns
both before and after assembly.
The WS57C51 B provides a low power alternative to those designs which are committed to a bipolar PROM
footprint. It is a direct drop-in replacement for a bipolar PROM of the same architecture (16K x 8). No software,
hardware or layout changes need be performed.
PIN CONFIGURATION
vee
A,.
:
An
A'2
As
A4
A'3
A.
CS1N pp
A3
CS2
A2
CS3
A,
CS4
A.
07
o.
o.
0,
O.
O.
O.
GND
03
:J6
28[:
~~: o:~~
A13
CS1Npp
A, '::J9
25[: CS3
A.
24[:
=J10
NC =J 11
a. :J 12
a, :J 14 15 16 17 18
13 r1 fl fl rl rl
23[=
NC
22[:
07
19 20L_
rl fl 21
o.
A. NC GND 0 3 NC A.
as
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C51B-40
WS57C51B-45
WS57C51B·55
WS57C51B·70
Address Access Time (Max)
40 ns
45 ns
55 ns
70 ns
Output Enable Time (Max)
20 ns
20 ns
20 ns
25 ns
3-33
WS57C51B
"Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature ....... -65° to + 150°C
Voltage on any pin with
respect to GND ............... -O.6V to +7V
VPPwith respecttoGND ..... -O.6Vto+14.0V
ESD Protection .................... > 2000V
OPERATING RANGE
Range
Comm'l
Military
Temperature
0° to +70°C
_55° to +125°C
Vcc
+5V+5%
+5V± 10%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
VOL
10L
VOH
Output High Voltage
10H
Icct
Vcc Active Current (CMOS)
Notes 1 and 3
Icc2
Vcc Active Current (TTL)
Notes 2 and 3
III
Input Load Current
ILO
Output Leakage Current
= 5.5V or Gnd
VO UT = 5.5V or Gnd
NOTES:
MIN
= 16 mA
= -4 mA
Output Low Voltage
0.4
3)
A.C.
UNITS
V
2.4
Comm'l
Military
Comm'l
Military
30
35
40
40
VIN
1) CMOS inputs: GND ± O.3V or Vce ± O.3V.
2) TTL inputs: V 1L " O.SV, V 1H " 2.0V.
MAX
Power component adds 3
Note
3
mA
Note
3
-10
10
-10
10
IlA
rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
SYMBOL
Address to Output Delay
WS57C51B-40 WS57C51B-45 WS57C51B-55 WS57C51B-70
MIN
MAX
MIN
MAX
MIN
MAX
MAX
MIN
tACC
40
45
55
70
CS to Output Delay
tcs
20
20
20
25
Output Disable to
Output Float
tOF
20
20
20
25
Address to Output Hold
tOH
UNITS
ns
0
0
0
0
TEST LOAD (High
AC READ TIMING DIAGRAM
Impedance Systems)
980
ADDRESSES
~.
VALID
.,'
tAce
CS
J.
~ tOH
'""
3-34
D.U.T.
I
-=-
/
TIMING LEVELS
les
OUTPUTS
2'01V~
-
VALID
tOF
/
Input Levels: 0 and 3V
I--
Reference Levels: 1.5V
30pF
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
WS57C51B
PROGRAMMING INFORMA TION
DC CHARACTERISTICS (TA
= 25 ±
PARAMETER
5°C, Vee
= 5.50V ±
= 12.5 ±
5%, Vpp
0.5V)
SYMBOLS
MIN.
MAX.
UNIT
III
-10
10
p.A
60
rnA
Input Leakage Current
VIN = Vee or Gnd
Vpp Supply Current During
Programming Pulse
Vee Supply Current (Notes 2 and 3)
lee
25
rnA
Input Low Level
Vll
-0.1
0.8
V
Input High Level
VIH
2.0
Vec+0.3
V
Output Low Voltage During Verify
(IOl = 16mA)
VOL
0.45
V
Output High Voltage During Verify
(IOH = -4mA)
VOH
Ipp
2.4
V
NOTE: 5) Vpp must not be greater than 14 volts including overshoot.
AC CHARACTERISTICS (TA
= 25 ±
PARAMETER
5°C, Vee
= 5.5V ±
5%, Vpp
SYMBOLS
MIN.
Address Setup Time
tAs
2
Chip Disable Setup Time
toF
Data Setup
tos
tpw
2
2
Program Pulse Width (Note 6)
Data Hold Time
tOH
Chip Select Delay
tcs
Vpp Rise and Fa" Time
tRF
= 12.5 ±
0.5V)
TYP.
1
3
MAX.
UNIT
30
P.s
ns
10
P.s
ms
/-lS
30
ns
1
/-ls
NOTE: 6) 10 ms is the pulse width required for simple, one pulse only, programming routines.
PROGRAMMING WA VEFORM
ADDRESSES
DATA
ADDRESS STABLE
,H
v
V,L
v••
=>
-
tDF
DATA IN
> <
'001
DATA
out
.. ~
V,H
CSt/V ••
V,L
3-35
WS57C51S
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C51B has all 16Kx8
bits in the "1," or high state. "O's" are loaded into the WS57C51B
through the procedure of programming.
Programming is performed by raising Vee to 5.75V, disabling
the outputs, addressing the byte to be programmed, presenting the data to be programmed onto the data pins, and applying a 12.5V pulse to the CS1Npp pin for 5 ms. The byte is then
verified by removing the input data and reading the programmed byte as in the read operation. A 0.1 I1F capaCitor
between Vpp and GND is needed to prevent excessive voltage
transients which could damage the device.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C51B to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS57C51B. This dosage can be obtained by exposure
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 12000" W/cm 2 for 15 to 20 minutes. The
WS57C51B should be about one inch from the source and all
filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS57C51B and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C51B and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
PROGRAMMERS
Data I/O Unipak 2B, software version 13 or later, family/pinout
code 7B/71; WSI's MagicPro™ IBM PC Compatible Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C51B-400
WS57C51B-4OT
WS57C51B-45CMB
WS57C51 B-450
WS57C51 B-450MB
WS57C51 B-45T
WS57C51B-45TMB
WS57C51B-55CMB
WS57C51 B-550
WS57C51B-550MB
WS57C51 B-55T
WS57C51B-55TMB
WS57C51 B-70CMB
WS57C51 B-700M
WS57C51 B-7OT
3-36
SPEED
(ns)
40
40
45
45
45
45
45
55
55
55
55
55
70
70
70
PACKAGE
TYPE
24
24
32
24
24
24
24
32
24
24
24
24
32
24
24
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CEROIP
Pin CEROIp,
PACKAGE
DRAWING
0.6"
0.3"
0.6"
0.6"
0.3"
0.3"
0.6"
0.6"
0.3"
0.3"
0.3"
01
T1
C2
01
01
T1
T1
C2
01
01
T1
T1
C2
T1
T1
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
Comm'l
Comm'l
Military
Comm'l
Military
Comm'l
Military
Military
Comm'l
Military
Comm'l
Military
Military
Military
Comm'l
Standard
Standard
MIL-STO-883C
Standard
MIL-STO-883C
Standard
MIL-STO-883C
MIL-STO-883C
Standard
MIL-STO-883C
Standard
MI L-STO-883C
MI L-STO-883C
Standard
Standard
WS27C64F
WAFERSCALE INTEGRA170N. INC.
MILITARY BK x B CMOS EPROM
KEY FEATURES
• EPI Processing
• Fast Access Time
-
-
90 ns
-
Latch-Up Immunity Up to 200 rnA
• Standard EPROM Pinout
• Military Temperature
Operating Range
• Low Power Consumption
1 mW During Power Down
240 mW Active Power (Max)
GENERAL DESCRIPTION
The WS27C64F is a HIGH PERFORMANCE 64K UV Erasable Electrically Programmable Read Only Memory. It is
manufactured in an advanced CMOS technology which allows it to operate at high speeds and very low power
over the Military operating range.
The WS27C64F is a direct drop-in replacement for the industry standard 27C64 and/or 2764 EPROMs. It was
developed specifically for this purpose and requires no board or software modifications to complete the change.
The WS27C64F is configured in the standard EPROM pinout which provides an easy upgrade path to the
WS27C128F and WS27C256F.
PIN CONFIGURATION
P
.... t ! l ; u H G u
Cc>z>Mz
I
I
I
I
II
II
vpp
"1
II
L..I
.....
L.""
I L. ..............
4
3
2
I
: ~~: 0
As :~5
~~
32 31 30
1
A2 :~ 9
A,
:J 10
A. :]11
NC
29[: A.
::~~
A.
A.
A.
A11
A,
NC
A.
25[: OE
24[:
o. :J13
A11
OE
A,.
A,.
A,
23[: CE
22:: 0 7
21[: O.
NC :J12
vee
PGM
A.
O.
0,
14 15 16 17 18 19 20
....
,., PO"'l""
r'" .........
• II II
II
II II • I I
CE
07
O.
O.
O.
0,
GND
o.
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS27C64F-90
WS27C64F-12
WS27C64F-15
Address Access Time (Max)
90 ns
120 ns
150 ns
Chip Select Time (Max)
90 ns
120 ns
150 ns
Output Enable Time (Max)
30 ns
30 ns
35 ns
3-37
WS27C64F
ABSOLUTE MAXIMUM RATINGS*
·Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ........ -650 to + 150°C
Voltage on any pin with
respect to GNO ................ -O.6V to +7V
VPP with respect to GNO ... -O.6V to +14.0V
ESO Protection ..................... > 2000V
OPERATING RANGE
Range
Temperature
Vee
Military
_55° to +125°C
+5V ±10%
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range with Vpp = Vce.
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL=4mA
VOH
Output High Voltage
ISB1
Vcc Standby Current CMOS
IOH= -1mA
Note 1
ISB2
Vcc Standby Current TTL
Note 2
ICC1
ICC2
Ipp
Active Current (CMOS)
Vcc Active Current (TTL)
Vpp Supply Current
V~p
III
MIN
PARAMETER
Address to Output Delay
"TIE to Output Delay
C5E to Output Delay
V
2.4
V
200
10
/LA
mA
Notes 1 and 3
25
mA
Notes 2 and 3
Vpp=Vcc
35
100
mA
Vcc-O.4
Input Load Current
Output Leakage Current
ILO
NOTES: 1) CMOS inputs: GND ± 0:3V or Vee ± 0.3>1.
2) TTL inpulS: V1L .. O.EN, V1H .. 2.OV.
UNITS
0.4
Vpp Read Voltage
AC READ CHARACTERISTICS
MAX
/LA
V
Vcc
-10
10
VIN = 5.5V or Gnd
-10
10
VOUT = 5.5V or Gnd
3) A.C. Active power component is 3 rnA/MHz (Power = AC + DC).
p.A
/LA
Over Operating Range with Vpp = Vce.
SYMBOL
WS27C64F-90
MIN
MAX
WS27C64F-12
MIN
MAX
WS27C64F-15
MIN
MAX
tACC
90
120
150
t CE
90
120
150
tOE
30
30
35
Output Disable to Output Float
t DF
Address to Output Hold
tOH
30
30
0
AC READ TIMING DIAGRAM
0
UNITS
ns
35
0
TEST LOAD (High
Impedance Systems)
3200
ADDRESSES
2.0W
CE ------..
o----I\J'-l
D.U.T.~ 100 pF
I-=-
(INCWDING SCOPE
AND JIG
CAPACITANCE)
OE - - - - - - - - - . , . .
TIMING LEVELS
OUTPUTS
------------.~~VAi::iDl'tH+-
Input Levels: .45 and 2.4V
Reference Levels: .8 and 2.0V
3-38
WS27C64F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C,
PARAMETER
Input Leakage Current
iVIN = Vee or Gnd)
Vp p Supply Current During
Programming Pulse
(CE = PGM = V,L)
Vee Supply Current (Note 3)
Vee
= 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
MIN.
SYMBOL
-10
III
Ipp
Icc
V,l
V,H
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOl = 16mA)
-0.1
2.0
MAX.
UNIT
10
p.A
60
mA
50
mA
0.8
Vee+ 0.3
V
0.45
VOL
V
V
Output High Voltage During Verify
V
V OH
2.4
(IOH = -4mA)
NOTES: 5) Vec must be applied either cOincidentally or before Vpp and remove~lth~lncldenta"y or after Vpp.
6) Vpp must not be greater than 14 volts including overshoot. During eE = PGM = V,L , Vpp must not be switched
from 5 volts to 13.5 volts or vice-versa.
7) During power up the PGM pin must be brought high (~ V,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS
(TA
= 25 ± 5°C,
PARAMETER
Address Setup Time
Chip Enable Setup Time
Vee
= 5.5V ± 5%,
SYMBOL
t AS
= 13.5 ± 0.5V).
MIN.
2
8)
UNIT
p's
p's
2
2
p's
p's
p's
0
2
0
130
p's
ns
ns
10
p's
ms
130
tOE
2
tvs
t pw
1
Single pulse programming algorithms should use one 10 ms PGM pulse per byte.
Vpp Setup Time
PGM Pulse Width
NOTE:
MAX.
TYP.
2
teEs
tOES
tos
tAH
tOH
tOF
Output Enable Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Chip Disable to Output Float Delay
Data Valid from Output Enable
Vpp
3
PROGRAMMING WA VEFORM
ADDRESSES
~
ADDRESS STABLE
_lAS"
DATA IN STABLE
DATA~
I-- los--
HIGH Z
I+IOH .....
41oE-
V••
V••
Vee
CE
----1 I-Ivs -
_~
tAH
-
I ••
K=
I--
DATA OUT
VALID
I--
VIH~
V'L
I- ICES'"
V,H
PGM
V'L
V ,H
OE
V,L
\,
j
~Ipw-.j
f-- IOES '1
~
I
3-39
WS27C64F
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS27C64F has all 8192x8
bits in the "1:' or high state. "O's" are loaded into the WS27C64F
through the procedure of programming.
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 12000/1 Wlcm 2 for 20 minutes. The WS27C64F
should be about one inch from the source and all filters should
be removed from the UV light source prior to erasure.
The programming mode is entered when +13.5V is applied to
the Vpp pin and CE is at V1L. During programming, CE is kept
at VIL. A 0.1 /1F capacitor between V pp and GND is needed
to prevent excessive voltage transients, which could damage
the device. The adgress to be programmed is applied to the
proper address pins. 8-bit patterns are placed on the respective data output pins. The voltage levels should be standard
TTL levels.
It is important to note that the WS27C64F and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS27C64F and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
ERASURE
PROGRAMMERS
In order to clear all locations of their programmed contents,
it is necessary to expose the WS27C64F to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS27C64F. This dosage can be obtained by exposure
Data I/O Unipak 2 or 2B, software version 9 or later, familyl
pinout code 3C/33; WSI's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS27C64F-90CMB
WS27C64F-900MB
WS27C64F-12CMB
WS27C64F-120MB
WS27C64F-15CMB
WS27C64F-150MB
90
90
120
120
150
150
3-40
PACKAGE
TYPE
32
28
32
28
32
28
Pad CLLCC
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
C2
02
C2
02
C2
02
Military
Military
Military
Military
Military
Military
MIL-STO-883C
MI L-STO-883C
MIL-STO-883C
MIL-STO-883C
MI L-STO-883C
MIL-STO-883C
!F==
,::~
.---r =: =:..E =
...,
~~~ ~
WS57C64F
----------------------------------------------------------------
WAFERSCALE INTEGRA 110N, INC.
HIGH SPEED BK X 8 CMOS EPROM
KEY FEATURES
• Fast Access Time
• EPI Processing
-55ns
-Latch-up Immunity up to 200mA
• Low Power Consumpt1on
• Standard EPROM Pinout
• Bipolar Speeds
-90mW During Power Down (18 MHz)
-280mW Active Power (18 MHz)
GENERAL DESCRIPTION
The WS57C64F is an extremely HIGH PERFORMANCE 64K UV Erasable Electrically Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar speeds while
consuming very little power.
Two major featu res of the WS57C64F are its Low Power and High Speed. These featu res make it ~n ideal solution
for applications which require fast access times, low power, and non-volatility. Typical applications include
systems which do not utilize mass storage devices and/or are board space limited. Examples of these
applications are modems, secure telephones, servo controllers, and industrial controllers.
The WS57C64F is configured in the standard EPROM pinout which provides an easy upgrade path to higher
density EPROMs.
PIN CONFIGURATION
P
,..~t(J8Go
CC>z>Mz
L.
,"
II
........ ""
......
I
I
4
3
2
"
II
.,
vee
PGM
•
, .......... 1. ...
32 31 30
1
0
As :~6
::~~:
A1 ~J 10
Ao :;11
NC
28'-
A.
Ag
:il:
Aa
24r~. A'0
23[:
NC :} 12
CE
22:: 0 7
0 0 :]13
21[= O.
0,
16 17 .....
18 _
19.. ".20...
"14.....15, r-.,,...,
I
II
I
I
II
II
I'
II
O.
•
GND
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C64F-55
WS57C64F-70
Address Access Time (Max)
55ns
70ns
Chip Select Time (Max)
55ns
70ns
Output Enable Time (Max)
20ns
25ns
3-41
WS57C64F
ABSOLUTE MAXIMUM RA TINGS*
·Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65° C to +150° C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14.0V
ESD Protection ......................... >2000V
OPERATING RANGE
Range
Temperature
Vee
Comm'l.
0° to +70°C
Military
-55° to +125°C
± 5%
+5V ± 10%
DC READ CHARACTERISTICS
+5V
Over Operating Range with Vpp = Vcc.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Output Low Voltage
IOL= 16mA
VOH
Output High Voltage
IOH= -4mA
ISBl
Vcc Standby Current (CMOS) CE=Vcc ± 0.3V. Notes 1 and 3
ISB2
Vee Standby Current(TTL)
VOL
Notes 1 and 4
Icc2
Vee Active Current (TTL)
Notes 2 and 4
Ipp
Vpp Supply Current
Vpp= Vcc
Vpp
Vpp Read Voltage
ILO
NOTES:
Output Leakage Current
CMOS mputs: GNO ± O.3V or Vee ±
2) TTL inputs: V 1L .. O.BV, V1H .. 2.0V.
1)
500
p.A
15
mA
V
V
CE=VIH. Notes 2 and 3
Vee Active Current (CMOS)
Input Load Current
UNITS
2.4
Iccl
III
MAX
0.4
Comm'l.
20
mA
Military
30
mA
Comm'l.
25
mA
35
mA
100
p.A
Military
Vee-0.4
Vce
V
-10
10
p.A
-10
VOUT = 5.5V or Gnd
3) A.C. Power component adds 1 rnA/MHz.
4) A.C. Power component adds 3 rnA/MHz.
10
p.A
VIN = 5.5V or Gnd
O.3V.
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vec.
PARAMETER
Address to Output Delay
TI to Output Delay
OE to Output Delay
SYMBOL
WS57C64F-55
MAX
MIN
WS57C64F-70
MIN
MAX
tACC
55
70
t CE
55
70
tOE
20
25
Output Disable to Output Float
t OF
Address to Output Hold
t OH
20
10
AC READ TIMING DIAGRAM
UNITS
ns
25
10
TEST LOAD (High Impedance Systems)
97.50
ADDRESSES
2.01V~
CE ------,..
D.U.T.~ 30pF
I-=-
(INCWDING SCOPE
AND JIG
CAPACITANCE)
OE---------~
TIMING LEVELS
OUTPUTS
--------------~:tVALiDTi;~---
Input Levels: 0 and 3V
Reference Levels: 0.8 and 2.0V
3-42
WS57C64F
PROGRAMMING INFORMATION
DC CHARACTERISTICS
± 5°C,
(TA = 25
PARAMETER
± 5%,
Vee = 5.5V
± 0.5V)
Vpp = 13.5
SYMBOLS
MIN.
MAX.
UNIT
Input Leakage Current
VIN = Vee or Gnd
III
-10
10
IJ.A
Vpp Supply Current During
Programming Pulse
(CE = PGM = Vll)
Ipp
60
rnA
Vee Supply Current (Note 4)
lee
25
rnA
Input Low Level
Vil
-0.1
0.8
V
Input High Level
VIH
2.0
Vee+0.3
V
Output Low Voltage During Verify
(IOl = 16mA)
VOL
0.45
V
Output High Voltage During Verify
(IOH = -4mA)
VOH
NOTES:
2.4
V
6) Vee must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp.
7) Vpp must not be greater than 14 volts including overshoot. During eE = PGM = VIL, Vpp must not
be switched from 5 volts to 13.5 volts or vice-versa.
8) During power up the PGM pin must be brought high ""VIH) either coincident with or before power is applied to VPP.
AC CHARACTERISTICS
(TA = 25
± 5°C, Vee
PARAMETER
= 5.5V
± 5%, Vpp
= 13.5
± 0.5V)
TYP.
MAX.
UNIT
SYMBOLS
MIN.
tAs
2
IJ.S
Chip Enable Setup Time
teEs
2
IJ.s
Output Enable Setup Time
toES
2
IJ.s
Data Setup Time
tos
2
IJ.S
Address Hold Time
tAH
0
IJ.s
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tOF
0
Address Setup Time
Data Valid from Output Enable
IJ.s
tOE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
130
ns
130
ns
10
ms
IJ.S
3
NOTE: 9) For simple, one pulse only, programming algorithms, use a 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
~
ADDRESS STABLE
-lAS -DATA
----1
v••
L
DATA IN STABLE
HIGH Z
"'-
I-IOH -
--105 -
I-IoE
v••
Vee - - - '
CE
VIH~
~
-I
c:=
-- _~
tAoH
DATA OUT
VALID
>---
IDF
1- 1.. -
VIL
i--ICES -V,H
PGM
VIL
V,H
OE
V,L
~
i--tDES
1
~
J
3-43
WS57C64F
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C64F has all 8192x8
bits in the "1:' or high state. "O's" are loaded into the WS57C64F
through the procedure of programming.
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 1200011 W/cm 2 for 20 minutes. The WS57C64F
should be about one inch from the source and all filters should
be removed from the UV light source prior to erasure.
The programmi~mode is entered when +13.5V is applied to
the Vpp pin and CE is taken to V1L• During programming, CE is
kept at V1L• A 0.1 I1F capacitor between Vpp and GND is
needed to prevent excessive voltage transients which could
damage the device. The address to be programmed is applied
to the proper address pins. 8-bit patterns are placed on the
respective data output pins. The voltage levels should be
standard TTL levels.
It is important to note that the WS57C64F and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C64F and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
ERASURE
PROGRAMMERS
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C64F to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS57C64F. This dosage can be obtained by exposure
Data 1/0 Unipak 2 or 2B, software version 9 or later, familyl
pinout code 3C/33; WSI's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C64F-550
WS57C64F-70CMB
WS57C64F-700
WS57C64F-700MB
3-44
SPEED
PACKAGE
TYPE
(ns)
55
70
70
70
24
32
24
24
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
Pin CEROIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
01
C2
01
01
Comm'l
Military
Comm'l
Military
Standard
MIL-STO-883C
Standard
MI L-STO-883C
WS27C128F
WAFERSCALE INTEGRAll0N. INC
MILITARY 16K x 8 CMOS EPROM
KEY FEATURES
• EPI Processing
• Fast Access Time
-
90/120/150 ns
-
• Low Power Consumption
-
Latch-Up Immunity Up to 200 rnA
• Standard EPROM Pinout
1 mW During Power Down
300 mW Active Power
• Military Operating Range
GENERAL DESCRIPTION
The WS27C128F is an extremely HIGH PERFORMANCE 128K UV Erasable Electrically Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at high speeds and very
low power over the full Military temperature operating range.
The WS27C128F was specifically designed to replace standard EPROMs in military environments. No hardware or
software changes are required to replace standard military 27128 EPROMs with the WSI WS27C128F.
The WS27C128F is configured in the standard EPROM pinout which provides an easy upgrade path for the WS27C64F
and the 256K bit WS27C256F.
PIN CONFIGURATION
I
I
•
II
••
II II 1'1
I&....I L .. L...I
L..1 .............. I
4
lie
:~5
~-l~
A, :] 10
A. :] 11
3
2
L~
32 31 30
0
29~:
1
A.
~l~~
24r~.
A,.
23[:
CE/PGM
Ne
:J 12
22~:
07
o.
:]13
21[:
o.
Ao
o.
0,
14 15 16 17 18 19 20
...• ""I I.. .,I r'.,,.."lII"""
...... ""
I
II
II II I ••
O•
OOC'olQO"''''''''
GND
i§zoOO
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS27C128F-90
WS27C128F-12
WS27C128F·15
Address Access Time (Max)
90 ns
120 ns
150 ns
Chip Select Time (Max)
90 ns
120 ns
150 ns
Output Enable Time (Max)
30 ns
30 ns
35 ns
3-45
WS27C128F
ABSOLUTE MAXIMUM RATINGS*
*Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ........ -65° to + 150°C
Voltage on any pin with
respect to GND ................ -O.6V to + 7V
VPP with respect to GND ... -O.6V to +14.0V
ESD Protection ..................... > 2000V
OPERATING RANGE
Range
Temperature
Vee
Military
_55° to +125°C
+5V ±10%
DC READ CHARACTERISTICS Over Operating Range with V pp = Vee.
SYMBOL
PARAMETER
TEST CONDITIONS
VOH
Output Low Voltage
Output High Voltage
ISB1
Vcc Standby Current CMOS
VOL
MIN
MAX
0.4
IOL=4mA
IOH= -1mA
Notes 1 and 3
2.4
UNITS
V
V
200
p.A
ISB2
Vcc Standby Current TIL
mA
Active Current (CMOS)
Notes 2 and 3
Notes 1 and 4
10
ICC1
25
mA
ICC2
Ipp
Vcc Active Current (TIL)
Vpp Supply Current
Notes 2 and 4
Vpp=Vcc
35
100
mA
p.A
Vpp
Vpp Read Voltage
III
Input Load Current
ILO
Output Leakage Current
NOTES: 1) CMOS inputs: GND ± O.3V or Vcc
2) TTL inputs: V,l"O.8V, VIH~.OV.
± O.3V.
Vcc-O.4
Vcc
V
VIN = 5.5V or Gnd
-10
10
p.A
Vour=5.5Vor Gnd
-10
10
p.A
3) A.C. standby power component is lmA/MHz.
4) A.C. Active power component is 3mA/MHz (Power = AC
+ DC).
AC READ CHARACTERISTICS Over Operating Range with V pp = Vce.
PARAMETER
SYMBOL
Address to Output Delay
WS27C128F-90
MIN
MAX
WS27C128F-12
MIN
MAX
WS27C128F-15
MIN
MAX
tACC
90
120
150
CE to Output Delay
t CE
90
120
150
OE to Output Delay
tOE
30
30
35
Output Disable to Output Float
t DF
30
30
30
Address to Output Hold
tOH
0
0
UNITS
ns
0
NOTE: Single shot programming algorithms should use one 10 ms PGM pulse per word.
AC READ TIMING DIAGRAM
TEST LOAD (High
Impedance Systems)
3200
ADDRESSES
..
C E - - -.........
2.01V~
D.U.T.~ 100 pF
I-=-
(INCWDING SCOPE
AND JIG
CAPACITANCE)
OE - - - - - - - - - . .
TIMING LEVELS
OUTPUTS
3-46
---------~a~~1lZ3~-
Input Levels: .45 and 2.4V
Reference Levels: .8 and 2.0V
WS27C12BF
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 12.5 ± 0.5V)
PARAMETER
1,nput Leakage Current
VIN = Vee or Gnd)
Vpp Supply Current During
Programming Pulse
(CE = PGM = VIL)
Vee Supply Current
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL = 16mA)
SYMBOL
-10
III
Ipp
Icc
V IL
VIH
MAX.
UNIT
10
IJ.A
30
mA
50
0.8
Vee + 0.3
-0.1
2.0
0.45
VOL
Output High Voltage During Verify
(IOH = -4mA)
NOTES:
MIN.
VOH
mA
V
V
V
2.4
V
6) Vee must be applied either comcldentally or before Vpp and removed elth~mcldenta"y or after Vpp.
7) Vpp must not be greater than 14 volts including overshoot. During CE = PGM = V'L, Vpp must not be switched
from 5 volts to 13.5 volts or vice·versa.
8) During power up the PGM pin must be brought high (~ V,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 12.5 ± 0.5V)
PARAMETER
Address Setup Time
Chip Enable Setup Time
Output Enable Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Chip Disable to Output Float Delay
Data Valid from Output Enable
Vpp Setup Time
PGM Pulse Width
(Note 9)
NOTE:
SYMBOL
tAS
teEs
tOES
tos
tAH
tOH
tOF
tOE
tvs
t pw
MIN.
2
2
2
2
0
2
0
MAX.
TYP.
UNIT
p's
p's
p's
p's
p's
p's
130
130
2
1
ns
ns
p's
ms
5
9) For single pulse programming algorithms, use one 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
~
ADDRESS STABLE
--1
I+- lAS ....
DATA _ _
DATA IN STABLE
I-- los .....
Vee
CE
~IoE ...
I-IOH -
V ••
v••
HIGH Z
----1 I+- Ivs-
-
tAH
K=
\4-
DATA OUT
VALID
IDF
t--
VIH~
V'L
I- ICES"
V ,H
PGM
V'L
V ,H
OE
V'L
\
I-
~
Ipw-j
_IOES~
~
J
3-47
WS27C128F
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS27C128F has all I 6,384 x 8
bits in the "I," or high state. "O's" are loaded into the
WS27CI28F through the procedure of programming.
The programming mode is entered when + 13.5V is applied to
the Vpp pin and CE is taken to V1L • During programming, CE is
kept at V1L• A 0.1 I1F capacitor between V pp and GND is
needed to prevent excessive voltage transients which could
damage the device. The address to be programmed is applied
to the proper address pins. 8-bit patterns are placed on the
respective data output pins. The voltage levels should be
standard TTL levels.
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 1200011 W/cm 2 for 20 minutes. The
WS27CI28F should be about one inch from the source and all
filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS27CI28F and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS27CI28F and exposure
to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS27CI28F to an ultra-violet light
source. A dosage of 15W second/cm2 is required to completely
erase a WS27C128F. This dosage can be obtained by exposure
PROGRAMMERS
Data 1/0 Unipak 2 or 2B, software version 12 or later, familyl
pinout code 3C/51; WSI's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS27CI28F-90CM
WS27CI28F-90CMB
WS27CI28F-900M
WS27C128F-900MB
WS27CI28F-12CM
WS27CI28F-12CMB
WS27C128F-120M
WS27C128F-120MB
WS27C128F-15CM
WS27C128F-15CMB
WS27C128F-150M
WS27C128F-150MB
3-48
SPEED
PACKAGE
TYPE
ens)
90
90
90
90
120
120
120
120
150
150
150
150
32
32
28
28
32
32
28
28
32
32
28
28
Pad CLLCC
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
0.6"
0.6"
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
C2
C2
02
02
C2
C2
02
02
C2
C2
02
02
Military
Military
Military
Military
Military
Military
Military
Military
Military
Military
Military
Military
Standard
MIL-STD-883C
Standard
MIL-STO-883C
Standard
MIL-STO-883C
Standard
MIL-STD-883C
Standard
MIL-STD-883C
Standard
MIL-STD-883C
--..F==':~
_---:..'ji-ii=ji-ii -
WS57C128F
WAFERSCALE INTEGRA710N, INC.
PRELIMINARY
=
~
iiiII:P~:'
HIGH SPEED 16K x 8 CMOS EPROM
KEY FEATURES
• EPI Processing
• Fast Access Time
-Latch-up Immunity up to 200mA
-55ns
• Standard EPROM Pinout
• Bipolar Speeds
• Low Power Consumption
-90mW During Power Down (18 MHz)
-30SmW Active Power (18 MHz)
GENERAL DESCRIPTION
The WS57C128F is an extremely HIGH PERFORMANCE 128K UV Erasable Electrically Programmable Read
Only Memory. It is manufactured in an advanced CMOS technology which allows it to operate at Bipolar speeds
while consuming only 60mA.
Two major features of the WS57C128F are its Low Power and High Speed. These features make it an ideal
solution for applications which require fast access times, low power, and non-volatility. Typical applications
include systems which do not utilize mass storage devices and/or are board space limited. Examples of these
applications are modems, secure telephones, servo controllers, and industrial controllers.
The WS57C128F is configured in the standard EPROM pinout which provides an easy upgrade path for systems
which are currently using standard EPROMs.
PIN CONFIGURATION
I
I
I
"ll
II
I.
II
vee
I
'4"' '3" L.£ ~~ 32 '3130
0
As ~~5
29~:
1
~: ~~:
A2 =~9
A1 ~J10
PGM
A.
::~~ :~
A.
Al1
25[: OE
A,
24[:. A10
AD :}11
23:: CE
Ne :J12
22~:
00
A13
A.
:J 13
21::
CE
AD
07
,
II
o.
o.
~
I
I
II
II
,.
,
07
O.
14 15
16 17 18 .19
20
.. ., , . . , ,..., r
.......
1"""
OE
A,o
••
0,
O.
GND
O.
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C128F-55
WS57C128F-70
Address Access Time (Max)
55ns
70ns
Chip Select Time (Max)
55ns
70ns
Output Enable Time (Max)
25ns
2Sns
3-49
WS57C12BF
ABSOWTE MAXIMUM RATINGS*
*Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ............ -65° to +150°C
Voltage on Any Pin with
Respect to GND ................ -0.6V to +7V
Vpp with Respect to GND ......... -0.6V to +14V
ESD Protection ........................ >2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
Comm'l
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V + 10%
= Vcc.
DC READ CHARACTERISTICS Over Operating Range with Vpp
PARAMETER
SYMBOL
TEST CONDITIONS
VOL
Output Low Voltage
VOH
Output High Voltage
IOH
IOL
MIN
= 16 mA
= -4 mA
MAX
UNITS
0.4
V
2.4
V
IS81
Vcc Standby Current (CMOS)
Notes 1 and 3
500
j.tA
IS82
Vcc Standby Current (TTL)
Notes 2 and 3
20
mA
Icc1
Active Current (CMOS)
Notes 1 and 4
Icc2
Vcc Active Current (TTL)
Notes 2 and 4
Ipp
Vpp Supply Current
Vpp
= Vcc
Vpp
Vpp Read Voltage
III
Input Load Current
V1N
= 5.5V or Gnd
Output Leakage Current
VOUT = 5.5V or Gnd
ILO
NOTES:
Comm'l
25
Military
30
Comm'l
35
Military
40
mA
100
j.tA
-10
Vcc
10
j.tA
-10
10
IlA
Vcc - 0.4
1) CMOS Inputs: GND ± O.:W or Vee ± 0.3V.
2) TTL inputs: VIL .. O.av, VIH ~ 2.OV.
mA
V
3) A.C. Standby power component IS 1 rnA/MHz (Power = AC + DC).
4) A.C. Active power component is 3 rnA/MHz (Power = AC + DC).
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vcc.
PARAMETER
SYMBOL
WS57C128F-55
MIN
MAX
WS57C128F-70
MIN
MAX
Address to Output Delay
tACC
55
70
CE to Output Delay
tCE
55
70
OE to Output Delay
tOE
25
Output Disable to Output Float
tOF
Address to Output Hold
tOH
25
10
AC READ TIMING DIAGRAM
25
0
UNITS
ns
25
10
TEST LOAD (High Impedance Systems)
97.50
ADDRESSES
:.:~;,~
I=
30pF
(INCWDING SCOPE
AND JIG
CAPACITANCE)
OE--------------~
TIMING LEVELS
OUTPUTS
3-50
--------------~~~~!~~---
Input Levels: 0 and 3V
Reference Levels: 0.8 and 2.0V
WS57C128F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± O.5V)
PARAMETER
l1nput Leakage Current
VIN = vee or Gnd)
Vpp Supply Current During
Programming Pulse
(CE = PGM = VII)
Vee Supply Current
Notes 2 & 4
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL
16mA)
=
Output High Voltage During Verify
(IOH
~4mA)
MAX.
UNIT
10
itA
60
mA
-10
III
Ipp
Icc
VIL
VIH
30
0.8
Vee + 0.3
-0.1
2.0
mA
V
V
V
0.45
VOL
VOH
=
NOTES:
MIN.
SYMBOL
V
2.4
6) Vcc must be applied either cOincidentally or before Vpp and removed elth~lncldentally or after Vpp.
7) Vpp must not be greater than 14 volts including overshoot. During CE = PGM = VIL , Vpp must not be switched
from 5 volts to 13.5 volts or vice-versa.
8) During power up the PGM pin must be brought high (2: VIH) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 5%, Vpp = 13.5 ± 0.5V)
PARAMETER
Address Setup Time
Chip Enable Setup Time
Output Enable Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Chip Disable to Output Float Delay
Data Valid from Output Enable
Vpp Setup Time
PGM Pulse Width
MIN_
2
2
2
2
0
2
0
SYMBOL
t AS
t CES
tOES
tos
tAH
tOH
tOF
tOE
tvs
tpw
TYP.
MAX.
.
2
1
-
130
130
3
10
UNIT
p's
p's
p's
p's
p's
p's
ns
ns
p's
ms
NOTE: Single shot programming algOrithms should use a single 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
~
ADDRESS STABLE
..... I AS . .
DATA IN STABLE
DATA~
CE
14 toE -l
V,,
Vee - - - '
VIH~
VIL
~
'lc
1+ 10H .....
4-1;"-
v,,
HIGHZ
L
c=
- ~
tAH
DATA OUT
VALID
)---
I DO
1- 1.. -
r--
ICES'"
V,H
PGM
VIL
V,H
OE
VIL
~
I-- IOE5 1
~
/
3-51
D
WS57C128F
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C128F has all 16,384x8
bits in the "1," or high state. "O's" are loaded into the
WS57C128F through the procedure of programming.
The programmin9..!!l0de is entered when +13.5V is applied to
the Vpp pin, and CE is at V 1L• During programming, CE is kept
at V1L • A 0.1 /1F capacitor between Vpp and GND is needed
to prevent excessive voltage transients, which could damage
the device. The address to be programmed is applied to the
proper address pins. 8-bit patterns are placed on the respective data output pins. The voltage levels should be standard
TTL levels.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C128F to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS57C128F. This dosage can be obtained by exposure
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 12000/1 W/cm 2 for 20 minutes. The
WS57C128F should be about one inch from the source and
all filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS57C128F and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A. the exposure to fluorescent light and
sunlight will eventually erase the WS57C128F and exposure
to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
PROGRAMMERS
Data 1/0 Unipak 2 or 2B, software version 11 or later, familyl
pinout code 3C/51; WSl's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C128F-550
WS57C128F-70CMB
WS57C128F-700
WS57C128F-700MB
3-52
SPEED
PACKAGE
TYPE
(n8)
55
70
70
70
28
32
28
28
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
Pin CEROIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
02
C2
02
02
Comm'l
Military
Comm'l
Military
Standard
MIL-STO-883c
Standard
MIL-STO-883C
WS27C256F
PRELIMINARY
WAFERSCALE INTEGRA TION, INC.
MILITARY 32K
x 8 CMOS EPROM
KEY FEATURES
• Fast Access Time
-
• EPI Processing
-
90 ns (Military)
-
Latch-Up Immunity Up to 200 mA
• Military High Rei Processing
• Drop-In Replacement for
• Low Power Consumption
1 mW During Power Down
325 mW Active Power
-
M27256
GENERAL DESCRIPTION
The WS27C256F is a HIGH PERFORMANCE 256K UV Erasable Electrically Programmable Read Only Memory. It
is manufactured in an advanced CMOS technology which allows it to operate at speeds as fast as 90 ns Access
Time over the full military operating range. (If faster speeds are required, contact your WSI sales representative.
Two major features of the WS27C256F are its Low Power and High Speed. While operating in a TTL environment
it consumes only 65 mA while cycling at full speed. Additionally, the WS27C256F can be placed in a standby mode
which drops operating current below 30 mA in a TTL environment and 200 ~ in a CMOS environment.
The WS27C256F is configured in the standard EPROM pinout which provides an easy upgrade path for systems
which are currently using standard EPROMs.
MODE SELECTION
PIN CONFIGURATION
MODE
~
CE
OE Vpp Vee
Read
VIL
VIL Vee Vee DOUT
Output Disable
X
Standby
VIH
Program
VIL
Program Verify
X
OUTPUTS
VIH Vee Vee High Z
X
Vee Vee High Z
VIH Vpp Vee DIN
VIL Vpp Vee DOUT
Program Inhibit
VIH VIH Vpp Vee High Z
Signature*
VIL
VIL Vee Vee Encoded Data
to H , ,
... S!
Cc>z>c(c
0
"I
II
';;' '3
A,; :;5
A, :; 6
~'"
A'~~8
A2 _,9
A, ~~10
A• . ,11
NC ::12
0 0 :113
II
II
I,
"
~~
I
2~1323130
1
29[: As
28[: A,;
a""
26~~~
25 •. OE
VPP[ 1
A12 [
A7C
A,c
A,c
28
27
2
3
4
5
~
A,.
25~A,
24~A.
A'C6023~Al1
A,c 7
24~~ ~_ A2 e 8
23 •. CElPGM A,[ 9
22:: 0 7
A,;[ 10
21~: 0&
00c 11
!~!~ 16,F, l'!lH~
0, [ 12
.; • ~' " .. ~. ~. ~
0, [ 13
oo~~ooo
GND[14
X can be either V,L or V'H'
'For Signature. Ag = 12V. Ao is toggled. and all other address are at:
TTL low. Ao = V'L = MFGR 23H. Ao = V'H = DEVICE A8H.
~Vcc
26~A13
22 ~ OE
21:JA,o
20~CEIPGM
19?07
18pO&
17~ 0,
16100.
15100,
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS27C256F-90
WS27C256F-12
WS27C256F-15
Address Access Time (Max)
90 ns
120 ns
150 ns
Chip Select Time (Max)
90 ns
120 ns
150 ns
Output Enable Time (Max)
30 ns
35 ns
40 ns
3-53
WS27C256F
ABSOWTE MAXIMUM RATINGS·
·Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65° to +150°C
Voltage on any pin with
respect to GND .............. -0.6V to +7V
Vpp with respect to GND ........ -0.6V to +14V
ESD Protection ...................... >2000V
OPERATING RANGE
TEMPERATURE
Vee
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vcc.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNITS
0.4
V
250
itA
VOL
Output Low Voltage
IOL = 4 rnA
VOH
Output High Voltage
IOH = -1 rnA
ISB1
Vcc Standby Current CMOS
CE = Vcc ± 0.3V (Note 1)
ISB2
Vcc Standby Current TIL
CE = VIH (Note 2)
5
rnA
Icc1
V ce Active Current (CMOS)
Note 1
30 (Note 3)
rnA
Icc2
Vcc Active Current (TIL)
Note 2
40 (Note 3)
rnA
Vpp = Vce
Ipp
Vpp Supply Current
Vpp
Vpp Read Voltage
III
Input Load Current
ILO
Output Leakage Current
NOTES:
2.4
V
100
itA
Vcc -0.4
Vcc
V
VIN = 5.5V or Gnd
-10
10
VO UT = 5.5V or Gnd
-10
10
ItA
ItA
1) CMOS inputs: GNO ± 0.3V or Vee ± 0.'311.
2) TTL inputs: V1L " O.BV, V1H ;. 2.0V.
3)
A.C.
Ac1ive power component is 3
rnA/MHz
(Total Power =
AC + OC).
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vcc.
PARAMETER
SYMBOL
Address to Output Delay
WS27C256F·90
MIN
MAX
WS27C256F-12
MIN
MAX
WS27C256F-15
MIN
MAX
tACC
90
120
150
CE to Output Delay
tCE
90
120
150
OE to Output Delay
tOE
30
35
40
Output Disable to Output Float
tOF
30
35
40
Address to Output Hold
tOH
0
AC READ TIMING DIAGRAM
0
UNITS
ns
0
TEST LOAD (High Impedance Systems)
320n
ADDRESSES
ce-----...
:::~;~
~I (INC~DING
-=-
100 F
SCOPE
AND JIG
CAPACITANCE)
O E - - - - - - -____
TIMING LEVELS
OUTPUTS---------~KtV.MIi'~~-
Input Levels: .45 and 2.4
Reference Levels: 0.8 and 2.0V
3-54
WS27C256F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 -+ 5°C, Vee = 5.5V -+ 10%, Vpp
PARAMETER
SYMBOL
Input Leakage Current
iVIN = Vee or Gnd)
Vee Supply Current During
Programming Pulse
(eE = PGM = V,l)
Vcc Supply Current (Note 3)
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOl=4mA)
Output High Voltage During Verify
(IOH=-1mA)
12.5 + 0.5V)
MIN.
-10.
III
Icc
Icc
V,l
V,H
MAX.
UNIT
10
p.A
60
mA
30
mA
V
V
O.B
-0.1
2.0
Vee+ O.3
0.45
VOL
V
2.4
VOH
V
NOTES: 5) Vee must be applied either cOincidentally or before Vpp and removed either cOinCidentally or after Vpp.
6) Vpp must not be greater than 14 volts including overshoot. During CE = PGM = V ,L' Vpp must not be switched from 5 volts
to 12.5 volts or vice-versa.
7) During power up the PGM pin must be brought high (~ V,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 10%, Vpp = 12.5 ± 0.5V)
PARAMETER
SYMBOLS
MIN
Address Setup Time
tAS
2
TYP
MAX
UNIT
~s
CE High to OE High
teoH
2
~s
Output Enable Setup Time
tOES
2
~s
Data Setup Time
tos
2
~s
Address Hold Time
tAH
0
~s
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tOF
0
~s
55
Data Valid From Output Enable
tOE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
OE Low to CE "Don't Care"
toex
2
55
ns
ns
~s
10
3
ms
~s
NOTE: 8) Single pulse programming algorithms should use one 10 ms PGM pulse per byte.
PROGRAMMING WA VEFORM
ADDRESSES
~
~
~ IA.-DATA
----1
DATA IN STABLE
I-- los'"
HIGH Z
f4-IoE ...
_ loH -
V••
CElPGM'
V'L
V'H
DE
VIL
-
IDF
-r--
I-- Iv. f- ICE."
V'H
tAH
DATA OUT
VALID
V ••
Vee - - - '
C
ADDRESS STABLE
locx-
~
~
~
f=tpw~
I-- I- 1e0H
l-
I--IOE.j
~
J
3-55
WS27C256F
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS27C256F has all
32,768x8 bits in the "1;' or high state. "O's" are loaded into
the WS27C256F through the procedure of programming.
The programming mode is entered when +12.5V is applied to
the Vpp pin, and CE/PGM is taken to V1L• During programming, CE/PGM is kept at V1L• A 0.1 IlF capacitor between Vpp
and GND is needed to prevent excessive voltage transients,
which could damage the device. The address to be programmed is applied to the proper address pins. 8-bit patterns
are placed on the respective data output pins. The voltage levels
should be standard TIL levels.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS27C256F to an ultra-violet light
source. A dosage of 15W second/cm2 is required to completely
erase a WS27C256F. This dosage can be obtained by exposure
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 1200011 W/cm 2 for 20 minutes. The
WS27C256F should be about one inch from the source and
all filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS27C256F and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A. the exposure to fluorescent light and
sunlight will eventually erase the WS27C256F and exposure
to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
PROGRAMMERS
Data 1/0 Unipak 2 or 2B, software version 12 or later, familyl
pinout code 3C/32; WSI's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS27C256F-90CMB
WS27C256F-900MB
WS27C256F-12CMB
WS27C256F-120MB
WS27C256F-15CMB
WS27C256F-150MB
90
90
120
120
150
150
3-56
PACKAGE
TYPE
32
28
32
28
32
28
Pad CLLCC
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
C2
02
C2
02
C2
02
Military
Military
Military
Military
Military
Military
MIL-STO-883C
MIL-STO-883C
MIL-STO-883c
MIL-STO-883C
MIL-STO-883C
MIL-STD-883C
...==
_
===~~
.......
...
.~-
----
WS57C256F
...
r~~~_
~-===:
~~
PRELIMINARY
WAFERSCALE INTEGRA TION, INC.
HIGH SPEED 32K x 8 CMOS EPROM
KEY FEATURES
• Fast Access Time
-
• EPI Processing
55 ns
-
• Low Power Consumption
-
Latch-Up Immunity Up to 200 rnA
• Standard EPROM Pinout
75 mW During Power Down
325 mW Active Power
• Bipolar Speeds
GENERAL DESCRIPTION
The WS57C256F is an extremely HIGH PERFORMANCE 256K UV Erasable Electrically Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at speeds as fast as 55 ns
Access Time.
Two major features of the WS57C256F are its Low Power and High Speed. While operating in a TTL environment
it consumes only 65 rnA while cycling at full speed. Additionally, the WS57C256F can be placed in a standby mode
which drops operating current below 15 rnA in a TTL environment and 200 ~ in a CMOS environment.
The WS57C256F also has exceptional output drive capability. It can source 4 rnA and sink 16 rnA per output.
The WS57C256F is configured in the standard EPROM pinout which provides an easy upgrade path for systems
which are currently using standard EPROMs.
MODE SELECTION
~
PIN CONFIGURATION
MODE
CE
OE Vpp Vee
Read
VIL
VIL Vee Vee DOUT
Output Disable
X
OUTPUTS
VIH
Program
VIL VIH Vpp Vee DIN
X
A6
Vee Vee High Z
:~ 5
~"
A,:;S
A,:;9
:1 ~~ 10
o . J 11
NC :; 12
0 0 ~] 13
Program Verify
X
Program Inhibit
VIH
VIH Vpp Vee High Z
Signature*
VIL
VIL Vee Vee Encoded Data
X can be either
VIL Vpp Vee DOUT
0'::'" '"
!~
o
2
A7 3
A,f 4
A12
26r:NC
25[:lJE
27pA 14
26pA 13
25pA,
Me'
PoJ;
A.6
23pA
A' f7 0 2 2
24~~. ~ _
A,{ 8
21pA 10
23. - CElPGM All 9
20 CE/PGM
22:: 0,
A"f 10
19p 0,
21 ~= 0,
Oof 11
18 0,
O,f 12
17 Os
~~ }~g }~)~?~
O,f 13
16 O.
C'I Q
U M"
OzzOOO
GNDf 14
15 0,
I/)
CI
VfL or VIH .
• For Signature, Ag
vpp~pvcc
4 3 2 .. .1323130
1
29[= A8
As :;6
2sr: As
VIH Vee Vee High Z
Standby
,...~~ug:!~
cccc>z>cct
:..~ :..~ :.~: ::.;:.. ~ :....:
=12V, Ao is toggled, and all other address are at
TIL low. Ao =VfL =MFGR 23H, Ao =VfH =DEVICE A8H.
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS57C256F-55
WS57C256F-70
Address Access Time (Max)
55 ns
70 ns
Chip Select Time (Max)
55 ns
70 ns
Output Enable Time (Max)
25 ns
30 ns
3-57
WS57C256F
ABSOLUTE MAXIMUM RATINGS*
*Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ........ -65° to + 150°C
Voltage on any pin with
respect to GND ................ -O.6V to + 7V
VPP with respect to GND ... -O.6V to +13 .OV
ESD Protection ..................... >2000V·
OPERATING RANGE
I emperature
0" to +70"C
-55" to +125"C
Range
Comm'l
Military
Vee
+5V+ 5%
+5V±10%
DC READ CHARACTERISTICS
Over Operating Range With Vpp=Vcc.
MIN
MAX
0.4
UNITS
VOL
PARAMETER
Output Low Voltage
IOL=16mA
VOH
Output High Voltage
IOH=-4mA
ISB1
Vcc Standby Current CMOS
CE=Vcc ± 0.3V. Note 1 & 3
500
p.A
ISB2
Vcc Standby Current TTL
CE=V,H. Note 2 & 3
SYMBOL
TEST CONDITIONS
Notes 1 and 4
Vcc Active Current (CMOS)
Icc1
15
rnA
30
rnA
Military
40
rnA
Cornrn'l
Military
35
rnA
45
100
Vcc
mA
p.A
V
Vcc Active Current (TTL)
Ipp
Vpp
III
Vpp Supply Current
Vpp Read Voltage
Input Load Current
Y,N -5.5V or Gnd
ILO
Output Leakage Current
VouT =5.5V or Gnd
Vpp=Vcc
NOTES: 1) CMOS inputs: GNO ± O.3V or Vee ± O.3V.
2) TTL inputs: V1L .. O.BV, V1H ;. 2.0V.
AC READ CHARACTERISTICS
V
Cornm'l
Icc2
Notes 2 and 4
V
2.4
Vcc-0.4
-10
-10
10
/LA
10
/LA
3) A.C. Power component adds 1 rnA/MHz.
4) A.C. Power component adds 3 rnA/MHz.
Over Operating Range with Vpp = Vcc.
PARAMETER
Address to Output Delay
SYMBOL
WS57C256F-55
WS57C256F-70
MIN
MIN
MAX
tACC
50
MAX
70
CE to Output Delay
tCE
55
70
OE to Output Delay
tOE
25
30
Output Disable to Output Float
tOF
25
30
Address to Output Hold
tOH
0
AC READ TIMING DIAGRAM
UNITS
ns
0
TEST LOAD (High
Impedance Systems)
97.50
ADDRESSES
CE---"""",-
:.:~:~
~30PF
I=-
(INCWDING SCOPE
AND JIG
CAPACITANCE)
OE--------,
TIMING LEVELS
OUTPUTS
---------~::tVAuol"t:~--
Input Levels: 0 and 3V
Reference Levels: 0.8 and 2.0V
3-58
WS57C256F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA=25 ± 5°C, Vcc=5.50V ± 5%, Vpp=12.5±0.5V)
PARAMETER
Input Leakage Current
iVIN = Vee or Gnd)
Vee Supply Current During
Programming Pulse
(CE = PGM = VIL)
Vee Supply Current (Note 4)
SYMBOL
MAX.
UNIT
10
/LA
60
mA
35
mA
V
V
-10
III
Icc
Icc
VIL
VIH
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL=16mA)
-0.1
2.0
0.8
Vee+ 0.3
0.45
VOL
Output High Voltage During Verify
(IOH= -4mA)
NOTES:
MIN.
V
2.4
VOH
V
6) Vcc must be applied either cOincidentally or before Vpp and removed elthER,£Qlncldentally or after Vpp.
7) Vpp must not be greater than 14 volts including overshoot. During CE ~ PGM ~ V,L, Vpp must not be switched
from 5 volts to 12.5 volts or vice-versa.
8) During power up the PGM pin must be brought high (2 V,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA
= 25
= S.SOV
± 5°C, Vec
PARAMETER
± 5%, Vpp
= 12.5
± O.5V)
TYP
MAX
UNIT
SYMBOLS
MIN
Address Setup Time
tAS
2
CE High to OE High
teoH
2
I!S
Output Enable Setup Time
tOES
2
I!s
Data Setup Time
tos
2
I!S
Address Hold Time
tAH
0
I!S
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
Data Valid From Output Enable
tOE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
OE Low to CE "Don't Care"
toex
2
I!S
I!S
130
ns
130
ns
10
ms
lIs
3
lIS
NOTE: 9) A single shot programming algOrithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
~
ADDRESS STABLE
--1
,..IAS ..
DATA
-----1
DATA IN STABLE
!--Ios-
HIGH Z
Vpp
Vpp
Vee - - - '
locx- I-
V,H
V,L
V,H
OE
V,L
-
IoF
I+-
r--Ivs ...
-ICES"
CE/PGM
C
I+-
DATA OUT
VALID
f.IOE ....
I+-I0H -
tAH
~
Ji
~Ipw-j
I--I OES
1
~
~ I- ICOH
~
j
3-59
WS57C256F
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C256F has all
32,768x8 bits in the "1," or high state. "O's" are loaded into
the WS57C256F through the procedure of programming.
The programming mode is entered when +13.5V is applied to
the V pp pin and CElPGM is taken to V 1L. During Programming,
CE/PGM is kept at VIL' A 0.1 I1F capacitor between V pp and
GND is needed to prevent excessive voltage transients which
could damage the device. The address to be programmed is
applied to the proper address pins. 8-bit patterns are placed
on the respective data output pins. The voltage levels should
be standard TTL levels.
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with Intensity of 1200011 W/cm 2 for 20 minutes. The
WS57C256F should be about one inch from the source and
all filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS57C256F and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C256F and exposure
to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C256F to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS57C256F. This dosage can be obtained by exposure
PROGRAMMERS
Data I/O Unipak 2 or 2B, software version 12 or later; WSI's
MagicPro™ IBM PC Compatible Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS57C256F-550
WS57C256F-70CMB
WS57C256F-700
WS57C256F-700MB
3-60
SPEED
PACKAGE
TYPE
(ns)
55
70
70
70
28
32
28
28
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
Pin CEROIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
02
C2
02
02
Comm'l
Military
Comm'l
Military
Standard
MIL-STO-883C
Standard
MIL-STD-883C
WS57C256F
ADVANCE INFORMATION
WAFERSCALE INTEGRA110N, INC.
HIGH SPEED 32K
x 8
CMOS EPROM
KEY FEATURES
• EPI Processing
• Fast Access Time
-
-
35 ns
• Low Power Consumption
-
Latch-Up Immunity Up to 200 mA
ESD Protection Exceeds 2000V
• Standard EPROM Pinout
75 mW During Power Down
325 mW Active Power
GENERAL DESCRIPTION
The WS57C256F is a 32K x 8 CMOS EPROM which has been speed-enhanced from 55 ns to 35 ns. It is based
upon WaferScale's patented CMOS Split Gate EPROM technology.
The 35 ns access time of the WS57C256F is a key parameter. Traditionally, as memory densities increase, memory
access times become slower. This forces microprocessors to insert,Wait States which negatively impact system
throughput. Real Time applications cannot afford Wait States regat(jfess''bf memory density. WaferScale's unique
memories can keep pace with the fastest microprocessors. Tlie~c~tfon of speed and density available in the
WS57C256F enables the use of more complex and cori1Prehe~ive algorli:ims in Real Time applications.
WaferScale's patented CMOS Split-GateEPROMtechnoIb-9y~toniy'~bles the development of fast and dense
memory products, it also provides a higher level,of Quality an¢Reliability. Tests have proven that WSI EPROM products
program very efficiently and quickly. Also, the W$I EPROM retains its data an order of magnitude better than traditional
EPROM technologies. This combination speed, density, quality and reliability make WSI the obvious choice when
selecting a non-volatile memory supplier.
of
The WS57C256F is configured in the JEDEC standard EPROM pin configuration. It is also easily programmed
on popular EPROM programmers as well as the MagicPro™ IBM PC compatible engineering programmer offered
byWSI.
MODE SELECTION
~
PIN CONFIGURATION
MODE
CE
OE Vpp Vce
Read
VIL
VIL Vee Vee DOUT
Output Disable
X
Standby
VIH
Program
V1L
Program Verify
X
OUTPUTS
,..
~
0( 01(
VIH Vee Vee High Z
X
Vee Vee HighZ
VIH Vpp Vee DIN
VIL Vpp Vee DOUT
Program Inhibit
VIH VIH Vpp Vee High Z
Signature*
VIL
VIL Vee Vee Encoded Data
1:0 g :! ,
> z> c c(
:..~:..; ~;: ::..~:..~ ~~
432"'323130
1
29~: A,
A,
27'A4 :~7
A"
A. :;8
NC
A2 :~ 9
25(: i5E
A, :~ 10
24~:. A10
A, :]11
23:: CE/PGM
NC :]12
22:: 0,
0 0 :J 13
21~: 0&
As :~5
A, :;6
0
26~:
!~ !H~ ~~ !l!.lH~
"'",,'''''''
<5
Q (,)
o zzOOO
N
X can be either V1L or VIH •
-For Signature, Ag = 12V, Ao is toggled, and all other address are at
TTL low. Ao= V1L = MFGR 23H, Ao= V1H = DEVICE ASH,
2sr:
(OJ
OIl'
01»
CI
vPP[~~Vcc
A12 [ 2
A,[ 3
AoC4
A,C5
A.[ 6
A31:
A2
7
8
A:~ 9
A,c 10
OoC 11
0, c 12
O,C 13
GNDC 14
27~A,.
26 JA13
25JA,
24JA.
23 JA l1
0 2 2 JOE
21 JAiD
20 CEtPGM
19 JO,
18 O.
17 0,
16 O.
15 J0 3
TOP
PRODUCT SELECTION GUIDE
WS57C256F-35
WS57C256F-45
Address Access Time (Max)
PARAMETER
35 ns
45 ns
Chip Select Time (Max)
35 ns
45 ns
Output Enable Time (Max)
20 ns
25 ns
3-61
WS57C256F
"Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
ABSOLUTE MAXIMUM RATlNGS*
Storage Temperature ........ -65° to + 150°C
Voltage on any pin with
respect to GND ................ -O.6V to + 7V
VPP with respect to GND ... -O.6V to +13.0V
ESD Protection ..................... > 2000V
OPERATING RANGE
Temperature
0' to +70'C
-55' to +125'C
Range
Comm'l
Military
Vee
+5V±5%
+5V±10%
DC READ CHARACTERISTICS Over Operating Range with Vpp = Vee·
SYMBOL
VOL
PARAMETER
Output Low Voltage
IOL=16mA
VOH
Output High Voltage
IOH=-4mA
1581
Vcc Standby Current CMOS
CE=Vcc ± 0.3V. Note 1
1582
Vcc Standby Current TTL
CE=VIH. Note 2
Vcc Active Current (CMOS)
ICCl
MAX
UNITS
0.4
V
500
pA
2.4
Notes 1 and 3
ICC2
Vcc Active Current (TTL)
Ipp
Vpp
III
Vpp Supply Current
Vpp Read Voltage
Input Load Current
VIN -5.5V or Gnd
ILO
Output Leakage Current
V
NOTES: 1) CMOS inpuls: GNO ± 03>1 or Vee
2) TTL inputs: V1L " OIN, V 1H .. 2.fN.
MIN
TEST CONDITIONS
Notes 2 and 3
V
5
mA
Comm'l
30
rnA
Military
40
rnA
Comm'l
35
rnA
Military
45
100
Vcc
10
rnA
pA
V
p.A
10
p.A
Vpp=Vcc
± 03>1.
Vcc-O.4
-10
ouT =5.5V or Gnd
-10
3) A.C. Power component adds 3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vec.
PARAMETER
SYMBOL
-_....
WS57C256F-35
WS57C256F-45
MIN
MIN
MAX
MAX
Address to Output Delay
t ACC
35
45
CE to Output Delay
OE to Output Delay
Output Disable to Output Float
Address to Output Hold
tCE
35
45
tOE
tDF
tOH
15
15
20
20
AC READ TIMING DIAGRAM
UNITS
ns
0
0
TEST LOAD (High Impedance Systems)
97.50
ADDRESSES
CE - - - - - - . .
:::~;~30PF
I-=- CAPACITANCE)
(INCWDING SCOPE
AND JIG
OE--------------,
TIMING LEVELS
OUTPUTS---------~~~~!l~--
3-62
Input Levels: 0 and 3V
Reference Levels: 0.8 and 2.0V
WS57C256F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.50V ± 5%, Vpp
PARAMETER
l,n put Leakage Current
VIN = vee or Gnd)
Vee Supply Current During
Programming Pulse
(eE = PGM = VIL)
Vee Supply Current (Note 4)
MIN.
SYMBOL
MAX.
UNIT
10
/.LA
60
mA
35
mA
V
V
-10
III
Icc
Icc
VIL
VIH
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL= 16mA)
-0.1
2.0
0.8
Vee + 0.3
0.45
VOL
Output High Voltage During Verify
(IOH= -4mA)
NOTES.
12.5 ± 0.5V)
VOH
V
2.4
V
6) Vcc must be applied either cOincidentally or before Vpp and removeQ.§lther cOincidentally or after Vpp.
7) Vpp must not be greater than 14 volts including overshoot. During CE = PGM = V,L, Vpp must not be switched
from 5 volts to 12.5 volts or vice-versa.
8) During power up the PGM pin must be brought high k V,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA
= 25
± 5°C, Vee
PARAMETER
= 5.50V
± 5%, Vpp
= 12.5
± 0.5V)
MAX
MIN
t AS
2
!-IS
CE High to OE High
teoH
2
!-IS
Output Enable Setup Time
tOES
2
!-IS
tos
2
!-IS
Address Hold Time
tAH
0
!-IS
Data Hold Time
tOH
2
tOF
0
Data Setup Time
Chip Disable to Output Float Delay
TYP
UNIT
SYMBOLS
Address Setup Time
!-IS
130
13(}
Data Valid From Output Enable
tOE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
OE Low to CE "Don't Care"
toex
2
ns
ns
!-IS
10
3
ms
!-IS
PROGRAMMING WAVEFORM
ADDRESSES
~
_ _ _+f
I-'AS ..
HIGHZ
DATA IN STABLE
DATA_
-4-'OH ....
--'os""
)
'-'IoE ...
V••
VPF
Vee
--1
--'vs-
'ocx- r-
-4-'CES"
V,H
CE/PGM
V'L
V ,H
DE
V'L
K=
ADDRESS STABLE
~
i
~'PW....j
l---'
oE8
1
~
tAH
DATA OUT
VALID
-
'DF
t--
Ir--
l-
~ r- 'COH
~
J
3-63
WS57C256F
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C256F has all
32,768x8 Bits in the "1," or high state. "O's" are loaded into
the WS57C256F through the procedure of programming.
The programming mode is entered when +13.5V is applied to
the V pp pin and CEJPGM is taken to V1L • During Programming,
CE/PGM is kept at V 1L • A 0.1 ).IF capacitor between V pp and
GND is needed to prevent excessive voltage transients which
could damage the device. The address to be programmed is
applied to the proper address pins. 8-bit patterns are placed
on the respective data output pins. The voltage levels should
be standard TTL levels.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C256F to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS57C256F. This dosage can be obtained by exposure
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 12000).1 W/cm 2 for 20 minutes. The
WS57C256F should be about one inch from the source and
all filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS57C256F and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C256F and exposure
to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C256F-350
WS57C256F-45CMB
WS57C256F-450
WS57C256F-450MB
WS57C256F-55CMB
WS57C256F-550MB
35
45
45
45
55
55
3-64
PACKAGE
TYPE
28
32
28
28
32
28
Pin CEROIp,
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pad CLLCC
Pin CEROIp,
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
02
C2
02
02
C2
02
Comm'l
Military
Comm'l
Military
Military
Military
Standard
MIL-STO-883C
Standard
MI L-STO-883C
MIL-STO-883C
MIL-STO-883C
---- - -
-5F==~~
-...,
.--. - ........
--
WS27C256L
~~
ADVANCE INFORMATION
WAFERS(,ALE INTEGRA TION, INC.
32K
X
8 CMOS EPROM
KEY FEATURES
• 300 Mil Dip or Standard 600 Mil Dip
• Fast Access Time
-
90 ns
• EPI Processing
• Low Power Consumption
-
0.5 mW During Power Down
150 mW Active Power @ 5 MHz
-
Latch·Up Immunity to 200 mA
ESD Protection Exceeds 2000V
• Drop-In Replacement for 27C256 or 27256
GENERAL DESCRIPTION
The WS27C256L is a HIGH PERFORMANCE 256K UV Erasable Electrically Programmable Read Only Memory. It
is manufactured in WSl's latest CMOS EPROM technology which enables it to operate at speeds as fast as 90 ns
access time over the full operating range. (If faster speeds are required, contact your WSI sales representative.)
The WS27C256L can directly replace any 32K x 8 EPROM which conforms to the JEDEC standard. Examples of
this would be as follows: 27256, 27C256, or 27C256F. It can be easily programmed using standard EPROM program·
mers or the MagicPro™ IBM PC compatible engineering programmer offered by WSI.
The WS27C256L is also available in a 300 mil Dip. The pin configuration remains the same as the 600 mil wide package
and the programming algorithms are unchanged. This allows for a sJmple PCB layout Change to take advantage of
a 50% reduction in required ,board space. An upgrade path to a 512K product (WS27C512F) is provided.
The high-speed (90 ns access time) of the WS27C256L enables it to run in a "No Wait State" environment with such
microprocessors as the 16 MHz 80286. Slower speed versions are also available for lower performance applications.
The WS27C256L is configured in the standard EPROM pinout which provides an easy upgrade path for systems which
are currently using standard EPROMs.
PIN CONFIGURATION
MODE SELECTION
~------------------------------~
...
~
MODE
CE
Read
VIL
Output Disable
~
8::0 8 :!
~
cc>z>cc
OE Vpp Vee
OUTPUTS
VIL Vee Vee DouT
X
VIH Vee Vee High Z
Standby
VIH
X Vee Vee High Z
Program
VIL
Program Verify
X
Program Inhibit
VIH
VIH Vpp Vee DIN
VIL Vpp Vee DOUT
VIH Vpp Vee High Z
x can be either V1L or VIH .
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS27C256L-90
WS27C256L-12
Address Access Time (Max)
90 ns
120 ns
Chip Select Time (Max)
90 ns
120 ns
Output Enable Time (Max)
30 ns
35 ns
3-65
WS27C256L
*Notlce: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
ABSOLUTE MAXIMUM RA TINGS*
Storage Temperature .......... -65 0 C to +150 0 C
Voltage on any pin with
respect to GND ..................... -0.6V to +7V
VPP with respect to GND ........ -0.6V to +14.0V
ESD Protection ......................... >2000V
OPERATING RANGE
TEMPERATURE
RANGE
Military
-55°C to +125°C
Commercial
0° to +70oC
Vee
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range With Vpp= Vcc.
SYMBOL
PARAMETER
MAX
UNITS
0.4
VOL
Output Low Voltage
IOL= 4mA
VOH
Output High Voltage
IOL=-1mA
ISBI
Vcc Standby Current CMOS
CE=Vcc
ISB2
Vcc Standby Current TTL
CE=VIH. Note 2
IccI
Vcc Active Current (CMOS)
ICC2
MIN
TEST CONDITIONS
V
2.4
V
± 0.3V. Note 1
100
p.A
3
mA
Note 1
17 (Note 3)
mA
33 (Note 3)
mA
Vcc Active Current (TTL)
Note 2
Ipp
Vpp Supply Current
Vpp= Vcc
Vpp
Vpp Read Voltage
100
p.A
Vcc - 0.4
Vcc
V
III
Input Load Current
VIN = 5.5V or Gnd
- 10
10
p.A
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
- 10
10
p.A
NOTES: I) CMOS inputs: GND ± O.3V or Vee ±
2) TTL inputs: V1L .. OJN, V1H ;. 2.0V.
O.3V.
3)
A.C. Active power component is 2.5 rnA/MHz (Total Power
AC READ CHARACTERISTICS Over Operating Range with V pp
PARAMETER
Address to Output Delay
SYMBOL
MAX
WS27C256L-12
MIN
90
120
CE to Output Delay
tCE
90
120
OE to Output Delay
tOE
30
35
Output Disable to Output Float
tDF
30
35
Address to Output Hold
tOH
AC READ TIMING DIAGRAM
UNITS
MAX
tACC
0
AC + DC).
= Vcc.
WS27C256L-90
MIN
=
ns
0
TEST LOAD (High
Impedance Systems)
3200
2.01V~
ADDRESSES
CE - - - - - - . ,
D.U.T.~ 100 pF
I=
(INCWDING SCOPE
AND JIG
CAPACITANCE)
OE-------,
TIMING LEVELS
OUTPUTS
3-66
---------~~~~!l~--
Input Levels: .45 and 2.4
Reference Levels: 0.8 and 2.0V
WS27C256L
PROGRAMMING INFORMATION
DC CHARACTERISTICS
(TA = 25
± 5°C, Vee = 5.5V ± 10%, Vpp = 12.5 ± 0.5V)
SYMBOL
PARAMETER
Input Leakage Current
iVIN = Vee or Gnd}
Vpp Supply Current During
Programming Pulse
(CE = PGM = V,d
Vee Supply Current
MIN.
MAX.
UNIT
10
/-LA
60
mA
33
mA
-10
III
Ipp
Icc
V ,L
V,H
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL=4mA)
-0.1
2.0
0.8
Vee+0.3
V
0.4
VOL
V
V
Output High Voltage During Verify
VOH
2.4
V
(low-1mA)
NOTES: 5) Vcc must be applied either cOincidentally or before Vpp and remove~lth~lncldentaily or after Vpp.
6) Vpp must not be greater than 14 volts including overshoot. During CE ~ PGM = V,L, Vpp must not be switched
from 5 volts to 12.5 volts or vice· versa.
7) During power up the PGM pin must be brought high (~V,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS
(TA = 25
PARAMETER
± 5°C, Vee = 5.5V ± 10%, Vpp = 12.5 ± 0.5V)
MAX.
SYMBOL
t AS
MIN.
2
I'S
to OE High
Output Enable Setup Time
teoH
2
1,5
tOES
2
1,5
Data Setup Time
Address Hold Time
Data Hold Time
tos
tAH
2
1,5
0
1,5
tOH
2
Chip Disable to Output Float Delay
tOF
0
Data Valid from Output Enable
tOE
Vpp Setup Time
PGM Pulse Width
tvs
2
tpw
tocx
1
Address Setup Time
CE High
OE Low to CE "Don't Care"
TYP.
UNIT
I'S
55
ns
ns
10
ms
55
,,5
3
2
1'5
NOTE: 8) Single pulse programming algorithms should use one 10 ms PGM pulse per byte.
PROGRAMMING WA VEFORM
ADDRESSES
~
C
ADDRESS STABLE
-.j
.... I AS ...
DATA IN STABLE
DATA~
.... Ios-
Vcc~
IAH
DATA OUT
VALID
·IoE-
I-IOH -
Vpp
Vpp
HIGH Z
-
- IOF
.... Ivs .....
locx-
-ICES'"
V ,H
CE/PGM
V ,L
V ,H
DE
V,L
Xi
~Ipw~
r-
1-
teoH
rt1f}.rI
I--IOES
1
~
J
3·67
WS27C256L
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS27C256L has all
32,768x8 Bits in the "1," or high state. "D's" are loaded into
the WS27C256L through the procedure of programming.
The programming mode is entered when +12.5V is applied to
the V pp pin and CEJPGM is taken to V1L. During Programming,
CE/PGM is kept at V1L' A 0.1 ~F capacitor between V pp and
GND is needed to prevent excessive voltage transients which
could damage the device. The address to be programmed is
applied to the proper address pins. a-bit patterns are placed
on the respective data output pins. The voltage levels should
be standard TTL levels.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS27C256L to an ultra-violet light
source. A dosage of 15W second/cm 3 is required to completely
erase a WS27C256L. This dosage can be obtained by exposure
to an ultra-violet lamp with wavelength of 2537 Angstroms and
intensity of 12000~ W/cm 3 for 20 minutes. The WS27C256L
should be about one inch from the source and all filters should
be removed from the UV light source prior to erasure.
It is important to note that the WS27C256L and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS27C256L and exposure
to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
ORDERING INFORMATION
PART NUMBER
WS27C256L-90D
WS27C256L-90DMB
WS27C256L-90P
WS27C256L-90S
WS27C256L-9OT
WS27C256L-9OTMB
WS27C256L-12CMB
WS27C256L-12D
WS27C256L-12DMB
WS27C256L-12P
WS27C256L-12S
WS27C256L-12T
WS27C256L-12TMB
3-68
SPEED
PACKAGE
TYPE
(n5)
90
90
90
90
90
90
120
120
120
120
120
120
120
28
28
28
28
28
28
32
28
28
28
28
28
28
Pin CERIlAP, 0.6"
Pin CERDIp, 0.6"
Pin Plastic DIP, 0.6"
Pin Plastic DIP, 0.3"
Pin CERDIp, 0.3"
Pin CERDIp, 0.3"
Pad CLLCC
Pin CERDIp, 0.6"
Pin CERDIp, 0.6"
Pin Plastic DIP, 0.6"
Pin Plastic DIP, 0.3"
Pin CERDIp, 0.3"
Pin CERDIp, 0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
D2
D2
P3
S2
T2
T2
C2
D2
D2
P3
S2
T2
T2
Comm'l
Military
Comm'l
Comm'l
Comm'l
Military
Military
Comm'l
Military
Comm'l
Comm'l
Comm'l
Military
Standard
M IL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
MIL-STD-883C
Standard
MIL-STD-883C
Standard
Standard
Standard
MI L-STD-883C
.... ...., ....,...---_ ........
::'.................
==
== :====
~
~aFAf
WS2C
____________________________
7~2~5~6~F
PRELIMINARY
WAFERsrALE INTEGRA 110N, INC.
COMMERCIAL 32K x 8 CMOS EPROM
KEY FEATURES
• EPI Processing
• Fast Access Time
-
-
90 ns
• Low Power Consumption
-
Latch-Up Immunity Up to 200 mA
• Standard EPROM Pinout
1 mW During Power Down
325 mW Active Power
• Compatible with WS57C256F
The WS27C256F is an extremely HIGH PERFORMANCE 256K UV Erasable Electrically Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at speeds as fast as 90
ns Access Time. (If faster speeds are required, contact your WSI sales representative.)
Two major features of the WS27C256F are its Low Power and High Speed. While operating in a TTL environment
it consumes only 65 mA while cycling at full speed. Additionally, the WS27C256F can be placed in a standby mode
which drops operating current below 1 mA in a TTL environment and 100 !lA in a CMOS environment.
The WS27C256F is configured in the standard EPROM pinout which provides an easy upgrade path for systems
which are currently using standard EPROMs.
MODE SELECTION
PIN CONFIGURA TlON
~
MODE
CE
OE Vpp Vee
Read
VIL
VIL Vee Vee DOUT
Output Disable
X
Standby
VIH
Program
VIL
OUTPUTS
VIH Vee Vee High Z
X
Vee Vee High Z
VIH Vpp Vee DIN
Program Verify
X
Program Inhibit
VIH
VIH Vpp Vee High Z
Signature*
VIL
VIL Vee Vee Encoded Data
VIL Vpp Vee DOUT
X can be either V1L or VIH .
'For Signature, A g = 12V, Ao is toggled, and all other address are at
TIL low. Ao V 1L MFGR 23H, Ao V 1H DEVICE A8H.
= =
= =
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS27C256F-90
WS27C256F-12
Address Access Time (Max)
90 ns
120 ns
Chip Select Time (Max)
90 ns
120 ns
Output Enable Time (Max)
30 ns
35 ns
3-69
D
WS27C256F
ABSOWTE MAXIMUM RATINGS·
*Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature .......... -65° to +150°C
Voltage on any pin with
respect to GND .............. -0.6V to +7V
Vpp with respect to GND ........ -0.6V to +14V
ESD Protection ...................... >2000V
OPERATING RANGE
TEMPERATURE
Vcc
+5V ± 10%
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range With Vpp= Vee.
PARAMETER
TEST CONDITIONS
= 4 mA
= -1 mA
= Vec ± 0.3V (Note
= VIH (Note 2)
VOL
Output Low Voltage
10L
VOH
Output High Voltage
10H
ISB1
Vee Standby Current CMOS
CE
ISB2
Vcc Standby Current TIL
CE
Icc1
Vcc Active Current (CMOS)
Note 1
Icc2
Vcc Active Current (TIL)
Note 2
Vpp
Ipp
Vpp Supply Current
Vpp
Vpp Read Voltage
III
Input Load Current
ILo
Output Leakage Current
NOTES:
PARAMETER
CE to Output Delay
UNITS
0.4
V
V
2.4
100
JJ.A
1
rnA
I Comm'l
30 (Note 3)
mA
J Comm'l
35 (Note 3)
mA
100
JJ.A
V
-10
Vcc
10
-10
10
1)
= Vce
= 5.5V or Gnd
VOUT = 5.5V or Gnd
VIN
3)
A.C.
Active power component is 3
Over operating Range with Vpp
SYMBOL
Address to Output Delay
MAX
Vcc -0.4
1) CMOS inputs: GND ± O.3V or Vee ± O.3V.
2) TTL inputs: V 1L .. O.8V, V 1H ~ 2.0V.
AC READ CHARACTERISTICS
MIN
rnA/MHz (Total
Power =
WS27C256F-12
MIN
MAX
tACC
90
120
120
t CE
90
OE to Output Delay
tOE
30
35
Output Disable to Output Float
t OF
30
35
Address to Output Hold
t OH
AC READ TIMING DIAGRAM
IlA
AC + DC).
= Vcc.
WS27C256F-90
MIN
MAX
0
IlA
UNITS
ns
0
TEST LOAD (High Impedance Systems)
320Q
ADDRESSES
..
C E - - -.........
:.:~;~
I-=-
100pF
(INCWDING SCOPE
AND JIG
CAPACITANCE)
O E - - - - - -.........
TIMING LEVELS
OUTPUTS --------_a.t"VALiDr~+_-
Input Levels: .45 and 2.4
Reference Levels: 0.8 and 2.0V
3-70
WS27C256F
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA = 25 ± 5°C, Vee = 5.5V ± 10%, Vpp = 13.5 ± 0.5V)
PARAMETER
Input Leakage Current
(V,N = Vee or Gnd)
Vee Supply Current During
Programming Pulse
(CE = PGM = V,L)
Vec Supply Current (Note 3)
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL=4mA)
Output High Voltage During Verify
(IOH=-1mA)
NOTES:
MIN.
SYMBOL
-10.
III
Icc
Icc
V,L
V,H
MAX.
UNIT
10
J.LA
60
mA
35
0.8
Vee +0.3
-0.1
2.0
0.45
VOL
VOH
mA
V
V
V
2.4
V
5) Vcc must be applied either cOincidentally or before Vpp and remove~lth~InCldentaily or after Vpp.
6) Vpp must not be greater than 14 volts including overshoot. During CE = PGM = V,L , Vpp must not be switched
from 5 volts to 13.5 volts or vice-versa.
7) During power up the PGM pin must be brought high (~ V,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA
= 25
± 5°C, Vee
PARAMETER
= 5.5V
= 13.5
± 5%, Vpp
± 0.5V)
SYMBOLS
MIN
Address Setup Time
tAS
2
~s
CE High to OE High
teoH
2
~s
Output Enable Setup Time
tOES
2
~s
Data Setup Time
tos
2
~s
Address Hold Time
tAH
0
~s
tOH
2
~s
Chip Disable to Output Float Delay
tOF
0
Data Valid From Output Enable
tOE
Data Hold Time
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
OE Low to CE "Don't Care"
toex
2
TYP
MAX
UNIT
55
ns
55
ns
10
ms
~s
3
~s
NOTE: 8) Single pulse programming algorithms should use one 10 ms PGM pulse per byte.
PROGRAMMING WA VEFORM
ADDRESSES
~
~
~IAS""
DATA~
DATA IN STABLE
~Ios"'"
HIGH Z
f.IOE .....
I-I OH -
Vcc
--.I ~Ivsf.- ICES"
V,H
CEIPGM
V,L
V,H
OE
V,L
tocx -
j
~tpw..j
~
i--tOES
1
~
tAH
:--
DATA OUT
VALID
V••
V••
C
ADDRESS STABLE
-
-
I-
IOF
I--
tCOH
~
/
3-71
WS27C256F
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS27C256F has all
32,768x8 bits in the "1," or high state. "O's" are loaded into
the WS27C256F through the procedure of programming.
The programming mode is entered when +13.5V is applied to
the Vp.e...Pin, and CE/PGM is taken to V1L • During Programming, CE/PGM is kept at V1L• A 0.1 I1F capacitor between Vpp
and GND is needed to prevent excessive voltage transients,
which could damage the device. The address to be programmed is applied to the proper address pins. 8-bit patterns
are placed on the respective data output pins. The voltage levels
should be standard TTL levels.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS27C256F to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS27C256F. This dosage can be obtained by exposure
to an ultra-violet lamp with wavelength of 2537 Angstroms (A.)
with intensity of 1200011 W/cm 2 for 20 minutes. The
WS27C256F should be about one inch from the source and
all filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS27C256F and similar devices
will erase with light sources having wavelengths shorter than
4000A.. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS27C256F and exposure
to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
PROGRAMMERS
Data 110 Unipak 2 or 2B, software version 12 or later, familyl
pinout code 3C/32; WSI's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
WS27C256F-90D
WS27C256F-120
90
120
28 Pin CEROIp, 0.6"
28 Pin CEROIp, 0.6"
02
02
Comm'l
Comm'l
Standard
Standard
3-72
iF==~~
----
--
WS27C512F
r..-..-..-_
~~~==
ADVANCE INFORMATION
WAFERSCALE INTEGRATION, INC.
HIGH SPEED 64K x 8 CMOS EPROM
KEY FEA TURES
• Fast Access Time
-
• EPI Processing
70 ns
-
• Low Power Consumption
-
75 mW During Power Down
325 mW Active Power
Latch-Up Immunity Up to 200 mA
• Standard EPROM Pinout
• Bipolar Speeds
GENERAL DESCRIPTION
The WS27C512F is an extremely HIGH PERFORMANCE 512K UV Erasable Electrically Programmable Read Only
Memory. It is manufactured in an advanced CMOS technology which allows it to operate at speeds as fast as 70
ns Access Time.
Two major features of the WS27C512F are its Low Power and High Speed. While operating in a TTL environment
it consumes only 72 rnA while cycling at full speed. Additionally, the WS27C512F can be placed in a standby mode
which drops operating current below 2 mA in a TTL environment and 200 IlA in a CMOS environment.
The WS27C512F also have exceptional output drive capability. It can source 1 mA and sink 4 mA per output.
The WS27C512F is configured in the standard EPROM pinout which provides an easy upgrade path for systems which
are currently using standard EPROMs.
MODE SELECTION
~
PIN CONFIGURA TION
MODE
CE
OEI
Vpp
Vee
Read
VIL
VIL
Vee
DOUT
C
VIH
Vee
High Z
High Z
Output Disable
OUTPUTS
Standby
VIH
X
Vee
Program
VIL
Vpp
Vee
DIN
Program Verify
VIL
VIL
Vee
DOUT
Program Inhibit
VIH
VIH
Vee
High Z
Signature'
VIL
VIL
Vee
Encoded Data
X can be either VIL or VIH
'For Signature, ~ = 12V, AD is toggled, and all other address are
at TTL low. Ao = VIL = MFGR 23H, Ao = VIH = DEVICE AAH.
TOP
PRODUCT SELECTION GUIDE
PARAMETER
WS27C512F- 70
WS27C512F-90
Address Access Time (Max)
70 ns
90 ns
Chip Select Time (Max)
70 ns
90 ns
Output Enable Time (Max)
25 ns
30 ns
3-73
WS27C512F
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature .......... -65° C to +150° C
Voltage on any pin with
respect to G N D ..................... -0. 6V to +7V
VPP with respect to GND ........ -0.6V to +13.0V
ESD Protection ......................... >2000V
OPERATING RANGE
Range
Temperature
Vee
Comm'l.
0° to +70°C
+5V ± 5%
Military
-55· to +125·C
+5V ± 10%
·Notice: Stresses above those listed here may
cause permanent damage to the device. This is a
stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect device reliability.
DC READ CHARACTERISTICS Over Operating Range with Vpp=Vee.
SYMBOL
PARAMETER
TEST CONDITIONS
VOL
Output Low Voltage
IOL = 4 mA
VOH
Output High Voltage
IOH = -1 mA
ISBI
Vee Standby Current CMOS CE=Vee ± 0.3V. Note 1
ISB2
Vee Standby Current TTL
CE=VIH. Note 2
Ice1
Vee Active Current (CMOS)
Notes 1 and 3
Comm'l.
Military
Ice2
Vec Active Current (TTL)
Notes 2 and 3
Comm'l.
Military
Ipp
Vpp Supply Current
Vpp=Vce
Vpp
Vpp Read Voltage
Input Load Current
III
ILO
NOTES:
MIN
MAX
0.4
UNITS
V
2.4
V
Output Leakage Current
VouT=5.5V or Gnd.
CMOS inputs: GND ± O.3V or Vcc ± O.3V.
3) A.C. Power component
2) TTL inputs: V1L .;; o.av, V1H " 2.0V.
1)
adds
IJ.A
2
30
40
35
45
mA
mA
mA
mA
mA
100
IJ.A
-10
Vcc
10
p.A
-10
10
p.A
Vee-{).4
VIN=5.5V or Gnd
200
V
3 rnA/MHz.
AC READ CHARACTERISTICS Over Operating Range with Vpp = Vee.
PARAMETER
SYMBOL
WS27C512F-70
MIN
MAX
WS27C512F-90
MIN
MAX
Address to Output Delay
tAee
70
CE to Output Delay
DE to Output Delay
teE
70
90
tOE
25
30
Output Disable to Output Float
toF
25
30
Address to Output Hold
tOH
90
0
AC READ TIMING DIAGRAM
UNITS
ns
0
TEST LOAD (High
Impedance Systems)
97.5Q
ADDRESSES
CE - - - - - . . .
2.0W
o----l\;"--,
D.U.T.~ 30 pF
I-=- AND
(INCWDING SCOPE
JIG
CAPACITANCE)
OE--------~
TIMING LEVELS
OUTPUTS---------~~~VAUOI~~--
Input Levels: 0.4 and 2.4V
Reference Levels: 0.8 and 2.0V
3-74
WS27C512F
PROGRAMMING INFORMA TION
DC CHARACTERISTICS
(TA
=
=
25 ± 5°C, Vee
pARAMETER
5.5V ± 5%, Vpp
12.5 ± 0.5V)
SYMBOL
MIN
MAX
UNIT
III
-10
10
J1.A
lee
60
rnA
lee
25
rnA
Input Leakage Current
(VIN = Vee or Gnd)
Vee Supply Current During
Programming Pulse
(CE = PGM = VIL)
Vee Supply Current (Note 3)
Input Low Level
VIL
-0.1
Input High Level
Output Low Voltage During Verify
(lOL = 4 rnA)
Output High Voltage During Verify
(IOH = -1 rnA)
VIH
2.0
0.8
Vee
V
+ 0.3
0.45
VOL
V
2.4
VOH
V
V
NOTES: 4) Yee must be applied either coincidentally or before Ypp and removed either coincidentally or after Ypp.
5) Ypp must not be greater than 14 volts including overshoot. During eE = PGM = Y IL, Ypp must not be switched
from 5 volts to 12.5 volts or vice-versa.
6) During power up the PGM pin must be brought high (;. Y IH) either coincident with or before power is applied to Ypp.
AC CHARACTERISTICS (TA
= 25 ±
= 5.5V ±
5°C, Vee
PARAMETER
Address Setup Time
5%, Vpp
= 12.5 ±
0.5V)
SYMBOL
MIN
tAS
2
TYP
MAX
UNIT
IlS
Vpp Hold Time
tVH
2
IlS
Data Setup Time
tos
2
IlS
Address Hold Time
tAH
0
IlS
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tDF
0
Data Valid From Chip Enable
teE
Vpp Setup Time
tvs
2
PGM Pulse Width
tpw
1
IlS
70
70
ns
ns
IlS
35
ms
NOTES: 7. A single shot programming algorithm should use one 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
~
K=
ADDRESS STABLE
~
__ I AS -
DATA IN STABLE
DATA
- - Ios -
I - IOH -
- - I vs -
_ I VH-
HIGH Z
~ICE-
tAH
DATA OUT
VALID
-+
IOF
VIH
OE/V"
I+-
-
Vll~
VIH
CE/PGM
VIL
~
_ I vs -
- - I VH
J'
r-I'w~
3-75
WS27C512F
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS27C512F has all 65,536x8
bits in the "1," or high state. "O's" are loaded into the
WS27C512F through the procedure of programming.
The programming mode is entered when +13.5V is applied to
the OEN pp pin and CEtPGM is taken to V 1L • During Programming, CE/PGM is kept at V 1L • A 0.1 IJ,F capacitor between V pp
and GND is needed to prevent excessive voltage transients,
which could damage the device. The address to be programmed is applied to the proper address pins. 8-bit patterns
are placed on the respective data output pins. The voltage levels
should be standard TTL levels.
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 120001J, W/cm 2 for 20 minutes. The
WS27C512F should be about one inch from the source and all
filters should be removed from the UV light source prior to
erasure.
It is important to note that the WS27C512F and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS27C512F and exposure
to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows should be covered by an opaque label or substance.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS27C512F to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS27C512F. This dosage can be obtained by exposure
PROGRAMMERS
Data 110 Unipak 2B; WSI's MagicPro™ IBM PC Compatible
Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
WS27C512F-70C
WS27C512F-700
WS27C512F-90C
WS27C512F-90CM
WS27C512F-90CMB
WS27C512F-900
WS27C512F-900M
WS27C512F-900MB
3-76
SPEED
PACKAGE
TYPE
(ns)
70
70
90
90
90
90
90
90
32
28
32
32
32
28
28
28
Pad CLLCC
Pin CEROIp,
Pad CLLCC
pad CLLCC
Pad CLLCC
Pin CEROIp,
Pin CEROIp,
Pin CEROIp,
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
C2
02
C2
C2
C2
02
02
02
Comm'l
Comm'l
Comm'l
Military
Military
Comm'l
Military
Military
Standard
Standard
Standard
Standard
MIL-STO-883C
Standard
Standard
MI L-STO-883C
--===~E
:' =r =r =r ==
==______________________________________________________________
WS27C010L
__
~
-.r~~
ADVANCE INFORMATION
WAFERSCALE INTEGRA TION, INC.
1 Meg (128K x 8) BYTE-WIDE EPROM
KEY FEATURES
• Compatible with JEDEC 27256 and
27512 EPROMs
• Fast Programming
• Simplified Upgrade Path
• High Performance CMOS
-
Vpp and PGM Are "Don't Care" During
Normal Read Operation
-
15 Seconds Typical
90 ns Access Time
65 mA Active Power
• JEDEC Standard Pin Configuration
• EPI Processing
-
-
-
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
32 Pin Dip Package
GENERAL DESCRIPTION
The WS27C010L is a high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 128 K-words of 8 bits each. Its pin-compatibility with byte-wide JEDEC EPROMs allows upgrades
from 16K through 512K EPROMs. The "Don't Care" feature during read operations allows memory expansions up
to 8M bits with no printed circuit board changes.
The WS27C010L can directly replace lower density 28-pin EPROMs by adding an A 16 address line and Vcc jumper.
During the normal read operation PGM and Vpp are in a "don't care" state which allows higher order addresses,
such as A 17 , A 18 , and A 19 to be connected without affecting the normal read operation. This allows memory upgrades
to 8M bits without hardware changes. The WS27C010L will also be offered in a 32-pin plastic Dip with the same
upgrade path.
The WS27C010L provides microprocessor-based systems with extensive storage capacity for large portions of operating
system and application software. Its 90-ns access time provides no-wait-state operation with high-performance CPUs
such as the 16-MHz 80186. The WS27C010L offers a single chip solution for the code storage requirements of 100%
firmware-based equipment. Frequently-used software routines are quickly executed from EPROM storage, greatly
enhancing system utility.
The WS27C010L is one of a three product megabit EPROM family. Other family members are the WS57C010F and
WS57C210F. The WS57C010F is the high-speed version of the WS27C010L. The WS57C210F is organized in a 64K x 16
configuration which is optimal for wordwide systems.
The WS27C010L is manufactured using WSI's advanced CMOS technology.
PRODUCT SELECTION GUIDE
PARAMETER
WS27C010L·90
WS27C010L·12
WS27C010L·15
Address Access Time (Max)
90 ns
120 ns
150 ns
Chip Select Time (Max)
90 ns
120 ns
150 ns
Output Enable Time (Max)
30 ns
40 ns
50 ns
NOTE: Plastic Dip will be available in the second half of 1988.
3-77
WS27C010L
ABSOWTE MAXIMUM RATINGS·
·Notice: Stresses above those listed under ''Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage Temperature ........... -65°C to +125°C
Voltages on Any Pin with
Respect to Ground .............. -0.6V to + 7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vee Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ....................... > 2000V
NOTICE: Specifications contained within the following tables are subject to change.
READ OPERATION
DC CHARACTERISTICS O°C'" TA ... +70oC; Vee (Comm'I/Military) = +5V ± 10%
LIMITS
SYMBOL
PARAMETER
CONDITIONS
MIN
MAX
UNITS
= 5.5V
VOUT = 5.5V
10
~
10
~
Vpp '" Vee
CE = V IH
10
~
2
mA
III
Input Load Current
ILO
Output Leakage Current
IpPI(I)
Vpp Load Current
ISB (TIL)
Vee Current Standby
ISB (CMOS)
Vee Current Standby
leel(l)
Vee Current Active
CE
lee2 (CMOS)
Vee Active Current (Note 3)
CE
V IL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOH
Vpp(l)
Output High Voltage
VIN
= Vee
= OE = V IL
= OE = OV
100
IlA
40
mA
14
mA
-0.1
+0.8
V
2.0
Vee +1
V
0.4
V
CE
IOL
IOH
Vpp Read Voltage
Vee
= 4 mA
= -1 mA
= 5.0V ±
2.4
-0.1
0.25
V
V
Vee +1
AC CHARACTERISTICS O°C ... T A'" + 70°C
SYMBOL
CHARACTERISTICS
tAee
Address to Output Delay
teE
CE to Output Delay
tOE
tDF(2)
OE to Output Delay
tOH
TEST
CONDITIONS
CE
MIN
= OE = V IL
= VIL
CE = VIL
CE = VIL
0
= OE = VIL
0
OE
OE High to Output Float
Output Hold from
Addresses CE or OE
Whichever Occurred First
WS27C010L·90 WS27C010L·12 WS27C010L·15
CE
MAX
MIN
MAX
MIN
UNITS
MAX
90
120
150
ns
90
120
150
ns
50
ns
50
ns
40
30
30
0
0
40
0
0
NOTES:
I. vpp should be at a TIL level except during programming. The supply current would then be the sum of Icc and IpP1 ' The maximum current
value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see timing diagram.
3. A.C. current component adds 2.5 mA per MHz.
3-78
WS27C010L
A.C. WAVEFORMS
V'H-----_
ADDRESS
VALID
ADDRESSES
V'L-----1-...,.
V'H _______
-------1----_
V'H
14----- I ACC ------1~
HIGH Z
HIGH Z
--------------f+H:+<
OUTPUT
NOTES:
1. Typical values are for TA = 25°C and nominal supply voltages.
2. This parameler is only sampled and is not 100% tested.
3. OE may be delayed up to tCE -tOE after the falling edge of CE without impact on tCE '
CAPACITANCEC2) TA = 25°C, f = 1 MHz
SYMBOL
PARAMETER
C IN
Input Capacitance
CO UT
Output Capacitance
Cvpp
Vpp Capacitance
CONDITIONS
Typ(l)
MAX
UNITS
VIN = OV
VOUT = OV
Vpp = OV
4
6
pF
8
12
pF
18
25
pF
A.C. TESTING INPUT/OUTPUT WAVEFORM
A.C. TESTING LOAD CIRCUIT
-...,....
2.01V
2.4
2.0
/ ' TEST POINTS
0.8
<
~
~
2.0
0.8
0.45
DEVICE
UNDER
TEST
I
3.3 KQ
,.... OUT
CL = 100pF
--
A.C. testing inputs are driven at 2.4V for a Logic "1" and
0.45V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and 0.8V for a Logic "0."
CL = 100 pF
CL includes Jig Capacitance
3-79
WS27C010L
MODE SELECTION
The modes of operation of the WS27C010L are listed in Table 1. A single 5V power supply is required in the read
mode. All inputs are TTL levels except for Vpp and 12V on A9 for device signature.
Table 1. Modes Selection
::-------::
CE
OE
PGM
Ag
Ao
V pp
Vcc
Read
VIL
VIL
X(l)
DOUT
V IH
High Z
VIH
X
5.0V
High Z
Programming
VIL
V IH
VIL
Program Verify
VIL
V IL
V IH
Program Inhibit
VIH
X
X
X
X
X
X
X
5.0V
Standby
X
X
X
X
X
5.0V
VIL
X
X
X
X
X
X
X
Output Disable
MODE
Signature
Manufacturer!3)
VIL
VIL
X
VH(2)
Device(3)
VIL
VIL
X
VH(2)
OUTPUTS
Vpp
Vee
DIN
Vpp
Vee
DOUT
Vpp
Vee
High Z
VIL
X
5.0V
23 H
V IH
X
5.0V
C1 H
NOTES:
1. X can be V1L or V1H
2. VH = 12.OV ±0.5V
3. A,-As• A,o-A'6 = V1L
DIP PIN CONFIGURATIONS
8 Mbil
4 Mbit
2 Mblt
A 19
Al &
A 1S
A12
A7
A&
As
A4
A3
A2
Al
AD
00
°1
°2
GND
XXlVpp
Al &
A 1S
A12
A7
A&
As
A4
A3
A2
AI
AD
00
°1
°2
GND
xx/Vpp
Al&
A1S
A12
A7
A&
As
A4
A3
A2
AI
AD
00
01
02
GND
27512
WS27C010L
27256
A1S
A12
A7
A&
As
A4
A3
A2
A1
AD
00
01
02
GND
Vpp
A12
A7
A&
As
A4
A3
A2
A1
AD
00
01
02
GND
A,.
A,s
A,.
A7
As
27256
vee
XXlVpp
XX/PGM-
xx
4
A,.
A,.
A.
As
A.
A,
Au
O.
0,
O.
GND
Al1 - OE
A,o
CE
07
O.
Os
O.
O.
Vec
A14
AI3
Ae
Ag
AI1
OE
AID
CE
07
0&
Os
°4
03
27512
Vce
XXlPGM
Vee
A17
A14
A14
A13
AI3
As
Ae
Ag
Ag
A11
A11
OEtvpp
OE
A 10
A10
CE
CE
07
07
0&
0&
Os
Os
04
°4
03
03
NOTES: 1. Plastic Dip will be available in the second half of 1988.
2. Compatible EPROM pin configurations are shown in the blocks adjacent to the WS27C010L pins.
PIN NAMES
3-80
Ao-A19
Addresses
CE
Chip Enable
OE
Output Enable
00-0 7
Outputs
PGM
Program
XX
Don't Care (During Read)
2 Mblt
4 Mbit
8 Mblt
Vee
A1e
A17
A14
A 13
Ae
Ag
A11
OE
Al0
CE
Vee
Ale
A17
AI4
AI3
Ae
Ag
°7
0&
Os
°4
03
211
OEtvpp
AID
CE
07
0&
Os
04
03
WS27C010L
ORDERING INFORMATION
PART NUMBER
WS27C010L-900
WS27C010L-120
WS27C010L-12DMB
WS27C010L-150
WS27C010L-150MB
SPEED
(ns)
90
120
120
150
150
PACKAGE
TYPE
32
32
32
32
32
Pin
Pin
Pin
Pin
Pin
CEROIp,
CEROIp,
CEROIp,
CEROIp,
CEROIp,
0.6"
0.6"
0.6"
0.6"
0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
04
04
04
04
04
Comm'l
Comm'l
Military
Comm'l
Military
Standard
Standard
MIL-STO-883C
Standard
MIL-STO-883C
3-81
3-82
WS57C010F
ADVANCE INFORMATION
WAFERSCALE INTEGRA110N, INC
1 Meg (128K x 8) BYTE-WIDE EPROM
KEY FEATURES
• Ultra-High Performance
-
• Fast Programming
55 ns
-
• Simplified Upgrade Path
-
15 Seconds Typical
• EPI Processing
Vpp and PGM Are "Don't Care" During
Normal Read Operation
Expandable to 8M Bits
-
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
• JEDEC Standard Pin Configuration
• Pin Compatible with WS27C010L
-
32 Pin Dip Package
GENERAL DESCRIPTION
The WS57C010F is an ultra-high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 128 K-words of 8 bits each. The 55 ns access time of the WS57C010F enables it to operate in high
performance systems. The "Don't Care" feature during read operations allows memory expansions up to 8M bits
with no printed circuit board changes.
High performance microprocessors such as the 80386 and 68020 require sub-70 ns memory access times to operate
at or near full speed. The WS57C010F enables such systems to incorporate operating systems and/or applications
software into EPROM. This enhances system utility by freeing up valuable RAM space for data or other program
store and eliminating disk accesses for the EPROM resident routines.
The WS57C010F pin configuration was established to enable memory upgrades to 8M bits without hardware changes
to the printed circuit board. Pins 1 and 31 are "don't care" during normal read operation. This enables higher order
addresses to be connected to these pins (see Figure 2). When higher density memories are required, the printed
circuit board is ready to accept the higher density device with no hardware changes.
The WS57C010F is part of a three product megabit EPROM family. Other family members are the WS27C010L and
WS57C210F. The WS27C010L is the standard speed version of the WS57C010F. The WS57C210F is organized in
a 64K x 16 configuration which is optimal for a word-wide system.
The WS57C010F is manufactured using WSI's advanced CMOS technology.
PRODUCT SELECTION GUIDE
PARAMETER
WS57C010F-55
WS57C010F-70
Address Access Time (Max)
55 ns
70 ns
Chip Select Time (Max)
55 ns
70 ns
Output Enable Time (Max)
20 ns
25 ns
3-83
WS57C010F
ABSOWTE MAXIMUM RATINGS·
*Notice: Stresses above those listed under ''Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage Temperature ........... -65DC to +125DC
Voltage on Any Pin with
Respect to Ground .............. -0.6V to +7V
Vpp with Respect to Ground ....... -0.6V to +14V
Vee Supply Voltage with
Respect to Ground .............. -0.6V to +7V
ESD Protection ........................ >2000V
NOTICE: Specifications contained within the following tables are subject to change.
READ OPERATION
DC CHARACTERISTICS
ODC ... T A ... +70DC; Vee (Comm'I/Military) = +5V ± 10%.
LIMITS
PARAMETER
CONDITIONS
III
Input Load Current
ILO
IpP1 (1)
Output Leakage Current
= 5.5V
VOUT = 5.5V
Vpp Load Current
ISB TTL
Vee Current Standby
Vpp '" Vee
CE = VIH
ISB CMOS
Vee Current Standby
CE
lee1(1)
Vee Current Active
VIL
Input Low Voltage
-0.1
VIH
Input High Voltage
2.0
VOL
Output Low Voltage
10L
VOH
Vp p(l)
Output High Voltage
10H
SYMBOL
SYMBOL
Vee
= VIH
= OE = V IL
= 16 mA
= -4 mA
= 5.0V ±
MAX
UNITS
10
~A
10
~A
10
~
2
mA
500
~A
60
mA
+0.8
V
Vee+ 1
V
0.4
V
2.4
0.25
V
-0.1
Vee+ 1
V
ODC ... TA'" + 70DC
CHARACTERISTICS
tAee
Address to Output Delay
teE
CE to Output Delay
tOE
tOF(2)
OE to Output Delay
tOH
CE
Vpp Read Voltage
AC CHARACTERISTICS
MIN
VIN
TEST
CONDITIONS
CE
MIN
= OE = VIL
= V IL
CE = VIL
CE = VIL
0
= OE = VIL
0
OE
OE High to Output Float
Output Hold From
Addresses CE or OE
Whichever Occurred First
WS57C010F-55
CE
MAX
WS57C010F-70
MIN
MAX
UNITS
55
70
ns
55
70
ns
20
20
0
0
25
ns
25
ns
ns
NOTES:
1. Vpp should be at a TTL level except during programming. The supply current would then be the sum of Icc and IpP1 ' The maximum current
value is with Outputs 0 0 to ~ unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see timing diagram.
3-84
WS57C010F
A.C. WAVEFORMS
V'H-----_
ADDRESS
VALID
ADDRESSES
V'L-----V'H -------1-_
-------1----_
V'H
1 + - - - - t ACC -----i~
HIGH Z
HIGHZ
--------------t+H:+O(
OUTPUT
NOTES:
1. Typical values are for TA ~ 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE -tOE after the falling edge of CE without impact on
CAPACITANCEl2) T A
= 25°C, f = 1 MHz
PARAMETER
SYMBOL
icE'
C'N
Input Capacitance
CauT
Output Capacitance
CvPP
Vpp Capacitance
CONDITIONS
TYP(1)
MAX
UNITS
= OV
VauT = OV
Vpp = OV
4
6
pF
8
12
pF
18
25
pF
A.C. TESTING INPUT/OUTPUT WAVEFORM
V,N
A.C. TESTING LOAD CIRCUIT
2.01V
~
2.4
2.0
;>
0.8
<
0.8
0.45
>>
~
2.0
TEST POINTS
DEVICE
UNDER
TEST
I
3.3 KQ
-0
OUT
CL =30pF
--
A.C. testing inputs are driven at 2.4V for a Logic "1" and
0.45V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and O.BV for a Logic "0."
Cl =30pF
C l includes Jig Capacitance
3-85
WS57C010F
DIP PIN CONFIGURATIONS
8 Mbll
4 Mbll
2 Mbil
A19
A16
A1S
A12
A7
A6
As
~
A3
A2
Al
AO
00
01
02
GND
XX/Vpp
A16
A1S
A12
A7
A6
As
A4
A3
A2
Al
AO
00
01
02
GND
XXlVpp
A16
A1S
A12
A7
A6
As
~
A3
A2
Al
Au
00
01
02
GND
27512
WS57C010F
27256
XX/V pp
A,s
A1s
A12
A7
A6
As
A4
A3
A2
Al
AO
00
01
02
GND
Vpp
A12
A7
A6
As
A4
A3
A2
Al
AO
00
01
02
GND
27256
Vee
XXlPGM
xx
A,.
A7
A,.
A,a
As
As
A.
A,
A.
O.
0,
O.
GND
A11
OE
A,.
CE
07
O.
O.
O.
O.
Vee
A14
A13
As
A9
All
OE
Al0
CE
07
06
Os
04
03
27512
2 Mbil
Vee
XXlPGM
Vee
A17
A14
A14
A13
A13
As
As
Ag
Ag
All
All
OE/Vpp
OE
Al0
Al0
CE
CE
07
07
06
06
Os
Os
04
04
03
03
4 Mbil
8 Mbil
Vee
A1S
A17
A14
A13
As
Ag
All
OE
Al0
Vee
A1S
A17
A14
A13
As
Ag
All
OElVpp
Al0
CE
07
06
Os
04
03
CE
07
06
Os
04
03
NOTES: 1. Plastic Dip will be available in the second half of 1988.
2. Compatible EPROM pin configurations are shown in the blocks adjacent to the WS57C010F pins.
PIN NAMES
~-A19
Addresses
CE
Chip Enable
OE
Output Enable
0 0-07
Outputs
PGM
Program
XX
Don't Care (During Read)
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
WS57C010F-55D
WS57C010F-70D
WS57C010F-70DMB
55
70
70
32 Pin CERDIp, 0.6"
32 Pin CERDIp, 0.6"
32 Pin CERDIp, 0.6"
04
04
04
Comm'l
Comm'l
Military
Standard
Standard
MIL-STD-SS3C
3-86
WS57C65
WAFERSCALE INTEGRA710N, INC.
HIGH SPEED 4K x 16 WORDWIDE CMOS EPROM
KEY FEA TURES
• Fast Access Time
- 55ns
• Low Power Consumption
• Ideal for 16/32 bit Processors
- TMS320, 68000, 80386, etc.
•
•
•
•
2 to 1 Package Reduction
30% + Space Savings
Single Chip Solution
Compatible with JEDEC pinout
GENERAL DESCRIPTION
The WS57C65 is an extremely High Performance EPROM based memory with a 4K x 16 architecture.
It is manufactured in an advanced CMOS process which consumes very little power while operating at
speeds which rival that of bipolar PROMs.
The major features of the WS57C65 are its 4K x 16 architecture and its high speed. This combination
makes the WS57C65 an ideal solution for applications which utilize 16/32 bit data paths. Examples in·
clude systems which are based on such processors as the TMS320 family of DSP processors as well
as high performance general purpose processors such as the MC68000 family and the 80286 and
80386 microprocessors.
The word wide architecture of the WS57C65 results in a 2 to 1 savings in EPROM component count and
a minimum 30% savings in board space.
The pin configuration utilized is upward compatible with the JEDEC standard pinout for word wide
EPROMs. This allows an easy upgrade path to higher density memories such as the WS57C257. No
board changes or jumper wires are required to complete the upgrade.
PIN CONFIGURATION
MODE SELECTION
MODE
~
CE
OE Vpp Vee
Read
VIL
VIL Vee Vee DouT
Output Disable
X
OUTPUTS
VIH Vee Vee High Z
Standby
VIH
X
Program
VIL
VIH
Vpp Vee DIN
Program Verify
X
VIL
Vpp Vee DOUT
Program Inhibit
VIH
VIH
Vpp Vee High Z
VIL
VIL Vee. Vee Encoded Data
Signature'
Vee Vee High Z
x can be either V1L or V1Ho
*For Signature, Ag = 12V, AD is toggled, and all other address are at
TTL low. Ao =VIL = MFGR 0023H, Ao = V'H = DEVICE 0081 H.
PRODUCT SELECTION GUIDE
PARAMETER
Address Access Time
WS57C65-55
WS57C65-70
55ns
70ns
Chip Select Time
55ns
70ns
Output Enable Time
25ns
30ns
3-87
3
WS57C65
ABSOWTE MAXIMUM RAT/NGS*
*Notiee: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ............ -65° to + 150°C
Voltage on Any Pin with
Respect to GND ................ -0.6V to +7V
Vpp with Respect to GND ......... -0.6V to +14V
ESD Protection ........................ >2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vee
Comm'l
0° to +700 C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
DC READ CHARACTERISTICS Over Operating Range. (See Above)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
= 16 mA
= -4 mA
MAX
UNITS
VOL
Output Low Voltage
IOL
VOH
Output High Voltage
IOH
IS81
Vcc Standby Current (CMOS)
Notes 1 and 3
500
ItA
IS82
Vcc Standby Current (TTL)
Notes 3 and 3
20
mA
ICC1
Active Current (CMOS)
Note 1
(Note 4)
mA
Icc2
Vcc Active Current (TTL)
Note 2
(Note 4)
mA
Ipp
Vpp Supply Current
Vpp
Vpp
Vpp Read Voltage
III
Input Load Current
ILO
Output Leakage Current
0.4
V
Comm'l
35
Military
45
Comm'l
45
Military
55
= Vcc
= 5.5V or Gnd
VOUT = 5.5V or Gnd
3)
4)
ItA
100
VIN
NOTES: 1) CMOS inputs: GND ± 0.3V or Vee ± 0.3V.
2) TIL inputs: VIL .. 0.81/, VIH ~ 2JN.
V
2.4
Vcc - 0.4
Vcc
V
-10
10
-10
10
ItA
ItA
A.C. Standby power component is 1 rnA/MHz (Power = AC + DC).
A.C. Active power component is 3 rnA/MHz (Power = AC + DC).
AC READ CHARACTERISTICS Over Operating Range. (See Above)
PARAMETER
SYMBOL
WS57C65-55
WS57C65-70
WS57C65-90
MIN
MIN
MIN
MAX
MAX
Address to Output Delay
tACC
55
70
90
CE to Output Delay
tCE
55
70
90
OE to Output Delay
tOE
20
25
30
Output Disable to Output Float
tDF
Address to Output Hold
tOH
CE
tACe
I"
~
'\J..
3·88
IDF
/
IOE
OUTPUTS
10H
/
I---ICE
DE
1950
K
VALID
1......--J.
0
TEST LOAD (High Impedance Systems)
AC READ TIMING DIAGRAM
ADDRESSES
0
ns
30
25
20
0
UNITS
MAX
""
f-
-
-
2.D1V~
D.U.T.
I-=TIMING LEVELS
Input Levels:
VALID
IDF
I-
3DpF
(INCWDING SCOPE
AND JIG
CAPACITANCE)
0
and
Reference Levels:
3V
0.8
and
2.0V
WS57C65
PROGRAMMING INFORMATION
DC CHARACTERISTICS (TA=25 ± 5°C, Vee = 5.50V ± 5%, Vpp=13.5±0.5V)
PARAMETER
lnput Leakage Current
(VIN = Vee or Gnd)
Vpp Supply Current During
Programming Pulse
(CE = PGM = VIL)
Vee Supply Current
Input Low Level
Input High Level
Output Low Voltage During Verify
(IOL = SmA)
Output High Voltage During Verify
(IOH = -2mA)
NOTES:
SYMBOL
III
MIN.
-10
Ipp
lee
VIL
VIH
-0.1
2.0
MAX.
UNIT
10
p.A
50
mA
35 (Note 4)
mA
V
V
0.8
Vee + 0.3
0.45
VOL
VOH
V
V
2.4
6) Vcc must be applied either cOincidentally or before Vpp and removed elth~lncldentally or after Vpp.
7) Vpp must not be greater than 14 volts including overshoot. During CE = PGM = V,L, Vpp must not be switched
from 5 volts to 13.5 volts or vice·versa.
8) During power up the PGM pin must be brought high (2 V,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS (TA=25 ± 5°C, VeC= 5.50V ± 5%, Vpp= 13.5±0.5V)
PARAMETER
Address Setup Time
Chip Enable Setup Time
Output Enable Setup Time
Data Setup Time
Address Hold Time
Data Hold Time
Chip Disable to Output Float Delay
Data Valid from Output Enable
Vpp Setup Time
PGM Pulse Width
SYMBOL
t AS
t CES
tOES
tos
tAH
tOH
tDF
tOE
tvs
tpw
MIN.
2
2
2
2
0
TYP.
-
2
0
2
1
MAX.
130
130
3
10
UNIT
/ls
/ls
/ls
/ls
/lS
/ls
ns
ns
/ls
ms
NOTE: Single shot programming algorithms should use a single 10 ms pulse.
PROGRAMMING WAVEFORM
ADDRESSES
DATA
v••
v••
Vee
V,H
CE
V'L
V,H
PGM
V'L
V,H
OE
V'L
3-89
WS57C65
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C65 has all 4096x16
bits in the "1," or high state. "O's" are loaded into the WS57C65
through the procedure of programming.
The programming mode is entered when +13.5V is applied to
the V pp pin, +5.75V is applied to Vee, and CE is at VIL' During
programming, CE is kept at VIL' A 0.1 ~F capacitor between
V pp and GND is needed to prevent excessive voltage transients which could damage the device. The address to be programmed is applied to the proper address pins. a-bit patterns
are placed on the respective data output pins. The voltage levels
should be standard TTL levels.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C65 to an ultra-violet light
source. A dosage of 15W second/cm 2 is required to completely
erase a WS57C65. This dosage can be obtained by exposure
to an ultra-violet lamp with wavelength of 2537 Angstroms (A)
with intensity of 12000~ W/cm 2 for 20 minutes. The WS57C65
should be about one inch from the source and all filters should
be removed from the UV light source prior to erasure.
It is important to note that the WS57C65 and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A. the exposure to fluorescent light and
sunlight will eventually erase the WS57C65 and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C65-550
WS57C65-70CMB
WS57C65-700
WS57C65-700MB
55
70
70
70
3-90
PACKAGE
TYPE
40
44
40
40
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
Pin CEROIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
03
C3
03
03
Comm'l
Military
Comm'l
Military
Standard
M IL-STO-883C
Standard
MIL-STO-883C
iF====::~
--- ==
--.:.......-!!F:=.-!P.=
-
WS57C66
-.-.- - "
WAFERSCALE INTEGRA TION, INC.
-"'"
ADVANCE INFORMATION
HIGH-SPEED 4K x 16 CMOS EPROM WITH MUX I/O
KEY FEATURES
• Low Power Consumption
• Fast Access Time
-
55 ns 70 ns -
Commercial
Military
• Chip Select Can be Latched (FT = 0)
or Unlatched (FT = 1)
• Multiplexed 1/0
-
• 28-Pin Cerdip Package
• Supported by the WSI MagicPro™
Engineering Programmer
Interfaces Directly to a 16-Bit Multiplexed Bus
Address Latched on Chip
• 4 to 1 Package Reduction
GENERAL DESCRIPTION
The WS57C66 is a high-performance CMOS EPROM memory in a 4K x 16 architecture that interfaces directly to
a multiplexed bus. The address and data are multiplexed enabling the circuit to be housed in a 28 pin DIP package.
The ALE input latches the address in the input latches when low. The latches are transparent when the ALE is high.
The CS to the WS57C66 can be latched for a maximum savings of 4 packages (FT = 0) or 2 packages when FT = 1.
The WS57C66 is an ideal solution for microprocessors or microcontrollers with multiplexed address and data busses.
FUNCTIONAL BLOCK DIAGRAM
ADo_,.
13
16
I
J
LATCH
G
ALE
OE
AO_12
J
t
16
cs
FT
I
J LATCH
G
J
~
-
J
J
CS
4K x 16
EPROM
OE
°0_15
t
PRODUCT SELECTION GUIDE
PARAMETER
WS57C66-55
WS57C66-70
UNITS
Address Access Time
55
70
ns
Chip Select Time
55
70
ns
Output Enable Time
20
25
ns
3-91
WS57C66
SYSTEM INTERFACE
16
ADD_,S
ADD_,S
[ AD,.
• REPLACES TWO 4K )( 8 HIGH-SPEED
EPROM. AND TWO 8-BIT LATCHES
CS
MICROPROCESSOR
WS57C66
4K)( 16
EPROM
ALE
ALE
FT
RD
OE
a) CHIP SELECT LATCHED (FT
l:-
= 0)
.
ALE
ADo-,s
MICROPROCESSOR
ADD_,S
LATCH
ALE
A8_15
I
: DECODER
I
IG
RD
LATCH
I--
WS57C66
4K)( 16
EPROM
CS OE FT
•
REPLACES TWO 4K )( 8
HIGH-SPEED EPROMs
W
Vee
AO_7
-IG
b) CHIP SELECT UNLATCHED (FT
= 1)
MODE SELECTION
PINS
CE
OE
V pp
Vee
V IL
V IL
Vee
Vee
X
V IH
Vee
Vee
High
Z
Standby
V IH
X
Vee
Vee
High
Z
Program
DIN
MODE
Read
Output Disable
V IL
V IH
Vpp
Vee
Program Verify
X
V IL
V pp
Vee
Program Inhibit
V IH
V IH
Vpp
Vee
OUTPUTS
DOUT
DOUT
High
WS57C66 PIN ASSIGNMENTS
0,. 0,.
0,. Vpp Vee FT
D,s
Vee
FT
D,s
AD,O
ALE
AD.
GND
0
GND
AD.
AD7
til
AD. _ .J
1.:-1 1::1
OE
ALE
AD,o
PGM
CE
r2ii
L_
ADD
AD.
Ne
r19
L_
AD,
Ne
NC
r-, r:-1 r-:-1 I I r-,
3-92
ADs AD. AD. AD. Ne Ne
PGM
CE
GND
AD.
AD,
1121 1131 1141 1151 1161 1171 118 1
Ne
GND
AD.
TOP
ADD
AD,
ADs
AD.
AD.
o...;.~_ _-IAD.
Z
WS57C66
ABSOWTE MAXIMUM RAT/NGS*
*Notiee: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ........... -65°C to +1500 C
Voltage to any pin with
respect to GND .................. -0.6V to +7V
Vpp with respect to GND ......... -0.6V to + 14.0V
ESD Protection ........................ >2000V
OPERATING RANGE
RANGE
TEMPERATURE
Comm'l
0° to +70°C
+5V
Military
-55° to +125°C
+5V
DC READ CHARACTERISTICS
SYMBOL
Vce
± 5%
± 10%
Over Operating Range with Vpp = VCC
PARAMETER
TEST CONDITIONS
Output Low Voltage
IOL = 8 rnA
VOH
Output High Voltage
IOH
IS81
Vcc Standby Current (CMOS)
Note 1
IS82
Vcc Standby Current (TTL)
Note 2
VOL
ICCI
Active Current (CMOS)
ICC2
Vcc Active Current (TTL)
Ipp
Vpp Supply Current
Vpp
Vpp Read Voltage
=
Note 2
Input Load Current
VIN
Output Leakage Current
VOUT
AC READ CHARACTERISTICS
3)
4)
15 (Note 3)
rnA
20 (Note 3)
rnA
35
Military
45
Comm'l
45
Military
55
(Note 4)
rnA
(Note 4)
rnA
100
lIA
Vcc-0.4
Vcc
V
-10
10
-10
10
lIA
lIA
A.C. standby power component is 1 rnA/MHz (Power = AC + DC).
A.C. active power component is 3 rnA/MHz (Power = AC + DC).
Over Operating Range with Vpp = Vcc
WS57C66-55
PARAMETER
V
Comm'l
= 5.5V or GND
= 5.5V or GND
III
ILO
UNITS
0.4
V
= Vcc
Vpp
MAX
2.4
-2 rnA
Note 1
NOTES: 1) CMOS inputs: GND ± O.~ or Vee ± 0311.
2) TTL inputs: V1L .. O.av, V1H ~ 2.OV.
MIN
SYMBOL
MIN
MAX
WS57C66-70
MIN
MAX
UNITS
tACC
55
70
ns
CE to Output Delay
tCE
55
70
ns
OE to Output Delay
Address to Output Delay
tOE
20
25
ns
Output Disable to Output Float
tOF
20
25
ns
Address Setup Time
tAS
6
8
ns
Address Hold Time
tAH
10
12
ns
Latch Pulse Width
tLW
10
12
ns
Output Disable to Latch Enable
tOOL
0
0
ns
Latch Disable to Output Enable
t LOO
10
12
ns
3-93
WS57C66
AC READ TIMING DIAGRAM
tOOL
I LW -
--
!+--ILDO -
ALE
-IDOL
\
\
----'
CE
(WITH FT
=
J.
0)
icE
CE
(WITH FT
=
1)
DATA
ADDRESS ~
}-
.tD-J
~tOE-
.IAS • •IAHJ
DATA
ADDRESS
tAce
0,2- 0 ,5
_~D~/Ii~TA~..J)~------------2000V
OPERATING RANGE
Range
Temperature
Vcc
Comm'l.
0° to +70°C
+5V ± 5%
Military
-55° to +125°C
+5V ± 10%
DC READ CHARACTERISTICS
SYMBOL
Over Operating Range with Vpp = Vee.
MIN
TEST CONDITIONS
PARAMETER
MAX
UNIT
0.4
VOL
Output Low Voltage
IOL= SmA
VOH
Output High Voltage
IOH=-2mA
ISB1
Vee Standby Current (CMOS) Notes 1 and 3
500
I1A
ISB2
Vcc Standby Current (TTL)'
Notes 2 and 3
20
mA
ICC1
Active Current (CMOS)
Note 1
lec2
Vce Active Current (TTL)
Ipp
Vpp Supply Current
Vpp
Vpp Read Voltage
Note 2
V
2.4
V
Comm'l.
40
Military
50
Comm'l.
50
Military
SO
Vpp= Vcc
(Note 4)
mA
(Note 4)
mA
100
J.lA
Vce - 0.4
Vce
V
III
Input Load Current
VIN = 5.5V or Gnd
- 10
10
J.lA
ILO
Output Leakage Current
VOUT = 5.5V or Gnd
- 10
10
J.lA
NOTES: 1) CMOS inputs: GND ± a.3V or Vee ± a.3V.
2) TTL inputs: V1L " a.BV, V1H ;. 2.aV.
3) A.C. standby power component is 1 mAlMHz.
4) A.C. active power component is 3 rnA/MHz (Power = AC + DC).
AC READ CHARACTERISTICS Over Operating Range with Vpp = VCC'
PARAMETER
Address to Output Delay
SYMBOL
WS57C257-55
MIN
MAX
WS57C257-70
MIN
MAX
tACC
55
70
CE to Output Delay
t CE
55
70
OE to Output Delay
tOE
25
30
Output Disable to Output Float
t DF
25
30
Address to Output Hold
t OH
AC READ TIMING DIAGRAM
0
UNITS
ns
0
TEST LOAD (High Impedance Systems)
1950
ADDRESSES
:.::;'~
~30PF
I=-
(INCWDING SCOPE
AND JIG
CAPACITANCE)
llE---------..
TIMING LEVELS
OUTPuTS--------~~~~11~--
Input Levels: a and 3V
Reference Levels: 0.8 and 2.0V
3-98
WS57C257
PROGRAMMING INFORMATION
DC CHARACTERISTICS
(TA = 25
PARAMETER
).nput Leakage Current
VIN = Vee or Gnd)
Vpp Supply Current During
Programming Pulse
(CE = PGM = Vll)
Vee Supply Current
± 5°C,
Vee = 5.50V
± 5%,
SYMBOL
III
Vpp = 12.5
± 0.5V)
MIN.
-10
Ipp
Input Low Level
Input High Level
Icc
V il
VIH
Output Low Voltage During Verify
(IOl
SmA)
Val
Output High Voltage During Verify
(IOH
-2mA)
V OH
=
=
-0.1
2.0
MAX.
UNIT
10
}LA
60
mA
35 (Note 4)
mA
0.8
V
V
Vee +0.3
0.45
V
V
2.4
NOTES: 6) Vcc must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp.
7) Vpp must not be greater than 14 volts including overshoot. During CE = PGM = V'L, Vpp must not be switched
from 5 volts to 13.5 volts or vice-versa.
8) During power up the PGM pin must be brought high (2:V,H) either coincident with or before power is applied to Vpp.
AC CHARACTERISTICS
(TA = 25
PARAMETER
± 5°C,
VCC = 5.50V
± 5%,
Vpp = 12.5
TYP.
± 0.5V)
SYMBOL
MIN.
Address Setup Time
t AS
2
MAX.
UNIT
Chip Enable Setup Time
t CES
2
!-,S
Output Enable Setup Time
tOES
2
!-,s
!-,s
!-,s
Data Setup Time
tos
2
Address Hold Time
tAH
0
!-,s
Data Hold Time
tOH
2
Chip Disable to Output Float Delay
tOF
0
!-,s
ns
Data Valid from Output Enable
tOE
Vpp Setup Time
tvs
tpw
PGM Pulse Width
130
130
2
1
3
10
ns
!-,s
ms
NOTE: Single shot programming algorithms should use one 10 ms pulse per word.
PROGRAMMING WA VEFORM
ADDRESSES
DATA
V __
v__
Vee
V,H
CE
V'L
V,H
PGM
VIL
V,H
CE
V'L
3-99
WS57C257
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WS57C257 has all 16,384x16
bits in the "1:' or high state. "O's" are loaded into the WS57C257
through the procedure of programming.
erase a WS57C257. This dosage can be obtained by exposure
to an ultra-violet lamp (wavelength of 2537 Angstroms (A» with
intensity of 1200011 W/cm 2 for 20 minutes. The WS57C257
should be about one inch from the source and all filters should
be removed from the UV light source prior to erasure.
The programming mode is entered when +13.5V is applied to
the Vpp pin, +5.5V is applied to Vcc, and CE is taken to V1L•
During programming, CE is kept at V1L• A 0.1 I1F capacitor
between Vpp and GND is needed to prevent excessive voltage
transients, which could damage the device. The address to be
programmed is applied to the proper address pins. 16-bit
patterns are placed on the respective data output pins. The
voltage levels should be standard TTL levels.
It is important to note that the WS57C257 and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A, the exposure to fluorescent light and
sunlight will eventually erase the WS57C257 and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
ERASURE
PROGRAMMERS
In order to clear all locations of their programmed contents,
it is necessary to expose the WS57C257 to an ultra-violet light
source. A dosage of 15W secondlcm2 is required to completely
Data I/O Unipak 2B, software version 13 or later, family/pinout
code 1F/E1; WSl's MagicPro™ IBM PC Compatible Engineering Programmer.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS57C257-550
WS57C257-70CMB
WS57C257-700
WS57C257-700MB
55
70
70
70
3-100
PACKAGE
TYPE
40
44
40
40
Pin CEROIp, 0.6"
Pad CLLCC
Pin CEROIp, 0.6"
Pin CEROIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
03
C3
03
03
Comm'l
Military
Comm'l
Military
Standard
MIL-STO-883C
Standard
MIL-STO-883C
!FEE ,:=:
----- - ;::=
----
-
~
WS57C210F
"'J:
--~~~
r.-
ADVANCE INFORMATION
WAFERSCALE INTEGRA170N, INC.
1 Meg (64K x 16) WORD-WIDE EPROM
KEY FEATURES
• Ultra-High Performance
-
• Fast Programming
-
55 ns
15 Seconds Typical
• EPI Processing
-
• Simplified Upgrade Path
-
Vpp and PGM Are "Don't Care" During
Normal Read Operation
Expandable to 8M Bits
Latch-Up Immunity to 200 mA
ESD Protection Exceeds 2000 Volts
• JEDEC Standard Pin Configuration
-
40 Pin Dip Package
GENERAL DESCRIPTION
The WS57C210F is an ultra-high performance, 1,048,576-bit Electrically Programmable UV Erasable Read Only Memory.
It is organized as 64 K-words of 16 bits each. The 55 ns access time of the WS57C210F enables it to operate in high
performance systems. The "Don't Care" feature during read operations allows memory expansions up to 8M bits
with no printed circuit board changes.
High performance microprocessors such as the 80386 and 68020 require sub-70 ns memory access times to operate
at or near full speed. The WS57C210F enables such systems to incorporate operating systems and/or applications
software into EPROM. This in turn enhances system utility by freeing up valuable RAM space for data or other program
store and eliminating disk accesses for the EPROM resident routines.
The WS57C210F pin configuration was established to allow memory upgrades to 8M bits without hardware changes
to the printed circuit board. Pins 1 and 39 are "don't care" during normal read operation. This enables higher order
addresses to be connected to these pins (see Figure 2). When higher density memories are required, the printed
circuit board is ready to accept the higher density device with no hardware changes.
The WS57C210F is part of a three product megabit EPROM family. Other family members are the WS27C010L and
WS57C010F. The standard speed WS27C010L is organized in a 128K x 8 configuration. The WS57C010F is the highspeed version of the WS27C010L.
The WS57C210F is manufactured using WSI's advanced CMOS technology.
PRODUCT SELECTION GUIDE
PARAMETER
WS57C210F-55
WS57C210F-70
Address Access Time (Max)
55 ns
70 ns
Chip Select Time (Max)
55 ns
70 ns
Output Enable Time (Max)
20 ns
25 ns
3-101
WS57C210F
ABSOWTE MAXIMUM RATINGS·
*Notice: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other conditions
above those indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may
affect device reliability.
Storage Temperature ........... -S5°C to +125°C
Voltages on Any Pin with
Respect to Ground .............. -O.SV to +7V
Vpp with Respect to Ground ....... -O.SV to + 14V
Vcc Supply Voltage with
Respect to Ground .............. -O.SV t& +7V
ESD Protection ........................ >2000V
NOTICE: Specifications contained within the following tables are subject to change.
READ OPERATION
DC CHARACTERISTICS
OOC';; TA .;; +70°C; Vce (Comm'I/Military) = +5V ± 10%
LIMITS
SYMBOL
PARAMETER
III
Input Load Current
ILo
IpPI(I)
Output Leakage Current
CONDITIONS
MIN
MAX
UNITS
VIN = 5.5V
10
VOUT = 5.5V
10
Vpp Load Current
Vpp ';; Vec
10
!1A
!1A
!1A
IS6 (TTL)
Vec Current Standby
CE = VIH
2
mA
IS6 (CMOS)
Vee Current Standby
CE = VIH
500
!1A
IccI(I)
Vee Current Active
CE = OE = VIL
75
mA
V IL
Input Low Voltage
-0.1
+0.8
V
VIH
Input High Voltage
2.0
Vee +1
V
VOL
Output Low Voltage
0.4
V
VOH
Vpp(l)
Output High Voltage
Vee +1
V
V pp Read Voltage
AC CHARACTERISTICS
SYMBOL
IOH = -2 mA
2.4
Vce = 5.0V ± 0.25
-0.1
V
O°C .;; TA ';; + 70°C
CHARACTERISTICS
tAee
Address to Output Delay
tCE
tOE
tOF(2)
tOH
IOL=8mA
TEST
~ONDITIONS
WS57C210f..55
WS57C210f..70
MIN
MIN
MAX
MAX
UNITS
CE = OE = V IL
55
70
CE to Output Delay
OE = V IL
55
70
ns
OE to Output Delay
CE = VIL
20
25
ns
OE High to Output Float
CE = V IL
0
25
ns
Output Hold from
Addresses CE or OE
Whichever Occurred First
CE = OE = VIL
0
20
0
0
ns
ns
NOTES:
1. Vpp should be at a TTL level except during programming. The supply current would then be the sum of Icc and IpP1 ' The maximum current
value is with Outputs 0 0 to 0 7 unloaded.
2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven-see timing diagram.
3·102
WS57C210F
A.C. WAVEFORMS
V'H-----_
ADDRESS
VALID
ADDRESSES
V'L-----V'H
-------+-_
V'H
--------1f----_
CE
OE
1 4 - - - - t ACC
-----I'""
HIGH Z
OUTPUT _ _ _ _ _~H~IG~H~Z~_ _ _ __f~~~{
NOTES:
1. Typical values are for TA = 25°C and nominal supply voltages.
2. This parameter is only sampled and is not 100% tested.
3. OE may be delayed up to tCE -tOE after the falling edge of CE without impact on tCE '
CAPAC/TANCE(2) T A
= 25°C, f = 1 MHz
SYMBOL
PARAMETER
CIN
Input Capacitance
COUT
Output Capacitance
CvPp
Vpp Capacitance
CONDITIONS
VIN
VOUT
A.C. TESTING INPUT/OUTPUT WAVEFORM
Vpp
= OV
= OV
= OV
Typ(l)
MAX
UNITS
4
6
pF
8
12
pF
18
25
pF
A.C. TESTING LOAD CIRCUIT
-
2.01V
- r-
2.4
>
2.0
TEST POINTS
0.45
0.8
<
2.0
0.8
DEVICE
UNDER
TEST
:>~I»
3.3 KQ
"
OUT
..... CL = 30 pF
I-
-
A.C. testing inputs are driven at 2.4V for a Logic "1" and
0.45V for a Logic "0." Timing measurements are made at 2.0V
for a Logic "1" and 0.8V for a Logic "0."
CL = 30 pF
CL includes Jig Capacitance
3-103
WS57C210F
DIP PIN CONFIGURATIONS
8 Mblt
A,S
4 Mbit
2 Mbit
512K
WS57C210F
WS57C257 WS57C65
XXNpp XXlVpp XXlVpp
XXlVpp
XXIVpp
WS57C65 WS57C257
512K
2 Mblt
Vec
Vee
- 'Vpp
Vcc -
Vee
Vee
paM-
XXlPGM
XXIPGM
NC
NC
NC
NC
NC
A,., -
NC
A"
A,
CEJVpp
CE
CE
CE
CE
CE
-
O,s
O,s
O,s
O,s
O,s
O'S
-
0,.
0,.
0,.
0,.
0,.
0,.
-
0,.
0,.
0,.
0,.
0,.
0,.
°,2
°'2
°'2
°'2
°,2
0"
°'2
0 11
- 0"
-
0"
0"
°11
0"
- 0"
°'0
Og
°'0
Og
°'0
Og
°'0
Og
°'0
Og
°'0
Og
-,0,.
- 0_
-
CE
0,.
0,.
Os
Os
Os
Os
Os
GND
GND
GND
GND
GND
°7
07
°7
0.
°7
0.
-
0.
°7
0.
°7
0.
0.
- 0,
Os
Os
Os
D.
D.
-
0,
0.
0.
0.
0.
D.
-
0.
0.
0.
0.
0.
0.
-
0.
03
°2
0,
°2
0,
O2
°2
0,
°2
0,
°2
0,
-
0.
0,
0,
00
00
00
00
00
00
OE
OE
OE
OE
OE
OE
-
A,.
A,.
NC
A,s
A,s
A,s
NC
A,.
A,.
A,.
A,.
NC
A,.
A,.
A,.
A,.
A,.
NC
A'2
A'2
A'2
A'2
A'2
A", -
A11
A11
A11
A11
A11
A11
A,
A,o
A,o
A,o
A,o
A,o
A,o
..-.-
A_ -
07
D.
A17
A,.
-
.-
G NO
Os
Vcc
A17
A,
0,
Os
GND
Vcc
NC
0,.
0.
OE
4 Mbit 8 Mblt
XXlPGM XXIPGM
Ag
Ag
Ag
Ag
Ag
Ag
GN 0-
GND
GND
GND
GND
GND
GND
-
As
As
As
As
As
As
A7
A7
A7
A7
A7
A7
As
A.
As
As
A.
As
As
A.
As
As
A.
As
A.
A.
A.
A.
A.
A.
A.
A.
A.
A.
A.
A.
A2
A2
A2
A2
A2
A2
A,
A,
A,
A,
A,
A,
Ao
Ao
Ao
Ao
Ao
Ao
NOTES: 1. Compatible EPROM pin configurations are shown in the blocks adjacent to the WS57C210F pins.
2. Plastic Dip Availability is scheduled for second half 1988.
PIN NAMES
Ao-A19
Addresses
CE
Chip Enable
OE
Output Enable
0 0-0 15
Outputs
NC
No Connection
XX
Don't Care (During Read)
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
WS57C210F-55D
WS57C210F-70D
WS57C210F-70DMB
55
70
70
40 Pin CERDIp, 0.6"
40 Pin CERDIp, 0.6"
40 Pin CERDIp, 0.6"
D3
D3
D3
Comm'l
Comm'l
Military
Standard
Standard
MIL-STD-SS3C
3-104
WSMAP162/WSMAP161
ADVANCE INFORMATION
WAFERSCALE INTEGRA170N, INC.
HIGH-SPEED MAPPABLE
MEMORY (MAp™)
KEY FEATURES
• Super Fast Access Time
-
• Addressable Range
EPROM/SRAM: 40 ns (including decode)
Chip Select Outputs: 22 ns
• High Density UV Erasable EPROM
-
128K Bits
32K Bits
Eliminates External Chip-Select Decode
Components and Delay
• Code Security
-
-
2K Bytes or 1K Words
-
Control 110 and Other System Devices
• Fully User Configurable
• On-Board Programmable Address Decoder
-
512K Bytes or 256K Words
• Eight Chip Select Outputs
• High Density 6-Transistor Static RAM
-
-
• Block Resolution
Contains Programmable Security Bit
-
Byte or Word Operation
• Reduces Board Space
-
Simplifies Routing
Replaces 2 or more EPROMs, 2 or more
SRAMs and One Decoder
GENERAL DESCRIPTION
The WSMAP162 and WSMAP161 are Mapped Address Programmable (MAp™) memory products that integrate 128K
bits of EPROM, 32K bits of SRAM and a Programmable Mapping Decoder (PMD™) into a single 40-pin package.
With a wide input addressing range, these memory products are compatible with large address space processor
systems. The on-board PMD™ enables the placement of physical 16K bytes or 8K words of EPROM and 4K bytes
or 2K words of SRAM anywhere in a total address space of 512K bytes or 256K words respectively. The PMD™
reduces system component count as well as board space, enhances performance and increases data security. The
major feature of this product is the integration of high speed, high density UV erasable EPROM and a CMOS SRAM
along with decoding logic on a single chip.
The WSMAP162 is ideal for use with digital signal processors such as the TMS320XX series. Its data path can be
programmed as either 8 or 16 bits. With the provision of Pin 2 programmable as either Chip Select (CSI)
or the highest address bit, its address range is from 128K to 256K words or 256K to 512K bytes. The EPROM architecture
is 16K x 8 (byte operations) or 8K x 16 (word operations). The SRAM architecture is 4K x 8 (byte operations) or
2K x 16 (word operations).
The 16-bit data path WSMAP161 is used with microcontrollers and microprocessors using a 16-bit data bus. With
Pin 39 as BHE (Byte High Enable), the WSMAP161 can accomodate either full word or byte operations (for those 16-bit
processors capable of byte operations). Its addressing range is from 64K words to 128K words (see pin 2 above).
Its EPROM is 8K x 16 and its SRAM is 2K x 16.
Refer to Application Note 002 in this databook for additional information.
3-105
WSMAP1621WSMAP161
BLOCK DIAGRAM
DECODED EPROM ADDRESS
"-
PGMH
Ao-A,.
"-
OE
OUT._7
SMAP~~--
EOEl
DECODED SRAM ADDRESS
ONLy)
PMD~
"-
ROEH
BHE(WSMAP181
ONLY)
WE/VppOECSIIAx -
OE
v
r---
E
ROEl
CS. CS7
OUT._7
IN._7
A.-A,.
SRAM
2K x 8
WE
OE
IN._7
OUT._7
WEl
EPROM
8K x 8
PGM
1-
SRAM
2K x 8
WE
A.-A'2
OE
IN._7
A.-A,.
v
WEH
r---
1:-
PGMl
(W
v
EPROM
8K x 8
PGM
EOEH
v
"-
A.-A'2
OUT._7
IN0-7
"-
-
{~ ~>
CON
OEl
2:1
MUX
~
10EH
2:1
MUX
fC
Ji-Al~
1-'
I
1-
~0
~
1100_'5 OR CSOO-?
TABLE 1. PRODUCT SELECTION GUIDE
WSMAP162-40
WSMAP161-40
WSMAP162-45
WSMAP161-45
WSMAP162-55
WSMAP161-55
UNITS
Address Access Time (Max.)
40
45
55
ns
Chip Select (CSI) Access Time (Max.)
40
45
55
ns
Output Enable (OE) Access Time (Max.)
18
21
23
ns
Chip Select Output Delay (Max)
22
25
2:l
ns
PARAMETER
TECHNICAL DESCRIPTION
Internally the memory is organized as two 8K x 8 EPROMs and two 2K x 8 SRAMs. The MAp™ memory can be
configured for byte or wordwide operations during the EPROM and PMD™ programming operation by programming
the configuration (CON) bit. In the wordwide operation, the I/Os of the two EPROMs and two SRAMs are common
and are brought out in parallel. In the byte wide operation, the 8 most significant bits of the I/O are multiplexed with
the 8 least significant bits using a multiplexer controlled by address bit Ao. An important feature offered with the byte
wide configuration is the 8 most significant I/O bits are replaced by 8 individual chip select outputs (CSOO-CS0 7)
which can be programmed to select and control other devices (I/O, SRAM, DRAM, etc.).
The PMD™ enables the WSMAP162IWSMAP161 to directly interface with high speed microprocessors and digital
signal processors which require 16K bytes (or 8K words) of EPROM program store and 4K bytes (or 2K words) of
SRAM data store in a non-contiguous address space.
In the byte wide configuration, it is possible (by programming the PMD™) to subdivide and selectively access 8
blocks of EPROM each configured in a 2K x 8 architecture. Anyone of these eight EPROM blocks can be mapped
into any of the 256 available 2K deep blocks in a 512K byte address space. Similarly, the two blocks of SRAM configured
as 2K x 8 can be mapped into any of the 256 2K blocks in a 512K byte address space (not occupied by the EPROM).
3-106
WSMAP162IWSMAP161
The physical blocks of EPROM and SRAM can be concatenated together to form a continuous sequentially addressable
section of memory, placed in non-sequential addressable individual blocks or any combination of the two.
In the wordwide configuration, the EPROM and SRAM are organized as 1K x 16. The PMD™ is used to map the
8 blocks of EPROM and 2 blocks of SRAM into any of the 256 1K blocks in a 256K word address space.
Pin 2 can be configured as a normal address input (''Ax'' or highest address bit) or as a chip select input (CSI). This
is done during the programming of the PMDTM. When configured as an address input, this pin goes directly to the
PMD™ and effectively doubles the address space. When configured as a chip select (CSI), this pin provides a very
low power stand-by mode when the chip is deselected.
In the WSMAP162, pin 39 is an address input (AU> and in the WSMAP161 it is Byte High Enable (BHE). As A17 , it
functions as a normal address input. As BHE, it is used in the x16 (wordwide) configuration if byte operations are
required. The combination of BHE and Ao control the memory access for a word, upper byte, or lower byte operation.
See table 4. This feature reduces the logic required in 16-bit microprocessors and microcontrollers capable of byte
operations. If only word operations are required, BHE and Ao should be connected to ground.
A security bit (SEC) bit is provided that functions as a "bridge" bit. After completion of programming the PMD™ and
EPROM, this bit can be programmed (the "bridge" can be "burned"). This prevents external access to the PMD™
contents and inhibits duplication of the PMD™ data by routine copying.
The WSMAP162IWSMAP161 pin out is derived from the JEDEC standard WSI WS57C257 16K x 16 high speed
EPROM, i.e., itis read compatible. This pinout enables memory expansion with future WSI mapped address products
up to 512K bytes of physical memory. The process technology used in the WSMAP162IWSMAP161 is common to
all of WSI's current family of high speed EPROM and RPROM™ memory products. Both the PMD™ and EPROM
blocks are programmed using the WSI MagicPro™ IBM PC compatible engineering programmer. A menu driven
software package for the IBM PC is provided from WSI to support the special PMD™ address mapping and
configuration.
TABLE 2. MAp™ MEMORY CONFIGURATIONS
WSMAP162 x 8
Pin 2 Configured as
Address Space
Block Size
Addressable Blocks
WSMAP162
x
16
WSMAP161 x 16
CSI
Ax
CSI
Ax
CSI
Ax
256K
Bytes
512K
Bytes
128K
Words
256K
Words
64K
Words
128K
Words
2K Bytes
2K Bytes
1K Words
1K Words
1K Words
1K Words
128
256
128
256
64
128
Available EPROM Blocks
8
8
8
8
8
8
Available SRAM Blocks
2
2
2
2
2
2
Number of Chip Select Outputs
8
8
0
0
0
0
EPROM Size Configuration
16K x 8
16K x 8
8K x 16
8K x 16
8K x 16
8K x 16
SRAM Size Configuration
4K x 8
4K x 8
2K x 16
2K x 16
2K x 16
2K x 16
8
8
16
16
16
16
Number of II0s
Low Power Standby
Yes
No
Yes
No
Yes
No
Protected Mode
Yes
Yes
Yes
Yes
Yes
Yes
Byte Operations
NIA
NIA
No
No
Yes
Yes
NOTE: Ax is Highest Address Bit
3-107
3
WSMAP1621WSMAP161
TABLE 3. MODE SELECTION
~
CSI
OE
WE/Vpp
ADDRESS
I/O
CONFIGURED x16, 1/00 - 15
CONFIGURED x8, 1/00- 7
CHIP SELECTS
CONFIGURED x8,
CSOO-CS0 7
Read EPROM/SRAM
VIL
VIL
VIH
EPROM/SRAM
Selected
DOUT
CSOUT
Read External
VIL
VIL
VIH
EPROM/SRAM
Not Selected
High Z
CSOUT
MODE
Output Disable
X
VIH
X
X
X
CSOUT
VIH
X
X
High Z
Stand-By
High Z
CS OUT
Write SRAM
VIL
X
VIL
SRAM Selected
DIN
CSOUT
X
CS OUT
Write External
VIL
X
VIL
No SRAM
Selected
Program EPROM
VIL
VIH
Vpp
EPROM
Program Address
DIN
DIN
Program Verify EPROM
VIL
VIL
VIH
EPROM
Program Address
DOUT
CS OUT
Program PMD™
VIL
VIH
Vpp
PMD Program
Address
DIN
DIN
Program Verify PMD™
VIL
VIL
VIH
PMD Program
Address
DOUT
CSOUT
TABLE 4. HIGH/LOW BYTE SELECTION TRUTH TABLE (IN x16 CONFIGURATION ONLY)
-
Ao
0
0
Whole Word
0
1
Upper Byte FromlTo Odd Address
1
0
Lower Byte FromlTo Even Address
1
1
None
-
NOTE: WR and BHE are used for SRAM Functions
3-108
OPERATION
SHE (PIN 39)
WSMAP1621WSMAP161
TABLE 5. DC READ CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
Output Low Voltage
VOL
IOL = 16 mA
Output High Voltage
VOH
IOH = -4 mA
Vcc Standby Current CMOS
ISBl
Notes 1 and 3
Vcc Standby Current TTL
ISB2
Notes 2 and 3
MIN
MAX
UNITS
0.4
V
2.4
V
Comm'l
10
mA
Military
20
mA
Comm'l
40
mA
50
mA
Military
Configured
x16
Active Current (CMOS)
No Blocks Selected
Icc 1A
Active Current (CMOS)
EPROM Block Selected
Icc 1B
Active Current (CMOS)
SRAM Block Selected
Icc 1C
Active Current (TTL)
No Blocks Selected
Icc 2A
Active Current (TTL)
EPROM Block Selected
Active Current (TTL)
SRAM Block Selected
Icc 2B
Icc 2C
Notes 1 and 4
Notes 1 and 4
Notes 1 and 4
Notes 2 and 4
Notes 2 and 4
Notes 2 and 4
x8
Comm'l
10
10
mA
Military
20
20
rnA
Comm'l
55
30
mA
Military
65
40
rnA
Comm'l
65
40
mA
Military
75
50
mA
Comm'l
40
40
mA
Military
50
50
mA
Comm'l
85
60
mA
Military
95
70
mA
Comm'l
95
70
mA
Military
105
80
mA
Input Load Current
III
V1N = 5.5V or GND
-10
10
Output Leakage Current
ILO
VOUT = 5.5 or GND
-10
10
NOTES: 1) CMOS inputs: GND ±
2) TTL inputs: V 1L " O.av,
3) A.c. power component
4) A.C. power component
!lA
!lA
0.311 or Vee ± 0.3V
V 1H ;. 2.0V
is 1.5 rnA/MHz (Power = AC + DC)
is 3.5 rnA/MHz (Power = AC + DC)
3-109
WSMAP1621WSMAP161
TABLE 6. AC EPROMISRAM READ AND SRAM WRITE CHARACTERISTICS
PARAMETER
SYMBOL
WSMAP162-40
WSMAP161-40
MIN
MAX
WSMAP162-45
WSMAP161-45
MIN
MIN
45
UNITS
MAX
Read Cycle Time
t RC
Address to Output Delay
t ACC
40
45
55
CSI to Output Delay
tCE
40
45
55
ns
OE to Output Delay
tOE
18
21
23
ns
Output Disable to Output Float
toEF
18
21
23
ns
Chip Disable to Output Float (CSI)
tCSF
18
21
23
ns
Address to Output Hold
tOH
Address to CSO Valid
40
MAX
WSMAP162-55
WSMAP161-55
10
55
10
22
tcso
ns
10
ns
'Zl
25
ns
ns
SRAM Write Cycle Time
twc
40
45
55
Chip Enable to Write End
tcsw
40
45
55
ns
0
0
0
ns
ns
Address Setup Time
tAS
Address Hold Time
tAH
0
0
0
ns
Address Valid to Write End
tAW
40
45
55
ns
SRAM Write Enable Pulse Width
tPWE
25
30
35
ns
tos
20
20
30
ns
tOH
0
Data Setup Time
Data Hold Time
Write Enable to Data Float
Write Disable to Data Low Z
0
0
18
tWEF
21
3
tWELZ
ns
23
3
3
ns
ns
TABLE 7. DATA RETENTION CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
V OR
Minimum Vcc for Data Retention
Current When in Data Retention Mode
IccoR
Chip Deselect to Data Retention
tCSOR
Recovery Time From Data Retention
t ROR
_Vcc = 2.0V,
CSI ~ Vcc -0.2V,
V IN ~ Vcc -0.2V
or V IN ~ 0.2V
DATA RETENTION WAVEFORM
-DATA RETENTION MODE-
vcc
3-110
4.SV
1\
11\
VDR ~ 2V
I
4.5V
MIN
MAX
2.0
UNITS
V
100
!1A
0
ns
t RC
ns
WSMAP1621WSMAP161
ABSOWTE MAXIMUM RATINGS·
*Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature 00000000000 -65°C to +150°C
Voltage to any pin with
respect to GNO 000000000000000000 -Oo6V to +7V
Vpp with respect to GNO 000000000 -Oo6V to +14.0V
ESO Protection 000000. 00000000000000000>2000V
OPERATING RANGE
RANGE
TEMPERATURE
Comm'l
0° to +70°C
+5V
Military
-55° to +125°C
+5V
Vcc
± 5%
± 10%
READ CYCLE TIMING DIAGRAM
TEST WAD
(High Impedance Test Systems)
~------~c------~
ADDRESSES
-----
9S0
2.01V~
D.U.T.
I-=-
30pF
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
TIMING LEVELS
DOUT--+------~~§~~$~~-
Input Levels: 0 and 3V
Reference Levels: 105V
cso __~----J~~----------
WRITE CYCLE TIMING DIAGRAM
ADDRESSES
Iwc
------...
----I
"""'"
"""",,,,""-"\I.
~I
I.......
lAW
'\
t AS
DOUT
D'N
BHE
---
It'
,tAH_
IPWE
tWEF~1
I+---tos
tDHI
1
I
tw,ELZ
I"-
I
r
DATA INVALID
I
/7/
BHE VALID
/
I
3-111
WSMAP1621WSMAP161
MAp™ MEMORY ARCHITECTURE
"-
ADDRESS
1/0
EPROM
-
es
"-
100-
EPROM
es
DIRECT ADDRESSES
100-
"-
100-
EPROM
cs
EPROM
"-
es
v..
es
ADDRESS BUS
.-PMDm
BLOCK DECODE I'
ADDRESSES
--
I
8
ES._7
WENpp
RS._,
eSI/Ax
eso._7
"-
!-
"-
h2 .--
1/0
EPROM
CS
EPROM
4
OE
EPROM
-"
es
EPROM
-
es
"
SRAM
es
~
V
SRAM
cs
WSMAP1621WSMAP161 PIN ASSIGNMENTS
BY 8
BY 16
40 PIN DIP
WE AND BHE ARE USED
FOR SRAM FUNCTIONS
3·112
WENpp
eSI/Ax
es07
eso.
eso.
eso.
eso.
es02
eso,
eso.
GND
1/07
1/06
1/05
1/04
1/03
1/02
1/01
1/00
OE
WE/Vpp
CSl/Ax
1/015
1/014
1/013
1/012
11011
1/010
1109
1/08
GND
1/07
1/06
1/05
1/04
1/03
1102
1/01
1/00
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
0
40
39
38
37
36
35
34
33
32
Vee
A17IBHE
A,.
A,.
A,.
A13
A12
Al1
A,.
As
A.
31
30
29
28
27
26
25
24
23
22
21
GND
GND
A.
A7
A7
Vee
A17IBHE A,.
A,.
A,.
A,.
A'2
Al1
A,.
A.
As
As
A.
A.
A.
A2
A,
A.
A.
A.
A.
A2
A,
A.
WSMAP162
WSMAP161
PIN 39
A17
BHE
WSMAP1621WSMAP161
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WSMAP1621WSMAP161 has
all bits in the PMD™ and EPROM in the "1" or high state.
"O's" are loaded through the procedure of programming.
Information for programming the PMD™ and EPROM is
available directly from WSI. Please contact your local sales
representative.
obtained by exposure to an ultra-violet lamp with wavelength
of 2537 Angstrom (A) with intensity of 1200011 W/cm 2 for 15 to
20 minutes. The WSMAP1621161 should be about one inch from
the source and all filters should be removed from the UV light
source prior to erasure.
It is important to note that the WSMAP162/161 and similar
devices will erase with light sources having wavelengths shorter
than 4000A. Although erasure times will be much longer than
with UV sources at 2537 the exposure to fluorescent light and
sunlight will eventually erase the WSMAP1621161 and exposure
to them should be prevented to realize maximum system
reliability. If used in such an environment, the package windows
should be covered by an opaque label or substance.
A.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the MAp™ Memory to an ultra-violet
light source. A dosage of 15W-second/cm2 is required to
completely erase the part. This dosage can be
ORDERING INFORMATION
PART NUMBER
WSMAP162-40D
WSMAP162-40P
WSMAP161-40D
WSMAP161-40P
WSMAP162-45D
WSMAP162-45P
WSMAP161-45D
WSMAP161-45P
WSMAP162-55D
WSMAP162-55DMB
WSMAP162-55P
WSMAP161-55D
WSMAP161-55DMB
WSMAP161-55P
SPEED
PACKAGE
TYPE
(ns)
40
40
40
40
40
40
40
40
55
55
55
55
55
55
40
40
40
40
40
40
40
40
40
40
40
40
40
40
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
CERDIp, 0.6"
Plastic DIP, 0.6"
CERDlp, 0.6"
Plastic DIP, 0.6"
CERDlp, 0.6"
Plastic DIP, 0.6"
CERDlp, 0.6"
Plastic DIP, 0.6"
CERDlp, 0.6"
CERDlp, 0.6"
Plastic DIP, 0.6"
CERDlp, 0.6"
CERDlp, 0.6"
Plastic Dip, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
D3
P1
D3
P1
D3
P1
D3
P1
D3
D3
P1
D3
D3
P1
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Comm'l
Military
Comm'l
Comm'l
Military
Comm'l
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
Standard
MIL-STO-883C
Standard
Standard
MIL-STD-883C
Standard
3-113
3·114
WSMAP168
ADVANCE INFORMATION
WAFERSCALE INTEGRA710N, INC.
HIGH SPEED MAPPABLE
MEMORY (MAp™)
KEY FEATURES
• Addressable Range
• Super Fast Access Time
-
EPROM/SRAM: 40 ns (including decode)
Chip Select Outputs: 22 ns
Fast Chip Select Output: 17 ns
• High Density UV Erasable EPROM
-
128K Bits
• High Density 6-Transistor Static RAM
-
32K Bits
• On-Board Programmable Address Decoder
-
Eliminates External Chip-Select Decode
Components and Delay
• Code Security
-
Contains Programmable Security Bit
-
2M Bytes or 1M Words
• Block Resolution
-
2K Bytes or 1K Words
D
• Chip Select Outputs
-
Control I/O and Other Devices
9 in Byte Wide Mode
1 in Word Wide Mode
• Fully User Configurable
-
Byte or Word Operation
• Reduces Board Space
-
Simplifies Routing
Replaces 2 or more EPROMs, 2 or more
SRAMs and One Decoder
GENERAL DESCRIPTION
The WSMAP168 is a Mapped Address Programmable (MAp™) memory product that integrates 128K bits of EPROM,
32K bits of SRAM and a Programmable Mapping Decoder (PMD™) into a single 44-pin package. With a wide input
addressing range, this memory product is compatible with large address space processor systems. The on-board
PMD™ enables the placement of physical 16K bytes or 8K words of EPROM and 4K bytes or 2K words of SRAM
anywhere in a total address space of 2M bytes or 1M words respectively. The PMD™ reduces system component
count as well as board space, enhances performance and increases data security. The major feature of this product
is the integration of high speed, high density UV erasable EPROM and a 6-transistor full CMOS SRAM along with
decoding logic on a single chip.
The WSMAP168 combines the features of the WSMAP162 and WSMAP161 MAp™ products into a single 44 pin
package.
The WSMAP168 is ideal for use with digital signal processors like the TMS320XX series, high-performance
microcontrollers and microprocessors using a 16-bit data bus. Its data path can be programmed as either 8 or 16 bits.
With the provision of Pin 3 programmable as either Chip Select (CSI) or the highest address bit, its address
range is from 512K to 1M words or 1M to 2M bytes. The EPROM architectures are 16K x 8 (byte operations) or 8K x 16
(word operations). The SRAM architectures are 4K x 8 (byte operations) or 2K x 16 (word operations).
With BHE (Byte High Enable) in the 16-bit mode, the WSMAP168 can accommodate either full word or byte operations
(for those 16-bit processors capable of byte operations).
Refer to Application Note 002 in this databook for additional information.
3-115
WSMAP168
BWCK DIAGRAM
DECODED EPROM ADDRESS
Ao-A,.
"
OE
OUTO_7
PGML
V
EOEL
"
DECODED SRAM ADDRESS
PMD"
WEH
Ao-A,o
OE
FCSO-
OUT0-7 . 1No_7
1-
"" m"
OUTO_7
EPROM
8K x 8
PGM
I----v
INo_7
Ao-A,o
OE
SRAM
2K x 8
OUTO_7
E~
WEL
CSI/Ax -
Ao-A,.
OE
INo_7
I:
WE
BHE-
OE-
r---
SRAM
ROEH
WElV pp -
1--------..
EPROM
8K x 8
PGM
EOEH
-"
"
Ao-A,.
v
PGMH
ROEL
CSO-CS7
J
CON
OEL
2:1
MUX
~
...
~
---'
~
1No_7
L
~
2:1
MUX
ir
R.,,~
a
1-
TABLE 1. PRODUCT SELECTION GUIDE
PARAMETER
WSMAP168-40
WSMAP168-45
WSMAP168-55
UNITS
Address Access Time (Max.)
40
45
55
ns
Chip Select (CSI) Access Time (Max.)
40
45
55
ns
Output Enable (OE) Access Time (Max.)
18
21
23
ns
Chip Select Output (CSOO-CS0 7)
22
25
27
ns
Fast Chip Select (FCSO) Output Time (Max.)
17
20
22
ns
TECHNICAL DESCRIPTION
Internally the memory is organized as two 8K x 8 EPROMs and two 2K x 8 SRAMs. The WSMAP168 can be configured
for byte or wordwide operations during the EPROM and PMD™ programming operation by programming the
configuration (CON) bit. In the wordwide operation, the II0s of the two EPROMs and two SRAMs are common and
are brought out in parallel. In the byte wide operation, the 8 most significant bits of the 1/0 are multiplexed with the
8 least significant bits using a multiplexer controlled by address bit Ao. An important feature offered with the byte
wide configuration is the 8 most significant 1/0 bits are replaced by 8 individual chip select outputs (CSOO-CS07)
which can be programmed to select and control other devices (110, SRAM, DRAM, etc.). A single fast chip select
output (FCSO) is provided regardless of byte or wordwide mode selection.
The PMD™ enables the WSMAP168 to directly interface with high speed microprocessors and digital signal
processors which require 16K bytes (or 8K words) of EPROM program store and 4K bytes (or 2K words) of SRAM
data store in a non-contiguous address space.
In the byte wide configuration, it is possible (by programming the PMD™ to subdivide and selectively access 8 blocks
of EPROM each configured in a 2K x 8 architecture. Anyone of these eight EPROM blocks can be mapped into
any of the 1024 available 2K deep blocks in a 2M byte address space. Similarly, the two blocks of SRAM configured
3-116
WSMAP168
as 2K x 8 can be mapped into any of the 1024 2K blocks in the 2M byte address space (not occupied by the EPROM).
The physical blocks of EPROM and SRAM can be concatenated together to form a continuous sequentially addressable
section of memory, placed in non-sequential addressable individual blocks or any combination of the two.
In the wordwide configuration, the EPROM and SRAM are organized as 1K x 16. The PMD™ is used to map the
8 blocks of EPROM and 2 blocks of SRAM into any of the 1024 blocks in a 1M word address space.
Pin 3 (CSI/A x) is a dual function input. It is always an address (MSB) input. Optionally, it can be programmed to be a
chip select input as well which enables the EPROM and SRAM memory when active low. In a system application,
usually one or the other modes is employed but rarely both even though it is possible to employ both modes
simultaneously. CSOs are not powered down since they are a function of the address input and the (always powered up)
PMDTM.
In the x16 (wordwide) configuration, pin 1 is used as a Byte High Enable (BHE) control (if byte operations are required).
The combination of BHE and Ao control the memory access for a word, upper byte, or lower byte operation. See
table 4. This feature reduces the logic required in 16-bit microprocessors and microcontrollers capable of byte operations.
If only word operations are required, BHE and Ao should be connected to ground.
A security bit (SEC) is provided that functions as a "bridge" bit. After completion of programming the PMD™ and
EPROM, this bit can be programmed (the "bridge" can be "burned"). This prevents external access to the PMD™
contents and inhibits duplication of the PMD™ data by routine copying.
The WSMAP168 pinout is derived from the JEDEC standard WSI WS57C257 16K x 16 high-speed EPROM, i.e.,
it is read compatible. This pinout enables memory expansion with future WSI mapped address products up to 2M
bytes of physical memory. The process technology used in the WSMAP168 is common to all of WSI's current family
of high-speed EPROM and RPROM™ memory products. Both the PMD™ and EPROM blocks are programmed using
the WSI MagicPro™ (or other) programmer. A menu driven software package for the IBM PC is provided from WSI
to support the special PMD™ address mapping and configuration.
TABLE 2. WSMAP168 CONFIGURATIONS
WSMAP168 x 8
Pin 2 Configured as
CSI
Address Space
1M Bytes
Block Size
WSMAP168 x 16
Ax
CSI
Ax
2M Bytes
512K Words
1M Words
2K Bytes
2K Bytes
1K Words
1K Words
512
1024
512
1024
Available EPROM Blocks
8
8
8
8
Available SRAM Blocks
2
2
2
2
Addressable Blocks
Number of Chip Select Outputs
9
9
1
1
EPROM Size Configuration
16K x B
16K x 8
BK x 16
8K x 16
SRAM Size Configuration
4K x B
4K x B
2K x 16
2K x 16
B
B
16
16
Number of II0s
Low Power Standby
Yes
No
Yes
No
Protected Mode
Yes
Yes
Yes
Yes
Byte Operations
NIA
NIA
Yes
Yes
3-117
3
WSMAP168
TABLE 3. MODE SELECTION
CSI
OE
WE/Vpp
ADDRESS
CONFIGURED x16
1/00- 15
CONFIGURED x8
1/00- 7
Read EPROM/SRAM
VIL
VIL
VIH
EPROM/SRAM
Selected
DOUT
CSOUT
Read External
VIL
VIL
VIH
EPROM/SRAM
Not Selected
High Z
CSOUT
Output Disable
X
VIH
X
X
High Z
CSOUT
PIN
MODE
CONFIGURED x16 FCSO
CONFIGURED x8 FCSO,
CSOO-CS07
Stand-By
V IH
X
X
X
High Z
CSOUT
Write SRAM
VIL
X
VIL
SRAM Selected
DIN
CSOUT
Write External
VIL
X
VIL
No SRAM
Selected
X
CSOUT
Program EPROM
VIL
VIH
Vpp
EPROM
Program Address
DIN
DIN
Program Verify EPROM
VIL
VIL
VIH
EPROM
Program Address
DOUT
CSOUT
Program PMD™
VIL
VIH
Vpp
PMD Program
Address
DIN
DIN
Program Verify PMD™
VIL
VIL
VIH
PMD Program
Address
DOUT
CSOUT
TABLE 4. HIGH/LOW BYTE SELECTION TRUTH TABLE (IN x16 CONFIGURATION ONLY)
BHE (PIN 1)
Ao
0
0
Whole Word
0
1
Upper Byte FromfTo Odd Address
1
0
Lower Byte FromfTo Even Address
1
1
None
NOTE: WR and SHE are used for SRAM Functions
3-118
OPERATION
WSMAP168
TABLE 5. DC READ CHARACTERISTICS
PARAMETER
SYMBOL
TEST CONDITIONS
Output Low Voltage
VOL
'OL=8rnA
Output High Voltage
VOH
IOH = -2 rnA
Vcc Standby Current CMOS
IS81
Notes 1 and 3
Vcc Standby Current TTL
IS82
Notes 2 and 3
MIN
MAX
UNITS
0.45
V
Cornrn'l
10
rnA
Military
20
rnA
Cornrn'l
40
rnA
Military
50
rnA
2.4
V
Configured
x16
x8
Active Current (CMOS)
No Blocks Selected
Icc 1A
Active Current (CMOS)
EPROM Block Selected
Icc 1B
Active Current (CMOS)
SRAM Block Selected
Icc 1C
Active Current (TTL)
No Blocks Selected
Active Current (TTL)
EPROM Block Selected
Active Current (TTL)
SRAM Block Selected
Input Load Current
Output Leakage Current
Icc 2A
Icc 2B
Icc 2C
Notes 1 and 4
Notes 1 and 4
Notes 1 and 4
Notes 2 and 4
Notes 2 and 4
Notes 2 and 4
Cornrn'l
10
10
rnA
Military
20
20
rnA
Cornrn'l
55
30
rnA
Military
65
40
rnA
rnA
Cornrn'l
65
40
Military
75
50
rnA
Cornrn'l
40
40
rnA
Military
50
50
rnA
Cornrn'l
85
60
rnA
Military
95
rnA
Cornrn'l
95
70
70
80
rnA
Military
105
III
V 1N = 5.5V or GND
-10
10
ILO
VOUT = 5.5V or GND
-10
10
rnA
IlA
IlA
NOTES: 1) CMOS inputs: GND ± 0:311 or Vee ± 0:311
2) TTL inputs: V 1L " OlN, V 1H ;;. 2.OV
3) A.C. power component is 1.5 rnA/MHz (Power = AC + DC)
4) A.C. power component is 3.5 rnA/MHz (Power = AC + DC)
3-119
WSMAP168
TABLE 6. AC EPROMISRAM READ AND SRAM WRITE CHARACTERISTICS
WSMAP168-40
PARAMETER
SYMBOL
Read Cycle Time
t RC
Address to Output Delay
tACC
CSI to Output Delay
tCE
OE to Output Delay
toE
Output Disable to Output Float
tOEF
Chip Disable to Output Float
tCSF
Address to Output Hold
tOH
Address to CSOO_7 True
tcso
Address to FCSO True
t FCSO
SRAM Write Cycle Time
twc
Chip Enable to Write End
tesw
Address Setup Time
tAS
Address Hold Time
tAH
Address Valid to Write End
tAW
SRAM Write Enable Pulse Width
tos
Data Hold Time
tOH
MAX
MIN
40
MAX
25
20
45
45
0
0
30
20
0
21
tWELZ
3
ns
ns
ns
ns
ns
ns
22
ns
ns
ns
ns
ns
ns
ns
ns
ns
23
3
3
ns
'Zl
55
55
0
0
55
35
30
0
45
18
Write Disable to Data Low Z
10
10
UNITS
ns
55
55
23
23
23
21
21
21
40
40
0
0
40
25
20
0
MAX
55
45
22
17
tWEF
MIN
45
10
Write Enable to Data Float
WSMAP168-55
45
40
40
18
18
18
tpWE
Data Setup Time
MIN
WSMAP168-45
ns
ns
TABLE 7. DATA RETENTION CHARACTERISTICS
PARAMETER
SYMBOL
Minimum Vee for Data Retention
V OR
Current in Data Retention Mode
leeoR
Chip Deselect to Data Retention
tesoR
Recovery Time From Data Retention
t ROR
TEST CONDITIONS
_Vee = 2.0V,
CSI ~ Vee -0.2V,
V IN ~ Vee -0.2V
or V IN ~ 0.2V
DATA RETENTION WAVEFORM
I---DATA RETENTION MODE--
VCC
3-120
4.5V
1\
VOR
;'
2V
I
4.5V
MIN
MAX
2.0
UNITS
V
100
mA
0
ns
t RC
ns
WSMAP168
ABSOWTE MAXIMUM RATINGS·
-Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Storage Temperature ........... -65°C to +150°C
Voltage to any pin with
respect to GND .................. -0.6V to +7V
Vpp with respect to GND ......... -0.6V to +14.0V
ESD Protection ........................ >2000V
OPERATING RANGE
RANGE
TEMPERATURE
Vcc
Comm'l
0° to +70°C
+5V + 5%
Military
-55° to +125°C
+5V + 10%
D
READ CYCLE TIMING DIAGRAM
I RC
ADDRESSES
=::)<
X
IACC
TEST LOAD
_ I ow-·
"-
(High Impedance Test Systems)
.J/
980
IcsF i---
j---ICE--
~
2.01V~
/
D.U.T.
I-
10E
I-=
DATA VALID
DOUT
I-
tOEF-..I
30pF
(INCLUDING SCOPE
AND JIG
CAPACITANCE)
TIMING LEVELS
~
Input Levels: 0 and 3V
_ I rcso -
Reference Levels: 1.5V
leso
WRITE CYCLE TIMING DIAGRAM
IWC
ADDRESSES
~
""'"
K"",-"'-~
L
I
tcsw
lAW
'\
lAS
DOUT
-
It"
I
IPWE
IWEF,I
AH
_
I
10H
I+--Ios
'I
I
I'
I
IjEU
I'..
SHE VALID
DATA INVALID
-tT
I
/
/
/
/
/
/
3-121
WSMAP168
MAP'" MEMORY ARCHITECTURE
A
ADDRESS
es
r-
EPROM
EPROM
CS
~
DIRECT ADDRESSES
~
I
v
t-.
EPROM
CS
EPROM
~
v..
CS
~
v..
CS
ADDRESS BUS
BLOCK DECODE
ADDRESSES
PMD'·
v
-----
ESo_7
WE/Vpp
CSl/Ax
OE
~
CSOG-7
~
FCSO ~
8
~
EPROM
CS
'"
RS O_1
EPROM
CS
~
v
L...-
I
I
I
I
I
I
I
EPROM
CS
I
0---
3-122
v.
EPROM
1/0
I
v..
'v.."
es
SRAM
SRAM
CS
I
1/0
WSMAP168
WSMAP168 PIN ASSIGNMENTS
44 PIN PLDCC PACKAGE
44 PAD CLLCC PACKAGE
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
44 PIN CPGA PACKAGE
x8
x16
GND
WENpp
CSl/Ax
CS0 7
CSO.
CSO.
CSO.
CSO.
CSO.
CSO,
CSOO
GND
FCSO
1107
110.
I/O.
liD.
I/O.
I/O.
liD,
1/00
DE
Ao
A,
A.
A.
A.
A.
A.
A7
A.
A.
A10
GND
BHE
WENpp
CSI/Ax
I/O,.
I/O,.
I/O,.
I/O,.
I/O"
1/0'0
liD.
I/O.
GND
FCSO
1/07
I/O.
I/O.
I/O.
liD.
I/O.
liD,
1100
DE
Ao
A,
A.
A.
A.
A.
A.
A7
A.
A.
A10
GND
A"
A,.
A'3
A,.
A,s
A,.
A'7
A,.
A,.
Vee
A"
A,.
A,.
A,.
A,.
A,.
A'7
A,.
A,.
Vee
PIN
NO.
A.
A.
B.
A.
B.
A.
B.
B,
C.
C,
D.
0,
E,
E.
F,
F.
G,
G.
H.
G.
H.
G.
H.
Hs
Gs
H.
G.
H7
G7
G.
F7
F.
E7
E.
D.
07
C.
C7
B.
B7
A7
B.
A.
Bs
x8
x16
GND
WE/Vpp
CSIlAx
CS07
CSO.
CSOs
CSO.
CSO.
CSO.
CSO,
CSOo
GND
FCSO
1/07
I/O.
liD.
I/O.
liD.
liD.
I/O,
1/00
DE
Ao
A,
A.
A.
A.
As
A.
A7
A.
A.
A,o
GND
BHE
WENpp
CSI/Ax
I/O,.
I/O,.
liD,.
liD,.
liD"
110'0
liD.
liD.
GND
FCSO
110 7
I/O.
liDs
liD.
1103
liD.
I/O,
1100
DE
Ao
A,
A.
A.
A.
As
A.
A7
A.
A.
A,o
GND
A"
A,.
A,.
A,.
A,.
A,.
A17
A,.
A,.
Vee
A"
A,.
A,.
A,.
A,.
A,.
A17
A,.
A,.
Vee
--
-
NOTE: WR and BHE functions are for SRAM functions.
WSMAP168 PIN ASSIGNMENTS
44 PIN CPGA PACKAGE
3 4 5 6 7
44 PIN PLDCC PACKAGE
6 5 4
7
3 2
, 4443.2 41 40
IIII1111111I1111111 III
_,LJ LJ LJ LJ LJ
LJ LJ L..I LJ LJ,_
i:
_..I
10
--,
11
12
13
14
15
16
=J
LJ
L..._
_"
_oJ
_J
_...I
_...J
39
38
37
36
35
34
33
32
31
30
29
A
B
C
0
E
F
G
H
44 PAD CLLCC PACKAGE
8
000000
00000000
00
00
00
00
00
00
00
00
00000000
000000
6 5 4 3 2 14443424140
7
8
9
10
11
12
13
14
15
16
17
LJUUUU!!UUUULJ
'\
u
C
~
_J
~-
-,
_ J
_J
_J
-"
_ J
_J
_ J
_-'
r1
0
r1 r1 rl r1 rl rl r1 rl r, r,
L_
L _
~-
rL_
L _
~L
_
L.._
~
38
37
36
35
34
33
32
31
30
29
11111 1 11111 1 1.11111111/
18 19 20 21 22 23 24 25 26 27 28
18 19 20 21 22 2324 25 26 27 28
TOP (THROUGH PACKAGE) VIEW
3-123
WSMAP168
PROGRAMMING
Upon delivery from WaferScale Integration, Inc. or after each
erasure (see Erasure section), the WSMAP168 has all bits in
the PMD™ and EPROM in the "1" or high state. "O's" are
loaded through the procedure of programming.
Information for programming the PMDTM and EPROM is
available directly from WSI. Please contact your local sales
representative.
ERASURE
In order to clear all locations of their programmed contents,
it is necessary to expose the WSMAPl68 to an ultra-violet light
source. A dosage of 15W-secondlcm2 is required to completely
erase a WSMAP168. This dosage can be obtained by exposure
to an ultra-violet lamp with wavelength of 2537 (A) with intensity
of 120011 W/cm 2 for 15 to 20 minutes. The WSMAP168 should
be about one inch from the source and all filters should be
removed from the UV light source prior to erasure.
It is important to note that the WSMAPl68 and similar devices
will erase with light sources having wavelengths shorter than
4000A. Although erasure times will be much longer than with
UV sources at 2537A. the exposure to fluorescent light and
sunlight will eventually erase the WSMAP168 and exposure to
them should be prevented to realize maximum system reliability.
If used in such an environment, the package windows should
be covered by an opaque label or substance.
ORDERING INFORMATION
PART NUMBER
WSMAP168-40C
WSMAP168-40CMB
WSMAP168-40J
WSMAP168-40X
WSMAP168-40XMB
WSMAP168-45C
WSMAP168-45CMB
WSMAP168-45J
WSMAP168-45X
WSMAP168-45XMB
WSMAP168-55C
WSMAP168-55CMB
WSMAP168-55J
WSMAP168-55X
WSMAP168-55XMB
3-124
SPEED
PACKAGE
TYPE
(ns)
40
40
40
40
40
45
45
45
45
45
55
55
55
55
55
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
Pad CLLCC
Pad CLLCC
Pin PLOCC
Pin Ceramic
Pin Ceramic
Pad CLLCC
Pad CLLCC
Pin PLOCC
Pin Ceramic
Pin Ceramic
Pad CLLCC
Pad CLLCC
Pin PLOCC
Pin Ceramic
Pin Ceramic
PGA
PGA
PGA
PGA
PGA
PGA
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
C3
C3
J2
X2
X2
C3
C3
J2
X2
X2
C3
C3
J2
X2
X2
Comm'l
Military
Comm'l
Comm'l
Military
Comm'l
Military
Comm'l
Comm'l
Military
Comm'l
Military
Comm'l
Comm'l
Military
Standard
M IL-STO-883C
Standard
Standard
MI L-STO-883C
Standard
MIL-STO-883C
Standard
Standard
MIL-STO-883C
Standard
MIL-STO-883C
Standard
Standard
MIL-STO-883C
--
.~1E1E':::
.....,.-......,
-....., .....,
'i=:=_=-!!F;'
--- ---~ IE
-
WAFERSCALE INTEGRA nON, INC.
, m."III"If:
,
iC"
,
e,
'
11J.1~1l!l:lr1ml!.tl~1'1
'"
4
SECTION INDEX
CMOS BIT SLICE PRODUCTS
WS5901
WS59016
WS59032
WS5910AlB
WS59510
WS59520/521
WS59820
4-Bit CMOS Bit Slice Processor ............................................. 4-1
16-Bit CMOS Bit Slice Processor ............................................ 4-9
32-Bit CMOS Bit Slice Processor ........................................... 4-21
CMOS Microprogram Controller ............................................ 4-33
16 x 16 CMOS Multiplier Accumulator ...................................... 4-43
Multilevel CMOS Pipeline Register ......................................... 4-51
Bi-Directional CMOS Bus Interface Register .................................. 4-55
For additional information,
call 800-TEAM-WSI (800-832-6974).
In California, call 415-656-5400.
WS5901
WAFERSCALE INTEGRA170N, INC.
CMOS 4-81T HIGH-SPEED MICROPROCESSOR SLICE
KEY FEATURES
• 2901 Architecture in CMOS
• High Speed
-
• Drop-In Replacement for 2901C
• Expandable in 4-Bit Increments
Maximum Clock Frequency of 43 MHz (23 ns)
• Very Low Power
-
30 mA Maximum (Commercial Temperature)
• EPI Processing
-
Latch-Up Immunity Over 200 mA
GENERAL DESCRIPTION
The WS5901 is a 4-bit high-speed microprocessor which contains the logic of a Bipolar 2901 bit slice processor.
This microprogram mabie circuit has the flexibility to efficiently emulate almost any digital computing machine. It is
an ideal candidate for such applications as peripheral controllers, CPUs, programmable microprocessors, and Digital
Signal Processors.
The advanced CMOS process, with which the 5901 is manufactured, provides significant performance improvements
over its counterpart. While operating as fast as a 2901C based system, the WS5901C requires less than 8% of the
power consumed by its Bipolar equivalent. The WS5901D is a 25% speed enhancement over the "C" speed.
The WS5901 is also a macro cell in the WaferScale cell library. As such it can be combined with other cells to build
High Performance CMOS Application Specific Integrated Circuits.
FUNCTIONAL BLOCK DIAGRAM
0
~ -1
CP
=::J:::"=:::fr--;,."
w
c
3
r... ~rV' r-4
_o~
i
(READ/WR,IT_E.:..:l
ADDRESS,
0
:>
z
0
c
2
III
ID
w
"A" (READl--~
ADDRESS
"8"
ALU
SOURCE
z
0
ALU
FUNCTION
~
:>
a:
5
In
z
6
0
is
a:
r~ r-7 DESTINATION
CONTROL
i
a
OUTPUT DATA MUX
4-1
WS5901
PIN DESCRIPTION
Signal Name
I/O
Description
AO-3
I
Addresses which select the word of on board RAM which is to be displayed through the A port_
80-3
I
Addresses which select the word of on board RAM which is to be displayed through the B port and into which
data is written when the clock is low.
10-8
I
Block of three instruction groups whic·h are to select 1) which data sources will be applied to the ALU (1012), 2)
what function the ALU will perform (1345), and 3) what data is to be written into the Q register or on board
RAM(l678).
Q3, RAM3
I/O
Signal paths at the MSB of the on-board RAM and the Q-register which are used for shifting data. When the
destination code on 1678 indicates an up shift (Octal 6 or 7) the three state outputs are enabled and the
MSB of the ALU output is available on the RAM 3 pin and the MSB of the Q-register is available on the Q3
pin. Otherwise, the pins appear as inputs.
When the destination code calls for a down shift, the pins are
used as the data inputs to the MSB of RAM (octal 4 and 5) and the Q register (octal 4).
Qo, RAMo
I{O
Shift lines similar to Q3 and RAM3. However the description is applied to the LSB of RAM and the Qregister.
00-03
I
These four direct data inputs can be selected as a data source for the ALU. DO is the LSB.
YO-Y3
0
These four three state outputs, when enabled, display either the data on the A-port of the register stack or
the outputs of the ALU as determined by the destination code 1678.
OE
I
When high, the Y outputs are in the high impedance state. When low, either the contents of the Aaregister or
G,P
0
The carry generate and propagate outputs of the ALU.
OVR
0
This signal indicates that an overflow into the sign bit has occurred as a result of a two's complement operation.
F= 0
0
This output, when high, indicates the result of an ALU operation is zero.
F3
0
The most significant ALU output bit.
Cn
I
The carry-in to the ALU.
the outputs of the ALU are displayed on YO- Y3 , as determined by 1678.
Cn+4
CP
0
I
The carry-out of the ALU.
This clock Signal is applied to the A and B-port latches, RAM, and Q-register. The clock low time is the write
enable to the on-board 16 x 4 RAM, including set-up time for the A and B port registers. The A and B port
and Q-register outputs change on the clock low-to-high transition.
PIN DESIGNATOR
Plastic Package
A3
OE
A_
Y3
A,
Y-
Ao
Y,
I.
Yo
I.
P
17
OVR
RAM3
Cn+ 4
RAMo
G
F3
Vce
F = 0
10
GND
Cn
12
I,
I.
I_
14
I.
CP
15
13
Q.
16
Do
Bo
17
0,
B_
19
D.
B.
20
Qo
D_
B,
TOP
4-2
WS5901
ABSOWTE MAXIMUM RATINGS*
*Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Operating Temp (Comm'l) ........ O°C to +70°C
(Mil) ........ -55°C to +125°C
Storage Temp. (No Bias) ...... -65°C to +150°C
Voltage on Any Pin with
Respect to GND .............. -0.6V to +7V
Latch-Up Protection ................. >200 mA
ESD Protection .................... > ±2000V
DC READ CHARACTERISTICS Over Operating Temperature Range (Note 1)
MIN MAX UNITS
TEST CONDITIONS
PARAMETER
SYMBOL
VOH
Output High Voltage
Vee = Min
VIN = V IH or V IL
VOL
Output Low Voltage
Vee = Min
V IN = V IH or VIL
V IH
Input High Voltage
Guaranteed Input High Voltage
V IL
Input Low Voltage
Guaranteed Input Low Voltage
All Outputs IOH
YO-Y3
IOL
All Others
IOL
= -1.6 mA
= 20 mA Comm'l
= 16 mA
2.4
0.5
2.0
0.8
Ilx
Input Load Current
Vee
= Max,
V IN
= Gnd or Vee
-10
loz
High Impedance
Output Current
Vee
= Max,
Vo
= Gnd or Vee
-50
lee
Power Supply Current Vee
= Max (Note 2)
NOTES: 1) Commercial: Vee = +5V ± 5%, TA = O·C to 700C.
V
10
50
30
Comm'l (O°C to +70°C)
ItA
mA
2) 100 ns System Cycle
P, C n +4, andOVR
The four signals, G, P, Cn + 4 and OVR are designed
Definitions (+ = OR)
to indicate carry and overflow conditions when the
Po = Ro + So
Go = RoSo
WS5901 is in the add or subtract mode. The table
P1 = R1 + S1
G1 = R1S1 .
below indicates the logic equations for these four
P2 = R2 + S2
G2 = R2S2
signals for each of the eight ALU functions. The R
P3 = R3 + 53
G3 = R3S3
C4 = G3 + P3G2 + P3 P2G1 + P3 P2GO + P3 P2 P1 PoC n
and S inputs are the two inputs selected according
C3= G2+ P2G1 + P2P1GO+ P2 P1 PoCn
to Table 1.
LOGIC FUNCTIONS FORG,
1543
Function
a
R+ S
1
S- R
..
Same as R + S equations, but substitute Ri for Ri in definitions
2
R-S
.
Same as R + S equations, but substitute Si for Si in definitions
3
RVS
LOW
P3 P2P1PO
4
RIIS
LOW
G3 + G2 + G1 + Go
5
RIIS
LOW
6
RYS
7
RYS
NOTES:
1)
2)
P
G
P3 P2P1Po G3 + P3G2 +P 3 P2G1+ P3 P2P1GO
Cn +
OVR
4
C 3 Y C4
C4
P3 P2P1Po+Cn
•
.
P3P2P1Po+Cn
G3 +G2+ G1+GO +C n G3 +G2+ G1+GO+ C n
_ _ Same as R II S equations, but substitute Ri for Ri in definitions _
.
..
Same as R ¥S equations, but substitute Ri for Ri in definitions
G3 + G2
+ G1 + Go
-
P3G2 +P3 P2G1+ P 3 P2P1GO
G 3+ P3G2 + P3P2G1
+ P3 P2P1Po (Go+Cn)
(I':! + G2f'1 + G2G1PO+ G2G1GOCn)¥ (P3 + G3P2 + G3G2f'1 + G3G2G1PO + G3G2G1GoCn)
+ = OR
See note 1
WS5901
FUNCTIONAL TABLES
ALU SOURCE
OPERANDS
MICROCODE
Mnemonic
AO
AB
ZO
ZB
ZA
DA
DO
DZ
MICROCODE
Mnemonic
Octal
12 11 10 Code
R
S
L
L
L
L
H
H
H
H
A
A
0
0
0
D
D
D
0
B
0
B
A
A
0
0
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
ADD
SUBR
SUBS
OR
AND
NOTRS
EXOR
EXNOR
RAM
FUNCTION
MICROCODE
OREG
NOP
RAMA
RAMF
RAMOD
RAMD
RAMOU
RAMU
Octal
18 17 16 Code
L L L
0
1
L L H
L H L
L H H
2
3
H L L
H L H
H H L
H H H
4
5
6
7
SHIFT
X
X
NONE
NONE
DOWN
DOWN
UP
UP
ALU
Function
SYMBOL
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
R Plus S
S Minus R
R Minus S
R ORS
RAND S
RAND S
R EXOR
R EX·NORS
R+ S
S-R
R-S
RvS
RIIS
RIIS
RVS
FfV"S
Table 2. ALU Function Control.
Table 1 : ALU Source Operand Control.
Mnemonic
Octal
15 14 13 Code
Q-REG.
FUNCTION
LOAD
SHIFT
NONE
NONE
Y OUTPUT
F-O
NONE
X
X
NONE
NONE
X
F/2-B DOWN 0/2-0
X
NONE
F/2-B
2F-B
UP
20-0
X
NONE
2F-B
Q SHIFTER
RAMo
RAM3
Qo
Q3
F
X
X
X
X
F
A
F
X
X
X
X
X
X
X
X
X
X
X
X
Fo
Fo
IN3
IN3
IN3
X
INo
INo
F3
F3
00
00
INo
X
LOAD
NONE
F-B
F-B
RAM
SHIFTER
F
F
F
F
03
03
x=
Don't care.
B = Register Addressed by B inputs.
DOWN is toward LSB. UP is toward MSB.
Table 3. ALU Destination Control.
1210
1543
(Octal Code)
0
1
2
3
4
5
6
7
ALU
Function
Cn = L
R Plus S
Cn = H
(Octal Code)
4
3
ALU Source (R, S)
O,B
O,A
5
6
7
O,A
O,Q
0,0
D+ A
D+ 0
D
0
1
2
A,Q
A, B
O,Q
A+ 0
A+ B
0
B
A
0+1
B+ 1
A+1
D+ A+ 1 D+ 0+ 1
A+ 0+ 1 A+ B+ 1
Cn = L
S Minus R
Cn = H
0-A-1
B-A-1
0-1
B-1
A-1
A-D-1
0- D-1
- D-1
O-A
B-A
0
B
A
A-D
O-D
-D
Cn = L
R Minus S
Cn = H
A- 0-1
A-B-1
-0-1
-B-1
-A-1
D-A-1
D- 0-1
D-1
A-O
A-B
-0
-B
-A
D-A
D-O
D
RORS
RAND S
RAND S
REX-OR S
AvO
AIIO
AIIO
AvB
B
0
B
B
A
0
A
AVO
0
0
0
0
DvA
DIIA
DIIA
DvA
DvO
AIIB
AIIB
AvB
OliO
DIIO
DvO
D
0
0
D
REX-NORS
~
AvB
a
B
OvA
DvO
D
+ - Plus; - - Minus; v - OR;
A -
A
A
AND; v - EX-OR.
Table 4. Source Operand and ALU Function Matrix.
4-4
D+1
WS5901
SOURCE OPERANDS AND ALU FUNCTIONS
Eight source operand pairs are available to the ALU as determined by the 10, 11, and 12 instruction
inputs. The ALU performs eight functions; three arithmetic and five logic. This function selection is
controlled by the 13, 14, and 15 instruction inputs. When in the arithmetic mode, the ALU results are also
affected by the carry, en. In the logic mode, the en input has no effect.
The matrix of Table 4 results when en and 10 through 15 are viewed together. Table 5 defines the logic
operations which the WS5901 can perform and Table 6 shows the arithmetic operations of the
device. Both carry-in HIGH (en = 1) and carry-in LOW (en = 0) are defined in these operations.
Octal
'543, '210
40
41
45
46
Group
Octal
Cn = H
Cn = L
'543'
AND
30
31
35
36
OR
60
61
65
66
EX-OR
70
7 1
75
76
EX-NOR
72
73
74
77
INVERT
62
63
64
67
32
33
34
37
Function
AIIO
AII8
DIIA
DIIO
AvO
Av8
DvA
DvO
AvO
Av8
DvA
DvO
AvO
Av8
DvA
DvO
0
B
Ii.
0
PASS
0
8
A
D
PASS
0
8
A
D
42
43
44
47
"ZERO"
50
51
55
56
MASK
'210
00
01
05
06
02
03
04
07
Group
ADD
Function
A+
A+
D+
D+
0
8
A
0
Group
ADD plus
one
22
23
24
17
0
8
A
D
0-1
Decrement 8-1
A-1
D-1
-0-1
1 's Compo -8-1
-A-1
-D-1
10
11
15
16
20
2 1
25
26
0-A-1
Subtract
8-A-1
Subtract
(1's Comp.) A- D-1 (2's Comp.)
0- D-1
A- 0-1
A- 8-1
D-A-1
D- 0-1
12
13
14
27
PASS
Increment
PASS
2'5 Compo
(Negate)
Function
A+
A+
D+
D+
0+
8+
A+
0+
1
1
1
1
0+1
8+1
A+1
D+1
0
8
A
D
-0
-8
-A
-D
O-A
8-A
A-D
O-D
A-O
A-8
D-A
D-O
Table 6. ALU Arithmetic Mode Functions.
0
0
0
0
AIIO
All 8
DIIA
OliO
Table 5. ALU Logic Mode Functions.
4-5
WS5901
WS5901C
COMMERCIAL RANGE AC
CHARACTERISTICS
CYCLE TIME AND CLOCK
CHARACTERISTICS
READ-MODIFY-WRITE (from select
of A, B registers to end of cycle)
Maximum Clock Frequency to Shift
0(50% duty cycle, 1= 432 or 632)
Minimum Clock Low Time
Minimum Clock High Time
Minimum Clock Period
The tables shown here specify the guaranteed
performance of the WS5901C over the Commercial
operating temperature range of ODC to +70DC and
a power supply range of 5V ± 5%. Inputs are
switching between 0 and 3V with rise and fall times
of 1 V/ns and measurements made at 1.5'1. All
outputs have maximum DC load.
31 ns
32MHz
15ns
15ns
31ns
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with C L = 5pF and
measured to O.5V change of output voltage.
From OE Low to Y output enable
From OE High to output disable
COMBINATIONAL PROPAGATION DELAYS (CL=
~
Y
F3
Cn+4
A, B ADDRESS
40
40
00-03
Cn
30
22
35
35
25
30
22
35
35
FROM
INPUT
OUTPUT
1012
1345
A BYPASSALU
(1= 2XX)
35
-
CLOCK
35
35
1678
50PF)
RAMO,
RAM3
00,
40
40
30
22
35
35
-
-
30
25
35
35
26
26
-
-
-
-
35
35
35
28
G, P
F=O
40
37
40
30
20
35
35
30
37
35
38
25
37
38
-
-
-
-
-
35
35
-
OVR
Q3
UNITS
-
-
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT
IN~P
A, B Source
Address
B Destination
Address
00-03
Cn
Set Up before H - L
15
Hold after H - l
Set Up before l - H
Hold after l - H
1 (Note3)
30(Note 4)
1
15
DO NOT CHANGE (Note 2)
1
-
-
0
0
0
-
25
20
1012
-
1345
-
1678
10
30
30
DO NOT CHANGE (Note 2)
-
-
RAMO,3and
00,3
NOTES:
4-6
12
UNITS
ns
0
0
0
1) Dashes indicate that a set-up time constraint or a propagation delay path does not exist.
2) The phrase "DO NOT CHANGE" indicates that certain Signals must remain low for the duration of the clock Low time.
Otherwise, erroneous operation may be the result.
3) Prior to clock H> L transition, source addresses must be stable to allow time for the source data to be set up before the
latch closes. After this transition the A address may be changed. If it is not being used as a destination, the B address
may also be changed. If it is being used as a destination, the B address must remain stable during the clock Low period.
4) Set-up time before H> L included here.
WS5901
CYCLE TIME AND CLOCK
CHARACTERISTICS
WS5901D
COMMERCIAL RANGE AC
CHARACTERISTICS
READ-MODIFY-WRITE (from select
of A, B registers to end of cycle)
Maximum Clock Frequency to Shift
Q (50% duty cycle, 1= 432 or 632)
Minimum Clock Low Time
Minimum Clock High Time
Minimum Clock Period
The tables shown here specify the guaranteed
performance of the WS5901D over the Commercial
operating temperature range of O°C to +70°C and
a power supply range of 5V ± 5%. Inputs are
switching between 0 and 3V with rise and fall times
of 1 Vlns and measurements made at 1.5V. All
outputs have maximum DC load.
23ns
43MHz
11ns
11ns
23ns
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with CL = 5pF and
measured to O.5V change of output voltage.
From OE Low to Y output enable
From OE High to output disable
COMBINATIONAL PROPAGATION DELAYS
(CL= 50PF)
~
Y
F3
Cn+4
G.p
A, B ADDRESS
30
30
30
28
30
00-03
Cn
21
17
26
26
16
20
17
25
24
-
20
14
24
24
20
24
24
24
19
25
26
-
-
-
A BYPASS ALU
(1= 2XX)
24
-
-
-
CLOCK
24
23
23
23
FROM
INPUT
OUTPUT
1012
1345
1678
-
RAMO.
RAM3
00.
30
30
-
21
16
24
24
-
-
22
18
25
26
21
21
-
-
-
-
24
24
24
19
OVR
F= 0
03
-
UNITS
ns
-
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT
I~P
A, B Source
Address
B Destination
Address
00-03
Cn
Set Up before H - L
Hold after H - L
Set Up before L - H
Hold after L - H
10
o(Note3)
21 (Note 4)
1
10
DO NOT CHANGE (Note 2)
1
-
-
-
-
0
0
1012
-
1345
-
19
19
DO NOT CHANGE (Note 2)
0
0
0
-
1
7
1678
RAMO,3and
00,3
NOTES:
-
16
13
9
UNITS
ns
1) Dashes indicate that a set-up time constraint or a propagation delay path does not exist.
2) The phrase "DO NOT CHANGE" indicates that certain signals must remain low for the duration of the clock Low time.
Otherwise, erroneous operation may be the result.
3) Prior to clock H> L tranSition, source addresses must be stable to allow time for the source data to be set up before the
latch closes. After this transition the A address may be changed. If it is not being used as a destination, the B address
may also be changed. If it is being used as a destination, the B address must remain stable during the clock Low period.
4) Set-up time before H> L included here.
4-7
WS5901
ORDERING INFORMATION
PART NUMBER
WS5901CP
WS5901DP
4-8
SPEED
C
0
PACKAGE
TYPE
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
40 Pin Plastic DIP, 0.6"
40 Pin Plastic DIP, 0.6"
P1
P1
Comm'l
Comm'l
Standard
Standard
FEE':E
--...,
._-------
-
~
r ..........
---~~
_
WS59016
WAFERSCALE INTEGRA nON, INC.
CMOS 16-81T HIGH-SPEED MICROPROCESSOR SLICE
KEY FEATURES
• Four CMOS 2901 Type Devices in a
Single Package
• On Board Look-Ahead Carry
Generator
-
31 ns Read-Modify-Write
• Fully Firmware Compatible with the
Bipolar Device Configuration of Four
29015 and One 2902A
• Low CMOS Power
-
• High Speed Operation
225 mW
GENERAL DESCRIPTION
The WS59016 is a 16-bit high-speed microprocessor which combines the functions of four 2901 4-bit slice processors
and distributed look-ahead carry generation on a single High Performance CMOS device.
This microprogram mabie circuit has the flexibility to efficiently emulate almost any digital computing machine. It is
an ideal candidate for such applications as peripheral controllers, CPUs, programmable microprocessors, and Digital
Signal Processors.
The advanced CMOS process, with which the WS59016 is manufactured, provides significant performance
improvements over an equivalent Bipolar device configuration. While operating faster than a 2901C based system,
the WS59016 requires less than 3% of the power consumed by an equivalent Bipolar system.
The WS59016 is also available as a macro cell in the WaferScale cell library. As such it can be combined with other
cells to build Application Specific Integrated Circuits.
FUNCTIONAL BLOCK DIAGRAM
CP----~--~r,m~~--.,
0
f-
~ f1
~----,
lU
c
2
III
8
ID
C
z
_o~
3
f-
"-~"/
fa:
4
~~
"8"
...
(READIWR,_IT:.::E:::)
=~~:jT-4Ft
ADDRESS,--
IU
:;)
10-1
"A" (READ)-----"
ADDRESS
ALU
SOURCE
z
0
ALU
FUNCTION
5
6
~ -7 OESTINATION
CONTROL
ti
:;)
a:
Iiiz
5a:
0
iii
8
OE--_~
A
OUTPUT DATA MUX
4-9
WS59016
PIN DESCRIPTION
Signal Name
I/O
Description
AO-3
I
Addresses which select the word of on board RAM which is to be displayed through the A port.
BO-3
I
Addresses which select the word of on board RAM which is to be displayed through the B port and into which
data is written when the clock is low.
10-8
I
Block of three instruction groups which are to select 1) which data sources will be applied to the ALU (1012),2)
what function the ALU will perform (1345), and 3) what data is to be written into the Q register or on board
RAM(1678).
Q15, RAM15
I/O
Signal paths at the MSB of the on-board RAM and the Q-register which are used for shifting data. When the
destination code on 1678 indicates an up shift (Octal 6 or 7) the three state outputs are enabled and the
MSB of the ALU output is available on the RAM 15 pin and the MSB of the Q-register is available on the Q15
pin. Otherwise, the pins appear as inputs.
When the destination code calls for a down shift, the pins are
used as the data inputs to the MSB of RAM (octal 4 and 5) and the Q register (octal 4).
Qo, RAMo
I/O
Shift lines similar to Q15 and RAM15, however the description is applied to the LSB of RAM and the Qregister.
00-015
I
These sixteen direct data inputs can be selected as a data source for the ALU. 00 is the LSB.
YO-Y15
0
These sixteen three state outputs, when enabled, display either the data on the A-port of the register stack or
the outputs of the ALU as determined by the destination code 1678.
OE
I
When high, the Y outputs are in the high impedance state. When low, either the contents of the A-register or
G, p-
O
The carry generate and propagate outputs of the ALU.
OVR
0
This signal indicates that an overflow into the sign bit has occurred as a result of a two's complement operation.
0
This output, when high, indicates the result of an ALU operation is zero.
0
The most significant ALU output bit.
the outputs of the ALU are displayed on YO-Y15, as determined by 1678.
F~
0
F15
Cn
Cn+ 16
CP
I
The carry-in to the ALU.
0
The carry-out of the ALU.
I
This clock signal is applied to theA and B-port latches. RAM, and Q-register. The clock low time is thewriteenable
to the on-board dual port RAM, including set-up time for the A and B-port registers. The A and B-port outputs
change while the clock is high. The Q-register is latched on the clock low-to-high transition.
PIN ORIENTATION
Dip
Chip Carrier
0,
03
D.
Os
D.
07
RAMo
I,
17
I.
V's
V,.
Cn +16
NC
TOP
4-10
A,
Ao
B3
B,
B,
Bo
Do
Vce
0,
0,
03
D.
Os
D.
07
RAMo
00
Is
I.
13
I,
"
10
Vo
V,
Cn
DE
V,
V3
V.
Vs
V.
A,
A3
015
014
0 '3
0"
0
"
0 '0
D.
0,
RAM,s
O,S
G
P
CP
I,
17
I.
F,s
OVR
Y,s
V,.
Cn+16
F=O
V'3
V"
V"
V,0
GND
V.
V,
V7
WS59016
ABSOLUTE MAXIMUM RATlNGS*
'Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Operating Temp (Comm'l) ........ O°C to + 70°C
(Mil) ........ -55°C to +125°C
Storage Temp. (No Bias) ...... -65°C to + 150°C
Voltage on Any Pin with
Respect to GND .............. -0.6V to +7V
Latch-Up Protection ................. >200 mA
ESD Protection .................... > ±2000V
DC READ CHARACTERISTICS Over Operating Temperature Range (Note 1)
PARAMETER
SYMBOL
TEST CONDITIONS
VOH
Output High Voltage
VOL
Output Low Voltage
= Min
= VIH or
Vee = Min
VIN = V IH or
Vee
VIN
All Outputs
V IL
All Outputs
V IL
MIN
10H
=
10L
= 12 mA Comm'l
= 8 mA Mil
10L
MAX UNITS
2.4
-3.4 mA
0.5
V IH
Input High Voltage
Guaranteed Input High Voltage
V IL
Input Low Voltage
Guaranteed Input Low Voltage
IIX
Input Load Current
Vee
=
Max, VIN
=
Gnd or Vee
-10
10
loz
High Impedance
Output Current
Vee
=
Max, Vo
=
Gnd or Vee
-50
50
lee
Power Supply Current Vee
NOTES: 1) Commercial: Vee
=
+5V ± 5%, TA
LOGIC FUNCTIONS FOR G,
The four signals G. P, Cn +16. and OVR are
designed to indicate carry and overflow conditions when the WS59Q16 is in the add or subtract
mode. The table below indicates the logic
equations for these four signals for each of the
eight ALU functions. The Rand S inputs are the
two inputs selected according to Table 1.
= Max
=
2.0
0.8
Comm'l (O°C to +70°C)
45
Mil (-55°C to + 125°C)
60
Doe to 7Doe.
V
2) Military: Vee
= +5V
± 1D%, TA
J.1A
mA
= -55°e to +125°e.
P, C n + 16, and OVR
Definitions
+
P,
~
R,
G,
~
R,·S,
PO·3~
P4'Y~
P B· l l
S,
P O,p , .P"P 3
P 4 'P 5,P S'P y
~ PB'P9'PlO'P"
P12-15 =
GO·3~
G 3 + P 3·G,+ P 3·P,·G , + P3·P,·P , ·G O
G7+ py·G s + p y·P S·G 5 + P Y'P S,P 5 'G 4
G B·l l ~ G " + P,, 'GlO + P, 1"PlO ·G 9 + P",P,0,P9·GB
G12"5~ G '5 + P15 ·G,4 + P15,P14·G,3 + P15,P14,P,3·G12
G4'7~
P12'P'3'P14'P'5
C n + 15 = G 12 -14 + P12-14,G B-11 + P12-14,Pa-l"G 4 -7 + P'2-14,PB-l1,P4-7,G O-3
P 12 " 4 ~ P12'P13,P,4
G12"4~ G'4 + P14 ·G,3 + P14·P,3·G12
1543
G
P
Function
G'2-15
0
R+S
1
S-R
2
R-S
3
RVS
LOW
4
RIIS
LOW
PO-3,P4-7 ·Pa-l1 'P'2-15
.
.
p·e, + G
Ri
OVR
en + lS(±)C n + 16
•
•
for R i in definitions
LOW
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
LOW
HIGH
LOW
LOW
HIGH
G'2-1S+
G 8 -1 ,+ G 4 _7
+ G O-3
Same as R II S except substitute
R for R in definition
LOW
6
R(±)S
PO-3 . P4-7' Pe-l"
7
R(±)S
Same as R(±)S except
Substitute R for R in
Definitions
+
16
Same as R + S Equations except substitute S for S in definitions
RIIS
1)
+ P'2-1S'G a-1,+
~2'15·P8-11·P4'7·GO.3
Same as R + S Equations except substitute
5
Note:
+
C n+
P'2.1s· P a.l1,G 4.7
P'2.15
OR
4-11
WS59016
FUNCTIONAL TABLES
Mnemonic
AO
AB
ZO
ZB
ZA
DA
DO
DZ
ALU SOURCE
OPERANDS
MICROCODE
MICROCODE
Mnemonic
Octal
12 11 I o Code
R
S
L
L
L
L
H
H
H
H
A
A
0
0
0
D
D
D
0
B
0
B
A
A
0
0
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
ADD
SUBR
SUBS
OR
AND
NOTRS
EXOR
EXNOR
Table 1 : ALU Source Operand Control.
RAM
FUNCTION
MICROCODE
Mnemonic
NOP
RAMA
RAMF
Octal
Is 17 16 Code
L L L
0
1
L L H
L H L
2
L H H
3
RAMOD
RAMD
RAMOU
H L L
H L H
H H L
4
5
RAMU
H H H
7
OREG
6
a-REG.
FUNCTION
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
YOUTPUT
LOAD
SHIFT
LOAD
X
NONE
NONE
F-O
X
NONE
NONE
NONE
F-B
F-B
DOWN
SYMBOL
0
1
2
3
4
5
R Plus S
S Minus R
R Minus S
RORS
RAND S
RAND S
R EXORS
R EX-NORS
R+ S
S- R
R-S
RvS
RIIS
RIIS
RVS
6
7
FfV'"S'
Table 2. ALU Function Control.
SHIFT
DOWN
UP
UP
ALU
Function
Octal
15 14 13 Code
NONE
X
X
NONE
NONE
X
F/2-B DOWN 0/2-0
NONE
X
F/2-B
2F-B
20-0
UP
X
NONE
2F-B
RAM
SHIFTER
a SHIFTER
RAMo RAM15
ao
a15
F
X
X
X
X
F
A
F
X
X
X
X
X
X
X
X
X
X
F
F
F
F
Fo
Fo
IN15
IN15
F15
F 15
00
IN15
X
INo
INo
00
INo
X
X
X
015
0 15
x=
Don't care.
B = Register Addressed by B inputs.
DOWN is toward LSB. UP is toward MSB.
Table 3. ALU Destination Control.
1
2
A,a
A, B
o,a
A+ 0
A+ B
0
1543
(Octal Code)
0
1
2
3
4
5
6
7
ALU
Function
Cn = L
R Plus S
Cn = H
A+ 0+ 1 A+ B+ 1
1210 (Octal Code)
4
3
ALU Source (R, S)
O,B
O,A
7
D,A
D,a
D,O
D+A
D+ 0
D
0
B
A
0+1
B+ 1
A+1
D+ A+ 1 D+ 0+ 1
D+1
Cn = L
S Minus R
Cn = H
0-A-1
B-A-1
0-1
B-1
A-1
A- D-1
0- D-1
-D-1
O-A
B-A
0
B
A
A-D
O-D
-D
Cn = L
R Minus S
Cn = H
A-0-1
A-B-1
-0-1
- B-1
-A-1
D-A-1
D-0-1
D-1
A-O
A-B
-0
-B
-A
D-A
D-O
D
AvO
AIIO
AIIO
AvO
AvB
A
0
A
DvA
DIIA
iJllA
DvO
DvO
D
0
0
D
DvO
i5
RORS
RAND S
RANDS
REX-OR S
REX-NORS
AIIB
AIIB
AvB
0
0
0
0
B
0
B
B
DvA
A
A
AvB
I5VA
0
B
+ - Plus; - - Minus; v - OR; A - AND; v - EX·OR.
Table 4. Source Operand and ALU Function Matrix.
4-12
I
6
5
AVO
DIIO
DIIO
WS59016
SOURCE OPERANDS AND ALU FUNCTIONS
Eight source operand pairs are available to the ALU as determined by the 10,11 and 12 instruction inputs. The ALU
performs eight functions; three arithmetic and five logic. This function selection is controlled by the 13, 14 and 15
instruction inputs. When in the arithmetic mode, the ALU results are also affected by the carry, en. In the logic
mode, the en input has no effect.
The matrix of Table 4 results when en and 10th rough 15 are viewed together. Table 5 defines the logic operations
which the WS59016 can perform and Table 6 shows the arithmetic operations of the device. Both carry-in HIGH
(en = 1) and carry-in LOW (eN = 0) are defined in these operations.
Octal
'543,1 210
Group
Function
Octal
Cn
=
L
Cn
=
H
'543'
40
41
45
46
AND
30
31
35
36
OR
60
6 1
65
66
EX-OR
70
7 1
75
76
EX-NOR
72
73
74
77
INVERT
62
63
64
67
PASS
Q
8
A
0
32
33
34
37
PASS
Q
8
A
0
42
43
44
47
"ZERO"
50
51
55
56
MASK
AAQ
AA8
OA A
OAQ
AvQ
Av8
OvA
OvQ
AvQ
Av8
OvA
OvQ
AvQ
Av8
OvA
OvQ
Q
B
A
0
1210
00
01
05
06
02
03
04
07
1
1
1
2
2
3
4
7
22
23
24
17
10
1 1
15
16
20
2 1
25
26
Group
ADD
PASS
Decrement
1'5 Compo
Function
A+
A+
0+
D+
Q
8
A
Q
Q
8
A
D
Q-1
8- 1
A-1
D-1
-Q-1
-8- 1
-A-l
-D - 1
Group
ADD plus
one
Increment
PASS
2's Compo
(Negate)
Q-A-l
Subtract
8-A-1
Subtract
(1'5 Comp.) A- D-l (2's Comp.)
Q- 0-1
A-Q-l
A-8-1
0-A-1
0-Q-1
Function
A+
A+
D+
0+
Q+
8+
A+
Q+
1
1
1
1
Q+1
8+ 1
A+ 1
D+l
Q
8
A
0
-Q
-8
-A
-0
Q-A
8-A
A-O
Q-O
A-Q
A-8
O-A
O-Q
Table 6. ALU Arithmetic Mode Functions.
0
0
0
0
AAQ
AA8
BAA
DAQ
Table 5. ALU Logic Mode Functions.
4-13
WS59016
COMPETITIVE TIMING ANAL YS/S
The following analysis compares the critical timing paths of a WS59016D vs. the equivalent Bipolar circuit
implementation using four 2901 C's and one 2902A.
As can be seen from this comparison. the WS59016 operates faster than even the theoretically achievable values
of the Bipolar implementation. The actual values for the Bipolar circuit will be lengthened by the layout
dependent interconnect delays between the individual devices. When these delays are taken into account. the
WS59016 speed advantage becomes even greater.
TIMI NG COMPARISON
WS59016D vs 2901C w/2902A (Comm'l)
DATA PATH
2901 C
wi 2902A
A. B Address
• j5 or G = 37ns
is or G
• C = 9ns
C
• F= 0, RAMo.15= 25ns
interconnect delay
•
Xns
Total Delay
• > 71 ns
590160
CONTROL PATH
2901 C
wi 2902A
1012
• PorG=37ns
• C= 9ns
C
• F = 0, RAMo.15 = 25ns
interconnect delay
•
Xns
.. > 71 ns
Total Delay
is orG
590160
A, B Address-F = 0, RAM o.15 = 46n5
interconnect delay
•
Ons
Total Delay
• < 46 ns
1012
• F= O. RAM o•15 = 41ns
interconnect delay
•
Ons
Total Delay
• ~ 41 ns
TIMING COMPARISON
WS59016D vs 2901C w/2902A (Military)
DATA PATH
2901 C
wI 2902A
• j5 or G = 44ns
A, B Address
is orG
• C = 11.5ns
C
• F= 0, RAM o.15 = 28ns
Xns
interconnect delay
•
Total Delay
• > 83.5ns
590160
A, B Address- F15, RAM O•15 = 56ns
interconnect delay
Ons
•
Total Delay
• < 56ns
CONTROL PATH
2901 C
wI 2902A
• is or G
= 44ns
• C= 11.5ns
• F= 0, RAMo.15= 28ns
C
III
= Xns
interconnect delay
Total Delay
• > 83.5ns
1012
is or G
590160
• F15, RAMo.15 = 49ns
1012
interconnect delay
Ons
•
<
49ns
Total Delay
•
---
NOTE: This competi1ive analysis holds true for any 16 bit system which performs arithmetic operations. If arithmetic operations are
not used, the Bipolar circuit can run faster than noted above.
4-14
WS59016
COMMERCIAL RANGE AC
CHARACTERISTICS
(WS59016C)
CYCLE TIME AND CLOCK
CHARACTERISTICS
READ-MODIFY-WRITE (from select
of A, B registers to end of cycle)
Maximum Clock Frequency to Shift
Q (50% duty cycle, 1= 432 or 632)
Minimum Clock Low Time
Minimum Clock High Time
Minimum Clock Period
The tables shown here specify the guaranteed
performance of the WS59016C over the Commercial
operating temperature range of O°C to +70oC and
a power supply range of 5V ± 5%. Inputs are
switching between 0 and 3V with rise and fall times
of 1 V/ns and measurements made at 1.5V. All
outputs have maximum DC load.
67ns
15MHz
33ns
33ns
67ns
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with CL = 5pF and
measured to O.5V change of output voltage.
From dE Low to Y output enable
From OE High to output disable
COMBINATIONAL PROPAGATION DELAYS
(CL= 50PF)
~
Y
F15
C n +16
G, P
F=O
OVR
RAMO,
RAM15
Q15
A, B ADDRESS
69
69
60
68
71
69
71
-
DO-D15
Cn
55
38
60
60
55
38
60
60
45
27
55
55
50
55
38
60
60
55
42
60
60
-
55
55
55
42
60
60
-
FROM
OUTPUT
OUTPUT
1012
1345
-
00,
-
1678
A BYPASS ALU
(1= 2XX)
30
-
-
-
-
-
27
26
45
-
-
-
-
-
-
-
CLOCK
65
65
65
65
55
65
70
30
IN~
Set Up before H - L
Hold after H - L
A, B Source
Address
B Destination
Address
00-015
15
2 (Note 3)
-
-
Cn
-
-
1012
1345
-
-
-
IS78
RAMO, 15 and
00,15
NOTES:
15
15
-
Set Up before L - H
65 (Note 4)
DO NOT CHANGE (Note 2)
50
34
55
55
DO NOT CHANGE (Note 2)
-
-
20
UNITS
Hold after L - H
ns
UNITS
1
1
0
0
ns
0
0
0
4
1) Dashes indicate that a set· up time constraint or a propagation delay path does not exist.
2) The phrase "DO NOT CHANGE" Indicates that certain signals must remain low for the duration of the clock Low time.
Otherwise, erroneous operation may be the result.
3) Prior to clock H> L transition, source addresses must be stable to allow time for the source data to be set up before
the latch closes. After this transition the A address may be changed. If it is not being used as a destination, the B
address may also be changed. If it Is being used as a destination, the B address must remain stable during the clock
Low period.
4) Set·up time before H> L included here.
4-15
WS59016
CYCLE TIME AND CLOCK
CHARACTERISTICS
MILITARY RANGE AC
CHARACTERISTICS
(WS59016C)
READ-MODIFY-WRITE (from select
of A, B registers to end of cycle)
Maximum Clock Frequency to Shift
Q (50% duty cycle, 1= 432 or 632)
Minimum Clock Low Time
Minimum Clock High Time
Minimum Clock Period
The tables shown here specify the guaranteed
performance of the WS59016C over the Military
operating temperature range of -55°C to +125°C
and a power supply range of 5V ± 10%. Inputs are
switching between 0 and 3V with rise and fall times
of 1 V/ns and measurements made at 1.5\1. All
outputs have maximum DC load.
80ns
12.5MHz
39ns
39ns
BOns
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with Cl = SpF and
measured to O.SV change of output voltage.
From DE Low to Y output enable
From OE High to output disable
COMBINATIONAL PROPAGATION DELAYS (Cl=
SOPF)
~
Y
F15
C n +16
G,P
F=O
OVR
RAMO,
RAM15
Q15
A, BADDRESS
83
83
72
82
83
83
83
-
00-015
Cn
66
46
72
72
36
66
46
72
72
-
54
33
66
66
-
60
66
66
66
53
72
72
66
46
72
72
66
53
72
72
-
-
-
-
31
31
55
-
-
-
-
-
-
-
78
78
78
78
66
78
78
36
FROM
OUTPUT
OUTPUT
1012
1345
1678
A BYPASSALU
(1= 2XX)
CLOCK
-
00,
UNITS
ns
SET· UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT
I~P
A, B Source
Address
B Destination
Address
00-015
Cn
1012
1345
1678
RAMO, 15 and
00,15
NOTES:
4-16
Set Up before H - L
Hold after H - L
Set Up before L - H
Hold after L - H
20
2 (Note 3)
78 (Note 4)
2
20
20
-
DO NOT CHANGE (Note 2)
2
-
0
0
0
60
41
66
66
DO NOT CHANGE (Note 2)
-
25
UNITS
ns
0
0
5
1) Dashes indicate that a set·up time constraint or a propagation delay path does not exist.
2) The phrase "DO NOT CHANGE" indicates that certain Signals must remain low for the duration of the clock low time.
Otherwise, erroneous operation may be the result.
3) Prior to clock H> l tranSition, source addresses must be stable to allow time forthe source data to be set up before the
latch closes. After this transition the A address may be changed. If it is not being used as a destination, the B address
may also be changed. If it is being used as a destination, the B address must remain stable during the clock low period.
4) Sel·up lime before H> l included here.
WS59016
CYCLE TIME AND CLOCK
CHARACTERISTICS
COMMERCIAL RANGE AC
CHARACTERISTICS
(WS59016D)
READ-MODIFY·WRITE (from select)
of A, B registers to end of cycle)
The tables shown here specify the guaranteed
performance of the WS59016D over the Commercial
operating temperature range of OOC to +70oC and
a power supply range of 5V ± 5%. Inputs are
switching between 0 and 3V with rise and fall times
of 1 V/ns and measurements made at 1.5V. All
outputs have maximum DC load.
Maximum Clock Frequency to Shift
a (50% duty cycle, 1=432 or 632)
31 ns
32 MHz
Minimum Clock Low Time
14 ns
Minimum Clock High Time
14 ns
Minimum Clock Period
40 ns
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with CL = 5pF and
measured to O.5V change of output voltage.
From OE Low to Y output enable
From OE High to output disable
COMBINATION PROPAGATION DELAYS (CL=50PF)
~
Y
F15
Cn +16
G,P
F=O
OVR
RAMO
RAM15
QO
Q15
A, BADDRESS
46
46
44
43
46
46
44
-
FROM
OUTPUT
OUTPUT
00-015
36
32
34
32
36
34
36
-
Cn
32
29
24
-
32
28
32
1012
39
39
37
38
39
38
41
-
1345
39
38
37
37
39
38
41
-
-
-
-
34
34
-
-
-
-
-
-
38
34
38
38
38
38
1678
28
A BYPASSALU
(1=2XX)
34
-
CLOCK
38
37
UNITS
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT
IN~P
Set Up before H - L
A, B, Source
Address
12
B Destination
Address
12
Hold after H - L Set Up before L- H Hold after L- H
o(Note 3)
DO NOT CHANGE (Note 2)
1012
-
1345
-
-
1678
12
RAMO, 15 and
00,15
-
00-015
Cn
NOTES:
23 (Note 4)
-
1
1
19
0
-
16
0
-
22
0
22
0
DO NOT CHANGE (Note 2)
-
17
UNITS
ns
0
3
1) Dashes indicate that a set·up time constraint or a propagation delay path does not exist.
2) The phrase "DO NOT CHANGE" indicates that certain signals must remain low for the duration of the clock Low time.
Otherwise, erroneous operation may be the result.
3) Prior to clock H> L tranSition, source addresses must be stable to allow time for the source data to be set up before
the latch closes. After this transition the A address may be changed. If it is not being used as a destination, the B
address may also be changed. If It is being used as a destination, the B address must remain stable during the clock
Low period.
4) Set·up time before H> L included here.
4-17
WS59016
MILITARY RANGE AC
CHARACTERISTICS
(WS59016D)
CYCLE TIME AND CLOCK
CHARACTERISTICS
READ·MODIFY-WRITE (from select)
of A, B registers to end of cycle)
The tables shown here specify the guaranteed
performance of the WS59016D over the Military
operating temperature range of -55°C to +125°C
and a power supply range of 5V ± 10%. Inputs are
switching between 0 and 3V with rise and fall times
of 1 V/ns and measurements made at 1.5V. All
outputs have maximum DC load.
Maximum Clock Frequency to Shift
36 ns
a (50% duty cycle, I = 432 or 632)
27 MHz
Minimum Clock Low Time
17 ns
Minimum Clock High Time
17 ns
Minimum Clock Period
47 ns
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with C L = SpF and
measured to O.SV change of output voltage.
From OE Low to Y output enable
From OE High to output disable
COMBINA TlON PROPAGA TlON DELA YS
~
(CL = 50PF)
Y
F15
C n +16
G,P
F=O
OVR
RAMO
RAM15
QO
Q15
A, BADDRESS
56
56
53
52
56
56
53
-
00·015
43
39
42
39
43
42
43
-
Cn
39
36
30
-
39
34
39
1012
48
48
46
47
48
47
49
1345
48
47
46
46
48
47
49
-
1678
34
-
-
-
-
-
42
A BYPASSALU
(1=2XX)
42
-
-
-
-
-
-
CLOCK
47
FROM
OUTPUT
OUTPUT
47
42
47
47
ns
--
42
--
---
46
UNITS
47
47
SET·UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT
I~
Set Up before H - L
A, B, Source
Address
16
B Destination
Address
16
Hold after H - L Set Up before L- H Hold after L - H
o (Note 3)
29 (Note 4)
DO NOT CHANGE (Note 2)
2
2
00·015
-
-
23
0
en
-
-
20
0
1012
-
-
27
0
1345
-
-
27
0
1678.
16
RAMO, 15 and
00,15
-
NOTES:
4·18
DO NOT CHANGE (Note 2)
-
21
UNITS
ns
0
4
1) Dashes mdlcate that a set-up time constraint or a propagatIOn delay path does not eXIst.
2) The phrase "DO NOT CHANGE" indicates that certain signals must remain low for the duration of the clock Low time.
Otherwise, erroneous operation may be the result.
3) Prior to clock H> L transition, source addresses must be stable to allow time for the source data to be set up before
the latch closes. After this transition the A address may be changed. If it is not being used as a destination, the B
address may also· be changed. If it is being used as a destination, the B address must remain stable during the clock
Low period_
4) Set-up time before H> L included here.
WS59016
ORDERING INFORMATION
PART NUMBER
SPEED
WS59016CB
C
WS59016CBMB
C
WS59016CJ
WS59016CL
WS59016CLMB
WS59016DB
C
C
C
D
WS59016DBMB
D
WS59016DJ
D
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
Sidebrazed
B1
Comm'l
Standard
Sidebrazed
B1
Military
MIL-STD-883C
J1
Standard
Standard
MIL-STD-883C
Standard
PACKAGE
TYPE
64 Pin Ceramic
DIP, 0.9"
64 Pin Ceramic
DIP, 0.9"
68 Pin PLDCC
68 Pin CLDCC
68 Pin CLDCC
64 Pin Ceramic
DIP, 0.9"
64 Pin Ceramic
DIP, 0.9"
68 Pin PLDCC
Sidebrazed
L1
B1
Comm'l
Comm'l
Military
Comm'l
Sidebrazed
B1
Military
MIL-STD-883C
J1
Comm'l
Standard
L1
4-19
4-20
='====
~~
~ == == ==-, .l1li ~ . . 1:=
_=_ii.!!!,,=,~;g
WS59032
== _______________
_
WAFERSCALE INTEGRA170N, INC
CMOS 32-81T HIGH-SPEED MICROPROCESSOR SLICE
KEY FEATURES
• Eight CMOS 2901 Type Devices in a
Single Package
• 32 x 32 Dual Port RAM
• Low CMOS Power
-
350 mW
• High Speed Operation
-
23 MHz Read-Modify-Write Cycle
• Fully Firmware Compatible
with the 2901
• On Board Carry Look-Ahead
GENERAL DESCRIPTION
The WS59032 is a 32-bit High-Speed microprocessor which combines the functions of eight 2901 4-bit slice processors and distributed look-ahead carry generation on a single High Performance CMOS device. The WS59032 dual
port RAM is 32-bits wide and 32 words deep. This architecture provides greater flexibility and eases the task of
generating new microcode while maintaining 100% compatible with existing 2901 based microcode.
This microprogram mabie circuit has the flexibility to efficiently emulate almost any digital computing machine. It is
an ideal candidate for such applications as peripheral controllers, CPUs, programmable microprocessors, and Digital
Signal Processors.
The advanced CMOS process, with which the WS59032 is manufactured, provides significant performance im·
provements over an equivalent Bipolar device configuration. While operating faster than a 2901C based system, the
WS59032 requires less than 3% of the power consumed by an equivalent Bipolar system.
The WS59032 is also available as a macro cell in the WaferScale cell library. As such it can be combined with other
cells to build Application Specific Integrated Circuits.
FUNCTIONAL BLOCK DIAGRAM
cp-----{==::~fiE:-1t:~--,~---,
0
~ -1
cw
2
0
CJ
U)
z
til
c
z
3
_o~ '- a:~rv" -4
a!:
"B"'
(READ/WR,~~IT..:E~)=::::::!~:::::lFt-Tr
ADDRESS,...
w
:::>
fD
"p,:' (READ)-----"
ADDRESS
AW
SOURCE
0
AW
FUNCTION
~
:::>
a:
5
ztil
6
:iii
15
a:
~ ff7
CJ
DESTINATION
CONTROL
~::~~::::::~~~~-r~==~~~~F~=~O~==~::~
C'N----+-+-..
8·FUNCTION 32·BIT AW
F31
OVR
Cn + 32
8
OE----I~
A
OUTPUT DATA MUX
4-21
4
WS59032
PIN DESCRIPTION
Signal Name
I/O
Description
AO-4
I
Addresses which select the word of on board RAM which is to be displayed through the A port.
80-4
I
Addresses which select the word of on board RAM which is to be displayed through the B port and into which
data is written when the clock is low.
10-8
I
Block of three instruction groups which are to select 1) which data sources will be applied to the ALU (1012), 2)
what function the ALU will perform (1345), and 3) what data is to be written into the a register or on board
RAM(1678).
a31,RAM31
I/O
Signal paths at the MSB of the on-board RAM and the a-register which are used for shifting data. When the
destination code on 1678 indicates an up shift (Octal 6 or 7) the three state outputs are enabled and the
MSB of the ALU output is available on the RAM 31 pin and the MSB of the a-register is available on the 0 31,
pin. Otherwise, the pins appear as inputs.
When the destination code calls for a down shift, the pins are
used as the data inputs to the MSB of RAM (octal 4 and 5) and the 0 register (octal 4).
ao, RAMO
I/O
Shift lines similar to 031 and RAM31. however the description is applied to the LSB of RAM and the aregister.
00- 031
I
These thirty two direct data inputs can be selected as a data sou rce for the ALU. DO is the LSB.
YO-Y31
0
These thirty two three state outputs, when enabled, display either the data on the A-port of the register stack
or the outputs of the ALU as determined by the destination code 1678.
OE
I
When high. the Y outputs are in the high impedance state. When low, either the contents of the A-register or
0
This signal indicates that an overflow into the sign bit has occurred as a result of a two's complement operation.
the outputs of the ALU are displayed on YO-Y31. as determined by 1678.
OVR
F=O
0
This output, when high, indicates the result of an ALU operation is zero.
F31
0
The most significant ALU output bit.
Cn
I
The carry-in to the ALU.
Cn+32
0
The carry-out of the ALU.
CP
I
This clock signal is applied to the A and B-port latches, RAM, and a-register. The clock low time is thewrite enable
to the on-board dual port RAM, including set-up time for the A and B-port registers. The A and B-port outputs
change while the clock is high. The a-register is latched on the clock low-to-high transition.
PIN DESIGNATOR
PIN
NAME
VCC
VCC
GNO
GNO
GNO
GNO
RAMO
RAM31
00
031
ClK
CIN
CN+32
OVR
F=O
F31
OEN
AO
A1
A2
A3
A4
BO
B1
B2
4-22
PGA
GRID #
N1
A1
N7
G13
A12
C6
M7
B6
L7
A6
A7
N13
A9
C8
C13
B8
M12
J1
J2
K1
K2
L1
M1
L2
M2
PIN
NAME
B3
B4
00
01
02
03
04
05
06
07
08
09
010
011
012
013
014
015
016
017
018
019
020
021
022
PGA
GRID#
N2
M3
N6
M6
L6
N5
M5
N4
M4
N3
H3
H2
H1
G1
G3
G2
F1
F2
F3
E1
E2
01
02
C1
C2
PIN
NAME
023
024
025
026
027
028
029
030
031
10
11
12
13
14
15
16
17
18
YO
Y1
Y2
Y3
Y4
Y5
Y6
PGA
GRID#
PIN
NAME
PGA
GRID#
B1
B2
B3
A2
A3
B4
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
Y21
Y22
Y23
Y24
Y25
Y26
Y27
Y28
Y29
Y30
Y31
K12
K13
J12
J13
H11
H12
H13
G12
G11
F13
F12
F11
E13
E12
013
012
B13
C12
A13
B12
B11
A11
B10
A10
B9
A4
B5
A5
N8
M8
L8
N9
M9
N10
A8
B7
C7
M10
N11
N12
M11
M13
l12
L13
i
WS59032
ABSOLUTE MAXIMUM RATINGS·
"Notice: Stresses above those listed here may
cause permanent damage to the device. This is a
stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect device reliability.
Operating Temp (Comm'I) ...... O°C to +70°C
(Mil) ...... -55°C to + 125°C
Storage Temp. (No bias) ... -65°C to + 150°C
Voltage on any pin with
respect to GND ............... -O.6V to + 7V
Latch Up Protection ............... >200 mA
ESD Protection .................. > ±2000V
DC CHARACTERISTICS
SYMBOL
Over Operating Temperature Range (Note 1)
MIN
TEST CONDITIONS
PARAMETER
Vcc = Min.
Vin = Vih or Vii
Voh
Output High Voltage
Vol
Output Low Voltage
Vih
Vii
Input High Voltage
Input Low Voltage
lol=12mA Com'l
YO-Y31
Vcc= Min
lol=9mA Mil
Vin = Vih or Vii
lol-SmA
All others
Guaranteed Input High Voltage
Guaranteed Input Low Voltage
I ix
Input Load Current
Vcc - Max, Vin - Gnd or Vcc
loz
High Impedance
Output Cu rrent
Vcc = Max, Vo = Gnd or Vcc
Icc
Power Supply Current
Vcc = Max
NOTES: 1) Commercial: Vee = +5V ± 5%, TA
2) Military: Vee
=
+5V ± 10%, TA
=
All outputs
loh = -1.6mA
MAX
UNITS
0.5
V
2.4
2.0
O.S
-10
10
-50
50
Comm'l (OOC to + 70°C)
!LA
70
85
Mil (-55°C to +125°C)
mA
= O°C to 70°C.
-55°C to +125°C.
PACKAGE ORIENTATION
101 PIN PGA PACKAGE
2
3
4
5
6
7
8
9
10
11
12
13
N
M
+
+
+
+
+
+
+
+
+
+
+
+
+
N
L
K
J
H
G
F
E
0
B
A
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + + + + + + + + +
+ + + + + + + + + +
+ + +
+ +
+
+
+
+ +
+
+ +
+
+ +
+
+
+ + +
+
+ + + + + + + + + +
+ + + + + + + + + +
+
+
+
+
+
+
+
+
+
+
+
+
+
M
L
A
K
J
H
G
F
E
0
C
C
TOP VIEW
B
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
E
A
B
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ + + + + + + + + + +
+ + + + + + + + + + +
+
+ + +
+ +
+ +
+ +
+
+ + +
+
+ + +
+
+ + +
+ +
+ +
+ + +
+ +
-+ + + + + + + + + + +
+ + + + + + + + + + +
A
B
C
C
0
0
E
F
F
G
G
H
H
J
J
K
K
L
L
M
M
N
2
3
4
5
6
7
8
9
10
11
12
13
N
BOTTOM VIEW
(THROUGH PACKAGE VIEW)
4-23
WS59032
FUNCTIONAL TABLES
ALU SOURCE
OPERANDS
MICRO CODE
Mnemonic
AO
AB
ZO
ZB
ZA
OA
DO
DZ
Octal
12 11 10 Code
R
S
L
L
L
L
H
H
H
H
A
A
0
0
0
D
D
0
0
B
0
B
A
A
0
0
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
MICRO CODE
Mnemonic
ADD
SUBR
SUBS
OR
AND
NOTRS
EXOR
EXNOR
OREG
NOP
RAMA
RAMF
RAMOO
RAM
FUNCTION
MICRO CODE
Octal
18 17 16 Code
L L L
0
1
L L H
L
L
H L
H H
2
3
L
H
4
5
6
7
RAMD
H L
H L
RAMOU
H H L
RAMU
H H H
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
0
1
2
3
4
5
6
7
ALU
Function
SYMBOL
R Plus S
S Minus R
R Minus S
R OR S
RAND S
RAND S
R EXOR S
R EX· NOR S
R+ S
S- R
R-S
RvS
RIIS
RIIS
RVS
R"VS
Table 2. ALU Function Control.
Table 1 : ALU Source Operand Control.
Mnemonic
Octal
15 14 13 Code
a-REG.
FUNCTION
Y OUTPUT
RAM
SHIFTER
a SHIFTER
SHIFT
LOAD
SHIFT
LOAD
RAMo
RAM15
ao
X
NONE
NONE
F-O
F
X
X
X
X
X
NONE
F-B
F-B
X
NONE
F
X
X
X
X
X
X
NONE
NONE
A
F
X
X
X
X
X
X
X
X
F/2-B DOWN 0/2-0
NONE
F/2-B
X
F
Fa
Fo
IN15
00
2F-B
UP
20-0
F
INa
00
INa
IN15
X
UP
IN15
F15
UP
2F-B
X
NONE
F
INa
F 15
X
NONE
NONE
DOWN
DOWN
F
a 15
0 15
0 15
x - Don t care.
B ~ Register Addressed by B inputs.
DOWN is toward LSB. UP is toward MSB.
Table 3. ALU Destination Control.
1210 (Octal Code)
1
0
1543
(Octal Code)
ALU
Function
0
Cn = L
R Plus S
Cn = H
1
2
3
4
5
6
7
+
~
Plus; -
2
3
5
6
7
D,A
D. a
D,O
D+ A
D t 0
D
4
ALU Source (R, S)
0, B
O.A
A.a
A, B
O. a
AtO
A+ B
0
B
A
0+1
B+ 1
A+1
D + A+ 1 0+ 0+ 1
A+ 0+ 1 A+ B+ 1
Cn = L
S Minus R
Cn = H
0-A-1
B-A-1
0-1
B-1
A-1
A-D-1
0- D-1
- D- 1
O-A
B-A
0
B
A
A-D
O-D
-D
Cn = L
R Minus S
Cn = H
A- 0-1
A- B-1
- 0-1
- B-1
-A-1
0-A-1
D - 0-1
0-1
A-O
A-B
-0
-B
-A
D-A
0-0
0
0
0
0
B
0
B
A
DvA
OvO
0
A
OllA
D
0
DIIA
DIIO
OliO
0
B
A
DvA
DvO
D
B
A
DVA
OvO
0
ROR S
AvO
AvB
RAND S
RAND S
AIIO
AIIO
AIIB
REX-OR S
AVO
AIIB
AvB
REX-NORS
Ava
AvB
~
Monus; v
~
OR;
A ~
AND; v
~
0
EX-OR.
Table 4. Source Operand and ALU Function Matrix.
4-24
D+ 1
0
WS59032
SOURCE OPERANDS AND ALU FUNCTIONS
Eight source operand pairs are available to the ALU as determined by the 10, 11, and 12 instruction
inputs. The ALU performs eight functions; three arithmetic and five logic. This function selection is
controlled by the 13, 14, and 15 instruction inputs. When in the arithmetic mode, the ALU results are also
affected by the carry, en. In the logic mode, the en input has no effect.
The matrix of Table 4 results when en and 10 through 15 are viewed together. Table 5 defines the logic
operations which the WS59032 can perform and Table 6 shows the arithmetic operations of the
device. Both carry-in HIGH (en
1) and carry-in LOW (en 0) are defined in these operations.
=
=
Octal
Group
Function
40
4 1
45
46
AND
AAQ
AAB
DAA
DAQ
30
31
35
36
OR
60
6 1
65
66
EX-OR
70
7 1
75
76
EX-NOR
72
73
74
77
INVERT
62
63
64
67
PASS
Q
B
A
D
32
33
34
37
PASS
Q
B
A
D
42
43
44
47
"ZERO"
50
5 1
55
56
MASK
1543,1210
AvQ
AvB
DvA
DvQ
AvQ
A-vB
DvA
DvQ
AvQ
AvB
DvA
DvQ
Q
B
A
B
Octal
1543 ,
1210
00
o1
05
06
02
03
04
07
Cn
Group
ADD
=L
Cn
Function
Group
Function
At-Q
A f B
D+A
DtQ
ADD plus
one
A+Q+1
A+ B+ 1
D + A+ 1
D+ Q +1
22
23
24
17
Q
B
A
D
Q-1
B-1
Decrement
A-1
D-1
-Q- 1
1'5 Compo -B - 1
-A-1
-D-1
10
11
15
16
20
21
25
26
Q-A-1
Subtract
B-A-1
Subtract
(1'5 Comp.) A- D-1 (2's Comp.)
Q- D-1
A- Q-1
A- B-1
D-A-1
D- Q-1
12
13
14
27
PASS
=H
Increment
PASS
2'5 Compo
(Negate)
Q+1
9+ 1
A+ 1
D+1
Q
B
A
D
-Q
-B
-A
-D
Q-A
B-A
A-D
Q-D
A-Q
A-B
D-A
D-Q
Table 6. ALU Arithmetic Mode Functions.
0
0
0
0
AAQ
"AA B
BAA
BAQ
Table 5. ALU Logic Mode Functions.
4-25
WS59032
WS59032D
COMMERCIAL RANGE AC
CHARACTERISTICS
CYCLE TIME AND CLOCK
CHARACTERISTICS
The tables shown here specify the guaranteed performance of the WS59032D over the Commercial
operating temperature range of O°C to +70°C and
a power supply range of 5V ± 5%. Inputs are
switching between 0 and 3V with rise and fall times
of 1 V/ns and measurements made at 1.5V. All outputs have maximum DC load.
READ-MODIFY-WRITE (from select
of A, B reaisters to end of cycle)
Maximum Clock Frequency to Shift
Q~50% duty cycle I =432 or 632)
Minimum Clock Low Time
Minimum Clock High
26.4 MHz
Minimum Clock Period
48ns
51ns
22ns
26ns
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with CL = 5pF and
measured to O.5V change of output voltage.
From OE Low to Y output enable'
From OE High to output disable
COMBINATIONAL PROPAGATION DELAYS (CL= 50PF)
~
OUTPUT
Y
F3l
Cn + 32
F=O
A, B ADDRESS
66
66
58
66
00-031
45
45
35
45
FROM
INPUT
RAMO,
RAM3l
00,
031
62
75
35
48
-
OVR
Cn
36
36
18
36
32
42
1012
1345
46
51
46
51
35
41
46
51
41
46
58
53
22
20
-
-
59
22
1678
22
-
-
-
A BYPASS ALU
(I=2XX)
46
-
-
-
-
CLOCK
51
51
42
51
46
UNITS
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT
~P
INPUT
A, B Source
Address
B Destination
Address
Set Up before H L
Hold after H L
20
1 (Note 3)
Set Up before L
53 (Note 4)
H
Hold after L
DO NOT CHANGE (Note 2)
0
-
-
20
0
Cn
-
22
0
1012
-
-
28
1345
7
30
DO NOT CHANGE (Note 2)
0
0
-
-
1678
RAMO. 31 and
QO,31
NOTES:
4-26
-
7
UNITS
0
10
00-031
H
ns
0
3
1) Dashes indicate that a set-up time constraint or a propagation delay path does not exist.
2) The phrase "DO NOT CHANGE" indicates that certain signals must remain low for the duration of the clock Low time.
Otherwise, erroneous operation may be the result.
3) Prior to clock H> L transition, source·addresses must be stable to allow time for the source data to be set up before the
latch closes. After this transition the A address may be changed. If it is not being used as a destination, the B address
may also be changed. If it is being used as a destination, the B address must remain stable during the clock Low period.
4) Set-up time before H> L included here.
WS59032
WS59032D
MILITARY RANGE AC
CHARACTERISTICS
CYCLE TIME AND CLOCK
CHARACTERISTICS
The tables shown here specify the guaranteed per·
formance of the WSS9032D over the Military
operating temperature range of -SsoC to +12SoC
and a power supply range of SV ± 10%. Inputs are
switching between 0 and 3V with rise and fall times
of 1 Vlns and measurements made at 1.SV. All out·
puts have maximum DC load.
READ·MODIFY·WRITE (from select
of A, B registers to end of cycle)
Maximum Clock Frequency to Shift
(50% duty cycle I = 432 or 632)
Minimum Clock Low Time
Minimum Clock High
28ns
30ns
Minimum Clock Period
60ns
SOns
23.6 MHz
a
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with CL = SpF and
measured to O.SV change of output voltage.
From DE Low to Y output enable
From DE High to output disable
COMBINATIONAL PROPAGATION DELAYS (CL= SOPF)
~
Y
F31
Cn + 32
F=O
OVR
RAMO,
RAM31
QO,
Q31
A, B ADDRESS
72
72
63
69
69
81
-
FROM
OUTPUT
INPUT
00·031
51
51
40
52
42
52
Cn
41
41
21
39
36
36
-
1012
48
48
40
48
44
63
-
1345
54
54
46
56
51
57
-
1678
27
-
-
20
-
-
-
21
51
-
-
-
58
58
50
58
53
66
29
A BYPASS ALU
. (I=2XX)
CLOCK
UNITS
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT
~P
INPUT
Set Up before H
L
Hold after H
L
Set Up before L
A, B Source
Address
25
B Destination
Address
25
DO NOT CHANGE (Note 2)
1 (Note 3)
63 (Note 4)
H
Hold after L
00·031
-
-
30
0
-
30
0
1012
-
36
0
1345
-
-
42
0
1678
13
DO NOT CHANGE (Note 2)
0
RAMO, 31 and
00 31
-
-
5
NOTES:
UNITS
1
Cn
10
H
1
ns
1) Dashes indicate that a set-up time constraint or a propagation delay path does not exist.
2) The phrase" DO NOT CHANGE" indicates that certain signals must remain low for the duration of the clock Low time.
Otherwise, erroneous operation may be the result.
3) Prior to clock H> L transition, source addresses must be stable to allow time for the source data to be set up before the
latch closes. Afterthis transition the A address may be changed. If it is not being used as a destination, the B address
may also be changed. If it is being used as a destination, the B address must remain stable during the clock Low period.
4) Set-up time before H> L included here.
4-27
WS59032
WS59032E
CYCLE TIME AND CLOCK
CHARACTERISTICS
COMMERCIAL RANGE AC
CHARACTERISTICS
The tables shown here specify the guaranteed performance of the WS59032E over the Commercial
operating temperature range of O°C to +70°C and
a power supply range of 5V ± 5%. Inputs are
switching between 0 and 3V with rise and fall times
of 1 Vins and measurements made at 1.5V. All outputs have maximum DC load.
READ-MODIFY-WRITE (from select
of A B registers to end of cyple)
Maximum Clock Frequency to Shift
a (50% dulY cycle I ~ 432 or 632)
Minimum Clock Low Time
Minimum Clock High
33 MHz
Minimum Clock Period
40ns
42ns
18ns
21ns
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with Cl = 5pF and
measured to O.5V change of output voltage.
COMBINA TlONAL PROPAGA TlON DELA YS
(Cl = 50PF)
~
OUTPUT
Y
F31
Cn + 32
F=O
OVR
RAMO,
RAM31
QO,
Q31
A, B ADDRESS
55
55
48
55
51
62
-
00-031
37
37
29
37
29
40
-
Cn
30
15
30
26
35
FROM "
INPUT
1012
38
30
38
29
38
34
48
1345
42
42
34
42
38
44
-
-
18
16
-
-
-
-
-
35
42
38
49
18
1678
18
A BYPASS AlU
(1=2XX)
38
-
CLOCK
42
42
UNITS
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (CP) INPUT
I~CP
Set Up before H
L
Hold after H
L
Set Uj) before L
H
Hold after L
A, B Source
Address
20
B Destination
Address
10
DO NOT CHANGE (Note 2)
-
18
0
-
20
0
1012
-
26
0
1345
-
-
29
0
1678
5
DO NOT CHANGE "(Note 2)
0
RAMO, 31 and
aO,31
-
-
3
00-031
Cn
NOTES:
o (Note 3)
44 (Note 4)
5
H
UNITS
0
0
ns
1) Dashes indicate that a set-up time constraint or a propagation delay path does not exist.
2) The phrase "DO NOT CHANGE" indicates that certain Signals must remain low for the duration of the clock low time.
Otherwise, erroneous operation may be the result.
3) Prior to clock H> l transition, source addresses must be stable to allow time forthe source data to be set up before the
latch closes. After this transition the A address may be changed. If it is not being used as a destination, the B address
may also be changed. If it is being used as a destination, the B address must remain stable during the clock low period.
4) Set·up time before H> l included here.
4-28
WS59032
WS59032E
MILITARY RANGE AC
CHARACTERISTICS
CYCLE TIME AND CLOCK
CHARACTERISTICS
READ-MODIFY-WRITE (from select
of A, B registers to end of cycle)
Maximum Clock Frequency to Shift
a (50% du!y cycle I = 432 or 632)
Minimum Clock Low Time
Minimum Clock High
The tables shown here specify the guaranteed performance of the WS59032E over the Military
operating temperature range of -55°C to +125°C
and a power supply range of 5V ± 10%. Inputs are
switching between 0 and 3V with rise and fall times
of 1 V/ns and measurements made at 1.5V. All outputs have maximum DC load.
50ns
29 MHz
23ns
25ns
Minimum Clock Period
50ns
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with C L = SpF and
measured to O.SV change of output voltage.
From OE Low to Y output enable
From OE High to output disable
COMBINATIONAL PROPAGATION DELAYS (CL= SOPF)
~
FROM
OUTPUT
RAMO,
RAM31
QO,
Q31
57
67
-
35
43
-
32
30
30
33
40
36
52
-
45
38
46
42
47
-
-
-
16
-
-
17
42
-
-
-
48
48
41
48
44
55
24
F=O
OVR
52
57
33
43
17
40
45
22
Y
F31
A, B ADDRESS
60
60
00-031
42
43
Cn
34
1012
34
40
1345
1678
A BYPASS ALU
(1=2XX)
Cn + 32
INPUT
CLOCK
UNITS
ns
SET-UP AND HOLD TIMES RELATIVE TO CLOCK (ep) INPUT
IN~CP
Set Up before H
L
Hold after H
L
Set Up before L
H
Hold after L
A, B Source
Address
23
B Destination
Address
23
DO NOT CHANGE (Note 2)
1
-
-
25
0
-
25
0
30
0
-
00-031
Cn
o (Note 3)
52 (Note 4)
1345
35
0
1678
10
DO NOT CHANGE (Note 2)
0
RAMO, 31 and
aO,31
-
-
5
NOTES:
7
UNITS
1
-
1012
H
ns
1) Dashes indicate that a set-up time constraint or a propagation delay path does not exist.
2) The phrase "DO NOT CHANGE" indicates that certain signals must remain low for the duration of the clock Low time.
Otherwise, erroneous operation may be the result.
3) Prior to clock H> L transition, source addresses must be stable to allow time for the source data to be set up before the
latch closes. After this transition the A address may be changed. If it is not being used as a destination, the B address
may also be changed. If it is being used as a destination, the B address must remain stable during the clock Low period.
4) Set-up time before H> L included here.
4-29
WS59032
COMPETITIVE TIMING ANAL YSIS
The following analysis compares the critical timing paths of a WS59032E vs. the equivalent Bipolar circuit
implementation using eight 2901C's, two 2902A's and three high speed logic gates (See Figure).
As can be seen from the following comparison, the Data Path of the WS59032E is 44% faster than the Data Path
of the Bipolar/ECl functional equivalent circuit. Additionally, the Control Path of the WS59032E is 50% faster
than the Bipolar/ECl implementation. The actual values for the Bipolar/ECl circuit will be lengthened by the
layout dependent interconnect delays between the individual devices. When these delays are taken into account,
the WS59032E speed advantage becomes even greater.
TIMING COMPARISON
WS59032D vs Eight 2901 C's, Two 2902A's Plus High Speed Logic
DATA PATH
CONTROL PATH
WS59032E
WS59032E
A,S Address
interconnect delay
Total Delay
.. F =0 = 55ns
= 0ns
:::; 55ns
• F =0 =·48ns
= gns
:::;,48ns
1012
interconnect delay
Total Delay
DISCRETE IMPLEMENTATION (See Figure)
DISCRETE IMPLEMENTATION (See Figure)
A,S
P3,G3
P,G
C16
C28
interconnect delay
1012
P3,G3
P,G
C16
C28
interconnect delay
"P3,G3=37ns
.. P,G = 11ns
.. C16 = 10ns
.. C281= 14ns
.. F = 0 = 25ns
= Xns
Total Delay
>97ns
.. F = 0 = 37ns
• P,G = 11ns
"C16=10ns
.. C28 = 14ns
• F = 0 = 251ns
= Xns
Total Delay
>97ns
Look-Ahead Carry Using Discrete Components
Four 2901Cs
Four 2901Cs
C20, 24, 28
C4,8,12
C'N
4-30
2902A
2902A
WS59032
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS59032DG
WS59032DGMB
WS59032EG
WS59032EGMB
D
D
E
E
PACKAGE
TYPE
101
101
101
101
Pin
Pin
Pin
Pin
Ceramic
Ceramic
Ceramic
Ceramic
PGA
PGA
PGA
PGA
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
G2
G2
G2
G2
Comm'l
Military
Comm'l
Military
Standard
Mll-STD-SS3C
Standard
Mll-STD-SS3C
4-31
4-32
iFEE;:E
r======_
'=-iili-i~ E
WS5910AIB
WAFERSCALE INTEGRATION, INC.
PRELIMINARY
---
----~
-
CMOS MICROPROGRAM CONTROLLER
KEY FEATURES
• High Speed Operation
-
50% Faster Than Bipolar
• Low Power
-
225 mW
• On-Board Stack
-
9 Words Deep
• Bipolar Replacement
-
Fully Compatible with AM2910A
• Immune to Latch-Up
-
Over 200 rnA
• ESD Protection
-
Exceeds 2000 Volts
GENERAL DESCRIPTION
The WS5910A1B microprogram controller is an address sequencer which provides addresses to a control store memory.
These addresses can come from one of four internal sources: 1) the Microprogram Counter, 2) the 9 word x 12 bit
stack, 3) the 12-bit Register/Counter, or 4) the Direct Data Input. The address source selected is dependent upon
the instruction applied to the WS5910AlB.
The device can sequentially address memory or it can provide a conditional branch address anywhere within its
addressing range. In addition, the WS5910AlB also contains a last-in, first-out stack which provides capabilities for
looping as well as providing the microsubroutine return linkage. The on-board register/counter provides loop count
control with a count capacity of 4096.
The CMOS WS5910AlB is a form, fit and function replacement for the bipolar/ECl AM2910A. A.C. performance and
output drive capability, meet or exceed the specifications of its bipolar counterpart. The WS5910AlB is also available
as a macro cell in the WSI cell library.
FUNCTIONAL BLOCK DIAGRAM
4-33
WS5910AlS
PIN DESCRIPTION
SIGNAL NAME
I/O
Di
I
Direct Input to Register/Counter and Multiplexer. Do is LSB.
Ii
I
Instruction Inputs to the WS5910NB
DESCRIPTION
CC
I
Condition Code Input. Pass Test is a LOW on CC.
CCEN
I
When HIGH, CC Input is Ignored and Internally Forced LOW
CI
I
Carry Input to the LSB of the Microprogram Counter
RLD
I
When LOW, Register/Counter is Loaded Regardless of Instruction or Condition
OE
I
Three State Control of Vi Outputs
Vi
a
Address to Microprogram Memory. V0 is LSB.
CP
I
FULL
MAP
a
a
a
VECT
a
~
PL
All Internal States Change at LOW-to-HIGH Edge
Stack Full Indicator. (Stack is Nine Levels Deep.)
Active LOW Signal Used to Select the Pipeline Register as the Direct Input Source
Active LOW Signal Used to Select the Mapping PROM (or PLA) as the Direct
Input Source
Active LOW Signal Used to Select the Interrupt Vector as the Direct Input Source
PIN CONFIGURATION
v4
03
04
V3
V.
O2
D.
V2
VECT
0,
Pi:
V,
MAP
Do
13
Vo
I,
CI
Vee
CP
I,
GND
10
OE
CCEN
V"
CC
0"
RLD
V,o
FULL
010
D.
V.
V.
D.
07
V.
V7
D.
TOP
4-34
WS5910AlB
INTRODUCTION
The WS5910AlB is a high performance CMOS microprogram controller that produces a sequence of addresses which
control the execution of a microprogram. These 12-bit addresses are selected from one of the four sources which
feed into a 12-bit 4 to 1 multiplexer. The source selected can be 1) the direct data inputs (0 0-0,,), 2) the
Register/Counter, 3) the Microprogram Counter, or 4) the stack register. Selection is dependent upon which of the
sixteen instructions is being executed as well as other external inputs. The selected source is used to drive the YO-Y'1
three state output buffers.
External Inputs: 0 0-0 11
The external inputs can be used to supply the jump address for conditional branch types of instructions. They can
also be used to load the register counter.
Register Counter
The RC is an edge triggered 12-bit register which is clocked on the LOW-to-HIGH (positive) transition of the clock,
CPO The RC is loaded synchronously from the inputs when the load control input, RLO, is LOW. The output of RC
is referred to as R in the table of instructions.
°
The RC operates as a 12-bit down counter and is decremented and tested for a zero result during instructions 8,
9, and 15. If the RC is loaded with a number N, the sequence will be executed N + 1 times. This allows microinstructions
to be repeated up to 4096 times.
THE STACK AND STACK POINTER
The last-in-first-out stack, which is 9 levels deep by 12-bits wide, provides return addresses from micro-subroutine
or from loops. Integral to it is the stack pointer which points to the last word written. This allows data on the top of
the stack to be referenced without having to perform a POP operation.
There are five microinstructions during which a POP operation may occur (8, 10, 11, 13, 15). A POP decrements the
stack pointer at the next rising clock edge following the microinstruction causing the POP. The stack pointer points
to zero when the stack is empty. A POP from an empty stock may place unknown data on the Y outputs. The stack
pointer remains at zero if a POP is attempted on an empty stack.
There are three operations during which a PUSH operation may occur (1,3, and 5). A PUSH increments the stack
pointer and the return linkage is then written into the stack at the location pointed to by the just incremented stack
pointer. RESET (instruction 0) forces the stack pointer to zero, effectively emptying the stack. Each PUSH increments
the stack pointer by one, each POP decrements the stack pointer by one. When the stack reaches the level of nine
(stack pointer equals nine), the FULL flag goes low. This flag indicates that a POP should occur prior to the next
PUSH. If a PUSH does occur on a full stack, the data is overwritten at the top of the stack (location nine) but the
stack pointer remains unchanged. The operation will usually destroy useful information and is normally avoided.
4-35
WS5910A/B
TABLE OF INSTRUCTIONS
0
JZ
1
CJS
2
JMAP
3
CJP
4
PUSH
5
JSRP
REGI
CNTR
NAME
13-10 MNEMONIC
CONTENTS
Jump Zero
X
RESULT
FAIL
CCEN=L and CC=H
V
STACK
PASS
CCEN=H or CC=L
V
STACK
REG!
CNTR
ENABLE
0
Clear
0
Clear
Hold
PL
D
Push
Hold
PL
Map
Cond JSB PL
X
PC
Hold
Jump Map
X
D
Hold
D
Hold
Hold
Cond Jump PL
PC
Hold
D
Hold
Hold
PL
Push/Cond LD CNTR
X
X
PC
Push
PC
Push
Note 1
PL
Cond JSB R/PL
X
R
Push
D
Push
Hold
PL
6
CJV
Cond Jump Vector
X
PC
Hold
D
Hold
Hold
Vect
7
JRP
Cond Jump R/PL
X
RFCT
Repeat Loop,
CNTR *- 0
*-
Hold
Hold
D
F
Hold
Hold
Hold
Dec
PL
PL
=
0
0
R
F
9
RPCT
Repeat PL,
CNTR *- 0
*-
0
PC
PC
Pop
Hold
PC
D
Pop
Hold
Hold
Dec
PL
PL
=0
PC
Hold
PC
Hold
Hold
PL
10
CRTN
Cond RTN
PC
Hold
F
Pop
Hold
PL
11
CJPP
Cond Jump PL & Pop
X
X
PC
Hold
D
Pop
Hold
PL
PL
8
12
LDCT
LD Cntr & Continue
X
PC
Hold
PC
Hold
Load
13
LOOP
Test End Loop
X
F
Hold
PC
Pop
Hold
PL
14
CONT
Continue
X
15
TWB
Three-Way Branch
PC
F
Hold
Hold
PC
PC
Hold
Pop
Hold
Dec
PL
PL
Pop
PC
Pop
Hold
*-
0
=0
D
= Land CC = H, hold; else load.
ABSOWTE MAXIMUM RATINGS*
(Comm'I) ........ O°C to +70°C
(Mil) ........ -55°C to +125°C
Storage Temp. (No Bias) ....... -65°C to +150°C
Voltage on any pin with
respect to GND ............... -0.6V to +7V
Latch Up Protection ................. >200 mA
ESD Protection ..................... > ±2000V
SYMBOL
Over Operating Temperature Range (See Note 1)
PARAMETER
TEST CONDITIONS
Vce = Min.
VIN = V IH or V IL
MIN
IOH
=
IOL
= 12 mA
MAX
UNITS
0.5
V
VOH
Output High Voltage
VOL
Output Low Voltage
VIH
Input High Voltage
VCC = Min.
All Outputs
VIN = VIH or VIL
Guaranteed Input High Voltage
VIL
Input Low Voltage
Guaranteed Input Low Voltage
lee
Input Load Current
Vec
= Max, VIN = GND or Vee
-10
10
loz
High Impedance
Output Current
Vcc
= Max, Vo = GND or Vee
-50
50
Icc
Power Supply Current
Vce
= Max
NOTES: 1) Commercial: Vee = +5V
4-36
PL
= Don't Care
"Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Operating Temp.
DC CHARACTERISTICS
x
L = LOW
H = HIGH
NOTE: 1) If CCEN
±
5%, TA
= O"C to 7O"C.
All Outputs
-3.4 mA
2.4
2.0
0.8
O°C to +70°C (Comm'l)
-55°C to + 125°G (Mil)
2) Military: Vee = +5V
±
10%, TA
= -55"C to
45
70
+125"C.
!lA
mA
WS5910AlB
WS5910A
COMMERCIAL RANGE
AC CHARACTERISTICS
The tables shown here specify the guaranteed performance of the WS5910A over the commercial operating range
of O°C to +70°C and a power supply range of 5V ± 5%.
Inputs are switching between 0 and 3V with rise and fall times of WIns and measurements made at 1.5V. All outputs
have maximum DC load.
CYCLE TIME AND CLOCK CHARACTERISTICS
Minimum Clock LOW Time
20
Minimum Clock HIGH Time
20
Minimum Clock Period
50
Maximum Clock Frequency
20
COMBINATIONAL PROPAGATION DELAYS (C L
INPUT
Y
Do-D11
10-13
CC
ns
MHz
= 50 pF)
PL, VECT, MAP
FULL
UNITS
20
-
35
30
30
-
ns
31
CCEN
30
-
CP
40
-
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with CL = 5 pF and measured to 0.5V change of output voltage.
From OE LOW to Y Output Enable
25
From OE HIGH to Y Output Disable
27
ns
SET UP AND HOLD TIMES
INPUT
ts
tH
Di -
R
16
0
PC
30
0
10-13
35
0
Di -
CC
24
0
CCEN
24
0
CI
18
0
RLD
19
0
UNITS
ns
4-37
WS5910A1S
WS5910A
MILITARY RANGE
AC CHARACTERISTICS
The tables shown here specify the guaranteed performance of the WS5910A over the military operating range of -55°C
to +125°C and a power supply range of 5V ± 10%.
Inputs are switching between 0 and 3V with rise and fall times of 1 Vlns and measurements made at 1.5V. All outputs
have maximum DC load.
CYCLE TIME AND CLOCK CHARACTERISTICS
Minimum Clock LOW Time
25
Minimum Clock HIGH Time
25
Minimum Clock Period
51
Maximum Clock Frequency
19.6
ns
MHz
COMBINATIONAL PROPAGATION DELAYS (CL = 50 pF)
INPUT
Y
Do-D11
PL, VECT, MAP
FULL
25
-
-
10-13
40
35
-
CC
36
CCEN
36
-
CP
46
-
UNITS
ns
35
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with CL = 5 pF and measured to 0.5V change of output voltage.
From OE LOW to Y Output Enable
25
From OE HIGH to Y Output Disable
30
ns
SET UP AND HOLD TIMES
INPUT
ts
tH
Di - R
16
0
Di - PC
30
0
10-13
38
0
CC
35
0
CCEN
35
0
CI
18
0
RLD
20
0
UNITS
ns
WS5910AlB
WS5910B
COMMERCIAL RANGE
AC CHARACTERISTICS
The tables shown here specify the guaranteed performance of the WS5910B over the commercial operating range
of O°C to +70°C and a power supply range of 5V ± 5%.
Inputs are switching between 0 and 3V with rise and fall times of 1 Vlns and measurements made at 1.5V. All outputs
have maximum DC load.
CYCLE TIME AND CLOCK CHARACTERISTICS
Minimum Clock LOW Time
13
Minimum Clock HIGH Time
13
Minimum Clock Period
33
Maximum Clock Frequency
30
COMBINATIONAL PROPAGATION DELAYS (C L
ns
MHz
= 50 pF)
INPUT
Y
PL, VECT, MAP
FULL
Do-D11
18
-
-
10-13
24
-
-
CC
21
CCEN
21
-
-
CP
27
-
20
UNITS
ns
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with CL = 5 pF and measured to 0.5V change of output voltage.
From OE LOW to Y Output Enable
21
From OE HIGH to Y Output Disable
22
ns
SET UP AND HOLD TIMES
INPUT
ts
tH
Di - R
11
0
Di - PC
20
0
10-13
23
0
CC
16
0
CCEN
16
0
CI
12
0
RLD
12
0
UNITS
ns
4-39
WS5910AlB
WS5910B
MILITARY RANGE
AC CHARACTERISTICS
The tables shown here specify the guaranteed performance of the WS5910B over the military operating range of -55°C
to +125°C and a power supply range of 5V ± 10%.
Inputs are switching between 0 and 3V with rise and fall times of 1 Vlns and measurements made at 1.5V. All outputs
have maximum DC load.
CYCLE TIME AND CLOCK CHARACTERISTICS
Minimum Clock LOW Time
17
Minimum Clock HIGH Time
17
Minimum Clock Period
35
Maximum Clock Frequency
29
ns
MHz
COMBINATIONAL PROPAGATION DELAYS (CL = 50 pF)
INPUT
Y
0 0-0 11
PL, VECT, MAP
FULL
UNITS
22
-
10-13
26
23
CC
24
-
ns
CCEN
24
-
CP
30
-
24
OUTPUT ENABLE/DISABLE TIME
Disable tests performed with C L = 5 pF and measured to 0.5V change of output voltage.
From OE LOW to Y Output Enable
24
From OE HIGH to Y Output Disable
25
ns
SET UP AND HOLD TIMES
4-40
INPUT
ts
tH
Di - R
11
0
Di - PC
20
0
10-13
25
0
CC
23
0
CCEN
23
0
CI
12
0
RLD
13
0
UNITS
ns
WS5910AIB
SWITCHING WAVEFORMS
3V
INPUTS
OV
Is
3V
CLOCK
OV
...
3V
....
Ie.
I'N
•
IH
..
~
OUTPUTS
OV
ORDERING INFORMATION
PART NUMBER
SPEED
WS5910AP
WS5910ADMB
WS5910BP
WS5910BDMB
20
20
30
30
MHz
MHz
MHz
MHz
PACKAGE
TYPE
40
40
40
40
Pin
Pin
Pin
Pin
Plastic DIP, 0.6"
CERDIp, 0.6"
Plastic DIP, 0.6"
CERDIp, 0.6"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
P1
Y1
P1
Y1
Comm'l
Military
Comm'l
Military
Standard
MIL-STD-883C
Standard
MIL-STD-883C
4-41
4-42
-
- ==~
...--....
-..,
=====
------=-~!!!-~-= --~
i='
~~
=
WS59510
WAFERSCALE INTEGRA nON, INC.
16 X 16 MUL TIPLIER ACCUMULATOR
KEY FEATURES
• 16 X 16 Bit Parallel
Multiplication with Accumulation to 3S-Bit Result
• Fast
-
• Immune to latch-up
-
30 ns Multiply
Accumulate Time
Over 200 mA
• Pin compatible and functionally
equivalent to Am29S10 and
TDC1010
• Low Power
-
• Two's complement or unsigned
magnitude operation
Icc = 100 mA (10 MHz)
FUNCTIONAL DESCRIPTION
The WS59510 is a high-speed 16 x 16 parallel multiplier accumulator which operates at 30 ns clocked multiply
,accumulate (MAC) time (33 MHz multiply accumulate rate). The operands may be specified as either two's
complement or unsigned magnitude 16-bit numbers. The accumulator functions include loading the
accumulator with the current product, adding or subtracting the accumulator contents and the current product,
or preloading the accumulator from the external world,
All inputs (data and instructions) and outputs are registered. These independently clocked registers are positive
edge triggered O-type flip-flops, The 35-bit accumulator/output register is divided into a 3-bitextended product
(XTP), a 16-bit most significant product (MSP), and a 16-bit least significant product (LSP). The XTP and MSP
have dedicated ports for three-state output; the LSP is multiplexed with the V-input. The 35-bit
accumulator/output register may be pre loaded through the bidirectional output ports.
FUNCTIONAL BLOCK DIAGRAM
CLKX>--r---t~~~
CLKYr-~~-----~-~
TC
RND
ACC
SUB
35
4-43
4
WS59510
PRODUCT SELECTION GUIDE
I
Maximum MultiplyAccumulate Time Ins}
59510-30
59510-40
59510-50
Commercial
30
Military
-
40
40
50
I
-
PIN CONFIGURATIONS
e
53
98 998@9 8 9
8S 98999 @) 9
51
50
48
46
44
42
40
38
36
52
49
47
45
43
41
39
37
35
EVe
55
54
@@>
57
56
@@
@@
@@
@@
TOP
(Through Package View)
9
@
34
(3
(8
32
33
30.
8
31
§
S
8 S
S 9
8 8
(9 S
®~
tYs:\
IYW:'\ tru:I fv14:\
@®® "-!V
® fv8:\
8 e
\.IV
fv6:\
tru:\
fv15:\
fv13:\
®® \!V 9 @ \5' \5' 9
59
58
28
61
60
26
27
63
62
24
25
65
22
64
20
1
68
2
X,.
9
8
3
4
765
5
6
7
8
9
10
\!:!g/ ~ ~
11
13
15
12
14
~
16
18
64
X7
63
x.
X.
62
x.
X.
61
x,.
X.
60
Xll
X,
59
29
x.
23
58
21
19
17
67 66 65 64 63 62 61
10
60
P2 ,V2
p.,v.
p.,v.
OEl
RND
11
59
12
58
SUB
13
2
Ps,Ys
57
56
Y2,P2
55
V.,p.
54
OEl
RND
Y4,P4
53
SUB
V.,p.
52
Y6'PS
51
ACC
ClKX
Y7,P7
50
ClKV
GND
49
Vee
48
TC
47
OEX
PREl
Y,0'P,O
46
Y,1,P,1
45
V,2 ,P,2
44
ACC
14
15
43
17
GND
GND
V,3 ,P,3
Vee
V,4 ,P,4
42
Vee
18
Pa,Va
Y,S ,P,5
Vee
19
p.,V.
p,.
Vee
20
P'O'Y'0
P'7
TC
21
P,1,Y,1
OEX
22
PREl
OEM
ClKP
23
16
41
40
39
38
P,2,V,2
p,.
p,.
P,3,Y,3
P2•
36
37
24
P,4,Y,4
p.,
35
25
P,S,Y,5
p ..
34
p ••
33
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
TOP VIEW
4-44
Pa,Va
p,.
x,.
Yo,Po
Y"P,
ClKX
ClKV
56
X'2
x,.
x,.
OEM
ClKP
WS59510
PIN DESCRIPTION
·Pin No. Name
1/0
Description
54
RND
I
Round
When RND is High, a bit with a weight of P15 is added to the multiplier product.
RND is loaded on the rising edge of ClKx or ClKy.
48
TC
I
Two's Complement
When High, the X and Y inputs are defined as two's complement data, or as unsigned data when low.
The TC control is loaded on the rising edge of ClKx or ClKy.
46
PREl
I
Preload
When High, data is preloaded into the specific output register when its respective load Enable is High.
When low, the accumulator register is available at the P-port when the Output Enables are low.
47
lEx/OEx
I
load Enable Extended/Output Enable Extended
Active High load Enable for the XTP port during preloading. Active low three-state control for the
XTP port during normal operation (see Preload Function). (TSX)"
45
lEm/OEm
I
load Enable Most/Output Enable Most
Active High load Enable for the MSP port during preloading. Active low three-state
control for the MSP port during normal operation (see Preload Function). (TSM)"
55
lEL/OEL
I
load Enable least/Output Enable least
Active High load Enable for the lSP port during preloading. Active low three-state
control for the lSP port during normal operation (see Preload Function). (TSl)"'
51,50
ClK" ClKy
I
CLOCKS
load X and Y data respectively and TC, RND, ACC and SUB/ADD on the rising edge.
44
ClKp
I
CLOCK
loads data into the XTP, MSP and lSP registers on the rising edge.
1-7,
56-64
X15-XO
I
Multiplier Data Input
Data is loaded into the X register on the rising edge of ClK,.
8-15,
17-24
Y15- Yo
P15-PO
I/O
Bidirectional Port
Data is loaded into the Y register on the rising edge of ClKy. Product output for least Significant
Product (lSP) and input to preload lSP register.
41-43
P34-P32
I/O
Bidirectional Port
Product output for extended Product (XTP) and input to preload XTP register.
25-40
P31-P16
I/O
Bidirectional Port
Product output for the Most Significant Product (MSP) and input to preload MSP register.
52
ACC
I
Accumulate
When High, the multiplier product is accumulated in the accumulator. When low, the multiplier
product is written into the accumulator (see Accumulator Function Table). The ACC control
is loaded on the rising edge of ClKx or ClKy.
53
SUB/ADD
I
Subtraction/Addition
When High, the accumulator contents are subtracted from the multiplier product and the result
written back into the accumulator. When low, the multiplier product is added into the
accumulator (see Accumulator Function Table). The SUB/ADD control is loaded on the
rising edge of ClKx or ClKy.
'DIP Configuration
"TRW TDC1010 Pin Designation
4-45
WS59510
ABSOLUTE MAXIMUM RATINGS·
*Notice: Stresses above those listed here may
cause permanent damage to the device. This is a
stress rating only and functional operation of the
device at these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods of
time may affect device reliability.
Operating Temp (Comm'I) ........ O°C to +70°C
(Mil) ......... -55°C to +125°C
Storage Temp. (No bias) ....... -65°C to +150°C
Voltage on any pin with
respect to GND ..................... -o.6V to +7V
Latch Up Protection ................... > 200 mA
ESD Protection ........................ > ±2000V
DC CHARACTERISTICS Over Operating Temperature Range (Note 1)
SYMBOL
PARAMETER
TEST CONDITIONS
Voh
Output High Voltage
Vee=Min.
Vin=Vih or Vii
All outputs
Vol
Output Low Voltage
Vee=Min
YO-Y31
101=9mA Mil
Vin=Vih or Vii
All others
101=8mA
loh = -1.6mA
MIN
MAX
UNITS
0.5
V
2.4
101=12mA Comm'l
Vih
Input High Voltage
Vii
Input Low Voltage
Guaranteed Input Low Voltage
Iix
Input Load Current
Vee = Max, Vin = Gnd or Vee
-10
10
Vee = Max, Vo = Gnd or Vee
-50
50
/-LA
loz
High Impedance
Output Current
Icc
Power Supply Current
Vee = Max
Comm'l. (O°C to + 70°C)
100
mA
Mil (-55°C to +125°C)
110
NOTES:
Guaranteed Input High Voltage
2.0
0.8
1) Commercial: Vee = +5V ± 5%, TA = O°C to +700C.
2) Military: Vee = +5V ± 10%, TA = -55°C to +125°C.
DETAILED DESCRIPTION
The WS59510 is a high-speed 16 x 16-bit multiplier accumulator (MAC). It comprises a 16-bit parallel multiplier
followed by a 35-bit accumulator. All inputs (data and instructions) and outputs are registered. The WS59510 is
divided into four sections: the input section, the 16 x 16asynchronous multiplier array, the accumulator, and the
output/preload section.
The input section has two 16-bit operand input registers for the X and Y operands, clocked by the rising edge of
CLKX and CLKY, respectively. The four-bit instruction register (TC, RND, ACC, SUB) is clocked by the rising
edge of the logical OR of CLKX, CLKY.
The 16 x 16 asynchronous multiplier array produces the 32-bit product of the input operands. Either two's
complement or unsigned magnitude operation is selected, based on control TC. If rounding is selected, (RND =
1), a "1" is added to the MSB of the LSP (position P15). The 32-bit product is zero-filled or sign-extended as
appropriate and passed as a 35-bit number to the accumulator section.
The accumulator function is controlled by ACC, SUB, and PREL. Four functions may be selected: the
accumulator may be loaded with the current product; the product may be added to the accumulator contents;
the accumulator contents may be subtracted from the current product; or the accumulator may be preloaded
from the bidirectional ports.
The output/preload section contains the accumulator/output register and the bidirectional ports. This section is
controlled by the signals PREL, OEX, OEM, and OEL. When PREL is HIGH, the output buffers are in high
impedance state. When the controls OEX, OEM, and OEL are also high, data present at the output pins will be
preloaded into the appropriate accumulator register at the ri~ing edge of CLKP. When PREL is LOW, the Signals
OEX, OEM, andOEL are enable controls for their respective three-state output ports.
4-46
WS59510
WS59510
Input Formats
Fractional Two's Complement Input
YIN
XIN
115
14
13
12
11
10
9
8
7
6
5
4 3
2
1 0
I
115
14
13
12
11
10
9
8
7
6
5
4
3
2
1
01
-202-12-22-32-42-52-62-72-82-92-102-112-122-13 2-14 2-15
-202-12-22-32-42-52-62-72-82-92-102-112-122-13 2-14 2-15
(Sign)
(Sign)
Integer Two's Complement Input·
YIN
XIN
-215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
1 15 14 13 12 11 10 9 8 7 6 5 4 3 2
01
-215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
(Sign)
(Sign)
115
14
13
12
11
10
9
8
7
6
5
4
3
2
01
Unsigned Fractional Input
YIN
XIN
115
14
13
12
11
10
9
8
7
6
5
4
3
2
1 0
I
2-12-22-32-42-52-62-72-82-92-10 2-11 2-122-132-142-152-16
115
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
I
2-12-22-32-42-52-62-72-82-92-102-112-122-132-14 2-152-16
Unsigned Integer Input
XIN
115
14
13
12
11
10
9
YIN
8
7
6
5
4 3
2
01
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
115
14
13
12
11
10
9
8 7 6 5 4 3 2
01
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
WS59510
Output Formats
Two's Complement Fractional Output
XTP
MSP
LSP
134333211313029282726252423222120191817161115141312
-24 23 22
21 20 2-1 2-22-32-42-52.0 2-7 2-8 2-92-10 2-11 2-122-13 2-14
111098765432101
2-152-162-172-182-192-202-212-222-232-242-252-262-272-282-292-30
(Sign)
Two's Complement Integer Output
XTP
MSP
13433321
131 30 29 28 27 26 25 24 232221 20191817 161
115
LSP
-234233232
231230229228227226225224223222221220219218217216
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
14
13
12
11
10
9
8
7
6
5
4
3
2
01
(Sign)
Unsigned Fractional Output
XTP
MSP
LSP
134333211313029282726252423222120191817161
222120
2-12-22-32-42-52-62-72-82-92-102-112-122-132-142-152-16
115141312111098765432101
2-172-182-192-202-212-222-232-242-252-262-272_282_292_302-312-32
Unsigned Integer Output
XTP
MSP
13433321
131 30 29 28 27 26 25 24232221 20191817 161
-234233232
231230229228227226225224223222221220219218217216
LSP
115
14
13
12
11
10
9 8 7 6 5 4 3 2
01
215 214 213 212 211 210 29 28 27 26 25 24 23 22 21 20
4-47
WS59510
SWITCHING CHARACTERISTICS
Over Operating Range
PARAMETERS
DESCRIPTION
WS59510-30
WS5951 0-40
WS59510-50
MIN
MIN
MIN
MAX
30
MAX
40
UNITS
MAX
50
ns
Multiply Accumulate Time
tMA
Setup Time (XIN,YIN,RND,TC,ACC,SUB)
tSI
5
5
5
ns
Setup Time (PREl,OEX,OEM,OEl)
tS2
15
15
15
ns
Hold Time
tH
2
2
2
ns
Clock Pulse Width
tpw
10
10
15
ns
Output Clock to P
t pDP
20
25
30
ns
tpDY
20
25
30
ns
Output Clock to Y
OEX, OEM to P;
High to Z
tpHZ
20
25
30
ns
OEl to Y (Disable Time)
low to Z
tpLZ
20
25
30
ns
OEX, OEM to P;
Z to High
20
25
30
ns
OEL to Y (Enable Time)
Z to low
30
ns
tpzH
20
tpZL
Relative Hold Time
t HCL
25
0
0
0
ns
NOTE: Inputs are switching between 0 and 3V with rise and fall times of I V/ns and measurements made at 1.5V. All inputs have maximum
DC load.
TEST WAVEFORMS
Test
Vx
All tPD'S
VCC
VOH
VOL
VOH
tpHZ
*
OUTPUT WAVEFORM - MEASUREMENT lEVEL
O.OV
1.5V
.J
'\J"'4' 0.5V
O.OV
tPLZ
2.6V
VOL
tpZH
O.5V~
f
O.OV
O.OV
2.6V
tPZL
2.6V
Setup and Hold Time
1:
2.6V
VOH
1.5V
1 .5V
VOL
Pulse Width
·~:xxxt-IS-J-'-,jOOQ{~'
TIMING - - - - - -INPUT _ _ _ _ _---J_
-
:.:v
OV
Notes:
I Diagram shown for HIGH data only. Output transition may be
opposite sense.
2. Cross hatched area is don't care condition.
4-48
WS59510
WS59510 TIMING DIAGRAM
CLKX
---------1
CLKY
CLKP ________________________________________J
~~~~~~~7r.~~~~~~~~~~~~~~7r.~~~~~~,~--------
OUTPUT
~Y~~~~~~~~~~~~~~~~~~~~~~~~~~I~-------------
PRELOAD TIMING DIAGRAM
1-0---
Ipw
CLKP
PREL
OEX
----...;;;or
OEM ..
OEL
OUTPUT
PINS _
....~~..,,'--------I"""~L.IIiII..K..x..K..l~'_W..K.~~~L.IIiII..K.~~~u.c..K.K.l~~u.c. .
THREE-STATE TIMING DIAGRAM
3-STATE
CONTROL
-
VOH
1.5V
VOL
IpHz __
(DISABLE)
,.
VOH
1.5V
-~
1.5V
VOL
_ l pzH -
~
(HIGH LEVEL)
3-STATE
OUTPUT
VOH
(ENABLE)
O.5V
(HIGH IMPEDANCE)
"If(LOW LEVEL)
VOL +O.5V
-
(DISABLE)
IPZL ENABLE
4-49
WS59510
ACCUMULATOR FUNCTION
TABLE
SUB/
PREL ACC ADD
L
L
L
H
L
H
H
X
PRELOAD FUNCTION
P
OPERATION
X
Q
Load
L
Q
H
Q
X
Add
Subtract
PL
Preload
Output Register
LEx!
LEM!
LEe!
PREL
0Ex
OEM
OEL
XTP
MSP
LSP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Q
Q
Q
Q
Q
Q
Q
Z
Z
Q
1
1
0
0
0
1
0
1
0
Q
Q
Q
1
1
1
0
0
0
0
0
0
0
0
Z
Z
Z
Z
Q
1
1
1
1
1
1
1
1
PL
1
1
0
Z
Z
Z
Z
Z
Z
Z
Z
PL
PL
PL
1
1
1
1
0
0
0
Z
Z
PL
1
1
0
PL
PL
PL
1
1
1
1
1
1
1
1
PL
PL
PL
PL
Z
Z
Z
Z
Z
Z
Z
Z
Z = output buffers at High impedance (disabled).
Q = output buffers at Low impedance. Contents of output
register available through output ports.
PL = output disabled. Preload data supplied to the output
pins will be loaded into the output register at the rising
edge of CLKp.
ORDERING INFORMATION
PART NUMBER
SPEED
(ns)
WS59510-30J
WS59510-40G
WS59510-40GMB
WS59510-40J
WS59510-40P
WS59510-50G
WS59510-50GMB
WS59510-50J
WS59510-50P
30
40
40
40
40
50
50
50
50
4-50
PACKAGE
TYPE
68
68
68
68
64
68
68
68
64
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
PLDCC
Ceramic PGA
Ceramic PGA
PLDCC
Plastic DIP, 0.9"
Ceramic PGA
Ceramic PGA
PLDCC
Plastic DIP, 0.9"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
J1
G1
G1
J1
M1
G1
G1
J1
M1
Comm'l
Comm'l
Military
Comm'l
Comm'l
Comm'l
Military
Comm'l
Comm'l
Standard
Standard
MIL-STD-883C
Standard
Standard
Standard
MIL-STD-883C
Standard
Standard
, WS59520/WS59521
WAFERSCALE INTEGRA110N. INC.
MULTILEVEL PIPELINE REGISTER
KEY FEATURES
• Four 8-Bit Registers
• Contents of Each Register Available
at Output
• 24-Pin 300 Mil Package
• Dual Two Stage or Single Four Stage
Push Only Stack Operation
• Hold, Transfer and Load Instructions
• High Performance CMOS
• TTL Compatible
GENERAL DESCRIPTION
The WS59520 and WS59521 are CMOS drop-in replacements for the bipolar AM29520 and AM29521 devices offered
by Advanced Micro Devices. The high performance CMOS process with which these products are manufactured enables
them to operate at bipolar speeds while consuming one tenth the power of the bipolar circuits.
The WS59520/521 consists of four 8-bit registers which can be configured as a single four level pipeline or two dual
level pipelines. The architectural configuration is determined by the instruction inputs (10 and 11).
Each of the four registers contents is available at the multiplexed output. The register to be used as the output register
is determined by the control inputs (So and Sl). The output is 8-bits wide and is enabled by the OE input.
The WS59520 and WS59521 differ only in the dual two level stack mode of operation.
FUNCTIONAL BLOCK DIAGRAM
MUX
4-51
WS59520/521
ABSOLUTE MAXIMUM RATlNGS*
* Notice: Stresses above those listed here may
cause permanent damage to the device. This is a
stress rating only and functional operation of the
device at these or any other conditions above
those indicated in the operational section of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
of time may effect device reliability.
Operating Temp (Comm'l) ....... O·C to + 70·C
(Mil) ....... - 55·C to + 125·C
Storage Temp. (No bias) .... - 65·C to + 150·C
Voltage on any pin with
respecttoGND ............... -0.6Vto +7V
latch Up Protection ................. >200 mA
ESD Protection ... . . . . . . . . . . . . . .. > ± 2000V
PIN DESCRIPTION
SIGNAL NAME
DESCRIPTION
110
0 0-07
I
Data input port
YO-Y7
0
Data output port
ClK
I
Data latches on low-to-High Transition
10-11
I
Instruction inputs. Refer to Instruction Control Tables.
So' S1
I
Selects one of four registers to be read at the output port.
OE
I
Active low, output enable. A high signal disables the output port.
PIN CONFIGURATION
INSTRUCTION CONTROL
(INSTRUCTION) 10
Vee
(INSTRUCTION) I,
So (MUX SELl
Do
S, (MUX SELl
0,
Yo
D.
Y,
D.
Y.
0,
Y.
0,
Y,
D.
Y,
07
Y.
elK
Y7
GND
OE
11
10
0
0
4-52
50
0
0
0
W559520 or W559521
1
B1
0
A2
1
1
A1
A2
82
[EJ
[EJ
cfu
82
Em
[ill
[]I]
~
[EJ
~
@]
[EJ
QD
1
0
~
A2
B2
1
~
1
REGISTER SELECT
51
W
A2
0
1
1
W559521
W559520
82
~
ALL REGISTERS HOLD
ALL REGISTERS HOLD
WS59520/521
DC CHARACTERISTICS Over Operating Range (See Notes)
SYMBOL
TEST CONDITIONS
PARAMETER
Voh
Output High Voltage
Vee = Min.
Vin = Vih or Vii
Vol
Output Low Voltage
Vee = Min.
Vin = Vih or Vii
MIN
MAX
UNITS
0.5
V
2.4
10h = -6.5mA
IOL '" 20 mA
Comm'l
IOL '" 16 mA Mil
Vih
Input High Voltage
Guaranteed Input High Voltage
Vii
Input Low Voltage
Guaranteed Input Low Voltage
lix
Input Load Current
Vee = Max, Vin = Gnd or Vee
-10
10
loz
High Impedance
Output Current
Vee = Max, Vo = Gnd or Vee
-50
50
Icc
Power Supply Current
Vee = Max
O.B
I Comm'l (0° + 70°C)
I Mil (- 55° to + 125°C)
1) Commercial: Vcc = +5V ± 5%, TA = O°C to 70°C.
2) Military: Vcc = +5V ± 10%, TA = -55°C to +125°C.
NOTES:
2.0
3) CL
12
~A
mA
15
= 50 pF except for tOF where CL = 5 pF.
SWITCHING CHARACTERISTICS Over Operating Range (See Notes)
WS59520IWS59521
COMMERCIAL
PARAMETER
DESCRIPTION
MIN
MAX
MILITARY
MIN
MAX
tpo
Clock to Data Out
22
24
tSEL
Mux Select to Data Out
20
22
ts
Input (Data/lnstr.) Set Up
10
10
tH
Input (Data/lnstr.)Hold
3
3
tOF
Output Disable
16
22
21
tPWH
Clock Pulse Width High
10
10
tPWL
Clock Pulse Width Low
10
10
TIMING DIAGRAM
CLOCK
-
INSTR --...
-
DATA IN---"
MUXSEL~
OUTPUT TIMING DIAGRAM
IPWH-==::J
OE
VALID
_ I s _ . IH•
VALID
VALID
--
OUTPUT
... lpD ..
DATA OUT
r
'j."
~IPWL~
_ l s _ _ I H•
- ISEL
ns
15
Output Enable
tOE
UNITS
VALID
iIDF~ t=
Jt-IDE
Inputs are switching between 0 and 3V with rise and fall times of 1 Vlns and measurements made at 1.5V. All outputs
have maximum DC load.
4-53
WS59520/521
ORDERING INFORMATION
PART NUMBER
WS59520S
WS59520T
WS59520TMB
WS59521S
WS59521T
WS59521TMB
4-54
SPEED
(ns)
22
22
24
22
22
24
PACKAGE
TYPE
24
24
24
24
24
24
Pin
Pin
Pin
Pin
Pin
Pin
Plastic DIP, 0.3"
CERDIp, 0.3"
CERDIp, 0.3"
Plastic DIP, 0.3"
CERDIp, 0.3"
CERDIp, 0.3"
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
S1
K1
K1
S1
K1
K1
Comm'l
Comm'l
Military
Comm'l
Comm'l
Military
Standard
Standard
MIL-STD-883C
Standard
Standard
M IL-STD-883C
_-
.==~
...II' == == --------!i-~!i-~-=
......
-==
!!.
~
~-
WS59820
-'"
WAFERSCALE INTEGRA710N, INC
BI·DIRECTIONAL BUS INTERFACE REGISTERS
KEY FEATURES
• Two Banks of
ax
16 Registers
• Contents of Each Register Available
at Output
• Provides Temporary Address or Data
Storage Between Two Processor Ports
or Buses
• Bi-Directional Buses Interface - Dual
4-Deep or a-Deep Registers in Each
Direction
• Separate Control for Each Register Bank
• Direct Processor Bus-to-Bus Interface
• TTL Compatible
• Replaces Eight WS59520's
GENERAL DESCRIPTION
The WS59820 consists of two banks of registers, eight registers in each bank, each register 16 bits wide. A single
bank can be configured as an eight level pipeline or two each four level pipelines. The architectural configuration
is determined by the instruction inputs (10 and 11) for each register bank.
Each of the eight registers in each bank is available at the multiplex output. The output register is determined by
the control inputs (SO, S1, and S2) for each register bank. The multiplexed ouput is 16 bits wide and is enabled by
the -OEN signal. Each bank of registers has its own clock (elK), instruction inputs (10-1) and multiplex controls.
BLOCK DIAGRAM
DAYB
(15:0)
CLKA-+----..,~
EIGHT
A
REGISTERS
EIGHT
t---j--CLKB
B
REGISTERS
IBO•1
SBO•1•2
DBYA
(15:0)
4-55
WS59820
DAYB (15:0)
1
~-.
2
A
INSTRUCTION
lAo"
t--+
~
A
REGISTER
CONTROL
CLKA~
1
--.
--.
--.
•
I
HEX REG A7
I
HEX REG A.
I
HEX REG A.
I
HEX REG A.,
/
/
·..
t
"
+
L
HEX REG A3
I
HEX REG A.
I
HEX REG A,
I
HEX REG
..
.L
I
HEX REG Bo
I
I
HEX REG B,
1
I
I
HEX REG B.
I
I
I
HEX REG B3
/
MUX
t
•
t
r1
(;
','
8:1 MUX
Ao
+
~
BYPASS~
OENA
r
I
I
I
I
HEX REG B.
I
I
HEX REG
MUX
?
1
DBYA (15:0)
4-56
"-
••
I
/
1
t
1
HEX REG B•
6
1
HEX REG Bs
•
t
•
I
I
/
•
1
I
e,
t
2
/
::
:=
~ ~STRUCTION
B
REGISTER
CONTROL
..
'l
8:1 MUX
t
MUX
SB..,
t
~
t
•
~BYPASS
MUX
IB..,
~CLKB
1
WS59820
REGISTER SHIFT OPTIONS FOR
REGISTERS A OR B
SELECTION TABLE FOR
REGISTER A OR B
SX2
SX1
SXO
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
x=
IX., IX,
REGISTER
SELECTED
REG
REG
REG
REG
REG
REG
REG
REG
=0
IX., IX,
=1
lX., IX,
DATA
DATA
= 2
IX., IX, = 3
DATA
0
1
2
3
4
5
6
7
NO LOAD
OR
SHIFTING
Register A or B.
SINGLE
8-LEVEL
x
DUAL
4-LEVEL
= Register A or B.
MULTIPLEX CONTROL
OENA
OENB
BYPASS
0
0
1
Pass Output of 8:1 Muxes to Outputs
OPERATION
0
0
0
Not Allowed (Input is Preferred)
0
1
0
Pass Input From DAYB (15:0) to Output DBYA (15:0)
0
1
1
Pass Output From 8:1 Mux to Outputs DBYA (15:0)
1
0
0
Pass Input From DBYA (15:0) to Output DAYB (15:0)
1
0
1
Pass Output From 8:1 Mux to Outputs DAYB (15:0)
1
1
X
Inhibit Outputs (High Impedance)
PIN DESCRIPTION
DESCRIPTION
SIGNAL NAME
I/O
IAo,IA1
I
Instruction Inputs for Register Bank A
IBo,IB1
I
Instruction Inputs for Register Bank B
SAo-SA2
I
Multiplex Select for Register Bank A
SBo-SB 2
I
Multiplex Select for Register Bank B
OENA
I
Output Enable for Output Port DBYA
OENB
I
Output Enable for Output Port DAYB
ClKA
I
Clock Input for Register Bank A
ClKB
I
Clock Input for Register Bank B
DBYA 15:0
I/O
Register Bank B Input Port, Register Bank A Output Port
DAYB 15:0
I/O
Register Bank A Input Port, Register Bank B Output Port
BYPASS
I
BYPASS Control (Active low). See Table on Output Control
4-57
WS59820
PACKAGE ORIENTATION
68 PIN CPGA
(Top Through Package View)
A
2
3
4
-+-
.....
o
. -
-+.
. +-
6
7
8
9
10
.+-
-+-
-+-
-t-
-~-
.-t-
-+-
-+ .
-+.
.+-
5
.
0
-+.
.. -
.11
B
-+-
.,-
C
.-+--
-to
-"t-
D
--t-
.....-
...- .....,
E
·t- -t-
o
0
,
-t-t-+-
-1-
0
0
F
.,+-
-+-
-t- -t-
G
-+-
-+.
-.. 0
-i-
H
-+.
-+0
-+-
.+--
J
-+--
-....
-"t-
K
i
o
0
o
0
0
0
... -
...
.+.
... -
-t-
L
.0
-,
-1'-
.1.
,
-+- ."t-
-f-
0
--t-
.+-
-... -
-+-
... -
-+-
-t-
0
0
0
-+0
68 PIN PLDCC
(Top Through Package View)
!II
q q zQ
z z c:I
i t ilffi :. .g -Ii i
Q
Q
Q
,t '1
1_ L_ 1.._ I _ 1_ L_ L_ I _ I
,I
f
g
"
,I
II
,I
~
i ...
0 ~
,I
II
,I
,I
ff q q
>
U
"
II
t I
Z
Z
II
I
I
I
I '-_ I _ L_ L_ L_ L._ I _ Lo_
8765432':6867666564636261
Lf
60r:
N.C
N.C. -:~11
59r:
N.C
DBYA. -: J 12
DBYA. -:J13
58 ~:
DAYB,.
N.C. -:~ 10
57~:
DAYB,.
-:J 14
56r:
DAYB,.
DBYA. -:~15
DBYA7 -:~16
54~:
DBYA.
55r:
53~:
DBYA. -:J17
52r:
51r:
DBYA. -:~18
DBYA,o
DBYA"
DBYA,.
DBYA,.
-: ~ 19
-:J20
-:J21
50~:
49~:
48r:
47r:
46r:
-:~22
DBYA,. -:~23
DBYA,.
N.C.
N.C.
:J26
I
4-58
II
I -.., - , -
I -., -., -
1 -
I -., -., -
I -
I -
I
II
II
II
II
II
II
II
I
II
II
DAYB.
DAYB.
DAYB.
N.C.
I -
II II
DAY&,
DAYB.
N.C.
I -
II
DAYB.
DAYB.
44
II.,
II
DAYB"
DAYB,o
45~:
~HH~~n~M"U~nn~~~~
-"'\ - , -
DAYB,.
r:
WS59820
WS59820 THREE STATE TIMING
3-STATE
CONTROL
OE
"/
L
-'
(iiiS~~LE)
3-5TATE
OUTPUT
PORT
-
~~
_
VoH -O.5V
7 F-
-
VoH +O.5V
3V
1.5V
'<;;:
~
_ I OE _
- IDF (DISABLE)
OV
lo~.-=----::.£-
(ENABLE)
VOH
-1.5V
-1.5V
VOL
"
WS59820 TIMING DIAGRAM
IpwH
CLOCK
'I.
_ _ Is
IH...
INSTR
)I(
.~
DATA IN
.tPWL
VALID
Is
I H...
VALID
toya
i4-MUX SEL
ISEL
VALID
IpD
DATA OUT
--
X
VALID
tSEL
BYPASS
I BYP
68 PIN CPGA PIN DESIGNATOR
PIN
NAME
SIGNAL
NAME
PIN
NAME
SIGNAL
NAME
PIN
NAME
SIGNAL
NAME
PIN
NAME
SIGNAL
NAME
Ae
IA1
Be
BYPASS
A5
OENA
B5
DBYAo
A4
DBYA1
B4
DBYA2
A3
GND
B3
Not Used
A2
Not Used
C1
DBYA3
DBYA5
B2
O2
Not Used
DBYA4
B1
01
Not Used
C2
DBYAa
E1
oBYA7
E2
oBYAs
F1
oBYA9
F2
DBYAlO
G1
DBYA11
G2
DBYA12
H1
DBYA 13
H2
DBYA14
J1
DBYA 15
J2
Not Used
Kl
Not Used
L2
Not Used
K2
Not Used
l3
Vee
K3
ClKB
l4
SB 2
K4
SB 1
l5
SBo
K5
IBl
le
IBo
Ke
GND
l7
OENB
K7
DAYB o
ls
DAYB 1
Ks
DAYB 2
19
GND
K9
Not Used
LlO
Not Used
Kll
Not Used
KlO
Not Used
J 11
DAYB3
JlO
DAYB4
Hll
DAYB5
HlO
DAYB e
G 11
DAYB7
G10
DAYB s
Fll
DAYB9
FlO
DAYB lO
Ell
DAYB 11
ElO
DAYB 12
0 11
DAYB 13
010
DAYB 14
C11
DAYB 15
C10
Not Used
Bll
Not Used
A10
Not Used
BlO
Not Used
A9
Vee
B9
ClKA
As
SA2
Bs
SAl
A7
SAo
B7
lAo
4-59
WS59820
ABSOWTE MAXIMUM RATINGS·
*Notice: Stresses above those listed here may cause
permanent damage to the device. This is a stress rating
only and functional operation of the device at these or
any other conditions above those indicated in the
operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods of time may affect device reliability.
Operating Temp.
(Comm'I) ........ O°C to +70°C
(Mil) ........ -55°C to +125°C
Storage Temp. (No Bias) ....... -65°C to +150°C
Voltage on any pin with
respect to GND ............... -0.6V to +7V
Latch Up Protection ................. > 200 rnA
ESD Protection ..................... > ±2000V
DC CHARACTERISTICS
SYMBOL
Over Operating Range (See Notes)
PARAMETER
TEST CONDITIONS
MIN
MAX
VOH
Output High Voltage
Vee = Min.
V IN = VIH or Vil
VOL
Output Low Voltage
Vee = Min.
V IN = VIH or Vil
VIH
Input High Voltage
Guaranteed Input High Voltage
V il
Input Low Voltage
Guaranteed Input Low Voltage
IIX
Input Load Current
Vee
= Max, VIN = GND or Vee
-10
10
loz
High Impedance
Output Current
Vee
= Max, Vo = GND or Vee
-50
50
Icc
Power Supply Current
Vee
= Max
=
NOTES: 1) Commercial: Vee = +SV ± S%. TA
OOC to 7O"C.
2) Military: Vee = +SV ± 10%, TA = -SSoC to + 12SoC.
SWITCHING CHARACTERISTICS
IOH
=
IOl
= 20 rnA Comm'l
= 16 rnA Mil
IOl
I
I
2.4
-6.5 rnA
V
0.5
2.0
V
0.8
O°C to +70°C (Comm'l)
12
-55°C to + 125°C (Mil)
15
3) CL
UNITS
~
rnA
= SO pF except for tOF where CL = S pF.
Over Operating Range (See Notes)
WS59820
PARAMETER
DESCRIPTION
COMMERCIAL
MIN
MAX
MILITARY
MIN
MAX
t po
Clock to Data Out
23
25
tSEl
Mux Select to Data Out
20
22
ts
Input (DataJlnstr.) Set Up
6
6
5
5
tH
Input (DataJlnstr.) Hold
tOF
Output Disable
15
tOE
Output Enable
18
tPWH
Clock Pulse Width High
10
12
tPWl
Clock Pulse Width Low
11
12
UNITS
16
ns
22
teyp
Bypass to Data Out
17
20
toye
Data Via BYPASS
(Data In to Data Out When
BYPASS is Active Low)
13
16
NOTE: Inputs are switching between 0 and 3V with rise and fall times of 1 Vlns and measurements made at 1.SV. All outputs have
maximum DC load.
4-60
WS59820
ORDERING INFORMATION
PART NUMBER
WS59820J
WS59820G
WS59820GMB
SPEED
(ns)
PACKAGE
TYPE
PACKAGE
DRAWING
OPERATING
TEMPERATURE
RANGE
WSI
MANUFACTURING
PROCEDURE
23
23
25
68 Pin PLOCC
68 Pin Ceramic PGA
68 Pin Ceramic PGA
J1
G1
G1
Comm'l
Comm'l
Military
Standard
Standard
MIL-STO-883C
4-61
4-62
WAFERSCALE INTEGRATION,INC.
SECTION INDEX
MILITARY PRODUCTS . ....................................................................... 5-1
For additional information,
call 800-TEAM-WSI (800-832-6974).
In California, call 415-656-5400.
MILITARY PRODUCTS
WAFERSCALE INTEGRA 170N. INC
Waferscale Integration, Inc. (WSI) is committed to supplying products that meet the demands of the Military/Hi-Reliability
marketplace. WSI's very high performance CMOS EPROM (with its patented Split-Gate design) and Logic technology
offers an intrinsic reliability that, when coupled with Military screening and testing, produces an extremely enhanced
and reliable product. All WSI products can be procured fully compliant to Paragraph 1.2.1 of MIL-STD-883C.
The WSI Quality Assurance Program has been designed and implemented to perpetuate and maintain the high
standards needed to repeatedly produce these products. The cohesiveness of the Program is accomplished through
a comprehensive Document Control system that assures the repeatability of the process.
State-of-the-art equipment and techniques are being used extensively throughout Design, Wafer Fabrication, Assembly,
Screening and Testing (Method 5004), and Quality Conformance Inspections (Method 5005) to produce the highest
yields possible with their associated reliability enhancement.
The tables below describe the program in detail. Worthy of notation is the fact that WSI UV EPROMs are subjected
to two 100% data retention tests: one in wafer form (48 hours at 200°C) and the other in finished package form (72 hours
at 140°C). The wafer data retention test, with its high activation temperature, assures data retention problems are
reduced and virtually eliminated.
TABLE I. 100% SCREENING TO METHOD 5004
All product is subjected to the following 100% screening flow. Screening test methods are in
accordance with MIL-STD-883, Method 5004. (Latest issues in effect.)
SCREEN
TEST METHOD/CONDITION
QUALITY
LEVEL
Data Retention (EPROMs Only)
48 Hours at 200°C
Visual and Mechanical
Internal Visual
High.:remperature Storage
Temperature Cycle
Constant Acceleration
Hermeticity
Fine
Gross
5004
2010/Condition B
1008/Condition C
1010/Condition C
2001/Condition 0 or E (Y 1 Axis)
1014
Condition A or B
Condition C
External Visual
2009
100%
Data Retention (EPROMs Only)
72 Hours at 140°C
100%
Burn-In
Pre-Burn-In Electrical
5004
Per Applicable WSI Device Specifications or
Military Drawing. T A = + 25°C.
1015/Condition 0, TA = +125°C Minimum
Burn-In
Final Electrical Tests (See Note 1)
Static (DC)
Functional
Switching (AC)
5004
a) TA = + 25°C, + 125°C, and -55°C
b) Power Supply Extremes
Percent Defective Allowable (PDA)
5004
Paragraph 3.5.1
Quality Conformance Inspection
Sample Selection
5005
See Tables II Through V
External Visual
2009
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
100%
5%
Sample
100%
NOTE: 1. Per applicable WSI device specification or Military Drawing.
5·1
Military Products
TABLE II. GROUP A QUALITY CONFORMANCE INSPECTION
Group A Inspection is performed on each inspection lot per MIL-STD-883, Method SOOS, Table I.
MAXIMUM
TEST (SEE NOTE 1)
Subgroup 1
Static Tests at TA
=
+2SoC
LTPD
SAMPLE
SIZE
ACCEPT
NUMBER
2
266
2
Subgroup 2
Static Tests at Maximum Rated Operating Temperature
3
176
2
Subgroup 3
Static Tests at Minimum Rated Operating Temperature
S
10S
2
Subgroup 4 (See Note 2)
Dynamic Tests at T A = +2SoC
2
266
2
Subgroup 5 (See Note 2)
Dynamic Tests at Maximum Rated Operating Temperature
3
176
2
Subgroup 6 (See Note 2)
Dynamic Tests at Minimum Rated Operating Temperature
S
10S
2
Subgroup 7
Functional Tests at T A
=
2
266
2
Subgroup 8
Functional Tests at Maximum and Minimum Rated Operating Temperatures
S
10S
2
Subgroup 9
Switching Tests at TA
2
266
2
3
176
2
S
10S
2
=
+2SoC
+2SoC
Subgroup 10
Switching Tests at Maximum Rated Operating Temperature
Subgroup 11
Switching Tests at Minimum Rated Operating Temperature
NOTES: 1. Per applicable WSI deVice specification or Military DraWing.
2. Subgroups 4, 5, and 6 are not applicable to WSI products.
TABLE III. GROUP B QUALITY CONFORMANCE INSPECTION
Group B quality conformance tests are performed on each inspection lot in accordance with
MIL-STD-883, Method SOOS, Table lib.
TEST
TEST
METHOD
TEST CONDITIONS
QUALITY LEVEll
MAXIMUM ACCEPT
NUMBER
Subgroup 1
Physical Dimensions
2016
Per WSI Outline Drawing and
Appendix C of MIL-M-38S10
2 Devices (No
Failures)
Subgroup 2
Resistance to Solvents
201S
4 Chemical Solutions
4 Devices (No
Failures)
Subgroup 3
Solderability
2003
Soldering Temperature of
+24SoC ± SoC
LTPD 10/Accept = 2
38 Leads From 3
Devices Minimum
2014
Failure Criteria Based on Design and
Construction Requirements of WSI
Specification
1 Device (No
Failures)
Subgroup 4
Internal Visual and
Mechanical
(Table III Continued on Next Page.)
5-2
Military Products
TABLE III. GROUP B QUALITY CONFORMANCE INSPECTION (Cont.)
Group B quality conformance tests are performed on each inspection lot in accordance with
MIL-STD-883, Method 5005, Table lib.
TEST
Subgroup 5
Bond Strength
Ultrasonic or Wedge
Subgroup 6
Internal Water Vapor Content
Subgroup 7
Seal
Fine
Gross
TEST
METHOD
TEST CONDITIONS
QUALITY LEVELl
MAXIMUM ACCEPT
NUMBER
2011
Condition C or D
LTPD 15/Accept = 1
34 Bonds From 4
Devices Minimum
1018
This Test is Not Performed by WSI.
WSI Packages Do Not Contain
Dessicants.
3 Devices, 0 Failures
or 5 Devices,
1 Failure
1014
LTPD 5/Accept = 2
Condition A or B
Condition C
Subgroup 8
Electrostatic Discharge
Sensitivity Classification
3015
Unless Otherwise Specified, This Test
Will be Performed for Initial Qualification of New Product or Redesign.
LTPD 15/Accept = 0
TABLE IV. GROUP C QUALITY CONFORMANCE INSPECTION
Group C quality conformance tests are performed on inspection lots every 52 weeks in accordance
with MIL-STD-883, Method 5005, Table III.
TEST
Subgroup 1
Steady-State Life Test
TEST
METHOD
1005
Condition D, 1000 Hours at TA = 125°C
or Equivalent
Per WSI Specification or Military Drawing
1010
2001
1014
Condition C
Condition D or E
End-Point Electrical
Subgroup 2
Temperature Cycling
Constant Acceleration
Hermeticity
Fine
Gross
Visual Examination
End-Point Electrical Parameters
TEST CONDITIONS
QUALITY LEVELl
MAXIMUM ACCEPT
NUMBER
LTPD 5/Accept = 2
LTPD 15/Accept = 2
Condition A or B
Condition C
1010 or
1011
Per WSI Specification or Military Drawing
5-3
Military Products
TABLE V. GROUP D QUALITY CONFORMANCE INSPECTION
Group D quality conformance tests are performed on inspection lots every 52 weeks in accordance
with MIL-STD-883, Method 5005, Table IV.
TEST
Subgroup 1
Physical Dimensions
Subgroup 2
Lead Integrity
Hermeticity, Fine and Gross
Subgroup 3
Thermal Shock
Temperature Cycling
Moisture Resistance
Hermeticity, Fine and Gross
Visual Examination
TEST
METHOD
2016
2004 or
2028
1014
1011
1010
1004
1014
1004,
1010
End-Point Electrical Parameters
Subgroup 4
Mechanical Shock
Vibration, Variable Frequency
Constant Acceleration
Hermeticity, Fine and Gross
Visual ..Examination
End-Point Electrical Parameters
QUALITY LEVELl
MAXIMUM ACCEPT
NUMBER
TEST CONDITIONS
Per WSI Outline Drawing and
Appendix C of MIL-M-38510
LTPD 15/Accept
=2
Test Condition 82 (Lead Fatigue) or D
LTPD 15/Accept
=2
LTPD 15/Accept
=2
LTPD 15/Accept
=2
=2
Condition A or 8 and C
Condition 8 Minimum
Condition C Minimum
Condition A or 8 and C
Per WSI Specification or Military
Drawing
2002
2007
2001
1014
2009
Condition
Condition
Condition
Condition
8
A
D
A
Minimum
Minimum
or E
or 8 and C
Per WSI Specification or Military
Drawing
Subgroup 5
Salt Atmosphere
Hermeticity, Fine and Gross
Visual Examination
1009
1014
1009
Condition A Minimum
Condition A or 8 and C
LTPD 15/Accept
Subgroup 6
Internal Water Vapor
1018
5,000 ppm Maximum Water Content
at 100°C
3 Devices, 0 Failures
or 5 Devices, 1 Failure
Subgroup 7
Adhesion of Lead Finish
2025
Subgroup 8
Lid Torque
2024
LTPD 15/Accept
As Applicable to Glass-Frit Packages
=2
LTPD 15/Accept = 0
WSI supports the Standardized Military Drawings (SMD) program sponsored by DESC (Defense Electronics Supply Center)
and has submitted Certificates of Compliance for the following products:
MILITARY DRAWING NO.
WSI PART NO.
ESTIMATED DESC
PUBLICATION DATE
85102
5962-87661
5962-87063
5962-87515
5962-87650
WS27C64F
WS27C128F
WS27C256F
WS57C49 and WS57C498
WS57C191 and WS57C291
Late 01, 1988
Available Now
Late 01, 1988
Late 01, 1988
Available Now
NOTE: Compliant MIL-STO-883C products are marked with the letter "C" preceding the date code.
5-4
Military Products
When Military Drawings are not available for new, state-of-the-art products offered by WSI, WSI makes available its
own version of a Military Drawing composed and formatted like a DESC SMD for ease of recognition. A sample of
a WSI Military Drawing is depicted below. These can be obtained from a WSI sales office or authorized representative.
RnlSION HISTORY
Rn·
. '••NAT_"5
ECII"
IljlTE
f562
11121117
DESCRIPTION
SI"'''TUIIE 011
fiLE IN D.C.
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- - - - - - - - - - - - - -
Al'Y
P".
P".
ORIGINA IT SPECifiC ... nON
I
2
3
4
15
22 23
24
25
6
7
Al'Y
21
26 27
-
Wt:1FEr./C1:1 L-E
........
MM.
• •
10
28 29 30
TInE:
472eO '''TO _ . _ _ T. CA 945lIII
WSI MILITARY DRAWING
12
13
14 15
16
17
I.
I.
20
31 32
lI3
34 35
36
37
lie
n
40
ItICIlOCIRCUIT. _ITAI.. CtIOS. llik x.
(131.072 aln. W OIASAIII.£ ........
_ITHlC_1CCIII
_110,
WSS7C128F
CAGE CODE: 66579
PA. IOf 14
WSl's MIL-STD-883C COMPLIANT FAST EPROMs AND RPROMs
PART
NUMBER
WS57C191
WS57C291
WS57C43
WS57C43B
WS27C64F
WS57C49
WS57C49B
WS57C64F
WS27C128F
WS57C51
WS57C51B
WS57C128F
WS27C256F
WS57C256F
ARCHITECTURE
2K
2K
4K
4K
8K
8K
8K
8K
16K
16K
16K
16K
32K
32K
x
x
x
x
x
x
x
x
x
x
x
x
x
x
8
8
8
8
8
8
8
8
8
8
8
8
8
8
TYPE
RPROM
RPROM
RPROM
RPROM
EPROM
RPROM
RPROM
EPROM
EPROM
RPROM
RPROM
EPROM
EPROM
EPROM
28 PIN
32 PIN
24 PIN
FASTEST
0.300"
0.600"
CERAMIC CERAMIC CERAMIC MILITARY
CERDIP CERDIP
FLATPACK
CLLCC
CLLCC
SPEED
24 Pin
24 Pin
24 Pin
24 Pin
24
24
28
24
24
28
28
28
28
28
28
28
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
Pin
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
50
50
70
45
90
70
45
70
90
70
45
70
90
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5-5
5-6
WAFERSCALE INTEGRATION, INC.
WSI ASIC
6
SECTION INDEX
THE SHORTEST PATH FROM SYSTEM CONCEPT TO MARKET: WSI ASIC ............................. 6-1
User-Configurable Products ................................................................... 6-1
Microprogrammable Controller (PAC™) .......................................................... 6-2
Stand-Alone Microsequencer (SAMTM) ........................................................... 6-8
Cell-Based Custom Design Capability .......................................................... 6-11
For additional Information,
call 800-TEAM-WSI (800-832-6974).
In California, call 415-656-5400.
-----==
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== J:::~
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=:""'Ii-ii=Ii-ii-=
~~
WSI ASIC
WAFERSCALE INTEGRA TION, INC.
THE SHORTEST PATH FROM SYSTEM CONCEPT TO MARKET
WSI supports the needs of high-performance system designers and provides them with the edge they need to survive
and grow in today's competitive marketplace. WSI has positioned its organization and product portfolio to address
the most important needs concerning today's system designer:
-
Quick market entry
Higher integration
-
Lower power consumption
-
Higher system performance
WSI offers very high performance integrated circuit products that combine nonvolatile memory with macro logic functions
that result in "board-level" replacement circuits. Whether supplied as off-the-shelf product or customized for customer
needs, WSI can deliver this capability quickly. This makes WSI unique among semiconductor companies.
High-Performance EPROM Core
At the core of this capability lies WSI's high-performance CMOS EPROM technology. This technology has proliferated
into families of market leading EPROMs and bipolar PROM replacement products ... memory products that feature
bytewide and wordwide architectures, speeds as fast as 35 ns, and bit densities climbing to the 1 Mbit level. These
fast nonvolatile memory products are described in this catalog.
User-Configurable Product Families
WSI continues to build on its EPROM core technology. Configured as EPROM macro cells in the WSI custom cell
library, this high performance nonvolatile memory capability has been combined with other large functional CMOS
macro cells, fast static RAM cells, fast multipliers, and random logic blocks to produce very fast programmable offthe-shelf circuits to address the above market needs. These families of high-performance user-configurable products
are programmable by the user to suit particular system requirements. These products are supported by a complete
system development environment that includes software and hardware development tools for use during evaluation,
program development and debug.
The first user-configurable CMOS products offered by WSI are:
-
The PAC™ family of Microprogrammable Controllers
-
The MAp™ family of Mappable Memory Products (described in this databook)
-
The SAM™ family of Stand Alone Microsequencers
Rapid System Design
These user-configurable programmable products provide system designers with the ability to quickly try new concepts
or designs. With the development tools, system designers are free to fashion new products that combine new features
and increased performance within the confines of their own development laboratory. When incorporated into a system,
the new WSI user-configurable products deliver high levels of integration and exceptionally high system performance.
Custom Products for Custom Needs
But this is not where WSI's capabilities end. For customers who have special needs, WSI will customize its standard
products by modifying them to suit particular customer requirements. In addition, WSI will work with its customers
to define and produce completely customized integrated circuits that take advantage of WSI's high performance memory
and logic capabilities. WSI has a proprietary CAD/CAE design system and library of macrocells in place to guide
its customers from the earliest system conceptual stages through prototyping and into production.
6-1
WSI ASIC
User-Configurable Product Applications
The new WSI user-configurable product families are expanding the range of choices for today's system designers
who prefer to use low risk off-the-shelf products during the system prototyping and production stage. The Microprogrammable Controller PAC™ family provides high performance system solutions in a variety of applications
ranging from the interface of a microprocessor to a high-speed system, fast stand-alone system controllers, highspeed graphics processors or replacement of bit-slice engines. The PAC™ family is ideal for applications such as
address generation (both for instruction and data requirements), bus interface and control, fast arithmetic element
controllers and DSP algorithm controllers.
THE WSPAC116 PROGRAMMABLE CONTROLLER
The first product in the PAC™ family is the WSPAC116, a single chip 20 MHz programmable controller that consists
of a peripheral interface, 1K x 64 program store EPROM, a 16-bit instruction/data port, a 16-bit ALU, eight general
purpose individually programmed I/Os, up to 4M words of addressing capability, eight high-speed program test conditions and four interrupts. The following provides information on the PAC™ controller architecture, features and
capabilities. Please refer to the WSPAC116 product data sheet for detailed parameters or contact your WSI sales
representative for additional information.
5910 SEQUENCER
WITH 15 DEEP STACK
~---------------,
THE WSI WSPAC116 CIRCUIT REPLACES A PC BOARD WITH THE ABOVE COMPONENTS
USER BENEFITS
• 100% faster than conventional microprocessor implementation
• 20 MHz clock operation (50 nsec cycle times)
• Military operation rated at 15 MHz (75 nsec cycle times)
• 50-to-1 PC parts count reduction
• 20x less power
• 5x lower cost
6-2
WSI ASIC
WSPACl16 CONFIGURATION
4{VCC
CC TEST
/
8
"-
/
INTERRUPTS
"
4
<
"
<
A
MEMORY/ADDRESS
MEMORY DATA
/
6
/
16
7
WSPAC116
0
Z8
"
16
"I/O
v
ADD/DATA
v
CONTROL
16
v
CS
RD
WR
RESET
CCLK
5{GND
WSPAC116 FEATURES
•
Dual mode of operation
- Stand-alone controller
- Microprocessor peripheral interface
- 16-bit microprocessor interface
- 8 word instruction/data queue
• Very high performance for real time control
- 20 MHz instruction execution rate (single instruction per cycle)
- 20 MHz output port and address bus
• Advanced 16-bit controller architecture
- 59016A 16-bit ALU
- 59010M 12-bit sequencer with 15 deep stack
- 32 x 16 register file
- 22-bit memory address bus
- Interrupt controller
• High performance reprogram mabie memory
- 1K x 64 EPROM
• Dual I/O ports
- 16 real time control output lines
- 8 bidirectional I/O port
• High level program development tools
Macro assembler with "en like syntax
Functional simulator
Memory programmer
Debug facilities
6-3
WSI ASIC
WSPAC116 FUNCTIONAL SLOCK DIAGRAM
Ifj lfi! I~
SERIAL
IN/OUT
15 DEEP
STACK
16 BIT
BLOCK
COUNTER
BREAKPOINT
SINGLE STEP
SCAN IN
SCAN SEl
SCAN ClK
SCAN OUT
FLAG BUS
F (15:0)
6-4
I/O (7:0)
ADD (15:0)
WSI ASIC
MEMORY
ADDRESS BUS
MICROPROCESSOR
• 80286
• 80386
• 68020
DATA BUS
INTERRUPT
t
CONTROL
HANDSHAKE
SIGNALS
•
FAST SYSTEMS
• BUSSES
• GRAPHICS
• ETC.
PAC'·
1/0
STATUS
HIGH SPEED CONTROL
LOW SPEED CONTROL
PAC™ PRODUCT DELIVERS REAL TIME, HIGH-SPEED CONTROL
• Application program stored in the 1K x 64 on-board EPROM
• Standard peripheral interface link between host microprocessor and PAC™ product
• PAC™ product executes the application program, controls and monitors the fast system and generates
addresses to memory in real time
• Handshake protocol between the host and the PAC™ circuit is done through the 8-bit I/O port
MICROPROCESSOR
SYSTEM
ADDRESS (Ao_s)
"WSPAC116
A
DATA (Do-,s)
ADDRESS DECODING
cs
RD
WR
CS
A
rv
rv
AD (2:15)
"v
1/0 (2:7)
ADDRESSIDATA TO SLAVE
"INPUTIOUTPUT
v
RD
WR
INTERRUPT
1/00
HOLD
I/O,
HLBA
CLo
CC'_7
CONDITION CODES
"
INT (0:3)
INTERRUPTS
"
WSPAC116 PROVIDES A STRAIGHT-FORWARD BUS INTERFACE TO MICROPROCESSOR
• Simple host connections
• Interfaces like a peripheral
• 16-bit data bus for data and command transfer to WSPAC116
• 6-bit address bus for accessing internal WSPAC116 resources
• Standard CS, RD, and WR controls
• Handshake performed through I/O ports
6-5
WSI ASIC
cs
I
ADDRESS
ADDRESS RAM
WR
MICROPROCESSOR
SYSTEMS
WR_
OE
16
RD
DATA
f16
, 6
DATA
t
!
CONTROL
f
I
FLOATING POINT
PROCESSOR
• WEITEK
• AMD
• TI
• AD
BUS REQ.
WSPAC116
BUS ACK.
INTR. REO,
STATUS
t
INTR. ACK.
PACTIII CIRCUIT EXTENDS THE NUMBER CRUNCHING CAPABILITIES OF HIGH-SPEED
FLOATING-POINT PROCESSOR SYSTEMS
• Direct floating-point unit interface from WSPAC116
• Peripheral interface to microprocessor
• Direct access to memory for data loading/storing from/to floating-point processor
• Matrix multiplication of 4 x 4 matrices with data access in 4 ~sec
cs
I
RAM
ADDRESS
ADDRESS
16
WR
WR OE
MICROPROCESSOR
SYSTEMS
DATA
I I
J
RD
1-- 6
1
16
~
L-\
i
r-
BUFFER
t
BUS REQ.
BUS ACK.
DATA
WSPAC116
-~
INTR. REQ.
VME
BUS
BUFFER
~
j
CONTROL
9
INTR. ACK.
BR. BBSY, BERR
WRITE, LWORD, lACK
DSo, DS,
t
I
BUFFER
BUS GRANT, AS, DTACK, BERR
J
PAC TIII INTERFACES A HOST MICROPROCESSOR TO A HIGH-SPEED BUS
• Performs bus protocol
• Data transfer to/from the microprocessor bus to/from a fast bus (like VME or Multibus)
• Transfer rate of up to 20 Mbyte/sec
6-6
I.
'"
7
WSI ASIC
MAGICPRO"
PROGRAMMER
PACASM"
WISPER"
= WSI INTEGRATED SOFTWARE
AND -PROGRAMMING
gNVIBONMENT
PACT'" SYSTEM DEVELOPMENT TOOLS ARE USER FRIENDLY
• PACASM™ • PACSIM™ • MagicPro™ -
High level program entry
Logic simulator
IBM PC© hardware compatible programmer
6-7
WSI ASIC
WS444/WS448 STAND-ALONE MICROSEQUENCERS (SAMTM)
The third family of WSI's user-configurable products is known as STAND-ALONE MICROSEQUENCERS or SAM™S.
These products are fully-integrated CMOS VLSI microsequencers designed to provide an efficient vehicle for the
implementation of state machines and microcoded controllers. High performance on-chip EPROM memory (up to
448 words) is integrated with a microcode sequencer consisting of Branch Control logic, Stack and Loop Counter.
Eight general-purpose inputs feed the Branch Control logic along with current state information. The Branch Control
logic gives flexible multi-way microcode branch capability in a single clock, enhancing throughput beyond that of
conventional controllers or sequencers. The generiC microcoded architecture fits a wide range of applications spanning
the spectrum from basic state machines to traditional bit-slice controller applications.
Two versions of the SAM™ architecture are initially available. The number of output pins and packaging are the key
differences. The WS444 has 12 user-definable outputs, while the WS448 has 16. The SAM™ products are packaged
in either DIP or JLCC/PLCC chip carrier packaging to maximize circuit board flexibility. One.:rime-Programmable (OfP)
plastiC versions of the SAM™ products are available to minimize volume production costs.
WSI's world-class EPROM technology makes the microcode user-configurable and, in windowed packages, erasable.
The products feature a combination of low CMOS power and greater than 20 MHz performance. Designing with the
SAM™ products is eased through the use of WSI's MagicPro™ Programmer and SAM+PLUS™ Development Software. This software supports efficient microcode generation through high-level state machine entry and assembler
microcode compilation.
Ideal application areas for the SAM™ architecture include programmable sequencer generators, bus and memory
controller functions, graphics and DSP algorithm controllers, and other complex, high performance machines.
For additional information, please refer to the WS444IWS448 product data brochures available from your WSI sales
representative.
SAM™ DEVICE CONFIGURATION
NRESET
INPUTS
8
"
0
12 (16)
"-
v
OUTPUTS
ClK
6-8
WSI ASIC
WS44X SAM BWCK DIAGRAM
NRESET
INPUTS
(8)
-
I
I
ZERO
BRANCH
CONTROL
lOGIC
"
rV
+
CREG
.("
-
-
AD~
448 x 36
BITS
---v'
~~~7
I
MICROCODE
EPROM
STACK
II
1
15 x 8
'()'
PIPELINE
REGISTER
L.-
-
ouITPIUTS~-
I I
+i
ClK
WS444
16 - WS448
SIMPLE ARCHITECTURE ENHANCES CAPABILITIES
• On-chip reprogram mabie EPROM microcode memory up to 448 words deep
• 15 x 8 stack
• Loop counter
• Single clock, multi-way control branching
m
• 8 general-purpose branch control inputs
• 12 (WS444) or 16 (WS448) general-purpose control outputs
WS44X CASCADING
INPUTS
INPUTS
-v
WS44X
INPUTS
N
1----_-ClOCK
N
CONTROL
OUTPUTS
(N)
WS44X
WS44X
CLOCK ----< ........
WS44X
!L
INPUTS
VERTICAL CASCADE
CONTROL OUTPUTS (2N)
HORIZONTAL CASCADE
WSI SAM™ PRODUCT CASCADING BENEFITS
• Greater output fanout flexibility in horizontal cascaded mode
• Increased memory depth provided by vertical cascade implementation
• Cycle-by-cycle output enable control provides smooth device to device control transfer
6-9
WSI ASIC
MAGICPRO"
PROGRAMMER
WISPERm = WSI INTEGRATED SOFTWARE
AND -PROGRAMMING
gNVIBONMENT
WS/'s DESIGN DEVELOPMENT SOFTWARE SIMPLIFIES DESIGN ENTRY
• Development tools supported by WSI's MagicPro™ development environment
• System supports If.:rhen-Else Constructs or Truth Table Entry
• Functional simulator provides simulation capabilities for the SAM™ products
6-10
WSI ASIC
CELL-BASED CUSTOM DESIGN CAPABILITY
WSI's cell-based custom library offers the ability to modify or customize an existing standard or programmable product.
Hence, when WSI's users are ready to move from the prototyping stage to full production, a path exists to accomplish
the task.
The WSI cell-based custom library contains traditional SSI "glue" cells, soft macros (TTL-equivalent functions without
fixed layout), and proprietary macro cells. The list of macro cells includes such functions as ALU's, sequencers,
multipliers, register files, counters, FIFO's, barrel and funnel shifters, and memory arrays of ROMs, SRAMs and
EPROMs.
Integration of WSI's CAD and macro cell library onto a flexible system development platform provides the user with
a unique capability to quickly respond to market changes. For example, a custom cell-based design enables easy
incorporation of known test patterns from other macro cell-based designs. The test patterns from the standard products can be incorporated into the larger test programs for the cell-based custom design. This provides obvious benefits:
1) Reduced test program development time
2) Expected timing values are known
3) Error-free test patterns
READY
GRANT
INTERRUPTS
"---RESET
TYPICAL WSI CELL-BASED CUSTOM SINGLE CHIP APPLICATION
ON-CHIP EPROM DELIVERS FLEXIBILITY AND HIGH PERFORMANCE
• User-configurable functions
• Security protection bits available
• WSI on-chip EPROM insures high system performance
• On-board macro-elements enable system speeds as fast as 50 nsec per instruction
• Minimizes PC board space by replacing over 50 standard logic and memory devices
• Constructed using verified macro cell functions
6-11
6-12
WAFERSCALE INTEGRA nON, INC
SECTION INDEX
QUALITY AND RELIABILITY . .................................................................. 7-1
For additional information,
call 800-TEAM-WSI (800-832-6974).
In California, call 415-656-5400.
irEE ::~
--r =: == == IIIJII _________________________________
~
=r~~E
WAFERSCALE INTEGRA110N, INC.
QUALITY STATEMENT
WaferScale Integration, Inc. is committed to
producing and delivering defect-free products
and services that meet or exceed the specified
requirements. We are dedicated to a system
of defect prevention and an attitude of zero
defects through management example.
The management of WaferScale Integration,
Inc. pledges this to you ... our CUSTOMER.
7·1
7-2
QUALITY AND RELIABILITY
WAFERSCALE INTEGRA110N, INC.
QUALITY & RELIABILITY PROGRAM
INTRODUCTION
The Quality & Reliability (Q & R) Program at WSI is intended to comply with the latest requirements of: MIL-I-45208,
"Inspection System Requirements;" MIL-Q-9858, "Quality Program Requirements;" and Appendix A of MIL-M-38510,
"Quality Assurance Program."
The task of the Q & R Program is to assure that all delivered products conform to the requirements of each order
placed with the company and to drive the quality and reliability improvement process to optimize product performance
and market acceptance.
In order to support the above, WSI has organized its Q & R Department into four main sections:
1 . 0 Quality Control (QC) 1.1 QC Engineering support.
The main functions of QC are:
To provide the Quality Control function and the manufacturing function with technical
1.2 Materials Quality Control - Assures that all raw materials used in the manufacture of the final product
meet WSI specified requirements.
1.3 Process Quality Control - Assures that all WSI manufacturing processes are within their specified control
limits and that in-process product maintains the highest quality level.
2.0
Quality Assurance (QA) -
The main functions of QA are:
2.1 QA Engineering - To provide a factory interface for customers on all field returns and corrective action
requests; to provide technical assistance to other QA functions and engineering functions in matters of
product quality.
2.2 QA Inspection - To assure that the final product meets the internal product specifications, applicable
customer specifications, and/or other contractual requirements.
2.3 Calibration - To provide a function that assures all equipment used to test or accept product is properly
calibrated at set intervals to assure product quality.
3.0
Reliability -
The main functions of Reliability are:
3.1 Reliability Engineering (RE) - To assure that all manufactured products reflect the highest reliability standards and to measure this with in-house programs to compare against these standards; to provide technical
assistance to other engineering functions in matters of product reliability; to prepare and execute Qualification plans for new or revised designs, packages and processes.
3.2 Reliability Test Lab - To provide suitable step/stress facilities in-house, or at an appropriate vendor, for
the purpose of conducting qualifications or quality conformance inspections.
3.3 Failure Analysis Lab - To provide and maintain a Failure Analysis function in-house, or at an appropriate
vendor, for the purpose of investigating the cause(s) of failure(s) and for their systematic elimination from
the product.
4.0
Configuration Control -
The main functions are:
4.1 Document Control- To provide an organized, systematic function for originating, changing and distributing
internal specifications and drawings; to provide for the prompt notification of changes to customers with
Change Notification Requirements.
4.2 Audits - To provide a system for periodically checking WSI's and vendor's quality programs for compliance
with stated policies, procedures and contractual requirements.
4.3 Specification Review and Writing - To provide a function for reviewing customer documentation and converting those requirements to in-house requirements.
5.0
For detailed coverage of WS/'s total Q & R System, write or call for our "Quality &
Reliability Policy Manual."
7-3
Quality and Reliability
QUALITY
What Is Quality?
Quality is something we all strive for, but seem at a loss to define simply. At WSI we have chosen to adopt Phil
Crosby's definition because it is the simplest and to-the-point.
Quality Is: "Conformance to the requirements."
Quality is not relegated only to the state of the product. It encompasses all administrative areas also. At WSI we strive
for zero defects and our programs are geared to attain this.
Product Flows
WSI offers four standard product flows which are shown below:
1.0
Flows
883
Class B
MiI.:remp
Standard
Standard
2.0
Packages
Hermetic
Hermetic
Hermetic
Plastic
3.0
Operating Temperature Range
Military
-55°C to +125°C
Commercial
O°C to 70°C
SCREENS &
MIL-STD-883 METHOD/CONDITION
INSPECTIONS
OR WSI REQUIREMENT
883
M2010/Condition B
100%
N/A
N/A
N/A
N/A
100%
100%
100%
MIL-TEMP
STANDARD STANDARD
4.0
Preseal
Inspection
WSI Requirement
5.0
Stabilization
Bake
M1008/Condition C
24 Hours at + 150°C
100%
N/A
N/A
N/A
6.0
Temperature
Cycle
M1010/Condition C
10 Cycles, -65°C to +150oC
100%
N/A
N/A
N/A
7.0
Constant
Acceleration
M2001/Condition D or E
Y1 :20K Gs or 30K Gs
100%
N/A
N/A
N/A
8.0
8.1
8.2
Hermeticity
Fine Leak
Gross Leak
M1014/Condition A or B
M1014/Condition C
100%
100%
100%
100%
100%
100%
9.0
Data Retention Packaged Parts - 72 Hours at 140°C
(EPROMs only) Wafers - 48 Hours at 200°C
100%
N/A
N/A
N/A
N/A
N/A
100%
100%
100%
100%
10.0
Pre Burn-In
Electricals
Per Applicable Data Sheet
100%
N/A
N/A
N/A
11.0
Burn-In
M1015/Condition A or D
160 Hours at +125°C or Equivalent
100%
N/A
N/A
N/A
12.0
Post Burn-In
Electricals
Per Applicable Data Sheet
100%
N/A
N/A
N/A
13.0
% Defective
Allowable
M5004, Paragraph 3.5.1
5%
N/A
N/A
N/A
14.0
Final
Electricals
Per Applicable Data Sheet
100%
100%
100%
100%
15.0
Quality
Conformance
QCI per M5005/Group A
Sample
Sample
Sample
Sample
16.0
External *
Vision
100%
100%
N/A
N/A
N/A
N/A
100%
100%
17.0
Quality
Conformance
QCI per M5005/Group B, C and D
Sample
N/A
N/A
N/A
18.0
Shipping
Inspection
Every Shipment
100%
100%
100%
100%
M2009
WSI Requirement
'WSI ships Visual and mechanical crltena to a 1.0% AQL.
7-4
---=' ==., ==EE
.........
- --
. - . - ..-..--
-
...,
QUALITY AND RELIABILITY
---==I11III
r'-'~"'_
~~.-.-
WAFERSCALE INTEGRATION, INC.
RELIABILITY
INTRODUCTION
RELIABILITY PREDICTION
WSI is committed to serving its customers with the most
reliable products available. From the onset, products are
designed, manufactured and tested to rigorous WSI
standards which culminate in devices that are differentiatedly better in performance and reliability.
The life expectancy of an integrated circuit can be accelerated by both temperature and voltage. At WSI, both
are used extensively in assessing product reliability.
RELIABILITY GOALS
The failure rate for any integrated circuit has been
classically described as having a "bathtub" curve (see
Figure 1). The "bathtub" curve shows three main stages
of a product's life: 1) A very high failure rate in the beginning, known as the infant mortality period, which normally
represent the first 300 hours in a system. 2) A constant
failure rate period, with relatively few failures, known as
the intrinsic failure rate or useful life. This period
represents the next 20 years or more of operation. 3)
Eventually, the devices enter the wearout region where
failures begin to occur very rapidly again. The mean time
to failure for wearout is >20 years.
Temperature
For many years, temperature had been known to be an
accelerator of various types of failure mechanisms. By
increasing the temperature, it was observed that the
devices took less time to fail. By elevating the temperature, long term reliability data can be collected in a
relatively short time. Failure rate calculations are based
upon data collected from accelerated life testing.
The temperature dependence on accelerating failures
has been shown to be exponential. The acceleration
factor between two temperatures can be calculated by
using the Arrhenius equation:
A = Exp -Ea ( - 1
k
T,
T2
k
Ea
- ~2)
= Application Junction Temperature
= Accelerated Stress Junction Temperature
= 8.62 X 10- 5 eV/oK
= Thermal Activation Energy
Each failure mechanism is accelerated differently by
temperature. The thermal activation energy is a constant
which adjusts for the temperature dependence for the
various failure mechanisms. The following activation
energies are used for each failure mechanism:
INTRINSIC
TIME
Figure 1 -
T,
Bathtub Curve
Failure Mechanism
WSI has established the following Reliability Goals at
TA = 55°C:
• Infant Mortality
• Intrinsic Failure
Rate
• Wear Out
0-300 Hours
300 Hours20 Years
";;0.1%
";;100 FITs
0.3 eV
Masking Defects
0.5 eV
Assembly Defects
0.5 eV
Bulk Silicon Defects
MTTF >20 Years
In order to meet the infant mortality goal of 0.1%, an appropriate burn-in screen may be implemented. Data collected on 10,000 EPROMs, from various wafer fab runs,
showed the failure rate to be 0.23% during the first six
hours of burn-in which then dropped to 0.02% over the
next 21 hours. This demonstrated that a proper burn-in
(150°C, 6.5V) for six hours was sufficient to lower the
failure rate to less than 0.1%. This screen is revisited
on a periodic basis to determine whether or not it is
continuing to meet the stated goal. Similar data is collected when a new process is released to production.
Activation Energy (Ea)
Oxide Defects
Electromigration
0.5 eV
0.5-0.9 eV
Charge Loss
0.6 eV
Contami nation
1.0 eV
Voltage
Oxide defects are more highly accelerated by voltage
than by temperature (note the low activation energy for
oxide defects). To obtain a higher acceleration for oxide
defects during a lifetest, the supply voltage is increased
by 6.5 volts when possible. By increasing the supply
voltage, an additional acceleration of 55x is obtained for
oxide defects.
7-5
Quality and Reliability
FAIWRE RATE CALCULATIONS
Failure rate calculations are based on a summary of the
life test results. Typically, the failure rate is calculated for
a family of devices manufactured on a given process. To
calculate a failure rate, the acceleration factor for each
activation energy must be calculated between the
accelerated stress temperature and the application
temperature. Junction temperatures are used rather than
ambient temperatures. The junction temperature is the
temperature at the die surface due to the heat generated
by the device itself. The junction temperature is the
product of the power dissipation multiplied by the thermal
resistance of the package and is then added to the
ambient temperature.
TJ = TA + (GJAl(P); where P = (lccl(Vccl
The next step is to calculate the number of accelerated
device hours from the lifetest data. The number of device
hours is the product of the sample size multiplied by the
hours of the lifetest. The equivalent device hours for each
activation energy is calculated by multiplying the device
hours by the acceleration factor. The failure rate for each
activation energy is computed by dividing the total
number of failures with the same activation energy by
the equivalent device hours. Typically a 60% confidence
level is used for calculating failure rates. The total failure
rate is the summation of all the failure rates for each activation energy. The failure rate is expressed in FITs which
is the number of failures per 109 device hours:
Failure Rate =
L
F(E a , 60% UCL)
A(Ea, T 1 , T2) x 0
x 109 FITs
F(Ea, 60% UCL) = 1.049 (Failures with same Eal + 1.0305
A(Ea, T 1, T2) = Acceleration Factor
o = Device Hours
RELIABILITY DATA SUMMARY
The Reliability Data Summary is a quarterly publication
which presents all WSI reliability data and is available
to WSI customers. The data is presented with the test
results at each timepoint with accompanying failure
analysis where applicable. In this manner, the customer
can compute the failure rate for his own application. For
convenience, the failure rates have been computed to
55°C using the previous method discussed.
Current life test results show a failure rate of 40 FITs at
55°C on EPROMs with a density of 64K and higher. This
data was computed from approximately 5 million device
hours. The failure rate for Bit Slice products was approximately 130 FITs after 1.4 million device hours.
PRODUCT RELIABILITY
ElectroStatic Discharge Sensitivity (ESDS)
WSI products are tested for ESOS in accordance with
Method 3015 of MIL-STO-883. All devices exhibit an
7-6
ESOS greater than 2,001 volts with typical inputs beginning to fail around 5,000 volts and outputs in the range
of 3,000 to 4,000 volts. Testing is performed on new products or when changes occur that can influence the ESOS
of a device (Le., redesign, new process, etc.).
LatCh-Up
Latch-up is a condition that occurs due to excessive current (spikes) in the circuit periphery and creates a large
potential that triggers a parasitic SCR inherent to all
CMOS processes. Latch-Up can be destructive to the
device. To reduce latch-up, WSI employs an epitaxial
layer above a low resistivity substrate. This diverts the
current to the substrate, away from the active circuitry,
reducing the lateral potential which triggers the latch-up.
WSI products are tested for latch-up between -1.0 and
+ 7.0 volts with currents up to 200 mA forced on any
one pin.
Qualifications
All new processes, major process changes, or new
design rules must pass a reliability qualification. One to
three lots are used depending on the reliability risk
involved. Qualification requires a minimum 1000-hour life
test at 125°C. EPROMs are stressed dynamically at
150°C with an overvoltage condition of 6.5 volts. (The
overvoltage accelerates oxide defects an additional 55x.)
Qualifications place heavy emphasis on the first 48 hours
(infant mortality) of the life test. Larger sample sizes are
used initially with the number decreasing as the qualification progresses. If other reliability stresses are to be used
in the qualification, those units will receive a 48-hour
burn-in prior to starting those stresses in order to
eliminate any unrelated failures.
Bit Slice and EPROM products basically run on the same
fab process with the Bit Slice products lacking the steps
for the EPROM cell. Because of the common proceSSing
between the two product lines, more emphasis is placed
on performing reliability studies on EPROMs. The
peripheral circuitry of the EPROM, decoders, I10s, etc.,
have the identical design rules as the Bit Slice products.
Every reliability evaluation on an EPROM product also
evaluates the Bit Slice product line. Testing and failure
analysis is easier on an EPROM. Because of the large
availability of EPROM burn-in boards, larger sample
sizes can be used. Also, the straightforward operation
of an EPROM allows 100% dynamic stressing during
burn-in at a higher temperature and voltage.
EPROMs are subjected to special qualification requirements to study the data retention characteristics of
the EPROM cell. These devices are programmed with
a 100% zero pattern and then baked at 150°C, 200°C,
and 250°C for 1000 hours. These tests are performed to
insure that WSI reliability goals have been met.
Other tests include Temperature Cycle from -65°C to
+150oC for 1000 cycles. In addition, plastic packaged
products must pass 1000 hours of Temperature Humidity
Quality and Reliability
Bias at 85°C and 85% relative humidity, and 168 hours
of Pressure Pot at 15 PSIG.
EPROMs
Because of the floating gate storage cell, EPROMs have
unique reliability considerations. Data retention is related
to the ability to store a charge on the floating gate of the
EPROM cell. Charge loss can shift the threshold of the
EPROM cell from a programmed state to an unprogrammed state, i.e., from a logical 0 to a 1. Charge loss
is the result of defects in the oxide surrounding the
floating gate. These defects occur during wafer processing and generally affect a single bit in the array. It has
been shown that defective bits of this type lose their
charge very rapidly with high temperature. For this
reason, they can be effectively screened out with a high
temperature bake.
EPROM Screening
Data retention screening is performed on all EPROM
products. Screening is at the wafer level so that higher
temperatures can be used without the fear of affecting
the solderability of a packaged unit. The screen consists
of programming each device 100% and then baking the
wafers for 48 hours at 200°C. After the bake, the 100%
pattern is verified. This screen is equivalent to 4 years
of continuous operation at 55°C. The High Temperature
Storage Life (HTSL 200) data in Table 1 shows the effectiveness of the screen. The data shows that the failure
rate is very low for the first 500 hours of a 200°C bake.
This is equivalent to 38 years of operation at 55°C and
thereby demonstrates the reliability of the EPROM cell.
Product Assurance data collected on over 5000 units
showed programmability to be 99.98%. The most recent
Program/Erase cycling data had no fails out to 100 cycles.
By focusing on eliminating Program Disturb and DC
Erase, the threshold of a programmed EPROM cell is
consistently well above 7.0 volts and typically above
8.0 volts. This provides additional operating margin
and reliability.
Split Gate vs. Traditional EPROMs
The patented WSI split gate EPROM (Patent #4,639,893)
has several inherent advantages over the traditional
stacked gate EPROM. One major advantage is better
control over the etching of the floating gate during wafer
processing. With the traditional stacked gate EPROM,
a self-aligning process is used to define the floating gate.
That is, a layer of poly is first deposited for the floating
gate, followed by an oxide layer, and finally another poly
layer for the control gate. To define and etch the floating
gate, the control gate poly and poly-poly oxide are first
etched and are used as the mask to define the floating
gate. This means that the etching of the control gate and
the poly-poly oxide must be very well controlled in order
to achieve good definition of the floating gate. For the
WSI split gate EPROM, the floating gate is etched using
conventional methods in the step following the poly
deposition of the floating gate. This way the floating gate
etch is very well controlled and is not dependent upon
both a poly and an oxide etch.
Charge can also flow electrically to the floating gate.
Charge gain is charge transfer from either the word line
or the bit line to the floating gate such that an unprogrammed device becomes programmed. To date, charge
gain has not been observed on any WSI EPROM.
EPROM Programming
Electrical charge loss is the major cause for programming failure. Program Disturb is charge transfer from the
floating gate to the bit line. This charge loss mechanism
occurs during programming due to the high electrical
fields present. Failure occurs when an already programmed cell loses charge as other cells, with the same
bit line, are being programmed. This failure mechanism
is the result of oxide defects at the edge of the floating
gate.
DC Erase is electrical charge loss to the word line. DC
Erase is the result of defects in the oxide between the
floating gate and the word line above. Like Program
Disturb, DC Erase occurs during programming when an
already programmed cell losses charge as adjacent cells
on the same word line are programmed.
The WSI split gate EPROM has matured to the point that
programmability by the customer can be >99.9%.
TRADITIONAL STACKED GATE EPROM
GATE OXIDE
WSI SPLIT GATE EPROM
7-7
Quality and Reliability
This leads to another advantage for the WSI split gate
EPROM. Because of the critical etching involved with the
traditional stacked gate EPROM, it is difficult to use a
silicide on the control gate to reduce the poly resistance
and speed up the device. The conventional processing
steps used to make the WSI split gate EPROM does allow
for the successful use of silicide and is used on many
products.
metal shifting on double layer metal devices are minimized on even large die through a planarization process.
When processing is completed, the back of the wafer is
polished to remove oxides and other processing artifacts.
This results in better eutectic die attach at assembly and
reduces the chances of die cracking.
Another advantage lies in the quality of the oxide surrounding the floating gate. Following the floating gate
etch on the stacked gate EPROM, a third oxide is grown
which contacts the edge of the floating gate as well as
the poly-poly oxide. The floating gate is now surrounded
by three separate oxides (gate oxide, poly-poly oxide and
edge oxide), all of which contribute to defects. On the
other hand, the WSI split gate EPROM has a
homogeneous poly-poly oxide which contacts the floating
gate at the top as well as the edges. Because the floating
gate of the split gate EPROM is surrounded by only two
oxides, neither of which are etched, better oxide integrity
is obtained. Oxide integrity is the key in reducing reliability problems such as: Data Retention, Program Disturb
and DC Erase.
The low power characteristics of CMOS greatly enhance
the reliability of any system. This can be demonstrated
by comparing the thermal characteristics of WSl's
RPROM vs a Bipolar PROM and applying it to reliability.
The CMOS Advantage
For instance, if we assume a 24-pin CERDIP package
with a thermal resistance of 63°C in an ambient temperature of 55°C, the following junction temperatures are
obtained:
WS57C49
CMOS RPROM
(18 MHz)
64K Bipolar
PROM
Icc = 15 mA
Icc = 50 mA
Icc = 150 mA
P = 75 mW
P=250mW
P = 750 mW
TR = 5°C
TR = 16°C
TR = 47°C
TJ = 60°C
TJ = 71°C
TJ = 102°C
WS57C49
CMOS RPROM
(Standby)
PROCESS RELIABILITY
WSI utilizes a Class 10 wafer fab facility for all its wafer
processing. Most processing is performed by robotics
which reduces the human factors such as contamination
and handling from contributing to reliability failures.
Photolithography is performed using state-of-the-art steppers which eliminates marginal mask defects from
becoming reliability hazards. Passivation cracks and
Calculating the acceleration factor of the Bipolar PROM
over the WSI EPROM, using an activation energy of
0.5 eV, we find that the acceleration is 7x in the standby
mode and 4x at 18 MHz. This means that by running
cooler, the WSI RPROM will have a life expectancy of
4 to 7 times greater than its Bipolar PROM equivalent.
The following tables show reliability results obtained on various WSI products.
EPROM RELIABILITY DATA
Dynamic High Temperature Life Test
Table 1
Product Hours
Failures
Act. Eng.
Failure Rate
60% Conf at SS'C
4,808,388 Hours
3
3
8
2
0.3 eV x 55
0.5 eV
0.6 eV
1.0 eV
1.6 FITs
18 FITs
19 FITs
0.3 FITs
High Temperature
Storage Life Test
Combined Failure Rate:
Cause
Oxide Defects
Assembly Defects
Charge Loss
Contamination
38.9 FITs
HTSL 200'C
No Blaa
168 Hours
11502
332 Hours
01501
500 Hours
01501
1000 Hours
51501
HTSL 1S0'C
No Bias
168 Hours
01451
332 Hours
01451
500 Hours
01451
1000 Hours
01451
Product Hours
Failures
Act. Eng.
Failure Rate
60% Conf at· SS·C
Cause
( 501,168 at 20000)
451,000 at 15000
5
0.6 eV
1.0 eV
16.5 FITs
0.08 FITs
Charge Loss
Contamination
Combined Failure Rate:
16.6 FITs
1
Product Types: WS27C64F, WS57C64F, WS57C49, WS27C128F, WS27C256F
7-8
Quality and Reliability
OTP RELIABILITY DATA
Table 2
Dynamic High Temperature Life Test
DHTL lS0·C
6.S Volts
168 Hours
0/314
48 Hours
211522
11-
SOO Hours
0/246
Bond Short
Output Leakage
1000 Hours
1/246
1-
Charge Loss
Temperature/Humidity with Bias
THB
8S·C/8S% RH
S.O Volts
168 Hours
0/287
SOO Hours
0/2F51
1000 Hours
0/2F51
96 Hours
0/315
168 Hours
0/315
240 Hours
1/315
Pressure Pot
PPOT
lS PSIGI121·C
1-
Temperature Cycle
100 Cycles
0/234
TC
-SS·C/+1S0·C
SOO Cycles
0/234
1000 Cycles
2/234
11-
Products: WS57C64F
BIT SLICE RELIABILITY DATA
No Corrosion
Bond Lift
Input Leakage
Table 3
Dynamic High Temperature Life Test
DHTL 12S·C
S.S Volts
48 Hours
1/1670
168 Hours
0/1606
SOO Hours
111246
1000 Hours
01728
DHTL lS0·C
S.S Volts
48 Hours
111383
168 Hours
0/825
SOO Hours
21298
1000 Hours
0/295
Product Hours
Failures
Act. Eng.
Failure Rate
60% Conf at SS·C
1
1.0 eV
0.5 eV
1.5 FITs
127 FITs
Combined Failure Rate:
128.5 FITs
SOO Hours
0/412
1000 Hours
4/313
0
( 1,023,672 at 125 C)
411,826 at 150·C
4
Cause
Ionic Contamination
1 - Bond Short
3 - Functional
Temperature/Humidity with Bias
THB
8S·C/8S% RH
S.O Volts
168 Hours
11520
1-
Static 100
211-
Corrosion
Functional
Static 100
Pressure Pot
PPOT
lS PSIGl121·C
96 Hours
2/501
2-
Short
168 Hours
1/499
1-
240 Hours
0/182
Functional
Temperature Cycle
500 Cycles
1/390
TC
-SS·C/+1S0·C
1-
Wire to Wire
Short
1000 Cycles
1/389
1-
Wire to Wire
Short
Products: WS5901, WS59016, WS5910A, WS59520, ASIC1004
7-9
7-10
WAFERSCALE INTEGRA nON, INC.
PACKAGING
8
WSI PRODUCT PACKAGES
(By Alphabetical Drawing Number)
Drawing
Pins
Package
Window
Package Type
Page No.
B1
C1
C2
C3
01
02
03
04
F1
G1
G2
J1
J2
K1
64
(28)
(32)
5idebrazed Ceramic Dip. 0.9"
Ceramic Leadless Chip Carrier
Ceramic Leadless Chip Carrier
Ceramic Leadless Chip Carrier
CERDIp, 0.6"
CERDIp, 0.6"
CERDIp, 0.6"
CERDIp, 0.6"
Ceramic Flatpack
Ceramic PGA
Ceramic PGA
Plastic Leaded Chip Carrier
Plastic Leaded Chip Carrier
CERDIP, 0.3"
Ceramic Leaded Chip Carrier
Plastic Dip, 0.9"
Plastic Dip, 0.6"
Plastic Dip, 0.6"
Plastic Dip, 0.6"
Plastic Dip, 0.3"
Plastic Dip, 0.3"
CERDIp, 0.3"
CERDIp, 0.3"
Ceramic PGA
Ceramic PGA
CERDIp, 0.6"
Ceramic Leadless Chip Carrier
No
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
No
No
B
C
C
C
0
0
0
0
F
G
G
J
J
K
L
M
P
P
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5
5
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8-1
8-1
8-2
8-2
8-3
8-3
8-4
8-4
8-5
8-5
8-6
8-6
8-7
8-7
8-8
8-8
8-9
8-9
8-10
8-10
8-11
8-11
8-12
8-12
8-13
8-13
8-14
L1
M1
P1
P2
P3
51
52
11
12
X1
X2
Y1
Z1
(44)
24
28
40
32
24
68
101
68
44
24
68
64
40
24
28
24
28
24
28
88
44
40
(68)
T
X
X
Y
Z
(In Order of Pin Count)
Pins
Package
Window
Package Type
Drawing
Page No.
24
24
24
24
24
24
28
28
28
28
(28)
32
(32)
40
40
40
44
(44)
44
64
64
68
(68)
CERDIp, 0.3"
CERDIp, 0.3"
PlastiC Dip, 0.3"
CERDIp, 0.6"
Plastic Dip, 0.6"
Ceramic Flatpack
CERDIp, 0.3"
Plastic Dip, 0.3"
CERDIp, 0.6"
Plastic Dip, 0.6"
Ceramic Leadless Chip Carrier
CERDIp, 0.6"
Ceramic Leadless Chip Carrier
CERDIp, 0.6"
CERDIp, 0.6"
Plastic Dip, 0.6"
PlastiC Leaded Chip Carrier
Ceramic Leadless Chip Carrier
Ceramic PGA
5idebrazed Ceramic Dip, 0.9"
Plastic Dip, 0.9"
Ceramic PGA
Ceramic Leadless Chip Carrier
Plastic Leaded Chip Carrier
Ceramic Leaded Chip Carrier
Ceramic PGA
Ceramic PGA
No
Yes
No
Ves
No
Ves
Ves
No
Ves
No
Ves
Ves
Ves
No
Ves
No
No
Ves
Ves
No
No
No
No
No
No
Ves
No
K
T
5
0
P
F
K1
T1
51
01
P2
F1
8-7
8-11
8-10
8-3
8-9
8-5
8-12
8-11
8-3
8-10
8-1
8-4
8-2
8-13
8-4
8-9
8-7
8-2
8-13
8-1
8-8
8-5
8-14
8-6
8-8
8-12
8-6
68
68
88
101
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0
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C1
04
C2
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P1
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X2
B1
M1
G1
Z1
J1
L1
X1
G2
-- - - ===r:
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PRODUCT PACKAGES
,~~~-
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---~.-..
WAFERSCALE INTEGRATION, INC.
DRAWING 81
64 PIN Ceramic Side Braze (Package Type B)
0.008
JO.012
64
0.890
0.930
INDEX
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0.390 sa
0.445 sa
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DRAWING C2
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DRAWING 01
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Product Packaging
DRAWING D3
40 Pin CERDIP
(Package Type D)
0.590 BEND
D.62o
0.505
0:560
~~~~~~~~~
14------- 2.030
20
_ _ _ _ _ _ _ _ _~
2.100
DRAWING D4
32 Pin CERDIP (Package Type D)
0.590
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0.010
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0.420
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~
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0.053
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0.705
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WAFERSCALE INTEGRA nON, INC
SECTION INDEX
PROGRAMMERS/PROGRAMMING
WSI Programming Algorithms .................................................................. 9-1
WSI MagicPro™ Engineering Programmer ........................................................ 9-5
Data 110 Programming Support ................................................................ 9-7
For additional information,
call 800-TEAM-WSI (800-832-6974).
In California, call 415-656-5400.
EPROM PROGRAMMING ALGORITHM A
WAFERSCALE INTEGRATION, INC
PRODUCTS:
PROGRAMMING PARAMETERS
WS57C64F
WS27C64F
WS57C128F
WS27C128F
WS57C256F
WS27C256F
WS57C65
WS57C257
Vpp:
13.5V ± 0.5V*
PULSE: MIN Ipw
0.95 ms
=
>-_ _Y.:..;E:::S,--_.. FAIL (STOP)
FAIL
>-_--'-'FA.c.IL=------l.- FAIL (STOP)
*Vpp = 12.5V ±. 0.5V FOR:
WS27C256F
WS57C256F
WS57C257
WS27C512F
9-1
9-2
EPROM PROGRAMMING ALGORITHM B
WAFERSCALE INTEGRA110N, INC.
PRODUCTS:
PROGRAMMING PARAMETERS
WS57C49
WS57C43
WS57C191
WS57C291
WS57C51
WS57C49B
WS57C43B
WS57C51B
WS57C191B
WS57C291B
Vpp:
13.5V ± 0.5V
0.95 ms
PULSE: MIN tpw
=
> __Y..;.,E=cS, - - _ . FAIL (STOP)
FAIL
>_--=..:FA.::.IL=------<~ FAIL
(STOP)
9-3
9-4
== J:III
'lIsE
='
JIll
i&#~~
~
~
WS6000
___________________________________________________________
WAFERSCALE INTEGRA110N, INC.
MAGICPRO™ MEMORY AND LOGIC
PROGRAMMER
KEY FEATURES
• Programs All WSI CMOS EPROMs and
RPROMsTM (x8, x16, Mux 1/0 and All
Future Programmable Products
• Programs LCC and PGA Packaged
Product by Using Adaptors
• Easy-to-Use Menu-Driven Software
• Programs 24, 28, 32 and 40 Pin
Standard 600 Mil or Slim 300 Mil Dip
Packages Without Adaptors
• Compatible with IBM PC/XT/AT©
Family of Computers (and True
Plug-Compatible)
GENERAL DESCRIPTION
MAGICPRO™ is an engineering development tool designed to program existing WSI EPROMs and RPROMs™ and
future WSI programmable products. It is used within the IBM PC© and compatible environment. The MAGICPRO™
is meant to bridge the gap between the introduction of a new WSI programmable product and the availability of
programming support from the EPROM programmer manufacturers (e.g., Data 110, etc.). The MAGICPRO™
programmer and accompanying software enable quick programming of newly released WSI programmable products,
thus accelerating the system design process.
The MAGlcPRO™ plug-in board is integrated easily into the IBM PC©. It occupies a short expansion slot and its
software requires only 256K bytes of computer memory. The two external ZIF-Dip sockets in the Remote Socket Adaptor
(RSA) support WSI 24, 28, 32 and 40 pin standard 600 mil or slim 300 mil Dip packages without adaptors. LCC and
PGA packages are supported using adaptors.
9-5
WS6000
Many features of the MAGlcPRO™ Programmer show its capabilities in supporting WSI's future products. Some of
these are:
-
24 to 40 pin JEDEC Dip pinouts
1 Meg. address space (20 address lines)
16 data 1/0 lines
The MAGlcPRO™ menu driven software system makes using different features of the MAGICPRO™ an easy task.
Software updates are done via floppy disk which eliminates the need for adding a new memory device for system
upgrading. Please call 800-TEAM-WSI for inforr:nation regarding programming WSI products not listed herein. The
MAGICPRO™ reads .Intel Hex format for use with assemblers and compilers.
MAGICPRO™
-
COMMANDS
Help
Upload RAM from device
Load RAM from disk
Write RAM to disk
Display RAM data
Edit RAM
Movelcopy RAM
Fill RAM
Blank test device
Verify device
Program device
Select device
Configuration
Quit MagicPro™
WSI PRODUCTS
WS57C191/291
WS57C43
WS57C43B
WS57C49
WS57C49B
WS57C51
WS57C51B
WS27C64F
WS57C64F
WS57C65
WS57C66
WS27C128F
WS57C128F
WS27C256F
WS57C256F
WS57C257
WS27C512F
2K x 8
RPROM™
4K x 8
RPROM™
4K x 8
RPROM™
8K x 8
RPROM™
8K x 8
RPROM™
16K x 8
RPROM™
16K x 8
RPROM™
8K x 8
EPROM
8K x 8
EPROM
4K x 16
EPROM
4K x 16
EPROM
(Mux 1/0, 28 Pin DIP)
16K x 8
EPROM
16K x 8
EPROM
32K x 8
EPROM
32K x 8
EPROM
16K x 16
EPROM
64K x 8
EPROM
TECHNICAL INFORMATION
• Size: IBM PC© short length card
• Port Address Location: 100H to 1FFH~default 140H (If a conflict exists with this address space, the address location
can be changed in software and with the switches on the plug-in board.)
• System Memory Requirements: 256K bytes of RAM
• Power: +5 Volts, 0.03 Amp.; +12 Volts, 0.04 Amp.
• Remote Socket Adaptor (RSA): The RSA contains two ZIF-Dip sockets that are used to program and read WSI
programmable products. The 32 pin ZIF-Dip socket supports 24,28 and 32 pin standard 600 mil or slim 300 mil
Dip packaged product. The 40 pin ZIF-Dip socket supports all 40 pin Dip packages. Adaptor sockets are available
for LCC and PGA packages.
ORDERING INFORMATION
The WS6000 MAGICPRo™ System contains:
MAGIcPRO™
MAGIcPRO™
MAGIcPRO™
Operating
IBM PC© plug-in programmer board
Remote Socket Adaptor and cable
Operating System Floppy Disk and
Manual
MAGlcPRO™ Adaptors include:
WS6001
WS6002
WS6003
WS6005
28
32
44
28
CLLCC Adaptor
CLLCC Adaptor
CLLCC Adaptor
Pin Dip WS57C66 Adaptor
IBM is a trademark of IBM Corporation .
.RPROMTM and MAGlcPRo™ are trademarks of
WAFERSCALE INTEGRATION, INC.
9-6
iF==
,::~
----- .....
!=!!!r,:_.,_~II
_____D_~_TA_//I_O_P_R_O_G_R_A_M_M_'_N_G_S_U_P_P_O_R_T
WAFERsrALE INTEGRA 710N, INC.
All WSI memory products program easily on standard commercially available EPROM programmers. Manufacturers
of these EPROM programmers offer a broad range of products which cover prototyping through high volume production requirements. The leading programmer manufacturer is Data 110 Corporation located in Redmond, Washington.
The table below covers that portion of Data 1I0's product line which supports WSI's programmable products. For
more information regarding programming support for WSI products call toll-free 800.:rEAM WSI (800-832-6974) or
415-656-5400 (CA).
Data 110 Programming Support
PIN
Family/Pinout
Unipak 2
Unipak 2B/Cartridge
RPROMs: WS57C191
WS57C291
WS57C43
WS57C43B
WS57C49
WS57C49
WS57C49
WS57C49B
WS57C49B
WS57C49B
WS57C51
WS57C51B
7B/21
7B/21
7B/63
7B/63
3C/67
F3C/067
7B/67
3C/67
F3C/067
7B/67
7B/71
7B/71
V12
V12
V12
V12
V12
V12/V12/V121V12/V12/-
-
-
V12
V12/-
-
-
EPROMs: WS57C64F
WS57C128F
WS57C256F
WS27C64F
WS27C128F
WS27C256F
WS57C65
WS57C257
3C/33
3C/51
3C/32
3C/33
3C/51
3C/32
2C/E7
1F/E1
V12
V12
V12
V12
V12
V12
-
-
-
-
V13/351B101
V13/351B101
V12/351 B086
V12/351 B086
V12/351 B086
V12/351 B086
V12/351 B086
V12/351 B086
V12/351 B095
V13/351 B095
Unisite/Module
1.5/Site
1.5/Site
1.5/Site
1.5/Site
40
40
40
40
-
1.5/Site 40
-
1.5/Site 40
1.5/Site 40
1.5/Site 40
1.5/Site 40
1.5/Site 40
1.5/Site 40
1.5/Site 40
-
1.5/Site 40
-
GangPak
V07
-
V07
V07
V07
V07
-
V07
V07
V07
V07
-
9-7
9-8
WAFERSCALE INTEGRA170N, INC.
APPLICATION NOTES
10
SECTION INDEX
APPLICATION NOTES
001 EPROMs for Modern Times .............................................................. 10-1
002 Introduction to the WSI Family of Mappable Memory Products ................................. 10-5
For additional information,
call SOO-TEAM-WSI (SOO-S32-6974).
In California, call 415-656-5400.
APPLICATION NOTE 001
WAFERS(,ALE INTEGRA nON. INC.
EPROMs FOR MODERN TIMES
HIGH SPEED EPROMs:
Early generations of microprocessors (e.g., 6809, 8085, 8086, etc.) and microcontrollers (8048, 8051, 6805, etc.) operated
at frequencies in the 1-5 MHz range. At these operating frequencies, memory access time requirements varied from
200-500 ns. The EPROM technology available at the time was well suited for such applications. This technology,
based upon a single transistor "stacked gate" EPROM cell (see Figure 1), was optimized for programmability and
density, not speed. Many manufacturers were quite successful with this technology and manufactured EPROMs from
16K bits up to 1 Mbit.
However, today's generation of high performance microprocessors (80286, 80386, 68000, 68020, etc.), microcontrollers
(8096, etc.) and dedicated DSP processors (TMS320xx, MC56000, etc.) operate in the 12-40 MHz range and require
memories with access times well below 100 ns (see Table 1).
Table 1
MEMORY ACCESS TIME REQUIREMENTS
PART #
FREQUENCY
MEMORY ACCESS
80386
16 MHz
70 ns
68020
20 MHz
70 ns
32020
20 MHz
75 ns
56000
20 MHz
55 ns
320C25
40 MHz
40 ns
As will be shown, the traditional single transistor "stacked gate" approach is not able to provide such high speeds.
As a result, system designers are forced into alternatives such as down loading from slow EPROM into fast SRAM,
which provides non-volatility and high speed. Unfortunately, these techniques result in higher system costs (board
space, components, power, etc.).
Semiconductor manufacturers are attempting to solve this problem at the I.C. level with various approaches. This
article explains the various techniques for achieving high speed EPROMs and allows the reader to determine which
technique is best suited for their application and which technique provides the best path for the future.
HIGH SPEED NVM: A GENERAL DISCUSSION
Memory arrays are laid out in two-dimensional row and column formats. These are referred to as word lines and bit
lines, respectively. Selecting a word line determines which row of cells in the array has been chosen to provide the
programmed output. The bit line, or column, is used to determine which of the selected cells in the row is to be read
from an output. Although this technique singles out a particular EPROM cell for reading, the output of the selected
EPROM is still connected to the outputs of several non-selected EPROM cells which share the same column, or bit
line. Each of these non-selected cells adds some capacitance to the bit line. This capacitance must be overcome
by the selected cell before the proper state ("1" or "0") can be sent to the output. The selected cell must have enough
drive to be able to discharge the combined bit line capacitance. Higher drive, or read current, results in a faster capacitive
discharge and, therefore, faster reading. Lower bit line capacitance and/or increasing read current are the fundamental
goals associated with developing high speed, dense EPROMs. Lowering bit line capacitance is easily achieved by
reducing the number of memory cells. Although this results in a speed improvement, it severely limits density.
The main problem to solve, therefore, is how to manufacture an EPROM cell which can provide high read current
(for speed), high density (for small size), high reliability and ease of programming.
The following paragraphs discuss four approaches for developing a fast, dense, reliable and programmable EPROM
memory.
10-1
1m
Application Note 001
1. SINGLE TRANSISTOR ("STACKED GATE")
The industry standard single transistor stacked gate EPROM cell (Figure 1) is optimized for efficient programming
and high density. It is not well suited for high speed because of its low read current. The typical read current for
a single unprogrammed stacked gate EPROM cell is between 20-50 microamps and the total bit line capacitance
for a typical EPROM can be as high as 3-5 pF. Consequently, at 40 microamps of worst-case read current, it would
take a "stacked gate" EPROM cell 70 ns to discharge the bit line by enough voltage to detect an unprogrammed
condition. Address decoding and output buffers add another 25-50 ns (depending upon technology). Clearly, this
makes it very difficult to achieve a worst-case total access time which will allow an EPROM to run with today's generation of processors (see Table 1). Several semiconductor manufacturers are looking tor alternatives to surmount the
inherent limitations of the older single transistor "stacked gate" EPROM.
"STACKED GATE"
EPROM CELL
(INDUSTRY STANDARD)
I
CONTROL
~------------------~
GATE
I
FLOATING
GATE
~----------------------~
Figure 1
2. TWO TRANSISTOR FAST CELL ("STACKED GATE" EPROM)
In this approach each bit consists of two stacked gate EPROM cells in a differential pair. With this architecture, it
is possible to employ a differential sensing technique which allows a programmed or unprogrammed state ("0" or
"1") to be detected with a very small voltage swing. As a result, a memory cell can be read much faster than with
a standard sensing technique. However, this incurs the penalty of twice the area of the single cell memory array as
well as implications of lower yields, higher costs and lower reliability than a single cell approach.
3. FOUR TRANSISTOR FAST CELL ("STACKED GATE" EPROM)
In this approach, the differential senSing technique is also used. However, each half bit is constructed with two
tranSistors, one of which is optimized for programming efficiency while the second transistor is optimized to give high
read current (typically 150 microamps). This makes it possible to achieve very high speeds. However, a four transistor
cell results in a very large memory array resulting in problems more severe than those of the two transistor approach
(again, low yields, high costs and low reliability). Consequently, this technique is limited to low density devices.
STACKED GATE SUMMARY
10-2
MEMORY TYPE
RELATIVE SPEED
RELATIVE DIE SIZE
Single Transistor
Slow
Small
Two TranSistor
Fast
Large
Four Transistor
Fastest
Larger
Application Note 001
4. SINGLE TRANSISTOR FAST CELL ("SPLIT GATE" EPROM)
WaferScale Integration Inc. (WSI) has developed a proprietary technology which embodies all of the benefits of the
single transistor "stacked gate" (ease of programming, reliability, and density) and conquers the fundamental problem
of low read current. This patented technology is known as the "split gate" EPROM (see Figure 2).
WAFERSCALE'S PATENTED
"SPLIT GATE"
EPROM CELL
CONTROL
GATE
'--_ _ _ _ _ _ _ _
--'I~-r:TING
Figure 2
The "split gate" cell uses a single transistor per bit and, although it is nearly the same size as the "stacked gate,"
each cell provides a read current of at least 160 microamps under worst-case voltage and temperature conditions.
This allows the design of very high density and vel}' fast memory products. As an example of the capabilities of the
"split gate:' WaferScale has introduced, a family of Fast EPROM products varying in density from 16K to 256K bits
and in speed ranging from 35-55 ns, all manufactured with the same EPROM technology.
SPLIT GATE SUMMARY
MEMORY TYPE
RELATIVE SPEED
RELATIVE DIE SIZE
Single Transistor
Fastest
Small
As is seen from the table above, the WSI split gate EPROM technology provides the high density capability of the
single transistor "stacked gate" and the fast speed of the four transistor solution.
REQUIRED FEATURES
Although speed and density are necessary EPROM attributes, they alone are not sufficient for today's memory
requirements. Reliability and ease of programming play an equally important role in determining the usefulness of
a memory product.
10-3
mJ
,
Application Note 001
RELIABILITY
The fundamental criterion for evaluating the reliability of an EPROM cell is Data Retention. This is the ability of the
cell to maintain its programmed state over time. Under extensive testing, the WaferScale patented "split gate" compares quite favorably to the industry standard "stacked gate." Figure 3 displays the results of testing which compares
the charge loss of the two cell types over time.
CHARGE LOSS
SPLIT GATE vs STACKED GATE
TA = 250·C
1.0
CHARGE LOSS
(VOLTS)
0.1
0.01 '--_ _ _ _--1._ _ _ _ _- ' -_ _ _ _ _- ' -_ _ _ _- - '
500
1000
1500
2000
TIME (HOURS)
Figure 3
As can be seen from the above chart, the data retention of WaferScale's "split gate" is nearly an order of magnitude
better than the older industry standard "stacked gate," which is considered a very reliable technology.
In addition, life test data has shown excellent results at higher than normal conditions (TA
Fit levels of less than 100 are typical (1 Fit = 1 failure in 1 billion device hours).
=
150°C, Vee
=
6.SV).
This demonstrates that WaferScale has actually improved EPROM reliability in its pursuit of a high speed and high
density EPROM technology. For the latest Reliability Data Summary, contact your local WaferScale sales representative.
PROGRAMMING
All WaferScale memory products are easily programmed using standard 3rd party EPROM/PROM programmers. The
programming algorithms supplied to these manufacturers have been optimized for programming yield.
A further programming advantage is the fact that WaferScale devices program and verify with Vee set at 5.5V. This
feature is ideally suited for "on board" programming where other non-EPROM devices may be powered by the same
Vee power supply, because the common Vee voltage used by all devices can also be used during EPROM programming. Most "stacked gate" algorithms require Vee to be 6V or higher during the program mode and this requires
either a separate Vee supply or protection circuitry for the non-EPROM devices.
SUMMARY
Although the single transistor "stacked gate" EPROM technology is very well suited for its intended use (slow, dense
NVM), it is not we" suited for today's high performance memory requirements. Brute force techniques, such as using
multiple transistor memory cells, can provide high performance; however, the penalty paid in die size and resultant
higher costs limits these techniques to relatively low densities.
WaferScale's patented "split gate" technology combines a" of the attributes of the single transistor "stacked gate"
(reliability, ease of programming and density) with the speed of the multi-transistor memory cell. The result is a family
of dense, high speed EPROM based products. Also, since WaferScale's technology is we" suited for device scaling,
the technology path for future products is already in place. This wi" result in products with higher density that utilize
both standard and application specific architectures.
10-4
APPLICATION NOTE 002
WAFERSCALE INTEGRATION, INC.
INTRODUCTION TO THE WSI MAp™ FAMILY OF
MAPPABLE MEMORY PRODUCTS
The basic components in a typical microprocessor based system are an EPROM for program store, an SRAM for
data store and a decoder for selecting the appropriate memory device based on the address (Figure 1). The decoder
is typically implemented using descrete logic, 74XX138 type MSI building blocks or PAL® type of devices. Hardwired
devices require jumpers on the P.C. board for memory configuration changes and expansion. PAL® based decoders
are more flexible since they can be re-programmed for configuration changes.
"-
EPROM
v
CS
OE
t
J
ADDRESS BUS
~P
RD
to..
"
V
DATA BUS
RD
A
"SRAM
v
cs
WE
OE
"
1 11
WR
DATA BUS
1
DECODE
LOGIC
AND
JUMPERS
WR
RD
CSO
TO OTHER DEVICES
CSO
Figure 1. General Architecture -
Discrete Solution
Regardless of the method chosen to implement the decoder, some compromises will be incorporated that affect system
performance, board space and cost. Since the decoder is in the memory access path, the total memory access time
is the sum of the decoder delay and the access time of the memory. For example, to achieve a 40 ns total access
time, a 12 ns decoder can be used with a 25 ns memory allowing 3 ns for on-board interconnect delay (memory products
in the 25 ns range are expansive and usually are available in by 1 or by 4 bits wide configuration).
The WSI MAp™ family of mappable memory products has been developed to significantly enhance system performance by integrating (on one Chip) high density EPROM for program store, high density SRAM for data store and
high performance logic in the form of a Programmable Mapping Decoder (PMD™) (Figure 2). The products are
ADDRESS BUS
"-
ADDRESS
I'
RD
DE
WR
WE
MAP'"
~P
A
DATA BUS
"
"I'
I/O
r--- CSO
r---
cso
TO OTHER
DEVICES
Figure 2. Single-Chip Solution Using MapTM Memory
10-5
Application Note 002
ideally suited for DSP oriented applications (modems, analog data filtering or analysis, etc.), expansion memories
for 8 or 16-bit microprocessors and microcontrollers and applications that are very board space sensitive (Le., plug-in
cards, avionics, portable systems, etc.).
The EPROM is based on WSI's patented split gate EPROM technology for high density and very high speed. The
first generation of MApTIA products from WSI (WSMAP162N61, WSMAP168) contains a 128K bit UV erasable 40 ns
EPROM. This EPROM can be organized in the bytewide configuration as 16K x 8 and in the wordwide configuration
as 8K x 16.
The SRAM is based on the industry standard full CMOS 6-transistor cell. The advantages of this cell are high speed,
very low stand-by power, high noise immunity and good data retention when disturbed by alpha particles. In the first
MAp™ generation of products, the SRAM contains 32K bits which can be configured as 4K x 8 in the byte mode
or 2K x 16 in the wordwide mode.
MApTM MEMORY ARCHITECTURE
The memory is structured as a series of blocks to achieve a very flexible and highly configurable circuit for general
purpose applications (Figure 3). The EPROM is subdivided into 8 blocks and the SRAM is subdivided into 2 blocks.
These memory blocks can be considered as separate memories with dedicated internal chip selects. The on-board
Programmable Mapping Decoder (PMD™) selects the appropriate block based on the incoming address. This architecture enables the product to be configured and compatible with virtually any system address map. Complicated
address maps of microcontroller systems can be fully utilized by programming blocks of EPROM and SRAM to be
addressed by the various portions of the system address map.
....
ADDRESS
v
.--
I/O
EPROM
CS
_A
EPROM
CS
~
"
DIRECT ADDRESSES
~
I
~
v
cs
....
EPROM
v: cs
EPROM
....
ADDRESS BUS
EPROM
>--
....
PMD™
BLOCK DECODE"
ADDRESSES
--
-
8
ESo_7
WE/Vpp
RSO_1
CSI
CSOO_7
OE
FCSO
~
~
~
>->--
-
CS
I/O
"EPROM
I
"':
I
"': cs
""-
CS
EPROM
EPROM
CS
....
0---
A
v: cs
"v:
SRAM
SRAM
cs
I"\.
Figure 3. MapTM Memory Architecture
In addition to having fine control of memory allocation, it is now easier to make software updates which require changes
in the address map boundaries. This can be accomplished by simply reprogramming the PMD™ when the EPROM
code is altered. Now only one part is needed to be sent to the customer to accommodate field software changes,
a user-transparent method that requires no change of PC board jumpers.
10-6
Application Note 002
THE PROGRAMMABLE MAPPING DECODER (PMD™)
The PMD™ actually performs as an address comparator. When the address that was previously programmed into
the PMD™ is detected, the PMD™ enables the internal "Chip Select" to the memory block that is selected by that
address. If no block is selected by the address, both the EPROM and SRAM are powered down and the outputs
are disabled (the SRAM retains its data). This enables other devices to drive the data bus. In addition to selecting
internal blocks of memory, the PMD™ can also be programmed to select other devices using the Chip Select Outputs. The CSOs are programmable in the same block resolution as the internal memory. However, a CSO can be
active for any number of blocks in the address space, Le., it is possible to enable another external 128K byte memory
by programming a single CSO to be active for that entire address range.
The PMD™ is implemented similar to a PAL" device. All the block decode addresses are connected to the AND
plane. There is only one output per AND gate (there is no OR plane). Each AND gate output either selects a block
of internal memory or, in the case of Chip Select Outputs (CSOo-7), can select a number of blocks of external memory.
Addresses A,,-A2o are block decode addresses. EPROM select outputs ESo-ES 7 (ES outputs) select 1 of 8 available
EPROM blocks. SRAM select outputs RSo-RS, (RS outputs) select one out of 2 available SRAM blocks. For a particular address, the selection of one memory block from ES o-ES7 or one from RSo-RS, is allowed but not both. That
is, only the EPROM or SRAM can be active at a particular time. The CSOs are independent of the ES and RS outputs. Anyone address can be programmed to select one or more of the CSOs even if one of the ES or RS outputs
is selected. This is particularly useful for 1/0 control or wait state generation address decode.
The PMD™ is implemented with UV erasable EPROM cell-based "fuses". After UV erase or with new parts, the
EPROM cells are normally connected between the address inputs and the select outputs. The EPROM cells are disconnected by selective programming. For a select output to be enabled, all the "true" addresses must be disconnected.
For example, for selection if the address contains All '" 0, A'l must be disconnected and if the address contains
A'2 '" 1, A'2 must be disconnected (Figure 4). For ES and RS select outputs, it is possible to not select any combination by not disconnecting any of the addresses. The case when an address and its complement are not disconnected is termed "hard deselect".
A,A.
s. = A,A.
53 = HARD DESELECTED = NEVER SELECTED
s,
=
5,
=
D6 =
DON'T CARE
=
ALWAYS SELECTED
A,
• = CONNECTED
X = DISCONNECTED
Figure 4. PMD™ Programming Examples
CHIP SELECT OUTPUTS (CSO)
For CSOs, it is possible to make an address line a "don't care" by deselecting both the true and the complement
of that address (Figure 5). This enables the CSO to be active for more than one address combination. Thus, a group
of blocks of external memory can be selected with only one CSO. ACSO can be programmed to function as a configuration bit which is always deselected (Le., CSO o '" "1") or always selected (Le., CSOo '" "0") by programming
the addresses with "hard deselect" or with the "don't care" patterns respectively. This is similar in function to a PC
board wire jumper. Unused CSOs should be programmed with all addresses "don't care" to eliminate switching and
reduce power consumption.
Since the PMD™ is always powered up, CSOs are always active (depending on the PMD™ configuration).
10-7
1m
,
Application Note 002
ESo
ES,
ESs
RSo
RS,
Figure 5. PMD Array Architecture
POWER DISSIPATION
Power dissipation on the chip is managed by selectively powering up either the EPROM or SRAM. If the EPROM
is selected, it will draw power while the SRAM stays powered down and vice versa. When neither the EPROM or
the SRAM is selected, both are powered down. Even though the SRAM is in a "powered down" mode, its data stays
intact. A Chip Select Input (CSI) is provided for a very low power quiescent mode. With CSI = "1", the EPROM and
SRAM are powered down but the PMD™ is powered up (independent of the incoming address signals). The CSI
input can be connected to a system power down signal if such signal exists. Otherwise, to save power in the stand-bY
mode, it is possible to address a location in memory that does not select either the EPROM or the SRAM. In this
case, only the PMD™ is powered up and will draw only a small fraction of the active power.
The CSIIAx input is a dual function pin. It is always an address (MSB) input. Optionally, it can be programmed to be
a chip select input as well which enables the EPROM and SRAM memory when active low. In a system application,
usually one or the other modes is employed but rarely both even though it is possible to employ both modes
simultaneously.
SECURITY
The PMD™ is programmed through the circuit's address and 1/0 pins. When entering the PMD™ programming mode,
the contents of the PMD™ can be addressed and accessed through the 1/0 pins. After programming is completed,
it is possible to isolate the PMD'sTM programmed configuration by programming the security (SEC) bit. The security
bit, when programmed, disables external access to the PMD™ and ensures that the part can not be copied. To further aid in securing data in the MAp™ product, it is suggested that memory blocks that are addressed in a certain
order be placed in a different order in the PMDTM. The security bit will be erased during UV erase.
10-8
Application Note 002
SYSTEM APPLICATIONS
The MAP'" family of products is designed to reduce memory access time and board area utilization in high performance digital signal processor and microcontroller and microprocessor systems. These systems typically have the
following requirements:
• 16-bit data path (e.g., Motorola 68000/68020, Intel 8096/8086180286 Processors or National HPC16000 microcontrollers and T.I. TMS32020rrMS320C25 DSP circuits).
• 64K-1 Meg address space
• Fast access time (100 ns to 40 ns)
• Need decoding for 1/0 and memory
• Printed circuit board area limitations
• Need a mix of memory
- Program store: 128K bits EPROM
- Data store: 32K bits SRAM
Figure 6 illustrates a typical system based upon a 40 MHz TMS320C25 digital signal processor. Such a system allows
only 40 ns for memory access time. The access time can be broken down into decoding time and memory access
time. The fastest decoders available today require approximately 10 ns to complete their decode function. Due to
this decoding time, memory access time for both the EPROM and SRAM must be 30 ns or less. The MAp™ family
of products performs decoding on-board the chip with no speed penalty. As a result, in the above example, a 40 ns
MAp™ product would perform the function of a 10 ns decoder and a 30 ns EPROM and SRAM memory. In addition, the equivalent of two fast EPROMs, two fast SRAMs and at least one decoder are combined into one MAp™
product resulting in a 5 to 1 component count reduction.
cs TO PORTS
1/0 PORT
INTERFACE
16-18
ADDRESS~~~~---,--------------~~~-+~
RDr----------+--------------r-~---.~
16
DSP
DATA
r--I--------+--------------r-~--_+------+------+_+_----_4
TMS320C25·40
* REPLACED BY THE
MAP'" MEMORY FAMILY
Figure 6. General Block Diagram of a DSP System
10·9
Application Note 002
The general architecture of the first release of the MAp™ product line is shown in Figure 7. The family consists of
three products. They are the WSMAP162, the WSMAP161 and the WSMAP168. The memory consists of 128K bits
of EPROM and 32K bits of SRAM. A fast Programmable Memory Decoder (PMD™) is used on-board the circuit to
map and access different EPROM and SRAM sections depending on the address inputs. The EPROM and SRAM
can be partitioned into blocks of 1K 16-bit words or 2K 8-bit bytes depending on the user programmed configuration
of the product.
DECODED EPROM ADDRESS
-"
PGMH
'"
v
OE
OUTO_1
(1)A'9_
EOEl
DECODED SRAM ADDRESS
(1)A'8_
WEH
PMDN
E
WEl
WENpp-
ROEl
CSO-CS7
OE-
{J >
..
CON
SIIAX(2)-
OEl
(l)CSO-
"-
2:1
MUX
~
7
OUTo_7
INo_7
Ao-A,o
WE
OE
SRAM
2K x 8
OUTo_7
INo_7
~
'"
2:1
MUX
10EH
-
-
INo_7
OUTo_7
OE
>----v
SRAM
2K x 8
OE
EPROM
8K x 8
PGM
1-
Ao-A,o
WE
ROEH
(3)BHE-
'"
INo_7
1:-
PGMl
AO-A'2
-
EPROM
8K x 8
PGM
EOEH
AO-A'7
...
AO-A'2
~
C>-
or
~n
~1I08_'5~
-
~0
Ii-th
Notes:
1. WSMAP168 Pins
2. WSMAP162 Ax = A'B
WSMAP161 Ax = A17
3. Only WSMAPl68, WSMAP161
Figure 7. General Architecture of the MAP'" Products
Any of the three products can be programmed to operate in a bytewide or wordwide configuration. The internal memory
is organized as 8K x 16 EPROM and 2K x 16 SRAM in the wordwide mode and 16K x 8 EPROM and 4K x 8
SRAM in the bytewide mode. When configured for byte operations, I/Os to 11015 become outputs (CSOo to CS07)
that can be programmed to select other devices in the system.
The Chip Select Input (CSI) on each product can be programmed to select the chip or to be an additional (highest)
address input. On the WSMAP162 it can be CSI or A 1S; on the WSMAP161, CSI or A 17 ; and on the WSMAP168, CSI
or A20 . Table 1 summarizes the programmable options.
Table 1. Programmable Features of the MAp™ Family
x8 or x16
CSI or Address
10-10
WSMAP162
WSMAP161
WSMAP168
Yes
Yes
Yes
CSIIA20
CSIIA1S
CSIIA17
Programmable Decoder
Yes
Yes
Yes
Security Mode
Yes
Yes
Yes
Application Note 002
SYSTEM INTERFACE TO WSMAP162
The WSMAP162 is especially suited for high-speed word-oriented (no byte operations) microprocessors. The
TMS320C20/25 OSP family is an example of such a microprocessor. Figures 9 and 10 show two options of interfacing
the WSMAP162 to a TMS320C25 operating at 40 MHz with no wait states. The TMS320C25 has two pins for selecting
Program Memory (PS) and Data Memory (OS). These functions are connected to the higher order address of the
WSMAP162. PS is connected to A'B and OS is connected to A 17 . Usually PS will select the EPROM and OS will
select the SRAM. See Figure S.
8. CONTIGUOUS MAPPING
b. SPLIT MAPPING
Figure 8. Examples of Mapping Memory Using the WSMAP162
40 MHz
-
A'B
An
CK
~
Ao-A,.
~
TMS320C25
v
L
PS
OS
A
--"
0 0-0,.
......
READY
STRB
RiW
1
L..r;
A1_16
MEMORY CONFIGURATION
8K)( 16 EPROM
2K)( 16 SRAM
Ao
WSMAP162
0 0 -0,.
WR
OE
Figure 9. Interfacing the WSMAP162 to a TMS320C25 in a DSP Application (x16 Configuration)
When in a wordwide (x16) configuration, the total memory available on the WSMAP162 is SK x 16 of EPROM and
2K x 16 of SRAM. See Figure 9. This implementation replaces a minimum of:
• one high-speed decoder (10 ns)
• two SK x S EPROMs (30 ns)
• two 2K x S SRAMs (30 ns)
10-11
Application Note 002
or a total of 5 circuits. If the system was previously implemented using a boot EPROM, the WSMAP162 replaces:
• one high-speed decoder (10 ns)
• two 8K x 8 EPROMs (30 ns)
• two 2K x 8 SRAMs (30 ns)
• two 8K x 8 slow EPROMs
• three ICs for Wait-State generation
or a total of 10 circuits.
In a byte wide (x8) configuration, two WSMAP162s can be interfaced directly with a TMS320C25. See Figure 10.
Key features of this system are:
• 40 ns access time
• 16K x 16 EPROM
• 4K x 16 EPROM
• 16 general purpose programmable chip selects
The general purpose programmable chip selects can be mapped to any location in the address space via the
PMDTM. These chip selects can be used to access 1/0 ports, select additional memory or control other system
functions.
40 MHz
-
PS
A,.
OS
II
TMS320C25
0 0 -0,.
vee, -
...
I I
Ao-A,.
READY
STRB
RlW
~
'\.r--
A17
A,_,.
WSMAP162
Ao
CSO_7
0 0-0,.
~~WE
0- ....
TO
OE
I/O PORTS
OR
ADDITIONAL
MEMORY
A,.
A17
.f"
T
t
A,_,.
WSMAP162
Ao
CSO_7
V
0 0-0'5
WE
OE
Figure 10. WSMAP162 in a x8 Configuration
SYSTEM INTERFACE TO WSMAP161
The WSMAP161 has two basic configurations. They are a wordwide (x16) configuration with byte operation capability
and a byte wide (x8) configuration with 8 chip select outputs (for byte wide only applications, it is suggested to use
the WSMAP162 as the inclusion of A17 instead of BHE gives greater addressing range).
The 128K address space (during byte operations in the wordwide mode) makes the WSMAP161 especially suited
for microcontroller applications. Figure 11 illustrates a simple interconnection of the WSMAP161 to a microcontroller.
In the HPC16040 without wait states, the access time is 65 ns which makes the WSMAP161 (40 ns access time) a
good fit with plenty of margin. See Figure 11.
The WSMAP161 can be configured in a bytewide (x8) mode. This is equivalent to the WSMAP162 and can also be
used "doubled-up" as shown in Figure 10.
10-12
Application Note 002
~
AD o_. s
ALE
"-
'\.r-
LATCH
rv"
1
•
co NFIGURATION
8K x 16 EPROM
2K x 16 SRAM
A8- 15
G
-
MICROCONTROLLER
(HPCI6000,
8096, etc.)
"-
MEMORY
A. 6
WSMAP161
~
CSIIAx
G
~
Ao-7
LATCH
BHE WE OE
L
BHE
0 0 _15
i Jla
vcc
-
READY
0 0 _15
v
I
WR
RD
"-
Note: In an HPC16040, the access time is 63 nsec.
Figure 11. Interfacing the WSMAP161 to a Microcontroller (x16 Configuration)
SYSTEM INTERFACE TO WSMAP168
The WSMAP168 has the following key features:
• 1 Meg address space decoding
• One output chip select when in the wordwide mode (FCSO)
• 40 ns access time
• Nine output chip selects when in the bytewide mode
• Byte operations in wordwide mode (BHE)
• Programmable Mapping Decoder (PMD™)
"-
A1S-A19
A1S-A19
v
. AD o_. s
ALE
vcc
t
"-
A
i'r- ----v
ARDY
G
"A8-15
v
t
t
I---
80186
-----"'----v
SRDY
LATCH
G
LATCH
WSMAPI68
(x16)
"-
Ao-7
v
BHE
f----
BHE
UCS
f---f---f----
CSl/Ax
WR
RD
TO
WE
~ USER
PORT
OE
°0_15
AD o_. s
~LCS
tt
"
v
MCSO_3
Figure 12. Interfacing the WSMAP168 to an 80186 in an Embedded Control Application (x16 Configuration)
10-13
Application Note 002
Figure 12 illustrates the interface between an 80186 and the WSMAP168 (in the x16 mode). The UCS (Upper Chip
Select) is connected to CSl/Ax on the WSMAP168. The PMD™ is programmed to locate a 1K x 16 EPROM slot in
the upper memory address space for a reset subroutine. The rest of the memory can be located as required by the
user (Figure 13).
lK x 16
EPROM RESET
PROGRAM
STORE
DATA
STORE
VECTOR
INTERRUPT
STORE
Figure 13. Optional Memory Mapping Using a WSMAP168 in an 80186 System
MApTII FAMILY SUPPORT
WSI provides the programming environment needed to program the MAp™ family of products. The MagicPro™ and
the MApTM Utility provides the user with the ability to program the PMD™ and the EPROM. The menu-driven software and hardware use the IBM PC as a platform and are easily installed and used. For additional information, consult your nearest WSI sales representative.
10-14
WAFERSCALE INTEGRA noN, INC.
SALES REPRESENTATIVES AND DISTRIBUTORS
11
SECTION INDEX
SALES REPRESENTATIVES AND DiSTRIBUTORS ......... ........................................ 11-1
For additional information,
call SOO-TEAM-WSI (SOO-S32-6974).
In California, call 415-656-5400.
--='====
-- -
~-==~
---~~='-iF
~-'
SALES REPRESENTATIVES AND DISTRIBUTORS
WAFERSCALE INTEGRA710N, INC.
DOMESTIC REPRESENTATIVES
Alabama
Florida
Massachusetts
Rep, Inc.
P.o. Box 4889
Huntsville, Alabama 35815
(205) 881-9270
Twx: 8107262102 Fax: (205) 882-6692
Sales Engineering Concepts, Inc.
776 South Military Trail
Deerfield Beach, Florida 33442
(305) 426-4601
CompTech, Inc.
1 Bridgeview Circle
Tyngsboro, Massachusetts 01879
(617) 649-3030
Twx: 62875819 Fax: (617) 649-3276
Arizona
Shefler-Kahn Company
2017 North 7th Street
Phoenix, Arizona 85006
(602) 257-9015
Twx: 9109510659 Fax: (602) 252-3431
California
Bager Electronics Inc.
17220 Newhope Street, Suite 209
Fountain Valley, California 92708
(714) 957-3367
Fax: (714) 546-2654
Bager Electronics Inc.
21133 Victory Blvd., Suite 225
Canoga Park, California 91303
(818) 712-0011
Fax: (818) 712-0160
Reider Associates
2660 Bernardo Avenue
Escondido, California 92025
(619) 741-0496
Twx: 9103221157 Fax: (619) 741-1392
Canada
Har-Tech Electronics, Ltd.
5000 Dufferin Street, Suite 216
Downsview, Ontario (Toronto)
Canada M3H 5T5
(416) 665-7773
Fax: (416) 665-7290
(514) 694-6110
Telex: 05-822679 (Montreal)
Fax: (514) 694-8501
(613) 726-9410 (Ottawa)
Fax: (613) 726-8834
Colorado
Waugaman Associates, Inc.
4800 Van Gordon Street
Wheat Ridge, Colorado 80033
(303) 423-1020
Fax: (303) 467-3095
Connecticut
NRG, Ltd.
63 Duka Avenue
Fairfield, Connecticut 06430
(203) 384-1112
Telex: 710-4572169 Fax: (203) 335-2127
Sales Engineering Concepts, Inc.
926 Great Pond Drive, Suite 2002
Altamonte Springs, Florida 32714
(305) 682-4800
Fax: (305) 682-6491
Sales Enginering Concepts, Inc.
15107 Nighthawk
Tampa, Florida 33625
(305) 682-4800
Georgia
Rep, Inc.
1944 Northlake Parkway #1
Tucker, Georgia 30084
(404) 938-4358
Twx: 8107660822 Fax: (404) 938-0194
Illinois
Sieger Associates
1350 Remington Road, Suite UV
Schaumburg, Illinois 60173
(312) 310-8844
Telex: 206248 Fax: (312) 310-9530
Indiana
MIS Sales & Associates
7319 West Jefferson Blvd.
Ft. Wayne, Indiana 46804
(219) 436-3023
Twx: 8103321414 Fax: (219) 436-3026
Iowa
Gassner & Clark Co.
P.O. Box 10 (ALL MAIL)
Hiawatha, Iowa 52233
1834 Blairs Ferry Road NE
Cedar Rapids, Iowa 52402
(319) 393-5763
Twx: 62950087 Fax: (319) 393-5799
Maryland
Logical Technology, Inc.
Empire Towers Building
7310 Ritchie Highway, Suite 609A
Glen Burnie, Maryland 21061
(301) 766-7444
Fax: (301) 760-2054
Michigan
Action Component Sales
22765 Heslip Drive
Novi, Michigan 48050
(313) 349-3940
Telex: 509359
Minnesota
Electronic Sales Agency, Inc.
8053 Bloomington Freeway
Bloomington, Minnesota 55420
(612) 884-8291
Telex: 4310015 Fax: (612) 884-8294
New Jersey
Astrorep Inc.
1479 Route 23
p.o. Box 1612
Wayne, New Jersey 07470
(201) 696-8200
Twx: 7109885847 Fax: (201) 696-6497
New Mexico
Shefler-Kahn Company
2709J Pan American Freeway NE
Albuquerque, New Mexico 87112
(505) 345-3591
Fax: (505) 345-3593
New York
Astrorep Inc.
103 Cooper Street
Babylon, New York 11702
(516) 422-2500
Telex: 286852 Fax: (516) 422-2504
Tri:rech Electronics Inc.
300 Main Street
East Rochester, New York 14445
(716) 385-6500
Twx: 62934993 Fax: (716) 385-7655
Tri:rech Electronics Inc.
3215 East Main Street
Endwell, New York 13760
(607) 754-1094 (Binghampton)
Twx: 5102520891 Fax: (607) 785-4557
Tri-Tech Electronics Inc.
6836 East Genesee Street
Fayetteville, New York 13066
(315) 446-2881 (Syracuse)
Twx: 7105410604 Fax: (315) 446-3047
11-1
m
Sales Representatives and Distributors
DOMESTIC REPRESENTATIVES (Continued)
Tri·Tech Electronics Inc.
14 Westview Drive
Fishkill, New York 12524
(914) 897·5611 (Hudson Valley)
Twx: 62906505
North Carolina
Rep, Inc.
2500 Gateway Centre Blvd., #400
Morrisville, North Carolina 27560
(919) 851·3007
Twx: 821765 Fax: (919) 481·3879
Rep, Inc.
Independence Office Park
6407 Idlewild, Suite #425
Charlotte, North Carolina 28212
(704) 563·5554
Twx: 821765 Fax: (704) 535·7507
Ohio
G & H Sales Company
7754 Camargo Road
Cincinnati, Ohio 45243
(513) 272·0580
Fax: (513) 272·0582
G & H Sales Company
17600 Detroit Road, #409
P.O. Box 79191
Lakewood, Ohio 44107
(216) 226·6800 (Cleveland)
Oregon
Thorson Company Northwest
6700 S.W. 105th Avenue
Beaverton, Oregon 97005
(503) 644·5900
Telex: 294835 Fax: (503) 644·5919
Texas
Southwestern Technical Sales
3010 lBJ Freeway, #860
Dallas, Texas 75234·7704
(214) 243·0180
Telex~,797334 Fax: (214) 243·3512
Southwestern Technical Sales
6200 Turkey Hollow
Austin, Texas 78750
(512) 440·0499
Pennsylvania
Tech·Com Marketing, Inc.
P.O. Box 460
Sellersville, Pennsylvania 18960
(215) 723·0820
Fax: (215) 723·2861
Utah
Butterworth Marketing
302 West 5400 South, Suite 204
Murray, Utah 84107
(801) 268·2244
Fax: (801) 268·8344
Tennessee
Rep, Inc.
113 South Branner Street
P.O. Box 728
Jefferson City, Tennessee 37760
(615) 475·4105
Twx: 8105704203 Fax: (615) 475·6340
Washington
Thorson Company Northwest
12301 N.E. 10th Place, Suite 260
Bellevue, Washington 98005
(206) 455·9180
Twx: 9104432300 Fax: (206) 455·9185
Time Electronics
9751 Independence Avenue
Chatsworth, California 91311
(818) 998·7200
Wyle Laboratories
9525 Chesapeake Drive
San Diego, California 92123
(619) 565·9171
Time Electronics
8525 Arjons Drive, Suite A
San Diego, California 92126
(619) 586·1331
Colorado
Time Electronics
7399 S. Tucson Way, Suite A7
Englewood, Colorado 80112
(303) 799·8851
DOMESTIC DISTRIBUTORS
Alabama
Pioneer
4825 University Square
Huntsville, Alabama 35805
(205) 837·9300
Time Electronics
4801 University Square
Huntsville, Alabama 35816
(205) 721·1133
Arizona
Time Electronics
1203 West Geneva Drive
Tempe, Arizona 85282
(602) 967·2000
Wyle laboratories
17855 North Black Canyon Highway
Phoenix, Arizona 85023
(602) 866-2888
California
Time Electronics
370 S. Crenshaw Blvd., Suite E·104
Torrance, California 90503
(213) 320-0880
Time Electronics
1339 Moffett Park Drive
Sunnyvale, California 94089
(408) 734·9888
11·2
Time Electronics
2410 E. Cerritos Avenue
Anaheim, California 92806
(714) 937·0911
Wyle laboratories
3000 Bowers Avenue
Santa Clara, California 95051
(408) 727·2500
Wyle Laboratories
11151 Sun Center Drive
Rancho Cordova, California 95670
(916) 638·5282
Wyle Laboratories
17872 Cowan Avenue
Irvine, California 92715
(714) 863·9953
Wyle laboratories
26677 West Agoura Road
Calabasas, California 91302
(818) 880·9001
Wyle laboratories
451 East 124th Street
Thornton, Colorado 80241
(303) 457·9953
Connecticut
Pioneer
112 Main Street
Norwalk, Connecticut 06851
(203) 853·1515
Time Electronics
1701 Highland Avenue
Cheshire, Connecticut 06410
(203) 271·3200
Florida
Pioneer
221 North Lake Blvd.
Altamonte Springs, Florida 32701
(305) 834·9090
Sales Representatives and Distributors
DOMESTIC DISTRIBUTORS (Continued)
Pioneer
6745 Military Trail
Deerfield Beach, Florida 33441
(305) 428-8877
Time Electronics
6610 NW 21st Street
Ft. Lauderdale, Florida 33309
(305) 974-4800
Time Electronics
4405 Vineland, Suite C15
Orlando, Florida 32811
(305) 841-6565
Georgia
Pioneer
5835 B Peachtree
Corners East
Peachtree Crossings
Business Park
Norcross, Georgia 30092
(404) 448-1711
Time Electronics
5555 Oakbrook, Suite 535
Norcross, Georgia 30093
(404) 448-4448
Illinois
Pioneer
1551 Carmen Drive
Elk Grove Village, Illinois 60007
(312) 437-9680
Out-of-state: 800-323-0360
Time Electronics
945 N. Edgewood, Suite G
Wooddale, Illinois 60191
(312) 350-0610
Indiana
Pioneer
6408 Castleplace Drive
Indianapolis, Indiana 46250
(317) 849-7300
In state: 800-382-5503
IL-KY-MO: 800-428-9128
St. Louis: (314) 241-9232
Kansas
Pioneer
10551 Lackman Road
Lenexa, Kansas 66215
(913) 492-0500
Fax: (913) 492-7832
Maryland
Time Laboratories
9051 Red Branch Road
Columbia, Maryland 21045
(301) 964-3090
Massachusetts
Pioneer
44 Hartwell Avenue
Lexington, Massachusetts 02173
(617) 861-9200
Out-of-state: 800-225-8344
Time Electronics
lOA Centennial Drive
Peabody, Massachusetts 01906
(617) 532-6200
Michigan
Pioneer
13485 Stamford
Livonia, Michigan 48150
(313) 525-1800
Ann Arbor: (313) 455-9090
In-state: 800-624-5800
Pioneer
4505 Broadmoor Avenue, S.E.
Grand Rapids, Michigan 49508
(616) 698-1800
In-state: 800-482-0119
Minnesota
Pioneer
7625 Golden Triangle Drive, Suite G
Eden Prairie, Minnesota 55343
(612) 944-3355
Twx: 9105762738 Fax: (612) 944-3794
Time Electronics
4445 W. 77th Street, Suite 216
Edina, Minnesota 55435
(612) 835-1250
Missouri
Time Electronics
330 Soverign Court
St. Louis, Missouri 63011-4491
(314) 391-6444
New Jersey
Pioneer
45 Route 46
Pine Brook, New Jersey 07058
(201) 575-3510
Time Electronics
Montville Ind'i Park #3
55 Route 46
Pinebrook, New Jersey 07058
(201) 882-4611
New York
Pioneer
840 Fairport Park
Fairport, New York 14450
(716) 381-7070
In-state: 800-822-0885
Pioneer
60 Crossways Park West
Woodbury, New York 11797
(516) 921-8700
Pioneer
1806 Vestal Parkway E.
Vestal, New York 13850
(607) 748-8211
In-state: 800-252-1278
Time Electronics
70 Marcus Blvd.
P.O. Box 11248
Hauppauge, New York 11788
(516) 273-0100
Time Electronics
6075 Corporate Drive
East Syracuse, New York 13057
(315) 432-0355
North Carolina
Pioneer
9801 A. Southern Pine Blvd.
Charlotte, North Carolina 28210
(704) 527-8188
Time Electronics
Industry Drive
Oxford, North Carolina 27565
(919) 693-5166
Time Electronics
9800 L. Southern Pine Blvd.
Charlotte, North Carolina 28210
(704) 522-7600
Ohio
Pioneer
4800 E. 131st Street
Cleveland, Ohio 44105
(216) 587-3600
In-state: 800-362-9127
Pioneer
4433 Interpoint Blvd.
Dayton, Ohio 45424
(513) 236-9900
In-state: 800-762-7810
KY: 800-543-5113;
Cincinnati: (513) 628-1072
Columbus: (614) 221-0043
Time Electronics
6175H Shamrock Court
Dublin, Ohio 43017
(614) 761-1100
m
Oregon
Time Electronics
16125 S.w. 72nd Avenue
Portland, Oregon 97224
(503) 684-3780
Wyle Laboratories
5250 N.E. Elam Young Parkway
Suite 600
Portland, Oregon 97123
(503) 640-6000
11-3
Sa'es Representatives and Distributors
DOMESTIC DISTRIBUTORS (Continued)
Pennsylvania
Pioneer
261 Gibraltar Road
Horsham, Pennsylvania 19044
(215) 674-4000
Pioneer
259 Kappa Drive
Pittsburgh, Pennsylvania 15238
(412) 782-2300
WV: 800-245-0786
Erie: 800-242-0217
Time Electronics
600 Clark Avenue
King of Prussia, Pennsylvania 19406
(215) 337-0900
lItxas
Pioneer
9901 Burnet Road
Austin, Texas 78758
(512) 835-4000
San Antonio: 736-5544
Pioneer
13710 Omega Road
Dallas, Texas 75244
(214) 386-7300
Metro: 263-3168
In-state: 800-492-9027
OK-AR: 800-527-0387
Pioneer
5853 Point West Drive
Houston, Texas 77036
(713) 988-5555
Lafayette-Baton RougeNew Orleans: 800-231-9965
Time Electronics
10450 Stancliff Blvd.
Houston, Texas 77099
(713) 530-0800
Time Electronics
1826-F Kramer Lane
Austin, Texas 78758
(512) 339-3051
Wyle Laboratories
2120-F West Braker Lane
Austin, Texas 78758
(512) 834-9957
Utah
Time Electronics
2446 Progress Drive
West Valley, Utah 84119
(801) 973-8181
Wyle Laboratories
1325 West 2200 South, Suite E
West Valley, Utah 84119
(801) 974-9953
Time Electronics
2210 Hutton Drive
Carrollton, Texas 75006
(214) 241-7441
Washington
Time Electronics
8601 Willows Road
Redmond, Washington 98052
(206) 882-1600
Wyle Laboratories
1810 North Greenville Avenue
Richardson, Texas 75083
(214) 235-9953
Wyle Laboratories
1325 West 2200 South, Suite E
West Valley, Utah 84119
(801) 974-9953
Wyle Laboratories
11001 South Wilcrest, Suite 100
Houston, Texas 77099
(713) 879-9953
Washington, D.C.
Pioneer
9100 Gaither Road
Gaithersburg, Maryland 20877
(301) 921-0660
Baltimore: (301) 792-7500
INTERNATIONAL DISTRIBUTORS
Germany
Tekelec Airtronic GmbH
Kapuzinerstrasse 9
8000 Munchen 2, West Germany
895164 0
Telex: 841522241 Fax: 49 89 516410
Finland
OY Comdax AB
Italahdenkatu 23 A
SF-00210 Helsingfors, Finland
857067 02 77
Telex: 857125876 Fax: 358 0674886
Denmark
Distributoren Inereiko, A1S
Silovej 18
DK-2690 Karlslunde, Denmark
453140700
Telex: 85543507 Fax: 45 3 146805
England
Micro Call Ltd.
Thame Park Road
Thame, Oxon 0)(9 3XD, England
44 84 421 5405
Telex: 851837457 Fax: 44 84 421 7185
Norway
OTE A1S
P.O. Box 102 Tveila
N-0617 Oslo 6, Norway
472269955
Telex: 85678955 Fax: 47 2 268305
Spain
Unitronics, S.A.
Plaza de Espana, 18
28008 Madrid, Spain
3412425204
Telex: 83122596 Fax: 34 1 248 4228
France
REA (Radio Equipements-Antares)
90, Rue De Villiers, B.P. 5
92300 Levallois Perret Cedex
France
1 4758 11 11
Telex: 842620630 Fax: 33 1 47 58 79 13
Sweden
Traco AB
P.O. Box 103
S-123 22 Farsta, Sweden
468930011
Telex: 85410689 Fax: 468 947732
Belgium, Luxembourg
Inelco
Avenue Des Croix De Guerre, 94
1120 Brussels, Belgium
3222160160
Telex: 84664475 Fax: 32 2 2166150
Austria, Switzerland
Bacher GmbH
Sendlingerstrasse 64
8000 Munich 2, West Germany
89265094
Telex: 8415214624 Fax: 49 89 2604133
Holland
Components & Systems Electronics B.V.
Wegastnaat 77
NL 2516 AN DEN HAAG, Holland
70474991
Telex: 84432655 Fax: 31 70 475598
Italy
Silverstar
20, Via Dei Gracchi
20146 Milano, Italy
3924996
Telex: 843332189 Fax: 39 2 435594
11-4
Sales Representatives and Distributors
INTERNATIONAL DISTRIBUTORS (Continued)
Israel
Vectronics
60 Medinat Hayehudim St.
P.O. Box 2024
Herzlia B 46120, Israel
972 52 556070
Telex: 922342579 Fax: 972 52 558508
Hong Kong
Components Agent Ltd.
Unti 2301C-2, Nan Fung Centre
298 Castle Peak Road
New Territories, Hong Kong
0-499-2688
Telex: 78030398 Fax: 852 0-4993123
Korea
Eastern Electronics, Inc.
151-22, Hwayang-Dong
Sungdong-Ku, Seoul, Korea
C.P.O. Box 1075
82 2 463-2266
Telex: 78727381 Fax: 82 2 465-2607
Japan
Nippon Imex Corporation
No.6 Sanjo Bldg. 5F
1-46-9 Matsubara
Setagaya-ku, Tokyo 156 Japan
321 4415
Telex: 781 23444 Fax: 81 3 325 0021
Taiwan
Sertek International, Inc.
3 FL, 135, Sec. 2
Chien Kuo N. Road
Taipei, 10479, Taiwan, R.O.C.
2-501-0019
Telex: 78523756
Australia
Energy Control
26 Boron Street
Sumner Park
Brisbane, OLD 4074, Australia
Phone 61-7-376-2955
Fax: 61-7-376-3286
Telex: 43778
South West Regional Sales
Beeper: 714/550-3062
17011 Beach Blvd., Suite 900
Huntington Beach, California 92647
(714) 843-9407
Fax: 714/841-9083
South East Regional Sales
101 Washington Street, Suite 14
Huntsville, Alabama 35801
(205) 539-7406
Fax: 205/539-7449
Kyocera Corporation
2-13-2 Tamagawadai
Setagaya-ku, Tokyo, 158 Japan
3-708-3111
Telex: 7812466091 Fax: 813-708-3372
WSI DIRECT SALES OFFICES
North East Regional Sales
239 Littleton Road, Suite 3C
Westford, MA 01886
(617) 692-4083
Fax: 617/692-4083
Midwest Regional Sales
33 West Higgins Road, Suite 2054
South Barrington, Illinois 60010
3121551-9062
Fax: 312/551-9063
Mid Atlantic Regional Sales
3 Neshaminy Interplex, Suite 301
Trevose, Pennsylvania 19047
(215) 638-9617
Fax: 215/245-4705
Northwest Regional Sales
47280 Kato Road
Fremont, California 94538
(415) 656-5400
Telex: 289225
Fax: 415/657-5916
For additional information or assistance, call 800.:rEAM-WSI (800-832-6974). In California, call 415-656-5400.
m
11-5
11·6
WAFERSCALE INTEGRATION, INC
47280 Kato Road , Fremont, CA 94538
415-656-5400
800-TEAM-WSI
Fax : 415-657-5916
Telex : 289255
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