1989_OEM_Boards_and_Systems_Hanbook 1989 OEM Boards And Systems Hanbook

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LITERATURE
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OEM BOARDS AND SYSTEMS HANDBOOK
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280407
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SYSTEMS QUALITY IRELIABILITY HANDBOOK
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210620

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E00029

CG/LiT/100188

About Our Cover:
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intJ
Intel the Microcomputer Company:
When Intel invented the microprocessor in 1971, it created the era of
microcomputers. Whether used as microcontrol/ers in automobiles or microwave
ovens, or as personal computers or supercomputers, Intel's microcomputers
have always offered leading-edge technology. In the second half of the 1980s, Intel
architectures have held at least a 75% market share of microprocessors at 16 bits and above.
Intel continues to strive for the highest standards in memory, microcomputer components,
modules, and systems to give its customers the best possible competitive advantages.

OEM BOARDS
AND SYSTEMS
HANDBOOK

1989

intJ

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors
which may appear in this document nor does it make a commitment to update the information contained
.
herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office 10 obtain the latest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel Products:
Above, BITBUS, COMMputer, CREDIT, Data Pipeline, ETOX,
FASTPATH, Genius, i, t, ICE, iCEL, iCS, iDBP, iDIS, 121CE, iLBX,
im, iMDDX, iMMX, Inboard, Insite, Intel, intel, Intel376, Intel386, Intel486,
intelBOS, Intel Certified, Intelevision, inleligent Identifier, inteligent
Programming, Intellec, Intellink, iOSP, iPDS, iPSC, iRMK, iRMX,iSBC,
iSBX, iSDM, iSXM, KEPROM, Library Manager, MAPNET, MCS,
Megachassis, MICROMAINFRAME, MULTIBUS, MULTICHANNEL,
MULTIMODULE, ONCE, OpenNET, OTP, PC BUBBLE, Plug-A-Bubble,
PROMPT, Promware, QUEST, QueX, Quick-Erase, Quick-Pulse
Programming, Ripplemode, RMX/80, RUPI, Seamless, SLD, SugarCube,
UPI, and VLSiCEL, and the combination of ICE, iCS, iRMX, iSBC, iSBX,
iSXM, MCS, or UPI and a numerical suffix, 4-SITE, 376, 386, 486.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered
trademark of Mohawk Data Sciences Corporation.
*MULTIBUS is a patented Intel bus.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
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@INTELCORPORATION 1988

CUSTOMER SUPPORT
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
Customer Support is I ntel's complete support service that provides I ntel customers with hardware support, software
support, customer training, consulting services and network management services. For detailed information contact
your local sales offices.
After a customer purchases any system hardware or software product, service and support become major factors in
determining whether that product will continue to meet a customer's expectations. Such support requires an international support organization and a breadth of programs to meet a variety of customer needs. As you might expect,
Intel's customer support is quite extensive. It can start with assistance during your development effort to network
management. 100 Intel sales and service offices are located worldwide - in the U.S., Canada, Europe and the Far
East. So wherever you're using Intel technology, our professional staff is within close reach.

HARDWARE SUPPORT SERVICES
Intel's hardware maintenance service, starting with complete on-site installation will boost your productivity from
the start and keep you running at maximum efficiency. Support for system or board level products can be tailored
to match your needs, from complete on-site repair and maintenance support economical carry-in or mail-in factory
service.
Intel can provide support service for not only Intel systems and emulators, but also support for equipment in your
development lab or provide service on your product to your end-user/customer.

SOFTWARE SUPPORT SERVICES
Software products are supported by our Technical Information Phone Service (TIPS) that has a special toll free
number to provide you with direct, ready information on known, documented problems and deficiencies, as well as
work-arounds, patches and other solutions.
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information
Phone Service), updates and subscription service (product-specific troubleshooting guides and; COMMENTS
Magazine). Basic support consists of updates and the subscription service. Contracts are sold in environments which
represent product groupings (e.g., iRMX® environment).

CONSULTING SERVICES
Intel provides field system engineering consulting services for any phase of your development or application effort.
You can use our system engineers in a variety of ways ranging from assistance in using a new product, developing
an application, personalizing training and customizing an I ntel product to providing technical and management
consulting. Systems Engineers are well versed in technical areas such as microcommunications, real-time applications, embedded microcontrollers, and network services. You know your application needs; we know our products.
Working together we can help you get a successful product to market in the least possible time.

CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering various aspects of system design and implementation.
In just three to ten days a limited number of individuals learn more in a single workshop than in weeks of self-study.
For optimum convenience, workshops are scheduled regularly at Training Centers worldwide or we can take our
workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course categories include:
architecture and assembly language, programming and operating systems, BITBUS™ and LAN applications.

NETWORK MANAGEMENT SERVICES
Today's networking products are powerful and extremely flexible. The return they can provide on your investment
via increased productivity and reduced costs can be very substantial.
Intel offers complete network support, from definition of your network's physical and functional design, to implementation, installation and maintenance. Whether installing your first network or adding to an existing one, Intel's
Networking Specialists can optimize network performance for you.

Table of Contents
Alphanumeric Index .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . .

SYSTEMS PRODUCTS
CHAPTER 1
AT-BUS Boards and Systems
AT-BUS BOARDS
iSBC 386AT Baseboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 386ATZ Baseboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 386AT-25 Baseboard. . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AT-BUS SYSTEMS
MicroSystem/ AT 301Z. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MicroSystem/ AT 302 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OEM AT Platforms Service and Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1-1
1-3
1-5
1-7
1-9
1-11

CHAPTER 2
Real-Time Systems and Software
REAL-TIME SYSTEMS
2-1
System 120 ..............................................................
System 310 AP ........ . . . . . . . . • . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-4
2-6
System 310 AP 386 Upgrac;le ................. . . .. . . . . . . .. .. . . .. . .. . .. . .. . . .
2-8
System 320 ..............................................................
System 520 .............................................................. 2-10
Custom Boards and Systems from Intel...................................... 2-14
OPERATING SYSTEM SOFTWARE
iRMK Version 1.2 Real-Time Kernel..........................................
2-17
iRMX I Operating System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
iRMX II Operating System. . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
System V /386 Operating System. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-52
Software Migration from iRMX 86 to iRMX 286 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-54
SOFTWARE DEVELOPMENT TOOLS
AEDIT Source Code and Text Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-85
iPAT Performance Analysis Tool. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
iRMX Languages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91
iRMX Source Control System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95
iRMX Toolbox ............................................................ 2-97
iRMX X.25 Communications Software. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99
iSDM System Debug Monitor ............................................... 2-101
Soft-Scope* II Source-Level Debugger. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 2-105

MULTIBUS® I PRODUCTS
CHAPTER 3
MULTIBUS® I Single Board Computers
iSBC 80/1 OB Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . .
3-1
iSBC 80/24A Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-8
3-18
iSBC 80/30 Single Board Computer.........................................
iSBC 186/03A Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
iSBC 86/35 Single Board Computer ........... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38
iSBC 88/25 Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
iSBC 88/40A Measurement and Control Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56
3-65
iSBC 86/05A Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 86/14 and 86/30 Single Board Computers.... .......................... 3-75
3-84
iSBC 286/1 OA Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 286/12, 286/14, and 286/16 Single Board Computers. . . . . . . . . . . . . . . . . . . . 3-94
iSBC 337A MULTIMODULE Numeric Data Processor.......................... 3-106
iSBC 86C/38 Single Board Computer........................................ 3-116
vii

Table of Contents (Continued)
iSBC 386/12 Series Single Board Computers................................. 3-119
iSBC 386/21/22/24/28 and 386/31/32/34/38 Single Board Computers. . . . . . . .. 3-123

CHAPTER 4

MULTIBUS® I Memory Expansion Boards
iSBC MM01, MM02, MM04, MM08 High-Performance Memory Modules..........
iSBC 012CX, 010CX and 020CX iLBX RAM Boards............................
iSBC 012EX, 01 OEX, 020EX, 040EX High-Performance RAM Boards. . . . . . . . . . . . .
iSBC 304128K Byte RAM MULTIMODULE Board.............................
iSBC 300A 32K Byte RAM MULTIMODULE Board .
iSBC 301 4K Byte RAM MULTIMODULE Board...............................
iSBC 302 8K Byte RAM MULTIMODULE Board ...............................
iSBC 314 512K Byte RAM MULTIMODULE Board... ..........................
iSBC 341 28-Pin MULTIMODULE EPROM ... .' . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 429 Universal Site Memory Expansion Board ............................
iSBC 519/519A Programmable I/O Expansion Board. . . . . . . .. . . . . . . . . . . . . . . . . .

4-1
4-5
4-10
4-14
4-17
4-20
4-22
4-26
4-28
4-31

CHAPTER 5
MULTIBUS® I Peripheral Controllers
iSBC 208 Flexible Diskette Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 214 Peripheral Controller. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 215 Generic Winchester Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 220SMD Disk Controller..............................................
iSBC 221 Peripheral Controller. . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . .

5-1
5-5
5-9
5-15
5-19

CHAPTER 6·

MULTIBUS® I Serial Communication Boards
iSBC 88/45 Advanced Data Communications Processor Board .................
iSBC 188/56 Advanced Data Communications Processor Board................
iSBC 534 Four Channel Communication Expansion Board . . . . . . . . . . . . . . . . . . . . . .
iSBC 544A Intelligent Communication Controller ..............................
iSBC 561 SOEMI Controller Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 548/549 Terminal Controllers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .

6-1
6-10
6-19
6-24
6-33
6-38

CHAPTER 7

MULTIBUS® I Digital and Analog 110 Boards
iSBC 517 Combination I/O Expansion Board..................................
iSBC 569 Intelligent Digital Controller. . . . . . . . . . . . ... . . . . . . .. . .. . . . . . . . . . . . . . . .

7-1
7-5

CHAPTERS
MULTIBUS® I System Packaging and Power Supplies
iSBC 604/614 Modular Cardcage Assemblies. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 608/618 Cardcages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
iSBC 661 System Chassis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYP 341 Card cage Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SYP 342 Peripheral Module ................................................

8-1
8-4
8-8
8-11
8-13

CHAPTER 9
MULTIBUS® I Architecture
MULTIBUS System Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iLBX Execution Bus ........................................................

9-1 .
9-13

MULTIBUS® II PRODUCTS
CHAPTER 10
MULTIBUS® II Single Board Computers
iSBC 386/116 and 386/120 MULTIBUS II Single Board Computers..............
iSBC 286/1 OOA MULTIBUS II Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . .
viii

10-1
10-9

Table of Contents (Continued)
iSBC 186/100 MULTIBUS II Single Board Computer. . . . . . . . . . . . . . . . . . . . .. . . . ..
MULTI BUS II PC Subsystem. .. .. .. . .. . .. . .... .. .. . .. .. . .. . . . . . .. . .. .. . . .. ..

10-18
10-27

CHAPTER 11
MULTIBUS® II Memory Expansion Boards
iSBC MM01, MM02, MM04, MM08 High-Performance Memory Modules. . . . . . . . . .
iSBC MEM/312, 310,320,340 Cache-Based MULTIBUS II RAM Boards. . . . . . . . .

11-1
11-5

CHAPTER 12
MULTIBUS® II Peripheral Controllers
iSBC 386/258 Peripheral Controller................................. ........
iSBC 186/224A MULTIBUS II High-Performance Multi-Peripheral
Controller Subsystem ............................................... , . . . .

12-1
12-3

CHAPTER 13
MULTIBUS® II Serial Communication Board
iSBC 186/410 MULTIBUS II Serial Communications Computer..... .............

13-1

CHAPTER 14
MULTIBUS® II System Packaging and Development Accessories
SYSTEM PACKAGING
14-1
iSBC PKG/606, PKG/609 MULTIBUS II Card cage Assemblies. . . . . . . . . . . . . . . . . .
iSBC PKG 902, PKG 903 MULTIBUS II iLBX Backplanes. . . . . . . . . . . . . . . . . . . . . . .
14-5
iSYP/500 MULTIBUS II System Chassis............................. ........
14-8
DEVELOPMENT ACCESSORIES
iSBC CSM/001 Central Services Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 14-10
iSBC LNK/001 MULTIBUS II to MULTIBUS I Link Board........................ 14-15
MULTIBUS II High-Performance General Purpose Test Fixture (GPTF) ........... 14-20

CHAPTER 15
MULTIBUS® II Architecture
DATA AND FACT SHEETS
MULTIBUS II iPSB Parallel System Bus......................................
MULTIBUS II Message Passing Coprocessor-82389..........................
MULTIBUS II iLBX II Local Bus Extension ....................................
TECHNICAL BRIEFS
Enhancing System Performance with the MULTIBUS II Architecture .............
Increasing System Reliability with MULTIBUS II Architecture. . . . . . . . . . . . . . . . . . ..
Geographic Addressing in the MULTIBUS II Architecture. . . . . . . . . . . . . . . . . . . . . ..
Message Passing in the MULTIBUS II Architecture ............................

15-1
15-15
15-17
15-23
15-27
15-32
15-38

iSBXTM BUS PRODUCTS
CHAPTER 16
iSBXTM Expansion Modules
iSBX GRAPHICS MODULES
iSBX 279 Display Subsystem ...............................................
iSBX PERIPHERAL CONTROLLERS
iSBX 217C 1,4-inch Tape Drive Interface MULTIMODULE Board ....... ~ . . .. . . . . .
iSBX 218A Flexible Disk Controller ......................................•...
iSBX DIGITAL AND ANALOG I/O BOARDS
iSBX 311 Analog Input MULTIMODULE Board................................
iSBX 328 Analog Output MULTIMODULE Board...............................
iSBX 350 Parallel I/O MULTIMODULE Board.................................
iSBX 488 GPIB MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . ..
iSBC 556 Optically Isolated I/O Board .......................................
iSBX SERIAL COMMUNICATION BOARDS
iSBX 351 Serial I/O MULTIMODULE Board. . .. . .. . .. . .. . .. . .. .. . . . . . . .. . . . . ..
ix

16-1
16:3
16-6
16-10
16-14
16-18
16-22
16-26
16-29

Table of Contents (Continued)
iSBX 354 Dual Channel Serial 1/0 MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . ..
iSBX ARCHITECTURE
iSBX 1/0 Expansion Bus ............................... , . . . . . . . . . . . . . . . . . ..

16-35
16-40

LOCAL AREA NETWORK PRODUCTS

CHAPTER 17
Local Area Network Boards and Software
OpenNET Local Area Network Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

17-1

BITBUSTM PRODUCTS

CHAPTER 18
Distributed Control Modules
BITBUS STARTER KIT
BITBUS Starter Kit ............................................ :...........
BITBUS OPERATING SYSTEM SOFTWARE
'
iDCX 51 Distributed Control Executive .......................................
BITBUS LANGUAGES AND TOOLS
DCS 100 BITBUS Toolbox..................................................
DCS 110, BITWARE DCS 120 Programmers Support Package. . . . . . . . . . . . . . . . ..
8051 Software Packages...................................................
ICE 5100/044 In-Circuit Emulator ......... ;.................................
BITBUS Software Development Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
BITBUS BOARDS
iSBX 344A BITBUS Intelligent MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . ..
iPCX 344A BITBUS IBM PC Interface Board ..................................
iRCB 44/10A BITBUS Digital 1/0 Remote Controller Board.....................
iRCB 44/20A Analog 110 Controller Board ...................................
iRCX 910/920 Digitall Analog Signal Conditioning Isolation
and Termination Panels..................................................
iRCX 900 Isolation Module................................ ..................
BITBUS COMPONENTS
8044 BITBUS Enhanced Microcontroller .....................................
8044AH/8344AH/8744AH High-Performance 8-Bit Microcontroliers .............

18-1
18-5
18-13
18-20
18-25
18-33
18-41
18-46
18-54
18-60
18-69
18-77
18-81
18-83
18"104

SERVICE AND SUPPORT

CHAPTER 19
Service and Support
Insite User's Program Library .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iRUG Description .........................................................
Systems Engineering .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Training. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Support .........................................................
Hardware Maintenance . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Software Support Services PC-DOS . . .. . .. .. . . . .. .. . . . .. . . . . . . . .. . .. . .. . ....
Network Services .........................................................
PC AT 386 Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
PC & Peripheral Hardware Mairitenance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..

19-1
19-5
19-6
19-8
19-1 0
19-12
19-14
19-16
19-18
19-20

Alphanumeric Index
8044 BITBUS Enhanced Microcontroller . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . ..
8044AH/8344AH/8744AH High-Performance 8-Bit Microcontrollers ....................
8051 Software Packages.........................................................
AEDIT Source Code and Text Editor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . .. . . . . .
BITBUS Software Development Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
BITBUS Starter Kit...............................................................
Custom Boards and Systems from Intel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Customer Training ...............................................................
DCS 100 BITBUS Toolbox . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
DCS 110, BITWARE DCS 120 Programmers Support Package.........................
Enhancing System Performance with the MULTIBUS II Architecture . . . . . . . . . . . . . . . . . . ..
Geographic Addressing in the MULTIBUS II Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
Hardware Maintenance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
ICE 51001044 In-Circuit Emulator..................................................
iDCX 51 Distributed Control Executive..............................................
iLBX Execution Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Increasing System Reliability with MULTIBUS II Architecture. . . . . . . . . . . • . . . . . . . . . . . . . ..
Insite User's Program Library ............................................... :......
iPAT Performance Analysis Tool ...................... ,............................
iPCX 344A BITBUS IBM PC Interface Board.........................................
iRCB 44/10A BITBUS Digital 1/0 Remote Controller Board............................
iRCB 44/20A Analog 110 Controller Board .... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iRCX 900 Isolation Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iRCX 910/920 Digitall Analog Signal Conditioning Isolation
and Termination Panels ........................................................ .
iRMK Version 1.2 Real-Time Kernel ................................................ .
iRMX I Operating System ........................................................ .
iRMX II Operating System ........................................................ .
iRMX Languages .................................................. ; ............ .
iRMX Source Control System ..................................................... .
iRMX Toolbox ........................................................'.......... .
iRMX X.25 Communications Software ............................................. .
iRUG Description ............................................................... .
iSBC 012CX, 010CX and 020CX iLBX RAM Boards .................................. .
iSBC 012EX, 01 OEX, 020EX, 040EX High-Performance RAM Boards .................. .
iSBC 186/03A Single Board Computer ............................................ .
iSBC 186/410 MULTIBUS II Serial Communications Computer. " ..... , ............... .
iSBC 186/100 MULTIBUS II Single Board Computer ................................ ','
iSBC 186/224A MULTIBUS II High-Performance Multi-Peripheral
Controller Subsystem ......................................................... .
iSBC 188/56 Advanced Data Communications Processor Board ...................... .
iSBC 208 Flexible Diskette Controller .............................................. .
iSBC 214 Peripheral Controller ................................................... .
iSBC 215 Generic Winchester Controller ........................................... .
iSBC 220 SMD Disk Controller .................................................... .
iSBC 221 Peripheral Controller ................................................... .
iSBC 286/10A Single Board Computer ............................................ .
iSBC 286/12,286/14, and 2~6/16 Single Board Computers .......................... .
iSBC 286/1 OOA MULTIBUS II Single Board Computer ............................... .
iSBC 300A 32K Byte RAM MULTIMODULE Board .................................. .
iSBC 301 4K Byte RAM MULTIMODULE Board ..................................... .
iSBC 302 8K Byte RAM MULTIMODULE Board ..................................... .
iSBC 304 128K Byte RAM MULTIMODULE Board ................................... .
iSBC 314 512K Byte RAM MULTIMODULE Board ...... , ............................ .
xi

18-83
18-104
18-25
2-85
18-41
18-1
2-14
19-8
18-13
18-20
15-23
15-32
19-12
18-33
18-5
9-13
15-27
19-1
2-87
18-54
18-60
18-69
18-81
18-77
2-17
2-24
2-41
2-91
2-95
2-97
2-99
19-5
4-5
4-10
3-27 .
13-1
10-18
12-3
6-10
5-1
5-5
5-9
5-15
5-19
3-84
3-94
10-9
4-14
4-17
4-20
4-14
4-22

Alphanumeric Index (Continued)
iSBC 337A MULTIMODULE Numeric Data Processor .................................
iSBC 341 28-Pin MULTIMODULE EPROM .................... ,.....................
iSBC 386/116 and 386/120 MULTIBUS II Single Board Computers ................. ' ...• '
iSBC 386/12 Series Single Board Computers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iSBC 386/21/22/24/28 and 386/31/32/34/38 Single Board Computers ...............
iSBC 386/258 Peripheral Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. .
iSBC 386AT Baseboard ..........................................................
iSBC 386AT-25 Baseboard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . .
iSBC 386ATZ Baseboard .........................................................
iSBC 429 Universal Site Memory Expansion Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 517 Combination I/O Expansion Board........................................
iSBC 519/519A Programmable I/O Expansion Board.................................
iSBC 534 Four Channel Communication Expansion Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 544A Intelligent Communication Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 548/549 Terminal Controllers ...................... , . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 556 Optically Isolated I/O Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
iSBC 561 SOEMI Controller Board ...................... ;............. ... ..........
iSBC 569 Intelligent Digital Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .... .. . . . . . . . . . . .
iSBC 604/614 Modular Cardcage Assemblies. . . . . . . . . . . . . . . . . . . . .. . .. . . . . . . . . . . . . . .
iSBC 608/618 Card cages ...............................•........... " . . .. . . . . . . . . .
iSBC 661 System Chassis. . . . . . . . . . . . . . . . . . . . . . . .. . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 80/10B Single Board Computer...............................................
iSBC 80/24A Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. .. . . . . . • . . . . .
iSBC 80/30 Single Board Computer ............................................ ;...
iSBC 86/05A Single Board Computer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 86/14 and 86/30 Single Board Computers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 86/35 Single Board Computer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iSBC 86C/38 Single Board Computer .. " ...................... ; . . . . . . . . . . . . . . . . . . . ..
iSBC 88/25 Single Board Computer...................................... ..........
iSBC 88/40A Measurement and Control Computer ............................. ; .. . . .
iSBC 88/45 Advanced Data Communications Processor Board ... . . . . . . . . . . . . . . . . . . . . .
iSBC CSM/001 Central Services Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . .. . . . . . ..
iSBC LNK/001 MULTIBUS II to MULTIBUS I Link Board ..............................
iSBC MEM/312, 310, 320, 340 Cache-Based MULTIBUS II RAM Boards................
iSBC MM01, MM02, MM04, MM08 High-Performance Memory Modules. . . . . . . . . . . . . . . . .
iSBC MM01, MM02, MM04, MM08 High-Performance, Memory Modules.................
iSBC PKG 902, PKG 903 MULTIBUS II iLBX Backplanes..............................
iSBC PKG/606, PKG/609 MULTIBUS II Card cage Assemblies.........................
iSBX 217C %-inch Tape Drive Interface MULTIMODULE Board .... " . . . . . . . . . . . . . . . .. .
iSBX 218A Flexible Disk Controller ....................................... ; . . . .. . ...
iSBX 279 Display Subsystem . .. . .. .. .. . .. . .... . .. .. . .. . .. . .. .. .. . . . . . . .. . . .. . . . . ..
iSBX 311 Analog Input MULTIMODULE Board.. . . . .. .. . .. . .. . .. .. .. .. .. . .. . . .. .. . . ..
iSBX 328 Analog Output MULTIMODULE Board.....................................
iSBX 344A BITBUS Intelligent MULTIMODULE Board ................................
iSBX350 Parallel I/O MULTIMODULE Board ........................................
iSBX 351 Serial I/O MULTIMODULE Board .........................................
iSBX 354 Dual Channel Serial I/O MULTIMODULE Board. . . . . . . . . . . . . . . . . . . . . . . . . .. ..
iSBX 488 GPIB MULTIMODULE Board .............................................
iSBX I/O Expansion Bus.................................................... ......
iSDM System Debug Monitor .................................................... "
iSYP/500 MULTIBUS II System Chassis............................................
Message Passing in the MULTIBUS II Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. ..
MicroSystem/ AT 301 Z ............................... ;...........................
MicroSystem/ AT 302. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . .
xii

3-106
4-26
10"1
3-119
3-123
12-1
1-1
1-5
1-3
4-28
7-1
4-31
6-19
6-24
6-38
16-26
6-33
7-5
8-1
8-4
8-8
3-1
3-8
3-18
3-65
3-75
3-38
3-116
3-47
3-56
6-1
14-10
14-15
11-5
11-1
4-1
14-5
14-1
16-3
16-6
16-1
16-10
16-14
18-46
16-18
16-29
16-35
16-22
16-40
2-101
14-8
15-38
1-7
1-9

Alphanumeric Index (Continued)
MULTIBUS II High-Performance General Purpose Test Fixture (GPTF) ................. .
MULTIBUS II iLBX II Local Bus Extension .......................................... .
MULTIBUS II iPSB Parallel System Bus ............................................ .
MULTIBUS II Message Passing Coprocessor-82389 ............................... .
MULTIBUS II PC Subsystem ..................................................... .
MULTIBUS System Bus ......................................................... .
Network Services ............................................................... .
OEM AT Platforms Service and Support ........................................... .
OpenNET Local Area Network Family ............. , ............................... .
PC & Peripheral Hardware Maintenance ........................................... .
PC AT 386 Conversion .......................................................... .
Soft-Scope* II Source-Level Debugger ............................................ .
Software Migration from iRMX 86 to iRMX 286 ...................................... .
Software Support ............................................................... .
Software Support Services PC-DOS ............................................... .
SYP 341 Cardcage Module ............................................. ; ......... .
SYP 342 Peripheral Module ...................................................... .
System 120 .................................................................... .System 310 AP ................................................................. .
System 310 AP 386 Upgrade ..................................................... .
System 320 .................................................................... .
System 520 .................................................................... .
System V /386 Operating System ................................................. .
Systems Engineering ............................................................ .

xiii

14-20
15-17
15-1
15-15
10-27
9-1
19-16

1-11
17-1
19-20
19-18
2-105
2-54
19-10
19-14
8-11
8-13
2-1
2-4
2-6
2-8
2-10
2-52
19-6

AT-BUS
Boards and Systems

iSB(;®38tit\T PRODIJ(;T PROfiLE

POWERFIfL 32-BI'I' PERFORMIINCE WI'I'H PC 11'1' FLEXIBIU'I'Y
The iSBC386:\T is the board level core for an advanced 32·bit computing system. The board is form.
fit and function compatible with the PC AT. but with the 80386 as the CPU. provides 2·3 times the
performance of the PC AT. Additional features include on·board serial and parallel ports. two 32·bit
memory expansion slots. and a socket which supports the 80387 math coprocessor.
:\ system designed using the iSBC386AT emulates the PC AT but replaces the 16·bit, data paths of

the AT with 32·bit data handling for both memory and math interfaces. It also provides access to the
full capabilities of 80386 protected mode architecture. With the ability to address up to 16 MB of
memory. it is an excellent platform for UNIX* applications. The complete iSBC386AT board set
includes the system baseboard. and 32·bit memory expansion boards available in densities of
2 and 8 MB. It provides the capability to bring a high quality 32·bit DOS compatible system to
market quickly with a minimum of technical risk.

FEII'I'IfRES
ISBC3B6AT-BASEBOARD
• Intel 80386 CPU running at 16 MHz
• Socket for 16 MHz 80387 numeric
cuprocessor
• Phoenix Technologies ROM BIOS
• 512 KB of 32·bit R:\\1 on the baseboard and
two connectors for high speed 32·bit RAM
expansion
• Expansion bus interface: two PC·compatible
8·bit bus slots and four PC AT compatible 16·
bit bus slots

• Keyboard interface and Clock/calendar with
battery·backed CMOS memury
• Sixteen interrupts and Seven OMA (direct
memory access) channels
• One IBM·compatible serial RS·232
communication port and une Centrunics·
compatible parallel printer port

imJ-------------------l \1\ IS;] lrad('marllJf ~T&T PC -\11:-0 a 1rademark of II\M
Intel wrporalron assume~ no rt"spon:.ihllil} for Ihl' USl' o( All) rircuitry olhlor than (1f('Ullry l'mhutJll' .IJansion

INTEl. OIJ,4UTI'-I'OIJR GIJA.R,4NTEE
Intrl brings the saml' high standards to the drsign and
manufacture of the SAC3BIHT family that it is known for
in component. hoard. and system products.

Intt'! quality is designed in and then verified by rigorous
tt'sting in our state·o[·the·art ~;nvironmental Test
Lalxlratury.'
,

SERJlICE" SlJrPORT
flO day [,(·turn to factory warranty.
(>;uhalm~j warranty and service contracts [or fast part
['('pair arl' available on a worldwide basis.
Factol'~

st'I'vices inciudepart exchange and spare parts.

SPECIFICATIONS
, REFERENCE IfI,4NIJ,41.

ENl'IRONIfIENT
,\mbien!. Temperature
Operating
\on~lperating

iSBC386AT User's Guide Order" 14H56B·()02
0 tu + 3jOC
- -10 to + iQoC

Rl'latil(' Humidity
Operating.

010 85%. lioncomlensing at 55°C

,\ltitllcle
Operating

(J·IO,OOO [rl't

Shock

5(J (j liJr II msec, l/2 sine wall'

\ ibration

Random ,'al'iatioll

O· J.(JOO Hz

rHI'SIC,41. CH,4R,4CTERISTICS
Length
Width
.\pproximatl' \\('ight

12.0 in. (30-1.8 mm)
13.8 in. (350.5 mm)
18 oz. (510 gml

POWER REOIJIREMENTS
tw'8jIr

II'"

Tokl'811rr

+ii\±5%.
+ 12\ ± I(J%'
- 12 \. + IO%.
TOl\L

No.'a,.' Ca~a'
5.2 ,\
0.06.\
0.08 ;\

Wa"N

26.00
0.72
0.fJ()
27.68

\otl': Ours \OT include power [or expansion hoards.

1-2

ISBC® 38fiATZ BASEBOARD

HIGH PERFORMANCE 16 MHz 3B6™ BASEBOARD
The iSBC 386:\TZ is an advanced 16 MHz 80386, PC AT,compatible, baseboard, Two megabytes of
on-board memory running at zero wait states, and the ability to download Phoenix BIOS into RAM,
allow for excellent performance, Highly flexible, the board offers 32-bit memory expandable to
16 MS, and eight I/O expansion slots,
The unique design of the iSSC 3B6ATZ captures the full 32-bit capabilities of the powerful 80386
CPL', without sacrificing compatibility with the industry standard 8 MHz PC AT bus. Exhaustive
testing of numerous add-in boards and applications assures this compatibility, The iSBC 386 ATZ
delil'ers the OEM unsurpassed quality, flexibility, and performance in an off-the-shdr PC AT
compatible product.

ISBC@ 3B6ATZ BASEBOARD STANDARD FEATIJRES:
• Intel 80386 running at 16 MHz
• 2 ~IB of zero wait state on-board SIMM
memory
• Socket for a 16 MHz 80387 math
coprocessor
• Phoenix Technologies ROM BIOS

• B flexible I/O expansion slots:
-Two 32-bit slots or 8-bit PC slots
-Four 16-bit standard PC AT slots or B-bit PC
slots
-Two dedicated B-bit PC slots
• One serial and one parallel port

OPTIONS:
• 2 MB (iSBC 386 ME:M020) 32-bit, one
wait state, add-in memory board
• 8 ~IB (iSBC 386 MI!:M080) 32-bit, one
wait state, add-in memory board

• Ability to download Phoenix BIOS into RAM

intJ---------Inld Vlrp:lratum 3:-;:-;unll':'i nil n':-;I~)fI~ltllhl} for thl' USI' Hf iln) mrUllQ olin Itlan.,( irrlJitry rmhu(hcd in an Imel prodUlt, Nn ntht'r I'lf('Ult p.l1l'nl (i(l'flSt'S <11\'
Implllod.lnfllrmalion mn131nl'd ti!'I'I1n SUJ'Il'l'SI.'rk's 111'1.'\1011.'4) Pllhhshl'lj sJ~'rilll'illi()n~ (10 Lhrsr {)(>~ires (rum Inlcl ilnd IS suh~'rL In rhangl' \\o'ilhout nntu'~.

'\u~ust.

1086

Ordt'T \umbf:r: 2f10H3;'i-tXI2

1-3

SPECIFICATIONS
BASEBOIIRD

POWER RE(}IJIREMEN'I'S
~1I1~

Central Processor

.Intt'l 80386. 16

Floating·Point Pl"(x.'essor

Intl'180387. H\.\llIz

\Iain \Irmorl·
R:\\I
.
\Iaximum R:\\I
C~l'le Time
Data Bus \\idth
Ermr Detection
1/0

+5V±5 tKI

2 \IB on·hoarri
1.6 \18
12~ ns
32·Bits
Bit Parity

Onr sl'rial 110rt (asYIll'h.
RS2:12C. 9-pin mnm'ftor. :\T
eompa~ihll')

Ollt' parallt'IIMII·t(CmtrollifS
compatilJlt'. 2:i'llin CIlnm~'tor.
~Tcompatihl(')

8 ('~pansioll slot.s
2 32·bit or B-bit slots
2 8·bit slots
.r IG·bit or B·bit sl(~s

PHI'SICII" CHIIRIIC'I'ERIS'I'ICS
Length
\\idth
.\pproximate \\eight

tblla., ••" 'lU1era1K'e No.1_I CIIrre.'

12.0 in. (30U mm)
13.8 in. (350.5inin)
36.8
(10-:13 gm) .

oz.

+ 12V± 10%

(W6 A

-12V± 10%

0.08

[)()~S

0:72
0.96

TOTI\L

Nolr:

WaUtoi
36.50

7.3 A

:18.18

NOT indudr pO\wr for

~xpansi()n

hoards.

ENVIRONMEN'I'
Ambi~nt

Trmperature
Operating
Non·operating

Ow +55OC
-40to +7()OC

Relative Humidity
Operating

oto 85 % non condensing at 55°C

Altitude
Operating

()-I 0.000 feet

Shock

50 G for 11 msec. V2 sine wave

Vihration

Random variation
0·1.000 Hz

SERJ'lCE & SIJPPOR'I'
90 day return to factory warranty.
~:nhanrcd warranty and service contracts for fast part
repair are available on a worldwide basis.

F'actory services include part exchange and spare parts.

1-4

ISB(;@ 38fiAT-25 BASEBOARD

INTEl. 25 MHz 80386 PERFORMANCE-PC AT COMPATIBLE
The iSBC 386AT-25, based on Intel's 25 MHz H03Hti, offers ORMs the board level core to develop a
superior 32-bit computing system, Highly flexible and extremely powerful, the board offers eight 110
expansion slots and up to 24 MB of zero wait state memory in several configurations. Additional
features include !I 25 MHz 80387 math coprocessor socket, two serial ports, one parallel port, and a
real-time clock.
A system design using the iSBC 386AT-25 takes advantage of the full power of the 80386 at 25 MHz,
yet remains completely compatible with the industry standard 8 MHz PC AT bus. The iSBC 386AT-25
allows an OEM the opportunity to bring a high quality, superior performance system to market
quickly with a minimum of risk.
lSBC~

386AT-25 BASEBOARD FEATlJRES

• Intel 80386 running at 25 MHz
• Zero wait state performance provided by a
64K byte cache
• 1. 2, 4, or 8 megabytes on-board SIMM main
memory
• Phoenix Technologies ROM BIOS (optional
download into RAM)
• 8 flexible 110 expansion slots:
-Two 32-bit high performance
ur 16-bit PC AT
or 8-bit PC slots
-One dedicated 8-bit PC slot
-Five 16-bit PC AT or 8-bit PC slots

• Optional 32-bit 8 MB (iSBC ATMEM8) and
4 MB (iSBC ATMRM4) add-in cards allow
memory expansion to 24 MB
• Two IBM-compatible serial RS 232
communication ports
• One Centronics-compatible parallel printer
port
• Real-time clock with battery-backed CMOS
memory
• IBM AT compatible keyboard interface

intJ-------------IBM Is a trademark or InlctnatiufIi:Il

Bu~lness

Machines

Int/.'I Corporation assumes no responsibility ror the use 0( any circuitry oLhcr than circuitry embodied in an lntd product. Nil tither firruit pal.{'nt lir'l,'nst's art'
implied Information contained herein supt'rscdes pm.ioush published spccif'icaLiolis on these dC\lires rrom Intd % nnnrondl'nsing at 55°C

Altitude
Operating

0·10.000 feet

Shock

50 G for 11 mSI'C. V2

Vibration

Random variation
0·1.000 Hz

~ine

wave

SERVICE & SlJrroR'I'
FCC CFR 47 Part 15 Subpart J.
Class B
VDE OB71 Level B

COMr,,'I".'U'I'1'

90 day return to factory warranty.
Enhanced warranty and service contracts for fast part
repai!' are avaiJatJle on a worldWide basis.
Factory services include part exchange and spare parts.

An extensive list of applications and add·in cards has been
verified as compatible.

1·6

MICROSYSTEM/AT 301Z

'.""I11,',·',,,1,

, j 1 ../"._

, - ." l "

__a~r::"li-_' ./ 1 J."

.1". J '.

J l ,/ -,1']
"I.
, . , vl".1
• "_If •• ,

3:l-BIT SYSTEM PERFORMANCE WITH PC AT CAPABILITY
The MicroSystemlAT 301 Z offers the power of the Intel 80386 microprocessor with the flexibility of
the PC AT based architecture. This combination produces an OEM system well suited to high
performance applications such as computer aided design (CAD). computer aided engineering (CAE).
and advanced financial analysis which require greater processing and memory capability as well as
PC compatibility. With eight PC card slots. the system can be customized easily by OEMs using off·
the·shelf boards. operating systems alld application software.

STANDARD FEATlJRES:
• Intel 80386 processor running at 16 MHz.
o wait state
• 2 MB main memory
• Phoenix Technologies ROM BIOS
• 8 110 expansion slots
2 8·Bit PC XT
2 8·Bit PC XT or 32·Bit memory expansion
4 16·Bit PC AT

•
•
•
•

220 watt pOwer supply and chassis
Serial port
Centronics parallel port
Expansion capability for up to five half·
height. 5.25' peripheral devices.

OPTIONS:
• Intel 80387 Floating·Polnt coprocessor
• 2 MB and 8 MB 32·Bit memory expansion
boards (2 slots maximum)
• Zero memory option

• 40 MB Winchester disk drive
• 1.2 MB floppy disk drive
• Disk Controller with floppy or Winchester

intJ---------1nlr.1 (nrpnr8lion assumes no rcsponsmtlily ror t.Ile usc or any ClrtUlLI':1' oUlfr lhan clrculLrv ombodleQ In an Inwl product No oLher clrciJlL paLimlliccntICs arc
Implied. Information contained herein supersedes previously publl:;!it:d speciricaLlons OIllhcse dC\o'lres from Intel.
AuguSl. 19B8
Order Numhcr: 280821.{)O3
© Inlel OJrporalion 1968

1-7

SPECIFICATIONS
B.4SE SYSTEM

ENt'lllONIUENT

Central Processor

Intel 80386. 16 MHz

Floating-Point Prucessor

Intel 80387. 16 Mllz

Main Memory
RAM
Expansion RA~I
Maximum RAM
Cycle Time
Data Bus Width
Error Detectiun .
1/0

Floppy Disk Option

Slep Rate
Head Settling Time
Winchester Disk
t;nFormatted (',apacity
Average Access Time

2M Bytes on CPU bourn
2~1 l1ytes board.
8M Bytes board
16M Byles
125ns
32-Bits
Byte Parity
I serial porI (asynchlllllous.
RS232C. 9-pinl'Onllt'Clor)
I paraliel port (centronics
compatible. 2fl pin
connector)
fl expansion slots
5.25' f(K)tprint
High Density Floppy Dis~
Drive
UnFormatted Capacity 1.6 MB
6 milliseconds
15 millisecunds
5.25' Fooqlrint
40.fl MB Formatted
28ms typ

llE6IJt.4TIONS
Meets or exceeds the Following requirements:
SaFety
US
Canada
Europe

L!L 478 5th Edition
CSA C22.2 No. 154
IEC 435 and VDE 0806

Europe

- :l~ to 60°C

Relative Humidity
System On:
System orr:

" to
" to

,\Itilud!'
Opt'!'utlng:
SLaLiC Dischargt':

IG.O to :12.2°C ((iO to 90 0 r)

H" 'Yo. nonconrlensing
[)ii %.

noncondensing

21 :J:l.6 meters (7000 Ft.)
ma.\imum
7.;; I\v ma\imunt

EtECTllIC.4L
AC Voltlext Day

Installation

.... YES2

It
a~

.~
el

Moatllly

....aaaal
". YES
". YES
.... YES

7:00 am·6:00 pm
Mon.·Fri.

.... YES

150 miles radius of service location. Zone mark ups apply.
2'legotiated

FttC'I'OIlt' SEIlYICES

Spres aad Sel'J'lfJe 'I'l'al,,'.

Intel has designed factory services to provide the OEM's
field service organization full access'to Intel's part
delivery and repair services. Standard Offerings are:

Spare parts for field replaceable units are available for
current Intel products and some obsolete parts,

• Enhanced warranties
• Spare parts
• Custom consulting

• Part repair
• Service training
• Service diagnostics

Service training for rield service personnel is available in
a classroom setting or self paced video tape modules.
Training modules may be customized to include unique
third party devices,

Eallllaf)ftl OEM WBl'l'aatles

Custo", Sel''''res

Two enhanced OEM warranty options provide low cost,
rapid part delivery and quick turn around time un part
repairs. The first option provides next day part delivery
for the Intel field replaceable units. The second option
will ship a replacement part 48 hours after reeeipt of the
defective part. Both warranty plans cover part
replacement for one year.

Intel's experienced field consulting staff can provide
speCific expertise to your engineering staff in areas of
UNIX· driver development, customized diagnostics and
system design support,

l'afJrol'Y Sel'J'lres
Ilepall'lReplaoome"ra
IleslflOase

It
aE
~I

!feJrtDay

System 30X
Plan A
Plan B

". YES

30X modules

.... YES

48 "flUl'
.... YES
.... YES

.... YES

Per Incident
3

4 wee"

Module level repair

1·12

Real. .Time
Systems and Software

IKMX® SYSTEM. 20

LOW-COST REIIL-TIME B03B6 SYSTEM FROM INTEL
The Intel System 120 delivers real·time capability to users demanding a IOW'C08t 8ystem for running
time·critical applications. The System 120 combines the rich functionality of the world's most
popular Real·Time Operating System with the power and speed of the 386" 32·M microprocessor.
Par the first time, the System 120 makes available the ability to host, on a standard computing
platform, real·time applications that have previously been impractical with other AT·Bus systems.
Applications developed for the System 120 can be moved easily to Intel's complete line of
MULTIBUS@ I and MULTIBUS II products, giving the user a broad spectrum of price, performance,
and functions fl'om which to choose.

FEIITIJRES:
• iRMX~ 11.3: a complete real·time operating
system: more than a kernel
• Intel 386'" low,cost AT·Bus system
• Development platform for iRMX applications
• Easy migration of applications to and from
MULTIBlJS systems
• 110 expansion for PC·AT" and PC boards
• iRMX 11.3 to DOS file exchange capability
• OpenN ET'" networking support.
• Intel 80387 numeric co·processor support

.lrIf_r
Sy_s_te_m__l_20__as__
an__iR_~_lX_~_d_e_w_lo~p_m_e_n_t_PI_at~fu_r_m_w_i_th
••'e'" ______1'the_he__addition
of a monitor, video adapter, and keyboard.
Intl'i Cur~lralilm flt>... UOH'S nu n.':ip"nslhillt~ fur lh(' ust' IIf £In) mfuitr~ IILilef tlliln l'iN'Ullr~ l'mhudk.'(j ill an Int.l'l/u'Iw,lufL Nil other flrmlt paLI'nllll't'nSl.':> ,If!'
Imlllil1J. Infurmallitn runlalf'll'd hen'ln ~llp(:rSl'dI's prt'~iuusl~ puhlislll'd SIJ(.'tlnrllllllfls on lht'S(' dl'\U'I'~ (rum InLt'lllnd Is suhll'rllu rhan~'t' 'AlthtmL nllllf(',
IKM.\. ML I.TltSl 5 1Hld opt'nN!,:T 3n'l't'glsL('red Iradl'fl13rk:-l IIf tnLd Corporatilln
·1'C·\1' IS a tradl'mark

(It

InLl'rnallunal Husin;,'t'>s ,l.1.:!rhltll.'s c..orvuraliull
.lUi'll', IHHR
Ord('r Numht'r: 2IiUIl-l!HKlt

2-1

fEATIlRES
IIlM~ 11.3:

tt COMr£ETE IlEttt.-TIME
twEll.4TINQ SYSTEM

Intel offers PC·AT add·in boards for the System 120 that
include: 2M·byte and 8M·byte 32·bit memory boards. the
OpenNET PCLlNK2 networking board and the iPex 344A
BITBUS" board. A standard keyboard is also available.

IRMX system software is used in more real·time designs
than any other operating system. There are over 500.000
CPUs worldwide running the iRMX Operating System.
making it the most widely accepted standard real·time
operating system for microprocessor·based designs.

Table • : System 120 Configurations
PRODIJCT
CODt:

The iRMX 11.3 Operating System provides a rich set of real·
time programming facilities not found in general·purpose
operating systems such as DOS. OS/2" or UNIX**. These
include:

SYS 120KITB40
SYS 120KITB80
SYS 120KITZ40*
SYS 120KITZBO'
SYS 120MBZ40'
SYS 120MBZBO*

11.:1

MfJIJI'IBfJS Det'elo".e.' 'I'_11d1:8
Toolkits are also available for the development of MULTI BUS
and component·level· applications. These are packaged with
a preconfigured operating system and allow development of
MULTI BUS I and MULTIBUS II applications on a low-cost
System 120 platform.

Development Toolkits

IRIIIll~

11.:1

FOR
IIIIJ"Tl8(JS~

...
...
...

...

You can develop applications directly on the system using
the System 120 Development Toolkit. In addition ,to the
special version of the iRMX 11.3 Operating System for the
System 120. the toolkit contains: PIJM 286 Compiler. ASM
assembler. AEDIT and a source level debugger. Soft·Scope'"
II. Intel also offers a number of compilers (C, F'ortran.
Pascal). performance and debug tools for iRMX 11.3.

C::PIJ RAItl

SO""'ARE
fOR
Sl'SRM t2IO

ttI·.yta

Syste. IflO Dere/o".e., 'I'oo/ldl:s

The System 120 is available with a number of memory and
mass storage options to fit a range of applications. These
include a basic system with 8 open slots. and a 40M·byte
hard disk system with an 80387 and noppy disk (see
Table I).

IRMll~

K·.yta

2
2

DISK

atO

Development Toolkits are available for development and
testing of applications. These toolkits contain the System
120 (in 40M·byte or 80M·byte configurations). iRMX 11.3 and
languages. an editor and a debugger (see Table 2). The
iRMX 11.3 Operating System includes a pre·conflgured
operating system. object modules and device drivers.
interface libraries. and a powerful tool for system
generation.

UN' COST PC-ttT BttSED
CONI'IQIJIlATIONS

c::oot:

lII-IIyta

EttSY ttrr£lCttTlON DE'fEWrMENT

F'inally. the iRMX 11.3 Operating System is highly
configurable. Its modular design allows you to select only
those functions and device drivers that are required. This
keeps memory requirements to a minimum. Guided by the
many examples in the System 120 Development Toolkit
documentation. you can add custom device drivers and
applications to the iRMX Operating System.

1'IlOD1Jc::T

aOIl a07

HARD

FWPPl'
DISK

• Available 04 1988.

The iRMX 11.3 Operating System also offers high
performance and code integrity. iRMX typically responds
100 times faster than general·purpose operating systems.
enabling real·time applications to keep up with the rapid
data and control now of machine and communication
interfaces. Code integrity is ensured through sophisticated
memory protection schemes.

MULTlBUS~

RAtti

SYP 120 16Z0·
SYP120l6Z40·

• Pl'!X!mptive. dynamic priority·based scheduling of
application tasks
• Bounded interrupt latency
• Multitasking support for real·time applications
• Inter·task communications through priority·based
mailboxes. semaphores. and regions
• Interrupt management with exception handling
• Cross or on·target development

TaMe 21: System 120 and

CPli

...
...

•Available 04 1988
BITBUS Is a registered trademark of Intel Corporation,

PIJItI :£86
ASIII
UDIT

:186
&:

FWPPl'

...

...
...
...
...
",

:1601(11 :I.ZItI.. 4011111 8OM1I
2.5
4.5
2
4
2
4

...
...

...

...
...

...

"0s/2 is a trademark of Microsoft.
UNIX is a trademark of AT&T.
Soft·Scope Is a trademark of Concurrent Sciences, Inc.

2-2

.ARB

11111

SOFl'S(;OPE 387

...
...
...
...
...

DISI(S

...
...

...

FEATURES
APPUCATION "'GRA'I'ION '1'0 HIGHER
PERFORMANCE SYSTEMS
Applications written for the System 120 can be easily
moved to the higher performance and functionality of
MULTIBUS I and MULTIBUS II designs. That's because the
System 120 iRMX 11.3 Operating System is binary
compatible with the MULTIBUS implementation of iRMX 11.3.
The iRMX 11.3 Operating System spans the entire Intel
systems product line. from the low·cost System 120 through
the MULTIBUS I System 320. to the high·end. multiprocessing MULTIBUS II products. Applications can easily
be rc-hosted on different bus architectures. allowing you to
create a group of products satisfying a Wide range of
customer performance requirements.

DOS APPUCATION COMPA'I'IBIUTY
The System 120 supports the DOS 3.X operating system as
well as iRMX 11.3. enabling you to use popular DOS
applications to process data collected in real time. The
System 120 hard disk can be divided into iRMX and DOS
partitions. allowing users to boot from either partition. A
System 120 utility allows transfer of iRMX files into a DOS

environment. DOS execution requires a customer·supplied
version of DOS. a video adapter. a monitor. and a keyboard.

WORLDWIDE SERVICE AND SIJPPORT
The System 120 is fully supported by Intel's worldwide staff
of trained hardware and software support engineers. Intel
also provides field application assistance. extensive iRMX
Operating System classes. maintenance services. and a help
hotline.
The System 120 Development Toolkits come with a 90-day
software warranty and a olle-year hardware warranty. In
volume. the System 120 comes with a 9(}day hardware
warranty. Other support packages are optionally available;
for more information please contact your local Intel Sales
Office.

INTEl. (}IJAl.ITY AND REl.IABIl.ITY
The System 120 is designed to meet the high standards of
quality and reliability that users have come to expect from
Intel products. The iRMX Operating System software has
undergone thousands of hours of testing and evaluation and
is one of the most stable operating systems in the industry
today.

SPECIFICATIONS
SYSTEM 120 BASE SYSTEM

ENJ'lIlONMENT

Central Processor

Intel 80386. 16 MHz

Floating·Point Processor

Intel 80387. 16 MHz··

Ambient Temperature
System On:
System Off:

15.6 to 32.2°C
- 34 to 60°C

Main Memory

2M Bytes on CPU Board·
0.5M Bytes on CPU Board
16M Bytrs
120 ns
32-Bits
Byte Parity

Relative Humidity
System On:
System Off:

Ii to 85 %. nOllcondensing
5 to 95 %. noncondensing

Maximum RAM
Cycle Time
Data Bus Width
Error Detection

110

8 expansion slots:

1 serial port (asynchronous.
RS232C. 9·pin connector)
1 parallel port (centronics
compatible. 25 pin connector)
2 32·or 8-bit slots
4 16-bit slots
2 8·bit slots'

REGlJl.ATIONS

Altitude
Operating:

2133.6 meters (7000 ft.) maximum

Static Discharge:

7.5 Kv maximum

ELECTRICAL
AC Voltage/Frequency

Switching power supply.
115 Vl60Hz or 230V/50 Hz;
convenience outlet

DC Power
+5V
+ 12 V

220 Watts
23.0 A maximum continuous
8.0 A maximum continuous; 11.0 A
maximum total for 15 seconds
0.5 A maximum continuous
0.5 A maximum continuous

Meets or exceeds the fOllowing requirements:
Safety
lJS
Canada
Europe
EMIIRFI
US and Canada
Europe

UL 478 5th E;dition
CSA C22.2 No. 154·M 1983
IEC 435 and VDE 0806
F'CC47 CFR Part 15 Subpart J
Class A
VDE 0871 Level A

'Available ()4. 1988
··Not included in SYP12016Z0

- 12V
-5V

DIMENSIONS
Length
Width
Height

441 millimeters (17.3 Inches)
541 millimeters (21.3 inches)
163 millimeters (6.5 inches)

WEIGHT
Base System:

2-3

20 kilograms (44 Ibs)

SYSTEM 310 AP

SYSTEM 310 tlP
The System 310 AP is faster than many minicomputers. Powerful dedicated processors for
communications and mass storage input/output control allow the 8 MHz 80286 CPU to concentrate
on application software. The System 310 AP is open. which means you can upgrade performance
and/or functionality in the future without purchasing a new system. The open system design protects
your investment from becoming obsolete. Open systems design also means easy system
customization with Intel and third·party add·in MULTIBUSllll\'rSl'(It'~ prnluusl~

Illlhllshl'rl :>lwnfll'Hllulls Ull thl'S,' ,kIln's lnom 11110'1.

;lIlfi"" rSSsor·hast'll System 320, the
widely used iRMX II real·time software. complete network service softwnrp and comprehensive
customer support capabilities to deliver, install and maintain a com pi&> sys!A.'m, Thp result is the
iRMX System 320 gives you the performance, and capabilities of a minicompu!A.'r utless than half the
l'OSL The system is especially suited for applications requiring real·time response and resuurce
control typically found in finanCial transaction, industrial automation. medical and communications
markets, The IRMX System 320 is also appropriate as the development l'nvironment for module·
based design,
IRItI~

St'Sf'EItl 320 FEAf'IJRES

• 80385 Based System
• iRMX Real·time Multitasking Operating
System
• Open System Architecture
• OpcnNP.T Local Area Networking
• Completf Installation. Service and Support
• \\'orldwide User Group Support
• Range of Configurations

intel·---------

IntI'! fJorptlr1lticll'lllll.'1U/Tlf':'l nn "'sflllnsltHlil~ for till' 1Il!j'ti lln~ mrllilr) ,.. hI'T than riJ'('Ullr~ l'nltl!Kti,'oI Hllm Inlt'l "r,~llll'l. \n ,~tl!T dr.'1111 11I11I'n! 1I(1'n~'s lin'
Implil'd. InrllrmmIEJf1I'flntntl1l~1 IM'rt'ltl ~lIIK'r'l-ll~I!'t; Jlt1'\iuosl~ IMlhllshid SI.~·lfll·ilt~II'ISlln 1111'111' d.... If'l'S rrllfll InWI

3Rfi IS 11 trmk'lIwrL til Irld C,lIrtMlI'iIlllIII
OI'lI~'1

if) IntdOIl'Jlllrrrrlun IOK1

2-8

s..'flh'IIIIM'r.lmllt
\uml_'I': 2Im:"1412·IKI2

FE .... TURES
IRIfIX@ II-REAt.-TIIfIE SOITWARE
The iRMX II operating system delivers real·time perfor·
mance. Designed to manage and extend the resources of the
System 320, this multitasking operating system provides
configurable resources ranging from interrupt management
and standard device drivers to data file maintenance
commands for human interface and program development.
The iRMX II facilitieA~ also include powerful utilities for easy,
interactive configuration and debugging,

SI'STEIfI :J20-AN OrEN SI'STEIfI
The IRMX System 320 is based un MliLTIBUS architecture.
(IEEE 796) industry standard system bus supported by
over 200 vendors providing over 2000 compatible products.
and on the iRMX II operating system composed of modular
layers, highly configurable for tailoring to target applica·
tions. A Wide range of popular industry standard high·level
languages are supported for application development.
Special configurations can be tailored by the user, by Intel's
Custom System Integration group or by Intel's authorized
Value Added Distribution Centers.

Ope_NETNNETWORKINGCArABIUTI'
Intel's OpenNET product family provides a complete set of
networking software and hardware that follows the Interna·
tional Standards Organization (ISO) Open Systems Intercon·
nect (OSI) model.
OpenNET Network File Access Protocol adheres to the IBM!
Microsoftllntel Core File Sharing ProtucQI specification,
providing transparent local/remote file access and file
transfer capability between Intel's complete line of systems

products. as well as with MSNET* and VAXlVMS** based
systems.
The System 320 distributes the transport protocol process·
ing to intelligent Ethernet controllers that host Intel's OSI·
oompliant iNA 960 Class 4 Transport software, thereby
unburdening the system CPU for greater performance.

INSTAUATION SERJ'ICE & SllrPORT
The Intel iRMX System 320 is backed by Intel's worldWide
servioe and support organization. Installation is available to
quickly get the system up and running. Total hardware and
software support is available, including a hotline number for
when the user needs help fast. Intel also provides hands-on
training workshops to give the user a thorough understand·
ing of the iRMX System 320. These workshops are
conducted at Intel training centers or customer sites
worldwide.

WORl.DWIDE IlSER GROllr SllrPORT
iRUG (iRMX User Group). provides members a user's library
of iRMX software tools and utilities, aceess to the group
bulletin buard, receipt of regularly published newsletters
and invitations to User Group Conferences. iRUG numbers
over 42 local chapters in 20 countries worldwide.

RANGE OF CONFIGIlRATIONS
Intel offers a wide range of configurations for the iRMX
System 320. Contact your local Intel reprcsentative fol'
further information.
• M:-iNl:1'Is OJ track'mark of MiC'rm\uH
•• \.o\XAMS i~" tradt'mark nf IJj~ilal j':quiIJITlI'flL CUfllor.1Lic.ln

SPECIFICATIONS
ENI'lRONIfIENT
Operating Temperature
Wet Bulb Temperature
Relative Humidity
Altitude

DIIfIENSIONS
lOoC to 40°C
26°C maximum
85 % at 40°C
Sea level to 10.000 feet

Height
Width
Depth
Weight

REGIlMTIONS
Meets or exceeds the fullowing requirements:
Safety
US
Canada
Europe

UL 478
CSA C22.2
IEC 435

EMURFI
US and Canada
Europe

FCC Class B Computing Device
VDE Limit Class B

ELECTRICAl.
DC Power Output
AC Power Input

435 wau maximum
88·132 VAC or 176·264 VAC,
. 47·63 Hz. single phase

2-9

8'
17.5'
22.25'
Approx. 55 lbs

iRMX®11 SYSTEM 520

IJNUJCKS THE POWER OF REAl-TIME MfJ"TlPROCESSING IN AN
INTE"t!> 386'" MfJ"TlBfJSt!> "OEM SYSTEM
The Intel iRM,\ II System 520 and MU1;I'IBUS II Sy~tl'm t\rcilil.{'cturt' (MSA) make it easy to unlock
tile puwer uf real-tillie llIultipmcessing. Tile Systelll 520 is the first in a family of hi~h performance,
real-time OEM systems W mmhinc Intel's open MSA arTilill'('turt', tht' IXllwrful 386 micmprocessor.
and the industry-leading iRMX II Real-Time Multitasking Operating System. Togl'ther, they pmvide
the first easily scalable, recomposable multiprocessor open bus system.
As an open OEM system, the System 520 allows users W adil to the basic system, 01' pur<'iJase till'
system's cuntents separately and repackage them into anoLilt'r enclosure. Intel's MSA provides this
capability via a structured set of open, standard intel'fuces and pmlo('ols t.hat. build on and are fully
compatible with the MULTJBUS II (IEEE 1296) bus standard. As a reSUlt, thl' ik~lX II System 520
provides new standards of ease of inte{lration, ease of use, and hoard compatibility for I.he OEM,

I'EATIJRES
• 386-based high performance \1ULTlBlIS II
multiprocessor OEM system
• iRMX II Real-Time Multitasking Operating
Svstem
• 386 Application Pmcessor ExpanSion (I to 4)
• High performance 386-based SCSI I/O
subsystem
• F.asy system expansion via Intel's
MULTIBUS II System Arrhitecturt: (MSA) &
iSBCO' family

• OpenNE'I" transparmt remote fill' sharing &
virtual terminal het\\'t~'n iSBC :lR6 processors
and IEEI': 802,:J net\\orked systems
• Hardware windOlH'd graphics/virtual
U~rminal support
• ikMX II d{wlopnlt'nt systems available

il1tel'------------:lflli

1,\

a Ir."ll'm:Jtl t~ ImO'! O'flKw:nll,n

Inli'l !;.lfrK1rlIIIU!l ,1""lIfl~~ flU ro""p"fl~ih,lll~ tnr Ih... II,,"' "I iln~ "IIl'Ullr~ ,~11"1 It~1I1 "II'_IIII~ ,'mlnHI"ll ill Ollll,llc'j rll'I!IL~ I 'II" '~ll"1 "1'1111 1',ll<'1I1 1111'11:;1':< a!1'
mll,III"J InlnrmS1 transport protocol processing to intelligent
Ethernet controllers hosting Intel's OSI compliant iNA 960
Class 4 Transport software. Inters OpenNET NetWOrk File
Access (NFA) protocol provides the upper layer functionality
of transparent local/remote file access and file transfer
between Intel's complete line of system products. as well as
MSNETo-based personal computers. The OpenNET NFA
protoCol adheres to the standard IBM*lMlcrosoft*/Intel Core
File Sharing protoCol specification.

WfMUW'DE SE.J'lfJE .tND slIPron .
The iRMX II System 520 is fully supported by Intel's
worldwide staff of trained hardware and software support
engineers. Intel also provides field application assistance.
extensive iRMX Operating SYRtem classes. maintenance
services. and a help hotline.
The System 520 OEM System products come with a
standard 9O-day hardware warranty. The iRMX II System
520 MlIl.TIRllS II Development System product comes
bundled with a one (1) year service warranty. This one year
warranty includes: hardware installation and one year of on·
site maintenance. software installation of the iRMX II
Operating System and 48 hours of TIPS phone support.

INTE" OIJ.tUTI' .tND .EU.tB'UI'I'
The System 520 Is designed to meet the high standards and
reliability that users have come to expect from Intel products. The iRMX Operating System software has undergone
thousands of hours of testing and evaluation. and is one of
the most stable operating systems in the Industry today:

·IBM is a rcgisWred trad"mark or Inwrnational BIINI",'l!.~ Mac~hin(oH Curl!.
·MIc..uNurt and MSNKT art' trnck'markN ur MicJ'Cl!!"fl CUl'IlClrnUun.

2-12

S PE e:: I FIe:: AT ION S
SYSI'ElfI 5:10 fJONI'I6IJIIA'I'IfJNIOPTION8'IitIIU I

System 520 OEM
Base Plus 110
System 520 OEM Base'.,..,.
System 520
Development System

Add-'
In.

~~-+--r--r~--~~~--+--r~--+-~

.,.",.",.",.",.

",. Add-'
In.

",.

'Contact Intel for configuration availability information.
IIIMX " SylJle_ lJ:ltJ 1Ie..el.".elll SYllle_
Sen",,,",

lJwIIeals:

SYP520RIBP

iRMX II Operating System
iRMXNet Networking Software
iNA 960 Networking Transport Software
SYRII Language Kit: (PLM & ASM 286. builderibinder)
C 286 compiler
iRMX 1hllbox
Softscope* II Source Level Debugger
AEDIT Editor
RUNIUDI for 86-based UDI Development Tools
iPPS PROM programmer support
iSBX 279 Graphics Interface Software
Open NET Virtual Terminal (VT)
·Sul\.~JJlI· Is a n'llISII'n~1 trad"mark ,t Cuncurn'nl Sci,,"('(," In,'.

MEGIJMI'IfJNS
Meets or exceeds the following requirements:
Safety
UL 478 5th Editon
US
CSA C22.2 No. 220
Canada
IEC 380 and VDE 0806
Europe
EMIIRFI
US & Canada
Europe

FCC47 eFR Part 15 Subpart J Class B
VDE 0871 Level B

E£EfJI'MIfJAI.
DC Power Output
AC Power Input

""DEllING INl'OIllflAI'ION

SYP520RI13
SYS520R IOKIT2

UfJENSING
Before iRMX II software will be shipped. a.customer must
sign (or have already signed) Intel's Software License
Agreement (SLA). Once the SLA is Signed. the customer Is
licensed for development. Customers who want to
"incorporate" portions of the iRMX II Object Code In an
application will have to Sign an Incorporation License which
clearly spells out the terms and conditions under which
incorporations can be made.
Contact your local Intel oft'ice for more information on the
System 520 and for iRMX licensing.
For more information or the number of your nearest Intel
sales olTice. call 800-548-4725 (gum,,,,!'I" 1l'll1",nsIMll) fUl'lIw uS""r ;II\~ Iin'u_r,1 ,gill', 11~lrl nnUllr} l'mhIMIIl~lln lm 11I11'l prcMliM1" """'_T 1"I1l'I'lllllIh'nllll\'U~':Illn'
1111,,11,11. Inr'II"f1'l!li.," 'l1l1lHl1'll11 hl1"n ~111""rSl1h'~ Jlrc"\IIMI"I> I'nhll~h,"!t ~., ir~""IMMI~ u" 111."1'1" I~" in':> h'~l' h~'" "nil I~ ~ullll~"1111 d~IIII.~· \l111~"11 n'~ln'
~l'I'nlnlHlUI

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2-14,

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2-15

~'-(-'-iJlI

IIU)

or Onlcl'

D Il\Il

12111tl

SERVICES
1fIOIJ'''t'.NG BOttIlDS '1'0 "IJNtJI'IONtiI.
IlEOIJ.IlEItIEN'I'S
Starting lI'ith exlstin{.l prnducts \\l' lI'ili d(wllljl
manufacturing and t~st prngrams til prO'.idp th(,
funl'lillnalit~· ~ou Sllt'fify. This inclnops jump.'r mlloifiralilln,
custllm firmll'arP and 1'.\1. programming, higil!'r r('liahilit~·
parts n'IJlart'ml'nl and Cllil!'r similar sprvil't's,

'NI'EGlltlI'lNG BOttIlDS tlND St'SI'EItIS
Inll'l qualit~ all()\\s ~oulO implement "dllck-to-stllck"
prtlllrams.lI'hill'lnlel cuslom capahiliti('s allll\\ ~IIU til
impl(,ITIl'nt "rlock·tll·apIJlicatilln" prngrams, \\1' ran intt'grall'
~IJUr n'qnin'nll'nts HIIH~h hl~lrd ami systl'm 11'$'1s. 'I'hl'
(,('!lulling ('ustnm tallnl't~1 hllamllr SVSlpm mllws fl1lm \$(11'
ciuck to ~lIl1r alJIJllcatinn ('n\il'tmm('lit lI'ith nil adciitillrnil
SlqlS (JI' inslx,'U(Jns t'(~llIll't~1. (&I' ngull' 1:)

tJIJS'I'01tl SOITWtlllE tlND "."",WtlIlE
\Inn' ('uslOIl1 appli.'ation lIIa~· al~o inl'iud(' ('uSlnm StJi'twal'l'.
(lUl'It'am will \\lII'" dust'l~ \1 ith ~ou on defining tlK'Sf.'
Stlll\\l!n' lIt,'ds allIl i(llpl('(II('nling thl'm, This allow!; Intt'l ttl
IN' ~OUl' lotall'uslolll SI'I'\ in' \l'ntllll', ('nsUI'ing a stl'tlng link
of sUPJMJI'1 fmm hal'dllall'llI Stllllllll'(',

tJIJS'I'01tl SEllt'ltJES I'tJtJIJSED ON t'0IJ1l
NEEDS
\nur I(.x'al SlII('S nllil'(' will 11111'1; with ~1l(1 ancluur IllUup til
dmra('h'I'i~(,·~')()I' I.,'hnil'al and husint's.~ n'llIil'('(III'nts, (lUi'
('ngint"I'S will \\lII'k with ~Oll(' I'ngim'(,I's In 1'1'\ i.'II· ~Olll'
funt1ionalul' 11,'hni('al sJM\'ilkatiuns ancllhl'n IlIIll)(ISt,' a
snlutiun Ihrrupts baSt'll on task priority. or implementing
statistical and diagnostic monitors.
• Interrupt management by immediately switching control
to user·written interrupt handlers when an interrupt
occurs. Response to interrupts is both fast and
predict.able. Most of the Kernel's system calls can be
executed directly from interrupt handlers.
• Time managl'mcnt providing single·shot alarms. repetitive
alarms. and a real·time clock. Alarms can be reset.
These time manageml~nt facilities can solve a wide range
of real·timl' programming problems. Single·shot alarms.
for example. can bl' used to handle timeouts. If the
timeout occurs. till' alarm invokt'S a user-written handler:
if the event oCl~Urs befort' tht' timeout. the application
simply delrtes the alarm. Other uses for the Kernel's time
management facilities include polling devices with
repetitive alarms. putting tasks to sleep for specified
periods (If time. 01' implementing a time-of-day clock .
• Semaphores. rt'~itlns. anti mailboxes for intertask
synchronization and t~lmmunication. Semaphores are
used for intertasle Signalling and synchronization. Regions
are special binary semaphores used to ensure mutual
exclusion and prevent dradlock when tasks contend for
control of system resources. A task holding a region'S
unit runs at the priority of the highest priority task
waiting for the rt'glnn's unit.
Mailboxes are queues that can hold any number of
messages and are used to exchange data between tasks.
Either data or pointers ran be scnt using mailboxes. The
Kernel allows mailbox messages to be of any length. High
" priority messages can be placed (jammed) at the front of
the message queue to ensure that they are received
before other messages queued at the mailbox.
To ensure that high priority tasks are not blocked by
lower priority t.asks, the Kernel allows ~sks to queue at
semaphores and mailboxes in priority order. The Kernel
also supports first·in. first·out tasle queuing.
• Memory pool manager that provides fixed and variable
block allocation. Memory can be divided into any number
of pools. Multiple memory pools might be created for
different speed memories or for allocating different size
blocks. Access to a memory pool for fixed,sized allocation
is always deterministic.
The Kernel·supplied memory manager works with flat.
segmented. and paged addressing. Users can write their
own memory manager to provide different memory
management policies or to support virtual memory.

2-18

FEATIlRES

SlJrPOIlT I'fIIl MlJ"TlrIlOCESSIN6
J'1.4 MlJ"TIBlJS~ " .4IlCHITECTlJIlE
The MULTIBUS (( architecture is designed to optimize
multiprocessor designs. This bus:
• Implements a loosely coupled architecture in which
interprocessor interrupts and data are exchanged via
messages transmitted as packets over the bus;
• Provides fast bus access;
• Allows interprocessor signalling at interrupt speeds from
as many as 255 sources;
• Provides data transfer rates of up to 32 megabytes per
second;
• Allows multiple communication seSSions to occur
simultaneously between processors; .
• Supports up to 21 CPU boards per chaSSiS with each
hoard providing the processor. memory. and 1/0 needcd
for Its portion of the application; and
• Provides registers-called Interconnect Space-on each
board that can be used for dynamic system conCiguration.
Two optional modules allow iR:'.1K Kernel applications to
make full use of the MULTIBUS (( architl'cturc. Thc first
module Implements message passing allowing the
application to have direct access to the message passing
hardware or to use Intel's MULTIBUS (( transport protncol.
The second module implements interconnect space access to
support dynamic system configuration.
These modules can be used to implement high performance
multiprocessor designs that:
• Break. a highly complex real·time application into multiple
lower complexity applications distributed across multiple
processors
.
• Distribute an application that's too CPU intensive for a
Single processor between several processors
• ProVide redundancy
• Dedicate processors tn specific tasks
• Provide interoperation with any operating system or
controller board that uses Intel's MULTI BUS (( transport
protocol, including the iRMX" 11.3. iRMK 1.2. and Intel
System V/386 operating systems.

1IMlD1t'.4IlE llE()lJIIlEIJIEN'I'S IIN/IJ
SlJrPOIlT
The iRMK Kernel requires only an 80386 microprocessor or
an 80376 embedded controller and sufficient memory for
itself and its application. Its design. however. recognizes that
many systems use additional programmable peripheral'
devices and coprocessors. The Kernel provides optional
device managers for:
•
•
•
•

The 80387 and 80387SX Numeric Coprocessors
The 82380 and 82370 Integrated System Peripherals
The 8254 Programmable Interval Timer
The 8259A Programmable Interrupt Controller

An application can supply managers for other devices and
coprocessors in addition to or In replacement of the devices
listed above.
The iRMK Kernel was designed to be programmed into
PROM or EPROM. making it easy to use in embedded
designs.
The iRMK Kernel can be used with any system bus
including the MULTIBUS I and MULTIBUS II busses. The
optional MUI:I'II3US II message passing and Interconnect
Space access modules use the Message Passing Coprocessor
(MPC). Till' Kernel provides managers to use the
82380/82370 Intt'{lrated System Peripherals or the 82258
Advanced D:'.1A controller with t.he MPC for message
passing,

SlJrroRT FOil THE INTE"3B6" liND
INI'E£376'" .4IlCnlI'ECTfJIlES
Thl' iRMK Kernl'l providl'S 32·bit. protl'cted mode 80386
anll 80376 Olll'l'ation, By lIl'lilUlt. the Kernel and iI.~
application I'Xt:l'utl' in a flat nwmory space of up to 4
gigahytes and in a single privilege level. Applications can
add support for any lIIixtun' of adllitional protected mode
features including:
•
•
•
•
•.

Any model of sC{lml'Rtation
Memory paging
Virtual memory
Multiple privilege levels
Call and trap gates

These protected mode features can be used to increase the
reliability of the application by using the processor's
hardware to;
• Protect against attempts to write beyond segment bounds
(to catch, for example, situations like stack overflow or
underflow)
• Allow only privileged or trusted code to access key
routines and data
• Isolate bugs to single mudules so that the rest of the
application and the Kernel are not corrupted
• Assign access rights to code and data
• Isolate address spaces
To use these features. the application manipulates tlie
proCessor's descriptor tables. Since the Kernel was designed
specifically to support 80386 and 80376 applications. it
provides an optional Descriptor Table manager that
Simplifies proteetl'd mode programming. This manager
provides system calls to read and write descriptor table
entries. to convert addresses from linear to physical and
vice versa. and to get a segment's selector.

2-1.9

FEATIJRES

Application

UserSupplied
System
Routines·

Language Interface Libraries

Kernel
Core
Modules

Kernel
Supplied
Device
Managers

Kernel
Optional
Modules

Hardware
ftpre t: iRMK'" Version 1.2. Real-Time Kernel Architecture
·User-supplied system routines would include interrupt handlers. user-written device managers. and similar routines.

iRMXII> 11.3
Operating
System

I
11

iRMK'"1.2
Real-Time
Kernel

Intel System V/386
Operating
System

MULTIBUSII> II Parallel System Bus
(IEEE 1296)

Terminal
Concentrator

I
Disk
Controller

npre Z:

The optional MULTIBUSII> II message passing modules give the iRMK'" 1.2 Version 'Sernel full multiprocessing
capabilities for distributing applications among processors and interoperating with oth~r operating systems.

2-20

FEtlTIlRES
.t MODIJMIl Ml€IlI'l'E€'I'IJRE I'OR
E.tSI' €lfS'I'OMIZ.t'l'1ON
The iRMK Kernel was designed for maximum flexibility so it
can be customized for each application. Each major
function-mailboxes. for example-was implemented as a
separate module. The Kernel's modules have not been linked
together and are supplied individually. You link the modules
you need for your application. Any module not used does
not need to be linked in. and does not increase the size of
the Kernel in your application. You can also replace any
optional Kernel module with one that implements specific
features required by your application. For example. you
might want to replare the Kernel'S memory manager with
one that supports virtual memory.
Table 1 lists the Kernel's modules.

0",...",

fM'e

hact1H8
• Task manager
• Time manager
• Interrupt
manager

•
•
•
•
•
•

1fIN.k8
Mailbox manager
Semaphore
manager
Memory Pool
manager
Descriptor Table
manager
MULTIBUS II
Message Passing
MULTIBUS II
Interconnect Space
Access

0",...", Del'b
".~

•
•
•
•

80387 & 80387SX
82380 & 82370
8254
8259A

DEVELOPING WI'I'H 'I'HE '''Mr
1lE.t£-'I'IME IlEIlNE"
iRMK Kernel applications can be written using any language
or compiler that produces code that executes in the 80386's
protooted mode or on the 80376. This independence is
achieved by using interface libraries. These libraries work
with the idiosyncrasies of each language-for example. the
ordering of parameters. The interface libraries translate the
call provided by the language into a standard format
expected by the Kernel. Intel provides interfare libraries for
our iC 386 and PUM 386 languages. The source code for
these libraries is provided so you can modify them to
support other compilers.
Intel's 80386 Utilities are used to link the Kernel's modules
and to locate the Kernel In memory. Applications written
with a oompiler that produces OMF386 object module
format can be linked directly to the Kernel for the highest
possible performanre. Alternately. applications written in
OMF386 or another object module format can access the
Kernel through a call gate mechanism included with the
Kernel.
Because the Kernel Is supplied as unlinked object modules.
applications can be developed on any system that hosts the
dewlopment tools that you will use.

€OMrIlEHENSII'E DEI'EUJrMEN'I'

'I'0OI. SlJrroR'I'
Intel provides a complete line of 80386 and 80376
development tools for writing and debugging iRMK Kernel
applications. These tools include:
Software:

Debuggers:

PUM 386 Complier
iC 386 Compiler
ASM 386 Assembler
RLL 386 Utilities
ICE" 386 and ICE 376
P·MON 386
D·MON 386

These tools run on IBM* PC AT systems and compatibles
running Pc. or MS·DOS* 3.X. The languages and utilities
also run on VAXNMS and MicroVAXNMS· systems. The
iRMK Version 1.2 Kernel software is available on IBM PC
format 51/4 inch. 360K byte diskettes.

IN'I'E" SlJrroll'l', €OIfSIJ"'I'ING, .tND
TR.tINING
With the iRMK Kernel you get the Intel386 architecture and
real·time expertise of Intel's customer support engineers. We
provide phone support. on· or off·site consulting.
troubleshooting guides. and updates. The Kernel includes 90
days of Intel's Technical Information Phone Service (fIPS).
Extended support and consulting are also available.

€ON'I'EN'I'S OF 'I'HE IRMr IlERNE£
DEI'EWrMEN'I'r.t€I£.tGE
The iRMK Kernel comes in a comprehensive package that
includes:
• Kernel object modules
• Source for the Kernel·supplled 82380 and 82370
Integrated System Peripherals: 8259A PIC: 8254 PIT; and
80387 and 80387SX Numeric Coprocessor device
managers
• Souroe for PUM 386 and iC 386 Interface libraries
• Souroe for the call gate interfare
o Souroe for sample applications showing:
-Structure of Kernel applications
-Use of the Kernel with application written in both PUM
386 and iC 386
-Compile. bind. and build sequenees
-Sample initialization code for the 80386
microprocessor
-MULTIBUS II message passing
-Applications written to execute in a flat memory space
and in a segmented memory space
• User Referenre Guide
• 90 days of Customer Support
·IBM Is a registered trademark of the International Business
Machines Corporation.
• M&DOS is a trademark of Microsoft Corporation.
• VAX is a registered trademark 01 Digital Equipment
Corporation. VMS is a trademark of Digital Equipment
Corporation.

2-21

SI'STEM C" ...... S
IRIfIK'" VERSION 1.2 MERNEL SYS'I'EIfI C/ULS'
KEMt;L INITIAUZATION
KN_initialize
Initialize Kernel
OBJt;Cf MlANAGt;Mlt;NT
KN_token_to_ptr
Returns a pointer to area holding
object
KN_currenLtask
Returns a token for the current
task
TASK MlANAGt;MlMT
KN_create_task
Create a task
KN_delete_task
Delete a task
KN_suspend_task
Suspend a task
KN_resume_task
Resume a task
KN_seLpriority
Change priority of a task
KN_geLpriority
Return priority of a task
INTt;RRlIPT MlAIUGt;Mlt;NT
KN_seUnterrupt
Specify interrupt handler
KN_stop_scheduling
Suspend task switching
KN_starLscheduling
Resume task switching
TlMlt; MlANAGt;Mlt;NT
KN_sleep
Put calling task to sleep
KN_create_alarm
Create and start Virtual alarm
clock
KN_reseLalarm
Reset an existing alarm
KN_delete_alarm
Delete alarm
KN_geUime
Get time
KN_seLtime
Set time
Notifv kernel that clock tick has
KN_tick
occurred
INTERTASK COMlMlliNICATION AND
SYNCHRONIZATION
KN_create_semaphore Create a semaphore
KN_delete_semaphore Delete a semaphore
KN_send_unit
Add a unit to a semaphore
KN receive unit
Receive a unit from a semaphore
KN=create_-mailbox
Create a mailbox
.
KN_delete_mailbox
Delete a mailbox
KN_send_data
Scnd data to a mailbox
KN_send_priority _data Place (jam) priority message at
head of message queue
KN_receive_data
Request a message from a mailbox
Mlt;MlORY MlANAGt;Mlt;NT
KN_create_pool
Create a memory pool
KN_delete_pool
Delete a memory pool
KN_create_area
Create a memory area from a pool
KN_delete_area
Return a memory area to a
memory pool
KN_geLpooLattributes Get a memory pool's attributp-s
Dt;SCRIPTOR TABU MlANAGt;Mlt;NT
KN_geLdescriptor_
Get a descriptor'S attributes
attributes
'
KN_seLdescriptoc
Set a descriptor's attributl's
attributes
Initialize local descriptor tahle
KN_initialize_LDT
(LOT)

KN_nulLdescriptor

Overwrite a descriptor with the null
descriptor

KN_initialize_
subsystem

Allows application to be divided
into multiple subsystems when
application interfaces to Kernel
through a call gate
Convcrt a linear address to a
pointer
CAlnVert a pointer to a linear
address
Get the selector for the data
segment
KN_geLcodt'_sclector Get the selector for the code
se,gmcnt
Converts a rminter that will be
hased on a user-sppdfled selector
82380, 82:1'70, AND 82119A PIC
MlANAGEMlt;NT
KN_initialize_PICs
Initialize the PICs
KN_masLslot
Mask out interrupts on a specified
slot
1!nmask interrupts on a sp('~ifjffi
slot
Signal the PIC that the interrupt on
a specified slot has been serviced
KN_new_masks
Change interrupt fIlaSks
KN_geLslot
Return the most important active
interrupt slot
82:180, 82:170, AND 8:£54 PIT
MlAIUGt;Mlt;NT
K'UnitiaJize_PIT
Initialize u PIT
KN_staI'LPIT
Start PIT counting
K:'LgeLPILinterval
Rctul'll PIT intl'rval
80:187 "NO 80:l87SX NlIltlt;RIC
COPROCt;SSOR MlANAGt;Mlt;NT
KN_initialize_NDP
Initialize an 80387 or 80387SX
Numeric Coprocessor
MllILTIBlIS@ .. MlESSAGt; PASSING
MlANAGEMIENT
KN_initialize_message_ Initialize the message paSSing
passing
module
KN_mp_workin~
Compute Size of work space needed
storage_size
for message passing
KN_scnd_tp
Send a transport message
KN_attach_rcceive_
Attach a receive mailbox
mailbox
KN_canceUp
Cancel a soliCited message or
request-response transaction
KN_send_dl
Send a data link message
KN_attacLprotocoL Attach a protocol handler
I
handler
KN_canceLdl
Cancel a data link butTer request
MllILTIBlIS@ II INTt;R(;ONNt;(;T SPi\Ct;
MlANAGt;Mlt;NT
KN_initialize_
Initialize the interconnect module
intercon nect
KN_geLinterconnect
Get the value of an interconnect
register
KN_seUnterconnect
Set the value of an interconnect
register
KN_IocaLhosUD
Get the host 10 of the local host

2-22

ORDERING INFORltIATION

RMK

iRMK Version 1.2 Development
Software

iRMK Version 1.2 Kernel

RMKDEVP
RMKDEVC

iRMK Version 1.2 Developer's
Kit

iRMK Version 1.2 Kernel
PUM 386 or IC 386 Compliers
ASM 386 Assemhler
RLL 386 Utilities

SSC-430

Technical Information Phone
Support

Phone support
;Comments Magazine, Troubleshooting Guides

CONSULTIDAILY
CONSULTILT

On- or orr-site consulting on IRMK 1.2 Kernel or other Intel products by Intel systems engineer.
Available on a daily or long term basis.
iRMK Real-time Kernel

Customer Training Workshop

80386 Programming Using
ASM 386

Customer Training Workshop

80386 System Software

Customer Training Workshop

80386 System Hardware
Design

Customer Training Workshop

2-23

intJ

iRMX® I OPERATING SYSTEM

•

Real-Time Processor Management for
Time-Critical 8086, 8088, 80186, 80188,
and 80286/386TM (Real Address Mode)
Applications

•
•
•
•

On-Target System Development with
Universal Development Interface (UDI)
Conflgurable System Size and Function
for Diverse Application Requirements
All IRMX® I Code Can Be {P}ROM'ed to
Support Totally Solid State Designs
Configured Systems for the 8086,
80286, and 386 Processors in the Intel
System 300 Series Microcomputers

Multi-Terminal Support with Multi-User
• Human
Interface
Range of Device Drivers
• Broad
Included for Industry Standard
MULTIBUS® Peripheral Controllers
of 8087, 80287, and 80387
• Support
Processor Extension
Powerful Utilities for Interactive
• Configuration
and· Real-Time
Debugging

The iRMX I Operating System is an easy-to-use, real-time, multi-tasking and multi-programming software
system designed to manage and extend the resources of iSBC@ 86, iSBC 186, iSBC 188, iSBC 286, and iSBC
386 Single Board Computers, as well as other 8086, 8088, 80186, 80188, and 80286/386TM (Real Address
Mode) based microcomputers. The Operating System provides a number of standard interfaces that allow
iRMX I applications to take advantage of industry standard device controllers, hardware components, and a
number of software packages developed by Independent Software Vendors (ISVs). Many high-performance
features extend the utility of iRMX I Systems into applications such as data collection, transaction processing,
and process control where immediate access to advances in VLSI technology is paramount. These systems
may deliver real-time performance and explicit control over resources; yet also support applications with
multiple users needing to simultaneously access terminals. The configurable layers of the System provide
services ranging from interrupt management and standard device drivers for many sophisticated controllers, to
data file maintenance commands provided by a comprehensive multi-user human interface. By providing
access to the standard Universal Development Interface (UDI) for each user terminal, Original Equipment
Manufacturers (OEMs) can pass program development and target application customization capabilities to
their users.

USER APPLICATIONS
210885-1

iRMX@ VLSI Operating System

2-24

November 1988
Order Number: 210885-004

iRMX® I OPERATING SYSTEM
The iRMX I Operating System is a complete set of
system software modules that provide the resource
management functions needed by computer systems. These management functions allow Original
Equipment Manufacturers (OEMs) to best use resources available in microcomputer systems while
getting their products to market quickly, saving time
and money. Engineers are relieved of writing complex system software and can concentrate instead
on their application software.

Process Management
To implement multi-tasking application systems, programmers require a method of managing the different processes of their application, and for allowing
the processes to communicate with each other. The
Nucleus layer of the iRMX I System provides a number of facilities to efficiently manage these processes, and to effectively communicate between them.
These facilities are provided by system calls that
manipulate data structures called tasks, jobs, regions, semaphores and mailboxes. The iRMX I System refers to these structures as 'objects".

This data sheet describes the major features of the
iRMX I Operating System. The benefits provided to
engineers who write application software and to users who want to take advantage of improving microcomputer price and performance are explained. The
first section outlines the system resource management functions of the Operating System and describes several system calls. The second section
gives a detailed overview of iRMX I features aimed
at serving both the iRMX I system designer and programmer, as well as the end users of the product
into which the Operating System is incorporated.

Tasks are the basic elements of all applications built
on the iRMX I Operating System. Each task is an
entity capable of executing CPU instructions and issuing system calls in order to perform a function.
Tasks are characterized by their register values (including those of an optional 8087, 80287, or 80387
Numeric Processor Extension), a priority between 0
and 255, and the resources associated with them.
Each iRMX I task in the system is scheduled for operation by the iRMX I Nucleus. Figure 1 shows the
five states in which each task may be placed, and
some examples of how a task may move from one
state to another. The iRMX I Nucleus ensures that
each task is placed in the correct state, defined by
the events in its external environment and by the
task issuing system calls. Each task has a priority to
indicate its relative importance and need to respond
to its environment. The Nucleus guarantees that the
highest priority ready-to-run task is the task that
runs. The nucleus can also be configured to allow
multiple tasks of the same priority to run in a roundrobin, time-slice fashion.

FUNCTIONAL DESCRIPTION
To take best advantage of 8086, 8088, 80186,
80188, and 80286/386 (Real Address Mode) microprocessors in applications where the computer is required to perform many functions simultaneously,
the iRMX I Operating System provides a multiprogramming environment in which many independent,
multi-tasking application programs may run. The
flexibility of independent environments allows application programmers to separately manage each application's resources during both the development
and test phases.

Jobs are used to define the operating environment

The resource management functions of the iRMX I
System are supported by a number of configurable
software layers. While many of the functions supplied by the innermost layer, the Nucleus, are required by all systems, all other functions are optional. The I/O systems, for example, may be omitted in
systems having no secondary storage requirement.
Each layer provides functions that encourage application programmers to use modular design techniques for quick development of easily maintainable
programs.

of a group of tasks. Jobs effectively limit the scope
of an application by collecting all of its tasks and
other objects into one group. Because the environment for execution of an application is defined by an
iRMX I job, separate applications can be efficiently
developed by separate development teams.
The iRMX I Operating System provides two primary
techniques for real-time event synchronization in
multi-task applications: regions and semaphores.

Regions are used to restrict access to critical sections of code and data. Once the iRMX I Operating
System gives a task access to resources guarded by
a region, no other tasks may make use of the resources, alld tile task is given protection agains: doletion and suspension. Regions are typically used to
protect data structures from being simultaneously
updated by multiple tasks.

The components of the iRMX I Operating System
provide both implicit and explicit management of
system resources. These resources include processor scheduling, up to one megabyte of system memory, up to 57 independent interrupt sources, all input
and output devices, as well as directory and data
files contained on mass storage devices and accessed by a number of independent users. Management of these system resources and methods for
sharing resources between multiple processors and
users is discussed in the following sections.

Semaphores are used to provide mutual exclusion
between tasks. They contain abstract "units" that
are sent between the tasks, and can be used to implement the cooperative sharing of resources.
2-25

inter

iRMX® I OPERATING SYSTEM

SYSTEM ROOT JOB
JOB A

TASK A1

JOB B

TASK B1

TASK B2

MAILBOX
TASK~

I~
AM

MAil·
BOXES

SEMAPHORE

~SKA3
OBJECT DIRECTORY
MAILBOX AM
MAILBOX AN
TASK A3

OBJECT DIRECTORY
TASK B2

OBJECT DIRECTORY
MAILBOX RM,(QLA
SEMAPHORE RS.IQLJI
TASK B2

(101

(NON EXISTENTI

210885-2

210885-3

NOTES:
1. Task is created.
2. Task becomes highest priority ready task.
3. Task gets pre-empted by one with higher priority.
4. Task calls SLEEP or task waits at an exchange.
5. Task sleep period has ended, message was
sent to waiting task or wait has ended.
6. Task calls SUSPEND on self.
7. Task suspended by other than self.
8. Task suspended by other than self or a resume that did not bring suspension depth to
zero.
9. Task was resumed by other task. '
10. Task is deleted.

Two example jobs are shown in Figure 2, to demonstrate how two tasks can share an object that was
not known to the programmer at the time the tasks
were developed. Both Job 'A' and Job 'B' exist within the environment of the 'Root Job' that forms the
foundation of all iRMX I systems. Each job posseses
a directory in which tasks may catalog the name of
an object. Semaphore 'RS', for example, is accessi·
ble by all tasks in the system, because its name is
cataloged in the directory of the Root Job. Mailbox
"AN" can be used to transfer objects between
Tasks 'A2' and 'A3' because its token is accessible
in the object directory for Job 'A'.

Figure 1. Task State Diagram

Table 1 lists the major functions of the iRMX I Nucleus that manages system processes.

Multi-tasking applications must communicate information and share system resources among cooperating tasks. The iRMX I Operating System assigns a
unique 16-bit number, called a token, to each object
created in the System. Any task in possession of this
token is able to access the object: The iRMX I Nucleus allows tasks to gain access to objects, and
hence system resources, at run-time with two additional mechanisms: mailboxes and object directories.

Memory Management
Each job in an iRMX I System defines the amount of
the one megabyte of addressable memory to be
used by its tasks. The iRMX I Operating System
manages system memory and allows jobs to share
this critical resource by providing another object
type: segments.
Segments are contiguous pieces of memory between 16 Bytes and 64 Kbytes in length, that exist
within the environment of the job in which they were
created. Segments form the fundamental piece of
system memory used for task stacks, data storage,
system buffers, loading programs from secondary
storage, pa:ssing information between tasks, etc.

Mailboxes are used by tasks wishing to share objects with other tasks. A task may share an object by
sending the object token via a mailbox. The receiving task can check to see if a token is there, or can
wait at the mailbox until a token is present.
Object Directories are also used to make an object
available to other tasks. An object is made public by
cataloging its token and name in a directory. In this
manner, any task can gain access to the object by
knowing its name, and job environment that contains
the directory.

The example in Figure 2 also demonstrates when
information is shared between Tasks 'A2' and 'A3';
'A2' only needs to create a segment, put the infor·
mation in the memory allocated, and send it via the
Mailbox 'AM' using the RQ$SEND$MESSAGE sys2-26

iRMX® I OPERATING SYSTEM

Table 1. Process Management System Calls
System Call
RQ$CREATE$JOB
RQ$DELETE$JOB
RQ$OFFSPRING
RQ$CATALOG$OBJECT
RQ$UNCATALOG$OBJECT
RQ$LOOKUP$OBJECT
RQ$GET$TYPE
RQ$CREATE$MAILBOX
RQ$DELETE$MAILBOX
RQ$SEND$MESSAGE

RQ$RECEIVE$MESSAGE

RQ$DISABLE$DELETION
RQ$ENABLE$DELETION
RQ$FORCE$DELETE
RQ$CREATE$TASK
RQ$DELETE$TASK
RQ$SUSPENDS$TASK
RQ$RESUME$TASK
RQ$SLEEP
RQ$GET$TASK$TOKENS
RQ$SET$PRIORITY
RQ$GET$PRIORITY
RQ$CREATE$REGION
RQ$DELETE$REGION
RQ$ACCEPT$CONTROL
RQ$RECEIVE$CONTROL
RQ$SEND$CONTROL
RQ$CREATE$SEMAPHORE
RQ$DELETE$SEMAPHORE
RQ$SEND$UNITS
RQ$RECEIVE$UNITS

Function Performed
Creates an environment for a number of tasks and other objects, as well as
creating an initial task and its stack.
Deletes a job and all the objects currently defined within its bounds. All
memory used is returned to the job from which the deleted job was created.
Provides a list of all the current jobs created by the specified job.
Enters a name and token for an object into. the object directory of a job.
Removes an object's token and its name from a job's object directory.
Returns a token for the object with the specified name found in the object
directory of the specified job.
Returns a code for the type of object referred to by the specified token.
Creates a mailbox with queues for waiting tasks and objects with FIFO or
PRIORITY discipline.
Deletes a mailbox.
Sends an object to a specified mailbox. If a task is waiting, the object is
passed to the appropriate task according to the queuing discipline. If no task
is waiting, the object is queued at the mailbox.
Attempts to receive an object token from a specified mailbox. The calling
task may choose to wait for a specified number of system time units if no
token is available.
Prevents the deletion of a specified object by increasing its disable count by
one.
Reduces the disable count of an object by one, and if zero, enables deletion
of that object.
Forces the deletion of a specified object if the disable count is either 0 or 1.
Creates a task with the specified priority and stack area.
Deletes a task from the system, and removes it from any queues in which it
may be waiting.
Suspends the operation of a task. If the task is already suspended, its
suspension depth is increased by one.
Resumes a task. If the task had been suspended multiple times, the
suspension depth is reduced by one, and it remains suspended.
Causes a task to enter the ASLEEP state for a specified number of system
time units.
Gets the token for the calling task or associated objects within its
environment.
Dynamically alters the priority of the specified task.
Obtains the current priority of a specified task.
Createsa region, with an associated queue of FIFO or PRIORITY ordering
discipline.
Deletes the specified region if it is not currently in use.
Gains control of a region only if the region is immediately available.
Gains control of a region. The calling task may specify the number of system
time units it wishes to wait if the region is not immediately available.
Relinquishes control of a region.
Creates a semaphore.
Deletes a semaphore.
Increases a semaphore counter by the specified number of units.
Attempts to gain a specified number of units from a semaphore. If the units
are not immediately available, the calling task may choose to wait.

2-27

iRMX® I OPERATING SYSTEM

tem call (see Table 1). Task 'A3' would get the message by using the RQ$RECEIVE$MESSAGE system
calL The Figure also shows how the receiving task
could signal the sending task by sending an acknowledgement via the second Mailbox 'AN'.

time response to events. Use of a pre-emptive
scheduling technique ensures that the servicing of
high priority events always takes precedence over
other system activites.
The iRMX I Operating system gives applications the
flexibility to optimize. either interrupt response time
or interrupt response capability by providing two tiers
of Interrupt Management. These two distinct tiers
are managed by Interrupt Handlers and Interrupt
Tasks.

Each job is created with both maximum and minimum limits set for its memory pool. Memory required
by all· objects and resources created in the job is
taken from this pool. If more memory is required, a
job may be allowed to borrow memory from the pool
of its containing job (the job from which it was created). In this manner, initial jobs may efficiently allocate memory to jobs they subsequently create, without knowing their exact requirements.

Interrupt Handlers are the first tier of interrupt service. For small simple functions, interrupt handlers
are often the most efficient means of responding to
an event. They provide faster response than interrupt tasks, but must be kept simple since interrupts
(except the 8086, 8088, 80186, 80188, 80286, and
386TM processors non-maskable interrupts) are
masked during their execution. When extended
service is required, interrupt handlers "signal" a
waiting interrupt task that, in turn, performs more
complicated functions.

The iRMX I Operating System supplies other memory management functions to search specific address
ranges for available memory. The System performs
this search at system initialization, and can be configured to ignore non-existent memory and addresses reserved for I/O devices and other application
requirements.

Interrupt Tasks are· distinct tasks whose priority is
associated with a hardware interrupt level. They are
permitted to make an iRMX I system call. While an
interrupt task is servicing an interrupt, interrupts of
lower priority are not allowed to pre-empt the system.

Table 2 lists the major system calls used to manage
the system memory.

Interrupt Management
Real-time systems, by their nature, must respond to
asynchronous and unpredictable events quickly. The
iRMX I Operating System uses interrupts and the
event-driven Nucleus described earlier to give real-

System Call

Table 2. Memory Management System Calls
Function Performed

RQ$CREATE$SEGMENT
RQ$DELETE$SEGMENT
RQ$GET$POOL$ATIRIBUTES
RQ$GET$SIZE
RQ$SET$POOL$MIN

System Call
RQ$SET$INTERRUPT
, RQ$RESET$INTERRUPT
RQ$GET$LEVEL
RQ$SIGNAL$INTERRUPT
RQ$WAIT$INTERRUPT
RQ$EXIT$INTERRUPT
RQ$ENABLE
RQ$DISABLE

Table 3 ~hows the iRMX I System Calls provided to
manage Interrupts.

Dynamically allocates a memory segment of the specified size.
Deletes the specified segment by deallocating the memory.
Returns attributes such as the minimum and maximum, as well as current
size of the memory in the environment of the calling task's job.
Returns the size (in bytes) of a segment.
Dynamically changes the minimum memory requirements of the job
environment containing the calling task.

Table. 3. Interrupt Management System Calls
Function Performed
Assigns an interrupt handler and, if desired, an interrupt task to the specified
interrupt level. Usually the calling task becomes the interrupt task.
Disables an interrupt level, and cancels the assignment of the interrupt
handler for that level. If an interrupt task was assigned, it is deleted.
Returns the number of the highest priority interrupt level currently being
processed.
Used by an interrupt handler to signal the associated interrupt task that an
interrupt has occurred.
Used by an interrupt task to SLEEP until the associated interrupt handler
signals the occurrence of an interrupt.
Used by an interrupt handler to relinquish control of the System.
Enables the hardware to accept interrupts from a specified level.
Disables the hardware from accepting interrupts at or below a specified
level.
2-28

iRMX® I OPERATING SYSTEM

tions. The BIOS allows liD functions to overlap other system functions. In this manner, application
tasks make asynchronous calls to the iRMX I BIOS,
and proceed to perform other activities. When the
liD request must be completed before an application can continue, the task waits at a mailbox for the
result of the operation. Some system calls provided
by the BIOS are listed in Table 4.

INTERRUPT MANAGEMENT EXAMPLE
Figure 3 illustrates how the iRMX I Interrupt System
may' be used to output strings of characters to a
printer. In the example, a mailbox named 'PRINT' is
used by all tasks in the system to queue messages
to be printed. Application tasks put the characters in
segments that are transmitted to the printer interrupt
task via the PRINT Mailbox. Once printing is complete, the same interrupt task passes the messages
on to another application via the FINISHED Mailbox
so that an operator message can be displayed.

CALL TO
ROSSENDS
MESSAGE

The Basic liD System communicates with peripheral devices through device drivers. These device drivers provide the System with four basic functions
needed to control and communicate with devices:
Initialize liD, Finish liD, Queue liD, and Cancel 110.
Using the device driver interface, users of non-standard devices may write custom drivers compatible
with the liD System.
The iRMX I Operating System includes a number of
device drivers to allow applications to use standard
USART serial communications devices, multiple
CRTs and keyboards, bubble memories, diskettes,
disks, a Centronics-type parallel printer, and many of
Intel's iSBC and iSBXTM device controllers (see Table 8). If an application requires use of a non-standard device, users need only write a device driver to
be included with the BIOS, and access it as if it were
part of the standard system. For most common random-access devices, this job is further simplified by
using standard routines provided with the System.
Use of this technique ensures that applications can
remain device independent.

LO-~~';;';;;"--r--.J

CALLT

L---------------------------------:...--------IRMXTN I SYSTEM

ROSSIGNALSINTERRUPT

210885-4

Figure 3. Interrupt Management Example

Basic I/O System
The Basic liD System (BIOS) provides the direct access to liD devices needed by real-time applica-

Table 4. Key BIOS 1/0 Management System Calls
System Calls

Function Performed

RQ$A$ATTACH$FILE

Creates a Connection to an existing file.

RQ$A$CHANGE$ACCESS

Changes the types of accesses permitted to the specified user(s) for
a specific file.

RQ$A$CLOSE

Closes the Connection to the specified file so that it may be used
again, or so that the type of access may be changed.

RQ$A$CREATE$DIRECTORY

Creates a Named File used to store the names and locations of other
Named Files.

RQ$A$CREATE$FILE

Creates a data file with the specified access rights.

RQ$A$DELETE$CONNECTION

Deletes the Connection to the specified file.

RQ$A$GET$FILE$STATUS

Returns the current status of a specified file.

RQ$A$OPEN

Opens a file for either read, write, or update access.

RQ$A$READ

Reads a number of bytes from the current position in a specified file.

RQ$A$SEEK

Moves the current data pointer of a Named or Physical file.

RQ$A$WRITE

Writes a number of bytes at the current position in a file.

RQ$WAIT$IO

Synchronizes a task with the I/O System by causing it to wait for I/O
operation results.

2-29

iRMX® I OPERATING SYSTEM

Multi-Terminal Support
The iRMX I Terminal Support provides line editing
and terminal control capabilities. The Terminal Support communicates with devices through simple drivers that do only character 1/0 functions. 'Dynamic
terminal reconfiguration is provided so that attributes
such as terminal type and line speed may be
changed without modifying the application or the
Operati.ng System. Dynamic configuration may be
typed in, generated programmatically or stored in a
file and copied to a terminal 110 connection.
The iRMX I Terminal Support provides automatic
translation of control characters to specific control
sequences for each terminal. This translation· enables applications using standard control characters
to function with non-standard terminals. The translation requirements for each terminal can be stored in
terminal description files and copied to a connection, as described above.

Peripheral Device Drivers
Each device driver can be used to interface toa
number. of separate· and, .in some cases, different
devices. The ,iSBC 215G Device Driver, supplied
with the system, is capable of supporting the. jSBC
215G Winchester Disk Controller, .the iSBC 220
SMD Disk Controller, and the iSBX 218A Flexible
Disk Controller (when mounted on an iSBC 215G
board). Each device controller may, in turn, control a
number of separate device units. In addition, each
driver may control a number of like device controllers. This capability allows the use of large storage
systems with a minimum of 1/0 system code to write
or maintain.
.

Logical file and device names are provided by the
, EIOS to give applications complete file and device
. independence. Applications may send data to the
'line printer' (:LP:) without needing to know which
specific device will be used as the printer. This logical name may, in fact, not be a printer at all, but it
could be a disk file that is later scheduled for printing.
The EIOS uses the functions provided by the BIOS
to synchronize individual 1/0 requests with results
returned by device drivers. Most EIOS system calls
are similar to the BIOS calls, except that they appear
to suspend the operation of the calling t~sk until the
1/0 requests are completed.
'

File Management
The iRMX I Operating System provides three distinct
types of files to ensure efficient management of both
program and data files: Named Files, Physical Files,
and. Stream Files. Each file type provides access to
1/0 devices through the standard device drivers
mentioned earlier. The same device driver is used to
access physical and named files for a given device.
NAMED FILES

Named files allow users to access information on
secondary storage by referring to a file with its ASCII
name. The names of files stored on a device are
stored in special files called directories in a hierarchical file structure.
The iRMX I BIOS uses an efficient format for writing
the directory and data information into secondary
storage. This structure enables the system to directly access any byte in a file, often without having to
do additional 1/0' to access space allocation information. The maximum size of an individual file is 4.3
billion bytes.

Extended 1/0 System
The iRMXI Extended 1/0 System (EIOS) adds a
number of 1/0 management capabilities to simplify
access to files. Whereas the BIOS provides users
with the basic system calls needed for direct management of 1/0 resources, many users prefer to
have the system perform all the buffering and synchronization of 1/0 requests automatically. The
EIOS allows users to access 1/0 devices without
having to write procedures for buffering data, or to
specify particular devices with constant device
names.
By performing device buffering automatically, the
iRMX I EIOS optimizes accesses to disks and other
devices. Often, when an application task, asks the
System to READ portion of a file, the System is
able to respond immediately with the data it has
read in advance of the request. Similarly, the EIOS
will not delay a task for writing, data to a device unless it is specifically told to, or if its output buffers are
filled.

EASE OF ACCESS

The hierarchical file structure is. provided to isolate
and organize collections of named files. To give op, erators fast and simple access to any level within
the file tree, an ATIACHFILE command is provided.
This command allows operators to create a logical
name to a point in the tree so that a long sequence
of characters need not be typed each time a file is
referred to.

ACCESS PROTECTION

Access· to each Named File is protected. by the
rights assigned to each user by the owner of the file.
Rights to read, append, update, and delete may be
2-30

inter

iRMX® I OPERATING SYSTEM

selectively granted to other users of the system. In
general, users of Named Files are classified into one
of two categories: User and World. Users are used
when different programmers and programs need to
share information stored in a file. The World classification is used when rights are to be granted to all
who can use the system.

Human Interface
The flexibility of the interface between computer
controlled machines and their users often determines the usability and ultimate success of the machines. Table 11 lists iRMX I Human Interface functions giving users and applications simple access to
the file and system management capabilities described earlier. The process, interrupt, and memory
management functions described earlier, are performed automatically for Human Interface users.

PHYSICAL FILES

Physical Files allow more direct device access than
Named Files. Each Physical File occupies an entire
device, treated as a single stream of individually accessible bytes. No access control is provided for
Physical Files as they are typically used for such applications as driving a printing device, translating
from one device format to another, driving a paper
tape device, real-time data acquisition, and controlling analog mechanisms.

MULTI-USER ACCESS

Using the multi-terminal support provided by the
BIOS, the iRMX I Human Interface can support several simUltaneous users. The real-time nature of the
system is maintained by providing a priority for each
user, and using the event-driven iRMX I Nucleus to
schedule tasks. High-performance interrupt response is guaranteed even while users interact with
various application packages. For example, multiterminal support allows one person to be using the
iRMX I Editor, while another compiles a FORTRAN
86 or PASCAL 86 program, while several others load
and access applications.

STREAM FILES

Stream Files provide applications with a method of
using iRMX I file management methods for data that
does not need to go into secondary storage. Stream
Files act as direct channels, through system memory, from one task to another. These channels are
very useful to programs, for example, wishing to preserve file and device independence allowing data
sent to a printer one time, to a disk file another time,
and to another program on a different occasion.

Each terminal attached to the iRMX I multi-user Human Interface is automatically associated with a
user, a memory pool, and an initial program to run
when the terminal is connected. This association is
made using a file that may be changed at any time.
Changes are effective the next time the system is
initialized.

BOOTSTRAP AND APPLICATION LOADERS

Two utilities are supplied with the System to load
programs and data into system memory from secondary storage devices:

The initial program specified for each terminal can
be a special application program, a custom Human
Interface, or the standard iRMX I Command Line Interpreter (CLI).

The iRMX I Bootstrap is typically used to load the
initial system from the system disk into memory, and
begin its execution. Error reporting and debug switch
features have been added to the Bootstrap Loader.
When the Bootstrap Loader detects errors such as:
"File Does Not Exist" or "Device Not Ready", an
error message is reported back to the user. The debug switch will cause the Bootstrap Loader to load
the system but not begin its execution. Instead the
Bootstrap Loader will pass control to the monitor at
the first instruction to be executed by the system.

Specifying an application program as a terminal's initial program makes the interface between operators
and the computer system much simpler. Each operator need only be aware of the function of a particular application.
Specifying the standard iRMX I Human Interface CLI
as the initial program enables users of the terminals
to access all iRMX I functions. This CLI makes it
easy to manage iRMX I files, load and execute Intelsupplied and custom programs, and submit command files for execution.

The Application Loader is typically used by application programs already running in the system to load
additional programs and data from any secondary
storage device. The Human Interface layer, for example, uses the Application Loader to load the nonresident Human Interface Commands. The Application Loader is capable of loading both relocatable
and absolute code as well as program overlays.

2-31

inter

iRMX® I OPERATING SYSTEM

Building Security
System
SYSTEM BUFFERS
AND DATA

APPLICATION CODE
'OPERATOR
CONSOLE
APPLICATIONS

COMMON
UTILITIES

RAM

BACKGROUND
APPLICATION

HUMAN INTERFACE
EIOS

BIOS

WINCH ESTER
DISK
DRIVER

FLOPPY
DISK
DRIVER

NUCLEUS
'PROM

BOOTSTRAP LOADER

210885-8

Data Communication
Controller
SYSTEM
BUFFERS
DATA

RAM

PROM

16K BYTES
APPLICATION CODE
23K BYTES NUCLEUS CODE

210885-9

Figure 4. Typical iRMX® I Configurations

Many real-time systems require high performance
operation. To meet this requirement, all of iRMX I
can be put into high-speed P(ROM). This approach
eliminates the possibility of disk access times slowing down performance, while allowing system designers to take advantage of high performance
memory devices.

FEATURE OVERVIEW
The iRMX I Operating System is well suited to serve
the demanding needs of real·time applications executing on complex microprocessor systems. The
iRMX I System also provides many tools and featues
needed by real-time system developers and programmers. The following sections describe features
useful in both the development and execution environments. The description of each feature outlines
the advantages given to hardware and software engineers concerned with overall system cost, expandability with custom and industry standard options,
and long-term maintenance of iRMX I-based systems. The development environment features also
describe the ease with which the iRMX I Operating
System can be incorporated into overall system de~gnL

CONFIGURABILlTV

The iRMX I Operating'system is configurable by system layer, and by system call within each layer. In
addition all the 1/0 port addresses used by the System are configurable by the user. This flexibility gives
designers the freedom to choose configurations of
hardware and software that best suit their size and
functional requirements. Two example configurations are shown in Figure 4.

Most configuration options are selected during system design stages. Others may be selected during
system operation. For example, the amount of memory devoted to queues within a Mailbox can be specified at the time the Mailbox is created. Devoting
more memory to the Mailbox allows more messages
to be transmitted to other tasks without having to
degrade system performance to allocate additional
memory dynamically.

Execution Environment Features
REAL·TIME PERFORMANCE

The iRMX I Operating System is designed to offer
the high performance, multi-tasking functions required by real-time systems. Designers can make
use of VLSI devices such as the 8087, 80287 or
80387 Numeric Processor Extension.
2-32

iRMX® I OPERATING SYSTEM

ment used to monitor job costs while developing
new device control specifications instructions. The
iSBC 544A Intelligent Terminal Interface supports
multiple user terminals without degrading system
performance to handle character 1/0.

The chart shown in Table 6 indicates the actual
memory size required to support these different configurations of the iRMX I System. Systems requiring
only Nucleus level functions may require no more
than 13 Kbytes for the Operating System. Other applications, needing 1/0 managment functions, may
select portions of additional layers that fit their
needs and size constraints.

EXTENDABILITY
The iRMX I Operating System provides three means
of extensions. This extendability is essential for
support of OEM and volume end user value added
features. This ability is provided by user-defined op-

This configurability also applies to the Terminal Handier, Dynamic Debugger, and System Debugger.
The Terminal Handler provides a serial terminal interface in a system that otherwise doesn't need an
1/0 system. Either one of the debuggers need to be
included only as debugging tools (usually only during
system development).
MULTI-USER ACCESS
Many real-time systems must provide a variety of
users access to system control functions and collected data. The iRMX I System provides easy-touse support for applications to access multiple terminals. It also enables multiple and different users to
access different applications concurrently.
Figure 5 illustrates a typical iRMX I application simultaneously supporting multi-terminal data collection
and real-time environments. Shown is a group of terminals used by machinists on a shop floor to communicate with a job management program, a building security system that constantly monitors energy
usage requirements, a system operator console capable of accessing all system functions, and a group
of terminals in the Production Engineering depart-

210885-10

Figure 5. Multi-Terminal and Multi-User
Real-Time System

Table 6. iRMXTM 86 Configuration Size Chart
System Layer

Min. ROMabie
Size

Max.
Size

Data
Size

1.5K

6K·

10.5K

24K

BIOS

26K

78K

Application Loader

10K

10.5K

12.5K

Human Interface

22K

.15K

UDI

Terminal Handler

O.3K

Bootstrap Loader
Nucleus

EIOS

System Debugger

20K

Dynamic Debugger

28.5K

Human Interface Commands

116K

Interactive Configuration Utility

308K

'Usable by System after bootloadlng.

2-33

iRMX® I OPERATING SYSTEM

Table 7. User Extension System Calls
System Call

Function Performed

RQ$CREATE$COMPOSITE

Creates a custom object built of previously defined objects.

RQ$DELETE$COMPOSITE

Deletes the custom object, but not the various objects from which it
was built.

RQ$INSPECT$COMPOSITE

Returns a list of Token Identifiers for the component objects from
which the specified composite object is built.

RQ$ALTER$COMPOSITE

Replaces a component object of a composite object.

RQ$CREATE$EXTENSION

Creates a new type of object and assigns a mailbox used for
coliecting these objects when they are deleted.

RQ$DELETE$EXTENSION

Deletes an extension definition.

erating system calis, user-defined objects (similar to
Jobs, Tasks, etc.), and the ability to add functions
later in the product life. cycle. The modular, layered
structure of the System easily facilitates later addi.tions to iRMX I applications. User-defined objects
are supported by the functions listed in Table 7.

SUPPORT OF STANDARDS

The iRMX I Operating System supports the many
hardware and software standards needed by most
application systems to ensure that commonly available hardware and software packages may be interfaced with a minimum of cost and effort. The iRMX I
System supports the iSBC family of products built on
the Intel MULTIBUS I (IEEE Standard 796), and a
number of standard software interfaces such as the
UDI and the common device driver interface (See
Figure 6). The procedural interfaces of the UDI are
listed in Table 9.

Using standard iRMX I system calis, users may define custom objects, enabling applications to easily
manipulate commonly. used structures as if they
were part of the original operating system;
EXCEPTION HANDLING

The Operating System includes support for the 8087
Numeric Data Processor and equivalent instructions
and registers in the 80287 and 80387 Numeric Data

The System includes predefined exception handlers
for typical 1/0 and parameter error conditions. The
errors handling mec;:hanism is both configurable and
extendable.

APPLICATIONS
SUPPORT

• ETHERNET IS .a '!glsttleel I"dem.rk 01 XI!'IO' Corp

Figure 6. iRMX@1 Standard Interfaces

2-34

210885-11

iRMX® I OPERATING SYSTEM

Processors. Standards such as an Ethernet communication interface are supported by optional software
packages available to run on the iRMX I System.

controllers. The particular boards and types of devices supported are listed in Table 8. The device controllers all adhere to industry standard electrical and
functional interfaces.

SPECTRUM OF CPU PERFORMANCE

In addition to the on-CPU board terminal drivers, the
iRMX I BIOS includes two iSBC board-level device
drivers to support multiple terminal interfaces:

The iRMX I Operating System supports a broad
range of Intel processors. In addition to support for
8086, 8088, 80186 and 80188-based systems, the
iRMX I system has been enhanced to support
80286/386, (16-bit, Real Address Mode)-based Systems. This new support enables the user to take advantage of the faster speed and higher performance
of Intel's 80286 and 386 based microprocessors
such as the iSBC 286/12 and iSBC 386/21 single
board computers. By choosing the appropriate CPU,
designers can choose from a wide range of performance options, without having to change application
software.

The iSBC 544A Intelligent Four-Channel Terminal Interface Device Driver provides support for multiple
controllers each supporting up to four standard
RS232 terminals. The iSBC 544A driver takes advantage of an on-board processor to greatly reduce
the system processor time required for terminal I/O
by locally managing input and output buffers. The
iSBC 544A firmware provided with the operating system can offload the system CPU by as much as 75%
when doing character outputting.
The iSBC 534 Four-Channel USART Controller Device Driver also provides support for multiple controller boards each supporting up to four standard
RS232 terminals.

COMPONENT LEVEL SUPPORT

The iRMX I System may be tailored to support specific hardware configurations. In addition to system
memory, only an 8086, 8088, 80186, 80188, 80286,
or 386 microprocessor, an 8259A Programmable Interrupt Controller (PIC), and either an 8253, 8254, or
82530 Programmable Interval Timer (PIT) are required as follows:

The RAM disk feature in iRMX I makes a portion of
the memory address space look like a disk drive to
the I/O system ..
Table 8_ Supported Devices

• 8086 and 8088 systems need either:
- 8253/4 PIT and 8259A PIC (master) or
- 80130 firmware (PIC is master)

Function

Module/Device
iSBC® 86/C38, 86/05A,
86/12A, 86/30, 86/35,
186/03A, 186/51, 188/56,
286/10A,286/12,386/21,
386/31
Peripheral controller iSBC 186/03A SCSI, 208,
214, 215G, 220, 221,
iSBXTM 217C, 218A
Terminal Controller/ iSBC 188/56,534, 544A,
HostComm.
548, iSBX 351, 354
Network Controller
iSBC 552A, 186/51
Graphics
iSBX279
Microprocessor
8086,8088,80186,80188,
(Note 1)
80286,386
Math Coprocessor
8087,80287,80387
(Note 1)
Serial Port
8251A,8274,82530
Interrupt Controller
8259A,80130,80186
Timer
8253,8254,80186
Parallel Port/
8255, iSBX 350
Line Printer
RAM Disk
SRAM, DRAM

Single Board
Computer (Note 1)

• 80186 and 80188 systems where 186 PIC is
slave, needs either:
- 8253/4 PIT and 8259A PIC (master) or
- 80130 firmware (PIC is master)
where 186 PIC is master:
-

Use 186 PIT for the system clock; no external
PIT is needed
Can use either
186 PIC (master) only or
8259A/80130 PIC (slave)

• 80286 systems need
- 8253/4 PIT and 8259A PIC
For systems requiring extended mathematics capability, an 8087, 80287, or 80387 Numeric Data Processor may be added to perform these functions up
to 100 times faster than equivalent software. For applications servicing more than 8 interrupt sources,
additional 8259A's may be configured as slave controllers.
BOARD LEVEL SUPPORT

NOTE:
1. Supports 16-bit, real address mode, 8086/8087 instruction set, functions and registers.

The iRMX I Operating System includes device drivers to support a broad range of MULTIBUS I device
2-35

inter

iRMX®1 OPERATING SYSTEM

Development Environment Features

LANGUAGES

TheiRMX I Operating System supports the efficient
utilization of programming time by providing important tools for program development. Some of the
tools necessary to develop and debug real-time systems are included with the Operating System. Others, such as language compilers, are available from
Intel and from leading Independent Software Vendors.

The iRMX I Operating System supports 31 standard
system calls known as the Universal Development
Interface (UDI). Figure 6 shows the iRMX I standard
interfaces to many compilers and language translators, including Intel's 8086 Macro Assembler and the
Pascal 86, PL/M 86, FORTRAN 86 and C86 compilers.

System Call
MEMORY MANAGEMENT
DQ$ALLOCATE
DQ$FREE
DQ$GET$SIZE*
DQ$RESERVE$IO$MEMORY*
FILE MANAGEMENT
I
DQ$ATTACH
DQ$CHANGE$ACCESS*
DQ$CHANGE$EXTENSION
DQ$CLOSE
DQ$CREATE
DQ$DELETE
DQ$DETACH
DQ$OPEN
DQ$GET$CONNECTION$STATUS*
DQ$FILES$INFO*
DQ$READ
DQ$RENAME*
DQ$SEEK
DQ$TRUNCATE
DQ$WRITE
PROCESS MANAGEMENT
DQ$EXIT
DQ$OVERLAY*
DQ$SPECIAL
DQ$TRAP$CC
EXCEPTION HANDLING
DQ$GET$EXCEPTION$HANDLER
DQ$DECODE$EXCEPTION
DQ$TRAP$EXCEPTION
APPLICATION ASSISTANCE
DQ$DECODE$TIME
DQ$GET$ARGUMENT*
DQ$GET$SYSTEM$ID*
DQ$GET$TIME*
DQ$SWITCH$BUFFER

Table 9. UDI System Calls
Function Performed
Creates a Segment of a specified size.
Returns the specified segment to the System.
Returns the size of the specified Segment.
Reserves memory to OPEN and ATTACH files.
Creates a Connection to a specified file.
Changes the user access rights associated with a file or directory.
Changes the extension of a file name in memory.
Closes the specified file Connection.
Creates a Named File.
Deletes a Named File.
Closes a Named File and deletes its Connection.
Opens a file for a particular type of access.
Returns the current status of the specified file Connection.
Returns data about a file Connection.
Reads the next sequence of bytes from a file.
Renames the specified Name File.
Moves the position pointer of a file.
Truncates a file.
Writes a sequence of bytes to a file.
Exits from the current application job.
Causes the specified overlay to be loaded.
Performs special 1/0 related functions on terminals with special
control features.
Capture control when CNTRL/C is type.
Returns a pointer to the program currently being used to process
errors.
Returns a short description of the specified error code.
Identifies a custom exception processing program for a particular
type of error.
Returns system time and date in binary and ASCII character format.
Returns the next argument from the character string used to invoke
the application program.
Returns the name of the underlying operating system supporting the
UDI.
Returns the current time of day as kept by the underlying operating
system.
Selects a new buffer from which to process commands.

'Calls available only through the UDI.

2·36

iRMX® I OPERATING SYSTEM

Also included are other Intel development tools, language translators and utilities available from other
vendors. The full set of UDI calls (which includes the
URI system calls) is required to run a compiler.

INTERACTIVE CONFIGURATION UTILITY
The iRMX I Operating System is designed to provide
OEMs the ability to configure for specific system
hardware and software requirements. The Interactive Configuration Utility (ICU) builds iRMX I configurations by asking appropriate questions and making
reasonable assumptions. It runs on either an Intellec® Series IV development system or iRMX I development system that includes a hard disk and the
UDI. Table 11 lists the hardware and support software requirements of different iRMX I development
system environments.

These standard software interfaces (the UDI) ensure
that users of the iRMX I Operating System may
transport their applications to future releases of the
iRMX I Operating System and other Intel and independent vendor software products. The calls available in the UDI are shown in Table 9.
The high performance of the iRMX I Operating System enhances the throughput of compilers and other
development utilities.

Table 11. IRMX® Development Environment
Intellec Series IV:
ASM 86 Assembler and Utilities
PL/M 86 Compiler
One hard disk and one diskette drive

TOOLS
Certain tools are necessary for the development of
microcomputer applications. The iRMX I Human Interface includes many of these tools an non-resident
commands. They can be included on the system
disk of a application system, and brought into memory when needed to perform functions as listed in
Table 10.

iRMX I Development System:
ASM 86 Assembler and Utilities
PL/M 86 Compiler
iSDM System Debug Monitor
640K Bytes of RAM
5M Byte On-Line Storage and one
double-density diskette drive
SYSTEM 86/300, 286/300, or 386/300 Series:
Microcomputer System Basic configuration

Table 10. Major Human Interface Utilities
Command
BACKUP
COPY
CREATEDIR
DIR

ATTACHFILE

PERMIT
RENAME
SUBMIT
SUPER

TIME
VERIFY

Function
Copy directories and files from
one device to another.
Copy one or more files to one
or more destination files.
Create a directory file to store
the names of other files.
List the names, sizes, owners,
etc. of the files contained in a
directory.
Give a logical name to a
specified location in a file
directory tree.
Grant or rescind user access
toa file.
Change the name of a file.
Start the processing of a series
of commands stored in a file.
Change operator's 10 to that of
the System Manager with
global access rights and
privileges.
Set the system time-of-day
clock.
Verify the structure of an
iRMX I Named File volume,
and check for possible disk
data errors.

Figure·7 shows one of the many screen displayed
during the process of defining a configuration. It
shows the abbreviations for each choice on the left,
a more complete description with the range of possible answers in the center, and the current (sometimes default) choice on the right. The bottom of the
screen shows three changes made by the operator
(lower case lettering), and a request for help on the
Exception Mode question. In response to a request
for help, the ICU displays an additional screen outlining possible choices and some overall system effects.
The ICU requests only information required as a result of previous choices. For example, if no Extended 1/0 System functions are required, the ICU will
not ask any further questions about the EIOS. Once
a configuration session is complete, the operator
may save all the information in a file. Later when
small changes are necessary, this file can be modified. A completely new session is not required.

2-37

inter

iRMX® I OPERATING SYSTEM

REAL-TIME DEBUGGING TOOLS

PARAMETER VALIDATION

The iRMX I Operating System supports two distinct
debugging environments: Static and Dynamic. While
the iRMX I Operating System does support a mUltiuser Human Interface, these real-time debugging
aids are usually most useful in a single-user environment where modifications made to the system cannot affect other users.

Some iRMX I System Calls require parameters that
may change during the course of developing iRMX I
applications. The iRMX I Operating System includes
an optional set of routines to validate these parameters to ensure that correct numeric values are used
and that correct object types are used where the
System expects to manipulate. an object. For systems based only on the iRMX I' Nucleus, these routines may be removed to improve the performance
and code size of the System once the development
phase is completed.

System Debugger
The static debugging aid is the iRMX I System Debugger. This debugger is an extension of the iSDM
System Debug Monitor. The System Debugger provides static debugging facilities when the system
hangs or crashes, when the Nucleus is inadvertently
overwritten or destroyed, or when synchronization
requirements prevent the debugging of certain
tasks. The System Debugger stops the system and
allows you to examine the state of the system at that
instant, and allows you to:
- Identify and interpret iRMX I system calls.
-

START-UP SYSTEMS
Three ready-to-run start-up systems are included in
the iRMX I Operating System package for 8086,
80286, and 386-based MULTIBUS I systems. These
iRMX I start-up systems are fully configured, iRMX I
Operating Systems ready to be loaded into memory
by the Bootstrap Loader. The start-up systems are
configured to include all of the. system calls for each
layer and most of the features provided by iRMX I
software. iRMX I start-up systems include UDI support so that users may run languages such as
PLlM-86, Pascal, FORTRAN, and software packages from independent vendors.

Display information about iRMX I objects.
Examine a task's stack to determine system call
history.

The start-up system for the 8086 processor is configured for Intel SYSTEM 86/300 Series microcomputers with a minimum of 384K bytes of RAM. The
following devices are supported.
'

iRMX® I Dynamic Debugger
The iRMX I Dynamic Debugger runs as part of an
iRMX I application. It may be used at any time during
program development, or may be integrated into an
OEM system to aid in the discovery of latent errors.
The Dynamic Debugger can be used to search for
errors in any task, even while the other tasks in the
system are running. The iRMX I Dynamic Debugger
communicates with the developer via a terminal handier that supports full line editing.
Nucleus
(ASC)
(PV)
(ROD)
(MTS)
(DE H)
(NEH)
(EM)
(NR)

• iSBC 215G/iSBX 218 or iSBC 215G/iSBX 218A
or iSBC 214
• Line Printer
• 8251A Terminal Driver
• iSBC 544A, Terminal Driver

All Sys Calls [Yes/No]
Parameter Validation [Yes/No]
Root Object Directory Size [O-OFFOh]
Minimum Transfer Size [O-OFFFFH]
Default Exception Handler [YeslNo/Deb/Use]
Name of Ex Handler Object Module [1-32 chs]
Exception Mode [Never/Program/Environ/ All]
Nucleus in ROM [Yes/No] .

Enter Changes [Abbreviations?/ = new-value]:
:pv = no
:rod = 48
:em?

ASC = N

Figure 7.ICU Screen for iRMX® I Nucleus

2-38

Yes
Yes
0014H
0040H
Yes
Never
No

iRMX® I OPERATING SYSTEM

80286/386 Microprocessors (16-bit, Real Address
Mode Only)

The start-up system for the 80286 processor is configured for Intel SYSTEM 286/300 Series microcomputers with a minimum of 512 Kby1es and a maximum of 896 Kbytes of RAM. The following devices
are supported.

8087 Numeric Data Processor Extension
80287/387 Numeric Data Processor Extension
(8087 Functions and Registers)

• iSBC 208
• iSBC 215G/iSBX 218 or iSBC 215G/iSBX 218A

8253 and 8254 Programmable Interval Timers
8259A Programmable Interrupt Controller

• Line Printer for iSBC 286/1 X

8251A USART Terminal Controller

• 8274 Terminal Driver

8255 Programmable Parallel Interface

• iSBC 544A Terminal Driver

8274 Terminal Controller

A start-up system is also provided for 386-based designs.

82530 Serial Communications Controller

The systems will run without hardware or software
configuration changes and can be reconfigured on a
standard system with at least 512 Kbytes of RAM.
Definition files are also included for iSBC 186/03A,
186/51 and 188/56 configurations.

iSBC® MULTIBUS BOARD AND SYSTEM
PRODUCTS

This start-up system may be used to run the ICU (if a
Winchester disk is attached to the system) to develop custom configurations such as those pictured in
Figure 5. As shipped, the Human Interface supports
a single user terminal. However, the Start-up System
terminal configuration file may be altered easily to
support from two to five users.

iSBC 186/51 Ethernet Controller

iSBC 86/C38, 86/12A, 80/05A, 86/30, 86/35, and
88/40A Single Board Computers
iSBC 186/03A Single Board Computer
iSBC 188/56 Communications Controller
iSBC 286/10A and 286/12 Single Board Computers
(Real Address Mode only)
iSBC 386/21 and 386/31 (16-bit, Real Address
Mode only)
iSBC 208 Diskette Controller
iSBC 214 and 215(G) Winchester Disk Controllers

SPECIFICATIONS

iSBX 218A Flexible Diskette Multi-Module Controller

Supported Software Products

iSBC 220 SMD Disk Hard Controller

R86ASM86

8086 Assembler and Utilities

iSBC 221 Disk Controller

R86C86

C 86 Compiler

iSBC 534 4-Channel Terminal Interface

R86PAS86

PASCAL 86 Compiler

R86FOR86

FORTRAN 86 Compiler

iSBC 544A Intelligent 4-Channel Terminal Interface
and Controller

R86PLM86

PL/M 86 Compiler

iSBC 548 Intelligent 8-Channel Terminal Controller

iRMX 864

AEDIT Screen-oriented Editor

iSBC 552A Ethernet Controller
iSBX 350 Parallel Port (Centronics-type Printer Interface)

Supported Hardware Products

iSBX 351 and 354 Serial Communications Port

COMPONENTS

SYSTEM 86/300 Family

iSBX 279 Graphics Subsystem
8086 and 8088 Microprocessors

SYSTEM 286/300 Family

80186 and 80188 Microprocessors

SYSTEM 386/300 Family

2-39

iRMX® I OPERATING SYSTEM

USER MANUALS
The iRMX I Operating System is provided with one
five volume set of reference manuals:
iRMX I INSTALLATION AND PROVolume I
GRAMMER'S GUIDES

ettes. The software includes one set of user manuals and 90 days of initial support. This support includes: "TIPS" Technical Information Phone Service; software updates that occur during the support
, period; monthly ";Comments" magazine and quarterly Troubleshooting Guide; Software Problem Report Service; and membership in the Insite User's
Program Library.

Volume II

iRMX I OPERATING SYSTEM USER
GUIDES

Volume III
Volume IV

iRMX I SYSTEM CALLS
iRMX I OPERATING SYSTEM UTILITIES

Please contact your local Intel Sale!! Office or authorized distributer for product order codes.

Volume V

iRMX I INTERACTIVE CONFIGURATION UTILITY REFERENCE GUIDE

LICENSING
Before iRMX I software will be shipped, a customer
must sign (or have already signed) Intel's Software
License Agreement (SLA). Once the SLA is Signed,
the customer is licensed to use tne iRMX software
for application development. Customers who want to
"incorporate" portions of the iRMX I Object Code in
an application, will have to sign an Incorporation License which 'clearly spells out the terms and conditions under which incorporations can be made. Contact your local Intel office for more information and
for appropriate licensing.

Additional sets of manuals may be ordered.

Training Courses
Training courses are available on the iRMX I Operating System, Intel languages, and Intel microprocessor architectures.

ORDERING INFORMATION
iRMX I Operating System development software is
available on both 5%" and 8"iRMX-format di,sk-

2-40

L'~iQ)~b\IM~I~ ~1NI1F©~lR1tAW~(Q)1NI

~1-R-n--X-®--I-I--O-P-E-'-R-A-T-I-N--G--S-~--S-T--E-n-s~1

The iRMX II family of operating systems provides ti(>~ign,>r~ lilt' IIlIrlt!'s 1ll,,,1 ",1\'Ull'l'ti I'l'al-time ~oftware for
16-bit designs boscd on the 80286 and 386'" prot'l'ssO"_ The PJ'IIt1Ul't of ten ,('ars of real-tiuw e'pmise by
Intel. iRMX II software provides high performance r('sponse 10 ('\1<'1'11<11 ,'wnls, "\t't'II('1ll ~upporlof special
purpose hardware, and sophisticated real time progrnmming fa!'iliti('s_

ADJ'ANCED FEATIJRES AJ'AILABLE TODAY
•
•
•
•

80286 and 386'" microprocessor support
80287 and 80387 math coprocessor support
16 megabyte memory arldressability
Multiple tasks and multiple jobs

• ~lultipl'(J('t'~sing :-tuppol'l
• Priority haSt'!] nnd/or' round I'tIhin scilt'duling
• L"st>r ('xtt'IHiahl(' ()hit'ct (lI'it'Jltt'd architecture
• ~Iultiplt> u~er~

A COMPLETE REAL-TIME OPERAl'ING SYSTEM,
NOT .IllSI' A KERNEL
• Maior functions of iRMX 11 software include:
-Nucleus
-Named, Remote_ Physical and Stremn File,
System
-Basic I/O ilntl ,;xtended I/O systems including
device drivers for many Intel MULTlllUS'" I/O
boards
-Bootstrap and Application Loaders

-llllman intl'rral't' :-iuPPOI'tillg on Wrgt:'t
(it'wlopl1H'nt and t'rHIII~('I' ['('programming
-Inlerement with custom exception handlers
-support for multiple tasks
-preemptive. priority based scheduling with round rouin
(time Slice) scheduling within a priority level
-intertask communication threlUgh mallb4lxe.s and
semaphores

With iRMX II software and other s(~tware from Intel's family of
real·time soFtware products. engineers can design complex. highcapability systems with a minimum of custom code. An example
is the system shown in figure 1. This system has a single iSIlC
386/258 peripheral controller board that functions as both a
bexltserver and fileserver to multiple iSBC386/120 CPU hoards
In the system. File transfers are handled via the ISIlC 186/530
Network Interface Adapter. which also provides an Ethernet
network connection. The iSIlC 186/410 terminal controller board
uses communication software that is downloaded from the
system disk. The iSIlX'" 279 Display Suhsystem. to~ether with
iRMX Virtual Terminal soFtw~l't'. provides a('cess ttl any
processor in the system via a single console with multiplt'
windows.

• Easily ......a ...etIIl... PReMo
Rt'al time applications hullt with iRMX II softwart' art' ('asily
IJrtlgr,lmmed into PROM's or ~:PROM's for higilly

St'SrEMS
MULTIBUS II systems. which pass data over the hus using highspeed messages. enable engineers to easily assemble highperformance. multiprocessor systems. Ilus arbitration problems
are virtually eliminated and slower speed I/O boards cannot slow
down data transFer across the bus since all data is passed at tile
full hus bandwidth of 40 Mllytesisecond.

2-42

FEATURES

OpanNET'" Local Area Network
iSBX'" 279
Display SubSystem

To Local Terminals
or Modams

Terminal
Controller

Network
Interlace
Adapter

MULTI BUS· II System Bus-40 MBIsac, Data li'ansler Rata

t'l1II_re .: MU[;I'lllllSe> II iRMX 1I·llased MulLipl'Ocessol' SysLPm

tI COM,.UTE liEtiL TIME O,.ElltiTING

SYSTEM. NOT oIlJST IIIiEIlNEL
With ('omparablc perrorman('C, IR\tX II operating ~y~t('m~
provide ma~y reatures that are extra cost items, or sirriply
unavailable, in real time kernels. These reatures make the
development or real time applications much easier and raslt'r. hilt
do nol add Ullllet't'essary owrhead. III ract, all runcLionallayers
except the nucleus arr optional In IRMX II sortware. This
lIexibility alluws you tu include only those reatures that your
application requires. The rollowing is a hrier desrription or Ihl'
major runcllonal groups within iRMX II soltware.

NrIdeM
The Nucleus is the heart or the operating system and controls all
resources availahle W the system. The nurleus provides ke~' 1'1'31
tlmc reatUl'cs including:
•
•
•
•
•
•
•
•
•
•

support or mullipl!" tasks
priority based and/or lime slice scheduling
dynamic priority adjustment
memury management with 16 ml'gahytr addrl'ssahllity
intertask rommunicalion and synchroni~ation using mailhoxes
and semaphorrs
interrupt management with rustom exCt'ption handlers
descriptor table management
lime management
object management
the addition or custom olreraling system extensinns

/Wilden t:e••••'atflo.s Sft'rlf)e
The Nucleus Communications Service provides the software
inlerrarr hetween application code and the MULTIBUS II
message·passlng coproressor, This software simplifies the
job or sending messages hetween tasks on dirrerent boards
and provides a standard sortware Interrace to any other
MULTIIlUS II board in the s~slem,

Bask 110 Sy,*- (BIOS)
The Basil' I/O System (BIOS) provides primitives to read rrom and
write 10 peripherals. as well as the ability to burrer I/O, The BIOS
also sets up the file structures used by the system and provides

aerl's" 10 alll'l'quir<'d pl'riphl'rals,tiJrough a standard devlcr
driwr InU'rran'. ~Iany devin' driwrs an' provided with iRMX /I
Operating Hysh'ms, and l'usWm dl'\'il'l' drivers and file'drivrrs
may hi' alllll'lI hy 1111' USl'r.

IR,"XII> II DHlee Orlft1'8
iSBX" 3~O
iSIlX 217<:
iSBX 218:\
ISBX 270
iSBX :m~

8251A.82H,
825:m
Memor~'

Ml'I:I'IIll!HI:
iSBG 188156
iSIlC 5~8
iSIlC 208
iSIlC 220
iSIlC 214
iSIlC 215(1
iSllC 221
iSIlC!i:H
iSIlC5HA
MULTIIlUS II:
iSBC 186/~ 10
iSBC 1861224.\
ISBC 286//()OA
iSIlC 3861258

Parallt'l Port (printer interfacr)
'Iilpe DriVl' Conll'llllrr
Vll'xihlr Disk Controllrr
Display Subsyslt'm
:I Ch,mnrl Serial PorI
&'rial Communiealinns Controllers
RAM Disk Driwl'
Tl'rminal Controller
'I~'rminal Contl'llller
Vh'xihle j)jsk Controllel'
SMllllisk Contl'lllll'r
Mulli·Prrll)heral Controller
\\inchester Ilisk Controllrr
i'l'riphl'ral Controller
4 Channel Terminal Interrace
Intelligent 4 Ch, Terminal Controllrr
Tl'rminal Coni roller
Prriphrral Contl'lilier
SCSIIlril'er
Pl'riphrral Controllrr/CPU

bU."eflIIO Sys'e. (BIOS)
Thl' gxtrndrd I/O System (~;IOS) providr;; similar services to thl'
IlIOS. with simplifiell!'alls thut giVl' It'ss ('xpllcit ('ontrol or device
hehavior anll performanrt', The ~;IOS also provides a logical·tl>
physical devil'!' l'llnnet'lion, anll allows a program to specify a
logical addl'l'ss ror output.

2-43

FE"TIlRES
II.'tW'IJIIl ~e'" I.rert_ce (IIDI)
The Universal Development Interface provides an easy to use
Interface with a standard set of system calls to allow programs
and languages to be easily transported to or from iRMX II
Operating Systems to other operating systems that support the
UDI standard.

"H·klltle. '-*"

The Application Loader Is used to load programs from mass
storage into memory. Programs may be loaded under pro~ram or
operator control.

...,.".." '-*"

The Bootstrap Loader is used at initialization to load the
operating system or an application system from mass st.oragf
Into memory. and then to begin the system's execution.

S1'SU. De6.~
The System Oehugger is used to dehug applications and give a
view Into the system Itself.

".. . . ,lICft'Iace
The Human Interface allows multiple users to effectively 'develop
applications. maintain files. run programs. and communicate
with the operating system. It consists of a set of system calls. a
set of commands. and a Command Line Interpreter. Commands
are available for file management. device management. and
system status. The Command Line Interpreter is a sophisticated
tool for program development and system design. Its fe,atures
include dynamic logon. full line editing. user extensions. and
support for background jobs. In addition. the Command Line
Interpreter may be replaced for special applications. For
example. a Computer Aided Tomography (CAT) scanner controlled
by iRMX II software can use a custom Command Line Interpreter
to allow the operator to direct the movcment of the scanner.
iRMX networking alluws your real time application to
communicate effectiveliwith general purpose computer systems
as well as other realtime systems.
IRMlX~ ..

c:o.flpratl•• Size °

System Layer

Codp, Size Data Sizp,

Nucleus
Nucleus Comm. Service
BIOS
(';IOS

34KB
17KB
97KB
19KB
9KB
10KR
35KR
84KB

UDI
Application Loader
System Debugger
Human In\,P,rface

2KB
3KB
108 bytes
16 bytes
32 bytes
100 hytes
lKB
224 hytes

°Alllayp,rs are optional except the nucleus.

IRMXS" _.,,'RMX-NEr" So/lware Ma"e
1'IIeI_,*lqEilsy
Systems using iRMX II software are easily networked to other
iRMX. DOS. VAXNMS. or X(,;NIX systems using iRMX-N(';T
networking software. a member of Intel·s family of OpenN(,;'!""
network software products. Using this software. a local system
can access files on other systems connected to the network.
including the ability to Backup and Restore files to a remote
system or disk. This network file access is transparent to the
local system. even if the remo\,p, sys\,P,ms liSP, an operating system
other than iRMX II software.

MULTIBUS I systems have the added capability of booting over
the network and executing as a diskless workst

NITS

1fr«1e. MalNltlJe~.'
R!)$CRK'\m$R~:GIOI\

R!)$Df:Lf:n;$Rf:GION
RI)$S~;ND$CONTR()L
R!)$:\(;C~:PT$CONTR()L

R!)$Rr;C~:I\,E$CONTROL

RQ$DEL~TE$SEGM~NT

RQ$GET$SIZE
RQ$SI>T$POOL$MIN
. RQ$GET$POOL$ATTRIB
RQ~:$(a:T$PO()L$ATTRIJl

R(.)~:$CR~:ATf:$D~:SCRIPT()R

~Q~:$DEI,~:T~:$D~:SCRIPTOR

Se...1IIIorr 1tIa_~~.,
RI)$CRf:'\n:$S~:MAPIIOR~:
RI)$J)~:I.~:T~:$S~:~1.,\PIIOR~:
RI)$S~;\,jD$IINITS

RQ$CREATE$SEGMENT

Creatt's a region
flt>letes a rt'gion
Rt'linquishes ('ontr()1 lolhe nt"1 task
\loiling at the regioll
Causes the railing task to accept
cuntrol from a re.gion if control is
immediately availahle
Causes the calling task to wait at tht'
region unlil the task reeeives ('(Intml

RQE$eHANG~:$IJ~:SCRIPT()~

Creates a memory segmt'llt
Rrturns a segmem to the memory
pool from which it was allorali'd
Returns the size of a segment
Changes the minimum size of the
memory ptlol of the caller's loh
Returns memory pt~ll aUrih"les
of the caller's loh
Ret."rns information ahoul a joh
with more t.han I megahytt' of
memory
Cr"atrs a deseripUlr in the Glohal
Descriptor Tahle drscrihing a
memory segmt'nt
Removt's a descriptor t'ntry from
tht' Glol,al IkstTiptor Talllt'
Changes thr physical add"rss or
Hizt' of a mt'mory

~wgrnl'nl

hjt

modifying its lit'''Tipto,' in Ihe
(;Iollal Descriptor Talllt'
KQ$eRr:!VI'~:$llln'~;R$I'()()L Estahlishes a huflt'r pool anti
ASE$lll 1FFr:R
Rrturns a buffer tu the specified
hulfer prl
Retul'ns thl' type {'otll' of ,nl
oiljret

RI)$L(J(J~l'P$IJIl.lECT

RI,JE$GET$(JHJf:CT$.\CCESS
R~Jf:$CH\~GE$OIl.lECT$n

re;

ROf:$Cf:T$\DDRf:SS
RO$CET$T\ PI-:

BUr.8". Ollleel MIINwe_r.,
Rt)$CREYI'E$f:\Tf:NSION
RO$DfU:Tr;$r;XTENSION

e,ratt'S a llew I; po of ohjert
Dell't!'s the m'w tYl!t' oj' ohjl'l'l anll
all

ill~lallres

of that IYIW

(;o_/t08/.e O"/ee. IfIIINwe..e••
~1)$CRf:'Wf:$CO~II'OSITr:

Creates a IIl'W Oiljl'!'t of a I; IW
tiefim'tillY

RI,I$Ilr:I.~:n:SCmll'OSITI':

Ilt'lett's a new oiljert of a tYllt'
tiefillt'tll"
RQSCRf:.\TE$EXTf:NSH J~
Replan's t'Olllllllnents oj t'IIlllposilt'

R~I$CR~::Wf;$E'\TEN~IIJN

RI)$:\I:r(o;R$C()~II'OSln:

(Ihil'ets
RI)$IN~l'f:CT$CO~II'OSITr:

Rt'tlll'l1s a list of the rtHnpoJlt'1I1
't,kl'ns "Ililtaill('ll in n l'ompositl'

olllt't't

U/lClVlI.t: Sys'r.. ~'Ue.,do.
RI)E$Sf:T$OS$I,:\n:NSION
RI)$SICN.\L$K\CJo:I'TIO~

MIIN~r.r••

·\lIarllt's a IIs!'r written svstt'm ('[111
to tilt' ollt'rmlng systt'm .
Signals tht' Offllrrt'llt"eOr an
1'\t'I'plioll to a user written system ('jIll 10

Iht' opt'r;)ling

S~'slplll

Dr'r'''. (;o.'I'O/,U".""r.e.,
,lla,,'s all fllljt'rt illllllUlll' to ordinary
Ri.l$IlIS·IIlI.ESIlEL~;TIII"

RI)$I':~·\IlI.E$IlEI.I';T10N
RI,I$FllkC~;$IlI':I.I':T1':

dt'lt'tion
"laht'S an olljt'rt sust't')llIhll' to
onlillal'Y dt'lt'tion
1lt'It'lt'S ohjt'rts "ho,t' tii,alliing
dl'plh~

al'(' zt't'O 01' om'

BASIC 110 SYSTEM
.Jell £ewr'
RO$SET$DEFlLLT$PREFI.\ Set dl'faull prefix 1'01' joh
RI,J$Cf:TSfJEFIl'LT$PRf:FL\ Inspect default prrflx
Sl'1 default "SI'I' 1'01' joh
RO$S~T$DEI':\L'LT$L'SER
Inspect offallit 115el'
Rl)$GETSfJf:FIl'lJ$l'Sf:R
~~Ill'I)dt's uSt:'t' pas~i\\(I['d
RO$E\CR\I'T

RI)$!I$(;r:T$CI IN Nf:t :'1'11 IN$S'I"I'I'l'S
KI)$ . \$(;r:T$11IK~;CTi IK\ $r:NTK\
RI,l$\$(;r:T$FILI':$STSrl'S

Drw/~£erel

slll 1U!'t

RO$\SPH\ SIC\L$\THCH$DI-:\·ICI-:
RC}$\$PH\ SIr,\L$OEHCH$OE\ICr:
R(,lS\$SPf:CI \1,

1,;lIrhl'olloOS gt't
ronnt'Ction sta!llS
·ISYlll'ill'lltlflUS inspt't't
din'l'!ol'; t'llIr,
·Isynrhronflus gt't hit'

\sy·nrhronou5 attarh
dp\"ic'P
\s\nchronons ((PWch
((e;ice
-\s~'nrhrllnous

perform

tierice-Iel'el function

kl)$\$(;f:T$PITII$CmIl'ONIWI'

·Isy·nchronous oiltain )lotll
nall1t' from t'onlwction

tok"n

liNer Ob/e€IS
KI,J$CRI'::\TI':$\'SI':R Cn'att' a IISt'I" ohjt'rt
K()$IlEI.I':TI':$['Sr:R Ildt'tt' a IISt'1" oiJit't't
RO$INSPECT$['SI':R (;t't Ills ill a IISt'1" IIhil'!'t

I'Ilr£e~rl

ROS.\$CRK\TI-:$FILr:
ROS.\$CRKWf:$DI REe,1 JR\
ROS.\$DELETESFILE
RC}S\$\THCH$FILE
ROS.\Sm:Lf:n:Sc(J~NEGrJ(JN

\srnchronous !Iata fill' creation

l,~;'nchron(Jus C'rt'alt' a directory

Bx'r.8loa Billa
~1)$:\$Sr:TSE'\Tr:NSION$1l I'n

.\::;ynl'hronous (it:,lt'lt' a dulH fill'

RI,l$·I$I:r:'I'$K\TI':NSHINSIl\T. I

conllt'ction

T1.r/B"'r

a{'('t'~s

.lsYII!'lmltlous ston' a filt's
!''\tension data

or a directory
. \synchronous attach file
. \synchronous cielt'te filt'

IS;Ilt'lm,"olls n'cdle II file's
t'\tt'llsion

data

RI)S.I$CH.\NGE$.ICCESS

Asynchnmous chang«'
rights to a file

R(,I$Sf:nTIW':

St't dalt'Ailllt' lalut' in illternally-

ROS\$RE\\~IE$FILE

:\synrhronllus rt'nHnlt' fiJI'
Asynchronous truncate filt.'

K(,I$m:T$'I'I~IE

:\s;·nchronous open file
.\sy·nchronous close file
\synrhronous rearl file
'synchronolls write file
-\synrhronotls rnilVf rilr ptlinlc'l'
\synrhronous finish wriling to
olltput (Iplirt'
Svnchl'onous wait fol' status
after InpuliOulput

RI,l$Sr:TSI;LlIIlO\L$TI~Ir:

eet dall'ililllt' laille in illlel'tlally'
ston'd fllnlH.ll
St'ts tilt' iJattl'l'y llal'kt'd·up hm'tlwure
.-Iork to a Slw!'ifteti time
Ohtains tilt' tilllt' of day from thl'

RQS\$TRlNGm:
ROSI$OPE\
ROS\$CLOSE
R~IS\$RE\1l

ROS\$\\ RITf:
R~IS\$SEEf,.

RC}S\$lPo.m:
ROS\\.\IT$IO

slol'{'d fOl'lIIat

RI,l$(;~:T$(;Wfl.\I.$T1"lf:

lJattl'ry

fAIIlclll

hil{,~I'(f'IIP

'0 rllYNlaI' """reNH
(;o."rl'H".
Kt'illl'tls the phys;ral arltll'l'", Ill' a

KI)$IlI()S$(;~:'I'$AIlIlR~:SS

St'lt'ClOr

2-47

hanlwart> clock

SYSTEM f:ALLS
'"SIC 110 SfSFBItI (co."••e4)
IIIIJU'IIIIJS" ..."".."" 1IIIIMIer,.".
BSSSENO
Send a message to a remote port
BSSRIo:CIo:IVIo:
Receives a data message
BSSSIo:NOSRSVP
Sends a message to a remote port
and requests a reply
BSSBROAOCAST
Broadcasts a control meRl\llge 1.0 all
boards
BSSSETSINTERCON:'
VR Display 110 Request/Result Segnwnt
VS Display stack and system enll information
VT Display any iRMX II object
VU Display system calls in a task·s stack

2-49

SYSTEM

~t\

.... S

H • •a.'.rerrace

uor.-s••

RQ$C$GI'.:T$IWUT$
CONNECfION
RQ$(,'$GI'.:T$OUTPUT$
CO\lNECfION

ee..1l11f1 U.e .1IIftJJI'deI' ee..,,11118

Return an I-:IOS connection for thA
spl'fified input liIe
Return an I<.:IOS wnncctlon for the
specified output file

~IIIIhrsI.

RQ$C$BACKL!P$CHAR

Move the parsing buffer polnWr
back one byte
RQ$C$GET$CHAR
Get a character from the
command line
RQ$C$G~:T$INPL!T$
Parse the mmmand line ",I~
PATHNAME
return an input pathname
RQ$C$GI'T$OI'TrUT$
Parse lhe command Ime an~
PATHNAMI'.:
return an output palhname
RQ$C$GET$P.~RAMI'TI'R
rarse the command line for Ihe
next parameter and return it as a
keyword name and a value
RQ$CSSET$PARSE$BUFFER Parse a buffer other Ihan the
current command line
RQ$C$GETSCOMMAND$
Return the command name by
NAME
which the current command was
Invoked
~

1"nH:etJ8'__

Create a default messagf for an
ex('('ptlon cod('
RO$C$SI-:ND$COSRI-:SPONSI' Send a message to the command
output (CU) and read a response
from the command Input (CI)
RQ$CSSIlND$EO$RESPONSt.; Send a message to the operator's
terminal and return a response
from that terminal
RQ$C$f'ORMAT$~XCI-:PTION

c.-1111

r.-r.I.

RQSC$GRI-:ATIl$C()MMANDS Greate a command conn('etion
CONN~CfIO~

RQ$CSDIlLIlTIl$COMMAND$ Delete a command connection
CONNI<.:CfION .
Concalenate command lines Into
RQSC$SIlND$COMMAND
the data structure cN',llted by
CR~:Am$COM\1A'lD$·

GONN,;CTION and then invoke the
command

l"Iw/fnIa C.""..
RO$C$SI-:T$CONTROLSC Changes a calling task's GONTROL-C
exchange to the semaphore speCified
by the call

Recalls a Sllt'cllit'd command line
Alias
Assigns un ulJbn'~ iation to a rHlnmwld
Background Caust's a command to bt' t'xecu\('d III baekground
Illodl'

Changeid
iX'alius
Ilxll
Hislory
Johs

1\111
Logoff
Sel

Suhmit

Chanb't's the currt'nl USt'I' II> to an~' valli!' llt'lween
II and 6;;535
Cance)s lhe ahhl'elialion assigned by ;\lias
I.t'es the names of Illes or ,1IJ't'ftories
Kxamlnp a text file a s('r!'fnful ata time
Display or m()(Ji[y the ('onneelion or lermlnal
altrihute
C()nwrl to upper or 11)\\('1' cus('
Display directory hierarrhy and disk usaI,'('
({('IX)rts n'p('at('d lint'S ill a fill'
Copies files, via Ihl' iSml monilm: from all Inteilt'l'
Ilt'vl'loPIU('lIt S~stelll 10 an iRMX II \olulIl('

SI'STEM c;Al..l..S
BIJMAN INTEIlI'A(;E ((;o.." ..ued)
r:___8

1eI..-

fIIII.a~.

Com hines the IlUtput 01 I.OCDATA and an iRMX II
houtloadahle lilr., TIw oUlput 01 ADDLOC is
anuthrr IRMX II hIK.tluadahll' Iile
Auarhdrvil"l' t\tlal~hrs a new physical (kvice 10 thr sysWm und
calalo~s its loglral namt' in till' root job's object
dil"t'ltory
Backup
CIlpirs nmned liIes Ul a Ilat~kull vulumt'
IJtoLlichtlt'vit",' R,'mows a physical .it'vier Irum syslf'm USf' and
d"it't"s its logical nam,' Irum Ih,' nK.I joh's Uhjl'l't
tlir,,'IIII'Y
Iliskwrif~
Vt'rili,'s Iht' dala "lrLlI'lurt'S III' naml'd anti ph~sical
lolum,'"
\\ril,'s furmal informlliion un lin it.:~I.\ II mlul1w
~"rmal
I.llt'llulll,
R"ad" Ih,' spt'rifi,'d .Iala llllil Iwatt'S a "Iocalt'd"
fiI,'lhall'an ht' Ilrllt','s';('1I h~ Iht' AIlDLOC
I'tImmand
!llIls a uSt'r st'ssiun f'lr US"rH lI'ith H customized
Cummand I.in(' Inlt'rprel.t'r

SUller
linlol'k

Chan~es passwords rur dynamic lI'1lon users and
creau's new users whell invu!u'd by Ihe sysl,'m
mallager
Chanb~'S Iht' opt'rator's Usel' ID into thot of Ihe
system manager (U~I' II) 0) for users whll are using
a rustom Cummand Line Intrrprete.r
Permits the Uuman Inlt'rfaer Ul tTrat" an interaclive
joh, afler the terminal has heen lorketl hy I,he LOCK

rnmmand
Datr
Drhug

K"Hds or sels lilt' h"'HI/glohal "Iork IIUlI'
Transfers conlrulllllht' is/lM mllnilm' In dehug
lin iRMX II appli"alion Ilrogr,lm
I.ogiralnam,'s Lists all the Illgit'ullUlIIU'S illailahl,'ltllh,' US"I'
Memory
lJisplays lilt' 1I"'mur~ al'ailahlt'lu Ih" uSt'r
Prompts the uSt;r II ith, a nlt'ssagl' an,1 wails for a
Pausl'
('arl'iagl' l'l'tUl'1l

I'ath
Shuldown
Suhmil

Time
VerSion
Whoami
~sl'an

Shows the palhnam,' fo a fiI,'
Pmvides an urd,'rly shuldll\\'Il of Ih"
~(·mls. \UUdN.

s~'slt'm

and f;'M,('Ult'S tI :O:ll'in:! Ilf C'IImrnlllHls

frum srcondary sturag" inst,'ad of I'rumll,,'
k('yhuard Illr uSt'rs wilh a rustom Com maud Lim'
Inlerprelt'r
Reads ur St'ts the IOl'allgluhul t'III.. k liml' '
Displays the Vl'rsion mlmhers ur I~lmmmllis
Displays the rurrenlill assucialed with Iht' US('I'
Lists Ihe Z,~Ps (updales) appllrd III an ubjecl
modul(', lihrary, ur tXlUUoaciahle file

ORDERING INFORMATION
,"/flX II OPEIltlTIN6 SYSTEMS

£I(;ENSING

Versions or iRMX II Olll'mUng 8,sl.,'ms aI'" availahll'l.u SUPIXlr!
('ompum'nl, Multihus I alld Mullihus lI,has('d d('signs, th" System
:100 SI'ril's mil'l'Ill'llmpul('I'S, anrllht' Sys!t'm',,20,
'

Ilrfurr iRMX II sliftware williI(' shillp,'d, a ('uslum,'1' lIIusl sign (Ill'
haVl' alrt'ady signed) Inwl's Su!t",ar(' !.il'I'IlS(' A~rt'I'III('nt (SI.A),
Ont't' tht' SLA Is si~nt'll. thl' ('ustumt'!' is 1i(,t'IIS1~1 fill' (1('v,'lollm,'nl.
Guslllmers whll want 10 "lm'UrjHlralt'" (lurliuus or tilt' iRMX II
Ohjt',t etlll,' ill all a(l(llit'aliun, wIll lIaw III sign an l",wplII'atiun
!.it'l'nsl' II'hil'h cI,'arly Slll'lIs out tilt' tel'tns and mnditions 'lIIder
"'lIi"1I inml'lltlr publitihed specinrauunslln 11ll'S!' dl'\'ln'l4 from InIt! Ann i~ !lubjtrt lU (itanll£".lWithoulllOl.lre.
,
Scp&ember. 1988
Cl hUt'l torporalKln 1988

flNk'r ...mbtr :.1806790001

2-52

FEATURES
SJ'tlNlMRD IJNIX· ENJ'IRONMENJ'
Developed over the past twenty years. first at AT&T Bell
Laboratories. Wen in Universities and more rccently in
commercial organizations. UNIX is the most popular multi·
user. multitasking operating system Hvailahle for multiple
wmputer architectures. from micros to mainframes. UNIX
System V/386 is the standard interactive. mulli·user
()perating system for the 386.
The UNIX system offers one of the richest development
environments available and is the most widely used in
technical settings. where its I(){lieal. hierarchical structure.
uniform Ii Ie and device 110. ease of reconfiguratio'n and
wealth of applications and tools make it the system software
environment of choice for multi· user. multi·tasking
applications.
Intt'l has worked with AT&T and others to produce UNIX
System V for the 80386. and will continue to offer new
versions and releases lor the 386 and luture Intel
microprocessors. Intel is also active in numerous UNIX
standardization efforts. chief among them being the IUSI'I
group and IEEE POSIX definitions. As these and other
standards are defined. Intel will provide them for MULTIBUS
environments.

SJ'tlNlMRD FEtlTIJRES
• MULTIBUS II support including an application level
interface to MULTIBUS II transport. driver and kernel·
Ie..el support for message paSSing and interconnect space
access.
• Complete. enhanced UNIX de..elopment enVironment.
including 'krslon 4.1 of the C Programming Language
Utilities. System Generation Utilities. the Advanr:ed
Programming Utilities and Productivity tools. Intel
enhancements include an improved kernel debugger.
COFF-to·lntel OMF' convevsion tools and Virtual 86 UDI
tools support.
• SystelU V Enhancements. including t'J(ecutable shared
libraries. demand paging/virtual memory. reliable signals.
the 2KB me system. file and record locking. me{!ia
independent UUCp. extenSive terminal support utilities.
the terminfo database and tools. and multiple installation
and system administration tools and enhancements from
previous releases.

• STREAMS and TLI support. including support for a
STRI':AMS·hased version of OpenNET providing
intcroperation with RMXNET. XNXNET. MSNET. and
V\ISNET and support for the ISO/OSI Transport Layer
Interface.
• International environments support including full support
for 8·hit code sets. alternate date and time formats. and
alternate character and conversion sets.

UCENSING
~:ach copy of UNIX is licensed for use on a single system.
and Intel provides licenses for copying and distributing
MULTI BUS versions of System V/386. Licensing lor the use
of source code and distrihution of binary. derived works is
also availahle.

SOIJRCE RELEtiSES
Complete MULTIBUS I and II source bases are available to
!IT&T and Intel·licensed sites. Device driver source licenses
and code are also available independent of the complete
UNIX source base.

HtlRDWtlRE RE()IJIRED
Intel System V/386 is availahle for standard conligurations
of the MULTIBUS lI·based Modules Development Platform
(SYPMDP) and the System 520. MULTIBUS I versions are
available from Intel and other authorized vendors.
~T&SlJrroRr,CONS~nNG~ND

TRtllNING
Intel's world·wide support organization provides phone
support. troubleshooting guides and updates. On·site or off·
site consulting engineers are available. as are training
courses in device driver writing and system internals.
Ninety days of support and service are included with the
product. Extended hardware service. software SUIJport ami
consulting contracts are also available.

ORDERING INFORMATION

MBlIMDP.
MBlIMDP2

Single p('()(''Cssor MULTI BUS II
Modules Development Platform
Dual pmcessor MULTIBUS II
Modules Development Platform

Sl'STEM 520
Sl'STEMV38611

"lIN!.' is 11 l'C-gisWIt"{llmilt'mark It ,\1'&1
Ml'l.l'llillS,

:mtl. and ()pt'llll.jt:'I' an'll,ltlt'm
NPXerror

8259A PIC master
8259A PIC slaves
* Available tq users *

New Calls
GENERAL RULES
IMPORTANT
Here are some general rules to apply.

All iRMX 286 system calls beginning with RQ$ ... are 100% compatible with iRMX 86.

All iRMX 286 system calls beginning with RQE$ ... are new to iRMX and exist only in iRMX 286.
a. All iRMX 86 system calls beginning with RQ$ ... for which there is a like iRMX 286 system call beginning
with a RQE$ ... use the function procedure of the RQE$ ... call.

All iRMX 286 system calls and user extensions use call gates.

All iRMX 86 BIOS, EIOS, and loader calls are 100% compatible with iRMX 286 calls.

All objects are identified by 16-bit tokens which represent an entry in the Global Descriptor Table (GDT).

The iRMX 286 system call RQE$SET$OS$EXTENSION must be used in place of
RQ$SET$OS$EXTENSION. This call dynamically .attaches an operating system extension to a call gate.
A few specific system calls merit further discussion.

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RQE$SET$OS$EXTENSION
This system call as mentioned in Rule 6 above will find the following usage.

DECLARE
. Typical PUM 286 statements
MY$OS$EXT: PROCEDURE EXTERNAL;

. Typical PUM 286 statements
END MY$OS$EXT;
CALL RQE$SET$EXTENSION (0141H, @MY$OS$EXT, @STATUS);
Where: 0141H represents the entry number of the call gate from the GOT. This parameter is named
GATE$NUMBER.
@MY$OS$EXT represents the pointer to first instruction of MY$OS$EXT. This parameter is
named START$ADOR.
: @STATUS represents a pointer to a word containing the condition code for this call. This param~
ter is named EXCEPT$PTR.
A user-written operating system extension can also be attached to a call by the Interactive Configuration Utility (ICU).
Example of an ICU screen:

OS Extension
(GSN) GOT s.lot number
(OCN) entry point name

[0140H-01 FFEH] 0141 H
[1'-45 characters] MY$OS$EXT

Enter changes [Abbreviation 11= NEW_VALUE]:
Do you need any more O.S. extensions?
This causes the GDT slot 141H to be configured as a call gate whose entry point is MY$OS$EXT.

RQE$CREATE$JOB
This call is an example of Rule 2a where two calls perform nearly the same function. In this case the extended versions of
POOL$MIN and POOL$MAX parameters are DWORDS instead of WORDS. This is to allow a memory pool of up to
16MB for tasks and objects. WhileRQ$CREATE$JOB will create a memory pool of up to 1MB, it will use the same
function procedure as RQE$CREATE$JOB. This is possible because the RQ$CREATE$JOB interface procedure changes
the word pool parameters to DWORDS by padding them with zeros, then calling the RQE$CREATE$JOB function
procedure.

RQ$CREATE$SEGMENT
This call's first parameters, SIZE, yields a different value than in iRMX 86.

In iRMX 86: Segment = RQ$CREATE$SEGMENT (SIZE, EXCEPT$PTR);
Where: SIZE is a word containing the size, in bytes, of the requested segment in MULTIPLES OF
16 BYTES.
In iRMX 286: SEGMENT = RQ$CREATE$SEGMENT (SIZE, EXCEPT$PTR);
Where: SIZE is a word containing the actual memory size in bytes.
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RQ$GET$POOl$ATTRIB
In this case more parameters have been added.
In iRMX 86:
Where:

RQ$GET$POOL$ATTRIB (ATTRIB$PTR, EXCEPT$PTR);
ATTRIB$PTR is a painter to the following structure.
Structure

In iRMX 286:

(POOLMAX WORD,
POOLMIN WORD,
INITIAL$SIZE WORD,
ALLOCATED WORD,
AVAILABLE WORD);

RQE$GET$POOL$ATTRIB has a different structure though everything else is the same
Structure

(TARGET$JOB TOKEN,
PARENT$JOB TOKEN,
POOLMAX DWORD,
POOLMIN DWORD,
INITIAL$SIZE DWORD,
ALLOCATED DWORD,
AVAILABLE DWORD,
BORROWED DWORD);

RQ$SET$INTERRUPT
Users should also be aware of the following when using this call in iRMX 286. When specifying interrupts in iRMX 286,
a special descriptor table called the Interrupt Descriptor Table (IDT) is located at a user-specified address in memory. This
table is accessible through an entry in the Global Descriptor Table (GDT). This makes an interrupt procedure entry point
to be directly accessed via a jump to the specific SELECTOR:OFFSET pointer in the IDT. All interrupts will have a
SELECTOR:OFFSET address just as in the iRMX 86 operating system. Therefore, the system calls syntax will remain
the same, except the parameter called INTERRUPT$HANDLER as shown below:
Example: iRMX 286
CALL RQ$SET$INTERRUPT (LEVEL, INTERRUPT$FLAGS, INTERRUPT$HANDLER,
INT$HANDLER$DS, EXCEPT$PTR);
Where INTERRUPT$HANDLER, the entry point to the interrupt handler, should be coded directly, i.e.,
@MY$HANDLER.
By referencing a handler directly, all other intermediate steps are unnecessary. (See the example in the PLIM 286 section.)

BASIC INPUT/OUTPUT SYSTEM (BIOS)
The BIOS of the iRMX 86 operating system is nearly identical to the iRMX 86 operating system BIOS. The same system
calls are available with no changes or additions. The significant differences between the two BIOS's are the 16MB
addressability and memory protection available in the iRMX 286 operating system.

Protection
The memory protection offered by the iRMX 286 operating system BIOS protects the code and data by preventing any task
from reading or writing a segment of memory unless explicit access has been granted. It also prevents memory reads or
writes from crossing segment boundaries. Therefore any task using the A$READ or A$WRITE BIOS system calls must
have read or write access priVileges.
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Device Drivers
Not all iRMX 86 operating system device drivers have been included in the iRMX 286 operating system. Consult the
following list or the iRMX 286 Interactive Configuration Utility for the specific Intel-supplied drivers.

Intel Device Drivers Supplied With iRMX® 286R. 2.0
iSBC® 215G
iSBC214
iSBXTM 218A
iSBX 217C
iSBC220
iSBC 208
iSBX251
iSBC264
iSBX 350 Line Printer
Li ne Pri nter for 286/1 0

iSBC 534
iSBC 544
Terminal Comm Cntlr
to include:
iSBC 188148
iSBC 188/56
iSBC 546
iSBC 547
iSBC 548
8274
8251A
82530
RAM disk

iSBC 286/10
iSBC 286/10A
iSBC 286/1 X
iSBC 386/2X

Not included are the following device drivers:

iSBC 204
iSBC 206

SCSI
iSBC 226

EXTENDED INPUT/OUTPUT SYSTEM (EIOS)
The EIOS of the iRMX 286 operating system is nearly identical to the iRMX 86 operating system EIOS. The same system
calls are available with few changes and additions. The significant differences between the two EIOS's are the 16MB
addressability and memory protection available in the iRMX 286 operating system.

Protection
The memory protection offered by the iRMX 286 operating system EIOS protects the code and data by preventing any task
from reading or writing a segment of memory unless explicit access has been granted. It also prevents memory reads and
writes from crossing segment boundaries. The system calls S$READ$MOVE and S$WRITE$MOVE are two calls that
will send an exception code called E$BAD$BUFF whenever this occurs.

Extended Memory Pool
Since the iRMX 286 operating system supports the 16MB addressability of the 80286 processor, the memory pools
created by 110 jobs can also be as large as 16MB. The new system call providing this feature is called RQE$CREATE$
IO$JOB.

New Calls
Several new system calls have been added to the iRMX 286 operating system EIOS layer. They are:

1. RQE$CREATE$IO$JOB
POOLMIN and POOLMAX parameters changed to DWORDS for 16MB addressability.
2.

RQS$GET$DIRECTORY$ENTRY
Retrieve name of any file in a directory.

RQS$GET$PATH$COMPONENT
Retrieve name of any file as it is known in its parent directory.

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iRMX® 286 APPLICATION LOADER
802860MF
Two utilities are supplied with the iRMX 286 operating system to load programs and data into system memory from
secondary storage devices. They are the bootstrap loader and the application loader. Typically the bootstrap loader is used
to load the initial system and begin its execution. The application loader will typically be called, by programs running in
the system, to load additional programs. The application loader can load I/O jobs up to 16MB. These programs must be in
the 80286 Object Module Format (OMF). This differs from the iRMX 86 operating system, which loads only 8086 OMF
records. Further, the 80286 records must be in STL format. (See a later section called BND 286 for a discussion of STL
format.)

New Calls
RQE$A$LOAD$IO$JOB

This calls memory pools changed to DWORD values from word. (See RQE$CREATE$JOB call in the Nucleus section.)

RQE$S$LOAD$IO$JOB

Same as above.

HUMAN INTERFACE
Enhanced Command Line Interpreter (CLI)
The new CLI provides line-editing features, as well as its own set of commands. With CLI commands, aliases
can be created, background programs ran, output redirected or redefined for a terminal in the configuration file. The
commands are: .
BACKGROUND

ALIAS
HISTORY

JOBS

KILL

CHANGEID
LOGOFF

SET

DEALIAS
SUBMIT

EXIT
SUPER

To include or customize features in the CLI, user extensions have been added to the Human Interface.

New Calls
ADDLOC

LOGOFF

SHUTDOWN

LOCK

UNLOCK

ZSCAN

Old Calls
The following Human Interface commands have been revised:
BACKUP

DISKVERIFY

FORMAT

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RESTORE

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UDI

New System Calls
The iRMX 286 UDI contains three system calls not contained in the iRMX 86 UDI. They are:
DQ$MALLOCATE
DQ$MFREE
DQ$GET$MSIZE
All of the calls have their counterparts in the iRMX 86 UDI, however, the new system calls use full pointers instead of
selectors and DWORD instead of WORD for memory block start address and size specifications, respectively.
These three calls are only supported in programs compiled in the compact or large segmentation models. Also, earlier
versions of these calls cannot be mixed. For example:
After using DQ$MALLOCATE to allocate memory, do not use DQ$FREE to free it.
Use DQ$MFREE instead.

BOOTSTRAP LOADER
Two Stage Loader
To facilitate loading an application so that it may execute has been known as "pulling it up by its bootstraps" or simply
"booting" the application. iRMX bootstrap loaders have been divided into stages, each possessing a unique purpose
and role.
In the iRMX 86 operating system, the bootstrap loader exists as only two stages. The first stage resides in PROM located
on the.CPU's board. If supplied by Intel, it will occupy less than 8Kb of memory within the PROM. Once running, it will
identify the applications name and location, then load part of the second stage, passing control to it. The second stage
finishes loading itself, loads the application into memory, then passes control to the application. While the first stage is
user-configurable, the second stage is not. The second stage is only supplied by Intel and is present on all iRMX
formatted, named volumes.

New Third Stage
1Il r;,<:;

iRMX 286 operating system, the bootstrap loader exists as three stages. The extra stage was added to be able to load
80286 OMF fIles. This will also permit loading 8086 OMF fIles with just the first and second stages. This means either
system can be booted without compromising the other. To allow for this, some fIles have to be renamed and some new
conventions adopted. (See below and Figure 3.)
1.

All 80286 OMF bootloader application systems must have the extension" .286".

The third stage bootstrap loader must have the same name as the application, less the extension.

The third stage bootstrap loader must reside in the same directory as the bootloadable system.

File Name Conventions
Third Stage

System to be Loaded

ISYSTEM/RMX86

ISYSTEM/RMX86.286

ISYSTEM/RMX

ISYSTEM/RMX.286

IBOOT/RMX286

IBOOT/RMX286.286

This chart indicates to those wanting to boot the iRMX 86 operating system that their fIle ISYSTEM/RMX86 had better
be renamed to avoid confusion.
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INPUT

,
/ii
+

860MF

lsi STAGE
ON·BOARD
PROM

iRMX' FORMATTED
VOLUME WITH
iRMX' 286
BOOTSTRAP 2nd STAGE

iRMX' FORMATTED
VOLUME WITH
iRMX'286
BOOTSTRAP 2nd STAGE
m·OB03

Figure 3.

When installing the iRMX 286 operating system on a system containing the iRMX 86 operating system, the "BS" option
of the format command will install ONLY the new second stage bootstrap loader on track 0 of the hard disk. The
installation process will also add new directories as required by the iRMX 286 operating system.

Memory Locations of the Three Stages
Bootstrap Loader Locations
Config. File

Description

Default

Approx. Size

1st STAGE CODE

Application
dependent

12KB

BS1.CSD

2nd STAGE CODE
1stl2nd DATA
and STACK

OB8000H

8KB

BS1.CSD

3rd STAGE
(specific) CODE
DATA and STACK

OBCOOOH

16KB

BS3.CSD

3rd STAGE
(generic) CODE

OBCOOOH

8KB

BG3.CSD

3rd STAGE
(generic)
DATA and STACK

OB8000H

BG3.csd

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CONFIGURATION SIZE CHART

iRMX® 286
Memory
Requirements

Operating
System
Layer

iRMX® 86·
Code
Size

UDI

34K
95K
19K
12K
36K
11K

Bootstrap Loader

24K
78K
12.5K
10K
22K
8K
1.5K

leu

Nucleus
BIOS
EIOS
Application Loader
HI

iRMX® 286·
Code
Size

27K
67K
16K
11K
26K
9.4K
32K
-

iRMX®86·
Data
Size

iRMX® 286·
Data
Size

2K
1K
1K
2K
15K
OK
6K
308K

3.5K
19.5K
16.75K
2K
1K
O.1K
6K
384K

'These numbers reflect actual memory size required to support the different configurations of the operating systems.

FILE STRUCTURE
The file system of the iRMX 286 operating system provides for the same types of mes as are on the iRMX 86 operating
system. In fact, both me systems can exist on the same volume using the same hierarchical file structure. This is made
possible through the installation of the iRMX 286 bootstrap loader's second stage onto the iRMX 86 operating system's
volume. This second stage will allow either operating system to be booted from the same volume. One fact should be
remembered: iRMX 286 uses the 80286 OMF, while iRMX 86 uses the 8086 OMP. This stops either operating system
from loading and executing the other's files or programs. Copying, deleting or other maintenance operations can still be
accomplished across the volume. iRMX 286 operating system will also read iRMX 86 back-up format mes from another
volume. The following Figure 4 shows a me system with both operating systems installed, including the changes to its
structure. Remember, iRMX 286 can reside by itself or with iRMX 86 on the same volume.

Conventions
New me conventions have been adopted to differentiate between several types of files. They are:
* . P28
*.P86
* .A28
* .A86
*.GAT

PLiM 286 source files
PLiM 86 source files
ASM 286 source files
ASM 86 source files
Gate definition mes

*.BLD

Build, file for BLD 286

*.286

Bootable iRMX 286 system file

*.86

Bootable iRMX 86 system file

After booting iRMX 286, the following assignments are assumed:
: SYSTEM:

ISYS286

: UTIL:

IUTIL286

: LANG:

ILANG286

After booting iRMX 86, the following still apply: '
: SYSTEM:

ISYSTEM

: UTIL:

IUTILS

: LANG:

ILANG

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i
iRMX® 86.286
iRMX' 86.86
DIR
~DIR
COPY
~COPY
SUPER

COPYDIR

cC"

iii
f"

'T1

I\)

m
.....

"P
~

r:::

f
"Denotes lile additions
Diagram rellects the installation of iRMX' 286
upon an iRMX· 86 volume.

'"oa>ex>
o
o

'f'

m-OB07

AP.405
LANGUAGES: ASM 286
Because ASM 286 supports the 80286 in protected mode, ASM 286 has more changes than other languages. Often users
converting their programs to ASM 286 from ASM 86 will assemble the programs in ASM 286 and store the error
messages generated and change the code accordingly. A few notable changes are listed below.

Group Directive
ASM 286 does not possess a group directive as in ASM 86. By giving the segments the same name, they will be grouped
together into one segment at link time.

Example: ASM 86
DATAGRP GROUP DATA 1, DATA2
DATA1 SEGMENT
'
ABYTE DBO
DATA1 ENDS
DATA2 SEGMENT
AWORDDWO '
DATA2ENDS
ASSUME DS:DATAGRP
: ASM286
DATA1 SEGMENT RW PUBLIC
ABYTEDBO
DATA1 ENDS

In one module

DATA1 SEGMENT RW PUBLIC
AWORDDWO
DATA1 ENDS
ASSUME DS:DATA1

In another module

Segment Directive
The fields of the SEGMENT directive ,are also different. ASM 286 does not use anything but para-aligned and
access-type;
"

Example: ASM 86
NAME SEGMENT [ALIGN·TYPE) [COMBINE·TYPE)
WHERE [ALlGN·TYPE) = PARA, BYTE, WORD, PAGE, INPAGE,
OR NONE
ASM286
NAME SEGMENT [ACCESS·TYPE) [COMBINE·TYPE)
WHERE SEGMENT IS ALWAYS PARA·ALlGNED AND
[ACCESS·TYPE) = READ-ONLY (RO),
EXECUTE·ONLY (EO),
EXECUTE-READ (ER), or
READ·WRITE (RW)
Class name is also not present in ASM 286

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Stack Segment
In ASM 286, stack segments are defined using the STACKSEG directive.
Example: ASM 286
PROG_STACK STACKSEG 10;

/* MEANS 10 BYTES ON STACK * /

The operator STACKSTART is used to define a label at the beginning of the stack to initialize the Stack Pointer (SP).
Example: ASM 286
MOV Sp, STACKSTART PROG_STACK

Selector Access
In ASM 286 the selectors used for the DS, SS, and ES in the ASSUME directive must have certain access types.
Example: ASM 286
ASSUME DS:EDATA
EDATA SEGMENT RW PUBLIC
WHERE DBO
EDATAENDS

Further, the ASSUME directive will not accept an assume for the code segment. The current code segment being assembled is automatically assumed into the CS. For more information regarding other changes in ASM 286 consult: ASM 286
Reference Manual (Appendix G), order #122671 .

LANGUAGES: PL/M 286
Users migrating their code to PLiM 286 should be aware of the following:

Pointer and Selector Variables
Pointer and selector variables cannot be assigned absolute values. All values must be assigned by reference to another
variable or through based-variables.
Example: PLIM 86
Declare
A$POINTER

POINTER;

Start: DO;
A$POINTER = 0;
Example: PLIM 286
Declare
A$POINTER
Start: DO;
A$POINTER

POINTER;

= NIL;

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Similarly selectors can be assigned values as follows:
Example: PUM 86
Declare token literally 'WORD',
A$TOKEN
TOKEN;
Start: DO;
A$TOKEN = 0;
Example: PLIM 286
Declare token literally 'SELECTOR',
A$TOKEN
TOKEN;
Start: DO;
A$TOKEN = SELECTOR$OF(NIL);
The only relational operations allowed in PUM 286 for pointers and selectors are "equals" and "not equals".

Models of Compilation
In PUM 86 the default is SMALL
In PUM 286 the default is LARGE

Interrupt Vectors
In PUM 286 all interrupt numbers on all interrupt procedures must be deleted. The required interrupt vectors will be
assigned by the 80286 system builder if not already defined by the iRMX 286 operating system call RQ$SET$
INTERRUPT.
Consequently the PUM 86 built-ins SET$INTERRUPT and INTERRUPT$PTR are unavailable in PUM 286 and should
be removed. Also, all calls to interrupt procedures are not allowed. As the conversion process takes shape, all of these
changes tum out better than initially expected as the following example shows.
Example: PLIM .86
1. DECLARE
2.

ZERO
LITERALLY
'00001000b',
INTERRUPT_HANDLER POINTER;
·

TYPICAL PLIM 86 STATEMENTS

6. INTERRUPLHANOLER: PROCEDURE INTERRUPT 56 PUBLIC REENTRANT;
·

TYPICAL PLIM 86 STATEMENTS

10.
CALL RO$SIGNAL$INTERRUPT (ZERO, @STATUS);
11. END INTERRUPT_HANDLER;
12. INTERRUPT_TASK

: PROCEDURE PUBLIC REENTRANT;
·

16.
17.

INTERRUPT_HANDLER = INTERRUPT$PTR (INTERRUPLHANDLER);
CALL RO$SET$INTERRUPT (ZERO, 1, INTERRUPLHANDLER,
DATA$SEG$ADDRESS.BASE, @STATUS);
·

21.
22.

TYPICAL PUM 86 STATEMENTS

TYPICAL PLIM 86 STATEMENTS

CALL RO$WAIT$INTERRUPT (ZERO, @STATUS);
END INTERRUPT_TASK;

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Comments
Line
Number
2.
6.
16.
17.

Description
INTERRUPT_HANDLER was defined as a pointer
Interrupt entry 56 was."hard-coded"
INTERRUPT_HANDLER was assigned the location (address) of the first instruction of the
handler via the PLIM 86 built-in "INTERRUPT$PTR"
This call could have looked like: RQ$SET$INTERRUPT (ZERO, 1, INTERRUPT_PTR(INTERRUPT_HANDLER), etc eliminating lines 2 and 16.

Example: PLIM 286
1. DECLARE

ZERO

LITERALLY

'00001000b';

· TYPICAL PLIM 286 STATEMENTS
5. INTERRUPT_HANDLER

: PROCEDURE INTERRUPT PUBLIC REENTRANT;
· TYPICAL PLIM 286 STATEMENTS

9.
10.

CALL RQ$SIGNAL$INTERRUPT (ZERO,@STATUS);
END INTERRUPTHANDLER;

11. INTERRUPT_TASK

: PROCEDURE PUBLIC REENTRANT;
· TYPICAL PLIM 286 STATEMENTS

15.

CALL RQ$SET$INTERRUPT (ZERO, 1, @INTERRUPLHANDLER,
DATA$SEG$ADDRESS.BASE, @STATUS);
· TYPICAL PLIM 286 STATEMENTS

19.
20.

CALL RQ$WAIT$INTERRUPT (ZERO, @STATUS);
END INTERRUPT_TASK;

Comments
Line
Number
5.
15.

Description
Notice PLIM 286 does not need to identify the interrupt in this statement
The third parameter becomes simply a pointer to the first instruction of the handler.

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DEVELOPMENT TOOLS -

BND 286

All iRMX 86 programs linked using LINK 86 will instead have to be bound using BND 286. BND 286 is used to create all
single-task application programs that will be dynamically loaded. (See Figure 5.) The following are tasks of the binder.
1.

Creates a linkable or loadable module by combining input modules with other bindable modules.

Checks the type of variables and procedures.

Selects modules from libraries to resolve all symbolic references.

Combines logical segments by name, attribute, and privilege levels into physical segments that the processor can
manipulate efficiently.

Can create a module the application loader can load.

Linkable Modules
In a process called incremental linking, BND 286 combines linkable object modules, including library modules, output by
translators. The result is a file containing a linkable module.

Loadable Modules
A dynamically loadable module created by BND 286 is an executable module created by the combination of one or more
linkable modules. Loadable modules can be of two types:

1. Single-task loadable (STL)
2.

Variable-task loadable (VTL)

r-------,

SOURCE
FILES

r-------..,

r--

I--+-j" TRANSLATOR

I
L
________ JI

OBJECT
(H.OBJ")

r--------,
I

WitH LOAD

LOADABLE

: OPERATING :

:
- : BND286
:~===~l-"'. (EX~~~~~~LE) _!: SYSTEM
LOADER I
:
~
MODULE
I
L _______ J:
L________ J WITH NOLOAD

r-------.,
I
I
I

'-----+-:

I
I
I

SIM286

:L ________ Ji
r--------l

LINKED
OBJECT
MODULE
HLlNK"

LIBRARY
FILE

'--_ _~.:

MAP286

L__

-r-

:
I

r--J---,

LEGEND:
-INPUT AND OUTPUT OF
SOFTWARE PRODUCTS

I
' - - -. . . .,1

LIB286

: .....- - - - <
I

PRINTED
MAPS

L ______ .J

m·0804

----- SOFTWARE PRODUCTS

Figure 5. BND 286 Application Program Development

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STL Modules
These modules are functionally similar to LTL-format records in the 8086 OMF. STL modules are designed to optimize
loader execution time because each contains only one executable task. iRMX 286 and XENIX 286 operating systems will
execute only files containing STL modules. BND 286 outputs STL modules when the FASTLOAD, RCONFIGURE, and
XCONFIGURE controls are specified. In iRMX 286 only, the RCONFIGURE control is used.

VTLModules
VTL modules are designed, when provided by BND 286, to also contain a single executable task, but in a format
structured for multiple tasks. BND 286 outputs VTL modules when the LOAD control is specified.

IRMX' 286 USAGE

T
CONSOLE
MESSAGES

CONSOLE
MESSAGES

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BND 286 TO LINK 86 COMPARISON

BND 286 CONTROLS

LINK 86 CONTROLS

CONTROLFILE (pathname)

DEBUG/NODEBUG

SYMBOLS/NOSYMBOLS

ERRORPRINT (pathname)1
NOERRORPRINT

FASTLOAD/NOFASTLOAD

*LDTSIZE ([ + I number)

LOAD/NOLOAD

NAME (modulename)

OBJECT (pathname)1
NOOBJECT

PACKINOPACK

PRINT (pathname)1
NOPRINT

PUBLlCS/NOPUBLlCS

PUBLlCS/NOPUBLlCS/PUBLlCSONLY

RCONFIGURE (dm,m)

BIND and MEMPOOL

RENAMESEG (old to new)

RESERVE (number)

SEGSIZE (name(size»

*TASKPRIVILEGE ( )

TYPE/NOTYPE

*XCONFIGURE

'Not used in iRMX 286

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The following is an example of BND 286 for a simple human interface Commonly Used System Program (CUSP) used on
an iRMX 286 Release 1.0 system.
BND286

iRMX 286 Libraries-

EXAMPLE.OBJ,

EXAMPLE.LlB,

IRMX286/L1 B/UPI FC. LIB,

IRMX286/L1 B/U DI.GAT,

IRMX286/L1B/HPIFC.LlB,

IRMX286/L1B/HI.GAT,

IRMX286/L1B/LPIFC. LIB,

IRMX286/L1B/LOA.GAT,

IRMX286/L1B/EPIFC. LI B,

IRMX286/L1B/EIO.GAT,

IRMX286/L1 B/IPIFC. LI B,

IRMX286/L1B/IOS.GAT, '

IRMX286/L1 BIN UCIFC. LIB,

IRMX286/L1B/NUC.GAT

iRMX 286 Library Privilege
Gates

RCONFIGURE (DM(10000H, 10000H»
(Analogous to BIND&MEMPOOL)
SEGSIZE (STACK(1024»
(Analogous to segsize)
OBJECT (EXAMPLE)
(A new control)

The following is an example of BND 286 for a simple human interface Commonly Used System Program (CUSP) on an
iRMX 286 Release 2.0 system. Notice all of the .GAT fIles and many of the .UB fIles are gone. All of these "missing"
fIles are now contained in the fIles RMXIFC.LIB and UDIIFC.LIB for convenience.
.
EXAMPLE.OBJ,

EXAMPLE. LIB,

IRMX286/L1B/UDIIFC.LlB,

IRMX286/L1B/RMXIFC.LlB,

BND 286

RCONFIGURE (DM(10000H,10000H»
(Analogous to BIND & MEMPOOL)
SEGSIZE (STACK(1024»
(Analogous to SEGSIZE)
OBJECT (EXAMPLE)
(A new control)

2·75

280608·001

AP-40S

iRMX(R) XXX.BLD File
system_bid;
segment
nucdat.code(dpl == 0),
nucdat.data(dpl = 0),
memory
(reserve
(0 ..0001 FFFH.
003AOOOH ..OFFFFFFh»;

gate
Gate_CreateJob (entry =
RqCreateJob, dpl =0, wc =0),
table
Idt1 (limit = OD600h.dpl == 0,
reserve = (2.;2,4 .. 4AH,
4CH .. 4EH, 51 H .. 59h,
122H .. 005FFh),
entry = ( O:nucdat.escape_ss,
3:nucdat.stack,
75:nucdat.jobdat,
79:nucdat.escape_ss,
80:nucdat.entry_code) );
task
rmxtask (dpl = O,object = nucdat,
Idt = Idt1. no ie);
table
gdt (limit = 00600H, dpl = 0,
reserve = (3.;3BH.30H .. 4EH,
51 H ..53H, 55H .. 59H, OC1 H ..OC7H.
OE3H .. OE5H,OEAH .. OEFH,
101H .. 103H~ 00137h .. 00140h),
entry = (60:nucdat.data.
79:rmxtask,
80:nucdat.code,
84:ldt1,
90:Gate_AcceptControl,
91 :Gate-AlterComposite,

308:sdbcnf.code,
309:sdbcnf .data,
310:sdbcnf.newstack,
291 :bios_code,
292:bios_data,

table

idt(limit =00080h. dpl =0);

end

2-76

AP-405

DEVELOPMENT TOOLS -

BLD 286

BLD 286 exceeds LOC 86 in capability and versatility. In many cases the use of BLD 286 is transparent to iRMX 286
users, due to the ICU 286 automatically generating the BUILD file. All iRMX 286 users, however, should possess an
understanding of the following key functions:
A. Assigns physical addresses to entities, sets segment limits and access rights. (See XXX.BLD file)
B.

Allows memory ranges to be reserved or allocated for specific entities. (See XXX.BLD file)

Creates one Global Descriptor Table (GDT), one Interrupt Descriptor Table (IDT), and one Local Descriptor
.
Table (LDT). (See XXX.BLD file)

D. Creates gates. (See XXX.BLD file)
E. Creates task state segments and (task gates). (See XXX.BLD file)
F.

Creates a bootloadable module. (See XXX.BLD file)

G. Creates object files containing exported system entries. (See XXX.BLD file)
H. Selects required modules from specified libraries automatically, as needed to resolve symbolic references.
I.

Performs reference-resolution and typechecking.

Detects and reports errors and warnings found during processing (in the XXX.MP2 file)

See Figure 6 for an example of BLD 286 program development.

Usage
BLD 286 is primarily used for building an application program that deals extensively with system interfaces to a hardware
environment. This could include configuring gates and/or segments that provide this interface, then place these interfaces
in a separate file for later exportation.
The types of executable output produced by BLD 286 are bootioadable, loadable, or incremental-built. Bootloadable
modules are absolutely-located object modules that are booted via a simple loader. Loadable modules consist of single- or
multiple-task modules used for dynamic loading. Incrementally-built modules are non-executable modules used interactively to build large systems.
Many users will only use BLD 286 when they produce a new configuration using the ICU. ICU 286 generates a file called
ICUBLD.CSD which invokes the builder using the file XXX.BLD as the builder definition file.
The following is a typical example ofthe contents of ICUBLD.CSD:

BLD 286,

&
NUCLUS.LNK,

SDB.LNK,

IOS.LNK,

EIOS.LNK,

LOADER.LNK,

HI.LNK,

UDI.LNK

OBJECT (/BOOT/""" .286)

NODEBUG NOTYPE

(Produced by BND 286)..-1

BUILDFILE (""" .BLD)

( Where to put the
bootloadable file)

( Where to obtain the
build information)

2-77

280608·001

AP-405

LIBRARIES

r--------l

I
80286
I
: TRANSLATORS

'- ________ .J

TRANSLATED
OBJECT
MODULE(S)

BUILD
FILE

BUILDER
EXPORT
MODULE(S)

'NOT USED BY iRMX'" 286

m·0801

Figure 6. BLD286 Application Program Development
The build file contains a specific language used by BLD 286 to produce the system or System program. BLD 286 takes all
linked input modules and assigns all of the access and protection attributes for each subsystem. A build file is created to
specify the characteristics of the relationships among the subsystems. Segment attributes, gates, descriptor tables, aliases,
.
and memory allocation are also described in the build file and read by BLD 286.

2-78

280608-001

AP·405

..-----.., -- ----1 WITH NO BOOTLOAD
BLD286

LOADABLE

. (EXECUTABLE)
1-_____-,
OBJECT

Lif: -------1

I WITH .

MODULE

...•• r· BOOTLOAD

EXAMPLE
LOADER
I

r------,
i

10 . . . . . . ...

•
r----iBOOTLOADER

:~...... ...

r---LL--"l
OBJECT
MODULE
(".OBJ")

BOOTLOADABLE
L.o.
OBJECT
MODULE

~---,
.

'----

If debug information is in "MYPROG" all of the maps will be produced.

IRMX® 86 OPERATING SYSTEM PROGRAM MIGRATION
Compiling In PL/M 286
The following is an example of converting an iRMX 86 Commonly Used System Program (CUSP) called NOTE. To assist
readers, ail of the conversion steps will be described.

Source Program
The program NOTE is written in PLIM 86 for use oli iRMX 86 operating system. When invoked, the utility will echo a
line of keyboard input to the console.
The source code file name for NOTE is NOTE.P86. 1b adhere to PLIM 286 and iRMX 286 operating system file naming
conventions, the file should be renamed to NOTE.P28. Next, the file has to be changed to reflect changes in PL/M 286
and iRMX 286 library files. Finally the tile is compiled and bound with BND 286. See the following examples for further
explanation.
STEP 1
Copy NOTE.P86 to NOTE.P28

< CR >

STEP 2
The NOTE.P28 tile has to be edited to change
A. All '0' pointers to 'NIL'
B. All '0' selectors to 'SELEC'IORS$OF(NIL),
Also notice all of the include files assume an iRMX 86 operating system and have to be changed to iRMX ~86 libraries.
STEP 3
The new NOTE.P28 program is compiled and any errors are corrected.
2-80

280608·001

AP·405

$title('iRMX 86 HI NOTE command')
$subtitle('module header')
/***********************************************************************
TITLE: note
ABSTRACT:
This module contains the main routine for the HI note command.
NOTE

message

Message will be printed on EO.
***********************************************************************/
hnote: DO;
$include(:sd:inc/hstand.lit)
$include(:sd:rmx86/inc/hgtchr.ext)
$include(:sd:rmx86/inc/hsneor.ext)
$include(:sd:inc/hutil.ext)
DECLARE
version(*) BYTE DATA ( 'program_version_number=F001',
'program_name=Note' ,0);
1
2
3

4
5
6
7
8

main: DO;
/* local variables */
DECLARE
excep
WORD,
BYTE,
char
count
WORD,
msg

STRUCTURE (
length
BYTE,
char(STRING$MAX) BYTE) ;

count = 0;
char = rq$C$get$char( @excep);
DO WHILE( (char := rq$C$get$char( @excep» <> 0);
IF count < LAST(msg.char) THEN
DO;
14
msg.char(count) = char;
15
count = count + 1;
16
END;
17
END;
18
msg.char(count) = cr;
19
count = count + 1;
THIS POINTER
20 .
msg. char ( count) = 1£;
NEEDS CHANGING.
21
count = count + 1;
22
msg.length = count;
23
CALL rq$C$send$EO$response( 0, 0, @msg, @excep);
9
10
11
12
13

/* exit from command */
24
25

CALLcusp$error( excep, @(O), @(O), ABORT);
END main;

END hnote;

.PlM 86 Example

2-81

2B060B'()()1

AP·405
$title('iRMX 286 HI NOTE command')
$subtitle('module header')
/***********************************************************************
TITLE: note
ABSTRACT:
This module contains the main routine for the HI note command.
NOTE

message

Message will be printed on EO.
***********************************************************************/
hnote: DO;
$include(:sd:inc/hstand.lit)
$include(:sd:rmx86/inc/hgtchr.ext)
$include(:sd:rmx86/inc/hsneor.ext)
$include(:sd:inc/hutil.ext)
DECLARE
version(*) BYTE DATA(· 'program_version_number=F001',
'program_name=Note' ,0);
1

2
3
4
5

6
7
8
9

10
11

12
13

14
15
16
17

18
19
20
21
22
23

main: DO;
/* local variables */
DECLARE
excep
WORD,
BYTE,
char
WORD,
count
msg

STRUCTURE (
length
BYTE,
char(STRING$MAX) BYTE);

count = 0;
char = rq$C$get$char( @excep);
DO WHILE( (char:= rq$C$get$char( @excep» <> 0);
IF count < LAST(msg.char) THEN
DO;
msg.char(count) ~ char;
count = count + 1;
END;
END;
msg.char(count) = cr;
count = count + 1;
THIS IS
msg.char(count) = If;
) ~_____O_K~N_O_W_.____~
count = count + 1;
msg.length = count;
CALL rq$C$send$EO$response( NIL, 0, @msg, @excep);
/* exit from command */

24
25

CALL cusp$error( excep, @(O), @(O), ABORT);
END main;

END hnote;

PlM 286 Version Example

2-82

280608-001

AP·405

Binding an iRMX® 286 Application
STEP 1

If a program was previously linked in iRMX 86, we then examine the original
LINK file used and notice the following:
PLM86 %0 ..P86 COMPACT ROM OPTIMIZE( 3) NOTYPE PW( 132)

LINK86
%O.obj,
/rmx86/hi/hutil.lib,
&
/lib/plm86/plm86.1ib,
&.
/rmx86/1ib/hpifc.lib,
&
/rmx86/1ib/epifc.lib, &
/rmx86/1ib/ipifc.lib, &
/rmx86/1ib/rpifc.lib &
to %.86
bind mempool(lOOOO,OBOOOOH)
nosb noty

1. The library names will change
2. The pathnames to access the libraries will change
3. BIND and MEMPOOL will change.
STEP 2

The following is the iRMX 286 Release 1.0 version of the file in Step 4.
Remember the libraries have changed names between iRMX 286 Release 1.0 and 2.0.
PLM286%O.p28 G()MPACT ROM OPTIMIZE(3) NOTYPE PW( 132)

bnd286

%O.obj,
&
/rmx286/1ib/hutil.lib,
&
/rmx286/1ib/plm286.1ib,
&
/rmx286/1ib/hpifc.lib, /rmx286/1ib/hi.gat,
&
/rmx286/1ib/epifc.lib. /rmx286/1ib/eio.gat, &
/rmx286/1ib/ipifc.lib, /rmx286/1ib/ios.gat, &
/rmx286/1ib/nucifc.lib, /rmx286/1ib/nuc.gat &
renameseg(hi_code to code, hi_data to data) segsize (stack(1000H))
object(%O) rc(dm(12000,1000000))
nodebug noty

STEP 3

This is an example of the Step 4 file modified to run on iRMX 286 Release
2.0. Notice the reduction of library statements.
PLM286 %O.p28 COMPACT ROM OPTIMIZE(3) NOTYPE PW( 132)

bnd286

%O.obj,
&
/RMX286/hi/hutil.lib,
&
/RMX286/1ib/plm286/plm286.1ib, &
/HMX286/1ib/rmxifc.lib
&
renameseg(hi_code to code, hi_data to data) segsize (stack(1000H))
object(%O) rc(dm(12000,lOOOOOO))
nodebug noty

Though these few migration examples reflect trivial modifications, larger
and more complex applications might require a little more attention.

2-83

280608-001

AP-405

SUMMARY
The purpose of this application note is to provide insight and direction to those individuals contemplating using the iRMX
286 operating system. For those already familiar with the iRMX 86 operating system, this paper's focus is to provide the
pathway to a superior product.
The iRMX 286 operating system is a vast improvement over its previous counterpart. Some notable changes are round
robin scheduling, hardware-enforced protection, hardware-assisted debugging, and access to the 80386 processor. With
this operating system the capabilities of the 80286 processor can be fully utilized for multiple environments.
Since the iRMX product line was introduced, many applications, programs, and lines of code have been written to support
a tangible demand for real-time processing; in manufacturing, in medicine, and in finance, to name a few. As a result
more time is being spent on designing, writing, and testing software than ever before. The iRMX 286 operating system is
the preferred product for generating error-free programs while utilizing the highest CPU technology available in the OEM
modules market.

2-84

280608·001

"'EDIT

SOUR~E

~ODE

AND TEXT EDITOR

rIlO6BA.IfIIfIEB slfrroRT
AEDIT is a full-screen text editing system designed specifically for software engineers and technical
writers_ With the facilities for automatic program block indentation_ HEX display and input. and full
macro support. AEDIT is an essential tool for any programming environment. And with AEDIT. the
output file is the pure ASCII text (or HEX code) you Input-no special characters or proprietary
furma~_
.
Dual file edIting means you can create source code and its supporting documents at the same time.
Keep your program listing with its errors in the background for easy reference while correcting the
source in the foreground. Using the split-screen windowing r.apability. it is easy to compare two files.
or copy text from one to the other. The DOS system-escape command eliminates the need to leave the
editor to compile a program. get a direetory listing. or execute any other program executable at the
DOS system level.
There are no limits Illaced on the size of the file or the length of the lines processed with AEElIT. It
even has a bateh mode for those times when you need to make automatic string substitutions or
insertions in a number of separate text files.

A.EDIT I'EA.TIJBES
• Complete range of editing support-from
document prooessing to HEX cOde entry and
modification
• Supports system escape for quick execution
of PC-DOS System level commands
• Full macro support for complex or repetitive
editing tasks

• Hosted on PC-DOS and RMX operating
systems
• Dual file support with optional split-screen
windowing
• No limit to file size or line length
• Quick response with an easy to use menu
driven interfaL'e
• Configurable and extensible for complete
control of the editing process

inter---------1m.r.1 C.nrporaLIon assumes no responSibility lor Lhe usc (j any Circuitry o!.her lhan circuitry embodied in an Intel pnx1uct. Nu uLhcr circuit paw" IicenliCs are
implied. Information corMaiood herein supersedes prevIOUsly published Speclrlcations on these dc~1res frum Intel and is suhll'Ct \.0 change \\'Ithuut notice.

Scp~mhcr, 1988
Order Number: 280804 002

@ lmel Corporation 1988

2-85

FEATURES
POWERFIlL TEXT EDITOR

MAlJRO SIlPPORT

As a text editor, :\EDIT is versatile and complete, In addition
to simple character insertion and cursor positioning
commands, /\EDIT supports a number of text bloek
pl'Ocessing commands. Using these commands you ran
easily move, copy, or delete both small and large blocks of
text. AI<:DIT also provides facilities for forward or reverse
string searches, string replacement and qurry replace.

AJ.:DIT will create macros hy simply keeping track of the
command and text that you type. "learning" the [unction thl'
mac I'll is to Jll'rform. The editor remt'mhers your actions for
later t'Xl'cution_ or you lTlay storl' them in a rile to use in a
later editing sl'Ssion.

AEDIT removes the restrictilln IIf only inserting characters
when adding or modifying text. When adding text witll
AEDIT you may choose to either insert characters at til('
current cursuI' locatilln. III' liver-write till' existing t('xt as YIIU
type. This flexibility simpliFif'S the rrPm ion ami f~iliting of
tahles and charts.

IlSER INTERFAlJE
The menu-driven interface AEDIT provides makes it
unnecessary to memorize long lists of commands and their
syntax. Instead, a complete list of the commands or options
available at any point is always displayed at the bottom of
the screen. This makes AEDIT both easy to learn and easy
to use.

FIlLL FLEXIBILITY
In addition to the standard PC terminal support provided
with AEDIT. you are able to configure AEDIT to work with
almost any terminal. This along wit.h user-definable mnrros
and [ull adjustable tabs. margins. and case sensitivity
cambme to make AEDIT one of the most flexible editors
available today.

Alternatively. you c~n design a m~cro using AJ.:DIT's
powerrul IlltllTO languagt> Inl'iudt'(j with the editor is an
extensive lihrary of IIseful macros whirh you may use or
1Tl0oify to meet your individu~1 eOi!.ing needs.

TEXT PROlJESSING
For your documentation neeos. paragrnph filling 1)1'
jllstification simrlifies the chore of document formatting
Automatic carriage return insertion means you can rocus on
the content of what you are tyring instead or how riose you
are to the edge or the screen.

SERJlllJE, SIlPPORT, AND TRAINING
Intel augments its dewlopmt'llt tmls with a full array of
seminars, riaSSt's, and workshops: on-site consulting
servin's: fipld application t'ngilllwmg expertise: telephone
hot-line support: and SOftIHlI'[' anti hardwarl' maintenance
contracts. This full lint' or SPI'I ices will ensure your design
surcess.

SPE£IFI£ATIONS
HOST SYSTEM
AEDIT far PC-DOS has been designed to run on the IBM· PC
Xl IBM PC AT. and compatibles. It has been tested and
evaluated for the PC-DOS 3.0 or greater operating system.

For dirert ini'nrmatlon on Inters Development Tools. or ror
the number of your nearest sales office or distributor. call
800-874-6835 (U.S,). For information or literature on
additional Intel products, call 8()()-548-4725 (U.S. and
Canada).

Versions of AEDIT arc available for the iRMX"-86 and
RMX II Operating System.

ORDERING INI'ORMATION
0861\DINL

AJ<;DIT Source Code Editor Release 2.2 for
PC-DOS with supporting dacumentution

122716
122721

AEDIT-DOS Users Guide

RMX864WSLI.

AEDIT for iRMX-86 Operating System

AEDIT-DOS Pocket Referrnce

R286EDI286EU AEDIT for iRMX II Operating System

2-86

IPAT'" PERFORMANCE ANALYSIS TOOL

REA.L-'I'IItIE SOnWA.RE A.1ULI'SIS FOR THE 8086188,
80186/188, 80286, A.ND 80386
Intel's iPAT'" Performance Analysis Tool enables OEMs developing applications based on the 8086/88,
801861188, 80286, or 80386 microprocessors to analyze real-time software execution in their prototype systems at speeds' up to 20 MHz. Through such analysis, it is possible to speed-tune applications
with real-time data, optimize use of operating systems (such as Intel's iRMX II Real-Time Multitasking
Executive for the 80286 and 80386, and iRMK'" Real-Time Multitasking Kernel for the 80386),
characterize response characteristics. and determine code execution coverage by real·time test suites.
Analysis is performed symbolically. non-intrusively. and in real·time with 100% sampling in the
microprocessor. prototype environment. iPAT supports analysis of OEM-developed software built using
8086, 80286, and 80386 assemblers and compilers supplied by Intel and other vendors.
All iPAT Performance Analysis Tool products are serially linked to DOS computer systems (such as
IBM· PC AT. PC XT. and PS/2· Model 80) to host iPAT control and graphic display software. Several
means of access to the user's prototype microprocessor system are supported. For the 80286 (real and
protected ·mode), a 12.5 MHz iPAT-286 probe can be used with the iPATCORE system. For the 8086/88
(MAX MODE designs only), a 10 MHz iPAT·88 probe can be used with. the iPATCORE system. iPATCORE
systems also can be connected to sockets provided on the ICE"'-286 and ICE-186 in-circuit emulators,
or interfaced to PICE'" in-circuit emulators with probes supporting the 8086/88, 801861188, or 80286.
The 20 MHz iPAT"'·386'" probe, also supported by the common iPATCORE system, can be operated
either in "piggyback" fashion connected to an Intel ICE in·circuit emulator for the InteI386"', or directly
connected to a prototype system independent of an ICE. iPAT·386 supports all models of 80386
applications anywhere in the lowest 16 Megabytes of the 80386 linear address space.

IPA.'I' FEA.'I'IJRES
• Up to 20 MHz real-time analysis
• Histograms and analysis tables
• Performance profiles of up to 125 partitions

•
..
•
•

Code execution coverage over up to 252K
Hardware or software interrupt analysis
Simple use with function keys and graphics
Use with or without Intel ICEs

imJ-------------------Intel Corporalton assumes no responSIt-llilY ror the use of '''; .11"
_tll"'j " ... II'~ 1'10"\ "'II~I\ l'IL!OIi~IN11 ~1.,,,,tH all"II'i lOll III, ''"'' ,k' In's II"m Ii~ d ;lIld I~ '1Ihl'" I I" , II,UII:'- 11111\",,1 11,,11""
~·pll'l\ll.·1

2-91

1!llIIi

FEATURES

FIlU I.A.N61lA.6E SlJrPOllI' FOR
IRItIX~-BA.SED SI'SI'EItIS
Intel has all the software languages and tools you will need
to develop a wide range of high·performance applications
using the 80861186. 80881188. 80286. and 386 processors.
iRMX lanRuage compilers run on an Intel 300 series
microcomputer or System 120. and can be used for
MULTIBUSIIlI or " target systems or embedded
applications. Software tools arc also available for 8051ramlly applications.
.
IR\lX languages include C. PUM. FORTRA!'<. Pascal. and
Assembler. Application code can be easily transported
across pmce8S0r architectures to yield increased
performance. For example. 8086 object code will run on the
80286 and 386 processors. and 80286 code will run on the
386 processor. ~'aster execution results from increased .
processor pipellnlng and higher clock rates.
In addition to the wealth of languages available. iR\lX·based
systems are complemented by utilities with which to create
and manage object modules. For the iRMX " system ..
utilities are provided that allow system programmers to
initialilR and manage the memory protection features of the
80280/386 transparently to the applications programmer.
This latitude in configurability allows programmers to team
their efforts in order to achieve a shorter development time
than would otherwise be possible.
.
Because the high-level languages are actually resident on
the iRMX-based system. OEMs can pass applicat.ion
software directly on to end users. End users may then tailor
tht' OIo:M's system to better meet application needs by
writing programs using the same languages.

UN61JA6E-INDErENDENI'
A.rrUCllI'ION DEJlEUlrltlENI'

IRMX oprratillg system calls are made directly from C.
~·()K·I·KA~. Pascal and PIM. This means that application
developers can take full advantage of the iRMX multi-tasking
capability. wherehy multiple applications execute
concurrently on tilt' operating system. Multi-tasking. a
I't'{lulrem~nt of most real·time systems. Is as necessary In
application softW'dre development as .In an operating system
environment.

SI'A.NIMRDIZED 1tIA.1'1I SllrrtJll'l'
All the iRMX languages support floating point operations.
This ensurt'S universal consistency in numeric computation
results and enables the user to take advantage of the Intel
8087.80287. and 80387 NumeriC Data Prore&'IDJ'S.

COMPUI'ESEI' 01' PIlOGRA.1tI
UNMA.6E A.ND SI'SI'EItI BIlIYIN6
IlI'IUI'IES
Utilities for iKMX I operating systems include Inters LINK
86. LOCATio: 86 and LIBRAKIAN. ~'ur IRMX II systems. BND
286 and HI./) 286'replace I.I'lK and I.OCATR.
l:slng the LINK 86 or BND 286 programs. I1sers may
combln!' Individually complll~t ohJect modules to Corm a
single. relll(~atable objl'ct mlxlulr.. This pmvldes the ability to
merge work from slweral Ilnlgrammers into one cohesive
application system ..

The LOCATE 86 utility maps rt~locatable object code InW the
pmressor memory st'{lments. allowing user definition of
modult'/memory type allocation. For example:often·used
portions of an application may he mapped to (P)ROM.
The RI.D 286 utility pmvides the major capabilities of
LOCATE 86 plus allows the system prtlllrammer to specify
thl:' memory prtltl'ction scheml:' for the 80286 system.

Inters Universal Development Interface (UOI) and Object
\lodule Format (OMF) enable several users to write different
modules of an application. in different languages. then link
them together.

The LIRRARIAI\ object cude library manager affords easy
creation. collection and maintenance of related object code
Wreducl' thl' owrhead ·of Sl~parately maintained modules.

Tht' OMF provides users with the ability to mix languages
on a single application system. affording the luxury of
chOOSing rxactly the right language tools for specific pieces
of the application. rather than compromising specialized
tasks for the sake of one. project-wide language.

11011111. 1102116. and 8116 processors generate t',xtremely
efficient code and invoke 808618087 or 802861386 machine

Finally. the MACKO Assemblers for the 8086. 80186. 8088.
Instructions.

I'A.Sr, UA.N PIlOGRAItIS FOR RA.PlD
PIlfI£ESSIN6
The IRMX language products enable programmers W writ\!
the smallest. fastest programs available in high-level
languages. due to tht' compiler's superior ability to optimize
code.

2-92

FEt\TURES
The popular programming language C is fully supported on
iRMX-based systems. iRMX C offers both small and large
se{lml'ntation models. enabling applications to be written
effjcientl~: The iRMX C compilers combine assembly
language efficiency with high-level language convenience; it
can manipulate on a machine-address level while
maintaining the power and speed of a structured language.

iRMX AEDIT Text Editor allows the simultaneous edit of two
files. This allows easy transferral of text between files and
usc of existing material in the creation or new files. Creating
macros. strings of frequently-used commands. is also very
~illlple. The editor "remembers" the selected commands and
allows the user to re-use them repeatedly_ The iRMX II
version also supports operating system level command
execution.

The iRMX Ccompilers afford eaRY portability of existing C
programs tu iRMX-based systems.

IR!fIX@ " son-SCOrE" HIGH Ul'E"
"A.NGIlIIGE DEBIlGGER

IR!fIX@ C c01Ur."ER

IR!fIX@ rU!fI
PUM offers full access to micro-computer architecture while
simultaneuusly offering alilhe henefits or a high-level
language. Invented by Intel in 1976. PUM 80 was the first
microcomputer-specific. block-st~uctured. high-Ievellangllage
availahle. Since lhell. thousands of users have generated
code for millions uf microcumputer-based systems using
PUM 80_ PUM 86. and PUM 286.
PUM 86 software written for 8086 processurs are e.asily
ported to PUM 286 for more pO\\crful applications un the
80286 and 386 processors.

lR!fIX@> I'ORTRIIN
The iR~IX F'ORTRAN compiler provides total compatibility
with FORTRAN 66 language standards. plus most features
provided by the FORTRAN 77 language standard including
complex numbers. iRMX FORTRAN includes extensions
specifically for microcomputer application development.
Programming is simplified by relocatable object libraries.
which provide run-time support for execution time activities_
iRMX rDRTRAN 86 supports the 8087 math coprocessur
and iRMX FORTRAN 286 supports the 80287 for the most
powerful microcomputer solutions availahle in numberintensive applications.

IR!fIX@> rllscII"
iRMX Pascal meets the ISO language standard and
implements several microcomputer extensions. A cumpiletime uption rhecks conformance to the standard. making it
easy to write uniform code. Industry-standard specifications
contribute to portability of application programs and
provide greater reliability.
Pascal supports extensions. such as an interrupt-handler
and direct port I/O extension. that allow programs to be
written specifically for microcomputers. Separate module
compilation allows linkage of Pascal modoles with modules
written in other high-level languages.

B051 "IINGIlIIGES
For target applications using an 8051 family microcontrollcr.
Intel offers the PUM 51 compiler and the ASM 51 Macro
Assemhler and Utilities. Both languages are for use on
iRMX I-based development system.

lR!fIX@ IIEDIT TEXT EDITOR
The iRMX AEDIT Tt'xt Editor is screen-oriented_ menu-driven
and easy to learn. Guided by the menu of commands at the
bottom of the screen_ thr user can edit text and programs
easily and efficiently_

The Soft-Scope II debugger allows users to debug programs
running on the iRMX II Operating System_ Programs written
in PUM 286. fi'ORTRAN 286. Pascal 286. andC 286 can he
detJUgged using source r.ode listings.

REIIL-Tl!flE SOnWIIRE IINII"I'SIS I'OR
THE BOB6IBB, BOIB61IBB, " B02B6
Intel's IPAT Performance Analysis Tool enables OEMs
developing applications based on the 8086/88. 80186/188.
or 80286 microprocessors to analyze real-time software
execution in their prototype systems at speeds up to. 12.5
·MHz. Through such analysis. it is possible to speed-tune
applications. optimize use of operating systems (such as
Intel's iRMXCI> II Real-Time Multitasking Executive).
characterize response. and determine r.ode execution
coverage by test suites. Analysis is performed symholically.
non-int.rusively. and in real-time with 100% sampling in the
microprocessor prototype environment.
..

IR!fIX@ SOIlRCE CONTROl. SI'SfE!fI
The iRMX Source Control System (SCS) provides an
integrated version r.ontrol and generation management
system for user's in an iRMX software development cycle.
This facility is useful for large and small software projects
to assist in bringing more control. order and methodol(l{lY to
the software development process. SCS can be effectively
used on a single iRMX II-based system or across the
Open NE'I"" network.

IR!fIX TOOUlOX
The iRMX Toolbox Is a set of utilities that provide text
formatting. spelling verification. file comparison. and files/·
record/data sorting for program development. The Toolbox
also includes Ii noating point "drsk" c.alculatnr. The iRMX
Toolbox supports 80286 language application development
on an iRMX II host system.

WORWW.DE SllrPORT
With iRMX Languages. you're not alone when developing a
real time application. Intel has the best technical sales
support in the real time business. If you run into a problem.
training. consulting. and design advice Is available through
Intel'S Worldwide customer support organization. To ensure
a successful product life. Support Contracts are available on
an annual basis that include;
• 'I'echnicallnformation Phone Service
• Software Updates
• Troubleshooting Guides
• Monthly ;Comments Magazine
• Response to Software Problem Reports
• Membership to Insite Users' Program Library

2-93

FEATURES
IN'l'El, HAS ro'l'Al, SOl,IJ'l'IONS FOR
REAl.-'l'IIfIE SI'S'l'EIfIS
iRMX I and .iRMX " are the fastest. most powerful operating
systems available for multi-tasking. mUlti-user. real-time
applications. OJmplemented by a wide range of industrystandard languages and utilities. the iRMX-based systems
are highly flexible and configurable.
Application development.for iRMX-based systems ispossible
at the board or the system level. OEMs can integrate
functionality at the most profitable level of prouuct design.
using one system for both development and target use.
Inters choice ofindustry standard high-level languages
enables the end user to extend OEM-provided functionality
even further. if desired.

Who is vettcr qualified to writc and supply software for Intel
VLSI than Intel? l))day yuu have the abilitY to tap into
hundreds of available application software packages.
languages and utilities. peripherals and controllers and
MULTI BUS'" boards.
Intel also has a briJad range of hardware products.
including MUL:rJBUS I and II boards and systems. and the
System 120. a low-cost system for both software
ueveluplllent and realtime target applications.
Tomorrow. and ten year~ down t.he road. you will be ahle to
tap into the lale~t high-performance VLSI-without lOSing
touay's soft\Var~' investment.

SPECIFICATIONS
RE(JIJIIlED HARDWARE
• Any 8086/286/386-based or iSBC 86/286/386-based
system includinglntef"s System 300 series
microcomputer family (lI'the System 120.
Nute: 8086 object code will run on 80286 and 386
processors and 80286 object code will also run on
the 386 prucessur. In buth cases. the cumpiler'S
only support 8086/80286 instruction sets.
registers and functiuns.
• 700l\B of memory
• Two iRMX compatible floppy disks or one hard disk
• One 5.25' duuble·density floppy disk drive fur
distributiun software

Purchase of any IRMX-resiuent language requires Signing of
Inters Software License Agreement (SLA).

DA'l'A SHEETS
• BOB() Compilt'rs:
801l6/flfl/lfl6/1flfl Software Packages
(Intel order number 210689)
• 80286 Compilers:
80286 Software Development Tools
(intt'l order number 231(65)
• 8051 Software:
8051 Software Packages
(Intel orde!' numbel' 162771-004)

• System console device

RE(JIJIRED SOF'l'WARE
The iRMX I (iRMX 86) Operating System Release 7 or later.
including the Nucleus. Basic 110 System. Extended 1/0
System and Human Interfare layers.
~ur-

The iRMX " (iRMX 286) Operating System Release 2 or
later. including the Nucleus. Basic 1/0 System.Extended 1/0
System and Human Interface.

2-94

IRMX@ SOURCE CONTROL SYSTEM

.pP

I"I

IRMX'
SYSTEM
320

'RMX'
SYSTEM

1", i -~

32Q,R

==""

- n ..y

......

iAMX'
SYSTEM

• :120

IRM~ SOIJRCE CON'l'ROL St'S'l'EM
The iRMX Source Control System (SCS) provides an integrated verSiOn control and generation
management system for users in an iRMX software development cycle, This facility is useful for large
and small software projects to assist in bringing more control, order and methodology tu the
software development process, SCS can be effectively used on a single iKMX ~ystclll or aCfOSS the
OpenNET'" network.

l'EiI'l'lJRI;S
•
•
•
•
•

Controls access to source files
Tracks changes to source files
Approachable and efficient
Generates any version of project
Supports range of iRMX languages

_________________________

Inlt'l Cllrporatlon a."sum('~ no rr~ponSlhllll) lor thr II~ IJf any CIr(uilr~' uther than circuitry ~mbudll\l In t'd('~ prr\Ulu..~ly puhlishrr1 spri'llirallilos lin th('s!' rJnln'~ lrum tntt! and IS suhWd III fhiHlh~' II.lthouIIlO!Il"l'

[Inuher. lYli7

Ilrdt'r I\umhl'r :m{l7JU 001

2-95

FEATURES
CONTROLS tlCCESS TO SOIJRCE I1US
\\·ith iR\I.\ Source [,olltrol System the sy stem manag('r
(projecllrader) has certain prinleged commands, Th!'s!'
commands can be useful to designate tho,;,.' t('alll 1I11'rnh('r8
II hI) can accrss the soU!'('t' mes only for ohject gt'nl'r~tion
and those Ilho cail access the source files fill' updating or
changing. Other such pril ilt'ged ('olllmanus incliule tht'
ability to archil(, a specific iersion of source anc! cOlllhifl('
sel'eral I'ersions of a snu!'('e fill',

TRtlCIlS CHtlNGES TO SOIJRCE FILES
The iR\I\ Sour(,e Cuntrol Slstelll kpl'ps tmr~ of changes
made to any source files, These changes are stored as
backwarcl deltas for disk l'Conoml and fast acc('ss to the
liIt('l;t wrsion, The pmjrrt tealll can nUll hetter interact ami
sy nrhronize using the latest updated Il'rsion for integration
and testing, esperialll as projects grt)11 increasingly
c{Jmpl('\. The sperific Il'rsions of tools tiSI'd to producl' the
source code is also tracked,

tlPPROtlCHtlBU tlND EFFICIENT
Tht' iR\I\ Sou!'('r Control Slstt'lll Iws st'lt'ral facililit'S tliat
hrlp make it IPry approarliahle by the user. Tht' tutorial
leads the first time SCS user through thl' structure and
capahilities of the iR\I\ Sourct' ClIntrol Slstt'lli. Tht' mt'/lIl
interface helps eren thl' t'\IWrienCed SCS ust'r it'm'n and
take adl'anlage of the ptJllerful capahilities of ses, .'\n on·
line hdp farility assists in qui('~ rpmindt'I'S for using thl'
referenced commands.

The iR MX Source Control SystelTl makes efficient use of the
system s\orag!' !Irt'a .and the development engillt'er's time.
The iRMX SOllrn' Control System can be used on a single
iRMX Systt'm 01' can ht' IItiliZl'd hy a networketf/distl'ihult'fl
development team,

GENERtlTES tlNY J'ERSION OF
PROJECT
The iRMX Sourer Control System can hl' of particular uSt' to
iJoth new active drvrlopment projects as well as the evolving
enhanrement ilnti maintenance of previous product releases,
8eS provides for generation of any version of a project so
t.hat users can SIiPPOI't (or test) different releases of a
project from one source datil base, VerSions can be tagged
for retrieval with symbolic names. stilte attributt'S or
programmer name, Parallt'l development paths can be mOI'e
easily and automatically merged using SCS,

SIJPPORTS RtlNGE OF IRIUX
LtlNGlJtlGES
The iRMX Source Control System can be utilized by
developers using any of thl' popular iRMX languagesPUM, Asst'mbler. FURTRAN, 'C: PASCAl.. The user can also
confiEUl'l' support other speciallangunge rt'quirt'ments,

SPEtIFItATIONS
PREREt)IJISITE HtlRDWtlRE
iR\I\ System 320 with at least 2\1B .. random acc('ss
memory, I~O"B Ilinche$tt'r disk. anti tapt' dl'ill',

PREREt)IJISITE SOF'I'WtlIlE
il<\I.\ 286 R2.0 and ,\EOIT fol' singlt' nodt' sY$tPIll acct'ss.
The abol'e softllart> pmequisite and iR\I\~ET 1<2,D art'
rt'quired for 11t'lllI.lI'keciutilizatioll.
.
.

ORDER CODE
RMNSCSSl

2-96

iRMX~

TOOI.BOX

The iRMX toolbox is a set of utilities to provide assistance to the software developer in the
housekeeping aspects of program development. These utilities offer facilities for text processing and
document preparation.
Sort facilities and a desk calculator are also included.

FEATlJRES:
•
•
•
•
•
•

Text formatting
Spelling verification
File comparisons
Sort
Floating point desk calculator
Pocket reference guide

inter---------IIUI Corporation assumes no responSibillt~ for the use or any clrc.utry other than circuitry embodied In an Intel product.. No other circuit pa~nt llcenses are
implied. Inlonnatioo oontaii"lld herein supersedes pm'iOUSly published spe(lricatloo8 on tl'lese cie'o'ices from Irtel and Is sublect to change wltllom notice.

Oclober, 1987
C InId Corporauon 1988

Order Number: 280731.()()1

2-97

FEATURES
TEXT FORM.tTTIN.,G (SCRIPT)

SORT (ESORT, HSORT)

. Files ran be sorted on multiple keys (or fields) in ascending
The SCRIPT utility is a text formatting program that
or descending order and the resultant sorted files stored.
streamlines document formatting and preparation.
Commands include facilities tn do paging. ct'ntering. left and
Another ut.ility can be invoked to sort records or data in
right margins. justification. subscripts. superscripts. page
headers and footers. underlines. boldface type. uppt'r and
:\SCII lexical order.
lower case. etc.
. Input te.\t which has been prepared using the .\EDIT utilit~
can be formatted using tht' SCRIPT utilit~ and tht' output
directed to a printt'r or stored on disk for future
manipulation . .\ short tutorial e.\ample is prul'ided to hl'lp
the first timt' user of this formatter.

SPElLING J'ERIFlC.tTION
(SPElL, WSORT)
The SPELL utility finds misspelled Ilords in a tt'xt filt'. Tht'
included dictionary can ht' t'xpandrd by the user for any
addi! ions as wt'li as specialized I'ocailularirs. This utility can
be used interactively or in a batch mode..\nother utilil.~
(\\"SORT) then can bt' used to sort and compress the user
crrated dictionar~.

FW.tTING POINT DES"
CAUlJt.tTOR (DC)

The DC utility accepts lines of text as input. Each line
containing an expression is parsed. evaluated and the result
displayed on the console. Expressions can contain
t'mbedded assignment statements and single letter
lariables.

POC"ET REFERENCE "IJIDE
In addition to the User's Guide pmvided with iRMX Toolbox.
a reference guide in small pocket[ormat provides a handy
reference to commands and functions.

FlU COMP.tRISONS (COMP)
Tht' CO\fP lltilit~ performs lint' oriented te\t flit'
comparisons showing changt's betlll't'n tt'\t or source filt's.
This utility can also compare obirrt files.

SPE~IFI~ATIONS

OPER.tTING ENJ'IRONMENT
iR\I\ 286 Operating System Release 2.0 (If' Im!'r running on
an Intel Series 300 S~ste/1l OJ' equilall'nt hardllan'lIith
\umprir Data Processor (\DP) support and at least I ~IB of
memory. The .\EDIT utility is rt'lluired for use of tbt' SCRIPT
t~xt formatting program.

DOCIJMENT.tTION
.-\n iR\f\ 286 Toolbox l'ser's Guide ami Pocket Rdel'l'nct'
Guide art' shipped Ilith thr product.

ORDERING INFORM.tTION
Product Code: R\f.\286TLB
The product is shipped on a :i If.' iR\I\ formatted floppy
diskette.

2-98

iRMX@ X.25 COMMUNICATIONS SOFTWARE

",-

,~;"

~("
1.'...\
\""". A'.'.'

'~(

~»q>/

iRMX'

SYSTff~

PACKET
SWrrCHED
NETWORK

II.

iRMX' SYSTEM 320

lRItI~ X.:l5 COMMlJNICA1'IONS SOFTWARE
The iRMX X.25 C.ommunications Software provides routines til connect. an iRMX Sysrem 320 to a
Packet. SWitch "letwork (PSN), The IRMX X.25 software allows connections of similar as well as
dissimilar r,omputer types that support Ute CCITT X.25 WHOII fJ84 recommendation.
The iRMX X.25 software has been designed to allow tile programmer the greatest l'Iexibilily ill
accessing packet-switch networks. In order to achieve this fum:tionality_ till' progl'ammer has access
to a full-function programmatic interface. The design of i~\>IX X.2~ allows not only host computer
access as a Data Terminal Equipment (DTE) device. but in addition as a Data Circuit-terminating
Equipment (DCE) device. The DCE configuration makes possible the programming of a complete
packet-switch network service.

SOFTWARE FEA'I'lJRES
•
•
•
•

Application interface library
Interactive utility package
Conforms to CCITT X.25 1980
User Selectable X.25 variants

• LiseI' Configurable
-Four physical links supported
-Softwarr configurahlt' Raud Rates
-C,onfigurahle as Iln:/IlC~;
-255 Configurable Virtual Circuits
(Permanent or Switched)

imJ------------------Inl('1 tilrpurlliion ils:mml'S n" Tt'SptlnSlhllil) fllr Ihr USc' "f lIn~ nrrUllr~ ',ll1l'r [han rlrnlllr~' "nllllMl~llln nn Inl\'[llrlxllM'I. NIII~hcT ('LffUlt pall'nl lin'n~l's art'
Implird, Inlurmallun conlained hrrl~n slJ[X"fscdrs pTt'\illlJsl~ puhli.,>hl'd spt'Cifir.1tlUns (mlh..-.",' dl'\I(\'S rml'll Intd ,lOti is SUhjl'fl til dl 0 OPTION 1
33011

1kll
1kll

+5~--------<>OOPTION

ORDERING INFORMATION

280217-3

Part Number .Description

iSBC80/10B

3-7

Single Board Computer

iSBC® 80/24A
SINGLE BOARD COMPUTER
Compatible Replacement for
• Upward
iSBC 80/20-4 Single Board Computer
CPU Operating at 4.8 or 2.4
• 8085A-2
MHz
iSBXTM Bus Connectors for iSBX
• Two
MULTIMODULETM Board Expansion
8K Bytes of Static Read/Write Memory
• Sockets
for Up to 32K Bytes of Read
• Only Memory
48 Programmable Parallel I/O Lines
• with
Sockets for Interchangeable Line
Drivers and Terminators

•

Programmable Synchronous/
Asynchronous RS232C Compatible
Serial Interface with Software
Selectable Baud Rates

•
•
•
•

Full MULTIBUS® Control Logic for
Multimaster Configurations and System
Expansion
Two Programmable 16-Bit BCD or
Binary Timers/Event Counters
12 Levels of Programmable Interrupt
Control
Auxiliary Power Bus, Memory Protect,
and Power-Fail Interrupt Control Logic
Provided for Battery Backup RAM
Requirements

The Inte180/24A Single Board Computer is a member of Intel's complete line of OEM microcomputer systems
which take full advantage of Intel's LSI technology to provide economical, self-contained computer-based
solutions for OEM applications. The iSBC 80/24A board is a complete computer system on a single 6.7 x
12.00-inch printed circuit card. The CPU, system clock, iSBX bus interface, read/write memory, read only
memory sockets, I/O ports and drivers, serial communications interface, priority interrupt logic, and programmable timers all reside on the board. Full MULTIBUS interface logic is included to offer compatibility with the
Intel OEM Microcomputer Systems family of Single Board Computers, expansion memory options, digital and
analog I/O expansion boards, and peripheral and communications controllers.

142927-1

3-8

September 1988
Order Number: 142927-004

iSBC® 80/24A SINGLE BOARD COMPUTER

ity of a spectrum of functions for greater application
potential. iSBX boards are available to· provide expansion equivalent to the I/O available on the iSBC
80/24A board or the user may configure entirely
new functionality, such as math, directly on board.

FUNCTIONAL DESCRIPTION
Central Processing Unit
Intel's powerful 8-bit N-channel 8085A-2 CPU fabricated on a single LSI chip, is the central processor
for the iSBC 80/24A board operating at either 4.8 or
2.4 MHz Gumper selectable). The 8085A-2. CPU is
directly software compatible with the Intel 8080A
CPU. The 8085A-2 contains six 8-bit general purpose registers and an accumulator. The six general
purpose registers may be addressed individually or
in pairs, providing single and double precision operators. Minimum instruction execution time is 826
nanoseconds. A block diagram of the iSBC 80/24A
functional components is shown in Figure 1.

The iSBX 350 Parallel I/O MULTIMODULE board
provides 24 I/O lines using an 8255A Programmable
Peripheral Interface. Therefore two iSBX 350 modules together with the iSBC 80/24A board may offer
96 lines of programmable I/O. Alternately, a serial
port may be added using the iSBX .351 Serial I/O
MULTIMODULE board.

Memory Addressing
The 8085A-2 has a 16-bit program counter which
allows direct addressing of up to 64K bytes of memory. An external stack, located within any portion of
read/write memory, may be used as a last-in/firstout storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing of this external stack. This stack provides subroutine nesting bounded only by memory
size.

MULTIMODULETM Board Expansion
The iSBX bus interface brings designers incremental
on-board expansion at minimal cost. Two iSBX bus
MULTIMODULE connectors are provided for plug-in
expansion of any iSBX MULTIMODULE board. The
iSBX MULTIMODULE concept provides the ability to
adapt quickly to new technology, the economy of
buying only what is needed, and the ready availabil-

RS232C

USER DESIGNATED
PERIPHERALS

PAOGRAMMABLE
PARALLEL
I/DUNES

COMPATIBLE
DEVICE
SERIAL

DATA

r-'-'-;::''''-, INTERFACE

POWEAFAIL
INTERRUPT

MUL TIBUS. SYSTEM BUS

142927-2

Figure 1. iSBC® 80/24A Single Board Computer Block Diagram

3-9

intJ

iSBC® 80/24A SINGLE BOARD COMPUTER

brought out to two 50-pin edge connectors that mate
with flat, woven, or round cables.

Memory Capacity
The iSBC 80/24A board contains 8K bytes of static
read/write memory using an 8K x 8 SRAMs. All
RAM read and write operations are performed at
maximum processor speed. Power for the on-board
RAM may be provided on an auxiliary power bus,
and memory protect logic is included for RAM battery backup requirements.

Serial 110 Interface
A programmable communications interface using
the Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 80/24A board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. - The USART can be
programmed by the system software to select the
desired asynchronous or synchronous serial data
transmission technique (including IBM Bi-Sync). The
mode of operation (Le. synchronous or asynchronous), data format, control character format, parity,
and baud rate are all under program control. The
8251A provides full duplex, double buffered transmit
and receive capability. Parity; overrun, and framing
error detection are all incorporated in the USART.
The AS232C compatible interface, in conjunction
with the USART, provides a direct interface to
AS232C compatible terminals, .cassettes, and asynchronous and synchronous modems. The RS232C
command lines serial data lines, and signal ground
line are brought out to a 26-pin edge connector that
mates with RS232C compatible flat or round cable.

Four sockets are provided for up to 32K bytes of
nonvolatile read only memory on the iSBC 80/24A
board. EPROM may be added as shown with whiteout and 2732A.
.

Parallel 110 Interface
The iSBC 80/24A board contains 48 programmable
parallel I/O lines implemented using two Intel 8255A
Programmable Peripheral Interfaces. The system
software is used to configure the I/O lines in any
combination of unidirectional input/output and bidirectional ports as indicated in Table 1. Therefore,
the I/O interface may be customized to meet specific peripheral requirements. In order to take full advantage of the large number of possible I/O configurations, sockets are provided for interchangeable
I/O line drivers and terminators. Hence, the flexibility
of the I/O interface is further enhanced by the capability of selecting the appropriate combination of optional line drivers and terminators to provide the required sink current, polarity, and drive/termination
characteristics for eEich application. The 48 programmable I/O lines and signal ground lines are

Multimaster Capability
The iSBC 80/24A board is a full computer on a single board with resources capable of supporting a
large variety of OEM system requirements. For

Table 1 Input/Output Port Modes of Operation
Mode of Operation
Port

Unidirectional

Lines
(qty)

Input
Latched &
Strobed

Unlatched

1
2
3
4
5
6

8
8
4
4
8
8
4
4

X
X
X
X
X
X
X
X

Output

...

X
X

Latched

X
X
X
X
X
X
X
.X

Bidirectional

Control

Latched &
Strobed

X
X

X
X1
X1

X
X

X
X2
X2

NOTES:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.
.
2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a
latched and strobed output port or port 4 is used as a bidirectional port.

3-10

iSBC® 80/24A SINGLE BOARD COMPUTER

those applications requIring additional processing
capacity and the benefits of multiprocessing (Le.
several CPUs and/or controllers logically sharing
system tasks through communication over the system bus), the iSBC 80/24A board provides full MULTIBUS arbitration control logic. This control logic allows up to three iSBC 80/24A boards or other bus
masters to share the system bus in serial (daisy
chain) priority fashion, and up to 16 masters to share
the MULTI BUS system bus with the addition of an
external priority network. The MULTIBUS arbitration
logic operates synchronously with a MULTIBUS
clock (provided by the iSBC 80/24A board or optionally connected directly to the MULTIBUS clock)
while data is transferred via a handshake between
the master and slave modules. This allows different
speed controllers to share resources on the same
bus since transfers via the bus proceed asynchronously. Thus, transfer speed is dependent on transmitting and receiving devices only. This design provides slow master modules from being handicapped
in their attempts to gain control of the bus, but does
not restrict the speed at which faster modules can
transfer data via the same bus. The most obvious
applications for the master-slave capabilities of the
bus are multiprocessor configurations, high speed
direct memory access (DMA) operations, and high
. speed peripheral control, but are by no means limited to these three.

mands are included so that the contents of each
counter can be read "on the fly".
Table 2. Programmable Timer Functions
Operation

Function
Interrupt on
terminal
count

Programmable
one-shot

Rate generator

Square-wave
rate generator

Software
triggered
strobe

Programmable Timers
The iSBC 80/24A board provides three independent, fully programmable 16-bit interval timers/event
counters utilizing the Intel 8254 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller, to the I/O
line drivers associated with the 8255A Programmable Peripheral Interface, or may be routed as inputs
to the 8255A chip. The gate/trigger inputs may be
routed to I/O terminators associated with the 8255A
or as output connections from the 8255A. The third
interval timer in the 8254 provides the programmable baud rate generator for the RS232C USART serial port. In utilizing the iSBC 80/24A board, the systems designer simply configures, via software, each
timer independently to meet system requirements.
Whenever a given time delay or count is needed,
software commands to the programmable timers/
event counters select the desired function. Seven
functions are available, as shown in Table 2. The
contents of each counter may be read at any time
during system operation with simple read operations
for event counting applications, and special com-

Hardware
triggered
strobe
Event counter

When terminal count is
reached, an interrupt request
is generated. This function is
extremely useful for
generation of real-time clocks.
Output goes low upon receipt
of an external trigger edge or
software command and
returns high when terminal
count is reached. This
function is retrlggerable.
Divide by N counter. The
output will go low for one input
clock cycle, and the period
from one low-going pulse to
the next is N times the input
clock period.
Output will remain high until
one-half the count has been
completed, and go low for the
other half of the count.
Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.
Output goes low for one clock
period N counts after rising
edge on counter trigger input.
The counter is retriggerable.
On a jumper selectable basis,
the clock input becomes an
input from the external
system. CPU may read the
number of events occuring
after the counting "window'
has been enabled or an
interrupt may be generated
. after N events occur in the
system.

Interrupt Capability
The iSBC 80/24A board provides vectoring for 12
interrupt levels. Four of these levels are handled directly by the interrupt processing capability of the
8085A-2 CPU and represent the four highest priority
interrupts of the iSBC 80/24A board. Requests are
routed to the 8085A-2 interrupt inputs-TRAP, RST
7.5, RST 6.5, and RST 5.5 (in decreasing order of
priority), each of which generates a call instruction to
3-11

inter

iSBC® 80/24A SINGLE BOARD COMPUTER

a unique address (TRAP: 24H; RST 7.5: 3CH; RST
6.5: 34H; and RST 5.5: 2CH). An 8085A-2 JMP instruction at each of these addresses then provides
linkage to interrupt service routines located independently anywhere in memory. All interrupt inputs with
the exception of the trap interrupt may be masked
via software. The trap interrupt should be used for
conditions such as power-down sequences which
require immediate attention by the 8085A-2 CPU.
The Intel 8259A Programmable Interrupt Controller
(PIC) provides vectoring for the next eight interrupt
levels. As shown in Table 3, a selection of four priority processing modes is available to the systems designer for use in designing request processing configurations to match system requirements. Operating
mode and priority assignments may be reconfigured
dynamically via software at any time during system
operation. The PIC accepts interrupt requests from
the programmable parallel and serial I/O interfaces,
the programmable timers, the system bus, iSBX bus,
or directly from peripheral equipment. The PIC then
determines which of the incoming requests is of the
highest priority, determines whether this request is
of higher priority than the level currently being serviced, and, if appropriate, issues an interrupt to the
CPU. Any combination of interrupt levels may be
masked, via software, by storing a single byte in the
interrupt mask register of the PIC. The PIC generates a unique memory address for each interrupt
level. These addresses are equally spaced at intervals,of 4 or 8 (software selectable) bytes. This 32 or
64-byte block may be located to begin at any 32 or
64-byte boundary in the 65,536-byte memory space.
A Single 8085A-2 JMP instruction at each of these
addresses then provides linkage to locate each interrupt service routine independently anywhere in
memory.

Interrupt Request Generation
Interrupt requests may originiate from 23 sources.
Two jumper selectable interrupt requests can be
generated by each iSBX MULTIMODULE board.,
Two jumper selectable interrupt requests can be automatically generated by each programmable peripheral interface when a byte of information is ready
to be transferred to the CPU (Le., input buffer is full)
or a byte of information has been transferred to a
peripheral device (Le., output buffer is empty). Three
jumper selectable interrupt requests can be automatically generated by the USART when a character
is ready to be transferred to the CPU (Le., receiver
channel buffer is full), a character is ready to be
transmitted (Le., the USART is ready to accept a
character from the CPU), or when the transmitter is
empty (Le., the USART has no character to transmit). A jumper selectable request can be generated
by each of the programmable timers. Nine interrupt
request lines are available to the user for direct interface to user designated peripheral devices via the
MULTIBUS system bus. A power-fail signal can also
be selected as an interrupt source.

Power-Fail Control
A power-fail interrupt may be detected through the
AC-Iow signal generated by the power supply. This
signal may be configured to interrupt the 8085A-2
CPU to initiate an orderly power down instruction sequence.

MULTIBUS® System Expansion
Capabilities

Table 3. Programmable Interrupt Modes
Mode

Operation

Fully nested

Interrupt request line priorities
fixed at 0 as highest, 7 as
lowest.

Autorotating

Equal priority. Each level, after
receiving service, becomes
the lowest priority level until
next interrupt occurs.

Specific
priority

System software assigns
lowest priority level. Priority of
all other levels based in
sequence numerically on this
assignment.

Polled

System software examines
priority-encoded system
interrupt status via interrupt
status register.

Memory and I/O capacity may be expanded and additional functions added using Intel MULTIBUS system compatible expansion boards. Memory may be
expanded to 65,536 bytes by adding user specified
combinations of RAM boards, EPROM boards, or
combination boards. Input/output capacity may be
increased by adding digital I/O and analog I/O expansion boards. Mass storage capability may be
achieved by adding single or double density diskette
or hard disk controllers as subsystems. Expanded
communication needs can be handled by communication controllers. Modular expandable backplanes
and card cages are available to support multi board
'
systems.

3-12

iSBC® 80/24A SINGLE BOARD COMPUTER

SPECIFICATIONS

OFF-BOARD EXPANSION

Word Size

Up to 64K bytes using user specified combinations
of RAM, ROM, and EPROM.

Instruction- 8, 16 or 24 bits
Data

Up to 128K bytes using bank select control via I/O
port and 2 jumper options.

8 bits

May be disabled using PROM ENABLE via I/O port
and jumper option, resulting in off-board RAM overlay capability.

Cycle Time
BASIC INSTRUCTION CYCLE

I/O Addressing

826 ns (4.84 MHz operating frequency)
1.65 f.Ls (2.42 MHz operating frequency)

ON-BOARD PROGRAMMABLE I/O

NOTE:
Basic instruction cycle is defined as the fastest instruction (Le., four clock cycles).

I/O Address

Device

Memory Addressing
ON-BOARD EPROM

.O-OFFF using 2708, 2758 (1 wait state)
0-1 FFF using 2716 (1 wait state)
0-3FFF using 2732 (1 wait state)
using 2732A (no wait states)
0-7FFF using 2764A (no wait states)
ON·BOARD RAM

EOOO-FFFF
NOTE:
Default configuration-may be reconfigured to top
end of any 16K boundary.

Memory Capacity

8255A No.1
PortA
Port B
Port C
Control

E4
E5
E6
E7

8255A No.2
PortA
Port B
PortC
Control

E8
E9
EA
EB

8251A
Data
Control

EC,EE
ED,EF

iSBX MULTIMODULE J5
MCSO
MCS1

CO-C7
C8-CF

iSBX MULTIMOPULE J6
MCSO
MCS1

FO-F7
F8-FF

I/O Capacity

ON-BOARD EPROM

Parallel

32K bytes (sockets only)

1 transmit, 1 receive, 1 SID,
1 SOD
iSBX MULTIMODULE- 2 iSBX MULTIMODULE
Boards
Serial

May be added in 1K (using 2708 or 2758), 2K (using
2716), 4K (using Intel 2732A), or 8K (using Intel
2764A) byte increments.
ON-BOARD RAM

8K bytes

3-13

48 programmable lines

iSBC® 80/24A SINGLE BOARD COMPUTER

Serial Communications Characteristics

Interrupts

Synchronous -

Addresses for 8259A Registers (hex notation, 110
address space)
DA or D8 Interrupt request register
DA or D8 In-service register
DB or D9 Mask register
DA or D8 Command register
DB or D9 Block address register
DA or D8 Status (polling register)

5-8 bit characters; internal or external character synchronization;
automatic sync insertion
Asynchronous- 5-8 bit characters; break character generation; 1, 1%, or 2 stop
bits; false start bit detectors
Baud Rates
Output
Frequency
in kHz
.153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

NOTE:
Several registers have the same physical address;
sequence of access and one data bit of control
word determine which register will respond.

Baud Rate (Hz)
Synchronous

38400
19200
9600
4800
2400
1760

Asynchronous
+16
9600
4800
2400
1200
600
300
150
110

+64
2400
12QO
600
300
150
75

Interrupt levels routed to 8085A-2 CPU automatically
vector the processor to unique memory locations:
Interrupt
Input
TRAP
RST7.5
RST6.5
RST5.5

NOTE:
Frequency selected by 110 write of appropriate 16-bit frequency factor to baud rate register.

Memory
Address
24
3C
34
2c

Priority

Type

Highest

Non-maskable
Maskable
Maskable
Maskable

i
Lowest

Timers
Register Addresses (hex notation, I/O address
space)
DF
Control register
DC
Timer 0
DD
Timer 1
DE
Timer 2

Register Address (hex notation, I/O address
space)
DE Baud rate register
NOTE:
Baud rate factor (16 bits) is loaded as two sequential output operations to same address (DEH).

NOTE:
Timer counts loaded as two sequential output operations to same address as given.

Output Frequencies/Timing Intervals

Function

Single
Timer/Counter
Min

Max

Dual Timer/Counter
(Two Timers
Cascaded)
Min

Max

Real-Time Interrupt
60.948 ms
1.109 hrs
1.86 J.Ls
3.72 fJ-s
Programmable One-Shot
1.109 hrs
1.86 fJ-s 60.948 ms
3.72 fJ-s
Rate Generator
16.407 Hz 537.61 kHz 0.00025 Hz 268.81 kHz
Square-Wave Rate Generator 16.407 Hz 537.61 kHz 0.00025 Hz 268.81 kHz
Software Triggered Strobe
1.109 hrs
1.86 fJ-s 60.948 ms
3.72 fJ-s
Hardware Triggered Strobe
1.109 hrs
1.86 fJ-s 60.948 ms
3.72 fJ-s
. NOTE:
Input frequency to timers is 1.0752 MHz (default configuration).

3-14

iSBC® 80/24A SINGLE BOARD COMPUTER

Input Frequencies
Reference: 1.0752 MHz
nominal)

Memory Protect
± 0.1 %

(0.930 /1s period,

An active-low TTL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of RAM contents during system powerdown sequences.

Event Rate: 1.1 MHz max

Interfaces
MULTIBUS

All signals TTL compatible

Line Drivers and Terminators

iSBX Bus

All signals TTL compatible

Parallel I/O

All signals TTL compatible

Serial I/O

RS232C compatible, configurable as a data set or data terminal

1/0 Driver- The following line drivers and terminators are all compatible with the 1/0 driver sockets on the iSBC 80/24A Board:

Timer

......, All signals TTL compatible

Interrupt Requests- All TTL compatible

System Clock (8085A-2'CPU)
4.84 or 2.42 MHz

± 0.1 %

Gumper selectable)

Driver

Characteristic

Sink Current (rnA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTE:

Auxiliary Power

I = inverting; NI = non-inverting; OC = open collector.

An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of readlwrite memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.

Ports E4 and E8 have 32 mA totem-pole drivers and
1K terminators.
I/Q Terminators- 220fl./330fl. divider of 1 kfl. pullup.

Connectors
Double-Sided
Pins (qty)

Centers
(In.)

MULTIBUS
System Bus

0.156

ELFAB BS1562043PBB
Viking 2KH43/9AMK12 Soldered PCB Mount
EDAC 337086540201
ELFAB BW1562D43PBB
EDAC 337086540202
ELFAB BW1562A43PBB Wire Wrap

Auxiliary Bus

0.1.00

EDAC 345060524802
ELFAB BS1020A30PBB
EDAC 345060540201
ELFAB BW1020D30PBB Wire Wrap

Parallel 1/0 (2)

0.100

3M 3415-001 Flat Crimp
GTE Sylvania 6AD01251A1DD Soldered

Serial 1/0

0.100

AMP 15837151
EDAC 345026520202 PCB Soldered
3M 3462-0001
AMP 88373-5 Flat Crimp

Interface

Mating Connectors'

'NOTE:
Connectors compatible with those listed may also be used.

3-15

inter

iSBC® 80/24A SINGLE BOARD COMPUTER

Bus Drivers
220n/330n OPTION 1

Function

Characteristic

Sink Current (rnA)

Data
Address
Commands

Tri-State
Tri-State
Tri-State

32
32
32

220n

+5V-----,--------,;=-~__4__0

Physical Characteristics

+5V--------.NV'---------

lknOPTION2

Width: 12.00 in. (30.48 em)
Height: 6.75 in. (17.15 em)

lkn

142927-3

Depth:

0.50 in. (1.27 em)

Weight: 12.64 oz. (354 gm)

Electrical Characteristics
DC POWER REQUIREMENTS

Current Requirements
Configuration

Vee = +5V
±5% (max)

Vee = +12V
±5% (max)

Vee = -5V
±5% (max)

VAA = -12V
±5% (max)

Without
EPROM(1)

2.66A

·40mA

20mA

RAM Only(2)

0.01A

With
iSBC 530(3)

2.66A

140mA

With4K
EPROM(4)
(using 2708)

3.28A

300mA

With4K
EPROM(4)
(using 2758)

3.44A

40mA

20mA

With 8K
EPROM(4)
(using 2716)

3.44A

40mA

20mA

With 16K
EPROM(4)
(using 2732A)

3.46A

40mA

20mA

With 32K
EPROM(4)
(using 2764A)

3.42A

40mA

20mA

180mA

120mA

20mA

NOTES:

1. Does not include power for optional EPROM, I/O drivers, and I/O terminators.
2. RAM chips powered via auxiliary power bus.
3. Does not include power for optional EPROM, I/O drivers, I/O terminators. Power for iSBC 530
Adapter is supplied via serial port connector..
4. Includes power required for four EPROM chips, and I/O terminators installed for 16 I/O lines; all
terminators inputs low.

3-16

intJ

iSBC® 80/24A SINGLE BOARD COMPUTER

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051. .

Environmental Characteristics
Operating Temperature: O°C to 55°C

Reference Manual

ORDERING INFORMATION

148437-001- iSBC 80/24A Single Board Computer
Hardware Reference Manual (NOT
SUPPLIED)

Part Number Description
SBC 80/24A Single Board Computer

3-17

iSBC® 80/30
. SINGLE BOARD COMPUTER

•
•
•
•
•

•

Programmable ·Synchronous/
• Asynchronous
RS232C Compatible

8085A CPU Used as Central Processing
Unit
16K Bytes of Dual Port Dynamic Read/
Write Memory with On-Board Refresh
Sockets for up to 8K Bytes of Read
Only Memory
Sockets for 8041A/8741A Universal
Peripheral Interface and
Interchangeable Line Drivers and Line
Terminators
24 Programmable Parallel I/O Lines
with Sockets for Interchangeable Line
Drivers and Terminators
Full MULTIBUS® Control Logic Allowing
up to 16 Masters to Share the System

•
•
•

•

Serial Interface with Fully Software
Selectable Baud Rate Generation
12 Levels of Programmable Interrupt
Control
Two Programmable 16-Bit BCD or
Binary Counters
Auxiliary Power Bus, Memory Protect,
and Power-Fail Interrupt Control Logic
for RAM Battery Backup
Compatible with Optional iSBC® 80
CPU, Memory, and I/O Expansion
Boards

The iSBC 80/30 Single Board Computer is a member of Intel's complete line of OEM computer systems which
take full advantage of Intel's LSI technology to provide economical self-contained computer-based solutions
for OEM applications. The iSBC 80/30 is a complete computer system on a single 6.75 x 12.00-inch printed
circuit card. The CPU, system clock, read/write memory, nonvolatile read only memory, universal peripheral
interface capability, I/O ports and drivers, serial communications interface, priority interrupt logic, programmable timers, MULTIBUS control logic, and bus expansion drivers all reside on the board.

280219-1

3-18

September 1988
Order Number: 280219-002

iSBC® 80/30 SINGLE BOARD COMPUTER

to 64K-address space. The iSSC 80/30 provides extended addressing jumpers to allow the on-board
RAM to reside within a one megabyte address
space when accessed via the MULTIBUS. In addition, jumper options are provided which allow the
user to reserve 8K- and 16K-byte segments of onboard RAM for use by the 808SA CPU only. This
reserved RAM space is not accessible via the MULTIBUS and does not occupy any system address
space.

FUNCTIONAL DESCRIPTION
Central Processing Unit
Intel's powerful 8-bit n-channel 8085A CPU, fabricated on a single LSI chip, is the central processor for
the iSBC 80/30. The 808SA CPU is directly software
compatible with the Intel 8080A CPU. The 8085A
contains six 8-bit general purpose registers and an
accumulator. The six general purpose registers may
be addressed individually or in pairs,providing both
single and double precision operators. The minimum
instruction execution time is 1.45 microseconds. The
8085A CPU has a 16-bit program counter. An external stack, located within any portion of iSBC 80/30
read/write memory, may be used as a last-in/firstout storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing of this eternal stack. This stack provides subroutine nesting' bounded only by memory
size.

EPROM/ROM Capacity
Sockets for up to 8K bytes of nonvolatile read only
memory and provided on the iSSC 80/30 board.
Read only memory may be added in 1 K-byte increments up to a maximum of 2 K-bytes using Intel
2708 or 2758 erasable and electrically reprogrammabie ROMs (EPROMs); in 2 K-byte increments up
to a maximum of 4 K-bytes using Intel 2716
EPROMs; or in 4 K-byte increments up to 8K-bytes
maximum using Intei 2732 EPROMs. All on-board
EPROM/ROM operations are performed at maximum processor speed.

Bus Structure

Parallel I/O Interface

The iSBC 80/30 has an internal bus for all on-board
memory and I/O operations and a system bus (I.e.,
the MULTISUS) for all external memory and I/O operations. Hence, local (on-board) operations do not
tie up the system bus, and allow true parallel processing when several bus masters (I.e., DMA devices, other single board computers) are used in a multimaster scheme. A block diagram of the iSBC
80/30 functional components is shown in. Figure 1.

The iSSC 80/30 contains 24 programmable parallel
I/O lines implemented using the Intel 8255A Programmable Peripharal Interface. The system software is used to configure the I/O lines in any combination of unidirectional input/output and bidirectional ports indicated in Table 1. Therefore, the I/O interface may be customized to meet specific peripheral requirements. In order to take full advantage of
the large number of possible I/O configurations,
sockets are provided for interchangeable I/O line
drivers and terminators. Hence, the flexibility of the
I/O interface is further enhanced by the capability of
selecting the appropriate combination of optional
line drivers and terminators to provide the required,
sink current, polarity, and drive/termination characteristics for each application. The 24 progr~mmable
I/O lines and signal ground lines are brought out to a
50-pin edge connector that mates with flat, woven,
or round cable.

RAM Capacity
The iSBC 80/30 contains 16K bytes of dynamic
read/write memory using Intel 2117 RAMs. All RAM
read and write operations are performed at maximum processor speed. Power for the on-board RAM
may be provided on an auxiliary power bus, and
memory protect logic is included for RAM battery
backup requirements. The iSBC 80/30 contains a
dual port controller, which provides dual port capability for the on-board RAM memory. RAM accesses
may occur from either the iSBC 80/30 or from any
other bus master interfaced via the MULTISUS.
Since on-board RAM accesses do not require the
MULTIBUS, the bus is available for any other concurrent operations (e.g., DMA data transfers) requiring the use of the MULTIBUS. Dynamic RAM refresh
is accomplished automatically by the iSBC 80/30 for
accesses originating from either the CPU or via the
MULTIBUS. Memory space assignment can be selected independently for on-board and MULTIBUS
RAM accesses. The on-board RAM, as seen by the
808SA CPU, may be placed anywhere within the 0-

Universal Peripheral Interface (UPI)
The iSBC 80/30 provides sockets for a user supplied Intel 8041A/8741A Universal Peripheral Interface (UPI) chip and the associated line drivers and
terminators for the UPI's I/O ports. The
8041A18741A is a single chip microcomputer containing a CPU, 1K bytes of ROM (8041 A) or EPROM
(8741 A), 64 bytes of RAM, 18 programmable I/O
lines, and an 8-bit timer. Special interface registers
included in the chip allow the 8041 A to function as a
3-19

SERIAL

RS232C

DATA
INTERFACE

COMPATIILE
DEVICE

USER DESIGNATED
PERIPHERALS
42 PROGRAMMABLE
PARALLEL 110 LINES

"'II

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c

iil
:-"

enID

o@J

POWER FAil
INTERRUPT

4 INTERRUPT
REQUEST LINES

2 INTERRUPT
REQUEST LINES

c»
Q
......
Co)

o
......
CJ.)
o

8 INTERRUPT
REQUEST
LINES

(J)

en
Z
C)

ce
iD
(,)
N oID
o II)

ol>

o
o
3

::D

o
o

TWO
PROGRAM·

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C

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s::

TIMERS

c:
-I
m

0'
(')
~

::D

iii"

iil
3

MUlTiBUS

280219-2

inter

iSBC® 80/30 SINGLE BOARD COMPUTER

of OEM system requirements. For those applications
requiring additional processing capacity and the
benefits of multiprocessing (i.e., several CPUs and/
or controllers logically sharing system tasks through
communication over the system bus), the iSBC
80/30 provides full MULTIBUS arbitration control
logic. This control logic allows up to three iSBC 80/
30's or other bus masters to share the system bus in
serial (daisy chain) priority fashion, and up to 16
masters to share the MULTIBUS with the addition of
an external priority network. The MULTIBUS arbitration logic operates synchronously with a MULTIBUS
clock (provided by the iSBC 80/30 or optionally connected directly to the MULTIBUS clock) while data is
transferred via a handshake between the master
and slave modules. This allows different speed controllers to share resources on the same bus, and
transfer via the bus proceed asynchronously. Thus,
transfer speed is dependent on transmitting and receiving devices only. This design prevents slow
master modules from being handicapped in their attempts to gain control of the bus, but does not restrict the speed at which faster modules can· transfer
data via the same bus. The most obvious applications for the master-slave capabilities of the bus are
multiprocessor configurations, high speed direct
memory access (OMA) operations, and high speed
peripheral control, but are by no means limited to
these three.

slave processor to the iSBC 80/30's 8085A CPU.
The UPI allows the user to specifiy algorithms for
controlling user peripherals directly in the chip,
thereby relieving the 8085A for other system functions. The iSBC 80/30 provides an RS232C driver
and an RS232Creceiver for optional connection to
the 8041A18741A in applications where the UPI is
programmed to handle simple serial interfaces. For
additional information, including 8041A18741A instructions, refer to the UPI-41 A User's Manual and
application note AP-41.

Serial 1/0
A programmable communications interface using
the Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 80/30. A software selectable baud rate
generator provides the USART with all common
communication frequencies. The USART can be
programmed by the system software to select the
desired asynchronous or synchronous serial data
transmission technique (including IBM By-Sync).
The mode of operation (i.e., synchronous or asynchronous), data format, control character format,
parity, and baud rate are all under program control.
The 8251A provides full duplex, double buffered
transmit and receive capability. Parity, overrun, and
framing error detection are all incorporated in the
USART. The RS232C compatible interface on each
board, in conjunction with the USART, provides a
direct interface to RS232C compatible terminals,
cassettes, and asynchronous and synchronous modems. The RS232C command lines, serial data
lines, and signal ground line are brought out to a 26pin edge connector that mates with RS232C compatible flat or round cable.

Programmable Timers
The iSBC 80/30 provides three independent, fully
programmable 16-bit interval timers/event counters
utilizing the Intel 8253 Programmable Interval Timer.
Each counter is capabile of operating in either BCD
or binary modes. Two of these timers/counters are
available to the systems designer to generate accurate time intervals under software control. Routing
for the outputs and gate/trigger inputs of two of
these counters is jumper selectable. The outputs
may be independently routed to the 8259A Program-

Multimaster Capability
The iSBC 80/30 is a full computer on a single board
with resources capable of supporting a great variety

Port

2
3

Lines
(qly)

8
8
4
4

Mode of Operation
Unidirectional
Input
Output
Latched &
Latched &
Latched
Unlatched
Strobed
Strobed
X
X
X
X
X
X
X
X
X
X
X
X

Bidirectional

Control

X
X1
X1

NOTE:
1. Part of port 3 must be used as a control port when either port 1 or port
latched and strobed output port or port 1 is used as a bidirectional port.

3-21

:2 are used as a

latched and strobed input or a

inter

iSBC® 80/30'SINGLE BOARD COMPUTER

contents of each counter may be read at any time
during system operation with simple read operations
for event counting applications, and special commands are included so that the contents of each
counter can be read "on the fly".

mabie Interrupt Controller, to the I/O line drivers associated with the 8255A Programmable Peripheral
Interface, and to the 8041 Al8741 A Universal Programmable Interface, or may be routed as inputs to
the 8255A and 8041A18741A chips. The gate/trigger inputs may be routed to I/O terminators associated with the 8255A or as output connections from
the 8255A. The third interval timer in the 8253 provides the programmable baud rate generator for the
iSBC 80/30 RS232C USART serial port. In utilizing
the iSBC BO/30,the systems designer simply configures, via software, each timer independently to meet
system requirements.

Interrupt Capability
The iSBC 80/30 provides vectoring for 12 interrupt
levels. Four of these levels are handled directly by
the interrupt processing capability of the 8085A CPU
and represent the four highest priority interrupts of
the iSBC BO/30. Requests are routed to the 8085A
interrupt inputs, TRAP, RST 7.5, RST 6.5, and RST
5.5 (in decreasing order of priority) and each input
generates a unique memory address (TRAP: 24H;
RST 7.5: 3CH; RST 6.5: 34H; and RST 5.5: 2CH). An
B085A jump instruction' at each of these addresses
then Jptovides linkage to interrupt service routines
located independently anywhere in memory. All interrupt inputs with the exception of the trap interrupt
may be' masked via software. The trap interrupt
should be used for conditions such as power-doWn
sequences which require immediate attention by the
8085A CPU. The Intel 8259A Programmable Interrupt Controller (PIC) provides vectoring for the next
eight interrupt levels. As shown in Table 3, a selection of four priority processing modes is available to
the systems designer for use in designing request
processing configurations to match system requirements. Operating mode and priority assignments
may be reconfigured dynamically via software at any
time during system operation. The PIC accepts interrupt requests from the programmable parallel and
serial I/O interfaces, the programmable timers, the
system bus, or directly from peripheral equipment.
The PIC then determines which of the incoming requests is of the highest priority, determines whether
this request is of higher priority than the level currently being serviced, and, if appropriate, issues an
interrupt to the CPU. Any combination of interrupt
levels may be masked, via software, by storing a
single byte in the interrupt mask register of the PIC.
The PIC generates a unique memory address for
each interrupt level. These addresses are equally
spaced at intervals of 4 or 8 (software selectable)
bytes. This 32- or 64-byte block may be located to.
begin at any 32- or 64-byte boundary in the 65,536byte memory space. A single BOB5A jump instruction
ateach of these addresses then provides linkage to
locate each interrupt service routine independently
anywhere in memory.

Whenever a given time delay or count is needed,
software commands to the programmable timers/
event counters select the desired function. Seven
functions are available, as shown in Table 2. The
Table 2. Programmable Timer Functions
.

Function

Operation

Interrupt on
Terminal COUl1t

When terminal count is
reached, an interrupt request is
generated. This function is
extremely useful for generation
of real-time clocks.

Programmable
One-Shot

Output goes low upon receipt of
an external trigger edge or
software command and returns
high when terminal count is
reached. This function is
retriggerable.

Rate
Generator

Divide by N counter. The output.
will go low for one input clock
cycle, and the period from one
low-going pulse to the next is N
times the input clock period.

Square-Wave
Rate Generator

Output will remain high until
one-half the count has been
com'pleted, and go low for the
other half of the count.

Software
Triggered
Strobe

Output remains high until
software loads count (N). N
counts after counfis loaded,
output goes low for one input
clock period.

Hardware
Triggered
Strobe

Output goes low for one clock
period N counts after rising
edge on counter trigger input.
The counter is retriggerable.

Event Counter

On a jumper selectable basis,
the clock input becomes an
input from the external system.
CPU may read the number of
events occurring after the
counting "window" has been
enabled or an interrupt may be
generated after N events occur
in the system.

Interrupt Request Generation-Interrupt requests
may originate from 18 sources. Two jumper selectable interrupt requests can be automatically generated by the programmable peripheral interface when

3-22

inter

iSBC® 80/30 SINGLE BOARD COMPUTER

density diskette controllers as sub-systems. Modular
expandable backplanes and cardcages are available
to support multi-board systems.

a byte of information is ready to be transferred to the
CPU (Le., input buffer is full) or a byte of information
has been transferred to a peripheral device (Le., output buffer is empty). Two jumper selectable interrupt
requests can be automatically generated by the
USART when a character is ready to be transferred
to the CPU (Le., receive channel buffer is full), or a

SPECIFICATIONS
Word Size

Table 3. Programmable Interrupt Modes
Mode
Fully
Nested

Operation

Instruction: 8, 16, or 24 bits
Data: 8 bits

Interrupt request line priorities
fixed at 0 as highest, 7 as
lowest.

Autorotating

Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.

Cycle Time

Specific
Priority

System software assigns lowest
priority level. Priority of all other
levels based in sequence
numerically on this assignment.
System software examines
priority-encoded system
interrupt status via interrupt
status register.

NOTE:
Basic instruction cycle is defined as the fastest instruction (i.e., four clock cycles).

Polled

Basic Instruction Cycle: 1.45 IJ-S

Memory Addressing
On-Board ROM/EPROM: 0-07FF (using 2708 or
2758 EPROMs); O-OFFF (using 2716 EPROMs); 01FFF (using 2716 EPROMs; 0-1 FFF (using 2,732
EPROMs).

character is ready to be transmitted (Le., transmit
channel data buffer is empty). A jumper selectable
request can be generated by each of the programmable timers and by the universal peripheral interface, eight additional interrupt request lines are
available to the user for direct interface to user designated peripheral devices via the system bus, and
two interrupt request lines may be jumper routed directly from peripherals via the parallel 110 driver/terminator section.

On-Board RAM: 16K bytes of dual port RAM starting
on a 16K boundary. One or two 8 K-byte segments
may be reserved for CPU use only.

Memory Capacity
On-Board Read Only Memory: 8K bytes (sockets
only)
On-Board RAM: 16K bytes
Off-Board Expansion: Up to 65,536 bytes in user
specified combinations of RAM, ROM, and EPROM

Power-Fail Control
Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow Signal from
the iSBC 635 Power Supply or equivalent.

NOTE:
Read only memory may be added in 1K, 2K, or 4K
byte increments.

Expansion Capabilities
Memory and 1/0 capacity may be expanded and additional functions added by using Intel MULTIBUS
compatible expansion boards. High speed integer
and floating point arithmetic capabilities may be added. Memory may be expanded to' 65,536 bytes by
adding user specified combinations of RAM boards,
EPROM boards, or combination boards. Input/output capacity may be increased by adding digital 1/0
and analog 1/0 expansion boards. Mass storage capability may be achieved by adding single or double

I/O Addressing
On-Board Programmable: 1/0 (see Table 1)
Port

8255A

8041A18741A

1 I 2 I 3 IControl
Address EsIE91EAI

3-23

USART

Data I Control DatalControl
E4 or E61 E5 or E7 EC

iSBC® 80/30 SINGLE BOARD COMPUTER

NOTE:
Several registers have the same physical address;
sequence of access and one data bit of control
word determine which register will respond.

110 Capacity
Parallel: 42 programmable lines using one 8255A
(241/0 lines) and an optiona18041A18?41A (18 I/O
lines)

Interrupt Levels routed to 8085A CPU automatically
vector the processor to unique memory locations:

Serial: 2 programmable lines using one 8251A and
an optional 8041 Al8? 41 A programmed for serial operation

Interrupt
Input

NOTE:
For additional information on the 8041 Al8? 41 A refer to the UPI-41 User's Manual (Publication
9800504).

TRAP
RST?5
RST6.5
RST 5.5

Serial Communications Characteristics

Memory
Address
24
3C
34
2C

Priority

Type

Highest

Non-maskable
Maskable
Maskable
Maskable

J,
Lowest

Timers

Synchronous: 5-8 bit characters; internal or external
character synchronization; automatic sync insertion.

Asynchronous: 5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit detection.

DF Control register
DC Timer 0
DD Timer 1
DE Timer 2

Baud Rates
Frequency (kHz)
(Software
Selectable)

NOTE:
Timer counts loaded as two sequential output operations to same address, as given.

Baud Rate (Hz)
Synchronous

153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

38400
19200
9600
4800
2400
1760

Asynchronous
"'" 16
9600
4800
2400
1200
600
300
150
110

"'" 64
2400
1200
600
300
150
75

Input Frequencies
Reference: 2.46 MHz ± 0.1 % (0.041 J.ts period,
nominal); 1.23 MHz ± 0.1 % (0.81 J.ts period, nominal); or 153.60 kHz ± 0.1 % (6.51 J.ts period nominal).

NOTE:
Above frequencies are user selectable

NOTE:
Frequency selected by I/O write of appropriate 16-bit frequency factor to baud rate register (8253 Timer 2) .

Event Rate: 2.46 MHz max
NOTE:
Maximum rate for external events in event counter
function.

Interrupts
Addresses for 8259A Registers (Hex notation, I/O
address space)

Interfaces

DA Interrupt request register
DA In-service register

MULTIBUS: All signals TIL compatible

DB Mask register

Parallel I/O: All signals TIL compatible

DA Command register

Interrupt Requests: All TTL compatible

DB Block address register

Timer: All signals TIL compatible

DA Status (polling register)

Serial I/O: RS232C compatible, data set
configuration

3-24

iSBC® 80/30 SINGLE BOARD COMPUTER

System Clock (SOSSA CPU)
2.76 MHz ±0.1%

Auxiliary Power
An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of read/write memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.

Bus
Parallel I/O
Serial I/O

Pins Centers
(qty)
(in.)
86
50
26

Characteristics

Sink Current (mA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTE:
I = inverting; NI

Connectors
Interface

Driver

0.156
0.1
0.1

= non-inverting; OC = open collector

Mating Connectors

Port 1 of the 8255A has 20 mA totem-pole bidirectional drivers and 1 kO terminators.

Viking 2KH43/9AMK12
3M 3415-000
3M 3462-000

I/O Terminators: 2200/3300 divider or 1 kO pullup
220!l

OPTION 1

220!l/3::~_r-_-_- -_-_~-'13",~N;",,~!1""~_-_-_

OPTION 2

1 k!l

_ __

Memory Protect
An active-low TTL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of AAM contents during system powerdown sequences.

1"""'-0

- : ---"'
...

1 k!l
+5V ---~·"""fV·,-----'----o

280219-3

Bus Drivers

Line Drivers and Terminators
I/O Drivers: The following line drivers are all compatible with the I/O driver sockets on the iSBC
80/30.

Function

Characteristic

Sink Current (mA)

Data
Address
Commands

Tri-State
Tri-State
Tri-State

50
50
32

Physical Characteristics
Width:
Height:
Depth:
Weight:

12.00 in. (30.48 cm)
6.75 in. (17.15 cm)
0.50 in. (1.27 cm)
18 oz. (509.6 gm)

Output Frequencies/Timing Intervals
Function
Real-Time Interrupt
Programmable One-Shot
Rate Generator
Square-Wave Rate Generator
Software Triggered Strobe
Hardware Triggered Strobe

Single Timer/
Counter

Dual Timer/Counter
(Two Timers Cascaded)

Min

Max

Min

Max

1.63 f-I-s
1.63 f-I-s
2.342 Hz
2.342 Hz
1.63 f-I-s
1.63 f-I-s

427.1 ms
427.1 ms
613.5 kHz
613.5 kHz
427.1 ms
427.1 ms

3.26 f-I-s
3.26 f-I-s
0.000036 Hz
0.000036 Hz
3.26 f-I-s
3.26 f-I-s

466.50 min
466.50 min
306.8 kHz'
306.8 kHz
466.50 min
466.50 min

3-25

intJ

iSBC® 80/30 SINGLE BOARD COMPUTER

Electrical Characteristics
DC POWER REQUIREMENTS
Current Requirements
Configuration
Without EPROM(1)

Vee = +5V
±5% (max)
Icc

= 3.SA

Voo = + 12V
±5% (max)
IDD

220mA

Vee = -5V
±5% (max)
IBB

VAA = -12V
±5% (max)
IAA

SOmA

3.6A

220mA

350mA

20mA

2.SmA

With iSBC 530(4)

3.5A

320mA

150 mA

With 2K EPROM(5)
(using 8708)

4.4A

350mA

95mA

40mA

With 2K EPROM(5)
(using 2758)

4.6A

220mA

50mA

With 4K EPROM(5)
(using 2716)

4.6A

220mA

50mA

With 8K EPROM(5)
(using 2332)

4.6A

220mA

50mA

With 8041/8741(2)
RAM only(3)

SOmA

NOTES:
1. Does not include power required for optional EPROM/ROM, 8041A18741A 110 drivers, and 110 terminators.
2. Does not include power required for optional EPROM/ROM. 110 drivers and 110 terminators.
3. RAM chips powered via auxiliary power bus.
4.Does not include power required for optional EPROM/ROM, 8041A18741A 110 drivers, and 110 terminators. Power for
iSBC 530 is supplied through the serial port connector.
5. Includes power reqiured for two EPROM/ROM chips, 8041A18741A and 2200/3300 input terminators installed for 34
110 lines; all terminator inputs low.
.

Reference manuals are shipped with each product
only if designated SUPPLIED. Manuals may be ordered from any Intel sales representative, distributor
office or from Intel Literature Department, 3065
Bowers Avenue, Santa Clara, California 95051.

Environmental Characteristics
Operating Temperature:O°C to 55°C

Reference Manual
ORDERING INFORMATION

98006118- iSBC 80/30 Single Board Computer
Hardware Reference Manual (NOT
SUPPLIED)

Part Number Description
SBC 80/30
Single Board Computer with 16K
bytes RAM

3-26

iSBC® 186/03A
SINGLE BOARD COMPUTER
8.0 MHz 80186 Microprocessor with
• Optional
8087 Numeric Data Processor
Eight (Expandable to 12) JEDEC 28-Pin
• Sites
Programmable Timers and 27
• Six
Levels of Vectored Interrupt Control
MULTIBUS® Interface for System
• Expansion
and Multimaster

24 Programmable
Lines
• Configurable
as a SCSI Interface,
1/0

Centronics Interface or General
Purpose I/O
iSBXTM Bus Interface Connectors
• Two
for Low Cost
Expansion
iLBXTM (Local Bus Extension) Interface
• for
High-Speed Memory Expansion
Programmable Serial Interfaces;
• Two
One RS 232C, the Other RS 232C or
1/0

Configuration

RS 422 Compatible
The iSBC 186/03A Single Board Computer is a member of Intel's complete line of microcomputer modules
and systems that take advantage of Intel's VLSI technology to provide economical, off·the-shelf, computerbased solutions for OEM applications. The board is a complete microcomputer system on a 7.05 x 12.0 inch
printed circuit card. The CPU, system clock, memory, sockets, I/O ports and drivers, serial communications
interface, priority interrupt logic and programmable timers, all reside on the board.
The iSBC 186/03A board incorporates the 80186 CPU and SCSI interface on one board. The extensive use of
high integration VLSI has produced a high-performance single-board system. For large memory applications,
the iLBX local bus expansion maintains this high performance.

230988-1

3-27

September 1987
Order Number: 230988-005

iSBC® 186/03A COMPUTER

OVERVIEW

BITBUSTM MASTER CONTROLLER
The BITBUS interconnect environment is a high performance low-cost microcontroller interconnect
technology for distributed control of intelligent industrial machines such as robots and process controllers. The BITBUS interconnect is a special purpose
serial bus which is ideally suited for the fast transmission of short messages between the microcontroller nodes in a modularly distributed system.

Operating Environment
The iSBC 186/03A single board computer features
have been designed to meetthe needs of numerous
microcomputer applications. Typical applications include:
• Multiprocessing single board computer
• BITBUS master controller

The iSBC 186/03A board can be implemented as
the MULTIBUS-based master controller CPU which
monitors, processes and updates the control status
of the distributed system. The iSBX 344 board is
used to interface the iSBC 186/03A board to the
BITBUS interconnect. Actual message transfer over
the iSBX bus can be accomplished by either software polling by the CPU or by using the on-chip
80186 DMA hardware instead of the CPU. Using
DMA, the CPU is only required to start the DMA process and then poll for the completion of the message transfer, thus dramatically improving the data
transmission rate and master control processor efficiency. The maximum transfer rates over the iSBX
bus for the iSBC 186/03A board are about 900 messages/second in polled mode and 2500 messages/
second in DMA mode. An 8 MHz iSBC 186/03A
board in DMA mode is 3 times as fast as a typical
5 MHz iSBC 86/30 board running in polled mode.
The iSBC 186/03A board in DMA mode provides the
highest performance/price solution for BITBUS
message transmission out of all of Intel's complete
line of 16-bit CPU modules.

• Stand-alone singel board system
MULTIPROCESSING SINGLE BOARD
COMPUTER
High-performance systems often need to divide system functions among multiple processors. A multipr.oc~ssing single ~oard computer distributes an applications processing load over multiple processors
that communicate over a system bus. Since these
applications use the system bus for inter-processor
communication, it is required that each processor
has local execution memory.
The iSBC 186/03A board supports loosely coupled
multiprocessing (where each processor performs a
spe~ific function) through its MULTIBUS compatible
architecture. The IEEE 796 system bus facilitates
processor to processor communication while the
iLBX bus makes high-speed data and' execution
memory available to each CPU as shown in Figure 1.
This architecture allows multiple processors to run in
~arallel enabling very high-performance applications.

SERIAL LINK
TO MAINFRAME

c:::J c:::::J
ISBC" 544
BOARD

ISBC" 188/03A
BOARD

ISBC'" 012CX RAM
BOARD

MUL TlBUS· SYSTEM BUS

230988-2

Figure 1. A Multiprocessing Single Board Computer Application
3-28

isec® 186/03A COMPUTER
INTERNAL MACHINE CONTROL

r - ------

...----..,

¢¢

MASTERC~TROL;:; -

"""1

ISBX'· BUS

ISBX'" 344
BITBUS'·
INTERFACE
BOARD

BITBUS'·
INTERCONNECT

MOTOR
L....-_ _ _.... CONTROL

¢¢

ISBX'" BUS

,...",.",.,,.,,.,.,,... OPERATOR
INTERFACE
PUSH
~=::'::::'..1 BUTTONS

IRCB 44/10

TEMPERATURE ...---";"'.....,
MONITORING
AND CONTROL L -_ _ _......

. . . - - - - . . . . , OPERATOR
1--_ _ _...... DISPLAY

L ___________________

ICHANDLER

230988-3

Figure 2. Sample ISBC@) 186/03A BITBUSTM Master Application
iSBC 186/03A board. The KEPROM memory device
employs a data protection mechanism which makes
the memory array unreadable until unlocked by an
authorized 64-bit "key".KEPROMs protect system
software from unauthorized use. If more memory is
needed, an optional iSBC 341 memory site expansion board can be added to provide an additional
four JEDEC sites. Two iSBX MULTIMODULETM
boards can be added to the iSBC 186/03A board to
customize the board's 1/0 capabilities. As shown in
Figure 3, the iSBX connectors can support a singleboard system with the analog input and output modules needed by machine or process control systems.

STAND-ALONE SINGLE BOARD SYSTEM
A stand-alone single board system is a complete
computer system on one board. By reducing the system's board count, the single board system saves
space, power, and ultimately, costs. The on-board
resources need to be capable of performing all of
the basic system functions. These applications typically require terminal support, peripheral control, local RAM and program execution. In previous generations of single board computers, these functions
could only be obtained with multiple board solutions.
The iSBC 186/03A board integrates all the functions
of a general purpose system (CPU, memory, 1/0 and
peripheral control) onto one board. The iSBC
186/03A board can also be customized as a single
board system by the selection of memory and iSBX
1/0 options. The board's 8 JEDEC 28-pin sockets
can accommodate a wide variety of byte-wide memory devices. For example, four 27256 EPROMS and
four 2186 IRAMs can be installed for a total of 128
KB of EPROM program storage and 32 KB of RAM
data storage. In addition, Intel's JEDEC site compatible 27916 KEPROMTM (Keyed Access EPROM)
memory device may be configured for use on the

FUNCTIONAL DESCRIPTION

Architecture
The iSBC 186/03A board is functionally partitioned
into six major sections: central processor, memory,
SCSI compatible parallel interface, serial 1/0, interrupt control and MULTIBUS bus expansion. These
areas are illustrated in Figure 4.

3-29

inter

iSBC® 186/03A COMPUTER

SCSI BUS

ISBX'"311
ANALOG INPUT
BOARD

230988-4

Figure 3. A Stand-Alone Single Board System Application

1
EXPANSION
:
IL ____________ _ ,

MULTI BUS· SYSTEM BUS

230988-5

Figure 4. iSBC® 186/03A Board Block Diagram

3-30

iSBC® 186/03A COMPUTER

generator, square-wave generator, software triggered strobe, hardware triggered strobe and event
counter. The contents of each counter may be read
at any time during system operation.

CENTRAL PROCESSOR
The 80186 component is a high-integration 16-bit
microprocessor. It combines several of the most
common system components onto a single chip (Le.
Direct Memory Access, Interval Timers, Clock Generator and Programmable Interrupt Controller). The
80186 instruction set is a superset of the 8086. It
maintains object code compatability while adding
ten new instructions. Added instructions include:
Block I/O, Enter and Leave subroutines, Push Immediate, Multiply Quick, Array Bounds Checking,
Shift and Rotate by Immediate, and Pop and Push
All.

MEMORY
There are eight JEDEC 28-pin memory sites on the
iSBC 186/03A board providing flexible memory expansion. Four of these sites (EPROM sites) may be
used for EPROM or E2PROM program storage,
while the other four (RAM sites) may be used for
static RAM or iRAM data storage or used as additional program storage. The eight sites can be extended to twelve by the addition of an iSBC 341
MULTIMODULE board. These additional sites will
provide up to 64K bytes of RAM using 8K x 8 SRAM
or iRAM devices. The EPROM sites (Bank B) are
compatible with 8K x 8 (2764), 16K x 8 (27128A),
32K x 8 (27256), 64K x 8 (27512) as well as 2K x 8
(2817A) and 8K x 8 (2864) E2PROMs. The RAM
sites (Bank A) are compatible with all bytewide
SRAM, iRAM or NVRAM devices. NVRAM usage requires additional circuitry in order to guarantee data
retention. (Refer to AP-173 for further information.)
Bank A can be reassigned to upper memory just below the assigned memory space for Bank B to support additional EPROM or E2PROMs.

Use of the 80130 component is limited to the 3 timers and 8 levels of interrupts available. Direct processor execution of the 16K bytes of iRMX 86 Operating System nucleus primitives is not supported.
An optional 8087 Numeric Data Processor may be
installed by the user to dramatically improve the
186/03A board's numerical processing power. The
interface between the 8087 and 80186 is provided
by the factory-installed 82188 Integrated Bus Controller which completes the 80186 numeric data processing system. The 8087 Numeric Data Processor
option adds 68 floating-point instructions and eight
80-bit floating point registers to the basic iSBC 186/
03A board's programming capabilities. Depending
on the application, the 8087 will increase the performance of floating point calculations by 50 to 100
times.

Memory addressing for the JEDEC sites depends on
the device type selected. The four EPROM sites are
top justified in the 1 MB address space and must
contain the power-on instructions. The device size
determines the starting address of these devices.
The four RAM sites are, by default, located starting
at address O. The addressing of these sites may be
relocated to upper memory (immediately below the
EPROM site addresses) in applications where these
sites will contain additional program storage. The
optional iSBC 341 MULTIMODULE sites are addressable immediately above the RAM site addresses.

TIMERS
The 80186 provides three internal 16-bit programmable timers. Two of these are highly flexible and
are connected to four external pins (two per timer).
They can be used to count external events, time external events, generate nonrepetitive waveforms,
etc. As shipped on the iSBC 186/03A board, these
two timers are connected to the serial interface, and
provide baud rate generation. The third timer is not
connected to any external pins, and is useful for
real-time coding and time-delay applications. In addition, this third timer can be used as a prescaler to
the other two, or as a DMA request source. The
80130 provides three more programmable timers.
One is a factory default baud rate generator and outputs an 8254 compatible square wave that can be
used as an alternate baud rate source to either serial
channel. The 80130's second timer is used as a system timer. The third timer is reserved for use by the
iRMX Operating System. The system software configures each timer independently to select the desired function. Available functions include: interrupt
on terminal count, programmable one-shot, rate

Power-fail control and auxiliary power are provided
for protection of the RAM sites when used with static
RAM devices. A memory protect signal is provided
through an auxiliary connector (J4) which, when asserted, disables read/write access to RAM memory
on the board. This input is provided for the protection of RAM contents during system power-down sequences. An auxiliary power bus is also provided to
allow separate power to RAM for systems requiring
battery back-up of read/write memory. Selection of
this auxiliary RAM power bus is made via jumpers on
the board.

3-31

intJ

iSBC® 186/03A COMPUTER

The Centronics interface requires very little software
overhead since a PAL device is used to provide necessary handshake timing .. Interrupts are gene~at~d
for printer fault conditions and a DMA request IS ISsued for every character. The interface supports
Centronics type printers compatible with models 702
and 737.

SCSI PERIPHERAL INTERFACE
The iSBC 186/03A board includes a parallel peripheral interface that consists of three 8-bit parallel
ports. As shipped, these· ports are configured for
general purpose 1/0. The parallel interface may be
reconfigured to be compatible with the SCSI disk in"
terface by adding two user-supplied and programmed Programmable Array. Logic (PAL) devic~s,
moving jumpers and .installing a user-su~phed
74LS640-1 device. Alternatively, the parallel Interface may be reconfigured as a DMA controlled C~n
tronics compatible line. printer interface by adding
one PAL and changing jumpers. Refer to the iSBC
186/03A Hardware Reference Manual for PAL
equations and a detailed implementation procedure.

SERIAL 1/0
The iSBC 186/03A Single Board Computer contains
two programmable communications interfaces using
the Intel 8274 Multi-Protocol Serial Controller
(MPSC).
Two 80186 timer outputs are used as software selectable baud rate generators capable of supplying
the serial channels with common communications
frequencies. An 80130 baud rate timer may be jumpered to either serial port to provide higher frequency
baud rates. The mode of operation (i.e., asynchronous, byte synchronous or bisynchronous pro~o
cols), data format, control character format, panty,
and baud rate are all under program control. The
8274 provides full duplex,. double I:)uffered trans~it
and receive capability. Parity, overrun, and framing
error detection are all incorporated in .the MPSC.
The iSBC 186/03A board supports operation in the
polled, interrupt and DMA driven in.terfa~es t~rou~h
jumper options. The default configuration IS With
channel .A as RS422A1RS449, channel B as
RS232C. Channel A can optionally be configured to
support RS232C. Both channels are default configured as data set (DCE). Channel A can be reconfiguredas data terminal (DTE) for connection to a modem-type device.

The SCSI (Small Computer Systems Interface) interface allows up to 8 mass storage peripherals such
as Winchester disk drives, floppy disk drives and
tape drives to be connected directly to. the iSBC
186/03A board. Intel's iSBC 186/03A board utilizes
a Single initiator, single target implementation of the
SCSI bus specification. Bus arbitration and deselectlreselect SCSI features are not supported. Single host, multiple target configurations can be used.
However, the iSBC. 186/03A board will stay. connected to one target until the transaction is completed before switching to the second target. The iSBC
186/03A board's SCSI interface implements a 5 megabitlsecond transfer nite. A sample SCSI application is shown in Figure 5. Intel tested iSBC 186/03A
board compatible SCSI controllers include Adaptek
4500, DTC 1410, Iomega Alpha 10, Shugart 1601
and 1610, Vermont Research 8103 and Xebec
1410.

SCSI BUS

ISac· 188f03A
BOARD

MULTIBUS· SYSTEM BUS

230988-6

Figure 5. Sample SCSI Application
3-32

iSBC® 186/03A COMPUTER

iLBX local bus expansion and the iSBX MULTIMODULE expansion bus as shown in Figure 6. Each bus
structure is optimized to satisfy particular system requirements. The system bus provides a basis for
general system design including memory and 1/0
expansion as well as multiprocessing support. The
iLBX bus allows large amounts of high performance
memory to be accessed by the iSBC 186/03A board
over a private bus. The iSBX MULTIMODULE expansion board bus is a means of adding inexpensive
1/0 functions to the iSBC 186/03A board. Each of
these bus structures are implemented on the iSBC
186/03A board providing a flexible system architecture solution.

INTERRUPT CONTROL
The iSBC 186/03A board provides 27 on-board vectored interrupt levels to service interrupts generated
from 33 possible sources.
The interrupts are serviced by four programmable
interrupt controllers (PICs): one in the 80186 component, one in the 80130 component, one in the 8259A
component and one in the 8274 component. The
80186, 8259A and 8274 PICs act as slaves'to the
80130 master PIC. The highest priority interrupt is
the Non-Maskable Interrupt (NMI) line which is tied
directly to the .80186 CPU. This interrupt is typically
used to signal catastrophic events (e.g. power failure). The PICs provide prioritization and vectoring for
the other 26 interrupt requests from on-board 1/0
resources and from the MULTlBUS system bus. The
PICs then resolve the requests according to the programmable priority resolution mode, and if appropriate, issue an interrupt to the CPU.

MULTIBUS® SYSTEM BUS-IEEE 796
The MULTIBUS system bus is an industry standard
(IEEE 796) microcomputer bus structure. Both 8and 16-bit single board computers are supported on
the IEEE 796 structure with 20 or 24 address and 16
data lines. In its simplest application, the system bus
allows expansion of functions already contained on
a single board computer (e.g., memory and 1/0).
However, the IEEE 796 bus also allows very powerful distributed processing configurations with multiple processors and intelligent slave, 1/0 and peripheral boards capable of solving the most demanding
microcomputer applications. The MULTIBUS system
bus is supported with a broad array of board-level
products, LSI interface components, detailed published specifications and application notes.

Table 1 contains a list of devices and functions capable of generating interrupts. These interrupt
sources are jumper configurable to the desired interrupt request level.

Expansion
OVERVIEW
The iSBC 186/03A board architecture includes
three bus structures: the MULTIBUS system bus, the

Table 1. Interrupt Request Sources
Function

Device

Number of
Interrupts

MULTIBUS Bus
Interface
INTO-INT7

Requests from MUL TIBUS Bus Resident Peripherals or
Other CPU

8274 Serial Controller

Transmit Buffer Empty, Receive Buffer Full and Channel
Errors

Internal 80186 Timer
and DMA

Timer 0, 1, 2, Outputs (Function Determined by Timer
Mode) and 2 DMA Channel Interrupts

80130 Timer Output

iRMX System Timer (SYSTICK)

iSBX Bus Connectors

Function Determined by iSBX MULTIMODULE Board

6
(3 per
iSBX Connector)

Bus Fail-Safe Timer

Indicates Addressed MULTIBUS Bus Resident Device
Has Not Responded to Command within 10 ms

8255A Parallel 1/0
Controller

Parallel Port Control

J4 Connector

External/Power-Faillnterrupts

3-33

iSBC® 186/03A COMPUTER

(SBX'·
MULTlMODULE'·
BOARD

230988-7

Figure 6. iSBC® 186/03A Board System Architecture
lines for maximum data transfer rates. MULTIMODULE boards designed with 8-bit data paths and using
the 8-bit iSBX connector are also supported on the
iSBC 186/03A board. A broad range of iSBX MULTIMODULE options are available from Intel. Custom
iSBX bus modules may also be designed. An iSBX
bus interface specification is available from Intel.

iLBXTM BUS-LOCAL BUS EXTENSION
The iSBC 186/03A board provides a local bus ex·
tension (iLBX) interface. This standard extension allows on-board memory performance with physically
off-board memory. The combination of a CPU board
and iLBX memory boards is architecturally equivalent to a single board computer and thus can be
called a "virtual single board computer". The iLBX
bus is implemented over the P2 connector and requires independent cabling or backplane connection.

OPERATING SYSTEM SUPPORT
Intel's iRMX 86 Operating System is a highly functional operation system with a very rich set of features and options based on an object-oriented architecture. In addition to being modular and configurable,functions include a sophisticated file management and 1/0 system, and a powerful human interface. The iRMX 86 Release 6 Operating System can
be used with the iSBC 186/03A board to generate
application code for iRMX 86 based systems.

iSBXTM BUS MULTIMODULETM
ON-BOARD EXPANSION
Two iSBX MULTlMODULE board connectors are
provided on the iSBC 186/03A microcomputer
board. Through these connectors, additional onboard 1/0 functions may be. added. iSBX MULTIMODULE boards optimally support functions provided by VLSI peripheral components such as additional parallel and serial 110, analog 1/0, and graphics
control. The iSBX bus connectors on the iSBC
186/03A board provide all Signals necessary to interface to the local on-board bus, including 16 data

NOTE:
Intel does not support the direct processor execution of the 16K bytes of the iRMX 86 Operating
System nucleus primitives from the 80130 component.

3-34

iSBC® 186/03A COMPUTER

allowing explicit control of the system's resources
when needed. C 86 is especially appropriate in applications requiring portability and code density. FORTRAN 86, PASCAL 86, and BASIC 86 are also available on the iRMX 86 operating system, on the System 86/3XX and on the Intellec development system.

DEVELOPMENT ENVIRONMENT
Intel offers numerous tools to aid in the development
of iSBC 186/03A board applications. These include
on-target development, full development systems,
in-circuit emulators and programming languages.
Some of the features of each are described below.
Using the iRMX 86 Operating System, software development can be performed directly on the iSBC
186/03A board. This on-target development is the
most economical way to develop iSBC 186/03A
board" based projects.
The development cycle of iSBC 186/03A board
products can be significantly reduced and simplified
by using either the System 86/3XX (iRMX 86-based)
or the Intellec® Series Microcomputer Development
Systems.

SPECIFICATIONS
Word Size
. Instruction-8, 16, 24 or 32 bits
Data-8 or 16 bits

System Clock
8.0 MHz

The Integrated Instrumentation In-Circuit Emulator
(12ICETM) provides the necessary link between an
Intellec development system and the "target" iSBC
186/03A execution system. In addition to providing
the mechanism for loading executable code and
data into the iSBC 186/03A boards, the 121CE 186
emulator provides a sophisticated command set to
assist in debugging software and final integration of
the user hardware and software.

Numeric Data Processor (Optional)
8087-1

Basic Instruction Cycle Time
750 ns
250 ns (assumes instruction in the queue)

Intel has two systems implementation languages,
PL/M 86 and C 86. Both are available for use on the
iRMX 86 Operating System, on the System 86/3XX
and on the Intellec Microcomputer Development
System. PLIM 86 provides the capability to program
in algorithmic language and eliminates the need to
manage register usage or allocate memory while still

NOTE:
Basic instruction cycle is defined as the fastest instruction time (i.e. two clock cycles plus instruction
fetch). Zero wait-state memory is assumed.

MEMORY RESPONSE TIMES
OeviceType
EPROM Memory Sites
o Wait States
1 Wait State
RAM Memory Sites
with SRAMs or EPROMs
o Wait States
1 Wait States
with 21861RAMs
1 Wait State
2 Wait States

Max Access Time
(from Chip Enable)

Min Cycle Time

245 ns
370 ns

318 ns
443 ns

197 ns
322 ns

318 ns
443 ns

261 ns
386 ns

443 ns
568 ns

NOTE:
The number of wait states inserted is jumper selected depending on memory device speCifications.

3-35

inter

iSBC®186/03A COMPUTER

MEMORY CAPACITY I ADDRESSING

Common Baud Rates
Using 80186 Timers:
Using 80130 Timer:
500K
750K
125K
500K
64K
125K
48K
64K
19.2K
48K
9600
19.2K
4800
9600
2400
4800
1200
2400
600
1200
300
600
150
300
110"
150
110'
75"
75"

Four EPROM Sites
Device

2764 EPROM
27128 EPROM
27256 EPROM
27512 EPROM

Capacity

32 KB
64 KB
128 KB
256 KB

Address Range

F8000H-FFFFFH
FOOOOH-FFFFFH
EOOOOH-FFFFFH
COOOOH-FFFFFH

Four RAM Sites
Device

Capacity

Address Range

2KSRAM
8KSRAM
32KSRAM
2186 RAM
2817A E2PROM
2764 EPROM

8KB
32 KB
128 KB
32 KB
8KB
32 KB

27128 EPROM

64 KB

27256 EPROM

128 KB

0-01FFFH
0-07FFFH
0-1FFFFH
0-07FFFH
FOOOOH-F7FFFH'
FOOOOH-F7FFFH
(below EPROM Sites)
EOOOOH-EFFFFH
(below EPROM Sites)
COOOOH-OFFFFH
(below EPROM Sites)

"Asynchronous use only
NOTE:
Frequency selected by 110 write of appropriate 16·bit frequency factor to baud rate register of 80186 or 80130 timers.

Four iSBC® 341 Expansion Sites
Device

Capacity

2KSRAM
8KSRAM
32KSRAM
2186 RAM
2817A E2PROM

8 KB
32 KB
128 KB
32 KB
8KB

Timer Input Frequency

Address Range

80186 Reference: 2.0 MHz ± 0.1 %
80130 Reference: 8.0 MHz ±0.1%

02000H-03FFFH
08000wOFFFFH
10000H-1FFFFH
08000H-OFFFFH
02000w-03FFFH* "

Interface Compliance
MULTIBUS- IEEE 796 compliance: Master 016
M24 116 VO EL
iSBX Bus- Two 8/16 bit iSBX bus connectors allow use of up to 2 single-wide modules or 1 single-wide and 1 doublewide module. InteliSBX bus compliance: 016/16 OMA
iLBXIntel iLBX bus compliance: PM 016
SerialChannel A: Configurable as RS 422A
or RS 232C compatible,
configurable as a data
set or data terminal
Channel B: RS 232C compatible,
configured as data set
Parallel 1/0- SCSI (ANSI-X3T9, 2/82-s) compatible or Centronics 702 or 737 compatible (requires user supplied PALs and
74LS640-1)

NOTE:
All on board memory is local to the CPU (Le. not dual-ported).

"Must use 8k x 8 decode option, there are four copies of
the E2PROM in the 8K x 8 address area.
""(May be mixed with 2K x 8 SRAM)

Serial Communications Characteristics
Synchronous-

5-8 bit characters, internal or external character synchronization;
automatic sync insertion; break
character generation
Asynchronous- 5-8 bit characters; 1, %, or 2
stop bit; false start bit detection.

3-36

inter

iSBC® 186/03A COMPUTE ..

, CONNECTORS
Interface
MULTIBUS
System

iSBX Bus
8-Bit Data
16-Bit Data

PHYSICAL CHAPIACTERISTICS

Doublesided
Pins

Width: 12.00 in. (30.48 cm)
Length: 7.05 in (17.90 cm)
Height: 0.50 in. (1.78 cm)

Mating
Connectors

86 (P1)

Viking
3KH43/9AMK12
Wire Wrap

60 (P2)

Viking
3KH30/9JNK

Viking 000292-0001

Viking 000293-0001

Serial 1/0

iLBX Bus

Kelam
RF30-2853-542

Parallel
Interface

3M 3425-6000
3M 3425-6050
w/strain
Ansley 609-5001 M

Weight: 13 ounces

ENVIPlON·MENTAL CHARACTERISTICS
Operating Temperature: O°C to 60°C at 6 CFM airflow over the board.
Relative Humidity: to 90% (without condensation)

3M 3452-0001 Flat
AMP88106-1 Flat

ELECTPI.CAL CHARACTERISTICS
The maximum power required per voltage is shown
below. These numbers do not include the power required by the optional memory devices, SCSI PALs,
battery back-up or expansion modules.

Voltage
(volts)
+5
+ 12
-12

ORDERING INFORMATION
Part Number
SBC 186/03A

Description
186-based single board computer

REFERENCE MANUAL
iSBC® 186/03A Single Board Computer Hardware
Reference Manual-Order Number 148060

3-37

Max. Current
(amps)
5.4
0.04
0.04

Max Power
(watts)
27
0.48
0.48

intJ

iSBC® 86/35
SINGLE BOARD COMPUTER

Programmable Synchronous/
(8086·2) Microprocessor with 5 or
• Asynchronous
• 88086
RS232C Compatible
MHz CPU Clock
Serial Interface with Software
Optional 8086 Numeric Data Processor
• with ISBC® 337A MULTIMODULETM
Selectable Baud Rates

•
•

Processor
Upward Compatible with iSBC 86/30
Single Board Computer
512K Bytes of Dual·Port Read/Write
Memory Expandable On·Board to 640K
or 1M Bytes
Sockets for up to 128K Bytes of JEDEC
24/28·Pin Standard Memory Devices
Two iSBXTM Bus Connectors

•
• 24 Programmable Parallel I/O Lines
•

•
•
•
•

Three Programmable 16·Bit BCD or
Binary. Timers/Event Counters
9 Levels of Vectored Interrupt Control,
Expandable Off Board to 65 Levels
MULTIBUS® Interface for Multimaster
Configurations and System Expansion
Supported by a Complete Family of
Single Board Computers, Memory,
Digital and Analog I/O, Peripheral
Controllers, Packaging and Software

The iSBC 86/35 Single Board Computer is a member of Intel's complete line of OEM microcomputer systems
that take full advantage of Intel's technology to provide economical, self-contained, computer-based solutions
for OEM applications. The board is a complete computer system containing the CPU, system clock, dual port
read/write memory, nonvolatile read only memory, I/O ports and drivers, serial communications interface,
priority interrupt logic and programmable timers, all on a single 6.75 x 12.00 in. printed circuit card. The iSBC
86/35 board is distinguished by its large RAM content of 512K bytes which is expandable on-board to 1
megabyte; the direct addressing capability of the 8086-2 CPU. The large, on-board memorY resource combined with the 8086 microprocessor provides high-level system performance ideal for applications, such as
robotics, process control, medical instrumentation, office systems, and business data processing.

210219-1

3-38

September 1987
Order Number: 210219-004

iSBC® 86/35 SINGLE BOARD COMPUTER

registers, all accessed by a total of 24 operand addressing modes for comprehensive memory addressing and for support of the data structures required for today's structured, high level languages
as well as assembly language.

FUNCTIONAL DESCRIPTION
Overview
The iSBC 86/35 board combines the power of the
industry standard 8086 CPU with up to a megabyte
page of board resident, dual ported system memory
to improve the system's overall performance. By
placing the direct memory addressing capability of
the iAPX 86/10 CPU on board, MULTIBUS® access
to system memory can be eliminated, significantly
improving system throughput. Intel's incorporation of
256K bit DRAM technology, parallel and serial I/O,
iSBXTM connectors, and interrupt control capabilities
make this high performance single board computer
system a reality.

Instruction Set
The 8086 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8-bit and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manipulation functions.
For enhanced 5 or 8 MHz numerics processing capability, the iSBC 337A MULTIMODULE Numeric
Data Processor extends the iAPX 86/10 architecture
and data set. Over 60 numeric instructions offer
arithmetic, trigonometric, transcendental, logarithmic
and exponential instructions. Supported data types
include 16-, 32-, and 64-bit integer, and 32- and 64bit floating point, 18-digit packed BCD and 80-bit
temporary.

Central Processing Unit
The central processor for the iSBC 86/35 board is
Intel's iAPX 86/10 (8086-2) CPU. A clock rate of 8
MHz is supported with a jumper selectable option for
5 MHz. The CPU architecture includes four 16-bit
byte addressable data registers, two 16-bit index

,...-------I 1211" II IUSIc1> 3041
I $12KlIlIlIsaC$314)
512K

e USlcl!lallf35)

MULTI BUS ® SYSTEM BUS

210219-2

Figure 1. iSBC® 86/35 Block Diagram

3-39

inter

iSBC® 86/35 SINGLE BOARD COMPUTER

The dual~port controller allows access to the onboard RAM (including RAM MULTIMODULE board
options) from the iSBC 86/35 board and from any
other MULTIBUS master via the system bus .. Segments of on-board RAM may be configured as a private resource, protected from MULTIBUS system
access.

Architectural Features
A 6-byte instruction qLJeue provides pre-fetching of
sequential instructions and can reduce the 750 ns
minimum instruction cycle to 250 ns for queued instructions. The stack-oriented architecture readily
supports modular programming by facilitating fast,
simple, inter-modular communication, and other programming constructs needed for asynchronous realtime systems. The memory expansion capabilities
offer a 1 megabyte addressing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses.
Each register maps 64K bytes at a time and activation of a specific register is controlled explicitly by
program control and is also selected implicitly by
specific functions alid instructions.

EPROM

Capabili~ies

Four 28-pin JEDEC sockets are provided for the use
of Intel 2764, 27128, 27256, 27512, EPROMs and
their respective ROMs. When using 27512,the onboard EPROM capacity is 256K bytes. Other JEDEC
standard pinout devices are also supported, including byte-wide static RAMs.

Parallel 1/0 Interface
The iSBC 86/35 Single Board Computer contains 24
programmable parallel 110 lines implemented using
the Intel 8255A Programmable Peripheral Interface.
The system software i,s used to configure the 110
lines in any combination of unidirectional input/output and bidirectional ports indicated in Table 1. In
order to take advantage of the large number of possible 110 configurations, sockets are provided for interchangeable 110 line drivers and terminatOrs, allowing the selection of tne appropriate combination
of optional'line drivers and terminators with the required drive/termination characteristics. The 24 programmable 110 lines and signal ground lines are
brought out to a 50-pin edge connector.
'

RAM Capabilities
The iSBC 86/35 microcomputer contains 512K
bytes of dual-port dynamic RAM which may be expanded ,on-board by adding a RAM Multimodule
board as an option. The on-board RAM may be expanded to 640K bytes with the iSBC 304 MULTIMODULE board mounted, onto the iSBC 85/35
board. Likewise, the iSBG 86/35 microcomputer.
may be expanded to 1 Megabyte with the iSBC 314
MULTIMODULE board option.

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Port

Unidirectional

Lines
(qty)

Input

Control

Output

Bidirectional

Latched

Latched &
Strobed

Latched

Latched &
Strobed

NOTE:
1. Part of port 3 must be used asa control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.

3-40

inter

iSBC® 86/35 SINGLE BOARD COMPUTER

Table 2. Programmable Timer Functions

Serial 1/0

Function

A programmable communications interface using
the Intel 8251A Universal Synchronous/Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 86/35 board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(i.e., synchronous or asynchronous), data format,
control character format, parity, and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun, and framing error detection are all
incorporated in the USART. The RS232C command
lines, serial data lines and signal ground line are
brought out to a 26-pin edge connector.

Operation

When terminal count is reached,
Interrupt on
terminal count an interrupt request is generated.
This function is extremely useful
for generation of real-time clocks.
Programmable Output goes low upon receipt of an
external trigger edge or software
one-shot
command and returns high when
terminal count is reached. This
function is retriggerable.
Rate
generator

Programmable Timers

Divide by N counter. The output
will go low for one input clock
cycle, and the period from one low
going pulse to the next is N times
the input clock period.

Square-wave Output will remain high until onerate generator half the count has been
completed, and go low for the
other half of the count.

The iSBC 86/35 board provides three independent,
fully programmable 16-bit interval timers/event
counters utilizing the Intel 8253 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate timer intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
110 terminators associated with the 8255A to allow
external devices or an 8255A port to gate the.timer
or to count external events. The third interval timer
in the 8253 provides the programmable baud rate
generator for the iSBC 86/35 board's RS232C
USART serial port. The system software configures
each timer independently to select the desired function. Seven functions are available as shown in Table 2. The contents of each counter may be read at
any time during system operation. .

iSBXTM MULTIMODULETM On-Board
Expansion
Two 8/16-bit iSBX MULTIMODULE connectors are
provided on the iSBC 86/35 microcomputer.
Through these connectors, additional on-board 110
functions may be added. iSBX MULTIMODULE
boards optimally support functions provided by VLSI
peripheral components such as additional parallel
and serial I/O, analog I/O, small mass storage device controllers (e.g., cassettes and floppy· disks),

3-41

Software
triggered
strobe

Output remains high until software
loads count (N). N counts after
count is loaded, output goes low
for one input clock period.

Hardware
triggered
strobe

Output goes low for one clock
period N counts after rising edge
counter trigger input. The counter
is retriggerable.

Event counter

On a jumper selectable basis, the
clock input becomes an input from
the external system. CPU may
read the number of events
occurring after the counter
"window" has been enabled or an
interrupt may be generated after N
events occur in the system.

inter

ISBC® 86/35 SINGLE BOARD COMPUTER

and other custom interfaces to meet specific needs.
By mounting directly on the single board computer,
less iliterface logic, less power, simpler packaging,
higher performance, and lower cost result when
compared to other alternatives such as MULTIBUS
form factor compatible boards. The iSBX connectors
on the iSBC 86/35 board provides all Signals necessary to interface to the local on-board bus, including
16 data lines for maximum data transfer rates. iSBX
MULTIMODULE boards designed with 8-bit data
paths and using the 8-bit iSBX connector are also
supported on the iSBC 86/35 microcomputer. A
broad range of iSBX MULTIMODULEoptions are
available in this family from Intel. Custom iSBX modules may also be designed for use on the iSBC 861
35 board.' An iSBX bus interface specification and
iSBX connectors are available from Intel.

both serial (daisy chain) and parallel priority
schemes. The serial scheme allows up to three iSBC
86/35 boardslbus masters to share the MULTIBUS
system bus; while up to .16 masters may be connected using the parallel scheme and external decode
logic.

Interrupt Capability

MULTIBUS® SYSTEM BUS
CAPABILITIES
Overview
The MULTIBUS system bus is Intel's industry standard (IEEE 796) microcomputer bus structure. Both
8- and 16-bit single board computers are, supported
on the MULTIBUS structure with 24 address and 16
data lines. In its simplest application, the MULTIBUS
system bus· allows expansion of functions already
contained on a single board computer (e.g., memory
and digital 1/0). However, the MULTIBUS structure
also allows very powerful distributed processing
configurations with multiple processors and intelligent slave 1/0, and peripheral boards capable of
solving the most demanding microcomputer applications. The MULTIBUS system bus is supported with
a broad array of board level products, LSI interface
components, detailed published specifications and
application notes. Please refer to the MULTIBUS,
Handbook (order number 210883) for more detailed
information.

Multimaster Capabilities

The iSBC 86/35 board provides 9 vectored interrupt
levels. The highest level is the NMI (Non-Maskable
Interrupt) line which is directly tied to the 8086-2
CPU. This interrupt is typically used for Signaling catastrophic events (e.g., power failure). The Intel
8259A Programmable Interrupt Controller (PIC) provides control and vectoring for the next eight interrupt levels. As shown in Table 3, a selection of four
priority processing modes is available for use in deSigning request processing configurations to match
system requirements for efficient interrupt servicing
with minimal latencies. Operating mode and priority
assignments may be reconfigured dynamically via
software at any time during system operation. The
PIC accepts interrupt requests from all on-board 1/0
resources and from the MULTIBUS system bus. The
PIC then resolves requests according to the selected mode and, if appropriate, issues an interrupt to
the CPU. Any combination of interrupt levels may be
masked via software, by storing a single byte in the
interrupt mask register of the PIC. In systems requiring additional interrupt levels, slave 8259A PICs may
be interfaced via the MULTIBUS system bus, to generate additional vector addresses, yielding a total of
65 unique interrupt levels.
Table 3_ Programmable Interrupt Masks
Mode

Operation

Fully nested

Interrupt request line priorities
fixed at 0 as highest, 7 as lowest.
Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.
System software assigns lowest
priority level. Priority of all other,
levels based in sequence
numerically on this assignment.
System software examines priorityencoded system interrupt status
via interrupt status register.

Auto-rotating

Specific
priority

For those applications requiring additional processing capacity and the benefits of multiprocessing (Le.
several CPUs and lor controllers logically sharing
system tasks through communication on the system
bus), the iSBC 86/35, board provides full MULTIBUS
arbitration control logic. This control logic allows

Polled

3-42

inter

ISBC® 86/35 SINGLE BOARD COMPUTER

Power-Fail Control and
Auxiliary Power

Interrupt Request Generation
Interrupt requests to be serviced by the iSBC 86/35
board may originate from 28 sources. Table 4 includes a list of devices and functions supported by
interrupts. All interrupt signals are brought to the interrupt jumper matrix where any combination of interrupt sources may be strapped to the desired interrupt request level on the 8259A PIC or the NMI input
to the CPU directly.

Control logic is included to accept a power-fail interrupt in conjunction with the AC-Iow signal from the
Power Supply to initiate an orderly shut down of the
system in the event of a power failure. Additionally,
an active-low TIL compatible memory protect signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of RAM contents during system power-

Table 4. Interrupt Request Sources
Device

Function

Number of
Interrupts

MULTIBUS® interface

Requests from MUL.,TIBUS® resident
peripherals or other CPU boards

8255A Programmable
Peripheral Interface

Signals input buffer full or output
buffer empty; also BUS INTR OUT
general purpose interrupt from
driver/terminator sockets

8251A USART

Transmit buffer empty and receive
buffer full

8253 Timers

Timer 0, 1 outputs; function determined by timer mode

iSBXTM connectors

Function determined by iSBXTM
MULTIMODULETM board

Bus fail safe timer

Indicates addressed MULTIBUS®
resident device has not responded
to command within 6 ms

Power fail interrupt

Indicates AC power is not within
tolerance

Power line clock

Source of 120 Hz signal from power
supply

External interrupt

General purpose interrupt from auxiliary (P2) connector on backplane

iSBC 337A MULTIMODULE
Numeric Data Processor

Indicates error or exception condition

Edge-level conversion

Converts edge triggered interrupt request to level interrupt

OR-gate matrix

Outputs of OR-gates on-board for
multiple interrupts

3-43

8; may be expanded to
64 with slave 8259A
PICs on MULTIBUS® .
boards

4
(2 per iSBXTM connector)

intJ

iSBC® 86/35 SINGLE BOARD COMPUTER

down sequences. An auxiliary power bus is also provided to allow separate power to RAM for systems
requiring battery backup of read/write memory. S~
lection of this auxiliary RAM power bus is made via
jumpers on the board.

SPECIFICATIONS
Word Size
INSTRUCTION -

8, 16, 24, or 32 bits

System Development, Capabilities

DATA -

The development cycle of iSBC 86/35 products can
.be significantly reduced and simplified by using either the System 86/330 or the Intellec!!> Series IV
Microcomputer Development System.

System Clock

IN-CIRCUIT EMULATOR

Cycle Time

8, 16 bits

5 MHz or 8 MHz ±0.1% Oumper selectable)

The 121CE In-Circuit Emulator provides the necessary liI'lk between the software developmentenvi".
ronment and the "target" iSBC 86/35 execution system. In addition to providing the mechanism for loading executable code and data into the iSBC 86/35
board, the 121CE In-Circuit Emulator provides a sophisticated command set to assist in debugging software and final integration of the user hardware and
software.

BASIC INSTRUCTION CYCLE
8 MHz - 250 ns (assumes instruction in the queue)
5 MHz -

400 ns (assumes instruction in the queue)

NOTE:
Basic instruction cycle is defined as the fastest instruction. time (i.e., two clock cycles). Jumper selectable for 1 wait-state on-board memory access.

Software Support

Memory Capacity/ Addressing

Real time support for the iSBC 86/35 board is provided by the iRMX 86 operating system. The iR~X
86 Operating System is a highly functional operating
system with a rich set of features and options based
on an object-oriented architecture. In addition to being modular and configurable, functions beyond the
nucleus include a· sophisticated file management·
and I/O system, and powerful human interface. Both
packages are easily customized and extended by
the user to match unique requirements.

ON-BOARD EPROM

Total Capacity

Address Range

2764
27128
27256
27512

32Kbytes
64K bytes
128K bytes
256K bytes

F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
DOOOO-FFFFFH

ON-BOARD RAM

Interactive mUlti-user support is provided bytheXenix' operating system. Xenix is a compatible deriva.
tive of UNIX", System III.
Language support for the iSBC 86/35 board includes Intel's ASM 86, PL/M 86, and PASCAL, and
FORTRAN, as well as many third party 8086 lan- .
guages. The iSDM monitor provides on-target, interactive system debug capability including breakpoint
and memory examination features. The monitor supports iSBC/iAPX 86,88, 186, and 188 based applications.

Device

Board

Total Capacity

Address Range

iSBC 86/35

512K bytes

0-7FFFFH

. .WITH MULTIMODULETM RAM

'Xenix is a trademark of Microsoft Corp.
"UNIX is a trademark of Bell Labs.

3-44

Board

Total Capacity

Address Range

iSBC 304
iSBC314

640K bytes
1M bytes

8-9 FFFFH
8-FFFFFH

iSBC® 86/35 SINGLE BOARD COMPUTER

I/O Capacity

OUTPUT FREQUENCIES/TIMING INTERVALS

PARALLEL-24 programmable lines using one
8255A.

Single
Timer/Counter

Function

Min

Max

1.63 p,s 427.1 ms

3.26s

466.50 min

Programmable 1.63 p,s 427.1 ms

3.26s

466.50 min

SERIAL-1 programmable line using one 8251A.
Real-time
Interrupt

iSBXTM MULTIMODULETM-2 iSBX boards

~>ne-shot

Serial Communications Characteristics
SYNCHRONOUS-5-8 bit characters; internal or
external character synchronization; automatic sync
insertion
ASYNCHRONOUS-5-8 bit characters; break character generation; 1, 1%, or 2 stop bits; false start bit
detection
BAUD RATES
Frequency (kHz)
(Software
Selectable)

Max

Dual
Timer/Counter
(Cascaded)

Rate
generator

2.342 Hz 613.5 kHz 0.000036 Hz 306.8 kHz

Square-wave 2.342 Hz 613.5 kHz 0.000036 Hz 306.8 kHz
rate generator
Software
riggered
strobe

1.63 p,s 427.1 ms

3.26s

466.50 min

Hardware
riggered
strobe

1.63 p,s 427.1 ms

3.26s

466.50 min

Event
counter

Baud Rate (Hz)

2.46 MHz

Synchronous Asynchronous

153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

38400
19200
9600
4800
2400
1760

+16 +64
9600 2400
4800 1200
600
2400
1200 300
600
150
300
75
150
110

Interfaces
MULTIBUS®-AII signals TTL compatible
iSBXTM BUS-All signals TTL compatible
PARALLEL I/O-All signals TTL compatible

SERIAL I/O-RS232C compatible, configurable as
a data set or data terminal

NOTE:
Frequency selected by 110 write of appropriate 16-bit frequency factor to baud rate register (8253 Timer 2).

TIMER-All signals TTL compatible

Timers

Connectors

INTERRUPT REQUESTS-All TTL compatible

INPUT FREQUENCIES

DoubleSided
Pins

(In.)

0.156

36
44

0.1
0.1

Parallel 110
(2)

0.1

3M 3415-000 Flat
or
TI H312125 Pins

Serial 110

0.1

3M 3462-0001
Flat or
AMP 88106-1 Flat

Interface

Reference: 2.46 MHz, ± 0.1 % (0.041 JA-s period,
nominal); or 153.60 kHz ±0.1 % (6.51 JA-s period,
nominal)

MULTIBUS@
System

NOTE:
Ab.ove frequencies are user selectable.

iSBXTM Bus
8-Bit Data
16-Bit Data

Event Rate: 2.46 MHz max

3-45

Connectors
Viking
3KH43/9AMK12
Wire Wrap
Viking
000292-0001
000293-0001

inter

iSBC® 86/35 SINGLE BOARD COMPUTER

Line Drivers and Terminators

Electrical Characteristics

I/O DRIVERS-The following line drivers are all
compatible with the I/O driver sockets on the iSBC
86/05 board

DC POWER REQUIREMENTS

Driver

Characteristic

Sink Current (rnA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTE:
I = inverting; NI

non-inverting; OC

Curtent Requirements
(All Voltages ± 5%)

Configuration
Without EPROM(l)

Port 1 of the 8255A has 20 mA totem-pole bi-directional drives and 1 kO temrinators

+12V

-12V

25mA

23mA

660mA

With 32K EPROM(3)
(using 2764)

5.6A

25mA

23mA

With 64K EPROM
(using 27128)

5.7A

25mA

23mA

With 128K EPROM
(using 27256)

5.8A

25mA

23mA

RAM only(2)

open collector.

+5V
5.1A

NOTES:
1. Does not include power for optional ROMIEPROM, 1/0
drivers, and 1/0 terminators.
2. RAM chips powered via auxiliary power bus in powerdown mode.
3. Includes power required for 4 ROMIEPROM chips, and
1/0 terminators installed for 16 1/0 lines; all terminator inputs low.

I/O TERMINATORS-2200/3300 divider or 1 kO
pullup
(OPTION 1)

2200/3300
2200

+5V-------'::=+---1
~

...L

Environmental Characteristics

OPERATiNG TEMPERATURE - O°C to 55°C
200 linear feet per minute (LFM) air velocity

210219-3

RELATIVE HUMIDITY ,
sation)

(OPTION 2)

to 90% (without conden-

1 kO

Reference Manual

1 kll

+ 5V----~VV\'r-------O,

146245-002 - iSBC 86/35 Hardware Reference
Manual (NOT SUPPLIED)

210219-4

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

MULTIBUS® Drivers
Function

Characteristic

Sink Current (rnA)

Data
Tri-State
Address
Tri-State
Commands Tri-State
Bus Control Open Collector

32
32
32
20

ORDERING INFORMATION

Physical Characteristics
Width:
Height:
Depth:
Weight:

12.00 in. (30.48 cm)
6.75 in. (17.15 cm)
0.70 in. (1.78 cm)
14 oz. (388 gm)
3-46

Part Number

Description

SBC 86/35

Single Board Computer

iSBC® 88/25
SINGLE BOARD COMPUTER

•
•
•
•
•
•

•

8-Bit 8088 Microprocessor Operating at
5 MHz
One Megabyte Addressing Range
Two iSBXTM Bus Connectors

•
•
•
•
•

Optional Numeric Data Processor with
ISBC® 337A MULTIMODULETM
Processor
4K Bytes of Static RAM; Expandable
On-Board to 16K Bytes
Sockets for up to 64K Bytes of JEDEC
24/28-Pin Standard Memory Devices;
Expandable On-Board to 128K Bytes

Programmable Synchronous/
Asynchronous RS232C Compatible
Serial Interface with Software
Selectable Baud Rates
24 Programmable Parallel 1/0 Lines
Two Programmable 16-Bit BCD or
Binary Timers/Event Counters
9 Levels of Vectored Interrupt Control,
Expandable to 65 Levels
MULTIBUS® Interface for Multimaster
Configurations and System Expansion
Development Support with Intel's iPDS,
Low Cost Personal Development
System, and EMV-88 Emulator

The iSBC 88/25 Single Board Computer is a member of Intel's complete line of OEM microcomputer systems
which take full advantage of Intel's technology to provide economical, self-contained, computer-based solutions for OEM applications. The iSBC 88/25 board is complete computer system on a single 6.75 x 12.00-in.
printed circuit card. The CPU, system clock, read/write memory, nonvolatile read only memory, I/O ports and
drivers, serial communications interface, priority interrupt logic and programmable timers, all reside on the
board. The large control storage capacity makes the iSBC 88/25 board ideally suited for control-oriented
applications such as process control, instrumentation, industrial automation and many others.

143847-1

3-47

October 1988
Order Number: 143847-003

infef

iSBC® 8.8/25 SINGLE BOARD COMPUTER

FUNCTIONAL DESCRIPTION

ASCII data, and iterative word and byte string manipulation functions.

Central Processing Unit

For enhanced numerics processing capability, the
iSBC 337 A MULTIMODULE Numeric Data Processor extends the architecture and data set. Over 60
numeric instructions. offer arithmetic, trigonometric,
transcendental, logarithmic and exponential instructions. Supported data types include 16, 32, and 64bit integer, and 32 and 64-bit floating point, 18-digit
packed BCD and 80-bit temporary.

The central processor for the iSBC 88/25 board is
Intel's 8088 CPU operating at 5 MHz. The CPU architecture includes four 16-bit byte addressable data
registers, two 16-bit memory base pointer registers
and two 16-bit index registers, all accessed by a total of 24 operand addressing modes for comprehensive memory addressing and for support of the data
structures required for today's structured, high level
languages, as well as assembly language.

Architectural Features
A 4-byte instruction queue provides pre-fetching of
sequential instructions and can reduce the 750 ns
minimum instruction cycle to 250 ns for queued instructions. The stack-oriented architecture readily
supports modular programming by facilitating fast,
simple, inter-module communication, and other programming constructs needed for asynchronous realtime systems. The memory expansion capabilities

Instruction Set
The 8088 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8-bit and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked

MUL TIIUS' SYSTEM IUS

143847-2

Figure 1. iSBC® 88/25 Block Diagram

3-48

iSBC® 88/25 SINGLE BOARD COMPUTER

offer a 1 megabyte addressing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses.
Each register maps 64 Kbytes at a time and activation of a specific register is controlled explicitly by
program control and is also selected implicitly by
specific functions and instructions. All Intel languages support the extended memory capability, relieving the programmer of managing the megabyte
memory space, yet allowing explicit control when
necessary.

The iSBC 88/25 Single Board Computer contains 24
programmable parallel 110 lines implemented using
the Intel 8255A Programmable Peripheral interface.
The system software is used to configure the I/O
lines in any combination of unidirectional input/output and bidirectional ports indicated in Table 1. In
order to take advantage of the large number of possible I/O configurations, sockets are provided for interchangeable 1/0 line drivers and terminators, allowing the selection of the appropriate combination
of optional line drivers and terminators with the required drive/termination characteristics.

Memory Configuration

The 24 programmable I/O lines and signal ground
lines are brought out to a 50-pin edge connector.

Parallel 110 Interface

The iSBC 88/25 microcomputer contains 4 Kbytes
of high-speed static RAM on-board. In addition, the
on-board RAM may be expanded to 12 Kbytes via
the iSBC 302 8 Kbyte RAM module which mounts on
the iSBC 88/25 board and then to 16 Kbytes by adding two 4K x 4 RAM devices in sockets on the iSBC
302 module. All on-board RAM is accessed by the
8088 CPU with no wait states, yielding a memory
cycle time of 800 ns.

Serial 1/0
A programmable communications interface using
the Intel 8251 A Universal Synchronousl Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 88/25 board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(Le., synchronous or asynchronous), data format,
control character format, parity and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun and framing error detection are all
incorporated in the USART. The RS232C compatible interface on each board, in conjunction with the
USART, provides a direct interface to RS232C compatible terminals, cassettes and asynchronous and
synchronous modems. The RS232C command
lines, serial data lines and signal ground line are
brought out to a 26-pin edge connector.

In addition to the on-board RAM, the iSBC 88/25
board has four 28-pin sockets, configured to accept
JEDEC 24/28-pin standard memory devices. Up to
64 Kbytes of EPROM are supported in 16 Kbyte increments with Intel 27128 EPROMs. The iSBC
88/25 board is also compatible with the 2716, 2732
and 2764 EPROMs allowing a capacity of 8K, 16K
and 32 Kbytes, respectively. Other JEDEC standard
pinout devices are also supported, including byte. wide static and integrated RAMs.
With the addition of the iSBC 341 MULTIMODULE
EPROM option, the on-board capacity for these devices is doubled, providing up to 128 Kbytes of
EPROM capacity on-board.

Table1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port

Lines
(qty)

Input
Latched

1
2
3

8
8
4
4

X
X

Output

Latched &
Strobed

X
X

Bidirectional

Latched

Latched &
Strobed

Control

X(1)

NOTE:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.

3-49

intJ

iSBC® 88/25 SINGLE BOARD COMPUTER

The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
I/O terminators associated with the 8255A to allow
external devices or an 8255A port to gate the timer
or to count external events. The third interval timer
in the 8253 provides the programmable baud rate
generator for the iSBC 88/25, board RS232C
USART serial port. The system software configures
each timer independently to select the desired function. Seven functions are available as shown in Table 2. The contents of each counter may be read at
any time during system operation.

Programmable Timers
The iSBC 88/25 board provides three independent,
fully programmable 16-bit interval timers/event
counters utilizing the Intel 8253 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
Table 2. Programmable Timer Functions
Function

Operation

Interrupt on
Terminal Count

When terminal count is
reached, an interrupt request
is generated. This function is
extremely useful for
generation of real-time
clocks.

Programmable
One-Shot

Output goes low upon receipt
of an external trigger edge or
software command and
returns high when terminal
count is reached. This
function is retriggerable.

Rate
Generator

Divide by N counter. The
output will go low for one
input clock cycle, and the
period from one low going
pulse to the next is N times
the input clock period.

Square-Wave
Rate Generator

Output will remain high until
one-half the count has been
completed, and go low for the
other half of the count.

Software
Triggered
Strobe

Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.

Hardware
Triggered
Strobe

Output goes low for one clock
period N counts after rising
edge counter trigger input.
The counter is retriggerable.

Event Counter

On a jumper selectable basis,
the clock input becomes an
input from the external
system. CPU may read the
number of events occurring
after the counter "window"
has been enabled or an
interrupt may be generated
after N events occur in the
system.

ISBXTM MULTIMODULETM On-Board
Expansion
Two 8-bit iSBX MULTIMODULE connectors are provided on the iSBC 88/25 microcomputer. Through
these connectors, additional on-board I/O functions
may be added. iSBX MULTIMODULES optimally
support functions provided by VLSI peripheral components such as additional parallel and serial I/O,
analog I/O, small mass storage device controllers
(e.g., cassettes and floppy disks), and other custom
interfaces to meet specific needs. By mounting directly on the Single board computer, less interface,
logic, less power, simpler packaging, higher performance, and lower cost result when compared to other
alternatives such as MULTIBUS form factor compatible boards. The iSBX connectors on the iSBC
88/25 provide all signals necessary to interface to
the local on-board bus. A broad range of iSBX MULTIMODULE options are available in this family from
Intel. Custom iSBX modules may also be designed
for use on the iSBC 88/25 board. An iSBX bus interface specification 'and iSBX connectors are available
from Intel.

MULTIBUS® SYSTEM BUS AND
MULTIMASTER CAPABILITIES
Overview
The MULTIBUS system bus is Intel's industry standard microcomputer bus structure. Both 8 and 16-bit
single board computers are supported on the MULTIBUS structure with 24 address and 16 data lines.
In its simplest application, the MULTIBUS system
bus allows expansion of functions already contained
on a single board computer (e.g., memory and digital
I/O). However, the MULTIBUS structure also allows
very powerful distributed processing configurations
with multiple processor and intelligent slave I/O, and
peripheral boards capable of solving the most demanding microcomputer applications. The MULTIBUS system bus is supported with a broad array of
board level products, LSI interface components, detailed published specifications and application notes.
3-50

intJ

iSBC® 88125 SINGLE BOARD COMPUTER

Table 3. Programmable Interrupt Mode

Expansion Capabilities

Mode
Fully Nested

Memory and I/O capacity may be expanded and additional functions added using Intel MULTIBUS compatible expansion boards. Memory may be expanded by adding user specified combinations of RAM
boards, EPROM boards, or combination boards. Input/output capacity may be added with digital I/O
and analog I/O expansion boards. Mass storage capability may be achieved by adding single or double
density diskette controllers, or hard disk controllers.
Modular expandable backplanes and cardcages are
available to support multiboard systems.

Auto-Rotating

Equal priority. Each level,
after receiving service,
becomes the lowest priority
level until next interrupt
occurs.

Specific
Priority

System software assigns
lowest priority level. Priority of
all other levels based in
sequence numerically on this
assignment.

Polled

System software examines
priority-encoded system
.interrupt status via interrupt
status register.

Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (Le.,
several CPUs and/or controllers logically sharing
system tasks through communication of the system
bus), the iSBC 88/25 board provides full MULTIBUS
arbitration control logic. This control logic allows up
to three iSBC 88/25 boards or other bus masters,
including iSBC 80 and iSBC 86 family MULTIBUS
compatible single board computers to share the system bus using a serial (daisy chain) priority scheme
and allows up to 16 masters to share the MULTIBUS
system bus with an external parallel priority decoder.
In addition to the multiprocessing configurations
made possible with multimaster capability, it also
provides a very efficient mechanism for all forms of
DMA (Direct Memory Access) transfers.

Operation
Interrupt request line priorities
fixed at 0 as highest, 7 as
lowest.

interrupt mask register of the PIC. In systems requiring additional interrupt levels, slave 8259A PICs may
be interfaced via the MULTIBUS system bus, to generate additional vector addresses, yielding a total of
65 unique interrupt levels.

Interrupt Request Generation

Interrupt Capability
The iSBC 88/25 board provides 9 vectored interrupt
levels. The highest level is the NMI (Non-Maskable
Interrupt) line which is directly tied to the 8088 CPU.
This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel 8259A
Programmable Interrupt Controller (PIC) provides .
control and vectoring for the next eight interrupt levels. As shown in Table 3, a selection of four priority
processing modes is available for use in designing
request processing configurations to match system
requirements for efficient interrupt servicing with
minimal latencies. Operating mode and priority assignments may be reconfigured dynamically via software at any time during system operation. The PIC
accepts interrupt requests from all on-board I/O resources and from the MULTIBUS system bus. The
PIC then resolves requests according to the selected mode and, if appropriate, issues an interrupt to
the CPU. Any combination of interrupt levels may be
masked via software, by storing a single byte in the

3-51

Interrupt requests to be serviced by the iSBC 88/25
board may originate from 24 sources. Table 4 includes a list of devices and functions supported by
interrupts. All interrupt signals are brought to the interrupt jumper matrix where any combination of interrupt sources may be strapped to the desired interrupt request level on the 8259A PIC or the NMI input
to the CPU directly.

Power-Fail Control and Auxiliary
Power
Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal from
the iSBC 635 and iSBC 640 Power Supply or equivalent, to initiate an orderly shut down of the system in
the event of a power failure. Additionally, an activelow TTL compatible memory protect signal is
brought out of the auxiliary connector which, when
asserted, disables read/write access to RAM memory on the board. This input is provided for the protection of RAM contents during system power-down
sequences. An auxiliary power bus is also provided
to allow separate power to RAM for systems requiring battery backup of read/write memory. Selection
of this auxiliary RAM power bus is made via jumpers
on the board.

~®

.'25 SINGLE BOARD COMPUTER

System Development C8jI8bIities

Run-Time Support

The development cycle of iSBC 88/25 products can
be significantly reduced and simplified by using the
Intellec Series IV Microcomputer Development System.

Intel also offers two run-time support packages;
iRMX 88 Realtime Multitasking Executive and the
iRMX 86 Operating System. iRMX 88 is a simple,
highly configurable and efficient foundation for
small, high performance applications. Its multitasking structure establishes a solid foundation for modular system design and provides task scheduling
and management, intertask communication and synchronization, and interrupt servicing for a variety of
peripheral devices. Other configurable options include terminal handlers, disk file system, debuggers
and other utilities. iRMX 86 is a high functional operating system with a very rich set of features and options based on an object-oriented architecture. In
addition to being modular and configurable, functions beyond the nucleus include a sophisticated file
management and 110 system, and powerful human
interface. Both packages are easily customized and
extended by the user to match unique requirements.

PLlM·86
Intel's system's implementation language, PL/M-86,
is available as an Intellec Microcomputer Development System option. PL/M-86 provides the capability to program in algorithmic language and eliminates
the need to manage register usage or allocate memory while still allowing explicit control of the system's
resources when needed.
.

Table 4. Interrupt Request Sources
Device

Function

MULTIBUS Interface

Requests from MULTIBUS resident peripherals or other
CPU boards

8255A Programmable
Peripheral Interface

Signals into buffer full or output buffer empty; also BUS
INTR OUT general purpose interrupt from driverl
terminator sockets
Transmit buffer empty and receive buffer full
Timer 0, 1 outputs; function determined by timer mode
Function determined by iSBX MULTIMODULE board

8251A USART
8253 Timers
iSBX Connectors

Indicates addressed MULTIBUS resident device has not
responded to command within 6 ms
Indicates AC power is not within tolerance
Power Fail Interrupt
Source of 120 Hz signal from poWer supply
Power Line Clock
General purpose interrupt from parallel port J1 connector
External Interrupt
iSBC 337 MULTIMODULE Indicates error or exception condition
Numeric Data Processor
Bus Fail Safe Timer

3-52

Number of
Interrupts
8; may be expanded to
64 with slave 8259A
PIC's on MULTIBUS
boards
3

2
2
4
(2 per iSBX connector)
1
1
1
1
1

iSBC® 88125 SINGLE BOARD COMPUTER

SPECIFICATIONS

ON-BOARD RAM
4 Kbytes-O-OFFFH

Word Size
Instruction-8, 16, 24, or 32 bits
Data-8 bits

WITH iSBC 302 MULTIMODULE RAM

System Clock

WITH iSBC 302 MULTIMODULE BOARD AND
TWO 4K x 4 RAM CHIPS

12 Kbytes-0-2FFFH

5.00 MHz or 4.17 MHz ± 0.1 % (jumper selectable)

16 Kbytes-0-3FFFH
NOTE:
4.17 MHz required with the optional iSBC 337 module.

1/0 Capacity
Parallel-24 programmable lines using one 8255A
Serial-1 programmable line using one 8251A
iSBX Multimodule-2 iSBX MULTIMODULE boards

Cycle Time
BASIC INSTRUCTION CYCLE

Serial Communications Characteristics

At 5 MHZ-1.2 IJ-S
-400 ns (assumes instruCtion in the
queue)

Synchronous-5 8-bit characters; internal or external character synchronization; automatic sync insertion
Asynchronous-5 8-bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit detection

NOTES:
Basic instruction cycle is defined as the fastest instruction time (Le., two clock cycles).

Memory Cycle Time

Baud Rates

RAM-800 ns (no wait states)
EPROM-Jumper selectable from 800 ns to 1400 ns

Frequency (KHz)
(Software
Baud Rate (Hz)
Selectable)
Synchronous Asynchronous
..;.16
..;.64
153.6
9600
2400
76.8
4800
1200
38.4
38400
2400
600
1200
19.2
19200
300
9.6
9600
600
150
4.8
4800
300
75
150
2.4
2400
1.76
1760
110
-

Memory Capacity I Addressing
ON-BOARD EPROM
Device
Total Capacity
2716
8 Kbytes
2732
16 Kbytes
2764
32 Kbytes
27128
64 Kbytes

Address Range
FEOOO-FFFFFH
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH

NOTES:
Frequency selected by 110 write of appropriate t6-bit frequency factor to baud rate register (8253 Timer 2).

WITH iSBC 341 MULTI MODULE EPROM
Device
2716
2732
2764
27128

Total Capacity
16 Kbytes
32 Kbytes
64 Kbytes
128 Kbytes

Address Range
FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH

NOTES:
iSBC 88/25 EPROM sockets support JEDEC 24/28-pin
standard EPROMs and RAMs (2 sockets); iSBC 341 sockets also support E2PROMs.

3-53

inter

iSBC® 88/25 SINGLE BOARD COMPUTER

Timers

CONNECTORS

, INPUT FREQUENCIES

DoubleSided Centers
(in.)
Pins
(qty)

Interface

Reference: 2.458 MHz ± 0.1 % (406.9 ns period,
nominal); or 1.229 MHz ± 0.1 % (813.8 ns period,
nominal); or 153.6 KHz ± 0.1 % (6.510 }Ls period,
nominal)

MULTIBUS
System

NOTE:
Above frequencies are user selectable.

iSBX Bus
8-Bit Data

Event Rate: 2.46 MHz max
OUTPUT FREQUENCIES/TIMING INTERVALS

Function

Min

Max

Min

Max

Real·Time
Interrupt

1.63 J.'s

427.1 ms

3.26$

466.50 min

Programmable
One-Shot

1.63 J.'s

427.1 ms

3.26s

466.50 min

Rate
Generator

2.342 Hz

613.5 KHz

0.000036 Hz

306.8 KHz

Square-Wave
Rate
Generator

2.342 Hz

613.5 KHz

0.000036 Hz

306.8 KHz

Software
Triggered
Strobe

1.63 J.'s

427.1 ms

3.26s

466.50 min

Hardware
Triggered
Strobe

1.63 J.'s

427.1 ms

3.26s

466.50 min

2.46 MHz

Event
Counter

0.156

Viking
3KH43/9AMK12
Wire Wrap

0.1

iSBX960-5

Parallel 110
(2)

0.1

3M 3415-000 Flat
or
TI H312125 Pins

Serial I/O

0.1

3M 3462-0001
Flat or
AMP 88106-1 Flat

Dual
Timer/Counter
(Two Timers
Cascaded)

Single
Timer/Counter

Mating
Connectors

Line Drivers and Terminators
I/O Drivers: The following line drivers are all compatible with the I/O driver sockets on the iSBC 88/
25 board.

Driver

Characteristics

Sink Current (mA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTES:
I = inverting; NI

non-inverting; OC

open collector.

Interfaces

Port 1 of the 8255A has 32 mA totem-pole bidirec- ,
tional drivers and 100 terminators..

Multibus: All signals TTL compatible

liD Terminators: 2200/3300 divider or 1 KO pull up.

iSBX Bus: All signals TTL compatible

2200/3300 Option 1

Parallel I/O: All signals TTL compatible
2200

Serial I/O: RS232C compatible, configurable as a
data set or data terminal

+5V

Timer: All signals TTL compatible

;;

0
143847-3

Interrupt Requests: All TTL compatible
1KO Option 2

3-54

iSBC® 88/25 SINGLE BOARD COMPUTER

MULTIBUS Drivers
Function
Data
Address
Commands
Bus Control

Environmental Characteristics

Characteristic
Tri-State
Tri-State
Tri-State
Open Collector

Sink Current (rnA)

Operating Temperature: O°C to 55°C

32
24
32
20

Relative Humidity: to 90% (without condensation)

Reference Manual
143825-001-iSBC 88/25
Manual (NOT SUPPLIED)

Physical Characteristics
Width: 12.00 in. (30.48 cm)

Depth: 0.70 in. (1.78 cm)
Weight: 14 oz. (388 gm)

ORDERING INFORMATION

Electrical Characteristics
DC POWER REQUIREMENTS

Without EPROM(I)
RAM only(2)
With 8K EPROM(3)
(using 2716)
With 16K EPROM(3)
(using 2732)
With 32K EPROM(3)
(using 2764)

Reference

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

Height: 6.75 in. (17.15 cm)

Configuration

Hardware

Current Requirements
(All Voltages ±5%)
-12V
+5V
+12V
3.8A

25mA

23 rnA

104 rnA
4.3A

25 rnA

23 rnA

4.4A

25mA

23 rnA

4.4A

25 rnA

23 rnA

NOTES;
1. Does not include power for optional ROM/EPROM, I/O
drivers and I/O terminators.
2. RAM chips powered via auxiliary power bus in powerdown mode. Does not include power for optional RAM.
3. Includes power required for 4 ROM/EPROM chips, and
1/0 terminators installed for 16 1/0 lines; all terminator inputs low.

3-55

Part Number

Description

SBC 88/25

8-bit Single Board Computer
with 4 Kbytes RAM

iSBC® 88/40A
MEASUREMENT AND CONTROL COMPUTER
High Performance 4.8/6.67 MHz 8088
• 8-Blt
HMOS Processor
12-Blt KHz Analog-to-Digital Converter
•. with Programmable Gain Control.

•
•

16-Bit Differential/32 Single-Ended
Analog Input Channels
Three iSBXTM MULTIMODULETM
Connectors for Analog, Digital, and
other I/O Expansion

4K Bytes Static RAM, Expandable via
• iSBC®
301 MULTIMODULETM RAM to
8K Bytes (1K Byte Dual-Ported)
Sockets for up
• toFour64KEPROM/E2PROM
Bytes, Expandable to
128K Bytes with iSBC® 341 Expansion
MULTIMODULETM

•

MULTIBUS® Intelligent Slave or
Multimaster

The Intel iSBC 88/40A Measurement and Control Computer is a member of Intel's large family of Single Board
Computers that takes full advantage of Intel's VLSI technology to provide an economical self-contained
computer based solution for applications in the areas of process control and data acquisition. The on-board .
8088 processor with its powerful instruction set allows users of the iSBC 88/40A board to update process
loops as much as 5-10 times faster than previously possible with other 8-bit microprocessors. For example,
the high performance iSBC 88/40A can concurrently process and update 16 control loops in less than 200
milliseconds using a traditional PID (Proportional-Integral-Derivative) control algorithm. The iSBC 88/40A
board consists of a 16 differential/32 single ended channel analog multiplexer with input protected circuits,
AID converter, programmable central processing unit, dual port and private RAM, read only memory sockets,
interrupt logic. 24 channels of parallel 110, three programmable timers and MULTIBUS control logic on a single
6.75 by 12.00-inch printed circuit card. The iSBC 88/40A board is capable of functioning by itself in a standalone system or as a multimaster or intelligent slave in a large MULTIBUS system.
.

280220-1

3-56

October 1986
Order Number: 280220-001

iSBC® 88/40A COMPUTER

FUNCTIONAL DESCRIPTION

iSBC 88/40 boards or other single board computer
masters or intelligent slaves.

Three Modes of Operation

Intelligent Slave

The iSBC 88/40A Measurement and Control Computer (MACC) is capable of operating in one of three
modes: stand-alone controller, bus multimaster or
intelligent slave. A block diagram of the iSBC
88/40A Measurement and Control Computer is
shown in Figure 1.

The iSBC 88/40A board can perform as an intelligent slave to any Intel 8- or 16-bit MULTIBUS master CPU by not only offloading the master of the analog data collection, but it can also do a significant
amount of pre-processing and decision-making on
its own. The distribution of processing tasks to intelligent slaves frees the system master to do other
system functions. The Dual port RAM with flag bytes
for signaling allows the iSBC 88/40A board to process and store data without MULTIBUS memory or
bus contention.

Stand·Alone Controller
The iSBC 88/40A Measurement and Control Computer may function as a stand-alone single board
controller with CPU, memory and I/O elements on a
single board. The on-board 4K bytes of RAM and up
to 64K bytes of read only memory, as well as the
analog-to-digital converter and programmable parallel I/O lines allow significant control and monitoring
capabilities from a single board.

Bus Multimaster
In this mode of operation the iSBC 88/40A board
may interface and control a wide variety of iSBC
memory and I/O boards or even with additional

MULTIBUS'~

Central Processing Unit
The central processor unit for the iSBC 88/40A
board is a powerful 8-bit HMOS 8088 microprocessor. By moving on-board jumpers, the user can select either a 4.8 or 6.67 MHz CPU clock rate. The
iSBC 88/40A board can also run at 8 MHz by changing the CPU clock oscillator to a 24 MHz unit. For 8
MHz operation, the iSBC 88/40A board should either be the only MULTIBUS master in the system or
'be an intelligent slave that never directly accesses
the MULTIBUS interfa.ce.

SYSTEM BUS

LOCAL BUS

r---"'--..c.,
8088 CPU

STATiC RAM

4.IfB.67MHl
(8 MHz OPT.)

c....,------I
:
8087 NUMERIC
I DATA PROCESSOR
I
EXPANSION
r--=~~l

..,
I
:
I
I

_________ J
ISBell7

USER
BATTERY
BACKUP

3K (8185A)

. . . .------'1
4KRAM

EXPANSiON

I
I

L. _________ ..J
ISSC 301

PORT B SOCKETS
24

ANALOG INPUTS

ACCEPT 55V, 300 mA
L1NEORIYERS

Jl
PARALLEL DIGITAL 110

':-r-------'
ADDITIONAL FOUR
28·PIN SOCKETS

,
lI
I

I
I
~----------....I
ISBe341

Figure 1. iSBC® 88/40A Measurement and Control Computer Block Diagram

3-57

280220-2

intJ

iSBC® 88/40A COMPUTER

INSTRUCTION SET-The 8088 instruction repertoire includes variable length instruction format (including double operand instructions), 8cbit and 16-bit
signed and unsigned arithmetic operators for binary,
BCD and unpacked ASCII data, and iterative word
and byte string manipulation functions. The instruction set of the 8088 is a superset of the 8080Al
8085A family and with available software tools, programs written for the 8080Al8085A can be easily
converted and run on the 8088 processor. Programs
can also be run that are implemented on the 8088
with little or no modification.

TIMODULE RAM is added to the protected RAM.
The MULTIBUS port base address of the dual-port
RAM can be jumpered to any 1K byte boundary in
the 1M byte address space. The dual-port RAM can
be accessed in a byte-wide fashion from the MULTIBUS system bus. When accessed from the MULTIBUS system bus, the dual-port RAM decode logic
will generate INH1/ (Inhibit RAM) to allow dual-port
RAM to overlay other system RAM. The dual-port
control logic is designed to favor an on-board RAM
access. If the dual-port is not currently performing a
memory cycle for the MULTIBUS system port, only
one wait state will be required. The on-board port
any require more than one wait state if the dual-port
RAM was busy when the on-board cycle was requested. The LOCK prefix facility of the iAPX 88/10
assembly language will disallow system bus accesses to the dual-port RAM. In addition, the. on-board
port to the dual-port RAM can be locked by other
compatible MULTIBUS masters, which allows true
symmetric semaphore operation. When the board is
functioning in the master mode, the LOCK prefix will
additionally disable other masters from obtaining the
system bus.

ARCHITECTURAL FEATURE5-A 4-byte instruction queue provides pre-fetching of sequential instructions and can reduce the 1.04 ms minimum instruction cycle to 417 ns (at 4.8 MHz clock rate) for
queued instructions. The stack oriented architecture
facilitates nested subroutines and co-routines, reentrant code and powerful interrupt handling. The
memory expansion capabilities offer a 1 megabyte
addressing range. The dynamic relocation scheme
allows ease in segmentation of pure procedure and
data for efficient memory utilization. Four segment
registers (code,stack, data, extra) contain program
loaded offset values which are used to map 16-bit
addresses to 20-bit addresses. Each register maps
64K bytes at a time and activation of a specific regis~
ter is controlled explicitly by program control and is
also selected implicitly by specific functions and instructions.

PRIVATE RAM-In addition to the 1K byte dual-port
RAM, there is a 3K byte section of private static
RAM not accessible from the system bus. This RAM
has a base address of 00000, and consists of three
Intel 8185 RAM chips which are interfaced to the
multiplexed address/data bus of the 8088 microprocessor. Expansion of this private RAM from 3K to
7K byte scan be accomplished by the addition of an
iSBC 301 MULTIMODULE RAM (4K bytes). When
the 301 is added, protected RAM extends from 0 to
7K, and the base address of the dual-port RAM is
relocated from 3K (OOCOO) to 7K (01 COO). All protected RAM accesses require one wait state. The
private RAM resides on the local on-board bus,
which eliminates contention problems between onboard accesses to private RAM and system bus accesses to dual-port AM. The private RAM can be
battery backed (up to 16K bytes).

Bus Structure
The iSBC 88/40A single board computer has three
buses: 1) an internal bus for communicating with one
board memory,analog-to-digital converter, ISBX
MULTIMODULES and I/O options; 2) the MULTIBUS system bus for referencing additional memory
and I/O options, and 3) the dual-port bus which allows access to RAM from the on-board CPU and the
MULTIBUS system bus. Local (on-board) accesses
do not require MULTIBUS communication, making
the system bus available for use by other MULTIBUS masters (Le., DMA devices and other single
board computers transferring to additional system
memory). This feature allows true parallel processing in a multiprocessor environment. In addition, the
MULTIBUS interface can be used for system expansion through the use of .other 8- and 16-bit iSBC
computers, memory and I/O expansion boards.

Additional RAM can be added by utilizing JEDECcompatible static RAMs in the available EPROM
sockets.

Parallel 1/0 Interface
The iSBC 88/40A single board computer contains
24 programmable parallel I/O lines implemented using the Intel 8255A Programmable Peripheral Interface. The system software is used to configure the
I/O lines in any combination of unidirectional input/
output and bidirectional ports indicated ,in Table 1.
There the I/O interface may be customized to meet
specific peripheral requirements. In order to take full
advantage of the large number of possible I/O

RAM Capabilities
DUAL-PORT RAM-The dual-port RAM of the iSBC
88/40A board consists of 1K bytes of static RAM,
implemented with Intel 2114A chips. The on-board
base address of this RAM is OOCOO (3K) normally; it
is relocated to 01COO (7K) when the iSBC 301 MUL3-58

intJ

iSBC® 88/40A COMPUTER

configurations, sockets are provided for interchangeable 110 line drivers and terminators. Port 2
can also accept TTL compatible peripheral drives,
such as 75461/462, 75471/472, etc. These are
open collector, high voltage drivers (up to 55 volts)
which can sink 300 mA. Hence, the flexibility of the
I/O interface is further enhanced by the capability of
selecting the appropriate combination of optional
line drivers and terminators to provide the required
sink current, polarity, and drive/termination characteristics for each application. The 24 programmable
I/O lines and signal ground lines are brought out to a
50-pin edge connector that mates with flat, woven,
or round cable. This edge connector is also compatible with the Intel ICSTM 920 Digital I/O and iCS 930
AC Signal Conditioning/Termination Panels, for field
wiring, optical isolation and high power (up to 3 amp)
power drive.

Timing Logic
The iSBC 88/40A board provides an 8254-2 Programmable Interval Timer, which contains three·
independent, programmable 16-bit timers/event
counters. All three of these counters are available to
generate time intervals or event counts under software control. The outputs of the three counters may
be independently routed to the interrupt matrix. The
inputs and outputs of timers 0 and 1 can be connected to parallel I/O lines on the J1 connector, where
they replace 8255A port C lines. The third counter is
also used for timing E2PROM write operations.

Interrupt Capability
The iSBC 88/40A board provides 9 vectored interrupt levels. The highest level is NMI (Nonmaskable
Interrupt) line which is directly tied to the 8088 CPU.
This interrupt cannot be inhibited by software and is
typically used for signalling catastrophic events (Le.,
power failure). On servicing this interrupt, program
control will be implicitly transferred through location
00008H. The Intel 8259A Programmable Interrupt
Controller (PIC) provides vectoring for the next eight
interrupt levels. As shown in Table 2, a selection of
four priority processing modes is available to the designer to match system requirements. Operating
mode and priority assignments may be reconfigured
dynamically via software at any time during system
operation. The PCI accepts interrupt requests from
the programmable parallel and/or iSBX interfaces,
the programmable timers, the system bus, or directly
from peripheral equipment. The PIC then determines
which of the incoming requests is of the highest pri,
ority than the level currently being serviced, and, if
appropriate, issues an· interrupt to the CPU. Any
combination of interrupt levels may be masked, via
software, by storing a single byte in the interrupt
make register of the PIC. The PIC generates a

EPROM Capabilities
Four 28-pin sockets are provided for the use of Intel
2716s, 2732s, 2764s, 27128s, future JEDEC-compatible 128K and 256K bit EPROMs and their respective ROMs. When using 27128s the on-board
EPROM capacity is 64K bytes. Read only memory
expansion is available through the use of the
iSBC 341 EPROM/ROM memory expansion MULTIMODULE. When the iSBC 341 is used an additional
four EPROM sockets are made available, for a total
iSBC 88/40A board capacity of 128K bytes EPROM
with Intel 27128s.

E2PROM Capabilities
The four 28-pin sockets can also accommodate Intel
2817A or 2816A E2PROMs, for dynamic storage of
control loop setpoints, conversion parameters, or
other data (or programs) that change periodically but
must be kept in nonvolatile storage.

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port

Lines
(qty)

Input
Latched

Output

Latched &
Strobed

Latched

Bidirectional

Control

Latched &
Strobed

X(1)

NOTE:
1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.

3-59

inter

iSBC® 88/40A COMPUTER

unique memory address for each interrupt level.
These addresses are equally spaced at 4-byte intervals. This 32-byte lock may begin at any 32-byte
boundary in the lowest 1K bytes of memory, and
contains unique instruction pointers and code segment offset values (for expanded memory operation)
for each interrupt level. After acknowledging an interrupt and obtaining advice identifier byte from the
8259A PIC, the CPU will store its status flags on the
stack and execute an indirect CALL instruction
through the vector location (derived from the device
identifier) to the interrupt service routine.

Power-Fail Control
Control logic is also included to accept a power,fail
interrupt in conjunction with the AC-Iow signal from
the iSBC 635, iSBC 640, and iCS 645 Power Supply
or equivalent.

iSBXTM MULTIMODULETM Expansion'
Capabilities
Three iSBX MULTIMODULE connectors are provided on the iSBC 88/40A board. Up to three single
wide MULTIMODULE or one double wide and one
single wide iSBX MULTIMODULE can be added to
the iSBC 88/40A board. A wide variety of peripheral
controllers, analog and digital expansion options are
available. For more information on specific iSBX
MULTIMODULES consult the Intel OEM Microcomputer System Configuration Guide.

NOTE:
The first 32 vector locations are reserved by Intel
for dedicated vectors. Users who wish to maintain
compatibility 'With present and future Intel products
should not use these locations for user-defined
vector addresses.
Table 2. Programmable Interrupt Modes
Mode
Fully Nested
Auto-rotating

Operation
Interrupt request line priorities
fixed at 0 as highest, 7 as lowest.
Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.

Specific
Priority

System software assigns lowest
priority level. Priority of all other
levels based in sequence
numerically on this assignment.

Polled

System software examines priorityencoded system interrupt status
via interrupt status register.

Processing Expansion Capabilities
The addition of a iSBC 337 Multimodule Numeric
Data Processor offers high performance integer and
floating point math functions to users of the iSBC
88/40A board. The iSBC 337 incorporates the Intel
8087 and because of the MULTIMODULE implementation, it allows on-board expansion directly on
the iSBC 88/40A board, eliminating the need.for additional boards or floating point requirements.

MULTIBUS® Expansion
Memory and 1/0 capacity may be expanded further
and additional functions added using Intel MULTIBUS compatible expansion boards. Memory may be
expanded by adding user specified combination of
RAM boards, EPROM boards, or memory combination boards. Input/output capacity may be increased
by adding digital 1/0 and analog 1/0 MULTIBUS expansion boards. Mass storage capability may be
achieved by adding single or double density diskette
controllers, or hard disk controllers either through
the use of expansion boards and iSBX MULTIMODULES. Modular expandable backplanes and cardcages are available to support multiboard systems.

INTERRUPT REQUEST GENERATION-Interrupt
requests may originate from 26 sources. Two jumper
selectable interrupt requests can be' automatically
generated by the programmable peripheral interface
when a byte of information is ready to be transferred
to the CPU (Le., input buffer is full) or a byte of information has been transferred to a peripheral device
(Le" output buffer is empty). A jumper selectable request can be generated by each of the programmable timers. An additional interrupt request line may
be jumpered directly from the parallel 1/0 driver terminator section. Eight prioritized interrupt request
lines allow the iSBC 88/40A board to recognize and
service interrupts originating from peripheral boards
interfaced via the MULTIBUS system bus. The fail
safe, timer can be selected as an interrupt source.
Also, interrupts are provided from the iSBX connectors (6), end-of-conversion, PFIN and from the power line clock.

NOTE:
Certain system restrictions may be incurred by the
inclusion of some of the iSBC 80 family options in
an iSBC 88/40 system. Consult the Intel OEM Microcomputer System Configuration Guide for specific data.

Analog Input Section
The analog section of the iSBC 88/40A board receives all control signals through the local bus to
3-60

inter

iSBC® 88/40A COMPUTER

initiate channel selection, gain selection, sample and
hold operation, and analog-to-digital conversion.
See Figure 2.
INPUT CAPACITY-32 separate analog signals
may be randomly or sequentially sampled in singleended mode with the 32 input multiplexers and a
common ground. For noisier environments, differential input mode can be configured to achieve 16 separate differential signal inputs, or 32 pseudo differential inputs.
RESOLUTION-The analog section provides 12-bit
resolution with a successive approximation analogto-digital converter. For bipolar operation (- 5 to + 5
or -10 to + 10 volts) it provides 11 bits plus sign.
SPEED-The A-to-D converter conversion speed is
50 /Ls (20 kHz samples per second). Combined with
the programming interface, maximum throughput via
the local bus and into memory will be 55 microseconds per sample, or 18 kHz samples per second, for
a single channel, a random channel, or a sequential
channel scan at a gain of 1, 5 ms at a gain of 5,250
ms at a gain of 50, and 20 ms at a gain of 25.0. A-toD conversion is initiated via a programmed command from the 8088 central processor. Interrupt on
end-of-conversion is a standard feature to ease programming and timing constraints.
ACCURACY-High quality components are used to
achieve 12 bits resolution and accuracy of 0.035%
full scale range ± % LSB at gain = 1. Offset is adjustable under program control to obtain a nominal
± 0.024 % FSR ± % LSB accuracy at any fixed temperature between O°C and 60°C (gain = 1). See
specifications for other gain accuracies.

made configurable via user program commands up
to 250 x (20 millivolts full scale input range). User
can select gain ranges of 1 (5V), 5 (1 V), 50
(100 mY), 250 (20 mY) to match his application.
OPERATIONAL DESCRIPTION-The iSBC 88/40A
single board computer addresses the analog-to-digital converter by executing IN or OUT instructions to
the port address. Analog-to-digital conversions can
be programmed in either of two modes: 1) start conversion and poll for end-of-conversion (EOG), or 2)
start conversion and wait for interrupt at end of conversion. When the conversion is complete as signaled by one of the above techniques, INput instructions read two bytes (low and high bytes) containing
the 12-bit data word.
Output Command-Select input channel and start
conversion.
GAIN

BIT POSITION

CONNECTOR

CHANNEL SELECT

1...JIc..G_2...l.1_..J..I_J--L1_C3_I c_2-,I_c_1. J.1_C--,OI

INPUT CHANNELlL G_

Input Data-Read converted data (low byte) or
Read converted data (high byte).
DATA

~
BIT POSITION
LOW/STATUS BYTE

I 03 I 02 I 01 I DO I

IEDCI

DATA

HIGH BYTE

I011 I 010 I 09 I DB I 07 I 06 I 05 I 04 I

GAIN-To allow sampling of millivolt level signals
such as strain gauges and thermocouples, gain is
LOCAL
BUS

HIGH
IMPEDANCE
BUFFER

AMP
16 CHANNEL

INPUT
MUl TlPLEXER
PROGRAMMABLE
GAIN SELECT
& OFFSET
ADJUST

ANALOG
INPUT
SIGNALS

16 CHANNEL

INPUT
MUL TlPlEXER

G~lg~:~--4~"

PSEUDO DIFFERENTIAL GROUND

280220-3

Figure 2. iSBC® 88/40 Analog Input Section
.
3-61

inter

iSBC® 88/40A COMPUTER

Offset Correction-At higher gains (X 50, x 250)
the voltage offset tempco in the AID circuitry can
sometimes cause unacceptable inaccuracies. To
correct for this offset, one channel can be dedicated
to be used as a reference standard. This channel
can be read from the program to. determine the
amount of offset. The reading from this channel will
then be subtracted from all other channel readings,
in effect eliminating the offset tempco.

MEMORY ADDRESSING
On-Board ROM/EPROM
FEOOO-FFFFF (using 2716· EPROMs)
FCOOO-FFFFF (using 2732 EPROMs)
F8000-FFFFF (using 2764 EPROMs)
FOOOO-FFFFF (using 27128 EPROMs)

SYSTEM SOFTWARE DEVELOPMENT

On-Board ROM/EPROM (With iSBC 341
MULTIMODULE EPROM option installed)

The development cycle of the iSBC 88/40 board
may be significantly reduced using an Intel Intellec
Microcomputer Development System and Intel's
FORTRAN, PASCAL, or PL/M 86/88 Software
packages.

FCOOO-FFFFF (using 2716 EPROMs)
F8000-FFFFF (using 2732 EPROMs)
FOOOO-FFFFF (using 2764 EPROMs)
EOOOO-FFFFF (using 27128 EPROMs)
On-Board RAM (CPU Access)

SPECIFICATIONS

OOOOO-OOFFF
00000-01 FFF (if iSBC 301 MULTIMODULE RAM option installed)

Word Size
Instruction-8, 16, or 32 bits
Data-8 bits

On-Board RAM
Jumpers allow 1K bytes of RAM to act as slave RAM
for access by another bus master. Addressing may
be set within any 1K boundary in the 1-megabyte
system address space.

Instruction Cycle Time (minimum)
8088 Clock Rate

Instruction

4.8 MHz 6.67 MHz 8.0 MHz
In Queue
417 ns
Not in Queue 1.04 ns

300 ns
750 ns

250 ns
625 ns

Number of
Clock Cycles
2
5

Slave RAM Access
Average: 350 ns

MEMORY CAPACITY

INTERVAL TIMER

On-Board ROM/EPROM/E2PROM

Output Frequencies

Up to 64K bytes; user installed in 2K, 4K, BK or 16K
byte increments or up to 12BK if iSBC 341 MULTIMODULE EPROM option installed. Up to 8K bytes of
E2PROM using Intel 2816As or 2817As may be
user-installed in increments of 2, 4, or 8 bytes.

Single Timer

Function
Real-Time
InterrUpt
Interval

On-Board RAM

Min

Max

0.977 J.ls

64ms

Dual Timers
(Two Timers
Cascaded)
69.9 minutes
maximum

Rate
15.625 Hz 1024 KHz 0.00024 Hz
Generator
minimum
(Frequency

4K bytes or 8K bytes if the iSBC 301 MULTIMODULE RAM is installed. Integrity maintained during
power failure with user-furnished batteries. 1K bytes
are dual-ported.
Off-Board Expansion

CPU CLOCK

Up to 1 megabyte of user-specified combination of
RAM, ROM, and EPROM.

4.8 MHz ± 0.1 % or 6.67 MHz
able via jumpers);

± 0.1 %.

(User select-

8.0 MHz (with user installed 24 MHz oscill!3-tor)
3-62

iSBC® 88/40A COMPUTER

110 Addressing

Gain TC (at gain = 1)-30 PPM (typical), 56 PPM
(max) per degree centigrade, 40 PPM at other gains.

All communications to parallel I/O ports, iSBX bus,
A/D port, timers, and interrupt controller are via read
and write commands from the on-board 8088 CPU.

OffsetTC(in % of FSRrC)

Gain
1

Offset TC (typical)
0.0018%
0.0036%
0.024%
0.12%

5
50
250

Interface Compatability

Sample and Hold-Sample Time: 15 '""S
Aperature-Hold Aperature Time: 120 ns
Input Overvoltage Protection: 30 volts
Input Impedance: 20 megohms (min.)
Conversion Speed: 50 ,""S (max.) at gain = 1
Common Mode Rejection Ratio: 60 dB (min.)

Parallel 1/0-24 programmable lines (8 lines per
port); one port includes a bidirectional bus driver. IC
sockets are included for user installation of line drivers and/or I/O terminators and/or peripheral drivers
as required for interface ports.

Interrupts

Physical Characteristics

8088 CPU includes a non-maskable interrupt (NMI).
NMI interrupt is provided for catastrophic events
such as power failure. The on-board 8259A PIC provides 8-bit identifier of interrupting device to CPU.
CPU multiplies identifier by four to derive vector address. Jumpers select interrupts from 26 sources
without necessity of external hardware. PIC may be
programmed to accommodate edge-sensitive or level-sensitive inputs.

Width: 30.48 cm (12.00 in.)
Length: 17.15 cm (6.75 in.)
Height: 1.78 cm (0.7 in.)
2.82 cm (1.13 in.) with iSBC Memory Expansion, MULTIMODULES, iSBX Numeric Data
Processor or iSBX MULTIMODULES.

Electrical Requirements

Analog Input

Power Requirements

16 differential (bipolar operation) or 32 single-ended
(unipolar operation).

Current

Voltage

Full Scale Voltage Range--5 to +5 volts (bipolar), 0 to + 5 volts (unipolar).

+5V
+5VAux
+12V
-12V

NOTE:
Ranges of 0 to 10V and ± 10V achievable with externally supplied ± 15V power.

Maximum

Typical

5.5A
150mA
120 mA
40mA

4A
100 mA
80mA
30mA

NOTES:

Gain-Program selectable for gain of 1, 5, 50, or
250.

1. The current requirement includes one worst case (active-standby) EPROM current.
2. If + 5V Aux is supplied by the iSBC 88/40A board, the
total + 5V current is the sum of the + 5V and the + 5V
Aux.

Resolution-12 bits (11 bits plus sign for ± 5, ± 10
volts).
Accuracy-Including noise and dynamic errors.
Gain

25°C

1
5
50
250

±0.035% FSR*
±0.06%FSR*
±0.07% FSR*
±0.12% FSR*

Environmental Requirements
Operating Temperature: 0° to +60°C with 6 CFM
min. air flow across board
Relative Humidity:

NOTE:

to 90% without condensation

Equipment Supplied

FSR = Full Scale Range ± '12 LSB. Figures are in percent
of full scale reading. At any fixed temperature between O'C
and 60'C, the accuracy is adjustable to ± 0.05% of full
scale.

iSBC 88/40A Measurement and Control Computer
Schematic diagram

3-63

intJ

iSBC® 88/40A COMPUTER

REFERENCE MANUALS

ORDERING INFORMATION

147049-001- SBC 88/40A Measurement and Control Computer Hardware Reference
Manual (Order Separately).

Part Number Description
SBC 88/40A Measurement and Control Computer

Manuals may be ordered from an Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

3-64

iSBC® 86/05A
SINGLE BOARD COMPUTER

•

Programmable Synchronous/
• Asynchronous
RS232C Compatible

8086/10 (8086-2) Microprocessor with 5
or 8 MHz CPU Clock

Serial Interface with Software
Selectable Baud Rate

Software Compatible with 8086, 8088,
• 80186,80286
Based 16-bit Single Board

•

Computers
8086/20 Numeric Data
• Optional
Processor with iSBC® 337 A

Programmable 16-Bit BCD or
• Two
Binary Timers/Event Counters
Levels of Vectored Interrupt Control,
• 9Expandable
to 65 Levels
MULTIBUS® Bus Interface for
• Multimaster Configurations and System

MULTIMODULETM Processor
8K bytes of Static RAM; Expandable
• On-Board
to 16K Bytes

•
•

24 Programmable Parallel 110 Lines

Sockets for up to 256K Bytes of JEDEC
24/28-Pin Standard Memory Devices;
Expandable On-Board to 512K Bytes

Expansion

•

Two iSBXTM Bus Connectors

Supported by a Complete Family of
Single Board Computers, Memory,
Digital and Analog 110, Peripheral
Controllers, Packaging and Software

The iSBC 86/05A Single Board Computer is a member of Intel's complete line of OEM microcomputer systems which take full advantage of Intel's technology to provide economical, self-contained, computer-based
solutions for OEM applications. The iSBC 86/05A board is a complete computer system on a single 6.75 x
12.00 in. printed circuit card. The CPU, system clock, read/write memory, nonvolatile read only memory, I/O
ports and drivers, serial communications interface, priority interrupt logic and programmable timers, all reside
on the board. The large control storage capacity makes the iSBC 86/05A board ideally suited for control-oriented applications such as process control, instrUmentation, industrial automation, and many others.

143325-1

3-65

September 1987
Order Number: 143325-003

iSBC® 8S/05A SINGLE BOARD COMPUTER

FUNCTIONAL DESCRIPTION

Memory Configuration
The iSBG86/05A microcomputer contains 8K bytes
of high-speed 8K x 4 bit static RAM on-board. In
addition, the above on-board RAM may be expanded to 16K bytes with the iSBC 302 MULTIMODULE
RAM option which mounts on the iSBC 86/05A
board. All on-board RAM is accessed by the 8086-2
CPU with no wait states, yielding a memory cycle
time of 500 ns.

Central Processing Unit
The central processor for the iSBC 86/05A board is
Intel's iAPX 86/10 (8086-2) CPU. a clock rate of 8
MHz is supported with a jumper selectable option of
5 MHz. The CPU architecture includes four 16-bit
byte addressable data registers, two 16-bit memory
base pointer registers and two 16-bit index registers.
All are accessed by a total of 24 operand addressing
modes for comprehensive memory addressing and
for support of the data structures required for today's structured, high level languages as well as assembly language.

The iSBC 86/05A board also has four 28:pin, 8-bit
wide (byte-wide) sockets, configured to accept
JEDEC 24/28-pin standard memory devices. Up to
256K bytes of EPROM are supported in 64K byte
increments with Intel 27512 EPROMs. The iSBC
86/05A board also supports 2K x 8, 4K x 8, 8K x 8,
16K x 8 and 32K x 8 EPROM memory devices.
These sites also support 2K x 8 and 8K x 8 bytewide static RAM (SRAM) devices and iRAM devices,
yielding up to 32K bytes of SRAM in 8K byte increments on the baseboard.

Instruction Set
The 8086 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8- and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manipulation functions.

When the addition of the iSBC 341 MULTIMODULE
EPROM option, the on-board capacity for these devices is doubled, providing up to 512K bytes of
EPROM and 64K bytes of byte-wide SRAM capacity
on-board.

For enhanced numerics processing capability, the
iSBC 337A MULTIMODULE Numeric Data Processor extends the iAPX 86/10 architecture and data
set: Over 60 numeric instructions offer arithmetic,
trigonometric, transcendental, logarithmic and exponential instructions. Supported data types include
16-, 32-, and 64-bit integer, and 32- and 64-bit floating point, 18-digit packed BCD and 80-bit temporary.

Parallel 1/0 Interface
The iSBC 86/05A Single Board Computer contains
24 programmable parallel I/O lines implemented using the Intel 8255A Programmable Peripheral Interface. The system software is used to configure the
I/O lines in any combination of unidirectional input/output and bidirectional ports indicated in Table
1. In order to take advantage of the large number of
possible I/O configurations, sockets are provided for
interchangeable I/O line drivers and terminators, allowing the selection of the appropriate combination
of optional line drivers and terminators with the required drive/termination characteristics. The 24 programmable I/O lines and signal ground lines are
brought out to a 50-pin edge connector.

Architectural Features
A 6-byte instruction queue provides pre-fetching of
sequential instructions and can reduce the 740 ns
minimum instruction cycle to 250 ns for queued instructions. The stack-oriented architecture readily
'supports modular programming by facilitating fast,
simple, inter-module communication, and other programming constructs needed for asynchronous realtime systems. The memory expansion capabilities
offer a 1 megabyte addreSSing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses.
Each register maps 64K, bytes at a time with activation of a specific register controlled explicity by program control and selected implicity by specific functions and instructions. All Intel languages support
the extended memory capability, relieving the programmer of managing the megabyte memory space
yet allowing explicit control when necessary.

Serial 1/0
A programmable' communications interface using
the Intel 8251 A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 86/05A board. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(Le., synchronous or asynchronous), data format,
control character format, parity, and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun, and framing error detection are all
3-66

iSBC® 86/05A SINGLE BOARD COMPUTER

OK BYTES RAM
(iSBC· 302)
(4x2168) -

,
I

III

I
L.
________ .J

ISBC· 337A
NUMERIC

PRO~~:SOR

L. __ ..!81!!L __ J

MULTI BUS· SYSTEM BUS

143325-2

Figure 1. iSBC® 86/05A Block Diagram
incorporated in the USART. The RS232C compatible .interface in conjunction with the USART, provides a direct interface to RS232C compatible terminals, cassettes, and asynchronous/ synchronous
modems. The RS232C command lines, serial data
lines and signal ground line are brought out to a 26pin edge connector.

or to count external events. The third interval timer
in the 8254 provides the programmable baud rate
generator for the iSBC 86/05A .board RS232C
USART serial port. The system software configures
each timer independently to select the desired function. Seven functions are available as shown in Table 2. The contents of each counter may be read at
any time during system operation.

Programmable Timers

iSBXTM MULTIMODULETM On-Board
Expansion

The iSBC 86/05A board provides three independent, fully programmable 16-bit interval timers/event
counters utilizing .the Intel 8254 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the
I/O terminators associated with the 8255A to allow
external devices or an 8255A port to gate the timer

Two 8/16-bit iSBX MULTIMODULE connectors are
provided . on the iSBC 86/05A microcomputer.
Through these connectors, additional on-board I/O
and memory functions may be added. iSBX MULTIMODULE boards support functions such as additional parallel and serial I/O, analog I/O, mass storage
device controllers (e.g., cassettes and floppy disks),
BITBUSTM controllers, bubble memory, and other
custom interfaces to meet specific needs. By mounting directly on the single board computer, less inter3-67

iSBC® 86/05A SINGLE BOARD COMPUTER

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port

Lines
(qty)

Input

a
a

4
4

Control
Bidirectional

Latched

2
3

Output

x
x

Latched
& Strobed

Latched

x
x

Latcched
& Strobed

NOTE:

1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.

Table 2. Programmable Timer Functions
Function

Operation

Interrupt on
Terminal Count

When Terminal Count is Reached, an Interrupt Request is Generated. This Function
is Extremely Useful for Generation of Real-Time Clocks.

Programmable
One-Shot

Output Goes Low upon Receipt of an External Trigger Edge or Software Command
and Returns High when Terminal Count is Reached; This Function is Retriggerable.

Rate Generator

Divide by N Counter. The Output will go Low for One Input Clock Cycle, and the
Period from One Low Going Pulse to the Next is N Times the Input Clock Period.

Square-Wave
Rate Generator

Output will Remain High Until One-Half the Count has been Completed,and go Low
for the Other Half of the Count.

Software
Triggered Strobe

Output Remains High Until Software Loads Count (N). N Counts After Count is
Loaded, Output goes Low for One Input Clock Period.

Hardware
Triggered Strobe

Output Goes Low for One Clock Period N Counts After Rising Edge Counter Trigger
Input. The Counter is Retriggerable.

Event Counter

On a Jumper Selectable Basis, the Clock Input Becomes an Input from the External
System. CPU may Read the Number of Events Occurring After the Counter
"Window" has been Enabled or an Interrupt may be Generated After N Events Occur
in the System.

face logic, less power, simpler packaging, higher
performance, and lower cost result when compared
to other alternatives such as MULTIBUS form factor
compatible boards. The iSBX connectors on the
iSBC 86/05A board provide all signals necessary to
interface to the local on-board bus, including 16 cata
lines for maximum data transfer rates. iSBX :viULTIMODU LE boards designed with a-bit data paths and

using the 8-bit iSBX connector are also supported
on the iSBC 86/05A microcomputer. A broad range
of iSBX MULTIMODULE options are available in this
family from Intel. Custom iSBX modules may also be
designed for use on the iSBC a6/05A board. An
iSBX bus interface specification is available from Intel.

3-68

inter

iSBC® 86/05A SINGLE BOARD COMPUTER

MULTIBUS SYSTEM BUS AND
MULTIMASTER CAPABILITIES

Interrupt Capability
The iSBC 86/05A board provides 9 vectored interrupt levels. The highest level is the NMI (Non-Maskable Interrupt) line which is directly tied to the 8086
CPU. This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel
8259A Programmable Interrupt Controller (PIC) provides control and vectoring for the next eight interrupt levels. As shown in Table 3, a selection of four
priority processing modes is available for use in designing request processing configurations to match
system requirements for efficient interrupt servicing
with minimal latencies. Operating mode and priority
assignments may be reconfigured dynamically via
software at any time during system operation. The
PIC accepts interrupt requests from all on-board I/O
resources and from the MULTIBUS system bus. The
PIC then resolves requests according to the selected mode and, if appropriate, issues an interrupt to
the CPU. Any combination of interruptlevels may be
masked via software, by storing a single byte in the
interrupt mask register of the PIC. In systems requiring additional interrupt levels, slave 8259A PICs may
be interfaced via the MULTIBUS system bus, to generate additional vector addresses, yielding a total of
65 unique interrupt levels.

Overview
The MULTIBUS system bus (IEEE 796) is Intel's industry standard microcomputer bus structure. Both
8- and 16-bit single board computers are supported
on the MULTIBUS structure with 24 address and 16
data lines. In its simplest application, the MULTIBUS
system bus allows expansion of functions already
contained on a single board computer (e.g., memory
and digital I/O). However, the MULTIBUS structure
also allows very powerful distributed processing
configurations with multiple processors and intelligent slave I/O, and peripheral boards capable of
solving the most demanding microcomputer applications. The MULTIBUS system bus is supported with
a broad array of board level products, LSI interface
components, detailed published specifications and
application notes.

Expansion Capabilities
Memory and I/O capacity may be expanded and additional functions added using Intel MULTIBUS compatible expansion boards. Memory may be expanded by adding user specified combinations of RAM
boards, EPROM boards, or combination boards. Input/output capacity may be added with digital I/O
and analog I/O expansion boards. Mass storage capability may be achieved by adding single or double
density diskette controllers, or hard disk controllers.

Interrupt Request Generation
Interrupt requests to be serviced by the iSBC
86/05A board may originate from 24 sources. Table
4 includes a list of devices and functions supported
by interrupts. All interrupt signals are brought to the
interrupt jumper matrix where any combination of interrupt sources may be strapped to the desired interrupt request level on the 8259A PIC or the NMI input
to the CPU directly.

Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (i.e.,
several CPUs and/or controllers logically sharing
system tasks through communication of the system
bus), the iSBC 86/05A board provides full MULTIBUS arbitration control logic. This control logic allows up to three iSBC 86/05A boards or other bus
masters to share the system bus using a serial (daisy chain) priority scheme and allows up to 1.6 masters to share the MULTIBUS system bus with an external parallel priority decoder. In addition to the multiprocessing configurations made possible with multimaster .capability, it also provides a very efficient
mechanism for all forms of DMA (Direct Memory Access) \ransfers.

Power-Fail Control and Auxiliary
Power
Control logic is also included, to accept a power-fail
interrupt in conjunction with a power-supply having
AC-Iow signal generation capabilities, to initiate an
orderly shut down of the system iri the event of a
power failure. Additionally, an active-low TTL compatible memory protect signal is brought out on the
auxiliary connector which, when asserted, disables
read/write access to RAM for systems requiring battery backup of read/write memory. Selection of this
auxiliary RAM power bus is made via jumpers on the
board.

3-69

inter

iSBC@ 86/05A SINGLE BPARD COMPUTER

Table 3 Programmable Interrupt Modes
Mode
Fully Nested
Auto-Rotating
Specific
Priority
Polled

Operation
Interrupt Request Line Priorities Fixed at 0 as Highest, 7 as Lowest.
Equal Priority. Each Level, After Receiving Service, Becomes the Lowest Priority
Level until next Interrupt Occurs.
System Software Assigns Lowest Priority Level. Priority of all Other Levels Based in
Sequence. Numerically on this Assignment.
System Software Examines Priority-Encoded System. Interrupt Status via Interrupt
Status Register.
Table 4. Interrupt Request Sources

Device
MULTIBUS Bus Interfape

8255A Programmable
Peripheral Interface
8251A USART
8254 Timers
iSBX Connectors
Bus Fail Safe Timer

Power Fail Interrupt
Power Line Clock
External Interrupt
iSBC 337 A MULTIMODULE
Numeric Data Processor

Number of
Interrupts
8; may be Expand~d to 64
Requests from MULTIBUS Resident
with Slave 8259A PICs on
Peripherals or Other CPU Boards
MULTIBUS Boards
Signals Input Buffer Full or Output Buffer Empty;
3
also BUS INTR OUT General Purpose Interrupt
from Driver/Terminator Sockets
·2
Transmit Buffer Empty and Receive Buffer Full
Function

Timer 0, 1 Outputs; Function Determined by
Timer Mode
Function Determined by iSBX MULTIMODULE
Board
Indicates Addressed MULTIBUS Resident
Device has not Responded to Command within
6-10 ms
Indicates AC Power is not within Tolerance
Source of 120 Hz Signal from Power Supply
General Purpose Interrupt from Auxiliary (P2)
Connector on Backplane
Indicates Error or Exception Condition

3-70

2
4
(2 per iSBX Connector)
1

1
1
1
1

iSBC® 86/05A SINGLE BOARD COMPUTER

ing many different real-time applications. Key iRMX
86 operating system features include multitasking,
multiprogramming, interrupt management, device independence, file protection and control, interactive
debugging, plus interfaces to many Intel and non-Intel developed hardware and software products.

System Development Environment
Development support for the iSBC 86/05A Board is
offered on the System 310 and Series IV Microcomputer Development System from Intel as well as the
IBM Personal Computer.

The iRMX86 operating system is highly modular and
configurable, and includes a sophisticated file management, I/O system, and powerful human interface. The iRMX 86 operating system is also easily
customized and extended by the user to match
unique requirements.

In the Series IV, System 310 and ISM PC development environments, languages offered are Assembler, PLM-86, C, Fortran and Pascal. A powerful software debugger, PSCOPE, is also offered on all
development systems. PSCOPE provides Software
Trace Execution, defineable breakpoints and user
defined/executable debugging procedures.

SPECIFICATIONS
In-Circuit Emulator

Word Size

The 12 1CETM In-Circuit Emulator provides the necessary link between the software development environment and the "target" iSSC 86/05A board, the
12 1CE In-Circuit Emulator provides a sophisticated
command set to assist in debugging software and
final integration of the user hardware and software.

Instruction: 8, 16, 24, or 32 bits
Data: 8, 16 bits
System Clock

5.00 MHz or 8.00 MHz

iSDMTM System Debug Monitor

± 0.1%

Oumper selectable)

Basic Instruction Cycle

The Intel iSDM System Debug Monitor package contains the necessary hardware, software, cables,
EPROMs and documentation required to interface,
through a serial or parallel connection, an iSSC
86/05A target system to System 310 or Series IV
Intellec® Microcomputer Development System for
execution and interactive debugging of applications
software on the target system. The Monitor can:
load programs into the target system; execute the
programs instruction by instruction or at full speed;
set breakpOints; and examine/modify CPU registers,
memory content, and other crucial environmental
details. Additional custom commands can be built
using the Command Extension Interface (CEI).

At 8 MHz: 750 ns
250 ns (assumes instruction in the
queue)
At 5 MHz: 1.2 sec.
400 ns (assumes instruction in the queue)

NOTE:
Basic instruction cycle is defined as the fastest instruction time (I.e., two clock cycles).

Memory Cycle Time
500 ns cycle time (no wait states requires a memory
component access time of 250 ns or less)
RAM: 500 ns
EPROM: Jumper selectable from 500 ns to 875 ns

Software Support
The iRMX 86 operating system is offered for development with a System 310 and provides users with a
powerful set of system building blocks for develop-

3-71

inter

iSBC® 86/05A SINGLE BOARD COMPUTER

Memory Capacity/ Addressing

Baud Rates
Baud Rate (Hz)
Frequency (KHz)
(Software
Synchronous Asynchronous
Selectable)

JEDEC 24/28 Pin Sites
Total Capacity

Device
2K x 8
4K x 8
8K x 8
16K x 8
32K X 8
64K x 8

8K bytes
16K bytes
32K bytes
64K bytes
128K bytes
256K bytes

Device

Total Capacity

Address Range

FEOOO-FFFFFH
FCOOO'FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH
With iSBC® 341 MULTIMODULETM
EPROM/SRAM

2K x 8
4K x 8
8K x 8
16K x 8
32K X 8
64K X 8

Address Range

16K bytes
32K bytes
64K byte~
. 128K bytes
256K bytes
512K bytes

FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH
EOOOO-FFFFFH
COOOO-FFFFFH
80000-FFFFFH

+16
9600
4800
2400
1200
600
300
150
110

153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

38400
19200
9600
4800
2400
1760

+64
2400
1200
600
300
150
75

NOTE:
1. Frequency selected by 1/0 write of appropriate 16-bit
frequency factor to baud rate register (8254 Timer 2).

TIMERS

NOTE:
iSBC 86/05A EPROM sockets support JEDEC 24/28-pin
standard EPROMs and RAMS.

Input Frequencies

ON-BOARD STATIC RAM

Reference: 2.46 MHz ± 0.1 % (0.041 sec. period,
nominal); or 153.60 KHz ± 0.1 %
(6.51 sec. period, nominal)

8K bytes -

0-1 FFFH

NOTE:
Above frequencies are user selectable

16K bytes- 0-3FFFH (with iSBC 302 MULTIMODULE Board)

Event Rate: 2.46 MHz max

I/O CAPACITY
PARALLEL
SERIAL

Output Frequencies/Timing Intervals

24 programmable lines using one 8255A.

Function

1 programmable .Iine using
one 825.1 A.

iSBX MULTIMODULE- 2
iSBX
single
wide
MUL TIMODULE board or 1
iSBX double-width MULTIMODULE board.

SERIAL COMMUNICATIONS
CHARACTERISTICS
SYNCHRONOUS -

5-8 bit characters; internal or
external character synchronization; automatic sync insertion.

3-72

Dual
Timer/Counter
(Two Timers
Cascaded)

Min

Max

Min

Max

Real·Time
Interrupt

1.63 )J.s

427.1 ms

3.26s

466.50
min

Programmable
One-Shot

1.63 )J.s

427.1 ms

3.26s

466.50
min

Rate Generator

2.342 Hz

613.5 kHz

0.000036
Hz

306.8 kHz

Square-Wave
Rate Generator

2.342 Hz

613.5 kHz

0.000036
Hz

306.8 kHz

Software
Triqqered Strobe

1.63 f's

427.1 ms

3.26s

466.50
min

Hardware
Triggered Strobe

1.63 )J.s

427.1 ms

3.26s

466.50
min

2.46 MHz

Event
Counter

ASYNCHRONOUS- 5-8 bit cliaracters; break
character generation; 1, 1%,
or 2 stop bits; false start bit direction.

Single
Timer/Counter

intJ

iSBC® 86/05A SINGLE BOARD COMPUTER

INTERFACES

110 Terminators

MULTIBUS Bus:

220/330 divider or 1K pullup

AIL signals TTL compatible
iSBX BUS Bus:
All signals TTL compatible
PARALLEL I/O:
All signals TTL compatible
RS232C
compatible,
SERIAL I/O:
configurable as a data
set or data terminal
TIMER:
All signals TTL compatible
INTERRUPT REQUESTS: All TTL compatible

22011/33011

__ i _________________ _
1kll

Interface
MULTIBUS
System
iSBXBus
8-Bit Data
16-Bit Data
Parallel I/O
(2)
Serial I/O

Centers
(In.)

Mating
Connectors

0.156

Viking
Wire Wrap

36
44
50

0.1
0.1
0.1

0.1

1kll
+5V -----vvv------143325-3

MULTIBUS® DRIVERS
Function
Data
Address
Commands
Bus Control

Connectors
DoubleSided
Pins
(qty)

22011

+5V-----'\~

Characteristic Sink Current (mA)
Tri-State
50
Tri-State
50
Tri-State
32
Open Collector
20

Physical Characteristics
Width:
Height:
Depth:
Weight:

iSBX 960-5
iSBX 961-5
3M Flat
or
T1 PINS
3M Flat
or
AMP Flat

12.00 in. (30.48 cm)
6.75 in. (17.15 cm)
0.70 in. (1.78 em)
14 oz (388 gm)

ELECTRICAL CHARACTERISTICS
DC Power Requirements

LINE DRIVERS AND TERMINATORS

Configuration
Without EPROM(1)
RAM only(2)
With 8K EPROM(3)
(using 2716)
With 16K EPROM(3)
(using 2732)
With 32K EPROM(3)
(using 2764)

1/0 Drivers
The following line drivers are all compatible with the
I/O driver sockets on the iSBC 86/05A board.
Driver
7438
7437
7432
7426
7409
7408
7403
7400

Characteristic
I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

Sink Current (mA)
48
48
16
16
16
16
16
16

NOTES:
I = inverting; NI = non-inverting; OC = open collector.

Current Requirements
(All Voltages ±5%)
+5V
+12V -12V
4.7A
2SmA 23mA
120mA
2SmA 23mA
S.OA
4.9A

2SmA

23mA

4.9A

2SmA

23mA

NOTES:
1. Does not include power for optional ROM/EPROM, I/O
drivers, and I/O terminators.
. 2. RAM chips powered via auxiliary power bus in powerdown mode.
3. Includes power required for 4 ROM/EPROM chips, and
I/O terminators installed for 16 I/O lines; all terminator inputs low.

Port 1 of the 8255A has 20 mA totem-pole bidirectional drivers and 1K terminators
3-73

intJ

iSBC® 86/05A SINGLE BOARD COMPUTER

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

ENVIRONMENTAL
CHARACTERISTICS
Operating Temperature: O·C to 55·C
Relative Humidity: to 90% (without condensation)

ORDER INFORMATION
Part Number

REFERENCE MANUAL

SBC 86/05A

Order no. 147162-002-iSBC 86105A Hardware
Reference Manual (NOT SUPPLIED)

3-74

Description
16-bi~

Single Board Computer with
8K bytes RAM

iSBC® 86/14 AND iSBC® 86/30
SINGLE BOARD COMPUTERS

•
•
•
•
•
•
•

Programmable Synchronous/
• Asynchronous
RS232C Compatible

8086 Microprocessor with 5 or 8 MHz
CPU Clock

Serial Interface with Software
Selectable Baud Rates

Fully Software Compatible with iSBC®
86/12A Single Board Computer

•
•
•
•

Optional 8086 Numeric Data Processor
with iSBC® 337A MULTIMODULETM
Processor
32K/128K bytes of Dual-Port Read/
Write Memory Expandable On-Board to
256K bytes with On-Board Refresh
Sockets for up to 64K bytes of JEDEC
24/28-pin Standard Memory Devices
Two iSBXTM Bus Connectors
24 Programmable Parallel I/O Lines

Two Programmable 16-Bit BCD or
Binary Timers/Event Counters
9 Levels of Vectored Interrupt Control,
Expandable to 65 Levels
MULTIBUS® Interface for Multimaster
Configurations and System Expansion
Supported by a Complete Family of
Single Board Computers, Memory,
Digital and Analog I/O, Peripheral
Controllers, Packaging and Software

The iSBC 86/14 and iSBC 86/30 Single Board Computers are members of Intel's complete line of OEM
microcomputer systems which take full advantage of Intel's technology to provide economical, self-contained,
computer-based solutions for OEM applications. Each board is a complete computer system ona single 6.75 x
12.00-in. printed circuit card distinguished by RAM memory content with 32K bytes and 128K bytes provided
on the iSBC 86/14 and iSBC 86/30 board, respectively. The CPU,system clock, read/write memory, nonvolatile read only memory, I/O ports and drivers, serial communications interface, priority interrupt logic and
programmable timers, all reside on the boards.

280007-1

3-75

September 1987
Order Number: 280007-004

intJ

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

For enhanced numerics processing capability, the
iSBC 337A MULTIMODULE Numeric Data Processor extends the 8086/10 architecture and data set.
Over 60 numeric instructions offer arithmetic, trigonometric, transcendental, logarithmic and exponential instructions. Supported data types include 16-,
32, and 64-bit integer, and 32- and 64-bit floating
point, 18-digit packed BCD and 80-bit temporary.

FUNCTIONAL DESCRIPTION
Central Processing Unit
The central processor for the iSBC 86/XX' boards is
Intel's iAPX 86/10 (8086-2) CPU. A clock rate of 8
MHz is supported with a jumper selectable option of
5 MHz. The CPU architecture includes four 16-bit
byte addressable data registers, two 16-bit memory
base pOinter registers and two 16-bit index registers,
all accessed by a total of 24 operand addressing
modes for comprehensive memory addressing and
for support of the data structures required for today's structured, high level languages as well as assembly language.

Architectural Features
A 6-byte instruction queue provides pre-fetching of
sequential instructions and can reduce the 750 nsec
minimum instruction cycle to 250 nsecfor queued
instructions. The stack-oriented architecture readily
supports modular programming by facilitating fast,
simple, inter-module communication, and other programming constructs needed for asynchronous realtime systems. The memory expansion capabilities
offer a 1 megabyte addressing range. The dynamic
relocation scheme allows ease in segmentation of
pure procedure and data for efficient memory utilization. Four segment registers (code, stack, data, extra) contain program loaded offset values which are
used to map 16-bit addresses to 20-bit addresses.
Each register maps 64K bytes at a time 'and activation of a specific register is controlled explicitly by
program control and is also selected implicitly by
specific functions and instructions.

NOTE:
iSBC 86/XX designates both the iSBC 86/14 and
iSBC 86/30 CPU boards.

Instruction Set
The 8086 instruction repertoire includes variable
length instruction format (including double operand
instructions), .8-bit and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manipulation functions.

280007-2

Figure 1. iSBC® 86/XX Block Diagram

3-76

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

RAM Capabilities

Parallel 1/0 Interface

The iSBC 86/14 and iSBC 86/30 microcomputers
contain 32K bytes and 128K bytes of dual-port dynamic RAM, respectively. In addition, on-board RAM
may be doubled on each microcomputer by optionally adding RAM MULTIMODULE boards. The onboard RAM may be expanded to 256K bytes with
the iSBC 304 MULTIMODULE Board mounted onto
the iSBC 86/30 board. Likewise, the iSBC 86/14 microcomputer may be expanded to 64K bytes with
the iSBC 300A MULTIMODULE option. The dualport controller allows access to the on-board RAM
(including RAM MULTIMODULE options) from the
iSBC 86/XX boards and from any other MULTIBUS
master via the system bus. Segments of on-board
RAM may be configured as a private resource, protected from MULTIBUS system access. The amount
of memory allocated as a private resource may be
configured in increments of 25% of the total onboard memory ranging from 0% to 100% (optional
RAM MULTIMODULE boards double the increment
size). These features allow the multiprocessor systems to establish local memory for each processor
and shared system memory configurations where
the total system memory size (including local onboard memory) can exceed one megabyte without
addressing conflicts.

The iSBC 86/XX Single Board Computers contain .
24 programmable parallel I/O lines implemented using the Intel 8255A Programmable Peripheral Interface. The system software is used to configure the
I/O lines in any combination of unidirectional input!
output and bidirectional ports indicated in Table 1. In
order to take advantage of the large number of possible I/O configurations, sockets are provided for interchangeable I/O line drivers and terminators, allowing the selection of the appropriate combination
of optional line drivers and terminators with the required drive/termination characteristics. The 24 programmable I/O lines and signal ground lines are
brought out to a 50-pin edge connector.

Serial 1/0
A programmable communications interface using
the Intel 8251 A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) is contained on
the iSBC 86/XX boards. A software selectable baud
rate generator provides the USART with all common
communication frequencies. The mode of operation
(Le., synchronous or asynchronous), data format,
control character format, parity, and baud rate are all
under program control. The 8251A provides full duplex, double buffered transmit and receive capability.
Parity, overrun, and framing error detection are all
incorporated in the USART. The RS232C command
lines, serial data lines and signal ground line are
brought out to a 26-pin edge connector.

EPROM Capabilities
Four 28-pin sockets are provided for the use of Intel
2716s, 2732As, 2764s, 27128s, and their respective
ROMs. When using 27128s, the on-board EPROM
capacity is 64K bytes. Other JEDEC standard pinout
devices are also supported, including byte-wide static RAMs.

Programmable Timers
The iSBC 86/XX boards provide three independent,
fully programmable 16-bit interval timers/event
counters utilizing the Intel 8253 Programmable In-

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Port

Lines
(Qty)

Input
Latched

1
2
3

8
8
4
4

X
X
X
X

Output

Latched &
Strobed
X
X

Latched
X
X
X
X

Bidirectional

Control

Latched &
Strobed
X
X

X
X(1)
X(1)

NOTE:

1. Part of port 3 must be used as a control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.

3-77

intJ

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

terval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs and gate/trigger inputs of two of these counters is jumper selectable.
The outputs may be independently routed to the
8259A Programmable Interrupt Controller and to the·
I/O terminators associated with the 8255A to allow
external devices or an 8255A port to gate the timer
or to count external events. The third interval timer
in the 8253 provides the programmable baud rate
generator for the iSBC 86/XX boards' RS232C
USART serial port. The system software configures
each timer independently to select the desired function. Seven functions are available as shown in Table 2. The contents of each counter may be read at
any time during system operation.

iSBXTM MULTIMODULETM On-Board
Expansion
Two 8/16-bit iSBX MULTIMODULE connectors are
provided on the iSBC 86/XX rnicrocomputers.
Through these connectors, additional on-board I/O
functions may be added. iSBX MULTIMODULE
boards optimally support functions provided by VLSI
peripheral components such as additional parallel
al'ld serial I/O, analog 110, small mass storage device controllers (e.g., cassettes and floppy disks),
and other custom interfaces to meet specific needs.
By. mounting directly on the single board computer,
less interface logic, less power, simpler packaging,
higher performance, and lower cost result when
compared to other alternatives such as MULTIBUS
form factor compatible boards. The iSBX connectors
on the iSBC 86/XX boards provide all signals necessaryto interface to the local on-board bus, including
16 data lines for maximum data transfer rates. iSBX
MULTIMODULE boards designed with 8-bit data
paths and using the 8-bit iSBX connector are also
supported on the' iSBC 86/XX microcomputers. A
broad range of iSBX MULTIMODULE options are
available in this family from Intel. Custom iSBX modules may also be designed for use on the iSBC 86/
XX boards. An iSBX bus interface specification and
iSBX connectors are available from Intel.

Table 2. Programmable Timer Functions
Function
Operation
Interrupt on
When terminal count is reached,
Terminal Count an interrupt request is generated.
This function is extremely useful
for generation or real-time clocks.
Programmable
One-Shot

Rate
Generator

Output goes low upon receipt of
an internal trigger edge or
software command and returns
high when terminal count is
reached. This function is
retriggerable.

MULTIBUS® SYSTEM BUS AND
MULTIMASTER. CAPABILITIES

Divide by N counter. The output
will go low for one input clock
cycle, and the period from one
low going pulse to the next is N
times the input clock period.

Overview
The MULTIBUS system bus is Intel's industry standard microcomputer bus structure. Both 8 and 16-bit
single board computers are supported on the MULTIBUS structure with 24 address and 16 data lines.
In its simplest application, the MULTIBUS system
bus allows expansion of functions already contained
on a single board computer (e.g., memory and digital
I/O). However,·the MULTIBUS structure also allows
very powerful distributed processing configurations
with multiple processors and intelligent slave I/O,
and peripheral boards capable of solving the most
demanding microcomputer applications. The MULTIBUS system bus is supported with a broad array of
board level products, LSI interface components, detailed published specifications and application notes.

Square-Wave
Output will remain high until oneRate Generator half the count has been
completed, and go low for the
other half of the count.
Software
Triggered
Strobe

Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.

Hardware
Triggered
Strobe

Output goes low for one clock
period N counts after rising edge
counter trigger input. The counter
is retriggerable.

Event Counter

On a jumper selectable basis, the
clock input becomes an input
from the external system. CPU
may read the number of events
occurring after the counter
"window" has been enabled or
an interrupt may be generated
after N events occur in the
system.

Expansion Capabilities
Memory and I/O capacity may be expanded and additional functions added using Intel MULTIBUS compatible expansion boards. Memory may be expand. ed by adding user specified combinations of RAM
boards, EPROM boards, or combination boards. On3-78

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

board EPROM capacity may be expanded to 128K
by user reprogramming of a PAL device to support
27256 EPROM devices. Input/output capacity may
be added with digital I/O and analog 110 expansion
boards. Mass storage capability may be achieved by
adding single or double density diskette controllers,
or hard disk controllers. Modular expandable backplanes and cardcages are available to support multiboard systems.

request processing configurations to match system
requirements for efficient interrupt servicing with
minimal latencies. Operating mode and priority assignments may be reconfigured dynamically via software at any time during system operation. The PIC
accepts interrupt requests from all on-board I/O resources and from the MULTIBUS system bus. The
PIC then resolves requests according to the selected mode and, if appropriate, issues an interrupt to
the CPU. Any combination of interrupt levels may be
masked via software,. by storing a single byte in the
interrupt mask register of the PIC. In systems requiring additional interrupt levels, slave 8259A PICs may
be interfaced via the MULTIBUS system bus, to generate additional vector addresses, yielding a total of
65 unique interrupt levels.

Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (Le.,
several CPUs and/or controllers logically sharing
system tasks through communication of the system
bus), the iSBC 86/XX boards provide full MULTIBUS
arbitration control logic. This control logic allows up
to three iSBC 86/XX boards or other bus masters,
including iSBC 80 family MULTIBUS compatible 8-bit
single board computers to share the system bus using a serial (daisy chain) priority scheme and allows
up to 16 masters to share the MULTIBUS system
bus with an external parallel priority decoder. In addition to the multiprocessing configurations made
possible with multimaster capability, it also provides
a very efficient mechanism for all forms of DMA (Direct Memory Access) transfers.

Interrupt Request Generation
Interrupt requests to be serviced by the iSBC 86/XX
boards may originate from 28 sources. Table 4 includes a list of devices and functions supported by
interrupts. All interrupt signals are brought to the interrupt jumper matrix where any combination of interrupt sources may be strapped to the desired interrupt request level on the 8259A PIC or the NMI input
to the CPU directly.

Power-Fail Control and Auxiliary
Power

Interrupt Capability

Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal from
the iSBC 635 and iSBC 640 Power Supply or equivalent, to initiate an orderly shut down of the system in
the event of a power failure. Additionally, an activelow TTL compatible memory protect signal is
brought out on the auxiliary connector which, when
asserted, disables read/write access to RAM memory on the board. This input is provided for the protection of RAM contents during system power-down
sequences. An auxiliary power bus is also provided
to allow separate power to RAM for systems requiring battery back-up of read/write memory. Selection
of this auxiliary RAM power bus is made via jumpers
on the board.

The iSBC 86/XX boards provide 9 vectored interrupt
levels. The highest level is the NMI (Non-Maskable
Interrupt) line which is directly tied to the 8086 CPU.
This interrupt is typically used for signaling catastrophic events (e.g., power failure). The Intel 8259A
Programmable Interrupt Controller (PIC) provides
control and vectoring for the next eight interrupt levels. As shown in Table 3, a selection of four priority
processing modes is available for use in designing
Table 3. Programmable Interrupt Modes
Mode

Operation

Fully Nested Interrupt request line priorities fixed
at 0 as highest, 7 as lowest.
Auto-Rotating Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.
Specific
Priority

System software assigns lowest
priority level. Priority of all other
levels based in sequence
numerically on this assignment.

Polled

System software examines priorityencoded system interrupt status via
interrupt status register.

System Development Capabilities
The development cycle of iSBC 86/XX products can
be significantly reduced and simplified by using either the System 86/310 or the Intellec Series IV Microcomputer Development System or the IBM PC.

3-79

inter

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

SPECIFICATIONS

IN·CIRCUIT EMULATOR
The 121CE In-Circuit Emulator provides the necessary link between the software development environment and the "target" iSBC 86/XX execution
system. In addition to providing the mechanism for
loading executable code and data into the iSBC 86/
XX boards, the 121CE In-Circuit Emulator provides a
sophisticated command set to assist in debugging
software and final integration of the user hardware
and software.

Word Size
Instruction: 8, 16, 24, or 32 bits
Data: 8, 16 bits

System Clock
5.00 MHz or 8.00 MHz ± 0.1 % Oumper selectable)

PL/M-86
Cycle Time

Intel's system's implementation language, PLlM-86,
is standard in the System 86/310 and is also available for the Series IV and the IBM PC. PL/M-86 provides the capability to program in algorithmic language and eliminates the need to manage register
usage or allocate memory while still allowing explicit
control of the system's resources when needed.
FORTRAN 86, PASCAL 86 and C86 are also available the Intellec Series IV, 86/310 systems and the
IBM PC.

BASIC INSTRUCTION CYCLE
8 MHz: 750 ns
250 ns (assumes instruction in the queue)
5 MHz: 1.2 p.s
400 ns (assumes instruction in the queue)
NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le., two clock cycles).

Table 4. Interrupt Request Sources
Device

Function

Number of
Interrupts

MULTIBUS Interface

Requests from MULTIBUS resident peripherals or other 8; may be Expanded to
CPU boards.
64 with Slave 8259A
PICs on MULTIBUS
Boards

8255A Programmable
Peripheral Interface

Signals input buffer full or output buffer empty; also BUS
INTR OUT general purpose interrupt from driver/
terminator sockets.

8251A USART

Transmit buffer empty and receive buffer full.

8253 Timers

Timer 0, 1 outputs; function determined by timer mode.

iSBX Connectors

Function determined by iSBX MULTIMODULE board.

Bus Fail Safe Timer

Indicates addressed MULTIBUS resident device has not
responded to command within 6 ms.

4
(2 per iSBX Connector)
1

Power Fail Interrupt

Indicates AC power is not within tolerance.

Power Line Clock

Source of 120 Hz signal from power supply.

External Interrupt

General purpose interrupt from auxiliary (P2) connector
on backplane.

iSBC 337 A MULTIMODULE Indicates error or exception condition.
Numeric Data Processor

Parity Error

Indicates on-board RAM parity error from iSBC 303
parity MULTIMODULE board (iSBC 86/14 option).

Edge-Level Conversion

Converts edge triggered interrupt request to level
interrupt.

OR-Gate Matrix

Outputs of OR-gates on-board for multiple interrupts.

3-80

inter

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

Memory Cycle Time

Serial Communications
Characteristics

RAM:
750 ns
EPROM: Jumper selectable from 500 ns to 875 ns

Synchronous: 5-8 bits characters; internal or external character synchronization; automatic sync insertion
Asynchronous: 5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit direction

Memory Capacity1Addressing
ON-BOARD EPROM
Device
2716
2732A
2764
27128

Total Capacity
8K bytes
16K bytes
32K bytes
64K bytes

Address Range
BAUD RATES

FEOOO~FFFFFH

FCOOO-FFFFFH
F8000-FFFFFH
FOOOO-FFFFFH

NOTE:
iSBC 86/XX EPROM sockets support JEDEC 24/
28-pin standard EPROMs and RAMs. Total EPROM
capacity may be increased to 128 bytes by the user .
reprogramming an on-board PAL.
ON-BOARD RAM
Board
Total Capacity Address Range
iSBC86/14
32K bytes
0-07FFFH
iSBC86/30
128K bytes
0-1 FFFFH

Frequency (kHz)
Baud Rate (Hz)
(Software
Selectable
Synchronous Asynchronous
+16
+64
153.6
9600
2400
76.8
4800
1200
38.4
38400
2400
600
19.2
1920.0
1200
300
9.6
9600
150
600
4.8
4800
300
75
2.4
2400
150
1.76
1760
110
NOTE:
Frequency selected by I/O write of appropriate 16-bit frequency factor to baud rate register (8253 Timer 2),

WITH MULTIMODULETM RAM
Board
Total Capacity Address Range
64K bytes
iSBC300A
O':'OFFFFH
(with iSBC 86/14)
iSBC304
256K bytes
0-3FFFFH
(with iSBC 86/30)

Timers
·INPUT FREQUENCIES
Reference: 2.46 MHz ± 0.1 % (0.041 /ksec period,
nominal); or 153.60 kHz ± 0.1 % (6.51 /ksec period,
nominal)

1/0 Capacity
Parallel: 24 programmable lines using one 8255A.
Serial: 1 programmable line using one 8251A
iSBX MULTIMODULE: 2 iSBX boards

NOTE:
Above frequencies are user selectable.
Event Rate: 2.46 MHz max

OUTPUT FREQUENCIES/TIMING INTERVALS

Function

Real-Time Interrupt
Programmable One-Shot
Rate Generator

Single
Timer/Counter

Dual
Timer/counter
(Cascaded)

Min

Max

Min

Max

1.63/ks

427.1 ms

3.26s

466.50 min

1.63/ks

427.1 ms

3.26s

466.50 min

2.342 Hz 613.5 kHz 0.000036 Hz

306.8 kHz

Square-Wave Rate Generator 2.342 Hz 613.5 kHz 0.000036 Hz

306.8 kHz

Software Triggered Strobe

1.63/ks

Hardware Triggered Strobe
Event Counter

427.1 ms

3.26s

466.50 min

1.63/ks

427.1 ms

3.26s

466.50 min

2.46 MHz

3-81

intJ

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

Port 1 of the 8255A has 20 mA totem-pole bidirectional drivers and 1 Kn terminators

Interfaces
MULTIBUS: All signals TIL compatible
iSBX Bus: All signals TIL compatible

1/0 TERMINATORS

Parallel 1/0: All signals TIL compatible

220n/330n divider or 1 k!l pullup

Serial 110: RS232C compatible, configurable as a
data set or data terminal
Timer: All signals TIL compatible
Interrupt Requests: All TIL compatible

220.0./330.0.
2200
+5V - - - - : " " ; " , . . - - - - ,

__ f ______________~ __ _

Connectors
DoubleCenters
Sided
(In.)
Pins

Interface
MUILTIBUS
System

0.156

iSBX Bus
8-Bit Data
Parallel 1/0
(2)

0.1

Serial 1/0

0.1

Mating
Connectors

1 kO

lKD
+5V - - - - - "..Ny.....- - - - - - 0 0

280007-3

Viking
3KH43/9AMK12
Wire Wrap
iSBX960-5

MULTIBUS® Drivers

3M 3415-000 Flat
or
TI H312125 Pins
3M 3462-0001
Flat or
AMP 88106-1 Flat

Function

Characteristic

Sink Current (rnA)

Data
Address
Commands
Bus Control

Tri-State
Tri-State
Tri-State
Open Collector

32
32
32
20

Physical Characteristics
Line Drivers and Terminators

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.70 in. (1.78 cm)
Weight: 14 oz (388 gm)

1/0 DRIVERS
The following line drivers are all compatible with the
1/0 driver sockets on the iSBC 86/05 board
Driver
7438
7437
7432
7426
7409
7408
7403
7400

Characteristics
I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

Environmental Characteristics

Sink Current (rnA)

NOTE:
, = inverting; N'· = non-inverting; OC

48
48
16
16
16
16
16
16

Operating Temperature: O°C to 55°C
Relative Humidity: to 90% (without condensation)

= open collector.

3-82

infef

iSBC® 86/14 AND iSBC® 86/30 SINGLE BOARD COMPUTERS

Electrical Characteristics

Environmental Characteristics

DC POWER REQUIREMENTS

Operating Temperature: O°C to SsoC
Relative Humidity: to 90% (without condensation)

Configuration
Without EPROM1
RAM only2
With 8K EPROM3
(using 2716)
With 16K EPROM3
(using 2732A)
With 32K EPROM3
(using 2764)

Current Requirements
(All Voltages ±S%)
+SV
S.1A
600mA
S.4A

+12V
2SmA

-12V

Reference Manual

23mA

2SmA

23mA

144044-002: iSBC 86/14 and iSBC 86/30 Hardware
Reference Manual (NOT SUPPLIED)

S.SA

2SmA

23mA

S.6A

2SmA

23mA

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
. Department, 306S Bowers Avenue, Santa Clara,
California 9S0S1.

NOTES:
1. Does not include power for optional ROM/EPROM, I/O
drivers, and I/O terminators.
2. RAM chips powered via auxiliary power bus in powerdown mode.
3. Includes power required for 4 ROM/EPROM chips, and
I/O terminators installed for 16 I/O lines; all terminator inputs low.

ORDERING INFORMATION
Part Number Description
SBC 86/14
Single Board Computer
SBC 86/30
Single Board Computer

3-83

iSBC® 286/10A
SINGLE BOARD COMPUTER

•
•
•
•o
•

On-Board Memory Capacity
• Maximum
384 KB

8 MHz 80286 Microprocessor
Supports User Installed 80287 Numeric
Data Processor

iLBXTM Interface for iLBX Memory
Board Expansion
Wait-State Synchronous Interface to
EX Memory Expansion Boards

Eight JEDEC 28-Pln Sites for Optional
SRAM/iRAM/EPROM/E2PROM
Components

•

Optional Expansion to Sixteen JEDEC
28-Pln Sites with Two ,SBE® 341
Boards

•

Two iSBXTM Bus Interface Connectors
for 1/0 Expansion

•
•
•

Centronics-Compatible Parallel I/O
Printer Interface

16 Levels of Vectored Interrupt Control

Two Programmable Multiprotocol
Synchronousl Asynchronous Serial
Interfaces; One RS232C, the Other
RS232C or RS4221449 Compatible

The iSBC® 286/10A Single Board Computer is a member of Intel's complete line of microcomputer modules
and systems which take advantage of Intel's VLSI technology to provide economical, of,f-the-shelf, computerbased solutions for OEM applications. The board is a complete microcomputer system on a 6.75 x 12.0 inch
printed circuit card. The CPU, system clock, memory sockets, liD ports and drivers, serial communications
interface, priority interrupt logic and programmable timers all reside on the board. The iSBC 286/10A board
offers both a standard iLBX interface for high-speed memory access to Intel's series of iLBX memory boards
and a new, 0 wait-state, synchronous interface for use with Intels EX series of memory boards. The iSBC
286/1 OA Single Board Computer is fully compatible with its predecessor, the iSBC 286/1 OA board, and can be
used in applications originally designed for the earlier model.

280079-1

• XENIXTM is a trademark of MICROSOFT Inc.
• UNIX® is a registered trademark of BELL Labs.

3-84

September 1987
Order Number: 280079-005

iSBC® 286/10A SINGLE BOARD COMPUTER

FUNCTIONAL DESCRIPTION

Architectural Features
The 8086, 8088, 80186 and the 80286 microprocessor family contains the same basic set of registers,
instructions, and addressing modes. The 80286
processor is upward compatible with the 8086,
8088, and 80186 CPUs.

Overview
The iSBC 286/10A board utilizes the powerful
80286 CPU within the MULTIBUS® system architecture, enhanced by the industry standard iLBX bus
and a new, 0 wait-state, synchronous memory interface, to provide a high performance 16-bit solution.
This board also includes on-board interrupt, memory
and I/O features facilitating a complete signal board
computer system. The iSBC 286/10A board is designed to be fully compatible with the iSBC 286/10
board, and only minor changes to software timing
loops may be required.

The 80286 operates in two modes: 8086 real address mode, and protected virtual address mode. In
8086 real address mode, programs use real address
with up to one megabyte of address space. Programs use virtual addresses in protected virtual address mode, also called protected mode. In protected mode, the 80286 CPU automatically maps 1 gigabyte of virtual addresses per task into a 16 megabyte real address space. This mode also provides
memory protection to isolate the operating system
and ensure privacy of each task's programs and
data. Both modes provide the same base instruction
set, registers, and addressing modes.

Central Processing Unit
The central processor for the iSBC 286/10A board
is the 80286 CPU operating at a 8.0 MHz clock rate.
The 80286 CPU is upwardly compatible with Intel's
8088 and iAPX 86 CPUs. The 80286 CPU runs 8088
and 86 code at substantially higher speeds due to
it's parallel chip architecture. In some cases, software timing loops may have to be adjusted to accommodate the faster CPU clock. In addition, the
80286 CPU provides on chip memory management
and protection and virtual memory addressing of up
to 1 gigabyte per task. Numeric processing power
may be enhanced with the user installed 80287 numerics processor. The clock rates for the 80286 and
the 80287 are independent with the 80287 rate
jumper selectable at either 5.3 or 8.0 MHz.

VECTORED INTERRUPT CONTROL

Incoming interrupts .are handled by two on-board
8259A programmable interrupt controllers and by
the 80286's NMI line. Interrupts originating from up
to 16 sources are prioritized and then sent to the
CPU as a vector address. Further interrupt capability
is available through bus vectored interrupts where
slave 8259 interrupt controllers are resident on separate iSBC boards and are then cascaded into the
on-board interrupt control.
INTERRUPT SOURCES

Instruction Set

Twenty-three potential interrupt sources are routed
to the interrupt jumper matrix where the user can
connect the desired interrupt sources to specific interrupt levels. Table 1 includes a list of devices and
functions supported by interrupts.

The 80286 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8-bit and 16-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manipulation functions.

MEMORY CAPABILITIES

There are a total of eight 28-pin JEDEC sites on
board. Four sites are for local memory and can contain up to 256K bytes of EPROM devices. The four
other sites are known as the dual-port memory and
may be addressed by the MULTIBUS interface and
the on-board CPU bus. Up to 128K bytes of either
iRAM, SRAM, EPROM, or E2PROM can reside in
these sites. Both the local and dual-port memory
can be expanded to eight sites each by using two
iSBC 341 JEDEC expansion modules. In this way,
smaller size memory devices can be used up to the
256KB (local) and 128KB (dual-port) memory capacities.

For enhanced numerics processing capability, the
80287 Numeric Data Processor extends the 80286
architecture and data set. Over 60 numeric instructions offer arithmetic, trigonometric, transcendental,
logarithmic and exponential instructions. Supported
data types include 16-, 32-, and 64-bit integer, 32and 64-bit floating pOint, 18-digit packed BCD and
80-bit temporary. The 80287 meets the proposed
IEEE P754 standard for numeric data processing
and maintains compatibility with 8087-based systems.

3-85

cl
.zyl..~n'~~~
RS232C/RS4221
RS449 INTERFACE

DRIVERITERMINATOR
INTERFACE

POWER FAIL ' - - - - -

...cCD

iii

III
0
@)

I\)
(,)

m .....
.....
0)

(I)

INTERRUPT
MATRIX
,(JUMPERS,

, 7

PROGRAMMABLE
PERIPHERAL
INTERFACE
(1255A)

80287 NUMERIC
DATA PROCESSOR
(USER SUPPUED)

Isax"

I
I

MULTIMODULE~

ISBX~BUS
MULTIMODULE~

CONNECTOR

----.
"I'
I

ONE
PROGRAMMABLE
TIMER
(tl31254A,

PROGRAMMABLE
INTERRUPT
CONTROLLERS
(TWOI25eA,

III

;I;'

iii'
co

;;

iL8X'·BUS
INTERFACE

.,.
SERIAL
INTERFACE
(USART,
(1274)

<;ilBX'. BUS/sYNCHRONDUS

PROGRAMMABLE
BAUD RATE
GENERATOR
(2/31254,

FOUR 28 PIN SITES
(LOCAL MEMORY,

8MHz
80288
CPU

MULTIBUS' I
MULTIMASTER
INTERFACE

~
en

Z
r-

m
o
::u
o
l>

DUAL-PORT
CONTROLLER

(')

r------,

/'--A

I FOUR,21 PIN SITES I
ISac' 341

Y-VI

FOUR 21 PIN SITES

;;.

INTERFACE~

c:n
......

;;.
A

;FOUR28Piij
iSBC' 341

j,.

SYNCHRONOUS
INTERFACE

en
m

(')

SiTeS]

~----J

ON,BOARD LOCAL BUS

--.

I
I

N
011

-------

!!
co
:""

f-'

;:..

r---D--~!'!.Il!--i .!z----l

RS232C
,INTERFACE

MUlTIBUS" SYSJEM BUS

280079-2

!!:

c:
-I

::u

inter

iSBC® 286/10A SINGLE BOARD COMPUTER

Table 1. Interrupt Request Sources
Device

Function

MULTIBUS Interface

Requests from MULTIBUS Resident Peripherals or Other CPU Boards

8259A Programmable 8 Level Vectored Interrupt Request Cascaded to Master 8259A
Interrupt Conroller

Number of
Interrupts
8"
1

8274 Serial Controller 8 Level Vectored Interrupt Request Cascaded to Master 8259A
8255A Line Printer
Signals Output Buffer Empty
Interface

1
2

8254 Timers

Timer 0, 1 Outputs; Function Determined by Timer Mode

iSBX Connectors

Function Determined by iSBX MULTIMODULE Board

Bus Fail Safe Timer

Indicates Addressed MULTIBUS Resident Device Has not
Responded to Command within 6 ms

4
(2 per iSBXTM
Connector)
1

Power Fail Interrupt

Indicates AC Power Is not within Tolerance

External Interrupt

General Purpose Interrupt from Auxiliary Connector, Commonly Used
as Front Panel Interrupt

On-Board Logic

Conditioned Interrupt Source from Edge Sense Latch, Inverter, or OR
Gate

• May be expanded to 56 with slave 8259A PIGs on MULTIBUS' boards

SERIAL 1/0

A two channel serial communications interface using
Intel's 8274 Multi-Protocol Serial Controller (MPSC)
is contained on the iSBC 286/10 board. Two inde~
pendent software selectable baud rate generators
provide the MPSC with all common communication
frequencies. The protocol (Le., asynchronous, IBM'
bisync, or SDLC/HDLC), data format, control char. acter format, parity and baud rate are all under program control. Software interfacing to the MPSC can
be via either a polled or interrupt driven routine. One
channel may be configured for· an RS232C or
RS422/RS449 interface with the other channel
RS232C only. The data, command and signal
ground lines for each channel are brought out to two
26-pin edge connectors.
PROGRAMMABLE TIMERS

The iSBC··286/10A board provides three independent, fully programmable 16-bit interval timersl event
counters utilizing the Intel 8254 Programmable Interval Timer. Each counter is capable of operating in
either BCD or binary modes. Two of these timersl
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs of these counters is
jumper selectable. The outputs may be independently routed to the 8259A Programmable Interrupt
Controller or to the 8274 MPSC to count external
events or provide baud rate generation. The third

3-87

interval timerin the 8254 is dedicated to providing a
clock for the programmable baud rate generator in
the iSBC 286/10A board's MPSC serial controller.
The system software configures each timer independently to select the desired function. Seven functions are available as shown in Table 2. The contents of each ,counter may be read at any time during
system operation.
LINE PRINTER INTERFACE

An 8255A Programmable Peripheral Interface (PPI)
provides a line printer interface,· several on-board
functions, and four non-dedicated input bits. Drivers
are provided for a complete Centronics compatible
line printer interface. The on-board functions implemented with the PPI are power fail sense, override,
NMI mask, non-volatile RAM enable, clear timeout
interrupt, LED 0 and 1, clear edge sense flop, MULTIBUS interrupt, and serial channel A loopback. The
PPl's 1/0 lines are divided into three eight bit ports:
A, B, and C. Four non-dedicated input bits allow the
state of four user-configured jumper connections to
be input. The PPI must be programmed for mode 0
with ports A and C used as outputs and port B as
input. A 16-bit write to Port B is used to set the iSBC
286/10A board into 24-bit address mode. The parallel port assignment is shown in Table 3.

inter

iSBC® 286/10A SINGLE BOARD COMPUTER

Table 2. Programmable Time Functions
Function

Operation

Interrupt on
Terminal Count

When terminal count is
reached, an interrupt-request
is generated. This function is
extremely useful for
generation of real-time clocks.

Programmable
One-Shot

Output goes low upon receipt
of an external trigger edge or
software command and
returns high when terminal
count is reached. This
function is retriggerable.

Rate Generator

Divide by N counter. The
output will go low for one input
clock cycle, and the period
from one low going pulse to
the next is N times the input
clock period.

Square-Wave
Rate Generator

Output will remain high until
one-half the count has been
completed, and go low for the
other half of the count.

Software
Triggered
Strobe

Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.

Hardware
Triggered
Strobe

Output goes low for one clock
period N counts after rising
edge counter trigger input.
The counter is retriggerable.

Even Counter

On a jumper selectable basis,
the clock input becomes an
input from the external
system. CPU may read the
number of events occurrin~
after the counter "window'
has been enabled or an
interrupt may be generated
after N events occur in the
system.

Table 3. Parallel Port Bit Assignment
Bit
0
1
2
3
4
5
6
7

The MULTIBUS system architecture includes three
bus structures: the system bus, the local bus extension and the MULTIMODULE expansion. bus as
shown in Figure 2. Each bus structure is optimized to
satisfy particular system requirements. The system
bus provides a basis for general system design including memory and 110 expansion as well as multiprocessing support. The local bus extension allows
large amounts of high performance memory to be
accessed from a CPU board over a private bus. The
MULTIMODULE extension bus is a means of adding
inexpensive 110 functions to a base CPU board.

Line Printer Data Bit 0
Line Printer Data Bit 1
Line Printer Data Bit 2
Line Printer Data Bit 3
Line Printer Data Bit 4
Line Printer Data Bit 5
Line Printer Data Bit 6
Line Printer Data Bit 7
Port B--Input

Bit
0
1
2
3
4
5
6
7

Function
General Purpose Input 0
General Purpose Input 1
General Purpose Input 2
General Purpose Input 3
Line Printer ACKI (Active Low)
Power Fail SenseI (Active Low)
Line Printer Error (Active Hi)
Line Printer Busy (Active Hi)
Port C-output

Bit

Function

0
1
2
3

Line Printer Data Strobe (Active Hi)
Overridel (Active Low)
NMI Mask (0 = NMI Enabled)
Non-Volatile RAM Enable; Clear Timeout
Interrupti
LED 0 (1 = On); Clear Edge Sense Flopl
MULTIBUS Interrupt (1 = Active)
Serial CHA Loopback
(0 = Online, 1 = Loopback)
LED 1 (1 = On);
Clear Line Printer Ack Flopl

4
5
6
7

Each of these three bus structures are implemented
on the iSBC 286/10A board providing a total system
architecture solution.

SYSTEM BUS-IEEE 796

MULTIBUS® SYSTEM ARCHITECTURE
Overview

Port A-output
Function

The MULTIBUS system bus is Intel's industry standard, IEEE 796, microcomputer bus structure. Both
8- and 16-bit single board computers are supported
on the IEEE 796 structure with 24 address and 16
. data lines. In its simplest application, the system bus
allows expansion of functions already contained on
a single board computer (e.g., memory and digital
110). However, the IEEE 796 bus also allows. very
powerful distributed processing configurations using
multiple processors, 1/0 boards, and peripheral
boards. The MULTIBUS system bus is supported
with a board array of board level produCts. VLSI interface components, detailed published specifications and application notes.

3-88

inter

iSBC® 286/10A SINGLE BOARD COMPUTER

share the MULTIBUS system bus with an external
parallel priority decoder. In addition to multiprocessing configuration made possible with multi master capability, it also provides a very efficient mechanism
for all forms of DMA (Direct Memory Access) transfers.

SYSTEM BUS-EXPANSION CAPABILITIES

Memory and I/O capacity may be expanded and additional functions added using Intel MULTIBUS compatible expansion boards. Memory may be expanded by adding user specified combinations of RAM
boards, EPROM boards, bubble memory boards, or
combination boards. Input/output capacity may be
added with digital I/O and analog I/O expansion
boards. Mass storage capability may be achieved by
adding single or double density diskette controllers,
or hard disk controllers. Modular expandable backplanes and cardcages are available to support multiboard systems.

HIGH SPEED OFF-BOARD MEMORY

The iSBC 286/10A board can access off-board
memory either over the MULTIBUS (P1) interface, or
over the P2 interface as shown in Figure 3. Memory
transfers over the P2 interface are faster because
the CPU board doesn't have to arbitrate for access
to the MULTIBUS interface.

SYSTEM BU5-MULTIMASTER CAPABILITIES

Using the P2 interface, the iSBC 286/1 OA Board can
be configured to operate with either a standard iLBX
interface or with· a high-performance, synchronous
interface.

For those applications requiring additional processing capacity and the benefits of multiprocessing (i.e.,
several CPUs and/or controllers logically sharing
system tasks through communication of the system
bus), the iSBC 286/1 OA board provides full system
bus arbitration control logic. This control logic allows
up to three iSBC 286/10A board or other bus masters, including the iSBC 80 board family of MULTIBUS compatible 8-bit single board computers to
share the system bus using a serial (daisy chain)
priority scheme and allows up to 16 masters to

The iSBC 286/10A Board as supplied is configured
to operate with a synchronous, P2 interface. This
high-performance interface is designed to connect
to Intel's new EX series of memory expansion
boards to yield a CPU to memory read/write time of
o wait-states. The EX memory expansion boards are
available in sizes ranging from 512K bytes up to 4M

280079-3

Figure 2. MULTIBUS® System Architecture

3-89

inter

iSBC® 286/10A SINGLE BOARD COMPUTER

280079-4

Figure 3. MULTIBUS® liLBXTM/Synchronous Interface Configurations
bytes and available in sizes ranging from 512K bytes
up to 2M bytes; Memory expansion boards from oth'
er manufact~rers that meet the iLBX standard may
also be used. GPU to memory access time is usually
1 or more wait-states depending on the speed of the
memory used.

Software Support
Software support from Intel includes the iRMX 86,
iRMX 286, and XENIX' operating systems, assembly and high level languages, development systems,
in-circuit emulators, and various other hardware and
software tools.

A total of four memory boards can be placed on the
iLBXor synchronous interface bus. With 4M byte
memory boards, this results in a total of 16M bytes
on the memory expansion bus.

iSBXTM BUS MULTIMODULETM ON-BOARD
EXPANSION
Two 8/16-bit iSBX MULTIMODULE connectors are
provided on the iSBG 286/10A microcomputer
board. Through these connectors, additional onboard I/O functions may be added. iSBX MULTIMODULEs optimally support functions provided by
VLSI peripheral components such as additional parallel and serial I/O, analog I/O, small mass storage
device controllers (e.g., bubble cassettes and floppy
disks), and other custom interfaces to meet specific
needs. By mounting directly on the single board
computer, less interface logic, less power, simpler
packaging, higher performance, and lower cost result when compared to other alternatives such as
MULTIBUS Board form factor compatible boards.
The iSBX interface connectors on the iSBG 286/
10A provide all signals necessary to interface to the
local on-board bus, including 16 data lines for maximum data transfer rates. iSBX MULTIMODULE
boards designed with 8-bit data paths and using the
8-bit iSBX connector are also supported on the iSBG
286/1 OA microcomputer board. A broad range of
iSBX MULTIMODULE options are available from Intel. Gustom iSBX modules may also be designed. An"
iSBX bus interface specification and iSBX connectors are available from Intel.

3-90

For those applications needing a real-time, multitasking operating system, Intel offers the iRMX 86
and iRMX 286 operating systems. The iRMX operating systems are particularly well suited for industrial
or commercial applications where the processor is
simultaneously controlling multiple, real-time, interrupt intensive processes. Typical applications include machine and process control, data aquisition,
signal processing, front-end processing, and digital
PABX control. The iRMX operating systems employ
a highly configurable, modular structure that allows
easy system configuration and expansion.
The iRMX 86 operating system enables the iSBG
286/10A board to address up to 1MB of memory in
real address mode. Using the iRMX 286 operating
system, this address range is extended to 16 MB in
native mode. The iRMX 286 operating system also
allows the user to take advantage of the hardware
traps built into the 80286 processor that provide expanded debug capabilities and increased code reli-'
ability.
Application code written for the iRMX 86 operating
system can be compiled using 286 compilers to run
under the iRMX 286 operating system. Application
code will require only minor changes.
Assembly and many high level languages are supported by the iRMX operating systems and Intellec®
Series IV development systems. Language support
for the iSBG 286/10A board in real address board

inter

iSBC® 286/10A SINGLE BOARD COMPUTER

includes Intel's ASM 86, PLIM 86, PASCAL 86,
FORTRAN 86, and C86, as well as many third party
8086 languages. Language support for native address mode include ASM 286, PLIM 286, PASCAL
286 and FORTRAN 286. Programs developed in
these languages can be downloaded from an Intel
System 310 or Series IV Development System to the
iSBC 286/10A board via the iSDM System Debug
Monitor. The iSDM monitor also provides on-target
program debugging support including breakpoint
and memory examination features.

NOTE:

Basic instruction cycle is defined as the fastest instruction time (i.e., two clock cycles)

Local Memory
Number of sockets-Four 28-pin JEDEC sites, expandable to 8 sites using iSBC 341 JEDEC Expansion Module
Maximum Size-256 KB

Intel also offers the XENIX operating system which
is designed for those applications needing an interactive, multiple user system. Typical applications include small business systems, software development/ engineering workstations, distributed data processing, communications, and graphics.

Compatible Devices-EPROM, up to 64K x 8 (Intel
27512)

Dual-Port Memory
Number of sockets-Four 28-pin JEDEC sites, expandable to 8 sites using iSBC 341 JEDEC Expansion Module

Intel's XENIX operating system is a fully licensed derivative of UNIX', enhanced by Intel to provide device driver support for Intel board and component
products plus other features that yield greater flexibility, increased reliability, and easier configurability.
Intel's XENIX operating system has been optimized
for use with the 80286 microprocessor and supports
such features as on-chip memory management and
protection which provide ease of portability and
higher performance.

Maximum Size-128 KB
Compatible Devices-EPROM, up to 32K x 8 (Intel
27256)
SRAM
iRAM, up to 8K x 8 (Intel 2186)
E2PROM, up to 2K x 8 (Intel 2817A)

Applications software can be written in either Intel's
FORTRAN, COBOL, or BASIC languages using a
XENIX-based, Intel 286/310 or 286/380 system, or
by using an Intel iDISTM Database Information System. The user can also select from a wide variety of
existing third party languages and applications software.

Off-Board Physical Memory
Operating
System

iRMX 86 Rise. 6
iRMX 286 Rise. 1
XENIX Rise. 3

SPECIFICATIONS
Word Size

Address
Mode

Real
Native
Native

Size

1MB
16 MB
16 MB

1/0 Capability

Instruction-8, 16, 24, 32 or 40 bits
Data-8 or 16 bits

Parallel-Line printer interface, on-board functions,
and four non-dedicated input bits
Serial-Two programmable channels using one
8274 device

System Clock
CPU-8.0 MHz
Numeric Processor-5.3 or 8.0 MHz (Jumper Selectable)

Timers-Three programmable timers using one
8254 device

Cycle Time

Expansion-Two 8/16-bit iSBX MULTIMODULE
connectors

Basic Instruction-8.0 MHz-375 ns; 250 ns (assumes instruction in queue)

3-91

inter

iSBC® 286/10A SINGLE BOARD COMPUTER

BAUD RATES
Baud Rate (Hz)

Frequency (kHz)
(Software Selectable)

Synchronous

Reference: 1.23 MHz

+ 16

+32

+64

615.
307.
154.
76.8
56.0
38.4
19.2
9.6
4.6
2.4
1.2
0.6

615,000
307,000
154,000
76,800
56,000
38,400
19,200
9,600
4,800
2,400
1,200
600

615,000
307,000
154,000
76,800

38,400
19,200
9.600
4,800

19,200
9,600
4,800
2,400.

9,600
4,800
2,400
1,200

2,400
1,200
600
300
150
75

1,200
600
300
150
75

600
300
150
75

Asynchronous

38,400
19,200
9.600
4,800
2,400
1,200
600

Interrupt Capacity

Serial Communications
Characteristics

Potential Interrupt Sources-25, 5 fixed; 20 jumper
selectable
.

Synchronous-5-8 bit. characters; internal or
HOLC/SOLC character synchronization; automatic
sync insertion; even or odd parity

Interrupt Levels-16 vectored requests using two
8259As and the 80286's NMI line.

Asynchronous-5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits; false start bit de-·
tection; even or odd parity

Timers
Input Frequencies-1.23 MHz ±0.1% or 3.00 MHz
± 0.1 % (Jumper Selectable)

OUTPUT FREQUENCIES/TIMING INTERVALS
Single Timer/Counter
Function
Real-Time Interrupt
Programmable One-Shot
Rate Generator
Square-Wave Rate. Generator
Software Triggered Strobe
Hardware Triggered Strobe
Event Counter

Dual Timer/Counter
(two timers cascaded)

Min

Max

Min

Max

667 ns
667 ns
18.8 Hz
18.8 Hz
667 ns
667 ns

53.3 ms
53.3 ms
1.50 MHz
1.50 MHz
53.3 ms
53.3 ms
8.0 MHz

1.33 JIos
1.33 JIos
0.000286 Hz
0.000286 Hz
1.33 JIos
1.33 JIos

58.2 min
58.2 min
750 kHz
750 kHz
58.2 min
58.2 min

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iSBC® 286/10A SINGLE BOARD COMPUTER

MATING CONNECTORS (OR EQUIVALENT PART)
# of Pins

Centers (in)

Connector Type

Vendor

Vendor Part No.

iSBX Bus Connector
16-Bit (J5, J6)

0.1

Soldered

Viking

000293-001

1/0 Connectors
(J1-J3)

0.1

Flat Crimp

3462-0001

Front Panel
Connector (J4)

0.5

Flat Crimp

3385-6014

iLBX/Synch. Interface
Edge Connector (P2)

0.1

Flat Crimp

KEL-AM
T & BAnsley

RF30-2803-5
A3020

Function

INTERFACES

Physical Characteristics

MULTIBUS Bus-All signals TTL compatible

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.4 in. (1.0 cm)
.
Minimum Slot Spacing: 0.6 in. (1.5 cm)
Weight: 14 oz. (397 gm)

iSBX Bus-All signals TTL compatible
iLBX Bus-All signals TTL compatible
Synchronous Interface-All signals TTL compatible

Electrical Characteristics

Serial I/O-Channel A: RS232C/RS422/RS449
compatible, DCE or DTE; Channel B; RS232C compatible, DCE only

DC Power Requirements:
(serial I/O)

NOTE:
User supplied 34487 line driver and SIP termination
resistor need to be installed for RS422/RS499 operation.

+ 5V, 7.0A; ± 12V, 50 mA

NOTE:
Does not include power for optional EPROM,
E2PROM, or RAM memory devices, or installed
MULTIMODULE boards

Timer-All signals TTL compatible

Environmental Characteristics

Interrupt Requests-All TTL compatible

Operating Temperature: O°C to 60°C with 7 CFM airflow across board

MULTIBUS® DRIVERS
Function

Characteristic

Sink Current (rnA)

Data
Address
Commands
Bus Control

Tri-State
Tri-State
Tri-State
Open Collector

16
16
32
20

Relative Humidity: to 90% (without condensation)

Reference Manual
147532-001-iSBC® 286/10A Hardware Reference
Manual (order separately)

iLBXTM DRIVERS
Function
Data
Address
Commands
Bus Control

Characteristic
Tri-State
Tri-State
Tri-State
TTL

ORDERING INFORMATION

Sink Current (rnA)
9
20
8
8

3-93

Part Number

Description

SBC 286/10A

Single Board Computer

iSBC® 286/12,286/14,286/16
SINGLE BOARD COMPUTERS
High-Speed Interface for
8 MHz 80286 Microprocessor
• Two
• Synchronous
o Wait-State Read!Write to EX Memory
JEDEC 28-Pin Sites for up to 128K
• Bytes of Local EPROM Memory,
Expansion Boards
iLBXTM Interface for iLBX Memory
Expandable to 256K Bytes Using an
• Board Expansion
iSBC® 341 Expansion Module
1, 2, or 4 Megabyte, 0 Wait-State,. Dual16 Levels of Vectored Interrupt Control
• Port,
• Centronics-Compatible
Parity Memory
Para"ell/O
•
Printer Interface
Supports User Insta"ed 80287 Numeric
• Data Processor and 82258 Advanced
Programmable Multiprotocol
• Two
DMA Controller Devices
Synchronous! Asynchronous Serial
iSBXTM Bus Interface Connectors
• Two
for I/O Expansion

Interfaces; One RS232C, the Other
RS232C or RS422!449 Compatible

. The iSBC 286/12, iSBC 286/14, and iSBC 286/16 Single Board Computers are members of Intel's high
performance family of 16-bit microcomputers. The boards feature an 80286 microprocessor running at 8 MHz
together with 1, 2, or 4 megabytes of dual-ported, 0 wait-state, parity memory. These features make the iSBC
286/12/14/16 boards the ideal single board solution for applications requiring high performance and up to 1,
2, or 4 megabytes of memory. For those applications needing more memory, up to four memory expansion
boards may be connected to the iSBC 286/12/14/16 boards over its P2 interface. The P2 interface supports
both standard iLBX memory boards and Intel's EX series of synchronous, 0 wait-state, memory boards that
provide up to 16 megabytes of system memory. The iSBC 286/12/14/16 boards also feature two sockets for
user installed 80287 Numeric Data Processor and 82258 Advanced Direct Memory Access Controller devices.
These components further increase board performance by off-loading time intensive tasks from the 80286
microprocessor. The iSBC 286/12/14/16 CPU boards are true single-board solutions that also include two
serial 1/0 channels, one parallel line printer channel, local memory, interrupt controllers and programmable
timers all on one board.

280147-1

'XENIX is a registered trademark of Microsoft Corp.
"UNIX is a trademark of Bell Laboratories.

3-94

September 1986
Order Number: 280147-002

iSBC® 286/12, iSBC® 286/14, iSBC® 286/16 SBC

with Intel's 8088 and 8086 CPUs. The 80286 CPU
runs 8088 and 8086 code at substantially higher
speeds due to its parallel architecture. In addition,
the 8028S CPU provides on-chip memory management and protection and virtual memory addressing
of up to 1 gigabyte per task. Processing speed and
efficiency may be further enhanced by installing an
80287 numerics coprocessor and an 82258 ADMA
controller. The clock rates for the 8028S and the
80287 are independent with the 80287 rate jumper
selectable at either 5.3 MHz or 8.0 MHz.

FUNCTIONAL DESCRIPTION
Overview
The iSBC 286/12/14/16 boards utilizes the powerful 80286 CPU within the MULTIBUS® system architecture, enhanced by the industry standard iLBX bus
and a new, 0 wait-state, synchronous memory interface, to provide a high-performance 16-bit solution.
This board features 1, 2, or 4 megabytes of dualport, 0 wait-state, parity memory, plus interrupt,
memory and I/O features facilitating a complete single-board computer system. The iSBC 286/12/14/
16 boards can be used in many applications originally designed for Intel's other 16-bit microcomputers.
Only minor changes to the system hardware or applications software may be required to match the application to the iSBC 286/12/14/16 boards. These
changes may include adjusting software timing
loops, changing the Oumper) default configuration of
the board, and using pin and socket I/O connectors
in place of edge connectors.

Instruction Set
The 80286 instruction repertoire includes variable
length instruction format (including double operand
instructions), 8'bit and 1S-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data, and iterative word and byte string manipulation functions.

Numeric Data Processor
For enhanced numerics processing capability, the
80287 Numeric Data Processor extends the 80286
architecture and data set. Over SO numeric instructions offer arithmetic, trigonometric, transcendental,

Central Processing Unit
The central processor for the iSBC 286/12/14/16
board is the 80286 CPU operating at an 8.0 MHz
clock rate. The 80286 CPU is upwardly compatible

280147-2

Figure 1. iSBC® 286/12 Block Diagram
3-95

iSBC® 286/12, iSBC® 286/14, iSBC® 286/16 SBC

logarithmic and exponential instructions. Supported
data types include 16-, 32-, and 64-bit integer, 32and 64-bit floating point, 18-digit packed BCD and
80-bit temporary. The 80287 meets the IEEE P754
standard for numeric data processing and maintains
compatibHity with 8087-based systems.

structions, and addressing modes. The 80286 processor is upward compatible with the 8086, 8088, and
80186 CPUs.
The 80286 operates in two modes: 8086 real address mode, and protected. virtual address mode. In
8086 real address mode, programs use real address
with up to one megabyte of address space. Programs use virtual addresses in protected virtual address mode, also called protected mode. In protected mode, the 80286 CPU automatically maps 1 gigabyte of virtual addresses per task into a 16 megabyte real address space. This mode also provides
memory protection to isolate the operating system
and ensure privacy of each task's programs and
data. Both modes provide the same base instructio'n
set and registers.

Advanced DMA Controller
For those applications that require frequent moving
of large blocks of data, the user may install an Intel
82258, 4 channel, advanced DMA (ADMA) controller
to further increase system performance. The ADMA
Controller supports DMA requests from the 8274
USART (2 channels) and the iSBX interfaces on the
. board (1 per interface). The ADMA can also perform
data transfers over the on-board CPU bus, the MULTIBUS (P1) interface, and the iLBX/synchronous
(P2) interface. With this arrangement, the device can
rapidly move blocks of data between the iSBC 286/
12/14/16 boards and iSBX MULTIMODULETM
Boards installed on the baseboard, between the
iSBC 286/12/14/16 boards and other boards installed in the system, or between any other memory/controller/I/O boards installed in the system.

Vectored Interrupt Control
Incoming interrupts are handled by two on-board
8259A programmable interrupt controllers (PIC) and
by the 80286's NMI line. Interrupts originating from
up to 15 sources are prioritized and then sent to the
CPU. The 8259 devices support both polled and
vectored mode of operation. Further interrupt capability is available through bus vectored interrupts
where slave 8259 interrupt controllers resident on
separate iSBC Boards supply an interrupt vector to
the on-board CPU.

ARCHITECTURAL FEATURES
The 8086, 8088, 80186 and 80286 microprocessor
family contains the same basic set of registers, in-

Table 1. Interrupt Request Sources
Function

Number of
Interrupts

MULTI BUS Interface

Requests from MULTIBUS resident peripherals or other CPU boards

8259A Programmable
Interrupt Controller

8 level vectored interrupt request from slave 8259A

Device

8274 Serial Controller

6 internal interrupt requests directed to master 8259A

8255A Line Printer Interface

Signals output buffer empty. Directed to slave PIC

8254 Timers

Timer 0, 1 outputs; function determined by timer mode

iSBX connectors

Function determined by iSBX MULTIMODULE board Directed to
slave PIC

Bus Fail Safe Timer

Indicates addressed MULTIBUS resident device has not responded
to command within 10 ms

2
2 periSBX
Connector

Power Fail Interrupt

Indicates AC power is not within tolerance (from power supply)

ADMA Interrupt

Common interrupt for 4 DMA channels

Parity Interrupt

Parity error indicator from memory module

On-Board Logic

Conditioned interrupt source from edge sense latch, inverter, or OR
gate

Bus Request Error

Indicates CPU was unable to access the MULTIBUS interface

External Interrupt

Supports system front panel reset switch

NOTE:
'May be expanded to 56 with slave 8259A PICs on MULTIBUS boards.

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iSBC® 286/12, iSBC® 286/14, iSBC® 286/16 SBC

Interrupt Sources

Programmable Timers

Twenty-six potential interrupt sources are routed to
the slave PIC device and to the interrupt jumper matrix where the user can connect the desired interrupt
sources to specific interrupt levels. Table 1 includes
a list of devices and functions supported by interrupts.

The iSBC 286/12/14/16 boards provide three independent, fully programmable 16-bit interval timers/
event counters utilizing the Intel 8254 Programmable
Interval Timer. Each counter is capable of operating
in either BCD or binary modes. Two of these timers/
counters are available to the systems designer to
generate accurate time intervals under software
control. Routing for the outputs of these counters is
jumper selectable. The outputs may be independently routed to the 8259A Programmable Interrupt
Controller or to the 8274 MPSC to count external
events or provide baud rate generation. The third
interval timer in the 8254 is dedicated to providing a
clock for the programmable baud rate generator in
the iSBC 286/12/14/16 boards' MPSC serial controller. The system software configures each timer
independently to select the desired function. Seven
functions are available as shown in Table 2. The
contents of each counter may be read at any time
during system operation.

Memory Capabilities
DUAL-PORT MEMORY
The iSBC 286/12/14/16 boards feature 1, 2, or 4
megabytes of 0 wait-state, parity memory installed
on the board. This memory, which is implemented
using 256 Kb or 1 Mb DRAMs installed on a daughter board, is dual-ported to the on-board CPU bus
and the MULTIBUS (P1) interface. For those applications requiring more memory, the iSBC 286/121
14116 boards also feature an iLBX and synchronous
memory interface to increase physical memory capacity to 16 megabytes.

Table 2. Programmable Timer Functions

LOCAL MEMORY

Function

Operation

Interrupt on
Terminal Count

When a terminal count is reached,
an interrupt request is generated.
This function is extremely useful for
, generation of real-time clocks.

Programmable
One-Shot

Output goes low upon receipt of an
external trigger edge or software
command and returns high when
terminal count is reached. This
function is retriggerable.

Rate Generator

Divide by N counter. The output will
go low for one input clock cycle,
and the period from one low going
pulse to the next is N times the
input clock period.

Square-Wave
Rate Generator

Output will remain high until onehalf the count has been completed,
and go low for the other half of the
count.

Software
Triggered
Strobe

Output remains high until software
loads count (N). N counts after
count is loaded, output goes low
for one input clock period.

Hardware
Triggered
Strobe

Outputs goes low for one clock
period N counts after rising edge
counter trigger input. The counter
is retriggerable.

Event Counter

On a jumper selectable basis, the
clock input becomes an input from
the external system. CPU may read
the number of events occurring
after the counter "window" has
been enabled or an interrupt may
be generated after N events occur
in the system.

Two, 28-pin sites are provided for installing up to
128 KB of EPROM firmware.
By installing an iSBC 341 EPROM expansion module, local memory can be increased to four sites to
support up to 256 KB of EPROM. Local memory access time is selectable at one, two, or three waitstates and is a function of the speed of the devices
used.

Serial 110
A two-channel serial communications interface using Intel's 8274 Multi-Protocol Serial Controller
(MPSC) is contained on the iSBC 286/12114/16
boards. Two independent software selectable baud
rate, generators (% of the 8254 timer) provide the
MPSC with all common communication frequencies.
The protocol (i.e. asynchronous, bisync, or SDLCI
HDLC), data format, control character format, parity
and baud rate are all under program control. Software interfacing to the MPSC can be via either a
polled or interrupt driven routine. Channel A may be
configured for an RS232C or RS422/RS449 interface; channel B is set for RS232C operation only.
DMA operation for channel A is available if the optional 82258 (ADMA) is installed. The data, clock,
control, and signal ground lines for each channel are
brought out to two 26-pin, pin and socket connec'
tors.

3-97

iSBC® 286/12, iSBC® 286/14, iSBC® 286/16SBC

Three jumpers on the iSBC 286112/14/16 boards
let the software determine, by examining bits 0, 1,
and 2 of port B, the board type (iSBC 286/10A
board or iSBC 286/12/14/16 board), and the presence of hardware options (82258 ADMA and 80287
Numeric Data Processor devices) installed on the
board. The parallel port assignment is shown in Table 3.

Line Printer Interface/Board 10
An 8255A Programmable Peripheral Interface (PPI)
provides a Centronics compatible line printer interface, several on-board functions, and four non-dedicated input bits. Drivers are provided for a complete
Centronics compatible line printer interface. The onboard functions implemented with the PPI are Power
Fail Sense, Lock Override, NMI Mask, Clear Timeout
Interrupt, LED 1 and 4, Clear Edge Sense flop, and
MULTlBUS interface directed interrupts (2). The
PPI's I/O lines are divided into three eight bit ports;
A, B, and C. The PPI must be programmed for mode
o with ports A and C used as outputs and port B as
input A 16-bit write to Port B is used to set the iSBC
286/12/14/16 boards into 24 bit address mode.

Software Reset
The software reset feature allows the 80286 microprocessor to return to Real Address mode operation
from PVAM under software control. The system reset line (INIT') and the dual-port memory are not
affected, and all 1/0 context is preserved. The software reset is activated by a byte write to 1/0 location '
OOEOH. To distinguish the software reset from a true
system initialization reset, a flag is provided. Another
flag is provided that indicates whether the iSBC
286/12/14/16 board hardware (not the 80286 device) is currently configured for PVAM or Real Address Mode.

Table 3. Parallel Port Bit Assignment
Port A-Output
Bit
0
1
2
3
4
5
6
7

Function
Line
Line
Line
Line
Line
Line
Line
Line

Printer Data Bit 0
Printer Data Bit 1
Printer Data Bit 2
Printer Data Bit 3
Printer Data Bit 4
Printer Data Bit 5
Printer Data Bit 6
Printer Data Bit 7

Front Panel Connector-J4
A 14-pin connector is mounted on the top edge of
the board and is designed to connect to the front
panel and power supply of the system enclosure.
Leads supported include Reset and Interrupt input
lines from (conditioned) front panel switches, a Run
signal to drive a front panel LED, a Power Fail Interrupt line that connects to the power supply, and extra power and ground leads to support miscellaneous front panel circuitry.

Port B-Input
Bit
0
1
2
3
4
5
6
7

Function
Board 10 Bit 0
Board 10 Bit 1
Board 10 Bit 2
LPT Interrupt (Active High)
Line Printer ACK/(Active Low)
Power Fail Sense/(Active Low)
Line Printer Error (Active High)
Line Printer Busy (Active High)

MULTIBUS® SYSTEM ARCHITECTURE
Overview
The MULTIBUS system architecture includes three
bus structures: the system bus, the local bus extension and the iSBX MULTIMODULE expansion bus
as shown in Figure 2. Each bus structure is optimized to satisfy particular system requirements. The
system bus provides a basis for general system design including memory and I/O expansion as well as
multiprocessing support. The local bus extension allows large amounts of high performance memory to
be accessed from a CPU board over a private bus.
The MULTIMODULE extension bus is a means of
adding inexpensive I/O functions to a base CPU
board. Each of these three bus structures are implemented on the iSBC 286/12/14/16 boards providing a total system architecture solution.

Port C-Output
Bit

Function

0
1
2
3
4
5
6
7

Line Printer Data Strobe (Active High)
Overridel (0 = lock asserted)
NMI Mask (0 = NMI Enabled)
Clear Timeout Interrupt (Active High)
LED 0 (1 =On); Clear Edge Sense Flopl
MULTIBUS Interrupt 1 (Active High)
MULTIBUS Interrupt 2 (Active High)
LED 1 (1 = On); Clear Line Printer
ACK Flop/(Active High)

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iSBC® 286/12, iSBC® 286/14, iSBC® 286/16 SBC

ed by adding user specified combinations of RAM
boards, EPROM boards, bubble memory boards, or
combination boards. Input/output capacity may be
added with digital 1/0 and analog 1/0 expansion
boards. Mass storage capability may be achieved by
adding single or double density diskette controllers,
or hard disk controllers. Modular expandable backplanes and cardcages are available to support multiboard systems.

System Bus-IEEE 796
The MULTI BUS system bus is Intel's industry standard, IEEE 796, microcomputer bus structure. Both
8- and .16-bit single board computers are supported
on the IEEE 796 structure with 24 address and 16
data lines. In its simplest application, the system bus
allows expansion of functions already contained on
a single board computer (e.g., memory and digital
1/0). However, the IEEE 796 bus also allows very
powerful distributed processing configurations using
multiple processors, 1/0 boards, and peripheral
boards. The MULTIBUS system bus is supported
with a broad array of board level products, VLSI interface components, detailed published specifications and application notes.

System Bus-Multimaster Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (i.e.,
several CPUs andlor controllers logically sharing
system tasks through communication of the system
bus), the iSBC 286/12/14/16 boards provide full
system bus arbitration control logic. This control logic allows up to three iSBC 286/12/14/16 boards or
other bus masters, including the iSBC 80 Board family of MULTIBUS compatible 8-bit single board computers to share the system bus using a serial (daisy

System Bus-Expansion Capabilities
Memory and 110 capacity may be expanded and additional functions added using Intel MUTLIBUS compatible expansion boards. Memory may be expand-

280147-3

Figure 2. MULTIBUS® System Architecture

3-99

iSBC® 286/12, iSBC® 286/14, iSBC® 286/16 SBC

chain) priority scheme and allows up to 16 masters
to share the MULTIBUS system bus with an external
parallel priority decoder. In addition to multiprocessing configuration made possible with multimaster capability, it also provides a.very efficient mechanism
for all forms of OM A (Direct Memory Access) transfers.

except the total amount of on-board DRAM memory
is 2 or 4 MB, and the dual-port memory space is
larger. The memory map, which shows the default
configuration of the board, may be easily changed
by the user to meet the needs of almost any' system
deSign. As a result, the iSBC 286/12114116 boards
are particularly suited for complex multiple processor and lor multiple intelligent lID board-based systems.

Memory Map
The memory map of the iSBC '286/12/14/16 board
is shown in Figure 3. The memory maps for the iSBC
286114 and iSBC 286/16 boards are similar,

The memory map can be changed by moving onboard jumpers or by installing user-programmed
PALs (programmable array logic devices).

REAL ADDRESS MODE
OFFFFFH
OFOOOOH

64 KB

1-_ _'"

OEFFFFH
64 KB
OEOOOOH

OFFFFFH

LOCAL EPROM
MEMORY

OEOOOOH

MULTIBUSf> WINDOW
(RELOCATABLE
VIA JUMPERS OR PALS)

ODFFFFH

128 KB

SINGLE PORT MEMORY (CLOSED
TO THE MULTIBUS" INTERFACERELOCATABLE VIA JUMPERS)

896 KB

ON·BOARD DUAL·PORT RAM
(AVAILABLE TO THE MULTIBUS"
INTERFACE)

ODFFFFH

896 KB

ON·BOARD
DUAL·PORT
RAM

OOOOOH ' -_ _....J

OOOOOH 1 -_ _- '

CPU MEMORY MAP

ON· BOARD, DUAL·PORT MEMORY
VIEWED FROM MULTIBUS® PORT

PROTECTED VIRTUAL ADDRESS MODE (PVAM)
FFFFFFH
64 KB

LOCAL
EPROM
MEMORY

960 KB

MULTIBUS'"
INTERFACE

FFOOOOH
FEFFFFH
FOOOOOH

FFFFFFH

RELOCATABLE
VIA PALS

15MB

USER
DEFINED

FFFFFH
14MB

iLBXTM
INTERFACE

1 MB

ON·BOARD
DUAL·PORT RAM

100000H

OFFFFH
OOOOOOH

CPU MEMORY MAP

OFFFFFH
1 MB
OOOOOOH

ON·BOARD DUAL·PORT RAM (CAN·
BE SINGLE PORTED TO THE CPU IN
64 KB INCREMENTS VIA JUMPERS)

MEMORY VIEWED FROM MULTIBUS® PORT

Figure 3. Memory Map for ISBC® 286/12 Board (Default Configuration)

3-100

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iSBC® 286/12, iSBC® 286/14, iSBC® 286/16 SBC

Using qnly the jumpers on the iSBC 286/12/14/16
board, the MULTIBUS window size can be set at 0
(no window), 64 KB, 128 KB, 256 KB, or 1 MB in real
address mode. The MULTIBUS window is normally
not available in PVAM, however, a PAL may be programmed to provide this feature. Jumpers are also
used to set aside a portion of the dual-port memory
so that it may only be accessed by the CPU (singleported memory). Block sizes of 64 KB, 128 KB, 256
KB, 512 KB or 1 MB may be selected. Finally, jumpers are used to select any of 6 EPROM memorY
sizes ranging from 4 'KB (using 2716 devices) up to
256 KB (using 27512 devices and an iSBC 341 module).
If the user needs to alter the memory map further,
five PALs on the baseboard are socketed and may
be replaced by custom designed devices. Using programmed PALs, the designer can:
- Set the base DRAM memory starting address (as
viewed by the 80286 microprocessor) at 0 (default configuration) or to any % megabyte boundary up through 16 MB (0 or 512 KB in real address mode).
-

Set the base DRAM memory starting address (as
viewed by other boards over the MULTIBUS interface) at 0 (default configuration) or ~o any
megabyte boundary up through 16 MB (fixed at 0
in real address mode).

Set single or multiple MULTIBUS windows as
small as 64 KB or as large as 1 MB within the
first megabyte of address space. MULTIBUS
windowing can be enabled both in real address
mode and PVAM. The window size can also be
set at 0 (no window) so that the CPU can only
access its own DRAM memory.

The jumper and PAL changes may be used in combination with each other. For example, jumpers can
be installed to set EPROM address space and to
exclusively allocate (single-port) a portion of the
dual-port memory to the CPU. Then, PALs can be
installed to establish two MULTIBUS windows of different sizes and to set the DRAM base starting addresses.

High Speed Off-Board Memory
The iSBC 286/12/14/16 boards can access offboard memory either over the MULTIBUS (P1) interface, or over the P2 interface as shown in Figure 4.
Memory transfers over the P2 interface' are faster
because the CPU board doesn't have to arbitrate for
access to the MULTIBU$ interface.
Using the P2 interface, the iSBC 286/12/14/16
boards can be configured to operate with either a
standard iLBX interface or with a high-performance,
synchronous interface.
The iSBC 286/12/14/16 boards as supplied are
configured to operate with a synchronous, P2 inter-

280147-4

Figure 4. MULTIBUS® liLBXTM/Synchronous Interface Configurations

3-101

inter

iSBC® 286/12, ISBC® 286/14, iSBC® 286/16 SBC

face. This high-performance interface is designed to
connect to Intel's EX series of memory expansion
boards to yield a CPU to memory readlwrite time of
o wait-states. The EX memory expansion boards are
available in sizes ranging from 512K bytes up to 4M
bytes.
By moving several jumpers on the board, the iSBC
286112/14/16 Single Board Computers may be reconfigured for an iLBX interface, and are compatible
with Intel's CX series of memory expansion boards,
which are available in sizes ranging from 512K bytes
up to 2M bytes. Memory expansion boards from other manufacturers that meet the iLBX standard may
also be used. CPU to memory access time is usually
1 or more wait-states depending on the speed of the
memory used.
A total of four memory boards can be placed on the
iLBX or synchronous interface bus. With 4M byte
memory boards, this results in a total of 16M bytes
on the memory expansion bus.

iSBXTM Bus MULTIMODULETM
On-Board Expansion
.
Two 8-, 16-bit iSBX MULTIMODULEconnectors are
provided on the iSBC 286/12/14/16 boards.
Through these connectors, additional on-board 1/0
functions may be added. The iSBX MULTIMODULE
Boards optimally support functions provided by VLSI
peripheral components such as additional parallel
and serial 1/0, analog 1/0, small mass storage de·"
vice controllers (e.g., floppy disks), and other custom interfaces to meet specific needs. By mounting
directly on the single board computer, less interface
logic, less power, simpler packaging, higher performance, and lower cost result when compared to other
alternatives such as MULTIBUS Board form factor
compatible boards. The iSBX interface connectors
on the iSBC 286/12/14/16 boards provide all signals necessary to interface to the local on-board
bus, including 16 data lines for maximum data transfer rates. The iSBX MULTIMODULE Boards designed with 8-bit data paths and using the 8-bit iSBX .
connector are also supported on the iSBC 286/121
14116 microcomputer boards. A broad range of
iSBX MULTIMODULE Board options are available
from Intel. Custom iSBX modules may also be designed. An iSBX bus interface specification is available from Intel.
.

SOFTWARE SUPPORT
Software support from Intel includes the iRMX 86,
iRMX 286, and XENIX· Operating Systems, assem-

bly and high level languages, development systems,
in~circuit emulators, and various other hardware and
software tools.
For those applications needing a real time, multitasking operating system, Intel offers the iRMX 86
Release 6 and iRMX 286 Release 1. Operating Systems. The iRMX operating systems are particularly
well suited for industrial or commercial applications
where the processor is simultaneously controlling
multiple, real time, interrupt-intensive processes.
Typical applications include machine and process
control, data acquisition, signal processing, frontend processing, and digital PABX control. The iRMX
operating systems employ a highly configurable,
modular structure that allows easy system configuration and expansion.
The iRMX 86 Release 6 Operating System enables
the iSBC 286/12/14/16 boards to address up to 1
MB of memory in real address mode. Using the
iRMX 286 Operating System, this address range is
extended to 16 MB in protected mode. The iRMX
286 Operating System also allows the user to take
advantage of the hardware traps built into the iAPX
286 processor that provide expanded debug capabilities and increased code reliability.
Applications software written for earlier releases of
the iRMX 86 Operating System is upwardly compati- .
ble through Release 6. Furthermore, application
code written for the iRMX 86 Operating System can
be compiled using 286 compilers to run under the
iRMX 286 Operating System. Application code will
require only minor changes.
Assembly and many high level languages are supported by the iRMX Operating Systems and Intellec@ Series III and Series IV development systems.
Language support for the iSBC 286/12/14/16
boards in real address mode includes Intel's ASM
86, PL/M 86, PASCAL 86, FORTRAN 86, and C86,
as well as many third party 8086 languages. Language support for protected address mode include
ASM 286, PL/M 286, PASCAL 286, and FORTRAN
286. Programs c:leveloped in these languages can be
downloaded from an Intel Series III or IV Development System to the iSBC 286/12/14/16 boards via
the iSDMTM 286 System Debug Monitor. The iSDM
286 monitor also provides on-target program debugging support including breakpoint and memory examination features.
Intel also offers the XENIX operating system which
is designed for those applications needing an inter- .
active, multiple user system. Typical applications include small business systems, software ·develop-

3-102

inter

iSBC® 286/12, iSBC® 286/14, iSBC® 286/16 SBC

mentlengineering workstations, distributed data processing, communications, and graphics.
Intel's XENIX operating system is a fully licensed derivative of UNIX", enhanced by Intel to provide device driver support for Intel board and component
products plus other features that yield greater flexibility, increased reliability, and easier configurability.
Intel's XENIX operating system has been optimized
for use with the 80286 microprocessor and supports
such features as on-chip memory management and
protection which provide ease of portability and
higher pe~ormance.
Applications software can be written in either Intel's
FORTRAN, COBOL, or BASIC languages using a
XENIX based, Intel 2B6/310 or 2B6/3BO system, or
by using an Intel iDISTM Database Information System. The user can also select'from a wide variety of
existing third party languages and applications software.

SPECIFICATIONS

Local Memory
Number of sockets-two 28-pin JEDEC sites, expandable to 4 sites using iSBC 341 JEDEC Expansion Module
Maximum Size-12B KB expandable to 256 KB by
installing an iSBC 341 EPROM Expansion Module.
Memory size is set by jumpers on the iSBC 2B6/121
14116 board.
Compatible Devices-EPROM, up to 64K x B (Intel
27512)

Off-Board Physical Memory
Operating
System

Address
Mode

Size

iRMX 86 Release 6 O.S.
iRMX 2B6 Release 1 O.S.
XENIX Release 3 O.S.

Real
Protected
Protected

1 MB
16MB
16MB

Socket provided for Intel B2258, 4 channel, advanced DMA controller. Data transfer rate = 4 MB
per second (two cycle transfer mode, memory to
memory); 2.67 MB per second (16-bit iSBX 1/0 to
dual-port memory).

Word Size
Instruction-B, 16, 24, 32 or 40 bits
Data-B or 16 bits

Interrupt Capacity
System Clock

26 interrupt sources (total); 5 hard-wired to the
8259A PIC; 21 jumper selectable

CPU-B.O MHz
Numeric Processor-5.3 MHz or 8.0 MHz (Jumper
Selectable)

Interrupt Levels-16 vectored requests using two
B259A devices and the 80286 microprocessor's NMI
line

Cycle Time

1/0 Capability

Basic Instruction-B.O MHz - 250 ns (assumes instruction in queue)

Parallel

Line' printer interface, on-board functions, and 3-bit board installed options
code

Serial

Two programmable channels using
one B274 device

NOTE:
Basic instruction cycle is defined as the fastest instruction time (i.e. two clock cycles)

Dual-Port Memory
1, 2, or 4 megabyte, 0 wait-state, parity DRAM dualported to the on-board CPU bus and the MULTIBUS
interface. ,

Three programmable timers using one
8254 device
Expansion- Two 8/16-bit iSBX MULTIMODULE
connectors

Timers

3-103

inter

iSBC® 286/12, iSBC® 286/14, iSBC® 286/16 SBC

Timers
Input Frequencies-1.23 MHz±0.1% or 4.00 MHz
± 0.1 % (Jumper Selectable)

OUTPUT FREQUENCIES/TIMING INTERVALS
Single Timer/Counter
Function
Real-Time Interrupt
Programmable One-Shot
Rate Generator
Square-Wave Rate Generator ,
Software Triggered Strobe
Hardware Triggered Strobe
Event Counter

Dual Timer/Counter
(two timers cascaded)

Min

Max

Min

Max

500 ns
500 ns
18.8 Hz
18.8 Hz
500 ns
500 ns

53.3 ms
53.3 ms
2.0 MHz
2.0 MHz
53.3ms
53.3 ms
8.0 MHz

1.0/Ls
1.0/Ls
0.000286 Hz
0.000286 Hz
1.0/Ls
1.0/Ls

58.2 min
58.2 min
1 MHz
1 MHz
58.2 min
58.2 min

Interfaces

Serial Communications Characteristics

MULTIBUS Bus-All si~nals,TTL compatible
iSBX Bus-All signals TTL compatible

Synchronous-5-8 bit characters; internal or
HDLC/SDLC character synchronization; automatic
sync insertion; even or odd parity

iLBX Bus-All signals TTL compatible

Asynchronous-5-8 bit characters; break character
generation; 1, 1%, or 2 stop bi1s; false start bit detection; even or odd parity

Synchronous Interface-All signals TTL compatible
Serial I/O- Channel A: RS232C/RS422/RS449 '
compatible, DCE or DTE
Channel B: RS232Ccompatible, DCE

BAUD RATES
NOTE:
,',
'
For RS422/RS449 operation, ,user supplied line
drivers and resistor terminators must be installed.
Timer-All signals TTL compatible

Synchronous-600, 1.2 KB, 2.4 KB, 4.8 KB, 9.6 KB,
19.2 KB, 38.4 KB, 56 KB, 76.8 KB, 154 KB, 307 KB,
615 KB.

Interrupt Requests-All TTL compatible

Asynchronous-75, 150, 300, 600, 1.2 KB, 2.4 KB,
4.8 KB, 9.6 KB, 19.2 KB.

MULTIBUS® DRIVERS

NOTE:
Baud rates are software selectable.

Function

Type

Sink Current (mA)

Data
Address
Commands
Bus Control

Tri-State
Tri-State
Tri-State
Open Collector

64
24
32
16/32

iLBXTM DRIVERS
Function

Type

Sink Current (mA)

Data
Address
Commands
Bus Control

Tri-State
Tri-State
Tri-State
TTL

64
24
24
24

Physical Characteristics
Width: 12.00 in. (30.48 cm)
Height: 7.05 in. (18.00 cm)
Depth: 0.88 in. (2.24 cm)
1.16 in. (2.95 cm) with iSBX
MULTIMODULE board installed
flecommended Slot spacing (without iSBX MULTIMODULE): 1.2 in. (3.0 cm)
Weight: 26 oz. (731 gm)

3-104

iSBC® 286/12, iSBC® 286/14, iSBC® 286/16 SBC

Mating Connectors (or Equivalent Part)
# of Pins

Centers (in)

Connector Type

Vendor

Vendor Part No.

iSBX Bus Connector
16-Bit (J5, J6)

0.1

Soldered

Viking

000293-0001

I/O Connectors
(J1-J3)

0.1

Flat Crimp

3399-6026

Front Panel
Connector (J4)

0.5

Flat Crimp

3385-6014

iLBX/Synch. Interface
Edge Connector (P2)

0.1

Flat Crimp

KEL-AM
T & B Ansley

RF30-2803-5
A3020

Function

Electrical Characteristics

Reference Manual

DC Power Requirements:

147533- iSBC 286/12/14/16 Hardware Reference
Manual (order separately)

Maximum: +5V, 8.7A; ±12V, 35 mA (for serial 110)

ORDERING INFORMATION

Typical: +5V, 5.7A; ±12V, 20 mA
NOTE:
Power requirements are for the default configuration. Does not include power for optional EPROM,
80287 or 82258 devices, or installed iSBX MULTIMODULE boards.

Part Number Description

SBC 286/12 Single Board Computer with 1 MB of
Memory
SBC 286/14 Single Board Computer with 2 MB of
Memory
SBC 286/16 Single Board Computer with 4 MB of
Memory

Environmental Characteristics
Operating Temperature: ObC to 60·C with 8 CFM airflow across board (default
configuration)

C80287-3
080287-8
R82258-8

Relative Humidity: to 90% (without condensation)

3-105

Numeric Processor Ext., 5 MHz
Numeric Processor Ext., 8 MHz
ADMA Coprocessor, 8 MHz

iSBC® 337A
MULTIMODULETM NUMERIC
DATA PROCESSOR
•

High Speed Fixed and Floating Point
Functions for 8 MHz or 5 MHz iSBC®
86, 88 and iAPX 86, 88 Systems

•

Supports Seven Data Types Including
Single and Double Precision Integer
and Floating Point

•

Extends Host CPU Instruction Set with
Arithmetic, Logarithmic,
Transcendental and Trigonometric
Instructions

•

Software Support through ASM 86/88
Assembly Language and High Level
Languages

•

MULTIMODULETM Option Containing
8087 Numeric Data Processor

Fully Supported in the Multi-Tasking
Environment of the iRMXTM 86
Operating System

•

Up to 80X Performance Improvement in
Whetstone Benchmarks over 8 MHz
IAPX-86/10 Performance

The Intel iSBC® 337A MULTIMODULETM Numeric Data Processor offers high performance numerics support
for iSBC 86 and iSBC 88 Single Board Computer users, for applications including simulation, instrument
automation, graphics, signal processing and business systems. The coprocessor interface between the 8087
and the host CPU provides a simple means of extending the instruction set with over 60 additional numeric
instructions supporting seven additional data types. The MULTIMODULE implementation allows the iSBC
337 A module to be used on all iAPX 86/88 board designs, all iSBC 86/88 single board computers and can be
added as an option to custom iAPX board designs.

280077-1

3-106

October 1988
Order Number: 280077-001

iSBC 337A MULTIMODULE BOARD

The iSBC 337A MULTI MODULE Numeric Data Processor (also called NDP) provides arithmetic and logicaL instruction extensions to the 86/88 of the iAPX
86/88 families. The instruction set consists of arithmetic, transcendental, logical, trigonometric and exponential instructions which can all operate on seven different data types. The data types are 16-, 32-,
and 64-bit integer, 32- and 64-bit floating point, 18
digit packed BCD and 80-bit temporary.

All synchronization and timing signals are provided
via the coprocessor interface with the host CPU.
The two processors also share a common address/data bus. (See Figure 2.) The NDP component is capable of recognizing and executing NDP
numeric instructions as they are fetched by the host
CPl). This Interface allows concurrent processing by
the host CPU and the NDP. It also allows NDP and
host CPU instructions to be intermixed in any fashion to provide the maximum overlapped operation
and the highest aggregate performance.

Coprocessor Interface

High Performance and Accuracy

The coprocessor interface between the host CPU
and the iSBC 337A MULTIMODULE provides easy
to use and high performance math processing. Installation of the iSBC 337 A is simply a matter of removing the host CPU from its socket, installing the
iSBC 337A MULTIMODULE into the host's CPU
socket, and reinstalling the host CPU chip into the
socket provided for it on the iSBC 337A MULTIMODULE (see Figure 1).

The 80-bit wide internal registers and data paths
contribute significantly to high performance and minimize the execution time difference between single
and double precision floating point formats. This 80bit architecture provides very high resolution and accuracy.

OVERVIEW

This precision is complemented by extensive 'exception detection and handling. Six different types of
exceptions can be reported and handled by the
NDP. The user also has control over internal precision, infinity control and rounding control.

HOST CPU

CONNECTOR FOR
INTERRUPT REQUEST
FROM Isec. 337 A

280077-2

Figure 1. iSBC® 337A MULTIMODULE Installation

3-107

iSBC 337A MULTIMODULE BOARD

ADDRESS /DATA BUS
ADDR/DATA

HOST CPU
ClK (8 MHz)
8284A
CLOCK
GEN

READY

STATUS II NES

RESET

STATUS
TEST

OS RO/GT

-- ----- -- -BUSY

'-----i

.----

----~

I
I
I
I
I

OS RO/GT
STATUS

I
I

ADDR/DATA
I
I
I
I
I

8087
NDP
ISBCI family
of boards. The iSBCI!> 386112 series provides increased 110 performance and functionality. and full
compatibility with past 80286·based MLJLTIBUS I single board computers for easy design migration.
Extensive use of surface mount technology combined with new memory and 110 controller designs
enables both speed and functionality to be improved over previous generation boards. A variety of
models is available. differing in speeds. amount of on·board DRAM memory. and installation of a
math coprocessor.

FEATlJRES
• 16 or 20 MHz 80386 microprocessor and
optional 80387 numeric coprocessor
• ADMA Advanced DMA Controller
• Dual·bus architecture with separate high·
handwidth execution bus
• I-16MB of 32·bit. dual·port. on·board. parity
DRAM

o Sockets for up to 1MB EPROM memory
• Two serial and one parallel 110 ports
• iLBX'" bus and two iSBX'" Bus Interface
Connectors
• Multiprocessor support. including memory
aliasing
• Upward·compatible from iSBC 286112 single
board computers

intel"-------------'Imel Cmpm:l1l1Jll aS$Uml'S flll rl'S~)I'lSlhllll~ ftll' th!.' UM' uf an~ mrU;lf~ lItl\.'r llian ml'UlLty I'mhlldn~d in an IIlI.CJ product Nn Illher drruil pall'lll rj['(~n~'s all'
Implll'd. InforrnalJon (omaml.'d ht'tt'lfl supl'rs~:dt'S prl'~iUl.Lsl~ plIhllstlt'd slX-'rifir'almns WI Lht'IW lJl:vin's frum Intel and is suhjL':C-l Lu chang<' wilhnul nnticl'.
·3Rfi IS a lradl'ffiar~ Ilr Intl'! Curpllralilin

ScptcmtM:r. HlIlt!
Order Number. 21-1U671-001

3-119

FEATIlRES
386 ItIICIlOPIlOCESSOR
PERI'ORItI,4NCE
Using advanced design techniques from Inters first
generation. 386 chip-based CPL' boards. the iSBC 386112
series olTers an immediate 2X performance increase over
8086 and 80286-based MULTIBUS CPU boards. Computing
performance is optimized by an on-board. high speed. 32·bit
execution bus connecting the 386 CPU. 80387 coprocessor.
and 1 to 16MB of dual-ported DRAM memory. Performance
sUlrts with the iSBC 386112 series 16 or 20 MHz 386
processor.

80387 NlIltIERIC COPROCESSOR
Numeric processing speed may be enhanced with a 32-bit
80387 floating point math coprocessor. The 80387 provides
80-bit precision. accelerating floating point calculations
through hardware execution. Matched to the speed of the
386 CPU. the iSBC 386112 series supports the 16 or 20 MHz
versions of the 80387 coprocessor.

DlI,4L-BlIS ,4RCHIf'ECf'lIRE
The iSBC 386112 series uses multiple busses. a design technique that increases system performance. The board
includes both a high-speed 32-bit execution bus malching
the needs of the CPU. and a separate on-bOard bus for 110.
iLl3X. and local r;PROM transfers_ The architecture also
provides separate access to on-board DRAM over MULTlAliS
I and a variety of parallel bus operations. increasing system
performance. For example. other CPU boards can access the
iSBC 386112's dual-ported DRAM over MULTI BUS I while the
iSBC 386112 is handling 110. EPROM. or iLBX operations.
This increases total system responsiveness over all bus and
1/0 transactions.

II'GB-SPEED ItIE/tIORI' CONf'ROUER
On-board DRAM memory is provided on modules attached
III the baseboard. providing from 1 to 16 MB of parity on-,
board DRAM. On·board access is optimized by a high-speed
memory controller and the latest DRAM technology. DRAM
memory is dual-ported and fully addressable from the 32bit on-board bus or from MULTIBUS I. The iSBC 386112
boards also include two 32-pin JEDEC sockets for up to
512 KB of local EPROM using 27020. 2 mc{:abit EPROM
devices_
Memory addressing flexibility surpasses the iSBC 286112.
For example. on-board DRAM memory may be addressed
above the 16MB address space. allowing use of the first
16MB address space for EPROM. iLBX. and MUI.TIBUS I.

HIGH PERI'ORItI,4NCE I/O ,4ND BlIS
CONf'ROUERS
The iSBC 386112 series 110 and bus controllers have heen
designed USing the latest high speed custom logic to speed
up on·board 110 and to maximize throughput over the
MULTI BUS I. dual-port. and iLBX bus interface. As a result.
most applications can expe,ct measurable increases.in
system and 110 performance over other MLiLTIBUS I single
board computers_
In addition. on-board 110 recovery time is handled by the
iSBC 386112 series in hardware. eliminating the need to add
or adiust software delay loops. and optimizing perfo~mance.

COItlPI,Ef'E I/O I'E,4'1'lIRE SEf'
Through extensive use of s'urface mount technology. the
iSBC 386112 series has suhstantially increased the on-board
functionality over previous CPU boards. Each board
provides two serial ports based on Intcrs 8274 MultiProtocol Serial Controller and one parallel port based on the
8255A Programmable Peripheral Interface. It also provides
interrupt support based on two 8259A programmable
interrupt controllers and the 386 chip's own Non Maskable
Interrupt line and programmable timerlcounter functions
based on the 8254 Programmable Interval Timer
Direct memory aceess transfers are provided by the 82258
advanced DMA (ADMA) controller. The ADMA controller has
been further enhanced to increase flexibility and support
synchronous transfers over both of the boards' serial ports
and iSBX Bus Interface Connectors for use in high speed
data communications.

I/O EXP,4NSION lISING 'SBX BlIS
Two iSBX Bus Interface Connectors allow you to add a
variety (If capabilities. such as additional serial or parallel
ports. SCSI. BITBUS. or network controllers. on-board
graphics support. or your own custom-built SBX modules.

ItIl11,f'lBlIS I ,4ND 'UIX CO/tlPU,4NCE
Thc iSBC 386/12 boards support the full MULTIBUS I
speCification. including the MULTIBUS I system bus (with
full Multimaster and bus-vectored interrupt support). the
iLBX local bus extension. and the iSBX MULTIMODULE'"
expansion bus with two iSBX connectors.

/tIlII,f'I-PIlOCESS'NG SlIPPORf'
Multiprocessor support is enhanced through high
performance dual-port arbitration control logic. and features
like "aliasing" mcmory over MULTIBUS I. bus-vectored
interrupts. and the real mode page register (compatible with
the iSBC 86135). In addition. the addressing approach used
in iSBC 38612X13X boards is also supported.

'SBC 286/12 COItIP,4f'1BIUf'1'
The iSBC 386112 series is fully compatible with 80286based CPU boards. so applications can be upgraded with a
simple board swap. To increase performance. only changes
III software timing loops are needed. Some of the features
that provide this level of compatibility are independent
iumber configurable memory maps for real and protected
modes. dual port memory granularity of 64K st'{:ments.
support for bus veclllred interrupts. support for memory
aliasing. and support for the iLBX bus extension. To make
upgrades even eaSier. the iSBC 386112 Series Software .
Upgrade Guide provides an the information for an upgrade
in one conCise document.

DEJ'EI,OPItIENf' SlIPPORf'
To help complete designs. Intel offers a chOice of operating
systems. languages. in-circuit emulators. and other debug
tools_ Real-time operating systems include the iRMX"'-1
Operating System in real mode and the iRMX-1i Operating
System in protected mode applications. For 32-bit
embedded applications Intel olTers the iRMK'" rC8Hime
kernel.

3-120

FEATIJRES
IJPGRADING '1'0 'l'HE ISBC 3B6/12 IS AS EASI' AS I ••• 2 ... 3.

1. Remove your MULTIBUS I. ISOC
80286 based CPU board.

2. Jumper your new ISOC 386/12.

3. Run your application

WORLDWIDE SIJPPOR'I' AND SERJ'ICE

IN'I'EL ()IJALI'I'I'-I'OIJR GIJARAN'I'EE

Assistance in developing and supporting applications is
available through Inters worldwide network of field
application engineers. system engine~rs. customer training
centers and service centers. \\p're experts in developing a
variety of real-time and system applications and can help
make your iSBC 386/12 series design a success.

The iSBC 386/12 series is designed and manufactured in
accordance with Intel's high quality standards. Quality is
verified by rigorous testing in Inters state-of·the·art
Environmental Test Laboratory.

S PE(;I FI~AT ION S
WORD SIZE
Instruction-B. 16.24. 32. or 40 bits
Data-8. 16. or 32 bits

SI'S'I'EM CLOCN
386 CPU: 16 or 20 MHZ
80387 \umeric Coprocessor: matches CPU speed

DIJAL-POR'I' DRAM MEMORI'
- On·board. parity memory
Available with 1. 2. 4. or 8 MB installed
Memory expansion available by plugging in one additional
iSBC MMOxFP module.
Maximum Addressahle Physical Memory:
16 Megabytes in protected virtual address mode. 1
Me{labyte in real address mode. On-board DRAM memory
may be addressed above the 16 MB address space to
allow use of the first 16 MB address space for EPRO~.
iLBX. and MULTIBUS.
Memory Map Granularity:
CPU real mode addressing granularity-64KB
CPU protected mode addressing granularity-64KBIIMB
Dual-port addressing granularity-64KR

EPROM MEMORI'
Two 32·pin JEDEC sockets (compatible with 28 and 32 pin
devices). Maximum Size: 5121-: bytes using 27020 (2 MB)
EPROMs when available. Memory Addressing granularity:
16K blocks using 2764 EPROMs.

IN'I'ERRIJP'I' CIlPACI'I'1'
Interrupt suurces: 26 total. 5 hard·wired to the 8259A PIC.
21 jumper selectable
Interrupt levels: 16 vectored requests using two 8259A
devices and the 80386 CPU's NMlline.
Supports both on·board and bus· vectored interrupts.

I/O CAPABIU'I'I'
ExpanSion: Two 8116·bit iSBX MULTIMODULE connectors.
supporting up to two single·wide. or one single and nne
double-wide iSBX MULTI MODULE boards.
Parallel: Line printer interface. on·board functions. and 3·bit
board installed options code.
Serial: Two programmable channels using one 8274 device
Timers: Three programmable timers using one 8254 device
DMA: Intel 8 or 10 MHz. 82258. advanced DMA (ADMA)
controller. depending on CPU speed. Supports DMA block.
transfers between on·board memory over the MULTIBllS I
interface. iLBX interface. both iSBX interfaces. and both
serial challneis.

SERIAL COMMIJNICA'I'IONS '
CHARIlC'I'ERIS'I'ICS
Synchronous: 5-8 bit characters: internal or HDLClSDLC
character synchronization: automatic sync insertion: even
or odd parity: baud rates from 600 baud to 615 KB.
Asynchronous: 5-8 bit characters: break character
generation: 1. Ilh. or 2 stop bits: false start bit detection:
even or odd parity: baud rates from 75 baud to 19.2 KB.

3-121.

SPE(;I FI(;ATIONS
PHYSIC,U CHARACTERISTICS
Width:
Width:
Depth:

12.00 in. (30.48 em)
7.05 in. (18.00 em)
0.86 in. (2.18 em). "1.62 in. (-t.11 em) with
added memory module

. Recommended slot spacing: 1.2 in. (3.0 em). 1.8 in. (-t.6 em)
with added memory module.
"

INTERFACES
MULTIBL'S 1Bus: All signals TIL compatible
iSBX Bus: All signals TTL compatible
iLBX Bus: All signals TTL compatible
Serial 110: Channel :\: RS232C1RS-I22IRS·I·19 compatible.
DCE or DTE
Channel B: RS232C compatible. DCE
NOTE: For RS422IRS449 operation. line drivrrs and resistor
terminators must be supplied.
Timer: :\11 signals TIL compatible
Interrupt Requests: :\11 TTL compatible

E£ECTRICAL CHARACTERISTICS
DC Power Requirements:
Maximum: + 5\". 14:'1
± 12\"' 35 rna

NOTE: Power requirements are Ihr versions without an
80387 device. Does not include power for:EPROM ..
iSBX MULTIMODULE boards. or iSBC MMOX·FP
memory modules.

ENJIIIlONMENTAL CHARACTERIS'I'ICS
Operating Temperature: OOC to 60°C at 8 CFM airflow
across board (default configuration)
"
Relative Humidity: 0% to 90% (without condensation)
" Stprage Temperature: - 40°C to + 70°C

REFERENCE MANIIALS
-i55fi21l·001 iSBC 386112 Series Hardware Reference
Manual (order separately). Provides complete
inFormation on hardware Features. installation.
jumpering, memory maps. altdre~8ing. and
schematics.
"
-I62435·(J01 iSBC 386/12 Series Software Upgrade Guide
(order separately). Provides complete
information on upgrading existing applications
(hardware and software). from an iSBC
286/1ON12/14/16. iSBC 86130/3fi. or iSBC
386/2X13X to an iSBC 3116112 board.

Typical: + 5\". 9A
± 12\".20 rna

ORDERING INFORMATION
ran N• •ber

rarlNu.ber

iSBC 386112·16FOI

iSBC 386/12·20F'01 20 MHz iSBC with
memory
iSBC 386/12·20r'02 20 MHz iSBC with
memory
iSBC 386/12·20F04 20 MHz iSBC with
memory
iSBC 386/12·20F08 20 MH~ iSBC with
memory

lJetKl'lprltJa
16 MHz iSBC with I \tB DRAM
memory
iSBC 386/12·16F02 16 \IHz iSBCwith 2 ~IB DRAM
memor~

iSBC 386/1 2· 16FO-I 16 MHz iSaC with -I ~IB DRAM
memory
iSBC ~86112·16F08 16 \IHz iSBC with 8 MB DR:\~I
memory

Bescl'lpUOu
I MB DRAM
2 MB DRAM
4 MB DRAM
Il MB DRAM

Models with an installed 80387 coprocessor may be
" fobr more inFormation or the number of your nearest Intel
ordered by adding an \1 suffix to the above order codrs. For sales office. mil 800·548·4725 (good in the V.S .. and
.
example. an iSBC 386/12·20F08~1 is the order rode for a 20 Canada).
MHz iSBC with 8 MR DR:\~lmf'mory and installed 80387
math coprocessor.
To order additional memory. use the following ('uties:
iSBC MMOI·FP
iSBC MM02-FP
iSBC MM04·FP
iSBC MM08·FP

1MB. 85ns parity
expansion module
2 MB. 85ns parity
expansion module
4 MB. 85ns parity
expansion module
8 MR. 85ns parity
expansion module

DRAM memory
DR:\\I memory
DRAM memory
DRAM memory

3-122

intel~
iSBC® 386/21/22/24/28 AND 386/31/32/34/38
SINGLE BOARD COMPUTERS

•
•
•
•
•

Choice of 16 MHz or 20 MHz
386TM Microprocessor
Available with 1,2,4, or 8 Megabytes
of On-Board 32-Bit Memory,
expandable to 16 Megabytes
High Speed 80387 Floating Point Math
Coprocessor
Uses iRMX® or iRMK Kernel Operating
Systems
Complete Starter Kits to Speed
Development

32-Bit JEDEC Sites for up to 512
• Two
Kilobytes of EPROM Memory
RS232C Interface for Local/Remote
• Control
and Diagnostics

•

iSBX® Interface for Low Cost I/O

•
•

16 Levels of Direct Vectored Interrupt
Control

Expansion

64 Kilobyte 0 Wait-State Cache Memory

The iSBC® 386/2x and 3x series boards (iSBC 386/21/22/24/28 and iSBC 386/31/32/34/38) are Intel's
highest performance MULTIBUS® I CPU boards. These boards feature either a 16 MHz or 20 MHz 386 CPU,
an 80387 math coprocessor, a 64k byte, 0 wait-state cache memory to support the CPU, and a 32-bit interface
to 1, 2, 4, or 8 megabytes of dual-port parity DRAM memory. An additional 1, 2, 4, or 8 MB iSBC MMOx series
memory module may be installed to provide up to 16 MB of on-board DRAM memory. The iSBC 386/2x and 3x
boards also feature an 8/16-bit iSBX MULTIMODULE interface for low-cost I/O expansion, an asynchronous
RS232C interface to support a local terminal or modem, two 16-bit programmable timer/counters, a 16-level
direct-vectored interrupt controller, two 32-pin JEDEC sites for up to 512 kb of EPROM memory, and multi master MULTIBUS arbitration logic. The iSBC 386/2x and 3x boards are ideal for applications needing 32-bit
performance together with full MULTIBUS I compatibility.

280602-1

·XENIX is a registered trademark of Microsoft Corp.
·UNIX is a trademark of AT&T.

3-123

October 1988
Order Number: 280602-001

inter

iSBC® 386/21/22/24/28 AND 386/31132134138 BOARDS

OVERVIEW-iSBC 386/2x AND 3x
SERIES CPU BOARDS

16 MHz or 20 MHz
Central Processor Unit

The
iSBC
386/21/22/24/28
and
iSBC
386/31/32/34/38 boards (iSBC 386/2x and 3x series) are Intel's first 32-bit MULTIBUS I single board
computers using the 386 microprocessor. The
boards employ a dual-bus structure, a 32-bit CPU
bus for data transfers between the CPU and memory, and a 16-bit bus for data transfers over the MULTIBUS interface, iSBX interface, EPROM local memory, and I/O interfaces. In this manner, the boards
take advantage of the 386 CPU's 32-bit performance while maintaining full compatibility with the
MULTIBUS I interface and iSBX MULTIMODULE
boards.

The heart of the iSBC 386/2x and 3x CPU board
is the 386 microprocessor. The complete series
includes two lines, with a c~oice of CPU speed.
The iSBC 386/21/22/24/28 boards use the
16 MHz 386 microprocessor and the iSBC
386/31/32/34/38 boards use the 20 MHz 386 microprocessor. The 386 CPU utilizes address pipelining, a high speed execution unit, and on-chip memory management/protection to provide the highest
level of system performance. The 386 microprocessor also features an Address Translation Unit that
supports up to 64 terabytes of virtual memory.

The DRAM memory, which is 011 a module that is
secured to the baseboard, may be expanded by installing a second 1, 2, 4, or 8M byte memory mod- .
ule. A block diagram of the board is shown in Figure

1.
The iSBC 386/2x and 3x series boards can be used
in many applications originally designed for Intel's
other 8- and 16-bit microcomputer based, single
board computers.

The 386 CPU is upward compatible from Intel's
8088, 8086, 80186, and 80286 CPUs. Application
software written for these other 8- and 16-bit microprocessor families can be recompiled to run on the
80386 microprocessor. Some changes to the software such as adjustment of software timing loops
and changing I/O address references may be required; The 386 microprocessor resides on the 32bit wide CPU bus which interconnects the CPU with
the math coprocessor and dual-port memory.

~
~
32·M CPU I MEMORY BUS

.280602-2

Figure USBC@ 386/2x and 3x CPU Board Block Diagram

3-124

inter

iSBC® 386/21122/24/28 AND 386/31132/34/38 BOARDS

Instruction Set

80386 processor is upward compatible with the
8086, 8088, 80186, 80188, and 80286 CPU's.

The 386 CPU instruction set includes: variable
length instruction format (including double operand
instructions; 8-, 16-, and 32-bit signed and unsigned
arithmetic operators for binary, BCD and unpacked
ASCII data; and iterative word and byte string manipulation functions. All existing instructions have been
extended to support 32-bit addresses and operands.
New bit manipulation and other instructions have
been added for extra flexibility in designing complex
software.

Numeric Data Processor
For enhanced numerics processing compatibility,
the iSBC 386/2x and 3x boards include an 80387
numeric coprocessor. Over 60 numeric instructions
offer arithmetic, trigonometric, transcendental, logarithmic and exponential instructions. Supported data
types include 16-, 32-, and 64-bit integer, 32- and
64-bit floating point, 18-digit packed BCD and 80-bit
temporary. The numeric data processor meets the
IEEE P754 (Draft 7) standard for numeric data processing and maintains compatibility with 8087-based
systems. Data transfers to and from the CPU are 32bits wide.

Architectural Features
The 8086, 8088, 80188, 80286, and 386 microprocessor family contain the same basic sets of registers, instructions, and addressing modes. The

Architectural Features
The 386 CPU operates in two modes: protected virtual address mode; and 8086 real address mode. In
protected virtual address mode (also called protected mode), programs use virtual addresses. In this
mode, the 386 CPU automatically translates logical
addresses to physical addresses. This mode also
provides memory protection to isolate the operating
system and ensure privacy of each task's programs
and data. In 8086 real address mode, programs use
real addresses with up to one megabyte of address
space. Both modes provide the same base instruction set and registers.

Interrupt Control
Incoming interrupts are handled by two cascaded
on-board 8259A programmable interrupt controllers
and by the 386's NMI line. Twenty interrupt sources
are routed to the programmable controllers and the
interrupt jumper matrix. Using this jumper matrix, the
user can connect the desired interrupt sources to
specific interrupt levels. The interrupt controllers prioritize interrupts originating from up to 15 sources
and send them to the CPU. The user can connect a
sixteenth interrupt to the 386 NMI line. Table 1 includes a list of devices and functions suported by
interrupts. Bus vectored interrupts are not supported.

Table 1. Interrupt Request Sources
Source

Function

Number of
Interrupts

MULTIBUS® Interface

Aequests from MULTIBUS® resident peripherals or other
CPU baords

8251A Serial Controller

Indicates status of transmit and receive buffers and AI
lead of the AS232C interface

8254 Timers

Timer 0, 1 outputs; function determined by timer mode
(hardwired to interrupt controller)

iSBXTM Connector

Function determined by iSBXTM MULTIMODULETM board

Bus Timeout

Indicates addressed MULTIBUS® or iSBXTM resident device
has not responded to a command within 10 ms

Power Fail Interrupt

Indicates AC power is not within tolerance (signal
generated by system power supply)

Parity Interrupt

Indicates on-board parity error

Programmable Aegister

Generate interrupt under program control

3-125

intJ

iSBC® 386/21/22/24/28 AND 386/31/32/34/38 BOARDS

nostic/monitor routines, application code,and ROMable operating system software. Maximum 'local
memory capacity is 512K bytes using Intel 27020
(256k x 8) 2 megabit EPROM devices. The EPROM
memory resides at the upper end of the 386 device's
memory space for, both real address, mode and
PVAM operation.

Memory Capabilities
The iSBC 386/2x and 3x boards support both
EPROM local memory and dynamic RAM (DRAM),
which is located on-board. The DRAM is supported
by a high speed on-board cache memory.

DRAM Memory

Memory Map

The iSBC 386/2x and 3x series CPU boards come
with 1, 2, 4, or 8M bytes of DRAM memory. This
memory is on a low profile module that is installed
on the baseboard. The module measures approximately 4" x 4" and uses surface mount DRAM devices. The DRAM memory supports byte-parity error
detection and has a 32-bit wide data path to the
80386 CPU and 16-bit wide data path to the MULTIBUS interface.

In real address mode, the maximum amount of· addressable physical memory is 1 Mbyte. In protected
virtual address mode (PVAM), the maximum amount
of addressable physical memory is 1" Mbytes. The
system designer can easily change the CPU memory map to adapt the CPU board to the required overall system memory map. Reconfiguration is usually
necessary for multiple processor-based systems
with more than two CPU boards and/or intelligent
I/O boards. By changing PAL devices and/or by
moving jumpers, the designer can set:

The memory may be expanded by installing an additional iSBC MMOx series memory module" which is
available in 1, 2, 4; or 8M byte sizes. All mounting
hardware is included. Maximu'm DRAM'memory is
16M bytes using an iSBC 386/28 or 386/38 CPU
board and an 8M byte iSBC MM08 memory module.
This combination requires only 1.8 inches of cardcage space.

• EPROM memory space
• Starting address of DRAM memory
• Amount of DRAM memory that is dual-ported to
the CPU and MULTIBUS interface or single-ported to the CPU
• Access to off-board MULTIBUS address space

Cache 'Memory
A 64K byte cache memory on the iSBC 386/2x and
3x boards supports the 386 CPU and provides' 0
wait-state reads for data and program code resident
in the cache memory. The cache memory is updated
whenever data is written into the dual-port memory
or when the CPU executes a read cycle and the data
or program code is not present in cache memory.
This process is controlled by the cache replacement
algorithm. Cache "misses" require additional waitstates to retrieve data from the DRAM memory. If
the processor is in pipelined mode, 2 wait-states (4
clock cycles) are required to retrieve data. If the
processor is in non-pipelined mode, 3 wait-states
are required. All writes to DRAM memory require 2
(pipelined) or 3 (non-pipelined) wait-states,
The cache memory supports 16K entries, with each
entry comprised of a 32-bit data field and an 8-bit tag
field. The tag field is used to determine which actual
memory word currently resides in a cache entry. The'
cache memory size and effective replacement algorithm are designed to optimize both the probability of
cache "hits" and local bus utilization.

EPROM Memory
The EPROM memory consists of two 32-pin JEDEC
sites that are intended for boot-up and system diag-

EPROM Memory
The EPROM memory space is set using four jumpers to accommodate 27256 (256 kb), 27512
(512 kb), 27010 (1 Mb), or 27020 (2 Mb) byte-wide
devices. Smaller EPROM devices may be used,
, however the EPROM will appear more than once
within the EPROM address space. Using a pair of
27020 EPROMs will provide 512k bytes of memory.
The iSBC 386/2x and 3x series boards are designed
to accommodate EPROM devices with access times
ranging from 130 ns-320 ns, In real address mode,
the ending address of EPROM memory is. always
1M byte (FFFFFH). In PVAM, the ending address of
EPROM memory is always 4G bytes (FFFF FFFFH),
which is the top of the 386 CPU address space.

DRAM Memory Size/Location
The iSBC 386/2x and 3x boards allow the user to
control ,the location and size of the DRAM memory
(on the iSBC 386/2x and 3x boards) available for
use by the CPU and other boards in the system. ,In
PVAM,the starting address of DRAM can be set to
start on any 1M byte boundary up through 15M
bytes by setting jumpers and by installing a customprogrammed PAL device. In real address mode, the
DRAM memory always starts at OH (hex).

3-126

intJ

iSBC® 386/21/22/24/28 AND 386/31132134138 BOARDS

The ending address can be set on 64k byte boundaries using jumpers in both PVAM and real address
mode. Setting the ending address at lower than the
actual amount of installed memory effectively deselects a portion of DRAM and creates additional
MULTIBUS address space.

MULTIBUS Address Space
Any address space not set aside as EPROM or
DRAM memory automatically becomes address
space the CPU can use to access other boards in
the system. For example, Figure 2A shows a real
address mode CPU memory map for a 1M byte
iSBC 386/21 board. With the DRAM ending address
set at 512k bytes and 128k bytes of installed
EPROM, 384k bytes of MULTIBUS address space is
accessable by the CPU. Figure 2B shows a typical
PVAM configuration where the 4 Mbytes of DRAM
has been set to start at 1M byte and end at 4.5M
bytes. The address space from 0 to 1M byte and 4.5
to 16M bytes is the MULTIBUS address space accessable by the CPU.

Programmable Timer
Three 16-bit, programmable interval timer/counters
are provided using an 8254 device, with one timer
dedicated to the serial port for use as a baud rate
generator. The other two timers can be used to generate ,accurate time intervals under software control.
The timers are not cascadable. Four timer/counter
modes are available as listed in Table 2. Each counter is capable of operating in either BCD or binary
modes. The contents of each counter may be read
at ailY time during system operation.
Table 2. Programmable Timer Functions

Dual-Port/Local Memory

1MB
128KB

~~B~K~
512KB

Operation
When terminal count is reached,
an interrupt request is generated.
This function is extremely useful
for generation of real-time clocks.

Rate generator Divide by N counter. The output
will go low for one input clock
cycle, and the period from one
low going pulse to the next is N
times the input clock period.

Figure 2C illustrates another way the board can establish additional MULTIBUS address space. If the
DRAM memory starts at 0, a jumper on the board
can be used to create additional MULTIBUS address
space between 512k bytes and 1M byte. This feature is available both in real address mode and
PVAM.

A portion or all of the DRAM memory can be selected to be dual-port (shared) memory. Both the starting and ending addresses are, set on 256k byte
boundaries using jumpers on the board. Any DRAM
memory that is not configured as dual-port memory
is local (single-port) memory available only to the
CPU.

Function
Interrupt on
terminal count

Square-wave
rate generator

Output will remain high until
one-half the count has been
completed, and go low for the
other half of the count.

Software
triggered
strobe

Output remains high until software loads count (N). N counts
after count is loaded, output
goes low for one input clock
period.

Serial 1/0
The iSBC 386/2x and 3x boards include one
RS232C serial channel, which is configured as an

EPROM
MULT1BUS~
ADDRESS
SPACE

DRAM

~...,."...>..>.(

MULTIBUS ~
ADDRESS

~,......~/ACE

1MBm~~/
512KB ~~~

....MULTlBUS·
ADDRESS
SPACE

L-_--'
2B0602-3

Figure 2A. Real Address
Mode iSBC® 386/21
Board Memory Map

Figure 2B. PVAM ,
iSBC® 386/24
Board Memory Map
3-127

Figure 2C. PVAM
iSBC® 386/22
Board Memory Map

inter

iSBC® 386/21/22/24/28 AND 386/31/32/34/38 BOARDS

asynchronous, DTE interface. Data rates up to 19.2k
baud may be selected. The serial channel can connect either to a host system for software development orlo a stand alone terminal for field diagnostic
support. For stand alone use, unhosted monitor software needs to be programmed by the user into the
local EPROM memory. The serial channel may· also
be connected to a modem to provide remote diagnostic support or to download program codes. The
physical interface is a 10-pin ribbon-style connector .
located on the front edge of the board.

local bus extension and the iSBX MULTIMODULE
expansion bus. Each bus structure is optimized to
satisfy particular system requirements. The system
bus provides a basis for general system design including memory and 1/0 expansion as well as multiprocessing support. The iLBX bus, which· is usually
used for memory expansion, is not supported by the
iSBC 386/2x and 3x boards since all DRAM memory
is located on-board. The iSBX bus povides a low
cost way·to add 1/0 to the board.

System Bus-IEEE 796

iSBXTM Interface
For iSBX MULTIMODULE support, the iSBC 386/2x
and 3x CPU boards provide an 8/16-bit iSBX connector that may be configured for use with either 8or 16-bit, single or double-wide iSBXMULTIMODULE boards: Using the iSBX interface, a wide variety
of specialized 1/0 functions can be added easily and
inexpensively to the iSBC 386/2x and 3x boards.

Reset Functions
The iSBC 386/2x and 3x boards are designed to
accept an Auxilliary Reset signal via the boards' P2
. interface. In this way; system designs that require
front panel reset switches are supported. The iSBC
386/2x and 3x boards use the AUX reset signallo
reset all on-board logic (excluding DRAM refresh circuitry) and other boards in the MULTIBUS system.
The iSBC 386/2x and 3x boards will also respond to
an INIT reset signal generated by another board in
the system.

LED Status Indicators
Mounted on the front edge of the iSBC 386/2x and
3x boards are four LED indicators that indicate the
operating status of the board and system. One LED
is used to show that an on-board parity error or a
MULTIBUS bus parity error has occurred. A second
LED indicates that a MULTIBUS or iSBX bus access
timeout has occurred. The third LED is triggered by
the start of an 386 bus cycle and will turn off if the
386 CPU stops executing bus cycles. The fourth
LED will light under software control if the program
writes to a specific 1/0 location.

MULTIBUS® SYSTEM ARCHITECTURE
.Overview
The MULTIBUS system architecture includes three
bus structures: the MULTIBUS system bus, the iLBX

The MULTIBUS system bus is Intel's industry standard, IEEE'796, microcomputer bus structure. Both
8- and 16-bit single board computers are supported
on the IEEE 796 structure with 24 address 'and 16
data lines. In its simplest application, the system bus
allows expansion of functions already contained on
a single board computer (e.g., memory and digital
110). However, the IEEE 796 bus also allows -very
powerful distributed processing configurations using
multiple processors, 1/0 boards, and peripheral
boards. The MULTIBUS system bus is supported
with a broad array of board level·products, VLSI interface components, detailed published specifications and application notes.

System Bus-Expansion Capabilities
The user can easily expand or add features to his
system by adding various MULTIBUS boards to his
system. Products available from Intel and others include: video controllers; DI A and AID converter
boards; peripheral controller cards for floppy disk,
hard disk, and optical disk drives; communicationsl
networking boards; voice synthesis and recognition
boards; and EPROM/bubble memory expansion
.
boards.

System Bus-Multimaster
Capabilities
For those applications requiring additional processing capacity and the benefits of multiprocessing (Le.,
several CPUs and/or controllers sharing system
tasks through communication over the system bus),
the iSBC 386/2x and 3x boards provide full system
bus arbitration control logic. This control logic allows
up to four bus masters to share the system bus using a serial (daisy chain) priority scheme. By using an
external parallel priority decoder, this may be extended to 16 bus masters. In addition to multiprocessing, the multimaster capability also provides a
very efficient mechanism for all forms of DMA (Direct Memory Access) transfers.

3-128

iSBC® 386/21/22124/28 AND 386/31/32/34/38 BOARDS

iSBXTM Bus MULTIMODULETM
On-Board Expansion
One 8-/16-bit iSBX MULTIMOOULE interface is provided on the iSBC 386/2x and 3x microcomputer
boards. Through this interface, additional on-board
1/0 functions may be added, such as parallel and
serial 1/0, analog 1/0, small mass storage device
controllers (e.g., floppy disks), BITBUS Control, and
other custom interfaces to meet specific needs.
Compared to other alternatives such as MULTIBUS I
boards, iSBX modules need less interface logic and
power, and offer simpler packaging and lower cost.
The iSBX interface connector on the iSBC 386/2x
and 3x boards provides all the signals necessary to
interface to the local on-board bus, and is compatible with both 8-bit and 16-bit MULTIMOOULES. A
broad range of iSBX MULTIMOOULE options are
available from Intel. Custom iSBX modules may also
be designed using Intel's "MULTIBUS I Architecture
Reference Book" (order no. 210883) as a guide.

II release 2 software. Application code will require
only minor changes and may then take advantage of
the added memory addressability, code reliability,
and debug capability of the iRMX 286 operating system.
Applications software written for Release 1 of the
iRMX II Operating Systems is upward compatible
with iRMX II Release 2 software.
The XENIX operating system is a very high performance, UNIX operating system. This industry standard
mUlti-user, multitasking operating system, provides a
broad range of programming languages, system
software, and application software for the system
and application designer.
For customers preferring the UNIX operating system, third party software vendors offer UNIX System
V.3.

Languages and Tools
SOFTWARE SUPPORT
Operating Systems
The iSBC 386/2x and 3x boards are supported by a
variety of operating systems, including the iRMX I
Release 8, iRMX II Release 2, and XENIX Release
3.4.2 operating systems from Intel, and System VI
386 operating systems from third party vendors.
The iRMX II Release 2 operating system is a realtime multi-tasking and multi-programming software
system capable of executing all the configurable layers of the iRMX II operating system on the 386 microprocessor and the iSBC 386/2x and 3x single
board computers. Up to 16 MB of physical system
memory is supported. The iRMX II Operating System
also allows the user to take advantage of the hardware traps built into the 386 processor that provide
expanded debug capabilities and increased code reliability.
The iRMX II Release 2 operating system is designed
to support time-critical applications requiring real
time performance in the industrial automation, financial; medical, communications, and data acquisition
and control (including simulation) marketplaces.
Application code written under the iRMX I operating
system can also run on the iSBC 386/2x and 3x
boards. The code may either be. run directly on the
iRMX I operating system, or may be recompiled using Intel's 286 compilers and then run under iRMX

A wide variety of languages is available for the
iRMX, XENIX and System Vi386 operating systems.
For the iRMX II Release 2 operating system, Intel
offers ASM 286, PASCAL 286, PUM 286, C 286,
and FORTRAN 286. For the XENIX operating system Intel offers ASM 386, PLiM 386, C 386, and
PASCAL 386. For the System V1386 Operating System several different software vendors provide selections of languages, including ASM, C, PASCAL,
FORTRAN, COBOL, RPG, PL 1, BASIC, and Artificial
Intelligence programming languages LISP and Arityl
Prolog. Software development tools include
PSCOPE Monitor 386 (PMON 386 and OMON 386),
Softscope 286 (for iRMX II Release 2), and an ICE
386 in-circuit-emulator.

Starter Kits
The iSBC 386/2x and 3x Starter Kits are a set of
hardware, software and support products designed
to allow the user to easily evaluate the iSBC 386/2x
and 3x boards and 386 microprocessor, and to b 1gin system design and software development for
their iSBC 386/2x and 3x applications. The kits include an iSBC 386/2x or 3x board (with memory
module), choice of iRMX II release 2 software or of
the OM ON 38ql020 Oebug Monitor, free admission
to one Customer Training Workshop, valuable discounts on development tools, and complete documentation. Each kit includes ali items at one low
price. The kits come in two major types, either the
iRMX Starter Kits or the OMON-based Starter Kits.
Each of these types are described below.

3-129

iSBC® 386/21/22124/28 AND 386/31/32/34/38 BOARDS

The monitor allows the designer to debug both real
mode and protected mode applications that run on
the iSBC 386/2x and 3x boards.

iRMX® II Release 2-Based iSBC®
386/2x Starter Kits
The iRMX Starter Kits are designed to provide a
complete development solution for new iRMX-based
applications and enable an existing iRMX II Release
1 application to run on the iSBC 386/2x and 3x
boards. The starter kits include the complete iRMX II
Release 2 operating system with single user license
and include a 16-bit debug monitor that supports 16bit application software development either in an ontarget development environment using an Intel
286/310 system or in a host-target development environment using a Series III/IV system. These two
, development environments are shown in Figure 3.

The monitor provides commands that perform the
following functions:
• Bootstrap load the program of your choice
• Examine and modify the contents of the 386 CPU
registers and board memory
• Display the contents of memory and descriptor
,tables
• Load and execute relocatable and absolute object files
• Move blocks of memory from one location to another
.

The starter kit contains diskettes, two 27256
EPROMs, 10 foot serial cables for connection to the
host Series III/IV development system or separate
console
terminal,
and
installation/operating
instructions.
The diskettes provide the iRMX II Release 2 Operating System, ported tg run on the iSBC 386/2x and
3x boards, and 16-bit monitor software. Both 8" ISIS
format and 5%" iRMX format diskette media are
provided. The EPROMs, which the user installs on
the iSBC 386/2x and 3x boards, contain the bootloader, device initialization code, and the debug
monitor. The iRMX 286/310 system or Intellec® Series III/IV development system are user provided.

•
•
•
•

Using the starter kit, designers can generate and debug 16-bit application software either on the host
Intellec system or on the iSBC 386/2x and 3x based
system.
The iRMX II Operating System together with the
monitor support the use of iRMX II 16-bit lan-

INTEL SYSTEM 286/31 0

iSBC® 386
CPU

MONITOR EPROMS

- - . HOST (INTELLEC"')'
TARGET (iSBC" 386/2X)
DEVELOPMENT
ENVIRONMENT

DOCUMENTATION
AND SERIAL CABLES

L - STARTER KIT----.J

- . ON·TARGET
DEVELOPMENT
ENVIRONMENT

• OR •

iRMXTM II
OPERATING SYSTEM

Perform I/O to a specified port
Disassemble and execute instructions
Single-step execution of instructions
Define and examine symbols in a program

INTEllEC® SERIES III, IV
l...-_ _

USER SUPPLIED --.--.J
280602-4

Figure 3. iRMX® Starter Kit Development Environments

3-130

inter

iSBC® 386/21/22/24/28 AND 386/31/32/34/38 BOARDS

guages and tools including ASM 86, ASM 286, PL/M
286, BIND 286, BUILD 286, and AEDIT text editor.
Thirty-two-bit languages are not supported.

On-Target Debug with the DMON
386020-Based iSBC 386/2x and 3x
Starter Kits

The starter kit also allows designers to download all
or part of an existing iRMX II-based application to
the iSBC 386/2x and 3x boards for execution. In
some cases, software timing loops may need to be
readjusted to compensate for the increased clock
rate of the 386 microprocessor. Furthermore, I/O
address references may also need changing to
match the I/O map of the iSBC 386/2x and 3x
boards.

The DMON 386-Based starter kits use the unhosted
DMON 386020 Debug Monitor, which is intended for
debugging embedded, 32-bit code. Once the user
has either downloaded their code (using their own
bootstrap loader) to the iSBC 386/2x and 3x board's
DRAM memory, or programmed their code in
EPROMs and plugged them in the iSBC 386/2x's
and 3x's sockets, DMON may be used to fully debug
the code, including any code using the 386's 32-bit
OMF (object module format).

iRMX I-based 8086 applications will also run on the
iSBC 386/2x and 3x boards under the iRMX I operating system or under the iRMX II operating system
included in the starter kit. To run them under the
iRMX II operating system, the code is first recompiled using 286 compilers. The code is then downloaded to the iSBC 386/2x and 3x boards using the
monitor software. As with other' code, the iRMX I
application code may have to be modified to adjust
software timing loops and I/O address references.

Configuring the On-Target
Development Environment
If the designer chooses to configure an on-target
development environment using an Intel 286/310
system, either a standard SYS 310-40(A), -41 (A), or
-17(A) system may be used.
In addition to the iSBC 386/2x and 3x boards and
memory, other boards that the iRMX II software supports may be installed in the system. These boards
include the iSBC 214/215G1217/218A series of
disk controller boards, the iSBC 188/48 and iSBC
544A 8- and 4-channel communications boards, the
iSBC 350 line printer board, the iSBX 351 2-channel
communications MULTIMODULETM and a RAM
(disk) driver, and many more.

HOST
DEVELOP SMI

The DMON 386020 portion of the DMON-based
starter kits provides DMON in two 27512 EPROMs,
ready for use immediately in an iSBC 386/2x and 3x
board, and in a 5%" diskette, for integration with
other, user-supplied code. Complete documentation
is also included.
The DMON 386020 monitor provides the following
debug capabilities:
• Examine/modify memory, I/O ports, processor
registers, descriptor tables, and the task state
segment
• Evaluate expression
• Control execution both in real and protected
mode
• Set software breakpoints on execution addresses
• Set hardware breakpoints on execution and data
addresses
• Disassemble instructions
The DMON 386020 based starter kit does not provide operating system (O.S.) support. If the application software uses an O.S. interface, the O.S. must
be ported to run with the 386 microprocessor, the
8251A Serial Controller, and the 80387 math coprocessor (if used).

______:_===::::-----.. I
DOWNLOAD

(USER SUPPLIED)

TARGET

EXECUTE CODE
AND DEBUG
DOCUMENTATION

L..-_ _ _ _ USER SUPPLIED - - - - - ' L.._ _ _ _ _ STARTER KIT - - - - - - - '

Figure 4. D-MON386ES Target Development Environment

3-131

280602-5

inter

iSBC® 386/21/22/24/28 AND 386/31/32/34/38 BOARDS

System Compatibility
The iSBC 386/2x and 3x Single Board Computers
are complemented by a wide range of MULTIBUS
hardware and software products from over 200 manufacturers worldwide. This product support enables
the designer to easily and quickly incorporate the
iSBC 386/2x boards into his system design to satisfy
a wide range of high performance applications.
Applications that use other 8- and16-bit MULTIBUS
single board computers (such as Intel's iSBC
286/10A and iSBC 286/12 8 MHz, 80286 based single board computers) can be upgraded to use the
iSBC 386/2x and 3x boards. Changes to hardware
and systems software (for speed and I/O configuration dependent code) may be required.

Sizes accommodated-64 kb (8k x 8),128 kb (16k x
8),256 kb (32k x 8),512 kb (64k x 8), 1 Mb (128k x
8), 2 Mb (256k x 8)
Device access speeds-130 ns to 320 ns
Maximummemory-512k bytes with 27020 (2M bit)
EPA OMs

Type-One AS232C DTE asynchronous channel using an 8251A device

Instruction-8, 16,24,32 or 40 bits
Data-8, 16, 32 bits
System Clock
386 CPU-16 MHz or 20 MHz
Numeric Processor-80387 module-16 MHz or
20 MHz

Data Characteristics-5-8 bit characters; break
character generation; 1, 1%, or 2 stop bits; false
start bit detection; automatic break detect and handling; even/odd parity error generation and detection
Speed-110, 150, 300, 600, 1.2 kb, 2.4 kb, 4.8 kb,
9.6 kb, 19.2 kb

Cycle Time
Instruction:
iSBC
386/21/22/24/28,
Basic
16 MHz-125 ns
iSBC 386/31/32/34/38,20 MHz-100 ns (assumes
instruction in queue)
NOTE:
Basic instruction cycle is defined as the fastest instruction time (Le. two clock cycles)

Memory expansion-One additonal plug-in module:
iSBC MM01-1M byte
iSBC MM02-2M bytes
iSBC MM04-4M bytes
iSBC MM08-8M bytes

Number of sockets-Two 32-pin JEDEC Sites (compatible with 28-pin and 32-pin devices)

Serial Channel

Word Size

On-board parity memory
iSBC 386/21/31 board-1 M byte
iSBC 386/22/32 board-2M bytes
iSBC 386/24/34 board-4M bytes
iSBC 386/28/38 board-8M bytes

EPROM Memory

1/0 Capability

BOARD SPECIFICATIONS

DRAM Memory

Maximum Addressable Physical Memory-16 Megabytes (protected virtual address mode) 1 Megabyte
(real address mode)

Leads supported-TO, AD, ATS, CTS DSA, AI, CD,

SG
Connector Type-10 pin ribbon
Expansion-One 8/16-bit iSBX interface connector
for. single or double wide iSBX MULTIMODULE
board.
Interrupt Capacity
Potential Interrupt Sources-21 (2 fixed, 19 jumper
selectable)
Interrupt Levels-16 using two 8259A devices and
the 80386 NMI line
Timers
Quality-Two programmable timers using one 8274
device
Input Frequency-1.23 MHz ± 0.1%

3-132

iSBC® 386/21/22/24/28 AND 386/31/32134138 BOARDS

Output Frequencies/Timing Intervals
Single Counter

Function
Real-time interrupt
Rate Generator
Square-wave rate generator
Software triggered strobe

Min

Max

1.63 p.s
18.8 Hz
18.8 Hz
1.63 p.s

53.3 ms
615 kHz
615 kHz
53.3 ms

Interfaces

Recommended Minimum Cardcage Slot Spacing
1.2 in. (3.0 cm), with or without iSBX
MULTIMODULE
1.8 in. (4.6 cm), with addded iSBC MMOx memory
module
Approximate Weight
26 oz. (738 gm)
29 oz. (823 gm), with added iSBC MMOx memory
module

Reference Manual

MULTIBUS Bus-All signals TTL compatible
iSBX Bus-All signals TTL compatible
Serial I/O-RS 232C, DTE

149094-iSBC 386/21/22/24/28 Hardware Reference Manual (order separately)

MULTIBUS® DRIVERS

453652-iSBC 386/31/32/34/38 Single
Computer Hardware Reference Manual

Function·

Type

Sink Current (mA)

Data
Address
Commands
Bus Control

Tri-State
Tri-State
Tri-State
Open Collector

64
24
32

16/32

Board

Ordering Information
Part Number Description
CPU Boards
SBC38621

16 MHz 386 MULTIBUS I CPU Board
with 1 MB DRAM Memory

Power Requirements

SBC38622

iSBC 386/2x and 3x boards.
Maximum: + 5V, 12.5A
±12V, 35 mA
Typical:
+ 5V, 9A
±12V, 20 mA

SBC38624

16 MHz 386 MULTIBUS I CPU
with 2 MB DRAM Memory
16 MHz 386 MULTIBUS I CPU
with 4 MB DRAM Memory
16 MHz 386 MULTIBUS I CPU
with 8 MB DRAM Memory
20 MHz 386 MULTIBUS I CPU
with 1 MB DRAM Memory

NOTE:
Does not include power for iSBX module, EPROM
memory, or added iSBCMMOx memory modules.
Add the following power when adding iSBC MMOX
memory modules:
iSBC MM01 +5V,0.71A
MM02 + 5V, 0.96A
MM04 +5V,0.71A
MM08 + 5V, 0.96A

Environmental Requirements
Operating Temperature-O·C to 60·C at 300 LFM
Relative Humidity-O% to 85% noncondensing
Storage Temperature--40·C to +70·C

SBC38628
SBC38631

Board
Board
Board
Board

SBC38632

20 MHz 386 MULTIBUS I CPU Board
with 2 MB DRAM Memory

SBC38634

20 MHz 386 MULTIBUS I CPU Board
with 4 MB DRAM Memory
20 MHz 386 MULTIBUS I CPU Board
with 8 MB DRAM Memory

SBC38638

Memory Modules
1 MB Parity DRAM Memory ExpanSBCMM01
.
sion Module
SBCMM02
SBCMM04
SBCMM08

Physical Characteristics
Dimensions
Width-12.00 in. (30.48 cm)
Height-7.05 in. (17.91 cm)
Depth-0.86 in. (2.18 cm), 1.62 in. (4.11 cm) with
added memory module
3-133

2 MB Parity DRAM Memory Expansion Module
4 MB Parity DRAM Memory Expansion Module
8 MB Parity DRAM Memory Expansion Module

intJ

iSBC® 386/21/22/24/28 AND 386/31/32/34/38 BOARDS

Starter Kits
SBC38621SPKG

Starter Kits
SBC38631SPKG
SBC38621 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38631SPKGR2
SBC38621 SPKGR2 SBC38621 plus iRMX II R.2.
O.S., Monitor, Training, Documentation, and Discount on
tools.
SBC38622SPKG
SBC38622 plus DMON386020
SBC38632SPKG
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38622SPKGR2 SBC38622 plus iRMX II R.2.
SBC38632SPKGR2
O.S., Monitor, Training, Documentation, and Discount on
tools.
SBC38624SPKG
SBC38624 plus DMON386020
SBC38634SPKG
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38624SPKGR2 SBC38624 plus iRMX II R.2.
SBC38634SPKGR2
O.S., Monitor, Training, Documentation, and Discount on
tools.
SBC38628SPKG
SBC38628 plus DMON386020
SBC38638SPKG
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38638SPKR2
DMON386020
Debug Monitor provided in two
media, both in EPROMs for immediate use in the iSBC
386/2x board, and in a 5%"
diskette. Also includes documentation.
SBC38628SPKR2 SBC38628 plus iRMX II R.2.
O.S. Monitor, Training, Documentation and Discount on
tools.
Mating Connectors
No. of Centers Connector
Function
Vendor
Pins
(in)
Type
iSBX Bus
44
0.1
Soldered
Viking
Connector
10
Flat Crimp
3M
Serial RS232C
0.1
Connector
Kel-AM
P2 Interface
60
0.1
Flat Crimp
Edge Connector
T&BAnsley

3-134

SBC38631 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38631 plus iRMX II R.2.
O.S., Monitor, Training, Documentation, and Discount on
tools.
SBC38632 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38632 plus iRMX II R.2.
O.S., Monitor, Training, Documentation, and Discount on
tools.
SBC38634 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38634 plus iRMX II R.2.
O.S., Monitor, Training, Documentation, and Discount on
tools.
SBC38638 plus DMON386020
Debug Monitor, Training, Documentation, and Discount on
tools.
SBC38638 plus iRMX II R.2.
O.S. Monitor, Training, Documentation and Discount on
tools.

Vendor Part
Number
000293-0001
3399-6010
RF30-2803-5
A3020

MULTIBUS® I ,
M.emory Expansion Boards

-n+ _I~
II 1'eI
•
•
•

iSBC® MM01, MM02, MM04, MM08
HIGH PERFORMANCE MEMORY MODULES
to Provide up to 16M Bytes
• ofStackable
High Speed Memory for MULTIBUS I

Provides High Speed Parity Memory
Expansion for Intel's iSBC 386/2X,
iSBC 386/3X and iSBC 386/1XX
CPU Boards

and MULTIBUS II CPU Boards
32-Bit, 16-Bit and 8-Bit Data
• Supports
Paths
Independent Read/Writes
• Supports
Easily Installed
•

Available in 1M, 2M, 4M, and 8M Byte
Sizes
32 Bits Wide with Byte Parity

The iSBC MM01, iSBC MM02, iSBC MM04, and iSBC MM08 DRAM memory modules are members of Intel's
complete line of iSBC memory and I/O expansion boards. The MM-Series of memory modules use a dedicated interface to maximize CPU/memory performance. The iSBC MM series of memory modules have been
designed to provide both the on-board and expansion memory for the iSBC 386/2X, the iSBC 386/3X and the
iSBC 386/1XX CPU Boards.
The modules contain (respectively) 1 M byte, 2M, 4M, and 8M bytes of read/write memory using surface
mounted DRAM components (see Figure 1).
Due to the high speed interface of the memory modules, they are ideally suited in applications where memory
performance is critical.

Figure 1_ iSBC® MM08 Memory Module

4-1

280346-1

September 1988
Order Number: 280346-002

inter

iSBC® MM01, MM02, MM04, MM08 MODULES.

FUNCTIONAL DESCRIPTION

Installation

The iSBC MMxx memory modules provide high performance, 32-bit parity DRAM memory for the MULTIBUS I and MULTIBUS II CPU boards. These CPU
boards come standard with one MMxx module installed, with memory expansion available through
the addition of a second stackable iSBC MMxx module.

The iSBC MMxx memory modules are easily installed by the user. Each module includes all necessary connectors, screws, and other hardware for installation, either as a second stacked module or as a
replacement for a module with less memory.

SPECIFICATIONS
Memory Access Capabilities

Word Size Supported

The dynamic RAM memory of the memory modules
is accessed through the dedicated memory module
interface.

8-, 16-, or 32-bits

Memory Size

The MM memory module is designed for direct
transfer of data between the CPU and the memory
module without accessing the MULTIBUSinterface.

iSBC
iSBC
iSBC
iSBC

MMOllMM02/MM04/MM08
Memory Size

MM01 1,048,576
MM02 2,097,152
MM04 4,194,304
MM08 ·8,388,608

bytes
bytes
bytes
bytes

Access Time (All Densities)

The iSBC MM01, iSBC MM02, iSBC MM04, and
iSBC MM08 modules can be stacked on the CPU
baseboard in any combination.

Read/Write -

107 ns (max)

The MMxx-series memory modules run with the
iSBC 386/2X and iSBC 386/116 Boards at 16 MHz,
and with the iSBC 386/3X and iSBC 386/120
Boards at 20MHz. Wait state performance information with each of these CPU baseboards is contained in the Hardware Reference Manual for the
specific CPU baseboard.

Data Bus Structure
The MMxx-series memory modules use a 32-bit wide
data path with storage for byte parity that can accommodate 8-bit byte, 16-bit or 32-bit word data
transfers. In addition, the data path is capable of
independent byte operations. This means that one
byte can be written while the other three bytes (or
any other combination) can be read.

Cycle Time (All 8ensities)
Read/Write -

200 ns (min)

Parity
Power Requirements

One parity bit is provided for each of the four, 8-bit
bytes in the 32-bit wide data path. For special applications, the parity bits can ~erve as data bits making
possible 9-, 18-, or 36-bit data transfers.

Voltage -5 VDC ±5%

Memory addressing for the iSBC MMxx memory
modules is controlled by the host CPU board over
the memory module interface. The maximum system
RAM size is 16M Bytes.

Memory Function
The module protocol supports standard dynamic
RAM READ, WRITE, RAS' only REFRESH cycles,
and CAS' before RAS* REFRESH.

4-2

inter

iSBC® MM01, MM02, MM04, MM08 MODULES

Top View

ISBC® t.tt.txx
t.tEt.tORY t.tODULE

4.25"
7.05"

CPU BASEBOARD

CONNECTOR

OUTLINE
.. -------.,

Ir. _. _ _ _ _ _ _ ..I

'1-.------'
---4.175" ---.11

280346-2

Side View
ISBC®t.tt.txx
t.tEt.tORY t.tODULE

STANDOFF

0.847"
(:to.023)

CPU BASEBOARD
280346-3

Single iSBC® MMxx Memory Module

Side View
ISBC iRl t.tt.txx
t.tEt.tORY t.tODULES
STIFFENER

1.564"
(:to.D33)

0.525 INCH STACKING CONNECTOR
STANDOFFS
0.625 INCH BASEBOARD CONNECTOR.

CPU BASEBOARD
280346-4

Stacked iSBC® MMxx Memory Modules

4-3

inter

iSBC® MM01, MM02, MM04, MM08 MODULES

ORDERING INFORMATION

Environmental Requirements
Operating Temperature Storage Temperature -

Part Number

O°C to 60°C
40°C to

+ 75°C

iSBCMM01

Description
1M Byte RAM Memory Module

iSBCMM02

2M Byte RAM Memory Module

Cooling Requirement - 3 cubic feet per minute of
airflow at an ambient temperature of O°C to 60°C

iSBCMM04

4M Byte RAM Memory Module

iSBCMM08

8M Byte RAM Memory Module

Operating Humidity without condensation

The Memory Modules ship with the required hard~
ware (connectors, mounting screws, stand-ofts, etc.)
to stack a second module on the module already
mounted on the base CPU board.

To 95% relative humidity

Physical Dimensions
Module Alone:
Width -

4.250 inches (10,795 cm)

Length -

4.175 inches (10,604 cm)

Height -

0.500 inches (1,270 cm)

Weight -

iSBC MM01 IMM04: 2.5 ounces (70.0 gm)
iSBC MM02/MM08: 3.5 ounces (11 0.0 gm)·

4-4

iSBC® 012CX, 010CX, AND 020CX
iLBXTM RAM BOARDS
Dual Port Capability via MULTIBUS®
• and
iLBX Interfaces
Single Bit Error Correction and Double
• Bit
Error Detection Utilizing Intel 8206

Error Status Register Provides Error
• Logging
by Host CPU Board
16 Megabyte Addressing Capability
• Supports 8- or 16-bit Data Transfer and

•
•

ECC Device

•
•

512K Byte, 1024K Byte, and 2048K Byte
Versions Available
Control Status Register Supports
Multiple ECC Operating Modes

24-bit Addressing
Auxiliary Power Bus and Memory
Protect Logic for Battery Back-Up RAM
Requirements

The iSBC 012CX, iSBC 010CX and iSBC 020CX RAM memory boards are members of Intel's complete line of
iSBC memory and 110 expansion boards. Each board interfaces directly to any iSBC 80, iSBC 86, iSBC 186,
,and iSBC 286 Single Board Computers. The dual port feature of the CX series of RAM-boards allow access to
the memory of both the MULTIBUS and iLBX bus interfaces.
In addition to the dual port features the "CX" series of RAM-boards provide Error Checking and Corrections
Circuitry (ECC) which can detect and correct single bit errors and detect, but not correct, double and most
multiple bit errors.
The iSBC 012CX board contains 512K bytes of read/write memory using 64K dynamic RAM components. The
iSBC 010 CX and iSBC 020 CX boards contain 1024K and 2048K bytes of read/write memory using 256K
dynamic RAM components.

231023-1

4-5

September 1988
Order Number: 231023-002

intJ

iSBC® 012CX, 010CX AND 020CX iLBXTM RAM BOARDS

Extension) interface as outlined in the Intel iLBX
Specification (see Figure 1).

FUNCTIONAL DESCRIPTION

General

Dual Port Capabilities

The iSBC 012CX, 010CX, arid 020CX RAM boards
are physically and electrically compatible with the
MULTIBUS interface standard, IEEE-796, as outlined in the Intel MULTIBUS.specificatiori. In addition
the CX series of RAM-boards are physically and
·electrically compatible with the iLBX bus (Local Bus

The "CX" series of RAM-boards can be accessed
by either the MULTIBUS interface or the iLBX interface (see Figure 2). Intel's iLBX interface is an unarbitrated bus architecture which allows direct transfer
of data between the CPU and the memory boards

231023-2 .

Figure 1. TyplcallLBXTM System Configuration

512K
1024K,20HK
BYTES ARRAY

I·
I

231023-3

Figure 2. iSBC® 012CX/010CX/020CX Block Diagram
4-6

iSBC® 012CX, 010CX AND 020CX iLBXTM RAM BOARDS

without accessing the MULTIBUS bus .. Due to the
un arbitrated nature of the iLBX interface significant
improvements in memory access times result, typically a 2-6 Wait State improvement over MUL TIBUS
memory access.

CONTROL STATUS REGISTER
There are six ECC modes of operation in the "CX"
family of RAM boards. Each mode is obtained by
software programming of the CSR from the master
iSBC board. The six modes are:

System Memory Size

a.
b.
c.
d.
e.
f.

Maximum system memory size with this series of
boards is 16 megabytes. Memory partitioning is independent for the MULTIBUS interface and the iLBX
interface.
For MULTIBUS operations, on-board jumpers assign
the board to one of four 4-megabyte pages. Each
page is partitioned into 256 blocks of 16K bytes
each. The smallest partition on any board in this series is 8K bytes. Jumpers assign the base address
(lowest 16K block) within the selected 4-megabyte
page.

Interrupt on any error mode
Interrupt on non-correctable error only mode
Correcting mode
Non-correcting. mode
Diagnostic mode
Examine syndrome word mode

Modes (a) and (b) can be used in conjunction with
(c) and (d). The six modes are described below.
Interrupt on Any Error Mode-In this mode the
RAM board will interrupt the iSBC processor board
when any error (single bit or multiple bit) is detected
by the ECC circuitry.

The iLBX bus memory partitioning differs from the
MUL TIBUS bus partitioning in that the iLBX bus address space consists of 256 contiguous blocks of
64K bytes totaling 16 megabytes. As with the
MULTlBUS bus partitioning, the base addresses are
set with on-board jumpers.

Interrupt on Non-Correctable Error Mode-In this
mode the RAM board will interrupt the iSBC processor board only when a non-correctable (multiple bit)
error is detected by the ECC circuitry. A multiple bit
error is not correctable by the ECC circuitry.
Correcting Mode-In this mode the RAM board
corrects any correctable error (single bit error). Errors which are not correctable are not modified. Interrupts are generated depending on the interrupt
mode selected.

Error Checking and Correcting (ECC)
Error checking and correction is accomplished with
the Intel 8206 Error Checking and Correcting device.
This ECC component, in conjunction with the ECC
check bit RAM array, provides error detection and
correction of single bit errors and detection only of
double bit and most multiple bit errors. The ECC circuitry can be programmed via the Control Status
Register (CSR) to various modes while error logging
is supported by the Error Status Register (ESR).
Both CSR and ESR communicate with the master
CPU board through a single I/O port.

Non-Correcting Mode-In this mode the RAM
board does not correct any error. The ECC circuitry
continues to check for errors, but no corrective action is taken. Interrupts continue as described previously.
Diagnostic Mode-This mode is used for testing
the on-board ECC circuitry. In this mode the write
enable strobe to the ECC RAM array is continuously
disabled. The diagnostic mode can be used to simulate errors and in conjunction with the "Examine
Syndrome Word Mode" examine the check bits generated by the ECC circuitry.

ECC 1/0 Address Selection
The processor board communicates with the ECC
circuitry via a single I/O port. This port is used for
the Control Status Register (CSR) and the Error
Status Register (ESR). The CSR is programmed by
the user to determine the mode of operation while
the ESR provides information about memory errors.

Examine Syndrome Word Mode-This mode, in
conjunction with the diagnostic mode, is used for
testing the ECC memory. In this mode, the syndrome bits/ check bits are clocked into the ESR on
every memory. read/write cycle, respectively. The
ESR translation PROM switches to a transparent
mode in the examine syndrome word mode. This allows the actual syndrome word generated by the
8206 ECC device to be examined.

The iSBC 012CX, iSBC 010CX, and iSBC 020CX
RAM boards are shipped with a Programmed Array
Logic (PAL) device which allows selecting one of 9
possible addresses for the I/O port. The actual selection is done by jumper configuration. Additional
unprogrammed locations are left in the PAL to allow
application specific I/O addresses to be defined.

4-7

inter

iSBC® 012CX, 010CX AND 020CX iLBXTM RAM BOARDS

Table 1. Error Status Register Format
Bit

Bit
Meaning
Error in row

5
0
1
0
1

6
0
0
1
1
Bit

4
0
0
0
0
0
0
0
0
0
0

3
0
0
0
0
0
0
0
0
1
1

2
0
0
0
0
1
1
1
1
0
0

1
0
0
1
1
0
0
1
1
0
0

0
0
1
0
1
0
1
0
1
0
1

0
1
2
3

Meaning

Error in data bit

0
1
2
3.
4
5
6
7
8
9

4
0
0
0
0
0
0

3
1
1
1
1
1
1

2
0
0
1
1
1
1

1
1
1
0
0
1
1

0
0
1
0
1
0
1

1
1
1
1
1
1

0
0
0
0
0
0

0
0
0
0
1
1

0
0
1
1
0
0

0
1
0
1
0
1

1
1

0
1

Meaning
Error in data bit

Error in check bit

10
11
12
13
14
15
0
1
2
3
4
5

No Error
Non-correctable
(multiple-bit error)

Access Times (All densities)

ERROR STATUS REGISTER
The 8-bit register contains information about memory errors. The ESR reflects the latest error occurrence. Table 1 shows the status register format. Bits
5 and 6 show the failing row while bits 0 through 4
indicate which bit (of the 16-bit data word or the 6-bit
EGG syndrome) is in error. Bit 7 is always high.

MULTIBUS® System Bus
Read/Full Write- 380 ns (max)
Write Byte

530 ns (max)

iLBXTM Local Bus

Battery Back-Up/Memory Protect

Read/Full Write- 340 ns (max)

An auxiliary power bus is provided to. allow separate
power to the RAM array for systems requiring backup of read/write memory. An. active lovy TTL .compatible memory protect signal is brought out on the
auxiliary bus connector which, when asserted, disables read/write access to the RAM board. This input is provided for the protection of RAM contents
during system power-down sequences.

Write Byte

440 ns (max)

Cycle Times (All densities)
MULTIBUS® System Bus
Read/Full Write- 490 ns (max)

SPECIFICATIONS

Write Byte

885 ns (max)

Word Size Supported.

iLBXTM Local Bus
Read/Full Write- 375 ns

8- or 16-bits

Write Byte

Memory Size

-740 ns

NOTE:
If an error is detected, read access time and cycle
times are extended to 255 ns (max)

524,288 bytes (iSBG 012GX board)
1,048,576 bytes (iSBG 010GX board)
2,097,152 bytes (iSBG 020CX board)
4-8

inter

iSBC® 012CX, 010CX AND 020CX iLBXTM RAM BOARDS

Memory Partitioning

Environmental Requirements

Maximum System memory size is 16M Bytes for
both MULTIBUS and iLBX BUS. MULTIBUS partitioning is. by Page, Block and Base, while the iLBX
BUS is by Blockand Base only~

Operating Temperature: O°C to 55°C airflow of 200
linear feet per minute
Operating Humidity:
To 90% without condensation

Page Address

Physical Dimensions

MULTIBUS®- 0-4 megabytes; 4-8 megabytes, 812 megabytes; 12-16 megaby1es
iLBXTM BUS - NI A

Width:
Height:
Thickness:
Weight:

Base Address
MULTIBUS® System Bus-Any 16K byte boundary
4M-by1e
within
the
page.
iLBXTM Local Bus
- Any 64K byte boundary
selectable on board
boundaries to 8M-bytes
and some 64K-byte
boundaries in the first
megaby1e. Others available if PAL programming is changed.

30.48 cm (12 inches)
17.15 cm (6.75 inches)
1.27 cm (0.50 inches)
iSBC 012CX board: 6589 gm (23.5
ounces); iSBC 010CX board: 5329 gm
(19.0 ounces); iSBC 020CX board: 6589
gm (23.5 ounces)

Reference Manuals
145158-003-iSBC® 028CX/iSBC® 056CX/iSBC®
012CX Hardware Reference Manual
144456-001-lntel iLBXTM 010CX, 020CX
Specification
9800683-03-lntel MULTIBUS® Specification
Manuals may be ordered from any Intel Sales Representative, Distributor Office or from the Intel Literature Department, 3065 Bowers Avenue, Santa
Clara, CA. 95051

Power Requirements
Voltage-5 VDC ±5%
Product

Current

Standby
(Battery Back-Up)

iSBC® 012CX
Board

4.4A (typ.)
6.8A (max.)

2.2A (typ.)
2.4A (max.)

Part Number
iSBC012CX

iSBC® 010CX
Board

4.8A (typ.)
7.0A(max.)

2.1A (typ.)
2.3A(max.)

iSBC010CX

iSBC® 020CX
Board

5.3A (typ.)
7.5A (max.)

2.2A (typ.)
2.4A(max.)

iSBC020CX

ORDERING INFORMATION

4-9

Description
512K byte RAM board with EGC
and iLBX Connectors
1M by1e RAM board with ECC
and iLBX Connectors
2M by1e RAM board with ECC
and iLBX Connectors

iSBC® 012EX, 010EX, 020EX, and 040EX
HIGH PERFORMANCE RAM BOARDS

•o

Parity Generator/Checker
• On-Board
Independently Selectable Starting and

Wait States at 8 MHz Performance
with the iSBC® 286/10A,
iSBC 286/12 Board

•
•

•

Dual Port Capability Via MULTIBUS®
and High Speed Synchronous Interface

Ending Addresses

16 Megabyte Addressing Capability
• 512K
Byte, 1024K Byte, 2048K Byte,
• and 4096K
Byte Densities Available

Configurable to Function Over
iLBXTM Bus

The iSBC 012EX, iSBC 010EX, iSBC 020EX, and iSBC 040EX RAM memory boards are members of Intel's
complete line of iSBC memory and I/O expansion boards. The EX boards are dual ported between the
MULTIBUS interface and one of two types of dedicated memory buses. The dedicated buses are the iLBX bus
and a high speed interface. The EX series of RAM-boards can be configured to be accessed over the iLBX
bus, as well as MULTIBUS bus, to provide memory support for the iSBC 286/10 board, performing at,6 MHz
and the iSBC 186/03A board, performing at 8 MHz. The EX boards are default configured to run over the
MULTIBUS interface and the high speed interface. This provides 0 wait state 8 MHz memory support for the
iSBC 286/1 OA and iSBC 286/12 boards.
The EX RAM-boards generate byte oriented parity during all write operations and perform parity checking
during all read operations. An on-board LED provides a visual indication that a parity error has occurred.
The iSBC 012EX, iSBC 01 OEX, iSBC 020EX, and iSBC 040EX boards contain 512K bytes, 1M byte, 2M bytes,
and 4M bytes of read/write memory using 256K dynamic RAM components.
Due to the high speed synchronous interface capability of the boards, they are ideally suited in applications
where memory performance is critical.

280142-1

4-10

September 1988
Order Number: 280142-001

inter

iSBC® 012EX, 010EX, 020EX, 040EX BOARDS

FUNCTIONAL DESCRIPTION

SELECTABLE ENDING ADDRESS

General

The ending address is selectable as memory size
minus select options of 0, 128K, 256K, or 512K on
all of the EX boards.

The iSBC 012EX, 010EX, 020EX, and 040EX RAM
boards are physically and electrically compatible
with the MULTIBUS interface standard, IEEE-796,
as outlined in the Intel MULTIBUS architecture specification.

The I/O address of the Parity Interrupt Clear circuitry
is jumperabl.e to anyone of 256 addresses.

Dual Port Capabilities

SPECIFICATIONS

PARITY INTERRUPT CLEAR

The "EX" series of RAM-Boards can be accessed
by the MULTIBUS interface, and either the iLBX
Bus, or the high speed synchronous interface (see
Figures 1 and 2). The EX series require jumper and
PAL configuration to be accessed over iLBX Bus.

Word Size Supported
8- or 16-bits.

Intel's iLBX interface is an un arbitrated bus architecture which allows direct transfer of data between the
CPU and the memory boards without accessing the
MULTIBUS bus. Due to the unarbitrated nature of
the iLBX interface, significant improvements in memory access times compared to the MULTIBUS bus
accesses result. The EX Boards provide 1 wait state
performance at 6 MHz and 2 wait states at 8 MHz
over the iLBX board. The EX Memory Board Hardware Reference Manual should be consulted for details.

Memory Size
524,288 bytes (iSBC 012EX board)
1,048,576 bytes (iSBC 01 OEX board)
2,097,152 bytes (iSBC 020EX board)
4,194,304 bytes (iSBC 040EX board)

Access Times (All densities)
MULTIBUS® SYSTEM BUS

The high speed synchronous interface, like the iLBX
Bus, is a bus architecture which allows direct transfer of data between the CPU and the memory
boards without accessing the MULTIBUS bus. This
high speed interface runs synchronously with the
iSBC 286/10A and iSBC 286/12 to provide 0 wait
state performance at 8 MHz.

Write Byte- .

System Memory Size

Write Byte-

Read/Full Write- 375 .ns (max)
375 ns (max)
HIGH SPEED SYNCHRONOUS INTERFACE

Read/Full Write- 167 ns (max)

Maximum system memory size with this series of
boards is 16 megabytes. Memory partitioning is independent for the MULTIBUS interface and the iLBX
interface.

132 ns (max)

iLBXTM BUS

Read/Full Write- 295 ns (max)
116 ns (max)

Write Byte-

Address Selection/Memory

Cycle Times (All densities)

SELECTABLE STARTING ADDRESS

MULTIBUS® SYSTEM BUS

A 256K boundary select is implemented on the iSBC
012EX board. A 512K boundary select is implemented on the iSBC 01 OEX board. A 1M boundary is implemented on the iSBC 020EX and iSBC 040EX
boards.

Read/Full Write- 625 ns (max)
Write Byte-

4-11

625 ns (max)

iSBC® 012EX, 010EX, 020EX, 040EX BOARDS

HIGH SPEED SYNCHRONOUS INTERFACE

PHYSICAL DIMENSIONS

Read/Full Write- 250 ns (max)
Write Byte
- 250 ns (max)

Width:
Height:

12 inches (30.48 cm)
6.75 inches (17.15 cm)

Thickness: 0.50 inches (1.27 cm)
iLBXTM BUS

Weight:

Read/Full Write- 437.5 ns (max)
Write Byte.

iSBC 010EX board: 9.0 ounces
(2550 gm)
iSBC 020EX board: 13.5 ounces
(3830 gm)

437.5 ns (max)

Memory Partitioning

iSBC 040EX board: 18.0 ounces
(5100 gm)

Maximum System memory size is 16M Bytes for the
MULTIBUS, iLBX bus and the high speed interface.

REFERENCE MANUALS

BASE ADDRESS
Board

Base Address

iSBC 012EX Board

any 256K boundary in
first 4 megabytes

iSBC 010EX Board

any 512K boundary in
first 8 megabytes

iSBC 020EX Board

any 1M boundary

iSBC 040EX Board

any 1M boundary

147783-001- iSBC012EX/iSBC 010EX/iSBC
020EX/iSBC 040EX Hardware
Reference Manual
9800683-03-'- Intel MULTIBUS Specification
144456-001- Intel iLBX Specification
Manuals may be ordered from any Intel Sales Representative, Distributor Office or from the Intel Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

Power Requirements

ORDERING INFORMATION

VOltage-5 VDC ± 5%
Product

Current

iSBC 012EX Board

3.2A (typ)
4.9A (max)

iSBC 01 OEX Board

3.4A (typ)
5.0A (max)

iSBC 020EX Board

3.7A (typ)
5.2A (max)

iSBC 040EX Board

3.9A (typ)
5.5A (max)

Part Number
iSBC012EX

Description
512K byte RAM board with parity,
iLBX connectors, and high speed
interface

iSBC010EX

1M byte RAM board
iLBX connectors, and
interface
2M byte RAM board
iLBX connectors, and
interface
4M byte RAM board
iLBX connectors, and
interface

iSBC020EX

iSBC040EX

ENVIRONMENTAL REQUIREMENTS
Operating
Temperature: O°C to 60°C airflow of 5 cubic feet per
minute
Storage
Temperature: - 40°C to + 75°C
Operating
Humidity:

iSBC 012EX board: 6.8 ounces
(1910 gm)

To 90% without condensation

4-12

with parity,
high speed
with parity,
high speed
with parity,
high speed

inter

iSBC® 012EX, 010EX, 020EX, 040EX BOARDS

280142-2

Figure 1. Typical iLBXTM System Configuration

512K,1024K,
2056K, 4096K
BYTES ARRAY

MULTIBUS'
INTERFACE

MULTIBUS'
DATA
TRANSCEIVERS

280142-3

Figure 2. iSBC® EX Memory Board Block Diagram

(

4-13

iSBC® 304 128K BYTE RAM MULTIMODULETM BOARD
iSBC® 300A 32K BYTE RAM MULTIMODULETM BOARD
304 Module Provides 128K Bytes
Memory Expansion for the
• On-Board
• iSBC®
iSBC
iSBC
and iSBC
of Dual Port RAM Expansion for the
86/30,
86/14
Single Board Computers

iSBC 86/30 or iSBC 86/35 Board

•
•

iSBC 300A Module Provides 32K Bytes
of Dual Port RAM Expansion for the
iSBC 86/14 Board
Simple, Reliable, Mechanical and
Electrical Interconnection

•

86/35

On-board Memory Expansion
Eliminates MULTIBUS® System Bus
Latency and Increases System
Throughput

• Low Power Requirements

The iSBC 304 and iSBC 300A RAM modules provide simple, low cost expansion of the memory compliment
available on the iSBC 86/30 and iSBC 86/14 Single Board Computers, respectively. Each module doubles the
on-board RAM memory capacity of the host board. Additionally, the iSBC 304 provides 128K bytes RAM
expansion to the iSBC 86/35 giving a total capacity of 640K bytes'RAM memory. The RAM MULTIMODULE
options for the host boards offer system designers a new level of flexibility in defining and implementing Intel
single board computer systems. Because th!3Y expand the memory configuration on-board, they can be accessed as quickly as the existing host board memory by eliminating the need for accessing the additional
memory via the MULTIBUS system bus.

\
210329-1

4-14

September 1987
Order Number: 210329-002

inter

iSBC® 304/iSBC® 300A

The module is then secured at three additional
points with nylon hardware to ensure the mechanical
security of the assembly.

FUNCTIONAL DESCRIPTION
Each MULTIMODULE contains dynamic RAM devices and sockets for the Intel 8203 dynamic RAM controller and memory interface latching. To install the
module, the latches and controller from the host
CPU board are removed and inserted into sockets
on the RAM MULTIMODULE. The module is then
mounted onto the host board. Pins extending from
the controller and latch sockets mate with device
sockets underneath (see Figure 1). Additional pins
mate to supply other signals to complete the electrical interface.

To complete the installation, one socketed PROM is
replaced on the host CPU board with the one supplied with the MULTIMODULE kit. This is the
MULTIBUS address decode PROM which allows the
host board logic to recognize its expanded on-board
memory compliment.

REPLACEMENT
MEMORY ADDRESS
DECODE PROM
(SUPPLIED WITH Isec'
MUL TIMODULE'- OPTION)

NYLON MOUNTING
HARDWARE (3 PLACES)
(SUPPLIED WITH isec'
MULTIMODUlE'· OPTION)

210329-2

Figure 1. Installation of the MULTIMODULETM RAM on the Host Single Board Computer

4-15

inter

iSBC® 304/iSBC® 300A

The iSBC 300A module mounted on the iSBC 86/14
board supports private allocation of 16K, 32K, 48K,
or 64K bytes of RAM memory.

SPECIFICATIONS
Word Size
8 or 16 bits (16-bit data paths)

Auxiliary Power

Memory Size

The . low power memory protection option included
on the CPU host boards supports the RAM modules.

iSBC 304 Module-128K bytes RAM

Physical Characteristics

iSBC 300A Module-32K bytes RAM

Width: 2.4 in. (6.10 cm)

Cycle Time

Height: 5.75 in. (14.61 cm)

iSBC 304-700 ns (read); 700 ns (write)

Depth': 0.72 in. (1.83 cm)

iSBC 300A-700 ns (read); 700 ns (write)

Weight: 0.13 oz. (59 g)

Memory Addressing

*NOTE:
Combined depth including host board.

CPU ACCESS

Electrical.Characteristics

iSBC 304 (with iSBC 86/35)-640K bytes (total capacity); 0-9FFFFH (address range)

DC POWER REQUIREMENTS
iSBC 304: 640 rnA at

iSBC 304 (with iSBC 86/30)-256K bytes (total capacity); 0-3FFFFH (address range)

+ 15V incremental power

iSBC 300A: 256 rnA at
iSBC 300A (with iSBC 86/14)-64K bytes (total capacity); O-OFFFFH (address range)

+ fN incremental power

Environmental Characteristics

MULTIBUS® Access

Operating Temperature: O·C to 55·C

Jumper selectable for any 32K (8K) byte boundary,
but not crossing. a 256K (128K) byte boundary on
the iSBC 86/30 (iSBC 86/14) host board. .

Relative Humidity: to 90% (without condensation)

Reference Manual
Interface

All necessary documentation for the iSBC 304 and
iSBC 300A MULTIMODULE boards is included in
the iSBC 86/14 and iSBC 86/30 Hardware Reference Manual, Order No. 144044-002 (NOT SUPPLIED).

The interfaces for the iSBC 304 and iSBC 300A
module options are designed only for the
iSBC 86/30 and iSBC 86/14 host boards, respectively.

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara, CA
95051.

Private Memory A"ocation
Segments of the combined hostlMULTIMODULE
RAM memory may be configured as a private resource, protected from MULTIBUS system access.
The amount of memory allocated as a private resource may be configured in increments of 25% of
the total on-board memory ranging from 0% to
100%. The iSBC 304 module mounted on the
iSBC 86/30 board, therefore, supports private allocation of 64K, 128K, 192K, or 256K bytes of RAM
memory.

ORDERING INFORMATION
Part Number Description

4-16

SBC 304

128K MULTIMODULE option for
iSBC 86/30 or iSBC 86/35 CPU
boards

SBC 300A

32K MULTIMODULE
iSBC 86/14 board .

option

for

iSBC® 301
4K-BYTE RAM
MULTIMODULETM BOARD

•

Watts Incremental Power
• 0.5
Dissipation

On-Board Memory Expansion to 8K
Bytes for iSBC® 88/40A Single Board
Computers

•

•
Uses 5 MHz (8185-2) RAMs
• Single
+ 5V Supply
•

Provides 4K Bytes of Static RAM
Directly On-Board

On-Board Memory Expansion
Eliminates MULTIBUS® System Bus
Latency and Increases System
Throughput

I!II Reliable Mechanical and Electrical

Interconnection

The Intel iSBC 301 4K-byte RAM MULTIMODULE Board provides simple, low cost expansion to double the
RAM capacity on the iSBC 88/40A Single Board Computer to 8K bytes. This offers system designers a new
level of flexibility in defining and implementing system memory requirements. Because memory is configured
on-board, it can be accessed as quickly as the existing iSBC 88/40A memory, eliminating the need for
accessing the additional memory via the MULTIBUS system bus. As a result, the iSBC 301 board provides a
high speed, cost effective solution for systems requiring incremental RAM expansion. Incremental power
required by the iSBC 301 module is minimal, dissipating only 0.5 watts.

280224-1

4-17

September 1988
Order Number: 280224-001

iSBC® 301

on the host board. Pins extending from the RAM
socket mate with the device's socket underneath
(see Figure 1). Additional pins mate to the power
supply and chip select lines to complete the electrical interface. The MULTIMODULE board is then secured at two additional points with nylon hardware to
insure mechanical security of the assembly. With the
iSBC 88/40A board mounted in the top slot of an
iSBC 604 or iSBC 614 cardcage, sufficient clearance
exists for mounting the iSBC 301 option. If the
iSBC 88/40A board is'inserted into some other slot,
the combination of boards will physically (but not
electrically) occupy two cardcage slots.

FUNCTIONAL DESCRIPTION
The iSBC 301 Board measures 3.95" by 1.20" and
mounts above the RAM area on the iSBC 88/40A
single board computer. It expands the on-board
RAM capacity from 4K bytes to 8K bytes. The iSBC
301 MULTIMODULE board contains four 1K byte
static RAM devices and a socket for one of the RAM
devices on the iSBC 88/40A board. To install the
iSBC 301 MULTIMODULE board, one of the RAMs
is removed from the host board and inserted into the
socket on the iSBC 301 board. The add-on board is
then mounted into the vacated RAM socket

!.,\

NYLON MOUTING
~-.~ HARDWARE
(2 PLACES)

""
- - -_ _

(SUPPLIED WITH
ISBC~301 OPTION)

280224-2

Figure 1. Installation of iSBC® 301 4K Byte RAM MULTIMODULETM Board

4-18

iSBC® 301

SPECIFICATIONS

Electrical Characteristics
DC Power Requirements:

Word Size

10 mA at + 5 Volts incremental power

8 bits

Environmental Characteristics
Operating Temperature: O°C to + 55°C
Relative Humidity:
to 90% (without condensation)

Memory Size
4096 bytes of RAM

Reference Manuals

Access Time
Read: 140
200
Write: 150
190

ns
ns
ns
ns

(from
(from
(from
(from

READ command)
ALE)
READ command)
ALE)

All necessary documentation for the iSBC 301
MULTIMODULE board is included in the CPU board
Hardware Reference Manual (NOT SUPPLIED)
iSBC 88/40A-Order No. 147049-001
Manuals may be ordered from any Intel sales representative, distributor office, or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

Memory Addressing
Memory addressing for the iSBC 301 4K-Byte-RAM
MULTIMODULE Board is controlled by the host
board via the address and chip select signal lines
and is contiguous with the host board RAM.

SPECIFICATIONS
Part Number Description
SBC 301
4K Byte RAM MULTIMODULE Board

iSBC 88/40A and iSBC 301 board: 00000-01 FFF

Physical Characteristics
Width: 1.20 in. (3.05 cm)
Length: 3.95 in. (10.03 cm)
Height: 0.44 in. (1.12 cm) iSBC 301 Board
0.56 in. (1.42 cm)
iSBC 301 Board + host board
Weight: 0.69 oz. (19 gm)

4-19

iSBC® 302
8K BYTE RAM MULTIMODULETM
•

Expands On-Board Memory of the iSBC
86/05A and iSBC 88125 Signal Board
Computers

•

On-Board Memory Expansion
Eliminates System Bus Latency and
Increases System Throughput

•

Uses Four Intel 2168 Static RAMs

•

Single

Reliable Mechanical and Electrical
Interconnection

+ 5V Supply

The Intel iSBC 302 8K byte MULTIMODULE RAM provides simple, low cost expansion to double the RAM
capacity on the iSBC 86/05A Single Board Computer to 16K bytes or increase RAM capacity on the iSSC 881
25 Single Soard Computer to 12K bytes. This offers system designers a new level of flexibility in implementing
system memory. Secause the MULTIMODULE memory is configured on-board, it can be accessed as quickly
as the standard on-board iSSG 86/05A or iSSC 88/25 memory, eliminating the need for accessing the
additional memory via the MULTISUS system bus. As a result, the iSSC 302 board provides a high-speed, cost
effective solution for systems requiring incremental RAM expansion.

280225-1

4-20

September 1988
Order Number: 280225-001

intJ

iSBC® 302

With the iSBC 88/25 board:

FUNCTIONAL DESCRIPTION

The 8K bytes of RAM on the iSBC 302 board occupy
the 8K byte address space immediately after that of
the iSBC 88/25 board's 4K RAM (Le., default configuration -

The iSBC 302 MULTIMODULE measures 2.60" by
2.30· and mounts above the RAM area on the iSBC
86/05A or iSBC 88/25 Single Board Computer. The
iSBC 302 MULTIMODULE board contains four 4K x
4 static RAM devices and sockets for two of the
RAM devices on the iSBC 80/05A board. With the
iSBC 302 MULTIMODULE mounted on the iSBC 881
25 board, the two sockets on the iSBC 302 MULTIMODULE may be filled with 4K x 4 static RAMs. The
two sockets on the iSBC 302 module have extended
pins which mate with two sockets on the base
board. Additional pins mate to the power supply and
chip select lines to complete the electrical interface.
The mechanical integrity of the assembly is assured
with nylon hardware securing the module in two
places. With the iSBC 86/05A or iSBC 88/25 board
mounted in the top slot of an iSBC 604/614 cardcage, sufficient clearance exists for the mounted
iSBC 302 option. If the iSBC 86/05A or iSBC 88/25
board is inserted into some other slot, the combination of the boards will physically (but not electrically)
occupy two card cage slots.

iSBC 88/25 board's RAM - O-OFFFH
iSBC 302 board's RAM -01000H-02FFFH).

Physical Characteristics
Width: 2.6 in. (6.60 cm)
Length: 2.3 in. (5.84 cm)
Height: 0.56 in. (1.42 cm) iSBC 302 board
86/05A or iSC 88/25 board

iSBC

Weight: 1.25 oz. (35 gm)

Electrical Characteristics
DC Power Requirements: 720 rnA at + 5V incre.
mental power

SPECIFICATIONS

Environmental Characteristics

Word Size
8/16 bits

Operating Temperature: O°C to + 55°C
to 90% (without condensaRelative Humidity:
tion)

Memory Size

Reference Manuals

16,384 bytes of RAM

Cycle Time

. All necessary documentation for the iSBC 302 MULTIMODULE board is inciuded in the CPU board
Hardware Reference Manuals (NOT SUPPLIED).
iSBC 86/05A -Order No. 147162-002

Provides "no wait state"memory operations on the
iSBC 86/05A board at 5 MHz or 8 MHz or the iSBC
88/25 at 5 MHz.
5 MHz cycle time 8 MHz cycle time -

iSBC 88/25

-Order No. 143825-002

Manuals may be ordered from any Intel sales representative, distributor office, or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

800 ns
500 ns

Memory Addressing
ORDERING INFORMATION

Memory addressing for theiSBC 302 MULTIMODULE board is controlled by the host board via the
address and chip select signal lines.

Part Number Description
SBC 302
8K byte RAM MULTIMODULE

With the iSBC 86/05A board:
The 8K bytes of RAM on the iSBC 302 board occupy
the 8K byte address space immediately after that of
the iSBC 86/05A board's 8K RAM (Le., default configuration iSBC 86/05A board's RAM - 00000-01 FFFH
iSBC 302 board's RAM - 02000-03FFFH).
4-21

iSBC® 314
512KBVTE RAM MULTIMODULETM BOARD

•
•
•

On-Board M~mory Expansion for the
iSBC 86/35 Single Board Computer

•

iSBC 314 Module Provides 512K Bytes
of Dual Port RAM Expansion for the
iSBC 86/35 Board

Completes iSBC 86/35 Memory Array
Providing a Full Megabyte Page of
System ,Memory

•

Increases System Throughput by
Reducing AccessestoMULTIBUS®
Global Memory

Reliable Mechanical and Electrical
Interconnection

•
•

Low Power Requirements
Battery Backup Capability

The iSBC 314 512K byte RAM MULTIMODULE board provides simple, low cost expansion to double the onboard RAM capacity of the' iSBC 86/35 Single Board Computer host to one megabyte. This RAM MULTIMODULE option offers system designers a simple, practical solution to expanding and improving the memory
capability and performance of the iSBC 86/35 board. The iSBC 314 memory is configured on-board and can
be accessed as quickly as the standard iSBC 86/35 memory, eliminating the need for accessing additional
memory via the MULTIBUS system bus.

280000-1

4-22

October 1986
Order Number: 280000-002

inter

ISBC® 314 BOARD

REPLACEMENT
MEMORY ADDRESS
DECODE PAL
(SUPPUED WITH ISBC~
MULTIMODULET"
OPTION)

NYLON MOUNTING
HARDWARE (3 PLACES)
(SUPPLIED WITH ISBC'
MULTIMODULE" OPTION)

280000-2

Figure 1. Installation of the MULTIMODULETM RAM Module on the Host Single Board Computer

FUNCTIONAL DESCRIPTION

SPECIFICATIONS

The iSBC 314 MULTIMODULE board measures
2.40" by 5.75" and mounts above the RAM array on
the iSBC 86/35 Single Board Computer. The iSBC
314 board contains sixteen 256 Kbit x 1 dynamic
RAM devices and three sockets; two for the memory
latches and one for the Intel 8203 dynamic RAM
controller. The addition of the iSBC 314 memory
MULTIMODULE board to the iSBC 86/35 board
makes possible a one megabyte single board solution; the full direct addressing capability of the iAPX
86 CPU.

Word Size
8 or 16 bits (16-bit data paths)

Memory Size
512K bytes RAM

System Cycle Time (8 MHz, 2 Wait
States)

To install the module, the latches and controller
from the host iSBC 86/35 board, are removed and
inserted into sockets on the iSBC 314 board. The
module is then mounted onto the host board. Pins
extending from the controller and latch sockets
mate with device sockets underneath (see Figure 1).
Additional pins mate to supply other signals to complete the electrical interface. The module is then secured at three additional points with nylon hardware
to ensure the mechanical security of the assembly.

750 ns (read); 750 ns (write)
NOTE:
1 wait state achieved with jumper change on iSBC
86/35 board.

Memory Addressing
iSBC 314 module with iSBC 86/35 board - 1M byte
(total capacity); O-FFFFFH. (See Figure 2, Memory
Allocation)

To complete the installation, one socketed PAL is
replaced on the iSBC 86/35 board with the one supplied with the MULTIMODULE kit. This is the PAL
which allows the host board logic to recognize its
expanded on-board memory compliment.

Interface
The interface for the iSBC 314 MULTIMODULE
board option is designed only for the iSBC 86/35
host board.
4-23

iSBC® 314 BOARD

Wait-State Performance

Auxiliary Power

A significant performance advantage of 2 wait-states
is achieved when accessing memory on-board the
iSBC 86/35 versus the performance of 6 wait-states
when accessing memory off-board over the MULTIBUS. The iSBC 314 puts an additional 512K bytes of
system memory on-board the iSBC 86/35 reducing
the execution time by as much as 70%.

The low power memory protection option included
on the iSBC 86/35 board supports the iSBC 314
module.

Physical Characteristics
Width: 2.4 in. (6.10 cm)
Length: 5.75 in. (14.61cm)
Depth·: 0.72 in. (1.83 cm)
Weight: 0.13 oz. (59g)

Memory Allocation
Segments of the combined hostiMULTIMODULE
RAM may be configured to be accessed either from
off-board or on-board resources. The amount of
memory allocated as either public or private resource may be configured in a variety of sizes .. The
address range boundaries for the 1 megabyte of
RAM array of the iSBC 314 and iSBC 86/35 board
combination are shown in Figure 2 for accesses
from both on-board and off-board resources.

NOTE:
·Combined depth including host board.

RAM
ACCESS
FROM
1M

ON-BOARD

FFFFFH

RAM
ACCESS
FROM
OFF·BOARD
FFFFFH)

960K

1----1 ~~~~~

896K t-----i~m~~

(lM·64K)

960K

FOOOOH
EFFFFH

(lM-128K)

896K

EOOOOH
DFFFFH

512K

80000H
7FFFFH

256K

40000H
3FFFFH

128K

20000H
1FFFFH

ENDING
ADDRESS

ISBC' 314 MODULE
512KBYTES

512K

t - - - - - i ~~~~~

ISIIC"' 88/35 BOARD
512KBYTES

64K

·BEGINNING
ADDRESS

1OOOOH
OFFFFH

o L.._ _....... OOOOOH

OOOOOH

NOTE:
.
280000-3
All memory above this boundary may be disabled under· software control to allow access to MULTIBUS® system bus.

Figure 2. Address Range Selection
4-24

intJ

iSBC® 314 BOARD

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara, CA
95051.

Electrical Characteristics
DC Power Requirements'
• Additional power required by the iSBC 314 MULTIMODULE is:
Typical: 60 mA @ + 5V
Maximum: 140 mA

ORDERING INFORMATION
Part Number Description
iSBC® 314
512K byte Memory MULTIMODULE
option for iSBC 86/35 board

+ 5V

Environmental Characteristics
Operating Temperature: O°C to + 55°C
Relative Humidity:
to 90% (without
condensation)

Reference Manual
All necessary documentation for the iSBC 314 MULTIMODULE board is included in the iSBC 86/35
Hardware Reference Manual (NOT SUPPLIED); Order Number: 146245-002.

4-25

inter

iSBC® 341

28·PIN MULTIMODULETM EPROM
•

•

On-board Memory Expansion for
iSBC® 86/05A, iSBC 88/25,
ISBC 186/03A, ISBC 286/10A,
ISBC 286/12 Series, and iSBC 88/40A
Microcomputers

•

Sockets for Up to 256K Bytes of
Expansion with Intel 27512 EPROMs

•

On-Board Expansion Provides "No Walt
State" Memory Access with Selected
Devices

Supports JEDEC 24/28-Pin Standard
Memory Devices, Including EPROMs,
Byte-Wide RAMs, and E2PROMs

•

Simple, Reliable Mechanical and
Electrical Interface

The iSBC 341 28-pin MULTIMODULE EPROM board provides Simple, low-cost expansion of the on-board
EPROM capacity of the iSBC 86/05A, the iSBC 88/25, iSBC 186/03A, iSBC 286/10A, iSBC 286/12 Series
Single Board Computers and the iSBC 88/40A Measurement and Control Computer. Four additional 28-pin
sockets support JEDEC 24/28-pin standard devices, including EPROMs, byte-wide static and psuedo-static
RAMs.
The MULTIMODULE expansion concept provides the optimum mechanism for incremental memory expansion. Mounting directly on the microcomputer, the benefits include low cost, no additional power requirements
beyond the memory devices, and higher performance than MULTIBUS-based memory expansion.

280214-1

4-26

. October 1988
Order Number: 280214-001

iSBC® 341 BOARD

FUNCTIONAL DESCRIPTION

POWER REQUIREMENTS

Devices(1)

The iSBC 341 28-pin MULTIMODULE EPROM option effectively doubles the number of sockets available for EPROM on the base microcomputer board
on which it is mounted. The iSBC 341 board contains six 28-pin sockets. Two of the sockets have
extended pins which mate with two of the sockets
on the base board. Two of the EPROMs which
would have been inserted in the base board are then
reinserted in the iSBC 341 sockets. Additional interface pins also connect chip select lines and power.
The mechanical integrity of the assembly is assured
with nylon hardware securing the unit in two places.

Max Current

± 5%

420mA
600mA
600mA

2716
2732A
2764

NOTE:
1. Incremental power drawn from host board for four additional devices.

Auxiliary Power
There are no provisions for auxiliary power (battery
backup) on the iSBC 341 option.

Through its unique interface, the iSBC 341 board
can support 8- or 16-bit data paths. The data path
width is determined by the base board-being 8 bits
for the iSBC 88/40A and iSBC 88/25 microcomputers,and 8/16 bits for the iSBC 86/05A,
iSBC 186/03A, iSBC 286/10A, and iSBC 286/12
Series Single Board Computers.

Physical Characteristics
Width: 3.4 in. (8.64 cm)
Length: 2.7 in. (6.86 cm)
Height: 0.78 in. (1.98 cm)'
Weight: 5 oz. (141.5 gm)
'Includes height of mounted memory devices and
base board.

SPECIFICATIONS

Word Size

All necessary mounting hardware (nylon screws,
spacers, nuts) is supplied with each kit.

8 or 8/16 bits (determined by data path width of
base board).

Environmental Characteristics
Operating Temperature: O'C to + 55'C
Relative Humidity:
to 90% (without condensation)

Memory Size
256K bytes with available technology (JEDEC standard defines device pin-out to 512-bit devices).

Reference Manuals

Device Size EPROM Max iSBC® 341 Capacity
(Bytes)
(Bytes)
Type
2Kx8
4Kx8
8Kx8
16K x 8
32Kx8
64Kx8

2716
2732A
2764
27128
27256
27512

All necessary documentation for the iSBC 341 module is included in the CPU board Hardware Reference Manuals (NOT SUPPLIED)

8K
16K
32K
64K
128K
256K

iSBC
iSBC
iSBC
iSBC
iSBC
iSBC

Access Time

186/03A - Order No. 148060-001
86/05A - Order No. 147162-002
88/25 - Order No. 143825-002
88/40A - Order No. 147049-001
286/10A - Order No. 147532-001
286/12 - Order No. 147533-001

Manuals may be ordered from any Intel sales representative, distributor office, or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

Varies according to base board and memory device
access time. Consult data sheet of base board for
details.

Memory Addressing

ORDERING INFORMATION

Consult data sheet of base board for addressing
data.

Part Number
SBC 341
4-27

Description
28-Pin MULTIMODULE EPROM

ISBC® 429 UNIVERSAl, SITE ltIEltIORl' EXPANSION BOARD

CIfIOS IfIlJl;I'IBlJS®IIfIEIfIORI' EXPANSION BOARD SlJPPORJ'S
£AJ'ESJ'IfIEIfIORI'J'ECHNO£OGI'
The iSBC 429 board providt'S a wide range of lllelllOl'Y e~pansion capabilities for \1l'1:rIBI'S tit'signs
lip to 4 \!Bytes of memory can Ill' installed using r:I'I<()~1. Vlasl1 nl!'mor~, S[':'\\I.I,:zpl<()\1 oJ' Slatic
\\R:\~I,

The C~IOS illlplflllt'lltation of till' iSBG 429 makes it idml IiiI' it)\\

Po\\I'I'

applit'ations,

All of Intel's Singlr Bmrd COlllplltfrs can cllnllllllllicat.t' \\ith till' iSIlC 42f1l1sing til" \1l'1:rllll'S
System hus, Alternatively, the iSBe 429 nlHY ht' optionall~ l'IInfiglll'l'd to liSt' till' iLB'\'" hilS "II' faster
access to the iSflC 186/03:\, 28(il10II, ~H()/I~ st'ries or :lBli/12 sl'ril's of SlIlgit' Board COIllIHltl'J'S,

FEAJ'lJRES:
• Supports EPROM, Pagl' ~lode EPROM,
r:2PI<()~1. Flash Memol'Y, SRIIM and Static
\\K\~I

• Thirt~-two standal'd 32-pill .IEDEC sites
(suPP0l'ts both 2B-pin and 32'pin dl'vil'l's) up
to 4\IByte capacity
• iloB:>; Bus or MlILTIBLIS Configurahility
• Lo\\ po\wr CMOS design
• Battery Backllp/\kllloI'Y Pl'otect suppmt
• .\ssignahle anywhere within a 16 Megahytl'
address space on 41\ hytl' Imllndal'il's

intel-_~_---,------inti I O"I",rol\'Hn il~Sllml'" n" ll"l.m~!hlhl~ I"rll~ IIN"~ ,In~ 'III'WU, .. tt~, lholn 1'lIl'llIll~ 11I1hl~!I<~11I1 ,Ill hlll'l 1'1'1111111 \11 ,,1111', '1t,'UI1 ]lOlh'n! II'n1.... ·~.I11

mll,It'·11. 11I1"r11I.11111n n,nl,!IIlI~llk'I'I'1Il SlIl_'rN11,os pn'\MISI, pllhll~t\l'd 1'>IH'lfll"lli,>ns 'jllll~'N' I~'\I""S hlllil Im"1 ,IIHII~ Stll'II'11 III rI~IIIl!" \1.1111'1111 I)UIII"
:-\o·l~'·'lll.·1 I!IHH
111'1," \lII1I1"'1 :!Htlhli.tI,\lOI

'<;, Inll'! 1;'111.,1,1111111 l!IHf!

4-28

FEt\TlJRES
IUlXB.s
The iSBC 429 board can be configured via jumpers to
communicate with either the MULTIBUS interface or the
iLBX Bus interface. Significant memory access time
improvements can be realized using the iLBX Bus interface
versus the MULTIBUS interface. due to its dedicated.
unarbitrated architecture. Additional information on the
iLBX Bus Is available in the iLBX Specificalion. order
number 145695·Rev. A.

MEMORY IICCESS
The iSBC 429 board has jumper-selectable access times for
e.ach bank which allows the board to be tailored to the
performance of the particular devices which are installed in
• the iSBC 429 buard. The iSBC 129 accepts devices with an
access time ranging from 150 ns with a minimum
granularity of 99 ns and results in a board access time from
182 ns to 1667 ns. Each bank can be configured for access
time.

CMOS DESIGN

INHIBITS

For embedded control applications which are sensitive to
power consumption. the iSBC 429 was designed with CMOS
components and it will support many CMOS memory
devices. Unpopulated. the iSBC 429 requires 5.25 watts at
5 volts.

Inhibit signals are provided on the iSSC 429 board to allow
ROM to overlay RAM for bootstrapping or diagnostic
operations. Each bank of the iSBC 429 board can be
overlayed with the system RAM by jumpers provided on the
board. (i.e. If banks are overlapped. inhibits can be used to
select the appropriate bank.)

""IISH MEMORY SIJPPORT
The iSBC 429 board suppurts Intel's new CMOS Flash
Memory devices. These new memory devices offer the most
cost-clTective and reliable alternalive for updatable nonvolatile memory. Memory contents can be erased and
reprogrammed on-board during subassembly test. in-system
during final test. and in·system after sale.

MEMORY BIlNIlS
The thirty·two sites on the iSBC 429 board are partitioned
into two banks of 16 Sites each. Both banks are
independently configurable to any of the device types
supported on the board. Each bank can support up to 2
Megabytes using 27010 devices.

MEMORY IIDDRESSING
The address space of each bank can be independently
configured for starting address and size. The starting
address can be on any 4 KByte boundary within the 16
MByte MULTIBUS address space. The size of each bank is a
multiple of 64 KBytes.

MODE OF OPERII'I'ION
The iSBC 429 board can operate in one of two modes: the 8
bit only mode or the 8/16 bit mode. The 8 bit mode provides
the most efficient memory configuration for systems
handling 8 bit data only. The 8/16 bit mode allows the iSBC
429 board to be compalible with systems employing 8 bit
and 16 bit masters. The mode of operation is selected by onboard jumpers and is available for both MlILTIBliS and
iLBX Bus configurations.

BIITTERY BIlCIlIJP
The iSBC 429 board supports battery backup operation via
a connector on the board. An auxiliary power bus is
provided to allow separate power to the memory array for
systems requiring battery backup. Selection of this auxiliary
power bus is made via jumpers on the board.
An active-low TTL compatible Memory Protect signal is
brought out on the auxiliary connector which. when
asserted. disables access to the memory array. This input is
provided for the protection of Memory contents during
system power-down sequences.

INTEL ()lJIIUTY-YOlJR GlJlIRIINTEE
The iSBe 429 is designed and manufactured in accordance
with Intel's high quality standards. We then verify quality
through rigorous testing in our state-of-the-art
P.nvironmental Test Laboratory.

WORLDWIDE SERJ'ICE AND SIJPPORT
The iSBC 429 is fully supported by Intel's worldwide
network of field application engineers. We're experts in
developing a variety of real·time and system applications
and want to make your design succeed.

4-29

SP.ECIFICATIONS
MEMORY DEnCES SVPPORTED BY THE ISBC 429
Slzt
TYflt

BllxB 1611xB 3211xB 6411xB UBllxB 25611xB 4 x 1611xB Bx 1611xB

EPROM

276-1

27128

27256

27512

27010

27020

ROM

.... 1

....

Page ~'ode
EPROM

....
-

E2pROM2

286-1.\

Flash

27F6-1

27F25Cl
28F256

Statlr
WR-\W

....

SR.\'.

....

~mory3

27~13

27011

denotes that the iSBC -129 board II ill ~lIpport thl' lIt'l ICl' indicated, but that it is not currently availaiJle from Inkl.
File \olt onll. Enhanced
12 \olt \ PI' onl)
.
Static \\R\\1 del ices exceed the height ~perirication fill' \ll LTIBUS. The iSBC 429 will occupy more than one slot with
these del ices installed.

1 ........
2
3
4

WORD SIZE

POWER REQIlIREMENTS

B or 8116 bits

V,.,. = 5 volts ± 5%
Vpp = 12 volts ± 5%
I,... = 1.2 amps. maximum. without any memory devices in
the boar'd.

MEMORY SIZE
Sockets are prOlidcd fur up to thirty·tll() 32·pin or 28·pin
delires II hich c~n prOl ide up to -I \iegall)!t's of EPR(J~1I
~O\I/SR\\llFlash \lemor).

ACCESS TIME
.\ccess time is jumperahle from 182 ns-to 1667 ns Ilith a
granularit) of 99 ns to optimize performance for the deviCes
which are installed and is equilalent for \ll ILTIBlIS and
iLB\ Bus.

PHYSICAL CHARACTERIS'I'ICS
Width· 12.00 inches (30.48 em)
Depth· 7.05 inches (17.91 em)
Heigllt . 5 inches (1.27 cm)

ENVIRONMENT
Operating Temperature· ODC to + 60 DC (Convection
cooling)
Relative Humidity· 90% non·condensing

ORDERING INFORMATION
PART NIfItlBER

DESCRlnlON

tlDDI'I'IONAL LlTERATIlRE

SBe -129

L'niversal Site Memor~ I-:xpansion
Board

980683·004 . Intel MULTIBUS Specification Manual
145695·001 . iLBX Bus Specification

REFERENCE MANIlAL
-157317·001· iSBC -129 Hardllare Reference Manual (NOT
SL'PPLlED)

.4-30

iSBC® 519/iSBC® 519A
PROGRAMMABLE 1/0 EXPANSION BOARD
•

iSBC® lID Expansion via Direct
MULTIBUS® Interface

•

iSBC® 519A Provides 16 Maskable
Interrupt Request Lines

•

72 Programmable lID Lines with
Sockets for Interchangeable Line
Drivers and Terminators

•

Jumper Selectable 0.5,1.0,2.0, or
4.0 ms Interval Timer

•

iSBC® 519A Provides Full 16-Bit I/O
Addressability

•

iSBC® 519A Provides 3 iSBX
Multimodule Connectors

The iSBC® 519 Provides Eight
Maskable Interrupt Request Lines with
Priority Encoded and Programmable
Interrupt Algorithms

The iSBC 519/iSBC 519A Programmable I/O Expansion Board is a member of Intel's complete line of iSBC
memory and I/O expansion boards. The iSBC 519/iSBC 519A interfaces directly to any iSBC single board
computer via the system bus to expand input and output port capacity. The iSBC 519/iSBC 519A provides 72
programmable I/O lines. The system software is used to configure the I/O lines to meet a wide variety of
peripheral requirements. The flexibility of the I/O interface is further enhanced by the capability of selecting the
appropriate combination of optional line drivers and terminators to provide the required sink current, polarity,
and drive/termination characteristics for each application. Address selection is accomplished by using wirewrap jumpers. The board operates with a single + 5V power supply.

280230-1

4-31

September 1988
Order Number: 280230-001

iSBC® 519/iSBC® 519A BOARD

iSBXTM MULTIMODULETM Expansion
Capabilities

FUNCTIONAL DESCRIPTION
The 72 programmable I/O lines on the iSSC 519/
iSBC 519A are implemented utilizing three Intel
8255A programmable peripheral interfaces. The system software is used to configure the I/O lines in
combinations· of undirectional input! output and bidirectional ports. In order to take full advantage of the
large number of possible I/O configurations, sockets
are provided for interchangeable I/O line drivers and
terminators. The 72 programmable I/O lines and signal ground lines are brought out to three 50-pin edge
connectors that mate with flat, round, or woven cable.

Three iSBX MULTIMODULE connectors are provided on the iSSC 519A board. Up to three single wide
MULTIMODULE or one double wide and one single
wide iSBX MULTIMODULEcan be added to the
iSBC 519A board. A wide variety of expansion options are available.

Physical Characteristics
Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm),
1.16 in. (2.95 cm) with iSBX modules
Weight: 14 oz. (397.3 gm)

Interval Timer
Typical I/O read access time is 350 nanoseconds.
Typical I/O read/write cycle time is 450 nanoseconds. The interval timer provided on theiSBC 519/
iSBC 519A may be used to generate real time clocking in systems requiring the periodic monitoring of
I/O functions. The time interval is derived from the
constant clock (SUS CCLK) and the timing interval is
jumper selectable. Intervals of 0.5, 1.0, 2.0, and 4.0
milliseconds may be selected when an iSBC single
board computer is used to generate the clock. Other
timing intervals may be generated if the user provides a separate constant clock reference in the
system.

Electrical Characteristics
Average DC Current
Without Termlnatlon(1) With Terminatlon(2)
ICC ~ 1.5A max

NOTES:
1. Does not include power required for operational I/O drivers and liD terminators.
2. With 18 22011/33011 input terminators installed, all terminator inputs low.

Environmental Characteristics

Eight-Level Vectored Interrupt

Operating Temperature: O°C to

Intel 8259A programmable interrupt controller(s)
(PIC) provides vectoring for interrupt levels. As
shown in Table 1, a selection of three priority processing algorithms is available to the system designer so that the manner in which requests are serviced
may be configured to match system requirements.
Priority assignments may be reconfigured dynamically via software at any time during system operation.
Table 1. Interrupt Priority Options
Algorithm

Interrupt request line priorities
fixed.

Auto-rotating

Equal priority. Each level, after
receiving service, becomes the
lowest priority level until next
interrupt occurs.

Specific priority

+ 55°C

Reference Manual
9800385B-iSBC 519/iSSC 519A Hardware Reference manual (NOT SUPPLIED)
Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

Operation

Fully nested

3.5A max

ORDERING INFORMATION
Part Number Description
SBC 519
Programmable I/O Expansion Soard
SBC519A
Programmable I/O Expansion Soard

System software assigns lowest
priority level. Priority of all other
levels are based in sequence
numerically on this assignment.

4-32

MULTIBUS® I
Peripheral Controllers

I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I

iSBC® 208
FLEXIBLE DISKETTE CONTROLLER
Compatible with All iSBC® 80, iSBC 86,
• and
iSBC 88 Single Board Computers
Controls Most Single and Double
• Density Diskette Drives
iSBXTM Bus for Additional
• On-Board
Functions
User-Programmable Drive Parameters
• allow
Wide Choice of Drives

Phase Lock Loop Data Separator
• Assures
Maximum Data Integrity
Read and Write on Single or Multiple
• Sectors
Single + 5V Supply
• Capable
of Addressing 16M Bytes of
• System Memory

The Intel iSBC 208 Flexible Disk Controller is a diskette controller capable of supporting virtually any soft-sectored, double density or single density diskette drive. The standard controller can control up to four drives with
up to eight surfaces. In addition to the standard IBM 3740 formats and IBM System 34 formats, the controller
supports sector lengths of up to 8192 bytes. The iSBC 208 board's wide range of drive compatiblity is
achieved without compromising performance. The operating characteristics are specified under user program
control. The controller can read, write, verify, and search either single or multiple sectors. Additional capability
such as parallel or serial I/O or special math functions can be placed on the iSBC 208 board by utilizing the
iSBX bus connection.

280228-1

5-1

September 1986
Order Number: 260226-001

iSBC® 208

Universal Drives and the iSBC® 208
Controller

FUNCTIONAL DESCRIPTION
Intel's 8272 Floppy Disk Controller (FDG) circuit is
the heart.of the iSBC 208 Controilier. On-board data
separation logic performs standard MFM (double
density) and FM (single density) encoding and decoding, eliminating the need for external separation
circuitry at the drive. Data transfers between the
controller and memory are managed by a DMA device which completely controls transfers over the
MULTIBUS® system bus. A block diagram of the
iSBC 208 Controller is .shown in Figure 1.

Because the iSBC 208 Controller has universal drive
compatibility, it can be used to control virtually any
standard- or mini-sized diskette drive. Moreover, the
iSBC 208 Controller fully supports the iSBX bus and
can be used with any iSBX module compatible with
this bus. Because the iSBC 208 Controller is programmable, its performance is not compromised by
its universal drive compatibility. The track-to-track
access, head-load, and head-unload characteristics
of the selected drive model are program specified.
Data may be organized in sectors up to 8192 bytes
in length.

co·,

MINI·DAIVES

STANDARD DRIVES

W~")

)

CONNECTOR

J2
CONNECTOR

Jr J

u
I---t
l+-

isax
CONNECTOR

1-----0
I--

8237

DMAC

Til 11

DATA BUS(8)

'-L----,

,
8218
BUS

...

Pll

SEGMENT
REGISTER

ADDER

c~'L

(16)

ADDRESS
BUFFER

C24,

10
DECODE

CONTROLLER

AUX
PORT

TIMING

T fr
I

C16,

f----o
l+-

8272
FOC

DATA
BUFFER

ADDRESS
BUS

co,

DATA
BUS

MUlTIBUS SYSTEM BUS P1

280228-2

Figure 1. iSBC® 208 Flexible Disk Controller Block Diagram

5-2

inter

iSBC® 208

Interface Characteristics

SPECIFICATIONS

The standard iSBC 208 Controller includes an Intel
8272 Floppy Disk Controller chip which supports up
to four drives, single or double sided.

CPU

Compatibility
- Any iSBC MULTIBUS computer or system main frame
Devices- Double or single density standard (8")
and mini (5%") flexible disk drives. The
drives may be single or double sided .
Drives known to be compatible are:

SIMPLIFIED INTERFACE-The cables between the
iSBC 208 Controller and the drive(s) may be low
cost, flat ribbon cable with mass termination connec. tors. The mechanical interface to the board is a
right-angle header with locking tabs for security of
connection.

Standard (8" )
Caldisk
Remex
Memorex
MFE
Siemens
Shugart
Pertec
CDC

PROGRAMMING-The powerful 8272 FDC circuit is
capable of executing high-level commands that simplify system software development. The device can
read and write both single and multiple sectors. CRC
characters are generated and checked automatically. Recording density is selected at each Read and
Write to support the industry standard technique of
recording basic media information on Track 0 of
Side 0 in single density, and then switching to double density (if, necessary) for operations on other
tracks.

Mini (5%")

143M
RFD4000
550
700
FDD200-8
SA 850/800
FD 650
9406-3

Shugart
Micropolis
Pertec
Siemens
Tandon
CDC
MPI

450 SA 400
1015-IV
250
200-5
TM-100
9409
51/52/91/92

Diskette- Unformatted IBM Diskette 1 (or equivalent single-sided media); unformatted
IBM Diskette 20 (or equivalent doublesided)

Program Initiation-All diskette operations are initiated by standard input/output (1/0) port operations
through an iSBC single board computer.

Equipment Supplied

System software first initializes the controller with
the operating characteristics of the selected drive.
The diskette is then formatted under program control. For subsequent transfers, the starting memory
address and transfer mode are specified for the
DMA controller. Data transfers occur in response to
commands output by the CPU.

iSBC 208 Controller
Reference Schematic
Controller-to-drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described in the iSBC 208 Hardware Reference Manual

Data Transfer-Once a diskette transfer operation
has been initiated, the controller acts as a bus master and transfers data over the MULTIBUS at high
speed. No CPU intervention is required until the
transfer is complete as indicated either by the gener. ation of an interrupt on the bus or by examination of
a "done" bit by the CPU.

Physical Characteristics
Width: 6.75 inches (17.15 cm)
Height: 0.5 inches (1.27 cm)
Length: 12.0 inches (30.48 cm)
Shipping Weight: 1.75 pounds (0.80 Kg)
Mounting: Occupies one slot of iSBC system chassis or iSBC 604/614 Cardcage/Backplane. With an iSBX MULTIMODULE
board mounted, vertical height increases
to 1.13 inches (2.87 cm).

iSBX BUS SUPPORT-One connector is available
on the iSBC 208 board which supports the iSBX system bus. This connector supports single-byte transfer as well as higher-speed transfers supervised by
the DMA controller. Transfers may take place in
polled or interrupt modes, user-selected. The presence of the iSBX bus allows many different functions
to be added to the board. Serial 1/0, parallel 110 and
various special-purpose math functions are only a
few of the capabilities available on iSBX MULTIMODULE boards.

Electrical Characteristics
Power Requirements:

5-3

+ 5 VDC

3.0A

inter

iSBC® 208

Data Organization and Capacity
Standard Size Drives
Double Density

Single Density

IBM System 34

Non-IBM

IBM System 3740

Non-IBM

Bytes per Sector

256 1 512 1 1024

20481409.618192

10241204814096

Sectors per Track

128 1 256 1 512
·26 1 15 1 8
77

Tracks per Diskette
Bytes per Diskette
(Formatted, per
diskette surface)

1 15
77

512,512
(256 bytes/sector)
591,360
(512 bytes/sector)
630,784
(1024 bytes/sector)

Drive Characteristics
Transfer Rate (K bytes/s)

1 21
256

630,784

256,256
(128 byte/sector)
295,680
(256 bytes/sector)
315,392
(512 bytes/sector)

1 2 1 1
256

315,392

Standard Size

Mini Size

Double/Single Density

62.5/31.25

31.25/15.63

Disk Speed (RPM)

360

300

Step Rate Time
(Programmable)

1 to 16 ms/track in
1 ms increments

2 to 32 ms/track in
2 ms increments

Head Load Time
(Programmable)

2 to 254 ms in
2 ms increments

4 to 508 ms in
4 ms increments

Head Unload Time
(Programmable)

16 to 240 ms in
16 ms increments

32 to 480 ms in
32 ms increments

Environmental Characteristics

Reference Manual

Temperature: O°C to 55°C (operating); -55°C to
,+ 85°C (non-operating)

143078-001- iSBC 208 Flexible Disk Controller
Hardware Reference Manual (NOT
SUPPLIED).

Humidity:

Up to 90% Relative Humidity without
condensation (operating); all conditions without condensation or frost
(non-operating)

Reference manuals may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa,
Clara, CA 95051.

ORDERING I.NFORMATION
Part Number Description
SBC 208

5-4

Flexible Disk Controller

intJ
•
•
•
•

iSBC® 214
PERIPHERAL CONTROLLER SUBSYSTEM

•
•
•
•

Based on the 80186 Microprocessor
Controls up to Two ST506/412 5%"
Winchester Disk Drives
Controls up to Four Single/Double
Sided and Single/Double Density 5%"
Flexible Disk Drives
Controls up to Four QIC-02 Streaming
Tape Drives

Supports 20 or 24-Bit Addressing
On-Board Diagnostics and Winchester
ECC
Incorporates Track Caching to Reduce
Winchester Disk Access Times
IRMXTM and XENIX· Operating System
Support

The iSBC 214 Subsystem is a single-board. multiple device controller that interfaces standard MULTIBUS®
systems of three types of magnetic storage media. The iSBC 214 Peripheral Controller Subsystem supports
the following interface standards: ST506/412 (Winchester Disk). SA 450/460 (Flexible Disk). and QIC-02 (%"
Streaming Tape).
The board combines the functionality of the iSBC 215 Generic Winchester Controller and the iSBC 213 Data
Separator. the iSBXTM 218A Flexible Disk Controller, and the iSBX 217C %" Tape Drive Interface Module.
The iSBC 214 Subsystem emulates the iSBC 215G command set, allowing users to avoid rewriting their
software.
The iSBC 214 Peripheral Controller Subsystem offers a single slot solution to the interface of multiple storage
devices. thereby reducing overall power requirements, increasing system reliability, and freeing up backplane
slots for addtional functionality. In addition, the new iSBC 214 Subsystem can be placed in a 16 Megabyte
memory space.

280089-1

·XENIX is a trademark of MICROSOFT Corp.

5-5

September 1986
Order Number: 280089-001

inter

iSBC®214

ware decode the' command request, allocate RAM
buffer space, and dispatch the tasks.

The iSBC 214 represents a new Peripheral Controller Subsystem architecture which is designed
around a dual bus structure .and supported by realtime, multitasking firmware. The 80186 controls the
local bus and manages the interj'ace between the
MULTIBUS and the controller. It is responsible for
high speed data transfers of up to 1.6 megabytes
per second between the iSBC 214 Subsystem and
host memory. The 80186 and the multitasking firm-

A second bus, the liD Transfer Bus, supports data
transfers between the controller and the various peripheral devices. It is this dual bus system that allows the iSBC 214 Subsystem to provide simultaneous data transfers between the controller and the
storage devices, and between.the controller and the
MULTIBUS. (See Figure 1).

80188
1/0 PROCESSOR

DMA
CONTROLLER

LOCAL
BUS
INTERFACE

MULTIBUS·
INTERFACE

.....

WINCHESYER
DISK
INTERFACE

1/0 TRANSFER
BUS
INTERFACE.

FLEXIBLE
DISK
INTERFACE

ROM

RAM

QIC.Q2
TAPE
INTERFACE

lSac" 214 PERIPHERAL CONTROLLER SUBSVSTEM

280089-2

Figure 1. Block Diagram ISBC® 214 Peripheral Controller Subsystem

MULTIBUS"

Isac" 214 PERIPHERAL CONTROLLER SUBSYSTEM

1/0 INTERFACE
ST506I412
WINCHESTER

110 INTERFACE

110 INTERFACE
SA450 FLOPPV

QIC·02TAPE

.""l

O'~
O~

QDJ
v.' TAPE DRIVE

280089-3

Figure 2. Fully Configured Peripheral Subsystem

. 5-6

inter

iSBC® 214

The iSBC 214 Subsystem implements an intelligent
track caching scheme through dynamic allocation of
buffer space. This provides reduced access times to
the Winchester disk and improved system performance. Operating systems with file management designed to handle sequential data can be supplied
directly from the cache without incremental access
to the disk.

Tape Controller Interface
The tape controller section of the iSBC 214 Subsystem is based on the 8742 Universal Peripheral Interface (UPI). It is capable of supporting up to four
QIC-02 compatible streaming tape drives over a
standard 50-pin daisy-chained cable.

FUNCTIONAL DESCRIPTION

All standard QIC-02 commands are supported. All
drives must be capable of streaming at 30 or 90
inches per second.

Winchester Disk Interface

MULTIBUS® Host Interface

The iSBC 214 Subsystem provides control of one or
two ST506/412 compatible Winchester devices and
supports up to 16 Read/Write heads per drive. The
Intel 82062 acts as the main controller taking care of
FM/MFM encoding and decoding, bit stream serialization and deserialization, address mark detection
and generation, sector identification comparisons,
CRC error checking and format generation. The
board uses a standard daisy-chained control cable
and a separate data transfer cable for each device
supported.

The MULTIBUS connection consists of two standard
printed circuit board edges that plug into MULTIBUS
edge connectors on a backplane in the system bus.
An active P1 connector is required and serves as the
Host systems's communciation channel to the controller. An active P2 connector is optional and only
required for supporting full 24-bit addressing and
power fail signals.

ECC

Compatibility

High data integrity is provided by on-board Error
Checking Code logic. For burst error correction, a
32-bit code is appended to the sector data fields by
the controller. During a read operation, the same
logic regenerates the ECC polynomial and compares this second code to the appended ECC. The
ECC logic can detect an erroneous data burst up to
32 bits in length with correction up to 11 bits.

CPU-any iSBC MULTIBUS computer or system
mainframe.

If an ECC error is detected the controller automatically initiates a retry operation on the data transfer. If
the maximum retry count is exceeded, the location
of the bad data within the transfer buffer is identified
and the 80186 then performs error correction on the
data bytes.

Tape drive-Any QIC-02 compatible, .25" streaming
tape drive.

SPECIFICATIONS

Winchester disk-Any
5.25" disk drive.

ST506/412

compatible,

Flexible disk-Any SA450/460 compatible, 5.25"
disk drive.

Controller-to-drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described in the iSBC 214 Hardware Reference Manual.

Flexible Disk Interface
The Flexible Disk Controller performs all data separation, FM (single density) and MFM (double density)
encoding, and CRC support. The 34-pin connector is
designed to support the SA450/460 interface directly and up to four flexible disk devices may be connected to the controller. -

Physical Characteristics
Width: 6.75 in. (17.15 cm)
Height: 0.5 in. (1.27 cm)
Length: 12.0 in. (30.48 cm)
Shipping Weight: 19 oz. (540 g)

5-7

intJ

iSBC® 214

Humidity:

Ordering Information
iSBC 214 Peripheral Controller Subsystem.
Mounting: Occupies one slot or SBC system chassis or cardcage/backplane.

Up to 90% relative humidity without
condensation (operating); all conditions without condensation or frost
(non-operating).

Reference Manual
134910-001: iSBC 214 Peripheral Controller Subsystem Hardware Reference Manual
(not supplied). Reference Manual
may be ordered from any Intel sales
representative, distributor office or
from I~tel Literature Department,
3065 Bowers Avenue, Santa Clara,
CA9S0S1.

Electrical Characteristics
. Power Requirements:

+ 5 VDC @

4.SA max.

Environmental Characteristics,
Temperature: 10°C to 55°C with airflow of 200 linear
feet per minute (operating); - 55°C to
+ 85°C (non-operating).

5-8

iSBC® 215
GENERIC WINCHESTER CONTROLLER
up to Four 5%" ,8" or 14"
• Controls
Winchester Disk Drives from Over Ten

Diagnostics and ECC
• On-Board
Full Sector Buffering On-Board
• Capable of Directly Addressing 16 MB
• of System Memory
Removable Back-up Storage Available
• Through
the iSBXTM 218A Flexible Disk

Different Vendors
with Industry Standard
• Compatible
MULTIBUS® (IEEE 796) Interface
ANSI
Standard
• Supports
Interface
Software Drivers Available for
• iRMXTM
86, iRMX 88 and Xenix*
X3T9/1226

Controller and the iSBX 217C
Interface Module

%" Tape

Operating Systems
8089 I/O Processor Provides
• Intel
Intelligent DMA Capability
Using VLSI technology, the iSBC 215 Generic Winchester Controller (GWC) combines three popular Winchester controllers onto one MULTIBUS board: the iSBC 215A open loop controller, the iSBC 215B closed loop
controller, and an ANSI X3T9/1226 standard interface controller. The combined functionality of the iSBC 215
Generic Controller supports up to four 5114" ,8" or 14" Winchester drives from over 10 different drive vendors.
Integrated back-up is available via two iSBX MULTIMODULE boards; the iSBX 218A module for floppy disk
drives and the iSBX 217C module for 114" tape units.
From the MULTIBUS side, the iSBC 215 GWC appears as one standard software interface, regardless of the
drive type used. In short, the iSBC 215 GWC allows its user to change drive types without rewriting software.
The iSBC 215 Generic Controller is totally downward compatible with its predecessors, the iSBC 215A and
215B controller; allowing existing iSBC 215A and 215B users to move quickly to the more powerful iSBC 215
Generic Winchester Controller. In addition, the iSBC 215 GWC directly addresses up to 16 megabytes of
system memory.

210618-1

Xenix is a trademark of Microsoft Corp.

5-9

October 1986
Order Number: 210618-002

inter

iSBC® 215

ECC polynomial to the appended ECC. The ECC
logic can detect an erroneous data burst up to 32
bits in length and using an 8089 algorithm can correct an erroneous burst up to 11 bits in length.

FUNCTIONAL DESCRIPTION
Disk Interface
The iSBC 215 Generic Winchester Controller can interface to over 10 different disk drives. To change
drive types the user need only reconfigure a minimal
number of board jumpers and, if required, insert the
proper formatting information into the command parameter· blocks.

iSBXTM Interface
Two iSBX bus connectors provide 1/0 expansion capability for the iSBC 215 GWC. With the optional addition of the iSBX 218A Flexible Disk Controller
MULTIMODULETM and or the iSBC 217C %" Tape
Interface Module, the iSBC 215 GWC can be configured into one of four types of peripheral subsystems, see Table 1.

The ANSI X3T9/1226 standard interface is a simple
one-for-one flat cable connection from drive to controller.

Table 1. Peripheral Subsystem Configurations
iSBC® iSBXTM iSBXTM
215
2f8A
217C

Full On-Board Buffer
The iSBC 215 Generic controller contains enough
on-board RAM for buffering one full data sector. The
controller is designed to make use of this buffer in all
transfers. The on-board sector buffer prevents data
overrun errors and allows the iSBC 215 Generic
Winchester Controller to occupy any priority slot on
the MULTIBUS.

Winchester Only

+ Floppy
+ %" Tape
Winchester + Floppy
+ %" Tape

Winchester

ECC

Expanded 1/0 Capability

High data integrity is provided by on-board Error
Checking Code (ECG) logic. When writing sector 10
or data fields, a 32-bit ECC, for burst error correction, is appended to the field by the controller. During a read operation, the same logic regenerates the

The iSBC 215 GWC controller allows the execution
of user-written 8089 programs located in on-board
or MULTIBUS system RAM. Thus the full capability
of the 8089 1/0 processor can be utilized for custom
1/0 requirements.

1-------------------------'
I
I

I
I

....

I
I
I

lOP

lOP
J1
LOCAL
BUS

MULTIBUS·
INTERFACE

MULTIBUS·
BUS

INTERFACE

SYSTEM
MEMORY
110 COMMUNICA·
TlONS BLOCKS

I
I

ROM

RAM

L________1~~2~ ~E~E~~~~~T~ ~~R~L~~

________

210618-2

Figure 1. Block Diagram of iSBC® 215 Generic Winchester Disk Controller
5-10

intJ

iSBC® 215

Interface with ShugartiQuantum/RMS Drives

210618-3

NOTE:
1. Shugart SA1000 or RMS Data Express.'

'Data Express is a trademark of Rotating Memory Systems.

Interface with Memorex/Shugart Drives

210618-4

DRIVEl

[--_.

210618-5

Interface with PRIAM Drives
'-_-:,>--C
"CI
AI
::l

:z:J
C

a.m
n

iii'

»-I
0Z
OJ

::l

c::
Z
0

»0

enOJ

SUNES

280238-2

ISBC® 534 COMMUNICATION BOARD

Interrupt Request Generation-As shown in Table
3, interrupt requests may originate from 16 sources.
Two jumper selectable interrupt requests (8 total)
can be automatically generated by each USART
when a character' is ready to be transferred to the
MULTIBUS system bus (Le., receive buffer is full) or
a character has been transmitted (transmit buffer is
empty). Jumper selectable requests can be generated by two of the programmable timers (PITs), and six
lines are routed directly from peripherals to accept
carrier detect (4 lines), ring indicator, and the Bell
801 present next digit request lines.

Asynchronous- 5-8 bit characters; break character
generation; 1, 1%, or 2 stop bits;
false start bit detection.

Sample Baud Rates(1)
Frequency(2)
Baud Rate (Hz)
(kHz, Software
Selectable)
Synchronous Asynchronous

153.6
76.8
38.4
19.2
9.6
4.8
6.98

Systems Compatibility
The iSBC 534 provides 16 RS232C buffered parallel
1/0 lines implemented utilizing an Intel 8255A programmable peripheral interface (PPI) configured to
operate in mode 0.· These lines are configured to
be directly compatible with the Bell 801 automatic
calling unit (ACU). This capability allows the
iSBC 534 to interface to Bell 801 type ACUs and up
to four modems or other serial communications devices. For systems not requiring interface to an ACU,
the parallel 1/0 lines may also be used as general
purpose RS232C compatible control lines in system
implementation.

38400
19200
9600
4800
6980

PORT 0 Rx,RDY
PORTOTx RDY
PORT 1 RxRDY
PORT 1 Tx RDY
PORT 2 RxRDY
PORT2TxRDY
PORT 3 RxRDY
PORT3TxRDY

Input Frequency (On-Board Crystal Oscillator)1.2288 MHz ± 0.1% (0.813,...s period, nominal)

Function

0
1
2
3
4
5
6
7

2400
1200
600
300
150
75
110

Interval Timer and Baud Rate
Generator Frequencies

Table 3. Interrupt Assignments
PICD

+ 64

9600
4800
2400
1200
600
300

NOTES:
1. Baud rates 'shown here are only a sample subset of possible software programmable rates available. Any frequency from 18.75 Hz to 614.4 kHz may be generated utilizing
on-board crystal oscillator arid 18-bit programmable interval timer (used here as frequency divider).
2. Frequency selected by 110 writes of appropriate 16-bit
frequency factor to Baud Rate Register.

"NOTE:
Complete operational details on the Intel 8251A
USART, the Intel 8253 Programmable Interval Tim- .
er, the Intel 8255A Programmable Peripheral Interface, and the Intel 8259A Programmable Interrupt
Controller are contained in the Intel Component
Data Catalog.

Interrupt
Request
Line

+ 16

Single Timer

PIC 1 '
PIT 1 counter 1
PIT 2 counter 2
Ring Indicator (all ports)
Present next digit
Carrier detect port 0
Carrier detect port 1
Carrier detect port 2
Carrier detect port 3

Real-Time
Interrupt
Interval

Dual/Timer
Counter
(Two Timers
Cascaded)

Min

Max

Min

Max

1.63,..s

53.3ms

3.26,..s

58.25
minutes

Rate
Generator
18.75 Hz 614.4 kHz 0.0029 Hz 307.2 kHz
(Frequency)

SPECIFICATIONS
Serial Communications Characteristics
Synchronous- 5-8 bit characters; internal or external character synchronization; automatic sync insertion.
6-22

inter

ISBC® 534 COMMUNICATION BOARD

Interfaces-RS232C Interfaces

Physical Characteristics

EIA Standard RS232C Signals provided and supported:
Carrier detect
Receive data
Clear to send
Ring indicator
Data set ready
Secondary receive data
Data terminal ready Secondary transmit data
Transmit clock
Request to send
Receive clock
Transmit data

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth:

Electrical Characteristics
Average DC Current

Parallel 110-8 input lines, 8 output lines, all signals
RS232C compatible

Voltage

Bus-All signals MULTIBUS system bus compatible

Vee = +5V
VDD = +12V
VAA = -12V

1/0 Addressing

Reference Manual
502140-002-iSBC 534 Hardware Reference Manual (NOT SUPPLIED) ,
Reference manuals are shipped with each product
only if designated SUPPLIED (see above). Manuals
may be ordered from any Intel sales representative,
distributor office or from Intel Literature Department,
3065 Bowers Avenue, Santa Clara, California 95051.

Compatible Connectors
Bus

Pins Centers
(qty.) (in.)
86

Serial and
26
parallel 110

1.9A, max
420 mA, max
400 mA, max

Operating Temperature: O°C to + 55°C

USART registers
Parallel I/O registers
Interval timer registers
Interrupt controller registers

Interface

1.9A, max
275 mA, max
250 mA, max

Environmental Characteristics

1/0 Access Time
ns
ns
ns
ns

Without
With
Opto-Isolators Opto-lsolators(l)

NOTE:
1. With four 4N33 and four 4N37 opto-isolator packages
installed in sockets provided to implement four 20 mA current loop interfaces.

The USART, interval timer, interrupt controller, and
parallel interface registers of the iSBC 534 are configured as a block of 16 I/O address locations. The
location of this block is jumper selectable to begin at
any 16-byte I/O address boundary (i.e., OOH, 10H,
20H, etc.).

400
400
400
400

0.50 in. (1.27 cm)

Weight: 14 oz. (398 gm)

Mating Connectors

0.156

Viking 2KH43/9 AMK12

0.1

3m 3462-0001 or
II H312113

ORDERING INFORMATION
Part Number Description

Compatible Opto-Isolators
Function
Driver

Supplier
Fairchild
General Electric
Monsanto

Part Number

Receiver

Fairchild
General Electric
Monsanto

4N37

SBC 534

4N33

6-23

Four Channel Communication Expansion Board

iSBC® 544
INTELLIGENT COMMUNICATIONS CONTROLLER
III iSBC® Communications Controller

III Ten Programmable Parallel I/O Lines

Acting as a Single Board
Communications Computer or an
Intelligent Slave for Communications
Expansion

Compatible with Bell 801 Automatic
Calling Unit
III Twelve Levels of Programmable

Interrupt Control

III On-Board Dedicated 8085A

III Individual Software Programmable

Microprocessor Providing
Communications Control and Buffer
Management for Four Programmable
Synchronous/Asynchronous Channels

Baud Rate Generation for Each Serial
I/O Channel
III Three Independent Programmable

Interval Timer/Counters

III Sockets for Up To 8K Bytes of EPROM

III Interface Control for Auto Answer and

III 16K Bytes of Dual Port Dynamic Read/

Auto Originate Modem

Write Memory with On-Board Refresh
III Extended MULTIBUS® Addressing

Permits iSBC 544 Board Partitioning
into 16K-Byte Segments in a
1-Megabyte Address Space
The iSBC 544 Intelligent Communications Controller is a member of Intel's family of single-board computers,
memory, I/O, and peripheral controller boards. The iSBC 544 board is a complete communications controller
on a single 6.75 x 12.00 inch printed circuit card. The on-board 8085A CPU may perform local communications
processing by directly interfacing with on-board read/write memory, nonvolatile read only memory, four synchronous/asynchronous serial I/O ports, RS232IRS366 compatible parallel I/O, programmable timers, and
programmable interrupts.

280239-1

6-24

November 1986
Order Number: 280239-001

iSBC® 544 COMMUNICATIONS CONTROLLER

8085A CPU to coordinate up to four serial channels.
Using the iSBC 544 as an intelligent slave, multichannel serial transfers can be managed entirely onboard, freeing the bus master to perform other system functions.

FUNCTIONAL DESCRIPTION
Intelligent Communications Controller
Two Mode Operation - The iSBC 544 board is
capable of operating in one of two modes: 1) as a
single board communications computer with all com- '
puter and communications interface hardware on a
single board; 2) as an "intelligent bus slave" that
can perform communications related tasks as a peripheral processor to one or more bus masters. The
iSBC 544 may be configured to operate as a standalone single board communications computer with
all MPU, memory and I/O elements on a single
board. In this mode of operation, the iSBC 544 may
also interface with expansion memory and I/O
boards (but no additional bus masters). The iSBC
544 performs as an intelligent slave to the bus master by performing all communications related tasks.
Complete synchronous and asynchronous I/O and
data management are controlled by the on-board

1 - SEiiiALUoI

Architecture - The iSBC 544 board is functionally
partitioned into three major sections: I/O, central
computer, and shared dual port RAM memory (Figure 1). The I/O hardware is centered around the four
Intel 8251A USART devices providing fully programmable serial interfacing. Included here as well is a
10-bit parallel interface compatible with the Bell 801
automatic calling unit, or equivalent. The I/O is under full control of the on-board CPU and is protected
from access by system bus masters. The second
major segment of the intelligent communications
controller is a central computer, with an 8085A CPU
providing powerful processing capability. The 8085A
together with on-board EPROM/ROM, static RAM, .
programmable timers/counters, and programmable

SERiAL iiO - -

SEAlAlVO

SeRiAL.

uo - - - -

PARAUelii'"O -

I
I

I
I
I
I

I
I
I
r--

PROGRAMMABLE I/O

"'T - - - - - - - - 1
a INTERRUPTS:
RECEIVER READY

RINQ INDICATOR

TRANSMITTER READY

CARRIER DETECT

a INTERRUPTS:

I
I

1IK.I

DY~.::'C

I
I
I
I
I
I

MULTIBUS

280239-2

Figure 1. iSBC® 544 Intelligent Communications Controller Block Diagram
6-25

I
I

iSBC® 544 COMMUNICATIONS CONTROLLER

Bell Model 801, or equivalent, and can also be used
for auxiliary functions. All signals are RS232C compatible, and the interface cable signed assignments
meet RS366 specifications. For systems not requiring an ACU interface, the parallel I/O port can be
used for any general purpose interface requiring
RS232C compatibility.

interrupt control provide the intelligence to manage
sophisticated communications operations on-board
the iSBC 544 board. The timer/counters and interrupt control are also common to the I/O area providing programmable baud rates to the USARTs and
prioritizing interrupts generated from the USARTs.
The central computer functions are protected for access only by the on-board 8085A. Likewise, the onboard 8085A may not gain access to the system bus
when being used as an intelligent slave. When the
iSBC 544 is used as a bus master, the on-board
8085A CPU controls complete system operation accessing on-board functions as well as memory and
I/O expansion. The third major segment, dual port
RAM memory, is the key link between the iSBC 544
intelligent slave and bus masters managing the system functions. The dual port concept allows a common block of dynamic memory to be accessed by
the on-board 8085A CPU and off-board bus masters. The system program can, therefore, utilize the
shared dual port RAM to pass command and status
information between the bus masters and on-board
CPU. In addition, the dual port concept permits
blocks of data transmitted or received to accumulate
in the on-board shared RAM, minimizing the need
for a dedicated memory board.

Central Processing Unit
Intel's powerful 8-bit n-channel 808SA CPU, fabricated on a single LSI chip, is the central processor for
the iSBC 544. The 808SA CPU is directly software
compatible with the Intel 8080A CPU. The 808SA
contains six 8-bit general purpose registers and an
accumulator. The six general purpose registers may
be addressed individually or in pairs, providing both
single and double precision operators. The minimum
instruction execution time is 1.45 microseconds. The
8085A CPU has a 16-bit program counter. An external stack, located within any portion of iSBC 544
read/write memory, may be used as a last-in/firstout storage area for the contents of the program
counter, flags, accumulator, and all of the six general purpose registers. A 16-bit stack pointer controls
the addressing·of this external stack. This stack provides subroutine nesting bounded only by memory
size.

Serial 110
Four programmable communications interfaces using Intel's 8251 A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) are contained
on the board and controlled by the on-board CPU in
combination with the on-board interval timer/counter to provide all common communication frequencies. Each USART can be programmed by the system software to individually select the desired asynchronous or synchronous serial data transmission
technique (including IBM Bisync). The mode of operation (Le., synchronous or asynchronous), data format, control character format, parity, and baud rate
are all under program control. Each 8251A provides
full duplex, double-buffered, transmit and receive capability. Parity, overrun, and framing error detection
are all incorporated in each USART. Each channel is
fully buffered to provide a direct interface to RS232C
compatible terminals, peripherals, or synchronous/
asynchronous modems. Each channel of RS232C
command lines, serial data lines, and signal ground
lines are brought out to 26-pin edge connectors that
mate with RS232C flat or round cable.

EPROM/ROM Capacity
Sockets for up to 8K by1es of nonvolatile read only
memory are provided on the iSBC 544 board. Read
only memory may be added in 2K by1e increments
up to a maximum of 4K bytes using Intel 2716
EPROMs or masked ROMs; or in 4K byte increments up to 8K by1es maximum using Intel 2732
EPROMs. All on-board EPROM/ROM operations
are performed at maximum processor speed.

RAIIIICapacity
The iSBC 544 contains 16K bytes of dynamic read/
write memory using Intel 2117 RAMs. Power for the
on-board RAM may be provided on an auxiliary power bus, and memory protect logic is included for
RAM battery backup requirements. The iSBC 544
contains a dual port controller, which provides dual
port capability for the on-board RAM memory. RAM
accesses may occur from either the on-board 8085A
CPU or from another bus master, when used as an
intelligent slave. Since on-board RAM accesses do
not require the MULTIBUS, the bus is available for
concurrent bus master use. Dynamic RAM refresh is
accomplished automatically by the iSBC 544 for accesses originating from either the CPU or from the
MULTIBUS.

Parallel 110 Port
The iSBC 544 provides a 1O-bit parallel I/O interface
controlled by an Intel 8155 Programmable Interface
(PPI) chip. The parallel I/O port is directly compatible with an Automatic Calling Unit (ACU) such as the
6-26

inter

iSBC® 544 COMMUNICATIONS CONTROLLER

Addressing - On board RAM, as seen by the onboard 8085A CPU, resides at address 8000HBFFFH. On-board RAM, as seen by an off-board
CPU, may be placed on any 4K byte address boundary. The iSBC 544 provides extended addressing
jumpers to allow the on-board RAM to reside within
a one megabyte address space when accessed via
the MULTIBUS. In addition, jumper options are provided which allow the user to protect 8K or 12K
bytes on-board RAM for use by the on-board 8085
CPU only. This reserved RAM space is not accessible via the MULTIBUS and does not occupy any system address space.

vals. The sixth PIT timer/counter (TINT1) can be
used to generate interrupt intervals to the on-board
8085A. In addition to the timer/counters on the 8253
PITs, the iSBC 544 has a 14-bit timer available on
the 8155 PPI providing a third general use timer/
counter (TINTO). This timer output is jumper selectable to the interrupt structure of the on-board 8085A
CPU to provide additional timer/counter capability.
Timer Functions - In utilizing the iSBC 544 board,
the systems designer simply configures, via software, each timer independently to meet systems requirements. Whenever a given baud rate or interrupt
interval is needed, software commands to the programmable timers select the desired function. The
on-board PITs together with the 8155 provide a total
of seven timer/counters and six operating modes.
Mode 3 of the 8253 is the primary operating mode of
the four dedicated USART baud rate generators.
The timer/counters and useful modes of operation
for the general use timer/counters are shown in Table 1.

Static RAM - The iSBC 544 board also has 256
bytes of static RAM located on the Intel 8155 PPI.
This memory is only accessible to the on-board
8085A CPU and is located at address 7FOOw
7FFFH·

Programmable Timers
The iSBC 544 board provides seven fully programmable and independent interval timer/counters utilizing two Intel 8253 Programmable Interval Timers
(PIT), and the Intel 8155 . .The two Intel 8253 PITs
provide six independent BCD or binary 16-bit interval
timer/counters and the 8155 provides one 14-bit binary timer/counter. Four of the PIT timers (BDGO-3)
are dedicated to the USARTs providing fully independent programmable baud rates.

Interrupt Capability
The iSBC 544 board provides interrupt service for up
to 21 interrupt sources. Any of the 21 sources may
interrupt the intelligent controller, and all are brought
through the interrupt logic to 12 interrupt levels. Four
interrupt levels are handled directly by the interrupt
processing capability of the 8085A CPU and eight
levels are serviced from an Intel 8259A Programmable Interrupt Controller (PIC) routing an interrupt request output to the INTR input of the 8085A (see
Table 2).

Three General Use Timers - The fifth timer
(BDG4) may be used as an auxiliary baud rate to any
of the four USARTs or may alternatively be cascaded with timer six to provide extended interrupt inter-

Table 1. Programmable Timer Functions
Function

Operation

Interrupt on Terminal
Count (Mode 0)

When terminal count is reached, an interrupt request is
generated. This function is useful for generation of realtime clocks.

Rate Generator
(Mode 2)

Divide by N counter. The output will go low for one input
clock cycle and high for N - 1 input clock periods.

Square-Wave Rate
Generator (Mode 3)

Output will remain high until one-half the TC has been
completed, and go low for the other half of the count.
This is the primary operating mode used for generating a
Baud rate clocked to the USARTs.

Software Triggered
Strobe (Mode 4)

When the TC is loaded, the counter will begin. On TC
the output will go low for one input clock period.

Single Pulse

Single pulse when TC reached.

Counter

8253
TINT1

8253
BDG4*

8253
BDGO-4
TINT1

8253
BDG4*
TINT1

8155
TINTO

Repetitive Single Pulse

Repetitive Single pulse each time TC is reached until a
new command is loaded .

8155
TINTO

• BDG4 is jumper selectable as an auxiliary baud rate generator to the USARTs or as a cascaded output to TINT1. BDG4
may be used in modes 2 'and 4 only when configured as a cascaded output.

6-27

inter

iSBC® 544 COMMUNICATIONS CONTROLLER

to the 8085A interrupt inputs, TRAP, RST 7.5, RST
6.5 and RST 5.5 have a unique vector memory address. An 8085A jump instruction at each of these
addresses then provides software linkage to interrupt service routines located independently anywhere in the Memory. All interrupt inputs with the
exception of the TRAP may be masked via software.

Table 2 Interrupt Vector Memory Locations
Interrupt
Source

Vector
Location

Power Fail
TRAP
24H
8253 TlNT1
RST7.5
3CH
8155 TINTO
Ring Indicatod1) RST 6.5
34H
Carrier Detect
Flag Interrupt
RST5.5
2CH
INTOI -INT7 I (1 of 8)
RXRDYO
INTR
Programmable
TXRDYO
RXRDY1
TXRDY1
RXRDY2
TXRDY2
RXRDY3
TXRDY3

Interrupt
Level
1
2
3

8259A Interrupts - Eight interrupt sources signaling transmitter and. receiver ready from the four
USARTs are channeled directly to the Intel 8259A
PIC. The PIC then provides vectoring for the next
eight interrupt levels. Operating mode and priority
assignments may be reconfigured dynamically via
software at any time during I system operation. The
PIC accepts transmitter and receiver interrupts from
the four USARTs. It then determines which of the
incoming requests is of highest priority, determines
whether this request is of higher priority than the level currently being serviced, and , if appropriate, issues an interrupt to the CPU. The output of the PIC
is applied directly to the INTR input of the 8085A.
Any combination of interruptlevels may be masked,
via software, by storing a single byte in the interrupt
mask register of the PIC. When the 8085A responds
to a PIC interrupt, the PIC will generate a CALL instruction for each interrupt level. These addresses
are equally spaced at intervals of 4 or 8 (software
selectable) bytes. Interrupt response to the PIC is
software programmable to a 32- or 64-byte block of
memory. Interrupt sequences may be expanded
from this block with a Single 8085A jump instruction
at each of these addresses.

4
5-12

NOTE:
1. Four ring indicator interrupts and four carrier detect interrupts are summed to the RST 6.5 input. The 8155 may be
interrogated to inspect anyone of the eight Signals.

Interrupt Sources - The 22 interrupt sources originate from both on-board communications functions
and the MULTISUS. Two interrupts are routed from
each of the four USARTs .(8 interrupts total) to indicate that the transmitter and receiver are ready to
move a data byte to or from the on-board CPU. The
PIC is dedicated to accepting these 8 interrupts to
optimize USART service request. One of eight interrupt request lines are jumper selectable for direct
interface from a bus master via the system bus. Two
auxiliary timers (TINTO from 8155 and TINT1 from
8253) are jumper selectable to provide general purpose counterltimer interrupts. A jumper selectable
Flag Interrupt is generated to allow any bus master
to interrupt the iSSC 544 by writing into the base
address of the shared dual port memory accessable
to the system. The Flag Interrupt is then cleared by
the iSSC 544 when the on-board processor reads
the base address. This interrupt provides an interrupt link between a bus master and intelligent slave
(see System Programming). Eight inputs from the
serial ports are monitored to detect a ring indicator
and carrier detect from each of the four channels.
These eight interrupt sources are summed to a single interrupt level of the 8085A CPU. If one of these
eight interrupts occur, the 8155 PPI can then be interrogated to determine which port caused the interrupt. Finally, a jumper selectable Power Fail Interrupt
is available from the MULTISUS to detect a power
down condition.

Interrupt Output - In addition, the iSSC 544 board
may be jumper selected to generate an interrupt
from the on-board serial output data (SOD) of the
8085A. The SOD signal may be jumpered to anyone
of the 8 MULTISUS interrupt lines (INTOI -INT7 I) to
provide an interrupt signal directly to a bus master.

Power-Fail Control
.Control logic is also included to accept a power-fail
interrupt in conjunction with the AC-Iow signal from
the iSSC 635 Power Supply or equivalent.

Expansion Capabilities
When the iSSC 544 board is used as a single board
communications controller, memory and 1/0 capacity may be expanded and additional functions added
using Intel MULTISUSTM compatible expansion
boards. In this mode, no other bus masters may be
configured in the system. Memory may be expanded
to a 65K byte capacity by adding user specified combinations of RAM boards, EPROM boards, or combination boards. Input/output capacity may be in'
creased by adding digital 1/0 and analog 1/0 expan-

8085 Interrupt - Thirteen of the twenty-two interrupt sources are available directly to four interrupt
inputs of the on-board 8085A CPU. Requests routed
6-28

intJ

iSBC® 544 COMMUNICATIONS CONTROLLER

sion boards. Furthermore, multiple iSBC 544 boards
may be included in an expanded system using one
iSBC 544 board as a single board communications
computer and additional controllers as intelligent
slaves.

vi des a linker, object code locater, and library manager. A unique in-circuit emulator (ICE-85) option
provides the capability of developing and debugging
software directly on the iSBC 544 board.

SPECIFICATIONS

System Programming
In the system programming environment, the
iSBC 544 board appears as an additional RAM
memory module when used as an intelligent slave.
The master CPU communicates with the iSBC 544
board as if it were just an extension of system memory. Because the iSBC 544 board is treated as memory by the system, the user is able to program into it
a command structure which will allow the iSBC 544
board to control its own I/O and memory operation.
To enhance the programming of the iSBC 544
board, the user has been given some specific tools.
The tools are: 1) the flag interrupt, 2) an on-board
RAM memory area that is accessible to both an offboard CPU and the on-board 8085A through which a'
communications path can exist, and 3) access to the,
bus interrupt line.
Flag Interrupt - The Flag Interrupt is generated
anytime a write command is performed by an offboard CPU to the base address of the iSBC 544
board's RAM. This interrupt provides a means for
the master CPU to notify the iSBC 544 board that it
wishes to establish a communications sequence. In
systems with more than one intelligent slave, the
flag interrupt provides a unique interrupt to each
slave outside the normal eight MULTIBUS interrupt
lines (INTO/ -INT7/).

Serial Communications Characteristics
Synchronous Asynchronous -

5-8 bit characters; automatic
sync insertion; parity.
5-8 bit characters; break character generation; 1, 1%, or 2
stop bits; false start bit detection; break character detection.

Baud Rates
Frequency (KHz)(1)
Baud Rate (Hz)(2)
(Software
Selectable)
Synchronous Asynchronous

153.6
76.8
38.4
19.2
9.6
4.8
6.98

38400
19200
9600
4800
6980

+16

+64

9600
4800
2400
1200
600
300

2400
1200
600
300
150
75
110

NOTES:
1. Frequency selected by I/O writes of appropriate 16-bit
frequency factor to Baud Rate Register.
2. Baud rates shown here are only a sample subset of possible software programmable rates available. Any frequency from 18.75 Hz to 614.4 KHz may be generated utilizing
on-board crystal oscillator and 16-bit Programmable Interval Timer (used here as a frequency divider).

On-Board RAM - The on,board 16K byte RAM
area that is accessible to both an off-board CPU and
the on-board 8085A can be located on any 4K
boundary in the system. The selected base address
of the iSBC 544 RAM will cause an interrupt when
written into by an off-board CPU.
Bus Access - The third tool to improve system
operation as an intelligent slave is access to the
MULTIBUS interrupt lines. The iSBC 544 board can
both respond to interrupt Signals from an off-board
CPU, and generate an interrupt to the off-board CPU
via the MULTIBUS.

8085A CPU
Word Size -

System Development Capability
The development cycle of iSBC 544 board based
products may be significantly reduced using the Intellec series microcomputer development systems.
The Intellec resident macroassembler, text editor,
and system monitor greatly simplify the design, development and debug of iSBC 544 system software.
An optional ISIS-II diskette operating system pro-

Cycle Time -

8, 16 or 24 bits/instruction; 8 bits of
data
1.45/p.s ± 0.01 % for fastest executable instruction; i.e., four clock cycles.

Clock Rate -

2.76 MHz ± 0.1 %

System Access Time
Dual port memory -

740 ns

NOTE:
Assumes no refresh contention.
6-29

inter

iSBC® 544 COMMUNICATIONS CONTROLLER

Memory Capacity

Interrupts

On-Board ROM/PROM - 4K, or 8K bytes of user
installed ROM or EPROM
On-Board Static RAM -

256 bytes on 8155

On-Board Dynamic RAM (on-board access) 16K bytes. Integrity' maintained during power failure
with user-furnished batteries (optional)
On-Board Dynamic RAM (MULTIBUS access) 4K, 8K, or 16K bytes available to bus by swtich selection

Memory Addressing
On-Board ROM/PROM - O-OFFF (using 2716
EPROMs or masked ROMs); 0-1FFF (using 2732A
EPROMs)
.
On-Board Static RAM - 256 bytes: 7FOO-7FFF
On-Board Dynamic RAM (on-board access) 16K bytes: 8000-BFFF.
On-Board Dynamic RAM (MULTIBUS® access) any 4K increment OOOOO-FFOOO which is switch and
jumper selectable. 4K, 8K or 16K bytes can be made
available to the bus by switch selection.

I/O Capacity
Serial - 4 programmable channels using four
8251 A USARTs
Parallel - 10 programmable lines available for Bell
801 ACU,or equivalent use. Two auxiliary jumper
selectable signals

I/O Addressing
On-Board Programmable I/O
Port

Data

Control

USARTO
USART 1
USART2
USART3
8155 PPI

00
02
04
06
E9 (PortA)
EA (Port B)
EB (PortC)

01
03
05
07
E8

Address for 8259A Registers (Hex notation, I/O
address space)
E6
E6
E7
E6
E7
E6

Interrupt request register
In-service register
Mask register
Command register
Block address register
Status (polling register)

NOTE:
Several registers have the same physical address:
Sequence of access and one data bit of the control
word determines which register will respond.
Interrupt levels routed to the 8085 CPU automatically vector the processor to unique memory locations:
24 TRAP
3C RST 7.5
34 RST 6.5
?C RST 5.5

Timers
Addresses for.8253 Registers (Hex notation, I/O
address space)
Programmable Interrupt Timer One
08
Timer 0
BOGo
09
Timer 1
BOG1
OA
Timer 2
BOG2
OB
Control register
Programmable Interrupt Timer Two
OC
Timer 0
BOG3
00
Timer 1
BOG4
OE
Timer 2
TINT1
OF
Control register
AddresS for 8155 Programmable Timer
E8
Control
, Timer (LSB)
TINTO
Timer (MSB)
TINTO
EO
Input Frequencies - Jumper selectable reference
1.2288 MHz ± 0.1% (0.814 ,""S period nominal) or
1.843 MHz ± 0.1 % crystal (0.542 ,""S period, nominal)

iSBC® 544 COMMUNICATIONS CONTROLLER

Output Frequencies (at 1.2288 MHz)
Function

Single
Timer/Counter

Dual Timer/Counter
(two timers cascaded)

Min

Max

Min

Max

Real·Time Interrupt Interval

1.63 J-ts

53.3 J-ts

3.26 J-ts

58.25 min

Rate Generator (frequency)

18.75 Hz

614.4 KHz

0.00029 Hz

307.2 KHz

Interfaces

Connectors

Serial I/O - EIA Standard RS232C signals provided and supported:
Carrier Detect
Clear to Send
Data Set Ready
Data Terminal Ready
Request to Send
Receive Clock

Receiver Data
Ring Indicator
Secondary Receive Data'
Secondary Transmit Data'
Transmit Clock
Transmit Data
DTE Transmit clock
* Optional if parallel I/O port is not used as Automatic Calling Unit.

Centers
(in.)

Mating
Connectors

Bus

0.156

Viking
2KH43/9AMK12

Parallel I/O

0.1

3M 3415-000 or
AMP 88083-1

Serial 110

0.1

3M 3462-000 or
AMP 88373-5

Memory Protect

Parallel I/O - Four inputs and eight outputs (includes two jumper selectable auxiliary outputs). All
signals compatible with EIA Standard RS232C. Directly compatible with Bell Model 801 Automatic
Calling Unit, or equivalent.
MULTIBUS -

Pins
(qty)

Interface

An active·low TTL compatible memory protect Signal
is brought out on the auxiliary connector which,
when asserted, disables read/write access to RAM
memory on the board. This input is provided for the
protection of RAM contents during the system power-down sequences.

Compatible with iSBC MULTIBUS.

On-Board Addressing

Bus Drivers

All communications to the parallel and serial 110
ports, ·to the timers, and to the interrupt controller,
are via read and write commands from the on-board
8085A CPU.

Auxiliary Power

Function

Characteristic

Sink
Current (mA)

Data
Address
Commands

Tri-state
Tri-state
Tri-state

50
15
32

NOTE:

Used as a master in the Single board communications
computer mode.

An auxiliary power bus is provided to allow separate
power to RAM for systems requiring battery backup
of read/write memory. Selection of this auxiliary
RAM power bus is made via jumpers on the board.

Physical Characteristics

6-31

Width:

30.48 cm (12.00 inches)

Depth:
Thickness:
Weight:

17.15 cm (6.75 inches)
1.27 cm (0.50 inch)
3.97 gm (14 ounces)

iSBC® 544 COMMUNICATIONS CONTROLLER

Electrical Characteristics
DC Power Requirements
Current Requirements
Configuration
With 4K EPROM
(using 2716)
Without EPROM

Vee = +5V ±5%
(max)

Voo = ± 12V ±5%
(max)

VBB = -5V(3) ±5%
(max)

VAA = -12V ±5%
(max)

Icc = 3.4A max

IDD = 350 rnA max

IBB = 5mAmax

IAA = 200 rnA max

3.3Amax

350 rnA max

5 rnA max

200 rnA max

RAM only(1)

390 rnA max

176 rnA max

5 rnA max

RAM(2) refresh
only

390 rnA max

20 rnA max

5mAmax

NOTES:
1. For operational RAM only, for AUX power supply rating.
2. For RAM refresh only. Used for battery backup requirements. No RAM accessed.
3. Vee is normally derived on-board from VAA, eliminating the need for a Vee supply. If it is desired to supply Vee from the
bus, the current requirement is as shown.

Reference manuals are shipped with each product
only if designated SUPPLIED (see .above). Manuals
may be ordered from any Intel sales representative,
distributor office or from Intel Literature Department,
3065 Bowers. Avenue, Santa Clara, California 95051.

Environmental Characteristics
Operating Temperature: O°C to 55°C (32°F to 131°F)
Relative Humidity: To 90% without condensation

Reference Manual .

ORDERING INFORMATION

502160 - iSBC 544 Intelligent Communications
Controller Board Hardware Reference Manual (NOT
SUPPLIED)
.

6-32

Part Number

Description

iSBC 544

Intelligent Communications Controller

inter
•
•

iSBC® 561
SOEMI (Serial OEM Interface)
CONTROLLER BOARD
Includes a SMC-to-BNC Cable
• Assembly
to Attach into the IBM 3270

Dedicated I/O Controller Provides a
DirectConnection of MULTIBUS®Based Systems to an IBM 9370 or 4361
Mainframe Host or to any IBM System/
370 via an IBM 3174 Subsystem Control
Unit via IBM's SOEMI (Serial OEM
Interface) Protocol

Information Display System

•

On-Board Diagnostic Capability
Provides Operational Status of Board
Function and Link with the Host

by a Complete Family of
• Supported
Single Board Computers, Memory,

Physical Interface is via IBM 3270 Coax
with a Maximum Distance of 1.5 km

Digital and Analog I/O, Peripheral and
Graphics Controllers' Packaging and
Software

•
Dual I/O Processors Manage Both
• SOEMI
and MULTIBUS® Interfaces

Maximum Transmission Rate of 2.36
Megabits/Second

The Intel iSBC 561 SOEMI (Serial OEM Interface) Controller Board is a member of Intel's family of single
board computers, memory, I/O, peripheral and graphics controller boards. It is a dedicated intelligent I/O
controller on a MULTIBUS form-factor printed circuit card. The board allows OEMs of MULTIBUS-based
systems a direct, standard link to an IBM 9370 Information System, to an IBM System 4361, or to any IBM
System/370 attached to an IBM 3174 Subsystem Control Unit via the SOEMI (Serial OEM Interface). The
iSBC 561 Controller also provides IBM System/370 users access to the broad range of applications supported
by hundreds of MULTIBUS vendors.
The SOEMI interface is comprised of an IBM System/370 programming interface and an IBM 3270 coax
interface. It is a flexible, high speed, point-to-point serial interface offered as a feature on the IBM 9370 and
4361 processor families and on the 3174 Subsystem Control Unit. The iSBC 561 SOEMI Controller Board
contains two processors and provides the necessary intelligence for conversion, control functions, and buffer
management between the IBM mainframe and the MULTIBUS system. This board allows an IBM user to
distribute control and information to MULTIBUS compatible systems for a variety of applications including
factory automation, data acquisition,measurement, control, robotics, process control, communications, local
area networking, medical instrumentation, and laboratory automation.

290114-1

"IBM is a trademark of International Business Machines Corp.

6-33

November 1988
Order Number: 280114-002

inter

iSBC® 561 BOARD

SOEMI INTERFACE OVERVIEW
The Serial OEM Interface (SOEMI) is a new means
of connecting Original Equipment Manufacturer
(OEM) MULTIBUS-based systems and subsystems
to an IBM System/370 mainframe. Previously, the
only low-cost way to attach non-IBM equipment into
the IBM mainframe environment was to use 3270
emulation software and hardware adaptors. This
type of interface is low-speed (approx. 19.6K bits/
sec.) and not very flexible as to the type and format
of data that can be transferred. The 3270 emulators
must mimic the device formats of the displays and
printers that are typically attached on this interface;
stripping out command characters, carriage return
and I line feed characters, etc. The SOEMI interface
is available on; the IBM 9370, the IBM 4361, and the
3174 Subsystem Control Unit model1L. The SOEMI
Protocol is much faster and more flexible, in that any
type of raw data or formatted data may be sent
across the connecting coax cable.
The SOEMI attachment into the MULTIBUS system
architecture, via the iSBC 561 SOEMI Controller
Board, extends the attachment capabilities of the
IBM 9370, 4361 and 3174 to a variety of systems,
boards, and I/O devices provided by other manufacturers. Figure 1 is an example of the variety achievable on Intel's MULTIBUS (IEEE 796) system architecture.
The SOEMI interface utilizes the System/370 Programming Interface on the IBM 9370, 4361 and
3174 to create the protocols and formats required by
a given application for connection to and communication with virtually any type of OEM device.

IBM 3174 MODEL 1L
SUBSYSTEM CONTROL UNIT

8086
166. 286. etc.
IRMXT'M OPERATING
SYSTEM
XENIX'

The System/370 Programming Interface provides
the standard System/370 I/O instructions for exchanging data between the host and the
MULTIBUS-based system. System/370 applications
see MULTIBUS system I)'lemory as one or more entities called "spaces." The System/370 host system
program writes to and reads from these spaces. The
user can define the number of spaces or the layout
of fields in the SOEMI interface at his discretion and
as required by the application and the MULTIBUS
system configuration.
The 3270 coax interface provides the physical connection between the OEM MULTIBUS system and
the IBM host. The coax cable (type RG62AU) can
operate over a distance of 1.5 kilometers at a maximum transfer rate of 2.3587 Mbits/second. The distance of 1.5 kilometers can be increased to a maximum of 3 kilometers by installing an IBM 3299 Terminal Multiplexer (repeater) between the IBM 9370,
4361 or 3174 and the MULTIBUS system. The protocol at the coax interface includes a polling mechanism, a set of Write and Read commands, and requires a buffer with an address register at the OEM
controller end.
The connection to the IBM 4361 is made via the IBM
3270 Information Display System's Display/Printer
Adapter (DPA) and/or Work Station Adapter (WSA)
coax ports. The DPA can drive up to sixteen 32701
SOEMI coax ports, and is the standard configuration. The WSA is an optional add-on to the IBM 4361
that increases the total number coax ports supported to 40. The connection to the IBM 9370 is made
via the Workstation Subsystem Controller feature,
and a workstation adapter which can connect up to

IBM 4361
DISPLAY PRINTER ADAPTER
OR WORK STATION ADAPTER

RAM
ROM
EPROM
BUBBLES

'XENIX is a trademark of MICROSOFT Corporation

IBM 8370
WORKSTATION SUBSYSTEM
CONTROLLER

ETHERNET
IEEE 488
RS 232
MAP
ANALOG 110
DIGITAL 110
OTHER INTERFACES

DEVICES
DISK
DISKETTE
PRINTER
DISPLAY (ASC II)

290114-2

Figure 1. IBM 4361-to-MULTIBUS® Attachment Capability Block Diagram

inter

iSBC® 561 BOARD

6 SOEMI ports. This can be increased to 32 ports
using optional terminal multiplexers. The connection
to the IBM 3174 model 1L is made via IBM dual-purpose connectors (DPC) which can connect up to 4
SOEMI ports. This can be increased to 32 ports using terminal multiplexer adapters. A typical configuration can support an aggregate data rate of approximately 45K Bytes/second (approx. 360K bits/second).

bus ownership, generate bus clocks, respond to and
generate interrupts, etc. With the iSBC 561 controller connected to the mainframe, all MULTIBUS system resources are available to the IBM host program/controller. From the IBM side, the mainframe
is capable of accessing the entire 16 MBytes of
MULTIBUS system memory, 64K Bytes of I/O
space, and all on-board resources of the iSBC 561
board. Other intelligent MULTIBUS boards access
iSBC 561 controller services through normal interrupt mechanisms.

OPERATING ENVIRONMENT
Using the SOEMI interface in a relatively low-level
application may simply require the user to write System/370 application control programs that reside in
the IBM mainframe. A more elaborate implementation would also involve application programs that reside in the MULTIBUS system under its "native" op-

The iSBC board functions as a slave to the host
mainframe,
reacting
and
executing
under
System/370 program control as as mainframe resource. In addition, it has a full multi master MULTIBUS interface that allows the board to arbitrate for

,----------------------,

I FRONT.END
LS~'~

I
I
I
I
I
I
I.
I
I

__, __ -.l

____ _

I
I
I
--..l--l
I

I~~~~g~

I
'-_-.1 ____ _
I BACK·END

SECTIO~N_~"

I
I
I

I
I

I
I
I

I
I
_-.l

L_
MULTlBUS· I SYSTEM BUS

290114-3

Figure 2_ iSBC® 561 SOEMI (Serial OEM Interface) Controller Board Functional Block Diagram
6-35

inter

iSBC® 561 BOARD

ing on the direction of the transfer and type of operation or task to be performed. The information is
stored in the shared buffer as a set(s) of structured
fields. The back-end processor transfers this information by performing 8- or 16-bit data transfers to or
from the MULTIBUS system bus, the shared buffer,
and the local memory.

erating environment (i.e., iRMX or XENIX operating
systems) and an end-to-end protocol that ties both
sets of application programs together.

ARCHITECTURE
The iSBC 561 board is functionally partiti,oned into
three major sections: the front-end section, the common section, and the back-end section (see Figure
2).

The control program for this high-speed, back-end
processor is resident in two local ROM sites. The
processor also has access to 16K bytes of static
RAM for local data storage.
.

Front-End Processor Section:
IBM Host Interface

The back-end section interfaces to other MULTIBUS
boards through two bus controllers, a bus arbiter,
and the address, data, and command buffers for access over the 24 address lines and 16 data lines of
the MULTIBUS system bus.

The front-end section of the iSBC 561 Controller
board interfaces with the IBM mainframe via the IBM
3270 Information Display System, and consists of an
8X305 Signetics microcontroller, the 8X305 instruction memory, and the coaxial interface. The 8X305
executes the coax commands and places the structured field's instructions in shared memory buffers
for subsequent execution by the back-end processor. The front-end instruction memory consists of
three 2K x 8-bit PROMs which provide the instruction code for the 8X305 processor and the information needed to generate the various control signals
required by the 8X305 to elicit system functions. The
information contained in each PROM is not modifiable by the user. The coaxial interface is based on a
DP8340 transmitter component that converts 8-bit
parallel data received from the front-end processor
to a 12-bit serial stream, and a DP8341 receiver
component, that converts a 12-bit serial stream of
data from the mainframe to parallel data with separated command and parity bits.

OPERATION FLOW
The commands and information passed along the
coax by the IBM host to theiSBC 561 controller represent what is known as a "structured field." The
iSBC 561 front-end processor strips out the 12-bit
protocol header deposits the remaining structured
field(s) in the shared memory buffer, and notifies the
back-end processor, The back-end processor then
processes these structured fields in order to access
the proper MULTIBUS memory space and 1/0 ports.
It then deposits the information or task in the space
and notifies the MULTIBUS subsystem master that a
transfer has occurred and is awaiting service.
When requiring service, the MULTIBUS system application sends an interrupt to the iSBC 561 board.
The board then issues an attention to the mainframe. At this point, the mainframe is under no obligation or time constraint to service the interrupt, and
its response is application dependent.

Common Section:
Shared Memory Buffer
The common section of the iSBC 561 board consists
of two 8-bit, bi-directional message registers and a
16K x 8-bit static RAM shared buffer. This shared
memory buffer between the front-end processor and
the back-end processor is the resource for transferring information and control messages between the
IBM host and the MULTIBUS system.

The mainframe issues commands to service the interrupt. The information concerned with the interrupt
is then passed through the shared memory and serialized by the iSBC 561 board before being sent to
the mainframe. The exact communications protocol
used for this end-to-end transfer is defined by the
user application programs funning in both operating
environments.

Back-End Processor Section:
MULTIBUS® Interface

Interface Connector/Cable Assembly

The back-end section of the board provides an intelligent interface to the MULTIBUS system bus, and
consists of the 8086-2 microprocessor, local memory, bus interface circuitry, and memory-mapped logic. The 8086 processor is capable of either retrieving
information the 8X305 placed in the shared buffer,
or placing information in the shared buffer, depend-

The cable assembly used to connect the iSBC 561
SOEMI Controller Board to the IBM mainframe or
3174 control unit cable assembly consists of RG180
type cable having an SMC connector on one end
(which mates to the iSBC 561 board right angle SMC
connector) and a BNC connector on the other end
(which mates to the IBM cable assembly connector).
6-36

infef

iSBC® 561 BOARD

SPECIFICATIONS

Cable Characteristics
Impedance:

coax connector-50 ohms (nominal)
external cable (user furnished)95 ohms (nominal)
Capacitance: 35 pF/ft
Propagation: 1.6 ns/ft

Operational Characteristics
Back-end processor- Intel 8086-2/5 MHz
- 20-bit address path; 8/16 bit
data path
Front-end processor- Signetics 8X305/8 MHz
- 16-bit instruction path; 8-bit
data path
Serial Transfer Rate- 2.3587 Mbits/second (max.
bit rate)
- 360K bits/second (approx.
aggregate throughput)
Serial Transfer Rate- Binary dipulse (with 12-bit
serial stream)
Memory Capacity - All iSBC 561 controller board
memory is available to onboard firmware only.
Common memory - 16K Bytes of Shared Buffer
memory (SRAM @ 0 wait
state access)
8086-2 memory
- 16K Bytes of EPROM;
- 16K Bytes of SRAM
8X305 memory
- 4K Bytes of Instruction memory (EPROM)
- 2K Bytes of Control memory
(EPROM)

Environmental Characteristics
Operating Temperature: 0° to 55°C at 200 LFM air
velocity
Operating Humidity: 10 to 85% non-condensing
(0° to 55°C)
Non-Operating Temperature: -40°C to 75°C
Shock: 30G for a duration of 11 ms with % sinewave
shape.
Vibration: 0 to 55 Hz with 0.0 to 0.010 inches peak
to peak excursion.

Reference Manuals
147048-001- iSBC 561 SOEMI (Serial OEM Interface) Controller Board Hardware Reference Manual (NOT SUPPLIED)
Reference manual may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, California 95051.
GA33-1585-0 (File No. S370-03-IBM Serial OEM
Interface (SOEMI) Reference Manual
(NOT SUPPLIED)

Physical Characteristics
Width:
Height:
Depth:
Weight:

30.48 cm (12.00 in)
17.15 cm (6.75 in)
1.78 cm (0.70 in)
510 gm (18 oz)

Reference manual may be ordered from IBM Advanced Technical Systems; Dept. 3291, 7030-16;
Schoenaicherstr. 220; 7030 Boeblingen. Federal
Republic of Germany.

Electrical Characteristics
DC Power Requirements:
Voltage-+ 5V
Current (Max)-6.28A
Current (Typ)-5.46A
Power Dissipation (Max)-35.5VA

ORDERING INFORMATION
Part Number Description
iSBC 561
SOEMI (Serial OEM Interface) Controller board

6-37

iSB(;® 548/549 TERMINAl. (;ONTROttERS

HIGH PERFORMANCE TERMINAL CONTROLLER BOARDS FOR
MIJLTIBIJS@I
The iSBC 548 and iSBC 549 are intelligent terminal controllers for MULTIBUS I applications. The
iSBC 548 provides basic multiuser support with 8 channels of RS 232 Asynchronous interface. The
iSBC 549 combines 4 serial channels with a real-time clock and a line printer interface. Acting as
intelligent slaves for communication expansion, these boards provide high performance, low cost
solutions for multi-user systems.

I'EATIJRES
ISBC 548 FEATURES
• Supports eight channels asynchronous
RS232 interface
ISBC 549 FEATURES
• Supports four channels asynchronous RS232
interface
• Line printer interface
• Real-time clock/calendar with battery backup
STANDARD ISBC 548/549 FEATURES
• 8 MHz 80186 Microprocessor
• Supports transfer rates up to 19.2K Baud
• 128K Bytes Zero Wait State DRAM (32K Dual
Port)
• Supports Full Duplex Asynchronous
Transmissions
• Jumper selectable memory mapping, 110
mapping and MULTIBUS Interrupts

intel·-----------'--InlE'1 CorPl)ratlon assumt'S 110 I"("SpHnSlhlllt~ fut UIl' U~' uf an~ m(,Ultr~ ut!k'r than ('irc'ultt~ emhudu't1ln an Intd p,ujut'1. Nu ulht'l' ,'il'ruIL pau.'nt lirt'nSl'~ art'
impllt'd. \nfllrmauun ('{Jntam('d !x'tt'ln supc:r:-;t.·dl's prl'\lOllSI~ pubhstll'd spt'('lfirf1licms UI! tllI':'i\' dt'\'j,,·s frum fnLd and is subject w rMoge: wi1huut nuLin'.

&:ptcmtJl:r. 19f18
Order Numht~r: 2HUtl74 UUI

,© Intel wrpIJr3110n 1988

6-38

FEATURES
ASt'NCHRONOIlS RS232 INTERFACE
SIlPPORT
The is[3C 5~815~9 :\s~nchronous RS232 Internal support is
presented in DTE Conrigufiltion. 82530 St'rial
OJIIllllllnications Controllers (SCCS) prOl ide channels of half!
full duplex serial 110. Confjgurabilit~ of the 82~30 allows
handling all as~·nchronous data furmats regardless of data
siZt'o Illll1lbpl· of start or stup bits. or parit~ requirements.
The synchronous transmission features of the 1)2530 are
not supported ..\n on-chip baud rate generator allows
indepenuent baod rates onPach channel. The serial lines
can .be brought to the bac~·panel I·ia ~O·pin connectors and
ribbon cable.

l.INE PRINTER INTERFACE
The iSBC 3~9 incorporates a standard linl' printer interface
compatible Ilith 113\1" or ('Rntronics" line printers.
Intelligent buffering on the iSBC 5~9 allows the CI'L' to
offload printing tas~s and return to higher priority jobs.

REAL-'I'IME CLOCN/CALENDAR
\Iultibus systems II ill bl'l1erit from the real·time clol'k
present on the iSBC 519 in applications requiring time
stamp operations. unattended boots and other calendar
requirements. The cloclJcalcndar circuit is backed up by a
non·rechargeable battery II hich keeps the rloclJcalendar
0flPmting for six munths Ilith aJI other power off.

B MHZ BOl86 MICROPROCESSOR
The 80186 central processor component prOlides highperformance. flexibility. and pO\\erful pro('essing. The
80186182530 combination I\ith on-hoard PRO\III:<:PRo\l
sitps. and dual·port R.\\I prol·ides the intelligence and speed
to manage multi·user communications.

MEMORt'
The iSBC ~481549 have three areas or memory on·buard:
dual·port RAM. private RAM. and EPROM. I:<:a('h board
contains 128K bytes or oll·boarci RAM. :121\ bytes or dualport RA~I can be addressed by other MULTIBUS boards.
Tht' dual port memory is configurable in a 16M byte
address space on 321\ byte boundaries as addressed rrom
the ~llIl;I'Ifl[lS port. The starting address. is jumper
selectahle.
The Sl~·tllid area 01" memory is 961\ bytes or private RAM
which is addressable by the 80186 on·board.
The third area or memory is r:PROM memory expansion.
Two 28·pin .II';UEC sockets are provided. These sockets
come popillatt'.d with two EPROMs which contain the
controller firmware. The boards cun support 2704. 27128
and 27256 EPROMs. giving a total capacity or 641' bytes.
The I:<:PROM runs with zero wait states if EPROMs of access
timeH 250 ns or less are used. No jumper changes are
needed to access dirferent si~e EPROMs.

WORLDWIDESERYICEANDSIlPPORT
Intd provides slIpport tor board repair or on·site service.
IJeIl'lopmcnt options include phone support. subscription
service. on·site consulting. and customer training.

f)IlAf,JTt' AND REf,JABll.ITt'
The iSHC ,,48 and iSBC 549 are designed 11ml manufactured
in lIl'l"Ol"danct' with Inters high quality standardS. We then
leriry quality through rigorous testing in our state-or-the-art
~;n\"ir()nmental Test Laboratory.

TRANSFER RATES IlPTO 19.2N BAIlD
CoJlectilely. each buard has dual·port R.\\I prill iding an on·
board bufrer to handle incoming and outgoing messages at
data rates up to 19.21' baud. The reSident firmllare
supports asy·nchronous RS232 serial channl'is. prill ides
modem contrul and perfOl'l1ls plllwr·lIp diagnostics. ~:ach
serial channel can be inclilidually programnll'd to difrl'rent
baud rates to allUl\" s~stem cunfigurations Ilith ciirrpring
terminal types.
*1B\1 is a trad('mar~ of In[{'rnalilmtlJ Hu.:'ln!'s.... \IClf'hillt':-:
·Cmtflmirs is a rt'~bll'rl'cl tradt'IllMk of Cl'ntronit':'. In('.

6-39

FEATURES

MULTIBUSOO SYSTEM BUS

MULTIBUS® SYSTEM BUS

"cure 1: TerminallCluster Controller Application

RS232 INTERFACE
CHlS 7 AND 8
(iSBC 548 ONLY)

RS232 INTERFACE
CHLS 5 AND 6
(iSBC 548 ONLY)

RS232 INTERFACE
CHLS 3AND4
(ALL BOARDS)

RAM CONTROL
SIGNALS

RS232 INTERFACE
CHLS 1 AND 2
(ALL BOARDS)

PRINTER INTERFACE
(iSBC 549 ONLY)

"cure:!: iSBC 548/5-/9 Boards Block Diagram

6-40

SPE(;IFI(;ATIONS
ENJlIRONMEN'I'AL CHARAC'I'ERIS'I'ICS

SERIAL COMMIJNICA'I'IONS
CHARAC'I'ERIS'I'ICS

Temperature - 0 to 55°C aL 200 Line,ar FeetiMinute M'M)
Air Velocity
Humidity 5% to 90% non-condensing (25 to 70°C)

.\synchronous only
6-8 bit chilracter length
1. 1y,. or 2 stop bits per character
Parit,
Programmable r1oc~
Brea~ Generation
Framing error detection

PHYSICAL CHARAC'I'ERIS'I'ICS

Baud Rates
The on-board firmware can automaticilill detert and set
baud rates of 150. 300. fiOO. 1200. ~800. 9600 and
Hl200. Other baud rates can be set by the host.
Serial RS232C Signals Supported
CD Carrier Detect
RXD Receile Data
TXD Transmit Data
OTR Data Terminal Read,
SG Signal Ground
DSR Data Set Read,
RTS Ready to Send
CTS Clear to Send
RI Ringer Indicator

MEMORY

On·Board Capacit,
16K

Start Address

27128

~2K

272:;li

6-1K

FHOOOII
1"00011

Maximum Power Required per Voltage
Voltage (Volts)
Current (Amps)
Power (Watts)
iSBC 548
17.5
3.49
+ J
.14
1.7
+ 12
-12
.11
1.3
iSBC 549
lfl.~
3.26
+ 5
.07
.8
+ 12
-12
.7
.06

Part NUBI#Jer DeSCriptiOll

iSBC 548

~'COOOH

8 Channel High Performance Terminal
Controller
4 Channel High Performance Terminal
Controller with Line Printer/Clock

REFERENCE MANIJALS
iSHC 546/547/548/549 High Performance Terminal
Controller Hardware Reference Manual - Orner Number
122704-002
I-\)r more information or the number of your nearest Intel
sales office. call 800-~1H-4725 (good in the U.S. and
Canada).

MIJL'I'IBIJS SYS'I'EM BIJS IN'I'ERFACE
The iSBC 5~8/5~9 boards meet \IL'LTIBLIS ilEP.P. 796) hus
specification 016 \12~ 116 \0 P..

DEJIICE DRIJlERS
Check the latest release of the following operating systl'ms
for detailS:
iR\I.\ 86

iSRC 549
30.34cm (12.00 in)
16.87em (6.75 in)
1.27 em (.~ in)
358 gm (12.5 oz)

POWER REt)IJIREMEN'I'S

iSBC 549

On-Board R\\I - 128K bytes total
Prilate R\\I - 96K bytes
Dual Port R\\1 - 32K bytes. can be addressed from
\IL'LTlBLS interface at any 32K houndary
betlleen 80000H and F800011 or betwcen
P80000H and 1"1"800011.

276-1

iSBC 548
30.34rm (12.00 in)
16.87cm (6.75 in)
1.27 em (.5 in)
400 gm (14 nz)

ORDERING INFORMA'I'ION

These signals are supportcd by the iSBC S~8/ii~9
Controller and on·board firnl\\are ..\11 signals may not IlP
supported by the host operating system.

EPRO\I Opliolls Component

Width
J,pngth
Height
Weight

iR\IX II

6-41

MULTIBUS®I
Digital and Analog
I/O Boards

iSBC® 517
COMBINATION 1/0 EXPANSION BOARD
•

48 Programmable 1/0 Lines with
Sockets for Interchangeable Line
Drivers and Terminators

•

Synchronousl Asynchronous
Communications Interface with RS232C
Drivers and Receivers

•

Eight Maskable Interrupt Request Lines
with a Pending Interrupt Register

•

1 ms Interval Timer

The iSBC 517 Combination I/O Expansion Board is a member of Intel's complete line of iSBC memory and I/O
expansion boards. The board interfaces directly with any iSBC single board computer via the system bus to
expand serial and parallel I/O capacity: The combir;Jation I/O board contains 48 programmable parallel I/O
lines. The system software is used to configure the I/O lines to meet a wide variety of system peripheral
requirements. The flexibility of the I/O interface is significantly enhanced by the capability of selecting the
appropriate combination of optional line drivers and terminators to provide the required sink current, polarity,
and drive/termination characteristics for each application. A programmable RS232C communications interface is provided on the iSBC 517. This interface may be programmed by the system software to provide
virtually any asynchronous or synchronous serial data transmission technique (including IBM Bi-Sync). A
comprehensive RS232C interface to CRTs, RS232C compatible cassettes, and asynchronous and synchronous modems is thus on the board. An on-board register contains the status of eight interrupt request lines
which may be interrogated from the system bus, and each interrupt request line is maskable under program
control. The iSBC 517 also contains a jumper selectable 1 ms interval timer and interface logic for eight
interrupt request lines.

280229-1

7-1

October 1986
Order Number: 280229-001

inter

iSBC® 517 EXPANSION BOARD

FUNCTIONAL DESCRIPTION
Programming Flexibility
The 48 programmable 1/0 lines on the iSBC 517 are
implemented utilizing two Intel 8255 programmable
peripheral interfaces. The system software is used
to configure these programmable 1/0 lines in any of
the combinations of unidirectional input/output, and
bidirectional ports indicated in Table 1. In order to
take full advantage of the large number of possible
1/0 configurations, sockets are provided for interchangeable 1/0 line drivers and terminators to provide the required sink current, polarity, and drive/termination characteristics for each application. The 48
programmable 1/0 lines and signal ground lines are
brought out to two 50-pin edge connectors that mate
with flat, round, or woven cable. Typical 1/0 read
access time is 280 nanoseconds. Typical 1/0 read
cycle time is 600 nanoseconds.

Communications Interface
The programmable communications interface on the
iSBC 517 is provided by an Intel 8251 Universal
Synchronousl Asynchronous Receiver/Transmitter
(USART). The USART can be programmed by the
system software to select the desired asynchronous
or synchronous serial data transmission technique
(including IBM Bi-Sync). The mode of operation (i.e.,
synchronous or asynchronous), data format, control
character format, parity, and asynchronous serial

transmission rate are all under program control. The
8251 provides full duplex, double-buffered transmit
and receive capability, and parity, overrun, and framing error detection are all incorporated in the
USART. The comprehensive RS232C interface on
the board provides a direct interface to RS232C
compatible equipment. The RS232C serial data lines
and signal ground lines are brought out to a 26-pin
edge connector that mates with RS232C compatible
flat or round cables.

Interrupt Request Lines
Interrupt requests may originate from eight sources.
Four jumper selectable interrupt requests can be automatically generated by the programmable peripheral interface when a byte of information is ready to
be transferred to the CPU (i.e., input buffer is full) or
a character has been transmitted (i.e., output data
buffer is empty). Two jumper selectable interrupt requests can be automatically generated by the
USART when a character is ready to be transferred
to the CPU (i.e., receive buffer is full) or a character
has been transmitted (transmit buffer is empty).
These six interrupt request lines are all maskable
under program control. Two interrupt request lines
may be interfaced directly from user designated peripheral devices via the I/O edge connector. An onboard register contains the status of all eight interrupt request lines, and may be interrogated by the
CPU. Each interrupt request line is maskable under
program control. Routing for the eight interrupt request lines is jumper selectable. They may be ORed

RS232C

COMPATIBLE

USER DESIGNATED PERIPHERALS

DEVICES

O~NTERRUPT
REQUEST
LINES

,....._..¥..-....

ADDRESS BUS
DATA BUS

CONTROL BUS

}

~
L/

MULTI.US
INTERFACE

280229-2
. NOTE:
Interrupts originating from the programmable communications interface and programmable peripheral interface are jumper selectable.

Figure 1. iSBC® 517 Combination 1/0 Expansion Board Block Diagram
7-2

iSBC® 517 EXPANSION BOARD

Table 1. Input/Output Port Modes of Operation
Mode of Operation
Unidirectional
Input

Lines
(qty)

Ports

1
2
3

8
8
4
4
8
8
4
4

4
5
6

Output
Latched 8<
Strobed

Unlatched

X
X
X

X
X

Bidirectional

Control

Latched 8<
Strobed

Latched

X
X

X
X(1)

X
X

X(1)
X

X
X

X·

X
X(2)
X(2)

X
X

NOTES:
1. Part of port 3 must be used as control port when either port 1 or port 2 are used as a latched and strobed input or a
latched and strobed output port or port 1 is used as a bidirectional port.
2. Part of port 6 must be used as a control port when either port 4 or port 5 are used as a latched and strobed input or a
latched and strobed output port or port 4 is used as a bidirectional port.

to provide a single interrupt request line for the iSBC
80/10B, or they may be individually provided to the
system bus for use by other iSBC single board computers.

Serial Communications Characteristics
Synchronous-5-8 bit characters; internal or external character synchronization; automatic sync insertion.

Interval Timer
Each board contains a jumper selectable 1 ms interval timer. The timer is enabled by jumpering one of
the interrupt request lines from the I/O edge connector to a 1 ms interval interrupt request signal
originating from the baud rate generator.

Asynchronous-5-8 bit characters; peak characters
generation; 1, 1%, or 2 stop bits; false start bit detectors.

Interrupts
SPECIFICATIONS
110 Addressing
Port

Eight interrupt request lines may originate from the
programmable peripheral interface (4 lines), the
USART (2 lines), or user specified devices via the
I/O edge connector (2 lines) or interval timer.

8255
8255
USART USART
No.1
No.2
Data Control
Control Control

Address X4 X5 X6 X8 X9 XA

Interrupt Register Address
NOTE:
X is any hex digit assigned by jumper selection.

X1
XO

1/0 Transfer Rate

NOTE:
X is any hex digit assigned by jumper selection.

Parallel-Read or write cycle time 760 ns max
Serial-(USART)
Baud Rate (Hz)
Frequency (kHz)
(Jumper
Asynchronous
(Program
Selectable)
Synchronous
Selectable)

153.6
76.8
38.4
19.2
9.6
4.8
6.98

38400
19200
9600
4800
6980

716
9600
4800
2400
1200
600
300

Interrupt mask register
Interrupt status register

Timer Interval
1.003 ms
1.042 ms

764
2400
1200
600
300
150
75
110

7-3

± 0.1 %
± 0.1 %

when 110 baud rate is selected
for all other baud rates

inter

iSBC® 517 EXPANSION BOARD

Bus Drivers

Interfaces

Function
Data
Commands

Bus-All signals TTL compatible
Parallel liD-Ali signals TTL compatible
Serial 1/0-RS232C
. Interrupt Requests-All TTL compatible

Sink Current (mA)
50
25

Physical Characteristics

Connectors

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Weight: 14 oz. (397.3 gm)

Interface Pins (qty) Centers (In.) Mating Connectors
Bus
86
0.156
CDC VPB01 E43AOOA 1
3M 3415'000 or
Parallel 1/0
50
0.1
TIH312125
3M 3462·000 or
Serial 1/0
26
0.1
TI H312113
AMP PE5·14559 or
lA.uxiliary(1 )
60
0.1
TIH311130

Electrical Characteristics
Average DC Current
Vcc = +5V ±5%
VDD = +12V ±5%
VAA = -12 ±5%
Icc = 2.4 mA max
IDD = 40 mA max
IAA = 60 mA.max

NOTE:

1. Connector heights and wire· wrap pin lengths are not
guaranteed to conform to Intel OEM or system packaging.
Auxiliary connector is used for test purposes only.

Line Drivers and Terminators

NOTE:
Does not include power required for optional liD
drivers and liD terminators. With eight 220fl/330fl.
input terminators installed, all terminator inputs low.

I/O Drivers-The following line drivers and terminators are compatible with all the liD driver sockets on
the iSBC 517:
Driver
7438
7437
7432
7426
7409
7408
7403
7400

Characteristics
Tri-state
Tri·state

Sink Current (mA)
48
48
16
16
16
16
16
16

Characteristics
I,OC
I
NI
I,OC
NI,OC
NI
I,OC
I

Environmental Characteristics
Operating Temperature-O°C to + 55°C

Reference Manual
9800388B-iSBC 517 Hardware Reference manual
(NOT SUPPLIED)
Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

NOTE:

I = Inverting; NI = non-inverting; OC = open·collector.
Ports 1 and 4 have 25 mA totem-pole drivers and
1 kfl terminators.

ORDERING INFORMATION

liD Terminators-220fl/330fl divider or 1 kfl pull up

Part Number

Description

SSC 517

Combination 110 Expansion Board

----::v---,-----,
2200

+5.

220Q/3300,f

~v-~- - - ' - - - - < 0 Isac 901 OPTION

1k0

1 kQ

+ SV ------"'l/Vlv-.- - - - - - 0 ISBC 902 OPTION

7-4

280229-3

iSBC® 569
INTELLIGENT DIGITAL CONTROLLER

•

Single Board Digital I/O Controller with
up to Four Microprocessors to Share
the Digital Input/Output Signal
Processing

•
•

3 MHz 8085A Central Control Processor

•
•

fil:l

Sockets for up to 8K Bytes of Intel
2758, 2716, 2732 Erasable
Programmable Read Only Memory

!II 48 Programmable Parallel I/O Lines

with Sockets for Interchangeable Line
Drivers or Terminators

Three Sockets for 8041/8741A
Universal Peripheral Interface (UPI-41A)
for Distributed Digital I/O Processing

•

Three Programmable Counters

I!!l 12 levels of Programmable Interrupt

Three Operational Modes
- Stand-Alone Digital Controller
- MULTIBUS® Master
-Intelligent Slave (Slave to MULTIBUS
Master)

Control

•
•

2K Bytes of Dual Port Static
Read/Write Memory

Single

+ 5V Supply

MULTIBUS Standard Control Logic
Compatible with Optional iSBC 80 and
iSBC® 86 CPU, Memory, and I/O
Expansion Boards

The Intel iSBC® 569 Intelligent Digital Controller is a single board computer (8085A based) with sockets for
three 8041 Al8741 A Universal Peripherals Interface chips (UPI-41A). These devices, which are programmed
by the user, may be used to offload the 8085A processor from time consuming tasks such as pulse counting,
event sensing and parallel or serial digital I/O data formatting with error checking and handshaking. The iSBC
569 board is a complete digital controller with up to four processors on a single 6.75 inches x 12.00 inches
(17.15 cm x 30.48 cm) printed circuit board. The 8085A CPU, system clock, read/write memory, non-volatile
memory, priority interrupt logic, programmed timers, MULTIBUS control and interface logic, optional UPI processors and optional line driver and terminators all reside on one board.

280232-1

7-5

October 1986
Order Number: 280232-001

inter

iSBC® 569 CONTROLLER

Intelligent Slave-The iSBC 569 controller can perform as an intelligent slave to any 8- or 16-bit MULTIBUS master CPU by offloading the master of digital control related tasks. Preprocessing of data for
the master is controlled by the on-board·8085ACPU
which coordinates up to three UPI-41A processors.

FUNCTIONAL DESCRIPTION
Intelligent Digital Controller
Three Modes of Operation-The iSBC 569 Inteiligent Digital Controller is capable of operating in one
of three modes; stand alone controller, bus master,
or intelligent slave.

Using the iSBC 569 board as an intelligent slave,
multi-channel digital control can be managed entirelyon-board, freeing a system master to perform other system functions. The dual port RAM memory allows the iSBC 569 controller to process and store
data without MULTIBUS memory contention.

Stand Alone Controller-The iSBC 569 board may
function as a stand alone, single board controller
with CPU, memory, and I/O elements on a single
board. Five volt (+ 5VDC) only operation allows configuration of low cost controllers with only a Single
power supply voltage. The on-board 2K bytes RAM
and up to 16K bytes ROM/EPROM, as well as the
assistance of three UPI-41A processors, allow significant digital I/O control from a single board.

Simplified Programming
By using Intel UPI-41 A processors for common
tasks such as counting, sensing change of state,
printer control and keyboard scanning/debouncing,
the user frees up time to work on the more important
application programming of machine or process optimization. Controlling the Intel UPI-41 A processors
becomes a simple task of reading or writing command and data bytes to or from the data bus buffer
register on the UPI device.

Bus Master-In this mode of operation, the iSBC
569 controller may interface with and control iSBC
expansion memory and I/O boards, or even other
iSBC 569 Intelligent Digital Controllers configured as
intelligent slaves (but no additional bus masters).

MULTIBUS

280232-2

Figure 1. iSBC® 569 Intelligent Digital Controller Block Diagram

7-6

inter

iSBC® 569 CONTROLLER

(EPROMs); in 2K byte increments up to a maximum
of 4K bytes using Intel 2316 ROMs or 2716
EPROMs; in 4K byte increments up to 8K bytes
maximum using Intel 2732 EPROMs; or in 8K byte
increments up to 16K bytes maximum using Intel
2364 ROMs (both sockets must cor,ltain same type
ROM/EPROM). All on-board ROM/EPROM operations are performed at maximum processor speed.

Central Processing Unit
A powerful Intel 8085A 8-bit CPU, fabricated on a
single LSI chip, is the central processor for the iSBC
569 controller. The six general purpose 8-bit registers may be addressed individually or in pairs, providing both single and double precision operations.
The program counter can address up to 64K bytes
of memory using iSBC expansion boards. The 16-bit
stack pointer controls the addressing of an external
stack. This stack provides sUb-routine nesting
bounded only by memory size. The minimum instruction execution time is 1.30 microseconds. The
8085A CPU is software compatible with the Intel
8080A CPU.

Universal Peripheral Interfaces
(UPI-41A)

The iSBC 569 Intelligent Digital Controller utilizes a
triple bus architecture concept. An internal bus is
used for on-board memory and I/O operations. A
MULTIBUS interface is available to provide access
for all external memory and I/O operations. A dual
port bus with controller enables access via the third
bus to 2K bytes of static RAM from either the onboard CPU or a system master. Hence, common
data may be stored in on-board memory and may be
accessed either by the on-board CPU or by system
masters. A block diagram of the iSBC 569 functional
components is shown in Figure 1.

The iSBC 569 Intelligent Digital Controller board provides three sockets for user supplied Intel 8041 AI
8741 A Universal Peripheral Interface (UPI-41 A)
chips. Sockets are also provided for the associated
line drivers and terminators for the UPI I/O ports.
The UPI-41 A processor is a single chip microcomputer containing a CPU, 1K byte of ROM (8041 A) or
EPROM (8741 A), 64K bytes of RAM, 16 programmable I/O lines, and an 8-bit timer/event counter.
Special interface registers included in the chip allow
the UPI-41A processor to function as a slave processor to the iSBC 569 controller board's 8085A
CPU. The UPI processor allows the user to specify
algorithms for controlling peripherals directly thereby
freeing the 8085A for other system functions. For
additional information, including UPI-41A instructions, refer to the UPI-41 User's Manual (Manual No.
9800504).

RAM Capacity

Programmable Timers

The iSBC 569 board contains 2K bytes of read/write
memory using Intel 2114 static RAMs. RAM accesses may occur from either the iSBC 569 controller or
from any other bus master interfaced via the MULTIBUS system bus. The iSBC 569 board provides addressing jumpers to allow the on-board RAM
to reside within a one megabyte address space
when accessed via the system bus. In addition, a
switch is provided which allows the user to reserve a
1K byte segment of on-board RAM for use by the
8085A CPU. This reserved RAM space is not accessible via the system bus and does not occupy any
system address space.

The iSBC 569 Intelligent Digital Controller board provides three independently programmable interval
timer/counters utilizing one Intel 8253 Programmable Interval Timer (PIT). The Intel 8253 PIT provides
three 16-bit BCD or binary interval timer/counters.
Each timer may be used to provide a time reference
for each UPITM processor or for a group of UPI processors. The output of each timer also connects to
the 8259A Programmable Interrupt Controller (PIC)
providing the capability. of timed interrupts. All gate
inputs, clock inputs, and timer outputs of the 8253
PIT are available at the I/O ports for external access.

Bus Structure

Timer Functions-In utilizing the iSBC 569 controller, the systems designer simply configures, via software, each timer to meet systems requirements. The
8253 PIT modes are listed in Table 1. The contents
of each counter may be read at any time during system operation with simple read operations for event
counting applications. The contents of each counter
can be read "on-the-fly" for time stamping events or
time clock referenced program initiations.

EPROM/ROM Capacity
Two sockets for up to 16K bytes of nonvolatile read
only memory are provided on the iSBC 569 board.
Nonvolatile memory may be added in 1K byte increments up to a maXimum of 2K bytes using Intel 2758
erasable and· electrically reprogrammable ROMs

7-7

inter

iSBC® 569 CONTROLLER

8259A Interrupts-The eight interrupt sources originate from both on-board controller functions and
the system bus:

Table 1 8253 Programmable Timer Functions
Function
Interrupt on
Terminal Count
Programmable,
One-Shot

Operation
When terminal count is reached,
an interrupt request is generated.

UPI-41A Processors-One interrupt from each of
three UPI processor sockets.

Output goes low upon receipt of
an external trigger edge or
software command and returns
high when terminal count is
reached. This function is
retriggerable.

8253 PIT-One interrupt from each of three outputs.
MULTIBUS System Bus-one of eight MULTIBUS
interrupt lines may be jumpered to either of two
8259A PIC interrupt inputs.

Rate
Generator

Divide by N counter. The output
will go low for one input clock
cycle, and the period from one
low-going pulse to the next is N
times the input clock period.'
Square-Wave
Output will remain high until oneRate Generator half the count has been
, completed, and go low for the
other half of the count.

Software
Triggered
Strobe

Hardware
Triggered
Strobe
Event Counter

Programmable Reset-The iSBC 569 Intelligent
Digital Controller board has a programmable output
latch used to control on-board functions. Three of
the outputs are connected to separate UPI-41A RESET inputs. Thus, the user can reset any or all of the
UPI-41A processors under software control. A fourth
latch output may be used to generate an interrupt
request onto the MULTIBUS interrupt lines. A fifth
latch output is connected to a light-emitting diode
which may be used for diagnostic purposes.

Output remains high until
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.
Output goes low for one clock
period N counts after rising edge
on counter trigger input. The
counter is retriggerable.

Expansion Capabilities
When, the iSBC569 controller is used as a single
board digital controller, memory and'l/O capacity
may be expanded using Intel MULTIBUS compatible
expansion boards. In this mode, no other bus masters may be in the system. Memory may be expanded to a 64K byte capacity by adding user specified
combinations of RAM boards, EPROM boards, or
combination boards. Input/output capacity may be
increased by adding liD expansion boards. Multiple
iSBC 569 boards may be, included in an expanded
system using one iSBC 569 Intelligent Digital Controller as the, system master and additional controllers as intelligent slaves.

On a jumper selectable basis, the
clock input becomes an input
from the external system. CPU
may read the number of events
occurring after the counting
"window" has been enabled or
an interrupt may be generated
after N counts occur in the
system.

Intelligent Slave Programming

Interrupt Capability

When used as an intelligent slave, the iSBC controller appears as an additional RAM memory module.
System bus masters communicate with the iSBC
569 boards as if it were just an extension of system
memory. To simplify this communication, the user
has been given some specific tools:

. The iSBC 569 Intelligent Digital Controller provides
interrupt service for up to 12 interrupt sources. Any
of the 12 sources may interrupt the on-board processor. Four interrupt levels are handled directly by
the SOS5A CPU and eight levels are serviced from
an Intel 8259A Programmable Interrupt Controller
(PIC) routing an interrupt request output to the INTR
input of the 8085A.

Flag Interrupt-The Flag Interrupt is generated any
time a write command is performed by an off-board
CPU to the first location of iSBC 569 RAM. This interrupt provides a means for the master CPU to notify the iSBC 569 controller that it wished to establish
a communications sequence. The flag interrupt is
cleared when the on-board processor reads the first
location of its RAM. In systems with more than one
intelligent slave, the flag interrupt provides a unique

808SA Interrupt-Each of four direct 8085A interrupt inputs has a unique vector memory address. An
8085A jump instruction at each of these addresses
then provides software linkage to interrupt service
routines located independently anywhere in the
memory.

7-8

inter

iSBC® 569 CONTROLLER

interrupt to each slave outside the normal MULTIBUS interrupt lines (INTOf-INT7 f).

I/O Capacity
Parallel-Timers-Three timers, with independent
gate input, clock input, and timer output user-accessible. Clock inputs can be strapped to an external
source or to an on-board 1.3824 MHz reference.
Each timer is connected to a 8259A Programmable
Interrupt Controller and may also be optionally connected to UPI processors.

RAM-The on-board 2K byte RAM area that is accessible to both an off-board CPU and the on-board
8085A may be configured for system access on any
2K boundary.

MULTIBUS® Interrupts-The third tool to improve
system operation as an intelligent slave is access to
the MULTIBUS interrupt lines. The iSBC 569 controller can both respond to interrupt signals from an offboard CPU, and generate an interrupt to the offboard CPU via the system bus.

UPI-lfO-Three UPI-41 A interfaces, each with two
8-bit 110 ports plus the two UPI Test Inputs. The 8bit ports are user-configurable (as inputs or outputs)
in groups of four.

System Development Capability

Serial-1 TTL compatible serial channel utilizing SID
and SOD lines of on-board 8085A CPU.

Software development for the iSBC 569 Intelligent
Digital Controller board is supported by the Intellec®
Microcomputer Development System including a
resident macroassembler, text editor, system monitor, a linker, object code locator, and Library Manager. In addition, both PLIM AND FORTRAN language
programs can be compiled to run on the iSBC 569
board. A unique incircuit emulator (ICE-85™) option
provides the capability of developing and debugging
software directly on the iSBC 569 board. This greatly
simplifies the design,. development, and debug of
iSBC 569 system software.

On-Board Addressing
All communications to the UPI-41A processors, to
the programmable reset latch, to the timers, and to
the interrupt controller are via read and write commands from the on-board 8085A CPU.

Memory Addressing
On-board ROMfEPROM-0-07FF (using 2758
EPROMs); O-OFFF (using 2716 EPROMs or 2316
ROMs); 0-1FFF (using 2732 EPROMs); 0-3FFF (using the 2364 ROMs)

SPECIFICATIONS

On-board RAM-8000-87FF System access-any
2K increment 00000-FF800 (switch selection); 1 K
bytes may be disabled from bus access by switch
selection.

8085ACPU
Word Size:

8, 16 or 24 bits

Cycle Time: 1.30 J.Ls ± 0.1 % for fastest executable
instruction; i.e., four clock cycles.
Clock Rate: 3.07 MHz ± 0.1 %

I/O Addressing

System Access Time
Dual port memory-725 ns

Memory Capacity

Source

Addresses

8253
UPIO
UPI1
UPI2
PROGRAMMABLE RESET
8259A

OEOH-OE3H
OE4H-OE5H
OE6H-OE7H
OE8H-OE9H
OEAH-OEBH
OECH-OEDH

On-board ROM/EPROM-2K, 4K, 8K, or 16K bytes
of user installed ROM or EPROM.

Timer Specifications

On-board RAM-2K bytes of static RAM. Fully accessible from on-board 8085A. Separately addressable from system bus.

Input Frequencies-jumper selectable reference
Internal: 1.3824 MHz ±0.1% (0.723 J.Ls,
nominal)
External: User supplied (2 MHz maximum)

Off-board expansion-up to 64K bytes of EPROMI
ROM or RAM capacity.

7-9

inter

iSBC® 569 CONTROLLER

Line Drivers and Terminators

Output. Frequencies (at 1 3824 MHz)
Function

Min 1

Max 1

Real-time
interrupt interval

1.45 JA-sec 47.4 msec

Rate Generator
(frequency)

21.09 Hz 691.2 KHz

I/O /Drivers-The following line drivers are all compatible with the I/O driver sockets on the iSBC 569
Intelligent Digital Controller.

1. Single 16-bit binary count

Interfaces
MULTIBUSTM Interface-All signals compatible with
iSBC and MULTIBUS architecture
Parallel I/O-All signals TTL compatible
Interrupt Requests-All TTL compatible

Driver

Characteristics

Sink Current (mA)

7438
7437
7432
7426
7409
7408
7403
7400

I,OC
I
Ni
I,OC
NI,OC
NI
I,OC
I

48
48
16
16
16
16
16
16

NOTE:

Timer-All signals TTL compatible

inverting; NI

non-inverting; OC

open collector.

I/O Terminators-: 2200/3300 divider or 1 k.o. pullup (DIP) - user supplied

Serial I/O-All signals TTL compatible

220U

+5V------";----,

Connectors
Pins Centers
(qty) (In.)

Interface
Bus

0.156

Parallel I/O

0.1

Mating Connectors
Viking 3KH43/9AMK12

k~.'

1 kll + 5V - - - - - - - - " V V \ . , - - - , , - - - - - , - (

280232-3

3M 3415-000 or
TIH312125

Environmental Characteristics
Physical Characteristics
Width:
Depth:

Operating Temperature: 0° C to 55° C (32° F to 131°F)
Relative Humidity: To 90% without condensation

30.48 cm(12.00 inches)
17.15 cm (6.75 inches)

Thickness: 1.27 cm (0.50 inch)
Weight:

Reference Manual

3.97 gm (14 ounces)

502180":"" iSBC 569 Intelligent Digital Controller
Board Hardware Reference Manual (NOT
SUPPLIED)

Electrical Characteristics
DC Power Requirements-+ 5V @ 2.58A with no
optional devices installed. For each 8741 A add 135
mA. For each 220/330 resistor network, add 60 mA.
Add the following for each EPROM/ROM installed. '
Type
2758,
2716
2316E
,2732
2364

Reference manuals are shipped with each product
only if designated SUPPLIED (see above). Manuals
may be ordered from any Intel sales representative,
distributor office or from Intel Literature Department,
3065 Bowers Avenue, Santa Clara, California 95051.

+ 5.0V Current Requirement
1ROM

,2ROM

100mA
iOOmA
120mA
40mA
40mA

12,5 mA
125mA
240mA
. 55mA
55mA

ORDERING INFORMATION
Part Number
SBC 569

,7-10

[)escrlptlon
Intelligent Digital Controller

MULTIBUS®I
System Packaging and
Power Supplies

iSBC® 604/614
MODULAR CARDCAGE ASSEMBLIES
•

Interconnects and Houses up to Four
MULTIBUS® Boards per Card cage

•

Card cage Mounting Holes Facilitate
Interconnection of Units

•

Connectors Allow Interconnection of
up to Four Cardcage Assemblies for 16
Board Systems

•

Compatible with 3.5-lnch RETMA Rack
Mount Increments

•

Strong Cardcage Structure Helps
Protect Installed Boards from Warping
and Physical Damage

Interleaved Grounds on Backplane
Minimize Noise and Crosstalk

II Up to 3 CPU Boards per System for

Multiprocessing Applications

The iSBC 604 and iSBC 614 Modular Cardcage Assemblies units provide low-cost, off-the-shelf housing for
OEM products using two or more MULTIBUS boards. Each unit inerconnects and houses up to four boards.
The base unit, the iSBC 604 Cardcage Assembly, contains a male backplane PC edge connector and bus
signal termination circuits, plus power supply connectors. It is suitable for applications requiring a single unit, or
may be interconnected with up to three iSBC 614 cardcage assemblies for a four cardcage (16 board) system.
The iSBC 614 contains both male and female backplane connectors, and may be interconnected with iSBC
604/614 units. Both units are identical, with the exception of the bus signal terminator feature. A single unit
may be packaged in a 3.5 inch RETMA rack enclosure, and two interconnected units may be packaged in a 7
inch enclosure. The units are mountable in any of three planes.

280205-1

8-1

September 1986
Order Number: 280205-001

inter

iSBC® 604/614 CARDCAGES

660 . . . 1...._ - - - 1 2 8 7 5 - - - -.~. 1

-188 DIA, THRU. 3 HOLES

120 DIA x .50 DEEP. 8 HOLES

-I

-r
5500

q.50

t-:~==e~~~~
I

lSac- 814 ONLY

285

Isac<> 614 ONLY

_8500_
300 ... _

2.750

END VIEW

SIDE VIEW

1...- - - - - 1 4 2 0 - - - - . . ;..~,
/

ISBC6140NLV

+
+

3,340

t
3!>....

lSaC'_ONLY

13500-----t~~

I~DIA.X'60DEEP
4 HOLES

280205-2

BOTTOM VIEW

Figure 1.ISSC® 604/614 Cardcage Assembly Dimensions

SPECIFICATIONS·

Mating Power Connectors

Backplane

AMP

Sus Lines-Ali MULTIBUS system bus address,
data, and command bus lines are bussed to all four
connectors on the printed' circuit backplane
Power Connectors-G. for ground, + 5,
+12V, -12V, and -10V power supply lines

Molex
- 5,

Connector

87159·7

87023·1

Polarizing Key

87116·2

Connector

09·50·7071

08·50·0106

Polarizing Key

15·04·0219

NOTE:
1. Pins from a given vendor may only be used with connec·
tors from the same vendor.

iSSC 604-Bus signal terminators, backplane male
PC edge connector only, and power supply headers
iSSC 614-Backplane male and female connectors
and power supply headers

8·2·

inter

iSBC® 604/614 CARDCAGES

ORDERING INFORMATION

Environmental Characteristics

Part Number Description
SSC 604
Modular Card cage Assembly (Sase
Unit)

Operating Temperature: O'C to 55'C

Reference Manual

Sus Arbitration: Serial; up to 3 CPU masters
Equipment Supplied: iSSC 604 or iSSC 614
Card cage Schematic

9800708-iSBC 604/614 Card cage Hardware Reference Manuai (ORDER SEPARATELY)

Physical Dimensions

SSC 614

Part Number Description
Modular Card cage Assembly (Expansion Unit)

Height: 8.5 in. (21.59 cm)
Width: 14.2 in. (36.07 cm)
Depth: 3.34 in. (8.48 cm)
Weight: 35 oz. (992.23 gm)
Card Slot Spacing: 0.6 in,

8-3

iSBC® 608/618
CARDCAGES

•
•
•
•

Houses Eight MULTIBUS® iSBC®
Boards in an Aluminum Package
Board-to-Board Clearance for iSBC®
MULTIMODULETM Boards on All Slots
Board-to-Board Clearance for iSBXTM
MULTIMODULETM Boards on Two Slots
Parallel Priority Circuitry for up to Eight
Multimaster iSBC® Boards

Enhanced Bus Noise Immunity for High
Speed Systems
Plug on iSBC 618 Unit for up to Sixteen
Board Systems
NEMA-Type Backwall or 19-1nch Rack
Mount Hardware Included
Signal Line Termination Circuitry on
iSBC® 608 Cardcage

Intel's iSBC 608/618 Cardcages are matched to the latest generation of iSBC/iSBX boards which mount in
the MULTIBUS system bus. These products provide several features which make them the industry's leading
price/performance card cage product. MULTIMODULE board clearance, parallel priority circuitry, enhanced
backplane noise immunity, and precision fit card guides are a few of the distinctions which make this the
industry's better product.
The iSBC 608 Cardcage is the base unit, housing up to eight iSBC boards and their MULTIMODULE boards.
Additionally, this base unit includes mounting hardware and fan mounting bracketry. The iSBC 618 is the
expansion unit, providing eight additional iSBC board slots to the iSBC 608 Cardcage for a total of sixteen
board slots which can be NEMA-type backwall or 19-inch rack mounted. This is accomplished with the mounting hardware of the iSBC 608 Cardcage. The iSBC 618 expansion unit also includes fan mounting bracketry.

210373-1

8-4

November 1986
Order Number: 210373-001

iSBC® 608/618 CARDCAGES

connections. There are six different priority schemes
allowed, each requiring a different jumper configuration. In systems where an iSBC 618 Cardcage is attached to the base unit, the base unit will have lower
priority overall. That is, master boards in the
iSBC 608 base unit bay gain control of the
MULTIBUS lines only when no boards in the
iSBC 618 expansion unit are asserting the bus request (BREQ/) signal.

FUNCTIONAL DESCRIPTION

Mechanical Aspects
The iSBC 608/618 Cardcages provide housing and
a MULTIBUS system bus for up to sixteen single
board computers and their MULTIMODULE boards.
The iSBC 608 unit and iSBC 618 unit offer board-toboard clearance (0.8 inches or greater) on all eight
slots for iSBC MULTIMODULE boards. Two slots
provide clearance (1.2 inches or greater) for iSBX
MULTIMODULE boards as shown in Figure 1. Each
cardcage includes precision fitted nylon cardguides
for secure board fit and accurate MULTIBUS board
pin alignment. Fan mounting bracketry is also included with each cardcage. This bracketry allows the
mounting of several industry standard fans. The
iSBC 608 Cardcage base unit includes aluminum
mounting hardware for NEMA-type backwall mounting, or anchoring a sixteen slot iSBC 608/618 combination in a standard 19-inch rack.

Noise-minimizing ground traces are strategically interleaved between Signal and address lines on these
backplanes. This provides the enhanced noise immunity and minimized signal-to-signal coupling
which is important in high speed, high board count
microcomputer systems.
The iSBC 608/618 Cardcages provide power connector lug bolts for + 5 VDC and ground. The lug
bolts, compared to other power connection methods, help transfer higher amounts of current. Oth~r
voltages (± 12 VDC, - 5 VDC) are connected via a
mating power connector plug as shown in Figure 2.

Electrical Aspects
The iSBC 608/618 Cardcages implement a parallel
priority resolution scheme by using plug-in jumper

Isax'· MULTIMODULE'·
BOARD SPACING

l·,,·----J

IF-"
/
e
. . . .. ..................,..................... °

JIG POWER
PLUG
.
'-

I"" •• ' •••••• · .......... u

~ Jl
'

. . . . . . . . . . . , ••

HYDC

TERM::~ ~: ;~;~;;;;;;~~~;~~;;~~~~;;~;:~~;;~;~~~~;~~~~; :
TERMINAL

.... 'i ..................................~~.

°
°@

~ :;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;1:;: ::
........................................
.....
,.............................. ···ji.
J7

~ :·::::::=_:::::::~:::::I\: \

Isa~

0
0

t°'-------'

°
C:2:

o @

I ::::::::::::::::::::::::::::::::::::::::::: I

I-----7.00·-----~1

o @

E-'lF

MULTIMODULE'·
BOARD SPACING

210373-2

Figure 1. iSBC® 608/618 Cardcages Dimensions

8-5

ISBC® 608/618 CARDCAGES

Environmental Characteristics

SPECIFICATIONS

Operating Temperature: O°C to 55°C

Bus Lines
All MULTIBUS (IEEE 796) system bus address and
command lines are bussed to each of the eight
MULTIBUS connectors on the backplane. Ground
traces are interleaved among these signal lines and
bussed to the backplane edge connector for inter. connection of the iSBC 608 and iSBC 618 back. plane.

Storage Temperature:
Humidity: .

-40°C to + 85°C
50% to 95% non-condensing at 25°C to 40°C.

Vibration and Shock:

2G max. through 50 Hz

Physical Characteristics
SLOT-TO-SLOT DIMENSIONS (See Figure 1)

Power Connectors

Top-J1:
J1-J2:

Ground (OV), + 5V, - 5V, + 12V, -12V power supply header stakes and power lug bolts are provided
on the iSBC 608/618 Cardcages as shown in Figure

1.200 in. (to center)
1.300 in. (center to center)

J8-Bottom: 0.700 in. (to center)
All Others: 0.800 (center to center)

Physical Dimensions
Height:

8.38 in: (21.29 cm)

Length:

13.16 in. (33.43 cm)

7.50 in. (19.05 cm)
Width:
3.50 Ibs (1.59 kg)
Weight:
Shipping Weight: 5.75 Ibs (2.61 kg)

Equipment Supplied
iSBC® 608 BASE UNIT
Eight Slots:

Two at greater than 1.2
inches; six at 0.8 inches

Male Backplane
Connector:

For expansion with iSBC
618 cardcage

Parallel Priority Circuitry: Eight slots are configurable via the use of jumper
stakes.
Six
priority
schemes allowed

210373-3

Figure 2. Power Header Stakes and Lugs

Construction Materials:

Aluminum card housing
Nylon card guides
Power connector header
stakes and lug bolts

8-6

inter

iSBC® 608/618 CARDCAGES

Accessories

User-Supplied Equipment

ISBC® 618 EXPANSION UNIT
Eight-Slots:
Two at greater than 1.2
inches; six at 0.8 inches
Female Backplane
For expansion to iSBC
Connector:
608 base unit
Parallel Priority Circuitry: Eight slots are configurable via the use of jumper
Six
priority
stakes.
schemes allowed.
Construction Materials:
Aluminum card housing
Nylon card guides
Power connector header
stakes and lug bolts
Fan Mounting Hardware
Schematic

MATING POWER CONNECTORS
Vendor Part Number

3M
Ansley
Berg

3399-6026
609-2600M
65485-009

MOUNTABLE FANS
Vendor Part Number

Rotron
SU2A 1-028267
Torin
TA300-A304 73-10
Pamotor 85060

8-7

inter

iSBC® 661
SYSTEM CHASSIS

•
•

UL, FCC and CSA Approved for Data
Processing Equipment

•

230 Watt Power Supply with Power Fail
Warning

•

Designed for Slide Rack Mounting or
Table-Top Use

•

Eight-Slot MULTIBUS® Chassis with
Parallel Priority Circuitry

Extra-Wide Cardcage Slot Spacing for
iSBXTM MULTIMODULETM Board
Clearance

for Front or Rear Access
• Configurable
to MULTIBUS® Circuit Boards
Five Connector Ports for I/O Cabling
• Operational
from 47 Hz to 63 Hz,

•

100/120/220/240 VAC ± 10%

The iSBC 661 System Chassis is an advanced MULTIBUS (IEEE) 796 chassis which incorporates unique
usability and service features not found on competitive products. This chassis is designed or rack~mount or
table-top. applications and reliably operates up to an ambient temperature of 50°C. Additionally, this sytem
chassis is certified by UL, CSA and FCC for data processing equipment.
An application requiring multiprocessing will find this eight-slot MULTIBUS chassis particularly well suited to its
needs. Parallel priority bus arbitration circuiry has been integrated into the backplane. This permits a bus
master to reside in each slot. Extra-wide inter-slot spacing on the card cage allows the use of plug-on MULTIMODULE boards without blocking adjacent slots. For this reason, the iSBC 661 System Chassis provides the
slot-functionality of most 16-slot chassis. Standard logic recognizes a system AC power failure and generates
a TTL signal for use in powerdown control. Additionally, current limiting and over-voltage protection are
provided at all outputs.

210866-1

8-8

October 1986
Order Number: 210866-002

intJ

iSBC® 661 CHASSIS

FUNCTIONAL DESCRIPTION

under User Supplied Options. Rubber feet are included on the chassis for convenient table-top use.

Mechanical Features

The chassis is constructed of burnished aluminum
which has been coated with corrosion-resistant
chromate. It contains a system control module which
presents the front panel control switches to the user,
and holds the 1/0 cabling bulkhead to the rear. The
chassis has the unique feature of being configurable
for either front or rear access to MULTIBUS circuit
boards.

The iSBC 661 System Chassis houses, cools, powers, and interconnects up to eight iSSC single board
computers and their MULTIMODULE boards for the
MULTIBUS System Bus. Based on Intel's iSBC 608
Card cage, the chassis provides 0.8 inches of board
center-to-center clearance on six slots, and 1.2
inches or more of center-to-center clearance on
two slots. This permits the users of standard MULTIMODULE boards and custom wire-wrap boards to
plug into the MULTISUS System Bus without blocking adjacent slots. All slots provide enough clearance for iSBC MULTIMODULE boards, and two
slots can accommodate iSBX MULTIMODULE
boards.

This is accomplished by a simple procedure involving removal of the system control module, reversing
it end-for-end, and re-securing it to the chassis. The
system chassis is shipped in a configuration such
that the MULTIBUS boards are installed from the
front.

Electrical Features

High-technology MULTIBUS applications requIring
rack-mount, or laboratory table-top use will find the
iSBC 661 System Chassis ideal. Standard 19" slidrack mounting is possible with user-provided slides
attached to the side panels. Slide mounting holes
are provided in the chassis for the slide-rails listed

The iSBC 661 System Chassis is powered by the
iSSC 640 power supply. This is a standard Intel power supply which has been adopted by several
MULTIBUS vendors throughout the industry. It sup-

r------,
I
1
1L _ _ _ _ _ ---l1
I
I

POWER SUPPLY
AREA

FAN

1
L

19"

r------,
1
1
I

EIGHT·SLOT
CAROCAGE

L _____

1
1
1

I
FAN

---l

1
To.5"

TOP VIEW

0.5"~r---

~~_.,J 1 urn5
." 0
~ ~~~'2K.OUTS

8.72~

1~r--

_ _ _ _ _inIeI
__

/-. - - - - ' 6 . 9 5 "

-----1-.1 TI 0.625"

........--_ _ _ _ _ _ _......

BACKPANEL

FRONT VIEW

1"'1·----'9"-----01
SIDE VIEW

210866-2

Figure 1. iSBC® 661 System Chassis Dimensions

8-9

inter

iSBC® 661 CHASSIS

Operational Humidity-1O % to 85% relative, noncondensing
Remote Sensing-Provided for + 5 VCD
Output Transient Response-50 tJ-s or less for
± 50% load change

plies 230 watts of power, power fail warning, and
remote sensing of + 5 volts. Its electrical and operational parameters are listed under Specifications.
The card cage of the iSBC 661 System Chassis implements a user-changeable parallel priority bus arbitration scheme by using plug-in jumper connections. Six different priority schemes are allowed,
each scheme fixing the priority to the eight MULTIBUS board slots. Bus contention among eight busmasters in a multiprocessing environment can be
managed using this approach.

Physical Characteristics
Width: 16.95 inches (43.05 cm)
Height: 8.72 inches (22.2 cm)
Depth: 19.00 inches (48.3 cm)
Weight: 41 pounds (21 kg)
Shipping Weight (approx.): 50 pounds (25 Kg)

Noise minimizing ground traces are strategically interleaved between Signal and address lines on the
system bus. This provides the enhanced noise immunity and minimized signal-to-signal coupling
which is particularly important in high speed, high
board count. microcomputer systems.

Equipment Supplied
iSBC® 661-1-Eight-slot MULTIBUS system chassis
with parallel priority arbitration circuitry and 230 watt
linear power supply

SPECIFICATIONS
Electrical Parameters

Reference Manual

OUTPUT POWER

(Not included: order separately)

Table 1. Output Power Levels iSBC® 661-1
Voltage

Output
Current
(max.)

Current
Limits
(amps)

Over-Voltage
Protection

+12V
+5V
-5V
-12V

4.5A
30.0A
1.75A
1.75A

4.7-6.8
31.5-45.0
1.8-3.2
1.8-3.2

15V ±1V
6.2V ±O.4V
-6.2V ±O.4V
-15V +1V

145340-001-iSBC 661 System Chassis Hardware
Reference Manual

User Supplied Options
Compatible Rack-Mount Slides-Chassis Trak, Inc.,
P. O. Box 39100, Indianapolis, IN 46239; Part No.
C300 S 122

Operational Parameters

ORDERING INFORMATION

Input AC Voltage-100/120/220/240 VAC ± 10%
(User selects via external switch), 47-63 Hz
Power-Fail Indication and Hold-Up Time (triggered at
'90% of VAC in)-TTL O.C. High 3 msec. (min,)

Part Number Description
Eight-slot MULTIBUS system chasSBC6611
sis with parallel priority arbitration circuitry and 230 watt Linear Power
Supply

Output Ripple and Noise-1 % Peak-to-Peak output
nominal (DC to 0.5 MHz)
Operational Temperature-O°C to 50°C
Storage Temperature--40°C to 70°C

8-10

Sl'P34. £ARD £AGE MODULE

A 16-SLO'l' MIlL'I'IBIlS@1 CARD CAGE MODIlLE FOR FLEXIBLE,
EXPANDABLE SYS'I'EMS CONFIGIlRA'I'IONS
Intel's SYP341 Card Cage i~ a standard module designed w provide, along with the companion
SYP342 Peripheral Module, a basic platform for the integration of large capacity systems. Intel's
modular packaging scheme allows for integration into standard 19 inch rack·mount cabinets or
NEMMypc enclosures.

FEA'I'IlRES
• 16·slot MULTIBUS I backplane with
integrated priority and interrupt circuitry.
• Accepts standard 7 x 12 inch MULTIBUS I
boards and up W seven 10 x 12 inch boards.
• Meets EIA, 19 inch rack standard.
• 4·layer backplane construction. Interleaved
bus signal traces. Dedicated power and
ground layers.
• 24·bit addressing supported on all slots.
• Extended gold pins for all P2 signals.
Supports iLBX bus cables.
• Backplane generated bus clock.
• MULTIBUS reset and interrupt switches with
power·on and status indicators.
• 750 watt multiple output switching power
supply. Switch selectable 110/220 VAC.
• Forced air cooling. Provides 300 Ifm across
boards.

__ r_________________~S_Y_P3_4_1_a_nd_S_Y_P_34_2_m_o_u_nt_ed
__
in
, '''ell
typical 19·inch rack·mount cabinet.
l.rwt
In\.('1 u)tporallUfl aSSUffil'S no l\'!'po.lIlslhllll) for the' uS(' It

imp1i{'(i. InlOrmallun ronlCllflC'd hrrrlfl

~upersrdrs

an~

mru.Lr) llthrr than tir(,Ullry

l'mh~)dit'd

pr('\lously puhllshed spt'flriraLums un thl'~

dc~jQ's

in an Intel prllduct. No uthl'r mruil

p8t.('.nlli(l'l1~~'i

arc

rmm lnt.cl and is subjt:rl Ix) rh.1rlgr. Without notice.

SePlCmhcr. 1988
@lnu'ICorporallon 1988

Order Number: 2A0641·0U2

8-11

SPECIFICATIONS
ENI'IBONMENTALS

WOllYWIDE SERI'ICE AND SfJPPOIlT

Ambient Temperature
Operating
Jlion-Operating
Relative Humidity
Operating
Non-operating
Altitude
Operating
Non-Operating

Intel provides support for Intel and non-Intel boards and
peripherals as well all on-site service. \)ew,lopment support
options Include phone support. subscription service. on-Site
mnsulting. and cllstomer training.

oto 55°C
--10 to BOoC
BO% at -lOoC
95% at 55°C

OIlttUT)' AND RE"'ABIUT),

Sea Level to 10.000 ft't't
Sea Level to 40.000 feet

The SYP341 is designed. t.ested and manuractured in
8cmrdance with Inters industry leading quality and
rrliability standards.

EUCTRICA"
DC Power Output

+5,·

+ 12,·
-12v
AC Power Input

750 watt maximum
100.0:\ maximum
10.0 :\ maximum
10.0 :\ maximum
90-132 \:-\Cor IBO-26-1 \AC
-17-63 Hz

IlEGIJUTIONS
Meets the following safety
US
Canada
Europe

requirements:
L'L-17B 5th Edition remgniZl'i1
GS:\ C22.2 \,jo. 220 rertified
lEe 380 and IEC 950

Power Supply meets the following EMIIRFI requireml'nts:
L'S
FCC Class B Conducted
emissions
Europe
\"DE Limit Class B Conducted
emissions

PH),SICA" CHARACTERIStICS
"'.e.slells
Standard Rear Mount Power Supply
Height
-lBB.1 mm (19.22 in)
Width
4B2.7 mm (19.00 in)
Depth
501.6 mm (19.75 in)
Weight
23.9 kilugrams (5:llbs)
Optional Mounting:
Side Mounted PO\\lhllll~ [II[

Itl.'

ll~'

an~

('IT! Ullr:. olh\'f than ('In'wtry embodied In an Intel prudurl. Nt) IJtht'r mcult patl'nt U(\'n:;cs c

3
"2CD

Parts List
1 PWB Termination Backplane
2 7 Post Wafer Connectors (0.156" Pin Centers) (J6 and J8)
4 Edge Board Connectors, 43/86 Pins on 0.156" Centers (J2-J5)
12 Wire Wrap Posts
410 Pin, 2.2K, 9 RES, 1.5W Resistor Packs (RP1-RP4)
1 10 Pin, 1K, 9 RES, 1.5W Resistor Pack (RP5)
1 10 Pin, 1.1 K, 9 RES, 1.5W Resistor Pack (RP6)
1 1K Resistor, VoW, ±5% (R1)
1 2.2K Resistor, VoW, ±5% (R5)
2 220n Resistors, y.,W, ±5% (R9, R11)
2 330n Resistors, y.,W, ±5% (R10, R12)
2 510n Resistors, VoW, ±5% (R7, R8)

c:
!:j
iii
c:
en@>

~
~
m

i:
m

MUlTIBUS® SYSTEM BUS

Physical Characteristics (Continued)

J2
(A POSSIBLE CONNECTOR CONFIGURATION)

COMPONENT SIDE

P1
85
86

2
SOLDER SIDE

SOLDER SIDE

Figure 6. Connector and Pin Numbering

9-10

280294-7

intJ

MULTIBUS® SYSTEM BUS

PHYSICAL CHARACTERISTICS (Continued)

Iii

005'11-

III

0
Z

Co
a:_

.........
1110

0 ..

.
Q,

...
C

.
i:
~

.LOY.lNOO

'l, -

= '

:!
l!!

-__

IlL

'[~
~

III

iii

...z

...

.
..:II

c~~~r-

0
~

....~

ii:

a_
'~1
__ 'L~

:!
l!!

...
0
0

.......
....
co
III

"'N
.LOY.LNOO

1,--

\.+------------+ -,'-

~-----------5--------------+1~:··1
o

~ ~

Figure 7. Standard Printed Wiring Board Outline

9·11

). .
::
~

MULTIBUS® SYSTEM BUS

Backplane Connectors
Table 4. Connector Vendors
# Of

Pins

Centers
Inches

Multibus
Connector
(Pi)

43/86

0.156

Soldered(1)

Multibus
Connector
(Pi)

43/86

0.156

Wire wrap(1,

Auxiliary
Connector
(P2)

30/60

0.1

Auxiliary
Connector
(P2)

30/60

0.1

Function

Connector
Type

Vendor

Vendor #

Intel #

VIKING
ELFAB

2KH43/9AMK12
BS1562D43PBB

102247-001

ELFAB
ELDAC

BW1562D43PBB
3370860540201

102248-001

ELFAB
EDAC

BW1562A43PBB
337086540202

102273-001 (3)

Soldered(1 )

ELFAB
EDAC

BS1020A30PBB
345060524802

102238-001

Wire wrap(1 , 2)

TI
VIKING

H421121-30
3KH30/9JNK

N/A(3)

EDAC
ELFAB

345060540201
BW1020D30PBB

102241-001

NOTES:
1. Connector heights are not guaranteed to conform to Intel packaging equipment.
2. Wirewrap pin lengths are not guaranteed to conform to Intel packaging equipment.
3. With mounting ears with 0.128 mounting holes.

Environmental Characteristics

Reference Manuals

Operating Temperature: O°C to 60·C; free moving
air across modules and
bus
90% maximum (no conHumidity:
densation)

210883-002- MULTIBUS Architecture Reference
Book

9-12

inter

iLBXTM EXECUTION BUS

•

High Bus Bandwidth
- 9.5 Mbytes/sec. for a-Bit Transfers
-19 Mbytes/sec. for 16-Bit Transfers

•

16 Mbyte Addressing Range

•

a and 16-Bit Data Transfers

• Supports up to 5 iLBXTM Compatible
Devices Per Bus
•

Primary and Secondary Master Bus
Exchange Capabilities

• Standard 60-Pin MULTIBUS® P2
Connector

The iLBXTM Execution Bus is one of a family of standard bus structures resident within Intel's total system
architecture. The Local Bus Extension (iLBX) Bus is a dedicated execution bus capable of significantly increasing system performance by extending the processor board's on-board local bus to off-board resources. This
extension provides for arbitration-free, direct access to high-performance memory. Acting as a "virtual"
iSBC®, up to 16 megabytes of processor addressable memory can be accessed over the iLBX bus and appear
as though it were resident on the processor board. The iLBX Bus preserves advantages in performance and
architecture of on-board memory, while allowing memory configurations larger than possible on a single board
computer. High throughput and independence from MULTIBUS® activities make the iLBX bus an ideal solution
for "working store" type program memory and data processing applications requiring large amounts of high
performance memory. Such applications include graphics systems, robotics, process control, office systems,
and CA~/CAM.

280215-1

9-13

September 1988
Order Number: 280215-001

inter

iLBXTM EXECUTION BUS

FUNCTIONAL DESCRIPTION

Structural Features
The iLBX bus uses a non-multiplexed 16-bit configuration capable of 8 and 16-bit transfers. Used in conjunction with the MULTIBUS interface, the iLBX bus
resides on the MULTIBUS form factor P2 connector
and supercedes the MULTIBUS interface definitions
for the P2 signals. The iLBX bus uses the standard
60-pin MULTIBUS P2 connector and occupies 56 of
the P2 connector pins with 16 data lines, 24 address
lines plus control, command access, and parity signals. The four MULTIBUS address extension lines
on the MULTIBUS/iLBX P2 connector retain the
standard MULTIBUS interface definition.

Architectural Overview
The iLBX bus is an architectural solution for supporting large amounts of high performance memory. It is
the first structure that allows the CPU board selection to be decoupled from the on-board memory requirement, and still maximizes the processor's performance potential. It eliminates the processor's
need to access its off-board memory resources
solely over the MULTIBUS system bus. Architectural
consistency with the single board computer approach including iLBX memory can be maintained by
dual port access of memory resources between the
iLBX bus and the MULTIBUS system bus. This allows for global access by other processors and 1/0
devices while still providing high speed local CPU
operations. This sub-system created by the iLBX bus
of a single board computer and a maximum of 4
memory cards can be perceived architecturally as a
"virtual single board computer". The implementation
of iLBX bus "virtual modules" makes it possible to
create functional modules with a new level of flexibility and performance in implementing a wide range of
memory capabilities. With future needs in mind, the
iLBX bus has the capability of accessing a full 16
megabytes of memory.

Bus Elements
The iLBX bus supports three distinct devicecategories: 1) Primary Master, 2) Secondary Master, 3)
Slave. These three device types may be combined
to create several iLBX local busses ranging (in size)
from a minimum of two to a maximum of five devices
per iLBX bus. There is only one Primary Master in
any given implementation of iLBX bus, and its presence is required along with the attachment of at
least one Slave device. To provide alternate access
over an iLBX bus, one optional Secondary Master

REMOTE CONTROL MODULES

BIT BUS"

280215-2

Figure 1_ MULTIBUS® System Architecture
9-14

inter

iLBXTM EXECUTION BUS

may be incorporated to create a "two-master" local
bus subsystem. By limiting the iLBX bus to two masters (a Primary and a Secondary), bus arbitration is
reduced to a simple request and acknowledge process, with privileged use of the bus maintained by
the Primary Master, and limited access granted to
the Secondary M~ster when needed.

driven by the active bus master. The iLBX bus master uses them to select a specific slave device.
Three control lines specify the type of data transfer
between master and slave devices, while the three
command lines initiate, control, and terminate the
transfer. There are also three bus access lines used
to transfer bus control between master devices.

The Primary Master executes the role of iLBX bus
"supervisor" by controlling the general operation of
the bus and managing Secondary Master accesses
to the Slave memory resources.

Bus Pin Assignments
The iLBX bus uses the standard 60-pin MULTIBUS
P2 connector. The physical location of each pin assignment and its corresponding function is listed in
Table 1. The four MULTIBUS address extension
lines (pins 55-58 on the P2 connector) retain the
standard MULTIBUS interface functions.

The Secondary Master Device is an option providing
alternate access to the Slave resources on the iLBX
bus. Secondary master devices are typically DMA
driven. This feature is provided for implementation
flexibility when occasional DMA transfers in and out
of iLBX memory resources can optimize the overall
system performance. The Secondary Master essentially duplicates the Primary Master's data transfer
capability, but must rely on the Primary Master to
grant access. Once access is granted, the Secondary Master controls the bus, and drives all signal
lines until the operation is complete and control is
passed back to the Primary Master.

Bus Operation Protocol
The operation protocol for the iLBX bus is a straightforward set of procedures consisting of three basic
operations: bus control access, write data to memory, read data from memory. These operations use
asynchronous protocol with positive acknowledgment.

The Slave devices contain the memory resources
used by the Primary Master and the optional Secondary Master. Each iLBX implementation can contain a maximum of four Slave devices. Using 64K
RAM technology on four slave devices with ECC can
provide for over 2 megabytes of "on-board" high
performance memory. With 256K RAM chips, each
iLBX bus could contain slave devices with memory
totalling 8 megabytes. As memory technology increases, the iLBX bus is designed to incorporate it in
rapid fashion because it is capable of directly accessing a full 16 megabytes of memory on its highperformance Slave devices.

Bus Access
The iLBX bus is shared by at most two masters; one
Primary Master and one optional Secondary Master,
each providing an alternate access path to iLBX bus
memory resources. The mechanism for obtaining
bus access is a simple request and acknowledge
process communicated between masters. Each
master is a bus controller of similar capabilities, responsible for data transfer operations between devices, but the Primary Master has the added responsibility of controlling iLBX bus accesses.
The Primary Master has default control of the iLBX
bus. If the Secondary Master needs access to the
bus, it must initiate a request and wait for acknowledgment from the Primary Master. The choice of
when to surrender control of the bus rests with the
Primary Master, but if no data transfer is in progress,
the Primary Master normally relinquishes control immediately to the Secondary Master.

Bus Interface/Signalline Descriptions
The iLBX bus interface is divided into four functional
classes of signal lines: address and data lines, control lines, command lines, and bus access lines. The
40 address and data lines defined by the iLBX Bus
Specification consist of 16 data lines and 24 address
lines.

Data Transfer Operation

There are 16 bi-directional data lines exclusively
used to handle 8-bit. and 16-bit data transfers between the active bus master and the selected slave
device. The iLBX bus uses these data lines for all
data transfers, and are driven by tri-state drivers.

The iLBX bus supports two types of data transfer
operations: write data to memory and read data from
memory. These data transfer operations facilitate
the passing of information between the active bus
master and the selected slave device. The operation
of these two transfer types is very similar; the only
differences being the direction of the data transfer
and the device driving the data lines.

The 24 address lines on the iLBX bus provide the
ability to directly address 16 megabytes of memory.
These single-direction address lines are exclusively
9-15

inter

iLBXTM EXECUTION BUS

The iLBX Bus Specification includes provisions for
both optimized and non-optimized data transfers.
Optimized operation uses pipelining and signal overlapping techniques to manage the data transfer timing relationships between the active bus master and
the selected slave. The use of signal overlapping
requires that every device attached to the iLBX bus
provide a means of varying the timing of the slave
request and acknowledge signals. The non-optimized operation uses fixed signal sequences, instead of signal overlapping, to assure a valid data
transfer, and a device does not need a variable request or acknowledge to read data-valid timing on
the iLBX bus. Please refer to the iLBX Bus Specification for detailed descriptions of these transfer operations.

For either type of data transfer, the active bus master first initiates the transfer operation by placing the
memory address on the address lines (AB23-ABO)
and a control configuration on the control lines to
select the slave device. Once the slave device is
selected, the type of data transfer becomes the key
factor. With the write operation, the active master
maintains control of the data lines and provides valid
data within the specified time. Upon accepting a
data element, the slave sends a receipt acknowledgment signal to the master which completes the data
transfer operation.
With the read operation, the slave device drives the
data lines and places valid data on the data lines
before sampling by thE'l active master. The slave acknowledges the master to signal the end of the data
transfer, and the master completes the operation.

Table 1. iLBXTM Bus Pin Assignments, P2 Edge Connector
Component Side
16·Bit Pin

Mnemonic

Solder Side

Signal Name

16·Bit Pin

Mnemonic

Signal Name

1
3
5
7
9
11
13
15
17

DBO
DB2
DB4
DB6
GND
DB9
DB11
DB13
DB15

Data Line 0
Data Line 2
Data Line 4
Data Line 6
Ground
Data Line 9
Data Line 11
Data Line 13
Data Line 15

2
4
6
8
10
12
14
16
18

DB1
DB3
DB5
DB7
DB8
DB10
DB12
DB14
GND

Data Line 1
Data Line 3
Data Line 5
Data Line 7
Data Line 8
Data Line 10
Data Line 12
Data Line 14
Ground

19
21
23
25
27
29
31
33
35

ABO
AB2
AB4
AB6
GND
AB9
AB11
AB13
AB15

Address
Address
Address
Address
Ground
Address
Address
Address
Address

Line 0
Line 2
Line 4
Line 6
9
11
13
15

20
22
24
26
28
30
32
34
36

AB1
AB3
AB5
AB7
AB8
AB10
AB12
AB14
GND

Address
Address
Address
Address
Address
Address
Address
Address
Ground

Line 1
Line 3
Line 5
Line 7
Line 8
Line 10
Line 12
Line 14

37
39
41
43

AB16
AB18
AB20
AB22

Address
Address
Address
Address

Line 16
Line 18
Line 20
Line 22

38
40
42
44

AB17
AB19
AB21
AB23

Address
Address
Address
Address

Line 17
Line 19
Line 21
Line 23

45
47
49
51

GND
BHEN
ASTB*
SMRQ*

Ground
Byte High Enable
Address Strobe
Secondary
Master Request
Access Lock

46
48
50
52

ACK'
R/IN
DSTB*
SMACK'

GND

Slave Acknowledge
Read Not Write
Data Strobe
Secondary Master
Acknowledge
Ground

MULTIBUS® Address
Extension Line 22
MULTIBUS® Address
Extension Line 20
Reserved

ADR23'

ADR21 *

TPAR*

LOCK'

ADR22*

ADR20*

RES

Line
Line
Line
Line

9-16

MULTIBUS® Address
Extension Line 23
MULTIBUS® Address
Extension Line 21
Transfer Parity

inter

iLBXTM EXECUTION BUS

Mechanical Implementation

SPECIFICATIONS

Because the iLBX bus uses the P2 connector of the
MULTIBUS form factor, the iLBX bus "shares" a
MULTIBUS chassis with the MULTIBUS backplane
system bus in the system design. The iLBX mechanical specifications are synonymous with the MULTIBUS specifications for board-to-board spacing,
board thickness, component lead length, and component height above the board. The iLBX bus interconnection can use either flexible ribbon cable or a
rigid backplane. The iLBX bus interconnect maximum length is limited to 10 cm (approximately 4
inches); that is sufficient to span 5 card slots across
two connected chassis. Figure 2 shows an iLBX bus
cable assembly.

-~-"""

~"","""""'''''."",..-''~
~

Word Size
Data: 8 and 16-bit

Memory Addressing
24-bits-16 megabyte-direct access

Bus Bandwidth
9.5 megabytes/sec: 8-bit
19 megabytes/sec: 16-bit

,~,~--,*"

280215-3

Figure 2. Typical iLBXTM Bus
Interface Cable Assembly

Electrical Characteristics
DC SPECIFICATIONS
Table 2
Signal
Name

Driver
Type

DB1S-0
TPAW
AB23-0
R/IN
BHEN
LOCK*
SMRQ*
SMACK*
"i"ASTB*
tDSTB*
ACK*

TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TRI-STATE
TAl-STATE
TTL
TTL
TRI-STATE
TRI-STATE
Open Coil.

Termination
(to +5 Vdc
At Master
10 K!!
10 K!!
None
None
None
None
10 K!!
None
10 K!!
10 K!!
330 !!

Min Driver Requirements
High
0.6 rnA
0.6 rnA
0.4 rnA
0.2 rnA
0.2 rnA
0.2 rnA
0.05 rnA
O.OSmA
0.2 rnA
0.2 rnA
NA

tAt slave, additional series RC terminatIOn to GND (100

Low
Load Cap.
9mA
7SpF
9mA
7SpF
20 rnA
120 pF
8mA
7SpF
8mA
7SpF
8mA
7S pF
2mA
20pF
2mA
20pF
9mA
75 pF
9mA
7SpF
20 rnA
4S pF
!!, 10 pF) .
9-17

Max Receiver Requirements
High
0.1SmA
0.1S rnA
0.10 rnA
0.05 rnA
O.OSmA
O.OS rnA
O.OS rnA
O.OS rnA
O.OS rnA
O.OSmA
O.OSmA

Low
2mA
2mA
SmA
2mA
2mA
2mA
2mA
2mA
2mA
2mA
2mA

Load Cap.
18 pF
18 pF
30pF
18 pF
18 pF
18 pF
18 pF
18 pF
18 pF
18 pF
18 pF

iLBXTM EXECUTION BUS

BUS TIMING

MULTIBUS'

INIT*~:J

SMACK*

I
I

SMRQ*

--=========::S::3~--f-.-J~======

TRI·STATE
PRIMARY DRIVERS
MASTER _

-----------~==3------

SECONDARY
MASTER
TRI·STATE DRIVERS

280215-4

Figure 3. iLBXTM Bus Granting Timing Chart
16-Blt Transfer Timing
I

AB23 to ABO

I
BHEN

VZZIfl///M
I

R/W

,m,....------t----'wzzzm,....-----+---~XZlL

7":/j7'7"7/TT7/'T"T/Z""'4
I

'k;zmJl7l/VR/7I7I!I/X

YlllllZ

MBII
WINDOW

",-"-

·"1

BASE ADDRESS IS ANY

V·"CT"",O""

ON·
BOARD
DRAM

v_o,""m,", ..

BASE ADDRESS IS ANY
MULTIPLE OF 128K OR 256K

512KB

./'

./
0

/./

0
280263-3

Figure 2. Memory Mapping Diagram

10-21

iSBC® 186/100 MULTIBUS BOARD

programmable timer interrupts. In addition, direct- .
vectored interrupt· capability of the serial communication controller (SCC) may be used. Figure 3 depicts the interrupts in terms of their priorities.
Interrupt Services
80186 Timer 0
8087 -1 Error Interrupt
Message Interrupt
iPSB Bus Error Interrupt
82530 SCC Interrupt
82258 ADMA Interrupt
80186 Slave PIC Interrupt
8259 Slave PIC Interrupt
PPIO Interrupt
iSBX Bus Interrupt 0
iSBX Bus Interrupt 1
Interconnect Space Interrupt
80186 Timer 1 Interrupt
PPI 1 Interrupt
Ground

The Centronics interface requires very little software
overhead since a user supplied PAL device is used
to provide necessary handshake timing. Interrupts
are generated for printer fault conditions and a DMA
request is issued for every character.

Interrupt Priority
Master Level 0
1
2
3
4
5
6
7

SERIAL I/O LINES
The iSBC 186/100 board has one 82530 Serial
Communciations Controller (SCC) to provide 2 channels of serial 110. The SCC generates all baudrate
clocks and provides loopback capability on both
channels. Channel A is configured for RS 422A mUltidrop DTE application. Channel B is RS 232C only
and is configured as DTE.

Slave 0
1
2
3
4
5
6&7

Figure 3. iSBC® 186/10 Interrupt Priority Scheme

PARALLEL/SCSI PERIPHERAL
INTERFACE
The iSBC 186/100 board includes an 8255A parallel
peripheral interface that consists of three 8-bit parallel ports. As shipped, these ports are configured for
general purpose 110. Programmed PAL devices
(Programmable Array Logic) and the bi-directional
octal transceiver 74LS245 are provided to make it
easy to reconfigure the parallel interface to be compatible with the SCSI (Small Computer System Interconnect) peripheral interface. Alternatively, the iSBC
186/100 board provides the jumper configuration facilities for operating the parallel interface as an interrupt driven interface for a Centronics compatible line
printer by adding one PAL and reconfiguring jumpers. Both interfaces may use the 82258 DMA controller for data transfers if desired.
The SCSI interface allows multiple mass storage peripherals such as Winchester disk drives, floppy disk
drives, and tape drives to be connected directly to
the iSBC 186/100 board. A sample SCSI application
is shown in Figure 4. The SCSI interface is compatible with SCSI controllers such as Adaptek 4500,
DTC 1410, Iomega Alpha 10, Shugart 1601 and
1610, Vermont Research 8403, and Xebec 1410.

The multidrop configuration may either full-or halfduplex. A full-duplex multidrop configuration with a
single master driving the output lines allow a slave to
monitor the data line and to perform tasks in parallel
with tasks performed on another slave. However,
only the selected slave may transmit to the master.
A half-duplex multidrop configuration is more strict in
its protocol. Two data lines and a ground line are
required between a master and all slaves in the system and although all units may listen to whomever is
using the data line, the system software protocol
must be designed to allow only one unit to transmit
at any given instant.

BUILT-IN-SELF-TEST DIAGNOSTICS
On-board built-in-self-test (BIST) diagnostics are implemented using the 8751. microcontroller and the
80186. microprocessor. On-board tests include initialization tests on DRAM, EPROM, the 80186 microcontroller, and power-up tests. Additional activities performed include a Reset Operating System
initialization at power-up and a program table check,
a feature allowing users to add custom code in
EPROM while still maintaining full use of the factory
supplied BISTs..
Immediately after power-up and the 8751 microcontroller is intialized, the 80186 microprocessor begins
its own initialization and on-board diagnostics. Upon
successful completion of these activities, the Reset
Operation System invokes the user-defined program
table. A check is made of the program table and the
custom programs that the. user has defined for his
application will then execute sequentially.

10-22

intJ

iSBC® 186/100 MULTIBUS BOARD

•

SCSI BUS

ISBC" 186/100
BOARD

MULTIBUS@ II PARALLEL SYSTEM BUS

280263-4

Figure 4. SCSI Application

BISTs improve the reliability, error reporting, and recovery capability of MULTIBUS II boards. In addition,
these test and diagnostics reduce manufacturing
and maintenance costs for the user. A yellow LED
(labeled 'BIST') on the front panel indicates the
status of the initialization checks and the power-up
tests. It is illuminated if any of the initialization
checks fail and remains off if the board successfully
completes its tests. The LED also illuminates when
the BIST tests start and stays on until the test complete successfully. The results of the BIST diagnostics are stored in the last 6 registers of the Header
Record in Interconnect space.

iSBXTM BUS MULTIMODULETM
EXPANSION
One 8-or 16-bit iSBX bus MULTIMODULE connector
is provided for I/O expansion. The iSBC 186/100
board supports both 8-bit and 16-bit iSBX modules
through this connector. DMA is also supported to
the iSBX connector and can be configured by programming the DMA multiplexor attached to the
82258 DMA component. The iSBX connector on the
iSBC 186/100 board supports a wide variety of standard MULTIMODULE boards available from Intel

and independent hardware vendors. Custom iSBX
bus MULTIMODULE boards designed for MULTIBUS or proprietary bus systems are also supported
as long as the IEEE P959 iSBX bus specification is
followed.
iPSB BUS INTERFACE SILICON

The MPC (message passing coprocessor) provides
all necessary iPSB bus interface logic on a single
chip. Services provided by the MPC include memory
and I/O access to the iPSB by the 80186 processor,
bus arbitration, exception cycle protocols, and transfers as well as full message passing support. Dual
port architecture may be implemented using the
message passing coprocessor.

Interconnect Subsystem
The interconnect subsystem is one of the four MULTIBUS II address spaces, the other three being
memory space, I/O space, and message space. The
purpose of interconnect space is to allow software
to initialize, identify, configure, and diagnose the
boards in a MULTIBUS II system. All Intel MULTIBUS II boards support interconnect space.

10-23

iSBC® 186/100 MULTIBUS BOARD

The interconnect space is organized into a group of
8-bit registers called a template. The interconnect
registers are organized into functional groups called
records. Each register belongs to only one record,
and there are three basic types of interconnect records: a header record, a function record, and an End
of Template (EOT) record. The 80186 on the iSBC
186/100 board accesses its own template via the
interconnect address space on the iPSB bus.
The header record provides board and vendor 10
information, general status and control information,
and diagnostic status and control information. The
function record contains parameters needed to perform specific functions for the board. For example,
an iPSB memory record contains registers that define the start and end address of memory for access
across the iPSB bus. The number of function records in a template is determined by the manufacturer. The EOT record simply indicates the end of the
interconnect template.

Cycle Time
BASIC INSTRUCTION: 8.0 MHz - 500 ns for mini-

mum code read

Memory Capacity
LOCAL MEMORY
NUMBER OF SOCKETS: four 28-pin JEDEC sites
Memory
Capacity

8K
16K
32K
64K

EPROM
EPROM
EPROM
EPROM

x
x
x
x

8
8
8
8

Chip Example

2764
27128
27256
27512

ON-BOARD RAM

There are two types of registers in the MULTIBUS II
interconnect space, read-only and software configurable registers. Read-only registers are used to hold
information such as board type, vendor, firmware
level, etc. Software configurable registers allow read
and write operations under software control and are
used for auto-software configurability and remotel
local diagnostics and testing. A software monitor
can be used to dynamically change bus memory
sizes, disable or enable on-board resources such as
PROM or JEDEC sites, read if the iSBX bus or
PROM are installed as well as access the results of
Built-In-Self-Tests or user installed diagnostics.
Many of the interconnect registers on the iSBC
186/100 board perform functions traditionally done
by jumper stakes. Interconnect space support is implemented with the 8751 microcontroller and iPSB
bus interface logic.

512K bytes 64K

4 bit Dynamic RAM

110 Capability
Serial:
- Two programmable channels using one 82530
Serial Communications Controller
- 19.2K baud rate maximum in full duplex in asynchronous mode or 1 megabit per second in full
duplex in synchronous mode
- Channel A: RS 422A with DTE multidrop capabil. ity
-

Channel B: RS'232C compatible, configured as
DTE
Parallel: SCSI, Centronics, or general purpose

110
Expansion: One 8-or 16-bit IEEE P959 iSBX
MULTIMODULE board connector supporting
DMA

SPECIFICATIONS
Word Size

Serial Communications Characteristics

INSTRUCTION: 8-, 16-, 24-, 32-, or 40-bits
DATA: 8-or 16-bits

ASYNCHRONOUS MODES:

• 19.2K baud rate maximum in full duplex
• 5-8,bit character; odd, even, or parity; 1, 1.5, or 2
stops bits

System Clock
CPU: 8.0 MHz
NUMERIC COPROCESSOR: 8.0 MHz (part number

8087-1)

10-24

• Independent transmit and receive clocks,1X,
16X, 32X, or 64X programmable sampling rate
• Error detection: Framing, Overrun, and Parity
• Break detection and generation

inter

iSBC® 186/100 MULTIBUS BOARD

BIT SYNCHRONOUS MODES:
• 1 megabit per second maximum in full duplex

iSBX BUS:

As per IEEE P959 specification

• SOLC/HOLC flag generation and recognition
• Automatic zero bit insertion and detection
• Automatic CRC generation and detection (CRC
16 or CCITI)
• Abort generation and detection

CONNECTORS
Location
P1

Function
iPSB Bus

Part #
603-2-IEC-C096-F

• I-field residue handling

Physical Dimensions

• SOLC loop mode operation
• CCITT X.25 compatible

The iSBC 186/100 board meets all MULTIBUS II
mechanical specifications as presented in the MULTIBUS II specification (# 146077)

BYTE SYNCHRONOUS MODES:
• Internal or external character synchronization (1
or 2 characters)

DOUBLE-HIGH EUROCARD FORM FACTOR:

• Automatic CRC generation and checking (CRC
16 or CCITI)

Depth:

220 mm (8.7 in.)

233 mm (9.2 in.)
Height:
Front Panel Width: 20 mm(0.784 in.)
Weight:
743 g (26 oz.)

• IBM Bisync compatible

Timers
Three programmable timers on the 80186 microprocessor

Environmental Requirements

INPUT FREQUENCIES:

Temperature: Inlet air at 200 LFM airflow over all
boards
Non-operating: - 40° to + 70°C

Frequencies supplied by the internal 80186 16 MHz
crystal
Serial chips:

crystal driver at 9.8304 MHz divide
by two

Humidity:

iSBX connector: 9.8304 crystal driven an 9.8304
MHz

Operating: 0° to + 55°C
Non-operating: 95% RH @55°C, noncondensing
Operating: 90% RH @ 55°C, non-condensing

Electrical Characteristics

Interrupt Capacity

The maximum power required per voltage is shown
below. These numbers do not include the power required by the optional memory devices, SCSI PALs,
or expansion modules.

POTENTIAL INTERRUPT SOURCES:

255 individual and 1 broadcast
INTERRUPT LEVELS:

12 vectored requests using two 8259As, 3 grounded
inputs, and 1 input to the master PIC from the slave
PIC
INTERRUPT REQUESTS:

All signals TIL compatible INTERFACES
IPSB BUS:

As per MULTIBUS II bus architecture specification
10-25

Voltage
(Volts)

Max Current
(Amps)

Max Power
(Watts)

+5
+12
-12

6.5mA
50mA
50mA

34.13W
0.06W
0.06W

ISBC@ 186/100 MULTIBUS BOARD

Reference Manuals

ORDERING INFORMATION

iSBC 186/100 Single Board Computer User's Guide
(#148732·001)

SBC186100

Part Number Description

Intel MULTIBUS II Bus Architecture Specification
(#146077)
Manuals may be ordered from any Sales Represent·
ative, Distribution Office, or from the Intel Literature
Department,3065 Bowers Avenue, Santa Clara, CA,
95051.

10·26

MULTIBUSII 80186·based Single
Board Computer

THE MUtTIBUS®1I P(; SUBSYSTEM

PC/AT- COMPATIBILITY COMES TO MIlLf'lBIlS" SYSTEMS
The Intel MULTIBUS II PC Subsystem combines the power of the 386'" micfoprocessor, t1ll'lnulti'
processing capabilities of the MULTIBUS II architecture and the large base of DOS compatible
software into a high performance IBM PC/AT compatible two board set. Wlwn used with a standard
PC/AT compatible keyboard and YGA compatible monitor this subsystem provides an ('xl'dlcnt
foundation for a human interface with color graphics IiiI' MlJl:rIBUS II systems. Running off·the·shelf
software packages it is suitable for data acquisition or prOfess monitoring applications, and can he
e,asily eustomizcd using a variety of available PC compatihle products.

FEATIlRES
CPU BOARD
• Fully IBM PC/AT compatible subsystem
running a 16 \lh7. 386 32-bit CPU.
° Includes socket for Intel 80387 Of Wcitek
numeric co-processor chip, 64 K of high
speed SRAM caclie, 2 serial ports, I parallel
port, keyboard and floppy drive cOnLroliers.
° Completely MliLTlIlLIS II syst.ems
architecture compatible including ADMA,
MPC and 8751 interconnect conLrolier.

PERIPHERAL C,oMP-\NION BOARD

° ST-:;06/sT-412 cornpalihl(' liard Disk
°
°

Controller
YGA graphics contl'ollel', \\ith VGA, eGA,
f:<;A, and mono-graphic:; soft\\HI\'
compatihility
Built-in CS~I funclionalit\

r______________________

O.rrt
__
I I"e"

A_d_d spt'rlflcalions on,these de~'ices frum Inld and IS ~uhJI·rt tn rhan~' "'llhmt nlllite.
September, 1988
Intel Corporation 1998
(Jrd~r Number: 280673-001

10-27

FEATURES
P.tRT OF 'l'HE IfIIJL'l'IBIJS~" F.tIflILI'
Now PGlAT compatibility has come to a MULTI BUS II CPU.
The MULTIBUS II Parallel System Bus is the bus of choice
for Real Time multiprocessing. Its advanced bus architecture
Includes such features as a high speed (32 Mbyteslsec)
Parallel Systems Bus (PSB) with message passing and bus
parity detection. virtual interrupts. simplified systems
configuration through interconnect space. and extensive
power·up testing. Now our MULTIBUS II family is even more
complete with DOS complementing iRMX~. iRMK"'. and
UNIX· operating systems. and bringing with it a complete
human interface including keyboard controller and VGA
graphics.

3B61f1UJIlOPIlO€ESSOll SPEED .tND
PEIlFOllIfI.tNCE
The iSBC 386JPC16 CPU board features a 386'" CPU
running at 16 Mhz and 64 K'of 0 wait state (read hit) cache
memory for 32-bit speed and performance. PerFormance can
be t-'Yen further enhanced by adding an Intel 80387 or
Weitek math co:processor In the provided socket.
As much as 16 M-byte of DRAM can be provided on·board
using memory expanSion modules. Third party software
allows this memory to be used as extended or expanded
memory per tbe LotusllntellMicrosoFt Expanded Memory
SJIOCmcation. For filII IBM PGlAT software compatibility the
ISBC 386IPC16 comes with an Award BIOS and runs either
PC-DOS* or MS-DOS*. As a 386'" microprocessor-based PC
platForm. UNIX V/386 can also be easily ported to this
board.

FllU COIfIPLEIfIEN'l' OF PC
PEIlIPHEIlALS
To minimize the need For add-in cards. the iSBC 386IPC16
CPU board includes 2 serial ports. I Centronics compatible
parallel port. keyboard controller. and noppy disk controller.

The iSBC PCSYSIIOO Peripheral Companion Board adds to
that a hard disk controller. and a VGA graphics controller
which is softwarc compatible with EGA. CGA. and Hercules*
monochrome graphics modes. In addition. it provides builtin MULTIBUS II Central Services Module Functionality.

IN'l'EGIl.tTES E.tSILI' IN'l'O .t
IfIllLTlBllS " SI'S'l'EIfl
The ISBC 386JPC16 CPU board was designed to integrate
easily into a MULl'IBUS II system. Hardware support
includes the MULTI BUS II Message Passing Co-processor
(MPC). 8751 Interconnect space controller. and 82258
ADMA controller to provide full message passing support. It
can ·also access global memory and UO on the Parallel
Systems Bus.
Conforming to the MULl'IBUS II Systems Architecture (MSA).
the SBC 3861PC16 includes firmware support for BISTs
(Built-In Self Tests). lOX (Initialization and Diagnostics
eXecutive). and DOS MULTIBUS II Transport Protocol. A
DOS Transport Gall Library. provided on a noppy disk.
allows user implementation of communlr,atlon and data
sharing with other MULTIBUS II CPUs and peripherals.

B.tCIl.PL.tNES .tND .4IJ.tP'l'Oll BO.4IlD
Rounding out the complement of products in the Intel
MULTIBUS II PC Subsystem family are 2 and 4 slot
backplanes for the P2/aPC bus (the PC bus brought out on
the MliLTlBlIS II P2 connector) and an Adaptor Board.
Intended for development purposes. the iSBC PCSYS/900
Adaptor Board plugs into a MULTI BUS II card cage or
chassiS and accommodates either four "half size" PClXT"
add·on cards or two "half size" PC/XI' and either two PC/AT
"full size" or two Pc/XT ,"full size" add-on boards.

HIG" IlEU.4B1U'l'1'
Intel has deSigned the MULTIBLIS II PC Subsystem for high
reliability. Extensive lise of CMOS circuitry keeps the boards
running cooler. and since excess heat can cause premature
failure. running longer. DIN pin and socket connectors
ensure reliable connectivity with the backplane, and parity
error checking In the DRAM circuitry and on the Parallel
Systems Bus improves overall system integrity. Furthermore
the boards conform to Intel's strict design and
manufacturing standards.

"'OIlLD ""DE SEIlJ'ICE .4ND SllPPOllI'
Should this or any Intel board ever need service. Intel
maintains a world wide network of servioe and repair
facilities to keep you and your customers up and running. In
addition. should you need system level design support, our
international Systems Engineering organization is available
. to integrate Intel boards and systems components into your
products.

·UNIX is a trademark of AT & T
·PC-OOS and PClXT are trademarks of Inwrnational Business Machines
.MS-OOS is a trademark of Microsoft
·Hercules is a trademark of Hercules (',omputcr Technology. Inc.

10-28

SPt:~IFICATIOIllS

Multillu..

PC ...

a038&'PC CORE

Multlbullllnl.rlaca

f"'Fe .: iSBC 386/PC16 Functional Block Diagram

_"
PC I ..
(',24BITAIlOReSS.'OBITDATA.CONTAOL

fl".Fe 2: iSBC PCSYSflOO Functional Block Diagram
.XT1\aIf11z.-or
2 XT"haII size" and
olher2XTorAT

·'ull stze- add-on

boa""

...

~~
Board

Ancohor
IUJbus II

Ancoher
_oil

Board

fI"aFe:l: MULTlBlISl!>lIl'C Subsystem Block Diagram

10·29

SPECIFIl:t\TIONS
r:llaPC BtlfJ"r£tlNES.
SBfJ ftJSYSI60:l tlND SBfJ rfJSYSI604

crlJ BOARD-SBC 3B61PC'6
CPU
386 microprocessor running at 16Mhz

• Available In 2 and 4 slot versions

DRAM Memory

tlDtlPmR BOtiRD-SBfJ PCSYSI900

32·bit parity protected memory:

Model
SBC 386PC16 MOl
SBC 386PC16 M02
SBC 386PC16 M04
SBC 386PC16 M08

Supplies
1 Mb
2 Mb
4 Mb
8 Mb

• Accommodates either four '·half size" PClXT add·on cards
or two "half size·' PClXT and either two "full size" PClAT
or two PClXT "full size" add~m boards
• Adaptor board is 3 MULTIBUS II card slots wide

ENI'IRONMENTII£ RE(}fJIREItlENTS

Note: Moriel suffix(~s M02 and MOB requilY' two MI II,TIBI IS
II card slol..~. Model suffixes MOl and M04 require only one
Mli/,T/BUS 1/ card slat.

Storage Temperature:
Operating Temperature:

- 40° to 70°C ( 0° to 158°F)
OOC to 55°C (320 to 131°F)

Storage Humidity:

Memory expansion modules-ont' may be added to bast'
models above

Operating Humidity:

5%·95% non·condensing at
55°C
8%·90% non·condensing at
55°C

Model
SBC MM01
SBC MM02
SBC MM04
SBr. MM08

Supplies
1 Mb
2 Mb
4 Mil
8 Mb

SRAMC8che
Capacity: 64K
Speed:
0 wait state on read hit
2 walt states on write
3 wait states on read miss
EPROM Memory
Two 32·pin JEDEC sites containing 256 K or EPROM
memory with Award BIOS and MSA firmware.

ORDERING INFORMIITION
SBC386PC16MOI

386·based PC compatible CPU board
with 1 Mb of DRAM
SBC386PC 16M02 386·based PC compatible CPU board
with 2 Mb of DRAM
SBC386PC 16M04 386·based PC compatible CPU board
with 4 Mb of DRAM
SBC386PC 16M08 386·based PC compatible CPU board
with 8 Mb of DRAM
SBCPCSYS100

Companion board with VGA graphics.
HD controller and·CSM functionality

S301K3

101·key enhanced AT·style keyboard

SBCPCSYS602

2·slot Backplane for the P2/aPr. bus

Two additional 32·pin .IEDEC Sites provided for user
EPROM or EEPROM memory. r.ircuitry is provided to write
as well as read EEPROM memory.

SBCPCSYS604

4·slot Backplane for the P2/aPC bus

SBCPCSYS900

Adaptor Board

PERIPIIERtI£ COItlrtlNION BOtlRDSBfJ nSYSI'OO

SBC MM01
SBC MM02
SBC MM04
SBC MMOB

1 Mb Memory ExpanSion Module
2 Mb Memory ExpanSion Module
4 Mb 'vlcmory «;xpansion Module
8 Mb \AclIIory ~;xpansion Module

Hard Disk Controller
• PClAT Compatible Winchester Controller
• SupporlS up to two ST·506/ST·412 drives
Graphics
• SupporlS VGA. EGA. CGA. and Hercules Compatible
graphics
• rour text mode resolutions: 40 x 25.80 x 2;'. 132 x 25.
132 x 43
• Three graphics mode resolutions: 640 x 480 with 16
colors. 9aO x 720 with 4 colors. and 1280 x 960
monochrome

CSM
• ASSigns card slot and arbitration IDs at initialization
• Generates system clock for all agents on the PSB
• Provides system wide reset signals for power·up. warm
reset. and power failure
• Detects bus timmuts

10-30

MULTIBUS® II
Memory Expansion Boards

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-n+_r
II 1'eII

iSBC® MM01, MM02, MM04, MM08
HIGH PERFORMANCE MEMORY MODULES

High Speed Parity Memory
• Provides
Expansion for Intel's iSBC 386/2X,

to Provide up to 16M Bytes
• Stackable
of High Speed Memory for MULTIBUS I

iSBC 386/3X and iSBC 386/1XX
CPU Boards

•

in 1M, 2M, 4M, and 8M Byte
• Available
Sizes
• 32 Bits Wide with Byte Parity

and MULTIBUS " CPU Boards
Supports 32-Bit, 16-Bit and 8-Bit Data
Paths

Independent Read/Writes
• Supports
• Easily Insta"ed

The iSBC MM01, iSBC MM02, iSBCMM04, and iSBC MM08 DRAM memory modules are members of Intel's
complete line of iSBC memory and I/O expansion boards. The MM-Series of memory modules use a dedicated interface to maximize CPU/memory performance. The iSBC MM series of memory modules have been
designed to provide both the on-board and expansion memory for the iSBC 386/2X, the iSBC 386/3X and the
iSB,C 386/1XX CPU Boards.
The modules contain (respectively) 1M byte, 2M, 4M, and 8M bytes of read/write memory using surface
mounted DRAM components (see Figure 1).
Due to the high speed interface of the memory modules, they are ideally suited in applications where memory
performance is critical.

Figure 1. iSBC® MM08 Memory Module

11-1

280346-1

September 1988
Order Number: 280346-002

inter

iSBC® MM01, MM02, MM04, MM08 MODULES

FUNCTIONAL DESCRIPTION

Installation

SPECIFICATIONS
Memory Access Capabilities

Word Size Supported

The dynamic RAM memory of the memory modules
. is accessed through the dedicated memory module
interface.

8-, 16-, or 32-bits

Memory Size

The MM memory module is designed for direct
transfer of data between the CPU and the memory
module without accessing. the MULTIBUS interface.

iSBC
iSBC
iSBC
iSBC

MM01/MM02/MM04/MM08
Memory Size

The MMxx-series memory modules use a 32-bitwide
data path with storage for byte parity that can accommodate 8-bit byte, 16-bit or 32-bit word data
transfers. In addition, the data path is capable of
independent byte operations. This means that one
byte can be written while the other three bytes (or
any other combination) can be read.

1,048,576
2,097,152
4,194,304
8,388,608

bytes
bytes
bytes
bytes

Access Time (All Densities)

The iSBC MM01, iSBC MM02, iSBC MM04, and
iSBC MM08 modules can be stacked on the CPU
baseboard in any combination.

Data Bus Structure

MM01
MM02
MM04
MM08

Read/Write -

107 ns (max)

The MMxx-series memory modules run with the
iSBC 386/2X and iSBC 386/116 Boards at 16 MHz,
and with the iSBC 386/3X and iSBC 386/120
Boards at 20 MHz. Wait state performance informationwith each of these CPU baseboards is contained in the Hardware Reference Manual for the
specific CPU baseboard.

Cycle Time (All Densities)
Read/Write -

200 ns (min)

Parity
Power Requirements

One parity bit is provided for each of the four, 8-bit
bytes in the 32-bit wide data path. For special applications, the parity bits can serve as data bits making
possible 9-, 18-, or 36-bit data transfers.

Voltage -5 VDC ±5%
Memory addressing for the iSBC MMxx memory
modules is controlled by the host CPU board over
the memory module interface. The maximum system
RAM size is 16M Bytes.

Memory Function
The module protocol supports standard dynamic
RAM READ, WRITE, RAS' only REFRESH cycles,
and CAS' before RAS' REFRESH.

11-2

infef

iSBC® MM01, MM02, MM04, MM08 MODULES

ISBC@MMxx
MEMORY MODULE

4.25"
7.05"

CPU BASEBOARD

CONNECTOR
OUTLINE

.. - - - - - - - 1

I&. _ _ _ _ _ _ _

4.175"

280346-2

Side View
iSBC® MMxx
MEMORY MODULE

/STANDOFF

0.847"
(:1:0.023)

CPU BASEBOARD
280346-3

Single iSBC® MMxx Memory Module

Side View
ISBC® MMxx
MEMORY MODULES
STIFFENER

1.564"

0.525 INCH STACKING CONNECTOR

(:I: 0.033)

~STANDOFFS

0.625 INCH BASEBOARD CONNECTOR

CPU BASEBOARD
280346-4

Stacked iSBC® MMxx Memory Modules

11-3

iSBC® MM01, MM02, MM04, MM08 MODULES

Environmental Requirements

ORDERING INFORMATION

Operating Temperature -

Part Number

O°C to 60°C

Description

iSBCMM01

1M Byte RAM Memory Module

iSBCMM02

2M Byte RAM Memory Module

Cooling Requirement - 3 cubic feet per minute of
airflow at an ambient temperature of O°C to 60°C

iSBCMM04

4M Byte RAM Memory Module

iSBCMM08

8M Byte RAM Memory Module

Operating Humidity without condensation

The Memory Modules ship with the required· hardware (connectors, mounting screws, stand-offs, etc.)
to stack a second module on the module already
mounted on the base CPU board.

Storage Temperature -

40°C to

+ 75°C

To 95% relative humidity

Physical Dimensions
Module Alone:
Width -

4.250 inches (10,795 cm)

Length -

4.175 inches (10,604 cm)

Height -

0.500 inches (1,270 cm)

Weight -

iSB9 MM01 IMM04: 2.5 ounces (70.0 gm)
iSBC MM02/MM08: 3.5 ounces (11 0.0 gm)

11-4

iSBC® MEM/312, 310, 320, 340
CACHE-BASED MULTIBUS® II RAM BOARDS

•

iSBC® MEM/3XX MULTIBUS® II
Memory Boards Are High-Speed CacheBased Boards with 8K Bytes of Cache
RAM

•
•

32-bit MULTIBUS® II Parallel System
Bus (iPSB) and Local Bus Extension II
(iLBXTM II Bus) Interface Support

•

Eurocard Standard Form
• Double-high
Factor, Pin and Socket DIN Connectors
MULTIBUS II Software Interconnect
• Support
for Dynamic Memory
Configuration and Diagnostics with No
Jumpers Necessary on the Board

•
•
•

Zero Wait State Over iLBXTM on a
Cache Hit, One Wait State for Cache
Misses and Writes at 8 MHz
Dual Port Memory with Four Versions
Available:
iSBC MEM/312
%M Byte
1M Byte
iSBC MEM/310
iSBC MEM/320
2M Bytes
iSBC MEM/340
4M Bytes

Built-In-Self-Test (BIST) Diagnostics
On-Board with Both LED Indicators and
Software Access to Error Information
Automatic Memory Initialization at
Power-Up and at Power-Fail Recovery
Byte Parity Error Detection

The iSBC MEM/312, 310, 320, 340 cache-based memory boards are the first Intel memory products to
implement the MULTIBUS II system architecture. They have 32-bit architecture throughout, supporting 8-, 16-,
and 32-bit central processors. The iSBC MEM/3XX (generally refers to this family of boards) memory boards
are dual-ported, with access to the interfaces of both the MULTIBUS II Parallel System Bus (iPSB bus) and the
iLBX II (Local Bus Extension):
In addition to the 32-bit memory transfer, the iSBC MEM/3XX high-speed cache control subsystem, standard
on these boards, improves performance by allowing zero wait state read access over the iLBX II when data
requested is in the cache memory.

280071-1

11-5

October 1988
Order Number: 280071-002

inter

ISBC® MEM/312, 310, 320, 340 BOARDS

reduces read access timers. The 8K Bytes of 45
nsec SRAM allows zero wait state read accesses
over the iLBX II bus when data requested is in the
cache memory (cache hit). A cache hit takes only
two iLBX II bus clocks (250 nsec at 8 MHz).

FUNCTIONAL DESCRIPTION

General
The iSBC MEM/312, 310, 320, 340 high-speed
cache-based memory boards are physically and
electrically compatible with the MULTIBUS II iPSB
bus standard and the new iLBX II bus (Local Bus
Extension) as outlined in the Intel MULTIBUS II
specification. Figure 1 illustrates a. typical multiprocessing MULTIBUS II system configuraton.

Each entry in the 8K Byte cache memory subsystem
consists of a data field of 32-bits and a tag field of up
to 9-bits (depending on board DRAM size). Each
byte in the main memory DRAM array directly maps
to one and only one entry on the cache array. This
direct mapped cache array along with tag labels ensure data integrity and accurate identification of
cache hits. The cache memory size and simple but
effective replacement algorithm is designed to optimizeboth the probability of cache hits and the CPU
bus utilization. On any miss or write access, the contents of one cache entry are updated to maintain
consistency with the corresponding entry in the
DRAM memory array.

Architecture
The four main subsystems of the iSBC MEM/3XX
boards are the cache controller subsystem, the
cache memory subsystem, the DRAM memory subsystem, and the interconnect space subsystem (see
Figure 2). The following sections describe these
subsystems and their capabilities in more detail.

Dual Port DRAM Capabilities
Cache Memory Capabilities

The iSBC MEM/312 module contains 112M Byte of
read/write memory using 64K dynamic RAM compo-

The cache memory system is designed around the
32-bit architecture of the main memory system and
BlrBUS··

280071-2

Figure 1. Typical MULTIBUS® II System Configuration

CACHE

CONTROLLER
SUBSYSTEM

280071-3

Figure 2. iSBC® MEM/3XX Board Block Diagram
11-6

inter

iSBC® MEM/312, 310, 320, 340 BOARDS

nents. The iSBC MEM/310, MEM/320 and
MEM/340 modules respectively contain 1M Byte,
2M Bytes and 4M Bytes of read/write memory using
256K dynamic RAM components.

1. EPROM Checksum:
This test-performs a checksum test on its internal
EPROM to check operation of the 8751 microcontroller.

The dual port capability of the iSBC MEM/3XX
boards allows 32-bit access from either the iPSB
bus interface or the iLBX II bus interface (see Figure
1). Due to the simple arbitration nature of the iLBX II
bus interface and the cache memory subsystem, the
iSBC MEM/3XX family allows optimal access to
. 20M Bytes of DRAM on the iLBX II bus.

2. Cache Data Test:
The microcontroller performs a sliding ones test
on the cache memory in hit-only mode.
, 3. Cache Address Test:
This test verifies that the cache address path is
working properly.
4. Refresh Check:
This test performs RAM test on a small portion of
DRAM with an elapsed time between the write
operation and the verification of the data.

System Memory Size
Using this series of memory boards the maximum
system memory capacity based on one CPU board
and 19 memory boards is 76M Bytes on the iPSB
bus. The' memory partitioning is independent for the
iPSB bus interface and the iLBX II bus interface.

5. Dynamic RAM Address Test:
This test performs Address Rippled RAM test on
the board memory (MISS ONLY operation mode).
6. Dynamic RAM Data Test:
This test runs an AA-55 data pattern to check the
DRAM data path.

The start address can be on any 64K Byte boundary
on the iPSB bus and any 64K Byte boundary on the
iLBX II bus. Software configures the start and ending
addresses through the interconnect space. No jumpers are needed.

7. Parity Test:
This test injects parity errors in the DRAM array
and then verifies that the board detects these
errors.

Interconnect Space Capabilities

These tests are described in detail' in the User's
Manual, Section 9-23.

The iSBC MEM/3XX board module has a set of interconnect registers which allow the, system software to dynamically configure and test the status of
the memory board, replacing hardwired jumper functions. This interconnect subsystem also provides
control and access to the Built-In-Self-Test (BIST)
features. During power-up reset, the iSSC
MEM/3XX board initializes the memory and cache,
sets all interconnect registers to their default values
and performs a self-test. Error information from both
Built-In-Self-Test (SIST) and parity checking is indicated in front panel LEOs and recorded in interconnect space registers accessible to software.

Memory Initialization and Reset
Memory is initialized automatically during power-up.
All bytes are set to 00.

Error Detection Using Byte Parity
Parity will detect all single bit parity errors on a byte
parity basis and many muiltiple bit errors. LED 2 (labelled Parity) is used to indicate parity errors. LED 2
is turned on when a parity error is detected and
turned off when the parity status register within interconnect space is cleared. This same LED turns on
and off during power-up to verify operatoin' of the
LED.

Built-In-Self-Test (BIST)
Self-test/diagnostics have been built into the heart
of the MULTIBUS II system. These confidence tests
and diagnostics improve reliability and reduce manufacturing and maintenance costs. LED 1 (labelled
BIST) is used to indicate the status of the Built-In
Self Test. It is turned on when the BIST starts running and'is turned off when the BIST completes successfully. The Built-In-Self-Test performed by the
on-board microcontroller at power-up or at software
command are:

Error information is recorded in interconnect space
so it is accessible to software for errorreporting.

11-7

inter

iSBC® MEM/312, 310, 320, 340 BOARDS

ENVIRONMENTAL REQUIREMENTS

SPECIFICATIONS

Temperature: (inlet air) at 200 LFM airflow ,over
boards
Non-Operating: - 40 to + 70°C
Operating: 0 to + 55°C
Humidity:
Non-operating: 95% RH @ 55°C
Operating: 90% RH @ 55°C

Word Size Supported
8-, 16-, 24-, and 32-bits

Memory Size
% Megabyt~ (iSBC MEM/312) board
1 Megabyte (iSBC MEM/310) board
2 Megabytes (iSBC MEM/320) board
4 Megabytes (iSBC MEM/340) board

Physical Dimensions
The iSBC MEM/3XX boards meet all MULTIBUS II
mechanical specifications as presented in the
MULTIBUS II specification (# 146077).

Access Times (All Densities)

Double High Eurocard Form Factor:

MULTIBUS II Parallel System Bus-iPSB (@
10 MHz)

Depth: 220 mm (8.6 in.)
Height: 233 mm (9.2 in.)
Front Panel Width: 20 mm (0.784 in.)

Read: 562 ns (avg.)
775 ns (max.)

Weight:

Write: 662 ns (avg.)
775 ns (max.)

iSBC
iSBC
iSBC
iSBC

NOTE:
Average access times assume 80% cache hit rates
iLBXTM II Bus-Local Bus Extension

MEM/312
MEM/310
MEM/320
MEM/340

board: 6720
board: 6160
board: 6720
board: 10080

gm
gm
gm
gm

(24
(22
(24
(36

oz.)
oz.)
oz.)
oz.)

Reference Manuals

Read: 250 ns (min.)
275 ns (avg.)
375 ns (max.)

iSBC MEM/3XX Board Manual (#146707-001)

Write: 375 ns (avg.)
375 ns (max.)

Manuals may be ordered from any Intel Sales Representative, Distributor Office, or from the Intel literature Department. 3065 Bowers Ave., Santa Clara,
CA 95051.

Base Address

Ordering Information

iPSB Bus-any64K Bytes boundary
iLBX II Bus-any 64K Bytes boundary

Part Number
iSBC MEM/312

Description

Power Requirements

iSBC MEM/310

1M Byte Cache Based
MULTIBUS II RAM Board

iSBC MEM/320

2M Byte Cache Based
, MULTIBUS II RAM Board

iSBC MEM/340

4M Byte Cache Based
MULTIBUS II RAM Board

Voltage: 5V DC

± 5%

Product
iSBC MEM/312
Board
iSBC MEM/310
Board
iSBC MEM/320
Board
iSBC MEM/340
Board

Current
3.5 A (typ)
6.0A (max)
3.5 A (typ)
6.0 A (max)

3.5 A (typ)
6.0A(max)
4.1 A (typ)
6.7 A (max)
11-8

%M Byte Cache Based
MULTIBUS II RAM Board

MULTIBUS® II
Peripheral Controllers

ISB£® 386/2 S8 PERIPHERAL £ONTROLLER

MIJIII'IBIJS@1I CONTROLLER FOR HIGH-PERFORMANCE, SCSI
PERIPHERALS
The iSBC 386/258 is a high-performance peripheral controller that provides a unique combination of
powerful 110 performance and access to SCSI peripherals for MULTIBUS II applications_
Minicomputer-level I/O performance is achieved by utilizing the 386'" microprocessor and a large
data cache. The added power of the 386 processor gives the iSBC 386/258 the potential to off-load
tasks from other system crus as an 110 server. The SCSI standard has achieved wide acceptance
because of its extensive capabilities and excellent performance_

FEATIJRES
• 16 MHz 386 microprocessor
• 1 or 4 Mbyte data buffer
• Common Command Set (CeS) SCSI
peripheral support
• Asynchronous SCSI up to 1.5 Mbytes per
second. Synchronous SCSI up to 4.0 Mbytes
per second
• Single-ended or differential SCSI options
• 8/l6-bit iSBX'" interface connector
• RS232 serial port
• On-board self-test diagnostics

intel·------------:IBn is a Irar1rmarK of Inlt'l f.orporatlfm
Inlt'l Corporation assumrs nn I'('sponsihllily for lhl" use 0( any nrruilr) Ilther than cirruitry embodied In an Inr.cl product No other circuit pal.enl hcenscs arc
irnpllrd. Infnrmallon rnntaiJ'lt'd ht>rt'in suprrsrdrs prniously publishrd s~'('Jflralilms (In these dC\lircs from Im.cl and Is subject \.0 change wlthuut notice
September. 1988
@

Order Number: 2B0670'()()1

Inti'l O1rpllTillinn 19M

12-1

FEATIJRES
COMPLETE SCSI CAPABll.ITI'
The iSBC 386/258 supports communication with up to se\en
, other host/peripheral adapters and up to ,56 possible
devices. Vendor-unique features of peripherals can be
accessed using the pass through capability. ,-\Iso supported
is the ability to be a bus initiator andlor a bus target. and
the use of disconnect/reconnect. This extensi\e SCSI support
allows the iSBC 386/258 to be used in applications such as
high·speed data transfer between systems.
Peripherals that support the SCSI standard include magnetic
hard disk. magnetic tape. noppy disk drhe. opt ical disk. and
Iinl' printers.

HIGH PERFORMANCE
1/0 critical applications are accelerated by the combination
of a 16 Mhz 386 processor. a large data buffer for cacheing.
and the 4.0 Mbytcs per second synchronous transferrate
for SCSI.

WORLDWIDE SERVICE AND SIJProRT
Intel provides support for board repair or on-site service.
Development support options include phone support.
subscription service. on·site consulting. and customer
tmining ..

t)IJAl.ITI' AND REl.IABll.ITI' TESTING
The iSBC 385/258 is designed and manufactured in
accordance with Inters high quality standards. We then
verify quality through rigorous testing in our state·of-the art
EnVironmental Test Laboratory.

SPE~IFI~ATIONS

INTERFACES

ORDERING INFORMATION

ML'LTIBUS II: 32-bit Parallel System Bus (IEEE 1296)
Interface with Full ~lessage Passing Capability
SCSI: .-\\SI X3.131 . 1986
iSBX Bus Interface: compliance level DI6/16 D~I.\ for single·
ended version. compliance level D16116 for differential
version
Serial liO Port: RS·232·C (subset) interface (DTE). 9·pin
D·shell shielded connector. Configurable baud ralrs: 300.
600. 1200.2400.4800.9600 and 19200

Part Number
SBC 386 258S MO I

DEJ'ICE DRIVERS

SBC 386 258S M04
SBC 386 258D M04

for more information or the number of your nearest Intel
sales office. rail 800·548·4725 (good in the U.S. and
Canaua).

Check the latest release of the follo\\ing operating systems
for details:
iR\IX II
UNIX* System \/386

PHI'SICAL CHARACTERISTICS
Height: 9.18 in. (233.2 mm)
Depth: 8.65 in. (220 mm)
Front Panel \\iuth: 0.76 in. (19.2 mm)

roWER REt)IJIREMENTS
Typical: + 5\' @ 111\
± 12 V @ 0.50\
Does not include power for installed iSH X MlILTI\10DlILE
boards

ENVIRONMENTAL REt)IJIREitfENTS
Operating Temperature: 0 to 55 C @ 200 LFM
Non-operating: - 40 to 70 C
Humidity: 0 to 85% non-condensing

REFERENCE MANlJAl.
iSBC 386/258 SCSI Peripheral Controller User's Guide
'V\IX is a re~istrrrd

trademar~

Description
Single·ended SCSI Peripheral
Controller with 1 Mbyte
Single-ended SCSI Peripheral
Controller with 4 Mbyte
Differential SCSI Peripheral
Controller with 4 Mbyte

of :\T&T.

12-2

iSBC® 186/224A
MULTIBUS® II
MULTI-PERIPHERAL CONTROLLER SUBSYSTEM
Subsystem for Mass
• Complete
Storage Devices

128K Bytes of On-Board DRAM Allows
• Multiple
Track Caching for High Speed

1/0

•

Based on the 80186 Microprocessor

•

Controls up to Four ST506/412
Winchester Disk Drives, up to Four
SA450/460 Floppy Drives, and up to
Four QIC-02 Streaming Tape Drives

Winchester Data Access

•
•
•

On-Board Firmware Provides
• Concurrency
of Operation

MPC (Message Passing Coprocessor)
Single Chip Interface to the Parallel
System Bus With, Full Message Passing
Software Configurability: Geographic
Addressing
Built-In-Self-Test (BIST) Diagnostics
On-Board

The iSBC 186/224A Multi-Peripheral Controller Subsystem supports the full Message Passing protocol of the
MULTIBUS \I System Architecture and provides peripheral I/O control for a wide variety of OEM applications.
The iSBC 186/224A controller serves as a complete peripheral I/O subsystem and supports the predominant
types of storage media: Winchester disks, floppy disks, and quarter-inch streaming tapes. On-board firmware
for the board provides improved Winchester disk operation through multiple data track caching. This subsystem capability is provided on a single 8.7 x 9.2 inch double-high Eurocard form factor printed circuit board.

280713-1

12-3

December 1987
Order Number: 280713-003

inter

iSBC® 186/224A MULTI-PERIPHERAL CONTROLLER SUBSYSTEM·

The I/O Transfer bus supports data transfers between the iSBC 186/224A controller and the various
peripheral devices. The Winchester, floppy, and tape
interfaces reside on the I/O Transfer bus as do the
DMA controller and track cache DRAM.

ARCHITECTURE
Dual-Bus Architecture On-Board
The iSBC 186/224A controller is designed around a
dual bus structure and is supported by real-time,
multitasking firmware. The dual bus structure consists of the local bus and the -I/O transfer bus. This
dual-bus approach offers maximum task concurrency-allowing the 80186 CPU to execute code and/
or manipulate data during data transfers to and from
the various storage media.

The 8237 A-5 DMA controller directly controls four
independent DMA channels and provides thecapability for performing time-multiplexed, concurrent
data transfer operations between the respective device interfaces and the local DRAM.
A total of 128K bytes of zero wait state DRAM is
provided on-board. This DRAM is local to the I/O
Transfer bus. It is accessible to both the CPU and
the DMA controller. It supports the 80186 stack and
interrupt vectors and 64K bytes of Winchester track
caChe. The DRAM is configured for 16-bit (word) access and also supports byte-swapping.

The iSBC 186/224A controller uses the MULTIBUS
II Parallel System Bus (iPSB) to transfer commands
and data to requesting and sending agents via solicited and unsolicited messages as specified in the
MULTIBUS II Bus Architecture Specification Handbook. (See Figure 1 for functional block diagram of
the 186/224A board).

This dual-bus architecture combined with the realtime control firmware and peripheral command protocol allows the concurrent transfer of data between
multiple storage devices and the controller and between the controller and the MULTIBUS·II Parallel
System Bus resulting in improved system level performance.

The local bus consists of the 80186 microprocessor,
the EPROM, MPC (for access to the iPSB), and interrupt control. The 80186 component controls the
local bus and manages the interface between the
iPSB and the controller. DMA channels internal to
the 80186 are used for data transfers between onboard memory and the MPC.

TO IPsa

280713-2

Figure 1. iSBC® 186/24A Board Block Diagram

12-4

inter

iSBC® 186/224A MULTI-PERIPHERAL CONTROLLER SUBSYSTEM

Winchester Connections: One 50-pin D-type, right
angle female, high density connector which provides
all of the required signals for up top four Winchester
disk drives.

Interconnect Space Subsystem
MULTIBUS II Interconnect Space is a standardized
set of software configurable registers designed to
hold and control board configuration information as
well as system and board level diagnostics and testing information. Interconnect space is implemented
with the 8751 microcontroller and the MPC bus interface silicon.

Flexible Disk Connections: One 25-pin D-type connection which provides all of the required signals for
up to four daisy-chained flexible disk drives.
QIC-02 Streaming Tape Connections: One 25 pin
D-type connection which provides the required signals for up to four daisy-chained tape drives.

The read-only registers store information such as,
board type, vendor 1.0., firmware revision level, etc.
The software configurable registers are used for
controller options, identifying certain device characteristics, and diagnostics.

I/O Connectors: The I/O connections for each interface are on the front panel. In order to provide a
reliable connection to the peripheral devices, additional ground lines are included at the connector.

Built-In-Self-Test Diagnostics
SPECIFICATIONS

On-board built-in-self-test (BIST) diagnostics provides confidence testing of the various functional areas of the iSBC 186/224A controller board. The initialization checks are performed by the 8751 microcontroller, while the BIST package is executed by
the 80186 microprocessor.

CPU:

5 MHz 80186 synchronized to 5 MHz
8237 A-5 DMA controller

Memory: 128K bytes DRAM on-board for buffers
and track cache
2 PROM sites contain Built-in-Self-Test
(BIST) and PCI firmware

BIST provides valuable testing and error reporting
and recovery capability on MULTIBUS II boards, enabling the OEM to reduce manufacturing and maintenance costs. An LED on the board's front panel
indicates go/no go status of power-up diagnostics.
Further information ls available via interconnect
space.

Mass Storage Device Compatibility
Wirichester-ST506/412 compatible 5%" drives
with up to 1024 cylinders.
Manufacturers include: Quantum, CMI, CDC,
Maxtor, Memorex, Atasi.
Densities range from 10 MB to 140 MB.

Peripheral Communications Interface
A message-based peripheral communications interface provides a software interface to the 186/224A
board. This protocol provides a vehicle to issue multiple commands or statuses concurrently. This allows the 186/224A board to accept multiple commands and queue them in on-board memory.

Floppy-SA450/460 compatible 5%" drives.
Manufacturers include: Teac, Shugart.
Sizes include half height, full height, 48TPI, 96TPI.
Tape-QIC-02 compatible, %" streaming tape
drives.
Manufacturers include: Archive, Cipher, Tandberg.

BACKPLANE BUS INTERFACES
Physical Dimensions

P1 Connector: This is used as the standard MULTIBUS II 32-bit parallel system bus. It contains allsignals required to implement the full standard interface.

The iSBC 186/224A board meets all the mechanical
specifications as presented in the MULTIBUS II specification (order #146077 rev. C).

P2 Connector: The P2 connector is not electrically
connected internally on the board.

DOUBLE-EUROCARD FORM FACTOR
Depth: 220 mm (8.6 in)
Height: 233 mm (9.2 in)
Front Panel Width: 20 mm (0.784 in.)

12-5

inter

iSBC® 186/224A MULTI-PERIPHERAL CONTROLLER SUBSYSTEM

CONNECTORS
Interface

Connector

Part No.

iPSB bus (P1)

96 Pin DIN, Right Angle Female

603-2-IEC-C096-F

96 Pin DIN, Right Angle Female,
Not Connected Internally

603-2-IEC-C096-F

ST506/412 (Winchester)

50 Pin D Type, Right Angle Female,
High Density (See Note)

SA450/460 (Floppy)

25 Pin D-Type, Right Angle Female,
(See Note)

QIC-02 (Tape)

25 Pin D-Type, Right Angle Female,
(See Note)

NOTE:

The manufacturers below provide connectors which will plug into the connectors supplied on· the iSBC 186/224A board
front-panel.

Connector Type Manufacturer Pins
Flat Ribbon
Crimped
T&BAnsley
50
T&BAnsley
25
Bulk Cable
Solder Cup

Pin Crimp

Reference Manuals

Part No.

iSBC 186/224A Board Hardware Reference Manual
(order number 138272-001)

609-50P
609-25P

Amlan
Amlan
ITT Cannon
ITT Cannon

50
25
50
25

CDS50L
CDS25L
DD-50P
DB-25P

AMP
AMP
ITT Cannon
ITT Cannon

50
25
50
25

206438-1
205436-1
DDC-50P
DBC-25P

Intel MULTIBUS II Bus Architecture Specification
(order number 146077)
Manual may be ordered from any Sales Representative, Distribution Office, or from the Intel Literature
Department, 3065 Bowers Ave., Santa Clara, CA
95051.

ORDERING INFORMATION
Part Number

Description

iSBC 186/224A

Multiperipheral
system

Controller

Sub-

12-6

MULTIBUS® II
Serial Communication Board

iSBC® 186/410 MULTIBUS® II
SERIAL COMMUNICATIONS COMPUTER
Serial Communication Channels on
• Six
a Single MULTIBUS® II Board,

TIBUS® II iPSB (Parallel System
• MUL
Bus) Interface with Full Message

Expandable to 10 Channels via iSBXTM
Bus Connectors

Passing Capability

•

Integration 8 MHz 80186
• High
Microprocessor
Advanced DMA Controller
• 82258
Provides 4 Independent High
Performance DMA Channels
Supports RS232C-Only on 4 Channels,
• RS422A or RS232C Interface
Configurable on 2 Channels
• 512K Bytes DRAM Provided

Four 28-Pin JEDEC Sites, Expandable
to 8 Sites with iSBC® 341
MULTIMODULETM for a MaximOm of
512K Bytes EPROM

iSBXTM Connectors for Low Cost
• Two
1/0 Expansion
MULTIBUS® II Interconnect Space for
• Software
Configurability and
Diagnostics
Resident Firmware to Support Host-to• Controller
Download Capability and
Built-In-Self-Test (BIST) Diagnostics

The iSBC 186/410 MULTIBUS II Serial Communications Computer is an intelligent 6-channel communications
processor implementing the full, high performance message passing interface of the MULTIBUS II (iPSB)
Parallel System Bus. This iSBC board combines an 8 MHz 80186 16-bit microprocessor, with six serial channels (expandable to 10 serial channels on-board via iSBX connectors), up to 512K bytes of DRAM, four 28-pin
JEDEC sites, two iSBX connectors, and an 82258 ADMA controller on a single 220 mm x 233 mm (8.7 in. x 9.2
in.) Eurocard printed circuit board. The iSBC 186/410 board supports asynchronous, byte synchronous, and
bit-synchronous (HDLC/SDLC) communications protocols on the two full/half duplex RS232C/RS422A channels, and asynchronous-only on the four full/half duplex RS232C-only channels. Acting as a terminal controller
or front-end processor, this board adds significant data communications flexibility to an OEM's MULTIBUS II
design.

280268-1

13-1

October 1987
Order Number: 280268-002

iSBC® 186/410

ter controller applications also require character and
format conversion capabilities to allow attachment
of different types of terminals.

OPERATING ENVIRONMENT
The iSBC 186/410 MULTIBUS II Serial Communications Computer is a powerful data communications
sub-system specifically designed to operate in and
support the message-based, multi-processor system
configurations being implemented on the MULTIBUS II architecture. The board's on-board CPU, an 8
MHz 80186 microprocessor, provides significant intelligence to off-load and distribute the serial communications functions away from one or all of.a system's processor boards.

The iSBC 186/410 MULTIBUS II Serial Communications Computer is well suited for multi-terminal system applications (see Figure 1). Up to 10 serial
channels can be serviced in multi-user or cluster
configurations by adding two iSBX 354 Dual Serial
Channel MULTIMODULE boards. The on-board
512K byte (expandableto.512K bytes) DRAM array
is the buffer area designed to handle incoming and
outgoing messages at data rates up to 19.2K baud
(asynch). Each serial channel can be individually
programmed for different baud rates to allow system
configurations with differing terminal types. The onboard 80186 CPU handles the protocols and character manipulation tasks traditionally performed by a
system host.

The iSBC 186/410 board was designed with a set of
features to address several communications application areas: terminal/cluster controller, or front-end
processor.

Terminal/Cluster Controller
Front-end Processor

A terminal/cluster controller concentrates communications in a central area of a system. Efficient handling of messages coming in or going out of the system requires sufficient buffer space to store messages along with high speed I/O channels to transmit and receive those messages. Sophisticated clus-

A front-end processor off-loads a system's central
processor of bandwidth-draining tasks such as data
manipulation and text editing of characters collected
from the attached serial I/O devices. Since most ter-

ISBX'· 354
BOARD

ISBC@ 186/410
BOARD

;SBC" 386/100 BOARD

80186

FIRMWARE

CLUSTER
CONTROLLER

SYSTEM
PROCESSSOR
MULTIBUS'" IPSB BUS

280268-2

Figure 1. Terminal/Cluster Controller Application

13-2

inter

iSBC® 186/410

o
•

MAINFRAME

ISBX'· 354
BOARD

ISBC® 186/410
BOARD

80186

FIRMWARE

CLUSTER
CONTROLLER

280268-3

Figure 2. Front-End Processor Application
minal and serial liD devices require flexible interfac·
es, program code is often dynamically downloaded
to the front-end processor from a system CPU.
Downloading code requires sufficient memory space
for protocol handling and program code. Flow con·
trol and interrupt handling requirements need an efficient real time operating software environment to
manage the hardware and software resources on
the board.

eas: Processor, Serial liD, Memory, General lID,
iPSB bus interface, and Interconnect (see Figure 3).

Processor Subsystem
80186 PROCESSOR
The central processor unit on the iSBC 186/410
board is Intel's 16-bit 8 MHz 80186 microprocessor.
The highly integrated 80186 CPU combines several
system components onto a Single chip (Le., two Direct Memory Access lines, three Interval Timers,
Clock Generator, and Programmable Interrupt Controller). The 80186 instruction set is a superset of
the 8086 and maintains object code compatibility
while adding additional instructions.

The iSBC 186/410 board features are designed to
provide a high performance solution for front-end
processor applications (see Figure 2). A large
amount of memory is provided for dynamic s~orage
of program code. Two serial channels (as well as
four iSBX expansion serial channels) can be configured for links to mainframe systems, point-to-point
terminals, modems or multi·drop designs and four
serial channels are for terminal communication,
asynchronous RS232C operation only.

This high performance component manages the
board's multi-user, multi-protocol communications
operations. Refer to the Microsystem Components
Handbook, Order Number 230843-00X, for more detailed information on the hardware operation and requirements of the 80186 microprocessor component.

ARCHITECTURE
The iSBC 186/410 MULTIBUS II Serial Communications Computer consists of six major subsystem ar13-3

--'oL

RS422A I RS232C

SERIAL
INTERFACE

"11

IE
c

...

RS'32CIRS422A

RS232C

SERIAL

RS232C
SERIAL

INTERFACE

RS232C
SERIAL
INTERFACE

...,

lii
OJ

...
......
...
@>

(I)

...

SERIAL
COMMUNICATIONS

....
c.:>

OJ
0

CONTROLLER
(S'S3D}

...

SERIAL

COMIIUNICATIONS
CONTROLLER
(.'S3D}

, SERIAL
COMIIUNICATIONS
CONTROLLER
(S'S3D}

INTERRUPT

iSBX'1t

CONTROL
(2-8259As)

MULTIMODULE no
CONNECTOR

iSBX'.

M~~~:g~~~'"

c;;

n@J

....

II)

.b. a.

-<'<

"11

::J

'"c

1
1 I

il~

ON-BOARD 110 LOCAL BUS

0
::J
!!!.

~~nPLEXEr
OPTION

...

82258ADMA
DMACONTROL

(OPTION}

80186
CPU
SMHZ

512KBYTES
DRAM

IQ
II)

FOUR '8-P1N SITES

}

JEDEC

....
o

MEMORY
(OPTION}
FOUR .8-PIN SITES

.,.......

I'
L ~li~1 ~

MULTIBUS"II

iPsa

INTERFACE

i'-

8751

p.CONTROLLER
(INTERCONNECTI

BIST}

ON-BOARD MEMORY LOCAL BUS

A
IIULTIBUS' II PARALLEL SYSTEIIBU$

280268-4

iSBC® 186/410

DIRECT MEMORY ACCESS (DMA) FUNCTION

SERIAL I/O SUBSYSTEM

The iSBC 186/410 board provides 13 channels of
DMA to support serial liD, iPSB interface, and/or
iSBX bus transfer operations. The 80186 microprocessor provides two DMA channels, the 82258 Advanced (ADMA) controller supports three "direct"
channels of DMA, and the ADMA multiplexer circuit
uses the fourth 82258 ADMA channel providing
eight additional multiplexed DMA channels. The allocation of the board's DMA channels to on-board resources is listed in Table 1.

Six serial interfaces are provided on the iSBC
186/410 board: two interfaces support full asynchronous, byte-synchronous, and bit-synchronous
(HDLC/SDLC) communication and four interfaces
support asynchronous-only communication. The two
RS422A configurable ports can also be tri-stated to
allow multi-drop networks. The board's serial capability can be expanded to 10 channels by adding two
iSBX 354 Dual Channel Serial I/O MULTIMODULE
boards. Each added iSBX 354 board uses an

Table 1.ISBC® 186/410 Board DMA Channel Allocation
Channel
Count

DMA Configuration
Local Bus Resource

Channel
Number

80186
1

DMAChannel

Half-Duplex High Speed Serial Interface (SCC1 Channel A)
(-High Density 15-Pin Connector)

DMAChannel

Full-Duplex Serial Interface (SCC1 Channel A) or SBX1 DMA Request

Input DMA from MPC (Message Passing Coprocessor)

82258ADMA
3

DMAChannel

Output DMA to MPC

DMAChannel

Half-Duplex High Speed Serial Interface (SCC1 Channel B)
(-High Density 15-Pin Connector) or SBX1 DMA REO

DMAChannel

Full-Duplex High Speed Serial Interface (SCC1 Channel B) or
INT2 DMA REO from DMA Multiplexer

DMA Multiplexer"
6

DMAChannel

Half-Duplex Serial Interface (SCC2 Chan. A, 9-pin conn.)

DMAChannel

Full-Duplex Serial Interface (SCC2 Chan. A)

DMAChannel

Half-Duplex Serial Interface (SCC2 Chan. B, 9-pin conn.)

DMAChannel

Full-Duplex Serial Interface (SCC2 Chan. B) or SBX1 DMA Request
or Half-Duplex SCC1 Channel B.

DMAChannel

Half-Duplex Serial Interface (SCC3 Chan. A, 9-pin conn.)

DMAChannel

Full-Duplex Serial Interface (SCC3 Chan. A) or SBX2 DMA Request

DMAChannel

Half-Duplex Serial Interface (SCC3 Chan. B, 9-pin conn.)

DMAChannel

Full-Duplex Serial Interface (SCC3 Chan. B) or INT1 SBX1 for
SBX344

NOTE:
°ADMA Channel 3 is used to add the DMA Multiplexer.

13-5

inter

iSBC® 186/410

SOLC) modes. The increased capability at the serial
controller point results in off-loading a CPU of tasks
normally assigned to the CPU or its associated hardware. Configurability of the 82530 allows the user to
configure it to handle all asynchronous data formats
regardless of data size, number of start or stop bits,
or parity requirements. An on-chip baud rate generator allows independent baud rates on each channel.

82530 SCC component to provide two independent
full duplex serial channels configurable as either
RS232C or RS422A interfaces. It also supports both
asynchronous or programmable byte and bit synchronous· (HOLC/SOLC) protocols.. The HOLC/
SOLC interface is compatible with IBM system and
terminal equipment and with CCITT's X.25 packet
switching interface.
Three 82530 Serial Communications Controllers
(SCCs) provide six channels of half/full serial I/O.
Two channels are configurable as either RS232C or
RS422 on two high density 15-pin female O-shell
connectors. Four more channels are RS232C-only.
using IBM standard g-pin male O-shell connectors.
All six channels directly support the Data Terminal
Equipment (OTE) configuration, with the Data Communication Equipment (OCE) pin-out supported by
changes in the cable wiring.

Memory Subsystem
The iSBC 186/410 board's on-board memory subsystem consists of a large DRAM array and a set of
universal memory sites. Access to the on-board
memory subsystem resources, as well as off-board
iPSB bus access, is accomplished by observing the
iSBC186/410 board memory map (see Figure 4).
The mapping occurs within the 1 megabyte memory
space of the 80186 microprocessor, and is split into
three main areas: DRAM reserved, iPSB window,
and EPROM reserved. The first 0 to 512K bytes is
always reserved for local DRAM, the next 128K or

The 82530 component is designed to satisfy several
serial communications requirements; asynchronous,
byte-synchronous, and bit-synchronous (HOLC/

IPSB
MEMORY
MAP

D'GB~B

MBII
MEMORY

1024K

186/410
MEMORY
MAP

ON··
BOARD
EPROM
768K

WINDOW MAY BE
128KOR 256K

640K

J~s!,

WINDOW
512K

MBII
WINDOW

_- A----~-

BASE ADDRESS IS ANY MULTIPLE OF 128K
OR 256K (SIZE OF MULTIPLE WINDOW SIZE)

ON·
BOARD
DRAM

'--_ _...10
280268-5

Figure 4. iSBC® 186/410 Board Memory Map Diagram
13-6

intJ

iSBC® 186/410

256K bytes (or up to 768K) is the iSPB window, and
the remaining 384K or 256K byte area is reserved
for local EPROM. The iPSB window maps a 128K or
256K byte local memory area into the 4 gigabyte
global physiqal address range of the MULTIBUS II
iPSB bus. This window is programmable and allows
, the 80186 processor to access the complete 4 gigabyte memory space of the iPSB bus.
The board's memory map also supports a 64K byte
access window for, I/O space between local and
iPSB bus access. The 64K bytes of local I/O space
is mapped 1-to-1 to the iPSB bus' 64K byte I/O
space and is not programmable. The upper 32K
bytes access the iPSB bus I/O space, and the lower
32K bytes are reserved for local on-board,I/O.

tervals under software control. The outputs may be
independently routed to a PIC to count external
events. The system software configures each timer
independently and can read the contents of each
counter at any time during system operation.
In a MULTIBUS II system, external interrupts (inter. rupts originating from off-board) are interrupt type
messages over the iPSB bus rather than signals on
individual lines. Interrupt type messages are handled
by the bus interface logic, the MPC Message Passing Coprocessor chip. The MPC component interrupts the 80186 processor via an 8259A Programmable Interrupt Controller (PIC) indicating a message has been received. This means that 1 Interrupt
line can handle interrupts from up to 255 sources.
Two on-board 8259A PICs are used in a masterslave configuration for processing on-board interrupts. One of the interrupt lines handles the interrupt
messages received from the iPSB bus. Table 2 includes a list of devices and functions supported.

PRAM CAPABILITIES
The iSBC ,186/410 board comes standard with a
512K byte DRAM memory array on-board.
EPROM,- MEMORY

iSBXTM BUS I/O EXPANSION

A total of four 28-pin JEDEC universal sites reside
on the iSBC 186/410 board. These sockets support
addition of byte-wide ROM and EPROM devices in
densities from 8K bytes (2764) to 64K bytes (27512)
per deyice.,Two of the four sockets contain a pair of
27812 EPROM deviCes iristalled at the factory(1l.
These devices contain 128K bytes of firmware providing both the Host-to-controller download routine
and the Built-In-Self-Test (BIST) power~up diagnostics routine. The remaining two sockets allow the
user to add either two additional devices or an iSBC
341 EPROM MULTIMODULE for a maximum of
, 512K bytes.

Two 8/16-bit iSBX bus (IEEE P959) connectors are
provided for modular, low-cost I/O expansion. The
iSBC186/410 board supports both 8-bit and 16-bit'
iSBX MULTIMODULEs through these mating, gastight pins and socket connectors. DMA is also supported to the iSBX connectors and can be configured by programming the DMA multiplexor attached
to the 82258 ADM A component. The iSBX connectors on the iSBC 186/410 board support a wide variety of standard iSBX compatible boards from Intel
and other independent, vendors providing add-on
functions such as, floppy control, %" tape' control,
bubble memory, parallel/serial 110, BITBUSTM interface, math, graphics, IEEE 488, and analog I/O.
Custom iSBX module designs are also supported as
per the IEEE P959 iSBX bus specification.

NOTE:
(1) Tl)ese devices may be removed by the user for
access to the two 28-pin sites.

iPSB Bus Interface Subsystem

. GeneraH/O Subsystem

This subsystem's main component is the Message
Passing Coproc;:essbr chip. Subsystem services provided by the MPC bus interface component include
full message passing support and memory, I/O, and
interconnect access to the iPSB bus by the 801 a6
processor. The single-chip Message Passing Coprocessor is a highly integrated CHMOS device ,implementing the full message passing protocol and
performing all the arbitration, transfer, and exception
cycle protocols specified in the MULTIBUS II Architecture Specification Rev. C., Order Number
146077.

The I/O subsystem provides timers, interrupt control
and two IEEE P959 iSBX connectors for I/O expansion or customization.
PROGRAMMABLE TIMERS AND INTERRUPT
CONTROL
The 80186 microprocessor on the iSBC 186/410
board provides three independent,' fully programmable 16-bit interval timers/event counters for use by
the systems deSigner to generate accurate time in-

13-7

intJ

ISBC® 186/410

Table 2.ISBC® 186/410 Board Interrupt Devices and Functions
Device

Function

Number of
. Interrupts

iPSB Bus Interface (MPC)

Message·Based Interrupt Requests from the iPSB
bus via MPC Message Passing Coprocessor

1 interrupt for
up to 255
sources

8751 Interconnect Controller

Interconnect Space

80186 Timers & Interrupt

Timers 0 and 1 and Interrupt Acknowledge 1

82530 SCCs (3 devices)

SCC # 1 and SCC # 2 or SCC # 3 for Transmit
Buffer Empty, Receive Buffer Full, and Channel
Errors

iPSB Bus Interface (MPC)

Indicates Transmission Error on iPSB Bus

82258ADMA

DMA Transfer Complete

IEEE P959 iSBX Bus Connectors (2)

Functions Determined by iSBX Bus
MULTIMODULE Boards

IEEE P959 iSBX Bus Connectors (2)

DMA Interrupt from iSBX (TDMA)

4
(2/ connector)
2

for the exclusive use of the download program. Host
CPUs must not overwrite this area with download
commands.

Interconnect Subsystem
MULTIBUS II interconnect space is a standardized
set of software configurable registers designed to
hold and control board configuration information as
well as system and board level diagnostics and testing information. Interconnect space is implemented
with the 8751 microcontroller and the MPC silicon
resident on the iSBC 186/410 board.

Software on the host is responsible for accessing
the iSBC 186/410 board's firmware on disk or from
ROM visible to the host and translating it into linear
sequences of bytes suitable for downloading (see
Figure 5). After downloading the firmware, the host
issues a command for the loader routine on the controller to begin execution of the downloaded software.

The read-only registers store information such as
board type, vendor 1.0., firmware rev. level, etc. The
software configurable registers are used for autosoftware configurability and remote/local diagnostics and testing.

BUILT-IN SELF-TEST DIAGNOSTICS
On-board built-in self-test (BIST) diagnostics provide
a customer confidence test of the various functional
areas on the iSBC 186/410 board. The initialization
checks are performed by the 8751 microcontroller,
while the BIST package is executed by the 80186
microprocessor. On-board tests included in the BIST
package are: DRAM, EPROM, 80186, 82530 SCCs,
and the MPC.

Firmware Capability
HOST/CONTROLLER SOFTWARE DOWNLOAD
ROUTINE
Resident in ROM on this controller is a host-to-controller software .download routine to support the
downloading of communication firmware into the
iSBC 186/410 Serial Communication Computer.
This loader adheres to the MULTIBUS II Download
Protocol and responds to commands issued by software running on a host CPU board. The host CPU
passes these commands to the loader via registers
defined in the board's interconnect space. A download function, a commence execution function, and
an examine local memory function are all provided in
the routine. Data transfers are supported by both
shared memory systems and message based systems. The top 1K of DRAM on the board is reserved

Additional activities performed include initialization
at power-up using the Initialization and Diagnostics
Executive and a program table check, a feature allowing users to add custom code in EPROM while
still maintaining full use of factory supplied BISTs.
Immediately after power-up and initialization of the
8751 microcontroller, the 80186 microprocessor begins its own initialization and on-board diagnostics.
Upon successful completion of. these activities, the
Initialization and Diagnostics Executive invokes the
user-defined program table. A check is made of the
program table which then executes user-defined
custom programs.
13-8

iSBC® 186/410

HOST

FIRMWARE

CONTROLLER

ROM BASED
DOWNLOAD
ROUTINE

IPSBBUS

280268-6

Figure 5. Download Routine
The BIST package provides a valuable testing, error
reporting and recovery capability on MULTIBUS II
,boards enabling the OEM to reduce manufacturing
and maintenance costs. An LED on the board's front
panel indicates the status of power-up diagnostics. It
is on when BIST diagnostics start running and is
turned off upon successful completion of the BISTs.

NOTE:
Basic instruction cycle is defined as the fastest instruction time (i.e., 4 clock cycles).

Memory Capacity
Local Memory

SPECIFICATIONS

DRAM-512K bYtes on-board (64K x 4-bit devices);
8 sockets provided to support additional 256K bytes

Word Size

EPROM-Number of sockets-four 28-pin JEDEC
sites

Instruction: 8-, 16-, 24-, 32-, 40-, or 48-bits
Data: 8-. or 16-bits

EPROM

Device Size
(Bytes)

Max. Memory
Capacity

System Clock

2764
27128
27256
27512

8K
16K
32K
64K

32K bytes
64K bytes
128K bytes
256K bytes

CPU: 8.0 MHz

NOTE:
"EPROM Expansion to up to a maximum of 512K bytes is
achieved via attachment of the iSBC 341 EPROM (256K
byte) MULTIMODULE board.

Cycle Time
Basic Instruction: 8.0 MHz-500 ns

I/O Capability
Serial-Six programmable serial channels using
three 82530 Serial Communications Controller components.

13-9

i,SBC@ 186/410

I/O Expansion-Two 8/16-bit IEEE P959 iSBX connectors (DMA supported): (The board supports either two single wide or one double-wide form factor
iSBX module(s).)

Baud Rates

Timers-Three programmable timers on the 80186
microprocessor.

Synchronous X1 Clock
(Channels 0, 1)
Baud Rate

82530 Count Value
(Decimal)

64000
48000
19200
9600
4800
2400
1800
,1200
300

36
49
126
254
510
1022
1363
2046
8190

Input Frequencies-Frequencies supplied by the internal 80186 16 MHz crystal; 82530 SCCs: crystal
driven at 9.8304 MHz div. by two;iSBX Connector:
crystal driven at 9.8304 MHz.

Serial Communications Characteristics
Synchronous-Internal or external character synchronization on one or two synchronous characters.
Asynchronous-5-8 data bits and 1,·1 % or 2 stop
bits per character; programmable clock factor; break
detection and generation; parity, overrun; and framing error detection.

Asynchronous X16 Clock
(Channels 0-5)
Baud Rate

82530 Count Value
(Decimal)
6
14
30 '
62
83
126
510
1394

19200
9600
4800.
2400
1800
1200
300
110

Serial Signals/Pin-Outs
RS232C Interface Pin ASlIlgnment for High Density 15-Pln Connectors
J2
Pin

RS-232CPin
Number

RS-232C Signal
Name

R5-232C Signal Function

1
2
3
4
5
6

7
8

TXD
RTS
RXD
CTS
RXC
DSS
DTR
DSR
DCD
STXC
SGD
LCLPBK
RMLPBK
TSTMD
RNG

Transmit Data
Request To Send
Receive Data
Clear To Send
Receive Clock
Data Signal Select
Data Terminal Ready
Data Set Ready,
Carrier Detect
Transmit Clock
Signal Ground
L6calLoopback
Remote Loopback
Test Mode Indicator
Not Supported

8
9
10
11
12
13
14
15

9
10
11
12
13
14
15

13·10

inter

ISBC® 186/410

RS422A Interface Pin Assignment for High Density 15-Pln Connectors
J1
Pin

Signal Name
On Board

RS-422A Signal
Name

RS42211

TR (a)
(a)
RD(a)
(a)
(a)
TR (b)
(b)
RD(b)
(b)
(b)

1
2
3
4
5
6

RS42212

7
8

RS42290

RS4229

9
10
11
12
13
14
15

RS-422A Signal Function
Transmit Data
Control
Receive Data
Indication
Signal Timing
Transmit Data
Control
Receive Data
Indication
Signal Timing
Signal Ground
Not Used
Not Used
Not Used
Chassis Ground

NOTE:
The iSBC@ 186/40 board does not support the unused signals.

RS232C Interface Pin Assignment for IBM® Compatible 9-Pln Connectors
Pin Number

Signal Name

Function

InlOut

1
2
3
4
5
6

CD
RXD
TXD
DTR
SG
DSR
RTS
CTS
RI

Carrier Detect
Received Data
Transmit Data
Data Terminal Ready
Signal Ground
Data Set Ready
Request To Send
Clear To Send
Ring Indicator

In
In
Out
Out

7
8
9

Interrupt Capability

In
Out
In
Not Supported

Connectors

Potential Interrupt Sources from iPSB Bus-255 individual and 1 Broadcast
Interrupt Levels-12' vectored requests using two
8259As and 1 input to the master PIC from the slave
PIC
Interrupt Requests-All levels TTL compatible

Interfaces
iPSB Bus-Compliance Level RQAlRPA D16M32
iSBX Bus-Compliance Level 08/16 DMA
Serial 1/0-2 ch. RS232C or RS422A compatible,
configured DTE only; 4 ch. RS232C IBM compatible
only, configured DTE only.

Interface
iPSB
bus (P1)

Connector
96-pin DIN, right
angle female

Part #
603-2-IEC-C096-F

RS232CI 15-pin high density,
RS422A o type, right
angle female
(see note)
RS232C- 9-pin IBM com patible, 0 type, right
only
angle male (see
note)
NOTE:
The manufacturers below provide connectors which
will mate with the connectors supplied on the iSBC
186/410 board front-panel.

13-11 '

inter

iSBC® 186/410

Mating Connectors, Shells and Cables
Connectors and Shells

Manufacturer

Pins

Part No.

High Density D-type Plug (male)
High Density D-type Plug (male)
D-type Receptacle (female)
D-type Receptacle (female)
Connector Shells

AMP
Positronic
AMP
ITT-Cannon
AMP
,
ITT-Cannon
3M

15
15
9
9
(For 15 or
9-pin connect.
above).

204501-1
DD-15M
205203-3
DE-9S
745171-X
DE-51218
358-2100

Cable Description
15 Conductor-Shield,
15 Conductor-Shield,
10 Conductor-Shield,
9 Conductor-Shield,

Manufacturer

Round
Round
Round
Round

Part No.

Alpha
Beldon
Alpha
Beldon

5120/15
9541
5120/10
9539

NOTE:
All cable referenced is available in 100 flo minimum lengths.

PHYSICAL DIMENSIONS

ELECTRICAL CHARACTERISTICS

The iSBC 186/410 board meets all MULTIBUS II
mechanical specifications as presented in the
MULTIBUS II Architecture Specification Handbook
(#146077, Rev .. C)

The maximum power required per voltage is shown
below.

Eurocard Form Factor
Depth: 220 mm (8.7 inches)
Height: 233 mm (9.2 inches)
Front Panel Width: 20 mm (0.76 inches)

Voltage
(volts)

Max. Current
(amps)

Max. Power
(watts)

+5V
+12V
-12V

8.22A
150 mA
150 mA

43.16W
1.89W
1.89W

REFERENCE MANUALS

Weight: 822 gm (29 ounces)
iSBC 186/410 Serial Communications Computer User's Guide (#148941-001)

ENVIRONMENTAL
CHARACTERISTICS

Intel MULTIBUS II Architecture Specification Handbook (# 146077)
Manuals may be ordered from any Intel Sales Representative, Distribution Office, or from the Intel Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

Temperature
Inlet air at 200 LFM airflow over all boards
Non-operating: - 40°C to + 75°C
Operating: 0° to + 55°C

ORDERING INFORMATION
Humidity

Part Number

Non-operating-95% Relative Humidity
non-condensing
Operating-900/0 Relative Humidity
condensing

+ 55°C,

Description

iSBC 186/410 MULTIBUS II Serial Communica-·
tions Computer

+ 55°C, non-

13-12

MULTIBUS® II
System Packaging and
Development Accessories

iSBC® PKG/606
iSBC PKG/609
MULTIBUS® II CARDCAGE ASSEMBLIES
• Available in Two Sizes to Hold Up to 6
or 9 MULTIBUS® " Boards
• Designed to Mount Inside a Chassis or
Other Enclosure

•

All Lines Fully Terminated per the iPSB
MULTIBUS " Specification

•

Assembly Uses Aluminum Extrusion
Construction for Strength and Rigidity

•

Uses a 6 Layer Parallel System Bus
(iPSB) Backplane

Accommodates Intel iSBC® PKG/902
and iSBC® PKG/903 2 and 3 Slot
iLBXTM " Backplanes

The iSBC PKG/606/609 series of card cages are designed to mount and interconnect up to 6 or 9 MULTIBUS II
boards for small to medium size advanced MULTIBUS II microcomputer systems. The cardcages are compact
in size and easily mount in standard or custom enclosures. Extra-wide support extrusions and heavy duty
endplates help make the iSBC PKG/606/609 cardcage assemblies especially suited for installation in systems
located in high vibration or high shock environments. Installed in the card cage assembly is a 6 layer iPSB
backplane that utilizes separate power and ground planes and fully terminates all signal lines. This layout
minimizes system noise and ensures reliable operation even in a fully loaded, multiprocessor,based system.

280075-1

14-1

September 1986
Order Number: 280075-002

iSBC® PKG/606 iSBC PKG/609

FUNCTIONAL DESCRIPTION.
Mechanical Features
The cardcages accommodate up to 6 (iSBC
PKG/606) or 9 (iSBC PKG/609) MULTIBUS II
boards spaced at 0.8 inch centers. The assemblies
are designed to. hold "double high" (6U) Euro formfactor boards (233.4 mm high x 220 mm deep) or a
mixture of "single high" (3U) and "double high"
boards using additional hardware (not supplied).
Each installed board is held in place by two screws
supplied as part of the board retainer hardware.
The cardcage frame is built using five support extrusions and two aluminum end' plates as shown in figure 1. Both cardcages are 10.5" wide and 10.1"
deep and vary in height according to model (see
specifications section).
The card cages are designed to mount inside chassis
or other enclosures and may be installed so that the
MULTIBUS II boards load either horizontally or vertically in the unit. All assembly hardware is countersunk allowing the card cages to be mounted flush
against any internal chassis surface.
A Parallel System Bus (iPSB) backplane is mounted
to the P1 side of the assembly, and one or more
iLBXTM II backplanes (not supplied) can be mounted
to the P2 side.

capacitive loading on the bus. Mounted on the backplane are 6 or 9, 96-pin, female DIN connectors (depending on model), bus termination resistors, decoupiing capacitors, and power terminals. Press-fit technology is used throughout. The PC board is UL recognized for flammability. The card cages themselves
are UL recognized components.
Single In-line Package (SIP) style resistors are used
to terminate all address, clock, data, and control
lines. Each termination consists of two resistors
which connects the line to + VCC and ground. Different size resistors are used according to the type
of driver connected to the line in an operating
system.
The DIN type connectors are female, 96 pins, fully
gold plated, and meet IEC standard 603-2-IECC096F. The connectors are mounted on 0.8" centers to match Intel's iPSB (Parallel System Bus)
MULTIBUS II backplanes and are keyed to ensure
proper mating to the MULTIBUS II board. The connector can provide up to 9 amps of current at + 5V
to each MULTIBUS II board in addition to the current
available over the iLBX II backplane.
Screw terminals on the backplane are provided for
connection to + 5V, ± 12V power and ground. In addition, an extra + 5V terminal is provided for connection to a backup battery for memory protection during power fail conditions. These terminals, each of
which can handle up to 25 amps of current at 55"C,
provide a simple and highly reliable connection
method to the system power supply.

Electrical Features
The iPSB backplane uses a 6 layer design with separate power and ground layers and a signal routing
scheme which minimizes ringing, crosstalk, and

The first slot position is designed to accept the Central Services Module (CSM) MULTIBUS II board. All
other slots can accept any combination of
MULTIBUS II boards.

END PLAte
(1 OF 2)
IPSB BACKPLANE
(9 SLOT SHOWN)

I.~(25.68CM.)~.1

-Pl\DE

SUPPORT
EXTRUSION _
(1 OF 5)

~,
10'
~I

10'

SLOT 0
(Jl)

10.11 IN

ILBX'" ..
MOUNTING
LOCATION
-P2 SIDE

' - 10.47 IN.
(26.59 CM.)

----l1

/
/'

SUPPORT
v--,EXTRUSION

V- CARD GUIDE

'SEE SPECIFICATIONS

280075-2

Figure 1. Cardcage Assembly Dimensions (iSBC® PKG/S09 shown)
14-2

iSBC® PKG/606 iSBC PKG/609

SPECIFICATIONS

Mechanical
Specification

ISBC® PKG/606 Cardcage

ISBC® PKG/609 Card cage

6
15.20 cm (5.98 in.)
26.59 cm (10.47 in.)
25.93 cm (10.21 in.)
4 Ibs. (1.8 kg)

9
21.20 cm (8.38 in.)
26.59 cm (10.47 in.)
25.93 cm (10.21 in.)
5 Ibs. (2.3 kg)

Board Capacity
Dimensions Height
Width
Depth
Weight
Board Spacing

0.8 in. (20.3 cm)

Mounting Hole Locations

See Figure 2

Construction Materials,
Cardcage Frame

Aluminum extrusions and end plates, nylon card guides

Construction Method
iPSB Backplane

Six layer backplane with separate VCC and ground layers;
all connectors, power terminals, and resistor/capacitor
sockets are press-fit into the backplane

Connector Type

96 pin "DIN" female, gold plated, meets IEC standard
603-2-IEC-C096-F
Quantity of Power Terminals and Current Rating:

Electrical
iPSB Backplane- Meets Intel MULTIBUS II specification No. 146077 for board
dimensions, layout, signal line
termination, and transmission
characteristics

Voltage

Quantity

r--

::~~~

I
0

f-o

(1l

(22.89 CM) ~

3
1
1
1
4

+5
+12
-12
+5BB
GND

Power Connections- Type: Screw terminal block,
AMP PIN 55181-1, Winchester PIN 121-25698-2, or
equivalent

.73 IN
.
(1.85 CM)I

ISBC® PKG/606
Cardcage

ISBC® PKG/609
Cardcage

Current
Current
Quantity
(amps)
(amps)
54
12
12
12
78

4
1
1
1
5

1.49 IN
(3.78 CM)

BOTTOM
VIEW

6.28 IN

M.)

~r-

.1881N (4.78 MM)
DIA. (4 PL)

7-------

BACKPLANE
MOUNTING ----'
LOCATION

REAR

280075-3

Figure 2. Mounting Hole Locations
14-3

81
18
18
18
135

ISBC® PKG/606 iSBC PKG/609

Operating Environment:
0-55·C (at 25 amps per power terminal);
0-70·C (at ~ 18 amps per power terminal);
0% to 95% relative humidity, non-condensing;
0-10,000 ft. altitude.

Mating Connection: No. S locking spade or ring
tongue lug

Maximum current available per slot:
- Current

Voltage

Reference Manual- MULTIBUS II Cardcage Assembly and iLBX II Backplane User's Guide, PIN
146709-001 (supplied).

9A
2A
2A
2A

+ 5V
+12V
-12V
+5BB

ORDERING INFORMATION
Part Number

Description

iSBC PKG/SOS

S slot MULTIBUS II Cardcage
Assembly

iSBC PKG/S09

9 slot MULTIBUS II Cardcage
Assembly

14-4

iSBC® PKG/902
iSBC® PKG/903
MULTIBUS® II iLBXTM II BACKPLANES

•
•
•

Provides iLBXTM II Interconnect for
Fastest CPU/Memory Data Transfers
Designed to Mount in MULTIBUS® II
Card cage Assemblies
Meets All Electrical and Mechanical
Requirements of the MULTIBUS® II
Specifications

Uses a 6 Layer, Fully Terminated
Backplane
Includes a 10 Pin Connector for
BITBUSTM Applications
Available In 2 Slot (iSBC® PKG/902)
and 3 Slot (iSBC® PKG/903) Sizes

The iSBC PKG/902 and iSBC PKG/903 series of iLBX II backplanes are designed to mount on the P2 side of
Intel's MULTIBUS II card cage assembly or other double Euro (6U) cardcage. One or more backplanes may be
installed in a system to allow high speed data transfers between the CPU and memory boards installed in the
system. The iLBX II backplane uses a 6 layer PCB with separate power and ground planes and full termination
on all signal lines. This design minimizes system noise and ensures reliable operation in all applications.

280074-1

14-5

October 1986
Order Number: 280074-002

inter

iSBC® PKG/902 ISBC® PKG/903 BACKPLANES

of driver connected to the line in an operating system. The· SIP style resistors help make the board
compact in size and allows the designer to mount
several backplanes directly adjacent to one another
in a system without having to skip slots.

I"..",_-a--·"I
o

JJ 1-,..-

.110 IN. DIA. (4PL)/

(2.8MM)

,.....

Mounted on the rear of the backplane is a 10-pin
BITBUS connector. This connector serves as the serial communication interface for any iSBX 344 BITBUS controller boards installed in the system.

:1-

The DIN type connectors are female, 96 pins, fully
gold plated, and meet IEC standard 603-2-IECC096F. The cOnnectors are mounted on 0.8" centers to match Intel's iPSB (Parallel System Bus)
MULTIBUS II backplanes and are keyed to ensure
proper mating to the MULTIBUS II board. The connectot can provide up to 6 amps of current at + 5V
to each MULTIBUS II board in addition to the current
available over the Parallel System Bus backplane.

.....
.r.i

!is'

u!i

0 ..
... 0

-~.,;

::.

Screw terminals on the backplane are provided· for
connection to + 5V power and ground. These terminals,each of which can handle up to 25 amps of
current, provide a simple and highly reliable connection method to the power supply.

Ol-~

- '-!-I""'..::::-:.-:.-A------------I-·~I

280074-2

Dimensions

iSBC PKG/902

IN
CM

1.55 .80
3.94 2.03

iSBC PKG/903

IN
CM

2.35
5.97

SPECIFICATIONS

Mechanical and Environmental

1.60
4.06

Connector Spacing: 20.3 cm (0.8 in)
Number of Slots: iSBC PKG/902: 2 slots
iSBC PKG/903: 3 slots

Figure 1.ILBXTM II Board Dimensions
(iSBC® PKG/903 Shown)

Board Dimensions: See Figure 1
Weight: iSBC PKG/902-O.2 kg (8 oz)

FEATURES

iSBC PKG/903-O.3 kg (12 oz)

Mechanical and Electrical

Connectors:
DIN: 96-pin female, gold plated, meets IEC standard 603-2-IEC-C096-F

The iSBC PKG/902 and iSBC PKG/903 iLBX II
backplanes use a 6 layer printed circuit board (PCB)
with separate power and ground layers and a signal
·Iead routing scheme which minimizes ringing, crosstalk, and capacitive loading on the bus. Mounted on
the PCB are two (iSBC PKG/902) or three (iSBC
PKG/903) 96 pin DIN connectors, one 10-pin BITBUS connector, terminating resistors, decoupling
capacitors, and power terminals. The resistors and
capacitors are mounted into sockets, and all parts
are press-fit into the backplane. The PCB is UL recognized for flammability.

BITBUS: 10-pin male, gold plated, T&B Ansley 6091012M, or equivalent
Constructed Method: Six layer backplane with separate VCC and Ground layers
All connectors, power terminals, and resistor/capacitor
sockets are press-fit into the
backplane
Mounting Hole Location: See Figure 1
Operating Environment: 0°C-70°C ambient temperature; 0% to 90% relative
humidity, non-condensing;
o ft.-1 0,000 ft. altitude

Single In-line Package (SIP) style resistors are used
to terminate all address, clock, data, and control
lines. Each termination consists of two resistors
which connects the line to + VCC and ground. Different size resistors are used according to the type
14-6

infef

iSBC® PKG/902 iSBC® PKG/903 BACKPLANES

Electrical

Backplane Electrical
Characteristics and
Line Terminations:

REFERENCE MANUAL
Per Intel MULTIBUS II
specification 146077,
Sec. II, iLBX II

MULTIBUS II Cardcage Assembly and iLBX Backplane User's Guide, PIN 146709-001 (not supplied)

ORDERING INFORMATION

Power Connections
Type: Screw terminal block: AMP PIN 55181-1;
Winchester PIN 121-25698-2; or equivalent
Mating Connection: No. 6 locking spade or ring
tongue lug
Quantity: 2(VCC, Ground)
Current Rating: iSBC PKG/902: 12 amps; iSBC
PKG/903: 18 amps (Power and
Ground)
Maximum Current
6 amps (over the iLBX II backAvailable Per Slot:
plane)

Part Number
iSBC PKG/902
iSBC PKG/903

14-7

Description
2 slot iLBX II Backplane
3 slot iLBX II Backplane

SYP 500

MULTIBUS® n
.SYSTEM CHASSIS

• Full enclosure MULTIBUS@ II design .
development tool or OEM.chassis
.• Office and industrial applications
• 3 full heighU6 half height peripheral
.
bays
• 8 slot MULTIBUS@ II cardcage
assembly
• 3 slot iLBX'"" II backplane
• 535 Watt power supply
• Fully tested: low-noise, shock/vibration
and electrostatic resistant

DECEMBER 1988
ORDER NUMBER: 28010;3.002

14-8

The SYP 500 System Chassis is a
MULTIBUS II design tool enabling
product designers to begin work
immediately on MULTIBUS II
development projects. It is also ideal
for OEM applications. Two front
mounted LEDs indicate "Power On"
and "Status" (PSB busy) while a
keyswitch provides external "reset"
capabilities for the chassis. The voltage
selector, power-on switch and cardcage
opening are located in the rear of the
chassis. Three peripheral bays, two of
which are accessible from the front of
the chassis, support up to three industry
standard 5.25" full-height or six halfheight peripherals. An eight slot
cardcage, Parallel System Bus
and iLBX II backplane assembly are
integrated with a 535 Watt
power supply.

FUNCTIONAL DESCRIPTION

Mechanical Features
Intel's SYP 500 MULTIBUS II Chassis
is a full enclosure, off-the-shelf design
development tool and OEM chassis.
Designers and systems integrators can
integrate their MULTIBUS II board set

with tape, Wini or floppy peripherals
into a complete system. The SYP 500
has three full-height 5.25" peripheral
bays. Peripheral power cables, office
and industrial environment cooling, and
peripheral mounting brackets for
industry standard full- or half-height
peripherals are provided with the
chassis. Access via the front panel
allows two of the bays to be configured
with removable media peripherals e.g.
tape and floppy drives.
This chassis includes an eight-slot
MULTIBUS II cardcage assembly with
0.8" centers (slot width). The cardcage
is made with heavy duty endplates and
extra-wide support extrusions to ensure
adequate support for most applications.
For industrial applications, this chassis
is mountable into any 19" vertical rack.
Two backplanes are installed in the
cardcage assembly: the system
backplane and the auxiliary backplane.
The system backplane is the Parallel
System Bus (iPSB) for communications
between up to eight MULTIBUS II
boards. This backplane utilizes separate
power and ground planes and fully
terminates all signal lines. The

SPECIFICATIONS:
Electrical Parameters
Maximum Amperage:

Electrical Features
The SYP 500 chassis has a 535 Watt
switching power supply with selectable
AC power input of 115 V or 220 V at
47-63Hz. The AC input power is
externally selectable with a slide switch
mounted on the rear of the chassis. A
power distribution board is installed in
the chassis to allow easy connection to
all peripheral bays through six plugs
mounted on the power distribution
board.
The chassis has been fully tested to
ensure low-audible noise emission,
resistance to electrostatic discharge and
resistance to appropriate levels of
vibration and shock in both office and
, industrial environments.

Physical Parameters

...-::-:-::------.----:-----,
Voltage
Current
r--+-5~V~-r--7~5~A--~

+12V
-12V
Designed to meet:

auxiliary backplane, on the other
hand, provides direct high speed
interconnection between a processor
board and memory boards. It contains
three iLBX slots. One of these slots has
a IO-pin BITBUS connector that serves
as a serial interface for any iSBX 344
BITBUS controller board installed in
the system. This cardcage conforms to
the published MULTlBUS II
specification.

lOA
2.5A

UL 478
CSA C22.2 No. 154
FCC Class B
VDE Level B
IEC 435

Height: 7.75" (19.7 cm)
Width:
17.5"(44.5cm}
Depth: 22.25" (56.5 cm)
Weight: 33 Ibs. (15 kg.)

Bay Dimensions
3.5" wide x 6"high x 8.5" deep

Acoustical Noise
Less than 50 dbA in office environment (30°C)

Electrostatic Discharge

Operational Parameters

No hard errors to 12.5 kV

AC Power Input: 90-132 VAC or
180-264 VAC at 47-63 Hz
Operating Temperature Range: 10°C to 55°C
Storage Temperature: -40°C to 60°C
Operational Humidity: 10% to 85% relative,
non-condensing

Contents
• 8-slot MULTIBUS II Chassis
• Power cord
• User's guide
• Two keys
• Peripheral mounting brackets & power cables

Ordering Information
SYP 500

14-9

inter
•

•
•

iSBC® CSM/001
CENTRAL SERVICES MODULE

iSBC® CSM/001 Central Services
Module Integrates MULTIBUS® II
Central System Functions on a Single
Board
MULTIBUS® II Parallel System Bus
Clock Generation for all Agents
Interfaced to the MULTIBUS II iPSB Bus
System~wide Reset Signals for Powerup, Warm Start, and Power Fallurel
Recovery

System-wide Time-out Detection and
Error Generation
Slot 1.0. and Arbitration 1.0.
Initialization

•

MULTIBUS II Interconnect Space for
Software Configurability and
Diagnostics

•

Built-In Self Test (BIST) Power-up
Diagnostics with LED Indicator and
Error Reporting Accessible to Software
via Interconnect Space

•
•
•

General Purpose Link Interface to
Other Standard (MULTIBUS I) or
Proprietary Buses
Tlme-of-day Clock Support with Battery
Back-up on Board
Double-high Eurocard Standard Form
Factor, Pin and Socket DIN Connectors

The iSBC CMS/001 Central Services Module is responsible for managing the central system functions of clock
generation, power-down and reset, time-out, and assignment of I.D.s defined by the MULTIBUS II specification. The integration of these central functions in a single module improves overall board area utilization in a
multi-board system since these functions do not need to be duplicated on every board. The iSBC CMS/001
module additionally provides a time-of-day clock and the general purpose link interface to the other standard
(MULTIBUS I) or proprietary buses.

280070-1

14·10

November 1986
Order Number: 280070-002

inter

iSBC CSM/001 MODULE

FUNCTIONAL DESCRIPTION
Overall
The iSBC CMS/001 Central Services Module integrates MUlTIBUS II central system functions on a
single board. Each MUlTIBUS II system requires
management of these central system functions as
defined in the MUlTIBUS II specification. Figure 1
illustrates a typical multiprocessing MUlTIBUS II
system configuration. To perform its central system
functions, the iSBC CSM/001 Central Services Module has a fixed slot 1.0. and location in the backplane. The iSBC CSM/001 board additionally provides an interface to the MUlTIBUS I Link board and
a time-of-day clock.

Architecture
The iSBC CSM/001 board is functionally partitioned
into 6 major subsystems. The.Central System Wide
Control subsystem includes MUlTIBUS II iPSB bus
clock generation and system wide reset signal generation. The Time-Out Control subsystem provides

system wide time out detection and error generation.
The System Interconnect Space subsystem controls
1.0. initialization and software configurable interconnect space. The Link Board interface subsystem
provides an interface to the MUlTlBUS I Link board
or links to other buses. The last two subsystems are
of the Time-of-Day clock and the iPSB bus interface.
These areas are illustrated in Figure 2.

CENTRALIZED SYSTEM-WIDE
CONTROL SUBSYSTEM
Parallel System Bus Clock Generation
The CSM generates the Parallel System Bus clocks.
The Bus Clock (BClK*) 10 MHz signal and the Constant Clock (CClK*) 20 MHz signal are supplied by
CSM to all boards interfaced to the Parallel System
Bus. These boards use the Bus Clock 10 MHz signal
for synchronization, system timing, and arbitration
functions. The Constant Clock is an auxiliary clock.
The frequency of the Bus Clock and Constant Clock
can be halved via jumpers for diagnostic purposes.

BITBUS'·

280070-2

Figure 1. Typical MULTIBUS® II System Configuration

280070-3

Figure 2. Block Diagram of iSBC® CSM/001 Board

14-11

inter

ISBC CSM/001MODULE

Reset Control and Power-Faill
Recovery
The CSM sends a system-level reset/initialization
Signal to all boards interfaced to the Parallel System
Bus. The CSM assigns slot 1.0. and arbitration 1.0: to
these boards during this initialization process. It pro"
vides this signal upon pressing of the reset switch,
restoration of system power or a software request
for reset received .via the CSM interconnect space.
The reset switch may be jumper-configured to cause
a power-up or warm reset, with cold reset the default
configuration. The reset switch is ,located on the
front panel. Addition~lIy, warm reset and cold reset
signals can be input through the P2 connector.
TheCSM .power supply interface' is' accomplished
via the ACLO input of the P2 connector. ACLO is an
open' collector input from the power supply which
provides advance warning of imminent power fail. If
battery backup is not required, a jumper is provided
on the CSM to disable the power fail signal ACLO.

TIME-OUT SUBSYSTEM
The TIMOUT* (Time-Out) signal is provided by the
CSM whenever it detects the failure of a module to
complete a handshake. This TIMOUT* signal is re¥6ive,d by all boards interfaced (0 the iPSB bus and
may be disabled via the interconnect space.

INTERCONNECT SUBSYSTEM
The CSM Interconnect subsystem provides arbitration 1.0., and slot 1.0. initialization, software configurable interconnect space, and on-board diagnostics
capability.

type, so that this"informationis available to the system software. The CSM software configurable interconnect space allows w~ite operations to support
board configuration and diagnostics under software
control. The CSM also uses interconnect space for
system wide functions such as providing a time/date
record (from time-of-day, clock), software access to
diagnostics and software control of the system wide
functions.

BUILT-IN-SELF-TEST (BIST)
DIAGNOSTICS
Self-test/diagnostics have been built into the heart
of the MULTI BUS II system. These confidence tests
and diagnostiCS improve reliability and reduce manufacturing and maintenance costs. LED 1 (labeled
BIST) is used to indicate the status of the Built-InSelf-Test. It is turned on when the BIST starts running and is turned off when the BIST completessuccessfully.' In addition, all error information is recorded in interconnect space so it is accessible to software for error reporting.
The Built-In-Self-Tests performed by the on-board
microcontroller at power-up or at software command
are:
1. PROM Checksum Test-Verifies the contents of
the 8751 microcontroller.
2. RAM Test-Verifies that each RAM location of
the 8751microcontroller may store O's and 1's by
complementing and verifying twice each RAM location.'
'
3. Real Time Clock Chip RAM Test-Verifies that
reads and writes to the RAM locations on Real
Time Clock Chip are functional.
4. Real Time Clock Test-Reads and writes all RAM
locations of the RTC chip. Not run
power-up
due to destr'uctivenature..

At reset, the CSM supplies each board interfaced to
iPSB bus with its slot 1.0. and its arbitration 1.0. The
slot I. D. assignment allows user or system software
to address any board by its physical position in the
backplane.

.5. Arbitration/Slot 1.0. Register Test-Verifies that
arbitration and slot.I.D.s can be read and written
from on-board.

The interconnect space has both read-only and, software configurable facilities. The read-only registers
hold information such as vendor number and board

S. 8751 Status Test-Verifies that input pins of the
8751 are at correct level.
7. Clock Frequency Test-Tests accuracy of Rea):
Time Clock to 0.2% against bus clock.

14-12

inter

iSBC CSM/001 MODULE

CSM LINK INTERfACE
The CSM Link Interface and the MULTIBUS I iSBC
LNK/001 board provides a bridge between MULTIBUS I and MULTIBUS II systems. Hybrid systems
can be built for development or target. The CSM
Link Interface uses the P2 connector on the iSBC
CSM/001 module for transferring commands and
data from MULTIBUS II to a MULTIBUS I Link board.
The MULTIBUS I Link board (iSBC LNK/001) is purchased separately from the iSBC CSM/001 board
and includes the cable which connects the iSBC
CSM/001 board and the MULTIBUS I Link board
(see Figure 3).

and provides a memory and 1/0 access window to
MULTIBUS I from the MULTIBUS II Parallel System
Bus. Only one iSBC LNK/001 board can be connected to the iSBC CSM/001 module.

TIME-Of-DAY CLOCK SUBSYSTEM
The Time-Of-Day Clock subsystem consists of a
clock chip, battery, and interface circuitrY. The clock
provides time keeping to 0.01 % accuracy of fractions of seconds, seconds, minutes, hours, day, day
of week, month, and year. This information is accessible via the interconnect space. The battery backup for the clock chip provides 2 years of operation.

The CSM Link Interface supports 8- or 16-bit transfers via a 16-bit addressl data path. The iSBC
LNK/001 board resides in the MULTIBUS I system

280070-4

Figure 3. ISBC® CSM/001 Link Interface

SPECifiCATIONS

Link Cable

System Clocks

The Link cable uses a 64-conductor ribbon cable for
interconnecting the CSM board to the Link Board.
The maximum length for the cable is 1 meter.

BCLK* (Bus Clock)
CCLK* (Constant Clock)
LCLK* (Link Clock)

10MHz
20 MHz
10 MHz

Interface Specifications
Location

Function

P1
P2

iPSB Bus
Link and Remote
Services

Jumper option available to divide these frequencies
in half

Interface Compliance
MULTIBUS
(#146077)

Bus

Architecture

Specification

14-13

Part #
603-2-1 EC-C096F
603-2-IEC-C064-F

intJ

. iSBC CSM/001 MODULE

PHYSICAL DIMENSIONS

BATTERY CHARACTERISTICS

The iSBCCSM/001 board meets all MULTIBUSII
mechanical specifications as presented in the MULTIBUS II specification (#146077).

3V nominal voltage; capacity of 160 milliamp hours
minimum.

Double-High Eurocard Form Factor:

BATTERY DIMENSIONS

Depth:
220 mm. (8.7 in.)
Height:
233 mm. (9.2 in.)
Front Panel Width: 20 mm. (0.78 in.)
Weight:
4820 gm. (16.5 oz.)

Outside dimension
Height

20 mm~23 mm
1.6 mm-3.2 mm

REFERENCE MANUALS
iSBC CSM/001 Board Manual (#146706-0Q1)

ENVIRONMENTAL REQUIREMENTS
'·ntel MULTIBUS II Bus Architecture Specification
(#146077)

Temperature: (inlet air) at 200 LFM airflpw over
boards
Non-operating: - 40 to + 70°C
Operating:
0 to +55°C
Humidity:
Non-operating: 95% RH @ 55°C
Operating:
90% RH @ 55°C

ManualS may be ordered from any Sales Representative, Distributor Office, or from the Intel Literature
DePll.rtment, 3065. Bowers Ave., .Santa Clara, CA
95051.

POWER REQUIREMENTS

ORDERING INFORMATION

Voltage (volts)

Current (amps)

+5
. +5VBB

6A(max.)
1A (max.)

Part Number
iSBC CSM/001

14-14

Description
MULTIBUS II. Central Services
Module

intJ

iSBC® LNK/001 BOARD
MULTIBUS® II TO MULTIBUS® I LINK BOARD

II Development Vehicle Making

1/0 Mapped
into MULTIBUS® II 1/0 Space
Configurable from MULTIBUS® II
Interconnect Space

II ·32K Bytes of MULTIBUS® I

MULTIBUS® I ISBC® Boards Accessible
to MULTIBUS® II Board Designers
II On Board 128K Byte Dual Port DRAM

Memory

II Conversion of MULTIBUS® I Interrupts

to MULTIBUS® II Interrupt Messages

II 16M Bytes of MULTIBUS® I Memory

.Mapped Into MULTIBUS® II Memory
Space Configurable from MULTIBUS® II
Inter.connect Space

.. MULTIBUS® I Form Factor Board
II Connects to MULTI.BUS® II Central

Services Module (ISBC CSM/001 Board)
via a 3 Foot Flat Ribbon Cable

The iSBC LNK/001 board maps MULTIBUS I memory and 1/0 space into the MULTIBUS II iPSB bus and
converts MULTIBUS I interrupts into MULTIBUS II interrupt messages. Up to 16M Bytes of MULTIBUS I
memory and up to 32K Bytes of MULTIBUS 11/0 is addressable from MULTIBUS II through the iSBC LNK/001
board. Additionally, 128K Bytes of dual port DRAM memory resides on the iSBC LNK/001 board for use by
both MULTIBUS I and Ml.JLTIBUS II systems. MULTIBUS II OEM product designers can now speed hardware
and software development efforts by using the iSBC LNK/001 board to access standard or custom MULTI.
BUS I products.

280135-1

14-15

November 1988
Order Number: 280135-1102

inter

iSBC® LNK/001

GENERAL DESCRIPTION
The iSBC LNK/001 board makes MULTIBUS I products accessible to MULTIBUS II designers. The
iSBC LNK/001 board resides in the MULTIBUS I
system and connects to the Central Services Module (iSBC CSM/001 board) via a 3 foot flat ribbon
cable. The ribbon cable connects the P2 connector
of the iSBC LNK/001 board to the P2 connector on
the Central Services Module. The iSBC LNK/001
board supports:
a. 128K Bytes of Dual Port DRAM,
b. 16- and 24-bit addressing into 16M Bytes of MULTIBUS I memory with 8- and 16-bit data paths,
c. 8- and 16-bit addressing into 32K Bytes of MULTIBUS I I/O with 8- and 16-bit data paths,
d. MULTlBUS I interrupt to MULTIBUS II interrupt
message conversions of up to eight levels of non
bus-vectored interrupts via an 8259A programmable interrupt controller, and

. MULTIBUS I system. A MULTIBUS II agent requesting a memory transfer involving the iSBC LNK/001
board is directed through the CSM to the iSBC
LNK/001 Dual Port memory or a MULTIBUS I slave.
If the access address is within the MULTIBUS II Dual
Port window, the transaction is acknowledged by the
iSBC LNK/001 board and returned to the MULTIBUS II iPSB through the CSM. In the event the address is outside the MULTIBUS II Dual Port window,
the transaction is directed to the MULTIBUS I system. Here the iSBC LNK/001 board enters arbitration for the MULTIBUS I system bus to complete the
requested transaction. Once the iSBC LNK/001
board is the owner of the MULTIBUS I system bus,
data is transferred to or from the iSBC LNK/001
board/Central Services Module connection. The
MULTIBUS I slave acknowledges the transfer and
the iSBC LNK/001 board passes the acknowledge
on through the Central Services Module to the MUL~
TIBUS II iPSB.

e. initialization tests and Built-In-Self-Test (BIST) using interconnected address space.

MULTIBUS II 110 operations are always directed to
the MULTIBUS I I/O slaves and consequently require arbitration for the MULTIBUS I system bus.

APPLICATIONS

INTERCONNECT MAPPING

The primary application of the iSBC LNK/001 board
is in the design development environment. The iSBC
LNK/001 board allows designers to start their devel~
opment efforts by leveraging existing MULTIBUS I
products or to begin modular design efforts and preserve investments in custom products. In either
case, the use of leverage with existing MULTIBUS I
hardware and software allows· designers to begin
their MULTIBUS II product designs,

The function record of the iSBC LNK/001 board, a
function record within the Central Services Module
interconnect template, appears as a board within a
board (see Table 1). The actual iSBC LNK/001
board configuration is done through unique interconnect registers using the same slot ID as the Central
Services Module. The iSBC LNK/001 function record begins at an offset of 256 from the start of the
CSM template and the EDT (End Of Template) byte
is attached as the last function of the iSBC LNK/001
function record.

MEMORY AND I/O READ/WRITE
SEQUENCE
The iSBC LNK/001 board establishes a master/
slave relation between a MULTIBUS II system and a

Dual Port 128K Byte DRAM Memory
A dynamic RAM Dual Port,. resident on the iSBC
LNK/001 board, provides a 128K Byte media for

MULTIBUS' I

SYSTEM BUS

280135-2

Figure 1. Sequence Diagram
14-16

iSBC® LNK/001

MULTIBUS I and MULTIBUS II agents to pass data
efficiently. With both buses sharing the Dual Port
memory the need for the MULTIBUS II system to
continuously arbitrate for MULTIBUS I system access is eliminated. Consequently, each bus can continue operating at its respective speed when accessing the iSBC LNK/001 Dual Port memory.

MULTIBUS® I Memory Addressability
The MULTIBUS I system views the iSBC LNK/001
Dual Port as a contiguous 128K Byte memory block
mapped into the 16M Bytes of MUL TlBUS I memory
address space starting at the Dual Port Start Ad-

dress register value. This memory block, configurable on any 64K Byte boundary within the MULTIBUS
I memory address space, is set via interconnect accesses to the iSBC LNK/001 function records from
the MULTIBUS II system (see Table 1). The first
16M Bytes of MULTIBUS II memory space can be
mapped in the 16M Bytes of MULTIBUS I memory
address space (see Figure 3).

MULTIBUS® 11/0 Addressability
Up to eight 4K Byte blocks of MULTIBUS II 110
space can be mapped into MULTIBUS I 1/0 space

Table 1. Function Record Overview iSBC® LNK/001 Board
Offset

Description

Offset

Description

0-255

iSBC CSM/001 Header and
Function Record
Board Specific Record Type
Record Length
Vendor 10, Low Byte
Vendor 10, High Byte
Link Version Number
Hardware Revision Test Number
Link General Status
Link General Control
Link BIST Support Level
Link BIST Data In
Link BIST Data Out
Link BIST Slave Status
Link BIST Master Status
Link BIST Test 10
MBI Dual Port Start Address

271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288

MBI Dual Port End Address
MBII Dual Port Start Address
MBII Dual Port End Address
MBII Memory Start Address
MBII Memory End Address
1/0 4K Segment Control
MBllnterrupt Enable
Link Interrupt 0 Destination Address
Link Interrupt 1 Destination Address
Link Interrupt 2 Destination Address
Link Interrupt 3 Destination Address
Link Interrupt 4 Destination Address
Link Interrupt 5 Destination Address
Link Interrupt 6 Destination Address
Link Interrupt 7 Destination Address
Interrupt Source Address
Link Status Register
EOT (End of Template)

256
257
258
259
260
261
262
263
264
265
266
267
268
269
270

MULTIBUS"'U

'"::::>
III

LINK

BUS AND

MESSAGE
CONTROL
LOGIC

DUAL

PORT
RAM
L -______

!;;:
1----'0
1---, ~
~

'"
280135-3

Figure 2. Link Board Dual Port Drawing
14-17

intJ

ISBC® LNK/001
which the interrupt message is being sent. Each of
the eight MULTIBUS I interrupt lines can be programmed to generate a unique MULTIBUS II .destination address. These destination addresses are initialized through interconnect space by programming
the iSBC LNK/001 Interrupt Destination Address
Registers. The message source address is also configurabie via interconnect space by writing to the Interrupt 0 Source Address Register with a base value.
Once the base value of source Address 0 is established, Source Address 1 through 7 are set for incrementing values by the 8751A interconnect processor. The iSBC LNK/001 board recognizes MULTIBUS II Negative Acknowledge agent errors
("NACK") and performs an automatic retry· algorithm .

MULTIBUS" II
4GB

MULTIBUS~

16MB! - - - .-....--"'1 ·16MB

DUAL
PORT

DUAL

.-..,..,~,... PORT

---_"""''''''''''''''''''0

MEMORY MAPPING
..lII"T.~~84KB
..

32KB.~.

Initialization Tests and BIST

-r---,32KB
",/'

Self test and diagnostics have been built into the
MULTIBUS II system. The BIST LED is used to indicate the result of the Built-In-Self-Test and turns on
when BIST starts running and turns off when it has
successfully executed. BIST test failure information
is recorded in the interconnect sPace and is accessible to software for error reporting.

. /'

o
1/0 MAPPING

280135-4

Figure 3. MULTIBUS® I Memory
and 1/0 Mapping Diagram
(see Figure 3). MULTIBUS 111/0 accesses must be
from 32K Byte to 64K Byte in order to be mapped
into MULTIBUS I 1/0 address space. These blocks
are specified through an interconnect access to the
"1/0 4K Segment Control" register (see Table 1).
Each bit in the register represents a 4K Byte block of
110 addresses. When a bit (or bits) is set,. the 4K
Byte block of MULTIBUS II 1/0 space represented
by that bit will be c::iedicated to MULTIBUS I 110
space.

Interrupt to Message Conversion
As the iSBC LNK/001 board receives non-bus vec.
tored interrupts from the MULTIBUS I system, the
on·board 8259A programmable interrupt controller
(PIC) prioritizes theMULTIBUS I interrupts and initiates the MULTIBUS II unsolicited interrupt message
generation process. Up to 8 levels of non-bus vectored interrupts are supported by the iSBC LNK/001
board.
The iSBC LNK/001 board generates the MULTIBUS
II interrupt messages and is the Interrupt Source.
The iSBC LNK/001 board is assigned a Source ID
through interconnect space when the MULTIBUS II
system is powered up or when the user programs
the source ID register via interconnect space. The
Interrupt Destination is the MULTIBUS II· board to

PHYSICAL CHARACTERISTICS
Form Factor
The iSBC LNK/001 board is a MULTIBUS I form factor board residing in a MULTIBUS I system. Physical
.dimensions are identical to all standard MULTIBUS I
boards.

Connection to MULTIBUS® II Bus
The iSBC LNK/001 board connects to the iSBC
CSM/001 board in the MULTIBUS II system via a 60
pin conductor flat ribbon cable. The physical con~
nection is made on the P2 connector of both the
iSBC LNK/001 board and the iSBC CSM/001 board.
. The cable termination requirements and DC requirements for the signal drivers and receivers are detailed in the iSBC CSM/001 USERS GUIDE, Section
6.6.4. The maximum length of the cable is 3 feet.
The cable and the connectors are shipped unassembled to allow user flexibility.

SOFTWARE SUPPORT
To take advantage of iSBC LNK/001 Dual Port architecture, existing software device drivers may require modification. Device driver changes depend on
the specific application and vary in complexity de~
pending upon the device driver.

14-18

inter

ISBC® LNK/001

ENVIRONMENTAL REQUIREMENTS

SPECIFICATIONS

16- and 24-bit Address Paths
8- and 16-bit Data Paths
Block transfers are not supported

Temperature: Inlet air at 200 LFM airflow over
boards
'
Non Operating: -40°C to + 75°C
Operating: O°C to + 55°C
Non Operating: 0 to 95% RH @ 55°C
Humidity:
Operating: 0 to 95% RH @ 55°C

Cable Characteristics

POWER REQUIREMENTS

The cable is a 60 pin conductor flat ribbon cable with
a maximum length of 3 feet. The P2 connector to the
iSBC LNK/001 board is a 30160 pin board edge
connector with 0.100" pin centers, KEL-AM Part
Number RF30-2853-5. The connector to the P2 DIN
connector on the iSBC CSM/001 board is 3M Part
Number 3338-000.

Voltage: + 5V
Current: 7.14 Amps

Word Size

REFERENCE MANUALS
iSBC LNK/001 Users Guide (#148756-001)
Intel MULTIBUS II Bus Architecture Specification,
Rev C (# 146077)

Interface Specifications
Location

Function

P1
P2

MULTIBUS IEEE 796 System Bus
Cable connection to P2 connector of
iSBC CSM/001 board

PHYSICAL DIMENSIONS
The iSBC LNK/001 board meets all MULTIBUS I
mechanical specifications as presented in the MULTIBUS I specification.

iSBC CSM/001 Users Manual (#146706-001)
Manuals may be ordered from any Sales Representative, Distributor Office, or from the Intel Literature
Department, 3065 Bowers Ave., Santa Clara, CA.
95051.

ORDERING INFORMATION
Part Number

Description

iSBC LKN/001

MULTIBUS II to MULTIBUS I iSBC
LNK/001 Interface Board

Depth: 17.15cm (6.75 in.)
Height: 1.27 cm (0.50 in.)
Front Panel Width: 30.48 cm (12.00 in.)
Weight: Estimated 565 g (20 oz.)

14-19

MULTIBUS® II
HIGH PERFORMANCE SBC
GENERAL PURPOSE TEST FIXTURE (GPTF)
•

Single Board Computer Tester for
MULTIBUS® II Boards in a Systems
Environment

•

Tests up to Four MULTIBUS II. Boards
Simultaneously in a Range from
Ambient Temperature to 70°C ,
- Voltage and Temperature Margins
are Software Controlled

•

Multiprocessor, Multitesting Functional
Tester with Totally Automated Test
Sequence, Requiring Minimum Human
Intervention

•

Powerful Command Language for
Troubleshooting and Evaluation

•

One STBL (System Test Board Level)
Test is Included. Additional Test
Programs are Available for Intel
MULTIBUS II Boards

•

GPTF Includes Video Monitor for Error
Message Display and Status of Testing,
Also, a Comprehensive Installation
Guide and Users Manual

• 'Bus Drawer Feature on P2 Connector
Allows User Flexibility to Test Boards
with Different Types of P2 Interfaces
•

Available in Either USA, Japan or
International Power Configuration

•

Safety. Features Including Thermal Cut
Out at 90°C

280189-1

14-20

October 1988
Order Number: 280189-002

MULTIBUS® II GPTF

TESTER OVERVIEW
The MULTIBUS II General Purpose Test-Fixture
(MULTIBUS II GPTF) is a state-of-the-art high performance tester used to test MULTIBUS II boards in
a typical systems environment. The System Test
Board Level or STBL, as it is usually referred to, is
done using the MULTIBUS II GPTF. The STBL is
used to validate that the iSBC board will perform in a
system environment under a variety of temperature
and voltage conditions. The MULTIBUS II GPTF is a
fully automated tester .with minimum operator intervention required. It can test from one to four boards
of the same type at a time. A full range of keyboard
commands are available for troubleshooting. The
human interface is through the Front Panel and the
CRT terminal. The MULTIBUS II GPTF requires the
use of a Televideo 955 terminal which is included
with the GPTF order.
The users manual is written at the operator's level
and thus does not require a technician to perform
tests. The users manual is written in two parts; operator's instructions and technician's troubleshooting
section. An installation guide is also furnished.
The MULTIBUS II GPTF does not require any special Test EPROMs to do the STBL. The STBL can
be loaded and stored in the hard drive using either
the floppy drive or downloaded from an Intel Series
III Development System. Once the STBLs are loaded into the hard drive, reconfiguration time (when
testing different types of boards) is typically limited
to exchanging the bus drawer. The STBLs for the
most part use the Built-In Self Tests (BISTs) which
are part of the MULTIBUS II Board Product Firmware, to test the Unit Under Test (UUT).
The MULTIBUS II GPTF adheres to MULTIBUS II
architecture and follows the Intel Interconnect Interface Specification (liS) and the Intel Initialization and
Diagnostics eXecutive (IDX).

HARDWARE OVERVIEW
The MULTIBUS II GPTF is uniquely designed for
ease of maintainability with three enclosures. The
front enclosure is the heat chamber that houses the
UUTs. Behind the heat chamber are the two computer systems; the Test Computer System and the
Control Computer System. Each system has its own
power supply.
The Test Computer System, which is MULTIBUS II
based, is located immediately behind the heat chamber. It is the slave system to the Control Computer
System. Its function is to perform the testing and
report test status back to the Control Computer System. The Test Computer System contains three
HOST MULTIBUS II boards which always reside in
the GPTF.

The Hot Box Test Chamber has slots for testing
one to four UUT's simultaneously. Both the + 5V
and temperature can be varied by the Control Computer (or the user) to test the boards in a worst case
condition. The + 5V voltage can be margined
± 10%, and the temperature can be raised from
room temperature to 70°C.
The Control Computer System is located in the
rear of the GPTF and is a MULTIBUS I based system. Its function is to control and manage the Test
Computer System. This system controls the AC
power to the Test Computer System, has the capability to margin the DC voltages to the UUT, controls
the heat chamber heater coils, reset and interrupt
lines to the iSBC CSM/001 board, and controls the
I/O to the CRT video display, front panel, and the
secondary storage. The Control Computer contains
an 8-slot MULTIBUS I backplane and five iSBC
boards.
The secondary storage consists of a 3.5" , 40 Mbyte
winchester hard drive and a 5.25", 48 TPI floppy
drive. Both iRMX86TM and PC-DOSTM format floppy
diskettes can be used. The hard drive and the floppy
drive are controlled by the Intel iSBC 214 Peripheral
Controller board. Additional 3.5" and 5.25" Peripheral Controller board. Additional 3.5" and 5.25" peripheral bays are designed in for future Intel use.
Variable P2 Interface capability in the MULTIBUS II
architecture allows for variable use of the P2 connector on iSBC boards. The iLBXTM II connector is
used on some boards, like the iSBC 286/100 and
the iSBC MEM/3XX boards, SCSI is used on boards
like iSBC 386/258 etc. The MULTIBUS II GPTF has
the bus drawer feature in the Test Computer System
to support the variable P2 interface. Each bus drawer is designed for a specific P2 interface. For example, the CODE1 bus drawer, shipped with the GPTF,
supports iLBX II. The bus drawers are easy to install-slide it in and tighten the two thumb screws.
Only two types are shipped with the product. All the
parts of the bus drawer are generic except the P2
connector itself. Each bus drawer is coded so that it
can be recognized by the STBL software.

SOFTWARE OVERVIEW
The MULTIBUS II GPTF runs on iRMX 86 software
specially configured for the GPTF. The operating
system resides on the hard drive Control Computer
System. The DIR command will assist in locating the
various directories on the hard drive.
The Tester Control Program (TCP), also iRMX 86based Operating System, resides on the hard drive
and runs on the Control Computer System (iSBC

14-21

inter

MULTIBUS® II GPTF

186/51 board). The TCP resembles a mini operating
system. It supports a range of keyboard commands
which are useful to run STBL and to troubleshoot
suspect boards. A set of ten command strings can
be stored in the STBL software and may be invoked
at run time by the operator.
USing,TCP commands, the operator can control the
functions of the GPTF. TCP also responds to the
front panel buttons,(START & QUIT) thus, making
the GPTF automated. The CRT displays dedicated
fields to indicate corresponding status of the testing
such as: UUT board ID, UUTpower supply status,
voltage margin as percent of nominal voltage, and
slot location of UUT.
The TCP operates in two modes, PRODUCTION
TEST MODE (default)· and TROUBLESHOOTING
MODE. These modes allow the GPTF to be operat·
ed in a fully automated mode or a manually con·
trolled mode. The PRODUCTION TEST MODE is
turned off while troubleshooting with. just a simple
keyboard command.
The TCP works in conjunction with the firmware on
the Host CPU board in the Test Computer System.
The firmware'is usually referred to as Host Firmware
(HFW). Apart from communicating with the TCP, the
HFW is an implementation of the Master Test Hand·

ler, as defined in the IDX. The Host firmware under
the control of the TCP performs the testing of the
UUTs.
The STBL can have tests of three different types.
TYPE 1 tests run on the HOST only, TYPE 2 tests
run on UUT only and TYPE 3 tests have both UUT
and HOST code and can run on both. When testing
more than one UUT, the TYPE 2 tests are executed
in parallel by the UUTs. A given STBLcan have any
mixture of these three types of tests.

TESTER BLOCK DIAGRAM
Figure 1 shows a block diagram of the tester, in a
level of detail sufficient to understand basic tester
operation. The top of the sketch shows the MULTI·
BUS II system where testing takes place. On the left
are the UUT slots, and on the right the host boards.
Both iPSB and iLBX II busses are shown. The iLBX II
backplane is physically installed in a removable bus
drawer. Important communication paths shown are:
a fast parallel path between host processor and con·
trol computer, and serial channels to the terminal
and Series III development system. Details omitted
for clarity include the heaters; most cabling; temper·
ature sensors; + 5B and heater relays.

.-"

TELEVIDEO
950

SERIES III

I
I

DEVELOPMENT

AND :y~~;~OAD

I
I

OPERATOR'S

TERMINAL

IL __

CONTROL COMPUTER

TERMINAL CABLE _ REQUIRED FOR OPERATION
_____________

DOWNLOAD CABLE -

________

I
I
I

REaUIRED FOR DOWNLOAD ONLY

280189-2

Figure 1. Tester Block Diagram

14-22

MULTIBUS® II GPTF

SPECIFICATIONS
Size:
25" W x 38" D x 24.5" H
Weight: 90 Ibs.
Power Ratings

USA Units

International Units

Japan Units

Nominal Voltage Rating
Current Rating
Frequency Rating

110 volts
30 amperes
60 hertz

220 volts
15 amperes
50 hertz

100 volts
30 amperes
50/60 hertz

HEATER COIL RATINGS

FUSE RATINGS
Power Ratings

USAIJapan

International

Power Ratings

USA/Japan

International

F1-Heater Coil
1 Fuse
F2-Heater Coil
2 Fuse
F3-MULTIBUS I
Power Supply Fuse
F4-MULTIBUS II
Power Supply Fuse

10A @250V

5A@250V

Heater Coil 1
Heater Coil 2

1000W 110V
660W 110V

1000W220V
660W 220V

6A@ 250V

3A@ 250V

7A@ 125V

4A@250V

15A@250V

10A@ 250V

Heater Coil 1 is to your right when you face the GPTF.

POWER SUPPLY RATINGS
Power Ratings

1. Control Computer System Power Supply
2. Test Computer System Power Supply

USA/Japan

International

'Input V

OutputW

Input V

OutputW

90-132V
90-132V

220W
750V

180-264V
180-264V

220W
750W

·"Input V" is the input voltage and the "Output W" is the output power.

POWER PLUGS
USA-The MULTIBUS II GPTF comes with a factory
installed power plug which is a TWIST LOCK 30A,
125V PLUG.
INTERNATIONAL AND JAPAN-The MULTIBUS II
GPTF is shipped WITHOUT a power plug because
of the varied nature of the power outlets in other
countries. CHOOSE A PLUG WHICH MEETS THE
ELECTRICAL REQUIREMENTS OF THE TESTER.
The GPTF is rated at 15A for INTERNATIONAL use
and 30A for JAPAN.

The power outlet should be of proper rating. THIS
APPLIES TO BOTH USA AND INTERNATIONAL
UNITS. PLEASE USE THE FOLLOWING GUIDELINES:
INTERNATIONAL-A 15A drop with a receptacle of
equivalent rating.
USA AND JAPAN-A 30A drop with a receptacle of
equivalent rating.

14-23

MULTIBUS® II
Architecture

MULTIBUS® II
iPSB PARALLEL SYSTEM BUS
Arbitration with Up to 20
• Distributed
Bus Masters

1296 Industry Standard Bus
• IEEE
Bandwidth
• -Very40 High
Megabytes/Sec Using Burst

Parity Protection for Data Transfer
• Full
Integrity
Message Passing Facility for
• Intermodule
Communication

Transfers
- 20 Megabytes/Sec with Single
Cycles
(32-bit) Addressing
• 8-,4 Gigabyte
24-, and 32-bit Data Transfers
• over16-,a 32-bit
Path

Addressing Facility for
• Geographic
Software Indentification and
Configuration of Boards

Multiplexed Structure
• Pin-Efficient
Reliable Synchronous Clocking at 10
• Megahertz with Full Handshaking for

Standard Eurocard Form
• Industry
Factors-233 mm x 220 mm and
100 mm X 220 mm

Data
The MULTIBUS " iPSB Parallel System Bus is the foundation of the MULTIBUS " Bus Architecture. It is a
general-purpose, processor independent structure which fully supports 8-, 16-, and 32-bit microprocessors.
This very high bandwidth structure is defined on a single 96-pin lEG 603-2 (DIN) connector. All data movement
functions required in a microcomputer system are defined including such advanced functions as an integrated
message passing protocol and a geographic addressing facility which allows software to address a board by
its slot position for software-based board identification and configuration.

280387-1

MULTIBUS® II Physical Diagram

15-1

September 1987
Order Number: 280387-002

MULTIBUS® II SYSTEM BUS

FUNCTIONAL DESCRIPTION

Structural Features

Architectural Overview

OVERVIEW
The iPSB bus structure is a processor-independent
general-purpose bus designed to support 8-, 16-,
and 32-bit processors. It is designed to operate at a
maximum bandwidth of 40 megabytes/sec while using off-the-shelf components.

The MULTIBUS II iPSB Parallel System Bus is the
foundation of the MULTIBUS II bus architecture (see
Figure 1). As a system bus, it is a very high bandwidth (40 megabytes/sec) bus optimized for intermodule communication; however, it also defines tlJe
complete set of basic bus functions required in a
microcomputer system: memory accesses for execution of data, accesses to I/O for control of I/O
functions, plus intermodule signalling. These basic
functions are supplemented with additional functions
supporting geographic (by slot) addressing and an
integral message passing protocol.

Special attention has been given to how the bus
structure, both electrically and mechanically, impacts system reliability. Synchronous sampling of all
bus signal lines assures good immunity from crosstalk and noise. Full byte parity generation and
checking protects all transfers on the bus to ensure
that any bus error is detected. Signal quality on the
bus is excellent due to the large number of interlaced ground lines. Mechanically, the iPSB bus is
defined on a two-piece 96-pin lEG 603-2 connector
to ensure good connector reliability.

Geographical addressing allows addressing of individual boards via their physical position in the backplane. Software can determine what boards are being used and configure itself appropriately. SoftWare
also can configure the hardware characteristics of
the board (e.g., the starting address of a memory
board). This can substantially reduce or even eliminate hardware jumper options and DIP switches for
board configuration. Geographical addressing is a
function ofthe interconnect address space.

MULTIPLEXING
The iPSB bus is highly multiplexed. The 32-bit address and data paths are multiplexed and the eight
system control lines have different uses depending
upon the phase of the transfer cycle. The six arbitration lines also serve dual purposes between system
initialization and normal operation.

MULTIBUS II's integral message passing protocol
defines a standard and uniform way for modules to
communicate over either the iPSB or iSSB buses.
Integrating the protocol at the bus structure level
lets the designer provide hardware support to increase system inter-module communication performance and opens the door for VLSI solutions.
Standardizing the interface ensures a uniform software interface so that users can take advantage of
new advances in technology without having to rewrite software.

This multiplexed structure has several benefits. The
entire 32-bit iPSB bus is defined on a single connector. This allows a full 32-bit iPSB bus interface on
even the smaller, single connector, form factor
board and opens the possibility of low cost 32-bit
systems. Multiplexing also reduces by half the number of high current drivers required for the interface

ISBX" BUS (10MBpB)

¢><>
ISac·

ISac·

MEMORY

ISBC·

BOARD

ILBPII BUS
(48MBps)

IPSB (40MBps)

280387-2

Figure 1. MULTIBUS@ II Bus Architecture

15-2

intJ

MULTIBUS® " SYSTEM BUS·

which significantly reduces a board's current requirements. The routing of signal lines between the bus
interface and connector is simplified.

This techniqLJe overcomes the significant problem of
interrupt configuration found in traditional buses.
Dedicated lines usually imply that only one particular
destination can service one particular interrupt
source. If an interrupt source wishes to target some
interruptsto one destination and some to a different
destination, separate bus interrupt lines are required
for each destination. This can quickly consume all
dedicated interrupt lines in even a moderate size
system.

ERRORS

The iPSB bus defines a complete set of bus error
reporting mechanisms. Serious errors, such as a
parity error or the failure of a module to complete the
data handshake, are flagged on unique bus signal
lines and are seen by all modules on the bus. These
errors induce a recovery time in which the bus is
allowed to stabilize before further transfer cycles
may begin.

Using interrupt bus cycles with embedded source
and destination module addressing removes the
need for dedicated interrupt lines at the same time it
allows any interrupt source to signal any interrupt
destination.

The iPSB bus also provides mechanisms for signaling less serious operational errors. Operational errors, such as attempting to perform a 32-bit access
to a a-bit device or writing to read-only memory, are
signaled as agent errors. These errors may induce
retry operations by an intelligent bus interface or
may be passed to the on-board processor as errors.

MESSAGE PASSING

With the trend in microcomputer systems toward
multiprocessing, it is important to provide the facilities and mechanisms to lend support for inter.modulecommunication. The iPSB bus includes such
mechanisms and defines the protocol for greatly enhanced performance in inter-module communication. This protocol is called MULTIBUS II Message
Passing.

INTERCONNECT ADDRESS SPACE

The ability to address a board by its physical position
in the backplane is also supported in the iPSB bus.
This facility allows board manufacturers to code
such items as their vendor number, board type,
board revision number, and serial number on the
board. This information is available to the system
software. This facility is defined in the iPSB bus interconnet address space.

Most multiprocessor systems use either a "pass by
reference" or a "pass by value" protocol for intermodule communication. In the "pass by reference"
case, the two modules share a common memory resource and pass pointers or tokens to extend addressability of a desired data structure to the other
module. In "pass by value",the modules exchange
a copy of the desired data structure. Each of these
protocols has a set of advantages and disadvantages associated with performance, data security,
extendability to additional modules, and ease of use.

Aside from this read-only information, the interconnect space allows write operations to support board
configuration and diagnostics under software control. This facility can help reduce or eliminate hardware-based jumper options and DIP switches.

MULTIBUS II Message Passing takes the best of
both methods and lends hardware support. Message passing uses a hardware "pass by value" interface that gives the performance of a "pass by reference" system. It replaces the software module used
by the "pass by value" method with a specialized
message passing interface. The processor "passes
by reference" the reference to the data structure to
the message passing co-processor interface. This
interface communicates with the destination module's message passing interface to transfer the data
without processor intervention. This data transfer is
performed in the message address space. This is
illustrated in Figure 2. (In many ways, it is helpful to
think of the two communication message passing
interfaces as a distributed, smart, DMA controller.)

INTERRUPTS

The iPSB bus supports up to 255 distinct interrupt
sources and 255 interrupt destinations. Rather than
the user of the traditional method of dedicated interrupt signal lines on the bus, the iPSB bus defines a
special bus cycle to convey interrupt information.
This special bus cycle (actually part of the message
passing protocol discussed below) redefines the
meaning of the address; instead of a byte location in
memory for example, 16 of the 32 lines encode a
bits for the source module generating the interrupt
and a bits for the destination module to service the
interrupt.

15-3

inter

MULTIBUS® II SYSTEM BUS

PROCESSOR A DOMAIN

CPU
A

PROCESSOR B DOMAIN

I
I
I
I
I
I
I

1.
OBJECT

- i, -

CPU
B

3.
OBJECT

-/-- - - - i_ - - - """,- --t I
L
I 2.

DATA /
PASSING
MODULE A
(HARDWARE)

""'-

DATA
PASSING
MODl,lLE B

(~ARDWARE)

280387-3

NOTES:
1. CPU A Requests Transfer of Object (Pass by Reference).
2. Data Movement is Negotia1ed; Data Movement'is independent of Either Processor.
3. Processor B Assigns Memory for Object and is Signaled of Object Availability.

Figure 2. MULTIBUS® II Message Passing

ARBITRATION

TRANSFER

RESOLUTION

ACQUISITION

(

REQUEST

H~
~~

RESOLUTION

REPLV

ACQUISITION

)-(

REQUEST

~ i'-.' ~---« ~

~ ,i'-'

EXCEPTION

RESOLUTION

------«

- - - - ( l ' i ' ..'

SIGNAL

)---t~

RECOVERV

ACQUISITION)

REQUEST)

)~--280387-4

Figure 3. Bus Cycle Relationships

15-4

MULTIBUS® II SYSTEM BUS

There are several significant benefits to this approach. First of all, the message passing interfaces
can take advantage of the full capabilities of the bus
(i.e., 32-bit data and burst transfer) independent of
the type or nature of the controlling processor. Even
a-bit processor or 1/0 boards can take full advantage of the bus. This means significantly higher intermodule communication performance over a completely software-base method. Another benefit is the
elimination of any shared memory. Dual-ported
memory structures are no longer needed nor are
global memory boards. The other primary benefit is
that MULTIBUS II message passing presents a uniform software interface for all modules. Modules can
be replaced with new modules containing newer
technology (e.g., moving from a single density to a
double density disk controller) without any software
changes required in the controlling module. This
makes it easy for users to integrate new technology
without the problem of completely rewriting the driver software.

ARBITRATION CYCLE

CENTRAL SERVICES MODULE

Starting the transfer cycle is the request phase. In
this phase, the bus owner (requesting agent) places
address and command information on the bus. This
information defines the replying agent(s), the type of
operation, and the type of address space. The request phase lasts one bus clock cycle.

The arbitration cycle is made up of a resolution
phase and an acquisition phase. The resolution
phase is the time-period in which all requesting
agents collectively arbitrate for access rights to the
bus. Depending on the arbitration algorithm, the
agents decide among themselves which of them is
going to control the bus after the current bus owner
is done. This arbitration method is referred to as
self-selecting since the agents decide ownership
among themselves.
The agent that wins the arbitration and obtains access rights to the bus begins the acquisition phase;
that agent becomes the bus owner. This agent begins its transfer cycle and holds the arbitration logic
in the resolution phase (resolving for the next access rights) until the transfer cycle is completed.
TRANSFER CYCLE

The iPSB bus specification defines the central system functions as the Central Services Module
(CSM). The minimal set of functions are: clock generation, power-down and reset, time-out. and assignment of slot IDs. Collecting these functions in a single module improves overall board area utilization,
since the functions are not duplicated on every
board and then only used on one. The system designer is free to implement the CSM on a separate
board or to include the functions as just one of several modules on another board.

The reply phase starts immediately after the request
phase, during this phase, the requesting and replying agents engage in a handshake that synchronizes
the data transfer sequence. The reply phase can
contain one or more data cycles. The final data
transfer is signaled by the requesting agent. During
this final transfer, the requesting agent releases
ownership of the bus allowing the new bus owner to
use the bus immediately. Note how the transfer cycle overlaps the resolution phase of the arbitration
cycle to minimize bus dead time.

Bus Cycle Overview
The iPSB bus defines three types of bus cycles: arbitration, transfer, and exception cycles. Each cycle is
made up of one or more phases. Figure 3 illustrates
the relationship among these cycles and phases.

15-5

MULTIBUS® II SYSTEM BUS

EXCEPTION CYCLE

ARBITRATION GROUP

If an agent detects an error during a transfer cycle, it
immediately begins an exception cycle. The exception cycle terminates any arbitration cycles and
transfer cycles in progress. The exception cycle
starts with the signal phase in which the detecting
agent activates one of the exception lines. This notifies all agents of the problem causing them to terminate any arbitration or transfer cycles. Next the recovery phase begins. During this .phase, all agents
idle; this allows the bus a fixed amount of idle-time to
stabilize before resuming normal operation.

The arbitration signals on the iPSB bus determine
which agent gains exclusive access to' the bus
(which agent is the bus owner). All requesting
agents that require access' to the bus resources
must arbitrate for use of the bus. On being granted
bus ownership, an agent begins using the address!
data lines to perform a transfer cycle. There are seven signals in the arbitration ,group: BREa' and
ARB5· through ARBO·.

Signal Groups
OVERVIEW
The iPSB bus contains five groups of Signals, Figure
4, over which the requesting and replying agents can
enact the protocol. An asterisk following the signal
name indicates that the particular signal or group of
signals are active when at their electrical low.

CENTRAL CONTROL _AL GROUP

{

ARBITRATION CYCl~ SIGNAL GROUP

EXCEPTION CYCLE SIGNAL GROUP

(

SYSTEM CONTROL SIGNAL GROUP

Hilil

IIIIB

Iff
IIIIH

IPSB
PARALLEL
SY:J: M

EXCEPTION CYCLE SIGNAL GROUP

HIIII I
I-

11
ARBITRATION CYCLE SIGNAL GROUP ")

AODRESSIOATA.USSIGNALGAOUP )

H II I

CENTRAL CONTROL SIGNAL GFIOUP

H
1111

lin

P:::ii~L ( AOOAESSIDATA.USSIGNALGROUP
BUS

. A particular agent's arbitration ID number is coded
on lines ARB4' through ARBO' (Arbitration). An
agent requiring use of the iPSB bus asserts BREa'
and drives its arbitration ID onto the OR-tied ARB
lines. The ARB5' line selects one of two arbitration
algorithms: fairness or high priority.

111

IPS8

BREa' (Bus Request) is an OR-tied signal Which is
bused on the backplane. All agents that require access to the bus assert the BREa' Signal.

HIIIIII

IIIIIIH

IIIIIIH
SYSTEM CONTROL SlONAl GROUP )

I-

~
REPLYING
AGENT

REQUESTING
AGENT

REPLYING
AGENT

REQUESTING
AGENT

280387-5

Figure 4. IPSB Bus Signal Groups

15-6

inter

MULTIBUS® II SYSTEM BUS

Table 1. System Control Definition
Function

Signal

SCQ
SC1
SC2
SCS
SC4
SC5
SC6
SC7
SCB
SC9

Request Phase

Reply Phase

Request Phase
Lock
Data Width Q
Data Width 1
Address Space Q
Address Space 1
Read/Write
Reserved
Parity (SC7-4)
Parity (SCS-O)

Request Phase
Lock
End-of-Cycle
Requesting Agent Ready
Replying Agent Ready
Agent Error Q
Agent Error 1
Agent Error 2
Parity (SC7..,4)
Parity (SCS-O)

ADDRESS/DATA BUS GROUP

EXCEPTION SIGNAL GROUP

This signal group contains the lines used to transfer
the address and data information plus their respective byte parity lines. The AD31· through ADO· (Address/Data) lines are multiplexed and serve a dual
purpose depending upon the phase of the transfer
cycle.

The iPBS bus provides a group of two signals for
passing indications of exception errors to all agents:
BUSERR· (Bus Error), and TIMOUT· (Time-out).
An agent activates BUSERR· to indicate its detection of a data integrity problem during a transfer. Parity errors on the AD or SC lines are typical of errors
signaled on BUSERR. Any agent detecting such errors must signal BUSERR· and all agents must receive BUSERR·.

During the request phase, they contain the address
for the ensuing transfer. This address refers to the
byte location for memory and 110 spaces, a processing agent module in message space, and a
board slot .location in interconnect space. The requesting agent drives these lines during the request
.
phase.

TIMOUP is signaled by the CSM whenever it detects the failure of a module to complete a handshake. TIMOUP is received by all agents on the·
bus.

During the reply phase, they contain either eight, sixteen, twenty-four, or thirty-two bits of data. They are
driven by the requesting agent for write transfers
and by the replying agent for read transfers.

CENTRAL CONTROL GROUP

The system control group provides status concerning the operating state of the entire iPSB bus environment. It consists of seven signals plus the power
and ground lines.

The PAR3· through PARO· (Parity) lines are the
byte parity lines associated with the respective bytes
of the AD lines. They form even parity with their respective address/data byte.

The RST· (Reset) signal is a system-level initialization Signal sent to all agents by the CSM.

SYSTEM CONTROL SIGNAL

The RSTNC· (Reset Not Complete) signal is an ORtied line driven by any agent whose internal initialization sequence is longer than. that provided by the
RSP signal itself. .Due t6 its OR-tying, RSTNC· remains active until every agent has completed its initialization sequence. Agents cannot perform bus
transfer cycles until RSTNC· is inactive.

The transfer signal group consists of ten signals,
SC9· through SCO( (System Control). Agents use
these Signals to define commands or to report
status, depending on the phase of the transfer cycle.
During the request phase, the requesting agent
drives SC9· through SCO·. The SC lines provide
command information to the replying agent(s). During the reply phase, the requesting agent drives
SC9· and SCS· through SCO· with its handshake
and additional control information. The replying
agent drives the remainder with its handshake and
status. Table 1 lists the request and reply phase
functions for this group.

The CSM provides a DCLOW (DC Power Low) signal to all agents as a warning of an imminent loss of
DC power. DCLOW is typically generated from a signal supplied by the system power supply on the loss
of AC power. Any agent needing to preserve state

15-7

inter

MULTIBUS® II SYSTEM BUS

information in battery backed-up resources should
.do so upon receiving an active OCLQW.
Accompanying DCLOW. for power-down seql!encing
is the PROT· (Protect) signal. The CSM drives
PROT· active a short time after it activates OCLOW
to inform all bus interfaces to ignore any transitions
on the bus as power is lost.
The BCLK· (Bus Clock) and CCLK· (Constant
Clock) signals are supplied by the CSM to all agents.
Agents use the BCLK to drive. the arbitration ~nd
timing state machines on the iPSB bus. The active
going edge of BCLK~ provides all system timing references. The CCLK· is an auxiliary clock at twice
the frequency of BCLK.
An agent user its LACHn·(IO Latch)signal,~o sa~e
the slot 10 it receives from the CSM at reset time via
the ARB4· through ARBO· lines. The 10 latch signal
is called LACHn· where the "n" is the card slot to
which the'lO is ,assigned. At each card slot, the
LACHn· signal is connected to the AO line of the
same number.· As an example, card slot 7 has a
LACH7· signal that is connected to A07·.
When RSP is active, the CSM sends successive
slot 10's .(0 through 19) on the ARB4· through
ARBO· lines while activating the corresponding AO
line. Agents know when the ARB lines contain the
correctslot number when they see their LACHn· line
go.active.
POWER
System power supplied in the iPSB connector)ncludes + S volts, + 12 volts, ":'12 volts, and facilities
for + S volt battery back-up. Also defined are numerous ground lines some of .which are interlaced
throughout the connector.

iPSBBus Protocol
. OVERVIEW
In the MULTIBUS'II specification, both timing diagrams and' state-flow' dia~ran:'~ describe the iPSB
bus protocol.· The state-flow diagrams present the
lowest-Ievel'and most rigorqus definition while the
timing diagrams help conceptual understanding. For

the purposes of this data book, only the timing dia.
gram description is used.,
ARBITRATION CYCLE
An agent that wishes to transfer data on the iPSB
bus must begin by performing an arbitration cycle.
The cycle performs two functions: first, it gives all
agents the opportunity to be granted access to the
bus; and second, it eliminates the possibility of more
than one agent trying to transfer data on the bus at
anyone instant. In the case where more than one
agent requests access to the bus at the same in"
stant, the arbitration cycle grants access to the.
agents based upon one of two arbitration algorithms:
normal or high priority.
Normal priority mode provides "fairness" or "no
starvation", which means each agent has an .equal
opportunity ,to grant access to the bus. For examp!e,
assume all agents request the bus at the same I~
stant. In the normal priority mode, each agent IS
granted the bus, one by one, until all requests h~ve
been serviced. If an already serviced agent deSires
to use the bus again before all of the original agents
are serviced, it will wait until all of original requesting
agents have their request granted. This "round-robin" granting of access ensures that any agent requesting the bus Will eventually get it.. •
The high priority mode allows .an agent with high priority to force its way into the arbitration arid be granted the bus before agents with lesser priOrity. This .
means that a high priority agent gets access to the
bus quickly; however, it can also consume so mu~h
of the bus that agents with less priority never gain
access; they will "starve".
At reset, the CSM supplies each agent with its slot
10 and its arbitration 10. An agent making a normal
priority request activates BREa·, 'holds ARBS· inactive; arid drives its arbitration 10 onto ARB4* through
ARBO·. If the ARB lines hold its 10 after a specified
time (3 bus clocks), this agent won the arbitration
and can use the bus once any ongoing transfer completes. However, if the ARB lines do not match its 10
(after all, other agents might be also requesting the
bus and driving the ARB lines), another agent won
the arbitration. The losing agent removes its 10 and
waits for the next resolution phase before trying
again.

1S-8 .

inter

MULTIBUS® II SYSTEM BUS·

simultaneous normal priority requests. When more
than one agent simultaneously makes a high priority
request, the agent with the higher priority (lower numerical value) arbitration 10 will go first. Figure 5 illustrates the logic required to implement the iPSB
bus arbitration. With either priority mode, once an
agent owns the bus, it can perform any number of
transfer cycles until force off by arbitration. This
characteristic of the arbitration algorithms is called
"bus parking".

An agent makes a high priority request by activating
BREa', holding ARB5' active (ARB5' selects the
arbitration mode), and driving its arbitration 10 onto
the ARB lines. The high priority algorithm requires
that when a high priority request enters during an
arbitration cycle, the request immediately enters the
next resolution phase rather than waiting for the next
bus request cycle as do normal priority requests.
ARB5' being active causes the other requesting
agents to remove their requests guaranteeing the
high priority agent access to the bus before any

AGENT I PARALLEL

HIGH PRIORITY REQUEST
(HPRI)
_ _ _ _-,-_ _ _..,
ARBITRATION CYCLE
(NO CYCLE = L)
:=::[~~
LOCAL BUS REOUEST
(LBREQ)

I ~~~TEM

___-,~===lC>--r-~~
I

ARBS*

104

HT===t--..).-~-~~
-----r----IH----{
I

ARB4*

I
I

l>--r-~~
103

-----,----!-Hf---I

102

-----r-....:::=~+I+==t--'

ARB3*

I
I
I

)...jU:h:=:::t-)...........--4~

ARB2*

I
I

'1tta=E=t=»-T-~~ ARB,.
101

----.,.----!+H-+--I

I
I
100

GRANT INDICATION
(WIN)

----~~::~~EEf!~t=~-r_-~~,'
-----.r""t=~

ARBO*

I
I
I
I
I
I
280387-6

FIgure 5. IPSB Bus Arbitration Cycle

15-9

inter

MULTIBUS® II SYSTEM BUS

TRANSFER CYCLE
Transfer cycles consist of two phases: request and
reply. For illustration, an example of an access read
cycle is shown in Figure 6. During the request phase,
the bus owner (requesting agent) uses the transfer
cycle signal group (SC lines) to notify the replying
agent of the address space (memory, liD, interconnect, or message), the data width (8-, 16-, 24- or 32bit), and whether the cycle is read or write. The AD
lines contain the desired address for the selected
address space. Replying agents know the SC lines
contain this request information by the requesting
agent activating SCO' (Request Phase). The request

phase lasts one clock cycle. All potential replying
agents use the request phase to determine whether
they contain the addressed resource.
The reply phase starts immediately following the request phase. During this phase the agent with the
addressed resource (replying agent) and the requesting agent exchange data and status. Both the
requesting and replying agent must agree that the
data on the AD lines and the status on the appropriate SC lines are valid via the RORDY (Requesting
agent read-SC3*) and RPRDY (Replying agent
read- SC4 *) handshake lines. Either agent can

BUS CLOCK

AD31 * . ADO*

REPLY PHASE

sca
SC2*
SC3*

SC6*

SC9*
EOC

HANDSHAKE

280387-7

Figure 6. Transfer Cycle Example

15-10

MULTIBUS® II SYSTEM BUS

hold off the transfer by deactivating its ready line.
This handshaking supports any speed requesting or
replying agent.
The transfer cycle is complete when the requesting
agent signals the last data transfer via the End-OfCycle (EOC-SC2*). The last bus clock cycle of the
transfer is when EOC, RQRDY, and RPRDY are all
active simultaneously.
The replying agent has the opportunity to tell the
requesting agent if it does not support the requested
operation via the agent error (SC5', SC6', and
SC7') lines, These lines encode five types of errors:
width violation, continuation error, data error, illegal
operation, and negative acknowledgement of a message. Trying to extract 32-bits of data from an a-bit
peripheral is an example of a data width violation.
Continuation errors occur when attempting sequential access from an agent which does not support
them or running off the ending address of a memory
board. Writing to a read-only memory is an example
of an illegal operation. A parity or ECC error ina
memory board is an example of a data error. A replying agent signals a negative acknowledgement to a
message transfer cycle if its destination queue is full
(the source most perform source queuing). The
transfer cycle is terminated by the requesting agent
when it detects that the replier is signalling an agent
error. If the bus interface is intelligent, it might retry
the operation with a different type that the replying
agent can support. Other aspects of transfer cycle
include the ability of a requesting agent to LOCK the
bus via the SC1* line. SC1* is a non-multiplexed signal which inhibits alternate ports of any multi-ported
resource being addressed. By locking the bus, the
requesting agent can guarantee itself exclusive access to a multi-ported bus resource and retains bus
ownership for more than one transfer cycle.
As noted in the figure, in addition to parity protection
on the address/data lines, the SC lines are also protected by parity. The requesting agent is responsible
for the SC parity bits (SCa" and SC9*) during the
request phase (it drives all SC lines). The reply
phase requires two parity bits: one for those lines
driven by the requesting agent and one for those
driven by the replier. This ensures all aspects of the
transfer cycle have parity protection.

cycle as a result of sensing an exception. If no exception occurs, no exception cycles occur.
The exception cycle has two purposes in the protocol: first, it provides systematic termination of activity
on the iPSB bus and second, it provides a stabilization time before allowing agents to resume operation. These two purposes correspond directly to the
two phases of the exception cycle: the signal and
recovery phases.
The signal phase begins when an agent or a module
senses an exception and activates one of the bus
error lines. One receiving a bus error, all agents terminate any transfer or arbitration cycles in progress.
The net effect of the signal phase is to terminate all
bus activity. The signal phase continues until the error-detecting module deactivates the bus error line.
The recovery phase begins after the bus error line
becomes inactive. The recovery phase is a fixed-duration delay (in terms of bus clock cycles) that allows
time for the iPSB bus signals to settle before starting
more transfer cycles.
There are two types of bus exceptions supported by
the iPSB bus: timeout and bus error. The CSM monitors the bus to ensure that all data handshakes complete. If for some reason the handshake hangs and
exceeds a maximum time limit, the CSM activates
the TIMOUT* (Time Out) bus exception line to begin
the exception cycle.
An agent sends a bus error exception whenever it
determines that the information on the address/data
(AD) or the transfer control (SC) lines is in error.
Once an error is detected, the agent activates the
BUSERR* (Bus Error) signal line to begin the exception cycle.

Mechanical
The MULTIBUS II boards, board accessories, and
backplanes conform to mechanical standards defined by the International Electromechanical Commission (IEC); these standards are commonly referred to as the Eurocard mechanical standards.
This mechanical system offers modular board sizes
as defined in standard IEC-297-3 and reliable twopiece connectors as defined in IEC-603:2.

EXCEPTION CYCLE

The exception cycle is an error reporting mechanism. An agent or the CSM initiates an exception

15-11

inter

MULTIBUS® II SYSTEM BUS

FORM FACTOR

Connector

The MULTIBUS II specification calls out two modular
board form factors: 233 x 220 mm and· 100 x
200 mm (see Figure 7). The iPSB bus and iLBX II
bus portions of the MULTIBUS II system architecture
are always defined on the P1 and P2 connectors.
respectively. However, the user can oPtionally define the use of the P2 connector if the iLBX II bus is
not supported. (The iSSB bus is additionally defined
on the P1 connector.)

MULTIBUS II boards and backplanes use two-piece,
96-pin connectors for both the iPSB bus and iLBX II
bus. The right-angle connectors on the printed board
are IEC standard 603-2-IEC-C096-M; the receptacle
connectors on the backplane are IEC standard 6-032-IEC-C096-F (Figure 8). This connector family is
noted for its reliability, availability, and low cost.

~
.

...

8'661 ~:~~~~

(220,000

~~:~).

.109
(2,76)

~--------I--------------~~~--~I

9.187 +.000
-.012
(233,35 + 0,0 )
-0,3

COMPONENT SIDE

n~
(ar

5.468
1(138,89)
3.500

t...219
(5,55)
280387-10

Figure 7_ MULTIBUS®II Board Sizes

15-12

MULTIBUS@ II SYSTEM BUS

.0118--\
(2.5', \ • ____ _
DIA. TYP ...

3.50o".004
(88.110"0,10'

.100
TYP.

__t_

rFT[-l-~100
c=m
""-

.025

PINSON

!!!:. SQ.

---- -------- '~c:.~g~:'----

(0,84'

TYPICAL

3.700

______________~M.:..:.AX,,-.-:--

(114,00'

--_ ..

TYP.
(2,54'

_._-280387-8

I
::JkE1
I

-I

280387-9

Figure 8. MULTIBUS®n Connectors

15-13

inter

MULTIBUS® " SYSTEM BUS

The pin assignment for the iPSB bus on P1 is shown
in Table 2.

Please refer to Intel's MULTIBUS II Bus Architecture
Specification Handbook for more detailed information.

Table 2_ IPSB Bus Pin Assignments
Connector Pin Number
1
2
·S
4
S
6
7
S
S
10
11
12
1S
14
1S
16
17
1S
1S
20
21
22
2S
24
2S
26
27
2S
2S
SO
S1
S2

Row A

oVolts
+SVolts
+ 12 Volts
(Note 2)
TIMOUT'
(Note 1) LACHn
ADO'
AD2*
AD4*
AD7'
ADS" ,
AD11*
AD1S'
PAR1*
AD17*
AD20'
AD22'
AD24*
AD26*
AD2S'
ADS1'
+SVolts
BUSREQ'
ARBS'
ARBS'
ARB1'
SCS"
SC6'
SC4'
-12 Volts
+S Volts
oVolts

RowC

RowB
PROT"
DCLOW'
+S Battery
SDA (Note S)
SOB (Note S)
o Volts
AD1"
o Volts
ADS'
+SVolts
ADS'
+SVolts
AD14'
o Volts
AD1S"
o Volts
AD2S'
o Volts
. AD27'
oVolts
Reserved
+SVolts
RST"
+SVolts
RSTNC'
o Volts
SCS'
o Volts
SCS'
+S Battery
SC1'
SCO'

oVolts

+SVolts
+ 12 Volts
BCLK'
o Volts
CCLK"
o Volts
ADS'
AD6'
PARO'
AD10'
AD12'
AD1S'
AD16'
AD1S"
. AD21'
PAR02'
AD2S'
AD2S"
ADSO'
PARS'
Reserved
BUSERR*
ARB4'
ARB2'
ARBO"
SC7'
SCS"
SC2'
-12 Volts
+SVolts
o Volts

NOTES:
1. LACHno for all agents but the one driving CCLK"; line contains· a second CCLK* Signal in systems that have more than 12
cardslots.
..
2.0 Volts for all agents but the one driving BCLKo; line contains a second BCLKo signal in systems that have more than 12
cardslots.
3. Signal lines SOA and SOB are reserved for the Serial System Bus.

1S-14

IIIlLTIBIlS<:>
ISac"

ISBC·

BOARD

MEMORY
BOARD

ISBC·

BOARD

ILBX"'UBUS
(4BMBpo)

IPSB (40MBpa)

280376-2

Figure 1. MULTIBUS® II Bus Architecture

15-18

MULTIBUS® II LOCAL BUS EXTENSION

INTERCONNECT ADDRESS SPACE

BUS CYCLE OVERVIEW

The iLBX II bus supports the slot-addressing concept of the interconnect address space found in the
iPSB bus. Including this facility in the iLBX II bus
allows the system to identify and configure iLBX II
bus boards even though they may not contain a
iPSB bus port. (Please refer to the iPSB bus data
sheet for additional information on the interconnect
address space.)

Like the iPSB bus, the iLBX II bus protocol consists
of three types of bus cycles: arbitration, transfer, and
exception.

DUAL BUS MASTER
In order to support a wide range of system configurations, the iLBX II bus defines support for two bus
masters. One master is called the Primary master;
the other is known as the Secondary master. The
Primary master normally "owns" the bus and does
not have to spend any time arbitrating for access
rights. The Secondary master must ask the Primary
master for access rights. The Primary releases the
bus at the first opportune time. This hierarchical
structure ensures that the Primary master enjoys
good memory latency while at the same time gives
the Secondary the opportunity to access memory
when it needs to.
The iLBX II bus also includes a dedicated interrupt
line to facilitate signalling between the two masters
for commands and status, and between the memory
boards and the Primary master for things such as
non-recoverable memory errors.

ARBITRATION CYCLE
The arbitration cycle ensures that one and only one
requesting agent is allowed access to the bus at any
given time. When a requesting agent determines the
need for a bus operation, it enters the arbitration
cycle. For either requesting agent, this cycle lasts
until it acquires the right to use the bus. In configurations with only a primary requesting agent, no time is
spent for this cycle; the agent always has rights to
the bus. In configurations where there are both a
primary and secondary agent, the primary agent has
to arbitrate for the bus only when the bus is busy
under the secondary agent's control. Figure 2 illustrates the arbitration cycle.
TRANSFER CYCLE
The transfer cycle is the event where the request
(address and command) and reply (data) information
is exchanged between the bus agents. Like the iPSB
bus, it consists of a request and a reply phase. During block transfers, the termination of the transfer
cycle is controlled by the requesting agent. In nonblock transfer cycles, the cycle's termination is implicitly recognized by both agents. Figure 3 shows a
transfer cycle example.

BUBREQ

BUSACK

PRIMARY
TRANSFER CYCLE

/
SECONDARY
TRANSFER CYCLE

PRIMARY
TRANSFER CYCLE

280376-3

Figure 2. iLBXTM II Bus Arbitration Example

15-19

MULTIBUS® II LOCAL BUS EXTENSION

XC2*

XC3'
Address
Space
Memory

Access
Type

Interconnect

Write

TRANSFER CYCLE

REQUES.;..T_~_. . .
PHASE

Read

ADDRESSI
COMMAND

Figure 4. iLBXTM Ii Command Encoding

DATA
BUS

XC1*
XCO'
Width
Specification
1 byte
2 bytes
3 bytes
4 bytes

1 CYCLE - I_ _~
!lELAY

280376-4

Figure 3. iLBXTM II Transfer Cycle
EXCEPTION CYCLE
Exception cycles allow the bus agents to signal any
detected error or exceptional condition which might
arise during a transfer cycle. Typical exceptions are
uncorrectable Eee errors, parity errors, or physical
boundary overflows.

Signal Groups
OVERVIEW
There are ,five categories of signals used in the
iLBX II bus: address/command, data transfer, access control/status, bus control/status, and miscellaneous. An asterisk following the signal name or
group indicates that the signal or group use their low
electrical state as the active state.

Parity for the address/command group is not required. The bus does allow for a single parity bit
covering the address and command lines as a compliance level. The iLBX II bus environment is much
different than that of the iPSB system bus. It extends
only a short distance (6 card slots maximum) and,
employs lower switching currents. This more restrictive environment reduces the need for data integrity
protection in all but the larger systems.
DATA TRANSFER GROUP
This signal category consists of the 32 bi-directional
data lines and their optional parity line. XD31
through XDO (Extension bus data) transfer the read
or write data between the requesting and replying
agents. Each byte in the iLBX II bus memory is
mapped to one of the four byte locations of the XD
lines. This technique is commonly referred to as
"byte lanes" and is illustrated in Figure 5.
Like with the address/command group, the XDPAR
(Extension bus data parity) line is optional.

ADDRESS/COMMAND
The requesting agent uses this group of signals to
transfer address and command information to the
potential replying agents during the request phase of
a transfer cycle. This signal group consists of the
non-multiplexed address lines, XA25 through XAOO
(Extension bus address), the command specification
lines, XC3 through XCO (Extension bus command),
and an associated parity line, XAPAR (Extension
bus address/command parity).
The XA25 through XAOO lines define the starting
physical byte address. The command specification
lines select the address space (memory or interconnect), data width (1, 2, 3, or 4 bytes), and whether
the operation is a read or write cycle. The command
encodings for Xe3 through xeo are shown in Figure 4.

8 BIT
8
REQUESTING .....---1'-1
AGENT

16 BIT
16
REQUESTING .....~:......J
AGENT

32 BIT
REQUESTING .....~32r---t
AGENT

=AN 8 BIT BUFFER
280376-5

Figure 5. iLBXTM II Data Bus Alignment
Interface Requirements
15-20

inter

MULTIBUS® II LOCAL BUS EXTENSION

removing XBUSACK*. The secondary must return
the bus at the earliest time; typically when it completes its current transfer cycle.

ACCESS CONTROL/STATUS GROUP
This signal category consists of 5 lines which determine the start of an access request, its execution,
and finally, its termination.
The XACCREQ* (Extension bus access request)
signal indicates that the address/command information is valid during the current and next bus clock
cycles. It signals the presence of the request phase
of the transfer cycle. Replying agents which require
more time to decode the command information can
extend XACCREO* using the XWAIT* handshake
line.
The XWAIT* (Extension bus wait) signal has a twofold meaning in the access protocol: it can extend
the duration of the request phase and it serves as a
"not ready" replier indication during the reply phase.
If asserted in the first clock cycle of the request
phase, it extends the phase, otherwise, it will signal
"not ready" during the reply phase.
In many system configurations the iLBX II bus memory boards are dual-ported to both the iL.BX II ~~d
iPSB buses. This requires a mutual exclusion facility
when implementing semaphores and other data
structures in this shared memory. The XLOCK*
(Extension bus lock) signal allows the iLBX II b~s
requesting agents to lock out the other port while
performing indivisible accesses to shared structures.
To perform block transfers on the iLBX II bus, the
requesting agent asserts the XBTCTL * (Extension
bus block transfer control) Signal. This line informs
the replying agents that two or more data transfer
periods will accompany a single request phase.
XBTCTL * is de-asserted by the requesting agent to
signal the end of the block transfer.

MISCELLANEOUS CONTROL GROUP
The XRESET* (Extension bus reset) is driven by the
primary requesting agent to locally initialize its
iLBX II bus environment. It is typically asserted after
the agent receives a reset indication on the iPSB
system bus.
, The XINT* (Extension bus interrupt) allows the S?Condary requesting agent and any .of the replYI~g
agents to signal the primary requesting agent for Inter-module communication. Since the secondary
agent is usually performing tasks on behalf of the
primary agent, this interrupt line removes the need
for the primary to continuously poll the secondary for
completion of its tasks.
The XID2* through XIDO* (Extension bus identify)
lines are hardwired lines on the backplane to allow
any iLBX II bus board to determine its position on
the bus. They encode the interconnect space least
significant three bits of the slot ID field. (See the
iPSB bus data sheet for an explanation of the interconnect address space.)
The final line is the XBCLK* (Extension bus clock)
line. It provides the reference timing Signal for the
synchronous bus operations. It is driven by the primary requesting agent at its processor bus frequency.
The iLBX II bus also defines additional
ground pins.

+ 5 volt and

Bus Protocol
BUS CONTROL/STATUS GROUP
The signals in this group control the passing of bus
ownership between the primary and secondary requesting agents. When the bus is in use, they also
indicate which agent is in control.
The XBUSREQ* (Extension bus request) signal is
driven by the secondary requesting agent to acquire
the bus from the primary agent. Only the primary
requesting agent receives this signal. When the primary detects that the secondary is reques~ing the
bus, it replies with the XBUSACK* (ExtenSion bus
acknowledge) signal to inform the secondary that
the bus is now his. This bus exchange occurs at the
discretion of the primary.
The secondary owns the bus after asserting XBUSREO* and receiving XBUSACK* active. The primary
can request that the bus be returned at any time by

In the MULTIBUS II specification, both timing diagrams and state-flow diagrams describe the iLBX II
bus protocol. The state-flow diagrams present the
lowest level and most rigorous definition while the
timing diagrams help conceptual understa~di.ng. ~or
the purposes of this data sheet, only the timing diagram description is used. The following sections use
Figure 6 as an example of the protocol.
ARBITRATION CYCLE
With only two potential requesting agents contending for access rights to the bus, the arbitration cycle
is very simple. The figure illustrates the secondary
requesting agent requesting the bus from the Primary and then running a simple transfer cycle. The
secondary requesting agent makes its request by
asserting XBUSREO*. The primary gives up the bus

15-21

inter '

MULTIBUS® II LOCAL BUS EXTENSION

by returning XBUSACK* active. In this example, the
secondary uses the bus for only a single transfer
cycle so it de-asserts XBUSREQ* when complete.
The primary agent responds by withdrawing
XBUSACK* to indicate it now owns the bus.

EXCEPTION CYCLE

TRANSFER CYCLE

Like in the iPSB bus, the transfer cycle proceeds as
a request phase and a reply phase. The requesting
agent (either the primary or the secondary depending upon who currently owns the bus) informs the
potential replying agents of the request phase by
driving valid information on the address/command
signal group and asserting XACCREQ*. The request
phase normally lasts two clock cycles although the
replying agents have the opportunity to extend the
phase as long as necessary by asserting XWAIT*
during the first clock period of the phase. The phase
is extended as long as XWAIT* is active. In the example, the request phase is extended one additional
clock.
The reply phase begins when XWAIT* is de-asserted. At this point, the meaning of XWAIT* changes to
become a "not ready" indication from the selected
replying agent. In the example, the replying agent
requires one additional clock period to supply the
data so XWAIT* is asserted for one clock. The reply
phase terminates on the same clock that data is valid.

XBUSREQ"

If transfer integrity checking is implemented on the
iLBX II bus, errors are signalled on the clock following the last valid information period. In example, errors detected on the address/command lines during
the request phase are signalled on the clock following the removal of valid request information ..The
same applies to errors detected on the data lines
during the reply phase.

Mechanical
The iLBX II bus is definec;l on the P2 connector of
two-connector MULTIBUS II boards. Since the iLBX
II bus environment is local to a particular processor
board, the iLBX II bus backplane does not extend
the entire length of the iPSB bus backplane. This
allows for multiple iLBX II bus environments in a given system.
The pin assignment for the iLBX II bus on P2 is
shown in iLBX II specification section in the
MULTIBUS II Bus Architecture Specification Handbook.
Please refer to Intel's MULTIBUS II Bus Architecture
Specification Handbook for more detailed information.

~-"""f---I---+--t---t---t-'

XBUSACK"

XA(25.0)~-:-II_I_~~_~~"':~
XC(3·0)I
XACCREQ"

XWAIT"

XD(31.0)1----!--+--+---t---t~

~~::::~-.....,r--~-I---+--t---t~
280376-6

Figure 6. iLBX

Transfer Cycle Example

15-22

ENHANCING SYSTEM PERFORMANCE WITH
THE MULTIBUS@ II ARCHITECTURE

Although the MULTIBUSI!> II architecture can accommodate systems with a wide range of performance, systems
that take advantage of its multiprocessing capabilities can
achieve new performance levels while maintaining· reasonable price/performance ratios. Today, multiprocessing provides an easy path to increased functionality and processing
power largely because of the availability of inexpensive
memory and CPUs.

This product brief will discuss the MULTIBUS II multiprocessing capabilities and their user benefits. The capabilities include:
• A high-speed local environment
• An efficient burst transfer capability
• A hardware-based message passing facility

Higher Performance Through
Multiprocessing

The low cost of high-performance microprocessors and
RAM chips has drastically altered the cost dynamics of
systems design. The material cost of a CPU and its mem. ory are typically a small portion of the total system cost,
in sharp contrast to mini and mainframe computers where
the cost of the CPU and memory is the majority of system
cost. The decreased cost factor means today' s designer can
optimize a system's price/performance by dedicating a
CPU to each function in the system.

The key to high performance in multiprocessing systems is
allowing all of the processors to run concurrently in their
own private environments. For this to occur, each functional module must contain its own CPU, memory and
110 resources. It also means that the system bus is primarily used for passing commands and data between
modules.
A system using this approach might consist of a host processing board and intelligent disk controller, a terminal
concentrator and LAN controller boards (Figure I). Each

Figure 1. Functional Partitioning is the Distribution of CPU,
Memory & I/O Resources to Support Different Functions in a System

The following are trademarks ollnlsl Corporalion: MULTIBUS, iSBC.

15-23

functional module would contain the resources required to
perform its assigned function. Further, each module would
operate over its own private local bus which is decoupled
from the system bus. This enables the modules to operate
concurrently with each other and leaves the system bus open
for communication between the intelligent modules.

and a local memory bus extension. The MULTIBUS II
board form factor is the Eurocard Standard 233mm by
220mm (9.1 "X9.0"), chosen because it allows most functional modules to completely fit on one board. This factor
is critical to system performance because on-board
resources can be optimized to run at their full potential
without impacting the system bus. A smaller board size
would force a particular function onto multiple boards
with a resulting decrease in performance.

High-Speed Local Environment Optimizes
On-Board Resources
In mUltiprocessing systems, performance is optimized
when all execution code and data is accessed in a local
environment. The most important performance factors in
a local environment are the CPU clock speed, the number
of CPU clocks per instruction, the CPU instruction set,
and the number of memory wait states. While the CPU
choice dictates the CPU performance factors, the bus
architecture can assist in providing a good CPU-memory
and I/O environment.

Burst Transfers
A key development to optimizing the iPSB bus for multiprocessor communications is the high-speed burst transfer
capability. Since address information is transferred over
the bus only once for the entire burst, performance is
greatly enhanced.
The synchronous handshake capabilities of the iPSB
bus nearly double the speed of burst transfers compared
to traditional asynchronous handshakes (Figure 2). Burst

The MULTffiUS II architecture provides a high-speed local
environment through its moderate size board form factor

TRADITIONAL ASYNCHRONOUS HANDSHAKE
ADDRESS

----I.

COMMAND
DATA
STOBE
ACKNOWLEDGE

ADDRESS

COMMAND

----t

DATA 2

DATAl

I-"

DATA 3

.J- 1--1

~/ .....".
"t::....J

...J-

FOUR EDGE TRANSITIONS
ARE REQUIRED IN SEQUENCE
FOR EACH DATA TRANSFER
IPSB SYNCHRONOUS HANDSHAKE
ADDRESS

DATA 1

DATA.

DATU

DATA 3

ADDRESS/DATA t--L.._.ll..r--""1.._...ll..r--'_--..JIL.r--1-_.u.~-"'L_----I
COMMAND
REQUESTOR READY

t==i~~~~:;:::l~----~----il-----;7

REPLIER READY

II--.:......--.u.--,L-;c-it>---:;~-:-..,rr-L:::::=:-'1f----''-:;
L--.:~.u...r~=::~w~==:::::tf.-----L

COM

ENDOFBLOCKr----it----~~---~~----tt--,
XFER

ACTIVE (LOW) INDICATES
PROVIDED
VALID
DATA
REQUESTING
BOARD
HAS
DURING TIME WINDOW
ACTIVE (LOW) INDICATES
THE
REPLYING
BOARD
HAS
ACCEPTED
DATA
DURING
TIME WINDOW
ACTIVE (LOW) INDICATES
LAST DATA IN BLOCK
TRANSFER

~ TWO CLOCK EDGE TRANSITIONS REQUIRED

CENTRAL CLOCK

FOR EACH DATA TRANSFER

SIGNAL VALID TIME WINDOWS

Figure 2. iPSB Synchronous Handshake Compared to Asynchronous Handshake

15-24

transfers allow boards to transfer blocks of data over
the iPSB bus at speeds up to 40 Mbytes/s. This speed
approaches the limit of what can be expected from TTL
technology when propagation across a 20-slot backplane
is required.

various manufacturers will all be able to communicate
compatibly at tremendous speeds.
Message passing, as defined in the MULTIBUS II protocol, allows modules to communicate directly. In other
words, one module sends a message (data) over the iPSB
bus to the address of another module. This differs from
the normal CPU functions of reading or writing only
from memory or 110..

In the iPSB bus, a burst transfer consists of one address
clock followed by multiple data transfers. The receiving
board takes care of actual memory location placement
(ie., auto-increments the memory address, as necessary).
The actual speed of the burst transfer will depend on the
abilities of the communicating boards. For example, burst
transfers from an intelligent board to dual-port memory
will typically be only marginally faster than single-cycle
writes, due to the long access times from the system bus
side of dual-port memory boards.

Since conventional CPUs do not contain facilities to perform direct CPU-to-CPU communication, additional hardware logic is required. The hardware can be thought of as
a coprocessor to the primary CPU, e.g., a coprocessor that
adds the function of direct module-to-module communication at speeds many times thai which the primary CPU
could perform. The coprocessor logic for message passing resides in the bus interface.

To achieve the true performance benefits of burst transfers, each board needs the ability to send and receive small
bursts at the full bandwidth of the system bus. This can be
accomplished by bus interface logic containing high-speed
buffers and the ability to format and send 32-bit-wide data
bursts.

An example best illustrates how message passing works
(Figure 3). Assume Board A wants to send I Kbyte of
data to Board B. First, the CPU on Board A would instruct
its message passing unit to send I Kbyte of data (with the
assistance of a DMA device), beginning at a particular
location in local memory, to Board B. Next, the message
passing coprocessor on Board A takes over so the CPU

In the MULTIBUS II architecture, the interface bus logic
to the iPSB is defined with burst capability in a messagepassing scheme. This ensures that boards developed' by

Isac'·· 386/100

Isac· 386{100

2.
IPSS
1. OMA LOADS MPC (MESSAGE PASSINO COPROCESSOR)
2, MPC CREATES 32·BYTE PACKETS TO SEND OVER THE IPsa. MPC ON·CHIP
DOUBL.E 32·BVTE BUFFERING LETS IT BE SENDINQ SIMULTANEOUSLY WITH

MORE DATA BEING LOADED.
3. OMA UNLOADS MPC. DOUBLE RECEIVE BUFFERS LET THE MPC BE
RECEIVING SIMULTANEOUSL.Y WITH DATA BEING L.OAOEO.

BUS UTILIZATION"

1. LOCAL BUS 11

2. IPsa
3. LOCAL BUS '2

• NOTE: TRANSFER liMES ARE BASED ON IS8C' 31111100 BOARD PERFORMANCE

Figure 3. A Message Passing Example

15-25

Summary

can perform other processing. At this point, the DMA
device loads the data into the message pa~ing coprocessor
on Board A. Once enough data has been loaded (typically
32 bytes), the coprocessor arbitrates for the bus and sends
the first packet of data as a burst transfer to the messagepassing logic on Board B.

Five important performance benefits result from the
MULTIBUS II multiprocessing capabilities and specifically from hardware-assisted message passing. First, all
single-cycle memorylIO transfers can be designed to occur
in local CPU environments. These environments are optimized for single-cycle transfers over their local memory
buses and usually run at few or no wait states, compared
to substantial wait state delays over a system bus.

While the message passing logic on Board B is unloading
the first packet out of its high-speed buffers into local RAM,
the message-passing logic on Board A is reading the next
piece of data into its high-speed buffers. Meanwhile, the
system bus is free of traffic and available for another pair
of boards to communicate over.

Second, transfers over the iPSB bus can be done.as burst
transfers between message-passing logic containing highspeed buffers, thereby transferring data at the maximum
bus data rate. Third, the iPSB bus is not in use between
data packets and is available for other traffic. Fourth,
each CPU does not need direct access into the other
board's local environment. That is, no dual port memory
(which is slower than single port memory) is required.
And fifth, each CPU is available to process other tasks
while the data transfer is occurring.

The message-passing logic on Board A continues to build
and send small packets of data to Board B' s message-passing logic, and Board B continues to unload this data into
its local memory until the entire I Kbyte has been transferred. At the completion of the transfer, the messagepassing logic on both boards interrupts their respective
CPU s to notify them that the transfer is complete.

15-26

INCREASING SYSTEM RELIABILITY WITH THE
MULTIBUS® II BUS ARCHITECTURE
into lOOns increments with signals sampled at the end of
each period. This method avoids looking at the signal
while transitions caused by reflections and crosstalk are
occurring. Therefore, signals are vulnerable only during
the small sampling window.

System reliability is more than just mechanical factors
like Eurocard and DIN connectors. It involves many
design factors often overlooked in traditional buses. The
MULTIBUS@U bus architecture addresses the problem of
system reliability not only from a mechanical point of
view, but from protocol and electrical factors as well.
This product brief will discuss how the following
MULTIBUS U features resolve specific reliability problems while enhancing overall system reliability:

Figure 1 shows the iPSB timing with the lOOns period
divided into three intervals: driver timing, bus propagation, and receiver timing. The 40ns driver timing interval
takes into account driver logic delays and the capacitive
loading for a maximum of 20 loads spaced over 16.8
inches.

• Synchronous Timing
• Bus Parity
• Protocol Error Handling
• Bus Timeout
• Power Sequencing
• Eurocard/DIN Connectors
• Front Panel Design

BUS
CLOCK

• Backplane Design'

INCREASING ELECTRICAL RELIABILITY
I,.

Synchronous Timing for Enhanced Noise
Immunity
,

. . -.. ·,"·1
40ns

I 30ns

___

30nsl

WINDOW

Traditional buses, such as MULTIBUS I and VME, are
based on asynchronous timing where the' edges or transitions of the bus-control signals cause the bus to perform
its functions. Unfortunately, edge-sensitive timing is susceptible to external disturbances and noise. If noise causes a
signal to look as though it made a transition, the transition
is misinterpreted and a failure results.
The MULTIBUS U architecture addresses this problem by
using synchronous sampling of all signal lines. Both the
MULTIBUS U Parallel System Bus (iPSB) and the Local
Bus Extension (iLBXTM U bus) employ synchronous sampling for enhanced noise immunity. The iPSB serves as a
good example of the benefits of synchronous sampling.

Figure 1. IPSB Timing, Showing Synchronous Sample
Driving Stable Data Window
The bus propagation interval accounts for 25ns of signal
transit time and 5ns of potential clock skew. A signal traveling on the backplane creates reflections on itself and crosstalk on other signals. The signal tninsit time allows the
signal to propagate down and back on the backplane. It
also allows time for crosstalk to subside. This guarantees
that the signals have stabilized in spite of distance and
interference from other signals.

In the iPSB bus, all signals (address, data, control, and
arbitration) are driven and sampled with respect to a 10
MHz bus clock. The 10 MHz clock breaks the bus activity

15-27

The receiver interval consists of a·30ns receiver setup
time plus 5ns of hold time which extends into the next
cycle. This interval is the time the signal is stable prior to
sampling on the falling edge of the clock.

Guaranteed Electrical Compatibility
Synchronous sampling also has a less obvious benefit guaranteed electrical compatibility among boards. The
lOOns timing of the iPSB is based upon a worst-case
environment of 20 boards over a backplane length of
16.8 inches (0.8 inch separation). All derating for loading,
voltage margin, and skew is included. Thus, any number
of boards, up to 20, are guaranteed to work together.

Thus, the MULTIBUS II parallel bus timing creates a
65ns interval (driver timing plus bus propagation) when
the bus is completely immune to noise or external disturbances. That means during 65 % of the time interval, noise
causing a transition or level change is simply ignored. It
is only during the 35ns receiver setup and hold interval
that the bus timing is vulnerable to noise. During this interval, howeve~, the bus contains parity protection (to be
discussed in another section).

Electrical compatibility is much harder to achieve in
asynchronous buses. Because they are edge-sensitive,
asynchronous boards are naturally susceptible to changes
in signal edge rates and timing. When the number of boards
in a system change, edge rates and timing also change, in
some cases adversely affecting system reliability.

Comparable Performance at Higher
Speeds

The synchronous nature of the bus moves the point of
synchronization to the local bus of each board. When two
asynchronous CPUs communicate, synchronization between
them occurs between each CPU and its interface. This provides a better electrical environment for dealing with
reliability problems caused by metastability.

A conunon complaint about synchronous buses is that fixed
time increments limit performance compared to asynchronous buses. This may be true at slower bus clock speeds.
However, at 10 MHz the differences diminish. If both an
asynchronous and a synchronous bus use similar TTL technology for the bus drivers and receivers over the same
backplane length, they possess roughly the same bus timing. In other words, the driver timing, bus propagation,
and receiver intervals of both buses will be approximately
the same with nearly equal performance. However, as
we've seen, a synchronous bus offers a significant
. improvement in system reliability that easily justifies
its use.

Bus Parity Versus Memory Parity
At this point, it is important to distinguish between BUS
parity and MEMORY parity. (See Figure 2.) Both allow
the detection of errors. Memory parity protects data while
it is resident on a memory board. Bus parity, on the other
hand, protects address, control, and data while in transit
on the bus. In a sense, one complements the other in reliable systems. In both cases, it is possible to handle errors
via retry or other mechanisms.

MEMORY

DATA BYTE

I I I II II Ilpl -

MEMORY
LOGIC

I I
BUS INTERFACE
W/PARITY

ADDRESS
DATA CONTROL

PARITYlIlT STORED WITH
-

DATA TO PROTECT DATA
WHILE STORED

MEMORY LOGIC CHI:CKSI
ADDS PARITY WHEN
ACCESSED OR STORED

BUS INTERFACE ADOS/CHECKS
PARITY FOR EACH TRANSFER

ON BUS

II
)

WITH PARITY

Figure 2. Parity Protects Address Data and Control from Errors which could be Incurred on the iPSB Bus

15-28

Bus parity in the MULTIBUS II architecture provides
another level of electrical reliability by protecting the bus
from noise and external disturbances during the receiver
timing interval. It also protects the bus from failed interface components.

requested operation. As with other board-to-board errors,
the requesting board many retry with another request.
The last kind of error, called a negative acknowledge
error, occurs during a message transfer when resources
are not available in the receiving board. This is used for
flow control in the MULTIBUS II message passing protocol, a queue-based data movement protocol. Negative
acknowledge errors instruct the requesting board to retry
the operation at a later time, giving the replying board
time to process the data in its queue.

On the iPSB bus, the board driving the bus generates bus
parity. Address and data lines use byte parity, while con.trollines use nibble (4-bit) parity. All receiving boards
check parity during the receiver timing sampling interval.
If an error is detected, the BUS ERROR line is activated.
This stops activity on the bus and puts the bus into a ptedefined known state.

Bus Timeout

At this point, the system designer has a number of options:
retry the transfer, swap in a hot spare, log the error, ignore
it, or shut down the system gracefully. Which option he
chooses depends on his specific system requirements.
Basically, the protocol gives him the opportunity to
evaluate the situation and take appropriate action.

Another protocol reliability feature in the MULTIBUS II
architecture is the BUS TIMEOUT monitor in the Central
Services Module (CSM). If a bus transfer fails to complete
within a specified time (e.g., a failed board), the CSM,
which monitors all bus activity, activates the BUS TIMEOUT line. This stops all bus activity and places the bus in
a predefined known state for recovery. At this point, the
error is logged and normal bus activity can resume. As an
added feature, designers may define their own timeout
error Itandling policy.

PROTOCOL RELIABILITY

Board·to·Board Error Indications
Not all errors occur because of noise or component failure.
Sometimes they occur when one board asks another to do.
something it is not capable of doing. Although traditional
buses typically ignore these kinds of errors, they can cause
system failure just as noise can. The MULTIBUS II architecture offers a solution.

POWER SEQUENCING
The iPSB bus protOCol also contains a mechanism for
orderly handling of power-up and power-down sequencing .. For normal power on/off and unexpected power failures, timing of the RESET, OCLOW, and PROTect signals
coordinate the sequencing. The combination of the RESET
and DCLOW lines signal whether the power-up operation
is a warm or cold start of the system.

In the iPSB bus protocol, when one board cannot perform

the request, it simply informs the requesting board and allows it to attempt a retry. Five types of error indications
are supported: data, transfer width, continuation, notunderstood, and negative acknowledge.

Once the system is running, the DCLOW signal (driven
by the CSM) is used to indicate imminent loss ofOC
power (Figure 3). At this time, the system has a predetermined time to save state information. After that interval,

A data error indicates that the replying board has detected
an error with the requested data, for example a memory
parity error. Data transfer errors occur when the replying
board does not support the requested data width. For
example, the requesting board might ask for a 32-bit
transfer from an 8-bit device. After the replying board indicates the error has occurred, the requesting board can retry
the transfer with an 8-bit width.

II SYSTEM
STOPS

POWER I .
FAiliNG I

DCLOW~

Although the iPSB bus protocol allows for burst transfers
(multiple data cycles following one address cycle), not all
boards need to support this capability. If a requesting board
attempts a burst transfer with a hoard which does not support bursts, the replying board will return a continuation
error. The requesting board can recover by simply retrying
with the necessary address cycles.

'-------~I---------

------+---------'-t
I

PROT

1
I '----I

nilE FOR SYSTEII TO SAYE
STATUS, DATA B~OAE
TOTAL POWER LOSS

Trying to write to a read-only memory board is a good
example of a transfer-not-understood error. This type of
error occurs when the replying board does not SUpport the

Figure 3. Power Failure Control Lines

15-29

the CSM activates the PROTect line which prevents transitions on bus lines from affecting the system during
power loss.

blade. This connector approach offers advantages over the
board-edge style connectors. Among them are tighter
dimensional tolerances, reduced sensitivity to vibration,
improved protection from environmental contaminants, and
a larger number of cycles for insertion and removal.

MECHANICAL RELIABILITY
The MULTIBUS II mechanical specification is b~sed upon
the Eurocard form factor and DIN connectors. However,
unlike traditional bus architectures, it goes beyond these
mechanical' standards with a front panel design that helps
the system designer solve EMI (Electro-Magnetic Interference) and ESD (Electro-Static Discharge) problems.

FRONT PANEL SYSTEM

The MULTIBUS II front panel system (Figure 4), while
dimensionally compatible with standard Eurocard front
panels, offers several important advantages.
(Note that while this front panel technology is different from normal
Eurocard practice, the dimensioning is such that MUIIIBUS II boards
fit in any standard Eurocard packaging.)

Eurocard and DIN Connectors

Standard Eurocard front panels make it difficult to comply
with EMI and ESD regulations without the use of additional
shielding. Adjacent front panels form small, narrow slits
between boards which function like a slot antenna at some
frequencies. Through these narrow slits, EMI can enter or
exit the system and additional shielding is usually required.

The Eurocard family of mechanical specifications is noted
for its high reliability in rugged and industrial environments. The MULTIBUS II specification calls out the twoconnector 233mm by 220mm and single-connector lOOmm
by 220mm size boards. The two connector board contains
almost the same board area as the 6.75 by 12 inch MULTIBUS I board. That is, it is large enough to allow the implementation of single-board computers with I/O, CPU, and
memory onboard, even for 32-bit CPUs.

To solve this problem, the MULTIBUS II front panel is
U-shaped. From an EMI point-of-view, this makes the
front panel electrically thicker. While the size of the slit
between adjacent boards is the same as the standard Eurocard front panel, the electrically thicker front panel attenuates EMI which satisfies FCC EMI regulations and
protects the system from external EMI.

The DIN 41612 (also known as IEC 603.2) connectors are
96-pin two-piece connectors where each pin consists oLa
blade mating with two contact points on each side of the

DIN
CONNECTORS
"U" SHAPED FRONT

PANEL CHASSIS GROUND

RETA1~i:~~ ---HI.......

EJECTg:7~ ----~

LABELING
SPACE FOR:
110 CONNECTORS
LEOS
SWITCHES
TEST POINTS

Figure 4. MULTIBUS® II Front Panel System

15-30

The V-shaped front panel also adds structural rigidity to
the board and has captive retaining screws for securing
the board to the system. Shielded 110 connectors located
through the front panel eliminate the need for intermediary
cables and connectors. In addition, the front panel is at
chassis ground for protection against static discharge.

ground planes provide for good power distribution. Moreover, since they are in between each signal layer, they
reduce the opportunity for crosstalk due to coupling
between the signal layers.
On each signal layer, signal lines are laid out identically
to minimize signal skew across the backplane. To control
reflections, each signal line is passively terminated.

BACKPLANE DESIGN

Both power and ground connections are evenly distributed
across the connectors with 9 pins allocated for + 5 volts
and 15 for ground providing ample current and good
ground return paths.

Designed for reliability, the iPSB bus backplane consists
of six layers - three signal layers sandwiched between
three power and ground planes (Figure 5). The power and

SUMMARY

InI ~CONNECTOR

SIGNAL LAYER

SIDE)

Because the MULTIBUS II architecture addresses the problems of electrical, protocol and mechanical reliability, it
is superior to traditional buses in achieving overall system
reliability. Besides the mechanical reliability of its Eurocard form factor, DIN connectors, and backplane design,
the MULTIBUS II electrical protocol is highly immune to
noise and external disturbances because of its synchronous
sampling and bus parity. In addition, the agent error capability catches common operational errors. Other operational
concerns such as bus time-out and power sequencing are
fully specified.

InI

GROUND PLANE 1111
INTERNAL SIGNAL LAYER
POWER PLANE
GROUND PLANE "2
SIGNAL LAYER SOLDER SIDE

Figure 5. Backplane Design

15-31

GEOGRAPHIC ADDRESSING IN THE
MULTIBUS® II ARCHITECTURE
Although microcomputer board designers and system
integrators have different sets of requirements for building their products, some degree of overlap exists. Board
designers are concerned about factors like function and
life cycle costs, testing procedures, development time, and
manufacturing costs. System integrators need fast turnaround as well, but they are also faced with the challenge
of trying to customize a single board design by configuring it slightly differently for each application. Like the
board designer, system integrators are also concerned
with testing procedures and inventory costs.

TO 110 DEVICES

The MULTIBUSiIlII architecture satisfies the requirement!
of both board and system designers by defining a unique
address space called interconnect space which provides
geographic addressing. The following discussion will
center on the advantages that interconnect space and geographical addressing bring to system integration and
single-board computer design:

INTERCONNECT SPACE
ADDRESSING

• Easy system configuration
• Improved board testing productivity
• Efficient system testing

Figure 1. Board Configuration Using Interconnect Space.

• Reduced inventory costs
Since system software can write the board parameters
over the Parallel System Bus (iPSB bus), jumper stakes
are virtually eliminated. If jumpers are required, as in
switching from RS 232 to RS 422 drivers for example,
software can still read the jumpers to verify they were
installed correctly.

System Configuration Simplified
In traditional bus architectures, system configuration is
typically an arduous and complex process. The configurable features of boards are selected manually with jumper
stakes connected by wirewrap, a jumper plug or DIP
switches. With complex boards, the number of jumper
stakes often exceeds 150 and can exceed 300. Getting
the jumpers correctly connected is rarely accomplished
the first time.

Another benefit of auto-configuration, is that only one
version of the host operating system is needed to run
several configurations of the system. For example, if a
particular communications board is installed, the operating
system detects the board and properly configures it into
the system. Moreover, the slot picked to install the new
board is irrelevant because arbitration priority and interrupt control are configured independent of the slot in
which the board resides.

Interconnect space greatly simplifies system configuration
through geographic addressing (Figure 1). Critically important is the system's ability to identify which boards are
installed in each slot. This allows two identical boards to
be uniquely addressed and configured separately. Each
board is identified through one or more data bytes accessed
through interconnect space addresses. For example, the
manufacturer, the board name, the board type, and other
parameters are accessible in each· board's interconnect
space. Further information (e.g. memory size, memory
protection) that is available in each board's interconnect
space categorizes the exact configuration.

The toIJowlng are trademarks of Intel Corporation: MULTIBUS,

In addition, a level of fault-tolerant systems can be built
using geographic addressing. Redundant hot spare boards
can be installed into the system, but not configured by the
operating system until needed. Thus, in the normal operating mode, the redundant boards are not active on the
backplane. If a board fails, the operating system can
isolate the board from the bus, and then configure in the
new board. Again, human intervention is not needed to
complete the swap.

Isse.

15-32

Test procedure productivity also improves because several
configurations of a particular board can be tested in the
same general test suite. Since stake pin jumpers are mini·
mized, the test software can actually reconfigure a board
several times during the same test. For example, a I Mbyte
memory board can be tested in an entire 16 Mbyte address
range. Moreover, because human intervention is not
required, tests execute more smoothly.

More Productive Board Testing
Besides simplifying system configuration, interconnect
space supports registers for Built·in·Self·Tests (BISTs).
Diagnostic software resides on each board (in a PROM)
enabling an independent processor to execute the code.
That is, a secondary microcontroller and/or the primary
CPU can execute board level tests and store the results in
interconnect registers. The results can be accessed by any
other board in the system and displayed on each board's
front panel LED.

More Efficient System Testing
Once individual boards have passed board·level tests, they
still must be tested in the systems environment. System·
level testing becomes significantly more efficient because
of geographic addressing. For example, just one System
Confidence Test (SCT) could potentially exist for all
MULTIBUS II systems. The SCT can IQok at all the
boards in the system, examine BIST results, and execute
system test software based on the BISTs. In fact, detailed
results, including configuration parameters, can be dis·
played on a console (Figure 2).

Geographic addressing also makes board testing proce·
dures more productive. This is because one general·
purpose test suite is all that is required to test many dif·
ferent boards. The test software goes out on the iPSB bus,
identifies each board, and reads the results of the BIST for
each board. It can then report to the test engineer which
board failed what test. Additionally, because the same test
program executes for all boards, boards can be mixed and
matched on a single backplane.

REPOAT
BOARD
FAULT TO
SCREEN

Figure 2. System Confidence Test (SeT) Flow Diagram.

Another benefit of geographic addressing is remote diag·
nostics. Since interconnect registers are accessible over
the iPSB bus to any board, a remote terminal can address
the registers through a GAN (Global Area Network) card.
Thus, modem communication to a serial port in a system
gives the system designer a more versatile test
environment.

System integrators in particular can capitalize on the
advantages of MULTIBUS II system testing. Typically,
many configurations of a base system are available from a
system vendor. The system integrator only needs one sys·
tem test program (much like the board vendor described
above needs only one general·purpose test suite) to test
all of his different systems.

15·33

confusio!! regarding which configuration is standard from
the vendor, or which configuration is appropriate for the
application.

Lower Inventory Costs
Geographic addressing aids the industrial engineer in
managing board inventories. Since board vendors typically stock a few configurations of eaCh basic board,
jumpering boards is necessary for each individual con. figuration. In the MULTmUS n architecture, however,
different board configurations look the same so separate
bins of board inventory are not necessary. Thus, the cost
and effort required for inventory management can be
dramatically reduced.
The system builder stocks boards in the incoming parts
warehouse. Like the board vendor above, he can now
stock all the boards in the same bin, also reducing his
inventory efforts. Then when the system engineers integrate
their system, software configures the board to the needs of
the application. Because jumpering is reduced, there is less

Summary
Geographic addressing offers many important benefits to
single-board computer designers and system integrators
alike. All configuration parameters are stored in interconnect registers that sit on each board. Because the registers
are accessible over the iPSB bus, a single operating system
. can configure the system without operator intervention.
Both board wid system level testing procedures are
improved, as only one general test suite is needed.
Finally, inventories are managed more efficiently because
there are less board configurations not ·requiring separate
bins.
.

15-34

APPENDIX 1. MEMORY BOARD INTERCONNECT SPACE LAYOUT
Register
Number

Format

Global
Access

Local
Access

Default Value

312

310

320

340

RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIW
RIW
RIW
RIW
RIW
RIW
RIW

91H
OOH
4DH
45H
4DH
2FH
33H
31H
32H
OOH
OOH
OOH

01H
OOH
4DH
45H
4DH
2FH
33H
31H
30H
OOH
OOH
OOH

01H
OOH
4DH
45H
4DH
2FH
33H
32H
30H
OOH
OOH
OOH

01H
OOH
4DH
45H
4DH
2FH
33H
34H
30H
OOH
OOH
OOH

t
t
t
t
t

13H
OOH
OOH
OOH
OOH
OOH
OOH
OOH
OOH
01H
OOH
OOH
OOH
20H
OOH

RIO
RIO
RIW
RIO

OBH
02H
OOH
OOH

Header Record

o (OOH)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31

(01 H)
(02H)
(03H)
(04H)
(05H)
(06H)
(07H)
(08H)
(09H)
(OAH)
(OBH)
(OCH)
(ODH)
(OEH)
(OFH)
(10H)
(11H)
(12H)
(13H)
(14H)
(15H)
(16H)
(17H)
(18H)
(19H)
(1AH)
(1BH)
(1CH)
(1DH)
(1 EH)
(1 FH)

Vendor 10, Low Byte
Vendor 10, High Byte
Board 10, character 1
Board 10, character 2
Board 10, character 3
Board 10, character 4
Board 10, character 5
Board 10, character 6
Board 10, character 7
Board 10, character 8
Board 10, character 9
Board ID, character 10
Intel Reserved
Intel Reserved
Intel Reserved
Intel Reserved
Hardware Test Revision #
Class 10
RFU
RFU
RFU
RFU
RFU
RFU
General Status
General Control
BIST-SUPPORT-LEVEL tt
BIST-DATA-IN
BIST-DATA-OUT tt
BIST-SLAVE-STATUS tt
BIST-MASTER-SLAVE
BIST-TEST-ID tt

Binary
Binary
, ASCII
ASCII
ASCII
ASCII
ASCII
ASCII
ASCII
ASCII
ASCII
ASCII
BCD+
BCD+
BCD+
BCD+
BCD+
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary

RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIO
RIW
RIO
RIW
RIO
RIO
RIW
RIO

Protection Record
32
33
34
35

(20H)
(21H)
(22H)
(23H)

Protection Record Type
Record Length
Protection Level Register
Reserved for Future Use

Binary
Binary
Binary
Binary

15-35

RIO
RIO
RIO
RIO

APPENDIX 1. MEMORY BOARD INTERCONNECT SPACE LAYOUT (Con't)
Register
Number

Format

Global
Access

Local
Access

Default Value
312

310

,320

340

01H
05H
07H
OOH
01H
A1H
OOH

01H
05H
OFH
OOH
01H
A1H
OOH

01H
05H
1FH
OOH
01H
A1H
OOH

01H
05H
3FH
OOH
01H
A1H
OOH

06H
06H
FFH
OOH
OOH
OOH
OOH
OOH

06H
06H
FFH,
OOH
OOH
OOH
OOH
OOH,

06H
06H
FFH
OOH
OOH
OOH
OOH
OOH

Memory Record
36
37
38
39
40
41
42

(24H)
(25H)
(26H)
(27H)
(28H)
(29H)
(2AH)

Memory Record Type
Record Length
Memory Size - 1 low byte
Memory Size - 1 high byte
Memory Control Register
Memory Status Register
Reserved for Future Use

Binary
Binary
Binary
Binary
Binary
Binary
Binary

RIO
RIO
RIO
RIO

RIW

RIO
RIO

IPSB Control Board
43
44
45
,46
47
48
49
50

(2BH)
(2CH)
(2DH)
(2EH)
(2FH)
(30H)
(31H)
(32H)

iPSB Control Record Type
Record Length
iPSB Slot 10
iPSB Arbitration 10
iPSB Error Register
iPSB ControllStatus Register
iPSB Diagnostic Register
Reserved for Future Use

Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary

RIO
RIO
RIO

RIO
F.l/O
RIO

RIW
RIW
RIW
RIW

RIO

06H
06H
FFH
OOH
OOH
OOH
OOH
OOH

IPSB Memory Record
51 (33H)
52 (34H)

iPSB Memory Record Type
Record Length

Binary
Binary

RIO
RIO

02H
05H

53
54
,55
56

iPSB Start Address low byte
iPSB Start Address high byte
iPSB End Address low byte
iPSB End Addless high byte

Binary
Binary
Binary
Binary

RIW
RIW
RIW
RIW

02H
05H
\

FFH
FFH
OOH
OOH

FFH
FFH
FFH ' FFH
OOH
OOH
OOH
OOH

FFH
FFH
OOH
OOH

Reserved for Future Use

Binary

RIO

OOH

(35H)
(36H)
(37H)
(38H)

57 (39H)

ILBX'Y II Memory Board
58 (3AH)
59 (3BH)

iLBX II Memory Record Type
Record Length

Binary
Binary

RIO
RIO

03H
07H

60
61
62
63
64

iLBX 1/ Start Address low byte
iLBX 1/ Start Address high byte
iLBX 1/ End Address low byte
iLBX 1/ End Address high byte
iLBX 1/ Clock Frequency
iLBX II Slot 10

Binary
Binary
Binary
Binary
Binary

RIW
RIW
RIW
RIW
RIW

RIW
RIW
RIW
RIW
RtW

FFH
03H
OOH
DOH
DCH

FFH
03H
OOH
OOH
DCH

Binary
Binary

RIO
RIO

OOH
OOH

(3CH)
(3DH)
(3EH)
(3FH)
(40H)

65 (41 H)
66 (42H)

Reserved for Future Use

15-36 '

APPENDIX 1. MEMORY BOARD INTERCONNECT SPACE LAYOUT (Con't)
Register
Number

Format

Global
Access

Local
Access

Default Value
312

310

320

340

04H
08H
03H
OOH
OOH
OOH
OOH
OOH
OOH
OOH

04H
OSH
03H
OOH
OOH
OOH
OOH
OOH
OOH
OOH

04H
08H
03H
OOH
OOH
OOH
OOH
OOH
OOH
OOH

05H
05H
1FH
OOH
03H
OOH
OOH

05H
OSH
1FH
OOH
03H
OOH
OOH

05H
05H
1FH
OOH
03H
OOH
OOH

FFH

Memory Parity Record
67
68
69
70
71
72
73
74
75
76

(43H)
(44H)
(45H)
(46H)
(47H)
(48H)
(49H)
(4AH)
(4BH)
(4CH)

Memory Parity Record Type
Record Length
Parity Control Register
Parity Status Register
Bank Status Register
Error Offset byte 0
Error Offset byte 1
Error Offset byte 2
Error Offset byte 3
Reserved for Future Use

Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary
Binary

RIO
RIO

RIW

RIO
RIO
RIO
RIO
RIO
RIO
RIO

Cache Memory Board
77
78
'79
80
81
82
83

(4DH)
(4EH)
(4FH)
(50H)
(51H)
(52H)
(53H)

Cache Memory Record Type
Record Length
Cache Size - 1 low byte
Cache Size - 1 high byte
Cache Entry Size - 1
Cache Control Register
Reserved for Future Use

Binary
Binary
Binary
Binary
Binary
Binary
Binary

RIO
RIO
RIO
RIO
RIO

RIW

RIO

05H
05H
1FH
OOH
03H
OOH
OOH

RIO

FFH

End of Template Record
84 (54H)
Note:

EOT Record Type

Binary

RIO

These registers are defined for Intel's use. The values in these registers are dependent upon
the revision of the board and are subject to change.

The BIST_DATA-OUT and the BIST_SLAVE_STATUS registers are RIW registers locally.
However, the Test Handler that resides on the iSBC@ MEM/3XX board does not allow off-board
writes to these registers.

ttt

BCD + has the same encoding as a normal BCD signal except that OFH denotes a null, and the
remaining unused encodings are reserved.

tttt

The registers indicated with the italicized type are the nine registers that must be programmed
before the board can operate in a system. Refer to the Configuration Sequence section for
more information.
R/O = READ/ONLY
RIW m READIWRITE
DEFAULT VALUE = POWER UP DEFAULT

15-37

MESSAGE PASSING IN THE MULTIBUS® II ARCHITECTURE
The demand for increased functionality and processing
power in microcomputer systems is growing faster than
single-processor solutions can satisfy. Multiprocessing,
which allocates individual microprocessors to different
functions within a system, has proven to be a viable solution, largely because of the advent of inexpensive memory
and CPUs. Today, multiprocessing is highly evident in
computers where microprocessors are found not only on
general-purpose CPU boards, but on intelligent disk controller boards, communication boards, and other specialized boards.

with the idea of improving system performance and
reducing complexity.
The MULTIBUS'" II architecture employs an innovative
mechanism called message passing to improve performance and simplify the implementation of multiprocessing
computer systems. This product brief will discuss message
passing and the benefits it brings to system design.

Functional Partitioning and
Microprocessor Communications
There are two general types of multiprocessing: one that
employs transparent multiprocessing in a tightly coupled
system architecture and another that uses a heterogeneous
mix of processors in a loosely coupled architecture
(Figure I).

To build multiprocessor computer systems, a designer
selects a set of boards that solves his application requirements. The system bus is the vehicle for connecting the
boards together and the medium through which intelligent
boards communicate. Unfortunately, until now, conventional buses have not addressed this communication need

Figure lAo Transparent Multiprocessing all the same CPUs

Figure lB. Heterogenous Mix of Processors-Different Proce,ssors Selected to Satisfy Different Aspects of an Application

15-38

problems as well as to facilitate the more complex feature
of intertask communications required for a multitasking
operating system. A virtual interrupt is a message that
contains a destination and a source address and two bytes
of qualifying information (Figure 2). In addition, up to 28
bytes of user data can be included in the interrupt. The
entire message is sent as one packet on the system bus at
the 40-megabyte-per-second maximum bus rate.

A functionally partitioned system is characterized by the
use of a separate CPU and memory on a board with an
optimized local environment. Other boards communicate
via an interface which is independent of the implementation of the board. Therefore, future enhancements in the
functional module can be easily integrated without redesigning the entire system. Also, since lIO, CPU, and
memory technology evolve at different rates, a functionally partitioned system can be upgraded as technology
allows, so the system integrator's products stay on the
technological treadmill.

When the entire process of interrupt signaling is evaluated,
including the software involved, sending a virtual interrupt
with user data can be faster than an interrupt line approach.

Key to the success of a functionally partitioned system is
the mechanism for communication between the various
fun~tions. The MULTIBUS II message-passing feature
was designed to resolve the problems of communication in
multiprocessing systems by providing a unique approach
to intermodule interrupts and data movement. In addition,
the MULTIBUS II solution can be implemented in a single
coprocessor device that augments the CPU, providing a
cost-effective solution as well.

Data Sharing
Traditionally, processors share data on a bu~ through a
common memory area. This memory area is either globally
available or a dual-port into one of the processors' local
memories. There are several performance issues with
these approaches.
First, it is necessary for one or both of the processors to
use the system bus to reach the memory. When a processor
uses the bus, it typically incurs an arbitration delay and the
possibility of having to wait for other bus users to complcte
their activities.

Solving the N x N Interrupt Problem
In traditional systems, interrupts are propagated via discrete interrupt lines. To get n processors to signal one
another unambiguously, the bus needs n x (n -1) interrupt
lines (this phenomenon is called the NxN problem).
Since existing buses usually provide 7 or 8 interrupt lines,
multiple sources of interrupts are assigned to a line, and
the interrupted processor must poll to determine the
source.

In a dual-port approach, only one processor incurs the
bus delay. However, the local processor performance is
adversely affected by two factors; The first is the dualport control logic . The second is contention from the processor accessing the local memory through the dual-port
from the system bus.

In contrast, the MULTIBUS II architecture uses message
passing in a virtual interrupt scheme to resolve N x N

o-Q
QW

o-Q
OW

z!!l

z!!l
SIT 24

z!!l

M. ,o;;;AuK "

z!!l

81T 18
ILl

"iI,

~.~

"::>0
II:

iii

I
1SIT8

.:~

ffi;::

BITO

~
~

INTERRUPT

INTERRUPT WITH DATA
MESSAGE DATA MOVEMENT

i'PSB TRANSFERS
(@ 40 MBVTElSEC
ONE/lOONS CLOCK)

Figure 2. Message Format-Virtual Interrupt is First Two Transfers with Optional Data

15-39

III the MULTIBUS n architecture, the mechanism for
moving data from one board to another is built into the
MULTIBUS n bus interface hardware. The component
which supports the requirements of message passing is
referred to as the message passing coprocessor (MPC). A
pafr of MPC devices, one on each communicating intelligent board, moves the data from .one board to another.
Figure 3. shows atypicai message-passirig system with
a host CPU and a disk controller using MPC devices to
communicate.

to coordinate and communicate the location of the shared
memory, performance can further degrade, Finally, shared
memory designs are also wasteful of bus bandwidth, complicatedto debug, and are not easily extensible to beyond
a single pair of communicating CPUs.

The MULTIBUS@ II Solution
The ideal shared data system would have one CPU signal
.to another that it has data to share, followed by it becoming
available to the second processor within its local memory.
An example might be a disk system with a program or a
set of data that a second processor spends a large portion
of its time accessing, Getting the program or data quickly
into the,local memory of the second CPU is the key to
achieving a performance improvement.

For systems where the data to be shared is small and infrequently accessed, the performance impact may be trivial.
However, as shared data needs increase, the CPUs pay a
noticeable penalty. At'this point, the system bus can also
become a bottleneck. When systems software is required'

MPC
UF

MULTIBUS' II PARALLEL SYSTEM BUB
FILE TRANSFER MESSAGES
I,

2. II

FILE REQUEST
BUFFER REQUEST
BUFFER GRANT

4 ...
DATA

Figure 3. File Transfer Using Messages
The packets that are communicating and moving data
between the MPC devices are transferring data at maximum bus bandwidths - 40 megabytes per second or lOOns
per -32 bits. This constitutes a significant performance
improvement, over traditional 'global memory and
dual-port memory transfers.

In this example, the following is the sequence of events
that occurs when the host desires a file:
1. The host requests the file using an interrupt message
that uses the data: field to describe the file.

2. The disk controller responds back to the host after
retrieving the file with a request for memory.

By comparing this rate of data movement with today's
VLSI devices, 40 megabytes/second is about five times as
fast as the fastest microprocessor devices. The MPC performs a speed-matching function between the bus and the

3. The data is then arranged into 32-byte packets, and
each packet is transmitted over the bus until all the
data is at the host. The transfer is theri complete,

15·40

LOCAL BUS

Figure 4. Message Passing Coprocessor Dataflow
local microprocessor environment. Between the system
bus and the local bus, first-in first-out memories perform
the speed matching. Figure 4 shows the data flow in an
MPC device.

message, it is packetized and moved at 40 megabytes per
second over the iPSB bus. As a result, any bus overhead
is paid only once per interrupt message or once per 32
bytes of the data transfer.

Data messages are broken into 32-byte packets because of
the speed difference between the bus and the data rate that
can be supported on a board. Since even the fastest microprocessor DMA devices cannot keep pace with these datarates, and real-time performance is affected if the packets
are too large, it is advantageous to break a large data
movement into small pieces and let the bus interface
reconnect the pieces.

In addition, the CPUs never pay a penalty for arbitration
or contention on the bus, nor does either CPU incur any
performance penalties associated with dual port memory
operation. The wait states that a CPU would traditionally
incur are either greatly reduced or eliminated. Furthermore, if the boards in our example have a local DMA
device, the CPUs are free to perform other tasks while the
transfer is occurring.

A 32-byte message packet only takes one microsecond of
bus time (2-cycle header plus 8 cycles data x 100 ns/cycle).
This allows other boards to use the bus between the packets
that make up a large data movement. Also, the system bus
is not tied up for long periods of time when large data
movements occur. For real-time applications, interrupts
may be sent without having to wait for a long data transfer
to complete.

One final point - it is important to understand that the
MULTIBUS II architecture also supports the traditional
methods of communication such as dual-port and global
memories. Message passing is an incremental capability.

Summary
The original design goals for message passing were to
provide a performance enhancement and make it easier
to implement multiprocessing systems. The achievement
of these goals have resulted in the following benefits: message passing has solved the N x N interrupt problem; it has
provided a high-performance solution to functionally partitioned systems; and finally, MULTIBUS II message passing can be implemented in a single-chip solution, thereby
providing a cost-effective answer for today's system
design.

Examining the Performance Benefits
A closer look at the example in Figure 3 shows the impact
. message passing has on system performance. Note that during the disk me request and transfer, neither CPU has to
access the bus. The interrupt-like messages that request
and set up the transfer as well as the transfer itself all
occur through the MPC. When the MPC sends a message,

15-41

iSBXTM Expansion Modules

ISBXTII 279 DISPL""

SUBS"ST~M

BI6B-SPBED 61ttP11lfJSlWINDflWIN6FtJR 'R/fIXe II SYSI'EMS

The ISBX 279 Is a complete graphics subsystem designed to provide users of Intel's iRMX II real·
time systems with advanced Interactive graphics runctlons. Based on Intel's 82786 Display
Processor. the ISBX 279 elTlclently off·loads bitmap and window manipulation rrom the application
CPU. preserving real·tlme system performance. High·speed windowing. ASCII terminal emulation
with system console support. and powerful drawing commands are provided in a convenient system
expansion package. Complete software support. Including iRMX II Device Driver. Application
Interface Libraries for Co 286 and PIJM 286. and loadable fonts. provides a hlgh·level. network
.transparent Interface. allowing application portability across Intel's real·time platforms and
shortening application development time.
.

I'EtI'IJIlES:
•
•
•
•
•
•
•
•

Intel 82786 Display Processor
iRMX II Operating System Device Driver
High·LeveI Language Interface
System Console Support Kits
Windowed User Interface
Terminal Emulator
Standard GraphiCS Command Interpreter
Net'Wrk Transparent Graphics Protocol

inter--------------------------------The iSBX 279 Display Subsystem

11It.4 CapuraLlon.assulJll.'S no rcspun:dbllll.y fur lbe usc or any ClrcUilry oUIer Ulan circuitry embodied in an rriCl pnxlUd.. Nu ~ drcuU, palCr&111EIIIIeI8I'C
Implied.lnfwmaLion cortalned hc:n:ln BU~ Pf'C\'iOUSI) Ilunllshcd speclflClUons on Lhcac tblcr:s from Imrl and Is aublUL1 tu chance wt\hcK& IKIJm.
Sepoanbcr. 1088

Order ~m"'" 280661-001

Iii I.... Olrporau... 1968

16-1

FEATURES
IN'I'EI. B27B6 DISrUI' rROCESSOR

'l'ERMINAI. EMIJI.A'I'OR

The Intel 82786 Display Processor is used to provide nearly
instantaneous window manipulation. Together with the iSBX
279 firmware and iRMX II software. this allows mUltiple
overlapping windows displaying graphical information or
terminal sessions to be presented simultaneously.

The terminal emulator allows existing applications to run in
a window without modification. The terminal emulator is
compatible with the iRMX II Human Interface. the AEDIT
text editor. iRMX Virtual Terminal software. and other
terminal oriented programs that can be configured to
operate with a smart CRT. By using the virtual terminal
capability. it is possible to access any host on an OpenNE:T"'
network from a single display.

.RMX " OrERA'I'ING SI'S'I'EM DEVICE
DRIVER
The IRMX II Interactive Configuration Utility provides the
screens needed to configure the iSBX 279. The device driver
is provided as part of the iSBX 279 upgrade kit. The device
driver manages the device interface and performs 1/0 on
behalf of application requests through deviceifile
conn!X:tions in the iRMX II lOS. The device driver is
compatible with iRMX II Terminal Support. This speeds
development by allowing the programmer to remain
unaware of the device interface. instead concentrating on the
application code needed for the target system..

S'I'ANDARD GRArHICS COMMAND
IN'I'ERrRE'I'ER
The graphics command interpreter is an implementation of
the Computer Graphics Interface (CGI). providing an
interface that is Gonsistent with current ISO-CGM and ANSICGI standardization efforts. while extending this interface to
include Window and bitmap manipulation functions. The
interface is fully compatible with Inters existing iVDI 720
R1.8 interface providing a dir!X:t upgrade for iSBC 186n8A
applications.

II1GII-l.EVEI. UNGIJAGE INTERFACE
Application Interface libraries are provided for C-286 and
PUM 286. The application interface is a rich set of graphics
and windowing primitives that prOVide standard drawing
functions with complete control of bitmaps and windows.
This allows the application programmer to quickly begin
writing sophisticated real~time graphics applications using a
portable interface foriRMX II systems.

SI'S'I'EM CONSOl.E slJrroll.'I' "''I'S
The iSBX 279 is designed to be the system console for iRMX
II MULTIBUS@ systems based on iSB

DMA
SIGNAL
GENERATOR

READ
WINDOW
GENERATOR

8272
FDC

-t

TIMING
AND
PLL

READ
DATA
SHAPING

lit

WRITE
PRECOMPENSATION

ADDRESS, DATA, AND CONTROL BUS

ISBX'"BUS

1
503810-2

Figure 1. Block Diagram of iSBXTM 218A Board

16-7

intJ

iSBXTM 218A CONTROLLER

DMA OPERATION-The iSBX 218A module can be
used either with or without a DMA controller on the
host board: Standard DMA controllers provide a
DACK (DMA Acknowledge) signal for proper DMA
operation with the 8272. The iSBX 218A's on-board
DACK generator provides the interface to allow the
iSBX 218A module to be used with DMA controllers
such as Intel's 8089 and 80186 processors that do
not provide a DACK signal.

is a right-angle header with locking tabs for security
of connection.
PROGRAMMING-The powerful 8272 FDC circuit is
capable of executing high-level commands that simplify system software development. The device can
read and write both single and multiple sectors. CRC
characters are generated and checked automatically. Recording density is selected at each Read and
Write to support the industry standard technique of
recording basic media information on Track 0 or
Side 0 in single density, and then switching to double density (if necessary) for operations on other
tracks.

SPECIFICATIONS
Compatibility

PROGRAM INITIATION-All diskette operations
are initiated by standard iSBX bus input/output (I/O)
operations through the host board. System software
first initializes the controller with the operating characteristics of the selected drive. The diskette is then
formatted under program control. Data transfers occur in response to commands output by the CPU.

CPU-Any single board computer or I/O board implementing the iSBX bus interface and connector.
Deviees'-Double or single density standard (8")
and mini (51,4") flexible disk drives. The'drives may
be single or double sided. Drives known to be compatible are indicated in the table to the right.

DATA TRANSFER-Once a diskette transfer operation has been initiated, the controller will require a
data transfer every 13 microseconds (double density) or 26 microseconds (single density). Most CPUs
will operate in a polled mode, checking controller
status and transferring bytes when the controller is
ready. Boards utilizing the Intel 8080 chip, such as
the iSBC 80/10B board, will be restricted to single
density operation with the iSBX 218A Controller, due
to these speed requirements.

Standard (8" )
Caldisk
Remex
Memorex
MFE
Siemens
Shugart
Shugart
Pertee
CDC

Mini (5Y4")
Shugart
Shugart
Mieropolis
Pertee
Siemens
Tandon
CDC
MPI

143M
RFD 4000
550
700
FDD 200-8
SA 850/800
SA 860/810
FD650
9406-3

450/400
460/410
1015-IV
250
200-5
TM-100
9409
51/52191/92

Data Organization and Capacity
Standard Size Drives
Single Density

Double Density
IBM System 34

Non-IBM

IBM System 3740

Non-IBM

Bytes per Sector

256 1 512 1 1024

20481409618192

128 1 256 1 512

10241204814096

Sectors per Track

1 15

Tracks per Diskette

Bytes per Diskette
(Formatted, per
diskette surface)

512,512
(256 bytes/sector)
591,360
t512 bytes/sector)
630, 784
(1024 bytes/sector)

1 2

1 1

630,784

16-8

1 15

77
256,256
(128 byte/sector)
295,680
(256 bytes/sector)
315,392
(512 bytes/sector)

1 2

1 1

315,392

iSBXTM 218A CONTROLLER

Diskette-Unformatted IBM Diskette 1 (or equivalent single-sided media); unformatted IBM Diskette
2D (or equivalent double-sided).

Electrical Characteristics

Equipment Supplied

Environmental Characteristics

iSBX 218A Controller

Temperature: O°C to + 55° (operating); - 55°C to
+ 85°C (non-operating).

Power Requirements:

Reference Schematic
Controller-to-drive cabling and connectors are not
supplied with the controller. Cables can be fabricated with flat cable and commercially-available connectors as described in the iSBX 218A Hardware
Reference Manual.

Humidity:

Nylon Mounting Screws and Spacers

3.15 inches (8.0 cm)

Height:
Length:

0.83 inches (2.1 cm)
7.5 ounces (19.1 cm)

Weight:

4.5 ounces (126 gm)

Transfer Rate (K bytes/sec)

1.7A max.

Up to 90% Relative Humidity without
condensation (operating); all conditions without condensation or frost
(non-operating).

145911-001- iSBX 218A Flexible Disk Controller
Hardware Reference Manual (NOT
SUPPLIED).
Reference manuals may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, California 95051.

Mounting: Occupies one double-wide iSBX MULTIMODULETM position on boards; increases board height (host plus iSBX board) to
1.13 inches (2.87 cm).

Drive Characteristics

Reference Manual

Physical Characteristics
Width:

+ 5VDC

Standard Size

Mini Size

Double/Single Density

62.5/31.25

31.25/15.63

Disk Speed (RPM)

360

300

Step Rate Time
(Programmable)

1 to 16 ms/track in
1 ms increments

2 to 32 ms/track in
2 ms increments

Head Load Time
(Programmable)

2 to 254 ms in
2 ms increments

4 to 508 ms in
4 ms increments

Head Unload Time
(Programmable)

16 to 240 ms in
16 ms increments

32 to 480 ms in
32 ms increments

ORDERING INFORMATION
Part Number Description

SBX 218A

Flexible Disk Controller

16-9

iSBXTM 311
-ANALOG INPUT MULTIMODULETM BOARD -

•

Low Cost Analog Input Via iSBXTM
MULTIMODULETM Connector

Differential/16 Single-Ended, Fault
• 8Protected
Inputs
20 mV to 5V Full Scale Input Range,
• Resistor
Gain Selectable

•+
•
•

Unipolar (0 to + 5V) or Bipolar (- 5V to
5V) Input, Jumper Selectable

12-Bit Resolution Analog-To-Digital
Converter

18 KHz Samples Per Second
Throughput to Memory

The Intel iSBX 311 Analog Input MULTIMODULE board provides simple interfacing _of non-isolated analog
signals to any iSBC board which has an iSBX compatible bus and connectors. The single-wide iSBX 311 plugs
directly onto the iSBC board, providing data acquisition of analog signals from eight differential or sixteen
single-ended voltage inputs,jumper selectable. Resistor gain selection is provided for both low level (20 mV
full scale range) and high level (5 volt FSR) Signals. Incorporating the latest high quality IC components, the
iSBX 311 MULTIMODULE board provides 12 bit resolution, 11 bit accuracy, and a simple programming interface, all on a low cost iSBX MULTIMODULE board.

280233-1

16-10

October 1986Order Number: 280233-002

iSBXTM 311 BOARD

For noisier environments, differential input mode can
be configured to achieve 8 separate differential signal inputs, or 16 pseudo-differential inputs.

FUNCTIONAL DESCRIPTION
The iSBX 311 Analog Input MULTIMODULE board is
a member of Intel's growing family of MULTIMODULE expansion boards, designed to allow
quick, easy, and inexpensive expansion for the Intel
single board computer product line. The iSBX 311
Analog Input MULTIMODULE Board shown in Figure
1, is designed to operate with a variety of microcomputer modules that contains an iSBX bus connector
(P1). The board provides 8 differential or 16 singleended analog input channels that may be jumper-selected as the application requires. The MULTIMODULE board includes a user-configurable gain, and a
user-selectable voltage input range (0 to + 5 volts,
or - 5 to +5 volts). The MULTIMODULE board receives all power and control signals through the
iSBX bus connector to initiate channel selection,
sample and hold operation, and analog-to-digital
conversion.

Resolution
The iSBX 311 MULTIMODULES provide 12-bit resolution with a successive approximation analog-todigital converter. For bipolar operation (- 5 to + 5
volts) it provides 11 bits plus sign.

Speed
To A-to-D converter conversion, speed is 35 microseconds (28 KHz samples per second). Combined
with the sample and hold, settling times and the programming interface, maximum throughput via the
iSBX bus and into memory will be 54 microseconds
per sample, or 18 KHz samples per second, for a
single channel, a random channel, or a sequential
channel scan. A-to-D conversion is initiated via the
iSBX connector and programmed command from
the iSBC base board. Interrupt on end-of-conversion
is a standard feature to ease programming and timing constraints.

Input Capacity
Sixteen separate analog signals may be randomly or
sequentially sampled in single-ended mode with the
sixteen input multiplexers and a common ground.

HIGH
IMPEDANCE

BUFFER

AMP
8 CHANNEL
INPUT

MULTI·

SIGNAL

ANALOG

GROUND

RESISTOR

PLEXER

INPUT
SIGNALS

'NTR

GAIN

"....

GAIN
SELECT

&
OFFSET
ADJUST

SAMPLE

DATA

HOLD

LINES

AMP

START
CONVERSION

AND
CHANNEL
SELECTOR
LOGIC

280233-2

Figure 1. iSBXTM 311 Analog Input MULTIMODULETM Board

16-11

inter

iSBXTM 311 BOARD

Accuracy
High quality components are used to achieve 12 bits
resolution and accuracy of 0.035% full scale range
± % LSB. Offset and gain are adjustable to
± 0.024 % FSR ± % LSB accuracy at any fixed tem. perature between O·C (gain = 1). See specifications
for other gain accuracies.

Gain

SPECIFICATIONS

To allow sampling of millivolt level signals such as
strain gauges and thermocouples, gain is made configurable via user inserted gain resistors up to 250 x
(20 millivolts,full scale input range). User can select
any other gain range from 1 to 250 to match his
application;

The host iSBC microcomputer addresses the iSBX
311 MULTIMOOULE board by executing IN or OUT
instructions to the iSBX 311 MULTIMOOULE as one
of the legal port addresses. Analog-to-digital conversions can be programmed in either of two modes: 1.
start conversion and poll for end-of-conversion
(EOC), or 2. start conversion and wait for interrupt
(INTRO/) at end of conversion. When conversion is
complete as signaled by one of the above techniques, INput instruction read two bytes (low and
high bytes) containing the 12 bit data word plus
status information as shown below.
OUTput Command-5elect input channel and start
ponversion.
Bit Position
Input Channel

76543210
I

I c31 c21 C1 I CO I

INput Data-Read converted data and status (low
byte) or Read converted data (high byte). Reads can
be with or without reset of interrupt request line
(INTRO/).
Bit Position
Low/Status Byte

7 6 5 43

Inputs-8 differential. 16
lectable.

single~ended.

Jumper se-

Full Scale Input
Voltage Range---5 to +5 volts (bipolar). 0 to +5
volts (unipolar). Jumper selectable.
Gain-User-configurable through installation of two
resistors. Factory-configured for gain of X1.

OPERATIONAL DESCRIPTION

High Byte

Fastest data conversion and transfer to memory can
be obtained by dedicating the microcomputer to setting the channel address/starting conversion, pOlling
the status byte for EOC/, and when it comes true,
read the two bytes of the conversion and send the
start conversion/next channel address command.
For multitasking situations it may be more convenient to use the interrupt mode, reading in data only
after an interrupt signals end of conversion.

Resolution-12 bits over full scale range (1.22 mV
at 0-5V, 5 p,V at 0-20 mV).
AccuracyGain
1
5
50
250

Accuracy at 25"C
± 0.035% ± % LSB
± 0.035% ± % LSB
±0.035% ± % LSB
±0.035% ± % LSB

NOTE:
Figures are in percent of full scale reading. At any fixed
temperature between O· and 60"C, the accuracy is adjustable to ±O.035% of full scale.

Dynamic Error-±0.015% FSR for transitions.
Gain TC (at Gain = 1): 30 PPM per degree centigrade (typical); 56 PPM per degree centigrade
. (max).

10310~011001Istart/lbusY/IEoc/1

I011 I 010 I 091 osl 071 061 051 041

16-12

iSBXTM 311 BOARD

Offset TC (In percent of FSRI"C):
Gain
1
,
5
50
250

Electrical Characteristics (from iSBX
connector)

Offset
0.0018
0.0036
0.024
0.116

Vee = ±5 volts (±0.25V), lee = 250 mAmax
Vdd = + 12 volts (± 0.6V), Idd = 50 mAmax
Vss = -12 volts (±0.6V), Iss = 55 mAmax

Offset IS measured with user·supplled 10 PPMI'C gain resistors In·
stalled.

Environmental Characteristics

Input Protection- ± 30 volts.

Operating Temperature:

o· to 60·C (32· to 140·C)

Relative Humidity:

to 90% (without condensation)

Input Impedance-20 Mfl. (minimum).
Conversion Speed-50 ms (nominal).

Reference Manuals

Common Mode Rejection Ratio-60 db (minimum).

142913- iSBX 311 Analog Input MULTIMODULE
Board Hardware Reference Manual (order separately)

Sample and hold-sample time 15 ms.
Aperture-hold aperture time: 120 ns.

Related· Literature

ConnectorsCenters
in
cm

Interface

Pins
(Qty)

P1 iSBX Bus

0.1

J1 8/16
Channels
Analog

0.1

230973-Distributed Control Data Book

Mating
Connectors

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051.

iSBCiSBX
connector
3m 3415-000 or
0.254 T1 H312125 or
iCS 910 cable
0.254

ORDERING INFORMATION
Part Number Description
SXB 311
Analog Input MULTIMODULE Board

Physical Characteristics
Width: 9.40 cm (3.7 inches)
Length: 6.35 cm (2.5 inches)
Height: 2.03 cm (0.80 inch) MULTIMODULE board
only
2.82 cm (1.13 inches) MULTIMODULE and
iSBC board
Weight: 68.05 gm (2.4 ounces)

16-13

iSBXTM 328
ANALOG OUTPUT MULTIMODULETM
BOARD
•

Low Cost Analog Output Via iSBXTM
MULTIMODULETM Connector

•

8 Channel Output, Current Loop or
Voltage in any Mix

•

4-20 mA Current Loop; 5V Unipolar or
Bipolar Voltage Output

•

12-Bit Resolution

• 0.035% Full Scale Voltage Accuracy
@

•

25°C

Programmable Offset Adjust in Current
Loop Mode

The Intel iSBX328 MULTIMODULE board provides analog signal output for any intelligent board having an
iSBX compatible bus and connector. The single-wide iSBX 328 plugs directly onto the host board, providing
eight independent output channels of analog voltage for meters, programmable power supplies, etc. Voltage
output can be mixed with current loop output for control of popular 4-20 mA industri.al control elements. By
using an Intel single chip computer (8041) for refreshing separate sample-hold amplifiers through a single 12
bit DAC, eight channels are contained on a single MULTIMODULE board for high density and low cost per
channel. High quality analog components provide 12 bit resolution, and slew rates per channel of 0.1V per
microsecond. Maximum channel update rates are 5 KHz on a single channel to 1 KHz on all eight channels.

280234-.1 .

16-14

October 1986
Order Number: 280234-001

intJ

iSBXTM 328 BOARD

FUNCTIONAL DESCRIPTION

OPERATIONAL DESCRIPTION

The iSBX 328 MULTIMODULE board, shown in Figure 1 is designed to plug onto any host iSBC microcomputer that contains an iSBX bus connector. The
board uses an Intel 8041 microcontroller to manage
eight analog output channels that may be user-configured through jumpers to operate in either bipolar
voltage output mode (- 5V to + 5V), unipolar voltage output mode (0 to + 5V), or current loop output
mode (4 to 20 mAl applications. Channels may be
individually wired for simultaneous operation in both
current loop output and voltage output applications.
The outputs feed to a 50-pin edge connector (J1) on
the iSBX 328 MULTIMODULE board.

The host iSBC microcomputer addresses the MULTIMODULE board by executing IN or OUT instructions specifying the iSBX 328 MULTIMODULE as a
port address. The iSBX 328 is initialized to select
whether software or hardware offset is to be used
and how many channels will be active. Then a 2 byte
transfer to each active channel sets the 12 bit output
value, the channel selected and the current or voltage mode.

Commands
OUTput Command-Initialization of UPl/iSBX .328

Interfacing through the
Intel iSBX Bus

All data to be output through the MULTIMODULE
board is transferred from the host microcomputer to
the MULTIMODULE board via the iSBX bus connector. The iSBX 328 board accepts the binary digital
data and generates a 12-bit data word for the Digitalto-Analog Converter (DAC) and a four bit channel
decode/enable for selecting the output channel.
The DAC transforms the data into analog signal outputs for either voltage output mode or current loop
output mode. Offsetting of the DAC voltage in current output mode may be performed by the UPI software offset routine or by the hardware offset adjustments included on the board. The MULTIMODULE
board status is available via the iSBX bus connector,
to determine if the UPI is ready to receive updates to
analog output channels.

0 BII

I
NN: 0,0
0,1
1,0

I N 1 N 1,02 101 1DO 1

=unipolar configuration

software current off.et

= no mixing .
= bipolar configuration

lasl channel
10 be outpul

software current offset

OUTput Command 7

Dala Byles

DAC Dala
DAC channel
10 receive dala
o UPI generales off.el
1 = SBC generale. off••1 1 - - - - - - - - '
In currenl loop mode

280234-3

LOOP

AMP

INTEL'

004,A

DIGITAL·TO
ANALoa
CONVERTER

ANALOG
OUTPUT
MULTi-

12·81T
RESOLUTION

PLEXER

·
•
•

•

}

ANALOO

OUTPUT
8 CHANNEL

up,·

SAMPLE,HOLD
CAPACITOR

MUL TIPLEXEA CONTROL

DEMULTI·
PLEXER

280234-2

Figure 1.ISBC@ 328 Analog Output MULTIMODULETM
16-15

~oard

Block Diagram

intJ

iSBXTM 328 BOARD

INput Command-Status Buffer Read

Compliance
Voltage

280234-4

Interrupts

12V using on-board iSBX
power. If supplied by user, up
to 30 VDC max

Resolution

12 bits bipolar or unipolar

Slew Rate

0.1 V per microsecond mini.
mum

Single Channel
Update Rate

S KHz

Eight Channel
Update Rate

1 KHz

Output Impedance- 0.1 n. Drives capacitive loads
up to O,OS microfarads. (approx. 1000 foot cable)

No interrupts are issued from the iSBX 328 to the
host iSBC microcomputer. Data coordination is handled via iSBC software polls of the status buffer.

Temperature
Coefficient

Outputs·

8 non-isolated channels,
each independently jump- .
ered for voltage output or
current loop output mode.

Voltage Ranges

0 to + SV (unipolar operation)
-Sto +SV (bipolar operation)

Current Loop
Range

4 to 20 rnA (unipolar operation only)

Output Current

- ± S rnA maximum (voltage

-o.OOs%rc

Refresh and Throughput Rates··
Refresh 1 channel (no new data):
80 ,...s
Refresh all 8 channels. (no new data):6S0 ,...s
Update and refresh 1 channel with new
1S0 ,...s
data: firmware program 2
for each additional channel
130,...s
Update and refresh 1 channel with· new
200,...s
data: firmware program 1 or 3
for each additiMal channel
1SS ,...s
Update and refresh all 8 channels
1,OSO ms
(all new data): firmware program 2
per ch.annel of new data
SO,...s.
Update and refresh all 8 channels
(all new data): firmware program 1or 3
1,280 ms
80 ,...s
per channel of new data

SPECIFICATIONS ·

mode-bipolar operation)

Load Resistance -

0 to 2S0n with on-board
iSBX power. 1000n minimum
. with 30 VDC max. external
supply

.. All limes nominal

AccuracyMode
Voltage"Unipolar,
Voltage-Unipolar,
Voltage-Unipolar,
, Voltage-Unipolar,
Voltage-Bipolar,
Voltage-Bipolar,
Voltage-Bipolar,
Voltage-Bipolar,

typical
maximum
typical
maximum

Current Loop, typical
Current Loop, maximum
Current Loop, typical
Current Loop, maximum

Accuracy

Ambient
Temp

± 0.02S% FSR
± 0.03S% FSR
± 0.08% FSR
± 0.19% FSR

@2S·C
@2S·C
@ O· to 60·C
@ O· to 60·C

± 0.02S% FSR
± 0.03S% FSR
± 0.09% FSR

@25·C
@2S·C
@0·t060·C
@ o· to 60·C

± 0.17% FSR

± 0.07% FSR
± 0.08% FSR

± 0.17% FSR
± 0.37% FSR
16-16

@2S·C
@2S·C
@0·t060·C
@0·t060·C

inter

iSBXTM 328 BOARD

Connectors-

Environmental Characteristics

Interface

Pins
(Qty)

P1 iSBX Bus

0.1

0.254

iSBCiSBX
connector

J1 8/16
channels
analog

0.1

0.254

3m 3415-000 or
T1 H312125 or
iCS 910 cable

Centers
in
em

Mating
Connectors

Operating Temperature: O· to 60·C (32· to 140·C)
Relative Humidity:
to 90% (without condensation)

Reference Manuals
142914- iSBX 328 Analog Output MULTI-MODULE
Board Hardware Reference Manual (Order Separately)

Physical Characteristics

230973- Distributed Control Modules Databook

Width: 9.40 cm (3.7 inches)
Length: 6.35 cm (2.5 inches)
Height: 1.4 cm (0.56 inch) MULTlMODULE board
only
2.82 cm (1.13 inches) MULTIMODULE and
iSBC board.
Weight: 85.06 gm (3.0 ounces)

Manuals may be ordered from any Intel sales representative, distributor office or from Intel Literature
Department, 3065 Bowers Avenue, Santa Clara,
California 95051;

Electrical Characteristics.
vcc = ±5V (0.25V),
VDD

ORDERING INFORMATION
Part Number
SBX328

Icc = 140 rnA max

= ±12V(±0.6V), IDD
(voltage mode)

= 45 rnA max
= 200 rnA max

(current loop
mode
Vss

= -12V(±0.6V), Iss = 55 rnA max

16-17

Description
Analog Output MULTIMODULE
Board

intJ

iSBX™ 350
PARALLEL 1/0 MULTIMODULE™ BOARD

•

iSBXTM Bus Compatible 1/0 Expansion

•

24 Programmable 1/0 Lines with
Sockets for Interchangeable Line
Drivers and Terminators

•

Single + 5V Low Power Requirement

•

iSBX Bus On-Board Expansion
Eliminates MULTIBUS® System Bus
Latency and Increases System
Throughput

•

Three Jumper Selectable Interrupt .
Request Sources

Accessed as 1/0 Port Locations

The Intel iSBX 350 Parallel I/O MULTIMODULE Board is a member of Intel's line of iSBX bus compatible
MULTIMODULE products. The iSBX MULTIMODULE board plugs directly into any iSBX bus compatible host
board offering incremental on-board expansion. The iSBX 350 module provides 24 programmable I/O lines
with sockets for interchangeable line drivers and terminators. The iSBX board is closely coupled to the host
board through the iSBX bus, and as such, offers maximum on-board performance and frees MULTIBUS
system traffic for other system resources. In addition, incremental power dissipation is minimal reqLiiring only
1.6 watts (not including optional driver/terminators)..

280235-1

16-18

September 1986
Order Number: 280235-001

intJ

iSBXTM 350 BOARD

are brought to a 50-pin edge connector that mates
with flat, woven, or round cable.

FUNCTIONAL DESCRIPTION
Programmable Interface

Interrupt Request Generation

The iSBX 350 module uses an Intel 8255A-5 Programmable Peripheral Interface (PPI) providing 24
parallel I/O lines. The base-board system software
is used to configure the I/O lines in any combination
of unidirectional input/output and bidirectional ports
indicated in Table 1. Therefore, the I/O interface
may be customized to meet specific peripheral requirements. In order to take full advantage of the
large number of possible I/O configurations, sockets
are provided for interchangeable I/O line drivers and
terminators. Hence, the flexibility of the I/O interface
is further enhanced by the capability of selecting the
appropriate combination of optional line drivers and
terminators to provide the required sink .current, polarity, and driver/termination characteristics for each
application. In addition, inverting bidirectional bus
drivers (8226) are provided on sockets to allow convenient optional replacement to non-inverting drivers (8216). The 24 programmable I/O lines, signal
ground, and + 5 volt power Qumper configurable)

Interrupt requests may originate from three jumper
selectable sources. Two interrupt requests can be
automatically generated by the PPI when a byte of
information is ready to be transferred to the base
board CPU (i.e., input buffer is full) or a byte of information has been transferred to a peripheral device
(i.e., output buffer is empty). A third interrupt source
may originate directly from the user I/O interface (J1
connector).

Installation
The iSBX 350 module plugs directly into the female
iSBX connector on the host board. The module is
then secured at one additional point with nyion hardware to insure the mechanical security of the assembly (~ee Figure 1 and Figure 2).

INTEL ISBXTII 350
MULTI MODULE TIl
BOARD

HOST BOARD

..;> . . _

~
.,:;::; : ;::: . .

iSBX'"
MULTIMODULE
CONNECTOR

.!......

280235-2

Figure 1. Installation of iSBXTM 350 Module on a Host Board

16-19

iSBXTM 350 BOARD

1
O.BO(m...,

'T~

r-_ _....,j......._

......_ _ _. . . ._ _
so_c_K_ET_ _ _ _-,.

ISBX~

c_O_~S_:_E~_.~_O_R

o.SOl(min.,

1.13 (m...,

CONNECTOR
(MALE)

_ _--'...
______
S_OC_K_E_T_ _ _ _...,.
,.
(FEMALE,

280235-3

Figure 2. Mounting Clearances (inches)
Table 1. Input/Output Port Modes of Operation
Mode of Operation

Port

Unidirectional

Lines
(qty)

Input
Unlatched

Output

Bidirectional

Latched &
Strobed

Latched

Latched &
Strobed

Control

X(1)

NOTE:
1. Part of Port C must be used as a control port when either Port A or Port B are used as a latched and strobed input or a
latched and strobed output port or Port A is used as a bidirectional port.

SPECIFICATIONS

1/0 Addressing
8255A-5 Ports

Word Size

PortA
Port B
PortC
Control

Data: 8 Bits

Reserved

ISBX 350 Address
XO orX4
X1orX5
X2orX6
X30rX7
X8 toXF

NOTE:
The first digit of each port 1/0 address is listed as "X"
since it will change dependent on the type of host iSBC
microcomputer used. Refer to the Hardware Reference
Manual for your host iSBC microcomputer to determine the
first digit of the port address.

16·20

inter

iSBXTM 350 BOARD

1/0 Capacity

22011/33011 (ISBC 901 OPTION)
22011

24 programmable lines (see Table 1)

+5V------~~------'
o

.£0

Access Time

1 kll(lSBCg02op,"iciN"--~~~--------------

Read: 250 ns max.
Write: 300 ns max.

+5V

280235-4

NOTE:

Actual transfer speed is dependent upon the cycle
time of the host microcomputer.

Interrupts
Interrupt requests may originate from the programmable peripheral interface (2) or the user specified
1/0 (1).

Physical Characteristics
Width:
Length:
Height':

Weight:

7.24 cm (2.85 in.)
9.40 cm (3.70 in.)
2.04 cm (0.80 in.) iSBX 350 Board
2.86 cm (1.13 in.) iSBX 350 Board
Host Board
51 gm (1.79 oz)

Interfaces

'See Figure 2

iSBXTM Bus-All signals TTL compatible
Parallel I/O-AII signals TTL compatible

Electrical Characteristics

Parallel Interface Connectors

DC Power Requirements

Interface

No. of
Centers Connector
Pairs!
Vendor
(In.) .
Type
Pins

Parallel 1/0
25/50
Connector

0.1

Female

Parallel 1/0
25/50
Connector

0.1

Female
Soldered

Power
Requirements

Vendor
Part No.
3415-0001
with Ears

GTE 6AD01251A1DD
Sylvania

Configuration

+5@320mA

Sockets XU3, XU4, XU5, and XU6 empty (as
shipped).

+5V@ 500 mA

Sockets XU3, XU4, XU5, and XU6 contain
7438 bulters.

+5V@620mA

Sockets XU3, XU4, XU5, and XU6 contain
iSBC 901 termination devices.

NOTE:
Connector compatible with those listed may also be used.

Environmental
Line Drivers and Teminators

Operating Temperature: O·C to

1/0 Drivers-The following line drivers and terminators are all compatible with the 1/0 driver sockets on

the iSBX 350.
Driver
7438
7437
7432
7426
7409
7408
7403
7400

Reference Manual

Characteristic

Sink
Current (rnA)

9803191-01-iSBX 350 Parallel 1/0 MULTIMOD·
ULE Manual (NOT SUPPLIED)

I.OC
I
NI
I.OC
NI.OC
NI
I,OC
I

48
48
16
16
16
16
16
16

Reference Manuals may be ordered from any Intel
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers Ave., Santa
Clara, California 95051.

ORDERING INFORMATION

NOTE:
I = Inverting, NI = Non-Inverting, OC = Open Collector

Port 1 has 25 mA totem pole drivers and 1 ko' terminators.
1/0 Terminators-2200'/3300' divider or 1 ko' pull

up.

+ 55·C

16-21

Part Number Description
SBX 350
Parallel 1/0 MULTIMODULE Board

iSBX™ 488
GPIB MULTIMODULETM BOARD
IEEE 488-1978 Talker/
• Complete
Listener Functions Including:
- Addressing, Handshake Protocol,
Service Request, Serial and Parallel
Polling Schemes
Complete IEEE 488-1978 Controller
• Functions
Including:
- Transfer Control, Service Requests
and Remote Enable

• Simple Read/Write Programming

•
•
•
•

Software Functions Built into VLSI
Hardware for High Performance, Low
Cost and Small Size
Standard iSBX Bus Interface for Easy
Connection to Intel iSBCTM Boards
IEEE 488-1978 Standard Electrical
Interface Transceivers
Five Volt Only Operation

The Intel iSBX 488 GPIB Talker/Listener/Controller MULTIMODULE board provides a standard interface from
any Intel iSBC board equipped with an iSBX connector to over 600 instruments and computer peripherals that
use the IEEE 488-1978 General Purpose Interface Bus. By taking full advantage of Intel's VLSI technology the
single-wide iSBX 488 MULTIMODULE board implements the complete IEEE 488-1978 Standard Digital Interfa,ce for Programmable Instrumentation on a single low cost board. The iSBX 488 MULTIMODULE board
includes the 8291A GPIB Talker/Listener, 8292 GPIB Controller and two 8293 GPIB Transceiver devices. This
board represents a significant step forward in joining microcomputers and instrumentation using industry
standards such as the MULTIBUS® system bus, iSBX bus and IEEE 488-1978. The high performance
iSBX 488 MULTIMODULE board mounts easily on Intel iSBX bus compatible single board computers.
A simple user programming interface for easy reading, writing and monitoring of all GPIB functions is provided.
This intelligent interface minimizes the impact on host processor bandwidth.

143580-1

16-22

October 1986
Order Number: 143580-001

iSBXTM 488 BOARD

FUNCTIONAL DESCRIPTION

GPIB Talker/Listener Capabilities

The iSBX 488 MULTIMODULE board is a singlewide iSBX bus compatible I/O expansion board that
provides a complete implementation of the IEEE
488-1978 Standard Digital Interface for Programmable Instrumentation. The iSBX 488 MUL TIMODULE
board may be configured to be a GPIB controller,
talker, listener or talker/listener. The hardware implementation of the iSBX 488 board takes full advantage of Intel's VLSI capability by using the Intel
8292 GPIB controller, 8291A talker/listener and two
(2) 8293 bus transceivers. All communication between the host iSBC board and the iSBX 488
MULTIMODULE board is executed via the Intel standard iSBX connector. Many of the functions that previously were performed by user software have been
incorporated into VLSI hardware for high performance and simple programming. Both the Intel 8291 A
GPIB Talker/Listener device and the 8292 device
can each communicate independently with the host
processor on the iSBC board depending on configuration. Communication from the host iSBC board to
either device on the iSBX 488 board is flexible and
may be either interrupt or poll driven depending on
user requirements. Data transfers to or from the
GPIB may be executed by the host processor's 110
Read and I/O Write commands or with DMA handshaking techniques for very high speed transfers.

The Intel 8291A device on the iSBX 488
MULTIMODULE board handles all talker/listener
communications between the host iSBC processor
board and the GPIB. Its capabilities include data
transfer, bus handshake protocol, talker/listener addressing procedures, device clearing and triggering,
service requests, and both serial and parallel polling
schemes. In executing most procedures the iSBX
488 board does not interrupt the microprocessor on
the iSBC processor board unless a byte of data is
waiting on input or a byte is sent to an empty output
buffer, thus offloading the host CPU of GPIB overhead chores.

DEVICE
FUNCTION

SIMPLE PROGRAMMING INTERFACE
The GPIB talker/listener functions can be easily programmed using the high level commands made
available by the Intel 8291A on the iSBX 488
MULTIMODULE board. The 8291A device architecture includes eight registers for input and eight registers for output. One each of these read and write
registers is used for direct data transfers. The remaining write registers are used by the programmer
to control the various interface features of the Intel
8291A device. The remaining read registers provide
the user with a monitor of GPIB states, bus conditions and device status.

GPIB INTERFACE
FUNCTIONS

ISBX
CONNE CTOR

1
I
I

l/t l

'v-rYoDRESS,
SELECT,
IORlW

6 MHz
CLOCK

'r;--t

DMA

,..........1

~NTR
BLK
1

8291A
TALKER
LISTENER

I I

-"-

8292
CONTROLLER

,
,

DECODE

DATA

~
/1

L...

GPIB

TRANSCEIVER
" SUPPORT
LOGIC

8282
BUFFER

8293
XCVR

"- I,.....,
v

Ie
'"

TRANSFER

8293
XCVR

MGMT.

-v'"

'"
'-'

SYSTEM
CONTROL

JUMPER
LOGIC

'rALKeRLISTENER
ADDRESS

143580-2

Figure 1. iSBXTM 488 MULTIMODULETM Board Block Diagram

16-23

inter

iSBXTM 488 BOARD

SOFTWARE FUNCTIONS BUILT INTO VLSI
HARDWARE .
Additional features that have migrated from discrete
logic and software- into intel VLSI include programmable data transfer rate and three addressing
modes that allow the iSBX board to be addressed as
either a major or a minor talker/listener with primary
or secondary addressing. The iSBX 488
MULTIMODULE board can be programmatically
configured into almost any bus talker, listener, or
talker/listener configuration. Writing software to
control these and other iSBX 488 board functions is
simply a matter of reading or writing the control registers.
IEEE 488-1978 Functlons(1)
Function

ISBXTM 488
Supported
IEEE Subsets

Source Handshake (SH)
Acceptor Handshake (AH)
Talker(T)
Extended Talker (TE)
Listener(L)
Extended Listener (LE)
Service Request (SR)
Remote Local (RL)
Parallel Poll (PP)
Device Clear (DC)
Device Trigger (DT)
Controller (C)

SHO, SH1
AHO, AH1
TO through T8
TEO through TE8
LO through L4
LEO through LE9
SRO, SR1
RLO, RL1
PPO, PP1, PP2
DCO through DC2
DTO,DT1
CO through C28

simultaneous responses. In applications requIring
multiple bus controllers, several .iSBX 488 boards
may each be configured as a controller and pass the
active control amongst each other. An iSBX 488
board configured for a System Controller has the capability to send Remote Enable (REN) and Interface
Clear (IFC) for initializing the bus to a known state.

GPIB Physical Interface
The iSBX 488 MULTIMODULE board interfaces to
the GPIB using two Intel 8293 bidirectional transceivers. The iSBX 488 board meets or exceeds
all of the . electrical specifications defined in
IEEE 488-1978 including bus termination specifications. In addition, for direct connection to the GPIB,
the iSBC 988 cable, a 26 conductor 0.5 meter GPIB
interface cable is also available from Intel. The cable
is terminated with a 26-pin edge connector at the
iSBX end and a 24-pin GPIB connector at the other.
The cable is also supplied with shield lines for simple
grounding in electrically noisy environments.

Installation
The iSBX 488 MULTIMODULE board plugs directly
onto the female iSBX connector available on many
Intel iSBC boards. The MULTIMODULE board is
then secured at one additional point with nylon hardware (supplied) to insure the mechanical security of
the assembly.

SPECIFICATIONS
NOTE:

1. For detailed information refer to IEEE Standard Digital
Interface for Programmable Instrumentation published by
The Institute of Electrical and Electronics Engineers, Inc.
1978.

iSBXTM Bus-All Signals TTL compatible

Controller Capabilities

26-pin Edge Connector-Electrical levels compatible with IEEE 488-1978.

Interface Information

The GPIB controller functions supplied· by the
iSBX 488 board are provided by the Intel 8292 GPIB
controller device. The 8292 is actually an Intel
8041 A eight bit microcomputer that has been preprogrammed to implement all IEEE 488-1978 controller functions. The internal RAM in the 8041A is
used as a special purpose register bank for the 8292
GPIB Controller. Just as with the 8291A GPIB Talker/Listener device, these registers are used by the
programmer to implement controller monitor, read
and write commands on the GPIB.
When c;:onfigured as a bus controller the i$BX 488
board will respond to Service Requests (SRO) and
will issue Serial Polls. Parallel Polls are also issued
to multiple GPIB instrument devices for receiving

Physical Characteristics
Width: 3.70 in (0.94 cm)
Length: 2.85 in (7.24 cm)
Height: 0.8 in (2.04 cm)
Weight: 3.1 oz (87.8 gm)

GPIB Data Rate*
300K bytes/sec transfer rate with DMA host iSBC
board

16-24

iSBXTM 488 BOARD

50K bytes/s transfer rate using programmed I/O
730 ns Data Accept Time
·Data rates are iSBX board maximum. Data rates
will vary and can be slower depending on host
iSBC board and user software driver.

Environmental Characteristics
Operating Temperature: O· to 60·C (32· to 140·F)
Relative Humidity:
Up to 90% R.H. without
condensation.

Reference Manual

Electrical Characteristics

143154·001- iSBX 48B

GPIB MULTIMODULE
Board Hardware Reference Manual
(not supplied).

DC Power Requirements: Vcc = +5 VDC ±5%
Icc = 600 milliamps maximum

ORDERING INFORMATION

GPIB Electrical and Mechanical
Specifications
Conforms to IEEE 488-1978 standard electrical levels and mechanical connector standard when purchased with the iSBC 988 GPIB cable.

Part Number Description
SBX4BB
GPIB MULTIMODULE
SBC9B8
0.5 meter GPIB cable for iSBX 4BB
MULTIMODULE Board

16-25

inter

iSBC® 556
OPTICALLY ISOLATED 1/0 BOARD

• Up to 48 Digital Optically Isolated
Input/Output Data Lines for
MULTIBUS® Systems

• Provisions for Plug-In, Optically'
Isolated Receivers, Drivers, and
Terminators

• Choice of
- 24 Fixed Input Lines
-16 Fixed Output Lines
- 8 Programmable Lines

• Voltage/Current Levels
-Input up to 48V
-Output up to 30V, 60 rnA
• Common Interrupt for up to 8 Sources

• + 5V Supply Only
The iSBC 556 Optically Isolated liD Board provides 48 digital input/output lines with isolation between
process application or peripheral device and the system CPU board(s). The iSBC 556 contains two 8255A
programmable interface devices, and sockets for user supplied optically isolated drivers, receivers, and input
resistor terminators, together with common interrupt logic and interface circuitry for the system bus. Input
signals .can be single-ended or differential types with user defined input range (resistor terminator and optoisolated receiver selection), allowing flexibility in design of voltage and threshold levels. The output allows user
selection of Opto-Isolated Darlington Pair which can be used as an output driver either as an open collector or
current switch.

280231-1

16-26

November 1986
Order Number: 280231-001

iSBC® 556 BOARD

Table 1. 1/0 Ports Opto-Isolator Receivers, Drivers, and Terminators
Port No.
X =1/0
Base
Address

Type
of

1/0

X+O

Lines
(qty)

Input
Output
Input!
Control
Input
Output
Input! }
Output
Control

X+ 1

X+2
X+4
X+5
X+6
X+7

Resistor
Terminator
Pac-Rp 16-Pin DIP
Bourns 4116R-00
or Equivalent
1

8
8
8

Dual
Opto-Isolator
8-Pin DIP
Monsanto
MCT66
or Equivalent
4

Driver
7438
or
Equivalent

8
8

1 if input

Pull-Up
iSBC® 902

2 if input

SPECIFICATIONS

I/O Addressing .

Number of Lines

Con8255 #2
Con
trol
AlBic
A l B i c trol
I\ddress x+olx+ 11x+2 X+3 x+4Ix+5Ix+6 X+7
Port

24 input lines
16 output lines
8 programmable lines: 4 input -

8255 #1

Where: base address is from OOH to 1FH Uumper
selectable)

4 output

I/O Interface Characteristics

Connectors

Line-to-Line Isolation: 235V DC or peak AC
Input!Output Isolation: 500V DC or peak AC

Mating
Pins Centers
Connectors
qty. in. cm
P1 iSBC bus
Viking
86 0.156
3KH43/9AMK12
3M 3415-000 or
J 1 16 fixed input 50 0.1
TI M312125
& 8 fixed
output lines
3M 3415-000 or
J2 8 fixed input, 50 0.1
TI M312125
8 fixed
output, & 8
programmable input!
output lines
Interface

Terminator PAC
USER·SUPPLIED

DUAL OPTO·ISOLATOR

r - - -

___

-,-+....,...---,

USER-SUPPLIED

- -,

RESISTOR

+-_R_P-+:'_'P_'N_DI-oP

L+-+----+_ _ I

D-*=r---i~*==E=o"-+-I_RP:.1==:
L _____

(+)

iSBC

L_....1

280231-2
Rp determines voltage and current range.

Physical Characteristics
Bus Interface Characteristics
All data address and control commands are iSBC 80
bus compatible.

Width: 12.00 in. (30.48 cm)
Height: 6.75 in. (17.15 cm)
Depth: 0.50 in. (1.27 cm)
Weight: 12 oz. (397.3 gm)

16-27

inter

iSBC® 556 BOARD

Electrical Characteristics

Reference Manual
502170- iSBC 556 Hardware Reference Manual
(Order Separately)

Average DC Current
Vcc = +5V ±5%, 1.0A without user supplied isolated receiver I driver
Icc = 1.6A max with user supplied isolator receiverI
driver

Environmental Characteristics
Temperature: O'C to 55'C
Relative Humidity: 0% to 90%, non-condensing

ORDERING INFORMATION
Part Number Description
SBC 556
Optically Isolated 110 Board

16-28

iSBXTM 351
SERIAL 1/0 MULTIMODULETM BOARD
iSBXTM Bus Compatible I/O Expansion
• Programmable
Synchronous/
• Asynchronous Communications
Channel with RS232C or RS449/422
Interface
Software Programmable Baud Rate
• Generator
Programmable 16-Bit BCD or
• Two
Binary Timer/Event Counters

Jumper Selectable Interrupt
• Four
Request Sources
as I/O Port Locations
• Accessed
Low Power Requirements
• Single + 5V when Configured for
• RS449/422 Interface
Bus On-Board Expansion
• iSBX
Eliminates MULTIBUS® System Bus
Latency and Increases System
Throughput

The Intel iSBX 351 Serial 110 MULTIMODULE board is a member of Intel's new line of iSBX bus compatible
MULTIMODULE products. The iSBX MULTIMODULE board plugs directly into any iSBX bus compatible host
board offering incremental on-board I/O expansion. The iSBX 351 module provides one RS232C or RS449/
422 programmable synchronous/asynchronous communications channel with software selectable baud rates.
Two general purpose programmable 16-bit BCD or binary timers/event counters are available to the host
board to generate accurate time intervals under software control. The iSBX board is closely coupled to the
host board through the iSBX bus, and as such, offers maximum on-board performance and frees MULTIBUS
system traffic for other system resources. In addition, incremental power dissipation is minimal requiring only
3.0 watts (assumes RS232C interface).

280236-1

16-29

September 1986
Order Number: 280236-001

iSBXTM 351

FUNCTIONAL DESCRIPTION

Installation

Communications Interface
The iSBX 351 module uses the Intel 8251A Universal Synchronous/ Asynchronous Receiver/Transmitter (USART) providing one programmable communications channel. The USART can be programmed
by the system software to individually select the desired asynchronous or synchronous serial data
transmission technique (including IBM Bi-Sync). The
mode of operation (i.e., synchronous or asynchronous), data format, control character format, parity,
and baud rate are all under program control. The
8251A provides full duplex, double buffered transmit
and receive capability. Parity, overrun, and framing
error detection are all incorporated in the USART.
The command lines, serial data lines, and signal
ground lines are brought out to a double edge connector configurable for either an RS232C or RS449/
422 interface (see Figure 3). In addition, the iSBX
351 module is jumper configurable for either pointto-point or multidrop network connection.

The iSBX 351 module plugs directly into the female
iSBX connector on the host board. The module is
then secured at one additional point with nylon hardware to insure the mechanical security of the assembly (see Figures 1 and 2).

16·8it Interval Timers
The iSBX 351 module uses an Intel 8253 Programmable Interval Timer (PIT) providing 3 fully programmable and independent BCD and binary 16-bit interval timers. One timer is available to the system designer to generate baud rates for the USART under
software control. Routing for the outputs from the
other two counters is jumper selectable to the host
board. In utilizing the iSBX351 module, the systems
designer simply configures, via software, each timer
independently to meet system requirements. Whenever a given baud rate or time delay is needed, software commands the programmable timers to select
the desired function. The functions of the timers are
shown in Table 1. The contents of each counter may
be read at any time during system operation.

Interrupt Request Lines
Interrupt requests may originate from four sources.
Two interrupt requests can be automatically generated by the USART when a character is ready to be
transferred to the host board (i.e., receive buffer is
full) or a character has been transmitted (i.e., transmit buffer is empty). In addition, two jumper selectable requests can be generated by the programmable timers.

16-30

Table 1. Programmable Timer Functions
Function

Operation

Interrupt on
Terminal Count

When terminal count is
reached, an interrupt request
is generated. This function is
useful for generation of realtime clocks.

Programmable
One-Shot

Output goes low upon receipt
of an external trigger edge
and returns high when
terminal count is reached.
This function is retriggerable.

Rate Generator

Divide by N counter. The
output will go low for one
input clock cycle, and the
period from one low going
pulse to the next is N times
the input clock period.

Square-Wave
Rate Generator

Output will remain high until
one-half the count has been
completed, and go low for the
other half of the count.

Software
Triggered Strobe

Output remains high untii
software loads count (N). N
counts after count is loaded,
output goes low for one input
clock period.

Hardware
Triggered Strobe

Output goes low for one clock
period N counts after rising
edge counter trigger input.
The counter is retriggerable.

Event Counter

On a jumper selectable basis,
the clock input becomes an
input from the external
system. CPU may read the
number of events occurring
after the counting "window"
has been enabled or an
interrupt may be generated
after N events occur in the
system.

inter

iSBXTM 351

U8I!R 110

CONNECTOR _ _......~-?

BOARD

INTEL Isax

..~.",-,;;(."'"

MULTIMODULE
- - CONNECTOR

d'~"
.

280236-2

Figure 1. Installation of ISBC'"' 351 Module on a Host Board

.40

.0
MAX

SOCkET

r----L~~-----L------------~--,
iS8X 351 MUL TIMODULE BOARD

1.13
MAX

IS8X
CONNECTOR
IMALE)

____
r

~ ~ ~
CONNECTOR

___
;s_8_x__
IFEMALE)

____

_______S_0_Ck_E_T______

T
_____ylMIN

280236-3

Figure 2. Mounting Clearances (Inches)

16-31

intJ

iSBXTM 351

RB..232C CABLING

RS449/422 CABLING

CONNECTOR PIN 1

280236-4

Figure 3, Cable Construction and Installation for RS232C and RS449/422 Interface

SPECIFICATIONS

1/0 Addressing
, 1/0 Address for
an a-Bit Host

1/0 Address for
a 16-Blt Host

Chip Select

Function

8251A
USART

Write: Data
Read: Data

MCSOI
Activated (True)

Write: Mode or Command
Read: Status

ZOorZ8

8253 PIT

Write: Counter 0
Load: Count (N)
Read: Counter 0

X90rXD

Z20rZA

MSC11 Activated
(True)

Write: Counter 1
Load: Count N
Read: Counter 1

XAorXE

Z40rZC

Write: Counter 2
Load: Count (N)
Read: Counter 2

XBorXF

Z60rZE

Write: Control
Read: None

XO,X2, X4
orX6

YO, Y4, Y8
orYC

X1,X3,X5
orX7

Y2, Y6, YA
orYE

X80rXC

' '

NOTE:
X = The iSBX base address that activates MCSO & MSC1 for an 8-bit host
Y = The iSBX base address that activates MCSo' for a 16-bit host
Z = The iSBX base address that activates MCS1 for a 16-bit host
The first digit, X, Y or Z, is always a variable, since it will depend on the' type of host microcomputer used, Refer to the
Hardware Reference Manual for your host microcomputer to determine the first digit of the 1/0 base address.
The first digit of each port 1/0 address is. listed as "X" since it will change depending on the type of host iSBC microcomputer used. Refer to the Hardware Reference Manual for your host iSBC microcomputer to determine the first digit of the 1/0
address.

16-32

ISBXTM 351

Word Size

Serial Communications

Oata-8 bits

Synchronous-5-8-bit characters; internal character synchronization; automatic sync insertion; even.
odd or no parity generation/detection.

Access Time

Asynchronous-5-8-bit characters; break character
generation and detection; 1. 1 %. or 2 stop bits; false
start bit detection; even. odd or no parity generation/ detection.

Read-250 ns max
Write-300 ns max
NOTE:
Actual transfer speed is dependent upon the cycle
time of the host microcomputer.

Interval Timer and Baud Rate
Generator
Input Frequency (selectable):
1.23 MHz ±0.1% (0.813 p.s period nominal)
153.6 kHz ± 0.1 % (6.5 p.s period nominal)

Sample Baud Rate
8253 PIT(1)
Frequency (kHZ,
Software Selectable)
307.2
153.6
76.8
38.4
19.2
9.6
4.8
2.4
1.76

8251 USART Baud Rate (Hz)(2)
Synchronous

Asynchronous
+16
19200
9600
4800
2400
1200
600
300
150
110

38400
19200
9600
4800
2400
1760

+64
4800
2400
1200
600
300
150
75

NOTES:
1. Frequency selected by 110 writes of appropriate 16-bit frequency factor to Baud Rate Register.
2. Baud rates shown here are only a sample subset of possible software-programmable rates available. Any frequency from
18.75 Hz to 614.4 kHz may' be generated utilizing on-board crystal oscillator and 16-bit Programmable Interval Timer (used
here as frequency divider).

Output Frequency
Rate Generator
(Frequency)

Single Timer(1)
Single Timer(2)

Real-Time Interrupt
(Interval)

Min

Max

Min

Max

18.75 Hz

614.4 kHz

1.63 !,-S

53.3 ms

2.34 Hz

76.8 kHz

13.0 !'-S

426.7 ms

Dual Timer(3) (Counters 0 and 1 in Series)

0.000286 Hz

307.2 kHz

3.26!,-s

58.25 min

Dual Timer(4) (Counters 0 and 1 in Series)

0.0000358 Hz

38.4 kHz

26.0 !'-S

7.77 hrs

NOTES:
1. Assuming 1.23 MHz clock input.
2. Assuming 153.6 kHz clock input.

3. Assuming Counter 0 has 1.23 MHz clock input.
4. Assuming Counter 0 has 153.6 kHz clock input.

16-33

iSBXTM 351

EIA Standard RS449/422 signals provided and supported.

Interrupts
Interrupt requests may originate from the USART (2)
or the programmable timer (2).

Clear to Send (CS)
Data Mode (OM)
Terminal Ready (TR)
Request to Send (RS)
Receive Timing (RT)
Receive Data (RD)
Terminal Timing (TT)
Send Data (SO)

Interfaces
iSBX Bus-all signals TTTL compatible.
Serial-configurable of EIA Standards RS232C or
RS449/422

Physical Characteristics

EIA Standard RS232C signals provided and supported.
Clear to Send (CTS)
Data Set Ready (DSR)
Data Terminal Ready (DTR)
Request to Send (RTS)
Receive Clock (RXC)
Receive Data (RXD)
Transmit Clock (DTE TXC)
Transmit Data (TXD)

Width:

7.24 cm (2.85 inches)

Length:

9.40 cm (3.70 inches)

Height': 2.04 cm (0.80 inches)
iSBX 351 Board
2.86 cm (1.13 inches)
iSBX 351 Board and Host Board
Weight: 51 grams (1.79 ounces)
"(See Figure 2)

Serial Interface Connectors
Configuration
RS232C
RS232C
RS449
RS449

Mode(2)
DTE
DCE
DTE
DCE

MULTIMODULETM
Edge Connector
26-pin(5),3M-3462-0001
26-pin(5l, 3M-3462-0001
40-pin(6),3M-3464-0001
40-pin(6),3M-3464-0001

Connector(8)

Cable
3M(3)-3349/25
3M(3)-3349 I 25
3M(4)-3349/37
3M(4)-3349/37

25-pin(7),
25:pin(7),
37 -pin(1),
37 -pin(1),

3M-3482-1000
3M-3483-1000
3M-3502-1 000
3M-3503-1000

NOTES:

1. Cable housing 3M-3485-4000 may be used with the connector.
2. DTE-Data Terminal mode (male connector), DCE-Data Set mode (female connector).
3. Cable is tapered at one end to fit the 3M-3462 connector.
4. Cable is tapered to fit 3M-3464 connector.
5. Pin 26 of the edge connector is not connected to the flat cable.
6. Pins 37, 39, and 40 of the edge connector are not connected to the flat cable.
7. May be used with cable housing 3M-3485-1000.
8. Connectors compatible with those listed may also be used.

Electrical Characteristics

Reference Manual
9803190-01- iSBX 351 Serial I/O MULTIMODULE

DC Power Requirements
Mode
RS232C

RS449/422

Manual (NOT SUPPLIED)

Voltage

Amps
(Max)

+5V ±0.25V
+12V ±0.6V
-12V ±0.6V
+5V ±0.25V

460mA
30mA
30mA
530mA

Reference Manuals may be ordered from any Intel
sales representative, distributor office or from Intel
Literature Department, 3065 Bowers. Ave., Santa
Clara, California, 95051.

ORDERING INFORMATION
Part Number Description

Environmental Characteristics
Temperature: 0·C-55·C, free moving air across the
base board and MULTIMODULE
board.

SBX 351

16-34

Serial 1/0 MULTIMODULE Board

iSBXTM 354 DUAL CHANNEL SERIAL 1/0
MULTIMODULETM BOARD
RS232C or RS422A1449
• Two
Programmable Synchronous/
Asynchronous Communications
Channels

•
•

Programmable Baud Rate Generation
for Each Channel
Full Duplex Operation

iSBXTM Bus Compatible I/O Expansion
• Supports
HDLC/SDLC, NRZ, NRZI or
• FM Encoding/Decoding
Three Interrupt Options for Each
• Channel
• Low Power Requirements

The Intel iSBX 354 Serial I/O MULTIMODULE board is a member of Intel's line of iSBX compatible MULTIMODULE products. The iSBX MULTIMODULE board plugs directly into any iSBX bus compatible host board
offering incremental on-board I/O expansion. Utilizing Intel's 82530 Serial Communications Controller component, the iSBX 354 module provides two RS232C or RS422A1449 programmable synchronous/asynchronous
communications channels. The 82530 component provides two independent full duplex serial channels, on
chip crystal oscillator, baud-rate generator and digital phase locked loop capability for each channel. The iSBX
board connects to the host board through the iSBX bus. This offers maximum on-board performance and frees
the MULTIBUS® System bus for use by other system resources.

280045-1

16-35

September 1987
Order Number: 280045-003

intJ

ISBXTM 354 MODULE

FUNCTIONAL DESCRIPTION
Communications Interface
The iSBX 354 module uses the Intel 82530 Serial
Communications Controller (SCC) component providing two independent full duplex serial channels.
The 82530 is a multi-protocol data communications
peripheral designed to interface high speed communications lines using Asynchronous, Byte-Synchronous and Bit-Synchronous protocols to Intel's microprocessor based board and system level products.
The mode of operation (i.e. asynchronous or synchronous), data format, control character format,
and baud-rate generation are all under program control. The 82530 SCC component can generate and
check CRC codes in any Synchronous mode and
can be programmed to check data integrity in various modes. The command lines, serial data lines,
and signal ground lines are brought out to a double
edge connector.

The iSBX 354 module provides a low cost means to
add two serial channels to iSBC® boards with 8 or
16 bit MULTIMODULE interfaces. In the factory default configuration, the iSBX 354 module will support
two RS232C interfaces. With user supplied drivers
and termination resistors, the iSBX 354 module can
be reconfigured to support RS422A1449 communication interfaces with support on Channel A only for
multidrop control from the base board. Both channels can be configured as DTE or DCE with RS232C
interfaces.

Interrupt Request Line
The 82530 SCC component provides one interrupt
to the MINTRO signal of the iSBX interface. There
are six sources of interrupts in the SCC component
(Transmit, Receive and External/Status interrupts in
both channels). Each type of interrupt is enabled under program control with Channel A having higher
priority than Channel B, and with Receive, Transmit

280045-2

Figure 1. Installation of 2 ISBXTM 354 MULTIMODULETM Boards on an ISBC® Board

MULTIMODULE'· BOARD

v."

THREADED NYLON SPACER - - -

280045-3

Figure 2. Mounting Technique
16-36

inter

iSBXTM 354 MODULE

and External/Status interrupts prioritized in that order within each channel.

the iSBX 354 MULTIMODULE board on a Host
Board. Figures 3 and 4 provide cabling diagrams.

Installation

Programming Considerations

The iSBX 354 module plugs directly into the female
iSBX connector on the host board. The module is
then secured at one additional point with nylon hardware to insure the mechanical security of the assembly. Figures'1 and 2 demonstrate the installation of

The Intel 82530 see component contains several
registers that must be programmed to initialize and
control the two channels. Intel's iSBX 354 Module
Hardware Reference Manual (Order # 146531-001 )
describes these registers in detail.

RS232C DB-25 CONNECTORS

PIN 1

40 CONDUCTOR FLAT
RIBBON CABLE

ISBXTII 354 MODULE
COMPONENT SIDE

" ,40 PIN MALE
CONNECTOR

280045-4

Figure 3. RS232C Cable Construction
RS422A/449 DB-37 CONNECTORS
FEMALE

PIN 1
(START AT 5TH
NOTCH FROM END) __ _

'PIN 1
, (START AT 1ST NOTCH FROM END)
(START AT 6TH NOTCH FROM END)
2 CONDUCTORS
15 CONDUCTORS
280045-5

Figure 4. RS422A/449 Cable Construction

16-37

intJ

ISBXTM 354 MODULE

SPECIFICATIONS

Signals Provided

Word Size

RS232CDTE
-Transmit Data
-Receive Data
-Request to Send
-Clear to Send
-Data Set Ready
"Signal Ground
-Carrier Detect
-Transmit Clock (2)
-Receive Clock
-Data Terminal Ready
-Ring Indicator

Data-8 bits

Clock Frequency
4.9152 MHz

Serial Communications
Synchronous-Internal or external character synchronization on one or two synchronous characters
Asynchronous-5-8 bits and 1, 1Yz or 2 stop bits
per character; programmable clpck factor; break detection and generation; parity, overrun, and framing
error detection
Sample Baud Rate:
Synchronous X1 Clock
Baud Rate

82530 Count Value
(Decimal)

64000
48000
19200
9600
4800
2400
1800
1200
300

36
49
126
254
510
1022
1363
2046
8190

RS422A/449
-Send Data
-Receive Timing
-Receive Data
-Terminal Timing
-Receive Common
I/O Port Addresses
Port Address
8·Blt

82530 Count Value
(Decimal)

19200
9600
4800
2400
1800
1200
300
110

6
14
30
62
83
126
510
1394

Function

16·Blt
XO

Read Status Channel B
Write Command Channel B

Read Data Channel B
Write Data Channel B

Read Status Channel A
Write Command Channel A

Read Data Channel A
Write Data Channel A
Read Disable RS422A/449 Buffer
Write Enable RS422A1449 Buffer

Asynchronous X16 Clock
Baud Rate

RS232CDCE
-Transmit Data
-Receive Data
-Clear to Send
-Data Set Ready
-Signal Ground
-Carrier Detect
-Transmit Clock (2)
-Receive Clock
-Ring Indicator

NOTES:
1. The "X" and "Y" values depend on the address of the
ISBX Interface as ,viewed by the base board.
2. "X" corresponds with Activation of the MCSO/interface
signal; "Y" corresponds with Activation of the MCS1/interface signal.

Power Requirements
INTERFACES
ISBXTM Bus: Meets the iSBX Specification, Compliance Level: 08 F
.
.

+5V at 0.5A
+12V at 50 mA
-12V at 50 mA

Physical Characteristics
Serial: Meets the EIA RS232C standard on Channels A and B. Meets the EIA RS422A1449 standard
on Channels A and B, Multi-drop capability on Channel A only.

Width: 2.85 inches
Length: 3.70 inches
, Height: 0.8 inches
Weight: 85 grams

16-38

inter

iSBXTM 354 MODULE

ENVIRONMENTAL
CHARACTERISTICS

REFERENCE MANUAL

Temperature: O°C to 55°C operating at 200 linear
feet per minute across baseboard and
MULTIMODULE board
Humidity: To 90%, without condensation

146531-001-iSBX 354 Channel Serial liD Board
Hardware Reference Manual
Reference manuals may be ordered from any Intel
sales representative, distributor office, or from Intel
Literature Department, 3065 Bowers Avenue, Santa
Clara, CA 95051.

ORDERING INFORMATION
Part Number Description
iSBX 354

Dual Channel I/O MULTIMODULE

16-39

iSBXTM 1/0 EXPANSION BUS

•
•
•
•
•

IEEE 959·88 Industry Standard I/O
Expansion Bus
Provides On·Board Expansion of
System Resources
Small iSBXTM MULTIMODULETM Boards
Plug Directly hito ISBC® Boards
Supports Compatible 8· and 16·Bit Data
Transfer Operations

•
•
•

Part of Intel's Total System
Architecture: MULTIBUS®, iLBXTM and
iSBXTM

Low·Cost "Vehicle"to Incorporate the
Latest VLSI Technology into iSBC®·
Based Systems
Provides Increased Functional
Capability and High Performance
Supported by a Complete Line of
iSBC® Base Boards and iSBXTM
MULTIMODULETM Boards, Providing
Analog and Digital I/O, High·Speed
Math, Serial and Parallel I/O, Video
Graphics, and Peripheral Controllers

The iSBXTM 1/0 Expansion Bus is one of a family of standard bus structures resident within Intel's total system
architecture. The iSBX bus is a modular, 1/0 expansion bus capable of increasing a single board computer's
functional capability and overall performance by providing a structure to attach small iSBX MULTIMODULETM
boards to iSBC® base boards. It provides for rapid incorporation of new VLSI into iSBC MULTIBUS® systems,
reducing the threat of system obsolescence. The iSBX bus offers users new economics in design by allowing
both system size"and system cost to be kept at minimum. As a result, the system design achieves maximum
on-board performance while allowing the MULTIBUS interface to be used for other system activities. The iSBX
bus enables users to add-on capability to a system as the application demands it by providing off-the-shelf
standard MULTIMODULE boards in the areas of graphics controllers, advanced mathematics functions, parallel and serial 1/0, disk and tape peripheral controllers, and magnetic bubble memory. A full line of MULTIBUS
boards and iSBX MULTIMODULE boards are available from Intel and other third party sources in the industry.
Its success as an industry standard has been reinforced by adoption of the SBX specification by the Institute of
Electrical & Electronic Engineers - IEEE 959-88.

280255-1

16-40

September 1988
Order Number: 280255-001

inter

ISBXTM I/O EXPANSION BUS

FUNCTIONAL DESCRIPTION
Bus Elements
The iSBXTM MULTIMODULETM system is made up
of two basic elements: base boards and iSBX MULTIMODULE boards. In an iSBX system, the role of
the base board is simple. It decodes I/O addresses
and generates the chip selects for the iSBX MULTIMODULE boards.
The iSBX bus supports two classes of base boards,
those with direct memory access (DMA) support and
those without. Base boards with DMA support have
DMA controllers that work in conjunction with an
iSBX MULTIMODULE board (with DMA capability) to
perform direct I/O to memory or memory to I/O operations. Base boards without DMA support use a
subset of the iSBX bus and simply do not use the
DMA feature of the iSBX MULTIMODULE board.

power lines. The iSBX bus provides nine control
lines that define the communications protocol between base board and iSBX MULTIMODULE
boards. These control lines are used to manage the
general operation of the bus by specifying the type
of transfer, the coordination of the transfer, and the
overall state of the transfer between devices. The
five address and chip select signal lines are used in
conjunction with the command lines to establish the
I/O port address being accessed, effectively selecting the proper iSBX MULTIMODULE. The data lines
on the iSBX bus can number 8 or 16, and are used
to transmit or receive information to or from the iSBX
MULTIMODULE ports. Two interrupt lines are provided to make interrupt requests possible from the
iSBX board to the base board. Two option lines are
reserved on the bus for unique user requirements,
while several power lines provide + 5 and ± 12 volts
to the iSBX boards.

Bus Pin Assignments
The iSBX MULTIMODULE boards are small, specialized, I/O mapped boards which plug into base
boards. The iSBX boards connect to the iSBX bus
connector and convert iSBX bus signals to a defined
I/O interface.

Bus Interface/Signal Line Descriptions
The iSBX bus interface can be grouped into six functional classes: control lines, address and chip select
lines, data lines, interrupt lines, option lines, and

The iSBX bus uses widely available, reliable connectors that are available in 18/36 pin for 8-bit devices
and 22/44 pin for 16-bit devices. The male iSBX
connector is attached to the iSBX MULTIMODULE
board and the female iSBX connector is attached to
the base board. Figure 2 shows the dimensions and
pin numbering of the 18/36 pin iSBX connector,
while Figure 3 does the same for the 22/44 pin iSBX
connector. A unique scheme allows the 16-bit female connector to support 8 or 16-bit male MULTIMODULE boards. Table 1 lists the signal/pin assignments for the bus.

REMOTE CONTROL MODULES

280255-2

Figure 1. MULTIBUS@ System Architecture
16-41

inter

iSBXTM 1/0 EXPANSION BUS

Mnemonic

Table 1 iSBXTM Signal/Pin Assignments
Pin(1)
Mnemonic
Description

M08

MOATABit8

MDA

MDATABitA

MDB

MDATA Bit F

MDC

MDATABitC

MDD

MDATABitD
MDATA BitF

Pin(1)

M09

Description

MDATA Bit 9

MDE

MDATA Bit E

MDF

GND

Signal Gnd

+5V

MDO

MOATABitO

MDRQT

M DMA Request

MD1

MDATA Bit 1

MDACKI

M DMA Acknowledge

MD2

MDATA Bit2

OPTO

Option 0

MD3

MDATA Bit3

OPT 1

Option 1

MD4

MDATA Bit4

TDMA

Terminate DMA

MD5

MDATA Bit5

MD6

MDATA Bit6

MCSOI

M Chip Select 0

MD7

MDATA Bit 7

MCS/1

M Chip Select 1

GND

Signal Gnd

+5V

10RDI

I/O Read Cmd

MWAITI

MWait

10WRTI

1/0 Write Cmd

MINTRO

M Interrupt 0

MAO

M Address 0

MINTR1

MA1

M Address 1

MA2

M Address 2

MPSTI

iSBX Multimodule
Board Present

Reserved

M Interrupt 1
Reserved

RESET

Reset

MCLK

M Clock

GNO

Signal G'nd

+5V

+12V

12V

NOTES:
1. Pins 37-44 are used only on 8/16-bit systems,
2. All undefined pins are reserved for future use.

Bus Operation Protocol
COMMAND OPERATION

The iSBX bus supports two types of transfer operations between iSBX elements: I/O Read and 1/0
Write. An iSBX board can respond to these 1/0
transfers using either full speed mode or extended
mode.
For a full speed 1/0 Read (Figure 4) the base board
generates a valid 1/0 address and a valid chip select
for the iSBX MULTIMODULE board. After setup, the
base board activates the 1/0 Read line causing the
iSBX board to generate valid data from the addressed 1/0 port. The base board then reads the
data and removes the read command, address, and

chip select. The full speed 1/0 Write (Figure 5) operation is similar to the 1/0 Read except that the base
board generates valid data on the lines and keeps
the write command line active for the specified hold
time.
The extended Read operation (Figure 6) is used by
iSBX MULTIMODULE boards that aren't configured
to meet full speed specifications. It's operation is
similar to full speed mode, but must use a wait signal
to ensure proper data transfer. The base board begins the operation by generating a valid 1/0 addres~
and chip select. After setup, the base board actIvates the Read line causing the iSBX board to generate a Wait signal. This causes the CPU on the
base board to go intoa wait state. When the iSBX
board has placed valid Read data on the data lines,
the MULTIMODULE board will remove the Wait signal and release the base board CPU to read the data

16-42

intJ

iSBXTM 1/0 EXPANSION BUS

and deactivate the command, address, and chip select. The extended Write operation (Figure 7) is similar to the extended Read except that the Wait signal
is generated after the base board places valid Write
data on the data lines. The iSBX board removes the
Wait signal when the write pulse width requirements
are satisfied, and the base board can then remove
the write command after the hold time is met.

DMA OPERATION
An iSBX MULTIMODULE system can support DMA
when the base board has a DMA controller and the
iSBX MULTIMODULE board can support DMA
mode. Burst mode DMA is fully supported, but for
clarity and simplicity, only a single DMA transfer for
an 8-bit base board is discussed.
A DMA cycle (Figure 8) is initiated by the iSBX board
when it activates the DMA request line going to the
DMA controller on the base board. When the DMA
controller gains control of the base board bus, it acknowledges back to the iSBX board and activates
an 1/0 or Memory Read. The DMA controller then
activates an I/O or Memory Write respectively. The
iSBX board removes the DMA request during the
cycle to allow completion of the DMA cycle. Once
the write operation is complete, the DMA controller
is free to deactivate the write and read command
lines after a data hold time.

INTERRUPT OPERATION

the base board. The CPU processes the interrupt
and executes the interrupt service routine. The interrupt service routine signals the iSBX MULTIMODULE board to remove the interrupt, and then returns
control to the main line program when the service
routine is completed.
'Please refer to the Intel iSBX Bus Specification for
more detailed information on its operation and implementation.

SPECIFICATIONS

Word Size
Data: 8, 16-bit

Power Supply Specifications
Table 3

Minimum
(volts)

Nominal
(volts)

Maximum
(volts)

Maximum
(current)'

+4.75

+5.0

+5.25

3.0A

+ 11.4

+12

+12,6

1.0A

-12

-11.4

-12.6

GND

1.0A
3.0A

NOTE:

The iSBX MULTIMODULE board on the iSBX bus
can support interrupt operations over its interrupt
lines. The iSBX board initiates an interrupt by activating one of its two interrupt lines which connect to

'Per iSBX MULTIMODULE board mounted on base board.

Port ASSignments
Table 2. iSBXTM MULTIMODULETM Base Board Port Assignments
16-Bit Base
ISBXTM Connector
Chip
8-Bit Base
Board Address
Select
Board Address
Number
(8-bit mode)
iSBX1
MCSOI
FO-F7
OAD-OAF
MCS11
FB-FF
OBO-OBF

16-Bit Base
Board Address
(16-bit mode)
OAO,2.4,6,B,
A,C,E
OA 1,3,5,7,9,
B,D,F

iSBX2.

MCSOI
MCS11

CO-C7
CB-CF

080-0BF
090-09F

080,2.4,6,8
A,C,E
OBi ,3,5,7,9,
B,D,F

iSBX3

MCSOI
MCS11

BO-B7
BB-BF

060-06F
060-06F

060,2,4,6,B
A,C,E
061,3,5,7,9,
B,D,F

16-43

inter

ISBXTM 1/0 EXPANSION BUS

DC Specifications
Table 4. ISBXTM MULTIMODULETM Board I/O DC Specifications
Output 1
Bus Signal
Name

Type 2
Drive

IOLMax
-Min (mA)

@Volts
(VOL Max)

IOHMax
-Min (/LA)

@Volts
(VOH Min)

Co (Min)
(pf)

MDO-MDF

TAl

1.6

0.5

-200

2.4

130

MINTAO-1

TTL

2.0

0.5

-100

2.4

MDAQT

TTL

1.6

0.5

-50

2.4

MWAITI

TTL

1.6

0.5

-50

2.4

0.5

-50

2.4

OPT1-2

TTL

1.6

MPSTI

TTL

Note 3

Input 1
Bus Signal
Name

Type 2
Receiver

IlL Max
(mA)

@VINMAX
(volts)
TestCond.

IIHMax
(/LA)

@VINMAX
(volts)
TestCond.

CIMax
(pf)

MDO-MDF

TAl

-0.5

0.4

2.4

MAO-MA2

TTL

-0.5

0.4

2.4

MCSO/-MCS11

TTL

-4.0

0.4

100

2.4

MAESET

TTL

-2.1

0.4

100

2.4

MDACKI

TTL

-1.0

0.4

100

2.4

IOADI
IOWATI

TTL

-1.0

0.4

100

2.4

MCLK

TTL

-2.0

0.4

100

2.4

OPT1-0PT2

TTL

-2.0

0.4

100

2.4

NOTES:
1. Per iSBX MULTIMODULE I/O board.
2. TTL = standard totem pole output. TRI = Three-state.
3. iSBX MULTIMODULE board must connect this signal to ground.

16-44

All Inputs: Max VIL = O.BV
Min VIH = 2.0V

rl
~

o
U;

..... B

.La •a

iFi
c

!':I

....
C»

....
Co)

SECTION A-A

cD
J,..
01

'"CI

'1·

enm

-iI:

oo
:::J
:::J
CD

III--

.• ->i.

1OO REF

.045

LI~ H
'j "j (--o-D

" "

.,,->1II~.I--____

- I ytOO6I .035

:"""'8

::::

><
i!

125 - .015
. 36 Pt

.
are in inches and unless otherwise speclTed
All dimenSIons
I tolerances are'.

.....- § -

" __

.xxp

•.

o
m
><
~
zen

'I'l-j==rT
f!l
.a
.m

D-D
D-D

1-·

enm

1~
~

I:'

£ ,
SECTION B-B

iJ- ~ t:I

2.025

dtkrmR~111· r· ~''''~

><-I

l
VIEW A-A

).t!_. . . .
[]lcl

en
OJ

---,---,
"--l
...5

~
.....

a;
.l:.

<»

""'U
s-

:::::

SECTION C-C

en
III

,. -l

)(

1-.027 •

pt.

."Ol

,:,}Ii#~
~_~
Ie n
11

:s
:s
CD

211

....

L{= :

o...

~JI
.1135 REF

•

-0 0

0 0
0 0

D-& 8 O--;rO

2.555

ill

SECTION B-8

All dimensions are in inches and unless otherwise specified tolerances are:

.xxp01, .xxxpoos.

!AI ·7
-I

oz
OJ

c:
en

ISBXTM I/O EXPANSION BUS

Bus Timing Diagrams
SOURCE

SIGNAL

BASE BD

MACl-MA2

BASE BD

MCSI

~
\

BASE BD

ISax BD

VALID ADDRESS

IORDI

?
(

\((

MDCl-MD1

X VALID DATA )
280255-5

Figure 4. ISBXTM MULTIMODULETM Read, Full Speed

SOURCE

SIGNAL

BASE BD

MACl-MA2

BASE BD

MCSI

BASE BD

IOWRTI

BASE BD

MDO·MDF

VALID ADDRESS

VALID DATA

280255-6

Figure 5. ISBXTM MULTIMODULETM Board Write, Full Speed

SOURCE

SIGNAL

BASE BD

MAO·MA2 .J\_ _ _ _ _ _ _ _-1'7____v.:.,.A..:L..:ID_A_D_D_R_ES_S_ _ _ _ _ _ _ _ _ _ _ _-::;;;-A_ _

BASE BD

MCSI

lsax

MWAITI

BASE BD

IORDI

ISBX BD

MDCl-MDF _ _ _ _ _ _ _ _

-2~(==================:Jy(~====~V~A~L~ID~D~A~T~A======:J
280255-7

Figure 6. iSBXTM MULTIMODULETM Board Extended Read

16·47

inter

ISBXTM I/O EXPANSION BUS

SOURCE

SIGNAL

BASE BD

MAO-MA2

BASE BD

MCSI

VALID ADDRESS

(

(/"r-

\
iSBX BD

MWAITI

BASE BD

IOWATI

BASE BD

MDO-MDF

"7\

~~~

VALID DATA

280255-8

Figure 7. iSBC® MULTIMODULETM Board Extended Write
SOURCE

SIGNAL

ISax BD

MDRQT

BASE BD

MDACKI

BASE BD

IORDI

BASE BD

MEM WRITEI

,S8X BD

MDO·MDF

- - - - I f t----~-

-----11 f - - - - - - - - - - - ' M

ISBX VALID READ DATA

280255-9

Figure 8. iSBXTM MULTIMODULETM Board DMA Cycle
(iSBXTM MULTIMODULETM to BaseBoard Memory)

16-48

intJ

iSBXTM 1/0 EXPANSION BUS

Board Outlines
All dimensions are in inches and unless otherwise specified tolerances
are:
.xxp.OI, .xxxp005.
•06 R
4 PLACES

2.050

REF

.156 OIA.
1 PLACE

PIN I
LOCATION

280255-10

COMPONENT SIDE

Figure 9. iSBXTM Board Outline

All dimensions are in inches and unless otherwise
are:
,"p.OI, .xxxp005.

spec~ied

tolerances

.2011+---.~7'50-'-------------.j·1
I
5.100
.'
2.20_:
..
3.800
·1

IF
IL

-$-

.1580IA. /

l:300
REF

3 PLACES

PIN I
LOCATION

280255-11

COMPONENT SIDE

Figure 10. Double Wide iSBXTM Board Outline

Environmental Characteristics

Reference Manuals

Operating Temperature: O·C to 55·C

210883-002-MULTIBUS Architecture Reference
Book

Humidity: 90% maximum relative; non-condensing

16-49

Local Area Network
Boards and Software

fPl~~11JU¥il~li':!l~[glV

OpenNETTM LOCAL AREA NETWORK FAMILY

PCLlNK2

VMSNET

OpenNEr": THE COMPLETE OPEN NETWOR" SOUITION
The OpcnNF:T f~mjJy provides the m:M witll com ple\(' ()/X'II ,\('/III)/'1: ,,"111111111" Ii II' S
• Transport and Distrihutl~1 Naml' S~rver Software with
Programmatic :\('('t'ss
• iR~!X SvstelTl 120 (AT·bus), 32() (MlII.TIHlIS I) and 520
(~llILTII3L'S II) Connections
• Remot~ Boot for Diskless SySIA'ms

The iRMX o~el'ating SYSll'lII provides a I'irh Sft. of human
intt'rlacl' commands and system ralls for accessing local
files. With the add ilion of iRMX· "~:'I: these commands and
system ralls are transparently l'xtended to remote acl'ess as
well. Transparency means that applications using the iRMX
Human Intt'rfacl' commands or BIOS system mils elo not.
Ill't'd to know Whether the filcs they access reside locally or
on some remote system,

rietl\orkrd iR~IX systems serve In a wide range of rt~11·timt'
application areas including data acquisition, factory
automation, financial workstations. military. medical
Instrumentation. simulation and (l('()Cl'SS control.

17-3

[pl ~~IlJ~ ~ IN] ~USJ't7

IRltIX@-NET OpenNETTM NETWORKING SOFTWARE

iRMX'"
MULTIBUS'" I
SYSTEM 320

IRMX'" AT·BUS
SYSTEM 120

AT-BUS

MULTIBUS'" I

MULTIBUS@ II

COMPLETE OpeaNErM SOLfJTlON FOR
REAL-TIME St'STEMS

TRANSPARENT NETWOR" FILE
ACCESS

Real·Time mmpUler systt'ms require a real·Umt' operating
syslt'm. '1'11(' iKMX operating systl'm from Intel is tlw world's
most popular operating system for real·time systl'ms.

iRMX·N~:'I' impll'ments the NF·\ protocol to pro,ide
transparent file access cupahilitil's UIlHJIlg iR~lX. DOS. vAX!
VMS. UNIX. XENIX and iNDX systems on the OpenNI<.:T
network. Remote files al'P m'l't'ssed us if lhe, resided on the
local iRMX system. iRMX·Nr;T can hl' configured as a
network fill' consumer. \'ill' server. or hoth. depending on the
application's requirements.

Many rt'ai-time applications requirt' network communication.
Intel's iR~IX·NET ReleL9,l~I!Jffi.ffi~INl,%IXlV

INTEL SYSTEM" OpenNETTM NETWORKING SOFTWARE
COMPLE'I'E OpeIlNEr" SOUJ'l'ION FOR
IlNIX SI'S'I'EM I'
S\·OjX'n\ET connects Intel SYSTEM V/386 sysl,t>m~ with all
the Open\fo:T nodes. SY.(JpenNET is available for MlIl:rlBliS
I and \IL'LTIBL'S II. The product includes a complrte
solution: communications board. Mail. VT. print spooling.
namrseflrr interface library (NS!). and network
management.
S\·Open\ET allows application interfacing through the lINIX

'I'll library. Applications may also access SV'()llt'nN~;T via
the higher·lrvel NSI library. SV·Oprn:'configured with iNA 960 to run on Intel's ISBC·5~4 If:r:f:
802.4 Token Bus MAP hoard to provide a seven lavrr
solution. The preconfigured MAP21SXM software proiluct is
supplied withiRMX device drivers. user Intcrface utilitirs.
and the conlormance tested MAPNET software.

Thr MAPNf:T products provide session services. directory
st'rvlc('s. network managrment. FlAM. and CASE as
spt'cifi('d in tht' .~f'\P2.1 spt'~ification.
lising tht' servin's of \lAPr\ET. users can initiate
communications with otht'r us~rs on a MAP network, access
information rt'garding rt'sourc~s available on the network.
transft'r fib ~rro~s thl' nt'tllurk. and address others by
logiral nnmt'~ ratht'r than numbered addresses.
Tht' ~11mllfarturing ~Il'ssaging Sprcification (RS·511 or M\tS)
for M:\PNJo:T on iRMX·SO is also available from independent
~oftwart' v('f1dors.

PRODIJC'I' CODES
ItIAPNET21

Configul'able ISO/OSI Layers 5
through 7 of thr Mt\P2. I
Preconfigured ISOIOSI Laycrs 3·
through 7 of the MAP2. I

ItIAP21 SUIRO

CONFIGIJRABI..E IfIAPNE'I'21
The configurable MAPNET21 implement:; layers ~ thl'Ough 7
of the ~fAP2.1 specification. MAPNET21 is designed to
interface with iM 960 and the iSBC·554 to provide a
complete seven layrr configurable MAP solution for OEMs.

,I
/

I/
I

,
I

...Z

Directory
S.rviee.

V
FlAM
Consumer

Session

Transport

Network

...:Iiw

IJ-.f

Presentation

w
:Ii
w

!&z

FTAM

s....,

1'1

MAPHET2.1

1
MAPa.1SXII

Data Link
Physical

17-9

,2
j2
,1,)

[pl1Rl1E!L~ffi\!1J~!NI~!Rl'¥'

11\IA 960 OIJenl\lET™ l\IETWORIUl\IG sorTWARE
I'IJUI' (;OltlrUAN'I' ISOIOSI
'I'RANSroR'I' AND NE'I'tJ'OIlM
i\:\ 960 Is a rumplete ~etl\nrkand Transport (lSO/O..SI
Layers 3 anel -t) software system plus a cnmpr(')wnsivt' Sl't
of nctl\urk management functions. Data Link (OSI Layer 2)
drilt'rs for II~:~:E 1102.3 Ethernet and II!;EI'; 1102.4 'Men Bus
(\I:\P). and system enl'lronment fraturrs.

I'aXIBU AND HIGH£I'
(;ONI'16IJRABU
i\-\ 9tlO is a mature. nexlble. and ready-to-uS(' software
building block f(l,rO~;M SlIlllllil'rs of nelllllrkl' (lg~:~: H02.3)
cnmpatihlt' nrtwnrking capability jill' all
\ll'l :rmlIS~1I syst<'l11s
•

\ll'LTlBlIS~1I iPSR (Parallel SyslI'm Bus)
interlacl' wil.h lull ~kssag(' Passing
rapability

• i 341 MliLTIM(]DlIL~:~ fnr
a l1la~imum of 5121\ bytt':l of EPROM
.
• Provides one RS232C sl'rial port fnl'
dt'tlUg and II'sting

USl'

ill

• ('rnlluet Code: pSBC186530

peRilS OpeaNETTM NETWORKING ""RDW"RE

PC £INM.fl NETWORM. INTERFACE ADtlPTER (PC UNM.fl NIA}
CPU .........................................80186 (8 MHz)
LAN Communications Controller ........................82586
Ethernet Interface ..........15-pin connector, 82501 serial interface
DRAM 256 KB (dual-port), 0 wait·state memory access by the CPU
EPROM ......... : ....................................16 KB
Size .................................... .4.15 in H x 13.3 in W
Power Requirements + 5V ..............................2.0 A
+12V .............................0.5 A

• Intelligent high perfnrmance hardwal'l' with
on·board micropl'llcrssOl: 16K byt<'s
EPROM and 256K bytes RAM.
• Full slot PC AT. PC XT (nr compatihle
computer system) bnard
• 80186 microprocessor, 82586 LAri
coprocessor, 8 MHz zero-wait-stall'
memory access.

• RA\1 shal'l~t hy tht' I'C hllst anc! I'C l.ink2 hoard ria an 81\ memory
winduK
.
• .Iumlwr sl'!l~·tiun fill' ~:th('I'nl't
•

~:rrl~'ti\l' sl'lf diagnosti('s.

• I'I'IKlu('t COlll': sI'CI.I\f,;2NI:\

17-12

01' ((':~:I':

B02.:l.

r -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~~~~U[R;1J~lNJfo\lPl)f

OpeaNET™ NETWORKING ACCESSORIES

ISBX'" 5B6 DATA LlNIt. ENGINE MIlLl'IItlODIlLE@ BOARD
LAN Coprocessor ......................... , , .. 82586 (8 MHz)
RAM (Bytes) ..
. ...... , ..... , .. _... 16K (dual· port)
Software Support
. , ..... , ........... _... ,.iNA 960/961
Power Requirements + 5V
... 2.0 A
+12V....
. .................1.0 A

• PrOlides all IE;E;F: 802.3lEthernet
compatible connectioll lor 8086 and
8018ti·based host boards 01'('1' a Hi·hit
iSBX'" interlace

•

COlllp:ilihh' Ililll i\ \ !lIio/!}(iIIS() Hon Transport and ISO 8~73
N!'Illorl. SOnll:ll,(,

•

I'rolill,'s all 11·:1':1·: Bm.:llo 11':1·:1,: H01.·j ~ouler capahilitl \11ll'n uSt'd
willi IIII' iSIU;v ~:,I 11':1,:1,: Hm.1 1..\\ ('outrolll'r
'

•

I'rodlll'i Cod,': sSI;.VIBIl

Single-wide iSS"" MlII.TIMODl'I.W·

IDCM 911-1 INTELLlNIeM FtiN-OIlT IJNIT
Size.... . . .... ... . ... . . . . . .
. .. 14 in. Wx 7.8 in. H x 5.5 in. D
Power Requirements ........... .100/120/220/240 VAC, 47-64 Hz

•

Connects up 10 nine Ethernet colllpatihlt'
Ilorkstations wi tho III tile III'Cd IiiI'
transcei\'ers or coaXial callie

•

Cascadahll' 10 SIIPIII'I t 17-HI IIOllslilllOIiS

•

I'rod 1If'I Codl': pIlC\I! I1II

• Connl't'ls directly to the I·:therrwt coa~iul
ruble through a stanilaf'(t transct'iwl' cahlt'

ETHERNET/IEEE B02.3 THIN-WIR': TRtlNSCI:nll:R
... 2.8 in. x 3.6 in. x 3.8 in.
.... 375mA

Size
Power Requirements + 12V
(from transceiver cable)

• DiN'ast Illctalc8se lor protection. reduced
E\11. ami elficient heat dis:;ipatiou
•

1.011 inrusll current at power-up. allto
shutdown when lOW-input \oltage occurs.
and surge protection

•

IEf:f: R02.3-mmpliant. Ethernet V1.0/\,2.0

•

TllI'I'!' I.f:ll~ IIllll1ltlll' I'"llt'l' SI:lIu,;. pill'k"l I'lIl1i,;illl1s al1d signal qllalit~

•

~I'lIltl\ahlt' Il\C t~PI'I':rhlt'I kit l'onWining BITBl'S mwlog iIIHI digilal
hoards. tailored application software. and all the accessories (~.g .. powl'r tiuppl~ ami rahll'~)
required to set up a simple hut functional BITBliS network. A first-time lISl'r can construct aIlITBl!S
network and execute sample application programs within two hours of opl'ning thl' ho.\. lit' can then
incorporate this ha~ir net\\ork into his own distributed contl'ol application.

FEATIJRES:
• Self-contained BlTBI'S kit requiring only an
1fl\1 PC or compmihle host.
• BITRL"S analog and digital hoards, plus PC
Gate\\a\ In the RITRL'S network.
• Sample' application software with hUilt-in
installation. configuration. and diagnostic
softllare.
FlITFlL'S experienrr nrcpssal').

• '0

infe1'-----------lilt. 11~'IIM'I,lh ..1l .1~~uril'·S Ill' !!·~I~l!IslllllIl\ tur ItH' IN' "I 'III~ 1'11'('11111,1 u(l,,'!" 111,111 ,',r"Ulln ,'rnll'MIII'd III ,III IlIld pl,"lil' t \It I,lh"1 "rlilit 1'.l1c'nl hI', II",', ,III'
d Inli" n~III' Iii n'flloIUII~1 tH'r,'1I1 snl~'rSl~h':- I'WI l"u'l~ 11I11111:-hl~1 Sl~' Ilu';1111 ,II"; Ul1l1Wl't' I~" I!~'S 11~11Il ll~d ,11111 IS ~ul'W"1 1., IlloIll/.!" II 1111'1.11 !ltllIll'

!Ill ph,

FI'I"11,11 I, 1'lHII

18-1

SPECIFICATIONS
"EIiL-TlME IN'I'ERfJtlNNEfJ'I' FOIl
DIS'I'RIBlJ'I'ED CflN'I'1lfI£

BIlI"'I'·IN INSTII"LATION AND
DIAGNOSTIC StlF'I'WARE

The Intel BITBL'S network prol'ides the optimal solution for
building real-time distributed cuntrol systems. Thl' AITRl.'S
serial bus architecturl' ol('rcomes many of t he limitations
inherent in traditional industrial connertion methods to givt'
you increased performanre. reliability. and flexibility and
IUller implf'mentation costs.

Application software included with the BITBLIS Startet' Kit
provides network setup information. as well as
comprehensive error-chc'Cking software to verify that the
network is configured correctly. If there is an error. the
software direds you to the pl'Oblem and suggests a
correction. Oncr the network is working properly. the
sol'tware steps you through optional configurations. frolll a
host-based centralized control system to a node-based
distributed control srhe.me. Each cnnfiguration allows you to
interact with the network.

DESIGNED FOIlPIIlST-'I'IME BITBIlS
IlSERS
The BITBL'S Starter "it is the ideal wa\ for first·time
BITBL'S users to learn about the BITBL'S architecture.
Shortly after unpacking this Kit. you can bt' confidently
exeruting your first BITBL'S distributed ('ontrol application.

El'ER},'I'HING }'OlJ NEED
Based on standard Intel products. the BITBllS Starter "it
indudes the R1TBL'S analog board. the BITBllS digital
board. the PC Gatellay into the BITBL'S netllorK. [low('r
supply and cables. Supporting the standard product are
demonstration boards that the user can rnanipulatl' to
display analog or digital funl'tionality.

SERl'IfJE. SIlPPOR'I' AND 'l'RAINING
Intel provides worldWide support for repair. on-site service.
network design. and installation. Devrlopment support
options include phone support. Hubscription service. on-site
mnsulting. and customer training.

INTEL OlJALlT), AND RELlABILl'l'},
The BITBUS Starter Kit is designed and manufactured in
accordance wiLh Intel's high quality standards. We then
vl'rify qualit.y through rigorous testing in our state-of-the·art
~:nvironmental Test Laboratory.

18-2

SPECIFICATIONS

r;;-n
~

IRCB44I10
019l1li1 Board

IRCB44120
Analog Board

n ••re .:

BITBUS Starter Kit

ORDERING INFORMATION
BITBUSKIT

Basic Starter Kit which includes the' fulluwing items:
BITBUS Starter Kit User's Guide
HARDWARE
iPCX 344A-BITBUS IBM PC Interface Board-PC Gateway to BITBUS Network
iRCB 441OA-BITBUS Digital I/O Remute Controller Board
iRCB 4420A-BITBUS Analog 1/0 Remote Controller Board
Digital Demonstration Board
Analog Demonstration Board
Power Supply. 25 Watt. UL. VDE. CSA approved
Required ('.abies. SRAMS. Jumpers, etc.
SOrrWARE
iDCSI00-BITBUS Toolbox-The set of six software utilities that simplify development of host
application software
.
iDCS] ]O-Bitware-iDCX 5] interface library and declaration files
Starter Kit Application Software

BITBUSKITPLUS

Expanded version of the BITBUSKIT providing programming languages used to develop host
(8086 environment) and node code (805] environment) in addition to the basic BITBUS
network.

18-3

SPECIFICATIONS
Talt~

•• S ....ard BITBlJS" lalerraces
l.terI'ac~

SpedrlcaUoa

Electrical
Cahle

RS485
lO·conductor flat ribbon or 1 to 2 wire shielded twisted pail'
Hpin Standard DIN
Single·height. Double.
SW reset at a node
Set a node offline
Set port I/O address
XENIX/DOS shell escape from B8M
Display/create/change the value of
a user symbol
Unprotect
Controls echo and prompts

inter

DCS100

I/O ACCESS

each node. The task management commands are
especially useful when developing/troubleshooting
multitasking control programs.

Six commands are provided for writing to and reading from I/O ports on remote nodes. With these
commands, an operator can test the I/O connected
to a BITBUS node or monitor the status of an input
port. The I/O commands allow an operator to quickly isolate a problem at a remote node.

These four commands are used to send and receive
messages to and from tasks on remote nodes.

MEMORY ACCESS

MISCELLANEOUS COMMANDS

Seven memory access commands are provided.
These commands allow the operator to download
and upload both code (programs) and data (variables) between the host system and remote BITBUS
nodes .. Internal RAM memory within the 8044BEM
microcontroller can also be accessed. In addition,
the BBM'supports code download to both static
RAM and E2PROM devices. The memory access
commands are especially useful for on-target application development.

The BBM includes 15 commands that are used to
control the operating status of nodes, and to support
various troubleshooting fUnctions. These commands
include:

MESSAGE OPERATIONS

The HELP command-an on-line facility that displays the complete BBM command directory or detailed information on using the commands.

The BITBUS Monitor enables the user to reference
a memory location by using a symbolic reference or
label. For example, if a task running on a node includes a program variable called "rate", the operator can modify this variable simply by typing:

The SHELL command-allows an operator to do a
shell escape to DOS or XENIX, perform the needed
operating system function, and return to the monitor.
The RESET, FLUSH, and RESYNC commandsused to clear a node that is hung.

WIMEM .rate 6CH

OPERATING ENVIRONMENT

In this case, the program will execute with a value of
6C hex for "rate".
Symbolic references can also be used for other
BBM parameters, such as node address, port address, and data. Symbolic access allows the user to
more easily test and modify programs at run time.

The BITBUS Monitor will run on DOS, iRMX 86/286,
XENIX and iPDS-based systems. Both 5%" and 8"
media is provided for iRMX and XENIX systems. The
iPDS version of the monitor does not include the
following BBM commands (or equivalent UBI calls):
DELAY, LIST, PAUSE, RCMEM, RESYSC, SETPORT, SYMBOLS, TMSG, VERBOSE, WCMEM.

TASK MANAGEMENT

PC Bridge

Four commands are available to monitor and control
the running of tasks on the nodes.
The DCX 51 real time multitasking executive found
on all BITBUS boards can support up to 7 user tasks
(in addition to the RAC task). Each of these tasks
hav.e an initial Task Descriptor (ITO) which assigns a
function 10 to the task plus other important run-time
parameters used by the executive. By chaining ITDs
together, multiple tasks can become active upon
power up.

The PC Bridge is a communications program that
runs on a PC-DOS or MS-DOS system, and is used
to establish a communication link between, the PC
and an Intel iRMX 86/286 or XENIX-based microcomputer system. The software engineer can use
the Bridge in two ways. First, he can develop host or
node 'programs on the PC and download the code to
the host system or remote nodes. He can als6 use
the PC as a virtual terminal to the host system. The
PC Bridge effectively expands the development environment for the software engineer.

The BBM commands allow tasks to selectively be
made active (CTASK) or inactive (DT ASK). In addition, the SYS command can be used to display
which nodes are present and operational in a system and display the function IDs for active tasks on

The link between the PC and the host microcomputer can either be over an RS232 cable (supplied) or
via a modem link. The PC Bridge transfers data at up
to 19.2K baud (asynchronous) and supports
XON/XOFF flow control.

18-18

intJ

DCS100

OBJHEX

Documentation (supplied)

OBJHEX is an object code.to hex code conversion
utility similar to the OH51 hex converter supplied
with Intel "8051" languages. OBJHEX has the additional ability to retain the object module's symbol table during the conversion process. The table is
stored at the host system and enables the BITBUS
Monitor to symbolically access program memory.
OBJHEX runs on both DOS and iRMX86 (5",4" , 8"
medial-based systems.

BITBUS Toolbox Overview and
Installation Guide
BITBUS Monitor User's Guide
Universal BITBUS Interface
Use~'s Guide
BITBUS Interface Handlers User's
Guide
PC Bridge Communications Utility
User's Guide
BITBUS OBJHEX Conversion Utility
User's Guide

UDI2DOS
UDI2DOS converts Intel object code (8086 OMF) to
the .exe format so that it will run within a DOS environment.

iii
::;)

:z::
iii

0·;:
110111

0::;)

X
X
B
B
X

X
X
X
X
X

CI
"CI

..,III:z::

Q
N

X
A
X
X
X
X
X

149236-001
460237-001

Compatible Software

Order Number Description
BITBUS Toolbox Host Software
DCS100SU
Utilities, single-use license for development only. Includes RS232
cables to connect an Intel microcomputer system with an IBM·
PC-XT* or PC-AT", and full documentation. See above for media
provided.
DCS100BY
BITBUS Toolbox Host Software
Utilities. Same as above, except
sold with a buyout license. Allows
incorporation of UBI and BIH procedure libraries-no additional incorporation fee is required.

II)

ILl

Series II
III
IV
iPDS
IRMX5",4"
8"
XENIX5%"
8"
DOS

148685-002

Order Codes

Media Provided

:::Ii

460236-001

Intel ASM, PLlM, and C languages
(8086/80286/80386 versions)

SPECIFICATIONS

III
III

460235-001
148686-002

A
X
X
X
X
X

A
X
X

NOTES:

A. iPDS uses Release 1 Toolbox.
B. Supports operation with XENIX. XENIX disks not reo
quired.

18-19

inter

DCS110 BITWARE
DCS120 PROGRAMMERS SUPPORT PACKAGE

• Supports Calls to the 8044BEM
Microcontroller On-Chip, Multitasking
DCX 51 Executive
• Fully Compatible with Intel's ASM51
and PL/M51 Languages

• DCS110 also Includes DCM44 Code to
Support Emulation/Debug of BITBUSTM
Node Code using Intel In-Circuit
Emulators
• For DOS, IRMX@, iPDSTM, and Series
III/IV Development Environments

The DCS110 and DCS120 packages are designed to support software development of distributed control
BITBUS applications. Both products include a DCX51 interface library so that BITBUS application programs
can make calls to the DCX51 Executive. DCS110 also includes a DCM44 downloadable file that enables an
Intel in-circuit emulator such as the ICETM 5100/044 to emulate a BITBUS environment. By using an in-circuit
emulat~r together with DCS11 0, the developer can easily and quickly debug BITBUS application code.· ....

280731-1

18-20

October 1987
Order Number: 280731-1101

DCS110/DCS120

DCX 51 ENVIRONMENT
The 8044BEM microcontroller, used on every
BITBUS board, includes in firmware a preconfigured
version of the DCX 51 Executive. DCX 51 provides a
variety of services to the application code, including:
task management; interrupt management; inter·task
communications; memory management; and timing
services. Up to 7 user tasks can run concurrently
under DCX 51. Each task has a unique Initial Task
Descriptor (ITO) that describes to the executive several run·time parameters (e.g. stack space, priority
level, etc.). By also specifying an Initial Data De·

scriptor (100), the executive can be partially recon·
figured. Modifiable run·time constants include the
system clock rate, clock priority, internal memory
buffer size, and user (internal) memory size. DCX 51
calls are listed in Table 1.
By running applications under DCX 51, the designer
can make optimal use of the 8044BEM microcontrol·
ler. If a task needs to wait for a message, an inter·
rupt, or a time period, DCX 51 will temporarily assign
access to the 8044 to another task. In this way, mul·
tipletasks can access the microcontroller.

Table 1. DCX 51 Procedure Calls
Description

Call Name

Task Management Calls
RO$CREATE$TASK

Create and schedule a new task.

RO$DELETE$TASK

Delete specified task from system.

RO$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

Intertask Communication Calls
RO$ALLOCATE

Obtain a message buffer from the system buffer pool.

RO$DEALLOCATE

Return a message buffer to the system buffer pool.

RO$SEND$MESSAGE

Send a message to specified task.

RO$WAIT

Wait for a message event.

Memory Management Calls
RO$GET$MEM

Get available memory from the system memory pool.

RO$RELEASE$MEM

Release memory to the system memory pool.

Interrupt Management Calls
RO$DISABLE$INTERRUPT

,Temporarily disable an interrupt.

RO$ENABLE$INTERRUPT

Re·enable an interrupt.

RO$WAIT

Wait for an interrupt event.

Timer Management Calls
RO$SET$INTERVAL

Establish a time interval.

RO$WAIT

Wait for an interval event.

18·21

DCS110/DCS120

Interfacing
DCX
.
.to
.the
.'
. 51 Executive
To interface with the executive, DCS110 and
DCS120 both include a DCX 51 interface library plus
a set of "include" files. The interface library, which is
linked to the application modules, allow the code to
accessDCX 51 procedures. The "iriclude" files consist of DCX 51 declaration and macro definition files
that help simplify source code development. These
files are listed in Table 2.

DCS110 Bitware Software Package.
In addition to the DCX 51 interface files, DCS110.
also includes a DCM44 object file to support debug
of node code using an Intel in-circuit emulator.
DCM44 is the firmware found in all 8044BEM
BITBUS microcontrollers and together with an Intel

in-circuit emulator, successfully. duplicates. the
8044BEM environment. Emulators that are· supported include the ICETM 5100/044, the ICE 44, and the
EMV 44.

Developing Applications Software
Using OCS110, or DCS120 software to develop
BITBUS applications software is a straightforward,
multi-step process as diagrammed in Figure 1. The
designer uses a text ~ditor to write the application
code either in ASM 51 or PL/M 51. The source code
modules are then assembled/compiled along with
the DCX 51 "include" files. The final step is to link
together all of the modules, the DCX 51 interface
library, and the DCM441.LlB file. The linked/located
absolute object module can then be downloaded t6
the target board or burned into EPROM.

Table 2. DCS110/120 Flies
Filename

Description

DCX 51 Support Files:
DCX511.LlB

Interface library to the DCX 51 executive. Provides the linker with the address of data
variables and entry points for,DCX51 procedures called from other object modules.

DCX51A.EXT
DCX51 A. LIT
DCX51P.LlT

External and literal declaration files; These files support DCX 51 calls from ASM 51
and PL/M 51 code.
.
. ..
.

DCXBOP.EXT
DCXB1P.EXT
DCXB2P.EXT
DCXB3P.EXT

DCX 51 External procedure declarations for PL/M 51 modules using 8044 register
banks 0, 1, 2 or 3.

DCX51A.MAC

Initial Task Descriptor (ITO) and Initial Data Descriptor (100) macro definitions.

APPL1.A51
APPL2.A51

Sample application, parts 1 and 2;terriplate for generatinglTDs and 100•.

DCM441.LlB

This file maps out reserved memory needed by the 8044BEM firmware and is linked
to other user object modules using the RL51 Linker.
.

DCM44 Firmware Files (DCS110 Only):
DCM44

DCM44 (BITBUS) code for InteIICETM/EMV emulatorS.

18~22

intJ

DCS110/DCS120

WRITE
SOURCE CODE

COMPILE/
ASSEMBLE

LINK

LOAD/EXECUTE

LEGEND:

(

FILE
)

DCS 110/120 FILE
SOFTWARE TOOL

DCS110 ONLY
280731-2

Figure 1. DCS 11 0/120 Software Development Environment
DCS120BY

Development Environments
Both DCS110 and DCS120 are shipped with media
to support software development on PC/MS-DOS,
iRMX 86, iPDS, and Intellec® Series III/IV systems.
DCS110 is available with a single-use license for application development and debug. Designers planning to incorporte DCX 51 files in their application
should purchase the DCS120 "buyout" product.
Order Codes Description
Bitware Software Package. Includes
DCS110SU
DCM44 code to emulate a BITBUS
environment when using an Intel incircuit emulator and interface files to
support procedure calls to DCX 51.
Provided with documentation and
PC-DOS, iRMX 86 (5%" , 8"), iPDS,
and Series III/IV media. Single-use
license.

Programmers Support Package. Includes interface files to support procedure calls to DCX 51. Provided
with documentation and PC-DOS,
iRMX 86 (5%", 8"), iPDS, and Series III/IV media. Buyout license allows incorporation of software into
product-no additional incorporation
fee is required.

COMPATIBLE SOFTWARE TOOLS
DCS100

AEDIT

'XENIX is a trademark of Microsoft Corp.

18-23

BITBUS Toolbox Host Software Utilities for PC/MS-DOS, iRMX 86/286,
XENIX·, iPDS, and Series III/IV host
systems.
Source Code and Text Editor for all
Intel host environments (consult
data sheet for order codes).

intJ

DCS110/DCS120

8051 LANGUAGES
(Note: All products also include RL51 Linker/Relocator, LlB51 Librarian, and OH51 object to hex code
converter)
DB6ASM51
ASM 51 Assembler for PCDOS host system
RB6ASM51
ASM 51 Assembler for iRMX
86 host system
IB6ASM51
ASM.51 Assembler for Series
III/IV host systems
MC151ASM
ASM 51 Assembler for iPDS
and Series II host systems
DB6PLM51
PL/M 51 Compiler for PC-DOS
host system
RB6PLM51
PL/M 51 Compiler for IRMX 86
host system
IB6PLM51
PL/M 51 Compiler for Series
III/IV host systems
iMDX352
PL/M 51 Compiler for iPDS and
Series II host systems

IN-CIRCUIT EMULATORS AND PROM
PROGRAMMERS
(Note: + indicates that the product is no longer
available)
ICE51 00/044
In-Circuit Emulator for the RUPITM-44 Family (hosted on PCDOS, and Series III/IV-see
data sheet for order codes)
ICE-44:+8044 In-Circuit Emulator (hosted on Series II-IV systems)
iPDSEMV44CON + Kit to add 8044 support to an
EMV-51 /51 A emulator (iPDS
host)
iUP-200A,
Universal PROM programmer
iUP-201 A
(hosted on PC-DOS, iPDS, and
Series III/IV; see data sheet for
order codes)

1B-24

8051
SOFTWARE PACKAGES
• Choice of hosts:
PCDOS 3.0 based IBM" PC XT/AT* and
iRMX®86

• LIB51 Librarian which lets
programmers create and maintain
libraries of software object modules

• Supports all members of the Intel
MCS® ·51 architecture

8051 Software Development Package
Contains the following:

PL/M51 Software Package Contains the
following:

• 8051 Macro Assembler which gives
symbolic access to 8051 hardware
features

• PL/M51 Compiler which is designed to
support all phases of software
implementation
• RL51 Linker and Relocator which
enables programmers to develop
software in a modular fashion

• RL51 Linker and Relocator program
which links modules generated by the
assembler
• LIB51 Librarian which lets
programmers create and maintain
libraries of software object modules

LEGEND

D
:-D----:'
,,-----,

INTEL DEVELOPMENT
TOOLS AND OTHER
PRODUCTS

MCS«·51
SOFTWARE TOOLS
USER·CODED
SOFTWARE

162771-1

Figure 1. MCS® ·51 Program Development Process

·IBM and AT are registered trademarks of International Business Machines Corporation.

18-25

November 1988
Order Number: 162771-006

inter

8051 Software Packages

PL/M 51 SOFTWARE PACKAGE

•
•
•
•

High-level programming language for
the Intel MCS® -51 single-chip
microcomputer family
Enhanced to support boolean
processing
Tailored to provide an optimum
balance among on-chip RAM usage,
code size and code execution time
Produces relocatable object code
which is linkable to object modules
generated by all other 8051 translators

•
•
•
•
•

Allows programmer to have complete
control of microcomputer resources
Extends high-level language
programming advantages to
mlcrocontroller software development
Improved reliability, lower maintenance
costs, Increased programmer
productivity and software portability
Includes the linking and relocating
utility and the library manager.
Supports all members of the Intel
MCS® -51 architecture

PL/M 51 is a structured, high-level programming language for the Intel MCS-51 family of microcomputers. The
PLiM 51 language and compiler have been designed to support the unique software development requirements of the single-chip microcomputer environment. The PL/M language has been enhanced to support
Boolean processing and efficient access to the microcomputer functions. New compiler controls allow the
programmer complete control over what microcomputer resources are used by PL/M programs.
PL/M 51 is the high-level alternative to assembly language programming for the MCS-51. When code size and
code execution speed are not critical factors, PLiM 51 is the cost-effective approach to developing reliable,
maintainable software.
The PL/M 51 compiler has been designed to support efficiently all phases of software implementation with
features like a syntax checker, multiple levels of optimization, cross-reference generation and debug record
generation.
ICETM 5100 is available for on-target debugging.
Software available for PC DOS 3.0 based IBM' PC XT/AT' Systems.

LEGEND

o
-----,

INTEL DEVELOPMENT
TOOLS AND OTHER
PRODUCTS

Mess ·51
SOFTWARE TOOLS

10'
_____ I1

USER·CODED
SOFTWARE

162771-2

Figure 2. PL/M51 Software Package

18-26

8051 Software Packages

PL/M 51 COMPILER
FEATURES

Interrupt Handling

Major features of the Intel PL/M 51 compiler and
programming language include:

A procedure may be defined with the INTERRUPT
attribute. The compiler will generate code to save
and restore the processor status, for execution of
the user-defined interrupt handler routines.

Structured Programming
PL/M source code is developed in a series of modules, procedures, and blocks. Encouraging program
modularity in this manner makes programs more
readable, and easier to maintain and debug. The
language becomes more flexible, by clearly defining
the scope of user variables (local to a private procedure, for example).

Language Compatibility
PLIM 51 object modules are compatible with object
modules generated by all other MCS-51 translators.
This means that PL/M programs may be linked to
programs written in any other MCS-51 language.

Compiler Controls
The PL/M 51 compiler offers controls that facilitate
such features as:
- Including additional PL/M 51 source files from
disk
- Cross-reference
- Corresponding assembly language code in the
listing file

Program Addressing Control

Object modules are compatible with In-Circuit Emulators and Emulation Vehicles for MCS-51 processors: the DEBUG compiler control provides these
tools with symbolic debugging capabilities.

The PL/M 51 compiler takes full advantage of program addressing with the ROM (SMALL/MEDIUMI
LARGE) control. Programs with less than 2 KB code
space can use the SMALL or MEDIUM option to
generate optimum addressing instructions. Larger
programs can address over the full 64 KB range.

Supports Three Data Types

Code Optimization

PLIM makes use of three data types for various applications. These data types range from one to sixteen bits and facilitate various arithmetic, logic, and
address functions:
- Bit: a binary digit
- Byte: 8-bit unsigned number or,
- Word: 16-bit unsigned number.

The PL/M 51 compiler offers four levels of optimization for significantly reducing overall program size.
- Combination or "folding" of constant expressions; "Strength reductions" (a shift left rather
than multiply by 2)

Another powerful facility allows the use of BASED
variables that map more than one variable to the
same memory location. This is especially useful for
passing parameters, relative and absolute addressing, and memory allocation.

Two Data Structuring Facilities
PL/M 51 supports two data structuring facilities.
These add flexibility to the referencing of data stored
in large groups.
- Array: Indexed list of same type data elements
- Structure: Named collection of same or different
type data elements
- Combinations of Both: Arrays of structures or
structures of arrays.

Machine code optimizations; elimination of superfluous branches
Automatic overlaying of on-chip RAM variables
Register history: an off-chip variable will n~t be
reloaded if its value is available in a register.

Error Checking
The PLIM 51 compiler has a very powerful feature
to speed up compilations. If a syntax or program error is detected, the compiler will skip the code generation and optimization passes. This usually yields
a 2X performance increase for compilation of programs with errors.
A fully detailed set of programming and compilation
error messages is provided by the compiler and user's guide.

18-27

infef

8051 Software Packages

BENEFITS

Lower Development Cost

PL/M 51 is designed to be an efficient, cost-effective solution to the special requirements of MCS-51
Microsystem Software Development, as illustrated
by the following benefits of PLIM use:

Increases in programmer productivity translate immediately into lower software development costs
because less programming resources are required
for a given programmed function.

Low Learning Effort

Increased Reliability

PL/M 51 is easy to learn and to use, even for the
novice programmer.

PL/M 51 is designed to aid in the development of
reliable software (PL/M programs are simple statements of the program algorithm). This substantially
reduces the risk of costly correction of errors in systems that have already reached full production
status, as the more simply stated the program is, the
more likely it is to perform its intended function.

Earlier Project Completion
Critical projects are completed much earlier than
otherwise possible because PL/M 51, a structured
high-level language, increases programmer productivity.

Easier Enhancements and
Maintenance
Programs written in PL/M tend to be self-documenting, thus easier to read and understand. This means
it is easier to enhance and maintain PLIM programs
as the system capabilities expand and future products are developed.

RL51 LINKER AND RELOCATOR
•

Links modules generated by the
assembler and the PL/M compiler

•

Locates the linked object to absolute
memory locations

•

Enables modular programming of
software-efficient program
development

•

Modular programs are easy to
understand, maintainable and reliable

The MCS-51 linker and relocator (RL51) is a utility which enables MCS-51 programmers to develop software in
a modular fashion. The utility resolves all references between modules and assigns absolute memory locations to all the relocatable segments, combining relocatable partial segments with the same nanie.
With this utility, software· can be developed more quickly because small functional modules are easier to
understand, design and test than large programs.
The total number of allowed symbols in user-developed software is very large because the assembler number
of symbols' limit applies only per module, not to the entire program. Therefore programs can be more readable
and better documented. RL51 can be invoked either manually or through a batch file for improved productivity.
Modules can be saved and used on different programs. Therefore the software investment of the customer is
maintained.
RL51 produces two files. The absolute object module file can be directly executed by the MCS-51 family. The
listing file shows the results· of the link/locate process.

18-28

8051 Software Packages

LlB51 LIBRARIAN
The LlB51 utility enables MCS-51 programmers to
create and maintain libraries of software object modules. With this utility, the customer can develop standard software modules and place them in libraries,
which programs can access through a standard interface. When using object libraries, the linker will

call only object modules that are required to satisfy
external references.
Consequently, the librarian enables the customer to
port and reuse software on different projects-thereby maintaining the customer's software investment.

ORDERING INFORMATION

Order Code

Operating Environment

D86PLM51

PL/M51 Software for PC DOS 3.0 Systems

R86PLM51

PL/M51 Software for iRMX 86 Systems

Documentation Package

SUPPORT:

PLIM 51 User's Guide

Hotline Telephone Support, Software Performance
Report (SPR), Software Updates, Technical Reports, and monthly Technical Newsletters are available.

MCS-51 Utilities User's Guide

18-29

inter

8051 Software Packages

8051 SOFTWARE DEVELOPMENT PACKAGE
• Symbolic relocatable assembly
language programming for 8051
microcontrollers
• Produces Relocatable Object Code
which is linkable to other 8051 Object
Modules

• Encourage modular program design for
maintainability and reliability
• Macro Assembler features conditional
assembly and macro capabilities
• Supports all members of the Intel
MCS® 51 architecture

The 8051 software development package provides development system support for the powerful 8051 family
of single chip microcomputers. The package contains a symbolic macro assembler and relocationllinkage
utilities.
The assembler produces relocatable object modules from 8051 macro assembly language instructions. The
object code modules can be linked and located to absolute memory locations. This absolute object code may
be used to program the 8751 EPROM version of the chip:The assembler output may also be debugged using
.
the family of ICE 5100.
The converter translates 8048 assembly language instructions into 8051 source instructions to provide software compatibility between the two families of microcontroliers.
Software available for PC DOS 3.0 based IBM' PC XT/AT Systems.

LEGEND

D
:0----:

I,, _____ 1I

INTEL DEVELOPMENT
TOOLS AND OTHER
PRODUCTS
MCS·51
SOFTWARE TOOLS

USER-CODED
SOFTWARE

162771-1

Figure 1. MCS® ·51 Program Development Process

18-30

8051 Software Packages

8051 MACRO ASSEMBLER
•

Gives symbolic access to powerful
8051 hardware features

•

Produces object file, listing file and
error diagnostics

•

Object flies are linkable and locatable

•

Provides software support for many
addressing and data allocation
capabilities

•

Symbolic Assembler supports symbol
table, cross-reference, macro
capabilities, and conditional assembly

The 8051 Macro Assembler (ASM51) translates symbolic 8051 macro assembly language modules into linkable and locatable object code modules. Assembly language mnemonics are easier to program and are more
readable than binary or hexadecimal machine instructions. By allowing the programmer to give symbolic
names to memory locations rather than absolute addresses, software design and debug are performed more
quickly and reliably. Furthermore, since modules are linkable and relocatable, the programmer can do his
software in modular fashion. This makes programs easy to understand, maintainable and reliable.
The assembler supports macro definitions and calls. This is a convenient way to program a frequently used
code sequence only once. The assembler also provides conditional assembly capabilities.
Cross referencing is provided in the symbol table listing, showing the user the lines in which each symbol was
defined and referenced.
ASM51 provides symbolic access to the many useful addressing features of the 8051 architecture. These
features include referencing for bit and byte locations, and for providing 4-bit operations for BCD arithmetic.
The assembler also provides symbolic access to hardware registers, I/O ports, control bits, and RAM addresses. ASM51 can support all members of the 8051 family.
Math routines are enhanced by the MUltiply and DIVide instructions.
If an 8051 program contains errors, the assembler provides a comprehensive set of error diagnostics, which
are included in the assembly listing or on another file.
ICE 5100 is available for program debugging.

RL51 LINKER AND RELOCATOR PROGRAM
•

Links modules generated by the
assembler

•

Locates the linked object to absolute
memory locations

•

Enables modular programming of
software for efficient program
development

•

Modular programs are easy to
understand, maintainable and reliable

The 8051 linker and relocator (RL51) is a utility which enables 8051 programmers to develop software in a
modular fashion. The linker resolves all references between modules and the relocator assigns absolute
memory locations to all the relocatable segments, combining relocatable partial segments with the same
name.
With this utility, software can be developed more quickly because small functional modules are easier to
understand, design and test than large programs.
The number of symbols in the software is very large because the assembler symbol limit applies only per
module not the entire program. Therefore programs can be more readable and better documented.
Modules can be saved and used on different programs. Therefore the software investment of the customer is
maintained.

18-31

inter

8051 Software Packages

RL51 produces two files. The absolute object module file can be directly executed by the S051 family. The
listing file shows the results of the Iinkllocate process.

LIB51 LIBRARIAN
The L1B51 utility enables MCS-51 programmers to create and maintain libraries of software object modules.
With this utility, the customer can develop standard software modules and place them in libraries, which
programs can access through a standard interface. When using object libraries, the linker will call only object
modules that are required to satisfy external references.
Consequently, the. librarian enables the customer to port and reuse software on different projects-thereby
maintaining the customer's software investment.
.

ORDERING INFORMATION

Order Code

Operating Environment

D86ASM51

S051 Assembler for PCDOS 3.0 Systems

R86ASM51

S051 Assembler for iRMX S6 Systems

Documentation Package:

SUPPORT:

MCS-51 Macro Assembler User's Guide
MCS-51 Utilities User's Guide for SOSO/SOS5
Based Development System

Hotline Telephone Support, Software Performance
Reporting (SPR), Software Updates, Technical Reports, Monthly Newsletter available.

1S-32

ICETM-5100/044 In-Circuit Emulator
for the RUPITM-44 Family
Full-Speed, Real-Time
• Precise,
Emulation of the RUPITM-44 Family of

•

Symbolic Debugging Enables Access to
Memory Locations and Program
Variables

•
•

Four Address Breakpoints Plus InRange, Out-of-Range, and Page Breaks

Peripherals

•
•

64 KB of Mappable High-Speed
Emulation Memory

•
•
•
•

Serial Link to IBM* PC AT or PC XT
(and PC DOS Compatibles)

254 24-bit Frames of Trace Memory (16
Bits Trace Program Execution
Addresses and 8 Bits Trace Eternal
Events)

ASM-51 and PL/M-51 Language
Support
Built-in CRT-Oriented Text Editor
Source Code Display

Equipped with the Integrated Command
Directory (ICDTM) That Provides
- On-Line Help
- Syntax Guidance and Checking
- Command Recall

Disassembler and Single-Line
• On-Line
Assembler to Help with Code Patching
Provides an Ideal Environment for
• Debugging
BITBUSTM Applications
Code

• Symbolic Debug

The ICETM·51 00/044 in·circuit emulator is a high·level, interactive debugger that is used to develop and test
the hardware and software of a target system based on the RUPITM·44 family of peripherals. The ICE·
5100/044 emulator can be serially linked to an Intellec® Series III/IV or an IBM PC AT or PC XT. The emulator
can communicate with the host system at standard baud rates up to 19.2K. The design of the emulator
supports all of the RUPI·44 components at speeds up to and including 12 MHz.
'IBM is a registered trademark of International Business MaChines Corporation. Intel Corporation assumes no responsibility
for the use of any circuitry other than circuitry embodied in an Intel product. No other patent licenses are implied. Information
contained herein supersedes previously published specifications on these devices from Intel.

280325-1

18·33

September 1988
Order Number: 280325·002

ICETM·5100/044

tion of the microcontroller to debug the system as a
completed unit.

PRODUCT OVERVIEW
The ICE-51 00/044 emulator provides full emulation
support for the RUPI-44 family of peripherals, including 8044-based BITBUSTM board products: The
RUPI-44 family consists of the 8044, the 8744, and
the 8344.

The final product verfication test can be. performed
using the ROM or EPROM version of the microcontroller. Thus, the ICE-5100/044 emulator provides
the ability to debug a prototype or production system
at any stage in its development without introducing
extraneous hardware or software test tools. .

The ICE-5100/044 emulator enables hardware and
software development to proceed simultaneously.
With the ICE-5100/044, prototype hardware can be
added to the system as it is designed and software
can be developed prior to the completion .of the
hardware prototype. Software and hardware integration can occur while the product is being developed.

The ICE-5100/044 emulator consists of the following components (see Figure 1):

The ICE-5100/044 emulator assists four stages of
development: .
.

• Power supply
• AC and DC power cables

PHYSICAL DESCRIPTION

• Controller pod
• Serial Cable (host-specific)

• Software debugging
• Hardware debugging

• User probe assembly (consisting of the processor module and the user cable)

• System integration
• System test

• Crystal power accessory (CPA)
• 40-pin target adaptor

Software Debugging
The ICE~5100/044 emulator can be operated without being connected to the target system and before
any of the user's hardware is available (provided external data RAM is not needed). In this stand-alone
mode, the ICE~51 00/044 emulator can be used to
facilitate program development.

Hardware Debugging
The ICE-5100/044 emulator's AC/DC parametric
characteristics match the microcontroller's. The emulator's full-speed operation makes it a valuable tool
for debugging hardware, including time-critical serial
port, timer, and external interrupt interfaces.

System Integration
Integration of software and hardware can begin
when the emulator is plugged into the microcontroller socket of the prototype system hardware. Hardware can be added, modified, and tested immediately. As each section of the user's hardware is com~
pleted, it can be added to the prototype. Thus, the
hardware and software can be system tested in realtime operation as each section becomes available.

System Test
When the prototype is complete, it is tested with the
final version of the system software. The ICE5100/044 emulator is then used for real-time emula-

• Clips assembly
• Software (includes the ICE-5100/044 emulator
software,. diagnostic software, and a tutorial)
The controller pod contains 64 KB of emulation
memory, 254- by 24-bit frames of trace memory, and
the control processor. In addition, the controller pod
houses a BNC connector that can be used to connect up to 10 multi-ICE compatible emulators for
synchronous starting and stopping of emulation.
The serial .cable connects the host system to the
controller pod. The serial cable supports a subset of
the RS-232C signals.
The user probe assembly consists of a user cable
and a processor module. The processor module
houses the emulation processor and the interface
logic. The target adaptor connects to the processor
module and provides an electrical and mechanical
interface to the target microcontroller socket.
The crystal power accessory (CPA) is a small, detachable board that connects to the controller pod
and enables the ICE-5100/044 emulator to run in
stand-alone mode. The target adaptor plugs into the
socket on the CPA; the CPA then supplies clock and
power to the user probe.
.
The clips assembly enables the user to trace external events. Eight bits of data are gathered on the
rising edge. of PSEN during opcode fetches. The
clips information can be displayed using the CLIPS
option with the PRINT command.

18-34

inter

ICETM-51 00/044

280325.,2

Figure 1.'The ICETM-5100/044 Emulator Hardware
The ICE-51 00-044 emulator software supports mnetroller of the target system. Emulation is a transparmonics, object file formats, and symbolic references
ent process that happens in real-time. The execution
of the user software is facilitated with the ICEgenerated by Imel's ASM-51 and PLlM-51 programming languages. Along with the ICE-51 001044 emu51001044 command language..
latar software is a customer confidence test disk
with diagnostic routines that check the operation of
the hardware.
Memory Mapping
The on-line tutorial is written in the ICE-5100 command language. Thus, the user is able to interact
with and use the ICE-51001044 emulator while executing the tutorial.
.
A comprehensive set of documentation is provided
with the ICE-51 001044 emulator.

ICETM-5100/044 EMULATOR

FEATURES
The ICE-51 001044 emulator has been created to assist a product designer in developing, debugging and
testing designs incorporating the RUPI-44 family of
peripherals. The following sections detail some of
the ICE-5100/044 emulator features.

There is a 64 KB of memory that can be mapped to
the CODE memory space in· 4 KB blocks on 4 KB
boundaries. By' mapping memory to the ICE5100/044 emulator, software development can proceed before the user hardware is available. '

Memory Examination and Modification
The memory space for the 8044 microcontroller and
its target hardware is fully accessible through the
emulator. The ICE-51 00/044 emulator refers to four
physically distinct memory spaces, as follows:
• CODE-references program memory
• IDATA-references internal data memory
• RDATA-references special function register
memory
• XDATA-references external data memory

Emulation
Emulation is the controlled execution of the user's
software in the target hardware or in an artificial
hardware environment that duplicates the microcon-

ICE-5100/044 emulator commands that access
memory use one of the special prefixes (e.g., CODE)
to specify the memory space.

18-35

inter

ICETM_5100'044

The microcontroller's special function registers and
register bits can be accessed mnemonically (e.g.,
DPL, TCON, CY, P1.2) with the ICE-51 00/044 emulator software.
'
Data can be displayed or modified in one of three
bases: hexadecimal, decimal, or binary. Data can
also be displayed or modified in one of two formats:
ASCII or unsigned integer. Program code can be disassembled and displayed as ASM-51 assembler
mnemonics. Code' can be modified with standard
ASM-51 statements using the built-in single-line assembler.

Breakpoint Specifications
Breakpoints are used to halt a user program in order
to examine the effect of the program's execution on
the target system. The ICE-51 00/044 emulator supports three different types of break specifications:
• Specific address break-specifying a single address point at which emulation is to be stopped.
• Range break-an arbitrary range of addresses
can be specified to halt emulation. Program execution within or, optionally, outside the range
halts emulation.
• Page break-up to 256 page breaks can be specified. A page break is defined as a range of adiresses that is 256-bytes long and begins on a
'56-byte address boundary.

Symbolic references can be used to specify memory
locations. A symbolic reference is a procedure
name, line number, program variable, or label in the
user program that corresponds to a location.
Some typical symbolic functions include:
• Changing or inspecting the value of a program
variable by using its symbolic name to access the
memory location.
• Defining break and trace events using symbolic
references.
• Referencing variables as primitive data types.
The primitive data types are ADDRESS, BIT,
BOOLEAN, BYTE, CHAR (character), and
WORD.
The ICE-51 00/044 emulator maintains a virtual symbol table (VST) for program symbols. A maximum of
61 KB of host memory space is available for the
VST. If the VST is larger than 61 KB, the excess is
stored on available host system disk space and is
paged in and out as needed. The size of the VST is
. limited only by the disk capacity of the host system.
Print newest
,~
I hIt> PRINT'*NEWEST
4

Bre~ : registers are user-defined debug definitions
used to create and store breakpoint definitions.
Break registers can contain multiple breakpoint definitions and can ,optionally call debug procedures
when emulation halts.

Trace Specifications
Tracing can be triggered using specifications similar
to those w:;ed for breaking. Normally, the
ICE-5100/044 emulator traces program activity
while the user ~rogram is executing. With a trace
specification, trb.jng can be triggered to occur only
when specific conditions are met during execution.
Up to 254 24-bit frames of trace information are collected in a buffer during emulation. Sixteen of the 24
bits trace instruction execution addresses, and 8 bits
capture external events (CLIPS) .

four instructions in the buffer

FRAME
ADDR
CODE
(28)
300A
C02A
(30
300C
2532
(32)
300E
F52A
(34)
3010
B53210
hIt>
h1t>PRINT CLIPS OLDEST 2
FRAME
ADDR
CODE
(00)
007AH
0508
007CH
80E6
(01)

INSTRUCTIONS
PUSH
2AH
ADD
A, 32H
MOV
2AH, A
CJNE
A,32H, $+10H

Buffer display showing clips
INSTRUCTIONS
CLIPS
(76543210)
INC INDX PTR
10101111
SJMP (#28)
00100010

280325-3

Figure 2. Selected Trace Buffer Displays

18-36

ICETM·5100/044

The trace buffer display is similar to an ASM-51 program listing as shown in Figure 2. The PRINT command enables the user to selectively display the
contents of the trace buffer. The user has the option
of displaying the clips information as well as dissassembled instructions.

ARM

FOREVER

TIL

USING

Procedures
Debugging procedures (PROCs) are a user-defined
group of ICE-51 00/044 commands that are executed as one command. PROCs enable the user to define several commands in a named block structure.
The commands are executed by entering the name
of the PROC. The PROC bodies are a simple DO ...
END construct.
-

TRACE

\:>00 ~o.

hI t > GO FROM I3H

ARM

FOREVER

TIL

USING

TRACE-

hI t > GO FROM I3H USING

I3H USING brl
TRACE

hIt>GO FROM I3H USING brl TRACE

OUTSIDE

PAGE FROM TIL

hIt>GO FROM 13H USING brl TRACE traceit

280325-4

Figure 3. The Integrated Command Directory for the GO Command
18-37

infef

ICETM-51 00/044

PROCs can simulate missing hardware or software,
set breakpoints, collect debug information, and execute high-level software patches. PAOCs can be
copied to text files on disk, then recalled for use in
later test sessions. PAOCs can also serve as program diagnostics, implementing ICE-51 00/044 emulator commands or user-defined definitions for special purposes.

On-Line Syntax Menu
A special syntax menu, called the Integrated Command directory (ICD), similar to the, one used for the
121CETM system and the VLSiCE-96 emulator, aids in
creating syntactically correct command lines. Figure
3 shows an example of ,the ICD and how it changes
to reflect the options available for the GO command.

Help

tor's memory along with the .user's code to enable
rapid debug,of 8044 BITBUS applications code.

DESIGN CONSIDERATIONS
The height of the processor module and the target
'adaptor need to be considered for target systems.
Allow at least 1% inches (3.8 cm) of space to fit the
processor module and target adaptor. Figure 5
shows the dimensions of the processor module.
Execution of user programs that contain interr4Pt
routines causes incorrect data to be stored in the
trace buffer. When an interrupt occurs, the next in-'
struction to be executed is placed into the trace buff- .
er before it is actually executed. Following completion of the interrupt routine; .the instruction is execut-'
ed and again placed intp the trace buffer.

ELECTRICAL CONSIDERATIONS

The HELP command provides ICE-51 00/044 emulation command assistance via the host system terminal. On-line HELP is available for the ICE-5100/044
emulator commands shown in Figure 4.

The emulation processor's user-pin timings and,
loadings are identical to the 8044 component, except as follows.

BITBUSTM Applications Support

• Up to 25 pF of additional pin capacitance is contributed by the processor module and target
adaptor assemblies. "

The ICE-5100/044 emulator provides an ideal environment for developing applications code for BITBUS board products such as the ACB~44/10, the
RCB-44/20, the PCX-344,and the iSBXTM-344
board.
'
The BITBUS firmware, available separately as BITWAAE, can be loaded into the ICE-51 00/044 emula-

• Pin 31, EA, has approximately 32 pF of additional·
capacitance loading due to sensing circuitry.
• Pins 18 and 19, XTAL 1 and XTAL2 respectively,
have approximately 15-16 pF of additional capacitance when configured for crystal operation.' '

.f(
/hIt > HELP
HELP,is available for:
ADDRESS
BYTE
CURHOME
DISPLAY
EXPRESSION

APPEND
CHAR
CURX
DO
GO
~EYS
LABEL
: MAP
MENU
OPERATOR PAGING
REFERENCE REGS
STRING
SYMBOLIC
VERIFY
VERSION
hIt>

ASM
CI
CURY
DYNASCOPE
HELP
LINES
MODIFY
PARTITION
REMOVE
SYNCSTART
WAIT

BASE.
CNTL_C
DCI
EDIT
IF
LIST
MODULE
PRINT
REPEAT
TEMPCHECK
WORD

BIT
COMMENTS
DEBUG
ERROR
INCLUDE
LITERALLY
MSPACE
PROC
RESET
TRCREG
WRITE

BOOLEAN
CONSTRUCTS
DEFINE
EVAL
INVOCATION
LOAD
MTYPE
PSEUDO_VAR
RETURN
TYPES

BRKREG'
COUNT
DIR
EXIT
ISTEP
I
LSTEP
NAMESCOP;E
PUT
SAVE
VARIABLE

Ul\__~--~~~________~~------~~.
280325-5

Figure 4. HELP Menu
18-38

ICETM·5100/044

PROCESSORMODULE~

~a~ ~~/,'J
T
'u : 313".~
1!~~lr;i

I ----------1

39·

(9gem)

al:!):: m~

r------

CABLE BODY

~N 1

TOP VIEW

---------~+I--(10.~'em)__1

5 fr..".,
SIDE V1EW

PROCESSOR MODULE

--..£Jc

=--t...

TARGET
ADAPTOR

280325-6

Figure 5. Processor Module Dimensions

HOST REQUIREMENTS

PHYSICAL CHARACTERISTICS

• IBM PC AT or PC XT (or PC DOS compatible)
with 512 KB of available RAM and a hard disk
running under the DOS 3.0 ( or later) operating
system.

Controller Pod

• Disk drives-dual floppy or one hard disk and one
floppy drive required.

ICETM·5100/044 EMULATOR
SOFTWARE PACKAGE

Width:
Height:
Depth:
Weight:

8-%"
1-%"
13-%"
4 Ibs

(21
cm)
( 3.8 cm)
(34.3 cm)
( 1.85 kg)

User Cable

• ICE-51 00/044 emulator software
• ICE-51 00/044 confidence tests

The user cable is 3 feet (approximately 1 m)

• ICE-51 00 tutorial software

Processor Module

EMULATOR PERFORMANCE
Memory
Mappable
full-speed
emulation code
memory

64 KB

Mappable to user or ICE5100/044 emulator memory in 4 KB blocks on 4 KB
boundaries.

Trace memory

254 x 24 bit frames

Virtual Symbol
Table

A maximum of 61 KB of
host memory space is
available for the virtual
symbol table (VST). The
rest of the VST resides on
disk and is paged in and
out as needed.

(With the target adaptor attached)
Width:
3- 10/,6" (9.7 cm)
Height: 4"
(10.2 cm)
Depth:

1-%"

(3.8 cm)

Power Supply
Width:
Height:
Depth:
Weight

7-%"
4"
11 "
151bs

(18.1 cm)
(10.06 cm)
(27.97 cm)
( 6.1 kg)

Serial Cable
The serial cable is 12 feet (3.6 m).

18-39

inter

ICETM·5100/044

ELECTRICAL CHARACTERISTICS
Power Supply
100-120V or 200-240V (selectable)
50-60 Hz
2 amps (AC max) @ 120V
1 amp (AC max) @ 240V

ENVIRONMENTAL
CHARACTERISTICS
Operating temperature
Operating humidity

+ 10"C to + 40°C (50°F to
104°F)
Maximum of 85% relative
humidity, non-condensing

ORDERING INFORMATION
Emulator Hardware and Software
Order Code
1044KITAD

1044KITD

Description
This kit contains the ICE-5100/044
user probe assembly, power supply
and cables, serial cables, target
adaptor, CPA, ICE-5100 controller
pod, software, and documentation for
use with an IBM PC AT or PC XT. The
kit also includes the 8051 Software
Development Package and the
AEDIT text editor for use on DOS
systems. [Requires software license.]
This kit is the same as the 1044KITAD
excluding the 8051 Software Development Package and the AEDIT text
editor. [Requires software license.]

Other Usefullntel® MCS®-51 Debug and
Development Support Products '
Order Code Description
D86ASM51
8051 Software Development Package (DOS version)-Consists of the
ASM-51 macro assembler which
gives symbolic access to 8051 hardware features; the RL51 linker and
relocator program that links modules
generated by ASM-51; CONV51
which enables software written for
the MCS-48 family to be up-graded to
run on the 8051, and the LlB51 Li-,
brarian which programmers can use
to create and maintain libraries of
software object modules. Use with
the DOS operating system (version
3.0 or later).
D86PLM51
PL/M-51 Software Package (DOS
version)-Consists of the PLlM-51
compiler which provides high-level
programming language support; the
LlB51 utility that creates and
maintains libraries of software object
modules, and the RL51 linker and
relocator program that links modules
generated by ASM-51 and PL/M-51
and locates the linked object mod'ules to absolute memory locations.
Use with the DOS operating system
(version 3.0 or later).
D86EDINL
AEDIT text editor for use with the
DOS operating system.

18-40

BITBIlS'" SOFTW"RE DEVEI..OPMENT ENVIRONMENT

Intel has all the software tools you'll need to implement high-performance applications using Intel
BITBUS" products_ Tools include assemblers and compilers for host and BITBUS node code
development, debug monitors, in-circuit emulators, and specialized BITBUS software_ Inters software
tools are full-featured, easy-to-use, and help generate reliable, easily maintained code in amlnimum
amount of time_ Inters complete solution helps get your BITBUS-based distributed network quickly to
market_

.''I'.I1S NE'I'WOIlIi. €ONFIGI1IlA'I'IONS
A BITBUS network usually consists of a master (or supervisory) node and multiple remote nodes as
shown on figure 1_ All BITBUS host interface boards and remote control boards use the 8044
BITBUS Enhanced Mlcrocontroller (8044BEM)_ The 8044BEM bas built-in communications software,
memory management and 110 control procedures together with a multitasking operating system_
This built-In software, known as DCM44, greatly simplifies the programmer's software design taSk,
BITBUS networks can be configured In two ways, either as distributed 110 systems with centralized
control. or as distributed control systems_

__________________

Irtli ClIlllllraUun a~~u~ nn n.'!;pllfI:cibllil) fur the LN'

arl) (ilTuilry Ulhrr Lhan rlrculLI') cmtxldJoo In un IntI.'! product. fIIo ullIN rlrnlit paLrnt lin·Il!II.'~ all'

Irnptk'd, InrurmaUII" IUI1&8itllC
._~

D D D
D D D

X X

X
X
X
E

C C

.!!;
::>
'0

ORD~RING

INFORMATION

"'••, tell••,., &m?
Intel publishes several databooks that provide detailed
technical information on these and other software products
together with application data. If you would like more
information about Intel software for BITBUS applications.
contact your local Intel sales office or distributor for the
following literature:

230973
210940
210918

• Distributed Control Modules Databook
• Development Tools Handbook
• Embedded Controller Handbook
BITBUS Software Products Order Codes:

......ac:t
BITBUS Toolbox
BITWARE
Programmer's Support Package

~.. {;otIe

iDCS100
iDCS110

iDCS120

18-45

iSBX™ 344A
BITBUSTM INTELLIGENT MULTIMODULETM BOARD
•

High Performance 12 MHz 8044
Controller

•

2 28-Pin JEDEC Memory Sites for
User's Control Functions

•

Integral Firmware Including the iDCX 51
Executive Optimized for Real-Time
Control Applications

•

Low Cost, Double-Wide iSBXTM BITBUS
Expansion MULTIMODULETM Board

•

Power Up Diagnostics

•

Full BITBUSTM Support

The iSBX 344A BITBUS Intelligent MULTIMODULE board is the BITBUS gateway to all Intel products that
support the iSBX 1/0 Expansion Interface. Based on the highly integrated 8044 component (an 8-bit 8051
microcontroller and an SDLC-based controller on one chip) the iSBX 344A MULTIMODULE board extends the
capability of other microprocessors via the BITBUS interconnect. With the other members of Intel's Distributed
Control Modules (iDCM) family, the iSBX 344A MULTIMODULE board expands Intel's OEM microcomputer
system capabilities to include distributed real-time control. Like all members of the iDCM family, the iSBX 344A
MULTIMODULE board includes many features that make it well suited for industrial control applications such
as: data acquisition and monitoring, process control, robotics, and machine control.

280247-1

18-46

March 1988
Order Number: 280247·002

inter

iSBXTM 344A BOARD

OPERATING ENVIRONMENT

MULTIBUS® Expansion

Intel's Distributed Control Modules (iDCM) product
family contains the building blocks to implement
real-time distributed control applications. The iDCM
family incorporates the BITBUS interconnect to provide standard high speed serial communication between microcontrollers. The iDCM hardware products: including the iSBX 344A MULTIMODULE
board, iPCX 344A board and all iRCB BITBUS Remote Controller Boards communicate in an iDCM
system via the BITBUS interconnect as shown in
Figure 1.

Typically, MULTIBUS iSBC boards have a maximum
of two iSBX I/O expansion connectors. These connectors facilitate addition of one or two iSBX I/O
MULTIMODULE boards with varying numbers of I/O
lines. The iSBX 344A MULTIMODULE board increases the number of I/O lines that can be accommodated by a MULTIBUS system by at least an order of magnitude.

As a member of the iDCM product line the iSBX
344A MULTIMODULE board fully supports the BITBUS microcontroller interconnect. Typically, the
iSBX 344A MULTIMODULE board would be part of a
node (master or slave) on the BITBUS interconnect
in an iDCM system. As shown in Figure 2 the iSBX
344A MULTIMODULE board plugs into any iSBC®
board with an iSBX connector.
The iSBX 344A MULTIMODULE board is the hardware interface between Intel's MULTIBUS® and the
BITBUS environment. With this interface the user
can harness the capabilities of other Intel microprocessors e.g. 80386, 80286, 80186, 8086, 80188,
8088 in a iDCM system or extend an existing MULTIBUS system with the iDCM family.

Extending BITBUSTM/iDCM System
Processing Capability
The iSBX 344A MULTI MODULE board allows utilization of other processors in a iDCM system to accommodate particular application requirements. The
MULTIMODULE board is compatible with any iSBX
connector so that any board having a compatible
connector can potentially enhance system performance. Intel's DCS100 BITBUS Toolbox Software
provides easy to use high performance software interfaces for iSBC boards. The iSBC 86/35, 286/12,
and 188/48 boards are a few examples. Custom
configurations are also possible with user customized software.

BITBUS™
INTERCONNECT #2

280247-2

Figure 1. iDeM Operating Environment

18-47

iSBXTM 344A BOARD

ARCHITECTURE
Figure 3 illustrates the major functional blocks of the
iSBX 344A board: 8044 BITBUS Enhanced Microcontroller (BEM), memory, BITBUS microcontroller
interconnect, Byte FIFO interface, initialization and
diagnostic logic.

~
1/0 EXPANSION BUS

The iSBX 344A MULTIMODULE board memory consists of two internal and external memory. Internal
memory is located in the on-chip memory of the
iDCM controller. The iDCX 51 Ex~cutive and the remaining 8044 BEM firmware ration this resource.
However, eight bytes of bit addressable internal
memory are reserved for the user. Ample space is
reserved for user programs and data in the iSBX
344A MULTIMODULE board external memory.

BYTE FIFO
INTERFACE

OFF CHIP
MEMORY
~
DATA SITE
28PIN
CODE SITE

Two 28-pin JEDEC sites comprise the iSBX 344A
MULTIMODULE board external memory. One site
has been dedicated for data; the other for code. Table 1 lists the supported memory devices for each
site. Intel's 2764 and 27128 are examples. The user
may choose one of two memory configurations and
specify different memory sizes by placing the proper
jumpers at system initialization. The most flexible
configuration option provides the user with access to
the code site for program download or upload. This
feature ensures expansion of an existing system is
easily accommodated. For example, the addition of
another conveyor to a material handling system
would require adding another controller or controllers and changes to existing applications code and
addition of new code.

8044

BITBUS 1M ENHANCED

MICROCONTROLLER

t
BITBUS™
BUFFERS

The 8044 BEM microcontroller also includes built-in
firmware known as DCM44. This firmware includes a
set of functions called Remote Access and Control
(RAG), a preconfigured version of the DCX51 Executive, communications software, and a power-up test
procedure.

Memory

1
INITIALIZATION
& DIAGNOSTIC
LOGIC

face Unit (SIU). This dual processor architecture allows complex control and high speed communication to be realized cost effectively.

=~
BITBUS™ INTERCONNECT

280247-4

Table 1. Supported Memory Devices

Figure 3. iSBXTM 344A Block Diagram

iDCM Controller
The heart of the iSBX 344A MULTIMODULE board's
controlling and communication capability is the highly integrated 12 MHz 8044 microcontroller. The 8044
consists of the advanced 8-bit, 8051 microcontroller
and a SDLC-based controller called the Serial Inter-

18-48

Device

Data Site

Code Site

4Kx 8-64Kx 8
EPROM/ROM
2Kx8-32Kx8
SRAM
2Kx8-16Kx8
NVRAM and E2PROM

Yes

intJ

iSBXTM 344A BOARD

matically accepts messages for the FIFO. No user
code is required, increasing the time available for
application system development.

BITBUSTM Microcontroller
Interconnect
The iSBX 344A MULTIMODULE board fully supports
the BITBUS microcontroller interconnect. The
BITBUS interconnect is a serial bus optimized for
control applications. The interconnect supports both
synchronous and self-clocked modes of operation.
These modes of operation are selectable dependent
on application requirements as are the transmission
rates. Table 2 shows different combinations of
modes of operations, transmission rates, and distances. The SDLC-based protocol, BITBUS message format, and compatibility with Intel's other software and hardware products comprise the remainder of this established architecture. These features
contribute to BITBUS reliability and usefulness as a
microcontroller interconnect.
The BITBUS connection consists of one or two differential pair(s) of wires. The BITBUS interface of
the iSBX 344A MULTIMODULE board consists of a
half-duplex RS 485 transceiver and an optional
clock source for the synchronous mode of operation.

Byte FIFO Interface
The Byte FIFO Interface on the iSBX 344A
MULTIMODULE board implements the required
hardware buffering between the 8044 BEM and an
extension. An extension is defined as a device attached to the iSBX I/O expansion interface on the
iSBX 344A MULTIMODULE board. In an iDCM system, an example of an extension is an iSBC 286/12
board which may be considered the host board in a
MULTIBUS system. When used with the software
handlers in the BITBUS Toolbox, implementation of
this interface is complete.
For particular applications, the user may wish to develop a custom software interface to the extension
or host board. On the iSBX 344A MULTIMODULE
board side of the interface the iDCM firmware auto-

The Byte FIFO supports both byte and message
transfer protocol in hardware via three register ports:
data, command, and status. The extension side supports polled, interrupt, and limited DMA modes of
operation (e.g. 80186 type DMA controllers).

Initialization and Diagnostic Logic
Like the other members of Intel's Distributed Control
Modules (iDCM) product line, the iSBX 344A
MULTIMODULE board includes many features
which make it well suited for industrial control applications. Power up diagnostics is just one of these
features. Diagnostics simplify system startup considerably, by immediately indicating an 8044 BEM or
external bus failure. The LEOs used for power up
diagnostics are available for user diagnostics after
power up as well as to further contribute to reliable
operation of the system.
Initial iSBX 344A MULTIMODULE board parameters
are set by positioning jumpers. The jumpers determine the BITBUS mode of operation: synchronous,
self-clocked, transmission rate, and address of the
iSBX module in the BITBUS system. This minimizes
the number of spare boards to be stocked for multiple nodes, decreasing stocking inventory and cost.

INTEGRAL FIRMWARE
Resident firmware located in the 8044 BEM includes: a pre-configured iDCX 51 Executive for user
program development; a Remote Access and Control (RAG) function that enables user communication
and control of different microcontrollers and I/O
points; a communications gateway to connect the
BITBUS interconnect, iSBX bus, and iDCX 51 Executive tasks; and power up diagnostics.

Table 2. BITBUSTM Microcontroller Interconnect Modes of Operation
Speed
Kb/s

Maximum Distance
Between Repeaters
M/ft

Maximum # Nodes
Per Segment

. Maximum # Repeaters
Between a Master
and Any Slave

Synchronous

500-2400

30/100

Self Clocked

375
62.5

300/1000
1200/4000

28
28

2
10

Segment. DIstance between master and repeater or a repeater and a repeater.
Synchronous mode requires user supplied crystal.

18-49

intJ

iSBXTM 344A BOARD

The services provided by the iSBX 344A MULTIMODULE board integral firmware simplify the development and implementation of complex real-time
control application systems. All iDCM hardware
products contain integral firmware thus supplying
the user with a total system solution.
'

The Remote Access and Control Function is a special purpose task that allows the user to transfer
commands and program variables to remote BITBUS controllers, obtain the status of a remote I/O
line(s), or reverse the state ofa remote I/O line.
Table 4 provides a complete listing of the RAC services. No user code need be written to use this function.

Intel provides a complete development environment
for the iSBX 344A MULTIMODULE board. Software
development support consists of: the 8051 Software
Development Package, the DCS100 BITBUS Toolbox Host Software Utilities, the DSC11 0 Bitware for
ICETM Support, and the DCS120 Programmer's Support Package. The 8051 Software Development
Package provides the RL 51 Linker and Relocator
Program, and ASM 51. PLIM 51 is also available.
Hardware tools consist of the In-Circuit Emulator
(ICE 5100/044).

DEVELOPMENT ENVIRONMENT

Table 3. iDCX 51 Calls

Call Name

Description

TASK MANAGEMENT CALLS

RQ$CREATE$T ASK

Create and schedule a new task.

RQ$DELETE$T ASK

Delete specified task from system.

RQ$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

INTERTASK COMMUNICATION CALLS

RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCATE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.

MEMORY MANAGEMENT CALLS

RQ$GET$MEM
RQ$RELEASE$MEM

I Get available SMP memory.
Release SMP memory.

INTERRUPT MANAGEMENT CALLS

RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RQ$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS

RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

18-50

inter

iSBXTM 344A BOARD
Table 4. RAC Services
Action Taken by Task 0

RACService
RESET_STATION

Perform a software reset.
Perform an RQ$CREATE$TASK system call.

TASK

CREATE

DELETE_TASK
GET

FUNCTION

RAC

PROJECT

Perform an RQ$DELETE$TASK system call.

Return values from specified 110 ports.

READ_I/O
I/O

WRITE

Perform an RQ$GET$FUNCTION$IDS call.
Suspend or resume RAC services.
Write to the specified I/O ports.

UPDATE_I/O

Update the specified I/O ports.

UPLOAD_MEMORY

Return the values in specified memory area.

DOWNLOAD

Write values to specified memory area.

MEMORY

OR_1I0

OR values into specified I/O ports.

I/O

AND values into specified I/O ports.

XOR_1I0

XOR values into specified I/O ports.

AND

READ_INTERNAL

Read values at specified internal RAM areas.

WRITE

Write values to specified internal RAM areas.

INTERNAL

NODE_INFO

Return device related information.

OFFLINE

Set node offline.

UPLOAD

CODE

DOWNLOAD_CODE

Read values from code memory space.
Write values to specified EEPROM memory.

NOTE:
Internal memory locations are included in the 192 bytes of data RAM provided in the microcontroller. External memory refers
to memory outside the microcontroller - the 28·pin sockets of the iSSX 344A module and the iRCS 44/10A board. Each
RAC Access Function may refer to multiple I/O or memory locations in a single command.

SPECIFICATIONS

Address Range

CPU
8044 BITBUS Enhanced Microcontroller (BEM)

Word Size
Instruction: 8 bits
Data: 8 bits

Processor Clock 12 MHz
Instruction Execution Times
1 fJ-s 60% instructions
2 fJ-s 40% instructions
4 fJ-s Multiply & Divide

Memory CapacityI Addressing
iDCM Controller: Up to 64 Kbytes code

Option A

Option B

External
Data
Memory

0000H-7FFFH

External
Code
Memory

1000H-OFFFFH

8000H~OFEFFH

Internal
Code
Memory

OOOOH-OFFFH

Option A: Supports maximum amount of external EPROM code memo
ory.
Option B: Supports downloading code into external RAM or EEPROM
memory.

Terminations
Sockets provided on board for % Watt 5% Carbon
type resistors. Resistor value to match characteristic
impedance of cable as closely as possible-120n or
greater.

Message Size
54 bytes max

18-51

iSBXTM 344A BOARD

8044 BITBUSTM Enhanced Microcontroller
(8044 + Firmware) 1/0 Addressing as Viewed from the 8044
Address

Read

Write

Oata

Function

FFOOH

Command

FF01H

""
""

Status
-RFNF*
-TFNE*
-TCMO*

B3H
B2H
92H

LEO #1

90H

LEO #2

91H

ROYINE*

B4H

Node Address

FFFFH

Configuration

FFFEH

""
""
""
""
""
""

""
""

Bit

Comments

Write sets command to
extension - Read clears
command from extension

""""
""
""

Also INT1 Input
Also INTO Input

""
""

iSBXTM 344A MULTIMODULETM Board 1/0 Addressing as Viewed from the
iSBXTM 344A MULTIMODULETM Board
Register Function

Address

Comments

Base'

Read/Write

Command

Base'.+ 1

Write sets command from
extension
Read clears command to
extensipn

Status

Base' + 2

Read Only

Oata

InterruptlDMA Lines

Status Register Interface

Signal

Location

Interface
Option

RINT
TINT
RCMI
RORQ
TORQ

MORQ/MINTO
MINT1
OPTO
MORQ/MINTO
MINT1

INT
INT
INTor OMA
OMA
OMA

Status Register Interface
7 6 5 4 3 2
0

I I f I fl.-'_'__' ~_ ~~~~**

16-52

RCMO*
280247-5

intJ

iSBXTM 344A BOARD

The iSBX 344A MULTIMODULE board presents one
standard load to the BITBUS bus

Connector Options
10 Pin Plug

Flat Cable: 3M 3473-6010, TB Ansley 609-1001M,
or equal
Discrete Wire: BERG 65846-007, ITT Cannon 1217326-105, or equal

Power Requirements
0.9A at + 5V ± 5% (does not include power to the
memory devices)

Physical Characteristics
Pinout
Pin

Signal

1
2
3
4
5
6
7
8
9
10

+12V
+12V
GND
GND
DATA'
DATA
DCLK*/RTS'
DCLK/RTS
RGND
RGND

Double-wide iSBXTM MUL TIMODULETM Form Factor
Dimensions

Height: 10.16 mm (0.4 in) maximum component
height
Width: 63.5 mm (2.50 in)
Length: 190.5 mm (7.50 in)
Weight: 113 gm (4 ounces)

Environmental Characteristics
Operating Temperature: O°C to 55'C at 200 Linear
Feet/Minute Air Velocity
Humidity:
90% non-condensing

Electrical Characteristics
Interfaces
iSBXTM I/O Expansion Bus: supports the standard
I/O Expansion Bus Specification with compliance
level IEEE 959.

Reference Manual (NOT Supplied)
148099- iSBX 344A Intelligent .BITBUS Interface
Board User's Guide

Memory Sites: Both code and data sites support the
standard 28-pin JEDEC site.

Ordering Information

BITBUSTM Interconnect: Fully supported synchronous mode at 2.4 Mbits/sec and self clocked mode
for 375 kbits/sec and 62.5 kbits/sec

Part Number Description
iSBX 344A
BITBUS Intelligent MULTIMODULE
board

18-53

iPCX 344A
BITBUSTM IBM* PC INTERFACE BOARD

•
•
•

High Performance 12 MHz 8044 SingleChip Microcontroller
Integral Firmware Optimized for RealTime Control Applications Using the
BITBUSTM Interconnect
Fully Supports Intel's Complete Remote
Control Board Produ.ct Line (iRCB)

•
•
•
•

Compatible with Intel's DOS-Based
Development Tools
External Memory Sites for User's
Control Programs
IBM PC System Form Factor Board
Power Up Diagnostics

The iPCX 344A BITBUS IBM PC INTERFACE board provides the BITBUS gateway to IBM's family of Personal
and Industrial Computers. Based on Intel's highly integrated 8044 (an 8051 microcontroller and an SDLC
controller on one chip) the iPCX 344A IBM PC INTERFACE board extends the real-time control capability of
the IBM PC via the BITBUS interconnect. The PC system performs the human interface functions for the
BITBUS interconnect. Like all members of Intel's Distributed Control Modules (iDCM) family, the iPCX 344A
IBM PC INTERFACE board includes features that make it well suited for Industrial Control applications such
as: data acquisition and monitoring, process control, machine control, and statistical process control (SPC).

280414-1

'IBM is a trademark of International Business Machines.

18-54

March 1988
Order Number: 280414-002

inter

iPCX344A

ISBXTW 311
ANALOG BOARD
INDUSTRIAL
...... ~ .......
CHASSIS
_....
I
.......

........
...I....

I
I

........

.. .... ..

...~

.... ..... .......... ! .. ., .. .. .. ...."

....

IRCB 44/1 OA
DIGITAL BOARD

.. .... :
. . .. .
.. .
.. ..

..~

280414-2

Figure 1.IDCM Operating Environment

OPERATING ENVIRONMENT

ARCHITECTURE

Intel's Distributed Control Modules (iDCM) product
family provides the building blocks to implement
real·time distributed I/O control applications. All of
the iDCM family utilizes the BITBUS interconnect to
provide standard high speed serial communication
between microcontrollers. The iDCM hardware prod·
ucts: including the iPCX 344A board, iSBXTM 344A
MULTIMODULETM board and all iRCB BITBUS Remote Controller Boards communicate in an iDCM
system via the BITBUS interconnect as shown in
Figure 1.

Figure 2 illustrates the major functional blocks of
the iPCX 344A IBM PC INTERFACE board: 8044
BITBUS ENHANCED MICROCONTROLLER, memo
ory, BITBUS interconnect, PC System Interface, and
initialization/ diagnostic logic.

As a member of the iDCM Product line, the iPCX
344A IBM PC INTERFACE board fully supports the
BITBUS microcontroller interconnect. Typically, the
iPCX 344A IBM PC System INTERFACE board will
be part of a node (master or slave) on the BITBUS
interconnect. The iPCX 344A board plugs into the
PC add-in slot. .
The iPCX 344A IBM PC INTERFACE board is the
hardware interface between the PC system and the
BITBUS environment. With this interface the user
can utilize the human interface and application soft"
ware of the PC and extend the I/O range of the PC
to include real·time distributed control.

Memory, mode of operation, and bus transmission
rate options are easily selected by the user, thereby
decreasing inventory levels and associated costs.

8044 BITBUSTM Enhanced
Microcontroller (BEM)
The source of the iPCX 344A IBM PC INTERFACE
board's controlling and communication capability is
Intel's highly integrated 12 MHz 8044 microcontroller. The 8044 consists of the advanced 8-bit, 8051
microcontroller and a SDLC controller called the Se·
rial Interface Unit (SIU). This dual processor architecture provides complex control and high speed
communications in a cost-effective, single chip implementation.

18-55

intJ

iPCX344A

Two 28-pin JEOEC sites comprise the iPCX 344A
board's external memory. One site is dedicated to
data; the other to code. Table 1 lists the supported
memory devices for each site. Intel's 2764 and
27128 are examples. The user can choose one of
two memory configurations and specify different
memory sizes by configuring the correct jumpers.
This configurability provides the user with access to
the code site for program download or upload and
ensures that an existing system is easily expanded.

PC BUS

Table 1. Supported Memory Devices
OFF CHIP
MEMORY

INITIAUZATION I
• DIAGNOSTIC
LOGIC

28 PIN

DATA SITE
28 PIN
CODE SITE

8044

BITBUS" ENCHANCED
MICROCONTROLLER

Device

Data Site

Code Site

4Kx8-64Kx8
EPROM/ROM

Yes

2Kx8-32Kx8
SRAM

Yes

2K x 8-16K x 8
NVRAM and E2PROM

Yes

BITBUSTM Microcontroller
Interconnect
The iPCX 344A IBM PC INTERFACE board fully supports the BITBUS microcontroller interconnect. The
BITBUS interconnect is a serial bus optimized for
control applications and supports both synchronous
and self-clocked modes of operation.· Each mode of
operation and the different transmission rates ·are
jumper selectable dependent on application requirements.

280414-3

Figure 2. IPCX 344A Block Diagram
Another essential part of the 8044 controller is the
integral firmware residing on-chip to implement the
BITBUS interface. In the operating environment of
the iPCX 344A board, the 8044's SIU acts as an
SOLC controller offloading the on-chip 8051 microcontroller of communication tasks; freeing the 8051
to concentrate on real-time control.
The 8044 BEM (8044 microcontroller and on-chip
firmware) provides in one package a simple user interface, and high performance communications and
control capabilities to efficiently and economically
build a complex control system.

Table 2 shows different combinations of mode of
operation, transmission rate, and distance. The
SOLC protocol, BITBUS message format, and compatibility with Intel's other software and hardware
, products comprise the remainder of this established
architecture. These features contribute to BITBUS
reliability and usefulness as a microcontroller interconnect.
The BITBUS connection consists of one or two differential user selected pair(s) of wires. The BITBUS
interface on the iPCX 344A board consfsts of a halfduplex RS485 transceiver and an optional clock
source 'for the synchronous mode of operation.

Memory
The iPCX 344A IBM PC System INTERFACE board
contains both internal and external memory. Internal
memory is located in the on-chip memory of the
8044 BEM. The BITBUS firmware includes Intel's
powerful iOCX 51, real-time, multitasking, executive.
Eight bytes of bit-addressable internal memory are
reserved for the user. Additional space is reserved
for user programs and data in the board's external
memory.

PC System Interface
The iPCX 344A board will operate in any IBM PC XT,
PC AT, or compatible system that meets the following reqUirements:
-

18-56

An IBM PC, PC XT with an oscillator running at
4.77 MHz (processor running at 4.77 MHz also)

iPCX 344A

An IBM PC AT with an oscillator running at 12 or
16 MHz (processor running at 6 or 8 MHz)
An available I/O channel with addresses that are
not used by any other boards in the system in the
range of 200H to 3FFH on even addresses
At least one available system interrupt (required
ONLY if running the iPCX 344A board in interrupt
mode; user selectable from PC Interrupts 2, 3, 4,
5, 6, or 7)

All IBM guidelines have been followed to ensure
complete IBM PC system compatibility.

Initialization and Diagnostic Logic
Like the other members of Intel's Distributed Control
Modules (iDCM) product line, the iPCX 344A
BITBUS IBM PC INTERFACE board includes many
features making it well suited for industrial control
applications. Power on diagnostics simplify system
startup considerably by immediately indicating an
8044 BEM or external bus failure.

The iDCX 51 Executive is an event-driven software
manager that can respond to the needs of multiple
tasks. This real-time multitasking executive provides:
task management, timing, interrupt handling, and
message passing services. Table 3 shows the
iDCX 51 operating system calls. The executive supports up to seven user tasks at each node while
making BITBUS operations transparent.
Remote Access and Control (RAG) is a special purpose task that allows the user to transfer commands
and program variables to and from BITBUS controllers to obtain the status of I/O or data line(s), or
reverse the state of an I/O line or read and Write
memory, etc. No user code need be written to use
this function. See Table 4 for a complete listing of
RAC services.
The services provided by the iPCX 344A board's integral firmware simplify the development and implementation of complex real-time control systems.

DEVELOPMENT ENVIRONMENT
Intel provides a variety of development environments for BITBUS applications. Intel's Development
Systems and OEM Systems Handbooks provide details on the following development tools.
- BITBUS TOOLBOX-BITBUS Monitor and Interface Handlers
- ASM/PLM 51-Low and High level languages
for application code generation on 8044

INTEGRAL FIRMWARE

The iPCX 344A BITBUS PC-BUS INTERFACE board
contains resident firmware located in the 8044
BITBUS ENHANCED MICROCONTROLLER. This
on-chip firmware consists of: a pre-configured
iDCX 51 Executive for real-time, multitasking control;
DCM 44, a Remote Access and Control (RAG) program that enables BITBUS communication and control of I/O points on the BITBUS interconnect; and
power up diagnostics.
Table 2. BITBUSTM Microcontroller Interconnect Modes of Operation
Speed
Kb/s

Maximum Distance
Between Repeaters
M/ft

Maximum # Nodes
Per Segment'

Maximum # Repeaters
Between a Master and
Any Slave

Synchronous

500-2400

30/100

Self Clocked

375
62.5

300/1000
1200/4000

28
28

2
10

'Segment: Distance between master and repeater or repeater and repeater.
Synchronous mode requires user supplied crystal.

Table 3. iDCX 51 Systems Calls
Call Name

Description

TASK MANAGEMENT CALLS
RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

Delete specified task from system.

RQ$GET$FUNCTION IDS

Obtain the function IDs of tasks currently in the system.

INTERTASK COMMUNICATION CALLS
RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCATE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.
18-57

inter

iPCX344A

Table 3.iDCX 51 Systems Calls (Continued)
Call Name

Description

MEMORY MANAGEMENT CALLS
RQ$GET$MEM

Get available SMP memory.

RQ$RELEASE$MEM

Release SMP memory.

INTERRUPT MANAGEMENT CALLS
RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RE$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS
RQ$SET$INTERVAL

.Establish a time interval.

RQ$WAIT

Wait for an interval event.

Table 4. RAC Services
RACService
RESET_STATION

Action Taken by Task 0
Perform a software reset.

CREATE_TASK

Perform an RQ$CREATE$TASK system call.

DELETE_TASK

Perform an RQ$DELETE$TASK system call.

GET_FUNCTION_ID

Perform an RQ$GET$FUNCTION$IDS call.

RAC_PROJECT

Suspend or resume RAC services.

READ_I/O

Return values from specified I/O ports.

WRITE_I/O

Write to the specified 110 ports.

UPDATE_1I0

Update the specified I/O ports.

UPLOAD_MEMORY

Return the values in specified memory .area.

DOWNLOAD_MEMORY

Write values to specified memory area.

OR_I/O

OR values into specified I/O ports.

AND_I/O

AND values into specified I/O ports.

XOR_I/O

XOR values into specified I/O ports.

READ_INTERNAL

Read values at specified internal RAM areas.

WRITE_INTERNAL

Write values to specified internal RAM areas.

NODE_INFO

Return device related information.

OFFLINE

Set node offline.

UPLOAD_CODE

Read values from code memory space.

DOWNLOAD_CODE

Write values to specified EEPROM memory.

SPECIFICATIONS
CPU

Processor Clock
12.0 MHz

8044 BITBUS Enhanced Microcontrolier (BEM)

Instruction Execution Time

Word Size

1 fJ-s 60% instructions
2 fJ-s 40% instructions
4 fJ-s Multiply and Divide

Instruction-8 bits
Data-8 bits

18-58

iPCX344A

Physical Characteristics

Memory Capacity Addressing
iDCM Controller: Up to 64 Kbytes code.
Device

EPROM/ROM
4Kx8-64K x8
SRAM
2K x 8-32Kx 8
NVRAM and E2PROM
2Kx8-16Kx8

IBM PC ADD-ON FORMAT
Height: 3.98 in.

Data

Code

Yes

Interfaces

Yes

BITBUS Interconnect: Fully supports synchronous
mode at 500 Kbps to 2.4 Mbs
and self-clocked modes at
375 Kbs or 62.5 Kbs

Depth: 6 in.

External 1/0 Space
OFFOOH-OFFFFH
space)

(mapped

into

data

Note: On-board ALE clock
supports 1 Mbps synchronous operation. All other synchronous mode speeds require user-supplied 2.0 MHz9.6 MHz crystal.
Two unidirectional, one-bytedeep, nine-bit FIFO buffers
(ninth bit distinguishes between data and command)

memory

Termination
Minimum 120.0 each end of BITBUS interconnect
with user supplied resistors

PC System:

A dd ress Ranges
Option A
External Data 0000H-7FFFH
Memory Site

Power Requirements

Option B
0000H-7FFFH

0.9A at

External Code 1000H-OFFFFH 8000H-OFEFFH
Memory Site (OOOOH-OFFFFH
If EA Active)
Internal Code
Memory

OOOOH-OFFFH

Option A: Supports maximum amount of external EPROM code memo
ory.
.
Option B: Supports downloading code into external RAM or EEPROM
memory.

up to 54 bytes

± 5% (memory not included)

Environmental Requirements

OOOOH-OFFFH

Message Size:

+ 5V

Operating Temperature: 16°C to 32°C at no air flow
O°C to 55°C at 200 Linear
Feet/Minute air velocity
. Operating Humidity:
90% Noncondensing

+ 70·C

Storage Temperature:

-40°C to

Storage Humidity:

95% Noncondensing

REFERENCE MANUAL
149235-001- iPCX 344A BITBUS IBM PC System
Interface Board User's Guide

Connectors
Standard 9-pin-D Subminiature socket

ORDERING INFORMATION
Part Number

Description

iPCX344A

BITBUS IBM PC System
INTERFACE Board

18-59

iRCB 44/10A
BITBUSTM DIGITAL 1/0 REMOTE CONTROLLER BOARD

•
•
•
•
•

High Performance 12 MHz 8044
Controller
Integral Firmware: iDCX Executive,
Optimized for Real-Time Control
Full BITBUSTM Support
Standard Industrial Packaging:
Eurocard, DIN Connector

•
•
•
•

I/O Expansion with 8-Bit iSBXTM
Connector
Programmable Control/Monitoring
Using 24 Digital I/O Lines
Power Up Diagnostics
Compatible with iRCX 910 Digital Signal
Isolation and Termination Module

2 28-Pin JEDEC Memory Sites for
User's Control Functions

The iRCB 44/10A BITBUSTM Digital 1/0 Remote Controller Board is an intelligent real-time controller and a
remote I/O expansion device. Based on the highly integrated 8044 component (an 8 bit 8051 microcontroller
and an intelligent SDLC-based controller on one chip) the iRCB 44/10A board provides high performance
control capability at low cost. The iRCB 44/1 OA board can expand Intel's OEM microcomputer system capabilities to include distributed real-time control. Like all members of the iDCM family, the iRCB 44/10A board is
well suited for industrial control applications such as data acquisition and monitoring, process control, robotics,
and machine control.

280213-1

18-60

March 1988
Order Number: 280213-003

infef

IRCB 44/10A

OPERATING ENVIRONMENT

ARCHITECTURE

Intel's Distributed Control Modules (iDCM) product
family contains the building blocks to implement
real-time distributed control applications. The iDCM
family incorporates the BITBUS interconnect to provide standard high speed serial communication between microcontrollers. The iDCM hardware products, which include the iPCX 344A board, iSBX 344A
MULTIMODULETM board and the iRCB 44/10A BITBUS Remote Controller Board (and other iRCB
boards), communicate in an iDCM system via the
BITBUS interconnect as shown in Figure 1.

Figure 2 illustrates the major functional blocks of the
iRCB 44/10A board: 8044 BITBUS Enhanced Microcontroller, memory, BITBUS microcontroller interconnect, parallel liD, iSBX expansion, initialization
and diagnostic logic.

The iRCB 44/1 OA board can be used as an intelligent remote controller or an I/O expansion device.
When performing as an intelligent controller the
iRCB 44/10A board not only monitors the status of
multiple process points, but it can execute varied
user supplied control algorithms. When functioning
as an I/O expansion device, the iRCB 44/10A board
simply collects data from multiple I/O ports and
transmits this information via the BITBUS or iSBX
bus interface to the system controller for analysis or
updating purposes.
As a member of the iDCM product line, the iRCB
44/10A board fully supports the BITBUS microcontroller interconnect. Typically, the iRCB 44/10A
board would be a node in a BITBUS system. The
iRCB 44/10A board could be a master or slave
node. (The BITBUS system supports a multidrop
configuration: one master, many slaves.)

8044 BITBUSTM Enhanced
Microcontroller
The heart of the iRCB 44/10A board's controlling
and communication capability is the highly integrated 12 MHz 8044 microcontroller. The 8044 consists
of the advanced 8-bit 8051 microcontroller and a
SDLC controller called the Serial Interface Unit
(SIU). This dual processor architecture allows complex control and high speed communication functions to be realized cost effectively. The 8044's SIU
acts as a SDLC-based controller which off loads the
on-chip 8051 microcontroller of communication
tasks; freeing the 8051 to concentrate on real-time
control.
The 8044 BEM microcontroller also includes, in firmware, a set of procedures known as Remote Access
and Control (RAG), a preconfigured version of the
DCX 51 Executive, communications software, and
power-up diagnostics.
The BEM (8044 microcontroller and on-chip firmware) provides, in one package, a simple user interface, and high performance communications and
control capabilities to efficiently and economically
build a complex control system.

280213-2

Figure 1. IDeM Operating Environment

18-61

inter

iReB 44/10A

ensures expansion of an existing system is easily
accommodated.

Memory
The iRGB 44/10A board memory consists of two
sections: internal and external. Internal memory is
located in the on-chip memory of the BEM. The
iDGX51 Executive and the remaining BEM firmware
ration this resource. However, eight bytes of bit addressable internal memory are reserved for the user.
Ample space is reserved for user programs and data
in the iRGB 44/10A board external memory.
Two 28 pin JEDEG sites comprise the iRGB 44/10A
board external memory. One site has been dedicated for data, the other for code. Table 1 lists the supported memory devices for each site. Intel's 2764,
and 27128 are examples. The user may choose one
of two memory configurations and specify different
memory sizes by placing the proper jumpers at system initialization. The most flexible configuration option provides the user with access to the code site
for program download or upload. This feature

Table 1. Supported Memory Devices
Device

Data Site

Code Site

4K x 8-64K x 8
EPROM/ROM·

YES

x 8-32K x 8

YES

YES·

SRAM.
2K x 8-16K x 8
NVRAMand E2PROM

BITBUSTM Microcontroller
Interconnect
The iRGB 44/10A board serial interface fully supports the BITBUS microcontrolle(interconnect. The
BITBUS interconnect is a serial bus optimized for

INmALIZATION
AND
DIAGNOSTIC
LOGIC
28 PIN CODE SITE
24 LINES
PARALLEL

110

BITBUS~

REPEATERS
(OPTIONAL)

-===- -=-===---

BITBusm INTERCONNECT

.. ,.....=>. :c:::::::::-4

REPEATED BITBUS"
INTERCONNECT

280213-3

Figure 2. iRCBTM 44/10A Block Diagram
18-62

inter

iReB 44/10A

control applications. The bus supports both synchronous and self-clocked modes of operation. These
modes of operation are selectable dependent on application requirements as are the transmission
speeds. Table 2 shows the different combinations of
modes of operation, transmission speeds, and distances. The SDLC-based protocol, BITBUS message format, and compatibility with Intel's other software and hardware products comprise the remainder of the BITBUS architecture. These features contribute to BITBUS system reliability and usefulness
as a microcontroller interconnect.
The BITBUS connection consists of one or two differential pair(s) of wires. The serial (BITBUS) interface of the iRCB 44/10A board consists of: a halfduplex RS 485 transceiver, an optional BITBUS repeater and an optional clock source for the synchronous mode of operation.

Digital Parallel 1/0
In order to provide an optimal parallel 1/0 interface
for control applications, the iRCB 44/10A board supports 24 software programmable parallel 110 lines.
This feature supplies the flexibility and simplicity required for control and data acquisition systems. Sixteen of these lines are fully programmable as inputs
or outputs, with loopback, on a bit by bit basis so
that bit set, reset, and toggle operations are streamlined. The remaining eight lines are dedicated as inputs. Figure 3 depicts the general 1/0 port structure.
The parallel 1/0 lines can be manipulated by using
the Remote Access and Control (RAG) function (in
BEM firmware) from a supervisory node or locally by
a user program. The user program can also access

the RAC function or directly operate the 1/0 lines.
Input, output, mixed- input and output, and bit operations are possible simply by reading or writing a
particular port.

iSBXTM Expansion
One iSBX I/O expansion connector is provided on
the iRCB 44/1 OA board. This connector can be used
to extend the 110 capability of the board. In addition
to specialized and custom designed iSBX boards, a
full line of compatible high speed, 8-bit expansion
MULTIMODULE boards, both single and double
wide, are available from Intel. The only incompatible
modules are those that require the MWAIT' signal or
DMA operation. A few of Intel's iRCB 44/10A board
compatible iSBX MULTIMODULE boards include:
parallel 1/0, serial 1/0, BITBUS expansion, IEEE
488 GPIB, analog input and analog output.
With the iSBX 344A BITBUS Controller MULTIMODULE board and user supplied software, the iRCB
44/10A board can act as an intelligent BITBUS repeater faCilitating the transition between two BITBUS segments operating at different speeds.

Initialization and Diagnostic Logic
Like the other members of Intel's Distributed Control
Modules (iDCM) product line, the iRCB 44/1 OA
board includes many features which make it well
suited for industrial control applications. Power up
diagnostics is just one of these features. Diagnostics
simplify system startup considerably, by immediately
indicating an iDCM controller or external bus failure.
The LEDs used for power up diagnostics are

Table 2. BITBUSTM Microcontroller Interconnect Modes of Operation
Speed
Kb/s

Maximum Distance
Between Repeaters
M/ft

Maximum #Nodes
Per Segment'

Maximum # Repeaters
Between A Master And
Any Slave

Synchronous

500-2400

30/100

Self Clocked

375
62.5

300/1000
1200/4000

28
28

2
10

'Segment: Distance between master and repeater or repeater and repeater. Synchronous mode requires user supplied crystal.

18-63

inter

iReB 44/10A

available for user diagnostics after power up as well
to further contribute to reliable operation of the system.
Initial iRCB 44/10A board parameters are set by positioning jumpers. The jumpers determine the
BITBUS mode of operation: synchronous, self
clocked, transmission speed, and address of the
iRGB 44/10A board in the BITBUS system. This
minimizes the number of spare boards to be stocked
for multiple nodes, decreasing stocking inventory
and cost.

INTEGRAL FIRMWARE
The iRCB 44/10A board contains resident firmware
located in the 8044 BEM. The on-chip firmware consists of: a pre-configured iDCX 51 Executive for user
program development; a Remote Access and Controller (RAG) function that enables user communication and control of different microcontrollers and I/O
points; a communications gateway to connect the
BITBUS interconnect, iSBX bus, iPCX bus and iDCX
51 tasks; and power up diagnostics.

Table 3.IDCX 51 Executive Calls
Call Name

Description

TASK MANAGEMENT CALLS
RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

Delete specified task from system.

RQ$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

INTERTASK COMMUNICATION CALLS
RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCATE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.

MEMORY MANAGEMENT CALLS
RQ$GET$MEM

Get available SMP memory.

RQ$RELEASE$MEM

Release SMP memory.

INTERRUPT MANAGEMENT CALLS
RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RQ$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS
RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

+5V

RESET-

OPEN
COLLECTOR

DATA
BUS - -. . .--iD
BIT

Qt-----j

:>0>---....-

__- - 110 PORT PIN

WR- - - - t - - - - - '

RD----j---.,

280213-4

Figure 3_ 1/0 Port Structure

. 18-64

iReB 44/10A

BUS controllers, obtain the status of a remote I/O
line(s), or reverse the state of a remote I/O line.
Table 4 provides a complete listing of the RAC services. No user code need be written to use this function. Power up tests provide a quick diagnostic service.
The services provided by the iRCB 44/10A board
integral firmware simplify the development and implementation of complex real-time control application systems. All iDCM hardware products contain
integral firmware thus supplying the user with a total
system solution.

Table 4. RAC Services
RACService

Action Taken by Task 0

RESET_STATION

Perform a software reset.

CREATLTASK

Perform an RQ$CREATE$TASK system call.

DELETE_TASK

Perform an RQ$DELETE$TASK system call.

GET_FUNCTION
RAC

PROTECT

READ_IO
WRITE

Return values from specified I/O ports.

Write to the specified I/O ports.

UPDATLIO
UPLOAD

Perform an RQ$GET$FUNCTION$IDS call.
Suspend or resume RAC services.

Update the specified I/O ports.

MEMORY

DOWNLOAD

MEMORY

OFLI/O

Return the values in specified memory area.
Write values to specified memory area.
OR values into specified I/O ports.

I/O

AND values into specified I/O ports.

XOR_I/O

XOR values into specified I/O ports.

AND

READ_INTERNAL

Read values at specified internal RAM areas.

WRITE_INTERNAL

Write values at specified internal RAM areas.

NODLINFO

Return device related information.

OFFLINE

Set node offline.

UPLOAD_CODE

Read values from code memory space.
Write values to specified EEPROM memory.

DOWNLOAD_CODE

18-65

infef

iReB 44/10A

mounting for one RCB 44/10A, with connectors for
power, the BITBUS interconnect signals, and 24 Industry Standard I/O isolation and signal conditioning
modules. These modules, available from a number
of vendors worldwide, typically provide greater than
1500V isolation and support signal conditioning in a
number of voltages including 5-60 VDC, 120 and
240 VAC.

INDUSTRIAL PACKAGING
The iRCB 44/10A form factor is a single high, 220
mm deep Eurocard and supports most stahdard industrial packaging schemes as well as Intel's RCX
910 Digital Signal Conditioning, Isolation ~nd Termination Module (see below). The Eurocard form factor specifies reliable DIN connectors. A standard 64
pin connector is included on the iRCB 44/10A
board.

SPECIFICATIONS

Physical Characteristics

Word Size

Single high, 220 mm deep Eurocard Form Factor

Instruction: 8 bits
Data:
8 bits

Dimensions
Width: 13.77 mm (0.542 in) maximum component
height
Height: 100 mm (3.93 in.)

Processor Clock 12 MHz

Depth: 220 mm (8.65 in.)
Weight: 169 gm (6 ounces)

Instruction Execution Times
1 ""sec 60% instructions
2 J.tsec 40% instructions
4 J.tsec Multiply & Divide

DIGITAL SIGNAL CONDITIONING,
ISOLATION, AND TERMINATION
The RCB 44/10A is fully compatible with the RCX
910 Digital Signal Conditioning, Isolation and Termination Panel. The RCX 910 panel provides integral

Memory Capacity/Addressing
iDCM Controller: Up to 64 Kbytes code

DEVELOPMENT ENVIRONMENT
Intel provides a complete development environment for the iRCB 44/10A board.
BITBUSTM Development Environments
BITBUSTM TOOLS

ICETM

NODE
CODE

EPROMPROG.
(/)

<'(f)

DCS 100
TOOLBOX
Q)

"0
::2;
In
In

[ij

d5
(J

0..

Series II
III
X
IV
iPDS A
A
A
IRMXS%" X
X
X
X
8" X
X
X
X
XENIXS%" X
X
B
8" X
X
B
X
DOS X
X
X
NOTES:
A. iPDS uses Release 1 Toolbox.
B. Supports operation with XENIX.
C. Down-revision version.
D. Available for iRMX® 86.

iii
xW

(f)

15
=>

...,
0

X
X
X
X
X

0
C\J

-- co

iii

(f)

(/)

::2;

(f)

X
X
X
X
X'

X
X
X
X
X

C
X
X
C
D
D

XENIX disks not required.

18-66

iii

::2;
iii
....
....J
....J

0..

0::

C
X
X
C
D
D

.;.;-

0
....
0
0

iii
W
9
X
X

<.';-0..
.,...~9:
0 .... "0

~ff~
;:§g;.!!1
~:c.g

~.~ ~

:;
"0
0

E
<..,

.;-(/)

E~~

"coo..

(f)LJ..'-

00.."0

9:;2~

X
X
X
X

iRes 44/10A

Address Ranges
Memory

Interrupt Sources
Option A

Option B

Two external: iSSX I/O Expansion bus sources or
other sources.
SITSUS Microcontroller Interconnect.

External -Data 0000H-7FFFH 0000H-7FFFH
-Code 1000H-OFFFFH 8000H-OFEFFH
Internal

OOOOH-OFFFH

NOTES:

Option A: Supports maximum amount of external EPROM
code memory.
Option B: Supports downloading code into RAM or
EEPROM memory.

8044 BITBUSTM Enhanced Mlcrocontroller 1/0 Addressing
Address

Read

Write

PORTA

Function

FFCOH

",.

PORTS

FFC1H

",.

PORTC

FFC2H

",.

MCSO

FF80H-FF87H
FFOO,FF01

",.

MSC1

FF88H-FF8F

",.

LED #1

90H

",.

LED #2

91H

",.

RDY/NE*

S4H

",.

NODE ADDRESS

FFFFH

",.

CONFIGURATION

FFFEH

",.

92H

",.

OPT1

93H

",.

INTO

S2H

",.

INT1

S3H

",.

OPTO

Bit

",.

PARALLEL I/O
Number: 2 8-Sit Si-directional Ports
1 8-Sit Input Port
Table 5. Parallel 1/0 Electrical Specification
Parameter

Condition

VOL
VOH
VIH
VIL
IlL
IIH
II

IOL =16 mA
IOH= -2 mA

Min
2.4
2.0
-1.0

VIL =0.5V
VIH = logic high
VIH=7V

18-67

Max

Units

0.5

V
V
V
V
mA
mA
mA

7.0
0.8
6.0
0.0
-2.2

inter

iRCB44/10A

Terminations

Memory Sites: Both code and data sites support the
electrical Universal Memory Site specification

Sockets provided on board for % Watt 5% Carbon
type resistors. Resistor value to match characteristic
impedance of cable as closely as possible-120n or
greater.

BITBUSTM Interconnect: The iRCB 44/10A Remote
Controller Board supports the BITBUS Specification
as follows:

Repeaters

Fully supported synchronous mode at 2.4
Mbitslsecond and self clocked mode for 375 kbitsl
second and 62.5 kbitslsecond

Sockets provided on board: Devices 75174 and
75175

The iRCB 44/10A Remote Controller Board presents one standard load to the BITBUS without repeaters, with repeaters two standard loads

Connector Options
Message length up to 54 bytes supported
10 PIN PLUG

RAC Function support as shown in Table 4

Flat Cable: 3M 3473-6010, TB Ansley 609-1001M,
or equal

Parallel 110: See the Table 5 for Electrical Specifications of the interface.

Discrete Wire: BERG 65846-007, ITT Cannon 1217326-105, or equal

Power Requirements
0.9A at +5V ±5% iRCB 44/10 board only (power
to memory, repeater, or iSBX board NOT included)

DIN CONNECTOR PLUG

Flat Cable: GW Elco 00-8259-096-84-124, Robinson
Nugent RNE-IDC64C-TG30, or equal

Environmental Characteristics

Discrete Wire: ITT Cannon G06 M96 P3 BDBL-004
GW Elco 60 8257 3017, or equal

Operating Temperature: O°C to 55°C at 200 Linear
Feet/Minute Air Velocity

10 Pin Repeater Connector Pin Out
Pin

Signal

1
2
3
4
5
6
7
8
9
10

+12V
+12V
GND
GND
DATA'
DATA
DCLK*/RTS*
DCLK/RTS
RGND
RGND

Humidity:

90% non-condensing

Reference Manual (NOT Supplied)
iRCB 44/10 Digital liD Remote 148100-001 Controller Board User's Guide

Ordering Information
Part Number

Description

iRCB 44/10A

BITBUS Digital 110 Remote
Controller Board

Electrical Characteristics
Interfaces
iSBX 110 expansion bus: supports the standard
110 Expansion Bus Specification with compliance
level D8/8F

18-68

iRCB 44/20A
ANALOG 110 CONTROLLER
Distributed Intelligence via BITUSTM
• Serial
Bus
8044 8-bit Microcontroller at 12 MHz
• 12-bit Analog Resolution
• Up To 20 KHz Aquisition Rate (50 ms)
•
Programmable Gain: 1, 10,
• Software
100, 500
• Two 28-pin JEDEC Memory Sites

16 Single-ended or 8 Differential Input
• Channels
Channels
• 2±Outputs
Range or 4-20 mA Current Loop
• 1/010VExpandable
via iSBXTM Connector
• Compact Single-Eurocard
• Low Power Consumption Packaging
• Compatible with iRCX 920 Analog
• Signal Conditioning, Isolation and
Termination Panel

The iRCS 44/20A is a fully programmable analog lID subsystem on a single-Eurocard form-factor board. The
resident 8044 microcontroller operating at 12 MHz provides a means of executing data aquisition and control
routines remote from the. host computer. Real-time capability is made possible by the iDCX 51 Distributed
Control Executive, resident in the 8044 microcontroller. Distribution of real-time control is implemented by the
SITSUS Serial Sus protocol, which is also managed integrally by the 8044.
Offering high performance, low-cost, and improved system bandwidth via distributed intelligence, the iRCS
44/20A Analog I/O Controller is ideal for data acquisition and control in both laboratory and industrial environments.

280721-1

MULTIMODULETM is a trademark of Intel Corporation.
IBM@ PC is a registered trademark of International Business Machines Corporation.

18-69.

November 1988
Order Number: 280721-002

inter

iRCB44/20A

APPLICATION ENVIRONMENT

FUNCTIONAL ·DESCRIPTION

Intel's Distributed Control Modules (iDCM) product
family contains the building blocks to implement
real-time distributed control applications. The iDCM
family incorporates the BITBUS interconnect to provide standard high-speed serial communication between microcontrollers. The iRCB 44/20A may communicate with other nodes in a. distributed system
via the BITBUS interconnect as shown in Figure 1.
Other nodes in the system may be the iSBX 344A
BITBUS Controller MULTIMODULETM, the iPCX
344A BITBUS IBM@ PC Interface, the iRCB 44/10A
BITBUS Digital 1/0 Controller Board, or other BITBUS compatible products.

The major functional blocks of the iRCB 44/20A
board, shown in Figure 2, include the S044 microcontroller and BITBUS interconnect, local memory,·
Analog 1/0, and iSBX expansion.

The iRCB 44/20A board, can be used as an intelligent remote controller or an 110 expansion device.
When performing as an intelligent controller the
iRCB 44/20A board not only monitors the status of
multiple sensors, it can also locally execute user developed control algorithms. When functioning as an
110 expansion device the iRCB 44/20A board manages the multiple 110 ports, transmitting this information via the BITBUS bLis or iSBX interface to the
system controller for analysis or data logging purposes.
Typically, the iRCB 44/20A board will operate .as a
node in a BITBUS system. BITBUS communication
supports a multidrop configuration with one master,
and multiple subordinate nodes. The iRCB 44/20A
board may be either a master or slave node to manage a wide variety of analog input or output tasks.

Distributed Intelligence .
The heart of the iRCB 44/20A board's controlling
and communication capability is the highly integrated 8044 microcontroller which operates at 12 MHz.
The S044 contains the advanced S-bit, S051 microcontroller and a complimentary SDLC controller,
called the Serial Interface Unit (SIU). This dual processor ,architecture provides complex control and
high speed communication functions at a low cost.
Another essential part of the S044 controller is the
on-chip firmware that exercises the BITBUS interface. The S044's SIU acts as an SDLC controller, off
loading the on-chip microcontroller of communication tasks so it may concentrate on real-time control.
The S044 microcontroller simplifies the user interface, and offers high performance communications·
and control capabilities in a single component pack:
age. Many interconnected Distributed Control Modules can form a powerful platform to efficiently and
,economically administer a complete control system.

INPUT t&V,t:1OV.

O-SV,O"10V
• THERIoIOCOUPlE

• STRAIN GAUGE
• PRESURE SENSOR
ef1.OW WETER
eL.EVD. MONR'OR
OUTPure "-20mA.t5V.:I: 1OV.

0-5V'O"10V~ IRCB44/2OA

• SERVO CONTROL

• VOLTAGE SOURCE

ANALOG

CONTROLLER

280721-2

Figure 1. BITBUS Distributed Control Example

1S-70

inter

iReB 44/20A

• ±10V, ±5V, o-SV, 0-10V
.4-20mA

INPUT
• ±10V, ±SV,O-SV.O-l0V
PROGRAMMABLE GAIN
INSTRUMENTATION
AMPLIFIER

MUX
L-_ _ _ _..I

BITBUS'· BUS

280721-3

Figure 2. IRCB 44/20A Functional Diagram

BITBUSTM Microcontroller
Interconnect

Local Memory

The iRCB 44/20A board fully supports the BITBUS
microcontroller interconnect. BITBUS is a serial bus
optimized for control applications. Both synchronous
and self-clocked modes of operation are supported
as well as multiple transmission rates. Table 1
shows the different combinations of modes of operation, transmission speeds, and distances. The
SOLC protocol and BITBUS message format comprise the data-link level of the BITBUS architecture.
Use of these standards maximizes system reliability
and flexibility.
The physical connection to BITBUS uses either one
or two pairs of wires across which differential signals
travel. The iRCB 44/20A board contains a half-duplex RS 485 tranceiver and an optional clock source
for the synchronous mode of operation.

The iRCB 44/20A board contains both internal and
external local memory. Internal memory is located
within the 8044 controller and is used by the iOCX
51 Executive and the SIU. Eight bytes of bit-addressable internal memory have been reserved for the
user.
Two 28-pin JEOEC sites provide the iRCB 44/20A
board with memory that is external to the 8044. One
site has been dedicated for data, the other for application code. Table 2 lists the supported memory devices for each site. The user may select one of two
memory configurations using jumpers. One option
provides the user with access to the application
code site for uploading or downloading programs,
which allows expansion or modification of an existing system from a remote site.

Table 1, BITBUSTM Microcontroller Interconnect Modes Of Operation
Speed
Kb/S

Maximum Distance
Between Repeaters
Mlft

Maximum # Nodes
Per Segment'

Maximum # Repeaters
Between A Master And
Any Slave

Synchronous

500-2400

30/100

Self Clocked

375
62.5

300/1000
1200/4000

28
28

2
10

• Segment: Distance between master and repeater or repeater and repeater. Synchronous Mode requires user supplied
crystal.

18-71

inter

iRes 44/20A

Initialization and Diagnostic Logic

Table 2 Supported Memory Devices
Device

Data Site

Code Site

4K x8-64Kx 8
EPROM/ROM

YES

2K x 8-32Kx 8
SRAM

YES

2K x8-16Kx 8
NVRAM and E2PROM

YES

Like the other members of the Intel's Distributed
Control Modules (iDCM) product line, the iRCB
44/20A board includes many features which make it
well suited for industrial control applications. Powerup diagnostics simplify system initialization by immediately indicating a failure in either the 8044 microcontroller or external bus. On-board LEOs indicate
diagnostic status and are available after power-up
for user developed diagnostic routines.

Analog 1/0
The iRCB 44/20A has been designed to manage a
wide variety of analog functions. The jumper-selectable voltage or current ranges plus software programmable gain allows the iRCB 44/20A to acquire
data from a combination of up to 16 thermocouples,
strain gauges, pressure transducers, flow meters,
level sensors, or any devices that operate on a
4-20 mA current loop. Two analog output channels
provide, the capability to adjust system parameters
locally through servo control, voltage-driven devices,
or other actuators that respond to 4-20 mA signals.
The 8044 microcontroller on the iRCB 44/20A allows Proportional Integral/Derivative (PID) algorithms, event timing, or averaging tasks to operate
independent of the host computer or programmable
controller. By off-loading the host in this manner, the
overall system performance can be improved significantly.
The analog I/O lines can be manipulated' from a remote supervisor by communicating with the Remote
Access and Control (RAG) functions, which are included in the 8044 controller firmware. The local application program running on the iRCB 44/20A can
also access the RAC functions or directly operate
the I/O lines.

Initial iRCB 44/20A board parameters are manually
set with jumpers. These jumpers specify the mode of
operation (synchronous or self clocked), and transmission speed. The address of the iRCB 44/20A
board within the BITBUS system is also declared in
this manner. Therefore, spare board inventory is reduced, since the iRCB 44/20A may be positioned at
any node address.

INTEGRAL iDCX 51 FIRMWARE
The iRCB 44/20A board contains resident firmware
located within the 8044 controller. This on-chip firmware, known as DCM 44, consists of a pre-configured iDCX 51 Distributed Control Executive for user
program development and execution, a library of Remote Access and Control (RAG) functions for internode communications and I/O control, plus an iSBX
communications gateway, and power-up diagnostics.

iSBXTM Expansion

The iDCX 51 Executive is an event-driven software
manager that can respond to the needs of multiple
tasks. This real-time multitasking ex~cutive provides
task management and timing, interrupt handling, and
message passing services. Table 3 shows the iDCX
51 user command library. Both the executive and
the communications gateway allow for the addition
of seven user tasks at each node that are independent of BITBUS bus management operations.

One 8-bit iSBX I/O expansion connector is provided
to expand the functionality of the iRCB 44/20A
board. A full line of compatible expansion MULTIMODULE boards are available from Intel; both single- and double-wide versions are supported by the
iRCB 44/20A. Parallel I/O, serial I/O, IEEE 488,
magnetic-bubble memory, or additional analog I/O
may be added in this manner.

Remote Access and Control (RAC) functions are
special purpose tasks that allow the host system to
transfer commands and program variables to remote
BITBUS controllers and read/write to the remote
I/O lines. Table 4 provides a complete listing of the
RAC commands. No user code need be written to
use this function. Power-up tests provide a quick diagnostic service.

Also, the iSBX 344A BITBUS Controller MULTIMODULE can be used to implement another BITBUS
hierarchy with the iRCB 44/20A functioning as the
master. With user supplied software, this product
combination 'can operate as an intelligent BITBUS
repeater, facilitating the transmission between two
BITBUS segments operating at different speeds.

The DCM 44 firmware, integral to the iRCB 44/20A
board, simplifies the development and implementation of complex real-time control applications. All
iDCM hardware products contain this integral firmware, providing the user with application code portability.

18-72

inter

iReB 44/20A

Table 3.IDCX 51 Executive Calls
Call Name

Description

TASK MANAGEMENT C~LLS

RQ$CREATE$TASK

Create and schedule a new task.

RQ$DELETE$TASK

Delete specified task from system.

RQ$GET$FUNCTION$IDS

Obtain the function IDs of tasks currently in the system.

INTERTASK COMMUNICATION CALLS

RQ$ALLOCATE

Obtain a message buffer from the system buffer pool.

RQ$DEALLOCA TE

Return a message buffer to the system buffer pool.

RQ$SEND$MESSAGE

Send a message to specified task.

RQ$WAIT

Wait for a message event.

MEMORY MANAGEMENT CALLS

RQ$GET$MEM

Get available SMP memory.

RQ$RELEASE$MEM

Release SMP memory.

INTERRUPT MANAGEMENT CALLS

RQ$DISABLE$INTERRUPT

Temporarily disable an interrupt.

RQ$ENABLE$INTERRUPT

Re-enable an interrupt.

RQ$WAIT

Wait for an interrupt event.

TIMER MANAGEMENT CALLS

RQ$SET$INTERVAL

Establish a time interval.

RQ$WAIT

Wait for an interval event.

Table 4. RAC Services
Action Taken by Task 0

RACServlce

RESET_STATION

Perform a software reset.

CREATE

TASK

Perform an RQ$CREATE$TASK system call.

DELETE_TASK

Perform an RQ$DELETE$TASK system call.

GET_FUNCTION_ID

Perform an RQ$GET$FUNCTION$IDS call.

RAC_PROTECT

Suspend or resume RAC services.
Return values from specified 1/0 ports.

READ_IO
WRITE

Write to the specified 1/0 ports.

UPDATE_IO

Update the specified 1/0 ports.

UPLOAD_MEMORY

Return the values in specified memory area.

DOWNLOAD_MEMORY

Write values to specified memory area.
OR values into specified 1/0 ports.

OR_I/O

1/0

AND values into specified 1/0 ports.

XOR_I/O

XOR values into specified 1/0 ports.

AND

READ_INTERNAL

Read values at specified internal RAM areas.

WRITE_INTERNAL

Write values to specified internal RAM areas.

NODLINFO

Return device related information.

OFFLINE

Set node offline.

UPLOAD_CODE

Read values from code memory space.

DOWNLOAD

Write values to specified EEPROM memory.

CODE

NOTES:
Internal memory locations are included in the 192 by1es of data RAM provided in the microcontrolier. External memory refers
memory outside the microcontrolier-the 28-pin sockets of iRCS 44/20A board. Each RAC Access Function may refer to 1,
2, 3,4, 5 or 6 individual 1/0 or memory locations in a single command.

18-73

intJ

iReB 44/20A

INDUSTRIAL PACKAGING

Processor Clock

The iRCB 44/20A board conforms toa single-wide
(3V), 220 mm deep Eurocard form-factor. This allows the iRCB 44/20A to fit within standard industrial racks or chassis as well as Intel's RCX 920 Analog Signal Conditioning, Isolation & Termination Panel (see below). The Eurocard specification references DIN 41612 connectors, which are used on the
iRCB 44/20A board.

12 MHz

1 J.Lsec 60% instructions
2 J.Lsec 40% instructions
4 J.Lsec Multiply & Divide

ANALOG SIGNAL CONDITIONING,
ISOLATION AND TERMINATION

Memory Addressing

Instruction Execution Times

The RCB 44/20A is fully compatible with the RCX
920 Analog Signal Conditioning, Isolation and Termination Panel. The RCX 920 panel provides integral
mounting for one RCB 44/20A, with connectors for
power, the BITBUS interconnect signals, arid 18
Analog Devices 5B Series Signal Conditioning and
Isolation Modules. These modules provide 240V
RMS field wiring protection, and 1500V RMS common mode voltage isolation and support signal conditioning in a wide range of analog voltages and currents including thermocouple and RTD sensors, millivolt and volt inputs and 4-20 mA and 0-20 mA
outputs.

iDCM Controller
Up to 64K bytes code

Address Ranges
Option A
External Data
Memory Site
External Code
Memory Site
Internal Code
Memory

SPECIFICATIONS
CPU

Option B

OOOOH-7FFFH

1OOOH -OFFFFH
(OOOOH-OFFFFH if
EAActive)

8000H-OFFEFH

OOOOH-OFFFH

NOTES:

8044 BITBUS Enhanced Microcontroller (BEM)

Option A: Supports maximum amount of external EPROM
code memory
Option B: Supports downloading code into external RAM or
EEPROM memory

Word Size
Instruction-8 bits
Data-8 bits

BITBUSTM Development Environments
BITBUSTM TOOLS

HOST
SYSTEM

ICETM

NODE

DCS 100
TOOLBOX

iii
Ql

'"
d5

::;
OJ
OJ

10
=>

Series II
III

0..

x
J:
....,

oo
0
D

C\I

15
=>

IV
iPDSTM

iRMX®5%"
8"
XENIX5W

8"
DOS

A
X
X
X
X
X

A
X
X

X
X
B
B
X

EPROMPROG.

CODE

X
X
X
X
X

C\I

oo
Q

:::;

iii
::;
oo

iii
~
...J

iii

0..

c==:==:,.

c:===::-

<:::=:=

Example Configuration

18·82

c:=:==>

IRCB 44/10A
Remotl Digital Boord

8044 BITBUSTM
ENHANCED MICROCONTROLLER
Dual Processor Microcontroller
• Architecture
Performance S-Bit CPU
• High
Embedded Parallel Communications
• Firmware
Tuned for Distributed Real-Time
• Control

Firmware Included On-Chip
• BITBUSTM
Diagnostics
• Power-Up
DCX 51 Distributed Control Executive
• Included On-Chip
• MCS®-51 Software Compatible

The 8044 BITBUS Enhanced Microcontroller (BEM) is a powerful 8-bit microcontroller with on-chip firmware.
The dual processor architecture of the 8044 combined with the inherent the processing power of an 8051 CPU
is well suited for distributed data acquisition and control applications in both the factory and laboratory. The
firmware integral includes facilities for: diagnostics. task management. message passing. and user-transparent
parallel and serial communication services.

FREQUENCE
REFERENCE

192 BYTES
DUAL PORT
RAM

SIU
(SERIAL
INTERFACE
UNIT)

I---'-DATA

1 - - - . SDLt-BASED
SERIAL
COMMUNICATIONS

TWO 16-BIT
TIMER EVENT
COUNTERS

INTERRUPTS

CONTROL

PARALLEL PORTS
ADDRESS DATA BUS
AND 110 PINS

COUNTERS

280129-1

Figure 1. BEM Block Diagram

"IBM is a trademark of International Business Machines Corporation.

18-83

October 1987
Order Number: 280129-003

inter

8044 BITBUSTM Enhanced Microcontroller

and computational power are provided by the onchip 8-bit 8051 CPU. The Serial Interface Unit (SIU)
executes a majority of the communications functions
in hardware resulting in a high performance solution
for distributed control applications where communication and processing power are equally important.
The BEM's firmware implements the BITBUS message structure and protocol,and the pre-defined I/O
command set.

OPERATING ENVIRONMENT

Introduction
The BITBUS Interconnect Serial Control Bus Specifi~
cation defines an integrated architecture optimized
for implementing real-time distributed control systems. The architecture includes a message structure
and protocol for multitasking. environments, and a
predefined interface for I/O access and control. As
with traditional bus specifications the mechanical,
electrical, and data protocols have been defined.
Over a twisted pair of wires the bus can support up
to 250 nodes at three different bit rates dependent
on application performance requirements. Figure 2
illustrates the BITBUS Interconnect architecture.

Firmware
The 8044 microcontroller requires specific hardware
to interface to BITBUS. The BEM's firmware also
requires a pa,rticular hardware environment in order
to execute correctly, just as the iOCX 86 Operating
System or other operating systems required a specific hardware environment, i.e., interrupt controller,
timers, etc. Based upon the hardware provided, Basic or Extended firmware environments result.

The 8044 BITBUS Enhanced Microcontroller (BEM)
.or OCM Controller provides the user with the smallest BITBUS building block-a BITBUS component
solution. With its dual processor architecture, this
unique single chip provides both communication and
computational engines (Figure 3). Real-time control

The Basic firmware environment supports the minimum configuration for the BEM to execute as a

MASTER
TASKS
TRANSACTION
PROTOCOL
DATA LINK
PHYSICAL
LINK

PHYSICAL
LINK

/
PHYSICAL
LINK

DATA LINK

TRANSACTION
PROTOCOL

SLAVE TASKS

280129-2

Figure 2. BITBUSTM Architecture

CONTROL
LINES

8051
MICRO·
CONTROLLER

DUA ....PORT
RAM

HOLCI

..... SDLC

~-+

PORT

280129-3

Figure 3. 8044's Dual Processor Architecture
18-84

intJ

8044 BITBUSTM Enhanced Microcontroller

BITBUS device. The Extended firmware environ-,
ment requires hardware incremental to the Basic environment and allows the user to take full advantage
of all the features included in the BEM's firmware.
The designer may implement the Basic or Extended
firmware environment as desired as long as the programmatic requirements of the firmware are met
(see below).

EXTENDED FIRMWARE ENVIRONMENT
(Continued)

Figure 4 shows one example of an Extended firmware environment. This particular example represents the BITBUS Core as used on Intel's iSBXTM
344A BITBUS Controller MULTIMODULETM Board
and iRCB 44/10A BITBUS Remote Controller
. Board.

Configuration

OFFFEH external data
space

System RAM

0-02FFH external data
space

Diagnostic LED ;II 1

Port 1.0 (Pin 1)

Diagnostic LED /I 2

Port 1.1 (Pin 2)

User Task Interface

First Task DescriptorOFFFOH to OFFFFH in
External data space
Other Task Descriptors
and User Code01000H to OFFEFH '
in external code space

User RAM Availability

On-Chip-02AH to 02FH
bit space
Off-Chip-BITBUS
Master: 0400H to
OFFEFH external data
space
BITBUS Slave: 0100Hto
OFFEFH external data
space

Remote Access and
Control Interface

Memory-Mapped 1/0OFFOOH to OFFFFH
external data space

BASIC FIRMWARE ENVIRONMENT
Memory Bus

Parallel ports of 8044

BITBUS Node Address

OFFFFH external data
space

Configuration

OFFFEH external data
space

System RAM

0-02FFH external data
space

Diagnostic LED /I 1

Port 1.0 (Pin 1)

Diagnostic LED /I 2

Port 1.1 (Pin 2)

EXTENDED FIRMWARE ENVIRONMENT
Memory Bus

Parallel ports of 8044

BITBUS Node Address

OFFFFH external data
space

ADO-AD7

)

BITBUS'-INTERCONNECT

OPTIONAL

DATA

~
DCLK/·
RTSPAIR

ro~

SCLK

1/0'

l[b

r---

ADO·AD7

ADO-AD7

DATA
SERIAL
INTERFAC

[

12MHz CRVSTAL

O.SC~TOR

CONFIG,

,-:.

BEM

MEMORY

RTS'

f'.--

CDDE
MEMORY

AO-AF

LATCH

A8-AF

PMEM'

_.-

I-

AS-AF

DECODER

~I
[

IOCS'

C ONCS'

t--

t - - FIFO

280129-4

Figure 4. Extended Firmware Environment Example
18-85

8044 BITBUSTM Enhanced Microcontroller

suits in high performance and reliability for distributed control and processing environments. The intelligent SIU offloads the CPU from communication
tasks,thus dedicating more of its compute power to
external processes.

EXTENDED FIRMWARE ENVIRONMENT
(Continued)
Parallel Interface to
Extension Device

FIFO Command Byte-:OFF01 H external data
space
FIFO Data Byte-OFFOOH
external data space
Receive Data Intr-INTO
(pin 12)
Transmit Data Intr-INT1
(pin 13)
Command/Data BitP1.2

Major features of the 8051 microcontroller are:
• 8-bit CPU
• On-chip oscillator
• 4K bytes of RAM
• 192 bytes of ROM
•
•
•
•
•

FUNCTIONAL DESCRIPTION

High Performance 8044
Microcontroller
The 8044 combines the powerful 8051 microcontroller with an intelligent serial communications controller to provide a single-chip solution that efficiently
implements distributed processing or distributed
control systems. The microcontroller is a self-sufficient unit containing ROM, RAM, ALU, and peripherals. The 8044's architecture and instruction set are
identical to the 8051's. The serial interface of the
8051 is replaced with an intelligent communications
processor,the Serial Interface Init (SIU), on the
8044. This unique dual processor architecture re-

32 I/O lines
64K address space external data memory
64K address space external program memory
Two Programmable 16-bit counters
Five source interrupt· structure with two priority
levels

• Bit addressability for Boolean functions
• 1 foLs instruction cycle time for 60% instructions
2 foLsinstruction cycle time for 40% instructions
• 4 foLs cycle time for 8 by 8 unsigned multiple and
divide
As noted in the Operating Environment discussion,
the BITBUS firmware requires various CPU resources, Le., memory, timers, and I/O dependent upon
the firmware environment selected.

EXTERNAL,

OFFF

EXTERNAL

INTERNAL

(n
0000

(Ell 0)

0000

~,--------~¥------~_/

INTERNAL
DATA MEMORY

PROGRAM MEMORY

"---"
EXTERNAL
DATA

MEMORY

280129-5

Figure 5. BEM Memory Map
18-86

inter

8044 BITBUSTM Enhanced Microcontroller

Memory Architecture

SIGNAL FUNCTIONS

The 8044 microcontroller maintains separate data
and code memory spaces. Internal data memory
and program memory reside on the controller. External memory resides outside the controller. The BEM
firmware uses the available internal code memory
space and most of the remaining internal data memory with the exception of bit space 02AH to 02FH.
Figure 5 shows the BEM's memory map.

The 8044 BEM's pin configuration and pin description follow.

P1.0
P1.1

P1.2

m
I/O ADDRESSING REQUIREMENTS

eTS
RST

The table below provides the BEM's I/O port addresses.
Table 1. BEM I/O Addressing
Function

Address

Bit

Red LED P1.0

90H

Green LED P1.1

91H

TCMD
RFNF#

92H

B3H

TFNF#

B2H

RDY/NE"

B4H

TXD
INTI
INTO

TO
T1

Byte

WR
liD

P1.3
P1.4
P1.5
P1.6
P1.7
P3.0
P3.1
P3.2
P3.3
P3.4

P3.5
P3 ••

P3.7
XTAL2

XTAL1
VSS

.0
3.
3.
37
3.
3.
3.
33
32
31
3D
2.
28
27
2.
2.
2.

•
•
6

•
•
10
11

12
13
1.
1.
16
17
18
1.
20

vee
".0
PD.1
".2

........

PO.3

PO.6

".7

1!li

VPP
ALE JIIWlI
PSm
P2.7
P2.6
P2.5
P2.'
P2.3
P2.2

22 P2.1
21 P'.O

280129-6

Figure 6A. BEM DIP Pin Configuration

Node Address

FFFFH

Configuration

FFFEH

Reserved

FFEOH-FFFDH

Digital I/O

FFCOH-FFDFH

SBX #4

FFBOH-FFBFH

P1.7

SBX #3

FFBOH-FFAFH

RST/VPD
P3.0

SBX #2

FF90H-FF9FH

Nle

SBX #1

FF80H-FF8FH

User Defined

FF40H-FF7FH

Reserved

FF02H-FF3FH

FIFO Command

FF01H

FIFO Data

FFOOH

P1.5

P1.6

9
11

8044

P3.1

12
13

P3.2
P3.3

",
15

P3.'
P3.5

1.
17

R0112

39
38
37
3.
3S
3.
33
32
31
30

PD.'
PO.S
PO ••
PO.7

P2.S

EA
Nle
ALE
PSEN
P2.7
P2 ••

1B 1920 21 22 23 2. 25 2. 27 2B

280129-26

Figure 6B. BEM PLCC Pin Configuration
Table 2. BEM Pin Description
Name

Description

VSS

Circuit ground potential.

Vee

+ 5V power supply during operation and program verification.

PORTO

Port 0 is an 8-bit open drain bidirectional I/O port. It is also the multiplexed low-order address
and data bus when using external memory. It is used for data output during program
verification. Port 0 can sink/source eight LS TIL loads.

PORT 1

Port 1 is an 8-bit quasi-bidirectional I/O port. It is used for the low-order address byte during
program verification. Port 1 can sink/source four LS TTL loads.
In non-loop mode two of the I/O lines serve alternate functions:
-RTS (P1.6) Request-to Send output. A low indicates that the 8044 is ready to transmit.
-CTS (P1. 7) Clear-to-Send input. A low indicates that a receiving station is ready to receive.
18-87

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8044 BITBUSTM Enhanced Microcontroller

Table 2. BEM Pin Description (Continued)
Name

Description

PORT 2

PORTS

Port S is an 8-bit quasi-bidirectional 1/0 port. It also contains the interrupt, timer, serial port
and RD and WR pins that are used by various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for that function to operate. Port S
can sinklsource four LS TTL loads.
In addition to 1/0 some of the pins also serve alternate functions as follows:
• 1/0 R x 0 (PS.O). In point-to-point or multipoint configurations, this pin controls the
direction of pin PS.1. Serves as Receive Data input in loop and diagnostic modes.
-. DATA T x 0 (PS.1). In point-to-point or multipoint configurations, this pin functions as
data input/output. In loop mode, it serves as transmit pin. A '0' written to this pin
enables diagnostic mode.
• INTO (PS.2). Interrupt 0 input or gate control input for counter O.
• INT1 (PS.S). Interrupt 1 input or gate control input for counter 1.
• TO (PS.4). Input to counter O.
• SCLK T1 (PS.5). In addition to 1/0, this pin provides input to counter 1 or serves as
SCLK (serial clock) input. • WR (PS.6). The write control signal latches the data byte from Port 0 into the External
Data Memory.
• RD (PS.7). The read control signal enables External Data Memory to Port O.

RST

A high on this pin for two machine cycles while the oscillator is running resets th'e device. A
small external pulldown resistor (::::: 8.2 KO) from RST to VSS permits power-on reset
when a capacitor (::::: 10 /Lf) is also connected from this pin to Vee.

ALE/PROG

Provides Address Latch Enable output used for latching the address into external memory
during normal operation. It is activated every six oscillator periods except during an
external data memory access. It also receives the program pulse input for programming
the EPROM version.

PSEN

The Program Store Enable output is a control signal that enables the external Program
Memory to the bus during external fetch operations. It is activated every six oscillator
periods, except during external data memory accesses. Remains high during internal
program execution.

EAIVPP

When held at a TTL high level, the 8044 executes instructions from the internal ROM when
the PC is less than 4096. When held at a TTL low level, the 8044 fetches all instructions
from external Program Memory. The pin also receives the 21V EPROM programming
supply voltage on the 8744.

XTAL1

Input to the oscillator's high gain amplifier. Required when a crystal is used. Connect to
VSS when external source is used on XTAL 2.

XTAL2

Output from the oscillator's amplifier. Input to the internal timing circuitry. A crystal or
external source can be used.

Firm~are

Basic Firmware Services

The BEM's Basic firmware environment provides
two services: BITBUS Communications and PowerUp Diagnostics. The Extended firmware environment provides the Basic firmware services plus Parallel Communications and User Software Services
(iDCX 51 Executive, Remote Access and Control
functions). A discussion of each service follows.

POWER·UP DIAGNOSTICS
INCREASE RELIABILITY
For added reliability and simplified system start up,
the BEM firmware includes power~up diagnostics. ,At
chip reset the BEM diagnostic firmware checks the
integrity of the 8044's instruction set, ROM, internal

18-88

infef

8044 BITBUSTM Enhanced Microcontroller

RAM, and external RAM. LED indicator lights may
be used to show the progress of the diagnostics.
Intel's BITBUs boards use one red LED, and one
green LED as indicators for test progress. Since the
test halts if a fault is found, the last LED state indicates the trouble area.
No programmatic interface exists for the power-up
diagnostics. Only LEOs (or other indicators) connected to the outputs of Port 1 of the 8044 are required. For the test sequence shown in Table 3, the
red LED is connected to pin P1.0, and the green
LED is connected to pin P1.1.

BITBUSTM Physical Interface
Implementation of the electrical interface to BITBUs
requires external hardware. Specifically, an EIA
Standard Rs-485 driver and transceiver and an optional clock source for the synchronous mode of operation. A self clocked mode of operation is also
available. Different modes of operation facilitate a
variety of performance/distance options as noted in
Table 4. Figure 7 illustrates the BEM's BITBUs interface hardware requirements.
Table 4. BITBUSTM
Interconnect Modes of Operation

Table 3. Power-Up Test Sequence

Max.Dlst
Max #
Speed Between
Nodes
Max #
Kb/s Repeaters Between Repeaters
M/ft
Repeaters

State of Port'
After Test Completion
Test Sequence

Red LED
(Pin 1.0)

Green LED
(Pin 1.1)

Power-on

Prior to Start of Tests

Off

Test 1-lnstruction Set

Test2-ROM
Checksum Test

Off

Test 3-lnternal RAM

Off

Test 4-External RAM

Off

synchro2400
nous
selfClocked

30/100

375 300/1000
62.5 1200/4000

28
28

2
10

BITBUSTM Data Link Service

'Ports are Active Low.

BITBUSTM INTERFACE SIMPLIFIES DESIGN
OF DISTRIBUTED CONTROL SYSTEMS
The BITBUs Serial Control Bus is a serial bus optimized for high speed transfer of short messages in a
hierarchical system. From the perspective of systems using the BITBUs bus there are three external
protocols that must be adhered to: physical, data
link, and transaction control as shown in Figure 2.
The physical interface includes all bus hardware requirements, e.g. cable and connector definition,
transceiver specification. The data link interface refers to the device to device transfer of frames on the
bus. The transaction control interface indentifies the
rules for transmitting messages on the bus as well
as the format of the messages passed.
For maximum reliability and to facilitate standardization the following existing standards were chosen as
portions of the BITBUs Specification: International
Electrotechnical Commission (lEG) mechanical
board and connector specifications, the Electronic
Industry Association (EIA) Rs-485 Electrical Specification and IBM"s Serial Data Link Control protocol
for the physical and data link levels of the BITBUs
interface.

The 8044's serial interface unit (SIU) implements a
majority of the data link interface, a subset of IBM's
Serial Data Link Protocol (sDLG), in hardware resulting in a significant performance advantage compared with multichip solutions. Multichip solutions require both hardware and software glue that degrade
performance, decrease reliability, and increase cost.
This portion of the BITBUs interface requires no
user involvement for execution.
For a detailed discussion of the protocol executed
by the BITBUs data link service refer to "The
BITBUs Interconnect Serial Control Bus Specification". A basic subset of sDLC with the REJECT op,tion is implemented. The standard frame format
transferred across the BITBUs is shown in Figure 8.
The information field carries the BITBUS message.
BITBUSTM Transaction Control Service
For added reliability, the BITBUs interface incorporates error checking at the message level in addition
to the imbedded error checking provided by sDLC at
the data link level. The message control interface
defines the format and function of messages transmitted in frames across the BITBUs bus. (Figure 9)
The transaction protocol requires that for every order message transmitted across the bus a reply
message must be transmitted in return. Error types
and error detection mechanisms are also designated
by this interface.

18-89

8044BITBUSTM Enhanced Microcontroller

+5V

ALE

..-- D

."V

Q-

r--D

-::-

P------

CLA

I
MCLK

:>--

0_0-

CLA

0
DATA

S DATA

110.
~

ATS'

.J~

"'>

-cr- I

~
'v

0..2..
-::-

DATA-

.5V

L-J

DCLK/ATS

DCLK'/
ATI'

.J>--

SCLK

280129-7

NOTES:
1. Connect to ground for self·clocked mode andSCLK for synchronous mode.
2. Remove for self·clocked operation with repeater(s).
3. Connect to RTS· for synchronous mode or IIp· for self·clocked mode.
4. Selects MCLKas serial clock source.
5. Selects ALE or oscillator as serial clock source.

Figure 7. BITBUSTM Interface Hardware Requirements

IFLAG IADDRESS ICONTROL IINFORMATION IFCS IFLAG I
N

(BYTES)

Figure 8. BITBUSTM Frame Format
Msa
LENGTH
MT I SE I DE I TR I RESERVED
NODE ADDRESS
SOURCE TASK

IDESTINATION TASK

COMMAND/RESPONSE

MT • MESSAGE TYPE
SE • SOURCE EXTENSION
DE • DESTINATION EXTENSION
TR • TRACK FIELD

DATA

280129-8

Figure 9. BITBUSTM Message Format

18·90

intJ

8044 BITBUSTM Enhanced Microcontroller

BITBUSTM Interface Configuration
The BEM's firmware also simplifies designation of
the bus mode of operation (Speed/distance option)
as well as the node address, memory configuration
and parallel interface parameters by reading two external locations for this information as shown in Fig-

ure 10. The designer no longer needs to directly manipulate the 8044's serial mode register (SMD),
status/command register (STS) , and send/receive
counter register (NSNR). These two 8-bit locations
are derived by multiplexing the 8044's port 0 address lines ADO-AD?

Node Address Register

o
o
o
o
o
o
o
o

BITO
BIT 1
BIT2
BIT3
BIT4
BITS
BIT6
BIT 7

ALL JUMPERS REMOVED SELECTS
NODE ADDRESS OOH.
ALL JUMPERS INSTALLED SELECTS
NODE ADDRESS FFH.

280129-9

Mode Register
ESTABLISH THE BITBUS'· MODE IN THE
BEM FIRMWARE. THEY ARE USED ONLY
DURING POWER·UP. BITBUS" MODE AND
BIT RATE ARE AS FOLLOWS:
00· SYNCHRONOUS
01 • SELF·CLOCKED 375Kb/SEC
10· RESERVED
11 • SELF·CLOCKED 62.5Kb/SEC.
RESERVED FOR FUTURE USE.
CONNECTED TO THE EA PIN OF THE
8044, ALLOWING INTERNAL ROM TO BE
DISABLED. JUMPER REMOVED ENABLES
INTERNAL ROM.

BITO
BIT 1
BIT2

BIT3

BIT4
BITS

_______

______

o
o
o~

CONNECTED TOTHE MEMORY DECODE PAL
TO PROVIDE THE TWO MEMORY
ADDRESSING OPTIONS. IN BOTH CASES,

~~~~O:~t~'i~lT;;I~:; I~F SEPARATE
MAINTAINED. JUMPER REMOVED ROR
OPTION A; JUMPER INSTALLED FOR OPTION B.

BIT6
BIT7

~NR~litJi.~~~g~~E~I::~l~~I~~J~

THIS INFORMATION ON
INITIALIZATION. JUMPER REMOVED
INDICATES NO BYTE FIFO.
SELECTS EXTENSION MODE IF
BYTE FIFO IS PRESENT:
0= INTERRUPT
1 =DMA
RESERVED FOR FUTURE USE.

280129-10

NOTE:
Jumper Installed = 1
Jumper Removed = 0

Figure 10. BITBUSTM Firmware Configuration
18-91

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8044 BITBUSTM Enhanced Microcontroller

Extended Firmware Services
PARALLEL COMMUNICATION INTERFACE
EXTENDS DISTRIBUTED CONTROL
CAPABILITY

The BEM's firmware also includes a parallel interface for expanding the capabilities of distributed systems. For example, this interface allows other processors to be employed in BITBUS systems if more
processing power is required as shown in Figure 11.
This interface provides the means for connection to
other buses: iSBX bus, STD bus, IBM's PC bus.
The interface consists of a byte-FIFO queue through
which BITBUS messages can be passd via embedded communications firmware. From the BEM's perspective the user simply designates the correct routing information in the BITBUS message header and
the message is directed to the communications firmware and passed through the parallel interface. One
example of an implementation that uses this interface is the iSBX BITBUS Controller MULTIMODULE
Board via the iSBX bus.
Parallel Interface Hardware

To implement the Parallel Interface, the user must
provide hardware for two FIFOs (one byte minimum)
in external data memory, and control signals to/from
the 8044's Pins: INTO (P3.2), INT1 (P3.3), and P1.2.
Key hardware elements required are: decoder for
the registers' external addresses, temporary storage
for bytes passing through the interface, a way to
designate bytes as command or data, and a means
to generate the control signals. FIFO's must be used
to move the data through the interface although the
depth of the FIFO need not exceed one byte.

Interface hardware must also be provided for the
"extension" side of the interface. Implementation of
this hardware is left to the user with the restriction
that the operation of the BEM side remains independent.
Parallel Byte Stream and Message Protocol

The two byte registers (FIFOs) provide the path for
bytes to move through the parallel interface. Bytes
are read or written from the registers designated:
FIFO Data Byte (FFOOH) and FIFO Command Byte
(FF01 H). INTO, INT1 and P1.2 provide control signals to the firmware for moving the bytes through
the registers. These signals are referred to as the
Parallel Interface Control Bits:
Pin

INTO
INT1
P1.2

Function

RFNF
TFNE
TCMD

Internal Bit Address

B3H
B2H
92H

The hardware uses RFNF to control the output of
bytes from the BEM. RFNF is set when the FIFO
Data or FIFO Command Byte Registers can receive
information. RFNF remains clear when the FIFO
Data or Command Bytes are not available. Transmission of a BITBUS message across the parallel
interface consists of successively outputing message bytes to the FIFO Data Byte Register until all
bytes are sent. The firmware then writes a value of 0
to the Command Byte register indicating all the message bytes have been sent. The first data byte in the
message indicates the number of bytes in the message.

280129-11

Figure 11. Extending the Capability of BITBUSTM System with the Parallel Communications Interface
18-92

inter

8044 BITBUSTM Enhanced Microcontroller

TFNE controls the input of data bytes to the BEM.
This bit is set when bytes are available for reading.
When no bytes are available this bit is clear. TCMD
indicates whether the next byte read is a Data Byte
or Command Byte. BITBUS messages are received
by inputing data bytes until a command byte is received. Data bytes are read from the FIFO Data Byte
Register. Command Bytes are read from the FIFO
Command Byte Register.
Figure 12 provides one example of a Byte FIFO Interface. This specific example illustrates the interface provided on the iSBX 344A BITBUS Controller
MULTIMODULE Board. Figure 13 shows transmission of bytes from the BEM across the parallel interface. Figure 14 shows transmission of bytes to the
BEM.

SEND MESSAGE

TO BITBUS''"INTERCONNECT

WRITE

,----------------,
I
I

NEXT
DATA
BYTE

iSBX'" 344 BOARD

I
I

BEM

8044 lOCAL BUS

TCMO·

RFNf"

TFNE"

TRANSMIT
FIFO

RECEIVE
FIFO

YES

I
I
I

I
TFNF'
:6~~··
I
L ________________ ~

EXTENSION DEVICE CPU

WRITE

LOCAL BUS

ENDOF
MESSAGE
COMMAND
EXTENSION

DEVICE CPU

280129-12

Figure 12. Byte FIFO Interface Example

RETURN

280129-13

Figure 13. Transmitting a Message from BEM

18-93

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8044 BITBUSTM Enhanced Microcontroller

RECEIVE MESSAGE

READ
END OF
MESSAGE
COMMAND

1989_OEM_Boards_and_Systems_Hanbook 1989 OEM Boards And Systems Hanbook

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