1989_SEEQ_Data_Book 1989 SEEQ Data Book

User Manual: 1989_SEEQ_Data_Book

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TAARCOM, INC.
Ma~ufacturers

Represe ntatives

45' N. Shoreline Blvd .
. Mt. View , CA 94043
(415) 960 · 1550

seeQ
EEPROMS
FLASH
EPROMS
DATACOM
EEPLD
MILITARY
I

RELIABILITY
APPLICATIONS
GENERAL INFORMATION
seeQ

Technology, Incorporated - - - - - - - - -

ii

Table of Contents
EEPROMS
EEPROMS (Electrically Erasable Programmable Read Only Memories)
EEPROM Alternate Source ............................................................ 1-1
EEPROM Replacement Chart .......................................................... 1-2
16K Latched ........................................ 1-3
64K Latched, 10K cycles/byte ......................... 1-11
4K Latched & Timed, 10K cycles/byte ................... 1-19
16K Latched & Timed, 10K cycles/byte .................. 1-25
16K Latched & Timed, 1 M cycles/byte .................. 1-25
16K Latched & Timed, rdy/busy, 10K cycles/byte .......... 1-31
16K Latched & Timed, rdy/busy, 1 M cycles/ byte ........... 1-31
64K Latched & Timed, rdy/busy ........................ 1-37
64K CMOS Page Mode .............................. 1-43
64K CMOS Page Mode (W/Rdy/Busy) ................... 1-51
256K CMOS Page Mode ............................. 1-59
High Speed CMOS64K EEPROM ...................... 1-67
High Speed CMOS 256K EEPROM ............ , ........ 1-69
High Speed CMOS Bipolar PROM Replacement ........... 1-71
High Speed CMOS EEPROM .......................... 1-77
CMOS Timer E2 .......................... , ......... 1-83
Timer E2 .......................................... 1-85

52B13/52B13H
52B33/52B33H
2804A
2816A12816AH
5516A15516AH
2817A12817AH
5517A
2864/2864H
28C64
28C65
28C256
28C64A
28C256A
36C16/32
38C16/32
28C010
Modules Q/E28C01 0

FLASH
48F512
48F010
27F010
KT48

512K CMOS FLASH EEPROM .......................... 2-1
1024K CMOS FLASH EEPROM ........................ 2-13
1024K CMOS FLASH EEPROM ........................ 2-25
FLASHTM EEPROM PROGRAMMER .................... 2-37

EPROMS
EPROMS (Erasable Programmable Read Only Memories)
2764
27128
27C256

64K ............................................... 3-1
128K .............................................. 3-1
256KCMOS ........................................ 3-9

DATACOM
DATA COMMUNICATIONS
8003
8020
8023A
8005

Ethernet Data Link Controller ........................... 4-1
Manchester Code Converter ........................... 4-13
Manchester Code Converter ........................... 4-27
Advanced Ethernet Data Link Controller ................. 4-43

EEPLD
20RA10Z

Registered Asynchronous CMOS EEPLD ................. 5-1

seeQ Technology, Incorporated
iii

MILITARY
Military Standard-883 Class B Compliant Product Processing ................................ 6-1

EEPROMs
16K Latched ....................................... 6-7
16K Latched, (-40° to 85°C) ......................... 6-7
64K Latched ...................................... 6-15
64K Latched, (- 40° to 85°C) ........................ 6-15
16K Latched & Timed ............................... 6-21
16K Latched & Timed, rdy/busy pin .................... 6-27
64K Latched and Timed, rdy/busy pin .................. 6-33
64K CMOS Latched & Timed ......................... 6-39
64K CMOS Page Mode, Latched & Timed rdy/busy pin ..... 6-46
256K CMOS Page Mode, Latched & Timed .............. 6-55
High Speed CMOS Bipolar PROM Replacement .......... 6-63
High Speed CMOS Bipolar PROM Replacement .......... 6-63
High Speed CMOS ................................. 6-69
High Speed CMOS ................................. 6-69
1024K Electrically Erasable PROM .................... 6-75

M52B13/M52B13H
E52B13/E52B 13H
M52B33/M52833H
E52B33/E52B33H
M2816A1E2816A
M2817AlE2817A
M2864/2864H - E2864/2864H
M28C64/E28C64
M28C65/E28C65
M28C256/E28C256
M36C16/M36C32
E36C16/E36C32
M38C16/M38C32
E38C16/E38C32
Module M28C010

EPROMs
64K ............................................. 6-83
64K (- 40° to 85°C) ................................ 6-83
128K ............................................ 6-83
128K (- 40° to 85°) ................................ 6-83
256K CMOS ...................................... 6-91
256K CMOS ( - 40° to 85°C) ......................... 6-91
DESC SMD-Compliant 64K UV EPROM ................ 6-99
DESC SMD-Compliant 122K UV EPROM .............. 6-103
DESC SMD-Compliant 256K CMOS UV EPROM ......... 6-107

M2764
E2764
M27128
E27128
M27C256
E27C256
82005
82025
86063
FLASH

512K CMOS FLASH EEPROM ....................... 6-111
1024KCMOS FLASH EEPROM ...................... 6-123

ElM48F512
ElM48F010

RELIABILITY
SEEa EEPROM Reliability Report ..................................................... 7-1
Radiation and MOS Non-Volatile Memories .............................................. 7-7
Memory Products Reliability Note 1 ................................................... 7-11

S99Q Technology, Incorporated

----------------------

iv

APPLICATIONS
. Note 2
Note 5
Note 6
Note 7
Note 8
Note 9
Note 10
Note 11
Note 24
Note 27
Note 28

Microprocessor Interfacing With
SEEQ's Latched EEPROM ............................. 8-1
Interfacing The 8003 EDLC® To A 16-Bit Bus ................ 8-11
DMA Interconnection To The 8003 EDLC® .................. 8-19
8005 Advanced EDLC® Users Guide ...................... 8-27
EEPROM Interfacing .................................. 8-49
Software Downline Load Using
SEEQ's CMOS EEPROMs ............................ 8-65
Power-Up/Down With SEEQ's EEPROM ................... 8-73
Power Fail Protection With SEEQ's CMOS EEPROMs ........ 8-77
EEPROM As A Substitute For Bubble Memory .............. 8-83
Using High Speed CMOS EEPROMs With
High Performance Microprocessors ..................... 8-89
EEPLDs Interface IBM PC BUS With The EDLC® 8003 ...... 8-103

GENERAL INFORMATION
Thermal Resistance ................................................................... 9-1
Packaging Information ................................................................. 9-1
Package Diagrams .................................................................... 9-2
Bonding Diagrams ................................................................... 9-23
Domestic Sales/Rep. Office Listing ...................................................... 9-35
Distributor Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-35
International Sales/Rep. Office Listing .................................................... 9-35

seeQ

Technology. Incorporated

v

vi

seeQ

DATA BOOK

SEEO is your link to the future.
As the acknowledged leader in thin film EEPROM technology, we continue to advance the
state of the art. SEEO's full-featured EEPROM family leads the industry- and enhances your
system applications through ever-greater performance and higher endurance.
Our clustered product strategy uses this EE technology to tie together a group of focused
system solutions, high-density EEPROMs and EPROMs, our popular new high-speed
FLASHTM EEPROMs, EEPLDs and more. Each of these product disciplines uses the proprietary SEEO base memory technology, as well as versions of our proprietary a Cell
memory design.
This unique cell design, combined with our proprietary oxynitride process, results in the
most reliable EEPROMs available. For example, endurance failure rates on our 5516A (2K x 8
EEPROM) are S .0010/0 per 1,000 cycles (guaranteed for a minimum of 1 million writel erase
cycles). This represents a profound advance over typical failure rates of .050/0 per 1,000 hours
with intrinsic MOS.
SEEO has now also expanded into two important new product areas: bipolar PROM
replacements and EEPALs (our new 20RA1OZ). Keeping pace with our customer's needs, we
have also developed an important new family of Ethernet controller parts- newest is the 8005
data link controller.
Best known of all is SEEO's FLASH family of high-density EPROMs and EEPROMs.
These devices combine the in-circuit reprogrammability of traditional EEPROMs with the
high density until now associated only with UVEPROMs.
Packaging of our products includes standard dual in-line packages and a variety of surface
mount options. SEEa products may be ordered in plastic, ceramic dip, LCC, PLCC, flatpack
or if you wish, unencapsulated die.
Serving our customers, advancing technology, opening new markets-these are what
keep us at the forefront of our industry. Let SEEO be your link to the future. Call us today for
your design solution.

J. Daniel McCranie
President and CEO
vii

viii

lroduct Previews contain information on products under development. These specifications
llay be changed at any time, without notice.
"dvance Data Sheets contain target product specifications which are subject to change upon
jevice characterization over the full specified temperature range. These specifications may
:>e changed at any time, without notice.
~reliminary Data Sheets contain minimum and maximum limits specified over the full temp3rature range based upon initial production device characterization. These specifications may
:>e changed at any time, without notice.
a.dditional copies of this manual or other SEEQ literature may be obtained from:
SEEQ Technology Incorporated
Literature Department
1849 Fortune Drive
San Jose, CA 95131
The following are trademarks of SEEQ Technology and may only be used to identify SEEQ
products:
SEEQ®
Silicon Signature®
EDLC®
DiTrace®
MCCTM
FLASHTM
QCeWM
Assembly locations: Military products are assembled at SEEQ's offshore (Korea, Phillippines, Taiwan) and stateside assembly plants. The assembly plants are identified by
a designated alpha code as part of the device backside marking. The alpha codes used are: Korea = K, Philippines = P, Taiwan = T, United States= US.A.
Applications for any integrated circuits contained in this publication are for illustration purposes only and SEEQ makes no representation orwaranty that such applications
will be suitable for the use specified.
Circuit diagrams are included as a means of illustrating typical applications, and complete information for construction purposes is not necessarily given. The information
presented here has been carefully checked, and is believed to be entirely reliable, but no responsibility is assumed for inaccuracies. Furthermore, no responsibility is
assumed by SEEQ Technology, Inc., for use; not for any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication, or otherwise, under any patent or patent rights of SEEQ Technology, Inc.
Products of SEEQ may not be used as critical components in Life Support Systems without the express written authorization of the President and Vice-President of
Quality/Reliability of SEEQ Technology, Inc.
A critical component is any component whose failure to perform its intended function, could possibly lead to loss of life, or bodily harm.
Life Support Systems that may include but are not necessarily limited to:
1) Surgical implants in a human body,
2) Equipment used to sustain human life, or
3) Equipment used to monitor and/or measure human body conditions.
SEEQ Technology makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein.
SEEQ retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the latest specifications before plaCing your order.
A "For Reference Only" specification on a purchase order denotes the designated specification is for reference by the customer and is not invoked on the manufacturer.

seeQ

Technology, Incorporated

ix

x

SEEQ Technology
Product Selection Guide
4K EEPROMs
PART
NUMBER

ORGANIZATION

2804A

512 x8

250

80

40

C,E,M

2804A

512 x8

300

80

40

C,E,M

2804A

512 x8

350

80

40

C,E,M

PART
NUMBER

ORGANIZATION

ACCESS
TIME(ns)

52B13

2Kx8

200

80

30

C

52B13

2Kx8

250

80

30

C,E,M

52B13

2Kx8

300

80

30

M

52B13

2Kx8

350

80

30

C,E

2816A

2Kx8

200

110

40

C

2816A

2Kx8

250

110

40

C,E, M

2816A

2Kx8

300

110

40

C,E,M

2816A

2Kx8

350

110

40

C

5516A

2Kx8

200

110

40

C

5516A

2Kx8

250

110

40

C

5516A

2Kx8

300

110

40

C

2817A

2Kx8

200

110

40

C

2817A

2Kx8

250

110

40

C,E, M

2817A

2Kx8

300

110

40

C,E,M

ACCESS
TIME(ns)

ICC MAX. (mA*)
ACTIVE
STANDBY

TEMP
RANGE

PACKAGE
PD N L F

••
••
••

DATA SHEET
PAGE #
1-19
1-19
1-19

16K EEPROMs
ICC MAX. (mA*)
ACTIVE
STANDBY

TEMP
RANGE

2817A

2Kx8

350

110

40

C

5517A

2Kx8

250

110

40

C

5517A

2Kx8

300

110

40

C

TEMPERATURE RANGE

PACKAGE
PD N L F

••
••
••
••
••
••
••
••
•
•
•
••
••
••
••
•
•

PACKAGE
P =
D=
N=
L =
F =
M=

C = Commercial O°C to +70°C
E = Extended -40°C to +85°C
M = Military-55°C to +125°C
TBD = To Be Determined
*Commercial Temperature Range

xi

Plastic Dip
Ceramic Dip
Plastic Leaded Chip Carrier
Ceramic Leadless Chip Carrier
Flat Pack
Module

DATA SHEET
PAGE #
1-3
1-3, 6-7
1-3, 6-7
1-3, 6-7
1-25
1-25, 6-21
1-25, 6-21
1-25
1-25
1-25
1-25
1-31
1-31 6-27
I

1-31 6-27
I

1-31
1-31
1-31

64K EEPROMs
PART
NUMBER

ORGANIZATION

ACCESS
TIME(ns)

ICC MAX. (mA*)
ACTIVE
STANDBY

TEMP
RANGE

PACKAGE
P 0 NL F

••
•• •
•• •
••
•••••
•••••
•••••
••••
••••
••••
••••
••••
••••
••••
••••

52833

8Kx8

200

110

40

C

52833

8Kx8

250

110

40

C,E,M

52833

8Kx8

300

110

40

C,E,M

52833

8Kx8

350

110

40

C

2864

8Kx8

250

110

40

C,E,M

2864

8Kx8

300

110

40

C,E,M

2864

8Kx8

350

110

40

C,E,M

28C64

8Kx8

200

50

.150

C,E,M

28C64

8Kx8

250

50

.150

C,E,M

28C64

8Kx8

300

50

.150

C,E,M

28C64

8Kx8

350

50

.150

C,E,M

28C65

8Kx8

200

50

.150

C,E,M

28C65

8Kx8

250

50

.150

C,E,M

28C65

8Kx8

300

50

.150

C,E,M

28C65

8Kx8

350

50

.150

C,E,M

DATA SHEET
PAGE #

1-11
1-11,6-15
1-11,6-15
1-11
1-37,6-33
1-37,6-33
1-37,6-33
1-43,6-39
1-43,6-39
1-43,6-39
1-43,6-39
1-51, 6-46
1-51, 6-46
1-51, 6-46
1-51,6-46

256K EEPROMs
PART
NUMBER

ORGANIZATION

ACCESS
TIME(ns)

ICC MAX. (mA*)
ACTIVE
STANDBY

TEMP
RANGE

PACKAGE
P 0 NL F

DATA SHEET
PAGE #

•••••
•••••
•••••
•••••

1-59,6-55

28C256

32Kx8

200

60

.150

C,E,M

28C256

32Kx8

250

60

.150

C,E,M

28C256

32Kx8

300

60

.150

C,E,M

28C256

32Kx8

350

60

.150

C,E,M

1-59,6-55
1-59,6-55
1-59, 6-55

1024K EEPROMs
PART
NUMBER

ORGANIZATION

M28C010

128K x8

250

70

M28C010

128K x8

300

70

M28C010

128Kx8

350

70

2

C,E,M

ACCESS
TIME (ns)

ICC MAX. (mA*)
ACTIVE
STANDBY

T8D = To 8e Determined

PACKAGE
MP ON L

2

C,E,M

2

C,E,M

•
•
•
PACKAGE

TEMPERATURE RANGE
C = Commercial O°C to + 70°C
E = Extended -40°C to +85°C
M =Military-55°Cto+125°C

TEMP
RANGE

P =
D=
N=
L =
F =
M=

*Commercial Temperature Range

xii

Plastic Dip
Ceramic Dip
Plastic Leaded Chip Carrier
Ceramic Leadless Chip Carrier
Flat Pack
Module

F

DATA SHEET
PAGE #

1-85, 6-75
1-85,6-75
1-85,6-75

FLASH™ EEPROMS
PART
NUMBER

ORGANIZATION

ACCESS
TIME (ns)

48F512

64Kx8

200

ICC MAX. (mA*)
ACTIVE
STANDBY

60

TEMP
RANGE

.100

C

48F512

64Kx8

250

60

.100

C,E,M

48F512

64Kx8

300

60

.100

C,E,M

48F010

128Kx 8

200

60

.100

C

48F010

128K x 8

250

60

.100

C,E,M

48F010

128Kx8

300

60

.100

C,E,M

27F010

128Kx8

200

60

.100

C

27F010

128Kx 8

250

60

.100

C

27F010

128Kx8

300

60

.100

C

KT48

FLASH
PROGRAMMING KIT

PACKAGE
P D N L F

•••
••••
••••
•••
•• ••
••••
•••
•••
•••

DATA SHEET
PAGE #

2-1
2-1,6-111
2-1,6-111
2-13
2-13,6-123
2-13, 6-123
2-25
2-25
2-25
2-37

HIGH SPEED 16K EEPROMs
PART
NUMBER

ORGANIZATION

ACCESS
TIME (ns)

ICC MAX. (mA*)
ACTIVE
STANDBY

TEMP
RANGE

36C16

2Kx8

35

80

-

C

36C16

2Kx8

40

80

-

C

36C16

2Kx8

45

80

-

C,E,M

36C16

2Kx8

55

80

-

C,E,M

36C16

2Kx8

70

80

-

E,M

38C16

2Kx8

35

80

40

C

38C16

2Kx8

40

80

40

C

38C16

2Kx8

45

80

40

C,E,M

38C16

2Kx8

55

80

40

C,E,M

38C16

2Kx8

70

80

40

E,M

PACKAGE
P D N L F

••
••
•• •
•• •
• •
•••
•••
••••
••••
• •

DATA SHEET
PAGE #

1-71
1-71
1-71,6-63
1-71, 6-63
6-63
1-77
1-77
1-77,6-69
1-77,6-69
6-69

HIGH SPEED 32K EEPROMs
ICC MAX. (mA*)
ACTIVE
STANDBY

TEMP
RANGE

PART
NUMBER

ORGANIZATION

ACCESS
TIME (ns)

36C32

4Kx8

35

80

-

C

36C32

4Kx8

40

80

-

C

36C32

4Kx8

45

80

-

C,E,M

36C32

4Kx8

55

80

-

C,E,M

36C32

4Kx8

70

80

-

E,M

38C32

4Kx8

35

80

40

C

38C32

4Kx8

40

80

40

C

38C32

4Kx8

45

80

40

C,E,M

38C32

4Kx8

55

80

40

C,E,M

38C32

4Kx8

70

80

40

E,M

FLASH is a trademark of SEEQ Technology Inc.

xiii

PACKAGE
P D N L F

••
••
•• •
•• •
• •
•••
•••
••••
••••
••••

DATA SHEET
PAGE #

1-71
1-71
1-71, 6-63
1-71, 6-63
6-63
1-77
1-77
1-77,6-69
1-77, 6-69
6-69

64K1128K1256K UVEPROMs
PART
NUMBER

ORGANIZATION

2764

8Kx8

160

100

30

C

2764

8Kx8

200

100

30

C,E,M

ACCESS
TIME (ns)

ICC MAX. (rnA*)
STANDBY
ACTIVE

TEMP
RANGE

2764

8Kx8

250

100

30

C,E,M

2764

8Kx8

300

100

30

C

2764

8Kx8

350

100

30

E,M

2764

8Kx8

450

100

30

C,E,M

27128

16Kx8

200

100

30

C,E,M

27128

16Kx8

250

100

30

C,E,M

27128

16Kx8

300

100

30

C

27128

16Kx8

350

100

30

E,M

27128

16Kx8

450

100

30

C,E,M

27C256

32Kx8

200

50

.150

C,E,M

27C256

32Kx8

250

50

.150

C,E,M

27C256

32Kx8

300

50

.150

C,E,M

27C256

32Kx8

450

50

.150

C

PACKAGE
PD N L F

•
•
•

DATA SHEET
PAGE #

3-1
3-1,6-83
3-1,6-83

•

3-1

•
•
• •
• •
•
• •
• •

6-83
3-1,6-83
3-1,6-83
3-1, 6-83
3-1
6-83
3-1, 6-83

• •
• •
• •
•

3-9,6-91

PACKAGE
P D NL F

DATA SHEET
PAGE #

3-9, 6-91
3-9,6-91
3-9

DESC-COMPLIANT UVEPROMS
PART
NUMBER

ORGANIZATION

ACCESS
TIME (ns)

82005

8Kx8

200

100

30

M

82005

8Kx8

250

100

30

M

ICC MAX. (rnA*)
ACTIVE
STANDBY

TEMP
RANGE

82005

8Kx8

450

100

30

M

82025

16Kx8

200

100

30

M

82025

16Kx8

250

100

30

M

82025

16Kx8

300

100

30

M

82025

16Kx8

450

100

30

M

86063

32Kx8

200

50

.150

M

86063

32Kx8

250

50

.150

M

86063

32Kx8

300

50

.150

M

•
•
•
•
•
•
•
•
•
•

6-99
6-99
6-99

•
•
•
•
•
•
•

6-103
6-103
6-103
6-103
6-107
6-107
6-107

COMMUNICATION PRODUCTs
PART
NUMBER

ICC MAX.
ACTIVE (mA*)

TEMP
RANGE

8003

200

C

••

Ethernet Data Link
Controller

8020

75

C

10 MHz Manchester
Encoder/Decoder

4-13

8023A

75

C

10 MHz Manchester
Encoder/Decoder

4-27

8005

350

C

•••
•••
•

Advanced Ethernet Data
Link Controller

4-43

PACKAGE
P D NL F

xiv

FUNCTION

DATA SHEET
PAGE #

4-1

CMOS EEPLDs
PART
NUMBER

DESCRIPTION

PINS

SPEED

tpo (ns)

ICC MAX. (rnA*)
ACTIVE STANDBY

TEMP
RANGE

20RA10Z-35

Asynchronous

24

35

25**

.150

C***

20RA10Z-40

Asynchronous

24

40

25**

.150

C:** E, M

20RA10Z-45

Asynchronous

24

45

25**

.150

C:** E, M

TBD = To Be Determined

••••
••••
••••

PACKAGE

TEMPERATURE RANGE
C = Commercial O°C to + 70°C
E = Extended -40°C to +85°C
M = Military -55°C to +125°C

PACKAGE
P D N L F

P = Plastic Dip
D = Ceramic Dip
N = Plastic Leaded Chip Carrier
L = Ceramic Leadless Chip Carrier
F = Flat Pack
M=Module

*Commercial Temperature Range
**f = 1 MHz; 5mA/Additional MHz
***Commercial O°C to 75°C

xv

DATA SHEET
PAGE #

5·1
5·1
5·1

xvi

EEPROMS

(Electrically Erasable Programmable Read Only Memories)

I

SEEQ Technology
EEPROM Alternate Source

MFG.

Part No.

Description

SEEQ Part No.

AM.D.

2817A

2K X8 EEPROM

2817A

AM.D.

9864

8K X8 EEPROM

2864

AM.D.

28648

8K X8 EEPROM

28C64

ATMEL

28C64

8K X8 EEPROM

28C64

EXEL

2804A

512 X 8 EEPROM

2804A

EXEL

46C16-55

2K X8 EEPROM

36C16-55

EXEL

2816A

2K X 8 EEPROM

2816A

EXEL

2864

8K X 8 EEPROM

28C64

EXEL

2865

8K X8 EEPROM

28C65

FUJITSU

28C64

8K X8 EEPROM

28C64

FUJITSU

28C65

8K X8 EEPROM

28C65

GJ.

28C64

8K X8 EEPROM

28C64

HITACHI

58064

8K X8 EEPROM

52833

INTEL

2816

2K X 8 EEPROM

52813

INTEL

2816A

2K X 8 EEPROM

52813

INTEL

2817A

2K X 8 EEPROM

2817A

NATIONAL

9816A

2K X8 EEPROM

2816A

NATIONAL

9817A

2K X8 EEPROM

2817A

SAMSUNG

2816A

2K X8 EEPROM

2816A

SAMSUNG

2817A

2K X8 EEPROM

2817A

XICOR

2616

2K X 8 EEPROM

36C16-45

XICOR

2816H

2K X8 EEPROM

38C16-45

XICOR

2804A

512 X 8 EEPROM

2804A

XICOR

2816A

2K X8 EEPROM

2816A

XICOR

2864A

8K X8 EEPROM

28C64

XICOR

28648

8K X8 EEPROM

28C64

XICOR

28256

32 K X 8 EEPROM

28C256

--seeQ

Technology,lncorporated--------------------------

1-1

SEEQ Technology
PROM Replacement Chart

MFG.

Part No.

Description

SEEO Part No.

A.M.D.

AM27PS291 DC

2KX8 PROM

36C16-45

A.M.D.

AM27PS291 DM

2K X8 PROM

36C16-55

A.M.D.

AM27PS291 ADM

2K X8 PROM

36C16-55

A.M.D.

AM27S291 ADC

2KX8 PROM

36C16-35

CYPRESS

CY7C291-35

2K X8 PROM

36C16-35

CYPRESS

CY7C291-50

2K X8 PROM

36C16-45

FUJITSU

MB7138Y-SKZ

2KX8 PROM

36C16-35

FUJITSU

MB7138H-SKZ

2K X8 PROM

36C16-45

FUJITSU

MB7138E-WZ

2K X8 PROM

36C16-45

HARRIS

6-76161

2KX8 PROM

36C16-45

M.M.I.

63S1681NS

2K X8 PROM

36C16-45

M.M.I.

63S1681ANS

2K X8 PROM

36C16-35

NATIONAL

DM77S291

2KX8 PROM

36C16-55

NATIONAL

DM87S291

2KX8 PROM

36C16-55

RAYTHEON

29681ASM

2KX8 PROM

36C16-55

RAYTHEON

29681ASC

2K X8 PROM

36C16-55

RAYTHEON

29681SC

2K X8 PROM

36C16-55

RAYTHEON

29683ASC

2K X8 PROM

36C16-45

RAYTHEON

29683ASM

2K X8 PROM

36C16-55

SIGNETICS

82S291

2K X8 PROM

36C16-45

T.I.

27C291-35

2KX8 PROM

36C16-45
36C16-45

T.I.

27C291-50

2K X8 PROM

T,I.

TBP28S166N

2KX8 PROM

36C16-45

WAFRSCAL

57C291-40

2K X8 PROM

36C16-35

WAFRSCAL

57C291-55

2K X8 PROM

36C16-55

NATIONAL

DM87S421

4K X8 PROM

36C32-55

NATIONAL

DM87S421A

4K X8 PROM

36C32-45

NATIONAL

DM77S421

4K X8 PROM

36C32-55

NATIONAL

DM77S421A

4KX8 PROM

36C32-55

RAYTHEON

29671ASC

4KX8 PROM

36C32-45

RAYTHEON

29671ASM

4K X8 PROM

36C32-55

RAYTHEON

29673SC

4KX8 PROM

36C32-55

RAYTHEON

29673SM

4KX8 PROM

36C32-55

seeQ T e c h n o / o g y , l n c o ' p o ' a t e d - - - - - - - - - - - - - - - - - - - - - - - 1-2

seeQ

52B13/52B13H
16K Electrically Erasable PROM
October 1988

Features

Description

• Input Latches
• TTL Byte Erase/Byte Write
• 1 ms(52B13H} or9msByteErase/Byte Write

SEEQ's 52B13 and 52B13H are 2048 x 8 bit, 5 volt
electrically erasable programmable read only
memories (EEPROM) with input latches on all
address, data and control (chip and output enable)
lines. Data is latched and electically written by either
a TTL or a 21V pulse on the Write Enable pin. Once
written, which requires under 10 ms, there is no limit to
the number of times data may be read. Both byte and
chip erase modes are available. The erasure time in
either mode is under 10 ms, and each byte may be
erased and written a minimum of 10,000 times. They
are direct pin-for-pin replacement for SEEQ's 5213 and
Intel 281612816A.

• Power Up/Down Protection
• 10,000 Erase/Write Cycles per Byte Minimum
• 5V ± 10% Operation
• Fast Read Access Time - 200 ns
• Infinite Number of Read Cycles
• Chip Erase and Byte Erase
TII

• DiTrace
• JEDEC Approved Byte Wide Memory Pinout
• Military And Extended Temperature Range
Available

The 52B13 and 52B13H are ideal for applications that
require a non-volatile memory with in-system write and
erase capability. Dynamic reconfiguration (the alteration of operating software in real-time) is made possible
by this device. Applications for the 52B13 and 52B13H
will be found in military avionics systems, programmable character generators, self-calibrating instruments!

• Direct Replacement For Intel 281612816A

Siock Diagram

(continued on next pagel

Pin Configuration
52B13/52B13H
AO-3

A4-10

COLUMN
ADDRESS
LATCHES

COLUMN
ADDRESS
DECODE

ROW
ADDRESS
DECODE

ROW
ADDRESS
LATCHES

E2
MEMORY
ARRAY

A7

VCC

AS

As

A5

As

A4

WE

A3

i5E

A2

A10

A1

CE

AO

1/07

1/00

I/Os

1/01

1/05

1/02

1/04

GND

1/03

LATCH ENABLE
WRITE/ERASE ENABLE

Pin Names
AO-A10

Q Cell is

a trademark of SEEQ Technology, Inc.
1/00-7

seeQ
MD400006/B

Technology, Incorporated

1-3

ADDRESSES

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/00-7

DATA INPUT (WRITE OR
ERASE)
DATA OUTPUT (READ!

52813/52813H
machines, programmable industrial control/ers, and an
assortment of other systems. Designing the 52813 and
528 13H into eight and sixteen bit microprocessor systems is also simplified by utilizing the fast access time
with zero wait states. The addition of the latches on aI/
data, address and control inputs reduces the overhead
on the system control/er by eliminating the need for the
control/er to maintain these signals. This reduces IC
count on the board and improves the system performance. Extended temperature and military grade
versions are available.

For certain applications, the user may wish to erase the
entire memory. A chip erase is performed in the same
manner as a byte erase except that Output Enable is
between 14V and 22V. AII2K bytes are erased in under
10ms.
A characteristic of all EEPROMs is that the total number
of write and erase cycle is not unlimited. The 52 B 13 and
52813H have been designed for applications requiring
up to 10,000 write and erase cycles per byte. The write
and erase cycling characteristic is completely byte
independent. Adjacent bytes are not affected during
write/erase cycling.
A fter the device is written, data is read by applying a TTL
high to WE, enabling the chip, and enabling the outputs.
Data is available t CE time after Chip Enable is applied or
fAA time from the addresses. System power may be
reduced by placing the 528 13 or 528 13H into a standby
mode. RaiSing Chip Enable to a TTL high will reduce the
power consumption by over 60%.

Device Operation
SEEQ's 52813 and 528 13H have six modes of operation
(see Table 1) and except for the chip erase mode they
require only TTL inputs to operate these modes.
To write into a particular location of the 52813 or
52813H, that byte must first be erased. A memory location is erased by presenting the 52813 or 52813H with
Chip Enable at a TTL low while Output Enable is at TTL
high, and TTL highs (logical1s) are being presented to
all the I/O lines. These levels are latched and the data
written when write enable is brought to a TTL low level.
The erase operation requires under 10 ms. A write operation is the same as an erase except true data is
presented to the I/O lines. The 52813H performs the
same as the 52813 except that the device byte
erase/byte write time has been enhanced to 1 ms.

DITrace®
SEEQ's family of EEPROMs incorporate a DiTrace
field. The DiTrace feature is a method for storing
production flow information to wafer level in an extra
column of EEPROM cells. As each major manufacturing
operation is performed the DiTrace field is automatically updated to reflect the results of that step. These
features establish manufacturing operation traceability of the packaged device back to the wafer level.
Contact SEEQ for additional information on these
features.

The 52 B 13 is compatible to prior generation EEPROMs
which required a high voltage signal for writing and
erasing. In the 52813 there is an internal dual level
detection Circuit which allows either a TTL low or 21 V
signal to be applied to WE to execute an erase or
write operation. The 52813 specifies no restriction
on the rising edge of WE.

DiTrace is a registered trademark of SEEQ Technology, Inc.

Table 1. Mode Selection (Vee = 5V ± 10%)

~

CE
(18)

Read 111

Standbyl11
Byte Erase l21
Byte Write l21

I/O
(9-11,13-17)

OE
(20)

WE
(21)

V,L

V,L

V,H

Dour

V,H

Don't Care

V,H

High Z

V,L

V,H

V,L

DIN = V,H

V,L

V,H

V,L

DIN

Chip Erase 121

V,L

VOE

V,L

DIN = V,H

Write/Erase Inhibit

V,H

Don't Care

Don't Care

High Z

Mode

NOTES:
1. WE may be from V,H to 6V in the read and standby mode.

2. We may be at V,L (TTL WE Mode) or from 15 to 21 V (High Voltage WE Mode) in the byte erase, byte write, or chip erase mode of
the 52B13/52B13H.

seeQ

MD4000061B

Technology, Incorporated

1-4

52B13152B13H

Typical EEPROM Write/Erase Routine

Power Up/Down Considerations
SEEQ's "528" E2 family has internal circuitry to minimize false erase or write during system Vee power up or
down. This circuitry prevents writing or erasing under
anyone of the following conditions:

WAIT SUBROUTINE

1. Vcc is less than 3 v,f1'
2. A negative Write Enable transition has not occurred
when Vee is between 3 V and 5 V.
Writing will also be prevented if CE or OE are in a
logical state other than that specified for a byte write in
the mode selection table.
(Note: Data is

invalid in this
operation.)

Microprocessor Interface Circuit Example for Byte Write/Erase
:~~RESS

,....------------------------"\1

ADDRESSES

,....----------------q~

r-----------,

SYSTEM RESET

>>---------i------'">-------_....,.....r'"'\

EEPROM SELECT
MEMORY WRITE

I

)-",--TI.qWE

I
I
>">---------l-L~~L-_-_-_-_-_-_---I_..J_ ~L~OJ

)>--------+

CHi'P'SEiTcT>">-----------------------<1 CE
DATA BUS

V-----------------------v1

NOTE:
1. Characterized. Not tested.

seeQ
MD4000061B

Technology, Incorporated

1-5

1/00_7

52813152813H
Absolute Maximum Stress Ratings*
Temperature
Storage .................. -65 0 C to +1500 C
Under Bias ............... -10 0 C to +80 0 C
All Inputs or Outputs with
Respect to Ground .......... +6V to -0.3V
WE During Writing/Erasing
with Respect to Ground ...... +22.5V to -0.3V

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Recommended Operating Conditions
52813·200/·250/·350
52813 H·200/·250/·350

I Vec Supply Voltage
I Temperature Range (Aml:lient)

5 V± 10%
O°C to 70°C

Endurance and Data Retention
Symbol

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TDR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

D.C. Operating Characteristics During Read or Write/Erase
Nom. 111

Condition

(Over the operating Vcc and temperature range)

Symbol

Parameter

Max.

Unit

Test Conditions

liN

Input Leakage Current

10

f.1A

VIN = Vee Max.

10

Output Leakage Current

10

f.1A

VOUT = Vee Max.

IWE

Write Enable Leakage
Read Mode

WE = VIH

Min.

10

f.1A

TTL W/E Mode

10

fJ.A

WE= VIL

High Voltage W/E Mode

1.5

mA

WE = 22V, CE = VIL

High Voltage W/E Inhibit Mode

1.5

mA

WE = 22V, CE = VIH

Chip Erase - TTL Mode

10

fJ.A

WE= VIL

Chip Erase Mode

High Voltage
1.5

mA

WE= 22V

lee1

Vee Standby Current

15

30

mA

CE = VIH

lec2

Vee Active Current

50

80

mA

CE = OE = VIL

VIL

Input Low Voltage

-0.1

0.8

V

VIH

Input High Voltage

2

Vec

VWE

WE Read Voltage

2

Vee

+1
+1

V
V

WE Write/Erase Voltage
TTL Mode

-0.1

0.8

V

High Voltage Mode

14

22

V

VOL

Output Low Voltage

VOH

Output High Voltage

2.4

VOE

OE Chip Erase Voltage

14

Notes:
1. Nominal values are for TA

seeQ
MD400006/B

= 25

0

C and Vee

0.45
22

= 5.0V

Technology, Incorporated

1-6

V

IOL = 2.1 mA

V

10H = -400 fJ.A

V

IOE = 10 fJ.A

52813152B13H
A.C. Operating Characteristics During Read

(Over the operating Vee and temperature range)

Device
Number
Extension

52813
52813H
Min.
Max.

Unit

Test Conditions

Symbol

Parameter

tAA

Address Access Time

-200
-250
-350

200
250
350

ns
ns
ns

CE= OE= VIL

teE

Chip Enable to Data Valid

-200
-250
-350

200
250
350

ns
ns
ns

OE = VIL

tOEI11

Output Enable to Data Valid

-200
-250
-350

80
90
100

ns
ns
ns

CE= VIL

tOFI21

Output Enable to High Impedance

-200
-250
-350

0
0
0

60
70
80

ns
ns
ns

CE= VIL

tOH

Output Hold

All

0

ns

CE= OE=VIL

Capacitance/3} TA=25°C. f=1
Symbol

Parameter

A.C. Test Conditions

MHz

Max.

Unit

Conditions

CIN

Input Capacitance

10

pF

VIN =OV

COUT

Output Capacitance

10

pF

VOUT = OV

CVcc

Vee Capacitance

500

pF

OE = CE = VIH

CV WE

VWE Capacitance

10

pF

OE = CE = VIH

Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: :s; 20ns
Input Pulse Levels: 0.45 V to 2.4V
Timing Measurement Reference Level:
Inputs
1 V and 2V
Outputs 0.8V and 2V

Read Timing
ADDRESSES
VALID

ADDRESSES

HIGH Z

OUTPUT------------------~~~~------~~~~~_<

VALID OUTPUT

~----------tAA----------~

NOTES:
1. OE may be delayed to tAA -,..!Qe after the falling edge of CE without impact on tAA.
2. tOF is specified from OE or CEo whichever occurs first
3. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.

seeQ
MD400006/B

Technology, Incorporated

1-7

HIGH Z

52813152813H
A. C. Operating Characteristics During Write/Erase (Overthe operating Vcc and temperature range)
Symbol

Parameter

ts

CE, OE or AN Setup to WE

Min.
50

ns

tos

Data Setup to WE

15

ns

tHIII

WE to CE,

OE, AN or Data Change

Pulse Width
tWRI21

Units

50

ns

52B13

9

ms

52B13H

1

ms

Write Enable, WE,

t wpl11

Max.

WE to Mode Change
WE to next Byte Write/Erase Cycle

ns

50
2

WE to start of a Read Cycle

pS

52B13/52B13H High Voltage Write Specifications
Except for the functional differences noted here, the 52B 13 and 52B 13H operate to the same specifications,
including the TTL W/E mode.

52813H

52813
Max.

Min.

Symbol

Function/Parameter

twp

Write Enable Pulse Width
Byte Write/Erase

Min.

Max.

Units

9

20

1

10

ms

9

20

9

20

ms

14

22

14

22

V

Chip Erase

WE Write/Erase Voltage

VWE

High Voltage Mode

Byte Erase or Byte Write Timing

~(
I

ADDRESSES

K

DDN'TCARE

!\

V

DON'T CARE

:

Y

f\

DON'TCARE

I

VALID

:
I

I

CE

I
I
I

OE

!
I--IH-o

~18
I

I
6V

f\

I

I
I

)J

1--- I- l-iH~

108

1/0

HIGHZ

(WRITE)

1/0

(ERASE)

I
I
I

HIGHZ

,
)

I
I

VALID

I

\

I

:

I
I

1r-14~--~\-----"'"

I
I

I

I

!w.

I
WE

I

K

I
I

\

I

l/

I
I

I-!wR-.J
I

DONTCARE

NOTES:

1. After ttl, hold time, from
edge of WE.

I
I
I

j

DONTCARE

I
I

BYTE ERASEIWRITE PERIOD

.1.

I

I·

I

WE. the inputs, CE, BE, address and Data are latched and are "Don't Cares"

I

START OF NEXT MODE

until twR, write recovery time. after the trailing

2. The Write Recovery Time, tWR. is the time after the trailing edge of WE that the latches are open and able to acceptthe next mode set-up conditions. Reference
Table 1 (page 2) for mode control conditions.
i.--

seeQ
MD400006/B

Technology, Incorporated

1-8

52813152813H
Chip Erase Specifications
Symbol

Parameter

ts

CE,

Min.

tOEH

OE Hold Time

twp

WE Pulse Width

tER

Erase Recovery Time

OE Setup to WE

Max.

Units

1

p.s

1

p.s

10

ms

10

p's

Chip Erase Timing
VIH

~ ----~~~---------------~>~~~~-----I--------!WP--------.I

VWE (1) _ _ _ _ _ _ -

-

-+-~---------"""'I

-

14V

Vee ± 1V

VOE [11 -

-

-

-

-

-

-

-

-+------------.. . --,

...

--14V
Vee± 1V

NOTES:
1. VWE and VOE can be from 15V to 21 V in the high voltage mode for chip erase on 52813.

Ordering Information

r I

D Q 52813 H-200

1

PACKAGE
TYPE

D-CERAMIC DIP
P-PLASTIC DIP
UX- UNENCAPSULATED DIE

seeQ
MD400006/B

T------.T
____

TEMPERATURE
RANGE

PART TYPE

EEPROM BYTE WRITE TIME

ACCESS TIME

Q-O°C to + 70°C
(Commercial)

2K x 8 EEPROM

(Blank)- Standard Write Time
H- Fast Write Time

200-200 ns
250-250 ns
350-350 ns

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----J

1-9

1-10

seeQ

52B33/52B33H

64K Electrically Erasable PROM
October 1987

Features

Description

• High Write Endurance Over Temperature
Range
- 52B33/52B33Hi 10,000 cycles/byte
minimum

SEEQ's52833 isa8192 x8 bit, 5 volt electrically erasable
programmable read only memory (EEPROM) which is
specified over a ooe to 70 e temperature range. Data
retention is specified to be greater than 10 years. The
device has input latches on all addresses, data, and
control (chip and output) lines. Data is latched and electrically written by a TTL pulse on the Write Enable pin.
Once written there is no limit to the number oftimes data
may be read. The erasure time is under 10 ms, and each
byte may be erased and written a minimum of 10,000
times. For applications requiring a faster byte write or
erase time, a 52833H is available at 1 ms, giving a 10
times speed increase.
0

• Input Latches
• Fast TTL Byte Write Time
- 1 ms for 52B33H
- 9 ms for 52B33
.5 V± 10% Vcc
• Power Up/Down Protection
• 200 ns Read Access Time
• DiTrace®
• Infinite Number of Read Cycles
• JEDEC Approved Byte Wide Memory Pinout

(continued on next pagel

• Military And Extended Temperature Range
Available

Pin Configuration

Block Diagram

CC

Vee

A12

WE
N/C

A7
COLUMN
ADDRESS
LATCHES

ROW
ADDRESS
LATCHES

COLUMN
ADDRESS
DECODE

ROW
ADDRESS
DECODE

E2
MEMORY
ARRAY

Aa

As

As

A9

A4

A11

A3

OE

A2

A10

A1

CE

Ao

1107

1/ 0 0

1I0a

1101

1/05

1/02

1/04

GND

1/03

WRITE/ERASE ENABLE

Pin Names
Ao-A4

ADDRESSES- COLUMN (LOWER ORDER BITS)

As-A12

ADDRESSES- ROW

CE

1/00-7

seeQ
MD40000B/A

Technology, Incorporated

1-11

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/00·7

DATA INPUT (WRITE OR ERASE), DATA OUTPUT (READ)

cc

CHIP CLEAR

N/C

NO CONNECT

52B33152B33H
Write
To write in to a particular location, that byte must first
be erased. A memory location is erased by having
valid addresses, Chip Enable at a TTL low, Output
Enable at TTL high, and TTL highs (logical 1 's) presented to all the 110 lines. Write Enable is then brought
to a TTL low level to latch all the inputs and I/O lines.
All inputs can be released after the write enable hold
time (tH) and the next input conditions can be established while the byte is being erased. During this
operation, the write enable must beheld at a TTL low
for 9 ms (twp). A write operation is the same as an
erase except true data is presented to the I/O lines.
The 52833H performs the same as the 52833 except
that the byte eraselbyte write time has been enhanced
to 1 ms.

The pin configuration is to the JEDEC approved byte
wide memory pinout. EEPROMs are ideal for applications that require a non-volatile memory with
in-system write and erase capability. Dynamic configuration (the alteration of opening software in
real-time) is made possible by EEPROMs. Applications
will be found in military avionics systems, programmable character generators, self-calibrating
instrument/machines, programmable industrial controllers, and an assortment of other systems.
Designing the EEPROMs into these systems is simplified because of the fast access time and input latches.
The specified 200 ns access time eliminates or reduces the number of microprocessor wait states. The
addition of the latches on all data, address and control inputs reduces the overhead on the system
controller by eliminating the need for the controller to
maintain these signals. This reduces IC count on the
board and improves the system performance.

Chip Clear
Certain applications may require all bytes to be
erased simultaneously. See A. C. Operating Characteristics for TTL chip erase timing specifications.

DITrace®
SEEQ's family of EEPROMs incorporate a DiTrace
field. The DiTrace feature is a method for storing
production flow information in an extra row of EEPROM
cells. As each major manufacturing operation is performed the DiTrace field is automatically updated to
reflect the results of that step. These features establish
manufacturing operation traceability of the packaged
device back to the wafer level. Contact SEEQ for
additional information on these features.

Device Operation
SE EQ's 52833 has six modes of operation (see Table 1)
and requires only TTL inputs to operate these modes.
The "H" members of the family operate in the same
manner as the other devices except that a faster write
enable pulse width of 1 ms is specified during byte erase
or write.

Power Up/Down Considerations
SEEQ's "528" E2 family has internal circuitry to minimize false erase or write during system Vee power up
or down. This circuitry prevents writing or erasing
under anyone of the following conditions:
1. Vec is less than 3 VJ11
2. A negative Write Enable transition has not occurred
when Vee is between 3 V and 5 V.

Read
A read is accomplished by presenting the address of
the desired byte to the address inputs. Once the
address is stable, CE is bought to a TTL low in order
to enable the chip. The write enable (WE) pin must be
at a TTL high during the entire read cycle. The output
drivers are made active by bringing output enable
(OE) to a TTL low. During read, the address, CE, OE,
and I/O latches are transparent.

Mode Selection

Writing will also be prevented if CE or OE are in a
logical state other than that specified for a byte write
in the mode selection table.

(Table 1)

~n
Mode
(Pin)

CE

(20)

CC
(1)

OE

WE

(22)

(27)

I/O
(11-13,15-19)

Read

VIL

VIH

VIL

VIH

DOUT

Standby

VIH

Don't Care

Don't Care

Don't Care

HighZ

Byte Erase

VIL

VIH

VIH

VIL

DIN - VIH

Byte Write

VIL

VIH

VIH

VIL

DIN

Chip Clear

VIL

VIL

VIH

VIL

VIL orVIH

Write/Erase Inhibit

VIH

Don't Care

Don't Care

Don't Care

HighZ

NOTE:
1. Characterized. Not tested.

seeQ
MD40000B/A

DiTrace is a registered trademark of SEEQ Technology, Inc.

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....J

1-12

52B33152833H
Absolute Maximum Stress Rating*
Temperature
Storage ..... ................... -65°C to +100
Under Bias ...................... -10°C to +80

0
0

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

e
e

All Inputs or Outputs with
Respect to Ground . ................ +6V to -O.3V

Recommended Operating Conditions
52833,52833H

I Vcc Supply Voltage
I Temperature Range (Ambient)

5 V± 10%
O°C to lO°C

Endurance and Data Retention
Symbol

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TDR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

D.C. Operating Characteristics During Read or Erase/Write

Condition

(Over the operating Vee and temperature range)

Symbol

Parameter

Max.

Unit

Test Conditions

liN

Input Leakage Current

10

J.l.A

VIN = Vee Max.

10

Output Leakage Current

10

J.l.A

VOUT = Vee Max.

IWE

Write Enable Leakage

10

J.l.A

WE=VIL

Min.

Nom.

lee1

Vee Standby Current

18

40

mA

CE=VIH

ICC2

Vcc Active Current

60

110

mA

CE= OE=VIL

VIL

Input Low Voltage

-0.1

0.8

V

VIH

Input High Voltage

2

Vcc+ 1

V

VOL

Output Low Voltage

0.45

V

IOL=2.1 mA

VOH

Output High Voltage

V

10H = -400 J.l.A

Notes:
1. Nominal values are for TA

seeQ
MD40000B/A

2.4

= 25° C and Vcc = 5.0 V

Technology, Incorporated

1-13

52833152833H
A C Operating Characteristics During Read (Over the operating Vcc and temperature range)
Device
Number
Extension

52833
52833H
Min.
Max.

Symbol

Parameter

tAA

Address Access Time

-200
-250
-350

200
250
350

Unit
ns
ns
ns

CE= OE= VIL

Test Conditions

tCE

Chip Enable to Data Valid

-200
-250
-350

200
250
350

ns
ns
ns

OE= VIL

tOE I1 ]

Output Enable to Data Valid

-200
-250
-350

80
90
100

ns
ns
ns

CE= VIL

tOF[2]

Output Enable to High
Impedance

-200
-250
-350

0
0
0

60
70
80

ns
ns
ns

CE= VIL

tOH
CIN/
Coutl3]

Output Hold
Input and Output
Capacitance

All
All

0
10

ns
pF

CE= OE= VIL
VIN= 0 Vfor
CIN, VOUT = 0 V
for COUT,
TA = 25°C

Read Cycle Timing
ADDRESSES
VALID

ADDRESSES

HIGH Z

OUTPUT--------------------~----------------~~_+~~~

1-------- tAA

HIGH Z

-------I~

NOTES:

1. DE may be delayed to tAA - tOE after the falling edge of CE without impact on tAA·
2. tOF is specified from DE or CE, whichever occurs first
3. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
4. AftertH, hold time, from WE, the inputs CE, QE,
Address and Data are latched and are"Don't Cares" until t WR, Write Recovery Time, after the
trailing edge of WE.
5. The Write RecoveryTime, twr, is the time after the trailing edge of WE that the latches are open and able to accept the next mode set-up conditions.
Reference Table 1 (page 2) for mode control conditions.

ce,

seeQ
MD400008/A

Technology, Incorporated

1-14

52B33152B33H
A.C. Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: :::;20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs O.B V and 2 V

A.C. Operating Characteristics During Write/Erase (Over the operating Vee and temperature range)
Max.

Min.

Symbol

Parameter

ts

CE, OE or Address Setup to WE

50

ns

tos
tH[4j

Data Setup to WE

15

ns

WE to CE, OE, Address or Data Change

50

ns

Write Enable (WE) Pulse Width
Byte Modes - 52833

9

twp

tWR[5]

ms

1

Byte Modes - 52B33H·
WE to Mode change
WE to Start of Next Byte Write Cycle
WE to Start of Read Cycle

Units

50

ns

1

f.,Ls

Byte Erase or Byte Write Cycle Timing

}<~

ADDRESSES

K

DON'T CARE

V

DON'T CARE

VALID

I

I

I

I

!\

CE

I

I

I
I

I

Y

1\

DON'T CARE

I
I

I--tH-

I

-r

I

I

I
OE

I

Is

twp

I

WE------------~--~

I
I

twR-l
[

I

1/0 ________
HI_G_H_Z__~

(WRITE MODE)

I
I
I

1/0 _______H_I..;.G_H_Z~~
iERASE MODE)

I
I

i + - - - - - - B y T E ERASEIWRITE PERIOD-----.I.,I.>--START OF NEXT MODE

I

(Notes 4 and 5 are on previous page)

seeQ

MD40000B/A

Technology, Incorporated

1-15

52B33152B33H
A. C. ODerating Characteristics During Chip Erase (Dverthe operating Vee and temperature range)
Symbol

Parameter

is

CC, CE DE Setup to WE

50

tH (4)

WE to CE, DE, CC change

50

ns

twp

Write Enable (WE) Pulse Width
Chip Erase - 52B33
Chip Erase - 52B33H

10

ms

tWR[51

WE to Mode change
WE to Start of Next Byte Write Cycle

50

ns

Min.

WE to Start of Read Cycle

CE

OE

WE ------------~~~

NOTE: Address, Data are don't care during Chip Erase.

MD40000B/A

Unite
ns

JLS

TTL Chip Erase Timing

~seeQ

Max.

Technology, Incorporated

1-16

52833152833H
Microprocessor Interface Circuit Example for Byte Write/Erase

~~~RESS c=====================~~ ADDRESSES

,----------------------------q~

r----------i

SYSTEM RESET

>>------------------j--------I-
EEPROM SELECT
MEMORY WRITE

»

WE

>>-----------------~ILr-:I~L--_--_--_--_-_--_--I_L.....I_ ~L_~O ~
L!4~3~

CHIPSELECT

DATA BUS

>,>-------------------------------------------~~

,,-----------------------------------------------,/1

1i00-7

NOTE:
ALL SIGNALS MUST SATISFY THE RELATIONSHIPS INDICATED BY THE
TIMING DIAGRAMS SHOWN ON PAGES 4 AND 5. EEPROM SELECT IS
DERIVED FROM THE CHIP SELECT SIGNALS OF ALL DEVICES FOR
WHICH THIS CIRCUIT GATES WE. THIS MAY ENTAIL A SIMPLE OR
FUNCTION. IN CASE OF A SINGLE EEPROM, THE TWO SIGNALS WOULD
BE COMMON.

Typical EEPROM Write/Erase Routine
WAIT SUBROUTINE

(Note: Data is
invalid in this
operation)

Ordering Information

PACKAGE

~

RANGE

PART TYPE

EEPROM BYTE WRITE TIME

ACCESS TIME

D-CERAMIC DIP
P- PLASTIC DIP
UX - UNENCAPSULATED DIE

Q=0·CT070·C
(COMMERCIAL)

8Kx8 EEPROM

(BLANK) = STANDARD WRITE TIME
H
= FAST WRITE TIME

200- 200 ns
250= 250 ns
350= 350 ns

seeQ
MD40000B/A

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1

1-17

1-18

seeQ

2804A
Timer ~
4K Electrically Erasable PROM

PRELIMINARY DATA SHEET

October 1988

Features

Description

• High Endurance
- 10,000 Cycles/Byte Minimum
• On-Chip Timer
- Automatic Erase and Write Time Out
• AI/Inputs Latched by Write or Chip Enable
• Direct Replacement to 512 x 8 EEPROMS
• 5 V ± 10% Power Supply
• Power Up/Down Protection Circuitry
• 250 ns max. Access Time
• Low Power Operation
- 80 mA max. Active Current
- 40 mA max. Standby Current
• 10 Year Data Retention
• JEDEC Standard Byte-Wide Pinout

SEEQ's 2804A is a 5 V only, 512 x 8 electrically
erasable programmable read only' memory
(EEPROM). EEPROMs are ideal for applications
which require non-volatility and in-system data
modification. The endurance, the number of times
that a byte may be written, is 10 thousand cycles
for the 2804A
This device has an internal timer that automatically
times out the write time. A separate erase cycle is
not required and the minimum write enable (WE)
pulse width needs to be only 150 ns. The on-chip
timer, along with the inputs being latched by a
write or chip enable signal edge, frees the microcomputer system for other tasks during the write
time. The write time is 10 ms. Once a byte is written,
it can be read in 250 ns. The inputs are TTL for both
the byte write and read mode.
(Continued on page 2)

Block Diagram

COLUMN
ADDRESS
LATCHES

Pin Configuration

COLUMN
ADDRESS
DECODE

A7

'Vee

As

As

As

NC

A4

WE
Oe

A3
A2

NC

Al

CE
1/07

AS-AS

ROW
ADDRESS
LATCHES

ROW
ADDRESS
DECODE

1/06

E2
MEMORY
ARRAY

1/01

1/05

GND

1/03

1/04

Pin Names

CE

AO-A4

OE

COLUMN ADDRESSES

A5- AS

ROW ADDRESSES

~

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/00-7

DATA INPUT (WRITE)
DATA OUTPUT (READ)

1/°0-7

Q Cell is a trademark of SEEQ Technology, Inc.

seeQ
MD400019/B

Technology, Incorporated

--------------------------~
1-19

2804A
PRELIMINARY DATA SHEET

Device Opera tion

Mode Selection (Table 1)

There are four op erational modes (see Table 1)
and only TTL inpu ts are required. To write into a
particular location, a TTL low is applied to the
write enable (WE) pin of a selected (CE low)
device. This, com bined with output enable (OE)
being high, initiates a write cycle. During a byte write
cycle, addresses are latched on the last falling
edge of CE or WE and data is latched on the first
rising edge of CE or WE An internal timer times
out the required byte write time. An automatic byte
erase is performed internally in the byte write mode.
The 2804A ignores attempts to read or write while
the internal write cycle is in progress.

I/O

VIH

DouT

Standby

VIH

X

X

HIZ

Byte Write

VIL

VIH

VIL

DIN

X
X

VIL
X

X
VIH

HI Z/DouT
HI Z/DouT

The 2804A has internal circuitry to minimize a
false write during system Vcc power up or down.
This circuitry prevents writing under anyone of
the following conditions.
1. Vcc is less than 3 v. lt ]
2. A negative Write Enable (WE) transition has not
occurred when Vcc is between 3 V and 5 V.
Writing will also be prevented if CE or OE are in a
logical state other than that specified for a byte
write in the Mode Selection table.
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

2804A
5 V± 10%

WE

VIL

Power Up/Down Considerations

Recommended Operating Conditions

Vcc Supply Voltage

OE

VIL

X - Any TTL Level.

Temperature
Storage ........ ........... -65°C to +150°C
Under Bias .... ............. -10°C to +80°C
All Inputs or Outp uts with
Respect to Grou nd . ........... +6V to -O.3V

(Ambient) O°C to 70°C

CE

Read

Write
Inhibit

Absolute MaXI"mum Stress Ratings*

Temperature Range

MODE

Endurance and Data Retention
Condition

Parameter

Value

Units

N

M inimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TOR

0 ata Retention

>10

Years

MIL-STD 883 Test
Method 1008

Symbol

DC Operating Characteristics TA=O° to 70°C; Vcc=5 V± 10%, unless otherwise noted.
Limits
Symbol

Parameter

Max.

Unit

Test Condition

Icc

Active Vcc Current

80

mA

CE=OE7'VIL; All I/O open;
Other Inputs = 5.5 V

IS8

Standby Vcc Current

40

mA

CE=VIH, OE=VIL; All I/O's
Open; Other Inputs = 5.5 V

ilL

Input Leakage Current

10

p.A

VIN=5.5 V

10L

Output Lea kage Current

10

p.A

VouT=5.5 V

VIL

Input Low Voltage

-0.1

0.8

V

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output Hig h Voltage

NOTE:
1. Characterized.

'--

Min.

2.4

Not tested

seeQ
MD4000191B

1-20

6

V

0.4

V

IOL=2.1 mA

V

IOH=-400 p.A

2804A

AC Characteristics
Read Operation TA=O° to 70°C; Vcc=5 v ±

PRELIMINARY DATA SHEET
10%, unless otherwise noted.
limits
2804A-300

2804A-250
Symbol

Parameter

Min.

tRC

Read Cycle Time

250

tCE

Chip Enable Access Time

250

300

ns

tAA

Address Access Time

250

300

ns

tOE

Output Enable Access Time

90

100

ns

tu

CE to Output in Low Z

tHZ

CE to Output in HI Z

100

ns

Max.

Min.

10

OE to Output in Low Z
OE to Output in HI Z
Output Hold from Address Change

20

20

tpu(11

CE to Power-up Time

0

0

tPD(11

CE to Power Down Time

Max

Data (I/O) Capacitance

VZAP(11

10 pF

Value

ns
ns

50

Conditions

VIIO=OV

Test Conditions

MIL-STD 883
>2000 V Test Method 3015

E.S.D. Tolerance

ns
ns

50

E. S. D. Characteristics
Symbol Parameter

100

100

6 pF VIN= OV

COUT

ns

50

50

MHz

Symbol Parameter
Input Capacitance

ns

100

toHZ
toH(11

CIN

ns

10

tou

Capacitance[2] TA=25°C, f=1

Units

Max.

300

A. C. Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: <20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V

Read Cycle Timing
IRC

ADDRESS

=:J.

IAA
IAA

ICE

....

\

/

"'rI--IOE-

\

/

~

r
!---tOHZ-

I--loLz DATA OUT

]

HIGHZ

I--IHZ-

_ IOH -

.)
_ILZ-

~

-[

DATA VALID

~-

~:

DATA VALID

..,

_Ipu

Vcc
SUPPLY
CURRENT

Ise

!

-r-

Icc

NOTES:

_ I po

L

1.Characterized Not tested
2. This parameter measured only for the initial qualification and after process or design changes which may affect capacitance.

seeQ----------------------~

MD4000191B

1-21

2804A
PRELIMINARY DATA SHEET

AC Characteristics
TTL WRITE CYCLE TA=O° to 70°C; Vcc=5

v±

10%, unless otherwise noted.
2804A-250
Max.

Min.

Max.

Units

10

ms

Parameter

twc

Write Cycle Time

tAS

Address Set Up Time

10

10

ns

tAH

Address Hold Time

50

70

ns

tcs

Write Set Up Time

0

0

ns

tCH

Write Hold Time

0

0

ns

tcw

CE to End of Write Input

150

150

ns

tOES

OE Set Up Time

10

10

ns

tOEH
t wp l1)

OE Hold Time

10

10

ns

WE Write Pulse Width

150

150

ns

Data Latch Time

50

50

tOL
toV(2)

Min.

2804A-300

Symbol

10

Data Valid Time

ns
1

1

J.ls

tos

Data Set Up Time

50

50

ns

tOH

Data Hold Time

0

0

ns

NOTES:
1. WE is noise protected Less than a 20 ns write pulse will not activate a write cycle.
2. Data must be valid within 1 p.s maximum after the initiation of a write cycle. Characterized, not tested.

TTL Byte Write Cycle
WE CONTROLLED WRITE CYCLE

CE CONTROLLED WRITE CYCLE
J-------twc-------t

ADDRESS

DATA IN

seeQ
MD4000191B

1-22

2804A
PRELIMINARY DATA SHEET

Ordering Information

o

1

Q

2804A - 250

r~

PACKAGE
TYPE

TEMPERATURE
RANGE

PART TYPE

ACCESS TIME

D- CERAMIC DIP

Q-O·C TO +70·C
(COMMERCIAL)

512 x 8 EEPROM

250-250 ns
300-300 ns

P- PLASTIC DIP

seeQ----------------------~
1-23

MD400019/B

1-24

seeQ

2816A/5516A

Timer ~
16K Electrically Erasable PROMs
October 1988

Features

Description

• High Endurance Write Cycles
- 5516A: 1,000,000 Cycles/Byte Minimum
- 2816A: 10,000 Cycles/Byte Minimum
• On-Chip Timer
- Automatic Erase and Write Time Out
- 2 ms Byte Write Time (2816AH)
• AI/Inputs Latched by Write or Chip Enable
• 5 V ± 10% Power Supply
• Power Up/Down Protection Circuitry
.200 ns max. Access Time
• Low Power Operation
- 110 mA max. Active Current
- 40 mA max. Standby Current
• JEDEC Approved Byte-Wide Pinout
• Military and Extended Temperature
Range Available.

SEEQ's5516A and2816A are 5 V only, 2Kx8 electrically erasable programmable read only memories
(EEPROMs). EEPROMs are ideal for applications
which require non-volatility and in-system data
modification. The endurance, the minimum number
of times that a byte may be written, is 1 million for
the 5516A and 10 thousand for the 2816A. The
5516A's extraordinary high endurance was
accomplished using SEEQ's proprietary oxyntride
EEPROM process and its innovative Q Cel/T M
design. The 5516A is ideal for systems that
require frequent updates.
Both EEPROMs have an internal timer that
automatically times out the write time. A separate
erase cycle is not required and the minimum write
enable (WE) pulse width needs to be only 150 ns.
The on-chip timer, along with the inputs being
latched by a write orchip enable Signal edge, frees
the microcomputer system for other tasks during
the write time. The standard 2816A and 5516A's
write time is 10 ms, while the 2816AH's write time

Block Diagram

(continued on next page)

COLUMN
ADDRESS
LATCHES

Ao-4

A5-10

ROW
ADDRESS
LATCHES

Pin Configuration

COLUMN
ADDRESS
DECODE

ROW
ADDRESS
OECOOE

E2
MEMORY
ARRAY

A7

Vcc

As

As

A5

Ag

A4

WE

A3

OE

A2

AlO

Al

CE

Ao

1107

1100

1I0s

1101

1105

1102

1104

GND

1103

Pin Names
AO-Al0

Q Cell is

a trademark of SEEQ Technology, Inc.

seeQ

MD4000161B

1/00-7

Technology, Incorporated

1-25

ADDRESSES

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/00-7

DATA INPUT(WRITE OR
ERASE)
DATA OUTPUT (READ)

2816AI5516A
is a fast 2 ms. Once a byte is written, it can be read
in 200 ns. The inputs are TTL for both the byte
write and read mode.

Mode Selection (Table 1)
Mode

CE

OE

WE

1/0

Read

VIL

VIL

VIH

DouT

Device Operation

Standby

VIH

X

X

HighZ

There are five operational modes (see Table 1) and,
except for the chip erase mode{2~ only TTL inputs are
required. To write into a particular location, a TTL low
is applied to the write enable (WE) pin of a selected
(CE low) device. This, combined with output enable
(OE) being high, initiates a write cycle. During a byte
write cycle, addresses are latched on the last falling
edge of CE or WE and data is latched on the first rising
edge of CE or WE. An internal timer times out the
required byte write time. An automatic byte erase is
performed internally in the byte write mode.

Byte Write

VIL

VIH

VIL

DIN

Write
Inhibit

X
X

VIL

X

X

VIH

High Z/DouT
High Z/DOUT

X: any TTL level

Power Up/Down Considerations
The 2816A/5516A has internal circuitry to minimize a
false write during system Vcc power up or down. This
circuitry prevents writing under anyone of the following conditions.
1. Vee is less than 3 v.[3J
2. A negative Write Enable (WE) transition has not
occurred when Vcc is between 3 V and 5 V.

Writing will also be prevented if CE or OE are in a
logical state other than that specified for a byte write in
the Mode Selection table.

Absolute Maximum Stress Ratings*
'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.

Temperature
Storage ................... -65°C to +150°C
Under Bias ................. -10°C to +80°C
AI/Inputs or Outputs with
Respect to Ground ............ +6V to -0.3V

Recommended Operating Conditions
5516A15516AH
2816A12816AH

l
I

Temperature Range (Ambient)
Vee Supply Voltage

O°C to 70°C
5 V± 10%

Endurance and Data Retention
Symbol

Parameter

N

Minimum Endurance
Data Retention

TDR

Units
Cycles/Byte

MIL-STD 883 Test
Method 1033

>10

Years

MIL-STD 883 Test
Method 1008

NOTES:
1.5516A·l million cycles/byte.
2. Chip Erase is an optional mode.
3. Characterized. Not tested.

seeQ

MD4000161B

Condition

Value
10,000
1,000,000 II]

Technology, Incorporated

1-26

2816AI5516A
DC Operating Characteristics

TA=O° to 70o e, Vcc=5

v±

10% unless otherwise noted

Limits
Symbol

Parameter

Max.

Units

lee

Active Vee Current

110

rnA

CE = OE = VIL; All I/O Open;
Other Inputs = 5.5 V

ISB

Standby Vee Current

40

rnA

CE = VIH, OE = VIL; All I/O's
Open; Other Inputs = 5.5 V

Min.

Test Condition

= 5.5 V
= 5.5 V

III

Input Leakage Current

10

f.lA

VIN

ILO

Output Leakage Current

10

f.lA

VOUT

VIL

Input Low Voltage

-0.1

0.8

V

VIH

Input High Voltage

2.0

6

V

VOL

Output Low Voltage

0.4

V

IOL

VOH

Output High Voltage

V

IOH

2.4

= 2.1 rnA
= -400 f.lA

AC Characteristics
Read Operation TA=O° to 70°C, Vcc=5 V ±

10%, unless otherwise noted
Limits

5518A/5518AH·200 5518A/5518AH·25Cl 5518A/5518AH·300
2818A/2818AH·200 2818A/2818AH·25Cl 2818A/2818AH·300

Parameter

Min.

tRC

Read Cycle Time

200

teE

Chip Enable Access Time

200

250

300

350

ns

tM

Address Access Time

200

250

300

350

ns

tOE

Output Enable Access Time

90

90

100

100

tLZ

~ to Output in Low Z

Max.

Min.

2818A·350

Symbol

Max.

250

10

Min.

Max.

Max.

10

10

Units
·ns

350

300

10

Min.

ns
ns

tHZ

CE to Output in High Z

toLZ

OE to Output in Low Z

10Hz

OE to Output in High Z

toHlll
tpu ll1

Output Hold from Addr Change

20

20

20

20

ns

CE to Power-up Time

0

0

0

0

ns

tpolll

CE to Power Down Time

Capacitance l2] TA=25°C, f=1

100
50

50

CIN
COUT

Data (I/O) Capacitance

Conditions

10 pF Vl/o=OV

E. S. D. Characteristics
Symbol

Parameter

VZApl l l

E.S.D. Tolerance

Value
>2000 V

100

50

ns
ns

100

50

ns

ns

A.C. Test Conditions

MHz

6 pF VIN=OV

Input Capacitance

50

100
50

50
100

100

Max

Symbol Parameter

100

100
50

Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: <20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V

Test Conditions
MIL-STD883
Test Method 3015

NOTES:
1. Characterized. Not tested.
2. This parameter measured only for the initial qualification and after process or design changes which may affect capacitance.

seeQ
MD400016/B

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - '

1-27

2816AI5516A
Read Cycle Timing
IRC

ADDRESS

J:

~,..
IAA
ICE

1M
~~

\

/
I-IOE-

\

-

J

-'~

f--JOHZ-

I--I 0lZ -

DATA OUT

HIGHZ

J
j
_ILZ _
_ l
pU

ISB

-IOH-

~

!

VCC

SUPPLY
CURRENT

-

I-IHZ-

~K

DATA VALID

]:

-

DATA VALID

-r-

Icc

L

_lpO

AC Characteristics
Write Operation

TA=O° to 70°C, Vcc=5

v±

10% unless otherwise noted

Limits
55181-200
28181/28181H-200

Symbol
twc

Parameter
Write Cycle Time

Min.
5516AH/2816AH
5516N2816A

55181-250
28181/28181H-250

55181-300
28181/28181H-300

Max.

Min.

2

2

2

-

10

10

10

Max.

Min.

Max.

Min.

28181-350

Max.

-

Units
ms

10

tAS

Address Set Up Time

10

10

10

10

tAH

Address Hold Time

50

50

70

70

ns

tcs

Write Set Up Time

0

0

0

0

ns

ns

0

0

0

0

ns

150

150

150

150

ns

OE Set Up Time

10

10

10

10

ns

OE Hold Time

10

10

10

10

ns

WE Write Pulse Width

150

150

150

150

ns

Data Latch Time

50

50

50

50

tCH

Write Hold Time

tcw

CE to End of Write Input

tOES
tOEH
twp[11
tOl
tov[21

Data Valid Time

tos

Data Set Up Time

50

50

50

50

ns

tOH

Data Hold Time

0

0

0

0

ns

Notes:
1. WE is noise prolected. less than a 20 ns write pulse will not activate a write cycle.
2. Data must be valid within 1 P.s maximum after the initiation of a write cycle.

seeQ

MD400016/B

1

1

1

Technology, Incorporated

1-28

ns
1

ILs

2816AI5516A
TTL Byte Write Cycle
WE CONTROLLED WRITE CYCLE

CE CONTROLLED WRITE CYCLE

ADDRESS

DATA IN

Ordering Information

r I
o
o

1

PACKAGE
TYPE

D-CERAMIC DIP
P- PLASTIC DIP
UX- UNENCAPSULATED DIE

seeQ

Q
Q

5516A -200
2816A H-200

1"--------,:=
_______

TEMPERATURE
RANGE

PART TYPE

EEPROM BYTE WRITE TIME

ACCESS TIME

Q-O·C to + 70·C
(Commercial)

2Kx8 EEPROM

(Blank) - Standard Write Time
H - Fast Write Time

200 - 200
250 - 250
300-300
350-350

ns
ns
ns
ns

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - '

MD400016/B

1-29

1-30

seeQ

2817A/5517A
Timer e
16K Electrically Erasable PROMs
October 1988

Features
• Ready/Busy Line for End-of-Write
• High Endurance Write Cycles
- 5517A: 1,000,000 Cycles/Byte Minimum
-2817A: 10,000 Cycles/Byte Minimum
• On-Chip Timer
- Automatic Byte Erase Before Byte Write
- 2 ms Byte Write Time (2817AH)
• AI/Inputs Latched by Write or Chip Enable
• 5 V ± 10% Power Supply
• Power Up/Down Supply
• 200 ns max. Access Time
• 10 Year Data Retention for Each Write
• JEDEC Approved Byte-Wide Pinout
• Military and Extended Temperature Range
Available

Description
SEEQ's5517Aand2817A are5Vonly, 2Kx8 electrical/y erasable programmable read only memories
(EEPROMs). They are packaged in a 28 pin package
and have a ready/busy pin. These EEPROMs are
ideal for applications which require non-volatility

and in-system data modification. The endurance,
the minimum number of times which a byte may be
written, is 1 million for the 5517A and 10 thousand
for the 2817A The 5517A's extraordinary high
endurance was accomplished using SEEQ's proprietary oxynitride EEPROM process and its innovative
Q Ce/fT M design. The 5517A is ideal for systems that
require frequent updates and/or high reliability.
System reliability is enhanced greatly over lower
specified endurance EEPROMs while still maintaining 10 year data retention.
Both EEPROMs have an internal timer that automatically times out the write time. The on-chip timer, along
with the input latches, frees the microcomputer system for other tasks during the write time. The standard
5517A/2817A's write time is 10 ms, while the
2817AH's write time is a fast 2 ms. An automatic
byte erase is performed before a byte operation is
started. Once a byte has been written, the ready/
busy pin signals the microprocessor that it is available for either a write or read mode. The inputs are
TTL for both the byte write and read mode. Data
retention is specified for 10 years.

Pin Configuration
Block Diagram

RDY/BuSv

Vcc
WE

NC
A7

NC

As

As

AS

A9

A4

NC

1.3

DE

A2

A10

A1

CE

Ao

1/07

1/00

I/OS

1/01

I/OS

1/02

1/04

GND

1/ 0 3

Pin Names
.--

Q Cell is

a trademark of SEEQ Technology, Inc.

Ao-AlO

ADDRESSES

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/00 _7

DATA INPUT(WRITE OR ERASE)
DATA OUTPUT (READ)

RDY/BUSY

DEVICE READY/BUSY

NC

NO CONNECT

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

--1

MD400014/B

1-31

2817AI5517A
Device Opelatlon

Power Up/Down Cons/delations

There are five operational modes (see Table 1) and,
except for the chip erase mode{2~ only TTL inputs are
required. To write into a particular location, a TTL
low is applied to the write enable (WE) pin of a
selected (CE low) device. This, combined with output enable (OE) being high, initiates a write cycle.
During a byte write cycle, addresses are latched on
either the falling edge of CE or WE, whichever one
occurred last. Data is latched on the rising edge of
CE or WE, whichever one occured first. The byte is
automatically erased before data is written. While the
write operation is in progress, the ROY/BUSY output
is at a TTL low. An internal timer times out the
required byte write time and at the end of this time,
the device signals the ROY/BUSY pin to a TTL high.
The RDY/BUSY pin is an open drain output and a
typical3K n pull-up resistor to Vce is required. The
pull-up resistor value is dependent on the number of
OR-tied 2817A ROY/BUSY pins.

The 2817A/5517A has internal circuitry to minimize a
false write during system Vce power up or down.
This circuitry prevents writing under anyone of the
following conditions.
1. Vee is less than 3 v.[3]
2. A negative Write Enable (WE) transition has not
occurred with Vec is between 3 V and 5 V.
Writing will also be prevented if CE or OE are in TTL
logical states other than that specified for a byte
write in the Mode Selection table.

Absolute Maximum Stress Ratings*
Temperature
Storage .................... -65°C to +150°C
Under Bias .................. -10°C to +80°C
AI/Inputs or Outputs with
Respect to Ground ............. +6V to -0.3V

Mode Selection (Table 1)
Mode/Pin

CE

OE

WE

Read

VIL

VIL

VIH

DouT

HighZ

Standby

VIH

X

X

HighZ

HighZ

Byte Write

VIL

VIH

VIL

DIN

VOL

X
X

VIL
X

X
VIH

High Z/DouT
High Z/DouT

HighZ
HighZ

Write
Inhibit

'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device
reliability.

ROY/BUSY

I/O

X: Any TTL level

Recommended Operating Conditions
5517A
2817 A/2817 AH

I
I

5 V± 10%

Vcc Supply Voltage
Temperature Range (Ambient)

O°C to 70°C

Endurance and Data Retention
Parameter

Symbol

N

Minimum Endurance

TOR

Data Retentiol"l

Value

Units

10,000
1,000,00011)

Cycles/Byte

Condition
MIL-STD 883 Test
Method 1033

> 10

Years

MIL-STD 883 Test
Method 1008

NOTES:
1. 5517A - 1 million cycleS/byte.
2. Chip Erase Is an optional mode.
3. Characterized Not tested.

seeQ
MD400014/B

Technology, Incorporated

----------------------------~
1·32

2817A/5517A
D.C. Operating Characteristics

(Over the operating Vee and temperature range)
Limits

Symbol

Parameter

Max.

Units

Icc

Active Vcc Current
(includes Write Operation)

110

mA

CE = OE = VIL; All I/O Open;
Other Inputs = 5.5 V

ISB

Standby Vcc Current

40

mA

CE = VIH, OE = VL All I/O
Open; Other Inputs = 5.5 V

III

Input Leakage Current

10

JlA

VIN = 5.5 V

ILO

Output Leakage Current

10

JlA

VOUT = 5.5 V

VIL

Input Low Voltage

-0.1

0.8

V

VIH

Input High Voltage

2.0

Vcc+ 1

V

VOL

Output Low Voltage

0.4

V

IOL = 2.1 mA

VOH

Output High Voltage

V

IOH = -400 JlA

Min.

2.4

A. C. Characteristics
Read Operation (Over the operating Vee

Test Condition

and temperature range)
Limits

2817AH-200
2817A-200

2817AH-250
5517A-250
2817A-250

2817AH-300
5517A-300
2817A-300

Min.

Min.

Symbol

Parameter

Min.

tRC

Read Cycle Time

200

tCE

Chip Enable Access Time

200

250

300

tAA

Address Access ·Time

200

250

tOE

Output Enable Access Time

75

tOF

Output F.nable High
to Output Not being
Driven

60

tOH

Output Hold from Address
Change, Chip Enable, or
Output Enable whichever
occurs first

Read Cycle Timing

0

Max.

Max.

250

2817A-350

Max.

300

Min.

Max.

Units

Test Conditions

ns

CE= OE= VIL

350

ns

OE= VIL

300

350

ns

CE= OE= VIL

90

100

100

ns

CE= VIL

60

60

80

ns

CE= VIL

ns

CE or OE= VIL

0

350

0

0

1~--------------tRC--------------~1

Ir-------- - - - - - - -__I , - - - - - - ADDRESSES

ADDRESSES VALID

1'--------- - - - ----'I -------

tOH
OUTPUT----------~----------~H

seeQ

MD400014/B

Technology, Incorporated

1-33

VALID

OUTPUT

2817AI5517A
Capacitance{1] TA=25°C, f=1
Symbol Parameter

MHz
Max

CrN

Input Capacitance

COUT

Data (110) CapaCitance

A.C Test Conditions
Conditions

Ourput Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: <20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V

6 pF VrN= OV
10 pF Vr/o= OV

E.S.D. Characteristics
Symbol

Parameter

VZAP(2)

E.S.D. Tolerance

Value
>2000 V

Test Conditions
MIL-STD883
Test Method 3015

AC Characteristics
Write Operation (Over the operating Vccand temperature range)
Limits
2817AH-200
2817A-200

2817AH-250
5517A-250
2817A-250

2817AH-300
5517A-300
2817A-300

Min.

Min.

Min.

Parameter

lAs

Address to Write
Set UpTime

tcs
twp(3)

CE to Write Set Up Time

10

10

10

10

ns

WE Write Pulse Width

120

150

150

150

ns

tAH

Address Hold Time

50

50

50

70

ns

tos

Data Set Up Time

50

50

50

50

ns

tOH

Data Hold Time

0

0

0

0

ns

tCH

CE Hold Time

0

0

0

0

ns

tOES

OE Set Up Time

10

10

10

10

ns

tOEH

OE Hold Time

10

10

10

10

ns

tOL
tov(4)

Data Latch Time

50

Data Valid Time

toe
tWR

twc

Max.

10

Max.

Max.

2817A-350

Symbol

10

10

Max.

Units
ns

10

ns

50

50

50

Min.

1

1

1

1

p's

Time to Device Busy

120

120

120

120

ns

Write Recovery Time
Before Read Cycle

10

10

10

10

p.s

2817A15517A
Byte Write Cycle Time
2817AH

10

10

10

10

2

2

2

rns
ms

NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not tested.
3.WE is noise protected. Less than a 20 ns write pulse will not activate a write cycle.
4. Data must be valid within 1 ms maximum after the initiation of a write cycle.

seeQ
MD400014/B

Technology, Incorporated

-----------------------------~
1-34

2817AI5517A
Write Cycle Timing

AD-Au

1/00 -

7

ROY/BUSY
WRITE CYCLE

---------1-- READ CYCLE-I

Ordering Information

D Q 5517A
D Q 2817A

1

PACKAGE

D-CERAMIC DIP
P- PLASTIC DIP
UX- UNENCAPSULATED DIE

LseeQ
MD4000141B

I

-250
- 250

~ l__-~_:-=--=--=__
TEMPERATURE
RANGE
Q-o"C to 70·C

PART TYPE

EEPROM BYTE WRITE TIME

ACCESS TIME

2Kx8 EEPROM

(Blank) - Standard Write Time
H - Fast Write Time

200-200 ns
250-250 ns
300-300ns
350-350 ns

Technology, IncotpOl8ted

1-35

1-36

seeQ

286412864H

e

Timer
64K Electrically Erasable PROM
October 1987

Features

The EEPROM has an internal timer that automatically
times out the write time. The on-chip timer, along
with the input latches, frees the microcomputer
system for tasks during the write time. The
standard byte write cycle time is 10 ms. For systems
requiring faster byte write, a 2864H is specified at 2
ms. An automatic byte erase is performed before a
byte operation is started. Once a byte has been
written, the ready/busy pin signals the microprocessor that it is available for another write or a read
cycle. All inputs are TTL for both the byte write and
read mode. Data retention is specified for ten years.

• Ready/Busy Pin
• High Endurance Write Cycles
-10,000 Cycles/Byte Minimum
• On-Chip Timer
- Automatic Byte Erase Before Byte Write
- 2 ms Byte Write (2864H)
• 5 V± 10% Power Supply
• Power Up/Down Protection Circuitry
• 250 ns max. Access Time
• Military and Extended Temperature
Range Available

These two timer EEPROMs are ideal for systems with
limited board area. For systems where cost is important, SEEQ has a latch only "528" family at 16K and
64K bit densities. All "528" family inputs, except for
write enable, are latched by the falling edge of the
write enable signal.

Description
SEEQ's 2864 is a 5 V only, 8K x 8 NMOS electrically
erasable programmable read only memory(EEPROM). It
is packaged in a 28 pin package and has a ready/busy
pin. This EEPROM is ideal for applications which require
non-volatility and in-system data modification. The
endurance, the number of times which a byte may be
written, is a minimum of 10 thousand cycles.

Pin Configuration
PLASTIC LEADED CHIP CARRIER
TOP VIEW

DUAL-IN-LINE
TOP VIEW

Block Diagram

I~

..:.l~~JlI~~

-- I; ...---

ROY/BUSY

1

Au
A,

'2

-

28

Vee

21

WE
NC

I.e

E2
MEMORY
ARRAY

A.
A.
A..

A.
A.
A.
A.
A,

A.
A.
A"

OE

NC

A,.

2.

Ao

vo.
vo,
VOl
GNO

Ice

OE

A.
A,

A,.

"

I vo,

11

~

• VOl

NC

vo,

16

~ VO.

VO.

VOl

CE

vo.

• Vo.

Pin Names

gg~~ggg

Ao-4

ADDRESSES - COLUMN (LOWER ORDER BITS)

AS-12

ADDRESSES - ROW

~

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

I/O

DATA INPUT (WRITE OR ERASE), DATA OUTPUT
(READ)

ROY/BUSY DEVICE READY/BUSY
N/C

NO CONNECT

seeQ Technology,lncorpo,.ted------------------------.......
MD400002/A

1-37

286412864H
Device Operation

Chip Erase

There are five operational modes (see Table 1) and,
except for the chip erase mode, only TTL inputs are
required. To write into a particular location, a 150 ns
TTL pulse is applied to the write enable (WE) pin of
a selected (CE low) device. This, combined with
output enable (OE) being high, initiates a 10 ms
write cycle. During a byte write cycle, addresses are
latched on either the falling edge of CE or WE,
whichever one occurred last. Data is latched on the
rising edge of CE or WE, whichever one occurred
first. The byte is automatically erased before data is
written. While the write operation is in progress, the
ROY/BUSY output is at a TTL low. An internal timer
times out the required byte write time and at the end
of this time, the device signals the ROY/BUSY pin to
a TTL high. The ROY/BUSY pin is an open drain
output and a typical 3K n pull-up resistor to Vcc is
required. The pull-up resistor value is dependent on
the number of OR-tied ROY/BUSY pins. If ROY/BUSY
is not used it can be left unconnected.

Certain applications may require all bytes to be
erased simultaneously. This feature is optional and
the timing specifications are available from SEEQ.

Power Up/Down Considerations
The 2864 has internal circuitry to minimize a false
write during system Vcc power up or down. This
circuitry prevents writing under anyone of the
following conditions.
1. Vcc is less than 3 V. [1J
2. A negative Write Enable (WE) transition has not
occurred when Vcc is between 3 V and 5 V.
Writing will also be prevented if CE or OE are in TTL
logical states other than that specified for a byte
write in the Mode Selection table.

Abso/ute Maximum Stress Ratlngs*

Mode Selection
Mode/Pin

Temperature
Storage .......................... -650 C to + 15(J" C
Under Bias ...................... -1(J" C to +8(J" C

(Table 1)

CE

OE

WE

I/O

(20)

(22)

(27)

(11-13,15-19)

ROY/
BUSY
(1 )*

Read

VIL

VIL

VIH

DouT

High Z

Standby

VIH

X

X

High Z

High Z

Byte Write

VIL

VIH

VIL

DIN

VOL

X
X

VIL
X

X
VIH

High Z/DouT
High Z/DouT

High Z
HighZ

Write
Inhibit

AI/Inputs or Outputs with
Respect to Ground . .................. , +6 V to -0.3 V

'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

'Pin 1 has an open drain output and requires an external 3K
resistor to Vee . The value of the resistor is dependent on the
number of OR-tied ROY/BUSY pins.

Recommended Operating Conditions

I Vce Supply Voltage

LTemperature Range: (Ambient)

2864 H-250/H-300
2864-250/-300

2864-350

5 V± 10%

5 V± 10%

O°C to 70°C

O°C to 70°C

Endurance and Data Retention
Condition

Symbol

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TOR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

NOTE: 1 - Characterized. Not tested.

seeQ

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--J

MD400002/A

1-38

286412864H
DC Opetatlng Chatacterlstlcs

(Over the operating Vee and temperature range)
Limits

Symbol

Parameter

Icc

Active Vee Current
(Includes Write Operation)

ISB

Min.

Max.

Units

110

mA

CE = OE = VIL; All I/O Open;
Other Inputs = Vee Max.

40

mA

CE = VIH, OE = VIL; All I/O Open;
Other Inputs = Vee Max.

Test Condition

Standby Vee Current

III

Input Leakage Current

10

,.,.A

VIN = Vee Max.

ILO

Output Leakage Current

10

,.,.A

VOUT = Vee Max.

VIL

Input Low Voltage

-0.1

0.8

V

2.0

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

AC Chatacteristlcs

Read Operation

Vee

+1

V

0.4
2.4

V

IOL = 2.1 rnA

V

IOH = -400 p.A

(Over the operating Vee and temperature range)
Limits

Symbol Parameter

2864H-250
2864-250

2864H-300
2864-300

2864-350

Min.

Min.

Min.

Max.

250

Max.

tRe

Read Cycle Time

teE

Chip Enable Access Time

250

300

tAA

Address Access Time

250

tOE

Output Enable Access Time

90

tOF

Output Enable High to Output Not
being Driven

0

tOH

Output Hold from Address Change, Chip
Enable, or Output Enable whichever occurs
first

0

Read Cycle Timing

300

60

0

Units

Test Conditions

ns

CE= OE=VIL

350

ns

OE = VIL

300

350

ns

CE = OE = VIL

100

100

ns

CE = VIL

80

ns

CE = VIL

ns

CE orOE= VIL

60

0

0

tRC

Max.

350

0

------t

---_ Ir-------- ---- ---_I ,._------

ADDRESSES

ADDRESSES VALID

-----' ~------- - - ----'"'I "'------

tOH
OUTPUT--------~----------_+t+{

NOTES:

VALID

OUTPUT

IAA

1. OE MAY BE DELAYED T~AA - tOE AFTER THE FALLING EDGE OF CEWITHOUT IMPACT ON lAA.
2. tOF IS SPECIFIED FROM OE ORCE, WHICHEVER OCCURS FIRST.

SeeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
M 0400002/A

1-39

286412864H
Capacitance

T A [1]

= 25°C; f = MHz

A C Test Conditions

Symbol

Parameter

Max.

Conditions

CIN

Input Capacitance

6 pF

VIN =0 V

COUT

Data (liD) Capacitance 10 pF Vvo=OV

Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fali Times: <20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V

E. S. D. Characteristics[4/
Symbol

Parameter

VZAP

E.S.D.
Tolerance

Value
>2000 V

Test Conditions
MIL-STD 883
Test Method 3015

AC Characteristics

Write Operation (Over operating temperature and Vcc range)
Limits
2864H-250
2864-250
Symbol

Parameter

twc

Write Cycle Time/Byte
Standard Family Only

Min.

Max.

2864H-300
2864-300
Min.

Min.

10

10

"H" Family Only

Max.

2864-350

2

2

Max.

Units

10

ms

-

ms

tAS

Address to WE Set Up Time

10

10

10

ns

tcs
twpl21

CE to Write Set Up Time

0

0

0

ns

WE Write Pulse Width

150

150

150

ns

tAH

Address Hold Time

50

50

70

ns

tos

Data Set Up Time

50

50

50

ns

toH

Data Hold Time

20

20

20

ns

tCH

CE Hold Time

0

0

0

ns

tOES

DE Set Up Time

10

10

10

ns

tOEH

DE Hold Time

10

10

10

ns

tol

Data Latch Time

50

50

50

tovl31

Data Valid Time

tos
tWR

ns

1

1

1

Time to Device Busy

200

200

200

J.I.S
ns

Write Recovery Time
Befo~e Read Cycle

10

10

10

p,s

Notes:
1. This parameter measured only for the initial qualification and after process or design changes which may affect capacitance.
2. WE is noise protected. Less than a 20 ns write pulse will not activate a write cycle.
3. Data must be valid within 1 p.S maximum after the initiation of a write cycle.
4. Characterized. Not tested.

seeQ

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J

MD400002/A

1-40

286412864H
Write Cycle Timing

Ao-A'2

CE

WE

ROY/BUSY

WRITE CYCLE

-----:..---...1-- READ CYCLE

--I

Ordering Information

DO
DO

TEMPERATURE
RANGE
D=CERAMIC DIP Q = O°C to + 70°C
P= PLASTIC DIP
N=PLASTIC LEADED
CHIP CARRIER
U=UNENCAPSULATED DIE

seeQ

Technology, Incorporated

MD400002/A

2864
2864

- 250
H - 250

TIT
DEVICE TYPE
8Kx8 EEPROM

T

EEPROM WRITE TIME
(BLANK)-STANDARD
WRITE TIME
H-FASTWRITETIME

ACCESS TIME

25O=25Onl
3OO=300nl
350=350 nl

-------------------------------1
1-41

1·42

seeQ

28C64
Timer ~
64K Electrically Erasable PROM

PRELIMINARY DATA SHEET

October, 1988

Features

Description

• CMOS Technology
• Low Power
• 50 mA Active
• 150 pA Standby
• Page Write Mode
• 64 Byte Page
• 160 us Average Byte Write Time
• Byte Write Mode
• Write Cycle Completion Indication
• DATA Polling
• On Chip Timer
• Automatic Erase Before Write
• High Endurance
• 10, 000 Cycles/Byte
• 10 Year Data Retention
• Power Up/Down Protection Circuitry
• 200 ns Maximum Access Time
• JEDEC Approved Byte Wide Pinout
• Military and Extended Temperature
Range Available

SEEQ's 28C64 is a CMOS 5V only, 8K x 8 Electrically Erasable Programmable Read Only Memory
(EEPROM). It is manufactured using SEEQ's advanced 1.25 micron CMOS Process and is available in
both a 28 pin Cerdip package as well as a Plastic
Leaded Chip Carrier (PLCC). The 28C64 is ideal for
applications which require low power consumption,
non-volatility and in system reprogrammability. The
endurance, the number of times a byte can be written,
is specified at 10,000 cycles per byte and is typically
1,000,000 cycles per byte. The extraordinary high
endurance was accomplished using SEEQ's proprietary oxynitride EEPROM process and its innovative
Q CelfM design. System reliability, in all applications,
is higher because of the low failure rate of the Q Cell.
The 28C64 has an internal timer which automatically times out the write time. The on-chip timer,
along with input latches free the microprocessor

Pin Configuration
PLASTIC LEADED CHIP CARRIER
TOP VIEW

DUAL-IN-LiNE
TOP VIEW

~ ~ il il ::tl I~ il

E2
MEMORY
ARRAY

Ne
A6

As

As

Ag

~

A12

2

A7
A6

3

As
A11

Ne
A2
Al

A'0

CE
1/07

6
7
S

A4
A3
A2
A,
Ao

10

1/00 ~ 11
1/0, ~ 12
1/02 ~ 13

GND

e

14

27
26

Vee

WE
Ne

2S
24

As
Ag

23

All

22
21
20
19
lS
17
16
lS

OE
A'0

CE
1/07
1/0 6
I/0s

1/04
1/03

gg~~ggg
1/00·7

Pin Names

Q Cell is a trademark of SEEQ Technology, Inc.

A" ••

ADDRESSES-COLUMN

A.·A,.

ADDRESSES-ROW

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

i/Oo-7

DATA INPUT (WRITE)/DATA
OUTPUT (READ)

NC

NO CONNECTION

~-~~~~~C~Ofu~~~~orn~d----------------------------~
MD400004/C

1-43

28C64
PRELIMINARY DATA SHEET

Writes

for other tasks while the part is busy writing. The
28C64's write cycle time is 10 ms. An automatic
erase is performed before a write. The DATA polling
feature ofthe 28C64 can be used to determine the
end of a write cycle. Once the write has been completed, data can be read in a maximum of 200 ns.
Data retention is specified for 10 years.

To write into a particular location, the address must
be valid and a TTL low applied to the Write Enable
(WE) pin of a selected (CE low) device. This combined with Output Enable (OE) being high,
initiates a write cycle. During write cycle, all inputs
except data are latched on the falling edge of WE
orCE, whichever occurred last. Write enable needs
to be at a TTL low only for the specified twp time.
Data is latched on the rising edge of WE or CE,
whichever occurred first. An automatic erase is
perfomed before data is written.

Device Operation
Operational Modes
There are five operational modes (see Table 1)
and, except for the chip erase mode, only TTL
inputs are required. A Write can only be initiated
under the conditions shown. Any other conditions
for GE, OE, and WE will inhibit writing and the I/O
lines will either be in a high impedance state or
have data, depending on the state of aforementioned three input lines.

Write Cycle Control Pins
For system design Simplification, the 28C64 is
designed such that either the CE or WE pin can be
used to initiate a write cycle. The device uses the
latest high-to-Iow transition of either CE or WE
signal to latch addresses and the earliest low-tohigh transition to latch the data. Address and OE
setup and hold are with respect to the later of CE
or WE; data setup and hold is with respect to the
earlier of WE or CE.

Mode Selection
MODE

CE

OE

WE

I/O

Read

VIL

VIL

VIH

DouT
HIZ

Standby

VIH

X

X

Write

VIL

VIH

VIL

DIN

Write
Inhibit

X
X

VIL
X

X
VIH

HI Z/DouT
HI Z/DouT

VIL

VH

VIL

X

Chip Erase

To simplify the following discussion, the WE pin is
used as the write cycle control pin throughout the
rest of this data sheet. Timing diagrams of both
write cycles are included in the AC Characteristics.

X: Any TTL level
VH: High Voltage

Reads
A read is accomplished by presenting the address
of the desired byte to the address inputs. Once the
address is stable, CE is brought to a TTL low in
order to enable the chip. The WE pin must be at a
TTL high during the entire read cycle. The output
drivers are made active by bringing Output Enable
(OE) to a TTL low. During read, the address, CE,
OE, and I/O latches are transparent.

seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

MD400004/C

1-44

28C64
PRELIMINARY DATA SHEET

Write Mode
One to 64 bytes of data can be randomly loaded
into the page. The part latches row addresses,
A6-A 12, during the first byte write. These addresses
are latched on the falling edge of the WE signal
and are ignored after that until the end of the write
cycle. This will eliminate any false write into another
page if different row addresses are applied and
the page boundary is crossed.

not start the page load timer. When WE returns
high, the input data is latched and the page load
cycle timer begins. In CE controlled write the same
is true, with CE holding the timer reset instead
of WE.

DATA Polling
The 28C64 has a maximum write cycle time of
10 ms. Typically though, a write will be completed
in less than the specified maximum cycle time.
DATA polling is a method of minimizing write times
by determining the actual endpoint of a write cycle.
lf a read is performed to any address while the
28C64 is still writing, the device will present the
ones-complement of the last byte written. When
the 28C64 has completed its write cycle, a read
from the last address written will result in valid
data. Thus, software can simply read from the part
until the last data byte written is read correctly.

The column addresses, AO-AS, which are used to
select different locations of the page, are latched
every time a new write initiated. These addresses
and the OE state (high) are latched on the falling
edge of WE signal. For proper write initiation and
latching, the WE pin has to stay low for a minimum
of twp ns. Data is latched on the rising edge of WE,
allowing easy microprocessor interface.
Upon a low to high WE transition, the 28C64
latches data and starts the internal page load timer.
The timer is reset on the falling edge of the WE
signal if another write is initiated before the timer
has timed out. The timer stays reset while the WE
pin is kept low. If no additional write cycles have
been initiated within taLC after the last WE low to
high transition, the part terminates the page load
cycle and starts the internal write. During this time
which takes a maximum of 10 ms, the device
ignores any additional write attempts. The part
can be read to determine the end of write cycle
(DATA polling).

A DATA polling read can occur immediately after a
byte is loaded into a page, prior to the initiation of the
internal write cycle. DATA polling attempted during
the middle of a page load cycle will present a onescomplement of the most recent data byte loaded
into the page. Timing for a DATA polling read is the
same as a normal read.

Chip Erase
Certain applications may require all bytes to be
erased simultaneously. This feature, which
requires high voltage, is optional and timing
specifications are available from SEEQ.

Extended Page Load
In order to take advantage of the page mode's faster average byte write time, data must be loaded at
the page load cycle time (tau;). Since some applications may not be able to sustain transfers at this
minimum rate, the 28C64 permits an extended
page load cycle. To do this, the write cycle must be
"stretched" by maintaining WE low, assuming a
write enable-controlled cycle, and leaving all other
control inputs (CE, OE) in the proper page load
cycle state. Since the page load timer is reset on
the falling edge of WE, keeping this signal low will

seeQ

Power Up/Down Considerations
There is internal circuitry to minimize a false write
during power up or power down. This circuitry prevents writing under anyone of the following
conditions:
1. Vcc is less than VwN
_
2. A high to low Write Enable (WE) transition has
not occurred when the Vcc supply is between
VwN and Vcc with CE low and OE high.
Writing will also be inhibited when WE, CE, or OE
are in TTL logical states other than that specified
for a write in the Mode Selection table.

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

MD400004/C

1-45

28C64
PRELIMINARY DATA SHEET

Absolute Maximum Stress Range*
Temperature
Storage ................... -65°C to +150°C
Under Bias ................. -10°C to +80°C

*COMMENT: Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions beyond those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

D. C. Voltage applied to all Inputs or Outputs
with respect to ground . ..... +6.0 Vto -0.5 V
Undershoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground . ............. -1.0 V
Overshoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground . ........... , + 7. 0 V

Recommended Operating Conditions
28C64

I

Temperature Range (Ambient)

O°C to 70°C

I Vcc Power Supply

5 V± 10%

Endurance and Data Retention
Condition

Symbol

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TOR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

DC Characteristics

(Over operating temperature and Vee rang.;, unless otherwise specified)
Limits

Symbol

Parameter

Max.

Units

Icc

Active Vee Current

50

rnA

CE = OE = VIL; All I/O Open;
Other Inputs = Vee Max.;
Max read or write cycle time

ISBl

Standby Vee Current
(TTL Inputs)

2

rnA

CE = VIH, OE = VIL; All I/O Ope'n;
Other Inputs = ANY TTL LEVEL

ISB2

Standby Vee Current
(CMOS Inputs)

150

p.A

CE = Vee-0.3
Other inputs = VIL to VIH
All I/O Open

hLI21

Input Leakage Current

10L

Output Leakage Current

VIL

Input Low Voltage

VIH

Input High Voltage

VOL

Output Low Voltage

VOH

Output High Voltage

VWI(11

Write Inhibit Voltage

Min.

Test Condition

= Vee Max.

1

p.A

VIN

10

p.A

Vour = Vee Max.

-0.3

0.8

V

2.0

6

V

0.45

V

10L = 2.1 rnA

2.4

V

10H= -400 p.A

3.8

V

Notes:
1. Characterized Not tested
2. Inputs only. Does not include I/O.

.SeeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD400004/C

1-46

28C64
PRELIMINARY DATA SHEET

Capacitance[1[

AC Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: <10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs O.B V and 2 V
Outputs O.B V ana 2 V

TA = 25 C, f = 1 MHz

Max. Conditions

Symbol

Parameter

CIN

Input Capacitance

6 pF VIN = OV

COUT

Data (I/O) Capacitance

12 pF VI/O= OV

E.S.D. Characteristics
Symbol

Parameter

VZAP[2]

E.S.D.
Tolerance

Value
>2000

Test Conditions
MIL-STD 883
Test Method 3015

V

AC Characteristics Read Operation

(Over operating temperature and Vcc Range, unless otherwise specified)

28C64-200

28C64-250

Min.

Max.

Max.

Limits
28C64-300

Max.

Units

Test
Conditions

ns

CE=OE=VIL

ns

OE=VIL

Parameter

Min.

tRC

Read Cycle Time

200

teE

Chip Enable Access Time

200

250

300

350

tAA

Address Access Time

200

250

300

350

ns

CE=OE=VIL

tOE

Output Enable Access Time

80

90

90

90

ns

CE=VIL

tOF

Output or Chip Enable High to
output n,ot being driven

0

80

ns

CE = VIL

tOH

Output Hold from Address Change,
Chip Enable, or Output Enable,
whichever occurs first

0

ns

CE = OE = VIL

60

Max.

Min.

Symbol

250

Min.

28C64-350

350

300

0

60

0

0

80

0
0

0

Read/Data Polling Cycle Time

.
~

ADD RESSES

.

IRC

~~

ADDRESS AN

NEXT ADDRESS

-

lAA

-

~

~r

l- ICE

~~

~r
_IOF __

__ IOE_
IOH

_~IOH
HIGHZ

DATA

~<

..

lAA

.

DATA VALID : } (
I

~

t-l

DATA VALID

~

t-

Notes:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized Not tested

seeQ

Technology. Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

MD4000041C

1-47

28C64
PRELIMINARY DATA SHEET

A C Characteristics Write Operation (Over the operating temperature and V cc range, unless otherwise specified)
Limits
28C64-200

Min.

28C64-250

Max.

Min.

28C64-300

Max.

Max.

Min.

Max.

Units

10

ms

Parameter

twc

Write Cycle Time

tAS

Address Set-up Time

10

10

10

10

tAH

Address Hold Time (see note 1)

150

150

150

150

ns

tcs

Write Set-up Time

0

0

0

0

ns

10

Min.

28C64-350

Symbol

10

10

ns

tcH

Write Hold Time

0

0

0

0

ns

tcw

CE Pulse Width (note 2)

150

150

150

150

ns

toES

OE High Set-up Time

10

10

10

10

ns

tOEH

OE High Hold Time

10

10

10

10

ns

twp

WE Pulse Width (note 2)

150

150

150

150

ns

tos

Data Set-up Time

50

50

50

50

ns

tOH

Data Hold Time

tBlC

Byte Load Timer Cycle
(Page Mode Only) (see note 3)

tlP

Last Byte Loaded
to DATA Polling

0
0.2

0
300

300
200

200

0.2

ns

0

0

0.2

300
200

0.2

300

us

200

ns

Write Timing
WE CONTROLLED WRITE CYCLE

CE CONTROLLED WRITE CYCLE

r---OE

OE

X

~

CE

WE

WE

CE

DATA

f---

DATA

~

~~
HIGHZ

r,---

Notes:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. tBlC min. is the minimum time before the next byte can be loaded. tBlC max. is the minimum time the byte load timer waits before
initiating internal write cycle.

seeQ Technology. Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

---A

MD400004/C

1-48

28C64
PRELIMINARY DATA SHEET

Page Write Timing

DATA POLLING

"--

PAGE LOAD

-I
rf--

----or:-----.,r----'C::::~--:::::-:...J'--r----or-,--..;~\

,--:DO=N..:.'T..::C~AR~E=--_-ifPc=

. ::-:;'-------'--1~'-=-- ~1'-<

WE-----.J

r---<

DATA _H_IG_H_Z_ _ _(j

Ordering Information

PACKAGE

TEMP. RANGE

PART TYPE

ACCESS TIME

D = CERAMIC DIP

o-O'to70'C

8KK8E"PROM

200 = 2oon.

P= PLASTIC DIP

(COMMERCIAL)

250= 25On.
300- 3OOn.

N = PLASTIC LEADED
CHIP CARRIER

350 = 35On.

UX= UNENCAPSULATED DIE

seeQ

Technology. Incorpol1Jted - - - - - - - - - - - - - - - - - - - - - - - -.......

MD400004/C

1-49

seeQ

28C65
Timer E?64K Electrically Erasable PROM

PRELIMINARY DATA SHEET

October, 1988

Features

Description

• CMOS Technology
• Low Power
• 50 mA Active
• 150 pA Standby
• Page Write Mode
• 64 Byte Page
• 160 us A verage Byte Write Time
• Byte Write Mode
• Write Cycle Completion Indication
• DATA Polling
• ROY/BUSY Pin
• On Chip Timer
• Automatic Erase Before Write
• High Endurance
• 10,000 Cycles/Byte
• 10 Year Data Retention
• Power Up/Down Protection Circuitry
• 200 ns Maximum Access Time
• JEDEC Approved Byte Wide Pinout
• Military and Extended Temperature
Range Available

SEEQ's 28C65 is a CMOS 5V only, 8K x 8 Electrically Erasable Programmable Read Only Memory
(EEPROM). It is manufactured using SEEQ's advanced 1.25 micron CMOS Process and is available in
both a 28 pin Cerdip package as well as a Plastic
Leaded Chip Carrier (PLCC). The 28C65 is ideal for
applications which require low power consumption,
non-volatility and in system reprogrammability. The
endurance, the number of times a byte can be written,
is specified at 10,000 cycles per byte and is typically
1,000,000 cycles per byte. The extraordinary high
endurance was accomplished using SEEQ's proprietary oxynitride EEPROM process and its innovative
Q CelfM design. System reliability, in all applications,
is higher because of the low failure rate of the Q Cell.
The 28C65 has an internal timer which automatically times out the write time. The on-chip timer,
along with input latches free the microprocessor

Pin Configuration
PLASTIC LEADED CHIP CARRIER
TOP VIEW

.t ~

I~
i

DUAL-IN-LiNE
TOP VIEW

~ ~ I~ ~
RDY/BUSv
A12
A7

As

3
4

A5

5

A2

A11
NC

A4
A3

OE

A2
Al

A10

RDYliiiiiY _ _--'=====~-----~~

CE

Ao
11 0 0
1/ 0 1
1/02
GND

10
11
12
13
14

28
27
26
25
24
23
22
21
20
19
18
17

16
15

vcc

WE
NC

As
A9
All

Of
Al0

CE
1107
110 6
11 0 5
1/0 4
1/0 3

Pin Names
AO-5
1/00.7

Q Cell is a trademark of SEEQ Technology, Inc.

ADDRESSES - COLUMN

Ae-A12

ADDRESSES ROW

CE
5E
WE

CHIP ENABLE

1/00-7

DATA INPUT (WRITE)
DATA OUTPUT (READ)

OUTPUT ENABLE
WRITE ENABLE

RDY/MiSY DEVICE READY/BUSY

NC
NO CONNECTION
SeeQ Technology, Incorporated _ _ _ _ _ _ _-':;=====::;:===;;;=:==;;;=:=::...-------1

MD4000251B

1-51

28C65
PRELIMINARY DATA SHEET

for other tasks while the part is busy writing. The
28C65's write cycle time is 10 ms. An automatic
erase is performed before a write. The DATA polling
feature of the 28C65 can be used to determine the
end of a write cycle. Once the write has been completed, data can be read in a maximum of 200ns.
Data retention is specified for 10 years.

Device Operation
Operational Modes
There are five operational modes (see Table 1)
and, except for the chip erase mode, only TTL
inputs are required. A Write can only be initiated
under the conditions shown. Any other conditions
for CE, OE, and WE will inhibit writing and the I/O
lines will either be in a high impedance state or
have data, depending on the state of aforementioned three input lines.

Mode Selection
MODE

CE

OE

WE

I/O

RDY/BUSyll!

Read

VIL

VIL

VIH

DOUT

HIZ

Standby

VIH

X

X

HIZ

HIZ

Write

VIL

VIH

VIL

DIN

VOL

Write
Inhibit

X
X

VIL

X

X

VIH

HI Z/DOUT
HI Z/DOUT

HIZ
HIZ

VIL

VH

VIL

X

HIZ

Chip Erase

Writes
To write into a particular location, the address must
be valid and a TTL low applied to the Write Enable
(WE) pin of a selected (CE low) device. This combined with Output Enable (OE) being high,
initiates a write cycle. During write cycle, all inputs
except data are latched on the falling edge of WE
orCE, whicheveroccurredlast. Write enable needs
to be at a TTL low only for the specified t Wp time.
Data is latched on the rising edge of WE or CE,
whichever occurred first. An automatic erase is
perfomed before data is written.

Write Cycle Control Pins
For system design Simplification, the 28C65 is
designed such that either the CE or WE pin can be
used to initiate a write cycle. The device uses the
latest high-to-/ow transition of either CE or WE
signal to latch addresses and the earliest low-tohigh transition to latch the data. Address and OE
setup and hold are with respect to the later of CE
or WE; data setup and hold is with respect to the
earlier of WE or CE.
To simplify the following discussion, the WE pin is
used as the write cycle control pin throughout the
rest of this data sheet. Timing diagrams of both
write cycles are included in the AC characteristics.

X: Any TIL level
VH: High Voltage

Reads
A read is accomplished by presenting the address
of the desired byte to the address inputs. Once the
address is stable, CE is brought to a TTL low in
order to enable the chip. The WE pin must be at a
TTL high during the entire read cycle. The output
drivers are made active by bringing Output Enable
(OE) to a TTL low. During read, the address, CE,
OE, and I/O latches are transparent.

NOTES:
1. RDY/BUSY Pin 1 (Pin 2 on PLCC) has an open drain output and requires an external3K resistor to Vee. The value of the resistor is
dependent on the number of OR-tied RDY/BUSY pins.

seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

MD4000251B

1-52

28C65
PRELIMINARY DATA SHEET

Write Mode
OA TA polling is a method of minimizing write times
by determining the actual endpoint of a write cycle.
lf a read is performed to any address while the
28C65 is still writing, the device will present the
ones-complement of the last byte written. When
the 28C65 has completed its write cycle, a read
from the last address written will result in valid
data Thus, software can simply read from the part
until the last data byte written is read correctly.

One to 64 bytes of data can be randomly loaded
into the page. The part latches row addresses,
A6-A 12, during the first byte write. These addresses
are latched on the falling edge of the WE signal
and are ignored after that until the end of the write
cycle. This will eliminate any false write into another
page if different row addresses are applied and
the page boundary is crossed.
The column addresses, AO-A5, which are used to
select different locations of the page, are latched
every time a new write initiated. These addresses
and the DE state (high) are latched on the falling
edge of WE signal. For proper write initiation and
latching, the WE pin has to stay low for a minimum
of twp ns. Data is latched on the rising edge of WE,
aI/owing easy microprocessor interface.

A OA TA polling read can occur immediately after a
byte is loaded into a page, prior to the initiation of
the internal write cycle. DATA polling attempted
during the middle of a page load cycle will present
a ones-complement of the most recent data byte
loaded into the page. Timing for a OATA polling
read is the same as a normal read.

Upon a low to high WE transition, the 28C65
latches data and starts the internal page load timer.
The timer is reset on the falling edge of the WE
signal if another write is initiated before the timer
has timed out. The timer stays reset while the WE
pin is kept low. If no additional write cycles have
been initiated within tSLC after the last WE low to
high transition, the part terminates the page load
cycle and starts the internal write. During this time
which takes a maximum of 10 ms, the device
ignores any additional write attempts. The part
can be read to determine the end of write cycle
(OA TA polling).

READY/BUSY Pin
28C65 provides write cycle status on this pin.
ROY/BUSY output goes to a TTL low immediately
after the falling edge of WE. ROY/BUSY will
remain low during the byte load or page load cycle
and continues to remain at a TTL low while the
write cycle is in progress. An internal timer times
out the required write cycle time and at the end of
this time, the device signals ROY/BUSY pin to a
TTL high. This pin can be pol/ed for write cycle
status or used to initate a rising edge triggered
interrupt indicating write cycle completion. The
RO Y/B USY pin is an open drain output and a typical
3 K pull-up resistor to Vcc is required. The pull-up
value is dependent on the number of OR-tied
ROY/BUSY pins. If ROY/BUSY is not used it can
be left unconnected.

Extended Page Load
In order to take advantage of the page mode's faster average byte write time, data must be loaded at
the page load cycle time (tSLc). Since some applications may not be able to sustain transfers at this
minimum rate, the 28C65 permits an extended
page load cycle. To do this, the write cycle must be
"stretched" by maintaining WE low, assuming a
write enable-controlled cycle, and leaving all other
control inputs (CE, DE) in the proper page load
cycle state. Since the page load timer is reset on
the falling edge of WE, keeping this signal low will
not start the page load timer. When WE returns
high, the input data is latched and the page load
cycle timer begins. In CE controlled write the same
is true, with CE holding the timer reset instead
of WE.

DATA Polling
The 28C65 has a maximum write cycle time of
10 ms. Typical/y though, a write will be completed
in less than the specified maximum cycle time.

Chip Erase
Certain applications may require a/l bytes to be
erased simultaneously. This feature, which
requires high voltage. is optional and timing
specifications are available from SEEQ.

Power Up/Down Considerations
There is internal circuitry to minimize a false write
during power up or power down. This circuitry prevents writing under anyone of the following
conditions:
1. Vee is less than VwN
_
2. A high to low Write Enable (WE) transition has
not occurred when the Vee supply is between
VwN and Vec with CE low and DE high.
Writing will also be inhibited when WE. CEo or DE
are in TTL logical states other than that specified
for a write in the Mode Selection table.

SeeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

--J

M0400025/B

1-53

28C65
PRELIMINARY DATA SHEET

Abso lute Maximum Stress Range*
Tempe rature
Stora ge ................... -65°C to +150°C
Unde r Bias ................. -10°C to +80°C

*COMMENT: Stresses beyond those listed under "Ab~olute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions beyond those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

D.C. Vo /tage applied to all Inputs or Outputs
with respect to ground. . . . . . + 6. 0 V to -0.5 V
Undershoot pulse of less than 10 ns (measured at
50% pOint) applied to all inputs or outputs
with respect to ground . ............. -1.0 V
Oversh oot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground . ............ +7.0V

Reeom mended Operating Conditions
28C65

ODC to 70 DC

Tempe rature Range (Ambient)
Vee Po wer Supply

5 V± 10%

Endu ranee and Data Retention
Symb 01

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TOR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

DCC haracteristics

Condition

(Over operating temperature and Vee range, unless otherwise specified)
Limits

Symbo I

Parameter

Icc

Max.

Units

Active Vee Current

50

mA

CE = OE = VIL; All I/O Open;
Other Inputs = Vec Max.;
Max read or write cycle time

ISB1

Standby Vee Current
(TIL Inputs)

2

mA

CE = VIH, OE = VIL; All I/O Open;
Other Inputs = ANY TIL LEVEL

ISB2

Standby Vee Current
(CMOS Inputs)

150

ILA

CE = Vee -0.3
Other inputs = VIL to VIH
All I/O Open

IILI21

Input Leakage Current

1

ILA

VIN = Vce Max.

IOL

Output Leakage Current

VOUT

VIL

Input Low Voltage

-0.3

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

V

IOL = 2.1 mA

VOH

Output High Voltage

2.4

V

10H= -400

VWl l 1 1

Write Inhibit Voltage

3.8

V

Min.

Not tested.
2. Inputs on Iy. Does not include 1/0.

SeeQrechnology, Inco rpra ted
0

MD4000251B

ILA
V

6

V

0.45

Notes:
1. eharacte rized.

"""--

10
0.8

1-54

Test Condition

= Vce

Max.

JLA

28C65
PRELIMINARY DATA SHEET

Capacitance!'1

AC Test Conditions
Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: <10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V

TA

= 25

C. f

= 1 MHz

Symbol

Parameter

Max. Conditions

CIN

Input Capacitance

6 pF VIN = OV

COUT

Data (I/O) Capacitance

12 pF VIIO = OV

E. S. D. Characteristics
Symbol

Parameter

VZApl 21

E.S.D.
Tolerance

Value

Test Conditions

>2000 V

AC Characteristics

MIL-STD 883
Test Method 3015

Read Operation (Over operating temperature and Vee Range, unless otherwise specified)
28C65-200

28C65-250

Limits
28C65-300

28C65-350

Test
Symbol

Parameter

Min.

tAc

Read Cycle Time

200

Min.

Max.

Max.

Min.

250

Max.

Min.

300

Max.

Units

Conditions

ns

CE=OE=VIL

350

teE

Chip Enable Access Time

200

250

300

350

ns

OE=VIL

tM

Address Access Time

200

250

300

350

ns

CE=OE=VIL

tOE

Output Enable Access Time

150

ns

CE=VIL

tDF

Output or Chip Enable High to
output not being driven

0

80

ns

CE=VIL

tOH

Output Hold from Address Change,
Chip Enable, or Output Enable,
whichever occurs first

0

ns

CE=OE=VIL

.

80
0

60

0

150
80

0

0

0

0

Read/Data Polling Cycle Time

.

IRC

~

ADDRESSES

90

60

~

ADDRESS AN

-

NEXT ADDRESS
lAA

...,~~

~-

l-

icE

~~

-

...,IZ~
... toF_

-toEtoH

_~toH

HIGHZ

DATA

~~

DATA VALID

X.

)l

-I

DATA VALID

:».t-

..

lAA
Notes:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
oO

2. Characterized Not tested

seeQ

Technology. Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - -.....

MD400025/B

1-55

28C65
PRELIMINARY DATA SHEET

AC Characteristics
Write Operation (Over the operating Vccand temperature range)
Limits
28C65-200
Min.

Max.

28C65-250
Min.

Max.

28C65-300
Min.

Max.

28C65-350
Min.

Max.

Units

10

ms

Symbol

Parameter

twc

Write Cycle Time

tAS

Address Set-up Time

10

10

10

10

ns

tAH

Address Hold Time (see note 1)

150

150

150

150

ns

los

Write Set-up Time

0

0

0

0

ns

loH

Write Hold Time

0

0

0

0

ns

low

CE Pulse Width (note 2)

150

150

150

150

ns

toES

OE High Set-up Time

10

10

10

10

ns

toEH

OE High Hold Time

10

10

10

10

ns

twp

WE Pulse Width (note 2)

150

150

150

150

ns

tos

Data Set-up Time

50

50

50

50

ns

toH

Data Hold TIme

0

0

0

0

taLC

Byte Load Timer Cycle
(Page Mode Only) (note 3)

tlP

Last Byte Loaded
to DATA Polling

200

200

toB

Time to Device Busy

100

100

10

10

0.2

300

0.2

300

10

0.2

300

0.2

ns
300

us

200

200

ns

100

100

ns

Write Timing
CE CONTROLLED WRITE CYCLE

WE CONTROLLED WRITE CYCLE

DATA

DATA

_______.-.-.. . _1_ POLLING -I-::-- POLLING --I

_l~~OE

ADDRESSES

CE _ _ _--.

WE _ _ _ _..J

loB

-I

RDY/BU~SY!.-.._ _ _.......,.j,'-_______"''-./ ...J.~----NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CE.
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. tSLC min. is the minimum time before the next byte can be loaded. tSlC max. is the minimum time the byte load timer waits before
initiating the internal write cycle.

seeQ

Technology. Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

MD400025/B

1-56

28C65
PRELIMINARY DATA SHEET

Page Write Timing
I

DATA

----t-- POLLING

PAGE LOAD

c=:::::::-J--r"---.. . .,.--""""\

-F-

-r,-

DATA
POLLING

-1

r~

__...!DON='T.:.;CAR=E~_-4:~

.:SE:::S:..-,.,..._+---r~_",-",:VALI~D:.....;"~_ _ _ Z:::~

ADDRES•

i i i E - - -........u

HIGHZ

DATA

RDY/BUSY

------4....(1

------..I-t___________

Ordering Information

o

Q 28C65 - 250

=2l:

PACKAGE

TEMP. RANGE
D = CERAMIC DIP
p= PLASTIC DIP

8K x 8 E'PROM

o-O'to 70·C
(COMMERCIAL)

N = PLASTIC LEADED
CHIP CARRIER

ACCESS TIME

200

~

200 ns

250

=

250 ns

300

~

300 ns

350

=

350 ns

UX= UNENCAPSULATED DIE

seeQ

Technology. Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.....J

MD4000251B

1-57

1-58

seeQ

2BC256

Tim ere
256K Electrically Erasable PROM

PRELIMINARY DATA SHEET

November, 1988

Description

Featu,es
• CMOS Technology
• Low Power
• 60 mA Active
• 1501lA Standby
• Page Write Mode
• 64 Byte Page
• 160 us Average Byte Write Time
• Byte Write Mode
• Write Cycle Completion Indication
• DATA Polling
• On Chip Timer
• Automatic Erase Before Write
• High Endurance
• 10,000 Cycles/Byte
• 10 Year Data Retention
• Power Up/Down Protection Circuitry
• 200 ns Maximum Access Time
• Military and Extended Temperature Range
Available.

SEEQ's 28C256 is a CMOS 5V only, 32K x 8 Electrically Erasable Programmable Read Only Memory
(EEPROM). It is manufactured using SEEQ's advanced 1.25 micron CMOS Process and is available in
both a 28 pin Cerdip package as well as a Leadless
Chip Carrier (LCC). The 28C256 is ideal for applications which require low power consumption, nonvolatility and in system reprogrammability. The
endurance, the number of times a byte can be written,
is specified at 10,000 cycles per byte and is typically
1,000,000 cycles per byte. The extraordinary high
endurance was accomplished using SEEQ's proprietary oxynitride EEPROM process and its innovative
Q CelfM design. System reliability, in all applications,
is higher because of the low failure rate of the Q Cell.
The 28C256 has an internal timer which
automatically times out the write time. The onchip timer, along with input latches free the micro-

Pin Configuration
DUAL-IN-LiNE
TOPVIEW

Au
A12
A7
As
As
A_
A3
A2
A1
Ao

E2
MEMORY
ARRAY

1/0 0
1/0,
1/02

GND

2S

.
3

25

5

6

PLASTIC LEADED CHIP CARRIER
TOP VIEW

Vee

WE

A8

A13
As
Ag
An

A'1
NC

Ag

OE

A2

OE

A10

A,o

9

CE

10

1/0 7
1/0 6
1/0 5
1/0_
1/0 3

l'

'2
'3

,.

'6
'5

CE
1/07
1/0 0

2,

I/0s

Pin Names
Ao-s

ADDRESSES - COLUMN

A6-1.

ADDRESSES - ROW

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1100'"7

DATA INPUT (WRITE)/DATA
OUTPUT (READ)

1/00.7

o Cell is a trademark of SEEO Technology, Inc.
L--·6;E~E~C;~

--

Technology, Incorpof8ted _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-J

M040002010

1-59

28C256
PRELIMINARY DATA SHEET

processor for other tasks while the part is busy
writing. The 28C256's write cycle time is 10 ms
maximum. An automatic erase is performed before
a write. The DATA polling feature of the 28C256
can be used to determine the end of a write cycle.
Once the write cycle has been completed, data
can be read in a maximum of 200 ns. Data retention is greater than 10 years.

Device Operation
Operational Modes
There are five operational modes (see Table 1)
and, except for the chip erase mode, only TTL
inputs are required. A Write can only be initiated
under the conditions shown. Any other conditions
for GE, DE, and WE will inhibit writing and the I/O
lines will either be in a high impedance state or
have data, depending on the state of the a forementioned three input lines.

Tab Ie 1
Mod e Selection
MO DE

CE

OE

WE

I/O

Rea d

VIL

VIL

VIH

DouT

Sta ndby

VIH

X

X

HIZ

Writ e

VIL

VIH

VIL

DIN

X
X

X

VIH

VIL

X

HI Z/DouT
HI Z/DouT

VIL

VH

VIL

X

Writ e
Inhi bit
Chi p Erase

Writes
To write into a particular location, the address must
be valid and a TTL low applied to the Write Enable
(WE) pin of a selected (CE low) device. This combined with Output Enable (DE) being high
initiates a write cycle. During a byte write cycle, all
inputs except data are latched on the falling edge
ofWEorCE, whichever occurred last. Write enable
needs to be at a TTL low only for the specified twp
time. Data is latched on the rising edge of WE or
CE, whichever occurred first. An automatic erase
is performed before data is written.
The 28C256 can write both bytes and blocks of up
to 64 bytes. The write mode is discussed below.

Write Cycle Control Pins
For system design simplification, the 28C256 is
designed such that either the CE or WE pin can
be used to initiate a write cycle. The device uses
the latest high-to-Iow transition of either CE or WE
signal to latch addresses and the earliest low-tohigh transition to latch the data. Address and DE
sefJ!.E and hold are with respect to the later of CE
or WE; data set u~nd hold is with respect to the
earlier of WE or C£
To simplify the following discussion, the WE pin is
used as the write cycle control pin throughout the
rest of this data sheet. Timing diagrams of both
write cycles are included in the AC Characteristics.

x: anyTT L level
VH: Hig h Voltage

Rea ds
A read is typically accomplished by presenting the
addresses of the desired byte to the address
inputs. Once the address is stable, CE is brought
to a TTL low in order to enable the chip. The WE pin
must be at a TTL high during the entire read cycle.
The output drivers are made active by bringing
Output Enable (DE) to a TTL low. During read, the
addresses, CE, DE, and input data latches are
transparent.

seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

MD400020lD

1-60

28C256
PRELIMINARY DATA SHEET

Write Mode

DATA Polling

One to 64 bytes of data can be randomly loaded
into the device. The part latches row addresses,
A6-A 14, during the first byte write. These
addresses are latched on the falling edge of the
WE signal and are ignored after that until the end
of twe. This will eliminate any false write into
another page if different row addresses are
applied and the page boundary is crossed.

The28C256 hasa maximum write cycle time of 10
ms. Typical/y though, a write will be completed in
less than the specified maximum cycle time. DATA
polling is a method of minimizing write times by
determining the actual endpoint of a write cycle. If
a read is performed to any address while the
28C256 is still writing, the device will present the
ones-complement of the last byte written. When
the 28C256 has completed its write cycle, a read
from the last address written will result in valid
data. Thus, software can simply read from the part
until the last data byte written is read correctly. A
DATA polling read should not be done until a
minimum of tLpmicroseconds after the last byte is
written. Timing for a DATA pOlling read is the same
as a normal read once the tLP specification has
been met.

The column addresses, AO-A5, which are used to
select different locations of the page, are latched
every time a new write is initiated. These
addresses and the OE state (high) are latched on
the falling edge of WE signal. For proper write
initiation and latching, the WE pin has to stay low
for a minimum of twp ns. Da ta is latched on the rising
edge of WE, aI/owing easy microprocessor
interface.
Upon a low to high WE transition, the 28C256
latches data and starts the internal page load timer.
The timer is reset on the falling edge of the WE
signal if another write is initiated before the timer
has timed out. The timer stays reset while the WE
pin is kept low. If no additional write cycles have
been initiated in (tsLC) after the last WE low to high
transition, the part terminates the page load cycle
and starts the internal write. During this time
which takes a maximum of 10 ms, the device
ignores any additional write attempts. The part
can now be read to determine the end of write
cycle (DATA Polling).

Chip Erase
Certain applications may require aI/ bytes to be
erased simultaneously. This feature, which
requires high voltage, is optional and timing
specifications are available from SEEQ.

Power Up/Down Considerations
There is internal circuitry to minimize a false write
during power up or power down. This circuitry prevents writing under anyone of the following
c.onditions:
1. Vee is less than VW1 V
2. A high to low Write Enable (WE) transition has
not occurred when the Vee supply is between
VW1 V and Vee with r:;E low and OE high.

Extended Page Load
In order to take advantage of the page mode's faster average byte write time, data must be loaded at
the page load cycle time (tsLd. Since some
applications may not be able to sustain transfers
at this minimum rate, the 28C256 permits an
extended page load cycle. To do this, the write
cycle must be "stretched" by maintaining WE low,
assuming a write enable-control/ed cycle, and
leaving aI/ other control inputs (CE, OE) in the proper page load cycle state. Since the page load
timer is reset on the falling edge of WE, keeping
this signal low will inhibit the page load timer.
When WE returns high, the input data is latched
and the page load cycle timer begins. In CE control/ed write the same is true, with CE holding the
timer reset instead of WE.

seeQ

Writing will also be inhibited when WE, CE, or OE
are in TTL logical states other than that specified
for a byte write in thp. Mode Selection table.

Technology, Incorpof8ted _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _......l

MD400020lD

1-61

28C256
PRELIMINARY DATA SHEET

Absolute Maximum Stress Range*

*COMMENT: Stresses above those listed under
"Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at
these or any other conditions above those
indicated in the operational sections of this
specification is not implied. Exposure to absolute
maximum rating conditions for extended periods
may affect device reliability.

Temperature
Storage .................... -65°C to +150°C
Under Bias . ................. -10°C to +80°C
D. C. Voltage applied to all Inputs or Outputs
with respect to ground . ..... +6.0 Vto -0.5 V
Undershoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respectto ground . ............. -1.0 V
Overshoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground . ........... , + 7.0 V

Recommended Operating Conditions
28C256

I Temperature Range
I Vcc Supply Voltage

(Ambient) O°C to 70°C
5 V± 10%

Endurance and Data Retention
Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TDR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

Symbol

DC Characteristics Read Operation

Condition

(Over operating temperature and VccRange, unless otherwise specified)

Limits
Symbol

Parameter

Min.

Max.

Units

60

mA

Test Condition
CE=OE=V'L; All I/O open;
Other Inputs = Vee Max.
Min. read or write cycle time

Icc

Active Vcc Current
Standby Vee Current
(TIL Inputs)

2

mA

IS81

CE=V'H, OE=V,L; All I/O open;
Other Inputs = V,L to V,H

Standby Vee Current
(CMOS Inputs)

150

pA

IS82

CE=Vee-0.3
Other Inputs = V,L to V,H
All I/O Open

IrL[2)

Input Leakage Current

1

pA

V'N=Vee Max.

IOL[3)

Output Leakage Current

10

pA

VouT=Vce Max.

V,L

Input Low Voltage

-0.3

0.8

V

V,H

Input High Voltage

2.0

6

V

VOL

Output Low Voltage

V

IOL=2.1 mA

VOH
VWI[1)

Output High Voltage

2.4

V

IOH=-400 pA

Write Inhibit Voltage

3.8

V

0.45

NOTES:
1. Characterized. Not tested.
2. Inputs only. Does not include I/O.
3. For I/O only.

seeQ

Technology, Incorpol8ted _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----1

MD400020lD

1-62

28C256
PRELIMINARY DATA SHEET

AC Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V

Capacitance l11

TA

E. S. D. Characteristics

= 25°C, f = 1 MHz

Symbol

Parameter

Max. Conditions

Symbol

CIN

Input Capacitance

6 pF VIN= OV

VZApI2]

COUT

Data (I/O) Capacitance

12 pF VI/o= OV

Parameter

Value

Test Conditions

E.S.D. Tolerance

> 2000V.

MIL-STD 883
Test Method 3015

AC Characteristics Read Operation (Over operating temperature and Vcc range, unless otherwise specified)
28C256-200
Symbol

Limits
28C256-300

28C256-250

Min.

tRC

Read Cycle Time

200

ns

CE=OE=VIL

tCE

Chip Enable Access Time

200

250

300

350

ns

OE=VIL

200

250

300

350

ns

CE=OE=VIL

80

90

90

90

ns

CE=VIL

80

ns

CE=VIL

ns

CE=OE=VIL

Max.

250

tAA

Address Access Time

tOE

Output Enable Access Time

tDF

Output or Chip Enable High to
output in Hi-Z

0

tOH

Output Hold from Address Change,
Chip Enable, or Output Enable,
whichever occurs first

0

60

0

Max.

300

60

Max. Units

350

0

0

Min.

80

0

0
0

Read/DATA Polling Cycle

.

.

IRC

~:

ADD RESSES

Min.

Test
Conditions

Parameter

Max.

Min.

28C256-350

-~

ADDRESS AN

NEXT ADDRESS

-

1M

-

~

"1f-

1-

teE

~~

-

;Zf..-IOF ...

-IoE-

DATA

IoH-_1

_~IoH

HIGHZ

.<
o

1M

.

DATA VALID

X.

)!Ir

DATA VALID

H t-

Notes:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized Not tested

seeQ
M040002010

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

1-63

28C256
PRELIMINARY DATA SHEET

A C Characteristics Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits

28C256-200

28C256-250

28C256-300

28C256-350

Min.

Min.

Min.

Min.

Symbol

Parameter

Max.

twc

Write Cycle Time

tAS

Address Set-up Time

20

20

20

20

ns

tAH

Address Hold Time (see note 1)

150

150

150

150

ns

tcs

Write Set-up Time

0

0

0

0

ns

tCH

Write Hold Time

0

0

0

0

ns

tcw

CE Pulse Width (note 2)

150

150

150

150

ns

tOES

OE High Set-up Time

20

20

20

20

ns

tOEH

OE High Hold Time

20

20

20

20

ns

twp

WE Pulse Width (note 2)

150

150

150

150

ns

tDS

Data Set-up Time

50

50

50

50

ns

tDH

Data Hold Time

0

0

0

0

tSlC

Byte Load Timer Cycle
(Page Mode Only) (note 3)

tlP

Last Byte Loaded
to DATA Polling Output

10

0.2

Max.

Max.

10

300

0.2

600

300

10

0.2

300

0.2

600

600

Max.

Units

10

ms

ns
300

us

600

us

Write Timing
WE CONTROLLED WRITE CYCLE

CE CONTROLLED WRITE CYCLE

WE _ _ _ _--....

CE _ _ _ ____.

WE _ _ _ _ _----.I

CE _

_____..I

~

~~~----"L~~ ~
i

_Icw_

los

-<

DATA _ _ _ _ _ _ _ _

IOH

DATA _ _ _H_I_GH_Z_ _ _ _-<

Notes:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. tSlC min. is the minimum time before the next byte can be loaded. tSlC max. is the minimum time the byte load timer waits before
initiating internal write cycle.

seeQ
MD400020/D

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

1-64

28C256
PRELIMINARY DATA SHEET

Page Write Timing
DATA POLLING

PAGE LOAD

1-

~--------~---r------~~~-----:::::-::;--------------,---~\

ADDRE,:::;SS:::E::::S__,....=;::-~~

__-"_V.:.::A::L:.:::ID~~

_ _ _ _Z:::~

~

WE------...u

~::~;'

y

-I

~r-----

DON'T CARE

I~,~t<=i

1-

~

DATA _H_IG.;.;H__Z:"-'_ _(J

Ordering Information

..-__li-----'T I28C256-~
PACKAGE
TYPE
P- PLASTIC DIP
D-CERAMIC DIP
N - PLASTIC LEADED
CHIP CARRIER
UX - UNENCAPSULATED DIE

seeQ
MD400020lD

I

-T-E-M-P-E.l..RA-T-U-R-E

PART TYPE

~

ACCESS TIME

RANGE
Q-O·Cto +70·C
(Commercial)

32K x8 EEPROM

200 =200
250=250
300=300
350=350

ns
ns
ns
ns

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-..J

1-65

1-66

seeQ

28C64A
High Speed CMOS
64K Electrically Erasable PROM

PRODUCT PREVIEW

October. 1988

Features

Block Diagram

• High Speed: 90, 120, 150 ns Access Times
• Commercial and Military Temperature Ranges
• CMOS Technology
• Low Power
• 300 mW (Typical)
• Less than 1mW Standby
• Page Write Mode: 64 Byte Page
• Fast Write: 5ms Byte/Page Write Time
• Write Cycle Completion Indication
• DATA Polling of Data Bit 7

• On Chip Timer
• Automatic Erase Before Write
• High Endurance
• 10,000 Cycles/Byte Minimum
• 10 Year Data Retention
• Power Up/Down Protection Circuitry
• JEDEC Approved Byte-Wide Pinout

1/00-7

LEADLESS CHIP CARRIER
BOTTOM VIEW
U

z

I; ~

u

z

u

z

DUAL-IN-LiNE
TOP VIEW

~ C

Vee

Description
SEEQ's 28C64A is a high speed CMOS 5V only,
8K x 8 Electrically Erasable Programmable Read
Only Memory (EEPROM). It is manufactured using
SEEQ's advanced 1.25 micron CMOS process and
is available in 28 pin Cerdip, Plastic DIP packages
and 32 pin LCC, PLCC. The 28C64A is ideal for
high speed applications which require low power
consumption, non-volatility and in-system reprogrammability. The endurance, the number of
times which a byte may be written, is specified at
10,000 cycles per byte minimum.
The 90 ns, 120 ns, 150 ns access times meet the
requirements of many of today's high performance
microprocessors. The 28C64A has an internal
timer which automatically times out the write time.
The on-chip timer, along with the input latches,
frees the microprocessor for other tasks during
the write time. The 28C64A's write cycle time is
5 msec typical. An automatic erase is performed
before a write. The Data Polling feature of the
28C64A can be used to determine the end of a
write cycle. All inputs are CMOS/TTL for both write
and read modes. Data retention is specified to be
greater than 10 years.

seeQ

WE
A7

As

A5

At

A11

NC

NC

As
At

A11

AI

OE

A2
A10

A1

CE
1/0,

1/0,

1/00

gg~

!i!

Q

z

C!I

C; 0
:::.

:::.

A:!

A10

A1

a

Au

110,

1/00

110.

1/01

1105

1/02

1104

GND

1103

Pin Names

Ao-As

ADDRESSES-COLUMN

As-A12

ADDRESSES-ROW

CE
OE

OUTPUT ENABLE

CHIP ENABLE

WE

WRITE ENABLE

1/0 0-7

DATA INPUT (WRITE)/DATA
OUTPUT (READ)

NC

NO CONNECT

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J

1-67

1-68

seeQ

28C256A
High Speed CMOS
256K Electrically Erasable PROM

PRODUCT PREVIEW

Features

October, 1988

Block Diagram

• High Speed: 90, 120, 150 ns Access Times
• Commercial and Military Temperature Ranges
• CMOS Technology
• Low Power
• 300 mW (Typical)
• Less than 1mW Standby
• Page Write Mode: 64 Byte Page
• Fast Write: 5ms Byte/Page Write Time
• Write Cycle Completion Indication
• DATA Polling of Data Bit 7

• On Chip Timer
• Automatic Erase Before Write
• High Endurance
• 10,000 Cycles/Byte
• 10 Year Data Retention
• Power Up/Down Protection Circuitry

1/00-7

Pin Configuration
DUAL-IN-LINE
TOP VIEW

LEAD LESS CHIP CARRIER
BOTTOM VIEW

• JEDEC Approved Byte-Wide Pinout

C I~

~

c c

0

z

~

Description
SEEQ's 28C256A is a high speed CMOS 5Vonly,
32K x 8 Electrically Erasable Programmable Read
Only Memory (EEPROM). It is manufactured using
SEEQ's advanced 1.25 micron CMOS process and
is available in 28 pin Cerdip, Plastic DIP packages
and 32 pin LCC, PLCC. The 28C256A is ideal for
high speed applications which require low power
consumption, non-volatility and in-system reprogrammability. The endurance, the number of
times which a byte may be written, is specified at
10,000 cycles per byte minimum.
The 90 ns, 120 ns, 150 ns maximum access times
meet the requirements of many of today's high
performance microprocessors. The 28C256A has
an internal timer which automatically times out the
write time. The on-chip timer, along with the input
latches, frees the microprocessor for other tasks
during the write time. The 28C256A's write cycle
time is 5 msec typical. An automatic erase is performed before a write. The DATA Polling feature of
the 28C256A can be used to determine the end
of a write cycle. All inputs are CMOS/TTL for both
write and read modes. Data retention is specified
to be greater than 10 years.

seeQ

As

As

A9

As

Au

Vee

A12

WE

A7

Au

A4

A11
NC

A3

OE

A2

A10

A1

CE

g ggz
0

Q

Z
CI

gg

As

As

A9

A.

A11

A3

OE

A2

A10

A1

CE

Ao

1/07

1/00

1/06

1/07
1/00

A6

1/0 1

1/05

1/0 2

110.

GND

1/03

Pin Names
Ao-A5

ADDRESSES-COLUMN

As-A14

ADDRESSES-ROW

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/0 0-7

DATA INPUT (WRITE)/DATA
OUTPUT (READ)

NC

NO CONNECT

Technology, Incorporated --------------------------~

1-69

1-70

seeQ

36C16
36C32

High Speed CMOS Electrically Erasable PROM
October, 1988

PRELIMINARY DATA SHEET

Features

Description

• High Speed:
• 35 ns Maximum Access Time
• CMOS Technology
• Low Power:
• 350mW
• 10 Year Data Retention
• High Output Drive
• Sink 16 mA at 0.45 V
• Source 4mA at 2.4 V
• 5 V ± 10% Power Supply
• Power Up/Down Protection Circuitry
• Fast Byte Write
• 5ms/Byte
• Automatic Byte Clear Before Write
• JEDEC Approved PROM Pinout
• Direct Replacement for Bipolar PROMs
• Slim 300 mil Packaging Available
• Military and Extended Temperature Range
Available.

SEEQ's 36C16/32 are high speed 2K x 8/4K x 8 Electrically Erasable Programmable Read Only Afemories,
manufactured using SEEQ's advanced 1.25 micron
CMOS Process.
The 36C16132 are intended as bipolar PROAf
replacements in high speed applications. The 35ns
maximum read access time meets the requirements
of many of today's high performance processors. The
endurance, the number of times the part can be
erasedlwritten, is specified to be greater than 100
cycles. The 36C16/32 are built using SEEQ's proprietary oxynitride EEPROAf process and its innovative
Q CelfM design.
Data retention is specified to be greater than 10 years.
The 36C16/32 are available in 24 pin Slim 300 mil
CERAAf/C DIP and PLASTIC DIP. 24/28 pin full
featured EEPROM versions are also available
(38C16/32). All parts are available in commercial as
well as military temperature ranges.

Block Diagram

Pin Configuration
DUAL-IN-LiNE
TOPVIEW
E2
MEMORY
ARRAY

36C16/36C32
(24 pins)

Vee
As
Ag

COLUMN ADDRESS
GATING

ERASE
WRITE
READ

1/0
BUFFERS
CS2
1/07
1/06

1/0 5
1/00-7

1/04

Pin Names

GND ""'-_ _. . . . 1/03

Ao-A3

ADDRESSES - COLUMN

A4- A l l (3]

ADDRESSES -

CS1
C S2
CS3

CHIP SELECT INPUTS

I/O

DATA INPUT (WRITE)

ROW
NOTES: 1. Pin 19 is A" on the 36C32.
2. CS3 is On the 36C16 only.
3. A4-A10 on 36C16

DATA OUTPUT (READ)

Q Cell is
~---

a trademark of SEEQ Technology, Inc.

SeeQ
AfD4000271B

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

1-71

36C16/36C32
PRELIMINARY DATA SHEET

Device Operation
Operational Modes
MODE PIN
Read
Standby

Write

CS,

CS2

CS3(2)

I/O

VIL

VIH

VIH

DouT

VIH

X

X

X

VIL

X

X

X

VIL

VH 1l )

VIL

X

HIZ

DIN

X: Any TTL level

Read
A read is started by presenting the addresses of
the desired byte to the address inputs. Once the
address is stable, the chip select inputs should be
brought to the proper levels in order to enable the
outputs (see Table above).

Write
To write into a particular location, addresses and
data must be valid, CS2 must be TTL low and a V/ I
pulse has to be applied to CS 1 for 5ms. An
automatic internal byte clear is done prior to the
byte write. The byte clear feature is transparent to
the user.

NOTES:
1. VH - High Voltage
2. CS3 applies only to the 36C16. This pin becomes All in the 36C32 .

......_-- SeeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

....l

MD4000271B

1-72

36C16/36C32
PRELIMINARY DATA SHEET

Absolute Maximum Rating
Temperature
Storage . . . . . . . . . . . . . . . . . . . ..
Under Bias. . . . . . . . . . . . . . . . . ..
All Inputs and Outputs
with Respect to Ground . . . . . . . ..
CS 1 with Respect to Ground ....

- 65°C to + 150°C
- 10°C to + BO°C

COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

- 3. V to + 7 V D. C.
- 0.5 V to + 14 V D. C.

Recommended Operating Conditions
36C16
36C32
5V±10%

Vee Supply Voltage
Temperature Range (Read Operation)

O°C to 70°C
(Ambient)

DC Operating Characteristics (Over operating temperature and Vee Range, unless otherwise specified)
Limits
Symbol
Icc

Parameter

Min.

Vee Active Current

Max.

Unit

Test Condition

80

rnA

CS2 = CSa =VIH ; CS 1 = VIL ;
Address Inputs = 20MHz
1I0=OmA

liN

Input Leakage Current

1

pA

0.1V> =VIN < = Vee Max.

lOUT

Output Leakage Current

10

pA

VOUT = Vee Max.

VIL

Input Low Voltage

0.8

V

2

6.5

V

10.8

13.2

V

For CS1 Input Only

0.45

V

IOL=16rnA, Vee = Vee Min.

VIH

Input High Voltage

VH

Input High Voltage During Write

VOL

Output Low Voltage

-0.5

VOH

Output High Voltage

2.4

V

losll)(2)

Output Short Circuit Current

-20

rnA

Vel 12)

Input Undershoot Voltage

-3

V

Vee Min.

10H= -4mA, Vee = Vee Min.
Vee = Vee Max, VOUT = 0
VIN undershoot pulse width < 10ns

NOTE:
1. Only one pin at a time for less than one second.
2. Characterized. Not Tested.

L....._ _ _

SeeQ
MD4000271B

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

1-73

36C16/36C32
PRELIMINARY DATA SHEET

AC Test Conditions

VzApl21

Parameter
E.S.D. Tolerance

AC Characteristics

Value
>2000 V

/J.HO

.... 90%

10%

GND

\10%

~5n8_1 ~

_

1-~5n8

INPUT PULSES

Capacitance 111

TA=25°C, f=1 MHz

Test Conditions

Symbol Parameter

Max.

MIL-STD 883
Test Method 301 5

CIN

Input Capacitance

COUT

Data (110) Capacitance

E. S. D. Characteristics
Symbol

I

3.0V

Output Load: 10 TTL gates and total CL = 30pF
Input Rise and Fall Times: < 5 ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level:
Inputs 1.5V
Outputs 1.5 V

Conditions

6 pF VIN= OV
12 pF VI/o= OV

Read Operation (Over operating temperature and Vce Range, unless otherwise specified)
LImits
36C16-35
36C32-35

Symbol

Parameter

Min.

36C16-45
36C32-45

36C16-40
36C32-40

Max.

Min.

Max.

Max.

Units

30

35

ns

40

45

55

ns

25

25

30

ns

tRC

Read Cycle Time

teE

Chip Select Access Time

25

25

lAA

Address Access Time

35

tOF

Output Enable to Output
not being driven

25

toH

Output Hold from Address
Change or Chip Select
whichever occurs first

35

Min.

45

40

0

Max.

0

0

0

•

tRe

\1

\/t/\

ADDRESSES
VALID

/~

\

CS1

CS2

CS3

\

/
J

1/

\....

J

~
toH-

~~

1/00-7

-

-tm:...

!-tcE-+

VALID
OUTPUT

~~
..

~~

~tAA_

NOTES:
This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not Tested.
3. Transition is measured at steady state level - O.SV or steady state low level + O.SV on the output from the 1.SV level on the input.
1.

seeQ
MD4000271B

Technology, Incorporated

1-74

Min.

ns

55

Read Cycle Timing

ADDRESSES

36C16-55
36C32-55

NOTE 3
NOTE 3

ns

36C16/36C32
PRELIMINARY DATA SHEET

AC Characteristics Write Operation (All Speeds)

=

(Over Vcc Range, TA 25° ± 5°C unless otherwise specified)

36C16
36C32
Symbol

Parameter

Min.

Max.

Units

twp

Write Pulse Width

5

50

ms

tAS

Address Set-up Time

0

Ils

tAH

Address Hold Time

0.5

Ils

tcs

CS 2 Set-up Time

0

IlS

tCH

CS 2 Hoid Time

0

p.S

tos

Data Set-up Time

0

IlS

tOH

Data Hold Time

0

tWR

Write Recovery

Ils

10

Ils

Write Cycle Timing
ADDRESSES

'I

--'~-tAS- : - - - - - o o f t - J

----------ofl

8.SV - - - - - - - - - - - -

Ci,

VIH

VIL _ _ _ _ _ _ _ _ _J

tea

1100-7

.~~~
~

DATA OUT

I...

t - - - - - - - W R r r E C Y C L E - - - - -........ --READ CYCLE

t-I
.
l.

NOTE:

1. cSa is Allan 36C32.

'----- SeeQ Techno/ollY, Inco'po'.ted---------------------------~
~D400027/B

1-75

36C16/36C32
PRELIMINARY DATA SHEET

Ordering/nformation

D
D

PACKAGE

D-SLIM
CERAMIC DIP
P-SLIM
PLASTIC DIP

Q
Q

36C16-35
36C32-35

=2I~

TEMPERATURE
RANGE

PART TYPE

Q-O·Cto70·C
(COMMERCIAL)

36C16-2Kx8 EEPROM
36C32 - 4K x 8 EEPROM

SPEED

35-35 "8
45-45 "8

55-55

"8

The "Preliminary Data Sheet" designation on a SEEQ data sheet indicates that the product is not fully characterized. The
specifications are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. SEEQ
Technology or an authorized sales representative should be consulted for current information before using this product. No responsibility is assumed by SEEQ for its use, nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. SEEQ reserves the right to make changes in specifications at any time and without notice.

a-...---seeQ
MD400027/ B

Technology, I n c o r p o r e t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -.......
1-76

seeQ

38C16
38C32

High Speed CMOS Electrically Erasable PROM
October, 1988

PRELIMINARY DATA SHEET

Features

Description

• High Speed:
• 35 ns Maximum Access Time
• CMOS Technology
• Low Power:
• 350mW
• High Endurance:
• 10,000 Cycles/Byte Minimum
• 10 Year Data Retention
• On-Chip Timer and Latches
• Automatic Byte Erase Before Write
• Fast Byte Write: 5 ms/Byte
• High Speed Address/Data Latching
• 50 ms Chip Erase
• 5 V ± 10% Power Supply
• Power Up/Down Protection Circuitry
• DATA Polling of Data Bit 7
• JEDEC Approved Byte Wide Pinout
• 38C16: 2816A Pin Compatible
• 38C32: 28C64 Pin Compatible
• Military and Extended Temperature Range
Available.

SEEQ's 3BC16/32 are high speed 2Kx B/4Kx B Electrically Erasable Programmable Read Only Memories
(EEPROM), manufactured using SEEQ's advanced
1_ 25 micron CMOS process_
The 3BC16/32 are ideal for high speed applications
which require non-volatility and in-system reprogrammability. The endurance, the number of times a byte
may be written, is specified at 10,000 cycles per byte
minimum. The high endurance is accomplished using

Pin Configuration

ADDRESSES - COLUMN

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/0 0-7

DATA INPUT (WRITE)
DATA OUTPUT (READ)

ROW ADDRESSES

38C32
(28 pins)

(24 pins)

Pin Names
Ao-A3
A4_ A l1[1[

DUAL-IN-LINE
TOP VIEW

38C16

A7

Vee

NC

Vee

As

As

NC

WE

As

Ag

A7

NC

A4

WE

As

As

Aa

OE

As

Ag

A2

A,o

A4

A"

OE

A,

CE

Aa

Ao

1/0 7

A2

1/00

I/0s

1/0,

1/05

1/02

1/04

GND

I/0a

A,
Ao
1/00
1/0,
1/02

GND

Block Diagram
PLASTIC LEADED CHIP CARRIER
TOPVIEW

38C16

38C32

AS
Ag

An

NC
NC

OE

A2

A,o

CE
1/07
1/00

I/0s

Q Cell is a trademark of SEEQ Technology, Inc.

---- SeeQ
MD4000291B

Techno'ogy,'ncorporated--------------------------.....
1-77

SEEQ's proprietary oxynitride EEPROM process and its
innovative "DQ cell" design. System reliability in applications where writes are frequent is increased because
of the DO-cell. The 35 ns maximum access time meets
the requirements of many of today's high performance
processors. The 38C16132 have an internal timer which
automatically times out the write time. The on-chip
timer, along with the input latches, frees the
microprocessor for other tasks during the write time.
DATA polling can be used to determine the end of a
write cycle. All inputs are TTL compatible for both write
and read modes.

38C16/38C32
PRELIMINARY DATA SHEET

Write
To write into a particularlocation, addresses must
be valid and a TTL low is applied to the write enable (WE) pin of a selected (CE low) device. This
initiates a write cycle. During a write cycle, all
inputs except for data are latched on the falling
edge of WE (or CE, whichever one occurred last).
Write enable needs to be at a TTL low only for the
specified twp time. Data is latched on the rising
edge of WE (or CE, which ever one occurred first).
An automatic byte erase is performed before data
is written.

Data retention is specified to be greater than
10 years.
The 38C16 and 38C32 are both available in
CERAMIC DIP, PLASTIC DIPand PLCCpackages.
24 pin versions of both 38C16 and 38C32 intended
for bipolar PROM replacement are also available
(36C16/36C32). All parts are available in commercial as well as military temperature ranges.

DATA Polling
The EEPROM has a specified twe write cycle time
of 5ms. The typical device has a write cycle time
faster than the t we . DATA polling is a method to
indicate the completion of a timed write cycle.
During the internal write cycle, the complement of
the data bit 7 is presented at output 7 when a read
is performed. Once the write cycle is finished, the
true data is presented at the outputs. A software
routine can be used to "poll", i.e. read the output,
for true or complemented data bit 7. The polling
cycle specifications are the same as for a read
cycle. During data polling, the addresses are
don't care.

Device Operation
Operational Modes
MODE PIN

CE

OE

WE

I/O

Read

VIL

VIL

VIH

DouT
HIZ

Standby

VIH

X

X

Write

VIL

VIH

VIL

DIN

Write
Inhibit

X

X
X

VIH

VIL

VIL
VIL

VIH
VIL

HI Z/DouT
HIZ
HI Z/DouT
No Operation
(HI Z)

VIH

VH I2]

VIH

VIH

X

Chip Erasel1 ]

X

Chip Erase
Certain applications may require all bytes to be
erased simultaneously. This feature, which
requires high voltage, is optional and timing
specifications are available from SEEQ.

HIZ

X: Any TIL level

Power Up/Down Considerations
Protection against false write during Vee power
up/down is provided through on chip circuitry.
Writing is prevented under anyone of the following
conditions:
1. Vee is less than VW1 V.
_
1. A high to low Write Enable (WE) transition has
not occurred when the Vee supply is between
VW1 V and Vee with CE low and OE high.
Writing will also be inhibited when WE, CE, or OE
are in TTL logical states other than those
specified for a byte write in the Mode Selection
table.

Read
A read is started by presenting the addresses of
the desired byte to the address inputs. Once the
address is stable, CE is brought to a TTL low in
order to enable the chip. The WE pin must be at a
TTL high during the entire read cycle. The output
drivers are made active by bringing output enable
(OE) to a TTL low. DurJng read, the address, CE,
OE, and I/O latches are transparent.

NOTES:
1. Chip erase is an optional mode.
2. VH - High Voltage.

'----- SeeQ
MD4000291B

Technology, Incorporated - - - - - - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _-J

1-78

38C16/38C32
PRELIMINARY DATA SHEET

Absolute Maximum Rating
Temperature
Storage . . . . . . . . . . . . . . . . . . . .. - 65°e to + 150 0 e
Under Bias. . . . . . . . . . . . . . . . . .. - 10 0 to + 80 0
All Inputs and Outputs
with Respect to Ground . . . . . . . .. - 3. V to + 7 V D.

e

COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

e

e.

Recommended Operating Conditions
38C16
38C32

I Vcc Supply Voltage
I Temperature Range (Ambient)

5 V± 10%
O°C to 70°C

Endurance and Data Retention
Symb()1

Parameter

N

Minimum Endurance

TOR

Data Retention

Value

Units

10,000

Cycles/Byte

Condition
M I L-STD 883 Test
Method 1033

>10

Years

MIL-STD 883 Test
Method 1008

DC Operating Characteristics (Over operating temperature and Vcc Range, unless otherwise specified)
Limits
Symbol

Parameter

Min.

Max.

Unit

Test Condition

Icc

Vee Active Current

80

mA

CE=OE=VIL ;
Address Inputs = 20M Hz
1/0=OmA

ISB

Standby Vee Current

40

mA

CE=VIH ;
All 1/0 open;
All other inputs TTL don't care;

liN

Input Leakage Current

1

pA

0.1V> =VIN < = Vee Max.

lOUT

Output Leakage Current

10

pA

VouT=Vee Max.

VIL
VIH

Input Low Voltage

-0.5

0.8

V

Input High Voltage

2

6.5

V

Vee Min.

VOL

Output Low Voltage

0.45

V

IOL = 2.1 mA, Vee = Vee Min.

VOH
VWI[1]
VeL[1]

Output High Voltage

2.4

V

IOH = - 400 pA, Vce Min.

Write Inhibit Voltage

3.8

V

Input Undershoot Voltage

-3

V

VIN undershoot pulse width < 10ns

NOTES:
1. Characterized. Not tested.

'----- SeeQ
MD4000291B

Technology, Incorporated

------------------------------1
1-79

38C16/38C32
PRELIMINARY DATA SHEET

AC Test Conditions
Output Load: 1 TTL gate and total CL = 30pF
Input Rise and Fall Times: < 5ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level:
Inputs 1.5V
Outputs 1.5 V

VZApl2)

Parameter
E.S.D. Tolerance

}.,-

'" 90%

10%

GND

1\10%

_ /-S5M

~

S5na_1

INPUT PULSES

Capacitance{1/ TA=25°C, f=1

E.S.D. Characteristics
Symbol

J

3.0V

Value

Test Conditions

Symbol Parameter
GIN

Input Capacitance

> 2000 V

MIL-STD 883
Test Method 3015

COUT

Data (I/O) Capacitance

MHz
Max.

Conditions

6 pF VIN= OV
12 pF VI/O= OV

AC Characteristics Read Operation
(Over operating temperature and Vcc Range, unless otherwise specified)
Limits
38C16-40
38C32·40

38C16-35
38C32·35
Symbol

Parameter

Min.

Max.

Min.

38C16-45
38C32·45

Max.

Min.

38C16-55
38C32·55

Max.

Max.

Min.

Units

Test
Conditions

tRC

Read Cycle Time

ns

CE=OE",VIL

tee

Chip Enable Access Time

25

25

30

35

ns

OE=VIL

tAA

Address Access Time

35

40

45

55

ns

toe

Output Enable Access Time

20

20

25

30

ns

CE=OE=VIL
CE=VIL

tOF

Output or Chip Enable to
Output Float not being Driven

15

15

25

30

ns

CE=VIL

toH

Output Hold from Address
Change, Chip Enable or
Output Enable whichever
occurs first

ns

CE or OE=VIL

40

35

0

45

0

55

0

0

.-

Read Cycle Timing
IRe

ADDRESSES

\1

/\

CE

\/

ADDRESSES
VALID

J\

\

/
J

\

OE

\

)

~
~ -toE
... tee_

1/00-7

~~

toH-

II

~to:~

VALID

OUTPUT

_tAA_
NOTES:

1. This parameter is measured
2. Characterized. Not Tested.

only for the initial qualification and after process or design changes which may affect capacitance.

3. Transition is measured at steady state level -O.5Vor steady state low level +O.5V on the output from the 1.5V level on the input.

seeQ

MD4000291B

1ieehno/oflY, Ineor'Porated

1-80

~~

NOTE 3

~~

NOTE 3

38C16/38C32
PRELIMINARY DATA SHEET

AC Characteristics Write Operation
(Over operating temperature and Vcc Range, unless otherwise specified)
38C16-35
38C32-35

Symbol

Parameter

Min.

38C16-40
38C32-40

Max.

Min.

38C16-45
38C32-45

Max.

Min.

38C16-55
38C32-55

Max.

Min.

Max.

Units

5

ms

twc

Write Cycle Time

tAS

Address Set-up Time

0

0

0

0

tAH

Address Hold Time

25

25

25

30

ns

tcs

Write Set-up Time

0

0

0

0

ns

5

5

5

ns

tcH

Write Hold Time

0

0

0

0

ns

tcw

CE Pulse Width

20

20

25

30

ns

toES

DE High Set-up Time

5

5

5

5

ns

toEH

DE High Hold Time

0

0

0

0

ns

twp

WE Pulse Width

20

20

25

30

ns
ns

tos

Data Set-up Time

20

20

25

30

tOH

Data Hold Time

0

0

0

0

top

Time to DATA Polling
from Byte Latch

35

40

ns

45

55

ns

Write Cycle Timing

CE CONTROLLED WRITE CYCLE

WE CONTROLLED WRITE CYCLE

1 + - - - - BYTE WRITE--~~-

I - - - - B Y T E WRITE----+f4-

----J1'--'I'----,----------iX

'---

I---'-----twc---~-..

WE

_______.I,'-------':r--------i
,~,

tDH~
D~A

HIGHZ
--------------~

DATA IN

~.5----

tDH:::j
O~A

HIGHZ

------------~

DATA IN

~r---

NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo

----seeQ
MD4000291B

Technology, Incorporated

--------------------------------1
1-81

38C16/38C32
PRELIMINARY DATA SHEET

Ordering Information

D Q

-'-PACKAGE
TYPE

D- CERAMIC DIP
P- PLASTIC DIP
N-PLCC

38C16-35

~Li
TEMPERATURE
RANGE

PART TYPE

Q- O·C to 70·C

38C18 - 2K x 8 EEPROM
38C32 - 4K x 8 EEPROM

(COMMERCIA~

ACCESS TIME

35-35n.
40-40M
45-45n.
55-SSM

The "Preliminary Data Sheet" designation on a SEEQ data sheet indicates that the product is not fully characterized. The
specifications are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. SEEQ
Technology or an authorized sales representative should be consulted for current information before using this product. No responsibility is assumed by SEEQ for its use, nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. SEEQ reserves the right to make changes in specifications at any time and without notice.

~------E:;~~(i) T8Chnolog~/ncorpor.ted--~------------------------------------------------------~
MD400029/S

1·82

seeQ

28C010
CMOS Timer E2
1024K Electrically Erasable PROM

PRODUCT PREVIEW

Features

October, 1988

Block Diagram

• Fast Access Times: 150, 200 ns
• Commercial and Military Temperature Ranges
• CMOS Technology
• Low Power
.300mW
• Less than 1mW Standby
• Page Write Mode: 256 Byte Page
• Fast Write: 5ms Byte/Page Write Time
• Write Cycle Completion Indication
• DATA Polling
• On Chip Timer
• Automatic Erase Before Write
• High Endurance
• 10,000 Cycles/Byte
• 10 Year Data Retention
• Power Up/Down Protection Circuitry
• JEDEC Approved Byte-Wide Pinout

000-7

Pin Configuration
LEADLESS CHIP CARRIER

DllAL-IN-UNE

BOTTOM VIEW

TOPYlEW

Vee

IV
NC

A,.
A.

Description

Ac

A,

A"
NC

SEEQ's 28C010 is a CMOS 5Vonly, 128K x 8 Electrically Erasable Programmable Read Only Memory NC
""
A,
(EEPROM). It is manufactured using SEEQ's advanced
A,
1.25 micron CMOS process and is available in both A,.
Ao
a 32 pin Cerdip package as well as a 44-pin LCC.
DOo
00,
The 28C010 is ideal for applications which require
DO,
low power consumption, non-volatility and in-system
~
8gg gg
v..
reprogrammability. The endurance, the number of
times which a byte may be written, is specified at Pin Names
10,000 cycles per byte minimum.
ADDRESSES-COLUMN
Ao-A7
The 28C010 has an internal timer which automatiADDRESSES-ROW
As-A16
cally times out the write time. The on-chip timer,
along with the input latches, frees the microprocessor
CHIP ENABLE
E
for other tasks during the write time. The 28C010's
OUTPUT ENABLE
G
write cycle time is 5 msec typical. An automatic
WRITE ENABLE
W
erase is performed before a write. The DATA Polling
DATA INPUT (WRITE)/DATA
feature of the 28CO 10 can be used to determine the
D/Oo-7
OUTPUT (READ)
end of a write cycle. All inputs are CMOS/TTL for
both write and read modes. Data retention is greater
NO CONNECT
NC
than 10 years.
DU
DON'T USE

seeQ

A..

At
At
A"

II
A,.

00,

DOe
00.
00.
DO,

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J

1-83

1-84

seeQ

MODULES Q/E~8C010

Timer E2
1024K Electrically Erasable PROM
October 1988

PRELIMINARY DATA SHEET

Features

Description

• CMOS Technology
• Military Temperature Range
• Low Power Operation
• 70 mA Active Current
• 2 mA Standby Current
• On-Chip Timer
• Automatic Erase Before Write
• 64 Byte Page Mode . .. Fast Effective
Write Time
• 80 p.sec Average Byte Write Time
• Write Cycle Completion Indication
• Data Polling
• 5V± 10% Power Supply
• Power Up/Power Down Protection Circuitry
• JEDEC Approved Byte Wide Pinout

SEEQ's MQ/ME28C010 is a CMOS 5V only,
128K x 8 Electrically Erasable Programmable Read
Only Memory (EEPROM). The MQ/ME28C010 consists of 4 28C256 (32K x 8) CMOS EEPROMs and a
2 to 4 line decoder in LCC packages, mounted on
and interconnected on a ceramic substrate. The
MQ/ME28C010 is available in a 32 pin module
package and is ideal for applications which require
low power consumption, non-volatility and insystem reprogrammability.

Pin Names
ADDRESSES

A16·AO
CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

I/O

DATA INPUT (WRITE)/DATA
OUTPUT (READ)

Pin Configuration

Block Diagram

I

A16-AO

~"""""""""......_
A16-AO~

ADDRESS

t A14-AO

A14-AO

'SLJl:l:::jl::lji::

...

~

t A14-AO

VCC

__ LJC!l:Cjl-:l:Cl;:o

WE

;:0

NC

~

A14
A13

r,Jt.----~~i~o;EI[~~~~~~r.o~E.~.:J[J[Jt J[JeJ

A8

OE - -...

A15

L..,

SEL1

A16L-... SEL2
.....

CE

CE--~~~--~EN

0

CE1

1/07-0

CE21
1
2~--~----~~----~A14-AO
CE31
3

~

CE4

DECODER

~

....

U~'UUUULl

.'iLl"

A9
1/07-0

A14

A11

AO

OE

iUU

A2

A10

A1

CE

AO
~.-

1/07

1106
1/01

1/0 5
1/04
1/0 3

seeQ
MD400066 I

Technology, Incorporated

-------------------------.....1
1-85

MQIME28C010
PRELIMINARY DATA SHEET

Writes

The MQIME28C010 has an internal timer which
automatically times out the write time. The on-Chip
timer, along with the input latches, frees the microprocessor for other tasks during the write time. The
MQIME28C010's write cycle time is 10msec maximum. An automatic erase is performed before a write.
The Data Polling feature of the MQIME28C010 can
be used to determine the end of a write cycle. Data
retention is greater than 10 years.

To write into a particular location, addressess must
be valid and a TTL low is applied to the write enable
(WE) pin of a selected (eE low) device. This combined with the output enable (OE) being high, initiates a
write cycle. During a byte write cycle, all inputs ex~t data are latched on the falling edge of WE (or
CE, whichever one occurred last). Write enable
needs to be at a TTL low only for the specified !YiP
time. Data is latched on the rising edge of WE (or eE,
whichever occurred first). An automatic erase is performed before data is written.

Device Operation
Operational Modes
There are four operational modes (see Table 1); only
r11 inputs are required. Write can only be initiated
under the conditions shown. Any other conditions
for CE, DE, and WE will inhibit writing and the liD
lines will either be in a high impedance state or have
data, depending on the state of the forementioned
three input lines.

The MQIME28C010 can write both bytes and blocks
of up to 64 bytes. The write mode is discussed
below.

Write Cycle Control Pins
For system design simplification, the MQIME28C010
is designed such that either the CE or WE pin can be
used to initiate a write cycle. The device uses the
latest high-to-Iow transition of either CE or WE signal
to latch the data. Address and DE set up and hold
are with respect to the later of CE or WE; data se!J!p
and hold is with respect to the earlier of WE or "CE-

Table 1
Mode Selection
Mode Pin

CE

READ

V,L
V,H
V,L
X
V,H
X

STANDBY
WRITE
WRITE
INHIBIT

OE
V,L
X
V,H
X
X
V,L

WE
V,H
X
V,L
V,H
X
X

I/O
DOUT
HI-Z

To simplify the following discussion, the WE pin is
used as the control pin throughout the rest of this
document. Timing diagrams of both write cycles are
included in the AC characteristics.

DIN
HI-Zor DOUT
HI-Z
HI-Z or DOUT

Write Mode

X: any CMOS/TTL level

One to 64 bytes of data can be loaded randomly into
the MQIME28C010. Address lines A15 and A16
must be held valid during the entire page load cycle.
The part latches row addresses, A6-A 14 during the
first byte write. These addresses are latched on the
falling edge of WE signal (assuming WE control write
cycle) and are ignored after that until the end of the
write cycle. This will eliminate any false write into
another page if different row addresses are applied
and the page boundary is crossed.

Reads
A read is typically accomplished by presenting the
addresses of the desired byte to the address inputs.
Once the address is stable, CE is brought to a TTL
low in order to enable the Chip. The WE pin must be
at a TTL high during the entire read cycle. The output
drivers are made active by bringing output enable
(OE) to a TTL low. During read, the addresses, CE,
CiE, and input data latches are transparent.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - -.....
MD400066

1-86

MQIME28C010
PRELIMINARY DATA SHEET

Data Polling

The column addresses, AO-AS which are used to
write into different locations of the page, are latched
every time a new write is initiated. These addresses
along with DE state (high) are latched on the falling
edge of WE signal. For proper write initiation and latching, the" WE pin has to stay low for a minimum of
t WP ns. Data is latched on the rising edge of WE,
allowing easy microprocessor interface.

The MQIME28G010 has a maximum write cycle time
of 10ms. Typically though, a write will be comp/~ted
in less than the specified maximum cycle time.
DATA polling is a method of minimizing write times
by determining the actual end point of a write .cycle.
If a read is performed to any address while the
MQIME28G010 is still writing, the device will present
the Ones-complement of the last data byte written.
When the MQIME28G010 has completed its write
cycle, a read from the last address written will result
in valid data. Thus software can simply read from the
part until the last data byte written is read correctly.
A DATA polling read should not be done until ~
minimum of tLP microseconds after the .last byte IS
written. Timing for a DATA pOlling read IS the same
as a normal read once the tLP specifications have
been met.

Upon a low to high WE transition, the MQIME28G010
latches data and starts the internal page loader
timer. The timer is reset on the falling edge of WE
signal if a write is initiated before the timer has timed
out. The timer stays reset while the WE pin is kept
low. If no more write cycles have been initiated in
(tsLC) after the last WE low to high transition, ~he part
terminates page load cycle and starts the mternal
write. During this time, which takes a maximum of
10ms, the device ignores any additional load attempts. The part can be now read to determine the
end of write cycle (DATA Polling). A 160p,s maximum
effective byte write time can be achieved if the page
is fully utilized.

Power Up/Down Considerations
There is internal circuitry to minimize a false

write
during Vee power up or down. This ~ircuitry ~~events
writing under anyone of the followmg conditions:
1. Vee is less than VWI
2 . A high to low Write Enable (WE) transition has not
occurred when the Vee supply is between VWI V
and Vee with GE low and OE high.

v.

Extended Page Load
In order to take advantage of the page mode's faster
average byte write time, data must be loaded at the
page load cycle time (tSLc)' Since some applications may not be able to sustain transfers at this
minimum rate, the MQIME28G010 permits an extended page load cycle. To do this, the write cycle
must be 'stretched' by maintaining WE low, assuming a write enable controlled cycle and leaving all
other control inputs (GE, OE) in the proper page load
cycle state. Since the page load timer is reset on the
falling edge of WE, keeping.J!J.js signal low will inhibit
the page load timer. When WE returns high, the input
data is latched and the page load cycle timer begins.
In CE controlled write the same is true, with GE
holding the timer reset instead of WE.

Writing will also be inhibited when WE, GE, ?!' OE are
in TTL logical states other than that speCified for a
byte write in the Mode Selection table.

seeQ Technology, Incorporated
MD400066

1-87

MQ/ME28C010
PRELIMINARY DATA SHEET

Absolute Maximum Stress Range *

*COMMENT: Stresses above those listed under
''Absolute Maximum Ratings" may cause permanent
damage to the device. This Is a stress rating only and
functional operation of the device at these or any
other conditions above those Indicated In the oper&tlonal sections of this specHicatlon Is not Implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Temperature
Storage . ................ - 65°C to + 150°C
Under Bias . ............. - 65°C to + 135°C
All Input or Output Voltages
with Respectto Vss . .......... +6Vto -0.5V

Recommended Operating Conditions
Temperature Range
(Ambient)

ME28C010

MQ28C010

-55°e to 85°e

ooe to 70°C

5V±10%

5V±10%

Vee Power Supply

Endurance and Data Retention
Symbol

Parameter

Value

Unit.

N
K

Minimum Endurance(4)

10,000
1,000

Cyclesl Byte

ToR

Data Retention

>10

Years

Condition
MIL-STD 833 Test
Method 1033
MIL-STD 833 Test
Method 1008

DC Charateristics
(Over operating temperature and Vee Range, unless otherwise specffied)
Limit.
Symbol

Parameter

Max.

Unit.

Icc

Active Vee Current

70

mA

CE-OE-VIL; All UO-Oma;
Addr-5MHz

ISB1

Standby Vee Current
(TTL Inputs)

10

mA

CE - 'IIH, OE. 'ilL; All UO - 0 ma;

ISBa

Standby Vee Current
(CMOS Inputs)

2

mA

CE - Vee - 0.2;
A15, A16-Vee-0.2
Other Inputs - VIH
All UO-O ma

Min.

Teat Condition

IIL(2)
lod3)

Input Leakage Current

5

~

VIN - Vee Max.

Output Leakage Current

25

VOUT - Vee Max.

VIL

Input Low Voltage

-0.3

0.8

~
V

VIH

Input High Voltage

2.0

6

V

VOL

Output Low Voltage

0.45

V

IOL-2.1 mA

VOH

Output High Voltage

2.4

V

10H- -400~

Vw1l 1)

Write Inhibit Voltage

3.8

V

NOTES:
1. Characterized. Not tested.
2. Inputs only. Does not include 110.
3. For 110 only.
4. Endurance can be specified as an option to be 1000 or 10000 cycles/byte minimum for ME28C010
and is 1000 cycles/byte minimum for MQ28C010.

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

-..1

MD400066

1-88

MQIME28C010
PRELIMINARY DATA SHEET

AC Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V

Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V

Capacitance(1) TA =25°C, t =1 MHz

E.S.D. Characteristics

Symbol

Parameter

Max.

Conditions

Symbol

CIN

Input CapaCitance

30pF

VIN=OV

VZAP(2)

COUT

Data (I/O) Capacitance

40pF

VI/O=OV

Parameter

Value

E.S.D. Tolerance > 1000 V

Test Conditions
MIL=STD 883
Test Method 3015

AC Characteristics Read Operation
(Over operating temperature and Vcc range, unless otherwise specified)
Limits
MQ28C01D-250
ME28C01D-250

Max.

MQ28C01D-300
ME28C010-300

ns

CE=OE=V!L

Min.

tRC

Read Cycle Time

250

teE

Chip Enable Access Time

250

300

350

ns

OE=VIL

tAA

Address Access Time

250

300

350

ns

CE=OE=VIL

150

ns

CE=VIL

80

ns

CE=VIL

ns

CE=OE=VIL

tOE

Output Enable Access Time

tOF

Output or Chip Enable High to
Output in Hi-Z

0

tOH

Output Hold from Address Change,
Chip Enable, or Output Enable,
whichever occurs first

0

60

350

150

150
0

Max.

Test
Conditions

Parameter

300

Min.

Units

Symbol

Min.

Max.

MQ28C01D-350
ME28C01D-350

80

0

0
0

Read/DATA Polling Cycle
1+-----tRc-----+l

ADDRESS AN

ADDRESSES

ce-----+-.. . . .

....

OE----------~------

DATA ____--...!H~IG:!!:H~Z~-----------(l7rr~~~ _----_1-----~:""ll

1+----tAA-----I

NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect
capacitance.
2. Characterized. Not tested.

seeQ
MD400066

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - -.....

1-89

MQIME28C010
PRELIMINARY DATA SHEET

AC Characteristics Write Operation
(Over the operating temperature and Vcc range, unless otherwise specified)
Limits
M028C01G-250
ME28C01G-250

Symbol

Parameter

twc

Write Cycle Time

tAS

Address Set-up Time

tAH

Address Hold Time (see note 1)

tcs

Write Set-up Time

tcH

Write Hold Time

tcw

CE Pulse Width (see note 2)

tOES

OE High Set-up Time

Min.

M028C01G-3OO
ME28C01G-3OO

Max.

Min.

10

tOEH

OE High Hold Time
WE Pulse Width (see note 2)

tos

Data Set-up Time

tOH

Data Hold Time

tBlC

Byte Load Timer Cycle (Page Mode Only)

Min.

10

Max.

Units

10

ms

20

20

20

ns

150
0
0
150

150
0
0
150
20

150
0
0
150

ns

20

ns

20

twp

Max.

MQ28C01D-350
ME28C01D-350

ns
ns
ns

20

20

20

ns

150
50
0
0.2

150
50
0
0.2

150
50
0
0.2

ns

200

200

ns
ns

200

p.s

1

ms

(see note 3)

1

Last Byte Loaded to DATA POlling

tlP

1

Write Timing
WE CONTROLLED WRITE CYCLE

CE CONTROLLED

WRITE CYCLE

CE----.~01

CE--~LI

WE---""!ill

NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. talc min. is the minimum time before the next byte can be loaded. tBlC max. is the minimum time the byte
load timer waits before initiating internal write cycle.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - -.....
MD400066

1-90

MQIME28C010
PRELIMINARY DATA SHEET

Page Write Timing
PAGE L O A D - - - - - - - - - , -POLLING
DATA~

I

--------~--~------~\:::::-----:::-~::I-~~--------~,---~\

. twe

----------r
,-_J

we----.u

.

~I

~

~

=L

HIGHZ

DATA-------~

Ordering Information

L

.----- it

I

f 1"

I

1_0----.

I

PACKAGE
TYPE

TEMPERATURE
RANGE

PART TYPE

ENDURANCE

ACCESS TIME

M-MODULE

Q-O°C to 70°C

128 Kx8
EEPROM

K = 1000 Cycles
N = 10000 Cycles

250=250 ns
300=300 ns
350=350 ns

(Commercial)

E-55°C to 85°C
(Extended)

seeQ
MD400066

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - -........

1-91

1-92

FLASH

seeQ

48F512
512K FLASH™ EEPROM

PRELIMINARY DATA SHEET

October 1988

Block Diagram

Features
•
•
•
•
•
•
•
•

64K Byte FLASH Erasable Non-Volatile Memory
Low Power CMOS Process
Electrical Byte Write and Chip/Sector Erase
Input Latches for Writing and Erasing
Fast Read Access Time
Single High Voltage for Writing and Erasing
FLASH EEPROM Cell Technology
Ideal for Low-Cost Program and Data Storage
• Minimum 100 Cycle Endurance
• Optional 1000 Cycle Endurance Screening
• Minimum 10 Year Data Retention
• 5 V± 10% Vcc, 0° C to + 70° C Temperature Range
• Silicon Signature@
• JEDEC Standard Byte Wide Pinout
• 32 Pin DIP
• 32 Pin J-Bend Plastic Leaded Chip Carrier

ARRAY

128x512x8

1/°0-7

Pin Names

Pin Configurations

Ao-As

COLUMN ADDRESS INPUT

Ag-A15

ROW ADDRESS INPUT

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

vpp

i~!i:!~I~s

WRITE ENABLE

1/00-7

DATA INPUT (WRITE)/OUTPUT (READ)

N.C.

NO INTERNAL CONNECTION

Vpp

WRITEIERASE INPUT VOLTAGE

D.U.

DON'T USE

DUAL-IN-LiNE
TOP VIEW

PLASTIC LEADED CHIP
CARRIER TOP VIEW

He

A,.

A3

A7

A'3

As

As

AS

AS

~

A"

A3

Silicon Signature is a registered trademark
of SEEQ Technology.
FLASH is a trademark of SEEQ Technology.

gg~gggg

seeQ
MD400062/-

Vce
We
Ne

Technology, Incorporated

2-1

or

AZ

A,O

A,

BE

Ao

1/07

1/00

1/0e

I/O,

1/05

1/02

I/O.

Vss

1/03

48F512
PRELIMINARY DATA SHEET

tABORT delay, the sector erase will begin. The erase
is accomplished by following the erase algorithm in
figure 2. Vpp can be brought to any TTL level or left at
high voltage after the erase.

Description
The 48F512 is a 512K bit CMOS FLASH EEPROM
organized as 64K x 8 bits. SEEQ's 48F512 brings
together the high density and cost effectiveness of
UVEPROMs, with the electrical erase, in-circuit reprogrammability and package options of EEPROMs.
On-chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to
perform other tasks once write/ erase/read cycles
have been initiated. The memory array is divided into
128 sectors, with each sector containing 512 bytes.
Each sector can be individually erased, or the chip
can be bulk erased before reprogramming.
Endurance, the number of times each byte can be
written, is specified at 100 cycles with an optional
screen for 1000 cycles available. Electrical write/
erase capability allows the 48F512 to accommodate
a wide range of plastic, ceramic and surface mount
packages.

Read
Reading is accomplished by presenting a valid address
with chip enable and output enable at v'v write enable
at V,H, and Vpp at any level. See timing waveforms for
A. C. parameters.

Erase and Write
Latches on address, data and control inputs permit
erasing and writing using normal microprocessor
bus timing. Address inputs are latched on the falling
edge of write enable or chip enable, whichever is
later, while data inputs are latched on the rising edge
of write enable or chip enable, whichever is earlier.
The write enable input is noise protected; a pulse of
less than 20 ns. will not initiate a write or erase. In
addition, chip enable, output enable and write enable
must be in the proper state to initiate a write or
erase. Timing diagrams 1epict write enable controlled writes; the timing also applies to chip enable
controlled writes.

Sector Erase
Sector erase changes all bits in a sector of the array
to a logical one. It requires that the Vpp pin be brought
to a high voltage and a write cycle performed. The
sector to be erased is defined by address inputs Ag
through A 15. The data inputs must be all ones to
begin the erase. Following a write of 'FF', the part will
wait for time tABORT to allow aborting the erase by
writing again. This permits recovering from an unintentional sector erase if, for example, in loading a
block of data a byte of 'FF' was written. After the

seeQ
MD400062/-

Chip Erase
Chip erase changes all bits in the memory to a logical one. Refer to figure 3 for the chip erase algorithm.
Vpp can be brought to any TTL level or left at high
voltage after the erase.

Sector and Chip Erase Algorithm
To reduce the sector and chip erase times, a software erase algorithm is used. Refer to figures 2 and
3 for the sector erase and chip erase flow charts.

Byte Write
A byte write is used to change any 1 in a byte to a O.
To change a bit in a byte from a 0 to a 1, the byte
must be erased first via either sector erase or chip
erase.
Data are organized in the 48F512 in a group of bytes
called a sector. The memory array is divided into
128 sectors of 512 bytes each. Individual bytes are
written as part of a sector write operation. The programming algorithm for either chip or sector write is
detailed in figure 1.
Sectors are written by applying a high voltage to the
Vpp pin and writing individual non -FF bytes in sequential order. Each byte write is automatically latched
on-chip, so that the user can do a normal microprocessor write cycle and then wait a minimum of twc
ns. for the self-timed write to complete. Each byte
write incrementally programs bits that are to become
a zero. A write loop has been completed when all
non-FF data for all desired blocks have been written.
After 10 loops, a read-verification is performed. For
any bytes which do not verify, a fill-in programming
loop is performed. Sectors need not be written
separately; the entire device or any combination of
sectors can be written using the write algorithm.
the number of loops required. Sectors need not be
written separately; the entire device or any combination of sectors can be written using the write algorithm.
Because bytes can only be written as part of a sector write, if data is to be added to a partially written
sector or one or more bytes in a sector must be
changed, the contents of the sector must first be
read into system RAM; the bytes can then be added
to the block of data in RAM and the sector written
using the sector write algorithm.

Technology, Incorporated

2-2

48F512
PRELIMINARY DATA SHEET

Power Up/Down Protection

Silicon Signature

This device contains a Vcc sense circuit which
disables internal erase and write operations when
Vcc is below 3.5 volts. In addition, erases and writes
are prevented when any control input (CE, DE, WE) is
in the wrong state for writing or erasing (see mode
table).

A row of fixed ROM is present in the 48F512 which
contains the device's Silicon Signature. Silicon Signature contains data which identifies Seeq as the
manufacturer and gives the product code. This allows
device programmers to match the programming
specification against the product which is to be
programmed.
Silicon Signature is read by raising address Ag to 12
± 0.5 V. and bringing all other address inputs plus
chip enable and output enable to V,L with Vcc at 5 V.
The two Silicon Signature bytes are selected by
address input Ao- Silicon Signature is functional at
room temperature only (25°C.)

High Voltage Input Protection
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification which
must not be exceeded, even briefly, or permanent
device damage may result. To minimize switching
transients on this pin we recommend using a minimum O. 1 uf decoupling capacitor with good high
frequency response connected from Vpp to ground
at each device. In addition, sufficient bulk capacitance should be provided to minimize Vpp voltage
sag when a device goes from standby to a write or
erase cycle.

Silicon Signature Bytes
Ao

Data (Hex)

SeeqCode

VIL

94

Product code 48F512

VIH

1A

Mode Selection Table
MODE

CE

OE

WE

Vpp

A9-15

Ao·a

00-7

Read

VIL

VIL

VIH

X

Address

Address

DouT

Standby

VIH

X

X

X

X

X

HI-Z

Byte write

VIL

ViH

VIL

Vp

Address

Address

DIN

Chip erase select

VIL

VIH

VIL

TTL

X

X

X

Chip erase

VIL

VIH

VIL

Vp

X

X

'FF'

Sector erase

VIL

VIH

VIL

Vp

Address

X

'FF'

Absolute Maximum Stress Ratings
Temperature:
Storage .. ............... .
Under bias . ............. .

E.S.D. Characteristics[1]
-65°C to + 125°C
-10°C to +85°C

AI/Inputs except Vpp and
outputs with Respect to Vss. . .

+7 Vto -0.5 V

Vpp pin with respect to Vss. . . .

14 V

seeQ
MD400062/-

Symbol Parameter
VZAP

E.S.D. Tolerance

Value

Test Conditions

>2000 V MIL-STD883
Method 3015

Note 1: Characterization data-not tested.

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - -.....

2-3

48F512
PRELIMINARY DATA SHEET

Recommended Operating Conditions
Symbol Parameter

48F512
5V± 10%

Vec supply voltage
Temperature range

O°Cto 70°C
(ambient temp.)

Value

CIN

Input capacitance

COUT

Output capacitance

6 pt.
12 pt.

Test Conditions
VIN=OV
VI/O=OV

Note 2: This parameter is only sampled and not 100% tested.

DC Operating Characteristics
Over the Vec and temperature range

Limits
Min.

Symbol

Parameter

Max.

Unit

Test Conditions

IIH

Input leakage high

1

ILA

VIN= Vcc

IlL

Input leakage low

-1

ILA

VIN= 0.1 v

IOL

Output leakage

10

ILA

VIN=Vec

Vp

Program/erase voltage

11.75

13

V

VPR

Vpp Voltage during read

0

Vp

V

Ipp

Vp current
Standby mode
Read mode
Byte write
Erase

200
200
40
80

ILA
ILA
rnA
rnA

Icc1

StandbyVce current

100

ILA

CE = Vec -0.3 v

Icc2

Standby Vcc current

5

rnA

CE -VIH min.

60

rnA

CE=VIL

Icc3

Active Vcc current

VIL

Input low voltage

-0.3
2.0

VIH

Input high voltage

VOL

Output low voltage

VOH1

Output level (TTL)

VOH2

Output level (CMOS)

seeQ
MD400062/-

0.8

V

7.0

V

0.45

CE = VIH, Vpp = Vp
VIL, Vpp = Vp
Vpp= Vp
Vpp=Vp

CE =

V

IOL = 2.1 rna

2.4

V

IOH = - 4OOILA

Vcc- O.4

V

IOH = -1 OOILA

Technology, Incorporated

2-4

48F512
PREUMINARY DATA SHEET

AC Characteristics

READ

(over the Vee and temperature range)

48F512
-200
Symbol

Parameter

Min.

tRC

Read cycle time

200

tAA

Address to data

teE
toe

~todata

OEtodata

tOF

OE/~ to data float

toH

Output hold time

48F512

48F512
-250

Max.

Min.

-300

Max.

Min.

250
250
100
60

200
200
75
50
0

Unit
ns

300
300
150
100
0

0

Read Timing

Max.

300

250

ns
ns
ns
ns
ns

-1----,.*_-

----,.J:=--:..:::::::-_-_tRC..:::::::-_-_
ADDRESS

----",1"'.•

-=--=--=--------t-AA-_-_-_-_-_-_-~.-,- - - - - - - - - - - - - - - - - - -

1~.7---------~~

WE

___

J~--------~·'-----'1

I

AC Test Conditions
Output load: 1 TTL gate and C(load) 100 pf.
Input rise and fall times: < 20 ns.
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level:
Inputs 1 Vand 2 V
Outputs 0.8 Vand 2 V

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MD400062/-

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2-5

48F512
PRELIMINARY DATA SHEET

AC Characteristics

BYTE WRITE

(Over the Vcc and temperature range)

48F512
·200
Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

tcs
tcH

CE setup time
CE hold time

toES

2
250
0
0
10
10
20
100
50
0
100
100

tOEH

OE setup time
OE hold time

tAS

Address setup time

tAH

Address hold time

tos

Data setup time

tOH

Data hold time

twp

WE pulse width

twc

Write cycle time

tWR

Write recovery time

48F512
·250

Max.

150
1.5

Min.

2
250
0
0
10
10
20
100
50
0
100
100

48F512
·300

Max.

150
1.5

I

Min.

2
250
0
0
10
10
20
100
50
0
100
100

Max.

Unit

f..Ls
f..Ls
ns
ns
ns
ns
ns
ns
ns
ns
ns

150
1.5

f..Ls
ms

Note: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the user
must provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device, e.g. access
time, erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.

Byte Write Timing

ADDRESS ____

,~-+----~,----_it;~----JX~..........--

"°0-7 ---,.,.lol+--.,."---.....,;.~-----

,----

'----it----_f
~-------twR------~

~--------~--------~

.-----BYTE WRITE -------t
BYTE #1

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MD400062/-

Technology, Incorporated

2·6

BYTE WRITE
BYTE #2

BYTE WRITE -----t
LAST BYTE

48F512
PRELIMINARY DATA SHEET

Figure 1
4BF512 Write Algorithm

SETVpp=Vp
WAIT Tvps
LOOP_COUNT=1

RE·WRITE
BYTE
WAITTwcllS

SET ADDRESS
1 ST LOCATION

RE-WRITE BYTE
WAIT
Twc+ lWrllS

SET ADDRESS
1 ST LOCATION

WRITE BYTE
WAITTwcllS
INC. ADDRESS

INCREMENT
ADDRESS

YES

INCREMENT
LOOP_COUNT

NO

END

INCREMENT
LOOP_COUNT

WAITTwrllS
LOOP_COUNT=1

NO

DEVICE
FAILED

M=10
N=6

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD4000621-

2-7

48F512
PRELIMINARY DATA SHEET

SECTOR ERASE

AC Characteristics
(Over the Vee and temperature range)

48F512
-250

48F512
-200
Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

2
500
0
0
20
100
50
0
100
0
0

Symbol

tcs

~setuptime

toES

OE setup time

tAS

Address setup time

tAH

Address hold time

tos

Data setup time

tOH

Data hold time

twp

WE pulse width

tcH

~holdtime

toEH

OEholdtime

tERASE

Sector erase time

tABORT

Sector erase delay

tER

Erase recovery time

Max.

Min.

48F512
-300

Max.

Max.

2
500
0
0
20
100
50
0
100
0
0

2
500
0
0
20
100
50
0
100
0
0
500
250
250

Min.

J.Ls
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns

500
250
250

500
250
250

Unit

ms

J.Ls
ms

Sector Erase Timing
Vp
!4-------tVPH------·, \ - - - - - - - - -

ROW
ADDRESSES - - - - - - ' . , ........--t-t-----I--'~'---T~------' ' - _ _ _ _

+-_---J '______

110 0-7

OE

_ _ _ _---J

------+-'

WE _ _---J
14-----tERASE-----~

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MD400062/-

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2-8

48F512
PRELIMINARY DATA SHEET

Figure 2
4BF512 Sector Erase Algorithm

WRITEFF
TO SECTOR
ADDRESS

INCREMENT
LOOP_COUNT

VERIFY ALL
SECTOR
BYTES=FF

DEVICE FAILED

L=30

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Technology, Incorporated

2-9

48F512
PRELIMINARY DATA SHEET

CHIP ERASE

AC Characteristics
(Over the Vcc and temperature range)

48F512
-200

48F512
-250

48F512
-300

Symbol

Parameter

tvps

Vpp setup time

2

2

2

J.Ls

tVPH

Vpp hold time

500

500

500

ms

tcs

CE setup time

0

0

toES

OE setup time

0

0

0
0

ns
ns

Max.

Min.

Min.

Max.

Min.

Max.

Unit

ns

tos

Data setup time

50

50

50

tOH

Data hold time

0

0

0

ns

twp

WE pulse width

100

100

100

ns

tcH

CEholdtime

0

0

toEH

0

0

0
0

ns

OE hold time

tERASE

Chip erase time

500

500

500

ms

tER

Erase recovery time

250

250

250

ms

ns

Chip Erase Timing
Vp
VIH
Vpp

- tOH
1100-7

!-

"\

--.J

1,~.

~

\
I..

/

tVPH

\

.

f-- tcs
CE

-

OE

tOES-1
WE

---.I

--

---

II

\

1\

tCH

~tOEH

/

\

LJ

twp
i---tos

seeQ Technology, Incorporated

-'

MD4000621-

\
-tERASE

2-10

X
- -

"r---{

48F512
PRELIMINARY DATA SHEET

Figure 3
48F512 Chip Erase Algorithm

INCREMENT
LOOP_COUNT

WAIT tER mS
THEN VERIFY
ALL BYTES=FF

DEVICE FAILED

L=30

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MD400062/-

Technology, Incorporated

2-11

48F512
PRELIMINARY DATA SHEET

Ordering Information

o
-,Package

I

T...._ _---.

Device

'tYpe

Temperature
Range

D = Ceramic Dip

Q= Oto 70°C

64Kx8FLASH
EEPROM

I
Endurance

I

Access

nme

P = Plastic Dip
N

-200

48F512 K

Q

I

Blank

=100

K = 1000

=Plastic Leaded

200 = 200ns
250 = 250ns
300

Chip Carrier

=300ns

seeQ Technology, Incorporated - - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

--A

MD400062/-

2-12

seeQ

48F010
1024K FLASH™ EEPROM

ADVANCE DATA SHEET

October 1988

Block Diagram

Fftatures
• 128K Byte FLASH Erasable Non-Volatile Memory
• Low Power CMOS Process
• Electrical Byte Write and Chip/Sector Erase
• Input Latches for Writing and Erasing
•
•
•
•

Fast Read Access Time
Single High Voltage for Writing and Erasing
FLASH EEPROM Cell Technology
Ideal for Low-Cost Program and Data Storage
• Minimum 100 Cycle Endurance
• Optional 1000 Cycle Endurance Screening
• Minimum 10 Year Data Retention
.5 V± 10% Vcc, O°Cto+ 70°C Temperature Range
• Silicon Signature")
• JEDEC Standard Byte Wide Pinout
• 32 Pin DIP
• 32 Pin J-Bend Plastic Leaded Chip Carrier

ARRAY
128x1024x8

CE

WE

OErrr~_""'I--"

__"

1100-7

Pin Names
Ao-Ag

Pin Configurations
COLUMN ADDRESS INPUT

A1O- A16

ROW ADDRESS INPUT

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/00-7

DATA INPUT (WRITE)/OUTPUT (READ)

N.C.

NO INTERNAL CONNECTION

Vpp

WRITE/ERASE INPUT VOLTAGE

D.U.

DON'T USE

PLASTIC LEADED CHIP
CARRIER TOP VIEW

DUAL-IN-LINE
TOP VIEW
Vee
Wl
He

Vpp

An

"'2
A14
A13

2

As

As

26 Ag

"5

"9

A4

""
6E

All

Silicon Signature is a registered trademark
of SEEQ Technology.
FLASH is a trademark of SEEQ Technology.

"7

As

7

1

OE

A3

~~o

A2

1/07

"I

"'0

BE

1107
1100

1106
1105
1104

____...r

1103

seeQ Technology, I n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - -....
MD400063/-

2-13

48F010
ADVANCE DATA SHEET

Description
The 48F010 is a 1024K bit CMOS FLASH EEPROM
organized as 128K x 8 bits. SEEQ's 48F010 brings
together the high density and cost effectiveness of
UVEPROMs, with the electrical erase, in-circuit reprogrammability and package options of EEPROMs.
On-chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to
perform other tasks once write/ erase/read cycles
have been initiated. The memory array is divided into
128 sectors. with each sector containing 1024 bytes.
Each sector can be individually erased, or the chip
can be bulk erased before reprogramming.
Endurance, the number of times each byte can be
written, is specified at 100 cycles with an optional
screen for 1000 cycles available. Electrical write/
erase capability allows the 48FO 10 to accommodate
a wide range of plastic, ceramic and surface mount
packages.

Read
Reading is accomplished by presenting a valid address
with chip enable and output enable at V,L, write enable
at V,H and Vpp at any level. See timing waveforms for
A.C. parameters.

Erase and Write
Latches on address, data and control inputs permit
erasing and writing using normal microprocessor
bus timing. Address inputs are latched on the falling
edge of write enable or chip enable, whichever is
later, while data inputs are latched on the rising edge
of write enable or chip enable, whichever is earlier.
The write enable input is noise protected; a pulse of
less than 20 ns. will not initiate a write or erase. In
addition, chip enable, output enable and write enable
must be in the proper state to initiate a write or
erase. Timing diagrams depict write enable controlled writes; the timing also applies to chip enable
controlled writes.

Sector Erase
Sector erase changes all bits in a sector of the array
to a logical one. It requires that the Vpp pin be brought
to a high voltage and a write cycle performed. The
sector to be erased is defined by address inputs A 10
through A 16• The data inputs must be all ones to
begin the erase. Following a write of 'FF', the part will
wait for time tabort to allow aborting the erase by
writing again. This permits recovering from an unintentional sector erase if, for example, in loading a
block of data a byte of 'FF' was written. After the

seeQ
MD4000631-

tABORT delay, the sector erase will begin. The erase
is accomplished by following the erase algorithm in
figure 2. Vpp can be brought to any TTL level or left at
high voltage after the erase.

Chip Erase
Chip erase changes all bits in the memory to a logical one. Refer to figure 3 for the chip erase algorithm.
Vpp can be brought to any TTL level or left at high
voltage after the erase.

Sector and Chip Erase Algorithm
To reduce the sector and chip erase times, a software erase algorithm is used. Refer to figures 2 and
3 for the sector erase and chip erase flow charts.

Byte Write
A byte write is used to change any 1 in a byte to a O.
To change a bit in a byte from a 0 to a 1, the byte
must be erased first via either sector erase or chip
erase.
Data are organized in the 48FO 10 in a group of bytes
called a sector. The memory array is divided into
128 sectors of 1024 bytes each. Individual bytes are
written as part of a sector write operation. The programming algorithm for either chip or sector write is
detailed in figure 1.
Sectors are written by applying a high voltage to the
Vpp pin and writing individual non-FF bytes in sequential order. Each byte write is automatically latched
on-chip, so that the user can do a normal microprocessor write cycle and then wait a minimum of twe
ns. for the self-timed write to complete. Each byte
write incrementally programs bits that are to become
a zero. A write loop has been completed when al/
non-FF data for all desired blocks have been written.
After 10 loops, a read-verification is performed. For
any bytes which do not verify, a fill-in programming
loop is performed. Sectors need not be written
separately; the entire device or any combination of
sectors can be written using the write algorithm.
Because bytes can only be written as part of a sector write, if data is to be added to a partially written
sector or one or more bytes in a sector must be
changed, the contents of the sector must first be
read into system RAM; the bytes can then be added
to the block of data in RAM and the sector written
using the sector write algorithm.

Technology, Incorporated

2-14

48F010
ADVANCE DATA SHEET

Power Up/Down Protection

Silicon Signature

This device contains a Vcc sense circuit which
disables internal erase and write operations when
Vcc is below 3.5 volts. In addition, erases and writes
are prevented when any control input (CE, OE, WE) is
in the wrong state for writing or erasing (see mode
table).

A row of fixed ROM is present in the 48F010 which
contains the device's Silicon Signature. Silicon Signature contains data which identifies Seeq as the
manufacturer and gives the product code. This allows
device programmers to match the programming
specification against the product which is to be
programmed.
Silicon Signature is read by raising address Ag to 12
± 0.5 V. and bringing all other address inputs plus
chip enable and output enable to V,L with Vcc at 5 V.
The two Silicon Signature bytes are selected by
address input Ao. Silicon Signature is functional at
room temperature only (25°C.)

High Voltage Input Protection
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification which
must not be exceeded, even briefly, or permanent
device damage may result. To minimize switching
transients on this pin we recommend using a minimum O. 1 uf decoupling capacitor with good high
frequency response connected from Vpp to ground
at each device. In addition, sufficient bulk capacitance should be provided to minimize Vpp voltage
sag when a device goes from standby to a write or
erase cycle.

Silicon Signature Bytes
Ao

Data (Hex)

Seeq Code

VIL

94

Product code 48F01 0

VIH

1C

Mode Selection Table
MODE

CE

OE

WE

Vpp

A10-16

Ao-g

00-7

Read

VIL

VIL

VIH

X

Address

Address

DouT

Standby

VIH

X

X

X

X

X

HI-Z
DIN

Byte write

VIL

VIH

VIL

Vp

Address

Address

Chip erase select

VIL

VIH

VIL

TTL

X

X

X

Chip erase

VIL

VIH

VIL

Vp

X

X

'FF'

Sector erase

VIL

VIH

VIL

Vp

Address

X

'FF'

Absolute Maximum Stress Ratings
Temperature:
Storage . ................ .
Underbias . ............. .
All Inputs except Vpp and
, outputs with Respect to Vss. . .
Vpp pin with respect to Vss . ...

E.S.D. Characteristics[1]
-65°C to + 125°C
-10°Cto+85°C

Symbol Parameter
VZAP

+7 Vto -0.5 V
14 V

E.S.D. Tolerance

Value

Test Conditions

>2000 V MIL-STD883
Method 3015

Note 1: Characterization data-not tested.

~~~~~~oo~g~~~~O~~d--------------------------~
MD400063/-

2-15

48F010
ADVANCE DATA SHEET

Capacitance[2] TA=25°C, t=1

Recommended Operating Conditions

Symbol Parameter

48F010

Temperature range

O°Cto 70°C
(ambient temp.)

Value

CIN

Input capacitance

COUT

Output capacitance

5V± 10%

Vce supply voltage

MHz
Test Conditions

6 pt.

VIN=OV

12 pf.

VI/O=OV

Note 2: This parameter is only sampled and not 100% tested.

DC Operating Characteristics
Over the Vcc and temperature range
Limits
Symbol

Parameter

Max.

Unit

Test Conditions

IIH

Input leakage high

1

J.LA

VIN=Vec

IlL

Input leakage low

-1

J.LA

VIN =0.1 v

IoL

Output leakage

10

J.LA

VIN=Vce

Vp

Program/erase voltage

11.75

13

V

VPR

Vpp Voltage during read

0

Vp

V

Ipp

Vp current
Standby mode
Read mode
Byte write
Erase

200
200
40
80

J.LA
J.LA
mA
mA

CE = VIH. Vpp = Vp
CE = VIL. Vpp = Vp
Vpp=Vp
Vpp=Vp

lec1

Standby Vee current

100

J.LA

CE = Vec -0.3 v

lec2

Standby Vee current

5

mA

CE - VIHrnin.

lec3

Active Vee current

60

mA

CE=VIL

VIL

Input low voltage

-0.3

0.8

V

VIH

Input high voltage

2.0

7.0

V

VOL

Output low voltage

0.45

VO H1

Output level (TTL)

VOH2

Output level (CMOS)

seeQ
MD400063/-

Min.

V

IOL = 2.1 rna

2.4

V

IOH = -400J.LA

Vee- O.4

V

IOH = -100J.LA

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--J

2-16

48F010
ADVANCE DATA SHEET

READ

AC Characteristics
(over the Vec and temperature range)

Symbol

Parameter

Min.

tRC

Read cycle time

200

tAA

Address to data

tCE

CEtodata

tOE

OEto data

tDF

OE/CE to data float

tOH

Output hold time

48F010

48F010
-250

48F010
-200
Max.

Min.

-300

Max.

250
200
200
75
50

0

Min.

250
250
100
0

Unit
ns

300
300
150
100

60
0

Max.

300

ns
ns
ns
ns
ns

-tRC----.l*
Read Timing

JI-:

ADDRESS
1/0

0-7

----...J~l'-I:=-=-=-=-=-=--tA-A-------=--------.J.-!--------------' ~-----.....

---------'-----.Jl---------~r'----_..t-----

WE

I

AC Test Conditions
Output load: 1 TTL gate and C(/oad) 100 pf.
Input rise and fall times: < 20 ns.
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level:
Inputs 1 Vand 2 V
Outputs 0.8 V and 2 V

seeQ
MD400063/-

Technology, Incorporated

2-17

48F010
BYTE WRITE

AC Characteristics
(Over the Vee and temperature range)

48F010
·200
Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

tcs

~setuptime

tcH

~holdtime

tOES
tOEH

OE setup time
OE hold time

tAS

Address setup time

tAH

Address hold time

tos

Data setup time

2
250
0
0
10
10
20
100
50
0
100
100

tOH

Data hold time

twp

WE pulse width

twe

Write cycle time

tWR

Write recovery time

48F010
·250

Max.

150
1.5

Min.

2
250
0
0
10
10
20
100
50
0
100
100

48F010
-300

Max.

150
1.5

Min.

2
250
0
0
10
10
20
100
50
0
100
100

Max.

UnIt
Il8
IJ8

n.
ns
ns
ns
n.
n.
n.
n.
n.
150
1.5

IJ8
ma

Note: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as I minimum time; the user
must provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device, •.g. ICC8II
time, erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.
Advance Data Sheets contain target product specifications which are subject to change upon device characterization over the full specified
temperature range. These specifications may be changed at any time, without notice.

Byte Write Timing
lc'
Vpp

ADDRESS

1/0

0-7 - - - " ,

"H--.,,-----r.~----

\\,..,----'
___n _ _ _

f

1 4 - - - BYTE WRITE---.....-I

seeQ
MD4000631-

BYTE #1

Technology, Incorporated

2-18

BVTEWRITE
BVTE#2

,,/

48F010
ADVANCE DATA SHEET

Figure 1
48F010 Write Algorithm

SETVpp=Vp
WAIT Tvps
LOOP_COUNT=1

RE-WRITE
BYTE
WAITTwcjlS

SET ADDRESS
1ST LOCATION

RE-WRITE BYTE
WAIT
Twc+ TwrjlS

SET ADDRESS
1ST LOCATION

WRITE BYTE
WAITTwcjlS
INC. ADDRESS

INCREMENT
ADDRESS

YES

INCREMENT
LOOP_COUNT

NO

INCREMENT
LOOP_COUNT

WAITTwrjlS
LOOP_COUNT=1

DEVICE
FAILED

NO

M=10
N=6

seeQ
MD400063/-

END

Technology. Incorporated

2-19

48F010
ADVANCE DATA SHEET

SECTOR ERASE

AC Characteristics
(Over the Vee and temperature range)

48F010

48F010

·200

·250

Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

fes

2
500
0
0
20
100
50
0
100
0
0

toES

CE setup time
OJ: setup time

tAS

Address setup time

tAH

Address hold time

los

Data setup time

loH

Data hold time

twp

WE pulse width

feH

~holdtime

toEH

OE hold time

teRASE

Sector erase time

tABORT

Sector erase delay

teR

Erase recovery time

Max.

Min.

48F010
·300

Max.

2
500
0
0
20
100
50
0
100
0
0
500
250
250

Min.

Max.

2
500
0
0
20
100
50
0
100
0
0
500
250
250

Unit
I-Ls
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns

500
250
250

ms

I-Ls
ms

Sector Erase Timing
Vp

1 4 - - - - - - t v P H - - - - - - · I ....- - - - - - -

ROW

ADDRESSES -----,-..---I"t-----t-....-~""--~~----,.,

"'-----t----' '-----

1/00-7 _ _ _ _--'

OE _ _ _ _ _+'

WE

----'

seeQ
MD400063/·

14-----teRASE-----~

Technology, Incorporated

2·20

48F010
ADVANCE DATA SHEET

Figure 2
4BF010 Sector Erase Algorithm

WRITEFF
TO SECTOR
ADDRESS

INCREMENT
LOOP_COUNT

VERIFY ALL
SECTOR
BYTES=FF

DEVICE FAILED

L=30

seeQ
MD400063/-

Technology, Incorporated

2-21

48F010
ADVANCE DATA SHEET

AC Characteristics

CHIP ERASE

(Over the Vee and temperature range)

48F010
-200
Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

tcs

CE setup time

tOES

DE setup time

tDS

Data setup time

2
500
0
0
50
0
100
0
0

tDH

Data hold time

twp

WE pulse width

tcH

CE hold time

tOEH

DE hold time

tERASE

Chip erase time

tER

Erase recovery time

48F010
-250

Max.

Min.

48F010
-300

Max.

2
500
0
0
50
0
100
0
0
500
250

Min.

Max.

2
500
0
0
50
0
100
0
0
500
250

Unit
/-Ls
ms
ns
ns
ns
ns
ns
ns
ns

500
250

ms
ms

Chip Erase Timing

VIH
Vpp

1/00-7

CE

OE

WE

seeQ
MD400063/-

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----1

2-22

48F010
ADVANCE DATA SHEET

Figure 3
48F010 Chip Erase Algorithm

INCREMENT
LOOP_COUNT

WAIT tER mS
THEN VERIFY
ALL BYTES=FF

DEVICE FAILED

L=30

SOOQ
MD400063/-

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - '

2-23

48F010
ADVANCE DATA SHEET

Ordering Information

o

I

Package
Type
D = Ceramic Dip

--r-

I

Temperature
Range
Q

= a to 70°C

128K x 8 FLASH
EEPROM

I

Endurance

Blank
K

N = Plastic Leaded
Chip Carrier

MD400063/-

T

Device

P = Plastic Dip

seeQ

-200

48F010 K

Q

= 100

= 1000

-r

Access
Time
200

250 = 250ns
300

Technology, Incorporated

2-24

= 200ns
= 300ns

seeQ

27F010
1024K FLASHTM EPROM
October 1988

ADVANCE DATA SHEET

Features

Block Diagram

•
•
•
•
•
•
•
•

128K Byte FLASH Erasable Non-Volatile Memory
Low Power CMOS Process
Electrical Byte Write and Chip/Sector Erase
Input Latches for Writing and Erasing
Fast Read Access Time
Single High Voltage for Writing and Erasing
FLASH EPROM Cell Technology
Ideal for Low-Cost Program and Data Storage
• Minimum 10 Year Data Retention
.5 V± 10% Vcc

• Silicon Signature
• JEDEC Standard Byte Wide Pinout
.32 Pin DIP
• 32 Pin J-Bend Plastic Leaded Chip Carrier

ARRAY
128x1024x8

R

CE
WE

O£ITT~"""~~""'"

Pin Names
Ao-Ag

COLUMN ADDRESS INPUT

AlO- A16

ROW ADDRESS INPUT

CE

CHIP ENABLE

OE

OUTPUT ENABLE

PGM

PROGRAM

1/00-7

DATA INPUT (WRITE)/OUTPUT (READ)

N.C.

NO INTERNAL CONNECTION

Vpp

WRITE/ERASE INPUT VOLTAGE

D.U.

DON'T USE

1100.7

Pin Configurations
PLASTIC LEADED CHIP
CARRIER TOP VIEW

Silicon Signature is a registered trademark
of SEEQ Technology.
FLASH is a trademark of SEEQ Technology.

seeQ
MD400067/-

Technology, Incorporated

2-25

DUAL-IN-LINE
TOPVIEW

27F010
ADVANCE DATA SHEET

Description

Chip Erase

The 27F010 is a 1024K bit CMOS FLASH EPROM
organized as 128K x 8 bits. SEEQ's 27F010 brings
together the high density, cost effectiveness, and
reprogrammability of UVEPROMs with the electrical
erase and package options of EEPROMs.
On-chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to
perform other tasks once write/erase/read cycles
have been initiated. The memory array is divided into
128 sectors, with each block containing 1024 bytes.
Each sector can be individually erased, or the chip
can be bulk erased before reprogramming.

Chip erase changes all bits in the memory to a logical one. Refer to figure 3 for the chip erase algorithm.
Vpp can be brought to any TTL level or left at high
voltage after the erase.
.

Read

To change a bit in a byte from a 0 to a 1, the byte
must be erased first via either sector erase or chip
erase.
Data are organized in the 27F010 in a group of bytes
called a sector. The memory array is divided into
128 sectors of 1024 bytes each. Individual bytes are
written as part of a sector write operation. The programming algorithm for either chip or sector write is
detailed in figure 1.
Sectors are written by applying a high voltage to the
Vpp pin and writing individual non-FF bytes in sequential order. Each byte write is automatically latched
on-chip, so that the user can do a normal microprocessor write cycle and then wait a minimum of twc
ns. for the self-timed write to complete. Each byte
write incrementally programs bits that are to become
a zero. A write loop has been completed when aI/
non-FF data for all desired sectors have been written.
After 10 loops, a read-verification is performed. For
any bytes which do not verify, a fill-in programming
loop is performed. Sectors need not be written
separately; the entire device or any combination of
sectors can be written using the write algorithm.

Reading is accomplished by presenting a valid address
with chip enable and output enable at v'v PGM at
"'H, and Vpp at any level. See timing waveforms for
A. C. parameters.

Erase and Write
Latches on address, data and control inputs permit
erasing and writing using normal microprocessor
bus timing. Address inputs are latched on the falling
edge of PGM or chip enable, whichever is later, while
data inputs are latched on the rising edge of PGM or
chip enable, whichever is earlier. The PGM input is
noise protected; a pulse of less than 20 ns. will not
initiate a write or erase. In addition, chip enable,
output enable and PGM must be in the proper state
to initiate a write or erase. Timing diagrams depict
PGM controlled writes; the timing also applies to
chip enable controlled writes.

Sector Erase
Sector erase changes aI/ bits in a sector of the array
to a logical one. It requires that the Vpp pin be brought
to a high voltage and a write cycle performed. The
sector to be erased is defined by address inputs A 10
through A 16. The data inputs must be all ones to
begin the erase. Following a write of 'FF', the part will
wait for time tabort to allow aborting the erase by
writing again. This permits recovering from an unintentional sector erase if, for example, in loading a
block of data a byte of 'FF' was written. After the
tabort delay, the sector erase will begin. The erase is
accomplished by following the erase algorithm in
figure 2. Vpp can be brought to any TTL level or left at
high voltage after the erase.

seeQ
MD400067/-

Sector and Chip Erase Algorithm
To reduce the sector and chip erase times, a software erase algorithm is used. Refer to figures 2 and
3 for the sector erase and chip erase flow charts.

Byte Write
A byte write is used to change any 1 in a byte to a O.

Sectors need not be written separately; the entire
device or any combination of sectors can be written
using the write algorithm.
Because bytes can only be written as part of a sector write, if data is to be added to a partially written
sector or one or more bytes in a sector must be
changed, the contents of the sector must first be
read into system RAM; the bytes can then be added
to the block of data in RAM and the sector written
using the sector write algorithm.

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - -

2-26

27F010
ADVANCE DATA SHEET

Power Up/Down Protection

Silicon Signature

The 27F010 contains a Vcc sense circuit which disables internal erase and write operations when Vcc
is below 3.5 volts. In addition, erases and writes are
prevented when any control input (CE, OE, PGM) is
in the wrong state for writing or erasing (see mode
table).

A row of fixed ROM is present in the 27F010 which
contains the device's Silicon Signature. Silicon Signature contains data which identifies Seeq as the
manufacturer and gives the product code. This allows
device programmers to match the programming
specification against the product which is to be
programmed.
Silicon Signature is read by raising address Ag to 12
± 0.5 V. and bringing all other address inputs plus
chip enable and output enable to V,L with Vcc at 5 V.
The two Silicon Signature bytes are selected by
address input Ao. Silicon Signature is functional at
room temperature only (25°C.)

High Voltage Input Protection
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification which
must not be exceeded, even briefly, or permanent
device damage may result. To minimize switching
transients on this pin we recommend using a minimum 0.1 uf decoupling capacitor with good high
frequency response connected from Vpp to ground
at each device. In addition, sufficient bulk capacitance should be provided to minimize Vpp voltage
sag when a device goes from standby to a write or
erase cycle.

Silicon Signature Bytes
Data (Hex)

Ao
Seeq Code

VIL

94

Product code 27F01 0

VIH

1C

Mode Selection Table
MODE

CE

OE

PGM

Vpp

A10-16

AO-9

1/0 0-7

Read

VIL

VIL

VIH

X

Address

Address

DouT

Standby

VIH

X

X

X

X

X

HI-Z

Byte write

VIL

VIH

VIL

Vp

Address

Address

DIN

Chip erase select

VIL

VIH

VIL

TTL

X

X

X

Chip erase

VIL

VIH

VIL

Vp

X

X

'FF'

Sector erase

VIL

VIH

VIL

Vp

Address

X

'FF'

Absolute Maximum Stress Ratings
Temperature:
Storage . ................ .
Under bias .
. ....... .

E.S.D. Characteristics[ 1]
-65°C to + 125°C
-10°C to +B5°C

All Inputs except Vpp and
outputs with Respect to Vss. . .

+7 Vto -0.5 V

Vpp pin with respect to Vss ..

14 V

seeQ
MD400067/-

Symbol Parameter
VZAP

E.S.D. Tolerance

Value

Test Conditions

>2000 V MIL-STD883
Method 3015

Note 1: Characterization data-not tested.

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----1

2-27

I

27F010
ADVANCE DATA SHEET

Capacitance[2] TA=25°C, t=1

Recommended Operating Conditions
27F010

Symbol Parameter.

5V ± 10%

Vcc supply voltage
Read Temperature range

O°C to 70°C
(ambient temp.)

Write/Erase Temperature

25°C ± 5°C

MHz

Value

CIN

Input capacitance

COUT

Output capacitance

6 pt.
12 pt.

Test Conditions
VIN=OV
Vl/o=OV

Note 2: Th is parameter is only sampled and not 100% tested.

DC Operating Characteristics
Over the Vcc and temperature range

Limits

'---

Symbol

Parameter

Max.

Unit

IIH

Input leakage high

1

JlA

VIN =Vcc

IlL

Input leakage low

-1

JlA

VIN = 0.1

IOL

Output leakage

10

JlA

VIN =Vce

Min.

Test Conditions

V

Vp

Program/erase voltage

11.75

13

V

VPR

Vpp Voltage during read

0

Vp

V

Ipp

Vpcurrent
Standby mode
Read mode
Byte write
Erase

200
200
40
80

JlA
JlA
mA
mA

CE = VIH, Vpp = Vp
CE = VIL, Vpp = Vp
Vpp=Vp
Vpp=Vp

Icc1

Standby Vec current

100

JlA

CE = Vce -0.3 v

lee2

Standby Vee current

5

mA

CE - VIH min.

lec3

Active Vcc cu rrent

60

mA

CE=VIL

VIL

Input low voltage

-0.3

0.8

V

VIH

Input high voltage

2.0

7.0

V

VOL

Output low voltage

0.45

V

VOH1

Output high level (TTL)

VOH2

Output high level (CMOS)

IOL = 2.1 ma

2.4

V

IOH = -400JlA

Vee- 0.4

V

IOH = -1 OOJlA

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

----a

MD400067/-

2-28

27F010
ADVANCE DATA SHEET

AC Characteristics

READ

(over the Vcc and temperature range)

27F010
-200
Symbol

Parameter

Min.

tRC

Read cycle time

200

tAA

Address to data

teE

CEto data

tOE

OEtodata

tOF

OE/CE to data float

toH

Output hold time

27F010
-250

Max.

Min.

27F010
-300

Max.

250
200
200
75
50

0

Min.

250
250
100
60
0

Max.

300

Unit
ns

300
300
150
100
0

ns
ns
ns
ns
ns

Read Timing

~J:=-:
...::::::-_-_tR_c-=--=---==i,..---J~~-=--=--------

ADDRESS _ _ _ _

••

--tA-A-=--=------_-_-+1-"- ,_ _ _ _ _ _ _ _ _ _ _. J ' - - - - - - -

I/OO.7-----------1~____~---------~~----~

PGM

I

AC Test Conditions
Output load: 1 TTL gate and C(/oad) 100 pf.
Input rise and fall times: < 20 ns.
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level:
Inputs 1 Vand 2 V
Outputs 0.8 Vand 2 V

seeQ
MD400067/-

Technology, Incorporated

----------------------------1
2-29

27F010
ADVANCE DATA SHEET

BYTE WRITE

AC Characteristics
(Over the Vcc range)

27F010
Symbol

Min.

Parameter

tvps

Vpp setup time

tVPH

Vpp hold time

tcs

CE setup time

tCH

CE hold time

tOES

OE setup time

tOEH

OEholdtime

tAS

Address setup time

tAH

Address hold time

tDS

Data setup time

tDH

Data hold time

twp

PGM pulse width

twc

Write cycle time

tWR

Write recovery time

Max.

Unit

2

/-Ls

250
0
0
10
10
20
100
50
0
100
100

/-Ls
ns
ns
ns
ns
ns
ns
ns
ns
ns

150
1.5

/-Ls
ms

Byte Write Timing

Vpp

~~

ADDRESS

1/°0-7

__~~____~~_____x~_____

~

___

~~~

_______x=

_ _ _J

\~---'----T~--_7
~-------twR------~~

~--------twc--------~

BYTE WRITE -----~~
BYTE #1

BYTE WRITE
BYTE #2

BYTE WRITE
LAST BYTE

Note: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the user must
provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device, e.g., access time,
erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.
Advance Data Sheets contain target product specifications which are subject to change upon device characterization over the full specified
temperature range. These specifications may be changed at any time, without notice.

seeQ
MD400067/-

Technology, Incorporated

2-30

27F010
ADVANCE DATA SHEET

Figure 1
27F010 Write Algorithm

SETVpp=Vp
WAIT Tvps
LOOP_COUNT=1

RE-WRITE
BYTE
WAITTwcflS

SET ADDRESS
1 ST LOCATION

RE-WRITE BYTE
WAIT
Twc+Tw(flS

SET ADDRESS
1 ST LOCATION

WRITE BYTE
WAITTwCflS
INC. ADDRESS

INCREMENT
ADDRESS

YES

INCREMENT
LOOP_COUNT

NO

INCREMENT
LOOP_COUNT

WAITTwrflS
LOOP_COUNT=1

DEVICE
FAILED

NO

M=10
N=6

seeQ
MD400067/-

END

Technology, Incorporated

2-31

27F010
ADVANCE DATA SHEET

AC Characteristics

SECTOR ERASE

(Over the Vee range)

27F010
Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

tcs
tOES

CE setup time
DE setup time

tAS

Address setup time

2
500
0
0
20
100
50
0
100
0
0

tAH

Address hold time

tos

Data setup time

tOH

Data hold time

twp

PGM pulse width

tCH

CE hold time

tOEH

OE hold time

tERASE

Sector erase time

tABORT

Sector erase delay

tER

Erase recovery time

Max.

Unit
Ils
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns

500
250
250

ms
Ils
ms

Sector Erase Timing
Vp
f4-------tvPH---------i~1

'to--------

ROW
ADDRESSES _______J~_ _ _~----~~r'----~~------J~-------+_---J,------

1/00-7

_ _ _ _- J

OE _ _ _ _ _+'

PGM

---

seeQ
MD400067/-

'-----tERASE------.J

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

2-32

27F010
ADVANCE DATA SHEET

Figure 2
27F010 Sector Erase Algorithm

WRITEFF
TO SECTOR
ADDRESS

INCREMENT
LOOP_COUNT

VERIFY ALL
SECTOR
BVTES=FF

DEVICE FAILED

L=30

seeQ
MD400067/ -

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

2-33

27F010
ADVANCE DATA SHEET

AC Characteristics

CHIP ERASE

(Over the Vee range)

27F010
Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

2
500
0
0
50
0
100
0
0

tcs

CE setup time

tOES

OE setup time

tos

Data setup time

tOH

Data hold time

twp

PGM pulse width

tcH

CE hold time

tOEH

OE hold time

tERASE

Chip erase time

tER

Erase recovery time

Max.

Unit

/-LS
ms
ns
ns
ns
ns
ns
ns
ns

500
250

ms
ms

Chip Erase Timing

VIH
Vpp

1 4 - - - tVPH---~

1/0 0-7

CE

OE

WE

tERASE - - - - p i

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - -....
MD400067/-

2-34

27F010
ADVANCE DATA SHEET

Figure 3
27F010 Chip Erase Algorithm

INCREMENT
LOOP_COUNT

WAITtERmS
THEN VERIFY
ALL BYTES=FF

DEVICE FAILED

L=30

seeQ
MD400067/-

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1

2-35

27F010
ADVANCE DATA SHEET

Ordering Information

o
I

Package
Type

Q

27F010

I
Temperature

I

P

Device

Access
Time

128K x 8 FLASH

200 = 200ns

Range

0= Ceramic Dip

-200
--,--

EPROM

=Plastic Dip

250 = 250ns

N = Plastic Leaded
Chip Carrier

300=300ns

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - -....
MD400067/-

2-36

seeQ

KT48
FLASH™ EEPROM PROGRAMMER
May 1988

Features

Description

• Programs SEEQ FLASH EEPROMs

KT48 is a FLASH EEPROM programmer from SEEQ
Technology. The complete unit consists of a halfcard size hardware board, a ribbon cable connected
to a 40-pin ZIF DIP socket and MS/DOS compatible
software. The programmer card fits into a single
expansion slot on an IBM PCIXT/AT or IBM PC compatibles. The software is user friendly and menu
driven. The programmer currently supports erasing/
programming of SEEQ 128K-bit and 512K-bit density
FLASH EEPROMs. Software updates will provide
support for future members of SEEQ's FLASH
product family.

• Half-card size programmer board fits Into
single expansion slot on IBM PC/XT/AT, with
cable connector to a 40-pln ZIF DIP socket
• User-friendly menu driven software:
Software resides on single floppy diskette

• Can load and save buffer:
Reads/generates binary, Intel hex or Motorola
S-record files
• Easy buffer editor with different entry modes
Including string and hex
• Split EEPROM feature allows splitting of 16- or
32-bit files
• Buffer allows stacking of code/data

KT48 enables an IBM PC to be turned into a local
development station for program generation and
product prototyping. By eliminating the need for
separate downloading, the KT48 reduces the time
needed for protyping/deve/opment work. The programmer erases/programs/verifies FLASH EEPROMs
with one single socket insertion! Gone is the need for
a UV-light eraser and 20 long minutes of waiting to
erase a UV EPROM. These programmer features
make program development easy, convenient, and
cost effective.

Programmer Features:
All programmer commands are menu driven with
user-selectable options. There is an online HELP
system for programmer operation.

Erase Command: This command erases the FLASH
EEPROM and verifies erasure of the device. Errors,
if any, are reported.

Program Command: This command programs the
target device with data in the buffer memory and
performs an automatic verification of programmed
data. An automatic 'blank check' is also performed
on the target device before programming. Errors, if
any, are reported.

Verify Erase Command: This command is similar to
a 'Blank Check: Checks target device to see if it is
erased. Errors, if any, are reported.
Verify Data Command: This command compares
target device data to buffer data. Errors, if any, are
reported.

~~~~~C~O~~~~~O~~d------------------------~
MD400058/-

2-37

Read Command: This command reads target device
data into the buffer. Buffer size is automatically
determined by the selection of the target device type.

Configure System Command: This command
allows the user to specify port address selection for
the programmer card, specify Vee voltage levels
during programming/erase and verify operations,
select Vpp voltage during progamming/erase and
Enable or Disable 'Beeper' sound prompts.
Select Buffer Pointer Command: This command is
used to change the Buffer Pointer, normally O. Using
this command the user can divide or shuffle datal
code for simplified partitioning into multiple FLASH
EEPROM devices. For example, a 64K-byte large
code can be split into four 16K-byte blocks-each
small enough to be accommodated on a single 48128
device. Data can also be stacked into the buffer. For
example, two 2764s (8K-bytes each) can be read into
the buffer and re-programmed into a Single 48128.
Split FLASH EEPROM Command: Using this
command, 16- or 32-bit wide data can be split and
programmed into standard 8-bit wide devices.

Display/Modify Buffer Command: This command

Read File Command: This command reads a
specified file from a disk into the buffer. Buffer size is
determined by target device type selection. Binary,
Intel HEX and Motorola S-record formats are supported. File Off-set option allows files to be off-set
into the buffer as desired by the user.

Save File Command: This command allows buffer
data to be saved to a disk under a specified file name.
Binary, Intel HEX and Motorola S-record formats are
supported. Buffer size i.e., length of the file is determined by the device type selected. Read and Save
file commands allow 'Chip Master' copies to be
maintained.
Copy Buffer Command: This command allows a
user-defined block of buffer data to be copied into
another block with a specified starting address.
Print Buffer Command: This command writes buffer
data into a print file on the disk. The print file can be
printed for a hard copy using MSIDOS print command
or a word processing program.
Fill Buffer Command: This command fills the buffer
with user specified data. User specifies starting address and ending address for the buffer fill command.

displays buffer data. Using the buffer editor, data
can be edited. The editor supports various entry
modes including string and HEX.

Ordering Information
KT48- FLASH EEPROM Programmer

FLASH is a trademark of SEEQ Technology, Inc.

* IBM, XT, AT are trademarks of International Business Machines.
SEEQ Technology reserves the right to make changes without further notice to products and their specifications herein to improve reliability,
function or design. SEEQ does not assume any liability arising out of the application or use of any product described herein; neither does it
convey any license under its patent rights nor the rights of others. The software described herein will be provided on an 'as is' basis and
without warranty. SEEQ accepts no liability for incidental or consequential damages arising from the use of the software. SEEQ Technology
distributes the product described herein for the sole purpose of facilitating programming support of SEEQ products and does not extend any
warranty independent of that extended by the original equipment manufacturer.

~~~~Th~~~~~~~on~d--------------------------­
MD400058/-

2-38

EPROMS

(Erasable Programmable Read Only Memories)

seeQ

2764
64K EPROM

27128
128K EPROM
March 1987

Features

Description

• Fast Access Times at 0° to 70°C
- 2764 - 160 ns
- 27128 - 200 ns
• Programmed Using Intelligent Algorithm
- 21 VVpp
- 2 Minutes for 27128
- 1 Minute for 2764

SEEQ's 2764 and 27128 are ultraviolet light erasable
EPROMs whichareorganized8Kx8 and 16Kx8 respectively. They are pin for pin compatible to JEDEC
approved 64K and 128K EPROMs in all operational!
programming modes. The devices have access times as
fast as 160 ns over the 0° to 70° C temperature and Vcc
tolerance range. The access time is achieved without
sacrificing power since the maximum active and
standby currents are 100 mA and 30 mA respectively. The fast access times allow higher system
efficiency by eliminating the need for wait states in
today's 8 - or 16-bit microprocessors.

• JEDEC Approved Bytewide Pin
Configuration
- 2764 8K x 8 Organization
- 27128 16K x 8 Organization
• Low Power Dissipation
- 100 mA Active Current
- 30 rnA Standby Current

Initially, and after erasure, all bits are in the "1" state.
Data is programmed by applying 21 V to Vpp and a TTL
"0" to pin 27 (program pin). The 2764 and 27128 may be
programmed with an intelligent algorithm that is now

• Military And Extended Temperature
Range Available
• Silicon Signature ®
Block Diagram

Pin Configuration
2764/27128

q
AC

~

ROW
DECODERS

MEMORY
ARRAY

V

q

~
~

COLUMN
DECODER

---

COLUMN ADDRESS
GATING

1/0

CONTROL
LOGIC

BUFFERS

~
MODE
Read
Output Disable
Standby
Program
Program Verify

Program Inhibit
Silicon Signature *

CE
(20)
VIL
X
VIH
VIL
VIL
VIH
VIL

OE

PGM
(27)

Vpp
(1)

Vcc

(22)

VIL
VIH
X

VIH
Vee
X

VIH
VIL
X

VIL
VIH
X

Vee
Vee
Vee
Vpp
Vpp
Vpp

VIL

VIH

Vee

Vee
Vee
Vee
Vee
Vee
Vee
Vee

(28)

MD400010/-

A

A6

As

As

Ag

,3

A4

A

A3

OE"

A2

A,o

A,

CE

Ao

0 7

0 0

0 6

0,

05

[1]

NOTE 1: PIN 26 IS A NO CONNECT
ON THE 2764.

Outputs
(11-13,15-19)
DOUT
High Z
High Z
DIN
DOUT
High Z
Encoded
Data

= 12V, and all other addresses are at a TTL low.

Silicon Signature is a registered trademark of SEEQ Technology.

seeQ

PGM

A7

GND

X can be either VIL or VIH

* For Silicon Signature: Ao is toggled, A9

Vcc

A'2

02

-u

Mode Selection

Vpp

Technology, Incorporated

3-1

Pin Names
Ae
AR
CE
OE

ADDRESSES - COLUMN (LSB)
ADDRESSES - ROW
CHIP ENABLE
OUTPUT ENABLE

00- 07

OUTPUTS
PROGRAM

PGM

2764
27128
available on commercial programmers. The programming
time is typically 5 ms/byte or 2 minutes for all 16K bytes
of the 27128. The 2764 requires only half of this time,
about a minute for 8K bytes. This faster time improves
manufacturing throughput time by hours over conventional50 ms algorithms. Commercial programmers (e.g.
Data I/O, Pro-log, Digelec, Kontron, and Stag) have
implemented this fast algorithm for SE EQ's EPROMs. If
desired, both EPROMs may be programmed using the

conventional 50 ms programming specification of older
generation EPROMs.
Incorporated on SEEQ's EPROMs is Silicon Signature. Silicon Signature contains encoded data
which identifies SEEQ as the EPROM manufacturer,
the product's fab location, and programming information. This data is encoded in ROM to prevent
erasure by ultraviolet light.

Absolute Maximum Ratings
Temperature
Storage ..................... -65° C to +150° C
Under Bias .................... -10°C to +80°C
All Inputs or Outputs with
Respect to Ground ................. +6V to -0.3V
Vpp During Programming with
Respect to Ground ................ +22V to -0.3V
Voltage on A9 with
Respect to Ground .............. +15.5V to -0.3V

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Recommended Operating Conditions
2764
27128
Vce Supply Voltage (2 )

5 V± 10%
(Ambient) ooe to 700 e

Temperature Range (Read Mode)
Vpp During Programming

21 ± 0.5 V

DC Operating Characteristics During Read or Programming
limits
Min.

Symbol

Parameter

Max.

Unit

liN

Input Leakage Current

10

p,A

VIN = Vee Max.

10
Ipp(1)

Output Leakage Current

10

p,A

VOUT = Vee Max.

Read Mode

5

mA

Vpp = Vee Max.

Prog. Mode

30

mA

Vpp= 21.5V

lecl'11

Vce Standby Current

30

mA

CE=VIH

lec2(1)

Vee Active Current

100

mA

CE=OE=VIL

VIL

Input Low Voltage

-0.1

0.8

V

VIH

Input High Voltage

2

Vcc+ 1

V

VOL

Output Low Voltage

VOH

Output High Voltage

Vpp Current

0.45
2.4

Test Condition.

V

10L =2.1 mA

V

10H =-400J.l.A

NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after VPP.

seeQ
MD400010/-

Technology, Incorporated ----------------------------~

3-2

2764
27128
AC Operating Characteristics During Read
Limits

2764-16
Symbol

Parameter

27XX-20

27XX-25

27XX-30

27XX-45

Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.

tM

Address Access Time

160

200

250

300

tCE

Chip Enable to Data Valid

160

200

250

300
120

75

tOE

Output Enable to Data Valid

tDF

Output Enable to Output Float

0

tOH

Output Hold from Chip
Enable, Addresses, or
Output Enable whichever
occurred first

0

60

75
0

60

0

100
0
0

60

0
0

105

Test
Conditions

450 CE= OE= VIL
450 OE= VIL
150 CE= VIL
0
0

130 CE= VIL
CE = OE= VIL

A. C. Test Conditions

Capacitance I1 I
Symbol

Parameter

Typ.

Max.

Unit

Conditions

CIN

Input Capacitance

4

6

pF

VIN = OV

COUT

Output Capacitance

8

12

pF

VOUT = OV

Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: :s 20ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs
1V and 2V
Outputs O.BV and 2V

A. C. Waveforms

ADDRESSES

ADDRESSES
VALID

HIGH Z
OUTPUT .........................--.....----~--~~~------~~_+_+~~

~-----------tAA----------~

HIGH Z

IOH

NOTES:
1. I!:!IS PARAMETER IS SAMPLED AND IS NOT 100% TESTED.
2. OE MAY BE DELAYED TCUbA - IQLAFTER THE FALLING EDGE OF CE WITHOUT IMPACT ON 1M.
3. tOF IS SPECIFIED FROM OE OR CE, WHICHEVER OCCURS FIRST.
4. THESE ARE EQUIVALENT TEST CONDITIONS AND ACTUAL TEST CONDITIONS ARE DEPENDENT ON THE TESTER.

seeQ
MD400010/-

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---J

3-3

2764
27128
Erasure Characteristics
the column address AD- There are 2 bytes of data
avaiJable (see Table 2). The data appears on outputs
00 to 06, with 07 used as an odd parity bit. This
mode is functional at 25 ± 5° C ambient temperature.

The 64K and 128K EPROMs are erased using ultraviolet light which has a wavelength of 2537
Angstroms. The integrated dose, i.e., intensity x
exposure time, for erasure is a minimum of 15 wattsecond/cm2 . The EPROM should be placed within
one inch of the lamp tube during erasure. Table 1
shows the typical EPROM erasure time for various
light intensities.

Table 2. Silicon Signature Bytes

Table 1. Typical EPROM Erasure Time
Light Intensity
(Micro-Watts/cm 2 )

Erasure Time
(Minutes)

15,000

20

10,000

30

5,000

55

94

Product Code (Byte 1)
2764
27128

VIH
VIH

40
C1

Both EPROMs may be programmed using an intelligent algorithm or with a conventional 50 msec
programming pulse. The intelligent algorithm
improves the total programming time by approximately 10 times over the conventional 50 msec
algorithm. It typically requires only 1 and 2 minute
programming time for all 64K and 128K bits
respectively.

Incorporated in SEEQ's EPROMs is a row of mask
programmed read only memory (ROM) cells which is
outside of the normal memory cell array. The ROM
contains the EPROM's Silicon Signature. Silicon
Signature contains data which identifies SEEQ as the
manufacturer and gives the product code. This data
allows programmers to match the programming
specification against the product which is to be
programmed. If there is verification, then the programmer can proceed programming.

The intelligent algorithm requires Vee = 6V and Vpp
= 21 V during byte programming. The initial program
pulse width is one millisecond, followed by a sequence of one millisecond pulses. A byte is verified
after each pulse. A single program pulse, with a time
duration equal to 4 times the number of one millisecond pulses applied, is additionally given to the
address after it is verified as being correctly programmed. A maximum of 15 one millisecond pulses
per byte should be applied to each address. When
the intelligent algorithm cycle has been completed,
all bytes must be read at Vee = Vpp = 5V.

Silicon Signature is activated by raising address Ag to
12V ± O.5V, bringing chip enable and output enable
to a TTL low, having Vee at 5V, and having all
addresses except Ao at a TTL low. The Silicon Signature data is then accessed by toggling (using TTL)

MD400010/-

Hex Data

VIL

Programming

Silicon Signature

seeQ

Ao
SEEa Code (Byte Q)

Technology,lncorpotated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - J

3-4

2764
27128
Intelligent Algorithm Flowchart

DEVICE
FAILED

DEVICE
FAILED

seeQ
MD400010/-

Technology, Incorporated

3-5

2764
27128
Intelligent Algorithm
-.- - --V'H
ADDRESSES
VIL

.-.

PROGRAM

~

-[

VERIFY

ADDRESS STABLE

I
- - - tAs _
(2)
VIH

D~TA IN STABLE

J
\

DATA

1

~

VIIIII}

HIGHZ

---

'OH
(2)

DATA OUT

~\~\'

f

VIL

~---~~j---

,l

--

V~LlD

--

...

tAH
(0)

'OFP
(0.13)
MAX.

I

I:---

Vpp

/~

Vpp
Vee

I
~'{;~--

Vee' 1
Vee
Vee

/
f-----'{i)s---

VIH

CE
VIL

-'[-

t-------'fi)s-

VIH

t

PGM
VIL

---

I'-----J
'pw
(0.95 ms)

VIH

--

L~"1
(2)

-

'OPw
(3. 8 ms

I

~(~~~)--I
MAX.

\

OE
VIL

I

i
I

--

NOTES:
1. ALL TIMES SHOWN IN ( ) ARE MINIMUM AND IN !,SEC UNLESS OTHERWISE SPECIFIED.
2. THE INPUT TIMING REFERENCE LEVEL IS .8V FOR A VIL AND 2V FOR A VIH.
3. tOE AND tOFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER .

seeQ

Technology, Incorporated - - - - - - - - - - - - - -

3-6

._ _J

2764
27128
Intelligent Algorithm
AC Prolll'lmmlng Characterlstlcsl 4 TA = 25° ± 5°C, Vcc l11 = 6.0 V ± 0.25 v, Vpp = 21

V ± 0.5

v

Limits

Symbol

Parameter

tAS

Address Setup Time

2

J.lS

tOES

OE Setup Time

2

J.lS

tos

Data Setup Time

2

J.lS

tAH

Address Hold Time

0

J.lS

tOH

Data Hold Time

2

J.lS

Min.

tOFP

Output Enable to Output Float Delay

0

tvps

Vpp Setup Time

2

tvcs

V cc Setup Ti me

tpw l21

PGM Initial Program

Typ.

130

PGM Overprogram Pulse Width

tCES

CE Setup Time

tOE

Data Valid from OE

0.95
3.8

ms

63

ms
J.lS

Input Rise and Fall Times (10% to 90%)
Input Pulse Levels ..................
Input Timing Reference Level ........
Output Timing Reference Level ......

Orderinllinformation

D Q 27128-XX

~l~-,
O-CEROIP

Q- o'C to 70'C

PART TYPE

ACCESS TIME
18-180 na
20-200 na

(Commercial)

ns

AC Test Conditions

NOTES:
1. Vec must be applied simultaneously or before Vpp and
removed simultaneously or after VPP.
2. Initial Program Pulse width tolerance is 1 msec ± 5%.
3. The length of the overprogram pulse will vary from 3.B msec
to 63 msec as a function of the iteration counter value X.
4. For 50 ms programming, Vce = 5 V ± 5%, Tpw = 50 ms
± 10%, and Topw is not applicable.

2784-8Kx8 EPROM

25-250 na

27128-18Kx8 EPROM

30-300 na
45-450 na

MD400010/-

1.05

150

TEMPERATURE
RANGE

ns

J.lS

1.0

2

PACKAGE
TYPE

Unit

J.lS

2
Pulse Width

topwl 31

seeQ

Max.

Technology, Incorpof8ted

3-7

...... 20 ns
0.45V to 2.4V
O.BV and 2.0V
O.BV and 2.0V

3-8

seeQ

27C256
256K CMOS EPROM
March 1987

Features

Description

• 256K (32K x 8) CMOS EPROM

SEEQ's 27C256 is the industry's first 256K CMOS
EPROM. It has a 32K x 8 organization and has very
low power dissipation. Its 40 mA active current is
less than one half the active power of n-channel
EPROMs. In addition the 100 IlA Vee standby
current is orders of magnitude lower than those
same EPROMs. Consequently, system memory sizes
can be substantially increased at a very small
increase in power. Low active and standby power is
important in applications which require portability,
low cooling cost, high memory bit density, and long
term reliability.

• Ultra Low Power
• 100 pA Max. Vcc Standby Current
• 40 mA Max. Active Current
• Programmed Using Intelligent Algorithm
• 12.5 VVpp
• 200 ns Access Times
. 5 V±10% Vcc
• 0° to 70°C Temperature Range
• Minimum 10 Year Data Retention
• JEDEC Approved Bytewide Pin
Configuration

The 27C256 is specified overthe 0° to 70°C temperature range and at 5 V± 10% Vco The access time is
specified at 200 ns, making the 27C256 compatible
with most of today's microprocessors. Its inputs and
outputs are completely TTL compatible.

• Silicon Signature®
• Military And Extended Temperature Range
Available.

Block Diagram
Pin Configuration
27C256
Vee

c=>

~

ROW
DECODERS

A,.

MEMORY
ARRAY

V

A'3
As
A9

A"

5E

A3
Ao-As

c=>

--

~

COLUMN
DECODER

COLUMN ADDRESS
GATING

v'

A2

A,o

A,

CE
0,

O.
1/0

CONTROL
LOGIC

-u

PINS
Read
Output Disable

0.
03

00-7

Mode Selection
MODE

°5

0,

BUFFERS

CE
(20)

Outputs
(11-13,15-19)

OE
(22)

Vpp

VCC

(1)

(28)

VIL

VIL

Vee

Vee

X

VIH

Vee

Vee

DOUT
High Z

Pin Names

Standby

VIH

X

High Z

Ao- A5

ADDRESSES -

COLUMN (LSB)

VIL

VIH

Vee
Vpp

Vee

Program

Vee

DIN

A6- A14

ADDRESSES -

ROW

Program Verify

VIH
VIH

VIL

Vpp

Vee

CHIP ENABLE

Vpp

Vee

OE

OUTPUT ENABLE

Silicon Signature™*

VIL

VIH
VIL

DOUT
High Z

CE

Program Inhibit

Vee

Vee

Encoded
Data

00-07

OUTPUTS

X can be either VIL or \lIH.
*'For Silicon Signature: Ao is toggled, Ag = 12 V, and all other addresses are at a TTL low.
Silicon Signature IS a registered trademark of SEEQ Technology.

seeQ
MD400012/-

Technology, Incorporated

3-9

27C256
Initially, and after erasure, all bits are in the "1" state.
An intelligent algorithm is used to program the
27C256 typically in four minutes. Data is programmed
using a 12.5 V Vpp and an initial chip enable pulse of
1.0ms.

Incorporated on the 27C256 is Silicon Signature.
Silicon Signature contains encoded data which identifies SEEQ as the EPROM manufacturer and gives
the product code. This data is encoded in ROM to
prevent erasure by ultraviolet light.

Absolute Maximum Ratings
*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Temperature
Storage ........................ -65°C to +150°C
Under Bias ............ .......... -10°C to +80°C
All Inputs or Outputs with
Respect to Ground ................ +6 V to -0.3 V
Vpp with Respect to Ground ...... +14.0 V to -0.3 V
Voltage on A9 with
Respect to Ground ............. +14.0 V to -0.3 V

Recommended Operating Conditions
27C25S-20, 27C25S-25,
27C25S-30, 27C25S-45,
Vee Supply Voltage l11
Temperature Range (Read Mode)

5 V ± 10%
(Ambient) O°C to 70°C

Vpp During Read(2)
Vpp During Programming(3)

Vee
12.5 ± 0.3 V

DC Operating Characteristics During Read or Programming
Limits
Symbol
hN(4)

Max_

Unit

Input leakage

1

VIN=Vec Max.

10(5)

Output leakage

10

#LA
#LA

Ipp

Vpp current
Standby mode
Read Mode
Programming mode

150
1
30

mA
mA

#LA

CE=Vcc-1 v. min.
F=5 MHz., CE=VIL
Vpp=12.5 v.

Parameter

Min.

Test Condition
VOUT=VCC Max.

ICCl

Vcc standby current

100

#LA

CE>=Vcc-1 v.

Icc2

Vcc standby current

1.5

mA

CE=VIH

Icc3

Vcc active current

40

mA

CE=OE=VIL, 0 0 - 7 =0,
F=5 MHz.

VIL

Input low voltage

VIH

Input high voltage

VOL

Output low voltage

VOH

Output high voltage

-0.1
2.0
2.4

0.8

V

Vcc+ 1

V

0.45

V

IOL=2.1 ma

V

IOH=-400 #LA.

NOTES:
1. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after VpP.
2. Vpp cannot be left floating and should be connected to Vcc during read.
3. 0.1 #LF ceramic capacitor on Vpp is required during programming only, to suppress voltage transients.
4. Inputs only. Does not include I/O.
5. For I/O only.

seeQ
MD400012/-

Technology, Incorporated

3-10

27C256

AC Characteristics Read Operation (Over Operating Temperature And Vcc Range, Unless Otherwise Specified)
Limits
Symbol

Parameter

27C256-20

27C256-25

27C256-30

27C256-45

Min.

Min.

Min.

Min.

Max.

Max.

Max.

Max.

Units

Test
Conditions
CE=OE=VIL

tM

Address Access Time

200

250

300

450

ns

tCE

Chip Enable Access Time

200

ns

OE=VIL

Output Enable Access Time

150

ns

CE=VIL

tDF

Output or Chip Enable off
To Output Float(3)

75
60

300
120

450

tOE

250
100
60

105

130

ns

CE=VIL

ns

CE=OE=VIL

Output Hold from Address
Change, Chip Enable, or
Output Enable,
whichever occurs first

tOH

0

0

0

Capacitance 111

0

A.C. Test Conditions

Symbol

Parameter

Typ.

Max.

Unit

CIN

Input Capacitance

4

6

pF

Conditions
VIN

COUT

Output Capacitance

8

12

pF

VOUT

= OV
= OV

Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: ~ 20ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
1 V and 2V
Inputs
Outputs O.BV and 2V

A.C. Waveforms
ADDRESSES

ADDRESSES
VALID

HIGHZ

110",

NOTES:
1. THIS PARAMETER IS SAMPLED AND IS NOT 100% TESTED.
2. De MAY BE DELAYED TO 1M -toe AFTER THE FALLING EDGE OF Ce WITHOUT IMPACT ON 1M.
3.loF IS SPECIFIED FROM 5E OR eE, WHICHEVER OCCURS FIRST.

seeQ
MD400012/-

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

3-11

27C256
Erasure Characteristics
12V + O.5V. bringing chip enable and output enable
to a TTL low, having Vee at 5V, and having all
addresses except Ao at a TTL low. The Silicon Signature data is then accessea by toggling Ao- The data
appears on outputs 00 to 06, with 07 used as an odd
parity bit (see Table 2).

The 27C256 is erased using ultraviolet light which
has a wavelength of 2537 Angstroms. The integrated
dose, i.e., intensity x exposure time, for erasure is a
minimum of 15 watt-second/cm 2 . The EPROM
should be placed within one inch of the lamp tube
during erasure. Table 1 shows the typical EPROM
erasure time for various light intensities.

Table 2. Silicon Signature Bytes

Table 1. Typical EPROM Erasure Time

r--Ao:---"--::D:-a-:-ta-:(;:-H;-e~x);----'

Light Intensity
Erasure Time
(Micro-Watts/cm 2 )
(Minutes)
~----~--------~----~---20
15,000
------1
10,000
30

5,000

r

l

94

VIH

C2

The 27C256 is programmed using the industry standard intelligent algorithm.
The intelligent algorithm requires Vee = 6 Vand Vpp =
12.5 V during byte programming. The initial program
pulse width is 1.0 millisecond, followed by a sequence
of 1.0 millisecond pulses. A byte is verified after each
pulse. A single program pulse, with a time duration
equal to 3 times the number of 1.0 millisecond pulses
applied, is additionally given to the address after it is
verified as being correctly programmed. A minimum of
one to a maximum of 25 1-ms pulses, plus one 3X
overpulse, may be applied to each byte. When the
intelligent algorithm cycle has been completed, all
bytes must be read at Vee = Vpp = 5 V.

Incorporated in SEEQ's EPROMs is a row of mask
programmed read only memory (ROM) cells which is
outside of the normal memory cell array. The ROM
contains the EPROM's Silicon Signature. Silicon Signature contains data which identifies SEEQ as the
manufacturer and gives the product code. This data
allows programmers to match the programming
specification against the product which is to be programmed. If there is verification, then the programmer proceeds to program.
Silicon Signature is activated by raiSing address Ag to

MD400012/-

VIL

Product Code (Byte 1)

Programming

55

Silicon Signature

~ SeeQ

SEEQ Code (Byte Q)

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

3-12

27C256
Intelligent Algorithm Flowchart

DEVICE
FAILED

DEVICE
FAILED

seeQ
MD400012/-

Technology,

,ncOrpof8ted----------------------~
3-13

27C256

Intelligent Algorithm
VERIFY

PROGRAM

X

ADDRESSES

K

ADDRESS STABLE

~IA~I
(2)

,

D~TA IN STABLE

I

DATA

~~~i-

~

1

Vpp

HIGHZ

~
IOH
(2)

UUJ11b

I\\\\\\\\~

~
DATA OUT

IAH
(0)

V~LlD

I--

1\
~

-- L
IOFP
(0.13)
MAX.

I--

I~

Vpp
(4)
Vee

1---1(:)5_
Vee -1
Vee

I~

Vee
I---lve5 ___
(2)

VIH

I

i

er
VIL

--

~
Ipw
(1.0ms)

--

_ _ IOE5~
(2)

VIH

--

topw
(3 ms)

MAX.

\~

OE
VIL

IOE

~(0.15)-

--

"

NOTES:
1.ALL TIMES SHOWN IN ( ) ARE MINIMUM AND IN I'SEC UNLESS OTHERWISE SPECIFIED.
2. THE INPUT TIMING REFERENCE LEVEL IS 0.8 V FOR A VIL AND 2 V FOR A VIH.
3.IOE AND IOFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER.
4.0.1 p.F CERAMIC CAPACITOR ON Vpp IS REQUIRED DURING PROGRAMMING ONLY, TO SUPPRESS VOLTAGE TRANSIENTS.

seeQ
MD400012/-

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

3-14

27C256
Intelligent Algorithm
AC Programming Characteristics TA= 25°± 5°C, Vcc(1 )= 6.0V±0.25V. Vpp= 12.5V
Limits
Typ.

Symbol

Parameter

tAS

Address Setup Time

2

tOES

OE Setup Time

2

p'S

tos

Data Setup Time

2

p.s

tAH

Address Hold Time

0

loiS

tOH

Data Hold Time

2

loiS

Min.

Max.

Unit
p's

tOFP

Output Enable to Output Float Delay

0

tvps

Vpp Setup Time

2

loiS

tves

Vee Setup Time

2

loiS

tpw

CE Initial Program Pulse Width

0.95

topw[2]

CE Overprogram Pulse Width

2.85

tOE

Data Valid from OE

130

1.0

ns

1.05

ms

78.75

ms

150

ns

NOTES:
1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after VPP.
2. The length of the overprogram pulse will vary from 2.85
msec to 78.75 msec as a function of the iteration counter
value X.

AC Conditions 01 Test
Input Rise and Fall Times (10% to 90%) ...... 20 ns
Input Pulse Levels ................. 0.45 V to 2.4 V
Input Timing Reference Level ....... 0.8 V and 2.0 V
Output Timing Reference Level ..... 0.8 V and 2.0 V

Ordering Information

o

Q

27C256 - 25

--L.....---l~-=_
PACKAGE
TYPE

TEMPERATURE
RANGE

PART TYPE

ACCESS TIME

D-Cerdlp

Q-0'Cto70'C
(Commercial)

32Kx8 EPROM

20-200 ns
25-250 ns

UX - Unencapsulated Ole

seeQ
MD400012/-

30-300 ns
45-450 ns

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - 6

3-15

3-16

DATA COM

(Data Communications)

seeQ

8003
EDLC® Ethernet
Data Link Controller
October 1988

Features
• Optimized for Burst Mode DMA Applications
• 100% Ethernet/IEEE 802.3 (10BASE5) and
IEEE802.3/CHEAPERNET (10BASE2)
• 10 MHz Serial/Parallel Conversion
• Preamble Generation and Removal
• Automatic 32-Blt FCS (CRC) Generation and
Checking
• ColI/slon Handling, Transmission Deferral
and Retransmission with Automatic Jam and
Backoff Functions
• Error Interrupt and Status Generation
• 40 Pin Package
• Single 5 V ±10% Power Supply
• Standard CPU and Peripheral Interlace
Control Signals
• Loopback Capability for Diagnostics
• Single Phase Clock
• Inputs and Outputs TTL Compatible

8003 interfaces directly to the 8023 Manchester Code
Converter to complete the station resident Ethernet
functions. The protocol used is Carrier Sense, Multiple
Access with Collision Detection (CSMA/CD). The
8003 EDLC chip is a single 40 pin VLSI device which
replaces approximately 60 MSI and SSI devices. It is
designed to greatly simplify the development of
Ethernet communication in computer based systems.
The 8003 provides an economic solution for the construction of an Ethernet node, providing high speed
data communication at 10 Megabits/second and sees
applications in terminals, workstations, personal
computers, small business systems, and large computer systems, in both the office and industrial
environment. The 8003 EDLC chip has a universal
system interface compatible with almost any microprocessor, microcomputer, or system bus, allowing
the system designer to make the price/performance
tradeoffs for each application. The transmit and
receive sections of the EDLC chip are independent
and can operate simultaneously to allow reception of a
transmitted frame for use in loopback diagnostics
modes.

Description
The SEEQ Ethernet Data Link Controller (EDLC) is
designed to support the Data Link Layer (layer 2) of
the Ethernet specification for Local Area Networks
(LAN). The system interface is optimized for ease of
connection to commonly available DMA Controllers
and specifically for BURST MODE OPERA TlON. The

Functional Block Diagram
TxD

A2
Al
AO

ENCODER
INTERFACE

BACKOFF
CONTROLLER
COMMAND/
STATUS
INTERFACE

INTERRUPT
AND
CONTROL

CONTROL
REGISTER
FILE
COLL

TxEN

TRANSMIT BYTE
CONTROL

C DST(O-7)

RECEIVE BIT
CONTROL
PLA

TxRDY

CSN

}

DECODER
INTERFACE

RxD
DATA
INTERFACE

RECEIVE
BYTE
CONTROL

RECEIVE
COUNTER

EDLC is a registered trademark of SEEQ Technology, Inc.

seeQ

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-----J

MD4000241A

4-1

8003
Funct~nalDescrlpUon

Frame Check Sequence: The Frame Check Sequence
(FCS) field is a 32-bit cyclic redundancy check (CRC)
value computed as a function of the Destination
Address Field, Source Address Field, Type Field, and
Data Field. The FCS is appended to each transmitted
frame, and used at reception to determine if the
received frame is valid.

Frame Formal
On an Ethernet communication network, information
is transmitted and received in packets or frames. An
Ethernet frame consists of a preamble, two address
fields, a byte-count field, a data field, and a frame
check sequence (FCS). Each field has a specific format which is described in detail below. An Ethernet
frame has a minimum length of 64 bytes and a maximum length of 1518 bytes exclusive of the preamble.
The Ethernet frame format is shown below.

I
PREAMBLE
(8)

I

SOU~CE

I1

ADDRESS
(6)

DESTINATION
ADDRESS
(6)

D~TA

(46-1500)

Transmitting
The transmit data stream consists of the Preamble,
four information fields, and the FCS which is
computed in real time by the EDLC chip and
automatically appended to the frame at the end of the
serial data. The Preamble is also generated by the
EDLC chip and transmitted immediately prior to the
Destination Address. Destination Address, Source
Address, Type Field and Data Field are prepared in the
buffer memory prior to initiating transmission. The
EDLC chip encapsulates these fields into an Ethernet
frame by inserting a preamble prior to these in;ormation
fields and appending a CRC after the information fields.

1 J
F~S
(4)

BYTE
COUNT
(2)

NOTE:
Field length in bytes in parentheses.

Preamble: The preamble is a 64-bit field conSisting of
62 alternating "1 "s and "O"s followed by a "11" End-ofPreamble indicator.
Destination Address: The Destination Address is a
6-byte field containing either a specific Station
Address, a Broadcast Address, or a Multicast Address
to which this frame is directed.

Transmission InltlatlonlDe'erral
The Ethernet node initiates a transmission by storing
the entire information content of the frame to be
transmitted in an external buffer memory, and then
transferring initial frame bytes to the EDLC Transmit
FIFO. "Transmit-buffer to FIFO" transfers are
coordinated via the TxWR and TxRDY handshake
interface, i.e., bytes are written to the FIFO via TiWff
only when TxRD Y is HIGH. Actual transmission of the
data onto the network will only occur if the network
has not been busy for the minimum defer time (9.6 j.Ls)
and any Backoff time requirements have been
satisfied. When transmission begins, the EDLC chip
activates the transmit enable (TxEN) line concurrently
with the transmission of the first bit of the Preamble
and keeps it active for the duration of the transmission.

Source Address: The Source Address is a 6-byte field
containing the specific Station Address from which
this frame originated.

Byte-Count Field: The Byte-Count Field consists of
two bytes providing the number of valid data bytes in
the Data Field, 46 to 1500. This field is uninterpreted
at the Data Link Layer, and is passed through the
EDLC chip to be handled at the Client Layer.
Data Field: The Data Field consists of 46 to 1500 bytes
of information which are fully transparent in the sense
that any arbitrary sequence of bytes may occur.

BIT
NAME

PIN
NO.

RxTxOO 6
RxTxD1
7
RxTxD2
6
RxTxD3 9
RxTxD4 10
RxTxDS 11
RxTxD6 12
iRXTXD7 13

l

FIRST BYTE
PREAMBLE

•
A71 AI

A1S1

SIXTH BYTE

••• ; . . .

I

A40

A471 SOURCE ADDRESS

'~---------------'I--------------~/
DESTINATION ADDRESS

BITS WITHIN A BYTE ARE TRANSMITTED/RECEIVED BIT NO. "0" FIRST THROUGH BIT NO. "7" LAST.

Figure 1. Bit Serlalizatlon/Oeserlalizatlon

E7~~~TKhMmg~m~~~'ed------------------------------------------------~
MD4000241A

4-2

8003

FIRST BYTE

A7

AO

A15

A8

A23

A16

A31

A24

A39

A32

A47

A40

Terminating Transmission
Transmission terminates under the following
conditions:

B7

BO ,'\

B15

B8

B23

B16

B31

B24

B39

B32

847

B40

Normal: The frame has been transmitted successfully
without contention. Loading of the last data byte into
the Transmit FIFO is signaled to the EDLC chip by
activation of the RxTxEOF signal concurrently with
the last byte of data loaded into the Transmit FIFO.
This line acts as a ninth bit in the Transmit FIFO. When
this last byte is serialized, the CRG is appended and
transmitted concluding frame transmission. The
Transmission Successful bit of the Transmit Status
Register will be set by a normal termination.
Collision: Transmission attempted by two or more
Ethernet nodes. The Jam sequence is transmitted, the
Collision status bit is set, the TxRET signal is
generated, and the Backoff interval begun.

DESTINATION
ADDRESS
(6 BYTES)

SOURCE

f- ADDRESS

T7
T15

(6 BYTES)

i/

TO }
TO

BYTE COUNT
(2 BYTES)

07

Underflow: Transmit data is not ready when needed
for transmission. Once transmission has begun, the
EDLC chip on average requires one transmit byte
every 800 ns in order to avoid Transmit FIFO
underflow (starvation). If this condition occurs, the
EDLC chip terminates the transmission, issues a
TxRET signal, and sets the Transmit-Underflow status
bit.
16 Transmission Attempts: If a ColliSion occurs for the
sixteenth consecutive time, the 16- TransmissionAttempts status bit is set, the Collision status bit is set,
the TxRET signal is generated, and the Backoff
interval begun. The counter that keeps track of the
number of collisions is modulo 16 and therefore rolls
over on the 17th collision.

OO}
r ,. -,..
DATA

~Bfl.r

BYTES)

Figure 2. Typical Frame Buffer Format
for Byte-Organized Memory

Collision
When concurrent transmissions from two or more
Ethernet nodes occur (collision), the EDLC chip halts
the transmission of the data bytes in the Transmit
FIFO and transmits a Jam pattern conSisting of
55555555 hex. At the end of the Jam transmission, the
EDLC chip issues a TxRET signal to the CPU, and
begins the Backo" wait period.

At the completion of every transmission or
retransmission, new status information is loaded into
the Transmit Status Register. Dependent upon the bits
enabled in the Transmit Command Register, an
interrupt will be generated for the just completed
transmission. In both collision and underflow the
TxRET signal is activated.

To reinitiate transmission, the initial bytes of the frame
information fields must be reloaded into the EDLC
Transmit FIFO. The TxRET is used to indicate to the
buffer manager the need for frame reinitialization. The
reloading of the Transmit FIFO may be done prior to
the Backott interval elapsing, so that no additional
delay need be incurred to retransmission.

Receiving
The EDLC chip is continuously monitoring the network. When activity is recognized via the Carrier
Sense (CSN) line going active, the EDLC chip synchronizes itself to the incoming data stream during the
Preamble, and then examines the destination address
field of the frame. Depending on the Address Match
Mode specified, the EDLC chip will either recognize
the frame as being addressed to itself in a general or
specific fashion or abort the frame reception.

Scheduling of retransmission is determined by a
controlled randomization process called Truncated Binary
Exponential Backoff. The EDLC chip waits a random
interval between 0 and 2K slot times (51.2 J.LS per slot
time) before attempting retransmission, where uK" is
the current transmission attempt number (not to
exceed 10).
When 16 consecutive attempts have been made at
transmission and all have been terminated due to
collision, the EDLC Transmit Control sets an error
status bit and issues an interrupt to the CPU if enabled.

-seeQ

Preamble Processing
The ELDC chip recognizes activity on the Ethernet via
the Carrier Sense line. The Preamble is normally 64

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - -......

MD400024/A

4-3

8003
bits (8 bytes) long. The Preamble consists of a
sequence of 62 alternating "1"s and "O"s followed by
"11", with the frame information fields immediately
following. In order for the decoder phase-lock to
occur, the EDLC chip waits 16 bit times before looking
for the "11" end of preamble indicator. If the EDLC
chip receives a "00" before receiving the "11" in the
Preamble, an error condition has occurred. The frame
is not received, and the EDLC chip begins monitoring
the network for a carrier again.

Terminating Reception
Reception is terminated when either of the following
conditions occur:
Carrier Sense Inactive: Indicates that traffic is no
longer present on the Ethernet cable.
Overflow: The host node for some reason is not able to
empty the Receive FIFO as rapidly as it is filled, and an
error occurs as frame data is lost. On average the
Receive FIFO must be serviced every 800 ns to avoid
this conditions.

Address Matching
Ethernet addresses consist of two 6-byte fields. The
first bit of the address signifies whether it is a Station
Address or a Multicast/Broadcast Address.
First Bit

0
1

Frame Reception Conditions
Upon terminating reception, the EDLC chip will
determine the status of the received frame and conditionally load it into the Receive Status Register. An
interrupt will be issued if the appropriate conditions as
specified in the Receive Command Register are present. The EDLC chip may report the fol/owing
conditions at the end of frame reception:

Address
Station Address (Ph~Jlsical)
Multicast/Broadcast Address
(logical)

Overflow: The EDLC internal Receive FIFO overflows.
Dribble Error: Carrier Sense did not go inactive on a
receive data byte boundary.

Address matching occurs as follows:

CRC Error: The 32-bit CRG transmitted with the frame
does not match that calculated upon reception.

Station Address: All destination address bytes must
match the corresponding bytes found in the Station
Address Register.

Short Frame: A frame containing less than 64 bytes of
information was received (including FGS).

Multicast Address: If the first bit of the incoming
address is a 1 and the EDLC chip is programmed to
accept Multicast Addresses, the frame is received.

Good Frame: A frame is received that does not have a
CRC error, Shortframe, or Overflow condition.

System Interface

Broadcast Address: The six incoming destination
address bytes must all be FF hex. If the EDLC chip is
programmed to accept Broadcast or Multicast
Addresses the frame will be received.
If the incoming frame is addressed to the EDLC chip
specifically (Destination Address matches the
contents of the Station Address Register), or is of
general or group interest (Broadcast or Multicast
Address), the EDLC chip will pass the frame exclusive
of Preamble and FCS to the CPU buffer and indicate
any error conditions at the end of the frame. If, however,
the address does not match, as soon as the mismatch is
recognized the EDLC chip will terminate reception and
issue an RxDG.

The EDLC chip system interface consists of two
independent busses and respective control Signals.
Data is read and written over the Receive/Transmit
Data Bus RxTxD (0-7). These transfers are controlled
by the TxRDY and TxWR signals for transmitted data,
and RxRDY and RxRD for received data. All
Commands and Station Addresses are written, and aI/
status read over a separate Command/Status Bus
CdSt (0-7). These transfers are controlled by the CS,
RD, WR, and AO-A2 Signals. The EDLC chip's
command and status registers may be accessed at any
time. However, it is recommended that writing to the
command register be done only during interframe
gaps.

The EDLC chip may be programmed via the Match
Mode bits of the Receive Command Register to ignore
all frames (Disable Receiver), accept all frames
(Promiscuous mode), accept frames with the proper
Station Address or the Broadcast Address (Station/
Broadcast), or accept all frames with the proper
Station Address, the Broadcast Address, or all
Multicast Addresses (Station/Broadcast/Multicast).

With the exception of the two Match Mode bits in the
Receive Command Register, all bits in both command
registers are interrupt enable bits. Changing the
interrupt enable bits during frame transmission does
not affect the frame integrity. Asynchronous error
events, however, e.g., overflow, underflow, etc., may
cause chip operation to vary, if their corresponding
enable bits are being altered at the same time.

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

----1

MD400024/A

4-4

8003

TRANSMIT
RECEIVE
DATA
BUFFER

DMAI
BUFFER
CONTROL

1
,t.

~

BUS
TRANSCEIVER
,t.

8003
EDLC'"

/I

J\.

"

"

8023
MANCHESTER
CODE
CONVERTER

~

t-..

v
COLLISION

7

,

SYSTEM
MEMORY

RECEIVE

TRANSMIT

I

/

TO
ETHERNET
TRANSCEIVER

CPU

Figure 3. Typical Ethernet Node Configuration

data stream, and indicating whether the address is
physical or logical. Bit 7 of station address byte 5 is
compared to the last bit of the received destination
address. The Station Address should be programmed
prior to enabling the receiver.

Reading the status registers may also occur at any
time during transmission or reception.
Internal Register Addressing
Register
Address
A2
A1
AO

0
1
2

3
4
5
6

7

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

Register Description
Read

-

Rx Status
Tx Status

Transmit Command Register
The Transmit Command Register is an interrupt mask
register, which provides for control of the conditions
allowed to generate transmit interrupts. Each of the
four least Significant bits of the register may be individually set or cleared. When set, the occurrence of the
associated condition will cause an interrupt to be generated. The four specific conditions for which interrupts
may be generated are:

Write

Station Addr 0
Station Addr 1
Station Addr 2
Station Addr 3
Station Addr 4
Station Addr 5
Rx Command
Tx Command

• Underflow
• Collision
• 16 Collisions
• Transmission Successful
The interrupt signallNT will be set when one or more
of the specified transmission termination conditions
occurs and the associated command bit has been set.
The interrupt Signal INT will be cleared when the
Transmit Status Register is read.

Status registers are read only registers. Command and
Station Address registers are write only registers.
Access to these registers is via the CPU interface:
Control signals CS, RD, WR, and the Command/Status
Data Bus CdSt (0-7).
Station Address Register
The Station Address Register is 6 bytes in length. The
contents may be written in any order, with bit "0" of
byte "0" corresponding to the first bit received in the

All bits of the Transmit Command Register are cleared
upon chip reset.

- SeeQ Technology, I n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I
MD4000241A

4-5

8003
Match Mode Definition

Transmit Command Register Format
7 6 5 4 3 2 1 0

Interrupt on Transmit Underllow
Interrupt on Transmit Collision
Interrupt on 16 Transmission
Attempts
'-----Interrupt on Transmission
Successful

Transmission Successful is set only on the successful
transmission or retransmission of a frame.
Transmit Status Register
The Transmit Status Register is loaded at the
conclusion of each frame transmission or
retransmission attempt. It provides for the reporting of
both the normal and error termination conditions of each
transmission.

3

2

1 0

' - - - - - - - - - Old/New Status

Receive Command Register
The Receive Command Register has two primary
functions, it specifies the Address Match Mode, and it
specifies Frames-of-Interest. i.e. frames whose arrival
must be communicated to the CPU via interrupts and
status register updates. Frames-of-Interest are frames
whose status must be saved for inspection, even at the
expense of losing subsequent frames.

0

Receiver Disable

Function

1

0

1

Receive All Frames

2

1

0

Receive Station or Broadcast
Frames

3

1

1

Receive Station,
Broadcast/Multicast Frames

Receive Status Register Format
7 6

5 4

3

2 1 0

Bit

Received
Error
Received
Received
' - - - - - Received
' - - - - - - Received
' - - - - - - - Received
' - - - - - - - - - - Old/New

Receive Command Register Format
4 3 2 1 0

0

Receive Status Register
The Receive Status Register is normally loaded with
the status of each received frame when the frame has
been received or frame reception has been terminated
due to an error condition. In addition, this register
contains the Old/New Status bit which is set when the
Receive Status Register is read or the chip is reset, and
cleared only when new status is loaded for a Frame-ofInterest (as defined by bits 0-5 of the Receive
Command Register). All other bits are Cleared upon
chip reset.

Bit

Transmit Underllow
Transmit Collision
16 Transmission Attempts
'-----Transmission Successful

7 6 ')

0

Interrupt Enable and Frames-of-Interest
Bits 0-5 when set specify interrupt generation on
occurrence of the corresponding frame reception
condition. They also specify the corresponding types
of frames to be Frames-of-Interest for use by the
Receive Status Register to control status loading.

Transmit Status Register Format
4

Match
Mode
0

Changing the receive Match Mode bits during frame
reception may change chip operation and give
unpredictable results.

The OLD/NEW status bit is set each time the Transmit
Status Register is read, and reset each time new status
is loaded into the Transmit Status Register. The
OLD/NEW status bit is SET, and a/l other bits
CLEARED upon chip reset.

7 6 5

Match
Mode
1

Bit

Bit

Interrupt on Overllow Error
Interrupt on CRC Error
Interrupt on Dribble Error
' - - - - - Interrupt on Short Frame
' - - - - - - Interrupt on End of Frame
L....------Interrupt on Good Frames
' - - - - - - - - Match Mode 0
' - - - - - - - - - Match Mode 1

Frame with Overflow
Frame with CRC Error
Frame with Dribble Error
Short Frame
End of Frame
Good Frame
Status

The Old/New Status bit write-protects the Receive
Status Register while it contains unread status for a
Frame-of-Interest. When this bit is zero, the register is
write-protected. The Old/New Status bit is cleared
whenever the status of a new Frame-of-Interest is
loaded into the Receive Status Register and is set atter
that status is read. When zero, it indicates "new status
for a Frame-ot-Interest".

Bits 0-5 specify Interrupt and Frame-of-Interest when
set. Bit 4, End of Frame, specifies any type of frame
except overflow.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD4000241A

4-6

8003
Thus the status of any frame received fol/owing the
reception of a Frame-of-Interest will not be loaded into
the Receive Status Register unless the previous status
has been read. If any following frame is received
before the status of the previous Frame-of-Interest has
been read, the new status will not be loaded, the
Receive Discard (RxDC) signal will be issued and the
Receive FIFO will be cleared.

from the EDLC chip to the encoder. This clock runs
continuously, and is asynchronous to RxC.
TxD Transmit Data (Output): Serial data output to the
encoder. Active HIGH.
TxEN Transmit Enable (Output): This Signal is used to
activate the encoder. It becomes active when the first
bit of the Preamble is transmitted and inactive when
the last bit of the frame is transmitted. Active HI GHand
cleared by Reset.

With this one exception caused by a write-protect
condition, the status of each frame is always loaded
into the Receive Status Register on completion of
reception.

RxC Receive Clock (Input): 10 MHz, 50% duty cycle
nominal. The receive clock is used to synchronize
incoming data to the EDLC chip from the decoder.
This clock runs continuously, and is asynchronous to
TxC.

Any frame received will cause an interrupt to be
generated if the corresponding Interrupt Enable bit is
set. This interrupt is reset upon reading the Receive
Status Register.

RxD Receive Data (Input): Serial input data to the
EDLC chip from the decoder. Active HIGH.

These conditions ensure that a maximum number of
good frames are received and retained.

CSN Carrier Sense (Input): Indicates traffic on the
coaxial cable to the EDLC chip. Becomes active with
the first bit of the Preamble received, and inactive one
bit time after the last bit of the frame is received. Active
HIGH.
COLL Collision (Input): Indicates transmission
contention on the Ethernet cable. The Collision input
is latched internally. Sampled during transmission,
Collision is set by an active high pulse on the COLL
input and automatically reset at the end of
transmission of the JAM sequence.
Data Buffer Interface
RxTxD (0-7) Receive/Transmit Data Bus (I/O): Carries
Receive/Transmit data byte from/to the EDLC chip
Receive/Transmit FIFOs.
RxTxEOF Receive/Transmit End of Frame (I/O):
Indicates last byte of data on the Receive/Transmit
Data Bus. Effectively a ninth bit in the FIFOs with
identical timing to RxTxD (0-7). Active HIGH.
RxRDY Receive Ready (Output):lndicates that at least
one byte of received data is available in the Receive
FIFO. This signal will remain active high as long as one
byte of data remains in the Receive FIFO. When this
condition no longer exists, RxRDY will.be deasserted
with respect to the leading edge of the RxRD strobe
that removes the last byte of data from the Receive
FIFO. RxRD should not be activated if RxRDY is low.
Active HIGH and cleared by Reset.

Figure 4. Pin Configuration

Pin Description
The EDLC chip has four groups of interface signals:
• Power Supply
• Encoder/Decoder

• Data Buffer
• Command/Status

Power Supply
Vee ...................................... +5V
Vss .................................. Ground

RxRD Receive Read Strobe (Input): Enables transfer
of received data from the EDLC Receive FIFO to the
RxTxD Bus. Data is valid from the EDLC Receive FIFO
at the RxTxD pins on the rising edge of this signal. This
signal should not be activated unless RxRDY is high.
Active LOW.

Encoder/Decoder Interface
TxC Transmit Clock (Input): 10 MHz, 50% duty cycle
transmit clock used to synchronize the transmit data

- - SeeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

----1

MD400024/A

4-7

8003
RxDC Recellle DIscard (Output): Asserted when one
of the following conditions occurs, and the associated
Interrupt Enable bit in the Receive Command Register
is reset. (1) Receive FIFO overflow. (2) CRC Error. (3)
Short Frame Error. (4) Receive frame address nonmatch or (5) current frame status lost because
previous status was not read. RxDC does not activate
on errors when the associated Interrupt Enable bit is
set. In this case, EOF will be generated instead when
the Receive FIFO is read out. This allows reception of
frames with errors. RxDC acts internally to clear the
Receive FIFO.
TxRDY Transmit Ready (Output): Indicates that the
Transmit FIFO has space available for at least one data
byte. This signal will remain active high as long as one
byte of space exists for transmitted data to be written
into. When this condition no longer exists, TxRD Y will
be deasserted with respect to the leading edge of the
TxWR strobe that fills the Transmit FIFO. TxRDY is
forced inactive during Reset, and when TxRET is
active. Active HIGH. Goes high after Reset.

AD-A2 Add,... (0-2) (Input): Address lines to select
the proper EDLC internal registers for reading or
writing.

CS ChIp Select (Input): Chip Select input, must be
active in conjunction with 1flj or WR to successfully
access the EDLC internal registers. Active LOW.

e

Reed (Input): Enables reading of the EDLC
internal registers in conjunction with ~. Data from
the internal registers is enabled via the falling edge of
Ff/5 and is valid on the rising edge of the Signal. Active
LOW.
WR Write (Input): Enables writing of the EDLC internal
registers in conjunction with CS. Write data on the
CdSt (0-7) data lines must be set up relative to the
rising edge of the Signal. Active LOW.
INT Infertupt (Output): Enabled as outlined above by a
variety of transmit and receive conditions. Remains
active until the status register containing the reason
for the interrupt is read. Active HIGH.

TxWR Transmit Write (Input): Synchronizes data
transfer from the RxTxD Bus to the Transmit FIFO.
Data is written to the FIFO on the rising edge of this
signal. This signal should not be active unless TxRDY
is high. Active LOW.

RESET (Input): Initializes control logic, clears
command registers, clears the Transmit Status
Register, clears bits 0-5 of the Receive Status Register,
sets the Old/New Status bit (bit 7 ofthe Receive Status
Register), asserts RxDC and TxRET and clears the
Receive and Transmit FIFOs. In addition, TxRDY is
forced low during a reset. TxRDY goes high when
~ goes high, indicating the EDLC chip is ready to
transmit. ~ is active LOW.

TxRET Transmit Retransmit (Output): Asserted whenever either transmit underflow or transmit collision
conditions occur. It is nominally 800 ns in width. Active
HIGH. Asserted by Reset.
TxRET clears the mternal Transmit FIFO.
Command/Status Interface
CdSt (D-7) CommandlStatus Data Bus (110): These
lines carry commands and status as well as station
address initialization information between the EDLC
chip and CPu. These lines are nominally high
Impedance until activated by CS and RD being
simultaneously active.

DC Characteristics TA

Absolut. "'.xlmum R.II",.
Ambient Temperature
Under Bias ........................ -10°C to +80°C
Storage Temperature ............. -65°C to +150°C
AI/Input or Output Voltages
with Respect to Ground ............. +6 V to -0.3 V
Package Maximum Power Dissipation ..... 1.5 Watts

= ooe to 70oe, Vee = 5 V± 5%
Llmlts(1)

Symbol

Paramater

liN

Input Leakage Current

10

Output Leakage Current

Min.

150

Icc

Vcc Current

VCH

Clock Input High Voltage

VCl

Clock Input Low Voltage

V'l

Input Low Voltage

V1H1

Input High Voltage

2.0

V1H2

Input High Voltage

3.0

VOL

.

VOH

Typ.

3.5

Output Low Voltage
Output High Voltage

2.4

Ma••

Units

10
10
200
6
0.8
0.8
6

pA
pA
mA

V

~~Aet rxvm and

6
0.4

V

'fiVm and AXI!iI5

V

IOl = 2.1 mA

V

IOH=-400pA

Condition
V'N = 0.45 V to 5.25 V
VOUT = 0.45 V to 5.25 V

V
V
V

NOTE:
1. Typical values are for TA = 25° C and nominal supply voltages.
Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1

SeeQ

MD400024/A

4-8

8003
Operating Conditions

AC Test Conditions

Ambient Temperature Range ....... 0° C to 70° C
Vcc Power Supply .............. 4.50 V to 5.50 V

Output Load: 1 Schottky TTL Gate + CL = 100 pF
(All pins except TxEN, TxD)
TxEN, TxD Load: 1 Schottky TTL Gate + CL = 35 pF
Input Pulse Level: 0.4 V to 2.4 V
Timing Reference Level: 1.5 V

Capacitance[6] TA = 25° C, FC = 1 MHz
Symbol

Parameter

CIN

Input Capacitance

15 pF

VIN = 0 V

CliO

I/O Capacitance

15 pF

VI/a =0 V

A.C. Characteristics TA

Maximum

Condition

= ooe to 70oe, Vee = 5 V± 5%
Limits

Symbol[5]

Parameter

Min.

Typ.

Units
Max.

(ns)

Condition

DATA AND COMMAND/STATUS INTERFACE TIMING
TDBD

RxTxlCdSt Bus Data Delay

TDBR

RxTx/CdSt Bus Release Delay

10

TDBS

RxTxlCdSt Bus Seizure Delay

10

TDRY

RxRDY/TxRDY Clear Delay

150

ns
ns

150

ns

100

ns

THAR

AO-2/CS Hold

10

ns

THDA

RxTx/CdSt Bus Hold

0

ns

THRW

RxRD/TxWR Hold

0

ns

TSAR

AO-2/CS Setup

0

ns

TSCS

CdSt Bus Setup

90

ns

TSRT

RxTx Bus Setup

90

ns

TWCH

RxRD/TxWR/RD//WR High Width

100

ns

TWCL

RxRD/TxWR/RD/WR low Width

200

10,000

ns

SERIAL TRANSMIT AND RECEIVE INTERFACE TIMING
TDDC

RxDC Set Delay

TDIC

INT Clear Delay

800

ns
150

ns

3400

ns

TDRE

TxRET Set Delay

2400

TDRI

Receive INT Delay

1000

TDTD

TxD/TxEN Delay

TDTI

Transmit INT Delay

THRD

RxD Hold

TPCK

RxC/TxC Clock Period

95

TSRD

RxD Setup

30

ns

TWDC

RxDC High Width

600

ns

TWRC

RxC High/low Width

TWRE

Note 1
Note 3

ns

Note 2

ns

CI = 35 pF

1200

ns

Note 4

20

ns

20

60

1000

ns

45

ns

TxRET High Width

600

ns

TWRS

RESET low Width

10,000

ns

TWTC

TxC High/low Width

45

ns

TWCO

COll Width

50

ns

NOTES:
1. Forframe reception with Shortframe or CRC Error. If frame reception is terminated due to Overflow, RxDC will be issued within 1.2/-1s
of Overflow. If frame reception is terminated due to non-match of address, RxDC will be issued within 2.4/-1s of the receipt of the last
address bit.
2. Normal frame reception without Overflow. If frame reception is terminated due to Overflow, INTwili be issued within 1.2/-1s of Overflow.
3. For TxRET caused by Collision or 16 ColliSion condition. If transmission is terminated due to Underflow TxRET will be issued within
1.2/-1s of the Underflow.
4. For INT caused by ColliSion or 16 Collision condition. If caused by Underflow, INT will be issued within 1.2/-1s. If caused by normal
termination, INT will be issueo within 200 ns of TxEN going lOW.
5. Italics indicate input requirement, non-italics indicate output timing.
6. Characterized. Not tested.

-seeQ Technology, Incorpotated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

---1

MD400024/A

4-9

8003
RECEIVE DATA INTERFACE TIMING
RxFIFO (BOTTOM) EMPTY

RxROY
j4----TWCt.----.j

TOBS
RxTxOO·7
RxTxEOF
NOTE 1

NOTE 1

TRANSMIT DATA INTERFACE TIMING

TxROY

RxTxOO·7
RxTxEOF

---..I
THDA

COMMAND/STATUS INTERFACE TIMING

t---~-TSA"

CclS10·7

NOTE 1: BUS IS DRIVEN AT THIS TIME. HOWEVER, NO VALID INFORMATION PRESENT.

seeQ T e c h n o l o g y , I n c o r p o f l l l e d - - - - - - - - - - - - - - - - - - - - - MD4000241A

4-10

8003
SERIAL TRANSMIT INTERFACE TIMING

SERIAL RECEIVE INTERFACE TIMING

RxC

RxD

__

CSN

COLL

RxOC

TxREY

INT

INT

Ri5

erN~1-

1--'1

f",eJ-

O,.de,.ing Info,.mation

DQ

L

PACKAGE

TYPE

D = Ceramic DIP
P = PIutk: DIP

-

8003

=L~
TEMPERATURE
RANGE

PART TYPE

Q-O"Cto+70·C

EDLC'"

SeeQ T e c h n o l o g y , / n c o t p O l 8 t e d - - - - - - - - - - - - - - - - - - - - - - - - '
MD400024/A

4-11

4-12

seeQ

8020
MCC™ Manchester
Code Converter

PREUMINARY DATA SHEET

Feetu,..

DeSCription

• CompaIIbIe""'" IEEE I02.3/Ethemet
(101JASE5), IEEEI02.3/Cheapemet (10BASE2J
and EthemeI Rete 1 SpecItIcatIona
• CompaIIbIe""'" lite 1003 EDLC, 1005
AdNnced EDLC

• "'anche.tel Data Encoding/Decoding and
•
•
•
•
•

•

October 1988

Recelvel Clock RecovelY with PIta.. Locked
Loop (PLLJ
Recelvel and ColIl./on Squelch Cllcult and
NoI.. ReJecllon Rltel
01".,.,,1181 TRANSMIT Cable Drivel
Loopback Capability fOl Diagnostics and
IlOIaflon
Fail-safe Watchdog nmel Circuit (0 Prevent
eonllnuou. 7hJnam/lSlon
20 MHz Cryafal Osclllatol
hnscelww Interface High MJItage (16 VJ

Short Cltcult ProtecfIon

• Low Powel CMOS Technology with Single
IV Supply
• 20 pin DIP a PLCC Paclcage.

The SEEQ 8020 Manchester Code Converter chip provides the Manchester data encoding and decoding
functions of the Ethernet Local Area Network physical
layer. It interfaces to the SEEQ 8003 and 8005 Controllers and any standard Ethernet transceiver as
defined by IEEE 802.3 and Ethernet Revision 1.
The SEEQ 8020 MCC" is a functionally complete
Encoder/Decoder including ECL level balanced driver
and receivers, on board oscillator, analog phase locked
loop for clock recovery and collision detection circuitry.
In addition, the 8020 includes a watchdog timer, a 4.5
microsecond window generator, flnd a loopback mode
for diagnostic operation.
Together with the 8003 or 8005 and a transceiver, the
8020 Manchester Code Converter provides a high performance minimum cost interface for any system to
Ethernet
DUAL·IN LINE
TOP VIEW

Pin Configuration
MODEl

Vee

GND

"Tx+

LPBKlWDTD

Tx-

Functional Block Diagram
TaEN

TxD

---..,....----y--;:========:rl-----..,

TiC

RxCaN

TxEN

COLL

Xl

RxC

X2

COLL+

fie

-+----..-...

TaD

4----+-;.__...

........... -~TJt+
ENCODER ~--I------...----t
Tx-

v••

~

_ _ _. .r

COLL-

TRANSMIT

U.~"~--------4------------+-----1

PLASTIC LEADED CHIP CARRIER
TOP VIEW

WDTD

------vee
------Vss
X1

_ - - - - - MODEl

X2
Rae

------+--f

RaD

- - - - - - L__....J

DECODER 1.-+-~--4
RJt+

Tx-

RxTxD

eOLL---------fD~~~~RI.-4----------------~

COLL+

COLL-

TxEN

COLLISION

'Igure 1. 8020 .CC •••nchHter Code Converter Block Diagram.

EDLC Is a teglsteted trademark of SEEQ Technology, Inc.
MCC Is a trademark of SEEQ 7iK:hnology, Inc.

- SeeQ
AfD4000231A

~

~

"

.!.

8

~
o
u

...

~

Technology,lncorpof8ted - - - - - - - - - - - - - - - - - - - - - '

4-13

8020
Functional Description
The 8020 Manchester Code Con verter chip has two portions, transmitter and receiver. The transmitter uses
Manchester encoding to combine the clock and data
into a serial stream. It also differentially drives up to 50
meters of twisted pair transmission line. The receiver
detects the presence of data and collisions. The 8020
MCC'" recovers the Manchester encoded data stream
and decodes it into clock and data outputs. Manchester
Encoding is the process of combining the clock and
data stream so that they may be transmitted on a single
twisted pair of wires, and the clock and data may be
recovered accurately upon reception. Manchester
encoding has the unique property of a transition at the
center of each bit cell, a positive going transition for a
"1," and a negative going transition for a "0" (See Figure
2). The encoding is accomplished by exlusive-ORing
the clock and data prior to transmission, and the decoding by deriving the clock from the data with a phase locked loop.

Clock Generator
The internal oscillator is controlled by a 20 MHz
parallel resonant crystal or by an external clock on
X1. The 20 MHz clock is then divided by 2 to generate a 10 MHz ±0.01% transmitter clock. Both 10 MHz
and 20 MHz clocks are used in Manchester data
encoding.
Manchester Encoder and Differential Output Driver
The encoder combines clock and data informatjon for
the transceiver. In Manchester encoding, the first halfof
the bit cell contains the complement of the data and the
second half contains the true data Thus, a transition is
always guaranteed in the middle of a bit cell.

Data encoding and transmission begin with TxEN going
active; the first transition is always positive for Tx(-) and
negative for Tx(+). In IEEE mode, at the termination of a
transmission, TxEN goes inactive and transmit pair
approach to zero differential. In Ethernet mode, at the
end of the transmission, TxE N goes inactive and the
transmit pair stay differentially high. The transmit termination can occur at bit cell center if the last bit is a one
or at a bit boundary if the last bit is a zero. To eliminate
DC current in the transformer during idle, Tx ± is brought
to 100 m V differential in 600 ns after the last transition
(IEEE mode). The back swing voltage is guaranteed to
be less than. 1 V.

Watchdog Timer
A watchdog timer is built on Chip. It can be enabled or
disabled by the LPBK/WDTD signal. The timer starts
counting at the beginning of the transmission. If TxEN
goes inactive before the timer expires, the timer is reset
and ready for the next transmission. If the timer expires
before the transmission ends, transmission is aborted
by disabling the differential transmitter. This is done by
idling the differential output drivers (differential output
voltage becomes zero) and deasserting CSN.

Differential Input Circuit (Rx+ and Rx-, COLL + and
COLL-J.
As shown in Figure 3, the differential input for Rx+
and Rx- and COLL + and COLL- are externally terminated by a pair of 39.2 0 ± 1% resistors in series
for proper impedance matching.
The center tap has a 0.01 I1F capacitor, tied to
ground, to provide the AC common mode impedance
termination for the transceiver cable.

--------------------~--+

SERIAL
DATA

39.2± 1%

COLLISION OR
RECEIVE
INPUT

TRANSMITTED
DATA
(MANCHESTER
ENCODED)

I

Figure 2. Manchester Coding

i.....--

SeeQ
MD4000231A

TRANSCEIVER
CABLE

0.01 pF
39.2

n

I

1%

Figure 3. Differential Input Terminator'

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4-14

8020
Both collision and receiver input circuits provide a static
noise margin of -140 m V to -300 m V (peak value). Noise
rejection filters are provided at both input pairs to prevent spurious signals. For the receiver pair, the range is
15 ns to 30 ns. For the collision pair, the range is 10 ns to
18 ns. The D. C. threshold and noise rejection filter
assure that differential receiver data signals less than
-140 mV in amplitude or narrower than 15 ns (10 ns for
collision pair) are always rejected, signals greater than
-300 mV and wider than 30 ns (18 ns for collision Dair) are
always accep1ed.
Manchester Decoder and Clock Recovery Circuit
The filtered data is processed by the dara and clock
recovery circuit using a phase-locked loop technique.
The PLL is designed to lock onto the preamble of the
incoming signal with a transition width asymmetry not
greater than +8.25 ns to-8.25 ns within 12 bit cell times
worst case and can sample the incoming data with a
transition width asymmetry of up to +8.25 ns to -8.25 ns.
The RxC high or low time will always be greater than
40 ns. RxC follows TxC for the first 1.2p,s and then
switches to the recovered clock. In addition, the
Encoder/Decoder asserts the CSN signal while it is
receiving data from the cable to indicate rne receiver
data and clock are valid and available. At the end of
frame, after the node has finished transmitting, CSN is
deasserted and will not be asserted again for a period
of 4.5p,s regardless of the state of the state of the
receiver pair or collision pair. This is called the inhibit
period. There is no inhibit period after packet reception. During clock switching, RxC may stay high for
200ns maximum.
Collision Circuit
A collision on the Ethernet cable is sensed by the

transceiver. It generates a 10M Hz ±15% differential
square wave to indicate the presence of the collision.
During the collision period, CSN is asserted
asynchronously with RxC. However, if a collision arrives
during inhibit period 4.5 J.LS from the time CSN was
deasserted, CSN will not be reasserted.
Loopback
In loopback mode, encoded data is switched to the PLL
instead of Tx+ITx- signals. The recovered data and
clock are returned to the Ethernet Controller. All the
transmit and receive circuits, including noise rejection
filter, are tested except the differential output driver and
the differential input receiver circuits which are disabled during loopback At the end of frame transmission,
the 8020 also generates a 650 ns long COLL sianal

-- SeeQ
MD4000231A

550 ns after CSN was deasserted to simulate the IEEE
802.3 SQE test. The watchdog timer remains enabled in
this mode.

Pin Description
The MCCTM chip signals are grouped into four
categories:
•
•
•
•

Power Supply and Clock
Controller Interface
Transceiver Interface
Miscellaneous

Power Supply
Vee ...................................... +5V
Vss .................................. Ground

X1 and X2 Clock (Inputs): Clock Crystal: 20 MHz
crystal oscillator input. Alternately, pin X1 may be
used as a TTL level input for external timing by floating pin X2.
Controller Interface
RxC Receive Clock (Output): This signal is the
recovered clock from the phase decoder circuit. It is
switched to TxC when no incoming data is present from
which a true receive clock is derived. 10M Hz nominal
and TTL compatible.
RxD Receive Data (Output): The RxD signal is the
recovered data from the phase decoder. During idle
periods, the RxD pin is LOW under normal conditions.
TTL and MOS level compatible. Active HIGH.
CSN CarrierSense(Output): The Carrier Sense Signal
indicates to the controller that there is activity on the
coaxial cable. It is asserted when receive data is present
or when a collision signal is present. It is deasserted at
the end of frame or at the end of collision, whichever
.occurs later. It is asserted or de asserted synchronously
with RxC. TTL compatible.
TxC Transmit Clock (Output): A 10M Hz Signal
derived from the internal oscillator. This clock is always
active. TTL and MOS level compatible.
TxD Transmit Data (Input): TxD is the N RZ serial input
data to be transmitted. The data is clocked into the MCC
by TxC. Active HIGH, TTL compatible.
TxENTransmitEnable(lnput): Transmit Enable, when
asserted, enables data to be sent to the cable. It is asserted synchronously with TxC. TxEN goes active with the
first bit of transmission. TTL compatible.

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4-15

8020
COLL Collision (Output): When asserted, indicates to
the controller the simultaneous transmission of two or
more stations on network cable. TTL Compatible.

I,

Transceiver Interlace
Rx+ and Rx- Differential Receiver Input Pair (Input):
Differential receiver input pair which brings the
encoded receive data to the 8020. The last transition is always positive-going to indicate the end of
the frame.

0.01pF ~

5

Rx+ 4
X2

Ol-A

39.20

±1%
12 Ol-B

Rx-

COLL + and COLL - Differential Collision Input Pair
(Input): This is a 10 MHz±15% differential signal from
the transceiver indicating collision. The duty cycle
should not be worse than 60%/40% - 40%/60%. The
last transition is positive-going. This signal will respond
to signals in the range of 5 MHz to 11.5 MHz. Collision
signal may be asserted if 'MAU not available' signal
is present.

RxC
RxO

Tx+ 19

OO-A

18

1OOO_B

CSN
COLL

Tx-

AUI
CABLE

8003

OR

SEEQ
8020

8005

16

17
15

Tx+ and Tx- Differential Transmit Output Pair (Output): Differential transmit pair which sends the
encoded data to the transceiver. The cable driver buffers are source follower and require external 243 n
resistors to ground as loading. These resistors must be
rated at 1 watt to withstand the fault conditions
specified by IEEE 802.3. If MODE1 = 1, after 200 ns
following the last transition, the differential voltage is
slowly reduced to zero volts in 8 J.1,S to limit the back
swing of the coupling transformer to less than 0.1 V.

TxC

COLL+ 12

TxEN

2 CI-A
39.211

TxO

±1%
COLL-

11

9

CI-B

39.211

±1%

1°.D1!'F
~5

Figure 4.8020 Interface

Miscellaneous
MODE1 (Input): This pin is used to select between
AC or DC coupling. When it is tied high or left
floating, the output drivers provide differential zero
Signal during idle (IEEE 802.3 specification). When
pin 1 is tied low, then the output is differentially high
when idle (Ethernet Rev. 1 specification).
LPBKIWDTD LoopbacklWatchdog Timer Disable
(Input):
Normal Operation: For normal operation this pin
should be HIGH or tied to Vee. In normal operation
the watchdog timer is enabled.

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MD400023/A

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-----------------------------~
4-16

8020
D.C. and A.C. Characteristics and Timing

Loopback: When this pin is brought low, the Manchester encoded transmit data from TxD and TxC is
routed through the receiver circuit and sent back
onto the RxD and RxC Pins. During loopback, Collision and Receive data inputs are ignored. The transmit pair is idled. At the end of transmission, the signal
quality error test (SOET) will be simulated by asserting
collision during the inhibit window. During loopback,
the watchdog timer is enabled.

Crystal Specification
Resonant Frequency (C L = 20 pF) ......... 20 MHz
± 0.005% 0-70 0 C
and ± 0.003% at 250 C
.......................

Fundamental Mode

Circuit ......................

Type

Parallel Resonance

Load Capacitance (Cd

.................... 20 pF

Watchdog Timer Disable: When this pin is between 10
V (Min.) and 16 V (Max.), the on chip 25 ms Watchdog

Shunt Capacitance (Co)

............... 7 pF Max.

Timer will be disabled. The watchdog timer is used to
monitor the transmit enable pin. If TxE N is asserted for
too long, then the watchdog timer (if enabled) will
automatically deassert CSN and inhibit any further
transmissions on the Tx+ and Tx-lines. The watchdog
timer is automatically reset each time TxEN is
deasserted.

Motional Capacitance (C1) ..........

Equivalent Series Resistance (R1) ....... 25

n Max.

0.02 pF Max.

Drive Level ..............................

2 mW

-==1

Interconnection to a Data Link Controller

Co

Figure 5 shows the interconnections between the 802"0
MCC" and SEEQ's 8003 or 8005. There are three connections for each of the two transmission channels,
transmit and receive, plus the Collision Signal line
(COLL).

EQUIVALENT CIRCUIT OF CRYSTAL

Figure 6.

Transmitter connections are:
Transmit Data, TxD
Transmit Clock, TxC
Transmit Enable, TxEN
Collision, COLL
Receiver connections are:
Receive Data, RxD
Receive Clock, RxC
Carrier Sense, CSN

TxD

TxD

TxC

TiC

TxEN

TxEN

LOOPBACK [1]

LOOPBACK

8020

8003
OR
8005

MCC·
COLL

COLL

RxD

RxD

RxC

RxC

CSN

CSN

Figure 5. Interconnection of 8020 and 8003/8005
NOTE
1. Loopback output on 8005 only.

- SeeQ
MD400023/A

Technology, Incorporated

----------------------------~
4-17

8020
Absolute Maximum Ratings'"

*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Storage Temperature ............ -65° C to 150° C
AI/Input and Output Voltage ..... -0.3 to Vee +0.3
Vee ................................. -0.3 to 7V
(RX±, TX±, COLL±) High Voltage
Short Circuit Immunity .............. -0.3 to 16V

DC Characteristics TA = O°C to 70°C; Vee = 5 V ±
Symbol

Parameter

ilL

Input Leakage Current (except MODE1,
Receive and Collision Pairs)

5%

Min.

MODE1 Input Leakage Current
Receive and Collision Pairs (Rx±,
COLL±) I nput Leakage Current

Max.

Unit

Conditions

10

pA

O~VIN~VCC

200

pA

O~VIN~VCC

VIN=O

2

mA

75

mA

-0.3

0.8

V

TTL Input High Voltage (except X1)

2.0

Vcc+0.3

V

X1 Input High Voltage

3.5

Vcc+0.3

V
V
V

IOL=2.1 mA
IOL=4.2 mA

V
V

tOH=-400pA
tOH=-400pA

Icc

Vcc Current

VIL

TTL Input Low Voltage

VIH
VOL

TTL Output Low Voltage except TxC
TxC Output Low Voltage

VOH

TTL Output High Voltage (except
RxC, TxC, RxD)
RxC, TxC, RxD Output High Voltage

VODF

Differential Output Swing

VOCM

Common Mode Output Voltage

VBKSV

TX±Backswing Voltage During Idle

VIDF

Input Differential Voltage
(measured differentially)

VICM
CIN[l)

Input Commnon Mode Voltage
Input Capacitance

COUT[l)

Output Capacitance

0.4
0.4
2.4
3.9

All Inputs, Outputs Open

±0.55

±1.2

V

7Sn Termination Resistor and
243n Load Resistors

Vcc-2.5

Vcc-1

V

7Sn Termination Resistor and
243n Load Resistors

0.1

V

Shunt inductive

±0.3

±1.2

V

0

Vcc

V

15

pF

15

pF

I

NOTE:
1. Characterized Not tested.

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MD4000231A

Technology, Incorporated

4-18

loa~27

I'H

8020
A.C. Test Conditions
Output Loading TTL Output:

1 TTL gate and 20 pF capaCitor

Differential Output:

243n resistor and 10 pF capacitor from each pin to Vss and

a termination TBB resistor load resistor in parallel with a
27 p.H inductor between the two differential output pins
Differential Signal Delay Time Reference Level:

SO% point of swing

Differential Output Rise and Fall Time:

20% to BO% paints

RxC, TxC, X1 High and Low Time:

High time measured at 3.0V
Low time measured at 0.6V

RxD, RxC, TxC, X1 Rise and Fall Time:

Measured between 0.6V and 3.0V points

TTL Input Voltage (except X1 ):

O.BV to 2.0V with 10 ns rise and fall time

X1 Input Voltage:

O.BV to 3.SV with 5 ns rise and fall time

Differential Input Voltage:

At least± 300 m V with rise and fall time of 10 ns measured
between -0.2V and +0.2V

20 MHz TTL Clock Input TimingTA =0°Cto70°C;Vcc =5V±50f0
Symbol

Parameter

Min.

Max.

Units

h

X1 Cycle Time

49.995

50.005

ns

t2

X1 High Time

15

ns

t3

X1 Low Time

15

ns

t4

X1 Rise Time

5

ns

is

X1 Fall Time

5

ns

tSA

X1 to TxC Delay Time

45

ns

10

15

Xl

TxC --------------~r

Figure 12. 20 MHz TTL Clock Timing

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MD400023/A

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4-19

8020
Transmit Timing TA =O°C to 70°C; Vee = 5 V ± 5%
Symbol
ta[l)

Min.

Max.

Units

TxC Cycle Time

99.99

100.01

ns

h

TxC High Time

40

ta

TxC Low Time

40

t9[1)

TxC Rise Time

5

t10[1)

TxC Fa[[Time

5

t11

TxEN Setup Time

40

ns

t12

TxD Setup Time

40

ns

Parameter

ns
ns
ns
ns

t13[1)

Bit Center to Bit Center Time

99.5

100.5

t 14[1)

Bit Center to Bit Boundary Time

49.5

50.5

ns

t15[1)

Tx+ and Tx- Rise Time

5

lis

t18[1)

Tx+ and Tx- Fa[[ Time

5

ns

t17

Transmit Active Time From The Last
Positive Transition

200

t17A[l)

From Last Positive Transition of the
Transmit Pair to Differentia[ Output
Approaches within 100 mV of 0 V

400

t 17 8[1)

From Last Positive Transition of the
Transmit Pair to Differential Output
Approaches within 40 mV of 0 V

ns

ns

600

ns

7000

ns

70

ns

t 18

Tx+ and Tx- Output Delay Time

t19

TxD Hold Time

15

ns

t20

TxEN Hold Time

15

ns

NOTE:
1. Characterized. Not tested.

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MD400023/A

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4-20

8020
MODE1 = 1

TxEN

11
19

112

TxO

"1"

LAST BIT /

"0"

"1"

"'"

\

.

"Oil"

_

118_

LAST BIT

0

Tx±--------4

L_A_ST_B_IT_l_LJ~

TX± _ _

_ _ _ _' [ : ,

1
I
Figure 7. Transmit Timing

(-)

MODE1 =0

TxEN

"1"

Tx (+)

LAST BIT

0

0

Tx(-)-----.1

Tx

(+)------y:;J

LAST BIT 1
Tx(-)------·

:::

C :x3Eco~

1 '-----0
-

1

I

Figure 8. Transmit Timing

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MD400023/A

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1

I

1

(-)

8020

Receive Timing TA = O°C to 70°C; Vee = 5 V ± 5%
Symbol

Parameter

Max.

Units

tZ1

CSN Assert Delay Time

240

ns

tzz

CSN Deasserts Delay Time (measured
from Last Bit Boundary)

240

ns

Min.

tZ3A

CSN Hold Time

30

ns

tZ3B

CSN Set up Time

30

ns

tZ4

RxD Hold Time

30

ns

tzs
t zo (1 )

RxD Set up Time

30

tn

RxC Rise and Fall Time

(1 )

ns

5

ns

200

ns

During Clock Switch RxC Keeps High Time

40

RxC High and Low Time

40

RxC Clock Cycle Time (during)
data period)

95

105

ns

l,o

CSN Inhibit Time (on Transmission
Node only)

4.3

4.6

P.s

t31
t 32!1]

Rx+/Rx- Rise and Fall Time

10

ns

tZB
t z1I (1 )

Rx+/Rx- Begin Return to Zero from Last
Positive-Going Transition

ns

ns

160

!,3(1)

RxD Rise Time

10

ns

t 3• (1 )

RxD Fall Time

10

ns

Rx(+)
Rx(-)

CSN

RxC

RxD

Figure 9. Receive Timing- Start of Packet
NOTE:
1. Characterized. Not tested.

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MD4000231A

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4-22

8020

RxC

Rx(+)
Rx(-)

(LAST BIT=O)

r--

~-----I~

CSN

--~~--------------~o-------~I
RxD

_ ________

~~~_"O_

.. ____________________________

.

-

i',

Figure 10. Receive Timing - End of Packet

LseeQ
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~~---------

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4-23

8020
Collision Timing TA = O°C to 70°C; Vee = 5 V ±

5%

Min.

Max.

Units

86

118
10

ns

COll+/COll- High and low Time

35

70

ns

COll+/COll- Width (measured at -0.3V)

26

Symbol

Parameter

ts1
ts2
ts3
ts4
tss
ts6
ts?
tsa

COll+/COll- Cycle Time
COll+/COll- Rise and Fall Time

ns
ns

COll Asserts Delay Time

300

ns

COll Deasserts Delay Time

500

ns

CSN Asserts Delay Time

400

ns

CSN Deasserts Delay Time

600

ns

Notes:

1.
2.
3,
4,

COLL + and COll- asserts and deasserts COLL, asynchronously, and asserts and deasserts CSN synchronously with RxC,
If COLl + and COLL- arrives within 4,5jis from the time CSN was deasserted; CSN will not be reasserted (on transmission node only),
When COLl + and COLL- terminates, CSN will not be deasserted if Rx+ and Rx- are still active,
When the node finishes transmitting and CSN is deasserted, it cannot be asserted again for 4,5 jis,

COll(+)
COll(-)

COll

CSN

Figure 11. Collision Timing

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MD4000231A

Technology, Incorporated

4-24

8020
Loopback Timing TA = O°C to 70°C; Vee = 5 V ± 5%
Symbol

Parameter

Min.

ts1

lPBK Setup Time

500

Max.

ns

ts2

lPBK Hold Time

5

IJ.S

ts3

In Collision Simulation, COll Signal
Delay Time

475

625

ns

ts4

COll Duration Time

600

750

ns

Units

Note:

1. PLL needs 12-bit cell times to acquire lock, RxD is Invalid during this period.

LPBK/WOTO

TxEN

TxO

COll

RxC

CSN ________________________

-J~I
"1"

RxO

"0"

r----\

--~Ir,-.l

''1''

"1"

r----\

L-J

I

1\

~~

L..

Figure 13. Loopback Timing

- SeeQ
MD400023/A

Technology, Incorporated

------------------------~
4-25

8020
Ordering Information

D

Q

8020

:l~

PACKAGE
TYPE

TEMPERATURE
RANGE

O·C TO 70·C
P = PLASTIC DIP
N PLASTIC LEADED
CHIP CARRIER

=

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MD4000231A

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4-26

PRODUCT

MCC· MANCHESTER
CODE CONVERTER

seeQ

B023A
MCCTM Manchester
Code Converter
October 1988

Features

Description

• Compatible with IEEE 802.3lEthernet
(10BASE5), IEEE802.3ICHEAPERNET
(10BASE2) and Ethernet Rev. 1 Specifications
• Compatible with the 8003 EDLCfJ 8005
Advanced EDLC and Intel 82586 LAN
Controller
• Manchester Data Encoding/Decoding and
Receiver Clock Recovery with Phase Locked
Loop (PLL)
• Receiver and Collision Squelch Circuit and
Noise Rejection Filter
• Differential TRANSMIT Cable Driver
• Loopback Capability for Diagnostics and
Isolation
• Fal/-Safe Watchdog Timer Circuit to Prevent
Continuous Transmission
• 20 MHz Crystal Oscillator
• Transceiver Interface High Voltage (16 V)
Short Circuit Protection
• Low Power CMOS Technology with Single
5V Supply
• 20 pin DIP & PLCC Packages

The SEEQ 8023A Manchester Code Converter chip
provides the Manchester data encoding and decoding functions of the Ethernet Local Area Network
physical layer. It interfaces to the SEEQ 8003 and 8005
Ethernet Data Link Controllers orto the Intel82586 LAN
Controller and any standard Ethernet transceiver as
defined by IEEE 802.3 and Ethernet Revision 1.
The SEEQ 8023A MCC is a functionally complete
Encoder/Decoder including ECL level balanced driver
and receivers, on board oscillator, analog phase
locked loop for clock recovery and collision detection
circuitry. In addition, the 8023A includes a 25 millisecond watchdog timer, a 4.5 microsecond window
generator, and a loopback mode for diagnostic operation.
Together with the 8003 or 8005 and a transceiver, the
8023A Manchester Code Converter provides a high performance minimum cost interface for any system to
Ethernet.

Pin Configuration

DUAL-IN-LINE
TOP VIEW
vee

Functional Block Diagram

Tx+
Tx-

TxEN ---l----,---;::::::====::::Il~---__.,

TxD
TxC
TxEN (TxEN)
X1

~-+--------I
ENCODER ~--+--------....--~
TxD

~B~

-+-----+-__I

X2

Tx+

.__~ Tx-

COlL+
COll-

TRANSMIT

~--~

WDTD

----vee
----vss
X1

_---MODE1

X2

----MODE2

RxC

_-----1---1
DECODER

1.-+-----1
Rx+

RxD __- - - - - - - 1

Rx-

.......----.....1

COll

PLASTIC LEADED CHIP CARRIER
TOP VIEW

- - - ' - - - - - - - 1 DE~E~~~R

t-........- - - - - - - - - <

COlL+
COll-

COLLISION

Figure 1. 8023A MCC Manchester Code Converter Block Diagram.
EDLC is a registered trademark of SEEO Technology, Inc.
MCC is a trademark of SEEO Technology, Inc.

- SeeQ
MD400022/ A

Q

Q

a:

~

8

Techno~y, Incorpof8ted -----------------------~
4-27

B023A
Functional Description
Data encoding and transmission begin with TxEN going
active; the first transition is always positive for Tx(-) and
negative for Tx(+). In IEEE mode, at the termination ofa
transmission, TxEN goes inactive and the transmit pair
approach to zero differential. In Ethernet mode, at the
end of the transmission, TxEN goes inactive and the
transmit pair stay differentially high. The transmit termination can occur at bit cell center if the last bit is a one
or at a bit boundary if the last bit is a zero. To eliminate
DC current in the transformer during idle, Tx ± is brought
to 100 m V differential in 600 ns after the last transition
(IEEE mode). The back swing voltage is guaranteed to
be less than. 1 V.

The B023A Manchester Code Converter chip has two
portions, transmitter and receiver. The transmitter
uses Manchester encoding to combine the clock and
data into a serial stream. It also differentially drives
up to 50 meters of twisted pair transmission line. The
receiver detects the presence of data and collisions.
The B023A MCC recovers the Manchester encoded
data stream and decodes it into clock and data
outputs. Manchester Encoding is the process of
combining the clock and data stream so that they
may be transmitted on a single twisted pair of wires,
and the clock and data may be recovered accurately
upon reception. Manchester encoding has the unique
property of a transition at the center of each bit cell, a
positive going transition for a "1'; and a negative
going transition for a "0" (See Figure 2). The encoding is accomplished by exlusive-ORing the clock
and data prior to transmission, and the decoding by
deriving the clock from the data with a phase locked
loop.

Watchdog Timer
A 25 ms watchdog timer is built on chip. It can be
enabled or disabled by the LPBK/WDTD signal. The
timer starts counting at the beginning of the transmission. If TxEN goes inactive before the timer
expires, the timer is reset and ready for the next
transmission. If the timer expires before the transmission ends, transmission is aborted by disabling
the differential transmitter. This is done by idling the
differential output drivers (differential output voltage
becomes zero) and deasserting CSN.

Clock Generator
The internal oscillator is controlled by a 20 MHz
parallel resonant crystal or by an external clock on
X1. The 20 MHz clock is then divided by 2 to generate a 10 MHz ±0.01% transmitter clock. Both 10 MHz
and 20 MHz clocks are used in Manchester data
encoding.

Differential Input Circuit (Rx+ and Rx-, COLL+ and
COLL-)
As shown in Figure 3, the differential input ;or Rx+
and Rx- and CaLL + and CaLL-are externally terminated by a pair of 39.2 0 ± 1% resistors in series
for proper impedance matching.
The center tap has a 0.01 /IF capacitor, tied to
ground, to provide the AC common mode impedance
termination for the transceiver cable.

Manchester Encoder and Differential Output Driver
The encoder combines clock and data information for
the transceiver. In Manchester encoding, the first halfof
the bit cell contains the complement of the data and the
second half contains the true data Thus, a transition is
always guaranteed in the middle of a bit cell.

--------------------~--+
SERIAL
DATA

39.2± 1%

COLLISION OR
RECEIVE
INPUT

TRANSMITTED
DATA
(MANCHESTER
ENCODED)

0.01

~F

TRANSCEIVER
CABLE

39.211 ± 1%

Figure 2. Manchester Coding

seeQ
MD400022/A

Figure 3. Differential Input Terminator

Technology, Incorporated

4-28

B023A
the 8023A also generates a 650 ns long COLL signal
550 ns after CSN was deasserted to simulate the IEEE
802.3 SQE test. The watchdog timer remains enabled in
this mode.

Both collision and receiver input circuits provide a static
noise margin of -140 m V to -300 m V (peak value). Noise
rejection filters are provided at both input pairs to prevent spurious signals. For the receiver pair, the range is
15 ns to 30 ns. For the collision pair, the range is 10 ns to
18 ns. The D. C. threshold and noise rejection filter
assure that differential receiver data signals less than
-140 mV in amplitude or narrower than 15 ns (10 ns for
collision pair) are always rejected, signals greater than
-300 mVand wider than 30 ns(18 ns for collision pair) are
always accepted.

Pin Description
The MCC chip signals are grouped into four categories:
• Power Supply and Clock
• Controller Interface
• Transceiver Interface
• Miscellaneous

Manchester Decoder and Clock Recovery Circuit

Power Supply

The filtered data is processed by the data and clock
recovery circuit using a phase-locked loop technique.
The PLL is designed to lock onto the preamble of the
incoming signal with a transition width asymmetry not
greater than +8.25 ns to -8.25 ns within 12 bit cell times
worst case and can sample the incoming data with a
transition width asymmetry of up to +8.25 ns to -8.25 ns.
The RxC high or low time will always be greater than 40
ns. If MODE 2 is high or floating, RxC will be held low for
1.2 us maximum while the JJ::.L is acquiring lock. If
MODE2 is low, RxC follows TxC for the first 1.2 pS and
then switches to the recovered clock. In addition, the
Encoder/Decoder asserts the CSN signal while it is
receiving data from the cable to indicate the receiver
data and clock are valid and available. At the end of
frame, after the node has finished transmitting, CSN is
deasserted and will not be asserted again for a period of
4.5 j.tS regardless of the state of the state of the receiver
pair or collision pair. This is called the inhibit period.
There is no inhibit period after packet reception. During
clock switching, RxC may stay high for 200ns maximum.

Vee
Vss

X1 and X2 Clock (Inputs): Clock Crystal: 20 MHz
crystal oscillator input. Alternately, pin X1 may be
used as a TTL level input for external timing by floating pin X2.

Controller Interlace
RxC (RxC) Receive Clock (Output): This signal is
the recovered clock from the phase decoder circuit.

It is switched to TxC when no incoming data is
present from which a true receive clock is derived.
10 MHz nominal and TTL compatible. If the MODE2
signal is high, RxC is inverted (RxC) and there is a
1.25 J.Lsec discontinuity at the beginning of frame
reception.

RxD Receive Data (Output): The RxD signal is the
recovered data from the phase decoder. During idle
periods, the RxD pin is LOW under normal conditions.
However, if the MODE2 signal is HIGH, the RxD output
will be HIGH during idle. TTL and MOS level compatible.
Active HIGH.

Collision Circuit

CSN (CSN) Carrier Sense (Output): The Carrier

A collision on the Ethernet cable is sensed by the
transceiver. It generates a 10M Hz ± 15% differential
square wave to indicate the presence of the collision.
During the collision period, CSN is asserted
asynchronously with RxC. However, if a collision arrives
during inhibit period 4.5 j.tS from the time CSN was
deasserted, CSN will not be reasserted.

Sense Signal indicates to the controller that there is
activity on the coaxial cable. It is asserted when
receive data is present or when a collision signal is
present. It is deasserted at the end of frame or at the
end of collision, whichever occurs later. It is asserted
or deasserted synchronously with RxC. TTL compatible. Normally active HIGH, unless MODE2 is HIGH,
in which case CSN is active LOW.

Loopback
In loopback mode, encoded data is switched to the PLL
instead of Tx+/Tx- signals. The recovered data and
clock are returned to the Ethernet Controller. All the
transmit and receive circuits, including noise rejection
filter, are tested except the differential output driver and
the differential input receiver circuits which are disabled during loopback. At the end offrame transmission,

-seeQ
MD4000221A

...................................... +5V
.................................. Ground

TxC Transmit Clock (Output): A 10 MHz signal
derived from the internal oscillator. This clock is always
active. TTL and MOS level compatible.
TxD Transmit Data (Input): TxD is the N R Z serial input
data to be transmitted. The data is clocked into the MCC
by TxC. Active HIGH, TTL compatible.

Technology, Incorporated

4-29

B023A
TxEN (TxEN) Transmit Enable (Input): Transmit
Enable, when asserted, enables data to be sent to
the cable. It is asserted synchronously with TxC.
TxEN goes active with the first bit of transmission.
TTL compatible. If MODE2 is HIGH, TxEN is
inverted.
COLL (COLL) Collision (Output): When asserted,
indicates to the controller the simultaneous transmission of two or more stations on network cable.
TTL compatible. If MODE2 is HIGH, COLL is inverted.
Transceiver Interface
Rx+ and Rx- Differential Receiver Input Pair (Input):
Differential receiver input pair which brings the
encoded receive data to the 8023A. The last transition is always positive-going to indicate the end of
the frame.

Miscellaneous
MODE1 (Input): This pin is used to select between
AC or DC coupling. When it is tied high or left
floating, the output drivers provide differential zero
signal during idle (IEEE 802.3 specification). When
pin 1 is tied low, the output is differentially high when
idle (Ethernet Rev. 1 specification).
MODE2 (Input): The MODE2 Input signal is normally
active LOW. In this configuration, the 8023A operates
in a mode compatible with the SEEQ 8003. An alternate mode of operation may be achieved by configuring the MODE Signal active HIGH, or by allowing
it to float HIGH with its internal pullup. In this configuration, RxC, TxEN, CSN and COLL become active
LOW. In addition, RxD is HIGH during idle, and RxC
has a 1.2 fls discontinuity during signal acquisition.

COLL+ and COLL- Differential Collision Input Pair
(Input): This is a 10M Hz ± 15% differential signal from
the transceiver indicating collision. The duty cycle
should not be worse than 60%140% - 40%160%. The
last transition is positive-going. This signal will respond
to signals in the range of 5 M Hz to 11.5 MHz. Collision
signal may be asserted if 'MAU not available' signal
is present.

LPBK/WDTD Loopback/Watchdog Timer Disable
(Input):
Normal Operation: For normal operation this pin
should be HIGH or tied to Vee. In normal operation
the watchdog timer is enabled.

j,

Tx+ and Tx- Differential Transmit Output Pair (Output): Differential transmit pair which sends the
encoded data to the transceiver. The cable driver buffers are source follower and require external 243 n
resistors to ground as loading. These resistors must be
rated at 1 watt to withstand the fault conditions
specified by IEEE 802.3. If MODE1=1, after 200 ns
following the last transition, the differential voltage is
slowly reduced to zero volts in 8 J.LS to limit the back
swing of the coupling transformer to less than 0.1 V.

3
MOOE1
lPBK/WOTO_ lPBKI
.-_---

';1"

--'

~

"1"

"1"

'''~ r-

•

LAST BIT /
"Oil"
_

\

r---.,I~------.,I~

LAST BIT = 0
Tx ( - ) - - - - - - - - - - -

Tx

(+>------y--NV

Tx

(_> _ _LA_S_T_B_IT_=

_l_~,-- ~
__

C
___

o

:r!iTI",-----1

I

Figure 8. Transmit Timing
NOTE:
1. If MODE2= 1, TxEN becomes active low signal TxEN.

-seeQ
MD4000221A

Technology, Incorporated

4-35

1

I

1

(-)

Receive Timing

B023A

TA=O°C to 70°C; Vcc=5 V± 10%

Symbol

Parameter

Max.

Units

ht

CSN Assert Delay Time

240

ns

h2

CSN Deasserts Delay Time (measured
from Last Bit Boundary)

240

ns

h3A

CSN Hold Time

30

h3B

CSN Set up Time

30

h4

CSN Deassertion Delay Time

10

hSA

RxD Hold Time

30

hSB
t 26 11 ]

RxD Set up Time

30

t 27 11 ]

During Clock Switch RxC Keeps High,
RXC Keeps Low Time

Min.

RxC, RxC Rise and Fall Time
40

ns
ns
35

ns
ns
ns

5

ns

200

ns

RxC, RxC High and Low Time

40

RxC, RxC Clock Cycle Time (during)
data period)

95

105

ns

t30

CSN Inhibit Time (on Transmission
Node only)

4.3

4.6

J.Ls

tat

Rx+/Rx- Rise and Fall Time

10

ns

ta2 11 ]

RxC Held Low Duration from First Valid
Negative-Going Transition

1.15

1.35

J.Ls

ta3

RxC Stops Delay Time from First Valid
Negative-Going Transition

240

ns

ta4 11 ]

Rx+/Rx- Begin Return to Zero from Last
Positive-Going Transition

he
hg l1 ]

tas l1 ]
ta6 11 ]

ns

ns

160

RxD Rise Time

10

ns

RxD Fall Time

10

ns

Rx(+)
Rx(-)

MODE2

=0
CSN

Rxe

RxD

MODE2

=1

-121

32-------Ih n n n

1

t---------

RxD

NOTE:
1. Characterized. Not tested.

seeQ
MD400022/A

-------i'ir--:-~d~-t:;=
Figure 9. Receive Timing-Start of Packet

Technology, Incorporated

4-36

B023A

MODE2 = 0

RxC

Rx(+)
Rx(-)

(LAST BIT = 0)

r--

po...----~~

CSN

--~~--------------~o--------~----~
RxD

______

~~~_"O_

.. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

~ir\----------

MODE2= 1

Rx(+)
Rx(-)
(LAST BIT = 1)

-------------~O

"1"

RxD

"1"

_____~/~---------------------~;~I-------Figure 10. Receive Timing -

-- SeeQ
MD400022/A

End of Packet

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---.1

4-37

B023A
Collision Timing

TA=O°C to 70°C; Vcc=5

v±

10%

Min.

Max.

Units

86

118

ns

10

ns

70

ns

COll Asserts Delay Time

300

ns

COll Deasserts Delay Time

500

ns

CSN Asserts Delay Time

400

ns

CSN Deasserts Delay Time

600

ns

Symbol

Parameter

ts1
ts2
ts3
ts4
tss
tsa
ts7
tss

COll+/COll- Cycle Time
COll+/COll- Rise and Fall Time
COll+/COll- High and low Time

35

COll+/COll- Width (measured at -0.3V)

26

ns

Notes:

1.
2.
3.
4.
5.

COll + and COll- asserts and deasserts COll, asynchronously, and asserts and deasserts CSN synchronously with RxC.
If COll+ and COll- arrives within 4.5,us from the time CSN was deasserted; CSN will not be reasserted (on transmission node only).
When COll+ and COll- terminates, CSN will not be deasserted if Rx+ and Rx- are still active.
When the node finishes transmitting and CSN is deasserted, it cannot be asserted again for 4.5 ,us.
If MODE2 = 1, then COll and CSN are inverted.

--

151

MODE2

=0

-153-

COLL(+)
COLL(-)

'I

(-)

-----i

f-

,l-

-f(+)

1--152

I~

l

l-

-154-

l

t

COLL

157

CSN

t

i;

Figure 11. Collision Timing

MD400022/ A

(-)

,

(+)

I

,

-156155

- seeQ

"

Technology, Incorporated

4-38

-'''1

B023A
Loopback Timing

TA=O°C to 70°C; Vcc=5 V± 10%

Max.

Symbol

Parameter

Min.

ts1

lPBK Setup Time

500

ns

ts2

lPBK Hold Time

5

/-Ls

ts3

In Collision Simulation, COll Signal
Delay Time

475

625

ns

ts4

COll Duration Time

600

750

ns

Units

Note:
1. PLL needs 12-bit cell times to acquire lock, RxD is invalid during this period. RxC is low for 1.35 JLs (max) if MODE2= 1. RxD=O if MODE2=O.
RxD=1 if MODE2=1.

MODE2 = 0

TxEN

"1"

"0"

"1"

"0"

"0"

I

"1"

"1"
(LAST BIT)

I

TxO

,

COLL

(NOTE 1)

RxC

r!

CSN

"1"
RxO

"0"

1\

_ _~,~

"1"

1\

L-J

Figure 13. Loopback Timing

-seeQ
MD4000221A

Technology, Incorporated

4-39

"1"

I

1\

~r--1

L-

B023A
MODE2 = 1

LPBK/WDTD

"1"

TxD

"0"

"0"

"1"

"0"

I

"1"

"1"

_---J/---~~---f-----

-rt - . . . . . .

,

(LAST BIT)

l~--~
"0"

"1"

"1"

"1"

RxD

Figure 14. Loopback Timing -

seeQ
MD400022/ A

(Cont.)

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

4-40

B023A
Ordering Information

D

Q

8023A

~l~

-- SeeQ
MD4000221A

PACKAGE
TYPE

TEMPERATURE
RANGE

D=CERDIP
P= PLASTIC DIP
N= PLCC

Q = O·C TO 70·C

PART TYPE
N

8023A= MCC MANCHESTER
CODE CONVERTER

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---..1

4-41

4-42

seeQ

8005
Advanced Ethernet
Data Link Controller

Preliminary

October 1988

Features
• Conforms to IEEE 802.3 Standard for Media
Access Control (Ethernet and Cheapernet)
• Recognizes One to Six Selectable Station
Addresses
• Software Selection of 2 Byte or 6 Byte
Station Addresses
• User Selectable Preamble and Frame
Check Sequence Generation
• Directly Supports 64K Bytes of Local
Packet Buffer
- Connects to RAS/CASIDatalControl of
64K x 4 Dynamic RAMS
- Automatic DRAM Refresh
• Manages Local Receiveflransmit Packet
Buffer by Buffer Chaining Technique
- Automatic Posting of Status in Buffer
Header
• Flexible System Bus Interlace
- 8 or 16 Bit Data Transfers with Byte
Swap capability
- Programmable DMA Burst Length
- Selectable for Intel or Motorola
Compatible Bus Signals
• Connects Directly to 8020 Manchester
Code Converter
• 68 Pin Surface Mount Plastic Leaded Chip
carrier Package

Pin Description
(An asterisk after a signal name signifies a low active
signal)
DO-D15: A 16 bit bidirectional system data bus, If BUSSIZE=O, the bus is configured as 8 bits and 08-015 are
not used for data transfer. 08-015 are used to provide
address information to the address PROM in both 8 and
16 bit modes, Byte order for local buffer data transfers
on a 16 bit bus is software configured,
EN*: An output which can be used to control the tri-state
control pin of external bi-directional drivers such as the
74LS245.
APEN*: Low active address PROM enable output.
IOW*/R.W.*: If busmode=1, this input defines the current bus cycle as a write. If busmode=O, this input defines
the bus cycle as a read if a 1 or a write if a O.
IOR*: If busmode=1, this input defines the current bus
cycle as a read. If busmode=O, this input is not used,

CS*: The chip select input, used to access internal
registers and the packet buffer.
AO-A3: Address select inputs used to select internal
registers for reading or writing. AD is not used in 16-bit
mode.
DACK*: An input used to acknowledge granting of thE:.
system bus for external OMA transfers. When OREQ is
active, OACK* functions as a chip select for reads and
writes.
DREQ/DREQ*: An output to an external OMA control/er
used to Signal that a OMA request is being made. This
signal is high active when busmode=1, low active when
busmode=O.
TERMCTITERMCT*: An input which Signals that the last
byte or word of a OMA access is on the bus. When
busmode=1, this input is high active; when busmode=O,
it is low active.

60 Vss
59 Vss
58 A3

INT 12
WDTD 13

57 A2

lPBK' 14

56 Al
54 lACK'

RESET' 16

53 NC

BUSMODE 17
BUSSIZE 18
CSN 19

8005
TOP VIEW

52 CS'
51 lOW'

COll 20

50 lOR'

NC 21
TXC* 22

49 Vee

E..

RXC
ClK 24

Vss ~
Vss 26

READY/DTACK*: A tri-state output. When busmode=1,
this output functions as a READY pin (Intel compatible);
when busmode = 0, this output is OTACK* (Motorola
compatible).

55 AD

Vee 15

INT/INT*: When busmode=1, this is a high active interrupt output; when busmode=O, this output is low active.

48 TERMCT'

£.

DACK'

~DREQ

45 READY

IACK*: /Jetive ION interrupt acknONledge input. When this
input is active and INT is active the contents of the interrupt vector register are placed on OO-Oz
/

~ EN'

EDLC is a registered trademark of SEEQ Technology, Inc.

seeQ T e c h n o l o g y , l n c c l r p o , r a t e 4 ' . 1 - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD400031/B

4-43

8005

Preliminary

5V

"

K
rn

~

7U _-------..II"

"N

A

~

DO-D7

'4

D G

~

~

rn

..
k

~

..

SEEE~'
E*O~\

30 PF

~:Az

NOTE~

~

.A

APEN*

~

r

~

,.

DO D7
2a04A
CE* -

/,'

I ~""'--'"

A

~ ~~:~::~_=D~a-~D~1~5~~~~

Da- D15

i

--.. fr'~

'r,::D
G

NOT NEEDED
IN 8·BIT MODE

~

II

DO-D7 EN*

IOR* (INTEL MODE)

RW. (MOTOROLA MODE)

:.,
..I..

_

Vee

L

I

~

COll-

~

!

t-

§

T

<<

!Z

39.2 OHMS 1%
~~.01UF
;

a020

:J:

Tx-

COll

39.2 OHMS 1% II:

COll+

RxD

~

<<

~~.01UF

Tx+

RxC

w

l~I&.

Vss

CSN

1

Ao

Rx+
Rx-

X1
a20MHZ

lPBK*

I I ,.

IOW*/R.w.l
IOR*

5V--,

~_ODE2

TxEN

Lt.3

~

I

OHMS , .. ,

w.

TXC*
TxD
READY/DTACK*
RESET*
INT/INT*

AD2

DREO/DREO*

AD3

DACK*
TERMCT/TERMCT*

AD4
AD5

CS*

AD6

BUSSIZE

A1

RAS*

Vee

CAS*

Vss

W*
G*

Aa
A4

en

~

AD3

~

AD4
AD5

~

01

!

A5

AD6

CII

0

A7
RAS* D03

I
NOTE:

AD2
-t

As

AD7

BUSMODE

AD1

A2

AD7

U

CAS* D02 f-W*
D01 >--G*
DOO

------

-

III

ADo

Ao

AD1

IACK*

1

5V ---,

ADo
a005

Ao85E18
A10 000
A2

Aa
A4

It)

A5

<0

0

~
~

~
As rn

~

A7

t-

u,u,

~C3~c,
I

III

I-- 5 V

tI-

L-

INTERCONNECT DIAGRAM

__ _

/IT:f~\

I

I

I

\ R.!W.

\

",-----/

/
/

MOTOROLA MODE

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

..J

MD4000311B

4-44

8005

Preliminary
RESET*: The low active reset input. Asserting RESET*
clears all configuration and pointer registers to 00.
Following reset, a wait of 4 p.s is necessary before
accessing the part.

provided for 2 byte address recognition, reduced slot time
and reduced preamble length.
The PBC provides management for a 64K byte local
packet buffer consisting of two 64K x 4 dynamic RAMS.
This block provides arbitration and control for four different memory ports: the EDLC transmitter, for network
transmit packets; the EDLC receiver, for received frames;
the BIU, for system data and control; and an internal
DRAM refresh generator. To minimize pin count, dynamiC
RAM addresses and data are time multiplexed on a
single 8 bit bus. A control line and an 8 bit address is
also provided to permit reading or writing to a locally attached EEPROM or PROM. This permits configuring a
Ae. board with its station addressees) and configuration
data independent of the network layer software used.

BUSMODE: An input which selects Intel-compatible bus
signals when high or Motorola-compatible bus signals
when low.
BUSSIZE: An input which selects 8 bit system bus when
low or 16 bit system bus when high.
ADO-AD7: A multiplexed address and data bus used to
provide row and column addresses and read/write data
to the packet buffer dynamic RAM.
RAS*: Row address strobe to the packet buffer memory.
CAS*: Column address strobe to the packet buffer
memory. Page mode addressing is used when possible
to speed access to the buffer.

The BIU interfaces to the system bus and provides access to internal configuration/status registers, the local
packet buffer and a control signal interface to permit DMA
or programmed I/O transfer of packet data. The data path
between the system bus and the local DRAM buffer is
buffered by a 16 byte FIFO called the DMA FIFO. This
permits high speed data transfers to occur even when
the PBC is busy servicing the EDLC transmitter or
receiver or refreshing the DRAM. Both 8 and 16 bit
transfers are supported, and byte ordering on a 16 bit
bus is under software control. The 8005 supports both
Intel-compatible and Motorola-compatible buses.

W*: An output to the dynamic RAM buffer that indicates
the current cycle is a write.
G*: An output to the dynamic RAM buffer that enables
read data onto the AD bus.
rXEN: An output to the Manchester Code Converter that
indicates a transmission is in progress.

rxc*: An input from the Manchester Code Converter that
is used to synchronize transmitted data.
rXD: The transmit data output to the Manchester Code
Converter.

Buffer Management
The PBC manages a 64K byte packet buffer into which

RXC: An input from the Manchester Code Converter
used to synchronize received data.

packets that are received are temporarily stored until the
system either reads or disposes of them and packets
placed there by the system are held for transmission over
the link. The buffer is logically divided into separate
receive and transmit areas of selectable size. The transmit area always originates at address o. Each packet in
the buffer is prefixed by a header of 4 bytes that contains command and status information and a 16 bit
pOinter to the start of the next packet in the buffer.

RXD: The receive data input from the Manchester Code
.Converter.

COLL: The collision input from the Manchester Code
Converter.
CSN: The carrier sense input from the Manchester Code
Converter.
WDrD: The watchdog timer disable output.

To transmit frames, the system loads one or more packets
of data, complete with header information, into the transmit area of the buffer and commands the 8005 to begin
transmission starting from the address contained in the
transmit pointer register. When transmission is complete,
the 8005 updates the status byte in the header and
interrupts the system if so programmed. The transmit pointer automatically wraps to location 0 when the
transmit end area is reached.

LPBK*: The loopback control output.
eLK: The master 20 MHz input clock.

Block Description
Three major blocks comprise the 8005: the EDLC®
(Ethernet Data Link Controller), PBC (Packet Buffer
Controller) and BIU (Bus Interface Unit).
The EDLC supports the link layer (layer 2) of the IEEE
802.3 standard. It performs serialization/deserialization, preamble generation/stripping, frame check sequence generation/stripping, transmission deferral, collision handling and address recognition of up to 6 station addresses as well as multicast/broadcast addresses.
It also supplies loopback and watchdog timer disable
outputs which can be controlled by software to provide
local diagnostic support. For non-IEEE 802.3 applications such as serial backplane buses, support is also

The PBC manages the buffer area as a circular buffer
with automatic wraparound. As data is received from the
EDLC it is stored in the buffer beginning at the location
specified by the receive pointer register. The receive
pointer will wrap from FF,FF to Transmit End Area Address + 1,00. For example, if TEA =80 the receive pOinter
wraps to 81,00. If the receive pointer reaches Receive
End Area Address + 1,00 an overflow has occurred.

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Preliminary
The receiver is then turned off and an interrupt is issued.
Restarting the receiver is accomplished by freeing up
buffer space and turning the receiver back on.

Transmit Packet Format

8005
Bit 7: Xmit/Receive. If this bit is a one, the current
header is for a packet to be transmitted. If this bit is a
zero, the frame header will be processed as a header
only, like the header only bit (bit 5).

Each packet to be transmitted consists of a four byte
header and up to 65,532 bytes of data which are placed
into the local buffer via the BIU. The header contains the
following information in the indicated order:

Byte 4 is the transmit status byte, which is written by
the PBC upon conclusion of each frame transmission
or retransmission attempt. It provides for reporting of both
normal and error termination conditions of each transmission.

1. Most significant byte of the address of the next packet
header.
2. Least significant byte of the address of the next packet
header.

BIT 0: Xmit Babble. If set to a one, transmit babble occurred during the transmission attempt. This is caused
by an attempt to transmit a packet larger than the allowed
1514 bytes, excluding preamble and CRG.

3. A transmit command byte.

4. A transmit status byte which should be initialized to

Bit 1: Xmit Collision. If set to a one, a collision occurred
during the transmission attempt.

zero by the system and will contain status for this
packet when transmission is complete.

Bit 2: 16 Collisions. If set to a one, 16 collisions occurred during the transmission attempt.

Bytes 1 and 2, called the next packet pointer, point to
the location immediately following the last byte of the
packet, which is the first byte of the next packet header,
if it exists. When in 16 bit mode, the user should note
the order of these bytes to be sure it is compatible with
the MSB-LSB storage convention of the processor/bus
being used.

Bit 7: Done. If set to a one, the controller has completed
all processing of the packet associated with this header
(either the packet has been sent successfully or 16 collisions occurred) and there is now valid status in the
status byte. The user may now reuse the buffer area.

Byte 3 is the transmit command byte. It contains information to guide the controller in processing the packet
associated with this block.
BIT 0: Xmit Babble Int. Enable. The 8005 will transmit
frames as large as the transmit buffer can hold but will
flag long frames in the transmit status byte and interrupt if this bit is set to a one. This condition is caused
by an attempt to transmit a packet larger than the allowed
1514 bytes, excluding preamble and CRG.
Bit 1: Xmit Collision Interrupt Enable. When set to a
one, a transmit interrupt will be generated if a collision
occurs during a transmit attempt.
Bit 2: 16 Collisions Enable. When set to a one, a
transmit interrupt will be generated if 16 collisions occur during a transmit attempt.
Bit 3: Xmit Success Interrupt Enable. When set to a
one, a transmit interrupt will be generated if the transmission is successful, that is, fewer than 16 colfisions
occurred.
Bit 4: Not used.
Bit 5: Header Only. If this bit is cleared to a zero, the
transmitter will process this header as a pointer only, with
no data associated with it.

Bit 3, 4, 5 and 6: Reserved.

Receive Packet Format
Each packet received is preceded by a four byte
header and is placed into the local buffer via the
PBC. The header contains the following information
in the indicated order:
1. Most significant byte of the address of the next

packed header.

2. Least significant byte of the address of the next
packet header.

3. Header status byte.
4. Frame status byte.

Bytes 1 and 2, called the next packet pointer, point to
the first byte of the next receive packet header. The
next packet header starts immediately after the end
of the current packet. The packet length is equal to
the difference between the starting addresses of the
two packet headers minus 4. If the value of the next
packet pointer is less than the current one, the pointer has wrapped around from the end of the buffer to
the Receive Start Area (the Receive Start Area equals
the Transmit End Area address + 1) and then to the

Bit 6: Chain Continue/End. If set to a one, there are
more headers in the chain to be processed. If this bit
is a zero, this header is the last one in the chain.

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8005

Preliminary
value of the next pointer. When in 16 bit mode, the
user should note the order of these bytes to be sure it
is compatible with the MSB-LSB storage convention
of the processor/bus being used.

Registers
There are nine directly accessible 16 bit registers in the
8005, one of which is used as a "window" into indirectly
accessed registers as well as the local buffer memory.
Access is controlled by chip select, I/O read, I/O write
and four address inputs, AO-A3. The following description
assumes a 16 bit wide system interface; as such, the
low order address input, AO, is shown as "X," a don't
care. In 8 bit mode, input pin AO selects bits 0 through
7 of the register when a zero, and bits 8 through 15 when
a one. Note that the byte swap bit does not affect the
byte order of these registers.

The third byte of the header contains header information associated with this packet.
Bits 0 through 4: Not used.
Bit 5: Header Only. If this bit is cleared to a zero, there
is no packet associated with this header. This enables
the controller to specify the end of a chain without touching the status of a packet already received. All 4 bytes
in a header-only packet will be 00.
Bit 6: Chain Continue/End. If this bit is set to a one,
there are more headers in this chain to be processed.
If this bit is a zero, this header is the last one in the
chain and this header space will be used for the next
packet that is received.

Command Register, A3-0=000X2 (Write only)
Bit 0: DMA Interrupt Enable. When set to a 1, completion of a DMA operation, as signaled by Terminal
Count, will generate an interrupt.
Bit 1: Rx Interrupt Enable. When set to a 1, this bit
enables interrupts whenever a packet becomes available
in the packet buffer.

Bit 7: XmitlReceive. This bit is always set to 0 by the
controller to indicate a receive packet header.

Bit 2: Tx Interrupt Enable. When set to a 1, this bit
enables interrupts for completion of transmit operations.
See the transmit header command byte description for
conditions that can cause an interrupt.

The fourth byte of the header, called the packet status
byte, contains status information resulting from processing the packet associated with this block.
Bit 0: Oversize Packet. If this bit is a one, the packet
was larger than 1514 bytes.
Bit 1: CRC Error. If this bit is a one, a CRC error (frame
check sequence error) occurred in this frame. CRC status
is captured on byte boundaries, so that 7 or less dribble bits will not cause a CRC error.
Bit 2: Dribble Error. Frames are integral multiples of
octets (bytes). If this bit is a one, the received frame did
not end on an octet (byte) boundary. This is normally not
a fatal error unless the CRC error bit is also set.
Bit 3: Short Frame. If this bit is a one, the frame contained less than 64 bytes including CRC. Short frames
are properly received as long as they are at least 6 bytes
long; frames with less than 6 bytes will only be received
if the match mode bits in configuration register #1 specify
promiscuous mode, multicast/broadcast is selected and
the first bit of the destination address is a 1, or the 2-byte
address mode has been selected.
BIT 4, 5 and 6: Not used.
Bit 7: Done. If this bit is a one, the controller has completed all processing of this frame and there are now valid
pointers and status in this header. The user may now
move this packet out of the local buffer, if desired, and
reuse this buffer space.

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MD400031/B

Bit 3: Buffer Window Interrupt Enable. Setting this bit
to a one enables interrupts for buffer window register
reads from the packet buffer.
Bit 4: DMA Interrupt Acknowledge. Setting this bit to
a one causes a pending DMA interrupt to be cleared.
Bit 5: Rx Interrupt Acknowledge. Settling this bit to
a one causes a pending receive interrupt to be cleared.
Bit 6: Tx Interrupt Acknowledge. Setting this bit to a
one causes a pending transmit interrupt to be cleared.
Bit 7: Buffer Window Interrupt Acknowledge. Setting
this bit to a one causes a pending buffer window interrupt to be cleared.
Bit 8: Set DMA On. Setting this bit to a one enables
the DMA request logic. If the DMA FIFO is set to the
read direction, a DMA request will be asserted when
the DMA FIFO has enough bytes to satisfy the burst
size. If the DMA FIFO is in the write direction the DMA
request will be asserted immediately. Clearing this bit
has no effect. Setting this bit with bit 11 set will force a
DMA interrupt, provided the DMA interrupt enable bit
is set, which permits testing the interrupt without
actually performing DMA operations.
Bit 9: Set Rx On. Setting this bit to a one enables the
EDLC receiver. Clearing this bit to a 0 has no effect. Setting this bit with bit 12 set will force an interrupt, provided
the receive interrupt enable bit is set, which permits
testing the interrupt without receiving packet data.

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Preliminary

8005

Bit 10: Set Tx On. Setting this bit to a 1 enables the
EDLC transmitter. The PBC will read the header information pointed to by the transmit pOinter and process
the frame accordingly (see transmit packet header
description). The conditions for interrupting upon completing packet processing are specified in the transmit
header command byte, which is stored in the buffer
memory. Setting this bit with bit 13 set will force a transmit
interrupt for test purposes.
Bit 11: Set DMA Off. Setting this bit to a one disables
the DMA request logic.
Bit 12: Set Rx Off. Setting this bit to a one disables the
EDLC receive logic. If the EDLC is actively receiving a
packet when bit 12 is set, the EDLC receiver will be disabled after completing reception of the packet.
Bit 13: Set Tx Off. Setting this bit to a one disables the
EDLC transmitter. If a packet is being transmitted when
this bit is set, the packet will be aborted.
Bit 14: FIFO Read. When set to a one, the DMA FIFO
direction is set to read from the packet buffer. The FIFO
direction should not be changed from a write to a read
until it is empty (see FIFO status bits).
Bit 15: FIFO Write. When set to a one, the DMA FIFO
direction is set to write to the packet buffer. Changing
the DMA FIFO direction clears the DMA FIFO.
Status Register, A3-0 = 000X2 (Read only)
Bit 0: DMA Interrupt Enable. When set, this bit indicates that interrupts are enabled for terminal count during a DMA operation.
Bit 1: Rx Interrupt Enable. When set, this bit indicates
that interrupts are enabled for receive events.
Bit 2: Tx Interrupt Enable. When set, this bit indicates
that interrupts are enabled for transmit events.
Bit 3: Buffer Window Interrupt Enable. When set,
this bit indicates that interrupts are enabled for buffer
window reads from the packet buffer.
Bit 4: DMA Interrupt. When set, this bit indicates that
a DMA operation has been completed. If the associated
interrupt enable bit is set, an interrupt will also be
asserted.
Bit 5: Rx Interrupt. When set, this bit indicates that a
receive packet chain is available. If the associated interrupt enable bit is set, an interrupt is also asserted.
Bit 6: Tx Interrupt. When set, this bit indicates that a
transmit packet or packet chain has been completed.
If the associated interrupt enable bit is set, an interrupt
is also asserted.
Bit 7: Buffer Window Interrupt. When set, this bit indicates that data has been read from the local buffer into the DMA FIFO and is ready to be read via the BIU.
If the associated interrupt enable bit has been set, an
interrupt is asserted.

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MD400031/B

Bit 8: DMA On. When set, this bit indicates that the
DMA logic is enabled. When terminal count is asserted, this bit will be reset to indicate that the DMA
activity has been completed.
Bit 9: Rx On. When set, this bit indicates that the EDLC
receiver is enabled.
Bit 10: Tx On. When set, this bit indicates that the EDLC
transmitter is enabled.
Bits 11 & 12: Not used.
Bit 13: DMA FIFO Full. When set, this bit indicates that
the DMA FIFO is full.
Bit 14: DMA FIFO Empty. When set, this bit indicates
that the DMA FIFO is empty.
Bit 15: FIFO Direction. When set, this bit indicates that
the DMA FIFO is in the read direction; when cleared,
it indicates that the DMA FIFO is in the write direction.
After hardware or software reset, this bit is cleared.
Configuration Register 1, A3-0 = 001X2
Bits 0-3: BufferCode. These four bits are the buffer window code bits, which determine the source of buffer window register reads and the destination of buffer window
register writes.

Buffer Code Selection Table
BufferCode Bits
3

2

1

0

0
0
0
0
0
0
0
0
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
1

0
0
1
1
0
0
1
1
0
0
1
X

0
1
0
1
0
1
0
1
0
1
X
X

Buffer Window Reg. Contents
Station addr. reg. 0
Station addr. reg. 1
Station addr. reg. 2
Station addr. reg. 3
Station addr. reg. 4
Station addr. reg. 5
Address PROM
Transmit end area
Local buffer memory
I nterru pt vector
Reserved - do not use
Reserved - do not use

Bits 4-5: DmaBurstlnterval. These two bits specify the
interval between DMA requests.

5

4

Burst Interval

0
0
1
1

0
1
0
1

Continuous
800 nanoseconds
1600 nanoseconds
3200 nanoseconds

If configured for continuous mode, the DMA request will
persist until TermCt is asserted.

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Preliminary
Bits 6-7: DmaBurstSize. These two bits specify the
DMA burst transfer count. In 16 bit mode, the number
of transfers is halt that in byte mode.

Bit 4: Dribble Error. When set, the receiver will accept
packets with a byte alignment error.
Bit 5: Short Frame Enable. When set, frames of less
than 512 bits (64 bytes) exclusive of preamble and start
frame delimiter bits will be received and placed in the
local buffer. Frames shorter than 6 bytes (2 bytes if bit
8= 1) will always be rejected unless the receiver is in promiscuous mode (all addresses match) or multicast/
broadcast mode and the packet is a multicast/broadcast packet.

DMA Burst Size Selection
7

6

0
0
1
1

0
1
0
1

# of DMA Transfers/Burst
1
4

8
16 (Illegal in word mode)

Bits 8-13: These six bits select which of the station
address register sets (each register set contains 6 bytes)
will be used to compare incoming destination addresses.
Bit 8 corresponds to station address register set 0, bit
9 to register set 1, ... bit 13 to register set 5. A 1 in any
bit enables that station address register set for reception. These bits are both read and write.
Bits 14-15: These two bits define the match modes for
the EDLC receiver logic.
15

14

Matchmode Description

0
0
1
1

0
1
0
1

Specific addresses only
Specific + broadcast addresses
Above + multicast addresses
All frames (promiscuous mode)

Configuration Register 2, AO-A3 = 010X2
Bit 0: ByteSwap. The normal order for packing packet
bytes into a 16 bit word is low byte first, i.e., the first byte
of a packet is contained in bits 0 through 7, the second
byte in bits 8 through 15. Setting this bit to a 1 causes
the high and low order bytes to be swapped for data
reads and writes to the buffer window when the 8005
is in 16 bit mode. Control registers are not affected. This
bit has no effect when the 8005 is in 8 bit mode. It should
not be changed when a DMA is in progress. Changing
this bit will not affect the sequence of receive data bytes
in the local buffer memory since the swap occurs on the
system (BIU) side of the buffer memory. This bit is both
read and write.
Bit 1: AutoUpdREA. If this bit is set to 1, the receive
end area register will be updated with the most significant byte of the DMA pOinter register after each DMA
transfer. In this way, as buffer memory space is released
by reading from it, free buffer space is automatically
allocated to the receive logic.

Bit 6: SlotSelect. This bit selects the slot time used
to calculate backott time following a collision. When
a 0, which is the state after reset, the slot time is 512
bits and meets the IEEE 802.3 standard; when a 1, the
slot time is 128 bits, the interframe spaCing is 24 bits
and the collision jam is 2 bytes long, which is useful
for smaller networks such as serial backplane buses.
Bit 7: PreamSelect. When this bit is a 0, which is the
state after reset, the 8005 automatically transmits an
IEEE 802.3 compatible 64 bit preamble; when set to 1,
the user must supply the preamble as part of the packet
data. The preamble must still follow the 802.3 form in
order to be recognized by other 8005's, but may have
arbitrary length. Note that a minimum of 16 preamble
bits are required by the 8005 on reception.
Bit 8: AddrLength. This bit selects the length of address
to be used in address matching. When a 0, which is the
state after reset, the length is 6 bytes, which conforms
with the IEEE 802.3 standard; when set to 1 the length
is 2 bytes, which is useful in limited networks such as
serial backplane buses.
Bit 9: RecCrc. If set to a 1, received frames will include
the CRC (Frame Check Sequence). If set to a 0, which
is the state after reset, the 4 byte CRC will be stripped
when received.
Bit 10: XmitNoCrc. If set to a 1, the transmitter will not
append the 4 byte frame check sequence to each frame
transmitted. This is useful in localloopback to perform
diagnostic checks, since it allows the software to provide its own CRC as the last four bytes of a frame to
check the EDLC receiver CRC logic. It is initialized to
o after hardware or software reset.
Bit 11: Loopback. This bit controls the external loopback pin. When set to a 1, the loopback output pin is
at Vol; after reset or when cleared to a 0, the loopback
output pin is at Voh.
Bit 12: WatchTimeDis. This bit controls the external
watchdog timer disable pin. When set to a 1, the watchdog timer disable pin is at Voh; when cleared to 0 or after
reset, the watchdog timer disable pin is at Vol.

Bit 2: Not used.
Bit 3: CRC Error Enable. When set, the receiver will
accept packets with CRC errors, place them in the local
buffer and indicate that a packet is available via the Rx
Interrupt status bit.

Bits 13-14: Not used.
Bit 15: ChipRst. Writing a 1 to this bit is the same as
asserting the hardware reset input. Chip reset should
be followed by a 4 JLs wait before attempting another
access. Reads as a O.

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Preliminary

8005

Receive End Area Register, A3-0

= 011X2

Sits 0-7: ReaPtr. The receive end area pointer contains
the high order byte of the local buffer address at which
the receive logic must stop to prevent writing over previously received packets. If the receive logic reaches
this address it will stop; the receiver will be turned off
and an interrupt will be issued. The receiver can be restarted by freeing up buffer space and turning the
receiver back 'ON' again. This register can be updated
automatically by setting bit 1in configuration register#2,
which causes ReaPtr to be updated after each DMA
read. It is both read and write.

= 100X2

Suffer Window Register, A3-0

This register provides access to the area specified
by the buffer code bits (bits 0-3) in configuration register #1. When the buffer code points to either the buffer memory (Bcode=1000 2) or the address PROM
(Bcode=0110~, the address of the data transferred
through this register is determined by the DMA pointer
register.
Receive Pointer Register, A3-0

code written into configuration register 1. Its normal use
is to provide an auto-incremented address to the local
buffer so that packet data can be moved via the BIU.
When the DMA address register is loaded, the DMA
FIFO is cleared. Therefore it is important to insure that
the DMA FIFO is empty if it is in the write direction before
loading the DMA register. When writing a packet to be
transmitted, the DMA address register automatically
wraps around to 0000 when the transmit end area (contained in an indirect register, buffer code 0111 2) has
been reached. When reading receive packets, the DMA
address register automatically wraps around to the
receive Sf t area (transmit end area + 1) when address
$FFFF has been read.

Indirectly Accessed Registers
Infrequently used registers, e.g., those that are normally
loaded only when initially configuring the 8005, are accessed indirectly by first loading the buffer code bits in
configuration register #1 with a code that points to the
desired register. Reads and writes occur through the buffer window register. All indirect registers (a total of 38)
are 8 bits wide, thus only DO-D7 are used.

= 101X2

The receive pointer register provides a 16 bit address
that pOints to the next buffer memory location into which
data or header information will be placed by the receive
logic. The low order 8 bits contain the least significant
byte of the address. Prior to enabling the receiver, this
register should be set to point to the beginning of the
receive area in the local buffer. This initial value should
be remembered by system software since it will be the
address of the first byte of the header block of the first
packet received. While receiving, the receive pointer will
be incremented for each byte stored into the local buffer. When the receive pointer increments past hex FFFF
the most significant byte will be set equal to the value
of the transmit end area + 1 and the least significant
byte will be set to 00. Reading this register may be
done at any time. It should be written only when the
transmitter is idle.
Transmit Pointer Register, A3-0

= 110X2

The transmit pointer register points to the current location being accessed by the transmit logic. Before starting the transmitter, software loads this register with the
address of the beginning of a transmit packet chain.
DMA Address Register, A3-0

= 111X2

Station Address Registers
The 8005 contains six 48-bit station address registers,
which permits one network connection to provide up to
6 different server functions. Each of these station address
registers is comprised of six 8-bit registers which must
be loaded through the buffer window register. Only those
station address registers that will be enabled for address
matching need to be loaded.
To load a station address register, first turn the receiver
off. Select the desired station number (0-5) by writing
the buffer code bits in configuration register # 1. Next
do 6 sequential byte writes to the buffer window register as follows: Write the least significant byte of the 6
byte station address; its low order bit, bit 0, will be the
first bit received. Next write the remaining 5 bytes in
ascending order. To read a station address register,
select the desired station number by writing the buffer
code bits in configuration register # 1. Do 6 sequential
reads to the buffer window; the first byte read will be
the least significant byte. If the 8005 is configured to
match 2 byte instead of 6 byte addresses, only the first
2 station address bytes are Significant, although all 6
will read and write properly.
Transmit End Area Pointer

The DMA address register provides 16 bits of address
information to the local buffer memory and 8 bits of address to the address PROM, depending on the buffer

The 8 bit value in this register defines, with 256 location
granularity, the end of the transmit packet buffer area
by specifying the highest value permitted in the most
significant byte of the transmit pointer register and, when
loading a packet to be transmitted, the DMA address
register. It also indirectly defines the receive start area

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MD4000311B

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Preliminary
address, since the PBC automatically calculates the high
order byte of this address by adding 1 to the transmit
end area pointer. To read or write this value, load the buffer code bits of configuration register #1 with the code
for the transmit end area, and do a read or write to the
buffer window register.

Interrupt Vector Register
This read/write register is accessed through the buffer
window register when the buffer code in configuration
register #1 is 9. It contains an 8 bit vector which is placed
on data bits DO-D7 during an interrupt acknowledge
cycle. If BUSMODE=O, an interrupt acknowledge cycle
is defined by INT*=O, IACK*=O and READIWRITE*=1.
When BUSMODE=1, an interrupt acknowledge cycle is
defined by INT=1, IACK*=O, and IOR*=O.

Other Buffer Window Register Uses
Address PROM Access
The 8005 supports access to up to 256 bytes of configuration data contained in a PROM or EEPROM. This
can be used for any purpose, such as storing station addresses, register configurations, network connection
data, etc. The address to the PROM is supplied by the
DMA register through data bus bits D8-D15; the data lines
from the PROM are connected to DO-D7. Chip select for
the PROM is provided by output APEN~ Before accessing this PROM, insure that transmit, receive and DMA
sections of the 8005 are disabled. Next load the PROM
starting address which you wish to access into the low
byte of the DMA register. Set the buffer code bits in configuration register #1 to point to the address PROM. Each
access to the buffer window register will chip enable the
PROM, permitting reads or writes. Successive accesses
will increment the DMA register to point to the next byte
in the PROM. If a 16 bit wide bus is used, the address
supplied to the PROM will also be read on D8-D15.

8005
Buffer Memory Access
The normal state of the buffer code bits, once the 8005
has been initialized with station addresses and buffer
areas have been allocated, is with buffer memory
selected. Access to the local buffer memory is provided
by the DMA register, which automatically increments after
each byte or word transfer. To read from or write to the
local buffer, set the buffer code to select the buffer
memory, set the FIFO direction (Command Register bits
14 and 15), load a starting address into the DMA register
and read from or write to the buffer window register. This
is the simplest way to access the local buffer as it requires no system DMA activity. It also permits network
layer software to read network control data at the beginning of a received packet to determine if it is necessary
to move the packet into global memory for further processing or simply reuse the area occupied by the packet
by updating the receive end area register. For fastest
transfer speed, e.g., to move packet data, an external
system DMA controller is supported via the DMA Request ouput, DMA Acknowledge input and Terminal
Count input signals.

Asynchronous Bus Control
The 8005 supports asynchronous bus control via the
READYIDTACK* pin. By using READYIDTACK,* the cycle
time minimums listed in the tables A thru J need not be
observed. READYIDTACK* takes care of these cycle
times. This greatly simplifies the task of interfacing to
the 8005 and also results in a higher overall data rate.
To achieve the highest possible data rate, all data transfers should terminate within 50 ns of READYIDTACK*
being asserted. This permits a sustained systE' 1 bus
transfer rate of 1.66 MWordslsec (3.33 Mbyteslsec) in
16 bit mode or 2.5 Mbytesl sec in 8 bit mode.

- SeeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

...J

MD4000311B

4-51

8005

Preliminary

Example of Chained Receive Frames
Bit #

7

5

6

Addr. ptr 1

3

4

o

2

Upper byte of next packet pointer

Addr. ptr 2

Lower byte of next packet pointer

Header status

0

1

1

X

X

X

X

X

Packet status

1

0

0

1

0

0

0

0

Data

"
"

"
Addr. ptr 1

Upper byte of next packet pointer

Addr. ptr 2

Lower byte of next packet pOinter

~

Header status

0

1

1

X

X

X

X

X

Packet status

1

0

0

1

0

0

0

0

Data

"
"
"

Addr. ptr 1

Upper byte of next packet pointer

Addr. ptr 2

Lower byte of next packet pointer

Header status

0

1

1

X

X

X

X

X

Packet status

1

0

0

1

0

0

0

0

Data

"
"
"

Addr. ptr 1

0

0

0

0

0

0

0

0

Addr. ptr 2

0

0

0

0

0

0

0

0

Header status

0

0

0

0

0

0

0

0

Packet status

0

0

0

0

0

0

0

0

Next receive packet
header goes here.
Last header in chain.

Packet Header Bytes
Transmit Header Command Byte

Receive Header Status Byte

(Byte #3)

7

6

5

4

3

(Byte #3)

2

o

7

Transmit Packet Status Byte
6

5

4

3

5

4

3

2

o

Receive Packet Status Byte

(Byte #4)

7

6

(Byte #4)

2

o

seeQ Technology, Incorporated-------------------------~
MD4000311B

4·52

8005

Preliminary
8005 Configuration and Pointer Registers
Command (write only) (A3-0 = OOOX)
15

14

13

12

11

10

15

14

13

12

11

10

15

14

13

12

11

15

14

13

12

11

15

14

13

12

11

10

9

8

X

X

X

X

X

X

X

X

15

14

13

12

11

9

7

8

6

5

4

3

2

o

4

3

2

o

4

3

2

o

4

3

2

o

4

3

2

0

Status (read only) (A3-0 = OOOX)
9

7

8

5

6

Configuration Register #1 (A3-0 = 00lX)
10

9

7

8

6

5

Configuration Register #2 (A3-0 = 010X)
10

7

8

9

5

6

Receive End Area Register (A3-0 = 011X)
7

6

5

Receive End Area Pointer

I

Receive Pointer Register (A3-0
10

9

7

8

6

=101X)
5

4

3

2

0

4

3

2

0

4

3

2

0

LOCAL BUFFER ADDRESS FOR NEXT RECEIVE BYTE

Transmit Pointer Register (A3-0 = 110X)
15

14

13

11

12

10

9

7

8

6

5

LOCAL BUFFER ADDRESS FOR NEXT TRANSMIT BYTE

DMA Address Register (A3-0 = 1l1X)
15

14

13

12

11

10

9

7

8

6

5

LOCAL BUFFER ADDRESS FOR SYSTEM READS OR WRITES

Buffer Window Register (A3-0
15

14

13

12

11

10

9

8

7

6

=100X)
5

4

3

2

BUFFER CODE BITS DETERMINE SOURCE/DESTINATION FOR READS AND WRITES

_ SeeQ Technology, Incorporated _
MD400031/B

4-53

0

Preliminary

8005
Station Address Register Format
2 of 6 Station Address Registers Shown

7

6

5

4

3

2

o

7

M
S
B

STATION ADDRESS REGISTER 1 BYTE 0
BUFFER CODE = 0001

6

5

4

3

STATION ADDRESS REGISTER 0
BUFFER CODE = 0000

BYTE 0

STATION ADDRESS REGISTER 0
BUFFER CODE = 0000

BYTE 1

STATION ADDRESS REGISTER 1 BYTE 1
BUFFER CODE = 0001

STATION ADDRESS REGISTER 0
BUFFER CODE = 0000

BYTE 2

STATION ADDRESS REGISTER 1 BYTE 2
BUFFER CODE = 0001

STATION ADDRESS REGISTER 0
BUFFER CODE = 0000

BYTE 3

STATION ADDRESS REGISTER 1 BYTE 3
BUFFER CODE = 0001

STATION ADDRESS REGISTER 0
BUFFER CODE = 0000

BYTE 4

STATION ADDRESS REGISTER 1 BYTE 4
BUFFER CODE = 0001

STATION ADDRESS REGISTER 0
BUFFER CODE = 0000

BYTE 5

STATION ADDRESS REGISTER 1 BYTE 5
BUFFER CODE = 0001

Absolute Maximum Stress Ratings

o

2

M
S
B

Recommended Operating Conditions

Temperature:
Storage . . . . . . . . . . . . . . . . .. - 65°C to + 150°C
Under Bias . ............... -10°C to +80°C
All Inputs and Outputs with
Respect to Vss. . . . . . . . . . . . . .. + 6 V to - 0.3 V

Vee Supply Voltage

5V ± 10%

Ambient Temperature

DC Operating Characteristics (Over the Vcc and Temperature Ranges)
Limits
Symbol

Parameter

IlL

Input/Output leakage

Icc

Active Vcc Current

VIL

Input low Voltage

VIH1

Min.

Max.

Unit

Test Condition

10
-10

f.lA
f.lA

VIN =Vcc
VIN = 0.1V
CS* = VIL, Outputs Open

350

mA

-0.3

0.8

V

Input High Voltage
(except TXC*, RXC, ClK)

2.0

Vcc+ 1

V

VIH2

Input High Voltage
(TXC*, RXC, ClK)

3.5

Vcc + 1

V

VOL1

Output low Voltage
(except ADo-7)

0.40

V

IOL=2.1 mA

VOl2

Output low Voltage
(AD o-7)

0.40

V

IOL= 2OO f.l A

VOH1

Output High Voltage
(except ADo-7)

2.4

V

IOH =-400f.lA

VOH2

Output High Voltage
(AD o-7)

2.4

V

IOH =-200f.lA

seeQ T e c h n o l o g y , l n c o r p o f 8 t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - - I
MD4000311B

4-54

8005

Preliminary
A.C. Characteristics (Assuming 20 MHz Input Master Clock)
Over the operating Vcc and Temperature Range
Capacitance

(Characterized -

Not Tested)

Ambient Temperature = 25°C, F = 1 MHz
Limits
Symbol

Parameter

CIN
COUT

Min.

Max.

Unit

Input Capacitance

15

pF

VIN = 0

Output Capacitance

15

pF

VOUT = 0

Electrostatic Discharge Characteristics
Symbol

Parameter

VZAP

E.S.D. Tolerance

(Characterized -

Test Condition

Not Test)
Test Condition

Value

> 2000

V

Mil-STD 883
Meth.3015

A.C. Test Conditions
Output Load:
AD0-AD7, RAS~ CAS~ W~ G*: I(load) = ± 200 JJA,
C(load) = 50 pF.
All Other Outputs: 1 TTL Gate and C(load) = 100 pF.
Input Rise and Fall Times (except TXC, RXC, CLK):
10 ns. maximum.

- SeeQ Technology, Incorporated
MD400031/B

Input Rise and Fall Times (TXC, RXC, CLK):
5 ns. maximum.
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs: 1 V and 2 V
Outputs: 0.8 V and 2 V

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----l

4-55

8005
A.C. Characteristics

(Assuming 20 MHz Input Master Clock)
Ove, the operating Vee and Temperature Range

Table A. Sus Write Cycle - SUSMODE
Ref. #

Symbol

Description

=0
Min.

1

TAVCSL

Address Setup Time

2

TRWVCSL

RIW* Setup Time

3

TCSLCSH

CS* Pulse Width

4

TDVCSL

Data Setup Time

5

TCSHDX

Data Hold Time

6

TCSLDTL

DTACK* Assertion Delay 4

7

TCSHDTH

DTACK* Deassertion Delay

8

TCSHDTZ

DTACK* Hi-Z Delay

9

TCSHAX

Address Hold Time

10
11

TCSHRWX

RIW* Hold Time

TCSHCSL

CS* High Time

12

TCSLCSL

Write Cycle Time:
a. FIFO Data Write'
b. Configuration Regs.,,2
c. Pointer Regs. 3

Max.

50
50
100
70
0

Units
ns
ns
ns
ns
ns

50
50
50

ns
ns
ns

20
20

ns

200

ns

600
600
1600

ns
ns
ns
ns

ns

50
50

ns

13

TCSLAPL

APEN* Assert Time

14

TCSHAPH

APEN* Deassert Time

15

TCSLENL

EN* Assert Delay

TCSHENH

EN* Deassert Delay

50
50

ns

16
17

TCSLDTV

CS* Active to DTACK* Valid

50

ns

ns
ns

NOTES:
1. Cycle time is for 16 bit writes. If BUSSIZE = 0 (8 bit writes). the cycle time Is 400 ns.
2. Configuration Registers are: Command/Status Register, Configuration Register #1, & 2. Interrupt Vector Register, and Station Address Registers.
3. Pointer Registers are: Receive End Area Pointer, Receive Pointer Register, Transmit Pointer Register, Transmit End Area Register, and DMA
Register. If BUSSIZE = O. the cycle time is 1000 ns.
4. DTACK* assertion will be delayed for all subsequent reads or writes until reference 12 cycle time has elapsed.

seeQ Technology, Incorporated------------------------~
MD4000311B

4-56

Preliminary

8005
®

--. f4-

~0-'

1
-.

\--®r

.

0

~~

~,

~

~.

./

~

"

~

@.

....

--. CD

-~
J

.......

HI-Z

~®-----

-~

0
00-015

@r

I

®

-....

1

HI-Z

----.. @ r---

@

,

@)

~

~~

@ I---

Figure A. Bus Write Cycle Timing Diagram -

----

@

~

I(
@JJ

BUSMODE = 0

L~oo __ ~~~-----------------------~
MD4000311B

4·57

8005

Preliminary
A.C. Characteristics

(Assuming 20 MHz Input Master Clock)

Over the operating Vee and Temperature Range

Table B. Bus Read Cycle - BUSMODE = 0
Ref. #

Symbol

Description

1

TAVCSl

Address Setup Time

50

ns

2

TRWVCSl

R/w* Setup Time

50

ns

3

TCSlDV

Read Data Delay from CS *:
a. FIFO Data
b. Configuration Regs. 1
c. Other Pointer Regs. 2

Min.

Max.

100
700
1700
ref. 3 + 50

Units

ns
ns
ns
ns
ns

4

TCSlDTl

DTACK* Assertion Delay

5

TCSlCSH

CS * Pulse Width

6

TCSHDTH

DTACK* Deassertion Delay

50

ns

7

TCSHDTZ

DTACK* Hi-Z Delay

50

ns

8

TCSHDZ

Data Hi-Z Delay

100

9

TCSHDX

Data Hold Time

20

ns

ns

100

ns

10

TCSHRWX

R/w* Hold Time

20

ns

11

TCSHAX

Address Hold Time

20

ns

12

TCSHCSl

CS* High Time

200

ns

13

TCSLCSl

Read Cycle Time

300

14

TCSLAPl

APEN * Assert Delay

50

ns

15

TCSHAPH

APEN* Deassert Delay

50

ns

16

TCSLENL

EN* Assert Delay

50

ns

17

TCSHENH

EN* Deassert Delay

50

ns

18

TCSLDTV

CS* Active to DTACK* Valid

50

ns

ns

NOTES:
1. Configuration Registers are: Command/Status Register, Configuration Register #1 & 2, Interrupt Vector Register, DMA Pointer Register, and Station
Address Registers. If BUSSIZE = 0 (8 bit writes), the read data delay is 500 ns.
2. Pointer Registers are: Receive End Area Pointer, Receive Pointer Register; Transmit Pointer Register, and Transmit End Area Register. If BUSSIZE = 0,
the read data delay is 1100 ns.

seeG)
MU400031/B

Technology, Incorporated -

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1

4-58

8005

Preliminary

--

-4-G)~

)~

AD-A3

® f4-

...

,..

I

-@

J

R/W

- ,..

f--@-l

® . .r

®

""I

..

CD
@

./

r"1/

'"

-,I

-+

or

®

"

HI-Z

J

I

@

.... 0

I

..

f+-

@

, -

@

-

~

r-®-

00-015

HI-Z

,

~ ... @....

@)

f+--

-k-

~~

Figure B. Bus Read Cycle Timing Diagram -

-

@) +--

{

@J

-

~

BUSMOOE = 0

- SeeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD4000311B

4-59

8005

Preliminary
A.C. Characteristics

(Assuming 20 MHz Input Master Clock)

Over the operating Vee and Temperature Range

Table C. Interrupt Cycle - BUSMODE = 0
Ref. #

Symbol

Description

Max.

Units

1

TIAVQV

Data Delay from IACK*

Min.

500

ns

2

TIAVDTV

DTACK* Delay from IACK*

500

ns

3

TDTLlAH

IACK* Hold from DTACK*

4

TIAHDX

Data Hold from IACK* Deassert

5

TIAHDZ

Data Hi-Z from IACK* Deassert

100

6

TIAHDTH

DTACK* Deassert from IACK*

50

ns

7

TIAHDTZ

DTACK* Hi-Z from IACK* Deassert

50

ns

8

TRHIAL

R/W* Setup Time

9

TlAHRX

R/W* Hold Time from IACK*

0

ns

20

ns
ns

20

ns

0

ns

10

TIALENL

EN* Assert Delay

50

11

TIAHENH

EN* Deassert Delay

50

ns

12

TIALDTV

IACK* Active to DTACK* Valid

50

ns

seeQ
MD400031/B

Technology, Incorporated

4-60

ns

8005

Preliminary
INT~

\-;1~--------------------------------------

[)o"07

HI-Z

t4----0 - - -..

Figure C. Interrupt Cycle Timing Diagram -

seeQ
MD400031/B

BUSMODE = 0

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----J

4-61

8005

Preliminary
A.C. Characteristics

(Assuming 20 MHz Input Master Clock)

Over the operating Vee and Temperature Range
Table D. DMA Read Cycle - BUSMODE = 0
Ref. #

Symbol

Description

Min.

1

TRWHDAL

RIW* Setup Time

2

TDALDAH

DACK* Pulse Width 1

3

TDALDV

Data Delay Time

4

TDAHDX

5

Max.

Units
ns

50
100

ns
100

ns

Data Hold Time

20

ns

TDAHDZ

Data Hi-Z Delay

100

ns

6

TDAHDAL

DACK* High Time

200

ns

7

TDALDAL

DMA Read Cycle Time

300

ns

8

TTCLDAL

TERMCT* Setup Time

0

ns

9

TDAHRWX

R/W* Hold Time

20

ns

10
11
12

TDAHTCX

2

TERMCT* Hold Time

100

ns
100

ns

TDALDRH

DREQ* Delay

TDALDTL1

DTACK* Assertion Delay 2

50

ns

50

ns

50

ns

13

TDAHDTH

DTACK* Deassertion Delay

14

TDTHDTZ

DTACK* Hi-Z Delay

15

TDRLDAL

DREQ* Setup to DACK*

16

TDALENL

EN* Assert Delay

50

ns

17

TDAHENH

EN* Deassert Delay

50

ns

18

TDALDTV

DACK* Active to DTACK* Valid

50

ns

19

TDALDTL2

Read Recovery Time 3•4

750

ns

ns

0

450

NOTES:
1. DACK* must be asserted until DTACK* is asserted and for a minimum of 100 ns
2. This delay applies only if the 8005 is "ready" when DACK* is asserted, i.e., the first read of a burst, or a read that occurs after the Ref. #19 TDALDTL2
period has elapsed.
3. The BIU pre-fetches FIFO data. Thus, data is available immediately for the first read of any burst. Once the BIU detects a read operation, it begins
fetching the next byte or word of data. This occurs during the Ref. #19 TDALDTL2 period. If a subsequent DACK* occurs within the Ref. #19 TDALDTL2
period, DTACK* will stay deasserted until the FIFO data has been fetched. If the subsequent DACK* does not occur until after the Ref. #19 TDALDTL2
period has elapsed, then the 8005 is "ready" and Ref. #12 TDALDTL 1 applies.
4. Subtract 200 ns if BUSSIZE = 0 (8 bit mode).
All the timings in this table also apply when reading data with programmed 1/0; CS* replaces DACK* and the DREQ* and TERMCT* signals do not apply.
AO-A3 setup times are the same as R/W*.

seeQ T e c h n o / o g y , ' n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I
MD4000311B

4-62

Preliminary

8005
·t-------0----_.1+--@-...- - - - - - - _

1...

DO-D15 - - - - - - -......+-_~

R/W

----...I
HI·Z

DTACK

HI·Z

-----------~~

Figure D. DMA Read Cycle Timing Diagram -

BUSMODE

=0

I

L 5eeQ
MD4000311B

TochnoIogY. IncotpOI8fed - - - - - - - - - - - - - - - - - - - - - - - - - - - '

4-63

8005

Preliminary
A.C. Characteristics

(Assuming 20 MHz Input Master Clock)
Over the operating Vcc and Temperature Range

Table E. DMA Write Cycle - BUSMODE
Ref. #

=0

Symbol

Description

Min.

1

TRWLDAL

R/W* Setup Time

ns

2

TDALDAH

DACK* Pulse Width 1

50
100

3
4
5

TDVDAH

Data Setup Time

ns

TDAHDX

Data Hold Time

TTCLDAL

TERMCT* Setup Time

6
7
8

TDAHDAL

DACK* High Time

70
0
0
200

TDALDAL

DMA Write Cycle Time

TDALTCH

TERMCT* Hold Time

9

TDAHRWH

R/w* Hold Time

10

TDALDRH

DREQ* Delay

11
12

TDALDTL

DTACK* Assertion Delay2

TDAHDTH

13
14
15

Max.

Units

ns

ns
ns
ns

300
100

ns
ns

20

ns

100

ns

50
50

ns

DTACK* Deassertion Delay

TDTHDTZ

DTACK* Hi-Z Delay

50

ns

TDRLDAL

DREQ* Setup to DACK*

TDALENL

EN* Assert Delay

50

ns

16

TDAHENH

EN* Deassert Delay

50

ns

17

TDALDTV

DACK* Active to DTACK* Valid

50

ns

18

TDAHDTL

Write Recovery Time3.4

750

ns

0

450

ns
ns

NOTES:
1. DACK* must be asserted until DTACK* is asserted and for a minimum of 100 ns.
2. This delay applies only if the 8005 is "ready" when DACK* is asserted, i.e., the first write of a burst, or a write that occurs after Ref. #18 TDAHDTl
period has elapsed.
3. The trailing edge of DACK* initiates an internal write sequence that lasts a minimum of 450 ns and a maximum of 750 ns in 16 bit mode. Should
another DACK* occur during this period, DTACK* will remain deasserted until Ref. #18 TDAHDTl period has elapsed.lfthe subsequent DACK* does
not occur until after the internal write sequence has ended, then the 8005 is "ready" and Ref. #11 TDAlDTl applies.
4. Subtract 200 ns if BUSSIZE = 0 (8 bit mode).
A" the timings in this table also apply when writing data with programmed liD; CS* replaces DACK* and the DREQ*, TERMCT* signals do not apply.
AO-A3 setup times are the same as RIW*.

seeQ Techno/ogy,'ncorporated------------------------------I
MD4000311B

4-64

Preliminary

8005
1-4------0-----~-@-~--------

00-015

HI-Z

HI-Z

Figure E. DMA Write Cycle Timing Diagram - BUSMODE = 0

- SeeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD4000311B

4-65

Preliminary
A.C. Characteristics

8005
(Assuming 20 MHz Input Master Clock)

Over the operating Vee and Temperature Range
Table F. Bus Write Cycle - BUSMODE

=1
Min.

Units

Symbol

Description

1

TAVWL

Address Setup Time

50

ns

2

TCSLWL

CS· Setup Time

50

ns

3

TWLWH

lOW· Pulse Width

100

ns

4

TDVWH

Data Setup Time

70

ns

5

TWHDX

Data Hold Time

0

6

TWLRYL

READY Deassert Delay

35

ns

7

TCSLRYV

lOW· Active to READY Valid

50

ns

8

TCSHRYZ

READY Delay to Hi-Z

50

ns

9

TWHAX

Address Hold Time

20

10

TWHCSH

CS· Hold Time

20

ns

11

TWHWL

Write Recovery Time

200

ns

12

TWLCSL

Write Cycle Time
a. FIFO Data Write'
b. Configuration Regs.1.2
c. Pointer Registers 3

600
600
1600

ns
ns
ns
ns

Ref. #

Max.

ns

ns

ns

13

TWLAPL

APEN· Assert Delay

50

14

TWHAPH

APEN* Deassert Delay

50

ns

15

TCSLENL

EN* Assert Delay

50

ns

16

TCSHENH

EN* Deassert Delay

50

ns

NOTES:
1. Cycle time is for 16 bit writes. If BUSSIZE = 0 (8 bit writes), the cycle time is 400 ns.
2. Configuration Registers are: Command/Status Register, Configuration Register #1, & 2, Interrupt Vector Register, and Station Address Registers.
3. Pointer Registers are: Receive End Area POinter, Receive Pointer Register, Transmit Pointer Register, Transmit End Area Register, and DMA
Register. If BUSSIZE = 0, the cycle time is 1000 ns.
4. READY· assertion will be delayed for all subsequent reads or writes until reference 12 cycle time has elapsed.

seeQ T e c h n o l o g y , ' n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - " '
MD400031/B

4-66

Preliminary

8005

CD - ....~!. . .~-- @

~-+--+----I~

cs
lOW

DCl)-D1S

READY

HI-Z

HI-Z

APEN

EN

Figure F. Write Cycle Timing Diagram -

BUS MODE

=1

- SeeQ Technology, Incorporated ---------------------~
MD400031/B

4-67

Preliminary
A.C. Characteristics

8005
(Assuming 20 MHz Input Master Clock)

Over the operating Vee and Temperature Range
Table G. Bus Read Cycle - BUSMODE
Ref. #

Symbol

Description

=1
Min.

Max.

Units

1

TAVRL

Address Setup Time

50

ns

1a

TCSLRL

CS * Setup Time

50

ns

2

TRHRL

Read Recovery Time

200

ns

3

TRLRYH

READY Assert Delay
a. FIFO Data
b. Configuration Regs_1
c. Pointer Registers 2

100
700
1700

ns
ns
ns
ns

35

ns

0

ns

50

ns

4

TRLRYL

READY Deassertion Delay

5

TDVRYH

Data Setup to READY Assert

6

TCSHRYZ

READY Delay to Hi-z

7

TRHDX

Data Hold Time

8

TRHDZ

Data Delay to Hi-Z

9

TRHAX

Address Hold Time

20

ns

10

TRHCSH

CS * Hold Time

20

ns

11

TRLRH

lOR * Pulse Width

12

TRLAPL

APEN * Assert Delay

50

ns

13

TRHAPH

APEN* Deassert Delay

50

ns

TCSLENL

EN* Assert Delay

50

ns

TCSHENH

EN* Deassert Delay

50

14
15
16

TCSLRYV

-50

20

CS* Active to READY Valid

ns
100

100

ns

ns

50

ns
ns

NOTES:
1. Configuration Registers are: Command/Status Register, Configuration Register #1 & 2, Interrupt Vector Register, DMA Pointer Register, and Station
Address Registers. If BUSSIZE = 0 (8 bit writes), the read data delay is 500 ns.
2. Pointer Registers are: Receive End Area Pointer, Receive Pointer Register, Transmit Pointer Register, and Transmit End Area Register. If BUSSIZE = 0,
the read data delay is 1100 ns.

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

---1

MD400031/B

4-68

Preliminary

8005

AO-AJ

cs

lOR

00-015

HI-Z

READY

APEN

EN

Figure G. Read Cycle Timing Diagram -

BUSMODE

=1

- SeeQ Technology, Incorporated --------------------~
MD400031/B

4-69

8005

Preliminary
A.C. Characteristics

(Assuming 20 MHz Input Master Clock)

Over the operating Vee and Temperature Range
Table H. Interrupt Cycle - BUSMODE

=1
Min.

Symbol

Description

1

TRLDV

Data Delay from IOR*

2

TRLRYL

READY Deassertion Delay

3

TRLRYH

4

TIAHDZ

5

Ref. #

Max.

Units

500

ns

35

ns

READY Assert Delay

500

ns

Data Delay to Hi-Z

100

ns

TIAHRYZ

READY Delay toHi-Z

50

6

TIAHDX

Data Hold from IOR*

20
50

ns
ns

7

TELRL

IACK* Setup Time

8

TIALENL

EN* Assert Delay

50

9

TIAHENH

EN* Deassert Delay

50

ns

10

TIALRYV

IACK* Active to READY Valid

50

ns

ns
ns

seeQ Technology,lncorporated-----------------------------I
MD4000311B

4-70

Preliminary

8005

\______...
1

INT

----------~s~------~

00-07

----------~s~------~-----c
HI-Z

READY ----------~$~------~~

HI-Z

------------~s~------~~

EN

Figure H. Interrupt Cycle Timing Diagram - BUSMODE = 1

seeQ
MD4000311B

Technology, Incorporated

-------------------------1
4-71

8005

Preliminary
A.C. Characteristics

(Assuming 20 MHz Input Master Clock)
Over the operating Vee and Temperature Range

Table I. DMA Write Cycle - BUSMODE

-

=1

Ref. #

Symbol

Description

1

TDALWL

DACK" Setup Time

50

ns

2

TWLWH

lOW" Pulse Width 1

100

ns

3

TDVWH

Data Setup Time

70

ns

4

TWHDX

Data Hold Time

ns

5

TWHWL

lOW" High Time

6
7

TWLWL

Write Cycle Time

0
200
300

nCHTCL

TERMCT Pulse Width

8

TTCLDRL

DREQ Delay from TERMCT

9

TWLDRL

DREQ Delay from lOW"

10

TDRHDAL

DACK" Delay

11

TWLTCH

TERMCT" Assert Delay

12

nCHWH

lOW" Hold Time

13
14
15

TWHDAH

DACK" Hold Time

TDALENL

EN* Assert Delay

TDAHENH

EN* Deassert Delay

16

TDALRYL

READY Deassert Delay

Min.

Max.

Units

ns
ns

80

ns

100
100

ns
ns

0

ns

20
80

ns

ns

0

450

ns

50

ns

50
35
750

ns

ns

17

TWHRYH

Write Recovery Time2. 3

18

TDAHRYZ

READY Delay to' Hi-Z

50

ns

19

TDALRYV

DACK" Active to READY Valid

50

ns

ns

NOTES:
1. lOW" must be asserted until READY is asserted and for a minimum of 100 ns.
2. The trailing edge of lOW" initiates an internal write sequence that lasts a minimum of 450 ns and a maximum of 750 ns in 16 bit mode. Should
another 10w* occur during this period, READY deasserts (Ref. #16 TDALRYL) and then asserts after the internal write sequence has finished
(Ref. #17 TWHRYH). If the subsequent lOW· does not occur until after the internal write sequence has ended, then Ref. #17 TWHRYH has no
meaning since READY does not deassert under this condition.
3. Subtract 200 ns when BUSSIZE = 0 (8 bit mode).

All the timings in this table also apply when writing data with programmed 110; CS· replaces DACK· and the DREQ·, TERMCT signals do not apply.
AO-A3 times are the same as CS·.

seeQ T e c h n o l o g y , ' n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD4000311B

4-72

8005

Preliminary
DREQ

TERMCT

00-015

Hi-Z

Hi-Z

READY------------~--~

Figure I. DMA Write Cycle Timing Diagram -

BUS MODE

=1

- SeeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - MD4000311B

4-73

8005

Preliminary
A.C. Characteristics (Assuming 20 MHz Input Master Clock)
Over the operating Vcc and Temperature Range
Table J. DMA Read Cycle - BUSMODE

=1

Ref. II

Symbol

Description

1

TDALRL

DACK* Setup Time

50

2

TRLRH

lOR * Pulse Width 1

100

3

TRLDV

Data Delay Time 2

4

TRHDX

Data Hold Time

20

ns

5

TRHRL

IOR* High Time

200

ns

6

TRLRL

Read Cycle Time

300

ns

7

nCHTCL

TERMCT Pulse Width

8

TTCLDRL

DREQ Delay from TERMCT

100

ns

9

TDALDRL

DREQ Delay from IOR*

100

ns

10

TDRHDAL

DACK* Delay

11

TRLTCH

12

Min.

Max.

Units
ns
ns

100

ns

ns

80

0

ns

TERMCT Assert Delay

20

ns

TTCLRH

IOR* Hold Time

80

ns

13

TRHDAH

DACK* Hold Time

0

14

TRHDZ

Data Hi-Z Delay

50

ns

15

TDALENL

EN* Assert Delay

50

ns

16

TDALENL

EN* Deassert Delay

50

ns

17

TDALRYL

READY Deassert Delay

35

ns

18

TRLRYH

Read Recovery Time3.4

750

ns

19

TDAHRYZ

READY Delay to Hi-Z

50

ns

20

TDALRYV

DACK* Active to READY Valid

50

ns

450

ns

NOTES:
1. 10R* must be asserted until READY is asserted and for a minimum of 100 ns.
2. This delay applies only if the 8005 is "ready" when lOR· is asserted, i.e., the first read of a burst or a read that occurs after the Ref. #18 TRLRYH
has elapsed.
3. The BIU pre-fetches FIFO data. Thus, data is available immediately for the first read of any burst. Once the BIU detects a read operation, it
begins fetching the next byte or word of data. This occurs during the Ref. #18 TRLRYH period. If a subsequent lOR· occurs within the Ref. #18
TRLRYH period, READY will deassert (Ref. #17 TDALRYL) and then assert after the FIFO data has been fetched (Ref. #18 TRLRYH). If the subsequent
10R* does not begin until Ref. #18 TRLRYH period has ended, then Ref. #18 has no meaning since READY does not deassert under this condition.
4. Subtract 200 ns if BUSSIZE = 0 (8 bit mode).
All the timings in this table also apply when reading data with programmed 1/0: CS· replaces DACK· and the DREQ, TERMCT signals do not apply.
AO-A3 times are the same as CS·.

seeQ
MD400031/B

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

4-74

Preliminary

8005

DREQ

TERMa-------------+____~--------~----~
00-015

------+---+<

Hi-Z
READY - -_ _ _ _ _J

Figure J. DMA Read Cycle Timing Diagram -

BUSMODE

=1

S99Q Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - -.....
MD4000311B

4-75

8005

Preliminary
A.C. Characteristics

(Assuming 20 MHz Input Master Clock)

Over the operating Vee and Temperature Range
Table K. Local Buffer Read or Write Cycle
Ref. II

Symbol

Description

Min.

1
2

TRSLAX

Row Address Hold Time

150

ns

TAVRSL

Row Address Setup Time

5

ns

200

ns

3

TRSHRSL

RAS* Pulse Width High

4

TCSLAX

Column Address Hold Time

5

TAVCSL

Column Address Setup Time

6

TCSHCSL

7

Max.

Units

45

ns

5

ns

CAS* Pulse Width - High

60

ns

TCSLCSH

CAS* Pulse Width - Low

110

ns

8

TAZGL

Address Hi-Z to G* Low Time

0

ns

9

TGLCH

G * Setup Time to G * Low

60

ns

10

TDVCSH

Data Setup to CAS *

15

ns

11

TCSHDX

Data Hold from CAS Deassert

12

TCSHDZ

Data Hi-Z from CAS Deassert

13

TAVAV

ns

0
40

ns

Read or Write Cycle Time

a Single Cycle
b. Page Mode

600
200

ns
ns
ns

14

TDVWL

Data Setup Time

10

15

TWLDX

Data Hold Time

60

ns
ns

16

TWLWH

Write Pulse Width

60

17

TCSLWL

CAS* Setup to W*

50

ns

50

ns

18

TWLCSH

Write Setup Time

19

TCSLWH

Write Hold Time

150

ns

20

TRSLRSL

RAS * Cycle Time

600

ns

seeQ T e c h n o l o g y , l n c o t p O r a t e d - - - - - - - - - - - - - - - - - - - - - - - -.......
MD40003118

4-76

8005

Preliminary
A.C. Characteristics

(Assuming 20 MHz Input Master Clock)

Over the operating Vee and Temperature Range

f4-----@----~

®~.~--------~----~
ADO-AD7

ROW ADDRESS

------~--------~r~--~~~~~

Figure K1_ Local Dram Buffer Page-Mode Read and Write Cycle Timing Diagram

@----------=---:1---~

~----------~----------~

.

~~-----------------------

ADO-AD7

W

@

i---------@---------t--Figure K2. Local Dram Buffer Single Cycle Read and Write Cycle Timing Diagram

seeQ Techno'ogy,'ncorporated------------------------------J
MD4000311B

4-77

Preliminary
A.C. Characteristics

8005
(Assuming 20 MHz Input Master Clock)

Over the operating Vee and Temperature Range

Table L. Local Buffer Refresh Cycle
Symbol

Ref. #

Description

Max.

Units

1

TAVRSL

Address Setup Time to RAS*

5

ns

2

TRSLAX

Address Hold Time from RAS*

150

ns

3

TRSLRSH

RAS* Pulse Width

200

ns

4

TRSLRSL

RAS* Cycle Time

400

ns

,

--0 1
RAS

ADO-AD7

Min.

-

0

~

,

J

,

-,

CD

K

L

) f

;

X

®

Figure L. Local Dram Buffer Refresh Cycle Timing Diagram

'--

seeQ Technology, Incorporated
MD400031/B

---

4-78

---------

Preliminary
A.C. Characteristics

8005
(Assuming 20 MHz Input Master Clock)

Over the operating Vcc and Temperature Range

Table M. Serial Interface Timing
Symbol

Description

Min.

Max.

Units

1

TCKHCKH

Txc/Rxe Cycle Time

95

1010

ns

2

TCKHCKL

Txe/Rxe High Width

45

3

TCKLCKH

Txe/Rxe Low Width

45

4

TCKLDV

T XD Delay from T xc

Ref. #

ns
ns
60

ns
ns

5

TDVCKH

RXD Setup to Rxe

30

6

TCKHDX

RXD Hold Time from Rxe

20

7

TCKLTEH

TXEN Delay from T xc

8

TCKLTEL

T XEN Hold Time from Txc

20

ns

9

TCSHCKH

CSN Setup to Rxe

20

ns

10

TCKHCSL

CSN Hold Time from Rxe

20

ns

11

TCHCL

COLL Pulse Width

Ref. 1 +10

ns

ns
60

ns

TXC
OR
RXC

TXD

RXD

TXEN

CSN

----------,

~@=='

COll

@~~--------------

\_------------

Figure M. Serial Transmit & Receive Interface Timing

seeQ Technology, Incorporated------------------------~
MD400031/B

4-79

Preliminary
A.C. Characteristics

8005
(Assuming 20 MHz Input Master Clock)

Over the operating Vcc and Temperature Range

Table N. Master Clock and Reset Timing
Ref. #

Symbol

Description

Min.

Max.

Units

1

TCKHCKl

ClK Pulse Width High

10

20

ns

2

TCKlCKH

ClK Pulse Width low

20

30

ns

3

TCKHCKH

ClK Cycle Time

49.9

50.1

4

TRSlRSH

Reset Pulse Width

10

ns
ILS

ClK

Figure N. Master Clock and Reset Timing

Ordering Information

1T

PART NUMBER
N

Q

8005

I

PRODUCT, 8005 ADVANCED EDLC
TEMPERATURE RANGE: Q
PACKAGE TYPE: N

= 0° TO 70°C

= 68 PIN PLCC

~~~~TKhOO/~~moo~~Nd----------------------------------------------~
MD4000311B

4-80

EEPLD

seeQ

EEPLD
20RA10Z
October 1988

Features
• CMOS EEPLD with Zero Standby Power:
• 10 JJA Typical, 150 JJA Maximum

• Quickly and Easily Reprogrammable In All
Package Types

• Operating Power Rises at Less Than 5 mA/MHz

• 100 Reprogramming Cycles, Minimum
• Silicon Security Bit for DeSign Secrecy

• Propagation Delay: 35, 40 or 45 ns

• 100% Field Programming Yield

• Asynchronous Architecture:
• 10 Output Macro Cells with Individually
Programmable Clocks, Preset and
Reset Signals

• 10 Years Data Retention Guaranteed

• Supported By: ABEL: CUPL: PALASM2:
PLDesigner*

• Individually Programmable and Global
Output Enable

• Programmed on Standard PAL * Device
Programmers

• Programmable Output Polarity
• Registers Can Be Bypassed Individually

• Space Saving 0.3" Wide 24-Pin

• Preloadable Output Registers Facilitate
Testing

• 28-Pin LCC and PLCC Packages in Development

Ceramic/Plastic DIP

Block Diagram
DEDICATED
INPUTS

INPUTI
OUTPUT

INPUTI
OUTPUT

INPUTI
OUTPUT

INPUTI
OUTPUT

INPUTI
OUTPUT

INPUTI
OUTPUT

INPUTI
OUTPUT

INPUTI
OUTPUT

INPUTI
OUTPUT

INPUTI
OUTPUT

* PAL, PALASM2 are registered trademarks of Monolithic Memories
a wholly-owned subsidiary of Advanced Micro Devices.
*ABEL is a trademark of DATA 110 Corporation.
* PLDesigner is a trademark of Minc Inc.
*CUPL is a trademark of Logical Devices, Inc.

seeQ
MD 4000651A

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - -.....

5-1

EEPLD
20RA10Z
General Description

Functional Description

The 20RA 10Z is functionally equivalent to the
bipolar PAL20RA 10. SEEQ's 20RA 10Z consumes
significantly less power than its bipolar equivalent:
Standby power consumption is typically less than
10 pA: active power rises at less than 5 mA per MHz
of operating frequency.

The 20RA 10Z has ten dedicated input lines and 10
programmable liD macrocells. The Registered
Asynchronous (RA) macrocell is shown on page 3.
Pin 1 of the EEPLD serves as global register preload,
pin 13 (DIP) or pin 16 (LCCIPLCC) serves as global
output enable. The exclusive-OR in evel}' macro cell
allows choosing between active high and active low
output polarity, and ensures highest possible utilization of the AND-OR array.

Bipolar devices can not be reprogrammed while UV
erasable PLDs can be reprogrammed only in windowed, ceramic packages. Electrically erasable
devices offer reprogrammability without constraints
in all package types.

Third party software packages allow users to enter
PLD designs on personal computers or engineering
workstations. Common input formats are: Boolean
Algebra, Truth- Tables, State Diagrams, Wave Forms
or schematics. The software automatically converts
such specifications into fuse patterns. These files,
once downloaded to PAL programmers, configure
PLDs according to the user's specifications.

Reprogrammability reduces development costs and
eliminates the risks involved in preprogramming production quantities. Systems can be updated quickly
by reconfiguring the EEPLDs. Reprogrammability
helps SEEQ to extensively test the entire device and
offer 100% field programming yield.
The asynchronous 20RA 10Z adds a new dimension
to PAL device flexibility. Its unique architecture
allows the designer to individually clock, set or reset
each of the 10 output macro cells, and to enablel
disable each output buffer individually.

Pin Configurations
(Top View)
20RA10Z

-=

oS

4

3

I~

()

Z

0

~

LCC PINOUT!1]

0

:::.

CD

0

2 :, 1:, 28 27 26
' ,
25 1/07

12

13 6

24 1/06

13

14 7

4

3

l!.J 28 27 26

2

21 1104

16 10

20 1103

'7

19 1102

11
12 13 14 15 16 17 18

z z I~

0

()

CJ

0

0

:::.

g

1I0s

110 5

22 NC

15 9

1109
110 7
1106

23 1105

NC 8

~

SLIM DIP PINOUT

:::.

12 5

~

20RA10Z

20RA10Z

PLCC PINOUT!1]

NC

15
16

1104
110 3

17

1102

1106
1105

12 13 14 15 16 17 18
CD

-

~

0

~

()

z

Pin Designations: I = Input
I/O = Input/Output
PL Preload
OE = Output Enable
Vcc=Supply Voltage
GND=Ground
NC = No Connection
Note:
1. Surface Mount Packages pinout conform to JEDEC Standard.

IW0 g0 g...

=

SeeQ
MD 4000651A

1100

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----1

5-2

EEPLD
20RA10Z
RA Macrocell Configuration
INPUT TERMS

~

PL

PRODUCT TERMS:

---....

OE

---,

r----

1/0

PRELOAD
DATA

I
I

--~

INPUT
PRELOAD

OUTPUT ENABLE

Programmable Preset and Reset

Bypass Mode/Registered Mode

In each macrocel/, two product lines are dedicated
to asynchronous preset and asynchronous reset. If
the preset product term is HIGH, the Q output of the
register becomes logic 1. If the reset product term is
HIGH, the Q output of the register becomes a logic O.
The operation of the programmable preset and reset
overrides the clock.

If both the preset and reset product terms are HIGH,
the flip-flop is bypassed (Bypass Mode) and the output becomes combinatorial. Otherwise, the output
is from the register (Registered Mode). Each output
can be configured to be combinatorial or registered.

Programmable Polarity
The outputs can be programmed either active-LOW
or active-HIGH. This is represented by the
Exclusive-OR gate shown in the 20RA 10Z logic
diagram. When the output polarity bit is programmed, the lower input to the Exclusive-OR gate is HIGH,
so the output is active-HIGH. Similarly when the output polarity bit is unprogrammed, the output is
active-LOW. The programmable output polarity
feature allows the user a higher degree of flexibility
when writing equations.

Programmable Clock
The clock input to each flip-flop comes from the programmable array, allowing any flip-flop to be clocked independently if desired.

Remark:The output buffer inverts the sum of products
signal.

seeQ
MD 4000651A

Technology, Incorporated

5-3

EEPLD
20RA10Z
Output Macrocell Configurations

REGISTER OUTPUT/ACTIVE HIGH

REGISTERED OUTPUT/ACTIVE LOW

ASYNCHRONOUS PRESET
PRODUCT TERM

SUM OF
PRODUCTS)

D

CLOCK

AP

I/O

I/O

Qt-+--f"

PRODUCT TERM
AR

AR
ASYNCHRONOUS RESET
PRODUCT TERM

COMBINATORIAL OUTPUT/ACTIVE LOW
(REGISTER BYPASS MODE)

SU~~

COMBINATORIAL OUTPUT/ACTIVE HIGH
(REGISTER BYPASS MODE)

I/O

I/O

SU~==:j

AR

seeQ
MD 4000651A

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

5-4

EEPLD
20RA10Z
Output Buffer with Individually Programmable
and Global Output Enable

OUTPUT ENABLE
PRODUCT TERM

=

1 OUTPUT ENABLED
0= OUTPUT DISABLED
1/0

GLOBAL
OUTPUT
ENABLE

OE
...----0<

OE Pin

1/0

1

0

Indiv. output enabled

0

X

Indiv. output disabled'

X

1

All outputs disabled'

'Output pin(s) floating or used as input(s)

Register preload allows any arbitrary state to be
loaded into the PAL device output registers. This
allows complete logic verification, including states
that are impossible or impractical to reach otherwise. To use the preload feature, first disable the outputs by bringing OE HIGH, and present the dat'!.E.t
the output pins. A LOW level on the preload pin (PL)
will then load the data into the registers. (See
Register Preload Waveform on page 10.)

Technology, Incorporated

OE Product Term

Note: Floating outputs, as well as unused or floating inputs should
be pulled HIGH or LOW. Otherwise noise, amplified through the
feedback paths or input buffers, may constantly trigger the edge
detection circuitry within the 20RA10Z and inhibit standby mode.

Register Preload

MD 4000651A

OE

OUTPUT ENABLE

The device provides a product term dedicated to
local output control. There is also a global output
control pin. The output is enabled if both the global
output control pin is LOW and the local output control product term is HIGH. If the global output control
pin is HIGH, all outputs will be disabled. If the local
output control product term is LOW, then that output
will be disabled.

seeQ

I-------~

Security Bit
A security bit prevents copying of your proprietary
design. When this bit is set, the verify data path in the
PLD is disabled, making it impossible to copy your
pattern. Since EEPLDs store patterns as electrical
charges on floating polysilicon gates (and not in
blown fuses, like other PLD technologies) it is not
possible to determine the pattern by simply examining the die. A copy protected EEPLD can be reused
after a block erase, which clears both the previously
programmed pattern and the security bit at the same
time.

-------------------------~
5-5

EEPLD
20RA10Z
EEPLD 20RA 10Z Logic Diagram
PL 1 (2

......

-

0

.

~~

...

7

10 2 (3I~

1

...

8

1

.....

..

m,

...

...

3(27) 110.

~

~2

-wr>ft ~ ~2
-'),,:-u-,TI
~-I~ 8;::fT~

,..,

15

m,~

~T~~2

2(26) 1/08

~

16

I

5)

...

e~~~n " J

...

23

~

...

...

-

24

...

..... 31

...

135 ( 6) ......

-

32

...

..... 39

.

...

........,

1
'I

"~

~

m,

~,

.

.A

...
-

48

1

~~ e,::~n
.:::t:"-

..... 55

...

.A

..
56

9 (23) 1105

"""'fJ

-~~,
-~

0(24) 1106

~J

1&-,

~

":::t:"~r:>ft
e~::n

157 ( 9) .........

~2

If=DJ,
~otb ~f=t:..
1

1

16 8 (1 0)

frDl.

~I::J'I
...... ~'::~IJ
~~
. :. .

40

47

1 (25) 1/07

~

8 (21) 1/04

7 (20) 1103

. . Tr=l~ott ~ ~~

16 (19) 1/02

~

15(18)1/0 1

1

... 63

179(1 1)

~

...
64

If=DJ,
~ott ~~
+
1

1810 ( 12)

...

71

...
.A

..

~

72

I

Tr

~
-......,

..... 79
19 11 ( 13)

~

..
0

..

39

~.~

.....:;.....

~
L<1--

14 (17) 1/00

13 (16) OE

PIN NUMBERS REFER TO DIP PINOUT (PLCC PINOUT)

SeeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - ' -_ _

----1

MD 4000651A

5-6

EEPLD
20RA10Z
Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device
failure. Functionality at or above these limits is not
implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.

Absolute Maximum Ratings
Supply voltage, Vee . .............. - 0.5 Vto 7V
DC input voltage, V,. . . . . . . . . - 0.5 V to Vee + 0.5 V
DCoutputvoltageVo ....... -0.5VtoVee +0.5V
DC output source/sink
current per output pin, 10 .............. ±35mA
DC Vee or ground current, leeorlGND .... ± 100mA
Input diode current, ' ,K:
V, Vee· ........................ +20mA
Output diode current, 10K:
Vo Vee . ........................ + 20mA
Storage temperature .......... -65°Cto 150°C
Static discharge voltage .............. > 2001 V
Latchup current . ................... > 100 mA
Ambient temperature
under bias . .............. - 55°C to + 125°C

Operating Ranges
Commercial (Q) Devices
Temperature (rA)
Operating Free Air . ............ OOCto + 75°C
Supply voltage, Vee ........... 4.75 V to 5.25 V
Industrial (E) Devices
Temperature (rA)
Operating Free Air . ......... - 40°C to + 85°C
Supply voltage, Vee . ........... . 4.5Vt05.5V
Operating ranges define those limits between which
the functionality of the device is guaranteed.

DC Characteristics over operating conditions unless otherwise specified.
Min.

Max.

Vil

Low-level input voltage

Guaranteed Input Logical LOW
Voltage for all Inputs[1]

0

0.8

Unit
V

VIH

High-level input voltage

Guaranteed Input Logical HIGH
Voltage for all Inputs[1]

2

Vee

V

hl

Low-level input current

Vee = Max.

VI=GND

-1

hH

High-level input current

Vee = Max.

VI = Vee

Vee = Min.

Iol=8 mA

0.5

Vee=5V

10l= 1pA

0.05

Vee = Min.

10H= -4.0 mA

3.80

Vcc=5V

10H= -1pA

4.95

Vo=GND[4]

-10

Symbol

Parameter

VOL

Low-level output voltage

VOH

High-level output voltage

Test Conditions

IOZl
IOZH
Icc

pA
1

pA
V
V
pA

Off-state output current

Vee = Max.

Standby supply currentl2]

10 = 0 mA, VI = GND or Vee

150

pA

Operating supply currentl3]

f= 1 MHz, 10=OmA, VI = GNDorVee

25

mA

Vo=Vec[4]

10

pA

Note: 1. These are absolute voltages with respect to the ground pin on the device and include all overshoots due to system andlor tester noise.
Do not attempt to test these values without suitable equipment.
2. Disabled output pins =Vee or GND.
3. Frequency of any input. See graph page 11 for ICC versus frequency.
4. 1/0 pin leakage is the worst case of III and 10Zl (or IIH and 10HZ).

Capacitance
Parameter
Symbol

Parameter Description

CIN

Input capacitance[1]

VIN= 2.0V at f= 1.0 MHz
Vee=5V TA=25°C

7

Output capacitance[1]

VOUT = 2.0V at f = 1.0 MHz
Vee=5VTA=25°C

8

COUT

Test Conditions

Typ.

Unit

pF

Note: 1. Sampled but not 100% tested.

seeQ
MD4000651A

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - -

5-7

EEPLD
20RA10Z
Switching Characteristics over commercial operating range(1)
-40(5)

-35
Parameter(2)

Symbol
tpD

Input or feedback to output

ts

Setup time for input or feedback to clock

tH

Hold time

teo

Clock to output or feedback(3)

twp

Preload pulse width

tsup

Preload setup time

tHP

Preload hold time

tAP

Asynchronous Preset to Registered Output(3)

tAPW

Asynchronous Preset pulse width

tAPR

Asyncronous Preset recovery time

tAR

Asynchronous Reset to Registered Output(3)

tARW

Asynchronous Reset pulse width

tARR

A.,ynchronous Reset recovery time

tWL

LOW

tWH

Width of
clock

fMAX

Maximum
frequency

tpzx

Common Enable to Output Buffer enabled

tpxz

Common Enable to Output Buffer disabled

tEA

Input to Output Buffer enabled(4)

tER

Input to Output Buffer disabled (4)

HIGH
External feedback 1/(ts + tco)
No feedback 1/(twL + twH)

Min.

Max.

Min.

35
15
10

25
25
25
15

25
15
15
15
22.2
33.3

ns
ns

ns
ns

30
15

25
15
20
20
16.6
25

ns
ns
ns

45
30
15
20
20
15.3
25

25
25
40
40

ns
ns

45

45

20
20
35
35

ns

45

45

40

Unit

45

30
25
25

30

40

Max.

20
15
40

35

25
15

Min.

40

20
15

25
20
20

-45(5)

Max.

ns
ns
ns
ns
ns
MHz
MHz

30
30
45
45

ns
ns
ns
ns

Data Retention and Endurance
Symbol

Parameter

Value

Unit

Conditions

tOR

Pattern data retention time

>10

years

Max. storage temperature
Mil-STD 883 Test Method 1008

N

Min. reprogramming cycles

100

cycles

Operating conditions

Notes:

1. The 20RA 10Z is designed for the full military operating range. Contact your nearest SEEQ representative for availability information and for
specifications of military devices.
2. Test conditions are specified in table on page 11.
3. Minimum values of these parameters are guaranteed to be larger than the hold time tHo
4. Equivalent functions to tpzx/tpxz but using product term control.
5. The 20RA 10Z-40, 20RA 10Z-45 are available and specified for commercial and industrial operating conditions.
Remark: All specified input-to-output delays include the time it takes the input edge detection circuitry to activate the device (from standby mode
into operating mode).

seeQ Technology, Incorporated -----------------------------~
MD 4000651A

5-8

EEPLD
20RA10Z
Switching Waveforms

~VT

INPUT OR
FEEDBACK

____________________~tPD~V~T---------­
COMBINATORIAL
OUTPUT
COMBINATORIAL OUTPUT (BYPASS MODE)

~"-VT_ _ _ _ _ _ _ __

INPUT OR ___________
FEEDBACK

...
'-.If---CLOCK

~~V_T________

REGISTERED
OUTPUT

REGISTERED OUTPUT (REGISTERED MODE)

OE

....-......-tpzx

14-~-tpxz

VOH - O.SV
OUTPUT

2.0V

~~~---------~~~VT

VOL + O.SV

O.BV

COMMON ENABLE (OE) TO OUTPUT DISABLE/ENABLE

INPUT

VOH - O.SV
OUTPUT

~~~--------~~~
VOL + O.SV

2.0V
O.BV

INPUT TO OUTPUT DISABLE/ENABLE

seeQ Technology, Incorporated ------------------------~
MD 4000651A

5-9

EEPLD
20RA10Z
Switching Waveforms (continued)

CLOCK WIDTH
~---- t A P W - - - - - + i

ASYNCHRONOUS
PRESET

REGISTERED
OUTPUT

..JF

tAPA

CLOCK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ASYNCHRONOUS PRESET

~---- tARw------I~

ASYNCHRONOUS
RESET

REGISTERED
OUTPUT

--'Ft

AAA

CLOCK _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
ASYNCHRONOUS RESET

uo

~'-_________))-----«'-____

PRELOAD TIMING

seeQ
MD 4000651A

Technology, Incorporated

-----------------------------1
5-10

EEPLD
20RA10Z
Switching Test Load
Vee

R1

OUTPUT

........---t4

o------...~--

Measured
Output Value

Specification

CL

R1

R2

tiL, teo

50pF

4400

1900

1.5V

TEST POINT

tpzx, tEA

50pF

4400

1900

Z-H: 2.0V
Z-L: O.BV

tpxz, tER

5pF

4400

1900

H-Z: VOH-0.5V
L-Z: VOL+0.5V

R2

ICC Versus Frequency
TYPICAL: Vee=5V,TA=25°C

100,...-----------,

75

25

10

15

20

INPUT FREQUENCY (MHz)

Key to Timing Diagrams
WAVEFORM

INPUTS

~

DON'T CARE:
CHANGE PERMITTED

CHANGING:
STATE UNKNOWN

Jtj (K

NOT APPLICABLE

CENTER LINE IS
HIGH IMPEDANCE STATE

MUST BE STEADY

WILL BE STEADY

MAY CHANGE FROM
H TO L

WILL BE CHANGING
FROM H TO L

\\\\\\\
!l/I/Jl
seeQ
MD 4000651A

MAY CHANGE FROM
L TO H

OUTPUTS

WILL BE CHANGING
FROM L TO H

Notes:
1. VT=1.5V
2. Input pulse amplitude OV to 3.0V
3. Input rise and fall times 2 - 5 ns typical

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

5-11

EEPLD
20RA10Z
'MAX Parameters
The second type of design is a simple data path application. In this case, input data is presented to the
flip-flop and clocked through; no feedback is
employed. Under these conditions, the period is
limited by the sum of the data setup time and the
data hold time (ts + tHJ. However, a lower limit for the
period of each f MAX type is the minimum clock period
(tWH + twU. Usually, this minimum clock period determines the period for the second f MAX, designated
"fMAX, No feedback:'

The parameter fMAX is the maximum clock rate at
which the device is guaranteed to operate. Because
flexibility inherent in programmable logic devices offers a choice of clocked flip-flop designs, fMAX is
specified in this case for two types of synchronous
designs.
The first type of design is a state machine with feedback signals sent off-chip. This external feedback
could go back to the device inputs, or to a second
device in a multi-chip state machine. The slowest
path defining the period is the sum of the clock-tooutput time and the input setup time for the external
signals (ts + tco). The reciprocal, fMAX' is the maximum frequency with external feedback or in conjunction with an equivalent speed device. This fMAX
is designated "fMAX, External Feedback:'

ClK

r

-

- -

-

- -

- -

-r- -

I

-

--,

••

I
I

I

I

i

_

lOGIC

~

rr......-_.....

......__
1_......
--"'. (SECOND CHIP)

....----ll
REGISTER

L _ _ _ _ _ _ _ _ _ _ _ _ .J

1-41..
1 - - - - - ts - - -.....~lfooI
..I - - - - t e o - -.....~I.-ts-+l
'MAX. External Feedback;

1/(ts + teo)

ClK

r -

-- - -

-

-

I

I

J----,
t
I

I

v

~

lOGIC

~

REGISTER

1--",

I
IL

I
___________

'MAX. No Feedback;

~ SeeQ
MD 4000651A

JI

1/(ts + tH) or 1/(tWH + twL)

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - '

5-12

EEPLD
20RA10Z
PLD Development

PLD Programmer Vendors

Development software assists the user in implementing a design in one or several PLDs. The software converts the users input into a device dependent fuse map in JEDEC format. The software
packages listed below support the 20RA 10Z
EEPLD. For more information about PLD development software contact SEEQ Technology or the software vendor directly:

Adams MacDonald
800 Airport Road, Monterey, CA 93940
(408) 373-3607

DATA 110 Corp.
10525 Willows Road NE, P.D. Box 97046,
Redmont, WA 98073-9746
(800) 247-5700
PLD Programming equipment:
System 29A or 29B
Logic Pak™303A - V04
Adaptor 303-011A for 24 pin DIP
303 - 011 B for 28 pin PLCC
Family Pinout Code for 20RA 1.0Z: 9E145

DATA 110 Corp.
10525 Willows Road, NE, P.O. Box 97046,
Redmont, WA 98073-9746
(800) 247-5700
Software offered: ABEL, PLD Test

Minc. Incorporated
1575 York Road, Colorado Springs, CO 80918
(719) 590-1155
Software offered: PLDesigner

Digilec Inc.
22736 Vanowen, Canoga Park, CA 91307
(800) 367-8750; in CA: (818) 887-3755

Kontron Electronics Inc.
630 Clyde Ave., Mountain View, CA 94039
(415) 965-7020

Logical Devices, Inc.
1021 N. W 65th Place, Fort Lauderdale, FL 33309
(305) 974-0967
Software offered: CUPL

PLD Programming
The 20RA 10Z can be programmed on standard
logic programmers. Previously programmed
devices can be reprogrammed easily, using exactly
the same procedure as required for blank EEPLDs. If
the user wants to erase a 20RA 10Z, but not program
it to a new pattern, an empty JEDEC file should be
loaded into the device programmer.

Logical Devices Inc.
1201 N. W. 65th Place, Fort Lauderdale, FL 33309
(305) 974-0967

PROMAC
see Adams MacDonald

Stag Microsystems Inc.
1600 Wyatt Dr., Santa Clara, CA 95054
(408) 988-1118

Storey Systems
3201 N. Hwy 67, Suite E, Mesquite, TX 75150
(214) 270-4135

Structured Design
333 Cobalt Way, Suite 107, Sunnyvale, CA 94086
(408) 988-0725

Varix Corporation
1210 E. Campbell, Rd., Suite 100,
Richardson, TX 75081
(214) 437-0777
For more information about PLD programmers contact SEEQ Technology 0; the programmer vendor
directly.
Logic Pak is

a trademark of DATA 110 Corporation.

seeQ
MD 4000651A

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J

5-13

EEPLD
20RA10Z
Ordering Information

P Q

T --

20

RA 10 Z - 35

-~ -~ -~

Package Type --_.....

--

TL-_ __
-

Speed
- 35 =35ns tpD
-40=40ns tpD
-45=45nstpD

P= Plastic DIP
D=Ceramic DIP
N=PLCC
L=LCC
Operating Range - - - - - - - '
Q =Commercial
E =Industrial
M=Military
Number of Array Inputs - - - -...

1------- Zero Standby Power
L..-_ _ _ _ _ _ _

Number of Outputs

Output Type
R = Registered
A = Asynchronous

- SeeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - '
MD 4000651A

5-14

MILITARY

(Military and Industrial Temperature Range)

seeQ

MIL-STD-883 Class B
Compliant Product Processing

SEEQ's Management emphasis is on Quality in products and performance, converting the results of the Technology
evolution and innovations to thegreatest benefit of our customers with an ever increased degree of system reliability,
quality, and functionality.
SEEQ's comprehensive and interactive Quality program is designed to exceed military and customer expectations
and requirements.
SEEQ's Quality program complies with MIL-STD-883 para 1.2.1 and military standards including MIL-Q-9858, MIL-I-45208,
MIL-M-38510 Appendix A, MIL-STD-45662 and FED-STD-209. Fundamental building blocks of the Quality program are
described below.

SEEQ's Military product flow (Chart 1) incorporates manufacturing processing, screening and controls. Controls
as specified in Military procedures or customer speCifications are an integral part of the processing flows in
wafer fabrication, assembly product screening and test. (Table 1)

Quality Conformance Inspection
Quality conformance testing is performed per MIL-STD883 para 1.2.1 and method 5005
Group A Tests
Group A-lot acceptance tests (see Table 2) are performed
on each SEEQ inspection lot after completion of all
screening per MIL-STD-883 method 5004 (see Table 1).
Electrical test is per applicable SEEQ specification.
Group B-Tests (see Table 3)
Group B testing is performed by package type, lead finish
and seal date code. The Group B covers all product manufactured using the same package type and lead finish
assembled with the same week of seal per MIL-STD-883
method 5005 alternate Group B test.
Group C Stresses - (see Table 4)
The product stressed, as part of Group C, is identical to
that shipped or from the same process and product family. The seal date code of the product covered will be the
same as or within the 51 * consecutive weeks following
the Group C seal date code. Electrical test is per applicable SEEQ specification.
Group 0 Stresses - (see Table 5)
Each package type and lead finish stressed, as part of
Group D, is identical to that shipped. The seal date code
of package lead finish covered will be the same as or within
the 51 * weeks following the Group D inspection lot code.

seeQ

Technology,lncotpOf8ted _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J

6-1

MIL..STD·883 Class B
Compliant Product Processing

CUSTOMER OROER

Product Processing Flow (Chart 1)

QC MONITORS
QAAUDITS

QC MONITORS

QA MONITORS

QC MONITORS

ASSEMBLY 100%
ENVIRONMENTAL
SCREENS: SEAL FINE
AND GROSS CONSTANT
ACCELERATION
TEMPERA TURE CYCLE

QC MONITORS

QC ASSEMBLY
MONITORS

QA ASSEMBLY
MONITORS

100% ELECTRICAL
TEST
+25' C. -55° C
AND +125°C

QA GROUP A ELECTRICAL
MECHANICAL
116/0+25°C.
+125°C AND -55°C

seeQ

Technology, Incorporated

QA TEST AUDITS
AND MONITORS

MARK VISUAL PACK
METHOD 2009

QA.QCI
DOCUMENTATION
REVIEW - GROUP B. C
AND D AND DATA
PREPARATION

QA SHIPPING
DOCUMENTATION
REVIEW AND
ACCEPTANCE

-----------------------------~
6·2

MIL-STD-883 Class B
Compliant Product Processing

SEEQ Screens & Tests (Table 1)
Military Screen

MIL-STD Method

Reqmt.

Internal Visual

2010, Test
Condition B

100%

Temperature Cycling

1010, Test
Condition C

100%

Constant Acceleration

2001, Y1
Orientation Only

100%

Seal
(A) Fine
(B) Gross

1014
Condition A
Condition C

100%

Visual Inspection

100%

Initial (Pre-Burn-In-Test) Per Applicable
Electrical
SEEQ Specification
Parameters

100%

Burn-In Stress

1015, Dynamic @
125°C MIN

100%

(Post-Burn-In-Test)
Electrical Parameters
Tested within 96 Hrs.

Per Applicable
SEEQ Specification

100%

Percent Defective
Allowable (PDA)
Calculation

5%

100%

Final
Electricals

Per Applicable
SEEQ Specification

100%

2009

100%

Qualification or Quality
Conformance Inspection
Test Sample Selection
External Visual

seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - "

6-3

MIL-STD-883 Class B
Compliant Product Processing

Group A Electrical Test per applicable SEEQ Specification (Table 2)
Subgroup

Description

Sample

1

Static Test @ 25°C

2

Static Test @ Max Rated Operating Temperature

116/0

3

Static Test @ Min Rated Operating Temperature

116/0

7

Functional Test @ 25°C

116/0

8A

Functional Test @ Max Rated Operating Temperature

116/0

8B

Functional Test @ Min Rated Operating Temperature

116/0

9

Switching Test @ 25°C

116/0

Switching Test @ Max Rated Operating Temperature

116/0

10
11

116/0

116/0

Switching Test @ Min Rated Operating Temperature

4

Dyanamic Test
Capacitance Testing

Performed on initial qualification and design
changes that may affect capacitance

Group B Tests (Table 3)
Test

Test
Method

Subgroup 2
Resistance to Solvents

2015

Subgroup 3
Solderability

2003

SubgroupS
Bond Strength
Ultrasonic or Wedge

2011

Test Conditions

Quality Levell
Accept Number
4 Devices (no failures)

Soldering Temperature of
+245°C Plus or Minus 5°C

LTPD 10= 1

Test Condition C or D

LTPD 15 = 1

Subgroups 1,4,6,7 and 8 have been deleted, the remaining Subgroups have not been renumbered, per MIL-STD-883, Method 5005.

Group C Stresses (Table 4)
Test
Subgroup 1
Steady-State Life Test
End-Point Electrical

seeQ

Test
Method
1005

Test Conditions
Condition 0, Equivalent to
1000 hours @ 125°C
Per SEEQ Specification

Technology, Incorporated

6-4

Quality Levell
Accept Number

LTPD5 = 1

MIL-STD-883 Class B
Compliant Product Processing

Group 0 Stresses (Table 5)

Test

MIL-STD
Test
Method

Test Conditions

Subgroup 1
Physical Dimensions

2016

Subgroup 2
Lead Integrity
Hermeticity, Fine and Gross

2004
1014

Subgroup 3
Thermal Shock
Temperature Cycling
Moisture Resistance
HermetiCity, Fine and Gross
Visual Examination
End-Point Electrical Parameters

1011
1010
1004
1014
1004
1010

Per SEEQ Specification
Per SEEQ Specification

2002
2007
2001

Condition B
Condition A
Y 1 Orientation

1014
1014
2009

Condition A
Condition C
Per SEEQ Specification
Per SEEQ Specification

Subgroup 4
Mechanical Shock
Vibration, Variable Frequency
Constant Acceleration
Hermeticity
Fine
Gross
Visual Examination
End-Point Electrical Parameters

Per SEEQ Outline Drawing

-65°C Condition B, 15 Cycles Minimum
-65°C Condition C, 100 Cycles Minimum
90% Minimum Relative Humidity

Minimum
Quality Levell
Accept Number

LTPD 15 = 1
LTPD 15

=1

LTPD 15

=1

LTPD 15

=1

LTPD 15

=1

Subgroup 5
Salt Atmosphere
Hermeticity
Fine
Gross
Visual Examination

1009

Condition A

1014
1014
1009

Condition A
ConditionC
Per SEEQ Specification

SubgroupS
Internal Wafer Vapor

1018

5,000 ppm Maximum Water Content at
T = +100°C

3 Devices, 0 Failures or
5 Devices, 1 Failure

Subgroup 7
Adhesion of Lead Finish

2025

Bend 90°, Inspect at 1Ox to 20x
Magnification

LTPD 15

Subgroup 8
Lid Torque

2024

As Applicable to Glass-Frit Packages

5 Devices, 0 Failures

seeQ

Technology, Incorporated

6-5

=1

6-6

seeQ

M528131M52813H
(Military Temperature Range)
E528131E52813H
(Extended Temperature Range)
16K Electrically Erasable PROM
October, 1988

Features

Description

•

SEEQ's M52B13 and M52B13H are 2048 x 8 bit, 5 volt
electrically erasable programmable read only
memories (EEPROMs) which are specified over the
military and extended temperature range respectively. They have input latches on all addresses, data,
and control (chip and output) enable lines. In addition,
for applications requiring fast byte write time (1 msec),
an M52B13H and E52B13H are also available. Data is
latched and electrically written by a TTL (or a 21V
pulse) on the Write Enable pin. Once written, which
requires under 10 ms, there is no limit to the number of
times data may be read. Both byte and chip erase
modes are available. The erasure time in either mode
is under 10 ms, and each byte may be erased and written a minimum of 10,000 times.

Military and Extended Temperature Range
M528131M52813H: -55° to 110°C WRITE
-55° to 125°C READ
E528131E52813H: -40° to 85°C

•

Input Latches

•

•

5V± 10% 2K X 8 EEPROM
1 ms (52B13H) or 9 ms Byte TTL Erase/Byte
Write

•

10,000 Erase/Write Cycles per Byte Minimum

•

Chip Erase and Byte Erase

•
•
•
•
•

DiTrace™
Fast Read Access Time - 250 ns
Infinite Number of Read Cycles
JEDEC Approved Byte Wide Memory Pinout
Intel M281612816A E2 Compatible

The M52B13 is compatible to the Intel M2816/2816A
and SEEQ's M5213. For system upgrades of these
older generation EEPROMs, the M52B13 is specified
over the military temperature range and has an access time of 250 ns. The M52B13 is available in a 24
pin cerdip package.

Block Diagram
Pin Configuration
M52B1~E52B13

AJ.o

A4-10

COLUMN
ADDRESS
LATCHES

COLUMN
ADDRESS
DECODE

ROW
ADDRESS
LATCHES

ROW
ADDRESS
DECODE

E2
MEMORY
ARRAY

A7

VCC

AS

As

A5

AS

A4

WE

A3

OE

A2

A10

A1

CE

AO

1/07

1/0 0

I/Os

1/01

1/05

1/02

1/04

GND

1/0 3

LATCH ENABLE
WRITE/ERASE ENABLE

Pin Names

WE

Ao-A1O

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/00 - 7

Q Cell is

a trademark of SEEQ Technology, Inc.

seeQ
MD400007!B

1/0 0_7

Technology, Incorporated

6-7

ADDRESSES

CE

DATA INPUT (WRITE OR
ERASE)
DATA OUTPUT (READ)

M52B 131M52B13H
E52B131E52B13H
tion circuit which allows either a TTL low or 21 V signal
to be applied to WE to execute an erase or write

These EEPROMs are ideal for applications that require a
non-volatile memory with in-system write and erase
capability. Dynamic reconfiguration (the alteration of
operating software in real-time) is made possible by this
device. Applications will be found in military avionics
systems, programmable character generators, selfcalibrating instruments/machines, programmable
industrial controllers, and an assortment of other systems. Designing the EEPROMs into eight and sixteen bit
microprocessor systems is also Simplified by utilizing
the fast access time with zero wait states. The addition
of the latches on all data, address and control inputs
reduces the overhead on the system controller by eliminating the need for the controller to maintain these
signals. This reduces IC count on the board and
improves the system performance.

operatiOn. The 52813 specifies no restriction on the
rising edge of WE
For certain applications, the user may wish to erase the
entire memory. A chip erase is performed in the same
manner as a byte erase except that Output Enable is
between 14 V and 22V. AII2K bytes are erased in under 10
ms.
A characteristic of all EEPROMs is that the total number
of write and erase cycles is not unlimited. The 52813 and
52813H have been designed for applications requiring
up to 10,000 write and erase cycles per byte. The write
and erase cycling characteristic is completely byte independent. Adjacent bytes are not affected during
write/erase cycling.

A fter the device is written, data is read by applying a TTL
high to WE, enabling the chip, and enabling the outputs.
Data is available, tCE time after Chip Enable is applied or
tAA time from the addresses. System power may be
reduced by placing the 528 13 or 52B13H into a standby
mode. RaiSing Chip Enable to a TTL high will reduce the
power consumption by over 60%.

Device Operation
SEEQ's 52B13 and 52813H have six modes of operation
(see Table 1) and except for the chip erase mode they
require only TTL inputs to operate these modes.
To write into a particular location of the 52813 or
52813H, that byte must first be erased. A memory location is erased by presenting the 52813 or 52813H with
Chip Enable at a TTL low while Output Enable is at TTL
high, and TTL highs (logical 1's) are being presented to
all the I/O lines. These levels are latched and the data
written when write enable is brought to a TTL low level.
The erase operation requires under 10 ms. A write operation is the same as an erase except true data is presented
to the I/O lines. The 52813H performs the same as the
52813 except that the device byte erase/byte write
time has been enhanced to 1 ms.

DiTrace®
SEEQ's family of EEPROMs incorporate a DiTrace field.
The DiTrace feature is a method for storing production
flow information to the wafer level in an extra column of
EEPROM cells. As each major manufacturing operation
is performed the DiTrace field is automatically
updated to reflect the results of that step. These
features establish manufacturing operation traceability
of the packaged device back to the wafer level. Contact
SEEQ for additional information on these features.
DiTrace is a registered trademark of SEEQ Technology, Inc.

The 52813 is compatible to prior generation EEPROMs
which required a high voltage signal for writing and
erasing. In the 52813 there is an internal dual level detecTable 1. Mode Selection (Vee = 5V ± 10%)

~

CE
(18)

Read[1]

Standby[1]
Byte Erase [2]

VIL

Byte Write[2]

VII,.

Chip Erase [2]
Write/Erase Inhibit

Mode

I/O
(9-11,13-17)

OE
(20)

WE
(21)

VIL

VIL

VIH

DOUT

VIH

Don't Care

VIH

High Z

VIH

VIL

DIN = VIH

VIH

VIL

DIN

VIL

VOE

VIL

DIN::: VIH

VIH

Don't Care

Don't Care

High Z

NOTES:
1. WE may be from VIH to 6V in the read and standby mode.
2. We may be at VIL (TTL WE Mode) or from 15 to 21 V (High Voltage WE Mode) in the byte erase, byte write, or chip erase mode of
the 52B13/52813H.

L-seeQ
MD400007/B

Technology, Incorporated

6-8

M52B13/M52813H
E528131E52B13H
Power Up/Down Considerations
SEEQ's "52B" E2 family has internal circuitry to
minimize false erase or write during system Vee
power up or down. This circuitry prevents writing
or erasing under anyone of the following
conditions:
1. Vcc is less than 3
2. A negative Write Enable transition has not
occurred when Vee is between 3 V and 5 V.

vJ1'

Under the above conditions, the outputs are in a
high impedance state.

Absolute Maximum Stress Ratlngs*
Temperature
Storage ..................... -65°C to +150°C
Under Bias . ................. -65°C to +135°C
All inputs or Outputs with
Respect to Ground .............. +6V to -O.3V
WE during Writing/Erasing
with Respect to Ground . ....... +22.5 to -O.3V

Recommended Operating Conditions

vccSu pply Voltage
Temperature Range:
M52B13/M52B13H (Case)
E52B13/E52B13H (Ambient)

5V± 10%
WRITE -55° to + 110°C
READ -55° to +125°C

-40° to +85°C

NOTE:
1. Characterized. Not tested.

seeQ
MD400007/B

Technology, Incorporated

6-9

'COMMENT: Stresses above those listed under ··Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating condi
tions for extended periods may affect device reliability

M528131M52813H
E528131E52813H

Endurance and Data Retention
Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TOR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

D.C. Operating Characteristics During Read or Write/Erase
Min.

Nom.

(Over operating Vcc and temperature range.)

Symbol

Parameter

Max.

Unit

Test Conditions

liN

Input Leakage Current

10

!J.A

V,N = Vee Max.

10

Output Leakage Current

10

!J. A

VOUT = Vee Max.

IWE

Write Enable Leakage
Read Mode

WE = V,H

10

!J. A

TTL W/E Mode

10

J.lA

WE

High Voltage W/E Mode

1.5

rnA

WE = 22V, CE = V,L

High Voltage W/E Inhibit Mode

1.5

rnA

WE = 22V, CE = V,H

Chip Erase - TTL Mode

10

J.lA

WE = V,L

1.5

rnA

WE = 22V

35

rnA

CE = V,H

90

rnA

CE = OE = V,L

0.8

V

Chip Erase-High Voltage
Mode
lee1

Vee Standby Current

lee2

Vee Active Current

V,L

Input Low Voltage

-0.1

V,H

Input High Voltage

2

Vee

VWE

WE Read Voltage

2

Vee

15
50

V

--

0.8

V

14

22

V

0.45

V

IOL = 2.1 rnA

V

10H = -400 !J.A

V

IOE= 1O !J. A

Output Low Voltage
Output High Voltage

2.4

VOE

OE Chip Erase Voltage

14

22

seeQ

Technology, Incorporated

6-10

--

V

-0.1

VOH

--

V,L

High Voltage Mode
VOL

MD4000071B

+1
+1

=::

WE Write/Erase Voltage
TTL Mode

NOTE:
1. Nominal values are for TA = 25°C and Vee = 5.0 V.

'"---

Condition

Parameter

Symbol

M528131M52813H
E528131E52813H
A.C. Operating Characteristics During Read

Symbol
tM

tCE

tOEl11

tDFl21

Device
Number
Extension

Parameter
Address Access Time

Chip Enable to Data Valid

Output Enable to Data Valid

Output Enable to High Impedance

M52B131
M52B13H
Min. Max.

E52B131
E52B13H
Min.

Max.

-250
-300
-350

250
300

250

-

350

-250
-300
-350

250
300

250

-

350

-250
-300
-350

90
90

-

-

-

90

-

110

Test
Units Conditions
ns
ns
ns

CE = OE=VIL

ns
ns
ns

OE= VIL

ns
ns
ns

CE = VIL

CE= VIL

-250
-300
-350

0
0

70
70

0

70

-

-

-

-

0

80

ns
ns
ns

0

ns

CE= OE= VIL

10
10

pF
pF

VIN = 0 V for
CIN, VOUT=OV
for COUT,
TA = 25°C

tOH

Output Hold

All

CIN/CoUTi 3 1

Input Capacitance
Output Capacitance

All
All

0
10
10

Equivalent A. C. Test Conditions [6J
Output Load: 1 TTL gate and CL

= 100 pF

Input Rise and Fall Times: ::; 20ns
Input Pulse Levels: 0.45V to 2.4V
Timing Measurement Reference Level:
1 V and 2V
Inputs
Outputs O.BV and 2V

READ TIMING
ADDRESSES

OUTPUT

ADDRESSES VALID

HIGHZ

-----+.:..::..::::..:...:=---H+1K-<
tOH

NOTES:
1. OE may be delayed ~ - tOE after the falling edge of CE without impact on tAA.
2. tDF is specified from OE oor CE, whichever occurs first
3. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
4. After tHo hold time, from WE, the inputs CE, OE, Address and Data are latched and are "Don't Cares" until t WR, Write Recovery Time, after the trailing
edge of WE.
5. The Write Recovery Time, twr, is the time after the trailing edge of WE that the latches are open and able to accept the next mode set-up conditions.
Reference Table 1 (page 2) for mode control conditions.
6. These are equivalent test conditions and actual test conditions are dependent on the tester.

seeQ
MD400007/B

Technology. Incorporated

6-11

M528131M52813H
E528131E52813H
A.C. Operating Characteristics During Write/Erase (Over the operating Vee and temperature range)
Min.

Symbol

Parameter

ts

CE, OE or Address Setup to WE

50

tDS

Data Setup to WE

15

ns

tHI41

WE to CE, OE, Address or Data Change

50

ns

twp

Write Enable (WE I Pulse Width
Byte Modes - M52B13/E52B13

9

Byte Modes - M52B13H /E52 B13H

1

WE to Mode change
WE to Start of Next Byte Write Cycle

50

tWR 1S1

Max.

Units
ns

ms

ns
2

WE to Start of Read Cycle

P.s

52B13/52B13H High Voltage Write Specifications
Except for the functional differences noted here, the 52B13 and 52B13H operate to the same specifications,
including the TTL W/E mode.
M52813~

M52B13
E52813
Symbol

Function/Parameter

twp

Write Enable Pulse Width
Byte Write/Erase
Chip Erase

VWE

WE Write/Erase Voltage
High Voltage Mode

E52813H

Min.

Max.

Min.

Max.

Units

9
9

20

1

20

ms

20

9

20

ms

14

22

14

22

V

BYTE ERASE OR BYTE WRITE TIMING

)<

ADDRESSES

VALID

I
I

DON'T CARE

/

DON'T CARE

I
I

~
I

CE

K

I
I
I

I
I

V

OE

WE

twp

I

I/O
(ERASE)

HIGHZ

HIGHZ

\

6V

1\

I
ii

i--r-tH-

I
I
I

\

I

108:_
I/O
(WRITE)

14V - - .., \- - - - - ....,

I

I

I

VALID

K

seeQ
MD4000071B

I
I
I
I
I
I

I
I
-IWR-l
I

I

I
I
I

DON'T CARE

I
BYTE ERASE/WRITE PERIOD

Notes: See AC notes
'--

DON'T CARE

I
I

I

I
I

DON'T CARE

r-

I
I
I

I

~

I-IH-

I
. - - Is
I

Technology, Incorporated

6-12

I
I

I
I

START OF NEXT MODE

M52813/M52B13H
E528131E52B13H
Chip Erase Specifications
Min.

Symbol

Parameter

ts

eE,

tOEH

DE Hold Time

twp

WE Pulse Width

tER

Erase Recovery Time

C5E Setup to WE

Max.

Units

1

p.S

1

p.S

ms

10
10

p's

Chip Erase Timing
V1H

~ ----~~~~~~~~~~~~
rts

VWE 11) _ _ _ _ -

-

-

1--------twP------~~1

-

--

14V

Vee ± 1V
VIH

Vo t 111 - - -

-

-

-

-

--_-+-------------+-....,

-

--14V
Vee

±

1V

NOTES:
1. VWE and VOE can be from 15V to 21 V in the high voltage mode for chip erase on 52813.

Ordering Information
D
D

E
M

TEMPERATURE
TYPE

RANGE

D- CERAMIC DIP

M-Military

L-LCC

E- Extended

52813
~

• 250
H·250

EEPROM BYTE WRITE TIME

2Kx8 EEPROM

(Blankl- Standard Write Time
H

- Fast Write Time

ACCESS TIME

SCREENING OPTION

250 - 250 ns

/B- MIL883 CLASS B

300-300 ns

Screened

350-350 ns

seeQ
MD4000071B

Technology. Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _.-.1

6-13

6-14

seeQ

M52B33/M52B33H
E52B33/E52B33H

64K Electrically Erasable PROM
October, 1988

Features

input latches on all addresses, data, and control (chip
and output) lines. In addition, for applications requiring
fast byte write time (1 ms), an E52 833H and M52 833H
are available. Data is latched and electrically written
by a TTL pulse on the Write Enable pin. Once written,
there is no limit to the number of times data may be
read. The erasure time is under 10 ms, and each byte
may be erased and written a minimum of 10,000 times.

• Full Military and Extended Temperature
Range
- M52B33/M52B33H: -55° to 125°C
- E52B33/E52B33H: -40° to 85°C
• 10,000 Write Cycles/Byte Over Temperature
• Input Latches
.5 V±10% Vee
• 1 ms (52B33H) or 9 ms (52B33)
TTL Byte Erase/Byte Write
• Power Up/Down Protection
• DITrace®
• Fast Read Access Tlme-250 ns
• Infinite Number ot Read Cycles
• JEDEC Approved Byte-WIde Memory Pinout

The EIM52833 is available in a 28 pin cerdip or 32
pin leadless chip carrier. The pin configuration is
to the JEDEC approved byte wide memory pinout
for these two types of packages. These EEPROMs are
ideal for applications that require a non-volatile
memory with in-system write and erase capability.
DynamiC configuration (the alteration of opening
software in real-time) is made possible by this
device. Applications will be found in military avionics
systems, programmable character generators, selfcalibrating instrument! machines, programmable
industrial control/ers, and an assortment of other

Description
SEEQ's M52833 and E52833 are 8192 x 8, 5V electrically erasable programmable read only memories
(EEPROMs) which are specified over the military and
extended temperature range respectively. They have

(continued on page 2)

Block Diagram

Pin Configurations
DUAL-IN-LiNE
TOP VIEW

COLUMN
ADDRESS
LATCHES

COLUMN
ADDRESS
DECODE

LEADLESS CHIP CARRIER
BOTTOM VIEW
~

C

INDEX
CORNER

cc
A12
A7
A6

As
3

Ag

4

A11
23

As-A12

ROW
ADDRESS
LATCHES

ROW
ADDRESS
DECODE

A11

NC

Of

E2
MEMORY
ARRAY

1/07
I/O.
I/O,

cc-

11

I/O.
I/O.
I/O.

110,

I/O.
WRITE/ERASE ENABLE

We-

Pin Names
Ao-A4
As-A12

ceoeDiTrace is a registered trademark of
SEEQ Technology, Inc.

CE

1100-7

ADDRESSES- COLUMN (LOWER ORDER BITS)
ADDRESSES - ROW
CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/00-7

DATA INPUT (WRITE OR ERASE). DATA OUTPUT (READ)

re

CHIP CLEAR

N/C

NO CONNECT

SeeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

....1

MD400009/8

6-15

M52833/M52833H
E52833/E52833H
systems. Designing the EEPROMs into eight and sixteen bit microprocessor systems is also simplified by
utilizing the fast access time with zero wait states. The
addition of the latches on aI/ data, address and control inputs reduces the overhead on the system
controller by eliminating the need for the control/er
to maintain these signals. This reduces IC count on
the board and improves the system performance.

After the device is written, data is read by applying a
TTL high to WE, enabling the chip, and enabling the
outputs. Data is available, teE time after Chip Enable
is applied or tAA time from the addresses. System
power may be reduced by placing the device into a
standby mode. Raising Chip Enable to a TTL high
will reduce the power consumption by over 60%.

DiTrace®
Device Operation

SEEQ's family of EEPROMs incorporates a DiTrace
field. The DiTrace feature is a method for storing
production flow information in an extra rowof EEPROM
cells. As each major manufacturing operation is performed the DiTrace field is automatically updated to
reflect the results of that step. These features establish
manufacturing operation traceability of the packaged
device back to the wafer level. Contact SEEQ for
additional information on these features.

SEEQ E/M52833 and E/M52833H have six modes of
operation (see Table 1) and require only TTL inputs to
operate these modes.
To write into a particular location, that byte must
first be erased. A memory location is erased by having valid addresses, Chip Enable at a TTL low,
Output Enable at TTL high, and TTL highs (logical
1's) presented to aI/ the I/O lines. Write Enable is
then brought to a TTL low level to latch aI/ the
inputs. The erase operation roquires under 10 ms. A
write operation is the same as an erase except true
data is presented to the I/O lines. The 52833H performs the same as the E/M52833 except that the byte
erase/byte write time has been enhanced to 1 ms.
A characteristic of all EEPROMs is that the total number
of write and erase cycles is not unlimited. The E/M52833
is designed for applications requiring up to 10,000 write
and erase cycles per byte over the temperature range.
The write and erase cycling characteristics are completelybyte independent. Adjacent bytes are not affected
during write/erase cycling.

Chip Clear
Certain applications may require all bytes to be
erased simultaneously. See A. C. Operating Characteristics for TTL chip erase timing specifications.

Power Up/Down Considerations
SEEQ's "528" E2 family has internal circuitry to minimize false erase or write during system Vee power
up or down. This circuitry prevents writing or erasing under anyone of the following conditions.
1. Vcc is less than 3 v.[1J
2. A negative Write Enable transition has not
occurred when Vee is between 3 V and 5 V.

Mode Selection

Writing will also be prevented if CE or OE are in a
logical state other than that specified for a byte write
in the Mode Selection table.

(Table 1)

~n
Mode
(Pin)

CE

CC

OE

WE

I/O

(20)

(1 )

(22)

(27)

(11-13,15-19)

_VIH

Read

VIL

VIH

VIL

Standby

VIH

Don't Care

Don't Care

Byte Erase

VIL

VIH

VIH

VIL

Byte Write

VIL

VIH

VIH

VIL

DIN

Don't Care

Dour
HighZ
DIN

= VIH

Chip Clear

VIL

VIL

VIH

VIL

VIL or VIH

Write/Erase Inhibit

VIH

Don't Care

Don't Care

Don't Care

HighZ

NOTE:
1. Characterized. Not tested.

seeQ
MD400009/B

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----1

6-16

M52833/M52833H
E52833/E52833H
Absolute Maximum Stress Ratlng*

·COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

Temperature
Storage . ..................... -65°C to +150°C
Under Bias . ................. -65°C to +135°C
All inputs or Outputs with
Respect to Ground.. .. . .. . . .. .. .. +6 V to -0.3 V

Endurance and Data Retention
Symbol

Parameter

Value

Units

Condition

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TOR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

Recommended Operating Conditions
Vcc Supply Voltage

5 V± 10%

Temperature Range:
M52B33/M52B33H

-55° to + 125°C

E52B33/E52B33H

(Case)
(Ambient)

-40° to + 85°C

DC Operating Characteristics During Read or Erase/Write
(Over the operating Vee and temperature range)
Nom,!1)

Symbol

Parameter

Max.

Unit

Test Condition

liN

Input Leakage Current

10

J..I.A

VIN = Vee Max

10

Output Leakage Current

10

J..I.A

VOUT = Vee Max

IWE

Write Enable Leakage
Read Mode
W/E Mode

10
10

J..I.A
J..I.A

WE= VIH
WE= VIL

Min.

lee1

Vee Standby Current

15

50

mA

CE= VIH

lee2

Vee Active Current

50

120

mA

CE= OE=VIL

--

Input Low Voltage

-<>.1

0.8

V

VIi;

Input High Voltage

2

VOL

Output Low Voltage

VOH

Output High Voltage

VIL

Vee

+1

0.45
2.4

V
V

IOL = 2.1 mA

V

IOH =-400 J..I.A

NOTE: See next page for notes.

SeeQ·TeChnOIOgy, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD400009/B
6-17

M52B33/M52B33H
E52B33/E52B33H
A.C. Operating Characteristics During Read
(Over the operating Vee and temperature range)
Device
Number
Extension

Symbol

Parameter

tAA

Address Access Time

-250
-300

tCE

Chip Enable to Data Valid

tOE(2l

M52B33
M52B33H
Min.

E52833
E52833H
Min.

Max.

Test
Conditions

Max.

Unit

250
300

250
300

ns
ns

CE= OE= VIL

-250
-300

250
300

250
300

ns
ns

OE= VIL

Output Enable to Data Valid

-250
-300

90
90

90
90

ns
ns

CE= VIL

tDFI3l

Output Enable to High Impedance

-250
-300

0
0

70
70

ns
ns

CE = VIL

tOH

Output Hold

All

0

ns

CE = OE = VIL

CIN!
Co uT(4)

InpuVOutput Capacitance

All

10

pF

VIN = 0 V for
CIN. VOUT = 0 V
for COUT.
TA = 25°C

70
70

0
0
0

10

Read Cycle Timing

\j.i----------- ~
ADDRESSES

P

_ _ _ _ _.1

ADDRESSES VALID

,.~_ _ _ _ _ _ _ _ _ _ _ _ _

____

1"0------------ I'""
----+-----\
V
\

I-ICE-

~

~---+---------

I-

foe[2[ -

HIGHZ

OUTPUT _ _ _ _ _ _+-_H_IG_H_Z
_ _ _H/I_/H/~/:_10

Years

MIL-STD 883 Test
Method 1008

NOTES:
1. Chip Erase is an optional mode.
2. Characterized. Not tested.

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MD400017/B

Technology, Incorporated

6-22

E/M2816A
DC Operating Characteristics

(Over the operating Vcc and temperature range)
Limits

Symbol

Parameter

Max.

Units

Icc

Active Vcc Current

125

mA

CE = OE = VIL; All I/O Open;
Other Inputs = 5.5 V

ISB

Standby Vcc Current

40

mA

CE = VIH, OE = VIL; All I/O's
Open; Other Inputs = 5.5 V

Min.

Test Condition

= 5.5 V
= 5.5 V

III

Input Leakage Current

10

IlA

VIN

ILO

Output Leakage Current

10

IlA

VOUT

VIL

Input Low Voltage

-0.1

0.8

V

VIH

Input High Voltage

2.0

6

V

VOL

Output Low Voltage

0.4

V

IOL

VOH

Output High Voltage

V

IOH

2.4

= 2.1 mA
= -400 IlA

AC Characteristics
Read Operation (Over the operating Vcc and temperature range)
Limits

Symbol

E/M2816A-250

E/M2816A-350

Parameter

Min.

Min.

250

Max.

Max.

tRC

Read Cycle Time

tCE

Chip Enable Access Time

250

350

ns

tAA

Address Access Time

250

350

ns

100

ns

tOE

Output Enable Access Time

tLl

CE to Output in Low Z

tHl

CEto Output in High Z

tOLl

OE to Output in Low Z

toHZ

OE to Output in High Z

350

Units

90
10

ns

10
100

50

ns
100

ns

100

ns

50
100

ns

toH!1]

Output Hold from Address Change

20

20

ns

tpu l1 ]

CE to Power-up Time

0

0

ns

tpO[1]

CE to Power Down Time

Capacitance[21 TA=25°C, f=1

Max

[nput Capacitance

COUT

Data (I/O) Capacitance

Parameter

VZApl1]

E.S.D. Tolerance

Conditions

6 pF VIN= 0 V
10 pF VI/o= OV

Value

Test Conditions

>2000 V

MIL-STD 883
Test Method 3015

NOTES:
1. Characterized Not tested.
2. This parameter measured only for the initial qualification and after process or design changes which may affect capacitance.

seeQ

MD400017/B

ns

Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: <20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V

E. S. D. Characteristics
Symbol

50

Equivalent A.C. Test Conditions

MHz

Symbol Parameter
CIN

50

Technology, Incorporated

6-23

E/M2816A
Read Cycle Timing
IRC

ADDRESS

=>-:

~CIAA
ICE

IAA

r-

\=

CE

j
f---IOE-

\

0-

J

-'~

-.--IO HZ -

I - I OLZ -

DATA OUT

_IOH -

HIGHZ
..J

_I

LZ

_

:J~

_ IHZ -

-K

DATA VALID

-r-

~~

DATA VALID

..,

_ lpU

!

VCC

SUPPLY
CURRENT

ISB

~L

Icc

_lpO-

A C Characteristics
Write Operation

(Over the operating Vcc and temperature range)

Limits
E/M2816A·250

E/M2816A·350

Min.

Min.

Symbol

Parameter

twc

Write Cycle Time

Max.

tAS

Address Set Up Time

10

10

ns

tAH

Address Hold Time

50

70

ns

tcs

Write Set Up Time

0

0

ns
ns

10

Max.

Units

10

ms

tCH

Write Hold Time

0

0

tcw

CE to End of Write Input

150

150

ns

tOES

OE Set Up Time

10

10

ns

tOEH

OE Hold Time

10

10

ns

twp[1]

WE Write Pulse Width

150

150

ns

tOL

Data Latch Time

50

toV[2]

Data Valid Time

tos

Data Set Up Time

50

50

ns

tOH

Data Hold Time

0

0

ns

50
1

ns

1

j1S

Notes:
1. WE is noise protected. Less than a 20 ns write pulse will not activate a write cycle.
2. Data must be valid within 1 IlS maximum after the initiation of a write cycle.

seeQ

MD4000171B

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

6-24

E/M2816A
TTL Byte Write Cycle
CE CONTROLLED WRITE CYCLE

WE CONTROLLED WRITE CYCLE

Ordering Information

~r
__________~===T~D__

1aI6A-;rLo~1====~____==~~____

PACKAGE
TYPE

TEMPERATURE
RANGE

PART TYPE

ACCESS TIME

SCRi:ENING OPTION

D- CERAMIC DIP

M- -SS'C to +12S'C
(MUltalY!
E - -40'C to +SS'C
(Extended)

2KxSEEPROM

250-250 ns
350-350 ns

/S- MILSS3 CLASS B
Screened

seeQ

Technology, Incorporated

MD400017/B

-------------------------------~
6-25

6-26

seeQ

E/M2817A

Timer £2
16K Electrically Erasable PROMs
February 1987

Description
Features
• Military and Temperature Range
• -55°C to +125°C: M2817A (Military)
• -40°C to +85°C: E2817A (Extended)
• Read/Busy Pin
• High Endurance, 10,000 Byte Write Cycles
Minimum
• On-Chip Timer
• Automatic Byte Erase Before Byte Write
• 5 V ± 10% Power Supply
• Power Up/Down Protection Circuitry
• 250 ns max. Access Time
• Low Power Operation
• 110 mA Active Current
• 40 mA Standby Current
• JEDEC Approved Byte-Wide Pinout

SEEQ's M2817A is a 5 V only, 2K x 8 electrically
erasable programmable read only memory
(EEPROM). It is packaged in a 28 pin package and
has a ready/busy pin. This EEPROM is ideal for
applications which require non-volatility and insystem data modification. The endurance, the
minimum number of times which a byte may be
written, is _10 thousand cycles.
The M2817A has an internal timer that automatically
times out the write time. The on-chip timer, along
with the input latches, frees the microcomputer system for other tasks during the write time. The 2817A's
write cycle time is 10 ms over the military temperature

Pin Configuration
LEAD LESS CHIP CARRIER
BOTTOM VIEW

DUAL-IN-LINE
TOP VIEW

Block Diagram

~

«
ROY/BUSY

Vee

We

NC

COLUMN
ADDRESS
LATCHES

A,

As

A.

;

A.

.

A3
A,
A,
A.

I/O.
I/O,
I/O,

A.

NC

)

A.

E2
MEMORY
ARRAY

INDEX
CORNER

A.

6

NC

7

DE
A, •

,.

CE

A,
NC
NC

OE
A,.

I/O, CE
I/O.
I/O,
I/O.

11

NC

l)

GND

1/03

Pin Names

OE

Ao-.

ADDRESSES - COLUMN (LOWER ORDER BITS)

A.- 1o

ADDRESSES - ROW

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/0 0 _ 7

DATA INPUT (WRITE OR ERASE), DATA OUTPUT
(READ)

RDY/BUSY DEVICE READY/BUSY
N/C

NO CONNECT

seeQ Technology, Incorporated --------------------------~
MD4000151A

6-27

E/M2817A
Power Up/Down Considerations

range. An automatic byte erase is performed before a
byte operation is started. Once a byte has been
written, the ready/busy pin signals the microprocessor
that it is available for another write or a read cycle.
All inputs are TTL for both the byte write and read
mode. Data retention is specified for ten years.

The M2817A has internal circuitry to minimize a false
write during system Vcc power up or down. This
circuitry prevents writing under anyone of the following conditions.
121
1. Vcc is less than 3 v.
2. A negative Write Enable (WE) transition has not
occurred with Vcc is between 3 V and 5 V.

Device Operation
There are five operational modes (see Table 1) and,
except for the chip erase mode,f11 only TTL inputs are
required. To write into a particular location, a TTL
low is applied to the write enable (WE) pin of a
selected (CE low) device. This, combined with output
enable (OE) being high, initiates a write cycle. During
a byte write cyole, addresses are latched on either
the falling edge of CE or WE, whichever one occurred
last. Data is latched on the rising edge of CE or WE,
whichever one occured first. The byte is automatically
erased before data is written. While the write operation is in progress, the ROY/BUSY output is at a TTL
low. An internal timer times out the required byte
write time and at the end of this time, the device
signals the ROY/BUSY pin to a TTL high. The ROY/
BUSY pin is an open drain output and a typical3K n
pull-up resistor to Vcc is required. The pull-up resistor
value is dependent on the number of OR-tied 2817A
ROY/BUSY pins.

Writing will also be prevented if CE or OE are in
TTL logical states other than that specified for a
byte write in the Mode Selection table.

Absolute Maximum Stress Ratings'"
Temperature
Storage . .................. -65°C to +150°C
Under Bias ................ -10°C to +135°C
All Inputs or Outputs with
Respect to Ground ............. +6V to -O.3V

'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may
affect device reliability.

Mode Selection (Table 1)
ROY/BUSY

Mode/Pin

CE

OE

WE

I/O

Read

VIL

VIL

VIH

DouT

HighZ

Standby

VIH

X

X

HighZ

HighZ

Byte Write

VIL

VIH

VIL

DIN

VOL

X
X

VIL
X

X
VIH

High Z/DouT
High Z/DouT

HighZ
HighZ

Write
Inhibit
X: Any TTL Level.

Recommended Operating Conditions
M2817A-300
M2817A-250

I
I

Vce Power Supply

5 V± 10%

Temperature Range

E2817A-300
E 2817A-250
5 V± 10%

(Case) -55°C to +125°C

(Ambient) -40°C to +85°C

Endurance and Data Retention
Symbol

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TOR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

NOTES:

1. Chip Erase is an optional mode.
2. Characterized. Not tested.

seeQ
MD400015/-

Technology, Incorporated

6-28

Condition

E/M2817A
D.C. Operating Characteristics

(Over the operating Vee and temperature range)
Limits

Symbol

Parameter

Min.

Max.

Units

Icc

Active Vec Current
(includes Write Operation)

110

mA

CE = OE = VIL; All I/O Open;
Other Inputs = 5.5 V

IS8

Standby Vce Current

40

mA

CE = VIH, OE = VIL All I/O
Open; Other Inputs = 5.5 V

III

Input Leakage Current

10

p.A

VIN

ILO

Output Leakage Current

10

p.A

VOUT

VIL

Input Low Voltage

-0.1

0.8

V

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Vcc

+1

Test Condition

= 5.5 V
= 5.5 V

V

0.4
2.4

V

IOL

V

IOH

= 2.1 mA
= -400 p.A

A.C. Characteristics
Read Operation

(Over the operating Vcc and temperature range)
Limits
E/M2817A-250

Max.

Symbol

Parameter

Min.

tRC

Read Cycle Time

250

tCE

Chip Enable Access Time

250

tAA

Address Access Time

tOE

Output Enable Access Time

tOF

Output Enable High to Output
Not being Driven

0

tOH

Output Hold from Address Change, Chip
Enable, or Output Enable whichever occurs
first

0

Read Cycle Timing
ADDRESSES

~
I

E/M2817A-300

Min.

CE

ns

OE

250

300

ns

CE

90

100

ns

CE

60

ns

CE

= OE = VIL
= VIL
= OE = VIL
= VIL
= VIL

ns

CE

= OE = VIL

60

0
0

~

---I

p-

I
-,
I

I--tce-l

,r~

I--tOF:-+
tOH---!

tAA

seeQ

MD400015/A

Technology, Incorporated

6-29

Test Conditions

300

ADDRESSES VALID

OUTPUT __________~----------_+~

Units
ns

tRC

\

Max.

300

VALID
OUTPUT

E/M2817A
Capacitance[11TA=25°C, f=1
Symbol Parameter

Max

CIN

Input Capacitance

COUT

Data (I/O) Capacitance

A.C. Test Conditions

MHz

Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: <20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 Vand 2 V

Conditions

6 pF VIN= 0 V
10 pF VI/o= 0 V

E.S.D. Characteristics
Symbol Parameter
VZAp I2]

E.S.D. Tolerance

Value

Test Conditions

MIL-STD 883
>2000 V Test Method 3015

AC Characteristics
Write Operation (Over the operating Vccand temperature range)
Limits
E/M2817A-250

E/M2817 A-300

Symbol

Parameter

tAS

Address to Write Set Up Time

10

10

tcs
twpl3]

CE to Write Set Up Time

10

10

ns

WE Write Pulse Width

150

150

ns

tAH

Address Hold Time

50

50

ns

tos

Data Set Up Time

50

50

ns

tOH

Data Hold Time

0

0

ns

Min.

Max.

Min.

Max.

Units
ns

tCH

CE Hold Time

0

0

ns

tOES

OE Set Up Time

10

10

ns

tOEH

OE Hold Time

10

10

ns

tOL

Data Latch Time

50

50

tov l4]

Data Valid Time

toe
tWR
twc

ns

1

1

Time to Device Busy

200

200

ns

Write Recovery Time
Before Read Cycle

10

10

p.S

Byte Write Time

10

10

ms

NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not tested.
3.WE is noise protected Less than a 20 ns write pulse will not activate a write cycle.
4. Data must be valid within 1 ms maximum after '''e initiation of a write cycle.

seeQ
MD400015/A

Technology, Incorporated

6-30

p.S

E/M2817A
Write Cycle Timing

OE

CE

WE

1/0 0 -

7

ROY/BUSY
WRITE CYCLE

-------~-

READ CYCLE-I

Ordering Information

D

M

2817A

--L----=-~T----IT

I

PART TYPE

PACKAGE

TEMPERATURE

TYPE

RANGE

D- Ceramic Dip
L- LCC

(Military)

M--55°C to +125°C

2Kx8 EEPROM

E--40°C to +85°C
(Extended)

seeQ

MD400015/A

. 250

Technology, Incorporated

6-31

T

/8

T

ACCESS TIME

250-250 ns
300-300 ns

SCREENING OPTION

18- MIL 883 CLASS 8
Screened

6·32

seeQ

M2864/M2864H
E2864/E2864H
Timere
64K Electrically Erasable ROMs
October 1987

The EEPROM has an internal timer that automatically
times out the write time. The on-chip timer, along
with the input latches, frees the microcomputer
system for other tasks during the write time. The
standard byte write cycle time is 10 ms. For systems
requiring faster byte write, an M2864H is specified
at 2 ms. An automatic byte erase is performed
before a byte operation is started. Once a byte has
been written, the ready/busy pin signals the microprocessor that it is available for another write or a read
cycle. All inputs are TTL for both the byte write and
read mode. Data retention is specified for ten years.

Features
_64KEEPROM
- Military Temperature M2864
- Extended Temperature E2864
• Ready/Busy Pin
• High Endurance Write Cycles
- 10,000 Cycles/Byte Minimum
• On-Chip Timer
- Automatic Byte Erase Before Byte Write
-2 ms Byte Write (M2864H)
• 5 V± 10% Power Supply
• Power Up/Down Protection Circuitry
• 250 ns max. Access Time
Description
SEEQ's M2864 is a 5 V only, 8K x 8 NMOS electrically
erasable programmable read only memory(E EPROM). It
is packaged in a 28 pin package and has a ready/busy
pin. This EEPROM is ideal for applications which require
non-volatility and in-system data modification. The
endurance, the number of times which a byte may be
written, is a minimum of 10 thousand cycles.

These two timer EEPROMs are ideal for systems with
limited board area. For systems where cost is important, SEEQ has a latch only "528" family at 16K and
64K bit densities. All "528" family inputs, except for
write enable, are latched by the falling edge of the
write enable signal.

Pin Configuration
LEADLESS CHIP CARRIER
BOTTOM VIEW

DUAL-IN-LiNE
TOP VIEW

Block Diagram

I~>:

~

o
a:

«

INDEX
CORNER

RDY/BUSv

A••
A.
A.
A.
A.
E2
MEMORY
ARRAY

A.

.

A"
NC

Oe

A,

..

A••

Ce

A••

A.

I/O.

CE

"

1/0'1/0
I/O.
•
1/0.1/0.
1/0.

8

A.

Ao

A.
A"

A.

I/O.
I/O.
I/O.
GND

A.

s

DE

12

u

"

NC

1/0.

21

0 0 0 (Jz 0z 0 6
Cl

Pin Names

~

~

~

~

~

Ao-4

ADDRESSES - COLUMN (LOWER ORDER BITS)

As-12

ADDRESSES -

~

CHIP ENABLE

ROW

OE

OUTPUT ENABLE

WE

WRITE ENABLE

I/O

DATA INPUT (WRITE OR ERASE), DATA OUTPUT
(READ)

ROY/BUSY DEVICE READY/BUSY
N/C

NO CONNECT

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

---J

MD400003/A

6-33

M2864/M2864H
E2864/E2864H
Device Operation

Chip Erase

There are five operational modes (see Table 1) and,
except for the chip erase mode, only TTL inputs are
required. To write into a particular location, a 150 ns
TTL pulse is applied to the write enable (WE) pin of
a selected (CE low) device. This, combined with
output enable (OE) being high, initiates a 10 ms
write cycle. During a byte write cycle, addresses are
latched on either the falling edge of CE or WE,
whichever one occurred last. Data is latched on the
rising edge of CE or WE, whichever one occurred
first. The byte is automatically erased before data is
written. While the write operation is in progress, the
RDY/BUSY output is at a TTL low. An internal timer
times out the required byte write time and at the end
of this time, the device Signals the RDY/BUSY pin to
a TTL high. The RDY/BUSY pin is an open drain
output and a typical3K n pull-up resistor to Vcc is
required. The pull-up resistor value is dependent on
the number of OR-tied RDY/BUSYpins.1f ROY/BUSY is
not used it can be left unconnected.

Certain applications may require aI/ bytes to be
erased simultaneously. This feature is optional and
the timing specifications are available from SEEQ.

Power Up/Down Considerations
The M2864 has internal circuitry to minimize a false
write during system Vcc power up or down. This
circuitry prevents writing under anyone of the
fol/owing conditions.
1. Vcc is less than 3 V. [IJ
2. A negative Write Enable (WE) transition has not
occurred when Vcc is between 3 V and 5 V.
Writing will also be prevented if CE or OE are in TTL
logical states other than that specified for a byte
write in the Mode Selection table.

Absolute Maximum Stress Ratlngs*

Mode Selection (Table 1)
Mode/Pin

CE
(20)

OE
(22)

WE
(27)

I/O
(11-13,15-19)

ROY/
BUSY
(1)*

Read

VIL

VIL

VIH

Dour

HighZ

Standby

VIH

X

X

High Z

HighZ

Byte Write

VIL

VIH

VIL

X
X

VIL
X

X
VIH

Write
Inhibit

DIN
High Z/Dour
High Z/Dour

Temperature
Storage .......................... -65 0 C to + 1500 C
Under Bias ..................... -65 0 C to +1350 C
AI/Inputs or Outputs with
Respect to Ground . ................... +6 V to -0.3 V

VOL
HighZ
HighZ

'COMMENT: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the operational .sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

'Pin 1 has an open drain output and requires an external 3K
resistor to Vee. The resistor value is dependent on the number of
OR-tied ROY/BUSY pins.

Recommended Operating Conditions
E2864
E2864H

M2864
M2864H

I VCC Supply Voltage
r Temperature Range

5 V± 10%

5 V± 10%

(Case) -55°C to +125°C

(Ambient) -40°C to +85°C

Endurance and Data Retention
Symbol

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

Condition
MIL-STD 883 Test
Method 1033

TOR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

NOTE: 1 - Characterized. Not tested.

seeQ

Technology,lncorpomled - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

MD400003/A

6-34

M2864/M2864H
E2864/E2864H
DC Operating Characteristics

(Over the operating Vee and temperature range)
Limits

Symbol

Parameter

lee

Active Vee Current
(Includes Write Operation)

IS8

Standby Vee Current

Min.

III

Input Leakage Current

ILO

Output Leakage Current

50
10
10

VIL

Input Low Voltage

-0.1

Input High Voltage

2.0

VOL

Output Low Voltage

VOH

Output High Voltage

Read Operation

Units

120

VIH

AC Characteristics

Max.

Test Condition

mA

CE = OE = VIL; All I/O Open;
Other Inputs = Vee Max.

mA

CE = VIH, OE = VIL; All I/O Open;
Other Inputs = Vee Max.

!J.A

VIN

!J.A

VOUT

0.8

V

+1
0.4

V

Vee

2.4

V

IOL

V

IOH

= Vee Max.
= Vee Max.

= 2.1 mA
= -400 J.lA

(Over the operating Vee and temperature range)
Limits

Symbol Parameter

E/112864H-250 E/112864H-300
E/M2864-250 E/M2884-300

l1li2864-350

Min.

Min.

Max.

250

Min.

Max.

CE

OE

300
100

100

ns

80

ns

= OE = VIL
= VIL
CE = OE = VIL
CE = VIL
CE = VIL

ns

CE or OE

Chip Enable Access Time

250

300

tAA

Address Access Time

250

tOE

Output Enable Access Time

90

tOF

Output Enable High to Output Not
being Driven

0

tOH

Output Hold from Address Change, Chip
Enable, or Output Enable whichever occurs
first

0

ADDRESSES

60

0
0

0

Read Cycle Timing

tRC

Test Conditions

ns

teE

0

Units

350
350

350

Read Cycle Time

60

Max.

ns

300

tRe

-----

ns

= VIL

~

ADDRESSES VALID

-,

~

.., I

---

OUTPUT ________~----------_+~

-------

~

~

'-

-

f4tOF[21 ..
tOH-

VALID
OUTPUT

---<

r\ \

-; -I'

NOTES:
IAA
1.OE MAY BE DELAYED TOIM-IoE AFTER THE FALLING EDGE OFCEWITHOUT IMPACT ON 1M
5E OR Ce, WHICHEVER OCCURS FIRST.
.
Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--J

2. IDF IS SPECIFIED FROM

SeeQ

MD400003/A

6-35

M2864/M2864H
E2864/E2864H
Capacitance

1

AC Test Conditions

Tl =25°C; f= 1 MHz

Symbol

Parameter

Max.

Conditions

CIN
COUT

I nput Capacitance

6 pF

VIN =0 V

Data (I/O) Cap,

10 pF VJio=OV

Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fal; Times: <20 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 1 V and 2 V
Outputs 0.8 V and 2 V

E.S.D. Characteristics[4]
Symbol

Parameter

Value

VZAP

E.S.D.
Tolerance

>2000 V

Test Conditions
MIL-STD 883
Test Method 3015

AC Characteristics

Write Operation (Over operating temperature and Vcc range)
Limits

Symbol

Parameter

twc

Write Cycle Time/Byte
Standard Family Only

E/M2864H-250
E/M2864-250

E/M2864H-300
E/M2864-300

Min.

Min.

Max.

Min.

10

10

.. H" Family Only

Max.

E/M2864H-350
E/M2864-350

2

2

Max.

Units

10

ms

-

ms
ns

tAS

Address to WE Set Up Time

10

10

10

tcs
twp(2)

CE to Write Set Up Time

0

0

0

ns

WE Write Pulse Width

150

150

150

ns

tAH

Address Hold Time

50

50

70

ns

tos

Data Set Up Time

50

50

50

ns

tOH

Data Hold Time

20

20

20

ns

tCH

CE Hold Time

0

0

0

ns

tOES

OE Set Up Time

10

10

10

ns

tOEH

OE Hold Time

10

10

10

ns

tOl

Data Latch Time

50

toV(3)

Data Valid Time

toe

Time to Device Busy

tWR

Write Recovery Time
Before Read Cycle

50

ns

50

1

1

1

200

200

200

ns

10

10

p.s

10

p's

Notes:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. WE is noise protected. less than a 20 ns write pulse will not activate a write cycle.
3. Data must be valid within 1 pS maximum after the initiation of a write cycle.
4. Characterized Not tested.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD400003/A

6-36

M2864/M2864H
E2864/E2864H

Write Cycle Timing

ROY/BUSY
WRITE CYCLE

-------~-

READ CYCLE-I

Ordering Information

o
o

E
M

2864
2864

H· 250 /B
H· 250 /B

11~____
T

PACKAGE
TYPE
D=CERAMIC DIP
L-LCC

L-~;:;~ele(~

TEMPERATURE
RANGE

PART TYPE

EEPROM BYTE
WRITE TIME

ACCESS TIME

SCREENING OPTION

M - -55°C to +125°C
(Military)
E - -40°C to +SsoC
(Extended)

SKxS EEPROM

(Blank) - Standard Write Time
H - Fast Write Time

250-250 ns
300-300 ns
350-350 ns

/B- MILSS3 CLASS B
SCREENED

Technology, Incorporated

MD400003/A

------------------------------..1
6-37

6-38

seeQ

E/M28C64
Timer £2
64K Electrically Erasable PROM

PRELIMINARY DATA SHEET

October, 1988

Features

Description

• Military and Extended Temperature Range
• -55°C to +125°C Operation (Military)
• -40°C to +B5°C Operation (Extended)
• CMOS Technology
• Low Power
• 60 mA Active
• 250 #LA Standby
• Page Write Mode
• 64 Byte Page
• 160 us Average Byte Write Time
• Byte Write Mode
• Write Cycle Completion Indication
• DATA Polling
• On Chip Timer
• Automatic Erase Before Write
• High Endurance
• 10,000 Cycles/Byte Minimum
• 10 Year Data Retention
• Power Up/Down Protection Circuitry
• 200 ns Maximum Access Time
• JEDEC Approved Byte Wide Pinout

SEEQ's EIM28C64 is a CMOS 5V only, 8K x 8 Electrically Erasable Programmable Read Only Memory
(EEPROM). It is manufactured using SEEQ's advanced 1.25 micron CMOS Process and is available in
both a 28 pin Cerdip package as well as a Leadless
Chip Carrier (LCC). The EIM28C64 is ideal for applications which require low power consumption, nonvolatility and in. system reprogrammability. The
endurance, the number of times a byte can be written,
is specified at 10,000 cycles per byte and is typically
1,000,000 cycles per byte. The extraordinary high
endurance was accomplished using SEEQ's proprietary oxynitride EEPROM process and its innovative
Q CelfM deSign. System reliability, in all applications,
is higher because of the low failure rate of the Q Cell.
The EIM28C64 has an internal timer which
automatically times out the write time. the onchip timer, along with input latches free the micro

Pin Configuration
DUAL-IN-LiNE
TOP VIEW

LEADLESS CHIP CARRIER
BOTTOM VIEW

E2
MEMORY
ARRAY

A'2

Ao-As

2

A7

3

A6
As

4

A4
A3
A2
A,
Ao
1/00

26
25
24
23
22
21

NC
As
A9
An

OE
A'0

9
19
10
18
11
1/0,
12
17
16
1/02
13
GND"'\oIi'4_ _
15

r

CE
1/07
1/06

1/05
1/0 4
1/03

Pin Names

"°0.1

Ao-.

ADDRESSES-COLUMN

Ao-A'2

ADDRESSES-ROW

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/00-7

DATA INPUT (WR ITE)I DATA
OUTPUT (READ)

NC

NO CONNECTION

Q Cell is a trademark of SEEQ Technology, Inc.

SeeQ Technology, Incorporated --------------------------~
MD400001/C

6-39

E/M28C64
PRELIMINARY DATA SHEET

Writes

processor for other tasks while the part is busy
writing. The E/M28C64's write cycle time is 10 ms.
An automatic erase is performed before a write. The
DA TA polling feature of the E/M28C64 can be
used to determine the end of a write cycle. Once
the write cycle has been completed, data can be
read in a maximum of 200 ns. Data retention is
specified for 10 years.

To write into a particular location, the address must
be valid and a TTL low applied to the Write Enable
(WE) pin of a selected (CE low) device. This combined with Output Enable (0 E) being high,
initiates a write cycle. During write cycle, all inputs
except data are latched on the falling edge of WE
orC£, whichever occurred last. Write enable needs
to be at a TTL low only for the specified twp time.
Data is latched on the riSing edge of WE or CE,
whichever occurred first. An automatic erase is
perfomed before data is written.

Device Operation
Operational Modes
There are five operational modes (see Table 1)
and, except for the chip erase mode, only TTL
inputs are required. A Write can only be initiated
under the conditions shown. Any other conditions
for CE, OE, and WE will inhibit writing and the I/O
lines will either be in a high impedance state or
have data, depending on the state of aforementioned three input lines.

Mode Selection
MODE

CE

OE

WE

I/O

Read

VIL

VIL

VIH

Dour

Standby

VIH

X

X

HIZ

Write

VIL

VIH

VIL

DIN

Write
Inhibit

X
X

VIL

X

X

VIH

HI ZlDour
HI Z/Dour

VIL

VH

VIL

X

Chip Erase

Write Cycle Control Pins
For system design simplification, the E/M28C64 is
designed such that either the CE or WE pin can be
used to initiate a write cycle. The device uses the
latest high-to-Iow transition of either CE or WE
signal to latch addresses and the earliest low-tohigh transition to latch the data. Address and OE
setup and hold are with respect to the later of CE
or WE; data setup and hold is with respect to the
earlier of WE or CEo

To simplify the following discussion, the WE pin is
used as the write cycle control pin throughout the
rest of this data sheet. Timing diagrams of both
write cycles are included in the AC Characteristics.

X: Any TIL level
VH: High Vollage

Reads
A read is accomplished by presenting the address
of the desired byte to the address inputs. Once the
address is stable, CE is brou9.!!.! to a TTL low in
order to enable the chip. The WE pin must be at a
TTL high during the entire read cycle. The output
drivers are made active by bringing Output Enable
(OE) to a TTL low. During read, the address, CE,
OE, and I/O latches are transparent.

seeQ T e c h n o ' o g y , ' n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - -....
MD4000011C

6-40

E/M28C64
PRELIMINARY DATA SHEET

Write Mode

DATA Polling

One to 64 bytes of data can be randomly loaded
into the page. The part latches row addresses,
A6-A 12, during the first byte write. These addresses
are latched on the falling edge of the WE signal
and are ignored after that until the end of the write
cycle. This will eliminate any false write into another
page if different row addresses are applied and
the page boundary is crossed.

The E/M28C64 has a maximum write cycle time of
10 ms. Typically though, a write will be completed
in less than the specified maximum cycle time.
DA TA polling is a method of minimizing write times
by determining the actual endpoint of a write cycle.
lf a read is performed to any address while the
E/M28C64 is still writing, the device will present
the ones-complement of the last byte written.
When the ElM28C64 has completed its write
cycle, a read from the last address written will
result in valid data. Thus, software can simply read
from the part until the last data byte written is read
correctly.

The column addresses, AO-A5, which are used to
select different locations of the page, are latched
every time a new write initiated. These addresses
and the OE state (high) are latched on the falling
edge of WE signal. For proper write initiation and
latching, the WE pin has to stay low for a minimum
of twp ns. Data is latched on the rising edge of WE,
allowing easy microprocessor interface.

A DATA polling read can occur immediately aftera
byte is loaded into a page, prior to the initiation of
the internal write cycle. DATA polling attempted
during the middle of a page load cycle will present
a ones-complement of the most recent data byte
loaded into the page. Timing for a DATA polling
read is the same as a normal read.

Upon a low to high WE transition, the ElM28C64
latches data and starts the internal page load timer.
The timer is reset on the falling edge of the WE
signal if another write is initiated before the timer
has timed out. The timer stays reset while the WE
pin is kept low. If no additional write cycles have
been initiated within tBLC after the last WE low to
high transition, the part terminates the page load
cycle and starts the internal write. During this time
which takes a maximum of 10 ms, the device
ignores any additional write attempts. The part
can be read to determine the end of write cycle
(DATA polling).

Chip Erase
Certain applications may require all bytes to be
erased simultaneously. This feature, which
requires high voltage, is optional and timing
specifications are available from SEEQ.

Power Up/Down Considerations
There is internal circuitry to minimize a false write
during power up or power down. This circuitry prevents writing under anyone of the following
conditions:

Extended Page Load
In order to take advantage of the page mode's faster average byte write time, data must be loaded at
the page load cycle time (tBLC). Since some applications may not be able to sustain transfers at this
minimum rate, the ElM28C64 permits an extended
page load cycle. To do this, the write cycle must be
"stretched" by maintaining WE low, assuming a
write enable-controlled cycle, and leaving all other
control inputs (CE, OE) in the proper page load
cycle state. Since the page load timer is reset on
the falling edge of WE, keeping this si~/low will
not start the page load timer. When WE returns
high, the input data is latched and the page load
cycle timer begins. In CE controlled write the same
is true, with CE holding the timer reset instead
of WE.

1. Vcc is less than VwN
2. A high to low Write Enable (WE) transition has
not occurred when the Vce supply is between
VwN and Vcc with CE low and OE high.
Writing will also be inhibited when WE, CE, or OE
are in TTL logical states other than that specified
for a write in the Mode Selection table.

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

---1

MD400001/C

6-41

E/M28C64
PRELIMINARY DATA SHEET

Abso/ute Maximum Stress Range*
Temperature
Storage.................... -65°C to +150°C
Under Bias ................ -65°C to +135°C

*COMMENT: Stresses beyond those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions beyond those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

D.C. Voltage applied to all Inputs or Outputs
with respect to ground . ..... +6.0 Vto -0.5 V
Undershoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground . ............. -1.0 V
Overshoot pulse of less than 10 ns (measured at
50% pOint) applied to all inputs or outputs
with respect to ground . ............ +7.0 V

Recommended Operating Conditions
M28C64

E28C64
(Ambient) -40°C to +85~C-

(Case) -55°C to +125°C

Temperature Range
Vcc Power Supply

5 V± 10%

5 V± 10%

Endurance and Data Retention
Symbol

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TOR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

DC Characteristics

Condition

(Over operating temperature and Vee range, unless otherwise specified)
Limits

Symbol

Parameter

Icc

Active Vcc Current

IS61
IS62

Min.

Max.

Units

60

mA

CE = OE = Vll; All I/O Open;
Other Inputs = Vee Max.;
Max read or write cycle time

Standby Vce Current
(TIL Inputs)

2

mA

CE = VIH, OE = Vll; All I/O Open;
Other Inputs = ANY TIL LEVEL

Standby Vce Current
(CMOS Inputs)

250

pA

CE = Vce-0.3
Other inputs = Vil to VIH
All I/O Open

Test Condition

hl[21

Input Leakage Current

1

pA

VIN = Vcc Max.

10l

Output Leakage Current

10

pA

VOUT= Vcc Max.

Vil

Input Low Voltage

-0.3

0.8

V

VIH

Input High Voltage

2.0

6

V

VOL

Output Low Voltage

0.45

V

10l = 2.1 mA

VOH

Output High Voltage

2.4

V

10H= -400p..A

VWI£1]

Write Inhibit Voltage

3.8

V

Notes:

1. Characterized. Not tested.
2. Inputs only. Does not include 1/0.

---- seeQ

Techno/ogy,'ncorporated----------------------------'
MD4000011C
6-42

E/M28C64
PRELIMINARY DATA SHEET

Aceha racteristics Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
ElM28C64-200
Symbol

Parameter

twc

Write Cycle Time

tAS

Address Set-up Time

tAH

Address Hold Time (see note 1)

les

Min.

Max.

ElM28C64-250
Min.

Max.

10

ElM28C64-300
Min.

10

Max.

ElM28C64-350
Min.

10

Max.

Units

10

ms

10

10

10

10

ns

150

150

150

150

ns

Write Set-up Time

0

0

0

0

ns

leH

Write Hold Time

0

0

0

0

ns

lew

CE Pulse Width (note 2)

150

150

150

150

ns

tOES

OE High Set-up Time

10

10

10

10

ns

tOEH

OE High Hold Time

10

10

10

10

ns

twp

WE Pulse Width (note 2)

150

150

150

150

ns

tos

Data Set-up Time

50

50

50

50

ns

tOH

Data Hold Time

0

0

0

0

tBlC

Byte Load Timer Cycle
(Page Mode Only) (see note 3)

tlP

Last Byte Loaded
to DATA Polling

0.2

200

0.2

200

200
200

0.2

200
200

0.2

ns
200

us

200

ns

Write Timing
WE CONTROLLED WRITE CYCLE

CE CONTROLLED WRITE CYCLE

Notes:
1. Address hold time is with respect to the falling edge of the control Signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. tBlC min. is the minimum time before the next byte can be loaded. tBlC max. is the minimum time the byte load timer waits before
initiating internal write cycle.

seeQ

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~-----I

MD4000011C

6-43

E/M28C64
PRELIMINARY DATA SHEET

Capacitance l11

AC Test Conditions
Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: <10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V

TA = 25°C, f= 1 MHz

Symbol

Parameter

CIN

Input Capacitance

6 pF

COUT

Data (I/O) Capacitance

12 pF VIIO= OV

Max. Conditions
VIN= OV

E.S.D. Characteristics
Symbol

Parameter

VZApl2J

E.S.D.
Tolerance

Value
>2000 V

Test Conditions
MIL-STD 883
Test Method 3015

AC Characteristics Read Operation (Over operating temperature and Vcc range, unless otherwise specified)
ElM28C64-200

ElM28C64-250

Limits
ElM28C64-300

ElM28C64-350

Parameter

Min.

Min.

Min.

Min.

tRC

Read Cycle Time

200

teE

Chip Enable Access Time

200

250

tAA

Address Access Time

200

tOE

Output Enable Access Time

80

tDF

Output or Chip Enable High to
output not being driven

0

tOH

Output Hold from Address Change,
Chip Enable, or Output Enable,
whichever occurs first

0

Symbol

.
CE

Max.

60

Units
ns

CE=OE=VIL

300

350

ns

OE=VIL

250

300

350

ns

CE=OE=VIL

90

90

90

ns

CE=VIL

80

ns

CE=VIL

ns

CE=OE=VIL

300

0

Test
Conditions

Max.

250

Max.

60

0

350

80

0

0

0

0

Read/Data Polling Cycle Time

.

IRC

~~

ADDRESSES

Max.

~I..

ADDRESS AN

-

NEXT ADDRESS
lAA

-,~~

~

l- ICE

OE

~ Ie

...,I;z~
__ IOF __

_

IOE_
IoH-r-l

_~IOH

DATA

HIGHZ

.

~,

lAA

.

DATA VALID

:x
I

)

DATA VALID

~ f-

Notes:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characlerized. Not tested.

- seeQ Techno'ogy,'ncorporated-------------------------------'
MD4000011C

6-44

E/M28C64
PRELIMINARY DATA SHEET

Page Write Timing
DATA POLLING

PAGE LOAD

'1---\

----....,--..,....---..'===---:::::-:7--,----.
.
.,-.-...;..
. . . .\

~y F"'-=-""--Y1-

WE---_iJ

DATA

r~

'=:~?

~

HIGHZ

Ordering Information

rl

D M 28C64 -250/8
----;:==T~--.lT - - , - 1:2=;----....."

PACKAGE
TYPE
D=CERAMIC DIP
L= LCC

TEMPE~ATURE
RANGE

DEVICE
8K x 8 E2 PROM

M- -55· - +125·C
(Military)
E- -40· - +85·C

ACCESS TIME
200=200 ns
250=250 ns
300=300 ns
350=350 ns

MIL 883
CLASS B
SCREENED

(Extended)

seeQ

Technology, Incorporated

MD400001/C

-----------------------------1
6-45

6-46

seeQ

E/M28C65

Timer ~
64K Electrically Erasable PROM

PRELIMINARY DATA SHEET

October. 1988

Features

Description

• Military and Extended Temperature Range
• -55°C to +125°C Operation (Military)
• -40°C to +85°C Operation (Extended)
• CMOS Technology
• Low Power
• 60 mA Active
• 250 pA Standby
• Page Write Mode
• 64 Byte Page
• 160 us A verage Byte Write Time
• Byte Write Mode
• Write Cycle Completion Indication
• DATA POlling
• ROY/BUSY Pin

SEEQ's EIM28C65 is a CMOS 5V only, 8K x 8 Electrically Erasable Programmable Read Only Memory
(EEPROM). It is manufactured using SEEQ's advanced 1.25 micron CMOS Process and is available in
both a 28 pin Cerdip package as well as a Plastic
Leadless Chip Carrier (LCC). The EIM28C65 is ideal
for applications which require low power consumption, non-volatility and in system reprogrammability.
The endurance, the number of times a byte can be
written, is specified at 10,000 cycles per byte and is
typically 1,000,000 cycles per byte. The extraordinary
high endurance was accomplished using SEEQ's
proprietary oxynitride EEPROM process and its
innovative Q CelfM design. System reliability, in all
applications, is higher because of the low failure rate
of the Q Cel/.

• On Chip Timer
• Automatic Erase Before Write
• High Endurance
• 10,000 Cycles/Byte Minimum
• 10 Year Data Retention
• Power Up/Down Protection Circuitry
• 200 ns Maximum Access Time
• JEDEC Approved Byte Wide Pinout

The EIM28C65 has an internal timer which automatically times out the write time. The on-Chip timer,
along with input latches free the microprocessor

Pin Configuration
LEADLESS CHIP CARRIER
BOTTOM VIEW

DUAL-IN-L1NE
TOP VIEW

Vcc

ROY/BUSY
A12
A7

WE
3

NC

As

As
A5

1.4
Aa

6

A10

Ce

A1

Ao

10

1/00
1/01
1/02

13

GNO __
14_ _-r
1ft

....

CO')

0

Q

N

1/07
I/OS
1/05
1/04
1/03

....

gggz~gg

Pin Names
AO-5

ADDRESSES - COLUMN

AS-12

ADDRESSES ROW

CE

CHIP ENABLE
OUTPUT ENABLE

1/°0-7

WRITE ENABLE

1/0 0-7

Q Cell is a trademark of SEEQ Technology, Inc.

DATA INPUT (WRITE)
DATA OUTPUT (READ)

RDY/BUSv DEVICE READY/BUSY
NC

NO CONNECTION

- SeeQ Technology, Incorporated---------.....!:=========~====;!....-----I
MD400026/B

6-47

E/M28C65
PRELIMINARY DATA SHEET

Writes

for other tasks while the part is busy writing. The
E/M28G65's write cycle time is 10 ms. An automatic
erase is performed before a write. The DATA polling
feature of the E/M28G65 can be used to determine
the end of a write cycle. Once the write has been
completed, data can be read in a maximum of 200
ns. Data retention is specified for 10 years.

To write into a particular location, th.e address must
be valid and a TTL low applied to the Write Enable
(WE) pin of a selected (eE low) device. This combined with Output Enable (OE) being high,
initiates a write cycle. During write cycle, all inputs
except data are latched on the falling edge of WE
orCE, whicheveroccurred last. Write enable needs
to be at a TTL low only for the specified twp time.
Data is latched on the rising edge of WE or CE,
whichever occurred first. An automatic erase is
perfomed before data is written.

Device Operation
Operational Modes
There are five operational modes (see Table 1)
and, except for the chip erase mode, only TTL
inputs are required. A Write can only be initiated
under the conditions shown. Any other conditions
for GE, OE, and WE will inhibit writing and the I/O
lines will either be in a high impedance state or
have data, depending on the state of aforementioned three input lines.

Mode Selection
MODE

CE

OE

WE

I/O

RDY/BUSyI 11

Read

VIL

VIL

VIH

Dour

HIZ
HIZ

Standby

VIH

X

X

HIZ

Write

VIL

VIH

VIL

DIN

VOL

Write
Inhibit

X
X

VIL
X

X
VIH

HI Z/Dour
HI Z/Dou r

HIZ
HIZ

VIL

VH

VIL

X

HIZ

Chip Erase

Write Cycle Control Pins
For system design Simplification, the E/M28C65 is
designed such that either the CE or WE pin can be
used to initiate a write cycle. The device~ses the
latest high-to-Iow transition of either CE or WE
Signal to latch addresses and the earliest low-tohigh transition to latch the data. Address and OE
setup and hold are with respect to the later of CE
or WE; data setup and hold is with respect to the
earlier of WE or CE.
To simplify the following discussion, the WE pin is
used as the write cycle control pin throughout the
rest of this data sheet. Timing diagrams of both
write cycles are included in the AG Characteristics.

X: Any TIL level
VH: High Voltage

Reads
A read is accomplished by presenting the address
of the desired byte to the address inputs. Once the
address is stable, CE is brou9.!!! to a TTL low in
order to enable the chip. The WE pin must be at a
TTL high during the entire read cycle. The output
drivers are made active by bringing Output Enable
(OE) to a TTL low. During read, the address, GE,
OE, and I/O latches are transparent.

NOTES:
1. ROY/BUSY Pin 1 (Pin 2 on LeG) has an open drain output and requires an external3K resistor to Vee.The value of the resistor is
dependent on the number of OR-tied ROY/BDSY pins.

seeQ Technology, Incorporated
MD400026/B

6-48

E/M28C65
PRELIMINARY DATA SHEET

Write Mode
One to 64 bytes of data can be randomly loaded
into the page. The part latches row addresses,
A6-A 12, during the first byte write. These addresses
are latched on the falling edge of the WE signal
and are ignored after that until the end of the write
cycle. This will eliminate any false write into another
page if different row addresses are applied and
the page boundary is crossed.
The column addresses, AO-A5, which are used to
select different locations of the page, are latched
every time a new write initiated. These addresses
and the OE state (high) are latched on the falling
edge of WE signal. For proper write initiation and
latching, the WE pin has to stay low for a minimum
of twp ns. Data is latched on the rising edge of WE,
allowing easy microprocessor interface.
Upon a low to high WE transition, the E/M28C65
latches data and starts the internal page load timer.
The timer is reset on the falling edge of the WE
signal if another write is initiated before the timer
has timed out. The timer stays reset while the WE
pin is kept low. If no additional write cycles have
been initiated within tSLC after the last WE low to
high transition, the part terminates the page load
cycle and starts the internal write. During this time
which takes a maximum of 10 ms, the device
ignores any additional write attempts. The part
can be read to determine the end of write cycle
(DATA polling).

Extended Page Load
In order to take advantage of the page mode's faster average byte write time, data must be loaded at
the page load cycle time (tSLC). Since some applications may not be able to sustain transfers at this
minimum rate, the E/M28C65 'Permits an extended
page load cycle. To do this, the write cycle must be
"stretched" by maintaining WE low, assuming a
write enable-controlled cycle, and leaving all other
control inputs (CE, OE) in the proper page load
cycle state. Since the page load timer is reset on
the falling edge of WE, keeping this signal low will
not start the page load timer. When WE returns
high, the input data is latched and the page load
cycle timer begins. In CE controlled write the same
is true, with CE holding the timer reset instead
of WE.

DATA Polling
The E/M28C65 has a maximum write cycle time of
10 ms. Typically though, a write will be completed

in less than the specified maximum cycle time.
OA TA polling is a method of minimizing write times
by determining the actual endpoint of a write cycle.
If a read is performed to any address while the
E/M28C65 is still writing, the device will present
the ones-complement of the last byte written. When
the E/M28C65 has completed its write cycle, a read
from the last address written will result in valid
data. Thus, software can simply read from the part
until the last data byte written is read correctly.
A OA TA polling read can occur immediately after a
byte is loaded into a page, prior to the initiation of
the internal write cycle. DATA polling attempted
during the middle of a page load cycle will present
a ones-complement of the most recent data byte
loaded into the page. Timing for a DATA polling
read is the same as a normal read.

READY/BUSY Pin
E/M28C65 provides write cycle status on this pin.
ROY/BUSY output goes to a TTL low immediately
after the falling edge of WE. ROY/BUSY will
remain low during the byte load or page load cycle
and continues to remain at a TTL low while the
write cycle is in progress. An internal timer times
out the required write cycle time and at the end of
this time, the device signals ROY/BUSY pin to a
TTL high. This pin can be polled for write cycle
status or used to initate a rising edge triggered
interrupt indicating write cycle completion. The
ROY/BUSYpin is an open drain output and a typical
3 K pull-up resistor to Vcc is required. The pull-up
value is dependent on the number of OR-tied
ROY/BUSY pins. If ROY/BUSY is not used, it can
be left unconnected.

Chip Erase
Certain applications may require all bytes to be
erased simultaneously. This feature, which
requires high voltage, is optional and timing
specifications are available from SEEQ.

Power Up/Down Considerations
There is internal circuitry to minimize a false write
during power up or power down. This circuitry prevents writing under anyone of the following
conditions:
1. Vcc is less than VwN
_
2. A high to low Write Enable (WE) transition has

not occurred when the Vee supply is between
VwN and Vee with CE low and OE high.
Writing will also be inhibited when WE, CE, or OE
are in TTL logical states other than that specified
for a write in the Mode Selection table.

SeeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD400026/B

6-49

E/M28C65
PRELIMINARY DATA SHEET

Absolute Maximum Stress Range*
Temperature
Storage . ................... -65°C to +150°C
Under Bias ................ -65°C to +135°C

*COMMENT: Stresses beyond those listed under "Abso/ute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions beyond those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

D. C. Voltage applied to aI/Inputs or Outputs
with respect to ground. . . . . . + 6. 0 V to -0.5 V
Undershoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground . ............. -1.0 V
Overshoot pulse of less than 10 ns (measured at
50% point) applied to aI/ inputs or outputs
with respect to ground. . . . . . . . . . . .. + 7.0 V

Recommended Operating Conditions
M28C64

I
I

Temperature Range

E28C64
(Ambient) -40°C to +85°C

(Case) -55°C to +125°C

Vee Power Supply

5 V± 10%

5 V± 10%

Endurance and Data Retention
Symbol

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TOR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

DC Characteristics

Condition

(Over operating temperature and Vcc range, unless otherwise specified)
Limits

Symbol

Parameter

Icc

Active Vee Current

Max.

Units

60

mA

CE = OE = VIL; All I/O Open;
Other Inputs = Vee Max.;
Max read or write cycle time

IS81

Standby Vee Current
(TIL Inputs)

2

mA

CE = VIH, OE = VIL; All I/O Open;
Other Inputs = ANY TIL LEVEL

IS82

Standby Vec Current
(CMOS Inputs)

250

J.l.A

CE = Vee -0.3
Other inputs = VIL to VIH
All I/O Open

Min.

Test Condition

hL(2]

Input Leakage Current

10L

Output Leakage Current

VIL

Input Low Voltage

-0.3

VIH

Input High Voltage

2.0

VOL

Output Low Voltage

V

IOL= 2.1 mA

VOH

Output High Voltage

2.4

V

10H= -400J.l.A

VWI[1j

Write Inhibit Voltage

3.8

V

1

J.LA

VIN = Vee Max.

10

J.l.A

VOUT = Vce Max.

0.8

V

6

V

0.45

Notes:
1. Characterized. Not tested.
2. Inputs only. Does not include I/O.

seeQ

Techno/ogy,'ncorporated-------------------------------....

MD400026/B

6-50

E/M28C65
PRELIMINARY DATA SHEET

AC Test Conditions

Capacitance l11

Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: <10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs. 0.8 V and 2 V
Outputs 0.8 V and 2 V

TA = 25 C, f = 1 MHz

Symbol

Parameter

CIN

Input Capacitance

6 pF VIN = OV

COUT

Data (1/0) Capacitance

12 pF VI/O= OV

Max. Conditions

E.S.D. Characteristics
Symbol

Parameter

VzApl2)

E.S.D.
Tolerance

Value

Test Conditions

>2000 V

MIL-STD 883
Test Method 3015

AC Characteristics Read Operation (Over operating temperature and Vcc range, unless otherwise specified)
ElM28C65-200

ElM28C65-250

Limits
ElM28C65-300

ElM28C65-350

Parameter

Min.

Min.

Min.

Min.

tRC

Read Cycle Time

200

teE

Chip Enable Access Time

200

250

300

350

ns

OE=VIL

tAA

Address Access Time

200

250

300

350

ns

CE=OE=VIL

90

ns

CE=VIL

80

ns

CE=VIL

ns

CE=OE=VIL

Symbol

toE

Output Enable Access Time

tOF

Output or Chip Enable High to
output not being driven

0

tOH

Output Hold from Address Change,
Chip Enable, or Output Enable,
whichever occurs first

0

.

Max.

250

Max.

300

80

350

90

60

0

90

60

0

0

80

0

0

0

~

Test
Conditions

ns

CE=OE=VIL

-

NEXT ADDRESS
tAA-

~~<-

l_tcE-IoE-

;z<-

~~

toH -I

__ tDF ....

_~IoH

HIGHZ

.

Units

.

IRe
ADDRESS AN

X-

DATA

Max.

Read/Data Polling Cycle Time

~

ADD RESSES

Max.

."'tAA

.

DATA VAUD

:J(

)!

DATAVAUD

H t-

Notes:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not tested

seeQ Technology.lncorporated--------------------------------'
MD400026/B

6-51

E/M28C65
PRELIMINARY DATA SHEET

AC Characteristics
Write Operation (Over the operating Vccand temperature range)
Limits
ElM28C65-200
Min.

Max.

ElM28C65-250
Min.

Max.

ElM28C65-300
Min.

Max.

ElM28C65-350
Min.

Max.

Units

10

ms

Symbol

Parameter

twc

Write Cycle Time

tAS

Address Set-up Time

10

10

10

10

tAH

Address Hold Time (see note 1)

150

150

150

150

ns

tes

Write Set-up Time

0

0

0

0

ns

tcH

Write Hold Time

tew

CE Pulse Width (note 2)

10

10

10

ns

0

0

0

0

ns

150

150

150

150

ns

toES

OE High Set-up Time

10

10

10

10

ns

tOEH

OE High Hold Time

10

10

10

10

ns

twp

WE Pulse Width (note 2)

150

150

150

150

ns

tos

Data Set-up Time

50

50

50

50

ns

tOH

Data Hold Time

0

0

0

0

tBle

Byte Load Timer Cycle
(Page Mode Only) (note 3)

tlP

Last Byte Loaded
to DATA Polling

200

200

tOB

Time to Device Busy

100

100

0.2

200

0.2

200

0.2

200

0.2

ns
200

us

200

200

ns

100

100

ns

Write Timing
WE CONTROLLED WRITE CYCLE

CE CONTROLLED WRITE CYCLE

DATA
DATA
- - BYTE WRITE -~I- POLLING -~ POlLlNGr-...:.I_ __

CE

WE

WE

CE

HIGHZ

DATA

RDY/BUSY

DATA

tDB
RDY/BUSY

tDB-l

NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CE.
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. tSle min. is the minimum time before the next byte can be loaded. tSlC max. is the minimum time the byte load timer waits before
initiating the internal write cycle.

seeQ T e c h n o / o g y . l n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - - 1
MD4000261B

6-52

E/M28C65
PRELIMINARY DATA SHEET

Page Write Timing
I

-f.

\

.-----~t=7--r---~,.---:::::J

--toES....

-

r-

DATA

-------------·~I.. POLLING

PAGE LOAD

OE

\

-r-

DATA
POLLING

-!

r~

toEH

ADDRES...;;.SE;;.;;S'--".._+'""""f"'-i_.J'<.....::VA=U:=D..J'......._ _ _ _

:~:::::::~......._ _"'DON=_.:'T_=CAR=E'___...-lf~

WE-----.LI

HIGHZ
DATA - - - - + - < 1

ROY/BUSY

__________

-----~=L

Ordering Information

M 28C65

D

T

I

I

PACKAGE
TYPE

TEMPERATURE
RANGE

D=CERAMIC DIP
L=LCC

seeQ

T

I
DEVICE

8K x8 E' PROM

M- -55' - +125°C
(Military)
E- -40° - +85°C
(Extended)

-250/8
-':L
-----,

I

ACCESS TIME
200=200
250=250
300=300
350=350

ns
ns
ns
ns

MIL883
CLASS B
SCREENED

Technology. Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _--1

MD4000261B

6-53

6-54

seeQ

E/M28C256
Timer E!
256K Electrically Erasable PROM

PRELIMINARY DATA SHEET

November, 1988

Features

Description

• Military and Extended Temperature Range
• -55°C to +125°C Operation (Military)
• -40°C to +85°C Operation (Extended)

SEEQ's 28C256 is a CMOS 5V only, 32K x 8 Electrically Erasable Programmable Read Only Memory
(EEPROM). It is manufactured using SEEQ's advanced 1.25 micron CMOS Process and is available in
both a 28 pin Cerdip package as well as a Leadless
Chip Carrier (LCC). The 28C256 is ideal for applications which require low power consumption, nonvolatility and in system reprogrammability. The
endurance, the number of times a byte can be written,
is specified at 10,000 cycles per byte and is typically
1,000,000 cycles per byte. The extraordinary high
endurance was accomplished using SEEQ's proprietary oxynitride EEPROM process and its innovative
Q Ce/fM design. System reliability, in all applications,
is higher because of the low failure rate of the Q Cell.

• CMOS Technology
• Low Power
• 60 mA Active
• 250 pA Standby
• Page Write Mode
• 64 Byte Page
• 160 us A verage Byte Write Time
• Byte Write Mode
• Write Cycle Completion Indication
• DATA Polling
• On Chip Timer
• Automatic Erase Before Write
• High Endurance
• 10,000 Cycles/Byte
• 10 Year Data Retention
• Power Up/Down Protection Circuitry
• 200 ns Maximum Access Time
• JEDEC Approved Byte Wide Pinout

The 28C256 has an internal timer which
automatically times out the write time. The onchip timer, along with input latches free the micro-

Pin Configuration
LEAD LESS CHIP CARRIER
BOTTOM VIEW

£ I~

E2
MEMORY
ARRAY

~ ~

DUAL-IN-LiNE
TOPVIEW

INDEX

J :t < CORNER

Au

WE

26
25
24
23
22

A13
As
A9
A11

As
A4
A3
A2
A1

Ao

Q Cell is

a trademark of SEEQ Technology, Inc.

-- SeeQ Technology, Incorporated
MD4000211D

6-55

ADDRESSES - COLUMN

A6-14

ADDRESSES - ROW

4

9

1/00

10
11

1/01
1/02
GND

12
13
14

Pin Names
Ao-s

Vee

27

A7
A6

Ao-As

1/00·7

~

A12

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

I/O

DATA INPUT (WRITE)/DATA
OUTPUT (READ)

21
20
19
18
17

16
15

Of
A10

CE
1/07
1/06
1/05
1/04
1103

E/M28C256
PRELIMINARY DATA SHEET

processor for other tasks while the part is busy
writing. The 28C256's write cycle time is 10 ms
maximum. An automatic erase is performed before
a write. The DA TA polling feature of the 28C256
can be used to determine the end of a write cycle.
Once the write cycle has been completed, data
can be read in a maximum of 200 ns. Data retention is greater than 10 years.

Device Operation
Operational Modes
There are five operational modes (see Table 1)
and, except for the chip erase mode, only TTL
inputs are required. A Write can only be initiated
under the conditions shown. Any other conditions
for CE, DE, and WE will inhibit writing and the I/O
lines will either be in a high impedance state or
have data, depending on the state of the aforementioned three input lines.

Table 1
Mode Selection
MODE

CE

OE

WE

I/O

Read

V,L

V,L

V,H

DouT
HIZ

Standby

V,H

X

X

Write

V,L

V,H

V,L

DIN

Write
Inhibit

X
X

X
V,L

V,H
X

HI Z/DouT
HI Z/DouT

Chip Erase

V,L

VH

V,L

X

Writes
To write into a particular location, the address must
be valid and a TTL low applied to the Write Enable
(WE) pin of a selected (CE low) device. This combined with Output Enable (DE) being high
initiates a write cycle. During a byte write cycle, all
inputs except data are latched on the falling edge
of WE or CE, whichever occurred last. Write enable
needs to be at a TTL low only for the specified twp
time. Data is latched on the rising edge of WE or
CE, whichever occurred first. An automatic erase
is performed before data is written.
The 28C256 can write both bytes and blocks of up
to 64 bytes. The write mode is discussed below.

Write Cycle Control Pins
For system design Simplification, the 28C256 is
designed such that either the CE or WE pin can
be used to initiate a write cycle. The device uses
the latest high-to-Iow transition of either CE or WE
signal to latch addresses and the earliest low-tohigh transition to latch the data. Address and DE
set up and hold are with respect to the later of CE
or WE; data set up and hold is with respect to the
earlier of WE or CE.
To simplify the following discussion, the WE pin is
used as the write cycle control pin throughout the
rest of this data sheet. Timing diagrams of both
write cycles are included in the AC Characteristics.

X: any TIL level
VH: High Voltage

Reads
A read is typically accomplished by presenting the
address of the desired byte to the address
inputs. Once the address is stable, CE is brought
to a TTL low in order to enable the chip. The WE pin
must be at a TTL high during the entire read cycle.
The output drivers are made active by bringing
Output Enable (DE) to a TTL low. During read, the
addresses, CE, DE, and input data latches are
transparent.

seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

MD4000211D

6-56

E/M28C256
PRELIMINARY DATA SHEET

Write Mode

DATA Polling

One to 64 bytes of data can be randomly loaded
into the device. The part latches row addresses,
A6-A 14, during the first byte write. These
addresses are latched on the falling edge of the
WE signal and are ignored after that until the end
of twe. This will eliminate any false write into
another page if different row addresses are
applied and the page boundary is crossed.

The 28C256 has a maximum write cycle time of 10
ms. Typically though, a write will be completed in
less than the specified maximum cycle time. DA TA
polling is a method of minimizing write times by
determining the actual endpoint of a write cycle. If
a read is performed to any address while the
28C256 is still writing, the device will present the
ones-complement of the last byte written. When
the 28C256 has completed its write cycle, a read
from the last address written will result in valid
data. Thus, software can simply read from the part
until the last data byte written is read correctly. A
DATA polling read should not be done until a
minimum of tLP microseconds after the last byte is
written. Timing for a DA TA polling read is the same
as a normal read once the tLp specification has
been met.

The column addresses, AO-A5, which are used to
select different locations of the page, are latched
every time a new write is initiated. These
addresses and the DE state (high) are latched on
the falling edge of WE signal. For proper write
initiation and latching, the WE pin has to stay low
for a minimum of twpns. Data is latched on the rising
edge of WE, allowing easy microprocessor
interface.

Chip Erase
Upon a low to high WE transition, the 28C256
latches data and starts the internal page load timer.
The timer is reset on the falling edge of the WE
signal if another write is initiated before the timer
has timed out. The timer stays reset while the WE
pin is kept low. If no additional write cycles have
been initiated in (tSLC> after the last WE low to high
transition, the part terminates the page load cycle
and starts the internal write. During this time
which takes a maximum of 10 ms, the device
ignores any additional write attempts. The part
can now be read to determine the end of write
cycle (DATA Polling).

Certain applications may require all bytes to be
erased simultaneously. This feature, which
requires high voltage, is optional and timing
specifications are available from SEEQ.

Power Up/Down Considerations
There is internal circuitry to minimize a false write
during power up or power down. This circuitry prevents writing under anyone of the following
conditions:
1. Vee is less than VW1 V
2. A high to low Write Enable (WE) transition has
not occurred when the Vcc supply is between
VW1 Vand Vcc with CE low and OE high.

Extended Page Load

Writing will also be inhibited when WE, CE, or OE
are in TTL logical states other than that specified
for a byte write in the Mode Selection table.

In order to take advantage of the page mode's faster average byte write time, data must be loaded at
the page load cycle time (tSLc)' Since some
applications may not be able to sustain transfers
at this minimum rate, the 28C256 permits an
extended page load cycle. To do this, the write
cycle must be "stretched" by maintaining WE low,
assuming a write enable-controlled cycle, and
leaving all other control inputs (CE, DE) in the proper page load cycle state. Since the page load
timer is reset on the falling edge of WE, keeping
this signal low will inhibit the page load timer.
When WE returns high, the input data is latched
and the page load cycle timer begins. In CE controlled write the same is true, with CE holding the
timer reset instead of WE.

-

SeeQ Technology, Incorporated --------------------------..-&
MD4000211D

6-57

E/M28C256
PRELIMINARY DATA SHEET

Absolute Maximum Stress Range*

*COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Temperature
Storage .................... -65°C to +150°C
Under Bias ................ -65°C to +135°C
D. C. Volta~ ...' applied to all Inputs or Outputs
with respect to ground. . . . . . + 6. 0 V to -0.5 V
Undershoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respect .to ground . ............. -1.0 V
Overshoot pulse of less than 10 ns (measured at
50% point) applied to all inputs or outputs
with respect to ground . ............ +7.0V

I

Recommended Operating Conditions
Temperature Range

M28C256

E28C256

(Case) -55°C to +125°C

(Ambient) -40°C to 85°C

5 V± 10%

5 V± 10%

Vcc Power Supply

Endurance and Data Retention
Symbol

Condition

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TOR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

DC Characteristics Read Operation

(Over operating temperature and VccRange, unless otherwise specified)
Limits

Symbol

Parameter

Icc

Active Vcc Current

ISB1
ISB2

Min.

Max.
60

Units
rnA

Standby Vcc Current
(TTL Inputs)

2

rnA

CE=VIH, OE=VIL; All I/O open;
Other Inputs = VIL to VIH

Standby Vcc Current
(CMOS Inputs)

250

p.A

CE=Vcc-0.3
Other Inputs = VIL to VIH
All I/O Open

hL12]

Input Leakage Current

IOLI3]

Output Leakage Current

VIL

Input Low Voltage

-0.3
2.0

Test Condition
CE=OE=VIL; All I/O open;
Other Inputs = Vcc Max.
Min. read or write cycle time

1

p.A

VIN=VCC Max.

10

p.A

VOUT=VCC Max.

0.8

V
V

VIH

Input High Voltage

VOL

Output Low Voltage

V

IOL=2.1 rnA

VOH
VWI[l]

Output High Voltage

2.4

V

10H= -400 p.A

Write Inhibit Voltage

3.8

V

6
0.45

NOTES:

1. Characterized. Not tested.
2. Inputs only. Does not include I/O.
3. For I/O only,
i-..-

seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

MD4000211D

6-58

E/M28C256
PRELIMINARY DATA SHEET

AC Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V

Capacitance(1 1

E.S.D. Characteristics

TA= 25°C, f= 1 MHz

Symbol

Parameter

Max. Conditions

Symbol

Parameter

Value

Test Conditions

C'N

Input Capacitance

6 pF V'N= OV

VZAP(2)

E.S.D. Tolerance

> 2000V.

COUT

Data (1/0) CapaCitance

MIL-STD883
Test Method 3015

12 pF VI/O= OV

AC Characteristics Read Operation (Over operating temperature amd Vcc range, unless otherwise specified)
Umlts
ElM28C256-200 ElM28C256-250 ElM28C256-300 ElM28C256-350

Symbol

Parameter

Min.

lAC
tee

Read Cycle Time

200

fAA
toe

Address Access Time

tOF

Output or Chip Enable High to
output in HI-Z

0

toH

Ouput Hold from Address Change.
Chip Enable, or Ouput Enable,
whichever occurs first

0

Max.

Chip Enable Access Time

Output Enable Access Time

Max.

250
200
200
80
60

Min.

Max.

0
0

0

Test
Max. Units Conditions

350

300
250
250
90
60

Min.

300
300
90
80

0

0

ns

350
350
90
80

0

CE=OE=V'L

ns

OE=V'L

ns

CE=OE=V'L

ns

CE=V'L

ns

CE=V'L

ns

CE=OE=V'L

Read/DATA Polling Cycle

.

.

tRC

)]

ADDR ESSES

Min.

~

ADDRESS AN

-

NEXT ADDRESS
tAA-

~-

..SZf-

I-~-

_toE_

JZ5-

~~

DATA

.... 'oF ....

_I--

HIGHZ

.

DATAVAUD

JK
I

1M

toft-r,

toft
)!

DATAVAUD

H l-

•

Not••:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capaCitance.
2. Characterized. Nol lesled.

-- SeeQ Technology, Incorporated ------------------------~
MD400021/D

6-59

E/M28C256
PRELIMINARY DATA SHEET

A C Characteristics Write Operation (Over the operating temperature and Vcc range, unless otherwise specified)
Limits
ElM28C2S6-200 ElM28C2S6-2S0 ElM28C2S6-300 ElM28C2S6-3S0
Symbol

Parameter

twc

Write Cycle Time

Min.

tAS

Address Set-up Time

20

20

20

20

ns

tAH

Address Hold Time (see note 1)

150

150

150

150

ns

tcs

Write Set-up Time

0

0

0

0

ns

tCH

Write Hold Time

0

0

0

0

ns

low

CE Pulse Width (note 2)

150

150

150

150

ns

tOES

OE High Set-up Time

20

20

20

20

ns

tOEH

OE High Hold Time

20

20

20

ns

twp

WE Pulse Width (note 2)

150

150

150

20
150

tDS

Data Set-up Time

50

50

50

50

ns

tDH

Data Hold Time

0

0

0

0

ns

tSlC

Byte Load Timer Cycle
(Page Mode Only) (note 3)

tlP

Last Byte Loaded
to DATA Polling

Min.

Max.

10

0.2

Max.

Min.

10

0.2

200
650

200
650

Max.

Min.

10

0.2

200
650

0.2

Max.

Units

10

ms

ns

200

p,s

650

p,s

Write Timing
CE CONTROLLED WRITE CYCLE

WE CONTROLLED WRITE CYCLE

s----

OE

OE

X

X
CE

WE

~

~

~~

.~-=t
WE

DATA

CE

HIGHZ

DATA

HIGHZ

I---

Notes:
1. Address hold time is with respect to the falling edge of the control signal WE or CEo
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. tSlC min. is the minimum time before the next byte can be loaded. tSlC max. is the minimum time the byte load timer waits before
initiating internal write cycle.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD4000211D

6-60

E/M28C256
PRELIMINARY DATA SHEET

Page Write Timing
DATA POLLING

PAGE LOAD

"1-

------.~~--~c::::::---:::::-J.....,..----~\-~\

ADDRE:=:SS==E=S~"""=r-~",+_-"_"'.:::A:::L:.::ID,-,,......._ _ _ _

X::::::::::x=JALiiC

-I
r4f--

DON'T CARE

'---"

-;:-]~'----1~"-=-'"'~1-

WE _ _ _ _...j".J

r---<

DATA _H_IG_H_Z_ _ _{]

Ordering Information

D

L

28C256-250 /B

=:CIT

1:

PACKAGE
TYPE

TEMPERATURE
RANGE

PART TYPE

ACCESS TIME

SCREENING OPTION

D- Ceramic Dip

M--55'C to +125'C
(MIlitary)
E--40'C to +85'C
(Extended)

32K x 8 EEPROM

200~200

ns
250=250 ns
ns
350=350 ns

MIL 883 CLASS B
SCREENED

L-LCC

F-Fla.pack

--seeQ

M

300~300

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - -

MD400021/D

6-61

6-62

seeQ

E/M36C16
E/M36C32

High Speed CMOS Electrically Erasable PROM
PRELIMINARY DATA SHEET

October 1988

Features

Description

• Military and Extended Temperature Range
• -55°C to + 125°C Operation (Military)
• - 40°C to + 85 °C Operation (Extended)
• High Speed:
• 45 ns Maximum Access Time
• CMOS Technology
• Low Power:
• 400mW
• 10 Year Data Retention
• High Output Drive
• Sink 16mA at 0.45 V
• Source 4mA at 2.4 V
• 5 V ± 10% Power Supply
• Power Up/Down Protection Circuitry
• Fast Byte Write
• 5msiByte
• Automatic Byte Clear Before Write
• JEDEC Approved PROM Pinout
• Direct Replacement for Bipolar PROMs
• Slim 300 mil Packaging Available

SEEQ's 36C16/32 are high speed 2K x 8/4K x 8 Electrically Erasable Programmable Read Only Memories,
manufactured using SEEQ's advanced 1.25 micron
CMOS Process.
The 36C16/32 are intended as bipolar PROM
replacements in high speed applications. The 45ns
maximum read access time meets the requirements
of many of today's high performance processors. The
endurance, the number of times the part can be
erased/written, is specified to be greater than 100
cycles. The 36C16/32 are built using SEEQ's proprietary oxynitride EEPROM process and its innovative
Q Celf M design.
Data retention is specified to be greater than 10 years.
The 36C16/32 are available in 24 pin Slim 300 mil
CERAMIC DIP, and 28 pin LCe. Full featured EEPROM
versions are also available (38C16/32) in 24/28 pin
DIP and 32 pin surface mount packages.

Block Diagram

E2
MEMORY
ARRAY

ROW
DECODERS

Pin Configuration
LEAD LESS CHIP CARRIER
BOTTOM VIEW

DUAL-IN-L1NE
TOP VIEW

COLUMN ADDRESS
GATING

COLUMN
DECODER

36C16/36C32
CS,

ERASE
WRITE

CONTROL
CS2
LOGIC
CSa[2) - . _ - _. . .

(24 pins)

I/O

tl U
~ ~ > z

BUFFERS

READ

1/0 0_7

C S1
CS2
C S3

ADDRESSES - COLUMN
ADDRESSES - ROW

--- SeeQ
MD400028/B

Aa

As
A4

As
Ag

Aa
A2

CS,
CS3/A" (1)

A,

CS2

1/0 7

Ao

1/07

1/06

1/0 0

1/0 6

g'" uz

NOTES: 1.
2.
3.
4.

Q Cell is a trademark of SEEQ Technology, Inc.

Vee

A6

NC

gg

DATA INPUT (WRITE)
DATA OUTPUT (READ)

A7
A4

A2

CS2

CHIP SELECT INPUTS

1/ 0 0'7

£ .'£

CS3/A"[4)

Pin Names
Ao·A3
A4.A11 [31

.<

INDEX
CORNER

c

z

Cl

gg

1/0,

1/0 5

1/02

1/04
.... 1/0
3

GND _ _ _-

Pin 19 is A" on the 36C32.
CS3 is on the 36C16 only.
A4-A'0 on the 36C16.
Pin 23 is CS3 on 36C16 and is All on 36C32.

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J

6-63

E/M36C16
E/M36C32
PRELIMINARY DATA SHEET

Device Operation
Operational Modes
MODE PIN
Read
Standby

Write

CS,

CS2

CS3[2)

I/O

VIL

VIH

VIH

DouT

VIH

X

X

X

VIL

X

X

X

VIL

VH[1)

VIL

X

HIZ

DIN

X: Any TIL level

Read
A read is started by presenting the addresses of
the desired byte to the address inputs. Once the
address is stable, the chip select inputs should be
brought to the proper levels in order to enable the
outputs (see Table above).

Write
To write into a particular location, addresses and
data must be valid, CS 2 must be TTL low and a V/ 1
pulse has to be applied to CS 1 for 5ms. An
automatic internal byte clear is done prior to the
byte write. The byte clear feature is transparent to
the user.

NOTES:
1. VH - High Voltage.
2. GS 3 applies only to the 36G16. This pin becomes A11 in the
36G32.

~---seeQTh~~fu~~~~O~~d--------------------------~
MD4000281B

6-64

E/M36C16
E/M36C32
PRELIMINARY DATA SHEET

Absolute Maximum Rating
Temperature
Storage . . . . . . . . . . . . . . . . . . . ..
Under Bias. . . . . . . . . . . . . . . . . ..
All Inputs and Outputs
with Respect to Ground . . . . . . . ..
CS 1 with Respect to Ground. . . . ..

- 65°C to + 150°C
- 65°C to + 135°C

COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

- 3. V to + 7 V D. C.
- 0.5 V to + 14 V D. C.

Recommended Operating Conditions
E36C16
E36C32

I

l

Vee Supply Voltage
Temperature Range (Read Operation)

M36C16
M36C32

SV±10%

SV±10%

(Ambient) - 40°C to + 8SoC

(Case) -SsoC to 12SoC

DC Operating Characteristics (Over operating temperature and Vcc Range, unless otherwise specified)
Limits
Symbol

Parameter

Min.

Max.

Vee Active Current

Icc

Unit

Test Condition

80

rnA

CS2 = CS3 = VIH ; CS 1 = VIL ;
Address inputs = 20 MHz
I/O=OmA

liN

Input Leakage Current

1

pA

0.1 V>=VIN<=Vee Max.

lOUT

Output Leakage Current

10

pA

VouT=Vee Max.

VIL

Input Low Voltage

-O.S

0.8

V

VIH

Input High Voltage

2

6.S

V

Vee Min

VH

Input High Voltage During
Write/Chip Erase

10.8

13.2

V

For CS1 Input Only

VOL

Output Low Voltage

0.45

VOH

Output High Voltage

IOS[1][2]
Vel [2]

-

V

IOL=16 rnA, Vee= Vee Min.

2.4

V

IOH=-4 rnA, Vee= Vee Min.

Output Short Circuit Current

-20

rnA

Input Undershoot Voltage

-3

V

Vec=Vee Max,
Vour=O
VIN undershoot pulse width < 10ns

NOTES:
1. Only one input at a time for less than one second.
2. Characterized. Not Tested.

---- SeeQ
MD4000281B

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....J

6-65

E/M36C16
E/M36C32
PRELIMINARY DATA SHEET

AC Test Conditions
Output Load: 10 TTL gates and total CL =30pF
Input Rise and Fall Times: <5ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level:
Inputs 1.5V
Outputs 1.5 V

3.0V

Symbol

Parameter
E.S.D. Tolerance

Value

90%

GND----...IJ
~5ns

INPUT PULSES

E. S. D. Characteristics
VZAP[2)

------11--------'\1

Test Conditions

MIL-STD 883
>2000 V
Test Method 301 5

Capacitance [1)

TA=25°C, f=1 MHz

Symbol Parameter

Max.

CIN

Input Capacitance

COUT

Data (I/O) Capacitance

Conditions

6 pF VIN= OV
12 pF

VI/O=

OV

AC Characteristics Read Operation (Over operating temperature and Vcc Range, unless otherwise specified)
Limits
E/M36C16·45
E/M36C32·45

E/M36C16·70
E/M36C32· 70
Min.
Max.

55

70

Symbol

Parameter

Min.

tRC

Read Cycle Time

45

icE

Chip Select Access
Time

30

35

tAA

Address Access Time

45

tOF

Output Enable to
Output not being Driven

25

Output Hold from
Address Change or Chip
Select whichever occurs first

tOH

Max.

E/M36C16-55
E/M36C32·55
Min.
Max.

ns

45

ns

55

70

ns

30

35

ns

0

0

0

Units

ns

Read Cycle Timing
t--------tRc------+1
ADDRESSES
VALID

ADDRESSES

tOH

NOTE 3
VALID
OUTPUT

1/0 0-7

NOTE 3

NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not Tested.
3. Transition is measured at steady state level - O.SV or steady state low level + O.SV on the output from the 1.SV level on the input.
L - ._ _ _

SeeQ
MD4000281B

Technology, Incorporated

-------------------------------.1
6-66

E/M36C16
E/M36C32
PRELIMINARY DATA SHEET

AC Characteristics Write Operation (All Speeds)
(Over Vcc Range, TA = 25° ± 5°C, unless otherwise specified)

E/M36C16
E/M36C32
Symbol

Parameter

Min.

Max.

Units

twp

Write Pulse Width

5

50

ms

tAS

Address Set-up Time

0

JJ.s

tAH

Address Hold Time

0.5

JJ.s

tcs

CS 2 Set-up Time

0

JJ.s

tCH

CS 2 Hoid Time

0

JJ.s

tos

Data Set-up Time

0

JJ.s

tOH

Data Hold Time

0

tWR

Write Recovery

JJ.s

10

JJ.s

Write Cycle Timing

ADDRESSES

"

,

-tAS-

VHMIN
6.5V

"

ADDRESSES
VALID

J\

------------------------

l-twp.::1

I-

)\
!-tAH_

\
\

/

-'

,-

tcs-

--

-I"-

\
~twR
i-tCH

~~

- ...../

j

I

\

I

CS3[1)

1/00-7

}

1

-

-f~

DATA IN

••

1- tCEi--

:

~ '-tAA

\/f-

DATA OUT

J\

. - - - - - - - W R I T E CYCLE-----_.~I••--READ CYCLE

f - o •l

NOTE:
1. CS3 is A11 on

36C32.

---- SeeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

..J

~D400028/B

6-67

E/M36C16
E/M36C32

Ordering Information

PRELIMINARY DATA SHEET

D
D

M
M

36C16-45
36C32-45

/B
/B

~~I~

PACKAGE

TEMPERATURE
RANGE

PART TYPE

ACCESS TIME

SCREENING OPTION

D-SLIM
CERAMIC DIP

M - -55·C to +125·C
(MILITARY)
E - -40·C to +85·C
(EXTENDED)

38C18 - 2K x 8 EEPROM
38C32-4Kx8 EEPROM

45-45 n.
55-55 n.
70-70 n.

IB- MIL 883 CLASS B

L-LCC

SCREENED

The "Preliminary Data Sheet" designation on a SEEQ data sheet indicates that the product is not fully characterized. The
specifications are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. SEEQ
Technology or an authorized sales representative should be consulted for current information before using this product. No responsibility is assumed by SEEQ for its use, nor for any infringements of patents and trademarks or other rights of third parties
resulting from its use. SEEQ reserves the right to make changes in specifications at any time and without notice.

~------~~~(i) Technolog~ Incorporated--------------------------------------------------------------~
~D400028/B
6-68

seen

E/M38C16
E/M38C32

\,,)/

High Speed CMOS Electrically Erasable PROM
PRELIMINARY DATA SHEET

October, 1988

Features

Description

• Military and Extended Temperature Range
• - 55°C to + 125°C Operation (Military)
• -40°C to +85°C Operation (Extended)
• High Speed:
• 45 ns Maximum Access Time
• CMOS Technology
• Low Power:
• 400mW
• High Endurance:
• 10,000 Cyc/esl Byte Minimum
• 10 Year Data Retention
• On-Chip Timer and Latches
• Automatic Byte Erase Before Write
• Fast Byte Write: 5 msl Byte
• High Speed Addressl Data Latching
• 50 ms Chip Erase
• 5 V ± 10% Power Supply
• Power UplDown Protection Circuitry
• DATA Polling of Data Bit 7
• JEDEC Approved PROM Pinout
• 38C16: 2816A Pin Compatible
• 38C32: 28C64 Pin Compatible

SEEQ's 38C16132 are high speed 2K x 814K x 8 Electrically Erasable Programmable Read Only Memories
(EEPROM), manufactured using SEEQ's advanced
1.25 micron CMOS process.
The 38C16132 are ideal for high speed applications
which require non-volatility and in-system reprogrammability. The endurance, the number of times a byte may
be written, is specified to be greater than 10,000 cycles
per byte minimum. The high endurance is accomplished
using SEEQ's proprietary oxynitride EEPROM process
and its innovative Q CelfM design. System reliability in
applications where writes are frequent is increased because of the low endurance-failure rate of the Q Cell. The
45ns maximum access time meets the requirements

Pin Configuration
38C16

A4.A" [1]

A7

Vee

NC

Vee

A6

As

NC

WE

A5

Ag

A7

NC

As
Ag

A4

WE

A6

A3

DE

A5

A2

A,o

A4

A"

A,

CE

A3

DE

Ao

1/07

A2

A,o

ADDRESSES - COLUMN
ROW ADDRESSES

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

lIDo

1/0 6

DATA INPUT (WRITE)
DATA OUTPUT (READ)

I/O,

1/0 5

1/02

1/0 4

GND

1/0 3

1/00.7

Block Diagram

38C32
(28 pins)

(24 pins)

Pin Names
Ao-A3

DUAL-IN-LiNE
TOP VIEW

A,

CE

Ao

1/07

1/00

1/06

I/O,

1/05

1/02

1/04

GND

1/0 3

AO-A3

LEADLESS CHIP CARRIER
BOTTOM VIEW
38C16
38C32

~ I~ ~ ~ ~ ~ .(

1. A,-A,o on 38C16.
No Connect

2. NC -

INDEX
CORNER

~ I~ ~ ~ ~ ~.(

INDEX
CORNER

1/00-7

Q Cell is a trademark of SEEQ Technology, Inc.
L...-_ _ _

SeeQ
MD400030lB

Technology, Incorporated

--------------------------.....1
6-69

E/M38C16
E/M38C32
PRELIMINARY DATA SHEET

of many of today's high performance processors. The
38C16132 have an internal timer which automatically
times out the write time. The on-chip timer, along with the
input latches, frees the microprocessor for other tasks
during the write time. DATA POlling can be used to determine the end of a write cycle. All inputs are TTL compatible for both write and read modes.

Write
To write into a particular location, addresses must
be valid and a TTL low is applied to the write enable (WE) pin of a selected (CE low) device. This
initiates a write cycle. During a write cycle, all
inputs except for data are latched on the falling
edge of WE (or CE, whichever one occurred last).
Write enable needs to be at a TTL low only for the
specified twp time. Data is latched on the rising
edge of WE (or CE, which ever one occurred first).
An automatic byte erase is performed before data
is written.

Data retention is specified to be greater than
10 years.
The 38C16 is available in 24 pin CERAMIC DIP;
the 38C32 in 28 pin CERAMIC DIP; 32 pin LCC
packaged versions are also available. 24 pin
versions of both 38C16 and 38C32 intended for
bipolar PROM replacement are also available
(36C16/36C32). All parts are available in commercial as well as military temperature ranges.

DATA Polling
The EEPROM has a specified twe write cycle time
of 5ms. The typical device has a write cycle time
faster than the t we . DATA polling is a method to
indicate the completion of a timed write cycle.
During the internal write cycle, the complement of
the data bit 7 is presented at output 7 when a read
is performed. Once the write cycle is finished, the
true data is presented at the outputs. A software
routine can be used to "poll'~ i.e. read the output,
for true or complemented data bit 7. The polling
cycle specifications are the same as for a read
cycle. During data polling, the addresses are
don't care.

Device Operation
Operational Modes
MODE PIN

CE

OE

WE

I/O

Read

VIL

VIL

VIH

DOUT

Standby

VIH

X

X

HIZ

Write

VIL

VIH

VIL

DIN

Write
Inhibit

X

X
X

VIH

VIL

VIL
VIL

VIH
VIL

HI Z/DOUT
HIZ
HI Z/DOUT
No Operation
(HI Z)

VIH

VH I2]

VIH

VIH

X

Chip Erasel1 ]

X

Chip Erase
Certain applications may require all bytes to be
erased simultaneously. This feature, which
requires high voltage, is optional and timing
specifications are available from SEEQ.

HIZ

X: Any TIL level

Power Up/Down Considerations

Read
A read is started by presenting the addresses of

the desired byte to the address inputs. Once the
address is stable, CE is brought to a TTL low in
order to enable the chip. The WE pin must be at a
TTL high during the entire read cycle. The output
drivers are made active by bringing output enable
(DE) to a TTL low. During read, the address, CE,
OE, and I/O latches are transparent.

Writing will also be inhibited when WE, CE, or DE
are in TTL logical states other than those
specified for a byte write in the Mode Selection
table.

NOTES:
1. Chip erase is an optional mode.
2. VH - High Voltage.

'----- SeeQ
MD400030lB

Protection against false write during Vee power
up/down is provided through on chip circuitry.
Writing is prevented under anyone of the following
conditions:
1. Vee is less than VW1 V.
1. A high to low Write Enable (WE) transition has
not occurred when the Vee supply is between
VW1 V and Vee with CE low and OE high.

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

6-70

E/M38C16
E/M38C32
PRELIMINARY DATA SHEET

Absolute Maximum Rating
Temperature
Storage . . . . . . . . . . . . . . . . . . . .. - 65°C to + 150°C
Under Bias . ................ " - 65°C to + 135°C
All Inputs and Outputs
with Respect to Ground . . . . . . . .. - 3 V to + 7 V D. C.

COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Recommended Operating Conditions
M38C16
M38C32

I Vcc Supply Voltage
I Temperature Range

E38C16
E38C32

5 V± 10%

5V± 10%

(Ambient) -40°C to 85°C

(Case) -55°C to 125°C

Endurance and Data Retention
Condition

Symbol

Parameter

Value

Units

N

Minimum Endurance

10,000

Cycles/Byte

MIL-STD 883 Test
Method 1033

TDR

Data Retention

>10

Years

MIL-STD 883 Test
Method 1008

DC Operating Characteristics (Over operating temperature and Vec Range, unless otherwise specified)
Limits
Symbol

Parameter

Min.

Max.

Unit

Test Condition

Icc

Vce Active Current

80

rnA

CE=OE=VIL ;
Address Inputs = 20MHz
110 = OrnA

ISB

Standby Vce Current

40

rnA

CE=VIH ;
All 110 open;
All other inputs TIL don't care;

liN

Input Leakage Current

1

pA

0.1V> =VIN < = Vee Max.

lOUT

Output Leakage Current

10

pA

VouT=Vce Max.

VIL
VIH

Input Low Voltage

-0.5

0.8

V

Input High Voltage

2

6.5

V

VOL

Output Low Voltage

0.45

V

10L = 2.1 rnA, Vee = Vce Min.

VOH
VWI!l]

Output High Voltage

2.4

V

10H= -400pA, Vec Min.

Write Inhibit Voltage

3.8

V

VCI !l]

Input Undershoot Voltage

-3.0

V

Vcc Min.

VIN undershoot pulse width < 10ns

NOTE:
1. Characterized. Not Tested.

'"'-----seeQ
MD400030lB

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -......

6-71

E/M38C16
E/M38C32

AC Test Conditions

PRELIMINARY DATA SHEET

Output Load: 1 TTL gate and total CL = 30 pF
Input Rise and Fall Times: < 5 ns
Input Pulse Levels: 0 V to 3 V
Timing Measurement Reference Level:
Inputs 1.5V
Outputs 1.5 V

3.0V - - - - - - 1 r - - 9 0 - % - - - - - - , I

GND-----'I
S5ns

INPUT PULSES

E. S. D. Characteristics
Symbol
VZAP [2j

Parameter

Value

E.S.D. Tolerance

> 2000 V

Capacitance{1] TA=25°C, f=1
Test Conditions

Symbol Parameter

MIL-STD 883
Test Method 3015.3

CIN

Input Capacitance

COUT

Data (I/O) Capacitance

MHz
Max.

Conditions

6 pF VIN= OV
12 pF VI/o= OV

AC Characteristics Read Operation
(Over operating temperature and Vcc Range, unless otherwise specified)
Limits
E/M38C1 6-45
E/M38C32-45
Symbol

Parameter

Min.

E/M38C16-55
E/M38C32-55

Max.

tRC

Read Cycle Time

teE

Chip Enable Access
Time

30

Min.

45

Max.

E/M38C16-70
E/M38C32-70
Min.

Max.

Units

Test
Conditions

ns

CE=OE=VIL

35

45

ns

OE=VIL

55

70

tAA

Address Access Time

45

55

70

ns

CE=OE=VIL

tOE

Output Enable Access
Time

25

30

40

ns

CE=VIL

tDF

Output or Chip Enable to
Output not being Driven

25

30

35

ns

CE=VIL

tOH

Output Hold from
Address Change, Chip
Enable Or Output Enable
Which ever occurs first

ns

BE orOE=VIL

0

0

0

Read Cycle Timing
~-----tRC------~

ADDRESSES
VALID

ADDRESSES

tOE
tOH

110 0-7

-----------+----+

VALID
OUTPUT

NOTE 3
NOTE 3

NOTES:
,. This parameter is measured only for the initial qualification and after process or design changes which may affect capacitance.
2. Characterized. Not Tested.
3. Transition is measured at steady state level - O.SV or steady state low level + O.SV on the output from the' .SV level on the input.

~---~~~~Th~~~~~~~O~~d-------'-----------------------~
MD400030lB

6-72

E/M38C16
E/M38C32
PRELIMINARY DATA SHEET

AC Characteristics Write Operation
(Over operating temperature and Vee Range, unless otherwise specified)
E/M38C16-45
E/M38C32-45
Symbol

Parameter

twc

Write Cycle Time

Min.

tAS

Address Set-up Time

tAH

Address Hold Time

tcs

Write Set-up Time

tCH

Write Hold Time

tcw

CE Pulse Width

tOES

OE High Set-up Time

tOEH

OE High Hold Time

twp

WE Pulse Width

tos

Data Set-up Time

tOH

Data Hold Time

top

Time to DATA Polling
from Byte Latch

E/M38C16-55
E/M38C32-55
Min.

Max.

Max.

E/M38C16-70
E/M38C32-70
Min.

5

5
0
25
0
0
25
5
0
25
25
0

0
30
0
0
30
5
0
30
30
0

Max.

Units

5

ms
ns

0
40
0
0
40
5
0
40
40
0

45

55

ns
ns
ns
ns
ns
ns
ns
ns
ns

70

ns

Write Cycle Timing

CE CONTROLLED WRITE CYCLE

WE CONTROLLED WRITE CYCLE

1 - - - - - - BYTE WRITE----~-

i------BYTE WRITE----I4-

OE

~;x=

~

WE

~

~~-----~-----~

DATA

CE

HIGHZ
HIGHZ
DATA --------------~

NOTES:
1. Address hold time is with respect to the falling edge of the control signal

~--- SeeQ
MD400030lB

Technology, Incorporated

We or CE.

-------------------------------1
6-73

E/M38C16
E/M38C32
PRELIMINARY DATA SHEET

Ordering Information

r
OM

~CB.-1~

~----------------~

r-----------------------~

I

PAckAGE'
TYPE
D- CERAMIC DIP
L-LCC

1

38C16-45 /B

I

TEMPERATURE
RANGE

PART TYPE

ACCESS TIME

SCREENING OPTION

M - -55·C to +1 25·C
(MILITARY)
E - -40·C to +85·C
(EXTENDED)

38C16 - 2K x 8 EEPROM
38C32 - 4K x 8 EEPROM

45-45 ns
55-55 ns
70-70 ns

/B - MIL 883 CLASS B
SCREENED

The "Preliminary Data Sheet" designation on a SEEQ data sheet indicates that the product is not fully characterized. The
specifications are subject to change, are based on design goals or preliminary part evaluation, and are not guaranteed. SEEQ
Technology or an authorized sales representative should be consulted for current information before using this product. No responsibility is assumed by SEEQ for its use, nor for any infringements of patents and trademarks or other rights of third p~rties
resulting from its use. SEEQ reserves the right to make changes in specifications at any time and without notice.

L...-_ _ _ _

SeeQ
MD400030lB

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

6-74

seeQ

MODULE M28C010
Timer £2
1024K Electrically Erasable PROM
October 1988

PRELIMINARY DATA SHEET

Features

Description

• CMOS Technology
• Military Temperature Range
• Low Power Operation
• 70 mA Active Current
• 2 mA Standby Current
• On-Chip Timer
• Automatic Erase Before Write
• 64 Byte Page Mode . .. Fast Effective
Write Time
• 80 p,sec Average Byte Write Time
• Write Cycle Completion Indication
• Data Polling
• 5V± 10% Power Supply
• Power Up/Power Down Protection Circuitry
• JEDEC Approved Byte Wide Pinout

SEEQ's MM28C010 is a CMOS 5V only, 128K x 8
Electrically Erasable Programmable Read Only
Memory (EEPROM). The MM28C010 consists of 4
28C256 (32K x 8) CMOS EEPROMs and a 2 to 4 line
decoder in LCC packages, mounted on and interconnected on a ceramic substrate. The MM28C010
is available in a 32 pin module package and is ideal
for applications which require low power consumption, non-volatility and in-system reprogrammability.

Pin Names
A16-AO

ADDRESSES

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

I/O

DATA INPUT (WRITE)/DATA
OUTPUT (READ)

Block Diagram

Pin Configuration
vce
WE
NC
A14

A15
A 1 6 _ SEL2

2 T04

A7

A13

A6

AS

A5

A9

A4

All

A3

OE

A2

A10

Al

CE

AO

1/07

1/00

1/06

DECODER

..1\

I/~~~: ll--~'~I--"""I''''--''I

1/0 1

1/05

1/02

1/04

vss

1/03

1/07-0

~~~~~C~O~~~~~O~~d--------------------------~
MD 400044/A

6-75

MM28C010
PRELIMINARY DATA SHEET

The MM28C010 has an internal timer which
automatically times out the write time. The on-chip
timer, along with the input latches, frees the micraprocessor for other tasks during the write time. The
MM28C010's write cycle time is 10msec maximum.
An automatic erase is performed before a write.
The Data Polling feature of the MM28C010
can be used to determine the end of a write cycle.
Data retention is greater than 10 years.

Device Operation
Operational Modes
There are four operational modes (see Table 1); only
TTL inputs are required. Write can only be initiated
under the conditions shown. Any other conditions
for CE, DE, and WE will inhibit writing and the 110
lines will either be in a high impedance state or
have data, depending on the state of the forementioned three input lines.

Table 1
Mode Selection
Mode PI"

CE

OE

WE

READ

VIL

VIL

VIH

STANDBY
WRITE

VIH

X

X

VIL

VIH

VIL

X

VIH

VIH

X
X

X

VIL

WRITE
INHIBIT

X
X

110
Dour
HI-Z

Writes
To write into a particular location, addressess must
be valid and a TTL low is applied to the write enable
(WE) pin of a selected (CE lo.!!l. device. This combined with the output enable (OE) being high, initiates
a write cycle. During a byte write cycle, all inputs
exc!£!! data are latched on the falling edge of ~
(or CE, whichever one occurred last). Write enable
needs to be at a TTL low only for the specified twp
time. Data is latched on the riSing edge of ~ (or
CE, whichever occurred first). An automatic erase
is performed before data is written.
The MM28C010 can write both bytes and blocks of
up to 64 bytes. The write mode is discussed below.

Write Cycle Control Pins
For system design simplificatiOJ1. the MM28C010 is
designed such that either the CE or WE pin can be
used to initiate a write cycle. The device uses the
latest high-ta-Iow transition of either CE or ~
signal to latch the data. Address and DE sf!!J!p and
hold are with respect to the later of ~ or WE; data
setEE and hold is with respect to the earlier of WE
orCE.

To simplify the following discussion, the WE pin is
used as the control pin throughout the rest of this
document. Timing diagrams of both write cycles
are included in the AC characteristics.

DIN
HI-Z or Dour
HI-Z
HI-Z or Dour

Write Mode

X: any CMOS/TTL level

Reads
A read is typically accomplished by presenting the
addresses of the desired byte to the address inputs.
Once the address is stable, (JE is brought to a TTL
low in order to enable the chip. The WE pin must be
at a TTL high during the entire read cycle. The output
drivers are made active by bringing output enable
(CiE) to a TTL low. During read, the addresses, eE,
OE, and input data latches are transparent.

One to 64 bytes of data can be loaded randomly into the MM28C010. Address lines A15 and A16 must
be held valid during the entire page load cycle. The
part latches row addresses, A6-A14 during the first
byte write. These addresses are latched on the failing edge of WE signal (assuming WE control write
cycle) and are ignored after that until the end of the
write cycle. This will eliminate any false write into
another page if different row addresses are applied
and the page boundary is crossed.

seeQ T e c h n o l o g y , I n c O r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - J
MD4000441A

6-76

MM28C010
PRELIMINARY DATA SHEET

Data Polling

The column addresses, AO-AS which are used to
write into different locations of the page, are latched every time a new write is initiated. These addresse~ along with OE state (high) are latched on
the fallmg edge of WE ~al. For proper write initiation and latching, the WE pin has to stay low for a
minimurT}_E.t twp ns. Data is latched on the rising
edge of WE, allowing easy microprocessor interface.

The MM28G010 has a maximum write cycle time of
10ms. Typically though, a write will be completed in
less than the specified maximum cycle time. DA TA
polling f~ a method of minimizing write times by
determmmg the actual end point of a write cycle. If
a read is performed to any address while the
MM28G010 is still writing, the device will present
the Ones-complement of the last data byte written.
When the MM28G010 has completed its write cycle, a read from the last address written will result in
valid data. Thus software can Simply read from the
part until the last data byte written is read correctly.
A DATA polling read should not be done until a
mi~imum .Of. tLP micro~nds after the last byte is
wfltten. Tlmmg for a DATA polling read is the same
as a normal read once the tLP specifications have
been met.

Upon a low to high WE tranSition, the MM28GOto
latches data and starts the internal page loader
timer. The timer is reset on the falling edge of WE
signal if a write is initiated before the timer has timed out. The timer stays reset while the WE pin is
kept low. If no more write cycles have been initiated
in (tBU:) after the last WE low to high trans;t':~"', the
part terminates page load cycle and starts the internal write. During this time, which takes a maximum
of 1Oms, the device ignores any additional load attempts. The part can be now read to determine the
end of write cycle (DATA Polling). A 160p,s maximum
effective byte write time can be achieved if the page
is fully utilized.

Power Up/Down Considerations
There is internal circuitry to minimize a false write
du~i~g Vcc power up or down. This circuitry prevents
wfltmg under anyone of the following conditions:
1. Vcc is less than VWI V.
2 . A high to low Write Enable (WE) transition has
not occurred when J!!..e Vee sueeJy is between
VWI V and Vee with GE low and OE high.

Extended Page Load
In order to take advantage of the page mode's
faster average byte write time, data must be loaded
at. the. page load cycle time (tBLd. Since some applIcatIons may not be able to sustain transfers at
this minimum rate, the MM28G010 permits an extended page load cycle. To do this, the write cycle
must be 'stretched' by maintaining WE low, assuming a write enable controlled cycle and leaving all
other control inputs (GE, OE) in the proper page
load cycle state. Since the page load timer is reset
on the falling edge of WE, keeping this signal low
will inhibit the page load timer. When WE' returns
high~ the inpu.t data is latched and the page load cycle tImer begms. In GE controlled write the same is
true, with GE holding the timer reset instead of WE.

Writ~ng will also be inhibited when WE, GE, or DE
are m TTL logical states other than that specified for
a byte write in the Mode Selection table.

seeQ TeChnOIOgy.lncorporated----------------------------I
MD 4000441A

6-77

MM28C010
PRELIMINARY DATA SHEET

Absolute Maximum Stress Range *

* COMMENT: Stresses above those listed under
''Absolute Maximum Ratings" may cause permanent
damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.

Temperature
Storage . ................ - 65°C to + 150°C
Under Bias . ............. - 65°C to + 135°C
All Input or Output Voltages
with Respect to Vss . .......... + 6 V to - 0.5 V

Recommended Operating Conditions
MM28C010
Temperature Range

-55°C to +125°C
(case temp.)

vee Power Supply

5V± 10%

Endurance and Data Retention
Symbol

Parameter

Value

Units

N
K

Minimum Endurance(4)

10,000
1,000

Cycles/ Byte

TOR

Data Retention

>10

Years

Condition
MIL-STD 833 Test
Method 1033
MIL-STD 833 Test
Method 1008

DC Charateristics Read Operation
(Over operating temperature and Vee Range, unless otherwise specified)
Limits
Symbol

Parameter

lee

Min.

-

Max.

Units

Test Condition

Active Vee Current

70

mA

CE=OE=VIL; All 1/0=0 ma;
Addr=5MHz

ISB,

Standby Vee Current
(TIL Inputs)

10

mA

CE = VIH. OE = VIL; All I/O = 0 ma;

ISB2

Standby Vee Current
(CMOS Inputs)

2

mA

CE = Vee - 0.2;
A15, A16=Vee-O.2
Other Inputs = VIH
All 1/0=0 ma

hLl2)

Input Leakage Current

5

p,A

VIN = Vee Max.

loLl3)

Output Leakage Current

25

p,A

VOUT=Vee Max.

VIL

Input Low Voltage

-0.3

0.8

V

VIH

Input High Voltage

2.0

V

VOL

Output Low Voltage

6
0.45

V

IOL=2.1 mA

VOH
VWI(1)

Output High Voltage

2.4

V

IOH = - 400 p,A

Write Inhibit Voltage

3.8

V

NOTES:
1. Characterized. Not tested.
2. Inputs only. Does not include I/O.
3. For I/O only.
4. Endurance can be specified as an option to be 1000 or 10000 cycles/byte minimum.

MD 4000441A

6-78

MM28C010
PRELIMINARY DATA SHEET

AC Test Conditions
Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: < 10 ns
Input Pulse Levels: 0.45 V to 2.4 V

Timing Measurement Reference Level:
Inputs 0.8 V and 2 V
Outputs 0.8 V and 2 V

Capacitance[1 1 TA =25°C, t = 1 MHz

E. S.D. Characteristics

Symbol

Parameter

Max.

Conditions

Symbol

CIN

Input Capacitance

30pF

VIN=OV

VZAP[21

CaUl

Data (I/O) Capacitance

40pF

VI/O=OV

Parameter

Value

E.S.D. Tolerance >1000V

Test Conditions
MIL=STD 883
Test Method 3015

AC Characteristics Read Operation
(Over operating temperature and Vcc range, unless otherwise specified)
Limits
MM28C01D-250

Symbol

MM28C01D-300

MM28C01D-350

Units

Test
Conditions

ns

CE=OE=VIL

Parameter

Min.

tRC

Read Cycle Time

250

tCE

Chip Enable Access Time

250

300

350

ns

OE=VIL

tAA

Address Access Time

250

300

350

ns

CE=OE=VIL

150

ns

CE=VIL

80

ns

CE=VIL

ns

CE=OE=VIL

toE

Output Enable Access Time

tOF

Output or Chip Enable High to
Output in Hi-Z

0

tOH

Output Hold from Address Change,
Chip Enable, or Output Enable,
whichever occurs first

0

Max.

Min.

Max.

300

150
60

Min.
350

150
0

Max.

80

0

0
0

Read/DATA Polling Cycle
t------tRc-------+i

ADDRESSES

ADDRESS AN

CE------------~_

OE------------~------_

NOTES:
1. This parameter is measured only for the initial qualification and after process or design changes which may affect
capacitance.
2. Characterized. Not tested.

SeeQ T e c h n o l o g y , l n c O r p l o r a j t e d - - - - - - - - - - - - - - - - - - - - - - - - - - J
MD 4000441A

6-79

MM28C010
PRELIMINARY DATA SHEET

A C Characteristics Write Operation
(Over the operating temperature and Vcc range, unless otherwise specified)
Limits
MM28C010-250

Symbol

Parameter

twc

Write Cycle Time

tAS

Address Set-up Time

tAH

Address Hold Time (see note

tcs
tCH

Min.

Max.

MM28C010-300

Min.

10

Max.

MM28C010-350

Min.

10

Max.
10

Units
ms

20

20

20

ns

150

150

150

ns

Write Set-up Time

0

0

0

ns

Write Hold Time

0

0

0

ns

1)

tcw

CE Pulse Width (see note 2)

150

150

150

ns

tOES

OE High Set-up TIme

20

20

20

ns

tOEH

OE High Hold Time

20

20

20

ns

twp

WE Pulse Width (see note 2)

150

150

150

ns

tos

Data Set-up Time

50

50

50

ns

tOH

Data Hold Time

0

0

0

tBlC

Byte Load Timer Cycle (Page Mode Only)

0.2

200

0.2

200

0.2

ns
200

p,S

1

ms

(see note 3)

1

Last Byte Loaded to DATA POlling

tlP

1

Write Timing
WE CONTROLLED WRITE CYCLE

CE CONTROLLED WRITE CYCLE

C E - - -... ,

WE---~I

DATA----=.;..;;..-Cl

NOTES:
1. Address hold time is with respect to the falling edge of the control signal WE or CE.
2. WE and CE are noise protected. Less than a 20 nsec write pulse will not activate a write cycle.
3. tBlC min. is the minimum time before the next byt~ can be loaded. tBlC max. is the minimum time the byte
load timer waits before initiating internal write cycle.

~~~~~~n~~~~~~O~~d-----------------------------~
MD 4000441A

6-80

MM28 CO10
PRELIMINARY DATA SHEET

Page Write Timing
PAGE L O A D I - - - - - - - - - + . -POLLING
DATA~

I

---------r.--~------~\:::::-----:::-:::I-~-----------,-~--,

r-:.:~

ADDRESSES

VALID

.

~

X'"_--=D::.:O~N:..:·T:..:C::::A;::.:R:::.E_~;:x=

CE---_
wE----!lJ

DATA-...;.;.~..;;;....-

-)
v

ROW
DECODERS

MEMORY
ARRAY

A2

Al0

Al

CE
07
Os
°s

AC

c==>

---

04

-)
v

COLUMN
DECODER

MODE
Read
Output Disable
Standby
Program
Program Verify
Program Inhibit
Silicon Signature'M*

BUFFERS

-0
CE

OE

PGM

Vpp

(20)

(22)

(27)

(1)

VIL

VIL
VIH
X
VIH
VIL
X
VIL

VIH
Vee
X

X

Vee
Vee
Vee
Vpp
Vpp
Vpp

VIH

Vee

X
VIH
VIL
VIL
VIH
VIL

VIL
VIH

Vee
(28)

Vee
Vee
Vee
Vee
Vee
Vcc
Vee

Outputs
(11-13,15-19)
DOUT
High Z
High Z
DIN
DOUT
High Z
Encoded
Data

X can be either VIL or VIH
~ is toggled, Aa = 12V, and all other addresses are at TTL low.
Silicon Signature is a registered trademark of SEEQ Technology.

* For Silicon Signature:

seeQ
MD400011/-

03

PIN 26 IS A NO CONNECT
ON THE DIP 2764

11O

CONTROL
LOGIC

Mode Selection

~

COLUMN ADDRESS
GATING

Technology, Incorporated

6-83

Pin Names
Ae
AR
CE
OE
00- 0
PGM

7

ADDRESSES - COLUMN (LSB)
ADDRESSES - ROW
CHIP ENABLE
OUTPUT ENABLE
OUTPUTS
PROGRAM

M27641M27128
E27641E27128
Initially, and after erasure, al/ bits are in the "1"
state. Data is programmed by applying 21 V to Vpp
and a TTL "0" to pin 27 (program pin). They may be
programmed with an intelligent algorithm that is
now available on commercial programmers. This
faster time improves manufacturing throughput time
by hours over conventional 50 ms algorithms. Commercial programmers (e.g. Data 110, Pro-log, Digelec,
Kontron, and Stag) have implemented this fast
algorithm for SEEQ's EPROMs. If desired, the 27128

and the 2764 may be programmed using the conventional 50 ms programming specification of older
generation EPROMs.
Incorporated on the 27128 and 2764 is Silicon Signature . Silicon Signature contains encoded data
which identifies SEEQ as the EPROM manufacturer,
and programming information. This data is encoded
in ROM to prevent erasure by ultraviolet light.

Absolute Maximum Ratings
Temperature
Storage ..................... -65 0 C to +1500 C
Under Bias .................. -650 C to +135 0 C
All Inputs or Outputs with
Respect to Ground . ................ +6V to -0.3V
Vpp During Programming with
Respect to Ground ................ +22V to -0.3V
Voltage on Ag with
Respect to Ground .............. +15.5V to -0.3V

'COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at these or any other conditions above those
indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Recommended Operating Conditions
M2764
M27128
Vee Supply Voltage I1I

E2764
E27128

5 V± 10%

Temperature Range (Read Mode)

5 V ± 10%

(Case) -55° to 125°C

(Ambient) -40° to 85°C
21 ± 0.5 V

21 ± 0.5 V

Vpp During Programming

DC Operating Characteristics During Read or Programming
Limits
Symbol

Parameter

Min.

Max.

Unit

Test Conditions

liN

Input Leakage Current

10

p.A

Y,N = Vee Max.

10

Output Leakage Current

10

p.A

VOUT = Vee Max.

Ippl21

Vpp Current

5

rnA

Vpp = Vee Max.

lee1121

Vee Standby Current

lee2121

Vee Active Current

V,L

Input Low Voltage

-0.1

V,H

Input High Voltage

2

VOL

Output Low Voltage

VOH

Output High Voltage

Read Mode
Prog. Mode

(25°C)

30

mA

Vpp = 21.5V

40

rnA

CE= V,H

120

mA

CE= OE= V,L

0.8

V

Vee

+1

0.45
2.4

V
V

10L= 2.1 mA

V

10H = -400 p.A

NOTES:
1. Vee must be applied simultaneously or before Vpp and removed simultaneously or after Vpp.
2. Vpp may be connected directly to Vce except during programming. The supply current is the sum of Icc and Ipp.

seeQ
MD400011/-

Technology, Incorporated

-------------------------------~
6-84

M27641M27128
E27641E27128
AC Operating Characteristics During Read
Limits (nsec)

Symbol

E/M2764-20
E/M27128-20

E/M2764-25
E/M27128-25

E/M2764-35
E/M27128-35

Min.

Min.

Min.

Parameter

tM

Address Access Time

teE

Chip Enable to Data Valid

toE [2]

Output Enable to Data Valid

tDF[3]

Output Enable to Output Float

toH

Output Hold from Chip Enable,
Addresses, or Output Enable,
whichever occurred first

Max.

200
200
75
60

0
0

Max.

0
0

250
250
100
85

Capacitance [1]

0
0

Max.

350
350
125
105

M2764-45

Min.

0
0

Max.

450
450
150
130

Test
Conditions
CE= OE= VIL
OE=VIL
CE= VIL
CE= VIL
CE= OE= VIL

Equivalent A.C. Test Condltions[4]

Symbol

Parameter

Typ.

Max.

Unit

Conditions

CIN

Input Capacitance

4

6

pF

COUT

Output Capacitance

8

12

pF

= OV
VOUT = OV
VIN

Output Load: 1 TTL gate and CL = 100 pF
Input Rise and Fall Times: ::; 20ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs
1 V and 2V
Outputs 0.8V and 2V

A. C. Waveforms
ADDRESSES
VALID

ADDRESSES

OUTPUT __________________~~H~IG~H~Z------~~~~~~

~----------tAA----------~

NOTES:
1. THIS PARAMETER IS SAMPLED AND IS NOT 100% TESTED.
2. OE MAY BE DELAYED T<2-lM - toe AFTER THE FALLING EDGE OF BE WITHOUT IMPACT ON 1M.
3. !oF IS SPECIFIED FROM OE OR
WHICHEVER OCCURS FIRST.
4. THESE ARE EQUIVALENT TEST CONDITIONS AND ACTUAL TEST CONDITIONS ARE DEPENDENT ON THE TESTER.

-ee,

seeQ
MD400011/-

Technology, Incorpotated

6-85

HIGH Z

M27641M27128
E27641E27128
Erasure Characteristics

Silicon Signature is activated by raising address Ag to
12V ± 0.5\1, bringing chip enable and output enable to
a TTL low, having Vee at 5\1, and having all addresses
except AD at a TTL low. The Silicon Signature data is
then accessed by toggling (using TTL) the column
address AD. There are 2 bytes of data available. The
data (see Table 2) appears on outputs 00 to 0 6 , with
0 7 used as an odd parity bit. This mode is functional
at 25° ± 5°C ambient temperature.

The 2764 and 27128 are erased using ultraviolet light
which has a wavelenght of 2537 Angstroms. The
integrated dose, i.e., intensity x exposure time, for
erasure is a minimum of 15 watt-second/cm 2• The
EPROM should be placed within one inch of the
lamp tube during erasure. Table 1 shows the typical
EPROM erasure time for various light intensities.
Table 1. Typical EPROM Erasure Time

Table 2. Silicon Signature Bytes
Light Intensity
(Micro-Watts/cm2)

Erasure Time
(Minutes)

15,000

20

SEE

10,000

30

5,000

55

Product Code (Byte 1)
2764
27128

a

Code (Byte 0)

Ao

Data (Hex)

V1L

94

V 1H
V1H

40
C1

Silicon Signature
Incorporated in SEEQ's EPROMs is a row of mask
programmed read only memory (ROM) cells which is
outside of the normal memory cell array. The ROM
contains the EPROM's Silicon Signature. Silicon Signature contains data which identifies SEEQ as the
manufacturer and gives the product code. Silicon Signature allows programmers to match the programming
specification against the product which is to be programmed. If there is verification, then the programmer
proceeds programming.

seeQ
MD400011/-

Programming
The EPROMs may be programmed using an intelligent
algorithm or with a conventional 50 msec programming pulse. The intelligent algorithm improves the
total programming time by approximately 10 times
over the conventional 50 msec algorithm.
The intelligent algorithm requires Vee =6V and Vpp =
21 V during byte programming. The initial program
pulse width is one millisecond, followed by a sequence of one millisecond pulses. A byte is verified
after each pulse. A single program pulse, with a time
duration equal to 4 times the number of one millisecond pulses applied, is additionally given to the
address after it is verified as being correctly programmed. A maximum of 15 one millisecond pulses
per byte should be applied to each address. When
the intelligent algorithm cycle has been completed,
all bytes must be read at Vee = Vpp = 5V.

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

6-86

M27641M27128
E27641E27128

Intelligent Algorithm F/owcharl

DEVICE
FAILED

DEVICE
FAILED

seeQ
MD400011/-

J

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

6-87

M27641M27128
E27641E27128
Intelligent Algorithm
VERIFY

PROGRAM

VII.
ADDRESSES

~

K

ADDRESS STABLE

~~~~

,
J

DATA

D~TA IN STABLE

\

--

~~~~-

11711111
\\\ \\ \\'

HIGHZ

I
'OH
(2)

~.
DATA OUT

.

-

...-

Vpp
Vpp
Vee

I
~~:)s_

Vee+1
Vee
Vee

I
I---''{gs_

VIH

CE
VIL
L teEs _ _
(2)

VIH

PGM
VIL

VIH

-

~
tpw
(O.95ml)

-

_tOE~
(2)

\

OE
VIL

-

tOPW
(3.8ms)

tOE
-(0.15)-MAX.

--

NOTES:
1. ALL TIMES SHOWN IN ( ) ARE MINIMUM AND IN "SEC UNLESS OTHERWIS!' SPECIFIED.
2. THE INPUT TIMING REFERENCE LEVEL IS .8V FOR A VIL AND 2V FOR A VIH.
3. 'OE AND 'OFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER.

seeQ
MD400011/-

Technology, Incorporated

6-88

..

'AH
(0)

V~LlD
'OFP
(0.13)
MAX.

I+-

1\
~
I+-

M27641M27128
E27641E27128
Intelligent Algorithm

AC Programming Characteristics

TA = 25° ± 5°C, Vee[1,4]

= 6.0V ± 0.25V, Vpp = 21V ± 0.5V
Min.

Limits
Typ.

Max.

Symbol

Parameter

tAS

Address Setup Time

2

jJ.s

tOES

OE Setup Time

2

jJ.s

tos

Data Setup Time

2

jJ.s

tAH

Address Hold Time

0

jJ.s

tOH

Data Hold Time

2

tOFP

Output Enable to Output Float Delay

0

tvps

Vpp Setup Time

2

jJ.s

tves

Vee Setup Time

2

jJ.s

tpw l2j

PGM Initial Program Pulse Width

topw l3 ,41

PGM Overprogram Pulse Width

teEs

CE Setup Time

tOE

Data Valid from OE

0.95

jJ.s
130

1.0

3.8

NOTES:

3. The length
to 63 msec
4. For 50 ms
± 10%, and

ms

63

ms

150

ns

jJ.s

of the overprog ram pulse will vary from 3.8 msec
as a function of the iteration counter value X.
programming, Vee = 5 V ± 5%, Tpw = 50 ms
Topw is not applicable.

Ordering Information

OM

~....---rD
PACKAGE

TEMPERATURE

TYPE

RANGE

D-Cerdip

M--55·C to +125·C
(Military)

IT
27128·25

---"'----

SCREENING OPTION

2764 - 8K x 8 EPROM

20-200 ns

MIL 883 CLASS B

25-250 ns

SCREENED

35-350 ns

45-450 ns

(Extended)

MD400011/-

ACCESS TIME

27128-16K x8 EPROM

E--40·C to +85·C

seeQ

T:L-...-- -

PART TYPE

Technology, Incorporated

6-89

ns

1.05

2

1. Vee must be applied simultaneously or before Vpp and
removed simultaneously or after VPP.
2. Initial Program Pulse width tolerance is 1 msec ± 5%.

Unit

6-90

seeQ

M27C256/E27C256
256K CMOS EPROM
September 1988

Features

Description

• 256K (32K x 8) CMOS EPROM

SEEQ's 27C256 is the industry's first 256K CMOS
EPROM. It has a 32 K x 8 organization and has very
low power dissipation. Its active current is less
than one half the active power of n-channel
EPROMs. In addition the standby current is orders
of magnitude lower than those same EPROMs.
Consequently, system memory sizes can be substantially increased at a very small increase in
power. Low active and standby power is important
in applications which require portability, low
cooling cost, high memory bit density, and long
term reliability.

• Military and Extended Temperature Range
• -55° to +125°C: M27C256
• -40° to +85°C: E27C256
• Ultra Low Power
• 150 pA Max. Vcc Standby Current
• 50 mA Max. Active Current
• Programmed Using Intelligent Algorithm
• 12.5 VVpp
.200 nsAccess Times

The 27C256 is specified over both the extended
and military temperature ranges at 5 V±10% Vcc.
The access time is specified at 200 ns, making the
27C256 compatible with most of today's
microprocessors.
Its inputs and outputs are
completely TTL compatible.

.5 V±1096 Vcc
• JEDEC Approved Bytewide Pin
Configuration
• Silicon Signature®

Pin Configuration

Block Diagram

DUAL IN-LINE

As-Al4

c==>

~

ROW
DECODERS

INDEX
... CORNER

Vcc

MEMORY
ARRAY

II

LEAD LESS CHIP CARRIER
BOTTOM VIEW

c(

Al4
Al3

As
Ag

AS
AS

All

c==>

~

COLUMN
DECODER

--

07

CE

06

07

--u

Mode Selection
CE

OE

Vpp

MODE

(20)

(22)

(1)

Read
Output Disable
Standby
Program
Program Verify
Program Inhibit
Silicon Signature"

VIL
X
VIH
VIL

VIL
VIH
X

Vee
Vee
Vee
Vpp
Vpp
Vpp

VIH
VIH
VIL

AlO

CE
1/0
BUFFERS

CONTROL
LOGIC

~

DE

COLUMN ADDRESS
GATING

VIH
VIL
VIH
VIL

X can be either VIL or VIH.
*For Silicon Signature: Ao is toggled, A9

Vee

= 12 V,

VCC
(28)

Vee
Vee
Vee
Vee
Vee
Vee
Vee

Ao
NC

00

Outputl
(11-13, 15-19)
Dour
High Z
High Z
DIN
Dour
High Z
Encoded
Data

Pin Names
AO - As
A. - A14
CE
OE

ADDRESSES - COLUMN ILSB,
ADDRESSES - ROW
CHIP ENABLE
OUTPUT ENABLE

00-07

OllTPUTS

NC

NO CONNECT

and all other addresses are at a TTL low.

Silicon Signature is a registered trademark of SEEQ Technology.

seeQ
MD400013/A

Technology, Incorporated -

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _...J

6-91

M27C256
E27C256
Incorporated on the 27C256 is Silicon Signature .....
Silicon· Signature contains encoded data which
identifies SEEQ as the EPROM manufacturer and
gives the product code. This data is encoded in
ROM to prevent erasure by ultraviolet light.

Initially, and after erasure, all bits are in the "1"
state. An intelligent algorithm is used to program
the 27C256 typically in four minutes. Data is programmed using a 12.5 V Vpp and an inital chip
enable pulse of 1.0 ms.

Absolute Maximum Ratings
Temperature
Storage ........................ -65°C to +150°C
M27C256 Under Bias ........... -65°C to +135°C
E27C256 Under Bias ............. -50°C to +95°C
AI/Inputs or Outputs with
Respect to Ground ................ +6 V to -0.3 V
Vpp with Respect to Ground ....... +14.0 Vto -0.3 V
Voltage on A9 with
Respect to Ground ............. +14.0 Vto -0.3 V

·COMMENT: Stresses above those listed under "Absolute
Maximum Ratings" may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability.

Recommended Operating Conditions
M27C256-20,
M27C256-25,
M27C256-30

Vcc Supply Voltage l11
Temperature Range (Read Mode)
Vpp During Read l2)

E27C256-20,
E27C256-25,
E27C256-30

5 V± 10%

5 V± 10%

(Case) -55°C to +125°C

(Ambient) -40°C to 85°C

Vpp During Programming[3)

Vcc

Vcc

12.5 ± 0.3 V

12.5 ± 0.3 V

DC Operating Characteristics During Read or Programming
Limits
Symbol
hN(4)

Parameter

Min.

Input leakage

Max.

Unit

1

pA

VIN=VCC Max.

Test Condition

[0(5)

Output leakage

10

pA

VOUT=VCC Max.

[pp

Vpp current:
Standby mode
Read Mode
Programming mode

150
1
30

pA
mA
mA

CE=Vcc-1 v. min.
F=5 MHz., CE=VIL
Vpp=12.5 v.

[cc,

Vcc standby current

150

pA

CE>=Vcc-1 v.

Icc2

Vcc standby current

2

mA

CE=VIH

[CC3

Vcc active current

50

mA

CE=OE=VII., 0 0 - 7 =0,
F=5 MHz.

VIL

[nput low voltage

VIH

Input high voltage

VOL

Output low voltage

VOH

Output high voltage

-0.1
2.0

0.8

V

Vcc+ 1

V

0.45
2.4

V

IOL=2.1 ma

V

IOH=-400 pA.

NOTES:
1. Vcc must be applied simultaneously or before Vpp and removed simultaneously or after VPP.
2. Vpp cannot be left floating and should be connected to Vcc during read.
3.0.1 p.F ceramic capacitor on Vpp is required during programming only, to suppress voltage transients.
4. Inputs only. Does not include I/O.
5. For I/O only.

SeeQ
MD400013/A

Technology, Incorporated - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _---1

6-92

M27C256
E27C256
AC Operating Characteristics During Read
Limits (nsec)
M27C256-20
E27C256-20
Symbol

Min.

Parameter

tM

Address Access Time

tCE

Chip Enable to Data Valid

tOE(2)

Max.
200

M27C256-25
E27C256-25

M27C256-30
E27C256-30

Min.

Min.

Max.
250

Test
Conditions

Max.
300

CE=OE=VIL
OE=VIL

200

250

300

Output Enable to Data Valid

75

100

120

CE=VIL

tDF(3)

Output Enable or Chip Enable to Output Float

60

60

105

CE=VIL

tOH

Output Hold from Chip Enable, Addresses,
or Output Enable whichever occurred first

0

Capacitance{1]
Symbol

Parameter

Typ.

Max.

Unit

Conditions

CIN

Input Capacitance

4

6

pF

VIN = OV

COUT

Output Capacitance

8

12

pF

VOUT = OV

0

0

CE=OE=VIL

Equivalent A. C. Test Conditions{4]
Output Load: 1 TTL gate and C L = 100 pF
Input Rise and Fall Times: :::; 20ns
Input Pulse Levels: 0.45 V to 2.4 V
Timing Measurement Reference Level:
Inputs
1 V and 2V
Outputs O.BV and 2V

A. C. Waveforms
ADDRESSES
VALID

ADDRESSES

HIGH Z

OUTPUT------------------~~------------_+_+_+_+_+_<

~----------tAA----------~

NOTES:
1. THIS PARAMETER IS SAMPLED AND IS NOT 100% TESTED.
2. DE MAY BE DELAYED TO tAr toE AFTER THE FALLING EDGE OF CE WITHOUT IMPACT ON tM
3. tOF IS SPECIFIED FROM DE OR CE, WHICHEVER OCCURS FIRST.
.
4. THESE ARE EQUIVALENT TEST CONDITIONS AND ACTUAL TEST CONDITIONS ARE DEPENDENT ON THE TESTER.

seeQ
MD400013/A

Technology, Incorporated

6-93

HIGH Z

Af27C256
E27C256
Er.sure Ch.r.cterlstlcs
The 2 7C256 is erased using ultraviolet light which
has a wavelength of 2537 Angstroms. The
integrated dose, i.e., intensity x exposure time, for
erasure is a minimum of 15 watt-seconc://cm 2• The
EPROM should be placed within one inch of the
lamp tube during erasure. Table 1 shows the typical
EPROM erasure time for various light intensities.

Table 2. Silicon Signature Bytes

Table 1. Typical EPROM Erasure Time
Light Intensity
(Mlcro-Wattslcm2 )
1-----

Erasure Time
(Minutes)

15,000

20

10,000

30

5,000

55

Silicon Slgn.ture ....
Incorporated in SEEQ's EPROMs is a row of mask
programmed read only memory (ROM) cells which
is outside of the normal memory cell array. The
ROM contains the EPROM's Silicon Signature.
Silicon Signature contains data which identifies
SEEQ as the manufacturer and gives the product
code. This data allow programmers to match the
programming specification against the product
which is to be programmed. If there is verification,
then the programmer proceeds to program.
Silicon Signature is activated by raising address A9 to

seeQ
MD4000131A

12V±O.5V, bringing chip enable and output enable to a TTL low, having Vcc at 5V, and having all
addresses except Ao at a TTL low. The Silicon
Signature data is then accessed by toggling Ao.
The data appears on outputs 0 0 to OS,with 0 7 used
as an odd parity bit (see Table 2).

Data (Hex)

I

I

SEEO Code (Byte Ol

94

Product Code (Byte 1)

C2

Programming
The 27C256 is programmed using the industry
standard intelligent algorithm.
The intelligent algorithm requires Vcc=6 Vand
Vpp= 12.5 V during byte programming. The initial
program pulse width is 1.0 millisecond, followed
by a sequence of 1.0 millisecond pulses. A byte is
verified after each pulse. A single program pulse,
with a time duration equal to 3 times the number
of 1.0 millisecond pulses applied, is additionally
given to the address after it is verified as being
correctly programmed. A minimum of one to a
maximum of 25 1-ms pulses, plus one 3X overpulse, may be applied to each byte. When the
intelligent algorithm cycle has been completed,
all bytes must be read at Vcc=Vpp.=5 V.

Techno'ogy,'ncorporated--------------------------.....J
6-94

M27C256
E27C256
Intelligent Algorithm Flowchart

DEVICE
FAILED

DEVICE
FAILED

seeQ

MD4000131A

Technology, Incorporated

6-95

M27C256
E27C256
Intelligent Algorithm
VERIFY

PROGRAM
V,H
ADDRESSES
V,L

X

K

ADDRESS STABLE

~tA~1
(2)
V,H

D~TA IN STABLE

j

DATA

\

~

i///llll

HIGHZ

II

--

1--- \~~--to

tOH
(2)

\\\\\\\

DATA OUT

/~

(4)

Vee
~t'(;)S _ _

Vee

1

Vee
Vee

,

I
~ ___ t'(;)S_

V,H

CE
~

V,L
-

....

tpw
(0.95 ms)

I---

I--- tOES
(2)

V,H

Vil

-

-I

tOE
(0.15)-MAX.

\

OE

Iopw
(2.85m8)

i---

NOTES:
1. ALL TIMES SHOWN IN ( ) ARE MINIMUM AND IN ",SEC UNLESS OTHERWISE SPECIFIED.
2. THE INPUT TIMING REFERENCE LEVEL IS 0.8 V FOR A VIL AND 2 V FOR A VIH.
3. tOE AND tDFP ARE CHARACTERISTICS OF THE DEVICE BUT MUST BE ACCOMMODATED BY THE PROGRAMMER.
4.0.1 p.F CERAMIC CAPACITOR ON VPf' IS REQUIRED DURING PROGRAMMING ONLY, TO SUPPRESS VOLTAGE TRANSIENTS.

seeQ

MD4000131A

Technology, Incorporated

6·96

V~lIC

-...

I--

Vpp
Vpp

tAH
(0)

~,l

"

tOFP
(0.13)
MAX.

~

1\
l

I--

M27C256
E27C256
Intelligent Algorithm
AC Programming Characteristics TA = 25° ± 5°C, Vcc[ll = 6.0V ± 0.25V. Vpp = 12.5V
Limits
Symbol

Parameter

tAS

Address Setup Time

2

p.S

tOES

rn: Setup Time

2

P.s

Typ.

Min.

Max.

Unit

tos

Data Setup Time

2

P.s

tAH

Address Hold Time

0

P.s

tOH

Data Hold Time

2

tOFP

Output Enable to Output Float Delay

0

tvPS

Vpp Setup Time

2

P.s
130

2

tvcs

Vcc Setup Time

tpw

CE Initial Program Pulse Width

0.95

topw l21

CE Overprogram Pulse Width

2.85

tOE

Data Valid from OE

AC Conditions of Test
InputRiseandFaIlTimes(10%t090%) .... 20ns
Input Pulse Levels . ............. 0.45 V to 2.4 V
Input Timing Reference Level .... 0.8 Vand 2.0 V
Output Timing Reference Level. .. 0.8 Vand 2.0 V

P.s
1.0

1.05

ms

78.75

ms

150

ns

NOTES:
1. Vee must be applied simultaneously or before Vpp and removed
simultaneously or after Vpp.
2. The length of the overprogram pulse will vary from 2.85 msec to
78.75 msec as a function of the iteration counter value X.

Ordering Information

D

L

seeQ

MD400013/A

J

PACKAGE
TYPE

TEMPERATURE
RANGE

O-Cerdlp
L-LCC

M--55·C to +125·C
(Military)
E--40·C to +85·C
(Extended)

TI
M

27C256

25

T

/B

L

PART TYPE

ACCESS TIME

SCREENING OPTION

32Kx8 EPROM

20 - 200 ns
25-250 ns
30-300 ns

MIL 883 CLASS B
SCREENED

Technology, Incorporated

6-97

ns
P.s

6·98

seeQ

82005
MILITARY DRAWING
64K UV EPROM
May 1988

Features

Description

• 82005 Military Drawing Compliant

SEEQ's 82005 is a military drawing compliant,
21-volt programming, 65,532-bit (8192 x 8), ultraviolet erasable EPROM. The 64K EPROM is fabricated and tested in SEEQ Technology's DESCapproved manufacturing facility and has been processed per the requirements of Method 5004/5005
of MIL-STD-883. The 82005 EPROM provides continuing support for applications which utilize a
21-volt programming 64K EPROM in their design.

• Processing Per Method 5004/5005
MIL-STD-883
• 21-Volt Programming
• JEDEC-Approved Bytewide Pin Configuration
• 200 ns Access Time
• MIL-M-38510 Compliant Package Design

Using the 82005 will satisfy MIL-STD-454K which
dictates the use of military drawing parts over 883C
compliant parts if they are available. Furthermore,
designing with standard military drawing devices
eliminates the need for customer-generated source
control drawings, while ensuring the highest level of
device reliability.

• Programmed Using Intelligent Algorithm
• Silicon Signature®

Block Diagram

Pin Configuration
MEMORY
ARRAY

As-A12

Vee
A'2

Ao-A4

COLUMN
DECODER

~_ _--.J"
w__----,/

COLUMN
ADDRESS
GATING

O E - CONTROL
1/0
CE - I ..;L;O;.;G:IC;..i::::~_-_-_-:~t..I.:B;;U~FF~E;R.;;S~

P G M -..

A7

N/C

As

As

As

Ag

A4

A"

A3

OE

A2

A,o

A,

CE

Ao

Mode Selection

~
MODE
Read
Output Disable
Standby
Program
Program Verify
Program Inhibit
Silicon Signature *

00-07

CE
(20)

OE
(22)

PGM
(27)

Vpp

VIL

VIL
VIH

VIH
Vee

X
VIH
VIL
VIL
VIH
VIL

X

X

VIH
VIL

VIL
VIH

X

X

VIL

VIH

07
Os

0,

Vee

OUTPUTS

(1)

(28)

(11-13, 15-19)

Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee

Vee
Vee
Vee
Vee
Vee
Vee
Vee

Dour
High Z
HighZ
DIN
Dour
High Z
Encoded
Data

X can be either VIL or VIH
*For Silicon Signature:

PGM

Ao is toggled, Ag =12V, and all other addresses are at

a TTL low.

Os
°4

0

3

Pin Names
Ao-A4 ADDRESSES-COLUMN
As-A12 ADDRESSES-ROW
CHIP ENABLE
CE
OUTPUT ENABLE
OE
00-0 7 OUTPUTS
PGM
PROGRAM

Silicon Signature is a registered trademark of SEEQ Technology.

seeQ· Technology, Inco'porated--------------------------~
MD400059/-

6-99

82005

MILITARY DRAWING
64KUVEPROM

Description (cont.)

82005 Assembly/Test Flow Chart

The 82005 is manufactured using JEDEC approved
byte wide pinouts and 28-pin package. Access
times as fast as 200 ns eliminate the need for wait
states in high-performance microprocessor systems.
Programming can be accomplished using either the
intelligent algorithm or the 50 mslbyte algorithm
available on commercial programmers.

Screening per MIL-STD-883 Method 5004 and
quality-conformance acceptance per Method 5005
ASSEMBLY AND VISUAL
INSPECTION

Quality-Assurance Provisions
Quality-assurance screening for the 82005 is performed on 100% of the devices in accordance with
Method 5004 of MIL-STD-883. In addition, burn-in
(Method 1015, 125°C min) and data retention bake
are performed on each device after Method 5004
screening and prior to submitting for quality conformance inspection testing.

Quality-Conformance Inspection

ASSEMBLY
ENVIRONMENTAL SCREENS
FINE/GROSS LEAK
CONSTANT ACCELERATION
TEMPERATURE CYCLE

PRE BURN-IN TESTING

Quality-conformance inspection is performed in accordance with Method 5005 of MIL-STD-883. This
includes Group A, Group 8, Group C, and Group D
inspections tests as defined in military drawing
82005. Generic QCI summary data will be provided
upon request.

DYNAMIC BURN-IN
125°C MINIMUM

Electrical Performance Characteristics
The 82005 can be ordered from SEEQ Technology
with device access times =200 ns (82005-07),
250 ns (82005-02), and 450 ns (82005-01). Details
on device specific electrical performance can be
found in the complete DESC 82005 military drawing
or SEEQ's data sheet for generic part type DM2764.
SEEQ's testing meets or exceeds all electrical performance screening and test limits as specified on
the 82005 military drawing.

FINAL ELECTRICAL TESTS

GROUP A TESTING
+25°C, + 125°C, -55°C

MARK, PACK, VISUAL

a.A. LOT ACCEPTANCE
VISUAL/MECHANICAL

a.A. aCI DOCUMENTATION
REVIEW AND ACCEPTANCE

SHIP

seeQ T e c h n o l o g y , l n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - J
MD400059/-

6-100

82005
MILITARY DRAWING
64K UV EPROM

Programming

Erasure Characteristics

The 82005 may be programmed using an interactive
intelligent algorithm or with a conventional 50
mslbyte programming pulse. Use of the intelligent
algorithm improves the total device programming
time by approximately 10 times over the 50 mslbyte
algorithm.

The 82005 is erased by exposure to high-intensity
ultraviolet light with a wave length of 2537 angstroms.
The minimum integrated dose for erasure (i.e.
intensity x exposure time) is 15 watt-second/ cm 2•
The device should be placed within one inch of the
lamp tube during erasure. After erasure, all bits are
in the high state.

To program using the inte/~ent algorithm requires
Vce = 6\1, Vpp = 21 \I, and CE = V,L. The initial programming pulse applied to the PGM pin is one millisecond in duration, followed by a byte verification.
Additional one millisecond program pulses are applied and checked until the byte passes verification.
After verification, an overprogram pulse equal to 4X
the number of one millisecond pulses required to initially program the byte is applied to the address. A
maximum of 15 one millisecond pulses per byte is
allowed. When the intelligent programming cycle
has been completed, all bytes must be read with
Vce =Vpp =5.0 volts to verify correct programming.

Silicon Signature
Incorporated in SEEQ's 82005 EPROM is a row of
mask-programmed read-only memory (ROM) cells,
located outside of the normal memory cell array.
These ROM cells contain the EPROM's Silicon
Signature. Silicon Signature identifies SEEQ as the
manufacturer and gives the device's product code
for programming. This allows the programmer to
match the product to be programmed with the correct programming specification. Once the device
code and programming specification have been
verified, programming of the part can proceed.

Ordering Information
82005

==yDRAWING NUMBER
(8192 x 8 UV EPROM)

01

T

DEVICE TYPE

Y A

S

CASE OUTLINE

Device Type

Generic Number

01

2764-45

450 ns

02

2764-25

250 ns

07

2764-20

200 ns

LEAD FINISH PER
MIL-M-38510

Access Time

Case Outline
Y = D-10 (28 PIN, 112" x 1-3/8"), DUAL-IN-L1NE
PACKAGE

Lead Finish
A=HOT SOLDER DIPPED

seeQ TeChnology,'nCorporated--------------------------.....I
MD400059/-

6-101

6-102

seeQ

82025
MILITARY DRAWING
128K UV EPROM
May 1988

Features

Description

• 82025 Military Drawing Compliant

SEEQ's 82025 is a military drawing compliant,
21-volt programming, 131 ,064-bit (16,384 x 8), ultraviolet erasable EPROM. The 128K EPROM is fabricated and tested in SEEQ Technology's OESCapproved manufacturing facility and has been processed per the requirements of Method 5004/5005
of MIL-STO-883. The 82025 EPROM provides continuing support for applications which utilize a
21-volt programming 128K EPROM in their design.

• Processing Per Method 5004/5005
MIL-STD-883
• 21-Volt Programming
• JEDEC-Approved Bytewide Pin Configuration
• 200 ns Access Time
• MIL-M-38510 Compliant Package Design

Using the 82025 will satisfy MIL-STD-454K which
dictates the use of military drawing parts over 883C
compliant parts if they are available. Furthermore,
designing with standard military drawing devices
eliminates the need for customer-generated source
control drawings, while ensuring the highest level of
device reliability.

• Programmed Using Intelligent Algorithm
• Silicon Signature®

Block Diagram

Pin Configuration
MEMORY
ARRAY

Aa-A13

Vee
A12

AO-As

COLUMN 1'"-----------'"
DECODER \ r - - - - - , /

COLUMN
ADDRESS
GATING

O E - - CONTROL ------~
1/0
CE---~L;O;G;IC~._----.I...B;U~F~F~E~RS;.J
1
PGM---.

Mode Selection

~
MODE
Read
Output Disable
Standby
Program
Program Verify
Program Inhibit
Silicon Signature *

CE
(20)

OE
(22)

PGM
(27)

Vpp
(1)

Vcc
(28)

OUTPUTS
(11-13, 15-19)

VIL

VIL
VIH

VIH
Vee

Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee

Vee
Vee
Vee
Vee
Vee
Vee
Vee

Dour
High Z
High Z
DIN
Dour
High Z
Encoded
Data

X

VIH
VIL
VIL
VIH
VIL

X

X

VIH
VIL

VIL
VIH

X

X

VIL

VIH

X can be either VIL or VIH
*For Silicon Signature:

Ao is toggled, A9= 12V, and all other addresses are at

a TTL low.

PGM

A7

A13

A6

As

As

Ag

A4

All

A3

OE

A2

AID

AI

CE

AD

07

00

06

01

05

02

0 4
0 3

Pin Names
Ao-As ADDRESSES-COLUMN
Aa-A13 ADDRESSES-ROW
CE
CHIP ENABLE
OE
OUTPUT ENABLE
00-07 OUTPUTS
PROGRAM
PGM

Silicon Signature is a registered trademark of SEEa Technology.

seeQ
MD400060/-

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _----J

6-103

82025

MILITARY DRAWING
128K UV EPROM

Description (cont.)

82025 Assembly/Test Flow Chart

The 82025 is manufactured using JEDEC approved
byte wide pinouts and 28-pin package. Access
times as fast as 200 ns eliminate the need for wait
states in high-performance microprocessor systems.
Programming can be accomplished using either the
intelligent algorithm or the 50 ms/byte algorithm
available on commercial programmers.

Screening per MIL-STD-883 Method 5004 and
quality-conformance acceptance per Method 5005
ASSEMBLY AND VISUAL
INSPECTION

Quality-Assurance Provisions
Quality-assurance screening for the 82025 is performed on 100% of the devices in accordance with
Method 5004 of MIL-STD-883. In addition, burn-in
(Method 1015, 125°C min) and data retention bake
are performed on each device after Method 5004
screening and prior to submitting for quality conformance inspection testing.

Quality-Conformance Inspection

ASSEMBLY
ENVIRONMENTAL SCREENS
FINE/GROSS LEAK
CONSTANT ACCELERATION
TEMPERATURE CYCLE

PRE BURN-IN TESTING

Quality-conformance inspection is performed in accordance with Method 5005 of MIL-STD-883. This
includes Group A, Group B, Group C, and Group D
inspections tests as defined in military drawing
82025. Generic QCI summary data will be provided
upon request.

Electrical Performance Characteristics
The 82025 can be ordered from SEEQ Technology
with device access times = 200 ns (82025-08),
250 ns (82025-02), 300 ns (82025-09), and 450 ns
(82025-01). Details on device specific electrical performance can be found in the complete DESC 82025
military drawing or SEEQ's data sheet for generic part
type DM27128. SEEQ's testing meets or exceeds all
electrical performance screening and test limits as
specified on the 82025 military drawing.

DYNAMIC BURN-IN
125°C MINIMUM

FINAL ELECTRICAL TESTS

GROUP A TESTING
+25°C, +125°C, -55°C

MARK, PACK, VISUAL

a.A. LOT ACCEPTANCE
VISUAL! MECHANICAL

a.A. aCI DOCUMENTATION
REVIEW AND ACCEPTANCE

SHIP

seeQ T e c h n o l o g y . l n c o r p o r 8 t e d - - - - - - - - - - - - - - - - - - - - - - - - - . . . . J
MD400060/-

6-104

82025

MILITARY DRAWING
128K UV EPROM

Programming

Erasure Characteristics

The 82025 may be programmed using an interactive
intelligent algorithm or with a conventional 50
ms/byte programming pulse. Use of the intelligent
algorithm improves the total device programming
time by approximately 10 times over the 50 ms/byte
algorithm.

The 82025 is erased by exposure to high-intensity
ultraviolet light with a wave length of 2537 angstroms.
The minimum integrated dose for erasure (i. e.
intensity x exposure time) is 15 watt-second/cm 2•
The device should be placed within one inch of the
lamp tube during erasure. After erasure, all bits are
in the high state.

To program using the intellfILent algorithm requires
Vce = BV, Vpp = 21 V, and CE = V,L. The initial programming pulse applied to the PGM pin is one millisecond in duration, fOllowed by a byte verification.
Additional one millisecond program pulses are applied and checked until the byte passes verification.
After verification, an overprogram pulse equal to 4X
the number of one millisecond pulses required to initially program the byte is applied to the address. A
maximum of 15 one millisecond pulses per byte is
allowed. When the intelligent programming cycle
has been completed, all bytes must be read with
Vee = Vpp =5.0 volts to verify correct programming.

Silicon Signature
Incorporated in SEEQ's 82025 EPROM is a row of
mask-programmed read-only memory (ROM) cells,
located outside of the normal memory cell array.
These ROM cells contain the EPROM's Silicon
Signature. Silicon Signature identifies SEEQ as the
manufacturer and gives the device's product code
for programming. This allows the programmer to
match the product to be programmed with the correct programming specification. Once the device
code and programming specification have been
verified, programming of the part can proceed.

Ordering Information

DRAWING NUMBER
(16,384 x 8 UV EPROM)

Y A

01

82025

=r

T

DEVICE TYPE

S

CASE OUTLINE

Device Type

Generic Number

Access Time

01

27128-45

450 ns

02

27128-25

250 ns

08

27128-20

200 ns

09

27128-30

300 ns

LEAD FINISH PER
MIL-M-38510

Case Outline
Y = 0-10 (28 PIN, 112" x 1-3/8"), DUAL-IN-LlNE
PACKAGE
Lead Finish
A = HOT SOLDER DIPPED

seeQ
MD4000601-

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - -

6-105

6-106

seeQ

86063
MILITARY DRAWING
256K CMOS UV EPROM
May 1988

Features

Description

• 86063 MIlitary Drawing Compliant

SEEQ's 86063 Is a military drawing compliant,
262, 144-blt (32,768 x 8), ultr.vio/et erasable CMOS
EPROM. The 256K EPROM Is fablcated and tested
in SEEQ Technology's DESC-approved manufacturing facility and has been processed per the requirements of Method 5004/5005 of MIL-STD-883. It's
CMOS design draws less than one-haN the active
current and several orders of magnitude less standby current than the equivalent density N-channel
EPROMS.

• Processing Per Method 5004/5005
MIL-STD-883
• Low Power CMOS
• JEDEC-Approved Brtewlde Pin Configuration

• 200 ns Access Time
• MIL-Af..38510 Compliant Package Design
• Programmed Using Intelligent AlgOrithm

Pin Configuration

• Silicon Signature@

Dual-In-Line

Pin Names
AcrAs
Ae-A14

CE
~

00-07
NC

At3
As

A4

Att

A3

C5E

A2

AID

CE
07
Os

Os
04
03

COLUMN 1 " - - - - - ' ' \
DECODER:SIr------,/
CONTROL
LOGIC

28

As

MEMORY
ARRAY

CS!-

Vee

At4

A5

Block Diagram

~-

1

2
3

A7

ADDRESSES-COLUMN
ADDRESSES-ROW
CHIP ENABLE
OUTPUT ENABLE
OUTPUTS
NO CONNECT

AO-AS

Vpp

Au

.----1

Leadless Chip Carrier
Bottom View

COLUMN
ADDRESS
GATING
1/0
BUFFERS

00-07
Silicon Signature is a registered trademark of SEEa Technology.

L...-E;E~~(~TKh~"/~~~-------------------------------------------------~
MD400081/-

6-107

86063

MILITARY DRAWING
256K CMOS UV EPROM

Description (cont.)

86063 Assembly/Test Flow Chart

The 86063 is manufactured using JEDEC approved
byte wide pinouts for both the 28-pin dua/-in-line and
32-pin leadless chip carrier packages. Access times
as fast as 200 ns eliminate the need for wait states in
high-performance microprocessor systems. Device
programming is accomplished using the interactive
intelligent algorithm available on commercial
programmers.

Screening per MIL-STD-883 Method 5004 and
quality-conformance acceptance per Method 5005
ASSEMBLY AND VISUAL
INSPECTION

Using the 86063 will satisfy MIL-STD-454K which
dictates the use of military drawing parts over 883C
compliant parts if they are available. Furthermore,
designing with standard military drawing devices
eliminates the need for customer-generated source
control drawings, while ensuring the highest level of
device reliability.

ASSEMBLY
ENVIRONMENTAL SCREENS
FINE/GROSS LEAK
CONSTANT ACCELERATION
TEMPERATURE CYCLE

Quality-Assurance Provisions
PRE BURN-IN TESTING

Quality-assurance screening for the 86063 is performed on 100% of the devices in accordance with
Method 5004 of MIL-STD-883. In addition, burn-in
(Method 1015, 125°C min) and data retention bake
are performed on each device after Method 5004
screening and prior to submitting for quality conformance inspection testing.

DYNAMIC BURN-IN
125°C MINIMUM

Quality-Conformance Inspection

FINAL ELECTRICAL TESTS

Quality-conformance inspection is performed in accordance with Method 5005 of MIL-STD-883. This
includes Group A, Group B, Group C, and Group D
inspections tests as defined in military drawif]g
86063. Generic QCI summary data will be provided
upon request.

GROUP A TESTING
+25°C, + 125°C, -55°C

MARK, PACK, VISUAL

Mode Selection
MODE
~
Read
Output Disable
Standby
Program
Program Verify
Program Inhibit
Silicon Signature *

CE

OE

vpp

Vee

OUTPUTS

VIL
VIL
VIH
VIL
VIH
VIH
VIL

VIL
VIH

Vee
Vee
Vee
Vpp
Vpp
Vpp
Vee

Vee
Vee
Vee
6.0V
6.0V
6.0V
Vee

Dour
High Z
High Z
DIN
Dour
High Z
Encoded
Data

X
VIH
VIL
VIH
VIL

X can be either VIL or VIH
* For Silicon Signature: Ao is toggled, A9= 12V, and all other
addresses are at a TTL low.

seeQ

a.A. LOT ACCEPTANCE
VISUAL/MECHANICAL

a.A. aCI DOCUMENTATION
REVIEW AND ACCEPTANCE

SHIP

Technology, Incorporated - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _..J

MD400061/-

6-108

86063
MILITARY DRAWING
256K CMOS UV EPROM

Electrical Performance Characteristics

Erasure Characteristics

The 86063 can be ordered from SEEQ Technology
with device access times = 200 ns (86063-01), 250
ns (86063-02), and 300 ns (86063-03). Details on
device specific electrical performance can be found in
the complete DESC 86063 military drawing or SEEQ's
data sheet for generic part type DM27C256. SEEQ's
testing meets or exceeds all electrical performance
screening and test limits as specified on the 86063
military drawing.

The 86063 is erased by exposure to high-intensity
ultraviolet light with a wave length of 2537 angstroms.
The minimum integrated dose for erasure (i.e.
intensity x exposure time) is 15 watt-second/ cm 2•
The device should be placed within one inch of the
lamp tube during erasure. After erasure, all bits are
in the high state.

Silicon Signature
Incorporated in SEEQ's 86063 EPROM is a row of
mask-programmed read-only memory (ROM) cells,
located outside of the normal memory cell array.
These ROM cells contain the EPROM's Silicon
Signature. Silicon Signature identifies SEEQ as the
manufacturer and gives the device's product code
for programming. This allows the programmer to
match the product to be programmed with the correct programming specification. Once the device
code and programming specification have been
verified, programming of the part can proceed.

Programming
To program the 86063 using the intelligent algorithm
requires Vee =6V, Vpp= 12.5V, and DE =V,H. The initial
programming pulse applied to the CE pin is one
millisecond in duration, followed by a byte verification.
Additional one millisecond program pulses are applied and checked until the byte passes verification.
After verification, an overprogram pulse equal to 3X
the number of one millisecond pulses required to initially program the byte is applied to the address. A
maximum of 25 one millisecond pulses per byte is
allowed. When the intelligent programming cycle
has been completed, all bytes must be read with
Vee = Vpp =5.0 volts to verify correct programming.

Ordering Information

01

86063

=r
DRAWING NUMBER
(32,768 x 8 UV EPROM)

T

DEVICE TYPE

X

S

A

CASE OUTLINE

Device Type

Generic Number

Access Time

01

27C256-20

200 ns

02

27C256-25

250 ns

03

27C256-30

300 ns

LEAD FINISH PER
MIL-M-38510

Case Outline
X = 0-10 (28 PIN, 112" x 1-3/8"), DUAL-IN-LiNE
PACKAGE
Y = C-12 (32 TERMINAL, .450 x .550"),
RECTANGULAR CHIP CARRIER PACKAGE
Lead Finish
A = HOT SOLDER DIPPED
C=GOLD PLATE

seeQ
MD400061/·

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - -.....

6·109

6-110

seeQ

ElM 48F512
512K CMOS FLASHTM EEPROM

ADVANCE DATA SHEET

October 1988

Features
•
•
•
•

•
•
•
•

•

Block Diagram

64K Byte FLASH Erasable Non-Volatile Memory
FLASH EEPROM Cell Technology
Electrical Chip and 512 Byte Sector Erase
Input Latches for Writing and Erasing
-55° C to + 125° C Temp Read (M48F512)
-55°C to +85°C Temp Write!Erase (M48F512)
-400 C to + 85° C Temp Read! Write! Erase
(E48F512)
Ideal for Program and Data Storage Applications
• Minimum 100 Cycle Endurance
• Optional 1000 Cycle Endurance
• Minimum 10 Year Data Retention
Silicon Signature@

Ag-A1S

AO-AS

CE
WE

~rrr--..~~--"""·

Pin Names
Ao-As

COLUMN ADDRESS INPUT

Ag-A15

ROW ADDRESS INPUT

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/00.7

1/00-7

DATA INPUT (WRITE)/OUTPUT (READ)

N.C.

NO INTERNAL CONNECTION

Vpp

WRITE/ERASE INPUT VOLTAGE

D.U.

DON'T USE

PLASTIC LEADED CHIP
CARRIER TOP VIEW

Pin Configurations

LEADLESS CHIP CARRIER
TOP VIEW

DUAL-IN-LINE
TOP VIEW
Vee
NC

WE
NC

A12

seeQ
MD400068/-

Silicon Signature is a registered trademark
of SEEQ Technology.
FLASH is a trademark of SEEQ Technology.

A14

A7

A13

Ae

As

As

Ag

A4

All

A3

OE

A2

Al0

Al

CE

Ao

1/07

1/00

I/0e

1/01

1/05

1/02

1/04

Vss

1/03

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

6-111

ElM 48F512
ADVANCE DATA SHEET

Description
The M48F512 is a 512K bit CMOS FLASH EEPROM
organized as 64K x 8 bits. SEEQ's M48F512 brings
together the high density and cost effectiveness of
UVEPROMs, with the electrical erase, in-circuit reprogrammability and package options of EEPROMs.
On-chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to
perform other tasks once write/erase/read cycles
have been initiated. The memory array is divided into
128 sectors, with each sector containing 512 bytes.
Each sector can be individually erased, or the chip
can be bulk erased before reprogramming.
Endurance, the number of times each byte can be
written, is specified at 100 cycles with an optional
screen for 1000 cycles available. Electrical write/
erase capability allows the M48F512 to accommodate a wide range of plastic, ceramic and surface
mount packages.

Read
Reading is accomplished by presenting a valid address
with chip enable and output enable at v'v write enable
at V,H, and Vpp at any level. See timing waveforms for
A. C. parameters.

Erase and Write
Latches on address, data and control inputs permit
erasing and writing using normal microprocessor
bus timing. Address inputs are latched on the falling
edge of write enable or chip enable, whichever is
later; while data inputs are latched on the rising edge
of write enable or chip enable, whichever is earlier:
The write enable input is noise protected; a pulse of
less than 20 ns. will not initiate a write or erase. In
addition, chip enable, output enable and write enable
must be in the proper state to initiate a write or
erase. Timing diagrams depict write enable controlled writes; the timing also applies to chip enable
controlled writes.

Sector Erase
Sector erase changes all bits in a sector of the array
to a logical one. It requires that the Vpp pin be brought
to a high voltage and a write cycle performed. The
sector to be erased is defined by address inputs Ag
through A 15' The data inputs must be all ones to
begin the erase. Following a write of 'FF', the part will
wait for time tabort to allow aborting the erase by
writing again. This permits recovering from an unintentional sector erase if, for example, in loading a

block of data a byte of 'FF' was written. After the
tabort delay, the sector erase will begin. The erase is
accomplished by following the erase algorithm in
figure 2. Vpp can be brought to any TTL level or left at
high voltage after the erase.

Chip Erase
Chip erase changes all bits in the memory to a logical one. Refer to figure 3 for the chip erase algorithm.
Vpp can be brought to any TTL level or left at high
voltage after the erase.

Sector and Chip Erase Algorithm
To reduce the sector and chip erase times, a software erase algorithm is used. Refer to figures 2 and
3 for the sector erase and chip erase flow charts.

Byte Write
A byte write is used to change any 1 in a byte to a O.
To change a bit in a byte from a 0 to a 1, the byte
must be erased first via either sector erase or chip
erase.
Data are organized in the M48F512 in a group of bytes
called a sector: The memory array is divided into
128 sectors of 512 bytes each. Individual bytes are
written as part of a sector write operation. The programming algorithm for either chip or sector write is
detailed in figure 1.
Sectors are written by applying a high voltage to the
Vpp pin and writing individual non-FF bytes in sequential order: Each byte write is automatically latched
on-chip, so that the user can do a normal microprocessor write cycle and then wait a minimum of twe
ns.. fo~ the self-timed write to complete. Each byte
write Incrementally programs bits that are to become
a zero. A write loop has been completed when all
non-FF data for all desired sectors have been written.
After 15 loops, a read-verification is performed. For
any bytes which do not verify, a fill-in programming
loop is performed. Sectors need not be written separately; the entire device or any combination of blocks
can be written using the write algorithm.
Because bytes can only be written as part of a sector write, if data is to be added to a partially written
sector or one or more bytes in a sector must be
changed, the contents of the sector must first be
read into system RAM; the bytes can then be added
to the block of data in RAM and the sector written
using the sector write algorithm.

seeQ Technology, I n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - . . J
MD400068/-

6-112

ElM 48F512
ADVANCE DATA SHEET

Power Up/Down Protection
These two devices contain a Vcc sense circuit which

Silicon Signature

disables internal erase and write operations when
Vcc is below 3.5 volts. In addition, erases and writes
are prevented when any control input (CE, OE, WE) is
in the wrong state for writing or erasing (see mode
table).

contains the device's Silicon Signature. Silicon Signature contains data which identifies Seeq as the
manufacturer and gives the product code. This allows
device programmers to match the programming
specification against the product which is to be
programmed.
Silicon Signature is read by raising address Ag to 12
± 0.5 V. and bringing all other address inputs plus
chip enable and output enable to v,L with Vcc at 5 V.
The two Silicon Signature bytes are selected by
address input Ao. Silicon Signature is functional at
room temperature only (25°G.)

High Voltage Input Protection
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification which
must not be exceeded, even briefly, or permanent
device damage may result. To minimize switching
transients on this pin we recommend using a minimum O. 1 uf decoupling capacitor with good high
frequency response connected from Vpp to ground
at each device. In addition, sufficient bulk capacitance should be provided to minimize Vpp voltage
sag when a device goes from standby to a write or
erase cycle.

A row of fixed ROM is present in the M48F512 which

Silicon Signature Bytes
Ao

Data (Hex)

SeeqCode

VIL

94

Product code M48F512

VIH

1A

Mode Selection Table
MODE

CE

OE

WE

Vpp

A9-15

Ao-a

1100-7

Read

VIL

VIL

VIH

X

Address

Address

Standby

VIH

X

X

X

X

X

Dour
HI-Z
DIN

Byte write

VIL

VIH

VIL

Vp

Address

Address

Chip erase select

VIL

VIH

VIL

TTL

X

X

X

Chip erase

VIL

VIH

VIL

Vp

X

X

'FF'

Sector erase

VIL

VIH

VIL

Vp

Address

X

'FF'

Absolute Maximum Stress Ratings
Temperature:
Storage . ................ .
Under bias . ............. .

E.S.D. Characteristics[1]
-65°C to + 150°C
-65°C to + 135°C

All Inputs except Vpp and
outputs with Respect to Vss. . .

+7Vto-0.5V

Vpp pin with respect to Vss. . . .

14 V

seeQ
MD400068/-

Symbol Parameter

VZAP

E.S.D. Tolerance

Value

Test Conditions

>2000 V MIL-STD883
Method 3015

Note 1: Characterization data-not tested.

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _- - - J

6-113

ElM 48F512
ADVANCE DATA SHEET

Recommended Operating Conditions

Capacitance[2] TA=25°C, f=1

M48F512

E48F512

Symbol Parameter

Vcc supply voltage

5V± 10%

5V± 10%

CIN

Input capacitance

Temperature range
(read mode)

-55°C to
+125°C

-40°C to
+85°C

COUT

Output capacitance

Temperature range
(write/erase mode)

-55°C to
+85°C

-40°C to
+85°C

MHz

Value
6 pt.
12 pt.

Test Conditions
VIN=OV
VI/O=OV

Note 2: Only performed for initial qualification and after any design
or process change which could affect parameter limits.

DC Operating Characteristics
Over the Vcc and temperature range

Limits
Min.

Test Conditions

Symbol

Parameter

Max.

Unit

IIH

Input leakage high

1

/-LA

VIN=VCC

IlL

Input leakage low

-1

/-LA

VIN = 0.1 V

IOL

Output leakage

10

/-LA

VIN = Vee

Vp

Program/erase voltage

11.75

13

V

VPR

Vpp Voltage during read

0

Vp

V

Ipp

Vp current
Standby mode
Read mode
Byte write
Erase

200
200
50
90

lec1

Standby Vee current

lec2

Standby Vee current

lec3

Active Vcc current-

VIL

Input low voltage

-0.3

V IH

Input high voltage

2.0

VOL

Output low voltage

VO H1

Output level (TTL)

VOH2

Output level (CMOS)

seeQ
MD400068/-

/-LA
/-LA
mA
mA

CE = VIH, Vpp = Vp
CE = VIL, Vpp = Vp
Vpp=Vp
Vpp=Vp

400

/-LA

CE

5

mA

CE -VIH min.

100

mA

CE=VIL

0.8

= Vee -0.3 v

V

7.0

V

0.45

V

IOL = 2.1 ma

2.4

V

IOH

Vce-0.4

V

IOH = -100/-LA

= -400/-LA

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - ' "

6-114

ElM 48F512

ADVANCE DATA SHEET

AC Characteristics

READ

(over the Vcc and temperature range)

ElM48F512
·250
Symbol

Parameter

Min.

tRC

Read cycle time

250

tAA

Address to data

teE
toE

'CEtodata

Max.

OE/CE to data float

toH

Output hold time

Min.

Max.

300
250
250
100
60

OEtodata

tOF

ElM48F512
·300

0

ns

300
300
150
100
0

Read Timing

Unit

ns
ns
ns
ns
ns

__

~J:=-:
~_-_tR_C---=---=----==:*

11'...--=--=-------_---tAA---~:::::::.-,- - - - - - - - - - - - ' - - - - - - - -

oJ

ADDRESS - - - 1/0

0-7

----------<-----l~--------_'r'----}-I-----

WE

I

AC Test Conditions
Output load: 1 TTL gate and C(load) 100 pf.
Input rise and fall times: < 20 ns.
Input pulse levels: 0.45 V to 2.4 V
Timing measurement reference level:
Inputs 1 Vand 2 V
Outputs 0.8 Vand 2 V

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD4000681-

6·115

ElM 48F512
ADVANCE DATA SHEET

BYTE WRITE

AC Characteristics
(Over the Vcc and temperature range)

ElM48F512
Symbol

Parameter

Min.

tvPS

Vpp setup time

tVPH

Vpp hold time

tcs

CE setup time

tcH

~holdtime

toES

OEsetuptime

toEH

OEholdtime

tAS

Address setup time

tAH

Address hold time

tos

Data setup time

toH

Data hold time

twp

WE pulse width

twc

Write cycle time

2
250
0
0
10
10
50
100
50
20
150
100

tWA

Write recovery time

Max.

Unit

f..Ls
f..Ls
ns
ns
ns
ns
ns
ns
ns
ns
ns

150
2.0

f..LS
ms

Byte Write Timing

Vpp

~~

ADDRESS

1/00-7

__ ____ _____x______
~~

~~

_ _ _01

~---twR---~

~--------twc--------~

BYTE WRITE - - - - + \
BYTE #1

BYTE WRITE
BYTE #2

BYTE WRITE
LAST BYTE

Note: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the user must
provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device, e.g., access time,
erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.

seeQ Technology, Incorporated
MD4000681-

6-116

ElM 48F512
ADVANCE DATA SHEET

Figure 1
EIM48F512 Write Algorithm

SETVpp=Vp
WAIT Tvps
LOOP_COUNT=1

RE-WRITE
BYTE
WAITTwc/-LS

SET ADDRESS
1 ST LOCATION

RE-WRITE BYTE
WAIT
Twc+ Twr/-LS

SET ADDRESS
1 ST LOCATION

WRITE BYTE
WAITTwc/-LS
INC. ADDRESS

INCREMENT
ADDRESS

YES

INCREMENT
LOOP_COUNT

NO

INCREMENT
LOOP_COUNT

WAITTwr/-LS
LOOP_COUNT=1

NO

YES

M=15
N=6

SeeQ Technology, Incorporated
MD400068/-

END

6-117

DEVICE
FAILED

ElM 48F512
ADVANCE DATA SHEET

AC Characteristics

SECTOR ERASE

(Over the Vee and temperature range)

ElM48F512
Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

2
500
0
0
50
100
50
20
150
0
0

tcs

CE setup time

tOES

OE setup time

tAS

Address setup time

tAH

Address hold time

tDS

Data setup time

tDH

Data hold time

twp

WE pulse width

tcH

CE hold time

tOEH

OE hold time

tERASE

Sector erase time

tABORT

Sector erase delay

tER

Erase recovery time

Max.

Unit

f..Ls
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns

500
250
500

ms

f..Ls
ms

Sector Erase Timing
Vp
1-------tVPH-------..I'r---------

ROW
ADDRESSES _ _ _ _ _ _~~~__-H_ _ _ _ _~~'~--~~------J~------~----'~------

1/00-7

OE

WE

--------~

-------+-'
_ __ J

I..-----tERASE-------l.-l

seeQ
MD4000681-

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

6-118

ElM 48F512
ADVANCE DATA SHEET

Figure 2
EIM4BF512 Sector Erase Algorithm

WRITEFF
TO SECTOR
ADDRESS

INCREMENT
LOOP_COUNT

VERIFY ALL
SECTOR
BYTES=FF

DEVICE FAILED

L=60

seeQ Technology, Incorporated
MD4000681-

6-119

ElM 48F512
ADVANCE DATA SHEET

AC Characteristics

CHIP ERASE

(Over the Vcc and temperature range)
E/M48F512
Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

tcs

CE setup time

tOES

OE setup time

tos

Data setup time

2
500
0
0
50
20
150
0
0

tOH

Data hold time

twp

WE pulse width

tCH

CE hold time

tOEH

OE hold time

tERASE

Chip erase time

tER

Erase recovery time

Max.

Unit

f..Ls
ms
ns
ns
ns
ns
ns
ns
ns

500
500

ms
ms

Chip Erase Timing

VIH

Vpp
~---tVPH---~

1/00-7

CE

OE

WE

seeQ
MD4000681-

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

6-120

ElM 48F512
ADVANCE DATA SHEET

Figure 3
EIM48F512 Chip Erase Algorithm

WRITEFF
TO ANY
ADDRESS

WRITEFF
TO ANY
ADDRESS

INCREMENT
LOOP_COUNT

WAITtERmS
THEN VERIFY
ALL BYTES=FF

DEVICE FAILED

L=60

seeQ Technology, Incorporated -------------------------~
MD4000681-

6-121

Ordering Information
D

T

Package
Type
D = Ceramic Dip
L = Ceramic
Leadless Chip
Carrier

M

T

Temperature
Range
E = -40 to +85°C

48F512

T

K

-250

T T

/B

T

Device

Endurance

Access
Time

Screening

64Kx8 FLASH
EEPROM

Blank = 100

250 = 250ns

MIL 883 Class
B Screened
(Optional)

K= 1000

300 = 300ns

M = -55 to +125°C
(Read)
-55 to +85°C
(Write/Erase)

N = Plastic Leaded

Chip Carrier
(-40 to +85°C
Temp Range
Only)

seeQ Technology, Incorporated - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

--1

MD4000681-

6-122

seeQ

ElM 48F010
1024K CMOS FLASHTM EEPROM

ADVANCE DATA SHEET

October 1988

Features
•
•
•
•

128K Byte FLASH Erasable Non-Volatile Memory
FLASH EEPROM Cell Technology
Electrical Chip and 1024 Byte Sector Erase
Input Latches for Writing and Erasing
• -55°C to + 125°C Temp Read (M48F010)
• -55°C to +85°C Temp Write/Erase (M48F010)
• -400 C to + 85° C Temp Read/ Write/ Erase
(E48F010)

Block Diagram

Ao-Ag

• Ideal for Program and Data Storage Applications
• Minimum 100 Cycle Endurance
• Optional 1000 Cycle Endurance
• Minimum 10 Year Data Retention
• Silicon Signature@

CE
WE

~ITT~~"~-'"''''

Pin Names
Ao-Ag

COLUMN ADDRESS INPUT

A1O- A16

ROW ADDRESS INPUT

CE

CHIP ENABLE

OE

OUTPUT ENABLE

WE

WRITE ENABLE

1/°0·7

1/00 - 7

DATA INPUT (WRITE)/OUTPUT (READ)

N.C.

NO INTERNAL CONNECTION

Vpp

WRITE/ERASE INPUT VOLTAGE

D.U.

DON'T USE

PLASTIC LEADED CHIP
CARRIER TOP VIEW

Pin Configurations

LEAD LESS CHIP CARRIER
TOP VIEW

DUAL-IN-LiNE
TOP VIEW
Vpp

Vee

A1S

WE
Ne

A1S

seeQ

Silicon Signature is a registered trademark
of SEEQ Technology.
FLASH is a trademark of SEEQ Technology.

A12

A14

A7

A13

As

As

As

Ag

A4

All

Aa

OE

A2

Al0

Al

CE

Ao

1/07

1100

1I0s

1/01

1105

1/02

1/04

Vss

110 3

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - '

MD400069/-

6-123

ElM 48F010

ADVANCE DATA SHEET

Description
The M48F010 is a 1024K bit CMOS FLASH EEPROM
organized as 128K x 8 bits. SEEQ's M48FO 10 brings
together the high density and cost effectiveness of
UVEPROMs, with the electrical erase, in-circuit reprogrammability and package options of EEPROMs.
On-chip latches and timers permit simplified microprocessor interface, freeing the microprocessor to
perform other tasks once write/erase/read cycles
have been initiated. The memory array is divided into
128 sectors, with each sector containing 1024 bytes.
Each sector can be individually erased, or the chip
can be bulk erased before reprogramming.
Endurance, the number of times each byte can be
written, is specified at 100 cycles with an optional
screen for 1000 cycles available. Electrical write/
erase capability allows the M48F010 to accommodate a wide range of plastic, ceramic and surface
mount packages.

Read
Reading is accomplished by presenting a valid address
with chip enable and output enable at \.'Iv write enable
at \.'IH, and Vpp at any level. See timing waveforms for
A. C. parameters.

Erase and Write
Latches on address, data and control inputs permit
erasing and writing using normal microprocessor
bus timing. Address inputs are latched on the falling
edge of write enable or chip enable, whichever is
later, while data inputs are latched on the rising edge
of write enable or chip enable, whichever is earlier:
The write enable input is noise protected; a pulse of
less than 20 ns. will not initiate a write or erase. In
addition, chip enable, output enable and write enable
must be in the proper state to initiate a write or
erase. Timing diagrams depict write enable controlled writes; the timing also applies to chip enable
controlled writes.

Sector Erase
Sector erase changes all bits in a sector of the array
to a logical one. It requires that the Vpp pin be brought
to a high voltage and a write cycle performed. The
sector to be erased is defined by address inputs A 10
through A 16. The data inputs must be aI/ ones to
begin the erase. Following a write of 'FF', the part will
wait for time tabort to allow aborting the erase by
writing again. This permits recovering from an unintentional sector erase if, for example, in loading a

block of data a byte of 'FF' was written. After the
tabort delay, the sector erase will begin. The erase is
accomplished by fol/owing the erase algorithm in
figure 2. Vpp can be brought to any TTL level or left at
high voltage after the erase.

Chip Erase
Chip erase changes all bits in the memory to a logical one. Refer to figure 3 for the chip erase algorithm.
Vpp can be brought to any TTL level or left at high
voltage after the erase.

Sector and Chip Erase Algorithm
To reduce the sector and chip erase times, a software erase algorithm is used. Refer to figures 2 and
3 for the sector erase and chip erase flow charts.

Byte Write
A byte write is used to change any 1 in a byte to a O.
To change a bit in a byte from a 0 to a 1, the byte
must be erased first via either sector erase or chip
erase.
Data are organized in the M48FO 10 in a group of bytes
called a sector: The memory array is divided into
128 sectors of 1024 bytes each. Individual bytes are
written as part of a sector write operation. The programming algorithm for either chip or sector write is
detailed in figure 1.
Sectors are written by applying a high voltage to the
Vpp pin and writing individual non-FF bytes in sequential order: Each byte write is automatically latched
on-chip, so that the user can do a normal microprocessor write cycle and then wait a minimum of t~
ns. for the self-timed write to complete. Each byte
write incrementally programs bits that are to become
a zero. A write loop has been completed when al/
non-FF data for all desired blocks have been written.
After 15 loops, a read-verification is performed. For
any bytes which do not verify, a fill-in programming
loop is performed. Sectors need not be written separately; the entire device or any combination of blocks
can be written using the write algorithm.
Because bytes can only be written as part of a sector write, if data is to be added to a partially written
sector or one or more bytes in a sector must be
changed, the contents of the sector must first be
read into system RAM; the bytes can then be added
to the block of data in RAM and the sector written
using the sector write algorithm.

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

...J

MD400069/-

6-124

ElM 48F010
ADVANCE DATA SHEET

Power Upl Down Protection

Silicon Signature

These two devices contain a Vcc sense circuit which
disables internal erase and write operations when
Vcc is below 3.5 volts. In addition, erases and writes
are prevented when any control input (GE, OE, WE) is
in the wrong state for writing or erasing (see mode
table).

A row of fixed ROM is present in the M48FO 10 which
contains the device's Silicon Signature. Silicon Signature contains data which identifies Seeq as the
manufacturer and gives the product code. This allows
device programmers to match the programming
specification against the product which is to be
programmed.
Silicon Signature is read by raising address Ag to 12
± 0.5 V. and bringing all other address inputs plus
chip enable and output enable to 'ltL with Vcc at 5 V.
The two Silicon Signature bytes are selected by
address input Ao. Silicon Signature is functional at
room temperature only (25°G.)

High Voltage Input Protection
The Vpp pin is at a high voltage for writing and erasing.
There is an absolute maximum specification which
must not be exceeded, even briefly, or permanent
device damage may result. To minimize switching
transients on this pin we recommend using a minimum 0.1 uf decoupling capacitor with good high
frequency response connected from Vpp to ground
at each device. In addition, sufficient bulk capacitance should be provided to minimize Vpp voltage
sag when a device goes from standby to a write or
erase cycle.

Silicon Signature Bytes
Data (Hex)

Ao
Seeq Code

VIL

94

Product code M48F01 0

VIH

1C

Mode Selection Table
MODE

CE

WE

VPf>

A10-16

Ao-9

1/00-7

VIL

VIH

X

Address

Address

DouT

X

X

X

X

X

HI-Z

VIL

Vp

Address

Address

DIN

X

X

X

OE

Read

VIL

Standby

VIH
VIL

VIH

Byte write
Chip erase select

VIL

VIH

VIL

TTL

Chip erase

VIL

VIH

VIL

Vp

X

X

'FF'

Sector erase

VIL

VIH

VIL

Vp

Address

X

'FF'

Absolute Maximum Stress Ratings
Temperature:
Storage ..
Underbias . ......... .

E.S.D. Characteristics[ 1]
-65°G to + 150 0 G
-65°G to + 135°G

Symbol Parameter
VZAP

All Inputs except Vpp and
outputs with Respect to Vss. . .

+7Vto-O.5V

Vpp pin with respect to Vss . ..

14 V

E.S.D. Tolerance

Value

Test Conditions

>2000 V MIL-STD883
Method 3015

Note 1: Characterization data-not tested.

seeQ Technology, I n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - - - I
MD400069/ -

6-125

ElM 48F010
ADVANCE DATA SHEET

Recommended Operating Conditions
M48F010

E48F010

Symbol Parameter

Vee supply voltage

5V± 10%

5V± 10%

CIN

Input capacitance

Temperature range
(read mode)

-55°C to
+125°C

-40°C to
+85°C

COUT

Output capacitance

Temperature range
(write/erase mode)

-55°C to
+85°C

-40°C to
+85°C

Value

Test Conditions

6 pt.

VIN=OV

12 pt.

VI/O=OV

Note 2: Only performed for initial qualification and after any design
or process change which could affect parameter limits.

DC Operating Characteristics
Over the Vcc and temperature range

Limits
Symbol

Parameter

Max.

Unit

Test Conditions

IIH

Input leakage high

1

/-LA

VIN =Vcc

IlL

Input leakage low

-1

/-LA

VIN = 0.1 V

IOL

Output leakage

10

/-LA

VIN=VCC

Vp

Program/erase voltage

11.75

13

V

VPR

Vpp Voltage during read

0

Vp

V

Ipp

Vp current
Standby mode
Read mode
Byte write
Erase

200
200
50
90

ICCl

Standby Vcc current

ICC2

StandbyVcc current

ICC3

Active Vee current

V IL

Input low voltage

-0.3

0.8

VIH

Input high voltage

2.0

7.0

V

VOL

Output low voltage

0.45

V

IOL = 2.1 ma

VO H1

Output level (TTL)

2.4

V

IOH = -400/-LA

VOH2

Output level (CMOS)

Vcc-0.4

V

IOH = -100/-LA

Min.

/-LA
/-LA
mA
mA

CE =

400

/-LA

CE = Vcc -0.3 V

5

mA

CE -VIH min.

100

mA

CE=VIL

VIH. Vpp = Vp
CE = VIL. Vpp = Vp
Vpp=Vp
Vpp=Vp

V

seeQ Technology, I n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - I
MD400069/-

6-126

ElMADVANCE
48F010
DATA SHEET
READ

AC Characteristics
(over the Vcc and temperature range)

ElM48F010
-300

E/M48F010
-250
Parameter

Min.

tRC

Read cycle time

250

tAA

Address to data

tCE

CE to data

tOE

OEto data

tDF

OE/CE to data float

tOH

Output hold time

Symbol

Max.

Min.

Max.

300

ns

300
300
150
100

250
250
100
60
0

0

Unit

ns
ns
ns
ns
ns

Read Timing

ADDRESS=========~~.~=_-~=_-~=_-~=_--tA=A=~-_=~-_=~__=~_.~_I==_tR_C_-_-_-_-~_-~~_-_-_-_-_-~_-_-_-_-_-_--~~~------------1/0

0.7

---------\..----,,~---------_'r'-----"I

WE

7

AC Test Conditions
Output load: 1 TTL gate and C(load) 100 pf.
Input rise and fall times: < 20 ns.
Input pulse levels: 0.45 Vto 2.4 V
Timing measurement reference level:
Inputs 1 V and 2 V
Outputs 0.8 Vand 2 V

seeQ Technology, Incorporated ---------------------------.....1
MD4000691-

6-127

ElM 48F010
ADVANCE DATA SHEET

BYTE WRITE

AC Characteristics
(Over the Vcc and temperature range)

E/M48F010
Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

2
250
0
0
10
10
50
100
50
20
150
100

tcs

CE setup time

tCH

CE hold time

tOES

OE setup time

tOEH

OE hold time

tAS

Address setup time

tAH

Address hold time

tDS

Data setup time

tDH

Data hold time

twp

WE pulse width

twc

Write cycle time

tWR

Write recovery time

Max.

Unit

f..Ls
f..Ls
ns
ns
ns
ns
ns
ns
ns
ns
ns

150
2.0

f..Ls
ms

Byte Write Timing
(\'

tV

Vpp

~~

ADDRESS

1/00-7

t'~]\'----

____~~~~--------x==

__~~____~~____-JX~______

_ _ _oJ

\_----'
~__n _ _

_J7
~----tWR----~~

~----twc----..-j

WRITE - - - - - . . l
BYTE #1

~---BYTE

BYTE WRITE
BYTE #2

BYTE W R I T E LAST BYTE

Note: In A.C. characteristics, all inputs to the device, e.g., setup time, hold time and cycle time, are tabulated as a minimum time; the user must
provide a valid state on that input or wait for the state minimum time to assure proper operation. All outputs from the device, e.g., access time,
erase time, recovery time, are tabulated as a maximum time, the device will perform the operation within the stated time.
Advance Data Sheets contain target product specifications which are subject to change upon device characterization over the full specified
temperature range. These specifications may be changed at any time, without notice.

SeeQ Technology, Incorporated ----------------------------------------~
MD400069/ -

6-128

ElM 48F010
ADVANCE DATA SHEET

Figure 1
EIM48F010 Write Algorithm

SETVpp=Vp
WAIT Tvps
LOOP_COUNT=1

RE-WRITE
BYTE
WAITTwcl'S

SET ADDRESS
1 ST LOCATION

RE-WRITE BYTE
WAIT
Twc + Twr I'S

SET ADDRESS

1 ST LOCATION

WRITE BYTE
WAITTwcl1S
INC. ADDRESS

INCREMENT
ADDRESS

YES

INCREMENT
LOOP_COUNT

NO

END

INCREMENT
LOOP_COUNT

WAITTwr/JS
LOOP_COUNT=1

NO

DEVICE
FAILED

M=15
N=6

seeQ Technology, I n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - - - J
MD400069/-

6-129

ElM 48F010
ADVANCE DATA SHEET

AC Characteristics

SECTOR ERASE

(Over the Vcc and temperature range)

E/M48F010
Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

tcs

CE setup time

tOES

OE setup time

tAS

Address setup time

tAH

Address hold time

tDS

Data setup time

2
500
0
0
50
100
50
20
150
0
0

tDH

Data hold time

twp

WE pulse width

tCH

CE hold time

tOEH

OE hold time

tERASE

Sector erase time

tABORT

Sector erase delay

tER

Erase recovery time

Max.

Unit
/-ls
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns

500
250
500

ms

/-ls
ms

Sector Erase Timing
Vp
~------tvPH-------1

'""""-------

ROW
ADDRESSES _________J1~__~--------~~,~--~,~-------J~--------~-----'~--------

110 0-7

OE

-------'

-----+-'
r.-----tERASE-----~

seeQ
MD400069/-

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - '

6-130

ElM 48F010
ADVANCE DATA SHEET

Figure 2
EIM48F010 Sector Erase Algorithm

INCREMENT
LOOP_COUNT

WAIT tER mS
THEN VERIFY
ALL BYTES=FF

DEVICE FAILED

L=60

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

--1

MD400069/-

6-131

ElM 48F010
ADVANCE DATA SHEET

AC Characteristics

CHIP ERASE

(Over the Vee and temperature range)
ElM48F010
Symbol

Parameter

Min.

tvps

Vpp setup time

tVPH

Vpp hold time

2
500
0
0
50
20
150
0
0

tes

CE setup time

toES

~setuptime

tos

Data setup time

tOH

Data hold time

twp

WE pulse width

teH

CEholdtime

toEH

OE hold time

tERASE

Chip erase time

tER

Erase recovery time

Max.

Unit
J..Ls
ms
ns
ns
ns
ns
ns
ns
ns

500
500

ms
ms

Chip Erase Timing

Vpp

______________________- J

1100-7

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - '
MD400069/-

6-132

ElM 48F010
ADVANCE DATA SHEET

Figure 3
EIM48F010 Chip Erase Algorithm

INCREMENT
LOOP_COUNT

WAIT tER mS
THEN VERIFY
ALL BYTES=FF

DEVICE FAILED 14---'-"""""<.

L=60

seeQ
MD400069/-

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - -.......

6-133

Ordering Information

o

M

T

Package
Type
D = Ceramic Dip

T

Temperature
Range
E = -40 to +85°C

48F010

T

K

-250

18

T

T T

Device

Endurance

Access
Time

Screening

128K x 8 FLASH
EEPROM

Blank = 100

250 = 250ns

MIL 883 Class
B Screened
(Optional)

K = 1000

300 =300ns

I

L= Ceramic
Leadless Chip
Carrier

M = -55 to +125°C
(Read)
-55 to +85°C
(Write/Erase)

N = Plastic Leaded
Chip Carrier
(-40 to +85°C
Temp Range
Only)

seeQ
MD4000691-

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - '

6-134

For more information on SEEQ products,
call our toll-free number:

1- 800- 3EEPROM

seeQ Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

----1

6-135

6-136

RELIABILITY

(Reliability Report)

SEEQ EEPROM Reliability Report

Introduction and Product Description

Memory Cell Operation

SEEQ offers a family of EEPROMs (Electrically Erasable
Read Only Memories) which range in size from 4K t0256 K
bits in CMOS and NMOS technologies. They conform to
the JEDEC configurations for byte wide memories. One
family has internal input latches, a second family has internal input latches as well as a timer and a third with input
latches, timer, and a page mode feature for fast write. New
developments in process technology, circuit design
techniques, and memory cell design combine to provide
high performance from these EEPROMs that require only
a single 5-volt power supply. SEEQ uses an innovative aCell design on all its EEPROMs designed since 1983. The
a-Cell, combined with oxynitride in the tunnel dielectric,
substantially improves the write/erase endurance of
EEPROMs. This gives higher reliability to systems requiring infrequent writes (le., once a day for ten years) as well
as to systems writing 5-10 times per day.

The SEEQ EEPROM Memory Cell consists of aMOS
Floating Gate Memory Transistor and a Select Transistor.
See the Device Cross Section in Figure 1 and schematic
representation in Figure 2. The Memory Cell defines the
Logic state, either a" 1" or a "0", by storing negative or positive charge on the Floating Poly Silicon Gate (Poly 1 in
Figure 1). When the reference voltage is applied to the top
Poly Silicon Gate (Poly 2 in Figure 1), the Memory Cell will
or will not conduct a current This cell current is detected
by the sense amplifier and transmitted to the output buffers as the appropriate Logic state.
Charge is transferred on and off the Floating Gate through
the thin Oxynitride Tunnel Dielectric by Fowler-Nordheim
Tunneling; (A Quantum Mechanical transmission
mechanism of an electron penetrating through the energy
bandgap for the thin oxide MOS structure). FowlerNordheim Tunneling occurs when a high voltage, typically
17-20 Volts, is placed across the Tunnel Dielectric region
ofthe MemoryCell This high voltage is generated internal
to the device, the user need only to apply an externalS Volt
level.

Programming the state of the memory cells (via the write
and erase modes) is accomplished by charging and discharging a floating gate device via Fowler-Nordheim tunneling. This tunneling occurs through a proprietary
oxynitride dielectric under the floating gate (see Figure 1).
The use of oxynitride provides fast write/erase times at
internal voltages that are 25% lower than those required
for conventional oxide-only approaches due to a lower
barrier height than thermal oxide. In addition, oxynitride
provides lower charge trapping characteristics which
gives improved write/erase endurance of each cell. The
use of oxynitride in the dielectric area and SEEQ's proprietary a-Cell design allows endurance to be specified up to
1,000,000 cycleS/byte.

A1

For a Logic"1 ", electrons are stored on the Floating Gate;
using the conditions defined For "erase." For a Logic "0",
holes are stored on the Floating Gate; using the conditions defined for "write." The Memory Cells Thresholds
for a Logic "1" and "0" are shown in Figure 3.

POLY 2
VAPOX

FIELD
OXIDE

L - -_ _ _ _ _ _~

TUNNEL
DIELECTRIC

FIGURE 1. EEPROM N-MOS

Column
Row
Sense
Bit
ArrayVss
Floating Gate
Vr
I Cell

Program

Erase

Read

17V
20V
0
17V
Floating
-Vp
<-5V
401lA

5V
20V
20V
0
0
+VE
>+2V
01lA

5V
5V
0
2V
0

The select transistors are used to isolate the Memory
Transistor in order to prevent data disturb. Memory cells
and Peripheral Logic are combined to form the a-Cell,
which is a Memory Error Correction technique
transparent to the user.

seeQ Techno'ogy,'ncorporated---------------------------I
7-1

Static Life

SENSE AMP

"Static" refers to the D.C. bias of the cell periphery. Failure
modes for static life include threshold shifts and leakages.
The typical failure mechanisms are mobile ion contamination or trapped charges.

COLUMN (V)
SELECT LINE

Os

03
BIT LINE

The" static" stress mode may be used either for screening
or determining the long term reliability of the product

ROW (X)
SELECT LINE

O2

Operati ng Life
SENSE

The operating life of an EEPROM is limited by its general
reliability which includes integrity of the peripheral circuitry as well as the memory cells. The operating life is
characterized using a dynamic high temperature life
stress.

(SELECn LINE

0, = Memory Transistor
O2 = Row Select Transistor
0 3 = Column Select Transistor
Q. = Byte Select Transistor
Q s = Sense Select Transistor

ARRAYV ss

Dynamic high temperature life stress is a standard
approach used to evaluate the failure rate distribution of a
product under accelerated conditions. The failure rate is
statistically derived from the experimental results
obtained at elevated temperatures, then extrapolated to
typical operating temperature conditions. This extrapolation is accomplished using the Arrhenius relationship and
an apparent activation energy consistent with the failure
mechanisms observed This acceleration technique
works well for common causes of failure such as oxide
defects, interconnect voids, and defective bonding.

FLOATING GATE 85 ANGSTROMS OXY·NITRIDE

FIGURE 2. Generic EEPROM Memory Cell

Through the use of the proprietary Oxynitride process for
the Tunnel Dielectric and use of the Q-Cell, SEEQ provides EEPROM's with typical data retention times of
greater than 100 years, and Intrinsic Endurance Failure
Rates of less than .03%/1000 cycles. Devices with a
guaranteed Endurance of 1,000,000 cycles are
possible.

For ease of calculation, the instantaneous failure rate is
assumed to be constant throughout the lifetime of the product (i.e., the probability density function of the time to
failure is assumed to be exponentia~.

LOGIC MARG:l-- <::::--,

3

1

CJ

...

Units to be stressed were drawn from finished goods
inventory and written with a data pattern selected to program both logic states of"1" and "0" into locations in each
row and each colum n of the array. Initial, intermediate, and
final electrical testing of units was conducted at room
temperature using a test program that checks parametrics, functionality and timing parameters.

" I

UI
c(

SENSE AMPLIFIER
REFERENCE VOLTAGE

cl
9
0

> 0

I
ADDlTldNAL
OXYNITRIDE
MARGIN

J:

ff!

a:

...
;[

LOGIC 0 MARGIN
1'- _ _

THERMAL OXIDE

-~-;;N~;R7';----

-4
100

10'

102

_.... .... ....

__ - ... -

104

103

...... \

The dynamic high temperature stress was applied in
accordance with the conditions prescribed in MIL-STD883, Method 1015, Condition D. Oven ambient temperature was maintained at 125 degrees C. The schematics
are available upon request

~
105

107

106

NUMBER OF WRITE/ERASE CYCLES

FIGURE 3. EEPROM Cell Margin Characteristics

Table 1. Static Life Stress Results

-

Product

Total
Devices
Stressed

Total Device
Stress Hours
@ Ta = 125 C

Number of
Failures

52813

324

324,000 hrs.

0

2816

87

309,000 hrs.

0

0

Predicted Failure Rate
@90%
Confidence @ Ta = 55 C
(Ea= 0.6 eV)
0.019%/1000 hrs.
0.020%/1000 hrs.
0

SeeQ Techno'ogy,'ncorporated----------------------------..J
7-2

The results are summarized in Table 2. The predictions
use an assumed activation energy of Ea= 0.4 evforTa=
55 degrees C. The predicted charge gain failure rate is
less than one-half the intrinsic failure rate of NMOS, as
would be expected This implies the field usage failure rate
would be accurately predicted by dynamic life test

In order to determine the data retention capability of
SEEQ's products, unbiased devices are subjected to high
temperature bake at 250 degrees C. The failure mode is a
change in the state of the memory cel~ and the typical
failure mechanism is a dielectric defect resulting in
"charge loss". Because dielectric defects can be induced
by the electric fields generated during write/erase cycles,
data retention and endurance are related topics. The
effects of cycling on data retention are covered in the
endurance section In this section, the intrinsic data retention characteristics are evaluated and compared against
the minimum data retention goal of ten years.

Data Retention Bake
Intrinsic data retention is defined as the ability to retain
valid data over a prolonged period of time under storage
conditions. At the cell level, data retention is a measure of
the ability of the floating gate to retain charge in the
absence of applied external gate bias. Data retention
failures in a floating gate structure are commonly caused
by dielectric defects and can be accelerated by high temperature bake stress. This characteristic provides a technique for both screening potentially defective product
from the production flow as well as predicting expected
retention lifetimes of outgoing product

Units to be stressed are drawn from finished goods inventory and erased to an all 1's pattern (e.g., negative charge
on floating gate). After eraSing and initial testing, parts
were temperature stressed at 250 degrees C. Voltage
stress is not required for this evaluation; therefore, all
leads are held at ground potential
The results are summarized in Table3. Using an activation
energy of 0.6 ev, the data retention lifetime predicted by
the data exceed 100 years at a 55 degrees C temperature. This period exceeds the industry 10 year standard for erasable memories.

"

:Ii
~
Ul

W

CJ

a:
c
:z:
u
w
>

"Z

E 1012

Ul

0

A.

II.

0

Z

0

~

8

61-

f-

u

z

(

I-

2f-

""

---OXIDE

/

0

U

1011
10

Endurance is defined as the ability of an EEPROM to
operate to data sheet specifications after repeated write/
erase cycles to each byte. SEEQ specifies an endurance
option of either 10,000 or 1,000,000 cycleS/byte. The
extraordinary high endurance is accomplished using
SEEQ's proprietary oxynitride process and its innovative
Q-Cell design. Products which are specified with
1,000,000 cycle endurance are designated with "55"
series part numbers.

"

4f--

...a:z
w

Endurance

"".JC.
",,""

I

I

11

12

--OXYNITRIDE
I

13

14

15

16

STRESS FIELD (Mv/eM)

Endurance failures are characteristically caused by
dielectric breakdown occuring in the tunnel dielectric
itself. This breakdown is associated with charge trapping

FIGURE 4. Comparison of Positive Charge Trapping at
Tunneling-DielectriclSi Interface.

Table 2. High Temperature Dynamic Life Stress Results

Product
52813
2816/2817
36C16
52833
2864
2864
28C64
28C64
28C256
28C256

Total
Devices
Stressed
1089
1307
80
1086
370

77
237
157
350

77

Total Devices
Stress Hours
1,009,000
1,782,000
14,720
1,142,000
467,000
38,500
157,000
53,536
230,302
38,500

Stress
Temperature
125°C
125°C
150°C
125°C
125°C
150°C
125°C
150°C
125°C
150°C

Number of
Failures
1
3
0
2
1
1
1
0
3
1

Predicted Failure Rate @
90% Confidence @ 55°C
(Ea 0.4eV)
0.034%/1000 hrs.
0.033%/1000 hrs.
0.7118%/1000 hrs.
0.0112%/1000 hrs.
0.0411 %/1000 hrs.

=

0.459%/1000 hrs.
0.145%/1000 hrs.
0.196%/1000 hrs.
0.258%/1000 hrs.
0.459%/1000 hrs.

~~~~~C~~~~~~~O~~d-------------------------------~
7-3

that occurs during repeated write/erase cycles. 8ecause
this behavior is central to the device physics of an EEPROM memory cell, endurance will be discussed in two
parts; first at the cell leve~ then, at the product level.

dioxide case by at least a factor of ten. The oxynitride window demonstrates very little closing at 10 6 cycles, and
provides a very useable window at 107 cycles.
The improved performance of oxynitride over oxide is
directly related to the superior trapping characteristics of
the oxynitridefilm, as shown in Figures4 and5.ln Figure 4,
the positive charge trapping characteristics of oxynitride
and oxide are compared as a function of field strength (the
principal independent variable). The positive charge trap
density is consistently lower for oxynitride by approximately a factor of four. In Figure 5, the negative charge
trapping characteristics of oxynitride and oxide are cornpared as a function of total injected charge (the prinCipal
independent variable in this case). Note the benefit of
oxynitride in this case continues to increase with increasing charge, thus verifying the endurance improvement
first observed in Figure 3.

During each write/erase operation of a floating-gate EEPROM cell, a miniscule amount of charge is trapped in the
dielectric through which the programming charge tunnels
(Ref. 1). The cumulative effect of this charge trapping has a
strong impact on the effective threshold voltage that the
cell exhibits at each write/ erase cycle. The envelope of the
"written" threshold voltage and the "erased' threshold
voltage plotted over a number of cycles is referred to as
the cell threshold "window" and is a key figure of merit for
any EEPROM ceiL Referring to the representative
threshold window shown in Figure 3 the net effect of
charge trapping results in an initial widening oft he window
(due to positive trapped charge). Ultimately, negative
charge trapping sets the upper limit on endurance when
the window becomes too narrow to be useful.

Units were pulled from finished goods inventory and
stressed by performing repeated write/erase cycles on
every byte in the memory. Data retention, read/write
functionality, AC performance, and parametrics were
periodically tested against data sheet specs. Failures
(typically caused by the selective failure of random bits)
were analyzed and compiled for failure rate
calculations.

10~------------------------------------'

---OXIDE
- - OXYNITRIDE

10

15

A summary ofthe results is shown in Table 4. It shows that
all of SEEO's EEPROMs meet or exceed the intrinsic MOS
failure rate of 0.05%/1000 hours if you write once per day.
It should also be noted that the Q-Cell EEPROMs have
higher endurance than the non Q-Cell 52813. All of
SEEO's EEPROMs are Q-Cell except for the 52813. For
applications where writing occurs more frequently or
where a failure rate of less than 0.03%/1000 hours is
required, then a 1,000,000 cycle part such as the 16K
5516A should be considered

20

AMOUNT OF INJECTED CHARGES (C/CM2)

FIGURE 5. Comparison of Negative Charge Trapping

Reference

As seen from the endurance plot of Figure 3, the threshold
window achieved using the SEEO oxynitride dielectric
represents an improvement over the traditional silicon

(1) Ching S. Jeng et ai, IEDM Technology Digest 1982,
p.811.

Table 3. High Temperature Bake Test Results

Product

Total
Devices
Stressed

Total Device
Stress Hours
@Ta=250°C

52813
2816
52833
28C256

82
133
100
15

118,000
133,000
50,000
2,520

Number of
Failures

Predicted Failure Rate
@90%
Confidence @ Ta = 55 0 C
(Ea= 0.6 eV)

2

0.0023%/1000 hrs.

0
0

0.00087%/1000 hrs.
0.0014%/1000 hrs.
0.0461 %/1 000 hrs.

a

~~~~~~n~~~~~~O~~d---------------------------------------7-4

Table 4. Write/Erase Endurance Test Results

Product
52813
2816/2817
5516
52833
2864
28C64
28C256

Total
Devices
Stressed
189
8917
7481
4013
434
240
450

Total Device
Stress Cycles
4,400,000
3,355,820,000
7,798,000,000
1,787,810,000
35,100,000

Number of
Failures
5
190
88
68
6
5
11

2,400,000
45,000,000

Predicted Failure Rate
@ 90% Confidence
(Ea = 0.125 eV)
0.305%/1000 cycles
0.009%/1000 cycles
0.0018%/1000 cycles
0.006%/1000 cycles
0.043%/1000 cycles

Failure Rate
with One Write
Cycle per Day
0.013%/1000 hrs.
0.0004%/1000 hrs.
0.00008%/1000 hrs.
0.0003%/1000 hrs.
0.0018%/1000 hrs.

0.555%/1000 cycles
0.0529%/1000 cycles

0.023%/1000 hrs.
0.002%/1000 hrs.

Accelerated stress is updated quarterly and is available from SEEQ Technology.

seeQ

Technology, Incorporated

--------------------------------1
7-5

7-6

seeQ

Radiation and MOS
Non-Volatile Memories

Introduction
total dose before permanent damage. Variables include:
1. Thinner gate oxides are less likely to trap charge.
2. Bias applied during irradiation aggravates charge
trapping.

The effect of radiation on non-volatile memories is of
concern when the devices may be exposed to radiation
and are expected to continue functioning. Such
environments include space, non-hardened battlefield
conditions or commercial radiation applications. SEEQ
EEPROM's have demonstrated similar performance
as other MOS memories and can be successfully
used in the above listed environments, as well as
other applications requiring functionality during and
after radiation exposure. SEEQ EEPROM's have proven
particularly resistant to single event upsets.

B. Dose rate: Simulated by exposure to gamma rays
usually generated by a linear accelerator. Expect MOS
parts to withstand 10 6 to 10 7 rad(SO/sec before transient
damage and 109 to 10 10 rad(Si)/sec before permanent
damage.

Concerns

C. Neutron flux: Simulated by exposure to neutrons,
usually generated by a nuclear reactor. Expect MOS
parts to withstand greater than 1014 neutrons/ cm2 •

A. Permanent damage is a function of:
1. Total dosage of ionizing radiation;
2. Neutron flux;
3. Gamma dose rate.

D. Cosmic rays: Simulated by exposure to high
energy, heavy ions, usually generated by a particle
accelerator. Baseline standards are not well established
for MOS parts.

B. Transient errors (single event upset) are a
function of:
1. Charged particles, e.g. Cosmic rays
2. Gamma dose rate.

Data for SEEQ MOS parts

(see tables)

A. Total dose is as expected for a thin oxide, MOS part.
B. Dose rate for both transient and permanent damage
is typical for MOS parts.

Failure Mechanisms

C. No data for neutron flux, but expect to be similar to
other MOS parts, e.g. greater than 10 14/cm 2 .

A. Permanent Damage:
1. Build up of trapped charge in dielectrics, primarily
gate oxides; caused by charge generated by the
radiation flux congregating at defects in the oxide.
This results in threshold shifts and subsequent nonfunctionality.
2. Build up of interface states caused by charge
generated by the radiation flux accumulating at layer
boundaries. This results in degradation in transconductance and threshold shifts and subsequent
non-functionality.
3. Formation of interstitials and vacancies in the crystal
lattice structure caused by neutron flux. This results in
changes in the electrical characteristics of the bulk
silicon and subsequent non-functionality.

D. Data for single event upset (SEU) is using different
ions to simulate worse case cosmic rays. The parts
perform better than expected.

Definitions
A. Curie- A quantity of radioactive material undergoing
3.7 times 10 10 disintegrations per second.
B. Rad -Radiation Absorbed Dose - The absorbtion
of 100 ergs of radiation energy per gram of absorbing
material.
C. Roentgen - The amou nt of gamma rays required to
produce ions carrying 1 electro-static unit of charge in
1 cubic centimeter of dry air.

B. Transient Errors:
1. Generation of false electrical Signals from photocurrents in semi-conductor junctions caused by high
energy particles or gamma rays. These result in data
upset during read.

D. REM-Radiation Equivalent (in) Man-The measure of
the biological effect of radiation exposure is obtained
by multiplying the absorbed dose (in rads) by a "quality
factor" for the particular radiation.

Models

E. Radioactivity-The spontaneous emission of radiation, e.g. particles and/or electro-magnetic waves (photons), from the nuclei of an unstable isotope, which
eventually decays to a stable non-radioactive isotope.

A. Total dose Ionizing radiation: Simulated by
exposure to gamma rays, usually from a Co 60 source.
Expect MOS devices to withstand 103 to 104 rad (SO of

- SeeQ T e C h n O I O g y , l n C 4 ' 3 r D c ) r a t 4 9 d - - - - - - - - - - - - - - - - - - - - - - - - -.......
7-7

Radiation and MOS
Non-Volatile Memories

Radiation Test Results
16K EEPROM
(5516A12816A,
5517 Al2817 A,
52813)
Stress

Conditions

Failure Mode

Failure Range

64K EEPROM
(52833,
2864)
Failure Range

U nbaised total dose

Alternating data
patterns, (e.g.
1 st exposu re all 0' s,
next exposure all 1's)
Co 60 gamma ray
source (10 RAD/SEC)

Device will read
but some
locations fail
to write

9000 ± 2000
RAD(Si)

6500 ± 500
RAD(Si)

Biased total dose

Alternating data
patterns, (e.g.
1 st exposure all O's,
next exposure all 1's)
Co 60 gamma ray
source (10 RAD/SEC)

Device will read
but some
locations fail
to write

3000 ± 1500
RAD(Si)

3000 ± 500
RAD(Si)

Erased (1 's state),
linear accelerator
gamma ray source

Upset during
read; not
permanent

3 ± .75 X 107
RAD (Si)/SEC

1.6 ± .02 X 107
RAD (Si)/SEC

Device will
read, all
locations fail
to write

>

-10 10
RAD (Si)/SEC

Biased dose rate upset

Biased dose rate survival Erased (1's state),
linear accelerator
gamma ray source
(200 RAD/20 ns PULSE)

11,000 (±) 2500
RAD(Si)

Read only

10 10
RAD (Si)/SEC

256K EPROM
(27C256)
Stress
Biased total dose

Conditions
Memory Programmed
to all O's, Exposed
to Co60 source (1
to 35 RAD/SEC)

Failure Mode
Device Fails to
Read, Multiple
bits read 1's

7-8

Failure Range
15,000 (±) 2,000
RAD(Si)

Radiation Test Results
256K EEPROM
(28C256)

Stress

Conditions

Failure Mode

Failure Range

Biased Dose
Rate upset

Byte Checkerboard
Data Pattern; 54 ns
to 1.5 us Pulse
Widths; Linear
Accelerator

Single Bits
Change State

1.1 X 10 9 to
6.6 X 10 10
RAD (Si)/SEC

Biased Dose
Rate Lock-Up

Byte Checkerboard
Data Pattern; 54 ns
to 1.5 us Pulse
Widths; linear
Accelerator

Parts Fail to
Read, Recover
After Power
Down

5 X 10 7 to
1 X 108
RAD (Si)/SEC

Biased total dose

Alternating data patterns
(e.g. 1st exposure all O's,
next exposure all1's
Co 60 gamma ray source
(10 RAD/SEC)

Device will read
but some
locations fail
to write
Read only

-10,000
RAD(Si)

-20,000
RAD(~i)

16K EEPROM
(36C16)
Stress
Biased total dose

Conditions
Alternating data pattern
(e.g. checkerboard)
Co 60 gamma ray source
(125-200 RAD/SEC)

Failure Mode

Failure Range

Single Bits Fail
to Write

10,000 ± 2000
RAD(Si)

Read

20,000 ± 2000
RAD(Si)

Single Event Upset
64K EEPROM (52833)
Samples were programmed and subjected to different levels of radiation to simulate a cosmic flux.
The devices are read after irradiating for upsets
RUN#

IONS

LET

FACILITY

RAD H2O

TIME

UPSETS

1
2

Fe
Fe

8
6

BEVATRON
BEVATRON

144
144

30 SEC
30 SEC

NONE
NONE

3

Fe

4

BEVATRON

288

2MIN

NONE

4

Fe

3.8

BEVATRON

288

2 MIN

5

Kr

41

Ar

15.4

Ne

5.7

0

ENERGY

NONE

CYCLOTRON

200 MeV

NONE

CYCLOTRON

160 MeV

NONE

CYCLOTRON

88 MeV

NONE

1.8

CYCLOTRON

217 MeV

NONE
NONE

N

2.9

CYCLOTRON

68 MeV

6

P

.004

CYCLOTRON

148 MeV

NONE

7

CF-252

42

105 MeV

NONE

256K EEPROM (28C256)
FACILITY

ENERGY
105 MeV

-seeQ

Technology,lncorporated-------------------------------a

7-9

7-10

Memory Products
Reliability Note

CALCULA TION OF
EEPROM BOARD MTBF
November 1987

I
seeQ
Technology, Incorporated

7-11

Calculation of EEPROM Board MTBF
The increasing use of EEPROMs for large arrays
of non-volatile memory storage has raised
interest in how to calculate the MTBF (mean time
between failures) of the resulting assembly. This
paper will demonstrate how to calculate the
board MTBF as well as compare the results of
using different EEPROM technologies and failure
rates. Even though the microcircuit failure rate is
among the least significant factors in board
failures, the effects of other components will be
ignored for the purpose of simplicity.
The MOS Floating Gate EEPROM has two
reliability characteristics which require consideration beyond that of a normal MOS memory.
Endurance, the number of times an EEPROM
may be erased and re-programmed, is finite
because of the effects of the Fowler-Nordheim
tunneling current on the floating gate isolation
dielectric(s). Data retention, the length oftimethe
EEPROM will retain stored data, is finite because
of the impossibility of permanently storing an
electronic charge. The read or operating life
reliability will be similar to other MOS memories
of like density.
SEEa builds EEPROMs with a-Cell on-chip error
correction in order to reduce the endurance failure
rate. The cumulative reprogramming cycles in the
operational life of the application must be less
than the number of cycles before the onset of
endurance wear-out; therefore, the average reprogramming frequency (cycles/hour) times the
expected operational life of the application
should be less than the typically specified 10,000
cycle endurance limit During the operational life,
the failure rate should be as low as possible in
order to increase the system MTBF. The read and
data retention failure rates of SEEa EEPROMs
appear similar to other vendors, although these
rates should theoretically improve as a larger
statistical data base is acquired.
Mil-Hdbk-217 is frequently used to calculate
failure rates for microcircuits. Historically 217
has not made accurate predictions regarding LSI
or VLSI devices such as MOS memories. This is
exacerbated with EEPROMs that have the
additional application-dependent considerations
of data retention and endurance. In orderto make
accurate predictjons of expected failure rates,

seeQ

manufacturers use data from accelerated stressing. This data is then de-accelerated to normal
operating temperatures using the Arrhenius
relationship and the apparent activation energy
for the associated failure mechanism mortality
function. Similar in methodology to operating life
(read) calcu lations, failu re rates for data retention
in %/1 000 hours and endurance in %/1000 cycles,
may be calculated.
Most failure mechanisms are thermally
accelerated, so with a lower operating temperature, the board MTBF will be longer. CMOS
EEPROMs consume less current, both active and
standby, than comparable NMOS EEPROMs.
Therefore, the power requirements for CMOSpopulated PCBs are less and the system will
operate at a lower temperature.
In ordertocalculatethe board MTBF, the number
of EEPROMs, the read, endurance and data
retention failure rates, the re-programming frequency, the rail temperature, the appropriate
thermal resistances and the device power consumption must be known.
The calculation of the board MTBF is best illustrated through the use of an example. A comparison
will be made between NMOS and SEEa CMOS
256K bit EEPROMs to demonstrate the effects of
power consumption, and the intrinsically lower
endurance failure rate of SEEa EEPROMs with
a-Cell on-chip error correction.
The following assumptions have been made:
1. Number of devices per board = 96; 3 active,
93 standby, during the operating life of the
board.
2. The Icc of each device at the operating temperature will be 50% of the maximum specified
at -55 degrees C. and maximum operating frequency. Programming Icc is slightly less than
read Icc; therefore, programming Icc will be
ignored. The devices are operated at a nominal
5 volts.
3. The average re-programming frequency is
once every 8 operating hours.
4. The rail (heat sink) temperature is 71 degrees
C. Uniform heat dissipation across the PCB.

Technology,lncorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

7-12

5. Thermal resistances:
a board - rail, 9br. 3° C/W
b. case - board, 9cb: 2.5° C/W
e. junction - case, 9jc: 20° C/W

d. data retention failure rate: .001 %/1 000 hours
e. endurance failure rate: .2%/1000 cycles

9. The basic equations to be used are:
a junction temperature = (rail temperature +
9br * PDboard) + (9cb * PD part) + (9jc *
PDpart)); where 9xx is the appropriate thermal resistance and PDxx is the appropriate
power dissipation.
b. power dissipation/part = Vcc nominal * Icc
max * 50%.
c. Power dissipation/board = (3 * PDactive) +
(93 * PDstandby).
~
~)
d. Arrhenius acceleration factor=e K 'Tn TJ ;
where K= Boltzman'sconstant(8.62 x 10- 5 )
and Tn and Tj are the normalized and junction
temperatures expressed in degrees Kelvin.
e. MTBF = (1/(# parts * failure rate)) * 10 5
See note.
f. Board MTBF= (1/(# parts* (failure rate read
+ failure rate retention + failure rate
endurance)) * 10!!

6. Base failure ratesareat55 degreesC. and90%
Confidence Interval. Failure rates are
accelerated according to the Arrhenius
relationship, with following apparent activation
energies (Ea):
a read: .4 ev.
b. data retention: .6 ev.
e. endurance: .1 2 ev.

p __

7. The characteristics for the SEEQ 28C256
EEPROM are:
a Icc active: 60 rna max.
b. Icc standby: 250 JLa max.
e. read failure rate: .02%/1000 hours
d. data retention failure rate: .001 %/1000 hours
e. endurance failure rate: .05%/1000 cycles
8. Thecharacteristicsforthe NMOS EEPROM are:
a Icc active: 1 20 rna max.
b. Icc standby: 60 rna max.
e. read failure rate: .02%/1000 hours

The results of the calculations are summarized in
the following table:

TABLE 1
CMOS

PARAMETER

NMOS

Device power dissipation
active
standby

0.150 watts
.000625 watts

0.300 watts
0.150 watts

Board power dissipation

0.5081 watts

14.85 watts

71°C
72.52°C
72.89°C
75.89°C

71°C
115.55°C
116.3°C
122.3°C

.0466 %/1000 hrs
.0035 %/1000 hrs
.0080 %/1000 hrs

.2223 %/1000 hrs
.0370 %/1000 hrs
.0514 %/1000 hrs

22,318 hours
292,191 hours
129,252 hours

4,684 hours
28,097 hours
20,229 hours

17,868 hours

3,350 hours

Rail temperature
Board temperature
Case temperature
Junction temperature
Failure rates at calculated TJ
read
retention
endurance
MTBF of Devices:
read
retention
endurance
MTBF of BOARD
NOTE:
Actual MTBF =

1
(1-(1-failure rate)# parts)

but equivalent to

1
(# parts * failure rate)

I

for very low failure rates.

~~~~c~o~n/~M~~~d-----------------------------~
7-13

Each application will have different initial conditions; however, through use of the above
equations a board MTBF may be calculated. The
board failure rate will always be reduced through
the use of a CMOS EEPROM with lower power
requirements and will always be reduced when
using a SEEO EEPROM with a lower endurance
failure rate.

The approximately 500% improvement in MTBF
through use of the SEEO CMOS EEPROMs compared with the NMOS EEPROMs may be
attributed to two factors: the almost 50 degrees
C. higher junction temperature caused by the
higher power dissipation of the NMOS parts
significantly accelerated the read and data retention failure rates; and the initial lower endurance
failure rate ofthe SEEO CMOS EEPROMs which
is not greatly affected by temperature.

seeQ

Technology. Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

7-14

APPLICATIONS

(Application Notes)

Memory Products
Application Note

MICROPROCESSOR
INTERFACING
WITH SEEQ's
LATCHED EEPROM
March 1985

I
seeQ
Technology, Incorporated

8-1

Microprocessor Interfacing
with SEEQ's Latched EEPROM

Introduction
This application note describes the interfacing of
SEEQ's "latched" Electrically Erasable Read Only Memory (E2ROM or E2) to a microprocessor bus. The
latched E2ROM family is comprised of a 16K 52813
and 64K 52833. On each of these devices there are
internal latches on all inputs except write enable. A
byte must first be erased before it can be written. In
addition to the latched E2ROM family, SEEQ has a
timer E2ROM family. This family is comprised of a
16K 2816A (24 pins), a 16K 2817A (ready/busy) and a
64K 2864 (ready/busy). The timer family has internal
latches on all inputs and has an internal timer which
automatically performs a byte erase before write. In
this application note, the E2 used is SEEQ's 52813, a
2K x 8 memory. Since the timing of the higherdensity members of the family is compatible, the
circuits given can be extended to interface equally
well with the 52833 (8K x 8). 80th bus timing and
software timing are used to gate the control signals.
The case presented here uses general control signals
to permit adaptation to any system's bus structure. In
addition, modifications are given for interfacing to
specific processors.

CHIP SELECT is usually generated separately for
each word-wide group of devices. In this way, it
chooses the actual devices to be written. E2ROM
SELECT would be an "OR" function of the CHIP
SELECT signals for all the devices for which this
latch gates WE. With WE wired in common, only one
gated latch is required for the E2ROM array. Of
course, fanout must be considered, with a highcurrent driver used if necessary. In the example bus
interfaces shown in this application note, gating for
one device is assumed, and E2ROM SELECT is tied
directly to CHIP SELECT.
The bus interface components perform other tasks
common to a memory/bus interface. For a multiplexed data bus, the bus interface components must
demultiplex the data and addresses. In addition, this
bus interface circuitry may generate MEMORY READ
and MEMORY WRITE, if required. Details of this bus
interface are given in the section "Considerations for
Special Applications," beginning on page 5.

Details of Operation
Byte Write or Erase

Interface Signals

The timing diagram in Figure 2 shows the details of a
byte write or erase operation for SEEQ's latched
E2ROM family. The two modes are the same, except
that hex "FF" is presented to the I/O lines for erasure.
Due to this similarity, only the write mode will be
discussed.

The solution presented here (see Figure 1) uses an
(74LSOOl with TTL gates (74LS32) to
latch WE for the 52813. This flip-flop causes valid
data to be latched correctly, satisfies device setup
and hold times, and allows easy latch/unlatch of the
WE signal.

S- R flip-flop

The first step is initiation of a write cycle. First, the
processor issues addresses, and the system's decoding circuitry brings CHIP SELECT valid. Although
the chip is enabled at this point, a write to the chip
has not yet begun, because MEMORY WRITE has

The system-dependent direct bus interface components form the second part of the interface circuit.
These components will generate CHIP SELECT and
E2ROM SELECT to enable this part of memory.

seeQ Techno'ogy,'ncorporated-------------------------8-2

ADDRESSr-----------------------------------------------------~~::==~--------_,
'--____________________________________________________,/1 ADDRESSES

BUS

r---------------------------------~OE

r----------,

SYSTEM RESET

»------------------+---------1<:(----...,

I
n-_--..>---------------------------------------------------~~

DATA BUS

,,-----------------------------------------------------,./1
+5

1/0

CC (FOR 52B33)

Figure 1. E2ROM Interface Circuit

ADDRESSES

DATA

E2ROM SELECT

X

VALID

X
\\\

X X
XW
\\\m\~~
X
III \\\ //11
DON'T CARE

VALID

DON'T CARE

DON'T CARE

MEMORY WRITE

MEMORY READ - OE

I
Figure 2. Write-Cycle Timing Diagram Latched E2ROM Interface Application

SeeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - 8-3

not yet been issued. This prevents inadvertently writing to an incorrect address as the address lines are
allowed to settle out before a write is initiated. Following the timing events above, the active level of
MEMORY WRITE sets the flip-flop, bringing WE low
to the E2. Data, Addresses, CE, and OE are latched
at this point.

Regardless of the method used in the timeout, the
write pulse is terminated by WE being brought high.
This is effected by a read to any location in the
device, which resets the flip-flop to bring WE high.
A second read cycle is required for byte verify.
System designers should allow extra time between
the two reads to meet write recovery time (tWR)
requirement. This method of write-cycle termination
provides another form of protection against inadvertent writing to the chip. Even if a statistically unlikely
succession of glitches were to trigger both flip-flops,
enable the gates, and bring WE low, a subsequent
read to the device could terminate the write before
data would be written.

In the second part of a write, WE continues to be
active low for the entire write cycle. This requires a
timeout, which can be effected in any of several
ways. The designer can use a timing loop in software, or trigger a timer which interrupts the
processor after the correct time. The software
timeout may require less hardware on-board. The
hardware timeout, on the other hand, allows the
CPU to perform other tasks. Obviously, a good
compromise is a software architecture with regular
(perhaps one-millisecond) timing interrupts, for system real-time synchronization. Division of the task
between hardware and software is best left to the
individual systems engineer.

For the case of a fully software-timed write, a flowchart is given for the sequence of operations (see
Figure 3), This processor-independent flowchart
handles all the erasure and writing for storing data in
the E2ROM, using the circuit from Figure 1. In addition, a segment of example code (written for the Z8)
is shown (see Figure 4),

ERASES E2ROM;

WE GOES LOW

LOAD COUNTER
WITH PULSE
WIDTH. 1 ms FOR
52BXXH; 10 me
FOR 52BXX

TIME OUT WRITE CYCLE
DECREMENT
COUNTER

TURN OFF ERASE;
FORCES WE TO
HIGH STATE

LATCH ADDRESS
AND DATA INTO
E2ROM;
WE GOES LOW

TIME OUT WRITE CYCLE

TURN OFF WRITE;
GOES HIGH

WE

RETURN TO CALLING PROGRAM

*Data is not valid during this cycle.

Figure 3. Flowchart for 52BXX Erase/Write - Software Timing

SeeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - 8-4

P 0060 7C
P 0062 92
P 006<4 D6
P 0067 82

FF
70
0071
80

P 0069 92
P 0069 D6
P 006E 82

90
0071
80

P 0070 AF

186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204

//-----------------------

// The followinQ iii a 

As-Al0

Figure 6. Interfacing to a Z8

5 address bits and IO/M, using a 74LS154 decoder.
The RESET to the 8085 processor also supplies
RESET for the E2ROM interface. Finally, the demultiplexing of address and data lines is accomplished
by a 74LS373 latch triggered by ALE. Alternatively,
an 8212 latch can be used but requires more board
space.

plished with an 8212 octal latch, as in Figure 6.
Interfacing to a Z8000 (or 16-bit Z-8us) requires an
additional 8212 latch, to demultiplex ADa-AD15. AS,
the Z-8us address strobe, is active low, and must be
connected to the active low input in order to clock
these latches.
Use with ZSO Systems

Interfacing to SOSS/SOS6 (Minimum Mode) Systems

The circuit shown in Figure 7 provides a bus interface to a Z80, Z80A, or Z808 processor. In Figure 7,
MEMORY READ and MEMORY WRITE are generated from combining MREQ with the Z80 RD
and WR, respectively, Since address and data are
issued by the Z80 processor on separate lines, the
8212 latch is not needed.

The above considerations for implementation of this
solution in an 8085 system also apply to an 80881
8086 system operation in minimum mode, with two
additions. As above, the processor issues ALE, RD,
WR, and multiplexed address/data. However, an
inverter is required in order to produce loiM from
M/IO. In addition (for an 8086), another octal latch
must be added, in order to demultiplex ADa-AD15.

Use with SOS5 Systems
The implementation of the E2ROM interface circuit
in an 8085 system is extremely simple. Figure 8
shows the bus interfacing necessary. MEMORY
READ and MEMORY WRITE are issued by the processor directly. However, MEMORY WRITE must be
delayed, as shown in Figure 8, to ensure latching of
valid data. CHIP SELECT is generated from the top

The time delay indicated in Figure 8 depends on the
type of processor used and its clock frequency. For
a 5 MHz 8088/8086, this time delay should be 100
nanoseconds; for an 8088-2/8086-2 at 8 MHz, it
should be 60 nanoseconds. For a 10 MHz 8086-1, the
time delay should be 50 nanoseconds.

SeeQ Technology, Incorpol8ted - - - - - - - - - - - - - - - - - - - - - - - 8-7

I

RESET 1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - SYSTEM RESET

r----'

1-

1I

I

-LFlJ--+- - - - - - - - - - - - - - - - MEMORY WRITE

MiiEQ o - - - -__~

_
WR

RffiH

1

I T +"1"""k>--+-1- - - - - - - - - - - -____
I

I

MEMORY READ

:

~":-i-1:
r-v
l-!!~~S~.J

I

Ao-Al0

) Ao-Al0

TO
CIRCUIT
IN
FIGURE 1

Z80 BUS
A

")

Do-Dr

Oo-Dr

"

+5
124
19
20
21
22
23

AIS
A14
A13
A12
All

G1P!!G2
0
C
B
A

Ox

L

74LS154

CHIP SELECT

E2ROM SELECT

GND
~12

Figure 7. Bus Interface - ZBO

i-g74LS74-'I

I
.---r--_-_-_-_-_-_~t---i~lD

p

0

;~YS~T-E-M-R-E-S-ET__-------------------~-~I--~It__-~C

1

RD

I .

r

I
I

101M

DECODER

-y

Ox

ClK2

g Ot-L---i11-t1-----1-!-_ClWE

~
I- '-~+511,>+..l-Ja
III
]: J

l-( RESET

-"

X

~O~E-----C~C~--~

I

-I-IJ 0
WR b-_ _ _ _ _ _ _ _-I_-+---"-4
ClK

All-AIS

:

l
_

I

(FOR 52833)

I

Col
I
I

I

,--_2_"2_K

SEl
t>-=~>---+n

1/3
74LS11

B
A

A11

74LSl54

6800
MICROPROCESSOR

---< WE

CLR

--{

SEEQ
52BXX

2.2k

(SEE NOTE)

r

Q

1/2
74LS74

+5

G1

EE

+5--<

CC

(FOR 52B33)

DBE

t.

Ao-A10

1/

Ao-A10

t.

00-07

...

V

1/00-1/07

NOTE: THIS ELEMENT OF THE CIRCUIT SHOULD DELAY A
RISING EDGE (A TTL LOW-TO-HIGH TRANSITION)
BY 250 (MIN) TO 350 (MAX) NANOSECONDS.

Figure 11. 6800/52BXX Interface

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - 8-10

Communications Products
Application Brief

INTERFACING
THE 8003 EDLC®
TO A 16-BIT BUS
March 1985

I
~

seeQ
Technology, Incorporated

is a registered trademark of SEEQ Technology, Inc.

8-11

Interfacing the 8003 EDLC®
to a 16-Bit Bus

Introduction
MCC chip, is connected to the Transceiver by the
Access Unit Interface (AUI) cable. This cable consists
of 780 balanced, shielded tWisted-pair connections,
DC biased at the station end and transformer-coupled
at the Transceiver end.

The SEEQ 8003 Ethernet Data Link Controller (EDLC )
chip together with the SEEQ 8023A Manchester Code
Converter (MCC™) chip provide an economical twochip solution for the Data Link Layer and Physical
Layer of the Ethernet protocol. These chips are fully
Ethernet compatible and suitable for use in terminals,
personal computers, workstations, printers, disk drives
and host computers.

Besides a passive tap to the Trunk Coax, the transceiver provides signal amplification, preconditioning
on the receive path, impedance matching, DC isolation, collision detection and collision signaling
generation. DC power for the Transceiver circuits is
provided through the cable.

The 8003 is a VLSI data link controller chip in a 40pin package. It replaces approximately 60 MSI and
SSI components in a typical Ethernet node configuration. The choice of which one to use is governed by
the system interface requirements for the design. The
8003 provides protocol functions like frame formatting, link access control and error control. The part is
optimized for Direct Memory Access techniques for
frame storage.

Host-Dependent System Interface
There are three basic methods for interfacing the
CSMAlCD channel to the system bus. The first one
employs First-In, First-Out (FIFO) buffer memory to
temporarily fiold the transmit and receive frames. On
the system-bus side of the FIFOs, data is transferred
serially a byte at a time by the processor. The second
method uses Direct Memory Access to transfer data
directly between the Ethernet Data Link Controller
and the system memory. In the third method, Direct
Memory Access is also used, this time with a temporary buffer memory intervening between the system
memory and the EDLC chip. The intervening buffer
relieves the system bus of some of the traffic and
timing requirements associated with the channel.
(For more information on DMA-type interfaces, see
SEEQ's Application Brief 6).

The 8023A MCC Manchester Code Converter performs the signal encoding and decoding in Manchester
Code at 10 million bits per second. It also monitors
the channel for "carrier" and "collisions" (two nodes
transmit simultaneously). Low-power CMOS technology is used in the 8023A, which is in the 0.3 inch
20-pin package.
Ethernet Node Configuration
A typical Ethernet node is shown in Figure 1. The
System Interface on the left connects the host system bus to the network. This interface varies
depending on processor and system requirements.
The station-resident hardware, consisting of the System Interface, the 8003 EDLC chip and the 8023A
Mec is a trademark of SEEQ Technology, Inc.

seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - -

8-12

TRANSMIT
SYSTEM
BUS

/~-~"'"

SYSTEM
INTERFACE

8023A

RECEIVE
COLLISION

i

i

i

HOST-DEPENDANT
INTERFACE

DATA LINK
LAYER

PHYSICAL
LAYER

Figure 1. Ethernet Node Configuration

IEEE 802.3 CSMAlCD Standard Protocol for
Local Area Networks (Alias Ethernet)

nodes on the network can detect all signals
transmitted on the network from any source.
Multiple Access means all nodes can have
equal access to the network without need for
centralized control. A node is permitted to
transmit if the network is not already busy. If,
however, two or more nodes start to transmit
simultaneously, it is called a collision. Collision
Detection means that all nodes can detect a
collision by monitoring the medium. When a
collision occurs, the transmitting nodes resolve
which will retransmit first bv differential backoff
timing.

The first Ethernet local area network was
implemented in Palo Alto, California in 1975 as
a joint effort of Stanford University and Xerox
Corporation. Since then, Ethernet has been
expanding in use and accumulating history.
Over the years, it has proven to be reliable and
efficient in a wide variety of network applications. As a result, it has become the first
industry-standard protocol for local area networks, supported internationally by computer
manufacturers in the U.S. and Europe.

Data is transmitted in "packets" or "frames"
which begin with a preamble for synchronization and end with a CRC field for error
detection. In between, the frame has source
and destination addresses, a byte-count field
and an information field. Total frame length is
72 to 1526 bytes.

In 1980 the Institute of Electrical and Electronics Engineers (IEEE) sponsored a committee to
review, document and publish this protocol as
an international industry standard. After three
years of review and refinement, this specification is about to be published by IEEE Press
under the title IEEE 802.3 CSMA/CD Local
Area Network Standard Protocol, ("CSMAlCD"
describes the medium access method, Carrier
Sense, Multiple Access with Collision Detection), The IEEE 802.3 document supersedes all
previously published Ethernet specifications.

The physical signaling format used in Ethernet
is baseband Manchester Code transmitted at a
rate of 10 million bits per second. In Manchester Code, each bit is encoded by a transition. A
"one" is encoded as a low-to-high transition
and a "zero" as a high-to-Iow. In this way there
is a continuous supply of bit-framing information for the receiver, since the transmitted
Signal is never stationary for more than one bit
time.

CSMAlCD - Carrier Sense, Multiple Access
with Collision Detection
CSMA/CD: This expression describes the
medium access method used in Ethernet alias
IEEE 802.3 CSMAlCD. Carrier Sense means all

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - 8-13

I

Interface Techniques for 16-Bit Busses

Split-Word 16-Bit Data Interface

Ethernet is a byte-oriented protocol. That is to say,
the smallest unit of data which can be transmitted is
a byte. Hence, the 8003 EDLC chip has byte-wide
data bus. Whether the System Interface is the FIFObuffer type or the DMA type, the data transfers to and
from the 8003 are byte-wide. This application brief
describes some techniques for interfacing this bytewide communication channel to a 16-bit wide bus.

Refer to Figure 3 for a circuit diagram of this technique. The split-word method splits the 16-bit word
into two halves, using one half for transmit data and
the other for receive data. In Figure 3, the upper byte
of the system data bus is used for the transmit
memory buffer and the lower half for receive. Two
74LS244 tristate buffers isolate the system bus lines
from the RxTxDO-7 bus of the 8003. The upper
74LS244 is enabled by TxACK from the DMA Controller. TxACK is the DMA Acknowledge signal for
the transmit channel. When enabled, this buffer
transfers a byte of data from the upper byte of system memory to the 8003'5 Transmit FIFO. Similarly,
the lower 74LS244 transfers data from the 8003'5
Receive FIFO to the lower byte of system memory.
Configured in this way, the transmit and receive
buffers in system memory can occupy the same
word-address space.

In designing an Ethernet node, trade-offs have to be
made between processing speed and communication speed, cost and performance, flexibility and
simplicity, etc. The right balance may be different for
each piece of equipment designed, depending on its
purpose and system requirements. In order to help
you strike the right balance for your design, several
interface techniques will be given in the following
sections. They are covered in order of increasing
cost/complexity/performance.

Full-Word 16-Bit Interface Using Byte-Wide Memory
Transfers

In an 8-bit system, the 8003 can be interfaced
directly to the data bus as shown in Figure 2. The
RxTxDO-7 bus is the bus for transferring frame data.
It connects to the internal 16-byte transmit and
receive FIFOs. The CdStO-7 bus is a separate input!
output port for control and status. It interfaces to the
system bus so that the processor has direct access
to all command and status bits. In a 16-bit system,
CdStO-7 would connect either to the upper or lower
data byte.

Another type of 16-bit interface is one that assembles and disassembles words by transferring the
upper byte and the lower byte separately. For example, suppose the convention is chosen that the upper
byte is to be the first of the two bytes to be transmitted and the lower byte the second. Then the first
byte of a frame and all odd-numbered bytes are
always transferred to/from the upper byte of
memory, and the second and all even-numbered
bytes to/from the lower.

00-7

08-15

/\..

L

~

00-7

I"

HI DATA

A

...

....

V

'fiWii

LO DATA

C

CdSto_7

E

'----

-

I=)

74LS244
BUFFER

r--

r--

I

8003

!1

8003

RxRD

E

'"

A

...

"

V

~

RxTxDo·7

7

7

DATA BUS

"

DATA BUS

Figure 2. 8-Bit DMA Data Interface

A

74LS244
BUFFER

~

:;.

...
RITxDo.7

"

V

7
·FROM DMA CONTROLLER

Figure 3. Split-Word 16-Bit DMA Data Interface

seeQ Techno/ogy,lncorpol3ted - - - - - - - - - - - - - - - - - - - - - - - - - - 8·14

The data interface for this approach is a variation of
the one shown in Figure 3. Two tristate buffers are
replaced by two bi-directional transceivers. AO, the
least-significant bit of the DMA Controller's address
is decoded with TxACK and RxACK to enable the
transceivers. The more significant address bits from
the DMA Controller, A 1 through AN, are used as the
memory address. Upper and lower memory strobes
are also controlled by AO. Refer to Table 1 for the
truth table.

This is the simpler and more economical of two
"Full-Word" data interfaces described in this application brief. The other one, shown in Figure 5,
assembles and disassembles words in registers, and
transfers 16 bits at a time. The advantage of the latter approach is in saving bus bandwidth, since it
uses half as many bus cycles to transfer the same
amount of data; but there is some additional cost in
hardware.

Table 1. AO Address Decoding for Full-Word 16-Bit Interface Using Byte-wide Memory Transfers
Transceiver Enabled
Toward (Memory; 1/0)

DMA Controller
Outputs

Memory Activity
Upper

AO

TxACK

RxACK

-

1

1

-

-

-

-

0

0

1

liD

-

Read

-

I/O

Upper

1

0

1

-

0

1

0

Memory

1

1

0

-

Lower

Memory

Write

-

Lower

Read

Write

Note: - indicates not active.

b. With Request

a. No Request, No Walt

REQUEST ASSERTED

c. With Request and Acknowledge

d. With Request, Acknowledge and Bus Arbitration

REQUEST ASSERTED

I
Figure 4. Data Transfer State Diagrams - Four Types

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - 8-15

Four types of data transfers are shown in Figure 4. The first, labeled a, is an unconditional
transfer sequence such as the type that would
be used to refresh a CRT screen. This type has
no use in an Ethernet interface since it is not
controlled by availability of storage space or
stored data.

Helpful Hints for State Machine Designers

As with writing a program, it is desirable to
start with a "flow chart" or "state diagram".
Examples of state diagrams can be seen in
Figure 4. The following are the definitions used
in the circle-and-arrow state diagrams used
here.

The diagram in Figure 4 Part b, illustrates a
transfer which is initiated "on demand". The
transfer takes place only when a "request" is
given. An example of this type is data moved
by a processor on its own synchronous bus.
Physically the request is generated by the processor, manifesting itself as a set of
bus-controls, and an address.

1. Each circle represents a single physical
machine state or an unconditional sequence
of machine states such that there are no
"hidden branches" omitted from the
diagram.
2. All conditional branches, and wait states
(which may be viewed as conditional
branches) are indicated explicitly by arrows.
Each arrow is labeled with the condition
which determines the branch.

Part c illustrates a transfer that is requested by
one entity and acknowledged by another. The
acknowledge signal is used to notify the
requesting entity that the transfer is about to
take place. This implementation provides the
requesting entity verification that the transfer is
taking place. The diagram represents the
response of the acknowledging party to the
request. The requesting party normally waits
for the acknowledgement to occur. This allows
the acknowledging party to delay, if necessary,
for data access. This mechanism is used on
asynchronous busses, like that of the 68000
microprocessor.

Following these or similar guidelines will help
to avoid unforseen anomalies in the operating
flow.
Care should be taken in defining the programs
for state machines when inputs are asynch-,
ronous with respect to the state-register clock.
Problems can result when making a conditional
branch based on an asynchronous input. Such
problems can cause intermittent branching
failures with possibilities of perverse consequences. Intermittency makes this type of
problem hard to diagnose, so it pays off to
avoid them by following these design rules:

The diagram in Part d is that of a transfer with
request, acknowledge, and bus arbitration. This
implementation is one that is used to transfer
information using a DMA controller on the
main system bus. There are actually two
request/acknowledgement sequences in this
transfer, one for bus acquisition and one to
transfer information on the acquired bus.
I nitially a request generated by one of the two
"transferees" queues the DMA controller to exit
its idle state, and arbitrate for the system bus
by generating a "bus request" Signal. When the
bus master relinquishes the bus, a "bus grant"
acknowledgement is received, notifying the
DMA controller that it now owns the bus. The
DMA controller then performs the transfer, or
transfers, by generating a "DMA Acknowledge"
to the original requesting device, and generating the appropriate addresses and read/write
control signals. Finally the sequence is terminated with control of the bus returning to the
main processor through another arbitration.

1. When a branch is conditional on an asynchronous input bit, assign next-state addresses
such that only one state-register flip-flop is
affected by the asynchronous bit.
2. For a 3 or more-way conditional branch
based on more than one independent
asynchronous bit, break it down into independent 2-way branches which conform to
rule 1.
3. For inputs which are mutually-dependent
combinations of 2 or more bits, it is best to
synchronize them with an input register
whose clock is synchronized to the stateregister clock.
When you have finished the state diagram, you
have defined the operating program design.
The next step is to choose the hardware that
can run your program most efficiently.

Diagrams like these can be used to design
state machine programs for interfaces like the
one in Figure 5, which employs a single-chip
state machine.

After choosing the hardware, you can translate
the state diagram, verbatim into program code
for the state machine.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - 8-16

TxC

REal
ACKl
82371

REOO

ACKO
9517
OUAD
DMA
CONTROLLER

.:i

TxREO

R.REO
R.ACK
4.7K

+5
4.7K

~

I

TxACK

t

e.g. 82S159
OR 82S105A

STATE
MACHINE

CK

R.RDY
R.RD

-

T.RDY

fiWR

4.7K

EOF

+5

EOP

I~~~~~~~T_
DS.15

INT

00.7

A

~ ~~OEA
>---- I----

--

~

-

~

--:;s:V

~KA

CK~ IA- -

A

B
'l

10K
~

8003

OEB I-

SBA

74LS652
REGISTERED
SAB ~ 1/0 PORT

"RxTxDo·7

v

---

-

-

HI DATA

"

7-

"

A

t-..

~

V

LO DATA

OEA

OEB

CKA

eKB

A

A

B
'l

r - SBA

SAB

'1

74LS652
REGISTERED
1/0 PORT

7-

DATA BUS

10K

+5

Figure 5. 16-Bit Full-Word DMA Data Interface with 8237/9517 Using Registered 1/0 Ports

Full-Word 16-Bit Interface Using Registered
1/0 Ports
A state machine is used to sequence the assembly
and disassembly processes. Programmable singlechip state machines and logic blocks, available from
multiple sources, are excellent for this type of
design. Most are field-programmable one time by
burning fuseable links. Normally, the state machine
portion of the design can be done in one or two
chips.

This data interface method assembles/disassembles
16-bit words iti a pair of 8-bit registered 110 ports.
The data transfers between the memory and the 110
ports are 16 bits wide. Transfers between the ports
and the 8003 EDLC chip are byte-wide.
Registered 110 ports are configured by taking two
8-bit D-type registers with tri-state outputs and connecting them front-to-back. The result is two 8-bit
bus connections, each connected to the D inputs of
one register and the tri-state outputs of the other.
The port has two register clocks and two outputenable controls. An example of such a chip is the
74LS652. The more popular 8-bit registered 110 port
chips on the market are in the 0.3 inch 24-pin
package.

A circuit example with the 8237/9517 DMA Controller appears in Figure 5. A single-chip state
machine, such as the Signetics 828159 or 82S105A,
coordinates the timing for all other components.
Two 74LS652s are ttie two registered 110 ports. The
bus lines on the right side of the ports are commaned to make an 8-bit connection to the RxTxDO-7
pins of the 8003. On the left, the 16 port lines connect to the data bus.

This interface technique can be used with some
variation for any of the three basic types of system
interface, i.e. 1. with FIFO frame buffers, 2. with
DMA to off-line frame buffers or 3. with DMA to system memory.

seeQ

Most of the command signals associated with data
transfer are sequenced by the state machine. DMA
requests (REQO and REQ1), port output-enable line

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - -

8-17

I

OEB, register clock CKB, Transmit FIFO write
(TxWR) and Receive FIFO read (RxRD) are all under
state machine control. Output-enable OEA and
register clock CKA are controlled by the DMA
Acknowledge lines. All the status lines for data
transfer connect to the state machine's inputs.
Figures 6 and 7 summarize the state-machine state
diagrams for the application in Figure 5. Refer to
Figure 6 for the word disassembly diagram. The disassembly process starts with a DMA request issued
to the DMA's transmit channel. If the channel is not
enabled, no acknowledge will be given and the state
machine will remain in the DMA Request State. If the
channel is enabled, the DMA Controller will request
and acquire the system bus, then issue the DMA
Acknowledge. A 16-bit word of data is then read
from system memory into the two ports. The next
state is Idle 1. Here the state machine waits for a
TxRDY ready signal from the 8003 if not already
present. When TxRDY is high, the machine goes to
the Read First Byte State. This state moves the
upper data byte from the upper port into the Transmit FIFO of the 8003. Another idle state occurs
where TxRDY is checked for Transmit FIFO readiness. When ready, the lower data byte from the
lower port is moved to the Transmit FIFO, ending
the cycle.

Refer to Figure 7 for the word assembly state diagram. Word assembly starts in the Idle 1 State. Here,
the state machine waits for a signal from the Receive
FIFO (RxRDY pin) indicating data is present. When
RxRDY is high, the machine advances to load the
first byte of the word being assembled to the upper
port. As the data is read out of the FI FO, the 8003's
EOF line is tested to determine if it is the last byte of
the frame. If it is, reading of the second byte is
skipped. If not, the Idle 2 State is entered. When
ready, the second byte will be loaded into the lower
port. Then a DMA Request is given. The DMA Controller will then request the bus, acquire it and give
the DMA Acknowledge. Then the state machine
passes through the Transfer State, writing the 16-bit
word to system memory. That ends the word
assembly cycle.

Further References Available from SEEa
8023A MCC Data Sheet
8003 EDLC Data Sheet
Application Note 3: Manchester Encoding and Decoding for Local Area Networks
Application Brief 6: DMA
8003 EDLC™

Interconnection to the

Figure 7. State Diagram for 16-811 Word Assembly

Figure 6. State Diagram for 16-81t Word Disassembly

seeQ Technology, Incorporated
8-18

Communications Products
Application Brief

DMA
INTERCONNECTION
TO THE
B003EDLC®
March 1985

I
seeQ
~c

is

Technology, Incorporated

a registered trademark of SEEQ Technology, Inc.

8-19

DMA Interconnection
to the 8003 EDLC

Introduction
SEEQ's 8003 Ethernet-compatible data link controller provides an economical communication interface
for terminals, personal computers, workstations,
printers, disk drives and host computers. The 8003
is a 40-pin VLSI device which can replace approximately 60 MSI and SSI components in a typigsl
Ethernet node configuration.

then, Ethernet has been expanding in use and
accumulating history. Over the years, it has proven
to be reliable and efficient in a wide variety of network applications. As a result, it has become the first
industry-standard protocol for local area networks,
supported internationally by computer manufacturers in the U.S. and Europe.

This application brief is about design techniques for
an Ethernet node when direct-memory access (DMA)
is chosen as th~ means of transferring data between
the system bus and the channel. The methods described herein can be applied to virtually any computer or system bus architecture.

In 1980 the Institute of Electrical and Electronics
Engineers (IEEE) sponsored a committee to review,
document and publish this protocol as an international industry-standard. After three years of review
and refinement, this specification is about to be published by IEEE Press under the title IEEE 802.3
CSMA/CD Local Area Network Standard Protocol.
("CSMAlCD" describes the medium access method,
Carrier Sense, Multiple Access with Collision Detection.) The IEEE 802.3 document supersedes all
previously published Ethernet specifications.

Ethernet local area networks use the broadcast network topology. That is to say, a signal transmitted by
any station reaches all other nodes on the network.
This is in contrast to other types of networks, such
as the "star" and the "ring", which use point-to-point
interconnections. Transmitted messages in Ethernet
are "broadcast" on a segment of son coaxial cable.
Communication nodes are attached to this cable via
passive taps, so that new nodes can be added at any
time without interrupting the network service. Nodes
on the network can be addressed individually, in
"multicast" groups, or by the "broadcast mode" to all
nodes simultaneously. The broadcast topology is a
very efficient mode of communication, yet it is simple and inexpensive to implement.

CSMAlCD - Carrier Sense, Multiple Access with
Collision Detection
CSMAlCD: This expression describes the medium
access method used in Ethernet alias IEEE 802.3
CSMAlCD. Carrier Sense means all nodes on the
network can detect all signals transmitted on the
network from any source. Multiple Access means all
nodes can have equal access to the network without
need for centralized control. A node is permitted to
transmit if the network is not already busy. If, however, two or more nodes start to transmit simultaneously, it is called a collision. Collision Detection
means that all nodes can detect a collision by monitoring the medium. When a collision occurs, the

Ethernet alias IEEE 802.3 CSMAlCD
The first Ethernet local area network was implemented in Palo Alto, California in 1975 as a jOint
effort of Stanford University and Xerox Corp. Since

seeQ Technology, Incorporated
8-20

transmitting nodes resolve which will retransmit first
by differential backoff timing.

The physical signaling format used in Ethernet is
baseband Manchester Code transmitted at a rate of
10 million bits per second. In Manchester Code,
each bit is encoded by a transition. A "one" is
encoded as a low-to-high transition and a "zero" as
a high-to-Iow. In this way there is a continuous
supply of bit-framing information for the receiver,
since the transmitted signal is never stationary for
more than one bit time.

Data is transmitted in "packets" or "frames" which
begin with a preamble for synchronization and end
with a CRC field for error detection. In between, the
frame has source and destination addresses, a bytecount field and an information field. Total frame
length is 72 to 1526 bytes.

SYSTEM
BUS

/--~,.

SYSTEM
INTERFACE

I

I

I

HOST -DEPENDANT
INTERFACE

DATA LINK
LAYER

PHYSICAL
LAYER

Figure 1. Ethernet Node Configuration

The Data Terminal Equipment hardware, consisting of the System Interface, the 8003
EDLC chip and the 8023A MCC chip, is
connected to the Transceiver by the Access
Unit Interface (AUI) cable. This cable consists
780 balanced, shielded twisted-pair connections, DC biased at the Data Terminal end and
transformer-coupled at the Transceiver end.

Figure 1 shows a typical CSMA/CD node configuration. The System Interface connects the
host system bus to the network. This interface
varies depending on processor and system
requirements.
Data Link functions are performed by SEEQ's
8003 EDLC Ethernet Data Link Controller
chip. This device performs medium access
control, frame formatting and error detection.
The Physical Layer functions, carrier sense,
collision signal detection, data signal encoding
and decoding are performed by SEEQ's 8023A
MCCTM Manchester Code Converter chip. Manchester Code is the physical signaling format
used on the network. Data is transmitted on the
network at a rate of 10 million bits per second.

Besides the passive tap to the Trunk Coax, the
Transceiver provides signal amplification, preconditioning on the receive path, impedance
matching, DC isolation, collision detection and
collision signaling generation. DC power for
the Transceiver circuits is provided through the
cable.

Mee is a trademark of SEEQ Technology, Inc.

seeQ

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8-21

I

DMA DIRECTLY TO/FROM
SYSTEM MEMORY

SYSTEM
BUS

DMA WITH DEDICATED BUFFERS

SYSTEM
BUS

Figure 2. SEEQ's Ethernet Chip Family: 8003 EDLC
Ethernet Data Link Controller, 8023A MCC Manchester
Code Converter

Figure 3. DMA System Interface Techniques

Direct Memory Access System Interface
There are two basic methods for interfacing the
CSMA/CD channel to the system bus using DMA,
illustrated in Figure 2. The first method uses DMA to
transfer data directly between the Ethernet Data Link
Controller and the system memory. In the second
method, a temporary buffer memory intervenes
between the system memory and the EDLC chip.
The intervening buffer relieves the system bus of
some of the traffic and timing requirements associated with the channel. These two methods will be
the subject of the following sections.

periods will have to keep up. That means data has to
be moved at 1.25 million bytes per second to/from
the communication channel. The DMA Controller
must meet this speed requirement or frames will be
lost. If the system is to support loopback diagnostics, both transmit and receive DMA channels will
have to operate simultaneously, together transferring 2.5 million bytes per second. Not just any DMA
Controller will do.
Bus Bandwidth
This is only a consideration for systems with heavy
communications traffic and/or critical response timing. The transfer of data on the system bus can
sometimes use up a considerable percentage of the
bus time, at least for short bursts. If this is a problem, the method with dedication buffer memory can
be used to offload the system bus (see Figure 2
bottom).

DMA Design Considerations for Ethernet
In designing an Ethernet node, some trade-offs have
to be made between processing speed and communication speed, cost and performance, flexibility and
simplicity, etc. The right balance can be different for
each piece of equipment designed, depending on its
purpose and system requirements. In order to help
you evaluate the trade-offs for your design, this section discusses some of the key parameters for you to
consider at the outset.

With or Without Dedicated Buffer Memory
If the system architecture does not support 1.25M
Bytes/s DMA, the dedicated buffer approach can
solve the timing problem. If the system architecture
does support high-speed DMA, then bus bandwidth
is the key factor which influences this decision. In
this case it is clearly a cost-performance issue. The
dedicated buffer can relieve system bus traffic, but it
takes more hardware to implement.

Time is Data
Since the data transmission rate for Ethernet is 10
million bits per second, data transfers during active

seeQ

Technology, Incorporated

8-22

Cycle-ste~

8003/0MA Node Hardware

or Burst Mode DMA

The 8003 has an 8-bit bi-directional data bus
(RxTxDo-7) for data transfers to and from its internal
FIFOs. In Figure 6, the node hardware is configured
to transfer data directly to/from system memory over
this bus. (This is the technique referred to previously
in Figure 3 at the top.) A two-channel DMA Controller
is used, providing one channel for transmit data and
one for receive data.

Refer to Figures 3 and 4. In the Cycle-steal DMA
Mode, the DMA Controller "steals" a bus cycle to
transfer one and only one byte or word of data. In
the Burst DMA Mode, each time the DMA Controller
acquires the bus, it can transfer several bytes or all
the data to fill or empty a buffer. Either of these two
modes can work for Ethernet in principle if the
transfer speed is adequate. The Burst Mode is usually preferred by reason of timing efficiency. In Burst
Mode, bus arbitration and change-over delays are
kept to a minimum. Also, Burst Mode allows the
DMA Controller to fill or empty a buffer in one DMA
cycle.

A transfer to the transmitter of the 8003 begins with
a DMA Request given by the 8003 (its TxRDY pin
goes high), The DMA Controller then issues a Bus
Request to the processor. After completing the current cycle, the processor halts and gives a bus grant
to the DMA Controller, which then transfers the data
by issuing a DMA Acknowledge and all necessary
address and control signals. Additional transfers
would take place if Burst Mode is used until the
Transmit FIFO is full, indicated by the TxRDY pin
going low. Then the bus is released to the processor
and the DMA cycle is over.

On Demand
Transfers between memory and the communication
circuitry must be done on demand. Some DMA Controller chips will only transfer blocks of data in
predetermined lengths. This will not work since the
processor and DMA Controller cannot know in
advance how many bytes of data can be transferred
at a given time.

Data transfer from the Receive FIFO happens in the
same way but with data flowing in the opposite
direction. It starts with a DMA Request from the 8003
(its RxRDY pin goes high), If Burst Mode is used, the
DMA will continue to transfer until the Receive FIFO
is empty, indicated by a low on the RxRDY pin.

Maximum Bus Grant Latency
The time it takes to get the bus after a request is
made is called bus grant latency. If the DMA method
without buffer memory is used, each time a DMA
transfer to/from the 8003 EDLC chip begins, the
DMA Controller must arbitrate for and acquire the
system bus. If the latency is too long, the transmitter
may underflow or the receiver overflow. The 8003
has transmit and receive FIFOs which are 16 bytes
deep, so it must transfer data at least once every
12.8 microseconds when active (16 x 800 nanoseconds). Maximum bus grant latency should be
deterministic and always less than that required to
prevent underflow and overflow.

The Data Interface for a DMA node with buffer
memory appears in Figure 6. In this case, a 4channel DMA Controller is used. Two channels are
needed as before to transfer data between the 8003
and memory. These two channels operate "off-line"
and do not require bus arbitration. The other two
transfer data between the buffer memory and the
system bus. They do require the usual bus
arbitration.

DMAREQUEST

I
Figure 5. DMA Burst Mode State Diagram

Figure 4. DMA CYCle-steal Mode State Diagram

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Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - -

8-23

transferred passes through the transceiver shown in
the top center of the figure. The tri-state buffer
appearing at the bottom center passes the address
from the DMA Controller to the System Memory during the transfer. The tri-state buffer and transceiver
are enabled by the DMA Controller at the appropriate time in its cycle.

For this design, the RxTxD0-7 ReceivefTransmit
Data Bus of the 8003 connects to a separate bus
which is isolated from the system bus by a transceiver. This bus gives the 8003 immediate access to
the buffer memory without the need for arbitration.
The two channels for memory-to-memory transfer
use the usual bus arbitration method to access the
system bus. For these two channels, data being

,/',..

").

SYSTEM
MEMORY

A..

----'\

'f"

~

A

"-

"

V

RxTxDo.7
A

8003

"
e

A

DMA
REQUEST

==:)

"

VL-~

PROCESSOR

BUS REQUEST

-----

... 7

DMA
ACK NOWLEDGE

2 CHANNEL
DMA
CONTROLLER

"-

"

2

10-2

!Cc

BUS GRANT

...

'1'

SYSTEM
BUS

Figure 6. Data Interface for DMA Directly to/from System Memory

/'

/'r-

SYSTEM
MEMORY

~ ==:)
A

A

J,..

"

V

'l"

0

"-

...

e
e

l-

C

"

~

PROCESSOR

1-

2
DMA
REQUEST

2
.- DMA
ACKN OWLEDGE

4 CHANNEL
DMA
CONTROLLER

BUS REQUEST
BUS GRANT

---

,.

RxTxDO.7

8003

-4- ~

---

~

"

>-

RIITx
BUFFER
MEMORY

I~

A.

"

~

"'v"
SYSTEM
BUS

Figure l Data Interface for DMA with Buffer Memory

seeQ Technology, Incorporated
8-24

Command Status Interface
The Command/Status Interface for the 8003 is
shown in Figure 8. The 8003 has a separate bidirectional 8-bit bus for accessing its internal command and status registers. This bus is labeled
"CdStO-7" in the figure. Three address lines, Ao, A1
and A2 select the register to be accessed. Refer to
the 8003 data sheet for a full description of these
registers and their addresses.

Channel 1, the DMA Controller will issue simultaneously a DMA acknowledge (on DACK1) and an
input/output write (lOW), which are used to assert
the TxWR write line on the 8003. After a request for
Channel 0, the DMA Controller will issue simultaneously a DMA acknowledge on DACKO and an
input/output read (lOR). These are used to assert the
RxRD read line on the 8003.

To write to a command register, the system bus
decoder must provide a low level to both Chip Select
(CS) and Write (WR) while data and the three address
bits are valid. To read a status register, a low is applied to both Chip Select and Read (RD) while the
address is valid.

The EOP control line on the 8237/9517 indicates the
"end of process" which has the same meaning as the
8003's "end of frame" line (EOF). These lines are
used to terminate the transfer process after the last
byte of a frame has been transferred. Both the EOP
and EOF lines are bi-directional, the direction depending on the direction of data transfer. They are
interfaced together by an inverting transceiver, whose
direction of operation is controlled by the DACKO
and DACK1 acknowledge lines.

The Interrupt Request line (JNT) goes high to request
an interrupt when specific conditions occur. This
line drives the interrupt input of the processor, either
directly or through an interrupt-priority logic block.
Conditions for generating an interrupt are selected
by setting bits in the command registers. For details,
see the data sheet. The Interrupt Request line is
cleared automatically when the processor reads the
status registers.

The active polarities of the DREQ and DACK lines
on the 8237/9517 are programmable by setting
internal control bits. For the interface shown, they
should be programmed active high.

68440/68450 DMA Controller Interface

8237/9517 DMA Controller Interface

The 8003 interface to the 68440/68450 DMA
Controllers from the popular 68000 microcomputer
family is shown in Figure 9. The request lines on the
68440/68450 can be programmed to be level or edge
sensitive. In this example, level sensitivity is selected
by setting internal control bits. As in the previous
example of Figure 9, the TxRDY output of the 8003
drives the request line for Channel 1 and the RxRDY
requests Channel O.

The interconnection of popular the 8237/9517 DMA
Controller to the 8003 is illustrated in Figure 8. The
TxRDY control line from the 8003, which indicates
that the Transmit FIFO is not full, is used to generate
the DMA request for Channel 1, the transmit channel. Similarly, RxRDY which indicates that the
Receive FIFO is not empty generates a request for
Channel 0, the receive channel. After a request for

+5

DATA
BUS

A

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REQUEST

INT

Figure 8. Control/Status Interface

seeQ

DREQ1

TxRDY

DREQO

RxRDY

Figure 9. 8003 Interface to 8237/9517 DMA Controller

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - -

8-25

I

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EOF

Figure 10. 8003 Interface to 68440/68450 DMA Controller

The acknowledge lines on the 68440/68450 can be
connected directly to the TxWR and RxRD inputs of
the 8003 as shown in Figure 9.

status registers of the 8003. This is used for a variety
of conditions which can occur on the network. For
example, if 16 consecutive collisions occur, network
diagnostics and/or an alarm are ordered by interrupting the processor. The status code which has
generated the interrupt is read by the processor
from the 8003's internal status registers.

On the 68440/68450, the EOF function pin is called
"done". The DONE pin interfaces to the 8003's EOF
pin through an inverting bi-directional transceiver
shown at bottom center of the drawing. As in the
previous example, this signal terminates the channel
activity at the end of the frame.

The PCLO input can be programmed to be an input
for restarting Channel 0, the receive channel. In this
mode, a low on PCLO will re-initialize the channel
automatically. It is driven by the 8003's RxDC
receive discard line. RxDC goes high following
reception of a bad frame or frame fragment. This will
in effect discard the bad data and restart the receive
channel, without the need for processor intervention
in setting up the channel.

The PCLO and peL 1 lines on the DMA Controller
are put to good use in this application. They are
programmable inputs associated with Channel 0 and
Channel 1 respectively. By setting internal control
bits, the PCL 1 line can be programmed to activate
the on-chip interrupt request logic. The interrupt
request output of the 8003 (tNT) is used to drive it. A
low on PCL 1 will interrupt the processor to read the

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - 8-26

Communication Products
Application Note

8005
ADVANCED EDLC®
USER'S GUIDE
September 1987

I
seeQ
Technology, Incorporated

EDLC is a registered trademark of SEEQ Technology, Inc.

8-27

8005
Advanced EDLC
User's Guide

Introduction
Ethernet was developed by the Palo Alto
Research Center (PARC) of the Xerox Corporation. The first network was implemented in 1975,
as a result of a joint effort by Stanford University
and PARCo Over the years, it was proven to be reliable and efficient in a wide variety of network
applications. As a result of that success, it
became the first industry standard protocol for
LANs, supported internationally by computer
manufacturers in the United States and Europe.
The network allows equal access by all nodes,
can support upwards of 1000 nodes, and can
operate with a coaxial cable length in excess of
500 meters. Ethernet is easy to realize, due in
large part to currently available LSI chips which
implement it

The transceiver makes a connection to the cable
via connectors or has barbs to pierce the cable
and establish an electrical connection when a
screw or bolt is tightened. The transceiver provides collision detection, electrical isolation and
voltage level translation between the system at
the node and the cable carrying data

Multiple Access
All nodes have equal access to the network
There is no priority assigned to any node. Also,
there is no central control, nor is there any token
passing. Any given node may transmit if the network is not already busy. If two or more nodes
transmit at the same time, a collision occurs.

In 1980 the Institute of Electrical and Electronics
Engineers (IEEE) sponsored a committee to
review, document, and publish this protocol as an
international industry standard. After three years
of review and refinement, this specification has
been published by the IEEE press under the title,
"ANSI/IEEE 802. 3-1985 CSMNCD Local Area
Network Standard Protocol". The medium access
method is described by the abbreviation CSMN
CD, or Carrier Sense, Multiple Access with Collision Detection.

CSMAlCD: CarrierSense, MultipleAccesswith
Collision Detection
Carrier Sense
All nodes on the network can detect all signals
transmitted from any source. A node is any connection to the coaxial cable via transceiver,
shown in Figure 1.

seeQ

Figure 1.

Technology,lncorporated - - - - - - - - - - - - - - - - - - - - - - - - -

8-28

Collision Detection
All nodes can detect a collision by monitoring the
medium. When a collision occurs, the transmitting
nodes jointly decide which node will retransmit
first by a technique known as truncated binary
exponential backott, which provides for a random
timeout at each node before each retransmit
attempt.

Ethernet Data Format
Data is formatted and transmitted in "packets" or
"frames", as shown in Figure 2. These frames
begin with a preamble for synchronizatiol'l, and
end with a CRC field for error detection. In
between, the frame has destination and source
addresses, a byte count field, and a data field. This
data field contains from 46 to 1500 bytes of information which is passed to a higher layer of
software for processing. It is transparent to the
media access layer of Ethernet, and may contain
any arbitrary sequence of bytes.
Total frame length is 72 to 1526 bytes, including
preamble (8 bytes), and frame check sequence
(4 bytes).

DESTINATION
ADDRESS (6)

PREAMBLE (8)

The signaling method used in Ethernet is baseband Manchester code, transmitted at 10
Megabits per second. Manchester code is such
that each bit is defined by a transition at its mid-bit
point: a ONE is encoded as a high going signal
and a ZERO is a low going signal. Thus, the data is
said to be self clocked. This technique provides a
continuous supply of bit framing information for
the receiver, since the transmitted signal is never
static for more than one bit time.

Addressing Scheme
An Ethernet address contains six bytes to define
a station address. This allows for over 140 trillion
unique addresses. The 48th bit in the address is
reserved to indicate a broadcast or multicast
address. Xerox Corporation controls issuing
addresses for Ethernet. As a system manufacturer, you receive your block of addresses when
you receive a license. It is necessary to assign a
unique address for each product that communicates on Ethernet.

SOURCE
ADDRESS (6)

BYTE
COUNT(2)

DATA
(46-1500)

FRAME
CHECK SEQ
'(4)

STATION ADDRESS
REGISTER BIT 0

I

[
BYTE 0

~

STATION ADDRESS
REGISTER BIT 7
BYTE 1

PREAMBLE

A40 ... A47

SOURCE ADDRESS

Figure2. Ethernetframeformat. Numbers in parentheses indicate the length of each field. Bits
within a byte are transmitted and received LSB first and MSB last.

seeQ

Technology, Incorporated

8-29

I

Direct Memory Access System Interface
There are two basic DMA techniques for interfacing the network to the system bus. The first, in
Figure 3a, uses DMA to transfer data directly between the Ethernet controller and the system
memory. In Figure3b,atemporarybuffermemory
intervenes between the system memory and the
controller chip. This buffer eliminates the need to
service LAN traffic in real-time.

Why a Local Buffer?
Considerthefirst approach, where no local buffer
is used at the node. Since the LAN data rate is 1 ()
Megabits per second, the 0 MA controller must be
capable of handling system data at a minimum of
1.25 Megabytes per second. If the controller cannot operate at this rate continuously, LAN data
will be losl Additionally, ifthesystem istosupport
loop back diagnostics, both transmit and receive
must operate simultaneously, togethertransferring
2.5 Megabytes per second. Clearly, a garden
variety DMA controller will not get the job done.
Particular attention must be paid to how long it
takes the controller to acquire the system bus. If
too long, Ethernet data will be lost
Collision Effects
Collisions normally occur during transmission of
the first 64 bytes of data If packets are retrieved
via 0 MA from system memory, when a collision

occurs these 64 bytes must be retransmitted.
This is an inefficient use of bus bandwidth.
An Ethernet Controller is a True Asynchronous
Peripheral
Prudent system design calls for buffering any
peripherals which are asynchronous in nature.
Buffering makes the resource much more
manageable at the system level.

Implementing a Local Buffer
Most currently available Ethernet controllers
have a modest buffer built in, usually on the order
of 16 bytes. This is sometimes adequate to handle system bus acquisition delay, but it does not
make efficient use of bus bandwidth in three
important areas:

1. Collisions during transmit As network traffic
increases, the probability of a collision increases.
Each time a collision occurs the Ethernet controller must retransmit from the beginning of the
packet The time spent retransmitting due to collision uses bus bandwidth unnecessarily.
2. Frame check sequence (CRe) errors after
receive. Since errors are not detected until after a
packet has been received, bus bandwidth will be
wasted when receiving packets with errors.

SYSTEM
MEMORY

SYSTEM
MEMORY

ETHERNET
CONTROLLER

SYSTEM
BUS

SYSTEM
BUS

Figure 3a.

seeQ

DUAL-PORT
MEMORY

PROCESSOR

PROCESSOR

Figure3b.
Technology,lncorporated - - - - - - - - - - - - - - - - - - - - - - - - -

8-30

3. A significant number of receive packets are
minimum size (64 bytes) yet contain much less
than64 bytes of information. Forexample, packet
acknowledgments contain less than 20 bytes of
information and are padded to the 64 byte
minimum required. Transfer of these pad bytes
over the system bus cannot be avoided without
some large local buffer.
Supplementing the Controller Buffer
RAM can be added to the Ethernet board to add to
the modest buffer already on the controller chip.
Figures 4a and 4b show two possible ways.
The buffer should be at least 1514 bytes long.
Static RAMs were chosen in Figure 4a to avoid
having to include refresh control circuits in the
dual port memory control logic.
The memory control must regulate access to the
buffer by two buses: the system bus, and the data
bus from the controller. The SRAMsare costly.
If DRAMs are used as in Figure 4b the cost is
lower but they do require refresh circuitry in the
memory controller.

Local Buffering with the 8005

Figure 6 illustrates a cluster controller which services three printers and three PCs or terminals,
and provides access to the Ethernet for the devices.
The printer controller services the cluster of three
printers, and a low cost, low speed LAN provides
coverage for the PCs. This LAN coverage may
represent a relatively small geographic area, like
a single corporate department. Note, however,
that each device has access to the Ethernet, and
each has a specific Ethernet address.

Design Examples
In this section, we'll briefly examine the way in
which the 8005 can put two popular microprocessor bus formats on Ethernet, by way of
using the Intel and the Motorola bus modes built
into the 8005. Then we'll look in detail at a
intelligent Ethernet controller which could realistically reside on a PC board, and usurp a minimal
amount of resources from the system in which it is
installed.
The Intel Mode
Figure 7 shows an implementation of the 8005 in
an environment using an Intel processor. Note
that BUSMODE is pulled up, indicating that the
8005 will produce Intel-compatible output
signals, and accept inputs from an Intel bus. Also,
in this example, we have selected a 16 bit bus,
since BUSSIZE is high.

The 8005 Advanced Ethernet Data Link Controller combines several unique approaches to
the problem of implementing an Ethernet connection. Look at the design in Figure 5.

The Motorola Mode

First consider the local buffer: the 8005 is
designed to work with 64K x4 DRAMs which are
readily available, and inexpensive. It has on board
refresh circuitry, and just two DRAM chips provide 64 Kbytes of local buffer storage.

In Figure 8, the 8005 is configured for use with
Motorola processors, and the interface fits that
processor family. BUSMODE is a ZERO, and we
have specified a 16 bit bus, as before with the
Intel mode.

The 8005 treats the DRAM in a unique fashion: it
multiplexes both address and data over eight
lines. This saves on circuit board traces: only 12
lines are required to interface with the DRAMs,
compared with 26 lines if static RAMs are used.

A Board Level Ethernet Controller

The 8005 also directly supports an address (EE)
PROM, which allows for storage of the 8005's
Ethernet address and configuration data
The 8005 supports six unique station addresses.
Thus, one physical connection on the Ethernet
suffices for six logical connections. You could
make effective use of this feature by, for example,
connecting six devices to one Ethernet node, and
controlling access to each device.

seeQ

Figure9 illustratesadesign using the Intel80186
as a co-processor with the 8005, on the same PC
board, to implement Ethernet. The80186 isa particularlygood choice forthis application, because
it has an on-chip DMA controller.
The 80186 has multiplexed address and data
lines, here shown being demultiplexed by the
latch. The data bus is buffered by the 74LS245s,
but these may not be required, depending on the
fanout required by the specific application.
The important signals between the two chips are
the following; refer also to I ntel80186 and SEEQ
8005 data sheets.

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - -

8-31

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PORT C: SYSTEM BUS TO ETHERNET CO NTROLLER

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Figure4. Implementing a local buffer for Ethernettraffic, using static RAM (a), and dynamic RAM
(b). DRAMs are lower in cost, but require refresh circuitry.

seeQ

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8-32

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Figure 5. The 8005 Advanced Ethernet Datalink Controller: it supports a local buffer via DRAM,
keeps its Ethernet address and configuration data in its own on-board PROM, and
provides a very flexible and sophisticated link between your system and Ethernet.

~~~~~~~~~~C~~~~d----------------------------8-33

I

COAX

r-- --------- ---CLUSTER CONTROLLER
HARDWARE

SYSTEM CPU
AND
GLOBAL MEM

PRINTER
CONTROLLER

L ________________ _

PRINTER

PRINTER

PRINTER

NETWORK
ADDR=XX

NETWORK
ADDR=YY

NETWORK
ADDR=ZZ

TERMINAL
OR P.C.

TERMINAL
ORP.C.

TERMINAL
ORP.C.

Figure6. You can connect uptosixdevicestoone Ethernet node using the capabilityofthe8005
to decode up to six station addresses. In this example, three printers and three PCs or
terminals are connected to one Ethernet node. The 8005 and its system CPU controls
Ethernet access to and from the devices.

Use DREOfromthe8005 intoDROO ofthe80186.
This is the highest priority DMA request on the
80186. Since the 80186 has no explicit DMA acknowledgment signal, you need to use the
peripheral chip select signal: PCS1 is used as the
DMA acknowledge, and PCSO is the 8005 CS
(chip select). The 8005 INTerrupt is connected to
the 80186 INTO, and lACK of the 8005 is pulled
up, since the 80186 does not provide for its use.
The ROY line of the 8005 is connected to the
ARDY (asynchronous ready), since the two chips
are each running off their own clocks. At the
80186, pull up SRDY (synchronous ready).
The 80186 does not provide a terminal count output, as do many other DMA controllers, to indicate
to the 8005 to drop its DMA request. Therefore,
when the80186 Terminal Count Interrupt occurs,
software must disable the DMA request in the
8005 by setting bit 11 in the command register.

seeQ

Other Support Circuits

The 8005 supports a PROM, shown here as a
2804A E2 PROM. The PROM is used primarily to
store its Ethernet address and configuration
data, but other convenient data may be stored
there too.
The 8005 supports the TI TMS 4464 DRAMs (or
equivalent) with a minimum of PC board circuit
traces by multiplexing both address and data
lines to the DRAMs. Two DRAM chips provide an
ample 64 Kbytes of Packet Buffer storage. The
8005 allows you to partition this buffer into
receive and transmit areas of your own choice.
Finally, the diode RC network provides a power
on reset pulse (minimum 10 microseconds wide)
for both the 8005 and 80186.

Technology, Incorporated . , - - - - - - - - - - - - - - - - - - - - - - - - - -

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Figure7. The 8005 interfaced with an Intel processor. Thisexample illustrates the useofa 16 bit
bus, since BUSSIZE is a ONE.

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technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

8-35

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Figure 8. The 8005 in a Motorola environment, and with a 16 bit bus size.

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TxD

READY'
ARDY ~-+------------------~------------_::::::~
RESET'
INT

R~~-+------------------~4---------------~

lACK'
DREO

INTO ~-+----------------------.J

ADO
SEEO
8005

AD2

DROO~----------------------~--------+---~~

DACK'
PCS1'1-----------------------+---------t----=..:=--t
CS'
PCSO'~----------------------+--------+-___:===-I

I---rVccW

SRDY

TERMCT'

5V

X1

h

AD4
ADS
AD6

BUSMODE

RAS'

Vee

CAS'

~

VSS
X2'-L

AD3

AD7

BUSSIZE

RES'

AD1

o

w,
G'

-----

I
II
III

rill

INTERCONNECT DIAGRAM
8D05 AND INTEL 80186

Figure9. The useofthe8005 andthe Intel80186to implementa board level intelligent Ethernet
data link. The 80186 is a good companion for the 8005, since it has an on-chip DMA
controller. The 8005 supports an address PROM, and 64 Kbytes of DRAM to serve as a
local Packet Buffer.

The 8005 in Non Ethernet Applications
The Ethernet, because of its simplicity and high
speed, is often used in smaller physical configurations than those for which it was originally
intended, Applications include communications
between processors in a large parallel processing engine.
The 8005, because of its configurability, can be
"trimmed down" for use in networks which need
not strictly follow the Ethernet format
The Ethernet address is six bytes long. The 8005
may be configured to accept just a 2 byte address,
saving four bytes per address in a packet Since
there are two address fields per packet (destination and source), eight bytes are saved.
Ethernet specifies a minimum "slot time" of 51.2
microseconds. This represents the time required
for one round trip of a packet on a maximum

seeQ

jength cable, and is required for reliable collision
detection. The 8005 may be configured for a slot
time of 12 microseconds, which shortens waiting
time after a collision. Additionally, when you
select the shorter slot time, the 8005
automatically reduces the Collision Jam Pattern
from 8 to two bytes, and reduces the interframe
spacing from 9.6 to 2.4 microseconds.
Refer to the 8005 data sheet for more detail on
selecting these optional parameters.

Configuring the 8005
This step is required following hardware reset or
software reset. Note that a hardware reset must
be provided following power on. Following reset,
allow 10 microseconds after the reset before
attempting access to the part.

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8-37

I

Configuring includes loading the Ethernet station address(es), selecting transmit and receive
packet buffer size and defining interrupt conditions and an optional interrupt vector.
All this information may be stored in a PROM on
the same PC board as the 8005. This allows the
assigned Ethernet station address(es) to travel
with the board.

Register Architecture

value from 0000 to 0005 to Configuration Register # 1. Then write the appropriate 6 byte address
to the buffer window register, one byte at a time,
with the most significant byte first, and the least
significant byte last. Each write automatically
increments an internal pointer registerto the next
byte of the station address. Repeat this process
until you have loaded all desired station
address registers.

Specify Transmit Buffer Size

The general approach to initializing the 8005
consists of reading information from the PROM
into system RAM and writing it back into several
registers inside the chip. See Figure 10, which
depicts the Register Model of the 8005.
There are nine 16-bit registers which are directly
accessable by using the Signals Chip Select, I/O
read, I/O write and A1 through Aa. There are also
four registers which are selected by the buffer
window code bits and accessed indirectly
through the buffer window register.
In the discussion below, note that theB005 has
been configured for a 16 bit bus. Input Ao (pin 54)
is ignored when in 16 bit mode, and is shown as a
"Don't Care" (X). In 8 bit mode, Ao selects the low
order byte when a ZERO, and the high order byte
when a ONE.

Reading the Address (EE) PROM
Afterreset, if you are using a local Address PROM,
write that location to the DMA Address Register
which pOints to the first configuration byte in the
PROM. Select access to the Address PROM by
writing 0006 to the Buffer Code Bits in Configuration Register#1. The8005 willthendrivethechip
enable line of the PROM via APEN (pin 10) for
each Read or Write to the Buffer Window Register. When all configuration and station address
bytes have been moved into system RAM, the
next step is to write them into the 8005.

Loading Indirect Registers

Write a 0007 to Configuration Register #1 to
select the Transmit End Area register. Write an 8
bit value to the Buffer Window register which
specifies the most significant byte of the last
address in the Transmit Buffer space.
For example, to define space for four packets,
each 1 514 bytes long:
1 514 X 4 = 6056 bytes for data
16 bytes for header
4 X4 =
6072 bytes required;
6072/256 =

23+, or hex 0017

Thus, we wou Id write hex 001 7 to the transm it end
area register. This also sets the receive buffer
area, by default, to start at hex 1800, which
leaves 58 Kbytes(hex FFFF minus hex 1800) for
receive packets.
If interrupts will be enabled and an interrupt vector is required, write a 9 into Configuration Register#1 toselectthe Interrupt Vector Register, and
then write the 8 bit interrupt vector into the Buffer
Window Register.

Specify Receive Buffer Size
Write an 8 bit value into the least significant byte
of the Receive End Area Register to specify the
most significant byte of the last buffer address for
receive packets. This would normally be hex FF if
the rest of the local buffer is to be used for
received frames.

Loading Direct Access Registers

Indirect registers are selected by the buffer code
in Configuration Register #1 and accessed
through the buffer window register. All indirect
registers are 8 bits wide and therefore only use
data bits 0 0-0 7•

Station Address Registers
To load the station address registers, select the
desired station address register set by writing a

Initialize Transmit Pointer Register
Write 0000 to this register.

Configuration Register #1
Loading this register defines receiver match
modes, enables station address register sets and
sets up DMA burst interval and size. Access this
register by setting Aa-Ao to 001 X.

8-38

Ao

BUSSIZE

STATUS

REGISTER

CONFIGURATION

REGISTER #1

CONFIGURATION

REGISTER #2

NOT USED

REA REGISTER

RECV. POINTER

REGISTER

TRAN. POINTER

REGISTER

D.MA ADDRESS

REGISTER

16

BUSSIZE--"""

64KBYTE
PACKET
BUFFER

Figure 10. Register Model, which illustrates the register architecture inside the 8005. Using
both directly and indirectly accessable registers lowers pin count. All access to
indirect registers and the Packet Buffer is through the Buffer Window Register.

seeQ

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8-39

Configuration Register #2
Following reset, this register is configured for
IEEE 802.3 compatible network interface. It contains bits to select non-IEEE 802.3 network
operation, diagnostic modes (CRC enable/
disable for both receive and transmit), enable
receiving packets with errors (short frames,
dribble errors, CRC errors, overflow errors), select
byte order for 16 bit bus and enable automatic
receive end area update.

BUFFER
ADDRESS
X'OOOO'

BUFFER
CONTENTS
NEXT {
PACKET
POINTER
HEADER
COMMAND BYTE
HEADER
STATUS BYTE

BIT.

7

6

5

4

3

2

1

o

0

0

0

0

0

0

0

0

0

1

0

0

0

1

0

0

1

1

1

0

1

1

0

0

0

0

0

0

0

0

0

0

.1
----.,
----.,

X'OO'
X'44'

~

~

z
~

(5

z
>
c
C

:lJ

rnCJ>

Initialize Receive Pointer Register
Load this register with the same value as the
Receive Start Area (16 bit Transmit End Area
address plus hex 0100). Save this value, since it
points to the first byte of the next packet header,
and you will need it to find the next received
packet

~

C

:lJ

fri
c>
C

:lJ

~

C

In the example above, the Transmit End Area
address was hex 17FF. Therefore, the Receive
Pointer Register should be loaded with hex 1800.

~
X'OO44'

NEXT {
PACKET
POINTER
HEADER
COMMAND BYTE
HEADER
STATUS BYTE

Initialize DMA Address Register
If no packets are to be loaded into the transmit
area, load this register with the contents of the
Receive Pointer Register.

0

0

0

0

0

0

0

0

I~

1

0

0

0

1

1

1

1

~

1

0

1

0

1

1

0

0

0

0

0

0

0

0

0

0

X'OO'
X'SF'

~

~

z
~

(5

z
c>

Command/Status Register

C

:lJ

m

Set RXON (bit 9), and, if desired, Rx INT Enabl (bit
1) to ON Es. If you are not using interrupts, you
may poll Rx INT (bit 5) to see if a frame has
been received.

CJ>
CJ>

~

C

:lJ

C'l

m

>
c

Transmitting a Frame

C

:lJ

This discussion assumes that the system is connected to an IEEE 802.3 compatible network. The
contents of a Transmit frame have no meaning to
the Packet Buffer Controller and the Ethernet
Data Link Controller circuitry, and can be arbitrary in length and content. As discussed above,
transmission of the Preamble and CRC (frame
check sequence) can be suppressed under
software control for specialized network
requirements or diagnostic tests.
After you have gone through the configuring as
outlined above, the 8005 is ready to receive or
transmit frames. Refer to Figure 2 and recall that
a frame consists of from 64 to 1514 bytes, which
includes a 6 byte destination address, a 6 byte
sou rce add ress, and an area for data all of wh ich is
supplied by your system software. The entire
frame has a prefix containing a 62 bit preamble

seeQ

Technology. Incorporated

8-40

~
C

~

X'OOSF'

NEW PACKET
HEADER CHAIN
STARTS HERE.

LAST BYTE OF DATA

,----"

Figure 11. Transmit Packet Chain, residing
in the Packet Buffer, and ready to be
transmi~ed. Two packets are in this chain.
Note that the Packet Buffer is
nondestructively read, and the packets are
still in the buffer after they have been
transmitted. After transmission, the 8005
updates the Header Status Byte (byte 4).
The first two bytes of the Packet Header
pOint to the address of the first byte of the
second Packet Header.

(which synchronizes the phase-locked-loop in
the Manchester Code Converter with respect to
the received packet), and a 2 bit start frame
delimiter. Following the data field there is a4 byte
frame check sequence. All of the components of
the prefix and the CRC are supplied by the 8005.
A packet is prepared for transmission by writing
into the Transmit Buffer Area a 4 byte header,
followed by the destination address, the source
address, and finally the data field. Refer to
Figure 11. You may choose to do this via programmed I/O, or via an external DMA controller.
Frames may be chained together up to the
capacity of the available Transmit Buffer Area by
using the Next Packet Pointer (first two bytes)
and the Chain Continue bit (bit 6) in the Transmit
Header Command byte.

Refer to Figure 12. Read the Status Register to
see if the DMA FI FO direction is set to write to the
Packet Buffer(bit 15 cleared). If it is and the DMA
register is not going to be loaded with a new value
then data can be written immediately. If the DMA
register is to be changed, then check to ensure
that the FI FO is empty(Status Register bit 4 set). If
the FIFO is not empty, continue testing bit 14 until
the FIFO is empty. If you change the FIFO direction or write to the DMA Register, FIFO contents
will be cleared.
If necessary, load the DMA Register with the
address for the first byte of the Packet Header,
and write Packet Header and data into the FIFO.
The first Packet Header address is normallyOOOO.

SET FIFO TO WRITE
DIRECTION

SET FIFO TO WRITE
DIRECTION

LOADING TRANSMIT PACKETS INTO
LOCAL BUFFER PROGRAMMED 1/0

SET DMA INTERRUPT
ACKNOWLEDGE BIT

Figure 12. Loading Transmit Packets into
the local Buffer, under Programmed I/O
conditions. Note that, if you change the
direction of the DMA FIFO, or load the DMA
Pointer Register, you will lose any data
stored in the FIFO.

seeQ

DMA INTERRUPT

LOADING TRANSMIT PACKETS INTO LOCAL
BUFFER DMA TRANSFER WITH INTERRUPT

Figure 13. Loading Transmit Packets into
the Local Buffer under DMA transfer, using
Interrupt.

Technology, Incorporated

8-41

I

Figure 13 depicts the same operation, only under
DMA control, After you set up the system DMA
controller, set DMA ON (Command Register, bit
8), and DMA Interrupt Enable (Command Register, bit 0), if desired. The former enables the DMA
request logic, and the latter causes an interruptto
be generated at the completion of a DMA operation i.e., when terminal count has been input
After all of the packets in a given chain have been
written into the Transmit Buffer Area, load the
Transmit Pointer Registerwith the address of the
first byte of the first transmit packet header, set
TXON (bit 10) and, optionally, TXINTEnabl (bit 2) to
ONEs in the Command/Status Register.
The 8005 will then read the first header, which is
pointed to by the Transmit Pointer Register, and
process that packet, and all additional packets in
the packet chain in turn. Any retransmission of a
packet due to a collision will be automatically
handled by the 8005, thus relieving your system
from having to transfer that packet of data more
than once.
When a packet has been successfully transmitted (or 16 collisions occur), the Done bit (bit 7) in
the transmit header status byte will be set to a
ON E. The Transmit Buffer Area occupied by that
packet is now available for another packet, and
may be written to at the same time as subsequent
packets are being transmitted. The 8005 will
move to the next packet in the chain.
When all packets in a chain have been completed
(transmitted successfully or collided 16 times),
the 8005 resets TXON (bit 10) in the status register to indicate that it is ready to transmit another
packet chain. If 16 collisions occur on a packet,
the 8005 stops transmission attempts for that
packet only and moves to the next packet in the
chain, if one exists. In the example in Figure 11,
bits 2 and 3 are ON in the transmit header command byte which will cause the 8005 to set the
transmit interrupt bit in the status register and, if
enabled, interrupt the processor when 16
collisions occur or the transmission is successful.
The last packet in the chain is denoted by having
the Chain Continue bit cleared to a ZERO. The
Next Packet Pointer points to the address following the last byte of the last packet.
You may treat the transmit packet buffer in one of
two ways:
1. Asacircularbufferwithwraparound, where you
remember the address to load new packet

seeQ

headers and packet data The DMA register
automatically wraps around to address 0 when
the transmit end area has been reached.
2. As a linear buffer, where you reset the transmit
pointer to 0000 after each packet chain
transm ission.

Receiving Frames
Once the 8005 has been configured and the
receiver enabled, frames which meet the match
mode and station address requirements
specified in Configuration Register #1 and the
enable bits 2 - 5 in Configuration Register #2 will
be moved into the Receive Buffer Area beginning
at the address contained in the Receive
Pointer Register.
When one or more packets are available in the
receive area, the 8005 sets Rx Interrupt (bit 5) in
the Command/Status Register to a ON E. If
receive interrupts are enabled. (Command Register bit 1 set), then the external interrupt (pin 11) is
asserted. Frame header and data can now be
read by loading the DMA Register with the starting address of the Packet Header and executing
successive reads. If Auto Updat REA (bit 1 ofGonfiguration Register #2) is set, the Receive End
Area Register will be updated with the upper byte
ofthe DMA register each timea DMA read occurs.
This releases buffer space as its contents are
read, and allows forthe receipt of more data at the
same time as data is being read out
The action taken on a receive packet depends on
the status of the packet and its contents. If the
packet status is bad, it may be skipped entirely
without transferring any of its data to system
memory by loading the Receive End Area Register
with the most significant byte of the next packet
pointer. This will release the buffer space of the
previous packetforfuture packets. In likefashion,
if the packet data shows it to be an "overhead"
packet( such as a Packet Acknowledgement), this
can be so noted in network software and the packet
skipped Thus, unnecessary transfer of the packet
over the system bus can be avoided, and system
bandwidth preserved. If the packet data must be
processed, just the information portion of a packet
(exclusive of any bytes used to pad the packet to a
minimum size) can be read to system memory by
programmed I/O or by an external 0 MA controller.

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8-42

Receive Packet Chaining
The B005 automatically chains together receive
packets using a circular FIFO buffer structure.
Each packet is prefaced by a 4 byte header
whose first two bytes form a 16 bit address that
points to the next header. A chain of packets
always ends with a header-only packet whose 4
bytes equal 00. The address of this header-only
packet should be saved, since it will contain the
header of the next packet received. It is a simple
matter to follow the packet chain from header to
header until the chain Continue/End bit is read as
a ZERO, calculate the length of the chain and set
up the DMA Register and an external DMA controller to transfer the entire chain of packets to
system memory if desired. This is advisable in
applications where high average receive data
rates are expected and data must be moved quickly
from the local buffer to the system memory at the
expense of bus bandwidth. To minimize system
bus utilization, packets can be moved one at a
time; this permits moving only the information
content of a packet.
Calculating Packet Chain Length
In order to perform a DMA transfer, you need to
give the DMA controller the "counf'; Le., how
many bytes (or words, in a 16 bit system) will be
transferred. To do that, you need to calculate how
many bytes are available in the Packet Buffer as a
result of receive activity.
Refer to Figure 17. This flow chart illustrates the
steps required to calculate the length of the
packet chai n.
The first step requires that you know the Packet
Buffer address of the last packet header read in
the most previous receipt of Ethernet data. If the
B005 has just been initialized, the address is the
beginning of the Receive Packet Buffer which
was determined earlier in this note (hex 1 BOO). If
packets have been previously been read this
address will be the location of the header last
read that had the chain continue/end bit reset.
The next step, referring to Figure 17, is to turn off
the Auto Updat REA (Configuration Register #2,
bit 1). This insures that the B005 will not use the
area occupied by this packet chain for new
receive data.
Read each Packet Pointer in turn, and then read
the Header Status byte immediately after the
Pointer, which is Byte #3. Bit 6 of Byte #3 is the

Chain Continue bit. Continue reading this bit in
each packet header until this bit goes to ZERO.
This signals the end of the chain. Save the local
buffer address of the first byte of this last header
as this is the address of the header for the next
packet received. Subtract the address of the first
header in the chain from this address. If the result
is a positive number, you have the chain length
directly.
If the result is negative it denotes that the
Receive Pointer Register has wrapped around
past the beginning address of the receive area.
The chain length will be equal to the sum of the
receive buffer size plus the value (including sign)
of this result. You already know the buffer size,
since you defined it during configuration of the
B005: hex FFFF minus the receive start address
(defined during configuration) plus 1. Forthe previous example, the buffer length is hex EBOO
(FFFF - 1BOO + 1). Load the chain length into the
DMA controller, and set Auto Updat REA. You are
now ready to read data out of the receive buffer
and into system memory.
There are two ways to read Packets out of the
Local Buffer:
1. Via programmed I/O.
2. Via DMA transfer.
The front end portion of each procedure is the
same: first, check to see if the FIFO is empty; then
set it to Read. If the FIFO is not empty, check to
see if it is in the Write direction. If not, load the
DMA Registerwith the address of the next Packet
Header. If this is the first Packet to be read, this
address will be that which was derived when you
defined the Transmit Buffer size during configuration of the B005.
Reading Packets Using Programmed I/O
The data path between the local buffer and the
host bus is buffered by a 16 byte FI FO called the
DMA FIFO. It serves as a rate buffer between the
host and the local buffer, especially for 16-bit data
transfers. Because the local buffer is a shared
resource (there are 4 ports including the DRAM
refresh port), the initial read from the buffer
window which follows loading the DMA register
may take eight microseconds worst case. The
B005 signals this delay by deasserting Ready (if
Busmode= 1) or delaying DTACK (if Busmode=O). If
this initial read wait state is unacceptable, then
the buffer window interrupt feature can be used.

8-43

I

The buffer window interrupt is asserted for programmed I/O reads (not DMA reads) when the
DMA FIFO has data available.
Under Programmed I/O control (see Figure 14),
after you load the DMA Register, read Status
Register bit 7, Buffer Window Interrupt or wait for
a hardware Buffer Window I nterrupt if it is
enabled. When the interrupt is asserted, read
Packet Header and data out of the receive FIFO,
via the Buffer Window, until all bytes have
been transferred.

calculated packet chain length. Then set DMA
ON(bit8 intheCommand Register). Thisenables
the DMA Request logic inside the 8005.
Optionally, set DMA Interrupt Enable, which will
cause an I nterrupt to be generated when the
DMA controller has asserted Terminal Count. The
DMA Request output signal will be asserted when
there are a sufficient number of bytes in the DMA
FIFO to satisfy the DMA Burst Size (2,4,8, or 16
bytes) which you selected earlier when configuring the 8005.

Reading Packets Using DMA

Interrupts

The second approach is by DMA transfer. See
Figure 15. After loading the DMA Register, load
the system DMA controller with the destination
address in system memory, and the previously

There are several interrupt sources in the 8005.
This section describes these interrupts and how
to service them. For this discussion, refer to
Figure 18.

SET DMA INTERRUPT
ACKNOWLEDGE BIT

READING A PACKET FROM LOCAL
BUFFER PROGRAMMED I/O

DMA INTERRUPT

READING A PACKET FROM LOCAL BUFFER
DMA TRANSFER WITH INTERRUPT

Figure 14. Reading Packets out of the FIFO
using the Programmed I/O procedure.

seeQ

Figure 15. Reading the Local Buffer under
DMA control.

Technology,lncorporated - - - - - - - - - - - - - - - - - - - - - - - - - - -

8-44

Transmit Interrupts
There are four transmit interrupt sources in the
8005; Babble, Collision, 1 6 Collisions, and
Transmit Success. Each of these can set the
transmit interrupt bit in the status register if so
programmed in the transmit header command
byte. If Tx Interrupt Enable (Command Register
bit 2) is set, the 8005 will also assert an interrupt
on pin 11. The transmit interrupt is cleared by
setting TXINTACK (bit 6) in the command register.

Babble Interrupt
The 8005 will transmit packat'3 as large as will fit
in the transmit buffer. ThE;\ If FE 802.3 standard

specifies a maximum packet size of 1514 bytes.
The babble interrupt indicates that a packet
larger than 1514 bytes was transmitted.

Collision Interrupt
When a packet collision occurs, the 8005 packet
buffer controller automatically restores its
transmit pointer to the beginning of the packet
and schedules retransmission following the backoff time. In some applications it may be desirable
to record the number of collisions that occur. This
bit enables setting the TXINT bit in the status register for each collision.

=

CHAIN LENGTH
BUFFER SIZE +
RESULT

BUFFER WINDOW INT.

READING A PACKET FROM LOCAL BUFFER
USING BUFFER WINDOW INTERRUPT

Figure 17. The steps necessary to calculate
the length of a Packet Chain. You need to
save the address of the last header in the
last packet read, in order to perform the
calculation.

Figure 16. Reading a Packet from the local
Packet Buffer using the Buffer Window
Interrupt approach.

seeQ

Technology. Incorporated

8-45

16 Collisions Interrupt

PACKET
PACKET
BUFFER
BUFFER
ADDRESS CONTENTS
X'1800'
X'188E'
X'188F'

7

6

- - -1
".

2

1

..

FREE BUFFER

1

1

0

1

HEADER 1
OMMANDBYTE
HEADER 1
STATUSBYTE

1

0

FIRST {
PACKET
POINTER

1

1

The 8005 counts the number of collisions that
occur on each packet. If a packet has collided 16
times, the usual cause is a network fault such as
an unterminated coaxial cable or an open in the
cable. This interrupt notifies the host that a packet
has collided 16 times, and the packet buffer controllerwill now abandon transmit attempts forthat
packet and move on to the next packet in the
chain if one exists.

0

~~~:::::::-~----~
~

X'F840'

BIT"'"
4 3

5

Ol~

1

1

0

0

0

1

0

°i~

1

0

1

1

0

0

0

1

0

0

0

0

0

Transmit Successful Interrupt

cm
~

This interrupt indicates that a packet was successfully transmitted with less than 16 collisions.

Z

~

0

z
»
c
c

Receive Interrupts

The 8005 sets the receive interrupt bit (status
register bit 5) whenever a packet that meets the
criteria in bits 2 - 5 of Configuration Register #2
has been placed in the local buffer. It will remain
set and, if the receive interrupt enable bit is also
set, the external interrupt will remain asserted
until the receive interrupt acknowledge bit is set.
If a separate interrupt for each packet is desired,
the receive interrupt should be acknowledged
within 70 microseconds, which is the minimum
time for receipt of a subsequent 64 byte packet If
more than 70 microseconds elapses before
acknowledging a receive interrupt, it is possible
for additional packets to be added to the
packet chain.

:II

m

8!

~
c:

i!!m
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c

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m

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c

~
X'FC44'

PA~~~i

0----

0

0

0

1

1

0

0

1
POINTER
HEAD
COMMANDBYTE 1
HEADE R 1
STATUSBYTE

0

0

0

1

1

1

1

0

1

0

1

1

0

0

0

0

1

0

0

0

0

cm
~

The 8005 protects the receive interrupt condition
such that if a new interrupt is being generated
while the host is setting the receive interrupt
acknowledge, the receive interrupt will persist If,
however, a new frame is received after the
interrupt acknowledge and before the calculation of the packet chain length, the packet chain
which is read will include the new packet
associated with the new interrupt. The new
interrupt, when serviced, will now be associated
with an empty packet since it was part of the previous chain.

Z

»

::!
0

z
»
c
c

:II

m

8!
~

c:

:II

(")

m

»
c
c

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m

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c»

DMA Interrupts

~

X'FFFF'

Figure 17a. Example of two receive packets
in a packet chain with wraparound.

seeQ

The DMA interrupt bit in the status register is set
following receipt of terminal count from the
external DMA controller. If the DMA interrupt
enable bit (command register bit #0) is also set, an
external interrupt will be asserted. The interrupt
is cleared by writing a 1 to the DMA interrupt
acknowledge bit.

Technology. Incorporated

8-46

STATUS
REGISTER
Tx INT.ACK

~

I~
COMMAND
REGISTER

RxINT.ACK
COMMAND
REGISTER

BUF. WINDOW
INT.ACK

COMMAND
REGISTER

DMA INT. ACK

Figure 18. Functional diagram of interrupt logic.

Self-Test and Network Diagnostics

Interrupts

The 8005 contains a number of special features
for self-test and network diagnostic support

The 8005 has separate control bits for turning on
an off the receive logic, transmit logic and DMA
logic. The interrupts for these functions can be
tested without actually performing the function
by setting both the on and off control bits
simultaneously. For example, if the receive
interrupt logic is to be tested set both RXON and
RxOFF bits in the command register. This will
cause the receive interrupt bit in the status registerto be set and, ifthe receive interrupt enable bit
is also set, will cause an external interrupt This
mode has no effect on any logic other than the
interrupt logic and associated status register bit,
i.e., packets can be transmitted and received
while this diagnostic mode is set

Loopback
Two forms of loopback are possible with the
8005. Localloopback is accomplished when the
8005 is connected to an 8020 Manchester Code
Converter. When bit 11 of Configuration Register
#2 is set, the loopback pin of the 8020 will be
brought low. This causes transmitted data to be
looped back to the receiver of the 8020. If the
packet transmitted meets the match mode and is
addressed to one of the 8005's enabled station
addresses, it will be received and placed in the
local buffer. Using diagnostic control bits 9 and 10
in Configuration Register #2, it is possible to
transmit packets with CRC errors to check the
receive CRC logic, and to include the CRC in a
receive packet to check the transmit CRC logic.
Loopback can also be accomplished by connecting the 8020 to an Ethernet transceiver. Because
the network is half-duplex, any data transmitted
will also be received. Thus the same loopback test
as above can be performed while the network is
active by simply sending a packet to oneself.

seeQ

Detecting Network Cable Faults
It is possible to make a gross determination of
cable fau Its by taki ng advantage of the full-duplex
nature of the 8005: although it will not transmit
while receiving (that would violate the Ethernet
specification), it does receive while transmitting,
as long as the packet destination address fits the
receiver match mode.

Technology,lncorporated - - - - - - - - - - - - - - - - - - - - - - - - - -

8-47

Cable Opens/Missing Terminator
An open coaxial cable or a missing cable terminator results in the transmission line being terminated in an infinite impedance. Thus, any data
transmitted will be reflected back from the
impedance mismatch some time delay after it is
transmitted. This time delay depends on the
physical distance to the impedance mismatch, so
the length of the packet must be large enough to
insure that data are still being transmitted after
one round trip propagation delay to the mismatch. A 256 byte packet should be an adequate
size. The reflected signal will partially cancel the
transmitted signal and cause a collision to be
detected by the transceiver. Thus an open is.
indicated by repeated collisions when transmitting a packet or, ifthe network is known to be quiet
(no other nodes active), a single collision when
transmitting. It is also possible to make a rough

seeQ

determination of where the fault is by enabling
receipt of packets with errors (Configuration
Register#2 bits3- 5) and then counting the number of bytes correctly received. Note that if the
cable open is very close to the transmitting node,
the collision may occur during the preamble and
the 8005 would unconditionally reject the
receive packet
Cable Shorts
A shorted coaxial cable causes premature loss of
carrier sense to the receiver of the 8005 while it is
transmitting. It is therefore possible to send a
packet of at least 256 bytes to oneself with the
receiver enabled to accept frames with errors. A
cable short results in a truncated receive packet;
the size of the receive packet indicates the rough
distance to the cable short

TechnologY,lncorporated - - - - - - - - - - - - - - - - - - - - - - - - -

8-48

Memory Products
Application Note

EEPROM
INTERFACING
April 1987

I
seeQ
Technology, Incorporated

8-49

EEPROM Interfacing

Introduction
The continuing rapid evolution in semiconductor
E2ROM memory device technology offers the system
designer an ever-increasing choice of function and
capability. With these increasing choices for E2ROM
devices, however, comes the problem of standardization (or lack thereof) concerning such specifications as
endurance, timing characteristics, interface requirements, ad infinitum. Today, there are two popular types
of commercially available E2ROM devices.
Both of these types of devices have the JEDECapproved pinout shown in Figure 1, including the
multi-functional pin 1, but differ in the timing of the
control interface. The first E2ROM type, the latched
type device, such as SEEQ's 52B33 latches the addresses, control, and data inputs on the falling edge
of WRITE ENABLE (WE). For this type device, the
WE input must remain active low for the duration of
the write cycle. The second type of E2ROM, the timertype device, latches addresses, data, and control signals on the rising edge of WRITE ENABLE or the
rising edge of CHIP ENABLE (CE). For the timer
device, such as SEEQ's 2864 the WE input need not
be held low for the entire write cycle. The primary
difference between the latched and timer devices is
the control timing required to interface to the microprocessor. Each of these types of devices has advantages depending on system performance and configuration requirements.

I

28

A'2
A,

3

2.

A6

•

As

5

2

27

Vee

MF

WE

A12

2

27

A,

J

"

I

26

A6

•

2~

24

A9

A,

'

24

Ag

A11

A4

6

23

Al1

~~
eE

:~

:

64K:~ ~

23

A3

7

64K::

2.
"
"
17
16

15

It is hoped that these example interfaces will assist the
system designer in implementing E2ROMs in his system. By no means are these special cases presented to
limit the system designer, but to provide a starting point
for his design. The interface circuits presented are for
the family of E2ROM devices (16K, 32K, and 64KL
Other extensions of the ideas presented may permit
lower power, lower cost, or optimization of other
parameters deemed more important.

Vee

2S

6

The microprocessor interfaces described in this application note are for the 8085, 8086, 8088, Z80~ and
71840. Software examples are provided for the Z80 and
71840 processors. By extension, the Z80 code is easily
transportable to 808X processors. In most cases, the
hardware required for compatibility consists of only two
additional standard (14-pin) TTL packages.

WE

N/C
A8

A4

One of the most frustrating problems facing a system
designer is the design of an E2ROM/microprocessor
interface that will allow compatible operation of timer
and latched type E2ROM devices in the microprocessor-based system. The purpose of this
application note is to give examples of cost-effective
designs of E2ROM/microprocessor interfaces, which
allow the use of both timer and latched E2ROM devices
in the system with no changes required to either the
controlling software or the hardware. With the interfaces shown in this application note, it is possible to
operate with BOTH latched and timer devices simultaneously in the system if the device access times are
compatible.

TIMER
SEEQ 2864

LATCHED
SEEQ 52833

CC

When the designer attempts to use the advantages of
botl:! in the same system, a problem is encountered.

II0a
liD,
110 6
liD,
liD.

Figure 1. JEDEC Pinout -

I.

2.

A,
Ao
"
11
liD,
"
12
1/0 2
17
16
1/0 3
GND ~_ _.' 5.r

"
"

N/C
As

The body of this application note consists of two sections. First, the Basic Operation section gives the
theory of operation of all of the interfaces and should
be read to familiarize oneself with those factors common to all of the microprocessor interfaces. Second,
the Microprocessor Interface section details the design
of the TTL interface required for the given microprocessor.

CE
II0a
liD,
110 6
1/0 5
1/0 4

64K E2ROMs

seeQ Technology, Incorporated - - - - - - - - - - - - - - - 8-50

Basic Operation
Each of the E2ROM microprocessor interfaces described in the next section integrates hardware and
software to achieve compatibility between latched and
timer E2ROM devices. Naturally. both hardware and
software are processor-dependent. However. the write
cycle used is basically the same for all the examples
shown.

For compatibility between the latched and timer E2ROM
devices. the interface provides control waveforms that
have timing compatible with both. since the major difference between latched and timer E2ROM devices is
the timing of the write control interface to the microprocessor (see Introduction). The basic waveforms for
latched and timer E2ROMs are shown in Figures 2a
and 2b. respectively. The latched type E2ROM device
acquires data on the leading edge of WRITE ENABLE

ADDRESSES

YiE------I.-.-.I.

1/0
(WRITE)

HIGHZ

1/0
(ERASE)

HIGHZ

i - - - - - - B y T E ERASEIWRITE PERIOD-------..I.-START OF NEXT MODE

Figure 2a. Latched E2ROM Write Cycle

ADDRESS

t------iwp------

HIGHZ

DATA OUT

DATA IN

DATA VALID

1-----105-----1+--

Figure 2b. Timer E2ROM Write Cycle

seeQ Technology, IncotpOl8ted - - - - - - - - - - - - - - - - - - - - 8-51

I

(WE). The timer type device acquires data on either the
trailing edge of WE or the trailing edge of CHIP ENABLE (CEL Interface compatibility is achieved between
the latched and timer devices by strobing the data, control, and addresses on the leading edge of the Write
Enable pulse for the latched device and then by strobing the data on the trailing edge of CHIP ENABLE for
the timer device (see Figure 3). By using this technique,
the hardware interface is greatly simplified.
The software part of an E2ROM interface is very simple,
but very important. A read operation for both latched
and timer E2ROM devices is accomplished by a
straightforward issuance of a microprocessor Read

Ao-Al0

II01-I/Oe

X

VALID

~

VALID

CE\
WE

~:7I/////&
~ ;71//////4

I
\

5

'--------II

OE

~

\\\\\\\\\\

r-----1

IU-

Figure 3. Latched/Timer Compatible E2ROM Write Cycle

ADDRESSES

command at a particular address (see Figure 4), A write
operation, however, involves a more complex process.
The flow chart for writing to the E2ROM is the same for
all microprocessors and is shown in Figure 5. After a
Write command is issued, time is required to allow
proper writing to the storage cell of the E2ROM device.
A Read command is then issued to terminate the write
operation. Note that this Read command is not to be
used to actually read the E2ROM device, but is inserted
to reset the logic circuits used to drive the WE input of
the E2ROM device.
Between initiation and termination of a write, cycle, the
interface uses some timing mechanism to assure
proper write conditions to the E2ROM and to know
when the E2ROM is available for another read/write
cycle. The duration of the timeout (twp ) depends upon
the type of E2ROM used. For all.types, twp should fall
between the minimum and maximum specifications of
all E2ROMs for which the application is designed. The
latched type, of device requires less write time than
does the timer type device.
The implementation of this timing can be accomplished
in either hardware or software. In hardware timing, a
timer can interrupt the processor at regular intervals, or
at the end of the desired write time (twP)' In software
timing, the processor simply counts down, waiting for
the desired t wp . For ease of general implementation,
the given examples utilize software timing (see Figure
5), The tradeoffs, however, between software and
hardware timing comprise an involved topic. The system designer must make this decision, considering
such factors as processor throughput, board space,
and expense.

ADDRESSES
VALID

OUTPUT __________________~--H~IG~H~Z~------+_+_+_+_~

HIGH Z

~-----IACC-----.,

Notes: 1. OE may be delayed up to tACC - tOE after the falling edge of CE without impact on tACC.
2. tDF is specified from OE or CE, whiChever occurs first.
3. This parameter is periodically sampled.

Figure 4. E2ROM Read Cycle

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-52

WAIT ROUTINE

WRITE ROUTINE

After the cycle described by Figure 5 is complete, the
E2ROM device is available to be accessed for another
Read or Write command. Often, another read will be
performed in order to verify the written data. With the
solution proposed, this subsequent read cycle will have
normal timing, and all required write recovery parameters will be satisfied.
The general description provided above applies to most
of the processors shown in the specific examples
below. For more detailed information, the reader should
refer to the schematic, waveforms, and software that
apply to a specific processor.

Microprocessor Interfaces
8085 Interface

The schematic for the 8085 interface to a timer or
latched E2ROM device is shown in Figure 6. This interface consists of one each of a 74LS02 and 74LS74 type
package and allows the system designer to use the WR
signal from the 8085 to initiate the write cycle to the
E2ROM device. The design permits use of either a timer

Figure 5. Software Flowchart - E2ROM Write Cycle

,-1---,
I
.----------H
D

P

I

SYSTEM RESET

I
.------t--P
I

I
C

I

-'1'

I
I

I

I

a~

74lS74

I

RDb------------------+---------+----------~I------_+_+_+--~6E

I
ViR
ClK

b---------------_..-+--------------------yl D

J--------+-f-!-~--01~-

.--___--., ~~:
~"''' i

101M J-----~E

A11- A15

1 oJ>
..-_-_I_r-I--=C=lKc:..:W
.:....:-

Ox ~

~---~~,I

-------v-

/1

I

~
p

~
at-J4 -----t----q WE

~W-

~ - t,~ J

_

»-/r----------------------t----Q CE

L_~__- __- __-__
- ___
- ~____________________~
DECODER

8085

E2ROM

OCTAL
lATCH

I--__________________....,~/ I Ao-A7

I

AlEI----------------------~

ADO-AD7

~

1"'1~-------------------------------------------------------v

A10 J - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - y l Aa-A10
Aa-_
_______
________
~

v~

~

Figure 6. 8085/E2ROM Interface

seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - -

8-53

OR a latched E2ROM device with no change required
to the controlling software or hardware. The following
discussion of the operation of the 8085 interface relies
on the 8085 timing diagram summary for read and
write cycles shown in Figures 7a and 7b respectively.

/

ClK'

Aa-A15

ADo-AD7

ALE

\

X

ADDRESS

X

ADDRESS

J

Initiating a write cycle requires the software control
routine as charted in Figure 5. Should the reader desire
a specific example, the Z80 code (see Figure 12) is
transportable to the 8085.

x
""~
) ~--(J ttjT
,eLi'IX

)>---«---

DATA IN

\~------------------------/
\

RD/INTA

Figure 7a. 8085 Read Timing Summary

/

ClK " \

Aa·A15

ADo-AD7

ALE

J

X

ADDRESS

X

ADDRESS

/

\

\

\

/

X
X

DATA OUT

X
/

\

WR

I

/

\

Figure 7b. 8085 Write Timing Summary

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - 8-54

for the entire write time of the E2ROM device. In this
manner, the waveforms shown in Figure 3 are produced, providing signals compatible with both the
latched and timer type devices.

The basic write operation waveforms for this interface
are shown in Figure 8. The write cycle begins with the
addresses becoming valid and being decoded to drive
SELECT active low, in order to drive the CHIP
ENABLE (CE) active low at the E2ROM device pin
(selecting the desired device) (see
in Figure 6), An
active low level on WR from the 8085 (indicating a write
cycle initiation) allows the WRITE ENABLE latch of the
interface to be clocked by the next falling edge of the
8085 clock output (ClK) (see
Addresses, data,
and control inputs to the latched type E2ROM are
latched in at the falling edge of WRITE ENABLE (WE)
- shown as
in Figure 8. For the timer type E2ROM
device, however, data is latched on the rising edge of
CHIP ENABLE (CE) - shown as
in Figure B.
Note that CE is held active low for a relatively short
period of time, while WRITE ENABLE (WE) is held low

0

To end the write cycle, the 80B5 issues a Read command to the E2ROM device. This read cycle enables the Write Reset latch which in turn presets the
WRITE ENABLE latch (shown in Figure 6). The preset
in Figure
to the WE latch brings WE to VIH (see
8), As indicated in Figure 8, this read cycle does not
produce valid data from the E2ROM. This read cycle is
used merely to terminate the write cycle.

® ).

@

®

©

The latched and timer devices respond identically in a
read cycle. The B085 read cycle, shown in Figure 7a,
produces the read cycle waveforms shown in Figure 4.

WRITE CYCLE
INITIATION

WRITE CYCLE
TERMINATION

VALID

VALID

ADO-AD7

DATA

I
• i>

I

I
I

C

Y

I

I
I

I

I

H-

74LS74

~p_--------~~---~----~Ir_---+_r_r_~~

-----,
1Fr2

WRb-----------, ~--------.--~I 0
~ I

I

....-_-+__

74LSD2

,--~I

zaD

SELECT ~

All-A151--_~y/1
REFRSH 10-----1

I

I

Co...L-,-KW,,-,:-1-[>

L-

r-+P

Q~+-I-4--aWE

I

~

t -J
Q

: 1
!2.2K
)o-It"""-.......--------+--...q CE
L- _ _ _ _ ..J

I

DECODER

E2ROM

A

\.r,,---------------------------v...

0 0-07

An-A10

1/01-I/Oa

r--___________________________v(Ao-A10

~------------~

~------------~

Figure 9. Z80/E2ROM Interface

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - 8-56

WRITE CYCLE
TERMINATION

WRITE CYCLE
INITIATION

Figure 10. Timing Diagram -

E2ROM Interface (Write Cycle)

The termination of a write cycle is very straightforward.
As shown in the Basic Operation section (see Figure 5),
a read operation to the E2ROM terminates the write
cycle, but does not provide valid data. For the interface
operation in write cycle termination, the reader should
refer to Figure 10. The addresses are brought valid on
the address bus, and are decoded to drive SEL active
~Figure....!...O). The gating circuitry, howlow (see
ever, inhibits CE, and CE remains at VIH. At the rising
edge of RD, the flip-flop receives a positive edge
trigger, and clocks in the SEL Signal to preset the WE
latch. At this pOint, WE is brought high (see
in Figure 10), terminating the write cycle. For the remainder

@

@

of this processor bus cycle, CE becomes valid for a
short while. However, RD is no longer active low, and
no valid data is read in this bus cycle. There is no problem with tWR since the write recovery time occurs
during the remaining part of this bus cycle.

Frequently, one may wish to read again from the
device, in order to verify data written. This read will be a
normal read, following the general waveforms of Figure
4. In a read operation, the interface drives CE active low
to select the device, and RD enables the output from
the E2ROM device.

seeQ T e c h n o ' o g y , ' n c o r p o r a t e c l - - - - - - - - - - - - - - - - - - - - - - - 8-57

I

J\

CLOCK

;;

X

AO-A15

MREQ

AD

VALID ADDRESS

x=

::

\

if

lj

\

l5

l5

/
/

READ
OPERATION

00-07

===>

~~~~

l~

::

f

~f

WR

DATA

rr--i

WRITE
OPERATION

00-07

:~

<

DATA OUT

r---

Figure 11. Z80 Read and Write Cycle

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - 8-58

LaC

EEWRZ80.1
OBJ CODE M STMT SOURCE STATEMENT

009B
0090
009E
OOAI

3EFF
12
CDAEOO
lA

00A2
00A3
00A4
00A7
00A8
00A9
OOAA
OOAD

78
12
CDAEOO
lA
lA
B8
C2C800
C9

OOAE

78

OOAF

00B2
00B4
00B5
00B7

00B8
OOBA
OOBB
OOBC
OOeF
OOCO
00C3
00C6
00C7

3E07
47
3E06
4F

3EOO
OB
B8
C2BAOO
B9
C2BAOO
3A02CO
47
C9

175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230

ASM 5.9

;--------------------------------------

Z80 EEROM Write routine.
Incorporates auto-erase and timing
in soFtware.
Accepts: address to be written: Reg DE
Data
to be written: Reg B
Uses: A, B, D, E Destroys: A

EEWR:

LD
LD
CALL
LD

A,OFFH
(DE), A
WaitTwp
A, (DE)

; FF for erasure.
BEGIN ERASE

LD
LD
CALL
LD
LD
CP
JP
RET

A,B
(DE), A
WaitTwp
A, (DE)
A, (DE)

Data to be written
; BEGIN WRITE

B

END ERASE

Read to end Write
Read to Ver-ify
Check VeriFication

NZ. ERRI

., ----------------------------; Wait routine For EEROM Byte/ Erase
; Uses: Registers A, B,C
; Destroys; A,C

,-----------------------------WaitTwp:LD
A,B
Store B reg in TMPI
LD
(TMP1), A

Set timing constant for Twp.
This 16-bit constant is loaded
into Registers BC, and depends
on the speed of the CPU clock.
LD
A, 07
LD
B,A
LD
A, 06
LD
C, A
The following loop perForms the wait,
by decrementing BC until the 16-bit
number contained in BC equals zero.
Mor-e:

DUN:

LD
DEC
CP
JP
CP
JP
LD
LD
RET

A, OOH
BC
B

NZ, Mor-e
C

NZ, Mor-e
A, (TMPI)
B,A

Restor-e B Reg

I

Figure 12. Z80 E2ROM Erase/Write Routine

seeQ

Technology, IncotpOl8ted - - - - - - - - - - - - - - - - - - - - -

8-59

8088 Interface
similar device, eliminates this problem. Since the
74lS74 operates from bussed control and data lines, its
requirements are not so stringent, and a 74lS74 will
work fine in most applications.

An example interface is shown between an 8088 (operating in minimum mode) and a 16K E2ROM (see Figure
14). The reader may note that this is almost identical to
the 8085 E2ROM interface (see Figure 6), with only
minor differences. First, the NOR gates used cannot be
a standard TTL or lSTTl device, but must be a CMOS
or other high impedance input, so that the ClK signal
is not loaded. The ClK signal, as output by the 8284, is
used as the clock input to the 8088. The VOH level on
this signal can fall below specification as a result of a
TTL load. A CMOS NOR package, such as a 74C02 or

The operation of this circuit is almost identical to the
operation of the 8085 interface, as a comparison of the
timing diagrams will show (see Figures 7b and 15)
Because these processors share similar bus timing, the
signals differ only in magnitudes of setup and hold
times. All required setup and hold times should be confirmed to the satisfaction of the system designer.

ClK (8284 OUTPUT)

X'---__~___x=
~X~______
X~
J)(~_______
X
X~

IO/M,SSO

A15-Aa

______________
A_15_-Aa
__
(F_lO_A_T_D_UR_IN_G_I_NT_A_)______________

A19/S6-A 16/S3

ALE

READ CYCLE
NOTE 1)
(Wii,
VOH)

w& ~

f~-~o

A19-A16

_____________S_7-_S3______________

r--

I

\ "'----------------------------_------""'- -_ ..
I

X

AD7-ADo

>

f~~o

X

A D7-ADo

X
\

WR

Figure 13. 8088/8086 Bus Timing -

(

>

DATA IN

\

RD

WRITE CYCLE
NOTE 1

FLOAT

FLOAT

C

/

X

DATA OUT

/

Minimum Mode

seeQ T e c h n o ' o g y , / n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - 8-60

i

r--±-~
D

SYSTEM RESET

I

f

I
C

I
I
I

\Vii

r-----,

ClK
FROM
8284

I~
74C02

I

I

I

i&=?:
I

OUTPUT

Ox~

M/iO

~

.J\.

Al1-A15

-v

I

I
I

I
I

I
I

74lS74

I
OE

I
RESET

aH-

Y

I

AD
Lc

P

D

.r-+aI
P

WE

I

aH--

ClKWI

L-t,:;:J
+5

CE

____ .J

DECODER

8088

E2ROM

OCTAL
LATCH

A{J-A7

ALE

.

J.,

.A

ADo-A07

;:.

..

....

1101-1108

....
As-A10

As-A10

Figure 14_ E2ROM Interface - 8088 (Minimum Mode)

I
E7~~~TKh~/~~m~~~Md---------------------------------------------8-61

'Ao-A19: ADDRRESS SIGNALS MULTIPLEXED WITH STATUS AND DATA SIGNALS MUST BE DEMULTIPLEXED USING OCTAL LATCHES.

Figure 15. Timing Diagram - 8088/8086 E2ROM Interface

8086 Interface
A sample E2ROM interface shown for the 8086 (see
Figure 16) compares very closely in layout and operation to that for the 8088 (see Figure 14), The 8086
interface accounts for the 16-bit 8086 data bus by latching both bytes of address and implementing a pair of
devices to read and write an entire word at a time.
E2ROM interface control signals are identical to those
for the 8088 interface (see Figure 15),

seeQ T e c h n o l o g y , l n c o r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - 8-62

.--------~-+~
1_4~ ~ 11

"'' r """

:

il-;::::=::!=:::::;:------i-----'1-117:::4ls74 I
L<

RD~-----_+------~_7~~~.-~rrQOE

RESET

OE I O - - - - - H - - - - - - - ,

r - - - --1

ClK 1 - - : - - - - - - - + - 1 - + - 0 1

F~~8~

I~

II

OUTPUT

MIlO r-----

I

I

lOp QI--:-I-+---I-CfWE

I ClKW

I

I

I

L -

;lL.

C~
-

.J

1

~4C02 I

DECOD~~ ~=

SEl

}Ot,I---+---+--+-<:t CE
I

I

_ _ _ _ _ .....1

+5

fr ,

~

l:

4.05

Z

W4.00

t:::
a:

3: 3.95
3.90

.-=:--=------.1...-.----------'
AVERAGE
MAXIMUM

3.85
MINIMUM

MIN, AVERAGE AND MAXIMUM Vwi

Figure 1. WRITE INHIBIT VOLTAGE-28C256 AND 28C64

8-79

RAW DC

+5 VOLT
REGULATOR

Vee

Vee

Vee

EEPROM
HC32

Figure 2.

dependent, a POWER FAILURE IMMINENT
(PFI) signal can be generated at least 10 'ms
before Vcc fails.
This PFI signal can then be used to warn the
system processor that there is time for only one
more programming cycle before shut-down. Up
to 64 bytes of data can be stored in one 10 ms
programming cycle and return to its standby
mode before Vcc fails. The final store is accomplished, and all data is intact.
Now we must turn our attention to disabling the
EEPROM when Vcc is between 3.8 volts and
4.5 volts.

B. Multiple Control Pins
There are three control signals on SEEQ's
EEPROMs, and each signal must be at the
proper logic level for a write cycle to begin.
Therefore, writes can be inhibited if any of the
following input conditions are met:

seeQ

CE

WE

OE

Vee

WRITE MODE

VIH

X

X

X

INHIBITED

X

VIH

X

X

INHIBITED

X

X

VIL

X

INHIBITED

X

X

X

BELOW
VWI

INHIBITED

1. 3.8 < vwi < 4.25
2. X - Don't Care
3. All other inputs are don't care
4. Set-up and hold times on transition are in the specific data
sheets for each part.

By using an HCMOS logic gate and a RESET
signal (see figure 2) we can force anyone of the
control lines to a known state to disable the
EEPROM when Vcc is below 4.5 volts. We could
also use the RESET signal to remove power
from the device, which will accomplish the same
thing. An HCMOS gate should be used since it
will drive the control line to either power rail
even with Vcc as low as 3.0 volts.

Technology. Incorporated - - - - - - - - - - - - - - - - - - - - - - - -

8·80

Why must we have a separate RESET line?
Why not use the PFIline to disable the EEPROM?
Well, that would allow the EEPROM time to
finish an internal programming cycle before Vcc
fails, but there are several problems with this
approach.

would be the system's normal RESET line (see
figure 2).

EXTERNAL WRITE-PROTECT
CIRCUITRY (SEE FIGURE 2)

First, during power-up, the unregulated voltage
could be above threshold (enabling the EEPROM) some time before Vcc has reached 4.5
volts. This could lead to false writes. Second, if
the EEPROM is disabled as soon as an imminent
power failure is detected, the system would be
unable to initiate any final programming cycles
prior to shut-down. This could lead to the loss of
valuable data.

In this circuit, the RESET signal will disable the
EEPROM and hold the JLP in RESET any time
Vcc is below 4.5 volts (or whatever other threshold is chosen). This will prevent any false writes
from occuring during power-up. However, the
RESET line will only prevent false writes during
power-down if the EEPROM was not already in
an internal programming cycle. If this does
happen, only those bytes which were being
reprogrammed could possibly be corrupted.

From this, we can see that the EEPROM disable
signal must be generated from a low voltage
detector on the Vcc line. This disable signal

The PFI signal will prevent this from happening,
as well as allowing the system enough time to
save any vital data prior to power failure. By

RAW DC

+5V

vee

REGULATOR

vee
SENSE
RESIN

SENSE
TL1715A

CT

RESIN

cT

REF
GND

RESET

TL1705A
REF
GND

0.1 /-LF

vee

HC32

EEPROM

/-LP
NMI

PFI

RESET
RESET--~--------------------------------------~

Figure 3.

seeQ

Technology. Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

8-81

I

making Cf large enough (which is load dependent), PFI will warn the #LP 10 ms before Vcc
fails. After being warned, the #LP can initiate one
more programming cycle. The EEPROM will
then have enough time to complete its internal
programming cycle before it is disabled.
In conclusion, the possibility of false writes can

be totally eliminated if the system makes use of
a RESET signal and a PFI signal in combination
with SEEQ's on-board write-protection Circuitry.

A MONOLITHIC SOLUTION
(SEE FIGURE 3)
An alternative to using op-amps and discrete
components to produce the PFI and RESET
signals can be seen in Figure 3. This circuit
makes use of a monolithic supply voltage supervisor family from TEXAS INSTRUMENTS. These
devices are useful to detect power-up, powerdown, and brown-outs. In addition, Ct can be
chosen to determine how long the RESET
signals will remain active after Vcc is above
threshold, which guarantees proper system initialization on power-up. The reader should refer
to T.I:s data sheet for details.
In this example, a TL7715 is used to produce
PFI while a TL7705 is used to generate the
RESET signal. This arrangement ensures that
the EEPROM is disabled anytime Vcc is below
4.5 volts, and the PFI warning is issued anytime
the raw DC powering the system falls below
13.2 volts. (See TL7705 and TL7715 data sheets
for detailS).

seeQ

Lets assume that:
a. power is lost abruptly
b. Vf of 01 is 0.7 volts
c. The drop-out voltage of the regulator is 2.0
volts
Then we can see that the voltage across Cf
must take at least 10 ms to drop from 12.5 volts
to 7.0 volts at the given load, II. (13.2 - 0.7 =
12.5 and 5.0 + 2.0 = 7.0). Since II = Cf dv/dt
and dv = 5.5 volts, dt = 10ms, we have this
relationship: II = 550 Cf·
In other words, if II is 550 rnA, then Cf must be
1000 #LF for proper operation of the PFI
protection.

CONCLUSION
Designers must be careful to avoid false writes
to a system's EEPROM during power-up, powerdown, and brown-outs. This is especially true in
CMOS systems where "brown-outs" are often
entered purposely to achieve low Vcc/low power
standby states.
We have seen that to completely eliminate the
possibility of false writes, the system must
monitor the voltages on both sides of the Vcc
regulator. This is true whether software or hardware write-protection is used.
SEEQ Technology has incorporated all of the
on-chip hardware write-protection needed to
design a trouble-free system using EEPROMS.
In addition, this form of write-protection is completely transparent to the system, making the
software interface more convenient.

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - -

8-82

Memory Products
Application Note

EEPROMASA
SUBSTITUTE FOR
BUBBLE MEMORY
October 1987

I
seeQ
Technology, Incorporated

8-83

As more systems designers are dropping bubbles,
EEPROM-based designs are rapidly increasing.
In the early to mid 80's, we were told bubbles
would take over mass storage designs. Surely
bubbles were the design of the future for core
memories and even to replace disc memories. As
many of these dreams fade, let us consider some
of the pro's and con's of each technology.
Common design considerations include densitS',
power consumption, weight, access time, data
rate, and environmental susceptability.
Density is certainly one issue that gets a lot of discussion. Commonly available 4 megabit bu.bble
packs are approximately 1.25 cubic inches forthe
basic block. SEEO Technology's 256K PLCC
package has a volume of approximately .0125
cubic inches or 1% of the volume of the bubble
pack. Therefore, an equivalent 4 megabit EE
memory using 1 6 256 Kbit devices has less than
20% of the volume ofthe bubble memory. Mounting
of either device was not taken into consideration;
neither was the volume of the required support
chips. The EEPROMs would take more area
mounted than was implied strictly with a volume
specification. Spacing between packages could
increase total volume, although the ratio between
EE and bubble would still be substantial.

Additionally, the high profile of a bubble memory
device would greatly increase overall board
volume as boards cannot be spaced closer
together than the tallest component height
Decoding of a 4 megabit EEPROM array can be
done with a simple one-of-sixteen decoder such
as the 74LS154. In comparison, that 1.25 cubic
inch bubble pack required a series of controllers,
coil drivers, current drivers, etc. In the final
analysis, semiconductor EEPROM memory will
occupy a fraction of the space of bubble memories.
Access time is the time from the issuance of the
valid address or name of a file, data block, word or
byte until the first full size segment of data is available. A full size segment would be the first bit of a
serial data stream or the first full byte or word in a
parallel data bank. Common 4 megabit bubble
memories today have average random access
timeson the orderof50 t090 milliseconds. Some
of the new small size modules have average
access times less than 1Oms, but specify maximums
above500ms. SEEOTechnology's28C256 hasa
maximum access time of 250 nanoseconds.
Comparing the two technologies, bubble
memory's average access time is 200,000 times
longer than the EEPROMs worst case; the
EEPROMs could deliver 200,000 bytes of data
while the bubble memory is accessing the first bit

FIGURE 1
COMPARISON CHART
BUBBLES TO EEPROMs

Power Consumption

Access Time in microseconds
Average Data Rate
(Read) K Bits/Second
Data Rate
(Write) K Bits/Second
Weight (Grams)
1 Megabit Volume
(Unit onlyt Cubic Inches

---

BUBBLE
5

EEPROM
.5

RATIO
REMARKS
Considerable current
10/1
would be drawn by
bubble memory
support circuitry
200,000/1
1/256

50,000
125

.25
32,000

125

800

1/6.5

75
1.25

5
.2

15/1
6/1

SeeQ Technology, Incorporated
8-84

4 Megabit bubble and
sixteen 256K EEPROMs/
shown in fig. 3
Does not include
bubble support chips

Weight is one area that seldom becomes an issue
in most designs but does come up on occasion.
Once again, the comparison is not straight forward.
Basic bubble memory devices commonly have
weights in the vicinity of 75 grams per 1 megabit
device. This, of course, does not take the weight of
support circuitry into consideration. The
equivalent EEPROM bank of four 256K devices
would have an approximate weight of 5 grams.
With the bubble memory support devices also
taken into consideration, the ratio would
significantly surpass this 15 to 1 ratio.
Power consumption almost always warrants
some consideration. Four megabit bubbles have
power supply requirements around 4 watts typical
and greater than 5 watts maximum. Sixteen (16)
of the 256K type EEPROMs and a one-of-sixteen
decoder under worst case conditions would draw
less than 100 ma at 5 volts. This would be one-half
watt or about 10 percent of the power of a bubble
memory. While the sixteen 256K's only require a
single decoding chip for support, the bubble
requires numerous support chips. This support
draws power too. To get a realistic feel for bubble
power consumption, it becomes necessary to
examine then at the board level where the host of
necessary support devices are installed.
The boards considered for comparison were not
expandable, that is to say they were fully stuffed,
4 megabit boards. Power consumption on these
boards runs between 10 and 20 watts. Additionally,
there were multiple power supplies required, not
thesingle5 voltsupply required by the EEPROMs.
Data rate is the speed at which the data can be
continuously delivered to the addressing device.
In this area the bubble is specified at maximum
(burst) and average. Burst data rates can be fast
as 200,000 bits per second. Average data rates
can be on the order of 125,000 bits per second.
Making the EE comparison, data rates are the
same as access times, and therefore 250
nanoseconds per byte (8 bits). Putting this in
perspective, after the bubble has taken 88
milliseconds to get started (initial access time),
while the bubble is fetching 256 bytes the EEPROM
could deliver 65,536 bytes.
Data rate does not imply direction. This is to say
that data rate does not apply only to reads of data
but also to data writes. F or a bubble memory, read
and write data rates are equal, but the rates differ
when EEPROMs are used. Read data rates were

seeQ

discussed above. Write data rates in EEPROMs
are a bit more complex. In high density EEPROMs,
byte write times and page write times are the
same. A "page" is 64 consecutive bytes of data
This page of data can be loaded as fast as 350
nanoseconds per byte, thus a page load would
take 22.4 microseconds. Afterthis time, a maximum
of 10 milliseconds is required for the write cycle
to complete.
The microprocessor's write data process must
halt during this 10 milliseconds until the device is
again ready to load another page and begin the
10 millisecond write sequence again. This would
imply a write data rate of 350 nanoseconds per
byte "burst-mode" with a maximum of 64 bytes or
an over all rate of 6400 bytes per second. This
6400 bytes per second rate is comprised of one
hundred 10 millisecond write sequences of 64
bytes. While 6400 bytes per second (this would
be 51.2 K bits per second) is about half the speed
of the bubble's write data rate it can be improved
manyfold for systems using multiple EE Devices.
In the case of medium to large arrays, which
would be the case in mass storage applications,
the common approach is to decode chip selects
from the high-order address inputs (see figures 2
and 3). But pOSitioning the chip select decoder in
the address space immediately above the page
address inputs would allow each consecutive
device to store the next logical page.
Applying this approach to a 4 megabit array,
system addresses Ao to As would go directly to Ao
to As inputs of the EEPROMs. For an array of 16
E2 devices, requiring 4 address inputs to select
the 16 devices, system addresses A6 - As would
go to a 4 to 16 decoder network, providing the 16
chip selects required. System address Alo would
go to address A6, system address All to address
A7 , continuining thru system address AlB to
address Al4- The 10 msec write cycle would
continue independently in each device while the
system was continuing towrite logicallyconsecutive pages in the other devices. This makes the
page size 1024 bytes, thus the system should stop
writing and wait for the write cycle to complete
after 1024 sequential bytes had been written.
For a 4 megabit array (sixteen 256K EEPROMs),
this design approach would produce a data rate in
write mode of greater than 100,000 bytes per
second or 6% times the bubble's write data rate.

Technology,lncorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

8-85

Temperature sensitivity is often a major design
consideration. This is very true for military, industrial and space applications. These designs often
require operation or at least storage down to -55
degree C and as high as 125 degree C. Bubble
memories have problems at temperature extremes
and often specify their minimum temperature for
operation a few degrees above 0 C. This does not
comply with standard commercial grade temperature ranges and falls far short of either
military or industrial grade temperature ranges.
Similar problems exist at high temperature. We
commonly see maximum temperature for operation
between +30 degree C and +50 degree C. Even

the +50 degree C falls for short of the commercial
temperature specification of +70 degree C.
Needless to say both military and industrial temperature ranges are completely missed EEPROMs
operate over the entire commercia~ industrial
and military temperature ranges.
Clearly, EEPROMs share the intrinsic nonvolatility of bubble memories without the disadvantages in speed, power consumption and
temperature range. Figure 1 compares the important attributes of the two technologies. Complete
technical information is contained in Seeq's
28C256 datasheet

NORMAL CHIP SELECT DECODE

DATA

-- -- -

...
<
I

As-A14

~
DEVICE 1

D

:;)

~

ID

I

Ao-As

e
III

~

U)

OE

t;

-- CS

WE

I

t

DEVICE 16

D

---

U)

:&

D

DATA

...
<

tI
~
OE

CS

WE

0

:z:
READ
WRITE

CS1

a

10F
16
DECODE

D
D

D

CS16

Figure 2.

SOOQ T f d . n o l o g y , I n c o t p O n I I e d - - - - - - - - - - - - - - - - - - - - - - - '
8-86

DECODING METHOD TO ENHANCE
WRITE CYCLE DATA RATE

~>

\ ..
vi

DATA

C

I

~

\
vi

I

-•

DEVICE 1

Ao-As

..

--

C

A10-A18

DATA

•

I---

t

~
DEVICE 16

a

~

I

I

~

~
I---

OE

CS

WE

Oe

Cs

WE

j~

j

READ

WRITE
CS1

\
Ae-~

D

10F
16
DECODE

a
D
D

CS16

Figure 3.

seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

8-87

8-88

Memory Products
Application Note

USING HIGH SPEED
CMOS EEPROMS WITH
HIGH PERFORMANCE
MICROPROCESSORS.
October 1987

I
seeQ
Technology, Incorporated

8-89

Using High Speed CMOS EEPROMs with
High Performance Microprocessors.

Satisfying ever increasing demands on microprocessor throughout can be achieved in several
ways, the simplest of which is to increase system
clock frequency. However, this technique yields
higher performance only if the remainder of the
system is capable of operating at the higher rate.
Memory devices on the system must be able to
respond to the accelerated transfer rate to avoid
insertion of wait states. Speeding up clock rates
without decreasing access times will generally
cause the microprocessor to wait faster. The
38C16 and 38C32 high speed CMOS EEPROMs
from SEEQ technology are designed to satisfy
the performance requirements of high performance microprocessors.
The 38C16 and 38C32 are 2K x 8 and 4K x 8 bit
CMOS EEPROMs manufactured using SEEQ's
advanced 1.25 micron CMOS process. Seeq's

proprietary oxynitride process and patented differential QceWMdesign give the parts fast access
times and high endurance. The 38C16/32 are
ideal for high speed applications requiring nonvolatility and in-system reprogrammability. Both
commercial and military temperature range products are available.

Device Features:
Read Operation:
38C16 and 38C32 are available in access times
ranging from 35 ns to 70 ns. The operational
mode table is shown in Table 1. Read operation
for the devices is similar to any standard memory
device. Chip enable access times are faster than
address access times(see data sheet) which can
be a significant advantage in high speed microprocessor designs.

38C16/32 OPERATIONAL MODES
CE

OE

WE

I/O

Read

MODE PIN

VIL

VIL

VIH

DouT

Standby

VIH

X

X

HIZ

Write

VIL

VIH

VIL

DIN

Write
Inhibit

X
VIH
X
VIL

X
X
VIL
VIL

VIH
X
VIH
VIL

HI Z/DOUT
HIZ
HI Z/DouT
No Operation
(HI Z)

X: Any TIL level
Table 1.
Q Cell is

a trademark of SEEQ

Technology, Inc.

8-90

Write Operation:
The write operation is similar to static RAM.
Because of t he fast address a nd data latches, the
write data latch cycle is as fast as a read cycle. The
address is latched on the falling edge of CE orWE
whichever occurs last and data is latched on the
rising edge of CE or WE whichever occurs first.
Afterthe data is latched the built-in timercompletes
the non-volatile write cycle within a maximum
time of 5 ms. A typical device has a write cycle time
faster than the maximum specified 5 ms. The
38C16/32 feature DATA polling to enable the
user to optimize write time. During the internal
write cycle, the complement of bit 7 of the data
byte written is presented at the output 1/07 when
a read is performed. Once the write cycle is completed, true data is presented at the outputs. A
software 'polling' routine (see fig. 1) can be used
to determine write cycle completion. The data bit
7 polling cycle specifications are the same as a
read operation. During data polling, the
addresses are a don't care.

WRITE DATA
TO EEPROM
STORE ADDRESS.
DATA

t

Write data protection:

DATA POLLING LOOP
OPTION: CAN PERFORM OTHER
TASKS IN LOOP

38C16 and 38C32 provide protection against
false write during powerup/down using on chip
circuitry. Writing is prevented under anyone of
the following conditions:

NOT EQUAL

1. When Vcc is below write inhibit voltage VWI.
2. A high to low write enable transition has not
occured when Vcc is between VWI and Vcc min.
3. WE, CE or OE are in TTL logical states other
than those specified for byte write in the mode
table (Table 1).
38C16 and 38C32 feature an on-board bandgap
voltage level detector. The detector disables the
EEPROM write circuitrywheneverVcc falls below
write inhibit voltage VWI. The internal charge
pump (voltage multiplier) is disabled, preventing
the high voltages which are necessaryforthe programming cycle from being generated. It is
impossible for data corruption to occur when the
charge pump is disabled. Seeq's EEPROMs are
guaranteed to be write disabled when Vcc falls
below write inhibit voltage VWI. VWI is between 3.8
to 4.25 V over the military temperature range.

8-91

EEPROM AVAILABLE
FOR ACCESS

Figure 1. BYTE WRITE WITH DATA POLLING.

I

Since present day systems employ a mixmatch of
both TIL and CMOS components, it is recommended that external hardware write protection circuitry be used in addition to the on-board
protection circuitry just described. This is needed
to eliminates false writes when Vcc is between 3.8
to 4.5 V (see Application Note 11). Absolute protection from false writes can be thus achieved
while having the added benefit of being totally
transparent to the system software.

System Interface examples:
MIL-STO-17 50A is the U.S. Air Force's instruction
set for 16-bit microprocessors embedded in
avionic weapon systems. This standard is also
used by the Navy, Army and NATO. Typical 1 750A
applications
involve
real-time
avionic
applications in systems incorporated into aircraft,
missiles and even ships or ground vehicles. The
standard specifies the microprocessor architecture and instruction set Also defined are two
memory addreSSing modes, a standard mode of

38C32

---------"''''-1
LATCH
MDC281

ADDRESS
Al1-~

DATA 1 - 0
ADDRESS A•• - ~

OE

ADoo

WE

AD..

CE
NOTE: ADDRESS A,o FOR 38C16

XCEIVER
DATA 0 •• - Do

38C32
DO

~

_ _ _-+-....
ADDRESS
Al1-~

BUFFER

CONTROLS

wiD

R/W

Figure 2. MDC281 INTERFACE TO 38C16/32

8-92

Ao

64K-word direct addressing and an optional
expansion mode of 1-Mword direct addressing.
The latter mode is segmented into 256 blocks of
4K-words each. The 38C16 and 38C32 offer an
excellent fit for 1750A processors and give system designers/programmers a wider array of
choices to come up with the next generation of
flexible and more powerful adaptive systems.
MDC281 MIL-STD-1750A CPU Module:
The McDonnell Douglas MDC281 is a certified
MIL-STD-1750A(Notice 1) 16-bitCPU consisting
of three custom CMOS/SOS LSI chips
MDC17501 (Execution unit), MDC 17502 (Control unit) and MDC 17503 (Interrupt unit) mounted on and interconnected within a ceramic
substrate. The MDC281 CPU is designed for
military avionics applications like sensor data
processing, operation and control of weapons
systems. The CPU is particularly suitable for
embedded applications requiring less than 64Kwords of memory.
38C16/32 Interface:
A typical MDC281 interface to 38C16/32
memory is shown in fig 2. 38C16-70 or38C32-70
with a maximum addressaccesstimeof70 nscan
be used without wait states in the memory subsystem for a 20 MHZ MDC281. For a complete
description of pin assignments and signal
functions refer to the MDC281 data sheet. Each
machine cycle consists of a minimum of 5 OSC
periods. The synchronization clock(SYNC) output
high to low transition signals the start of a new
machine cycle and is used as the timing reference.
SYNC low indicates that address is on the AD bus.
The AD bus is a bidirectional multiplexed Address
and Data bus (ADoo - AD1s), This bus is shared
between the external system and the internal
module resources and hence to avoid bus contention, the AD bus must be isolated from the
external system using a bidirectional transceiver.
Data Direction signal DD is used for transceiver

direction control. DD low indicates read transfer,
while high indicates a write transfer. High to Low
transition of the address strobe AS is used to
latch Address into a transparent latch during AD
bus de-multiplexing.
All transfers between the module and the
memory are referenced to the AS and DS bus control signals and are characterized by IN/OP low
and M/iO, CD high. Control Direction signal CD is
used to control direction of the control signal
transceiver. This signal goes high to indicate that
the module is driving the AS, OS, M/iO, RD/WR
and IN/OP signals.
Read Operation:
Read transfers begin with address being placed
on the AD bus immediately following SYNC high
to low transition. This address is assured to be
valid for the cycle by latching it in a transparent
latch on the high to low transition of AS. The DD
signal is high during this portion of the transfer.
RD/W indicates direction of transfer. During read
(fig. 3) the AD bus drivers are placed in a high
impedance state at the low to high transition of
SYNC to give the memory access to the bus. Next
DS signal goes low and is used by the memory
system to generate output enable (OE). DD also
goes low shortly after DS goes low and this signal
reverses the direction of the AD bus transceivers.
The memory then pulls RDY low to conclude the
transfer. Read data from the 38C16/32 is latched
into the module on the SYNC high to low transition.
Write Operation:
Write is indicated by RD/W going low (fig. 4). The
address is replaced by data when SYNC transitions from low to high. Next, the DS signal goes
low and is used by the memory system to generate
WE. Data isvalid atthe lowto high transition of DS
and is latched into the 38C16/32. DD stays high
for the duration of a write transfer. The memory
system pulls RDY low to conclude the transfer.

8-93

I

OSC

SYNC

~~--------------~I

\---

\-------------------

AS

____I
1

_ _ _ _..J

AD
BUS

. - <__

M/iO

=.7

RD/W

OJ

---J)>-----...«

A_D_DR_E_SS_ _

~

DATA IN

'r-

I

Figure 3. MDC281 READ CYCLE

seeQ

Technology,lncorporated - - - - - - - - - - - - - - - - - - - - -

8-94

OSC

SYNC

AS

OS

"---

~_ _ _ _ _ _ _ _ _ _ _ _ _/

--~---_/

~---------------------

\... . ._______r-

____7

____7
~~S

>cBK___

~_ _ _A_O_OR_E_S_S_ _ _

>C

O_A_TA_O_U_T_....

M/iO

RO/W

"

I

Figure 4. MDC281 WRITE CYCLE

seeQ T e c h n o ' o g y , ' n c o r p o r a t e d ' - - - - - - - - - - - - - - - - - - - - - 8-95

I

Fairchild 9450:
Fairchild 9450 issinglechipsolution implementing
the complete MIL-STD 1750A instruction set
architecture (lSA) and its floating point standard.
It allows addressing of up to 2 M words of memory
and with the addition of the F9451 Memory
management unit (MMU), up to 16M words of
memory.
38C16/32 Interface:
A typical minimal configuration 38C16/32
memory subsystem interface is shown in fig. 5.
The 20 MHz F9450 provides for a 90 ns memory

access time without wait states. Hence, 38C16-70
or38C32-70 with a maximum address access time
of 70 ns can be used in the memory subsystem.
Bus cycles are a minimum of 4 or 5 states long.
Memory and I/O cycles are identical and the
status of the M/IO line distinguishes the two
cycles. State So is used for bus acquisition. This
state is followed by Sl state. After the start of Sl
state, the CpU outputs the address after a delay.
At the end of Sl, RDYA input is sampled. If RDYA is
low the CPU stays in Sl, extending the address
phase of the bus cycle. Otherwise, it proceeds to
states S2 followed by S3.

F9450
LATCH

38C32

,L=ll_____--=:AD::.::D::..:R::ES=S~------------..._"\'
IBo

is,.

/

/A"""-------v"'--~

,..-----vV

(.......
"

1------- '\

, - - -

r--

r-

LE

I------I/v/

----

1 "~JJ
1_ ' \

r-v'
r-

DATA OUT

[

LE

'--""----o.-_~
"""----.,..---,....,..-V
v/

6E

"""---_ _""----o_ _ _
~

LL----,-.......,rTII/

r~Ur::::oJ
~
~
LATCH
I l~
~

1-+_ _t----1r--

~-JU-.'-1-..,/
j+E

A"

D, - Do

-WE
NOTE:

0

__

r-~')~~-------t--------;;;:RE;;;A:;;:-D-"t;:t;t

F-

~

D/T

~-

-

Al1 -

DATA

~- (JE

M/iO

'----t--"'""1 LE

ADDRESS

....---1~-..,CE

cs

DECODER

R/Vii

$~'

_- - - ,

V

STRBD

OE
WE

,..-_

DATA IN

t-

DATA
D, - Do

IT
,----

LATCH
~

STRBA

Al1 -A"

"

I

r-

ADDRESS

ADDRESS

A,o-A"
FOR 38C16

DATA

Figure 5. F9450 MEMORY INTERFACE

seeQ

Technology. Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - -

8-96

82

81

SO

53

53

80

81

CLOCK

Wio R/W
olT

ROYO

\

/

ROYA

7

\

1

I

/\

STRBA

IBo - IB15
READ
STRBO

\

»ID»
I

V-OORES8

»») (

READ DATA

)

'WRITE

7

<=

I

\
Figure 6. F9450 READ CYCLE

so

81

S2

I

53

80

S4

CLOCK

R/iii
olT

M/iO

STRBA

ROYA

ROYO

-----------------~

______________1

\~

,-------________________________

------------------------~I

----------------1
IBo-IB15

,-------

\--~I

----------~(AOORESS»>X

WRITE DATA

\_--

>Ei~-

Figure 7. F9450 WRITE CYCLE

,seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - -

8-97

Read Operation:

DSP Applications:

STRBA signal is pulled low in state S2 (fig. 6). The
high to low transition of this signal is used to latch
the memory address. The CPU the pulls STRBD
output low and prepares to receive read data from
38C16/32 by turning the address/data bus
around. STRBD is used to enable data from the
memory.
Write Operation:
During write cycles the CPU starts driving the bus
with the write data immediately after the address
(fig. 7). STRBD signal is activated during S3, a"owing enough write data setup time to STRBD falling
edge and hold time for the rising edge of §ffi85
to write data. At the end of S3 RDYD is sampled,
and if low, state S3 is continued extending the
data phase. If the signal is sampled high the write
cycle is terminated.

Present day DSP processors are finding a wide
range of applications like Encryption/Decryption,
voice-band, precision servo control, pattern
recognition, adaptive control and intelligentfiltering. Most of today's applications use ROM or
EPROM based memories to store algorithms and
as a result use is restricted to applications that
utilize fixed algorithms and co-efficients. Adaptive algorithms must use RAM, thus forcing the
processor to repeat its adaption sequence each
time power is turned on. Seeq's high speed
CMOS EEPROMs 38C16 and 38C32 present an
excellent fit for many of today's DSP processors
and open the door for system designers and
programmers.

WRITE DATA
TO EEPROM
STORE ADDRESS,
DATA

Software Considerations:
Examples of hardware interface of MIL-STD1750A microprocessors to 38C16/32 have been
shown. 38C16/32 have a built-in timer to control
the internal non-volatile write cycle. The parts feature an automatic erase before write. The write
cycle takes a maximum of 5ms/byte. System
software has to take into account this byte write
time of the EEPROM. The system writes to the
EEPROM and then follows the write with a polling
routine as shown in fig. 1 to determine the end of
the EEPROM internal write cycle. If the system
application demands that the 5ms write time be
utilized usefully, the technique shown in fig. 8 can
be used. The on-board timers A or B can be used.
These timers can be used to timeout the 5ms
write time of the EEPROM and programmed to
interrupt the CPU. The CPU can thus carry out
other tasks while the internal write cycle of the
EEPROM is in progress.

TIMER:
5 MS BYTE WRITE
TIME TIMEDOUTGENERATE INTERRUPT

WRITE

Figure 8. EEPROM BYTE WRITE SEQUENCE
USING SOFTWARE CONTROLLED TIMER

seeQ

Technology,lncorporated - - - - - - - - - - - - - - - - - - - - - - - - - -

8-98

TMS320C25:
The TMS320C25 is a high performance digital
signal processor featuring a single accumulator
and a Harvard type architecture in which program
and data are implemented in separate address
spaces. The processor features on-chip data
RAM of 544 words, on-chip program ROM of 4K
words and supports direct addressing of up to
64K words of external program memory and 64K
words of external data memory. An on-chip serial
port provides direct communication capabilities
with serial devices.
For protyping, system expansion, external
memories maybe required. The38C16/32 can be
used as program memory and offer the ability to
implement adaptive algorithms because of
their reprogrammability.

the address bus and one of the memory space
select signals PS or OS. R/W isdriven high to indicate a read cycle. At the beginning of quarter
phase2, STRB goes low to indicate valid address.
STRB is used with R/W to state memory read
enable Signal. After decoding the address, the
memory system must set up READY during
quarter-phase2. READY is sampled by the
320C25 at the beginning of quarter-phase3. If
READY is sampled high, read data from the
memory is clocked in at the end of quarter-phase3.
Ready can be pulled high permanently, if the system components used do not require wait states.
At the beginning of quarter-phase4 STRB is
deasserted. The read cycle is terminated with the
de-activation of the address bus and PS, OS. Care
must be taken to avoid bus conflicts when a read
cycle isfollowed byawritecycle. The38C32 hasa
15ns max disable time and hence will not cause
bus conflict.

38C16/32 Memory Interface:
The TMS320C25 distinguishes between program memory and data memory spaces using PS
and OS signals. For a detailed description of pin
assignments and their functions refer to the
320C25 data sheet. The crystal or external clock
source is divided internally by the 320C25 to produce a four phase clock. All bus activity is referenced to the four-phase clock. The interface
discussed here is for a TMS320C25 running at 40
MHz. Fig. 9 shows 38C32-35 used as program
memory. The 35ns maximum address time of the
38C32 satisfies the memory performance
requirements of the 320C25.

External Read Cycle:
During the beginning of machine cycle (fig. 10)
clockquarter-phase1, the320C25 begins driving

External Write Cycle:
The external write cycle is similar to the read
cycle described above, with the following differences: R/W is driven low indicate an external
memory write. STRB is used with R/W to gate
write enable signal. Write data is placed on the
bus at the start of quarter-phase2. STRB is deasserted at the beginning of quarter-phase4 and
the write cycle ends with the de-activation of
address bus and PS, OS. As before, care must be
taken to avoid bus conflict when a write cycle is
followed by a read cycle. Since STRB is used to
enable the 38C32, potential bus conflict is
avoided.

8-99

I

TMS320C25
ADDRESS

A15

)

A;;

J

r--

iSS

~

--..

38C32
ADDRESS
A11-~

DATA
D7 - Do
CE

DE

r---+- WE

--(>0

R/iii

READ

WRITE
STRB

--Er)-~O-4

I--

t----4

I--

I-- 1----1

~

-V
+5V

-1\

READY

D15

Do

~

DATA

38C32
ADDRESS
A11-~

DATA
D7 - Do

vi,..
..

CE

~

WE

OE

~

Figure 9. TMS320C25 MINIMAL EXTERNAL MEMORY INTERFACE

-seeQ

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - -

8-100

3

2

"\

CLKOUT 1

I

>e<

A,s - Ao
PS,DS

4

'--I

\

STRB

>M

VALID

C

I

R/W

EXTERNAL
READ

7 \

READY

<

o,s- Do

DATA IN

)

I

~

R/W

EXTERNAL
WRITE

7 \

READY

e<

015 - Do

DATA OUT

>e-

Figure 10. TMS320C25 READ AND WRITE CYCLES

Software Considerations:
When 38C16 or 38C32 are used as program
memory, the system can take advantage of the
easy reprogrammability of these devices. Code or
Program coefficients can be easily altered to
implement adaptive systems. The38C16/32 byte
write time of 5ms max should be accommodated
by the system software (fig. 11). The on-chip timer
can be utilized to timeout the byte write time. A
timer interrupt is generated every time the timer
decrements to zero. The period register (PRO)

can be used if necessary, so that interrupts can be
programmed to occur at regular intervals.
Using the 38C16/32, remote down-load capabilities can be provided to the system using the onchip serial port. Object code can be downloaded
into RAM at high speed and then written into the
EEPROMs from the RAM. Typical DSP algorithm
implementations need up t04K words of program
space. Using the 38C16 or 38C32 only two packages are required thus minimizing package count

8·101

I

WRITE TO EEPROM:
MOVE FROM RAM
TO
PROGRAM SPACE

STORE
. ADDRESS
DATA

__ -

TIMER:
5 MS BYTE WRITE
TIME TIMEDOUTGENERATE INTERRUPT

-

-

START TIMER
TO COUNT
BYTE WRITE
TIME

DO
OTHER TASKS
UNTIL INTERRUPT
OPTION: 'IDLE' UNTIL
INTERRUPT

VERIFY
PASS

EEPROM
READY
FOR NEXT
ACCESS

Figure 11 . TMS320C25 WRITE SEQUENCE FOR 38C16/32 EEPROM WRITE.

8-102

Communications Products
Application Brief

EEPLD's
INTERFACE IBM PC BUS
WITH THE

EDLC®8003

August 1988

I
8-103

seeQ
Technology, Incorporated

Ethernet/Cheapernet Controller Design

Al

PC/AT personal computers can be networked

.....

Control/Status

.....

together via 10 Megabit per second
EthernetiCheapernet IEEE 802.3 CSMAlCD protocol
using the SEEQ 8003 Ethernet Datalink Controller
(EDLC® ) and the SEEQ 8020 Manchester Code
Converter (MCCTM). As the PC Bus data rate is
typically one byte per microsecond and interrupt
latency may be hundreds of microseconds, a FIFO
buffer memory is required to capture Ethernet data
frames which can come at any time. In this
application brief, the FIFO buffer consists of an
economical industry standard 8K byte static RAM
together with SEEQ EEPLD20RA 1OZ electrically
erasable programmable array logic devices. The
EEPLD devices provide handshakel arbitration
control logic between the FIFO, EDLC and PC Bus.
Additionally, the EEPLD devices provide the memory
address decode logic from the PC Bus. A system
block diagram for the Ethernet Controller is shown in
Figure 1.

.....

P
C

EEPAL
Control
Logic

......

/
A

T

......

....

t

B

FIFO
RAM
8Kx8

U
S

...
~

EDLC
B003

.....

....
~

A~

......

., r

Data

~

MCC
8020

~

l

,

AUI

FIFO RAM Buffer
The FIFO RAM buffer is divided into four 2K byte
sections as shown in Figure 2. Incoming Ethernet
data frames range from 60 to 1514 bytes which are
loaded into the RAM at locations 0, 2048, 4096, and
then back around to O. The PC must unload these
frames before the fourth frame overwrites the first
frame. More frames could, of course, be buffered by
increasing the RAM size to, say, 32K bytes. The PC
is aware of the location of the frames by keeping
count of the EDLC Receive End of Frame interrupts
or by closely watching the status of incoming frames
in the EDLC Receive Status Register.

Figure 1. Ethernet Controller System

8Kx8RAM
addrOOOO
Rx FIFO 0
addr2047
addr2048
Rx FIFO 1

Rx Counter
The FIFO RAM address is supplied by the RX
Counter (EEPLD) during
EDLC receive data
transfers. This counter is reset to 0 on PC 10 Write
Command "ResetRxCounter'. It is incremented on
EDLC RxRD unless RxTxEOF in which case it is
advanced to the next 2K boundary (0 if address
greater than 4K) .
Tx Counter
The FIFO RAM address is supplied by the Tx
Counter (EEPLD) during EDLC transmit data
transfers. This counter is loaded by the PC with

addr4095
addr4096
Rx FIFO 2
addr6143
addr6144
Tx FIFO
addr 8191

Figure 2. FIFO RAM Partitioning

EDLG is a registered trademark of SEEQ Technology, Inc.
MGG is

a trademark of SEEQ

Technology, Inc.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - 8-104

address 8191 minus the frame byte count. It is
incremented on EDLC TxWR. On arriving at the
terminal count, 8191, an RxTxEOF signal is supplied
to the EDLC, signaling the end of the frame.
The Tx Counter is used by the PC to read out
Receive frames. Simultaneously, the Rx counter may
be receiving a new frame while the current frame is
being transferred to the PC. Care must be taken in
the software design to assure that a transmit frame is
completed before using the Tx counter for an Rx
read out. The Tx Counter is incremented
automatically when the PC lOR read signal executes
a read byte.

Designing with SEEQ EEPLD's
The EEPAL20RA10Z devices provide the glue to
hook the EDLC, MCC, and FIFO RAM to the PC bus.
The design methodology utilizes PC based
assemblers such as PALASM~ ABELIM CUPL'!"M or
MINCTM to transform equations and simulations into
JEDEC link maps and test vectors. In this application
brief, PALASM2 is chosen. The design specifications
are shown in Figure 5.

Testing the Design
Four software programs demonstrate the operation
of the Ethernet Controller design. The source
language chosen is Turbo PASCAL 4.0 ™ (Borland
International). PC bus operations are implemented
using the PORT instructions:

PC Bus Decode
EEPLD devices decode the PC Bus Address, 10
Read, and 10 Write signals to provide PC access to
the EDLC 8003, FIFO RAM, Rx Counter, Tx Counter,
and miscellaneous controls such as reset, TxMode
and LoopBack.
Bus Transceivers
Data bytes are transferred to and from the PC, FI FO
RAM, and EDLC 8003 on the Data 00 .. 07 bus via
Transceiver 74LS245 and are controlled by EEPLD
signals DIR1 and G1. Control/Status bytes are
transferred to and from the PC and EDLC 8003 on
the CMMD 00 .. 07 bus via Transceiver 74LS245 and
are controlled by EEPLD signals DIR2 and G2.

Attachment Unit Interface, AUI
The Ethernet Controller Design provides a physical
data link between the PC and the AUI interface. The
six AUI signals Rx +, Rx-, COLL +, COLL-, Tx +, and
Tx- will drive up to 50 meters twisted pair
transmission line to another Controller as
demonstrated by this application brief or to a Media
Attachment Unit (MAU) for communication over
single wire coax Standard Ethernet cable. The
addition of a transceiver chip and electrical isolation
makes possible support of Cheapernet.

PC 10 Write:
Read:

Port[Address]: = Data;PC 10
Data: = Port[Address];

The software programs are illustrated in Figure 11.
RAM Test
The
basic PC operations of memory address
decode, load/increment Tx Counter, Read and Write
RAM are exercised by this test. The 8192 RAM
locations are loaded with numbers 0 thru 4095 in
pairs of bytes, then read back for comparison check.
LoopBack Test
The EDLC 8003 is tested by transmitting a frame to
itself in Loop8ack Mode. The frame received is
compared with the frame that was transmitted.
Continuous Transmit/Receive Test
Using two Ethernet Controllers in two PC's, random
frames are continuously transmitted from one
controller to the other and echoed back, while error
status is checked and errors are counted.
Hello Hello PC to PC Terminal Emulation
Two PCs are configured as terminals as shown in
Figure 3., allowing simultaneous frames to be
passed back and forth at each operators discretion.

PC Implementation on Half Card
The Ethernet Controller has been implemented on an
IBM PC expansion board using less area than that
required for a half card. The schematic diagram for
the design is shown in Figure 9.

AUI

Oiiiiillllllllllllil

El •

·

Oiiiiilllllllllllill

Figure3. PC to PC Terminal Emulation

8-105

S

Command Register EEPAL U8
7

6

5

432

1

Build Your Own
Ethernet/Cheapernet Controller

0

Reset EDLC

Using the SEEQ EDLC, MCC, and EEPLDs, you can
build your own Ethernet/Cheapernet Controller.
Contact you local SEEQ representative for a
PC/XT/AT floppy disk containing the EEPLD Design
Specifications and the EDLC Demonstration
software as described below:

EDLC.EXE
EDLC.PAS
EEPALU3.PDS
EEPALU3.JED
EEPALU4.PDS
EEPALU4.JED
EEPALU6.PDS
EEPALU6.JED
EEPALU7.PDS
EEPALU7.JED
EEPALU8.PDS
EEPALU8.JED
EEPALU9.PDS
EEPALU9.JED
EEPALU10.PDS
EEPAL103.JED
MAKE. BAT

Reset Rx
Add Counter

Loopback
8020
TxMODE

Figure 4. Command Register Bit Map

Address Map

Hex
Add
AO .. A9

Write
(lOW)

Read
(lOR)

300

Station Add 0

301

Station Add 1

302

Station Add 2

303

Station Add 3

304

Station Add 4

305

Station Add 5

306

Rx Status RxCommand

307

Tx Status TxCommand

EDLC 8003

308

Command Reg EEPAL U3 U4

309

LDTxAO .. A7

30A

LD TxA8.. A12 EEPAL U9 U10

308
30C

EEPAL U9

Unused
RAM Read RAM Write

RAM 8kX8

Figure 5. Address Map

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - 8-106

Figure 6. Ethernet/CheaperNet Controller Block Diagram

A9

lOR
lOW
AEN
07 RESET

~

.~.....

AO

,..

DO

~,....

...

Transceiver

...
LS245 U2
AO ....- - -......

CMMO
00 .. 07
CS

Address
Decoder

...
lOW
IIOR I
f---t

...._ _ _...... TXROy

EEPAL U3,8

CMMO

Hand-shake
TXWR
State Machine RXRO~
EEPAL U4

00-02

Command

RXRO

RESET EOLC
TxRet

Register

RESET RX
EEPAL U8

LPBAC

INC

,r

I--

...

EOLC
8003

, Ir

TX Counter

...

EEPALU9,10
RAM
8KX8

1

AO
A12

U11

RxOC

U12

RX Counter
EEPAL U6,7
MCC
8020

...

Tranceiver
LS245 U1

. ------------..------.
~, Ir

~~

PC
DO _ 07 ' Ir

AUI
, Ir Cable

Ethernet
IEE802.3
Compatible
XCVR

....

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - 8-107

Figure 7. RxRDY/RxRD Handshake Waveforms and Truth Table.

RxRDY

I

W
~~

I f~

~

I

,

~

~I

~~
~~
2

3

4

~

~

~I
5

6

7

8

9

10

11

1.RxRDY INACTIVE NO RECEIVED DATA EXISTS IN THE EDLC CHIP. RxRD, RxWE, RxCS AND
RxWRARE IN AN INACTIVE STATE.
2.THE PLD20RA10Z SAMPLES AN ACTIVE HIGH RXRDY,AT LEAST ONE RECEIVED DATA BYTE
EXISTS IN THE EDLC FIFO BUFFER. RxRD GOES ACTIVE LOW.
3.THE STATE MACHINE OUTPUTS RxWE, RxCS AND RxWR GO LOW. RxCS AND RxWR
CONTROL THE RAM INPUTS TO ENABLE AN ACTIVE WRITE CYCLE.
4.RxCS AND RxWR GO INACTIVE TO END THE RAM WRITE CYCLE.
5.RxRD AND RxWE GO INACTIVE HIGH TO COMPLETE THE HANDSHAKE CYCLE.
6.RxRDY STAYS INACTIVE LOW. ALL OUTPUTS RxRD, RxWE, RxCS AND RxWR HOLD IN AN
INACTIVE STATE.
7 -11.1F RxRDY GOES HIGH THEN THE STATE MACHINE WILL REPEAT THE HANDSHAKE
CYCLES WRITING TO THE RAM UNTIL RxRDY GOES INACTIVE AGAIN.

TRUTH TABLE:
RXRDY RxRD RxWE RxCS

L

H

H

H

;IDLE STATE NO HANDSHAKE ACTIVITY.

H

L

H

H

;RxRD ACKNOWLEDGES ACTIVE RXRDY.

X

L

L

L

;RxWE GOES LOW WITH RxCS.

X

L

L

L

;RxCS GOES INACTIVE AFTER WRITE.

L

H

H

H

;ONE HANDSHAKE CYCLE IS COMPLETE.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - 8-108

Figure 8. Design of the RxRDY/RxRD Handshake Logic:

EQUATIONS:

RxRD :

= RxRD * RxWE * RxCS * RxRDY

;HOLDS RxRD HIGH WHEN RxRDY
IS INACTIVE.

+ RxRD *

RxWE * RxCS

;TOGGLES RxRD INACTIVE AFTER
ACTIVE CYCLE.

+ RxRD *

RxWE * RxCS

;HOLDS RxRD HIGH WHEN THE PC IS
ACCESSING MEMORY.

RxWE : = RxWE*RxRD*RxCS

;TOGGLES RxWE INACTIVE AFTER
ACTIVE CYCLE.
;HOLD RxWE INACTIVE WHILE NO

RxCS :

= RxCS*RxWE*RxRD

;TOGGLES AFTER STATE 21N THE
WAVEFORM DIAGRAM. PROGRAMMABLE
POLARITY IS USED ON THIS OUTPUT.

+

G2*DIR2

RxWR := RxRD*RxWE*RxRD

GOES LOW FOR PC READ CYCLES.

;RxWR GOES LOW AFTER STATE 2 IN
WAVEFORM DIAGRAM. PROGRAMMABLE
POLARITY USED ON THIS OUTPUT.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - 8-109

Figure 9(a). Schematic Diagram, PC Bus and Address Decode
/lOW
/lOR
AO
Al

A2

+5V

/t\NI

!lOR
AO

B,3

;

Al

A4

A5
AS
A7

AS

PC

AS

XT

AT

AEN

BUS

DO
01
D2

7= /lOR

LDl

'8
&.;;.

AO
Al

A4

J'QA5

EEPLO

r.=I:

-~

~

GND

";

[§:

lOO

20RA1~
DlR2
U3

/G2

Address
DlRl
Oecocle1
/Gl

&.;;.

A25'-

NC
/CMMD

toE

GND

~

+5V
/cSRAM

~

§

LDl

~
21'

LDO

5
~

ICS8003
DIR2

191
..;;J
18"1
..;;J
i7'
.;.;.,I

IG2
DIRl
/Gl

16".
..;;J
~GND

m

~
A7

D3

=;=
~

D5

F=
A4

De

~

esc

I--

~
Al0
~

+5V

~

GND

921

IPL
AEN

~~j
~
SEL

A7

~
~

A9

6

DO

==

-

~

-

I--

7"

01

8

D2

==
;::
9

~
SYSCLK
F=
A1 f-----

IAQ7

1

~

TXRET

7A8

.....---

7f I - -

IOROY

"""-

:;=

RESET

RESET

"""-

GND

..-+5V

-

ICMMD

141
.;.;.J

=;= -

D4

07

ICSRAM

L.:..

=#{

A11

!IC1N

~
'7A3

~
~

vee

IPL

r7=A2

:;,

=
~

~

7
7

~

:;
A2 :;
:;
A3

7

-

IORDY

f----INT
f-----

GND

~
~

~
.....

EEPLO

ILPBK

/EDLCRST

~

TXRET

~

ILPBK

~
~

/EDLCRST

20RA10Z

~

RSTRX

U8

~

TXMODE

Address
~
/WE 17
Oecocle2
;::

/RXWR

D3

RSTRX

TXMODE

19

78

/WE

/RXWR 16
~

RESET
/CMMD
GND

/CSRAM

r;sr---.
~

/lOW 14
toE

~

i-

GND

+5V

CMMO 00 .. 07 ..

~

..

Bl
GND
~

PC 00 .. 07 ..

...

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-110

Figure 9(b). Schematic Diagram, Tranceiver and RAM
RAM AO .. A12
!WE
1

NC

RAM
8Kx8
U11

!eEl
1CE1

AO

07
D6

01

D5

D2

D4

GNO

D3

!G1

OATA 00 .. 07

DlR1

PC 00.. 07

CMMO 00 .. 07

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-111

Figure 9(c). Schematic Diagram, Tx and Rx Address Counters

~

TxCounter

Rx Counter

QO•• Q12

QO•• Q12

RAM AO .. A12
/RXRO

vee ~

r, /PI..
-I~
- /lNCTX
GNO r-;- NO
.....
+5\1

tI.N_CTX
_ _..._ _ _

...- - - 1 7 DO

~

"'---115

01

"'---1 8

~
~8

D2

"'---17

D3
D4

~

DI5

~

...- - . . .
..._ _...

CIOTX

=
=
=

"""ft

-

00.. 06 Q8TX ~

8

GNO

elYl :;:;: I - -

GNO

:;7
~

GNO

GND

GND

GND

~
~

~

~
a....
~
a....

vee ~

/PI..
RSTRXDC

QORX

~t---..
RXTXEOF
Q1RX
=
f,t---.. r+--~--f'4" IRXRO
Q2RX
EEPLD
I;::
EEPLD
Q3TX 20
GNO 15 NO
Q3RX
20RA10Z
~
U6
elYO 19
GNO 8 NO
CWYO
U9 Q4TX 18
~
Rx Q4RX
GNO 7 NC
Tx ~ ::::17
~
00 .. 07

....--I...- -...
lDO
~

I~

+5'1

Q1TX
Q2TX

...- -...~ os
GNO

+5\1

;t---..
___

NO

~

GNO

13
-

~
~

~
~
~
~

+5'1

'23t---..
=

~t---..
f,t---..
2Ot---..

=
=
=
19

18 t - - -..

::::

/RXWR

Q5RX 1 7 t - - -..

NC

Q8RX

NO

Q7RX :;:;:

NO

CWYl

~

GNO

~t---..

.1..-...- -....

:;71-~
13
-

GND
/RXWR
RxTxEOF

TXMOOE

+5'1

IT

....+--fl---f~
GNO

IT

i7

TXMODE

NO

RxTxEOF

...- t - -...

07

...-t--"'15

DO

~

.::;
D2

...- t - -...

ra

D3

...- t - -... 9

D4

~

_~
--f~

•LD_l_-++-...._ _

GNO

~
£§:

+5V

~

+5V

U10

rt

IRXRO

Q10RX 2 1 ' t - - -..

NC

Ql1RX

Et---...-t!-+H.....- ...tt RXTXEOF

Ql0TX
Q9TX

::

1a1
17'

----i

OSTX

07.. 012

elYl

==

Q7TX 18
elY2

-

~

LDO 7.; r - -

GNO

toE

-2!1

_

GNO

GNO

.:;;.;J

~t---..

/RXWR

8

/CS~

9

~R

~

Q12RX ·18 : t - - -..

S
CWY2 .!!J

UB.. Q12

RXDC
Q7RX
GNO

::::!

U7

7

~
~
.!!

:5t---..

cwy~ORA 10~3 191

=
=
To

L01

Q9RX

EEPLD

L,;..

GND [!:
---l8

:5
.!!.

~.;:J

+5V

OSRX 5 t - - -..

QllTX 20

01

vee ~

/PL
RSTRX

~

EEPLD

IT

r++-...~

Ql2TX 21'

20RA 1OZ

---+---4a.!.
__-+---41'7
~

vee ~

IPl
tlNCTX

.-

tlNCTX 1 6 t - - - - - . .
ICE1

~I--_....

RSTRXDC 7.;t----HI----II
toE

~

.!:t GNO

LDO
~R

IOSRAM

ICEl
RSTRX

CMMD

RXDC

~DO .. D7

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - 8-112

Figure 9(d). Schematic Diagram, EDLC and MCC
/lOW
/lOA
ICS8003
A2

.Al________________________________________________________~~ Al

vee

.AO________________________________________________________~~ AO

A2

__------is:;: :

/cs

TxEN

__---f~ TxD

TxAET

EDLC

+-----------------------------------------------__----~~ ~AET 8003
~6
------c..

.... DATA DO •• D7

vee

+5V -;- /Pl

_--1f-~=;

•/E_D_lC_A.....

---

~

~

rs

/Gl

/RXWR

RXTXEO

ICdSt5

~

---E AxTxD6

ICdStS

201
~
.!!J GND

----.J"13
~

ICdSt7

~

RXRDY

/AXCS

EEPJxREOFD
20RA10Z
U4

NC

SYSCLK

Hand
Shake

laY

TXRDY

lOX

TXMODE
~
-----I--Hf---1[! TXMODE

r-++---f~

ICdSt4

AxTxD5

~

·SY-SC--LK--I--+---~a.!. DIRl

-J'8

AxTxD4

~

IRXRD

+DI-Rl--+--+-----4;;:

[!::

ICdSt3

/RXWE

/RXWR

NC

IORDY

E

GND

@ GND

JOE

AxTxD7

......------1~ /TxC

~mJ18r-----1~---I--.----__1~
171
~
..:.:..J

--

~

/TXWR 16

RXTXEOF

GND

~

3--

.~
~

3---~ GND

GND

[§:

36~----------~

~
~

i33L-

/CdSt2

AxTxD3

/EDlCRST

...

~

AxTxD2

~

+5V

I

~t----=

/CdSto

~

TXClK

/Gl

twA

--; 9

24

+5V

~~

/AD ~I-----'"

AxTxDO U12 /CdSto

~~~. . . .~~~~~~~~~~~~~~~~~~~,.. .~ Ax~DO

40

~
~

CMMO 00 .. 07
...

S-..----.....

SS~

~

RxC ~

/TxWR

RxDC

TxRDY

INT

RxDC

St----It----------- 7
t25!t----It------------1N T

S-r-

AxTxEOF

COll

/RxRD

/RESET

RxRDY

CSN

VSS

RXD

~ .
~--

8----

~------------------------------~----_+--._~---------------------------..I

IORDY

E:
GND
/LPBK

~GND

MODEl

VCC

~

GND

Tx+

"3

/LPBK

r;sf~
17f~
/TxC
16
MCC

=
=
r=
4

Rx+

5

Ax-

Tx-

TxD

--

-S7.i1
i-

6

CSN

8020

TxEN

r.:=

COLL

U13

Xl

a.2.
18
~
L!..

e-

Axe

X2

AxD

COll+

GNDE VSS

COll-

...;..:.J

";'31

..;.:J

§---

0-

=pI'D~
T
20 MHz

GND
AUI

GND

Cable*

...

...
"Note resistor termination as shown in 8020 data sheet

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-113

I

Figure 10. EEPLD Design Specification
Address Decode 1
Logic Gates Example of selected Boolean
Equations;

TITLE
PATIERN
REVISION
AUTHOR
COMPANY
DATE

DECODE 1
U3
01
PEER RESEARCH.
PEER RESEARCH.
30TH APRIL 1988.

CHIP DECODE PAL20RA10
;PINS

1
/PL

2
/IOW

7
A3

A4

;PINS

13
fOE

14
/CMMD

;PINS

19
DIR2

20
21
/C88003 LDO

;PINS

8

5

3
/IOR

4
AO

Al

A2

S

9

AS

10
AS

11
SEL

12
GND

15
NC

16
/Gl

17
DIRl

18
/G2

22
LDl

23
24
/CSRAM VCC

Address decode PAL20RA10 U3 is designed generate
the enable inputs and direction control of
two 74LS245 bi-dlrectlonal buffer circuits.
Also, to create an I/O mapped control load input
to the transmit counters, i n addition to giving
select inputs to the RAM buffer and 8003 EDLC
device.
The enable signal G2 selcts a data path to and
from the 8003 EDLC device. Data read and write
is controlled by the DIR2 signal. The 8003
internal registers are selected in the I/O
mapping scheme address 0300 to 0307. The second
74LS245 is selected in the memory map 0308 to 030F
and enables a bi-directional path to the 8k
byte RAM buffer store and the RXTXDO-D7 I/O
path to and from the 8003 device.
EQUATIONS
G2

= SEL*/M*/A5*/A4*/A3*IOR

;ADDRESS
; SELECT
;300 TO
;306

= SEL*/M*/A5*/A4*/A3*IOR

;READ ONLY
;3OO-3OB
; (3OB UNSUED)
;ADDRESS
; SELECT
;3OCTO
;3OFDIR
; READ ONLY
; SELECT
;8003 300
;T0307
;RESET EDLC
;ADDRESS 308

+ SEL*/M*/A5*/A4*/A3*IOW
+ SEL*/M*/A5*/A4*A3*/A2*IOR
+ SEL*/M*/A5*/A4*A3*/A2*IOW

/DIR2

+ SEL*/M*/A5*/A4*A3*/A2*IOR

= SEL*/M*/A5*/A4*A3*A2*IOR

Gl

+ SEL*/M*/A5*/A4*A3*A2*IOW

/DIRl
CS8OO3

= SEL*/M*/A5*/A4*A3*A2*IOR
= SEL*/M*/A5*/A4*/A3*IOR

+ SEL*/M*/A5*/A4*/A3*IOW

=

CMMD

SEL*/M*/A5*/A4*A3*/A2*/A1
*/NJ*IOW

CSRAM

= SEL*/M*/A5*/A4*A3*A2*/A1

;RAM SELECT
;3OC
; ENABLES WRITE
;FROM PC

*/NJ*IOR
+ SEL*/M*/A5*/A4*A3*A2*/A1
*/NJ*IOW

seeQ

LDO

SEL */M*/A5*/A4*A3*/A2*/A1
*NJ*IOW

=

;LOAD DO-D6
;ADDRESS 309

LDl

SEL*/M*/A5*/A4*A3*/A2
*Al*/NJ*IOW

=

;LOAD 07, DO
;TOD4
;ADDRESS 30A

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - -

8-114

SIMULATION
TRACE_ON

IIOR/IOW
CS8003 LDO LD1
G1 DIR1 G2 DIR2
CMMD AO A1 A2 A3
A4AS A6 SEL
SETF
OE IPL IIOR IIOW
lAO IA1 IA2 IA3 IA4
IAS/A6 SEL
FOR L : = 0 TO 1 DO
BEGIN
IF L = 1 THEN
BEGIN SETF A3 IA2 IA1 lAO
END
FOR K : = 0 TO 1 DO
BEGIN
IFK = 1 THEN
BEGIN SETF A2/A1 lAO
END
FOR J : = 0 TO 3 DO
BEGIN
IFJ = o THEN
BEGIN SETF lAO IA1
END
IF J = 1 THEN
BEGIN SETF AD
END
IF J = 2 THEN
BEGIN SETF lAO A1
END
IFJ = 3 THEN
BEGIN SETF AO
END
FOR I : = 1 TO 2 DO
BEGIN
SETF
lOR IIOW
SETF
IIOR lOW
END
END
END
END
TRACE_OFF

;TRACE ALL
; SIGNALS

;ENABLE OUTPUT
; DISABLE PRE; LOAD. SET lOW
;IOR INACTIVE
;ADDRESS INPUT
;TOZERO SEL
;ACTIVE. ADDRESS
;AO-A3IS
; INCREMENTED
; FROM 0 TO F HEX
;IN LOOPS L,
;K, J. IN LOOP
;1 THE lOW AND
;IOR ARE TURNED
;ON AND OFF IN
;ANTIPHASE.

I
seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-115

Figure 10. EEPLD Design Specification
Address Decode 2

TITLE
PATTERN
REVISION
AUTHOR
COMPANY
DATE

DECODE 2
U8
01
PEER RESEARCH.
PEER RESEARCH.
30TH APRIL 1988.

CHIP DECODE PAl2ORA10
;PINS

1
IPL

2
IAEN

3
A7

4
AS

5
A9

6
DO

;PINS

7
01

8
02

9
03

10
RESET

11
ICMMD

12
GND

;PINS

13
IOE

14
IIOW

15
16
ICSRAM IRXWR

17
/WE

18
TXMODE

;PINS

19
RSTAX

21
22
20
IEDLCRST ILPBK TXRET

23
SEL

24
VCC

IAEN, address enable and AS, AS, A7, address
inputs from the PC bus are gated to form SEL
a chip select input to the lower order address
decoder logic PAl2ORA10 PATTERN U3./CMMD input
is a decoded Signal from U3 at address location
308 which enable the data inputs DO, 01, 02
and 03. When DO and CMMD are valid the 8003
EDLC chip is reset. 01 and CMMD reset the AX
counters U6 and U7. A loop back test in the
EDLC chip Is enabled when 02 and CMMD are valid
local testing of the Interface is possible
when this mode Is selected. 03 and CMMD enable
the EDLC device to mode 1 operation and 03 with
a valid CMMD Input enable the EDLC 8003 device
to perform transimlssion over the interface.
A composite RAM WE signal is generated from
CSRAM and lOW or RXWR, for PC and AXCounter
access respectively.
EQUATIONS
SEL

= AS*AS*/A7*AEN

;ACTIVE HIGH
;ADDRESS

EDLCRST
EDLCRST.CLKF
EDLCRST.SETF

:= DO
= ICMMD
= RESET

; RESET EDLC.
;8003 LOGIC
;PCRESET

RSTAX
RSTRX.CLKF
RSTRX.RSTF

:= 01
= ICMMD
= RESET

; RESET RECIEVE
;COUNTER.
;PCRESET.

LPBK
LPBK.CLKF
LPBK.SETF

:= 02
= ICMMD
= RESer

;ENABLE
;LOOPBACK
;PCRESET.

TXMODE
TXMODE.CLKF
TXMODE.SETF

:= 03
= ICMMD
= TXRET

;ENABLE EDLC
;FOR TRANS;PCRESET.

= IOW·CSRAM

WE

+RXWR

;COMPOSITE
;WRITE ENABLE
;TORAM.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - 8-116

SIMULATION
TRACE_ON

SETF

SElF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SETF
SElF
SETF
SETF
TRACE_OFF

/AEN M A8 A7 CMMO
DO 01 02 03 SEL
EOLCRST RSTRX LPBK
TXMOOE/WE
lOW CSRAM RXWR
RESET TXRET
/AEN /CMMO A7 AS M
/00 /01 /02/03
/IOW /CSRAM /RXWR
/RESET /TXRET
OE/PL
AEN
/A7
A7/AB
A8/A9
/AEN
CMMO
DO
/0001
/0102
/0203
/03
/CMMO
CSRAMIOW
/IOW
/CSRAM
RXWR
/RXWR

;TRACE ALL
; INPUT/OUTPUT
; SIGNALS

;TEST SEL OUTPUT

;TEST EOLC RESET
;TEST RXRST
; OUTPUT
;TEST LOOPBACK
;SELECT
;SELECT, TXMOOE
;TEST WRITE MODE
;SELECTION FOR
;THE RAM BUFFER.

8-117

Figure 10. EEPLD Design Specification
Handshake Logic

TITLE
PATTERN
REVISION
AUTHOR
COMPANY
DATE

HANDSHAKE LOGIC
U4
04.
PEER RESEARCH.
PEER RESEARCH.
30TH MAY 1988.

CHIP HSHAKE1 PAL20RA10
;PINS

1
IPL

;PINS

7
8
SYSCLK TXRDY

;PINS
;PINS

2
4
3
IEDLCRST TXCLK RXRDY

IG1

6
DIR1

11
10
9
TXMODE RXTXEOFNC

12
GND

IOE

14
10RDY

19
NC

22
20
21
RXTXEOFD/RXCS I~

13

15
IR'XWR

16
/TXWR

5

17

18

IQX

IQY

23

24
VCC

IRXRD

Pins RXRDY and /RXRD perform the handshake operation
between the 8003 ethemet interface and the PAL20RA10
the RXRDY high output from the 8003 chip tells the
PAL20RA10 that there exists, at least one, data byte
in the internal 16 byte FIFO. when this signal goes
high it is sampled by the rising edge of TXCLK which
is the transmitter clock output of the 8020 Manchester
encoder device. the internal state machine output of
IRXRD performs the handshake response, while IRXWE and
IRXCS cycles through a write operation. The IRXWE
signal is not used for RAM write operations it
is used here as an additional register to enable
the correct sequence in the /RXRD RXRDY handshake
state machine. it is /RXCS going active LOW that
creates the RAM write operation.
The TXRDY and /TXWR are the transmitter handshake
signals. The EDLC 8003 sends a valid TXRDY signal
when its internal 16 byte FIFO is empty. If the
handshake operation is enabled by TXMODE then the
process of reading data from the buffer RAM and
writing to the 8003's fifo continues until an end
of file (RXTXEOF) is generated by PAL20RA 10 U10.
Control of the buffer RAM is handled by RXCS and
RXWE. RXCS is the RAM chip select signal that is
active during write operations. It is gated with
two other signals in PAL20RA10 US to select the
RAM during both read and write operations. TXMODE
is enabled or disabled by software in the PC.
EQUATIONS
/RXRD

:= RXRD*~*/RXCS

/RXRD.CLKF
/RXRD.RSTF

= TXCLK
= EDLCRST
: = /RXRD*/RXWE*/RXCS

+ TXWR
+ IRXRD*/~*RXCS
+ /~*/RXCS*/RXRD
*/RXRDY

/RXWE
/RXWE.CLKF
/~.RSTF

RXCS
/RXCS.CLKF
/RXCS.RSTF
R'XWR
10RDY
10RDY.CLKF
IORDY.SETF
10RDY.TRST

+ RXRD*~*/RXCS
+ /RXRD*/RXWE*RXCS

= TXCLK
= EDLCRST
:= RXRD*/~*/RXCS
+ G1*DIR1
= TXCLK
= EDLCRST
= RXRD*RXWE*RXCS
G1*/RXRD
SYSCLK
EDLCRST
GND

;TOGGLE RXRD.
;WAITTXWR.
;HOLD RXRD ACTIVE.
;HOLD RXRD IF
; RXRDY NOT TRUE.
;CLOCK RXRD.
; RESET RXRD.
; HOLD RXWE.

;TOGGLE~.

; HOLD RXWE.

; ENABLE RAM
;ENABLE U2.

;WRITE TO RAM
;WHEN RXRD,RXWE
;RXCS ACTIVE
; ENABLE AND
;CONTROLU2
; DIRECTION.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - 8-118

TXWR

: = /TXWR*TXADY*TXMODE

QX,CLKF
QX.RSTF

;TXWR ACTIVE
*/RXTXEOFD*/RXADY*/RXRD;IF TXADY AND
+ TXWR*QX
;TXMODE SET.
+ TXWR*QY
;QXANDQY
= TXCLK
;HOLD TXWR
= EDLCRST
;ACTIVE FOR
;THREE CLOCK
: = /TXWR*TXADY*TXMODE ;CYCLES. TO
*/RXTXEOFD*/RXRDY*/RXRD;SATISFY RAM
= TXCLK
;WRITE CYCLE
= /TXMODE
;TIME.

QY
QY,CLKF
QY.RSTF

:= QX
= TXCLK
= /TXMODE

TXWR.CLKF
TXWR.RSTF
QX

; REGISTERS QX
;AND QY STRETCH
;TXWR.

RXTXEOFD
: = RXTXEOF
RXTXEOFD.CLKF = /TXWR
RXTXEOFD.SETF = /TXMODE
SIMULATION
TRACE_ON

TXCLK EDLCRST TXADY
;TRACE ON ALL
/TXWR IQX/QY RXRDY IRXRD ;SIGNALS.
I~E/RXCS/RXWRISYSCLK;

10RDY IG1 DIR1
SETF

/TXCLK ISYSCLK EDLCRST
IRXRDY OE IPL IG1
DIR1 /TXRDY TXMODE
SETF
IEDLCRST
FOR I : = 1 TO 8 DO
BEGIN
SETF
TXCLK/SYSCLK
SETF
/TXCLK SYSCLK
END
SETF
RXADY
FOR J : = 1 TO 2 DO
BEGIN
FOR I : = 1 TO 8 DO
BEGIN
SETF
RXRDY
IF I = 2 THEN BEGIN
SETF
IRXADY
END
SETF
TXCLK ISYSCLK
SETF
/TXCLK SYSCLK
END
END
SETF
IRXADY G1
FOR J : = 1 TO 4 DO
BEGIN
SETF
G1
FOR I : = 1 TO 4 DO
BEGIN
SETF
/TXCLK SYSCLK
SETF
TXCLK/SYSCLK
END
SETF
IG1
SETF
/TXCLK SYSCLK
SETF
TXCLK/SYSCLK
END
SETF
TXADY TXMODE IRXTXEOF
FOR I : = 1 TO 16 DO
BEGIN
SETF /TXCLK SYSCLK
SETF TXCLK ISYSCLK
END
TRACE_OFF

;
;SET IDLE MODE.
;NO INCOMING DATA
;FROM ETHERNET.
; NO PC ACCESS.
; CLOCK FOR EIGHT
; PERIODS TO TEST
;HOLD CONDITION.
;SET RECIEVER READY
;8003 FIFO HAS DATA
;FROM ETHERNET.
;SET A LOOP FOR
;SIXTEEN CLOCK
;CYCLES. FOUR HAND;SHAKE CYCLES TAKE
;PLACE. RXRDY TURNS
;OFF THEN ON AFTER
; FIRST AND THIRD
; HANDSHAKE.
;TURN OF RXADY
;SELECTION OF G1
; BY DECODING ADD;RESS FROM PC TO
;TEST I/O READY
; SIGNAL.

;TURN OF PC SELEC;TlON.
;TURN OF END OFF
; FILE TURN ON TXRDY
;AND TXMODE TO TEST
;THE TXRDY AND TXWR
; HANDSHAKE FOR
;SIXTEEN CYCLES.

8-119

Figure 10. EEPLD Design Specification
Rx Counter QOooQ7

TITLE
PATIERN
REVISION
AUTHOR
COMPANY
DATE

RXCOUNTER 00-07
US
04.
PEER RESEARCH.
PEER RESEARCH.
30TH MAY 1988.

CHIP COUNTER PAL20RA10
;PINS

1
/PL

2
4
3
RSTRXDC RXTXEOF /RXRD

;PINS

7
NC

8
/RXWR

9
NC

;PINS

13
JOE

14
CWY1

;PINS

19
CWYO

20
03RX

5
NC

6
NC

10
NC

11
NC

12
GND

15
07RX

16
06RX

17
05RX

18
04RX

21
02RX

22
01RX

23
OORX

24
VCC

The receive counter has been designed to give
a binary count output to the 8K RAM. Registers
OORX - 07RX are contained in PAL20RA 10 U6 and
registers 08RX - Q12RX in U7. The carry outputs
from US are connected to U7 to provide the
link necessary for a synchronous count. The
receive counter, RXCOUNTER is clocked by the
/RXWR input. After a valid RXRD (receiver
ready) /RXWR from U4 goes LOW to perform a
write cycle in the RAM. When /RXWR goes HIGH
the rising edge of this signal increments the
counter to pOint to the next location in the
RAM. The 3 - State control of U6's output
buffers are controlled by the RXRD so when
RXRD is active the registered outputs drive
the RAM address inputs. Unlike the transmit
counter the receive counter cannot be loaded
with a starting address, but it can be reset
from the PC by a decoded I/O address from the
bus. When RSTRXDC is active the contents of
the counter is asynchronously set to zero.
The RXTXEOF signal is an output from the
EDLC 8003 device during data reception, and
this signal is used to reset the counter
after a complete data frame has been received
EOUATIONS
OORX
OORX.CLKF
OORX.SETF
OORX.TRST

: = /QORX*/RXTXEOF
=/RXWR
= RSTRXDC
= RXRD

01RX

: = /01RX*OORX*/RXTXEOF
+ 01 RX*/OORX*/RXTXEOF
= /RXWR
= RSTRXDC
= RXRD

01RX.CLKF
01RX.SETF
01RX.TRST
Q2RX

Q2RX.CLKF
02RX.SETF
Q2RX.TRST

: = /Q2RX*OORX*Q1RX
*/RXTXEOF
+ 02RX*/Q1 RX*/RXTXEOF
+ 02RX*/OORX*/RXTXEOF
= /RXWR
= RSTRXDC
= RXRD

Q3RX

: = /Q3RX*Q2RX*OORX

Q3RX.CLKF
Q3RX.SETF
Q3RX.TRST

8-120

*01 RX*/RXTXEOF
+ 03RX*/Q2RX*/RXTXEOF
+ Q3RX*/01 RX*/RXTXEOF
+ 03RX*/OORX*/RXTXEOF
= /RXWR
= RSTRXDC
= RXRD

;TOGGLE QORX WHEN
; RXTXEOF INACTi'JE
; CLEAR OUTPUT
;HIGH - Z WHEN
; RXRD NOT ACTIVE.
;TOGGLE Q1RX
; HOLD 01 RX
; CLOCK 01 RX
; CLEAR OUTPUT
;HIGH -ZWHEN
;RXRD NOT ACTIVE.
;TOGGLE 02RX
;
; HOLD 02RX
;HOLD 02RX
;CLOCK 02RX
; CLEAR OUTPUT
; HIGH - Z WHEN
;RXRD NOT ACTIVE.
;TOGGLE Q3RX
;
; HOLD 03RX
; HOLD 03RX
;HOLD 03RX
;CLOCK 03RX
;CLEAR OUTPUT
; HIGH - Z WHEN

CWYO
Q4RX
Q4RX.CLKF
Q4RX.SETF
Q4RX.TRST
Q5RX

;RXRD NOT ACTNE.

= OORX*Q1RX*Q2RX*Q3RX;CARRY PROPAGATE.

: = /Q4RX*CWYO*/RXTXEOF ;TOGGLE Q4RX
+ Q4RX*/CWYO*/RXTXEOF ;
= /RXWR
;CLOCK Q4RX
... RSTRXDC
;CLEAR OUTPUT
= RXRD
;HIGH - Z WHEN
;RXRD NOT ACTNE.
: = /Q5RX*Q4RX*CWYO
;TOGGLE Q5RX
~~OF

;

+ Q5RX*/Q4RX*/RXTXEOF ;HOLD Q5RX

Q5RX.CLKF
Q5RX.SETF
Q5RX.TRST
06RX

06RX.CLKF
06RX.SETF
06RX.TRST
CWY1
Q7RX
Q7RX.CLKF
Q7RX.SETF
07RX.TRST
SIMULATION
TRACE_ON

+ Q5RX*/CWYO*/RXTXEOF ;HOLD Q5RX

= /RXWR
= RXRD

= RSTRXDC
: = /Q6RX*Q5RX*Q4RX

*CWYO*/RXTXEOF
+ 06RX*/Q5RX*/RXTXEOF
+ 06RX*/Q4RX*/RXTXEOF
+ 06RX*/CWYO*/RXTXEOF
= /RXWR
= RSTRXDC
= RXRD

= Q6RX*Q5RX*Q4RX
* Q3RX*Q2RX*Q1 RX*OORX

; CLOCK Q5RX
;CLEAR OUTPUT
;HIGH - Z WHEN
;RXRD NOT ACTIVE.
;TOGGLE Q6RX
;
; HOLD 06RX
; HOLD 06RX
;HOLD 06RX
;CLOCK 06RX
;CLEAR OUTPUT
;HIGH - Z WHEN
; NOT ACTIVE.
;CARRY PROPAGATE.
;

: = /Q7RX*CWY1 */RXTXEOF ;Q7RX TOGGLE
+ Q7RX*/CWY1 */RXTXEOF ;
= /RXWR
;CLOCK Q7RX
= RSTRXDC
= RXRD

;CLEAR OUTPUT
;HIGH - Z WHEN
; NOT ACTIVE.

/RXWR /RXRD RSTRXDC
;TRACE ALL SIGNALS.
~OF QORX Q1RX Q2RX ;
Q3RX CWYO Q4RX Q5RX
;
Q6RX CWY1 Q7RX
;

SETF
RXWR RXRD RSTRXDC /PL
OE/RXTXEOF
SETF
/RSTRXDC
FORI:- 1 TO 64 DO
BEGIN
SETF
/RXWR
SETF
RXWR
END
TRACE_OFF

; ENABLE OUTPUTS AND
;COUNTER, DISABLE
; PRELOAD.
; FOR 64 CLOCKS
;COUNT A BINARY
;ADDRESS SEQUENCE.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-121

Figure 10. EEPLD Design Specification
Rx Counter Q8.. Q12

TITLE
PATTERN
REVISION
AUTHOR
COMPANY
DATE

RXCOUNTER 08-Q12
U7
04.
PEER RESEARCH.
PEER RESEARCH.
30TH MAY 1988.

CHIP COUNTER PAL20RA10
;PINS

1
/PL

2
RSTRX

;PINS

7
IRXWR

8
9
ICSRAM /TXWR

;PINS

13
IOE

;PINS

19
CWY3

4
3
RXTXEOF/RXRD

5
NC

6
CWY1

10
RXDC

11
Q7RX

12
GND

14
15
RSTRXDC/CE1

16
IINCTX

17
CWY2

18
Q12RX

20
Q11RX

22
Q9RX

23
Q8RX

24
VCC

21
Q10RX

PAL20RA10 U7 is used in conjunction with U6
as an counter to address the 8K RAM as a
receive buffer. When the EDLC 8003 device is
receiving data the RXRDY and /RXRD handshake
control the flow of data from the EDLC's
FIFO. As with U6 RXWR and RXRD control the
incrementing and 3 - State disable of the
output buffers from each counter register.
Q7RX - Q10RX perform the conventional binary
count, but Q11 RX and Q12RX pOint to the page
boundaries at 0 - 2K, 2K - 4K and 4K - 6K.
The RXCOUNTER does not encroach into the
RAM space allocated for transmition of data,
6K - 8K. The count sequence of Q11 RX and
Q12RX is of the sequence 0 to 1 to 2 then
back to O.
Additional logic has been incorporated in
this device, IINCTX and ICE1. The IINCTX
output is a combinational sum of CSRAM and
/TXWR and is responsible for incrementing
the transmitter counter U9 and U10 after
a PC or EDLC access. The /CE1 is a sum of
CSRAM, /TXWR and /RXRD to enable RAM access
from the PC, EDLC in transmit mode or EDLC
in receive mode.
EQUATIONS

= CWY1*Q7RX

CWY2
Q8RX

: = /Q8RX*CWY2*/RXTXEOF ;TOGGLE Q8RX

OSRX.CLKF
OSRX.SETF
OSRX.TRST
Q9RX

Q9RX.CLKF
Q9RX.SETF
Q9RX.TRST
Q10RX

Q10RX.CLKF
Q10RX.SETF
Q10RX.TRST
CWY3

seeQ

; CARRY THROUGH
;FROM U6.

+ OSRX*/CWY2*/RXTXEOF
= /RXWR
= RSTRXDC
= RXRD

;HOLD Q8RX
;CLOCKQ8RX
;CLEAR OUTPUT
;HIGH - Z WHEN
; NOT ACTIVE.
: = /Q9RX*Q8RX*CWY2
;TOGGLE Q9RX
*/RXTXEOF
;
+ Q9RX*/Q8RX*/RXTXEOF ; HOLD Q9RX
+ Q9RX*/CWY2*/RXTXEOF ;HOLD Q9RX
= /RXWR
;CLOCK Q9RX
= RSTRXDC
;CLEAR OUTPUT
= RXRD
; HIGH - Z WHEN
; NOT ACTIVE.
: = /Q10RX*Q9RX*Q8RX
;TOGGLE Q10RX
*CWY2*/RXTXEOF
;
+ Q1 ORX*/Q8RX*/RXTXEOF; HOLD Q10RX
+ Q1 ORX*/Q9RX*/RXTXEOF; HOLD Q10RX
+ Q10RX*/CWY2*/RXTXEOF ;HOLD Q10RX
= /RXWR
;CLOCKQ10RX
= RSTRXDC
; CLEAR OUTPUT
= RXRD
; HIGH - Z WHEN
; NOT ACTIVE.
= CWY2*Q8RX*Q9RX*Q10RX ; CARRY PROPAGATE.

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - -

8-122

011RX
011RX.CLKF
011RX.SETF
011RX.TRST
012RX
012RX.CLKF
012RX.SETF
012RX.TRST
RSTRXDC
INCTX

;011 RX TOGGLES IF
;012RXIS LOW.
;AND NOT RXTXEOF
; ELSE HOLD.
;CLEAR OUTPUT
;HIGH • Z WHEN
; NOT ACTIVE.
: = /012RX*011 RX*RXTXEOF ;012RX TOGGLES IF
+ 012RX*/RXTXEOF
;011RXHIGHAND
= /RXWR
;NOT RXTXEOF ELSE
= RSTRX
; HOLD. CLEAR
RXRD
;OUTPUT HIGH· Z
;WHEN NOT ACTIVE.
= RSTRX + RXDC;RESET OR RXDC

: = /011 RX*/012RX
*RXTXEOF
+ 011 RX*/RXTXEOF
=/RXWR
= RSTRX
RXRD

=

=

= CSRAM
+TXWR

CE1

= CSRAM

+TXWR
+ RXRD

;CSRAM OR TXWR
; INCREMENTS TX
;COUNTER.
;RAM IS SELECTED
;FOR PC, TX OR
;RXACCESS.

SIMULATION
TRACE_ON

/RXWR /RXRD RSTRX
;TRACE ALL SIGNALS.
,
RXTXEOF oaRX 09RX
,
010RX CWY3 011RX
012RX
RXWR RXRD RSTRX/PL
; ENABLE OUTPUTS
SETF
;DISABLE PRELOAD.
OE 07RX CWY1
/RXTXEOF
;WHEN RXTXEOF NOT
SETF
/RSTRX
;ACTIVE CLOCK
FOR I : = 1 TO 64 DO
;COUNTER 64 TIMES.
;
BEGIN
SETF
/RXWR
;
SETF
RXWR
;
~D

;

TRACE_OFF

;

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-123

Figure 10. EEPLD Design Specification
Tx Counter QO .. Q6

TITLE
PATIERN
REVISION
AUTHOR
COMPANY
DATE

TXCOUNTER QO-06
U9
04.
PEER RESEARCH.
PEER RESEARCH.
30TH MAY 1988.

CHIP COUNTER PAL20RA10
;PINS

1
IPL

2
IINCTX

3
NC

4
DO

5
01

6
02

;PINS

7
03

8

9
05

10
06

11
LDO

12
GNO

;PINS

13
10E

14
NC

15
CTY1

16
06T

17
05T

18
04T

;PINS

19
CTYO

20
03T

21
02T

22
01T

23
OOT

24
VCC

04

The transmit RAM buffer counter is a load able
binary counter from the PC bus. When LDO is
active data on DO - 06 is loaded into registers
00 - 06. LDO is a signal decoded from the PC
at the I/O location 309. The /INCTX input
performs two functions, it controls the enable
output of the counter during a transmission
access to the RAM buffer and then increments
the counter on the rising edge. When HIGH the
counter outputs are in a 3 - State condition.
In a 3 - State the recieve counter can be
enabled onto the address inputs of the buffer
RAM. /INCTX comes from the RAM SELECT PAL20RA 10
U5. The binary counter 00 - 06 is synchronous
with carry enable signals CTY1 and CTYO linking
the registers in the counter.

EOUATIONS
ooT
ooT.CLKF
ooT.SETF
ooT.RSTF
ooT.TRST

:= lOOT
= /INCTX
= /OO*LOO

01T

: = /01T*OOT

= DO*LDO
= INCTX

+ 01T*/00T

01T.CLKF
01T.SETF
01T.RSTF
01T.TRST
02T

= /INCTX

= /01*LOO
= 01*LDO
= INCTX
: = /02T*00T*01T

+ 02T*/01T
+ 02T*/00T

02T.CLKF
02T.SETF
02T.RSTF
02T.TRST
03T

= /INCTX
= /02*LOO

= 02*LDO
= INCTX
: = /03T*02T*00T*01T

+
+
+
=

03T*/02T
03T*/01T
03P/00T
/INCTX
/03*LOO
03*LDO
INCTX

03T.CLKF
03T.SETF
03T.RSTF
03T.TRST

=
=

CTYO

= ooT*01T*02T*03T

=

;ooT LSB OF COUNT
;INCREMENT
; LOAD LOW
;LOAO HIGH
;HIGH-Z
;TOGGLE01T
;HOLOO1T
;INCREMENT
;LOAO LOW
;LOAO HIGH
;HIGH-Z
;TOGGLE02T
;HOLO 02T
;HOLO 02T
;INCREMENT
; LOAD LOW
;LOAO HIGH
;HIGH-Z
;TOGGLE03T
;HOL003T
;HOL003T
;HOLO 03T
;INCREMENT
;LOAO LOW
;LOAO HIGH
;HIGH-Z
; CARRY TO
;04T, 05T 06T

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-124

O4T
O4T.CLKF
O4T.SETF
O4T.ASTF
O4T.TAST
05T
O5T.CLKF
O5T.SETF
Q5T.ASTF
O5T.TAST
O6T

Q6T.CLKF
O6T.SETF
O6T.ASTF
O6T.TAST
CTY1
SIMULATION
TRACE_ON
SETF
SETF
SETF

104T*CTYO
O4T*/CTYO
IINCTX
1D4*LOO
D4*LDO
INCTX
: = 105T*Q4T*CTYO
+ O5T*/04T
+ 05T*/CTYO
= IINCTX
= 10S*LOO
= D5*LDO
=INCTX

;TOGGLEOT5
;HOLDOTS
;HOLOOT5
;INCAEMENT
; LOAD LOW
;LOAD HIGH
;HIGH-Z

: = IQ6T*OST*04T*CTYO
+ O6T*/05T
+ O6T*/04T
+ O6T*/CTYO
= IINCTX

;TOGGLEOT6
;HOLOOT6
;HOLOOT6
;HOLDOT6
;INCAEMENT
; LOAD LOW
;LOAO HIGH
;HIGH-Z

= ID6*LDO

= 06*LDO
= INCTX

= O6T*05T*04T*03T*02T ;CAAAY FOA
; NEXT STAGE
*01T*OOT
/INCTXLDO
ooT 01T 02T 03T CTYO
04T 05T 06T CTY1 OE /PL
/LDO DO 01020304
0506
OE/PLINCTX
LDO

;TAACEALL
; SIGNALS.
;TEST LOAD
; FUNCTION
;FOA ALL HIGH
;THEN ALL LOW.

ILDO IDO 101 102 /03

/04/05/06
SETF
LDO
SETF
/LDO
FOA I : = 1 TO 128 DO
BEGIN
SETF
INCTX
SETF
/INCTX
END
TRACE_OFF

seeQ

;TOGGLE04T
;HOLOO4T
;INCAEMENT
; LOAD LOW
; LOAO HIGH
;HIGH-Z

; DISABLE LOAD
; ENABLE COUNT
;FOA 128 TEST
;VECTOAS.

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - -

8-125

Figure 10. EEPLD Design Specification
Tx Counter Q7..Q12

TITLE
PATIERN
REVISION
AUTHOR
COMPANY
DATE

TXCOUNTER 07-012
U10
04.
PEER RESEARCH.
PEER RESEARCH.
30TH MAY 1988.

CHIP COUNTER PAL20RA10
;PINS

1
/PL

2
/INCTX

3
NC

4
07

5
DO

6
01

;PINS

7
02

S
03

9
04

10
CTY1

11
L01

12
GNO

;PINS

13
/OE

14
LDO

15
CTY2

16
07T

17
OST

18
09T

;PINS

19
010T

20
011T

21
012T

22
23
24
RXTXEOFTXMODE VCC

The transmit buffer counter outputs 07T - 012T
are the higher order address bits to ooT - 06T
registers from PAL20RA10 U9. 07T is ioaded from
the PC bus I/O location 309 and 010T - 012T is
loaded from DO - D4 at I/O location 3DA. The
outputs when enabled to count access locations
in the buffer RAM and are incremented by the
rising edge of /INCTX, when HIGH this signal
puts the output buffers into 3 - State.
The RXTXEOF goes active at the final count of the
counter, that is when registers 00 - 012
contain all logic HIGHs. The start location
of the data tranfer to RAM Is loaded from the
PC bus. The RXTXEOF signal, when active informs
the EOLC device that a block of data has been
read from the buffer RAM and tranmitted by the
SOO3 EOLC device The 3 - State condition of RXTXEOF
is qualified by TXMODE (and input) and /INCTX.
This is because the EOLC RXTXEOF signal also serves
as an RXTXEOF output during receive activity. The
RXTXEOF line is connected to the RXTXEOF pin of the
SOO3 EDLC Chip.
EOUATIONS
07T
07T.CLKF
07T.SETF
07T.RSTF
07T.TRST
O8T

: = /07T*CTY1
+ 07T*/CTY1
= /INCTX
= /07*LOO
= 07*LDO
= INCTX
: = /OaT*07T*CTY1
+ O8T*/07T
+ O8T*/CTY1

O8T.CLKF
O8T.SETF
O8T.RSTF
O8T.TRST
09T

09T.CLKF
09T.SETF
09T.RSTF
09T.TRST

= /INCTX
= /DO*L01
= DO*L01
= INCTX
: = /09T*08T*07T*CTY1
+ 09T*/oaT
+ 09T*/07T
+ 09T*/CTY1

= /INCTX
= /01*LD1
= 01*LD1

= INCTX

= 09T*08T*07T*CTY1

CTY2

;TOGGLE07T
;HOLD07T
; INCREMENT
; LOAD LOW
; LOAD HIGH
;HIGH-Z
;TOGGLEOaT
; HOLD OaT
; HOLD oaT
;INCREMENT
; LOAD LOW
;LOAD HIGH
;HIGH-Z
;rOGGLE09T
;HOL009T
;HOLD 09T
;HOL009T
;INCREMENT
; LOAD LOW
;LOAD HIGH
;HIGH -Z
; CARRY TO
; NEXT STAGE

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-126

Q10T

IQ10T*CTY2
Q10T*/CTY2
IINCTX
/D2*LD1
D2*LD1
INCTX

Q10T.CLKF
Q10T.SETF
Q10T.RSTF
Q10T.TRST
Q11T

:= 1011T*010T*CTY2
+ 011T*/010T

+ Q11T*/CTY2

Q11T.CLKF
Q11T.SETF
Q11T.RSTF
Q11T.TRST
Q12T

Q12T.CLKF
Q12T.SETF
Q12T.RSTF
Q12T.TRST
RXTXEOF
RXTXEOF. TRST
SIMULATION
TRACE_ON

= IINCTX
= ID3*LD1
= 03*LD1
INCTX

=

;TOGGLE Q10T
;HOLD Q10T
; INCREMENT
; LOAD LOW
; LOAD HIGH
;HIGH-Z
;TOGGLE 011T
; HOLD 011T
;HOLD 011T
; INCREMENT
;LOAD LOW
; LOAD HIGH
;HIGH-Z

: = 1012T*011T*010T*CTY2 ;TOGGLE Q12T
+ Q12T*/011T
+ 012T*/010T
+ 012T*/CTY2
= IINCTX

=ID4*LD1
= D4*LD1
= INCTX

=

012T*011T*010T*Q9T
*Q8T*07T*CTY1
= TXMODE*INCTX

INCTX LDl LOO 07T
OST 09T Ql0T CTY2
011T 012T RXTXEOF
TXMODE OE IPL
SETF
ILD1 ILOO INCTX
D7 00 D1 D2 D3 D4
CTY1 TXMODE OE IPL
LD1 LOO
SETF
SETF
ILD1 ILOO ID7 100
ID1/D2/03/04
SETF
LD1LOO
SETF
ILD1 ILOO IINCTX
FOR I : = 1 TO 64 DO
BEGIN
SETF
INCTX
SETF
IINCTX
END
TRACE_OFF

;HOLD 012T
;HOLD 012T
;HOLD 012T
; INCREMENT
;LOAD LOW
;LOAD HIGH
;HIGH - Z

;END OF FILE
;ACTIVE HIGH

;TRACEALL
; SIGNALS
;TEST FOR
; LOADING OF
; REGISTERS
;07T -012T
; ENABLE LOAD
;ALLHIGH
;THEN ALL LOW
; DISABLE LOAD
; ENABLE COUNT
;FOR 64 CLOCK
; PULSES.

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-127

Figure 11. PASCAL Software Source

Variable
Declaration

Constants

f)rogram EDLC;
{EDLC Hello Test }
{ Turbo Pascal Source Ustlng for PCW/AT 5/1/88 }
uses crt;
type
Str2 = strlng[2); Str4 = string[4);
Frame = record
DestinationAddress, SourceAddress: array[1 ..6) of byte;
ByteCount : array[1 ..21 of byte;
Data: array[1 ..46) of byte;
end;
var TransmltFrameBuffer, RecelveFrameBuffer : Frame;
ReadB}'te, Rx2kBank, TestData, TestData1 : byte;
InKey, OutChar, Select: char;
TxCount, TxFail, RxCount, RxFaii : word; i: integer;
Address, LastAddress, ReadWord : word;
Fail, InhibitMessage : boolean;
const
EDLCStatlonAddress
EDLCReceive
EDLCTransmit
Command
LoadTransmitCounterO
LoadTransmitCounter1
Fifo Data

= $300;

= $306;
= $307;
= $308;

= $309;
= $3OA;

= $3OC;

ResetEDLC
ResetRxCounter
SetEDLClpbk
SetTxMode
ResetTxMode
ResetAllCommands
NoCommand

=
=
=
=
=

StartTransmitCommand
Transmission Success
StartReceiveCommand
Received Good Frame
OldTransmltStatus
OldReceiveStatus
ResetStatus

= $08;
= $08;
= $EO;
= $20;
$80;
= $80;
= $80;

$01;
$02;
$04;
$08;
$00;
= $00;
= $00;

=

TestStationAddress : array[1 ..6) of byte = (00,11,22,33,44,55);
TestFrame : Frame =
(DestinationAddress: (00,11,22,33,44,55);
SourceAddress :
(00,11,22,33,44,55);
ByteCount :
(46,00);
Data:
(00,01,02,03,04,05,06,07,08,09,10,11,12,13,14,15,
16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,
32,33,34,35,36,37,38,39,40,41,42,43,44,45) );
ESC = #27; CR = #13; BKSP = #08;

Misc.
Functions

function UpCase(inchar : char): char;
begin
if inchar in ['a'. .'z') then Upcase : = chr( ord(inchar) and $DF)
else UpCase : = inchar;
end;
function h(number : inteaer) : char; begin
case number of O:h: ='1'0';1 :h: = '1 ';2:h: = '2';3:h: = '3';4:h: = '4';5:h: = '5';
6:h: = '6';7:h: = 7';8:h: = '8';9:h: = '9';10:h: = 'A'; 11 :h: = 'B'; 12:h: = 'C';
13:h: = '0'; 14:h: = 'E';15:h: = 'F';end; end;
function HexByte(Number : byte) ; str2;
begin Hex Byte : = h((Number shr 4) and 15) + h((Number) and 15); end;
function HexWord(Number : byte) : str4;
begin HexWord;= h((Number shr 12) and 15)+h((Number shr 8) and 15)
+h((Number shr 4) and 15) +h((Number) and 15); end;

Screen
Functions

proc:edure ClearScreen(Color: Word);
begin
TextBackGround (Color);
clrscr;
end;

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8-128

function Match (Mask, Arg : byte) : boolean;
begin Match: = not ((Mask and Arg) = 0); end;

Figure 11. PASCAL Software Source

procedure WritePCBus(Address: word; Data: byte);
begin port[Address] : = Data; end;

PC/XT/AT
I/O Port
Bus Instructions

function ReadPCBus(Address : word) : byte;
begin ReadPCBus : = port[Address]; end;
procedure ClearRAM;
var i,j : integer;
begin
WritePCBus(LoadTransmitCountero, OJ;
WritePCBus(LoadTransmitCounter1, 0 ;
for j : = 1 to 8192 do WritePCBus(FifoData, 0);
end;

RAM
Test
Procedures

procedure DumpRAM;
var i,j,k : integer;
begin
WritePCBus(LoadTransmitCountero, OJ;
WritePCBus(LoadTransmitCounter1, 0 ;
k:= 0;
while (not(k = 16)) and not(lnKey = ESC) do
begin
for j : = 0 to 15 do
begin
write((k*512 + j*32):4, ' ');
for i : = 0 to 31 do Write(HexByte(ReadPCBus(FifoData))); writeln(");
end;
writeln("); k:= k + 1; InKey:= Read Key;
end;
end;
pro~edure WritelnRAM(Address : word); var i : integer;
begin
WritePCBus(LoadTransmitCountero, Lo (Address));
WritePCBus(LoadTransmitCounterl, Hi (Address));
write(' 'Address'5 ,,).
for i : = to 31 do' Write(HexByte(ReadPCBus(FifoData)));
writeln(");
end;

0

pro~dure DumpRAMPackets; var i : integer;
begin
writeln!,,!; WritelnRAM(OOOO!; WritelnRAM(0032);
writeln " ; WritelnRAM~2048 ; WritelnRAM~2080~;
writeln "; WritelnRAM 4096; WritelnRAM 4128 ;
writeln " ; WritelnRAM 8128 ; WritelnRAM 8160 ;
end;
pro~dure

LoadStationAddress; var i : integer;
begin
fori:= lt06do
WritePCBus(EDLCStationAddress + i-l, TestStationAddress[i]);
end;
Function ReceiveEqualTransmit : boolean;
type Fb =array[1..60] of byte; var TfPtr, RfPtr: A Fb; i : integer;
begin
ReceiveEqualTransmit : = true; RfPtr: =addr(ReceiveFrameBuffer);
TfPtr: = addr(TransmitFrameBuffer);
for i : = 1 to 60 do if not(RfPtr A [i] = TfPtr A [ill then
ReceiveEqualTransmit : = false;
end;
pro~dure InitialTransmitFrameBuffer; var i : integer;
begin
fori:= 1 to 46 do ifTestData=$ll then
TransmitFrameBuffer.Data[i]: = random(255)
else TransmitFrameBuffer.Data[i] : = Testdata;
end;

procedure InitializeEDLC;
begin
WritePCBus(Command, ResetEDLC + ResetRxCounter);
WritePCBus(Command, ResetAlICommands);
ClearRAM;

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8-129

Figure 11. PASCAL Software Source

RAM
Tests
Continued

Rx2kBank : = 0;
LoadStationAddress;
WrltePCBus(EDLCReceive, StartReceiveCommand);
WritePCBus(EDLCTransmit, StartTransmitCommand);
end;
proc:edure Initialize;
begin
TxCount : = 1; RxCount: 0;
TxFaii : = 0; RxFail: = 0;
Randomize;
Inkey:= ";
TransmitFrameBuffer : = TestFrame;
InitialTransmitFrameBuffer;
InitializeEDLC;
gotoxy(20, 2); write('SEEQ 8003 EDLC Demonstration V1.0');
end;

=

proc:edure RAMTest;
begin
InKey : = '1'; Fail: = false; LastAddress: = 4095;
Initialize;
gotoxy(1, 3);
while not (!nKey = ESC )do
be~in

WntepCBUS!Command, ResetEDLC);
WritePCBus Command, ResetAIlCommands);
WritePCBus LoadTransmitCounterO, 0);
WritePCBus LoadTransmitCounter1, 0);
for Address: = 0 to LastAddress do
be~in

WntePCBus(FifoData, Hi (Address»; { write(H( Lo(Address)), ' ');}
WritePCBus(FifoData, Lo(Address»; { write(H( Hi (Acldress)) , ' ');}
end;
WritePCBus(LoadTransmitCounterO, 0);
WritePCBus(LoadTransmitCounter1, 0);
Address: = 0;
while not (Address = LastAddress+ 1) and
not (InKey = ESC) do
begin
ReadWord : = ReadPCBus(FifoData);
ReadByte: = ReadPCBus(14foData);
ReadWord : = swap(ReadWord) + ReadByte;;
if not(ReadWord = Address) then
begin
writeln('Address = ',HexWord(Address),
'Read DATA = ',HexWord(ReadWord));
InKey : = read key; Fail: = true;
end;
Address : = Address + 1;
end'
if keipressed then InKey : = read key;
if Fall then writeln('Fail RAM Test')
else
writeln('Pass RAM Tesf);
end;
end;

Receive
Frame

Transmit
Frame

procedure ReceiveFrame;
var i : integer;
begin
WritePCBus(LoadTransmitCounterO, 0);
WritePCBus(LoadTransmitCounter1, Rx2kBank*8);
with ReceiveFrameBuffer do
begin
for i: = 1 to 6 do DestinationAddress[i]: = ReadPCBus(FifoData);
for i: = 1 to 6 do SourceAcldress[i] : = ReadPCBus(FifoData);
for i: = 1 to 2 do ByteCount[il: = ReadPCBus(FifoData);
for i: = 1 to 46 do Data[i] : = AeadPCBus(FifoOata);
end;
if Rx2kBank = 2 then Rx2kBank : = 0
else Rx2kBank : = Rx2kBank + 1;
end;
procedure TransmitFrame(CurrentMode : byte);
var i : integer;
begin
WritePCBus(LoadTransmitCounterO, $C4);
WritePCBus(LoadTransmitCounter1, $FF);

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8·130

with TransmitFrameBuffer do
begin
for I: = 1 to 6 do WritepCBUS{FifoData,DestinatiOnAddreSS[i]);
for I: 1 to 6 do WrltePCBus FifoData, SourceAddress[i] );
for i: = 1 to 2 do WritePCBus Fifo Data, ByteCount[i] );
for i: = 1 to 46 do WritePCBus(FifoData, Data[i] );
end;
WritepCBUS{LOadTransmitCounterO, $C4);
WritePCBus LoadTransmitCounter1, $FF);
WritePCBus Command, SetTxMode + CurrentMode);
end;

Figure 11. PASCAL Software Source

=

procedure ReadCharacter;
var SaveX,SaveY : byte;
begin
while not keypressed do
begin
ReadByte: = ReadPCBus(EDLCReceive);
if not Match ( OldReceiveStatus, Read Byte) then
begin
SaveX: = whereX; SaveY: = whereY;
gotoxy(3,10);
write!'Receive Status = " Hex Byte (Readbyte) , , ');
RecelveFrame;
gotoxy'(3,6);
write( Receive Message ');
i:= 1;
rereat
i i = 1 then clreol;
OutChar : = (chr(ReceiveFrameBuffer.Data[i]));
if OutChar in ['0' ..'9', 'a' ..'z', 'A' ..'Z','.',',',' '] then write(OutChar);
i:= i + 1;
until (i = 47) or (OutChar = CR) or (OutChar = ESC);
gotoxy(1,13); DumpRAMPackets;
gotoxy(SaveX,Savey);
end'
end; ,
In Key : = readkey;
end;
procedure HelioHello;
var i : integer;
beQin
Initialize; InKey : = '7';
while not (InKey = ESC) do
begin
gotox;r:(3,4); clreol:
write ( Transmit Message ');
i:= 1;
repeat
ReadCharacter;
if InKey in ['0' ..'9', 'a' ..'z', 'A' ..'Z','.',',',' '] then
begin
write (In Key);
TransmltFrameBuffer.Data[l] : = ord(lnKey);
1:= I + 1;
end;
if (In Key = BKSP) and not (i = 1) then
begin
write(BKSP); write(' '); wrlte(BKSP);
i:= i-1;
TransmitFrameBuffer.Data[i] : = ord(, ');
end;
until (i = 47) or (InKey = CR) or (In Key = ESC);
while not Q = 47) do
begin
TransmitFrameBuffer.Data[i] : = 0;
1:= I + 1;
end;
TransmltFrame(NoCommand);
Read Byte : = OIdTransmitStatus;
1:= 1;
while Match(OldTransmitStatus, ReadByte) and not (i = 1(00) do
begin
Read Byte : = ReadPCBus(EDLCTransmit); i : = i + 1;
end;
WrltePCBus(Command, ResetTxMode);
gotoxy(3,8);

8-131

Read
Character

Hello Hello

I

Figure 11. PASCAL Software Source

Display
Frame

Wait
for
Status

Echo
Frame

LoopBack
Test

write('Transmit Status = " Hex Byte (Read byte) , ' ');
TxFaii : = TxFaii + 1;
gotoxy(1,13);
DumpRAMPackets;
end;
end;
Procedure WriteFrame(Buffer : Frame);
type Fb = array[1..60] of byte; var RfPtr: "Fb; i : integer;
begin RfPtr: =addr(Buffer); for i : = 1 to 14 do
write(HexByte(RfPtr" [i]), ' '); writeln(");
for i : = 15 to 37 do
write (HexByte(RfPtr" [I]), "); writeln(");
fori:= 38 to 60 do
write(HexByte(RfPtr" [i]), ' '); writeln(");
end;
procedure WaitWhile(Device : word; Status: byte);
var i : integer;
begin
Read Byte : = Status;
i:= 1;
while Match (Status , Read Byte) and not (i = 10000) do
begin
Read Byte : = ReadPCBus(Device); i: = i + 1;
end;
write (HexByte(Readbyte), ':');
end;
procedure EchoFrames;
var i : integer;
beQin
Initialize;
while not(lnKey = ESC) do
begin
gotoxy(1,13);
Read Byte : = OldReceiveStatus;
while Match(OldReceiveStatus , Read Byte) and not keypressed do
ReadByte: = ReadPCBus(EDlCReceive);
write (HexByte(Readbyte), :');
if Match ( ReceivedGoodFrame, ReadByte) then
writeln('Receive Good Frame') else
begin
writeln('Receive Fail
'); RxFail: = RxFaii + 1;
end'
ReceiveFrame; TransmitFrameBuffer : = ReceiveFrameBuffer;
if not Inhibit Message then WriteFrame(TransmitFrameBuffer);
writeln(");
TransmitFrame(NoCommand);
WaitWhile(EDlCTransmit, OldTransmitStatus);
WritePCBus(Command, ResetTxMode);
if Match ( TransmissionSuccess, Read Byte )
then writeln('Transmit Successful') else
begin
writeln('Transmit Fail'); RxFail : = RxFaii + 1;
end;
writeln(");
Write('COunt = " TxCount,' RxFaii = " RxFail,'
');
TxCount : = TxCount + 1;
if keypressed then InKey : = read key;
end'
end; ,
pro~dure loopBackTest(CurrentMode : byte); var i : integer;
beQin
Initialize;
WritePCBus(Command, CurrentMode);
while not(lnKey = ESC) do
begin
gotoxy (1,13);
TransmitFrame (CurrentMode);
WaitWhile(EDlCTransmit,OldTransmitStatus);
WritePCBus(Command, ResetTxMode + CurrentMode); clreol;
if Match( TransmissionSuccess, Read Byte )
then writeln(,Transmission Successful')
else writeln('Transmission Fail');
if not InhibitMessage then WriteFrame(TransmitFrameBuffer);
writeln("); WaitWhile(EDlCReceive, OldReceiveStatus);

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - 8·132

if Match( ReceivedGoodFrame, ReadByte) then
begin
ReceiveFrame; writeln('Receive Good Frame');
if not InhibitMessage then WriteFrame(ReceiveFrameBuffer);
if ReceiveEqualTransmit then
begin if CurrentMode = SetEDLCLpbk then
write('EDLC Loopback Test Pass')
else write('EDLC Transmit Test Pass');
end
else
begin
if CurrentMode = SetEDLCLpbk then write('EDLC Loopback Test Fail')
else write('EDLC Transmit Test Fail');
RxFail : = RxFail + 1; InitializeEDLC;
end;
end
else
begin writeln('Receive Fail
'); writeln(tt);
if not InhibitMessage then begin Writeln("); Writeln(tt); Writeln(tt); end;
end'
writeln(");
clreol; Write(, TxCount = " TxCount,' RxFaii = " RxFail, ' ');
TxCount : = TxCount + 1; InitialTransmitFrameBuffer;
if keypressed or (InKey = ") then InKey: = read key;
end;
end;
beQin !main program}
Initialize;
TextColor(yellow); InhibitMessage: = false; TestData : = $11; Select: = '1';
while not (Select = ESC) do
begin
ClearScreen(Blue); InKey : = '1';
gotoxy 20, 2); write 'SEEQ 8003 EDLC Demonstration V1.0');
gotoxy 25, 5; write 'H - Hello Hello');
gotoxy 25, 6; write 'L - Loop Back 1es1');
gotoxy 25, 7; write 'T - Transmit Data Frames');
gotoxy 25, 8; write 'E - Echo Frames');
gotoxy 25, 9; write('R - RAM Tes1');
gotoxy 25'10~; write('D - Dump RAM');
gotoxy 25,11 ; write('B - Dump RAM Brief);
gotoxy 25,12; if not InhibitMessage then
write('l- Messages = ON') else write('l- Messages = OFF);
gotoxy(25, 13); case TestData of
$11: writei'C - Data = Random'); $00: write('C - Data = hexOO'~;
$55: write 'C - Data = hex55');
$AA: write('C - Data = hexAA);
$FF: write 'C - Data = hexFF'); end;
gotoxy(25, 14); write('Esc - Quit to DOS');
gotoxy(25,16); if Select = '#' then
begin sound(400); delay(10);
write(,ERROR!, enter new selection'); nosound;
end
else
write('enter selection');
Select: = UpCase(readkey);
ClearScreen(red);
case Select of
'H': HelioHello;
'L': LoopBackTest(SetEDLCLpbk);
'T': LoopBackTest(NoCommand);
'E': EchoFrames;
'R': RAMTest;
'D': DumpRAM;
'B': begin gotoxy(1,13); DumpRAMPackets; InKey : = read key; end;
'I': InhibitMessage : = not InhibitMessage;
'C': begin case TestData of $11: TestData1 : = $00;
$00: TestData1 : = $55;$55: TestData1 : = $AA;
$AA: TestData1 : = $FF;
$FF: TestData1 := $11;
end;
TestData : = TestData1
end;
ESC: write('Qui1');
else Select: = '#'
end; {case}
end;
ClearScreen (Black);
end.

8-133

Figure 11. PASCAL Software Source

LoopBack
Test
Continued

Main Program

Menu
Display

Menu
Calls

I

PALASM is a registered trademark of Monolithic Memories,
a wholly owned subsidiary of Advanced Micro Devices.
ABEL is a trademark of DATA I/O Corporation.
CUPL is

a trademark of Logical Devices Inc.

MINC is a trademark of MINC.
Turbo PASCAL 4.0 is

a trademark of Borland International Inc.

seeQ Technology. Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - 8-134

GENERAL INFORMATION

Thermal Resistance of
SEEQ Products
March 1987
LEAD COUNT

20
24
28

32
40

(C/WATTS)

PACKAGE TYPE

9JJA (C/WATTS)

CERDIP (300 MILS)

60

22

PLCC

60

UE

CERDIP (600 MILS)

58

21

PLASTIC DIP (600 MILS)

49

UE

CERDIP (600 MILS)

45- 55

21

PLASTIC DIP (600 MILS)

40- 50

UE

LCC

50-65

18

PLCC

58

UE

CERDIP (600 MILS)

42

18

eJC

NOTES: 1. Actual Thermal Resistance of a given device may vary from the value on the table, this table contains the
representative values for the package types specified.
2. All plastic package data refers to CU leadframe material.
3. All values are for socketed units.
4.

UE =
LCC =
DIP=
PLCC =

Under evaluation
Leadless Chip Carrier
Dual-In Line Package
Plastic Leaded Chip Carrier

Packaging Information
SEEa Plastic Packages Incorporate:

SEEa Cerdip Packages Incorporate:

•
•
•
•

•
•
•
•

High thermal conductivity copper leadframe.
Silver-filled epoxy die attach material.
Gold bond wires.
Low stress, moisture-resistant molding compound.

9-1

Thermal conductivity Alumina substrates.
Gold Silicon Eutectic die attach.
Alloy 42 leadframe.
Aluminum bond wires.

PLASTIC DUAL-IN-LINE PACKAGES
20 LEAD PLASTIC PACKAGE TYPE P

_

1.035 (26.29) 1 .025 (26.04)
(NOTE 2)

1

,. TYP. (4 PLeS)

.130 (3.30) NOM.

t
.070 (1.78)
.060 (1.52)

-II~

l ~!:i~~~r r-

:~~ !: ::i:l

.170 (4.32) MAX

J;Vi ~I~ ~ ~F,~F R~::::: ~::E ~':: ~
u

~~

.065 (1.65)
.055(1.40)

~: ~
_

~

.1 ~~~54)

_~ t

.015(.38) MIN.

'h

-I

.160 (4.06)
.125 (3.18)
.021 (.53)
.015 (.38)

0".15"

:1\

~

......
_

.010±.OO2 (.25±.05)
(NOT';: 5)
~300

(7.62) •

I-

.310/.350 (7.87/8.89)

NOTES

1. All dimensions are in Inches and (millimeters).
2.
3.
4.
5.

Dimensions do not include mold flash. Max. allowable mold flash is .010 (.25).
Dimension is measured from shoulder to shoulder
Tolerances are ± .010 (.25) unless otherwise specified.
For solder dipped leads, thickness will be .020 (.51) max.

~~~~~~~~fu~~~~O~~d---------------------------------~
9-2

PLASTIC DUAL-IN-LINE PACKAGES
24 LEAD PLASTIC PACKAGE TYPE P

1--_ _ _ 1.1~J~~.94)---.-j

i'

, / PIN 1 INDICATOR

.530 (1 3.46)
.550 (13.97)
(NOTE 2)

L_~"T"T"""I""T"""~~
1.255 (31.88)

If4·----1.~:M~12~2) -----

.075 (1.91)

~"'.j~
SEATING PLANE _

.190(4.83) MAX.

.

7 TYP. (4 PLCS)
Q

-l I- .080 (2.03)

0 70
m r_m
_(1_.7_a_I
rm
_f
_
f_
i_
-_
- +-1-1
_--..
·_ .

-+;

1

.

- I.065 (1.65)
.055 (1.40)

1

1

___t_.015(.3~) MIN.

i

I

-II
.020 (.51 I
.016 (.41)

'~~~~!::':l

I I

H

.100 (2.54)

~1) NO:.

.
esc

[
Q

Q

t600(15'24~·15
BSC

n

::~~ ~:~:l

NOTES
1. All dimensions are in inches and (millimeters).
2. Dimensions do not include mold flash. Max. allowable mold flash is .010 (.25).
3. Dimension is measured from shoulder to shoulder
4. Tolerances are ± .010 (.25) unless otherwise specified.
5. For solder dipped leads, thickness will be .020 (.51) max.

~~~~hC~Ofu~~~~O~~d----------------------------------~
9-3

PLASTIC DUAL-IN-LINE PACKAGES
24·LEAD SLIM PLASTIC PACKAGE TYPE P

.325 (8.26)
.300 (7.62)
.170 (4.32) MAX

:g~~ ~U~~

.
I

1

.130 (3.30)
NOM
.1.255 (31.88)
1.245 (31.62)

.. ,

SEATINGW

~NE

f I -1I 1f 1f ~ 1f 1f lJ lJ 1I 1I 1I 1I~----~~~
I I
t

JL

.015 (0.38) MIN

.270 (6.86)
.250 (6.35)

.020(0.51)
.016 (0.41)

---r-

I

~

I

~

:g~~ !U~~

-Jtj\

.012 (0.30)
.135 (3.43) .008 (0.20):.J..125(3.18)

.100 (2.54)

sse

.300 (7.62)

I

~

sse

NOTES:
1. All dimensions In Inches and (millimeters).
Dimensions do not Include mold flash. Maximum allowable mold flash is .010 (.25).
Dimension Is measured from shoulder to shoulder.
Tolerances are :t .010 (.25) unle.. otherwise specified.
For solder dipped leads, thickne.. will be .020 (.51) max.

2.
3.
4.
5.

seeQ
MD400065/A

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - -......

9-4

PLASTIC DUAL-IN-LINE PACKAGES
28 LEAD PLASTIC PACKAGE TYPE P

I

PIN 1 INDICATOR

.550 (13.97)
.530 (1 3.46)
(NOTE 2)

L ~rTT"T'T""T'T"TT"1"T"TT"T'T"""""""~
1 .455 (36.96)
••_ _ _ _ 1.~~~~62~0) _ _ _----<~

I

NOTES
1. All dimensions are in inches and (millimeters).
2. Dimensions do not include mold flash. Max. allowable mold flash is .010 (.25).
3. Dimension is measured from shoulder to shoulder.
4. Tolerances are ± .010 (.25) unless otherwise specified.
5. For solder dipped leads, thickness will be .020 (.51) max.

~~~~~~~~~~~~O~~d----------------------------------~
9-5

PLASTIC DUAL-IN-LINE PACKAGES
40 LEAD PLASTIC PACKAGE TYPE P

.
I

'I

1.900
(48.28)
REF.

:ll~f[:::::::: :::::::::: ]~~N"N~~ .

1

8 25

I.

.075(1.91)
.085(.,85)1

_II-I

,
a-3 )MAX
'190--'Jr-.
-l - - .

:::: !::::~l.

.800 (15'88)J
(15.24)

,I

(NOTE 3)

(NOTE 2)

.085(2.18)
.075(1.91)

.150(3.a1)NO~

~ ~ ~ ~ ~ ~ I~I ~ ~ ~ ~ ~ ~ ~ ~ lUi ~ ~ t ::l~~
- ~

.055 (1.40)
.045 (1.14)

-II.020 (.51)
.018 (.41)

.015(.38) MIN.

1
I

SEATING PLANE.100 (2.54) BSC

J

~

n\.
:'~
Lr-.... ,'····,·:~r~\::~g g~:~:l--

.0'2(.301
008 (20)
iNOTE 5)

NOTES
1. All dimensions In Inch. . .nd millimeters).
2. Dimensions do not Include mold flaah. Allowable mold fI.ah la .010 (.25).
3. Dlmenalon la m. .aured from ahoulder to ahoulder.
4. Tolerencee .... ± .010 (.25) unle.. otherwl.. epeelfled.
5. For .older dipped leeda, thlckne.. will be .020 (.51) m.x.

L---

SeeQ Technology,lncorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
9-6

CERAMIC DUAL-IN-LINE PACKAGES
20 LEAD HERMETIC CERAMIC DIP PACKAGE TYPE D

~
I

::~~~;:~~:~
.900 REF.
(22.86)

•

I

[: : : : : : : : ]j~:~
~~

.330(8.38)
.300(7.62)

.015 (.38)

i(NOTE3)1

.040(1.02)

-11--.

005 (.13) MIN.

.200"'t-M-AX-.--~
(5.08)
SEATING
PLANE

L

*
.070J78)
.020 (0.51)

-J ~

JL

.020(0.51)
.016 (0.41)
•085(1.65)
.045 (1.14)

.17&(4.45)
.140(3.56)
t

-l f-.110(2.79)
.090 (2.29)

~
1-.
)I

l~

:~:~!:::
f

J
t

0°/10°
REF.

.015(.38) REF.
GAGE LINE

.012 (.30)
.008(.20)

380 (9.65)--l
.330(8.38)

.1SO(3.81)
MIN .

NOTES
1. For solder dipped leads, thickness will be .020 max.
2. All dimensions In Inches and (millimeters).
3. Dimension Is measured from outside shoulder to shoulder. This
complies with MII-M·38510, Appendix C, Dimension E2 on D outlines
which measures from center of shoulder·to-shoulder per section SOc min•
. 290 (7.37) max.• 320 (8.13).

seeQ

Technology, Incorporated _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _-1

9-7

CERAMIC DUAL-IN-LINE PACKAGES
24 LEAD HERMETIC CERAMIC DIP PACKAGE TYPE D

1

.600 (15.24)
.515 (13.08)

!

-i

.624 (15.65)
.600 (15.24)
(NOTE 3)

.225 (5.72) MAX.

~~~~G ~L_-..1-==~~:...'1

I

00/100

!-REF.

.050 (1.27)-.--1
.020 (0.51)
.110(2.79)
.090(2.29)

.125J16)
.160(4.06)
.150 (3.81) MIN.

J L
,.

.700 (17.78)
.620 (15.75)

JI

NOTES
1. All dimensions in inches and (millimeters).
2. For solder dipped leads, thickness will be .020 (.51) max.
3. DimenSion is measured from outside shoulder-ta-shoulder. This
complies with MII-M-38510, Appendix C, Dimension E2 on D outlines
which measures from center of shoulder-ta-shoulder per section SOc min •
•590 (14.99) max•• 620 (15.75).

~~~~~~~~~~~~O~~d----------------------------------9-8

CERAMIC DUAL-IN-LINE PACKAGES
24-LEAD HERMATIC SLIM CERAMIC PACKEGE TYPE 0

.308 (7.82)
.288 (6.81)

.320 (8.13)

.200 (5.08)
MAX.

1.250 (31.65)
1.230 (31.24)

1

_II-I

- .295 (7.4.,

.180 (4.57)
.065 (1 .65)
.045 (1.14)

.140 (3.56)
~

I---

-l-~
t-.-MIN. 1 -I
+ t
~I~ ~Il- -~'!-;-IN-.-:~~-5'-:!:::

.150(3.81)

-- -

l.I

+.060(1.52)
.020(.51)

F\v

l 1
0° - 15°

.020(.508)
.016 (.406)

l\...- .008

.012 (.30)
(.20)

.400(10.16)_
.320(8.13)

.110(2.79)
.090 (2.29)

NOTES
1. For eolder dipped leeds, thlckne.. will be .020 max.
2. All dlmenaions In Inches and (millimeters).
3. Dlmenlion Is measured from outside shoulder·to-shoulder. This
compile. with MII-M-38510, Appendix C, Dlmenlion E2 on 0 outlines
which measures from center of shoulder·to-shoulder per section 50c min .
.290 (7.37) max.. 320 (8.13).

seeQ Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - -.....
MD 400065/A

9-9

CERAMIC DUAL-IN-LINE PACKAGES
28-LEAD HERMETIC CERAMIC DIP PACKAGE TYPE D

.57± .05
(14.48 ± 1 .27)

1.43 ± .055
,.1475 ± .0275
(38.32 ± 1.4) - - - - - (3.75 ± .7)

M8X-'--l

0-.225

~ ~ ~ ~ ~ ~ ~ ~ ~ ~ I~I ~ ~ t

l.02
IS.'"

-L

(1.02 ± .51)

I

O"IO;';:;~ rll;o"r~';';'2 ~'N
1-

(2.54 ± 0.25)

I

(0.45 ± 0.05)

.0525 ± .0125
(1.33± .32)

NOTES
1. All dimensions in inches and (millimeters).
2. For solder dipped leads, thickness will be .020 (.51) max.
3. Dimension is measured from outside shoulder·ta-shoulder. This
complies with Mi1-M·38510, Appendix C, Dimension E2 on D outlines
which measures from center of shoulder-ta-shoulder per section SOc min .
. 590 (14.99) max•• 820 (15.75) .

.....--- SeeQ Technology. Incorporated
9-10

CERAMIC DUAL-IN-LINE PACKAGES
28 LEAD HERMETIC WINDOWED CERAMIC DIP PACKAGE TYPE D

0.558±0.043

' ' '1' .09'
I

1.46O±0.025
(37.08±0.64)

•

I

O.240MA~
I* i I ~
(6.10)

-

I

0.612±0.012
(15.49±0.25)-j
(NOTE 3)

,1

~'015 O'~~ ~ ~rII~,~~'N
(0.89±0.38)

(2.54±0.25)

(0.45±0.05)
0.055±0.010
(1.4O±0.25)

NOTES
1. All dimensions in inches and (millimeters).
2. For solder dipped leads, thickness will be .020 (.51) max.
3. Dimension Is measured from outside shoulder-to-shoulder. This
complies with MII-M-38510, Appendix C, Dimension E2 on D outlines
which measures from center of shoulder-to-shoulder per section 50c min.
. 590 (14.99) max.. 620 (15.75).

~~~~~c~o~n~~~O~~d----------------------------~
9-11

CERAMIC DUAL-IN-LINE PACKAGES
32-LEAD HERMATIC CERAMIC DIP PACKAGE TYPE D

E

1.685(42.8111
1.635(41.531
1.51111(38.1111 REF.

:r1

~..I......1-.L.!1
.61111115.241
.515113.881

~~~
l

·II98(2.291
.114511.141

1_.

628 (15.751

Ie: .""5.'"

l~,~~.
L

.728118.291
• 621t115. 751

]

\r-'
.11121.381
.11881.2111

~

NOlES,
I.
2.
3.

FOR SOLDER DIPPED LEADS. THICICNESS WILL BE .II21II IIRX.
ILL OIHENSIDHS IN INO£S lIND (HILLIHElERSI.
_ oI HENS ION IS HEASlJRED FRDH IlJTSIOE SHOULDER TO SHOUlDER.

seeQ
MD 4000651A

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

9-12

CERAMIC DUAL-IN-LINE PACKAGES
32-PIN CERAMIC SUBSTRATE MODULE TYPE M

I----I-U::l:'~l

~

I

I~HRRHRRI
I

~

-

-

UU, ~ U
u

u

-

IU

,

i

--I I--

IIHHHHfl

I II II

I

G.3=~:'3)

g:=~::~

I

l

]

-

0.091 (2.51)
0.081 (2.01)

U

~:. u J Lll~ II
0.022 (0.51)
0.004 (0.10)

NOTE: All dimensions in inches (millimeters).

seeQ T e c h n o l o g y . l n c o r p o r a t e d - - - - - - - - - - - - - - - I
9-13

CERAMIC DUAL-IN-LINE PACKAGES
40 LEAD HERMETIC CERAMIC DIP PACKAGE TYPE D

.800 (15.24)
.515 (13.08)

I
1-.090 (2.23)
.045 (1.14)
065 (1 ISH

II~

:045(1:1..4_.....;

SEATING
PLANE

~

~i

--,---

.225(5.72)
MAX.

.060(1.52)
.020(0.51)

JL

.020(0.51)
•018 (0.41)

____I..I~
.oos (.13) MIN.

.175(4.45)
.140(3.51)

--t--.--

.124(15.84

A
I

c:::::r::r=:J

1~15

(.38) REF.

GAGE UNE

::: t:

SEE NOTE 1

'12S(3'18)J
.180(4.08)

.110(2.79)
.090(2.29)

.150(3.81) MIN•

NOTES
1. For sold.r dipped I.ada, thlckn... will be .020 max.
~. All dlm.n.lon. In Inch. . .nd (mllllmr-rst.
3. Dlm.n.lon I. mea.untel from
'8hOUlaer to shoulder. Thl.
compll •• with MII-...38510, Appendix C, Dlm.n.lon E2 on D outline.
which m •••ures from c.nt.r of .hould....to-.hollld.r per section 50c min•
•590 (14.99) max. .820 (15.75).

ou1alcl.

seeQ T e C h n o l o g y , l n c O r p o r a t e d - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '
9-14

SURFACE MOUNT PACKAGES
28.. PIN CERAMIC LEADLESS CHIP CARRIER TYPE L

I

r·040X45.
(1.02x45·)
3 PLCS

~

rn
.un

.460 (11.68)
.44 2 (11.23)

.435 (11.05)

I

~

I

.OO9R
(.23R)
0.28 (0.71)
.022 (0.56)
(28 PLCS)

II-- - -- +I ----

-+T

I
I

I

--.l

t

t

.055 (1.40)
.045 (1.14)

.020 x 45·
(0.51 x45·)

L
t

.075 (1.91)
.060 (1.52)

Ilonnmnnnil

~
t

.062 (1.57)
.050 (1.27)

Notes:
1. All dimensions in Inches and (millimeters).
2. All tolerences shall be :t 0.010 (0.25) unless otherwise specified.

seeQ
MD4000651A

Technology, Incorporated

----------------------------1
9·15

SURFACE MOUNT PACKAGES
32 PIN CERAMIC LEAD LESS CHIP CARRIER TYPE L

~.~::.~~I

INDEXCORNER~C:0.67-10.16)

.02o±.010 x 45°
(.51±.25 x 45°)

~EF.

IIL w
I

.400
(10.16)

(13.21)

.560-.544
(14.22-13.82)

.520-.500
(13.21-12.70)

!

J

.045-.055
(1.14-1.40)
(TYP. 31 plcs.)

.040 x 45°
(1.02 x 45°)
(TYP. 3 plcs.)

.071-.059
(1.60-1.50)

H
tu

I

.082-.068
(2.08-1.73)

NOTES

1. All dimensions in inches and (millimeters).
2. All tolerances shall be ± .010 (.25) unless otherwise specified.

~~~~hC~O~~~~~O~~d-------------------------------~
9-16

SURFACE MOUNT PACKAGES
32 PIN WINDOWED CERAMIC LEADLESS CHIP CARRIER TYPE L

_

~
~-r

INDEX CORNER

.56
(14.2 2·13.32)

.520-.500
(13.21-12.70)

L

.458-.442
(11.63'11.23)

j
.020 ± .010 x 45"
(.51 ± .25 x 45")

I

.420-.400_
j-c10.67.10.16)

-

:T
I

0 u'
I

.400

I

.009± .OO5R
(.23 ± .13)

I

.300

--I

I-(7.62)---1

.040 x 45"
(1.02 x 45")
TYP. 3 PLCS

.015 MIN. (TYP.)
(.38)

.115-.098

"Fr
Il:::!

_. . .
o71
(1.80-1.50)

NOTES
1. All tolerances shall be ± .010 (.25) unleaa otherwise specified.
2. All dimensions are in inches and (millimeters).
3. Drawing 295003 forms a part of this drawing.

seeQ

Technology. Incorporated

9-17

SURFACE MOUNT PACKAGES
20 PIN PLASTIC LEADED CHIP CARRIER TYPE N

.045 x 45'
(1.14 x 45')

PIN NO.1 IDENTIFIER

n7~

I
I

.385 (9.78)
.395 (10.03)

----Efj-------I
I

~I---=-I...-J_.~'••~ ~
I
~
1_-----·385(9.78)
.395 (10.03)

.030 (.76)

.050(1.27)

REF.

REF.

1_

.020 (.51) MIN •

'--~-r------,Io--L~

.025(.84)
R
.045 (1.14)

.015(.38)
.025(.84)

NOTES
1. All dimensions In Inches and (millimeters).
2. All tolerances shall be ± ..003 (.08)
unle.. otherwise specified.
3. Dimensions do not Include mold flash.
Max allowable flash Is .008 (.20).

~~~~~~~~~~~~O~~d-------------------------------~
9-18

SURFACE MOUNT PACKAGES
28-PIN PLASTIC LEADED CHIP CARRIER TYPE N

.045x45°
(1.14 x 45°)

PIN NO. 1 IDENTIFIER

. .m
(".J1
"'"

,_.-

I

--+-L __ _
I

REF.
0.300
(7.62)

.0454 (11.53)

~.~("53)~1

I.-

I Ij.-

.030 (.76)
REF. --.j

...----..... ...)~

.050 (1.27)

REF •

("

.025 (.64)
R

_0.420(10.67)~

Notes:
1. All dimensions in inches and (millimeters).
2. All tolerences shall be ± .003 (.08) unless otherwise specified.
3. Dimensions do not include mold flash. Maximum allowable
flash is .008 (.20)

seeQ
MD 4000651A

Technology, Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - '

9-19

S.URFACE MOUNT PACKAGES
32 PIN PLASTIC LEADED CHIP CARRIER TYPE N

.485 (12.32)
.495 (12.57)
.449 (11 .41)
.453 (11.51)

PIN 1

jl·i·

.300 REF. (7.620)
C

'.'43)

~~~~~ t 1....!,.

11)

.585 (14.86)

f
.400 REF.
(10.160)

.549 (13.95)
.553 (14.05)

!

_1

-

.390 (9.91)
.430 (10.92)

.123 (3.12)
.140 (3.56)
.015 MIN. (.381)

1-11:
30·

Y
J..
t

-U-t-

NOTES

-I

1. All dimensions In Inch.. and (m""mete..).
2. A" tot...nc.s shall be ± .003 (.076)
un .... oth.rwl.. specified.
3. Dimensions do not Include mold flash.
Max allowabl. flash Is .008 (.20).

.015 (.38)
.025(.64)

.010(.254)

j.-

.078 (1.981)
.095 (2.413)

~~~~~~~~n~CM~~~d----------------------------~
9·20

SURFACE MOUNT PACKAGES
68 PIN PLASTIC LEADED CHIP CARRIER TYPE N
(.045

1_ _ _ _ _ .800 (20.32)-----1

x 45°)

REF.

('lIT
1------.953(24.21)

1------ .985 (25.02)
.995 (25.27)

~I

=====.i
.042 (1.07)
.056 (1.42)

l

E'Il--

"0'-

.020(.51) MIN •

1

.025 (.64)
.045 (1.14)R

T.015 (.38)
.025 (.64)

.890 (22.61)
.930 (23.62)

NOTES
1. All dimensions are in Inches and (millimeters).
2. Tolerances are ± .003 (.08) unless otherwise specified.
3. Dimensions do not include mold flash. Max. allowable flash is .008 (.20).

1
w_I

I.
~
~

.170 (4.32)
.180 (4.57)

Technology. Incorporated

9-21

.108(2.74)
.118(3.00)

SURFACE MOUNT PACKAGES
28-LEAD HERMETIC CERAMIC FLATPACK TYPE F

.015 (.38)

.050 (1.27)

asc

l
t

I .011 (~48)

------------

~

T
.-

.740 MAX. (18.80)

.000 MIN.

1. ______
L

...L

.045 MAX. (1.14)

.130(3.30)
.010 (2.21)

1

.380 (1.85)
.420 (10.87)

I'

-'-----I
•028(.88)
.045 (1.14)

~03O

(.78) MIN.-j
.250 (8.35)
.370(1.40)

--I

-l-

"

.003 (.08)
.008(.15)

FI=====L

i

,i

.180 (4.57) MIN•

"OTES

1. All dlmen.lon. ere In Inch•• end (mllllm.t....).
2. Tolerenc•• er. ± .003 (.078) un I••• oth.rwl. . .peclfl.d.

9-22

I

SEEQ Die Sales

Many of the SEEO Technology Products contained in this Data Book are available in
unencapsulated die form. Products sold in die form have been specifically screened to a
special die sales test flow and are ideally suited for hybrid and memory card applications.
After screening, all die are optically inspected per method 2010 condition B of MIL-STD
883C. Die are then placed in waffle packs and enclosed in anti-static vacuum sealed bags
prior to shipment
Foryour reference, the following pages detail product specific bond pad locations and die
dimensions for the SEEO products available in die form. Contact the factory or your local
SEEO representative for additional information.

seeQ T e c h n o l o g y , l n c o r p o l 8 t e d - - - - - - - - - - - - - - - - - - - - - - I
9-23

••

20

18.

19

•

17

.21
•

22

•

23

;.

•

24

W

•

1

•

2

•

3

•

4

..

16 •
15 •
14 •
13 •

52813

12 •
11 •
10 •
9.

5

6

7

••

••
I-

.161

9-24

8

.I

••
23

:.
0)

CD

•

22
24

•

25

•

27

•

21 • •

/

20 19 •

17.
18 •

16 •
15 •

28

.1

52833

.2
14.
•

3

•

4

•

5

.6

I•

13 •
12 •
11 •
10.
•

8.9•

7

.206

9-25

•I

• • • •
321

24

• •
23

N/C

2804A

8

9

10 11

12 13 14 15

16 17

• • ••••••••

1----------..

N/C.

18.

189 - - - - - - - - - -

9-26

I

• • •
3

ex)

• •

•

1

2

23

24

22

2816A/5516A

o

9
•

10

11

12

13

•

•

•

•

1----------.

14

15
••

16

17

19 •

•

•

18.

189 - - - - - - - - - - -

9-27

I

• • • •• • • •
5

4

3

27

1 28

25

N/e.

24

2817A/5517A

10

11

12

13

14

15

16

17

18

19

• • •••• • • • •

/---------.189 ---------1

seeQ

Technology. Incorporated - - - - - - - - - - - - - - - - - - - - - - - - - '

9-28

••

••
•

24

CO

20

19 •

.25

18.

•

27

17 •

•

28

16 •

•

1

15 •

~

2864

.2

CD

21

22

23

14.
13 •

•

3

•

4

•

5

12 •

6

11 •
10.

8

7

••

••
I.

9

.214

I

seeQ~~~~~~~~~~-----------~-----------~
9-29

•• • • • •• • • • •

.~.
7

432

N/C 28[1J

27

25

24

23

•
22

28C64

21

8

•
9

10

••
I·

•
• • • • • • • • •• ••I
11

12

13

14

14

15

16

17

18

19

20

.243

NOTE:
1. Should be double bonded.

seeQ

Technology. Incorporated - - - - - - - - - - - - - - - - - - - - - -.....

9-30

• • • •• • • • •
•
4

3

1 28[1)

2

27

25

24

23

22

28C65

8

•
9

21

10

••

I·

•
• • • • • • • • •• •. I
11

12

13

14

.243

NOTE:
1. Should be double bonded.

9-31

14

15

16

17 . 18

19

20

••

••
23

.....

N

21

22

•

24

•

25

19.
18 •

•

26

17 •

•

27

16.
15 •

•

28[1]

14 •
14.

28C256

13 •
12 •

•

1
.2

.4.3
•

11 •

5

10.

.6.7

I-

8.9 •
.353

NOTE·

1.

L

Sh~uld

20

be double bonded.

SeeQ Techno/ogy.lnco,po,.,.d
9-32

-I

•• • •••

• •••••
6

•

5

4

3

2

1

28

27

26

25

24

23

•
22

7

-

48128

W
W

21

8

•
••
9

I,

10

11

12

13

•••

14 15 16

17

18

19

• ••• ••

•
•
20

.182

seeQ Technology.lncorporated----------------------~
9-33

7~

.~9

•

.8

6

• 11
•

12

•

13

5•
4.
3•
2•
1.

•

:.

CO
W

28 •

14

.15

27C256

.16

27.

•

17

26 •

•

18

25 •

•

19

24 •

2223

20 21

••
I•
I

••
.164

•I

-seeQ Techno'ogy,'ncorporated----------------------.....J
9-34

u.s. Sales Offices
Corporste Sales
and Merlcetlng
Headquarters
SEEO Technology, Inc.
1849 Fortune Drive
San Jose, CA 95131
Tel: (408) 432·1550
Telex: 296609

NorlhwHt
Sales OffIce
SEEO Technology, Inc.
2105 South Bascom Ave.
Suite 185
Campbell, CA 95008
Tel: (408) 371·2100
FAX: (408) 37t·1392

South_t
Sales 0Iflce
SEEO Technology, Inc.
2310t Lake Center Dr.
Suite 120
EI Toro, CA 92630
Tel: (7t 4) 472·2015
FAX: (714) 472·0835

Mld-America
Sales OffIce
SEEO Technology, Inc.
300 Martingale Road
Suite 650
Schaumburg, IL 60t 73
Tel: (3t2) 5t7·15t5
FAX: (3t2) 517·1519

Northuat
Sales 0Iflce
SEEO Technology, Inc.
24 New England
Executive Park
Burlington, MA Ot803
Tel: (6t 7) 229-6350
FAX: (6t 7) 273-0322

fIouthMat

Sales 0Iflce
SEEO Technology Inc.
10480 UtIle Patuxent Pkwy.
Suite 500
Columbia MD 2t 044
(30t) 740·5696
(301) 740-8704

FAX: (408) 432·9549

Authorized North American Manufacturer's Representatives
Alabama
Rep., Inc.
Huntsville AL
(205) 881·9270
Arizona
Western High Tech
Scottsdale AZ
(602) 860·2702
CaIHonia
Bager Electronics
EncinitasCA
(619) 944-4188
First Rep
Chatsworth CA
(818) 718-6155
Taaroom, Inc.
Mountain View CA
(415) 960·1550
Connecticut
New England Tech Sales
North Haven CT
(203) 284·8300
Colorado
Sy/Comp
Englewood CO
(303) 773·9399

florida

IIInols
KMASales
Arlington Heights IL
(312) 398·5300

Iowa
Advanced
Technical Sales
Cedar Rapids IA
(319) 393·8280

Advanced Tech Sales
SI. LouisMO
(314) 878·2921
New Mexico
Neloo Electronlx
Alburquerque NM
(505) 293·1399

"'ryland
N_EraSales
Severna Park MD
(301) 554·4100

Georgia
Rep., Inc.
TuckerGA
(404) 938·4358
AtlantaGA

Indiana
Valetine & Assoc.
Greenwood IN
(317) 888·2260
South Bend IN
(219) 288·7070

IllaMuri

Ken...
Advanced
Technical Sales
Olathe KS
(913) 782·8702

Dyne·A·Mark Corp.
Casselberry FL
(407) 831·2822
Clearwater FL
(813) 441·4702
Fort Lauderdale FL
(305) 771·650t

New York
GenTech
Binghamton NY
(607) 648-8833
Liverpool NY
(315) 451·3480
Penfield NY
(716) 381·5159
J·Square
Marketing, Inc.
Jericho NY
(516) 935·3200

Maauchuse'"
N_England
Tech Sales
Burlington MA
(617) 272·0434
Michigan
A. Blumenberg
Assoc. Inc.
OakParkMI
(313) 968·3230
Mlnnaaota
Cahill, Schmitz, & Cahill
51. PaulMN
(612) 648·7217

NorlhCarollna
Rep., Inc.
ChariotteNC
(704) 563·5554
MorrisvilleNC
(919) 469-9997

Ohio
Omega Sales Inc.
Centerville OH
(513) 434-5507
Shaker Heights OH
(216) 751·9600
Oregon
Electronic
Component Sales
Tigard OR
(503) 602·6074
Penn~vanla

Delta Technical Sales
Willow Grove PA
(215) 657·7250
Tan_
Rep., Inc.
Jefferson City TN
(615) 475·9012
Taxu
Southern States
Marketing
AustinTX
(512) 835-5822
Richardson TX
(214) 238·7500
HoustonTX
(7t3) 960-9556

Utah
Sy/Comp
American ForkUT
(801) 756-5525
Wuhlngton
Electronic
Component Sales
Mercer Island WA
(206) 232·9301
Wlaconaln
KMASales
Milwaukee WI
(414) 259-1771
Canada
Electro Source, Inc.
Langley, B.C.
(604) 888·2412
Kanata Ontario
(613) 592·3214
Pointe Claire, Quebec
(514) 630·7488
Re.dale, Ontario
(416) 675·4490

Authorized North American Distributors
Alabama
O.C./ Southeast, Inc.
Huntsville AL
(205) 830·1881
Schweber Elect., Inc.
Huntsville AL
(205) 895·0480
Arizona
Anthem
TempeAZ
(602) 966·6600
Schweber Elect., Inc.
Phoenix AZ
(602) 431·0030
Time Electronics
TempeAZ
(602) 967·2000
CaIHomia
Anthem
Chatsworth CA
(818) 700·1000
E.lrvineCA
(714) 768-4444
RocklinCA
(916) 624-9744
San DiegoCA
(619) 453·4871
San JoseCA
(408) 828·1585
Bell Microproducts
Fountain Valley, CA
(714) 963·0667
Milpitas,CA
(408) 433-4623
Schweber Elect., Inc.
CaiabasasCA
(818) 880·9686
IrvineCA
(714) 863·0200
Sacramento CA
(916) 364·0222
San DiagoCA
(619) 450·0454
San Jose, CA
(408) 432·7151
Time Electronics
Agoura Hills CA
(818) 707·2890

Orlando FL
(305) 841·6565
Zeus Components
OviedoFL
(305) 365·3000

AnaheimCA
(714) 937·0911
ChatsworthCA
(818) 998·7200
San DiegoCA
(619) 586·1331
Sunnyvale CA
(408) 734-9888
Torrance CA
(213) 320·0880
Zeus Components
(818) 889·3838
San Jose CA
(408) 998·5121
Yorba Linda CA
(714) 921·9000

Georgia
O.C. I Southwest, Inc.
NorcrossGA
(404) 449·9508
Schweber Elect., Inc.
NorcrossGA
(404) 449·9170
Time Electronics
NorcrossGA
(404) 448-4448

Colorado
Anthem
Englewood CO
(303) 790-4500
Schweber Elect., Inc.
Englewood CO
(303) 799·0258
Time Electronics
Englewood CO
(303) 799-8851

Illinois
Anthem
Elk Grove Village IL
(312) 840·6066
Schweber Elect., Inc.
Elk Grove IL
(312) 364·3750
Time Electronics
Wood Dale IL
(312) 350·0610

Connecticut
Anthem
Meridian CT
(203) 237·2282
Schweber Elect., Inc.
DanburyCT
(203) 748·7080
Time Electronics
CheslreCT
(203) 271·3200

indiana
Schweber Elect., Inc.
Indianapolis IN
(317) 843·1050

florida
Schwaber Elect., Inc.
Aftamonte Springs FL
(305) 331·7555
Pompano Beach
(305) 977-7511
Time Electronics
Ft. Lauderdale FL
(305) 974-4800

Iowa
Schweber Elect., Inc.
Cedar Rapids, IA
(319) 373·1417

Time Electronics
ColumbiaMD
(301) 984·3090
Zues Components
ColumbiaMD
(301)997·1118

...uachu.....
Anthem
Wilmington MA
(617) 657·5170
Schweber Elect., Inc.
BedfordMA
(617) 275-5100
Time Electronics
PeabodyMA
(617) 532·6200
Zeus Components
Lexington MA
(617) 863·8800
Michigan
Schwaber Elect., Inc.
LivoniaMI
(313) 525·8100
Mlnneaote
Anthem
Eden Prarie MN
(612) 944·5454
Schweber Elect., Inc.
EdinaMN
(612) 941·5280
Time Electronics
EdinaMN
(612) 835·1250

MI_rI
Ken...
Schwebar Elect., Inc.
Overland Park KS
(913) 492·2921
"'ryland
Anthem
ColumblaMD
(301) 984·0400
Schweber Elect., Inc.
GalthersburgMD
(301) 840·5900

Schweber Elect., Inc.
EarthCItyMO
(314) 739·0526
Time Electronics
SI. LoulsMO
(314) 391-6444
New Hampshlrs
Schweber Elect., Inc.
Manchester NH
(603) 625·2250

9-35

NewJaraay
Anthem
FairfieldNJ
(201) 227·7960
Schwaber Elect., Inc.
FalrfieldNJ
(201) 227·7800
Time Electronics
Pinebrook NJ
(201) 882-4611
New York
Anthem
Hauppauge NY
(516) 273·1660
Schweber Elect., Inc.
Rochester NY
(716) 424·2222
Hauppauge NY
(516) 231·2500
TimeElecIronics
E. Syracuse NY
(315) 432·0355
Hauppauge NY
(516) 273·0100
Zeus Components
Port Chester NY
(914) 937·7400

NorlhCarollna
Quality Components
RalelghNC
(919) 876·7767
Schweber Elect., Inc.
RaleighNC
(919) 887·0000

Ohio
Schwaber Elect., Inc.
Beachwood OH
(216) 464-2970
DaytonOH
(513) 439·1800
Time Electronics
DubiinOH
(614) 761-1100
Zeus Components
DaytonOH
(513) 293-6162

Oklahoma
Quality Components
Tulsa OK
(918) 664-8812
Schwaber Elect., Inc.
Tulsa OK
(918) 622-8000
Oragon
Anthem
Beaverton OR
(503) 643·1114
Time Electronics
PortiandOR
(503) 684-3780
Penn~vanla

Anthem
HorshamPA
(215) 443·5150
Schwaber Elect., Inc.
HorshamPA
(215) 441·0600
Pittsburgh PA
(412) 963·6804
Time Electronics
King of Prussia PA
(215) 337·0900
Taxas
Anthem
Richardson, TX
(214) 238·7100
Quality Components
AddisonTX
(214) 733-4300
AustlnTX
(512) 835·0220
SugariandTX
(713) 240·2255
Schwaber Elect., Inc.
AustinTX
(512) 339-0088
DallasTX
(214) 661·5010
HoustonTX
(713) 784·3600

Time Electronics
AustlnTX
(512) 339·3051
CarrolitonTX
(214) 241·7441
HoustonTX
(713) 530·0800
Zeus COlnponents
Richardson TX
(214) 783·7010
Utah
Anthem
Salt Lake City UT
(801) 973·8555
Time Electronics
Salt Lake City UT
(801) 973-8181
Wuhlngton
Anthem
RedmondWA
(206) 881·0850
Time Electronics
RedmondWA
(206) 882·1600
Wlaconaln
Schweber Elect., Inc.
New Berlin WI
(414) 784·9020
Canada
Future Electronics
Calgery, Alberta
(403) 259-6408
Downsview, Ontario
(416)638-4771
Edmunton, Alberta
(403) 488·0974
Ottawa, Ontario
(613) 829-6313
Pointe Claire, Quebec
(514) 694·7710
Vancouver,
British Columbia
(604) 438·5545

International Sales Offices
Corporate International
Sales Office

Northern European
Sales Office

Central European
Sales Office

Southern European
Sales Office

SEEQ Technology, Inc.
1849 Fortune Drive
San Jose CA 95131
Tel: (408) 432-1550
TWX: 910-338-2313
Telex: 296609
FAX: (408) 432-9549

SEEQ International Ltd.
Dammas House
Dammas Lane
OldTown
Swindon SN1 3EF U.K.
Tel: 44 (0793) 694999
Telex: 444588
Fax: 447-93616201

SEEQ Central Europe
Lussweg 2
8110 Murnau
Federal Republic of Germany
Tel: 49 (08841) 5951
FAX: 49 (08841) 5955

SEEQ International Sari
4 Allee de Pomone, RN13
78100 Saint-Germaine-en-Laye
France
Tel: 33 (1) 30 61 21 23
Telex: 699912
Fax: 33 (1) 30 61 21 92

Authorized International Manufacturer's Representatives/Distributors
Australia
RAE Industrial
Electronics Ply, Ltd.
Austinner
Tel: (42) 2673722
Perth
Tel: (09) 470 2702
SI. Leonards
Tel: (02) 439 7599
Sydney
Tel: (02) 232 6933
Victoria
Tel: (03) 277 4033
Austria
Sieg-Electronic
Vienna
Tel: 43 (222) 975626
Belgium
Alcom Electronics B.V.B.A.
Platanenlaan 68
Wilrijk
Tel: 32 (3) 8283880
Brazil
Hitech
Sao Paulo
Tel: 55-11 (531-9355)
Denmark
Exatek A.S.
Copenhagen
Tel:451191022
Farsoe
Tel: 45 8 63 3311
Finland
ITIDisti
Helsinki
Tel: 358-90739100
Faderal Republic
of Germany
Astek Electronik
Kaltenkirchen
Tel: 49(4191)8711
Dacom Electronik
Stuttgart
Tel: 49(711)741021
Vertriebs GmbH
Solingen
Tel: 49(212)59 30 11
Munchen
Tel: 49(89)60 98 031

India
SRI RAM Assoc.
Bangalore
Tel: 602-140

Dacom Electronik
Buxhiem
Tel: 49(8458)4003
Karlsruhe
Tel: 49(721)47193
Metronik GmbH
Munich
Tel: 49(89)611 080
Hamburg
Tel: 49(40)522 80 91
Stuttgart
Tel: 49(711 )764033
Metronik
Dortmund
Tel: 49(231)432 037
Nurnberg
Tel: 49(911 )59 00 61
Mannheim
Tel: 49(6203)4701

Ireland
Allied Semiconductors
International Ltd.
Shannon
Tel: 353 6161777
Isreal
Vectronics Ltd.
Herzlia
Tel: (0/52) 556070 or 71
Italy
Moxel
Milano
Tel: 39 (2) 61 290521

France
Radio Television
Francaise (RTF)
Gentilly
Tel: 33(1) 46 6411 01
RTF Sud Quest
Escalquens
Tel: 33(61) 815157
RTF Aquitaine
Bordeaux
Tel: 33(56) 52 99 59
RTF Rhone-Aples
Meylan
Tel: 33(76) 90 11 88
RTF Quest
Cesson Sevigne
Tel: 33(99) 83 84 85
RTF Rhone-Auvergne
Venissieux
Tel: 33(78) 00 07 26
RTF Provence
Marseille
Tel: 33(91) 06 0218
Reptronic
Orsay
Tel: 33(1) 69288700

Japan
Japan Macnics
Corporation (JMC)
Kawasaki-City
Tel: (0/44) 711 0022
Osaka City
Tel: (0/6) 325 0880
Korea
Hanaro
Seoul
Tel: (02) 738-7141
The Netherlands
Techmation
Electronics Manudax
Heeswijk-Dinther
Tel: 31 (4189) 8895
New Zealand
VSI Electronics (N.Z.) Ltd.
Epsom Auckland
Tel: 600 760
Norway
Exatec. A.S.
Skaarer
Tel: 47 2 972 950

Hong Kong
Electrocon Products Ltd.
Kowloon
Tel: 3-687214-6

Peoples Republic of China
AET (Asia) LTD.
Bejing
Tel: 81-5728
Hong Kong
Tel: 0-4161384
Portugal
Teleprinta Lda
Lisboa
Tel: 351 (1) 54 8423
351 (1) 54 89 37
South Africa
Advanced Semiconductor
Devices (PYT) Ltd.
Sandton
Tel: (011) 802-5250
Singapore/Malaysia
Desner Electronics
(Far East) PTE Ltd.
Singapore
Tel: 3373188
Spain
Semiconductores
Barcelona
Tel: 34 (3) 217 23 40
Semiconductores S. A.
Madrid
Tel: 34 (1) 7422313
Sweden
Svensk Teleindustri AB
Vallingby
Tel: (46) 8761 7300
Switzerland
Anatec AG Electronische
Bauteile
Zug
Tel: 41 (42)412441
Taiwan
Bright Up Industries Co., Ltd.
Taipei
Tel: (0/2) 773 2194
United Kingdom
Amega Electronics Ltd.
Hampshire, U.K.
Tel: 0256-843166
Pronto Electronic Systems Ltd.
Gants Hill/Essex
Tel: (0/1) 554 6222

9-36



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