1990_Fujitsu_Dynamic_RAM_Products 1990 Fujitsu Dynamic RAM Products

User Manual: 1990_Fujitsu_Dynamic_RAM_Products
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NMOS DRAMs
CMOS DRAMs
Application-Specific RAMs
MOS RAM Modules
CMOS DRAM Modules
Quality and Reliability
Ordering Information
Sales Information
Appendix - Design Information

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FUJITSU

Dynamic RAM Products
1990

Data
Book

Fujitsu Limited
Tokyo, Japan
Fujitsu Microelectronics, Inc.
San Jose, California, U.S.A.
Fujitsu Mikroelectronik GmbH
Frankfurt, F.R. Germany
Fujitsu Microelectronics Asia PTE Limited
Singapore

Copyright© 1990 Fujitsu Microelectronics, Inc., San Jose, California
All Rights Reserved.
Circuit diagrams using Fujitsu products are included to illustrate typical semiconductor applications. Information sufficient for
construction purposes may not be shown.
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu
Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any license under the copyrights, patent rights or trademarks
claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
No part of this publication may be coPied or reproduced in any form or by any means, or transferred to any third party without prior
written consent of Fujitsu Microelectronics, Inc.
This document is published by the Publications Department, Fujitsu Microelectronics, Inc.,
3545 North First Street, San Jose, California, U.S.A. 95134--1804; U.S.A.
Printed in the U.S.A.
Edition 1.0

II

Contents and Alphanumeric Product List
DRAM PRODUCTS
Introduction -

DRAM Products ..........................................

Section 1 - NMOS DRAMs -

At a Glance . ................................

At a Glance . ................................

MB81 C258-1 0/-12/-15
MB81 C466-1 0/-12/-15
MB81 C1 000-70/-80/-1 0/-12
MB81 C1 000A-60/-80/-10
MB81 C1 001-70/-80/-1 0/-12
MB81C1001A-60/-80/-10
MB81 C1 002-70/-80/-1 0/-12
MB81 C1 002A-60/-80/-1 0
MB81 C4256-70/-80/-1 0/-12
MB81C4256A-60/-80/-10
MB81 C4257-85/-1 0/-12
MB81 C4258-70/-80/-1 0/-12
MB81 C4258A-60/-80/-1 0
MB8141 00-80/-10/-12
MB814400-80/-10/-12

MB81461-12/-15
MB81461B-12/-15
MB81 C4251-1 0/-12/-15
MB81 C4253-10/-12/-15
MB81C1501

Section 4 - MOS RAM Modules -

NMOS
NMOS
CMOS
CMOS
CMOS

At a Glance .....................

3-1

65536 x 4 bits Dual-Port DRAM ............. 3-3
65536 x 4 bits Dual-Port DRAM ............ 3-35
262144 x 4 bits Dual-Port DRAM ........... 3-67
262144 x 4 bits Dual-Port DRAM ........... 3-69
2293760 x 4 bits Three-Port DRAM ......... 3-71

At a Glance ............................

4-1

MOS 262144 x 9 bits DRAM Module ............... 4-3

Section 5 - CMOS DRAM Modules MB85230-10/-12
MB85231-10/-12
MB85235-10/-12
MB85237-10/-12
MB85240-10/-12
MB85254-80/-10/-12
MB85260-10/-12
MB85265-10/-12

2-1

CMOS 262144 x 1 bit Static Column Mode DRAM ..... 2-3
CMOS 65536 x 4 bits Static Column Mode DRAM .... 2-25
CMOS 1048576 x 1 bit Fast Page Mode DRAM ...... 2-41
CMOS 1048576 x 1 bit Fast Page Mode DRAM ...... 2-61
CMOS 1048576 x 1 bit Nibble Mode DRAM ......... 2-63
CMOS 1048576 x 1 bit Nibble Mode DRAM ......... 2-83
CMOS 1048576 x 1 bit Static Column Mode DRAM ... 2-85
CMOS 1048576 x 1 bit Static Column Mode DRAM .. 2-109
CMOS 262144 x 4 bits Fast Page Mode DRAM ..... 2-111
CMOS 262144 x 4 bits Fast Page Mode DRAM ..... 2-135
CMOS 262144 x 4 bits Nibble Mode DRAM ........ 2-137
CMOS 262144 x 4 bits Static Column Mode DRAM .. 2-161
CMOS 262144 x 4 bits Static Column Mode DRAM .. 2-183
CMOS 4194304 x 1 bit Fast Page Mode DRAM .... 2-187
CMOS 1048576 x 4 bits Fast Page Mode DRAM ... 2-207

Section 3 - MOS Application-Specific RAMs -

MB85227-10/-12/-15

1-1

262144 x 1 bit DRAM ........................... 1-3
262144 x 1 bit DRAM .......................... 1-25
65536 x 4 bits DRAM .......................... 1-49

MB81256-10/-12/-15
MB81257-10/-12/-15
MB81464-10/-12/-15

Section 2 - CMOS DRAMs -

vii

At a Glance ...............................

CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS
CMOS

5-1

1048576 x 8 bits DRAM Module ............. 5-3
1048576 x 8 bits DRAM Module ............ 5-21
1048576 x 9 bits DRAM Module ............ 5-39
1048576 x 9 bits DRAM Module ............ 5-55
262144 x 9 bits DRAM Module ............. 5-73
524288 x 40 bits DRAM Module ............ 5-89
1048576 x 8 bits DRAM Module ............ 5-93
1048576 x 9 bits DRAM Module ........... 5-107

iii

Contents and Alphanumeric Product List (Continued)
DRAM PRODUCTS
Section 6 - Quality and Reliability -

At a Glance . .........................

6-1

Quality Control at Fujitsu ................................................... 6-3
Quality Control Processes at Fujitsu .......................................... 6-4

At a Glance ...........................

7-1

IC Product Marking .......................................................
IC Ordering Code (Part Number) ............................................
Ie Package Codes .......................................................
IC Module Ordering Code (Part Number) ......................................
IC Module Package Codes .................................................

7-3
7-3
7-4
7-4
7-4

At a Glance . .............................

8-1

Section 7 - Ordering Information -

Section 8 - Sales Information -

Introduction to Fujitsu ..................................................... 8-3
Integrated CircuitS Corporate Headquarters - Wor1dwide .......................... 8-7
FMI Sales Offices for North and South America ................................. 8--8
FMI Representatives - USA ................................................ 8-9
FMI Representatives - Canada ............................................. 8-11
FMI Representatives - Mexico ............................................. 8-11
FMI Representatives - Puerto Rico ......................................... 8-11
FMI Distributors - USA ................................................... 8-12
FMI Distributors - Canada ................................................ 8-16
FMG Sales Offices for Europe ............................................. 8-17
FMG Distributors- Europe ............................................... 8-18
FMA Sales Offices for Asia and Australia ..................................... 8-20
FMA Representatives - Asia ............................................... 8-20
FMA Distributors - Asia and Austraila ....................................... 8-21

Section 9 - Appendix - Design Information . ............................. 9-1
Appendix. Application Note: Various Features of Fujitsu DRAMs . ................... 9-3

Iv

Contents and Alphanumeric Product List (Continued)
DRAM PRODUCTS

Alphanumeric List of Fujitsu Part Numbers
MBB1256-101-121-15 ......... 1-3
MBB1257-101-12/-15 ........ 1-25
MB81461-12/-15 ........... 3-33
MBB1461 B-12/-15 .......... 3-35
MBB1464-101-121-15 ........ 1-49
MBB1C25B-101-12/-15 ........ 2-3
MBB1C466-101-12/-15 ....... 2-25
MBB1C1000-701-BOI-101-12 .. 2-41
MBB1C1000A-601-BOI-10 .... 2-61
MBB1C1001-701-BOI-101-12 .. 2-63
MB81C1001A-601-BO/-10 .... 2-63
MBB1C1002-701-BOI-101-12 .. 2-85
MBB1C1002A-601-BO/-10 ... 2-109
MBB1C1501 .............. 3-71
MB81C4251-101-12/-15 ...... 3-69
MB81 C4253-1 01-12/-15 ...... 3-71

MBB1C4256-701-BOI-101-12 " 2-111
MB81C4256A-601-BOI-10 .... 2-135
MB81C4257-B5/-10/-12 ..... 2-137
MBB1C425B-701-BOI-101-12 " 2-161
MBB1C4258A-601-BOI-10 .... 2-1B3
MBB14100-BO/-101-12 ....... 2-1B7
MBB14400-BO/-101-12 ....... 2-207
MBB5227-10/-12/-15 . ......... 4-3
MBB5230-10/-12 ............. 5-3
MBB523HOI-12 ............ 5-21
MBB5235-10/-12 ............ 5-39
MBB5237-101-12 ............ 5-55
MBB5240-10/-12 ............ 5-73
MBB5254-BO/-101-12 ......... 5-93
MBB5260-101-12 ........... 5-89
MBB5265-101-12 ........... 5--107

v

vi

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Introduction

Page

ix

Fujitsu's Dynamic RAM

vii

Introduction

viii

Static RAM Data Book

Fujitsu's Dynamic RAM Products
Introduction
Fujitsu manufactures a wide range of integrated circuits that
includes linear products, microprocessors,
telecommunications circuits, ASICs, high-speed ECl logic,
power components (consisting of both discrete transistors
and transistor arrays), and both static and dynamic RAMs.
The Dynamic RAM product line offers devices for use in a
wide range of applications. These memories are
manufactured to meet the high standard of quality and
reliability that is found in all Fujitsu products.
This data book includes product information on the following
DRAM products:
NMOS and CMOS DRAMs
Fujitsu manufactures a complete family of leading technology
dynamic random access memories for the data processing,
telecom, and industrial markets. This family consists of the
highest density devices currently available with a broad
selection of organizations, access modes, and packages.
Application-Specific DRAMs
Fujitsu offers a family of dual-port dynamic random access
memories tailored for video imaging and graphics
applications. These devices adhere to JEDEC standards
where applicable and are available in the popular packages.
MOS and CMOS DRAM Modules
Fujitsu manufactures a complete family of reliable MOS and
CMOS dynamic RAM memory modules for those
applications requiring high density and large memory storage
capability. Fujitsu's family of memory modules are
pin-compatible with JEDEC standards.

ix

Introduction

J(

Dynamic RAM Data Book

Section 1

NMOS DRAMs -

..

At a Glance
Maximum
ACce88

Package
Options

Page

Device

Time (ns)

Capacity

1-3

MB81256-10
-12

100
120

262144 bits
(262144w x lb)

-15

150

16-pin
16-pin
16-pin
18-pad

Plastic
Ceramic
Plastic
Ceramic

DIP, ZIP
DIP
LCC
LCC

1-25

MB81257-10
-12
-15

100
120
150

262144 bits
(262144w x lb)

16-pin
16-pin
18-pin
18-pad

Plastic
Ceramic
Plastic
Ceramic

DIP,ZIP
DIP
LCC
LCC

1-49

MB81464-10
-12
-15

100
120
150

262144 bits
(65536w x 4b)

18-pin
la-pin
20-pin

Plastic
Ceramic
Plastic

DIP, LCC
DIP
ZIP

1-1

NMOS DRAMs

1-2

Dynamic RAM Data Book

1111111111111111111111111111111111111111111111111111111111

MB 81256-10
MB 81256-12
MB 81256-15

FUJITSU
11111111111111111111111111111111111

I

I
December 1985
Edition 4.1

262,144-BIT DYNAMIC RANDOM ACCESS MEMORY

..

The Fujitsu MB 81256 is a fully decoded, dynamic NMOS random access
memory organized as 262,144 one-bit words. The design is optimized for highspeed, high performance applications such as mainframe memory, buffer
memory, peripheral storage and environments where low power dissipation and
compact layout is required.
Multiplexed row and column address inputs permits the MB 81256 to be
housed in a standard 16 pin DIP/ZIP and 18 pad LCC. Pin·out conform to the
JEDEC approved pin out. Additionally, the MB 81256 offers new functional
enhancements that make it more versatile than previous dynamic RAMs.
"CAS-before·RAS" refresh provides an on-chip refresh capability. The
MB 81256 also features "page mode" which allows high speed random access
to up to 512 bits within a same row.
The MB 81256 is fabricated using silicon gate NMOS and Fujitsu's advanced
Triple-Layer Polysilicon process. This process, coupled with single-transistor
memory storage cells, permits maximum circuit density and minimal chip size.
Dynamic circuitry is employed in the design, including the sense amplifiers.

PLASTIC PACKAGE
DIP-16P-M03

PLASTIC PACKAGE

LCC-18P·M04

Clock timing requirements are noncritical, and power supply torelance is very
wide. All inputs are TTL compatible.
•
•
•

•

•

•
•

•

262,144 x 1 RAM, 16 pin DIP and
ZIP/18 pad LCC
Silicon-gate, Triple Poly NMOS,
single transistor cell
Row access time,
100 ns max. (MB 81256-10)
120 ns max. (MB 81256-12)
150 ns max. (MB 81256-15)
Cycle time,
200,nsmin. (MB81256·10)
220 ns min. (MB B1256-12)
260 ns min, (MB 81256·15)
Page cycle time,
100 ns max. (MB 81256-10)
120 ns max. (MB 81256-12)
145 ns max. (MB 81256-15)
Single +5V Supply, ±10% tolerance
Low power,
385 mW max. (MB 81256-10)
358 mW max. (MB 81256-12)
314 mW max. (MB 81256-15)
25 mW max. (standby)
256 refresh cycles every 4ms

•
•
•
•
•
•
•

CAS-before-RAS, RAS-only,
Hidden refresh capability
High speed Read·while-Write cycle
tAR, tWCR, tOHR, tRWO, are
eliminated
Output unlatched at cycle end
allows two-dimensional chip select
Common I/O capability using
Early Write operation
On-chip latches for Addresses and
Data·in
Standard 16·pin Ceramic (Seam Weld)
DIP (Suffix: -C)
Standard 16'pin Ceramic (Cerdip)
DIP (Suffix: -Z)
Standard 16-pin Plastic
DIP (Suffix: ·P)
Standard 18-pad Ceramic
LCC (Suffix: ·TV)
Standard 18'pin plastic
LCC (Suffix: -PV)
Standard 16·pin Plastic
ZIP (Suffix, ·PSZ)

Voltage on any pin relative to Vss

Voltage on Vee supply relative to Vss
Ceramic
I Plastic
Power dissipation

Storage temperature

Short circuit output current

Value
-1 to +7

Vce

-1 to +7
55 to +150
-55 to +125
1.0
50

Po

-

AS

DINt Vss CAS

~~tf!3Ll}J

RAS

Symbol
V IN , VO UT
TSTG

PIN ASSIGNMENT

WE

ABSOLUTE' MAXIMUM RATINGS (See NOTE)
Rating

PLASTIC PACKAGE
ZIP·16P·MOl
DIP-16C-A03: See Page 17
DIP-16C-A04: See Page 18
DIP-16C-C04: See Page 19
LCC-18C-F04: See Page 24

5:
4i
~~

Unit

NC

V
V

Ao

~;

A2

~]

'c
W
mA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

L'_6 DOUT
~1? A6
TOP VIEW

L'_4

NC

:'3 A3

[(2 A4
A, \ A7 A5
Vce

Pin assignment for ZIP; See Page 21
This device contains circuitry to protect the
inputs against damage due to high static volt·
ages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi·
mum rated voltages to this high impedance
circuit.

1-3

MB 81256-10
MB 81256-12
MB 81256-15

1111111111111111111111111111111111111111111111111

FUJITSU
111I1II111111111111111111111111111111111111111111

Fig. 1 - MB 81256 BLOCK DIAGRAM

III

AS

CLOCK GEN.
NO.1

AS

REFRESH
CONTROL
CLOCK

r--

-

AO

lL~
r--V
-

,
,

-

-

INTERNAL
ADDRESS
COUNTER

CLOCK GEN
NO.2

I

I
-'--I---

I_
",..J_

w

~

~

=r

~

f-u:;:
-f-O

101

"'

I-U~

-

I

--U

Typ

Max

Unit

C 'N1

7

pF

C 'N2

10

pF

COUT

7

pF

MB 81256-10 illllllllllllllllllllllllllllllllllllllllllllllllill
MB 81256-12 FUJITSU
MB 81256-15 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII!

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Parameter

Symbol

Min

Typ

Max

Unit

Vcc

4.5

5.0

5.5

V

Vss

0

0

0

V

Input High Voltage, all inputs

V ,H

2.4

6.5

V

Input Low Voltage, all inputs

V ,L

-2.0

0.8

V

Supply Voltage

..

Operating
Temperature

DoC to +70°C

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Value
Symbol

Parameter

Unit
Min

MB 81256·12

~

V IH; t RC

~

MB 81256·12
Min.)

PAGE MODE CURRENT*
Average Power Supply Current
(RAS eV,L, CAS cycling; t pc ~ Min.)

Icc2

4.5

Icc3

55

REFRESH CURRENT 2*
Average Power Supply Current
(CAS.before.FlAS; t RC ~ Min.)

50

MB 81256·10

35
30

Icc4

MB 81256·15

25

MB 81256·10

65

MB 81256·12

mA

60

MB 81256·15

MB 81256·12

mA

57

MB 81256·10

REFRESH CURRENT l '
Average Power Supply Current
(RAS cycling, CAS

65

Icc1

MB 81256·15

STANDBY CURRENT
Standby Power Supply Current
(RAS, CAS~V'H)

Max
70

MB 81256·10

OPERATING CURRENT'
Average Power Supply Current
(RAS, CAS cycling; tAC ~ Min.)

Typ

60

Icc5

MB 81256·15

mA

mA

mA

55

INPUT LEAKAGE CURRENT any input (V ,N ~ OV to
5.5V, Vcc ~ 5.5V, Vss ~ OV, all other pins not under test = OV)

I'ILI

-10

10

/lA

OUTPUT LEAKAGE CURRENT (Data is disabled,
V OUT = OV to 5.5V)

IOILi

-10

10

/lA

OUTPUT LEVEL Output Low Voltage (I OL = 4.2 mAl

VOL

0.4

V

OUTPUT LEVEL Output high Voltage (l oH = -5.0 mAl

V OH

NOTE

2.4

V

Icc is depended on output loading and cycle rates. Specified values are obtained with the output open.

1-5

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB 81256-10
MB 81256-12
MB 81256-15

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

Parameter

I&DiI

MB 81256-10

MB 81256-12

MB 81256-15

Min

Min

Min

Symbol

Unit
Max

Max

Time between Refresh

tREF

Random Read/Write Cycle Time

t RC

200

220

260

Read-Write Cycle Time

t RWC

200

220

260

Access Time from RAS

Elfil

Access Time from CAS

lUI

4

4

Max
4

ms
ns
ns

t RAC

100

120

150

ns

t CAC

50

60

75

ns

Output Buffer Turn off Delay

tOFF

0

25

0

25

0

30

ns

Transition Time

tT

3

50

3

50

3

50

ns

RAS Precharge Time

tRP

85

RAS Pulse Width

tRAS

105

RAS Hold Time

t RSH

55

CAS Pulse Width

tCAS

CAS Hold Time
RAS to CAS Delay Time

I IiI

55

tCSH

105

tRCO

20

90
100000

120

100
100000

60
100000

60

22

ns
100000

75
100000

120
50

150

75

ns
100000

25

ns
ns

150
60

ns

75

ns

CAS to RAS Set Up Time

tCRS

10

10

10

ns

Row Address Set Up Time

tASR

0

0

0

ns

Row Address Hold Time

tRAH

10

12

15

ns

Column Address Set Up Time

tASC

0

0

0

ns

Column Address Hold Time

tCAH

15

20

25

ns

Read Command Set Up Time

tRCS

0

0

0

ns

Read Command Hold Time Referenced
to CAS

III

tRCH

0

0

0

ns

Read Command Hold Time Referenced
to RAS

III

tRRH

20

20

20

ns

twcs

0

0

0

ns

twp

15

20

25

ns

Write Command Set Up Time

IIIJ

Write Command Pulse Width
Write Command Hold Time

t WCH

15

20

25

ns

Write Command to RAS Lead Time

t RWL

35

40

45

ns

tCWL

35

40

45

ns

tos

0

0

0

ns

Write Command to CAS Lead Time
Data In Set Up Time

tOH

15

20

25

ns

t cwo

15

20

25

ns

Refresh Set Up Time for CAS Referenced
to RAS (CAS-before-RAS cycle)

t FCS

20

20

20

ns

Refresh Hold Time for CAS Referenced to RAS
(CAS-before-RAS cycle)

t FCH

20

25

30

ns

Data In Hold Time
CAS to WE Delay

1-6

l.r.II.....-

IIIJ

MB 81256-10 IIIIIIIIIIII!IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
MB 81256-12 FUJITSU
MB 81256-15 illlllllllllllllllllllllllllllllllllllllllllllllllli

AC CHARACTERISTICS

-

(Recommended operating conditions unless otherwise noted.)

Parameter

Symbol

MB 81256·10

MB 81256·12

MB 81256·15

Min

Min

Min

Max

Max

CAS Precharge Time (CAS·before·RAS cycle I

t CPR

20

25

30

ns

RAS Precharge to CAS Active Time
(Refresh cycles I

tRPC

20

20

20

ns

Page Mode Read/Write Cycle Time

tpc

100

120

145

ns

Page Mode Read·Write Cycle Time

tpRWC

100

120

145

ns

Page Mode CAS Precharge Time

tcp

40

50

60

ns

Refresh Counter Test Cycle Time
Refresh Counter Test RAS Pulse Width
Refresh Counter Test CAS Precharge Time

m
m
m

tRTC

330

t TRAS

230

t CPT

50

265

ns

430

375
10000

10000

60

320

..

Unit

Max

10000

70

ns
ns

Notes:

a

EI

I

An initial pause of 200 /lS is required after power·up.
And then several cycle (to which any 8 cycle to per.
form refresh are adequate) are required before proper
device operation is achieved ..
If internal refresh counter is to be effective, a mini·
mum of 8 CAS before RAS refresh cycles are required.
AC characteristics assume tT

= 5 ns.

V IH (min) and VIL (maxi are refrence levels for mea·
suring timing of input signals. Also, transition times
are measured between V IH (min) and VIL (max.).

I

Assumes that tRCD ~ tRCD (max.) If tRCD is greater
than the maximum recommended value shown in this
table, t AAC will increase by the amount that tRCD
exceeds the value shown.

IiJ

Assumes that tACO ~ tRCD (max.l.

mMeasured
with a load equivalent to 2 TTL loads and
100 pF.

I

&I

Operation within the tAco (maxi limit insures that
t RAC (max) can be met. tACO (max) is specified as a
reference point only; if tRCD is greater than the
specified tRcD (max) limit, then access time is can·
trolled exclusively by t CAC '
tRCD (min)
(min).

= tAAH

(min) + 2tT (t T

= 5ns) + tAsc

II Either tAAH or tACH must be satisfied for a read cycle.
lID twcs and tCWD are not restrictive operating para·
meters. They are included in the data sheet as elec·
trical characteristics only. If twcs ~ twcs (min),
the cycle is an early write cycle and the data out pin
will remain open circuit (high impedance) throughout
entire cycle.
If tCWD ~ tCWD (min) the cycle is a read·write cycle
and data out will contain data read from the selected
cell. If neither of the above sets of conditions is satis·
fied the condition of the data out is indeterminate.

II Test mode cycle only.

1-7

MB 81256-10
MB 81256-12
1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImllll~~111 MB 81256-15
1IIIIIIIIIIIIIIIIIIIIIImlllllllllllllllllllllllili

FUJITSU

Read Cycle
~---------------tRC--------------~----"
1--------tRAS------~-I

RAS

VIHV 1L tCSH

,_ _J-------, RS H I - - - - - i - '
CAS

ADDRESSES

WE

VIH- ~~_7~r_-----,t-,
VIL- "

~------'CAS

VIHVIL -

VIHVIL -

!----tcAc------,

11-----------'
VOHDOUT

~~-------------

VOL

RA c----------i

---------HIGH-Z--------

3

«

2

'"Clz
f-

Ul

30r--+--1---r--+--1-~

u

~

c.:J

U

0-

o

70

w

ex:
ex:
:J
u

-"'

u

i=
~

fZ

so

0

:J

~

:;c
S

0-

w

~

o.S
-20
0
20
40
60
80 100
T A • AMBIENT TEMPERATURE (oC)

SO - T =25°C

30

-"'

/'

4.0
S.O
6.0
Vee SUPPLY VOLTAGE (V)

60

z
i=

U

0.9

«

:J

«

~

./

a:

!!-

w
0

1.0

«

V

z

«

c.:J

~
:::i

/'

o

U 0.8

ex:
ex:
u

1. 1

Cl

z

fZ
w

1.2

(/)

Cl

:;c
S

Ve~=s.oJ

w

:;;

T)2S0C

Ul
W

u

Fig. 4 - NORMALIZED ACCESS TIME
vs AMBIENT TEMPERAUTRE

'"

U

1

U

20

-~20~~0--~20~~4~0--6~0~~SO~~100
T A • AMBIENT TEMPERATURE (oC)

4.0
s.o
6.0
Vee. SUPPLY VOLTAGE (V)

1-15

MB 81256-10
MB 81256-12
MB 81256-15

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

Fig. 10 - REFRESH CURRENT 1
vs CYCLE RATE

Fig. 9 - STANDBY CURRENT
vs AMBIENT TEMPERATURE

<
5
....

6

2

w

a:
a:

4

:::l

u

>OJ

3

o-

2

50

w

a:
a:

40

u

30

2

(J)

W

a:
u..

'"

u

~

i

T)250C
70

W

60

:::l
U

:x:

50
40

a:

'"

u

V

".,

5
....

VCl=5.5J
50 -TA=25°C

a:
a:

40

w

Cl

V

<:J

.

Fig. 13 - PAGE MODE CURRENT
vs SUPPL Y VOLTAGE
60

40

:::l

u

w

:;;
w

<:J

30
20

..:

..

0.

u

~

1-16

V

V

<

--

~

I--

10

0

2
4
6
8
10
l/tpc, CYCLE RATE (MHz)

Fig. 14 - REFRESH CURRENT 2
vs CYCLE RATE

5
....

tpJl00nl
50 I-- TA =2SoC

w

Cl
Cl

10

u

~

4.0
5.0
6.0
Vcc, SUPPLY VOLTAGE (V)

a:
a:

V
,/

20

..:

30

.....

30

0.

20

5
....2

.'- -

0

:;;
w

~

<

60

u

!J)

a:
w

4

:::l

w

u.

10

Fig. 12 - PAGE MODE CURRENT
vsCYCLE RATE

2
w

2

",V

l/tRC, CYCLE RATE (MHz)

<

I

I-- tRc=200ns

V

0

Fig, 11 - REFRESH CURRENT 1
vs SUPPL Y VOLTAGE
80

/~

~

-20
0
20
40
60
80
100
TA, AMBIENT TEMPERATURE (oC)

a:
a:

20

a:

N

U

V

I

w

5
....

_vcl=5;5J
T A =25 C

:::J

r-- r--

!J)

<

60

5
....
2

Cl

......:

<

VCl=5.5J

60

N

50

2
w

a:
a:

40

u

30

_Vcb=5;sJ
TA =25 c

/

:::J

:x:

!J)

w

a:
u..

20

w

a:

.nu

. .V

/

'/

V

10

~

0

4.0
5.0
6.0
Vcc, SUPPLY VOLTAGE (V)

0

1

2

3

4

5

l/tRC, CYCLE RATE (MHz)

..

-

MB 81256-10
MB 81256-12
MB 81256-15

Fig. 15 - REFRESH CURRENT 2
vs SUPPL Y VOLTAGE
";(
.§
N

f-

80

tr:
tr:

:J
0
I

~-

-0:2:

0.

/

1.0

O~

z

30

-0:
I

20
~o

5~

6~

>

4~

o

3.0

Ve~=5.0J

I~

~~

V,HIMin.)

W-o:

~~

00

-:J

V'HI~in.)

-0:2:

en w 2.0

0.

J

T A 2S'e

0
z-

o

V'LIMax.)

6~

Fig. 18 - RAS, CAS AND WE INPUT
VOLTAGE vs SUPPLY VOLTAGE

Fig. 17 - ADDRESS AND DATA INPUT
VOLTAGE vs AMBIENT TEMPERATURE
3.0

5~

Vee, SUPPLY VOLTAGE IV)

Vee. SUPPLY VOLTAGE IV)

-0:>
jf-

--

:::-~IMax.)

-0:>

~

-0:
f-0:

FUJITSU
1111111111111111111111111111111111111111111111111111

Fig, 16 - ADDRESS AND DATA INPUT
VOLTAGE v.SUPPLY VOLTAGE
-0:

TJ2S0C

1111111111111111111111111111111111111111111111111111

l~ 1.0

1.0

Oz
z-

OZ

z-

-0:

-0:

I

I

->

>

o

-20
0
20
40
60
80
100
T A , AMB,ENT TEMPERATURE 1°C)

4.0
5.0
6.0
Vee, SUPPLY VOLTAGE IV)

Fig. 19 - RAS, CAS AND WE INPUT
VOLTAGE vs AMBIENT TEMPERATURE
3.0

Fig. 20 - ACCESS TIME vs LOAD
CAPACITANCE

Vee~S.OV
oS
V'H Min.)

W

:;:

f:
- -;(
..J E
0.-

15

~ ~

10

u~
2:;:,

5

"'w
u

o

RAS=CAS=VSS

o.w

0."

~~ ~
u..J

»uO

j,

V

!;(>
0::-

RAS=CASJ cC JV ,H -

I

I

'\

f0-

1
2
3
4
5
VOH. OUTPUT VOLTAGE Iv)

:[;fl I I I
o

1

19

-2

",0
::> >

-3

~~
"'..J

r\\

Fig. 24 - SUBSTRATE VOLTAGE
DURING POWER UP

w

U)

50,us/Division

1-18

>->

...J-

I- w

/

1,\ r\

o

t-TA =25°C

I I

'"

""CC=5.5V

JCC74.5V

1
2
4
5
VOL. OUTPUT VOLTAGE IV)

>->
..J-

!"

-

\

TA=25°C

f\.

f'..-

:%'
50J,ls/Division

I

MB 81256-10
MB 81256-12
MB 81256-15

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII!IIIIIIIIIII

FUJITSU
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII!IIIII

PACKAGE DIMENSIONS
Standard 16-pin Ceramic DIP (Suffix: -C)

DIP-16C-A03

16-DEAD CERAMIC (METAL SEAL) DUAL IN-LINE PACKAGE
(CASE No_: DIP-16C-A03)

R.05011.271
REF

[[

INDEX AREA

I.

I

]]
.760119.301
.800120.321

.28717.291
.29917.591

.1

~

I

.29017.371
.31017.871

Lll
.00810.201
.01210.301

Dimensions in
inches (millimeters)

1-19

MB 81256-10
MB 81256-12
illllllllllllllllllllllllllllllllllllllllllllllllill MB 81256-15
1111111111111111111111111111111111111111111111111111

FUJITSU

PACKAGE DIMENSIONS
Standard 16-pin Ceramic DIP (Suffix: -C)

DIP-16C-A04

16-LEAD SEAM WELD DIP PACKAGE
(CASE No.: DIP-16C-A04)

__ ,::::>1

""\~~"'''~ r ~{

J~ J

1,

<=~l: : .~~~:~~~~~~~~J~:::::.uJ·701
1=
= = I

INDEX AREA"'II

.760119.301
.800120.321

0 0_90

11

.290(7.371

....,=:!=\==.:]871

.01210.301
.04311.09ITYP

~~x=.=05=01=1.=27=IM=A=X===============t4

.090(2.291
.110(2.791
Dimensions in
Inches and (millimeters)

1-20

MB 81256-10
MB 81256-12 FUJITSU
MB 81256-15

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
Standard 16-pin Ceramic DIP (Suffix: -Z)

DIP-16C-C04

16-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE
(CASE No. : DIP-16C-C04)

I

.28417.21)

rn

.31317.95)

JI
.30017.S2)TYP

}-,--....--;r-,o,.......,,~~~~~~~~~_.,...JI_T" .325I1J~=__I-J
.754119.151
.788120.021

----j

,.05011.27)MAX

tfI1i1ii11DiJ11~
II1[ ~~~'."::,::~"
~ v11f11fJ
1l1f
.15013.81)

.090(229)
.11012.79)

.03210.81)
TYP

020(051)
.05011:27)

.01310.33)
.02310.581

Dimensions in
inches (millimeters)

1-21

..

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

MB 81256-10
MB 81256-12
MB 81256-15

PACKAGE DIMENSIONS
Standard 16-pin Plastic DIP (Suffix: -PI
l6-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M03)

:::~::i: :::::)j:::
I.

.29017.37)
.31017.87)

1

.748119.0)
.776119.7)

Dimensions in
inches (millimeters)

Standard 18-pin Plastic LCC (Suffix: -PV)
l8-LEAD PLASTIC CHIP CARRIER
(CASE No.: LCC.18p·M04)

.322±00513"''

I .• 1. 100 (2.54)
TYP

0 ~nUnUnununurLW
D

Dimensions in
inches (millimetres)

1-23

Imlllllllllllllllm~llmlllllmlllllllllllllll MB 81256-10
FUJITSU MB 81256-12
111111111111111111111111111I11111111111111111111111

MB 81256-15

PACKAGE DIMENSIONS
Standard l8·pad Ceramic LCC (Suffix: ·TV)

LCC·18C·F04

l8·PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER
(CASE No.: LCC·18C·F04)
PIN NO.1 INDEX

\
b

n
.485( 12.32)
.500(12.70)

.280(7.11)
.295(7.49)

I.

1.,,5(2.92)

·Shape of Pin 1 index: Subject to change without notice

1-24

MAX

Dimension in
inches (millimeters).

MB 81257-10
MB 81257-12
MB 81257-15
September 1985
Edition 4.0

262,144-BIT DYNAMIC RANDOM ACCESS MEMORY
The Fujitsu M B B1257 is a fully decoded, dynamic NMOS random access
memory organized as 262,144 one-bit words. The design is optimized for highspeed, high performance applications such as mainframe memory, buffer
memory, peripheral storage and environments where low power dissipation and
compact layout is required.
Multiplexed row and column address inputs permit the MB B1251 to be
housed in a standard 16 pin DIP/ZIP and lB pad LCC. Pin-outs conform to the
JEDEC approved pin out. Additionally, the MB 81257 offers new functional
enhancements that make it more versatile than previous dynamic RAMs.
"CAS-before-RAS" refresh provides an on-chip refresh capability that is an
upward compatible version of MB 8266A. The MB 81257 also features "Nibble
Mode" which allows high speed serial access to up to 4 bits of data.
The MB 81257 is fabricated using silicon gate NMOS and Fujitsu's advanced
Triple-Layer Polysilicon process. This process, coupled with single-transistor
memory storage cells, permits maximum circuit density and minimal chip size.
Dynamic circuitry is employed in the design, including the sense amplifiers.

D
PLASTIC PACKAGE
DIP-16-MOl

PLASTIC PACKAGE
LCC-18P-M04

Clock timing requirements are non-critical, and power supply tolerance is very
wide. All inputs and output are TIL compatible.
•
•
•

•

•

•
•

•

262,144 x 1 RAM, 16 pin Dlp'and
ZIP/18 pad LCC
Silicon-gate, Triple Poly NMOS,
single transistor cell
Row access time,
100 ns max. (MB 81257-10)
120 ns max. (MB 81257-12)
150 ns max. (MB 81257-15)
Cycle time,
200 ns min. (MB 81257-10)
220 ns min. (MB 81257-12)
260 ns min. (MB 81257-15)
Nibble cycle time,
45 ns max. (MB 81257·10)
50 ns max. (MB 81257·12)
60 ns max. (MB 81257·15)
Single +5V Supply, ±10% tolerance
Low power,
385 mW max. (MB 81257-10)
358 mW max. (MB 81257-12)
314 mW max. (MB 81257-15)
25 mW max. (standby)
256 refresh cycles every 4ms

•
•
•
•
•
•
•

C"AS-before-RAS, RAS-only,
Hidden refresh capability
High speed Read-white-Write cycle
tAR, tWCR, tDHR, tRWD are
eliminated
Output unlatched at cycle end
allows two-dimensional chip select
Common I/O capability using
Early Write operation
On-chip latches for Addresses and
Data-in
Standard 16-pin Ceramic (Seam Weld)
DIP (Suffix:-C)
Standard 16-pin Ceramic (Cerdip)
DIP (Suffix: -Z)
Standard 16-pin Plastic
DIP (Suffix: -PI
Standard 18-pad Ceramic
LCC (Suffix: -TV)
Standard 18-pin Plastic
LCC (Suffix: -PV)
Standard 16-pin Plastic
,ZIP (Suffix: -PSZ)

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating
Symbol
Voltage on any pin relative to Vss
VIN, VnUT
Voltage on Vee supply relative to Vss
VCC
Ceramic
Storage temperature
TSTG
Plastic
Power dissipation
Short circuit output current

Pn

-

PLASTIC PACKAGE
ZIP-16P-MOI
DIP-16C-A03: See Page 19
DIP-16C-A04: See Page 20
DIP-16C-C04: See Page 21
LCC-18C-F04: See Page 24

PIN ASSIGNMENT

L'_6 DOUT
Ll~ A6
TOP VIEW Ll~ NC

Value

Unit

-1 to +7
-1 to +7
-55 to +150
-55 to +125
1.0
50

V
V

'c
W
mA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

:13 A3

~j

A4

fa~9~o~ii~
.At \ A7AS

Vee

Pin assignment for ZIP: See page 23
This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi·
mum rated voltages to this high impedance
circuit.

1-25

1IIIIIIImlllllllllllllllllllllllllllllllllllili MB 81257-10
. FUJITSU MB 81257-12

~llllllllllllllllllllllllllllllllllllllllmllll MB 81257-15

Fig. 1 - MB 81257 BLOCK DIAGRAM

AS

CLOCK GEN.
NO.1

AS

REFRESH
CONTROL
CLOCK

r--

-

INTERNAL
AODRESS
COUNTER

r-A

WRITE
CLOCK
GEN.

!

p..- f-

I

--

r-'-- __

I-U.J

m~8

DATA
IN
BUFF.

COLUMN
DECODER

!II'

lL",
r-r--v "-U
-

0

~

=u

r·
:1:_

>-u;;:
->-0
"'<>:0:
O>...J_

CAPACITANCE

~

-

a:
w

0

~

0
u
w
0

....

~7

"

I

j

-

I

A

SENSE AMPS
I/O GATING

a>...J_

-

CLOCK GEN.
NO.2

, -1 - - - - - - - . - - -

I

-

L

~~

t

Ao

I

M-J

DATA
OUT
BUFF.

--

DOUT

262,144 BIT
STORAGE CELL

;;:

0
0:

---Vee

L----

-··--~vss

(TA = 25°CI

Parameter

Symbol

Typ

Max

Unit

Input Capacitance AotoAs, D'N

C 'N1

7

pF

Input Capacitance RAS, CAS, WE

C 'N2

8

pF

Output Capacitance DOUT

COUT

7

pF

MB 81257-10
MB 81257-12 FUJITSU
MB 81257-15

1111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Parameter

Symbol

Min

Typ

Max

Unit

Vcc

4.5

5.0

5.5

V

Vss

0

0

0

V

Input High Voltage, all inputs

V'H

2.4

6.5

V

Input Low Voltage, all inputs

V'L

-2.0

0.8

V

Supply Voltage

..

Operating
Temperature

O°C to +70°C

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Value
Symbol

Parameter
OPERATING CURRENTAverage Power Supply Current
(RAS, CAS cycling; t RC = Min.)

Min
M881257-10
M881257-12

NIBBLE MODE CURRENTAverage Power Supply Current
(RAS= V'L, CAScycling;tNc = Min.)

MB 81257-12

REFRESH CURRENT 2Average Power Supply Current
(CAS-before-RAS; tRc = Min.)

MB 81257-12

rnA

57
4.5

MB 81257-10
MB 81257-12

Unit

70

Icc2

REFRESH CURRENT 1Average Power Supply Current
(RAS cycling, CAS = V'H; t RC = Min.)

Max
65

ICCl

MB 81257-15

STANDBY CURRENT
Standby Power Supply Current
(RAS, CAS = V'H)

Typ

rnA

60
55

Icc3

MB 81257-15

rnA

50

MB 81257-10

22
20

Icc4

rnA

18

MB 81257-15

65

MB 81257-10

60

Iccs

MB 81257-15

rnA

55

INPUT LEAKAGE CURRENT any input
(V'N = OV to 5.5V, Vcc = 5.5V, Vss = OV, all other pins
not under test = OV)

IlIl)

-10

10

I1A

OUTPUT LEAKAGE CURRENT
(Data is disabled, V OUT = OV to 5.5V)

lOll)

-10

10

I1A

OUTPUT LEVEL Output Low Voltage
(Iol = 4.2 rnA)

VOL

0.4

V

OUTPUT LEVEL Output high Voltage
(I OH = -5.0 rnA)

V OH

NOTE

2.4

V

-. Icc is depended on output loading and cycle rates. Specified values are obtained with the output open.

1-27

D

1111111111111111111111111111111111111111111111111

MB 81257-10

FUJITSU MB 81257-12
1111111111111111111111111111111111111111111111111

MB 81257-15

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.) 1~1'lli..1t1il
Parameter

I&m

MB 81257-10

MB B1257-12

MB 81257-15

Min

Min

Min

Symbol

Unit
Max

Max

Ti me between Refresh

tREF

Random ReadlWrite Cycle time

t RC

200

220

260

Read-Write Cycle Time

tRWC

200

220

260

Access Time from RAS
Access Time from CAS

11m
lilm

4

4

Max
4

ms
ns
ns

tRAC

100

120

150

ns

tCAc

50

60

75

ns

Output Buffer Turn off Delay

tOFF

0

25

0

25

0

30

ns

Transition Time

tT

3

50

3

50

3

50

ns

RAS Precharge Time

tRP

85

RAS Pulse Width

t RAS

105

RAS Hold Time

t RSH

55

CAS Pulse width

t CAS

55

CAS Hold Time

90
100000

120

100
100000

60

ns
100000

ns

100000

ns

75

60
100000

150

100000

75

ns

tCSH

105

tRCD

20

tCRS

10

10

10

Row Address Set Up Time

tAS R

0

0

0

ns

Row Address Hold Time

tRAH

10

12

15

ns

Column Address Set Up Time

RAS to CAS Delay Time

.Hi]

CAS to RAS Set Up Time

22

ns

150

120
50

60

25

75

ns
ns

t ASC

0

0

0

ns

Column Address Hold Time

tCAH

15

20

25

ns

Read Command Set Up Time

tRCS

0

0

0

ns

Read Command Hold Time Referenced
to CAS

III

tRCH

0

0

0

ns

Read Command Hold Time Referenced
to RAS

III

tRRH

20

20

20

ns

1m

Write Command Set Up Time

twcs

0

0

0

ns

Write Command Pulse Width

twp

15

20

25

ns

Write Command Hold Time

t WCH

15

20

25

ns

Write Command to RAS Lead Time

t RWL

35

40

45

ns

25

ns

Write Command to CAS Lead Time

tCWL

20

30

Data I n Set Up Ti me

tos

0

0

0

ns

Data In Hold Time

tOH

15

20

25

ns

t cwo

15

20

25

ns

Referenced to RAS (CAS-before-RAS cycle)

t FCS

20

20

20

ns

Refresh Hold Time for CAS
Referenced to RAS (CAS-before-RAS cycle)

t FCH

20

25

30

ns

CAS to WE Delay

1m

Refresh Set Up Time for CAS

1-28

MB 81257-10
MB 81257-12
MB 81257-15

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIW

FUJITSU
111111111111111111111111111111111111111111111111111I

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)
MB 81257·10
Parameter

ImJm

Symbol

Max

Min

MB 81257·12

MB 81257·15

Min

Min

Max

Unit

Max

CAS Precharge Time (CAS·before·RAS cycle)

tePR

20

25

30

ns

RAS Precharge to CAS Active Ti me
(Refresh cycles)

tRPe

20

20

20

ns

Ni bble Mode ReadlWrite Cycle Time

tNC

45

50

60

ns

Nibble Mode Read·Write Cycle Time

tNRWC

45

50

60

tNCAC

Nibble Mode CAS Pulse Width

tNCAS

20

25

30

ns

Nibble Mode CAS Precharge Time

tNCP

15

15

20

ns

Nibble Mode Read RAS Hold Time

tNRRSH

20

25

30

ns

Nibble Mode Write RAS Hold Time

tNWRSH

35

40

45

Nibble Mode CAS Hold Time Referenced
to RAS

tRNH

20

20

20

ID
ID

tRTC

330

Refresh Counter Test RAS Pulse Width

tTRAS

230

Refresh Counter Test CAS Precharge
Time

ID

tCPT

50

Refresh Counter Test Cycle Time

25

ns

Nibble Mode Access Time

20

265
60

30

10000

320
70

ns

ns

430

375
10000

D

ns
10000

ns
ns

Notes:

D An

II Operation

fJ

iii
m
1m

initial pause of 200 /lS is required after power up.
And then several cycles (to which any 8 cycles to per·
form refresh are adequate) are required before proper
device operation is achieved.
If internal refresh counter is to be effective, a mini·
mum of 8 CAS before RAS refresh cycles are required.
AC characteristics assume tT = 5 ns.
V'H (min) and V'L (max) are reference levels for
measuring timing of input signals. Also, transition
times are measured between V'H (min) and V'L
(max.).
Assumes that t RcD ~ t RcD (max). If t RCD is greater
than the maximum recommended value shown in this
table, t RAC will increase by the amount that t RCD
exceeds the value shown.
Assumes that tRcD ~ t RCD (max).
Measured with a load equivalent to 2 TTL loads and
100 pF.

m

II

II

m

OJ

within the t RCD (max) limit insures that
t RAc (max) can be met. t RCD (max) is specified as a
reference point only; if t RCD is greater than the
specified t RCD (max) limit, then access time is con·
trolled exclusively by t eAe .
t RCD (min) = tRAH (min) + 2tT (t T =5ns) + t Ase (min)
Either tRRH or t RCH must be satisfied for a read cycle.
twcs and tCWD are not restrictive operating para·
meters. They are included in the data sheet as electrical
characteristics only. If twcs ~ twcs (min). the cycle
is an early write cycle and the data out pin will remain
open circuit (high impedance) throughout entire cycle.
If tewD ~ tCWD (min). the cycle is a read·write cycle
and data out will contain data read from the selected
cell. If neither of the above sets of conditions is satis·
fied the condition of the data out is indeterminate.
Test mode cycle only.

1-29

1111111111111111111111111111111111111111111111111

MB 81257-10

FUJITSU MB 81257-12
1111111111111111111111111111111111111111111111111

MB 81257-15

Read Cycle

D

f---------tRc--------------t
1-------tRAS-------t
RAS

lr----.l

V'HV'L-

J----tRSHI----t..;

CAS

ADDRESSES

_ .......--'+---+---. f-~--tCAS--__I r + - ' r - - - - - V'HV'L - ,

V'HV'L -

.
~tCAC

WE

i------tRAC-------I
DOUT

VOHVOL

-------HIGH-Z:------{I

'i,1~f

~-'::::=-.I)'"

G9 Don't Care

Write Cycle (Early Write)

DOUT

VOH '_ _ _ _ _ _ _ _ _ _ _ _ H I G H _ Z ' - - - - - - - - - - - VOL -

1-30

611 Don't Care

MB B1257-10 1111111111111111111111111111111111111111111111111111
MB 81257-12 FUJITSU
MB 81257-15 111111!lllllllllllllllllllllllllmlllllllllllllllll

..

Read-Write/Read-Modify-Write Cycle

~----------------------t~R~W~C==============~~:::::j
~---------------tRAS-

tCSH
---f-------tCAS------------I
tASH

ADDRESSES

~:~-=- •.

-,..:;:.::::;::.==-r

V'H---~~~~~:j---t::====~~======:{
V, L- --.......+;;.:...;..;.;..,J

DOUT

E]

Don't Care

Nibble Mode Read Cycle

ADDRESSES

DOUT

III Don"t Care

1-31

Ilmllm~~IIIIIIIIIIII~IIIIIIII~1II11111111111 MB 81257-10
FUJITSU MB 81257-12
il l l l l l l l l l ~1 1I 1I 1 1 1 1I 1 1 1 1 1 1 MB 81257-15

Nibble Mode Write Cycle

ADDRESSES

VOH- _ _ _ _ _ _ _ _ _ _ _ _ _ HIGH_Z _ _ _ _ _ _ _ _ _ _ __

DOUT

VOL-

II Don't Care
Nibble Mode Read-Write Cycle

ADDRESSES

•

1-32

Don't ear.

MB B1257-10 m~mlml~~llllm~~~~~~~~~~mm
MB 81257-12 FUJITSU
MB 81257-15 1IIIIIIIIIIIIIIIIIIIImlml l l l l l l l l l lili

..

RAS"-only Refresh Cycle
NOTE: WE, DIN = Don't care, As = V IH or V i l

ADDRESSES

(Ao to A1 )

VOH-----------~~
·

·

-----------+-------------HI GH-Z----------------

VOl- ____________

~

DOUT

•

Don't Care

CAS-before-RAS Refresh Cycle
NOTE: Address, WE, DIN = Don't care

tOFF

DOUT

VO·-----"'\l
VOL ________~-------------------HIGH.Z---------------------

I!iI Don't Car.

1-33

1111111111111111111111111111111111111111111111111111

MB 81257-10

FUJITSU MB 81257-12
1IIIIIIIIIIIIIIIIIImllllllllllllllllillmlllllili

MB 81257-15

Hidden Refresh Cycle

DOon'tesre

CAS-before-RAS Refresh Counter Test Cycle

ADDRESSES

WE(Read!

WE(Write)

LiD Don't Cere

1-34

MB 81257-10
MB 81257-12 FUJITSU
MB 81257-15

1111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111

DESCRIPTION
Simple Timing Requirement
The MB 81257 has improved circuitry

that eases timing requirements for high
speed access operations. The MB 81257
can operate under the condition of
tRCD (max) = tCAC thus providing
optimal timing for address multiplexing.
In addition, the MB 81257 has the
minimal hold times of Address (tCAH),
WE (tWCH) and D'N (t DH ). The
MB 81257 provides higher throughput
in inter·leaved memory system applications. Fujitsu has made timing requirement that are referenced to RAS
non-restrictive and deleted them from
the data sheet. These include tAR,
tWCR, tOH Rand t RWD . As a result,
the hold times of the Column Address,
D,N and WE as well as tCWD (CAS
to WE Delay) are not ristricted by
tRCD·
Address Inputs:
A total of eighteen binary input address
bits are required to decode any 1 of
262,144 cell locations within the
MB 81257. Nine row-address bits are
established on the input pins (Ao
to As) and are latched with the Row
Address Strobe (RAS)' Nine columnaddress bits are established on the input
pins and are latched with the Column
Address Strobe (CAS). All row addresses must be stable on or before the
falling edge of RAS. CAS is internally
inhibited (or "gated") by RAS to
permit triggering of CAS as soon as the
Row Address Hold Time (tRAH) specification has been satisfied and the
address inputs have been changed from
row-addresses to column-addresses.
Write Enable:
The read mode or write mode is selected
with the WE input. A high on WE
selects read mode, low selects write
mode. The data input is disabled when
read mode is selected.
Data Input:
Data is written into the MB 81257
during a write or read-write cycle. The
later falling edge of WE or CAS is a
strobe for the Data In (D'N) register. In
a write cycle, if WE is brought low

before CAS, D'N is strobed by CAS,
and the set-up and hold times are referenced to CAS. In a read-write cycle,
WE can be delayed after CAS has been
low and CAS to WE Delay Time (tCWD)
has been satisfied. Thus D IN is strobed
by WE, and set-up and hold times are
referenced to WE.
Data Output:
The output buffer is three-state TTL
compatible with a fan-out of two
standard TTL loads. Data out is the
same polarity as data-in. The output is
in a high impedance state until CAS is
brought low. In a read cycle, or readwrite cycle, the output is valid after
t RAC from transition of RAS when
tRCD (max) is satisfie~ after t CAC
from transition of CAS when the
transition occurs after tRCD (max.)
Data remain valid until CAS is returned to a high level. In a write cycle,
the identical sequence occurs, but data
is not val id.
Fast Read-While-Write cycle
The MB 81257 has a fast read while
write cycle which is achieved by precise
control of the three-state output buffer
as well as by the simplified timings,
described in the previous section.
The output buffer is controlled by the
sate of WE when CAS goes low. When
WE is low during CAS transition to
low, the MB 81257 goes into the
early write mode in which the output
floats and the common I/O bus can be
used on the system level. Whereas, when
WE goes low after tCWD following CAS
transition to low, the MB 81257 goes
into the delayed write mode. The
output then contains the data from the
cell selected and the data from D'N
is written into the cell selected. Therefore, a very fast read write cycle (tRwc
= tRcI is possible with the MB 81257.
Nibble Mode:

Nibble mode allows high speed serial
read, write or read-modify-write access
of 2, 3 or 4 bits of data. The bits of data
that may be accessed during nibble
mode are determined by the 8 row
addresses and the 8 column addresses.
The 2 bits of addresses (CAs, RAs) are

used to select 1 of the 4 nibble bits for
initial access. After the first bit is
accessed by normal mode, the remaining
nibble bits may be accessed by toggling
CAS high then low while RAS remains
low. Toggling CAS causes RAe and
CAs to be incremented internally while
all other address bits are held constant
and makes the next nibble bit available
for access. (See Table 1).
If more than 4 bits are accessed during
nibble mode, the address sequence will
begin to repeat. If any bit is written
during nibble mode, the new data will
be read on any subsequent access. If the
write operation is executed again
on subsequent access, the new data will
be written into the selected cell location.
In nibble mode, the three-state control
of the DOUT pin is determined by the
first normal access cycle.
The data output is controlled only by
the WE state referenced at the CAS
negative transition of the normal cycle
(first nibble bit). That is, when twcs>
twcs (min) is met, the data output will
remain high impedance state throughout
the succeeding nibble cycle regardless
of the WE state. Whereas, when tCWD >
tCWD (min) is met, the data output will
contain data from the cell selected
during the succeeding nibble cycle regardless of the WE state. The write
operation is done during the period in
which the WE and CAS clocks are low.
Therefore, the write operation can be
performed bit by bit during each nibble
operation regardless of timing conditions of WE (twcs and tCWD) during
the normal cycle (first nibble bit).
See Fig. 2.
Refresh:
Refresh of the dynamic memory cells is
accomplished by performing a memory
cycle at each of the 256 row-addresses
(AD to A7) at least every 4 ms.
The MB 81257 offers the following 3
types of refresh.
RAS-only Refresh;
The RAS only refresh aboids any output during refresh because the output
buffer is in the high impedance state unless CAS is brought low. Strobing each

1-35

..

1111111111111111111111111111111111111111111111111111

MB 81257-10

FUJITSU MB 81257-12
1111111111111111111111111111111111111111111111111111

MB 81257-15

of 256 row-addresses (Ao to A7) with
RAS will cause all bits in each row to
be refreshed. Further RAS-only refresh
results in a substantial reduction in
power dissipation. During l1AS-only
refresh cycle, either V'H or V'L is per·
mitted to As.
CAS-before-RAS Refresh;
CAS-before-RAS refreshing available on
the MB 81257 offers an alternate refresh method. If CAS is held low
for the specified period (tFCS) before
RAS goes to low, on-chip refresh
control clock generators and the refresh
address counter are enabled, and an
internal refresh operation takes place.
After the refresh operation is performed, the refresh address counter is automatically incremented in preparation
for the next CAS-before-RAS refresh
operation.
Hidden Refresh;
A hidden refresh cycle may takes place
while maintaining latest valid data at
the output by extending the CAS active
time. For the MB 81257, a hidden
refresh cycle is CAS-before-RAS" refresh.

The internal refresh address counters
provide the refresh addresses, as in a
normal CAS-before-RAS refresh cycle.
CAS-before-RAS Refresh Counter Test
Cycle:
A special timing sequence using CASbefore-RAS counter test cycle provides
a convenient method of verifying the
functionality of CAS-before-RAS reo
fresh activated circu itry. After the
CAS-before- RAS refresh operation, if
CAS goes to high and goes to low again
while RAS is held low, the read and
write operation are enabled. This is
shown in the CAS-before-RAS counter
test cycle timing diagram. A memory
cell address, consisting of a row address
(9 bits) and a column address (9 bits),
to be accessed can be defined as follows:
• A ROW ADDRESS - Bits Ao to A7
are defined by the refresh counter.
The bit As is set high internally.
• A COLUMN ADDRESS - All the bits
Ao to As are defined by latching
levels on Ao to As at the second
fall ing edge of CAS.

Suggested CAS-before-RAS Counter Test
Procedure
The timing, as shown in the CAS-beforeRAS Counter Test Cycle, is used for
the following operations;
1) Initialize the internal refresh address
counter by using eight CAS-befo'reRAS refresh cycles.
2) Throughout the test, use the same
column address, and keep RA8 high.
3) Write "low" to all 256 row address
on the same column address by using
normal early write cycles.
4) Read "low" written in step 3) and
check, and simultaneously write
"high" to the same address by using
internal refresh counter test readwrite cycles. This step is repeated
256 times, with the addresses being
generated by internal refresh address
counter.

5) Read "high" written in step 4) and
check by using normal read cycle for
all 256 locations.
6) Complement the test pattern and
repeat step 3), 4) and 5).

Table 1 - NIBBLE MODE ADDRESS SEQUENCE EXAMPLE
SEQUENCE

NIBBLE 81T

RAS/CAS (normal mode)
toggle CAS (nibble mode)

2

toggle CAS (nibble mode)

3

toggle CAS (nibble mode)

4

toggle CAS (nibble mode)

1-36

RAs

ROW ADDRESS

CAs

COLUMN
ADDRESS

0

10101010

0

10101010

input addresses

10101010

0

'''''''' J

generated i nternall y

0

10101010

1

10101010

0

10101010

10101010
10101010

0

10101010

sequence repeats

MB 81257-10 1IIIIIIIIIIIIIIIIIIIImlllllllllllllillmllllllili
MB 81257-12 FUJITSU
MB 81257-15 1111111111111111111111111111111111111111111111111111

..

Fig. 2 - Nibble Mode

1) The case of first nibble cycle is Early write
RAS

~~____________________________________~;---

WE~

\

I

x::x______x::x=x:::x____

D,N

DOUT ~>-----------HIGH.Z------------

LEady Write

.1.

No Ope.-'..J..!.___-write'-_II-.--Write---l

o :

(Add.lncrementl

Valid Data

2) The case of first nibble cycle is delyed write (Read·Write)
RAS

~

\~.

_______________--J'

,--

\~

____

,'------',
_________
___

_ _ _...JI

~~

x::x~

DOUT

L-Read.write---II......~Read.write

•

I • Read~Read-Write-J
0: Valid Oata

1-37

1IIIIIIIIIIIIIIIIIIIIIIIIIIImllllllllllllllllllili

MB 81257-10

FUJITSU MB 81257-12
1111111111111111111111111111111111111111111111111111

MB 81257-15

Table·2 FUNCTIONAL TRUTH TABLE
RAS

CAS

WE

D,N

DouT

Read

Write

Refresh

H

H

Don't Care

Don't Care

High·Z

No

No

No

Standby

L

L

H

Don't Care

Valid Data

Yes

No

Yes

Read

L

L

L

Valid Data

High·Z

No

Yes

Yes

L

L

L

Valid Data

Valid Data

Yes

Yes

Yes

Delayed Write or Read·Write
(twcs ,;;; twcs (min) or
tCWD ~ tCWD (min))

L

H

Don't Care

Don't Care

High·Z

No

No

Yes

RAS· only Refresh

L

L

Don't Care

Don't Care

Valid Data

No

No

Yes

CAS·before·RAS Refresh Valid
data selected at previous Read
or Read·Write cycle is held.

H

L

Don't Care

Don't Care

High·Z

No

No

No

CAS disturb.

Note

Early Write
twcs~twcs (min)

Fig. 3 - CURRENT WAVEFORM (Vcc=5.5V, TA =25°C)

Hidden Refresh Cycle

RAS/CAS Cycle

Nibble Mode Cycle

RAS·only Refresh Cycle

r--...

f-

I-- V- ' - f-/"

160
120
80
40

IA

A

\

U
AA ~
~ \ \. ~

!~

'fv../!\
V

\... ,.J

A

II \
\

Ir-,

N 'v L .J
50 ns/Division

1-38

-

\
\

IlIA
'-

V

1\1\.J\.

-- . f - -

.A i - -

MB 81257-10
MB 81257-12 FUJITSU
MB 81257-15

1111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111

TYPICAL CHARACTERISTICS CURVES
Fig. 4 - NORMALIZED ACCESS TIME
vs SUPPL Y VOLTAGE
UJ

~

i=

1. 1

o
UJ
N

1.0

~
o
z

CIl
CIl
UJ

~

UJ

u
~

:J
III
Cl

~

I-

2

CIl

30~_+-~-~_+-~~

u
u

2~~20~~0--~20~~4~0--6~0~~80~~100
T A. AM81ENT TEMPERATURE (OCI

N
u
u

1

4.0

5.0

6.0

Vee. SUPPLY VOLTAGE (V)

1-39

1IIIIIImllllllllllllllllllillmlmllllillmi

MB 81257-10

FUJITSU MB 81257-12
1IIIImllllllllllllllllllllllllllllllllllllllili

MB 81257-15

Fig. 11 - REFRESH CURRENT 1
vs CYCLE RATE

Fig. 10 - STANDBY CURRENT
vs AMBIENT TEMPERATURE
60

~

III

.5
IZ
w
0::
0::

6

>-

w

4
3

0:
0:

I---

r-- t--

C>

2

t.l
J:

'"0:
M
u

10

~

T)250C
70

I-

r- tRc=200ns

~
I-

zw

50

::J

40

0::
0:

60
50
40

W

0:

V
.,/

.....

V

w

C>

0

I

30

w

...J

u

20
4.0
5.0
6.0
Vee. SUPPL Y VOLTAGE (V)

.2

10
0

~
I-

50

.5
w

r-~N~=45nl
TA=25°C

40
30

:;;
w

20

'"Z

u

'"0:w

OJ

"-

ID

0:

.t

_~C~=5.5J
T A =25°C

40
30
20

W

,;,
u

u

.2

50

I-

V
./

J:

10

.2

0
4.0
5.0
6.0
Vee. SUPPLY VOLTAGE

-

4
8
12
16
20
1/tNC. CYCLE RATE (MHz)

::J

C>

Z

1-40

';(

.5
0:
0:

0

...J

60

w

t.l

-

~~

Fig. 15 - REFRESH CURRENT 2
vsCYCLE RATE

Fig. 14 - NIBBLE MODE CURRENT
vs SUPPLY VOLTAGE
60

--

20

'"

ID

.t

.2

W

5

..I.
l--~ec=5.5V
TA=25°C

:;;

Z

M 30
u

::J

4

U

::J

0::
0:

3

Fig. 13 - NIBBLE MODE CURRENT
vsCYCLE RATE
60

.5

I

Z

Z

2

1/tRe. CYCLE RATE (MHz)

REFRESH CURRENT 1
vs SUPPL Y VOLTAGE

"-

",V

0

~ig. 12 -

t.l
J:

20

.2

80

'"0:w

/

V

W

20
0
20
40
60
80
100
TA. AMBIENT TEMPERATURE (C)

0:
0:

30

0:

u

.2

w

/

40

::J

"w

'"N

.5

TA=25°C

Z

ID

Z
00:
I-

50

I-

::J

t.l

- r-~J5J
~

.5

VCl=5.5J

V

/

",V

10
0

2

3

4

5

1/tRC. CYCLE RATE (MHz)

MB 81257-10 1IIIIIIIIIIIIIIIIIIIIIIIIIIIImlllillmllillmili
MB 81257-12 FUJITSU
MB 81257-15 1I11111111111111111111111111111111111111111111111111

<
!
N

I2

::!

er

Fig. 16 - REFRESH CURRENT 2
vs SUPPL V VOLTAGE
0

8

«
~
o

~25'cl

T
Or. A
tRe=200ns

lil
w

40

er

.;,

u

~

«
~
o

V

.......V

,

30

..-

~

.~ ~Max.1

«>

1.0

2

«
:t

20

;>
4.0
S.O
6.0
Vee. SUPPLY VOLTAGE (VI

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (VI

Fig. 18 - ADDRESS AND DATA INPUT
VOLTAGE vs AMBIENT TEMPERATURE

Fig. 19 - RAS. CAS AND WE INPUT
VOL TAGE vs SUPPL V VOLTAGE

3.0

3.0

Ve~=s.oJ

TA=12S'C

I~0

VIH(~in.1

2-

«~

«;:;:; 2 0
'" t!) .

V,H(Min.1

ro~

256

I'«t!)
"
u«
W

2.0

-~

I""«""
er.~
I-

~>

V,L(Max.1
1.0

n

-

I-

V,L(Max.1

..II-

>~ 1.0

02
2-

0-

«

2

«

:t

;>

:t

:>

o

80
100
20
0
20
40
60
TA • AMBIENT TEMPERATURE ('CI

3.0

I~

.E

~~
2.0

V ,H Min.1

'"'"

W

er>

":'1;> i? 1.0

V,L(Max.1

02

20

«

:t

u
u

10

«
U
«

S

(j

0

;>

-20
0
20
40
60
80
100
TA • AMBIENT TEMPERATURE ('CI

VJ4.SJ

r- TA =2S'C

lS

a:

Z -

5~

w

:2

f=

:;
«0
/""

~O

Fig. 21 - ACCESS TIME vs LOAD
CAPACITANCE

Vee~S.OV

o

4~

Vee. SUPPLY VOLTAGE (VI

Fig. 20 - RAS, CAS AND WE INPUT
VOL TAGE vs AMBIENT TEMPERATURE

~ ~
I u«

/

0""

00

..:.5

~

>~

2>

.1..I;;)

2>
«w«
erl-

0-

0-

>~

T)2S'C

0_

SO

:t

ff

3.0

~ ~ 2.0

50

;;)

u

Fig. 17 - ADDRESS AND DATA INPUT
VOLTAGE vsSUPPLV VOLTAGE

-S

-

- ---

___ r-

f.--

100 200 300 400 SOO
CL • LOAD CAPACITANCE (pFI

I
1-41

1111111111111111111111111111111111111111111111111111

MB 81257-10

FUJiTSU MB 81257-12
1IIIIIIIIIIIIImllllllllllllllllllllllllllllllllili

MB 81257-15

Fig. 22 - OUTPUT CURRENT
vsOUTPUT VOLTAGE
TAJ25°C

«
g 250
I-

Z

w 200

:::>

100

:::>

0

.::. 50

I",

I-

ffi

VCC=4.5V

-100

:~ ~CC=5,5V

0:
0:

G

-75

1\\
,\

I-

:::>
0.

I

V

.9

-

TA~25°C

«E -125

-

V

I0.

I-

V  150

()

Fig. 23 - OUTPUT CURRENT
vs OUTPUT VOLTAGE

5o
J:

-50

VCCi4,5V
-25

1

2

3

4

o

5

VOL. OUTPUT VOLTAGE (V)

>->

~~
~~

Fig. 24 - CURRENT WAVEFORM
DURING POWER UP

:[371 1I 11
15

~!z

10

I I
RAS=CAS=Vs s

0.-

mw

u~

2:::>

()

5

o

/

o.w
o.(!)

~~
U..J

»uO

t

/

RAs=m=Lc JV IH -

1

I

:wl I I I I
o

~>
0:-

1

~ ~

-2

I-w
m(!)

.. 0

OJ>

1
2
3
4
5
VO H • OUTPUT VOLTAGE (V)

Fig. 25 - SUBSTRATE VOLTAGE
DURING POWER UP

w

m..J

50#,s/Division

1-42

>->
..J-

r-TA=25°C

>-..J «E

'\ ~

.2

-3

-

. \ T A =25°C

f\..

',---

:!:

50~s/Oivision

-

MB 81257-10
MB 81257-12 FUJITSU
MB 81257-15

1111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
Standard 16·pin Ceramic DIP (Suffix: ·C)

DIP·16C·A03

16·DEAD CERAMIC (METAL SEAL)DUAL IN·LlNE PACKAGE
(CASE No.: DIP·16C·A03)

R.050(1.2
REF

\

[
tJ

J

\~

INDEX ARE

.760(19.301
.800(20.321

I

.287(7.291

.290(7.371

J.591

'Ill=!:::::=l==

I

.008(0.201
.012(0.301

5j

.200(5.08IMAX

.120(3.051
.150(3.811

.090(2.291
.11012.791

.020(0.511
.043(1.101
.015(0.381
.023(0.581

Dimensions in
inches (millimeters)

1-43

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB 81257-10
MB 81257-12
MB 81257-15

PACKAGE DIMENSIONS
Standard l6-pin Ceramic DIP (Suffix: -C)

DIP-16C-A04

l6-LEAD SEAM WELD DIP PACKAGE
(CASE No_: DIP-16C-A04)

-

'"::~::~ ~ [[
1=

)~ J Cl"
~'"'

__ """,,1

00_ 9 0

11

.290(7.371

--.:...'--===*=1=·]·871

.760119.301
.800120.321

l.00810.201
.01210.301
.04311.09ITYP

.20015.08IMAX

.12013.051
.15013.811
.02010.511
.05011.271
Dimensions in
inches and (millimeters)

1-44

MB 81257-10
MB 81257-12
MB 81257-15

1111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
Standard 16-pin Ceramic DIP (Suffix: -Z)

DIP-16C-C04

16-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE
(CASE No. : DIP-16C-C04)

I

R.02510.64)
REF

.28417.21)

1'-c:::r-i=a--..:=::::a,==a-a::==--'=Cl5"--..:==--=~-=r
.754119.15)
.788120.02)

--j

.67)

rn

.31317.95)

JI
.30017.62)TVP

.325DJ~=--_--+-J

./

i·05011.27lMAX

.20015.08)MAX

.12013.05)
.15013.81)
.09012.29)
.11012.79)

.02010.51 )
.05011.27)
.01310.33)
.02310.58)

Dimensions in
inches (millimeters)

1-45

I111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB 81257-10
MB 81257-12
MB 81257-15

PACKAGE DIMENSIONS
Standard l6'pin Plastic DIP (Suffix: ·PI
16·LEAD PLASTIC DUAL IN· LINE PACKAGE
(CASE No.: DIP·16p·M03)

::::::1::: :: :Jj:
I.

.29bI7,37)

L_)-~""==~-

310

.1

.748119.0)
.776119.7)

,04711.20)
,05911.50)

,10012,54)

I

TYP

Dimensions in
inches (millimeters)

Standard l8'pin Plastic LCC (Suffix: ·PVI
IS-LEAD PLASTIC LEADED CHIP CARRIER
(Case No, : LCC-18P-M04)
'34

,322±,005

~:gg~1340~g6~)

,08011.52) MIN

18,18±0,13)

.02510,64) MIN

I

,527±,005
113,39±0,13)

C ,00410,10)

I

,468±,020
11'.89±0,5' )

,490±,003

o L-c--oh:n::rc
®

@

~2Toor

.t
R.03010, 75) TYP
,16013,81)

.02610,66)
TYP
I
,20015,08)

REF

I.
@:

©1989 FUJITSU LIMITED C18019S-1C

1-46

LEAD No.
Dimensions in
inches (millimeters)

MB 81257-10
MB 81257-12
MB 81257-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1IIIIIIImllllllllllllllllllllllllllllllllllllllili

PACKAGE DIMENSIONS
Standard 16-Pin Plastic ZIP (Suffix: ·PSZ)
PIN ASSIGNMENT
LEAD
No.1

16

ZIP-16P-M01

16 LEAD PLASTIC ZIGZAG-IN·LlNE PACKAGE
(CASE No.: ZIP-16P-M01)
.785(19.95)
.813(20.65)

I~

.104(2.65)
.120(3.05)

'1
INDEX

I

c5

~
.008(0.20)
.012(0.30)

-

.050(1.27)

TYP

,1"

.250(6.35)
.270(6.85)

--l

.016(0.40)
.02410.60)

~nUnUnUnununurLW

.327(8.3)
MAX

-~

-4

~

-.l

~

~~

I. . 1.

.118(3.0)MIN

100 (2.54)

TYP

Dimensions in
inches (millimetres)

1-47

mlimlm~mmll~IOOlmllm~mmllll MB 81257-10
rUJITSU MB 81257-12
mmm~m~m~~I~liimOOil MB 81257-15

PACKAGE DIMENSIONS
Standard 18·pin Ceramic LCC (Suffix: ·TV)

LCC·18C·F04

l8-PAD CERAMIC (FRIT SEAL) LEAOLESS CHIP CARRIER
(CASE No.: LCC·18C·F04)

~I
I

.4B5{12.32(
500(12701

'-~'''iiiiom'''l;'''ii-,--

 -0.5 V.

1-51

D

1111111111111111111111111111111111111111111111111111

FUJITSU
1IIIIIIIIIIIIIIIImlllllllllllllllllllllllllllllili

MB 81464-10
MB 81464-12
MB 81464-15

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
Parameter

III.BIiJ

111°11....

MB 81464·10

MB 81464·12

MB81464-15

Min

Min

Min

Symbol

Unit
Max

tREF

Random Read/Write Cycle Time

t RC

200

220

260

ns

Read-Modify-Write Cycle Time

t RwC

270

305

345

ns

Page Mode Cycle Time

tpc

100

120

145

ns

Page Mode Read-Modify-Write Cycle
Time

tpRwC

170

195

225

ns

11Ii]

tRAC

Access Time from CAS

lillil

t CAC

4

Max

Time between Refresh

Access Time from RAS

4

Max

100

4

120

50

60

ms

150

ns

75

ns

Output Buffer Turn Off Delay

tOFF

0

25

0

25

0

30

ns

Transition Time

tT

3

50

3

50

3

50

ns

RAS Precharge Time

tRP

80

RAS Pulse Width

t RAS

100

100000

150

RAS Hold Time

tRSH

50

60

75

ns

90
100000

120

100

ns
100000

ns

CAS Precharge Time (Page mode only)

tcp

40

50

60

ns

CAS Precharge Time
(All cycles except page mode)

tCPN

30

32

35

ns

CAS Pulse Width

tCAS

50

CAS Hold Time

100000

60

50

22

100000

75

60

25

100

tRCD

20

CAS to RAS Set Up Time

tCRS

10

10

10

ns

Row Address Set Up Time

tAS R

0

0

0

ns

Row Address Hold Time

tRAH

10

12

15

ns

Column Address Set Up Time

tASC

0

0

0

ns

Column Address Hold Time

tCAH

15

20

25

ns

Read Command Set Up Time

tRCS

0

0

0

ns

alii

150

ns

tCSH

RAS to CAS Delay Time

120

100000

ns
75

ns

Read Command Hold Time
Referenced to RAS

Ii)

tRRH

10

15

20

ns

Read Command Hold Time
Referenced to CAS

Ii)

tRCH

0

0

0

ns

Write Command Set Up Time

1m

twcs

-5

-5

-5

ns

Write Command Hold Time

tWCH

25

30

35

ns

Write Command Pulse Width

twp

25

30

35

ns

t RwL

35

40

45

ns

Write Command to RAS Lead Time

1-52

1m

MB 81464-10
MB 81464-12
MB 81464-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

AC CHARACTERISTICS (cont'd)
(At recommended operating conditions unless otherwise noted)
Parameter

I&D!.I

Write Command to CAS lead Time

MB 81464-10

MB 81464-12

Min

Min

MB81464-15

Symbol

Unit
Max

Max

Min

Max

tCWL

35

40

45

ns

Data In Set Up Time

tos

0

0

0

ns

Data In Hold Time

tOH

25

Access Time from OE

tOEA

OE to Data In Delay Time

tOEo

35

30
27

25

30
25

ns
40

ns
ns

30

Output Buffer Turn Off Delay from OE

tOEZ

0

OE Hold Time Referenced to WE

tOEH

0

0

0

ns

CAS Set Up Time Referenced to RAS
(CAS-before-RAS refresh)

tFCS

20

20

20

ns

CAS Hold Time Referenced to RAS
(CAS-before-RAS refresh)

tFCH

20

25

30

ns

RAS Precharg~ to CAS Hold Time
(Refresh cycles)

tRPC

10

10

10

ns

CAS Precharge Time
(CAS-before-RAS cycles)

tePR

30

30

30

ns

OE to RAS in active Set Up Time

tOES

0

0

0

ns

25

0

25

0

30

ns

DIN to CAS Delay Time

OJ

tozc

0

0

0

ns

DIN to OE Delay Time

III

tozo

0

0

0

ns

Refresh Counter Test Cycle Time

IB

tRTC

375

430

505

ns

Refresh Counter Test Cycle
RAS Pulse Width

IB

tTRAS

285

Refresh Counter Test CAS
Precharge Time

IB

tCPT

50

Notes:
An initial pause of 200lls is required after power-up
followed by any 8 RAS cycles before proper device
operation is achieved. In case of using internal refresh
counter, a minimum of 8 CAS-before-RAS initialization
cycles instead of 8 RAS cycles are required.
iii AC characteristics assume tT = 5 ns.
iii V IH (min) and V IL (max) are reference levels for measuring timing of input signals. Also, transition times are
measured between V IH (min) and VIL (max).
EI Assumes that tRCO ~ tRCO (max). If tRco is greater
than the maximum recommended value shown in this
table, tRAC will be increase by the amount that tRco
exceeds the value shown.
iii Assumes that tRCO ~ tRCO (max).

D

10000

330
60

II

II

iii
II

DD

III
III

10000

395
70

D

10000

ns
ns

Measured with a load equivalent to 2 TTL loads and
100 pF.
Operation within the tRCO (max) limit insures that
tRAC (max) can be met. tRCO (max) is specified as a
reference point only; if tRco is greater than the specified tRco (max) limit, then access time is controlled
exclusively by t CAC '
tRco (min) = tRAH (min) + 2tT (t T = 5 ns) + tASC (min)
Either tRRH or tRCH must be satisfied for a read cycle.
twcs is not restrictive operating parameter. It is included
in the data sheet as electrical characteristics only. Even if
twcs ~ twcs(min), the write cycle can be excuted by
satisfying t RWL or tCWL specification.
Either tozc or tORO must be satisfied for all cycles.
Refresh Counter Test Cycle only.

1-53

Illmllll~!~~!~llllilll~IIIIIIII!II~1
FUJI'I'SlJ
~~~~OO~OO~~II~~~~OO

MB 81464-10
MB 81464-12
MB 81464-15

..

Read Cycle

ADDRESSES

DO
(OUTPUT)
DO
(INPUT)

Write Cycle (Early Write)
OE: Don't care

DO
(INPUT)

DO
(OUTPUT)

1-54

VOH - - - - - - - - - - - - H I G H - Z - - - - - - - - - - - - - V O L - I I I Don" Car.

MB 81464-10
MB 81464-12
MB 81464-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

OE Write Cycle

ADDRESSES

DQ
(INPUT)

DQ
(OUTPUT)

m Don't care
Read-Modify-Write Cycle

DQ
(INPUT)

DQ
(OUTPUT)

. . Don't Care

Note: 1) When OE is kept high through a cycle, the DQ pins are kept high-Z state.

1-55

~1111!~~lli~III~llill!IIIIIII~~ml MB 81464-10
FUJITSU

MB 81464-12

i~~IIIIIII~~llil~illlli~~IIIIIIIIIIIIII~ MB 81464-15

Page Mode Read Cycle

DO
IINPUT)

DO
(OUTPUT)

Page Mode Write Cycle
(OE=Don't Care)

RAS

CAS

V 1H VI L -

VIHVIL-

v -

ADDRESSES V IH

IL-

DO
II NPUT)

DO
(OUTPUT)

V O H - - - - - - - - - - - - - - - H I G H _ Z - - - l C I o '_ _ _ _ _ _ _ _ _ __
VOL

III Don't Car.

1-56

MB 81464-10
MB 81464-12
MB 81464-15

11111~illl~~llllmlllml~IIIII~IIIII~~
PUJITSU
~~ml~~lllmlml~~lm~~~IM~i~~1

Page Mode OE Write Cycle

D
V ,H -

~*-++~~SS~

V'L-

ADDRESSES VV 'H -

IL-

V ,H -

----t--t--"lL

V,L-

DO
(INPUT)

DO
(OUTPUT)

III Don't Care
f:1:!t INVALID DATA
Note: 1) When OE is kept high through a cycle, the DQ pins are kept high-Z state.

1-57

1111~MII~~llmniillllllllillll MB 81464.10
FUJITSU MB 81464.12
li!mll!iiiii!!iiIIM~llliill MB 81464·15

..

Page Mode Read Modify-Write Cycle

V'HV'L-

RAS

V'H-

CAS

V'L-

ADDRESSES V,W
V 1L -

V'HV'L-

WE

DQ
(INPUT)

V ,H V 1L-

DQ
(OUTPUT)

OE

V'HV 1L-

E:J Don't Care

RAS-Only Refresh Cycle
(WE, OE= Don't Care)

(OUTPUT)
DQ

=====:t---------HIGH-Z:----------

OH
VOL:
V

Emf)

1-58

Don't Care

MB 81464-10
MB 81464-12
MB 81464-15

1111111111111111111111111111111111111111111111111111

FUJITSU

IIIIIIIIIIIIIIIIIIIIIIIII~

CAS-before-RAS Refresh Cycle
NOTE: Addresses, WE, OE = Don't care

II

DO

VOH-_ _ _ _ _ _ _ _ _ _ _ _ HIGH_Z_ _ _ _ _ _ _ _ _ _ __

(OUTPUT)

V OL -

II Don't car.

Hidden Refresh Cycle

RAS

V 1H -

V'L-

CAS

V 1H -·

V'L -

DO

(OUTPUT)

DO
(INPUT)

. . Don'teare

1-59

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

..

MB 81464-10
MB 81464-12
MB 81464-15

Refresh Counter Test Cycle

RAS

CAS

VIHV 1L-

VIHV 1L-

ADDRESSES VIHV 1L-

WE

DO
(INPUT)

DO
(OUTPUT)

OE

VIHVILVIHVILVOHV OLVIHVIL-

CJ Don't Care
DESCRIPTION
Address Inputs:
A total of sixteen binary input address
bits are required to decode parallel 4
bits of 262,144 storage cell locations
within the MB 81464.
Eight row·address bits are established on
the input pins (Ao through A7) and
latched with the Row Address Strobe
(RAS). The eight column·address bits
are established on the input pins (Ao
through A7) and latched with the
Column Address Strobe (CAS).
The row and column address inputs
must be stable on or before the falling
edge of RAS and CAS, respectively.
CAS is internally inhibited (or "gated")
by RAS to permit triggering of CAS as
soon as the Row Address Hold Time
(tRAH) specification has been satisfied
and the address inputs have been
changed from row·addresses to column·
addresses.

1-60

Write Enable:
The read mode or write mode is selected
with the Write Enable (WE) input. A
high on WE selects read mode and low
selects write mode. The data inputs are
disabled when the read mode is selected.
When WE goes low prior to CAS, data·
outs will remain in the high·impedance
state allowing a write cycle.
Data Pins:
Data Inputs;
Data are written during a write or read·
modify·write cycle. The later falling
edge of CAS or WE strobes data into the
on·chip data latches. In an early,write
cycle, WE is brought low prior to CAS
and the data is strobed by CAS with
setup and hold times referenced to CAS.
In a read·modify·write cycle, thus the
data will be strobed by WE with set·up
and hold times referenced to WE.
In a read·modify·write cycle, OE must

be low after tDzo to change the data
pins from input mode to output mode
and then OE must be changed to low
before tOED to return the data pins to
input mode. In an early write cycle,
data pins are in input mode regardless
of the status of DE.
Data Outputs;
The three-state output buffers provide
direct TTL compatibil ity with a fan out
of two standard TTL loads. Data-out
are the same polarity as data-in. The
outputs are in the high·impedance state
until CAS is brought low. In a read
cycle, the outputs go active after the
access time interval tRAC and tOEA are
satisfied. The outputs become valid
after the access time has elapsed and remain valid While CAS and OE are low.
In a read operation, either OE or CAS
returning high brings the outputs into
the high impedance state.

MB 81464-10
MB 81464-12
MB 81464-15

Output Enable:
The OE controls the impedance of the
output buffers. In the high state on OE,
the output buffers are high impedance
state. In the low state on OE, the output buffers are low impedance state.
But in early write cycle, the output buffers are in high impedance state even if
OE is low. In the page mode read cycle,
OE can be allowed low through the
cycle. In the page mode early write
cycle, OE can be allowed high throughout the cycle. In the page mode readmodify-write or delayed write cycle,
OE must be changed from low to high
with tOED,
Page Mode:
Page Mode operation permits strobing
the row-address into the MB 81464
while maintaining RAS at a low throughout all successive memory operations in

which the row-address doesn't change.
Thus the power dissipated by the
falling edge of RAS is saved. Further,
access and cycle times are decreased
because the time normally required to
strobe a new row-address is eliminated.
Refresh;
Refresh of the dynamic memory cells is
accomplished by performing a memory
cycle at each of the 256 row-addresses
(Ao through A7) at least every four
milliseconds.
The MB 81464 offeres the following
three types of refresh.
RAS-Only Refresh:
RAS-only refresh avoids any output
during refresh because the output buffuers are in the high impedance state
unless CAS is brought low. Strobing

each of 256 row-addresses with RAS
will cause all bits in each row to be refreshed.
Further RAS-only refresh results in a
substantial reduction in power dissipation.
CAS-before-RAS Refresh;
CAS-before-RAS refreshing available on
the MB 81464 offers an alternate refresh method. If CAS is held low for
the specified period (tFes) before RAS
goes to low, on chip refresh control
clock generators and the refresh address
counter are enabled, and a internal
refresh operation takes place.
After the refresh operation is performed, the refresh address counter is
automatically incremented in preparation for the next CAS-before-RAS
refresh operation.
Hidden Refresh:
Hidden refresh cycle may take place
while maintaining latest valid data at
the output by extending CAS active
time.

In MB 81464, hidden refresh means
CAS-before-RAS refresh and the internal refresh addresses from the counter
are used to refresh addresses i.e., it
doesn't need to apply refresh addresses,
because CAS is always low when RAS
goes to low in the cycle.
CAS-before-RAS Refresh Counter Test
Cycle:
A special timing sequence using CASbefore-RAS counter test cycle provides
a convenient method of verifying the
functionality of CAS-before-RAS refresh activated circuitry. After the
CAS-before-RAS refresh operation, if

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

CAS goes to high and goes to low again
whi Ie RAS is held low, the read and
write operation are enabled. This is

shown in the CAS-before-RAS counter
test cycle timing diagram. A memory
cell address, consisting of a row address
(9 bits) and a column address (9 bits),
to be accessed can be defined as follows:
* A ROW ADDRESS - All bits are
defined by the refresh counter.
*A COLUMN ADDRESS - All the bits
Ao to A7 are defined by latching
levels on Ao to A7 at the second
falling edge of CAS.
Suggested CAS-before-RAS Counter
Test Procedure
The timing, as shown in the CAS-beforeRAS Counter Test Cycle, is used for the
following operations:
1) Initialize the internal refresh address
counter by using eight CAS-beforeRAS refresh cycles.
2) Throughout the test, use the same
column address.
3) Write "low" to all 256 row address
on the same column address by using
normal early write cycles.

4) Read "low" written in step 3) and
check, and simultaneously write
"high" to the same address by using
internal refresh counter test cycles.
This step is repeated 256 times, with
the addresses being generated by
internal refresh address counter.
5) Read "high" written in step 4) and
check by using normal read cycle for
all 256 locations.
6) Complement the test pattern and
repeat step 3), 4) and 5).

1-61

..

1111111111111111111111111111111111111111111111111111

FUJITSU

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~IIIIIIIIIIIIIIIIIII

MB 81464-10
MB 81464-12
MB 81464-15

Fig. 2 - CURRENT WAVEFORM (Vee = 5.5 V, TA = 25°C)

10

.

"

Re d/W teCye\

RA

Long Cvcle

sl-- I--

V-- I-I~

E

r-r- +-'

c= 1=

V- r- I--

0

~

150

0

,

1\

VI

11lO0

JI

.

\

\/\

\

j'\..j)

" I

(\

iJ \ ..JI\

I'..

r\

1\

II

1\

50ns{OIVI$lon

PegeModeCvcle

RAS onlV Refresh evere

CAS:-before-RAS Refrelh Cycle

sl-- I--

Sr- I- l-

V-V- h
V-

0"E
200

1

160

Jl

100
0

1-62

I
IV 1\

'\1.1 I.Il

-

r

J-

ill
V \ d.

II
! \.

san sI Divi5ion

--

\.V

"\

III

II

\..

l-

I'-

11
1\

1I

MB 81464-10 ml~~lmllllm~~~III~lm~llllllllmllm
MB 81464-12 FUJITSU
MB 81464-15 11111111111111111111111111111111111~11111~llm~1

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - NORMALIZED ACCESS TIME
VS. SUPPLY VOLTAGE
w

:;

1.3

'"
w

1.2

~

1. 1

'"U
cw

N

::J

w

1.0

o
z

U

«
!J-

~

.§
fZ

i=

'"'"w
u

',,-

0.9
0.8

60
50

20

w

D-

o
U

10

"'- r---

~

w

/

V

fZ

V

.!!

,/'" V

80
70

SUPPLY VOLTAGE

T A =25'C
tRC = 230n5

w

a::
a::

60

:J

u

<:l

z
i=
«
a::

/

w

50

_____ 10""

40

D-

o

30

----- -----

u

.!!

20

litRe. CYCLE RATE IMHz)

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE IV)

Fig.7 - OPERATING CURRENT
VS. AMBIENT TEMPERATURE

Fig.8 - STANDBY CURRENT
VS. SUPPLY VOLTAGE

2

4

6

80 Vee = 5.5V
70 tRe = 230 ns

60~-+--~~r--r--+-~

6
~

.§

TA

='25'C

5

fZ

w

a::
a::

4

:J

50~-+--~~~-r--+-~

40~-+--1-~~~--+-~

D-

u

/

.§

:J

o

......

0.8

VS.

~

T A =25'C
Vee = 5.5V

u

z
i=

0.9

z
U
«
!J-

w

<:l

1.0

«
:;
0

z

~

cw

Fig. 6 - OPERATING CURRENT

0

~

N

a::

.!!

«

D

Fig.5 - OPERATING CURRENT
VS. CYCLE RATE

40
30

z

1.1

-20
0
20
40
60
80
100
TA. AMBIENT TEMPERATURE I'C)

U

i=
«
a::

~ 5.0V

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE IV)

:J

<:l

Vee
1.2

::J

w

a::
a::

1.3

u

«

~

«
~

:;

TA =25'C

i=

Fig. 4 - NORMALIZED ACCESS TIME
vs. AMBIENT TEMPERATURE

30~-+--~~~-r--+-~
20

-~20~+0--~20~~40~~6~0~8~0~1~00
T A • AMBIENT TEMPERATURE I'C)

u

>-

"'cz

~

~

1

.!!
4.0
5.0
6.0
Vee. SUPPLY VOLTAGE IV)

1-63

.illOOlillml

MB 81464-10
MB 81464-12
MB 81464-15

FUJITSU
Iml~~~~~~~~.lmm~~ml

~

III

E

Vcc

w

>'"0z
..:
l-

~

E

- -

4

:J
C,)

25.5V

5

IZ
II:
II:

Fig. 10 - REFRESH CURRENT 1
VS. CYCLE RATE

Fig. 9 - STANDBY CURRENT
AMBIENT TEMPERATURE

VI.

6

~

3
2

60

IZ

w

II:
II:

:J

C,)

:t:
I/)
w
II:

u.

40
30
20

10
M
()

.!:'

.!:'

70

TA = 25°C
'RC = 230n.

Fig. 12 - PAGE MODE CURRENT
vs. CYCLE RATE

II:
II:

:J

50

40

w
0
0

30

w

20

:;
40

II:

M 30
u

I--

20

-- ---

f..-

Cl

..:
0~

60

lZ

SO

0

:J

E
N

IZ

w

40

II:
II:

C,)

w
0
0

30

w

20

:;
t!)

..:
0~

10

- --

:J

C,)

~

u

.!:'

0
4.0
5.0
6.0
Vcc. SUPPLY VOLTAGE (V)

1-64

4
6
8
10
2
I/,pc. CYCLE RATE (MHz)

Fig. 14 - REFRESH CURRENT 2
vs. CYCLE RATE
~

TA = 25°C
tRC= 120n,

w

II:
II:

--- ---

V

.!:'

Fig. 13 - PAGE MODE CURRENT
vs. CYCLE RATE

E

.... V

10

()

4.0
5.0
6.0
Vcc. SUPPLY VOLTAGE

~

TA = 25°C
Vee ~ 5.5V

C,)

w

.!:'

SO

w

:t:
w
II:

l-

Z

I/)

u.

60

II:
II:

60

:J

C,)

~

E

IZ

4

I/'RC. CYCLE RATE (MHz)

Fig. 11 - REFRESH CURRENT 1
VS. SUPPLY VOLTAGE
80

2

0

-20
0
20
40
60
80
100
T A • AMBIENT TEMPERATURE (OC)

w

V

V

II:

N
u

~

/'
/'

w

I/)

.s

TA = 25°C
Vcc = 5.5V

50

60
50

TA=25°C
Vec = 5.5V

./

40
30

:t:

I/)

w
II:

u.

20

w
II:

u;
()
.!:'

10

0

V

V

/

2
4
5
I/tRC. CYCLE RATE (MHz)

MB 81464-10 111111111111111~lllmllllllllllllllllllllllllm~
MB 81464-12 FUJITSU
MB 81464-15 1111"mlll"""~lllllllmllllllllmlmllm"

Fig. 15 - REFRESH CURRENT 2
vs. SUPPLY VOLTAGE
o T A = 2501
C
o 'Re = 230 ns
fZ
W

a:
a:

13

50

40

_VV

30

-

"'
u

.2 20

Fig. 17 -ADDRESS AND DATA INPUT
VOLTAGE vs. AMBIENT TEMPERATURE
3.0

f-

Vee

o

15.ov

2.0

II ...J

0

0

~ >
~~
> ~

1.0

0-

z
«

o

>

I~

--

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE IVI

T A =25°C

«
V ,H Mini

2.0

V ,L Maxi

I~ ~
• W

I~uf-~

2.0

V ,H 1Min)

1.0

>~

I

V ,L Maxl

0-

o

---I--

~ f-"'

lui~>6
j~

1.0

>~

z

z

«

«
I

0
-20
0
20
40
60
80
100
T A. AMBIENT TEMPERATURE lOCI

->

I

->

0

Fig. 19 - RAS, CAS, WE AND OE INPUT
VOLTAGE vs. AMBIENT TEMPERATURE

I~
o
z

25
c

V ,H Min)

U~

en
en

~6
1 a:>

w
U
U

«

• f-

=' =>

1.0

V,L (Max)

I

0-

z
«

o

-20

20

TA =25°C
Vee = 4.SV

W

::;:

i=

«(!)

>~

Fig. 20 - ACCESS TIME

Vee l5.0V

«

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE IV)

vs. LOAD CAPACITANCE

3.0

I~ ~
rn~ w 2.0
I

I

--

V ,H IMinl
r~V
~
k~Maxl

3.0

z

~~

>

r--

Fig. 18 - RAS, CAS, WE AND OE INPUT
VOLTAGE vs. SUPPLY VOLTAGE

o

0-

~6
~>
j!;

>:

(!)

I

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE IVI

~2:

~

Vl

f3 ~

W

W
Vl(!)

TA = 25°C

« ;:

60

"-

«
«

3.0

«

Vl

a:

f':
o

I

~

Fig. 16 - ADDRESS AND DATA INPUT
VOLTAGE vs. SUPPLY VOLTAGE

U

15

V

./

5

«

II:

~

/'

10

0

~

-5
0
20
40
60
80
100
T A • AMBIENT TEMPERATURE lOCI

1 00 200 300 400 500 600
CL. LOAD CAPACITANCE (pF)

1-65

~~~~II~~~II~~~~~~~IOOI MB 81464-10
PtJJITStJ MB 81464-12
~~~I~~~~lmm~llll~mll~~lm~1111 MB 81464-15

Fig. 21 - OUTPUT CURRENT
VS. OUTPUT VOLTAGE
;(

.s

Fig. 22 - OUTPUT CURRENT
vs. OUTPUT VOLTAGE

300

-150

250

.s;( -125

fZ

Vee = 5.5V

~

150

l=:l

100

.:.

50

a

~ ~ ~e=4.5V

~

0

.2

iii-lOa
a:
a:

I--

V

lI'

o
o

o

i
.2
2

3

4

5

6

:LJlI I I I I
I\.

w

"\ TA

I-w

~~

.00
:»
-3

>'"

1-66

-4

= 25'C

"- '\

gJ ~ -2

a

50

100

150

rr-...

200

"'

I'--

250

I\. "

-25

o

Vee = 4.5'>-

r-..."

0123456
V OH • OUTPUT VOLTAGE (VI

Fig. 23 - SUBSTRATE VOLTAGE
DURING POWER UP

~ C -1

~ee=5.5V

\."\1\

-50

:l

VOL. OUTPUT VOLTAGE (VI

1--

\

-75

f:l

l=

=25'~

\

f-

w 200

a:
a:

:l
<..l
f:l

,\A

300

Fig. 24 - CURRENT WAVEFORM
DURING POWER UP

:LJ?I I I I I

M'B 81464-10
MB B1464-12
MB 81464-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS

(Suffix: ·PI

18 LEAD PLASTIC DUAL·IN·LlNE PACKAGE
(CASE No.: DIP·18p·M031

D

r=====:=:::::::,1..;."15o MAX

I

.260±.010
16.60±0.25)

~::::~~~~=.;86=8~:;::~=~r:I::;22r=.0::;:5~=~r:~~=):::::::~:1
.04911.25)
MAX

.300±.010
17.62±0.251

~
.010±.002
(O.25±0.051
.047~~'211.20~~·30)

.19715.00IMAX

.11813.0IMIN
.10012.54)

I

TYP

© FUJITSU LIMITED19S5 D18011S-2C

Dimensions in
inches (millimeters)

1-67

11111~mllllll~ml~ml~1111111111111111111111 MB 81464-10
FUJITSU
1111111111111111111111111111111111111111111111111111

MB 81464-12
MB 81464-15

PACKAGE DIMENSIONS

(Suffix: -PO)

18-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC-18P-M02)

no

.490'.003
112.45,O.OB)
.527'.005
113.39'0.13)

.OOB~~~~ 10.20~~~~)
R.03010.76)TYP

.01710.43)

-~
1.02610.65)
TYP

.2B5'.003A

17.24,O.OB)

.322'.005
IB.1B,O.13)

.02010.51 )
MIN

.06011.52)

.05011.27)
TYP

MIN

©FUJITSU LIMITED 1986 C18016S-3C

Dimensions in
inches (millimeters)

1-68

MB 81464-10
MB 81464-12
MB 81464-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS
(Suffix: -PSZ)

..

(TOP VIEW)

CAS

Vss

DQ,

211

411

611

WE
BI.

NC.

10'1

A6

12"

A4

1411

A7

1611

A2

1811

Ao

2011

L~c~~~~~c~c~r~~3~~[J~3~JC~[~I~C1~~c~t~

II,
OQ3

3"

5"

7"

gil

DQ 4

OE

OQ2

RAS

1311

1111
NC.

15"

A5

1711

Vee

A3

19"
A,

20-LEAD PLASTIC ZIGZAG-IN-LiNE PACKAGE
(CASE NO.: ZIP·20P-M01)
.112±.008
12.85'0.2)

1019~:~~~ 12588~~:~~)

I:

I

I

INDEX

.260'.010
1660'025)

d

~

m",,,

10.25'0 05)

-

.05011.27)TYP

©FUJITSU LlMITED1986

~

Z20001S-3C

.020,.004
10.50±0.10)

.325J.26)MAX

~~ ~

(1
~

~3.0)MIN

1

1· 10012.54)TYP

Dimensions in
inches (millimeters)

1-69

1IIIIIIImllmmm~llm~~mlm~~~~1111 MB 81464-10
FUJITSU
1IIIImlllllllllllllllllllllll!IIIIIIIImlllllili

MB 81464-12
MB 81464-15

PACKAGE DIMENSIONS
(Suffix: -C)

DIP-1BC-A01

18-LEAD CERAMIC (METAL SEAL) DUAL IN-LINE PACKAGE
(CASE No.: DIP-1BC-A01)
==.lO°to9O

"o",",.~~: ::::i[i3]' ,: F ,
I~

.900'.010
(22.86'0.251

.1

T

.Q10::gii!
(0.25:g:6g1

~:;;;;~::o~~,
~
l--I

.100 •. 01OJ
(2.54'0.2511

J~
l

.032(0.811
RE F

.800(20.32IREF
.050'.010
(1.27,0.251

©FUJITSU LIMITED 1987 D18014S·4C

1-70

.035'.015
(0.89'0.381

.018::gg~(0.46:g:6~1
Dimensions in
inches (millimeters)

Section 2

CMOS DRAMs -

At a Glance
Maximum
Access

Page

Device

Time (na)

Capacity

Package
Options

2~

MB81C258-10
-12
-15

100
120
150

262144 bits
(262144w x lb)

16-pin
IS-pin

Plastic
Plastic

2-25

MB81C466-10
-12
-15

100
120
150

262144 bits
(65536w x 4b)

IS-pin
lB-pin
20-pin

Plastic
DIP
Ceramic DIP
Plastic
ZIP

2-41

MB81Cl000-70

70

-80

80

1048576 bits
(I04B576w x lb)

-10
-12

100
120

lB-pin
18-pin
20-pin
26-pin

Plastic
Ceramic
Plastic
Plastic

DIP
DIP
ZIP
LCC

60
BO
100

1048576 bits
(1048576w x lb)

IS-pin
lB-pin
2O-pin
26-pin

Plastic
Ceramic
Plastic
Plastic

DIP
DIP
ZIP
LCC

70
80
100
120

1048576 bits
(1048576w x lb)

lB-pin
lB-pin
20-pin
26-pin

Plastic
Ceramic
Plastic
Plastic

DIP
DIP
ZIP
LCC

60
80
100

1048576 bits
(1048576w x lb)

lB-pin
18-pin
20-pin
26-pin

Plastic
Ceramic
Plastic
Plastic

DIP
DIP
ZIP
LCC

70
BO
100
120

1048576 bits
(I04B576w x lb)

IS-pin
18-pin
20-pin
26-pin

Plastic
Ceramic
Plastic
Plastic

DIP
DIP
ZIP
LCC

60
80
100

1048576 bits
(1048576w x lb)

IS-pin
18-pin
2O-pin
26-pin

Plastic
Ceramic
Plastic
Plastic

DIP
DIP
ZIP
LCC

60
80
100
120

1048576 bits
(262144w x 4b)

20-pin
20-pin
26-pin

Plastic
DIP
Ceramic DIP,ZIP
Plastic
LCC

60
80
100

1048576 bits
(262144w x 4b)

20-pin
20-pin
26-pin

Plastic
DIP,ZIP
Ceramic DIP
LCC
Plastic

85
100
120

1048576 bits
(262144w x 4b)

20-pin
20-pin
26-pin

Plastic
DIP,ZIP
Ceramic DIP
Plastic
LCC

1048576 bits
(262144w x 4b)

20-pin
20-pin
26-pin

Plastic
DIP,ZIP
Ceramic DIP
Plastic
LCC

60
80
100

1048576 bits
(262144w x 4b)

20-pin
20-pin
26-pin

80
100
120

4194304 bits
(4194304wx lb)

IS-pin
20-pin
26-pin

Plastic
Ceramic
Plastic
Plastic
Plastic
Plastic

DIP
ZIP
LCC

80
100
120

4194304 bits
(1048576 x 4b)

20-pin
26-pin

Plastic
Plastic

DIP,ZIP
LCC

2-61

MB81 Cl000A-60

-80
-10
2-63

MB81Cl00I-70

-80
-10
-12
2-83

MB81Cl001A-60

-80
-10
2-85

MB81Cl002-70

-80
-10
-12
2-109

MB81Cl002A-60

-80
-10
2-111

MB81C4256-70

-80
-10
-12
2-135

MB81C4256A-60

-80
-10
2-137

MB81C4257-B5
-10
-12

2-161

MB81C4258-70

70

-80

80

-10
-12

100
120

2-185

MB81C425BA-60

-80
-10
2-187

MB814100

-80
-10
-12

2-207

MB814400-80
-10
-12

DIP
LCC

DIP,ZIP
DIP
LCC

2-1

CMOS DRAMs

2-2

Dynamic RAM Data Book

MB81C258-10
MB81C258-12
MB81C258-15
October 1988
Edition 3.0

262,144 x 1 BIT CMOS STATIC COLUMN DYNAMIC RAM
The Fujitsu MB 81 C258 is CMOS static column dynamic random access memory, SC-DRAM, which is organized as 262144 word by 1 bit_ This SC-DRAM is
designed for high speed, high performance applications such as main frame
memory, buffer memory, and video memory, and. for applications to battery
backed-up systems where very low power dissipation and compact layout is
required_
The advantage of SC-DRAM is achieving the static mode operation such as
read, write and read-modify-write cycles in spite of dynamic RAM and the
fast read and write operation can be performed by this mode_
The MB 81C258 is fabricated using silicon gate CMOS process. Since the
CMOS circuit dissipates very small power, it can be easily used in battery
backed-up application system such as hand held computer_
The MB 81 C258 is pin compatible with HM 51258_
Air inputs and outputs are TTL compatible.
262144 xl SC-DRAM, 16'pin
DIP/18-pin PLCC
• Silicon-gate, CMOS, single
transistor cell
• Row Access Time (tRAC),
100 ns max. (M881C258·10)
120 ns max. (M881C258-12)
150 ns max. (MB 81C258-15)
• Random Cycle Time (tRC).
200 ns min. (MB 81C258-10)
230 ns min. (M881C258-12)
260nsmin. (MB81C258·15)
• Address Access Ti me (t AA l.
45 ns max. (MB 81C258-10)
55 ns max. (MB 81C258-12)
70 ns max. (MB 81C258-15)
• Static Mode Cycle Time (tscl,
50 ns min_ (MB 81C258-10)
60 ns min. (MB 81C258-12)
75 ns min. (MB 81C258-15)

•

•

•
•
•
•
•

Low Power Dissipation
330 mW max. (MB 81C258-10)
275 mW max. (MB 81C258-12)
248 mW max. (MB 81C258·15)
11 mW max. (TTL level input)
1.65 mW max. (CMOS level input)
Single 5V supply, ±10% tolerance
32 ms1256 refresh cycles
RAS-Only, CAS-before-RAS, and
Hidden refresh capability
Standard 16-pin Plastic DI P
(Suffix: ·P)
Standard 18-pin Plastic LCC
(Suffix: -PD)

PLASTIC PACKAGE
DIP·16p·M03

PLASTIC PACKAGE
LCC:-18P·M04

PIN ASSIGNMENT
Vss
CAS

DOUT
As
A3
A4

As

A7

ABSOLUTE MAXIMUM RATINGS
Rating
Voltage on any pin relative to Vss
Voltage on Vcc relative to Vss
Storage Temperature
Power Dissipation
Short Circuit output current

Symbol
V 1N , V OUT

Value
-1 to +7

a

Unit
WE

V

Vcc

-1 to +7

V

T STG

-55 to +125

°c

Po

1.0

W

50

mA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

3

16

Dol/T

RAS

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-

mum rated voltages to this high impedance
circuit.

2-3

1111111111mlllllllllllll~111111111111111111111111 MB81C258-10
FUJITSU MB81C258-12
Imlllllllllllllllllll~III~1111111111111111111111 MB81C258-15

Fig. 1 - BLOCK DIAGRAM

CLOCK
GEN.1

I--

WRITE
CLOCK
GEN.

0

r--

I
~

L..-..-

Ao

t--

-~

-

AS

~

CLOCK
GEN.2

-

roI

SENSE AMP. &
1/0 GATE

• . • j

,--

,.-'-ROW
ADD.
BUFFER

i-...l\
r---v'

ROW
DEC.

-

'--

-I

I--

I-

:--

~

-

DATA
IN
BUFFER

COLUMN
DECODER

COLUMN
ADD.
BUFFER

·

·•

262,144 BIT
STORAGE CELL

-

DATA
OUT
_ IDOUT
BUFFER

f--

-Vee

-Vss

CAPACITANCE ITA =2SoC,f= 1 MHz)
Symbol

Typ

C 'N1

Input Capacitance, RAS, CAS, WE
Output Capacitance,

Parameter
Input Capacitance, Ao to

2-4

As

DouT

and

D'N

Max

Unit

-

7

pF

C'N2

-

10

pF

COUT

-

7

pF

MB 81C258-10
MB81C258-12 FUJITSU
MB81C258-15

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

Vcc
Vss

4.5
0

5.0
0

5.5
0

V

Input High Voltage, all inputs

V 1H

2.4

-

6.5

V

Input Low Voltage, all inputs

V 1L

-1.0

-

O.B

V

Operating
Temperature

OoC to +70°C

DC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted)
Values
Parameter

Conditions
MBB1C25B·10

Operating Current'
(Average power
supply current)

MBB1C25B·12
MBB1C25B·15

Standby Current
(Power supply
current)

TTL level
CMOS level

CAS = V IL or V 1H ,
RAS cycling;
tAc = min

Symbol

Icc1

RAS = CAS = V IH
RAS = CAS~ V cc -O;2V

Icc2

MBB1C25B·10
Static Mode
Current'

MBB1C25B·12

RAS = CAS = V IL ,
RAS cycling; tsc = min.

Icc3

MBB1C25B·15
CAS· before· RAS
Refresh Current'
(Average power
current)

MBB1C25B·10

Unit
Min

Max

-

60

-

50

-

45

-

2.0

-

0.3

-

40

-

35

-

30

rnA

-

55

-

45

-

40

-10

10

RAS cycling,
CAS-before·RAS;
tAC = min

Ic.c4

OV:;;: VIN :;;: 5.5V,
Vce = 5.5V,
Vss = OV; pins not
under test = OV

IIIL)

Output Leakage Current

OV:;;: VOUT :;;: 5.5V;
Data out disabled

lOlL)

-10

10

Output High Voltage

IOH = -5mA

V OH

2.4

-

Output Low Voltage

IOL =4.2mA

VOL

-

0.4

Input Leakage Current

MBB1C25B·12
MBB1C25B·15

mA

rnA

rnA

IJA

V

NOTE: '; Icc depends on the output load operating speed. The specified values are with the output pin open.

2-5

III!!!!!IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

FUJITSU
1111111111111111111111111111111111111111111111111111

MB81C258-10
MB81C258-12
MB81C258-15

AC CHARACTERISTICS

(At Recommended operating conditions unless otherwise noted) LI\f!it1tiii'j
Parameter

mmm

MB 81 C258-1 0

MB 81C258-12

MB 81 C258-15

Min

Max

Min

Max

Min

Max

-

32

-

Unit

Time Between Refresh

tREF

-

32

Random Read/Write Cycle Time

t RC

200

Read-Modify-Write Cycle Time

t RWC

245

-

tRAC

-

100

-

120

-

150

ns

Access Time from CAS

t cAC

-

25

-

30

-

35

ns

Output Buffer Turn off Delay Time

tOFF

0

25

0

25

0

30

ns

Transition Time

tT

3

50

3

50

3

50

ns

45

-

55

-

70

ns

-

5

-

5

-

ns

Access Time from RAS

Column Address Access Time

I1IiJ

!l1iJ

tAA

-

32

ms

230

-

260

-

ns

285

-

325

-

ns

Output Hold Time from Column
Address Change

tAOH

5

Access Time from WE Precharge

t WPA

-

25

-

30

-

35

ns

tALW

-

90

-

110

-

140

ns

Access Time Relative to last
Write

[iJ

t WOH

0

-

0

-

0

-

ns

RAS Precharge Time

tRP

90

-

100

-

100

-

ns

RAS Pulse Width

t RAS

65

RAS Hold Time

t RSH

25

CAS Pulse Width (Read)

tCAS

25

100000

30

100000

35

100000

ns

CAS Pulse Width (Write)

tCAS

15

100000

20

100000

25

100000

ns

CAS Hold Time (Read)

tCSH

100

120

-

150

-

ns

tCSH

80

-

95

-

115

-

ns

tRCO

25

75

25

90

30

tCRS

20

25

30

-

ns

tASR

0

-

0

0

ns

-

15

20

-

0

-

ns

30

-

ns

25

80

ns

Write Latched Data Hold Time

CAS Hold Time (Write)
RAS to CAS Delay Time

100000
-

75
30

100000
--

95

100000

35

ns
ns

~-

115

ns

tRAH

15

fJ
fJ

tASC

0

-

0

tCAH

20

-

25

-

IiJriJ

tRAO

20

55

20

65

Column Address Hold Time
Reference to RAS

tAR

100

-

120

-

150

-

ns

Write Address Hold Time
Referenced to RAS

t AWR

80

-

90

-

110

-

ns

Read Address to RAS Lead Time

tRAL

45

-

55

-

70

-

ns

tAHR

15

-

15

-

20

-

ns

CAS to RAS Set Up Time
Row Address Set Up Time
Row Address Hold Time
Column Address Set Up Time
Column Address Hold Time
RAS to Column Address Delay
Time

Column Address Hold Time
Referenced to RAS Rising Time

2-6

Symbol

1m

ns

MB81C258-10
MB81C258-12
MB81C258-15

AC CHARACTERISTICS (Cont'd)
(At Recommended operating conditions unless otherwise noted)

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

.,
''''*ffl!SM1

MB 81C258-10

MB 81C258-12

MB 81C258-15

Min

Max

Min

Max

Min

Max

25

70

ns

ImJ'm

Symbol

mm

t LWAD

20

45

20

55

Column Address Hold Time
Referenced to Last Write

tAHLW

90

-

110

-

140

-

ns

Read Command Set Up Time
Referenced to CAS

t Res

0

-

0

-

0

-

ns

Parameter
Last Write to Column Address
Delay Time

Unit

Read Command Hold Time
Referenced to RAS

IE

tRRH

10

-

10

-

10

-

ns

Read Command Hold Time
Referenced to CAS

IE

tRCH

0

-

0

-

0

-

ns

twp

15

-

20

-

25

-

ns

tWI

15

-

20

-

25

-

ns

t WCH

15

-

20

-

25

-

ns

35

-

ns

35

-

ns

~-

WE Pulse Width
WE Inactive Time
-Write Command Hold Time
- -

Write Command to RAS Lead
Time

t RWL

25

-

30

-

Write Command to CAS Lead
Time

tCWL

25

-

30

-

t RWD

100

-

120

-

150

-

ns

CAS to WE Delay Time

tCWD

25

-

30

-

35

-

ns

Column Address to WE Delay
Time

t AWD

45

-

55

-

70

-

ns

RAS to Second Write Delay
Time

t RSWD

105

-

125

-

155

-

ns

Write Command Hold Time
Referenced to RAS

t WCR

80

-

95

-

115

-

ns

RAS Precharge Time from Last
Write

t RPLW

135

-

155

-

165

-

ns

0

-

ns

RAS to WE Delay Time

1m

Write Set Up Time for Output
Disable

1m

tws

0

-

0

Write Hold Time for Output
Disable

IE

tWH

0

-

0

-

0

-

ns

D'N Set Up Time

tos

0

-

0

-

0

tOH

20

-

25

-

30

-

ns

D'N Hold Time
D, N Hold Time Reference to
RAS

tOHR

80

-

90

-

110

-

ns

Refresh Set Up Time for CAS
-Referenced to RAS
(CAS-before-RAS cycle)

t FCS

20

-

25

-

30

-

ns

ns

2-7

1111111111111111111111111111111111111111111111111111

FUJITSU
Illiilllllllll!1111111111111111111111111111111111111

MB81C258-10
MB81C258-12
MB81C258-15

AC CHARACTERISTICS (Cont'd)

.

(At Recommended operating conditions unless otherwise noted) iMii&llMIJ
Parameter

ImIm

MB 81C258-10

MB 81C258-12

MB 81C258-15

Min

Max

Min

Max

Min

Max

Symbol

Unit

Refresh Hold Time for CAS
Referenced to RAS
(CAS-before-RAS cycle)

t FCH

20

-

25

-

30

-

ns

CAS Precharge Ti me
(CAS-before-RAS cycle)

tCPR

20

-

25

-

30

-

ns

RAS Precharge Time to CAS
Active Time (Refresh cycles)

tRPC

20

-

20

-

20

-

ns

Static Mode Read/Write Cycle
Time

tsc

50

-

60

-

75

-

ns

Static Mode Read-ModifyWrite Cycle Time

t SRWC

95

-

115

-

145

-

ns

Static Mode CAS Precharge
Time

tcp

15

-

20

-

25

-

ns

-

520

-

610

-

ns

500

10000

ns

70

-

ns

Refresh Counter Test Cycle
Time

1m

tRTC

440

Refresh Counter Test RAS
Pulse Width

1m

t TRAS

340

Refresh Counter Test CAS
Precharge Time

II!!

tcn

Refresh Counter Test CAS to
Col. Addreso Delay Time

1m

Refresh Counter Test Access
Time from CAS
Refresh Counter Test CASto WE Delay Time

10000

410

50

-

60

tCADT

-

100

-

120

-

150

ns

1m

t CACT

-

135

-

165

-

205

ns

1m

tCWDT

135

-

205

-

ns

10000
-

165

NOTES:

o
F)

r!I

An Initial pause (RAS = CAS::: VIH) of 200.us is required after
power-up followed by any 8 RAS-only cycles before proper
device operation is achieved. In case of using internal refresh
counter, a minimum of 8 CAS-before-RAS initialization cycles
instead of 8 RAS cycles are required.
AC characteristics assume tT::: 5ns, V IN ::: OV to 3V, V 1H = 2.4V,
V ,L = O.8V, V OH = 2AV,and VOL = OAV.
Assumes that tRAD ..::; tRAD (max). If tRAD is greater than the
maximum recommended value shown in this table, tRAC will be

increased by the amount that tRAD exceeds the value shown.

n Assumes that tRAD.2: tRAD (max).

13 Measured with a load equivalent to 2 TTL loads and 100pF.

m
o Write Cycle Only.
m

jf tRAD is greater than the specified tRAD (max) limit, then
access time is controlled by tAA'

III

2-8

=

tRAH Iminl + tT (tT

=

5nsl

is specified to latch column address by the rising edge of

mRAS.

Operation within the tLWAD (max) limit insures that tALW (max)
can be met. tLWAD (max) is spec'ified as a reference point only;
jf tLWAD is greater than the specified tLWAD (max) limit, then
access time is controlled by tAA'

IE tLWAD Iminl = tCAH Iminl + tT (tT = 5nsl.
III Either tRRH or tACH must be satisfied tor a read cycle.
lEI tws, tWH, and tRWD are specified as a reference point

Assumes that tLWAD S tLWAD (max). If tLWAD is greater than
the maximum recommended value shown in this table, tALW will
be increased by the amount that tLWAD exceeds the value shown.
Operation within the tRAD (max) limit insures that tRAC (max)
can be met. tRAD (max) is specified as a reference point only;

tRAD Iminl

1m tAH R

1m

only.
If tws .2: tws (min) and tWH .2. tWH (min), the data output pin
will remain High-Z state throughout entire cycle. It tRwD ~
tRWD (min), The data output will contain data read from the
selected cell.
CAS·before-RAS refresh counter test cycle only.

MB81C258-10
MB81C258-12 FUJITSU
MB81C258-15

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

Read Cycle
tAC
tAAS
RAS

V ,HV'L-

V'HV'L-

CAS

~

~

~

x:

ADDRESSES V,H
V ,L -

f----tAP-

tCSH
tCA

~
tRAO·

:x

ROW

~tAHR

~

tAA
tRAL

1

CDLUMN

-

t - t ACS

tRCH

-

L-tCAC-tAA
tRAC

DOUT

~Ir-- tARH
I--tOFF

VOH-;.....------HIGH-Z------{~V~A~LI~O~):---_IHIGH-Z _ __

VOL

o
'; If t RAO

2

'-

tASH

-tACO

Don'tCare

tR,AO (max), access time is tAA'

Write Cycle (WE Controlled)
tRC
tRAS
RAS

CAS

II
f

V,H
V'L-

V ,HV ,L -

~

--.J

tCSH
r-tACO
J----tCAS

~ r--RDW

tAWR

I

I---tCWL----I
f--

COLUMN

I

"

I

tRWL
tWCR

tASC_
WE

V'HV'L-

DOUT

V'H- ":X:' ",,:;."(":-:;~ -,~.:,,;~,
V,L -

f I;::-- tCAH'

1
tos-

D,N

'--

1

~H

,X

-

l~tRP-

tRSH

?:- ,.~ or:]

-l

f-tWH

twp-----

I

'I:;-tOHtOHRVALIDE

tRPLW

1i/,i.',

"

2;'<":'

~

:,

'~-'

,,:

~~~---------HIIIGH-Z-----~(C~IN~V~A~L~ID~F~-------tOFF

EJ

Don't Car.

"; Write Cycle only.

2-9

111111111111mllllllllllllllll~1111111111111111111 MB81C258-10
FUJITSU MB81C258-12
I I I I I I I I I I I I I ~I I I I I I I I I I I ~ MB81C258-15

Write Cycle (CAS Controlled)
~------------------tRC-----------------------1
~-----------tRAS--------------t

RAS

V IHV IL -

CAS

VIHVIL-

DIN

VIHV IL VO H-

DOUT

VOL

---------HGH-Z·1-----------------

*1; If tws 2 tws (min) and tWH
*2; Write Cycle only.

E::D Don't Care
2

tWH (minI. DouT is high-Z.
Read-Modify-Write Cycle
-------------tRWC-------------------~

f-------------tRAS,----------I
RAS

VIH_
VIL -

CAS

VIHVIL-

WE

V IH V IL -

DIN

VIHVIL -

DOUT

VOH---------HIGH-Z------t=~V~A~L~IU~==l~---HIGH-Z---VOL
~ Don'teare

*. Invalid Data

2-10

MBB1C25B-10 1111111111111111111111111111111111111111111111111111
MB81C258-12 FUJITSU
MB81C258-15 1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImi

Static Mode Read Cycle
~------------------tRC----------------------~
~-------------tRAS----------------~

RAS

V IH _ ----~I
V IL -

tc RS

tCSH-------'-'--t
tAR

tcp

tRCO-+----f

V IH -

---+-++---,,1

VI L-

tRAO

11---+----\

V IH - ---,.}--'-.,['-U...I.L.--,."."...,..,[,r---q..........L-....,.Jr-...J.I____--I..,[,,......I.......-ADDRESSES V IL- ..............;......4;.;;,;.~-',..,...--~·~....;..;~ F~;;.....-'1~...,.,-----r-'f'........,......-VIH-~----'--~-+---_+~-~r_+r-~~~-------~--

VI L - _

.............._.;,-_1

VOH- _ _ _ HIGH_Z
VOL

D

Don't ears

*; Invalid Data.

Static Mode Write Cycle

RAS

V IH V IL -

CAS

V IH V IL -

ADDRESSES V IH - ---V:~-:V-V~:-:-::_::_::_I:-{.,......"""'I~_:_:_L~~I~~~::77:::-:-:-~J....,V_J..--..J...
VIL-----4~~~~~~~...........J}rr~~~I~'~~~~~~r-T"""-_r-

WE

DIN

DOUT

VIH------+-.....,jJ
V IL -

V IHV IL V OHVOL

-------------HIGH-Z*---------------

D
*. If tws

Don'tear.

~ tws (min) and tWH ~ tWH (min!. DouT is high-Z.

2-11

11111111111111111111111111111111111111111111111111

PVJITSV
1111111111111111111111111111111111111111111111111111

MB81C258-10
MB81C258-12
MB81C258-15

Static Mode Read·Modify·Write
r------------------tRc----------------------~
r------------------tRAS----------------~

WE

D,N

VIHVIL-

V 1H -

,

V1L-

f::J Don't Car.
[SS)

Invalid Data

Static Mode Mixed Cycle' 1
RAS

f-------------------tRc'-----------------------i
r--------------'t RAS
4.

----------------i,___

V1H-

V'L-

CAS

WE

VIHVIL-

VtHVIL -

D,N

°OUT

V1HVIL - .

VO H-

VOL

C1SJ Don't Care
£SS)lnvalid Da..

"; This is an example of static mode mixed cycle.
*2; If tLWAD is satisfied its minImax value, tALW = tsc (min) + tAA (max)

2-12

MB81C258-10
MB81C258-12
MB81C258-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

RAS·Only Refresh Cycle
(Note; WE, DIN = Don't Care, As = V IH or V IL I

tRC
tRAS

~
tASR

ADDRESSES V IH(Ao-A7)
V IL-

-

I--

f--tRAHi

l

-H

tRP

l'

ROW

~tRPC
t

I

tCRS

~F
HIGH·Z

DOUT

I

D

Don't Care

CAS·before·RAS Refresh Cycle
(Note; Address, WE, DIN = Don't Carel

i-------tRC---------1
i----tRAS----i

r---------~
tFCS

DOUT

I~----------~

I"f---------------~I

VOH-==)----------HIGH.Z----------------------------V
OL

2-13

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB81C258-10
MB81C258-12
MB81C258-15

Hidden Refresh Cycle
r-----------tRC----------~

RAS

CAS

WE

VIHVIL -

VIHVIL-

VIH-----~----~r-~~--------~------------~~~----~~

VIL-------,....,I
tOFF

DOUT

VOH------HIGH-Z-----t=====~VA~L~I~D~D~A~TA~=====~

VOL-

D

Don'teare

CAS-before-RAS Refresh Counter Test Cycle
tRTC
RAS

V 1H VIL-

tTRAS

i

_tRP_

I'FCS i--'FCH
CAS

lr-- tCPT-

VIH- ~
V 1L-

-ff
I tCAOT.

I.

(Read)

I~ ~~H

tRCH

1..

tAA

r--tCA~

f--j tOFF
VALID

'RCS

(Write)

.., t

-'RWL~

tAwol--I--tCWOT- - ' C W L
twp
'os-

,,:'c: ;,'

,;

I
I

~
VALID J( ,
I

2-14

X

COLUMN

HIGH-Z

E

WE

~tAHR

J,

r

WE

DOUT

'---

'""

o

Don't Car.

,-""

MB81C258-10
MB81C258-12 FUJITSU
MB81C258-15

1111111111111111111111111111111111111111111111111111

1111111111111111111111111111111111111111111111111111

DESCRIPTION
Address Inputs:
A total of eighteen binary input address
bits are required to decode anyone of
the 262,144 storage cells within the
MB 81C258. Nine row address bits
are established on the address input pins
(Ao to As) and latched with the Row
Address Strobe (RAS). The nine column
address bits are established on the ad·
dress input pins (Ao to As) after the
Row Address Hold Time has been satis·
fied. In read cycle, the column address
are not latched by the Column Address
Strobe (CAS), so the column address
must be stable until the output becomes
valid. In write cycle, the column addresses are latched by the later falling
edge of CAS or WE.
Write Enable:
Read or Write cycle is selected with the
WE inputs. A high on WE selects read
cycle and low selects write cycle. The
write operation is asserted on the later
falling edge of CAS or WE (Both CAS
and WE are low). The time period of
the write operation is determined by
internal circuit, thus next write opera-

tion will be inhibited during the write
operation.

Data Input:
Data is written into the MB 81 C258
during write or read-modify-write cycle.
The input data is strobed and latched by
the later falling edge of CAS or WE.
Data Output:
The output buffer is three state TTL
compatible with a fan out of two standard TTL loads. Data out has the same
porality as data in. The output is in high
impedance state until CAS is brought
low. In a read cycle, the access time is
determined by the following conditions:
1. tRAe from the falling edge of RAS.
2. tAA from the column address inputs.
3. t eAe from the falling edge of CAS.
When both tReD and tRAD satisfy their
maximum limits, tRAC=tRCO+tCAC or

data is internally latched by the later
falling edge of CAS or WE and remains
valid internally until either returns to
high.
Static Mode:
The static mode operation allows continuous read, write, or read-modifywrite cycle within a row by applying
new column address. In the static mode,
CAS can be kept low throughout static
mode operation. The following four
cycles are allowed in the static mode.
1. Static mode read cycle;
In a static mode read cycle, the
access time is tRAe from the falling
edge of RAS or tAA from the
column address input. The data
remains valid for a time t AOH after
the column address is changed.
2. Static mode write cycle,
In a static mode write cycle, the
data is written into the cell triggered
by the later falling edge of CAS or
WE. If both tws and tWH are greater
than their minimum limits, the data
output pin is kept high impedance
state through the static mode write
cycle.
3. Static mode read-modify-write cycle;
In the static mode read-modify-write
cycle, WE goes low after t AWD from
the column address inputs and
tewD from the falling edge of CAS.
The data and column address inputs
are strobed and latched by the falling
edge a of WE.
4. Static mode mixed cycle,
In the static mode, read, write, and
read-modify-write cycles can be
mixed in any order.
In the next read cycle of static mode
write cycle or read-modify-write cycle,
the access time is determined by the
following conditions.
1. tALw from the falling edge of
WE at previous write cycle.
2. tAA from the column address inputs.
3. tWPA from the rising edge of WE at
the read cycle.
4. teAe from the falling edge of CAS.

tRAe~tRAD+tAA

.
Data output remains valid while the
column address inputs are kept constant. However, when CAS goes high,
the output returns to high impedance
state. In the static mode, the output

Refresh:
Refresh of dynamic memory cells is
accomplished by performing a memory
cycle at each of the 256 row addresses
(Ao to A7) at least every 4ms.

The MB 81 C258 offers the following
three types of refresh.
1. RAS only refresh;
The RAS-only refresh avoids any
output during refresh because the
output buffer is high impedance state
due to CAS high. Strobing of each
256 row address (Ao to A7) with
RAS will cause all bits in each row
to be refreshed. During RAS-only
refresh cycle, (either V'H or V'L)
is permitted to As.
2. CAS-before-RAS refresh;
CAS-before-RAS refreshing available
on the MB 81 C258 offers an alternate refresh method. If CAS is held
low for the specified period (t Fes )
before R AS goes low, on ch ip refresh
control clock generator and the
internal refresh address counter are
enabled, and an internal refresh
operation is executed. After the refresh operation, the refresh address
counter is automatically incremented

in preparation for the next CASbefore-RAS refresh.
3. Hidden refresh;
A hidden refresh cycle will be
executed while maintaining latest
valid data at the output pin by
extending the CAS low time. For the
MB 81C258, a hidden refresh cycle
is CAS-before-RAS refresh. The
internal refresh address counter provides the refresh address, as in a
normal
CAS-before-RAS
refresh
cycle.
CAS-before-RAS refresh counter Test:
A special timing sequence using CASbefore-RAS refresh counter test cycle
provides a convenient method of verifying the function of CAS-before-RAS
refresh activated circuitry. After the
CAS-before -RAS refresh cycle, if CAS
goes to high and goes to low again while
RAS is held low, the read and readmodify-write cycles are enabled according to the state of WE. This is shown in
the CAS-before-RAS counter test cycle
timing diagram. A memory cell address,
consisting of a row address (9 bits) and
a column address (9 bits), to be accessed
is shown below.
ROW ADDRESS - 8its Ao to A7 are
provided by the refresh counter. The

2-15

1111111111111111111111111111111111111111111111111111

FUJITSU
II!I!!IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

MB81C258-10
MB81C258-12
MB81C258-15

bits As is set high internally.
COLUMN AODRESS - All the bits Ao
to As are provided by externally
after t CADT •
The recommended procedure of CAS·
before-RAS refresh counter test cycle is
shown below. The timing of CASbefore-RAS refresh counter test cycle
should be used.
1) Initialize the internal refresh address

counter by using eight CAS-beforeRAS refresh cycles.
2) Throughout the test, use the same
column address.
3) Using a write cycle, write Os to all
256 row addresses.
4) Using
CAS-before-RAS
refresh
counter test cycle in read-modifywrite mode, read the 0 written in
step 3), and simultaneously write a 1

to the same cell. This step is repeated
256 row address generated by internal refresh address counter.
5) Using a normal read cycle, read back
the 1s written in step 4), from all
256 locations.
6) Complement the test pattern and
repeat step 3). 4). and 5).

Fig. 2 - CURRENT WAVEFORM (Vcc = 5_SV, TA = 2S0C)

RAS/CAS Cycle
RAS ~
CAS

«E

Hidden Refresh Cycle

RAS only Refresh Cycle

Static Column Mode Cycle

,-

-

200

U 150
~

100

J

50
1-

2-16

.IA

lJV L U I\-l)' r\.

j\

.~
Il
IV \ ~ IL)AJ IV UP\[A

I - -I-

1DOns/DIvIsion

MB81C258-10
MB81C258-12 FUJITSU
MB 81C258-15 Illillllllllllllllllllllllllllllllllllllllllllllllll
1111111111111111111111111111111111111111111111111111

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - NORMALIZED ACCESS TIME (tRAcl
vs SUPPL Y VOLTAGE
w
::;;

w

= 25°C

TA

~1.2

'"

w

~

1.1

«
D

~ 1.0

::;

«

~ 0.9

Ve~= 5.0J

::;;

i= 1.2
~

Fig. 4 - NORMALIZED ACCESS TIME (tRAC)
vs AMBIENT TEMPERATURE

(Jl

w

~1. 1

«

~

V
./

D

~ 1.0

"'-r-...

..J

«

::;; 0.9 f--.-"
a:

o

D

Z

z

«
If-

«
If4~

5~

S~

-20

Vee SUPPLY VOLTAGE (VI

Fig. 5 - NORMALIZED ACCESS TIME (tAA)
vs SUPPLY VOLTAGE
w

TA

i= 1.2

~

w

~ 1.1

«
D
~

I~

~

«

::;; 0.9
a:

o
z

.;:0.8

~
4.0

- - ---

~

-- -

'" """

w
~1.1

«

V

D

100

",..

,.....

./

~1.0

..,/

::;

«

::;; 0.9
a:

o

z.0.8

«

~

S.O

5.0

-20

0

20

40

60

80

100

T A • AMBIENT TEMPERATURE (OCI

Fig. 8 - OPERATING CURRENT
vs SUPPLY VOLTAGE
~60

Ve~ = 5.5~

.s

;:::501---TA = 25°e

TAL5Q C

I- 50 f- tRe =

z

Z

I

200n.

w

w

a:
a: 40

lli 40

::::>

::::>

u

Cl 30

V ...

z
i=

~ 20
w

/

./

V

u

~ 30

i=

«
a:2 0

V ~

0..

o
'1 0
U

.2

0
2

V

j...--"

w

U

.2

80

Vce= 5.0V

Fig. 7 - OPERATING CURRENT
vs CYCLE RATE

~ 10

60

i=1.2

Vee SUPPLY VOLTAGE (VI

E

40

(Jl
(Jl

1.0

«

20

Fig. 6 - NORMALIZED ACCESS TIME (tAA)
vs AMBIENT TEMPERATURE
::;;

~-

0

T A • AMBIENT TEMPERATURE (OCI

w

= 25°C

::;

_s0

~

uO.8

• 0.8
u

::;;

V

4

litRe. CYCLE RATE (MHzI

o

4.0

5.0

6.0

Vee SUPPLY VOLTAGE (VI

2-17

MB81C258-10
MB81C258-12
MB 81C258-15

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

_ 60

Fig. 9 - OPERATING CURRENT
vs AMBIENT TEMPERATURE

Fig. 10 - TTL STANDBY CURRENT
vs SUPPL Y VOLTAGE
~

Ve~=5.5J
E
;: 50 _ tRe=200n.
«

TA~25°CI

..s
~ 5
w

Z

w

~ 40

a:
a: 4

:::>

()

:::>

()

~ 3

Cl 30

z
1=
~ 20

o
Z

f--

w

~

2

..J

Q.

o, 10
U
2 0

t:

1

2

0

-20 0
20
40
60
80
100
T A• AMBIENT TEMPERATURE (OC)

TA~25oel

~500~~---r--+---~-+--~
w
a:
a:

:::> 4001---+---+---+---1---+---1

()

~300~-+---+---+---~-+--~

Z

Fig. 12 - STANDBY CURRENT
vs AMBIENT TEMPERATURE

Ve~ = 5.5V

~

..s

5

fZ

~ 4
a:

~2001---+---+---+---1---+---I
(I)

~

3

o

~ 2

f-

o

(I)

~100r-~~~__+---r-~o--~
N

N1
u
2

0 '---f::----'---;:-i::---'--"""",,:---..J
4.0
5.0
6.0
Vee SUPPLY VOLTAGE (V)

-20

0
20
40
60
80 100
TA. AMBIENT TEMPERATURE (OC)

Fig. 13 - REFRESH CURRENT 1
vs SUPPLY VOLTAGE
60
~
E
TA 25°CI
:- 50 -tRe = 200n.

J

fZ

~ 40

a:

:::>
() 30
J:

(I)

w

,....,.,,-

.,...., ,....,.

~ 40

a:

./

:::>
() 30
J:

w

a: 20

20

ll.
W

a:

a:

M 10
u

M 10
u
2
4.0

5.0

6.0

Vee SUPPLY VOLTAGE (V)

--- -

fZ

(I)

w

o

Fig. 14 - REFRESH CURRENT 1
YS CYCLE RATE
60
~
I
E
- 50 r-Vee = 5.5V
TA = 25°C

~

2-18

-

III

«

2

i"""

:::>

>-

[t

f...- f...-

4.0
5.0
6.0
Vee SUPPLY VOLTAGE (V)

Fig. 11 - CMOS STANDBY CURRENT
vs SUPPLY VOLTAGE

Jl

--

~

o

,

./

,,/

V

"

4
5
2
litRe. CYCLE RATE (MHz)

MBB1C258-10
MB81C258-12
MB81C258-15

Fig. 15 - STATIC COLUMN MODE
CURRENT vs CYCLE RATE
;;: 60

.s

~ 50
w

I

;;: 60

.s 50

-- ~

f-

zw

0:

0:
0: 40

u

u

!5 40
w

w

030
:;;

030

o

:;;

--

~ 20

«

Q.

.2

o

.. l--- .......
4

8

12

~ 20

f..-' I-

«
Q.

';10
u

.2

16

20

o

1/tse. CYCLE RATE 1M Hz)

Vee = 5.5J
-T A =25'C

I----

fZ

~ 40

~ 40

20

0:

.2

~I'

./

:E

w

0:

--I----

ui 10
u

2

o

4

4.0

5.0

6.0

Fig. 20 - ADDRESS AND DATA INPUT VOLTAGE
vs AMBIENT TEMPERATURE

3.0
TA =1 25,C

IMi~.) V"
....
V ~V
I

z >
«-

«

0: f-

..J

0

« >
,;. !; 1.0

V IH

.~

3.0

~
o

Vee l5.0V

0_

Z >

« -

~ ~ 2.0

w

o0:
o

V 1H (Min.)

«
f..J

0

« >
,;. !; 1.0

....... VIL IMax.)

> ~
o z

VIL IMax.)

> ~

o -

z

«

~

...I--" ~

r--

Fig. 19 - ADDRESS AND DATA INPUT
VOLTAGE vs SUPPLY VOLTAGE

~ ~2.0

>

20

~

Vee SUPPLY VOLTAGE IV)

0-

w

~

./

"..

1/tRe. CYCLE RATE IMHz)

~
«
o

o

V

I

.2

o

o

u 30

V

w

itll0

::>

~

I

Vl

u

TA l25'c
tRe = 200ns

0:

::>
u 30

w

6.0

l

'" 50

0:

:E

5.0

;;: 60

.s

l

fZ

4.0

Fig. 18 - REFRESH CURRENT 2
vs SUPPL Y VOLTAGE

- 60

'" 50

-

~

~V

Vee SUPPLY VOLTAGE IV)

Fig. 17 - REFRESH CURRENT 2
vs CYCLE RATE

.s«

1

tse 50ns
TA = 25'C

::>

o

,;10
u

FUJITSU
1111111111111111111111111111111111111111111111111111

Fig. 16 -STATIC COLUMN MODE
CURRENT vs SUPPLY VOLTAGE

J

Vee = 5.5V
TA=25'C

1111111111111111111111111111111111111111111111111111

0

4.0

5.0

6.0

Vee SUPPL Y VOLTAGE IV)

«
J:
:>
-20
0
20
40
60
80
100
T A. AMBIENT TEMPERATURE I'C)

2-19

MB81C258-10
MB81C258-12
MB 81C258-15

1111111111111111111111111111111111111111111111111111

FUJITSU
11111111111111111111I1111111111111111111111111111111

Fig. 21 - RAS, CAS AND WE INPUT VOLTAGE
vs SUPPLY VOLTAGE
3.0

I~
z
oO: >

I~
u

3. 0

TA~25'C

o

I~

C1

. «

I a:~

~
0
. >

-i- ~1.0

-'
..........-

~ ~
«
r
:> o

(~in.) V
~V

-

V 1L (Max.)

z-

oO: ~
w2.0

I~u

C1

I ~a:

0

~

VIL (Max.)

. >

~~1. 0
~ ~

J,

:>
4.0

5.0

0
-20

6.0

~

/'
/'

00:

5

0
-5

20 I-- TA = 25'C -

V

~ 15

en
~ 10
u
u

«

/"

~

5

j
<1

0

-

100

100 200 300 400 500
C L , LOAD CAPACITANCE (pF)

IV

a:

a

150

I-

::>

:=::> 100
o

::,

.E

5o

!J

01[

n

V

/
200

/
300

1/

400

500

CL, LOAD CAPACITANCE (pF)

Fig. 26 - OUTPUT CURRENT
vs OUTPUT VOLTAGE

I-

15 -100~4...-+-+--1--+--j
a:

Vee=4.5V

aa:

YI

_75I---I'\r--"IoI----I---I--+--l

I-

::>

:=

::>

-50 I--+--~~l---

o

:i:

-251--+--+~-+-'...-1--+--l

.E
1

2

3

5

VOL, OUTPUT VOLTAGE (V)

2-20

100

Vee = 5.5V

1/

15a: 20v

80

I

TA = 25'C

.E 25 0
I-

7

1/
-5

Fig. 25 - OUTPUT CURRENT
vs OUTPUT VOLTAGE
~

_.

w
I-

/'"

$-

60

Fig. 24 - ACCESS TIME (tAA) vs LOAD
CAPACITANCE

]
.;

~
~ 10

<1

40

1

u

U

20

Ve~ = 4.5 V

vee = 4.5J
TA = 25'C

15

«

0

T A , AMBIENT TEMPERATURE ('C)

l

w

1-----

00:

Fig. 23 - ACCESS TIME (tRAC) vs LOAD
CAPACITANCE

20

VIH Min.)

.00:

Vee SUPPLY VOLTAGE (V)

]

Vee l= 5.0J

o

V 1H

;;;2.0

Fig. 22 - RAS, CAS AND WE INPUT VOLTAGE
vs AMBIENT TEMPERATURE

o
VOH, OUTPUT VOLTAGE (V)

MB81C258-10
MB81C258-12 FUJITSU
MB 81C258-15 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII!IIIIIIIIIIIIIII
1111111111111111111111111111111111111111111111111111

Fig. 28 - CURRENT WAVEFORM
DURING POWER UP (2)

Fig. 27 - CURRENT WAVEFORM
DURING POWER UP (1)

>-...J2:
UJ 5
:lc:J
en..:
8~ 0

>~
~

>- E

...J -

it I:lz

3

-

~

I--

~

....

:lc:J
en..:
.1U...J

uO

TA = 25°C
RAS = CAS = O.8V ITTL V1LI

0

f-- I--

f--

~

T A =25°C
I

RAS = CAS = 5V
ICMOS VIHI

~.s

it

I:lz

RAS = CAS = ov

.cr:
Ucr:

It---ICMOS V1LI

enUJ

ITTLV~

L/:

O~

~

Ks=Ls=~.4V

1':0

5

»

/l

2

enUJ
U~ 1
U

>-S:
8:: W

...J-

Q.
Q.

U

I

·1 \ I

1':0

0

~

200J,Ls/Division

200,us/Division

FUNCTIONAL TRUTH TABLE
Clock Input

Address Input

Data

Operation Mode
RAS

CAS

WE

Row

Column

Input

Output

Standby

H

H

X

X

X

X

High·Z

Read Cycle

L

L

H

Valid

Valid

X

Valid

Write Cycle

L

L

L

Valid

Valid

Valid

High·Z*l

Static Mode Read Cycle

L

L

H

Valid*2

Valid

X

Valid

Static Mode Write Cycle

L

L

L

Valid*2

Valid

Valid

High·Z*l

Static Mode Mixed Cycle

L

L

L/H

Valid*2

Valid

Valid

High·Z or Valid

RAS·only Refresh Cycle

L

H

X

X

X

High·Z

Valid

X: Don't Care H: High level L: Low level
Note: *,:
*2:

If tws < tWS(minl and tWH < tWH (min), the data output become invalid.
After first cycle, row address is not necessary.

2-21

1111111111111111mllllllllll~111111111111111111111 MB81C258M10

FUJITSU

MB81C258M12

1IIIIIIIIIIIIIIIIIIIIImllllllllmllllllm~~111 MB 81C258M15

PACKAGE DIMENSIONS
(Suffix: -PI
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No_: DIP-16P-M03)
INDEX-'

I

.300±.010
(7.62±0.251

.260 •. 010

INDEX-2

!---O"H"or"L"

~ Invalid Data

Write Cycle (Early Write)

__________~I~========~~=~tR~C======~~----1
t
tRAS
RAS

VtHV'L-

tCSH
teAs
~

ADDRESSES

V'HV'L-

V'HV'L-

HIGH-Z

O"H"or"L"

2-49

MB81C1000-70
MB81C10Q0..80
MB81 C1 000-1 0
MB81C1000-12

Read-Write/Read-Modify-Write Cycle
r------------------------------tRwC----------------~------~

~---------------------tRAS------------------~ ~------~

--tCSH

~--------------tRSH--------------~
----4-----------tCAS----------------~

CAS

;....4-----

VIH __ --1.-+-1------,1,___,.
V IL -

ADDRESSES V IH -

WE

DOUT

V'L-~~~~~~ID.
VIH-~

___

........,..---,

VI L -

..........~~.....,..,

V OH -

---+-----

V OL --

V'IH _ ,..,.,....-_.".-.,.","""'_.._-,....--..,."..---__... ~,.,.,..,...,..".,"- , - - - - - - - V IL -

..........-

..........-

..........- - - - - - -......-

......J1';....:::::::...::~'-......- - - - -........

O"H"or"L"
~ Invalid Data

Fast Page Mode Read Cycle

1---------------------- tRAS·-----------------·--------i

VIL - '

ADDRESSES V IH -

VIH-~,....~-~-4----~~~+----++-1~---~+-----~
VIL -

.......-1-__'"

DOUT VOH- _ _ HIGH-Z:----, t RwD
(min), and t AWD ;;:: t AWD (min). the cycle is a readmodify-write cycle and data from the selected cell will
appear at the DauT pin.
If neither of the above conditions is satisfied, the cycle is
a delayed write cycle and invalid data will appear at the
DauT pin, and write operation can be executed by
satisfing tRWL, tCWL, and tRAL specifications.

O]J

tCPA is access time from the selection of a new column
address (that is caused by changing CAS from "L" to
"H"). Therefore, if tcp is long, tCPA is longer than tCPA
(max).

uring timing of input signals, Also, transition times are
measured between V IH (min) and V IL (max).
[ ] ] Assumes that tRCD :S: tRCD (max). tRAD :S: tRAD(ma
x). If tRCD (or tRAD) is greater than the maximum recommended value shown in this table, tRAC will be increased by the amount that t RCD (or tRAD) exceeds the
value shown. Refer to Fig. 2 and 3.

m

If t RCD ;::>, tRCD (max). tRAD ;::>, tRAD (max). and
tAsc ;::>, tAA -tCAC-tT, access time is tCAC'

[ ] ] If tRAD ;;:: tRAD (max) and tASC:S: tAA-tCAC-tT, access
time is tAA'
[ ] ] Measured with a load equivalent to two TTL loads and
100 pF,

OZJ RAS
Assumes that CAS-before-RAS refresh and
refresh counter test cycle only

CAS- before-

2-69

~

...

MB81C1001·70
MB81C1001·80
MB81C1001·10
MB81C1001·12

Fig. 2 - tRAC

vs

tRCD

Fig. 3 - tRAC

140

140

-;;; 120

.. 120

vs

tRAD

120n5 Version

S

S

.., 100

«
I!-

80
60

70ns Version

i i
I
I
I
I

T

I

20

I I

40

I
I
I
I

II

I

80

I

I

80 100 120
tRCO (nsl

i
I
I

T

.

I

I

I

I

I

70ns Version

60

I

I
I
I
I

"
60

u 100

«
I!-

I
I
I
I
I
I

I

20

I
I

I

I
I

I

I

I

I
I

I
II I I

30

40

I

I

50

70

.

tRAO (nsl

FUNCTIONAL TRUTH TABLE
Operation
Mode

Clock Input

Address Input

Data
Refresh

Note

RAS

CAS

WE

Row

Column

Input

Output

Standby

H

H

X

-

-

-

High·Z

-

Read Cycle

L

L

H

Valid

Valid

-

Valid

0.

tRCS 2 tRCS (min)

Write Cycle
(Early Write)

L

L

L

Valid

Valid

Valid

High·Z

0.

twcs 2 twcs (min)

Read·ModifyWrite Cycle

L

L

H->L

Valid

Valid

X->
Valid

Valid

0.

t cwo 2 t cwo (min)

RAS-Qnly
Refresh Cycle

L

H

X

Valid

-

-

High-Z

CAS·beforeRAS Refresh

L

L

X

-

-

-

High-Z

Hidden
Refresh Cycle

H->L

L

X

-

-

-

Valid

°
°
°

X; "H" or "L"
' ; It is impossible in nibble mode.

2-70

tCSR 2 tCSR (min)

Previous data is kept.

MB81C1001-70
MB81C1001-80
MB81C1001-10
MB81C1001-12

Read Cycle
~-------------------------tRC-·----------------------~
~--------------tRAS------~--------~

RAS

V IH V IL tCRP

CAS

ADDRESSES

V IH V IL -

tCSH
tRCD----~---------tRSH--------4-~

------tCAS------~ n-~r----------------

VIHVIL-

WE

VIHV IL -

V OH DOUT

VO L -

o

"H"or"L"

fL.2I

I"valid Data

Write Cycle (Early Write)
~---------------------tRC----------------------~

~----------------tRAS----------------~ ~---------J

RAS

V IH VIL-

tCSH

teAs

-cAS"

ADDRESSES

tRSH

VIHVIL-

VIHV IL -

~

V IH V IL -

DIN

DOUT

VO H VOL

HIGH-Z

O"H" or "L"

2-71

MB81C1001-70
MB81C1001-80
MB81C1001-10
MB81C1001-12

Read-Write/Read-Modify-Write Cycle
r---------------------------'RWC---------------,------~

RAS

'cf

CAS

'RAS

V'H- -----"
1\
V,L -

V'HV,L -

~\.

I..

H----+--'AWO
'RCSt-'

V,H -

DOUT

VOH --

II /

f--'RAO~
'ASCH----+--------------'RAL
1 . 1
.~ ----j'CAH

.I

V,L -

\.

AD~~~SP ;g~~~s~ J(".".. ':"""';,:.,..,,.~
'.:r.":"'··:::'="'""'' ' ,·.,....,-,......,-,·"'"' -'-H-"~

ADDRESSES V,H V,L -

WE

'RSH
'CAS

r----'RCO

..J
'At'!

1/

'CSH

".

,,"'fi

'RW~
'cwo

r---'RWL-

"""~~~--+-+r-r-------,~~:-A=:-L~--jT,: :.f~ ~t- - - ,'_O~Hf- -:. .; ~,:~ _
...

VOL I-------------'RAC ---------.-4 'OS

V'HD,N

V,L -

-yr+-+-/-r--~

1\

t----+---'AA---;

__--f_____

' -_ __

r--'CWL-

t:

'OFF

f:=:j'OH

,,""'1,---,"-.
-r'"'----.....;---.....;'"

. .'"
"VI" VALID V'",---,-,
______;....._ _ _ _ _ _ _ _ _ _ _"J'i.I DATA

o

"H"

0' "L"

!Z2l,nvalid Data

Nibble Mode Read Cycle

."H"o'"L'''

rn

2-72

InvajidData

MB81C1001-70
MB81C1001-80
MB81C1001-10
MB81C1001-12

Nibble Mode Write Cycle (Early Write)

RAS

CAS

ADDRESSES

WE

V IH _
V IL -

V 1H _

V IL -

V IH _
V 1L -

V IH V IL -

V 1H _

DIN

DOUT

V IL V OH V OL -

HIGH-Z

o

"H"o,"L"

Nibble Mode Read-Modify-Write Cycle
~--------------------------tRAS----------

RAS

V IH V 1L -

CAS

ADDRESSES

WE

DOUT

V IH V IL -

V OH V OL -

VIH'DIN

VIL--

D

uH" or "L" ~ Invalid Data

2-73

MB81C1001-70
MB81C1001-80
MB81C1001-10
MB81C1001-12

NOTE: WE,

RAS-Only Refresh Cycle
DIN = "H"or"L", Ag = V IH or V IL

VIHVIL -

RAS

ADDRESSES
(AD to AB)

CAS

VOHDOUT

VO L -

=====~~-------~IGH.Z:-------1[3 "H" or "L"

CAS-before-RAS Refresh Cycle
NOTE: Address, WE, DIN = "H"or"L"
t--------tRC--------i
t-----tRAS--~_I

RAS

V IH VILtCHR

CAS

VIHVIL -

DbuT

2-74

VO H VO L -

====~if-----------H'GH.Z:------------

MB81C1001-70
MB81C1001-80
MB81C1001-10
MB81C1001-12

Hidden Refresh Cycle

ADDRESSES

WE

(Read)

WE
(Read-ModifyWritel

m"H" or "L" rn Invalid Date

CAS-before-RAS Refresh Counter Test Cycle
RAS

VIHVll-

CAS

ADDRESSES

WE
(Read)

VIH
Vil

DOUT

WE
(Read-ModifyWrite)
V 1H
Dllil

Vil

o

"H" or "L"

m

Invalid Oat.

2-75

IfI

MB81C1001-70
MB81C1001-80
MB81C1001-10
MB81C1001-12

DESCRIPTION
Address Inputs:
A total of twenty binary input address
bits are required to decode anyone of
the 1,048,576 storage cells within the
MB 81Cl00l. Ten row address bits
are established on the address input pins
(Ao to Ag) and latched with the Row
Address Strobe (RAS). The ten column
address bits are established on the
address input pin (Ao to A9 ) and
latched with the Column Address
Strobe (CAS). All row and column
addresses must be stable on or before
the falling edge of RAS and CAS,
respectively. Since the flow through
type address latches are used, address
information at address pins are auto·
matically latched as column address
after tAAH (min) + t T.
Therefore, to get valid data within
tAAC, it is necessary to apply column
address within tAAO (max).
If t AAO :::: t AAO (max). access time is
tCAC or tAA whichever occure later.
Write Enable:
Read or Write cycle is selected with
the WE inputs. A high on WE selects
read cycle and low selects write cycle.
Data input is ignored during read cycle.
Data output is high impedance state
during write cycle.
Data Input:
Data is written into the MB 81Cl001
during write or read·modify·write cycle.
The input data is strobed and latched
by the later falling edge of CAS or WE.
In an early write cycle, data input is
strobed by CAS, and set up and hold
times are referenced to CAS. In a
delayed write or read·modify·write
cycle, WE is set low after CAS. Thus,
data input is strobed by WE, and set
up and hold times are referenced to
WE.
Data Output:
The output buffer is three state TTL
compatible with a fan out of two
standard TTL loads. Data out has the
same porality as data in. The output

2-76

is high impedance state until CAS is
brought low. In a read or read-modifywrite cycle, the output becomes valid
after tAAC from the falling edge of CAS
when tACO (max) is satisfied or after
tCAC when tACO is longer than tACO
(max). The data output remains valid
until CAS returns to high with tOH
and becomes high impedance state
after t OFF ' In an early write cycle,
the output buffer is high impedance
state during the entire cycle. In a
delayed write cycle, if t Awo or t cwo
is less than tAwo (min) or t cwo (min),
the output is invalid.
Read Cycle:
The read cycle is executed by keeping
both RAS and CAS "L" and keeping
WE "H" thr'lugh-out the cycle. The row
and column addresses are latched with
RAS and CAS, respectively. The data
output is remain valid with CAS "L",
i.e., if CAS goes "H", the data becomes
invalid with to H. During read cycle,
the D'N pin is "Don't Care". The access
time is determined by RAS (tAAcl,
CAS (tcAcl, or Column address input
(t AA ). If tACO (RAS to CAS delay
time) is greater than the specification,
the access time is t CAC ' If tAAo is
greater than the specification, the access
time is t AA .
Write Cycle:
The write cycle is executed by the same
manner as read cycle except for the
state of WE and D'N pin. The data on
D'N pin is latched with the latter falling
edge of CAS or WE and written into
memory. In addition, during write
cycle, t AWL , tCWL and tAAL must be
satisfied the specifications.
Read-Modify-Write Cycle:
The read-modify-write cycle is executed
by changing WE' from "H" to "L" after
the data appears at the DOUT pin.
After .the current data· is read out,modified data can be re-written into the same
address quickly.

Nibble Mode ReadlWrite/Read-ModifyWrite Cycle:
Nibble mode allows high speed serial
read, write, or read-modify-write access
of 2, 3, or 4 bits of data. The bits of
data that may be accessed during nibble
mode are determined by the 9 row and
9 column address bits (RAO to RA8 and
CAO to CAB). The 2 bits of addresses
(RA9 and CA9) are used to select 1 of
4 nibble bits for initial access. After the
first bit is accessed by the normal
mode, the remaining nibble bits may be
accessed by toggling CAS "H" then
"L" while RAS remains "L". Toggling
CAS causes RA9 and CA9 to be incremented internally while all other
address bits are held constant and makes
the next nibble bit available for access.
Refer to the table 1 for nibble mode
addr.ess sequence.
If more than 4 bits are accessed during
nibble mode, the address sequence will
begin to repeat.
Refresh:
The refresh of 0 RAM is executed by
normal read, write or read-modify-write
cycle, i.e., the cells on the one row line
are refreshed by executing one of three
cycles. 512 row address must be refreshed every B.2 ms period. During the
refresh cycle, the cell data connected to
the selected row are sent to sense
amplifier and re-written to the cell. The
M881Cl001 also has three types of
refresh modes, RAS-only refresh, CASbefore- RAS refresh, and Hidden refresh.

MB81C1001-70
MB81C1001-80
MB81C1001-10
MB81C1001-12

1. RAS·Only Refresh;
The RAs ·Only refresh is executed by
keeping RAS "L" and keeping CAS
"H" through the cycle. The row
address to be refreshed is latched
with the falling edge of RAS. During
RAS·Only refresh, the DouT pin is
kept high impedance state.

2. CAS·before·RAS Refresh;
The CAS-before·R-AS refresh is executed by bringing CAS "L" before
RAS. By this timing combination,
the MB 81C1001 executes CAS·
before·i=fAS refresh. The row address
input is not necessary because it is

generated internally.

3. Hidden Refresh;
The Hidden refresh is executed by
keeping CAS "L" to next cycle,
i.e., the output data at previous
cycle is kept during next refresh
cycle. Since the CAS is kept low
continuosly from previous cycle,
followed refresh cycle should be
CAS· before· R AS refresh.

Table 1 - NIBBLE MODE ADDRESS SEQUENCE
Mode

Nibble
bit

RAg

Row address
(As - Ao)

CAg

Column address
(As - Ao)

RAS/CAS

Normal

1

0

101010100

0

101010100

Toggle CAS

Nibble

2

1

101010100

0

101010100

Toggle CAS

Nibble

3

0

101010100

1

101010100

Toggle CAS

Nibble

4

1

101010100

1

101010100

Toggle CAS

Nibble

1

0

101010100

0

101010100

Sequence

--

Input address

Generated
Internally

Sequence repeats

2-77

MB81C1001-70
MB81C1001-80
MB81C1001-10
MB81C1001-12

PACKAGE DIMENSIONS
(Suffix: -PI
18 LEAD PLASTiC DUAL-iN-LINE PACKAGE
(CASE No.: DiP-18P-M04)

INDEX-'

DimensIons in
(f)

2-78

FUJITSU LIMITED 1986 D18015S-4C

inches (millimeters)

MB81C1001·70
MB81C1001-80
MB81C1001·10
MB81C1001·12

PACKAGE DIMENSIONS
(Suffix: -PJ)
PIN ASSIGNMENT
D,N

VSS

WE

°OUT

peAs
pNC
PAg

RAS
TE'
NC.

TOP
VIEW
AO
A,
A, [
A3 [
Vee [

PAa
PA 7
PA6
A5
P
PA4

26-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No.: LCC-26P-M04)

.14013.55)MAX
.08912.25)NOM

*.675±.005
117.15±0.13)

.02510.64)MIN

I

I

.30017.62) .332±.005

LJ '"T'"

No.CD

LEAO
.050±.005
11.27±0.13)

.268±.020

~0.511

"A"
R-"R'"RRRr====rArFniririD09812.50) NOM

---1 I •. 017±.0.9~

10.43±0.10)
Details of "Art part
NOTE: 1. *: This dimension includes resin protrusion, (Each side: .006(O.15)MAX)
2. Although this package has 20 leads only, its pin positions are the same as that of 26-lead package.
101989 FUJITSU LIMITED C26054S·1C

Dimensions in
inches (millimeters)

2-79

MB81C1001-70
MB81C1001-80
MB81C1001-10
MB81C1001-12

PACKAGE DIMENSIONS
(Suffix:-PSZ)

PIN ASSIGNMENT

(TOP VIEW)
CAS
2"

vss
4"

WE
(io

fl--l..c:::re:U;~"i--J.

III
Ag

3"

511

DOUT

DIN

TE'
8..

NC
10,1

Al

A3

12"

1I'p

A4
16 p

A6

As

18 11

20,1

J: J"L-:a.t"_Tt: l. c.:r t:. :I.e:r c.:t.r..::r r..:l1:' .J"t:"'J. .c:r~-..L
7 11
gil 11" 13 11 1511 1711 1911

RAS

NC

AO

A2

Vee

As

A7

20-LEAD PLASTIC ZIG-ZAG IN-LINE PACKAGE
(CASE No_: ZIP-20P-M02)

_387±.013

~''''

.010±.002
(O.25±0.05)

LEAD

_050(1.27)
TYP

J

~_I

_020±_004
(O.50±0_10)

-,.:,-10:::,0:..:.(2:::.:=:54c")-,:T-::y.;-.p+-1
(ROW SPACE)

NO-CD

~
@

(01988 FUJITSU LIM ITED Z20002S-4C

2-80

.118(3.pO)MIN

Dimensions in
inches (millimeters)

MB81C1001-70
MB81C1001-80
MB81C1001-10
MB81C1001-12

PACKAGE DIMENSIONS
(Suffix: ·C)

DlP·18C·A01

18·LEAD CERAMIC (METAL SEAL) DUAL IN·LlNE PACKAGE
(CASE No.: DIP·18C·A01)

.010~:gg~
10.25~g)~1

.100±.010
(2.54±0.251
.800(20.32)REF

©1987 FUJITSU LIMITED D18014S·4C

Dimensions in
inches (millimeters)

2-81

CMOS DRAMs

2-82

Dynamic RAM Data Book

cO

October 1989
Edition 1.0

FUJITSU

DATA SHEET

MBS1 C1 001 A-601-BOI-10
CMOS 1,048,576 BIT NIBBLE MODE DYNAMIC RAM
CMOS 1,048,576 X 1 Bit Nibble Mode Dynamic RAM
The Fujitsu MB81 C1001A is CMOS fully decoded dynamic RAM organized as 1,048,576 words x
1 bit. The MB81C1OO1A has been designed for mainframe memories, buffermernories, and video
image memories requiring high speed, high-banp width output with low power dissipation, as well
as for memory systems of handheld oomputers which need very low power dissipation.
Fujitsu's advanced thr8lKiimensionai stacked capacitor cell technology makes the MB81 C1001 A
High a-ray soft error immunity and long refresh time.
The CMOS circuits can be used as peripheral circuits. In addition, low power dissipation and high
speed operation are realized.

DIP-18P-MD4

PRODUCT LINE & FEATURES

DIP-18C-A02

• 1,048,576 words x 1 bit organization
• Silicon gate, CMOS, 3D-Stacked
Capacitor Cell
• All input and output are TIL oompatible
• 512 refresh cycles every 8.2 ms

• Common VO capability by using early write
• RAS only, CAS-before-flAS, or Hidden
Refresh
• Nibble Mode, Read-Modify-Write
capability
• On chip substrate bias generator for high
performance

LCC-26P·M04

ZIP-20P-M02

NOTE:

Permanent device damage may oc:cur if the above Absolute Maximum RatIngs are '-;;;;:;;::;;::::;:;::;;:;:;:;:;:::;::::::;:;:;;;:::;::::::.::::;:;::;;:;~
exceeded. Functional operation should be restricted to the conditions as detailed in the I"'ThI dovfco tal Ir"
h I
In
operational sections oflhis data sheet. Exposure to absolute maximum rating oonditions
Ii'~ :.a~ ~~ ~r· .\'.:~ rold:~
for extended periods may affect device reliability.
=1~~S:::Y~:'~='::x~~~~
vo"_ to thle high Irr!>odoiIce Clrcul.

d":' d:;:'

.

COpyr\lht© 1989 by FUJITSU LIMITED

2-83

CMOS DRAMs

IfJ

2-84

Dynamic RAM Data Book

cP

November 1989
Edition 1.1

FUJITSU

DATA SHEET

MB81 C1 002-701-801-101-12
CMOS 1,048,576 BIT STATIC COLUMN MODE DYNAMIC RAM
CMOS 1,048,576 X 1 BIT Static Column Mode Dynamic RAM
The Fujitsu MB81 C1002 is CMOS fully decoded dynamic RAM organized as 1,048,576 words x 1
bit. The MB81 C 1002 has been designed for mainframe memories, buffer memories, and video
image memories requiring high speed, high-bend widlll output with low power dissipation, as wei
as for memory systems of handheld computers which need very low power dissipation.

\\t\l\\~

\p\\\\\\I\\\\t:l

Fujitsu's advanced IIIree-dimensional stacked capacitor ceH technology makes 1heMB81C1002
High (X-ray soft error immunity and long refresh tima,
The CMOS circuits can be used as peripheral circuits. In addition, low power dssipation and high
speed operation are realized.
The specification is applied to 'BC' version revised willi intent to realized faster access time. So
faster speed version (7Ons and SOns) are available on this chip.

DIP-18P-M04

PRODUCT LINE & FEATURES

DlP-18C-A01

• 1,048,576 words x 1 bit organization
• Silicon gate, CMOS, 3D-Stacked
Capacitor Cell
• All input and output are TIL compatible
• 512 refresh cycles every 8.2 ms

• Common I/O capability by using early write
• liAS only, CAS-betora-l'iAS, or Hidden
Refresh
• Static .coIumn Mode, Read-Modily-Write
capaaty
• On chip substrate bias generetor for high
performance
LCC-26P-M04

ABSOLUTE MAXIMUM RATINGS (see NOTE)

NOTE:

ZlP-20P-M02
Permanent device damage may occur if lIIe above Absolute Maximum Ratings are ~:;;:;::;:;:;;;~:;:;~:;;;;;:;;=.;:;;:;~
exceeded. Functional operation should be restricted to lIIe conditions as detailed in lIIe r Thl device tal circuM 10
I UbI aI I
operational sections of this data sheet Exposure to absolute maximum rating conditions
duo~ ~
vollagao
fOr extended periods may affect device reliability.
~=,:':~~~n:.~:=~::'':',,::,:

d.:..a.

•..:

_'ho

or ':'00'.:.

vol\agellO this high ",*anco clleul.
Copyrlght© 1989 by FUJITSU LIMITED

2-85

MB81C1002-70
MB81C1002-80
MB81C1002-10
MB81C1002-12
Fig. 1 - MB81C1002 DYNAMIC RAM-BLOCK DIAGRAM

DIN

AO

A1
A2
A3

A4
A5

AS
A7

AS

-Vee

A9

-Vss

CAPACITANCE

(TA= 25°C, f= 1MHz)

Input Capacitance, AO to A9, D IN

5

pF

Input Capacitance, Ms, CAS, WE

5

pF

5

pF

Output Cso;scita.nce.

2-86

COUT

MB81C1002-70
MB81C1002-80
MB81C1002-10
MB81C1002-12

PIN ASSIGNMENTS AND DESCRIPTIONS
26-Pln SOJ:

18-Pln DIP:

-

(TOP VIEW)

(TOP VIEW)

----..
DIN

[

1

'WEe

2

RAS[

3

M

e•
e

A1

[

S

A2 [

7

A3 [

Vee [

TE

18

:J

Vss

17

]

DOUT

16

J'CAs

15

JAg

5

J

AS

13

]

A7

12

J

AS

8

11

J

A5

9

10

"

[

1

WE[

26

V 55

2

25
2.

OOUT

TE

[

NC.

[

•

DIN

RAS[

3
5

CAs

23

NC .

22

Ag

........

Q~¥igij~w6.

PM

AO

[

9

18

A8

DIN

A,

[

10

17

A7

11

1S

DOUT

A2 [

As

A3 [

12

vcc [

13

,. P
15

20-Pln ZIP:

..Ii

Data Input.
Data Output.

A5

WE

Write Enable.

A.

RAS

Row address strobe.

NC

No connection.

AOto A9

Address inputs.

(TOP VIEW)

CAS

V

ss

VCC

'WE

TE

NC.

A,

A3

A.

As

A8

~rtUnU~U~Un~~utiU~li~U~~
1"
3"
5"
7"
g"
11"
13'
15"
17"
19"
I

A 9 DOUT

DIN

RAS

NC.

Ao

A2

VCC

A 5

A 7

TE

+5 volt power supply.
Test Enable (will be available).

CAS

Column address strobe.

VSS

Circuit ground.

RECOMMENDED OPERATING CONDITIONS

Input High Voltage, all inputs

VIH

2.4

6.5

V

Input Low Voltage, all inputs

VIL

-2.0

0.8

V

2-87

MBS1C1002-70
MBS1 C1 002-S0
MBS1C1002-10
MBS1C1002-12

FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty input bits are required to decode any one of 1,048,576 cell addresses in the memory matrix. Since only ten address bits are available, the
column and raw inputs are separately strobed by ~ and"R)(S as shown in Figure 1. First, nine row address bits are input on pins AO-through-A9
and latched with the row address strobe (RAS ) then, ten column address bits are input and latched with the column address strobe(~ ). Both raw
and column addresses must be stable on or before the falling edge ofm and RAS , respectively. The address latches are of the flow-through type;
thus, address information appearing after IRAH (min)+ IT is automatically treated as the column address.

WRITE ENABLE
The read or write mode is determined by the logic state of WE . When WE is active Low, a write cycle is initiated; when WE is High, a read cycle is
selected. During the read mode, input data is ignored.

DATA INPUT
Data is written into the MBa 1C1002 during write or reacl-modily-write cycle. The input data is strobed and latched by the later falling edge o~ or
WE. In an early write cycle, data input is strobed by"CAS , and set up and hold times are referenced to"CAS . In a delayed write or reacl-modily-write
cycle, WE is set low after "CAS. Thus, data input is strobed by WE, and set up and hold times are referenced to WE.

DATA OUTPUT
Theth~tate buffers are TTL compatible with

a fanout of two TIL loads. Polarity of the output data is identical to that of the input; the output buffers
remain in the high-impedance state until the column address strobe goes Low. When a read or reacl-modily-write cycle is executed, valid outputs are
obtained under the following conditions:

tRAC:

from the falling edge of"RAS when tACO (max) is satisfied.

tCAC:

from the falling edge of "CAS when tACO is greater than tACO, tRAD (max).

tAA

from column address input when IRAo is greater then tRAO (max).

:

STATIC COLUMN MODE OF OPERATION
The static column mode operation allows continuous read, write, or reacl-modily-write cycle within a rowby applying new column address. In the static
column mode,"RAS can be kept low throughout static column mode operation.

2-88

MB81C1002-70
MB81 C1 002-80
MB81C1002-10
MB81C1002-12

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)

Input leakage current

(any input)

I I(L)

Output leakage current

IO(L)

Operating current
(Average power
supply current)

ICC,

Standby current
(Power supply
current)

ICC 2

Refresh current
#1 (Average power
supply current)

ICC.

Static column mode
current

ICC.

Refresh current
#2 (Average power
supply current)

ICC 5

G

G
G

G

OV :5: VIN :5: 5.5V;
4.5V:5: VCC S 5.5V;
VSS=OV;AII other pins
not under test =OV
OV :5: VOUT:5: 5.5V;
Data out disabled

Notes 3

-10

10
jJ.A

-10

10

RAs & CAs cycling;

mA

tRC= min

RAS=CAS=VIH

2.0

AAs=CAS ~ VCC-O.2V

1.0

mA

CAs=VIH,RAS
cycling; tAC= min

mA

RAS = CAS =VIL
cycling; tsc = min

mA

RAscyciing;
CAS-before-RAS;

mA

tRC =min

2-89

MB81C1002-70
MB81 C1 002-80
MB81C1002-10
MB81C1002-12

AC CHARACTERISTICS

33

2-90

DIN Hold Time

tOH

20

20

20

25

ns

MB81C1002-70
MB81 C1 002-80
MB81C1002-10
MB81C1002-12

AC CHARACTERISTICS

(Continued)

2-91

MB81 C1 002-70
MB81C1002-80
MB81C1002-10
MB81C1002-12
Notes:

1. Referenced to VSS
2.

Icc depends on the output load conditions and cycle rates; The
specified values are obtained with the output open.
Icc depends on the number of address change as1t!iS = VIL and
~=VIH.
ICC1, ICC3 and Iccs are specified at three time of address change
during liAS = VIL and ~ = VIH.
1CC4 is specified at one time of address change during liAS = VIL
and ~=VIH.

3. An Initial pause (1t!iS =~ =VIH) of 200~ is required after
power-up followed by any 8 liAS ~nly cycles before proper
device operation is achieved. In case of using internal refresh
counter, a minimum of 8 ~ -before-liAS initialization cycles
instead of 8 liAS cycles are required.
4.

AC characteristics assume h = 5ns

5.

V IH (min) and V IL (max) are reference levels for measuring
timing of input signals. Also, transition times are measured

6.

12. IRCO (min) = tRAH (min)+ 2t T + lAse (min).
13. Operation within the tRAD (max) limit insures thatlRAc (max) can
be mel. tRAO (max) is specified as a reference point only; iftRAD
is greater than the specified IRAD (max) limit, access time is
controlled exclusively by tCAC or t AA .

16. Assumes thattLWAD a'i tLWAD (max). IftLWAO is greater than the
maximum recommended value shown in this table, tAWL will be
increased by the amount that!LwAD exceeds the value shown.
17. tAHR

is specified to latch column address by the rising edge of

1t!iS .
18. Operation within the ILWAD (max) limit insures thatlAwL (max) can
be mel. tLWAD(max) is specified as areference point only; iftLwAD
is greaterthan the specifiedtLWAD (max) limit, then access time is
controlled by 1M.

between VIH (min) and VIL (max).

19.

ILWAD (min) = ICAH (min) + tr (IT=5ns).

Assumes that tRCO :;, tACO (max), and tRAD :;, tRAO (max). If

20.

tws, tWH and tRwD are specified as a reference point only. Iftws

tRcO (ortRAo) is greater than the maximum recommended value

" tws(min) and tWH" tWH(min), the data output pin will remain
High-Z state through entire cycle. If It IRWD ~ tRwo(min), the
data output will contain data read from the selected cell.

shown in this table, tRAC will be increased by the amount that
tRCO (or IRAO) exceeds the value shown. Refer to Fig. 2 and 3.
7. Assumes that write cycle only.
8.

If IRAO ~ IRAD (max), access time is t AA

9.

Measured with a load equivalent to two TTL loads and 100 pF.

10. IOFF is specified that output buffer change to high impedance
state.

11. Operation within the tRCD (max) limit insures that IRAC (max)
can be mel. tRCO (max) is specified as a reference point only; if
IRCO is greaterthan the specified tRCO (max) limit, access time is
controlled exclusively by !cAC or I AA .

2-92

21.

Assumes that CAs -before-RAS refresh, CAs -before-"RAS
refresh counter test cycle only

MB81C1002-70
MB81C1002-80
MB81C1002-10
MB81C1002-12

Fig. 2 -

t RAC (ns)

Fig. 3 -

t"AC VS. IRCD

t RAC (ns)

160

t"AC VS. IRAD

160
140

140

120

120

100

100

80

80ns Versio

80

80ns Version I

--Y+1-+ 70ns Version

70ns Versior

60

1:

-(!

I
I I
I I

40

60
t

RCD

8

100

120

I I
I I

II

60

II II
20

I
I

kill,! I

•

20

40

60

80

100

120

•

t RAD (ns)

(ns)

FUNCTIONAL TRUTH TABLE

L
L

L
L

L
H-)L

Valid

Valid

Valid

Valid

Valid

Valid

X-)
Valid

Valid

Static Column Mode
Read Cycle

L

L

H

'2
Valid

Valid

Static Column Mode
Write Cycle

L

L

L

'2
Valid

Valid

Static Column Mode
Read-Modify-Write Cycle

L

L

H-)L

'2
Valid

Static Column Mode
Mixed Cycle

L

L

UH

'2
Valid

RAS-<)nly
Refresh Cycle

L

H

X

Valid

CAS-before-RAS
Refresh Cycle

L

L

H-)L

L

Hidden Refresh
Cycle

0

t RCS '" t RCS (min)
t RCH '" 1 RCH (min)

'1
High-Z

0

tws '" Iws

Valid

0

Valid

X

Valid

'1
High-Z

X

Valid

X-)
Valid

Valid

X

Valid

Valid

High-Z
or Valid

X

High-Z

0

X

High-Z

0

X

Valid

0

(min)

t CWD ",I CWD (min)
t RCS '" t RCS

t RCH '"

t RCH

(min)
(min)

(min)

t CWD '" t CWD

Previous data is
kept

Notes:
X: "H"or"L"
'1: If tws < tws (min) and tWH < tWH (min), the data output become invalid.
'2: After first cycle, row address is not necessary.

2-93

MB81C1002-70
MB81 C1 002-80

MB81 C1 002-1 0
MB81C1002-12

TIMING DIAGRAMS
Fig. 4 - READ CYCLE

tRAS

VIHVIL-

RAs

\CSH
lASH
teAS

VIHVIL-

CAs

"I

tRAL

Ao

10

A9

WE

VIHVIL_

VIHVIL-

1M
tCAC
tRAG

Dour

VOHVOL_

HIGH·Z
j..--tON

II

'1; If tRAD ~ tRAD (max), access time is \CAC or 1M whichever occur later.

'H"or"L"

DESCRIPTION
The read cycle is executed by keeping both 'RAS and~ "L" and keeping~ "H" through out the cycle. Therow and column addresses are
latched with"RAS and~, respectively. The data output remain valid with
"L", i.e., if~ goes "H". the data becomes invalid with bH.
During read cycle, the DIN pin is "H" or "L". Theacces time is determined by ro\'S(RAC), ~(tCAC), or Column address input(IM). If tRCD(roiS
to CAS delay time) is greater than the specification, the access time is tAO or 1M whichever occur later.

ro

2-94

MB81C1002-70
MB81 C1 002-80
MB81C1002-10
MB81C1002-12

Fig, 5 - WRITE CYCLE (Early Write)

~-----------------------tRC
_ ____________~~~--------------tMS
~

VIH-VIL--

1------------ leSH

"CJrn"

Ao

to

A9

VIH-VIL--

v,,-VIL--

VALID
DATA IN

...... ...
~:

:.;.:.".:.:.:.:.:.:.:.:".:.:.:.".:.:.:.:.:.:.:.:.:.:.:':':':".:.:.:.:.:.:.:.:.:..-:;:.:':::::':;:::'::::::::::::::::::::::::::::::;:~:::::::.:.:.:.....,

....... .

lfff ;::=;=::::;:;:;:::=!::::::=:::=:=:=:=:=:=}:=:::=::H::::::f}}:=::f::::::!:trttt:ttrr:nr:(::::;::;:;:;:;:::::::::::::::.;.:::

'I
Dour VOH-- --------------------------------HIGH-Z~-------------------------------VOL--

'1; If tws ~ tws (min) and twH~ twH (min), Dour is high-Z.

11*;;'1

'H'or'L'

DESCRIPTION
The write cycle is executed by the same manner as read cycle except for the state ofWE and DIN pin. The data on DIN pin is latched with the
later falling edge of C~ WE
written into memory. In addition, duringwrite cycle, IRWL, leWL and tML must be satisfied the specifications.

ana

2-95

MB81C1002-70
MB81C1002-80
MB81C1002-10
MB81C1002-12

Fig" 6 - READ WRITE/READ-MODlFY-WRITE CYI4-"C.:;;cLE::......_ _ _ _ _ _ _ _ tRWC

RAS

VIHVIL-

~-------------------t~

~-----------------~H
---...,_-----tRsH
VIH_

CAS

AotoAe

1+----- leAS

VIL-

VIHVIL-

WE

DIN

VIHVIL-

VIHVIL-

DOUT

VOHVOL-

L-t:--t:I
I-

VALID DATA
toN

1*;1
DESCRIPTION
The read-modify-write cycle is executed by changing M from High to low after the data appears on the DOUT pin.
This new data is written into the same address as read oul.

2-96

"H"or"L"

MBB1C1002-70
MBB1C1002-BO
MBB1C1002-10
MBB1C1002-12

Fig" 7 - STATIC COLUMN MODE READ CYCLE

14------------ IRC ----------....-.J
VH_

RAS

--~_r_-------IRAS

Vll-

VIHCAS
Vll-

An

VIHtoAg

W-IWE
Vll-

DOUT

VOHVOl-

II

"H".,"l"

2-97

MB81C1002-70
MB81 C1 002-80
MB81C1002-10
MB81C1002-12

Fig. 8 - STATIC COLUMN MODE WRITE CYCLE
~

________________________ tRC ________________________~

VIH-

RAS

VIL-

CAS

At! to As

VIHVIL-

WE

VI-I-

DIN

VI-I-

VIL-

VIL-

DOUT

VOHVOL-

'I
- - - - - - - - - - HIGH-Z - - - - - - - - - - - - - - - -

'1; If tws~ tws (min) and IWH~ twH (min), DoUT is high-Z.

DESCRIPTION
In a static column mode write cycle, the data is written into the cell triggered by the later falling edge or&S or"WI:. It is not necessary to bring
both ~and CAS"L", only one signal should be brought"L" while the other signal is toggled. If both ws and IWH are greater than their minimum
limits, the data output pin is kept high impedance state through the static column mode write cycle.

2-98

MB81C1002-70
MB81C1002-80
MB81C1002-10
MB81C1002-12

Fig. 9 - STATIC COLUMN MODE READ-MODIFY-WRITE CYCLE
~-------------------------t~
RAS

VIHVIL-

CAS
VIL-

Ao'DAB

WE

VIHVIL-

DIN

VIHVIL-

Dour

VOH-

VOL----------t

'1; II tLWAD (min)~

ILw~

tLWAD (max), IALW = ISO (min) + IAA (max).

DESCRIPTION
In the static column mode reac:J..modity-write cycle, 'Wt: goes low after I!.WD from the column address inpulS and tWD lrom the Ialing edge 01

~. The data and column address in uts are strobed and latched b the lallin ed e ol~.

2-99

MB81C1002-70
MB81 C1 002-80
MB81C1002-10
MB81C1002-12

Fig. 10 - STATIC COLUMN MODE MIXED CYCLE *1
~

VIH_

____

_______________________

t~

________________________~

~lr~-------------------t~

VILtRP

VHVIL-

Ao

10

A.

VIHV,L-

IWH

WE

V,HVIL-

DIN

VIHVIL-

Dour

VOHVOL-

I

J~
11M

WRITE CYCLE

READ CYCLE

READ-MODIFY-WRITE CYCLE

't; This is an example of static column mode mixed cycle.
'2; If ILWAD is satisfied its minimax value, IALW = tse (min) + 1M (max)
DESCRIPTION
In the static column mode, read, write, and read-modify-write cycles can be mixed in any order.
In the next read cycle of static column mode write cycle or read-modify-write cycle, the access time is determined by the following conditions.
1. tALW from the falling edge ofM or ~atprevious write cycle.
2. 1M from the column address inputs.
3. IWPA from the rising edge of WI: at the read cycle.
4. !cAe from the falling edge of C1!S.

2-100

MB81C1002-70
MB81 C1 002-80
MB81C1002-10
MB81C1002-12
Fig. 11 - FiAS-oNLY REFRESH CYCLE
NOTE: A9, WE, DIN = " H " or " L "

AD to As

DOUT

VOH -VOL

________

~

I!IWI·H·or·L·

DESCRIPTION

Refresh of RAM memory cells is accomplished by performing a read. a write, or a read-modify-write cycleat each of 512 row addresses every
8.2-milliseconds. Three refresh modes are available: RAS-only refresh, llAS-befor&-'RAS refresh, and hidden refresh.
'RAS- 5.5V;
Data out disabled

-10

10

-10

10

RAS & CAS cycling;
Icc,

rnA

tRC = min

[!]

Standby current
(Power supply
current)

TIL level

2.0
ICC2

CMOS level

Refresh current #1
(Average power
supply current)

Icc3

Fast Page Mode
current

1CC4

[!]

[!]

RAs = CAS

~ Vee --O.2V

rnA
1.0

RAs" cycling;

rnA

FiAs =VIL, CAs cycling;

rnA

CAs = VIH,
tRC = min

tpc = min

1-----1

Refresh current #2
(Average power
supply current)

[!] I - - - - - - i

RAS cycling;
CAs-before-RAs;

65
rnA

tRC = min

2-115.

MBS1C4256-70
MBS1C4256-S0
MBS1C4256-10
MBS1C4256-12

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Notes 3, 4, 5

2-116

MBB1C4256-70
MBB1C4256-BO
MBB1C4256-10
MBB1C4256-12

AC CHARACTERISTICS (Continued)

Notes:
1. Referenced to V••
2. Icc depends on the output load conditions and cycle rates; The
specified values are obtained with the output open.
Icc depends on the number of address change as "R7iS = VIL
and ~=VIH.
Icc., Icc3 and Iccs are specified at three time of address change
during "RAS = VIL and ~ = VIH.
1= is specified at one time of address change during "RAS =
VIL and ~ = VIH.
3. An Initial pause ("RAS =~ =VIH) of 200J.lS is required after
power-- tRCD (max), tRAD:'> tRAD (max). If tRCD is
greater than the maximum recommended value shown in this
table, tRAC will be increased by the amount that tRCD exceeds
the value shown. Refer to Fig. 2 and 3.
7.

Assumes thattRco<: tRCO (max), tRAD<: tRAD (max). If tASC<:
tAA - tCAC -

8.

t T , access time is tCAC.

IftRAD<:tRAD (max)andtAsc:'>tM -tCAC -tT,access time is
tM

Measured with a load equivalent to two TTL loads and 100 pF.

10. tOFF and tOEZ is specified that output butter change to high
impedance state.

14.

or t AA

.

Either tRRH or tRCH must be satisfied for a read cycle.

15. twcs is specified as a reference point only. If twes <: twcs
(min) the data output pin will remain High-Z state through entire
cycle.
16. Assumes that twes < twcs (min)
17.

Either tDZC or tDZO must be satisfied.

18. tePA is access time from the selection of a new column address
(that is caused by changing ~ from "L" to "H"). Therefore, if
tcp is shortened, tCPA is longer than tCPA (max).
19.

Assumes that ~-before-"RAS refresh, ~-before-"R7iS
refresh counter test cycle only.

2-117

MB81C4256-70
MB81C4256-80
MB81C4256-10
MB81C4256-12

Fig. 2 - I RAC va. "'co

t RAC (ns)

Fig. 3 - I RAC va. "'AD

160

I RAC (ns) 160

140

140

120

120

100

100

80

80

'OOffi'~./

lOOns Version

~

80ns Version

I
I
II

60

1:

20

40

=1Fit

60

60

100

120

..

I

"'t:

70ns Version

II I I
II I I
I III I I

20

40

60

I RCD (ns)

80

100

120

..

t RAD (ns)

FUNCTIONAL TRUTH TABLE
Standby

H

H

X

X

High-Z

Read Cycle

L

L

H

L

Valid

Valid

Write Cycle
(Early Wrile)

L

L

L

X

Valid

Valid

Write Cycle

L

L

L-)H

Valid

Valid

'RAS-only
Relresh Cycle

L

H

X

X

Valid

L

L

X

L

X

Valid

0

tACS"tRCS (min)

Valid

High-Z

0

twcs"twcs (min)

Valid

Valid

0

High-Z

0

X

High-Z

0

tcsA"tWCSR (min)

L

Valid

0

Previous data
is kept.

Read-Modify-

CAS-beforeRAS Refresh
Cycle
Hidden Refresh

X; "H"or'L"
'; It is impossible in Fast Page Mode

2-118

MBS1C4256-70
MBS1C4256-S0
MBS1C4256-10
MBS1C4256-12

TIMING DIAGRAMS
Fig. 4 - READ CYCLE

~----------------------- I RC
~----------------tR~

RAS

~----------------- tCSH

---"*....-------

I RSH

I CAS -------....,
CAS

r

V'H-

WE

V'L-

1~.~-------7----~tRAC
DO
(Output)

DO
(Input)

VOH VOL _

lCAC

-------7-----.;
ir------.J

- - - - - - - HIGH-Z.....:-----~__cJ

t

i~

V'HV'L_

OZC

____ HIGH-Z _'"""':"_ _ _ _.;...._ _

~

V'HOE

V'L-

..

toza

~~~~~~~~~~~~~~---~~~~~~~~~

1..II

DESCRIPTION
To implement a read operation. a valid address is latched in by the

DE

RAs

and

CAs

address strobes and. with

WE

set to a High level and

set to a low level. the output is valid once the memory access time has elapsed. The access time is determined by

CAS

 t RGD (max). access time. t CAG.
I RAD > t RAD (max), access time .. t AA.

OE

• If
is broughllow after I RAe. f CAG • or t AA (which ever occurs later). access lime - tOEA
goes High, the output returns to a high-impedance state aner t OH Is satisfied.
.

2-119

MB81C4256-70
MB81 C4256-80
MB81C4256-10
MB81 C4256-12

Fig. 5 -

EARLY WRITE CYCLE (OE

= "H" or "L")

I RC
I RAS

V1H _

RAS

V1L -

~I

ICSH
I RSH

I RP

I CAS

V1H -

CAS

V1L I RAL

V1H -

AotoAs

V1L -

WE

DO

VALID
DATA IN

(Inpul)

DO

VOH

-

(OUlpUI) VOL -

-------------------------------HIGH-Z------------------------------I;;milll

DESCRIPTION

WE Is set to a Low state and Oe isa -H" or -L·slgnal. A write cycle can be lfT1)iementad
Oe write (delayed write). 01' read-rnodify-wrlte. During all write cycles, timing parameters t RWL ,

Awrile cycle is similar to a read cycle except

In either of three ways - early write,
I CWL and
edge of

2-120

CAs

t RAL must be satisfied. in the early write cycle shown above 1 WCS
and written Into memory.

satisfied. data on the DO pins Is latched with the failing

"H" or "L'

MBS1C4256-70
MBS1 C4256-S0
MBS1C4256-10
MBS1C4256-12

Fig. 6 - DE (DELAYED WRITE CYCLE)

~-------------------------------------tRC
V,H -

i'iAs

V,L -

V,H -

CAs

V,L -

V,H -

Ao to A

B

V'L -

V ,H -

WE

V'L-

V ,H -

DO
(Input)

V'L-

DO
(Output)

VOH VOL -

V'HV ,L -

DE

I~j]:l: : :l:[fl:l ~H· or ML·
•

DESCRIPTION
In the

OE

Invalid Dara

(delayed write) cycle. t WCS is nOl satisfied; thus, the data on the 00 pins Is latched with the failing edge of WE and written Inl0

memory. The Output Enable

(oe )signal must be changed from Low 10 High belora We

goes Low (I OED + t OS ).

2-121

MB81 C4256·70
MB81C4256·80
MB81C4256·10
MB81C4256·12

Fig, 7 - READ-MODIFY-WRITE-CYCLE

t Rwe

V 1H -

RAS

CAs

V 1L -

V 1H V 1L - ,

V 1H _

AotoA 8

V 1L -

WE

V 1H V 1L _

DO

V 1H -

(Input)

V 1L -

DO

VOH -

(Output)

VOL -

V 1H -

OE

V 1L -

II? I

DESCRIPTION
The read-modlfy-write cycle Is executed by changing
cycle,

WE:

from High to low after the data appears on the 00 pins. In the read-modify-write

Oe must be changed from Low to High after the memory ~cess time.

2-122

'W or "L'

MB81C4256·70
MB81 C4256·80
MB81C4256·10
MB81C4256·12

Fig. 8 - FAST PAGE MODE READ CYCLE

DO
(Input)

DO
(Output)

OE

V 1H V 1L -

V OH
VOL

V 1H V 1L -

tjij]j]:1:]j):1:::1

"H" or"L6

t~:>::>~l

Valid Data

DESCRIPTION
The fast page mode of operation permits faster successive memory operations at multiple column locations of the same rOW' address. This
operation is performed

by strobing in the row address and maintaining "RAs

at a Low level and

WE at a High level during aU successive

meroory cycles in which the row address is latched. The access time is determined by t CAC • t AA • t CPA • or tOEA • whichever one
is the latest in occuring.

2-123

lID

MBS1C4256-70
MBS1C4256-S0
MBS1C4256-10
MBS1C4256-12

Fig. 9 -

RAS

= "H" or "L")

V 1H V 1L

CAS

FAST PAGE MODE WRITE CYCLE (OE

-

V 1H V 1L _

WE

DO
(Input)

DO

VOH

(Output)

VOL

-------------HIGH-Z------------

1:1
DESCRIPTION
The fast page rmde write cycle Is executed In the same manner as the fast page mode read cycle excepl1he states of
Data appearing on the DO pins is latched on the failing edge of
lhe delayed

2-124

(OE )write and read-rmdlfy-wrifa cycles,

CAs

We

and

De

are reversed.

and written Into memory. During the fast page mode write cycle. Including

I CWL musl be satisfied.

'H"",'L"

MBS1C4256-70
MBS1C4256-S0
MBS1C4256-10
MBS1C4256-12

Fig. 10 -

FAST PAGE MODE OE WRITE CYCLE

V 1H -

RAS
V 1L -

V 1H -

CAS

V 1L _

V 1H -

AotD A 8
V 1L -

V 1H -

WE

V 1L _

DO

V 1H -

(Input)

V 1L -

V OH

DO
(Output)

VOL

V 1H -

OE
V 1L -

I::::::[@;ii:i:il MH" or"L"
•

Invalid Data

DESCRIPTION
The fast page mode

WE

and

DE.

OE:

(delayed) wr~e cycle is executed in the same manner as the fast page mode wrHe cycle except for the states of

Illlut data on the 00 pins are latched on the falling edge 01

DE must be changed from Low to High before WE goes Low (I OeD

WE and wrinen into memory. In the fast page mode

delayed wrHe cycle,

+ t OS),

2-125

MB81C4256-70
MB81 C4256-80
MB81C4256-10
MB81C4256-12

Fig. 11 - FAST PAGE MODE READ-MODIFY-WRITE CYCLE

V 1H

-

V 1L

-

WE

V 1H
V 1L

_

DO

V 1H

-

(Input)

V1L

-

Aoto A 8

DO
(Output)

VOH VOL -

V 1H

-

V 1L

-

OE

DESCRIPTION
During last page mode of operation, the read-rrodily-wrlte cycle can be executed by switching WE from High to Low after input date appears at
the DO pins during a normal cycle.

2-126

II

"H"or"L"

(:::>,::>1

Valid Data

MB81 C4256-70
MB81 C4256-80
MB81C4256-10
MB81C4256-12

Fig. 12 --

RAS-ONL Y REFRESH (WE

=OE ="H" or "L")

~--------------------

DO

VOH

(Output)

VOL

t RC

--------------------~

----------------~._----------------HIGH-Z-----------------------

DESCRIPTION
Refresh of RAM memory cells is accomplished by performing a read. a wr~e. or a read-modify-wr~e cycle at each of 512 row addresses every
8.2-milliseconds. Three refresh modes are available: RAs-only refresh. CAs-before--AAS refresh. and hidden refresh.
AAS=-only refresh is performed by keeping

RAS

Low and

CAs

High throughout the cycle; the

row address to be refreshed is latched on the

famng edge aiMS. During AAS-onty refresh, 00 pins are kept in a high-Impedance state.

Fig. 13 -- CAS-BEFORE-RAS REFRESH (ADDRESSES

roiS"

~

DO

= WE = OE = "H" or "L")

V 1H - V 1L - -

V 1H - V 1L - -

V OH

HIGH-Z

(Output) VOL

DESCRIPTION
refresh is an on-chip refresh capability thai elimnates the need for external refresh addresses. fICAS is held Low for the
specified setup time ( I eSR ) before
goes low, the on-ch~ refresh control clock generators and refresh addres,s counter are enabled. An
internal refresh operation automatically occurs and the refresh address counter is internally incremented in preparation for the next
CAS -befote-AAS refresh operation.

CAS--before..::RAS

RAS

2-127

MB81 C4256·70
MB81 C4256-80
MB81C4256·10
MB81C4256·12

Fig. 14 - HIDDEN REFRESH CYCLE

joO-------- t

V 1H -

RAS

----oL i"'1----

RC

-------101....-----

t RAS

V 1L -

V 1H -

CAS

V 1L -

Ao to A B

V 1H V 1L _

V 1H -

WE

V 1L -

DO

V 1H -

(Input)

V 1L -

>iiCjl>-------~------------------HIGH-Z----------~--~

V OH

DO
(Output)

VALID DATA OUT
VOL

V 1H V 1L _

OE

DESCRIPTION
A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the actJve time of
cycling

RAS.

that is required by DRAMs that do not have C'As--belore-RAs refresh capability.

2-128

CAS and

The refresh row address is provided by the o!H;hip refresh address counter. This eliminates the need for the external frm address

MBB1C4256-70
MBB1C4256-BO
MBB1C4256-10
MBB1C4256-12

Fig. 15 - CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE

"RAS"

V 1H V 1L -

t RSH
teAS
~

Ao to A •

V 1H V 1L -

V 1H V 1L -

WE

V 1H -

(Read)

V 1L -

DO

V 1H -

(Input)

V 1L -

DO

Voo

(Output)

VOL

OE

V 1H V 1L -

nMiiiii]

-H- or "L·

I,:>:;;:::..J

Valid Dala

DESCRIPTION
A special timing sequence using the CAs-before-flAs refresh oounler test cycle provides a convenient method to verify the functionality of
CAS-before-AAS refresh

circu~ry. If. aller a C'AS4lefor~As refresh cycle,

CAS makes a transition from High to Low while

RAS Is

held Low, read and write operations are enabled as shown above, Row and column addresses are defined as follows:
Row Address: Bits AO through AS are defined by the on-chip refresh counter.
Column Address: Blls AO through AS are defined by latching levels on AO-M at the second failing edge of
The CAS-before-RJ\S Counter Test Cycle is designed for use with the following procedures:
• Initialize the internal refresh address counter by using eight

'CAs-oetore-RAS

CAs.

refr8lh cycles.

•

Use the same column address throughout the test.

•

Wr~e

•

Read zeroes wr~ten in procedure :3 and check; aimu~aneously write ones (1s) to the same addresses by using

zeroes (OS) to all 512 row addresses at the same column address by using normal early wr~e cycles.

internal refresh counter test read-wrlte cycles. Repeat this procedure 512 times with addresses generated
by the Internal refresh address counter.
•

Read and check data written in procedure 4 by using normal read cycle for all 512 memory iocaJions.

•

Complement test panern and repeat procedures 3, 4, and 5.

2-129

MBS1C4256-70
MBS1C4256-S0
MBS1C4256-10
MBS1C4256-12

PACKAGE DIMENSIONS
(Suffix : -PI
20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-20P-M03)

RJ={
IH IPJ~
I
,
050(1.27)
MAX

,

'

V

i--- .10012.5~
TYP

© 1988 FUJITSU LIMITED o20011S-1 C

2-130

u

H

~

H

HH
U

~

II 018+.006
~.002

Lt~i
-

.19715.00) MAX
.125p.181 MIN

.02010.51) MIN

1045 ~ gb~)

Dimensions in
inches (millimeters)

M BB1 C4256-70
MBB1 C4256-BO
MBB1C4256-10
MBB1 C4256-12

PACKAGE DIMENSIONS

(Continued)

(Suffix: -C)
20-LEAD CERAMIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-20C-A03)

_::.::,,1

~ It :;"'; :)1 ~I~+~'

.300±.010
17.62±0.251

jJ

L

.

124.S9±0.251

J]
LtJ L
J

0 ,09 0

~~Tf

0 10+·004
-.002

1025~g6~1

.20015.0SIMAX

134~g~~

1340~gj~1

.100±.010
12.54±0.251

.047~g~~03210.SlI

·(1.20~g:~~1

L-l~ -032~g16

10.S1~g~~1

REF

.SOOI20.32IREF--

+.005

-

+0.13

.018. 003 1046 -0.081
Dimensions in
inches (millimeters)

© 1988 FUJITSU LIMITED D20Q12S·2C

2-131

MB81C4256-70
MB81 C4256-80
MB81C4256-10
MB81 C4256-12

PACKAGE DIMENSIONS (Continued)
(Suffix : -PJ)
26-LEAD PLASTIC LEADED CHIP CARRIER (SOJ-26)
(CASE No.: LCC-26P-M04)
.140(3.SS)MAX
.089(2.2S)NOM
*.675±.005
(17.15±0.13)

.02S(0.64)MIN

I

LEAD No.CD
.OSO±.OOS
(1.27±0.13)

I

.300(7.62) .332±.005

Ll "T'"

.268±.020

~o.Sl)

TYP
.600(lS.24)REF

"'A"'

.098(2.S0)NOM

~

I

.017±.004
(0.43±0.10)

Details of A" part
/I

NOTE: 1.• : This dimension includes resin protrusion. (Each side: .006(0.lS)MAX)
2. Although this package has 20 leads only. its pin p~sitions are the same as that of 26-lead package.
01989 FUJITSU LIMITED C260648·1C

2-132

Dimensions in
inches (millimeters)

MB81C4256·70
MB81 C4256·80
MB81C4256·10
MB81C4256·12

PACKAGE DIMENSIONS

(Continued)

(Suffix : -PSZ)
20-LEAD PLASTIC ZIG-ZAG IN-LINE PACKAGE
(CASE No.: ZIP-20P-M02)

112± 008
12.8S ± 0.20)

I

d

INDEX

0

I

.33S±. 010
IS.SO±O.2S)

~nrn~ftffi~~~~~
.D10±.002
10.2S±0.OS)
.OSOI1.27)
TYP

J

.387±.013
19.83±0.33)

~~-~

.11SI3.oo) MI N

--.l
.10012.S4) TYP
IROW SPACE)

LEADNO.~

~L-~~~IB~OT-T~O-M~
© 1988 FUIITSU LIMITED Z20002S-4C

Dimensions in
inches (millimeters)

2-133

CMOS DRAMs

2-134

Dvnamic RAM Data Book

cO

October 1989
Edition 1.0

FUJITSU

DATA SHEET

MB81 C4256A-601-BOI-1 0
CMOS 1,048,576 BIT FAST PAGE MODE DYNAMIC RAM
CMOS 262,144 x 4 BIT Fast Page Mode Dynamic RAM
The Fujitsu MB81 C4256A is CMOS fully decoded dynamic RAM organized as 262,144 words x 4
bits. The MB81 C4256A has been designed for mainframe memories, buffer memories, and video
image memories requiring high speed, high-band width output with low power dissipation, as well
as for memory systems of handheld computers which need very low power dissipation.
Fujitsu's advanced three-dimensional stacked capacitor cell technology makes the MB81 C4256A
High IX4ay soft error immunity and long refresh time.
The CMOS circuits can be used as peripheral circuits. In addition, low power dissipation and high
speed operation are realized.

DIP-20P-M03

T.B.O

DIP-2OC-XXX

• 262,144 words x 4 bits organization
• Silicon gate, CMOS, 3thStacked
Capacitor Cell
• All input and output are TTL compatible
.512 refresh cycles every 8.2 ms

• Early write OE controlled write capability
• RAS only, CAS-before-:fiAS, or Hidden

Refresh
• Fast Page Mode, Read-Modify-Write
capability
• On chip substrate bias generator for high
performance

LCC-26P-M04

ABSOLUTE MAXIMUM RATINGS (see NOTE)

ZIP-20P-M02

NOTE:

Permanent device damage may occur Wthe above Absolute Maximum Ratings are '";:;:::;:::;:=:::;::::;:::;::==:::;:::;::;:::=;::~
exceeded. Functional operation should be restricted to the conditions as detailed in the ,. Thl d ic8
.
I "
h I
al
operational sections of this data sheet. Exposure to absolute maximum rating conditions da~e: du:O~~I~ r:.t2' ~= !we efr:~1c'e~!~
for extended periods may affect device reliability.
=I~:=:::;~":=:~~~~~~~~~~
voltages to this. high

~anC8

circuit.

Copyrighl© 1989 by FUJITSU LIMITED

2-135

CMOS DRAMs

2-136

Dynamic RAM Data Book

CMOS 1,048,576 BIT
NIBBLE MODE
DYNAMIC RAM

111111111111111111111111111111111111111111111111111111111111111

FUJITSU

MB81C4257 -85
MB81C4257-10
MB81C4257 -12

111111111111111111111111111111111111111111111111111111111111111

February 1989
Edition 1.0

CMOS 262,144

x 4 BIT Nibble Mode Dynamic RAM

The Fujitsu MB81 C4257 Is a fully decoded CMOS Dynamic RAM (DRAM) that contains
1,048,576 memory cells accessible In 4-blt Increments. The MB81C4257 features a
"Nibble' mode of operation whereby high-speed random access of up to 512-blts of
data within the same row can be selected. The MB81C4257 DRAM Is Ideally suited for
mainframes, buffers, hand-held computers, video Imaging equipment, and other
memory applications where very low power dissipation and high bandwidth are basic
requirements of the design. Since the standby current of the MB81 C4257 Is only about
one-fifth that of a conventional NMOS DRAM, the device can be used as a non-volatile
memory In equipment that uses batteries for primary andlor auxiliary power.

OIP-20P-M03

The MB81C4257 Is fabricated using silicon gate CMOS and FuJitsu's advanced
triple-layer polysllicon process. This process, coupled with three-dimensional stacked
capacitor memory cells, reduces the possibility of soft errors and extends the time
Interval between memory refreshes. Clock timing requirements for the MB81 C4257 are
not critical and all Inputs are TTL compatible.

PRODUCT LINE & FEATURES
Row Access Time

85n8 max.

lOOns max.

120ns max.

Random Cycle Time

160ns min.

180ns min.

210ns min.

Column Address Time

50ns max.

SOns max.

60ns max.

Column Access Time

25ns max.

30ns max.

35ns max.

Nibble Mode Cycle Time

60ns min.

60ns min.

70ns min.

• Operating current

358mW max.

330mW max.

275mW max.

• Standby current

l1mW max. (TTL level) 15.5mW max. (CMOS level)

OIP-20C-A03

Low Power Dissipation

• 262, 144 words x 4 bit organization

• Early write or OE controlled write capacity

• Silicon gate, CMOS, 3D-Stacked
Capacitor Cell
• All Input and output are TTL compatible
.512 refresh cycles every 8.2 ms

• FiAS only, "CAs-before-Ms,

or Hidden
Refresh
• Nibble Mode, Read-Modify-Wrlte
capacity
• On chip substrate bias generator for high
performance

LCC-26P-M04

ABSOLUTE MAXIMUM RATINGS (see NOTE)

ZIP-20P-M02
NOTE:

Permanent device damage may occur If the above Absolute Maximum
Ratings are exceeded. Functional operation should be restricted to the
conditions as detailed In the operational sections of this data sheet. Exposure
to absolute maximum rating conditions for extended periods may affect

device reliability.

This device contains circuitry to protect the
Inputs against damage due to high static
voltages or electric fields.
However, It is
advised that normal precautions be taken to
avoid application of any voltage higher than
maximum rated voltages to this high impedance

circuit.

Copyright" 1989 by FUJITSU LIMITED.

2-137

1I111111111111111111111111111111111111111111111111111

FUJITSU
11111111111111111111111111111111111111111111111111111111111111111

MB8l C4257-85
MB8 C 2
0

MB8~ C:2~~: ~ 2

Fig. 1 - MB81C4257 DYNAMIC RAM - BLOCK DIAGRAM

AO
Al
A2
DOl DQ4

A3
A4
AS
A6
A7
AS

CAPACITANCE

(TA= 25°C, f = lMHz)

Input Capacitance,

AO

Input Capacitance,

RAS. CAs,

to

A8

Input/Output Capacitance,

2-138

DOl

WE,
to

OE

DQ4

CDQ

S

pF

S

pF

6

pF

MB81 C4257-85
MB81C4257-10
MB81 C4257 -12

I I I I I I I I I I I I I I I I I~ I I I I I I I I
FUJITSU
1IIIIIIIIIIIIIIIIIIIIIIIIIIIImlllllllllllllllllili

PIN ASSIGNMENTS AND DESCRIPTIONS
26-Pln SOJ:

l8-Pln DIP:

(TOP VIEW)

(TOP VIEW)

DOl

V55

D02

DQ4

WE

DOS

RAS

CAs

NC.

OE

AO

A8

Al

A7

A2

AS

AS

A5

~
WE
RAS ~
DOl

1

D02

2

2S
25

S

24

4

2S

5

22

e

NC.

AO
Al
A2
AS

~
~

e
VCC

A4

9

18

10

17

11

lS

12

15

13

14

~

VSS
DQ4
Doo

~ CAs
DE

~
~
P

AS
A7
AS
A5
A4

20-Pln ZIP:
(TOP VIEW)
CAS

OQ4

DOl

WE

NC.
A 1 A 3 A 4 A 6
A 8
2n 4n an an 10n 12n14n l6n 1Bn 2011
~UnunUnununUnUnUnUn

1113115117119'11111,11

OE

Doo

V 55 D02

RAS

AO

A2

151'17111011

Vce

A 5

A 7

RECOMMENDED OPERATING CONDITIONS
(All voltages referenced to ground; TA

= O°C to 70°C)

Input High Voltage. all Inputs

VIH

2.4

6.5

V

Input Low Voltage. all Inputs

VIL

-2.0

0.8

V

Input Low Voltage. DO( Note)

VILD

-1.0

0.8

V

Note: Undershoots of up to -2.0 volts with a pulse width not exceeding 20ns are acceptable.

2-139

11111111111111111111!11111!!111!1111111111111111!111111111111!

FUJITSU·
!111111111!1111111!111111111111111!!1111111!1111111111111!11!1111

MB81C4257-85
MB81C4257-10
MB81C4257-12

FUNCTIONAL OPERATION
ADDRESS INPUTS
Eighteen Input bits are required to deoode any four of
1,048,576 oell addresses In the memory matrix. Sinoe only
nine address bits are available, the oolumn and row Inputs are
separately strobed by CAS and RAS as shown In Figure 4.
First, nine row address bits are Input on pins AO-through-A8
and latohed with the row address strobe (RAS); then nine
oolumn address bits are Input and latohed with the oolumn
address strobe (CAS). Both row and oolumn addresses must
be stable on or before the falling edge of CAS and RAS,
respeotlvely. The address latohes are of the flow-through

the Input; the output buffers remain In the high-Impedance
state until the column address strobe goes Low. When a read
or read-modlfy-wrlte cycle Is exeouted, valid outputs are
obtained under the following oondltlons:
tRAC:
tCAC:
tAA:
tOEA:

type; thus, address Information appearing after tRAH (min) +
tT Is automatloally treated as the oolumn address.

from the falling edge of RAS when tRCD (max)
Is satisfied.
from the failing edge of CAS when tRCD Is
greater than tRAD (max).
from oolumn address Input when tRAD Is
greater than tRAD (max).
from the failing edge of DE when DE Is
brought Low after tRAC, tCAC, or tCAA.

The data remains valid until either CAS or DE returns to a
High logic level. When an early write Is exeouted, the output
buffers remain in a hlgh-Impedanoe state during the entire
oyole.

WRITE ENABLE
The read or write mode Is determined by the loglo state of
WE. When WE Is aotive Low, a write cycle Is initiated; when
WE Is High, a read oyole Is seleoted. During the read mode,
Input data Is Ignored.

NIBBLE MODE OF OPERATION

DATA INPUT
In the nibble mode of operation, the user can serially aooess
from one to four bits of data and perform high-speed read,
write, or read-modlfy-wrlte operations. During the nibble
mode, the aooessed bits of data are determined by row
address zero (0) and oolumn address one ( 1) . For initial
aocess, address bits CAO and CAl are used to seleot one of
four nibble bits. After the first bit Is aooessed by this method,
all remaining bits are aooessed by simply toggling the oolumn
address strobe (CAS) from High to Low. Eaoh Hlgh-to-Low
transition of CAS Internally Inorements CAO and CA 1 and
provides access to the next nibble bit.

Input data Is written Into memory In either of three baslo
ways--an early write cyole, an DE (delayed) write cyole, and
a read-modlfy-wrlte cyole. The failing edge of WE or CAS ,
whlohever Is later, serves as the Input data-latch strobe. In an
early write oycle, the Input data (001-004) Is strobed by
CAS and the setup/hold times are referenoed to CAS
beoause WE goes Low before CAS. In a del~yed write or a
read-modlfy-wrlte cyole, WE goes Low after CAS; thus, input
data Is strobed by WE and all setup/hold times are referenced
to the write-enable signal.

If more than four bits are aooessed during the nibble mode,
AC
the address sequenoe shown In Table 1 will repeat.
parameters for eaoh nibble mode of operation are shown In
subsequent timing diagrams (Figures 9 through 12).

DATA OUTPUT
The three-state buffers are TTL oompatlble with a fanout of
two TTL loads. Polarity of the output data Is Identical to that of

Table 1 - NIBBLE MODE ADDRESS SEQUENCE

RAS/CAs

(Normal mode)

101010101

Toggle

CAs

(Nibble mode)

Toggle

CAs

(Nibble mode)

3

101010101

Toggle CAS (Nibble mode)

4

101010101

Toggle CAS (Nibble mode)

2-140

0

101010101

101010101

0

1010101

0

1010101

a

Input address

Internally generated
address

1010101
1010101

a

1010101

0

Sequence repeats

MB81C4257-85
MB81C4257-10
MB81C4257-12

FUJITSU

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)

~~~~i

_F·.,.·!Y. .,. . . . . . . . .

II

I.•.·.•.•. f • •.• ·• • • • • •

I

· · · · · · .·.~ ~i

,y

V
Output

Voltage

VOL

IOl .4.2 mA

0.4

o V S VIN

Input Leakage Current (Any Input)

Output Leakage Current

II(L)

S 5.5 V;
4.5 V S VOO S 5.5 V;
V 55 : 0 V; All other pins not
under test: OV

IDQ(l)

, 0 V S VOUT ~ 5.5 V;
Data out disabled

1001
(Note)

RAS & CAS cycling;
IRO: min

-10

-

fJ.A
-10

-

MBB 1C4257 -B5
Operating Current
(Average Power
Supply Current)

Standby Current
(Power Supply
Current)
Refresh Current
#1 (Average
Power Supply
Current)

MBB1C4257-10

-

-

-

-

60

mA

IMBB1C4257-12
RAS : CAS : VIH

TTL Level

2.0

1002
CMOS Level

RAS :

CAS ;>: Voo

CAS :

VIH,

-0.2 V

MBB1C4257-85
MB81C4257-10

60
1003
(Note)

RAS

cycling;

IRO: min

-

-

MB81C4257-12

MB81C4257-10

IMI

55

mA

45

1004
(Note)

-RAS :VIL, CAS cycling
INO: min

40

-

-

40

mA

33

MB81 C4257-85
MB81C4257-10

mA
1.0

MB81C4257-12
Refresh Current
#2 (Average
Power Supply
Current)

10
65

MB81 C4257 -85
Nibble Mode
Current

10

ICC5
(Note)

-RAS cycling
--CAS-before-RAS:
IRO: min

60

-

-

55

mA

12

Nole: 100 depends on the output load conditions and cycle rates; The speCified values are obtained with the output open.
Icc depends on the Input low voltage level VIL, VIl>-0.5V.

2-141

1111111111111111111111111I1111111111111111111111111111111I11111

MB81 C4257 -85

III~I~~I~I;I;~III ~~~~ g~~~t ~ g
AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.) Notes 1. 2. 3

2-142

MB81C4257-85
MB81C4257-10
MB81C4257-12

AC CHARACTERISTICS

FUJITSU

(Continued)

(At recommended operating conditions unless otherwise noted.) Notes 1, 2, 3

:~~.

····.MB81 C4257:085 I MBSfC4257,.10
r.·. 1§~r11~~1 I {!\ill,.,. •••. ,.;" ..;. IMfnMill<'

..........

MB8i~1i5i2j2

I.)~'''' ·.IM~#

.•

!]g~!! l/~~~~

35

RAS Precharge Time to CAS
Active Time

t RPC

a

-

a

-

a

-

ns

-

36

CAS Set Up Time for " ~
RAS Refresh

tCSR

a

-

a

-

a

-

ns

-

tCHR

15

-

15

-

20

-

ns

-

tOEA

-

22

-

25

30

ns

7

tOEZ

-

25

-

25

-

25

ns

8

-

10

-

10

-

ns

-

ns

13

~ Hold Time for "'~

37

Refresh

38

~,,~sTim~from

39

Outpulluffer Turn Off Delay
from OE

40

OE
DE

to RAS Lead Time for Valid Data

tOEL

10

41

Hold Time

tOEH

a

42

DE

to Data In Delay Time

tOED

25

-

25

43

DIN to CAS[)elay Time

t DZC

-

a

44

DINto OE ~1,,~Time

tl>?O

a
Jl_

-

0

45

Time
(Counter Test Cycle)

t CAT

-

50

-

50

50

Nibble Mode Read/Write
Cycle Time

t NC

60

-

60

51

Nibble Mode Read-Modify-Write
c:ycle Time

·NRWC

115

-

Access Time from Nibble Mode

t NPA

-

60

[NCP

15

52

BE

ItoWE

CAS Pre charge
Nibble Mode CAS Dr~~" .. ,_~~ Time

53

a

a
-

ns

14

-"!.

14

-

60

ns

-

-

70

-

ns

-

115

-

130

-

ns

-

-

60

-

70

ns

7.16

15

-

25

a

a

-

15

ns

ns

Notes:
1.

An Initial pause (RAS~CAS~VIH) of 200j.ls Is required
after power-up followed by any eight RAS -only cycles
before proper device operation Is achieved. In case of
using Internal refresh counter. a minimum of eight
CAS-before-RAS Initialization cycles Instead of 8 RAS
cycles are required.

9.

Operation within the tRCD (max) limit ensures that tRAC
(max) can be met. tRCD (max) Is specified as a
reference point only; if tRCD is greater than the specified
tRCD (max) limit. access time Is controlled exclusively by
tCAC or t AA .

2.

AC characteristics assume tT = 5ns

10.

tRCD (min) = tRAH (mln)+ 2t T + tASC (min)

3.

VIH (min) and VIL (max) are reference levels for
measuring timing of Input signals. Also transition times
are measured between V IH (min) and V IL (max).

11.

Operation within the tRAD (max) limit ensures that tRAC
(max) can be met.
tRAD (max) Is specified as a

4.

Assumes that tRCD ~ tRcD (max). tRAD ~ tRAD (max).
If tRCD Is greater than the maximum recommended value
shown In this table. tRAC will be Increased by the amount
that tRCD exceeds the value shown. Refer to Fig. 2 and

3.
5.

Assumes that tRCD
If tASC

2

2

tRCD (max). tRAD

2

tRAD (max).

tAA - tCAC - t T. access time Is tCAC.

6.

If tRAQ ;::: tRAD (max) and tASC ~ tAA - tCAC - t T.
access time Is t AA .

7.

Measured with a load equivalent to two TTL loads and 100
pF.

8.

tOFF and tOEZ Is specified that output buffer change to
high Impedance state.

reference point only; If tRAD is greater than the specified
tRAD (max) limit. access time Is controlled exclusively by
tCAC or t AA .
12.

Either tRRH or tRCH must be satisfied for a read cycle.

13.

Assumes that twcs < twcs (min)

14.

Either tDZC or tDZO must be satisfied.

15.

twcs is specified as a reference point only. If twcs

2

twcs (min) the data output pin will remain Hlgh-Z state
through entire cycle.
16.

tNPA is access time from the selection of a new column
address (that Is caused by changing CAS from "L" to
"H" ). Therefore. if tNCP is shortened, tCAC Is longer than
!CAC (max).

17.

Assumes that CAS -before- RAS refresh,
fore- RAS refresh counter test cycle only.

CAS -be-

2-143

FUJITSU

MB81C4257-85
MB81C4257-10
MB81C4257-12

I RAClns)

,,~.v"'/

160

140

140

120

120

100

100

1OOns Version
~:

85ns Version

85ns Version
80

----r

80

1

20

40

60

1

•

100 120

I
I
I

20

40

60

•

100

120

i·.·· ..

Note)

80

I RADlns)

FUNCTIONAL TRUTH TABLE
OPeration Mo<:!~
......
.....•....
. .
.....

·clocklhhUt

Address •

RAS

CAS

WE

OE.

Siandby

H

H

X

X

Read Cycle

L

L

H

L

Valid

Valid

Wrile Cycle
I Early Wrile)

L

L

L

X

Valid

Valid

Read-ModifyWrlle Cycle

L

L

Valid

Valid

RAS-only
Refresh Cycle

L

H

X

X

L

L

X

H-+L

L

X

CAS-beforeRAS Refresh
Cycle
Hidden Refresh
Cycle

•RoW.......•••• ·Column

INY~tn

Hlgh-Z
Valid

0

tRCS~tRCS

Valid

Hlgh-Z

0

twcs~twcs

Valid

Valid

0

High-Z

0

X

High-Z

0

tcsR~tcsR

L

Valid

0

Previous dala
Is kept.

H-+L L-+H

Valid

X' "W or "L"
•. II is impossible In Nibble Mode

2-144

Input Data
Input ••· Output

I min)

Imin)

I min)

MB81C4257-85
MB81C4257-10
MB81C4257-12

FUJITSU

TIMING DIAGRAMS
Fig. 4 - READ CYCLE

~----------------------- t RC
~-----------------tRAS----------------~

RAS

~-----------------tcsH--------------~·1
----~~------tRSH--------~
V'H--

CAS

V'L --

Aoto AS

V'H-V'L --

WE

r

V'H-V'L--

tAA
tCAC -'------I

~--------~--~I--tRAC------~~--~w_----~~1
DO
(Output)

VOH -VOL __

DO
(Input)

V'H-V'L __

~tON

V'H-OE

V'L--

I::::::::::::::::]

DESCRIPTION

RAs

"H" or "L"

To implement a read operation, a valid address Is latched in by the
and "CAS address strobes and, with WE set to a High level and
set to a Low level, the output is valid once the memory access time has elapsed. The access time Is determined by
(t RAe),

DE

CAS

(t CAe ),

"OE,

RAs

(tOEA) or column addresses (tAA ) under the following conditions:

• 11

t Reo> t Reo (max), access time = t CAe.

• If

tAAD> tRAD (max), access time = tAA.

• If De Is brought Low after t RAe t CAe or t AA (which ever occurs later),
CAS or OE goes High, the output returns to a high-Impedance state after t OH Is satisfied.
I

However, If either

access time = tOEA.

2-145

MBS1 C4257-S5

II!II!II!III!II!III!IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

111~1.11~lml:I.111 ~~g~g:~~~:~g

Fig. 5 - EARLY WRITE CYCLE (OE

="H"

or "L")

t RC
t RAS

RAS

V1H V1L tCSH

t RSH

-I

t CAS
CAS

V1H V1L tRAL

Aoto As

V1H V1L -

WE

DO

VALID
DATA IN

(Input)

DO

V OH -

(Output) VOL -

------------------------------HIGH-Z-------------------------------

li'l

"H"

or "L"

DESCRIPTION
A write cycle is similar to a read cycle except

WE

Is set to a Low state andOe Is a "H" or "L" signaL A write cycle can be Implemented

In either of three ways -- early write, Oewrlte (delayed write), or read-modify-write. During all write cycles, timing parameters tRWL,
tCWL and tRAL must be satisfied. In the early write cycle shown above
edge of

2-146

CAs

and written Into memory.

twos

satisfied, data on the DQ pins Is latched with the falling

MB81C4257-85
MB81C4257-10
MB81C4257-12

FUJITSU

Fig. 6 - OE (DELAYED WRITE CYCLE)

~--------------------------tRC

r------------------- t RAS -------------1 Ir--~

V 1H -

RAs

V1L -

V1H -

CAs

V 1L -

AotO As

V 1H V 1L -

V 1H -

WE

V1L -

DO

V 1H -

(Input)

V1L -

DO

V OH -

(Output)

V OL -

V 1H -

OE

V1L -

DESCRIPTION
In the

OE

(delayed write) cycle,

memory. The Output Enable

twcs

toE)

III

"H" or "L"

•

Invalid Data

Is not satisfied; thus, the data on the DC pins Is latched with the falltng edge of WE and written Into

signal must be changed from Low to High before

WE goes Low

(t OED + t OS),

2-147

IIIII~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII M881 C4257-85
FUJITSU M
C
IIIIIIIMIIIIIIIIIIIIMIIIIIIIIIIIIIIII

M~g ~ C~~~~=~ g

Fig. 7 - READ-MODIFY-WRITE-CYCLE

V 1H -

RAS

V 1L -

V 1H -

CAS

V 1L -

V 1H _

Aoto As

V 1H -

WE

V 1L -

DO
(Input)

V 1H V 1L -

DO
(Output)

OE

V 1L -

V OH V OL -

V 1H V 1L -

DESCRIPTION

We from High to Low after the data appears on the DO pins.
OE must be changed from Low to High after the memory access time.

The read-modify-write cycle Is executed by changing

cycle,

2-148

In the read-modify-write

MB81 C4257-85
MB81C4257-10
MB81C4257-12

l!i!III!I!!!:!I!:!!IIIII!I!!:!!!!!!:IIIIII!:I'!!:::::1IIIII!!II:!

FUJITSU

Fig. 9 - NIBBLE MODE READ CYCLE

~--------------------tRAS----------------------~
RAS

CAS

Aoto AS

V 1H V 1L -

V 1H V 1L -

WE

DQ
(Input)

DQ
(Output)

OE

V 1H V 1L -

V 1H V 1L -

HIGH-Z+-

HIG'H-:7-~

V OH VOL -

V 1H V 1L -

IIII

"H or L"

E:~~~::J

Valid Data

2-149

111111111111111111111111111111111111111111111111111I1111111111111

FUJITSU
IIIIIIIIIIIIIIIII!IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII!IIIIII

MB81 C4257-85
MB81C4257-10
MB81 C4257-12

Fig. 10 - NIBBLE MODE WRITE CYCLE COE

= "H"

or "L")

RAS

CAS

WE

DO
(Input)

DO

V OH

-

(Output) VOL -

------------HIGH

7"z-------------

r:i:1ji:::1j::]

2-150

"H" or "L"

MB81C4257-85
MB81C4257-10
MB81C4257-12

FUJITSU

Fig. 11 - NIBBLE MODE OE (DELAYED) WRITE CYCLE

RAS

CAS

WE

DO
(Input)

DO
(Output)

OE

h::i::::i::i:J

"H" or "L"

•

Invalid Data

2-151

11111111111111111111111111111!111111111111111111111!1111111111111

FUJITSU
11111111111111111111111111111111111111111111111111111111111111111

MB8t C4257-85
MB81C4257-10
MB81 C4257-12

Fig. 12 - NIBBLE MODE READ-MODIFY-WRITE CYCLE

WE

V 1H V 1L -

DO
(Input)

DO
(Output)

OE

V 1L -

V OH VOL -

V 1H VIL -

tOEA

2-152

tOEA

III

"H" or "L"

•

Invalid Data

MB81C4257-85
MB81C4257-10
MB81C4257-12

Fig. 12 -

RAS-ONLY REFRESH (WE

= OE = "H"

1111111111111!1111111111111111111111111111111111111111I111111111

FUJITSU
1111111111111111!11111111\111111111111111111111111!1111111

or "L")

~-------------------tRC------------------~~

DO

VOH

(Output) VOL

-

::::::::::::::::~~------------------HIGH-Z------------------------

III

"H" or "L"

DESCRIPTION
Refresh 01 RAM memory cells Is accomplished by performing a read, a write, or a read-modify-write cycle at each of 512 row addresses every

B.2-mllllseconds. Three refresh modes are available: RAs-only refresh, CAs -before- RAs refresh, and hidden refresh.
RAs -only refresh is perforr:ned by keeping RAs Low and CAs High throughout the cycle; the row address to be refreshed Is latched on the
failing edge of RAs , During AAs-only refresh, DQ pins are kept In a high-Impedance state,

Fig. 13 - CAS-BEFORE-RAS REFRESH (ADDRESSES = WE = OE = "H" or "L")

OH
DO
V
(Output)
VOL

-_

::::::::::::b!....--------------------------- HIGH-Z------------------------

DESCRIPTION

CAs -be10re- RAS

CAs

refresh Is an on-chip refresh capability that eliminates the need for external refresh addresses. If
is held Low tor the
specified setup time (t eSR) before
goes Low, the on-chlp refresh control clock generators and refresh address counter are enabled. An
internal refresh operation automatically occurs and the refresh address counter Is Internally Incremented In preparation for the next
-beforerefresh operation.

CAs

RAs

RAs

2-153

~I I I I I I I I I I I I I I I~I I I I I I I I!I I I I1 1 1 MB81 C4257-85
FUJITSU MB8 C
11111111111111111111111111111111111111111111111111111111111111111

MB8~ C:~~~= ~ g

Fig. 14 - HIDDEN REFRESH CYCLE

~----------tRC----------~~------V1H RAS

V1L -

V1H CAS

V1L -

V1H Aoto As

V1L -

V1H WE

V1L -

V1H -

DQ
(Input)

V1L -

DQ
(Output)

OE

VOH VALID DATA OUT

VOL -

V1H V 1L _

I::::::)~/:I

"HOI or OIL"

DESCRIPTION
A hidden refresh cycle may be performed white maintaining the latest valid data at the output by extending the ·actlve time 01
cycling

Ms.

that Is required by DRAMs that do not have

2-154

CAS and

The rafresh row address Is provided by the on-chlp refresh address counter. This eliminates the need for the external row address

CAs -OO10r9- "RAs

refresh capability.

MB81C4257-85
MB81C4257-10
MB81C4257-12

FUJITSU

Fig. 15 - CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE

RAS

V1HV 1L -

CAS

V 1H V 1L -

Aoto As

V 1H V 1L -

(Read)

V 1H V 1L -

DO
(Input)

V1HV1L -

We

DO
(Output)

V OH VOL -

V1HV 1L -

OE

I;{ii!:!:!:!:i::i "H" or "L"

1,<~,<~~\\1

Valid Data

DESCRIPTION

CAs

A special timing sequence using the
-bElfore- RAS refresh counter test cycle provides a convenient method to verify the functIonality of
-beforerefresh circuitry. If, after a
-beforerefresh cycle,
makes a transition from High to Low while RAS Is
held Low, read and write operations are enabled as shown above, Rowand column addresses are defined as follows:

CAs

RAs

CAs

RAs

CAs

Row Address: Bits AD through A8 are defined by the on-chip refresh counter,
Column Address: 81ts AD through AS are defined by latching levels on AO-AS at the second failing edge of

The

CAS.

Cycle Is designed for use with the followlng~edures: _
InItialize the Internal refresh address counter by using eight CAS -before- RAS refresh cycles.

CAs -OOlore- RAS Counter Test
•
•

Use the same column address throughout the test.
WrIte zeroes (Os) to all 512 row addresses at the same column address by using normal early write cycles.

•

Read zeroes written in procedure 3 and check; simultaneously write ones (ls) to the same addresses by using
Internal refresh counter test read-write cycles. Repeat this procedure 512 times with addresses generated
by the internal refresh address counter.

•

Read and check data written in procedure 4 by usIng normal read cycle for all 512 memory locations.
Complement test pattern and repeat procedures 3, 4, and 5.

2-155

I I I I I I I I I I I I I I I I I I I I I I I I I!I I 111111111

MB81 C4257-85

Illiil~II~liI;I~111 ~gg ~ g:~~~=~ g
PACKAGE DIMENSIONS
(Suffix . -P)
20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-20P-M03)

© 1988 FUJITSU LIMITED 020011 S-1 C

2-156

Dimensions in
inches (millimeters)

MB81 C4257-85
MB81C4257-10
MB81C4257-12

PACKAGE DIMENSIONS

:I~II' 1"'1.'1',,111 IIIIII!I!I'II:I! !" ",1,1

FUJITSU
i'IIII:I!~i'i'

(Continued)

(Suffix : -C)
20-LEAD CERAMIC DUAL IN-LINE PACKAGE
(CASE No.:

DIP-20C-A03)

,~ tRCO (max). access time = tACo
• If tRAO > tRAO (max). access time = 1M.

_

.!.. If OE is brought Low after iAAC. ICAC. or 1M (which ever occurs later). access time = tlEA.

However if either CAS or OE oes Hi h the out ut returns to a hi h-im edance state after tlH is satisfied.

2-170

MB81C4258-70
MB81 C4258-80
MB81C4258-10
MB81C4258-12

Fig, 5 - EARLY WRITE CYCLE (m:

="H" or "L")

1--------------------------tRc
VIH-

------::ILt'I---------- tRAS

VIL-

1---------- tCSH
1 - - - - tRCO

VIHVIL-

~

---t------ tRSH

_ _ _•

DO
(Input)

DQ
VOH·1
(Output) VOL- - - - - - - - - - - - - - - - H I G H - Z - - - - - - - - - - - - - - - -

*1; If tws ~ tws (min) and tWH ~ twH (min), DO (Output) pin is high-Z.

1;J,::~11

'W or 'L'

DESCRIPTION
A write cycle is similarto a read cycle except ~s set to a Low state and ~s a "H" or "L" signal. A write cycle can be implemented in either of
three ways-earlywrite, Orwi'ite (delayed write), orread-modily-write. During all write cycles, timing parameterstRwL, tcwL and tRAL must be
satisfied. In the early write cycle shown above tiVCS satisfied, data on the DO pins is latched with the falling edge of Clrn and written into
memory.

2-171

IfJ

MBS1C425S-70
MBS1C425S-S0
MBS1C425S-10
MBS1C425S-12

Fig. 6 - READ-MODIFY-WRITE-CYCLE
~-----------------------tA~

RAs'

VIH_

~-------------------tA~

Vll-

~------------------t~H

~I

tAP

....----tACO ----...---------- tAsH

CAs'

~-----tcAS

VIHVll-

h ,,""
l
~fc1

VIH-

AotoA.

Vll-

VIH_

WE

Vll_

DQ
(Input)

DO
(Output)

VIH_
Vll_

VOH VOL _

_ _ _ _....;....;_

~----- HIGH-Z-.:...----

VIH-

OE

Vll-

DESCRIPTION
The read-modify-write cycle is executed by changing ~ from High to Low after the data appears on the DO pins. In the reacf-modify-write
cycle,
must be changed from Low to High after the memory access time.

rn:

2-172

MBS1C425S-70
MBS1C425S-S0
MBS1 C425S-1 0
MBS1C425S-12
Fig" 7 - STATIC COLUMN MODE READ CYCLE

~---------------------t~
VIHRAS

VIL-

VIH--

CAS

------------------__~

______~_~------------------tRM

----.:II:-~------_:D

VIL--

VIHVIL-

VIH--

WE

DO
(Input)

VIL--

VIHVIL-

DO
(Output)

VIH--

OE

VIL--

DESCRIPTION

II

"H"or"L"

In a static column mode read cycle, the access time istRAC from the falling edge ofmiS ortAA from the column address input or tOEA from the
falling edge of OE'. The data remains valid for a time tACH after the column address is changed.

2-173

MBS1C425S-70
MBS1C425S-S0
MBS1C425S-10
MBS1C425S-12

Fig. 8 - STATIC COLUMN MODE WRITE CYCLE (OE

VH _

___

~

="H " or "L")

_______________________ tRC ________________________

~:::==::_;~;_==:;I
tRSOO

tRAS

~

------------------1.J~-__L

VIL -

VIH_

IfJ

VIL-

Ao toA 8

WE

DO
(Input)

VH _

~~-:::±-u!'aJr-:-~~~l.n~,kl-\~~-s~

VIL -

.....TI';....::=~'"'TI'T;::;::;=...,:f'\.=ry:~:~~F

VH_ ------~I
VIL-

VH_
VILtOFF

DO
(Output)

VOL -

VIH _
OE

·1

VOH _
HIGH-Z

--------..,=r------......;~_4I_----"'""lm

VIL -

·1; If tws ~ tws (min) and tWH ~tWH (min). DO (Output) pin is high-Z.
DESCRIPTION
In a static column mode write cycle, the data is written into the cell triggered by the later falling edge oreAs or"Wl:. If bothtws and tWH are
greater than their minimum limits, the data output pin is kept high impedance state through the static column mode write cycle. The Ormust be
high before the data are applied to DO pins.

2-174

MB81 C4258-70
MB81 C4258-80
MB81C4258-10
MB81C4258-12

Fig, 9 - STATIC COLUMN MODE READ-MODIFY-WRITE CYCLE

~--------------------------tRC ------------------------~
VIHVIL-

VIH _--=li~~---_m..
VIL-

Ao toA 8 VIL-

WE

DO
(Input)

VIH
VIL-

VIH __
VIL--

DO
(Output)

OE

VIH- ------1.1
VIL- _ _ _ _ _ _

~---'

*1; If tLWAD (min)~ ILWAD ~ tLWAD (max). tALW
DESCRIPTION

=tsc (min) + tM (max).

II

'H'm'L'

l<~>~:l

Valid Data

In the static column mode read-modify-wrile cyde.~ goes low afler I\WD from the column address inputs andtcWD from the faling edge of

CAS. The data and column address inputs are strobed and latched by the falling edge of WE:TIie OE must be high before the data are applied
to DO pins.

2-175

MBS1C425S-70
MBS1C425S-S0
MBS1C425S-10
MBS1C425S-12
Fig. 10 - STATIC COLUMN MODE MIXED CYCLE *1
VH _

~------------------------tRe ------------------~----~
tRAS

L:------------

- -.....

VIL-

VIH _

-..,jp-;....--.....It.

VIL -

Ao toA

VIH _

~~~=-:t._u..l..~~~

VIL -

~~~~~'~~~~~~

VIH _

-------..

8

VIL-

DO

VIH _

(Input)

VIL -

DO
(Output)

VOHVOL -

VIH _

OE

VIL-

WRITE CYCLE

READ CYCLE

READ-MODIFY-WRITE CYCLE

'1; This is an example of static column mode mixed cycle.
'2; If ILWAD is satisfied its minimax value, tALW = tse (min) + tAA (max)

DESCRIPTION

1~@ili¥1

-H-

or"~

I",:~>:,,'I

VaM Data

In the static column mode, read, write, and read-modify-write cycles can be mixed in any order.
In the next read cycle of static column mode write cycle or read-modify-write cycle, the access time is determined by the following conditions.
1. tALw from the falling edge of WE or ~ at previous write cycle.
2.

IAA from

the column address inputs.

3. tWPA from the rising edge of WE' at the read cycle.

2-176

4.lcAe from the falling edge of~
5. toEA from the falling edge ofO'E

MB81 C4258·70
MB81 C4258·80
MB81C4258·10
MB81C4258·12

fig. 11 -

RAS-ONLV REfRESH (WE

= OE = "H" or "L")

~-----------------t~------------------~
VIH -

AAs
Ao toA

CAs

V1l -

8

V1H V 1l -

V1H V1l tOH

DO
(Output)

VOH
VOL

----------------~~---------------HIGH-Z----------------------

DESCRIPTION
Relresh of RAM memory cells is accomplished by performing a read, a write, or a read-modify-write cycleat each of 512 row addresses every
B.2-milliseconds. Three refresh modes are available; ~nly refresh, ~before-'RAS refresh, and hidden refresh.
~-only refresh is performed by keeping"RAS Low and ~ High throughout the cycle; the row address to be refreshed is latched on the

falling edge of~. During FtltS-'I~El.
MAX

L

,

f--'

nnn

'

H

II

H

t-'U'19715'00IMAX

-- --

.12513.181 MIN
U U
_
11018+.006
~_::-002020(0511 MIN
(0.45~g:b~1
~

f--- ~~.odanco clroul.

"""Icatlon

Ccpyrlght@l989byFUJITSU LIMITED

2-187

MB814100-80
MB814100-10
MB814100-12

Fig. 1 - MB814100 DYNAMIC RAM - BLOCK DIAGRAM

AO

DIN

Al
A2
A3
A4
A5
AS

DOUT

A7
AS
A9
Al0

Input Capacitance, AO to A 10, DIN

C 'N1

5

pF

WE

C 'N2

5

pF

C OUT

5

pF

Input Capacitance, RAS, CAS,
Output Capacitance, DOUT

2-188

MB814100-80
MB814100-10
MB814100-12

PIN ASSIGNMENTS AND DESCRIPTIONS
26-PlnSOJ:

16-Pln DIP:

(TOP VIEW)

(TOP VIEW)

DIN

DOUT

RAS

CAS

A,a

Ag

Aa

A.

A,

A7

A2

A6

WE

RAS

26
25
24

~ CAs

23

NC.

22

5

A,a [

A,
A2

.~

17

11

,. P~
16
15

13

Vee

~

CbUT

P A.

la

12

A3

~S

,

~ •
~

Aa

A4

VCC

1

2

3

NC.

A5

A3

:
:•

DIN

VSS

WE

20-Pln ZIP:
(TOP VIEW)

CAS

Vss

2..

4..

WE
6.

Al0

NC.

8..

I

10..

A,
12.

A3
14 I .

I

A4
16.

I

As
18.

I

A8
20.

I

~UnunUnUnUnUnUnunUn

l'

I

3"

Ag DOUT

5'

I

DIN

~.

RAs'

9"

1P'

NC.

Ao

13'

I

15"

A2

Vee

17'

I

19-

A 5

I

A 7

RECOMMENDED OPERATING CONDITIONS

Supply Voltage

V
DoC to +70

Input High Voltage, all inputs

IT]

VIH

2.4

6.5

V

Input Low Voltage, all inputs

IT]

VIL

-2.0

0.8

V

°c

2-189

MBS14100-S0
MBS14100-10
MBS14100-12

FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty-two input bits are required to decode anyone of 4, 194,304 cell addresses in the memory matrix. Since only eleven address bits (AO-A 10) are
available, the column and row inputs are separately strobed by~ and~ as shown in Figure 4. First, eleven row address bits are applied on pins
AO-through-A 10 and latched with the row address strobe (RAS ) then, eleven column address bits are applied and latched with the column address
strobe ~ ). Both row and column addresses must be stable on orbeforethe falling edge of~ and~ , respectively. The address latches are of
the flow-through type; thus, address information appearing after mH (min)+ IT is automatically treated as the column address.

WRITE ENABLE
The read or write mode is determined by the logic state of WE . When WE is active Low, a write cyde is initiated; when WE is High, a read cycle is
selected. During the read mode, input data is ignored.

DATA INPUT
Input data is written into memory in either of two basic ways-an early write cycle and a read-modify-write cycle. The falling edge oWE or ~ ,
whichever is later, serves as the input data-latch strobe. In an early write cycle, the input data is strobed by~ and the setup/hold times are
referenced to ~ because WE goes Low before ~ . In a delayed write or a reacHnodify-write cyde, WE goes Low after~ ; thus, input data is
strobed by WE and all setuplhold times are referenced to the write-~,"able signal.

DATA OUTPUT
The three-state buffers are TIL compatible with a fanout of two TIL loads. Polarity of the oulput data is identical to that of the input; the oulput buffers
remain in the high-impedance state until the column address strobe goes Low. When a read or reacHnodify-write cyde is executed, valid outputs are
obtained under the following conditions:
IRAC :

from the falling edge of~ when tReD (max) is satisfied.

ICAC:

from the falling edge of~ when tReD is greater than tReD (max).

IAA

from column address input when IRAD is greater than tRAD (max).

The data remains valid until either~ returns 10 a High logic level. When an earty write is executed, the oulput buffers remain in a high-impedance
state during the entire cyde.

FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode is implemented by keeping the
same row address and strobing in successive column addresses. To satisfy these conditions,~ is held Low for all contiguous memory cycles in
which row addresses are common. Foreachfastpage of memory, any of 2,048-bits can be accessed and, when multiple MB 814100s are used,~
is decoded to select the desired memory fast page. Fast page mode operations need not be addressed sequentially and combinations of read, write,
and/or readY-modify-write cycles are permitted.

2-190

MBS14100-S0
MBS14100-10
MBS14100-12

DC CHARACTERISTICS

--

(Recommended operating condHlons unless otherwise noted)

Input leakage current (any input)

II(L)

Output leakage current

loeL)

Oparating current
(Average Power
supply current)

OV:<:>Vo;:<:>5.5V;
4.5V:':>Vcc:':> 5.5V;
Vss = OV; All other pins
not under test = OV
OV:<:>Vou":-;; 5.5V;
Data out disabled

Notes 3

-10

10

-10

10

v

RAS & CAS cycling;
ICCl

rnA

IRC = min

~

Standby current
(Power supply
current)

1CC2

Refresh current # 1
(Average power~
ply current)
2

IcC3

Fast Page Mode

current

~

Refresh current #2
(Average power supply current)

~

1CC4

RAs = CAS

~ Vcc ...{J.2V

~ = VIH, ~ cycling;

lAC = min

"RAS =VIL,

rnA
1.0

rnA

~ cycling;

Ipc = min

rnA

RAs cycling;
Icc5

CAS-before-ro;s;

rnA

lAC = min

2-191

MBS14100-S0
MBS14100-10
MBS14100-12

AC CHARACTERISTICS

IfJ

2-192

MB814100·80
MB814100·10
MB814100·12

AC CHARACTERISTICS

(Continued)

(At recommended operating conditions unless otherwise noted.) Notes 3, 4, 5

Noles:
1. Referenced 10 VSS
2. Icc depends on the output load conditions and cycle rates; The
specified values are obtained with the output open.'
Icc depends on the number of address change as"RAS = VIL and
~=VIH.
ICC1, ICC3 and Iccs are specified at three time of address change
during "RAS = VIL and ~ = VIH.
Icc. is specified at one time of address change during ~ = VIL
and ~=VIH.
3. An Initial pause (~=~ =VIH) of 2ODI!S is required after
power-up followed by any eight ~ -ooly cycles before proper
device operation is achieved. In case of using internal refresh
counter, a minimum of eight ~ -before-"RAS initialization
cycles instead of 8 ~ cycles are required.
4. AC charecteristics assume Ir = 5ns.
5. VIH (min) and VIL (max) are reference levels for measuring
timing of input signals. Also transition times are measured
between V IH (min) and VIL (max).
6. Assumes that tRCO~ tRCO (max), tRAO~ tRAO (max). If tRCO is
greater than the maximum recommended value shown in this
table, tRAC will be increased by the amount that IRco exceeds the
value shown. Refer to Fig. 2 and 3.
7.

IftReo2:IReO (max), tRAO2: tRAO (max), andlASc 2:tAA -lcAc-

11. Operation within the IReD (max) limit ensures that tRAe (max)
can be met. IRco (max) is specified as a reference point only; if
tReO is greater than the specified lReo (max) limit, access time is
controlled exclusively by teAe or t AA .
12. tReO (min) = tRAH (min)+ 21T + lAse (min).
13. Operation within the tRAO (max) limit ensures that tRAe (max)
can be met. IRAO (max) is specified as a reference point only; if
IRAO is greater than the specified lRAo (max) limil, access time is
controlled exclusively by IcAc or t AA .
14. Either tRRH or tACH must be salisfied for a read cycle.
15. t wcs , I cwo , I,RWD and IAWD are not a restrictive operating
parameter. They are included in the data sheel as an electrical
characteristic only. If twos > I wcs (min), the cycle is an early
write cycle and Doul pin will maintain high impedance state
thoughoulthe entire cycle. If I cwo > I cwo (min), I RWD > t
RWO (min) , and I AWO > I AWO (min), the cycle is a read
modify-write cycle and data from Ihe selected cell will apper al
the Doul pin. If neither of the above conditions is satisfied, the
cycle is a delayed write cycle and invalid data will appear the Dout
pin , and write operation can be exacted by satisfying ~ ,I
CWL ,and IRAt specifications.

8.

If tRAO 2: tRAO (max) and ....sc ~ 1M - tCAC - t T , access time is

16 tePA is access time from the selection of a new column address
(thaI is caused by changing ~ from 'L"lo "H"). Therefore, if

9.

tAA .
Measured with a load equivalenl to two TIL loads and 100 pF.

tep is long, tePA is longer than k:PA (max).
17. Assumes that ~ --before- ~ refresh.

t T , access time is IcAc .

10. toFF and toEZ is specified that output buffer change to high
impedance state.

2-193

MBS14100-S0
MBS14100-10
MBS14100-12

Fig. 3 -I RAe va. \lAD

Fig. 2 -I RAe va. \lco

1 RAC (ns)

160

t RAe (ns) 160

140

140

120

120

100

100

80

80

,~.,-/
lOOns Version

---Y'I

80ns Version

I
I
I

60

1: I

20

I
I
I

60

I II

40

1'1

60

80

I

I

100 120

'1:

•

I I
I I
II

II I I

20

1 Reo (ns)

40

60

I

80

I

100

I

120

•

1 RAO (ns)

FUNCTIONAL TRUTH TABLE

L

Hidden Refresh
Cycle

Valid

Valid

Valid

Valid

Valid

X-+
Valid

L

L

Valid

L

H

Valid

L

L

H-+L

L

Not.. :
X: 'H'or'L"
'1: It is impossible in Fast Page Mode.

2-194

L

Valid

0'1

t RCS:l< t RCS (min)

High-Z

0'1

t wcs:l< t wcs(min)

Valid

0'1

t cwo :l< t CWO (min)

High-Z

0

H

High-Z

0

t CSR:l< t CSR

H

Valid

0

Previous data is
kept

(min)

MB814100-S0
MB814100-10
MBS14100-12

Fig, 4 - READ CYCLE

t RC
t RM
RAS
tCSH
t RSH
CAS

tCAS

V1H V 1L -

tRA!.

Ao to A,o

WE

Dour

V1H V 1L -

V1H V1L -

VOH VOL _

tM

I~·~-----tc~ ------~
- - - - - - - HIGH-Z---------::l InvaJ~ Data
DESCRIPTION
The read cycle is executed by keeping both AAs and~ 'L' and keeping WE 'H' throughout the cycle. Therow and column addresses are
latched with RAS and CAs, respectively. The data output remains valid with CAS 'L", ie., if CAs goes 'H' , the data becomes invalid after tOH
is satisfied. The access time is determined by AAs (tRAC), CAS (tCAC), or Column address input (tAA). IftRCD (RAS to CAS delay time)i.
greater than the specification, the access time is tAA.

2-195

MBS14100-S0
MBS14100-10
MBS14100-12

Fig" 5 -

WRITE CYCLE ( Early Write)

tAC
t RAS
RAS

V IH V IL tCSH
t RSH

-\

tR~

tcAS
CAS

V IH V IL tRAL

A otoA 10 VIH VIL -

WE

DIN

DOUT

V IH V IL -

VALID
DATA IN

VOH VOL -

HIGH-Z

11fu~111 "H" or~"
DESCRIPTION
The write cycle is executed by the same manner as read cycle except for the state of We and DIN pins. The data on DIN pin isatchedwith the
later falling edge of CAS or WE and written into memory. In addition, during write cycle, tRWL and tRAL must be satisfied with the
specifications.

2-196

MBB14100-BO
MBB14100-10
MBB14100-12

FIg, 6 - READ WRITEIREAD-MODIFY-WRITE CYCLE

VIH-

RAS

VIL-

VIH_

CAS
VIL-

AotoA10

VIHVIL-

WE

VIHVIL-

DIN

VIHVIL-

DOUT

VOH-

VOL-

II

'H'or'L'

(::>:::>:I,nvall'Idanco elreul.

Cq>yrighl© 1989 by FUJITSU LIMITED

2-207

MB814400-80
MB814400-10
MB814400-12

Fig. 1 - MB814400 DYNAMIC RAM - BLOCK DIAGRAM

AO
AI
A2
DOl to
DQ4

A3
A4
AS
A6
A7
AS
A9

Input Capacitance, AO to A9
Input Capacitance, RAS, CAS, WE,

OE

InpuVOutput Capacitance, DOl to D04

2-208

Coo

5

pF

5

pF

6

pF

MB814400-80
MB814400-10
MB814400-12

PIN ASSIGNMENTS AND DESCRIPTIONS
2D-Pln DIP:

26-PlnSOJ:

(TOP VIEW)

(TOP VIEW)

001

VSS

002

004

~

001
002

:

WE
"'RAS

WE

003

RAS

CAS

A.

OE

AO

A 8

AI

A 7

AO

A2

A.

AI

A3

A 5

~

VsS
004

003

4

2'
23

CAs"

5

22

OE

:•

18

A 8

10

17

A 7

A 6

11

16

12

15

A 5

[

13

14

A4

A3

A4

A3

A.

28
25

3

A. [

A2

Vee

1
2

Vec

2o-PinZIP:
(TOP VIEW)

CAS
DE

003

004

001

V SS

WE

002

A.

RAS

AI

AO

A2

V cc

A6

A5

A8

A7

RECOMMENDED OPERATING CONDITIONS

o :

Supply Voltage

[D

Input High Voltage, all inputs

[D

VIH

2.4

6.5

V

Input Low Voltage, all inputs

[D

VIL

-2.0

0.8

V

Input Low Voltage, DO( 0)

[D

VILD

-1.0

0.8

V

o °c to +70 °c

Undershoots of up to -2.0 volts with a pulse width not exceeding 20no are acceptable.

2-209

MBS14400-S0
MBS14400-10
MBS14400-12

FUNCTIONAL OPERATION
ADDRESS INPUTS
Twenty input bits are required to decode any four of 4,194,304 cell addresses in the memory matrix. Since only ten address bits are available, the
column and row inputs are separately strobed by~ andlUiS as shown in Figure 1. First, ten row address bits are input on pins AO-through-A9 and
latched with the row address strobe ~ ) then, ten column address bits are input and latched with the column address strobe ~). Both row and
column addresses must be stable on or before the falling edga o~ andlUiS , respectively. The address latches areofthe flow-through type; thus,
address information appearing after IRAH (min)+ tr is automatically treated as the column address.

WRITE ENABLE
The read or write mode is determined by the logic state of we . When We is active Low, a write cycle is initiated; when we is High, a read cycle is
selected. During the read mode, input da.ta is ignored.

DATA INPUT
Input data is written into memory in either of three basic ways-an eariy write cycle, anOE (delayed) write cycle, and a read-modify-write cycle. The
falling edge of we or ~ , whichever is later, serves as the input data-latch strobe. In an eariy write cycle, the input data (DQ1...JJ04) is strobed by
~ and the setuplhold times are referenced to ~ because we goes Low before~ .In a delayed write or a read-modify-writecycle, WE goes
Low after ~ ; thus, input data is strobed by we and all seruplhold times are referen09d to the write-enable signal.

DATA OUTPUT
The three-state buffers are TTL compatible with a fanout of two TTL loads. Polarity of the output data is identical to that of the input; the output buffers
remain in the high-impedan09 state until the column address strobe goes Low. When a read or read-modify-write cycle is executed, valid outputs are
obtained under the following conditions:
IRAC :

from the falling edge oflUiS when tACO (max) is satisfied.

ICAC:

from the falling edge of~ when tRcO is greater than tRCO (max).

IAA

:

IOEA:

from column address input when!RAo is greater than tRAO (max).
from the falling edge of OE when OE is brought Low after tRAe , !cAe , or 1M

The data remains valid until either ~ or OE rerums to a High logic level. When an early write is executed, the output buffers remain in a
high-impedance state during the entire cycle.

FAST PAGE MODE OF OPERATION
The fast page mode of operation provides faster memory access and lower power dissipation. The fast page mode is implemented by keeping the
same row address and strobing in successive column addresses. To satisfy these conditions,lUiS is held Low for all contiguous memory cycles in
which row addresses are common. Foreachfastpage of memory, any of 1,02~its can be accessed and, when multiple MB 814400s are used,~
is decoded to select the desired memory fast page. Fast page mode operations need not be addressed sequentially and combinations of read, write,
and/or ready-modify-write cycles are permitted.

2-210

MB814400-80
MB814400-10
MB814400-12

DC CHARACTERISTICS
(Recommended operating condHlons unless otherwise noted)

Input leakage current (any input)

II(L)

Output leakage current

IDQ(L)

Operating current
(Average Power
supply current)

Standby current
(Power supply
current)

1=

Icc.

Fast Page Mode
current

1CC4

Refresh current #2
(Average power supply current)

Icc5

I2J

-10

10

-10

10

RAs & CAs cycling;
ICCl

Refresh current #1

I2J

OVSVou-r.;; 5.5V;
Data out disabled

Notes 3

mA

tAC = min

AAs=CAS :2:Vcc ~.2V

mA
1.0

~ = VIH, ~ cycling;

mA

tRC = min

llAS =VIL,

~ cycling;

tpc = min

mA

RAscycling;

m-before-m;
tAC = min

mA

2-211

MBS14400-S0
MBS14400-10
MBS14400-12

AC CHARACTERISTICS

2-212

MBS14400-S0
MBS14400-10
MBS14400-12

Notes:
1. Referenced to VSS.
2. Icc depends on the output load conditions and cycle rates; The
specified values are obtained with the output open.
Icc depends on the number of address change as 1lA!l = VIL and
' m = VIH. VIL > -a.sv.
Icc1, 1= and Iccs are specified at three time of address change
during 1lA!l = VIL and ' m = VIH.
Icc. is specified at one timeof address change during 1lA!l = VIL
and'm=VIH.
3. An Initial pause (1lA!l ='m =VIH) of 200~ is required after
power-up followed by any eight 1lA!l-only cycles before proper
device operation is achieved. In case of using internal refresh
counter, a minimum of eight ' m -before-1lA!l initialization
cycles instead of 81lA!l cycles are required.
4. AC characteristics assume tr = 5ns.
5. V IH (min) and V IL (max) are reference levels for measuring
timing of input signals. Also transition times are measured
between VIH (min) and VIL (max).
6. Assumes that tRCD~ tReD (max), tRAD~ tRAD (max). If tRCD is
greater than the maximum recommended value shown in this
table, IRAC will be increased by the amount that IRCD exceeds the
value shown. Refer to Fig. 2 and 3.
7. IftRCD~tRCD (max), lRAD~tRAD (max),andtASc~1AA -ICACt T , access time is !cAe .

8. IftRAD ~ tRAD (max) and IAsc ~ tM - tCAe - t T , access time is
1M.
9. Measured with a load equivalent to two TTL loads and 100 pF.
10. tOFF and toez is specified that output buffer change to high
impedance state.
11. Operation within the IReD (max) limit ensures that tRAe (max)
can be met. IRCD (max) is specified as a reference point only; if

tRCD is greater than the specified IReD (max) limit, access time is
controlled exclusively by !cAe or I AA •
12. IReD (min) = IRAH (min)+ 21T + lAse (min).
13. Operation within the IRAD (max) limil ensures that tRAe (max)
can be met. IRAD (max) is specified as a reference point only; if
IRAQ is greater than Ihe specified IRAD (max) limit, access time is
controlled exclusively by !cAe or t M .
14. Either tRRH or IRCH must be satisfied for a read cycle.
15. !wes isspecifiedasareferencepointonly.lftwcs ~twcs (min)
the data output pin will remain High-Z stale through entire cyele.
16. Assumes that twcs  t RCO (max), access time - t CAe.
RAD > t RAO (max), access time - t M.

t RCD
t

• If DE is brought Low after t RAe. I CAe or t AA (which aver occurs later). access time .. t DEA.
CAs or DE goes High, the output returns to a high-ln'll8dance state after t OH Is satisfied.
I

However. If either

2-215

MBS14400-S0
MBS14400-10
MBS14400-12

Fig" 5 - EARLY WRITE CYCLE (OE

= "H" or "L")

tAC
tAAS
RAS

V'HV'L_
tCSH
t RsH
t CAS

CAS

V'HV'L tRAL

Aoto A.

V'HV'L-

WE

DO

VALID
DATA IN

(Input)

DO
VOH (Output) VOL _

- - - - - - - - - - - - - - - - HIGH-Z

11;::::1
DESCRIPTION

WE Is set to a Low state and '6E Is a ~H· or"L" signal. A write cycle can be irrplemented
DE write (delayed write). or read-modlfy-wrtte. During all write cycles, timing parameters 1 RWL •
mutt be satisfied. In the early wr~a cycle shown above t wes satisfied. data on the 00 pins Is latched with the Iaillng

A write cycle Is similar to a read cycle except
In ehher of three ways - early write.
1 CWL and

edge of

2-216

CAs

t RAL

and written into memory.

"H" or"L"

MBS14400-S0
MBS14400-10
MBS14400-12

Fig. 6 -

OE (DELAYED WRITE CYCLE)

t-------------

I RC

VrH -

RAS

V rL -

V rH -

CAs'

V rL -

V rH -

Aoto""

V rL -

V rH -

WE

V rL -

DO

V rH -

(Inpul)

VrL -

DO

VOH -

(Outpul)

VOL -

V rH -

OE

V rL -

IJM~I1)1 ·H~ or-e
•

DESCRIPTION
In the

De

rTl91"1'1Of)'.

(delayed write) cyde, I wcs Is not satisfied; thUB, the data on the DO plna II latched with the falling edge of

We

Invalid Data

and written Into

TheOutpul Enable (OE) signal must be changed from Low to High before WE goes Low (I OEO + IT + t OS).

2-217

MB814400-80
MB814400-10
MB814400-12

Fig, 7 - READ-MODIFY-WRITE-CYCLE

~-----------------------t~----------------------

__~

V IH -

RAS

CAs

V IL -

V IH V IL -

V IH _

Aoto-'g

V IL -

WE

V IH V IL -

DO

V IH -

(Input)

V IL -

DO

V OH -

(Output)

VOL -

FE

V IH _
V IL _

IIU

DESCRIPTION
Tho read-illOdWy-wlIlo O)'cie Is exoculed by changing

WE

Irom High to Low after the data - " ' " on !he oa pins. In the read-modif)'-'Nrlle

cycle. OE: must be changed from Low to High after the memc.wy access time.

2-218

'H" or'L'

MB814400-80
MB814400-10
MB814400-12

Fig" 8 - FAST PAGE MODE READ CYCLE

RAS

V1H V1l -

CAS

V1H V 1l -

Aoto\

V1H V1l -

V 1H _

WE

V1l -

DO
(Inpul)

V1H -

DO
(Outpul)

OE

V1l -

VOH
VOL

V 1H V 1l -

IMII

"H" or "!."

1<:;:,':;:)

VaMd Data

DESCRIPTION
The fast page rmde of operation permits faster sUCC88&N8 memory operations at mult~le column locations at the same rrJN address. ThtB
operation Is performed by strobing in the row address and maintaining

RAS

81 a low 'eYe! and

WE at a High IeYeI during allsUCC888lve

merrory cycles In which the raw address Is latched. The access time Is determined by t CAe • t AA '

t CPA • or t OEA • whlchevel" one

is the latest In occurlng.

2-219

MBS14400-S0
MBS14400-10
MBS14400-12

Fig. 9 - FAST PAGE MODE WRITE CYCLE (OE = "H" or "L")

~-----------------------t~ ------------------------~

CAS

DO

V rH -

(Input)

VrL -

DO

VOH -

HIGH-Z

(Output) VOL _

DESCRIPTION
The fast page mxIe wr~e cycle " executed In the sams manner as the fast page mode read cycle except the states or
Data appearing on the DO pins Is latched on the failing edge of

CAS

the delayed (OE )wrhe and read-modlfy-wrke cycles, I CWI.. mJst be satisfied.

2-220

WE

and

OE

are reversed.

and wrlnan Into memory. During the fast page mode write cycle, Including

MBB14400-BO
MBB14400-10
MBB14400-12

Fig. 10 -

FAST PAGE MODE OE WRITE CYCLE

V 1H -

RAS
V 1L -

V 1H V 1L _

CAS

V 1H -

Aoto-\
V 1L -

V 1H -

WE
V 1L -

V 1H -

DO
(Input)

V 1L -

V OH -

DO
(Output)

VOL -

V 1H -

OE
V 1L -

I;II

"H"o'"l"

•

Invalid Data

DESCRIPTION
The fast page mode

DE.

Oe

(delayed) wrile cycle Is executed in the same rranner as the fast page mode write cycle except for the states of

We

and

Oe

must be changed from Low to High before

Input data on the DO pins are latched on the failing edge of

WE g086low(t OED

WE and written Into memory. In the fast page mode delayed wrhe cycle,

+ IT + t OS)·

2-221

MB814400-80
MB814400-10
MB81440Q-12

Fig. 11 - FAST PAGE MODE READ-MODIFY-WRITE CYCLE

"i'iAs

CAS

Ao to Ag

V'HV'L _

V'HV'L -

V'HV'L -

WE

V'HV'L _

DO

V'H-

(Input)

V'L -

DO

VOH-

(Output)

VOL -

OE

V'HV'L-

DESCRIPTION
During fast page mode of operation. the J'8ad.-m)dify-wrfte cycle can be executed by sw1tchlng
the DO pins during a normal cycle.

2-222

WE

from High to low after input date appears at

[!~~~:frjl

-H- or"L"

t~~~'~~<1

Valid Data

MBS14400-S0
MBS14400-10
MBS14400-12
Flg.12-

RAS-ONLY REFRESH (WE

=OE ="H" or "L")

~--------------------tRC --------------------~

~--------.....;l("" 101>----- tRP ----101

DO

VOH

(Output)

VOL

----------------~----------------HIGH-Z---------------------

DESCRIPTION
Refresh d RAM mermry cells Is accoft1)Mshad by performing a read, a write. or a read--f'nJdify-write cycle at each ot 1024 reM' addresses every
16.4-milliseconds. Three refresh modes are available:AAs -only refresh,

RA'S-only refresh Is performed by keeping

RAS

Low and

CAS

CAS --before--RAs

refresh. and hidden refn:mh.

High throughout the cyda; the raw address 10 be refreshed is latched on the

falling edge afRAs . During RAS-only refresh. DO pins are kept in a high--ifTl>edan09 state.

Fig. 13 - CAS-BEFORE-RAS REFRESH (ADDRESSES

'I'tliS"

V'HV'L -

~

V'HV'L -

wr

V'HV'L -

= OE = "H "or "L")

V OH
DO
(Output) VOL
DESCRIPTION
CAS-before-RAS refresh Is an on-chlp refresh capability that eMmlnates the need 104" external refresh addresses. If CAS Is Ileld Low for the
specWied setup time ( t CSR ) before""RAS goes Low, the on-cnip refresh control clock generators and refresh address oounter are enabled. An
internal refresh operation automatically occurs and the refresh address counter Is Internally Incremented in preparation for the next

CAs --before-RAS refresh operation.
WE must be held High for the specified set up tIme (tWSA) before AAS goes Low in order not to enter "test mode- to be specified later.

2-223

III

MB814400-80
MB814400-10
MB814400-12

Fig. 14 - HIDDEN REFRESH CYCLE

14------- -------J.o. . . ----t RC

_ _ _~ 1---- tRAS
V'H-

R'As

V'L -

V'HCAS
V'L -

Ao to

Ag

V'HV'L _

V'HWE

V'L -

DO
(Input)

DO
(Output)

V'HV'L -

VOH VOL -

VALID DATA OUT

V'HV'L _

OE

DESCRIPTION
A hidden refresh cycle may be performed while maintaining the latest valid data at the output by extending the active time of CAS and
cycling

Ms.

The refresh row address Is provided by the ort-ehlp refresh address counter. This eliminates the need for the external ffYrN address

CAS -before-RM refresh C8pCt)illty.
WE must be held High for the specified sat up tima (tWSR) before RAS goes Low In order not to enter "test mode- to be speclfled later.
that Is required by DRAMs that do not have

2-224

MB814400-80
MB814400-10
MB814400-12

PACKAGE DIMENSIONS
(Suffix : -P)

20-LEAD PLASTIC DUAL IN-LINE PACKAGE
(Case No. : DIP-20P-M03)

IH

J={

IH

J={ J={ J={

, ! '

.050(1.27)

M~ '-

v

HHM

~I 01U8+,~06

U
100(2.54).'
TYP

© 1988 FUJITSU LIMITED D20011S-1e

-.002

(045~g6~)

~'197(5'00)

MAX

.12~3.18)MIN
,020(0.51) MIN

Dimensions in
inches (millimeters)

2-225

MBS14400-S0
MBS14400-10
MBS14400-12

PACKAGE DIMENSIONS

(Continued)

(Suffix: -PJN)
26-LEAD PLASTIC LEADED CHIP CARRIER
(Case No. : LCC-26P-M04)
•

.089(2.2S) NOM.
.02S(0.64) MIN.

@
]

o
,
.OSO±.OOS
(1.27±O.13)

.140(3.SS) MAX.

.67S±.00S
(17.1S±0.13)

__

.332±.00S
(8.43±0.13)
.300( .62)
NOM.

,

~ ~'1~0~~~2~S4)
TYP
__

f--------:.600( lS.24) REF.

;-- --D~~iIS ~f·:"A-;-· ~~;--1
I
I

I

.032(0.81) :
MAX
I
I

I
I
I

I
I

I

.017±.004

I

L______(<:4::<: ~~_j

NOTE: 1.• : This dimension includes resin protrusion. (Each side: .006(0. lS)MAX)

© 1989 FUJITSU LIMITED C26054S-1C

2-226

2,Although this package has 20 leads only, its pin positions are the same as

that of 26-lead package. Foot-print compatible with "SOJ-26':,. (lCC-26C-A01)

MB814400-80
MB814400-10
MB814400-12

PACKAGE DIMENSIONS

(Continued)

(Suffix : -PJ)

26-LEAD PLASTIC LEADED CHIP CARRIER
(Case No. : LCC-26P-M03)

*

15213 85) MAX

.675±.005
117.15±0.13)

.09412.40) NOM
.02510.64) MIN

r--~I
.318± .020
18.08±0.51l

~6b~
Lead No.

1

_I

I..

11.27±0.13)

r---------------l

i

100d2.54).

Details of "A" part

I
I
I

TYP

.600115.24) REF

.03210.81)
MAX

I
I
I

"A"

I
I
I
I
I
I
I

I

I

I
I

I
I

I
I
I

oil'

.Ol7±.004

I
:
I

L______ ~~~~o~~~_J
© 1988 FUJITSU LIMITED C26053S -1 C

* Remaining

Resin

.006(0.15) MAX

Dimensions in
inches (millimeters).

2-227

MB814400·80
MB814400·10
MB81440Q-12

PACKAGE DIMENSIONS

(Continued)

(Suffix : -PSZ)

20-LEAD PLASTIC ZIG-ZAG. IN-LINE PACKAGE
(Case No. : ZIP-20P-M02)

112± 008
(2.85±0.20)

I

0

INDEX
o/

1

335 ± 0 10
.
.

(8.50±0.25)

~~~~~ffiffi~~~
.010±.002
(0.25±0.05)

1

.387±.O13
(9.83±0.33)

~~r-~

.118(3.00) MI N

---.-l
.100(2.54) TYP

.050(1.27)
TYP.

(ROW 5 PACE

LEADNO'~~

(BOTTOM~
© 1988 FUJITSU LIMITED Z20002S-4C

Dimensions in
inches (millimeters)

Section 3
Application Specific DRAMs - At a Glance
Maximum
Acceu
Page

Device

Tlme(na)

3-3

MB81461-12
-15

120
150

Capacity

Package
Options

DRAM: 262144 bits
(65536w X 4b)
1016 bits
(256w x4b)

24-pin

Plastic DIP, ZIP

DRAM: 262144 bits
(65536w x 4b)
1016 bits
(256W x4b)

24-pin

Plastic DIP, ZIP

DRAM: 1048576 bits
(262144w x 4b)
2048 bits
(512w x4b)

28-pin
28-pin

Plastic DIP, ZIP
Plastic LCC

SAM:
3-35

MB81461B-12
-15

120
150

SAM:
MB81C4251-10
-12
-15

100
120
150

~9

MB81C4253-10
-12
-15

100
120
150

DRAM: 1048576 bits
(262144w x 4b)
SAM: 2048 bits
(512wx4b)

28-pin
28-pin

Plastic DIP, ZIP
Plastic LCC

3-71

MB81CI501

25

Read: 2350080 bits
(29376Ow x 4b x 2)
Write: 1175040 bits
(29376Ow x 4b xl)

38-pin

Plastic FPT

~7

SAM:

3-1

Application Specific DRAMs

3-2

Dynamic RAM Data Book

11111111111111111111111111111111111111111111111111111111111111111

262144-BIT DUAL PORT

FUJITSU~""~
DYNAMIC RANDOM

MB81461-12
MB81461-15

ACCESS MEMORY
11111111111111111111111111111111111111111111111111111111111111111

July 1987
Edition 3.0

262,144 BIT DUAL PORT DRAM
The Fujitsu MB 81461 is a fully decoded dual port NMOS dynamic random
access memory organized as 65,536 words by 4 bits dynamic RAM port and
256 words by 4 bits serial access memory (SAM) port.
The D RAM port is identical to the Fujitsu MB 81464 with four bits parallel
random access I/O while the SAM port is designed as four 256 bit registers each
operating as a serial I/O. The four serial registers operate in parallel with each
other during SAM port operation. Internal interconnects give the device the
capability to transfer data bi-directionally between the DRAM memory array
and the SAM data registers.
The MB 81461 offers complementely asynchronous access of both the DRAM
and SAM ports except when data is transfered between them internally_
The design is optimized for high speed imd performance which makes the
MB 81461 the most efficient solution for implementing the frame buffer of
a bit mapped video display system. Multiplexed row and column address
inputs permit the MB 81461 to be housed in a 400 mil wide 24 pin DIP and
ZIP. Pin outs conformed to the JEDEC approved pin out.

II

PLASTIC PACKAGE
DIP-24P-M04

The MB 81461 is fabricated using silicon gate NMOS and Fujitsu's advanced
Triple Layer Polysilicon process technology. This process coupled with single
transistor memory storage cells permits maximum circuit density and minimum chip size. All inputs and outputs are TTL compatible.
•

•
•
•

•

•

Dual port organization
•
64K x 4 Dynamic RAM port (DRAM)
256 x 4 Serial Access Memory port
(SAM)
24 pin DIP and ZIP package
Silicon-gate, Triple Poly NMOS,
single transistor cell
DRAM Port
Access Time (tRAcl,
120ns max. (MB 81461-12) •
150ns max. (MB 81461-15)
•
Cycle Time (t RC ),
230ns min. (MB 81461-12)
260ns min. (MB 81461-15) •
SAM Port
Access Time (ts AC ).
•
(MB 81461-121 •
40 ns max.
60 ns max.
(MB 81461-15) •
•
Cycle Time (tsc I,
40ns min.
(MB 81461-12)
60ns min.
(MB 81461-15) •
Single +5V power supply, ±10%
•
tolerance
•

Power Dissipation
DRAM; Act/SAM; Stby
523mW max.(MB 81461-12)
468mW max. (MB 81461-15)
DRAM; Stby/SAM; Act
275mW max.(MB 81461-12)
220mW max.(MB 81461-15)
DRAM; Stby/SAM; Stby
110mWmax.
Bi-directional Data Transfer between DRAM and SAM

PLASTIC PACKAGE
ZIP-24P-M02

Fast serial access asynchronous to

PIN ASSIGNMENT

D RAM except transfer operation
Real Time Read Transfer Capability
Page Mode capability
Bit Masked Write Mode capability
256 refresh cycles every 4ms
RAS-only, CAS-before-RAS and
Hidden refresh capability
Delayed write and Read-ModifyWrite capabil ity
Standard 24 pin plastic DIP
(Suffix; -PI
Standard 24 pin plastic ZIP
(Suffix; -PSZ)

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

Voltage on any pin
relative to VSS
Voltage on

Vee

relative to VSS
Storage Temperature
Power Dissipation
Short Circuit
output current

Symbol

Value

Unit
2

V IN , VOUT
VCC
TSTG

PD
-

-1 to +7
-1 to +7

V
V

-55 to +125
1.0

°c

50

mA

4

6

MO J /SD2 Vss
OC J

8

1(1121416

SOo TRf MOI/RAS

lB

2

A5 Vee AJ

A,

CAS

OE DC,

BOTTOM VIEW

W

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.

3-3

Imllmll~~~mmm~~III~rulmllllmlll
FUJITSU MB81461.12
Im~I~~~~lmmllmlloo~~~~~m~~~ MB81461.15

Fig. 1 - BLOCK DIAGRAM OF MB 81461 and PIN DESCRIPTION
Block Diagram

ID

AO

'-----t--,---oTR/OE

SDO

SD.

SD2

SD3

Pin Description
Pin Number

3-4

DIP

ZIP

1
2.3,22,23

7
8,9,4,6

4

10

5,6,19,20

11,12,1,2

7
8

13
14

17,16,15
14,11,10
9,13

23,22,21,
20,17,16,
15,19

12
18
21
24

Symbol
SAS
SDO to 503
TRIOE

Mode

Parameter
Serial Access Memory Strobe

Serial Data 1/0
Transfer Enablel
Output Enable

Input

1/0
Input

MOOIOaO
to
M03/0Q3
MEIWE

Mask Oata/Oat. 110

I/O

Mesk Mode Enable/Writ. Enable

Input

RAS

Row Address Strobe

Input

Ao to A7

Address Input

Input

18
24
3

Vee
CAS
SE

Supply Voltage +5 V

Power Supply

Column Address Strobe

Input

Serial port Enable

6

VSS

Ground

Input
Power Supply

1111111111111mllllllllllllll~11111111111111111111
MB81461-12 FUJITSU
MB81461-15 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~IIIIIIIII~IIIIIIII

DESCRIPTION
DRAM OPERATION
RAS;
Th is pin is used to strobe eight row-address inputs from AD to A7 pins and is
used to select the operation mode of
subsequent cycle, such as DRAM operation or transfer operation (by TR/OE
and bit mask write cycle or not (by
ME/WE and MOO/DOD to MD3ID03).
Since RAS ; "L" is the active condition
of circuit, to maintain RAS ; "H"
(standby condition) is effective to save
power dissipation.
CAS;
This pin is used to strobe eight column
address inputs at the falling edge. CAS
pin has the function to enable and disable the output at "L" and "H" respectively during the read operation.
Another function of CAS is to select
"early write" mode conditioned by
ME/WE = "L".
ME/WE;
Th is pin is used to select read or write
cycle. ME/WE ; "L" select write mode
and ME/WE = "H" select read mode.
This pin is also used to enable bit mask
write cycle. If ME/WE = "L" at the failing edge of RAS, bit mask write is enabled.
TR/OE;
This pin is used to select Transfer operation or not at the falling edge ofl'fAS,
TRIOE = "H" enables DRAM operation
and TRIOE = "L" enables Transfer
operation between DRAM and SAM.
After the falling of 'FfAS' with t yH , this
pin is used for output enable.
The TRIOE controls the impedance of
the output buffers. TR/OE = "H" forces
the output buffers at high impedance
state. TRIOE = "L" leads the output
buffers at low impedance state. But in
early write cycle, the output buffers are
high impedance state even if TR/OE is
low.
AD to A7;
These are multiplexed address input

pins and used to select 4 bits of 262,144
memory cell locations in parallel within
the MB 81461. The eight row address inputs are strobed by RAS and followed
eight column address inputs are strobed
by CAS. These are used to select the
start address of serial access memory
also.
MDOIDOO to MD3/D03
These are common 1/0 pins of DRAM
port. 1/0 mode is as specified for each
function mode in the truth table.
Data Outputs:
The output buffers have three-state
capability "H", "L" and "High-Z". To
get valid output data on the pins, one of
the read operations is selected such as
"read" or "read-modify-write" mode.
During a refresh cycle, either RAS-only
or CAS-before-RAS mode is selected,
output buffers are set in "High-Z" state.
Data inputs:
These are used as data input pins when a
data write mode such as "Early-Write",
"Delayed Write" or "Read-modifyWrite" is selected. In any of the above
cases, these pins are set at "High-Z"
state to enable data-in without any bus
conflict.
In any operation mode, read, write, refresh, transfer and their combined functions, output states "H", "L", "High-Z"
are set by control signals RAS, CAS,
ME/WE and/or TR/OE. When "Bit mask
write" mode is set, these pins are used
as a control signal for write inhibit with
MDi/DOi ; "L" on the selected bit i.
Page Mode;
The page mode operation is to strobe
the column address by CAS while RAS
is maintained at "L" through all the successive memory operations if the row
address doesn't change. This mode can
save power dissipation and get the faster
access time due to the elimination of
'FfAS' falling edge function.

Refresh;
Refresh of the 0 RAM cells is performed
for every 256 rows per every 4 milliseconds.
The MB 81461 offers the following
th ree types of refresh.
1) RAS-Only refresh; The RAS-Only refresh is performed with CAS="H"
condition. Strobing every 256 row
addresses with RAS will complete all
bits of memory cell to be refreshed
while all outputs are invalid due to
"High-Z" state. Further RAS-only refresh saves the power dissipation substantially.
2) CAS-before-RAS refresh; The CASbefore-RAS refresh offers an alternate refresh method. If CAS is set
low for the specified period (tFCS)
before the falling edge of RAS, refresh C"Ontrol clock generator and refresh address counter are enabled,
and an refresh operation is performed. After the refresh operation
is performed, the refresh address
counter is incremented automatically
for the next CAS-before-R AS refresh.
3) Hidden refresh; The hidden refresh is
performed by maintaining the valid
data of last read cycle at MDIDO
pins while extending CAS low. The
hidden refresh is equ iva lent to CASbefore-RAS refresh because CAS
stays low when RAS goes to low in
the next cycle.
Bit Mask Write;
This mode is used when some of the bits
should be inhibited to be written into
ce lis. The bit mask write mode is executed by setting ME/WE = "L" at the
falling edge of RAS during write mode
(early, delayed write or read-modifywrite cycle). The bits to be masked (or
inhibited to write) is determined by
MDIDO state at the falling edge of 'RAS,
for example, if MDOIDOO and MEIWE
are both low at the falling edge of RAS,
the data on MOO/DOD pin is not written
into the cell during the cycle. Refer to
the Fig. 2.

3-5

mlllllll~~~~m~mllllmlll~III~~mlm
FUJITSU MB81461-12
l~mlll~~~lmllll~lm~I~IIIII~~I~~~1 MB81461-15

EXAMPLE OF BIT MASK WRITE OPERATION
Falling edge of RAS
Function
TR/OE

H

MD2/D02

MD3/D03

X

X

X

L

H

L

ME/WE

MDO/Doo

MD1/DOl

H

X

L

H

Write enable
Write enable for DOO and D02
Write disable for DOl and D03
X. Don t Care

FUNCTIONAL TRUTH TABLE FOR DRAM OPERATION

III

RAS

CAS

ME/WE

TR/OE

ADDRESSES

H

H

X

X

L

H
L*

Valid

Valid Data Out

L

L
L

X
H.... L

MDO/DOO to
MD3/D03
X

H....X

Valid

Valid Data In

L

L

H.... L

H .... X"" H

Valid

Valid Data In
Valid Data Out

H.... L.... H

H.... L
Valid
.... Valid Data In
High·Z
H.... X
X
Row address
H
H.... X
L
High·Z
X
H"'L
X
*: If ME/WE = "L" at the failing edge of RAS, bit mask write mode IS enabled.
L

,

L

L

TRANSFER OPERATION:
Pseudo Write Transfer:
The transfer operation is featured in the . To start serial write cycle, the SD pins
MB B1461B. This mode is used to trans·
must be set in input mode. To do this,
fer simultaneously 256x4 data from
write transfer cycle should be executed.
DRAM to SAM or from SAM to DRAM.
The pseudo write transfer cycle is to
The direction of transfer is determined
change the SD pins into input mode
by the state of ME/WE at the falling
without data transfer from SAM to
edge of RAS. ME/WE="H" defines the
DRAM. Refer to Fig. 3.
transfer from DRAM to SAM (Read
Transfer Cycle) and ME/WE="L" de·
Refresh during transfer cycle;
fines the transfer from SAM to DRAM
DRAM and SAM are refreshed during
(Write Transfer Cycle).
transfer cycle as shown below.
I/O mode of SDO to SD3 determined
1) Read transfer cycle:
while the transfer operation is set (TR/
During read transfer cycle, the
OE="L") conjunctioned with ME/WE
selected row address of DRAM to be
state.
transfered to SAM is refreshed. SAM,
After Read Transfer Cycle, please apply
data are kept by applying 256 SAS:
two or more SAS Clock.
clocks within 4 ms after the read
transfer cycle.
TR/OE;
This pin is used to enable transfer oper. 2) Write transfer cycle:
ation at the falling edge of RAS.
During write transfer cycle, the new
data are written from SAM to DRAM
ME/WE;
This pin is used to select the direction
and this row address should be reo
of transfer at the falling edge of RAS.
freshed within 4 ms.
AOto A7;
But SAM data are not refreshed
These pins are used to seiect the row
during write transfer cycle. There·
address of D RAM port to be transfered
fore, the SAM refresh (applying 256
from or to, and the start address of
SAS clocks within 4 ms) must be
SAM port for the serial read or write
executed. Especially, when the write
operation. The row address is strobed
transfer cycle is executed conti·
by RAS and the start address is strobed
nuously, 256 SAS clock should be
by CAS".
applied within 4 ms.

3-6

Function
Standby
Read
Early Write
Delayed Write
Read·Modify·Write
RAS·Only Refresh
CAS·before·RAS Refresh

SERIAL ACCESS OPERATION:
The MB B1461 has 256 words by 4 bits
Serial Acess Memory (SAM) correspond·
ing to 64K words by 4 bits DRAM and
the fast serial read/write access is
achieved by SAM architecture. Read or
write cycle is determined when the last
read or write transfer operation is exe·
cuted. If the last transfer operation was
read transfer, the serial read cycle is
performed until the next write or
pseudo write transfer cycle is executed.
On the other hand, if the last transfer
operation was write or pseudo write
or pseudo write transfer, the serial write
cycle is performed. In the serial write
operation, 256 words by 4 bits data
stored in the SAM can be transfered to
DRAM under S!:="L" condition, and
SE="H" condition disables data transfer
from SAM to DRAM. The serial access
operation can be done asynchronously
from DRAM port.
SAS;
This pin is used as a shift clock for SAM
port. The serial access is triggered by the
rising edge of SAS. In the write cycle,
the data of the SD pins are strobed by
the rising edge of SAS and written into
the selected cell. In the read cycle, out·

111111111111111111~~IIII~~mm~~llllmlml
MB81461-12
MB81461-15

put data become valid after t SAC from
the rising edge of SAS and the data remain valid until the next cycle is defined. The SAS clock increments the
SAM address automatically. When the
SAM address exceeds #255 (Most Significant Address) it returnes to #0
(Least Significant Address).

SE;
Th is pin is used to enable serial access
operation by bit to bit. S1: = "H" disables serial access operation. In the
serial read operation, this pin is used for
output enable, i.e., SE = "H" leads SD
pins to "High-Z" state. SE = "L" leads
SD pins to valid data with specified access time. In the serial write operation,
this pin works as write enable control
pin.

SOO to S03;
These are used as data input/output pins
for SAM port. Input or output mode is
determined by last occured transfer
operation, if last transfer operation was
read transfer mode, they are output
mode. If the write transfer mode was
set, SO pins are enabled to write data
into SAM.
Refresh;
Since the SAM is constructed by dynamic circuitry, the refresh is necessary
to maintain the data .in it. The refresh
of SAM must be done by 256 cycles
of SAS clock/4ms in either output or
input mode. SE = "H" allows refresh
of SAM with SD pins at "High-Z" state.

FUJITSU

1IIIIml~~~mllllmlllllll~mlllll~lmllll

data continuously when row address is
changed without any timing loss from
the last bit of previous row to the first
bit of new row. Data transfer from
DRAM to SAM is triggered by rising
edge of T R/OE after the preparation of
internal circuit for this operation, while
SAM port can continue read operation
asynch ronously from the above mentioned internal move. Once TR/OE returns to "H" with the restricted timing
specification t TSL and t TSD refered to
SAS clock, SD pins can get the valid
output data continuously as shown in
Fig. 4. The key issue to achieve this
feature is to apply SAS clock continuously with the timing consideration to
the rising edge of TR/OE.

Real Time Read Transfer;
This feature is applicable to obtain valid

FUNCTIONAL TRUTH TABLE FOR SERIAL ACCESS (Asynchronous from ORAM port)
Falling edge of RAS
TR/OE

SAS

I

ME/WE

I

X

SE

Function

SDO to SD3

Sequential access enable
Clock
Input/Output'
L
Sequential access disable
Input/Output'
Clock
H
" The read or write operation of SAM port IS pre-determined by the last occurred transfer cycle. Input mode IS for write
operation. Output mode is for read operation.
H

x; Don't Care

Fig. 2 - EXAMPLE OF BIT MASK WRITE OPERATION
Set mask write mode

MOO/OOO

Masked

M01/DOl

Non masked Write "H"

MD2/DQ2

Masked

MD3/DQ3

Non masked Write "L"

[EJ

Don't Care

3-7

ID

Imllllllml~IIIIIIIIIIIIII~lm~lml~~~m
FUJITSU MB81461-12
11111111~~I~lmlllml~llllm~lml~~111111 MB 81461-15

Fig. 3 - EXAMPLE OF PSEUDO WRITE TRANSFER CYCLE

~=~~"

SAS

so

Serial Read for previous row

serial Write for new row

~ Inhibit of Rising Edge.
*The DRAM data of this row address are refreshed during pseudo write transfer cycle.

Fig.

ADDRESSES

4-

EXAMPLE OF REAL TIME READ TRNASFER OPERATION

----~''-~~''-~~~~.

ME/WE
trSD

SAS

51:

I~
"L" _ _ _ _N_.l_ _

SO (output)

___JX

so~

-.::.."""~-----'~----~""'----

N·2

SI

g

X,-__N_._l_ - - ' ' - -_ _N _ _........
Previous Row

a
3-8

Don'tCare

New Row

1111111111111111111111111111111111111111111111111111

MB81461-12
MB 81461-15

FUJITSU
1111111111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS

(Referenced to Vss)

Parameter

Symbol

Min.

Typ.

Vee

4.5

Max.

Unit

5.0

5.5

V

0

Supply Voltage
Vss

0

0

V

Input High Voltage

V IH

2.4

6.5

V

Input Low Voltage

V IL

-2.0

0.8

V

Operating Temperature

DoC to +70°C

CAPACITANCE (TA=25°C)
Max
Paramter

Symbol

Typ

Unit
DIP

ZIP

Input Capacitance (AD to A7)

C IN1

7

8

pF

Input Capacitance (RAS, CAS, ME/WE, SE, TR/OE)

C IN2

10

12

pF

Input Capacitance (SAS)

C IN3

7

7

pF

Input/Output Capacitance (MOO/DOD to M03/003)

C I01

7

8

pF

Input/Output Capacitance (SOD to S03)

C I02

7

8

pF

AC TEST CONDITIONS

3) Output Load
1) Input

4

VIL =0.8V

tT = 5ns

\~-

2) Output
SDO to SD3
VOH = 2.4V(
}•
HIGH·ZVOL = 0.4 V ' - - - - _ _ _ _ _...1.

Measuring Point

O>------~f
oo,,-..--~

3-9

1111111111111111111111111111111111111111111111111111

FUJITSU

MB81461-12

I I I I I I I I I I I I I I ~I I I I I I I I I I I MB81461-15

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Min

Max

Unit

SAM STANDBY SE; V ,H , SAS; V ,L
OPERATING CURRENT'
Average power supply current
(RAS, CAS cycling; tRc ; min)

MB 81461-12
MB 81461-15

STANDBY CURRENT
Power supply current (RAS ; CAS; V IH)
REFRESH CURRENT1'
Average power supply current
(CAS; V ,H , RAS cycling; tRC ; min)

95
85
Icc2

PAGE MODE CURRENT'
Average power supply current
(RAS; V ,L , CAS; cycling, tpc; min)

MB 81461-12

REFRESH CURRENT 2'
Average power supply current
(CAS-before-RAS; tRC ; min)

MB 81461-12

TRANSFER MODE CURRENT
Average power supply current
(RAS, CAS cycling; t RC ; min)

MB 81461-12

MB 81461-15

20

mA

Icc3
70
50

mA

Icc4
45

77
mA

Icc5
MB 81461-15

MB 81461-15

mA

77

MB 81461-12
MB81461-15

mA

Icc1

70
110
Icc6

mA
100

SAM ACTIVE SE; V ,L , tsc ; min
OPERATING CURRENT'
Average power supply current
(RAS, CAS cycling; t RC ; min)

MB 81461-15

STANDBY CURRENT
Power supply current
(RAS;CAS;V ,H )

MB 81461-15

REFRESH CURRENT1'
Average power supply current
(CAS ; V IH, RAS cycling; tRc ; min)
PAGE MODE CURRENT'
Average power supply current
(HAS; V ,L , CAS cycling, tpc ; min)
REFRESH CURRENT 2'
Average power supply current
(CAS-before-RAS; tRc ; min)
TRANSFER MODE CURRENT
Average power supply current
(RAS, CAS cycling; t RC ; min)

3-10

MB 81461-12

130
mA

Icc7
110

MB 81461-12

50
mA

Icca
40

MB 81461-12

112
mA

ICCg
MB 81461-15

95
85

MB 81461-12
I cc10
MB 81461-15

mA
70

MB 81461-12

112
mA

Icc11
MB 81461-15

95
145

MB 81461-12

mA

Icc12
MB 81461-15

125

1111111111111111111111111111111111111111111111111111

MB81461-12
MB81461-15

FUJITSU
1111111111111111111111111111111111111111111111111111

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Min

Max

Unit

I,(LI

-10

10

p.A

'0 (LI

-10

10

p.A

2.4

INPUT LEAKAGE CURRENT
Input leakage current, any input (OV ~ V IN ~ 5.5V,
Vcc =5.5V, Vss=OV, all other pins not under
test=OV)
OUTPUT LEAKAGE CURRENT
(Data out is disabled, OV ~ VOUT

S

5.5V)

OUTPUT LEVELS
Output high voltage

(IOH =-5mA/-2mA for DQi/SDi)

V OH

Output low voltage

1I0L =4.2mA)

VOL

Note:

V
0.4

Icc is dependent on output loading and cycle rates. Specified values are obtained with the output open.

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.) l~tilil-~--':iI

BM 81461-15

MB 81461-12
Parameter

Bm

Symbol

Unit
Min

Max

Min

4

Max
4

ms

Time between Refresh (RAM/SAM)

tREF

Random Read/Write Cycle Time

t RC

230

260

ns

Read·Modify·Write Cycle Time

t RWC

305

345

ns

Page Mode Cycle Time

tpc

120

145

ns

tpRWC

195

225

ns

Page Mode Read·Modify·Write
Cycle Time
Access Time from RAS

OliJ

t RAC

120

150

ns

AcceSs Time from CAS

IiJliJ

t CAC

60

75

ns

Output Buffer Turn Off Delay

tOFF

0

25

0

35

ns

Transition Time

tT

3

50

3

50

ns

RAS Precharge Time

tRP

RAS Pulse Width

t RAS

120

RAS Hold Time

t RSH

60

100

90
60000

150
75

ns
60000

ns
ns

3-11

II)

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB81461-12
MB81461-15

AC CHARACTERISTICS
MB81461-12
Parameter

Immm

Unit
Min

CAS Precharge Time

MB 81461-15

Symbol
Max

Min

Max

tCPN

40

50

ns

tcp

50

60

ns

tCPR

25

30

ns

CAS Pulse Width

tCAS

60

CAS Hold Time

tCSH

120

tRCO

22

CAS to RAS Set Up Time

tCRs

10

10

ns

Row Address Set Up Time

t ASR

0

0

ns

Row Address Hold Time

(Normal cycle)
CAS Precha rge Ti me
(Page mode only)
CAS Precharge Time
(CAS-befo re-R AS )

RAS to CAS Delay Time

a III

60000

75

60000

150

60

25

ns
ns

75

ns

tRAH

12

15

ns

Column Address Set Up Time

tAsc

0

0

ns

Column Address Hold Time

tCAH

20

25

ns

Read Command Set Up Time

tRCS

0

0

ns

iii

tRRH

20

20

ns

iii

tRCH

0

0

ns

Write Command Set Up Time

twcs

-5

-5

ns

Write Command Hold Time

tWCH

30

35

ns

Write Command Pulse Width

Read Command Hold Time
Referenced to RAS
Read Command Hold Time
Referenced to CAS

twp

30

35

ns

Write Command to RAS Lead Time

tRWL

40

45

ns

Write Command to CAS Lead Time

tCWL

40

45

ns

Data In Set Up Time

tos

0

0

ns

tOH

30

Data In Hold Time
Access Time from TR/OE
TR/OE to Data In Delay Time

3-12

Ii)

tOEA
tOED

35

25

ns
40

35
30

ns
ns

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImili

MB81461-12
MB 81461-15

FUJITSU

11~llllllllllllllllllllllllmlllllllllllllllllllll

AC CHARACTERISTICS
MB 81461-12
Parameter

IIIiBJ

TR/OE Hold Time Referenced to ME/WE
TR/OE to RAS inactive Set Up Time

Unit
Min

Output Buffer Turn Off Delay
from TR/OE

MB81461-15

Symbol
Max
25

Min

Max

tOEZ

0

tOEH

0

0

ns

0

ns

0

30

ns

tOES

0

Data In to CAS Delay Time

Hi)

tozc

0

0

ns

Data In to TR/OE Delay Time

Hi)

tozo

0

0

ns

Refresh Set Up Time Referenced to
RAS (CAS-before-RAS)

tFCS

25

30

ns

Refresh Hold Time Referenced to
RAS (CAS-before-RAS)

tFCH

25

30

ns

tRPc

20

20

ns

tsc

40

RAS Precharge to CAS Active
Time
Serial Clock Cycle Time

50000

50000

ns

Access Time from SAS

1m

tsAc

40

60

60

ns

Access Time from SE

ml

tSEA

40

50

ns

SAS Precharge Time

tsp

10

20

SAS Pulse Width

t SAS

10

20

ns

SE Precharge Time

t SEP

25

45

ns

SE Pulse Width

tSE

25

45

ns

tSOH

10

10

ns

tSEZ

0

tsos

0

0

ns

tSOH

20

25

ns

Serial Data Out Hold Time
after SAS High
Serial Output Buffer Turn Off
Delay from SE
Serial Data In Set Up Time
Serial Data In Hold Time

m
m

25

0

ns

30

ns

3-13

Im~~~m~~mmloo~oo~~oollmlml
FUJITSU MB81461-12
m~~~~~~lllllmllmlm~m~~~III~1 MB 81461-15

AC CHARACTERISTICS
MB 81461-12
Parameter

I&DiI

Unit
Min

Transfer Command (TR) to RAS
Set Up Time

tTs

Transfer Command (TR) to RAS
Hold Time

Max

Min

Max

0

0

ns

tRTH

90

110

ns

tRTHW

12

15

ns

Transfer Command (TR) to CAS
Hold Time

tCTH

30

35

ns

Transfer Command (TR) to SAS
Lead Time

tTSL

5

10

ns

Transfer Command (TR) to RAS
Lead Time

tTRL

130

140

ns

Transfer Command (TR) to RAS
Delay Time

tTRD

-65

-50

ns

First SAS Edge to Transfer Command
Delay Time

tTsD

25

35

ns

ME/WE to RAS Set Up Time

tws R

0

0

ns

ME/WE to RAS Hold Time

t RWH

12

15

ns

Mask Data (MD) to RAS Set Up Time

t MS

0

0

ns

Mask Data (MD) to RAS Hold Time

tMH

35

45

ns

Write Transfer Command (TR) to
RAS Hold Time

IfJ

Serial Output Buffer Turn Off
Delay from RAS

1&

tSDZ

10

Serial Output Buffer Tu rn On
Delay from RAS

III

tSRO

0

0

ns

SAS to RAS Set Up Time

OJ

tSRs

40

60

ns

RAS to SAS Delay Time

III

tSRD

30

45

ns

tszE

0

0

ns

tSDD

60

75

ns

Serial Data Input to SE Delay Time
Serial Data Input Delay from RAS

3-14

MB 81461-15

Symbol

III

60

10

75

ns

~mllll~~I~~~lllllmlllllml~~II~~~m
MB81461-12 FUJITSU
MB81461-15 1IIIIIIIImllmm~mm~mllml~mmlll~

AC CHARACTERISTICS
MB 81461-12

Parameter

I&DiJ

MB 81461-15

Symbol

Unit
Min

Min

Max

Max

Serial Data Input to RAS Delay Time

Iil

tszs

0

0

ns

Pseudo Transfer Command (SE) to
RAS Set up Time

III

tES A

0

0

ns

Pseudo Transfer Command (SE) to
RAS Hold Time

III

tAEH

12

15

ns

t sws

20

30

ns

Serial Write Enable Hold Time

m
m

tSWH

80

120

ns

Serial Write Disable Set Up Time

m

tSWIS

20

30

ns

Serial Write Disable Hold Time

m

tSWIH

40

60

ns

Serial Write Enable Set up Time

Asynchronous Command (TR) to
RAS Set Up Time

tyS

0

0

ns

Asynchronous Command (TFi) to
RAS Hold Time

tYH

12

15

ns

Time between Transfer

Oil

4

tREFT

4

II

ms

NOTES;

D

An initial pause of 200J.ls is required after power-up
fol\owed by any 8 RAS, 8 transfer, and 8 SAS cycle
before proper device operation is achieved. In case of
using internal refresh counter, a minimum of 8 CASbefore-RAS initialization cycles instead of 8 RAS cycle
are required
tl AC characteristics assume
II V IH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are
measured between V IH (min) and VIL (max).
Assumes that tACO::;: tACO (max). If tACO is greater
than the maximum recommended value shown in this
table, tAAC will be increased by the amount that tAco
exceeds the value shown.
Assumes that tACO 2. tACO (max).
Ii) Measured with a load equivalent to 2 TTL loads and
100pF.

lEI

m

fJ

iii

II

IIil

1m

Operation within the t RCO (max) limit insures that
t RAC (max) can be met. tACO (max) is specified as a
reference point only; if tACO is greater than the specified tRCO (max) limit, then access time is control\ed
exclusively by t CAC'.
tACO (min) = tAAH (min) + 2tT (tT=5ns) + tASC (min)
Either tAAH or tRCH must be satisfied for a read cycle.
Measured with a load equivalent to 2 TTL loads and
50pF.
Input mode only

Oil Write transfer and pseuso write transfer only.
lIB Read transfer only in the case that the previous transfer was write transfer.

lEI Pseudo write transfer only.
III If tAEFT is not satisfied, 8 transfer and 8 SAS cycles
before proper device operation is needed.

IIiJ Either tozc or tOZD

must be satisfied.

3-15

Illmmlll~mllllmllllll~~M~~llm~~

Ilm~;~rn.lm :::~::t~~

READ CYCLE

v,

MO/OQ
{OUTPUT!

MO/OQ
II NPUT!

II

Don'tee...

WRITE CYCLE (EARLY WRITE)
V'H_----.U---------'AAS-------l.l~--__L

--t=S~~~~:

V'L--

.'CA

..

__

r--r--

MO/OQ
IINPUT!

__ Don't Cart

Note 1) When MEtWE = "H", all data on the MOtOQ can be written into the cell.
When MEtWE ="L", the data on the MOtOQ are not written (masked) except for when MOtOQ ="H" at the
falling edge of RAS.

3-16

IIIIIIIIIIIIIII~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
MB81461-12
MB81461-15

FUJITSU

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~

DELAYED WRITE CYCLE

RAS

VIH -

VIL tCSH

teRs

CAS
ADDRESSES

tASH

VIH-_-r-----,----.....,t--"'\f-----tcAS;-----1.~.__----VII.. -

~II~ =

ME/we

VIH VIL• -

MDJDa

VIH _

(INPUT)

VIL• -

V,H

-----,+"---.rt-----,----,~------.r--------

VII.. -

Cl

Don't C...

Note 1) When ME/WE = "H", all data on the MD/DQ can be written into the cell.
When ME/WE = "L", th~ data on the MD/DQ are not written (masked) except for when MD/DQ = "H" at the
falling edge of RAS.
Note 2) When TR/OE is kept "H" through a cycle, the MD/DQ are kept High·Z state.
READ·MODIFY·WRITE CYCLE
VIH _-

__~~============~~~~t~"C~==========~~======i
tRAS

V,L -

VIH-'..,.,V--"'---ir-""'-=~~_.lr-.".,..--_ _.,.,=~~~_.,.,,..,...,-ADDRESSES VIL ____.,."......,.__-'I'--.I}-,--,--;-~"-------""'"':""':"-----

ME/WE

MOloa
(lNPUTl

V,H

-,,,,":'~r"--.lr.-+-~-:--i-----~I

VIL -......-''-_~''-'J'

--'""\J,---'"'\
VIL -_..Jl"---_-'f

VIH

~ Don'tC8re

Note 1) When ME/WE = "H", all data on the MD/DQ can be written into the cell.
When ME!WE = "L", the data on the MD/DQ are not written (masked) except for when MD/DQ = "H" at the
falling edge of RAS.

3-17

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB81461-12
MB81461-15

PAGE MODE READ CYCLE

t_A_~-:C----t-Ac----~~----t-As-H-:=J~~

V IH _

CAS

1}-__________________

V 1L -

teAs

teAs

~r---tRP~-

V 1H -

RAS

VIL -

I

~:: ='--'r"""II""tAf'~f"'s":7'l"""'i'--------,---'1'"'"":i"'-{'---....,.---i )..I};=f\-----.,..,---.,---t II
----.-J'

AODR ESSES
MEiwE

V IH -

MDJDQ

V OH -

V,L

l---t AAC

I
I

(OUTPUT) VOL _ - - -

(

H11'GH-Z
tozc

MD/DQ

V1H -

(INPUT)

V 1L

-----;-;--'f

VI H

_.--+---,1,.--,.

fA/DE

V 1L -

o

Don'tCare

PAGE MODE WRITE CYCLE (EARLY WRITE)
tRC- - ...---- ------_. --------- -_._- t R A s
------

-~---:-~
.. ~.----.-... =----~-~~----------

RAS
I}----------------------~
VI H

CAS

-.--Jjt~~I-

--- tASH

tRP

-tCAS-

V1L -

ADDRESSES

~IH
IL-~'r~~~~~~----------/~~"""'i'--------!~,I~~'----------------

VI H

_.--"r---'"'\r"\ III

V,L

-~'}_~_'t\~~--~--------~~----~--~~~--~~------------

MD/DQ
(INPUT)

MD/DQ
(OUTPUT)

----...:".---------------------HIGH-Z~ (\-,- - - - - - - - - - - - - - - - - - -

VO H
VOL -

II

tySr~tYH
TR/OE

~:: =..J

\'-----------1~)I__----

o

Don't Care

Note 1) When ME/WE = "H", all data on the MD/DO can be written into the cell.
When ME/WE = "L", the data on the MD/DO are not written (masked) except for when MD/DO = "H" at the
falling edge of RAS.

3-18

1111111111111111111111111111111111111111111111111111

MB81461-12
MB81461-15

FUJITSU
1111111111111111111111111111111111111111111111111111

PAGE MODE DELAYED WRITE CYCLE
1 - - - - - - - - - - - ~-.-.. ----tRC-·V,H...:-....... t - - - - - · - - - - -

·tRAS-

VIL -

... ..."=,,..-'--'-----

ADDRESSES V1H -,...,.h;:"""~""'-ir---...;;..-u-,=_.,-....:.- (I..

V'L-~~~ff~~~--~--~~~--~~~~~~~~-~---VIH-·'"'"\r--V---.... 1

V'L-~~~~~-~-f~~----~~~-..,~-~~~-----MD/DQ
(INPUT)

V ,H _.-.,--.....,.
V ,L

--'1'-_-.of

V'H

-.-+--""rr-----r-----t----,f---...U .....,---\r------......._____

~EH

V'L-

D

Don't Care

~ Valid Data In

Note 1) When ME/WE = "H", all data on the MD/DQ can be written into the cell.
When ME/WE = "L", the data on the MD/DQ are not written (masked) except for when MD/DQ = "H" at the
falling edge of RAS.
Note 2) When TR/OE is kept "H" through a cycle, the MD/DQ are kept High-Z state.
PAGE MODE READ-MODIFY-WRITE CYCLE
tRC---

V,H _
RAS

V 1L tCSH

CAS

V,H _

--tpc

1--'=+--tCAS

V,l -

V,H -."""\ .......-"--(r.~---il

ME/WE

MD/DQ
(INPUT)

V, L _....J\-_L\!'

V,H-'-fI'""-""""
V,L·-........'lo-_...-i

MOIDO
VOH (OUTPUT) VOL

_--7,--:.:.:.:'-{xm-

v IH---r--.I-"'\ I
VIL -

D

Don't Care

rn

Valid data In

IX!

V,lid data,Out

Note 1) When ME/WE = "H", all data on the MD/DQ can be written into the cell.
When ME/WE = "L", the data on the MD/DQ are not written (masked) except for when MD/DQ = "H" at the
falling edge of RAS.

3-19

IIIII~IIIIIIIIIIIIIIIIIIIIIIIIII~IIIIIIIIIIIIIIIII
FUJITSU MB81461-12
MB81461-15

1111111111111111111111111111111111111111111111111111

~·ONL Y REFRESH CYCLE (iI.lfE/WE=Don't Care)

tRC
tRAS

-

~
~ASRr- H
I AD~~~ssl

VIH
ADDRESSES V 1L

I

~
I---tRP-

~,

"

"

'._:",

~

II

:-,

",# ;

tRPe
',:,
"'

t OFF
MD/DO
(OUTPUT)

-1-1t
,

>

v_,f,'."

HIGH·Z

TRIOE

MD/DO
(iNPUT)

C])

Don't Care

CAS·BEFORE·RAS REFRESH CYCLE (ADDRESS, ME/WE, TRtOE=Don't Care)
~------tRC:----------I

RAS

CAS

V1H VIL -

_--------------~~----tRAS'-----~~----------~

V 1H
VIL -

MD/DQ
VOH _~-----J.
(OUTPUT) VOL _______...t---------------------HIGH-Z---------------

MD/DQ
(iNPUT)

III

3-20

Don'tea ..

MB81461-12
MB 814 61-15

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~IIIIIIIIIII
FUJITSU

1lllllllmllllllllmlllmlm~lllllllmlllmll

HIDDEN REFRESH CYCLE

t------tRc--;-----+---RAS

VIH-.-----.1 1 - - - - t R A S ; - - - I r - - - - - . i IV1L -

CAS"

VIH - ,....--,l---.:.~...J-.f-------+-I---tCAS------___l,..+-V 1L -

tRSH

MD/DQ VOH(OUTPUTI VOL - - - -

MD/DQ
(lNPUTI

tFCH----J

VALID DATA OUT

VIH _,..,---.....t
VIL _...
lI---------HIGH-Z------------

o

Don't Care

3-21

1~I~Mm~~••i
FUJITSU MB81461.12
~lln~~i~~ml~~~~~i~~~~ MB81461.15

READ TRANSFER CYCLE· (MD/DQ =Don't Care)

RA'S

CAs

ADDRESSES

VIH
VIL -

VIH
V 1L

~IH

IL

TF!~

M"E"IWE"

VIH
VIL

SAS

VIH
VIL -

SE

VIH
V1L -

SO

V 1H -

(lNPUTI

VIL -

SO

VOH-

(OUTPUTI

VOL -

Previous row

,I

Newrow

•

•

*: In the case that the previous transfer is read transfer.
**: Ifm: is low, the valid data will appear within t SAC or tSEA'

3-22

Don'tCars

mlmm~~~~m~~~~~~~~~~~~~
MB81461-12 FUJITSU
MB 814 61-15 1IIIIIIIIIIIIIImlllmllllmlllll~II~~llmlll

READ TRANSFER CYCLE* (MD/DQ = Don't Care)

SAS

so

(INPUT)

SO

(OUTPUT)

.Oon'tea..
~ Inhibit of Rising Edga

'; In the case that the previous transfer is write transfer.
"; IfSE is low and the previous cycle is serial write cycle, this should be valid data input.

3-23

~~~~lmm~~~III~I~~II~IIII~
FVJ'ITSV MB81461-12
m~II~lmlml~m~~i~llmll~~1 MB81461-15

WRITE TRANSFER CYCLE" (MD/DQ = Don't Care)

RAS

V1H VIL -

teRs
V 1H

CAS

V 1L

ADDRESSES VIH
V 1L

TRIOE

ME/WE

V1H
V 1L

V1H
VIL

SAS

Sf

SO
(INPUT)
SO
(OUTPUT)

VIH
VIL

VIH
VIL
VOHVOL -

HIGH-Z

*; In the case that the previous transfer is write transfer.
**; If SE is high these data are not written into the SAM.

3-24

III

Don't Care

~

Inhibit of Rising Edge

1111111111111111111111111111111111111111111111111111

MB81461-12
MB81461-15

FUJITSU

IIII~~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

PSEUDO WRITE TRANSFER CYCLE (MOl DQ = Don't Care)

RAS

CAS

VIH
VIL

VIH
ADDRESSES VI L

TRICE

ME~

SE

VIH
VIL

VIL
V IL

VIH
VIL

SAS

SD
(INPUT)

SD
(OUTPUT)

VOH
VOL

•

m

Don't Core
Inhibit of Rising Edge

*: If SE is high, these data are not written into SAM.
**: If SE is high, SD (SDO to SD3) are in High·Z state afterts Ez '

If SE becomes low, the valid data will appear meeting !sAC and tSEA'

3-25

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImllllllllllllili

FUJITSU MB81461-12
111111111111111mlllllll~1111111111111111111111111 MB81461-15

SERIAL READ CYCLE

VIH-

SAS

so
(INPUT)

VIL

---------""""\----...r----

In the case of SE="L" while the operation;

~~PUT) ~::

=---------

HI.GH-Z--------------

~ Invalid Data

3-26

o

Don'tCBre

1111111111111111111111111111111111111111111111111111

MB81461-12
MB81461-15

FUJITSU
1111111111111111111111111111111111111111111111111111

SERIAL WRITE CYCLE

~

~s

f

VIH-________________~
VIL

tRAs-l

tYH

~

______________________

tSWH

tSAS

SAS

tsp

tSAS

VIHV IL I--~~tsc---+__-~tsc

SO
(OUTPUT)

vow- - - - - - - - - - - - - - H I G H - Z - - - - - - - - - - - - - - - V OL -

SO

VIH-

(INPUT)

VIH-

In the case of SE="L" while the operation;

SAS

VIHV IL -

SO

VOH-

(OUTPUT)

V OL -

SO
(INPUT)

VIHV IL -

o

Don'tears

3-27

1111111111111111111111111111111111111111111111111111

FUJITSU

MB81461-12

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~I MB 81461-15

Fig. 5 - CURRENT WAVEFORM (Vee
RAS/CAS CYCLE

RA

CA

fT i\

s

If

-I-

J':fAS·ONLY REFRESH CYCLE

~

TR/OE

PAGE MODE CYCLE

CAS.BEFORE.RAS REFRESH CYCLE

r-r-

.... r- Ift-i\

-r-r- -- -

\1-

Ir-

'---'j'r-~

[\ .JI- ~ f..1 t- -h

\. r-

ME/W E

-

=5.5V, TA =25°C)

,- r-r-

\. --'

l- I-

I

\f-1

r-r-

l- I-'

20 0

I

A

I

160

~

120

1
u
u

If
11\ II

0

0

,.-

111

~

J
II

J1 W

11\

IJ \

I

0

~

\('1

II

I'

[l
J
IL J I Ll r} 111
V l\I _\ I" \J

=5.5V, TA =25°C) (cont'd)

TRANSFER MODE CYCLE

sI-t-

1,- l-

I'-t- l-

sl- I-h

SERIAL ACCESS CYCLE

f\. I- I-ll

l- I-

t- t-I!

1"- r-t-

II

E
TRIOEr-

1'-1- t-

rt- 1\

s
I

1'-

I

20 0

Jr 1'- Ir 1'- Ir 1'-If l.....If

I'i

1\

160

0

".5
u
u

1\

11\

0

0

If

IV

If

1

I\,

I

1\
1\ \

01-"
50ns/dlYIII,on

3-28

lL

50 ns/division

Fig.5 - CURRENT WAVEFORM (Vee

RA

11

{I.
r-

n

, If\.

(t

J

~

1111111111111111111111111111111111111111111111111111

MB81461-12
MB81461-15

FUJITSU
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~I

TYPICAL CHARACTERISTICS CURVES
Fig. 6 - NORMALIZED ACCESS TIME
vs SUPPLY VOLTAGE
w

f=

U)
U)

TA =
tRCD = 20 ns-

1.2

w

u
u

«

"-

1.1

Cl

w

N

1.0

:J

«
:.

0:
Cl
Z

U

w

~5°C

:.

0.9
0.8

«
5-

Fig. 7 - NORMALIZED ACCESS TIME
vs AMBIENT TEMPERATURE

VC~ = 5.dv

:.
f=
U)
U)

r- tRCD = 20 ns

1.2

w

U

'"

~

1. 1

Cl

~ r........

~
:J

1.0

~

0.9

.... ..,.....

«

Cl

z

U 0.8

«

5.0

5.5

-20

6.0

0

20

25°~

:0:
g

TA =

dsoc

I- 100 -tRC =230 ns

0:
0:
::J

0:
0:
::J
U

zw

w

80

U

./

60

f=

w

0

U

40
20

/"

',/"

V
,/

40

o
U

20

f=

11.

0

4.S
5.0
5.5
VCC. SUPPLY VOLTAGE (V)

Fig. 10 - OPERATING CURRENT
vs AMBIENT TEMPERATURE

Fig. 11 -STANDBY SURRENT
vs SUPPLY VOLTAGE

g

3

4

5

6

4

:0:

VJc = 5.L

g

90 r--tRC = 230 ns

TA=JSOC

18

--- -

I-

~

z

0:
0:
::J
U

80

(!)

70

w
0:
0:
::J

-

f=
0:

;iw

~

~

I/tRC. CYCLE RATE (MHz)

:0:

w
0

60

~
2

z
«

- -

80

z

(!)

~

Izw

100

Fig. 9 - OPERATING CURRENT
vs SUPPL Y VOLTAGE

TAl =

11.

80

Fig. 8 - OPERATING CURRENT
vs CYCLE RATE

I- 100 r-vcc =5.5V
z

«

60

T A • AMBIENT TEMPERATURE (OC)

:0:

0:

40

VCC. SUPPLY VOLTAGE (V)

g

z

....

54.5

4

(!)

.........
..,.,.......

60

u

>
-

'"CZ

«
f-

Fig. 13 - REFRESH CURRENT 1
vs CYCLE RATE

14

<"
!

fZ

"- "-

w

IX:

"

:;)

"

i'

!

w

12

IX:

u.

w

w

10

M 20
u

.2

w

<"

T A =J5°C
100 -tRC = 230n.

!

fZ

60

-

40

"--

IX:

40

"w

30

C

w

"
C

..

10

u

4.5
5.0
5.5
Vcc. SUPPLY VOLTAGE (V)

6.0

=~5QC

2
4
6
8
10
I/tpc. CYCLE RATE (MHz)

-

40
30

w

20

N

fZ

w

II:

I-~~

IX:

«
"i
u

TAl = 25°6
100 r-- V cc = 5.5V
80

V

:;)

"w

60

u.

40

:I:

'"

IX:

w

Cl

II:

.;,
u
.2

10

12

Fig. 17 - REFRESH CURRENT 2
vs CYCLE RATE

.s<"

TA
50 -tpc= 120 ns

0

::0

V"

.2

:;)

w

~

20

Fig. 16 - PAGE MODE CURRENT
vs SUPPLY VOLTAGE

zw

6

Cl

;t
4

IX:

.... ........ r-

0

::0

M 20
u

II:

5

T A I=25'6
50 -vcc =5.5V

:;)

.2

f-

4

w

II:

80

w

<"

3

Fig. 15 - PAGE MODE CURRENT
vs CYCLE RATE

IX:

!

2

Fig. 14 - REFRESH CURRENT 1
vs SUPPLY VOLTAGE

(fJ

u.

1

I/tRC. CYCLE RATE (MHz)

IX:

II:

~

-20
0
20
40
60
80 100
TA. AMBIENT TEMPERATURE ('C)

:;)

":I:

.................

.. ~

40

IX:

fZ
II:

60

:I:

(fJ

E

<"

80

II:

(fJ

u

TA 1= 2506
100 r--Vcc = 5.5V

.;

V

V

""

20

.2
4

4.

5~

~5

Vcc. SUPPLY VOLTAGE (V)

3-30

6

2

4

5

I/tRC. CYCLE RATE (MHz)

6

MB81461-12
MB 81461-15

Fig. 18 - REFRESH CURRENT 2
vs SUPPLY VOLTAGE

«

TA =b5°C

.s

...z

w

80

:::>
u

60

a:
a:

-

J:
Vl

w

40

a:

II.

aa:w

80

~

60

o

a:

~

z

a:

...~

20

.nu

2

4

i'jj
a:
a:

6

/1'

~

1

2

2

3

4

5

6

IftRe. CYCLE RATE (MHz)

Fig. 21 - RAM STANDBY/SAM ACTIVE CURRENT
vs CYCLE RATE

----- -

i=

80
60

a:

60

vL=s.L
50 I--TA = 25°C

~

100 i-- tRe = 230 n.

::;:

««
~!

30

gj

20

CI)

::;:u

z

«

a:-

40

a,

./

40

:g ...
~1£
... a:

CI)

.;,
u
2

V

7

w

o

IE«

./

/'

20

>

TA=125°C

w

:f

4.5
5.0
5.5
Vee. SUPPLY VOLTAGE (V)

Fig. 20 - TRANSFER MODE CURRENT
vs SUPPLY VOLTAGE

a
~

40

Vl

w

«
.s
...

T~=25°~
100 -Vee =5.5V

a:

I---- ~

Fig. 19 - TRANSFER MODE CURRENT
vs CYCLE RATE

1...
iii

100 -tRe =230n.

N

~llllllllllml~mlllllllmlllllllllll~~111111
FUJITSU
11~1111111111111111111111111111111~~lml~lm~

/

V

7

V

/'

10

u

2

20
4

4.5
5.0
5.5
Vee. SUPPLY VOLTAGE (V)

6

Fig. 22 - RAM STANDBY/SAM ACTIVE CURRENT
vs SUPPLY VOL TAG£

~5°C

TA =
01-- tse = 40 n.

--

0

~

5
10
15
20
25
Iftse. CYCLE RATE (MHz)

Fig. 23 - RAM STANDBY/SAM ACTIVE CURRENT
vs AMBIENT TEMPERATURE
w

I

>

---

i=
~

~

30

50

~ « 40

-

J

tse = 40 n.
Vee = 5.SV-

!!!. E

>-

:g ...
z1£
«a:
"'a:

Vl:::l

::;:u

30
20

«
a:

B
2

4

4.5
5
5.5
Vee. SUPPLY VOLTAGE (V)

6

10

-20
0
20
40
60
80 100
TA • AMBIENT TEMPERATURE rC)

3-31

1IIIIIIIIIIIIIIIIImlllllllllllllllllllllillmlili

FUJITSU

MB81461-12

1~~~~llllllllllmllllllllllllmlllllmlmlll MB 81461-15

Fig. 24 - ADDRESS AND DATA (DO AND SO)
INPUT VOLTAGE vs SUPPL V VOLTAGE
3.0

Fig. 25 - ADDRESS AND DATA (DO AND SO)
INPUT VOLTAGE vsSUPPL V VOLTAGE
3.0

TA=2~OC

~ -

f-=--

~
V IL (Max.)

o

r-

V IH (Min.) Vee = 5.5V

~

V IL (Max.) Vee = 4.5V

-

o
4

4.5
5.0
5.5
Vee, SUPPLY VOLTAGE (V)

6

Fig. 26 - RAS, CAS, ME/WE, TR/OE, SE, SAS
INPUT VOLTAGE vs SUPPL V VOLTAGE
3.0

-20
0
20
40
60
80 100
T A , AMBIENT TEMPERATURE (OC)

Fig, 27 - RAS, CAS, ME/WE, TR/OE, SE, SAS INPUT
VOLTAGE vs AMBIENT TEMPERATURE
3.0

TA=25J C

-

-

V IH I(Min.)

r-

V IH (Min.) Vee = 5.5V

.....::::...-

L
V IL (Max.!

~ VI L (Max.) Vee

=

4.5V

-

i

">

o

o
4

4.5
5.0
5.5
Vee, SUPPLY VOLTAGE (V)

6

-20
0
20
40
60
80 100
T A , AMBIENT TEMPERATURE (OC)

Fig. 28 - ACCESS TIME (RAM)
vs LOAD CAPACITANCE
25

V~e = 4.~V
"

Ul

20 - TA =2.5°C

S.
w
:;;

w

:;;

i=

15

/

en
en
w 10
U
u

«

U

5

;:;

0

/~

<
II:

/

V

'"
100 200 300 400 500
CL, LOAD CAPACITANCE (pF)

3-32

Fig. 29 - ACCESS TIME (SAM)
vs LOAD CAPACITANCE

i=

20

./

15

en

'"uuw

«
U
<

1!'

~

10

./

5
0

/'

V

,/

V

V"

50
100 150 200 250 300
CL , LOAD CAPACITANCE (pF)

1111111111111111111111111111111111111111111111111111

MB81461-12
MB 81461-1 5

Fig. 30 - DO OUTPUT CURRENT
vs DO OUTPUT VOLTAGE

.§.

TAl25°C

!z

I-

zw 200

a:
a:

:::J

()

I:::J
"I:::J
0
0
0

.:,
5?

200f---+--+---+---I---I

w

a:
a:

150

)E-

100
50

Fig, 31 - SO OUTPUT CURRENT
vs SO OUTPUT VOLTAGE

"<

~

.§.

FUJITSU

IIIIIIIIIIIIIIIIIIIIII~IIIIIIIIIIIIIIIIIIII~IIIIII

/.~ ""

Vee = 4.5V

a 150f---+--+-- -+_-_-5.5--I---I
v -ee

V

I:::J
"I:::J

o

o

"'.:,

V

o

o
o

4
2
3
5
VOL, DO DUTPUT VOLTAGE IV)

Fig. 33 - SO OUTPUT CURRENT
vs SO OUTPUT VOLTAGE

Fig. 32 - DO OUTPUT CURRENT
vs DO OUTPUT VOLTAGE

"<

"<

.§.

.§.

!z -100·/--:--+--+---+---+---\

!z -100f--t--+--+--+---;

a:
a:

a:
a:

w

w

:::J

()

i3 - 751-"~t--+--+--+---;

5

I:::J

§"" -50f---+---"1rl-'''r--I---i---i
o

c
:i
o

-25f----i---+--<+'~-i---i

1=
:::J
o
o

"' - 25f---+--~-"k---I---I
J:

o

°O~-+1-~2.-~3.-~4~~5
V OH , DO OUTPUT VOLTAGE IV)

Fig, 34 - SUBSTRATE VOLTAGE
DURING POWER UP

..

,
w

~">

-1

"'w
all!)
:::J «

-2

1--

"'I• ...l

"0
~> -3

>

[II I I I I

~

r\.

'\ , TA =25°C

"'

.......

I--

50 j.£SIDivision

3-33

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB81461-12
MB81461-15

PACKAGE DIMENSIONS
PLASTIC DIP (Suffix: -P)

PLASTIC ZIP (Suffix: -PSZ)
24-lEAD PLASTIC DUAL-iN-LINE PACKAGE
(CASE No.: OIP-24P-M04!

EJECTOR MARK"o

o

I

-m::
__ -

358!.O1O
j9.10!0.251

1t

MAX

I'

.400110;,16ITYP

-

'

I

1 010 >.002

(025-0.05)

I

rZ071S2SlMAX

1 I '''''''M'N
(0.46!0.08)

Q20(O.51 1M AX

p",,,,,,.,on,.,,
,nLh",(mlll"ne!",,)

24·LEAD PLASTIC ZIGZAG-iN-LINE PACKAGE

(CASE No.: lIP-24P-M02)

--._-

I

,.209~·.~',~(30.71~~·5,~1

""

r]

-I

"" _

.112> 008
""'0.20'

m

,F==o===o=e====li 'i~}g;:1I

J,m3

19.8N,331

I

.010'002
10.25'0.05)
,020'.. 004
10.50-0.101

10012.54!L
TYP

I

J

1
.11813001
MIN

Otnwn"n".on
Inch"~ hnllhmetersi

3-34

262144-BIT DUAL PORT

11111111111111111111111111111111111111111111111111111111111111111

FUJITSU ~tiM~~
DYNAMIC RANDOM

MB81461B-12
MB81461B-15

ACCESS MEMORY
11111111111111111111111111111111111111111111111111111111111111111

July 1987
Edition 1.0

262, 144 BIT DUAL PORT DRAM
The Fujitsu MB 81461 B is a fully decoded dual port NMOS dynamic random
access memory organized as 65,536 words by 4 bits dynamic RAM port and
256 words by 4 bits serial access memory (SAM) port.
The DRAM port is identical to the Fujitsu MB 81464 with four bits parallel
random access I/O while the SAM port is designed as four 256 bit registers each
operating as a serial I/O. The four serial registers operate in parallel with each
other during SAM port operation. Internal interconnects give the device the
capability to transfer data bi·directionally between the DRAM memory array
and the SAM data registers.
The MB 81461B offers complementely asynchronous access of both the
DRAM and SAM ports except when data is transfered between them internally.
The design is optimized for high speed and performance which makes the
MB 81461 B the most efficient solution for implementing the frame buffer of
a bit mapped video display system. Multiplexed row and column address
inputs permit the MB 81461 B to be housed in a 400 mil wide 24 pin DIP and
ZIP. Pin outs conformed to the JEDEC approved pin out.
The MB 81461B is fabricated using silicon gate NMOS and Fujitsu's advanced
Triple Layer Polysilicon process technology. This process coupled with single
transistor memory storage cells permits maximum circuit density and minimum chip size. All inputs and outputs are TTL compatible.
Some of the transfer cycle timing specification are different from MB 81461.
• Dual port organization
• Power Dissipation
64K x 4 Dynamic RAM port (DRAM) DRAM; Act/SAM; Stby
256 x 4 Serial Access Memory port
523mW max. (MB 81461 B-12)
(SAM)
468mWmax.(MB81461B-15)
• 24 pin DIP and ZIP package
DRAM; Stby/SAM; Act
• Silicon·gate, Triple Poly NMOS,
275mW max. (MB 81461B-12)
220mW max. (MB 81461B-15)
single transistor cell
• DRAM Port
DRAM; Stby/SAM; Stby
Access Time (tRAd,
110mW max.
120ns max. (MB 81461B-12). Bi-directional Data Transfer be150ns max. (MB 81461B-15)
tween DRAM and SAM
Cycle Time (t RC ).
• Fast serial access asynchronous to
230ns min. (MB 81461 B-12)
DRAM except transfer operation
260ns min. (MB 81461 B-15). Real Time Read Transfer Capa• SAM Port
bility
Access Time (tsAe ).
• Page Mode capability
40 ns max.
(MB 81461 B-12) • Bit Masked Write Mode capability
60 ns max.
(MB 81461B-15) • 256 refresh cycles every 4ms
Cycle Time (ts e ),
• RAS'only, CAS-before-RAS and
40ns min.
(MB 81461B-12)
Hidden refresh capability
60ns min.
(MB 81461B-15). Delayed write and Read-Modify• Single +5V power supply, ±10%
Write capability
• Standard 24 pin plastic DIP
tolerance
(Suffix; -P)
• Standard 24 pin plastic ZIP
(Suffix; -PSZ)

Voltage on any pin
relative to VSS
Voltage on Vee
relative to V S5
Storage Temperature
Power Dissipation
Short Circuit
output current

Symbol

PLASTIC PACKAGE
ZIP-24P-M02

PIN ASSIGNMENT

M02i

ABSOLUTE MAXIMUM RATINGS (See NOTE)
Rating

PLASTIC PACKAGE
DIP-24P-M04

lJa~

Value

:2

V 1N , V OUT

Vee
TSTG

-1 to +7
-1 to +7
-55 to +125

MOol MEl
SD J SAS 501 000 WE 1'06
5
1
9
111315

Sf

Unit
4

6

8

A4
17

1012141618

A7
19

A2
21

Aa

:2

:2

V
V

BOTTOM VIEW

°c

PD

1.0

W

-

50

mA

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATI NGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maximum rated voltages to this high impedance
circuit.

3-35

~~mllmlmmll~lloolllllllllllllllllllml
FUJITSU MB81461B-12
11~lmlllmlmmlll~llml~~~~I~~~~11 MB81461B-15

Fig. 1 - BLOCK DIAGRAM OF MB 81461B and PIN DESCRIPTION
Block Diagram

110

Soo

SOl

So2

So3

Pin Description
Pin Number

ZIP

1

7

2,3,22,23

8,9,4,5

4

10

5,6,19,20

3-36

Symbol

DIP

11,12,1,2

Mode

Parameter

SAS

Serial Access Memory Strobe

SDO to SD3

Serial Oat. I/O

I/O

TR/OE

Transfer Enable/
Output Enable

Input

MDO/DOO
to
MD3/D03

Mask Data/Data I/O

I/O

Input

7

13

ME/WE

Mask Mode Enable/Write Enable

Input

8

14

RAS

Row Address Strobe

Input

17,16,15
14,11,10
9,13

23,22,21,
20,17,16,
15,19

Ao to A7

Address Input

Input

Vee
CAS

Supply Voltage +5 V

Power Supply

Column Address Strobe

Input

12

18

18

24

21

3

SE

Serial port Enable

Input

24

6

Vss

Ground

Power Supply

1~llllllllllllllllmllllllllllllllllllllllllllllll
MBB1461B-12
MB81461B-15

FUJITSU

1~~llllllllllmlllllll~IIIIIIIII~~~I~~11111

DESCRIPTION
DRAM OPERATION
RAS;
Th is pin is used to strobe eight row-address inputs from AD to A 7 pins and is
used to select the operation mode of
subsequent cycle, such as DRAM operation or transfer operation (by TR/OE
and bit mask write cycle or not (by
ME/WE and MDD/DOD to MD3/D03)_
Since RAS ~ "L" is the active condition
of circuit, to maintain RAS ~ "H"
(standby condition) is effective to save
power dissipation_

pins and used to select 4 bits of 262,144
memory cell locations in parallel within
theMB61461B The eight row address inputs are strobed by RAS and followed
eight column address inputs are strobed
by C'AS. These are used to select the
start address of serial access memory
also.
MoO/oOO to Mo3/o03
These are common I/O pins of DRAM
port. I/O mode is as specified for each
function mode in the truth table.

CAS;
This pin is used to strobe eight column
address inputs at the falling edge. CAS
pin has the function to enable and disable the output at "L" and "H" respectively during the read operation.
Another function of CAS is to select
"early write" mode conditioned by
MEiWE; "L".
MEIWE;
This pin is used to .select read or write
cycle. MEM ; "L" select write mode
and MEIWE ; "H" select read mode.
This pin is also used to enable bit mask
write cycle. If ME/WE; "L" at the faIling edge of RAS, bit mask write is enabled.
TR/OE;
This pin is used to select Transfer operation or not at the falling edge of RAS,
TR/OE; "H" enables DRAM operation
and TR/OE ; '~L" enables Transfer
operation between DRAM and SAM.
After the falling of RAS with t yH , this
pin is used for output enable.
The TR/OE controls the impedance of
th~ output buffers. IR/OE ; "H" forces
the output buffers at high impedance
state. TR/OE ; "L" leads the output
buffers at low impedance state. But in
early write cycle, the output buffers are
high impedance state even if TR/OE is
low.
AD to A7;
These are multiplexed address input

Data Outputs:
The output buffers have three-state
capability "H", "L" and "High-Z". To
get valid output data on the pins, one of
the read operations is selected such as
"read" or "read-modify-write" mode.
During a refresh cycle, either RAS-only
or CAS-before-RAS mode is selected,
output buffers are set in "High-Z" state.
Data inputs:
These are used as data input pins when a
data write mode such as "Early-Write",
"Delayed Write" or "Read-modifyWrite" is selected. In any of the above
cases, these pins are set at "High-Z"
state to enable data-in without any bus
conflict.
In any operation mode, read, write, refresh, transfer and their combined functions, output states "H", "L", "High-Z"
are set by control signals RAS, CAS,
ME/WE and/or TR/OE. When "Bit mask
write" mode is set, these pins are used
as a control signal for write inhibit with
MDi/DOi ; "L" on the selected bit i.
Page Mode;
The page mode operation is to strobe
the column address by CAS while RAS
is maintained at "L" through all the successive memory operations if the row
address doesn't change. This mode can
save power dissipation and get the faster
access time due to the elimination of
RAS fall ing edge function.

Refresh;
Refresh of the DRAM cells is performed
for every 256 rows per every 4 milliseconds.
The MB81461 B offers the following
th ree types of refresh.
1) RAS-Only refresh; The RAS-Only refresh is performed with CAS;"H"
condition. Strobing every 256 row
addresses with RAS will complete all
bits of memory cell to be refreshed
while all outputs are invalid due to
"High-Z" state. Further RAS-only refresh saves the power dissipation substantially.
2) CAS-before-RAS refresh; The CASbefore-RAS refresh offers an alternate refresh method. If CAS is set
low for the specified period (tFcs)
before the fall ing edge of RAS, refresh control clock generator and refresh address counter are enabled,
and an refresh operation is performed. After the refresh operation
is performed, the refresh address
counter is incremented automatically
for the next CAS-before-RAS refresh.
3) Hidden refresh; The hidden refresh is
performed by maintaining the valid
data of last read cycle at MD/DO
pins while extending CAS low. The
hidden refresh is equivalent to CASbefore-RAS refresh because CAS
stays low when RAS goes to low in
the next cycle.
Bit Mask Write;
Th is mode is used when some of the bits
should be inhibited to be written into
cells. The bit mask write mode is executed by setting ME/WE; "L" at the
falling edge of RAS during write mode
(early, delayed write or read-modifywrite cycle). The bits to be masked (or
inhibited to write) is determined by
MD/DO state at the falling edge of RAS,
for example, if MDD/DOD and ME!WE
are both low at the falling edge of RAS,
the data on MDD/DOO pin is not written
into the cell during the cycle. Refer to
the Fig. 2.

3-37

D

mll~ru~m~IIIM~rulrumllmll
FUJITSU

MB81461B-12

~~~~llllmllllrulllrull~~I!ruru~~I~~ MB81461B-15

EXAMPLE OF BIT MASK WRITE OPERATION
Falling edge of RAS
Function
TR/OE

ME/WE

MDO/DoO

MOl/DOl

M02/D02

MD3/Do3

H

X

X

X

X

L

H

L

H

L

H

Write enable
Write enable for 000 and 002
Write disable for 001 and 003
X. Don t Care

FUNCTIONAL TRUTH TABLE FOR DRAM OPERATION
RAS

CAS

ME/WE

TR/OE

ADDRESSES

H

H

X

X

L
L

L
L

H
L*

X
H-->L

Valid
Valid

L

L

H-->L

H-->X
H-->X-->H

L

L

H-->L

H-+L-->H

Valid

L

H

X

H-->X

Row address

Valid

MOO/DOD to
MD3/Do3
X
Val id Data Out
Valid Data In
Valid Data In
Val id Data Out
--> Valid Data In
High·Z

High·Z
H.... X
X
X
*: If ME/WE = L at the falling edge of RAS, bit mask write mode IS enabled.
TRANSFER OPERATION:
Pseudo Write Transfer:
The transfer operation is featured in the To start serial write cycle, the SO pins
MB 81461 B. This mode is used to trans·
must be set in input mode. To do this,
fer simultaneously 256x4 data from
write transfer cycle should be executed.
to
SAM
or
from
SAM
to
DRAM.
DRAM
The pseudo write transfer cycle is to
The direction of transfer is determined change the SO pins into input mode
by the state of ME/WE at the falling
without data transfer from SAM to
edge of RAS. ME/WE="H" defines the
DRAM. Refer to Fig. 3.
transfer from DRAM to SAM (Read
Transfer Cycle) and ME/WE="L" de· Refresh during transfer cycle;
fines the transfer from SAM to DRAM
DRAM and SAM are refreshed during
(Write Transfer Cycle).
transfer cycle as shown below.
I/O mode of SDO to SD3 determined
1) Read transfer cycle:
while the transfer operation is set (TR/
During read transfer cycle, the
OE="L") conjunctioned with ME/WE
selected row address of DRAM to be
state.
transfered to SAM is refreshed. SAM
After Read Transfer Cycle, please apply
data are kept by applying 256 SAS
two or more SAS Clock.
clocks within 4 ms after the read
TR/OE;
transfer cycle.
This pin is used to enable transfer oper. 2) Write transfer cycle:
ation at the falling edge of RAS.
During write transfer cycle, the new
ME/WE;
data are written from SAM to DRAM
This pin is used to select the direction
and this row address should be reo
of transfer at the falling edge of RAS.
freshed within 4 ms.
AOto A7;
But SAM data are not refreshed
These pins are used to select the row
during write transfer cycle. There·
address of DRAM port to be transfered
fore, the SAM refresh (applying 256
from or to, and the start address of
SAS clocks within 4 ms) must be
SAM port for the serial read or write
executed .. Especially, when the write
operation. The row address is strobed
transfer cycle is executed conti·
by RAS and the start address is strobed
nuously, 256 SAS clock should be
by'CAS'.
applied within 4 ms.
H-->L

L

II

3-38

Function
Standby
Read
Early Write
Delayed Write
Read·Modify·Write
RAS·Only Refresh
CAS·before·RAS Refresh

"

SERIAL ACCESS OPERATION:
The MB 81461 Bhas 256 words by 4 bits
Serial Acess Memory (SAM) correspond·
ing to 64K words by 4 bits DRAM and
the fast serial read/write access is
achieved by SAM architecture. Read or
write cycle is determined when the last
read or write transfer operation is exe-

cuted. If the last transfer operation was
read transfer, the serial read cycle is
performed until the next write or
pseudo write transfer cycle is executed.
On the other hand, if the last transfer
operation was write or pseudo write
or pseudo write transfer, the serial write
cycle is performed. In the serial write
operation, 256 words by 4 bits data
stored in the SAM can be transfered to
DRAM under SE="L" condition, and
SE="H" condition disables data transfer
from SAM to DRAM. The serial access
operation can be done asynchronously
from DRAM port.
SAS;
This pin is used as a shift clock for SAM
port. The serial access is triggered by the
rising edge of SAS. In the write cycle,
the data of the SO pins are strobed by
the rising edge of SAS and written into
the selected cell. In theread cycle, out·

1I1111111111111111111111mllllllllllillmllllllili

MB81461B·12
MB81461B.15

put data become valid after tSAC from
the rising edge of SAS and the data remain valid until the next cycle is defined. The SAS clock increments the
SAM address automatically. When the
SAM address exceeds #255 (Most Significant Address) it returnes to #0.
(Least Significant Address).

SE;
This pin is used to enable serial access
operation by bit to bit. SE = "H" disables serial access operation. In the
serial read operation, this pin is used for
output enable, i.e., SE = "H" leads SD
pins to "High-Z" state. SE = "L" leads
SD pins to valid data with specified access time. In the serial write operation,
this pin works as write enable control
pin.

SOO to S03;
These are used as data input/output pins
for SAM port. Input or output mode is
determined by last occured transfer
operation, if last transfer operation was
read transfer mode, they are output
mode. If the write transfer mode was
set, SD pins are enabled to write data
into SAM.
Refresh;
Since the SAM is constructed by dynamic circuitry, the refresh is necessary
to maintain the data in it. The refresh
of SAM must be done by 256 cycles
of SAS clock/4ms in either output or
input mode. SE = "H" allows refresh
of SAM with SD pins at "High-Z" state.

FUJITSU
IllImlliOOllllllllllmlllllllllllllllllmllm

data conti nuously when row address is
changed without any timing loss from
the last bit of previous row to the first
bit of new row. Data transfer from
DRAM to SAM is triggered by rising
edge of TR/OE after the preparation of
internal circuit for this operation, while
SAM port can continue read operation
asynchronously from the above mentioned internal move. Once TR/OE returns to "H" with the restricted timing
specification tTSL and t TSD refered to
SAS clock, SD pins can get the valid
output data continuously as shown in
Fig. 4. The key issue to achieve this
feature is to apply SAS clock continuously with the timing consideration to
the rising edge of TRIITi:.

Real Time Read Transfer;
This feature is applicable to obtain valid

FUNCTIONAL TRUTH TABLE FOR SERIAL ACCESS (Asynchronous from DRAM port)
Falling edge of RAS
TR/OE

SAS

I

MEIWE

I

X

SE

Function

SDO to SD3

Sequential access enable
Clock
Input/Output"
l
Sequential access disable
Clock
Input/Output"
H
* : The read or write operation of SAM port IS pre-determined by the last occurred transfer cycle. Input mode IS for write
operation. Output mode is for read operation.
H

x; Don't Care

Fig. 2 - EXAMPLE OF BIT MASK WRITE OPERATION
Sat mask write mode

MDOfOQO

Masked

MOl/DO'

Non masked Write "H"

MD2/DQ2

Masked

MD3/0Q3

Non masked Wriu "L"

III Don't Care
3-39

Imlml~mlilmllllllllillmlllllllllillmill
FUJITSU MB81461B-12
Ilmmlllllllllmllllm~II~lllmlml~lll~ MB 814 61 B-15

Fig. 3 - EXAMPLE OF PSEUDO WRITE TRANSFER CYCLE

/
'\
ADDRESSES

-

--X

Row Add.'

X

/

I

SAM. Start Add. ISO)

X

I

~

/

~

/

,

\

:xB~~~"

SAS

SO

Serial Read for previous row

o

Serial Write for new row

Don'teare

~ Inhibit of Rising Edge.

*The DRAM data of this row address are refreshed during pseudo write transfer cycle.

Fig. 4 - EXAMPLE OF REAL TIME READ TRNASFER OPERATION

ADDRESSES

"'-";;"--'

trSD

\,-_~

SAS

SE"

"L" _ _ _

SO loutput}

~

~:---_~:---_so_~"""o::--

_

.g

___..JX....__N_.2_ _..J ....__N_-l_ _- ' ...._ _ _N_____
Previous Row

CJ

Don't Care

New Row

1111111111111111111111111111111111111111111111111111

MB81461B-12
MB81461 B-15

FUJITSU
1111111111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS

(Referenced to Vss)
Parameter

Symbol

Min.

Typ.

Max.

Unit

Vee

4.5

5.0

5.5

V

Vss

0

0

0

V

Input High Voltage

V ,H

2.4

6.5

V

Input Low Voltage

V ,L

-2.0

0.8

V

Operating Temperature

Supply Voltage
O°Cta +70°C

Max
Paramter

Symbol

Typ

Unit
DIP

ZIP

7

8

Input Capacitance (AD to A7)

C 'N1

Input Capacitance (RAS, CAS, ME/WE, SE, TR/OE)

C 'N2

10

12

pF

Input Capacitance (SAS)

C 'N3

7

7

pF

Input/Output Capacitance (MDO/DOO to MD3/DQ3)

e ,01

7

8

pF

Input/Output Capacitance (SDO to SD3)

C I02

7

8

pF

pF

AC TEST CONDITIONS

3) Output Load
1) Input

4

V ,L

= O.8V

tT

= 5ns

\'----

2) Output
SOO to SD3

VOH = 2.4V(

}-

.
VOL

= O.4V

HIGH·Z' - - - - _ _ _ _-J_

Measuring Point

O~fM,,--.----1Lt=

3-41

1111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111

MB81461B-12
MB81461 B-15

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted'!
Parameter
SAM STANDBY

Symbol

OPERATING CURRENT*
Average power supply current
(RAS, CAS cycling; tRc ~ min)
STANDBY CURRENT
Power supply current (RAS

~

MB 81461B-12

Max

Unit

CAS

~

Icc2

V 1H )
MB81461B-12

PAGE MODE CURRENT*
Average power supply current
(RAS ~ V IL, CAS ~ cycling, tpc

MB 81461 B-12
~

min)

V 1L , tsc

MB 81461B-15

mA

77

MB 81461 B-15

MB81461B-15

~

20

mA

Icc3
70
50

mA

Icc4
45

MB 81461B-12

TRANSFER MODE CURRENT
Average power supply current
(RAS, CAS cycling; tRc ~ min)
~

mA
85

MB 81461 B-15

REFRESH CURRENT 1 *
Average power supply current
(CAS ~ V IH, RAS cycling; tRC ~ min)

SAM ACTIVE SE

95
Icc1

REFRESH CURRENT 2*
Average power supply current
(CAS-before-RAS; tRc ~ min)

77
mA

Icc5
70
110

MB 81461B-12

mA

Icc6
100

MB 81461B-15

min

OPERATING CURRENT*
Average power supply current
(RAS, CAS cycling; tRc ~ min)

3-42

Min

SE~VIH,SAS~VIL

MB 81461B-12

130
mA

IcC7
MB 81461B-15

STANDBY CURRENT
Power supply current
(RAS ~ CAS ~ V 1H )

MB 81461B-12

REFRESH CURRENT 1*
Average power supply current
(CAS ~ V 1H , RAS cycling; tRC ~ min)

MB 81461B-12

MB 81461B-15

110
50
mA

Icca
40
112

mA

ICCg
M881461B-15

PAGE MODE CURRENT*
Average power supply current
(HAS ~ V 1L , CAS cycling, tpc ~ min)

MB 814618-12

REFRESH CURRENT 2*
Average power supply current
(CAS-before-RAS; tRC ~ min)

MB 814618-12

TRANSFER MODE CURRENT
Average power supply current
(RAS, CAS cycling; tRC ~ min)

MB 81461B-12

95
85
mA

I cc10
70

MB 81461B-15

112
Icc11

MB 81461B-15

mA
95
145
mA

Icc12
MB 81461B-15

125

1111111111111111111111111111111111111111111111111111

MB81461B-12
MB81461 B-15

FUJITSU
1111111111111111111111111111111111111111111111111111

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

Min

Max

Unit

Ilill

-10

10

Il A

IO(l)

-10

10

IJ.A

2.4

INPUT LEAKAGE CURRENT
Input leakage current, any input (OV";: V ,N
Vee

~5.5V, Vss~OV,

,,;: 5.5V,

all other pins not under

test~OV)

OUTPUT LEAKAGE CURRENT
(Data out is disabled, OV :S VOUT:S 5.5V)
OUTPUT LEVELS
Output high voltage

(l oH ~-5mA/-2mA for DQi/SDi)

V OH

Output low voltage

(I ol ~4.2mA)

Val

V
0.4

Note: Icc is dependent on output loading and cycle rates. Specified values are obtained with the output open.

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)

11111.....- ·
MB 81461B·12

Parameter

ImDi1

MB 81461B·15

Symbol

Unit
Min

Max

Min

4

Max
4

ms

Time between Refresh (RAM/SAM)

tREF

Random Read/Write Cycle Time

t Re

230

260

ns

Read·Modify·Write Cycle Time

tRwe

305

345

ns

Page Mode Cycle Time

tpc

120

145

ns

tpRwC

195

225

ns

Page Mode Read·Modify·Write
Cycle Time
Access Time from RAS
Access Time from CAS
Output Buffer Turn Off Delay

Elm
mm

tRAC

120

150

ns

t CAC

60

75

ns

0

35

ns

3

50

tOFF

0

25

3

50

Transition Time

tT

RAS Precharge Time

tRP

RAS Pulse Width

tRAS

120

RAS Hold Time

tRSH

60

100

90
60000

150
75

ns
ns

60000

ns
ns

3-43

lID

Imlllllllllllllillmllllillmllllllllllllllllill

FUJITSU
1111111111111111111111111111111111111111111111111111

MB81461B-12
MB81461B-15

AC CHARACTERISTICS
MB 81461B·12
Parameter

I&IiI

CAS Precharge Time

MB 81461B-15

Symbol

Unit
Min

Max

Min

Max

tCPN

40

50

ns

tcp

50

60

ns

t CPR

25

30

ns

CAS Pulse Width

tCAS

60

CAS Hold Time

tCSH

120

(Normal cycle)
CAS Precharge Time
(Page mode only)
CAS Precharge Time
(CAS-before-RAS )

RAS to CAS Delay Time

lUI

60000

75

60000

150

60

25

ns
ns

tRCO

22

75

CAS to RAS Set Up Time

t CRS

10

10

ns

Row Address Set Up Time

ns

t ASR

0

0

ns

Row Address Hold Time

tAAH

12

15

ns

Column Address Set Up Time

t ASC

0

0

ns

Column Address Hold Time

tCAH

20

25

ns

Read Command Set Up Time

tRCS

0

0

ns

IiJ

tRRH

20

20

ns

IiJ

tRCH

0

0

ns

Write Command Set Up Time

twcs

-5

-5

ns

Write Command Hold Time

Read Command Hold Time
Referenced to RAS
Read Command Hold Time
Referenced to CAS

tWCH

30

35

ns

Write Command Pulse Width

twp

30

35

ns

Write Command to RAS Lead Time

t RwL

40

45

ns

Write Command to CAS Lead Time

tCWL

40

45

ns

Data In Set Up Time

tos

0

0

ns

tOH

30

35

ns

Data I n Hold Time
Access Time from TR/OE
TR/OE to Data In Delay Time

3-44

rI

tOED

40

35

tOEA
25

30

ns
ns

1111111111111111111111111111111111111111111111111111

MB81461B-12
MB 81461B-15

FUJITSU
1111111111111111111111111111111111111111111111111111

AC CHARACTERISTICS
Parameter

!mID

MB 81461B-12

M881461B-15

Min

Min

Symbol

Output Buffer Turn Off Oelay

Unit
Max
25

tOEZ

0

TRIOE Hold Time Referenced to MEIWE

tOEH

0

0

ns

TRIOE to RAS inactive Set Up Time

tOES

0

0

ns

tozc

0

0

ns

tozo

0

0

ns

Refresh Set Up Time Referenced to
RAS (CAS-before-RASI

t FCS

25

30

ns

Refresh Hold Time Referenced to
RAS (CAS-before-RASI

tFCH

25

30

ns

tRPC

20

20

ns

tsc

40

from TRIOE

Data In to CAS Delay Time
Data In to TRIOE Delay Time

1m
1m

RAS Precharge to CAS Active
Time
Serial Clock Cycle Time
Access Time from SAS

IIiJ

t SAC

Access Time from SE

Il!J

tSEA

50000

0

Max

60

40
40

30

ns

50000

ns

60

ns

50

ns

SAS Precharge Time

tsp

10

20

ns

SAS Pulse Width

t SAS

10

20

ns

SE Precharge Time

t SEP

25

45

ns

tSE

25

45

ns

tSOH

10

10

ns

tSEZ

0

SE Pulse Width
Serial Data Out Hold Time
after SAS High
Serial Output Buffer Turn Off
Delay from SE
Serial Data In Set Up Time
Serial Data In Hold Time

m
m

25

0

30

ns

t SDS

0

0

ns

tSOH

20

25

ns

3-45

1IIIIIIIm~IIIIIIIIIIIIIII~IIIIII~lmmlm~
FUJITSU MB81461B-12
~1~llllmllmlmmll~I~~I~mllllllllml MB81461B-15

AC CHARACTERISTICS
Parameter

Transfer Command (TR) to RAS
Set Up Time

-

Min

Min

t TS

Unit
Max

Max

0

ns

tRTH

90

110

ns

tRTHW

12

15

ns

Transfer Command (TR) to CAS
Hold Time

tCTH

30

35

ns

Transfer Command (TR) to SAS
Lead Time

tTSL

5

10

ns

Write Transfer Command (TR) to
RAS Hold Time

lEI

Transfer Command (TR) to RAS
Lead Time

IB

tTRRL

25

35

ns

Transfer Command (TR) Hold Time
from RAS

II

tTRRH

25

35

ns

First SAS Edge to Transfer Command
Delay Time

tTSD

25

35

ns

ME!WE to RAS Set Up Time

tWSR

0

0

ns

ME!WE to RAS Hold Time

t RWH

12

15

ns

Mask Data (MD) to RAS Set Up Time

tMS

0

0

ns

Mask Data (MD) to RAS Hold Time

tMH

35

45

ns

Serial Output Buffer Turn Off
Delay from RAS

III

tSDZ

10

Serial Output Buffer Turn On
Delay from RAS

III

tSRO

0

0

ns

SAS to "RAS Set Up Time

II

t SRS

40

60

ns

RAS to SAS Delay Time

IIJ

tSRD

30

45

ns

tSZE

0

0

ns

tSDD

60

75

ns

Serial Data Input to SE Delay Time
Serial Data Input Delay from RAS

3-46

MB81461B·15

0

Transfer Command (TR) to RAS
Hold Time

lID

MB 81461 B·12
Symbol

IfJ

60

10

75

ns

MB81461B-12
MB81461B-15

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~~IIII
FUJITSU

IIIIIII~IIIIIIIIIIIIIIIIIII~~IIIIIII~IIIIIIII~I

AC CHARACTERISTICS
MB 81461 B-12
Parameter

ImJDit

MB 81461B-15
Unit

Symbol
Min

Max

Min

Max

Serial Data Input to RAS Delay Time

III

tszs

0

0

ns

Pseudo Transfer Command (SE) to
RAS Set up Time

III

tES R

0

0

ns

Pseudo Transfer Command (SE) to
RAS Hold Time

III

tREH

12

15

ns

t sws

20

30

ns

tswH

80

120

ns

tswlS

20

30

ns

tswlH

40

60

ns

Serial Write Enable Set up Time
Serial Write Enable Hold Time
Serial Write Disable Set Up Time
Serial Write Disable Hold Time

m
m
m
m

Asynchronous Command (TR) to
RAS Set Up Time

tyS

0

0

ns

Asynchronous Command (TR) to
RAS Hold Time

tYH

12

15

ns

Time between Transfer

mI

4

tREFT

NOTES:
An initial pause of 200lls is required after power-up
followed by any 8 RAS, 8 transfer, and 8 SAS cycle
before proper device operation is achieved. In case of
using internal refresh counter, a minimum of 8 CASbefore-RAS initialization cycles instead of 8 RAS cycle
are required.
AC characteristics assume.
V IH (min) and LIL (max) are reference levels for measuring timing of input signals. Also, transition times are
measured between V IH (min) and V IL (max).
Assumes that tRCD ::;: tRCD (max). If tRCD is greater
than the maximum recommended value shown in this
table, tRAC will be increased by the amount that t RCD
exceeds the value shown.
Assumes that tRCD ;;:: tRCD (max).
Measured with a load equivalent to 2 TTL loads and
100pF.

D

D

fJ

m

II
D

II
iii

4

ms

Operation within the t RCD (max) limit insures that
t RAC (max) can be met. t RCD (max) is specified as a
reference point only; if tRcD is greater than the specified tRCD (max) limit, then access time is controlled
exclusively by t cAC '

tRCD (min) = tRAH (min) + 2tT (tT=5ns) + tAsc (min)
REither tRRH or tFiCH must be satisfied for a read cycle.
IIiJ Measured with a load equivalent to 2 TTL loads and
50pF.
Input mode only
III Write transfer and pseuso write transfer only.
11.1 Read transfer only in the case that the previous transfer was write transfer.
HI Pseudo write transfer only.
Oil If tREFT is not satisfied, 8 transfer and 8 SAS cycles
before proper device operation is needed.
III Either tDZ C or tDzo must be satisfied.
OJ This timing specification is different from that of
MB 81461.

m

3-47

1IIImlmlmllllllllllllillmllllllllllllllllili

FUJITSU MB81461B-12
Illmllllllllllllllllm~lllllllmllllllll~lml MB81461B-15

READ CYCLE
r-------------------tAC--------------~------~

r---------------tAAS------------------j,b-___.J.

III

VIH~~_"~'~~~~c_~-~-~---~---------~~~~~
VILj~·P ,

MDIDO

VALID DATA OUT

(OUTPUT!

MDIDO

(INPUT)
tOEZ

'fRiOE
~ Don'teare

WRITE CYCLE (EARLY WRITE)
r---------------------tAC--------------------~
VIH-

RAS

CAS

f-------~-------tAAs----------~-U,.----J

V 1L -

V ,H

J:=j:====--tAsHH=====t,---.-__
~_
_.-,+---------i---.
tCAS-

V,L

ADDRESSES

~IH

COL. ADD.

::;~~f;':~"~
(MDIOQ
~,.":~ ) ~::~LlD~~~IMIMi.J'iW
",M>

VOH-_ _ _.:;II_ _ _ _ _ HIGH_Z: _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __

(OUTPUT)

VOL

~ •

tYSII~

II Don'teare
Note 1) When ME/WE = "H", all data on the MD/DO can be written into the cell.
When ME/WE = "L", the data on the MD/DO are not written (masked) except for when MD/DO = "H" at the
falling edge of RAS.

3-48

MB81461B-12
MB81461B-15

Ilmlllml~lmlllllllllllllll~II~~IIIIIIIII~
FUJITSU

111111111111~mllllllllllm~lllmllm~~~~1

DELAYED WRITE CYCLE

VIH_.--~j:U:~~~r-JL--~:;~~~:;rt---~~1,
V'L-'~~~~____-1~~~~

MD/OO
(INPUT)

__~__----...,...,~~

__~__""""__~------~~~~~-w~

___

V IH -,-....,........--....,.

V'L

-""""...:J',,..__

MD/DQ
(OUTPUT)

V'H . , . - - -....."'-----"--...,_,-----...,...,....------------.,.,.-...,....,.--.,.,..,..,,,""-'
V.L -

E:l Don't C.re
Note 1) When ME/WE = "H", all data on the MD/DO can be written into the cell.
When ME/WE = "L", the data on the MD/DO are not written (masked) except for when MD/DO
falling edge of RAS.
Note 2) When TR/OE is kept "H" through a cycle, the MD/DO are kept High-Z state.

=

"H" at the

READ-MODIFY-WRITE CYCLE
RAS

VtH-

V1L -

teAs
tASH

CAS

ADDRESSES

MelWe
MO/oa
(lNPUTI

tCAS---------1,~r----------

VIH VIL -

~:~='

',. -,

VIH _

V1L -

V 1H -

VIL -

MD/Do
(OUTPUT)

TR/OE

V 1H -,

E::::J

Don't Cere

Note 1) When ME/WE = "H", all data on the MD/DO can be written into the cell.
When ME/WE = "L", the data on the MD/DO are not written (masked) except for when MD/DO
falling edge of RAS.

= "H" at the

3-49

Imlll~lllmlm~lmlllllllllll~~~~~11111
FUJITSU M8814618-12
1IIIIIIImlm~lml~llllmlllll~~IIIII~~~1 M8814618-15

PAGE MODE READ CYCLE

V,H

-.-..J-U=~r--

V,L -

ADDRESSES

fi\EIWE

II

~:: ='~'1'-''''TIII'''tfR~'"s~1~'----;_..J~=7f'-'f'---:--...I1../1:7=f'-'-"""~-':-'-V'H 8 '"
V r l.:. ---------.JI

!I

f---tRAC
I

MD/OQ

!

VOH -

(OUTPUT! VOL

-~~~~...:I.:..I'~-.l:~:

MD/DQ

V'H_~

(INPUT)

V'L

TRioE

!

-'---....,.,-'t

V,L -

o

Don't Care

B~-------------tR-A-S~--~~--~~--~------tR-s-H-;:j--

PAGE MODE WRITE CYCLE (EARLY WRITE)
r--------------------tRc----

1r-____

:w

V,H __4:l.t~~1--

teAs

V,L -

MD/Da
(INPUT)

V'H -'"'""\~--"'-*'=.,..".'F"..."...-_ _\r_==-i.,......-....,; ~.I.,.:=cdr_.".,.-....,.,,....,...,.,...,...

v, L

......~=~\.....--"""'.,}..:;:.:;=_1'-"""'~ ilJ1~~_fi~.;.:.:.....;,...;.,""'".....

~"""i1}_....,.,.

MO/OO
VOH (OUTPUT) VOL _

tVSrJ~tVH

HIGH-Z

----If

'r)- - - - - - - - - - - - - - - - - -

II

Don't Care

Note 1) When ME/WE = "H", all data on the MD/DQ can be written into the cell.
When MEliNE = "L", the data on the MD/DQ are not written (masked) except for when MD/DQ = "H" at the
falling edge of RAS.

3-50

11~1111111~lllllm~IIIIIIIIIIIIIII~lllmllllll
MB81461B-12 FUJITSU
MB81461B-15 1IIIIIIIImlllllllllllllll~~mmlll~1111111111

PAGE MODE DELAYED WRITE CYCLE

V'H_-----rr==~~tRAS·~tRC~===:;~iR~
1r------,--------\<,----tRSH
~L

V'L CAS

teAs

-,....+"';--,1

VU·i

--"""\h;;i;vV1'/ii--\r----"--v.'1rr,-...:.--o--v.='r-'--...;I----

ADDRESSES V,H

V'L-.J~~~~~~---r-~~~~~_~~~~r_~-~----

V1H-·..,..,I--v---.. 1
V'L-~~~~~-~~~_f-------~~~--~~--_i~~---------

...,.,....-"':""Ic

MOloa

V'H -,•

(INPUT)

V1L

-'-'~

V'H

-.-t-..!.!..,r-,j.-------.r----+--.....,.r---( r""'T--\.....
-----~
\._ _ _ _ __

__--'f

V'L -

o

Don't Care

~ Valid Data In

Note 1) When ME/WE = "H", all data on the MD/DO can be written into the cell.
When ME/WE = "L", the data on the MD/DO are not written (masked) except for when MD/DO = "H" at the
fall ing edge of RAS.
Note 2) When TR/OE is kept "H" through a cycle, the MD/DO are kept High·Z state.
PAGE MODE READ·MODIFY·WRITE CYCLE
AAS

CAS

ME/WE

V,H V 1L -

V'H_

V,L -

v,H-·""",I--IrO..:.:----i1
V, L --..J\-_N'

MDIDO

V,H-·-.,..........'

(INPUT)

V'L-......,'~_--'f

MOIOO

VOH -

{OUTPUT) VOL

_----i+--:.;.;.:'-{Xxxt-

o

Don't Care

m

V,lid data In

m

Valid dlta Out

Note 1) When ME/WE = "H", all data on the MD/DO can be written into the cell.
When ME/WE = "L", the data on the MD/DO are not written (masked) except for when MD/DO
fall ing edge of RAS.

= "H" at the

3-51

~mllll~~mmllllllllllllml~~IIIIIIII~~
FUJITSU

MB81461B-12

111~~IIIIIII~~lm~~IM~lm~lml~mm MB 81461 B-15

RAS·ONLY REFRESH CYCLE (MEJWE"=Don't Carel

t----------tRc----------I
V1H _.------......,ir-----tRAS-----IJ.-----...J
VIL -

MOIOO
(OUTPUT)

TRIOE

VOH- _ _ _ _ _ _ _r - t - - - - - H I G H . Z - - - - - - - - - - -

~~:':(~~;;:~~•.,::;;.~

MOIOO
(INPUT)

Ell Don't Care

CAS·BEFORE·RAS REFRESH CYCLE (ADDRESS, ME/WE, TR/OE=Don't Carel

VOH _---...L
(OUTPUT) VOL _ _ _ _J---------,.---~IIG~I.Z---------

MDIDO

MOIDO
(INPUT)

•

3-52

Don'tCare

MB81461B-12
MB81461B-15

11~llllllllllllllllllllllllllllllllllllllmlllll~
FUJITSU
11~~IIIIIIIIIIIIIIIIIIIII~IIIIIIIII~llmlmll

HIDDEN REFRESH CYCLE

1-------tRC--;----~_I__---

RAS

.---_1

V'H-

f - - - t RAS------i·.1,----..J 1---tRAS

V'L -

VIS

V'H V'L -

MDIDO VOHIOUTPUT) VOL - - - -

MDIDO

IINPUT)

V'H

V'L

VALID DATA OUT

~~""""

~6;t~"'---------HIGH-Z------------

o

Don't ears

3-53

I11I1Hlm!l11l1
F'UJITSU

MBB1461B-12

lII!n~~II.~~~OO MB81461B-15

READ TRANSFER CYCLE- (MD/DQ

=Don't Carel

RAS"

CAS

ADDRESSES

V 1H
V1L

~IH

IL

fi'l/O'E

M"E"IWE

SAS

~

SO

VIH

VIH
VIL'

V 1H
V1L -

V 1H
V1L -

VIH -

(INPUT)

VIL -

SO

VOH -

(OUTPUT)

VOL Previous row

-\ New row

iii
*: In the case that the previous transfer is read transfer.
**: If SE is low, the valid data will appear within tsAc or !sEA"': These parameters are different from that of MB 81461.

3-54

Don'tCare

MB81461B-12
MB81461B-15

READ TRANSFER CYCLE" (MD/DQ

1111111~111111111111111~lllmllllllllll~~lmll
FUJITSU
1111111111111111111111111111111111111111111111m~1

= Don't Care)

~----------------------tAC--------------------~~

~--------------'tAAS--------------~

RAS

V 1H -

-----il

Ir---------~

V 1L-

1---------------tCSH---------------fto--l
,-_~-------tASH--------__I

CAS

V 1H -

-+--I+----b

tCAs--------+Jo~

r'T"--------

V 1L-

ADDRESSES V 1W
VILtTRAH···
TR/DE

V 1HV 1L-

MW/WE

V1HV 1L -

SAS

V 1H V 1L-

SE

V 1H V 1L-

SD
IINPUT)

V 1H -

SD
(OUTPUT)

V OH -

V 1L -

HIGH-Z---------++-----+-----j--_.--tSAO------I

VOL

------HIGH-Z----r~liNN;VV:;ALLI~D~D~A;Tr:;A~~;;L;'D;;;:~v-;,~~;:;;:;:;;1r-

o

Don't ears

ISS]

Inhibit of Rising Edge

'; In the case that the previous transfer is write transfer.
"; If SE is low and the previous cycle is serial write cycle, this should be valid data input.
" ' ; These parameters are different from that of MB 81461.

3-55

mm~~~~~IIIIIIIOOIIIIII~~IIIIII~~lill
FUJITSU MB81461B-12
lIIilllllilllllllllllllllllililllllllOOiilll MB81461B-15

WRITE TRANSFER CYCLE* (MD/DQ = Don't Care)

RAS

CAS

V'H
V'L

ADDRESSES V'H
V'L

TRIOE

V'H
V'L

MEIWE

V'H
V'L

SAS

SE

V'H
V'L

SO
(INPUT)

V'H
V'L

SO
(OUTPUT)

VOHVOL -

-----------HIGH-Z--------------•

m

*; In the case that the previous transfer is write transfer.
**; If SE is high these data are not written into the SAM_

Don'teare
Inhibit of Rising Edge

1111111111111111111111111111111111111111111111111111

MB81461B-12
MB81461B-15

PSEUDO WRITE TRANSFER CYCLE (MOl DO

FUJITSU
1111111111111111111111111111111111111111111111111111

= Don't Care)

tRC

RAS

tRAS

V,H _
V 1L -

CAS

tRP

tCSH

teRs

V,HV,L -

ADDRESSES VV1H-

-=vt™tJ

IL-·-J~~~\-J'~~~~-{'~

~::

____

~

_ _ _ _ _ _ _ _ _ _ ____

'_R_T_HW
_ _ _ _ _ _ _ _ _ _..;.-_ _ _ _ _ _ _ __

::~ -4t1-----------------------.;.-.------------'ES~EH

SAS

V,HV,L -

SO
(INPUT)

SO
IOUTPUT)

VOHVOL -

VALID"
____~~-~:l1:....._4r-------H
IGH-Z ------DATA

o

m

*:
**:

Don't Care
Inhibit of Rising Edge

If SE is high, these data are not written into SAM.
If SE is high, SO (SDO to SD3) are in High-Z state after t SEZ .
If SE becomes low, the valid data will appear meeting t SAC and tSEA.

3-57

1~~mmlmllmlmllmlml~~lmlml~m
FUJITSU MB81461B-12
Ilmlllllllmll~IIIIIII~II~I~llllllmlllllm MB 81461 B-15

SERIAL READ CYCLE

SAS

SO
(INPUT)

In the case of SE="L" while the operation;

SO
(INPUT)

VIH
V 1L

----------HIGH-Z-----'---------~ Invalid Data

3-58

•

Don't Care

1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIImi

MB81461B-12
MB 814 61 B-15

FUJITSU
I11I1II111111111111111111111111111111111111111111111

SERIAL WRITE CYCLE

RAS

VIH-

VIl.-

TR/OE

VIH-________________

SE

VIH-

VIL -

L------4't~
RAS

-J~~~

_________________________
tSEP

tSE

VIL -

tsws

SAS

tSWH

VIHVIL -

SO
(OUTPUT)

VOH------------------ HIGH-Z----------------------VOL-

SO

VIH-

IINPUT)

VIH-

In the case of SE~"L" while the operation;

SAS

SO
(OUTPl,lT)

SO
\INPUT)

VIHVIL -

VOHV OL -

V1HV 1L -

o

Don"tears

3-59

11111mllllllllllllllllllllllllllll~11111111111111
FUJITSU
1111111111111111111111111111111111111111111111111111

MB81461B-12
MB81461B-15

Fig. 5 - CURRENT WAVEFORM (Vee = 5.5V, TA = 25°C)
RAS/CAS

811
CAs

I_~

CYCLE

If

t"\

,

TRICE

RAS-ONl Y REFRESH CYCLE

1

!- I-

t- "\

V

!- r- - '

PAGE MODe CYCLE

t-t-t-

\ t-

1,.-

\ Il- I-

II

1'- I- r-

CAs·BEFORE·RAS REFRESH CYCLE

r- t-

--r -7F--

(\ r1 l- f\- f-' I- - II

rt- l-

\ r-

\-- l-

I

\f-I

I

I

I

20 0

~

16o

.

0

0

0

01-

If

1/\ II

- C-

I
I

n

/'I

-

III

I
II

11

11\

IJ \

,'"

II

\1'" I '

fJ

J

I

L11
r\
J
II J J1\ V\ 11\
V IV \ ~

Ll

"

50 ns/divlsion

.J
\1/

Fig. 5 - CURRENT WAVEFORM (Vee = 5.5V, TA = 25°C) (cont'd)
SERIAL ACCESS CYCLE

TRANSFER MOOE CYCLE

81-Isl- f-

,

1,-

f-[\

If

f-f-

1"-1- l-

h

l- I-

,I-

SAs

1"- i-f-

t-V

r-t-t-

M'/W

'fRIO

t-

r t-l\

't1

I

1'-

I I
'00

if 1'- Ir I.... Ir 1'- Ir l...I r

fI

160

f\

rr0

ir-- -IV

If
--

\

I
ItL
I\,

1\
1\ \

or-'
SOns/dIVISion

3 ..60

If

,

n

r\
\

1/\

1111111111111111111111111111111111111111111111111111

MB81461B-12
MB81461B-15

FUJITSU
1111111111111111111111111111111111111111111111111111

TYPICAL CHARACTERISTICS CURVES
Fig. 7 - NORMALIZED ACCESS TIME
vs AMBIENT TEMPERATURE

Fig. 6 - NORMALIZED ACCESS TIME
vs SUPPL Y VOLTAGE
w

w

::<
f=
If)

TA = 15°C
tRCD = 20 ns-

1.2

w

U

~

"

1. 1

o

~

1.0

:i

«

::<

0.9

II:

o
Z

U 0.8

'"

fll

If)

u

""

~

1. 1

~ 1'-0.

~
:i

1.0

:;:

0.9

«

~
z

U

«
!!-

I-

z

100

4.5
5.0
5.5
Vee. SUPPLY VOLTAGE (V)

-20

6.0

::>

..s

<.:l

«

II:

w

0

U
.!:?

20

V

,/

80

100

d5°C

~

40

-

o
U

20

.!:?

0

- f.---

Fig. 10 - OPERATING CURRENT
vs AMBIENT TEMPERATURE

Fig.11-STANDBY SURRENT
vsSUPPLY VOLTAGE

80

<.:l

70

«
II:

II:

3

4

5

4

6

<
..s

T A =45°C
18

I-

z

f=

60

5.0
4.5
5.5
VCC. SUPPLY VOLTAGE (V)

II:
II:

w
0

60

w

v~c=5L

::>
u

40

I/tRC. CYCLE RATE (MHz)

90 r-tRC = 230 ns

z

80

~

..

./

I-

zw

::>

u

V

1

<
..s

II:
II:

./

40

a..

TA =

zw

80
60

20

I- 100 I--tRC = 230 ns

c- Vcc =5.5V

U

z

0

Fig. 9 - OPERATING CURRENT
vs SUPPLY VOLTAGE

<

TAI=25°~

f=

.....

T A • AMBIENT TEMPERATURE (OC)

w

II:
II:

.....V

,.V

~

0.8

Fig. 8 - OPERATING CURRENT
vs CYCLE RATE

<
..s

= 5.dv
_tRCD =20ns

1.2

o

«
54

VC~

::<
f=

w

-

II:
II:

::>
u
t"-

>-

50

U
.!:?

14

III

0

60

a..

---

16

z
~

'"uN

-~

~

12
10

.!:?
-20
0
20
40
60
80 100
T A • AMBIENT TEMPERATURE (OC)

4

4.5
5.5
5.0
VCC. SUPPLY VOLTAGE (V)

6

3-61

1~~~~lm~~II~llmllmllml~~III~~1
FUJITSU MB81461B-12
IIlIlImll l l l l l l l l l l l l l l l l ml l l MB81461B-15

Fig. 12 - STANDBY CURRENT
vs AMBIENT TEMPERATURE

<
oS
I-

zw

a:
a:

20

vdc =sJv

....
18

>-

w

.............

14 f - -

~

~

w

a:

12

LL
W

..;
0
..!?

Fig. 14 - REFRESH CURRENT 1
vs SUPPLY VOLTAGE

Fig. 15 - PAGE MODE CURRENT
vs CYCLE RATE

I-

40

U

60

..--

-

40

~

30

o

:;;

w

20

.t
o
..!?
4.S
5.0
5.5
Vce, SUPPLY VOLTAGE (V)

:::>
u
w

0
0

- ----

:;;
w

30

.t
..!?

100 r-Vee =5.SV

a:
a:

80

I

60

w

a:

LL
W

40

a:

.;,

10

u

..!?
4

4.5

5.0

5.5

Vee, SUPPLY VOLTAGE (V)

/'

(I)

0

3-62

TAl =

N

:::>
u

«

Il.

25,b

oS

w

I----

6

12

Fig. 17 - REFRESH CURRENT 2
vs CYCLE RATE

IZ

20 1--,.



l-

<
oS

TA 1= 2s'6
100 r-Vcc = 5.5V

IZ

0

«

.s

r-.......

16

IX>

Z

<

.........

:::>

u

Fig. 13 - REFRESH CURRENT 1
vs CYCLE RATE

20

""

/"

V

!-"

2
4
5
I/tRC, CYCLE RATE (MHzl

6

!~!II~~I~~I~.I
FUJITSU

MB81461B-12
MB81461B-15

Fig. 19 - TRANSFER MODE CURRENT
vs CYCLE RATE

Fig. 18 - REFRESH CURRENT 2
vs SUPPLY VOLTAGE

«

~5'C

TA =
100 r-tRe = 230 ns

.s
""0:w
N

Z

'-'

-

60

J:

CI)

w
u.
w

40

0:

'-'

~ f--

80

o
o

:;

60

0:

w
u.

<

g:

20

4

4.5
5.0
5.5
Vee. SUPPLY VOLTAGE (V)

a

-

80

~

o

~

20

2

60

0:

t
<

--

:;

<<

40

g; ""

30

:i~
",,0:

(I) ~ 20
:;'-'

<
g:

40

0:

~

20 4

<

Z

4.5
5.0
5.5
Vee. SUPPLY VOLTAGE (V)

TA=~5'C

--

50 t-- tse = 40 ns

:;

~~
>--

40

~

30

;::0:

cO

!/'

/'

V
./

10

()

W

f5

V ..

./

cO

>

<
0:

6

.2

20

~

5
10
15
20
25
IItse. CYCLE RATE (MHz)

6

Fig. 22 - RAM STANDBY/SAM ACTIVE CURRENT
vs SUPPLY VOL TAG£

(I)

5

vJe =
50 I-- T A = 25"C

~E

CI)

t<

4

5.~V

>

60

~

3

Fig. 21 - RAM STANDBY/SAM ACTIVE CURRENT
vs CYCLE RATE
W

W

/

lItRe. CYCLE RATE (MHz)

TA =1 25'C
100 -tRe = 230ns

V

./

",'"

6

Fig. 20 - TRANSFER MODE CURRENT
vs SUPPLY VOLTAGE

0:

:;'-'

/

40

Z

,;,
()
.2

"'''''iij

= 5.5V

W

(I)

0:

.s
iij
""
0:

T~=25,h
100 -Vee

::l

80

::l

<

""
iij
0:
0:

0:

I!I.I~IM~I.

Fig. 23 - RAM STANDBY/SAM ACTIVE CURRENT
vs AMBIENT TEMPERATURE

T J

W

>

---

tse = 40 ns
V c e=5.5V-

i=

~

30

~

50

~

< 40

~ E

>--

g;ZW~

30

<0:

""0:

(I)::l

:;'-'

20

<

0:

10

cO

()

10

()

.2

.2
4

4.5
5
5.5
Vee. SUPPLY VOLTAGE (V)

6

o

20
0
100
40
60
-2
~
T A • AMBIENT TEMPERATURE ("C)

3-!53

IIIIIIIIIIIIIIIIIIIIII~IIIII~IIIIIIIIIIIIIIIIIIII
FUJITSU MB81461B-12
111111111111111111111~lllllllllllmllllllllllllll MB 81461B-15

Fig. 24 - ADDRESS AND DATA (DO AND SO)
INPUT VOLTAGE vs SUPPL Y VOLTAGE

Fig. 25 ~ ADDRESS AND DATA (DO AND SO)
INPUT VOLTAGE vs SUPPLY VOLTAGE

3.0

3.0

TA

•

i5°C

....

~ ~

1-=

V'H IMin.1 Vee = 5.5V

-

1--

V'L IMax.1 vee' 4.5V

-

o

o

4

4.5
5.0
5.5
Vec. SUPPLY VOLTAGE IVI

6

Fig. 26 - RAS, CAS, ME/WE, TR/OE, SE, SAS
INPUT VOLTAGE vs SUPPLY VOLTAGE
3.0

-20
0
20
40
60
80 100
TA • AMBIENT TEMPERATURE lOCI

Fig. 27 - RAS, CAS, ME/WE, TR/OE, SE, SAS INPUT
VOLTAGE vs AMBIENT TEMPERATURE
3.0

T A =25dC

-

I - - V'H IMin.1 Vee' 5.5V -

V'H IMin.1

I
I

V'L IMax.1

~ V'L IMax.1 Vec·4.5V

I I I

:i:

:>

o

4

o
4.5
5.0
5.5
v ec , SUPPL Y VOLTAGE IVI

6

-20
0
20
40
60
80 100
T A • AMBIENT TEMPERATURE lOCI

Fig. 28 - ACCESS TIME (RAM)
vs LOAD CAPACITANCE

Fig. 29 - ACCESS TIME (SAM)
vs LOAD CAPACITANCE
25

V~e' 4.15V
20 f--T A • 2.5°C
.5
w
:; 15

c
J

i=

Vl
Vl

w
u
u

«
U
.:
a:

:;

/

10

./

5
0

'"

,/

/

100 200 300 400 500
CL. LOAD CAPACITANCE IpF).

3-64

-

w
:;

i=
Vl
Vl

w
u
u

«

U
.:

$'

~

20
/

15
10

./

5
0

./

/

V

V

V'

50
100 150 200 250 300
CL • LOAD CAPACITANCE IpFI

MB81461B-12
MB81461B-15

Fig. 31 - SO OUTPUT CURRENT
vs SO OUTPUT VOLTAGE

Fig. 30 - DO OUTPUT CURRENT
VI DO OUTPUT VOLTAGE

<"

<"
i

.;
~ 2001--+--+---I---/---j

w
a:
a:

13

1llllllllllllllmllllllllllllll~llllllllllmlllll
FUJITSU
IIIIIII~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~IIIIII

~
w

~ol--+--+---I---/---j

a:
a:

:J

1501----1!----+

u

I-

::>

~ 100~-~~~~~~~-~

I:J

0..

::>

I:J

15

en

o

o
o

.J

.J

o

o

1

2

4

5

VOL. DO OUTPUT VOLTAGE (V)

Fig. 33 - SO OUTPUT CURRENT
vs SO OUTPUT VOLTAGE

Fig. 32 - DO OUTPUT CURRENT
vs DO OUTPUT VOLTAGE

<"
.;

TA =1 25,C

~ -100

w
a:
a:

13
I-

::>

~ -50I--+-~'

o

C!

o

-251---t--+----'ld-'..--+--j

i

V OH • DO OUTPUT VOLTAGE (V)

::>0

-t>

,

...

"
V

o

"",V CC =5.5V

~

"

y

=4.5i'"

~

1
2
3
4
5
VOH. SD OUTPUT VOLTAGE (V)

Fig. 34 - SUBSTRATE VOLTAGE
DURING POWER UP

~;;

en«
m~

en -25

o

°0~-+1-~~~3~~4~~5

0.. W
::>t:>

~ -50
:J
o
o
1:

o

0..-

-75

I:J

51
0

W

~;; -1
enw
lIlt:>
::> « -2
en I-

[II I I I I

..,

I\.

"\ ~TA = 25'C

1--

'\.,

• ..J

"0
~> -3

"'

>

50

~/Division

3-65

11111111111111111111~111~llllllllm~11111111111
FUJITSU MB81461B-12
111111111111111111111111~llmlllllllllllllllllllll MB81461B-15

PACKAGE DIMENSIONS
PLASTIC DIP (Suffix: -PI

PLASTIC ZIP (Suffix: -PSZ)
24-LEAD PLASTIC DUAL-IN·LlNE PACKAGE
leASE No.: DIP-24P-M041
<

l,5"MAX

_1
~40~"'m
.010•. 002

(0.25<0.051

-T.207!S'25)MAX

ID

1

'1S!3.0IMIN

O,menS'On$ln
Inches Im,lhmote,,)

24·LEAD PLASTIC ZIGZAG-IN-LINE PACKAGE
tCASE No.: ZIP·24p·M02)

[

---

r --r
.',2'.008

--- - 1209~g~gI3071:g~~I----

(2.85'0201

.387[.013

1981331
.DIOt.D02
(o.i5~·O~Ost

.050(1.271

. TYP

.020-,004
10:50+0.10)"

.'0~(2:5~IL J-'
TYe

t

.,,8(300)

M~:;>.:1

5-10

VIH

or

VIL

Invalid Data

111111111111111111111111111111111111111111111111111111

MB8S230-1 0
MB8S230-12

FUJITSU
111111111111111111111111111111111111111111111111111111

WRITE CYCLE (Early Write)

tRC
tRAS

liAS

VIHVILtCSH

CAS

VIHVIL-

ADDRESSES

VIH_

DO
(INPUT)

DO

(OUTPUT)

VIL- ........................_ _......., "l"-...:;;.;.~~-"'r ""-'~~~~~::...:..::...:..::...:..:::..:;..;:::..:;..;~

~~~= -----------HIGH-Z~------------

5-11

I I I I I I I I I I I I I I I I I I I I I~I I I I I I
FUJITSU MB85230-10
I I I I I I I I I I I I I I I ~I I I I ~I I~I I I MB85230-12

FAST PAGE MODE READ CYCLE

L - - - -_ _ _ _ _ _

tRAS

VIHVIL-

VIHVIL-

ADDRESSES

DQ

OUTPUT

VOH- VOL-

HIGiH-2:---~t;

D
•

ValidData

~f'~~

5-12

VIHorVIL

Invalid Data

111111111111111111111111111111111111111111111111111111

MB85230-10
MB85230-12

FUJITSU
111111111111111111111111111111111111111111111111111111

FAST PAGE MODE WRITE CYCLE

VIHVIL-

VIHVIL-

ADDRESSES VIHVIL-

VIHVIL-

DQ
(INPUT)

VIHVIL_

DQ
VOH(OUTPUT) VOL-

- - - - - - - -_ _ _ _ HIGH-Z - - - - - - - - - - - - - -

f::,>:::>J

VIH or VIL

5-13

1111111~111~llllllllmllilllllllllllllllllmlllll
FUJITSU MB85230-10
I I I I I I I I I ~I I I I!I I I I I I I I I I I I I MB85230-12

RAS-ONLY REFRESH CYCLE
NOTE: WE, DQ(lnput)=Don't care, A9 = VIH or VIL
~--------------tRC--------------~

V1H _

--------..L \ 4 - - - tRAS -----I..J.r:-----------,,L
~---------~~-----tRP----~

VIL -

Ao - As

V 1H V1L -

--------':"'P-------------------r-----------------...;;1("
tOH

DO
VOH
(OUTPUT) VOL

-

_ _ _ _ _ _ _ _ _1-*_ _ _ _ _ _ _ _
_ _ _ _ _ _....,

HIGH-Z--------------

I:::>;»

VIH

or

VIL

CAS-BEFORE-RAS REFRESH CYCLE
NOTE: ADDRESS, WE, DIN = Don't Care

DO
VOH (OUTPUT) VOL -

5-14

_ _ _ _ _ _ _~......- - - - - - - - - - - - - - - - - - _ _ __

HIGH-Z-----------------

IIIIIIIIIIIIIIIIIIIIIIIIIII~III~IIIIIIIIIIIIIIIIIIII
MB85230-10 FUJITSU
MB85230-12 I I I I I I I I I I I I I I I I I I I I I I~ I I~I

HIDDEN REFRESH CYCLE

~---------tRC--------~~-------

11J\S"

VIHVIL-

CAS

VIHVIL-

Ao - A9

VIHVIL-

M

VIHVIL-

----~~~~k ~~----~-----tcAS------------~

DQ
VOH(OUTPUT) VOL - - HIGH-Z

I_

tCHR

-----Irr---

VALID DATA

f:.~;.):!::;;;~J

Invalid Data

5-15

I I I I I I I I I I I I I I I I I I I I I I I ~I I I
FUJITSU
1IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIillllllllllllllllllili

MB85230-10
MB85230-12

DESCRIPTION
Block Analysis:
As shown In Fig. 1 and Fig. 2, the MB85230 Is composed of eight MB81C1000, and the memory selection of the each
MB81C1000 consists of a 1024-by-1 024 cell matrix.
Operational modes of the device are shown In the FUNCTIONAL TRUTH TABLE below.

Address Inputs:
A total of twenty binary Input address bits are required to decde any 8-blt of the 8,388,608 storage cells within the MB85230.
Ten row address bits are established on the address Input pins (Ao to A9) and latched with the Row Address Strobe, RAS.
The ten column address bits are established on the address Input pins (Ao to A9) and latched with the Column Address
Strobe, CAS. All row and column addresses must be stable on or before the failing edge of RAS and CAS, respectively.
Since the flow through type address latches are used, address Information at address pins are automatically latched as column address after tRAH (mln)+ tT. If tRAD ;;::: tRAD (max), access time Is tCAC or tAA whichever occurs later.

Write Enable:
Read or Write mode Is selected with the WE Inputs. A high on WE selects read cycle and low selects write mode.

Data Input/Output:

1. Data Input;
In write cycle, the 8-bit data Is written Into the MB85230 during write cycle through each DQ pins. Each Input data Is
strobed and latched by failing edge of CAS, and WE must be brought to VIL before falling edge of CAS, data Input
strobed by CAS, and setup and hold times are referenced to CAS.

2.

Data Output;
The output buffers on each chip are three state TTL compatible with a fan out of 2 TTL loads. Output data has the
same porality as Input data. The outputs are In high Impedance state until CAS Is brought low. In a read cycle, the
output becomes valid within tCAC or tAA whichever occurs later after failing edge of CAS.
The data output remans valid until CAS returns to high.

Read Cycle:
The read cycle Is executed by keeping both RAS and CAS=VIL and keeping WE=VIH throughout the cycle. The row and column addresses are latched with RAS and CAS, respectively. The output data Is remain valid with CAS=VIL, I.e., If CAS goes
VIH. the data becomes Invalid with tOH. The access time Is determined by RAS (tRAC), CAS (tCAC) , or Column address Input
(tAA). If tRCD(RAS to CAS delay time) Is greater than the specification, the access time Is tCAC. If tRAD Is greater than
the specification, the access time Is tAA.

Write Cycle:
The write cycle is executed Is executed by the same manner as read cycle except for the state of WE. The 8-blt data on
DQ pins are latched with the falling edge of CAS and written Into memory. In addition, during write cycle, tRWL, tCWL, and
tRAL must be satisfied the specifications.

Fast Page Mode Read Cycle:
The fast page mode read cycle Is executed after normal cycle with holding RAS=VIL, applying column address and CAS, and
keeping WE=VIH. Since the row address during fast page mode cycle Is latched by normal cycle, the cycle time is reduced.
During this mode, the access time Is tCAC, tAA, or tCPA, whichever occur later. Any of the 1024 bits belonging to each internal row address can be accessed.

Fast Page Mode Write Cycle:
The fast page mode write cycle Is executed by the same manner as fast page mode read cycle except for the state of WE.
The data on each DQ Is latched with the failing edge of CAS and written Into the memory. During this write cycle, tcwL
must be satisfied. Any of 1024 bits belonging to each Internal row address can be accessed.

5-16

111111111111111111111111111111111111111111111111111111

MB8S230-10
MB8S230-12

DESCRIPTION

FUJITSU
111111111111111111111111111111111111111111111111111111

(Continued)

Refresh:
The refresh of DRAM Is executed by normal read and write cycle, i. e., the cells on each one row line, Ao through As except
for Ag, are refreshed by one of two cycles. Each 512 row address must be refreshed every B. 2ms period. During the refresh cycle, the cell data connected to the selected row are sent to sense amplifier and re-write to the cell. The MB85230
also has three types of refresh modes, RAS-only, CAS-before-RAS, and Hidden refresh.

1,

RAS-only Refresh;
The RAS-only refresh is executed by keeping RAS=VIL and keeping CAS=VIH through the cycle. The row address to be
refreshed Is latched with the falling edge of RAS. During this refresh, the DQ pins are kept high impedance state.

2.

CAS-before-RAS Refresh;
The CAS-before-RAS refresh Is executed by bringing CAS=VIL before RAS. By this combination, the MB85230 executes
CAS-before-RAS refresh. The row address Input is not necessary because it is generated internally.

3.

Hidden Refresh;
The hidden refresh Is execute dby keeping CAS=VIL to next cycle during read mode, i.e., the output data at previous
cycle Is kept during next refresh cycle. Since the CAS Is kept VIL continuously from previous cycle, followed refresh
cycle should be CAS-before-RAS refresh.

FUNCTIONAL TRUTH TABLE
Operation
Mode

Clock Input
RAS

CAS

Address Input
WE

Row

Column

Note

Data
1/0

Standby

VIH

VIH

X

Hlgh-Z

Cells are not refreshed.

Read
(Normal)

VIL

VIL

VIH

Valid

Valid

Output
Valid

tRCS ;?; tRCS (min)

Read
(Fast Page)

VIL

VIL

VIH

Valid

Valid

Output
Valid

tRCS ;?; tRcs (min)
Cells are not refreshed.

Write
(Normal)

VIL

VIL

VIL

Valid

Valid

Input
Valid

twcs ;?; twcs (min)

Write
(Fast Page)

VIL

VIL

VIL

Valid

Valid

Input
Valid

twcs ;?; twcs (min)
Cells are nat refreshed.

RAS-only
Refresh

VIL

VIH

X

Valid

X

High-Z

CAS-beforeRAS Refresh

VIL

VIL

X

X

X

Hlgh-Z

tCRS

Hidden
Refresh

VIL

VIL

VIH

X

X

Output
Valid

Previous data Is kept.

Note: X:

*

X

X

;?;

tCRS

(min)

Don't Care
RAS puts VIH at once.

5-17

1 1 1 1 1 1 1 1 1 ~1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FUJITSU MB85230-10
Il l l l l l l l l l l l l l l l lil l l l l l l ~1 MB85230-12

PACKAGE DIMENSIONS
30·LEAD PLASTIC SINGLE IN·LlNE TYPE MODULE
(CASE No.: MSP·30P·P05)

1

".200IS.081

MAX

II •. 01 O~:gg~
IO.2S~gb~1
2.900(73.66)REF

REF
Dimension in
inches (millimeters)
"1989 FUJITSU LIMITED M300145-2C

5-18

11111111111111111111111111111111111111111111111

MB85230-10
MB85230-12

FUJITSU
11111111111111111111111111111111111111111111111

PACKAGE DIMENSIONS (Continued)
3D-LEAD PLASTIC MODULE (SOCKET TYPE)
(Case No. : MSS-30P-P04)

3500' 010
133

I

-I

(8890' 025)
3234' 005

005

(3~3)

(82 14

200(508)

0 13)

MAX

125- 005 DIA

R 060( 1 52) REF

u[JlJrTlrllJ
oUUU

-.

(3.18 + 0.13) DIA \

(lg~~~g~~) 11
250 + 005

j

(6 35 '.0 13)
080 T 005
(2.

~

I

008
020)

0

I

111
l-

O:3lOi-3)~-t·

300
(7.62

/u

C

_

~~'

- (20800'
1020 M
32 • 0 51 ) ~

i

0

I

J- (2.54'
----0 10)

1-

H

I

100' 004

100(254) MIN

~

2900+ .005

i W9(276) TYP

(7366' 013)

r Details of "A" part

: D .OCJ

-·tc

L _ __
1

(C) 1989 FUJITSU LIMITED M30013S-3C

_.

8(Oc 20 ) TYP

:

______ J

DimenSions
(millimeters)

In

inches

5-19

CMOS DRAMs

5-20

Dynamic RAM Data Book

11111111111111111111111111111111111111111111111111111111I111111

MB85231-10
MB85231-12

FUJITSU
IIIIIIIIIIIIIIIIIIIIIIIIII!IIIII!IIIIII!IIIIIIIIII!IIIIII!IIIII

July 1988
Edition 1,0

1,048,576

x

8 BIT DYNAMIC RANDOM ACCESS
MEMORY MODULE

The Fujitsu MB85231 Is a fully decoded, dynamic CMOS random access memory
module with eight MB81C1001, In 26-pln SOJ packages, and eight ,22iJ.F decoupling
capacitor under the each memory, mounted on a 30-pln SIP or a 30-pad SIMM
module, Organized as 1,048,576 x 8-bit words, the MB85231 PCB module Is
optimized for those applications requiring high density and large memory storage
capability, The operation and electrical characteristics of the MB85231 are the same
as the MB81 C1 001 devices which feature a Nibble mode operation,
•

1,048,576 x 8 DRAM, 30-pln SIP
and SIMM

•

RAS access time (tRAC):
100 ns max, (MB85231-10)
120 ns max, (MB85231-12)

•

Cycle time (tRC):
180 ns min,(MB85231-10)
210 ns max, (MB85231-12)

•

Column access time (tCAC):
30 ns max, (MB85231-10)
35 ns max, (MB85231-12)

•

Nibble mode cycle time (tNC):
50 ns max,(MB85231-10)
55 ns max, (MB85231-12)

•

•

Low power:
Active = 2640 mWmax ,
(MB85231-10)
2200mW max,
(MB85231-12)
Standby = 44mWmax,
(CMOS level)

•

Refresh:
- 8,2 ms / 512 refresh cycle
- "RAS-only" , "CAS-before-RAS"
and
"Hidden" refresh capability

•

Nibble Mode
capability

Read

•

Leaded and
available.

Leadless

•

JEDEC standard (30 pin SIP) pin
assignment

Dual +5V supply, ± 10% tolerance

and

Write

PIN ASSIGNMENT
type

ABSOLUTE MAXIMUM RATINGS (see Note
Rating
Voltage on any pin relative to Vss

Symbol

Value

Unit

VIN, VOUT

-1 to +7

V

Voltage on Vcc supply relative toVss

Vec

-1 to +7

V

Storage temperature

TSTG

-55 to 125

°C

Power dissipation

PD

8,0

W

Short circuit output current

-

50

mA

NOTE:

MSS-30P-P04

Permanent device damage may occur If the above Absolute
Maximum Ratings are exceeded, Functional operation should be
restricted to the conditions as detailed In the operational sections of
this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability,

are

--J

YQ;
CAS
DOO
AO
A1
D01
A2
A3
VSS
D02
A4
AS
D03
A6
A7
D04
A8
A9
NC
.Q,Q5
WE
VSS
D06
NC
D07

~

NC
NC
VCC

1
2
3
4
5
6
7
6
9
10
11
12
13
14
15
16
17
16
19
20
21
22
23
24
25
26
27
26
29
30

§I
§I
§I

0

§I

81

§I
§I
§I

0
0
0

0

This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
fields. However, It Is advised that normal precautions
be taken to avoid application of any voltage higher
than maximum rated voltages to this high impedance
circuit.

©

Copyright

1989 FUJITSU LIMITED

5-21

~IIIIIIIIIIIIIIIIIIIIIIIIIIOOIIIIIIIII~IIII
FUJITSU
111II1111111111111111111111111111111111111111111111

MB85231-10
MB85231-12

Fig. 1 - BLOCK DIAGRAM

o

CHIP
1

CHIP

CHIP

CHIP

CHIP

CHIP

CHIP

2

3

4

5

6

7

DOO

D01

D02

D03

D04

D05

D06

D07

CHIP

Fig. 2 - BLOCK DIAGRAM FOR EACH CHIP

5-22

11111111111111111111111111111111111111111111111111111111111111111

MB85231-10
MB85231-12

CAPACITANCE

FUJITSU
IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII!IIIIIII11111111111

(TA=25°C, f=1MHz)

Parameter

Symbol

Typ

Max

Unit

-

56

pF

47

pF

49

pF

46

pF

14

pF

Unit

Input Capacitance, AO to A9

CIN1

Input Capacitance, RAS

CIN2

Input Capacitance, CAS

CIN3

-

Input Capacitance, WE

CIN4

-

I/O Capacitance, DOO to D07

CDQ

RECOMMENDED OPERATING CONDITIONS
(Referenced to VSS)
Parameter

Symbol

Min

Typ

Max

Vee

vss

4.5
0

5.0
0

5.5
0

V
V

Input High Leve. all Inputs

VIH

2.4

6.5

V

Input Low Level, all Inputs
all DOs

ViL1
VIl2

-2.0

0.8
0.8

V
V

Operating Temperature
Range

TA

0

Supply Voltage

Note:

"
*2

-1.0. 1
25

70*2

·C

The device will withstand undershoots to the -2. OV level with a maximum pulse width of 20ns at
the -1.5V level.
Maximum ambient temper"ture is permissible under certain conditions.

5-23

.IMIMII~IMIII~llloomIMWIII!
FUJITSU
i1111111111111111111111111111M1111111111

MB85231-10
MB85231-12

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter
OPERATING CURRENT'
Supply Current
(RAS, CAS cycling; tRc=mln.)

Symbol

Typ

Max

mA

ICC1
MB65231-12

STANDBY CURRENT
Power Supply Current
(RAS = CAS = VIH)

CMOS level

REFRESH CURRENT 1

MB65231-10

400
16

TTL level
IC02

440
mA

MB65231-12

NIBBLE MODE CURRENT
Supply Current
(RAS=VIL, CAS=mln cycling)

MB65231-10

REFRESH CURRENT 2
Average Power Supply Current
(CAS-before-RAS; tRc=mln)

MB65231-10

360
320
mA

IcC4

~age P~

mA

6

ICC3

~age P~ Supply

Unit

460

MB65231-10

~~wer

Current
(CAS=VIH; RAS=mln cycling)

Min

MB65231-12

264
440
ICC5

mA

MB65231-12

360

INPUT LEAKAGE CURRENT

ilL

-30

30

jJ.A

OUTPUT LEAKAGE CURRENT

IOL

-10

10

jJ.A

OUTPUT HIGH LEVEL (loH=-5mA)

VOH

2.4

OUTPUT LOW LEVEL (IOL=4.2mA)

VOL

V
0.4

Nole: ' Icc Is dependent on oulput loading and cycle rates. Specified values are obtained with the output open.

5-24

V

111111111111111111111111111111111111111111111

MB85231-10
MB85231-12

FUJITSU
11111111111111111111111111111111111111111111111111111111111111111

AC CHARACTERISTICS
(At recommended operating conditions otherwise noted.) Notes 1, 2, 3
Symbol

Parameter
NOTES
Time Between Refresh

MB85231-10
Min.

Max.

MB85231-12
Min.

8.2

tREF

Unit

Max.
8.2

ms

Random Read/Write Cycle Time

4

tRC

Access Time from RAS

5,8

tRAC

100

120

ns

Access Time from CAS

6,8

tCAC

30

35

ns

Access Time from Column Address

7,8

tAA

50

60

ns

180

210

Output Data Hold Time

tOH

10

10

Output Buffer Turn On Delay Time

tON

5

5

Output Buffer Turn Off Delay Time

9

25

tOFF

ns

ns
ns

25

ns

50

ns

Input Transition Time

tT

RAS Precharge Time

tRP

RAS Pulse Width

tRAS

100

RAS Hold Time

tRSH

30

35

CAS to RAS Precharge Time

tCRP

0

0

tRCD

20

CAS Pulse Width

tCAS

30

35

ns

CAS Hold Time

tcsH

100

120

ns

Row Address Setup Time

tASR

0

0

ns

Row Address Hold Time

tRAH

15

15

ns

Column Address Setup Time

tASC

0

0

ns

Column Address Setup Time

tCAH

15

20

tRAD

20

Column Address to RAS Lead Time

tRAL

50

60

Read Command Setup Time

tRCS

0

0

ns

Read Command Hold Time
Referenced to RAs

tRRH

0

0

ns

13

Read Command Hold Time
Referenced to CAS

tRCH

0

0

ns

13

Write Command Setup Time

14

RAS to CAS Delay Time

RAS to Column Address Delay Time

10,11

12

3

50

3

ns

80

70
100000

70

50

120

20

20

100000

ns
ns
ns

85

ns

ns

60

ns
ns

twcs

0

0

ns

Write Command Hold Time

tWCH

15

20

ns

WE Pulse WIdth

twp

15

20

ns

Write Command to RAS Lead Time

tRWL

25

30

ns

Write Command to CAS Lead Time

tCWL

20

25

ns

DIN Setup Time

tDS

0

0

ns
ns

DIN Hold Time

tDH

15

20

Nibble Mode Read/Write Cycle Time

tNC

50

55

Access Time from CAS Precharge
Nibble Mode CAS Precharge Time

8,15

60

tCPA
tNCP

15

ns

55
15

ns
ns

5-25

I I I I I I I I I I I I I~I I I I I I I I I I I!I I I 1 1 1 1
FUJITSU
1111111111II1IIIIIIIIIIIIIIIIIII1IIII1IIIIIIIIIIIIII1IIIIIIIIII

MB85231-10
MB85231-12

AC CHARACTERISTICS(Continued)
(At recommended operating conditions otherwise noted.)

Notes

MB85230-10

Symbol

Parameter

NOTES

1, 2, 3

Min.

Max.

MB85230-12
Min.

Unit

Max.

CAS Precharge Tlme(CAS-before RAS refresh)

tCPN

15

15

ns

RAS Precharge Time to CAS
Active Time (Refresh Cycles)

tRPC

a

a

ns

CAS Setup Time for CAS-beforeRefresh

tCSR

a

a

ns

CAS Hold Time for CAS-beforeRAS Refresh

tCHR

15

20

ns

Ms

NOTES;
1. An Initial pause (RAS=CAS=VIH) of 200 jJ.s is required after power-up followed by any 8 RAS-only cycles before proper
device operation Is achieved. In case of using Internal refresh counter, a minimum of 8 CAS-before-RAS Initialization
cycles Instead of 8 RAS cycles are required.
2. AC characteristics assume tT=5ns
3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured
between VIH (min) and VIL (max).
4. The minimum cycle time depends up,on the ambient temperature and cooling condition. See Fig. 3.
5. Assumes that tRCD :::;; tRCD (max). If tRCD Is greater than the maximum recommended value shown In this table, tRAc
will be Increased by the amount that tRCD exceeds the value shown. Refer to Fig. 4 and 5.
6. If tRCD ;;::: tRCD (max). tRAD ;;::: tRAD (max). and tASC ;;::: tAA-tCAS-tT. access time is tCAC.
7. If tRAD ;;::: tRAD (max). tASC;;::: tAA-tCAS-tT. access time Is tAA.
8. Measured with a load equivalent to two TTL loads and 100 pF.
9. tOFF is specified that output buffer changes to high Impedance state.
10. Operation within the tRcD (max) limit Insures that tRAC (max) can be met. tRAC (max) is specifies as a reference point
only; If tRCD Is greater than the specified tRCD (max) limit. access time Is controlled exclusively by tCAS or tAA.
11. tRCD (min) = tRAH (min) +2tT + tASC (min).
12. Operation within the tAAD (max) limit Insures that tAAC (max) can be met. tAAD (max) Is specified as a reference point
only; if tAAD is greater than the specified tAAD (max) limit. access time Is controlled exclusively by tCAC or tAA.
13. Either tAAH or tACH must be satisfied for a read cycle.
14. twcs Is specified as a reference point only. If tWCS(min) .the DOn pins will maintain Impedance(High-Z) state
throughout the entire cycle.
15. tCPA is access time from the selection of a new column address (that is caused by changing CAS from VIL to VIH.) .
Therefore. If tcp Is short. tCAC Is longer than tCAC (max).

5-26

111111111111111111111111111111111111111111111111111111IIIIIII!III

MB85231-10
MB85231-12

FUJITSU
11111111111111!!IIIII!llllllllllllllllllllllllilllllll111111111

Fig, 3 - MB85230 DERATING CURVE (Normal Cycle)

'""'
U
0

, ....

70

~- -~
........

'-'

~

d.l

S'

~
--...

~

60

I.

1

.

..

.............

"-

d.l

f-<

1

' .

'..I.'. '.

,"-

~
d.l

j
~

50

I

Not allowable

Allowable

r--..........

~

.

...-;

.... ......

Air Flow
1_ _ _ _ _ _ _ _ _ _

"

•••••.....

o mls
1 mls
2 mls

40
0

2

1

3

4

5

lItRC, Cycle Rate (MHz)

Fig. 4 - tRAC vs tRCD

160
140
120

~20n~
100ns Version

100
80

'"

I
I I
I I
I I

II
20 40 60 80 100 120
t Reo (ns)

Fig. 5 - tRAC vs tRAD

160
140
120

~20n~
100ns Version

100
80
,~

I
I I
I I
I I

II
20 40 60 80 100 120
t RAD (ns)

5-27

I11111111111111111111111111111111111111111111111111111II

FUJITSU
11111111111111111111111111111111111111111111111111111111111

MB85231-10
MB85231-12

READ CYCLE

~--------------tRC------------------~

-----:!L~----------- tRAS -------------1 J,,~-~
VIHVIL-

VIHVIL-

ADDRESSES

VIHVIL -

iiIV-~_.....-;,r ""iiiiV·"H-'l.I~~~

VIHVIL-

DOUT

VOHVOL ------

HIGI~-Z·-------;}S,~_..;;.;..;..;.;.;...~:or

Il(~\;\j:;\: j: : ]

5-28

Don't Care

IIIIIIIIIII~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII~II

MB85231-10
MB85231-12

FUJITSU
11111111111111111111111111111I111111111111111

WRITE CYCLE (Early Write)

~---------------tRC --------------~

VIH- - - -.....t~----------
VIL-

VIHVIL-

ADDRESSES

VIHVIL-

WE

VIHVIL-

Do
(INPUT

VIHVIL-

5-29

I11111I111111111111111111111111111111111111

FUJITSU
WIIIIIIIIIIIIIIIIIIIIIIIIIIIIIOOIIIIIIIIIII

MB85231-10
MB85231-12

NIBBLE MODE READ CYCLE

tRP

~-----------------tRAS----------------~

1lAS

DO
(OUTPUT)

VIL-

VOH-:_ _ _ _ _+-Q,<,,"~
VOL
"""-"'"""'-_WIr

I~t~~~~~~lt:il Don t Care
I

1>'>""~llnvalld Data
,I"

NIBBLE MODE WRITE CYCLE

DO
(INPUT)

5-30

",

M885231-10
M885231-12

FUJITSU

RAs-ONLY REFRESH CYCLE
NOTE: WE, DO (Input) = Don't Care, A9=VIH or VIL
~-----------------tRC----------------~~

'RA"§"

Ao - As

"CAS

DOUT

V 1H V1L -

V 1H V 1L -

V1HVIL -

V OH VOL -

h:::::::::::::::1

Don't Care

CAS-BEFORE-RAS REFRESH CYCLE
NOTE: ADDRESS, WE, DO (Input) = Don't Care

~-------------tRC--------------~

,-----------~~ ~~----tRAS----~~ j~--------~

DQ
(OUTPUT)

VOH VOL -

---------.Q
.....------------------------ HIGH-Z--------------------_ _ _ _....

5-31

III~IIIMIIIMWIIIIIII~III~IIIIIII
FUJITSU
IIUIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

MB85231-10
MB85231-12

HIDDEN REFRESH CYCLE

VIHVIL-

VIHVIL-

ADDRESSES VIHVIL-

WE

(Read)

VIHVIL-

DQ
(Output)

l@j:jj:!!~f~1

5-32

Don't Care

IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII!IIIIIIIIIIIII!I

MB85231-10
MB85231-12

FUJITSU
1111111111111I111111111111111111111111111111111111111111111111111

DESCRIPTION
Block Analysis:
As shown In Fig. 1 and Fig. 2, the MB85231 Is composed of eight MB81C1001, and the memory selection of the each
MB81C1001 consists of a 1024-by-1024 cell matrix.
Operational modes of this module are specified below.

Address Inputs:
A total of twenty binary Input address bits are required to dec de any 8-blt of the 8,388,608 storage cells within the MB85231.
Ten row address bits are established on the address Input pins (Ao to A9) and latched with the Row Address Strobe. RAS.
The ten column address bits are established on the address Input plns(Ao to A9) and latched with the Column Address
Strobe, CAS. All row and column addresses must be stable on or before the falling edge of RAS and CAs, respectively.
Since the flow through type address latches are used, address Information at address pins are automatically latched as column address after tRAH (min) + tT. If tRAD ~ tRAD (max), access time Is tCAC or tAA whichever occurs later.

Write Enable:
Read or Write mode is selected with the WE Inputs. A high on WE selects read cycle and low selects write mode.

Data Input/Output:
1. Data Input;
In write cycle, the 8-blt data is written into the MB85231 during write cycle through each DO pins. Each Input data Is
strobed and latched by failing edge of CAS, and WE must be brought to VIL before failing edge of CAS, data Input
strobed by CAS, and setup and hold times are referenced to CAS.

2.

Data Output;
The output buffers on each chip are three state TTL compatible with a fan ~of 2 TTL loads. Output data has the
same porallty as input data. The outputs are In high Impedance state until CAS Is brought low. In a read cycle, the
output becomes valid within tCAC or tAA whichever occurs later after failing edge of CAs. The data output remans
valid until CAs returns to high.

Read Cycle:
The read cycle Is executed by keeping both RAs and CAS;VIL and keeping WE;VIH throughout the cycle. The row and column addresses are latched with RAS and CAS, respectively. The output data is remain valid with CAS;VIL, I. e., If CAS goes
VIH, the data becomes Invalid with tOH. The access time Is determined by RAS (tRAC), CAs (tCAC) , or Column address Input
(tAA). If tRCD(AAS' to CAs delay time) is greater than the specification, the access time Is tCAC. If tRAD Is greater than
the specification. the access time Is tAA.

Write Cycle:

We.

The write cycle Is executed by the same manner as read cycle except for the state of
The 8-blt data on DO pins are
latched with the failing edge of CAS and written Into memory. In addition, during write cycle, tRWL, tCWL, and tRAL must be
satisfied the specifications.

Nibble Mode:
The nibble mode Is a 4-blt serial access mode allows high speed addressing with CAS during read or write cycle. The each
cell accessed drlng nibble mode are determined by the combination of row and column address on A9(RA9 and CA9). The
two address are used to select one of four bits for Initial access. After the first bits Is accessed by normal read or write
mode, the remaining nibble bits can be accessed by toggling CAS, high to row level. Toggling CAS causes RA9 and CA9 to
be increased internally while all other address bits are held constant and makes the next nibble bit available for access.
Refer to Table 1 for nibble mode address sequence.
If more than four bits are accessed during nibble mode, the address sequence will begin to repeat.
1.

Nibble Mode Read Cycle:
The nibble mode write cycle Is also executed after normal cycle with holding RAS;VIL, applying column address and CAS,
and keeping WE;VIH. Since all address during nibble mode cycle is latched by normal cycle, the read operation is simplified.

2.

Nibble Mode Read Cycle:
The nibble mode write cycle Is also executed by the sa~anner as nibble mode read cycle except for the state of WE.
The data on each DO Is latched with the falling edge of CAS and written Into the memory.

5-33

11111111111111111111111111111111111111111111111111111111111111111

FUJITSU
1111111111111111111111111111111111111111111111111111111111111111

MB85231-10
MB85231-12

DESCRIPTION

(Continued)

Refresh:
The refresh of DRAM Is executed by normal read and write cycle, i. e., the cells on each one row line, Ao through As except
for A9, are refreshed by one of two cycles. Each 512 row address must be refreshed every 8. 2ms period. During the refresh cycle, the cell data connected to the selected row are sent to sense amplifier and re-write to the cell. The MB85230
also has three types of refresh modes, RAs-only, CAS-before-RAS. and Hidden refresh.

1.

RAS-only Refresh;
The RAS-only refresh Is executed by keeping RAS=VIL and keeping CAS=VIH through the cycle. The row address to be
refreshed Is latched with the failing edge of RAS. During this refresh. the DQ pins are kept high impedance state.

2.

CAS-before-RAS Refresh;
The CAS-before-RAS refresh Is executed by bringing CAs=VIL before Ms. By this combination, the MBB5231 executes
CAS-before-RAS refresh. The row address Input is not necessary because It Is generated Internally.

3.

Hidden Refresh;
The hidden refresh Is execute dby keeping CAs=VIL to next cycle during read mode, I. e., the output data at previous
cycle Is kept during next refresh cycle. Since the CAS is kept VIL continuously from previous cycle. followed refresh
cycle should be CAS-before-AAs refresh.

Table 1 - NIBBLE MODE ADDRESS SEQUENCE
Sequence

Column address

CA9

1

101010101

0

101010101

0

Toggling CAS (nibble mode)

2

101010101

1

101010101

0

Toggling CAS (nibble mode)

3

101010101

0

101010101

1

Toggling CAS (nibble mode)

4

101010101

1

101010101

1

Toggling CAs (nibble mode)

1

101010101

0

101010101

0

5-34

Nibble bit

Row address

RAg

RAS/CAS (normal mode)

)''''"
.,&...
Generated
Internally

Sequence repeats

MB85231-10
MB85231-12

FUJITSU

FUNCTIONAL TRUTH TABLE
Operation
Mode

Clock Input
RAS

CAS

Address Input
WE

Row

Column

Data
I/O

Note

Standby

VIH

VIH

X

High-Z

Cells are not refreshed,

Read
(Normal)

VIL

VIL

VIH

Valid

Valid

Output
Valid

tRCS ;;::: tRcs (min)

Read
(Fast Page)

VIL

VIL

VIH

Valid

Valid

Output
Valid

tRCS ;;::: tRCS (min)
Cells are not refreshed,

Write
(Normal)

VIL

VIL

VIL

Valid

Valid

Input
Valid

twcs ;;::: twcs (min)

Write
(Fast Page)

VIL

VIL

VIL

Valid

Valid

Input
Valid

twcs ;;::: twcs (min)
Cells are not refreshed,

RAS-only
Refresh

VIL

VIH

X

Valid

X

High-Z

VIL

VIL

X

X

X

High-Z

tCRS ;;::: tCRS (min)

VIL

VIL

VIH

X

X

Output
Valid

Previous data Is kept,

-CAS-before-

X

X

RAS Refresh
Hidden
Refresh

Note: X:

*
Don't Care
RAS puts VIH at once,

5-35

~11~MOOIMIIIIIIIIIMIIIOOIII
FUJITSU
111111111111111111111111111111111111111111111111111111III

MB85231-10
MB85231-12

PACKAGE DIMENSIONS
(Suffix:

PJPB)

30-LEAD PLASTIC MODULE (SOCKET TYPE)
(Case No. : MSS-30P-P04)
3.500±.010
(88.90±0.25)
3.234±.005
(82.14+0.13)

-c.=-=13:,::,3,..:.t;.;:.0",,05=-c---+--+- ._ _ _ _
(3.38±0.13)

"I
~200(5.08)
MAX

.125±.005 DIA
(3.18 ±0.13) DIA

R060(1 .52) REF

o

40;r~06_-~-l-+i-.l.jJJjfll-ll..J.UULJ.L.J.LJJ..JJLJ.LJUL.lLll..J.L1UH!J...il-.lLll..J.L1LlL1tJ-.lli.lLlltL-I-l

(10.16tO.15)

~

-.8001020

I

J.
I
I

~

t)_ .

(20.32jO.5...1

.250±.005
(6.35±0.13)
.080+.005
(2.03±0.13)
.300+.008
(7.62±0.20)

_I

.100(2.54) MIN

2.900±.005109(2,~!,:~
"I
(73.66±0.13)

.~~~+~E;]
L~Q:L
,(127+ 0 .15 )
. -0.08

Details of "A" part-- - - ,

:
1

©1989 FUJITSU LIMITED M30013S-:3C

5-36

D

.

~O)

--==r=

TYP

i
I

L ___________ ..J

Dimensions in inches
(millimeters)

I11I111111I111111111111I11111111111I1111I1111111111111Illillllll

MB85231-10
MB85231-12

FUJITSU
111!llllllllllllllillllllllllllllllllllll!111111111111illilll

PACKAGE DIMENSIONS (Continued)
(Suffix:

PJPS)

30-LEAD PLASTIC SINGLE IN-LINE TYPE MODULE
(CASE No_: MSP-30P-P05)

3.125±.010
(79.38±0.25)

"I

~~~~~~~~~

"I

I" .200(5.08)
MAX

.830(21.08)

~ .~10~OW±.~01~0~ ~ ~.0~47H~:~go~,~ ~ .~I~IW.~01~8~ :~g ~ ~ ~ 1(3.1 4~0!_~0:.43~6 )
(2.54±0.25)

(1.20~g:~~)

(0.45~g:6~)

2.900(73.66)REF

t~
.050(1.27)
REF

Dimension in

inches

(millimeters~

",989 FUJITSU LIMITED M300'4S-2C

5-37

CMOS DRAMs

5-38

Dynamic RAM Data Book

11111111111111111111111111111111111111111111

fUJITSU

MB85235-10
MB85235-12

1M x 9 DRAM MODULE

11111111111111111111111111111111111111111111

TS028-B87Z

1,048,576 x 9 BIT DYNAMIC RANDOM
ACCESS MEMORY MODULE

Dec. 1987

The Fujitsu MB85235 is a fully decoded, dynamic CMOS
random access memory module with eight MB8lClOOO, in
26-pin SOJ packages, and nine .22~F decoupling capacitors under the each memory, mounted on a 30-pin
SIP or a 30-pad SIMM module. Organized as 1,048,576
x 9-bit words, the MB85235 PCB module is optimized
for those applications requiring high density and
large memory storage capability. The operation and
electrical characteristics of the MB85235 are the
same as the MB81C1000 devices which feature a Fast
Page mode operation.

PLASTIC PACKAGE
MSP-30P-P04

• 1,048,576 x 9 DRAM, 30-pin SIP and SIMM
• RAS access time (tRAC):
100 ns max. (MB85235-l0)
120 ns max. (MB85235-12)
• Cycle time (tRC)~
180 ns min. (MB85235-l0)
210 ns max. (MB85235-l2)
• Column access time (tCAC):
30 ns max. (MB85235-10)
35 ns max. (MB85235-12)
• Fast Page mode cycle time (tpC):
60 ns max. (MB85235-l0)
70 ns max. (MB85235-l2)
• Dual +5V supply, ±10% tolerance
• Low power:
Active
2970 mW max. (MB85235-10)
2475 mW max. (MB85235-l2)
Standby
49.5 mW max. (CMOS level)
• Refresh:
- 8.2 ms I 512 refresh cycle
- "RAS-only", "CAS-before-RAS" and "Hidden"
refresh capability
• Fast Page Mode Read and Write capability
• Leaded and Leadless type are available.
• JEDEC standard (30 pin SIP) pin assignment

PLASTIC PACKAGE
MSS-30P-P03

PIN ASSIGNMENT
VCC

00
DQO
AO
Al
OQl
A2
A3
Vss
D02
A4
As
003
A6
A7
DQ4
AS
Ag
HC

~s

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Voltage on any pin relative to Vss
Voltage on

Vec

supply relative to Vss

Storage temperature

Symbol

Value

Unit

VIN,VOUT

-1 to +7

V

Vee

-1 to +7

V

.oC

TSTG

-55 to 125

Power dissipation

Po

9.0

W

Short circuit output current

-

50

mA

NOTE:

Permanent device damage may occur. if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

VSS
DQ6
NC
DQ7
08

ru
OOa
Qa
VCC

1
2
3
4
5
6

7
a
9
10

11
12
13
14
15
16
17
la
19
20
21
22
23
24
25
26
27
2a
29
30

0

0
0
00
0
0
00
0
0
00
0

This device contains circuitry to protect the
inputs against damage due to high static volt·
ages or electric fields. However, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi·

mum rated voltages to this high impedance
circuit.

5-39

I~I~I~~~~I!II~IIIIIIII
FUJITSU
1~~~I~li~~~~1I1I11I11111

MB85235-10
MB85235-12

Fig. 1 - BLOCK DIAGRAM
Addresso----.-----.-----.------r-----.-----.-----.------.-----,

ill
WE
CAS

DQO

DQl

DQ2

Chip
3

Chip
4

Chip
S

Chip
6

Chip
7

Chip
S

DQ3

DQ4

DQS

DQ6

DQ7

DS Qs

Fig. 2 - BLOCK DIAGRAM FOR EACH CHIP

.,...
Eli!"

WE

DIN

DOUT

--Vee

--Vss

CAPACITANCE

(TA=2S oC, f=lMHz)

Parameter
Input Capacitance, AO to A9
Input Capacitance, RAS
Input Capacitance, CAS

Symbol
CINI
CIN2
CIN3

Input Capacitance, WE
Input Capacitance, CASS
Input Capacitance, DS

CIN4

I/O Capacitance, DQO to DQ7
Output Capacitance, QS

CDQ

CINS
CD
Co

Typ

-

Max

Unit

60

pF

49

pF

49

pF

4S

pF

9

pF

7

pF

14

pF

10

pF

~II~IIIIII~III~~~I~II~III~~!
FUJITSU
IIIII~II~IIIIIII~III~IIII~~IIIII~

MB85235-10
MB85235-12

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Parameter

Symbol

Min

Value
Tvp

Max

5.0
0

5.5
0

V
V

Unit

Supply Voltage

VCC
VSS

4.5
0

Input High Level, all inputs

VIH

2.4

6.5

V

Input Low Level,. all inputs
all DQs

VILl
VIL2

-2.0
-1. 0*1

O.B
O.B

V
V

Operating Temperature Range

TA

0

°c

70~,2

25

Note: *1 The device will withstand undershoots to the -2.OV level with a maximum
pulse width of 20ns at the -1.5V level.
*2 Maximum ambient temperature is permissible under certain conditions.

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Parameter (conditions)

OPERATING CURRENT'"
Supply Current
(RAS, CAS cycling;tRC=min.)

Symbol

MBB5235-12

Current
(RAS = CAS = VIH)

CMOS level

REFRESH CURRENT 1

MBB5235-10

A~age Po~

Supply Current
(CAS=VIH, RAS=min cycling)

MBB5235-12

FAST PAGE MODE CURRENT

MBB5235-10

Average Po~ Supply Current
(RAS=VIL, CAS=min cycling)

MBB5235-12

REFRESH CURRENT 2

MBB5235-10

A~age Powe~upply

Current
(CAS-before-RAS; tRC=min)

MBB5235-12

Max

Unit
rnA

ICC1

450
1B

TTL level

P~r S~ly

Value
Tvo

540

MBB5235-10

Averag~ower

STANDBY CURRENT

Min

rnA

ICC2

9
495
rnA

ICC3

405
360
rnA

ICC4

297
495
rnA

ICC5

405

INPUT LEAKAGE CURRENT, all inputs

IIL1

-30

30

llA

INPUT LEAKAGE CURRENT, CASB and DB

IIL2

-10

10

llA

OUTPUT LEAKAGE CURRENT

IOL

-10

10

llA

OUTPUT HIGH LEVEL (IOH=-5mA)

VOH

2.4

OUTPUT LOW LEVEL (IOL=4.2rnA)

VOL

Note:

*

V
0.4

V

ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.

5-41

IIIIIIIIIIIIII~II~IIIII~II~I~II~II
FUJITSU
IIIIIIIII~IIIIIII~II~I~IIIIIIIII~II

MB85235-10
MB85235-12

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
Parameter

NOTES

Time Between Refresh
Random Read/Write Cycle Time
4
Access Time from RAS
5 8
Access Time from CAS
6 8
Access Time from Column
Address
7 8
Output Data Hold Time
Output Buffer Turn On Delay
Time
Output Buffer Turn Off Delay
Time
9
Input Transition Time
RAS Precharge Time
RAS Pulse Width
RAS Hold Time
CAS to RAS Precharge Time
RAS to CAS De1av Time
10 11
CAS Pulse Width
CAS Hold Time
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
Column Address Setup Time
RAS to Column Address Delay
Time
12
Column Address to RAS Lead Time
Read Command Setup Time
Read Command Hold Time
Referenced to RAS
13
Read Command Hold Time
Referenced to CAS
13
Write Command Setup Time
14
Write Command Hold Time
WE Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
DIN Setup Time
DIN Hold Time
Fast Page Mode Read/Write Cycle
Time
Access Time from CAS Precharge
8 15
Fast Page Mode CAS Precharge
Time
CAS Precharge Time
RAS Precharge Time to CAS
Active Time (Refresh Cycles)
CAS Setup Time for CAS-beforeRAS Refresh
CAS Hold Time for CAS-be foreRAS Refresh

5-42

Notes 1, 2, 3

tREF
tRC

MB85235-10
Max
Min
8.2
180

MB85235-12
Min
Max
8.2
210

tRAC
tCAC
tAA

100
30
50

120
35
60

Symbol

tOH
tON

10
5

tOFF

ms
ns
ns
ns
ns
ns
ns

10
5
25

Unit

25

ns

50

ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

tT
tRP
tRAS
tRSH
tCRP
tRCD
tCAS
tCSH
tASR
tRAH
tASC
tCAH
tRAD

3
70
100
30
0
20
30
100
0
15
0
15
20

tRAL
tRCS
tRRH

50
0
0

60
0
0

ns
ns
ns

tRCH

0

0

ns

twcs
tWCH
twp
tRWL
tCWL
tDS
tDH
tpc

0
15
15
25
20
0
15
60

0
20
20
30
25
0
20
70

ns
ns
ns
ns
ns
ns
ns
ns

tCPA

50
100000
70

50

3
80
120
35
0
20
35
120
0
15
0
20
20

100000
85

60

70

60

ns

tcp

15

15

ns

tCPN
tRPC

15
0

15
0

ns
ns

tCSR

0

0

ns

tCHR

15

20

ns

1IIIIIIIillllllllllllllllllllllllllllili

FUJITSU
I I I I I I~I I I I I I I I I I I I I I

MB85235-10
MB85235-12

AC CHARACTERISTICS

(Cont'd)

(At recommended operating conditions unless otherwise noted.)
Parameter

NOTES
Read-Modify-Write Cycle Time
16
Fast Page Mode Read-Modify-Write
Cycle Time
16
RAS to WE Delay Time
14 16
CAS to WE Delay Time
14 16
Column Address to WE delay Time
14 16

Notes 1, 2, 3

"RWC

MB85235-10
Min
Max
210

MB85235-12
Min
Max
245

"PRWC

85

100

ns

tRWD
"CWD
tAWD

100
30
50

120
35
60

ns
ns
ns

Symbol

Unit
ns

IIlTES;
1. An initial pause (RAS"CAS/CASa"V IH ) of 200 \-Is is required after power-up followed by any a RAs-only cycle!

before proper device operation is achieved. In case of using internal refresh counter, a minimum of
8 CAS-before-RAS initialization cycles instead of a RAS cycles are required.
2. AC characteristics assume t T"5ns
3. VIH (min) and VIL (max) are reference levels for measuring timing of input signals.
times are measured between VIH (min) and VIL (max).

Also, transition

4. The minimum cycle time depends upon the ambient temperature and cooling condition. See Fig.4.
5. Assumes that t RCD :::: t RCD (max). If t RCD is greater than the maxi mum recommended value shown in th i"
table, tRAC will be increased by the amount that t RCD exceeds the value shown. Refer to fig. 2 ''''(\ ,L
6. If t RCD

~

tRCD (max), tRAD

~

tRAD (max), and t ASC

~

7. If tRAD

~

tRAD (max), t ASC

~

tAA-tCAC-tT' access time is t AA .

tAA-tCAC-tT' access time is t CAC '

a. Measured with a load equivalent to two TTL loads and 100 pF.
9. tOFF is specified that output buffer changes to high impedance state.
10. Operation within the t RCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as
a reference point only; if t RCD is greater than the specified t RCD (max) limit, access time is controlled exclusively by t CAC or t AA .
11. t RCD (min) " tRAH (min) + 2tT + t ASC (min).
12. Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as
a reference point only; if tRAD is greater than the specified tRAD (max) limit, access time is controlled exclusively by t CAC or t AA •
13. Either tRRH or t RCH must be satisfied for a read cycle.
14. t wcs , t RWD ' tCWD' and t AWD are specified as a reference point only. If twcs ~ twcs (min), the cycle
is early write cycle and the output pins will maintain high impedance(High-Z) state throughout the
entire cycle. If t RWD ~ t RWD (min), tCWD ~ tCWD (min), and t AWD ~ tAWD (min), the cycle is a readmodify-write cycle and data from the selected cell will appear at the output pins.
If neither of the above conditions is satisfied, the cycle is a delayed write cycle and invalid data
will appear at the output pins, and write operation can be executed by satisfing tRWL' tCWL' and tRAL
specifications.
15. tCPA is access time from the selection of a new column address (that is caused by changing CAS/CAS a
from VIL to VIH .). Therefore, if tcp is short, t CAC is longer than t CAC (max).
16. For parify bit only.

5-43

IIII~IIIIIIIIII~~~I~IIIIIIIIIIIIIII

FUJITSU

II~IIIIIIIIII~~II~IIIIIIIIIIIIIIII~

MB85235-10
MB85235-12

Fig.3 - DERATING CURVE (Normal Cycle)

T.B,D.

Fig.4 - DERATING CURVE (Fast Page Mode Cycle)

T,B,D,

Fig.5 - tRAC

c

160

160
140

120
100

T

vs

tRAD

~

120n5 Version

-0 120

«

I

.'!' 100

1DOns Versio~

i iI

80

5-44

Fig.6 - tRAC

tRCD

140

-0
;

vs

II

I

20

I
I
I I

40

I
I
I
I
I

60

1DOns Version

I

I

I
I
I
I
I
I
I
I
I

20

40

60

80

I
I
I
80 100 120

T

I
I
I
I
I
I
I
I
I
I

II

80

I

I

100 120

MB85235-10
MB85235-12

Read Cycle
~---------------------tRc---------------------i
~------------tRAS--------------~

----t-------tRsH

V 1H -

___-Y__-++-______-r~r------tCAS-----~ A-~~--------------

V 1L-

ADDRESS

VO H -

DQ & Qa v
(OUTPUT)

-------HIGH.Z-----fl

ADDRESS

WE
DQ & QS VOH-_ _HIGH.Z
(OUTPUT) VOL-

ED Don't Car.
~ Valid Dati

IZ2I Invalid Data

Fast Page Mode Write Cycle
r----------------------tRAS----------------------~

RAS

ADDRESS

DQ & D
(INPUT) 8

V1H_

V 1L -

o

Don't Care

111~llill~~!lllni~I~1
FUJITSU
!i~li~~i~I~IM~!~i

MB85235-10
MB85235-12

Read-Modify-Write Cycle
r----------------------------tRWC:----------------~------~
r---------------------tRAS-------------------;j~----~

r-------------------t~H

CAS a

VIH -- ~::tr+t----_::Ib_"
V 1L --

teAS

~--+----------------tRAL,------------ri

ADDRESS

VOH-- ___~r_-----VOL-

=

r------------tRAC ------------;

~:: t:~.~@~~;;~~:,~,~~b~:,:i~r.;::;B::#.}~~~;~*7 1<-....::::=::...:.r ·:r~~~i~~~J!:~~~~:.~.
!Il Don't Co,.

~ Invalid Date

Fast Page Mode Read-Modify-Write Cycle
r------------------tRAS-----------------;

RAS

CASa

ADDRESS

WE

Qa
Da

V1L-

VIH __
VIL-

VOH __

VALID
DATA

VOLVIH __
V1L __

VA~~~ """-"-"'-'i',-~DATA

o

Don't Core

:-,."-.:,-,,
....'''_''_'_'_ _ _ __

f?lJ Invalid Dote
5-47

illlllllllll~IIIIIIIIIIII~II~1111111
FUJ ITSU
IIIIIIIIIIIIIIIIIIII~IIIIIIIIIIIIIII

MB85235-10
MB85235-12

RAS-only Refresh Cycle
NOTE: WE,D, DQ(Input)=oon't care, Ag=VIH or VIL

t--------tRC-------i

RAS
i - - -t A P - - - - i

ADDRESS

V,H-----+----------i:-------V,L - - - - - - ' 1

DQ & Q
(OUTPUT) S

VO HVOL -::::::::::::;;Flt-------DOon'tCare

CAS-before-RAS Refresh Cycle
NOTE: Address, WE, D, DQ(Input)=Oon't care

f------tAc.--------l
t----tRAs,---i

tCHA

DQ & Qs VOH-:===~-----_--HIGH.Z--------
(OUTPUT) V

OL -

5-48

~11~11~lllilllllllillilllllllll
FUJ ITSU

MB85235-10
MB85235-12

Ilillli~llilllill~IIIIII~11111

Hidden Refresh Cycle

VIH-~~"-+~=-!'r"..

tCHR

VILADDRESS

toFF

DQ

&

QS

(OUTPUT)

~OH=HIGH-Z------~~===~VA~L~ID~D~A~TA~==jf----OL

o

Don't Care

~ Invalid Data

5-49

IIIIIIIIIIIIIIII~II~IIIII~IIIIIIIIII
FUJITSU
I111111111111111111111111111111111111

MB85235-10
MB85235-12

DESCRIPTION
Block Analysis:
As shown in Fig. 1 and Fig. 2, the MB85235 is composed of nine MB81C1000, and the
memory selection of the each MB81ClOOO consists of a 1024-by-1024 cell matrix.
Operational modes of the device are shown in the FUNCTIONAL TRUTH TABLE below.
Address Inputs:
A total of twenty binary input address bits are required to decode any 9-bit of the
9,437,184 storage cells within the MB85235. Ten row address bits are established on
the address input pins (AO to Ag) and latched with the Row Address Strobe, RAS. The
ten column address bits are established~n~e address input pins(AO to Ag) and
latched with the Column Address Strobe, CAS/CAS8. All ~ and column addresses must
be stable on or before the falling edge of RAS and CAS/CAS8, respectively. Since the
flow through type address latches are used, address information at address pins are
automatically latched as column address after tRAR (min)+ tT. If tRAD ~ tRAD (max),
access time is tCAC or tAA whichever occurs later.
Write Enable:
Read or Write mode is selected with the WE inputs.
and low selects write mode.

A high on WE selects read cycle

Data Input/Output:
1. Data Input j
In write cycle, the 9-bit data is written into the MB85235 during write cycle
thr~h~ch DQ ~d D pin. Each input data is strobed and latched~ falling edge
of CAS/CAS8 and WE must ~brought to VIL before falling edge of CAS/CAS8~a~
input is strobed by CAS/CAS8, and setup and hold times are referenced to CAS/CAS8.
2. Data Output j
The output buffers on each chip are three state TTL compatible with a fan out of
2 TTL loads. Output data has the same porality as input data. The outputs are in
high impedance state until CAS and CAS8 are brought low~n a read cycle, the output becomes valid within tRAC from the falling edge of RAS when tRCD(max) is
satisfied. In the meanwhile when either tRCD or tRAD, or both, are equal or
greater than their maximum value, the output data becomes valid within tCAC or tAA
whichever oc~s lat~after falling edge of CAS/CAS8. The data output remains
valid until CAS and CAS8 return to high.
Read Cycle:
The read cycle is executed by the falling edge of both RAS and CAS/CASS, and ke~ng
WE t~i~throughout the cycle. The row and column addresses are latched with RAS
and CAS/CAS8 r~ectively~The valid data will appear at the DQ and Q pins~ter ___
determined by RAS(tRAC), CAS(tCAC), or Column address input(tAA). If tRCD(RAS to CAS
delay time) is greater than the specification, the access time is tCAC. If tRAD is
greater th~t~specification, the access time is tAA. The output data becomes invalid after CAS/CAS8 is brought high, with a delay time of tOR' and the DQ and Q pins
return to the high impedance with tOR.
Write Cycle:
The write cycle is executed by the same manner as read cycle except for the state of
WE. The 9-bit data on DQ and D pins are latched with the falling edge of CAS/CAS8
and written into memory. In addition, during write cycle, tRWL' tCWL, and tRAL must
be satisfied the specifications.

5-50

IIIIIIIIIIIIIIIIIII~
FUJITSU
I I I I I I I I I I I I I I I~I I I I I

MB85235-10
MB85235-12

DESCRIPTION

(Continued)

Fast Page Mode Read Cycle:
The fast page mode read cycle is executed after normal cycle with holding RAS low,
applying column address and CAS/CAS8, and keeping WE high. Since the row address
during fast page mode cycle is latched by normal cycle, the cycle time is reduced.
During this mode, the access time is tCAC, tAA, or tCPA, whichever occur later. Any
of the 1024 bits belonging to each internal row address can be accessed.
Fast Page Mode Write Cycle:
The fast page mode write cycle is executed by
cycle except for the state of WE. The data on
falling edge of CAS/CAS8 and written into the
must be satisfied. Any of 1024 bits belonging
accessed.

the same manner as fast page mode read
each DQ and D are latched with the
memory. During this write cycle, tCWL
to each internal row address can be

Refresh:
The refresh of DRAM is executed by normal read and write cycle, i.e., the cells on
each one row line, AO through A8 except for Ag, are refreshed by one of two cycles.
Each 512 row address must be refreshed every 8.2ms period. During the refresh cycle,
the cell data connected to the selected row are sent to sense amplifier and re-write
to the cell. The MB85231 also has three types of refresh modes below.
1. RAS-only Refresh;
The RAS-only refresh is executed by keeping RAS low, and CAS/CAS8 remains high
through the cycle. The row address to be refreshed is latched with the falling
edge of RAS. During this refresh, the data pins are kept high impedance state.
2. CAS-before-RAS Refresh;
The CAS-before-RAS refresh is executed by bringi~CAS/CAS8~w before RAS brought
low. By this combination, the MB85235 executes CAS-before-RAS refresh. The row
address input is not necessary because it is generated internally.
3. Hidden Refresh;
The hidden refresh is executed by keeping CAS/CAS8 low to next cycle during read
mode, i.e.~he ou~t data at previous cycle is kept during next refresh cycle.
Since the CAS and CAS8 are kept low continuously from previous cycle, followed
refresh cycle should be CAS-before-RAS refresh.

5-51

I I I I I I I I I ~I I I I I I I I I I
FUJITSU

IIIIIIIIIIIIIIIIIIIIII~IIIIIIIIII~IIII

MB85235-10
MB85235-12

FUNCTIONAL TRUTH TABLE
Clock Input

Address Input

Operation
Mode

RAS

CAS(S)

WE

Row

Standby

VIH

VIH

X

X

Read
(Normal)

VIL

VIL

VIH

Valid

Read
(Fast Page)

VIL

VIL

VIH

Write
(Normal)

VIL

VIL

Write
(Fast Page)

VIL

RAS-only
Refresh

Column

Data
I/O

Note

High-Z

Cells are not refreshed.

Valid

Output
Valid

tRCS

Valid

Valid

Output
Valid

tRCS ~ tRCS (min)
Cells are not refreshed.

VIL

Valid

Valid

Input
Valid

twcs

VIL

VIL

Valid

Valid

Input
Valid

twcs ~ twcs (min)
Cells are not refreshed.

VIL

VIH

X

Valid

CAS-beforeRAS Refresh

VIL

VIL

X

Hidden
Refresh

VIL

VIL

VIH

~~

Note: X; Either VIH or VIL.
,~; RAS puts VIH at once.

5-52

X

~

~

tRCS (min)

twcs (min)

X

High-Z

X

X

High-Z

tCSR

X

X

Output
Valid

Previous data is kept.

~

tCSR (min)

1111111111111111111111111111111111111111

FUJITSU

~IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

MB85235-10
MB85235-12

PACKAGE DIMENSIONS
(Suffix: PJPS)
3D-LEAD PLASTIC SINGLE IN-LINE TYPE MODULE
(CASE No.: MSP-3DP-PD4)

3.125±.010
(79.38±0.251

·1

~~O~F=O~F=~~~~~~~~~O~~O~>JF=O~~

.

I ..200(5.081
t

MAX

.830(21.081

MAX

.11 .018~:ggj

--1f--l---::.:=-::100±.01 0
(2.54±0.251

(0.45 ~g: 6~ 1

.134~:g:~
(3.40~g:~~1

2.900(73.66IREF

~~
G50(1.271
REF
Dimension in
inches (millimeters)
Cl1989 FUJITSU LIMITED M300f2S·2C

5-53

1111111111111111111111111111111111111111

FUJITSU

MB85235-10

1111111111111111111111111111111111111111

MB85235-12

PACKAGE DIMENSIONS
(Suffix: PJPB)
30·PAD PLASTIC SINGLE IN·LlNE TYPE MODULE
(CASE No.: MSS·30P·P03)

t·
I

I

~~lSJ~~~~~~

.050~gg~

--.+0.15

11.27-0.081

@19B9 FUJITSU LIMITED M30011 S<3C

5-54

Dimension in
inches (millimeters)

IIIIIIIIIIIIIIIIIIIIIIIII~IIIIIIIIIIIIIIIII

fUJITSU

MB85237-10
MB85237-12

1M x 9 SCRAM MODULE

WIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII

TS029-A881
Jan. 1988

1,048,576 X 9 BIT DYNAMIC RANDOM
ACCESS MEMORY MODULE
The Fujitsu MBB5237 is a fully decoded, dynamic CMOS
random access memory module with nine MBBlCl002, in
26-pin SOJ packages, and nine .22~F decoupling capacitors under the each memory, mounted on a 30-pin
SIP or a 3D-pad SIM module. Organized as 1,04B,576
x 9-bit words, the MBB5237 PCB module is optimized
for those applications requiring ·high density and
large memory storage capability. The operation and
electrical characteristics of the MBB5237 are the
same as the MBB1C1002 devices which feature a Static
Column mode operation.
• 1,04B,576 x 9 DRAM, 30-pin SIP and SIMM
• RAS access time (tRAC):
100 ns max. (MBB5237-l0)
120 ns max. (MBB5237-l2)
• Cycle time (tRC):
lBO ns min. (MBB5237-l0)
210 ns max. (MBB5237-l2)
• Address access time (tAA):
50 ns max. (MBB5237-l0)
60 ns max. (MBB5237-l2)
• Static Column mode cycle time (tSC):
55 ns max. (MBB5237-l0)
65 ns max. (MBB5237-12)
• Dual +5V supply, ±10% tolerance
• Low power:
Active
2970 mW max. (MBB5237-10)
2475 mW max. (MBB5237-12)
Standby
49.5 mW max. (CMOS level)
• Refresh:
- B.2 ms / 512 refresh cycle
- "RAS-only", "CAS-before-RAS" and "Hidden"
refresh capability
• Static Column Mode Read and Write capability
• Leaded and Leadless type are available.
• JEDEC standard (30 pin SIP) pin assignment
Rating

Symbol

Value

Unit

V 1N1 VOUT

-1.0 to +7.0

V

Vee

-1.0 to +7.0

V

TSTG

-55 to 125

·c

Power dissipation

Po

9.0

W

Short circuit output current

-

50

mA

Voltage on Vee supply relative to Vss

Storage temperature

PIN ASSIGNMENT
Vee

1

000

2
3

AO
Al

4
5

m

001

6

AZ
A3
VSS

7
8
9

002
A4
As
003

10
11
12
13
14
15
16
17

A6
A7

004
AS
Ag
He

lS
19

005

20
21
22
23
24
25
26
ill 27
l:'.l3s 2S

lit:

ABSOLUTE MAXIMUM RATINGS (See Note)

Voltage on any pin relative to Vss

PLASTIC PACKAGE
MSP-30P-P04

NOTE: Permanent dev,ce damage may occur 'f ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

Vss
006
He
007
Os
08

29

Vee

30

oD
D

D
D
D
D
D
Do

This device contains circuitry to protect the
inputs against damage due to high static volrages or electric fields. However. it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi·
mum rated voltages to this high impedance
circuit.

5-55

~III~~IIII~~~~~~II!I~~III
FUJITSU
i~III!II~~~II!~i~ili!lli

MB85237-10
MB85237-12

Fig. 1 - BLOCK DIAGRAM
Address O----,------,-----,,-----,------r-----,------,-----,-----,
RAS
WE

CAS

DQO

DQZ

DQS

Fig. 2 - BLOCK DIAGRAM FOR EACH CHIP
iiAS------..j

DIN

DOUT

CAPACITANCE

(TA=2SoC, f=IMHz)

Parameter

Symbol

Typ

Max

Unit
pF

49

pF

CIN3

-

60

49

pF

Input Capacitance, WE

CIN4

-

48

pF

Input Capacitance, CAS8

CINS

pF

CD

7

pF

14

pF

Output Capacitance, Q8

Co

-

9

Input Capacitance, D8
I/O Capacitance, DQo to DQ7

10

pF

Input Capacitance, AO to A9
Input Capacitance, RAS

CIN1

Input Capacitance, CAS

5-56

CINZ

CDQ

MB85237-10
MB85237-12

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Symbol

Parameter

Min

Value
Tvp

Max

Unit

5.0
0

5.5
0

V
V

Supply Voltage

VCC
VSS

4.5
0

Input High Level, all inputs

VIH

2.4

6.5

V

Input Low Level, all inputs
all DQs

VILI
VIL2

-2.0
-1. 0*1

O.S
O.S

V
V

Operating Temperature Range

TA

0

70*2

25

°c

Note: *1 The device will withstand undershoots to the -2.0V level with a maximum
pulse width of 20ns at the -1.5V level.
*2 Maximum ambient temperature is permissible under certain conditions.

DC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted)
Parameter (conditions)
OPERATING CURRENT*
Supply Current
(RAS, CAS cyclingjtRC=min.)

Symbol
MB85237-10

A~ag~ower

STANDBY CURRENT
Current
(RAS = CAS = VIR)

MB85237-12

CMOS level

MB85237-12

STATIC COLUMN MODE CURRENT
MB85237-10
Average P~r Supply Current
(RAS=VIL, CAS=cycling, tsC=min) MBS5237-12
REFRESH CURRENT 2
Average Powe~upply Current
(CAS-before-RAS; tRC=min)

Unit
mA

IS
mA

ICC2

9
495
mA

ICC3

405
270
mA

ICC4

207

MB85237-10
MBS5237-12

Max

450

MBS5237-10

A~age Po~

Value
Typ

540
ICCI

TIL level

P~r S~ly

REFRESH CURRENT 1
Supply Current
(CAS=VIR, RAS=min cycling)

Min

495
mA

ICC5

405

INPUT LEAKAGE CURRENT, all inputs

IILl

-30

30

J.lA

INPUT LEAKAGE CURRENT, CASS and DS

IIL2

-10

10

J.lA

OUTPUT LEAKAGE CURRENT

10L

-10

10

J.lA

OUTPUT HIGH LEVEL (IOR=-5mA)

VOR

2.4

OUTPUT LOW LEVEL (IOL=4.2mA)

VOL

V
0.4

V

Note: * ICC is dependent on output loading and cycle rates. Specified values are
obtained with the output open.

5-57

MB85237-10
MB85237-12

AC CHARACTERISTICS
(At recommended operating conditions unless otherwise noted.)
Parameter

NOTES

Time Between Refresh
Random Read/Write Cycle Time

Notes 1, 2, 3

t:REF
t:RC

MBS5237-10
Min
Max
S.2
180

MBS5237-12
Min
Max
8.2
210

t:RWC

210

245

Symbol

Unit
ms
ns

4
Read-Modify-Write Cycle Time
21
5 6
5

Access Time from RAS
Access Time from CAS
Access Time from Column
Address
5 7
Output Data Hold Time
Output Buffer Turn On Delay
Time
Output Buffer Turn Off Delay
Time
8
Input Transition Time
RAS Pre charge Time
RAS Pulse Width
RAS Hold Time
CAS to RAS Pre charge Time
RAS to CAS Delay Time
9 10
CAS Pulse Width
CAS Hold Time
CAS Precharge Time
(CAS-before-RAS Refresh)
Row Address Setup Time
Row Address Hold Time
Column Address Setup Time
11
Column Address Hold Time
RAS to Column Address Delay
Time
12
Column Address to RAS Lead
Time
Read Command Setup Time
Read Command Hold Time
Referenced to RAS
13
Read Command Hold Time
Referenced to CAS
13
Write Command Hold Time
WE Pulse Width
Write Command to RAS Lead
Time
Write Command to CAS Lead
Time
DIN Setup Time
DIN Hold Time
RAS to WE Delay Time
14 21
CAS to WE Delay Time
14 21
Column Address to WE delay
14 21
Time

5-58

t:RAC
t:CAC
ToM
ToOH
t:ON

100
30
50

120
35
60
7
5

7
5

ToOFF

ns

25

ns
ns
ns
ns
ns

25

ns

50

ns
ns
ns
ns
ns
ns
ns
ns
ns

t:T
"RP
"RAS
ToRSH
ToCRP
ToRCD
t:CAS
ToCSH
ToCPN

3
70
100
30
0
25
30
100
15

t:ASR
t:RAH
"ASC
"CAH
"RAD

0
15
0
15
20

ToRAL

50

60

ns

t:RCS
t:RRH

0
0

0
0

ns
ns

ToRCH

0

0

ns

t:WCH
"WP
"RWL

15
15
25

20
20
30

ns
ns
ns

ToCWL

20

25

ns

lODS
"DH
t:RWD
t:CWD
"AWD

0
20
100
30
50

0
25
120
35
60

ns
ns
ns
ns
ns

50
100000
70

50

3
SO
120
35
0
25
35
120
15
0
15
0
20
20

100000
85

60

ns
ns
ns
ns
ns

n~~~mm ~I I I I ~I~ ~ I ~
FUJITSU
mlllll~I~~~~I~111111111111111

MB85237-10
MB85237-12

AC CHARACTERISTICS

(Cont'd)
Notes 1, 2, 3

(At recommended operating conditions unless otherwise noted.)
Parameter

NOTES

RAS Precharge Time to CAS
Active Time (Refresh Cycles)
CAS Setup Time for CAS-be foreRAS Refresh
CAS Hold Time for CAS-beforeRAS Refresh
Static Column Mode Read/Write
4
Cycle Time
Static Colu= Mode CAS Precharge
Time
Static Column Mode Read-ModifyWrite Cycle Time
21
Access Time from Last Write 5 15
Access Time from WE Precharge
5
Output Hold Time from Column
Address Change
Write Latched Data Hold Time
16
Colu= Address Hold Time
Referenced to RAS
Last Write to Colu= Address
17 18
Delay Time
Column Address Hold Time
Referenced to Last Write
RAS to Second Write Delay Time
WE Inactive time
WE Setup Time for Output
Disable
19
WE Hold Time for Output
Disable
19
WE Setup Time for Output
20,21
Disable
WE Hold Time for Output
20 21
Disable

t:RPC

MB85237-10
Min
Max
0

MB85237-12
Min
Max
0

"CSR

0

0

ns

t:CHR

15

20

ns

t:SC

55

65

ns

tcp

15

15

ns

t:SRWC

95

115

ns

Symbol

tALW
tWPA

110
35

90
30

Unit
ns

ns
ns

"AOH

10

10

ns

t:WOH
t:AHR

0
15

0
15

ns
ns

t:LWAD

25

t:AHLW

95

120

ns

tRSWD
t:WI
t:WS

100
15
0

100
20
0

ns
ns
ns

tWH

0

0

ns

t:WS

0

0

ns

t:WH

0

0

ns

40

30

50

ns

5-59

MB85237-10
MB85237-12

AC CHARACTERISTICS

(Cont'd)

tIlTES;

1. An initial pause (RAS=CAS/CAS 8=V IH ) of 200 l.ls is required after power-up followed by any 8 ill-only
cycles before proper device operation is achieved. In case of using internal refresh counter, a lIinllIum of 8 CAs-before-RAS Initialization cycles instead of 8 RAS cycles are required.
2. AC characteristics assulle tT=5ns
3. VIH (.in) and VIL (.ax) are reference levels for _easuring ti_Ing of Input signals.
times are lIeasured between VIH (lIin) and VIL (IIax).

Also, transition

q. The II i n ilium cyc 1e t i lIIe depends upon the amb i ent temperature and coo 1 i ng cond i t I on. See Fig. 2 and 3.
5. Measured with a load equivalent to two TTL loads and 100 pF.
6. Assumes that tRCD ~ tRCD (max) and tRAD ~ tRAD (max). If tRCD and/or tRAD Is greater than the maximum
recommended value shown in this table, tRAC wi 11 be increased by the amount that tRCD (or t RAD )
exceeds the value shown. Refer to Fig. 3 and 4.
7. If tRAD

~

tRAD (max), access time Is t AA ·

8. tOFF is specified that output buffer changes to high Illpedance state.
9. Operation within the t RCD (max) 1 illit insures that tRAC ( .. ax) can be IIet. t RCD (max) is specified as
a reference point only; if t RCD Is greater than the specified t RCD (max) 1 imit, access time is controlled exclusively by tCAC. Refer to Fig. 5.
10. t RCD (lIIin) = tRAH (min) + 2tT + t ASC (min).
11. Assumes that write cycle only.
12. Operation within the tRAD (max) limit insures that tRAC (.ax) can be met. tRAD (max) Is specified as
a reference point only; If tRAD is greater than the specified tRAD (max) limit, access time is controlled exclusively by t AA . Refer to Fig. 6.
13. Either tRRH or t RCH must be satisfied for a read cycle.
14. t RWD ' tcWD' tAWD' and tws are specified as a reference point only. If tws ~ tws (1IIn), the cycle
entire cycle. If t RWD ~ t RWD (min), tCWD ~ tCWD (lIin), and tAWD ~ tAWD (min), the cycle Is a readmodify-write cycle and data from the selected cell will appear at the output pins.
If neither of the above conditions Is satisfied, the cycle Is a delayed write cycle and Invalid data
will appear at the output pins, and write operation can be executed by satlsflng t RWL ' tCWl' and tRAL
specifications.
15. Assumes tha tLWAD ~ t LWAD (.ax). If t LWAD Is greater than the .axi"u", recolI"ended value, tALW will be
increa.sed by the amount of the tLWAD exceeds the value shown. Refer to Fig. 7.
16. tAHR is specified to latch column address by the rising edge of RAS.
17. Operation within tLWAD (max) I h,it insures that tALW (_ax) can be .et. tLWAD (.ax) is specified as
a refrence point only; if tLWAD is greater than the specified tLWAD (.ax) Ii_it, then access time is
controlled by tAA.
18. t LWAD (lIin)

= tCAH (min)

+ tT·

19. Both tws (min) and tWH (.in) IIUSt be satisfied for a write cycle to avoid output confl iction.
20. tws' tWH and tRWD are specified as a reference point only. If tws ~ tws (lIin) and tWH ~ tWH(min),
the data output pin will rellain Hlgh-Z state through entire cycle. If tRWD ~ tRWD (lIin), the data
output will conta i n data read from the se 1ected ce 11.
21. For parify bit only.

5-60

MB85237-10
MB85237-12

Fig.3 - DERATING CURVE (Normal Cycle)

T.B.D.

Fig.4 - DERATING CURVE (Static Column Mode Cycle)

T.B.D.

Fig.5 - tRAC vs tRCD

160

160

,~

140

~ 120

«
5'00

Fig.6 - tRAC vs tRAD

120ns Version

1.40

120J
I

lOOns Version

lOOns Versio~

I I

80

II :I

I
I

T

I
!

I

,

20

40

60

I

I,

I

,

80 100 120

tRco ln "

T

I

,

20

40

I I
Ir II

60

Fig.7 - tALW vs tLWAD

160
140

.s

120

, 20ns Version

iI:

j.

100

-I

10~er~ion

80

T

/

I
I

I
I
I

I

!I

20

40

I
I
I

I
I

I
I

I

60

I I

I

I

80 100 120

tLwAO(ns)

5-61

1I1~1~~~~!llm~!~~
FUJ ITSU

MB85237-10
MB85237-12

111~~II~n!~~III~~~1

Read Cycle
VIM

~------------------t~----------------~
.It------i

_----,L I-------t...------------...,

VIL -

Via -

..M=~~l----

_~~~~I:=::;;:t

~--tc.s------i

VIL -

'--I--'-----:-----I....L,--:--;-----.,
COLUMN

1

~

VIH-~~I
. ~I

VIL-

000 to DO?
and aS

I

I.

~tcAC
I.Ae'-'_1AA_ _...,

VOM- _ _ _ _ _ HIGH.Z: _ _ _~~.
_ _-L.

,---------i

VIL-

ADDRESSES

00 0 to DO?
and Os
(Input)

000 to DO?
and aS

VO.VOL _ - - - - - - - - H I G H . Z - - - - - - - - - - - - - - - - - - - - - - - - - -

(Output)

~ Don't ear.

5-62

11~~~~~m~ml~111111
FUJITSU
11~~II~~ii~I~~II~~~~~

MB85237-10
MB85237-12

Static Column Mode Read Cycle

RAs

V,H V,L -

OO/CASB

VIH V,L -

.______

~--------------------tK:--------------------~
~~-----------------t~I------------------

AOORESSES

WE

000 1000 7
and 08
(OUlpUI)

VOM-

VOL_

- - - - - H I GH-Z---r

5-65

1I~~~~~m~I~~~~II~11
FUJITSU
1!~~~~~lliil~~II~I~~11

MB85237-10
MB85237-12

CAS-before-RAS Refresh Cycle
NOTE

;

Address, WE, 0, OQ(Input)=oon't

care

tRe
-tartRA'

VIH-

RAS

CAS/CAS8

--tf: 1{'"-

V'L-

VIH-

VIL-

000 to DO,
andOs
(Output)

V.H
VUL

y

i':I

~t'K~

~tc.. }

kn

"~$

HIGH·Z

o

Don't Car.

Hidden Refresh Cycle
! - - - - - - tRC: - - - - - - ! - - -__ t R C - - - - - - - - - i

V I H - - - - - , L f - - - - t l U s , - - - . , b - - - : : > l . . I - - - - t l U . - - - - i +-

....

VIL-

V,H _---±--:-:----';h
VIL-

ADDRESSES

II

\~------~------00 0 to DO,
and as
(Output)

VOH -

VOL _ - - - H I G H . Z - - - - < l

VALID DATA

~ Con'tear.

5-66

MB85237-10
MB85237-12

DESCRIPTION
Block Analysis:
As shown in Fig. 1 and Fig. 2, the MBS5237 is composed of nine MBSlCl002, and the
memory selection of the each MBSlCl002 consists of a l024-by-1024 cell matrix.
Operational modes of the device are shown in the FUNCTIONAL TRUTH TABLE below.
Address Inputs:
A total of twenty binary input address bits are required to decode any 9-bit of the
9,437,1S4 storage cells within the MBS5237. Ten row address bits are established on
the ,address input pins(AO to A9) and latched with the Row Addr~ Strobe, RAS. All
row addresses must be stable on or before the falling edge of RAS. Since the flow
through type address latches are used, address information at address pins are automatically latched as column address after tRAH(min) + tT. If tRAD ~ tRAD(max) , access
time is tCAC or tAA' whichever occurs later. In cas~f~ite mode, all column addresses are latched with the Column~dress Strobe, CAS/CASS, and must be stable on
or before the falling edge of CAS/CASSo
Write Enable:
Read or Write mode is selected with the WE inputs.
and low selects write mode.
Data Input/Output:
1. Data Input;
In write cycle, the
through each DQ and
edge of CAS/CASS or
input is strobed by

A high on WE selects read cycle

9-bit data is written into the MBS5237 during write cycle
D pin. Each input data is strobed and latched by later falling
WE. In case of early write(CAS control 1 write) cycle, data
CAS/CASS, and setup and hold times are referenced to CAS/CASSo

2. Data Output;
The output buffers on each chip are three state TTL compatible with a fan out of
2 TTL loads. Output data has the same porality as input data. The outputs are in
high impedance state until CAS and CASS are brought low~n a read cycle, the output becomes valid within tRAC from the falling edge of RAS when tRCD(max) is satisfied. In the meanwhile when either tRCD or tRAD, or both, are equal or greater
than their maximum value, the output dat~ecomes valid within tCAC or tAA whichever o~rs later after falling edge of CAS/CASSo The data output remains valid
until CAS and CASS return to high.
Read Cycle:
The read cycle is executed by the falling edge of both RAS and CAS/CASS, applying
column addresses, and keeping WE to high throughout the cycle. The row address are
latched with RAS. The valid data will appear at the DQ and Q ~s af~ determined by
RAS(tRAC), CAS(tCAC), or Column address input(tAA). If tRCD (RAS to CAS delay time)
is greater than the specification, the access time is tCAC. If tRAD is greater than
the ~cification, the access time is tAA. The output data becomes invalid after
CAS/CASS is brought high, with a delay time of tOR, and the DQ and Q pins return to
the high impedance with tOR. During this cycle, all column addresses must be held
before RAS is brought high with tAHR.
Write Cycle:
The write cycle is executed by almost same manner as read cycle. The column addresses
are latched with falling edge of CAS/CASSo The 9-bit data on DQ and D pins are also
latched with the falling edge of CAS/CASS and are written into memory. In addition,
during write cycle, tRWL' tCWL, and tRAL must be satisfied the specifications.

5-67

MB85237-10
MB85237-12

DESCRIPTION

(Continued)

Static Column Mode Read Cycle:
The static column mode read cycle is executed after normal cycle with holding RAS
low, applying column address and CAS/CASS, and keeping WE high. Since the row address
during static column mode cycle is latched by normal cycle, the cycle time is reduced.
During this mode, the access time is determined by tCAC' or tAA, whichever occur
later. Any of the 1024 bits' belonging to each internal row address can be accessed.
Static Column Mode Write Cycle:
The static column mode write cycle is executed by the same manner as static column
mod~ read cycle except for the state of WE. The data on each DQ and D are latched
with the falling edge of CAS/CASS and written into the memory. During this write
cycle, tws and tWI must be satisfied. Any of 1024 bits belonging to each internal
row address can be accessed.
Read-Modify-Write Cycle:
The read-modify-write cycle is permitted on parity chip, and is executed by changing
WE high to low after the output data appears the Q pin. The input data on D pin is
written into the same address as read out.
Static Column Mode Read-Modify-Write Cycle:
The static col~ mode read-modifr:write cycle is also permitted on parity chip, and
is executed by WE low pulse. The WE must be brought low after tRWD, tCWD, and tAWD
to strobe output data.
Refresh:
The refresh of DRAM is executed by normal read and write cycle, i.e., the cells on
each one row line, AO through AS except for Ag, are refreshed by one of two cycles.
Each 512 row address must be refreshed every S.2ms period. During the refresh cycle,
the cell data connected to the selected row are sent to sense amplifier and re-write
to the cell. The MBS5237 also has three types of refresh modes below.
1. RAS-only Refresh;
The RAS-only refresh is executed by keeping RAS low, and CAS/CASS remains high
through the cycle. The row address to be refreshed is latched with the falling
edge of RAS. During this refresh, the data pins are kept high impedance state.
2. CAS-before-RAS Refresh;
The CAS-before-RAS refresh is executed by bringi~CAS/CASS~w before RAS brought
low. By this combination, the MBS5237 executes CAS-before-RAS refresh. The row
address input is not necessary because it is generated internally.
3. Hidden Refresh;
The hidden refresh is executed by keeping CAS/CASS low to next cycle during read
mode, i.e.L-!he ou~t data at previous cycle is kept during next refresh cycle.
Since the CAS and CASS a~kept low~ntinuously from previous cycle, followed
refresh cycle should be CAS-before-RAS refresh.

5-68

1~~m~!II~~~~!~~!i

FUJ ITSU

Ii~m~~~~~ml!!ii

MB85237-10
MB85237-12

FUNCTIONAL TRUTH TABLE
Address Input

Clock Input

Operation
Mode

RAS

CAS(S)

WE

Row

Standby

VIR

VIR

X

X

Read
(Normal)

VIL

VIL

VIR

Valid

VIL

VIL

VIH

Valid

VIL

VIL

VIL

VIL

VIL

RAS-only
Refresh

VIL

CAS-beforeRAS Refresh
Hidden
Refresh

Read
Static Column)
Write
(Normal)
Write
Static Coulmn)

Column

Data
I/O

Note

Righ-Z

Cells are not refreshed.

Valid

Output
Valid

tRCS
tRCR

Valid

Output
Valid

tRCS ~ tRCS (min)
Cells are not refreshed.

Valid Valid

Input
Valid

tws
tWH

VIL

Valid

Input
Valid

tws ~ tws (min)
Cells are not refreshed.

VIR

X

Valid

VIL

VIL

X

VIL

VIL

VIH

*

X

Valid

tRCS (min)
tRCR (min)

~
~

~
~

tws (min)
tWH (min)

X

Righ-Z

X

X

Righ-Z

tCSR

X

X

Output
Valid

Previous data is kept.

~

tCSR (min)

Note: X Either VIR or VIL'
* RAS puts VIR at once.

5-69

I!i~ill~i!~~~~~~~i!
FUJ ITSU

!~~lli~~!!~~i~~~II!!

MB85237-10
MB85237-12

PACKAGE DIMENSIONS
(Suffix: PJPS)

30·LEAD PLASTIC SINGLE IN·L1NE TYPE MODULE
(CASE No.: MSP·30P·P04)

3.125'.010
179.38'0.251

-I

• I'
t

~==~~~F=~~~~==-W~O~~=O~r=~~=O~~

.20015.081

MAX

.830121.081

MAX

.13<:m

.100'.010
12.54'0.251

13.40~g:;~1
2.900173.66IREF

L~
G5011.271
REF
01989 FUJITSU LIMITED 113001"2S·2<:

5-70

Dimension in
inches (millimeters)

~~I~~IIIII~~IIIIIII~~II~~I1~
FUJ ITSU

IIIIIIIIIIIII~II~IIIIIIIIIIIIIIIIIII

MB85237-10
MB85237-12

PACKAGE DIMENSIONS
(Suffix: PJPB)

30-PAD PLASTIC SINGLE IN-liNE TYPE MODULE
(CASE No.: MSS-30P-P03)

r------ _._________--;3""5""0~0±~.0_;;;10:._- _ _ _ _ _ _ _--j
(88.90±0.251

+0.15

(1.27-0.081

Dimension in
inches (millimeters)

01989 FUJITSU LIMITED M30011S·3C

5-71

CMOS DRAMs

5-72

Dynamic RAM Data Book

11111111111111111111111111111111111111111111111111111111111111111

'262144X9 BIT DYNAMIC
ACCESS
MEMORY MODULE

FUJITSU "'IRIJIII~
RANDOM

MB85240-10
MB85240-12

11111111111111111111111111111111111111111111111111111111111111111

December 1987
Edition 1.0

262,144 x 9 BIT CMOS STATIC COLUMN
RANDOM ACCESS MEMORY
This Fujitsu MB85240 is a fully decoded, 262,144 words x 9 bits CMOS
static column random access memory composed of nine 256k SCRAM chips
(MB81C258x9). This module is designed for high speed, high performance
applications such as main frame memory, buffer memory, and video memory,
and for applications to battery backed-up systems where very low power
dissipation and compact layout is required. The electrical characteristics of the
MB85240 are quite same as the original MB81 C258; each timing requirements
are noncritical, and power supply tolerance is very wide. All inputs and outputs
are TTL compatible.
•
•

•

•

•

•

•
•
•

262,144 x 9 SCRAM MODU LE, 3D-pin SIP and socket type
Row Access Time (tRAd
100 ns max. (MB85240-10)
120 ns max. (MB85240-12)
Random Cycle Time (tAd
200 ns min. (MB85240-10)
230 ns min. (MB85240-12)
Address Access Time (t AA)
45 ns max. (MB85240-10)
55 ns max. IMB85240-12)
Static Mode Cycle Time (tse)
50 ns min. (MB85240-10)
60 ns min. (MB85240-12)
Low Power Dissipation
2970 mW max. IMB85240-10}
2475 mW max. IMB85240-12)
99 mW max. standby with TTL level input
15 mW max. standby with CMOS level input
+5V supply, ±10% tolerance
32ms/256 refresh cycles capability
RAS-only, CAS-before-RAS and Hidden refresh capability

PLASTIC PACKAGE
MSP-30P-P02

PLASTIC PACKAGE
MSS-30P-POI

PIN ASSIGNMENT

----'()
Vee
CAS
DOo
Ao
A,
DQ,
A,
A3

Vss
DQ,
A.
As
DQ3
A6
A,
DQ.
A,
NC
NC
DQs

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating

Symbol

Value

Unit

VIN' VOUT

-1.0 to +7.0

V

Vee

-1.0 to +7.0

V

.~1

TSTG

-55 to 125

°c

:g~S8

Power dissipation

Po

9.0

W

Short circuit output current

-

50

mA

Voltage on any pin relative to Vss
Voltage on Vee supply relative to Vss
Storage temperature

WE
Vss
DO.
NC

RAS

Vee

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data
sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

.

1

D
D
D
"
D
D
D
D
D
D0
2
3

•5

6
7
8
9
10

12
13
1.
15
16
17

18
19
20

21
22
23
2.
25
26
27
28
29
30

For parity bit .

This device contains circuitry to protect the
inputs against damage due to high static voltages or electric fields. However, it is advised
that normal

precautions be taken to avoid

application of any voltage higher than maximum rated voltages to this high impedance
circuit.

5-73

Illmlllll~lllmm~mllllllllllllllllll~11111
FUJITSU MB85240-10
1IIIIIIIIIIIIIIIIIIIIml~lllllllmlmllllll~111 MB85240-12

Fig. 1 - FUNCTIONAL BLOCK DIAGRAM

Fig. 2 - BLOCK DIAGRAM FOR EACH CHIP

'RAS-----i

cAs

Ao
A,

D'N

A,
A,

A.
DOUT

A,
A.

CAPACITANCE ITA

Z

Parameter

Max

Unit

C IN1

80

pF

Input Capacitance, RAS

C IN2

88

pF

Input Capacitance, CAS

C IN3

70

pF

Input Capacitance, WE

C IN4

49

pF

Input Capacitance, CASs

C IN5

11

pF

Input Capacitance, Ds

C INS

7

pF

I/O Capacitance, DOo to D0 7

Coa

15

pF

Co

11

pF

Os

Symbol

Typ

Input Capacitance, Ao to As

Output Capacitance,

5-74

25°C, f = lMHz)

1111111111111111111111111111111111111111111111111111

MB85240-10
MB85240-12

FUJITSU
1111111111111111111111111111111111111111111111111111

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Parameter

Symbol

Min

Vcc

4.5

Vss

0

Input High Voltage

V,H

2.4

Input Low Voltage

V,L

-1.0

Supply Voltage

Typ

Max

Unit

5.0

5.5

V

0

0

V

-

6.5

V

-

0.8

V

Operating
Temperature

O°C to +70°C*

Note .: Ambient temperature is dependent on cycle time and cooling conditions.
See the derating curve Fig. 3 for normal cycle, and Fig. 4 for static mode cycle.

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

OPERATING/REFRESH CURRENT"
Average Power Supply Current
(RAS, CAS cycling; t RC = min)

MB85240-10

STANDBY CURRENT
Standby Power Supply Current
(RAS, CAS = V IH )

TTL Level

STATIC MODE OPERATING CURRENT*
Average Power Supply Current
(RAS = CAS = V ,L , WE or Address = cycling;
tsc = min)
CAS-BEFORE-RAS REFRESH CURRENT"
Average Power Supply Current
(RAS cycling, CAS-before-RAS refresh;
tRC = min)

Min

Max
540

mA

ICC1

450

MB85240-12

18
mA

Icc2

2.7

CMOS Level
MB85240-10

360
mA

Icc3
MB85240-12

315
495

MB85240-10

mA

ICC4
405

MB85240-12
IUL)1
(CASe, De)

-10

10

1,(L)2
(Others)

-30

30

OUTPUT LEAKAGE CURRENT
Each output is high impedance
(Data is disable, VOUT = OV to 5.5V)

IO(L)

-10

10

OUTPUT LEVELS
Output High Voltage (lOH = -5 mAl
Output Low Voltage (lOL = 4.2 mAl

VOH
VOL

2.4

INPUT LEAKAGE CURRENT, ALL INPUTS
(V IN = OV to 5.5V, Vcc = 5V, Vss = OV, all other inputs not under
test = OV)

Unit

JlA

0.4

JlA

V

Note 1): Icc is dependent on the output loading and cycle time. Output pins are open.

5-75

1111111111111111111111111111111111111111111111111111

FUJITSU
1IIIIImllllllllllllllllllllllllllllllllllllllllili

MB85240-10
MB85240-12

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted'!

ImmIIIfa
MBB5240·10

Parameter

I&iI

MB85240·12

Symbol

Unit
Min

Max

Min

Max

Time between Refresh

tREF

-

32

-

32

ms

Random ReadIWrite Cycle Time

tRc

200

-

230

-

ns

1m

tRwc

245

lUI

t RAc

-

Read·Modify·Write Cycle Time
Access Time from RAS

-

285

-

ns

100

-

120

ns

25

-

30

ns

Access Time from CAS

tcAc

Output Buffer Turn Off Delay Time

tOFF

0

25

0

25

ns

t'r

3

50

3

50

ns

tAA

-

45

-

55

ns

tAOH

5

-

5

-

ns

1m

tWPA

-

25

30

ns

.1iJ1m

tALW

-

90

-

110

ns

1m

tWOH

0

0

-

ns

Transition Time

o III

Column Address Access Time
Output Hold Time from Column Address
Change
Access Time from WE Precharge
Access Time Relative to Last Write

t RP

90

-

100

-

ns

RAS Pulse Width

tRAS

65

100000

75

100000

ns

RAS Hold Time

t RSH

25

-

30

-

ns

CAS Pulse Width (Read)

tCAs

25

100000

30

100000

ns

CAS Pulse Width (Write)

Write latched Output Hold Time
RAS Precharge Time

tCAS

15

100000

20

100000

ns

CAS Hold Time (Read)

tCSH

100

-

120

-

ns

CAS Hold Time (Write)

tCSH

80

-

95

-

ns

RAS to CAS Delay Time

tRCD

25

75

25

90

ns
ns

CAS to RAS Set Up Time

tCRS

20

-

25

Row Address Set Up Time

tASR

0

-

0

-

Row Address Hold Time

tRAH

15

-

15

-

ns

tAsc

0

-

0

-

25

-

ns

ns

ns

Column Address Set Up Time

Q

Column Address Hold Time

Q

tCAH

20

mm

tRAD

20

55

20

65

Column Address Hold Time Reference to RAS

tAR

100

-

120

-

ns

Write Address Hold Time Referenced to RAS

t AWR

80

-

90

-

ns

RAS to Column Address Delay Time

5-76

ns

1llllllmllllllmllllllllllllllllllllllllllllll~1
MB85240-10 FUJITSU
MB85240-12 I I I I I I I I I ~I I I I I I I I I I I I I I I I

AC CHARACTERISTICS (Cont'd)

(Recommended operating conditions unless otherw·se
noted) "'1~"Iif"'I!ii"'I6""
I

rmmI

Parameter

MB85240·10

MB85240·12

Symbol

Unit
Min

Max

Min

Max

tRAL

45

-

55

tAHR

15

-

15

-

ns

tLwAO

25

45

30

55

ns

Column Address Hold Time Referenced
to Last Write

tAHLW

90

-

110

-

ns

Read Command Set Up Time Referenced
to CAS

tRCS

0

-

0

-

ns

Read Address to RAS Lead Time
Column Address Hold Time Referenced
to RAS Rising Time
Last Write to Column Address
Delay Time

IIiJ

mlDlIil

ns

Read Command Hold Time Referenced
to RAS

III

tRRH

10

-

10

-

ns

Read Command Hold Time Referenced
to CAS

III

tRCH

0

-

0

-

ns

twp

15

-

20

-

ns

WE Inactive Time

tWI

15

-

20

-

ns

Write Command Hold Time

t wcH

15

-

20

ns

tRwL

25

30
30

-

120

-

ns

30

-

ns

WE Pulse Width

Write Command to RAS Lead Time
Write Command to CAS Lead Time
RAS to WE Delay Time
CAS to WE Delay Time

1m
1m

tcwL

25

-

III 1m
1m

tRwO

100

!cwo

25

-

1m

ns
ns

tAwo

45

-

55

tRsWO

105

-

125

-

ns

RAS to Second Write Delay Time
Write Command Hold Time Referenced
to RAS

tWCR

80

-

95

-

ns

tws

0

-

0

tWH

-

0

-

ns

0

DIN Set Up Time

tos

0

-

0

-

ns

DIN Hold Time

tOH

20

-

25

ns

DIN Hold Time Reference to RAS

tOHR

80

-

90

-

Refresh Set Up Time for CAS
Referenced to RAS
(CAS·before·RAS cycle)

tFCS

20

-

25

-

ns

Column Address to WE Delay Time

Write Set Up Time for Output Disable
Write Hold Time for Output Disable

III

...

ns

ns

ns

5-77

1IIIIIImmlmlllllllloo~lllm~lmlllllllll
FUJITSU MB85240.10
mlmi~m~ml~~OO~~~lm~l~ml MB85240·12

AC CHARACTERISTICS (Cont'd)

(Recommended operating conditions unless otherwise noted) I~rifl!ilfl
Parameter

IIIiD!iI

MBB5240·10

Unit
Min

Max

Min

Max

Refresh Hold Time for CAS
Referenced to RAS
(CAS·before·RAS cycle)

tFCH

20

-

25

-

ns

CAS Prechar~me
(CAS·before·RAS cycle)

tCPA

20

-

25

-

ns

RAS Precharge Time to CAS
Active Time (Refresh cycles)

tAPC

20

-

20

-

ns

Static Mode Read/Write Cycle Time

lSc

50

60

95

tcp

15

-

ns

lSAWC

-

Static Mode Read·Modify·Write Cycle Time

1m

Static Mode CAS Precharge Time

NOTES:

D An

Initial pause (RAS = CAS = V 1H ) of 200 JJ.S is reo
quired after power·up followed by any a RAS·only
cycles before proper device operation is achieved. In
case of using internal refresh counter, a minimum of
CAS·before·RAS initialization cycles instead of RAS
cycles are required.
AC characteristics assume tT = 5ns, V 1N = OV to 3V,
V 1H =2.4V, V 1L =
VOH =2.4V, and VOL =O.4V.
Assumes that tAAD :0;; tAAD (max). If tAAD is greater
than the maximum recommended vaille shown in this
table, tRAC will be increased by the amount that tRAD
exceeds the value shown.
Assumes that tRAD ~ tAAD (max).
Measured with a load equivalent to 2 TTL loads and
100pF.
Assumes that tLWAD :0;; tLWAD (max). If tLWAD is
greater than the maximum recommended value shown in
this table, tALW will be increased by the amount that
tLWAD exceeds the value shown.
Write Cycle Only.

a

III
IJ

II

m
Ii)

Ii

5-78

MBB5240·12

Symbol

a

o.av,

mOperation

115
20

ns
ns

within the tRAD (max) limit insures that
tRAC (max) can be met. tRAD (max) is specified as a
reference point only; if tRAD is greater than the speci·
fied tRAD (max) limit, then access time is controlled by
t AA ·
tRAS (min) =tRAH (min) + tT (tT =5ns)
1m tAH R is specified to latch column address by the rising
edge of RAS.
Operation within the tLWAD (max) limit insures that
tALW (max) can be met. tLWAD (max) is specified as a
reference point only; if tLWAD is greater than the speci·
fied tLWAD (max) limit, then access time is controlled
by t AA .
III tLWAD (min) = tAHW (min) + tT (tT = 5ns)
III Either tRRH or tRCH must be satisfied for a read cycle.
IEl tws, tWH, and tRWD are specified as a reference point
only. If tws ~ tws (min) and tWH ~ tWH (min), the
data output pin will remain High·Z state throughout
entire cycle. It tRWD ~ tRwD (min). The data output
will contain data read from the selected cell.
Parity bit only.

m

m

iii!

~1~~~~mi~I~~~I~i.i
MBB5240-10 FUJITSU
MB85240-12 ~I~~I~.III

Read Cycle
tAC
tAAS

~
~

ADDRESSES

V1H1L -

V

~

_tAP_

tCSH
-tAcO

..

tCA

~

ROW

COLUMN
!t-=t ACS

tACH

-

I---=:!f"-

t A AH

I--tOFF

VOH----------HGH-Z-------t:~!gl§~)_---HI G
VOL
H-Z---

(Output)

•. If

-tAHA

tAAL

-c=.tCACtAA
tAAC

DCloOs
to D07
and

-

tAA

tRAO*

-

~

tASH

Ell Don't Car•

tAAO ~ tA AO (max). access time is tAA

Write Cycle (CAS Controlled)

V
V

DOo to D07

andDs
(Input)

DClo to D07
and Os

1H- - - - - - - i l
1LI'f-----------------.;f/

V,H-IIIIIIIIIIIIIIIIII~~~~::~II~~II!lIiIlIlIlIlIlIi~1I1I1II
V1L-lii
VOH-__________
HIGH-Z·,-----------------VOL

(Output)

•. If

•

Don't ear•

tws ~ tws (min) and tWH ~ tWH (min), DouT is high-Z.

5-79

~oo~m~~oomm~lml~m~~~~i~1
FUJITSU MBIS240.10
Imn~~~I~~~~m~~II~~~~i~~ MBIS 240·12

Read·Modify·Write Cycle
(Note; Only for parity bit.)
r--------------------tRWC----------------------~
~--------------tRAS------~------~

RAS

V 1H _
VIL -

CAS8

VIHVIL-

-,

08

------HIGH.Z-----t=~V~A~L~I~U==t:}---HIGH.Z:----

•. Invalid Data
Static Mode Read Cycle

It~===============;;:;=tRiC-----------------------~
tRASi------------------~
V1H_----..J1

I'---------......(\----------'fl

V 1L-

V1HV1L-

"...,....,....,.""*-+!---il
t}---+---\
:.0'. . . . . . . . .. . . . "

0 00 to DQ7 VOH-

andOe
(Output)

--VOL

III Don't Care
valid Data.

5-80

111111~mllllllllmllllllllllml~~mlm~~
MB85240-10 FUJITSU
MB85240-12 111~1~~~lm~~~lml~~~~mll~~~~~

Static Mode Write Cycle

~----------------------tRC:------------------------3-~

1~~----------------tRAS'-------------------~~t

RAS

~:~:::~~-~I--tRSH;tRP
V 1H -

----+-1+---,/.1

V 1L - _ _"';".1'

WE

V1H

------+-""\,!

V 1L-

~~---~

OQo to OQ 7 V
1Hand Os
V 1L (Input)
OQ o to DQ7
V OHand Q s
VOL
(Dutput)

*. If tws

-------------'HIGH-Z·--------------

o

Don'teara

~ tws (min) and tWH ~ tWH (min), DOUT is high-Z.

Static Mode Read-Modify-Write
(Note; Only for parity bit_)
r------------------'tAC----------------------~
~-----------------tAAS----------------~

D

Don't ear.

ISSIlnvalid Data

5-81

1~~III~~~~I~mlllml~llm~II~~~~~
FUJITSU MB85240-10
1IIIIIIIIImlllllllllllllllllll~~~lllilml~~ MB85240-12

Static Mode Mixed Cycle

-ttIR~C~==========~------1

i--------------tRAS-

teAs

ADDRESSES

DOa to D07
and Os
(Output)

Write

Read

L'::3 Don't Care
[S!J Invalid Dati
*; Only for parity bit.
RAS-Only Refresh Cycle
(Note; WE, DIN = Don't Care, As = VIH or V;L I

DOo to D07

and

Os

(Output)

=:::::::::~------~----------HIGH-Z---------------------------•

5-82

Don'tCa"

~~~~~~I~~~~I~~~IIIII~~~I~II~11
MB85240-10 FUJITSU
MB85240-12 ~~~~I~~~I~~~~~~~~~~liil

CAS-before-RAS Refresh Cycle
(Note; Address, WE, DIN

=Don't Care)

~-------------tRC:--------------~

I i------tRAs---------i I

RAS

V1HV1L-

CAS/CAS8

V1HVIL -

DOc to D07
and Os
(Output)

VOHVOL

r-------~

~--------~

HIGH-Z

f:] Don't car.

Hidden Refresh Cycle
~-----------tRC------------~

t----tRASI---'---4

CAS/CAS8

WE

VIH-~~~~~~~~-+~--------~~--~--~~~~~~~~~~
VIL -~.iI2Ii_u~~.:.II

DOctoD07VOH- __________ HGHZ _______-(===========~~~I~~~~~A~==========:)
a"dOe
VOL
I .
(Output)

f!'l Don't Care

5-83

1IIIm~m~~~lllmmllll~lmm~~~mm
FUJI'l'SU MB85240-10
Illmm~~~~lllllmllll~~~~I~~~ml MB8S 2 40 -12

FUNCTIONAL TRUTH TABLE
RAS

CAS and
CASe

WE

000 to 007 ,
De and Oe

H

H

Don't Care

High-Z

L

L

H

Valid Data Out')

Ready cycle

L

L

L

Valid Data In 2 )

Write cycle

L

L3 )

Don't Care

High-Z

CAS-before RAS Refresh cycle

L

H

Don't Care

High-Z

RAS-only Refresh cycle

L

H (CAS)
l (CASa )

Notes: 1): DO Pins are output mode.
2): DO pins are input mode.
3): tFCS;;;; tFCS (min)
4): tcwo;;;; tcwo (min)

5-84

H -+ l4)

High-Z (DOo to DQ7)
Valid Data In (Da)
Valid Data Out (Oa)

Function

Standby

RAS-only Refresh cycle
(Except for Pairyt bit)
Read-Write/Read-Modify-Write (Parity bit)

111111111111111111111111111111mlllllllllllllllll~
MB85240-10
MB85240-12

FUJITSU
1111111111111111111111111111111111111111111111111111

DESCRIPTION
Address Inputs:
A total of eighteen binary input address
bits are required to decode anyone of
the 262,144 storage cells within each
MB81C258. Nine row address bits are
established on the address input pins
(Ao to As) and latched with the Row
Address Strobe (RAS). The nine column
address bits are established on the ad·
dress input pins (Ao to As) after the
Row Address Hold Time (tRAH) has
been satisfied. In read cycle, the column
address are not latched by the Column
Address Strobe (CAS), so the column
address must be stable until the output
becomes valid. In write cycle, the
col umn address are latched by the later
falling edge of CAS or WE.
Write Enable:
Read or Write cycle is selected with the
WE inputs. A high on WE selects read
cycle and low selects write cycle. The
write operation is asserted on the later

falling edge of CAS or WE (Both CAS
and WE are low). The time period of
the write operation is determined by
internal circuit, thus next write opera·
tion will be inhibited during the write
operation.
Data Input:
Data is written into the MB85240
during write or read·modify·write cycle.
The input data is strobed and latched by
the later falling edge of CAS or WE.
Data Output:
Each output buffer is three state TTL
compatible with a fan out of two stand·
ard TTL loads. Data out has the same
porality as data in. Each output is in
high impedance state until CAS is
brought low. In a read cycle, the access
time is determined by the following
conditions:
1. tRAC from the falling edge of RAS.
2. tAA from the column address inputs.
3. tCAC from the falling edge of CAS.
When both tRCO and tRAO satisfy their
maximum limits, tRAC = tRCO + tCAC or
tRAC = tRAO + tAA'
Data outputs remain valid while the
column address inputs are kept can·
stant. However, when CAS goes high,
the output returns to high impedance
state.

Static Mode:
The static mode operation allows can·
tinuous read, write, or read·modify·
write cycle within a row by applying
new column address. In the static mode,
CAS can be kept low throughout static
mode operation. The following four
cycles are allowed in the static mode.
1. Static mode read cycle;
In a static mode read cycle, the
access time is tRAC from the falling
edge of R AS or tAA from the
column address input. The data reo
mains valid for a time tAOH after the
column address is changed.
2. Static mode write cycle;
In a static mode write cycle, the data
is written into the cell triggered by
the later falling edge of CAS or WE.
If both tws and tWH are greater than
their minimum limits, the data out·
put pin is kept high impedance state
through the static mode write cycle.
3. Static mode read·modify·write cycle;
In the static mode read·modify·write
cycle, WE goes low after tAwo from
the column address inputs and tcwo
from the falling edge of CAS. The
data and column address inputs are
strobed and latched by the falling
edge a of WE.
4. Static mode mixed cycle;
In the static mode, read, write, and
read·modify·write cycles can be
mixed in any order.
In the next read cycle of static mode
write cycle or read·modify·write cycle,
the access time is determined by the
following conditions.
1. tALW from the later falling edge of
CAS or WE at previous write cycle.
2. tAA from the column address inputs.
3. tWPA from the rising edge of WE at
the read cycle.
4. tCAC from the falling edge of CAS.
Refresh:
Refresh of dynamic memory cells is
accomplished by performing a memory
cycle at each of the 256 row addresses
(Ao to A7) at least every 32ms.
The MB85240 offers the following three
types of refresh.
1. RAS-only refresh;
The RAS-only refresh avoids any
output during refresh because each
output buffer is high impedance state

due to CAS high. Strobing of each
256 row address (Ao to A7) with
RAS will cause all bits in each row to
be refreshed. During RAS-only refresh cycle, either V IH or V IL is
permitted to As.
2. CAS·before-RAS refresh;
CAS-before·RAS refreshing available
on the MB85240 offers an alternate
refresh method. If CAS is held low
for the specified period (t FCS ) before
RAS goes low, on chip refresh control clock generator and the internal
refresh address counter are enabled,
and an internal refresh operation is
executed. After the refresh operation, the refresh address counter is
automatically incremented in pre·
paration for the next CAS-beforeRAS refresh.
3. Hidden refresh;
A hidden refresh cycle will be executed while maintaining latest valid
output datas at the DQ pins by
extending the CAS low time. For the
MB85240, a hidden refresh cycle is
CAS-before-RAS refresh. The inter·
nal refresh address counter provides
the refresh address, as in a normal
CAS-before-RAS refresh cycle.
Notice for using MB8520
The MB85240 is a SIP (Single-In-LinePackage) module which is composed of
nine MB81C258 DRAMs housed in
plastic LCC, and assembled on the
epoxy printed circuit board. Generally
the multilayer PCB board has large
wiring capacitance. This disadvantage
causes relatively noise induction be·
tween signal lines and power supply
lines (Vss or Vcc).
Furthermore, as the MB85240 is a very
high-speed memory, the timing windows
to strobe address WE and DIN signals
are very short (Approx. 10ns). Therefore, it is very sensitive even to very
sharp noise.
From the above reasons, special care
should be taken for use the MB85240.
The following notices are recommended;

5-85

11~~llllllllllllllllllllllmllmm~m~~ml
FUJITSU MB85240-10
1I~~~llllllmlllllllllllllllllllllllllllllllll~ MB85240-12

DESCRIPTION
1. Provide a externally capacitor of
approx. a few IlF each module, the
MBB5240 has the nine decoupling
capacitors (0.22 IlF on each SCRAM
0.221lF x 9).
2. Remove noise, riging, overshoot and
undershoot from the address, clocks

and DQ lines, so that the MB85240
won't latch wrong signals due to the
noise induction between signal lines
and between signal and power supply
lines.
3. Keep enough timing margin and reo
move critical timing in the board

design, to avoid the problem men·
tioned in the above item 2.
4. Provide an appropriate dumping if
necessary, to avoid excessive over·
shoot or undershoot on the TTL
input waveforms.

Fig. 3 - MB85240 DERATING CURVE

-

Air Flow

_ _ :Om/s

- - - : 1 mi.
-----:3m/s
1/tSC, Cycle Rate (MHz)

Fig. 4 - MB85240 DERATING CURVE

AirFlow

_ _ _ :Om/.
---:1m/s
- - - - - : 3m/s
1/tSC, Cycle Rate (MHz)

5-86

MB85240-10
MB85240-12

1IIIImlll~IIIIIIIII~lllllllllllllmlllmllllll
FUJITSU
1IIIm~IIIIIIIIIIIII~lllllllmllllll~1111111111

PACKAGE DIMENSIONS
30·LEAD SINGLE IN·LlNE TYPE MODULE
(CASE No.: MSP·30P·P02)

1

3.100±.015
178.74±0.381

1

.20M
OIA5 X
·081"I

·1

2.900173.66IREF

F-

.05011.27IREF

01989 FUJITSU LIMITED M300Q6S"C

Dimensions in
inches (millimeters)

5-87

IIIIIIIIIIIIIIIIIIIIIIIIIIIIII~IIIIIIIII~~IIIII~
FUJITSU
Imllllllllllllmllllllll~lllllll~mlllllmlll

MBa5240.10
MBa5240·12

PACKAGE DIMENSIONS
3D-PAD PLASTIC SINGLE IN-LINE PACKAGE MODULE
(CASE No_: MSS-3DP-PD1)
3.500±.010
(88.90±0.251
3.234±.005
(82.14±0.131
R .060(1.521

.133±.005
(3.38±0.131

REF

.200(5.081

MAX

I I

riF!ifh-----t-+~g~~1 ~
.250±.005
(6.35±0.131
.080±.005
(2.03±0.131
.300±.008
(7.62±0.201

.109(2.76lTVP
2.900±.005
(73.66±0.13 I

F'

I

tEfijjj]'ij 5ifij tEiiiiii@JlEjijjjjij fijjjjiijl5ifiiIDij ffiiiiiiij~ ~

. ---.:050~ :883
( 1.27~8:6~ I
01989 FUJITSU liMITED M30005S-5C

5-88

.110(2.791MIN

Details of "A" part··;

D

.00810.201

i

. ==.±. .:
TVP

j

Dimension in inches
(millimeters)

MBB5254-BO / -10 / -12

CMOS 512K x 40 DYNAMIC RANDOM ACCESS MEMORY MODULE

The Fujitsu MB85254 is a fully decoded, CMOS dynamic random access
memory module consists of twenty MB81C1000 devices, the MB85254
is optimized lor those applications requiring high speed, high performance,
large momory storage, and high density in ECC (Error Checking and
Correction) memory organizations.

•
•

•

•

Organization :
524,288 words x 40 bit
Memory:
MB81C1000, 20 pes
RAS Access time :
80ns max. (MB85254-80)
100ns max. (MB85254-10)
120ns max. (MB85254-12)
CAS Access time:
25ns max. (MB85254-80)
30ns max. (MB85254-10)
35ns max. (MB85254-12)
Column Address Access time :
45ns max. (MB85254-80)
SOns max. (MB85254-10)
60ns max. (MB85254-12)

• Active Power :
3.960mW max. (MB85254-80)
3.410mW max. (MB85254-10)
2.860mW max. (MB85254-12)
• Standby:
220mW max. (CMOS Level)
11 OmW max. (TTL Level)
• Single +5V supply ±1 0%
torelance
• TTL compatible I/O
• Decoupling Capacitor:
0.221lF, 20 pes
• JEDEC Standard 72-pin SIMM
Package Outline

ABSOLUTE MAXIMUM RATINGS (See NOTE.)
Rating

Symbol

Value

Unh

Supply Voltage

VCC

-1.0 to ..7.0

V

Input VoHage

VIN

-1.0 to +7.0

V

Output Voltage

VOUT

-D.5 to + 7.0

V

Short Circuit Output Current

lOUT

±SO

mA

Power Dissipation

PO

20.0

W

Storage Temperature

TSTG

-45 to +125

·C

NOTE: Permanent device damage may occur WABSOLUTE MAXIMUM RATINGES are
exceeded. Functioncal operation should be reslrictad ID the concitions as
detaned in the operationcal sections of lhis data sheet Exposure ID absolule
maximu rating conditions for exteded period may affect devise reliability.
Copyright

PLASTIC PACKAGE
MSS-72P-Pxx

0021 38 37
0023 40 39
41
VSS 42 43
IOE1 44 45
IWEt 46 47
0024 48 49
0026 50 51
0028 52 53
0030 54
VSS 56 55

0020
0022

NC

IOEO
!WEO
VCC
0025
0027
0029

::
0031 ::::
57/RASO ::::

IRAS1 58 59/CASO ::
60 61 VCC::

teAS1
0032
0034
0036
0038

NC
VSS

62 63 0033 ::
64 65 0035 ::

66

:;:;

68 67 0037 :;:;
70 69 D039 E
7271
NC

o

---oin>uiIIy
ogUIo,-. . . . . . . _01_'. __. ......
_.M._
..
nonnoI..--

be _

to __

lIfIPI....iDn

hig .... _ _!mum"" "'"- to,,", high

d ..." ......

~-.

e 1989 by FUJITSU LIMITED

5-89

MB85254-10
MB85254-12

Fig. 1 - BLOCK DIAGRAM
ADDRESS
RASO
CASO
WEO
OEO

CHIP
01

RAS1
CAS1
WE1
OE1

000-3

004-7

CHIP
02

CHIP
03

CHIP
04

CHIP
05

CHIP
06

CHIP
07

CHIP
08

CHIP
09

CHIP
12

CHIP
13

CHIP
14

CHIP
15

CHIP
16

CHIP
17

CHIP
18

CHIP
19

008-11

0012-15 0016-19 0020-23 0024-27

0028-31

0032-35 0036-39

Fig. 2 - BLOCK DIAGRAM for EACH CHIP

1'00
1'01
/U
A3

1'04
1'05
A6
A7

1'08

5-90

001004

MB85254·10
MB85254·12

PACKAGE DIMENSIONS
(Suffix: PJPBK)

DETAIL

(1.27+0.15

-o.oe I

Note: Dimensions in inches
and (milimeters)

5-91

CMOS DRAMs

5-92

Dynamic RAM Data Book

11111111111111111111111111111111111111111111

FUJITSU

MB85260-10
MB85260-12

1M x 8 DRAM MODULE

11111111111111111111111111111111111111111111

TS033-A882
Feb. 1988

1,048,576 x 8 BIT DYNAMIC RANDOM
ACCESS MEMORY MODULE
The Fujitsu MBS5260 is a fully decoded, dynamic CMOS
random access memory module with eight MBS1C1000, in
26~pin SOJ packages, and eight .22VF decoup1ing capacitor under the each memory, mounted on a low profile 30-pin SIP module. Organized as 1,04S,576 x
S-bit words, the MBS5260 PCB module is optimized for
those applications requiring high density and large
memory storage capability. The operation and electrical characteristics of the MBS5260 are the same as
the MBS1C1000 devices which feature a Fast Page mode
operation.
• 1,04S,576 x S DRAM, 30-pin SIP
• Row access time (tRAC):
100 ns max. (MBS5260-10)
120 ns max. (MBS5260-l2)
• Cycle time (tRC):
ISO ns min (MBS5260-l0)
210 ns max. (MBS5260-l2)
• Column access time (tCAC):
30 ns max. (MBS5260-l0)
35 ns max. (MBS5260-l2)
• Fast Page mode cycle time (tPC):
60 ns max. (MBS5260-10)
70 ns max. (MBS5260-12)
• Dual +5V supply, ±10% tolerance
• Low power:
Active = 2640 mW max. (MBS5260-10)
2200 mW max. (MBS5260-12)
Standby = 44 mW max. (CMOS level)
• Refresh:
- S.2 ms / 512 refresh cycle
- "RAS-only", "CAS-before-RAS" and "Hidden"
refresh capabilities
• TIL compatible inputs and outputs
• Leaded and Leadless type are available.
• JEDEC standard (30-pin SIP) pin assignment

PLASTIC PACKAGE
MSP-30P-P06

CAS
DQo
Ao
A1
DQ1
A2
A3

vss
DQ2
A4
As
DQ3
A6
A7
D~

ABSOLUTE MAXIMUM RATINGS (See Note)
Rating
Voltage on any pin relative to Vss

Symbol
VIN.VOUT

Voltage on Vee supply relative to Vss

Vee

Storage temperature

TSTG

Power dissipation

Po

Short circuit output current

-

:
:

PIN ASSIGNMENT
vcc

Value

Unit

-1 to +7
-1 to +7
-55 to 125
9.0
50

V

A8
A9
NC
~s
WE
Vss
DQ6
NC
DQ7
NC

V

ill

·C

NC
NC
VCC

W

.-----..

~

=

Production Process
Test/Inspection
Production Process
and Test/Inspection
QC Gate (Sampling)

Note:
The flow sequence may vary slightly
with individual product type.

6-5

Quality and Reliability

....

Dynamjc BAM Data Book

Section 7
Ordering Information -

At a Glance

I Page
7-3
7-3
7-3
7-4
7-4

I
IC Product Marking
IC Ordering Code (Part Number)
IC Package Codes
IC Module Ordering Code (Part Number)
IC Module Package Codes

D

7-1

Ordering Information

III

7-2

Dynamic RAM Data Book

Ordering Information

Dynamic RAM Data Book

IC Product Marking

Fujitsu Logo

Z Z - year
Note:

XX week number
Marking formats may vary, depending on the product. The country of origin appears on all finished parts.

IC Ordering Code (Part Number)

I1..
T
1
MB

XXXXX -1

P

Package Code (See Package Codes below)

Speed Designator (When applicable)

Device Type

Manufacturer Designator
MB
MBM
Note:

Identifies an IC designed and manufactured by Fujitsu that uses a Fujitsu-designated device number.
Identifies an IC designed and manufactured by Fujitsu that uses a device number designated by the industry
to be the industry standard number.
Please contact your nearest Fujitsu sales office, representative, or distributor for exact part number/order information.

II

IC Package Codes

I·..(i

.

f;;;;~;;',;.l;;f . . . i i ( )

Package Type

Package Code

.....................

:iiii·)t
Package Type

. .......................
•··•· · ••••·..../\?\'·':. ii·;· ... y
Package Code

LCC (Leadless Chip Carrier)

TV,CV

LCC (Leadless Chip Carrier)

PV

PGA (Pin Grid Army)

CR

PLCC (Leaded Chip Carrier)

PD

DIP (Side Brazed) 1

C

PGA (Pin Grid Array)

PR

DIP (CERDIPj2

Z

DIP (Dual In-line Package)

P,M

Shrink DIP

CSH

Shrink DIP

PSH

Flatpack, Metal Seal

CF

Flatpack

PF

Flatpack, Glass Seal

ZF

Single In-line, straight leads

PS

SOJ (Single Ourtine Junction)

CJ

Single in-line, zig-zag leads

PSZ,PZ

SOJ (Single Oudine Junction)

PJ

, I_____ Bmzed---,~

2

(_ide

7-3

Ordering Information

Dynamic RAM Data Book

IC Module Ordering Codes

1
MB

1
L
T

XXXXX -VV pp
Module Code (See Module Codes below)

Speed Designator (When applicable)

Device Type

Manufacturer Designator
MB
MBM

Note:

Identifies an IC designed and manufactured by Fujitsu that uses a Fujitsu-designated device number.
Identifies an IC designed and manufactured by Fujnsu that uses a device number designated by the industry
to be the industry standard number.
Please contact your nearest Fujitsu sales office, representative, or distributor for exact part number/order information.

IC Module Package Codes

Package Type
Ceramic dual leads

III

7-4

Module Code
COL

Package Type
Sin Ie in-line, leads
Single in-line, zig-zag leads
Single in-line, pads

Module Code

PL
PZ
PS

Section 8
Sales Information - At a Glance

I

Page

8--3
8--7
8--8
IHl
8-11
8-11
8-11
8-12
8-16
8-17
8--18
8-20
8-20
8-21

Introduction to Fujitsu
Integrated Circuits Corporate Headquarters - Worldwide
FMI Sales Offices for North and South America
FMI Representatives - USA
FMI Representatives - Canada
FMI Representatives - Mexico
FMI Representatives - Puerto Rico
FMI Distributors - USA
FMI Distributors-Canada
FMG Sales Offices for Europe
FMG Distributors - Europe
FMA Sales Offices for Asia and Australia
FMA Representatives - Asia and Australia
FMA Distributors - Asia and Australia

8-1

Sales Information

8-2

Dynamic RAM Data Book

Dynamic RAM Data Book

Sales Information

Introduction to Fujitsu

Fujitsu Limited

Fujitsu Limited, headquartered near Tokyo, Japan, is the largest
supplier of computers in Japan and is among the top ten
companies operating in Japan. Fujitsu is also one of the world's
largest suppliers of telecommunications equipment and
semiconductor devices.
Established in 1935 as the Communications Division spinoff of
Fuji Electric Company Limited, Fujitsu Limited, in 1985,
celebrated 50 years of service to the world through the development and manufacture of state-of-the-art products in data
processing, telecommunications and semiconductors.
Fujitsu has five plants in key industrial regions in Japan covering
all steps of semiconductor production. Five wholly-owned
Japanese subsidiaries provide additional capacity for production
of advanced semiconductor devices. Two additional facilities
operate in the U.S. and one in Europe to help meet the growing
worldwide demand for Fujitsu semiconductor products.

8-3

Dynamic RAM Data Book

Sales Information

Introduction to Fujitsu (Continued)
Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics. Inc. (FMI). with headquarters in San
Jose. California. was established in 1979 as a wholly-owned
Fujitsu Limited subsidiary for the marketing, sales. and distribution of Fujitsu integrated circuit and component products. Since
1979, FMI has grown to include one research and development
division, two marketing divisions, two manufacturing divisions
and a subsidiary. FMI offers a complete array of semiconductor
products for its customers.
The Advanced Products Division (APD) is responsible for the
complete product development cycle, from design through
operations support and worldwide marketing and sales. Products
are the result of both intemal development and external
relationships, such as joint development agreements, technology
licenses, and joint ventures. The SPARCTM RISC processor was
developed by both APD and Sun Microsystems, Inc.
In addition to designing and selling a full line of SPARC
processors and peripheral chips, APD also deSigned and is
selling the EtherStar™ LAN controller - the first VLSI device to
integrate both StarLANTM and Ethernet® protocols into one
device. The core of APD's EtherStar chip was the result of APD's
cooperative venture with Ungermann-Bass.
The Microwave and Optoelectronics Division (MOD) markets
GaAs, FETs, and FET power amplifiers, lightwave and microwave devices, optical devices, emitters, and SI transistors.
The largest FMI marketing division is the Integrated Circuits
Division (ICD).
Memory and programmable devices marketed by ICD include the
following:
DRAMs and DRAM Modules
EPROMs
EEPROMs
NOV RAMs
CMOS masked ROMs
CMOS SRAMs and CMOS SRAM Modules
BiCMOS SRAMs
Bipolar PROMs
ECLRAMs
STRAMs (self-timed RAM)
Hi-Rei PROMs and SRAMs
Ultra High-speed ECUECL-TTL Translator Circuits
Linear ICs and Transistors

8-4

Dynamic RAM Data Book

Sales Information

Introduction to Fujitsu (Continued)
ASIC products offered by ICD include the following:
CMOS, ECl, and BICMOS gate arrays
CMOS standard cells
Design Software Support
Customer support and customer training for ASIC products are
available through the following FMI design centers:
San Jose
Dallas
Atlanta

Gresham
Chicago
Boston

Microcomputer and communications products offered by ICD
include the following:
4-bit MCUs
8- and 16-bit MPUs
SCSI and controllers
DSPs
Prescalers
Plls
Memory Cards
FMl's manufacturing divisions are in San Diego, California and
Gresham, Oregon. The San Diego Manufacturing Division
assembles and tests memory devices. In 1988, the Gresham
Manufacturing Division began manufacturing ASIC products and
DRAM memories. This facility, when completed, will have one
million square feet of manufacturing-the largest Fujitsu
manufacturing plant outside Japan.
FMl's subsidiary, FujHsu Components of America, markets
connectors, keyboards, plasma displays, relays, and hybrid ICs.

Fujitsu Mikroelektronlk GmbH (European Sales Operation)
Fujitsu Mikroelektronik GmbH (FMG) was established in June,
1980, in Frankfurt, West Germany, and is a wholly-owned
subsidiary of Fujitsu Limited, Tokyo. FMG is the sole representative of the Fujitsu Electronic Device Group in Europe. The wide
range of ICs, lSI memories, microprocessors, and ASIC
products are noted throughout Europe for design excellence and
unmatched reliability. Branch offices are located in Munich,
london, Paris, Stockholm, and Milan.

8-5

Sales Information

Dynamic RAM Data Book

Introduction to Fujitsu

(Continued)

Fujitsu Microelectronics Ireland, Ltd. (European Production Operation)

Fujitsu Microelectronics ireland, Ltd. (FME) was established in
1980, in the suburbs of Dublin, as Fujitsu's European Production
Center for integrated circuits. FME assembles DRAMs,
EPROMs, and other LSI memory products.
Fujitsu Microelectronics, Ltd. (European ASIC Design Operation)

Fujitsu Microelectronics, Ltd., Fujitsu's European VLSI Design
Center, opened in October of 1983 in Manchester, England. The
Design Center is equipped with highly sophisticated CAD
systems to ensure fast and reliable processing of input data. An
experienced staff of engineers is available to assist in all phases
of the design process.
Fujitsu Microelectronics Asia PTE Ltd. (Asian/Oceanian Sales Operation)

Fujitsu Microelectronics Asia PTE Ltd. (FMA) opened in August
1986 in Hong Kong as a wholly-owned Fujitsu subsidiary for
sales of electronic devices to Asian and Southwest Pacific
markets.

SPARC'" Is a trademark of Sun MlcrosystelTB,lnc.
EthernetR i8 a regiatered trademark of Xerox Cotporatlon.
EtherStar'lN Is a trademark of FuPl8u Microeledronk:s. Inc.
Start.AN™ Is atrademarkof AT&T.

8-6

Sales Information

Dynamic RAM Data Book

Integrated Circuits Corporate Headquarters -

Worldwide

International Corporate Headquarters
FUJITSU LIMITED
Marunouchi Headquarters
6-1, Marunouchi l-<:home
Chiyocla-ku, Tokyo 100
Japan
Tel: (03) 216-3211
Telex: 781-22833
FAX: (03) 213-7174

For integrated circuits marketing information please contact the following:
Headquarters for Japan
FUJITSU LIMITED
Integrated Circuits and Semiconductor Marketing
Furukawa 8ogo Bldg.
6-1, Marunouchi 2-<:home
Chiyocla-ku, Tokyo 100
Japan
Tel: (03) 216-3211
Telex: 781-2224361
FAX: (03) 211-3987

Headquarters for North and South America
FUJITSU MICROELECTRONICS, INC.
Integrated Circuits Division
3545 Nor1h First Street
San Jose, CA 95134-1804

USA
Tel: (408) 922-9000
Telex: 910-338-Q190
FAX: (408) 432~044

Headquarters for Europe
FUJITSU MIKROELEKTRONIK GmbH
Lyoner Strasse 44-48
Arabella Centre 9. OG
0-6000 Frankfurt 71
Federal Republic of Germany
Tel: (069) 66320
Telex: 441963
FAX: (069) 6632122

Headquarters for Asia and Australia
FUJITSU MICROELECTRONICS ASIA PTE LIMITED
06-04106-07 Plaza by the Park
No. 51 Bras Basah Road
Singapore 0719
Tel: (65) 336-1600
Telex: 55573
FAX: (65) 336-1609

8-7

Dynamic RAM Data Book

Sales Information

Fujitsu Microelectronics, Inc. (FMI) Sales Offices for
North and South America
NORTHERN CALIFORNIA

MASSACHUSETTS (Boston)

Fujitsu Microelectronics, Inc.
10600 N. De Anza Blvd.
Suite 225
Cupertino, CA 95014
Tel: (4OS) 996-1600
FAX: (4OS) 725-a746

Fujitsu Microelectronics, Inc.
75 Wells Avenue
Suite 5
Newton Center, MA 02159-3251
Tel: (617) 964-7OS0
FAX: (617) 964-a301

Suite P
Hauppauge, NY 11786-1054

SOUTHERN CALIFORNIA

MINNESOTA (Minneapolis)

OREGON (Portland)

Fujitsu Microelectronics, Inc.
Century Centre
2603 Main Street
Suite 510
Irvine, CA 92714
Tel: (714) 724-an7
FAX: (714) 724-a778

Fujitsu Microelectronics, Inc.
3460 Washington Drive
Suite 209
Eagan, MN 55122-1303
Tel: (612) 4~323
FAX: (612) 454"'{)601

5285 SW Meadows Road
Suite 222
Lake Oswego, OR 97035--9998
Tet: (503) 684-4545
FAX: (503) 684-4547

NEW JERSEY (Mt. Laurel)

TEXAS (Dallas)

Fujitsu Microelectronics, Inc.
Horizon Corporate Center
3000 Atrium Way
Suite 100
MI. Laurel, NJ OS054
Tel: (609) 727Jd700
FAX: (609) 727Jd797

Fujitsu Microelectronics, Inc.
14785 Preston Road
Suite 670
Dallas, TX 75240
Tel: (214) 233Jd394
FAX: (214) 386-7917

GEORGIA (Atlanta)
Fujitsu Microelectronics, Inc.
3500 Parkway Lane
Suite 210
Norcross, GA 30092
Tel: (404) 449-a539
FAX: (404) 441-2016

ILLINOIS (Chicago)
Fujitsu Microelectronics, Inc.
One Pierce Place
Suite 910
Itasca, IL 60143-2681
Tel: (70s) 2S0-a580
FAX: (708) 250-a591

8-8

NEW YORK (Hauppauge)
Fujitsu Microelectronics, Inc.
601 Veterans Memorial Highway

Tet: (516) 36Hl565
FAX: (516) 361-a480

Fujitsu Microelectronics, Inc.

Dynamic RAM Data Book

Sales Information

FMI Representatives -

USA

For product information, contact your nearest Representative.
Alabama

Connecticut

Indiana

The Novus Group, Inc.
2905 Westcorp Blvd.
Suite 120
Huntsville, AL 35805
Tel: (205) 53-Hl044
FAX: (205) 53-Hl186

Conntech Sales, Inc.
182 Grand Street
Suite 318
Waterbury, CT 06702
Tel: (203) 754-2823
FAX: (203) 573--{)538

Fred Dorsey & Associates
3518 Eden Place
Carmel,lN 46032
Tel: (317) 844-4842
FAX: (317) 844-4843

Arizona

Florida

Aztech Component Sales Inc.
15230 N 75th Street
Suite 1031
Scottsdale, AZ 85260
Tel: (602) 991--6300
FAX: (602) 991-0563

Samtronic Associates, Inc.
657 Maidand Avenue
Altamonte Springs, FL 32701
Tel: (407) 831-8233
FAX: (407) 831-2844

Iowa

California
Harvey King, Inc.
6393 Nancy Ridge Drive
San Diego, CA 92121
Tel: (619) 587-9300
FAX: (619) 587-0507
Infinity Sales, Inc.
4500 Campus Drive
Suite 300
Newport Beach, CA 92660
Tel: (714) 833-0300
FAX: (714) 833-0003
Norcomp
3350 Scott Blvd.,
Suite 24
Santa Clara, CA 95054
Tel: (408) 727-7707
FAX: (408) 986-1947
Norcomp
2140 Professional Drive
Suite 200
Roseville, CA 95661
Tel: (916) 782-8070
FAX: (916) 782-8073

Samtronic Associates, Inc.
1467 S. Missouri Avenue
Clearwater, FL 33516
Tel: (813) 461-4675
FAX: (813) 442-2234
Samtronic Associates, Inc.
3471 NW 55th Street
Ft. Lauderdale, FL 33309
Tel: (305) 731-2484
FAX: (305) 731-1019
Georgia
The Novus Group, Inc.
6115-A Oakbrook Pkwy
Norcross, GA 30093
Tel: (404) 263-{)32O
FAX: (404) 263-8946
Idaho
Cascade Components
2710 Sunrise Rim Road
Suite 130
Boise, ID 83705
Tel: (208) 343-9886
FAX: (208) 343-9887
illinois

Colorado
Front Range Marketing
3100 Arapahoe Road
Suite 404
Boulder, CO 80303
Tel: (303) 443-4780
FAX: (303) 447-{)371

Beta Technology
1009 Hawthorn Drive
Itasca, IL 60143
Tel: (708) 256-9586
FAX: (708) 256-9592

Electromec Sales
1500 2nd Avenue
Su~e 205
Cedar Rapids, IA 52403
Tel: (319) 362--6413
FAX: (319) 362--6535
Maryland
Arbotek Associates
102 W. Joppa Road
Towson, MD 21204
Tel: (301) 825-<1775
FAX: (301) 337-2781
Massachusetts
Mill-Bern Associates
2 Mack Road
Woburn, MA 01801
Tel: (617) 932-3311
FAX: (617) 932-{)511
Michigan
Greiner Associates, Inc.
15324 E. Jefferson Avenue
Suite 12
Grosse Point Park, MI 48230
Tel: (313) 499-{)188
FAX: (313) 499-Q665
Minnesota
Electromec Sales
1601 E Highway 13
Suite 200
Burnsville, MN 55337
Tel: (612) 894-8200
FAX: (612) 894-9352

8-9

Sales Information

Dynamic RAM Data Book

FMI Representatives - USA

(Continued)

New Jersey

North Carolina

BGR Associates
Evesham Commons
525 Route 73
Suite 100
Maritan, NJ 08053
Tel: (509) 983-1020
FAX: (609) 983-1879

The Novus Group, Inc.
1026 Commonwealth Court
Cary, NC 27511
Tel: (919) 460-7771
FAX: (919) 460-5703

Technical Marketing, Inc.
290 1 Wilcrest Drive
Suite 139
Houston, TX 77042
Tel: (713) 783-4497
FAX: (713) 783--5307

Ohio

Technical Marketing, Inc.
1315 Sam Bass Circle

Technical Applications & Marketing
91 Clinton Road
Suite 10
Fairfield, NJ 07006
Tel: (201) 575-4130
FAX: (201) 57&-4563

Spectrum ESD
3947 Ray Court Road
Morrow, OH 45152
Tel: (513) 899-3260
FAX: (513)899-3250

New York
Quality Components
3343 Harlem Road
Buffalo, NY 14225
Tel: (716) 837--5430
FAX: (716) 837-0662
Quality Components
116 Fayette Street
Manlius, NY 13104
Tel: (315) 682-8885
FAX: (315) 682-2277
Quality Components
2318 Titus Ave.
Rochester, NY 14622
Tel: (716) 342-7229
FAX: (716) 342-7227

8-10

Spectrum ESD
8925 Galloway Trail
Novelty, OH 44072
Tel: (216) 338--5226
FAX: (216) 338-3214

Oregon
L-Squarad Limited
15234 NW Greenbrier Pkwy
Beaverton, OR 97006
Tel: (503) 629-8555
FAX: (503) 645-8196

Texas
Technical Marketing, Inc.
3320 Wiley Post Road
Carrollton, TX 75006
Tel: (214) 387-3601
FAX: (214) 387-3605

Suite~

Round Rock, TX 78681
Tel: (512) 244-2291
FAX: (512) 338-1596

Washington
L-Squared Limited
105 Central Way
Suite 203
Kirkland, WA 98033
Tel: (206) 827-8555
FAX: (206) 82!Hll02

Wisconsin
Beta Technology
9401 W Beloit Street
Suite304C
Milwaukee, WI 53227
Tel: (414) 543-6609
FAX: (414) 54~288

Sales Information

Dynamic RAM Data Book

FMI Representatives - Canada, Mexico and Puerto Rico
Canada

Mexico

Puerto Rico

Pipe-Thompson Limited
5468 Dundas Street W.
Suite 206
Islington, Ontario M9B 6E3
Tel: (416) 236-2355
FAX: (416) 236-3387

Solano Electronica
Ermita 1039-10
Colonia Chapalita
Guadalajara, JAL. 45042
Tel: (36) 47-4250
FAX: (36) 473433

Semtronic Associates
Mercantil Plaza Building
Suite 816
Hato Ray, Puerto Rico 00918
Tel: (809) 761HJ700

Pipe-Thompson Limited
RR2 North Gower
Ottawa, Ontario KOZ 2TO
Tel: (613) 258-4067
FAX: (613) 258-7649

Solano Electronica.
Thiers 100
Colonia Anzures
Mexico City, D.F. 11590
Tel: (55) 31-5915
FAX: (55) 31-5915

8-11

Sales Information

FMI Distributors Alabama
Marshall Industries
3313 S. Memorial Highway
Suite 121
Huntsville, AL 35801
(205) 881-9235
Repton Electronics
4950 Corporate Drive
Suite 105C
Huntsville, AL 35805
(205) 722-9565

Arizona
Insight Electronics
1515 W. University Drive
Suite 103
Tempe, AZ 85281
(602) 829--1800
Sterling Electronics
3501 E. Broadway Road
Phoeniz, AZ 85040
(602) 268-2121
Marshall Industries
9830 S. 51 st Street
Suite B121
Phoenix, AZ 85044
(602) 496--0290

California

Dvnamic RAM Data Book

USA
Marshall Industries
One Morgan
Irvine, CA 9271S
(714) 458-530S
Marshall Industries
336 Los Coches Street
Milpitas, CA 95035
(4OS) 942-4600
Marshall Industries
3039 Kilgore Ave.
Rancho Cordova, CA 95670
(916) 635-S700
Marshall Industries
10105 Carroll Canyon Road
San Diego, CA 92131
(619) 578--9600
Merit Electronics
2070 Ringwood Avenue
San Jose, CA 95131
(40S) 434-0800
Sterling Electronics
55310 Derry
UnitX
Agoura, CA 91301
(81S) 707...()911
Sterling Electronics
9410 Topanga Canyon Rd.
Chatsworth, CA 91311
(SI8) 407--9850

Insight Electronics
28035 Dorothy Drive
Suite 220
Agoura, CA 91301
(818) 707-2100

Sterling Electronics
1342 Bell Avenue
Tustin, CA 92680
(714) 259-0900

Insight Electronics
15835 Alton Parkway
Suite 120
Irvine, CA 92718

Western Microtechnology
28720 Roadside Dr.
Suite 175
Agoura Hills, CA 91301
(SIS) 356--0180

(714)727~111

Insight Electronics
6885 Flanders Drive
Suite G
San Diego, CA 92126
(619) 587-9757
Marshall Industries
9710 Desoto Ave.
Chatsworth, CA 91311
(818) 407-4100
Marshall Industries
9674 Telstar Ave.
EI Monte, CA 91731
(818) 459--5500

8-12

Western Microtechnology
1637 North Brian
Orange, CA 92667
(714) 637-0200
Western Microtechnology
6837 Nancy Ridge Drive
San Diego, CA 92121
(619)453-8430
Western Microtechnology
12900 Saratoga Ave.
Saratoga, CA 95070
(408)725--1660

Colorado
Marshall Industries
12351 N. Grant Road
SuileA
Thornton, CO 80241
(303) 451-8383
Sterling Electronics
8200 South Akron Street
Suite 111
Englewood, C080112
(303) 792-3939

Connecticut
Marshall Industries
20 Sterling Drive
Wallingford, CT 06492
(203) 265--3822
Milgray Electronics
326 W. Main Street
Milford, CT 06460
(203) 795--0711
Western Microtechnology, Inc.
731 Main Street
Suite B2
Lantern Ridge Monroe, CT 06468
(203) 452-0533

Florlde
Marshall Industries
380 S. Northlake Blvd
Suite 1024
Altamonte Springs, FL 32701
(407) 767-8585
Marshall Industries
2700 W. Cypress Creek Rd.
SuiteC 106
FI. Lauderdale, FL 33309
(305) 977-4680
Marshall Industries
2840 Sherer Drive
SI. Petersburg, FL 33716
(813) 573-1399
Milgray Electronics
1850 Lae Road
Suile 104
Winter Park, FL 32789
(407) 647--5747

Dynamic RAM Data Book

FMI Distributors -

Sales Information

USA (Continued)

Florida (Continued)

Kansas

Michigan

Aeptron Electronics
33320 N.w. 53rd Street
Suite 206
FI. Lauderdale, FL 33309
(305)735-1112

Marshall Industries
10413 W. 84th Terrace
Lenexa, KS 66214
(913) 492-3121

Reptron Electronics
34403 Glendele
Uvonia, MI48150
(313) 525-2700

Aeptron Electronics
14501 McCormick Drive
Tampa, FL 33626
(813) 855-2351

Milgray Electronics
6901 W. 63rd Street
Overland Park, KS 66202
(913) 236-8800

Maryland
Georgia
Marshall Industries
5300 Oakbrook Pkwy
Suite 146
Norcross, GA 30093
(404) 923-5750

Georgia
Milgray Electronics
3000 Northwoods Parkway
Suite 270
Norcross, GA 30071
(404) 446-97n
Aeptron Electronics
3040 H Business Park Drive
Norcross, GA 30071
(404)446-1300

illinois
Classic Components
3336 Commercial Ave.
Northbrook, IL 60062
(312) 272-9650
Marshall Industries
50 E. Commerce Dr.
Suite I
Schaumburg, IL 60173
(312) 490-0155
Milgray Electronics
3223 N. Wilkey Aoad
Arlington Heights, IL 60004
(312) 253-1573
Aeptron Electronics
1000 E. State Hwy
Suite K
Schaumburg, IL 60173
(312)882-1700

Indiana
Marshall Industries
6990 Corporate Drive
Indianapolis, IN 46278
(317) 297--1)463

Minnesota
Marshall Industries
3955 Annapolis Lane
Plymouth, MN 55447
(612) 559-2211

Marshall Industries
2221 Broadbirch
Suite G
Silver Springs, MD 20910
(301)622-1118

Reptron Electronics
5929 Baker Aoad
Minnetonka, MN 55345
(612) 938--1looo

Milgray Electronics
9801 Broken Land Parkway
Columbia, MD 21045
(301)995-6169

Missouri

Vantage Components, Inc.
6925-A Oakland Mills Road
Columbia, MD 21045
(301)7~100

Maasachusatts
Interface Electronic Corp.
228 South Street
Hopkinton, MA 01748
(617) 435-6858
Marshall Industries
33 Upton Drive
Wilmington, MA 01887
(508) 658-081 0
Milgray Electronics
187 Ballardvale Street
Wilmington, MA01887
(508) 657-5900
Vantage Components, Inc.
200 Bulfinch Drive
Andover, MA01810
(508) 687-3900
Western Microtechnology
20 Blanchard Road
9 Corporate Piece
Burlington, MA 01803
(617) 273-2800

Michigan
Marshall Industries
31067 Schoolcraft Rd.
Uvonia. MI 48150
(313) 525-5850

Marshall Industries
33n Hollenberg Drive
Bridgeton, MO 63044
(314) 291-4650

New Jersay
Marshall Industries
101 Fairfield Road
Fairfield, NJ 07006
(201) 882--1)320
Marshall Industries
158 Gaither Drive
MI. Laurel, NJ 08054
(609) 234-9100
Milgray Electronics
3002 Greentree Exec. Campus
SuiteB
Marlton, NJ 08053
(609) 983-5010
Vantage Components, Inc.
23 Sebago Street
P.O. Box 2939
Clifton, NJ 07013
(201) n7-4100
Western Microtechnology, Inc.
387 Passaic Avenue
Fairfield, NJ 07006
(201) 882-4999

New Mexico
Sterling Electronics
3450-0 Pan American Freeway
Albuquerque, NM 87107
(505) 884-1900

8-13

0

Sales Informaffon

FMI Distributors - USA

Dynamic RAM Data Book

(Continued)

New York

Ohio

Texas

Marshall Industries
275 Oser Avenue
Hauppauge, NY 11788
(516) 273--2424

Marshallinclusbies
3520 Park Center Drive
Dayton, OH 45414
(513) 898-4480

Marshallindusbies
129 Brown Street
Johnson City, NY 13790
(607) 798-1611

Marshallindusbies
30700 Bain Bridge Road
Unit A
Solon, OH 44139
(216) 248-1788

Insight Electronics, Inc.
1778 Plano Road
Suite 320
Richardson, TX 75081
(214) 783--0800

New York

Milgray Electronics
6155 Rockside Road
Cleveland, OH 44131
(216)447-1520

Marshall Industries
2045 Chanault
Carrollton, TX 75006
(214) 233--5200

Reptron Electronics
404 E. Wilson Bridge Road
Suite A
Worthington, OH 43085
(614) 436-6675

Marshall Industries
2635 South Highway 77
Harlingen, TX 78550
(512)421-4621

Marshall Industries
1280 Scottsville Road
Rochester, NY 14624
(716) 235-7620
Mast Distributors
95 Oser Avenue
P.O. Box 12248
Hauppauge, NY 11788
(516) 273-4422
Micro Genesis
90-10 Colin Drive
Holbrook, NY 11741
(516) 472-6000
Milgray Electronics
77 Schmitt Blvd.
Farmingdale, NY 11735
(516) 420-9800
Milgray Electronics
1200 A Scottsville Rd.
Rochester, NY 14624
(716) 235-0830
Vantage Components, Inc.
1041-G West Jericho Turnpike
Smithtown, NY 11787
(516) 543--2000

North Carolina
Marshallindusbies
5224 Greens Dairy Road
Raleigh, NC 27604
(919) 878-9882
Reptron Electronics
5954-A Six Fork Road
Raleigh, NC 27609
(214) 783-0800

8-14

Oklahoma
Radio Inc.
1000 South Main
Tulsa,OK74119
(918)587--9123

Oregon

Marshall Industries
8504 Cross Park Drive
Austin, TX 78754
(512)837-1991

Marshall Industries
7250 Langtry
Houston, TX 77040
(713) 895-9200
Milgray Electronics
16610 N. Dallas Pkwy
Suite 1300
Dallas, TX 75248
(214) 248-1603

Marshallindusbies
9705 S.w. Gemin Drive
Beaverton, OR 97005
(503) 644-¢050

Reptron Electronics
3410 Midcourt
Carrollton, TX 75006
(214) 702-9373

Western Microtechnology
1800 N.W. 169th Place
Suite 8300
Beaverton, OR 97006
(503) 629-2082

Western Microtechnology, Inc.
18333 Preston Road
Suite 460
Dallas, TX 75252
(214) 248-3775

Pennsylvania

Western Microtechnology, Inc.
2500 Wilcrest, 3rd Roor
Houston, TX 77042
(713) 954-4850

Interface Electronic Corp.
7 Great Valley Parkway
Malvern, PA 19355
(215) 889-2060
Marshallinclusbies
701 Alpha Drive
Pittsburg, PA 15237
(412) 788-0441

Dynamic RAM Data Book

FMI Distributors Utah
Marshall Industries
466 lawndale Drive
Suite C
Salt Lake City, UT 84115
(801)485-1551
Milgray Electronics
4190 S. Highland Drive
Suite 102
Salt Lake City, UT 84124
(801 ) 272-4999

Washington
Insight Electronics, Inc.
12002115thAvenue, NE
Kirkland, WA 98034
(206) 820-8100

Sales Information

USA (Continued)
Marshall Industries
11715 N. Creek Parkway
Suite 112
Bothell, WA98011
(206) 4SEH;747
Westem Microtechnology
14636 N.E. 95th Street
Redmond, WA 98052
(206) 881-6737

Marsh Electronics
1563 S. 101 st Street
Milwaukee, WI 53214
(414) 475-6000
Marshall Industries
20900 Swenson Drive
Suite 150
Waukesha, WI 53186
(414) 797-84004

Wisconsin
Classic Components
2925 S. 160th Street
New Bertin, WI 53151
(414) 7SEH;300

8-15

Sales Information

Dynamic RAM Data Book

FMI Distributors - Canada
British Columbia
ITT Industries
3455 Gardner Court
Burnaby, B.C. V5G 4J7
(604) 291-1227
Space Electronics
1695 Soundry Road
Vancouver, B.C. V5K 4X7
(604) 294--1166

Ontario
ITT Industries
300 North Rivermede Road
Concord, ON L4K 2Z4
(416)736--1114

8-16

Marshall Industries
4 Paget Road
Unit 10 & 11
Framton, ON L6T 5G3
(416) 458-a046
Milgray Electronics
150 Consumers Road
Sui\e502
Willowdale, ON M2J 4R4
(416) 756-4481

Quebec
Marshall Industries
3869 Sources Blvd
Suite 207
0.0.0., QUE H9B 2A2
(514) 683-9440
Space Electronics
5651 Rue Ferrier Street
Montreal, QUE H4P 2K5
(514) 697-8676

Dynamic RAM Data Book

Sales Information

Fujitsu Mikroelektronik GmbH (FMG) Sales Offices for
Europe
France
Fujitsu
Immeuble Ie Trident
3-{;, Voie Felix Eboue
1'-94024 Creteil Cedex
Tel: (1)4-207-8200
Telex: 262861
FAX: (1 )4-207-7933
F.R. Germany
Fujitsu Mikroelektronik GmbH
Lyoner Strasse 44-48
Arabella Center 9. OG
0-6000 Frankfurt am Main 71
Tel: (69)66320
Telex: 411963
FAX: (69)66321
Fujitsu Mikroelektronik GmbH
Am Joachimsberg 10-12
0-7033 Herrenberg
Tel: (07032) 4085
FAX: (07032) 4088

Fujitsu Mikroelektronik GmbH
CarI-Zeiss-Ring 11
D-8045lsmaning
bei Munchen
Tel: (89)960-9440
Telex: 8974464
FAX: (89)960-9442
"aly
Fujitsu Microelectronics
ltalia S.R.L.
Centro Direzionale Milancfiori
Strada 4 - Palazzo Al2
1-20094 Milanc
Tel: (39)(2)824-6170/176
Telex: 318546
FAX: (39)(2)824-6189

Sweden
Fujitsu Microelectronics Ltd.
Torggatan8
1715480Ina
Tel: (8)764-6365
Telex: 13411
FAX: (8)28- / data out (DQ) <0 .. .3>, and output enable (OR). Figure 5 shows the timing for bit masking.

9-17

Various Features
of Fujitsu DRAMs

ADDR

November 1989
FuHtsu Micrpe!ectronics. Ino.

Row

MDOIDClO

MDlIDQI

MD2IDQ2

MD3/DQ3

No change

No change

Figure 5. Bit Masking
Nol.. : 1Althe fall ol~ (and ilCE = H and ME =H). all MD inputs thaI are high will be prepared 10 receive new data. MD inputs
that are low at the fall of ~ will not be prepared 10 be rewritten.
2Atthe fall of ME the new data present on all MD pins that were high at the fall of ~ will be written 10 the appropriate bit 01
the memory.

DRAM Refresh Methods
DRAMs are basically made up of decoders, latches and capacitors. Capacitors store charges applied to
them. Due to leakage, capacitors also dissipate that charge. Consequently, in order to retain their data, all
DRAMs need to be periodically refreshed with a pulse to each cell. Methods of refreshing vary from
device to device. Some of these methods are discussed in the following paragraphs.
RJ{S'-Only Refresh
RAS-only refresh causes the output buffer to remain in a high-impedance state until certain RAS and CAS
timing parameters are met. This type of refresh cycle is ideal for wired-OR outputs. External glue logic

9-18

Various Features
of Fujitsu DRAMs

November 1989

Fujitsu Microelectronics. Inc.

generates row addresses and timing parameters so that all rows are refreshed within the allotted refresh
cycle time. Also, whenever a row is accessed for a read or write operation it is refreshed. A two-step
process is reqUired to refresh all the cells.
1.

Initially the RAS and CAS' are high. Then a row address is applied and the RAB' is brought low,
thereby refreshing all cells in that row.

2.

After the RAS is brought high, a new row address is applied and the procedure repeats.

A timing diagram is shown in Figure 6.

~----------------tRC----------------~

'1'--------.3;1---- tRP - - - - I

VH-

V\l -

DO~

----------~~--------------------------~-----------------------------r
tOH

OH

=::::::::::;::~~----------------

V -VOL
:

DESCRIPTION
Refresh of RAM memory cell. I. eccompHshed by performing a r.ad, a wr~e, or a read-modlfy-wrlte cycle at each of 512
row addr••••• every 8.2-mlliloecond•. Thr.e refr.sh mode. are Ivallable: l!ti:!-only refresh, rn-befor.-lln refresh, and
hidden refr••h.

l!ti:!-oniy refr.sh Is perform.d by ke.plng l!ti:! Low and ~ High throughout the cycle; the row address to be refreshed Is
latch.d on the failing .dge of lln. During l!ti:!-only refr.sh, Do~ pin I. kept In a high-Impedance state.

Figure 6. Typical A'lS'-Only Refresh Cycle
~

Before ~ Refresh

CAS' before RAS refresh eliminates the need for external logic to generate refresh addresses. When using
the CAS' before RAS refresh, a one-time start-up procedure must be undertaken enabling this feature and
ensuring proper device operation. This procedure initializes the internal address generator.
One requirement of the procedure is that when power is applied, the CAS' and RAS should be high. After
power stabilization, the CAS' should go low before the RAS goes low. This cycle has ~rtain setup and
hold time constraints, depending on the particular chip being used, but generally speaking at least eight
CAS' before RAS cycles must occur to initialize the internal counter.
Once this procedure is completed the nOrmal CAS' before RAS refresh operation is as follows:
1.

The CAS' is brought low then the RAS is brought low,

2, The refresh address is supplied by an internal address generator.
A timing diagram is shown in Figure 7,

9-1'

Various Features
of Fujitsu DRAMs

November 1989
Fujitsu Microelectronics. Inc.

V... V1L

-

VOH--=:::~::::3;~
Dour

VOL _ :

__________________________

HIGH-Z:----------------------

DESCRIPTION

~-before-rorn refresh I. an on-chip refresh capabll~y Ihal ellmlnales lhe need for exlemal rofresh addresses. If ~ Is
held Low for the spectfled setup time (tesR) before RAS goes Low, the on-chlp refresh control clock generators and refresh
address countsr are enabled. An, Internal refresh operation automatically occurs and the refresh address counter Is
Inlemally Incremented In preparallon for lhe nexi CAS-before-RA'§ refresh oporallon.

tCHR

tCSR
tOFF

_

15 ns min.

0 ns min.
25 ns

max.

tRAS
tRC

tRPe

_
_

106 na min.
200 ns min.
20 ns min.

Figure 7. CXS Before ~ Refresh Cycle
Hidden CXS Before ~ On-Chip Refresh
Hidden CAS before RAS on-chip refresh is similar to a CAS before RAS refresh except that data remains
valid on the data pins as long as the CAS is low. Because the internal address counter is used in this cycle,
at least eight dummy CAS-before-RAS refresh cycles should occur immediately after power-up. For this
type of refresh, keep the CAS low at the end of a normal read or read-write cycle, and then bring the RAS
high, then back to low. Since data remains valid on the output until the CAS goes high, this cycle is an
extended read or write cycle in the foreground and a "hidden" refresh cycle in the background. A timing
diagram is shown in Figure 8.

9-20

Various Features
of Fujitsu DRAMs

November 1989
Fujitsu Microelectronics Inc.

VIHRAS

Vll-

VIHCAS

Ao to Ag
(Read)

Vtl-

VIHV1L-

WE

V,H-

(Read)

Vll-

DOUT

teAS

•

tASR
tRAH

•
•

tRAS

•

lAC

•

10 na

min.

One mfn.
10 nl min.
105111 min.
200111 min.

tACO
_
tRRH.
tCHR
•

teAS

•

tCAC

_

tRAe

•

20 na min.
0,. min.
20", min.

55 na min.
50na min.
100 I'll

min.

Figure 8. 'TYpical Hidden ~ before JUS Refresh Cycle

DRAM Implementation in an MBL80286 Environment
Figure 9 shows a typical implementation of an MBL80286 microprocessor, an MB1430A DRAM controller,
an MBL82288 bus controller and severall-megabit DRAMs. The memory is organized in two banks; one
bank contains the data of odd addresses and the other bank contains the data of even addresses. This type
of configuration is known as interleaving memory. The main advantage to such an organization is that
while one bank of memory is in tRP (RAS precharge time) the second bank is accessed by the bus. Then,
while the second bank is in tRP the first bank is accessed by the bus. This decreases the perceived DRAM
cycle time. Interleaving memory is an optimum configuration as long as the same bank of memory cells
doesn't need to be accessed sequentially.

9-21

~.~

OSCf30MHZl

~g

.<>2
EO;
!!!§
~~

'"

S

~

1

MBLB0286j.LP

~

r-

ClK
RESET

foe "REJrn'i'

AS

COD7Imi\

M7IO

m

tlWTC'

AI-21

I

MBLB2a2
Latches
~ STB

Al-l0

Sf
Sll'
:!l~
~i/!

mQ

11;,,,,

.. s
:s:;::.

.g~
~'(s

ClK
RESET

MAO-9

RAO-9

~

MB81Cl001
(MB81Cl000
Separate
1/0

t-WlO'

WlO'
DOUTII

f--

DOUTII

ja ia

R7W

WlO'

...

/

,

I

t::7iS AO-9

f-

L--

t--

R)J;S

WlO'
DIN

WaitStete
Generator

DOUT

/

/

L. t::7iS AO - 9

MB81Cl00l
(MB81Cl000
Separate
1/0

MBLB2288
Bus
J.~
Control
Sf
DEN t-Sll'
DTlR I - - ClK
ALE

,I

RDY

L.

II

DIN

1a ia

m:

r~

t-R)J;S

I

t::7iS AO - 9

R)J;S'f
BS

I

I[ T~
ROr1DhRl
MBLB2284
CLK
Generator

CAO-9

F24S
Bidirectional
Transceiver

r-"

R)J;S
MB81Cl00l
(MB81Cl000
Separate

DIN

1/ tlWTC'

DO-IS

~

VO

,....ft.

,

/

t::7iS AO-9

All-A20

A21

/

MODEO
MODEl

~
~ f-

BAeO
BACl

...---J

/

Lrft.

liS

1>1::

Generator

'Sf

~
~

elK

J:S

lC

I

-Yj

/

MBI430Al31A
elK

R)J;S

MB81Cl00l
(MB81Cl000
Separate

VO

II

Leo WlO'
DIN

DOUTII

ja ia

Ja ia

Ht:AU~

ClK

Note: Unused pins should be tied high or lolA
N

Figure 9. Schematic of 1 megabit x 32 DRAM with Zero WaH States

I

iii

Various Features
of Fujitsu DRAMs

November 1989
Fujitsu Microelectronics. Inc.

Figure 10 shows the RASO and RASI timing that allows interleaving. If the same bank is accessed
sequentially then the microprocessor must generate wait states and endure the tRP. The odd or even bank
is selected depending on the value of bus high enable (BIlE) and AD. The size of the operation taking
place (word or byte) can also be determined by polling BHE' and AD. This relationship is shown in Table 4.

"'1.0-----

1sl RAM Cycle

. .----

-----.~I

~"'-----4-L-1".0-----

3rd RAM Cycle

tRP

·1

2nd RAM Cycle

,,----L
___

IRP

---..j

Figure 10. RXS Timing of Interleaving Memory

Table 4. Relationship Between BRE, AO, and Size of Operation
Operation

BRE

AO

0

0

Word Transfer

0

1

Byte Transfer on Upper Half of Data Bus (015-08)

1

0

Byte Transfer on Lower Half of Oala Bus (07-00)

1

1

Reserved

The purpose of the octal latches in the Figure 9 schematic (MBL8282) is two-fold: first to demultiplex the
address lines and secondly to increase the total drive capability to 32 rnA. Once the address lines have
been demultiplexed they become inputs to a DRAM controller. The DRAM controller generates the
necessary RA5 and CAS timing on the RA:Sn, CASU, RASI, and CABI lines. The MB1430A DRAM
controller can accommodate various microprocessors induding the Motorola 68000. In addition, the
MB1430A can drive up to 44 DRAMs without the use of drivers.
The purpose of the bus transceivers in the Figure 9 schematic is two-fold: first to demultiplex the data
lines from the multiplexed address-data lines, and secondly to allow microprocessor read-writes. In the
case of a write operation, once the data has been demultiplexed it is put through a bidirectional bus driver
which allows data to be read and increases the drive capability. The direction of data flow is determined
by the data transmit/receive (DT/R) pin. The bus controller in the Figure 9 schematic orchestrates the
entire system under the control of the microprocessor, MBL80286. The signals output by the
microprocessor determine the operation taking place (see Table 5).

9-23

Various Features
of FUjitsu DRAMs

November 1989
Fujitsu Microelectronics. Inc.

Table 5. MBL80286 Bus Cycle Status Definition
CODIJNTj(

M7fO

'Sf

SO

o(low)

0

0

0

Interrupt Acknowledge

0

0

0

1

Reserved

0

0

1

0

Reserved

0

0

1

1

None: Not a Status Cycle

0

1

0

0

If AI = 1 Then Halt; Else Shutdown

0

1

0

1

Mem~ry

0

1

1

0

Memory Data Write
None: Not a Status Cvcle

Bus Cycle Initiated

Data Read

0

1

1

1

1 (high)

0

0

0

Reserved

1

0

0

1

1/0 Read

1

0

1

0

1/0 Write

1

0

1

1

None: Not a Status Cycle

1

1

0

0

Reserved

1

1

0

1

Memory Instruction Read

1

1

1

0

Reserved

1

1

1

1

None: Not a Status Cycle

DRAM Modules
DRAM modules are dense memory packages that are a fraction of the size of the same memory structure
in a board design. Some of the common module sizes are 1M x 9,256 k x 9, and 16 k x 32.

Summary
Fujitsu DRAMs offer a selection of features that include: fast page mode, nibble mode, and static column
mode. Fujitsu also manufactures dual-port DRAMs and DRAM modules.

9-24

November 1989
Fujitsu Microelectronics Inc.

Various Features
of Fujitsu DRAMs

References
Fujitsu Microelectronics, Inc. 8116-Bit Microprocessors Microcomputers Peripherals. 1987 Data Book. Tokyo,
Japan: Fujitsu Limited; San Jose, CA: Fujitsu Microelectronics, Inc., 1986.

_. Memories, 1986-87 Data Book. Tokyo, Japan: Fujitsu Limited; San Jose, CA: Fujitsu Microelectronics, Inc.,
1986.
Iqbal, Mohammad S. Effects of Soft Errors on Bipolar and MOS Memories. Application Note. San Jose, CA:
Fujitsu Microelectronics, Inc., 1989.
Sedra, Adel S. and Kenneth C. Smith. Microelectronic Circuits. New York: CBS College Publishing, 1982.
Stone, Harold S. Microcomputer Interfacing. Reading, Massachusetts: Addison-Wesley Publishing Company, 1982.

9-25

Dynamic RAM Data Book

Notes

1-26

Dynamic RAM Data Book

Notes

9-27

Dynamic RAM Data Book

Notes

9-28

NMOS DRAMs

D

CMOS DRAMs

lID

Application-Specific RAMs

..
..
DI
..
..

D

MOS RAM Modules
CMOS DRAM Modules
Quality and Reliability
Ordering Information
Sales Information
Appendix - Design Information
1990_Fujitsu_Dynamic_RAM_Products 1990 Fujitsu Dynamic RAM Products

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