1990_Intel_Embedded_Applications_Handbook 1990 Intel Embedded Applications Handbook

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-

Intel the Microcomputer Company:
When Intel invented the microcomputer in 1971, it created the era of microcomputers. Whether
used in embedded applications such as automobifes or microwave ovens, or as the CPU in
personal computers or supercomputers, Intel's microcomputers have always offered leading-edge
technology. Intel continues to strive for the highest standards in memory, microcomputer
components, modules and systems to give its customers the best possible competitive advantages.

EMBEDDED APPLICATIONS
HANDBOOK

1990

-

Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear In this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the laiest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel pro~ucts:
376, 386, 387,486, 4-SITE, Above, ACE51, ACE96, ACE186, ACE196, ACE960,
BITBUS, COMMputer, CREDIT, Data Pipeline, DVI, ETOX, FaxBACK, Genius, i, t,
i486, i750, i860, ICE, iCEL, ICEVIEW, iCS, iDBP, iDIS, 12 1CE, iLBX, iMDDX, iMMX,
Inboard, h;site, Intel, intel, Intel386, intelBOS, Intel Certified, Intelevision, in!aligent
Identifier, inteligent Programming, Intellec, Intellink, iOSP, iPAT, iPDS, iPSC, iRMK,
iRMX, iSBC, iSBX, iSDM, iSXM, Ubrary Manager, MAPNET, MCS, Megachassis,
MICROMAINFRAME, MULTI BUS, MULTICHANNEL, MULTIMODULE, MultiSERVER,
ONCE, OpenNET, OTP, PR0750, PROMPT, Promware, QUEST, QueX, Quick-Erase,
Quick-Pulse Programming, Ripplemode, RMx/80, RUPI, Seamless, SLD,
SugarCube, ToolTALK, UPI, Visual Edge, VLSiCEL, and ZapCode, and the combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk
Data Sciences Corporation.
MULTI BUS is a patented Intel bus.
CHMOS and HMOS are patented processes of Intel Corp.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark or products.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
©INTEL CORPORATION 1989

CG·l01789

.,..

CUSTOMER SUPPORT
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
Customer Support is Intel's complete support serVice that provides Intel customers with hardware support,
software support, customer trainin(l, consulting services and network management services. For detailed information contact your local sales offIces.
After a customer purchases any system hardware or software product, service and support become major
factors in determining whether that product will continue to meet a customer's expectations. Such support
requires an international support organization and a breadth of programs to meet a variety of customer needs.
As you might expect, Intel's customer support is quite extensive. It can start with assistance during your
development effort to network management. 100 Intel sales and service offices are located worldwide-in the
U.S., Canada, Europe and the Far East. So wherever you're using Intel technology, our professional staff is
within close reach.

HARDWARE SUPPORT SERVICES
Intel's hardware maintenance service, starting with complete on-site installation will boost your productivity
from the start and keep you running at maximum efficiency. Support for system or board level products can be
tailored to match your needs, from complete on-site repair and maintenance support to economical carry-in or
mail-in factory service.
Intel can provide support service for not only Intel systems and emulators, but also support for equipment in
your development lab or provide service on your product to your end-user/customer.

SOFIWARE SUPPORT SERVICES
Software products are supported by our Technical Information Service (TIPS) that has a special toll free
number to provide you with direct, ready information on known, documented problems and deficiencies, as
well as work-arounds, patches and other solutions.
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information Phone Service), updates and subscription service (product-specific troubleshootmg guides and;
COMMENTS Magazine). Basic support consists of updates and the subscription service. Contracts are sold in
environments,which represent product groupings (e.g., iRMX® environment).

CONSULTING SERVICES
Intel provides field system engineering consulting services for any phase of your development or application
effort. You can use our system engineers in a variety of ways ranging from assistance in using a new product,
developing an application, personalizing training and customizing an Intel product to providing technical and
management consulting. Systems Engineers are well yersed in technical' areas such as microcommunications,
real-time applications, embedded microcontrollers, and network services. You know your application needs;
we know our products. Working together we can help you get a successful product to market in the least
possible time.

CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering various aspects of system design and implementation. InJ·ust three to ten days a limited number of individuals learn more in a single workshop than in weeks of
self-stu y. For optimum convenience; workshops are scheduled regularly at Training Centers worldwide or we
can take our workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course
categories include: architecture and assembly language, programming and operating systems, BITBUS and
LAN applications.
TN

NETWORK. MANAGEMENT SERVICES
Today's networking products are powerful and extremely flexible. The return they can provide on your investment via increased productivity and reduced costs can be very substantial.
Intel offers complete network support, from definition of your network's physical and functional design, to
implementation, installation and maintenance. Whether installing your first network or adding to an existing
one, Intel's Networking Specialists can optimize network performance for you.

CG/CUSTSUPP/100389

-

-.
Table of Contents
MCS®-48 FAMILY
Chapter 1
MCS®-48 APPLICATION NOTES
AP-24
AP-40
AP-49
AP-55A
AP-91

Application Techniques for the MCS®-48 Family.. .... ...... ....... .... ...... ...... ... ....
Keyboard/Display Scanning with Intel's MCS®-48 Microcomputers. .... .........
Serial I/O and Math Utilities for the 8049 Microcomputer .... ........................
A High-Speed Emulatorforthe Intel MCS®-48 Microcomputers ...................
Using the 8049 as an 80 Column Printer Controller .. ...... ....... ..... ..... .... ... ... ...

1-1
1-25
1-50
1-73
1-173

MCS®-S1 FAMILY
Chapter 2
MCS®-S1 APPLICATION NOTES & ARTICLE REilRINTS
AP-69
AP-70
AP-223
AB-38
AB-39
AB-40
AB-12
AP-252
AP-410
AB-41
AP-415
AP-425
AP-429

An Introduction to the Intel MCS®-51 Single-Chip Microcomputer ....... ..........
Using the Intel MCS®-51 Boolean Processing Capabilities ...........................
8051 Based CRT Terminal Controller ........................... :..............................
Interfacing the 82786 Graphic Coprocessor to the 8051 ...............................
Interfacing the Densitron LCD to the 8051 .............................. ,....................
32-Bit Math Routines for the 8051 ...............................................................
Designing a Mailbox Memory for Two 80C31 Microcontrollers Using EPLDs
Designing with the 80C51 BH .......................................................................
Enhanced Serial Port on the 83C51 FA .............. ;.........................................
Software Serial Port Implemented with the PCA ..... ... ....... ..... ... ..... ....... .......
83C51 FAlFB PCA Cookbook ......................................................... :............
Small DC Motor Control . ... .............. ... .......... ..... ... ............ ... ... ....... ...... ... .....
Application Techniques for the 83C 152 Global Serial Channel in.
CSMAlCD Mode .. ... ....... ... .... ...... ....... ............ ....... ....... ................. .... ..... .....
AR-517 Using the 8051 Microcontrollerwith ResonantTransducers .........................
AR-526 Analog/Digital Processing with Microcontrollers .... :......................................

Chapter 3

.

2-1
2-31
2-76
2-153
2-159
2-166
2-175
2-189
2-213
2-221'
2-244
2-287
2-301
2-369
2-374

.

ASIC FAMILY APPLICATION NOTE & ARTICLE REPRINT
AP-413 Using Intel's ASIC Core Cell to Expand the Capabilities of an 80C51
Based System ........................... :... .... ..... .... ..... ... .......... ..... ....... ... ..... ...........
AR-537 A Fast-Turnaround, Easily Testable ASIC Chip for Serial Bus Control..........

3-1
3-11

THE RUPITM FAMILY
Chapter 4
RUPITM APPLICATION NOTES
AP-281 UPI-452 Accelerates 80286 Bus Perlormance .............................................
AP-283 RUPITM/Flexibility in Frame Size with the 8044 ................................:...........

80186/80188 FAMILY
ChapterS
80186/188 APPLICATION NOTES
AP-186
AP-258
AP-286
AB-36
AB-37
AB-31
AB-35

4-1
4-21

.

Using the 80186/188/C186/C188 Microprocessor ........................................
High Speed Numerics with the 80186/80188 and 8087 ................................
80186/188 Interface to Intel Microcontrollers ...............................................
80186/80188 DMA Latency ................. ,.......................................................
80186/80188 EFI Drive and Oscillator Operation .. ........ ..... ...... ....................
The 80C186/80C188 Integrated Refresh Control Unit ..................................
DRAM Refresh/Control with the 80186/188 '" ..... ..... ..... ...............................

vii

5-1
5-83
'5-99
5-129
5-132
5-134
5-147

.
Table of Contents (Continued)
MCS®-96 FAMILY
Chapters
MCS®-96 APPLICATION NOTES & ARTICLE REPRINT
AP-248 Using the 8096 ... ;.,......................................................................................
AP-275 An FFT Algorithm with the MCS®-96 Products
.
Including Supporting Routines and Examples ........ .................... ...... ............
AB-32 Upgrade Path from 8096-90 to 8096BH to 80C196 ................ ~.....................
AB-33 Memory Expansion for the 8096 ............ ........ ............. ............ ........ .............
AB-34 Integer Square Root Routjne for the 8096 ........... :................................. ;......
AP-406 MCS®-96 Analog Acquisition Primer .... .................... ............ ...... ..................
AP-428 Distributed Motor Control Using the 80C 196KB ...........................................
AR-515 A Single-Chip Image Processor .......... :........................................................

Chapter 7
MCS®-96 Diagnostic Library ............................................................ .................. .......
Chapter 8

6-1
6-103
6-178
6-181
6-193
6-197
6-296
6-325
7-1

80960 ARTICLE REPRINTS
AB-42 80960KX Self-Test ...............................................:......................................
AR-541 Intel's 80960: An Architecture Optimized for Embedded Control ................ ,..
AR-551 Embedded Controllers Push Printer Performance ............................ ,...........
AR-557 A Programmer's View of the 80960 Architecture .................... ........ ...... ........

8-1
8-4
8-18
8-24

GENERAL MICROCONTROLLER
Chapter 9

APPLICATION NOTES
AP-125
AP-155
AP-318
AP-315

Designing Microcontroller Systems for Electrically N9isy Environments .......
Oscillators for Microcontrollers ..... :...............................................................
Intel's 87C75PF Port Expander Reduces System Size & Design Time .........
Latched EPROMs Simplify Microcontroller Designs .....................................

viii

9-1
9-23
9-55
9-80

-

MCS®-48 Application Notes

1

-

_

v

.inter

AP-24

APPLICATION
NOTE

.

© Intel Corporation, 1977

February 1977

98413A

1-1

AP-24

INTRODUCTION
The INTEL ® MCS-48™ family consists of a series
of seven parts, including three processors, which take
advantage of the latest advances in silicon technology to provide the system designer with an effective solution to a wide variety of design problems.
The significant contribution of the MCS-48 family
is that instead of consisting of integrated microcomputer components it consists of integrated
microcomputer systems. A single integrated circuit
contains the processor, RAM, ROM (or PROM), a
timer, and I/O.
This application note suggests a variety of application techniques which are useful with the MCS-48.
Rather than presenting the design of a complete
system it describes the implementation of "subsystems" which are common to many micropro-

cessor based systems. The subsystems described are
analog input and output, the use of tables for
function evaluation, receiving serial code, transmitting serial code, and parity generation. After an
overview of the MCS-48 family these areas are discussed in a more or less independent manner.
THE MCS-48™ FAMILY
The processors in the MCS-48 family all share an
identical architecture. The only significant difference is the type of on board program storage which
is provided. The 8748 (see Figure I) includes 1024
bytes of erasable, programmable, ROM (EPROM),
the 8048 replaces the EPROM with an equivalent
amount of mask programmed ROM, nd the 8035
provides the CPU function with no on board
program storage. All three of these processors

VOO

~PAOGRAMSUPPLY

POWER
SUPPLY

{

~
V

+5V (LOW POWER
STANDBYI

~GND

--

TEST 0
TEST 1

REGISTER

REGISTER

-

,NT

-,.-FLAG

a

TIMER FLAG

;>

3

REGISTER

4

REGISTER

5

REGISTER

6

REGISTER

7

8lEVEL STACK

(VARIABLE LENGTHI
OPTIONAL SECOND
REGISTER BANK

DATA STORE

REStDENT

RAM ARRAY
64 ~ 8
PROM
EXPANDER

CPU
MEMORY

STROBE

SEPARATE

MCS4s™ Internal Structure

1-2

AP-24
INSTRUCTION SET

S
~

:;
E

11
~

~

'5

~
~

g
~

c.

E

~

la:=

Bytes

Mnemonic

Description

ADD A.R
ADD A.@R
ADD A. =data
ADDC A. R
ADDC A.@R
ADDC A. =data
ANL A. R
ANL A.@R
ANL A. =data
DRL A. R
DRL A.@R
ORL A. =data
XRL A. R
XRL A.@R
XRL A, =data
INCA
DEC A
CLR A
CPL A
DAA
SWAP A
RL A
RLC A
RR A
RRCA

Add register to A

Add data memory to A

,,
,,
,
,
2

Add immediate to A

Add register with carry
Add data memory with carry
Add immediate with carry
And register· to A

And data memory to A
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive Or register to A
Exclusive or data memory to A
Exclusive or immediate to A

Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry

IN A. P
OUTL p. A
ANL P. =data
ORL P, =data
INS A. BUS
OUTL BUS, A
ANL BUS, =data
OR L BUS, =data
MOVD A, P
MOVD P,A
ANlDP,A
ORlD P. A

And A to Expander port
Or A to Expander port

INC R
INC@R
DEC R

Increment register
Increment data memory
Decrement register

JMP add,
JMPP@A
DJNZ R, addr
JC add,
JNC addr
J Z add,
JNZ add,
JTO add'
JNTO addr
JTl add,
JNTl addr
JFO addr
JF' addr
JTF addr
JNI addr
JBb add,

Jump unconditional
Jump indirect
Decrement register and skip
Jump on Carry:::: 1
Jump an Carry:::: 0
Jump on A Zero
Jump on A not Zero

I nput port to A
Output A to port
And immediate to port

2

,,
,,

2

2

,
,
2

,,
,,
,,
,,

,,

2
2

,,

Or immediate to port
Input BUS to A

Output A to BUS
And immediate to BUS
Or immediate to BUS
Input Expander port to A
Output A to Expander port

Cycle

'S

2

.c
~

2

2

2

2

~

>

,

0

:;
~

,,
,
,

C

,

,
2
2
2
2
2

,,

,,

23c
~

0

,tJ
"';::

=
E

i=

,

, g

,

2
2
2
2
2
2

c

.c
~
c

~

III

Jump on TO
Jump on TO

=,
=0

Jump on T1 = 1

Jump on T'
Jump on FO

=0
=,

Jump on Fl = 1
Jump on timer flag

Jump on

iNT = 0

Jump on Accumulator Bit

2
2
2
2
2
2
2
2
2
2
2
2
2
2
2

Mnemonic

Description

CALL
RET
RETR

Jump to subroutine
Return

CLR C
CPL C
CLR FO
CPL FO
CLR F'
CPL F'

Clear Carry

Bytes

0

tJ

MDV A. R
MOV A.@R
MDV A. =dat~
MOV R, A
MDV@R,A
MOV R. =data
MOV@R, =data
MDV A, PSW
MDV PSW, A
XCH A, R
XCH A,@R
XCHD A,@R
MDVX A,@R
MDVX@R,A
MOVPA,@A
MDVP3A,@A

2
2
2

immediate to A
2
A to register
A to data memory
immediate to register
2
immediate to data memory 2

2

Complement Carry

Clear Flag 0
Complement Flag 0
Clear I'Ia9 ,
Complement Flag'

Move register to A
Move data memory to A
Move
Move
Move
Move
Move

Move PSW to A
Move A to PSW

,,,
, ,
, ,
, ,
,, ,,
,, ,,
,
,,
,
,
,,

2
2

,,,
,,
'2

2
2
2

,,
,,
,

,,

,,,
,,
,,

Enable external interrupt
Disable external interrupt
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable Clock output on TO

,
,
,
,
,
,,

,,
,,,
,,

No Operation

,

,

Read Timer/Counter
Load Timer/Counter
Start Timer
Start Counter
Stop Timer/Counter
Enable Timer/Counter 'Interrupt
Disable Timer/Counter Interrupt

EN I
DIS I
SEL RBO
SEL RB'
SEL MBO
SEL MB'
ENTO CLK

NOP

2
2

Mnemonics copyright Intel Corporation 1976

1-3

,,
,

,

MOV A, T
MOV T,A
STRTT
STRT CNT
STDP TCNT
EN TCNTI
DIS TCNTI

Figure 2. 8048/8748/8035 Instruction Set

2

Exchange A and register
Exchange A and data memory
Exchange nibble of A and register 1
Move external data memory to A
Move A to external data memory
Move to A from current page
Move to A from Page 3

2

2
2,
2
2
2
2
2

Cycles

,
,

Return and restore status

III

,,,

2
2

~

e

,,
,, u::~
,,
,,
,,, .

2
2
2
2
2
2
2

,

.

,,

AP-24

operate from a single 5-volt power supply. The
8748 requires an additional 25-volt supply only
while the on board EPROM is.being programmed.
When installed in a system only' the 5-volt supply is
needed. Aside from program storage, these chips
include 64 bytes of data storage (RAM), an eight
bit timer which can also be used to count external
events, 27 programmable I/O pins and the processor
itself. The processor offers a wide range ofinstruction capability including many designed for bit,
nibble, and byte manipulation. The instruction set
is summarized in Figure 2.
Aside from the processors, the MCS48 family
includes 4 devices: one pure I/O device and 3 combination memory and I/O devices. The pure I/O
device is the 8243, a device which is connected to a
special 4 bit bus provided by the MCS48 processors
and which provides 16 I/O pins which can be programmatically controlled.
The combination memory and I/O devices consist
of the 8355, the 8755, and the 8155. The 8355
and the 8755 both provide 2,048 bytes of program
storage and two eight bit data ports. The only
difference between these devices is that the 8355
contains masked program ROM and the 8755 contains EPROM. The 8155 combines 256 bytes of
data storage (RAM), two eight bit data ports, a six
bit control port, and a 14 bit programmable timer.

[ ) Number of Available Timers
( ) Number of Available I/O Lines
1088

lK I8035
8048
8035
8355
8048
8355
2-8355
4·8155
4·8155
4-8155
4-8155
(101) [5)
(116) [5J
[5J
(116) [5J
(131)
832
768 r-'
8035
8048
8035
8355
8048
8355
2-8355
3-8155
,3·8155
3-8155
3·8155
(4)
(80) (4)
(95) (4)
(95) [4J
(110)

r8048
2-8155
[3)
(59)

8035
8048
8035
8355
8355
2·8355
2-8155
2-8155
2-8155
(3)
(74) (3)
(74) [3J
(89)

f8035
8048
8035
8048
8355
8355
2·8355
8155
8155
8155
8155
(38) (2)
(53) [2J
[2J
(53) [2J
(68)
64
8035
8048
8035
8048
8355
8355
2·8355
(1)
(24) [lL
(28) [lJ
(28) [lJ
(43)

lK

2K

3K

4K

PROGRAM MEMORY (ROM)

Figure 3 shows the various system configurations
which can be achieved using the MCS48 family of
parts. It should also be noted that eight of the processors' I/O lines have been configured as a bidirectional bus which can be used to interface to standard Intel peripheral parts such as the 8251 USART
(for serial I/O), the 8255A PPI (provides 24 I/O
lines) and the complete range of memory compo·nents.
. More detailed information concerning the MCS48·
family can be obtained from the "MCS48 Microcomputer User's Manual" which provides a complete description of the MCS48 family and its
.members. A general familiarity with this document
will make the application techniques which follow
easier to understand.

Figure 3. The Expanded MCS48 TM System

specifically designed to interface with microprocessors_
A block diagram oftheMP-IO is shown in Figure 4.
It consists of two eight bit digital to analog conver-

ters, two eight bit latches which are loaded from
the data bus, and address decoding logic to determine when the latches should be loaded. The 0/ A
converters each generate an analog output in the
range of 10 volts with an output impedance of In.
Accuracy is ±0.4% of full scale and the output is
stable 25~sec after the eight bit binary data is
loaded into the appropriate latch. The latches are
loaded by the write pulse (WR) whenever the
proper address is presented to the MP-IO. The
lower two addresses (AO and AI) are used internally by the device. Addresses A2 & A3 are compared with the address determination inputs B2
and B3. If their signals are found to be equal, and
if addresses A4-A 13 are all high, then the device
is selected and one of the latches will be loaded.
Address bit Al selects between output I and output 2. If address bit AO is set then the initialization channel of the DIA is selected. In order to
prepare for operation a data pattern of 80H must

ANALOG I/O
If analog I/O is required for a MCS48™ system

there are many alternatives available from the
makers of analog I/O modules. By searching through
their catalogs it is possible to find almost any combination of features which is technically feasible. Perhaps the best example of such modules are the MP10 and MP-20 hybrid modules recently introduced
by Burr-Brown Research Corporation. The MP-IO
provides two analog outputs and the MP-20 provides 16 analog inputs. Both of these units were
1-4,

AP-24

A,A,A,

.,.,

ADDRESS
LOGIC

AO

With no Rext (Rext = 00) thl! gain is two and the
input is 0-5 or ±5 volts full scale. Adding an I!xternal resistor results in higher gain so that low level
(±50mV) signals from thermocouples and strain
gauges can be accommodated. The output from
the amplifier is applied to the actual A/D converter which provides an eight bit output with
guaranteed monotonicity and an accuracy of ±0.4~
of full scale. Note that this accuracy is specitied
for the entire module, not just for the converter
itself. The control logic monitors address lines
A 15 through A4 to determine when the address of
the unit has been selected. An address that the unit
will respond to is determined by II address control
pins, labeled A4 through A 14. If one of these pins
is tied to a logic 0 then the corresponding address
pin must be high in order for the unit to be selected.
If the pin is tied to a logic I then the corresponding
address pin must be low. If the address of the
module is selected when MEMR pulse occurs, the
lower four addresses (A3-AO) are stored in a latch
which addresses the multiplexer. The coincidence
of the proper address and MEMR also initiates a
conversion and gates the output of the converter
on to the eight bit data bus.

w"R---Q

LOAD 2

DB 70'
REG 1

A'G'~

,

OA

ANALOG OUT

DA

ANALOG OUT

,

Figure 4. Mp·10 Block Diagram

be output to this channel folJowing the reset of the
device.
A block diagram of the MP-20 analog to digital
converter is shown in figure 5. This unit consists
of a 16 input analog multiplexer, an instrumentation amplifier, an eight bit successive approximation analog to digital converter, and control logic.
~he 16 inp~t multiplexer can be used to input
eIther 16 smgle ended or 8 differential inputs.
The output from the mUltiplexer is fed into the
instrumentation amplifier which is configured so
that it can easily be strapped for single ended 0-5
volt inputs, single ended ±5 volt inputs, or differential 0-5 volt signals. Provisions are made for an
external gain control resistor on the amplifier. The
gain control equation is:

The control logic of the MP-20 was designed to
operate directly with an MCS-80™ system. When a
MEMR occurs and a conversion is initiated the MP20 generates a READY signal which is used to
extend the cycle of the 8080A for the duration of
the conversion. READY is brought high after the
conversion is complete which allows the 8080A
to initiate a conversion and read the resulting data
in a single, albeit long, memory or I/O cycle. The
conversion time of the MP-20 depends on the gain
selected for the amplifier. With no external resistor
(R = 00) the gain is two and the conversion time is
35 Jlsec. For R = 5 IOn the gain is:

G = 2 + 50kn
Rext

EXTERNAL
GAIN CONTROL

A,.
A"

A15

G=2+ 50kn
.51kn -

RESISTER

100

A"
A"

A,O
A 9
A 8
A 7
A 6
A 5

and the conversion time becomes 100Jlsec. These
settling times are specified in the MP-20 data sheet
and range from 35 to 175 microseconds. The
READY timing is controlled by an external capacitor. For a gain of 2 no external capacitor is
required but if higher gains are selected a capacitor
is needed to extend .the timing.

A.
A,

A 2
A ,
A 0

A schematic showing both the MP-IO D/A and the
MP-20 A/D connected to the 8748 is shown in
Figure 6. This configuration, which consists of
only four major components, gives an excellent
example of what modern technology can do for

Figure 5. MP·20 Analog Subsystem

1-5

inter

AP-24

IK
-5V

I~ l:>llt;: l:gJ::d~ I:s: li;l I!: I~
~.J'J>~t!-!tlt
~

~r----!I'

Ai2 1!..
Ail ~
1L

..

A;O

'I~

••

~

lKH
·.V

~

cit

?OpF

ffi

XTAl2

cit
••

B

59
5B

57

~

~

~
~
~

TO

56
'55

T,

iNT

----E.
-----'!

"

'0

Mes 48"~

'B

,
,•

P"

p,.

~

P"

ALE

PROG

P"

"
r!L-

"

-a
~

~

StN/DIFF

IN,

MfM'R

IN6

DO
0,

IN,

0;

IN,

03
0,

IN,

~'
.
~l~ ~

06

-i

,

006

,~

01 3
01,

DO,

01,

DO,

DO,

15

14

4

9602

12

9'

~

»

I,,7l

17

•

6
4

~

~

~

tj ~ ~

~

06

OUT 1

05

D.

MP 10

0,
Do

OUT.2

~~J';gl;tt

,
.

MCS-48™ Based Analo9 Processor

1-6

1161

,!,-

,.

-

-

9602

~

ANA LOG
INPU TS

~ ~

rnJ'l",.!"J"l'J"

_

611

5

~

BS1

fJ~
£,., ~1a8~""
2.

~

OS>

RESET

1

~-

DO.
10
8212
DO,

0,

PSeN
Vss
EA

DO,

,
• 0,

VDD
SS

l>

"'"

~

a ~~

DO

~D7

,

):0
W

~l!l

[" ,

01 6

P"

Vee

):>

t.J

~
72

R

DIB
01,
01 5
01,

_

~
~

~
~

INO

0,

~
~

+0-

IN,

~'

~ PIO

5

IN9
INB

1>

P'17

P"

"

Qur LO

MUX ENAB2

MD

P"
P21

----2!.
---22

.

1N1O

lKH

e

'SV

INn

.5V

'6

----'.[

IA IN HI

MUX OUT HI

P"

~ P,o

~
~
--------B

IN 3
'
INT?

P"

P2S
~ P,.

----1!

IN'4
Mp·20

lAIN LO

05

54

~

P"

~

IN.

60

--1

IN , S

MUX

15

Rli

..

BPO
IA OUT

II~

-:f-f~ol1,~
, XTALI

CQMPIN

R'

6B

6 MHz

"
,.

JI

-"'-

As 1.!..As ~

OBIN
OUTPUT SELECT

65

20pF

Ajj
A,

'1·2

".I

CD

"l

--.j

"-I

co

I\J
(t)

-

~

~

~

~

0

-

~}

ANAL DG
QUTP UTS

121

~.

'K

-.

AP-24

be written to following a reset to initialize its
internal logic) all channels involve some form of
data transfer.
As was mentioned previously, the MP-:!o was
designed to use the READY line of the 8080A.
Obviously this presents a problem since the MeS48 does not support a READY line (with its
attendant requirement of entering WAIT state).
The necessity of a READY input can be overcome
by performing a read operation to set the channel
address, waiting the required delay (35 J.lsec for a
gain of two) and then performing a second read to
actually obtain the data. The second read will read
in the data from the channel selected by the first
read irrespective of the channel selected for the
second read. Thus it is possible to use the second
read to set up the channel for the third read. Each
read can read in the current channel and select the
next channel for conversion.
The MP-20 is shown in Figure 6 strapped to input
16 single ended ±5 volts signals. Programs which
were used to test this configuration are shown in
Figure 7. The first of these programs uses the D/ A
converter to generate sawtooth waveforms by
outputting an incrementing value to the D/ A
converters. The second program scans the analog
inputs and stores their digital values in a table
located in RAM.

the system designer. The four components provide:
a.
b.
c.
d.
e.
f.
g.
h.
i.

An eight bit microprocessor
64 bytes of RAM
1024 bytes of UV erasable PROM
A timer/event counter
16 digital I/O pins
2 testable input pins
An interrupt capability
16 eight bit analog inputs
2 eight bit analog outputs

The MCS48 communicates with the D/ A and AID
converters in a memory mapped mode (i.e., it treats
the devices as if they were external RAM). By setting an address in either RO or R I and then executing a MOVX the software can transfer data between
the accumulator' and the analog I/O. When the
MCS48 executes the MOVX instruction it first
sends the eight bit address out on the bus and
strobes it into the 82121atch with the ALE (Address
Latch Enable) signal. After the address is latched,
the MCS48 uses the same bus to transfer data to
or from the accumulator. If data is being sent out
(MOVX oRj, A) the WR strobe is used; if the data
is being moved into the accumulator (MOVX A,
oRj) the RD strobe is used. The one shots on the
WR line are used to delay the write strobe of the
MCS48 to meet the data set up specifications of
the MP-IO.
In order to provide reset capability for the analog
devices without dedicating an I/O pin from the
MCS48, special addresses are used as reset channels.
Executing any MOYXwith anaddressofOXXXXXXX
will reset the A/D module; a similar operation with
an address of X I XXXXXX will reset the D/ A; a
MOVX with an address of OIXXXXXX will reset
both devices. All data transfers are accomplished
with the upper two bits of the address field equal
to 10. A summary of the addressing of the analog
devices is shown in Table I. Notice that except for
an initialization channel for the D/A (which must

LaC

OBJ

2: •••.•. -----.-----------------3 ; TEST PROGRAM FOR AHALOG OUTPUT
"':
THIS PROGRAM OUTPUTS A SAWS;
TOOTH WAVEFORM BY C1UTPUTING
6;
AN IHCREM(NTIHG PATTERN.

. UBI

II'.

Reset AID
Reset D/A

INPUT
Read p,ID Channel

.

";

-------

7; -------.-----------.---.------

INPUT OR OUTPUT

nnnn

.

9 ; ------18 ; EQUATES

Table 1. Analog Interface Addresses

001 1

SOURCE STATEf'lEtH

•,

ilIB3
11181

OXXX XXXX
X1XX XXXX

SEQ

12
13 (HITCH
'''' INITDT
15 MTCH'

,.

IB3H

; D/A INITIALIZATION CHANNEL

EGU

BSH
IBIH

: D/A INITIALIZATION DATA
lOlA DATA CHANNEL

EGU

17; ------------19 ; START OF TEST
19 ; ------------21
ORG
l11H

"

Ilill 2391
11112 BBB3
III" 91

22 START:
23
24
2S

IllS BBBI
B11717
111B 9.
111192415

26 LOOP;

MOV

2.
"
2.

M!lVX

"

(HD

31

nnnn

EGU

/'IOV
MOV

.J!!IlVll

ONe

.....

; IHITIALIZE O/A
A,#IN/TOT
RI,ttIHITCH
@RO,A
I TEST lOOP-OUTPUT SAWTOOTH
RI. ItDATCH
A
@tRI.A
lOOP
; [HO or PROC.RAM

OUTPUT

1 01 1 0001
101 1 0000
101 1 0010

Initialize D/A
Write Channel 1
Write Channel 2

All mnemonics copyrighted © Intel Corporation 1976.

Figure7a. D/A Exercise Program

1-7

inter
LaC

OBJ

AP-24

SEQ

The above calculation, although conceptually
simple, would be time consuming and would
severely limit the possible output frequencies which
could be obtained. As an alternative to calculating
these values in real time, the values could be precalculated off line and stored in a table. Upon each
interrupt the MCS-48 would merely have to retrieve
the appropriate value from the table and output
it to the D/A converter. the MCS-48 provides a
special instruction which can be used to access
data in a table. If'the table is stored in the last 256
bytes of the first kilobyte of MCS-48 memory
then the table lookup can be performed by loading
the independent variable (time in this case) into
the accumulator and executing the instruction .

SOURe[ STATEJI£HT

•,
2
3

-------------------------------. ______ _
T[ST PROGRAM fOR ANAlOG IHPUT
TH"IS PROCiRAf'I SCAMS THE INPUT CHAtttElS
AHD STORtS THE R[ADINGS IN A TAkE
STARTltIG AT IU'f.
---------------------------------------

•
S

•
•
7

9 ; ------I' ; EQUATES

•• 2.

....
,,"5
.lIr

""

;

.------

138JF"f
14 P1AXCH

IS AIHCH
IS TlCIC

EOU
EOU
EOU
EOU

IBIH

i START OF 9JF'f[R
; HO or ANAl.OG I HPUTS
; BAst ADDRESS OF ANALOG INPUTS

S

; EXECUTION TlfIE

2 ••
IS

or

DJN2

"

18 ; -------------

"

..

1,lIlI92f

"'2 IB'f

"'48BBF"
"16 8.

..
..

19 ; START Of TEST

2' ; ------------23 START:

2S
26
27

.
.
20

"17 scla

"19 fet9

"'8 ca
",e 8.
'"0 AI

"IEG
".F SCI..
11il EC1'

1"3 [Bl8
IllS 2"'''

ORG

22

3t
31
32 LOOP:
33
3S
36
37
30
39

......
.....
.,

'"'"

"""
"'"

l11H
J 5[nP TO SCAN ANALOG UtPUTS
Ii 1 • "BlFr .I'IAXCH
R3,tlMAXCH
R,.#(AIHCH.I'!AX(;H)

; SEl.ECT CHAH/'IEL 'S

'"""

A,ORI

"'"

li!4, "",/TICK

DJItZ
DEC

; WAIT

••

'"""

A.OR'

"'"

.,

DEC

»". MICROSECOHDS

MOVP3 A,@A

Ii",$
;

~

SCAN AHALDGS

This instruction uses the initial contents of the
accumulator to index into page 3 of program
storage. The location pointed to is read and the
contents placed in the accumuhitor. If (as is often
the case) a table of fewer than 256 entries is
required, then the table can be located in any page
of program mel110ry and the instruction:

; GET OATA

; IOJE INTO 9JF'FER
ORI,A
j

D£CRtr:£HT BUF'fER PO I NT

; PAD 2. I'IJCROSEC

"'"

R4,#2'/TlCK

OJH2

R"',$

OJHZ

R3,LOOP

JI'P

START

! LOOP UNTIL DCIHE
! REPEAT TEST F'OREVER

; END

or

MOVPA,@A

PRQGRAI'I

EHI)

can be used to retrieve data from the table. This
instruction operates in the same manner as does
the previous instruction' except that the current
page of program storage is ass4med to contain
the table.

Figure 7b. AID Exercise Program

If it is possible to devote slightly more of the
microprocessor's time to tile table look up process,
then a much smaller table can often be utilized by
taking advantage of interpolation to determine
values of the function between values which are
actual entries in the table. As all example of this

TABLE lOOKUP TECHNIQUES
111 the previous section the interface between analog
I/O devices and the MCS-48™ was discussed. In
many applications involving analog I/O one quickly
finds that nature is inherently nonlinear, and the
mathematics involved in 'linearizing it' can tax the
cOJ11putational power of the microprocessor, particularly if it has other tasks to perform. Problems
of this nature are good candidates for the use of
tables.

FLOWMETER

As an example of how tables can be used as part of
an analog output scheme, consider a system which
requires an MCS-48 to output a variable frequency
sinusoidal waveform. One method of performing
this function would be to use the timer to generate
an interrupt at a fixed rate of 256 times the desired
output frequency. At each interrupt the appropriate
vahieof the sine function could be calculated from
the Maclaurin series:

----1
FLOWMETER

AD

----l
FLOWMETER

.
' x3
x5
x7
Sm x = x - 3! + 5! - 7T

MCS48

LJ

(_1)k x 2k +1
(2K + I)!

Where K is chosen to be large enough to provide
th~ required accuracy.

All mnemonics copyrighted

LJ

@ Intel Corporation 197ft

Figure 8. Flow Monitoring System

1-8

COFltTROL
PANEL

inter

AP-24

process consider the hypothetical system shown in
Figure 8. The purpose of this system is to measure
the flow through the three pipes, add them, and
display the total flow on the control panel. The
system consists of three flow meters which generate
a differential voltage which is some function of
flow, an A/D system with at least three differential
inputs, an MCS48, and a control panel. The
schematic sho\Vn in Figure 6 could easily become
part of this system, with the spare digital I/O of
the MCS48 used as an interface to the control
panel. The simplicity of this system is clouded by
the flow transducers, which are assumed to be not
only nonlinear but also to require individual calibration (this is not an unreasonable assumption for
a flow transducer). By usinga table look up process
and an 8748 the flow transducers can be calibrated
and the results of the calibration tests stored
directly in tables in the 8748. (The 8748 has a
PROM in place of the ROM of the 8048 and thus
makes such 'one off' programmin, oractical.)
The results which might be obtained from calibrating one of the flow meters is shown in Figure 9.
The results are plotted as gals/hour versus the
measured voltage generated by the transducer. The
voltage is shown in hexadecimal form so that it
corresponds directly to the digital output of the
analog to digital converter. The flow required to
generate seventeen evenly spaced voltages (OH-l bOH
in steps of 10H) has been measured and plotted.
This information is shown in tabular form in
Figure 10. It is necessary to generate a program
which will convert any measured input from OOH
to FFH into the flow in units which can be interpreted by a human operator. This can easily be
done by simple interpolation.

The eight bits of independent variable (voltage) can
be looked on as two four bit fields. The most significant four bits (7-4) will be used to retrieve one of
the table values. The lower four bits (3-0) will be
used to interpolate between this value and the
value retrieved from the next higher location in lhe
table. If the upper four bits are given the symbol I
and the lower four bits the symbol N, then lhe
interpolation can be expressed as:
F(x)

= F(I)

+

ii,

[F(I+I) - F(I)]

Where x is the measured voltage and F(x) is the
corresponding flow.
If, as an example, the transducer voltage was
measured as 48H then the flow (ref. Figure 10)
would be:
F

= 30

+

8
16

(34-30)

= 32

A subroutine which implements this caiculalJIIII is
shown in Figure II. Before it is called the indl·I"·1I
dent variable (V) is placed in the accumulator and
register R I is set to point at the first value in the
table. Aside from simple additions and subtractions
the only arithmetic required is to multiply two
values and then divide them by 16. The multiplication is handled via a subroutine which is also
shown in Figure II. The division by 16 can be performed by a four place right shift followed hy a
rounding operation. The routine shown will handle
a monotonic increasing function of a single independent variable. Fairly simple modifications are
required for nonmonotonic functions. Functions
of two variables can be handled by interpolating on
a plane rather than along a straight line. Although
this is more time consuming, requiring an interpolation for each of the independent variables and
a third to in terpola te the final answer, it still
provides a simple means of quickly calculating the
required function. The use of tables can offer a
powerful technique for function evaluation to the
designer.

60,------------------

'0

RECEIVING SERIAL CODE-BASIC
APPROACHES
Many microprocessor based systems require some
form of serial communication. Serial communication is extensively used because it allows two or
more pieces of equipment to exchange information
with a minimal number of interconnecting wires.
The minimization of interconnecting wires results
in simpler, cheaper, interconnects because fewer
(or smaller) cables and connectors are required.
Since the required number of drivers and receivers
required is reduced, it can become economically
feasible to provide much higher noise immunity

10

Figure 9. Flow Calibration Curve

TRANSDUCE R , . . - , - , - , - - , - , - , - , - , - - , . - - , . - - , . - - - - , - - - - - , - - , - - , - - - . - - .
VOLTAGE IHfX! 00 10
MEASURED FLOW

HHHH-I-I-I-I-I-+-+-+-+-+-+-+-1

IGA l HOURI '----''----''----'--'--'--'--'---'---'---'-----'-----'----'-----'-----'-----'-----'

Figure 10. Tabulated Flow Data

1-9

inter
Loe

OBJ

AP-24
. .0

SOURCE. STATEMENT

I

LaC

•••••••••.••••••••••••••••••••••••••••••••••

.•, ...........................................

OBJ

I"C 83

"10 BElie
,,,r
BAl.

9 1 EQUATES

'11'

...2
.113

'11'"

I I : ':'-----11
12 RXI
EOU
13 AXI
EOU
,,, AEX
EQU
15 COUNT
EOU
16 TEI'F
EOU
17

"21 97
R'
R'
R,
R3
R'

j POINTER I
I POINTER!
I E:xTENSIOH

or

A REGISTER

.,••

"22 1228
.,204 2A
112567

; COUNTER

.,26 2A

; IT"" STORAGE

112767
"28 EB22
112A 83

21; -------------

11,. IBI'"

1,.2 Bill
.,1431
IllS "17

111669

•,,7 A9

1118 E3
111929
IliA 17
111B E3
,tiC 37
111069
111E37

"282A

ORO
'3
2'1 APPROX: fI10V
'5
26
i'1OII
28
XCHD
",",P
29

.,

31
31
3•
33
3<
35
36

3'

.,

.....,
..,..
3B

II'H

112C 61

; POINT RXI AT TEI'F
RXI.#TEfIF

"2067

; TEI'P-N AND IfH

; A"P AHD IFH
@RXI,#I
A,ORXI

111B 69

••••
51

A,RXI
RXI,A

AIlD
CPl

A,OA
A,AXl
A
A,@A

A
A,AXl
A

CALL

'''IT

i'1OII
XCHD
SWAP
XCH
JB3
XCH

Rxt,#AEX
A.@iRXI
A
A,AEX
ADJUST
A,AEX
A,AEX
A
; A-A. TABLE(PJ
A,RXl
: AETURN

IHe

54

ADD

"'"

66 LOOPA:

CLA

68 LOOPB:
69
71
71
72

JB.
XCH
RRC
XCH
RRC

63 I>IUl.T:

f'IDV

",.
7S

DJN2
RET

77 ssli>1:
78
79
81
81

XCH
ADD
ARC
XCH
RRC

B3

DJNZ
RET

8.

.
8'

.,

; SET UP COUNT AND AEX
COUNT, #8
AEX.#I
; CLEAR CARRY

"1>1

; If MUlTIPLIER (I) () 1 THEN SflIFT PRODUCT

A,AEX
A
A,AEX
A
; LOOP UNTIL DONE
COUNT,LOOPB
; ELSE ADD f'>lJLTIPLIER AND SHIFT PRODUCT
A,AEX
A,@IU.
A
A,ArX
A
; LOOP' UNTIL DONE
COUNT,LOOPA

89 ; --------------------'

1381

; A-H-A/16

51 ADJUST: XCH

.5

87 I --------------------sa ; TABLE TO TEST PROGAAM

: A-TABLE (P.U-TABLECPJ

CPl

..,6'

8!i

; RX ,·TABlEIULTIPLY
61 ; --------

5

I ...

56

57
58

APPR[]X
AT ENTRY RI POIHTSAT TAkE
A HAS IHOCPEHOENT IIARIAB..E

8 I -------

SEO

1381 II
138t IA
1382 16
1383 lA
138'" lE
138522
1386 26
138728
1388 29
1399 2A
138A 2B
13aB 20
I38C 31
I3&D 31
I38E 35
l3Bf 38
1391 3F

91

ORG

93 TABl-E:

DB

94

DB

••

.,.
9S

DB

96

DB
DB
DB
DB

99

"'
"'
"'
113

".

1IS
'86

'87

"8
11.

'"
"'

DB
DB
DB

DB
DB
DB
DB

DB
DB
DB

.

38IH
; THIS TABlE: IS FROM FJG HI

11

••

26

31

.
34

38

.,

.,••

..
4S

.8
53
56

.3

EMD

Figure 11. Table Lookup With Interpolation

eighth data bit usually consists of even parity on
the remaining seven data bits; for the purposes of
this discussion the eighth bit will be considered
only as data. A m'inor variation of this fonnat
deletes one of the STOP bits. An algorithm which
might be used to sample serial data under software
control using a microprocessor is shown in Figure
13. Th~ basic intent of this algorithm is to minimize the effects of distortion and transmission rate
variations on the reliability of the communication
by sampling each data bit as close to its center as
possible. Upon entry to this routine the software
first samples the incoming data in a tight loop until
it is sensed as a MARK (logical one). As soon as a
MARK is detected, a second loop is entered during
which the software waits until the received data
goes to a SPACE (logical zero). The purpose of this
construction is to detect as accurately as possible
the leading edge of the START bit. This instant of
time will be used as a reference point for sampling
all of the following bits in the character. After
sensing the leading edge of the START bit a wait
of one half the expected bit time is implemented.
The period of the incoming signal is called P for
convenience. At the end of this wait the serial line
is tested-if it is MARK then the START bit was

with more sophisticated (and expensive) line
tenninators. The final, and usually most persuasive, argument in favor of serial communication
is that it may be the only method available to
accomplish the job. The obvious example of
this is telecommunications where it is necessary
to encode parallel infonnation into serial fonnat
in order to communicate via the telephone network. The intent of this section is to show how
the facilities of the MCS-48™ can be brought to
bear on the problem of serial communication.

Figure 12. Serial ASCII Code

Probably the most common form of serial communication is that used by the obiquitous Teletypeserial ASCII. This fonnat, shown in Figure 12, consists of a START bit (0 or SPACE) followed by
eight data bits which are in tum followed by two
STOP bits (I or MARK). In actual practice the
All mnemonics copyrighted © Intel Corporation 1976,

1-10

inter

AP-24

the processor will spend only a I OO~secs or so processing data and the rest of the 100 millisecs waiting to do the processing at the right time. This lack
of efficiency (approximately 0.1 %) in the utilization
of processing power is why devices such as the
8251 USART find broad application in microprocessor systems.

LOC

OSJ

5ClIRCE STATEMENT

5EO

";
, , ..............................
,,2 ,,,
SIf'FLE SERIAL II'IPUT
.THIS CODE ASSll'IES RltO IS
CONNECTED TO PIN TI

5 ,
6 ; ••••••••••••••••••••••••••••••
7
8; _______
'3 ; [QUATES

11:

"liZ
IU8
8182
I,M
lUI

"

-------

12 COUNT
13 BITHO
14 DlVH!

,.

15 DLYLD

"

,ou
,ou
,ou
'ou
OR.

"
8

IA4N

: LOOP, UNTIL IUD-MARl(

19 SEAIN: JNTI

; HOW LOOP UHTlL RXO-SPACE

20

.,123612

JTO

CALL

HBIT

a116 3611

"
"

25
26

JTO

SER(H

1118 BIllS

27

"~

"11'" 341C

'IIA 341C
.11C341C

22
23

28
29 LOOP:

""32
,.
,

.

: WAIT 112 BIT TIME

CALL

33

"IEEAIS
'11897
• ,11 3614
1,,3A7
811483

3S

37

38 EXIT:

DJHZ
CLR
JT.
CeL
R'T

.11597
"'62619

41 LOAD:

"18 A7
"1967

"

IliA 24'A

43 LLLA:

"0. The
USART requires a reset of approximately 6 CLK
periods so DELAY is chosen to be I which ensures
adequate reset timing. Note that for delays this
short, NOP instructions could also be used to time
the pulse.

19968
MH,

The data clocks required by the USART are provided by the modem if the USART is operated in
the synchronous mode. In the more common
asynchronous mode, however, these clocks must
be provided by circuitry associated with the 8251.
The 5.9904 MHz crystal was chosen because the
resulting 1.9968 MHz clock to the USART can be
evenly divided to provide transmit and receive
clocks to the USART. Assuming the USART is in
the x 16 mode (i.e. it requires data clocks 16 times
the baud rate) the 1.9968 MHz signal can be divided
by 13 to generate the proper clock rate for 9600
baud operation. This 9600 baud .clock can be
further divided to give 4800, 2400, 1200, 600, and
300 baud signals. The 1200 baud signal can be
divided by II to give a 109.1 baud signal which is
within I % of the 110 baud required by Teletypes.

'Install Jumper for 110 Baud OperatiOn (-111

Figure 15. MCS-48™ to 8251 Interface

necting the CLK signal of the USART to the TO
pin of the MCS-48. The TO pin of the MCS-48
can either be used as a directly testable input pin
or it can become, under program control, an out. put pin which oscillates at one third of the crystal
frequency. (Note that once this pin is designated
by the software to be ali output it will remain so
until the system is reset.) In Figure IS the crystal
frequency is 5.9904 MHz so the clock provided to
the 8251 is 1.9968 MHz, which conforms to its
specifications.
The initialization signal to the USART (RESET) is
provided ·programmatically by manipulation of bit
5 of port 2. It was-necessary to place the reset of
the 8251 under program control for two reasons.
The first reason is that the MCS-48 does not supply
a reset signal to other devices. The reason for this is
that it was felt to be more useful to provide another
pin of I/O function instead ofa RESET OUT signal

The MCS-48 communicates with the 8251 in a
memory mapped mode (i.e. as if the 8251 were
external RAM). The instructions available to do
this are MOVX aRj, A which stores the contents of
the accumulator at the external RAM location
addressed by Rj U=O or I), and its complement,
the MOVx' A, @ Rj instruction which moves data
from the external RAM into the accumulator.
Since the MCS-48 multiplexes addresses and data
on the same eight bit bus an external latch would
be required in order to address the USART with
1-12

AP-24

Lac

DIlJ

SEQ

to add the circuitry necessary to use RO or R I to
address the peripheral devices. The circuitry which
has to be added to Figure 15 in order to make use
of RO or RI to address the USART is shown in
Figure 17. Note that only the changes to Figure 15
are shown. The additional component required is
the 8212 eight bit latch. This latch is loaded, whenever a valid address is on the bus by the Address
Latch Enable (ALE) signal provided by the MCS48. During an ex ternal read or wri te cycle this
address is used to address the 8251 in a linear
select mode. In the circuit shown, the 8251 will be
.selected by any address with bit I a logical zero
(XXXXXXOX) and the selection of control or data
transfer (C/O) will be based on bit zero of the
address obtained from RO or R I. Figure 18 shows
the program of Figure 16 modified to utilize the
addressing inherent in the MOVX instructions.

SOURCE STATEMEMT

S[R[ALT[ST
TH[S

cooe:

ItHIALIZES TI1E USART

AND TRANSMITS AN IHCREMfNTlNG
PATTERN. HARr:wAR£ SH~ IF riG 15.

7; ---- __ _
8; EQUATES

9; -------

liZ'

ue,

UDF

UCE

1117F

11"
"Bf

"

11 MCLR

12
13
14
15
16

DLV
ueON

[au
[au

lilH
81H

[QU

[au

BeEH

; USAIH f'1JD(

eMD
STAT

[IlU
£QU

211,

; USART CMt)

7FH

(au
[au

; USAInSTATU5
; TEST VALUE

'SFH

; CHAt1VES eND TO DATA CHANNEL

ORO

lUSH

22
23 TEST;

Etne

eLK

24

ORL

2S

"""

P2,:tMCLR
R2,:tDLY
R2,LOOP

17 VAL
18 MASK

; TURHOHCLDCK

21

8187 9ADF

8119237F
81883A

S18el3eE
lilliE 98
IIUF2321
8111 9&

; USART RESET DELAY

; USART CONTROL ADDRESS

/'{JOE:

8188

8118 75
8!118AZI
ill13 BAil
illllSEAIS

; USART RESET ADDRESS

26 LOOP:
27

,.

; AHDR[SET USAIH

DJHZ
ANL

38

"
,.

P2,#(HOTMCLlU
; SELECTUSARTCOHTROL
A,#UCON

29

DUlL

32
33

MOVX

35

MOVX

3.

.

P2,A
SEND 1'l]D£ AND CCI'T'1AND
A,#MOD£
@RS,A; (CONTENTS OF Re UN[I'F'ORTANT)
A,#CMD
@RiI,A
; [)(] FOREVER
SELECT UsART STATUS
IF TXRDY-' THEN

3S

1112237f
1114 3A

042
043
0404 TLP;
045
046

lIlA 9AB(

....

""G
9'
8110 19

51
52

ill1s 88

111667
11117 [612
1119 F9

8"[2412

OUTPUT VALUE;
INCREMENT VALUE;
END;

P2,A
A,@RB

;

(CONTENTS OF RS UNII'F'ORTANT)

INC

53

JI'P

END

os,

'0

A

AHL

os,

13

22

'8

JHe

M!JVX

'I~
ALE ~-------"'l

A,#STAT
OUTl

"

55

'5V

END;

.,

"

WR~----------------------~

WR

R-a

00,

A,VAL
P2,#MASK
@RS,A
VAL
TLP
; END OF PROVRAM

16

U748

MO

00 8

DO,

I-

0'6

00 6

015

005

III-

00 4

I-

00 3

I-

~ DO,
------2

8212

0',

01 8

0'3

~3 00,

00,

DO, ~
DO, ~

8251

cs
c/o

D,~-+-t~+-~r+----------~ D.,
06~-+-r1-~~~-----------; 08 6
D5r---~1-~~~-----------; 08 5

D4~----~~~~-----------; 08 4

D3~------~~r+-----------; 08 3

D,r---------+-r+----------~ 08,
0, ~--------~~----------_1

Figure 16. 8251 Test Program

D.,

DO~----------~----------_1 0. 0

L..-_ _- '

RO or R I. In order to Immmize the circuitry in
Figure 15 an approach utilizing some of the I/O
pins of the MCS-48 to address the 8251 was chosen
instead. By connecting the chip select (CS) input
of the 8251 to bit 7 of port 2 (P27) and similarly
connecting the C/O address line of the 8251 to bit
6 of port 2 (P26) it is possible to address the 8251
without using RO or RI. The instruction sequence
to access the 8251 is to first reset P27 and set P26
to the appropriate state, use a MOVX instruction to
perform the appropriate operation, and then
finally set P27 to deselect the 8251. As a concrete
example of this addressing, Figure 16 shows the
code necessary to initialize the 8251 and output an
incrementing test pattern on a status driven basis.
If more than one 8251 were to be added to the
MCS-48, or if other types of peripheral circuitry
would be required (e.g. an 8253 timer to generate
the data clocks) it would probably become desirable
AU mnemonics copYrIghted © Intel Corporation 1976.

'-_ _- - '

Figure 17. Modified MCS48 to 8251 Interface

RECEIVING SERIAL CODE-A MORE
SOPHISTICATED ALGORITHM
Although the USART does an admirable job of
performing the serial I/O function for the MCS48™, there are some situations where it can not be
used. These situations may be caused by economic
factors, such as an extremely cost sensitive design,
or because the code which must be utilized cannot
be accommodated by the USART. An example of
of such a code will be discussed later. Recall that
the principal objection to the approach to serial
input shown in Figure 13 was that it consumes
much of the processor's power by merely spinning
in loops in order to wait preset time delays.
1-13

inter
LaC

AP-24

SEQ

OBJ

interrupt occurred. If the serial line has returned to
the MARK state, a status flag is set to indicate an
error and a return is made. On subsequent interrupt
detection, the data is sampled, the timer is reinitiated, and control is returned to the program which
was running when the interrupt occurred. When
the last (Le. STOP) bit is detected a completion
flag is set and a return is made to the program
running when the timer overflow occurred. By
periodically, checking the error and completion
flags the running program can determine when the
interrupt driven receive program has a character
assembled for it.

SOURCE STATEMENT

•........... __ ._----_._------------S[RIALT(ST
THIS CODE INTIALIZES THE USAAT
AND TRANSMITS AN INCREMENTiNG
"

PATTERN. HARDoIARE SHCIoIH IF FIG 17.

5
--------------------.--.----------6
7: ------8: EQUATES

9; -.-----

"

fl21

[DU

211'1

1 USART RESET ADDRESS

12 Dl..V

[QU

1183
liCE
1121
.111

13 UCON
14 I1JDE

[au

.,H
.3H

1 U5ART RESET DELAY
1 USAAT CONTROL ADDRESS

[DU

ICEH

; USART I'IDDE

IS Cf'ID
16 STAT

[QU
[OU

21H
13M

1111
1111

17 VAL

[DU

18 DATA

[OU

III
81

; USAATCfIID
; USART STATUS
I TEST VALUE
I USART DATA ADDRESS

21

ORO

1nM

EHTI
DRt.

eLK

"

''',

P'CLR

,.

1111

21

22,
23 TEST:
2<1
25

111. 7S
1111 8A21l

1113 BAI'
1115 EAtS

I TURN ON CLOCK

; AND RESET USART

1'IlII

26 LOOP
27

DJNZ

"17 SADF'

2.

11.92313

29
3'

1'IlII

31
32

1'IlII

11109'
1,.[ 2321

33

1'IlII

34
35
36
37
38
39

MOVX

.,ta2leE

"11 9,

AtiL

MOYX

"

""

1111 2313
111381
.,1467
'115 ES1'
'117 F'9

'118 BBl'
lilA 9.
",S 19

43 TLP:
44
45
46

MOV
MCJI.IX
RRC
JNC

.,
48
51

MQV
MOV
f'lQVx
INC

51

"'"

49

I"C 24"

52
53

P2,"MCLR
R2,#DLY
R2,LOOP
P2,It(NOTI'1CLR)
; SELECT USART CONTROL
A,ItUCON
; SEND !"ODE AND CCJ1'1AHD
A,#I'IJOE
ORI,A I (CONTENTS Of RI UNIMPORTANT)
A,ltCf'ID
@RI,A
; DO FORE\lER
SELECT USART STATUS
If TXRDY-1 mEN
!Xl;
OUTPUT VALUE;
INCR(II£HT VALUE;
END:
;
END:
A,#STAT
A,@RI : (COHTENTS OF RI UNIMPORTANT>
A

TIMER
OVERFLOW

TLP
A,VAL
RI,#DATA
ORI,A

VAL
TLP

; END Of PROGRAM

END

Figure 18. Modified 8251 Test Program

The timer resident on the MCS48 provides a solution to this problem. Instead of spinning in a loop
the program can set the timer for a given interval,
start it, and proceed to other tasks. When the timer,
overflows, an interrupt will be generated to notify
the software that the present time period has
elapsed. An e~tension of the algorithm of Figure
13 which uses the timer in this fashion in shown in
Figure 19. This algorithm is identical to the preceding one ,up until the detection of the leading edge
of the start bit. At this point the timer is set to one
half of the bit time (P) and a return is made to the
calling program which can start additional processing. At the completion of this time interval a
timer overflow interrupt is generated. When the
first interrupt is detected, the serial line is checked
to ensure that it is in a spacing condition (valid
START bit). If it is, the timer is set to P (to sample
the middle of the first data bit) and a return is
made to the program which was running when the,
All

mnemon~cs

copyrighted @ Intel Corporation 1976.

Figure 19. Improved Serial Input Routine

Using the timer to implement time delays as shown
in Figure 19 results in considerable savings in
processing time; two p,roblems remain, however,
which must be solved before an adequate software
solution to the problem ofreceiving serial code can
be found. The first problem is that even though the
delays between bit samples are implemented via
the timer rather than program loops the loop construction is still used to detect the leading edge of
1-14

AP-24

the START bit. Although this results in the waste
of processing power, the second problem is even
more serious. For longer messages the required
accuracy of the clocks becomes more and more
stringent. Using the sampling technique discussed
a cumulative error of one half a bit time in the
time at which a bit sample is taken will result in
erroneous reception. The maximum timing error
which can be tolerated and yet still allow proper
detection of an II bit ASCII character is then:

Both efficient detection of the start bit and increased timing accuracy can be obtained if the MCS48
can detect edges on the incoming received data
(RxD). A hardware construct which allows this
is shown in Figure 20.
The received data (RxD) is Exclusive NORed with
bit seven of port two and fed into the TEST (T I)
pin of the MCS48. By manipulating P27 the program can now cause TI to be either RxD or RxD.
(If P27 = I then TI = RxD; if P27 = 0 then TI =
RxD.) Note that not only can TI be tested directly
by the software but that it is the input which is
used when the MCS48 timer is in the event counter
mode. The significance of this will be discussed
later. The relationship between TI, P27, and RxD
is given by the Boolean expression:

O.SP
O.s*BIT TIME
Emax = CHARACTER TIME - TiP = 4.5%
where P is the period of single bit. The corresponding calculation for a 32 bit character yields:
Emax =

~i~

= 1.6%

TI

Since this calculation does not allow for distortion
on the signals, it is obvious that either extremely
stable clocks will be required or a more tolerant
algorithm must be devised. This problem is particularly serious at relatively high baud rates where
the resolution of the counter (80J.lsecs with a 6 MHz
crystal) becomes a significant percentage of the
period of the received signal. At the 110 baud rate
of the Teletype the 80J.lsec resolution of the clock
allows a maximum accuracy of 0.33%; at 2400
baud this figure is reduced to 3.8%.

PROG

T1

Figure 2 I flowcharts a means of utilizing this hardware construct to avoid the necessity of wasting
time in program loops to detect the leading edge of
the start bit. The receive operation is initialized
when the program desiring to receive serial data
calls the INIT subroutine (Figure 2Ia). Since INIT
is going to manipulate the timer the first action it
performs is to disable the timer overflow interrupt.
Its next step is to set P27 to a logical 1. Setting
P27 in this manner causes the TEST 1 input to the
MCS48 to follow RxD. By setting up the receive
circuitry in this manner a high to low transition
will occur on TEST 1 when the RxD goes from
the MARKING to SPACING state (Le. the START

WR

ALE
P17

P27
P26
P25
P24
P23
P21
P20

P16
P15
P14
P13
P12
Pll
PlO

TO

°7
06

Vcc
V OO

°5
04
03

ss
PSEN

°2
°1
DO

Vss
EA

-=

• RxD + P27 • RxD

AD

tNT

RxO

+5V

= P27

}~'"
},"

.::r::

Figure 20. Detecting RxD Edges

Figure 21a. Interrupt Driven Serial Receive Flowchart

1-15

intJ

AP-24

bit, occurs). By setting the timer to OFFH and
enabling it in the event count mode, the, .INIT
routine sets up the, MCS48 to generate a timer
overflow interrupt on the next MARK to SPACE
transition of RxD (the TEST I input doubles as
the event counter input). Before returning to the
calling program the INIT routine sets a flag (RDF)
which will be cleared by the receive program when
the requested receive operation is complete. INIT
also sets a value into a register called BCOUNT.
The receive program interprets BCOUNl as follows:

Number of bits remaining
to receive
If set indicates that the
ST A RT bit has not yet been
detected

NO

__2 -__________~~____~~

If set indicates that the
START bit has not yet bee'n '
verified

Figure 21 b. Interrupt Driven Serial Receive Flowchart

In order to request the reception of the II bit
ASCII code INIT would set BCOUNT to 1100101 lB.
The start bit has been neither verified nor detected
and II bits (lOIIB) are required.
After INIT is called the reception of the individual
serial data bits will proceed on an interrupt driven
basis until a complete character has been assemble~.
When this occurs the interrupt driven program will
set the RDF (Receive Done Flag) to a zero to indicate that it has completed the requested operation
and then terminate itself. The procedure which is
used to accomplish this is shown in Figures 21 b
and 21c.
Since all operations of this program are the result
of the occurence of a timer overflow interrupt, it
is necessary to briefly review the interrupt structure
of the MCS48, There are two sources of interrupt;
an external interrupt which is the result of a logical
zero signal applied to the INT pin of the MCS48,
and an internal interrupt which is caused by a
timer overflow condition. The timer overflow
occurs whenever the timer is incremented from
OFF H to zero whether it be in the timer or event
count mode, When one of these events occurs the
hardware in the MCS48 forces the execution of a
CALL. This CALL has a preset address of location
3 if it is due to the external interrupt and location
7 if it is due to a timer overflow. If both of these

Figure 21c. Interrupt Driven Serial Receive Flowchart

1-16

AP-24

RETR is executed. Note that since the state of
the flip flop which selects RB I is saved as part of
the PSW, the execution of RETR automatically
selects the register bank which was active when
the interrupt occurred.

events occur simultaneously the external interrupt
will take' precedence. The CALL automatically
saves the contents of the program counter for the
running program and its PSW (program status
word) on a stack the hardware maintains in RAM
locations 8-23. Although the hardware saves the
program counter and PSW, it remains the responsibility of any interrupt driven software to make
absolutely certain that it does not modify any
memory locations or registers which are being
used by the main program. The most convenient
way of ensuring this in the MCS48 is to dedicate
the second bank of registers (RB 1) to the interrupt
driven program. One of these registers has to be
used to save the accumulator (which is not part of
the register bank) but seven registers remain;
including two which can be used as pointers to the
rest of the RAM (RO and R I). Note that if this
approach is taken then these registers have to be
allocated between the program which services the
external interrupt and the one which services the
timer overflow. This problem is somewhat alleviated
by a hardware lockout which prevents the timer
overflow interrupt from interrupting the external
interrupt service routine and vice versa. This is
implemented by locking out new interrupts between
the time an interrupt is recognized and the time a
RETR instruction is executed. The RETR instruction is like a normal RET (return from subroutine)
except that the PSW as well as the program counter
is restored. The RETR instruction can be very
much thought of as a return from interrupt instruction in the MCS48.

If BCOUNT [7] is still set when it is tested, control is passed to START (Figure 21c) where bit 6
is tested to determine if the START has been
detected yet. If BCOUNT [6] is set it indicates
that this is the first occurrence of a timer overflow
since the receive process was initialized by the
INIT subroutine. If this is so, the program assumes
that the START bit has just started and therefore
it sets the timer to one-half of a bit time (1/2 P),
starts the timer in the timer mode, and clears
BCOUNT [6] to indicate that the START bit has
been detected. The next overflow will again result
in the execution of the program in Figure 21 band
again BCOUNT [7] will be found to be set. This
time, however, BCOUNT [6] will be reset and the
program will know that it should test the START
bit to ensure that it is still a SPACE. This test is
performed and if successful the timer is set for a
bit period P and BCOUNT [7] is reset so that on
the next occurrence of a timer overflow the program will know that it should start assembling
serial bits into a character. If the test is unsuccessful, the subroutine INIT is used to reinitialize the
receive program. In either case control is passed to
EXIT where a return from interrupt mode occurs.
This receive program, listings of which appear in
Figure 22, allows the reception of serial characters
transparently to the main running software. After
INIT is called the main program has only to check
RDF periodically to find out if there is data in the
buffer for it. It would be fairly easy to 'double
buffer' this operation by providing a buffer which
the receive program uses to deserialize the incoming code and a second buffer to store the assembled
character. If the program would reinitialize itself
upon completion, the reception of a string of
characters could proceed in much the same way as
it would if a status driven USART were being used.

The receive program under discussion uses register
bank I in the manner described. Whenever a timer
overflow occurs (e.g. on the next MARK to SPACE
transition of RxD after INIT is called), control is
passed (by the hardware generated CALL) to the
point labled TIMER OFLO in Figure 21 b. This
program segment immediately selects register bank
I (RB I) and then saves the accumulator (A) in a
location called ATEMP which is actually R7 of
RB I. The program then tests bit seven of BCOUNT
(R6 of RB 1) to find out if a START bit has been
verified (Le. the edge of the START bit has first
been detected and then verified to still be a SPACE
one-half a bit time later. If BCOUNT [7] is a zero
the START has been verified and the program proceeds to set the timer to P (the period of the serial
bit), get the current serial data into the carry bit,
and then shift the carry bit into a buffer. After
saving the data the program decrements BCOUNT
and tests it for zero. If BCOUNT is zero the receive
operation is complete so the program sets RDF to
a zero and disables timer overflow interrupts.
Whether or not BCOUNT is zero, control is passed
to EXIT where A is loaded with ATEMP and a

Although this program solves the first problem of
software controlled reception (lack of efficiency)
the second problem-sensitivity to frequency
variations-remains. An example of a code which
would be susceptible to this problem is the 3 I ,26
BCH code commonly used in supervisory control
systems. (A supervisory control system is, in
essence, a remote control system which allows a
human or computer operator the control of a
system via a serial communications link.) The BCH
codes are used because of their error detection
capabilities and are a class of cyclical redundancy
1-17

inter
,'DC

OBJ

Ap·24

SOURCE 5TAT£I'£HT

. .0

•• 23 FE
"2~ 0237

........................................
SERiAl INPUT U5IHG,TH[ I'ICS-48
THIS CDtlE ASS\K.S HARtIoIARE

•
7

........................................

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1128 2307

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OS

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A,#-P
T,A
T
P2,#7FH
I

A,ElCOUtiT
A,#7FH
seOUl'll,A

SElin
ELSE
DO,
CAlL,INIT:
EHD;

9G SLlD:

CALL IHIT
ELSE

DO,
TIM[A~P/2;

STAAT TIMER;

BCOUHT[SJ"I;

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,os
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.

END;

1135LLC:

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111 S£XlT:I'CV
RETR

A,#-(P/2)
T,A
T

A,BCOUHT
A, "IBFH
BCOUNT ,A
1 £1'40:
; /4[XiT INT[RUPT MODE·,

II,IIT["'"

----------------------------

...

TJ!iRD

,

"'
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HUT:

PROCEDURE;

'2'

'"SHIfT CAI5!V INTO BJFf"ER·'
RX'-SERBUF;

,

"'""""

STAT

"S

115 ; INTJALJzt ROlITIHESTARTS RECEIV£ PROCESS
116 ;
It ? ~ - - - - - - - - - - - - - - - - - - - - - - - - - - - -

C

CD,

123

DISABLE INTERRUPTS.
P27·';

RX',#S[fmUf
A,ORXI
A

'"
,,.

START [VENT COUNT:
RQF-,;

A,ORI'

127

'22

RSHrT MEf'IHUI);

,

TiMER Ow 1;

"S

BCOUHT-SCOUNT-l ;
IF BCDUNT-' THEN

BCOut4T,S(K1T

,

....

P27".;

••
••••
.7

114 ;

A,P2
A

114135

DO,

l'1l\I
ecR
l'1l\I
DIS

START TlI'IER;

113

'''CARRY-RIO'll
CARRY ..P27 XHOR T[ST1:

JT'

TJI'£R"P;

7.

112

58

62

1135''''41

'TOT

CP,

DO,

os

I SERIAL BUFFeR
; REtE I'VE DOH£. FLAG

Tlf'£R-P;

IN
OLC

SLLD

71

92
93

; HLl'l8ER OF' BITS

OB'
ATEf'F,A

S'

IflC 882"
litE 27

1133 .43f

1 POI"TER

; 00;

I'II\I

SI
51 TISR'D: I'lOl/
52 SLOOP: xeM
RRC
S'
.S<
'C"
SS
56
DJHZ

"
••
••••

,132 AS

17H

••

"'5882'
1117 2'

1131 537F

; ,"ENTER INTERRUPT MODE·'

'S

os

R2
R'

•..

; STORAGE FOR A DURIHG IMTtRUf'T
; COHTAINS HtJIIBER or BITS IN MSG
1 UTILITY COUNTER

; -------------------------.----------------

28
29
31

..
.
..
..

R7

112F FE

; CDHTAOL. PASSED HERE IofoI[H TIMER ORO OCCURS
; ------------------------------------------

,

'119-FE
IliA 1'223

.

IF' T[5T1-' THEN

J"

82

12 ; ------'4; ------'S
16 ATEJII' 'OU
17 BCOUHT [QU

DO,

7<
7S
7.

,.

SJDIoI IN FIG 2 •• TO USE
THIS ROUTIHE,CALl INIT.
IrI£N Ror·, THE ASSEI'Il.ED
CHARACTER WILL BE IN SERBUF

S

A,SCOUl'tT
SLLC

13
1126 563S

•
••

71 START: IIIDY
72
JB6

111"'2 BABI
RI)F'-';

11"'4231'".

DISAIl.E EX INT:

l1li4662

EtlDI

'1"745

RltI,#RDf
A

1148882<1

OIUI.A

18"C 881t

TCtITI

"<1£

8.4A Bill

Its.

; [fOlD;

sice

25
US183

SEX IT
I ELSE

; 00;

".".

BCOUHT·IC,H OR BITHO
END;
END HilT;
l!~iT:

DIS

TeNTl

'"
133

DO,
MIIV
MDV

Pl,#8I1H

"S

51R1
MOIl

131

...
,.
...'"
,....

132

142
14'

IF BCDUHTl6J-' Tf£N

Mav
MOIl
MOV
'N
RET

A,It-1

T,A
eNT
IU',#RDf
@lRXI,#B1H
; POI NT AT BCOUHT
RXIJ."'[H
@RU.#UCIH OR BITMO}
TCNTT
; EHD

or

PROGRAM

'NO

Figure 22. Interrupt Driven Serial Receive Program

codes such as those used in synchronous data communications (e.g. BISYNC or SDLC). BCH codes,
named for their originators Bose, Chaudhuri, and
Hocquenghem, are characterized by having a length
of n=2m-l, The number of redundant check bits
can be mt where t is a positive integer (clearly mt
';;;;n), The 31,26 code fits this format with m=5 and
and t= I. The length of each message is n=2 5-1 =31
with 5* I redundant bits, leaving 26 bits available
for. data transmission, With an appropriate polyAll mnemonics copyrighted @ Intel Corporation 1976.

nominal BCH codes can detect all errors consisting
of 2t error bits and all burst errors of mt or fewer
bits. The 31,26 BCH code will therefore detect any
erroneous messages with I or i errors or bursts of
errors of less th~n 5 bits, The 31,26 format (shown
in Figure 23) requires the reception of a start bit
followed by 31 infonnation bits, clearly beyond
the cap;:tbility of the USART but perhaps within
reach of a program controlled approach using the
MCS-48 itself.
'
.
1-18

inter

AP-24

Figure 23. 31,26 BCH Code

A concept which reduces sensitivity to frequency
deviations and thus allows the reception of longer
codes is shown pictorially in Figure 24. The first
line of this timing chart shows an alternative ones
and zeros pattern on the RxD with a period of S
milliseconds. The second line shows that by
sampling at a period of exactly S milliseconds the
data can be properly interpreted. The third and
fourth lines show the effects of sampling with a
period of six and four milliseconds respectively. In
either case, an error occurs at the third sample
where both periods result in sampling on an edge
of the RxD signal. The third line of Figure 24
shows a hybrid sampling scheme which, based on
some additional information, switches sampling
periods between the two values. As can be seen in
Figure 24, the data is sampled with a 4 milli~econd
period until the sampling begins to fall behmd the
data; at this point the sampling period is increased
to six milliseconds and the sampling first catches
up and then passes the center point of the data. As
soon as this happens, the sampling period reverts
to the 4 millisecond period and the cycle repeats.
It can be seen that this scheme sets up a pattern
which repeats indefinitely and the data can be
successfully sampled. Note that the sampling pattern
established is alternating periods of four and six
milliseconds. The average period of this pattern, as
might be expected, is Smsec. Line 5 of Figure 24
shows the effect of a change in transmission speed
to a period of S.5 msec with no change in the
sampling time. The sampling is again successful but
the new sampling pattern is 4-6-6-6; 4-6-6-6, etc.
Note that the average sample is again equal to the
period of the received data (S .S). While this scheme

1

does seem to work, the question of what additional
information is needed remains.
The MSC48 must somehow decide when it is drifting out of synchronization and take corrective
action. By referring back to Figure 24 it can be
seen that if the MCS48 could determine where the
edges of RxD occurred with respect to its sampling
times then the additional information would be
available. As can be seen in the figure the choice of.
sampling period can be based on the following rule:
If an edge on the RxD line occurs during the
first half of the current sampling period, then
use the short period for the next sample. If an
edge occurs during the second halfof the period,
then use the long sampling period for the next
sample.

If the data on the RxD line does not change, of
course, the MCS-48 will drift out of synchronization
just as the original algorithum did. As long as edges
occur on TxD, however, synchronization· can be
maintained. To maximize the allowable time
between edges, the following addition could be
made to the above rule:'
If no edge occurs on the RxD line during a
sample, then change sampling period from short
to long or vice versa.

Note that this addition to the rule will result in
using an average of the two sampling periods when
no edge occurs for several bit times.
The edges of RxD can be easily detected by the use
of the same structure (the Exclusive - NOR gate)
which was added to the MCS48 in Figure 20. This
gate, which .is used to detect the edge on RxD
which begins the START bit, can naturally be used
to detect any edge. Since the timer is being used to
time the bit period, however, the event count input
(T I) is not useful during the receive itself. By connecting the output of this gate, however, to the
00 input to the MCS48 (see Figure 2S)' it is
possible to detect edges on RxD with the event
counter when the program is trying to detect the
START bit and by the external interrupt when the
program is using the timer to control the sampling
times.

Smsec PERIOD
5msecSAMPLE

2. 5msecPERIOD
6msecSAMPLE

3

Smsee PERIOD
4msecSAMPLE

4

5msecPERIOD
HYBRID SAMPLE

-l~~~--1.-'..J.....!!....I...'-'-.!C.J..::..J..--"-J...::..J-"-...I..

5. 55msecPERIOO
HYB RIO SAMPLE

-l..:...J..cc...L...::...L."--'-"'::""'.L...::....L.:-'....::....J....::....J'--'.....L..'--'-;-

Figure 24. Various Sampling Alternatives

1-19

inter

AP-24

Because of this edge detection it is important to
condition RxD with hardware filters to ensure that
the edges of RxD are clean. Any ringing will cause
repeated CALLs to XISR and probable erroneous
operation. The changes to the START process
(Figure 26c) are two-fold; first the TIMER is set to
one half the average of the two sample periods
when the START bit is first detected (BCOUNT
[6) = I), and second the processing of the edge
information, is initialized by presetting SNAP and
clearing P27 .
SNAP is preset so that when the reception of data
actually begins (Figure 26b BCOUNT [7) = 0), the
decision block which tests SNAP against LIMIT
will be initialized. This block actually compares the
value in SNAP with a LIMIT value which is used to
determine if the sampling point is ahead or behind
the actual midpoint of the serial' data. If the
sampling is ahead then the timer is set for TMIN;
if the sampling is behind then the timer is set for

0
x,

x,

AD

'NT
R,O

D

T,

WR
PAOG
ALE
P"
P'B
P'5

P"
P'B
P'5

p,.

p,.

P"
P"
P"
P,O

P"
P"
P,o

0,
DB
05
D.
03
0,
0,
00

TO
'5V

·V ee

Voo
ss
PSEN

Vss
EA

}.~

}..

RESET

Figure 25. Modified Edge Detection

A modification to the program of Figure 21 which
implements this new sampling algorithm is shown
in Figure 26. The first deviation from the original
program is the addition of a routine (XISR, Figure
26a which is called when an external interrupt
occurs (Le. when an edge occurs on RxD). This
routine saves the status of the running program and
then stores the current value of the timer register
in a location called SNAP (R5 of RB I). After
doing these operations the program complements
bit 7 of port 2. Manipulating P27 in this manner
will cause the Exclusive NOR gate to turn off the
'external 'interrupt' and will set it up to generate
another interrupt when the RxD line changes again
(has another edge).

NO

-L__________- L__~~.

Hybrid Sampling Flowchart

Hybrid Sampling Flowchart

1-20

AP-24

lOC

OBJ

SOURCE STATEMENT

SEQ

SERIAL INPUT USIHG MCS-48
THIS CODE ASSlA'IES HARDoIARE
SH[WoI IN fie. 25. PROGRAI'I

IS SIMILAR TO PREVIOUS
ONE. A I'IIJRE S(J'HISTICATED
SAI'f'L INC, AL(iDRITI-t'I IS USED

YES

,.
11

NOTE;

A PLII'I II KE LANGUAGE WAS USED
TO CD"I'IEt'lT THIS LISTING AND
SEVERAL OTHERS '1'4 THIS NOTE. NO
C(J'f'ILER EXISTS fOR THE MCS-48.

12
13

14

THE CIl1'lENTS WERE 'HAtm

IS

CiM'ILEO' 11'410 ASSEMBLY COD[

16
17

••••••••••••••••••••••••••••••••••••••

I.

19 : ------21 ; EQUATES

....
,117

1115
"12

nla

liZ'
11'<11
"05

"09
frEe
IIZI
1124

21 : ----.-22
23 ATE/'P

[OU

2"
25
2G
27
28

[au

BCOUHT
SNAP
COUNT
R.IIO
SITNO

[QU
[OU
[OU
EOU

29 liMIT

EOU

31
31
32
33
3<11

[OU
[OU
EOU
[OU
EOU

mAX
TMIN
HALF
SER9Jr

RDr

.7

os

; STQRA(;( FOR A DUR I HG I NT(RUPT
j CONTAINS NlJfII9ER Of BiTS IN M5G

.5

; TAICES TlI'ER SNAP SHOT ON IUD EDGE

.2
21

;
;
;
;

·43

; MAX SAl'PLE PERIOD

-39

; MIN!,.."... SAl'PLE PERIOD
; HALF HOI'IIHAL PERIOD

••

32

-21
21H
2OTQN[: MOV

"

A,caWH

10'-'
A,PTOS

,

A, :tellH
PTOS,A

COI..INT

CL'
MIlV

.3

""

; SET TXD TO CARRV

, .--------------------------_.--

"

MOV
M()V
MOV

A,CHAR'AV
GOTOHE
e

A,Burr
PTOS,A
COUNT,tlU

CHARAV, liB

'ET
; END Of PROGRAM

,"0

AP-24

CONCLUSION
This Application Note has presented a very small
sampling of the application techniques possible
with the MCS-4S™ family. The application of this
new single chip computer system to tasks which
have not yet yielded to the power of the micro:processor Will present a fascinating challenge to the
system designer.

GENERATING PARITY
Many communications schemes require the generation and checking of parity. If a USART is used
it can be programmed to automatically generate
and check parity. If the communications is handled
by software within the MCS-4S™ then the program
must perform parity calculations. Calculating
parity is easy if one remembers what parity really
means. A character has even parity if the number
of one bits in it is even. A character has odd parity
if it has an odd number of ones. The program segment shown in Figure 29 can be caused to calculate
parity. It starts by setting a loop count to eight and

lOC

OBJ

SEQ

SOURCE STATEI"£I'IT

2 ; ••••••••••••••
3 :
.tIj

;

.

PARITY

5 1

THIS PROGRAM GENERATES PARITY

6;

ON THE ACCLnllATOR

7 1

CARRY WILL BE SET IF A HAS ODD PARITY

:

'3 \ ••••••••••••••

""

12 ; .-----13 : EQUATES

'"; ._-----

IS
1112

111.
.'81 BAIB
111297·

16 COUttT

17
Ie PAR:

"22"

[QU

OR.
MOIl

CL.

. ..

11tH
COUHT I # 8

C

21

1183 77

.'."'217
"16 A7

23 LOOP:

J.t

25
27
2.

ePl

•

: SET LOOP COUNT

; INITIALIZE CARRY
: fOR EACH ZERO BIT IN A
; CQrlFLEf'llENT THE CARRY FLAG

OVER

e

; £I'ID OF PROGRAM

'""

Figure 29. Parity Generation

clearing the CARRY flag. After this initialization a
loop is executed eight times. During each execution
the accumulator is rotated and the least significant
bit is tested. If the bit is a zero the CARRY flag is
complemented, if the bit is a one no further action
is taken. Since an even number of zeros implies an
even number of ones for an eight bit character,
after all eight loops have been accomplished the
CARRY bit will be set if an odd number of ones
were encountered; it will be reset if the number
were even. Since the RR instruction does not
involve CARRY the net result of executing this
program loop is to set CARRY if parity is odd
without effecting the character in the accumulator.

All mnemonics copyrighted @ Intel Corporation 1976.

1-24

-

-

inter

APPLICATION
NOTE

Ap·40

June 1978

• Intel Corporation, 1978

1·25

9800755

intJ

AP·40

INTRODUCTION

This application notes presents a software package for
,interfacing members of Intel's MCS-48™ family of
single-chip microcomputers with keyboards and displays using a minimum of external components. Because of the similarity of the architectures of the various members of the family (the 8035, 8048, 8748, 8039,
8049,8021, and 8022 microcomputers; also the 8041 and
8741 universal peripheral interfaces in the UPI-41'"
family), the code included here could run with minor
modifications on any member of the family.
Since keyboard and display logic can be just one of
several functions handled by a microprocessor, the
added cost of including these functions in a system is
minimal. In fact, considering the extremely low cost of
standard X-V matrix keyboards and integrated displays,
their use is often more cost effective than even a handful of discrete switches and indicators. Thus, the additional flexibility of keyboard input and display output
can be added to inexpensive consumer products (such
as games, clocks, thermostats, tape recorders, etc.),
while producing a net savings in system cost.

In traditional digital system deSign, various hardware
registers or counters were used to hold binary or BCD
values which had to be conveyed to the user. The standard way of presenting this information was by connecting each register to a seven-segment encoder (such as
the 7447) driving a single display character, as represented by Figure 1. Thus, two ICs, seven current limiting
resistors, and about 45 solder joints were required for
each digit of output. Consider how traditional techniques might be (mis-)applied in designing a microprocessor system: the designer c )uld add a latch, encoder,
and reSistors for each digit of the display. Still another
latch and decoder could be used to turn on one of the
decimal points (if used). The characiers displayed could
only be a sequence of decimal digits. In the same vein, a
large matrix of key switches could be read by installing
an MSI TTL priority encoder read by an additional input
port. Not only would all this use a lot of extra I/O ports
and increase the system price and part count drastically, but the flexibility and reliability of the system
would be greatly reduced.

+V

Since each potential application will have its own
unique combination of keys and display characters, the
program is written so that very little modification is
needed to interface it with a wide variety of hadware
configurations. In general, the only changes required
are within the set of initial EQUates at the beginning of
the program.

a

Along with the basic software for driving a multiplexed
display andlor scanning and debouncing an X-V matrix
of key switches, a collection of utility subroutines is
also included for implementing the most commonly
used keyboard and display utility functions, such as
copying simple messages onto the display or determining the encoded value of each key in the key matrix. As a
result of the versatile architecture and applications"
oriented instruction set of the MCS-48 family, the entire
package fits into about 250 bytes of internal program
ROM or EPROM, leaving the rest of the ROM space for
the program to cook the perfect piece of toast, or whatever. By tailoring the software to match a known hardware configuration, or by selecting only those functions
needed for a given application, the' program size could
be even further reduced.
Since what is being presented in this application note is
a software package, rather than the usual hardwarel
software system deSign, the format of this note is somewhat different from most - it conSists primarily of a
long program listing reproduced in the following pag,es.
For the most part, the listing is self-explanatory, with
comments introducing each subroutine and major code
segment. Some parts of this introduction are repro, duced in the program listing itself, explaining the configuration of the prototype system. However, an additional bit of explanation would make the listing easier to
understand, especially for those readers unfamiliar with
the concept of multiplexed displays and keyboards.

CIRCUIT REPEATED FOR EVERY DIGIT OF DISPLAY
(DOTS USED TO INDICATE SOLDER JOINTS)

, Figure 1. Wrong Way 10 Design Multiple Digil Displays lor
Microcomputer Systems

1-26

AP·40
Instead, a scheme of time·multiplexing the display can
be used to decrease costs, part count, and interconnec·
tions, while allowing a wider range of character types to
be used on the display. The techniques used here are
fairly typical of today's integrated subsystems designed
especially for controlling keyboards and displays (such
as in calculators or the Intel@> 4269,8278, and 8279 Key·
boardlDisplay Controller Devices).

to be displayed, and turns on the appropriate segments.
With the next character now turned on, the processor
may now resume whatever it had been doing before. The
whole display updating task consumes only a small frac·
tion of the processor's time.

In a multiplexed display, all the segments of all the
characters are interconnected in a regular two·dimen·
sional array. One terminal of each ,segment is in com·
man with the other segments of the same character; the
other terminal is connected with the same segments of
the other characters. This is represented schematically
in Figure 2. A digit driver or segment driver is needed for
each of these common lines.

1SEGMENT
J DRIVERS

_m __ __ __ __
__
w
_
~

~

~

~

SEGMENTS SEGMENTSSEGMEflHSSEGMENT5 SEGMENTS SEGMENTS

D~T_

~!!...

~c!!...

~~

_D~T

_~IT

1DIGIT

I "a" SEGMENTS OF

J All

J DRIVERS

DIGITS

~;-t-"",-:+-"",-:+-"",-:+~-:+~d-l"b"sEGMENTSOF
J ALL

DIOlrs

~;-,-t~;-,-t~rl-~t-"-'"t-""""-+- !"C"SECMENTSOF
J ALlDIGLTS
CURRENT
SOURCED

"

Figure 3. Segment and Digit Drivers used with 6·Posltlon, 7.Segment
LED Display

-'<":'""r--'C':""r--=-t-"'C:"-+-""'"-+-"""+- 1"d"SEQMENTSDF
J ALL DIGITS

SEGMENT

DRIVERS

~-::.rl~-::.rl~c1-,-""!-","+---=+- j ..... SEGMENTSOF
JOIGITS

-rir--,--1r--=-r--"'"'"+-"'"+-"""+-I"'''SEGMENTSOF

I DIGITS

-~!-~f-'-""!-"""+-""O':-+-~+-l "g"SEGMENTSOF
J ALLOIOITS

-ri-rir--;;:-:-r--"'"'"t-"'"'"+-",,-"+-

I

DECIMAL POINTS
, ALL DIGITS

OF

Moreover, since the computer rather than a standard
decoder circuit is used to turn the segments off and on,
patterns for characters other than decimal digits may be
included in the display. Hexadecimal characters, spe·
cial symbols, and many letters of the alphabet are pas·
sible. With sufficient imagination this feature can be ex·
plaited for some applications, as suggested by the
examples in Figure 4.

CURRENT SUNK BY

DIGIT DRIVERS

Figure 2. Schematic Representation 016·01gll, 7·Segment
Common·Cathod LED Multiplexed Display

,L"-'
,'- '- '-, '-,,-,

The various characters of the display are not all on at
once; rather, only one character at a time is energized.
As each character is enabled, some combination of seg·
ment drivers is turned on, with the result that a digit
appears on the enabled character. (For example, In Fig·
ure 3, if segment drivers 'a', 'b', and 'c' were on when
character position #6 was enabled, the digit '7' would
appear in the left·most place.) Each character is enabled
in this way, in 'sequence, at a rate fast enough to ensure
that the display characters seem to be on constantly,
with no appearance of flashing or flickering.

'I

L

, L'L
'I I I
,-, L/Il ,

In the system presented here, these rapid mOdifications
to the display are all made under the control of the MeS·
48™ microcomputer. At periodic intervals the com·
puter quickly turns off all display segments, disables
the character now being displayed and enables the next,
looks up the pattern of segments for the next character

,-,-, , 'I

'

'-'-'-, ___ -

/,- 1,/,

d=

III

Figure 4. Examples '01 Typical Messages ,Possible with Simple
7·Segment Displays

1-27

AP·40
As each character of the display is turned on, the same
signal may be used to enable one row of the key matrix.
Any keys in that row which are being pressed at the time
will then pass the Signal on to one of several "return
lines", one corresponding to each column of the matrix.
(Sell Figure 5.) By reading the state of these control
lines, and knowing which row is enabled, it is possible
to compute which (if any) of the keys are down. Note
that the keys need not be physically arranged in a rectangular array; Figure 5 is merely a schematic.

COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4
REtURN
RETURN
RETURN
RETURN

LINE

LINE

LINE

LINE

TO SWITCHES
ON ADDITIONAL
RETURN LINES

FROM SWITCHES ON
ADDITIONAL SCAN LINES

machine cycles. :One machine cycle occurs every 30
crystal oscillations for the 8021 and 8022, or every 15
oscillations for all other members of the family.) A more
detailed explanation of these variables is included in the
listing.
Port assignment is also at the discretion of the user all port references' in the listing are "logical" rather than
physical port names. The port used to specify which
character is enabled is referred to as "PDIGIT". The output segment pattern is written 1-0 "PSGMNT" and the
keyboard return lines are read by "PINPUT". These
logical port names may be assigned to whichever ports
the user pleases.
By way of example, the breadboard used to develop and
debug' this software used a matrix of 16 Single-pole
push buttons and an 8·character common-cathode LED
display with right·hand decimal point. No decoders external to the 8748 microcomputer were used; all logic
was handled through software. PDIGIT was the 8-bit
DUS, PSGMNT was port 1, and PINPUT was port 2. The
drivers used were 75491 and 75492 logically noninverting buffers: high level inputs were used to turn a
segment or character on. Pull-up resistors were used on
the 8748.output lines to source the current levels
needed by the buffers. The 8748 was socketed on the
breadboard, and was driven with an inexpensive 3.59
MHz television crystal. The short test program included
in this listing was used to echo key depressions as they
were detected, and ·to invoke four demonstration subroutines. A summary of the subroutines included in this
listing with a short explanation of the function of each is
included in Figure 6; Figure 7 shows how the various
utilities interact.

Figure 5. Schema'ic of X- Y Ma'rix Mulliplexed Keyboard
KBDIN

Since each character Is on for only a small fraction of
the total display cycle, its segments must be driven with
a proportionately higher current so that their brightness
averages out over time. This requires character and seg·
ment drivers which can handle higher than normal levels
of current. Various types of drivers can be used, ranging
from specially designed circuits to integrated or dis·
crete transistor arrays. The selection depends on
several factors, including the type of display being used
(LED, vacuum flourescent, neon, etc.), its size, the
number of characters, and the polarity of the individual
segments. Some drivers have'active high inputs, some
active low. Some invert their input logic levels, some do
not. Some require insignificant input currents, some
present a considerable load. Some systems use externallogic to enable one of N characters or to produce the
appropriate segment pattern for a given digit, some systems implement these functions through software.

CLEAR
ENCACC

WDISP

RENTRY

PRINT

FILL

ECHO

RDPADD
HDLD

Because of these and the other variables which make
each application unique, provisions are made in the first
page of symbol EQUates to allow the user to specify
such things as the number of characters In the display
or the polarity of the drivers used, and the program will
be assembled accordingly. The display is refreshed on
each timer interrupt, which occurs every 32 x (TICK)

DELAY

Keyboard Input. WBits until one keystroke input has been received
from the keyboard. determmes the meaning or legend 01 that key and
returns with the encoc:led value In the accumulator.
Blank out the display
Encode accumulator with bit pallern corresponding to the segment
pattern needed by the dIsplay to represent that symbol or character.
Uses the value of the accumulator when called to access a table can·
talnlng the patterns for all legal mput values.
Write into Display. Writes the bit paltern In the accumulator mto the
next character pOSition of the display Maintains a character position
counter so thaI repeated calls Will automatically write characters inlo
seQuenttal pOSItions
Righl·hand Entry. Siores the accumulator segment pattern In the
display In the rlghl·most character position. ShIfts all other characters
to the lell one place
Print a siring of arbItrary characters onlo the display. Useful for pro·
mpt.ng messages warnings. etc Uses a lable 01 segment patterns In
ROM. so thaI messages Will not be restncted to numbers. letters. elc.
Fill the display With the character pattern In the accumulator. Useful
lor writing dashes. segment test patterns. etc .• IOta all character posi·
tlOns
Walt for a key to be pressed by the operator and wrile that key onlo
the display Used for providing feedback to the operator when enter·
Ing numeric data. etc
Adds or deletes a deCimal POint to the character at the tlght·hand Side
of the display. lor entering lIoating pOint numbers
Called when a key IS known to be down Does not return until all keys
have been released. Used lor organ· type keyboards. or when some ac·
I.on should not be Inlflated unltl the key invoking that acllon has been
released
PrOVides a crude real·tlme delay corresponding to the value of the ac·
cumulator when called. Can be used 10 cause d.splay characters 10
blink. to momentarily flash Information. to enable a buzzer. elc Could
also be used by the program when delays are needed. such as to slow
down the computer reaction rate while playing a g:ame againsl the
human operator.

Figure 6. U'lII'y Subroutine Deflnilions

1-28

AP·40

MAIN BACKGROUND PROGRAM

I
CLEAR

I

FILL

I

I

.J+
I

PRINT

ECHO

RDPADD

KBDIN

ENCACC

RENTRY

DELAY

HOLD

Figure 7. Subroutine Interrelationships

I

2"[,lsf,otJ
•
•

J~

~CC VDO

75491

.13

"

f"F

~

."d" . .,..I.,... j"d'P."j
F'E'ElPr'F'F'r'l
=1. -'. _. ~. ~. ='. !:i. ='.

."S"

_"b'

"~"

_lEF!:~,?~!

'------'

I.
~

~

15492

0@@J:

@@}@D
I I

II

ALE

3<

! ! 1

"

pli

"

"

"
I.
I.

"·~"(E

I.
~

~::~:

N.C.~

.!!

N.C •

~

I

P20
P21

EXPAN~g: ,~ P••

13
75492

8748

13

II

II.

•

':: I!-

33

I'

P••

35
38

I

3'
38

--"~-""-

l~

Flgu"; 8 Prototype System Schematic

1-29

~~fN.C.

:::~

31

32

~

CD@@JD

T1

iNT

30

"

I~\\'::A~~:~

TO

211

;5491

55

2'
20

---'

N.C.-:
N.C..2

0®®=

-=

j

-l1l.!.\,J,J

"e'

h~~ T' 'y....

AP·40
1515-11 H(;S-48/1j;"1-41

MAC~J >\SSEf1lllE~,

'.12 [J

ANfJ lNfEl 11(5-48 fH'BllftFL'tl5F'LH" Hl'PLl(AllOll NC,TE APPElt',!,:

LOC iJBJ
1 SHAU'oF I LE ~\~'EF
2 nITLE' 'AF'40, WTEL

M(~:-48 I:E~Bl;HflD,'['ISPLH"

HPF'LII)ITIOtI NOTE APPENDIX",

4 ,THE FOLLi.MING SOFTIoiAPE P~iClAGE PP.O,,'WE5 fI 51:VEN SEliI1ENT [,ISF'Lfili
5 ,INrEP.F~Cr. Hili mC~~(lCO~1FIJTER~ iN THE lNTtl ;n-4S Fflt'!IL'y'
,; ,THE CODE IS WP.I HEN SO THAT VAl<' lOLlS HHFfll4APE
7 ,CI.lltFIGIJF.'fl1 IONS CAN f>E Al);.)t10(!ATE.[' 8'T' F.E[l£I' !t.JIIIj [HE HlI lIill "'~:IABLES
8 , IN MOS r 5ITUftTiONS, THE ~E','80Aj;'t'/IiL5FLH1' lUTERFFtCE WILL BE ~'W.lIRE[\ '\G
9 ,iMF'lHIEln MO.E. SOPfHSTIGfiTE[; ,:INGLE-CHiP Sl'5IEMS (c.~LL'lJuno~':;:, ,fflLE.S, CLUI.'f..5,
19 ,!:.Te, ), WITH SE('T!()NS OF THE FGLLl.lWINb un 3E'LECTEIJ AND i'liHF!E[> AS NECESSAfI"
11 ,FO~' mCH tlPPLl CATION

1<: '

~: ,A SINGLE SUflPWllNE «(fUEi) f;UJ.'SH! IS CISEu TO IMf'WlENi BOTH THE DISf-'Lkl'
14 ,joJIJLTIPLD:INlj AN[, ~E'y'BOftRt' SC,lUN1Nlj. 1J<,1N(' THE SRt11: ~j(jNAl BorH TO EIlABLe
15 ,ONE CHfiI?AClt~' OF THE DISFLA',' F1f4\ ,0 STROBE ONf ;;'0101 OF ,fit i(-Y ~'E'" tlffTPlt!
16 ,IHE SUIWOUTIPlE MI.I5T BE CfiLl,£[; ';lIFf'l,:mHL,' 0HEU 11) HISIJIlF. rH~ vISI'Lfl'i

r' ,CHf1F:AC1E~':, riO NOT FLlCKH'- Ai LEAS T 5.,1 tt)I1F'LETE DISPl.A" SefiPlS PER ~.ECONv
1:3 ,TO Hl(Wl0[JATE SWITCHES (If Aj;'t>lTRH~Y CflEFtPNESS, [HE DElMJNCE TIME GAP! BE
19 ,sn T,) BE ANI' [>tSIPED NI.lMBER or CONFUTE SlANS
28 ,THUS THE llEBi)IJNCE THfE IS H FUUCTION OF 80TH ,HE SCHN kFilE AND ,HE VALlJ!:.
i1 .,0F CtJNS rANT 'VEBNCE'
2i .'
~~ ; It! THIS Ll~T1NG, THE INTE~NAL ilME~' IS I)SE~TQ IjEt;EPAIE INTERRLlP'I5 THAT
24 ,SERVE AS A TIME BASE FOR THE PEFP[SH 5UBPOllTltlE
<:5 ,ALTERNATE mlE BASES MIGHT BE fiN EXTEPNAL u';CILLAi..w q)~I'JWI.l THE It-llERI TlRET
]0, mINT ~ElURN) GOIJl[, STilL BE I,;SE[1 TO ::;AVE AND "ESlOPE A(CtiMULflTOt.' CONTENTS
}1, THE INTEPFUF'l SEF.'\'ICIN(; flOI)TINE SELECTS J.'EGlSTE.' BANK 1
n ,FOP 1HE NEEVEli REGISTERS
2.3 '
A',
0:5 "Wi"lTWI I::Y JOHN WHfIRTUN, INTEL SIIl(;LE-CHIP COt'lf'UTER ftPPLlCATIOr4S
]6 '
'j,i !EmT

All mnemonics copyrighted @ Intel Corporation 1976.

1·30

AP-40
ISIS-II r1(,s-48.'UPI-41 i'fHCPO flSSEMBLER, V';: B
INTEl MCS-48 KEYBOAl1[,/IiISPLfi',' RPPLlCAflON,NOTE APPENIiIX

flP48

LO(' CIB]

SEO

SOUIICE STATEMENT

s8 ,IN iHIS Ii1PLEMEtHtil WN 'jF THE [015PUI'~ SCAN. IT 15 ASSUMED "iHfH THEilE WILL
:;9 "BE I"El.AlI','EL" L1TTl.E 1/0 OTHEII THAN ~,)", THE KE'r'BOfW[i/[OISf'LA',
4e ; IF HHS 15 THE CASE. THEtl THERE I~ NO NEED FOil FI.l~ RN'" AWIiIONAL EXtEPNAL
41 ,LOGIC (SUCH f6 ONE-of-ElGH1 DEW[OEI"S 011 :;E'~EN-SEGt1Hn ENCODERS), THOUGH
4~ ,THE~'E

43
44
45
46
47
48
49
5e
51
52
5~

:,4
55

16
'i,
58

59
6@

61

62
6,
64
65
66

WILL STILL BE A HEEl) FO~' CU~'REN1 OR VOLTAGE Dl HAT!,:!,', WEIi:E tlECTi<'ICftLL',' OPGANI:;ED
92 '
IN A 2:<8 ARRAY, ONLY TWO RETURN L1tlES Wt)IU BE NEEDED.
93 ;
i1N THis CASE, PEPHAPS Tii it,ll" 11 COllLD BE I)sE[J FOR INF1JT BIT::' "
94,
95 ,PULL -uP I<'ESISTfJRS ON THE

IIETI~N

LINES I'IIGHT BE III ORDEI< IF

THE~f

15 AN"

96, POSSIBILITY Of A HIGH-li'1PEDENtE CONDUCTIVE PHTH THRW(,H THE SWITCH WHEN
9, ,IT 15 SlIPF'OSED TO BE 'OPEPI'.
98 ,(THIS PHEHOI'1ENON HAS ACTlIALL'1 BE!:N (.BSERVEL· ;.
99 ;
10!:l , THE r~I"'ER5 USED IN THE pFiOTOlYPE HEf.'E ALL NON- INVERTING IN THAT
1~1 ; A HIGH LEVEL ON tlN WTPUT lINE b USED TO TIJRN Ii CHflRRCTEfi OP SEGMENT ON
192 . THERE ARE A TOTAl. OF SEVEN 1/9 LINES LEn (lVE~
1tl?
104
195
106

;
.
• THE ALOORlTHII FOIi: Llff'ECTl VEL ~'J
122 ,
123 ; THE K~YBOAR(l SCANNING ALGORITHM SHOWN HERE REQUIRES fl ~EY BE DOWN FOR
124 ; SOlE NlIHBER OF CO/1PLETE DISPLAY SCAN::' m BE ACKNOIoILEGED. SINCE IT IS
125 ; INTENDEv FOR '()£-F INGEll' OPERATIVN, Two-KEi' ROLLOI/ER/N-KEi' LOCKOUT HAS
126 ; BEEN IIIPLEMENTED HOIoIEVEFI, MOOIF (CATIONS IoIOll.D BE POSSIBLE Til ALLOW. FOR
127 ,EXAI1PLE, ONE KEY IN THE MATR1:, TO BE USID AS A SHIFT KEi' OR CONTROL KEY
128 • TO BE HELl) DOWN IoiiILE ANOTHE~ KEi' IN THE MATRI~ 15 PRES5Ev (SEE HuTE WITHIN
1~9, THE BOO',' OF THE LISTING, )
130;
131 SEJECT

All mnemonics copyrighted @ Intel Corporation 1976.

1-32

inter

AP·40
~~
PAGE
INTEL I'IC5-48 KE't'EOAFDlvI5PLAY APPLICi1TION NOTE APPENDiX

ISIS-II I'1CS-48/UPI-41 MACRO ASSEtlBm', '<'2
AP49

Loe OSJ

SEQ

4

SOIJRCE STATEt1EIlT

122 ; (BE flWARE THAT NO t'10~:E THAll TWO fl',':; CAN ~VEP BE D(j,IN UNlESS (,lODES
13:; ,ARE !'LACEr' IN SEkIES WITH ALL OF THE ~WITCHE5- CERTiHNl\' NOT THE CASE FOR EL
134 ,CHEAPO I\E't'BOARDS- BECAUSE SOME C,IMBINATIONS OF THREE KEYS ['oWN WILL RESULT
135 ; IN A 'PHAtHIJI'I FOURTH m' BEING p~RCm,'f.[,
136 ,THE PHANTOM rE',' I~OIJlD BE THE FOURTH CORNH" WHeN I HPEE KE'iS FORrmlG
E7 ,A "'ECTANGIJLftP PATIERN I IN THE ;':-'i ~E'r' /-IATRIX', ARE IXlWN \
E8 ,IF (HOOES H!<'E PLACE!: III THE SCrilllllNG MRRA'i, CONSiDERATIONS MUST BE NAvE
139 ,AfiOliT HOW THE DIODE VOL TAGE D~:OF' WILL fiFFEcr lHf'UT LOGIC LEVELS

140,
141 ; WHEN f, [iEBOIJNCEI> tH 15 DETECTE(', THE NUMBER 01' ITS POSITION IN THE f'El'
14~ ,MATRIX (lEFT-TO-I1IGHT., Bonurl-TO-TOP, STARTING FROM ell) IS PLACED INTO
143 ,PAM LOCATION '~B['I!IJF' AN INPUT SlJB~OIJTlNE THeN NEED ONL ... READ THIS LOCATION
144 ,I"EPEATE[I\. ... TO ~lERMINE WHEN H f:E',' HAS BEEN PIIESSED WHEN A ~El' IS DETECTE[,·
145 ,A SPECIAL COOE BYTE ~HOULD BE WRITTEN BAC~ TO INTO 'KBDBlIF' TO PI/EVENT
146 ; REf'EftrEf' fHE(! IONS OF THE SAt1£.KEI'
147 ; THE "'OUTINE 'KBDIN' DEf'lOI15TP.fliE A Tl'PICFt!. INPlIl F'ROlOCOL. ALONG WITH f1 METH(I[I
148 ,FOR TRANSLATINu A KEY posmON fO ITS ASSOCIA1ED SIGNIFICfiNCE SI' AC(b~,INJ.j
149 ; TABLE 'LEGN(;S' HI P.Ol'1.

150 '
151 SEJECT

All mnemonics copyrighted © Intel Corporation 1976.

1-33

inter

Ap·40

ISIS-II l'lCS-4~/UPHl MACIIO ASSEt·1EUR, 112. tI
PIIIjE
flP4/3' INTtL 1'1(5-48 kEI'BOAPMHSI'Lft\' APPLICATION NOTE APPENIH:\

Lor liBJ

ae10
eOOB
0009

SOIJPCE STATEtlENT

SEQ

152 ,*'U HA ."'...'" ~ 1*"'*... ·H.t<*.j<****~***.**.t**********"'************** .
!'5} •
1'54, ' - INITIAL EQUATES TO DEFINE SYSTB'I CONFIGURATION
155 .
156 ; ******H"..t***.t<*",,,,**.t<**.********.t<*** .., ,..********************
157 ;
158 PD!GIT W)
; USED TO ENABLE CHARACTERS ANI) STROBE ROWS OF KE'IBOARD
BUS
159 P5Gt1NT EOli
,USED TO TURN ON SEGHENTS OF CURRENTLY ENABLED DIGIT
F1
1613 PINPUT WJ
P2
,PQF:T USED TO SCAN FOR KEY CLOSURES
; (NOTE THAT THIS POIIT ALLOCAllON USES THE HIGHER
161
; CURRENT SOIJRCING ABILlT'r' OF THE BUS TO SWITCH ON THE
162
; DIGIT DR I '/ER5, AND LEAVES P23-P20 FkEE FOR USING
163
• AN 8243 PORT EXPAN\)E~' I H !HE S'~STEt1. )
164
165 ;
166 POSLOG tOU
167 NEfiUXi EllIJ
168 .
POSLOG ; DEFINES WHETHER OUTPUT LINES ARE ACTIVE HI OR LOW
E9 CH~FfJL. Ef,iIJ
1iO SEGPOl . COl)
POSLOfj ,\FOR [:'RI','lNG CHAIIACTERS fIN!) SEG1'IENT PATlERIIS
0HII-i
,ru INES 8lT5 IJSED AS INPUT
171 INPHSK Erill

1('2

I

1n CHARNO EOIJ

~0F

5

174

flllO~1S

175
176
1;7
178
1,9
188
181
182
183
184
185

1-lC~LS

6

E"QU
.
TICK
WJ
['EBNf..E b)lI
8LAttr. WU

;
ENCI'l5k EW
.
SEJECT

; NUt1BEI1 OF (llGllS IN OISf'LA't'
t'F KEYS ,LESS THffN OR EQUAL TO CHARNQ)
,LE5SEf' DHiENSION OF KEYBffiRD MATRIX

,~·ows

E,tU

-1SH
4
00"l

• [:ETEliI'1lt1ES INTERRUPT INTERVAL
. NUMBER OF SUCESSIVE SCANS BEFORE KEY CLOSURE ACCEPTED
.' CODE TO BLANI<' 0I SPLAY CHARACTERS.
. (lo!WlD BE 20H IF ASCII DECODING ROO USED OR flFH IF
.7447-WPE SEVEN-SEGMENT DEC1JDER EXTERNAL TO 8748)

0FH

,SELECTS WHICH BITS ARE RELEVANT TO ENGACC SUBROUTINE

All mnemonics copyrighted © Intel Corporation 1976.

1-34

-Ap·40
I SIS-II HCS-48/l1P I -41 t1IlCRO ASSEMBLER, V2. e
PAGE
AP49: INTEL HCS-48 KE'r'BOARD/DISPLAY ftPPLICAfIGN NOTE APPENDIX
LOC OBJ

SEQ

6

SOURC,E STATEMENT

186 ,~**********,,***********.j 39

299

HOII
ftOD
MOil

291

MOY

A, ISEGMfif'
A.• CURDI(j
PNTR1. A
fl, @PNTk1

292
293 ,

OIJTL

P5Gt1NT, it

288
289

; LOAf) Ace 101/ NEXT SEGMENT PATTERN
,ENABLE APPROPRIATE SEGtlENTS

294 ; *******.~********,.***************~~**********~**~********~*

295 ;

296 ;
297 ;

901£ B821
002a 9A

THE NEXT CHARACTER IS NOW BEING DISPLAYED.
THE KEYBOARD SCAN R(JIJTINE IS INTEGliHTED INTO lHE DISPLAY SCAN.
WITH THE CURRENT ROW ENERGIZED. CHECK IF THERE AilE ANY INPU1S

298 ; **************************************~***.j<***.j<.j<***********
299.:
309 SCAN.
MOY
PNTRe, tKEYLOC ,SET POINTER FOR SEVERAL KE'r'l.OC REFEIIENCES
391
IN
/1, PINPUT
; LOAD ANY SWITCH CLOSURES
302 ;
303 ; ..................................................#...................... .
304 ; III
THIS BLOCK (IF CODE IS NOT NEEDED 8Y THE KE ....BOApr' SCAN LOGIC
•••
305 .'"
HOWEVEfI, ITS INCLIJ5ION WOULD SPEED THINGS UP A Bll BY
...
3lJ6 ,II
SKIPPING OVER ROWS IN WHICH NO KEYS AilE DOWN.
II.
397 ;..
IT WAS OMITTED HERE TO CONSERVE ROH SPACE, BUT 11lGHl BE
...
30a ,..
RESTORED IF IIEIIY LARGE KEYBOARDS (ESPECIRLL'r THOSE WITH EIGHl
•••
309 ,..
KEYS PER ROW) ARE TO BE USED WITH THIS ALGORITHM
•••
31B: ........................................................... tItI.............
311 ;..
eft
A
; ANY CLOSURES [.oI::TECTED ARE 1m'", ONE 81 T5 tI..
312 ,.11
ANL
A, • I NPMSK
•••
313 ; ttl
JHZ
SCAN!; -IF A K~Y HI THE CURRENTL"r ENABLED ROW IS DOWN •••
314 ,it;
NO KEY 15 NOW OOWN SO THE KE'~LOr COIJNT l'tA',' BE IJPDAIED DIRECTLY ...
:1l5 ;..
~lOV
A. @PHTR0
...
316 ;..
ROO
A, .NCOLS
•••
:m ; it
MOil
@PNTRl!, A
III
318 :..
.IMP
SCAN6
Ill.
319 ; ........................................tItI••••• tll •••••m .................
329 ;..
IF THIS (;ODE IS USED, SUBSTITUTE THE ; Je SCANS' FuUR LINES
...
321: ••
HENCE WITH 'JNC SCANS· TO A(;COI1ODATE THE I HI/ERTED POL~ 1T'r'
•••
322 : ..........................................................................
323 sEJECT

All mnemonics copyrighted © Intel Corporation 1976.

1-37

inter

Ap·40

ISIS-II IICS-48/UPI-41 I1ACRO ASSEt1BLER, 112.8

PAGE

9

ff49. INTEL IICS-48 KEYBOARD/DISPLAY APPLICATION NOTE APPENDIX

LOC OSJ

SEQ

SOORCE STATEI1ENT

.*"'*"'*"'***************************."'***********************
ROTATE BITS THWl/I'JH THE CY WHILE INCREMENTING KEVlOC
326 .; .**********************************************************
327 ,

324 i
325 ;

8921 8004
8923 F7
0924 AC
0025 F63F

328 SCANt: 1101/
329 NXTLOC: RLC
I10V
338
JC
m

ROTt.'NT, IINCOLS
A
I"OTPAT, A
SCANS

; SET UP FOR (NCOLS) LO(fS THFOUGH 'NXTLOC'
SAllE SHIFTED BIT PATTEI1N
; ONE BIT IN CY INDICATES KEY NOT DOWN

i

:>32;
313 ,***************************-1<****************************"'**
334 ;
335 ;
HT THIS POINT IT HftS JUST BEEN DETERMINED THAT THE VALUE
336 ;
OF KEYLOC IS THE POSITION OF A KEY WHICH IS NOW DOWN
I~;' ;
THE FOLLOWING CODE DEBOUNCES THE KE'r', ETC.
33S ,
IF MODIFICATIONS TO THE KlYBOARl> LOGIC, l. E. THE INCLUSION
:m ;
Of A SHIFT, CONTI"OL.. OR MODE KEY Itl THE KEY HATRIX ITSELF)
349 ;
ARE DESIRED, THEY SHOllD BE MADE AT THIS POINT, BEFORE
341 ';
THE DEBOUNCE LOGIC BEGINS. FOI" EXAI1PLb AT THIS POINT
342 .;
KEI'LOC COULD BE COMPARED AGAINST THE POSITION OF THE. I100E
343 ;
KEY, AND IF THEY MATCH SET SOME FLAG BIT AI{) JUMP TO
344 ;
LABEL 'SCANS'. OR, BY COI'fPftRING KEYLOC AGAINST THE LAST
345 i
KEt' DEBOUNCED, IHMIODIATE TWO-KE',' ROLLOVER COULD BE
346 i
IIIPLEl'fENTED.
347 .;

9027 AS
0028 B5

348
349
350
351

,*****************>t-**************************.fc**************
i
(;LR
(''PL

; MARK THAT AT LEAST ONE KEY WAS DETECTED
; \ III THE CURRENT SCAN

F1

.Fi

352 ;
353

i

3S4 ;
355 i

0029 F9
002A 2E
002B DE
002C ·8820

002E C634

*******01<***************************************************
A KEYSTROKE WAS DETECTE!> FOR THE CURRENT COLIJIN. ITS
POSITION IS IN REGIS1ER KEI'LOC.

SEE If SAME I787
!le38 AiJ
0039 963F
8938 FE
893C 8822
003E A9

378
379 ;
389 SCAN~.

381
382
383
384
385
366
387

110Y
JZ
DEC
I10V
JHZ
11011
HOY
1'101/

A,~NTR8

SCANS
A
@f'NTRIl.A
SCANS
A, LflSTl'Y
PNTR9, *VB£i8iJF
@PNTRll,A

388 ;
003F 8821
904118
9tf42 Fe
!.III43 ED2:;

9945 EFS7

389 SCANS.
:;90

:m

1'1011

392
393 .
394 ;
395 SCAN6.

DJNZ

PNTRI.!. IKEYLOC
@PNTR0
fI, ~OTPAT
ROTCUT, NXTLOC

D.JNZ

CURD I 1], SCAN3

1'10','

INC

;96 ;
397 fEJECT

All mnemonics copyrighted © Intel Corporation 1976.

1-39

; I F AL~EAO't' ZE~O
• INDICATE ONE tl()~E

SUCr.ESI~'E

'H liUECTlON

dF DECREMENT DOES NOT RESULT IN

; TO MARK NEW KE.Y

CLOSIJ~'E

;::E~'O

Ap·40
ISIS-II MCS-48/UPI -41 t1ACRO ASSEMBlER, ',12. (I
PAGE' 11
RP4(1: INTEL HCS-48 KE'r'BOARD/DISPLfl'r' flPF'lICRTIONNOTE flPPENDnl

LOC OBJ

SEQ

SOURCE STATEI'1t:.1l7

398 ;
399 ; *************"'***********"*";**********'~*******"'*"'**********
490 ;
THE FOLLOWING CODE SEGI'lENT IS USED BV THE KE'r'BOAR[! SCANNING f"OIJTlNE
401'
IT I 5 EXECUTED ONLV AFTER A REFRESH SEQUENCE OF ALL
492 ;
THE CHAFACTERS IN THE DISPLAY IS COMPLETED
493 :
404 ;
0047
8049
0048
004D
904F

BFOO
8900
764F
BEFF
A5

0050 B923

0052 Fl
0053 COS7
9955 97

9056 Ai

495
496
497
408
409
410
411
412
413
414
415
416
417
418
419

****************************'1<*********"'''''1-*'''***'''****'''***.''''1<''

MOil
MOV
JF1
MOV
SCANS: CLR

CURDIG,IICHflRNO
,PNTR0 STILL CONTAINS IIk'E~'LOC
@PNTR0·110
; JUMP IF ANV KEVS WERE DETECT!:.D
SCAN8
,CHANGE (LASTK'f) WHEN NO KEYS ARE DOWN
LASTK'r' .lI0FFH
F1

;
.' **********************"'*********t**************************
.:
THE NE~:r CODE SEGMENT IS THE INTERRUPT-DRIVEN PORTION OF THE 'DELA'T"
.:
UTILlW IT DECREMENTS RAM LOCATION "RDELAV' ONCE PER OI5PLAY SCAN
.:
IF 'RDELAY' IS NOT ALREADY ZERO
,; *******~**************************U,~~***'I<*"'***"**********"
•
PNTR1,IIRDELfI't'
MOil
, MOV
A.@PNTR1
SCAN9
JZ
[lEC
A
429
@PNTR1,A
MOV
421

422 ;
9957 83

423 SCAN9' RET
424 .
425 ; *"'**i:**************,....**,.+·'H*·"i·t·I~:i~·*j:~*"'i<** ..*t**..***ot,***..

**

426 ;
0057
0058 01
0059 '.1~
f.ju5A 04
0(l5E! 08
B0se 1(1
(U)5!i 2('

flf:!:oE 40
1:01<: CHRPOl)
c'
-i-JI
,'I;.
,(10003<110[: :~i)f. CHRPOL J
,Oeljc.l01tXlE· xO!': !~HRPOL)
r..1;
4:1
tIE
1300:)10000 mR CHRPOL)
.tJ2
J?:"f:
,0l3li100€JOB XOR CHRPOU
!)f:
4:?4
13(11000000 XOR CHRPOU
<010000008 ~)R CHRPOL)
41'5
r'8
f'f:
(100090996 XOR CHRP(JL)
4:6
437
438 fETECT

All mnemonics copyrighted @ Intel Corporation 1976.

1·40

intJ

Ap·40

ISI5-1i HCS-48.!UF'I-41 IW:~'O ~<:~,Et4BLE~, V2 Q
PAGE
AP40' INTEL I'ICS-48 l'fYBOIlPM\ISPLfI\I APPLICATION NOTE APPENtoIX
LOC OB)

SEt)

SOIJRCE STATEHENT

0(160 D5

m ,Hm
44q INlT

O~q BF08
006;: B:322

442

0065 BOFF

J4}

441

'313,,7

B~21

4~4

0069

BO~t0

4d 5
44t
447
448

(t06B 23Ht
3fl
9(t6E C5
006F 149E
,*161)

(tIm A5
0072 2,F(t
00?4 62
(1075 ~5
0Et76 25

12

INITlilL 12E5 PF.CiCE5S0.' REGiSTERS
SEL
RBi
~IOV
CI.IRD1G,ICHAPNO
i10V
PNTR~qWB[ oBUF
t,to'.!
@F'tm:o, 1I0FF H
1'10','
F'NTF:e, IltEYLOC

i'lO'!

@p~m.B,

t1CIV
'.I IJTL

ft, UNPI1SK
"INPUT. R

SEl

RBO

449

CALL

450
451
452
451

CL~
~10\1

CLEAA
fl
R., niCK
1. A

STF.'l

T

Ell

Term

r~ov

454
455 '

10
,SET BWIRECT IONAL INPUl LINES
,OTlLIT'r' FO", SETTING INITIAl.. DISPLAY REGISTERS.
; LOAD INTEFRIJPT RATE VALUE

; ENABLE lIMER INTERRUPTS

456 ;
457
458
459
46\1
461

,**~.* <*I *.•*~** .~*." ~*"'*.foH****"'***.fo**"***"'*******************

:
; ECHO
'
;

cllm.

FOF.' AN\' NEW KI::YSTROKES DETECTED
TRANSLATE EACH KEYSTROKE INTO ft SEGMENT PATTERN
HN[.' WPlTE IT INTO THE APPI"OPRIATE DISPLA'r' REGISTER

46} . .u t ~ ~ ..***~**-t.***'*~·******H********·~*********""'**.'.*"'*.*
4';4 ;

*

0077 148:;

"'*

007D 14DB
007F 0477

469
470
471

CALL
KBD IN
.' GE.T NEXT KE~'5TROKE
.JB5
F~E~'
'JUMP IF rEI' IN RIGHTHANI) COLUMN.
SINCE THE ACG IS USE~ !:ill ENrACe AND RENTR~', ns CONTENT 5 MUST
BE PROCESSED OR SAVEv E:EFORE ENCAGC 15 CflLLED
CALL
ENeAce
,FORt'1 APPROPRlftTE SEGMENT PATTERN
CALL
RENTP't'
: WIi (~'ATHER THAN ITS POSITION IN SWITCH MATRIX) IS
.lS9 .
FHiJRNED Ttl lHE AGCUt1IJLAlGF.' .
11011
PNT!?!' lWBDBl.f
~90 KBDIN

494

flDC,

f1 . lIBftli
'1. 1!F'NTR1
KBDIN
fl.. lIlEGNDS

I'{,

~95

110VP

A.I~A

008D ·9]

496

RET

491

111),.1

. 0987 21
@tl88 .28:

4~'"

;-·:CfI

4"'~

.JE·~

008A €G8E

ewe

; KBDSUF WILL BE MARKED AS CLEAR
,LOAe BUFFER

~ALUE

,ADD BASE OF KEY ENCODING TABLE
: OBTAIN BYTE REPRESENTING KEY SIGNIFIUlNCE

437 .
4?a ;

49, : WiNDS IS THE BflSE FOR TABLE SHOWING !:.E',' MATRIX SIGNIFICANCE
5€1A .
FOP THE V.El'BOA~·D lISED IN THE f'ROTOTT'PE.
501:
IT~ LA't'OIJT 15 AS SHOWN TO THE RIGHT.
50~

501

!~OTE

~;04

~05

5(i€;

TIiAT BIT ti-B!T4 MAY BE USED TO ENCODE KEY TYPE. IN THIS CASE:
BI14 INDICATES REGULAR DECIMAL DIGITS,
lIlT5 :NulCA7ES RIGHT-COLUI1N FUNCTION KE'iS,
8m INfoiCATES PUNCTUATION HARKS ( * AND I ),

507

t1138E
B08E 4F
0Q8F 11?
'13€19tl 4E
~€1~1

01392

28
17

0139:': 18
~B94 19
OO~5 24
f.l0~6

14
~B97 15
0€198 16
tt099 22
fitl9A 11
~09B 12
£1139( :1.3
01cl9D 21

508 LEGNDS

.$ AND eFFH\

5139
5113

4FH
Hlli
4EH
2SH
17Ii
1SH
19H
24H
14H

511
512
51:;
514
515
516

517
518

15H

519
5213
521

[is

22H

[.f;

522

vB

llH
12H

5~'~

DB
DB

~;24

.' USE LOW ORDER BITS .AS TABLE INDEX

PL>IGIT4==}

1

f'DIGlT5==)

4

PDIGIT6==)

7

8

PDIG\T7=)

.f

9

16H

2

(3)

•

(4)

II
V
Y
V
PINP1JT7 f'INPIJT6 PINPUT5 PlNPIJT4

EH
21H

525 $LTECi
All mnemonics copyrighted © Intel Corporation 1976.

1-42

AP·40
ISIS-II I1CS-48 J UPH1 ~IH(FO flSSEMBLER, 112. iii
AN0 INTEL ~ICS-4S r:E'T'BOft~:[);DISPLAY HPPllUHlON NOTE

LOC Of.J

PAGE

14

RPPEN[JI:~

SOIJRCE SlATEfiENT

c .... '7

.•

'~;

f.it!9E 2:'131;1
013140 B938
@13142 BF(tS
OOft4 A1
~1(IA5 19
B0A6 EFfl4
00A8 BF€t8
€tORFi 8:;

BORS F8
~OFIC A3
00AD C6B4
fJ0AF 14D9
00Bl 18
0@B2 fJ4AB
0€184 83

52B ;CUfiR WRITES 'BLANr:' CHARACTERS INTO ALL DISPLAY REGI5TEI79
5ee
581
582
583
584
585
586

MOvi>

4F
66
6D
7D
97
7F

587

61'
OOCA 77

593

geCB 7C

OO(,C 39
oocr. 5E
99CE 79

OOCF 71

588

589
590
591
592

1l,IOOPIHS
ft, @R

~'H

,C'Gf'ATS IS THE ~ASE FOR THE TABLE OF SEGMENT PATTERNS FOR THE BASIC
. DIGITS HERE '!HE FULL HEX SET (0-Fi IS lIlCLUDED.
; F& MANY USE", f;Pt'L1CATIOIIS, THE CHARflCTl£.' SET MAY BE AMEIIDED OR AUGJ1E,.TED
,TO !NCLlJDE AOOlTlOtIAL SPEClft PURPOSE PATTEPNS.
; FORMAT IS
PUFEDCBA
IN STAIIDARD SEVEN-SEGMENT ENCOOHIG CONVENTION
;
WHE~'E P ",EPRESENT~ THE DECIMAL POINT
DGPATS EQIJ
J AND flFf'H
DB
00111111B XOR 5EIJPOL
DB
000001108 '3!91:l1113B :~OR SEGPOL
011:1.1001B ;:OR SEGPOL
01110001B XOR SEGPOL

601 ; ********i:,f<:lo*1o:l<+..***i<**+************************************

602 ;
603 ;!{llSP WP.!TES BIT PATTERN NOW IN ACe INTO NEXT CHARACTEI? POSITION
604 ;
OF THE DISPLAY (NEf.TPLI.. ADJUSTS NEXTPL POINTEr? VALUE.
605 ;
IJ0D0 A9
OOD1 FF

OOD2

e:m

. OOD4 29
eros Ai
00D6 EFDA
8!ID8 BF98
OODA 83

IIESlllS IN DISPLAY BEING FILLED LEFT TO RIGHT. THEN RESTARTING

606 WDISP' 110...
60,
HOY
ROO
698
XCH
699

PNTRl, A
A, NEXTPL

A, IISEGMAP
A, PHTR!

610

MOil

~lR1.A

611

DJN~

NEXTPL/ WISP1
NEXTPL, .CHARNO

1'1(1\1
612
6B WDISPl RET
614 .:
615 $EJECT

All mnemonics copyrighted @ Intel Corporation 1976.

1-44

inter

AP·40

ISIS-II I'lCS-4S,'I.IFH! l'lAC:~1) AS5EHBlE~', V2. II
PAGE
Af'40 INTEL M(:5-43 I;E'r'BOAliD/DI5PLAY Af'PlICATION NOTE APPENDIX

LOC OB.T

5I)IJRCf

SEQ

16

STATE~1ENT

"'*..

616 ,*~~*~**~",****~*~' "'* ~***",.~>t-***'" ••.t***t**.t<*************>t-**",
617 '
61~ RErITR'r' SIJBROOTIlJE TO ENTER ACC CONTENTS INTO THE RWHTHOST uIGIT
619 .
qt.jD SHIFT EYE[(YTHING ELSE ONE PLftCE TO THE LEFT
629 ~'ENTj;"I' '10','
f'lITR1, JSEGI1AP+1

00DB B938

OO[l[l BFEtS

621

MOV

NE'~TPL.

a0DF 2i

622 RENm

:~tH

A. I!PtlTPl

e~a

62:

iii':

624

D.1HZ

62'5

MOV
RET

P'lTII1
NElITf'L .IIENTR1
NEnFL, ICHARNO ; POINT TO LEFTI'10Sr CHARftCTER

19

00E1 EFDF
00E3 BF9S
fJ0E5 83

f..26
627 '

ICHARNO

628 ; ~t l<.U "'.",fIB••'" •t"'***1"'''' .*~u ~~ io.H**",*'.*******,.",*********>t-•.t<
6~~ ;
630 ,f,'UPtIDD TOGGLE uEC!MAL poI'lT HI LAST CHAPACTER DISPLAY CHARACTER
6}1 • [)PR[l[l TOGGLES [>EC!l'IfIl. POINT IN THE CHARACTER POINTED TO ElY THE ACe
6::2 .
6?5 PDPAUD I'lIJ\'
634 UPA[l[" ADD
MOil
6J5
M!jV
6:;'"

ooE6 2391
00E8 0337
0aEf1 ft9
~J0EB F1

00EC D,81J
OOEE Ai
tll3EF ,n

:'l;oL
MO'l

637
638
6,9
640 .

,SET INDEX TO j;'IGHTllOST POSITION
; ACCESS DISPLA'r' REGISTER FOR [)£SI~ED PLACE

fl.i91H
A, iSEIjMAP
PNTR1, "I
tI,!!/'NTR1
11,IS0H
@PNTR1,1i

RE~

••••**.j<**********.**.*******.**"**

00ff3

641 . '*·H~. '~*."***************
•. 42 .
64~ ; HOl[l
SlJSl(OUTlNE CALLED WHEN KEY IS KNOWN TO BE DOWN.
644 ;
WilL NOT I1ETURN UNTIL KEl' IS RELEASED.
64S HOLD' SEL
R~t
f10li
FI, LASTK'r'
; {LASTKY)=0FFH IFF NO KEYS DOWN
646
647
SEL
IIEIB
64B
CPL
A
649
IN<:
HOLD

[is

001'1 FE
OOF2 C5
OOF3 37
0~F4

96F13

RET

"~9

OOF6 83

6'51 .

652 ;
653.;

*'" ~***************"'*************.*****************.j:********

654 . DELAl' SIJBROiJTlNE HANGS iJP FOIl THE NiJMBER OF COHPLETE DISPLAY SCANS EQUAL
655 ;
TO THE CONTENTS OF THE ACr:oHllATO~ WHEN CALLED.
656 DELAY' HOV
PNTR1, IRDELfll'

00F7 8923

657
1'1011
658 DELAY1. 110\1
659
JNZ
€.r50
IlET

00f9 At

90FA F1
OOFB 96FA
0ltFD 83

@PNTR1. fl
fl. @PNTlll
(lfLA'r'l

661 tEJECT

All mnemonics copyrighted

@

Intel Corporation 1976.

1-45

Ap·40
1515-II MC!'-481lIPl-41 Mi'lCRO "SSEMBlEI"· V2 f.i
PAGE
AP40. INTEL I'1CS-41'i I:EYBOAIMDI5PLflY APPLICATION tl01E APPEtlHX

LOC OBI
0100

17

SOURCE STATEMENT

5E(1

662 O~'1j
661 .

l00H

6£,4 . l·t~·''f<*.*~*·~H*~**t~**~.**t***'t*'f<*.t*~*****'"*,******'''********

665 ;'
666 ; TilE CODE ON THIS PAGE IS FOP. [;EMONSTFATlON PURPOSES ONLY667 . I T~UEL Y DOUBT iJHE THH Rl'N END IJSEPS HOIJLD LI KE TO SEE A NAtlE
66S ,POPPING 1.If· ON TIiEll" CAU).lLATOP SCl1EENS
6~9 .; HOWEvER. TIiE CODE SIl(~lN HEj;l DOES INDICATE HOW THE UTILITY SUBROIJTINES
';713 ; ItIfU.lDE[· IiEPE C(IIJLfo E:E FtCCESSED
67i . THE Io'OIJTItIES T'lEMSELI,IES ftF.:E CALLED WHEN ONE OF THE FOUR BUTTONS
Eo;'2 . 01/ Of H~ ~ IGIiT -Hfl"I£; 5I[IE OF THE PPOl (in'PE KEVBORI'D IS PFESSE(),
6(":

I

•. 74 ; *~ H·****.H:t **tt .***..t*··~ .****·*********t~.'t<"'* u"'.*'" ** ***.***'"

0100 1212
81iJ2 320E
0104 528A
010614H
fJ108 04,7

675
676
677
678

679
6813
681
682
683
684

WIA 342E
010e 9477

685
f,86

'
.•UN':TN PO'JTlNE TO 1I1PlEI'lENT OllE 0'" "'OUR DEi'll) UTILI TIES, ACCORDING
•
TO W~I(:H OF 'l'HE FOLl" FI.~f(TION KE~'S WAS P~E55EI)
FIJNCfN:JB0.
FIJNCTl
.)81
. FIJNCT2
FIJNen
.
JB2
'
FUIlCR (ALL
RDPADD
ECHO
JI>1P
.
FUNCB CHLL
TES13
Jt1P
ECHO

687 ;
Etl8E 3424
911B 94;7

688 FIJNCT2: CALL
JI1P
68~

1E5T2
ECHO

690 ;
TESTl
691 FllNCT1' CALL
JI1P
ECHO
693 ;
694 ; **~****.****.********~******"'****.j<~t****~***********.*****'*

0112 3416
0114 0477

692

9116 BF98

695,
696; 1E511 CODE SEGMENT TO FILL DISPLAY PfGlS1EI02
703

1'11)\1

MOI/
CRLl
CALL

[)..TN2
/'101/
RET

PNTR0,IICHARNO; SET FOR EIGHT LOOP REPETI1 IONS
f\. NEXTPL
ENCRce

W[lISP
PNTR0, Tsm
NElI'TPL IICHARNO

705 •

786 SEJELT

All mnemonics copyrighted @ Intel Corporation 1976.

1-46

; COP~I NEXT DIGIT INTO DISPLAY REGISTERS

inter

Ap·40

ISIS-II I'1('S-48.'UP1-41 HAC~O ASSEMBLER. Y2. (I
PAGE
AP48: INTEL MG5-48 m'BOAAD/D ISF'LA'r' APPLICATION NOTE APPEl'll) I X
SEQ

LOC OSJ

SOURCE STATEMENT

737 ,**~*****,~'io**~**~*******.j<*********.f<************"'**",*********
70S·
7~9 : TE5T2 WRITES THE SEGMENT PATTERN FOR 'JOHN' ONTO THE DISPLA',I.
719 ;
IdfiITS FOR ~ WHILE, AIID THEN CLEAPS THE DISPLAY
711 TE5T2: HOII
PNTR0, i,JOHN
CALL
PPINT
712
MOV
A.1100 , SCAN DISPLAV FOR 19a CYCLES
713
;'14
GALL
DELAY
,JI1P
GLEAP
m
716 '
717 : ~*·ft *~*.t*~1'*·~*"'Y*~**~*~***~'*-~* *****************************
718 •
';'19 ,: lESE ~JJB~'OlJTINE TO -ILL DISPLfiY WIlH DASHES
72(1 ;
JI.IMf'5 INTO SUBROUTINE 'CLEAR'
721 '
I1S SOON AS 1HE KE,' IS RELEflSED.
722 TESE mv
fl. ~91ee00e0B :~OR 5EGPOI. ; PATTE~N FOR '-'
72:;
CALL
FILL
;'24
CALL
HOLf'
l25
JMP
CLEAR
72f ;

0124 B8B5
0126 HAB

0123 2364
012A 14F7
012C 049E

012E 2340

ano

18

HAB

BE214F0

0134049E

727 ,.' I< ~*,.*** .•*·*:t .j<****~****:j.*********************.j<**************
728 '
729 END
LlSER S'T'MBOlS
ASFIYE 0902
DEBNCE 0004
FILL !JeRe
INn 8960
HCOlS 0004
PNTR0 0000
I"EFPl eel?
S(;AN~

01.134

TE5T2 0124

BLAN¥.
liE LA','
Fm'
lHPMSK
HEGlOG
PNTR1
REFRSH
SCAtl5
TESE

ASSEMBL Y COI'1PLETE,

9000
00F?
131381
00FB
00FF
0001

CHARNO
DELAY1
FIJHCT1
JOHN
NE>:TPl
POSLOG

0008
0eFF!
13112
0005
0007

0000
0010
~ENTI?1 00DF
003F ' SCAN6 131345
012E

TICK

FFF0

CHRPOL
DGPATS
FIJII(;T2
V-BDBUF
NREPT5
PliiNT
RENT,,"Y
SCANS
mNT

0000
BOCa

lUBE
0022
002'"

9BAB
130LlB
004F
0007

NO ERRORS

All mnemonics copyrighted © Intel Corporation 1976.

1-47

CHRS1B
DPADD
FUNCB
KBDIN
HROWS
PRNTi
ROTeNT
SCAN9

T1RET

0057
00E8
€110ft
a083
9004
0084
0005
0057
fJOOE

ClEAP.
ECHO
FLINCH
KEYlOC
NXTLOC
PSGl'INT
ROTPAT
SEGl'IAP
TST11

099E

mm

0106
0921
0023

0008
00134

0037
911A

ClRl
ENCAce
FUNC1N
LASTKY
PIHGlT
RDELAY
SCAN
SEGPOl
WISP

9BA4
BBBA
9100
0806

0919
0023
00lE
0000

001)0

CURDIG
ENCMSK
HOlD
LEGHOS
PII/PUT

8007

800F
OOFC
008E
9009

R()f'fl()D 119E6
SCAN1 0021
TEST1 9116
WDlSPl OODA

intJ

AP·40

1515-II RsSEf1BlE~ S'r'1tBOl. (:~s REFEm/CE, ..,2 8
ASA\IE

BlAtl<

292.
179.

CHARNO In.
CHFPOL 169.
CHRSTB 282
CLEAI1 449

5:'>4l1
CIJRDIG 286.
DEaNeE 178.
[)flAY 656.
[.oELR'.'l 658.
[IGPAiS· 574
CL~l

DPflOC'
ECHO

ENCAce
ENC/'ISK
FILL
FKEY

HOLD

532.

723
4731
6911
6881
68511

466

679
688
682.
47:.>
645.

465
2m

205.
494
175.
1671
2121
174.
329.
158.
1681
1911
549
1921

POSLOO 1661
~NTl

PSGtlNT

I1DELA'r'
RDPAOO
REFill
REFRSH
RElITRl
REIfTR'r'

441
431

715

725

289

683

405

5n
432

537
433

395

485

441

686

689

692

612
434

621
435

625
436

697

698

783

5491
551
15911
2161
633.
2821
268
622.
470

700

573

678#
649
448.

724

446

711
386
499.
300
359
508.
328

1m 533

623

PRINT

430

714
659
5831

471
573J

562.
JOHN
KBDBlJF 214.

PNTR1

269
531

:m

465.
469
lSs'

236
INIT
INPHSK 171.

KBDUI
KE'r'LOC
LRSTKV
LEONeIS
NCOL5
NEGLOG
NEXTPL
NFEPTS
NFOWS
NXTLOC
PDIGIT
PINPUT
PNTRIl

1

534.

FUNCl1 678

PJNCT2
FIJNCT3
FIJNCT4
FIJNenl

249
288
228
429
4281
5311
536
283

PAGE

442
493
389
368

499
444
365

486

646

536

537

697

611

612

621

624

625

697

699

783

361

379
711
418
656

388

383

386

367

389

399

486

442

443

444

445

421
657

499
658

492

532

534

535

696

689

619

628

622

361
392
285
381
309
554
299
635
169
555
5561
281
417
682

447
356
698
291
636
170
712

m

417
636

292
656

288.
624
620.

All mnemonics copyrighted © Intel Corporation 1976.

1·48

inter

Ap·40

ISIS-I I ASSEHBLER SYMBOL CROSS

2l'!411

328

R01Pfli 293.
StfiN
300.

:;30

392
391

380.
371

]131

~OTCNT

SCAN1
SCANs
SCANS
SCAN6
SCANS
SCftN9
SEGflAP
5E~OL

rEST1
TEST2
TESE

TICK

328.
362
331
395.
497

395
220.
17911
593
691
688
685
177.

T!lHT
TlRET
T5TH
W['lSf'
WDISP1

269.
699.
552
611

CROSS

REFE~ENCE

409.
419

REFE~ENCE.

384

389.

629
564
597

V2 fJ

PfiGE

423.

2&8

m

280
594
697.

m

698
563

595

596

634
565
598

566
599

584
722

7111

722.
250

451

248'

792

606.

2

,(11

6131
COMI'Lf.TE

All mnemonics copyrighted @ Intel Corporation 1976.

1-49

585

586

587

588

589

590

591

!l92

--

inter

APPLICATION
NOTE

Ap·49

January 1979

9800904

© Intel Corporation 1979

1-50'

AP·49
INTRODUCTION

however, is more economic than technical; these same
peripheral chips which are such a bargain when coupled
to a microprocessor such as the MCS-85 or 86, have a
significant cost impact on a single chip microcomputer
based system. The high speed of the 8049, however,
makes it feasible to implement a serial link under software control with no hardware requirements beyond two
of the I/O pins already resident on the microcomputer.

The Intel'" MCS-48 family of microcomputers marked
the first time an eight bit computer with program
storage, data storage, and I/O facilities was available on
a single LSI chip. The performance of the initial
processors in the family (the 8748 and the 8048) has
been shown to.meet or exceed the requirements of most
current applications of microcomputers. A new member
of the family, however, has been recently introduced
which promises to allow the use of the single chip
microcomputer in many application areas which have
previously required a multlchip solution. The Intel'" 8049 virtually doubles ·processing power available
to the systems designer. Program storage has been increased from 1K bytes to :ilK. bytes, data storage has
been increased from 64 bytes to 128 bytes, and processing speed has been increased by over 80%. (The 2.5
microsecond instruction cycle of the first members of
the family has been reduced to 1.36 microseconds.)

There are many techniques for implementing serial I/O
under software control. The application note "Application Techniques for the MCS-48 Family" describes
several alternatives suitable for half duplex operation.
Full duplex operation is more difficult, however, since it
requires the receive and transmit processes to operate
concurrently. This difficulty is made more severe if it is
necessary for some other process to also operate while
serial communication is occurring. Scanning a keyboard
and display, for example, is a common operation of
single chip microcomputer based system which might
have to occur concurrently with the serial receive/transmit process. The next section will describe an algorithm
which implements full duplex serial communication to
occur concurrently with other tasks. The deSign goal
was to allow 2400 baud, full duplex, serial communication while utilizing no more than 50% of the available
processing power of the high speed 8049 microcomputer.
The format used for most asynchronous communication,
is shown in Figure 1. It consists of eight data bits with a
leading 'START' bit and one or more trailing 'STOP' bits.
The START bit is used to establish synchronization between the receiver and transmitter. The STOP bits ensure that the receiver will be ready to synchronize itself
when the next start bit occurs. Two stop bits are normally used for 110 baud communication and one stop
bit for higher rates.

It is obvious that this Increase in performance Is going
to result in far more ambitious programs being written
for execution in a Single chip microcomputer. This article will show how several program modules can be
designed using the 804g. These modules were chosen
to illustrate the capability of the 8049 In frequently encountered design situations. The modules included are
full duplex sarialllO, binary multiply and divide routines,
binary to BCD conversions, and BCD to binary conversion. It should be noted that since the 8049 is totally
software compatible with the 8748 and 8048 these
routines will also be useful directly on these processors. In addition the algorithms for these programs
are expressed in a program design language format
which should allow them to be easily understood and
extended to suit individual applications with minimal
problems.

FULL DUPLEX SERIAL
COMMUNICATIONS

I

Serial communications have always been an important
facet in the application of microprocessors. Although
this has been partially due to the necessity of connecting a terminal to the microprocessor based system
for program generation and debug, the main impetus
has been the simple fact that a large share of microprocessors find their way into end products (such as inteliigent terminals) which themselves depend on serial
communication. When it is necessary to add a serial link
to a microprocessor such as the Intel'" MCS-85 or 86 the
solution is easy; the Intel'" 8251A USART or 8273 SOLC
chip can easily be added to provide the necessary protocol. When It is necessary to do the same thing to a
single chip microcomputer, however, the situation
becomes more difficult.

BIT

01

02

03

04

05

06

07

08

BIT

Figure 1.

The algorithm used for reception of the serial data is
shown in Figure 2. It uses the on board timer of the 8049
to establish a sampling period of four times the desired
baud rates. For 2400 baud operation a crystal frequency
of 9.216 M Hz was chosen after the following calculation:
f = 480N(2400)(4)
where 480 is the factor by which the crystal frequency is divided within the processor
to get the basic interrupt rate
2400 is the desired baud rate
4 is the required number of samples per
bit time
N is the value loaded into the MCS-48
timer when it overflows

Some microcomputers, such as the Intel 8048 and 8049
have a complete bus interface built into them which
aliows the Simple connection of a USART to the processor chip. Most other Single chip microcomputers,
although lacking such a bus, can be connected to a
USART with various artificial hardware and software
constructs. The difficulty with using these chips,
00670A

STOP

START

1·51

AP·49
The value N was chosen to be two (resulting in f = 9.216
MHz) so that the operating frequency of the 8049 could
be as high as possible without exceeding the maximum
frequency specification of the 8049 (11 MHz).

I

STIRT IF RECEIVE ROOTII£

11 IF RECEIVE FlOO=e ll£N
;2
IF SERIAL Itf'IJT=SPfn ll£N
13
RECEIVE FlAG:=1
13
BYTE FINISI£)) FlAG:=8
12
OOIF
I 1 ELSE
SINCE RECEIVE FlAG=1 ll£N
:2
IF SVI«: FlOO=e TI£N
;3
IF SERIAL 11f'UT=SPfn ll£N
14
SVI«: FI.J1G:=1
;4
DATA: =88H
;4

SffIPLE CNTR:=4

;3
;4

ELSE
SINCE SERIAL 1If'UT=ItfRK l"1£N
RECEIVE FlOO:=8
;3
OOIF
; 2 ELSE
SINCE SVI«: FLAG=1 ll£N
SRlf>LE ro.M£II: =SRIf>LE CtlWTER-1
;3
;3
IF SRlf>LE ro.M£II=8 ll£N
SRlf>LE COUNTER: =4
:4
;4
IF BYTE FINISIED FlOO=e ll£N
;5
CARRY: =SERIAL IIf'UT
;5
SHIFT DATA RIGHT WITH CARRY
:5
IF CAR!1Y=1 ll£N
:6
(J(DfITA: =DATA
:6
IF DATA REf¥)\' FlOO=e THEN
;7
ME FINISI£)) FLAG=1
16
ELSE
;7
BYTE FINISNED FLAG:=1
;7
OYEl/Rlll FlAG: =1
;6
OOIF
15
OOIF
14
ELSE
slta ME FINISNED FlAG=1 ll£N
15
IF SERIAL 1If'UT=IIfIRK ll£N
,6
DATA REf¥)\' FlAG: =1
;5
ELS!:
SINCE SERIAL IIf'UT=SPACE TI£N
;6
ERROR FlAG: =1
15
OOIF
15
RECEIVE FLRG:=8
:5
SYNC FlAG: =8
;4
OOIF
:3
ENOIF
12
ENOIF
; 1 ENOIF

Once the meaning of these flags are understood the
operation of the algorithm should be clear. The Rece/lfe
Flag is set whenever the program is hi the process of
receiving a character. The Synch Flag is set when the
center of the start bit has been checked and found to be
a SPACE (if a MARK is detected at this point the receiver
process has been triggered by a noise pulse so the program clear!. the Receilfe Flag and returns to the idle
state). When the program detects synchronization it
loads the variable DATA with 80H and starts sampling
the serial line every four counts. As the data is received
it is right shifted into variable DATA; after eight bits
have been received the initial one set into DATA will
result in a carry out and the program knows that it has
received all eight bits. At this point it will transfer all
eight bits to the variable OKDATA and set the Byte
Finished Flag so that on the nextsample it will test for a
valid stop bit instead of shifting in data. If this test Is
successful the Data Ready Flag will be set to indicate
that the data is available to the main process. If the test
is unsuccessful the Error Flag will be set.
The transmit algorithm is shown in Figure 3. It is executed immediately following the receive process. It is a
simple prograr:n which divides the free running clock
down and transmits a bit every fourth clock. The variable
TICK COUNTER is used to do the division. The Transmitting Flag indicates when a character transmission is in
progress and is also used to determine when the START
bit should be sent. The TICK COUNTER is used to determine when to send the next bit (TICK COUNTER MODULO 4
0) and also when the STOP bits should be sent
(TICK COUNTER = 9 4). After the transmit routine completes any other timer baseq routines, such as a keyboard/dispJ'ay scanner or a real time clock, can be
executed.

=

; STfRT IF TRIIISIIIT ROOTII£
11
; 1 TIC!( CIXM'ER:=T1CK CIXM'ER+1
; 1 IF TICK ro.M£II IQ) 4=8 THEN
;2
IF TRIIISIIITIlt«l FlAG=1 ll£N
;3
IF TICK CWITEA=88 1818 88 BINfRY ll£N
;4
TRANSJ1IlTlt«l FlAG: =41
I3
ELSE
IF TICK CWITEA=88 1981 88 BINfRY THEN
;4
SEll> 00 IR!K
I oj
TRIIISIIITIlt«l FlAG: =8
I3
ELSE
SINCE TICK ClXM'EROTHE fIIOYE COUNT 'll£N
14
SEll> NEXT BIT
;3
OOIF
; 2 ELSE
SINCE TRANSJ11TT1t«l FlOO=e THEN
I3
IF TRIIISIIIT REIllEST FlAG-"1 THEN
;4
XIITBVT: =NXTBYT
;4
TRANSIIIT REUST FlAG: =8
;4
TRANSJ1ITTlt«l FlAG: =1
I 4
TICK COUNTER: =8
; oj
SEll> SYNC BIT (SPACE)
13
ENOIF
;2
ENOIF
;100IF

Figure 2

The timer interrupt service routine always loads the
timer with a constant value. In effect the timer Is used to
generate an independent time base of four times the reo
quired baud rate. This time base. is free running and is
never modified by either the receive or transmit programs, thus allowing both of them to use the same
timer. Routines which do other time dependent tasks
(such as scanning keyboards) can also be called periodically at some fixed multiple of this basic time unit.
The algorithm shown in Figure 2 uses this basic clock
plus a handful of flags to process the serial input data.

Figure 3

All mnemonics copyrighted CO Intel Corporation 1979.

1-52

inter

Ap·49
the 8049. Also included in Fig. 4 is a short routine which
was used to test the algorithm.

Figure 4 shows the complete receive and transmit pro·
grams as they are implemented in the instruction set of

ISIS-ll P1C5-48.'IJPH1 "AeF:) ASSEMBLER, Y2.

lOC OBJ

SEg

SOURCE

e

STATE~lEm

-l<

THIS f'ROORAtl TESTS THE FUlL l~JPLE;, COMMIJIHCATIOI-I :,UFTWARE

*
*
5 .; *****-t<**·t,..**tt*·H*-t<**$** .. **·~t**tt*·~*·~i4~·*-t"t********:t***-t<**·!:.f<:l>*******-t<**'i'****-t:*
6.
7 $INCLur'E( :F1.UPTEST PDl)
8 ;
9 ;
11) i

START OF '1 EST POUT! HE
====================

11.
12 .

13 '
14 ;

15 .
16 ,1 ERROR COLINT =8
G
18
19
20
21

91300
0000 C5

0001 2400

;1 REPEAT
;2
PATTERN Al
:2
lNHlALIZE TIMER
.2
CLEAFI FLAGB'm
,2
FLAG1 =t1AP.r.
22:2
REPEAT
23 ; 3
IF TRflNS~lIT REQUEST FLAG=9 THEN
24 ; 4
rmB'T'TE: =PATTERN
2~. ,4
rPAN5M n REQUEST FLAG=1
26 ; 7
ENDIF
27 : ~
IF DATA READ'" FLAG=1 THEN
28 ,4
PATTERN. =O¥l)ATA
29 ; 4
[*ITA FIEADI' FLAG =0
J0 ; 3
E"'[lJF
31. 2
UNTIL ERPOR FLAG OR OVERRUN FLAG
32 ; ~
mCPEMENT ERROR COUNT
n, 1 I),.,TIL FOREVEF!
34 . EOF
:>5 tEJECT
36
ORG
0
37 .1 SELECT REGISTER BAt,'K B
33
SEL
IiS9
:>9 ; 1 OOTO TEST
40
.IMP
TEST
41 $
INCLU(JE<.F1·UAIITI
42.
4:1 ,
44 ;
A5'ltlCHRONOU5 FIECEIIiE/TRANSMIT ROUlINE
45 ;
===================================
46 ;
THIS ROIJTINE RECEIVES SH:IflL COOE USING PIN TO AS R;,1)
47,
AND CONCIJRREtllLY TRANSMITS USING PIN P27
48;
NOTE.
49 ;
THIS ROUTINE USES FLAG 1 TO BUFFER THE TRANSMITTED
Figure 4

All mnemonics copyrighted © Intel Corporation 1979.

1-53

inter
LOC OSJ .

Ap·49
SEQ

SOURCE STRTEItENT

59 ; 1 [lATA LINE. THIS flIlHNflTE5 THE JITTER THAT
51 ,1 WIll.D BE CRUSEll BY YAFIATlOIIS IN THE RECEIVE
= 52 ,1 T1I'1ING. NO OTHER Pf,'1BA14 11AY USE FLfIf.i 1 WHILE
53 ,1 THE TIMEii' IrITERPUPT IS ENABLED
54 ;
55 ;
56;
'57 '
58,
59 .
60 i

61

PfGlSTEP. ASSIGllIft:.NTS-8Alt:l

=============__T~_==

i

0007
0006

= 62;
= 63 ATEMP EQIJ
= 64 FLGBYl EQU

9005
0004
0000

65
66
67 SAl4CTI1 EOU
= 68 TCKCTF EOU
=. 69 REGe Eoo

R7

116
f;'S,

114
R0

;
;
;
;
;
;
;

USED TO SAllE Af..ctJ'IULA' ~ CONtENTS WRiNG INTERRII'T
CONTAINS YfII;lOUS FLAGS 1.&0 10 COIITRQ.
f(£CEI'fi
AlID TAAIl5t11T Pf.:Qr.£SS. SEE CON5TANT DtflNITIOOS FOR
THE I1EfIIHNG OF EACH BIT
SAl'lf'LE CtlJlTEI1 F~ THE RECIEYE f'ROCES!:I
SAl'lf'LE CtlJNTEP FOIl THE TRANSI'IIT PROU:S!i
USEr, ~ POINTER Rl:G1STER

;
.'
,
;

I1EcmE RETlJINS Yf1L1D MTA IN THIS BYIE
RECEIIri ACctll1llATES DATA IN THIS BYTE
CONTAINS BYTE llElMjTRANSI1JlTED
COIlTAIt.'5 Tit: NEXT BVTE TO BE TRANSI1ITlED

'1£

70 ;

0029
0021
9022
9923

=
=
=
=
=

71 ;

Ii'A14 ASSIGltlENTS

72 ;

======:========

n;

74 I'IOt::DAT EQlJ
?S I'II)ftTA Eoo

76 IIXI1TBY EQlJ
77 ItI'..lTBY EOO
= 78 $EJECT

201i
21H

22H
23H

= 79 :
=
=
=
=

80;
81 ;
S2:
83 :

= 84 .;
0091
0002

Il904
0098

0019
0029

0049
0089

=
=
=
=

85;
86;

CONSTANTS
=======
THE FOLLOWING COOSTANTS ARE USED TO ACCESS THE FLAG BIlS CONTItINED
IN REGISTER FLGM

RCYFLG EQlJ

91H

SYNFLG EQIJ

92H

B't'FIfL EQlJ

94H

ctJu

08H

95 ERRFLG EOIJ
96
= 97 TRRQFL EQU
= 98
99

llJH

87
88
89
= 99
91
= 92
93
94

DRlWFL

= 199 .
= 191 TRNGFL EQU
= 102
= 19l OYRUN EOU
= 104

29H

40H

:
:
;
;
;
;
;
;
i

;
,
;
;
;
i
I

80H

;
;

5I:T WI£N START Bll IS FIIIST OETEm.D
RESET WHEN RECEIVE PROCESS IS COI1Pl.ETE
SET IoIHEN STAPT flIT 15 IIERIFIED
RESET WHEN RECEIVE PROCESS IS COI'IPLETE
RESET IlfEN STA.~T fjIT IS FIRST DETECTED
SET HN THE EIGHT !!ATA BIlS IfIYE fU BEEN kECEIVED
SHOULD BE RESET BY I'IfIIN PR~API WHEN DATA IS Att;EPTED
SET BY RECEIVE PROCESS WHEN STOP 8IHS) ARE VERIFIED
SHOULD BE RESET BV I1IIN I'ROORAPI WHEN SRIIPLEIJ
SET BY RECEIVE PIWI'.£SS IF A ~RAtlII«l Ekkill IS DETECTED
TESTED BY tIfliN PROCiRRI'I TO DETERftH£ I~ Rl:Ill>Y 10
TAANsI'IIT A rlEW BYTE-SET TO INDICATE 1HAT NXTBYT
HAS BEEN LOADED
I1ESET BY TRANSI1IT PROCESS IHN BYTE IS ACCEPTED
SET WHEN TRANSI!ISSION OF A BYTE STARTS
RESET WHEN STOP fjlT IS TRANSIItnED
SET BY RECEIVE PROCESS WHEN OYERUN OCCURRS
SHOULD BE RESET BY PlAIN PliOORAl'! IIIlN SAlRE:D

Figure 4 (continued)
All mnemonics copyrighted  Intel Corporation 1979.

1·54

inter

AP·49
LOC 08.1

90S9
FF7F

9900

SEQ

= 105
= 106
= 107
= 198
= 199
= 119
= 111
= 112
= 113

= 114

SOIJRCE STATEMENT
i

;
;

GENERRL COrlSTANTS
=================

i

E(lU
MARK
SPACE EQlJ
STPBTS EQlJ

80H
USED TO GENEFATED A !'lARK
NOT OOH ; lISED TO GENERATE A SPACE
9
COtlTROLS lHE NUMBER OF SWP BITS
9 GENERRTI;S ONE STOP BII
1 GEUERATES TI.'O SlOP BITS

i

= 115 $EJECT

= 116 ;

0097

0997 160A
0009 93
eallA 1)5

0fI0Il AF

000c 23FE
000E 62

= If?
= 118
= 119
= 129
= 121
= 122
= 123
= 124
= 125

;
;
;

ORO

9911 9A7F
9013 0417
9015 BAS0

0017 FE
0018 1224

001F1 3664
00lC FE
9010 4301
00lF 53FB

0021 AE
8022 13464

0I:l07H

i1

ENTER I NTERRUPT MODE
JTF
UART
RETR
UART: SEL
RB1
= 126 ; 1 SAYE ACCUMl.lATOR CONTENTS
= 127
1'101'
ATEtlP, A
= 128 ; 1 RELOAD TIMER

TI SR .

= 129
= 130
= 131 ;

1'1011

A, ITIHCNl

MOIl

T,11

= 132

OUTPUT Txt> BUFFER (Fl) TO TXD 110 LINE (P27)
=================================

;

= 133.,
ooeF 7615

START OF RECEIVE/TRANSMIT INTERRUPT SERVICE ROUTINE

= 134 ;
= 135
= 136
= 137
= 138
= 139
= 140
= 141

JF1
OMARK
OSPACE' ANL
P2, tlSPACE
JI1P
RCYOO0
O~1ARf(
ORL
P2, IHARK
;
;
START OF RECE lYE ROUTINE
=================
;

= 142

i

= 143
= 144
= 145
= 146
= 147
= 148
= 149
= 150
= 151
= 152
= 153
= 154

; 1 IF RECEIVE FLAG=0 THEN
RCVOO0: ItOIi
A, FLGBYT
JB9
RCV~19
;2
IF SEFI AL IIlPUT=SPACE THEN
JTfl
XMIT
;3
RECEII/E FLAG:=!
MOV
A, FlGBYT
ORL
A. tlRCIIFLG
.' 3
BYTE FINISHED FLAG: =8
AIIL
A,
BYFNFL
;2
ENDIF
MOl!
FLGB'r'T. A

.,m

= iSS
= 156
= 157
= 158
= 159

JMP

XMIT

; 1 1:15£
SINCE RECEIVE FLAG=1 THEN
;2
IF SYNC FLAG=8 THEN
RCW310. JB1
RCV939
d
IF SEFIAL INPUT=SPACE 1HEN
Figure 4 (continued)

All mnemonics copyrighted © Intel Corporation 1979.

1·55

inter

Ap·49
Loe OSJ
0026 3633

S()I.P.CE STATEMENT

SEQ

JTe

= 160
= 161 ; 4

RCI/029
5YOC FLAG' =1

m.

802F 0094

:: 162
= 163
= 164 . 4
= 165
= 166
= 167 ; 4
= 168

00?1 0464

= 169

JMf'
ELSE

0028 4302
oo2A HE

0028 8821
002D B0S0

= 170 .:,
0033 53FE
0035 AI:
0036 0464

00313 ED64

903A 8004

003(' 5259
903E 97
903F
0041
0042
9044

2642
A7
BS21
Fe

0045 67
0046 AO.
0947 E664

SlKTIi', 14

~y

XI1 IT
SINCE SERIftL INPUT=I'1ARK THEN
k,[CEI~'E FLfI(i.=0

= 171; 4
. = 172 Ii'CI/029'

ANL
AdlNOT RCYFU;
ENOIF
1'101,'
FLGf:I'L A
= 17'5
JMf'
XI1lT
= 176; 2 ELSE
SINGE SYNC ~LAG=l THEN
= 177 .3
SAMPLE COlINTEIi' =SAf1PLE COUNTEP.-l
= 178 I1CI/030 DJNZ
SAt1CTR, >''1'1 IT
= 179 ,3
IF SP.llPLE (,OlINl Er;:=e frifN
= 189 ; 4
SAI'lPLE COUNTER: =4
SAI1CTR,14
HOV
= 181
= ~82 ;4
I F B~'TE FItll SHED FLAG=0 THEN
RCI/950
= 183
= 184
CLR
!.'\
= 185 ; 5
CARR'T" =SERlftL INP/Jl
JNTO
I?CI/040
= 186
CPL
C
= 187
R0, .HDATA
= 188 I1C\l940 I'IOV

= 173 ;].
= 174

m:;:

= IS9
= 199 ; 5
= 191
= 192
= 193 ; 5

PlOY
RRC
!'lOY

.INC

=194

= 195

!6

0049 BS29
9048 A0

=196
= 19(

1'I0V

004C FE
004D 7254

= 199
= 200

I'IOV·
JB3

=201.,
= 202
= 203

OK

904F 4304
9951 AE
0052 0464

A, lIS'ltflG

FLGBYT. R
DATR: =80H
MOl,'
Re, OOATA
PlOY
@R0 ••8011
SAI'IPLE CNTR' =4

19)'.,'

=1913 ,;6

= 2134
= 295 ;6

I'IOV

A,~Re

SHIFT DATA "'1(jBT WI1H CARR..'
A

@F0,A
IF CARRI'=1 THEil
;':MIT

(}KOATA . =DATO
110.II'1OKDAT
~RO, A
IF [lATA RElICI,'

1'I0V
1MP

= 209
= 210
=211

Bt'lE FINISHED FLRG=1
A,tBYFNFL
FLGBYT, A

xrm
ELSE
BYTE FINISHED FLfiG: =1
OVERRIJN FLAG, =1

; 1'1(1','
ORL
I'IOY

= 212 ; 6
=213.;5
0057 9464

= 214

JI1P

A, FLGBYT

A, «(Bl'FNFL OR Ol/RUN)
FLGBYT,A
ENDIF
ENDIF
XMIT

. Figura 4 (conllnued)
All mnemonics copyrighted © Intel Corporation 1979.

lHEf'

[lCV045

=296;1'
= 207 ; 7
= 298 RC1I045:
0054 4384
0056 AE

FLAG=~

A.. FLGBYT

1-56

inter

AP·49
LOG OBJ

0059 26SF
0058 4308

eosl) 0461

0961 53FC
0963 AE

SEQ

= 215
= 216
= 217
= 218

SOLIRCE STATEI'1ENT

;4
;5

elSE,

SINCE BYTE FINISHED FLAG=1 THEN

IF SERIAL IHPUT=MARK THEN

RCY!I50: JNT0

RCV060

DATA READ',' FLAU: =1
A;'DRD'T'FL
= 219
OPL
ReVEl70
= 229
.IMP
ELSE
SINCE SERIAL INPUT=5PACE THEN
=221;5
eRROR FLAG. =1
=222;6
A••ERRFLG
= 223 Rel/a60: ORL
ENDIF
= 224 ,;5
= 225 ; 5
RECEI','\: ~LAG. =9
= 226 ; 5
5'r'NC FLOO:=!!
= 227 ReVEl7e. AHL
A.llroT(SVNFLG OR Rel/FLG)
= 228
MOV
FLGB'n. A
= 229 ; 4
END IF
= 2~9 ;:?
ENDIF
= 231 ; 2 EIIDIF
= 232 ,1 ENDIF
= 2:£3 rEJECT
= 234 ;
= 235 ;
STAin OF TRANSM IT POUTI NE
;6

= 236 ;

= 237 ;

=======================::

= 238 ; 1
0064 1C
006S 2303
0867 SC
0068 9697
006A FE
006B 37
006C 0286

006E 2324
0070 ric
0071 96;'B

ean

A5
0074 8'5

= 239
; TRANSMITTER OUTPUT BIT IS P2-7
= 240 ; 1 TICK COUNTER. =TICK COUHTER+1
= 241 XMIT: INC
TCKCTR
= ~42 ;1 IF TICK (;QUNTER "00 4=0 THEN
= 243
tolOV
A, .03H
= 244
ANL
A. TCKCTR
= 245
JNZ
RETURN
= 246 ; 2
IF TRRNSI'1ITTING FLOO=l THEN
= 247
MOV
A. FLGB'r'T
= 248
CPL
A
= 249
JB6
XI'1T040
= 259
IF STPBTS EQ 1
= 251 ; 3
IF TICK COUNTER=09 1910 00 BINARY lHEN
= 252
"011
A••28H
; CONDITIONAL ASSEMBL I'
= 253
XRL
A. TCKCTk
= 254
.JNZ
XI'ITB19
= 255 ; 4
TRANSMlTIING FLAG: =0
= 256
MO\I
A. FLGBYT
= 257
AHL
A. tNOT TRNGfL
= 258
1'1011
FLGBYT. A
= 2'59
JMP
RETURN
= 269
ENDIF
= 261 ,3
ELSE
IF TICK COUNTER=OO 1001 00 BINARY THEN
= 262 Xl'fT910: MOY
A••24M
= 263
XRL
A. TCKCTR
= 264
1HZ
('I'IT020
= 265 ,4
SEND 00 MARK
= 266
CLR
F1
; SET FLAGl TO MARK
= 267
CPL
F1
= 268
IF STPBTS EQ 9
= 269 ; 4
TRANSMITTING FLAG:=0
Figure 4 (continued)

All mnemonics copyrighled

e Inlel Corporation 1979.

1-57

intJ

Ap·49
LOC OB'!
9075 FE
9076538F
8878 AE
8879 9497

SEQ

SOORCE STATEI'IENT

= 270'
= 271
= 272

007D F0
907E 67
907F All
!l080 AS
0881 E697
0883 B5
0084 9497

=2?3
= 274

~TURN

ENDIF
ELSE

sna

TICK COOO'ER C)THE ABOI/E COUNT THEN

CLR

F1

JtIC
CPL

RETURN ; GO TO

JMP

RETURN

8823

-= 284
= 285
-= 286
= 287
= 288
-= 289
-= 290

F0

-= 291

BS22
A0

0097 FF
0098 93

F1

ENDIF
ELSE
SIt«:E TRANSMITTING H.AG=0 THEN
;3
IF TR~IS11I! REQUEST FlAG=l THEN
X1'1T940: JB5
R E T U R N ' FLAG BYTE THERE
,4
XIITBYT :=NXTBVT

= 292

MOil
1'10\1
1'1011

R0, IIIIIXTBY
A, @RO
RIl.• I/'IXIITlW

-=

MOY

@RIl,A

m

-= 296

0094 BC00

; FLltO 1 Will BE USED TO BlfFER 00
Rm~N PO nIT IF TXD=SI'I1CE (9)
; ELSE COMPLEI1EIIT FlAG 1 TO A tlARK

;:1
;2

= 294 ; 4
= 295
0091 4340
8893 fIE

= 297
= 298
= 299
= 390
-= 391
= 392
= 393
= 394
= 305

,4
.

. TRAIlSI1IT REQl(ST FLAG: =0
I'IOY
A, FUlBYT
Ali.
A, fNOT TRRQFl
TI"ANSl'IITTIIIG FlA(;: =1
ORL
A,ITRtIGFl
I'l0\l. FlGBYT, A

,4

TI CK COUNTER' =0
TCKCTR,1I0
;4
SEN!) S~'NC BIT (SPftCE) .
Cll!
F1
; SET FLAG 1 TO CAUSE A SPACI:
;~
ENDIF
;2
ENDIF
=396 ; 1 ENDIF
= 307 I1ETURN:
-= 308 ; 1 RESTORE ACCut1I.lATOR
= 399
t1O\I .' .A, ATEI'If'
= 310
RETR
311 $EJECT
P'.oy

]12 ;

9190
FFFE
901E

00lD
OO1C

0007
0006

; CONDITIONAL ASSEI'IBlY

= 276 ,4
SEND NEXT BIT
= 277 00920: i'KlY . RIl,II'IXItTBY
= 278
i'KlY .
A,fRO
= 279
~RC
A
@RIl,A
= 280
MOIl

= 281
= 282
= 283

00S6 8297
0988
008R
008B
. 9900

JI'I'

Ali.

= 275 ;3

8878 8822

I10V

A, FLGB'r'T
A, IINlT TRNGFL
FlGB'r'T, A .

f'tOY

3B;

START OF TEST ROUTINE

314 ;
315 '
316
m T1MCNT
318 HFLGBY
319 115A11CT

=============

320
321
322
323
324

ORG
EQIJ
EOO
EQIJ
"TCKCT EQIJ
;
ERRCNT EQU
PAn
EQU
;

019011

:-2

lEH
100

lCH
R7
R6

Figure 4 (continued)
All mnemonics copyrighted <0 Intel Corporation 1979.

1·58

Ap·49
LOt OBJ

9199 BFOO

91!12 BEOO
9194 23FE
01% 62
9107 55

9100 25
9199 881E
9UIB

aeee

8190 A5

911lE 85

81eF 881E
8111 Fe
9112 8224

0114 B923
9116 FE
8117 Al

SfJJRCE STATEI1ENT

SEQ

325
326
327
328
329

;
;
,; 1 ERR~ COONT: =9
TEST: I10Y
ERRCNT, III
; 1 REPEAT

339 TLOP
331 ; 2
PATTERN: =9
332
I10Y
PAn, .90
333 ; 2
INITIALIZE T!IIER
334
MO\I
A, ITlIDT
335
f1O\I
T, A
336
5TRT
T
:m
EN
TCNT!
:na .: 2 CLEAR FLAGBYTE
339
f'IOI,'
1/0, .HFLGBY

349
341 ,,2
242
343

I'IOV

~e,

III

FLAG1=MARK
CLF.'
F1
CPL
Fl
REPEAT

344 .: 2
345 TILOf':
346 ;3
IF TRAHSI1IT REQUEST FLAG--9 THEN
110\1
R8, WLGBY
347
f1O\I
ft @118
348
349
J85
TREC
350 ;4
NXTBYTE : =PATTERN

351
352
353
354.:4
355
356
357
358
359
360

HOY
I'lO\l
MO\l

Rl, II'tNXTBY
A,PAn

0128 8920

@R1.A
TRANSI1 IT REQUEST FLAG=l
DIS
TCNT!; LOCK OUT TIPlER INTERRUPT
; SO THAT MUTUAL EXCLUSION IS I'IAINTftINC.D WHILE
.: 'IHE FLAG B\'TE IS BEING MODIFIED
I'IOY
R,@R!j
ORL
A, tTRRQFL
@R!j,A
MOil
361
EN
TCNT!
TES1A
362
JTF
JriP
TREC
363
364 TESTA: CALL
IJART
.: CALL IJART BECAUSE TIMER OVERFLOWED Dl.JRIN(j LOCKOUl
365 ;3
ENDIF
366 ;3
IF DATA READ.,. FLAG=l THEN
367 TREC:
HOY
A,@R0
368
369
CPL
A
370
JBJ
TRECE
371 .:4
PATTERN: =OKDATA
J1O\I
R1, lMOKDAT
372

912A Fl

373
374

MOY
I'IOY

A,@Rl

912B AE

9118 35

0119 Fe
911A 4329
el1C A9
811D 25

011El622
(1120 2424
0122 149A

9124 F9
9125 37
9126 7238

812C 35

012D Fe

375 ;4
376
377
378

PATT, A
DATA READY FLAG: =II
DIS
TCNT!.: LOCK OUT TIMER INTERRUPT
; so THAT ItJTlR. EXCLUSION 15 MAINTIANED WHILE
; THE FLAG B't'TE IS BEING I'IOOIFIED

379

MOY
Figura 4 (continued)

All mnemonics copyrighted  Intel Corporation 1979,

1-59

AP"49
LOC OOJ

~

SEQ

912E 53F7

All.

0139 A9

I'IO't'
EN

9131 25
9132 1636
flB42438

9B6 149A

383

JTF

384

JMP
CRlL

385 TESTS:
J86 TRECE:
3117 ;]

388 ; 2

A, lOOT DRDYFl
@F1l.II
TeNT!
TESTB
TRECE '
UAIIT
; CALL UART IF T!MER OVERFLOWED DURING LOCKOllT

ENDIF

UNTIL ERROR FLAG OR OVERRUN FLRG

389
390
391
392 ; 2

/'10'.'
R,@R9
RNl
A.I(O't'RUN OR ERRFLG)
J2
llLOP
INCREMENT EIIROR COUNT
:m
INC
E~CNT
394 i 1 UNTIL FOREVER

913S F9
9139 5:>'99
913B C69F

0131) 1F
913E 2402

USER S'r'/'IBOlS
ATEI1/' 9997
If'LGBY 991E'
OVRUN 00S0
P.C\1050 9059
STPBTS 0099
TJ5R 9997
iiMTB11j fl06E

SlRTEl'ENT

395

Jt4P

396 iEOF
397

END

BI'Flfl
I1NXTBY
PATT
RC\1960
SVNFLG
TLOP
iiI'IT020

A55EMBlV COI1l'lETE,

0094
9023
0096
OO'5F
0002
0192

9978

JlOP

DRDI'FL
HOKDRT
RCI/900
RCV070
TCKCTR
TREC
XKT940

0098
9020
0017
0061
0004

9124

ERRCHT 0007
/'ISAI1CT 0011>
kl.'V010 9924
RCVFLG 0001
TEST 9100
TRECE91J8

ERRFLG
MTCKCT
RCY020
REG0
TESTA
TRNGfl

0010
091(;
0033

9899
9122

994IJ

FLGBI'T 901j6
HXI'ITB't' 9rra
RCY030 .9038
RETURN 999i'
lESTB 1j136
TRRIlFL 0020

MARK
OJ1ARK
RCY040
SAMCTk
llLOP
UART

0000

r1()RTA 9921

0015

OSPACE 9911

9942

kCII945
SPACE
1I11CNT
Xl'll)

0005
0191'
99IjA

0954
FF7F
mE

0064

0086

NO ERRORS
Figure 4 (continued)

All mnemonics copyrighted © Intel Corporation 1979.

MULTIPLY ALGORITHMS
Most microcomputer programmers have at one time or
another I'mplemented a multiply routine as part of a
larger program. The usual procedure is to find an algorithm that works and modify it to work on the machine
being used. There is nothing wrong with this approach.
If engineers felt that they had to reinvent the wheel
every time a new design is undertaken, that's probably
what most of us would be doing-designing wheels. If
the efficiency of the multiply algorithm, either in terms

+

of code size or execution time is Important, however, it
is necessary to be reasonably familiar with the multiplication process so that appropriate optimizations for the
machine being used can be made.
To understand how multiplication operates in the binary
number system, consider the multiplication of two four
bit operands A and B. The "ones and zeros" in A and B
represent the coefficients of two polynomials. The
operation A x B can be represented as the following
multiplication of polynomials:

BOA3*~

B1A3*24 + B1A2*~.
+ B2A2*24 + B2A1*23 +
B3A 1*~ + B3AO*23'

+

+
+ B3A3*26

+

B2A3*25
B3A2*25 +

1·60

BOA2"22
B1A 1*22 +
B2AO*22

+

+

+

BOA1"2 1
B1AO*2'

+

BOAO"2°

AP·49
The sum of all these terms represents the product of A
and B. The simplest multiply algorithm factors the
above terms as follows:
A * B = BO*(A)*20 + B1 *(A)*21 + B2*(A)*22 + B3*(A)*2 3
Since the coefficients of B (Le., BO, B1, B2, and B3) can
only take on the binary values of 1 or 0, the sum of the
products can be formed by a series of simple adds and
multiplications by two. The simplest implementation of
this would be:
MULTIPLY:
PRODUCT = 0
IF BO= 1 THEN
IF B1 = 1 THEN
IF B2= 1 THEN
IF B3 = 1 THEN
END MULTIPLY

PRODUCT: = PRODUCT + A
PRODUCT: = PRODUCT + 2* A
PRODUCT:=PRODUCT+4*A
PRODUCT: = PRODUCT + 8* A

In order to conserve memory, the above straight line
code is normally converted to the following loop:
MULTIPLY:
PRODUCT:=O
COUNT:=4
REPEAT
IF B[O] = 1 THEN PRODUCT: = PRODUCT + A ENDIF
A:=2*A
B:= B/2
COUNT: = COUNT-1
UNTIL COUNT:= 0
END MULTIPLY
The repeated multiplication of A by two (which can be
performed by a simple left shift) forms the terms 2* A,
4 * A, and 8* A .. The variable B is divided by two (performed by a simple right shift) so that the least significant bit can always be used to determine whether the
addition should be executed during each pass through
the loop. It is from these shifting and addition opera-

ISIS- II

~IC5-48/UPI-41

lOC 08.J

tions that the "shift and add" algorithm takes Its com·
mon name.
The "shift and add" algorithm shown above has two
areas where efficiency will be lost if implemented in the
manner shown. The first problem is that the addition to
the partial product is double precision relative to the
two operands. The other problem, which is also related
to double precision operations, is that the A operand is
double precision and that it must be left shifted and
then the B operand must be right shifted. An examina·
tion of the "longhand" polynomial multir Ication will
reveal that, although the partial product is Indeed dou·
ble precision, each addition performed is only single
precision. It would be desirable to be able to shift the
partial product as it is formed so that only single preci·
sion additions are performed. This would be especially
true if the partial product could be shifted into the "B"
operand since one bit of the partial product is formed
during each pass through the loop and (happily) one bit
of the "B" operand is vacated. To do this, however, it is
necessary to modify the algorithm so that both of the
shifts that occur are of the same type.
To see how this can be done one can take the basic
multiplication equation already presented:

and factoring 24 from the right side:
A*B=24[BO*(A*2- 4)+ B1*(A*2- 3 )
. + B2*(A*2- 2)+B3*CA*2- 1)]
This operation has resulted in a term (within the
brackets) which can be formed by right shifts and adds
and then multiplied by 24 to get the final result. The
resulting algorithm, expanded to form an eight by eight
multiplication, is shown in figure 5. Note that although
the result is a full sixteen bits, the algorithm only performs eight bit additions and that only a single sixteen
bit shift operation is involved. This has the effect of
reducing both the code space and the execution time
for the routine.

t1fICRO ASSEMBLER, V2. Il

SEQ

SOURCE STAmalT

1 $MACROFIlE
2 $INClUDKF1.t1Pi'S. Hm
j .:

***************************************"**************************************,.

4.:*
5 .: '"

HPY8X8

'"

i ; *==========--================--============*'"
B i*
,.*
THIS UTllITI' PROVIDES AN 8 BI' a UNSIGNED MULTlPLI'
9 i*
AT ENTR... :
10 i*
*
A = lOWER EIGHT BITS OF DESTINIITION OPERAND
11 i*
.'"
XA= DON'T CARE
12 i*
R1= POINTER TO SOURCE OPERAND (t'IUI.. TIPLIER) IN IN1ERNIII. MEMEORI'
13 .:*
*
Figura 5
All mnemonics copyrighted © Intel Corporation 1979.

1-61

inter

AP·49
SOURCE STATEl£NT

LOC 08.1

= 14;*

=

AT EXIT,

15 i*
16 i*'
17
18 ;*
19 i*

,i.

29 ;

A = LOWER EIGHT BITS OF RESllT
XA= UPPER EIGHT EIlTS OF RESUL r
C = SET IF OVERFLOW ELSE CLEARED

24 ; 1 MP'r'8X3,

25 ,1 I'IULTiFLICAND[ 15-8 J =0
: 26 .·1 CLiUNT. =8

27 i 1 REPEAT
23 i 2
IF I'lULTIPLICANV[0J=0 THai BEGIN
29 .:>
MULTIPLlCAND,=MULTIPlICANro/Z
i;1

:11 d
32,:
]} ,; 2

ELSE

MlILTlPLICRND[ 15-8], =t1ll T1PLItAN{)[15-S J+PlUL TIPLIER
MULTIPLlOINr':=I'1ULTIPLICAND/2
ENDIF

f4 i 2
~OOtlT =COIJNT-1
]5 ; 1 UNTIL COUIIT=0
~s ,lEN£, MP'J3XS

:·7 :
?8 EQIJATES
J9 i
4B ;
41 XA
EQIJ

9002
000?
9004

EQU

42 COuNT

R2
R3
R4

43lOIT
EQIJ
44 ;
45 OII3PR EQlJ
3
46 ;
47 $EJECT
48 $INCLlIDE<: F1: MP'r'8)
49 ; 1 MP'r'8X8'

9003

50 MP~'8l<:B:
51 ,.1 t1llTIPLIC.ANI)[15-81:=9
52
I10V
53 ; 1 COONT:=S
54
I'IOV

0000 BA00
0092 B!l9B

XA, 100
COUNT, tIS

55 ;1 REPEAT
56 I'IPYSLP.

9004 120E

=
9096 2A

aile?

9"1
Il008 67
OO~

2A

000A 67
0098 E894
900D 83

*
*".

**************••******.**********"'***~*******"'**"'**t******.t***••",...**********

21 ;
22 ;
23 $INCLUDE( :F1:t'lPVS POL)

:10

*

57 i 2

IF MlILTJPLlCAND[llJ=9 THEN BEGIN

58
59 i 3

JB0
I'1f'YSA
MIJL TIPLl CAND : =MIJL TIPLICAND/2

69
61

XCH
CLR

A, XA
C

62
63

RRC
XCH

154

RIle

A
A. XA
fI

65

orNZ

COUNT. MP'r'8LP

66
6;' ,;2

RET
ELSE
Figure 5 (contlnuad)

All mnemonics copyrighted © Intel Corporation 1979.

1-62

AP·49
LOC· OBJ

SEQ

SOURCE STATEMENT

68 I'lP'r'BA:

69 ,3

= 70
71
72

ewE 2A
000F 61

0018 67
13011 2A
0012 67

ADD

73
74
7!;
76
i7 ; 1
78 ,2
79 ; 2

0013 EB94
0015 83

sa .: 1
~~1

82
USER S'l't'1BOLS
COUNT iJ!.lO?

MIJLTlPLICAND[15-SJ:=I1IJLTlPLICI-lU(){15-S]+I'IULTlPLIER
XCH
A~ XA

;1

E~[i

DlGPP 0003

A5SEI1BL't' COMPLETE.

A, @111

RfiC
A
XCH
A, XA
Rr;'C
A
DJNZ
COUNT, HP't'8LP
RET
MIJL TIPLICANI): =I'IIJL TIPLICANI)/2
ENDIF
COUNT· =COUNT-1
UNTIL COUNT=0
END 11P~'3:<3

leNT

9004

MP'~SA

00iJE

MF'~8LP

0004

MPV8X8 !lOO!l

XA

tlO EJIRORS

All mnemonics copyrighted © Intel Corporation 1979.

DIVIDE ALGORITHMS
In order to understand binary division a four bit operation will again be used as an example. The following
algorithm will perform a four by four division:

DIVIDE:
IF 16*DIVISOR>= DIVIDEND THEN
SET OVERFLOW ERROR FLAG
ELSE
IF 8*DIVISOR>= DIVIDEND THEN
QUOTlENT[3]:= 1
DIVIDEND: = DIVIDEND - 8* DIVISOR
ELSE
QUOTlENT[3]: = 0
ENDIF
IF 4*DIVISOR>= DIVIDEND THEN
QUOTlENT[2]: = 1
DIVIDEND: = DIVIDEND- 4*DIVISOR
ELSE
QUOTlENT[2]: = 0
ENDIF
IF 2* DIVISOR> = DIVIDEND THEN
QUOTIENT[1]: = 1
DIVIDEND: = DIVIDEND - 2*DIVISOR
ELSE
QUOTIENT[1]: = 0
ENDIF
IF 1 *DIVISOR> = DIVIDEND THEN
QUOTIENT[O]: = 1
DIVIDEND: = DIVIDEND - 1 *DIVISOR
ELSE
QUOTIENT[O]: = 0
ENDIF
ENDIF
END DIVIDE

The algorithm is easy to understand. The first test asks
if the division will fit into the dividend Sixteen times. If it
will, the quotient cannot be expressed in only four bits
so an overflow error flag is set and the divide algorithm
ends. The algorithm then proceeds to determine if eight
times the divisor fits, four times, etc. After each test It
either sets or clears the appropriate quotient bit and
modifies the dividend. To see this algorithm in action,
consider the division of 15 by 5:
00001111
- 01010000

(15)
(16*5)

00001111
- 00101000

(15)

Doesn't fit-no overflow
(8*~)

Doesn't lit-Q[3] = 0
00001111
- 00010100

·(15)
(4*5)

00001111
- 00001010

(15)
(2*5)

Doesn't lit-Q[2]=0

00000101
00000101
- 00000101
00000000

Fits-Q[1] = 1
(15-2*5)
(1 *5)
Fits-Q[O] = 1

The result is ci = 0011 which is the binary equivalent 01
3-the correct answer. Clearly this algorithm can (and
has been) converted to a loop and used to perlorm divisions. An examination 01 the procedure, however, will
show that it has the same problems as the original multiply algorithm.

1·63

Ap·49
The first problem is that double precision operations are
involved with both the comparison of the division with
the dividend and the conditional subtraction. The
second problem is that as the quotient bits are derived
they must be shifted into a register. In order to reduce
the register requirements, it would be desirable to shift
them into the divisor register as they are generated
since the divisor register gets shifted anyway. Unfortunately the quotient bits are derived most significant
bits first so doing this will form a mirror image of the
quotient-not very useful.

When this algorithm is implemented on a computer
which does not have a direct compare instruction the
comparison is done by subtraction and the inner loop of
t,he algorithm is modified as follows:

REPEAT
DIVIDEND:= DIVIDEND*2
QUOTIENT: = QUOTIENT*2
DIVIDEND: = DIVIDEND - DIVISOR
IF BORROW=O THEN
QUOTIENT: = QUOTIENT + 1
ELSE
DIVIDEND: = DIVIDEND + DIVISOR
ENDIF
COUNT: = COUNT - 1
UNTIL COUNT = 0

Both of these problems can be solved by observing that
the algorithm presented for divide will still work if both
sides of all the "equations" involving the dividend are
divided by sixteen. The looping algorithm then would
proceed as follows:
DIVIDE:
QUOTIENT: = 0
COUNT:=4
DIVIDEND: = DIVIDEND/16
IF DIVISOR>=DIVIDEND THEN
OVERFLOW FLAG: = 1
ELSE
REPEAT
DIVIDEND:= DIVIDEND*2
QUOTIENT: = QUOTIENT*2
IF DIVISOR> = DIVIDEND THEN
QUOTIENT: = QUOTIENT + 1/*SET QUOTIENTIO]*/
.
DIVIDEND:= DIVIDEND- DIVISOR
ENDIF
COUNT: = COUNT - 1
UNTIL COUNT = 0
ENDIF
END DIVIDE

An implementation of this algorithm using the 8049 instruction set is shown in figure 6. This routine does an
unsigned divide of a 16 bit quantity by an eight bit quantity. Since the multiply algorithm of figure 5 generates a
16 bit result from the multiplication of two eight bit
operands, these two routines complement each other
and can be used as part of more complex computations.

ISiS- II HC5-4B/UPHl t1ACFO ASSEMBlER, Y2. 9

Lor 08,]

S(NJRCf STATEMENT

SEQ

1 tl'lACROFILE
;: tINCUJ[lE{ :F1·[lIII16. HED)

:: ,.~*~",,,,**.*~*******************************************. .************************
i*
*
:*
DIV1b
*
.*
,.

4
'5
6
7
S
9
19
11
12
13'

.14
1'5
16
17

.: *==============================================?========*
>I<
;*
,..
THIS UTILITY PRO\IIDES' AN 16 BY S UNSIGNED DIVIDe
;*
>I<
;*
AT ENTRY:
p~
A = LOWER ElGtH BITS OF DESTINATION OPERAND
*>I<
XA= UPPEI1 EIGHT BIT5 Of DIVIDEND
.
;*
R1= POIllTER TO DIVISOR IN INTERNAL MEMORY
>I<
; '"
AT EXIT:
:*
*
;*
A = LOWER EIGHT BITS· OF RESUL1
...
;*
XA= JlEt1AINDER

*

'"

*

Figure 6
All mnemonics copyrighled (0 Inlel Corporalion 1979.

1-64

inter
LOC OBJ

Ap·49
SEQ

SOURCE STATEMENT

C = SET IF OVERFLOW ELSE CLEARED

,.
'"

29 .' **~***** N .**~~ _* H~ '~*.j.*~·*f··.*******,H*****",*******.I<*********"'***~**"'*~,*******
21 ,

22 ;
2,
24
25
26
27
28
29

tINCLUDE(F1:DIV16 PDLl
; 1 [\11116
; 1 rOUrn·=3
; 1 ['JVJ[lEN~[15-8J=[JJVJDEN[U~H3H)lVI50~'
; 1 IF BORROIol=0 THEN l* IT FITS.:,'
;2
SET OVERFlOIJ "LAO
; 1 ELSE

30 ; ~

~ESTO~E

31
12
13
34
35
?6

PEPEAT
DIVlDEND:=DIVIDENU*2
OIJOTJENT =QIJOTIENT*2

;2
,3
;?
;:;
.: 1.
;4

:7 ; 3
38 :4

19 .:,.

0002
000:5

!lael BB0e.

0903 37

0004 61 .
8905 37
0996 F60B
m~e8 117
<1!llJ9 0424

0008 61

[Il'JlDENll

[;!V!I)END[15-8J:=~IV!l)END[1~-SHIVISOP

BOR~OH=l THEN
RESTORE DIVIDEND
ELSE

IF

;}UOTJENf[0] =1

ENDIF

411 ; -,
t:ourn . =COUNT-1
41 ;"2
IJPHIL COIJNT=0
42 .: 2
CLEAR OVERFLOW FLAG
4:5 ; 1 END:F
44 :1·ENDDmDE
45 ;
45 . EQUATES
47 .'
43 "
49 >:11
EGIJ
R2
f(!
59 COUNT EGU
51 ;
52 $EJECT
53 sJNCLlIDE< :F1:I!IV16)
54 ,1 DIVi6.
55DIVlt:. XCH
A,XA
,,"OOTlNE WORKS MOSTLY WITH BIl5 15-8
=.56 ;1 COllIIT:=8
57
t10V
COONT, #~o
58 ·1 DIVIDEN[I[1S-8l:=DIVIDEN[H5-SJ-DIVISOR
59
CF'L
A
60
ADf'
A. @R1
61
CPL
A
" 62; 1 IF BORROH=ll THEN /* IT m 5"'/
6"1
Ie
[)I VIA
64 ; 2
SET OVERFLOW FLAG
65
CPL
C
JMP
DIVIS
66
67 ; 1. ELSE
61'1 [)I','lft:
69 ·2
IJ=l THEN
90
,"'Ie
Dlvre
-. 91 ,4
PE5TOI3
0019
00lA
0018

;<(,H
110V

'55

O(l!:l5 8100

eaec

1'10'1

eCD' =BCD*2tC~R\'
~Ol
H.R9
R1.A
HOII
XCH
A.R9
11011
ICNT.IDIGPR
TEMP!. Ii
MOil

MOY
f100C

A·@R1

[lfl

MOil

A
@j;'LA

INC

Rl

~.@Rl

leNT. BCDOC
>31
MOY
A. TEMP1
82 .2 . IF CARRY FPCit'! BC[lACC GOTO ERROR EXIT
83
Je
BCOCOD
84 .' 2 couln .=COIJNT-1
85 ; 1 UNTIL GOUNT=!!
06
r, JNZ COUNT. BCOCOB

091F F624

0021 EBOC

8823 97

DJN2

G7
CLR
C
88 ; 1 END CONVERT-TO_BCD
89 ewcOD RET
90 END

0024 83

USER SYMBOLS
BWCOA il005

BCDCOI3 OOOC

TEMPi 0(,'.0'5

l:A

M55EMBL',' cot-RETE.

BC[JCOD 0024

; CLEAR CARRY TO ltIDICATE NORMAl.. TERHINftTlOtl

BCDOC 0017CNBC[1 0000

0W2
/10 ERI"OR5

Figure 7 (conllnuld)
All mnemonics copyrighted  Intel Corporation 1979.

1-68

COUNT 0003

DI (jPR e003

1(;NT

9004

intJ

Ap·49

The conversion of a BCD value to binary is essentially
the same process as converting a binary value to BCD.
CONVERT_TO..BINARY
BIN:=O
COUNT:= DIGNO
REPEAT
BCDACCUM: = BCDACCUM • 10
BIN:= 10· BIN + CARRY DIGIT
COUNT: = COUNT - 1
UNTIL COUNT=O
END CONVERLTO_BINARY
The only complexity is the two multiplications by ten.
The BCDACCUM can be multiplied by ten by shifting it
left four places (one digit). The variable BIN could be
multiplied using the multiply algorithm already dis·
cussed, but it is usually more efficient to do this by mak·

ing the following substitution:
BIN=10· BIN=(2)· (5)· (BIN)=2· (2·2+1)· BIN
This implies that the value 10 • BIN can be generated by
saving the value of BIN and then shifting BIN two places
left. After this the original value of BIN can be added to
the new value of BIN (forming 5 • BIN) and then BIN can
be multiplied by two. It is often possible to implement
the multiplication of a value by a constant by using such
techniques. Figure 8 shows an 8049 routine which con·
verts BCD values to binary. This routine differs slightly
from the algorithm above in that the BCD digits are read,
and converted to binary, two digits at a time. Protection
has also been added to detect BCD operands which, if
converted, would yield binary values beyond the range
of the result.

151:-!! I1CS-4:3!IJPI -41 MACI"O ASSEMBLEP, \(2. 0

lOC OBJ

SEQ

501JRCE: STATEMENT
1 Si'1HCROFILE
2 >INCLUDE( F1:CONIlIN. Hm)

] .: *************_.****-1<****** ~.~*.~*********************",***************.*******",*~,*
4 ;t

5.*

'"

CONBIN

'"

'"

7 ; *==================================================================*
B .:t
,..
THIS UIILlW CON'/EIHS A 6 DIGIT BCD '~ALUE TO B1NARI'
9 :*

10,.
11 :.~
12 :j<
13 j t
14.:*
1~

:*

16 :*

AT ENT,..... ·
RO= POINTER TO II PACKED BCD STFING
AT EXIT:
H = LOWER EHiHf BITS OF THE BINARY RESULl
l\f:= tiPPER EIGHT BITS OF THE BINARY RESIJl T
C = SET IF OVERFLOJ,l ELSE CLEARED

'"
'"
'"
'"
'"
'"
'"
'"

V.:*
'"
18 : ************"'i·'f<*~**.~*,'·t-*'f<**~*****""*"'***"'**t.j<************"'*"'***********"'*******

19.:
29 :
21 $INClUDE( ·F1:CONBW. POl)
22 ;
23.
24 .: 1 1.:ot·WERLTO_BINAR'r'
25 .: 1 POINTER0:=POHlTER0+DIGITPAIR-i
26 : 1 COlIIIT: =DIGITPAIR
27 ; 1 BIN:=~
23 : 1 REPEAT
29 : 2
BIN: =BIN"'W
:m:2 BIN:=BIN+MEM(RM7-4J
31:2
BIN:=8IN*10
12 .: 2
BIN. =BIN+r1EWR0)D-01

All mnemonics copyrighted © Intel Corporation t 979.

1·69

intJ

AP·49
lOC 08J

soo;:CE STRTEIENT

SEQ

3J ; 2
34.2

POJtIT~

=POINTER8-1
COUNT:=COUNT-l
~5 •1 UNTIL WUtH =~
36 ; 1 EN!) CON"'Ej;'L TO_BlNAI?Y

33 . EOIJRTES
39 .
40.:
41 XA
42 COUNT
43 leNT
44 ;
45 DIGPR

9003

EQIJ
EQU
EQU

R2
R3
R4

EQU

3

46;
47 fEJECT
43 $INCLUDE ( 'F1. CONBIN)

49 .
59 TEMPi
51 TEMP~

SET
SET

R5
R6

52 ;

9000 Fa

8001 11302
9003

~8

8W4 BSIl3

0006 27
8W7 AA

0008 142B
009A F62A

ttOOC AD
BOOD
000E
OOBF
0011

; 1 COt/VERLTO_BINARY
COIlBIN:
; i POINTER0:=POINTER0+DIGITPAIR-l
1'10'./
A, RIl
ROO
A,I01GPR-i
t'f()V
RB.• A
; 1 COllNT:=DIGITPAIR

69

1'1

6D

74
;'5
76
77
78
79 ;2
80
81
82 :2

0015 2Fl
0016 F62A

0018 142B
001A F62A
AD
Fe

72

73

3?
84

5~0F

as

61)

B6
37

2A

All mnemonics copyrighted CO Intel Corporation 1979.

MOV

COI.JNT, If) IGPR

61 .,1 BIN =0
62
elF:
A
E::
MOil
i(il, A
64 . i REPEAT
65 CGNBlP:
66,2
BIN:=BIN*10
67
CALL
CONB10
68
.Ie
CONSER
69 ,2
BIN. =BIN+MEM(R0)[ 7-41
79
MO\!
TEMP1, A

F9
47
530F

. 0012 2A
0013 1399

901C
0010
001E
B020
9021

53
54
55
56
57
58
59

!1OV

R, @RO

SWAP
A
A,#iJFH
ANl
AI)[>
Fl, TEI1Pi
A, XA
XCH
A,too
AOOC
;':CH
A. XA
K
CONBER
~IN =BItM0

CALL

CONB10

JC
CONBER
BIN =B IN+t1EH (RBi[ HlJ
MOV
TEt1Pl, A
A..@RQ
MOV
ANL
A,10FH
AOO
A, TEMPi
A, XA
XCH

1·70

intJ

Ap·49

LOC 00)

SOURCE STATEI'IENT

SEQ

88
89

0022 BOO
0024 2A
1l1l2'3 ~62R

AOOC
XCH

90
91 ; 2
92

0027 CS

A, 100
ft,XA

JC
COIISEII
POI'lTER9. =POINTER0-1
DEC
R0

93 ,2
COUlIT :=COUNT-l
94 ; 1 UN1IL COIJllT=e
95

002S EBBS

D.JNZ

CO'JIlT, CONBLP

96 ; 1 END CONVERLTO_BIHAR'I
97 COIl8ER: !lET
9S SEJECT
99

002A 83

=100 ;
= 101
= 102
= HIS ;

= 104 CONBl9. MO~'
= 105
XCH

002B All

902C 21'1

= 106
= 197
= 10S
= 109
= 119
= 111
= 112
= 113
= 114
= 115
= 116
= 117
= 118

902D AE
002E 2A

00'5 97
003B F7

0031 2A
0032 F7
0033 2A
00:14 F646
9036
00:?7
0038
0039

UTILI T'1' TO I'IIJLTIPL.,.. BIN BI' 10
CARR~' WILL BE SET IF OVERFLOW OCCURS

F7
2A
F7
2fl

I1(IV

TEMPi. A , SAVE A
A, XA
!>AVE XA
TEl'lnA

XCH

A,XA

CLR
PLC

C

XCH
RlC

A
A.Xft

JC

CONBIE ; ERROR 011 OVERFLOW,

RLC

A
A.XA

XCH
RLC

803ft F646
003C 6D
903& 2ft
883E lE

= 121
= 122
= 123
= 124

ADDe

=125

XCH

= 126
= 127

JC

= 128

RLt
XCH

2A
0040F646
0042
9043
9044
9045

F7
2A
F7
2A

0046 83

USER SYMBOLS
CONB10 0028
TEl1Pl 0095

CONBIE 0046
TEt1P2 0006

ASSEMBLV COMPLETE,

NO

; BIN: =BIIO*4

ft

XCH

A,XA

.Ie

CONBIE ; ERROR ON OVERrLOW

AI.lO
XCH

= 129
= 130
= H1
= B2 ;
= 133 CONalE:
= 134
= 135
136 ~N!)

; BIN: =BIN*2

;{r)l

= 119
= 120

OO~F

A

RLC
XCH

A. IDtf'1 ; BIN:=BIN*S

A, l(A
A, TEMP2
A. XA
COIIBIE ; ERROR ON OVERFLOW
A

; BIN: =8110*10

A. XA
A
A.XA

RET

CONSER 902A
i:A
0902

COIIBIN 0000

CONBLP 0008

E~:ROR5

All mnemonics copyrighted © Intel Corporation 1979.

1-71

COUNT 9003

DIGPR 0003

ICNT

0004

inter

Ap·49

CONCLUSION
The design goals of the full duplex serial communIcations software were realized; if transmission and reception are occurring concurrently, only 42 percent of the
real time available to the 8049 will be consumed by the
serial link. This Implies that an 8049 running full duplex
serial I/O will still outperform earlier members of the
family running without the serial I/O requirement. It is
also possible to run this program in an 8048 or 8748 at
1200 baud with the same 42 percent CPU utilization.

the highest performance microcomputer available to
date, the performance advantage of the 8049 should
allow the cost benefits of a single chip microcomputer
',to be realized in many applications which up until now
have required too much "computer power" for a'single
chip approach.

EXEC!JTION TIME
(MICROSECONDS)

The execution times for the other routines that have
been discussed have been summarized in Table 1. All of
these routines were written to maintain maximu'm useability rather than minimum code size or execution time.
The resulting execution times and code size are therefore what the user can expect to see in a real application. The results that were obtained clearly show the efficiency and speed of the 8049. The equivalent times for
the 8048 are also shown. It is clear that the 8049 represents a substantial performance advantage over the
8048. Considering, in most applications, that the 8048 is

BYTES

8049

8048

MPY8

21

109

200

DIV 16

37

183,MIN
204 MAX

335 MIN
375 MAX

CON BCD

36

733

1348

CONBIN

70

388

713

Table 1. Program Performance

1·72

intJ

APPLICATION
NOTE

AP·55A

August 1979

INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EII80DIED IN AN INTEl PRODUCT. NO OTHER CIRCUIT PATE.n utENSES ARE IMPLIED.
©INTELCDRPORATlDN.1979

1-73

9801007-<)1

AP·55A
I. PURPOSE AND SCOPE

• Breaks may be triggered by either program or external data RAM accesses;

This Application Note presents a description of the
design and operation of a high·speed emulator for the
Intel'" MCS·48™ family of single chip microcomputers.
The HSE·49™ emulator provides a simple and inexpen·
sive means for executing and debugging 8049 programs
which require the full 11·MHz operating speed of the
part.

• Any number of breakpoints may be used in any
combination;
• "Auto-Step" operation causes the current program
counter and Accumulator contents to be printed on
the display for a short time on every instruction
cycle;

Section II of this Application Note describes some of
the features of this development tool and how it may be '
used. Section III briefly discusses the hardware used to
implement these features, while Section IV describes
the manner in which program execution status is made
available to the operator.

• "Auto-Break" provides the above display only when
a break flag is encountered, with real time operation otherwise;
• While running in non-break mode, a TTL-level pulse
is generated whenever a break flag is encoun'tered.
This signal may be used to trigger an oscilloscope
or Logic Analyzer to assist in hardware and software debug.

A detailed description of all of the operator commands,
is presented in Section V of this note, along with the
modifiers and options which may be specified for each
command. Known restrictions and limitations of the
HSE·49 system are listed and explained in Section VI.
Section VII shows how the basic circuit may be
modified to provide options on memory organization, I/O
configurations, etc.
Full schematics of the system hardware, as well as
monitor software listings, are presented in Appendices
: A and B, respectively. A short summary of the command
syntax is presented in Appendix C,. Appendix D ex·
plains the error message codes which may appear duro
ing use.
It is assumed that the reader is already familiar with the
operation of the 8048 or 8049 microcomputers. Some
knowledge of the 8048 architecture is needed to under·
stand sections of the command and modifier descrip·
tions. Most users will already have this background.
Other readers are referred to the MCS·48 Microcom·
puter User's Manua/, Intel publication number 9800270.

• While running in any mode, the keyboard and
display are "alive". Execution may be suspended or
terminated by commands from the keyboard.

Intent of this Note
While the HSE-49 emulator can assist a new microcomputer user in becoming familiar with the 8048 and 8049
microcomputers, its inherent debug capabilities will
also prove helpful to design engineers. The design'
could be used for new system development and verification or adapted for prototype production.
The main concern in designing the HSE-49 emulator was
to keep the basic design simple, while maximizing the
system's flexibility. The design allows the use of
jumpers, hardware and software switches, etc. to allow
the user to reconfigure the system according to the way
he dedicates chip-select pins, 110, etc. The emulator can
be changed to fit each user's unique needs, rather than
forcing the user to alter his needs to what is provided ..
The primary intent of note is to provide the reader with
the information needed to reconstruct and make full use
of the HSE-49 emulator. Less emphasis is placed on
describing how the hardware operates or how the commands are implemented. This information may be found
in the schematic diagrams and software listings inCluded in the Appendices.

II. THE HSE·49 DEVELOPMENT TOOL
In essence, the HSE-49 emulator provides the user a
means for executing an MCS-48 program located in ex·
ternal RAM rather than internal ROM or EPROM. This
allows programs being debugged to be modified easily
and quickly during the debug cycle. A user's program
. may be entered into system RAM either manually or via
a serial link from a host computer such as an In·
tellec'" Microcomputer Development System. Once
loaded, the program can be modified using an on-board
keyboard and display, and executed in real-time in a
. number of breakpoint modes. The internal state of the
processor, including RAM,:accumulator, timer/counter,
and status register contents, can also be read and
modified through the keyboard.
'
Breakpoinf and 'debug facilities are extremely fl,exible.
The following execution modes are provided.
• Programs may be run in full (11 MHz) real time;
• Programs may be single-stepped;
• In break mode, programs run in full real time until
break occurs;

III. GENERAL HARDWARE OVERVIEW
User Program Emulation
The actual emulation of the user's program is done
using an 8039 microcomputer (IC29 on the schematics
in Appendix A) executing a program stored in external
RAM. The basic minimum configuration includes the
8039 microcomputer, an 8282 address latch (IC19), and
2K bytes of 2114 RAM to use for program development
and real-time,execution (ICs B1, C1, B2, and C2). Additional RAM may be added to allow the user to expand
his program and data memory to 4K each. (If an 11-MHz
crystal is used with the microcomputer, tYPE! 2114-3
RAMs must be used.)

1-74

intJ

AP·S5A

System Supervision

familiar with the PROMPT-48™ debug tool for the 8048
will find that 25 of the HSE-49 emulator keys are identical in function and layout to the PROMPT-48 keyboard,
and use the PROMPT-48 command syntax. The eight additional keys are used to generalize and augment the
PROMPT·48 capabilities, as described in Section V.

A second microcomputer - another 8039 (IC25) with an
8282 address latch (ICI6) and off-chip program memory
in a 2716 EPROM (iCI5) - is used to scan the on-board
keyboard and display, interpret and implement commands, drive serial interfaces, etc. In general, the
master processor is used to interface the execution
processor's memory spaces with the outside world and
control the operation of the execution processor. In this
note the two processors will be abbreviated "MP" and
"EP", respectively. Figure 1 shows how the two processors interrelate with the rest of the system.
system.

The eight-character seven-segment display (DS1-DS8)
is used for displaying addresses, data, and pseudoalphanumeric messages_ The display responses printed
in Section V and throughout this note use a mix of upper
and lower case letters to indicate what seven-segment
patterns appear. An 8243 (IC9) and eight DIP packages
(resistor packs, current buffers, etc_) are used for
multiplexing the display and scanning the keyboard_

Keyboard/Display
Breakpoint Detection

The 33-key keyboard shown in Figure 2 includes a 16-key
hexidecimal keypad and 17 special function keys for
specifying commands and modifiers. Readers already

Breakpoints are specified and detected using a 2102A
lK x 8 RAM corresponding to each pair of 21145 (ICs AI

USER
SYSTEM
PROTOTYPE

HOST
COMPUTER
SYSTEM
(INTELLEC)

DODOOE/e/D

O.O.O.c.I.D.C .Ll.O
C

D

E

F

CRT

A B
4

5

6

7

o

1

2

3

Figure 1. HSE49™ Emulator Signal Flow Diagram

B I

GO/RESET

I
I II

UPLOAD

SYS RST

DNLOAD

IG

I
I

I

EXAM/CHA

I

CLR/PREV

B I

HARD REG

IB

B

DDD0
DDDD
I DDD0
DODD
I

Figure 2. HSE_49™ Emulator Command Keyboard Organization

1-75

AP·55A
and A2). In effect, each program or data address accesses a 9-bit word. Eight bits are used normally for
code or data storage. The ninth bit, accessed in parallel
with the other eight, is used to indicate if a breakpoint
has been set for that address. This output, when
asserted, is latched {IC27 and IC36) and used to halt the
execution processor via the single-step input. (In other
modes, the break logic can be reconfigured to set the
break requested flip-flop on any EP machine cycle or
any EP "MOVX" instruction.)

baud from the on-board keybad. Blocks of data may be
transmitted to a CRT or printer and displayed in a
tabular format.
IV. INTERPROCESSOR COMMUNICATION
Program Break Sequence
When the MP detects that the EP has been halted by the
breakpoint hardware, or when the operator presses a
key while the program Is executing, the program break
sequence is initiated. The low-order 23. bytes of user program memory is read into a buffer within' the internal
RAM of the MP. A short program for reading and
transmitting internal EP status is written over the loworder program memory. (This is one of several "minimonitors" overlayed over the user program area.) The
link register is mapped logically over the user program
memory, and loaded with the 8049 machine code for a
"CALL" instruction to the mini-monitor program area
The EP is then allowed to fetch Ii single instruction fro~
the link, i.e., the "CALL" to the mini-monitor is forced
onto the EP data bus.

Link Register
An 8212 8-bit latch (IC18) is used to communicate data
and commands between the master and control processors. Under control of the MP, this register, called the
"Link" register, may be logically mapped into either the
program or data RAM address spaces. When this is
done, the 2114s in the respective memory space are
disabled and the link responds to all accesses.regardless of address. The link will be discussed in
greater detail in Section IV.
Control Logic

From this point on, the EP elfecutes code contained in
the mini-monitor. The link is logically mapped over the
data RAM address. space (whether or not any 2114 data
RAMs are present). A block diagram of the system at
this point is shown in Figure 3. The break logic is reconfigured so that any "MOVX" (RD or WR) operation executed by ttie EP will cause it to halt.

In addition to the devices mentioned above the
minimum configuration requires about 10 addition~IICs
for bus arbitration, system control, and breakpoint and
single-step logic; Additional parts may be optionally
added for serial port interfacing, I/O reconstruction, etc.
MP Monitor

For example, after entering the first mini-monitor, the
EP executes a "MOVX @RO,A" Instruction. This writes
the contents of the accumulator prior to the execution
termination into the link, and causes the EP to halt. The
MP may then read and retain the link contents to determine the EP accumulator value. The EP timer/counter
and PSW are preserved in the same manner.

The monitor program executed by the MP includes commands for filling, reading, or writing the various memory
spaces, including the execution processor's program
RAM, external ("MOVX") data RAM, accumulator, PSW,
PC, timer/counter, working registers, and internal RAM;
to execute the user's program from arbitrary addresses
in various debugging modes; and to upload or download
object or data files from diskettes using an Intellec@ development system. No special software is
needed for the Intellec@ other than ISIS Version 3.4 or
later. The data format is compatible with the standard
Intel hex file format produced by ASM-4; the baud rate
may be altered from 110 baud (default state) up to 2400

Accessing EP Internal RAM
After reading and saving EP internal status, the MP
loads a different mini-monitor into the same RAM area.
This monitor allows the internal RAM of the EP to be
read and written by the MP by passing address and data

EXECUTION"
PROCESSOR

MASTER
PROCESSOR

Figure 3. Communication between EP • MP
All mnemonics copyrlghled© Inlel Corporation 1976.

1-76

inter

AP·55A

values between the two processors using the link
register.
This is needed for two reasons. First, the EP program
counter prior to the forced "CALL" instruction may be
derived from the EP stack contents, and may be
modified to cause the EP to resume execution at any
desired address. Secondly, the internal RAM of the EP
may then be accessed and modified in the process of
executing a number of the monitor commands.
Resuming User Program Execution
In order to resume user program execution, a statusrestoration mini-monitor is overlayed. This restores the
EP internal status using a scheme analogous to the one
in which the status was originally saved. The final step
of the last mini-monitor is an "RETR" instruction, after
which the EP is again halted. The low-order program
memory saved earlier is rewritten into the appropriate
area, the break logic is reconfigured for the desired execution mode, and the EP is released to run at full speed
until the next break situation is encountered.
Note that all commands are implemented using
"logical" rather than "physical" addressing. Thus the
operator need not be concerned with the intricacies of
the system design. For example, when any monitor command refers to low-order user program memory, the appropriate byte of storage within the MP internal RAM is
accessed instead. If the location is altered, the internal
RAM is modified appropriately. When program memory
is reloaded prior to resuming user program execution,
the modified version of the user program will be the one
loaded.

low order part of a parameter; i.e., a command incorporating a data byte (such as [FILL]) will use only the
low-order 8 bits of the corresponding parameter; Internal RAM and hardware register addr,essing uses only
seven. In each case, higher order bits are ignored.
A command string is terminated and the command invoked by pressing the [END/.] key. The command will
also be invoked by pressing the [NEXT/,] key when no additional parameters are allowed. A command string may
be aborted at any point before the command is invoked
by pressing the [CLEAR/PREV] key, and the sign-on
message will appear.
Errors
An illegal command string, command terminator, or
hardware failure will cause an error message and error
code number to appear on the display (e.g., "Error-.3").
When this occurs, the monitor can be returned to command mode by preSSing the [CLEAR] or [END/.] keys. An
explanation of the various error codes is given in Appendix D.
Command Classes
Commands for the HSE-49 emulator are divided into
general classes, where all commands in each class have
the same choice of options or modifiers. A brief description of each command, followed by a description of the
allowed options, is presented below by class.
Data Manipulation/Control Command Group
Commands:
[EXAM/CHA]

Baud

HR06

HR07

110
150
300
600
1200
2400

93H
96H
45H
9DH
44H
1AH

04H
03H
02H
01H
01H
01H

Display Response Function -

Causes the memory address specified to be read
and presented on the display. New data may be
entered (if desired) from the hexidecimal keypad.
New data is verified before appearing on the
display. Subsequent or previous locations may be
read by pressing the [NEXT/,] or [PREY] keys,
respectively. Command terminated with [END/.]
key.

Table 1. Serial Interface Data Rate Parameters

v.

"ECh."

Examine/change memory location.

HSE-49 COMMAND DESCRIPTION

Whenever the characters "HSE-49" are present on the
system display, a command string may tie entered by
the operator. In general, all command strings consist of
a basic command initiator, an optional command
modifier or type-designator, and a number of parameters
or delimiters entered as hexidecimal digits. A command
is executed, or a command in progress terminated, by
pressing the [END/.] key. Logical default values are
assumed for the modifier and parameters if either (or
both) are omitted. A defualt parameter assumed for the
command modifier will be presented on the display
when the first parameter is entered.

[FILL]
Display Response -

"FIL."

Function - Fill range of memory addresses with a
single data value.
Fill the appropriate memory space between the addresses specified by the first two parameters with
the low-order byte of the third parameter. If second
parameter less than first, only the location
specified by the first is affected. IT third parameter
omitted, zero is assumed. If second and third
parameters omitted, individual address specified is
cleared. Command is useful for setting a large
range of breakpoints; e.g., all of page 3 may be
enabled for break with the command:.

Each parameter is a string of up to three hexidecimal
digits. If more than three digits are entered, only the
most recent three are considered. This allows an erroneous digit to be corrected without respecifying the
entire command. A parameter is completed by pressing
the [NEXT/,] key. Some commands may only need. the

[FILL][PROG BRK]<300>[,]<3FF>[,]<1>[.]

All mnemonics copyrighted©lntel Corporation 1976.

1-77

AP·55A
Function -

[LIST]

Display Response -

Register memory and RAM.

Internal RAM of execution processor. Locations
0-7 are working register bank 0; 18-1F are working
register bank 1. Only the low·order 7 bits of an ad·
dress are considered.

"LSI."

Function - List memory to output device through
HSE·49 serial port.
Display the contents of a range of addresses given
by two parameters to a, teletype or CRT screen.
Data,is formatted, 16 separated bytes per line, with
the starting address of each ,line printed. If used
with an Intellec'" system, the operator first uses
ISIS·II to transfer the TIY input to the CRT output
("COpy :TI: TO :CO:") then invokes this command
from the keypad. Alternatively, any ISIS device or
disk file name(:TO:, :LP:, :F1:HRDREG.SAV, etc.)
may be used as the destination.

[DATA MEM]
Display Response Function -

"dA."

External data memory (if installed).

Memory accessed by execution processor "MOVX
A;@Rr" or "MOVX @Rr,A" instructions. High·order
4 bits rr,ay or may not be relevant, depending on
jumpering option selected (explained in Section VII
of this note).

[DNLOAD]
Display Response -

[HARD REG]

"dnL."

Display Response -

Function - Download' memory through HSE·49 serial
port

Function -

"Hr."

Hardware registers.

Load data in hex file format through the serial input
port. If used with Intellec'" system, the operator
first invokes this command from the keypad, then
uses ISIS·II to transfer a disk file to the teletype
port ("COPY: Fn:file.HEX TO :TO:").

The execution processor (EP) hardware registers
(accumulator, timer/counter, etc.), as well as
several parameters for controlling HSE·49 system
status, are accessible through this catch·all
memory space. Addresses are as follows:

The use of the checksum field for the download
command is expanded slightly ,over the Intel hex
file format standard. If the first character of the
checksum field ,is a question mark ("?"), the
checksum for that record will not be verified. This
allows large object files produced by the assembler
to be patched using the ISIS text editor without the
necessity of manually recomputing the checksum
value.

00 -

EP accumulator.

01 -

EP PSW.
Bits correspond to 8049 PSW except that bit
3 (unused in the 8049) is u,sed to monitor and
alter the state of F1. Bits 2-0 correspond to
the stack pointer value after the EP executes
a CALL to the mini·monitor; i.e., one greater
than when EP was running the user's pro·
gram.

02 -

EP timer/counter.

03 -

EP internal RAM location 00.
(This value is also accessible through
[REGISTER] space.)

04 -

EP program counter (low byte).

05 -

EP program

[UPLOAD]
Display Response Function port.

"UPL."

Upload memory through HSE·49 serial

Output the contents of a range of addresses
specified by the two. parameters through the
HSE·49 serial port in standard Intel hex file format.
If used with Intellec'" system, the operator first
uses ISIS·II to transfer the TTY input to a disk file
("COPY :TI: TO :Fn:file.HEX"), then invokes this
command from the keypad.

HSE·49 automatic sequencing rate
parameter. Used in [GO][AUTO STP] and
[GO][AUTO BRK] execution commands. 00 fastest; FF - slowest. Defaults to 20H; ap·
proximately two steps per second.

09 -

Monitor version/release number (packed
BCD).

[PROG MEM]

Function -

"Pr."

User program memory.

Memory used to develop and execute user program.
Addresses 000 through 7FF are the execution proc·
essor's memory bank 0; 800 through FFF are
memory bank 1.

(lA-OF - Currently unused by the monitor program.
10-7F - Variables used by master processor (MP)
monitor. Should not be altered by operator.

[REGISTER]
Display Response -

(high nibble).

08 -

Data types allowed:
Display Response -

\~ounter

06-07 - HSE·49 serial interface baud rate paramo
eters. Defaults to 110 baud; other rates may
be selected by loading the values listed in
Table 1.

[PROG BRK]
"rG."

Display Response -

All mnemonics copyrighted© Intel Corporation 1976.

1-78

"Pb."

Ap·55A
Function -

Function - Go from reset state.

User program breakpoint memory.

Memory space used to indicate points where program execution should halt when running in a mode
with breakpoints enabled ([GO][W/ SRK) and
[GO][AUTOSRK)). Break will occur if enabled byte is
read as the first or last byte of a 2·byte instruction,
or read in executing a MOVP, MOVP3, or JMPP instruction. Memory is only 1 bit per location; 00 in·
dicates continue, 01 causes a hal!. Addresses 000
through 7FF are the execution processor's memory
bank 0; 800 through FFF are memory bank 1.

EP is hardware· reset and released to execute the
user's program from location OOOH. No parameters
are allowed. FO, F1, PSW, stack printer, memory
bank flip-flop, etc., are cleared.
Note that this command does not require the use of
mini·monitors to initiate program execution. As the
last phase of the program development cycle, the
2114 program RAMs and address decoder may be
removed and replaced by a ROM or EPROM part
(not shown in schematics). This command may be
used to start execution when the program RAM has
been removed. No interrogation of EP status or internal RAM may be done, nor are break or single·
step modes allowed in this case, though the 2102A
breakpoint RAM outputs may still be used to trigger
a logic analyzer.

[DATA SRK)
Display Response Function -

"db."

External data RAM breakpoint memory.

Memory space used to indicate points where data
accesses should halt when running in a mode with
breakpoints enabled ([GO)[W/ BRK) and
[GO][AUTOBRK)). Memory is only 1 bit per location;
00 indicates continue, 01 causes a hal!. High·order
4 bits of breakpoint address mayor may not be rele·
vant, dependent on jumpering option selected for
the corresponding data RAM (explained in Section
VII of this note).

Execution modes allowed:
[NO BRK]
Display Response Function -

Full-speed execution without breakpoints enabled.
Does not affect the state of the breakpoint
memories.

User Program Execution Control Group

[SING STP)

Commands:

Display Response -

[GO)
Display Response Function -

"nb."

Without breakpoints.

"Go."

Function -

"SSt."

Single Step.

Step through program one instruction at a time.
After each instruction is executed, execution halts
with the current value of the Execution Processor
Program Counter and Accumulator appearing on
the display in the form "PC.234-56". System status
is saved in the appropriate Hardware Registers. At
the pOint, [NEXT/,) will cause the program to ex·
ecute one more instruction, or any other command
may be invoked by pressing the appropriate com·
mand string. Does not affect the state of the Breakpoint Memories.

Begin execution.

If a parameter is given as part of the command
string, execution will begin at that address. Other·
wise, the EP program counter (hardware registers
04 and 05) will be used. These will contain the pro·
gram counter from an earlier program execution
break unless they have since been explicitly
modified by the operator.
If command is terminated by [END/.), the EP's F1,
PSW and stack pointer will be cleared. If command
string is terminated by [NEXT/,), PSW will be taken
from the EP PSW contents (hardware register 01).

[W/BRK]
Display Response - "br."

While running the' user's program, the characters
"-run-." are written on the display. Execution may
be halted and another command initiated by press·
ing the appropriate command key. Execution may
be suspended at any time in any mode by pressing
the [END/.) key. This will cause the current value of
'the execution processor program counter and accumulator to appear on the display in the form
"PC.234·56". System status is saved in the
appropriate hardware registers. At this point, or
when an enabled breakpoint is encountered, press·
ing the [NEXT/,) key will cause the program to con·
tinue in the same mode as before. Any other command may be invoked by pressing the appropriate
command string.

Function - With breakpoints.
Full·speed execution with breakpoints enabled.
When a breakpoint is encountered, execution halts
with the current value of the execution processor
program counter and accumulator appearing on the
display in the form "PC.234-56". System status is
saved in the appropriate hardware registers. At this
point, [NEXT.,) will cause the program to continue
until the next breakpoint is reached, or any other
command may be invoked by pressing the ap·
propriate command string.
[AUTO STP)
Display Response - "AS!'''

[GO/RESET)
Display Response -

Function - Automatically sequence through a series
of instructions.

"Gr."

All mnemonics copyrighted© Intel Corporation 1976.

1-79

AP·55A
Step through program one inst~uction at a time.
After each instruction is executed, execution halts
with the current value of the execution processor
program counter and accumulator appearing on the
display in the form "PC.234-56". System status is
saved in the appropriate hardware registers. Execution resumes after a time determined by contents
of hardware register 08. Does not affect the state of
the breakpoint memories.

System Control Command Group
Command:
[SYS RSn
Display Response Function -

Reset both the MP and EP and clear all preakpoints
(requires approximately one second). CAUTION If reset while EP is executing the user's program,
the low order,section of program memory (about 23
bytes) will be altered.

[AUTOBRK)
Display Response - "Abr."
Function points.

Automatically sequence between breakVI. SYSTEM LIMITATIONS

Execute a series ,of instructions in real time
between breakpoints. When breakpoint is en·
countered, halt EP temporarily while program
counter and accumulator contents are displayed,
then continue. Display is sustained after execution
resumes. Does not affect the state of the break·
point memories.
Breakpoint Control Command Group
Commands:
[B)

Display Response Function -

"Stb."

Breakpoint set.

Set breakpoint for the address given. Multiple
breakpoints may be set by entering additional addresses, separated by the [NEXT/,) key. Command
terminated by pressing [END/.). Action taken is to
fill the appropriate breakpoint memory locations
with logical ones.
[C)
Display Response -

"CLb."

Function - Clear breakpoint.
Clear breakpoint for the address given. Multiple
breakpoints may be cleared by entering additional
addresses, separated by the '[NEXT/;) key. Command terminated by pressing [END/.). Action taken
is to fill the appropriate breakpoint memory locations with logical zeroes.
Data types allowed:
[PROG MEM)
Display Res'ponse Function -

"Pr."

Break on program memory fetch.

Applies command to the program breakpoint
memory space.
[DATA MEM)
Display Response Function -

"HSE-49."

System reset.

"dA."

Break on data memory access.

Applies command to the external data breakpoint
memory space.

In designing the HSE-49 emulator, certain compromises
were made in an attempt to maximize the usefulness of
the'emulator while keeping the circuitry simple and inexpensive. As a result, the following limitations exist
and must be taken into account when using the system.
1. As explained in Section IV, user program execution
is terminated (by Single-stepping, breakpoints, press·
ing the [END/.) key, etc.) by forcing the execution
processor to execute a "CALL" instruction to the
mini-monitor. This uses one level of the EP
subroutine stack. The EP PSW reflects the value of
the stack pointer after processing this CALL. As a
result, the value indicated for stack depth ,by examining the EP PSW (hardware register 01) is one greater
than the depth when the break was initiated. The user
program must not be using all eight levels of stack
when a break is initiated or the bottom level will be
destroyed.
2. User program is initiated (by the [GO) command or
when resuming execution after a breakpoint, singlestepping, etc.) by forcing the EP to execute an
"RETR" instruction. This will clear the EP interruptin-progress flip-flop. If the user program allows both
external and timer interrupts to be enabled at the
same time, care must be taken to avoid causing a
break while the EP is within an interrupt servicing
routine. No limitation is placed on breakpoints or
Single-stepping in the background program because
of this.
'
3. When the user program execution is terminated (by a
break, single-stepping, etc.) and later resumed, the
EP timer/counter is restored to its value when the
break occurred (unless modified by the user)_ The
prescaler, however, will have changed. Thus, up to 31
machine cycles may be "lost" or "gained" if a break
occurs while the timer is running.
4. Timer interrupts occurring at the same time as an EP
break may be ignored if the timer overflow occurs
afler breaking user program execution be(orEl the
timer value is saved.
5. The 8049 "RET" and "RETR" instructions are each
1·byte, 2-cycle instructions. During the second cycle
the byte following the return instruction is fetched
and ignored. If a program breakpoint is set for a loca·
tion fe>lIowing a "RET" or "RETR" instruction, a break'
will be initiated when the return is executed ..

All mnemonics copyriQhted© Intel Corporation 1976.

1-80

Ap·55A
6. Breakpoints should not be placed in the last 3 bytes
of an EP memory bank (locations 7FDH-7FFH and
OFFDH-OFFFH). User program should not be single·
stepped or auto·stepped through these locations.

current·loop or RS·232C current buffers, but not both at
one time.
Standard Operating Configuration
(Minimum system configurations - up to 4K program
RAM; no data RAM; no serial interfaces; no execution
processor 110 reconstruction.)

7. Since 110 configuration is determined by external
hardware rather than software, 110 modes may not be
altered while a program is executing. (See Section VII
for further details.)

A. Basic 2K monitor from Appendix B:

8. The "ANL BUS,#nn" and "ORL BUS,#nn" instruc·
tions may not be used in the user program, as exter·
nal hardware cannot properly restore these func·
tions.

Install
Install
Install
Install
Install
Install
Install
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Install
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9. The memory bank select flag is not affected by the
user program break sequence. Upon resuming execu·
tion with the [GO) command this flag will remain in
the same state as before the preceding break. The
flag may be cleared only by executing the
[GOIRESET) or [SYS RST] commands.

VII. HARDWARE CONFIGURATIONS
A number of control and status lines are available to the
user. All are low·power Schottky TTL·compatible
signals.
TP1 -

Unused MP input.

TP2 - Unused MP output.
TP3 - User program suspended. Low when EP run·
ning user code. High when halted or running mini·
monitors.

B. Expansion 2K monitor:
Install IC14
Remove jumper 17

TP4 - Breakpoint encountered. Normally low. High·
level pulse generated when breakpoint passed. Useful
for triggering logic analyzers, oscilloscopes, etc.

Serial Interface Buffer Selection

TP5 & TP6 - Memory matrix mode control. Select
program vs. data RAM, link mapping configuration,
etc. (See Appendix B for details.)

A. Current loop serial interfaces (4N46s) installed for
use with full Intellec'" Model 800 development
system TTY port.

TP7 - Bus control. Low when MP controls common
memory buses. High when EP controls memory
buses.

Install IC21-IC22
Install resistor R1-R3
Install jumpers 4-9
(Remove RS·232 jumpers)

The HSE·49 emulator hardware is designed to allow the
user to reconfigure the system for a wide variety of dif·
ferent applications by installing or removing jumper
wires or additional components. The schematics in Ap·
pendix A show the components needed for a variety of
different configurations. In general, not all of the
devices are required (or allowed) for anyone configura·
tion. The devices which are required are included in the
following description.

B. RS·232C serial interfaces (MC1488 and MC1489) in·
stalled for use with CRT as output device for data
dumps:
Install IC23-IC24
Install jumpers 1-3
Install jumpers 10-11
(Remove current·loop jumpers)

The types of options allowed are divided below into
several general classes and subdivided into mutually·
independent features. Within some of these features
there are numbered, mutually exclusive configurations;
i.e., the serial interface (if desired) may use either

All mnemonics copyrighted © Intel Corporation 1976.

resistors R4-R6
transistor Q1
crystals Y1-Y2
capacitors C5-C38
switches S1-S33
displays DS1-DS8
IC1-IC2
RP3-RP5
IC6-IC7
RP8
IC9
IC15-IC20
IC25-IC30
IC34
IC36-IC38
A1-A2
B1-B2
C1·C3
jumpers 13-15
jumpers 17-18
jumper 20

External Data RAM Address Decoding Scheme for Ex·
ecution Processor
A. Up to 16 pages of on·board external data RAM in·
stalled for execution processor (addresses 0 through

1·81

AP·55A

=

OFFFH 4K bytes); port 2 used for addressing pages
. 0 through 15:
Install
Install
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Install
Install

Reconstructing 110 for Execution Processor
A. Application of port 2, pins P23-P20:

jumpers 21-25
jumper 27
A5-A8
B5-B8
C5-C8

(1) Using P23-P20 for latched output data (used with
"OUTL P2,A", "ANL P2,#data", and "ORL
P2,#data" instructions):
Install IC31

B. One page of on·board external data RAM installed
for execution processor (addresses 0 through OFFH);
port 2 not used for data addressing:

(2) Using P23-P20 for interfacing to an 8243 in user's
prototype:

Install jumper 26
Install jumper 28
Install A5
Install B5
Install C5
Connect the outputs of IC20 .. pins 7, 9, 10, & 11 to
the inputs of a 74LS21 AND gate (not shown). Connect the output to CE and CS inputs of A5-C5.
(Note: these signals are all present at jumpers
21-24 on the schematics.)

All mnemonics copyrighted @ Intel Corporation 1976.

Connect 03-00 pins on IC31 socket to corresponding 03-00 pins.
B. Application of execution processor BUS:
(1) Use of BUS as latched output port ("OUTL
BUS,A"):
InstalllC32

1-82

AP·55A

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(8;

; LIIlE5 GHIErnTCD 13'" MfICRO E)(PIlNSJON fiRE fLRGGCO CI' II PLUS SIGN ("+")
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131 ; A NUMBCR or LINES FROM HiE Vf~IOU~ i'IfICRO DEFINITIONS IoII1lCH 00 NOT
32; PPO[lIJCE fltf,' 08'][CT CODE ARE PRO(:E!;SEO BV HIE ASSEi'lBLER
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88 ;
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92; IS vEFINED OR REFEr;'ENCED. )HIS WILL BE:. or CRUlT fl5S15'IRNCE IN
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All mnemonics copyrighted @ Intel Corporation 1976.

1-87

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" 1114
= 195
= 106
" 197
= 1118
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8002
0893
9094

0093
11004
0085
0006

0087
0008
0982

SET

?fJ8R3
= 112 "BIlR4
= 113 ?OOPS
= 114 ?B0P6

SET

=i1!

2

Srt

3
4
5

SET
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58

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2

= 115 ?B1lR7
= 116 •

9093

= 11f.) ;
= 119 ?BIR2

!1004
0085

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= 121 ?B1F4

91.!86
9087
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9982

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8898

1

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= 118 ?OOR2

=117

a

= 12J ,1l1RG

=124 ?(J11t?
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=127 ;
=128 ORGPGIJ

7

SET

l
4

SET

5

SET

6
7

$1:1

SET
SET

S

SET

2

SET

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= 138 OR61'G2 SET

000H
100II
2Wl1

8300

= H1 ORGI'G3 SlT

.s08I1

8400
0500

Sl:T

400H
50911

0100

0688
8700

All

mnemonic~

= 129 ORGPG1 SET

=132 ORGrG4

= n~ ORGPG5 SIOl

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SET

= 135 ORGPG7 SET
= 1](.;
= 137 $EJECl

b8IlH
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copyrighled © Inlel Corporalion 1976.

1·88

intJ
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:: 1:l3
= 139
= 140
= 141

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= 142
= 143
= 144
= 145
= 146
= 147
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;

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START OF fllLOr...flTlON MACROS

;

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= 150
= 151 f

002!l

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RESTORE

?(l.~l:flNK&P'JT

= 15:?
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= 154 ;
= 155 i
= ISC ',I'IINDX SET

Sll

?B&eANK&R&f'NTVAL

21lfl

:: 157 ;

:: 1SS ?MSflVE Mr.CRO SYMEOL, LENGTIl, RDDR
SAVE liEN
= 159 $
:: WI
SYMBOL EQIJ flODR
:: 161 $
RE!:TORE
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:: 162 ?I'IINDX SET
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EGO 3
= IG6 ?&~""MIlOL
:: 167
?MSflVE S\'l'llJOL, LENGTH, ??i'lINDX
= 168 ENDI'I
:: 169 ;
= 170 [)[CLfl~E MOCRO S'r'MBOL, TYPE.
= 171 ?&S'r'MDOL
SET
?&WPE
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?&TVI'E EQ 2
:: 1n
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:: 1(4
EXITt1
:: 175 [NDIF
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:: 17C IF
?RSfW( S'r'I'IBOL, 9, ??WPNl
= 177
= 171]
EXITH
= 179 ENDIF
?&n'p[ EQ 1
:: 100 IF
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= IS1
:: 1iJ2

= 183 ENOlr
= 134
= 1('.5,
= 186 $

Em"
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All mnemonics copyrighted © Intel Corporation 1976.

1-89

Ap·55A
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(is,}

SOORCE STATEI1ENT

= 187 -'
= lDe -' P.l:QRG MACRO TO RESET THE INS1 RltTION LOCRTION COIJlT[R
= 11Y.) i
TO THE nr.:ST rllE[ LOCATION ON TIE FIRST PAGE IIODUI.E WILL
FIT WilHItI.
=190 -'
= 191 R[ORG PlACRO LOCHTION
= 192 $5AYE GEN
= 193
ORe
LOCATION

= ,194 tl\'ESTORE
= 19'5

ENDII
= 196 ,
= 197 ; rOOCDU(
"AeRO TO rIt(l fI PFIOC OF ROI'I
= 198 ;
IflICII TIllS BLOCK or CODE WILL fI1 WITHIN

= 199 COOCDLK I'IfICRO

LENGTIl
= 20e '-'lENGTH 5['1
L[NGTfI
= 201 IF
IIIGHll
= 243 ,l1f'TABLK
= 244
= 245
= 246
= 247
= 248
= 249

INSERTS ONTO PAGE 3

DflTflBlK IVlCm

Loon I

?LENGTH SET

lENGl H

IF

fIIG1HORGI"G3ilEOOTH-1l EQ 3
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= ~2
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= 254 ;
AM) (fOOTE!; APPROPRIATE ORGI'GI
= 255 ?SIZE MACRO BLK. rGE

:s -

= 256 t5flYE (lEN
= 25;'

SIZE SET

BlK

= 253 ;
= 25:) i *~,.~~**.j<*'*************************~,******.***********-**­
= 260 IF "lENGTII l T SIZE

= 261

:: 262
= 2(.3
= 264
= 265
= 266
= 26('

=26e
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ERROR

9

;

*** SIZE EXC£1:tY.i Sf'flCE Cf[!;K(I) FOI< BY COO[E!LK 11OCk'O

ENDIF
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9

;

SET

$

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SIZEClIK MflCRO
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= 270
= 271
[M)l'I
= 272
= 273 ;
= 274 .;
= 275 i RSOURCE

CHECKS SIZE OF I'RECEDII¥.i BLOCK, PRINTS SIZE 10 . lS'1 FIll

r.($··?START>., f.fIIGI·I(?!'IART>

CODE SP1lCE ALLOCATION
= 276 RSOURCE MACRO
=277 $SAliE LIST GEN
:: 27()
PGSIZE SET ~.iI'Ci0-800\1
= 279
PCi5IZE SET OR(,'PG1-100H
PGSIZE !..ET 0I\'GPG2'-209f1
= 2ee
ORGPG3- 300H
PGSIZE SEl
= 2e1
f'GSIZE 5E.T ORGPG4"·480H
=282
1'65121:. SET ORGPG5- 500H
= 283
PGSIZE SET ORGPG6--600H
=284
PGSIZE 5[1 ORGPGi" 709H
=2S5
= 2S6 $EJECT

=207 $RESTORE
= 283
ENDM
= 2fJ9 $l:.JECT

All mnemonics copyrighted @ Intel Corporation 1976.

1-91

stm1R\' STBTEl'UIT

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ON
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USED
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PAGE
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PAGE
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9
1
2
3
4

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298
291
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= 293
=294
= 2'J5
= 2%
= 297
= 298

i

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FOR GEI£RAl..IZII«l (I'COOE INSTRUCfIC*

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?F0RM1 1'IAf'..RO 0f'C00[, Slit
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= JOO

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R1, I<"..RC
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=304 $
.. 305

= J06

$

=307

?&Sk'C Ell 0 OR ?&SRC EO 1
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=310 $
=311
= 312

$

=313

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SflIIE GEN
OPCODE
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EXIlI'I

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A, ISRC

= 314 ENDIf
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ERROR

1

= 316 EhWI
= 317 ;

=318 i ?HJRI'I2 If1CRO

= 319?F0RI12

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= 321 $

= J22
= 323
= 324

$

=l25
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$

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FOR GENERAlIZII«l IIOYES H~OI'I THE ACe 10 A YARIAllL.C
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FOR GENERAlIZING I10YES FI..'OI'I TIE oct TO A YflRIAIlLE
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= 372
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[!ESTORE
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EXITi'I

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= 376

ERROR

?&$If ORM!

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MACRO
I'IftCRO

FOR GENERALIZING AOOC INSTRucnON
OCST, Sk'C

?lJINOP flOOC, IJI:ST, SRC
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MACl?O FOR GENERP.lIZING ANI. INSTRUClION
MftCRO !lEST, ~RC
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ENDM
;
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MORl

Mf\(;I?O FOR OCNERALIZING OR\. INSTk'UCTION
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,
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;
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I'IACIIO

lOR GENERALIZING xt:H INSTRUCTION

All mnemoniCS copyrighted @ Intel Corporation 1976.

1-94

inter
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SOURCE

= 455 MXCH I'fRCRO
'1S1f()P
= 456
=457
END"
=451) ;
=459 ':'UNflR't' MACRO

~"'RTEIt:.1ll

[lEST.5RC
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OPCOOE,DE$T

'?FORMi MOV,DEST
= 460
= 461 $SAllE (lEN

=462

OPCODE

A

= 46] fR[STORE
?FORMl DEST
=464
= 46.'5
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= 466';
=46'1 MINC IlACRO DEST
= 468
?I..IIflRY INC,IET
[ND/'!
= 469
=479 ;
= 471 II[l[C I'IACRO OCSl
?UNIlRY DEC,DEST
= 472
= 473
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= 474 ;
= 475 MDJNZ I'IfICRO DEST, AllOR
= 476
?UNAR't' DEC,DEST
= 477 $SAllE GEN
=478
.JNZ
ADDR
= 479 :m:STORE
END/,!
=489
= 481 ;
PlfiCRO I>E5T
= #'.02 I'IRl
?UIflRY Rl,DEST
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ENDM
= 484

= 485
= 4~ MRF
=43'1
,i

= 4!l8

=489 ;
= 49IJ MFRC
=491
=492

!'IRCRO

DEST
?lHlR't' RR, !)EST

END"
MACf.'O DEST
')UNARY RRC,DES'I
ENDM

= 493 ;

= 494 MRlC

IIflCRO DlST
= 495
?UNARY RlC, Dl:ST
= 496
ENOM
= 497 ;
= 498 $EJECT

All mnemonics copyrighted @ Intel Corporation t976,

1-95

intJ
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AP·55A
LINE

SOURCE STATEI£NI

499 .:
508 ; ================-------:;--::-:::-====
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583 ;====--=====,,======='
584 ; ===========--=====:--=--====--==

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588 :
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5111 ;

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511 ,********-**~:*. .
512 ;
51$ .:
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M4,
1'1
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P2
516,
P7
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51S rSEGHI mu
1'6
519 PSEGLO WU
P5
528 rINPUl EQlI
1'4
!l21 ;
5<12 i
!l23,
524 ;
JND IVIDUAL PINS

,USED FOR IlIDIF.ECTHM Al'a:m AN) DIITA lRfl6ERS
; USED AS INDIVIDUflL CONTROL OUTr1JTS fN) BREAK LOGIC
; IHIJIHJRDER ADDRE~S AND ADDReSS SPP.CE SELE(;lION
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; PORT rOR LOIoIJI FOUR SEGMENTS

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~;

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528 I:.MJRflI'I EQIJ

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5:se
531
532EPSSTP [00

090001001l

m
0018
8828

5j4 CLRElfF [00
535
t>36 EPRSET EQU
537 I'IODOUT EQU

88OO1.9OOC

08011188eB

li!II1e811ooe

538

539 lTYOUT EQU
549
541 ;

01900000B

; r10 - III ENABLES BREfl{ ON BkERK RAIl OUTPI.Il SIIHl.
,P11 .' HI ENflBLES BIED

542 $EJE.CT

All mnemonics copyrighted @ Intel Corporation 1976.

1-96

inter
LOC OS]

AP·55A
LINE

sourCE S1nTEMENT

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INDIVIDUAL PINS (IF PORT ~ USED f)~ FOlLOWS
,
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:
; AOR11-r.Dk'S f- OR r.etESS I NG f'k'UGRflII OR I>A1n RAM ARkflY

~59

'

545
'546
547
54G

0010
0029
0040

551 Me

LOU

552 I'll

f:.QU

0OO100001:s
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01000000B

553 Mf'USEL [()I.I
554
555 [xrOON [QIJ
556
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    ARD I'ION 11 (If<, KfJIlTHIG HN E~'Pfllj~1011 MONilOR PRESENT ~.' 55!1 .' WilEN Mf' IN CONTROL or i'lEl'1OI<'\' MATRIX 1'11-1'10 USED ns rOLLOWS ~!3; ~061 ; I'll M0 I'IODe f'ROGRflM ROM ARRAY ENAELED FOR R[AO & WR ITE DAlii RnM f-IRRAY eNABLED rOR ~lP,D & WF.: HE 5£;2 ' 0 563' 13 1 1. X LlNl( R[GISRR r:NI1BLlD FOR READ, f.:MII ,*RIW!) DISfIEllD. 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CONST [;[[lNCE [QIJ @) DIMENSION or KE\'BOAm MATRIX 4 ; NlJleEli 8 or 5IJCE551','[ SCflNS BHORI: Kl\' CLOSUR[ ACCEPTED C:<1 . (.32 rHLARt aa17 0010 O\,~,IZ[. CONS) (;4(' [VIS I ZE E(l1) (;47 . 1.48 OCCLARE r.urLEN. CO~IST 662 BlIFL[N EtlU (;C~ ; ~.IZt. UI' LnRGES', MINI-MONl1fW MRLA\' rOF 1:.1' 2~ . LENGTII OF HEX FORMAT ;1- 665 . fC6 . UTIlITY CONSTnNT DECLARATIONS 6(:7. 668 . ***i,~*'f'~t****"",u"t"*.t~***"'*l,*****~******~'*******~***~,*t**** 6(,9 . 0000 0001 0003 6'10 D(ClA~ <:ERO.I;ON5T 6l)4 m'o ml' 0 (.9':0 OCCLARE PltISL CONsr f.9:l !'lUS1 EIlIJ 1 ,'013 I)[CLi~r[ PLU53. CONSl ;'14 PL~~ lQU :> ;'15 HFI" f,ECUlF'E II[G1.. CONST .'29 NEG1 m [QU .. 1 fE.lECT A~I mnemoniCS, copYrighted © Intel Corporation 1976. 1·98 intJ Lo( 00.1 Ap·55A LIN[ 9JURC[ :;TflTEI1ENT ;'32 . ,'I~ ,; ***~**:~i:~'*l:*':**;:*~*~*****'*"'********************.********** 7]4 ; (3') ; BANI( 0 REGI~T[rl ALLOCm ION, I3G ; 73? ,l'*~, 't.*~,*~'~*****-I'*',*;,*",****:j.********~*********;:****""******** 738; ;'39 lULARE LDATn.IC:*>t*";'****"';'*********************;:*.'****** 341; 844 845 846 847 0002 0003 0004 0006 ,: [:fINI( 1 REGI~TER flLLOCI1TION " : *~,** ~****t.*~.**~.****** ~.,***********:~******************",***~ : ; USE.D TO HOLD INPUT I'flTTERN BUNG I\'OTATW THkruGH t~' B48 DEClfl!:'E ROTPilT. RBi 065+ ROl PAT SET f.:2 ; COUNTS 1lR'Irn:l< Of !l ITS ROl AltD THROUGH C\' 86~ DECLA~:E POTeNT,·1I1l1 066+ ROTCNT SET R] S90 DECLBRE UlSW.".IIB1 ; HOLDS KEY POSITION or LAST KEV DEPRESSION DUEtTED 907·1 lf15TK." SET R4 911 OCCLIlRE CURDIG. RIl1 ; HOLD!> "OSITION or NCXl CHAARCTER "iO BE DI~'LAYED 928+ WRDIG SET R5 n2 DECLtlRE m'rLG,f~B1 ;FU1G TO DrlECT WIlEN AlL Kl."S f1RE. f~[UFlSE[l 949+ m'FLG SET R6 :153 ; (k'EGI:;1~ ? NOT USED I'Ok Pkli'lflR't' MONITOR) 9S4 ; 95S ,; ******,~***:~****************;,**t******~,********************* 956 tEJ[CT All mnemonics copyrighted @ Intel Corporation 1976. 1·99 Ap·55A LOC OOJ LINE SOI.Jl<'C€ S1 ATEIOT 957 ; 958 ,*1-***.*i:*******.****.*~:*~'*******~.* 0920 80'.:1 0922 11023 0024 9025 0E!2G 0027 9II'.IS 0929 902A 002Il 002C 002D 802[ 0021· 0030 9831 0032 0033 0034 0935 1l03G 00:>7 963 ; YA DECLfft: [PAce, Rrd'l ; !:ltJ'flfJl IN 111' FOIl EF' f1l;CUl'lULf1TOr. EQU 32 969+ ~I'ACC 973 DECUiRE EPf'SW, ~'AM ; STORAGE IN Mr rOR EI' PROGRflM STATUS WORD 97(:+ [PPSW mu '13 932 DECLARE EPm!!?, ~RI1 ; SlomOE IN MF' rOf.: [f' T1I'1EI"ICOUNU:I< RlGIS1ER 907+ [F'Tl~ E(lt) :>4 991 DEcu:rE EPRS,~:FlI'I ' SlORfiGE IN Mr rOR EP FlEG 15Ttl1 0 OF BRNK {j E.(JU 35 996. El'\':0 1000 DECLARE EPI'CLO, (.'fl!'1 ; S1OI1FlGE IN 111' rOR LOW VI'l ( or EP rROGRAtI WOOER ErpCLO EOO 36 1005+ 109~ I)[CLA~ EF'PCfII. FAM 'STOIIfli.lE IN 1If' FOR HIGH NIBBLE OF EP I-'~OORfII'1 COUNT!:./.: [/'PCllI mll :)(' 1914. . rRROMETER 1 FOR <,;EPIAL LlN~ Df11A RflTl G[NERnTOR 1018 DECLfIFlE' HBITLO, Ff1'" 1023+ HBITLO E'.l1J 38 ,PMllM[TEI1 2 rOF 5E.RIAL Ll~ DMA RATE GENERA10R 1021' DECLflRE flS ITIi I ,PAl'! 1032·. f:CITHI EQU '.' ; rfWflf'l T[P f Of.' AUTo-STI;P flN(l AUl 0- BREflK SlQUENCIt«i wnn: 1936 ~CLfw.C DSPTlti, rAM DSPTII'I [QU 4ij 184H 1845 DECLARE IlERSNQ, RAM ' MON ITOr;' '.'EP~·I ON NUI1BEJ< YE~SNO [QU 41 t05~+ (UNUSED) 1054 OECLME I-IREGA, RnM . f:REGil EW 42 1{!5~+ (uPUSED) 1063 OCCLn~'[ IIREGD, RAM 196(a . IlREGC EQlJ 43 (lJNI.)<'.1:D) ; 107<: llECLAr;'E flREGC,lIfl1'1 i07?·} HREGC EQIJ 44 (1HY'.1:D) . 1981 OCCLfif HREGD, RrlM 1986-1 BREGD EGU 45 (UNUSED) 1090 DlCLflJ;'l 11RE1lE, FAM i 1095. flREGE [00 46 (UNIJ<~D) 11!99 DECLARE 1fREGF. RAM 110H HREGF EQU 47 ,f'Rll'IAR~'. ComlND Slr~TINGI'IE.t1OR'" HOOR135 (L~ INTE) 1100 DECLf1RE SHRLO, Rrd'l -•. . 111J+ SI'IflLU EQU 1117 DECLARE SIflHI, RAM 1122'~ SMAIl! EOO 1126 DECLflRE EI'IflLO, RAil 1131+ lIRO HllJ 1135 DECLAI1E· EI'IAI-Il.. RAI'I 1148+ EI'IflHI [QIJ 1144 DlCLARE I1El'II..O, RAM I1EIILO EW 114'+ 115:1 DECLARE MEltl!, RM 115tH MEIIIII EPU 1162 DlCLARE ElCODE. Rf1I'I l1G'?+ BCODE £:QIJ 1171 DECLARE TYPE, RflI'I EQU TI'PE 1176+ 48 ; PRllf'oRY ComlNl> ~TARIWO MEIU\' flOOK'l!>S (HIGI: BYlE) 49 ; PI"IMflk".' C.IJMIIANI) ENt'IN(; I'IE~\' ADDRES::; (LOW al'TE) 50 ; PRIMAt;",' COMMANI) ENDING MEI'IOR\' ADDRE.S!:> (HIGH BYlD 51 ; UIIRD PWSlI? PRRAMETER & HEX RECORD ADDRESS (LOW) S2 ; TIII~D PfP.SER PflRAMEW:': 8 HLX RECOOD AOORESS (HIGH) 53 ; PI1II'1flR't' COMMAND NUMBER FROM rff;:5[R HlBLES (lHJ) ~ ; f'RIMfIRY COi'II'IAND I'IODlrIER/OF'lION (0-5) 55 All mnemonics copyrighted © Intel Corporation 1976. 1-100 inter LOC OBJ 9939 9931l 993B 993C 993l) 993E OO4Il 0041 1l!l42 9843 994[ Ap·55A LINE 5tUICE 5TATB1[NT 111l1l DECLARE /lJI'tON, ~'flI'I 1185+ NlKOO [QU 11e9 DI:(.tflRE OPT! ON. RflI! 1194l OPTION EP.U 1198 OCCLR~E r£XTPL, RAM 1293+ IEXTPL EQIJ 12117 DECLflRE KBOEUF, RAM 1212+ KOOIllf EOO 1216 DECLRRE KEYLOC, RAM 1221+ KE\'LOC EQU 12'~S I!lCLARE ~PTS, RAM 1230+ NREPTS lQU 1234 DECL~ fI<"•..IWL Rf1I'I 1239;· flSflY[ EQU 1243 D[CLAPE RDELRI', R!iM 124fB RDELfll' [QlJ 1252 DEGlfiRE STFTMP, mM 1~7+ STRTI'IP EQI) 1261 DECLflRE BlfrNl, RAM 12(,(:+ BlfCNT EDIJ 1270 DECLRR[ RECTI,!" RAM 1275+ R£CTYP EQI) 1279 OCCLARE B, RAM ; IR<. IM'IOCR or PflRMTERS PUOWI:D FOR SELI;(;TED CO/I'IAN) 56 ; II«X f'OIN'IER lJS[D IN S£mCllIN6 rARSER TABlES 57 ; ClfARACTER f"~ITION rOR DISPLRI' UTiLlHES TO WRITE Pl.Xl 58 .; rtlSIl ION or 1((\' OCBOlllCED BY SCAlflING stfJRWTIPl. ~9 ; IM:R[tlEN1ED ns ; KEEPS TRACK or SUCCESSIVE REnDS or SAI'IE I([I'STROKE 69 SlJCCE!>SIYE KEY LOCATIONS SCANlED (;1 ; HOlDS OCtltU.ATOR WIUJE DlJFINIi SERVICE RotJl INE. 62 ; (.'(UfiER DECRDlENTED WIIlN flUTO'SlEP OlLfl'l' IN F'I\'tG.'ESS (;3 ; IPllEX POINTER FIJ<: DI~LfiY GflflRftCm: STRIN!i ACCESSING 64 ,COUNl or llt1TA BmS IN llEX FORI'IflT RECORO BUFFU: 65 ; lYrE OF flEX FORI'Ifll RECORD (9 OR 1) E.6 ;!llT COUNlER FOR flSCIl !>ERIP.L 110 UTILIW SlllROUlIPES B EQIJ 6r ; CHARriCTER BEING SHIH[J) DURING SERIAL 110 rROCESS 1288 DECLARE REGe, Rfil'l 1293+ REGC [til) C8 ; COUNTER IN SorTWfft: DELn'I DAm RATE GENERATOR 1297 DECLARE H, RAM [00 G9 1392~ H 1306 ; 1284·~ B97 MBlOCK 1311i 1314 ; 1315 MOCK 1319+ 1322; 1323 MBLOCK 1327+ 1330 ; 1331 SEJECT :.EGI1flP, ClIflRNO ; REGISTER flRRfI'I FOR DISPLf''t' PfllTERNS 5[GMflP [00 79 O\IIJUF,OVSIZE ; LOIHIFDlR IJSER PROGRAII DURING PHNHIONITOR OVERl/lYS OYBlf /:.QIJ fS HEXBIJF, BlfLEN ; ALLOCATE BLOCK or RAM I·OR lJ<.A: AS HEX liEXBIJF EQIJ 191 All mnemonic. copyrighted © Intel Corporation 1976. 1-101 REC~D btfFER intJ lOC Oil) 0300 0300 00 0301 00 0:;02 00 AP·55A LINE S(lIJ!CE STRTEI'[IIT 1332 13:>71 1341 ; INVf1LS 1142, 134:$, 1344.' 1345 , 1346 INVfll5: DATflJlK 4'1 1347 ORG INITIAL VliLlIt ====== .:::.== DB 00H 9393 a3 9394 00 1350 0:ros 00 B51 00 DB 00 00 DI:! !J31l(; 00 0307 01 0308 00 0309 00 0300 00 031:10 00 030C 93 9500 04 B39E 20 039F 25 0310 00 0311 00 0312 00 0313 00 8314 00 0315 00 13316 00 0317 00 0318 rF 9319 OF 031A 00 031B 00 1352 DB 1353 1354 00 ~!31C ~l31D 031E 031F 0329 13321 13]22 3023 8023 00 04 01 00 a3 IT 00 1348 1349 DB 1355 Of; 1356 DB 1357 135f.) DB DB 1S59 1369 1361 1362 1363 1364 1360 DC DEl DB DB DB Oil DB DB DB DB DB 00 DB DB DB 00 DB DB DB 00 DIl 08 1366 1367 1368 1369 1370 1371 1372 1373 13i'4 1315 1376 1377 1378 768 Tfll)lE OF CON::;Tf1NT~ 10 BE LOAOCD INTO ~ INTERIR. f RAI1 LOCATIONS "10 DEFIlED Yfl.OCS. INIT: SlL ROO Xl'COO[' 19 i'IOY Xl'TEST CALL A CLR lIO\II) PSE(llO, fl PSEGlII, R IUID RI!, 11AH ; START AT 1/01 (REG2) = RflII LOC lA1I i'IOY R1, ILOW NOVRLS lIlY R2, ILOW INYfl.5 i'IOY A,R2 INITLP: i'IOY =1497 =1498 =1499 =1410 =1411 =1412 =14B =1414 =1415 =1416 =1417 =141B =1419 I'IOYPJ A,~ @R9,1I =1429 I10Y =1421 INC R9 =1422 INC k2 1d.,INIlLP =1423 DJNZ =1424 STRT "I =1425 CALL EPI.:RK R9, ILOW(OV1BAS+QYSIZE) =1426 i'IOY =1427 Cf1Ll. OYlOAD =1428 CALl COI'IFIl R1,ITI'PE =1429 MOV @R1 =1439 INC =1431 CftLl INCSI'IA =1432 au COIf'll PL 1lflERJ ; WIlTR I'EPIORI' I100IFIERl ; [ (;LCflR/PREVIOOS 1 ; [IJ'LOAD C!1II1AND J ;[AU10S11P I1OOIFIER] ; [PROGRAI1 I'(~I' MQ() IHER J ;[REGISTER ME.~' rfJDUIERJ ; [FORI'IfITTED DATIl OUTPUT COI1IflHI) J ; [GO FRm REstT STATe t'atlAN» , [GO COItlRNri J ; [~XflI'lINE/I'IOOIF',' COI'IIfN) J ; [SET BIlEff(POINT COI'II'IflM) J ; [CLEAR IlREAKPOINT COI1IflN() J EQlJ (QU 1911 151-1 1111 100 WI tr.H ;[f'ROORRI'I BREflKf'OINT 11E~' I'IODIFIERJ .; [DATA BR£AKPOINT MEI1OR'r' I100IFlER 1 ; [IIARDWARE REGiS1ER I'IEI1ORI' MODlFIER] ;[lmllOUT CREAKf'OlNTS I'IOOlrIER] ; [WITH ERl:AKPOINTS ENRIlLEI> 11OO1f1ER] ;(SmGLE STEP I'IOOIf lERl (00 Eoo EQU EOO EQU EQlJ EtlU EQU Eoo EOO EOO (00 EQU EQU [00 EQU mu [00 EQlJ EQU All mnemonics copyrighted @ Intel Corporation 1976. 1-105 Ap·55A LOC OOJ 9929 111"01 ll02B "(401 Il020 2381 8Il2r 3400 001114EC !Jell f'B 11834 DJ13 11836 eG2S 11838 EC23 118311 B936 1183C B1111l 1IIl3E B937 9840B1lt11 9842 FC 11843, EJ 11844 B28C 11846 00 1184i' C652 11849 Fe 1184ft 0303 !I04C RC B936 II84F 11 l1li58 11442 11841) 0952 11854 0055 11857 B936 F1 011D 3482 LItE !am STRTDENT =1526 COOEBLK 168 =1531+ ORG 41 :1535 ;lIAIN OUTPUTJtE5Sf&:(C(MN)~T) CfLL IIf'ULIJVTE(KEY) =1536 ; =1537 ;1Ifl1N2 IF THE KEV=lND GO TO IfllN. =1518 ; =1539 f1flIN: IIOV XPCOOE.11 =1540 CflL :0 ICTRE EXHlIUSTEDI =1552 ; IF CTAIl< ITIf')=KEY GOTO IfIIIIl ICOItIflND lNTRY f'Wt> IN CTAB! =1553 ; ELSE lllf':=lTIIP+COltIRIlUNlR'l'..sm =1554 ; BCOOE: =!lCOOE+1 =1555 ; ENDIfIILE =1556 ; GOTO !»'OF =1557 lIlY 1111', ICTIlIl =1558 ItIOY 1lCODE, ZlRO . =1569+ IIOY Ri, ISCOOE =1570~ =1574 =1585+ =1586+ =15911 FINDOf'. =1591 =1592 =1593 =1594 =1595 =1596 =1597 =159S =1599 , =1699 =1601 ; =16112 ; =1(;03 i =1604 ; lIlY lIllY IlO\l lIlY lIlY 1IOYI'3 JaS XRI. J't: lIlY fI)() IIOV lIlY (IR1, lZERO TYPE, Z[RO rd., ITYf'[ IW,'O FI, ITW A, @fI I£RROR A, KEY IfIllfI A, 1TIIP ft,lCOllSIZ ITIt', A R1, IBCOOE @Rj" It«: @R1 .mP FlNlOP OOTI"ULI[SSOOE(5TRCOI'I«(;(;oo(» I: =H1 OPTION:::IEII(I> =1605 ; I :=['~1 =1696 ; NO_(J'J'ARAI'IETERS: =IEIf( I) =1607 i 1:=3 =1608; fl,BCOOl =1689 I'IAINfl: Ri,IIlCOOE =16113'1 fI,@R1 =1619+ n,15TRCOI'I =1623 =1624 OOTCLR All mnemonics copyrighled @ Inlel Corporalion 1976. 1-106 I*fmf'T FOR T~ C~£NT UJI/IFII)*I infel' LOC 00,] 9959 lC 0Il5A F(; 0058 E3 905C 1i939 005E fl1 W5f 1C 0060 rc OOC1 D 9062 89313 9064 R1 0965 0067 0069 006B 006C 006E B9BC fl8:?0 0000 18 E96!1 14EC 9079 8939 0072 1"1 0073 nc 00;>41C 0015 0076 0077 0078 rc E3 97 F7 0079 77 89lA Dr, 0078 C693 0071) r687 0071 LOS37 0W1 H OOG2 17 0083 A1 9984 1C 0085.0475 0087 B937 .0B89 B100 AP·55A LINE ~CE =1625 =1626 =1627 =1628 =1641+ =1642+ =1646 =1647 =1648 =1649 =1662t =1663+ =1667 ; =1668 ; =1669 ; =1670 =1671 =1672 I1fllNB: =1673 =1674 =1675 =1676 ; =1677 . =1673 .. =1679 ; =1680 ; =1681 " =16B2 =1(91)+ =1699'1 =1i'12+ =1715 =1f1C MAl NC1' =1732~ =173(; =17S7 =1f38 =1739 =1749 =1741 =1742 =1743 =1748+ =1749+ =1?S3+ =1?S8l =1761 =1762 =1763 .. =1764 i =1765 " =1766 MAI1ID1 =177(-1 =1778+ =1782 INC I'lO\l I'IOIJF'J !II1OV !'IOV rov STflTEMENT ITttP R, 1lI1f' R,@fl INC mil' I'lO\l A,11111' fI,@A MOVr3 MI'IOV /'fOIl MOV ; GEl OPTI ON PO INrrR OPTION, A R1, IOPTION @R1.A OCT NO OF f'fiRfll'lETtRS NltICQN, A R1, lNUl'lCON ~R1, n rnr.rn;TER_EtHER(9=)5). =9 MOil r1,1t; /'IOV /'IOV RII,ISMALO ~'0, .99H INC OJNZ CALL R9 1<1.I1flINE i E.ACH I'fiRAI'I IS 2 INl ES ; START (f PARflI'I E'.tJfFERS INPKEY WlIILE KEYOMEM(OPTHRliTI'P[)[ 6-9] DO IF t1El'f(OPTlON+T'IF,[)[ 7]=1 GOTO MAlND1 TYPE .=TI'I'E +1 ENDIoIIHLE I1I'IOY MOIl MQI} MOY INC MI'IOV MOIl I1OW3 (;LR f.'L(; RR XRL J2 JC MINe MOY I'lO\l INC /'lOY INC JI'/f' ITMP, OPTION Ri, 1I000TI ON A,@R1 ITMI"A Imp A, ITI'IP A,ITMP A,@A C A R fl, KEI' ''lUND . STRIP BIT SEVEN INTO CAF.'k1' 1'Ifl1M>1 TI'PE 1,:1, '1i'P~ A,@Rl A @Rl,A ITI'IP /'tIlINC1 MODIfIER NOT FOUNO so RESET TlfE INOEX TO DEf'AUlT CASE. (ZERO), MMOV MOIl MOV MI'IOV 1\'P[,ZERO R1.ITi'PE flOR1,IZERO A,OPTION All mnemonics copyrighted © Intel Corporation 1976 1-107 inter LOC (J)J I!8SB ~39 Fl 908£ B 800F 3494 0091 049E 998() !lII93 8939 999S Fl 999(; B 8897 8937 9899 61 889R3484 989C '14EC Il99E 0C0II 0000 2330 00A2 6C llIIfl36C 88fI4 AS IlIIA5 14C9 9IIfl7 FGBlI Il0fl9 1C 09RA 8938 9IIRC F1 9IlAI) 87 80RE R1 818· C68ft 8IlB1 FB 0002 D313 9084 CGBf1 88B6 14EC 8IlB8 84fl8 09BC Bfl01 8IlBE 249A 8897 AP·55A LINE SOI.RCE STRTEllENl =1791+ I'm Rl,IOf'T1~ A,@Rj, =1792+ ItOY =17% ItJ\IP3 fl,flIfl =1797 CALL OUTIISG =1798 Jt1P I'tRIN80 =1799 : =18911 i CfU OOTPUT..I£SSOOHImIFIl'R) A, OPTI(Jj =1881 /ifill{) ItKJY R1, 'Of'TI(Jj =181IH IIOV 1101,1 A, I!Rl =1811+ =1815 IIOYf'J A,@fl R, TYPE =1816 ~ =1822·t Ri, .TYPE IIOV =1823+ fl, 8:1 flOO CAlL =1827 OOTIISG =1828 CIlLL 1If'KE\' =1!l29i ITl'IP,10 =1830 I'IAIN£lII: MO\I A, ISIIILO =1831 ml1NB1: ItOV A,ITI1P =1832 ADD A,ITI1P =1833 roo R8,R =1834 \'lII/ IIffl)F: CAlL =1835 JC Cl'lDINT =1836 =1837 Illf' INC =1638 1m RL INlJII:ON A,~1 =1839 ItOV =1840 R DEC 1R1, A =1841 IIOV =1842 JZ CllDINT /{I\I A,KE\' =1843 A,IKE\'END =1844 XRL Cll[)INT =1845 12 =1846 CALL INPKE\' =1847 JIll' KAINBl =1848 i =1649 i CllDINT ENTER TI£ ctM1N) PROCESSOR WITIl: =1S511 .: BfISLCOOf.=TfE KAIN rotIfIN) noPE =1851 i WF'E"'SUBCOIII'IAND TYPE =1852 ; PARRl'lETER(1)=rIRST I'IDDIIESS =11.'53 ; PRRfI'IETEI!(2)=SECOND flOORESS =1854 i PAm'ETERO>=DATA =1855 CIID INT: JIt' lIf'LE" =1856 i =18~7 i 1'l"RROR [~ ENCOUNTERED IN /lAIN PfJ.SINl kOlITINE. .=1858 IlERROR: 1m LOOTA, 11 . =1859 JII' PERROR =1860 SIZECHK =1863+ SIZE SET 151 .=11l64t: =1L'65ti*-"'-*----*******"''*****---** =1S74 '$EJECT All mnemonics copyrighted @) Intel Corporation 1976. 1-108 inter LOC OOJ 8323 AP·55A LINE 5ru!C(STnTEtENT =1875 =1889+ =1884 ; DATfllLK 59 ORG SIB =1885 ; =1886; =1887 ; =1!J88 ; 9923 0093 8323 if 0324 ~F 8325 91 8J2G 1E 11327 49 832tl 91 8329 18 1132A :sf 832B 83 932C 1C 8J21) 3F 832E 92 832F 18 8:n83F 8:m 92 11332 14 8m 3F 8334 Il8 8335 lIE) 11336 46 8337 91 8lla OC 8m 46 9331\ 01 83Jl1 11> 113~ 49 SJID Iil8 833E IT *****_****************************>I-"*****l,***************** TflBlES F~ PAR'.1.R =1SC9 ; *****.~********-****-_*_***********************.* =1fJ90; =1091 ; TIE C1AB TABLE CONTAINS (C1JISIz) EN1RIE5 FOR EflCll COI1I'IflND. TIl: PlANING =1C92 ; or THE Eimms IS flS FOLLOWS: =1C93 ; =1894 ; ENTR'l' 8 COI9IftND KC'I' TO INITIATE =1895 ; ENTR'l' 1. POINTER TO HIE LIST or OPTlCtlS APPLICAELE 10 THIS COittANO =1896; ENTRY 2. NUMB[R OF NUI1ERIC f'ftRlllETERS I~QtJIRED "'..,. 1Hl rowHl =1C97 ; $ AN) BFFH EQU =1&'98 CTAB =1899 COMSll [QU 1 =1989 ; K(:\'i'IOI), LOW OPTAB1,1 ; EXAI! =1991 00 .=1992 DB KEYOO, LOW 01'1003, 1 ;GO =1983 DB KEYFIL, LOll (J'1A1l1.3 ; fILL =1984 OB KEYL5T, LOll (FTAB1,2 ;iXJI'IP =1985 l>B KC'I'REC, LOll OPTAEL 2 ; RECORD =1986 = DB KEI'REL, LOW OPTflB1. 8 ; kE.l.UAD =1987 OB i8 991B 9119 Il11A 9118 811C 991D 9110 911E 911f 9129 9121 9122 9123 9124 912S 31 37 3E 44 46 49 48 4E 51 54 57 SA so 9926 9126 SF 9127 61 912!l 63 =199lH =1$'94 PRNT2: =2004i =2Il98 =29119 =2919 =2911 =2916+ =2917+ =2921i =2926+ =29'.!9 =2939 PRNT1: =2931 i =2932 STRUTL =2933 =2934 =2935 =2936 ='.!037 STRmt =2931) =2939 =2949 =2841 =2942 =2943 =2944 =2945 =2946 COOEBLK 139 ORG 2:!6 OOlPUT (If: (f' F~ UTILlW DISPLA'/ PRM'TS (LEFT JUSlIFILD) fl.'C(RDII«l TO ACC ctIlTENTS (8-3). CLEff( DISPLAY All) OOIPUT CIflRACTER SlRIIIl STAATII«l AT Tl-E flOORESS POINTED TO I:IY BYTE itT roDRE.SS IN flCUJU.RT~. ~IIf. TO COP\' n STRIIIl (f OIl f'ATTI:RNS Fm! ROt! TO Tff. DISPLAY R[GI!.TERS. 5TRIIIl SIl.ECTED IS DETEF.IIII£D 8\' nee raN cnw.D. ON ENTERIIil OOTIf'..G, ACe CONTENTS lIRE USED TO ADDRESS A Il\'TE IN A LOOKlf TABLE ON TIlE ru:RENT PflOC IlllCiI CONTAINS f~SS OF A STRING IF SEGl'lENT PATTERN llflTA 8\'1 ES TO DE PRINlED ONIO Til. DISftAl'. TIE END OF TIlE STRING IS IN>ICHTED IfIEH 0I17 =1 CALLS SlIBROUTII£ 'IG)ISP' TO flCTlRLY EFFECT WRITING INTO Tl-E DI5PLAY REGISTERS. ft, 1STRU1L ADD CLEAR CALL A,@fl i'IOYf' 5TRTIf', A III'IOV R1, ISTRTI'IP I10Y @R1,A MOV ; LOll) NEXT CIIRRflCIIR LOCATI ON A, STRTII' I'KJY Ri, ISTRTI1P ItOY A,@R1 i'IOY A,@A i LOAD BIT PAllERN IN>IRl::CT KOVP JB7 PRNT1 ; OUTPUT TO NEXT CllARflClER POSITION CALL II>ISP STRTI1P ; I~X POINTER I'IINC R1, ISTRTIIP MOY fL@Ri I10Y A INC @R1,A I'KlV JIf' PRNT2 II>ISP JII' iDONE n:I, EQU 1>8 DB DB DB EQU DfJ DB DB DB 00 DB DB 00 DE; =2947 STRME" EQU DB =2848 =2tI49 DB =2959 DB LOW $ LOW(DERRQR) LOW(~) LOII(DRUIO LOW(DBPNl) LOll $ UJII(DIIOI) LOW(OOO) LOW(DF1LL> LOW(DLST) LOW(DREC) LOW(DREL) LOW(DSB) LOW(OCS) LOW(OOR) LOll $ LOW(DPRfllt> LOW (DDAI'IEI'I) LOW(IJRI1) All mnemonics copyrighted © Intel Corporation 1976. i UTILITY ;U1ILlW ; UTILIW i UTILl T\' I'ESSAGE I1E5SAGE I£SgJOE I£SSIU: 9 1 2 3 ADDRESS AI.JI)R[SS roDRESS ADDRESS i I:flSIC COI'II'fAN) 9 RESPONSE fIOORI:SS ; !!ASIC COI'IIflN) 1 RESPOOSE ADDRESS ; BASIC COI'IIfH) 2 RESPONSE ADDRESS i ElASIC cat1AND 3 RESPONSE fIOORESS i BASIC CO/II'ffl) 4 RE!.PONSE ROORESS i BASIC COItIAM) 5 RESPONSE flIlORESS ; BASIC COIfIAN) 6 RESI'ONSI: flD£*.tSS ; BASIC COI'\I'IIlN) .( RESPONSE ADDRESS .; IlfISIC COI'IIfH) 8 RESPONSE RlIlRESS ; DATA T't'I'E IIlDIFIt:R 9 RESPIWSE flDI)RESS ; DlfTA n'PE IQ>IFIER 1 Rt:SPOOSE roDRESS ; DATA lYrE IIODIFlt:R 2 RESPONSE AOORESS 1-111 inter AP·55A LOC (.(jJ LINE 11129 69 =2051 =2952 =295J =2Il54 =2855 =21!56 =2857 =2858 =2859 812A 65 912f) 67 9II2C ei2ca: 11121> 60 II12E E}" 1112f" 72 11139 75 !lOURCE STRTEI1ENl DB DB DB s) RGOC 1;00 DB DB DB 00 D8 L~(DINTRG) L~(DPRIJRK) LIII(OOlll'lJ:IO LIII $ L~(DI«lIRK) L~(DWBIIKt LOII(DSS) !:0II«()Pf\) LOW(DTR) ; DATA TVf'l IU>IFIER 3 RESPOlSE fWRESS ; DRTA TYPE IUlIFIEk 4 RESPONSE ROORESS ; llfiTR TYPE IUlIFlER ~ RESPONSE ftIDRlSS ;EXECUnOO ~ IIOOIFII:R ; EXECUTION ~ IUlIFIER ; EXECUTION IG)E 1IOO1fIER .: lXIDJTION I'IODE IUlIFIER ; fXCUTION I100E IU)IFIER =2868 .: 0131 0132 0133 0134 0135 01JG 79 50 50 5C 50 C0 1I1J7 013S 01J9 II1JR 00 76 GD 79 8flB 40 1113C 66 !lB!> E7 1113E !l0 !l1Jt 41! 0148 50 01411C 11142 54 11143 (,'0 8144 7J 0145 B9 =2061 ; =2062 ; =21163 DEf(R(JR: =21164 =2065 =2066 =21167 =2968 . =2069 =21170 DSGNON: =2071 =2072 =2073 =2074 =2075 =2076 =2077 =2078 DRUN: =2079 =20C9 =2081 =2982 =2003 =2084 =2085 OOfm: =2086 =2007 UTILITV OUTPUT I'ItSSFlGES 00 00 DB DB 00 DB 00 00 DB 00 DB DB DB DB 00 8111101118 1I101110ilefJ 111010000[1 010111001) 0101001l1l8 11001111008 i 'R' j '0' ; ; ...... .~. . 00000008B 011101198 01101101B 011110111[1 01000000B 011001100 111001118 ;' ~ ,." " 00 1110001l1.10B 1I1010001l1l 01101118 010181!l11E 111l1l01100B DB DB 11111811118 101111101B DB 00 00 ; IE' ; 'R' .i "H" ; '5' ; IE" ii_" ; 14" ; "9. "<1") ; I.' ; IR' i 'U' ; fiN' ; I .. • ;ara ; ·C.• =2088 mECT All mnemonics copyrighted @ Intel Corporation 1976. ' 1-112 II 1 2 3 4 infel' LOC OI)J 9146 ·,9 0147 J9 0148 F4 8149 31) 914A De 1l14E 71 814C :l0 014D IlS 014E. 38 1!14f 60 9158 Fa 9151 3E 0152 7J 915J Be 0154 5E 9155 ~4 9156 sa 0157 6D 0158 78 9159 Fe 91SA 39 015E J8 915C FC 01SD JD 915E 00 AP·55A LINE SOURCE STATEIf:NT =2089 ; =2990 ; =~1 ; =2092 DMOO: =2093 PF:11'flRY C~ [Jf; 911110018, 001119918, 11110190IJ , "EClt • =2094 000· =2095 DB 801111818, 110111888 ; -GO. 00 011108918, 081191.!1!0E), 10111000B ; 'HL.' =2098 DLST: =2099 DB 00111000B, 911011818, 11111988B ; 'LST. • =2190 DF:EC: =2191 00 901111100, 91119811E, 101111l09B j =2102 DREL: =210:1 /.l£I 010111100, 9191919011, 19111000B ; aDNl. =2194 DS&. =2105 OB 0111l11018, 011110Il00, 11111100£: ; "SIB.• =2106 DeC: =210, D8 0811111011), 00111900B, l1111100E ; 0ClO. =2108 DGR: =2109 OIl 1l0111191B, 11919001lE i =20% Df"ILL: =21197 = RESPONSE STRING f'RTTERN$ =2119 $EJECT All mnemonics copyrighted © Intel Corporation 1976. 1-113 u HlPL.• RGR. II II II Ap·55A lOC OBJ' 8151' 73 0168 00 8161 5[ 0162 F7 916:> 50 8164 00 9165 73 9166 rc 81e? 5E 9W) FC' -8169 76 8161l 00 816B 54 816C Fe 01GD lC 81GE 00 . 91er ro LINE ~ 51RTEI'IENT =2111 ; =2112 .; OOR',' srACE IU)IFIER OPTION =2113, =2114 DF'RI1EM' =2115 01119811[1, 119100e00 =2116 OOAI'IE.M: =2111' ~5PONSE STRINGS' ,"PR' 910111100, 11110111B .' -Dn. .. 8191I!BB0B, 10111101B ,'RG.• 91111!9118, 11111100B j DB 019111198, 111111008 i.OO =2124 DI NTRG . =2125 00 911191100, 119100WB ()[; =2111: DRI'I: =2119 '00 = =2120 DF'RBI':K' =2121 DB =2122 =2123 =2126 =2127 =2121: =2129 =2139 IPr:! .• ~I~' ; RESPOI6E MESSAGES rOR GO CONI) ITI ON MOO I FJ t~. ; ; DNOIlRI(: ; 1m 019191000, 111111900 I>B II - M =2131 IIIIIlRK: =2132 DB 911111008, 1111199008 ; "BR • =2133 D!;S: =2134 DB 011911918, 91191101[;, 11111000B ; 'SS1 • =2135 DPA: =2136 DB 01110111[l, 01111190E, 1101B0II0IJ' , "flBR. " =2B70TR: =2138 00 01110111B, 011011!!1El, 11111B90B ; "AST.• 9170 E;[) 8171 Fe 0172 77 9173 7C 9174 00 9175 77 9176 GI> 11177 F8 9978 =2B9 ; =2140 SIZECIi< =214J+ SIZE SET 120 =2144+; ******************************-*************************** =2145+; =2154 $EJECT All mnemonics copyrighted © Intel Corporation 1976. 1-114 AP·55A LOC OOJ 1IOC9 97 9OC1 R;' 99C2 B9JS 89C4 rt 90C5 C6D7 911C7 FB 99C892D7 99Cfl 29 89CEJ 47 OOCC 20 9OCO 39 09CE 1S OOCF 39 9IlD9 3478 99D214EC 99D4 97 991)5 94C7 .0007 FEJ eros 1>312 000Il C6E!i 900C Fa 9000 1)313 09I)f' Cf1:5 ·9OC1 BAIl2 99E3 24911 99[5 EJ846 9I!E7 8993 00E9 B4f5 99ED fJ3 992C LII£ sotJ/C( STATEI'ENT =2155 Coom.K 45 =21G0+ 1]10 192 =2164 ; INI'fIDR 1tf'UT DATIl INTO TI/O"BYTE PARlKTER IlIFFER ItlllCATED BY RB. =2165 ; RECEIYl lUDIC KEYS rRCfl KE'I'BOfWW !mIL '.' OR '. '. =2166 ; SHIH INTO I€lDRES!; B\.rFEI"; =2167 ; RE-WRnE I)ISPlfl'r'. =2168 ; IF I01BCR OF CONSTIIlTS 1£[1)[1) IS ZERO. t«J 1£1/ I'AfIfft:1U:S ff1E fUM!). =2169 ; =2178 IIf'ADR: CLR C =2171 Cf'I.. C =2172 !mY A.NIKON =2181+ I'm Ri. I/lftXlN =2182j· I'IOV 1I.@R1 =2186 12 ELSIrt =2187 1NPAD1: I'IOV A.KEY =2100 J84 EL!:.IF1 =21t.'9 XCH A. @R8 =2199 SIIlP A =2191 XCH A.i!R9 =2192 )(011) ILI!R8 =219:l INC R9 =2194 XCHD lURe lI'Dfl)R =2195 Cfll =2196 Cfl.L INPKEY =2197 CU: G Itf'fI)1 =2198 JI'IP =2199 ; =2290 ; El!.If1 IF KEY='. I ~ '. I TI£N RE'fmN. =2291 ; ='~a12 lLSIf1: I'IOV A..KE\' A.II(EYNXT =2293 XRI. =2294 12 ELSIF2 =2295 I'IOV ILKE\' =2206 XRl A.IKEYOI> =2207 J2 . illlF2 =2298 ; =2299 ; EL!.E GOI0 PERROR. =2219 ; =2'dl !lOY LDATA.'2 =2212· Jl'I' PERROR =2213 ELSIF2: PlOY R0.ISEIM' =2214 I'm Ri.13 =2215 CflLL OOI..ANK =2216 RET =2217 SIZECHK =2229+ SIZE SET 44 =2221+; =2222+;**-_**_ _ *~********** =2231 $EJECT __ All mnemonics copyrighted @ Intel Corporation 1976. 1-115 inter LOC OOJ 8178 D93A 917A 0193 817C F9 (;8 8171. 539F 9189 96CE 9182 D4D8 91fJ4 Fe 9185 47 9186 5301" 9188 9692 91SA D4D!l BlOC 2494 81SE D4DJ !l198 F~ 9191 47 9192 D4Dl 9194 F0 9195 D4Dl 0197 93 9920 L1/£ S(XEE STRTEI'II:NT COD£BLK J5 ORG 376 =2246 ; ~ tJ1)AT[ OODRESS FIELD =2247 ; (LAST nm CHf~TERS OF DISPLAY) WillI flOOfI'HI =2269 Cfl.L WOI5/' =2279 !'lOY fl, flIR9 =2211 ZIoIlI' /l =2272 ANI. A, tefH =2273 JNZ DSP!'I1 "2274 CRLL MOl51' =2275 JMP DSPLO =2276 DSPIII, CALL DSPACC =2277 DSPf1ID: I'IOV Il, tIR0 =2276 SWAP R =2279 DSPf11 CfLL DSPRCC =2'.169 DSPLO: I'IOV A, ~8 =2231 CfLL DSI'RCC =22C2 RET =221.13 SIZECIIK =2206-1 SIZl! !.ET 12 =2232 =2242+ 8178 9170 AP·55A =2'.!B7{ ; =2280+; =2297 $EJECT ***********-_**_*******____**___ All mnemonicS copyrighted C9 Intel Corporation 1976. 1-116 AP·55A Loe OBJ 8198 11198 1I19A 019C 019E 01!11" eIRe IlOO4 Er02 74D1 27 l>7 FEl 01Al D317 01A3 C6I)G 01AS 27 01AC 3400 01r.s FA I!lA9 041)3 01R!) 01AD alAr 01El 0182 01114 01£16 B93El 611F 14EC FD D3E 9698 0429 LINE SOURCE STATEMEN1 =22')8 CODEBLK 35 =2303+ ORG 408 =2312 ; r'ERROR . REPEAT =2313 ; OUTPUT J'/[SSAGl:(P~R()IU'ROI'IPT) =2314 • OIJTPUHLDATAl =2315; CAlL INPUUlI'lE(K[Y) =231G ; UNTIL KEI'='a.EIlRt'f'k'EII!OIJ.j' =2317 RCRflOR' MOil LI!ATn.14 =2313 PERROI"<- IIOV XPCOOE••2 =2m lkLL xrrrsT =2328 a.R A =2321 I'KJV P~. A =2322 II()\/ A. KEI' =2323 XRL A.IKE\'CLR =2324 JZ E.I1R0R2 =2325 CLR A =2326 CALL OUTUl L =2327 ItOV A, LDRTR =2328 CfU DSPOCC =2329 MMOIl KBOOUF. NEGl =2340+ PIOV Rl. IKCDClUF =2341t MOIl @R1. HGl =2345 CALL 1Nf'1(fI' =2346 MOil fl. KIY =234;' XRL fl.IKEI'E/{'l =2348 JNZ RERROR =2349 ERROR.,: JMP /'lAIN =2350 SIZI:.CIIK =2353+ SIZE Sf.T :s2 =2354+ ; **************',***************",***********************"***** 0200 2306 0202 8936 0204 61 020S 83 8206 er Irll!7 28 11288 22 021!9 lR 821!fl 11 0200 16 820C 2C 02I!D 2& 02I!E 2(; 82I!r 444f 9211 85 =2355i ; =2364 ; =236!J =2330+ =2384 ; IREM =2385 II'II'LE.I1: =2336 =2392+ =2393+ =2397 =2398 ; CODEDLK 80 oro 512 IIf'lU'[NT COMMfINI) 1l..ILOW(JI'II'TllL> /'/ROO A. OClJD( /'lOll Rl, .BCOOE 1100 fl, ~ JI'tPP (ffl /'lOll =2399 Jlf'Tl'.t.: =24118 =2481 =2482 =2483 =2484 =2485 =2486 =2487 =2483 =2409 =2410 =2411 =2412 DIJ LOW(JTO/'I()/) 00 LOW(JTOOO) LOW (JTOF"IU LOIHJTOLST) DIJ DB ·DB 00 D!l 00 DB ; JTOI1O[l: JMI' ; nOR[c' CLR LOW(JTOREC) LOWOTOREU LOW(COI'IS[:R) LOW(C~BR) LOW(JGORES) foXfl/'lIN Fe All mnemonics copyrighted © Intel Corporation 1976. ; r 0=8 ==) lEX FORmT DR1 A DU/'IP 1-117 Ap·55A LOC OIlJ 0212 B472 0214 0429 9216 5497 0218 042'.3 921A 85 0218 9S 021C B472 921E 0429 9229 8499 9222 W5 9224 9429 9226 8461 9228 BFI99 822!1 442E 922C 1JA01 922E 2304 0239 0232 i!233 0234 8236 0237 9239 023B El9J7 61 A1 F400 FB Dm 0230 023F 0241 i!243 0938 0191 OSSll 0090 9245 9247 0249 1r.!4B 024D C64D 14EC 0931 8199 14C0 E634 0429 LINE sotnE STATEPENT =2413 CALL flFILEO =2414 JMI' MAIN =2415 ; =2416 J10RR CALL f:ReCIN =2417 Jrt' MAIN =2418 ; =2419 JTfl..ST: CLR F0 =2420 CPL F9 =2421 HFILEO =2422 Jrt' MAIN =2423 ; =2424 JTOGO: Jrf' EPRUN =2425 ; =2426 JlOFIL: c/u COI'IFIL =2427 Jrt' MAIN =2428 ; =2429 JGORES: Jrt> COI'IGOR =2439 ; =2431 ; CCIIUlR C~ TO CLEAR BREAKPOINTS =2432 C!JICDR: I'KJY LDflH1I9 =2431 JIf' BRKfIL =2434 ; =2435 ; ctmSBR COItVlND TO SET BREAKI1JINl S =2436 COI'ISCR I'KJY LDftTfl•• 1 =2437 BRKFIL: !'lOY A..'4 =2438 I'troD T'lP1J n =2t48+ I10Y R1.'TVPE =24491 AOO n. @R1 =2455-1 I'1OV @rd. n =2459 BRKNXT: CALL L5TORE =246e 110\1 A, KEI' =2461 XRL A. IKEI'END =2462 Ji lJRKOO =2463 CALL IWKEI' =2464 ItIOV NUI'ICON. PLI.I$1 =2475+ !'lOY RL INI.JIUtI =2476+ I'KlV @Ri. IPlI.I$1 =2489 MOY RO. ISI'IflO =2481 !'lOY il'R0, 19 =2482 I'l'101/ 51'1A1H. ZERO =2493-1 I10V RL .2ftl1 =2494+ MOY @Ri.'ZERO =2498 CALL I NPRDR =2499 JNC DRKI«T =2""...00 BRl(END· JI'I' MAIN =2501 SIZECIlK =2504·f <:;Ize 51:.1 79 =2595+; cru ************************************************************ =2506+; =2515 $[JECT All mnemonics copyrighted @ Intel Corporation 1976. 1-118 AP·55A LOC 08J LINE =2516 =2531'1 924F 5~CE STATEl'ENT COOCBLK 75 ORG 591 =~35 ; EXAI'IIN EXAI'IINEII1OOIF'!' I'[~' COItIAND. =2536 ; DISPLAYS ME110RV f1ODRE55 SPACE OPT! ON, f'lDDfBS VALUE, AND CURRENT DflTA. =2537 ; READ!; 1([','BOflR() fIN) INTERPRETS RESPONSL 024F as 9250 am 0252 F1 0253 0326 9255 3492 0257 EB31 9259 347C 02".Al 2348 025D D400 lJ25F 14FC 1I261 FA 02(.2 9263 9265 92£6 926!) 47 D4D3 FA D4D3 14EC . 926A FE) 9268 9278 II:!6/) 026E 926f 11271 9273 0274 0275 9276 9277 9279 FA 47 5JF9 B675 27 95 68 AA F409 4459 =2538 ; =2539 ; OUTT'1JT_MES5AG( ( (1'II:roR\'_SPRCE_Of'n OH)(SMflY =' (DRTfLBVI E> ) =2549 EXAMIN: CLR F0 =2541 EXR/'I0: mlV A. TI'PE . =255fji 1'1011 R1,ITl'PE =2551+ MOV A, @R1 =~55 =2556 =2557 =255lJ =2559 =2!:>G9 =2561 =25&2 =2563 =2564 =25(;5 =2566 =2567 .: =2568 1 =2569 .: =2579 .: =2571 .: =2572 .: =2573 .: =2574 .: =2575 .: =2576 .: =2'577 .: =257C .: =2579 .: =2589 =2581 =2597+ =2601 =2692 .: =2693 .: =2694 .: =2[.e5 .: =2696 ; =2697 =2600 =2(;99 =2610 =2611 =2612 =2613 I,J Er wmt SYSTEM STATUS AND RELEflC...E. SEQlENCE IS AS FOLLOWS' IF L1J1tfIND WAS TERIIINffTEl) 8Y TIE 'NEXT' KEY: $lORE SI'IfI INTO EP PC; STORE EP PC INTO TOP··QF-STOC.K (RELATIVE. '/0 Er P'--U); PfiSS EP Re; PASS EP PSW; Pf\5S Er TIMER; PASS EP ACClKlATOR; MOV GILL n,12 OOTUTL ~Y A,NIJ1CON Ri, 1/UIC!14 A,@Ri EPC!I4T E.PrClO, 5Ift.O I10V i'IOY JNZ I'II'fO\I MOV I10V PlOY i'IOY MmY i'IOY I'IOY MOY Ri,ISlft.O A,@R1 R1, 1EI'PCl0 @Ri,A EPrCllI,5If1III RL IS/'IAHI A,@R1 RL IEPPCIII @R1,R !'lOY I'IOY . R,KE\' ftll 0YSIfIP SET If BREAK LOOIC FOR APPROPRIRTE Df."PEND ING 00 COOENTS IF '"M'('. III)Y I'IOY l'IO'II A,lWE RL.TVPE fl,@R1 AOO R,ILI»! GOTBL JII'I' (If! 00 LI»!(CGOtIl) All mnemonics copyrighted © Inlel Corporalion 1976. 1-122 BI\tfII( COtI)ITIIIIS, Ap·55A LOC ODJ 0472 8473 0474 0475 76 80 76 80 8476 99fD 11478 8~'91 047A 8482 947C 99F"C 847E 8482 0482 8484 9486 04eS ffi29 9flEF 991)1' F4F4 948f1 F4AC 948C r4flF 948E 37 84er F2!15 8491 86S9 0493 8400 9495 0499 9497 84ln 0499-B400 9498 8937 049D Fl 849E 93A! 9400 113 94Al A6 84A2 94A3 84R4 04A5 SA SA Afl All LIN[ =3929 =3921 =3922 =3923 =31124 =3025 =302G =3927 =3028 =3929 =3030 =3931 =3032 =31G3 =3034 =3035 =3936 =3917 =3938 =3939 =3049 =3941 =3042 =3843 =-3944 =3845 =3946 =3847 =3848 =3849 =3959 =3951 SOLm: STATEIt::NT 00 00 DB DB ; cGOpnr: CGOWO· AIIl.. OM_ Ji'tP LOW(CGQIoIl) LOW(CGOSS) L~(CGOPAT) LOW(CG()TRA) Pi, INOT Il90099100 Pi. 1990099911) Ept;>lJI4 ; CGOIID· ANI.. JI1P Pi, INOT 9IlIlOO911B EPRUN4 ; CGOTRA: CGOSS· In Pl, .il8OO9911B ; ; EPRUN4 SE1 Uf' CONTROL LOGIC TO RUN USER'S I'ROGRAI'I. , ~'ELEASE PROCESSOR TO f. BREAK EI'IUlf1TJON /100£, CONTINUE ACCORDING TO GO COItIAND TYPE . CfilL STSAVE i'II'JJV MOV I10V A, WI'E R1, ITYPE A, @Rl fl, 'UlII CNTmL flIA fllD JI'1PP DB 00 DB 00 DB LOW(BRKERR) LOW(EPRUN6) LOW(EPIWN6) LOW(CNTTRA) LOW(CNTTRA) All mnemOnics copyrighted © Intel Corporation 1976. 1-123 Ap·55A LOC 08J LINE SWlCE STRIDENT =3986 ; ~ BREAKPOINT LATCH IllS SE"I TllOOOH BREflKPOINl 5 NoT EIflBLED. =3987; DISPLAY =J9S8 1lRKERR: !lOY Il4fI6 BIl8Il 94IlS 249A =J009 ' 94AA om 94AC F1 =31!99 ; =3991 CNTTRA: I'II1OY =3193+ !lOY =3191+ !lOY 94AD 94F2 04flF F4fIF 94Il1 F241 , 0483 14EC 84B5 Fa , 94~ DlD 9488 96C7 94IlA 14EC 94BC FE 9400 D112 94Ef 96C7 94C1 2382 94Cl 3499 94C5 8441 94C7 9433 .M' I~ ~'a1I1ESSAGE. LOflTA, I9EII rH'J/OR A,DSI'll" Ri,'DSf'TIII fl,lIR1 =3195 CIU DElAY KOOI'(l. =3196 CALL =3197 JB7 ; Bi' SET INDICATf:S NO KEYSTRM. EPCNT =3198 ; =3109 ; Ef'RlK) IIf'UTCKEY), =3119 ; Ir KEY--OO GO TO PARSER, =3111 ; It.fUT KEY, =3112 ; IF KlY()1£l(T GO TO f'Al&R, =:!113 ; CONTINI..( IN SAI'IE 11ODE. =3114 ; =3115 EI'RI.Ki: CALL INPKEY A,KE\' =3116 MOY A,IKEYOO =3117 XRl =3118 JHZ EPREl =3119 EPRI.Il6: CALL IIf'KEY fl,KEY =3128 lIllY /I, IKEYNXT =3121 XRL =3122 JNZ L1'RET /1,12 =3123 I'tOY =3124 CAlL runm. =3125 Jill' Ef'CNT =3126 ; =3127 ; EPRET EXECUTIIIl I'IOOE IS TO BE TtRI'IIIflTl:l), =3128 ; JIJtP IN10 PARSER TO INTERPRET KE\' ALREADY DETECTED. =3129 EPRET: JItP 1lA1N2 =3139 ; =3131 SIZECHK =3134+ SIZE SET 291 =:1135+; =3BGi'; **t_**~,******._*_*_*_********_t "* =3145 $EJECT __ All mnemonics copyrighted © Intel Corporation 1976. 1-124 intJ LOC OOJ 85IlII 85IlII 74418S82 2383 85843488 858G 74511 8588 1lS8I: 858fl 746A 858C 8A28 Il5IE 2314 8518 91 8511 9fIOF !!:i13 8983 8515 F40B 8517 eA20 85199fU 8518 8903 851DF400 8!!1F B!lA5 8521 7461-1 1!523 F4D8 B928 8527 Ai 8:)25 8528 F400 852A 8922 852C Ai 852D F4D8 852F 8921 8531 A1 8532 1:400 8534 8536 !!:i37 8539 8923 Ai C8IlB 746A 8538 b'921 8531) F1 1153£ 87 853f 5387 AP-55A LINE sotm 51 ATEI£NT =3146 =3171+ =3175 ; STSAYE =3176 ; =3177 ; =3178 ; =$179 ; =3188 ; =3181 ; =3182 ; ·=3183 STSAVE: =3184 =3185 =3136 =3187 =3188 =3189 =3198 =3191 =3192 =3193 =3194 =3195 =31% =3197 =3198 =3199 ; =3288 ; =3281 ; =3282 ; =:a83 =3284 =:1285 =3286 =3219+ =S22B+ =3224 =3225 =3238+' =32$9+ =3243 =3244 =3257+ =3~O+ =3262 =32G3 =3276+ =3277+ =J281 =3282 =3283 =3292+ =3293+ COOEBLK 115 IE 1280 EP STATUS SAVE 9JlROOTlI£. F(gE CALL TO LOC 814H; SAVE EP ACC; $AYE Er TII£R; Sf1Yf:. EP P$II; SAVE EP Re; SA'IE EP lW-(F-5TACK IN EP PC; kE1U!N. EPfJRt( CALL R,13 /'lOY CAl.L OOTUll CALL OVSIR' 1\'8, 1l000(OY8OOS+OYSIZD /'lOY (M.0fl) CALL P2, 1II81!18OO81l Il EPt'ASS EPACC,f} 1\'1,tEM;C I!RLR EPPASS EPTlI1R, A R1,I£PTI~ @Rj.,A EPPASS EPPSW,R RLIEPPSW PRLA B'PflSS EPR8,R R1,1EPR8 @R1,A R8, 1l000(0Y1BAS'IOYSIZE> OYLOflD R,EPPSW fd.,1EPPSW A, f!fd. A A. 18711 All mnemonics copyrighted © Intel Corporation 1976. 1-125 inter AP·55A lOC OBJ LINE 9541 E7 85428388 =3299 =1J88 =3J81 =3J14. =J:U5+ =3119 =1128 =1121 ::JJ22 ::11J5+ 11544 854G 8547 8549 854B B9J8 Ai F487 93ft AA II54C 11924 Il54E Ai 854F 8551 11553 8554 85!J6 8557 0559 Il55A F4C1 B9J8 11 F487 fVl 5JF9 2A 1JFF 055C~ Il55E Il925 Il568 Ai 8561 4A IlS62 fIA Il56J F4C1 8565 Il825 8:i67 347C 9569 2348 056B D4DS 056() B82Il Il56F 3498 8571 03 8872 SW!CE STATEtt:NT RL roo /'IllY IIJV IIOY =:S~lG'1 =3348 =3341 =3342 =3343 =3344 =3345 , =3346 =3347 =3348 =3349 =3362+, =3363+ =1367 =3368 =3J69 =n78 ' =3371 =3372· =3173 =3374 =3375 =3376 =3377 , =3J88+ SIZE =3381+; II A.10SH SIIfl.O, A R1.ISIR.O 8RLA Cfl.l roD !lOY Ef'FET I'RlY IIOY El'PCl.O, A Rj"IEPPClO I!OV Cfl.l EPST~ I'KlY INC C/U /lOY All. XCI! AOOC AtL /'IllY IIJV IIOY 0Rl IIJV CAll IIJV CAll IU-2 WfllA,1I 8RLA RLISIR.O lIR1 E1'FET lDflTA. n A. 1111188888 A, looTA A.'-1 fl.18IlII811118 ErPCHI,A R1. IU'PCIII I!RLA A.lDflTA lDflTA.1l EPSTOR Re,1EPPcH1 lIf'1)fI)1' 1819888888 I'IOV fI, Cflll IIJV CfLl WDISP ; "-" ~ DISPlAY R8,IEPfJX DSF1IID RET SIZECII< 114 S£:.T ***-**********---*********--*-**** =3382+; =3391 $EJECT All mnemonics copyrighted @ Intel Corporation 1976. 1-126 intel' LOC OOJ 11090 90IIA 991A 9297 9297 34CD 9299 D31A 929B C6E9 929() D31A 829F 033A 92A1 9697 92A3 rooo 92A5 14F9 92fl7 E941 92A~ A1 92AA 14F9 92AC 9931 92AE A1 92flF 14F9 92E1 B938 92E3 fl1 9284 14f0 02868942 92B8 A1 92E9 8941 9200 F1 92b'C W:C 92BE 14F0 92C9 AA 92C1r490 92C3 341'2 92C5 B941 92C7 F1 92Cll 97 92(,'9 A1 92CA 4489 0:iCC 92CE 92D9 9202 92D4 II2D6 34CD 0331C6DB 033F 348/l 14F2 AP·55A LItE sotm STnTEI'ENT IIUOO£( :~9:HfILE.I'O) 3392 $ ; (CR) =3393 CHf1RCR EOO 0011 ; (Lf) =3394 CIm..F Et;'U 9FIl ; CONTROL-Z =3395 CNTRLZ [00 1P.H =3396 ; =3397 COOEBLK S9 =3412+ ORG 663 =3416 ; tlRECIN IlEXFILE RECORD IIf'UT ROUTINE =3417 Ift:CIN' CALL CHRRIN A, ICNTRI.2 =3418 XRL =3419 JZ DONE A, ICNTRLZ =3429 Xli'L R, ,(': ') =3421 XRL tRECIN =3422 JNZ CHKSUI1, ZERO =3423 ItIOV CH FOlR BIT VALlE. NOTE,· ~ ClECKING I.lOI£ TO VERIFY I£XIDECIIR. VALlDIT\' C/U CHARIN ; OCC=0F6-8FF FOR CllAROCTERS '8'-'9' ROO /l.. .-~ ; CHARACTERS ) '9' f'ROOlJCE OYEkfL~ 1M: NIBB ADD ; ACC=8"'5 FOR CIfIRIlCU:RS 'A' -'I·' ; ~ IF CHARRCTER BEllEEN 'S' IN> 'A' me ACC=0F61Hl5H FOR ClflRACTERS '8''''F' All mnemonics copyrighted @ Intel Corporation 1976. 1-128 intel' LOC OGJ 91C2 !!3FA 91C4 0310 91C6 E6C9 B1GS 83 91C9 E:Aen B1C1l 249fl 0015 AP-55A LIt£ SOURCE STATEtENT =3708 NIBI3: =37l.l9 =3710 =3711 =3712 =3713 ; =3"114 ; fl'IERR =$715 ASCERR =3716 =3717 =372l1t SIZE =3721+; n.I-·6 ADD ADO . A.I1BH JNC A'IfJ'F: ;ACC=0fflt·0fFfl for.: CHfIkflC1ERS '€I'-'F' ;f1CC=OOfHlFlI FOR CHARACTlRS '0'-'F'; ; OV£.f..'FLflI If f1IlO\J[ 15 JR!.(. RET ILLEGFt f£XIDECIMfll CfffllCTER i'KN LDAIn. leAH JI'IP PERROR SI2ECHK SET 21 ~,[CEIV£D =3722+; ******************~'************************'I"**************** =31'31 ; =3,32 ; 01CD B1L!) 1)449 1l1eF 537F 01D1 83 =3733 =:>743+ =3747 ; CUMIN =3748; =3749 Ch'ARIN' =3753 CODE81K 5 ORG 461 CHARACTER IIf'U) ROUTINE. RECEI't'[S 01£ fl'".>CII CHARACTER FROI'1 11£ LOGICft READER DEVICE. CAU CIN ANI.. n••7FH RET =1.752 SIZECHK =375S'f SI2[ 51: T ~ =~Z751 =3756+ • =3757+; t****************************~'***********************t****** =3l66 ; =3767 ; =3768 $EJECT All mnemonics copyrighted © Intel Corporation 1976. 1-129 inter LOC· 00,1 8572 9572 9574 9575 9S7? 8931 957lJ 957A 9S7B 1I!!711 8939 F1 8934 A1 9S7E rooo 1'1 8935 fl1 9SOO B865 Il582 14FC 9S84 1'1\ 9S8S All 9S86 18 8587 84£2 9589 E696 958B 34F2 FB 9388 E682 D49Il 0594 A472 95ro II5SE 9599 9592 Ap·55A SOO«I 5TATElENT LIIf: =3769 =3794i =3798 ; !-fILEO =3799 ; =J009 ; =3881 HFILEO: =3B17+ =3S1e+ =3B24t =3825+ =3820 =3S44+ =3S45i· =3851+ =3852+ =38:iS =3860+ =3864 =3865 ; =3866 ; LDB\'TE =3867 LOOVTE: =3868 =3869 =3879 =:ro71 =3B72 =3873 =3874 =387S =3f;76 =3877 =387S =3879 ; COO[[lLK 190 C»1G 1394 HEX FILE ooTPUT SlIlROUTIIf: lIEN CALLED WITH F9=9 OOTPUT IS STfHJflRO lEX FILE FORPIflT. WHEN CRLLED 101m: F0=1 ooll,\.IT IS rORllAlTED DA1A DUMP TO CRT I'II'IOY ~w MO\I MOV 1E11H1.. SPfAHI R1, tsI1flHl n, @R1 Ri, lIIEIVII A I'£I'ILO, SIRO Ri, 1Slft.0 A, toR1 MO\I~, I'mV MO\I MO\I 'ItJY MOY ItIOY MO\I MOV R1, 1tE1L0 @R1, A Clf(SU/'I, ~ CllKSUI'I, lZERO 1"9, 1HEX8lf LOAD /£XT B'r'TE FROI1 I'EI'IOR\' INTO lEX BLfFER CIU LFETt:f1 110V It, LDflTA MOV INC @Re, A CALL ,Ill: CllPI'IAS OOFIL CPU 110'' OOD JNC CAlL JMP R0 1NC'"J1A A, R9 A, t· (IllRlN+HEXBlf) L()[l\'TE HRECO IFILEO =3889 ; BUll 00 f£X FILE TRflNSI1ISSION· PRINT OUT BlfFIR FOR LAST DArn RECORD PRI NT OUT CAlf£D 'EOO-or· -FILE' RECORD 95% 959S 9S9A 959C 959E 9S9F 95A0 95A2 =3881 ; =3882 .; =3W3 ; RE1LRN. D400 =3884 CAlL IRECO B6/l7 34D2 B8AE 1'8 fl3 CCA7 =300S =38CG =3887 =300S E1I>F1: =300s =3899 =3891 =3892 =3893 =3894 HFOO/£: =3895 =3896 =3897 =3898 ; JFe· CIU ffDOl£ TCRlFO ~.'8, I(L(Io/ EOFREC) B4flI) . 95A4 18 85A5 A49E ~7 34D2 95A9 2310 9SAB S48D 0SfID 83 oom. MOV MOY I1OYI' JZ CALL Ill: Ji'IF' CALL I'IOY CllLL f\,@A ffOONE ClfIRO R0 [N>f1 TCRLFO fl, ICNTRLZ CfflRO RET =:r099 ; EOFREC CHARACTER SkTING FC»1 t'fllH:D END-{f-fILE RECORD rOR =3909 ; INT[l lEX rILE FORIIAT STf1NDARD. 95AE 293A3838 =3901 [OFREC: 00 ' :OO000091Fr' All mnemonics copyrighted @ Intel Corporation 1976. 1-130 inter LOC OOJ 05B2 39393939 95B6 30314646 9SBA 00 0049 AP·55A LINE SOlJ:CE STRTEI'lNT ; EIIl Of STR II«.i COO[ BVTl =3902 DB 9 =39113 51ZECH< =3ge6l S12E SET 73 =3997+; =3988+; ""***********************""*~-'''******.**-************'I''* =3917 ; =3918; II68Il Il689 FB 9601 9398 11603 8941 9605 A1 9606 3402 8688 2329 9600 B4CO 960C 8617 96IIE 233f\ 9WI II4BI> 11612 8941 9614 F1 9615 3400 9617 8935 11619 F1 1161A34DB 961C 13934 961E F1 1161F34DB 11621 B62B 11623 27 11624 3408 962(; C42C 9(;28 2330 ~B4BD 962C [:865 1162[ 8(;32 9630 C436 11632 2329 0634 E4BD 9&36 Fe 9m 3400 1lG391S 963A 13941 963C F1 . 11630 97 =J919 =j94!1+ =3953 ;~IIIECO =3954 ; =3955 URECO' =3956 =3957 =3970+ =3971l =3975 =3976 =3977 =J978 =3979 =3989 =3981 =3990+ =3991+ =J995 =3996 rDUl'\P1: =4005+ =4006+ =4019 =4011 =4929+ COOEBlK99 ORG 1536 HEXIDECIIR. REcoo) OOTPUT SEQlBa. lEX BlfFER ALREAD\' LOOOCD. A,RQ MOV A,I-fEXBlf flOO BlfCNT, A MtIOV Ri, IBUFCNT I'IOV ~,R MOV TCRLFO CALL fl, I' , /lOY CALL !lAW Jf9 FOOf'1 A,I' :' MOV CIU CIlARO ItIOY A, IllFCNT RL IBUFCNT A, @l.:1 ()'{fEO CALL R, I'EI'IHI tmV Ri, tl'lEl'IHl I'IOIJ A,@R1 !'IOV CALL B't'TE0 A, 1'E1'l0 ItIOY MOV R1, II'IEIt.ll A,@R1 =4921+ !'lOY =4825 C/lLl BYTEO =4926 Jf9 FOUI'IF'2 =4927 CLR A =4112!l CRI.L B'fTEO JIll ooTO =4929 =4039 FDltIP2: /lOY A, 1'=' =4031 CAll CHARO =4932 ;ooTO DAHl OUTPUT =4933 ooTO: MOV RfU/lEXBlF =4034 ooT01: JF9 FDUIf'5 =4035 Jl'IP f-0UI'IP3 A,l' , =403& F/.lUI'IP5: MOV =49:17 CIU CHARO A,@RIj =4038 FllUI'If'3: /'lOY =4039 CI1I.L BYTEO =4040 INC R9 =4041 1'IOJN2 BtfCNTI DAT01 =4046+ /lOY RLIBlfCNT A,@R1 =4047+ /lOY I)£C =4051+ A All mnemonics copyrighled © MOV MOV Inlel Corporation 1976. 1-131 inter LO:; OOJ 063£ Ai 8QF 962E 9641 B648 9643 fI) 8644 37 8645 17 964(; 3400 9648 83 9849 AP·55A LINE =4956+ 11)\1 I!R1., A =496&+ JNZ DAT01 =4062 ; =4IJ6J ; EN>REC EN) RECORD BEll«] TRANSMInEO =4964 EIMC: JF9 FDUI1I'4 =4965 .=4IlB1+ Ift)Y 11)\1 A, (;III(SIJI A, CfI(SIJI =4885 CPL A =4006 II«: A =4987 Cfll BVTEO =41J88 FDI..I?I'4: I5 94E9 83 9918 AU mnemonics copyrighted © Intel Corporation 1976. 1-133 intJ LOC OOJ II5IlB 95B8 34EG 85BD 11944 II5IlF /l1 85CII fl94J 95C2 BiIlB 95C4 97 ~F6CB 95C7 9geF 95C9 fl4CF 95CB 8948 ~ 95CE Il5CF 851>1 851>l Il5D4 011 011 94C9 94C9 97 A7 8944 951)7 F1 85DS G7 85D9 ft1 85J)S AP·55~ LII£ =4358 =4383+ =4387 ; NIIJO =4388 NIBO: =4389; =4398 ; 0fIR0 =4391 ; =4392 ClfRO: =4485+ , =4496+ =4419 =4421+ =4422. =4426 =4427 C01: =4428 =4429 =4439 CO2: =4431 =4432 =4433 COl: =4434 =4435 =4436 =4437 =4442+ =4443+ =4447'1 =4452+ =4455 =4456 95DR 8943 II50C f1 9500 97 050C R1 05DF 96C5 05E1 8l 11827 S(lf cle cle CI1 el1 ~' CI1 1B>I.A't' All mnemonics copyrighted © Intel Corporation 1976. 1-134 intel' LOC OIIJ 965B IIG5D 965F 9668 96G2 9663 94C9 5662 97 C465 97 A7 0664 90 fIG65 98 0666 ee 9667 ee 9668 8944 Il6GA F1 0C6B 67 966C R1 11661) 8943 9W" F1 9679 97 9671 A1 1lG72 %59 9674 B944 11676 F1 9677 83 IlIJ2F AP·55A sotm STAIDIEHT LIN: =4538 =45"".$9 =4549 =4541 =4542 CIl: =4543 =4544 =4545 C14: =4546 =4547 =4548 =4553+ =4554+ =4~-I =4563-1 =4566 =4571+ =4572+ =4576+ =4581+ =4585+ =4587 =45%+ =4597+ CfU IflDI..RY JT1 CLR JII' CIJ ; C1£CK SID LIN: LEII[l C Cl4 C C ; DATfI BIT IN C'!' CLI! (;f'l to' 10' NOr I«lP m1C I'IOV IIOV REGC R1,IREGC RRC IIOV tl)JNZ IIOV A @I/1,A El. CI2 R1,1B A..@R1 A @fU,A CI2 A..REGC R1,IREGC A..@R1 ; CIIRRACTER CO/fl.E1E IIOV DEC IIOV 1HZ ItIOY IIOV IIOV =4691 RET SIZECl-1< =46112 =4695t SIZE SET 47 =4696+; =46117i; ; EVEN OUT BmOf EXECUllOO TIlES A,~ *******_ _ _ _ _ _ _ _ _**'.:** =4616 $EJECT All mnemonics copyrighted © Intel Corporation 1976. 1-135 inter LOC ooJ AP·55A L11£ 4617 $ =4618 82E~ B9J4 92E7 F1 I12ES RfI 82E9 F489 82EB B4E2 82ED E6FJ 82EF J4F2 82F1 44E9 82FJ 8J =46JJt =4637 ; COIFIL =46JS ; =4619 mtrIL: =4655i =4656+ =4669+ =4672 LrILL: =4673 =4674 =4675 =4676 =4677 LFILL1: =4678 =4681+ SIZE ItnUllE( :~9:1EPI!Er.ID» COOEBLK 15 ORO CIltRI) IN LOll I1IKlY I'IOY I'IOY I'IOY CII.1 741 TO riLL fl)l)RESS SPfa: OCllEEN SIfl BYTE (f /'IEPl LDATA, 1ElL0 RL 1tElL0 A, I!R1 LDA·, A, A LSTORE III) EIII .. mlllRTft CfLL CI'fIft) JlI: LrILL1 CfLL INCSIfl JIf' U"ILL RET SIZECII{ SET . 15 =4682+; =468J+;**_*1..._IIIIII ..._*_ .. I _ _ _***II .. IIIIII .. 44 09FC D478 eerE flA 09FF 8J =4692 ; =4693 =4698+ =4792 ; LmCH =479J ; =4794 LFETCH: =4795 =4786 =4797 =4718+ SIZE =4711-1; COOEIlI..K 4 ORG 252 FETCI£S CIIlTENTS IF LOGICfl. 1£Im,' mDl. INTO 872F 8lS8 9732 8733 8938 Fl 5s7F C62f' E4C3 FA 11923 Ai 83 AP·55A LItE SMCE STRTEIENT =4915 =4958f =4954; =4955 ; LSTIJ:E =4956; =4957 LSTIIIE: =4966+ =4967+ =4971 =4972 =4973 ; =4974 LSTIIJI.: =4975 =4976 =4977 =4978 =4979 =4988; =4981 LSTI'tI: =4998+ . =4991+ =4995 =4996 =5885+ =5986+ =5818 =5811 =5912 =5821+ =5822+ =5826 =5827 =5828 =5829 =5838 =5831 ; =5832 LSTDII: =5833 COOEBLKSS am 1792 LOOICII. STIllE SlIJROOTItE STIllES cam:NTS (J LDfIm INTO YRRIOOS 1EIDl\' SM:ES. fl,TYPE IftJY ..w R1,I'M'[ ..w A, (IR1 fI)I) A, ILOW LSTTBL I!fl JII>P DB LOW LOW LOW LOll LOW LOW DB DB DB DB 00 /I'KlY ..w ..w JNZ /I'KlY IllY ..w fI)I) Je /ftlY IllY IIOY fI)I) IllV IllV IllY LSTPI1 LSTDII LSTREG LSTINl LSTBRI( LSTiiRl< fl,SlDtI RL ISIftfI 'URl LSTDII A, SlR.O RLISlR.O A, (IR1 Itl-OYSIZI: LSTDII ItS/R.O RLISIft..O . fI, I!R1 It IOYIltf RLA ItLDflTA f!R1, A RET ClLL lIlY =5834 11M( =5835 ;'5836 ; =5837 LSTREG: =5846+ =!IIM7+ =5851 =5852 =5853 =5854 ; .=5955 LSTR8: =5878" . =5884+ =5885+ =5888 =51189 ; =5898 LSTINl: Rtf PKIY IllV mY IN.. 12 JI1P /I'KlY mY IllV IllV LPGSEL A,LDflm !!H1, A It SlR.O R1.ISIR.O A, I!Rl A, 181lli111f1 LSTh'8 EPSTIR ; CI£CK IF LOW IJ.'DER BITS = 8 EPR8,LOATA ItLDflm RLID'R8 f!R1, A RET IftIY ItSIR.O All mnemonics copyrighted @ Intel Corporation 1976. 1-138 AP·55A LOC IEJ 07148930 0736 F1 0737 0320 97J9 A9 97JA rR 0738 Ai 073C 03 973D 073F 0740 0742 9744 9746 9749 974A 0749 9740 94£1 FA 1246 9ge1 E448 99FE 991'7 81 890B 03 004E 94E1 04E1 94E3 94E4 94E6 8937 r1 5301 47 94E7 8931 !l4E9 41 94EJl 4340 84EC 3A 94EI) 8930 94EF F1 WI! A9 94F1 93 9011 LINE SIX.m: STATEIEHT =5099-1 Ri,IS/ft.O I10V A,@R1 =5100+ 1m A,IEPOCC =5104 ADD Ri,A =5195 IIOY A,LOAm If.J\I =5196 @R1,A =5197 PlOY =5199 RET =5199 ; =5110 ; LSTIlRK LOGICRL STORE !W BmlK-POINT DATA =5ill LSTBRK: CALL Lf'GSEL =5112 t10V Ii, LOATA =5113 JOO LSTBR1 =5114 0Rl· Pi, t999ll09918 =5115 JIf' LSTBR2 =5116 LSTBR1: ANI. Pi, INO r 1IIl0IIIlIl01B =5117 L!::TBR2: AtI. 11., INOT 1l0Il011l01l0 =5119 I'KJ\IX A, @R1 =5119 OR!. Pi, tIl0Il0199IIB =5129 RET =5121 SIZECH< =5124+ SIZE SET 7S =5125+; =5126+; ***----"*****_*_******_*_ _***** =51~ ; =5136 COOEBl.I( 17 =5156+ ORG 1249 =5160 ; LPGSEL LOGICAL PAGE SELIOCI. =5161 ; SETS lJ' PORT 2 TO AOORf.SS Af'I'RtrRIATE BYTE !W RfIPI BLOCK. =5162 LPGSEL: I'II1OV A, TVPE =5171+ IIOV RUnoPE =5172·. I10Y fl, @R1 =5176 IN. fl, t090Il0II81B ; tfASI( Off DlITR noPE SElECTIII BIT =5177 SI«lP A =5178 IQ\. A, SIflHI =~104i roy R1, ISlftIi =5195+ OR!. A, f!R1 ~1!)9 ORL fl, 1019000098 =5199 =5191 OUTL I'II'IOV /lOY /lOY P2, A n, SlfLO Ri, 1Slft.0 A, @R1 RL A =5200+ =5291+ =5205 =5296 =5207 =5219-1 SIZE I'IOV . RET SIZECHK SET 17 =52W; =5212+;**-**_ _**********_ _ _*****=5221 ; =5222 $EJECT All mnemonics copyrighted © Intel Corporation 1976. 1-139 AP·SSA LOC OOJ LII£ SOO1CE STRTEl£NT . =5223 COOEBLK 11 =523".$~ 1I1F2 91F2 01F4 01.F5 01F6 8938 11 F1 96Ft 81f8 01F9 01FR 01FB 91fC 19 F1 17 31 83 OF:G =5237 ; IN;!;I1A =5238 IN;!;I1A: =5239 11«:11: =5240 =5241 =5242 =5243 =5244 =5245 498 11«:REl£NT ST~TII~ 1'E/IlR't' fl>DRESS WORD. I'KlY Ri, ISM.O It«: I«lY JN2 It«: I'KlY It«: XCII) @R1 R. @R1 11«:111 Ri A. @R1 A A. @R1 ~46 11011: RET =5247 SIZECII< =5250+ SIZE SET 11 =5251+; ******.----.. 02F4 02F4 8938 1l2f6 F1 02F7 07 02F8 21 Il2F9 96FF 02FD 19 02FC F1 07 02FE 31 02FF 83 Il2fl) =5252+; =5261 ; =5262 =5277f =5281 ; DECSIII =5282 DECSIIA: =5283 ~*******"*-**-**-** COOEBLK '12 (RG i'56 DECREI£NT SIIfl lOW. I'KlY Ri, IllY A. I!R1 ~ DEC' A =52re XCII A.1!R1 =5286 JNZ DECSIU =5287 INC Ri =52S8 I'KlY Pu I!R1 =5289 DEC 'A =52ge XCII> II. IR1 =5291 DECSItt: RET =5292 SIZECHK =5295+ SIZE SET 12 =5296+; mo =52S7·~;~** =5386 ; =5387 =5l32~ _ _**._ _ _ COOEBLK 15 (RG 1~ =5336 i CIf'IfIS COI1PARE I£IllRY ADI1RESSES =5337 i CIII'fRE SIfl BVTES WIlli BIA BYTES TO DETmlII£ RD.ATIYE IRlNlTWE. =5338 i RETIIlNS WITH CfflRY=1 IFF (SIIfl) )= DC It ElRiI ItlY flOOC RL IEIIIlI A, I!R1 RET SlZECII< SCT 15 =5481+;*.*'I:*.*********_ _ _ _ _* * - _ =54111 $EJECT All mnemonics copy'ighled @ Inlel Co'po,alion 1976. 1-141 inter lOC OOJ Ap·55A LIIE SIUCE STRIDENT 5411 $ IlUl.OC( :F9:KOO.I'ro) CODEBLK 199 =5412 974E =5447+ OOG =5451 ; =5452 ; 974E os 974F B93E 97~1 A1 975223f9 975462 8755 27 9756 3E 9757 3D 9758 FD 9759 97 07SA 3f 0758 OC 975C AA 0750 07Sl 0?Sf 0761 9762 9763 0764 9765 FD 97 0346 ~ AM) =5453 ; =5454 TIINT: =5455 =5468+ =5469+ DISPLA\' PROCESSINl ROOTII£ I'ERIOOIClLl \' loRN KIlO fH) DISPLAY fl.'E "fO BE fl.IYE. 5El R81 ItKJV AS/lYE, /1 ~ R1,1ASf1Y[ IlO\l @I/1,A CfU[J) ~ =5473 =5474 =5475 =5476 =5477 =547lJ =5479 ~ QR llOYD llOYD ~ DEC /'lOYD =5489 =5481 =54!J2 =5483 =5484 A,'(-19H) I, A R PSEGHI, A PSEGlO, A R,ruIDIG I'IOY IlO\l R, ~D JG DEC AOO 1'10'1 R, t<"...EGIR' f'IO\II) ; REUB> TIllER INTEIt-1<*******~'*********************************************** =5549 ; 076F B93C 9771 F1 =5541 =5550+ A, mtOC =55~1+ A,~1 Rl, tKE'r'lOC All mnemonics copyrighted © Intel Corporation 1976. 1-142 AP·55A LOC OEJ LIIE em 2C em DC =5556 e774 C67C 5O.E[ STATEI1ENT =5557 =555e ; =5559 ; =5568 ; =~561 ; =5562 ; =5563 ; 0776 B9JD =5564 9778 8106 I177A 1:488 =5SGS =5566 =5567 ; =5560 =5569 =5578 . =5571 =5572 8nc B93D 8nE F1 ilIfF C6BB 9781 07 0782 !J93D 8784 Al 07ElS 968B XCH XRL J2 =5555 . A. LHSTK'r' A. LASTK'r' SCAN3 ***********-***************-*-**-** A DIFFERENT KEY If1S R£AI) ON THIS C\'CLI:. THAN III THE PREVIOUS C\'CLE.. ; ; ; ; ; SET NREPTS TO THE OCIlOONC[ PARAME1Ell FOR A NEW COUNTDOWN. *****___ t***********_*_*****ot-******,t,***~:***** mil I10V JI1P Rl.INREPTS @R1.1G SCAN5 *****__**,t:*_-************_*******************_** SAI1E KE\' WAS DETECTED 3S III PREYIOOS CYCLE L()()I( AT Nro'TS: IF ALREAD\' ZERO, DO NOTHING. •ELSE DECREI'IENT NRCPT!;. IF THIS R£SIUS IN ZERO, /'lOVE LASTKY INTO KOOCUF. =5573 ; ***:t:***_**~·*********-~******************************_*** =5574 ; A.NR[PTS =5575 SCflNJ: I'IMOV R1,INREPTS =5584+ MOY A,~1 =5585+ I10Y ; IF flLREflD\' ZERO =5589 12 WlN5 ; INDICATE ONE I'IORE SOCCESIVE KE.Y DETECTION =5590 A DEC I'ItlOV NREl'T5. A =5591 RLINREPTS =5684+ MOY =5685~ I10V ~1.A =5689 =56HJ =5633+ JHZ SCANS I'II'IOV !'lOY KBD8UF. LASTK\' 07se =5639·~ I10Y 97SA 111 =5649+ =5643 ; =5644 SCIlN5: =5645 =5646 =5647 =5643 =5649 ; MOY 0787 Fe B93B 0788 B93C 0780 11 07aE EC63 0790 EDIlS iJ,'92 t;OOS MOV INC DlNZ DJNZ I10Y ; IF DECREMENT DOES NOl RESlU IN ZERO ; TO MflRK NEW KEY CUYJ.JRE /), LflSTKY R1,IKBOOUF @FILA Ri.IKEYLOC @R1 ROTCNT, NXTLOC CURDIG, TIRET1 CURDIG. lICHf1RNO =5650 ; ******~:*****~::{:*****_***********,t,*********_*_*~:***** =5651 ; THE FOLLOWING CODE SEG/'IENT IS IJSEl) L.... UIE KEYBOflRD SCAItlING ROUTINE;. =5652 ; IT IS EXECUTED ONL \' AFTlR r. REfRESH SEQUENCE IS COI'IPLETEO =5G53 ; =5654 ; =5655 ****************************......*****'t:********'t"t.*_**-.. 9794 B9:>C 0/96 Bllil0 =5666~ lIns rl: =5671 =5672 =5673 =56j'8+ =5632 ~ANS: =5683 ; 0799 969D 079B BCFf079D BE90 =5667·~ I'II'IOV !'lOY I10Y I10Y JHZ MMOY MOil I10Y KEYLOC, ZERO R1, lIKEYLOC @RL.ZERO 11, KEYFLG ; JUI1P IF AN\' KEYS WERE DHECl ED SCANS ; CHANGE (LASTK\') WHEN NO KE\'5 lIRE DOWN LAST((Y. NEG1 LAS1 K',', llNEG1 KE\fLG.1I0 All mnemonics copyrighted @ tntet Corporation 1976. 1·143 inter LOC ()(jJ AP·55A SOIJ!CE STAT£]'I[NT lifE =5G85 ! =5636 ; KOOIDISP RETURN COO[- RESTIMS SYSTE" ~TATUS. A, RtlELA't' I'II'IOIJ =5696+ Rj., IRDELflV !'lOY R,@R1 =569;'+ I'IOV =5791 JZ lIRETi =5782 DEC A k'OCLAI', A =5793 I'IMO\I =5716-1 I'KlY R1, IRDELA\' @RLR =5i'17+ tIOY =5121 TIRETi: I'II1OY A,AS/We =57J3-I !'lOY RLWJlYE A, INd. =5731'1 I'IOY =5735 RETR =5736 ; =5737 ; =5738 ; TOFPOl. TIIa OVERFLOW POLLING sueROOTINE. =5739 ; CfUED REl'EATEl'il..Y FROI'I IKID'ER I(BllIDISr /'lUST BE. fiLlYC. =5740 ; I'OIITOR!; mE TIIG OYERF1.1101 FLAG 3 5:;or 06D5 83EF 0607 A3 0600 AE =5907 =5937+ =5941 ; OSF'ACC =5942 DSPACC: =5943 =5944 =5945 ; WDISP =5946 ; =5947 ; =5940 WDISP: __ COOECLK 44 ORG 1747 DISPLAY VALUE or LOW NIBBLE Of IICC ANt. fl. IffH ADD A, #OOPATS MOVP A. @A WRITES BIT f-'AlTERN IJOW IN ilCC INTO NEXT UiARfICTER rOSITlON OF THE DISPLAY (NEXTPl). INCREMEN1S NEX1PL RESULTS IN DI$PLA~' BEING FILLED LEFT TO RIGH"f. lHEN RESTARTING MOV DSPTMP. A All mnemonics copyrighted @ Intel Corporation 1976. 1-145 inter LOC OOJ 0609 BF04 9600 7401 AP·55A LINE =~949 =59~ =5951 96DD 0CDF 061:9 06£2 960 96E4 893R F1 9345 R9 FE A1 96E5 96E7 96ES 96E9 96EA 093A Fl 97 A1 96EE 9(;[C !l10S 06EE 83 IlIlEF 96EF 0Cf9 96F1 116F2 116F3 06F4 96F5 96F6 06F7 06f8 96F9 86rA 86rE 96FC 96FD 06FE 3F 96 5E 4F 66 61) 7D 97 7F 6"? 77 7C 39 5E 79 71 882C =5960+ =5961+ =5965 =5966 =5967 =5968 =5969 =5974+ =5~75+ =5979+ =5984-1 =598S~ SOlJ.'CE $TRTIJENT I10Y CflLL MMOY /'f0',' 110',' 000 tm !'lOY !'lOY Ml)JN£ I'IOY I10Y DEC 110',' JNZ =59'"j9 MOOf =5991 WDISP1: RET =5992 .; =5993 ; OOPAT$ IS TI:E =5994 ; I-IERE. THE FULL =5995 ; =5996 DGPAT$ EQU =5997 ; =5998 ; FORI'IAT 1$ =5m; DB =600Il =6091 DB =6092 DB =6003 DB xrcOOE,14 XPTEST Il,NEXTPL R1, INEXTPL iI; ~1\'1 Il, #$EGMflP·1 R1,fl A, D5PTMf' @ld,A NEXTI'L, WI) ISPi R1.iNEXTPL A,@R1 R @R1,A WDISP1 @Rl, .CHARNO BASE FOR THE TAIlI.( OF $EGMENT PATTERNS FOR HEX DIGITS. I-lEX SET (0··n IS INCllVED. f AND 0fFH PGFEDCBA 1l8111111B eee09110C 01111191113 91091111& DB 01109111113 =6004 01} 01101101& =6995 Of) =6006 91111191El Of) =6807 00009111B 91111111B . =6900 I.lfl 01100111B =6999 DB =6010 00 911191110 Of) =6011 91111100E: =6012 011 001110018 Of) =6013 019111100 =6914 DB 011110018 .811100018 =6915 00 $IZECHI( =6016 =6919+ SIZE. SET 44 =6920+; IN STANOORO SEY[N-Sl(i1'lENT ENCODINU C(JI\IENl ION WHERE r REPRESEN1S TIlE DCCIIR POINT ; SEGMENT PATTERN FOR DIGIT '9' ; SEGl'ENT r'ATTERN FOR DIGIT '1' j ~EG1'IENT PAT! ERN FOR DIG IT '2' ; SEGMENT PATTERN HlR 0IG n '3' ; SEMNT PATTERN FII: 0IG IT ' 4' ; SEGMENT PATTERN FOR DIGIT '5' ; SEGI1ENT PRTlERN FOR DIGIT '6' ; SEGl'lENT PflTTERN FOR DIGIT '7' ; SEGl'ENT f'fITTERN FOR DIGn 's' ; !;EGIlENT PATTERN FOR DIGIT '9' ; SEGI1ENT PATTERN FOR DIGIT 'n' ; SEGI'fENT PATTERN FOR DIGIT 'B' ; SEMNT PATTERN FOR DIGIT 'c' ; $EGI1[NT PftTTE.RNTOR Dlull 'D' ; SEGMENT PATTERN FOk OIGIT 'E' ; SEGrlENT PATTERN rll: DIGIT 'F' ******************************-******************** 94F2 94F2 893F 94F4 Ai =6921t; =6039 ; CODEEllK 12 =6031 1266 =6051+ ORG =6055 ; DELAY SUBROUTINE IofIITS FOR TIlE NltIBER OF COItPLETE =6056 ; DISPLAY SCANS CORRESPONDING TO THE ACC CllfTENTS. USE!) WITH CRUDE Ill..l'Im INTI:RrRCES- AS WHEN OPERATOR SlW..D SEE =6057 ; =6958 ; SOI'IE DISPLAY CHANGE IoIIIU: IT IS CHANGING: ROELAY, It =6959 DELI1Y: /'fI1OV =6072~ 1'10\1 R1, 'RI>ElR'o' @R1,A =6073+ I'lO\l All mnemonics copyrighted © Intel Corporation 1976. . 1-146 AP·55A LOC OBJ 84F5 F4AC 9417 D93F 114F9 F1 I14FA 96F~ I14FC 83 LIM: SlUCE STATEPENT =6877 ocLAI'1: CALL lOITOL =697B A, ROCLAI' =6987+ =6888 f =699'.1 m:lV MOV RLtRDELR\' I'tOV fi,~1 JNZ DELAY1 =6993 RET =6B94 5IZECHK =6097+ SIZE SET 11 =6998+; =6899+; =6198 ; =6199 **...*******~,*"......**_**********...**..***...._***.. COO[8LK 8 87fIF =6144+ 87fIF 8F95 =6148 ; KeDl'OL POlL STATUS (f KE.I'SOARD INPUT ROOllNE. =6149 ; RETURN loin II ACC BIT 7 =, 0 IF KEI'SOfIRD IWUT HIlS BEEN RECEIYED. =6159 KBDI'OL. I'tOV XPCQDE, 115 9781 7401 07B3 B93B 9785 F1 97EJ6 113 =6151 =6152 =616H =6162+ =6166 =6167 (IlG CflL I'IIIOY I10Y MOY 1967 XPTEST n, K8DBI.Jf I~L .KElDBlf A, ~1 RET SlZECHK =(;179+ SIZE 5[1 B =6171+; =6172+; ***",*.*~,**",*******,,*************-**********--****~, =6181 SEJECT All mnemonics copyrighted © Intel Corporation 1976. 1-147 inter. LOC OOJ AP·55A LINE SCdJRC[ STATEI£NT 6182 $ =6183 =6218. 97E7 97E7 9789 971lR 97BC 971£ 97C9 97C2 IInUDE( :F9:LINK.I1OO) COOECLK 15 ORG 1975 B9J9 F1 F4DO 2389 F4D0 F4D9 83 900C 97C3 =6222 ) Ef'fET =6223 EPFET: =6212+ =6233+ =6237 =6238 =6239 =6249 =6241 =6242 =6245{ SIZE =624&+) FETCH DflTIl B\'TE FROM Er INTERIft. RAP! ADDRESSED B\' 5IR.O. I1I1OV A, Sl'lALO MOY R1.. tSI'R.O MOY 1l.@R1 CALL EPrASS MOY CALL CALL A••19999080B £l'PA5S EPPASS RET SIZECH< !.El 12 =6247+; ~. *****>t.***_",,**_**********_"'******'I"*****~"************ =6256 ; =6257 COOEBLK 15 =6292~ ORO 1987 =6296 ) EPSTOR STORE DATA IN Loom IN EP INTERIR. RAt! AT (SIflO) 97C3 rA 97C4 F4D0 97C6 8939 9i'C8 F1 97C9 5371" =6297' EPSTOR: =6298 =6299 =6300+ =6399+ =6313 07CB F4D0 =6~14 1l7Cl> F4D9 07CF 83 =6315 =6316 MOY Cill I'II'IOV A. LOOTA El'PASS A. SIfl..O RL .SMALO !«)II A. @R1 /'lOY AN. CALL CALL A, 1011111111) EI'Pf1S5 EPPAS5 RET SIZECUK =6329+ SIZE Sll 13 =6~17 =6121+) *-*****"'****"''''************'''************-************ =6122+) =6331 $EJECT All mnemonics copyrighted @ Intel Corporation 1976. 1-148 intJ LOC OIlJ 9700 AP·55A LINE !>OI.RCE !il flTEMENT =63J2 ; =6333 ; THE rOlLOIolING UTILITIES IN'r'Ol't'E INTERCIfINGES IlETloEEN TI£ 1'If' =6334 COOEIlLK 11 =6369-1 All) [Po ORG;:'000 =6373 ; EPPASS PASSES II SINGLE f'fII'7F400 9709 81 9700 BJ =6377 ; RET~N. =6370 EPPASS: OI\t P2••99110099B =637S 1'10'(;( liR1.fI =6300 =6381 OR\. AIL =6382 =63!B CAlL IIOYX =6J84 RET ; lNABlE llNK WRITES. ; WRITE ACe '10 LIN(. ; OI5ABll BREAKPOINTS. ; SET TO EREIlK ON LINK RlFERUU. Pl. INOT ENIlRPoPI P1.ICNIlLNK ~f'51 EP fl. @Rl =638:> SIZECflK =6333+ SIze SE.T 11 =6389-1; =6399+; **********.*************~.~,****'1"**-"'I-.****** =6399 ; =6499 9700 9700 F4f4 9700 Il99A 97Df 861"1 97E1 E9I)~ 9788919 97E5 744f 97E7 B8BB 97E9 746R 97ED 99EF 97m Ilfl9E 97EF 249R 9i'Fl 744f •••" ••*.* COOCBlK 2J =6435+ ORG 2011 =6439 ; EPS1Er RELEASES EP TO RUN IN PRESENT "00[ lRlTIL AN f1NTICIPAlm =6449 ; IfflROWARE BREAK OCCURS. =6441 ; (DUE TO SINGLl STEPPING, UNK Il'Coo[ FETCH. ~ LINk DPoTA mCH. ) =6442 ; I'IUST OC~ WIlHIN fI FINITE NUlt3ER Of ClUES «49 I1f' CYClES) =6443 ; OR IoIATCHDOG TIMER WILL RSSUME A COMtlUHICATIONS [R~OR =6444 ; BETWEEN TI[ If' I1lD EP. =6445 EPSTEP: CALL EPREl =6446 I'IOV R1, 119 =6447 EPSTE1: JNI EPSTE2 =6448 DJNZ Ri, EPSTEt =6449 ORL Pl. iEPRSET =6450 CtlLL EPERK =6451 MOIJ [,\1, ilOlolWY1BA5+0IlS1ZE) =6452 Cflll O't'LOAD =6453 ANI.. Pi, INOT EPRSET =6454 1'1011 LDATA, .9E1l =6455 JIf' PERROR E~'IlRK =6456 trSTE2: CALL 97f3 83 =6457 =6458 9919 =6461+ SIZE SI:."T =6462+; =6463+; RET SIZECHK . 25 **"'******************_*'1"'****__**_*********_ =6472 ; =6473 ; =6474 *EJECT All mnemonics copyrighted @ Intel Corporation 1976. 1-149 intJ LOC OOJ AP·55A LINE SOlE[ =6475 COOEBLK 9 =6510~' 1l7F4 07r4 07F6 07F8 07FA 07FC STflTEI£NT ORG 2036 =6514 ; fJ'REL RELEASES Er TO IN PRESENT 1I00I:. =6515 ; Sl:QUENCE IS AS FOLLOWS: =6:116 ; PUT 1'IEI'llR\' flRRA',' IN EP I'IOOE; 99f7 890S 9fI3F" 8904 83 m. =6517 ; RAISE ISSTEP; =6518 ; RETURN. =6519 EPREL: fK. Pi. lOOT CLREFF =6529 P1,ICLRBFF OR\.. =6521 IK. P2. lOOT 010II08II0B =6522 ORL PL 10000010011 =6523 RET =6524 SIZECH< =6527+ SIZE SET 9 ; CLEAR BREAK FIF. ; RE-OHlLE BREAK f IF. ; ElflBLE Er COOTRll. IF IEII fRRtW ; fREE EP TO RUN tllTIL 1J.'EflK. =652St; =65:ro ; =6519 ; 034f 034F 99FB 03:51 8929 8353 B995 0355 E955 0357 9A48 0359 83 11 =6540 =6588+ COOEBI.J( =G5B4 ; EPBRK =6565 ; =6586 ; ~7 ; REGAIN COOTROL Cf I'EJ'IOR',' ARRftY FRa'I EP. DROP ISS1EP; IIIIT 30 USECS.; PUT IDORY ARRfI\' IN If' i'IOOE; =6508 ; RETLm ORG =6589 EPBRK: fK. =65S0 0I\'l =6591 t«lY =6592 =6593 =6594 =6595 =6598+ SIZE =6599"; ()JNZ 047 PL lOOT 000001000 Pi. II'IOOOUT Ri. 15 R1, $ P2,I010001l001l ORL REl SIZECHK SET 11 ; FRlEZE ElU.ATION PROCES!;(R. ; SIGIR. EI' IS ooT RIHIING USER COOE. ; 1>EUl\' FOR Ef' TO FINISH INSTROCTION. ; SEIZE CONTROL or I'IEJ'I ARRfl','. =6609 ; 9351: 0917 =6610 ; =6611 =6651+ =6655 ; OYSWAP =665C ; =6657 0\I5IflP: =665S 835E 2340 =6659 0:s60 3A 0361 ca =6G60 =6661 OYSWi: =6662 DEC I)(C R1 =,6663 I1OY'O< Ii, @R1 ItJV;< fl, @R0 @R1. A 0351\ 8J5A B865 8362 C9 0363 81 0364 20 0365 91 0366 F9 83679661 8369 83 =66(;4 =6665 =6666 =6667 =6668 =6669 COOEBLK 16 ORG S5fJ OVERLAY !;Wff. SWAPS BLOCK OF DAlf1B','TES (USER'S /'lOY RIl,IOYIlI..f+OIlSIZE I10V Ri. IOYSIZE /'lOY R. l01i10OO0eB OUTL Fr.?, A xi:H R0 I'IOV A, Rl JHZ RET OYSII1 SIZ[CHI{ =6672+ SIZE SET 16 All mnemonics copyrighted @ Intel Corporation 1976. 1-150 ~) BETIEEN '" RAI'I & EP PIt AP·55A LOC OOJ LINE S(uCE ~TRT[Il.NT =6673+; 8361l 8J6A 936C 9J6E 936r 8370 8371 93"12 9373 8374 8375 8377 =6674+; ***-.*****-****~:*********~:*************-*********.*. =6603 ; =li684 COOEBLK 14 =6724+ (J.'G 874 . =6728 ; OYERLA'I' LOAD. =6729 ; I'KM$ IlLOCK Of OOTAEYTES (flSSlllliD ~(''E) fRc.I PG3 10 EP PII. =6739 ; TOP Of DIlTA BLOCK LOAI)(]) AI«) BLOCK lEMlTIl DETERtlIIf:D B\' 1!9 IliI Ri. =67J1 OYLOOD: IIOY R1.IOYSIZE =67J2 tIOV A, 1019080000 =e7J3 OUTl f'2, A =6734 IIL01: DEC R8 =6735 ' DEC R1 =6736 MOY fl, R9 =G737 MOYP3 fI, @A =6738 I'XJYX ~1, A =6739 MOY fk R1 =6740 JNZ 191..01 =6741 RET =6742 SIZECI-IK =6745+ SIZE SET 14 =6746+; ovum 1l91i' 2340 3f! C9 C9 Fa EJ 91 F9 9G6f 83 _****_********__*************11:****_************ =6747+; =6756 $EJECT All mnemonics copyrighted © Intel Corporation 1976. 1-151 inter lOC OOJ AP·55A Uti: SOO!CE STRTDENT =OlS7 ; ,=6758 ; =6759 ; =6768 ; =6761 ; =6762; =6763 ; =6764 ; =6765 ; =6766 =6771+ 8178 =6775 ; =6776 ;0Y8~mi =6778 ; =6779 ; =6789; 8378 8378 8378 1489 rnA 88 8378 8378 1489 837D 88 837E 88 837F 837F 8381 8382 8383 1489 88 88 88 8384 88 8385 8386 8387 8388 8389 118 88 88 88 88 83SR 88 8388 88 838C 838C 8816 84w.) 11£ REST (f lHIS PIOOllE COO'A1NS THE "INI-fOUTIJ1S IfIICH OYm.R'1' 11£ EIllRTIIII f'ROCESSG< PI\'OG:RIf RfII 10 GIVE 11£ /lASTER PROCESSCJ: ACCESS 10 INlERIR. REGISTERS IN> RAIl IX- 11£ Ef'. DflTfW( 22 ~ 80S OYERI.RY 10 IIREfI( EP EXECU"l11II fIN) JlJIP TO lOCRTIIII 8II9H. lOCRTIIII II8SII REfICIEI) WITH T(J'-(f"-STfO. = RETWI OODRESS+2 DIE TO FIJ1CEI) "CAll" DURING IfIICH PC IllS INCREII.NTED. lOC!; 88JH & 887H CfLll!99H TO SIIUlITE ~ ctN>1TI0N IF BREAK ~ DURING INll"Rru'T C\'Cl.E. SOl(!CE CODE FIJ:1 mNI--IDInm 0YERlA\'ED OYER lOll ImDER PROOkRII RAIl. . =67!l1; =6782 ; $ =6783 0\IIl8RS EQU =67fJ4 ~ OYIIBRS =6785 CAll 089H =6786 =6787 =6788 =6789 10> i ~ =6798 0Y9IIRS+883H CIU 8891-1 10> =6791 =6792; =6793 ~ I«JI' ~f94 CIlll 10> =6795 =6796 =6797 =6798 =6(99 =6S08 =6881 0V9BflS+887H N(J' I«JI' to' NO!' NOP =6882 10> NO/' =6883 NO!' =6884 =6885 =6Il86 ; 10> =6S87 ORG· =6888 =6889 i =6818 =6813+ SIZE 8891-1 NOP OY8IIRS+814H 8891-1. JI1I' SIi::ECII< SET 22 =6814+; =6815+;-**=61124 $EJECT All mnemonics copyrighted @ Intel Corporation t976. 1-152 inter LOC OOJ 838E 838E 83CE 938E 9499 8399 09 AP·55A LINE =6825 =68J9+ =6834 ; =6835 ;fRJ=6IlJ6 ; =68J7 ; =6839 ; =68J9 ; =6Il49OVJBAS =6841 ORG =6842 =684J SWkC[ STATEI'ENT DflTIIlLK 22 919 ORG OYERLR't' TO SAVE STATUS DflTA IFTER 1lREfJ<, fICC. TIPlER/COUNTER. PSW (WITH F1). & RflII LOC 9 PASSED SEQl(If1 IfillY 10 1'1'. Slm:E COOE FOR "INI -IIlNITOR OVERLA\,ED OYER LOll ORDER I'ROGRffI RIll. EQU $ O'r'3IlAS JI'IP MH NOr =6844 ; 8391 8391 9392 9393 8394 83 09 09 09 9395 9395 83 85% 09 8'397 839799 8398 42 8399 99 8l9f1 C7 8398 7611 8390 53F7 8311 939F 99 83A9 C5 83A1 Fe 83R2 9499 9916 =6845 ORO, =6846 =6847 =6Il48 =6849 =6S59 ; =6851 OOG =6852 =6B53 =CS54 ; =6S55 ORG =6856 =6857 =6858 =6859 =CS69 =C861 =6862 0Y3Il1 =6863 =6864 OV3IlAS+99JH RET NO!' NOI' Na' fR3BAStll97H RET NOf' 0Y3IIA5+1l99H tIOVX ~.A I'IOY I'KlYX I'IOY @R8.A A. T A./'SW JF1 fR3B1 11. 1111191118 (LOW 0Y3IlfIS) IN.. *- roo I'IOYX ~.fl =C865 I'IOY RB0 A.Re =C866 =6867 ; =6868 JI'I' Il99H sa SIZECHK =687H SIZE SET 22 =6872+; =6873+;_*('********_**('**"'****_*_ _ _*_ =6882 *EJECT All mnemonics copyrighted © Intel Corporation 1976. 1-153 inter Ap·55A ~ LOC teJ STAmEHT DIlTIIlLK 22 OOG 932 83/14 03A4 83114 848A 8~t6 88 =6892 =689l =6894 =6S95 =6896 =6897 =6898 =6899 ; ; 0Y1" ; ; OVERLAY 1 10 GIVE II' OCCESS TO Ef' RAIl LOCS. 01H-7FH. !irud:E COOE FOR I'IINl-IDIITOR OYERLAYED OYER LI»I IR:lU: PROGRfII Rift OV1B11S EQU $ ; 0V181 =6988; 83A7 83A7 8lAB 83119 8JA1 ::(,981 C3 88 88 88 DIm OV1DllS+883H =6982 =6983 =6984 RET =6905 =6986; I«JP I«JP I«IP 83f1l =6987 OOG OV1BAS+887H 8:s/13 83 =6988 83RC 88 ::(;989 I\'EJ I«JP =6918 ; =6911 DIm 0V1IIfIS+889H ::(;9~ I'IOVX @Re, A EQU $·OY1BAS I'IOVX !'lOY =6913; 888f1 83AE ee 83AF AS 8388 ee 8381 rID 8383 2e 8384 All 8385 8489 8313 =6914 OV1B1 =6915 ; =6916 IIOYX fl,i'R8 RIl,A fl,tlRIl JB7 XCII !'lOY fl,R0 @RIl,A JII' 80SH EQU H~ =6926 !'lOY 1I/@R8 =6927 =6928; JPI> 889H =6917 =6918 =6919 =6928 =6921 =6922 =6923; =6924 0V1E12 OV1B2 OV1BAS =6925; , 838"/ Fe 8388 IH89 =6929 8816 =6932~ SlZECII( SIZE 5£T 22 =6933+; =6934+; *~**~ =6943 $EJECT .*••--***•••*****-****-**-- All mnemonics copyrighted @ Intel Corporation 1976. 1-154 AP·55A lllC OOJ 11381) 8300 83 83BE 88 83BF 1!8 IBee 88 1l3C1 83C1 83 1l3C2 88 LINE S~ STATEMENT =6944 =6949+ =6953; =6954 ; 0112·=6955 ; =6956; =6957 0V2BAS =6958 ORG =6959 . DATABlK 23 ORG 954 =6969 =6961 ; =6962 ORG I«lP =6963 =6964 =6965 =6966 O\lERUlY TO RESTfJ1[ EP STATUS SAYED ON BREAK fft) ~SlI£ USER'S PROORIlII. SOURCI: CODE F~ I'IINHIONITOR OYERlA'l'ED OVER lOW OODI:R PROGr9 8300 83 931>9 F5 9300 9400 LINE SOJ:CE STATlI£NT 7995 ; 79116 COOEBLK 11 7946+ ORG 977 7959 Xl'TEST: (R P2, 100II 7951 IN A,P2 7952 fH. f'2, I(NOT 7953 7954 7955 7956 JB7 RLT SEL JII' O~) $+3 I1B1 S89H 7957 SIZECHK 7969+ SIZE SET 11 7961+; 79621·; _*************************** _ _**_*_*_ 93DC 28432931 9lE9 39373929 93[4 494[5445 93£8 4C 931)(; 9199 I&"D 9199 119E9 99fl) 99Ft 9IlFF 9IIFD 7971 ; 7972 7112+ 7116 COOEIILK 13 ~ 00 98{) '(C)1979 INlli' 7117 SIZEQI( 7129+ mE ~ 13 7121+; 7122+; -*******",*****'I"*******-*-~-*******-****** 7131; ?i32; 7133 R'"~ 7ilS-. ; CVTES USED 00 POOE II PGSIZE SET ORGPG9-999I1 ; 8YlE!; USE!) 00 PflGf: 1 71364 PGSI2E SET 0RGI'G1-100H 7137+ ; BWES lJ'..ED 00 PfIGE 2 PGSIZE SET ORGPG2-299I1 7138+ ; BYTB USED 00 PAGE 3 PGSIZE SET ORG'G3- 390H ; BYTES lJ'..E) 00 PAGE 4 7139+ PGSlZE SET 1I!Gf'G4-49IlI1 ; BYl E5 USED ON PAGE S 7149+ PGSlZE SET OOG'GS-599H ; BYTES USE!) 00 PffiE 6 7141+ PGSlZE SET ORGPG6-69011 ; BYTES Us£:() ON PAGE 7 7142+ PGSIZI:: SET ORGPG7·-79j,Jf 7143+$[JECT All mnemonics copyrighted @ Intel Corporation 1976. 1-156 infef LOC OOJ Ap·55A ~ ~IATEl£NT LIIE 7145 i-'.**-**-******----7146 i FILL fl.L lHJSEI) I£IG:\' LOCArHJI5 lin H I«J' IWCOO£S 7147 i 7148 ; ;******---*--*-**-- 81FD 81FD 99 81FE 99 81FF 99 83E9 83£9 83EA 83EB 8lEC 93ED 99 99 99 99 99 Ir~ 99 83EF 99 83f"9 89 83F1 89 93F299 93F3 89 93F4 89 83F5 89 93F6 89 93f"7 99 931'8 89 1l3F9 99 93f"A 99 93FB 99 83FC 99 93FD 99 93FE 99 93FF 99 94FD 94FD 89 84FE 99 94FF 99 95FF 7149 7158 ; 7151 $GEN Will; 7168 7161 i'162 7163 7164+ 7165+ 7166+ 7168 ; 7175 ; 7177 i>178 7179 7188 7181+ 7182" 7183+ 7184+ 7185" 7186·. 7187·' 7183·: 7189+ 7190i 7191+ 7192+ 7193+ 7194+ 7195+ 7196+ 7197+ 7198+ 7199+ 7289+ 7291~ 7292i' 7293+ 7295 i 7297 7298 7299 7219 7211+ 7212+ 7213+ 7215 ; 7217 721B ~ IRGPG1 REPT (2Il00 - 0RGI'G1) DB 8 EN>!! DB 8 DB If DB 8 ORO 0RGf'G3 REPT (499H - 1m'(3) DB 8 EN>II 00 0 DB 8 DB 0 00 8 DB 9 DB 8 00 8 DB 9' DB DB 8 8 DB DB 8 00 8 DB DB 9 DB 8 00 9 DB 9 DB DB 8 9 00 00 9 9 00 " " " ORG (l1Gf'G4 REPT (599H - ORGPG4) 9 00 ENDII 8 DB 9 DB 9 DB ORG ~ REPT (6911-1 - ORGPGS) All mnemonics copyrighted @ Intel Corporalion 1976. 1-157 intJ Ap·55A LOC OOJ LINE !i()lgE EtI)II 05FF 00 .7219 7220 7221+ 00 DB STRTEl'ENT 8 8 7223 ; 06FF 861'"F 00 87FD 87FD 00 87FE 00 87FF 00 722S 722G 7227 7228 7229t 7231 ; 7233 7234 7235 7236 7237+ ORG IRGPGG REPT (70IIl - ~) D8 8 EtI)II 00 8 ORG 1:m'G7 REPT (SIl0H - 0RGfG7) D8 II EtI)II 00 7238+ DB 7239+ 7241 ; 7242 $EJECT 00 8 8 8 All mnemonics copyrighted @ Intel Corporation 1976. 1-158 intel' LFILL LfILL1 LPGSEL LSTBR1 LSTBR2 LSTBRK LSTDn LSlINT LSTORE LSTPII LSTR8 LSTREG LSTTBL 110 46721 4674 4832 5113 !l115 4978 4975 4977 2459 4974 ~ 4976 4971 551. If1 5521 IR)[) 4301 /R.IOC 4351 I1AIN 1434 1fl1N2 15441 'fllm 1594 MIll! 16724 111111)0 1798 IIIINli 18311 111111:1 17161 I'IfIIIt> 1741 IflIIll1 1742 PIfH. 449. IIlI.OCK 165. 471. II>EC It)JNZ 4751 1011 11581 I£It.O 11491 t1ERro1 1592 4611 "III: 1IL01 67341 IftlV 39St 2464 3802 3519 4639 5191 6859 IIOOO.JT S".$7I 445. 11m. II'USEL 553. ItRL 482. 4941 I'tRLC I'RR 4861 ItRRC 11XCI' I'IXRI.. II:OLS IEG1 NEXTPl NIBB NIllIN NIBIN2 AP·55A 4676 4677. 4890 5032 5111 5162. 51161 5117. 4979 5111. 4995 5911 5032. 50981 2615 3!l27 4981. 59551 5037. 49741 46n 4957. 1816 2386 5:>l14 15391 1546 3129 1609. 1674 18301 1847 1762 10011 17661 2438 5358 2349 2414 2417 1387 J529 4041 3824 3851 1reat 1743 6748 1558 2482 3063 :s557 4759 J343 C978 3841 1315 1m 4320 4005 4456 4566 5%9 4020 4655 2011 2875 1574 2541 3091 3578 4783 5369 6152 6599 3631 1609 2581 3206 3801 4798 5455 1628 2714 3225 4548 5592 5678 2259 5000 (988 4981 4437 455. 450. 6141 5591 729t 2341 1203. 2253 3792 370Bl1 3627 3638 3553 37991 6223 3820 4814 5541 6299. 2422 2427 2500 2620 1649 2729 J,44 3855 4836 5575 1682 2756 3263 3957 4354 :'1591 1716 2787 3283 3981 1766 28115 3301 39% 1782 2838 3322 4811 4870 4957 5655 !l673 5969 5974 5619 51"(8 5886 :s699. All mnemonics copyrighled @ Inlel Corporation 1976. 1-159 4~1 1881 21156 J349 4965 4996 5687 1976 2893 3423 4257 5912 ~793 1994 2923 3433 4284 5937 5721 2172 2938 3452 4392 5955 5802 2248 2953 3471 4419 5999 51)('5 ;m9 296lJ :S499 4587 :'116<1 :'1951 inter NIfj() AP·55A 4159 1521. IlMl.S 1381. IIm'TS 12381 IIK:OO 11851 ~TlOC 55921 IFTIII1 1991 IFTf112 1997 IFTOO3 1992 IFTI(Jf 11941 (l((lI'G0 1281 2652 4368 6833 ORGPGl 1291 3691 4239 6938 (JiGPG2 1391 4585 6121 0RGPG3 131. 6768 7119 0RGPG4 132. 52201 6628 (J\'(J'(l5 133. 54891 7928 0RIf'G6 1341 5935 ~G7 1351 6366 7233 OOTClR 1624 00TI1SG 1797 OUTUTL 1542 0Y8BAS 3187 0Y1B1 6898 0Y1B2 6919 4161 1928 1416 5564 1662 0Y1BRS 1426 0Y2B1 6981 0Y2SAS 2921 3281 6451 69841 6957. 6958 OY3B1 0Y38AS 0Yrllr 0VUJAD OYSIZE 0YSW1 IJY<'JIJ' 6G62I , /QlRI( 6868 3<:113 13191 1427 6461 66611 2985 15181 Pl>IGIT 5171 Pm< ~1S59 PGmE 71351 PINPUT 5291 PlUS1 6991 43001 5584 lS:ro 5684 2181 2469 2475 2723 5646 1903 1908 1999 1641 1488 26741 4495 6111 1952 3739t 4365 6116 2377 4639 6195 1334 6769 71391 2694 S"J24 6791 3168 5434 7994 3946 68291 4947 6367 19741 1827 1973. 6783. 6914. 6924. 1984 19251 1927. 1698 1491 2679 4628 6185 1!153 3740 4588 6198 2378 4631 J 1791 14491 3148 4695 6259 1819 1528 .3399 1873. 361S 4696 47201 4724 6336 6482 6477 21531 2239 2240 22'J6I 3741 37651 3776 3926 4625 4i'29 49'.12 !l143 6264 6341 6407 64S2 25141 2528 2529 2647. 4691. 4734 4927 5148 6346 6412 6487 (;552 ~9 .1335 13951 1877 1~78 1943. 68231 6827 682S 6885 7138 7176 7177 2695 31441 3161 3786 3936 5429 5776 5855 5924 6848 7923 7889 7139 7296 7287 3169 33981 3791 3792 39161 5781 5869 5861 59051 592';/ 7140 7216 . 7217 3947 41921 4529 4~ 46151 6136 6219 6284 6361 6427 4948 51341 5444 :>445 ~757' 63981 6432 6433 64711 6597 1529 3617 6SS1. 1947 36S1. 4917 6542 2305 4111 5239 6547 2689 5274 6623 6577 6886 2157 3685 5138 6613 2386 4112 4249 6849 4259 4)551 4375 6197. 6126 628Il 3941 6131 4389 6295 4749 6592 6141 6508 4159 6567 6142 6537. 6914 6924 4812 ~9 2158 3735 ~ 6686 2363. 4137. 5231 ~2601 6618 3158 5275 6696 6578 69;421 66!11 3499 53951 7918 668SI 6946 2239t 2234 3771 3921 ~64 5389 7898 7974 2372 2523 4146 4147 5269 5314 i'9B 7979 3419 36131 5319 !l424 7984 1'137 6648 6649 6947 7993. 2399 41116 5414 7135 2684 41761 2993 6793 3124 6887 3185 68%1 6991 6987 6911 6962 6968 6972 6984 6845 6657 3204 2921 6851 6855 G!lG2 !l926 3188 1426 3282 31S7 6452 6731. 3293 3281 3186 6657. 2713 67B8 23181 2633 3089 3599 3716 6455 7137. 71381 11391 71481 71411 7142. All mnemonics copyrighted @ Intel Corporation 1976. 1-160 . -:1651 4234 ~761 ;>1~ i'1~3 3404 i'136 3781 3153 4185 5766 (159 3931 ~7?1 ~ ~919 4379 690 7169 1179 6722 67551 ~19 66821 6721 7943 t'944 4186 5&45 716i1 4244 ~ge'J 3698 4213. ~914 78781 7199 ~153 ,~154 6492 6~7 4937 !l~ &S62 66:S3 !l339 6796 45111 6274 4739 6351 4932 lA17 4381 6279 4491. 4515 6356 6422 4(44 6497 4913. 6638 61!l81 6572 4942 6/11 6215 6643 5439 1933 6216 6716 !l7s6 ~787 7899 7141 62551 6289 7938 i'1f14 6451 66!l7 6651) 6731 1975. 2326 6784 2367 4141 2518 4189 5848 2556 684111 6841 4828 2922 D21 6667 2995 1924 5489 2212 71361 5481 2476 1S8!I 1906 19221 !l8361 5934 7224 6299 '(142 7225 6Il9I 7232 inter ,PlUSl PRNT1 PRNT2 PSEGHI PSE!l.O RDELAY RECDOO RECTYI' 7141 2899 19941 5181 51.9t 12481 3524 12751 REGC 1293. REIJ/G 191. 2524 3686 4112 4586 4928 5320 5841 6117 6275 6428 6578 6722 7999 RERROR 2317. RINT 15291 ROTCNl ROTPflT C65I RSlm: 2761 SCf1N3 5557 SCANS 5532 SCANS 5672 SEGPW 13111 SING 1523. SIZE 1385. 886. 25Il4I 37551 46951 SIZECH Sl'lflfI S/IILO STRCOII STRGOC STRtIEII STRTIf' STROll STSIM: TCRlFO TIINT TIRET1 TOFPOI.. 53991 63201 68711 2791 3717 5292 6819 1122. 11131 5995 1623 1927 1922 1257. 1973 3956 3886 54541 5647 3846 AP·55A 2268 20391 2029 1414 1413 56% 35491 3583 4485 1335 ~ 3691 4142 4511 4933 5325 5846 6122 6289 6433 6614 6769 7995 2348 1923 5501 5482 7133 5476 5477 5716 5491 5439 (:072 5818 5819 6007 3587 4442 1401 2652 3736 4147 4516 4938 5339 5!l51 6127 6285 6478 6619 6C2S 7199 .6132 629Il 6483 6624 6886 7195 4186 4621 4948 5429 5861 6137 6337 C488 6629 6947 7119 5646 5507 5514 5529 5699 564411 587f1 5965 1442 2649 3909 4684 5759 6391 6935 1868 1863. 26641 40921 47101 5826. 6461. 69931 1930 4124 5892 7957 34f.>5 2557 5209 4553 1529 2688 3741 4181 4521 4943 5415 5856 4596 1878 2685 3m 1948 2699 3777 4235 4626 5139 5425 5919 6142 6342 6493 6634 i'OO9 1S53 2695 3782 4240 4631 5144 5439 5915 2240 3159 3922 4361 4(39 52'.16 5445 5939 6291 6362 6543 6687 7929 2M 3164 3927 4366 4n5 .:>231 :>762 5935 629C 6367 6548 6692 7934 2146 :na3 4169 5127 22291 360311 4293. 52101 69971 66721 C1SG 2158 3149 3787 4245 4696 5149 5435 5929 6191 6347 6498 6639 7914 6583 6644 ?919 3154 3792 4258 4,('25 5154 5449 5925 6196 6357 6588 6649 7924 1936 3m 4139 4986 5898 2143. 33801 41661 51241 68191 6530 6598. 6681 7963 2283 4342 6167 71291 2359 4478 6242 7123 2591 4602 6317 4m 4999 2889 5184 3314 5J78 2869 5282 5352 6232 6352 2235 2396 3169 3932 4371 4740 5265 576., (:034 6211 6403 6553 6697 7939 2368 3480 3937 4376 4(4:> 5279 57(2 6839 6216 6400 6553 67112 7944 2m 3495 3942 4381 4759 :>275 57n 6844 6268 64B 6563 6'(07 ?975 23,8 3419 3947 4496 491a 5319 5782 6949 62C5 641!l 6568 6712 1900 2519 3618 41117 4S81 4923 5315 578'( 6112 6279 6423 6573 6717 1'885 55751 5566 5589 5682. 2213 5486 1928 1388 14394 2507 2637. 3758 39061 4688 4681. 5402 5747. 6323 638S1 6874 6932. 1302 1436 3752 3993 5396 5744 686S 6929 2487 2493 1671 1fJ:S1 5021 5946 29371 2954lI 1..'125 294711 1989 2003 2932. 3962 3183. 3894 3975 5742 5791 5721. 5742. 5881 4989 5823 6999 2772 24811 5099 1866 26(," 4995 4713 5829 6464 6996 2149 4163 6816 7117 3817 2745 5238 1S33. :s1341 4127. 4903. 58951 6527. 7060t 2217 4200 6994 2555 2916 41191 6077 All mnemonics copyrighted © Intel C?rporation 1976. 1-161 611'.!2 3341 6398 C675 22861 2209 36711 3674 43451 4348 52501 5253 61791 6173 67451 6748 2353. :f?291 4481t :>2951 6245. 68131 3131 4900 6524 3377 5121 3689 6385 2661 4791 6458 6595 6669 366S 5247 6742 34\14 3844 4ll0i' 4023 4845 4879 2634 4C78 2223 3686 4286 5213 6100 5297 2356 3723 4484 529\1 6248 6816 inter Ap·55A TTYOOT 5J9I 4428 lYPE lJ'Dfi)1 If'IlOOR YERSI«) \oI!RK 11>151' 1I>1SP1 lIPCOOE Xf'TEST ~RO 11761 22G5I 2195 185111 1'5221 2819 5988 8m 1411 6841 4439 1429 1579 2558 1371 22481 1928 2939 59911 1419 1549 1579 1585 1748 1771' 1777 2269 22i'4 2569 3m 59481 1519 2119 1586 2118 5889 1778 5799 5959 2494 5949 6151 3428 61!!9 (9591 3869 5667 1822 CRO!>S IlEFEROCE CM'LETE All mnemonics copyrighted @ Intel Corporation '1976. 1-162 2448 255IJ 3811 3872 4i'6a 4966 5171 intel' BRKFIL 2433 ~ 24594 ElfCNT 12661 BlflEN 6621 B\'TE11 ~"54 B\'1EIN 3432 INTEO 3995 eGO 29S6 CGIHI 3819 CGmIT 3822 CGOSS 3821 CGOTRR 3823 CGOIIB 31128 CllARCR 3393. CHARIN 3417 CHff!l.F 3394. CIm«l ~geI CIiARO CHSPIU 2273 DSPIIID 22771 DSPTI" 1841. DSPllf' 8281 DSS 2957 DTR 2859 DWBRK 2856 ELSIF1 2186 ELSIF2 2284 E.'l'mI 11481 Elft.O 1131. ENlJlNI( 5291 EIfJRAII 5281 EN)f'1 3SIl8I ENDFIL 3872 EIIlREC 48641 EorREC 3887 EPOCC 9691 I:PIlRK 1425 EreNT 29211 EPCON1 2785 EPCONT 2728 EPFET 3319 EPPASS 2937 EPPCHI 19141 EPPClO 111851 6877' AP·55A 5S4 869 1872 1216 5291. 689 8911 1881 1225 616 911 1896 1234 632 932 1899 1243 2'.!Il1 2328 3219 6450 3125 3374 6456 4!l52 2967 2914 2S21 62231 29S2 3285 3362 :mo 3335 648 1252 678 97J 1117 1261 2564 2566 59421 4384 5184 964 1188 6SS 932 789 991 m 1126 1135 715 111011 1144 1278 1279 12!18 1989 1153 1297 :s262 6237 6239 6248 756 1918 11G2 m 1112" W1 1188 824 1854 1189 ·1198 6315 6378. 7911 1816 8117 1845 4216 52S2I 68591 6092 20631 28961 2894. 59961 21081 2124. mal 2092. 2129. 3595. 2135. 21281 21141 21881 21821 211111 29781 21941 29781 2279 22761 22891 22791 3375 3199 5948 2133. 2137. 2131. 2188 2297 5398 5364 3197 3197 3893 3tlS4I 5967 22112. 22m 6381 6388 3991. 2977 3183 3187 2tl85I 2783. 3343 2'J52 2779 2752 65891 3224 3243 All mnel!1onics copyrighted © Intel Corporation 1976. 1-164 6298 6314 inter EPPSW EPRIl rna 9781 9961 3042 311& 536. 2424 3il461 EmT EPRSET EPI\'IJN EI'M1 EPRUN2 3il5il ~3 3049 EF'RIJM 3929 EPWl5 3057 EPRUN6 3081 EPSSTP EPSTE1 EPSTE2 EI'STEP El'STOR EPTIIfR ERROR ERROR2 EXIlI0 EXAIf1 EXA1!2 AP·55A 2888 2932 6445 3122 1433 2,12' 2847 2992 3276 4863 6519. 3129. 29S4 29".-6 ~7 325( 3292 5884 6449 6453 3951 3962. 3856. 3931 3039. 3115. 3982 31191 532. 6447. 6447 29r.4 21174 987. 741) 2324 2541. 2681 2619 EXAIt3 2624 EXAIM 2629 EXAtIS 2619 EXfIIIN 2419 EXPIIOO 555. rDllt'1 3978 ~D111'2 4926 FWf>34035 fllUllP4 4064 F'DUII'5 4034 Fltro-' 15981 GOTBL 3916 H 13il21 l1li>1 4317 HBl>2 43181 fIlDlR\' 42571 IflITHI 19321 IIlITLO 1923. II>flTIN 35191 1£XRSC41931 I£XBtf 1327. HEXNIB 4195 IFOONE 3885 HFlLEO 2413 ~CIN 2416 HRECO 3877 6448 645Gt 3194 2920 2962 765 23491 2616 26181 2622. 2627. 2632. 26131 25401 319B 3349 :mB 782 63&2 64451 3369 5053 6297. m 816 B33 2626 2631 4535 4537 4538 3956 4033 lJ61 882 39961 40301 49381 4888. 49361 1699 3il19. 4289 4325 431S1 4319 4339 4433 4434 4273 4399 3547 4388 ~4 38~ 41981 3898 38941 2421 38il1. 3878 3417. 342'l 3592 3BB4 39551 tl!EGA 19591 II!EGB 19681 HREGC 19771 Ift:OO 111861 Ift:GE 111951 IREGf 11941 1I1PlEl1 1855 INCSIIA 1431 23&5. 2625 3S2S 3673 4675 523111 All mnemonics copyrighted © Intel Corporation 1976. 1-165 993 924 945 AP·55A INeN INCW1 INIT INITLP IIf'fI>1 Ill'ADR Itf'KEV INYfl.S ITII' 52391 5241 14891 14131 2187. 1035 1543 1346. ml 1832 JOOlES 2408 Jltl'TBL.2385 JlorIL 2492 JTOOO 2491 JH1LST 2403 JTOItOO 2400 JTIH:C 2404 JTIH:L 2405 KIlDBlf 12121 KOOI1 51)011 KBOIN 2650 KllOPtt 3847 KCLRB 1515. KEY 7691 2C59 KEYCLR 15051 KEYI)I1 15041 ID'EtIl 15811 KEI'FIL 14991 KEYFLG 9491 KEI'60 1512. KEI'lOC 1.<"211 KEI'lSl" 15101 KEI'!IOD 15m KEI'NX1 15891 Kl:I'f"AT 1583. KEI'PI1 15881 KEI'REC 15861 KEI'RE(j 15891 KEI'RI:.L 15821 KEI'TRA 1587. KGORES 151~1 K$ETB 15141 LASTKI' 987. LDflTA 7521 3321 41611 LDBVTE 3867. LFllJR1 4897 LFESRK LFEDPI LFEINT LFIJ'I1 LFER9 LrEREG LmBL LFETCH 4700 4m 4779 4776 4851 4778 4773 2561 !;2461 14~3 2190 21701 1675 1381 1557 1333 24291 23991 2426. 2424. 24191 2413. 24121 2416. 2334 5816 57991 3106 1908 1544 2783 2323 1923 1545 1983 5533 1902 5558 2498 1828 1417 1590 1837 1846 2196 2345 2463 2588 2658t 3115 3119 1595 1597 1625 1626 1Mb 1647 1,85 1712 1715 1725 1732 1761 1838 'S6J~ 5811 6161 1593 3116 2628 1926 1844 1749 3129 1843 21C7 2292 2205 2322 2346 2468, 259tl 2597 2613 2622 2627 2206 2347 2461 2618 3117 5671 568"2 5644 5660 5666 2'203 2623 2784 3121 1929 1923 1905 1m 5626 231;' Il67 4795 56::;3 232;' 2436 2562 :S629 5878 2565 :s641 5106 2697 364B Sill 2614 2828 2835 3868 2919 3088 4157 2349 6150' 1~ 1901 1923 1906 1929 1909 1997 5555 1B58 3:S44 4662 555G ;''211 3346 4669 :nre 5928 !;6;'l) 2432 3526 5lI:n :i598 50i'1 3876 489911 4/81 4890# 4797 4813 4832. 48701 4783. 48541 483611 4776. 3B67 4(04' All mnemonics copyrighted @ Intel Corporation 1976. 1-166 3C69 6297 2632 :s666 6454 3715 4154 intJ pciGlO 898C ROTCNT 9983 SIZE 801M) smJTL 9919 lI'M)1 917C ZERO 9999 Ap·55A RDElA\' ROlPAT SIZECII STSfIYE 993F Il982 9911 Il59II l.IPOfIlR 9178 fISSEIIJI. V CO'flL TE, I«) All mnemonics copyrighted @ RECOON r6 4859 2943 :B19 3631' 4875 ~ 5546 6228 6]04 3562 3392 3583 2388 3l1li7 2444 :s868 3358 4891 *7 5692 5728 4419 4459 7711 ;'00 Il8SI 991 4469 4569 7GB. m 9991 9'& 4579 3051 814 !l22' 9391 943 951. 831 8391 1561 ;:387 1561 2439 1567 2909 1610 3632 1616 5179 2390 5359 5385 3444 3511 3517 3532 3542 :>')62 3968 J982 3!188 4044 4954 3426 586 659 71? . 3426 599 654 721 3558 3564 681 671 4217 3571 602 672 421B 35"71 3&58 619 689 4226 3858 J858 4966 617 686 618 687 622 6~ 4972 626 695 3327 3333 2939 2945 5082 3249 3255 32B4 :Q9Il 1745 2762 3997 3504 4297 4876 5461 6229 2749 3481 li'OC 2769 3212 3634 4322 4963 1897 IB19 2793 . 2811 ~231 3259 3638 3897 4398 4439 4987 51192 5547 ~581 19a2 2818 3269 3814 4458 2999 5465 495J 5691 2776 3811 5629 4332 4449 585. 594 658 725 696 676 4222 4979 633 791 4979 634 792 2lI13 2862 3387 3841 4568 5961 5623 2178 2817 3328 :rJ55 ~963 39&7 638 796 3998 2975 3211 . 3:l17 2m 2912 3354 3369 2759 2896 2814 21.19 2798 . 2CJ9 2845 2894 2939 3268 3274 4S55 2969 3238 3236 1634 1655 1600 1695 2547 2587 2729 2735 2944 2959 2974 :sooa 3477 3496 3516 3531 4943 4871 4263 4279 4739 4894 4820 -4842 5197 5349 5361 5375 5!r.>7 5971 6965 69C4 1659 1692 1792 1986 3311 :J332 3359 3443 4492 4649 4659 5965 2923 2452 2887 3541 2990 4861 1722 2742 3069 3563 4299 4869 5387 6153 2739 3462 59S1 3651 !J969 All mnemonics copyrighted © Intel Corporation 1976. 1-168 5594 5918 5597 2!;44 32t'9 3834 4559 5943 5616 4593 5968 ~93 2:ss9 2899 4645 ::i996 570SI 6395 2766 3599 2797 3821 5636 4468 2815 3838 57B 45611 2a25 3848 6969 4578 2866 3967 3216 5520 5981 4267 3235 4277 inter AP.·55A ?H~"4 356. ?f0Rlf> 3801 2466 3994 3512 4641 5193 6961 ?H 1298. ?HBITH 1928. ?HBITl 1919. ?HEXEU 13241 ~GA 19551 ?lIREGB 18641 1569 2484 3559 4761 1516 2543 3993 3580 4735 ~345 ~371 6009 4262 4258 4285 6154 4273 4266 4~3 386S 1611 2583 3200 3803 4S8tJ 5457 6225 4323 42/1 4298 1&39 1(,51 lW4 2?1C 2731 27~ 3227 3339 4816 3246 3857 3265 1I1B 2789 3285 3959 3983 m8 483B 4S56 ~3 5577 ~593 4872 5612 4959 5C!l7 1717 1723 5637 1739 5893 1730 5664 !:i676 ~76 3639 3646 1(68 18jj3 1978 285(; 2~ 49V3 j351 4067 499S ~i'5 ~'9 ~ 6153 6159 5676 3646 s652 $658 19461 3147• 41491 4916. 59001 2146 3383 4169 339StI 3606 ~7 ~393· 1784 2840 3324 4013 3425 4259 5814 5795 1996 2925 3435 4286 5039 5723 2174 2948 3454 4394 5&57 :i894 ~ 4644 4669 2258 295S 3473 4412 5992 2331 2979 :S492 4:,&9 ~77 5953 4667 4667 ~1(.4 6391 433] ?HRI:OC lBnl ?HREGD ?IMGE ?fRtiF ?ITI'IP ?KEDEU 10021 19911 11991 (741 1687 12981 2I~2 ?KEY 757. 2582 ?KEYFL 933. ?KEVLO 1217. 5542 ?LASTK 8911 :J611 ?L1>ATR 7491 2819 5956 5Il64 ?LOOT 1333. 1383 . 23661 2587 37341 3758 44944 4698 53001 5402 6258. 6323 68261 6874 ?1'IIJ1l1 11541 3896 ~It.O 11451 J8I~ ?I'IINDX 156. 967 1912 19161 1961. 1061 1196 1111 1156 11691 1295. 1295 1258 1255 1390 1394# ?MSRVE 158. 587 851 872 1966 1975 1219 1219 ?NCOL5 6911 ?NEGl l16. 2338 ?NEXTP 11991 2251 ?Nr951. 42541 471101 :k?351 5791. 61461 64371 61261 69511 1861 2204 2662 3669 4090 4343 47118 5248 5824 6168 6459 6743 6991 1861 1869 2292 267Il 3677 4Il9S 4351 4716 1939 5832 6176 6467 6751 6999 1SS21 1931 231111 2351 26991 3132 36951 mB 41161 4125 43851 4479 4754. 49111 52791 5293 58651 5893 62201 6243 65121 G525 6m. 6811 78481 7Il58 1931 2351 6670 6939 1445 2226 2643 S609 3912 4209 4687 5216 5753 6103 6394 66706938 6811 i'058 5991 6251 6533 6819 i'966 2801 1583 3979 3539 21114 1746 4769 41142 2024 1756 4766 4321 1769 4958 4438 1769 4964 4451 1769 1775 5169 4567 1829 2448 2446 2453 2542 5503 ~97f1 1767 2483 3424 3856 56:l6 5730 37151 4421 44(,1 1569 1598 4529 1616 2m 1938 1119 1182 1254 741 839 C5Il 934 5694 35Il1 4493 4821 5J58 1383 2141 2582 3378 3753 4164 4603 5122 5397 61117 631B 6596 6604 6869 6Il?7 7118 7126 1987 1995 1577 1~77 3IlIl9 ' 3Il64 2012 2876 1575 1f11l1 1973 1145 1217 (74 993 1065 1137 1209 1281 7i'5 071 875 879 61164 6879 6979 aIC5 4551 4561 .45!J8 4594 5527 623 700 5527 627 797 639 814 2218 4281 6Il95 2491 2141 4164 61117 7118 2757 2861 4S43 6239 141151 21621 2533. 34141 37961 41991 46351 51591 54491 68531 63711 66531 699IlI 1263 757 611 763 4227 iIl58 983 1955 1127 1199 1271 758 934 1956 121l1l 1272 762 128Il 879 1128 l6II1 39Il4 4201 4679 5208 5745 6995 (;386 12tI8 4571 2590. All mnemonics copyrighted © Intel Corporation t976, 1-170 ~163 454~ 2284 2662 3669 4Il90 4343 4700 5248 5824 6168 6459 6(43 6991 11119 1982 1154 1226 1298 5256 sae 11119 1991 1163 1235 111211 11192 1164 1236 1928 111l1l 1172 1244 8Il8 8Il9 S13 JD2 3718 4125 4479 49111 !:i2S3 5893 6243 6525 91B 2359 3140 3726 4133 4487 4999 ~301 inter LOC OOJ Ap·55A LINE 7243 USEk S~'lW..S ?II IlOO4 ?IlIlR6 9997 '!B1R7 898f) ?CQ6T 9983 ?EJ'F'CH 8992 ?FOOM4 9Il1C ?HF:EOC 09Il2 ?KEYLO IlOO2 ?t«:Ol.S 8003 ?PUJS1 9993 ?REOC IlI!82 ?START 930C fl<".1lVE 993E IlRKNXT 9234 CGCfAT 9476 CHIlRO 958D 9649 CIN CNTTBL 94A1 ~9461 DEtfN( DECSII1 OOR I>PI\'I'IEft DSPIU DWBRf( EII)fIL EPrET EPRSET EPSSTP EXAIIl FDlIIP2 1IID2 ffl>ONE HREGE INPADl 95F5 92rF 8150 8151' !l1SE 9160 9596 9787 8919 9994 9270 8C28 94D5 1J:lfl7 892E 9OC7 J1000 922lI KBDPOI.. 9M Kl~'GO 981E 991B 96C1 98FC 97.>4 /R)() 8924 I'IAlNe1 0075 I'Elt.O 8934 I1RL 892E NEXTPI.. 003f1 NIJ[{)N 0038 IJ1GPG2 9389 OUTUTL 9109 OY3BAS93SE F'ERRlJ: 819A KEYREG LfEBR1 LFETCH LSlINT ?ASAYE ?B8Ri' ?BCOOE ?CURD I 8992 909S SOURCE STflTEI1ENT 00 8992 8087 90e2 9922 0001 0003 ?EPPCL 8002 0002 ?F0RI15 001E 9002 ?If(EGI) 0092 ?li:[G[ 9002 ?LRSTK 0001 '!lDRTA 0909 ?lEG1 M3 ?NEXTI' 0082 ?PlUS3 8003 ?R1 9800 ?ROTCN 11091 ?ROTPA 0001 ?STRTI1 9002 ?TYPE 9992 ASCERR 81C9 El 9043 BLfCNT 9041 BlfL£:N 0019 CGOSS 9489 CGOTRA 9480 CHKERR 92f1 CHKSUI1 0895 (;KSI1OI( 921)13 ClUIR 95F1 CNTTRA 94AfI cot 95C5 C(»ISIlR 922C COI1SIZ 8903 DBPNT 9144 OORK 8915 DELm' 94F2 DECSI'IIl 9?F4 DINTRG 8169 DlST 914E DREC 9151 DREL 0154 DSFtO 0194 DSPI'I1 B192 ELSIF1 9007 ELSlf2 09£5 ENOREC 9641 EOfREC 05AE EPPflSS 9709 EPPClII 9925 EPRUN1 848A EPRUN 9489 EPSTEi 87DF EPm207F1 EXAPI2 92£:1 EXAH3 028fl rDUl'l'4 064S FDUlf'3 9C36 flBlTHI 8927 HBDlflY 94C9 HFILEO 9572 HRECIN 9297 IR:GF 1182F II'IPLEI'I 0200 1NPf:DR 9IlC9 INPKE'r' OOEC JTOLST 921Il JTImOD 029F KCLRIl 999C KE'1' 0093 rntoc 983(; KEYLST 981C KEYREL 9814 KI.'YTRfi 0919 LFEBRK 86B1 . Lr~ 11698 LfILL 92E9 LFILLl 1k"f3 LSTORE 8789 LSTPII !l79C IflDOC 8925 MAIN 8929 I'IAIND 9993 I'IAIN>l 8007 I'IERROR Il9IlC MINC 89211 I1RLC 0931 IIRR 002F NIBI3 81C2 NIBIN 9188 NXTLOC 87CS OPTAB1 933f ORGPG3 93E9 0RGI'G4 84fD 0V9ElAS 9378 OV1B1 89!lR 0VBlF 004E OYLOflD 936A PGSIZE OOFD PINPUT 999lJ All mnemonics copyrighted © Intel ?B ?BiPNT ?IlllO' ?DEBNC ?EPPSW ?H Corporati~n ?BIlf'NT eeec ?B1R2 9993 ?BITSO 9003 ?I)<".,/'n ?IlI'IR2 ?B1R3 ?BtfCN ?DSPTI1 ?EJ'TlI'I ?llBlTL 0002 e994 9982 8900 09Il2 0092 ?ITII' 0009 ?IJ'R0 ilOO2 ?IIH"iH 0082 ?I-REGF 99Il2 ?LE:t«iT 99EII) ?NREPT Il9Il2 ?lE1II1 ?tu1CO ?Rf!8 ?'"..EGIIl ?YERSN ElITSO ?R~ 0002 ?RSAVE ?I.tIAR'.' SCOOE BVTEl1 CGOIIl CI9 CLRBFr CO2 CTAB 009Il 992A 89j6 99F2 DCB 915A 94F5 9146 91C3 81S1l 003J 9929 0024 9499 970B 0293 11632 11026 8699 01F2 0389 9211 0017 DElfl'1'1 DI'IOD Dim DSPI'IID Emf-II EPACC Erf'CLO EPRUN2 EPSTEP EXIlI4 FDIJf'S HBITLO HRECO INCSl'IA INVALS JTOREC KE'lCLR 8993 ~76 0640 0000 95CB 0923 Kl ~'IIOD 981F KGORES 9Il1D LFtlNT 96AS U1lSEl. 94f1 L~TR9 872F 1'Il1N2 003~ IIIH. ge26 111.01 836F I'IRRC 8939 NIBIN2 91BA OPTAB2 9346 ORGPG5 95FF 0Y1B2 8313 OVSIZE 9817 PLUS1 0091 8002 0092 8Il89 9083 8002 9900 II~'TEIN 99F9 CHARC~ il90D 9651 Cit CMl>INT 89I3A cm 95Cf .CURD I G 0005 00flBRI( 9167 OCRROR 9131 DNOBRK 9168 DRUN 8m DSPTlII 0028 EI'1AI..O 0!l32 EPElRI( 834F EPPSW 0021 EPRUN3 9495 H'STIJI 97C3 \:XAI'IS 9275 FINDOI' 0942 HDATIN 82B9 HREGA 11021-1 INCW 91F4 lTl'1I' 99Il4 JTOREL 9216 KE'r'DI1 9916 KE'r'NXI 9912 KSETB 9Il9B LFEPI'I 11684 LSTBR1 9746 ~lREG 8726 IflINA 11052 IIllOCK 9Il82 I'IIOY 8928 I1XCH 8929 NIBO 95BB OPTAIB 8349 0RGP66 96FF OV1BAS 93A4 0VSII1 9361 PLUS3 1le93 1976. 1-171 ?88I 9913 m'PAT 9815 LASTKY 9Il94 LFER9 96A5. LSTER2 0748 ~T1BL 0796 IfllNB 8969 !'IDEe 002C I'IOOOUT 8928 MXRI. 0028 N3 1)1k 91'/5 ENDf1 959E EPCONT 941~ IOf'RET 94C7 EPRI.tl6 948R [XA119 9258 FDIJ1P1 9617 HEXNIB 9ill liREliD 082D INITLP JTOfIL KBl>IN KE YF1G m'REt; LOOYTE LFElfJL 99IlE 8222 00:2 9Il86 9818 8582 96(£ ~TDI1 11721 111 8929 I'IAINB1 9IlA9 IIEIIII OO:s5 PIPUSEl. 9Il48 Nl:.G1 HfF IfID'TS 8!l3D ORGPG1 II1FD 0UTl1SG 9194 0\I3t'1 9311 I'DIGIT 898t f'C..EGlil I!9!j() intJ AP·55A APPENDIX C COMMAND SUMMARY Program execution commands: The following is a summary of the commands implemented by the HSE-49 emulator monitor. Within each command group, tokens in each column indicate options the user has when invoking those commands. Tokens in square brackets indicate dedicated keys on the keyboard (some keys having shared functions); angle brackets enclose hex digit strings used to specify an address or data parameter. Parameters in parentheses are optional, with the effects explained above. The notation used is as follows: Program/data entry and verific;ation commands: [EXAMI [PROG MEMJ" [.) [NEXl] [DATA MEM) [PREy] [REGISTER) [.) [HWRE REG) [PROG BRK) [DATA BRK) Program/data initialization commands: [FILL) [PROG MEM)- [.) [,I [.) [DATA MEM) [REGISTER) [HWRE REG) [PROG BRK) [DATA BRK) Intellec@ development system or TTY interface commands (for transferring HEX format files): [UPLOAD) .[DNLOAD) [PROG MEM)' [,) [.) [DATA MEM) [REGISTER) [HWRE REG) [PROG BRK) [DATA BRK) [PROG MEM)' [.) [DATA MEM) [REGISTER) [HWRE REG) [PROG BRK) [DATA BRK) Formatted data dump t9 TTY or CRT: [LIST] [PROG MEM)' [,) [.) [DATA MEM) [REGISTER) [HWRE REG) [PROG BRK) [DATA BRK) [NO BREAK)' «SMA» [.) [WI BREAK) [,) [SING STp) [AUTO BRK) [AUTO STp) [GO/RSl] [NO BREAK)' [.) [WI BREAK) [SINGSTP) [AUTO BRK) [AUTO STP) Breakpoint setting and c[earing: [SET BRK) - Starting Memory Address for block command, - Ending Memory Address for block command, - LOCation for Individual accesses, - DATA byte. Asterisks (*) indicate the default condition for each command; thus that token is optional and serves to regularize the command syntax. [GO) [PROG MEMJ" «,) ... ) [.J [DATAMEMJ . [CLR BRKJ [PROG MEMJ' ([,J ... ) [.J [DATA MEM) APPENDIX 0 ERROR MESSAGES The following error message codes are used by the monitor software to report an operator or hardware error. Errors may be c[eared by pressing [CLR/PREV] or [END/.]. The format used for reporting errors is "Error- .n" where "n" is a hex digit. Operator Errors 1. IIlega[ command initiator. 2. Illegal command modifier or parameter digit. 3. Illegal terminator for Examine command. 4. Illegal attempt to c[ear Error mode. 5-9. Not used. Hardware Errors A. ASCII error - non-hex digit encountered in data field of hex f9rmat record. B. Breakpoint error. Break logic activated though breakpOints not enabled. C. Hex format record checksum error. Note - the checksum will not be verified if the first character of the checksum field is a question mark ("?") rather than a hexidecimal digit. This allows object files to be patched using the ISIS text editor without the necessity of manually recomputing the checksum value. D. Not used. E. Execution processor failed to respond to a command or parameter passed to it by the master processor. EP automatically reset. EP internal status may be lost. Program memory not affected. F. Not used. All mnemonics copyrlghted©lntel Corporation 1976. 1-172 APPLICATION NOTE Ap·91 INTEL CORPORATION ASSUMES NO RESPONSIBIlITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED. ©INTElCORPORATlON.1979 AFN.(J1364A..()1 1-173 i~ AP·91 USING THE 8049 AS AN 80 COLUMN PRINTER CONTROLLER I. INTRODUCTION This Application Note details using INTEL's 8049 microcomputer as a dot matrix printer controller. Previous INTEL Application notes, (e.g. AP-27 and AP-54) described using intelligent processors and peripherals to control single printer mechanisms. This Application note expands upon the theme established in these prior notes and extends the concept to include a complete bi-directional 80 column printer using a single line buffer. For convenience this application note is divided into six sections: 1. INTRODUCTION 2. ·PRINT MECHANISM DESCRIPTION 3. INTERFACE CIRCUITRY 4. SOFTWARE . 5. CONCLUSION 6. APPENDIX Over the last few years 80 column output devices have become· somewhat of a defacto output standard forbusiness and some data processing applications. It should be mentioned that by no means is the 80 column format a "new" standard. 80 column computer cards have been around for more than 20 years and perhaps the existence of these cards in the early days of computers is why the 80 column format is a standard today. Many CRT terminals use the 80 by N format and to complement this a number of printers use this same format. One reason, aside from those historic in nature, for the 80 column standard is that 80 columns of 12 pitch text on standard typewritten 8.5 inch by 11 inch paper completely fills up an entire line and allow ample room for margins. So, the 80 column format is an aesthetically convenient format. Printers are usually divided into either impact or nonimpact and a character or line oriented device. Impact printers actually use some type of "striker" to place ink on the paper. More often than not the ink is contained on a ribbon which is placed between the striker and the paper. ·Non-impact printers use some means· other than direct pressure to place the characters on the paper. This type of printer is very fast because there is very little mechanical motion associated with placing the characters on the paper.. However, because the paper is required to be treated with a special substance, it is not as convenient as an impact . printer. Character printers are capable of printing one character at a time. (Any standard home typewriter is in effect a character printer.) Line printers must print an 1-174 entire line at a time. Line printers are usually quite a bit faster than character printers, but they usually don't offer the print quality of character printers. In recent years, the "computer boom" has caused the price of printers to tumble markedly.. High volume production, competition, and the tremendous demand for reliable print mechanisms have all corttributed to the decrease in price. Because of their simplicity, line printer mechanisms have decreased in price faster than other mechanisms. Therefore, when high quality print is not needed, a line printer is a very attractive choice. This application note describes how to control all 80 column impact-line printer with an 8049/8039. The complete software listing is included in the appendix. The 8049 is the high-performance member of the MCS48TM microcontroller family. The Processor has all of the features of the 8048 plus twice the amount of pro-· gram and data memory· and an llMHz clock speed. For details about the 8049, please refer to the MCS-48 user's manual. II. PRINT MECHANISM DESCRIPTION The model 820 printer is available from C. .ITOH ELECTRONICS (5301 BEETHOVEN STREET, LOS ANGELES, CA 90066). This inexpensive and simple printer is ideal for applications requiring 80 columns of dot matrix alpha-numeric information. The model 820 printer is comprised of three basic sub-assemblies; the chassis or frame, the paper feed . mechanism, and the print head. The diagram in Figure 2.1 ~ves the physical dimensions of the basic print . mechanis~. The basic chassis for the printer is constructed out of four sheet metal stampings. These stampings are screwed together to form a sturdy base on which all other components of the printer are mounted. The paper feed mechanism consists of a toothed wheel, a solenoid, a tension spril)g, and a "catcher." When the solenoid is activated, the arm of the solenoid pulls against the spring and drags over the toothed wheel. When the solenoid is released, its arm is pulled by the spring, but this time the arm grabs a tooth on the wheel and pulls the wheel forward which advances the paper. A "catcher," which is merely a piece of plastic held against the toothed wheel, is added. to assure that the paper is advanced only one "tooth" position each time the solenoid is activated. The print head is comprised of seven solenoids which are mounted in a common housing. The solenoids are physically mounted in a circle, but their hammers are positioned linearly along the vertical axis. These seven vertically positioned hammers are the strikers that actually do the printing. . intJ Ap·91 ~ 649(164'8):~ 5.63 (143.0)·~ ~2~1463(117.6) ..L T _ '1 " :'.,., "" 9B8~0015 (251 0 ~ 1038 (263.6) 04) r--gL 025 (64) I fu2~. --1 Q, I ~-4 77 (121 2)~ j3) 3.32. ___ H MARGIN FOR HEAD CABLE ROUTING' --~-.1132(287.5),----------I __ ~ _ _ _ ".82 ± 0.015 (3002 ± 0.4) 1-----6.18(157.0)---- UNIT INCH (MM) DIMENSIONS IN INCH GOVERN Figure 2.1 Physical Dimensions of C. ITOH Model 820 Printer ~~~~~ ~ ~ ~.~~~ ~ ~ ~~~~rx1 Figure 2.2 "Formation" of a Character by a Dot , Matrix Printer PRINT WIRE 2 3 4 5 6 7 A motor. mounted toward the back of the print mechanism. drives a rubber toothed belt which turns a roller guide. A motor turns a guide that moves the print head from right to left and left to right. By properly timing the current flow through the solenoids while the print head is moving across the paper, char· acters can be formed. Figure 2.2 illustrates how the dot matrix printer "forms" its characters. The timing pulses for the print head mechanism are generated by an opto-electronic sensor. This sensor, located on the left side plate of the printer, informs the print controller.when to apply current to the print head mechanism. This "on-board timing wheel" assures that all characters will be properly spaced and that they will all be "in-line" in a vertical sense. The print mechanism is also equipped with two additional sensors. Th~se are the left home position sensor. located near the left front of the mechanism. and the right home position sensor, located near the right front of the print mechanism. These sensors simply tell the controller when the print head is in either the left or right home position. A complete timing chart for the printer is shown in Figure 2.3. III. INTERFACE CIRCUITRY The manual supplied with the printer recommends some specific interface circuitry. For the most part the circuitry used in this Application Note followed these suggestions. The circuitry needed to drive the print head solenoid is shown in Figure 3.1. This same 1-175 intJ AP·91 MOTOR POWER LEFT HOME FLAG ~:F -I , I 1- ~-------- 75-1(10 ms (IN CASE MOTOR OFFl ::: - ~::~-----,~----------------------------------------------~------~ DARK RIGHT HOME FLAG -.J I LIGHT -----.,;----------------------......11 I ~ 'ms._ L TO R PAINT 53BmsNOMINAl - TIMING PULSES ISCALENOTPROPORTIONALI PAPER FEED POWER OFF 1_ J1 '-------!I--------- M t t 1- "7"""--------------------------------- -I -, I 5ms(DELAYFORALlGNMENn R TO L PRINT 538msNOMINAl - --t 1- ~gM~~AI --~ J\M t ------~r------- M , -~S_-- T~"" T, T480 -I ~ 1.. 179 m$ --NOMINAl-- Tt ON -I Nb~,o;;~L r-----1 1-'S-20ms -I __________---'n I_lOoms nnFL_f1_ (PAPER SLEWINGl Figure 2.3 Timing Diagram of C. ITOH Model 820 Printer + 5V and converted to TTL levels in order to interface to the controller. This conversion is accomplished with a simple voltage comparator. Figure 3.2 'is a schematic of the sensor interface circuitry. Note that hysterisis is employed on the voltage comparators. This eliminates "false" sensing, ~ 5% S' SOLENOID Tr, A, 250633 33OQ.lIBW R2 13Q::t5°'o.5W RJ lkO,l12W o 38Z61 C G l",F l00V SN74060A EQUIVALENT 33K >"'1-.,.--0 OUTPUT Figure 3.1 Solenoid Drive Circuit (Eliminate R2 for Line Feed Solenoid) circuit is used to drive the line feed solenoid except that the current limiting resistor R2 is eliminated. This resistor is not needed because the line feed solenoid is physically much larger than the print head solenoids and can'tolerate much higher levels of current. The print head drivers are connected to an 8212 latch. The latch is interfaced to the BUS PORT on the 8049 and is enabled whenever the WR pin and the BIT 4 of PORT 1 are coincidentally low. The line feed driver is connected to PORT 1 BIT 1 of the 8049. Note that the driver is simply a Darlington transistor that is driven by an open collector TTL gate. Resistor R2 is the current limiting resistor and diode D. capacitor C. and resistor R3 are used to "dampen" the inductive spike that occurs when driving solenoid S. This circuit is repeated for each of the seven solenoids in the print head. It should be mentioned that. although the type of Darlington transistor needed to drive the print head is not critical. a collector current rating of at least 5 amps and a breakdown voltage (Vceo) of at least 100 volts is needed. Transistors that do not meet these requirements will, be damaged by the inductive kickback of the solenoids. As mentioned in Section 2. the printer provides some sensor interface signals that are derived via three opt(}electronic sensors. These signals must be amplified 56K Figure 3.2 Example of Sensor Circuit Motor control is accomplished by using a Monsanto' MCS-6200 optically-coupled TRIAC. This part is ideal in this kind of application because it provides a simple means of controlling a line-operated motor without sacrificing the isolation needed for safe and reliable operation. Figure 3.3 is a schematic of the motor driving circuit. +5 YELLOW \ soov 7 TOR rBLK/RED NEU HOT '---..--/ ,'SVAC60HZ Figure 3.3 Motor Driving Circuit 1-176 Ap·91 To interface 8049 to the outside world one 8212 latch was used. This latch was connected to the BUS PORT and is enabled by an INS or MOVX instruction coincident with BIT 4 of PORT 1 being in a logical zero state. In this configuration, the 8212 was used to hold the data until read by the 8049. The connection of the 8212 to the 8049 is shown in Figure 3.4 and the parallel port timing diagram is shown in Figure 3.5. The 8212 parallel port was connected to the LINE PRINTER OUTPUT of an INTELLEC MICROCOMPUTER DEVELOPMENT SYSTEM. C ~ 010 0" --i; Db INPUT LINE S -fa 0:01, ~ 01. 20 Db ~~ 01. 8212 gg; : DEl<> DB. DB, DB, DB. DB, De. DB, 00, Db~ 10 DO~ 1 DO. 00,14 DOa 21 OS. This routine also initializes all of the variables used by the printer. The INPUT ROUTINE reads the characters that are present in the 8212 input port and writes them into the 8049's buffer memory. The routine then checks the characters to see if a CARRIAGE RETURN (ASCII OCH) has been transmitted. If a CR is detected, the input routine automatically inserts a LINE FEED as the next character. When the input routine detects a LINE FEED, it stops reading characters and sets the direction bits and the print bit in the status register. This action evokes the OUTPUT ROUTINE. A detailed flowchart of the INPUT ROUTINE is shown in Figure 4.1. 8049 RO OS, <}-- PI. INT TO I BUSY Figure 3.4 Connection of the 8212 Input Port to the 8049 DATA ~~------------------U BUSY ACKNLG ~r-------------,~___ --'----------L-S I----VARIABLE T I M E : - - - - I Figure 3.5 Parallel Port Timing IV. SOFTWARE As mentioned in Section 2, the bulk of the timing needed to control the printer is actually generated by the printer itself. Therefore, all the software must do is harness these timing signals and turn on and off the right solenoids at the right time. To make things easy, the software needed to drive the printer is broken into four separate routines. These are: 1. INITIALIZATION ROUTINE 2. INPUT ROUTINE 3. OUTPUT ROUTINE 4. LOOKUP ROUTINE The INITIALIZATION ROUTINE turns the motor on and checks the opto-electronic sensors. If a failure is found, the routine turns off the motor and loops on itself. This insures that the print mechanism is cycled properly before characters are accepted for printing. Figure 4:1 Input Routine Flowchart 1-177 AP·91 The OUTPUT ROUTINE initializes both the input and output buffer pointers and then reads the characters from the 8049's buffer memory. After a character is read the OUTPUT ROUTINE calls the LOOKUP ROUTINE which reads the proper bit pattern to form that character. This bit pattern is then used to strobe the solenoids. After each character is printed, the OUTPUT ROUTINE calls the INPUT ROUTINE and another character is placed into the buffer memory. This type of operation guarantees that the input buffer cannot "overrun" the output buffer. A flowchart of the OUTPUT ROUTINE is shown in Figure 4.2. Initially the input buffer pointer is loaded with the ad· dress of the first location in the buffer memory. As characters are read, the input buffer pointer incre· ments and fills the buffer memory as shown in Figure 4.3(b) through 4.3(f). When a CARRIAGE RETURNLINE FEED (CRLF) is encountered the input buffer pointer and the output buffer pointer are reset back to the first location. The OUTPUT ROUTINE then reads the character from the first location in the buffer memory, increments the output buffer pointer and calls the INPUT ROUTINE, which reads another character from the parallel input port. The OUTPUT ROUTINE, reads the e,ntire buffer, inserting space codes (20H) after a CR is detected, and the input buffer pointer follo~s the output buffer pointer as they "increment" up to the buffer memory. When the OUTPUT ROUTINE has printed the last character or space, the output buffer pointer and the input buffer pointer are set to point at the last location of the buffer memory. The OUTPUT ROUTINE then reads the character from the last location of the buffer memory and proceeds to "decrement" down the buffer memory. Space codes are inserted until a CR is found. Figure 4.3(1) to 4.3(0). The input buffer pointer follows the output buffer . pointer just as in the previous case. When the last, or in this case the first character is printed, the output buffer pointer and the input buffer pointer are set to' point at the last location of the buffer memory. Now the pointers are "decrementing" down the buffer memory, but the printer is actually printing in a "normal" left to right fashion. When the last character or space is printed, the output buffer and the input buffer pointer are set to the first location of the buffer memory and printing takes place in a reverse or right to left manner. After this line is printed, the print head and both buffer pOinters are in the same position as they were initially. So, four lines must be printed before the buffer pointers and the print head complete a cycle. Each of these situations is handled separately by four different subroutines: CAS EO, CASEl, CASE2, and CASE3. IV·II. TIMING Figure '4.2 Output Routine Flowchart IV·I. HANDLING THE 1/0 BUFFER Since the C. ITOH Model 820 printer is capable of printing in both directions the 80 character buffer must be manipulated in a manner as to allow maximum input-output efficiency. This is accomplished by reversing the "direction" of the buffer memory each time the printer is printing from right to left. For simplicity, if it is assumed that the buffer is only five bytes long, Figure 4.3 can be used to help explain the buffer operation. All critical timing for the printer controller came from two basic sources; the timing sensors on the printer and the internal eight-bit timer of the 8049. The internal timer of the 8049 was used to control the length of time the solenoids, were fired (600 microseconds) and was also used as a "one-shot" to align the printer. This alignment is needed to make the "backward" printing line up vertically with the normal or forward printing. The "one-shot" is used to measure the time from the last column of the last character position until the right sensor flag is covered. 1-178 inter 4.3A Ap·91 BUFFER MEMORY INPUT BUFFER 4.38 4.3P OUTPUT BUFFER OUTPUT BUFFER 1: 1 , INPUT BUFFER 4.30 BUFFER MEMORY INPUT BUFFER 4.3R OUTPUT BUFFER BUFFER MEMORY INPUT BUFFER 4.30 4.3E , BUFFER MEMORY A 1 I Ic INPUT BUFFER 4.35 1 INPUT BUFFER 4.3T BUFFER MEMORY 4.3F 4.3G 4.3H 4.31 4.3J 4.3K 4.3L 4.3M INPUT BUFFER 4.3U OUTPUT BUFFER BUFr:ER MEMORY BUFFER MEMORY INPUT BUFFER INPUT BUFFER 4.3V OUTPUT BUFFER OUTPUT BUFFER BUFFER MEMORY BUFFER MEMORY INPUT BUFFER INPUT BUFFER 4.3W OUTPUT BUFFER OUTPUT BUFFER BUFFER MEMORY BUFFER MEMORY INPUT BUFFER INPUT BUFFER 4.3X OUTPUT BUFFER OUTPUT BUFFER BUFFER MEMORY BUFFER MEMORY INPUT BUFFER INPUT BUFFER 4.3Y OUTPUT BUFFER OUTPUT BUFFER BUFFER MEMORY BUFFER MEMORY INPUT BUFFER INPUT BUFFER 4.3Z OUTPUT BUFFER OUTPUT BUFFER BUFFER MEMORY BUFFER MEMORY INPUT BUFFER INPUT BUFFER 4.3AA OUTPUT BUFFER OUTPUT BUFFER BUFFER MEMORY BUFFER MEMORY INPUT BUFFER INPUT BUFFER 4.388 OUTPUT BUFFER INPUT BUFFER 4.30 OUTPUT BUFFER BUFFER MEMORY 1 OUTPUT BUFFER BUFFER MEMORY 4~3N OUTPUT BUFFER BUFFER MEMORY B OUTPUT BUFFER INPUT BUFFER OUTPUT BUFFER BUFFER MEMORy OUTPUT BUFFER INPUT BUFFER OUTPUT BUFFER BUFFER MEMORY 1 INPUT BUFFER 4.3C OUTPUT BUFFER· BUFFER MEMORY I IJ OUTPUT BUFFER BUFFER MEMORY 1 INPUT BUFFER 4.3CC OUTPUT BUFFER OUTPUT BUFFER BUFFER MEMORY BUFFER MEMORY INPUT BUFFER INPUT BUFFER 4.300 OUTPUT BUFFER OUTPUT BUFFER BUFFER MEMORY BUFFER MEMORY INPUT BUFFER INPUT BUFFER Figure 4.3 1/0 8uffer Handler 1-179 a AP·91 When the print head reverses direction and the right sensor flag is uncovered. the timer is then used to determine where to start printing in the reverse direction. The timer and the print wheel on the printer are used to determine when to place a character. The strobe from the print wheel informs the 8049 when to fire the solenoids and the timer allows the proper spacing between the characters . . V. CONCLUSION Although the full speed of the 8049 was not used in this application. the high speed of the 8049 makes it possible to "fine·tune" any critical timing parameters. Additionally. the extra available CPU time could be used to add an interrupt driven keyboard and display. such as the ones discussed in AP-40. to the printer. This would allow the printer to function as a complete "terminal". Very little attempt was made to optimize the software. but still the entire program fits easily in 1.25K of memory; 750 bytes for printer control and 500 bytes for character lookup. Adding lower case to the printer would require an additional 500 bytes of lookup table. ·The remaining 250 bytes should be used to add "user" features such as tabs. double width printing. etc. The high speed of the 8049 combined with its hardware and software architecture make it an ideal choice for controlling an 80 column. bi-directionalline printer. The 1/0 structure of the 8049 minimizes the amount of external hardware needed to control the printer and the large amount of on-board program and data memory allow quite a sophisticated control program to be implemented. 1-180 APPENDIX A. SCHEMATIC DIAGRAM ( + 5 VOLTS ~ 11.0 MHZ XTAL 2 XTAL 1 = I ,. I , , 15pF P11~ 2,uF 2716 PlO 27 rlRESET I OPTO·TRIAC MOTOR DRIVER ~ r---------------------------------, 3 XTAL 2 8049 8039 P20~ P21 ~ ... P23 TO PSEN WR RD DBa DB1 DB2 DB3 DB. DB5 DB6 DB7 ...... , ...... ~ <0 1 9 10 8 12 13 14 15 16 17 18 19 I 21 19 17 15 10 8 6 4 008 007 006 005 004 003 002 DO, 8212 018 22 017 20 016 18 0151-1:..::..---, 014 9 013 7 012 5 Db 3 L THE 8212 AND THE 2716 WOULD NOT BE NEEDED IF AN 8049 WAS USED INSTEAD OF AN 8039 ~-----ll SOLENOID DRIVER #11 r---i SOLENOID DRIVER #21 r---1S0LENOID DRIVER #31 DS2 J~"UV" 1 2 3 4 5 6 7 8 l 1 23 D01DS1 INT DO, 003 004 L.---:~D05 8212 L._ _ _1~5HD06 L.._ _ _--.;.1;M7 007 L-_ _ _ _~1~~~D08 ~ A7 A6 As A4 AJ A2 A1 LINE FEED DRIVER ~2 011 012 013 014 0,5 016 017 3 5 7 9 16 18 20 r- {>o-- BUSY DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 SOLENOID DRIVER #41 SOLENOID DRIVER #51 8212 ll.i:= ISOLENOID DRIVER #61 L-----IISOLENOID DRIVER #71 > ~ .... inter AP·91 APPENDIX B. MONITOR LISTING dl ( 08 J ~Eg ,"I, ,P.O.P.." IMPLE"ENTS CONTROL OF THE C ITDH "ODEL 82B THE H"ROWARE CONFIGURATIDN IS AS SUCH: ,'PINTER :8212 INPUT PORT ON 8us • DATA INPUT 16 ;8212 OUTPUT PORT DN BUS' OUTPUT TO SOLENOID HAM"ERS ;TI !HPUT • CHARACTER POSITIONING SENSOR ON PRINTER ,TB :HPU! • iNTERRUPT FRO" 8212 INPUT PORT ;PORT IB MOTOR ON, LOW' ON ,PORT 11 LIME FEED STROBE, LOW' ON 'PORT 16 • LEFT HARGIN SENSOR, LOW WNEN COYERED, HIGH WHEN OPEN :PORT ,7 • RIGHT MARGIN SENSOR. LDU UHEN COVERED, HIGH UHEN OPEN ;TI • PIM 2 OF L"339, PRINT WHEEL SENSOR :PORT 16 PIN 13 OF LM339 :PORT 17 • PIN \4 OF LH33' 17 13 :.~ s ~ 10 J.I 12 13 14 15 19 20 21 OBBa B8BI 0811~ BD B3 ~ ~.* STBCHT 9804 26 TEMPI BOO~ 27 STATLIS E9U E9U E9U EgU EDU egU ;POINTS :POINTS ;STATUS : STROBE P.B Rl ~,;! R3 38 3I 32 33 34 35 36 37 aBOF aS26 38 3q LI HCH T 4B ,IUNK 1 41 "AX 42 FI P. ST 43 SEJE['T egU egU EQU EQU AT INPUT LOCATION AT OUTPUT LOCATION FOR PRINTING COUNTER ;BIT LINE FEED SET ;BIT PRINT :BIT CONTINUE ;BIT • CR FOUND :BIT LF FOUND :BIT LF FOUND IN PRINTING ;BIT 6 PRINT DIRECTION ;9 = RIGHT TO LEFT :\ = LEFT TO RIGHT :BIT 7 • BUFFER LOAD DIRECTION ;B = FIRST TO "AX :\ = MAX TO FIRST :THE LIKE COUNTER 29 Bsa, ••••••••••••••••••••• ••••••••••• R4 R5 2S BBB6 ~.~ : SYP EM EOLIATES 22 i IlB UF 23 OUTBUF 24 SAIIPHT 2S .•.• .. -.... •• * ••••••••• R6 ~7 6FH :"AX BUFFER LOCATION :BOTTOM OF BUFFER ~BH 1-182 intJ LOt OBJ AP·91 SE9 S OllP,( E 5THTEH£HT .4 asBB 45 ORe 4. '7 , J UM P 4~ [IJ S 5B 51 52 53 54 O~ 43 JaBB 15 aBB 1 94BB BBBA aOOH on R '! HE IHTERRUPT LOCATIOHS I BL I H , ' "P G ; DOH' T LISE IHTERRUPTS :BEGIH THE PROGRA" BAH :START THE PROGRAH 55 56 57 BBBA FD DB OF 3211 BBBD 340B OB BF 04 BA 58 'L O(IP PRHT, 5~ 60 61 62 63 64 65 67 iI( HK 69 LPRHT: ,IHP : GO F I X UP TH E STATUS 6~ LPRIH l' J87 ; ,IUHP TO CASE 2 AHD 3 [.~SE23 70 ,I"P : ,I UHP TO CASE B AHD I ( ~ SE 8J 7I 72 ,( .. 5 E0 I ' LOA[II HG THE BUFFER FRO" FIRS T TO "AX , n BBI7 B~2B 74 CASESl: HO '; 8828 ~5 lu , , "0'; BSIB FA as lL 940[' [)2S2 ~4 8 3 ?a OB2B lJB22 B431 as 9 I' 82 B3 882'- B~6F 84 CASH3: 35 ao 26 BBbF aa28 e92[1 aB2F ~9 CHL JBb CPLL JHP :(~~E23 NOV HOV MY CALL 9483 8~ CALL 04 aD 98 ~ I 92 HHC-T \,I"P D2C2 87 \186 T (lUT9UF ,HIRST 1 H3llF, 'FIRST A, ,A'/PHT "0'/ a. as 0828 F~ 31329 '34 [1[.. : GE T THE STATUS : IF PRIHTIHG, [:DHTIHUE :READ IHTO THE BUFFER :LOOP ,T HIS ROll T I HE PRIHTS A LI HE FIP.~T SA 'JE S THE STATUS ,AHD THEH DE~ER"IHES WHHH DIRECTIOH TO PRIHT 'AHP HCI!4 a MAHIPULATE THE BUFFER 8019 BBJE THE BUFFER F lLL S UP A,saTUS lPRl1T UIBUF PPIH 'p 6. DB II 34C' aSI, F224 aSls 0417 LIN T I I HOV J BI CALL J"P "[)TON ( t-I SE 1 PP.HTBK ( "SE 0 . :SET UP OUTBUF :SET UP IHBUF :GET THE SAYED STATU S ;TURN OH TNE MOTOR :PRINT F OW ARD :GET REAOV TO PRINT BACKWARDS ;PRIHT BACKWARDS LOA[II HG BUFFER FRDH MAX TO FIRST Ol! TaUF ""AX ,HBUF, 'HAX A '; !1'Jp NT HOHlIl C""E 3 P~llTBK ( H 5E 2 1-183 : SE T UP OUTBUF :SET UP IN8UF ; GE T THE PRINT STATUS ,: TURN OH THE HDTOR ; PR I NT LEFT TO RIGNT :GET READY TO PRINT BACKWARDS ,PP.INT RIGHT TO LEFT inter loe OBJ Bnl FI 8132 8134 ·1136 1138 lilA IIlC 813E 1141 1142 1144 34'1 8121 F242 '45E CUE BF2B '463 1431 BF28 8I4A 884B 884D 114F 1151 FL B128 l491 AF 1444 H6J 8146 945E 8848 CiAE 1152 FI Bl53 3491 IISS AF 1156 8128 1158 F262 liSA 9463 115C '4SE liSE C675 8168 8452 8862 B128 1164 BF28 I I " 9463 816B 945E IIU Ci75 8B6C Fl IB6D 3491 IBiF 8462 AP·91 SED 9J H SOURCE STATEIIENT CASEI' 95 ,." IBI " IBI H 112 FOC' 183 FOC I' 184 115 186 187 188 IB' 118 " 111 112 113 114 115 116 CASEI' 117 liB 119 121, 121 122 12l 124 125 CRFOKD. 126 127 12B 129 131 131 Il2 133 tEJECT IIOY CAlL HOY JB7 CALL JZ "OY CALL JIIP HOY CAlL CAlL JZ "OY "OY CALL HOY Jill' A, .OUTBUF FKPRHT .OUTBUF,12IH FOC I NCT ST WATCHD JUNK L 128H GTPRHT CASEI J UNU, 128H GTPRNT I KCTST WATCHD A, IDUTBUF tDUTBUF,12IH FKPRHT JUNU,A FOCI IGET THE CHARACTER IADJUST FOR PRINTING ,PUT A SPACE IN BUFFER RAN 'FOUND A CR 'UPDATE OUTBUF I WAIT FOR" END ICET A SPACE TO PRINT IGO PRINT A SPACE IlOOP IGO PRINT THE LAST SPACE IGO PRINT A CHARACTER )CHECK OUT BUFFER IWAIT FOR THE END )GET THE CHARACTER' ,PUT A SPACE THERE IFIX THE CHARACTER UP ) SAYE IT ,LOOP ) :CASE I. PRI NT! NG LEFT TO RIGHT. LOADING 8UFFER FRO" )FIRST TO UX "OY CAlL "OY "OY JB7 CAlL CALL JZ J"P "OY "OY CALL CAlL J2 "DY CALL JIIP A.IOUTBUF FKPRNT JUHU.A .OUTBUF,128H CRFOHD GT PRHT INCTST . YATCH CASE I tDUTBUF .128H J UKK I •• 28H GTPRHT· IHCTST YATCH A, lOUT BUF FXPRHT CRFOHD 1-184 eET THE CHARACTER ADJUST FOR PRINTING SAYE Ace PUT A SPACE IN THE BUFFER FOUND A CR? GO PRINT THE CHARACTER CHECK THE BUFFER IS THE LAST CHARACTER BEING PRINTED? LOOP PUT A SPACE IN THE BUFFER"IIEIIORY PUT A SPACE IH TEIIP LOCAT 10K GO PRINT THE SPACE CHECK THE BUFF ER LAST CHARACTER PRIHTtD? GET THE NEXT CHARACTER ADJUST IT LOOP intJ Lot OBJ AP·91 SEll SOURCE STATE"ENT I J4 lI?l 947B BB73 148A BI75 8876 Bl77 Bl7B 887A 887B 8170 887E 117F 27 62 55 3488 ., F27A 65 FD 5285 8881 '4DF 8883 53FD 8185 53F8 8187 AD IBBB FA IIU B271 BBBB B4BA 135 136 137 DOLF. 138 139 141 141 142 143 WATCN. 144 145 146 147 LOOPY. 14B 149 151 151 152 153 154 OYRI. 155 I" 157 158 159 JTHIS ROUTINE CALLS THE LINE FEED ;STROBE LINE FEED SOLENOID ;GO BACK TO THE PRINT ROUTINE L1HEFD PRHT :THIS ROUTINE CO"PLETES A LINE WHEN THE PRINT :NEAD IS "OYING LEFT TO RIGHT CLR "OY STRT CALL IN J87 STOP noy JB2 CALL ANL ANL nOY nOy JB5 J"P : ZERO Aci; :ZERO TI"ER :START THE TInER :GO READ TNE LAST CHARACTER :EXAnIH PORT ONE :CNECK RICNT NAND SENSOR ) SlOP THE TI"ER ;GET THE STATUS :JUHP IF CONTINUE IS SET ; TURN "DTOR OFF :RESET BIT ONE :RESE~ CONTINUE BIT ; RESTORE STATUS ICET THE SAYE_ STATUS :00 A LINE FEED IF BIT IS SET IGO BACk TO PRINT ROUTIHE A T, A T LDBUF A, PI LDOPW TCNT A,STATUS OYRI "OTOF A,IBFDH A,'BFBN STATUS,A A,SAYPNT DOLF PRNT I6B BaeD FI U8E 34'1 .891 8121 8892 F2'E 8894 9472 8896 t6AE 889B 8F28 189A 9463 IUC 8480 189E 8F 21 llAl '463 81A2 ,. 72 IIA4 .t6AE llA6 F I BlA? BlA' IUA BlAC 3491 AF BI28 BUB 161 162 163 164 ;CASE 2, PRIHTING RIGHT TO LEFT, LOADING BUFFER FRO" )"AK TO FIRST 165 CASE2. "OY CALL 166 167 168 169 178 171 172 173 174 FDCA' 1?5 FHRI' 176 177 178 179 188 181 182 183 $EJECT noy JB7 CALL JZ "OY CALL JftP noy CALL CALL JZ noy CALL noy "OY J"P A.eOUTBUF FXPRNT tOUTBUF, '28H HCR T>ECTST WATCHD JUHKI,128H GTPRHT CASE2 .1 UNK J, .2BH GTPRNT DE CrsT WATCHD ~,UUTBUF FXPRNT JUNKI, ~ POUTBUF,128H FDCRI 1-185 GET THE CHARACTER ADJUST FOR PRINTING PUT ~ SPACE IN BUFFER RA" FIND A CR YET CHECK THE BUFFER IF ZERO YAIT FOR SENSOR FLAG PUT SP~CE IN TE"P LOCATION GD PRIHT SP~CE LOOP GET A SPACE GD PRIHT THE CHARACTER CHECK THE BUFFER LEAH IF DDHE GET A CHARACTER ADJUST THE CHARACTER FOR PRINTING SAYE IT PUT A SPACE WHERE THE CHARACTER WAS LOOP inter LDC IIAE 1188 IIBI 1183 1184 D8J .,3411 IUA 118C IIBD Bl8E BlCI 02AE FD 52BA 940F UFo 53FB AD FA 8271 IUA IIC2 IICl IIC5 .IC6 I.CB IICA IICC 18CE 8101 1802 BI04 1106 IIVB 810A BlOC liDO BlOF FI 3491 AF B128 H02 9463 9472 C675 B4C2 BI21 BF28 '463 9472 C675 FI 3491 8402 I." IIB8 Ap·91 SEa SOURCE SUTUENT 184 : THI S ROUTINE WAITS FOR THE SEHSOR,FLAGS TO BE COYEREO 185 :IIHEN PRINTIHG RIGHT TO LEFT 186 187 188 WATCHO: CALL LDBUF :GD READ THE LAST CHARACTER A, PI IN JCET SENSOR IHFOR"ATION 18' 191 JU IIAltHD :'LOOP IF SEHSOR IS NOT COYERED A,STATUS 191 HOY JCET THE STATUS OYR :SEE IF CONTI HUE IS SET 192 J82 193 CALL :TURN THE ROTOR OFF "OTOF A,IIFOH :RESET BIT I 194 ANL A,IIFBH :RESET BIT 3 195 OYR : ANL STATUS,A 196 HOY :RESTORE STATUS A,SAYPHT :CET THE SAYED STATUS 197 "DY DOLF J DO A LI HE FEED 198 JB5 JRP PRHT J HIT 199 288 :CIISE l, PRIHTlNG LEFT TO RIGHT, LOADING BUFFER FRO" 211 282 :"IIK TO FIRST 283 I 214 CASEl : "OY A,'OUT8UF GET A CHARACTER FKPRHT FIX FOR PRINTIHG 285 CALL S'AYE CHARACTER 216 JUHK),A "OY tOUTBUF,12BH 287 HOY PUT A SPACE IN THE 8UFFER JB7 LEAVE IF A CR IS FOUND 288 CR'FNO 219 GTPRHT GO PRINT THE CHARACTER CALL 21B CALL DECTST CHECK THE BUFFER 211 WATCH LEAVE IF DONE JZ LOOP, 212 CASEl J"P POUTBUF,128H 213 CRF NO: HOY PUT II SPACE IN THE BUFFER RA" 214 HOY JUHK1,'2BH GET A SPACE 215 CALL GTPRHT PRINT A SPACE 216 CALL DE CT S T CHECK THE BUFFER 217 JZ WATCH LEAYE IF DONE ,2.18 A,tOUTBUF GET NEXT CHARACTER "OY 219 CALL FXPRNT ADJUST IT 228, CRFNO LOOP J"P 221 SEJECT 1-186 AP·91 LOC OBJ BIBB BIBB BIBI BIB3 8115 IIB7 8119 IliA BIIC BIBD BIBF BIll 1113 1114 8116 8118 IlIA n B21C 1287 8981 928F FE 438B AE 23FF 721A H78 19 721A 'JZU 2413 2488 SE Q 222 223 224 L08UF: 225 ORG I BBH IN A. PI READ PORT I JB5 IN"ODE 8IT 5 = H = LINE "ODE 226 J81 ARNP JU"P AROUHD IF "OTOR IS ON 227 PI. 181 H ORL TURN TNE "OTOR OFF J84 NOFF 228 ARHD' NO F OR" FEED KOY 229 A.L1NCNT GET TNE LINE COUNTER 231 ORL A.188N SET KS8 231 KOY L1HCHT.-A RESTORE THE LIHE COUHTER A,IBFFN KOY 232 SET ACC J83 233 HOFF: NOlF JUKP IF NO lINE FEED 234 CALL llHEFD GO DO A IF DR FF 235 8UTlOP: IN READ THE PORT A. PI WAIT FOR SWITCH TO 8E RELEASED 236 JB3 NOLF 237 WAIT FOR SWITCH TO 8E RELEASED JB4 NOlF 8UTLOP LOOP 238 J"P lOOP 2H HOlF' LDBUF J"P 248 241 ,FIRST SEE IF A CHARACTER IS PRESENT IN THE BUFFER 242 IIIC 261F III E 83 BlI F FD Bl2B 5249 1122 9249 BI24 724A 1126 9406 B128 3461 BI2A A8 8128 FD 112C F239 812E 18 812F 2378 8131 08 8132 %49 BI J4 F8 8135 17 1136A8_ BI37 2449 BI39 F8 BI3A B7 BI38 A8 BI3t 231F BI3E 08 BI3F %49 BI41 18 1142 2449 BI44 FO BI45 1249 BIH 9258 BI49 83 243 lNHOPE' JNTlI :IF CHARACTER PRESENT. READ IT CHAR 244 ; IF NOT. EXIT ROUTINE RET 245 2H ,IF THERE IS CHARACTER. READ IT 247 248 CHAR: A.STATUS :GET THE STATUS "OY : IF COHTINUE IS SET. DON'T LOAD 249 ARHDJP JB2 258 :IF IF IS SET, DON'T LOAD JB4 ARHDJP JBl LFCRCK 'WAS CR SET. SEE IF NEXT CHAR IS LF 251 252 CAll GTeAR 'CD ~EAD A CHARACTER 253 GOOD: CALL FXCHAR :"AKE SURE IT IS OK 254 KOY ;SAYE CHARACTER IN BUFFER "EHORY PIHBUF.A 255 HOY A, STATUS :GET THE STATUS 256 J87 SUBI :IF BIT 7 IS SET DECRE"ENT BUFFER 257 INC IH8UF :UPDATE IH8UF HOY 258 A,I"A~.I :CET TOP 259 XRL A"IllBUF :ARE WE AT THE TOP? 268 JNZ ARHDJP : IF HOT ,GET THE STATUS Koy 261 A.INBUF :GET IHBUF 262 DEC A : CHANGE 8V ONE IH8UF,A 263 KOY :PUT IT 8AC~ 264 ARHOJP :GET THE STATUS J"P 265 SUBI: "OY A.IHBUF 'GET IN8UF ;CHAHGE BY OHE DEC A 2" ;PUT INBUF BACK 267 KOY IHBUF.A 268 :GET THE BOTTO" OF THE 8UFFER HOY A.IFIRST-I A,INBUF ;TEST THE BUFFER 269 XRL ,INZ 'IF HOT ZERO READ THE STATUS 271 ARHDJP 271 INC I HBUF :"DVE INBUF BACK 272 ARNOJP :CO GET STATUS J"P 273 CETSTA: Koy A,STATUS 'CET THE STATUS 274 ARHDJP JBB :IF BIT B SET. BYPASS 275 JB4 ~TBlTl 'IF LF IS FOUHD. SET THE STATUS 276 ARNDJP' RET : EXIT 277 278 279 BI4A 9406 814C 2J8A 814E 2428 ;THIS ROUTINE "FORCES· A LF AFTER A CR 281 LF CRCK: CALL 281 KDY 282 283 284 J"P FP 3259 4382 8348 AD 83 5268 4384 1348 AD 1168 83 286 STBITI' "OY 287 288 J8I ORL ADD Koy 291 RET 292 STPRHT: JB2 293 ORL 294 ADD HOY 8VEBVE: RET 289 298 2" 2" 297 ;REAO A CHARACTER ;CET A lINE FEED :JUMP BACK ;THIS ROUTIHE SETS THE STATUS BITS 285 815B BI51 8153 81SS BI57 1158 8159 8158 8,150 815F GreAR A,I8AH GOOD A.STATUS STPRNT A.182H A.I48H STATUS,A BYE8YE A. tB4H A. t48H STATUS. A 1-187 LOAD 'tHE STATUS IF STILL PRINTIHG, LEAYE SET PRINT'8IT UPDATE POSITION COUNTER PUT STATUS BACK EX IT ROUT! NE CHECK CONTINUE 81T SET COHTINUE BIT UPDATE PRINT DIRECTION ~UT THE STATUS 8ACK EX IT inter LOC OB,I AP·91 SOUHE SE" ~,lH~E"'EHT ;THIS ROUTIHE 'CONYERTS' LOWER CASE LET TERS TO ;UPPER CASE 2'8 299 HI 8161 8162 8164 8165 BI67 81 " 8UA BI69 8160 BHE Bl7B BI71 8173 BI74 8175 BI77 817' BI7A BI7C BHD BI7F BI88 BI82 8184 8185 '7 537F AF B3AB E678 FF 37 8328 37 2474 J7 B3AB 37 AF D3 BD ,67F FD HB8 AD 248F FF 038A C689 FF D3ac 8187 '68F 8189 FD BIeA 4318 81SC AD 8180 3458 818F FF LOC 08,1 8198 83 81~1 8192 8134 BI96 BU? 8199 BI9B 819C BI9E BlAB 81AI BIA3 BIA5 BIA? BlAB BIAA BlAB BIAe BIAE BIAF 81Bl 8182 BIS3 BIB~ UI B6 BIB7 81B9 BIBA BIBC BIBD BIBE BICB H 03ac C682 FF 3BI 3B2 383 3B4 3B5 386 3B7 388 3B' 31B 311 312 313 314 315 316 317 318 319 328 321 322 323 324 325 326 321 328 32' 338 331 SEg FKCHAR': CLR AIIL A.17FH HDY JUH~J., A ADO A,IBABH JHC F I HE A, ,I UH~ I "DY ePL ADD A,128H CP L A FIXDUH J"P FIHE: CPL A ADO A,taASH CP L A FIXDUH: HOY JUHKI,.A XRL A,teOH JHZ LFTEST A.STATUS "DY OH A,IBSH HOY STATUS, A F I XF I H J"P LFTEST: HOY A,JlIHY.1 XR L A, IBAH J2 FIXUP HOY A.JUHKI XRL A,18CH JII2 F I XF I H F I XUP: HOY A,. STATUS ORL A,IIBH HOY STATUS,A CALL STBIlI F I XF I H: HOY A. ,IUH~ 1 SOURCE STATEMEHT " RET 3H FXPRHT: HOY XRL J2 HO', ,IUHKJ, A A, UCH FFFIX A. taOH CRFIX 343 XU J2 HOY FF 344 345 346 347 348 HOY AIIL ,IH2 358 351 HOY 352 RET 353 CRFIX' ORt 354 RET 355 l F F IK' HOY 356 ORt 357 HOY 359 HOY RE T 35' HB FFF IX: HOY 361 ORL 362 HOY 363 HOY 364 ORL 365 PiOY ,HOY 366 RET 367 368 lSCHAR' KOY AHL 369 37B RET 33 FF 533F 93 34~ ; SAY( A ,: IS CHAR~CTER A CR ; IF IT IS HOT TEST LF ; CE T THE STATUS J SE T BIT 3 :RESTORE THE STATUS ,: LEAYE :CET CHARACTER BACK ; IS IT A L F ; TF ITS HOT, WE ARE DOHE :CET THE CHARACTER BAC~ ; IS IT A FOR" FEED ; IF HOT FOR" FEED, JUMP ; CE T THE STATUS ; SE T BIT 4 ,:RETURH TH E STAT US ; SE T THE STATUS ;CET THE CHARACTER .: THI S ROUTIHE RECOGNIZES A LF, FF. AN[' CR ;DURING THE PR I HT OPERATIOH .: I T ALSO FORCES A SPACE IF A CHARACTER FOUHD ,: I H THE SUFFER IS HOT I H THE LOOKUP TABLE 03BD C6AB FF 03BA C6AB 53EB %BD 232B 83 4398 83 FO 4328 AO 2328 83 FO 4328 AO FE 4398 AE 2328 :JUHP TO TEST CR LF !HOW SUBTRACT ABH FRO" AC C :EKIT FIx('HAR 332 333 334 335 336 337 338 34B 341 342 CLEAR THE CARRV SYRI P "S8 SAYE ACC SEE IF HUI/BER IS 6BH : IF CARRV IS~'T SEL ,IU"P ; CE T Ace BACK ; SUBTRACT 2BH FROI/ THE ACe XP.L J2 ACC :FDRM FEED ,: CO SET FOR" FEED :RESTORE CHARACTER :SEE IF IT IS A CR :LEAYE IF IT IS ;GET ACC BACK :SEE IF IT IS A IF 'LEAH IF IT IS :CET CHARACTER BACK .: SE E IF IT IS A CHARACTER ;IF IT IS JUHP :PUT A SPACE I H ACC ; SA liE A ••.1 UHK 1 A,JUNK! A,IBAH LFFIX A, ,I UHK 1 A,IBEBH I SCHAR A.12BI! ;HIT >.BBH A.STATUS A,laH STATUS, A A,12BH A.STATLIS A.12UH STATUS, A A,LlHCHT A,18BH L1HCHl,. A A,12BH A J LINk 1 A,I3FH ; SE T 81T 7 : EX I T :CET THE STATUS :SET LF BI T I II STATUS :PlIT THE STATUS BACK : CE T A SPACE ; EXI T :CET THE STATUS ,: SE T L1HE F fED BIT :PlIT THE STATUS BACK ; GE T THE LI HE COUHT : SE T BIT 7 ,: PU T L1HE COUNT BAC~ :CET A SPA CE :EXIT :GET CHARACTER BACK :STRIP THE TWO "SB : HIT 1-188 intJ LOt 08,1 Ap·91 ~H 371 H2 !.OURCE STHTE"EHT :THIS ROLITlHE PRIHTS THE 373 AC E7 E7 BICI BIC2 BIC3 BIC4 6C BICS BIC. 81 CB BICA 2C 82CA 44AB 6U8 BICC BICD BICE BlOB BID2 BID4 8106 DID7 AF FD 0204 5608 2406 4604 BI08 BIDA BIDB BlOC 81 DE 81 EB BIEI 81 E2 81 E3 23F3 FF 9B 62 55 I6EB 24 DC 27 9B 65 83 CH~p.AeTER 1 H THE ACe TEftPI.A ; SA'H CHARACTER PRHTIT: HOY A :"ULTlPLY BY TWO RL 37S :"ULTIPLY BY FOUR RL A 376 A,'TEHPI :ADO OHCE TO HULTIPLY BY 5 ADD 377 378 ;HOU SEE WHAT PAR T OF THE LO[o':UP TABLE TO USE 379 388 :PUT CHARAC'TER I H A, TAR~ET IH TE"P I XCH 381 A.TE"PI ,185 SHORT : ,IU"P TO HI CH A[IDRESS IF BIT 5 SET 382 :CO TO FIRST PART OF LOOKUP TABLE PACEI 3B3 J"P ;GO TO SHOHD PACE OF LOOr.UP TABLE PAGE2 384 SHORT: J"P 3B5 :THIS ROUTIHE TRIC~ERS THE SOLEHOIDS FOR 6BB "ICROSECOHDS 3B6 ; AF TEP. WAITJH~ FOR THE HIGGER SI~HAL FRO" THE PRINTER 387 : 3BS 3B9 FIRE: HOY JUHKI,A : SAYE THE ACC 39B HOY A,STATUS :GET THE STATUS 391 JB6 HTI : SEE IF FORWARD OR BACKWARDS 392 FIREX: JTl ; WA IT FOR T1 F I REX 393 FIREY : LEAVE J"P 394 NT 1 : NTI JHTI 'lOOP 395 FIREY: A.JUNKI :GET ACC BACK HOY 396 PRB,A :TRIGGER THE SOLEHOID HOYX 397 398 :HOW ~ILL .BD HICROSECONOS 399 A, IBF3H :LOAD DELAY HUnBER 4BB HOY T.A : PU T IT IH TI"ER 4BI HDY T ; START THE TIHER 482 STRT ;LOOP OH TlftER FLAG JTF KrDUN 4B3 TSJTF: TSJTF 4B~ J"P ;ZERO ACC 4B5 ~TDUH: CLR A UB., A ;TURN OFF SOLEHOIDS HDYK 486 TCHT ;STOP THE TI"ER 4B7 STOP .: EX I T FIRE ROUTIHE 48S RET 4B9 tE J ECT 374 . 1-189 inter LOC OBJ AP·91 SEQ 418 411 412 413 8288 8211 8281 8212 ·8213 8284 n 8215 8216 8287 8288 828' ?C 12 II 12 7C 828A 8UB 828C 8280 821E 7F 49 H H 36 828F 8218 8211 8212 8213 3E 41 41 41 22 8214 8215 8216 1217 12J8 41 41 41 3E 3E 41 SO 59 7F ., ., 121' 7F 821A 821B H 821C 8210 41 414 415 416 417 418 419 428 421 TABLE I' 422 423 424 425 426 427 428 429 438 431 432 433 434 435 436 437 438 439 448 441 442 443 4" 445 446 447 448 449 451 451 452 453 454 455 456 IEJECT SOURCE STATEKENT ; •••• ~.~ ••••••• ~.~ •• •••• •••• ~ ~ ~.* •• •••••• * •• •••••• ~ ~ *.*~ •••••• *. - !THIS IS THE LOOkUP TABLE. THE "sa IS HOT USED; THE "SB I liS THE DOT TNAT IS THE TOP OF AHY GIVEN CHARACTER AHD THE !LSB IS THE ['OT THAT IS THE BOTTOK OF ANY GIVEN CHARACTER ; •••••••• **.* •• ~.*.~~ . ORC ) ...... .. ...... ~ 288H DB DB DB DB DB 3EH 41H SOH 59H 4EH DB DB DB DB 08 7tH 12H II H 12H DB DB DB DB DB 7FH 49H 49H 36H DB DB DB DB 08 HH 41H 41H 41H 22H DB DB 08 DB DB 7FH 41H 41H 41H lEN DB DB DB DB DB 7FH 49H 49H 49H 41H ~ .... - ...... ••• ... " ..... _ nH· ............ 4~H •• •• ...... • ....... ...... ........ 1-190 *•• * •••• ~.* .... *.* ••••• ~ ••• inter LOC OBJ 02lE 021F 0228 8221 8222 7F 89 B9 89 81 JE 41 8223 8224 0225 8226 8227 41 8228 8229 122A 822B 822C 7F 88 OB 8B 7F 822D 822E B22F 823B 8231 88 41 7F 41 HI 8232 8233 8234 8235 8236 21 48 48 41 3F 8237 8238 82l! 82JA 123B 7F 18 14 22 41 823& 823D 823E 823F 8248 7F 41 48 48 48 1241 8242 8243 B244 8245 7F 82 Be 82 7F 8246 8247 824B 824' 024A 7F 84 88 IB 7F 51 71 AP·91 SE g 457 458 45' 468 461 462 463 464 465 466 467 468 4" 478 471 472 473 4H 475 476 477 478 47' 4B8 481 482 4B3 484 4B5 4B6 487 4B8 4 B' 498 4'1 4 ~2 H3 494 4'5 4% 497 498 499 58B 501 502 58l 584 585 506 587 508 50' SIB SOURCE DB DB DB DB DB ST~TE"EHT 7FH O~H 8~H 8~H BIH DB DB DB DB DB JEH 4IH 41 H 51H 71H D8 DB DB DB DB 7FH 8SH BBH BBH DB DB DB DB DB B8H 41 H 7FH 41 H BOH DB DB D8 DB DB 28H 48H 4BH 4BH 3FH DB DB DB DB DB 7FH 88H I4H 22H 41H D8 DB 08 DB DB 7FH 4BH 4BH 48H 48H DB DB DB DB DB 82H BCH 82H 7FH DB DB DB DB DB 7FH 84H 88H 18H 7FH ... "... ....... " 7FH . . . . . . . III ....... ... ".. ......... .• ....... ...... ,. .... ".. 7FH ........ ...... :t • • 511 HJECT 1-191 inter lOC OBJ 124B 824C 8240 B24E B24F JE 41 41 41 8258 12'1 1252 8253 8254 7F 89 8' 89 1255 8256 8257 8258 82" 3E 41 51 21 5E 3E B6 825A 7F 825B 89 USC U 8250 29 B25E 46 825F 2i U68 82U 8262 49 826l 32 4'4' 8264 8265 82" 8267 826B 81 81 7F 81 81 82" 3F 826A 48 826B 48 BUt 48 8260 3F 8HE 826F 8278 8271 8272 IF 28 48 28 8273 8274 8275 8276 8277 7F 28 18 28 7F IF AP·91 SEQ 512 51J 514 515 516 517 518 519 528 521 522 523 524 525 526 527 528 529 518 531 532 53. 534 535 53. 537 538 539 548 541 542 543 544 545 546 547 548 549 558 551 552 55. 554' 555 556 557 558 55' 56D 561 562 563 564 565 566 fEJECT SOURCE STATE"ENT •• :fI". DB 08 DB DB DB lEH 41H 41H 41H lEH DB DB DB DB 08 7FM 89M 89M 89M 86H 08 DB 08 DB lEH 41M SIH .21H DB 5EH " * .... DB DB DB DB DB 7FH B9H 19H ••••• ,,* 08 DB DB 08 08 ...... ........ • •• .. 29H •• •• 46" 26H 49" 49" 49H 32H 08 DB DB DB 08 81H 81H 08 DB DB DB DB 3FH 48H 48H 48H lFH 08 08 DB 08 DB IFH 28H 48H 28H IFH DB 08 DB DB 08 ~FH •• ._.:t. 7FH 81H 81H ........ ...... .... .. : " . " "."fI: ......... 28H 18H •• ..... "' ...... 2BH 7FH 1-192 inter lOC 08J 827B 827' 827A 8278 B27C as 63 14 B27D B27E B27F 828B 8281 83 84 7B 84 B3 8282 8283 8284 B285 8286 61 51 4' 45 43 14 63 8287 7F 8288 7F un H 828A 41 828B 41 82SC 8280 828E 828F 8298 82 84 88 18 28 8291 8292 8293 8294 829'- 41 41 41 7F 7F B296 8297 8298 B2" 829A 18 DB B29B 829C 8290 . B29E .29F 4. 4. 4B B4 DB 18 4B 4. AP·91 SEg 567 568 569 578 571 572 573 574 575 576 577 518 579 58B 581 582 5B3 584 585 586 5B7 588 589 "8 "I B2 593 "4 595 5" "7 598 599 68D 681 682 6BJ 6B4 6B5 6B6 6B7 688 6B9 618 611 612 613 614 615 .EJECT SOURCE SHTE"EHT 08 08 DB DB 08 63H I4H 88H 14H 63H DB DB DB DB DB B3H B4H 78H B4H B3H' DB DB DB 08 DB 61H 51H 49H 45H 43H 08 08 DB DB DB 7FH •• •• .. •• .... •• .. •• .. •• ......... 7FH 41H 41H 41H DB DB DB DB DB B4H B8H 18H 28H DB 08 DB DB DB 41H 41H 41H 7FH 7FH DB DB 08 DB DB IBH B8H 84H B8H IBH DB DB 08 DB DB 48H 4BH 4BH UH 4BH B2H ....... ......... . 1-193 inter loe 12A8 12A2 12A3 IU4 12A6 BU7 IUB IUR 12AB B2AC B2AD UAF ,8281 OBJ 8811 FA 37 0283 Fe A3 Hce IC 18 FB 0385 "A6 84AE 1283 FC 1284 1286 8287 12BB B289 1288 Inc BUD 82BE I2SF I2ca I2C2 I2C4 nB4 AC FC A3 HCC FC 87 AC IB FB OU5 "B7 84AE AP·91 SEQ 616 617 618 619 628 621 622 623 624 625 6a 627 628 629 638 631 632 6ll 634 635 63' 637 638 639 648 641 642 SOURCE STATE"EHT PAGEl: lHO: "OY "OY CPl J86 "OY "OYP CALL INC INC HOY XRL JHZ Jilp BAKWRD: "OY ADD "OY LKLOI: "OY "OYP CALL "DY DEC KOY IHC HOY XRL JNZ 643 J"P 644 fEJECT STBCHT. nIH A.·SAYPHT A BAKWRD A. TE"PI A U FIRE TE"P I STaCHT' A,STBCHT A·185H LHO SETTI" A. TE"PI A.184H TEKP LA A.,TE"PI A. IA FIRE A·TEKPI A TE"P J.. A STBCHT A,STBCHT A,185H LKLOI SETTI" 1-194 ZERO STROBE COUNTER GET DIRECTIOH FLIP BITS IF BACKWARD JUHP OUT GET THE TARGET GE T THE DATA STROBE THE SOLENOIDS IHCRE"EHT THE POI HTER IHCRE"ENT THE STROBE COUNTER GET THE STROBE COUNTER IS IT FIH REPEAT IF NOT FIYE GO BACK GE T THE TARGET COKPEHSATE FOR GOING BACKWARDS SAYE IT GET THE TARGET GET THE DATA STROBE THE SOLENOIDS GE T TE"PI DECREASE BY ONE PUT IT BACK IHCREftEHT TNE STROBE CDUNTER GE T THE STROBE COUNTER IS IT FIH REPEAT IF NOT FIYE GO BACK, CHARACTER IS DONE inter lOC OBJ a385 1386 8Ja7 BlBB BlB' 88 64~ 658 651 652 653 654 DB DB DB DB DB BBH BBH BBH BBH BBH 65' DB DB DB BB 65& 657 658 08 IB 65' D9 BBH BBH 5FH BSH BSH OS OS D8 OS OS BBH B7H S BH S7H BBH DB DB 08 DB 08 14H aa 88 aa aa 88 5F B3U 87 830E aa 14 7F 14 7F 14 24 211 7F 2A 12 IJU 23 IJIA 13 83IB BS nlc 64 BHU 62 13lE 831F 832! 8321 8322 . II BJBA BS 1314 B315 BJH 8317 B31B SOURCE SlATE"EHl ;. ORC 8388 B7 B3BC BB n8F 13IB 8311 BJ12 1313 SEQ 645 646 647 648 BlBa 8388 a381 B312 B313 lJa4 AP·91 36 49 56 2B '8 ; 66B 661 662 663 664 665 666 667 668 6" 678 671 672 673 674 675 676 677 678 679 681 681 682 683 6S4 685 6S6 687 688 689 6~B 3BBH ·• •• 7~H . . . . . :t . . . ....... • 14H 7FH 14H 08 08 08 7FH DB DB 2AH HH DB DB DB 23H IJH BSH · ......... .• • ~4H ~AH DB 64H DB 62H DB DB OS lDH HH 56H 2BH 5BH 08 08 ... ..•• ..•• •• •• • • •• • •• tEJECl 1-195 inter l[le OS.I AP·91 SE Q HU~(E ST~:EI'IEtn 691 8323 8B B324 99 B32~, B;> 8326 B8 932:' 9B 695 [IS OS [IB [lB 696 ['8 BBH 8BH [IB [IS [IB [IS [IB HH 22H 41 H B8H 88H [IB OS [Ie DB [Ie BBH 8BH 41 H 22H ICH ['B [IS [,e De [IB J4H ~ FH 14 H 22H 692 693 694 ... 88H 89H 87H 697 B329 9329 B32A B328 832C It 22 41 BB 88 8320 BB 832E BB 832F 41 B338 22 8331 I t 8332 22 8333 14 8334 7F 833~ 14 B3Jt. 2~ 8337 8338 83H 833A 833B 9S 98 7F BS 693 699 788 7BI 7B2 ;>B3 7B4 lBS 7B6 797 79B 789 718 711 712 ? 13 714 ~2H 715 88 71 b 717 718 7B 729 DB OB DB DB ['B BSH BSH ?F H BSH BSH 721 833t 8330 833E 83 JF 8348 BB 48 3B B8 B8, 722 723 724 ?25 72\i [I,B ['B [Ie [IB [IB 3BH [IB OB [Ie [,e [IB BSH BSH BSH BSH BSH ['S DB ['B ['8 [19 B8H B8H 4BH BBH B8H [IB [IB ['B 2BH 18 H BSH BSH 4SH SB~ BBH 7"" 8341 8342 8343 8344 8345 BB B8 88 Be 8B B346 B34;> B34S B349 B34A 88 8B 4B BB 8B na 729 738 731 732 " 733 834B 834C 8340 834E B3H B358 B3S1 B352 B353 8354 28 18 8& 84 82 3E 51 49 45 JE 734 ?3~ 736 737 733 733 749 74 l 742 74 J ;>44 745 746 747 746 749 750 ['8 B4~ [lB B2H [IB [IB [IS [IB [IB 3 EH ,<1 H .... .. ' 4~H 45H JEH 751 8355 8356 B357 835S 8359 9B 42 7F 4B 8B 83SA B35S B3 SC B35D B3 SE 62 51 752 753 754 7~S 756 [IS [IB . (IB [IS [IS BSH 42H ;>FH 4SH 8BH .. . 757 49 49 46 B3SF 21 BHB 41 759 759 769 761 7ioC! 763 (64 7';5 [lB [IS [IB [lB [IB [18 [IS 62H ,<1 H 49H 49H 4f.H <1 H 41 H 1-196 inter' l~C 08,1 8361 4~ 8362 4P 8363 33 8364 83.5 836£ 8367 8368 IS 14 12 7F 18 836~ 27 836~ 45 8368 45 836C 45 8360 39 Ap·91 ~E" 76E 76 ;- 768 769 778 771 712 773 774 775 776 777 778 779 788 791 8lOE 830F 8378 8371 8372 8373 8374 8375 8376 8377 3C 782 4A 783 784 4~ 49 31 8J 71 99 85 83 8378 36 8379 49 83lA 49 837B 49 837C 36 785 78. 737 783 789 n8 791 792 7S3 7H 795 79i1 ;:'97 798 ~OUP.(E P9 81H7;:"EHT 4~H pe (.e 4 ['H 33H (.e De (.e [.e De ISH 14H 12H 08 OS DS [.s [.s 18H 27H 45H 45H 45H 3~H JrH 4AH 49H 49H 31H (.s [.e (.e DB ['B 8JH DB 3tjH 08 49H 49H 49H 36H DB D8 • .to.,. ••• 7FH De I·e 09 [.e pe (.s .. . ,..,. .. ... .. .. 7JH 89H a5H a3H • 799 $EJECT 1·197 inter LOC OBJ B370 46 U7E 49 B37F 4' neB 29 B381 lE AP·91 SEQ 8BB 881 882 9BJ 884 B85 SOUP.LE SHTE"ENT DB DB DB 46H DB 49H 49H 29H DB IEH DB DB DB DB DB BBH BBH 14H BIH BlH DB DB DB DB DB 88H 4BH .. •• • _.:t* 8Bb. 8382 BI 8333 B384 U8S 13U BB 14 B8 BB 8387 83SB 138' 83BA 8389 8B 887 888 aB' 83BC 83SD 83SE 838F 839. BB 14 22 41 811 BII 812 91J BI4 815 BI6 817 BI8 81' 828 821 822 BB 823 8391 8392 8H3 8394 83'S 14 14 14 14 14 48 34 B8 B8 8396 8B 8397 8398 83" B3'A 41 22 14 B8 8398 82 824 825 82' B27 828 8n 8J8 831 832 833 8H 835 836 DB DB DB DB 08 DB DB DB 08 I'S I'B DB OS DB ... 34H 88H BlH ·•• BSH 14H 22H 41H IBH •• • •• · ·· 14H 14H 14H 14H 14H BBH 41H · ... •••• 22H 1'9 14H BaH B2H B1H 1J9C 81 837 836 08 08 BHO B3'E B5 nn B2 839 S4B 841 08 5':4H OS 08 B2H " •• . : BSH 842 $EJECT 1-198 intJ LOC 08J B3AB 83A. 83A3 8lA4 83A6 83A7 83A9 B3AA BlAC 8lAD BlAE 8lAF 8lBI 83B3 8385 8386 B388 8lB9 B3BA 8388 8380 838E 838F 83eB 8lC I BlC2 8JC4 83C6 988a FA 37 02S5 FC 836a A3 HCC IC 10 FO IIl85 96;'6 34AE Fe 8364 AC FC Al HCL FC 87 AC 18 FB Ap·91 SEQ 843 PACE2: 844 845 8H 847 Lr. HI: 843 849 858 851 852 B5] 854 855 B56 9S7 8KURO: 853 859 86B L K H II : 861 962 D'3 8'4 865 8&6 867 D3BS 96B %B~ ~69 84~E 87B 871 SEJECT SOLIRL' E HOV HOV CPL JO. HOV .:tDel HO'JP CHL INC IHC HOV XRL ,,1HZ JHP HO'I AO[I HOV NOV HOH CALL "OV DEC HO'J INC NOV XRL \IHZ J"P sa T EHENl ,18CH., _88H II·SAVPNl II Bt:wrw A·TEHPI A·H9k A.~A FIRE TEMP I ST9LHT II .• T8C lIT II ,aSH U:HI S Ell I H A·TEHPI A.164H TEMPI .. A A.1EHPI A·~A FIRE II·TEMPI A TEHPI .. A S10CHT A,SlBCHT A,185H L r. H I I SEllIH 1·199 :ZERO SHOBE COUHTER : GE 1 DIRECTION : FL IP 8ITS : IF 8ACKWARD JUHP OUl : GE 1 lHE TARGEl :.A~~IUSl 1 N E lAHEl : GE 1 lHE DATA :SlR08E·THE SOLEIWIDS : INCREHENT THE POIHTER : IHCREHEHT THE STROBE COUNTER :GEl THE SlR08E COUNTER : IS IT F ]V E ; REPEAT IF HOT F lYE : GO 8ACK :GET THE TARGET : COMPENSATE FOR GOIHG BACKUARDS : SAVE IT :GEl THE TARGET :GEl THE 011 lA :STR08E THE SOLEHOIlIS : GE 1 TE"PI : DECREASE BY ONE :PUl 11 9AU: :INCREHEHT THE STROBE ('QUIlTER :GET THE STROH COUNTER : IS 11 F I V E :REPEAT IF HOT FIVE :GO BliCK, LHARArTER IS [IOHE intJ Loe AP·91 08J SOURLE S1IITE"ENT SEQ 872 87J 874 875 876 877 878 879 88B 881 882 88J 884 885 886 887 888 8S' S9B 891 lUI ,. 8411 27 8411 BU2 '418 G4B4 '4 JF 14B6 B48A 1488 23FE , I4IA J' 8488 14BO BUF 1411 1412 1413 1415 8CB5 8FFF 8EfF B' J7 F21D EE 11 B41? EF8F B4U ECBD B418 845A B410 B41F 1421 1422 1424 B426 B428 8CIN: . SETUP: BCB4 BFFF 8EFF B' 37 023C EE J8 EF 2E EC2C 845A 8'Bl 8J B43F 1441 8442 8443 B445 84 4~ 23FE 62 55 8B28 BEB8 BOBB B4H B448 844[> 844E B44F 8458 B452 8928 2328 Al 19 F" 0378 3HB 8454 "EF B45& sa 8457 8'IB :ZERO ArC :TURN OFF THE SOLEHOIDS , SE T UP THE PRINTER :SET UP THE SOFTWARE :GO 5 TART A . IBH H Pl. A :LDAD At r WITH VALUE TO TURN ON KOTOR :TURN ON "OTOP. "O~ ,NOW DHA'I J, 2 SECON[>S WH IlE CHECKIIIG RIGHT SElFC: SEL FB : SEL FA: U2 9B3 'B4 '85 '86 , A fRB· A SETUP VARSET PRNT DUYl "OY "OY KOY IN CPL TE"PI.1B5H ,IUHK I, I8FFH l I NCHT ,ISfFH A· PI ,187 OOHER LIHCHT.SELFA ,I UHK 1 SELF8 TEHP I SELFr EP. RO R DJNZ OJHZ DJ H2 ,I"P II JUHKI,IOFFH LI H~H T UFFH A. PI oOHEF L1HCHT. SELFI ,I UHK 1 .• ElF ERROR OOhEF : HOY SELFCC' HOY SElF8B: HOY SElFAA: III CPt J86 DJHZ OJHZ TEKP 1 104H JUHKI.I8FFH L I H['HT *SFFH A.Pl A DOHEl LIHCHT SELFAA ,I UHK I, SElFBB TEKP 1, SElF[ C ERROR P! .IDI H OJH~ [>OHEl : J"P ORL RE T 'ND~ YARSET: "[lY HOY STRT 928 "[lY !t29 KO'~ 93B '31 '32 '33 ,J4 "[lY 94. H. :SET UP DEL AV : S[IKE HORE [>HAY :GET THE FL H~ IHFORKATIOH : IS FLAt rL eARED , :IF HOT LOOP :LOOP 30"E "ORE iLEHYE IF FLAG IS HOT UNC O'HRED 'HO~ , AHL KDYX ORL :LOAD [>ELAY : LOAt> [>ElAY : L(It~(1 [IE l~ '!' 3 : RE A[> THE PORT : CHAlICE THIIIGS HROUIHI ZE R0 :O~ IF BIT I. ;S"~LL LOOP ;8IG~ER LOOP :BIGLEST LOOP :S[lKETHINt IS ~RONG :TURN MOTOP. (IFF :CO SACK " " UP THE VARIABLES SE T A UFEH T." : L (I~{) T THE Tl HE R :LOAD INPUT BUFFER :SET LI HE r OUH T . SET FORWAR[I 8 I: THE Tl HER :STH~T I HBUF, HI RST LIIHIH,IOBH 5TATUS IBBH 'CLEAP. THE RAft "REA BY OUTBUF.IFIRST "DY 935 CLR"EH: "DY A.'2BH ~OllTBUF," '36 "O'~ OUT8UF INC '37 A,OUTSUF HOY '38 A,IIHU(~l XU '39 ,1HZ [LR"EK '4B '41 ,NOW rLEAR THE 8212 942 '43 :""r.E 'NO~ CHEC~: THE LEFT SEHSO~ I H THE 5 AHE "ANHER AS THE 'RICHT SENSOR EXCEPT [IELA't [IHL V 2 5 SE~OH[lS ~27 945 SENSOR :LDAD DELAV VAlli E OHE ;L[lA() [>ELAV IJAlUE TWO :LOAO DELAY IJALUE THREE , RE AD POP.T OHE THINGS RIGHT : 1 S 91T 7 SET> ,S"ALL LOOP ,:SIGGER LOOP : 81 GUST LOOP :SO"ETHIH~ IS WROHG 'HOW "AH SURE THE RIGHT SEHSOR 15 rLEARED HOY HOY IH J87 DJHZ OJ HZ \,I"P 987 842A 8He B42E B4 JB 1431 1432 B4J4 14J6 B438 B4 JA 84JC B4 JE CLR CALL CAll J "P B'3 B94 895 8% 8'7 898 89' DOHER: 'BB SHF; 'BI SELFI: 'B8 'B' '18 911 '12 '13 • '14 '15 '16 917 '18 '1' 92B '21 '22 '23 '24 '25 '26 4DBH "DYX B92 8FFF 8EfF I' F22A EE 21 EFIF 845A ORC PI,IBEFH A,UHBUF PI. II 8 H '47 1·200 ~RITIHt SPACE COl> E5 :LOAD OUTSUF : PUT SPACE C. 0 [IE IH A [ [ ,: PU T SPACE ('O[>E IN OATH HEMOR'I :UPDATE THE POI NTER ,KOYE THE POINTER I lIT H Arr :SEE IF [lONE ;LOOP IF NOT CLEARE[> :5E1 EHABLE 8 I T :CLEAR THE 8212 IHPUT BUFFER ; RE SE T EHA8LE BIT inter LOC 08,1 Ap·91 5EQ H8 SOURCE STA7E"EHT ,HOW EKIT VAR&ET '4~ B45' B3 B4 SA a'FF B45C 845t B45E I' B4 SF 2378 B461 8462 83 8463 0' 8464 37 8465 ['263 846? 1608 B46' 8467 B46B .5 B46C FF B460 34C1 B46F HIC 04? ] 33 0' 8472 F~ B473 07 OH4 A~ 8475 D3]F B477 33 BHe FE 847; F23B OHB HF[I 847D BC4~ OHF BFlJ 8481 Ef 81 B483 H7F 848S 8'02 8497 1 E B488 fE B48~ [1328 B488 %8F B480 BESO RET :LEAVE IHITIALIZATIOH 'SO '51 , THI5 ROUTINE TURIIS THE "OTOR OFF AHO LOOf'S 952 '53 PI,IBFFH :TURN OFF "OTOR 954 ERROR: ORL HAD 'LOOP BECAUSE SO"ETHIHG IS WROHC '55 DEAD: J"P , 56 ,THESE ARE ALL SliBROUTIHES TH AT ARE CALLED 957 958 95~ 1 H[ lST: IHC OUTSUF ;UPOATE THE POIHTER NOV :GET THE VALUE FOR THE LAST CHARACTER %B ".tttHK+l A.OUTBUF 961 XRL : ['0 THE TE S T 962 RET :E:nT 963 GTP RH T: IN A.PI : RE AD PORT OHE 964 CPL A :FLIP BITS GTPRHT :LOOP UHT lL SEHSOR IS Ulle-OVERED %5 J86 ;SEE IF TI"ER FLAG IS SET 966 TSTJTF' JIF PIT H? TS TJ IF :TEST FLAC ,I"P 968 P] T : STOP TCHT 'STOP THE T IHER A . ,I UHK I HOV :GET THE CHARAI'TER 96~ ; PR I HT THE CHARACTER 978 PRIlTI! CHL I ; GE T AHOTHER CHARACTER CALL LHHOI'E ,n:lT 972 RE T A.OUTBUF :GET OUTBUF ~7J ['E CTS T : HOY ~74 A DEC 'RHUCE B'I' OHE !475 HO,Y OliTBUF·A 'PUT 8 AU: ] H Oll TBUF A.fFIHT-] :SEE IF IT IS ALL THE WA'I DOWH 9:'':' XU :E:OT 977 RE T ,? "8 979 ;THIS ROLITTHE ODES '8B A·LIHIHT '81 L1HEF[" HOV [. 0 F F ~J8 7' ~a~ ,a3 LF [.0: PI.IBFDH "Hl ~a4 TE HP I • 4[J H H["I .11) N~: I .~3H 995 LF L PI' HOV 996 LFLP2': ~JH< .1 U HK 1 LCLP;: ~87 ~9.! OJHZ ORl IHC NOV XP.L .1 HZ 9'3 "0'1 TEMPI. LFLPI PI.I02H L! IltHT A.LltHAT A t23H 'HOTOOH L I tttH T ISOH 988 981 ~~O ~ ~ I '~4 B48F BtaS OHI BFfF 84'33 EF~3 04~5 Et31 8497 SJ 04~B O~ B4~' H 53CB 04n C69B 049E 8901 S4AB ':147Ee 04A2 FE 04A3 537F' 84 "S 03BB B4.7 C6,,[I 04.9 94?B 84 AB 134 A2 B4 AD 83 B4~A B4 AE 23E8 BUB .2 B481 55 8482 83 '35 '96 ;HO~ ['E Lil \' ~S LI HE FEE[' :GET THE Ll HE COUHT BIT ~ IS SET, DO A fORHFEED : TURIl OH THE SOLEHOID : L Oft{, OllE [. EL"'I , LOA[' "HOTHER OELA'I 'lOOP .LOuP SO HE HORE :TURH OFf LF SOLEHOID :UPltATE THE Ll HE COUtHE? 'GET THE L IllE tOUHT : IS PAGE DO HE : S~: If' OVER :ZERD LI HE COUHTER :IF HILLl5ECOH['S :LOAO ['E LAY VALUES HOHOH: HO'I TE HP I· ISBH .1 UHK I .• OFFH ~93 LOP I : HO'I HI H~: I . L Of'2 '_GEHERATE OEL AI' [ILl HZ' 9~~ LOP 2: TEHP I· LOP 1 ISOS ['J Il' : Ll HE FEED IS [10 HE RE T 1 BS 1 IB82 : T Hl S ROll T I HE (IOE S A FORM FEE [. 18B3 IB04 PI :GET THS &TATU& IH 1005 ['OF F : CPL' . FL If "CC 1886 IBO~ 10CBI< "HL 'LE"VE OHL'I TWO Hsa'S [l OfF :IF A n"e ISH' T COVERED, LOOP 1888 J2 P: IBIH :TURH THE HOTOR OF F 180~ on 101 B CALL 'GO DO OHE Ll HE fEED l r :'0 NOV A Ll HC HT :GET THE Ll HE COUHT I B I I FFC>: : J B 1 .? J7FH :ST~lP Bn SEYE.H "HL 1 B13 XH : IS IT DOHE " .• BOH ,I, I B14 F F DOHE :LE"VE IF IT IS lOIS CALL L r ['0 'STROBE THE SOLEHOIDS FfO' 1816 ,I"P : CHEU: TH.E fOR" fEED OU T 1817 FFOcrHE' RET :t::nT FORH fEEO 1013 A nEBH :GET [IE L A'l VALUE 1019 SET T] H: "0'./ ! :PUT I H TIMER 1828 HOY :START THE TI HE Po STR! T 1821 : E:nT RE T 182'2 1823 ~97 " " 1-201 inter LOC 8483 8484 8485 84810 8487 B488 848' 848A 8UB B4U 148E B4Ca UCI I4C3 84C5 84C7 84CS AP·91 SEQ 42 37 17 1824 PRMTBK: 1825 1B26 1827 17 I? 17 17 62 8' HC8 S488 55 16C5 84CI 23FF 62 83 84CF AD 841'8 8413 84(J~ 4328 8404 SHe 8406 '!lEF 84 DB 98 9918 04!" 841'8 93 840C 9'F£ 840e 33 84DF 8'81' B4EI .83 USER S'tH90lS HI a;8831 84CJ BII71 [lOLF FlIeR! BlAB F UfoT aa~o L TC"~ B4I'f. lOBUF B1 la L IHrHT B886 L OPI B4~1 WOlf BI HI PIT SnFI:! SHORT T E"P 1 BHE! 0411 81 r~ SBB4 MY CPt IHC IHC 1B2S IHC 1829 INC INC 1838 1831 MO" 1832 IULOOP: IH 1833 J87 ,.IMP I8J4 1835 CONPSr.: STRT 183" CONPB: JTF 1837 J"P 1838 ROTOPT: HOY 1839 MOY 1848 RE T 1841' ;TNI S 1842 1843 1844 STACHK: HOY 1845 JB4 1846 84R ET : HOY 1847 ANL 1848 1849 MOY 1858 JHP 1851 LFser, OH ,IMP 1852 1853 1854 ;THIS 1855 1856 GHAR: AHL 1857 "on 1858 ORL RE T 185' 18&8 IBIoI !THIS 1B102 1863 "OTOH: ANL 1864 RE T 1865 ;THI S 1866 1867 1868 "OT OF : OAL RE T 18" 1878 1871 END 84C' FD 84CA 9202 84CL AA B4eD 53C2 UHfl LJiSEB ( OHPB SOURCE STHTEKENT 08J HDJf' 8141<1 UISEBl (OHPU ['OHEf 8917 Hek F 1 XbUH Co TPkHT LF CRC~ LIHEH lOP~ B4~3 ~R B4RET [~SE 1 BoIc( 842/01 U!F]X bONEl Dj AS 84 J[. 8411, F F!JDHE 81 74 B4b3 814M 847B Fl ~F 1 H 1 HBUF If[lO U:HI LPRHT BolA!' BISf BH8 DDS;: IIBBB 8478 03~6 BD 11 HOTOON B48F "T! 8104 PRHT BBBA &ElFAA D43a STACHK 84C~ TSJTF 81 ['C PRHTBk S,ElFB &TATUS T ST~ TF 13"03 OIlBF HSH"EtL'( ('OHPlETE. HO~ BIHlS 846;" , Gel THE TIHER 'TWO$ COMPlEMENT Ace A."I A . A· •A )ADJUST "lIHER )PUT IT BACr. IH THE TIMER :READ PORT I : IF HUSOR I ~ HOT COVERED . LEAVE 'OTHERWISE LOOP .:START THE TIHEP : SEE IF RE A0'/ TO PRINT )OTHERWISE LOOP ) LOM' A )PUT IT IN THE TIHER : EX IT T.~ A. PI CONPSr. IllLOOP T ROTOPT LOMPS •. IIFFH T.A ROUTINE ADJUSTS AND SAVES THE STATUS A,STATUS LFSET SAVPNT .• A, IBC2H DURIN~ PRINTING ) GE T THE STATUS .: SE T LINE FEED BIT :SAYE THE STATU& :RESET EYERYTNI NG EXCEPT :DIRECTION ANO PRINT )PUT THE STATUS BACK )HIT ; SET BIT 5 , ,IU"~ BACK STATUS.A LPRNTI A,IZ8H 84RET ROUTINE READS CHARACTER AHO PUTS IT IN Pl,18EFH A,@INBUF Pl,IIBH .: SE T ENABLE BIT :REAO THE CHARACTER :RESET ENABLe BIT :HIT G.TCHAR T~E Ace ROUT-I NE TURNS THE "OTOR OH PI,IIFEH )TURN "OTOP. ON 'eXIT ROUTIHE TURN& THE HOTOP. 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P1.0 P1.1 P1.2 P1.3 PO.2 P1.4 P1.5 P1.6 P1.7 VPO/RST PO.3 P3.D/RXD P3.1/TXO Pl.2I1NTO Pl,-3.iNTi P3.4/TO P3.5/T1 RST/VPO PO.4 PO.6 PO.7 YDO/EA PiiOGfALE }-" PSEN P2.7 TXD . {RXD iNTo mr1 P2.6 P3.6/WR P2.5 P2.4 P3.7fiiD P2.3 XTAL2 XTAL1 P2.2 P2.1 V5S P2.0 PORT 3 TO T1 WR AD Figure la. 8051 Microcomputer Pinout Diagram ~}~M'. Figure lb. 8051 Microcomputer Logic Symbol 1. INTRODUCTION some microprocessor (preferably Intel's, of course) or have a background in computer programming and digital logic. In 1976 Intel introduced the MCS-48'· family. consisting of the 8048. 8748. and 8035 microcomputers. These parts marked the first time a complete microcomputer system, including an eight·bit CPU. 1024 8·bit words of ROM or EPROM program memory. 64 words .of data memory. I 0 ports and an eight-bit timertcounter could be integrated onto a single silicon chip. Depending only on the program memory contents. one chip could control a limitless variety of products. ranging from appliances or automobile engines to text or data processing equipment. Follow-on products stretched the M CS-48'· architecture in several directions: the 8049 ami 8039 doubled the amount of on-chip memory and ran 83'ff faster; the 8021 reduced costs by executing a subset of the 8048 instructions with a somewhat slower clock; and the 8022 put a unique two-channel 8-bit analog-to-digital converter on the same NMOS chip as the computer, letting the chip interface directly with analog transducers. Family Overview Pinout diagrams for the 8051. 8751. and 8031 are shown in Figure I. The devices include the following features: Now three !lew high-performance singlecchip microcomputers .. the Intel® 8051, 8751. and 8031-extend the advantages of Integrated Electronics to whole new product areas. Thanks to Intel's new HMOS technology, the MCS-5I'· family provides four tli 'es the program' memo'ry and twice the data memory as the 8048 on a single chip. New I/O and peripheral capabilities both ' increase the' range of applicability and reduce total system cost. Depending on the use, processing throughput increases by two and one-half to ten times. This Application Note is intended to introduce the reader to the MCS-51'· architecture and features. While it does not assume intimacy with the MCS-48'· product line on the part of the reader. he/she should be familiar with • Single-supply 5 volt operation using HMOS technology. • 4096 bytes program memory on-chip (not on 8031). • 128 bytes data memory on-chip. • Four register banks. • 128 User-defined software flags. • 64 Kilobytes each program and external RAM addressability. • One microsecond instruction cycle with 12 MHz crystal. • 32 bidirectional I/O lines organized as four 8-bit ports (16 lines on 8031). • Multiple mode, high-speed programmable Serial Port. • Two multiple mode. 16-bit Timer/Counters. • Two-level prioritized interrupt structure. • Full depth stack for subroutine return linkage and data storage. • Augmented MCS-48'· instruction set. • Direct Byte and Bit addressability. • Binary or Decimal arithmetic. • Signed-overflow detection and parity computation. • Hardware Multiple and Divide in 4usec. • Integrated Boolean Processor for control applications. • Upwardly comp~tible with existing 8048 software. AFN-01502A-04 2-2 intJ AP-69 All three devices come in a standard 40-pin Dual InLine Package, with the same pin-out, the same timing, and the same electrical characteristics. The primary difference between the three is the on-chip program memory --different types are offered to satisfy differing user requirements. ware application examples illustrate many of the concepts. Several isolated tasks (rather than one complete system design example) are presented in the hope that some of them will apply to the reader's experiences or needs. A document this short cannot detail all of a computer system's capabilities. By no means will all the 8051 instructions be demonstrated; the intent is to stress new or unique MCS-51'· operations and instructions generally used in conjunction with each other. For additional hardware information refer to the Intel MCS-S\'· Family User's Manual. publication number 121517. The assembly language and use of ASM51. the MCS-51'· assembler, are further described in the MCS-S\'· Macro Assembler User's Guide, publication number 9800937. The 8751 provides 4K bytes of ultraviolet-Erasable, Programmable Read Only Memory (EPROM) for program development, prototyping, and limited production runs. (By convention, I K means 2'" = 1024. I k·-with a lower case "k"-equals IOJ = 1000.) This part may be individually programmed for a specific application using Intel's Universal PROM Programmer (UPP). If software bugs are detected or design specifications change the same part may be "erased" in a matter of minutes by exposure to ultraviolet light and reprogrammed with the modified code. This cycle may be repeated indefinitely during the design and development phase. The next section reviews some of the basic concepts of microcompu\er design and use. Readers familiar with the 8048 may wish to skim through this section or skip directly to the next. "ARCHITECTURE AND ORGANIZATION." The final version of the software must be programmed into a large number of production parts. The 8051 has 4K bytes of ROM which are mask-programmed with the customer's order when the chip is built. This part is considerably less expensive, but cannot be erased or altered after fabrication. MIcrocomputer Background Concepts. Most digital cdmputers use the binary (base 2) number system internally. All variables. constants, alphanumeric characters, program statements, etc .• are represented by groups of binary digits ("bits"), each of which has the value 0 or I. Computers are classified by how many bits they can move or process at a time. The 8031 does not have any program memory on-chip, but may be used with up to 64K bytes of external standard or multiplexed ROMs, PROMs, or EPROMs. The '8031 fits well in applications requiring significantly larger or smaller amounts of memory than the 4K bytes provided by its two siblings. The MCS-51'" microcomputers contain an eight-bit central processing unit (CPU). Most operations process variables eight bits wide. All internal RAM and ROM. and virtually all other registers are also eight bits wide. An eight-bit ("byte") v'ariable (shown in Figure 2) may assume one of 2" = 256 distinct values. which usually represent integers between 0 and 255. Other types of numbers. instructions. and so forth are represented by one or more bytes using certain conventions. (The 8051 and 8751 automatically access external program memory for all addresses greater than the 4096 bytes on-chip. The External Access input is an override for all internal program memory-the 8051 and 8751 will each emulate an 8031 when pin 31 is low.) Throughout this Note, "8051" is used as a generic term. Unless specifically stated otherwise, the point applies equally to all three components. Table I summari7.es the quantitative differences between the members of the MCS-48'· and MCS-51'· families. For example, to represent positive and negative values. the most significant bit (D7) indicates the sign of the other seven bits-O if positive. I if negative-allowing integer variables. between -128 and +127. For integers with extremely large magnitudes. several bytes are manipulated together as "multiple precision" signed or unsigned integers-16. 24. or more bits wide. The remainder of this Note discusses the various MCS-51'· features and how they can be used. Software and/or hard- Table 1. Features of Intel's Single-Chip Microcomputers EPROM Program Memory ROM Program Memory External Program Memory Program Memory (Int/Max) Data Memory (Bytes) Instr. Cycle Time Inputl Output Pins Interrupt Sources Reg. Banks -- 8021 8022 8048 8049 8051 -- IK!IK 2K'2K IK:4K 2K,4K 4K,64K 64 64 64 8.41,Sec 8. 4 "Sec 2.5"Sec 1.36,ISec 1.0"Sec 21 28 27 27 32 0 2 2 2 5 I I 2 2 4 8748 8751 8035 8039 8031 128 128 AFN-01S02A-05 2-3 intJ Ap·69 The letters "MCS" have traditionally indicated a system or family of compatible Intel@> microcomputer components, including CPUs, memories, clock generators, I/O expanders, and so forth. The numerical suffix indicates the microprocessor or· microcomputer which serves as the cornerstone of the family. Microcomputers in the MCS-48'· family currently include the 8048-series (8035,8048, & 8748). the 8049-series (8039 & 8049), and the 8021 and 8022; the family also includes the 8243, an I/O expander compatible with each of the microcomputers. Each computer's CPU is derived from the 8048, with essentially the same architecture, addressing modes, and instruction set, and a single assembler (ASM48) serves each. a single character. and a word or sequence of letters may be represented by a series (or "string") of bytes. Since the ASCII code only uses 128 characters. the most significant bit of the byte is not needed to distinguish between characters. Often D7 is set to 0 for all characters. In some coding schemes, D7 is used to indicate the "parity" of the other seven bits--set or cleared as necessary to ensure that the total number of "I" bits in the eight-bit code is even ("even parity") or odd ("odd parity"). The KOSI includes hardware to compute parity when it is needed. , A computer program consists of an ordered sequence of specific, simple steps io be executed by the CPU one-ata-time. The method or sequence of steps used collectively to solve the user's application is called an ··,algorithm." The program is stored inside the computer as a sequence of binary numbers. where each number correspond~ to one of the basic oper,ations ("opcodes") which the CPU is capable of executing. In the 80S I. each program memory location is one byte. A complete instr.uction consists of a sequence of one or more bytes. where the first defines the operation to be executed and additional bytes (if needed) hold additional information. such as data values or variable addresses. No instruction is longer than three bytes. The first members of the MCS-51'· family are the 8051, 8751, and 8031. The architecture of the 8051-series, while derived from the 8048, is not strictly compatible; there are more addressing modes, more instructions, larger address spaces, and a few other hardware differences. In this Application Note the letters "MCS-51" are used when referring to architectural features of the 8051-series-features which would be included on possible future microcomputers based on the 8051 CPU. Such products could have different ·amounts of memory (as in the 8048/8049) or different peripheral functions (as in the 8021 and 8022) while leaving the CPU and instruction set intact. ASM51 is the assembler used 9Y all microcomputers in the 8051 family. The way in which binary opcodes and modifier bytes are assigned to the CPU's operations is called the computer's "machine language." Writing a program directly in machine language is time-consuming and tedious. Human beings think in words and concepts rather than encoded numbers. so each CPU operation and resource is given a name and standard abbreviation ("mnemonic"). Programs are more easily discussed using these standard mnemonics. or "assembly language." and may be typed into an Intei'· Intellec® 800 or Series Il® microcomputer development system in this form. The development system can mechanically translate the program from assemhly language "source" form to machine language' "object" code using a program called an "assembler." The MCS-SI'· assemhler is called ASMSI. Two digit decimal numbers may be "packed" in an eightbit value, using four bits for the binary code of each digit. This is called Binary-Coded Decimal (BCD) representation, and is often used internally in programs which interact heavily with human beings. There are several important differences between a computer's machine language and the assembly language used as a tool to represent it. The machine language or instruction set is the set of operations which the CPU can perform while a program is executing ("at run-time"). and is strictly determined by the microcomputer hardware design. Alphanumeric characters (letters, numbers, punctuation marks, etc.) are often represented using the American Standard Code for Information Interchange (ASCII) convention. Each character is associated with a unique seven-bit binary number. Thus one byte may represent I The assembly language is a standard (though more-orless arbitrary) set of symbols including the instruction ,et mnemonics, but with additional features which further simplify the program design process. For example. ASMSI has controls for creating and formaning a program listing. and a number of directives for allocating variable storage and inserting arbitrary hytes of data into the ohject code for creating table> of con,tants. 0 07 06 05 04 03 02 01 DO Figure 2. Representation of Bits Within an Eight-Bit "Byte" (Value shown = 01010001 Binary = 81 decimal). AFN-01502A·06 2-4 AP-69 In addition. ASM51 can perform sophisticated mathematical operations. computing addresses or evaluating arithmetic expressions to relieve the programmer from this drudgery. However. these calculations can only use information known at "assembly time." assembly language by a series of ones and zeros (naturally). followed by the letter "B" (for Binary); octal numbers as a series of octal digits (0-7) followed by the letter "0" (for Octal) or "Q" (which doesn't stand for anything. but looks sort of like an "0" and is less likely to be confused with a zero). For example. the 8051 performs arithmetic calculations at run-time. eight bits at a time. ASM51 can do similar operations 16 bits at a time. The 8051 can only do one simple step per instruction. while ASM51 can perform complex calculaiions in each line of source code. However. the operations performed by the assembler may only use parameter values fixed at assembly-time. not variables whose values are unknown until program execution begins. Hexadecimal numbers are represented by a series of hexadecimal digits (0-9,A-F). followed by (you guessed it) the letter "H." A "hex" number must begin with a decimal digit; otherwise it would look like a user-defined symbol (to be discussed later). A "dummy" leading zero may be inserted before the first digit to meet this constraint. The character string "BACH" could be a legal label for a Baroque music synthesis routine; the string '~OBACH" is the hexadecimal constant BAC,.. This is a case where adding 0 makes a big difference. For example. when the assembly language source line, ADD A,#(LOOP_COUNT + I) * 3 Decimal numbers are represented by a sequence of decimal digits. optionally followed by a "D." If a number has no suffix. it is assumed to be decimal-so it had better not contain any non-decimal digits. "OBAC" is not a legal representation for anything. is assemhled. AS M51 will find the value of the previously-defined constant "LOOP_COUNT" in an internal symbol table. increment the value. mUltiply the sum by three. and (assuming it is between -256 and 255 inclusive) truncate the product to eight bits. When this instruction is executed. the 8051 ALU will just add that resulting constant to the accumulator. When an ASCII code is needed in a program. enclose the desired character between two apostrophes (as in 'W) and the assembler will convert it to the appropriate code (in this case 23H). A string of characters between apostrophes is translated into a series of constants; 'BACH' becomes 42H. 41 H, 43H. 48H. Some similar differences exist to distinguish number system ("radix") specifications. The 8051 does all computations in binary (though there are provisions for then converting the result to decimal form). In the course of writing a program, though. it may be more convenient to specify constants using some other radix, such as base Hr.,On other occasions.it is desirable to specify the ASCII code for some character or string of characters without refering to tables. ASM51 allows several representations for constants. which are converted to binary as each instruction is assembled. These same conventions are used throughout the associated Intel documentation. Table 2 illustrates some of the different number formats. 2. ARCHITECTURE AND ORGANIZATION Figure 3 blocks out the MCS-51'· internal organization. Each microcomputer combines a Central Processing Unit, two kinds of memory (data RAM plus program ROM or EPROM), Input/Output ports. and the mode. For example. binary numbers are represented in the Table 2. Notations Used to Represent Numbers Bit Pattern 00000000 00000001 ............... 00000111 00001000 00001001 00001010 ............... 0000 1 1 1 1 00010000 ............... o1 1 1 1 1 1 1 10000000 10000001 ............... 1 1 1 1 1 1 10 111111 I I Binary Octal HexaDecimal Decimal OB IB OQ IQ OOH OIH IIIB 1000B 100lB 10 lOB 7Q IOQ IIQ 12Q 07H 08H 09H OAH IIIIB looOOB 17Q 20Q OFH IOH 15 16 177Q 200Q 20lQ 127 128 129 ........ ... 7FH 80H 81H 1l111l10B IIIIIIIIB 376Q 377Q OFEH OFFH 254 255 .. .. .. lllllllB 10000000B 1000000lB '" . .. 0 I Signed Decimal 0 +1 ... .. . ... ... .. . ... ... ... 7 8 9 10 " ... +7 +8 +9 +10 +15 +16 .... +127 -128 -127 .... -2 -I AFN·01502A·07 2-5 AP-69 TIMER CONTROL Figure 3. Block Diagram of 8051 Internal Structure status. and data registers and random logic needed for a variety of peripheral functions. These elements communicate through an eight-bit data bus which runs throughout the chip. somewhat akin to indoor plumbing. This bus is buffered to the outside world through an I/O port when memory or I/O expansion is desired. Let's summarize what each block does: later chapters dig into the CPU's instruction set and the peripheral registers in much greater detail. Central Processing Unit The CPU is the "brains" of the microcomputer. reading the user's program and executing the instructions stored therein. Its primary elements are an eight-bit Arithmetic/ Logic Unit with associated registers A. B, PSW. and SP. and the sixteen-bit Program Counter and "Data Pointer" registers. 2-6 intJ AP-69 Arithmetic Logic Unit • • • • • The ALU can perform (as the name implies) arithmetic and logic functions on eight-bit variables. The former include basic addition. subtraction. multiplication. and division; the latter include the logical operations AND. OR. and Exclusive-OR. as well as rotate. clear. complement. and so forth. The ALU also makes conditional branching decisions. and provides data paths and temporary registers used for data transfers within the system. Other instructions are built up from these primitive functions: the addition capability can increment registers or automatically compute program. destination addresses; subtraction is also used in decrementing or comparing the magnitude of two variables: Arithmetic Operations Logical Operations for Byte Variables Data Transfer Instructions Boolean Variable Manipulation Program Branching and Machine Control MCS-48'· programmers perusing Table 4 will notice the absence of special categories for Input/Output. Timer! Counter. or Control instructions. These functions are all still provided (and indeed many new functions are added). but as special cases of more generalized operations in other categories. To explicitly list all the useful instructions involving I/O and peripheral registers would require a table approximately four times as long. Observant readers will also notice that all of the 8048's page-oriented instructions (conditional jumps. JMPP. MOVP. MOVP3) have been replaced with corresponding but non-paged instructions. The 8051 instruction set is entirely /loll-page-oriented. The MCS-48'· "MOVP" instruction replacement and all conditional jump instructions operate relative to the program counter. with the actual jump address computed by the CPU during instruction execution. The "MOVP3" and "JM PP" replacements are now made relative to another sixteen-bit register. which allows the effective destination to be anywhere in the program memory space. regardless of where the instruction itself is located. There are even three-byte jump and call instructions allowing the destination to be an,l'll'here in the 64K program address space. These primitive operations are automatically cascaded and combined with dedicated logic to build complex instructions such as incrementing a sixteen-bit register pair. To execute one form of the compare instruction. for example. the 8051 increments the program counter three times. reads three bytes of program memory. computes a register address with logical operations. reads internal data memory twice. makes an arithmetic comparison of two variables. computes a sixteen-bit destination address. and decides whether or not to make a branch-all in two microseconds! An important and unique feature of the MCS-51 architecture is that the ALU can also manipulate one-bit as well as eight-bit data types. Individual bits may be set. cleared. or complemented. inoved. tested. and used in logic computations. While support for a more primitive data type may initially seem a step backwards in an era of increasing word length. it makes the 8051 especially well suited for controller-type applications. Such algorithms inherent~1' involve Boolean (true/false) input and output variables. which were heretofore difficult to implement with standard microprocessors. These features are collectively referred to as the MCS-51'· "Boolean Processor." and are described in the so-named chapter to come. The instruction set is designed to make programs efficient both in terms of code size and execution speed. No instruction requires more than three bytes of program memory. with the majority requiring only one or two bytes. Virtually all instructions execute in either one or two instruction cycles-one or two microseconds with a 12-MH7. crystal-with the sole exceptions (multiply and divide) completing in four cycles. Many instructions such as arithmetic and logical functions or program control. provide both a short and a long form for the same operation. allowing the programmer to optimi7.e the code produced for a specific application. The 8051 usually fetches two instruction bytes per instruction cycle. so using a shorter form can lead to faster execution as well. Thanks to this powerful ALU. the 8051 instruction set fares well at both real-time control and data intensive algorithms. A total of 51 separate operations move and manipulate three data types: Boolean (I-bit). byte (8-bit). and address (16-bit). All told. there are eleven addressing modes-seven for data. four for program sequence control (though only eight are used by more than just a few speciali7.ed instructions). Most operations allow several addressing modes. bringing the total number of instructions (operation/addressing mode combinations) to III. encompassing 255 of the 256 possible eight-bit instruction opcodes. For example. any byte of RAM may be loaded with a constant with a three-byte. two-cycle instruction. but the commonly used "working regi~ters" in RAM may be initiali7.ed in one cycle with a two-byte form. Any bit anywhere on the chi p may be set. cleared. or complemented by a single three-byte logical instruction using two cycles. But critical control bits. I/O pins. and software flags may be controlled by two-byte. single cycle instructions. While' three-byte jumps and calls can "go anywhere" in program memory. nearby sections of code may be reached by shorter relative or absolute versions. Instruction Set Overview Table 4 lists these III instructions classified into five groups: AFN-Q1502A-09 2-7 inter AP-69 (MSB) I I Cy '(LSB) AC FO Symbol Position CY PSW 7 RS1 I I RSO Symbol Position Name and Significance OV PSW2 Overflow flag. Set/cleared by hardware during arithmetic instructions to indicate overflow conditions. OV Name and Significance Carry flag. Set/cleared by hardware or software during certain arithmetic and logical PSW.I (reserved) PSWO Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator. i.e .• even parity. Note- the contents of(RSI. RSO) enable the instructions. P AC PSW6 Auxiliary Carry flag. Set/cleared by hardware during addition or subtraction instructions to indicate carry or borrow out of bit 3. FO PSW5 Flag 0 Set/cleared/tested by software as a user-defined status flag. RSI PSW.4 RS PSW.3 working register banks as follows: (0.0) .. Bank (0.1) . Bank (I,O)---Bank (1.1) -Bank Register bank Select control bits I & O. Set/cleared by software to determine working register bank (see Note). 0 I 2 3 (OOH-07H) (OSH-OFH) (IOH-I7H) (ISH-IFH) Figure 4. PSW-Program Status Word Organization A significant side benefit of an instruction set more powerful than those of previous single-chip microcomputers is that it is easier to generate applications-oriented ,software. Generalized addressing modes for byte and bit instructions reduce the number of source code lines written and debugged for a given application. This leads in turn to proportionately lower software costs. greater reliability. and faster design cycles. and rotates. The carry also serves as a "Boolean accumulator" for one-bit logical operations and bit manipulation. instructions. The overflow flag (OV) detects when arithmetic overflow occurs on signed integer operand~, making two's complement arithmetic possible. The parity flag (P) is updated after every instruction cycle with the evenparity of the accumulator contents. The CPU does not control the two register-bank select bits, RS I and RSO. Rather, they are manipulated by software to enable one of the four register banks. The usage of the PSW flags is demonstrated in the Instruction Set chapter of,this Note. Accumulator and PSW The 8051, like its 8048 predecessor, is primarily an accumulator-based 'architecture: an eight-bit register called the accumulator ("A") holds a sour.ce operand and receives the result of the arithmetic instructions (addition. subtraction, multiplication, and division). The accumulator can be the source or destination for logical operations and a number· of special data movement instructions. including table look-ups and external RAM expansion. Several functions apply exclusively to the accumulator: rotates, parity computation, testing for zero, and so on. Even though the architecture is accumulator-based, provisions have been made to bypass the accumulator in common instruction situations. Data may be moved from any location on-chip to any register. address, or indirect address (and vice versa), any register may be loaded with a constant, etc., all without affecting the accumulator. Logical operations may be performed against registers or variables to alter fields of bits-without using or affecting the accumulator. Variables may be incremented, decremented, or tested without using the accumulator. Flags and control bits may be manipulated and tested without affecting anything else. Many instructions implicitly or eXp'licitly affect (or are affected by) several status 'flags, which are grouped together to form the Program Status Word shown in Figure 4. (The period wiihin entries under the Position column is called the "dot operator," and indicates a particular bit position within an eight-bit byte. "PSW.5" specifies bit 5 of the PSW. Both the documentation and ASM51 use this notation.) Other CPU Registers A special eight-bit register ("B") serves in the execution of the multiply and divide instructions. This register is used in, conjunction with the accumulator as the second input operand and to return eight-bits of the result. The mos!'''active'' statuS bit is called the carry flag (abbreviated "C"). This bit makes possible multiple precision arithmetic 6perations including addition, subtraction, The MCS-51 family processors include a hardware stack within internal RAM, useful for subroutine linkage, AFN-01S02A-10 2-8 infef AP-69 passing parameters between routines, temporary variable storage, or saving status during interrupt service routines. The Stack Pointer (SP) is an eight-bit pointer register which indicates the address of the last byte pushed onto the stack. The stack pointer is automatically incremented or decremented on all push or pop instructions and all subroutine calls and returns. [n theory, the stack in the 8051 may be up to a full 128 bytes deep. (In practice, even simple programs would use a handful of RAM locations for pointers, variables, and so forth-reducing the stack depth by that number.) The stack pointer defaults to 7 on reset, so that the stack will start growing up from location 8,just like in the 8048. By altering the pointer contents the stack may be relocated anywhere within internal RAM. are addressed using the Program Counter or instructions which generate a sixteen-bit address. To stretch our analogy just a bit, data memory is like a mouse: it is smaller and therefore quicker than program memory, and it goes into a random state when electrical power is applied. On-chip data RAM is used for variables which are determined or may change while the program is running. A computer spends most of its time manipUlating variables, not constants, and a relatively small number of variables at that. Since eight-bits is more than sufficient to uniquely address 128 RAM locations, the on-chip RAM address register is only one byte wide. [n contrast to the program memory, data memory accesses need a single eight-bit value-a constant or another variableto specify a unique location. Since this is the basic width of the ALU and the different memory . types, those resources can be used by the addressing mechanisms, contributing greatly to the computer's operating efficiency. Finally, a 16~bit register' called the data pointer (DPTR) serves as a base register in indirect jumps, table look-up instructions, and external data transfers. The high- and low-order halves 'Of the data pointer may be manipulated as separate registers (DPH and DPL, respectively) or together using special instructions to load or increment all sixteen bits. Unlike the 8048, look-up tables can therefore start anywhere in program memory and be of arbitrary length. The partitioning of program and data memory is extended to off-chip, memory expansion. Each may be added independently, and each uses the same address and data busses, but with different control signals. External program memory is gated onto the external data bus by the PSEN (Program Store Enable) control output, pin 29. External data memory is read onto the bus by the RD output, pin 17, and written with data supplied from the microcomputer by the WR output, pin 16. (There is no control pin to write external program ROM, which is by definition Read Only.) While both types may be expanded to up to 64K bytes, the external data memory may optionally be expanded in 256 byte "pages" to preserve the use of P2 as an I}O port. This is useful with a relatively small expansion RAM (such as the [ntel® 8155) or for addressing external peripherals. Single-chip controller programs are finalized during the project design cycle, and are not modified after production. [ntel's single-chip microcomputers are not "von Neumann" architectures common among main-frame and miniccomputer systems: the MCS-51 ,. processor dala memory-on-chip and external-may 1101 be used for program code. Just as there is no write-control signal for program memory, there is no way for the CPU to execute instruct-ions out of RAM. [n return, this concession allows an architecture optimized for efficient controller applications: a large, fixed program located in ROM, a hundred or so variables in RAM, and different methoils for efficiently addressing each. Memory Spaces Program memory is separate and distinct from data memory. Each memory type has a different addressing mechanism, different control signals, and a different function. The program memory array (ROM or EPROM), like an elephant, is extremely large and never forgets information, even when power is removed. Program memory is used for information needed each time power is applied: initiali7.ation values, calibration constants, keyboard layout tables, etc., as well as the program itself. The program memory has a sixteen-bit address bus; its elements (Von Neumann machines are.helpful for software development and debug. An 8051 system could be modified to have a single off-chip memory space by gating together the two memory-read controls (PSEN and RD) with a two-input AND gate (Figure 5). The CPU could then write data into the common memory array using W Rand AFN-01S02A-l t 2-9 inter 8051 AP-69 WI! ~ 1miWII} L-_ _ _ I'mi_IIII-I IiEIIliII TO MEMORY ARRAY Figure 5. Combining External Program and Data Memory Arrays external data transfer instructions, and read instructions or data with the AND gate output and data transfer or program memory look-up instructions.) In addition to the memory arrays, there is (yet) another (albeit sparsely populated) physical address space. Connected to the internal data bus are a score of specialpurpose eight-bit registers scattered throughout the chip. Some of these-B, SP, PSW, DPH, and DPL-have been discussed above. Others-I/O ports and peripheral function registers-will be introduced in the following sections. Collectively, these registers are designated as the "special-function register" address space. Even the accumulator is assigned a spot in the special-function register address space for additional flexibility and uniformity. Input/Output Ports The MCS-SI'· I/O port structure is extremely versatile. The 80S1 and 87S1 each have 32 I/O pins configured as four eight-bit parallel ports (PO, PI, P2, and P3). Each pin will 'input or output data (or both) under software control, and each may be referenced by a wide repertoire of byte and bit operations. Thus, the M CS-SI'· architecture supports several distinct "physical" address spaces, functionally separated at the hardware level by different addressing mechanisms, read and write control signals, or both: • .• • • • On-chip program memory; On-chip data memory; Off-chip program memory; Off-chip data memory; On-chip special-function registers. In various operating or expansion modes, some of these I/O pins are also used for special input or output functions. Instructions which access external memory use' Port 0 as a multiplexed address/data bus: at the beginning of an external memory cycle eight bits of the address are output on PO; later data is transferred on the same eight pins. External data transfer instructions which supply a sixteen-bit address, and any instruction accessing external program memory, output the high-order eight bits on P2 during the access cycle. (The 8031 alll'ays uses the pins of PO and P2 for external addressing, but P I and P3 are available for standard I/O.) What the programmer sees, though, are "logical" address spaces. For example, as far as the programmer is concerned,. there is only one type of program memory, 64K bytes in length. The fact that it is formed by combining on- and off-chip arrays (split 4K/60K on the 80S1 and 87S1) is "invisible" to the programmer; the CPU automatically fetches each byte from the appropriate array, based on its address. (Presumably, future microcomputers based on the MCS-SI ,. architecture may have a different physical split, with more or less of"the 64K total implemented on-chip. Using the' MCS-48'· family as a precedent, the 8048's 4K potential program address space was split I K/ 3K between on- and off-chip arrays; the 8049's was split 2KJ2K.) The eight pins of Port 3 (P3) each have a special function. Two external interrupts, two counter inputs, two serial data lines, and two timing control strobes use pIns of P3 as described in Figure 6. Port 3 pins corresponding to functi9ns not used are available for conventional 1/0.Even within a single port, I/O functions may be combined in many ways: input and output may be performed using different pins at the same time, or the same pins at different times; in parallel in some cases, and in serial in others; as test pins, or (in the case of Port 3) as additional special functions. Why go into such tedious details about address spaces? The logical addressing modes are described in the Instruction Set chapter in terms of physical address spaces. Understanding their differences now will payoff in understanding and using the chips later. 2-10 AP-69 (MS8) I I I RD WR (LS8) Tl Symbol Position 1'3.7 RD WR 1'3.6 TO l'Nn I I I I INTO TXD RXD Name and Significance Read data control output. Active low pulse generated by hardware when external data memory is read. Symbol Position INTI 1'3.3 Name and Significance Interrupt I input pin. Low-level or falling-edge triggered. INTO 1'3.2 Interrupt 0 input pin. Low-level or falling-edge triggered. TXD 1'3.1 Transmit Data pin for serial port in Write data control output. Active low pulse generated by hardware when external data memory b wriucn. UART mode. Clock output in shift Tl 1'3.5 Timer/counter I external input or test register mode. pin. RXD TO PH Timer/counter 0 external input or test 1'3.0 Receive Data pin fo'r serial port in UART mode. Data I/O pin in shift register mode. pin. Figure 6. P3-Alternate Special Functions of Port 3 software-accessible). These registers are called. naturally enough. THO. TLO. TH I. and TLI. Each pair may be independently software programmed to any of a d07en modes with a mode register designated TMOD (Figure 7). and controlled with register TCON (Figure 8). The timer modes can be used to measure time intervals. determine pulse widths. or initiate events. with one-microsecond resolution. up to a maximum interval of 65.536 instruction cycles (over 65 milliseconds). Longer delays may easily be accumulated through software. Configured as a counter. the same hardware will accumulate external events at frequencies from D.C. to 500 KHz. with up to sixteen bits of precision. Serial Port Interface Until now, microprocessor systems needed peripheral chips such as timer/counters. USARTs. or interrupt controllers to meet these needs. The 8051 integrates all of these capabilities on-chip! Each microcomputer contains a high-speed, full-duplex. serial port which is software programmable to function in' four basic modes: shift-register I/O expander. 8-bit UART. 9-bit UART. or interprocessor communications link. The UART modes will interface with standard I/O devices (e.g. CRTs. teletypewriters. or modems) at data rates from 122 baud to 31 kilobaud. Replacing the standard 12 MHz crystal with a 10.7 MHz crystal allows 110 baud. Even or odd parity (if desired) can be included with simple bit-handling software routines. Inter-processor communications in distributed systems takes place at 187 kilobaud with hardware for automatic add.ress/data message recognition. Simple TTL or CM OS shift registers provide low-cost I/O expansion at a super-fast I Megabaud. The serial port operating modes are controlled by the contents of register SCON (Figure 9). Timer/Counters Interrupt Capability and Control There are two sixteen-bit multiple-mode Timer/Counters on the 8051. each consisting of a "High" byte (corresponding to the 8048 "T" register) and a low byte (similar to· the 8048 prescaler. with the additional flexibility of being (Interrupt capability is generally considered a CPU function. It is being introduced here since. from an applications point of view, interrupts relate more closely to peripheral and system interfacing.) Special Peripheral Functions There are a few special needs common among controloriented computer systems: • keeping track of elapsed real-time; • maintaining a count of signal transitions; • measuring the precise width of input pUlses; • communicating with other systems or people; • closely monitoring asynchronous external events. AFN-01S02A-13 2-11 AP-69 (MSB) I GATE (LSB) I I CIT M1 MO I GATE I CIT M1 MD I M1 MO o o ~\ TIMER 1 Operating Mode MCS-48 Timer. "TLx" serves as fivebit prescaler. TIMER 0 o 16-bit timer· counter. "THx" and "TLx" are cascaded~ there is 'no presca'ier. o GATE Gating control. When set, Timer/counter "x"·is enabled only while "INTx" pin is high and "TRx" control bit is set. When cleared, timer/counter is enabled whenever "TRx" control bit is set. CjT Timer or Counter Selector. Cleared for Timer operation (input from internal system clock). Set for Counter operation (input from "Tx" input pin). 8-bit auto-reload timer counter. "THx" holds a value which is to be reloaded into ··TLx·· each time it overflows. (Timer 0) TLO is an eight-bit timer counter controlled bv the standard Timer 0 co~trol bits. . THO is an eight-bit timer only controlled by Timer I control bits. (Timer I) Timer,counter I stopped. Figure 7. TMOD-Timer/Counter Mode Register (MSB) I TF1 I TR1 TFO I (LSB) TRO IE1 IT1 lEO I ITO Symbol Position Name and Significance lEI TCON.3 Interrupt I Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Symbol Position Name and Significance TFI TCON.7 Ti.mer I overflow Flag. Set by hardware on timer/counter overflow. Cleared when interrupt processed. TRI TCON.6 Timer I Run control bit. Set/cleared by software to turn timer/counter on/off. TFO TCON.5 Timer 0 overflow Flag. Set by hardware on timer/counter overflow. Cleared when interrupt processed. TRO TCON.4 Timer 0 Run control bit. Set/cleared by software to tUTn timer/counter on/off. ITI TCON.2 Interrupt I Type control bit. Sct cleared by software to specify falling edge low level triggered external interrupts. I Ell TCON.I Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. ITO TCON.O Interrupt 0 Type control bit. Set 'cleared by software to specify falling edge low level lriggered external interrupts. Figure 8. TCON-Timer/Counter Control/Status Register AFN-01502A-14 2-12 AP-69 Symbol Posillon Name and Significance Symbol Position Name and Significance SMO SCON.7 Serial port Mode control bit O. Sct/cleared by software (sce note). RB8 SCON.2 Receive Bit 8. Set/c1cared by hardware to indicate stale of ninth data bil SMI SCON.6 Serial port Mode control bit I. Set/cleared by software (see note). TI SCON.I Scrial port Modc control bit 2. Set by softwarc to disable reception of frames for which bit 8 is zero. Transmit Intcrrupt flag. Set by hardware when byte transmitted. C1cared by software after servicing. RI SCON.O Received Inlerrupt flag. Set by hardware when byte received. Cleared by Note- the state of (SMO.SM I) "Ieets: (0,0) --Shift register 110 expansion (0.1)·-8 bit UART. variable data rate. (1.0)--9 bit UART. fixed data rate. (1.1)--9 bit UART. variable data rate. received. SM2 REN TB8 SCON.5 SCON.4 SCON.3 Receiver Enable control bit. Set/clcared by software to enable/disable serial data reception. software after servicing. Transmit Bit 8. Set/clcared by hardware to determine state of ninth data bit transmitted in 9-bit UART modc. Figure 9. SCON-Serial Port Control/Status Register These peripheral functions allow special hardware to monitor real-time signal interfacing without bothering the CPU. For example, imagine serial data is arriving from one CRT while being transmitted to another, and one timer/counter is tallying high-speed input transitions while the other measures input pulse widths. During all of this the CPU is thinking about something else. But how does the CPU know when a reception, transmission, count, or pulse is finished? The 8051 programmer can choose from three approaches. TCON and SCON contain status bits set by the hardware when a timer overflows or a serial port operation is completed. The first technique reads the control register into the accumulator, tests the appropriate bit, and does a conditional branch based on the result. This "polling" scheme (typically a three-instruction sequence though additional instructions to save and restore the accumulator may sometimes be needed) will surely be familiar to programmers used to multi-chip microcomputer systems and peripheral controller chips. This process is rather cumbersome, especially when monitoring multiple peripherals. background task long enough to handle the appropriate device, then return to the point where it left off. This is the basis of the third and generally optimal solution, hardware interrupts. The 8051 has five interrupt sources: one from the serial port when a transmission or reception is complete, two from the timers when overflows occur, and two from input pins INTO and INTI. Each source may be independently enabled or disabled to allow polling on some sources or at some times, and each may be classified as high or low priority. A high priority source can interrupt a low priority service routine; the manager's boss can interrupt conferences with subordinates. These options are selected by the interrupt enable and priority control registers, IE and IP . (Figures 10 and II). Each source has a particular program memory address associated with it (Table 3), starting at 0003H (as in the 8048) and continuing at .eight-.byte intervals. When an event enabled for interrupts occurs the CPU automatically executes an internal subroutine call to the corresponding address. ·A us_er subroutine starting at this location (or jumped to from this location) then performs the instructions to service that particular source. After completing the interrupt service routine, execution returns to the background program. As a second approach, the 8051 can perform a conditional branch based on the state of any control or status bit or input pin in a single instruction; a four instruction sequence could poll the four simultaneous happenings mentioned above in just eight microseconds. Table 3. 8051 Interrupt Sources and Service Vectors Unfortunately, the CPU must still drop what it's doing to test these bits. A manager cannot do his own work well if he is continuously monitoring his subordinates; they should interrupt him (or her) only when they need attention or guidance. So it is with machines: ideally, the CPU would not have to worry about the peripherals until they require servicing. At that time, it would postpone the Interrupt Source Service Routine Starling Address (Reset) External 0 Timer/Counter 0 External I Timer/ Counter I Serial Port OOOOH 0OO3H OOOBH OOl3H OOIBH 0023H AFN-01502A-1S 2-13 inter AP-69 IMSB) ILSB) ES ET1 EX1 ETO I EXO I Symbol Position Name and Significance EA IE.7 Enable All control bit. Cleared by software to disable all interrupts. independent of the stale of IE.4-IE.O. ES ETI Symbol Position Name and Significance EXI IE.2 Enable External interrupt I control bit. Set cleared by software to enable disable interrupts from INTI. IE.6 IE.5 (reserved) (reserved) ETO IE.I Enable Timer 0 control bit. Set cleared by software to enable disable interrupts from timer counter 0 IE.4 Enable Serial port control bit. Set/cleared by software to enable disable interrupts from TI or RI flags. EXO IE.O Enable External interrupt 0 control bit. Set cleared by software to enable disable interrupts from INTO. IE.3 Enable Timer I control bit. SeUcieared by software to enable/disable interrupts from timer/counter I. Figure 10. IE-Interrupt Enable Register IMSB) I- ILSB) PS 1 Symbol Position IP.7 IP.6 IP.5 PS PTI IP.4~ JP.3 PT1 I, px, 1PT. I px. I Name and Significance (reserved) (reserved) (reserved) Symbol POSition Name and Significance PXI IP.2 External interrupt I Priority control bit. Set cleared by software to specify high low priority interrupt, for INTI. Serial port Priority control bit. Set/cleared by software to specify high/low priority interrupts for Serial port. PTO Timer I Priority control bit. Set/cleared by software to specify high/low priority interrupts for timer/counter I. PXO IP.I Timer 0 Priority control bit. Set cleared by software to specify high low priority interrupts for timer counter O. IP.O External interrupt 0 Priority control bit. Set cleared by software to specify high low priority interrupts for INTO. Figure 11. IP-Interrupt Priority Control Register AFN-OtS02A-16 2-14 inter AP-69 Table 4. MCS-51'" Instruction Set Description DATA TRANSFER (conI.) ARIIIIMHIC OPERA1IONS !\tnernnnic .\1))) A.Rn AIlD ·\.dITCct A.lQ1RI ADD AD)) .\.udJta AnnC '\.Rn ADDC A.dlrcct A))))C ·\.Ca1 RI ,\nlle ,\.Ud.II.1 SllBB A.Rn SllHB '\,dm:cl SllBB A.@'Ri A)tdata SUnB A I"C I'\;C Rn direct I'C (a\RI I'\C me mc I)fT !lIT I'\;C .\1(11 I>IV J):\ A Rn dllect ~I\RI DPI R AI! AU A I),,\cription Add rcgl'lcf 10 Ac,"umul.llnT Add dlreCl tntc 1U ,\n.'UIl1Ulalor Add mUlrcct"RA\11ll Acculllul,l(nr Add Immcdl:!lC data tn Accumulator Add regl~tcr to Accumulatnr vdth c.lrr) Add direct h~(c (() A "Ith c.!rr~ n.lg Add mdm'ct R,\ M III A \Hlh c.trr~ flenement ,\n:ulllul.llor Decrement reg"ter Decrement due!:t b\le Dc!:remcnt Indlrct:,'RAM Im'rement Daw P(lmter Mu!tlpl~ A & B 1l1\ldc A h\ B Ilct:llllal Adlu,t Accumulator Byte C)C I I I I I I I I I I I I Or..tinatiun A'\;i) rel!l~ler to Accut1lul.llor A .....·f) dl;eci h\le to Accumulator " . . .·1> Indlrect'RAM In Accurnul.ltor MOVX (wDPI R.A PliSH POP XCH direct direct A.Rn XCH XCH A,dlrt'c! A.@lR, X('HI) A.@lRI 8~te ('~c I I I I I I ASD Immediate datil to Accul\lul.tlnr A \;D AccuTl1ulator 10 direct b\'le A 'iD Immedl..lte datJ to dln!ci byte OR rt:gl~tt'r tll Accumulator OR dm.'ct h\te to Accumul..llor OR mdlrelt'RAM to Accul\lul... I<)f OR Imrncdl.Jle data 10 Act:umulator OR Accumulator to dIrect h\'tc OR Immcdlatc dat.1 to dlrcct h\ tc Exc!u,,\e-OR rCJP~t~'r 10 AClllmuJatnr Exclu'-I\e-OR duect h\le to Accumulator Exciu"\e-OR IndirecI'RAM to A Exclu~l\e-OR Immediate data to A E'{clu~l\e-()R Accumulator 10 dlrccl b\te E'(clu~ne-OR zmmcc.llate data to dlrec! Clear Accumulator Complement Accumulator Ro{att· Accumulator I cit Rotale A I.ef! through the Carr) nag Rotate Accumulator Right Rolate A Right through Cany nag Swap mhhlc' Within the Accumulator Oe ..cription M()\e regl~ter to Accumulator Mtl\e direct b\'te to Accunmlalor M(J\e inum:cl'RAM 10 Accumulaltlr MO\t! lmmedlale d.lta to Accumuloltor Mo\e Accumulator \l) Icg"tel Mo\e direct h~\c 10 reg"lef Mo\e Immcdl.Jte Juta 10 regl,ler Mme Accumulator 10 d!r~'c! h~le Mine regl ..tef to direct hyle Mo\t! direct h\'te to dIrect Mo\e Indlrcct'RAM to direct b\tc M(l\e ImmedlJlc data to dllecl inte M(He Accumulator to mdllecl IfAM M<)\c dlfect h\te to mdlrect RAM MO\e Immedl:ltc data III mdlrect RAM I.oad Data Pmnter wllh a ](I-blt comtant De..eriplion Clear ('arr~ nag Clear direct hu Set Cm~ !lag Sel direct BII Cumplement Carr~ tlJg Complt'ment dln:ct hll A'\; I) direct bll to C;.rr~ IIJ!,! A '\;1> wmpkment ul dlfect hl1to Colrr~ OR direct hll ttl CJrr~ nag OR cmnplemcTlt 01 direct hit tn Carr~ Mmc e ..criprion Subroutine ('a11 long: Suhroulllle ('.til Return from ~uhroutlllt: Return trnm mtcrrupt Ah,olute .lump IOl1g.l um r Shorl .lump (relatne Jddr) Jump IIldlfect rc\atl\e 10 the DPT R Jump 11 Accumulalor" Zero .lump II A<:cumulalnr l\ "I;tlt Zero Jump II C.. rr:. nag" ~et .lump II !'io ('arr~ flag .lump J! dlreCI Bit ~et .lump d dlfect Bit \l"ot ,et Jump tI direct Hit 1\ ~et & Ck.. r hll Compare direct 10 A & .lump II :"oiot Equal CUTlIP Immed to A & Jump If '\;ot Equal Comp Immed tu reg & Jump If "iol Equal Comp Immed In Ind & Jump if :\lot Equal Decrcment reg,,,[er & Jumr If '\;01 Zero l>ecremenl direct & .lum" II '\;ot I.ero 'n nper.llllln "h~olult' data addre.... in~ mode.. : Wnfl.lng reg"ter RO R 7 12X Inlern:iI RAM locatlon~, an~ I 0 port. conlrol or ~Iatu~ rcgl~ter Inthrectilltermt! RAM iocatlUn addre~~ed h~ reg"ter RII or RJ X-bit cnn,tJnt mduded In in,tructlllll 16-hll con~tant mduded a~ h\te~ ~ &.' of In~tructmn 12X ,ottv.arc nag~. an~ I 0 pm. conlrol or ,{.tIU, hl\ 'op I I I I I ,I :\'ote" un Rn dITecl (a)RI ;idata #datal!l hit C.I~E I 2 I I I I I I 1l.l",Z f).I'Z C.I'\E eJ",E C)C ()c rei hlud hll.rcl bll.rel A.d.rect.rd A.*'dJla.ld Rn.udata.rel (wRI.#data.rel Rn.rel dlrel.'t.rel .IB .I",n .I Be CJ'\;F. 8)te B)te I PROGRAM A:'On MAClII:'OI: CONTROL [)AT·\ TRA \;~FER VJnemunic 'l0V A,Rn MOV A.l.llrect M()V A.(aIRI MOV \.tidala \10V Rn.A MOV H,n.dlfect \10\' Rn.*'d.II.1 MOV dlfCCt.A ."-IO\' dlrcct.Rn \1()V dllcct.dlrect dlrect,(,alRI MOV MOV I.hrect.tidata (aIRI.A MOV (a1Rz,dlrect MOV M()V «(lIRI.tidat •• MOV IlP I R.#datll l!l De\cription B)le (')'C MIne Code hvtc reiatl\C to [)PfR 10 A I 2 \10\C Code ",Ie rclatl\C to PC In A I Mmc E'I(,lcro.il RAM (1(·011 dddrlin A I Mmc E'(lcrn,J1 RAM (16·bn addr) to A I MO\~' A In E,lernoil RAM (H-hLt aodr) I Mmc A ttl r,lcrnal RAM (16-bll addr) I Pu,h direct tl\ Ie onto ,lac\.. Pop dIrect h~ic ]rom ,tad.. [,(change rcg.'\l'r "11h Accumulalm F,(changt' direct h~lc "11h AccumulalOr E'(changc mdlrect RAM '\dlh A Exch.angl' hl\\-nrdcr DIg:lIlnU RAM .... A 8()()I.EAN VARIARU: .I\IASIPt·I.ATlON I.O(;iCAI. OPERATIONS :\Inernonic A\;I A.Rn A'\; 1 A,dlrecl A\;/. A.@RI A\;I A.Mata A\;L dlrect.A A'\; 1 dlrect.#data ORI A.Rn ORI A.dlrect A,@JRI ORI A.#data ORI ORI duec1.A dlrec\.*tdata ORI XRI A.Rn XRI A.dlfl'cl A.(fURI .xRI XRI A.*"data xRI t.hrect.A dlrect.#dala .XRI CI R A CPI ~ RI A RIC A A RR A RRe SWAP A Mnemonic MOVe A.CWA+DP"J R Move A.@A+I'C MOVX A.@lRo MOVX A.@IJPrR MOVX @RJ.A J :'\iote.. on program addre....in2 mode .. : addrl!l De'tlTl.ltmn addre~~ tm I CAlI & I.lMP ma\ he otll\v.here "!lhm the M-Kllnh~tl' prngrJm memnr~ Jddrc" ~pac~" . addrll De~t1natHln addre .. , for ACAI I & A.lMP "II! rn: "!thm tht' 'arne 2-Klioh)IC pa!!t· 01 program m~'mor~ a, the tIT" h~le 01 the Inlhmlng IIl~trLlctltln rei All 3. INSTRUCTION SET AND ADDRESSING MODES S.lMP and all condillonJI tump~ mdude an X-hll ott,et h~,e R.Jn~e + 127 12X h~le, rel,ltl\C to flr,t byte 01 the fnllnv.mg lil,tructllln mnemonlc~ I~ copynghted © Intel Corpnralmn 1979 group. this chapter starts with the addressing mode classes and builds 10 include the related instructions. The 8051 instruction set is extremely regular. in the sense that most instructions can operate with variables from several different physical or logical address spaces. Before getting deeply enmeshed in the instruction sct proper. it is important to understand the details of the most common data addressing modes. Whereas Table 4 summari7es Ihe instructions set broken down by functional Data Addressing Modes MCS-51 assembly language instructions consist of an operalion mnemonic and 7ero to three operands separated by commas. In two operand instructions the destination is specified first. then the source. Many byte-wide data AFN·01502A-17 2-15 inter AP-69 . operations (such as ADD or MOV) inherently use the accumulator as a source operand and/or to receive the result. For the sake of clarity the letter "A" is specified in the source or destination field in all such instructions. For example, the instruction, ADD hardware reset enables register bank 0; to select a different bank the programmer modifies PSW bits 4 and 3 accordingly. Example 2-Selecting Alternate Memory B.anks PSW ••000100008 A. will add the variableto the accumulator, leaving the sum in the accumulator. Register addressing in the 8051 is the same as in the 8048 family, with two enhancements: there are four banks rather than one or two, and 16 instructions (rather than 12) can access them. The operand designated "" above may use any of four common logical addressing modes: • Register-one of the working registers in the currently enabled bank. • Direct-an internal RAM location, I/O port, or special-function register. • Register-indirect-an internal RA M location, pointed to by a working register. • Immediate data-an eight-bit constant incorporated into the instruction. Direct Byte Addressing Direct addressing can access anyon-chip variable or hardware register. An additional byte appended to the opcode specifies the location to be used (Figure 12.b). Depending on the highest order bit of the direct address byte, one of two physical memory spaces is selected. When the direct address is between 0 and 127 (00H-7FH) one of the 128 low-order on-chip RAM locations is used. (Future microcomputers based on the MCS-51'· architecture may incorporate more than 128 bytes of on-chip RAM. Even if this is the case, only the low-order 128 bytes will be directly addressable. The remainder would· be accessed indirectly or via the stack pointer.) The first three modes provide access to the internal RA M and Hardware Register address spaces, and may therefore be used as source or destination operands; the last mode accesses program memory and may be a source operand only. (It is hard to show a "typical application" of any instruc- tion without involving instructions not yet described. The following descriptions use only the self-explanatory ADD and MOV instructions to demonstrate how the four addressing modes are specified and used. Subsequent examples will become increasingly complex.) Example 3 - Adding RA M Location Contents .DIRADR ADD CONTENTS OF RAM LOCATION 41H TO CONTENTS OF RAN LOCATION 40H OIRADR ADD MOV The 8051 programmer has access to eight "working registers," numbered RO-R 7. The least-significant three-bits of the instruction. opcode indicate one register within this logical address space. Thus, a function code and operand address can be combined to form a short (one byte) instruction (Figure 12.a). The 805 I assembly language indicates register addressing with the symbol Rn (where n is from 0 to 7) or with a symbolic name previously defined as a register by the EQUate or SET directives. (For more information on assembler directives see the Macro Assembler Reference Manual.) Example PRTADR • REGAO~ ADD CONTENTS OF REGISTER 1 TO CONTENTS OF REGISTER (] MOV A. RO A, RI flO. A 4-Adding Input Port Data to Output Port Data . ,PRTADR ADD DATA INPUT ON PORT J TO DATA PREVl'OUSLY OUTPUT ON PORT (] Example I-Adding Two Registers Together ADD Mav 40H. A All I/O ports and special function, control, or status registers are assigned addresses between 128 and 255 (80H-OFFH). When the direct address byte is between these limits the corresponding hardware register is accessed. For example, Ports 0 and I are assigned direct addresses 80H and 90H, respectively. A complete list is presented in Table 5. Don't waste your time trying to memorize the addresses in Table 5. Since programs using absolute addresses for function registers would be difficult to write or understand, AS M51 allows and understands the abbreviations listed instead. Register Addressing REGADR • SELECT BANI!. :2 MOV A, PO ADD A. PI MOV PO. PI Direct addressing allows all special-function registers in the 8051 to be read, written, or used as instruction operands. In general, this is the only method used for accessing I/O ports and special-function registers. Ifdirect addressing is used with special-function register addresses other th(ln those listed, the result of the instruction is undefined. There are four such banks of working registers, only one of which is active at a time. Physically, they occupy the first 32 bytes of on-chip data RAM (addresses 0-1 FH). PSW bits 4 and 3 determine which bank is active. A AFN-01502A-1a 2-16 AP-69 The 8048 does nOl haye or need any generali/ed direct addressing mude. since there arc only five special registers (BUS. PI. P2. PSW. & T) rather than twenty. Instead. 16 special 8048 opcodes control output bits or read or write each register to the accumulator. These functions arc all subsumed by four of the 27 direct addressing instructions of the 8051. Indirect addressing on the 805 I is the same as in the 8048 family. except that all eight bits of the pointer register contents are significant; if the contents point to a nonexistent memory location (i.e .. an address greater than 7FH on the 8051) the result of the instruction is undefined. (Future microcomputers based on the MCS-5I'· architecture could implement additional memory in the on-chip RAM logical address space at locations above 7FH.) The 8051 uses register-indirect addressing for five new instructions plus the 13 on the 8048. Table 5. 8051 Hardware Register Direct Addresses Register Address KOH* KI H K2H H.'H HHH* H9H HAH KBH XCH HDH 90H* 9XH* 99H OAOH* OAXH* OBOH* OBXH* ODOH* OEOH* OFOH* 1'0 SP 1>1'1. DPH 'ICO~ TMOD 11.0 11.1 rHO rHI 1'1 SCO:'>: SHliF P2 IF 1'.' II' PSW ACe B Function Port 0 Immediate Addressing Stack Pointer Data Pointer (l.ow) Data Pointer (High) When a source operand is a constant rather than a variable (i.e. ~·the instruction uses a value known at assembly time). then the constant can be incorporated into the instruction. An additional instruction byte specifics the value used (Figure 12.d). Timer register Timer Mode register Timer 0 Timer I Timer 0 Timer I Port I Low byte Low byte High byte High byte Port 3 The value used is fixed at the time of ROM manufacture or EPROM programming and may not be altered during program execution. In the assembly language immediate operands are preceded by a number sign ("II"). The operand may be either a numeric string. a symbolic variable. or an arithmetic expression using constants. I ntcrrupt Prionty rcgi~ter Program Statu~ Word Example Serial Port Control regi~ter Serial Port data Buffer Port 2 Interrupt Enable regi!ttcr Accumulator (direct addre,,) B rcgi!tter 6 -~ Adding Constants Using Immediate Addressing • IMMADR ADO THE CONSTANT 12 IDECIMAL) TO THE CONSTANT 34 (DECIMAL) LEAVE SUM 1N ACCUMULATOR • = hit addn:v.. :'lhlc: rcgl\lCr IMMADR MOV A •• 12 A. _34 Register-Indirect Addressing The preceding example was included for consistency; it has little practical value. Instead. ASM51 could compute the sum of two constants at assembly time. How can you handle variables whose locations in RAM arc determined. computed. or modified while the program j; running? This situation arises when manipulating se4uential memory locations. indexed entries within tables in RAM. and mUltiple precision or string operations. Regi,ter or Direct addressing cannot be used. since their operand addresses are fixed at assembly time. Example ,ASMSUM LOAD ACC WITH THE SUM OF THE CONSTANT 12 (DECIMAL) AND THE CONSTANT 34 (DECIMAL) ASMSUM The 8051 solution is "register-indirect RAM addressing:' RO and R I of each register bank may operate as index or pointer registers. their contents indicating an address into RAM. The internal RAM location so addressed is the actual operand used. The least significant bit of the instruction opcode determines which register is used as the "pointer" (Figure 12.c). ADD A,R b.) Direct AddreSSing: I : : >+.: ADD A. : : /I : >+.++< : I direct c.) Register-Indirect Addressing: I : : +.+ ADD Example 5 -I ndirect Addressing : : I; I A.@R d.) Immediate Addressing: I : : >+.: . INOAOR ADD CONTENTS OF MEMORY LOCATJON ADDRESSED BY REGISTER 1 TO CONTENTS OF RAM LOCATION ADDRESSED av REGISTER 0 MOV ADD MOV MCV a.) Register Addressing: In the 8051 assembly language. register-indirect addressing is represented by a commercial "at" sign ("@") preceding RO. R I. or a symbol defined by the user to be e4ual to RO or R I. tNDADR 7 -Adding Constants Using ASM5 I Capabilities ADD A. @Rl : : II A.# : : :-~..: : : I data Figure 12. Data Addressing Machine Code Formats +.: : : Secondly, the interrupt logic is disabled from accepting any other interrupts from the same or lower priority. After completing the interrupt service routine, executing an RETI (Return from Interrupt) instruction will return execution to the point where the background program was interrupted -- just like RET ~ while restoring the interrupt logic to its previous state. c.) Short Jump (SJMP rei): 1 : : II.-.I_ , e l . _ .. " OI_I.el- - - ' Figure 15. Jump Instruction Machine Code Formats AFN-Ot502A-23 2-21 AP-69 Operate-and-branch instructions - CJNE, DJNZ Two groups of instructions combine a byte operation with a conditional jump based on the results. CJNE (Compare and Jump if Not Equal) compares two byte operands and executes a jump if they disagree. The carry flag is set following the rules for subtraction: if the unsigned integer value of the first operand is less than that of the second it is set; otherwise. it is cleared. However. neither operand is modified. The dollar sign in this example is a special character meaning "the address of this instruction." It is useful in eliminating instruction labels on the same or adjacent source lines. CJNE and DJNZ (like all .conditional jumps) use program-counter relative addressing for the destination address. Stack Operations - PUSH, POP The PUSH instruction increments the stack pointer by one. then transfers the contents of the single byte variable indicated (direct addressing only) into the internal RA M location addressed by the stack pointer. Conversely. POP copies the contents of the internal RAM location addressed by the stack pointer to the byte variable indicated. then decrements the stack pointer by one. The C.INE instruction provides. in effect. a oneinstruction "case" statement. .This instruction may be executed repeatedly. comparing the code variable to a list of "special case" value: the code segment following the instruction (up to the destination label) will be executed only if the operands match. Comparing the accumulator or a register to a series of constants is a convenient way to check for special handling or error conditions; if none of the cases match the program will continue with "normal" processing. (Stack Addressing follows the same rules. and addresses the same locations as Register-indirect. Future microcomputers based on the MCS-51 ,. CPU could have up to 256 bytes of RAM for the stack.) A typical example might be a word processing device which receives ASCII characters through the serial port and drives a thermal hard-copy printer. A standard routine translates "printing" characters to bit patterns. but control characters «DEL>' . . . ·. orvalue. ~OH. and processed with the printing characters. Interrupt service routines must not change any variable or hardware registers modified by the main program. or else the program may not resume correctly. (Such a change might look like a spontaneous random error.) Resources used or altered by the service routine (Accumulator. PSW. etc.) must be saved and restored to their previous value before returning from the service routine. PUSH and POP provide an efficient and convenient way to save register states on the stack. Example 16-Case Statements Using CJNE Example 18 - Use of the Stack for Status Saving on Interrupts R7 CHAR INTERP CJNE INTP RET CJNE • CHARACTER. CODE VARIABLE CHAR. '7FH. INTP __ 1 L.OC_TMP EQU • REMEMBER LOCATION COUNTER (SPECIAL ROUTINE FOR RUDOUT CODE) -I OR. CHAR. tIo07H. INTP __2 (SPECIAL ROUTINE FOR BELL CODE) L.JI'1P 0003H SERVER • STARTING ADDRESS FOR INTERRUPT ROUTINE ,.JUMP TO ACTUAL SERVICE ROUT INE LOCATEU RET INTP _2 C"'NE INTP _:3 RET CJNE CHAR. 4tOAH. INTP __3 OR. (SPECIAL ROUTINE FOR L.FEED CODE) SERVER INTP - 4 tNTP - • INTP _6 RET CJNE RET CJNE psw PUSH PUSH PUSH B CHAR. IODH. INTP_4 <:)OH • NULL CODE POP POP • PROCESS STANDARD PRINTING , CHARACTER RETI RET DJNZ (Decrement and Jump if Not Zero) decrements the register or direct address indicated and jumps if the result is not zero. without affecting any flags. This provides a simple means for executing a program loop a given number of times. or for adding a moderate time delay (from 2 to 512 machine cycles) with a single instruction. For example. a 99-usec. software delay loop can be added to code forcing an 110 pin low with only two instructions. ACC • SAVE ACCUMUL.ATOR (NOTE DIRECT ADDRESSING , NOTATION) • SAVE B REGISTER DPL • SAVE DATA POINTER DPH , PSW, '0000100013 • SELECT REGISTER IlANK 1 OPH DPL B ACC psw ,RESTORE REGISTERS IN REVERSE ORnER · RESTORE PSW AND RE-SELE'CT OR IGINAL. , REGISTER BANK · RETURN TO MAIN PROGRAM AND RESTORE • INTERRUPT L.OGIC If the SP register held I FH when the interrupt was detected. then while the service routine was in progress the stack would hold the registers shown in Figure 16; SP would contain 26H. The example shows the most general situation; if the service routine doesn't alter the B-register and data pointer. for example. the instructions saving and restoring those registers would not be necessary. The stack may also pass parameters to and from subroutines. The subroutine can indirectly address the parameters derived from the contents of the stack pointer. Example 17-lnserting a Software Delay with DJNZ CL.R 1'10V D.JNZ SETB L.OC_TMP ,RESTORE L.OCATION COUNTER PUSH PUSH WR R2, .49 R2." WR AFN-01S02A-24 2-22 AP-69 If the position of the motor is determined by the contents of variable POSM I (a byte in internal RAM) and the position of a second motor on Port 2 is determined by the data input to the low-order nibble of Port 2. a sixinstruction sequence could update them both. RAM ADDR 7FH 26H OPH 25H OPL 2.H " 23H POSI11 ACC 22H PSW 21H PC (HIGH) 20H PC (LOW) .ou 51 PUSH CALL POSI11 NXTPOS POP PI P' PUSH CALL pap IFH NXTPOS P2 Data Pointer and Table Look-up instructions MOV, INC, MOVC, JMP DOH Figure 16. Stack contents during interrupt One advantage here is simplicity. Variables need not be allocated for specific parameters. a potentially large number of parameters may be passed. and different calling programs may use different techniques for determining or handling the variables. For example. the following subroutine reads out a parameter stored on the stack by the calling program. uses the low order bits to access a local look-up table holding bit patterns for driving the coils of a four phase stepper motor. and stores the appropriate bit pattern back in the same position on the stack before returning. The accumulator contents are left unchanged. Example 19 - Passing Variable Parameters to Subroutines Using the Stack NXTPOS Example 21 - Loading and Unloading Stack Direct from 1/0 Ports ..-(SP) MOV DEC DEC RO. SP XCH A.@RO ANL ADO A •• 2 Move A. C!A .... PC ,READ LOOK-UP TABLE ENTRY • ACCESS LOCATION PARAMETER PUSHED INTO The data pointer can be loaded with a 16-bit value using the instruction MOV DPTR. #dataI6. The data used is stored in the second and third instruction bytes. highorder byte first. The data pointer is incremented by INC DPTR. A 16-bit increment is performed; an overflow from the low byte will carry into the high-order byte. Neither instruction affects any flags. The MOVC (Move Constant) instructions (MOVC A.@A+DPTR and MOVC A.@A+PC) read into the accumulator bytes of data from the program memory logical address space. Both use a form of indexed addressing: the former adds the unsigned eight-bit accumulator contents with the sixteen-bit data pointer register. and uses the resulting sum as the address from which the byte is fetched. A sixteen-bit addition is performed; a carry-out from the low-order eight bit, may propagate through higher-order bits. but the contents of the DPTR are not altered. The latter form uses the incremented program counter as the "base" value instead of the DPTR (figure 17). Again. neither version affects the flags. • READ INPUT PARAMETER AND SAVE • ACCUMULATOR ,MASK ALL nUT LOW-ORDER TWO BITS • ALLOW FOR OFFSET FROM Move TO TABLE • PASS BACK TRANSLATED VALUE MOVC A @ A + PC (LOCAL TABLE LOOK-UP) a) AND RESTORE · Ace RET 5TPTBL DB D. D. D. • RETURN TO BACJI,GROUND PROGRAM 0110111113 ,POSITION 0 010111l1B 10011111B lO1011l1B ,POSITION 1 • POSITION 2 ,POSITION 3 b) A Ace NXTPOS PI PC ~ACC MOVC A @l A+ DPTR (GLOBAL TABLE LOOK-UP) 16-81T I c) JMP @ A+ OPTR (GLOBAL INDIRECT JUMP) ~~~~~I~~RESS DPTR ~ACC ,-___'_6-_B'..!,T.J1 Example 20-Sending and Receiving Data Parameters Via the Stack CALL PDP I ' -_ _ _'6_-_"_,_T..1 The background program may reach this subroutine with several different calling sequences. all of which PUSH a value before calling the routine and POP the result after. A motor on Port I may be initialized by placing the desired position (zero) on the stack before calling the subroutine and outputing the results directly to a port afterwards. PUSH 16-BIT 16-81T ~~~~~~~RESS 1 OPTR ~ACC ' -_ _ _'_6-_6'_T..) LOADED INTO PC Figure 17. Operation of MOVC instructions AFN-01S02A-2S 2-23 AP-69 Each can be part of a three step sequence to access lookup tables in ROM. To use the DPTR-relative version . . load the Data Pointer with the starting address ofa lookup table; load the accumulator with (or compute) the index of the entry desired; and execute MOVC A.@A+DPTR. Unlike the similar MOVP3 instructions in the 8048. the table may be located anywhere in program memory. The data pointer may be loaded with a constant for short tables. Or to allow more complicated data structures. or tables with more than 256 entries. the values for DPH and DPL may be computed or modified with the standard arithmetic instruction set. The PC-relative version has the advantage of not affecting the data pointer. Again. a look-up sequence takes three steps: load the accumulator with the index; compensate for the offset from the look-up instruction to the start of the table by adding the number of bytes separating them to the accumulator: then execute the MOVC A.@A+PC instruction. Let's look at a non-trivial situation where this instruction would be used. Some applications store large multidimensional look-up tables of dot matrix patterns. nonlinear calibration parameters. and so on in a linear (onedimensionali) vector in program memory. To retrieve data from the tables. variables representing matrix indices must be converted to the desired entry's memory address. For a matrix of dimensions (MDIMEN x NDIMEN) starting at address BASE and respective indices INDEX I and INDEXJ. the address of clement (INDEX!. INDEXJ) is determined by the formula. Entry Address = BASE + (NDIMEN x INDEXI) + INDEXJ The code shown below can access any array with less than 255 entries (i.e .. an IIx21 array with 231 elements). The table entries are defined using the Data Byte ("DB") dire~tive. and will be contained in the assembly object code as part of the accessing subroutine itself. There are several different means for hranching to sections of code determined or selected at run time. (The single destination addresses incorporated into conditional and unconditional jumps, are. of course. 'determined at assembly time). Each has ad\'antages for different applications. The most common is an N-way conditional jump based on some variable. with all of the potential destinations known at assembly time. One of a numb~r of small routines is selected according to ,the \'alue of an index variable determined while the program is running. The most efficient way to solve this problem is \\ ith the MOVe and an indirect jump instruction. ming a short table of one byte offset values in ROM to indicate the relative starting addresses of the several routines. .IMP @A+DPTR is an instruction which performs an indirect jump to an address determined during program execution. The instruction adds the eight-bit unsigned accumulator contents with the contents of the sixteen-hit data pointer. just like MOVC A.@A+DPTR. The resulting sum is loaded into the program counter and is used as the address for subsequent instruction fetches. Again. a sixteen-bit addition is performed; a carry out from the low-order eight bits may propagate through the higher-order bits. In this case. neither the accumulator contents nor the data pointer is altered. The example subroutine below reads a byte of RA Minto the accumulator from one of four alternate addre" spaces. as selected by the contents of the \ariable MEMSEI.. The address of the byte to he read is determined by the contents of RO (and optionally R I). It might find use in a printiniperminal application. where four different model printers all use the same ROM code but use diffcrent types and SiICS' of buffer memory for different speeds and options. Example 23 -- N-Way Branch and Computed Jump Instructions via JMP @ ADPTR Example 22-Use of MPY and Data Pointer Instructions to Access Entries from a Multidimensional Look-Up Table in ROM ,MATRXI LOAD CONSTANT READ FROM TWO DIMENSIONAL LOOK-UP TABLE IN PROGRAM MEMORY INTO ACCUMULATOR USING LOCAL. TADLE LOOK-UP INSTRUCl ION. 'Move A, (!A+P( THE TOTAL NUMBER OF TABLE ENTRIES IS ASSUMED TO BE SMALL. 1 E LESS THAN ABOUT 250 ENTRIeS) TABLE USED IN THIS EXAMPLE IS ( 11 )( 21 ) DESIRED ENTRY ADDRESS IS GIVEN BY THE FORMULA, r (BASE ADDRESS) + (21 )( INDEXI) + (INDEXJl ] INDEXI INDEXJ I'IATRXI EOU EOU Rb 23H MOV MOV MUl. ADD A. INDEX I *21 INC Eau R3 JUMP _4 MOV HOV MOVC A, MEMSEL OPTR, *"MPTBL A, \tA"'OPTR JHP JMPTaL DB DB DB DB @A ... OPTR MEMSPO-JMPTBL MEMSPI-JMPl"BL MEMSP2-JMPTBL MEMSP3-JMPTaL MEMSPO MOV A. GlRD • READ FROM MEMSPI MOVX A, \tRO ,READ FROM 256 BYlES OF EXl"ERNAL RAM MEMSP2 RET MOV DPL. RO Mav DPH, RI ,FIRST COORDINATE OF ENTRY (0-10) ,SECOND COORDINATE OF ENTRY INTERNAL RAM RET 10-20) n. AD A.INDEXJ ALLOW FOR INSTRUCTION B'fTE BETWEEN "MOVC" ENTRY (0. OJ Move MEMSEL MEI"ISP3 A A. (fA+PC MOVX RET A. eOPTR ,READ FROM b4K BYTES OF EXTERNAL RAM • MOV ANL ANL ORL I10VX P1.*llI11000n A. RI A. *07H PI. A A,@RO • READ FROM 41'. BYTES OF EXl"ERNAL RAM RET RET BASEl DB DB • (ef1tr~ 0.0) , (entry 0,1) DB DB , (entr~ 0,20) • (entry 1.0) 22 ' DB DB 231 (f'f1tr~ 1.20) , (entry 10,20) Note that this approach is suitable whenever the sile of jump table plus the length of the alternate routines is Ie" than 256 bytes. The jump table and routines may he located anywhere in program memory. independent of 256-byte program memory pages. AFN-Ol ~02A-26 2-24 AP-69 For applications where up to 12K destinations must be ,elected. all of which reside in the same 2K page of program memory which ma5' be reached by the two-byte ab,olute jump instructions. the following techni4ue may be u,ed. In the above mentioned printing terminal example. this se4uence could "parse" 12K different codes for ASCII character, arriving via the X()SI serial port. Example 24·- N- Way Branch with 128 Optional Destinations OPTION EOU MDv R3 A. OPTION Rl INSTilL ,MULTIPLY DV 2 FOR MDV JMP DPTR •• INsrDL lM+DPTR A,JMP PROCOQ rRQCOl A.)Mf' ~ !lyrE .JlJMP TI\IiI.E ,FIRST ENrR"I' IN ,JUMP TAlliE ,JUMP INTO ,JUMP TABLE. • 128 CONSECUT I VE ,AJMP INSTRUCTIONS A,JMP A,JMP A,JMP PROC7E PRQC7F The de,tination, in the jump table (PROCOOPROC7F) are not all necc"arily uni4ue routine,. A large number of 'pecial control codes could each be processed with their own uni4uc routine. with the remaining printing characters all causing a branch to a common routine for entering the character into the output 4ueue. In those rare situations where even 12K options arc insufficient. or where the de,tination routines may cross a 2K page boundary. the above approach may be modified slightly as shown below. Example 25-256-Way Branch Using Address LookUp Tables RTEMP EGU JMP25b MDV MDv DPTR •• AORTDl A, OPTION elR Rle , FIRST ENTRY IN TABLE OF ADDRESSES ,MULTIPLY BY 2 rOR 2 INC MDv Move DPH RTEMP, A A.@'A+DPTR leCH. INC MOVC A. 'HEMP OW PRocoa PRDCOl • SAVE Ace FOR HIGH I)YTE READ • READ LOW In'TE FROM JUMP TADLE A A, @A+DPTR , GET LOW-ORDER BYTE FROM TABLF" PUSH ACC A, RTEMP MDV A, eA+[JPTR Move • GET HIGH--ORDER B't'TE FoROM TABLE PUSH ACC THE TWO ACC PUSHES HAVE PRODUCED A "RETURN ADDRESS" ON THE STACK WHICH CORRE5PO"lDS TO THE DESIRED STARTING ADDRESS IT MAY BE REACHED BY POPPING THE STACK INTO THE PC ADRTBL DW ,UP TO 256 CONSECUTIVE DATA ,WORDS INDICATING STARTING ADDRESSES PRDCFF DUMNY CODE ADDRESS DEFINITIONS NEEDED BY ABOVE TWO EXAMPLES PRDcaa PRDcal PRDca2 PRDC7E: PRDC7F PROCFF" Direct Bit Addressing A number of instructIOns operate on Boolean (one-bit) variables. using a direct bit addressing mode comparable to direct byte addressing. An additional byte appended to the opeode specifics the Boolean variable. I 0 pin. or control bit used. The state of any of these bits may be tested for "true" or "false" with the conditional branch instructions .IB (.lump on Bit) and .INB (Jump on Not Bit). The JBC (Jump on Bit and Clear) instruction combines a test-for-true with an unconditional clear. As in direct byte addressing. bit 7 of the address byte switches between two physical address spaces. Values between 0 and 127 (00H-7FH) define bits in internal RA M locations 20H to 2FH (Figure IXa); address bytes between 128 and 255 (XOH-OFFH) define bits in the 2 x "special-function" register address space (Figure I Xb). If no 2 x "special-function" register corresponds to the direct bit address used the result of the instruction is undefined. Bits so addressed have many wondrous properties. They may be set. cleared. or complemented with the two byte instructions SETB. CLR. or CPI.. Bits may be moved to and from the carry flag with MOV. The logical ANL and ORL functions may be performed between the carry and either the addressed bit or its complement. DYTE ,JUMP TAULE LDW128 LQW128 Prior to the introduction of the MCS-51'· family. nice number-crunchers made bad bit-bangers and vice versa. The X051 is the industry's first single-chip microcomputer designed to crunch and bang. (In some circles. the latter techni4ue is also referred to a, ··bit.-twiddling". Either is correct.) NDP NOP NOP NOP NOP NOP 4. BOOLEAN PROCESSING INSTRUCTIONS The commonly accepted terms for tash at either end of the computational vs. control application spectrum are. respectively. "number-crunching" and "bit-banging". Bit Manipulation Instructions - MOV The "MOV" mnemonic can be used to load an addressable bit into the carry flag ("MOV C. bi!"') or to copy the state of the carry to ,uch a bit ("MOV bit. C'). These instructions are often used for implementing serial 110 algorithms via software or to adapt the standard I 0 port structure. It is sometimes desirable to ··re .. arrange·· the order of I 0 pins because of considerations in laying out printed circuit boards. When interfacing the X051 to an immediately adjacent device with "weighted:' input pins. such as keyboard column decoder. the corresponding pins are'lik~ly to be ,not aligned (Figure 19). There is a trade-off in "scrambling" the interconnections with either interwoven circuit board traces or through software. This is extremely cumbersome (if not impossible) to do with byte-oriented computer architectures. The 8051"s unique set of Boolean instructions makes it simple to move indiVidual bits between arbitrary locations. AFN·Q1502A-27 2-25 infef AP-69 RAM BYTE 7FH -.... b.) Hardware Register Bit Addresses . ••) RAM BII Addresses. Direct (MSB) (LSB) 1 1 E71E61ESIE41ul E21E11EO ACC OOOH D71 D61 Dsl D41 D21D11DO PSW SO DOSH - I - I - I BC I DB I BA I B9 I BB IP OBOH B7 I B6 I BS I 8. I 83 I B2 I 81 I 80 P3 DASH AF I- I- I AC I AB I AA I J AB IE I AD P2 7E 7D 7C 7B 7A 79 7B 77 76 75 74 73 72 71 70 2DH 6F 6E 6C 6B 6A 69 6B 67 .. 6D 2CH 63 62 61 50 58 28H SF SE SD SC 58 SA 59 2AH 57 56 55 54 53 52 51 29H 4F 4E 4D 4C 4B 4A 49 43 42 41 40 3E 3D 3C 3B 3A 3. 38 47 27H 3F .. 4S . .. 26H 37 36 35 34 33 32 31 30 2SH 2F 2E 2D 2C 2B 2A 29 2. FO D31 A9 2.H 27 26 25 24 23 22 21 20 A7 I AS I AS I A4 I A3 I A2 I 1F 1E 1D 1C 1B 1A 19 ,. OAOH 23H 9BH .F I 9E I 9D I 9C I •• I .A I •• 1 •• 90H . 7 1 " 1 .5 1 " 1 .3 1 .2 1"1 BBH BF I BE I BD I BC I BB I BA I B. I BOH B7 I .. I BS I I 83 I B2 I B1 I 22H 17 16 15 14 13 12 11 10 21H OF DE OD DC DB OA 09 O. 20H 07 06 OS 04 03 02 01 50 1FH Register Symbol OFFH OEOH 7F . (LSB) F7 2FH 65 Hardware BII Addresses (MSB) OfOH 2EH 2BH Byle A1 Bank 3 1BH 17H 90 .. SCON P1 TeON Bank 2 10H B. BD PO DFH Bank 1 DSH D7H Bank 0 DOH Figure 18. Bit Address Maps Example 26-Re-ordering I/O Port Configuration ALE PSEN P2.7 P2.6 8351 8751 J J J -, OUT _PI [ (LSB) -' .'- --, r -' '- '- -' A2 P2.3 --, r -' '- A3 P2.2 -' P2.1 J J P2.5 P2.4 -' '- ~ P2.D Figure AD 19. "Mismatch" Decoder (MSB) '- RRC MOV RRC MOV RRC MOV RRC MOV RRC MOV A P2 6. C A ,MOVE ORIGINAL Ace 0 INTO CV ,STORE CARRY TO PIN P26 • MOVE ORIGINAL Ace 1 INTO CY p;, :i. C • STORE CARRY TO PIN P25 A ,MOVE ORIGINAL Ace 2 INTO CY • STORE CARRY TO PIN P24 ,MOVE ORIGINAL Ace 3 INT~ CY PO! 4. C A P2 3. C A • STORE CARRY TO PIN P23 , MOVE ORIGINAL ACC 4 INTO CY P2 2. C • 5TO~E CAF<~Y TO PIN P22 A1 DECODER Solving Combinatorial Logic Equations - ANL, ORL A4 [ [ Between 110 port and Virtually all hardware designers are familiar with the problem of solving complex functions using combinatorial logic. The (.echnologies involved may vary greatly. from IT. dtiple contact relay logic. \acuum tubes. TTL. or CMOS fo more esoteric approache, likc fluidic,. but in each case the goal is (he same: a Boolean (true false) function is computed on a number of Boolean \ ariables. AFN-01502A-28 2-26 inter AP-69 b.} Relay logic. a.) TTL CR. Q ~ (U • (V + W) + eX • Y) + Z z Figure 20. Implementations of Boolean functions INPUT. OUTPUT. l.OAD, STORE. etc .. instead of the uni\er,al MOV. Figure 20 shows the logic diagram for an arbitrary function of six variables named U through Z using ,tandard logic and relay logic symbols. Each is a solution of the eljuation. Q = (U • (V + W» + (X. Y) + Z (While this eljuation could be reduced using Karnaugh Map' or algebraic techniljues. that is not the purpose of this example. Even a minor change to the function cljuation would reljuire re-reducing from scratch.) Mo,t digital computers can solve eljuations of this type with ,tandard word-wide logical in,tructions and conditional jumps. Still. such software solutions seem ,omewhat sloppy because of the many paths through the program thc computation can take. A"umc U and V arc input pins being read by different input ports. Wand X are stutus bit, for two peripheral controllers (read as I 0 ports). and Y and Z are software Ilag' set or cleared earlier in the program. The end re,ull must bc written to an output pin on some third port. For the sake of comparison we will implement this function with ,oftware drawn from thrce proper suhsets of the MCS-SI ,. instruction set. The first two implcmentations follow the flow chart shown in Figure 21. Program flow would embark on a route down a testand-branch tree and leaves either the "Truc" or "Not rruc" cxit ASAP. These exits then write the output port "ith the data previously written to the,ame port with the re,ull bit respectivcly one or lero. In the first case. we assume there are no instructions for addrc"ing individual bits other than special flags like the carry. Thi, b typical of many older microproce!>Sors and mainframe computers designed for number-crunching. MCS-SI'· mnemonics arc u,ed hcre. though for most othcr machines thc issue would be even further clouded h~ thcir usc of operation-specific mnemonic, like (CONTINUE) Figure 21. Flow chart for tree-branching logic implementation 2-27 inter AP-69 Example 27 - Software Solution to Logic Function of 'Figure 20, Using only Byte-Wide Logical Instructions • BFUNCI SOL ....e Po RANDOM LOGIC FUNCTION OF b V~RIABLES BY L.OADING AND MASKING THE APPROPRIATE BJTS IN THE ACCUMULATOR. THEN EXeCUTING CONDITIONAL ..rUMPS BASED ON ZERO CONDITION (APPROACH useD BY BYTE-ORIENTED ARCHITECTURES) BYTE AND MASK VALUES CORRESPOND TO RESPECTIVE BYTE ADDRESS AND BIT POSITION OUTBUF EOU 22H TESTV "OV ANL JNl "OV ANL JZ "OV ANL IN' MOV ANL JZ HOV ANL J' A. P2 A ••00000100B TESTU Po. TCON TESTU • OUTPUT PIN STATE MAP These instructions may be "strung together" to simulate a multiple input logic gate. When finished, the carry flag contains the result, which may be moved directly to the destination or output pin. No flow chart is needed - it is simple to code directly from the logic diagrams in Figure 20. Example 29-Software Solution to Logic Function of Figure 20, Using the MCS-51 (TM) Unique Logical Instructions on Boolean Variables A•• OOloaaoon .IJFUNC3 SOLI,IE A RANDOM LOGIC FUNCTION OF 6 VARIAIKES USINQ STRAIGHT-LINE LOGICAL INSTRUCTIONS ON MCS-51 BOOLEAN VARIABLES TEST]( A. PI A.4tOOOOODIOD sera MOV ORL ANL HOV MOV ANL ORL ORL "OV A. TCON A ••000010000 TESTZ A.20H A ••00000001B SETO .",ov A.2IH I'll, .000000100 SETG ANL JZ eLRO aUTa Fa, C c. x C,IY C, FO C,/Z ,OUTPUT OF OR GATE • OUTPUT OF TOP AND GATE ,SAVE INTERMEDIATE STATE ,OUTPUT OF BOTTOM AND GATE , INCL.UDE VAL.UE SAVED ABOVE ,INCLUDE LAST INPUT VARIABLE ,OUTPUT COMPUTED RESULT A. CUTBUF A •• lll10111D Duro SEra c. v c.u "OV ORL HOV "OV Simplicity itself. Fast, flexible, reliable, easy to design, and easy to debug. 'A.OUTBUF A •• 00001000B OUTBUF, A P;3. Po The Boolean features are useful and unique enough to warrant a complete Application Note of their own . Additional uses and ideas are presented in Application Note AP-70, Using the Intel" MCS~51" Boolean Processing Capabilities, publication number 121519. . Cumbersome, to say the least, and error prone. It would be hard to prove the above example worked in all cases without an exhaustive test. Each move/mask/conditional jump instruction sequence may be replaced by a single bit-test instruction thanks to direct bit addressing. But the algorithm would be equally convoluted. 5. ON-CHIP PERIPHERAL FUNCTION OPERATION AND INTERFACING 1/0 Ports Example 28 - Software Solution to Logic Function of Figure 20, Using only Bit-Test Instructions The I/O port versatility results from the "quasibidirectional" output structure depicted in Figure 22. (This is effectively the structure of ports I, 2, and 3 for normal I/O operations. On port 0 resistor R2 is disabled except during multiplexed bus operations, providing • BFUNC2 SOLVE A RANDOM LOGIC FUNCTION OF £, VARIABLES BY DIRECTLY POLLINO EACH BIT (APPROACH USINC MCS-51 UNIQUE BIT-TEST INSTRUCTION CAPABILITY) SYMBOLS USED IN LOGIC DIAGRAM ASSIGNED TO CORRESPONDING 80:51 BIT ADDRESSES BIT PI 1 BIT BIT P2 2 TFO BIT BIT BIT lEI 20H 0 21H 1 P3 3 BIT TEST _V TEST U TEST=:X TEST_Z CLR_O SET _0 NXTTST ..18 JNB ..IS ..INB JNB ,JNB CLR V. TEST_U w. TEST_J( U. SET_O TEST_Z Y.SET_Q Z. SET_O J"P SETB NXTlST READ/MODIFY I WRITE x. INTERNAL BUS G o , (CONTINUATION OF PROGRAM) A more elegant and efficient 8051 implementation uses the Boolean ANL and ORL functions to generate the output function using straight-line code. These instructions perform the corresponding logical operations between the carry flag ("Boolean Accumulator") and the addressed bit, leaving the result in the carry. Alternate forms of each instruction (specified in the assembly language by placing a slash before the bit name) use the complement of the bit's state as the input operand. WRITE PULSE BUS CYCLE TIMING REAO Figure 22, Pseudo-bidirectional 1/0 port circuitry AFN-01502A-30 2-28 AP-69 e"entially open-collector output>. ror full electrical characteri,tic, ,ee the lber', Manual.) Example 30 -- Mixing Parallel Output. Input. and Control Strobes on Port 2 'rm24~1 An output latch bit a>sociated with each pin is updated by direct addre\Sing instruction, when that port i, the de,tination. The latch ,tate is buffcred to the oUbide world by R I and 0 I. which may drive a ,tandard TTL input. (in TTL term,. 01 and R I resemblc an opcncollector output with a pull-up re,istor to Vcc.) " J I I ,,~ .f·Ar~Df ~ 1t1l01001"""," I',' A . OUTPuT INSTfllJCl HITI ell!.!! .. ~ AI L INC f:Dr.E f1F. PIH1(, 1'.:!.4IOOOClII!IB .SET FO,", IN!,1," !',' Ijlll u"r.\ .t' ~t_AI' INI-IJ! Il[T<}i-JN I-I_U" HI I-It! .f ' ror-,>nr;" .;11\1' Serial Port and Timer applications R2 and 02 represent an "activc pull-up" deviec enablcd momentarily when a 0 previously output changes to a I. Thi, "jerb"thc output pin to a I level morc 4uickly than thc paS\i,'c pull-up. improving ri,c-time significantly if thc pin i, driving a capacitive load. Note thattne active pull-up i, only activated on (}-to-I transitions at the output latch (unlike thc X04X. in which 02 i, acti,ated whcncver a I i, writtcn out). Opcration, u,ing an input port or pin a, the sourcc operand usc the logic level of the pin itself. rather than the output latch contents. This level is affected by both the microcomputer it,elf and whatever device the pin is connected to externallv. The value read is cssentiallv the "OR-tied" function of'O I and the cxternal device. if the extcrnal device is high-impedencc. such as a logic gate input or a 1hree state output in thc third state. then reading a pin will rencctthe logic level previously output. To u,e a pin for input. the corresponding output latch mu,t be ,ct. The external device may then drive the pin with cithcr a high or low logic signal. Thus the same port may be u,cd a, both input and output by writing ones to all pin,,,used as input' on output operations. and ignoring all pin, u,ed a, output on an input operation. IN~'I'l r,,\T.\ ~1"'f1 t,~J 8 •.; COM,Eer; oj TO f','.l-P r'" Po.!" • I' '·1 MIMIC CS P;' I -p -~ lJ"::E"D AS iNP'JTS To: 'H ~£AD /rJ l,,". Configuring thc 8051's Scrial Port for a given data ratc and prolocol re4uirc> cs>cntially thrce short ,cclions of software. On power-up or hardware resel the serial port and timer control word, mu,t bc initiali/cd to thc appropriate value,. Additional software i, abo needed in the transmit routine to load thc ,erial port data rcgister and in the receive roulinc to unload the data a, it arrives. This i, be,t illu,trated through an arbitrary example. A"umc the 80S1 will communicate "ith a CRT operating at 2400 baud (bits per second)_ Each character b transmitted as ,even data bits. odd parity. and one stop bit. This re,ult, in a character rale of 2400 10=240 characters per second. For the sake of clarity. the transmit and rcceive subroutines arc driven by simple-minded soflware status polling code ralher than interrupts. (It might heir 10 refer back to Figures 7-9 showing the control word formats.) The serial port must be iniliali7cd to 8-bit UART mode (MO. M 1=01). enabled to receivc all messages (M2=O. REN=I). The nag indicating that the transmit register i, free for more data will be artificially ,et in order tolctthe output software know the output register is av'ailable. This can all be set up with one instruction. . In one operand instructions (INC, DEC, DJNZ and the Boolean CPL) the output latch rather than thc input pin Ic\cl i, u,ed a, the source data. Similarly. two operand in,tructions using the port as both one source and the dc,tination (AN\.. OR\.. XRL) u,c the output latches. Thi, cn,urc, that latch bits corresponding to pins used a, inputs will not bc cleared in the proces> of executing these Example 31 -- Serial Port Mode and Control Bits ,SPINlT INITIALIZE SERIAL PORT FOR B-B r T UART MO[lF r. seT TRANSMIT READY FLAG SCON. "010100103 in~tructi{)ns. 8351 8751 The Boolean operation JBC tests the output latch bit. rathcr than the input pin. in deciding whether or not to jump. Like the byte-wise logical operations. Boolean operations which modify individual pins of a port leave the other bits of the output latch unchanged. 8243 P' P2.7 P2.& P2.5 P2.4 P2.3 P2.2 P2.1 A good example of how these modes may play together may be taken from the hosl-processor interface expected by an X243 I 0 expander. Even though the 8051 does not include X048-type instructions for interfacing with an 8243. the parts can be interconnected (Figure 23) and the rrotocol may be emulatcd with simplc software. P2.0 } INPUTS CS PS PROG P23 P' P22 P21 P2. P7 F.igure 23. Connecting an 8051 with an 8243 I/O Expander AFN-01502A-31 2-29 inter AP-69 Timer I will be used in auto-reload mode as a data rate generator. To achieve a data rate of 2400 baud. the timer must divide the I M Hz internal clock by 32 x (desired data rate): I x H)" (32) (2400) which equals 13.02 rounded down to 13 instruction cycles. The timer must reload the value -13. or OF3H. (ASMSI will accept both the signed decimal or hexadecimal representations.) Example 32 -Initializing Timer Mode and Control BiH • TllNIT INITIALIZE TII'tER 1 FOR AUTO-RELOAD AT 32*2400 HZ eTa USED AS GATED lib-BIT COUNTER) TIINIT MOY "OV SEn TeoN. _110100108 THI. "-13 TRI A ~imple subroutine to transmit the character passed to it in the accumulator must first compute the parity bit. insert it into the data byte. wait until the transmitter is available. output the character. and return. This is nearly as easy said as done. Example 33 -Code for UART Output. Adding Parity. Transmitter Loading ,SP OUT ADD 000 PARITY TO Ace AND TRANSMIT WHEN SER I AL PORT READY SP_OUT MOV ePl MOV JNB elR MOV RET e. P e Ace 7, c TI •• 11 SBUF. A A simple minded routine to wait until a character is received. set the carry flag if there is an odd-parity error. and return the masked seven-bit code in the accumulator is equally short. Example 34-Code for UART Reception and Parity Verification .SP_IN INPUT NEXT CHARACTER FROM SERIAL PORT SET CARRY IFF ODD-PARITY ERROR 5P _IN JNB ClR MOV MOV CPl ANl RET RI. f; Rl A.SBUF C. P C A. "7FH 6. SUMMARY This Application Note has described, the architecture. instruction set. and on-chip peripheral features of the first three members of the MCS-SI T• microcomputer family. The examples used throughout were admittedly (and necessarily) very simple. Additional examples and techniques may be found in the MCS-SI ,. User's Manual and other application notes written for the MCS-48'· and MCS-SI T• families. Since its introduction in 1977. the MCS-48'· family has become the industry standard single-chip microcomputer. The MCS-.5IT. architecture expands the addressing capabilities and instruction set of its predecessor while ensuring flexibility for the future. and maintaining basic software compatability with the past. Designers already familiar with the 8048 or 8049 will be able to take with them the education and experience gained from past designs as ever-increasing system performance demands force them to move on to state-of-" the-art products. Newcomers will find the power and regularity of the 80S I instruction set an advantage in streamlining both the learning and design processes. Microcomputer system designers will appreciate the 80S I as basically a single-chip solution to many problems which previouslv required board-level computers. Designers of real:time control systems will find the high execution speed. on-chip peripherals. and interrupt capabilities vital in meeting the timing constraints of products previously requiring discrete logic designs. And designers of industrial controllers will be able to convert ladder diagrams directly from testcd-and-true TTL or relay-logic designs to microcomputer'software. thanks to the unique Boolean processing capabilities. 11 has not been the intent of this note to gloss over the difficulty of designing microcomputer-based systems. To be sure. the hardware and software design aspects of any ncw computer system are nontrivial tasks. Howevcr. the system speed" and level of integration of the MCS-SI'· microcomputers. the power and flexibility of the instruction set. and the sophisticated assembler and other support products combine to give both the hardware and software designer as much of a head start on the problem as possible. AFN-01502A-32 2-30 APPLICATION NOTE AP-70 April 19BO Using the Intel MCS®-51 Boolean Processing Capabilities JOHN WHARTON MICROCONTROLLER APPLICATIONS @ Intel Corporation, 1988 2-31 Order Number: 203830-001 intJ AP-70 1.0 INTRODUCTION The Intel microcontroller family now has three new members: the Intel® 8031, 8051, and 8751 single-chip microcomputers. These devices, shown in Figure 1, will allow whole new classes of products to benefit from recent advances in Integrated Electronics. Thanks to Intel's new HMOS technology, they provide larger program and data memory spaces, more flexible I/O and peripheral capabilities, greater speed, and lower system cost than any previous-generation single:chip microcomputer. - yee Pl.0 Pl.l- - PO.O Pl.2- - PO.l Pl.3 - - PO.2 P1.4 - - PO.3 Pl.S- - PO.4 Pl.6- - PO.S Pl.7 - - PO.6 - PO.7 RST P3.0lRXD - - YPP/EA P3.lITXD - - PI'!O'G/ALE P3.21iNTo - - PSEN P3.3/1NTI - - P2.7 P3.41TO - - P2.6 P3.S/TI - - P2.S P3.6/WR - - P2.4 P3.7/AD - - P2.3 XTAL2 - - P2.2 XTALl - - P2.1 YSS - - P2.0 203830-1 Figure 1.8051 Family Pinout Diagram Table 1 'summarizes the quantitative differences between the members of the MCS®-48 and 8051 families. The 8751 contains 4K bytes of EPROM program memory fabricated on-chip, while the 8051 replaces the EPROM with 4K bytes of lower-cost maskprogrammed ROM. The 8031 has no program memory on-chip; instead, it accesses up to 64K bytes of program memory' from external memory. Otherwise, the three new family members are identical. Throughout this Note, the term "8051" will represent all members of the 8051 Family, unless specifically statecI otherwise. The CPU iIi each microcomputer is one of the industry's fastest and most efficient for numerical calculations on byte operands. But controllers often deal with bits, not bytes: in the real world, switch contacts can only be open or closed, indicators should be either lit or dark, motors are either turned on or off, and so forth. For such control situations the most significant aspect of the MCS®-51 architecture is its complete hardware support for one-bit, or Boolean variables (named in honor of Mathematician George Boole) as a separate data type. The 11051 incorporates a number of special features which support the direct manipulation and testing of individual bits and allow the use of single-bit variables in performing logical operations. Taken together, these features are referred to as the MCS-51 Boolean Processor. While the bit-processing capabilities alone would be adequate to solve many control applications, their true power comes when they are used in conjunction with the microcomputer's byte-processing and numerical capabilities. Many concepts embodied by the Boolean Processor will certainly be new even to experienced microcomputer system designers. The purpose of this Application Note is to explain these concepts and show how they are used. For detailed information on these parts refer to the Intel Microcontroller Handbook, order number 210918. The instruction set, assembly language, and use 'of the 8051 assembler (ASM51) are further described in the MCS®-Sl Macro Assembler User's Guide for DOS Systems, order number 122753. Table 1. Features of Intel's Single-Chip Microcomputers EPROM Program Memory ROM Program Memory External Program Memory Program Memory (InttMax) Data Memory (Bytes) Instr. Cycle Time Inputt Output Pins Interrupt Sources Reg. Banks 8748 8048 8049 8051 8035 8039 8031 1K4K 2K4K 4K64K 64 128 128 2.5/Jos 1.36/Jos 1.0/Jos 27 27 32 2 2 5 2 2 4 8751 2-32 - inter AP-70 plex (albeit slower) ones, which in turn link together eventually solving the problem at hand. A four-bit CPU executing multiple precision subroutines can, for example, perform 64-bit addition and subtraction. The subroutines could in turn be building blocks for floatingpoint multiplication and division routines. Eventually, the four-bit CPU can simulate a far more complex "virtual" machine. 2.0 BOOLEAN PROCESSOR OPERATION The Boolean Processing capabilities of the 8051 are based on concepts which have been around for some time. Digital computer systems of widely varying designs all have four functional elements in common (Figure 2): • a central processor (CPU) with the control, timing, and logic circuits needed to execute stored instructions: • a memory to store the sequence of instructions making up a program or algorithm: In fact, any digital computer with the above four functional elements can (given time) complete any algorithm (though the proverbial room full of chimpanzees at word processors might first re-create Shakespeare's classics and this Application Note)! This fact otTers little consolation to product designers who want programs to run as quickly as possible. By definition, a real-time control algorithm must proceed quickly enough to meet the preordained" speed constraints of other equipment. • data memory to store variables used by the program: and • some means of communicating with the outside world. One of the factors determining how long it will take a microcomputer to complete a given chore is the number of instructions it must execute. What makes a given computer architecture particularly well- or poorly-suited for a class of problems is how well its instruction set matches the tasks to be performed. The better the "primitive" operations correspond to the steps taken by the control algorithm, the lower the number of instructions needed, and the quicker the program will run. All else being equal, a CPU supporting 64-bit arithmetic directly could clearly perform floating-point math faster than a machine bogged-down by multiple-precision subroutines. In the same way, direct support for bit manipulation naturally leads to more efficient programs handling the binary input and output conditions inherent in digital control problems. The CPU usually includes one or more accumulators or special registers for computing or storing values during program execution. The instruction set of such a processor generally includes, at a minimum, operation classes to perform arithmetic or logical functions on program variables, move variables from one place to another, cause program execution to jump or conditionally branch based on register or variable states, and instructions to call and return from subroutines. The program and data memory functions sometimes share a single memory space, but this is not always the case. When the address spaces are separated, program and data memory need not even have the same basic word width. A digital computer's flexibility comes in part from combining simple fast operations to produce more com- TIMING & CONTROL PROGRAM MEMORY ACCUMULATOR & REGISTERS INPUTI OUTPUT PORTS DATA MEMORY REAL WORLD CENTRAL PROCESSING UNIT 203830-2 Figure 2. Block Diagram for Abstract Digital Computer 2-33 AP-70 Processing Elements The introduction stated that the 8051's bit-handling capabilities alone would be sufficient to solve some control applications. Let's see how the four basic elements of a digital computer-a CPU with associated registers, program memory, addressable data RAM, and I/O capability-relate to Boolean variables. cpu. The 8051 ·CPU incorporates special logic devoted to executing several bit-wide operations. All told, there are 17 such instructions, all listed in Table 2. Not shown are 94 other (mostly byte-oriented) 8051 instructions. tions of Table 2, several sophisticated program control features like multiple addressing modes, subroutine nesting, and a two-level interrupt structure are useful in structuring Boolean Processor-based programs. Boolean instructions are one, two, or three bytes long, depending on what function they perform. Those involving only the carry flag have either a single-byte opcode or an opcode followed by a conditional·branch destination byte (Figure 3a). The more general instructions add a "direct address" byte after the opcode to specify the bit affected, yielding two or three byte encodings (Figure 3b). Though this format allows potentially 256 directly addressable bit locations, not all of them are implemented in the 8051 family. Program Memory. Bit-processing instructions are fetched from the same program memory as other arithmetic and logical operations. In addition to the instruc- opcode Table 2. MCS-S1TM Boolean Processing Instruction Subset Mnemonic Description SETB SETB CLR CLR CPL CPL C bit C bit C bit Set Carry flag Set direct Bit Clear Carry flag Clear direct bit Complement Carry flag Complement direct bit MOV MOV C.bit bit.C ANL ANL C.bit C.bit ORL ORL C.bit C.bit JC JNC JB JNB JBC rei rei bit.rel bit.rel bit.rel 2 1 1 1 1 1 1 Move direct bit to Carry flag Move Carry flag to direct bit 2 2 2 AND direct bit to Carry flag AND complement of direct bit to Carry flag OR direct bit to Carry flag OR complement of direct bit to Carry flag 2 2 2 2 2 2 2 2 2 2 3 3 3 2 2 2 2 2 Jump if Carry is flag is set Jump if No Carry flag Jump if direct Bit set Jump if direct Bit Not set Jump if direct Bit is set & Clear bit SETBC CLRC CPLC Byte eyc 1 2 1 2 1 1 opcode Idisplacement I JC JNC rei rei a.) Carry Control and Test Instructions opcode SETB CLR CPL ANLC, ANLC,! ORLC, ORLC,! MOVC, MOV Address mode abbreviations C-Carry flag. bit-12B software flags, any 110 pin, control or status bit. rei-Ali conditional jumps include an B·bit offset byte. Range is + 127 -12B bytes relative to first byte of the following instruction. opcode JB JNB JBC All mnemonics copyrighted@ Intel Corporation 1980. I I bit address bit bit bit bit bit bit bit bit bit,C I I bit address Idisplacement I bit, bit, bit, rei rei rei b.) Bit Manipulation and Test Instructions Figure 3. Bit Addressing Instruction Formats 2-34 AP-70 RAM Byte Direct 7FH~ Bit Addre.le. B~t. (LSB) (MSB) Addre•• (MSB) (LSB) Hardware Regl.ter Symbol OFFH -...:.. I~ 2FH 7F 7E 70 7C 7B 7A 79 78 2EH 77 76 75 74 73 72 71 70 20H 6F 6E 60 6C 6B 6A 69 68 2CH 67 66 65 64 63 62 61 60 2BH SF 5E 50 5C 5B SA 59 58 2AH 57 56 55 54 53 52 51 50 29H 4F 4E 40 4C 4B 4A 49 48 28H 47 46 45 44 43 42 41 40 27H 3F 3E 3D 3C 3B 3A 39 38 26H 37 36 35 34 33 32 31 30 25H 2F 2E 20 2C 2B 2A 29 28 24H 27 26 25 24 23 22 21 20 23H 1F 1E 10 1C 1B 1A 19 18 22H 17 16 15 14 13 12 11 10 '21H OF OE 00 OC OB OA 09 08 20H 07 06 05 04 03 02 01 00 OFOH F7 FO B OEOH E7 EO ACC OOOH 07 DO PSW B8 IP OB8H OBOH B7 BO P3 OA8H AF A8 IE OAOH A7 AO P2 98H 9F 98 SCON 90H 97 90 P1 88H 8F 88 TCON 80H 87 80 PO lFH 18H 17H 10H Bank 3 Bank 2 OFH 08H 07H 00 Bank 1 Bank 0 203830-3 a.) RAM Bit Addresses b.) Special Function Register Bit Addresses Figure 4. Bit Address Maps Data Memory. The instructions in Figure 3b can operate directly upon 144 general purpose bits forming the Boolean processor "RAM." These bits can be used as software flags or to store program variables. Two operand instructions use the CPU's carry flag ("C") as a special one-bit register: in a sense, the carry is a "Boolean accumulator" for logical operations and data transfers. Input/Output. All 32 I/O pins can be addressed as individual inputs, outputs, or both, in any combination. Any pin can be a control strobe output, status (Test) input, or serial I/O link implemented via software. An additional 33 individually addressable bits reconfigure, control, and monitor the status of the CPU and alI onchip peripheral functions (timer counters, serial port modes, interrupt logic, and so forth). 2-35 intJ AP-70 (MSB) I CY ! AC ! FO (LSB) RS1 RSO OV PSW.2 P PSW.1 PSW.O OV Symbol Position Name and Significance CY PSW.7 Carry flag. Set/ cleared by hardware or software during certain arithmetic and logical iristructions. AC PSW.6 Auxiliary Carry flag. Set/cleared by hardware during addition or subtraction instructions to indicate carry or borrow out of bit 3. FO PSW.5 Flag O. Set/cleared/tested by software as a user-defined status flag. RS1 PSW.4 Register bank Select control bits. RSO PSW.3 1 & O. Set/cleared by software to determine working register bank (see Note). Note- Overflow flag. Set/cleared by hardware during arithmetic instructions to indicate overflow conditions. (reserved) Parity flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of "one" bits in the accumulator, i.e., even parity. the contents of (RS1, RSO) enable the working register banks as follows: (0,0) - Bank 0 (00H-07H) (0,1) - Bank 1 (OBH-OFH) (1,0) - Bank 2 (10H-17H) (1,1)-Bank3 (1BH-1FH) Figure 5. PSW-Program Status Word Organization (MSB) (LSB) INT1 P3.3 INTO P3.2 TXD P3.1 RXD P3.0 !RD.! WR! T1! TO !INT1!INTO! TXD I RXDI Symbol Position Name and Significance RD P3.7 Read data control output. Active low pulse generated by hardware when external data memory is' read. WR P3.6 Write data control output. Active low pulse generated by hardware when external data memory is written. P3.5 T1 Timerlcounter 1 external input or test pin. P3.4 TO Timerlcounter 0 external input or test pin. Interrupt 1 input pin. Low-level or falling-edge triggered. Interrupt 0 input pin. Low-level or falling-edge triggered. Transmit Data pin for serial port in UART mode. Clock output in shift register mode. Receive Data pin for serial port in UART mode. Data 110 pin in shift register mode. Figure 6. P3-Alternate 1/0 Functions of Port 3 Direct Bit Addressing The most significant bit of the direct address byte selects one of two groups of bits. Values between 0 and 127 (DOH and 7FH) define bits in a block of 32 bytes of on-chip RAM, between RAM addresses 20H and 2FH (Figure 4a). They are numbered consecutively from the lowest-order byte's lowest-order bit through the highest-order byte's highest-order bit. 2-36 Bit addresses between 12S and 255 (SOH and OFFH) correspond to bits in a number of special registers, mostly used for I/O or peripheral control. These positions are numbered with a different scheme than RAM: the five high-order address bits match those of the register's own address, while the three low-order bits identify the bit position within that register (Figure 4b). AP-70 Notice the column labeled "Symbol" in Figure 5. Bits with special meanings in the PSW and other registers have corresponding symbolic names. General-purpose (as opposed to carry-specific) instructions may access the carry like any other bit by using the mnemonic CY in place of C, PO, Pt, P2, and P3 are the 805t's four I/O ports: secondary functions assigned to each of the eight pins of P3 are shown in Figure 6. Figure 7 shows the last four bit addressable registers. TCON (Timer Control) and SCON (Serial port Control) control and monitor the corresponding peripherals, while IE (Interrupt Enable) and IP (Interrupt Priority) enable and prioritize the five hardware interrupt sources. Like the reserved hardware register addresses, the five bits not implemented in IE and IP should not be accessed: they can not be used as software flags. Addressable Register Set. There are 20 special function registers in the 805t, but the advantages of bit addressing only relate to the 11 described below. Five potentially bit-addressable register addresses (OCOH, OC8H, OD8H, OE8H, & OF8H) are being reserved for possible future expansion in microcomputers based on the MCS-51 architecture. Reading or writing non-existent registers in the 8051 series is pointless, and may cause unpredictable results. Byte-wide logical operations can be used to manipulate bits in all non-bit addressable registers and RAM. 2-37 intJ (MSB) AP-70 (LSB) IE1 I TF1 I TR1 I TFO I TRO IIE1 1,IT1 IlEa liTO I Symbol Position Name and Significance TF1 TCON.7 Timer 1 overflow Flag. Set by hardware on timer/ counter overflow. Cleared when interrupt processed. TR1 TCON.6 Timer 1 Run control bit. Set!cleared by software to turn timer/counter on/off. TFO TCON.S Timer 0 overflow Flag. Set by hardware on timer/ counter overflow. Cleared when interrupt processed. TRO TCONA Timer 0 Run control bit. Set! cleared by software to turn timer/counter on/off. IT1 lEO ITO TCON.3 Interrupt 1 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt pro" cessed. TCON.2 Interrupt 1 Type control bit. Set!cleared by software to specify falling edgellow level triggered external interrupts. TCON.1 Interrupt 0 Edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. TCON.O Interrupt 0 Type control bit. Set!cleared by software to specify falling edgellow level triggered external interrupts. a.) TCON-Timer/Counter Control/Status Register (MSB) (LSB) RB8 I SMa I SM1 I SM2 I REN I TBS I RBSI TI I RI I SCON.2 Receive Bit B. Set/cleared by hardware to indicate state of ninth data bit received. Symbol Position Name and Significance SMO SCON.7 Serial port Mode control bit o. TI SCON.1 Transmit Interrupt flag. Set! cleared by software (see Set by hardware when byte note). transmitted. 'Cleared by software after serviCing. SM1 SCON.6 Serial port Mode control bit 1. Set!cleared by software (see RI SCON.O Receive Interrupt flag. note). Set by hardware when byte received. Cleared by software SM2 SCON.S Serial port Mode control bit 2. after servicing. Set by software to disable reception of frames for which bit Notethe state of (SMO, SM1) B is zero. selects: (O,O)-8hift register I/O REN SCONA Receiver Enable control bit. expansion. Set/cleared by software to en(O,1)-8-bit UART, variable able/disable serial data recepdata rate. tion. (1,O)-9-bit UART, fixed data TBB SCON.3 Transmit Bit B. rate. Set! cleared by hardware to de(1,1 )-9-bit UART, variable termine state of ninth data bit data rate. transmitted in 9-bit UART mode. b.) SCON--5erial Port Control/Status Register Figure 7. Peripheral Configuration Registers 2-38 inter AP-70 (MSa) (lSa) I EA I - I - I ES I En EX1 ET1 I EXO I Symbol Position Name and Significance 1E.2 EX1 EA IE. 7 Enable All control bit. Cleared by software to disable all interrupts, independent of the state of IE.4-IE.O. ETO 1E.1 (reserved) IE.6 1E.5 ES IE.4 Enable Serial port control bit. EXO lE.O Set! cleared by software to enable/disable interrupts from TI or RI flags. Enable Timer 1 control bit. ET1 IE.3 Set! cleared by software to enable/disable interrupts from timer/counter 1. c.) IE-Interrupt Enable Register (MSa) (lSa) I - I - I - I PS Symbol Position IP.7 IP.6 IP.5 PS IP.4 PT1 Enable External interrupt 1 control bit. Set! cleared by software to enable/disable interrupts from INT1. Enable Timer 0 control bit. Set! cleared by software to enable/disable interrupts from timer/counter o. Enable External interrupt 0 control bit. Set! cleared by software to enable/disable interrupts from INTO. IP.3 PT1 PX1 I PTO I PXO I Name and Significance (reserved) (reserved) (reserved) Serial port Priority control bit. Set/cleared by software to specify high/low priority interrupts for Serial port. Timer 1 Priority control bit. Set!cleared by software to specify high/low priority interrupts for timer/counter 1. PX1 IP.2 PTO IP.1 PXO IP.O External interrupt 1 Priority control bit. Set! cleared by software to specify high/low priority interrupts for INT1. Timer 0 Priority control bit. Set/ cleared by software to specify high/low priority interrupts for timer/counter O. External interrupt 0 Priority control bit. Set!cleared by software to specify high/low priority interrupts for INTO. d.) IP-Interrupt Priority Control Register Figure 7. Peripheral Configuration Registers (Continued) The accumulator and B registers (A and B) are normally involved in byte-wide arithmetic, but their individual bits can also be used as 16 general software flags. Added with the 128 flags in RAM, this gives 144 general purpose variables for bit-intensive programs. The program status word (PSW) in Figure 5 is a collection of flags and machine status bits including the carry flag itself. Byte operations acting on the PSW can therefore affect the carry. Instruction Set Having looked at the bit variables available to the Boolean Processor, we will now look at the four classes of 2-39 instructions that manipulate these bits. It may be helpful to refer back to Table 2 while reading this section. State Control. Addressable bits or flags may be set, cleared, or logically complemented in one instruction cycle with the two-byte instructions SETB, CLR, and CPL. (The "B" affixed to SETB distinguishes it from the assembler "SET" directive used for symbol definition.) SETB and CLR are analogous to loading a bit with a constant: 1 or O. Single byte versions perform the same three operations on the carry. The MCS-5l assembly language specifies a bit address in any of three ways: • by a number or expression corresponding to the direct bit address (0-255): AP-70 Logical Operations. Four instructions perform the logical-AND and logical-OR operations between the carry and another bit, and leave the results in the carry. The instruction mnemonics are ANL and ORL; the absence or presence of a slash mark ("/") before the source operand indicates whether to use the positive-logic value or the logical complement of the addressed bit. (The source operand itself is never affected.) • by the name or address of the register containing the bit, the dot operator symbol (a period: "."), and the . bit's position in the register (7 -0): • in the case of control and status registers, by the predefined assembler symbols listed in the first columns of Figures 5-7. Bits may also be given user-defined names with the as.sembler "BIT" directive and any of the above techniques. For example, bit 5 of the PSW may be cleared by any of the four instructions. USR_FLG BIT PSW.5 User Symbol Definition CLR CLR CLR OD5B PSW.5 FO CLR USR_FLG Absolute Addressing Use of Dot Operator Pre-Defined Assembler Symbol User-Defined Symbol Data Transfers. The two-byte MOY instructions can transport any addressable bit to the carry in one cycle, or copy the carry· to the bit in two cycles. A bit can be moved between two arbitrary locations via the carry by combining the two instructions. (If necessary, push and pop the PSW to preserve the previous contents of the carry.) These instructions can replace the multi-instruction sequence of Figure 8, a program structure appearing in controller applications whenever flags or outputs are conditionally switched on or off. All 8051 conditional jump instructions use program counter-relative addressing, and all execute in two cycles. The last instruction byte encodes a signed displacement ranging from -128 to + 127. During execution, the CPU adds this value to the incremented program counter to produce the jump destination. Put another way, a conditional jump to the immediately following instruction would encode OOH in the offset byte. A section of program or subroutine written using only relative jumps to nearby addresses will have the same machine code independent of the code's location. An assembled routine may be repositioned anywhere in memory, even crossing memory page boundaries, without having to modify the program or recompute destination addresses. To facilitate this flexibility, there is an . unconditional "Short Jump" (SJMP) which uses relative addressing as well. Since a programmer would have quite a chore trying to compute relative offset values from one instruction to another, ASM51 automatically computes the displacement needed given only the destination address or label. An error message will alert the programmer if the destination is "out of ~ange." ISOLATE SOURCE BIT NO SET DESTINATION BIT Bit-test Instructions. The conditional jump instructiolls "JC rei" (Jump on Carry) and "JNC rei" (Jump on Not Carry) test the state of the carry flag, branching if it is a one or zero, respectively. (The letters "rei" denote relative code addressing.) The three-byte instructions "JB bit.rel" and "JNB bit. rei" (Jump on Bit and Jump on Not Bit) test the state of any addressable bit in a similar manner. A fifth instruction combines the Jump on Bit and Clear operations. "JBC bit. rei" conditionally branches to the indicated address, then clears the bit in the same two cycle instruction. This operation is the same as the MCS-48 "JTF" instructions. CLEAR DESTINATION . BIT The so-called "Bit Test" instructions implemented on many other microprocessors simply perform the logical-AND operation between a byte variable and a constant mask, and set or clear a zero flag depending on the result. This is essentially equivalent to the 8051 "MOY C.bit" instruction. A second instruction is then needed to conditionally branch based on the state of the zero flag. This does not constitute abstract bit-addressing in the MCS-51 sense. A flag exists only as a field 203830-4 Figure 8. Bit Transfer Instruction Operation 2-40 AP·70 within a register: to reference a bit the programmer must know and specify both the encompassing register and the bit's position therein. This constraint severely limits the flexibility of symbolic bit addressing and reduces the machine's code-efficiency and speed. Table 3. Other Instructions Affecting the Carry Flag Byte eyc Mnemonic Description ADD A,Rn Add register to 1 Accumulator Add direct byte to 2 ADD A,direct Accumulator ADD A,@Ri Add indirect RAM to Accumulator ADD A,#data Add immediate data 2 to Accumulator Add register to ADDC A,Rn Accumulator with Carry flag Add direct byte to AD DC A,direct 2 Accumulator with Carry flag ADDC A,@Ri Add indirect RAM to Accumulator with Carry flag AD DC A,#data Add immediate data 2 to Acc with Carry flag Subtract register from SUBB A,Rn Accumulator with borrow Subtract direct byte 2 SUBB A,direct from Acc with borrow SUBB A,@Ri Subtract indirect RAM from Acc with borrow SUBB A, # data Subtract immediate 2 data from Acc with borrow Multiply A & B 4 MUL AB DIV AB Divide A by B 4 DA A Decimal Adjust 1 Accumulator Interaction with Other Instructions., The carry flag is also affected by the instructions listed in Table 3. It can be rotated through the accumulator, and altered as a side effect of arithmetic instructions. Refer to the User's Manual for details on how these instructions operate. Simple Instruction Combinations By combining general purpose bit operations with certain addressable bits, one can "custom build" several hundred useful instructions. All eight bits of the PSW can be tested directly with conditional jump instructions to monitor (among other things) parity and overflow status. Programmers can take advantage of 128 software flags to keep track of operating modes, resource usage, and so forth. The Boolean instructions are also the most efficient way to control or reconfigure peripheral and I/O registers. All 32 I/O lines become "test pins," for example, tested by conditional jump instructions. Any output pin can be toggled (complemented) in a single instruction cycle. Setting or clearing the Timer Run flags (TRO and TRI) turn the timer/counters on or off; poIling the same flags elsewhere lets the program determine if a timer is running. The respective overflow flags (TFO and TFI) can be tested to determine when the desired period or count has elapsed, then cleared in preparation for the next repetition. (For the record, these bits are all part of the TCON register, Figure 7a. Thanks to symbolie bit addressing, the programmer only needs to remember the mnemonic associated with each function. In other words, don't bother memorizing control word layouts.) In the MCS-48 family, instructions corresponding to some of the above functions require specific opcodes. Ten different opcodes serve to clear complement the software flags FO and FI, enable/disable each interrupt, and start/stop the timer. In the 8051 instruction set, just three opcodes (SETB, CLR, CPL) with a direct bit address appended perform the same functions. Two test instructions (JB and JNB) can be combined with bit addresses to test the software flags, the 8048 I/O pins TO, TI, and INT, and the eight accumulator bits, replacing IS more different instructions. RLC A RRC A Rotate Accumulator Left through the Carry flag Rotate Accumulator Right through Carry flag Compare,direct byte to Acc & Jump if Not Equal Compare immediate CJNE A, #data.rel to Acc & Jump if Not Equal CJNE Rn, # data. rei Compare immed to register & Jump if Not Equal CJNE @Ri,#data.rel Compare immed to indirect & Jump if Not Equal CJNE A,direct.rel Table 4a shows how 8051 programs implement software flag and machine control functions associated with special opcodes in the 8048. In every case the MCS-51 solution requires the same number of machine cycles, and executes 2.5 times faster. All mnemonics copyrighted 2-41 @ 3 2 3 2 3 2, 3 2 Intel Corporation 1980. inter AP-70 Table 4a. Contrasting 8048 and 8051 Bit Control and Testing Instructions 8048 Instruction Flag Control CLR C CPL FO 8x51 Instruction Bytes Cycles ,...Sec 1 1 1 1 2.5 2.5 CLR CPL C FO 2 Flag Testing _JNC offset JFO offset JB7 offset 2 2 2 2 2 2 5.0 5.0 5.0 JNC JB JB rei FO.rel ACC.7.rel 3 3 2 2 2 Peripheral Polling JTO offset JN1 offset JTF offset 2 2 2 2 2 2 5.0 5.0 5.0 JB JNB JBC TO.rel INTO.rel TFO.rel 3 3 3 2 2 2 1 1 1 2.5 2.5 2.5 SETB SETB CLR TRO EXO ETO 2 2 2 1 1 1 Machine and Peripheral Control STRT T 1 EN 1 1 DIS TCNT1 1 Bytes Cycles & ,...Sec 1 1 1 2 Table 4b. Replacing 8048 Instruction Sequences with Single 8x51 Instructions 8048 Instruction Flag Control Set carry CLR C CPL C Set Software Flag CLR FO CPL FO Bytes Cycles p.Sec 8051 Instruction Bytes Cycles & ,...Sec = 2 2 5.0 SETB C 1 1 = 2 2 5.0 SETB FO 2 1 Turn Off Output Pin P1.#OFBH ANL = 2 2 5.0 CLR P1.2 2 1 Complement Output Pin IN A.P1 A.#04H XRL OUTL P1.A = 4 6 15.0 CPL P1.2 2 1 Clear Flag in RAM RO.#FLGADR MOV A.@RO MOV A.#FLGMASK ANL @RO.A MOV = 6 6 15.0 CLR USER 2 1 2·42 FLG AP-70 Table 4b. Replacing 8048 Instruction Sequences with Single 8x51 Instructions (Continued) 8048 Instruction Bytes 8x51 Instruction Bytes Cycles & ].LSec FO.rel 3 2 JNB ACC.7.rel 3 2 12.5 JNB P1.3.rel 3 2 10.0 JB INTO.rel 3 2 Cycles ].LSec Flag Testing: Jump if Software Flag is 0 JFO $+4 JMP offset = 4 4 10.0 JNB Jump if Accumulator bit is 0 CPL A JB7 offset CPL A = 4 4 10.0 Peripheral Polling Test if Input Pin is Grounded IN A.P1 CPL A JB3 offset = 4 5 Test if Interrupt Pin is High JN1 $+4 offset JMP = 4 4 3.0 BOOLEAN PROCESSOR APPLICATIONS So what? Then what does all this buy you? Qualitatively, nothmg. All the same capabilities could be (and often have been) implemented on other machines using awkward sequences of other basic operations. As mentioned earlier, any CPU can solve any problem given enough time. Quantitatively, the differences between a solution allowed by the 80S I and those required by previous architectures are numerous. What the 8051 Family buys you is a faster, cleaner, lower-cost solution to microcontroller applications. Combining Boolean and byte-wide instructions can produce great synergy. An MCS-SI based application will prove to be: o simpler to write since the architecture correlates more closely with the problems being solved: • easier to debug because more individual instructions have no unexpected or undesirable side-effects: • more byte efficient due to direct bit addressing and program counter relative branching: • faster running because fewer bytes of instruction need to be fetched and fewer conditional jumps are processed: • lower cost because of the high level of system-integration within one component. These rather unabashed claims of excellence shaH not go unsubstantiated. The rest of this chapter examines less trivial tasks simplified by the Boolean processor. The first three compare the 8051 with other microprocessors; the last two go into 80S I-based system designs in much greater depth. The opcode space freed by condensing many specific 8048 instructions into a few general operations has been used to add new functionality to the MCS-51 architecture-both for byte and bit operations. 144 software flags replace the 8048's two. These flags (and the carry) may be directly set, not just cleared and complemented, and all can be tested for either state, not just one. Operating mode bits previously inaccessible may be read, tested, or saved. Situations where the 80S I instruction set provides new capabilities are contrasted with 8048 instruction sequences in Table 4b. Here the 80S I speed advantage ranges from Sx to ISx! \ Design Example # 1-Bit Permutation First off, we'll use the bit-transfer instructions to permute a lengthy pattern of bits. 2-43 AP-70 Different microprocessor architectures would best implement this type of permutation in different ways. Most approaches would share the steps of Figure lOa: • Initialize the Permutation Buffer to default state (ones or zeroes): A steadily increasing number of data communication products use encoding methods to protect the security of sensitive information. By law, interstate financial - transactions involving the Federal banking system must be transmitted using the Federal Information Processing Data Encryption Standard (DES). • Isolate the state of a bit of a byte from the Key Buffer. Depending on the, CPU, this might be accomplished by rotating a word of the Key Buffer through a carry flag or. testing a bifin memory or an accumulator against a,mask byte: • Perform' a conditional jump based on the carry or zero flag if the Permutation Buffer default state is correct: Basically, the DES combines eight bytes of "plaintext" data (in binary, ASCII, or any other format) with a 56bit "key", producing a 64-bit encrypted value for transmission. 'At the receiving end the same algorithm is applied to the incoming data using the same key, reproducing the original eight byte message. The algorithm used for these permutations is fixed; different user-defined keys ensure data privacy. • Otherwise reverse the corresponding bit in the permutation buffer with logical operations and mask bytes. It is not the purpose of this note to describe the DES in any detail. Suffice it to say that encryption/decryption is a long, iterative process consisting of rotations, exclusive -OR operations, function table look-ups, and an extensive (and quite bizarre) sequence of bit permutation, packing, and unpacking steps. (For further details refer to the June 21, 1979 issue of Electronics magazine.) The bit manipulation steps are included, it is rumored, to impede a general purpose digital supercomputer trying to "break" the code. Any algorithm implementing the DES with previous' generation microprocessors would spend virtually all of its time diddling bits. Each step above may require several instructions. The iast three steps must be repeated for all 48 bits. Most microprocessors would spend 300 to 3,000 microseconds 'on each of the 16 iterations. Notice, though, that this flow chart looks a lot like Figure 8. The Boolean Processor can permute bits by simply moving them from the source to the carry to the destination-a total of two instructions taking four bytes and three microseconds per bit. Assume the Shifted Key Buffer and Permutation Buffer both reside in bit-addressable RAM, with the bits of the former assigned symbolic names SKB_1, SKB_2, ... SKB_ 56, and that the bytes of the latter are named PB_1, ... PB_8. Then working from Figure 9, the software for the permutation algorithm would be that of Example 1a. The total routine length would be 192 bytes, requiring 144 microseconds. The bit manipulation performed is typified by the Key Schedule Calculation represented in Figure 9. This step is repeated 16 times for each key used in the course of a transmission. In essence, a seven-byte, 56-bit "Shifted Key Buffer" is transformed into an eight-byte, "Permutation Buffer" without altering the shifted Key. The arrows in Figure 9 indicate a few of the translation steps. Only six bits of each byte of the Permutation Buffer are used; the. two high-order bits of each byte are cleared. This means only 48 of the 56 Shifted Key Buffer bits are used in anyone iteration. Permuted and Shifted 56-Bit Key Buffer ~ ~ -----------------~-----------------~" "------------------~-----------------14151117 PERMUTATION BYTE 1 PERM BYTE 2 21 PERM BYTE 3 3233:M PERM BYTE 4 BYTE 5 BYTEe PERM BYlEr PERM 8YlE8 203830-5 48-Bit Key Kr Figure 9. DES Key Schedul,e Transformation 2-44 AP·70 REPEAT FOR EACH alTOF SHinED KEY BUFFER SET PERMUTATION (LEAVE PERMUTATION BUFFER BIT PC2111 BUFFER BIT 148 TIMESI CLEAREDI 203830-6 Figure 10a. Flowchart for Key Permutation Attempted with a Byte Processor 2-45 inter AP-70 I ~ I CLEAR ACCUMULATOR LOAD BIT MAPPED ONTO BIT 5 OF PERMUTATION BYTE INTO CARRY I I ROTATE LEFT INTO ACC. LOAD BIT MAPPED ONTO BIT 4 OF PERMUTATION BYTE INTO CARRY I I ROTATE LEFT INTO ACC. , REPEAT FOR EACH BYTE OF PERMUTATION BUFFER (8 TIMES) , LOAD BIT MAPPED ONTO BIT 0 OF PERMUTATION BYTE INTO CARRY I , , J ROTATE LEFT INTO ACC. STORE ACC. INTO PERMUTATION BUFFER I 203830-7 Figure 10b. DES Key Permutation with Boolean Processor 2-46 infef Ap·70 The algorithm of Figure lOb is just slightly more efficient in this time-critical application and illustrates the synergy of an integrated byte and bit processor. The bits needed for each byte of the Permutation Buffer are assimilated by loading each bit into the carry (1 J.l.s.) and shifting it into the accumulator (1 J.l.s.). Each byte is stored in RAM when completed. Forty-eight bits thus need a total of 112 instructions, some of which are listed in Example lb. Example I. DES Key Permutation Software. a.) "Brute Force" technique Worst-case execution time would be 112 microseconds, since each instruction takes a single cycle. Routine length would also decrease, to 168 bytes. (Actually, in the context of the complete encryption algorithm, each permuted byte would be processed as soon as it is assimilated-saving memory and cutting execution time by another 8 J.l.s.) To date, most banking terminals and other systems using the DES have needed special boards or peripheral controller chips just for the encryption/decryption process, and still more hardware to form a serial bit stream for transmission (Figure Ila). An 8051 solution could pack most of the entire system onto the one chip (Figure lib). The whole DES algorithm would require less than one-fourth of the on-chip program memory, with the remaining bytes free for operating the banking terminal (or whatever) itself. MOV MOV MOV MOV MOV MOV MOV MOV C,SKB_I PB_I.I, C C,SKB_2 PB_4.0,C C,SKB_3 PB_2.5,C C,SKB_4 PB_I.O,C MOV MOV MOV MOV C,SKB_55 PB_5.0,C C,SKB_56 PB_7.2,C b.) Using Accumulator to Collect Bits Moreover, since transmission and reception of data is performed through the on-board UART, the unencrypted data (plaintext) never even exists outside the microcomputer! Naturally, this would afford a high degree of security from data interception. 2-47 CLR MOV RLC MOV RLC MOV RLC MOV RLC MOV RLC MOV RLC MOV A C,SKB_14 A C,SKB_17 A C, SK1Lll A C,SKB_24 A C,SKB_I A C,SKB_5 A PB_I,A MOV RLC MOV RLC MOV C,SKB_29 A C,SKB_32 A PB_B,A AP·70 CONTROL AND ADDRESS BUSSES DISPLAY CPU RAM DATA ENCRY' PTiON UNIT ROM KEYBOARD l I I TO MODEM SYSTEM DATA BUS 203830-8 a.) Using Multi-Chip Processor Technology DISPLAY r'".. P2 T.D 8051 PO r R.D ... TO MODEM KEYBOARD ~ . P1 203830-9 b.) Using One Single-Chip Microcomputer Figure 11. Secure Banking Terminal Block Diagram Design Example # 2-Software Serial 1/0 An exercise often imposed on beginning microcomputer students is to write a program simulating a UART. Though doing this with the 8051 Family may appear to be a moot point (given that the hardware for a full UART is on-chip), it is still instructive to see how it would be done, and maintains a product line tradition. As it turns out, the 8051 microcomputers can receive or transmit serial data via software very efficiently using the Boolean instruction set. Since any I/O pin may be a serial input or output, several serial links could be maintained at once. 2-48 Figures 12a and 12b show algorithms for receiving or transmitting a byte of·data. (Another section of program would invoke this algorithm eight times, synchronizing it with a start bit, clock signal, software delay, or timer interrupt.) Data is received by testing an input pin, setting the carry to the same state, shifting the carry into a data buffer, and saving the partial frame in internal RAM. Data is transmitted by shifting an output buffer through the carry, and generating each bit on an output pin. A side-by-side comparison of the software for this common "bit-banging" application with three different microprocessor architectures is shown in Table Sa and 5b. The 8051 solution is more efficient. than the others on every count! AP-70 PIN SET CARRY CLEAR CARRY 203830-10 a.) Reception 203830-11 b.) Transmission Figure 12. Serial 110 Algorithms 2-49 AP-70 Table 5. Serial 1/0 Programs for Various Microprocessors a.) Input Routine. BOBS I~ A"I .IZ CMC 10. I XI MOV RR MOV 8051 B04B SFRI'OR I MASK 10 CI R .1"10 CPI MOV MOV RRC MOV HI..SERBlIF A.M M.A C 10 (" RfI .• SFRBI'r A.@RO A @RfI.A MO\' C.SERI'I" MOV RRC MOV A.S[RBl·r A SERBIIF.A RFSlll TS: K I"STRITTiO~S 14 BYTES 56 S rATES 19 uSEC 7 I~S I R l TTlO~S 9 BY I FS 9 CYCI.ES 12.5 uSFC 4 I,\S rRl'CTIO'\S 7 BYTES 4 CYCI.FS 4 uSFC B048 8051 b.) Output Routine. BOBS I XI MOV RR MOV 1:-; .IC 10. A:-;I .IMP HI: ORI O'"l:OIIT HI .SfRBlI~ A.M M.A SERPORT HI 'lOT MASK C'IT MASK SFRI'OR r HI: ("'" RO.'SERBII~ MOV MOV RRC MOV A.@RO A @RO.A .IC A'\1. .IMP ORI. HI SERPRT.• '\oT MASK C:-;T SERPRT.'MASK MOV RRC MOV A.sERBl'F A SERBl'F.A MOV SERPI'\.C RESULTS: 10lNSTRUCTIO)l;S 20 BYTES 72 STATES 24 uSEC K I)I;STRlICTiONS 13 BYTES II CYCLES 27.5 uSEC Design Example # 3-Combinatorial Logic Equations Next we'll look at some simple uses for bit-test instructions and logical operations. (This example is also pre,sented in Application Note AP-69.) Virtually all hardware designers have solved complex functions using combinatorial logic. While the hardware involved may vary from relay logic, vacuum tubes, or TTL or to more esoteric technologies like fluidics, in each case the goal is the same: to solve a problem represented by a logical function of several Boolean variables. 4 INSTR UCTIONS 7 BYTES 5 CYCLES 5 uSEC 203830-30 Figure 13 shows TTL and relay logic diagrams for a function of the six variables U through Z. Each is a solution of the equation. Q. = (U • (V + W)) + (X. '1) +Z Equations of this sort might be reduced using Karnaugh Maps or algebraic techniques, but that is not the purpose of this examp1e. As the logic complexity increases, so does the difficulty of the reduction process. Even a minot; change to the function equations as the design evolves would require tedious re-reduction from scratch. 2-50 AP-70 u v w x r----a y z Q = (U • (V 203830-12 + W)) + (X. Y) + Z a.) Using TTL v u y CR1 CR2 a z 203830-13 b.) Using Relay Logic Figure 13. Hardware Implementations of Boolean Functions For the sake of comparison we will implement this function three ways, restricting the software to three proper subsets of the MCS-Sl instruction set. We will also assume that U and V are input pins from different input ports, Wand X are status bits for two peripheral controllers, and Y and Z are software flags set up earli· er in the program. The end result must be written to an output pin on some third port. The first two implementations follow the flow-chart shown in Figure 14. Program flow would embark on a route down a test-and-branch tree and leaves either the "True" or "Not True" exit ASAP-as soon as the proper result has been determined. These exits then rewrite the output port with the result bit respectively one or zero. 2-51 AP-70 The code which results is cumbersome and error prone. It would be difficult to prove whether the software worked for all input combinations in programs of this sort. Furthermore, execution time will vary widely with input data. Thanks to the direct bit-test operations, a single instruction can replace each move mask conditional jump sequence in Example 2a, but the algorithm would be equally convoluted (see Example 2b). To lessen the confusion "a bit"' each input variable is assigned a symbolic name . . A more elegant and efficient implementation (Example 2c) strings together the Boolean ANL and ORL functions to generate the output function with straight-line code. When finished, the carry flag contains the result, which is simply copied out to the destination pin. No flow chart is needed-<:ode can be written directly from the logic diagrams in Figure 14. The result is simplicity itself: fast, flexible, reliable, easy to design, and easy to debug. FUNCTION IS FALSE CLEAR FUNCTION IS TRUE An 8051 program can simulate an N-input AND or· OR gate with at most N + 1 lines of source programone for each input and one line to store the results. To simulate NAND and NOR gates, complement the carry after computing the function. When some inputs to' the gate have "inversion bubbles", perform the ANL or ORL operation on inverted operands. When the first input is inverted, either load the operand into the carry and then complement it, or use DeMorgan's Theorem to convert the gate to a different form. Example 2. Software Solutions to Logic Function of Figure 13. a a.) Using only byte-wide logical instructions :BFUNCI 203830-14 Figure 14. Flow Chart for Tree-Branching Algorithm Other digital computers must solve equations of this type with standard word-wide logical instructions and conditional jumps. So for the first implementation, we won't use any generalized bit-addressing instructions. As we shall soon see, being constrained to such an instruction subset produces somewhat sloppy software solutions. MCS-51 mnemonics are used in Example 2a: other machines might further cloud the situation by requiring operation-specific mnemonics like INPUT, OUTPUT, LOAD, STORE, etc., instead of the MOV mnemonic used for all variable transfers in the 8051 instruction set. SOLVE RANDOM LOGIC FUNCTION OF 6 VARIABLES BY LOADING AND MASKING THE APPROPRIATE BITS IN THE ACCUMULATOR. THEN EXECUTING CONDITIONAL JUMPS BASED ON ZERO CONDITION. (APPROACH USED BY BYTE-ORIENTED ARCHITECTURES. 1 BYTE AND MASK VALUES CORRESPOND TO RESPECTIVE BYTE ADDRESS AND BIT POSITIONS. OUTBUF DATA 22H ;OUTPUT PIN STATE MAP 2-52 inter TESTV: TESTU: TESTX: TESTZ: CLRQ: SETQ: OUTQ: AP-70 MOV A,P2 ANL A,#OOOOOlOOB JNZ TESTU MOV A,TCON ANL A,#OOlOOOOOB JZ TESTX MOV A,Pl ANL A,#OOOOOOlOB JNZ SETQ MOV A,TCON ANL A,#OOOOlOOOB JZ TESTZ MOV A,20H ANL A,#OOOOOOOlB JZ SETQ MOV A,21H ANL A,#OOOOOOlOB JZ SETQ MOV A,OUTBUF ANL A,#llllOlllB JMP OUTQ MOV A,OUTBUF ORL A,#OOOOlOOOB MOV OUTBUF,A MOV P3,A U V W X Y Z Q BIT BIT BIT BIT BIT BIT BIT , Pl.l P2.2 TFO IEl 20H.O 21H.l P3.3 TEST_V: JB V,TEST_U JNB W,TEST_X TEST_U: JB U,SET_Q TEST_X: JNB X,TEST_Z JNB Y,SET_Q TEST_Z: JNB Z,SET_Q CLR_Q: CLR Q JMP NXTTST SET_Q: SETB Q NXTTST:(CONTINUATION OF : PROGRAM) c.) Using logical operations on Boolean variables :FUNC3 SOLVE A RANDOM LOGIC FUNCTION OF 6 VARIABLES USING STRAIGHT_LINE LOGICAL INSTRUCTIONS ON MCS-51 BOOLEAN VARIABLES. b.) Using only bit-test instructions ; :BFUNC2 SOLVE A RANDOM LOGIC FUNCTION OF 6 VARIABLES BY DIRECTLY POLLING EACH BIT. (APPROACH USING MCS-51 UNIQUE BIT-TEST INSTRUCTION CAPABILITY.) SYMBOLS USED IN LOGIC DIAGRAM ASSIGNED TO CORRESPONDING 8x51 BIT ADDRESSES. MOV ORL ANL MOV MOV ANL ORL ORL C,V C,W C,U FO,C C,X C,Y C,FO C,Z MOV Q,C 2-53 ;OUTPUT OF OR GATE ;OUTPUT OF TOP AND GATE ;SAVE INTERMEDIATE STATE ;OUTPUT OF BOTTOM AND GATE ;INCLUDE VALUE SAVED ABOVE ;INCLUDE LAST INPUT ;VARIABLE ;OUTPUT COMPUTED RESULT inter AP-70 An upper-limit can be placed on the complexity of software to simulate a large number of gates by summing the total number of inputs and outputs. The actual total should be somewhat shorter, since calculations can be "chained," as shown. The output of one gate is often the first input to another, bypassing the intermediate variable to eliminate two lines of source. Imagine the three position turn lever on the steering column as a single-pole, triple-throw toggle switch. In its central position all contacts are open. In the up or down positions contacts close causing corresponding lights in the rear of the car to blink. So far very simple. Two more turn signals blink in the front of the car, and two others in the dashboard. All six bulbs flash when an emergency switch is closed. A thermo-mechanical relay (accessible under the dashboard in case it wears out) causes the blinking. Design Example # 4-Automotive Dashboard Functions Now let's apply these techniques to designing the software for a complete controller system. This application is patterned after a familiar real-world· application which isn't nearly as trivial as it might first appear: automobile turn signals. Applying the brake pedal turns the tail light filaments on constantly ... unless a turn is in progress, in which case the blinking tail light is not affected. (Of course, the front turn signals and dashboard indicators are not affected by the brake pedal.) Table 6 summarizes these operating modes. Table 6. Truth Table for Turn-Signal Operation Input Signals Output Signals Right Turn Switch Left Front & Dash Right Front & Dash Left Rear Right Rear Off Off Blink Blink Blink Blink Off Off Blink Blink Blink Blink Off Blink Off Blink Blink Blink Off Blink Off Blink Blink Blink ' Off Off Blink Blink Blink Blink On On Blink On On Blink Off Blink Off Blink Blink Blink ' On Blink On On Blink On Brake Switch Emerg. Switch Left Turn Switch 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 0 1 0 1 0 1 1 1 0 0 0 0 0 1 0 1 0 1 1 1 1 0 0 1 0 1 1 1 0 1 0 2-54 Ap·70 But we're not done yet. Each of the exterior turn signal (but not the dashboard) bulbs has a second, somewhat dimmer filament for the parking lights. Figure 15 shows TTL circuitry which could control all six bulbs. The signals labeled "High Freq." and "Low Freq." represent two square-wave inputs. Basically, when one of the turn switches is closed or the emergency switch is activated the low frequency signal (about 1 Hz) is gated through to the appropriate dashboard indicator(s) and turn signal(s). The rear signals are also activated when the brake pedal is depressed provided a turn is not being made in the same direction. When the parking light switch is closed the higher frequency oscillator is gated to each front and rear turn signal, sustaining a low-intensity background level. (This is to eliminate the need for additional parking light filaments.) In most cars, the switching logic to generate these functions requires a number of multiple-throw contacts. As many as 18 conductors thread the steering column of some automobiles solely for turn-signal and emergency blinker functions. (The author discovered this recently to his astonishment and dismay when replacing the whole assembly because of one burned contact.) A multiple-conductor wiring harness runs to each corner of the car, behind the dash, up the steering column, and down to the blinker relay below. Connectors at L. TURN EMERG each termination for each filament lead to extra cost and labor during construction, lower reliability and safety, and more costly repairs. And considering the system's present complexity, increasing its reliability or detecting failures would be quite difficult. There are two reasons for going into such painful detail describing this example. First, to show that the messiest part of many system designs is determining what the controller should do. Writing the software to solve these functions will be comparatively easy. Secondly, to show the many potential failure points in the system. Later we'll see how the peripheral functions and intelligence built into a microcomputer (with a little creativity) can greatly reduce external interconnections and mechanical part count. The Single-Chip Solution The circuit shown in Figure 16 indicates five input pins to the five input variables-left-turn select, right-turn select, brake pedal down, emergency switch on, and parking lights on. Six output pins turn on the front, rear, and dashboard indicators for each side. The microcomputer implements all logical functions through software, which periodically updates the output signals as time elapses and input conditions change. 1---....- - - - - - L. DASH L. FRNT BRAKE L. REAR R.TURN }--....+----- R. DASH R.FRNT R.REAR PARK --------------~---~~ LO. FREO. OSCILLATOR HI. FREO. OSCILLATOR Figure 15. TTL Logic Implementation of Automotive Turn Signals 2-55 203830-15 inter AP-70 +12V +12V 8051 LE" FRONT BRAKE PEDAL Pl.0 EMERGENCY SWITCH Pl:l PARKING LIGHTS Pl.2 LE" TURN SWITCH Pl.5 RIGHT FRONT P1.I LE" OASHIOA.IID P1.7 RIGHT DASHBOARD Pl.3 P2.0 RIGHT Pl.4 .... LE" REAR P2.1 P2.2 .)r--~~--' RIGHT REAR • MODE SENSORS CONTROLLER SIGNAL CONDITIONING OUTPUT BUFFERS SIGNAL BULBS 203830-16 Figure 16. Microcomputer Turn-Signal Connections Design Example # 3 demonstrated that symbolic addressing with user-defined bit names makes code and documentation easier to write and maintain. Accordingly, we'll assign these I/O pins names for use throughout the program. (The format of this example will differ somewhat from the others. Segments of the overall program will be preSented in sequence as each is described.) INPUT PIN DECLARATIONS: ;(ALL INPUTS ARE POSITIVE-TRUE LOGIC) BRAKE BIT Pl.O ;BRAKE PEDAL ;DEPRESSED EMERG BIT Pl.l ;EMERGENCY BLINKER ;ACTIVATED PARK BIT Pl.2 ;PARKING LIGHTS ON I_TURN BIT Pl.3 ;TURN LEVER DOWN R_TURN BIT P1.4 ;TURN LEVER UP OUTPUT PIN DECLARATIONS: BIT Pl.5 ;FRONT LEFT-TURN ;INDICATOR R_FRNT BIT Pl.6 ;FRONT RIGHT-TURN ;INDICATOR I_DASH BIT Pl.7 ;DASHBOARD LEFT-TURN ;INDICATOR I~FRNT R_DASH BIT P2.0 ;DASHBOARD RIGHT;TURN INDICATOR I_REAR BIT P2.l.;REAR LEFT-TURN ;INDICATOR R_REAR BIT P2.2 ;REAR RIGHT-TURN ;INDICATOR Another key advantage of symbolic addressing will appear further on in the design cycle. The locations of cable connectors, signal conditioning circuitry, voltage regulators, heat sinks, and the like all affect P.C. board layout. It's quite likely that the somewhat arbitrary pin .assignment defined early in the software design cycle will prove to be less than optimum; rearranging the I/O pin assignment could well allow a more compact module, or eliminate costly jumpers on a single-sided board. (These considerations apply especially to automotive and other. cost-sensitive applications needing singlechip controllers.) Since other architectures mask bytes or use "clever" algorithms to isolate bits by rotating them into the carry, re-routing an input signal (from bit I of port I, for example, to bit 4 of port 3) could require . extensive modifications throughout the software. The Boolean Processor's direct bit addressing makes such changes absolutely trivial. The number of the port containing the pin is irrelevent, and masks and complex 2-56 intJ AP-70 program structures are not needed. Only the initial Boolean variable declarations need to be changed; ASM51 automatically adjusts all addresses and symbolic references to the reassigned variables. The user IS assured that no additional debugging or software verification will be required. ;INTERRUPT RATE SUBDIVIDER SUB_DIV DATA 20H ;HIGH-FREQUENCY OSCILLATOR BIT HLFREQ BIT SUB_DIV,O ;LOW-FREQUENCY OSCILLATOR BIT LO_FREQ BIT SUB_DIV,7 JMP ORG INIT "tuned" to approximately I Hz for the turn- and emergency-indicator blinking rate. Loading THO with -16 will cause an interrupt after 4.096 ms. The interrupt service routine reloads the high-order byte of timer 0 for the next interval, saves the CPU registers likely to be affected on the stack, and then decrements SUB_DIY. Loading SUB_DIY. with 244 initially and each time it decrements to zero will produce a 0.999 second period for the highest-order bit. ORG MOV PUSH PUSH PUSH DJNZ MOV OOOOH ORG lOOH ;PUT TIMER 0 IN MODE 1 INIT; MOV TMOD,#OOOOOOOlB ;INITIALIZE TlMER REGISTERS MOV TLO,#O MOV THO,#-l6 ;SUBDIVIDE INTERRUPT RATE BY 244 MOV SUB_DIV,#244 ;ENABLE TIMER INTERRUPTS SETB ETO ;GLOBALLY ENABLE ALL INTERRUPTS SETB EA ;START TIMER SETB TRO OOOBH ;TIMER 0 SERVICE VECTOR THO,#-l6 PSW ACC B SUB_DIV,TOSERV SUB_DIV,#244 The code to sample inputs, perform calculations, and update outputs-the real "meat" of the signal controller algorithm-may be performed either as part of the interrupt service routine or as part of a background program loop. The only concern is that it must be executed at least serveral dozen times per second to prevent parking light flickering. We will assume the former case, and insert the code into the timer 0 service routine. First, notice from the logic diagram (Figure 15) that the subterm (PARK • H_FREQ), asserted when the parking lights are to be on dimly, figures into four of the six output functions. Accordingly, we will first compute that term and save it in a temporary location named "DIM". The PSW contains two general purpose flags: FO, which corresponds to the 8048 flag of the same name, and PSW.l. Since the PSW has been saved and will be restored to its previous state after servicing the interrupt, we can use either bit for temporary storage. ;(CONTINUE WITH BACKGROUND PROGRAM) ;PUT TIMER 0 IN MODE 1 ;INITIALIZE TIMER REGISTERS ;SUBDIVIDE INTERRUPT RATE BY 244 ;ENABLE TIMER INTERRUPTS ;GLOBALLY ENABLE ALL INTERRUPTS ;START TIMER DIM BIT Timer 0 (one of the two on-chip timer counters) replaces the thermo-mechanical blinker relay in the dashboard controller. During system initialization it is configured as a timer in mode 1 by setting the least significant bit of the timer mode register (TMOD). In this configuration the low-order byte (TLO) is incremented every machine cycle, overflowing and incrementing the high-order byte (THO) every 256 J.Cos. Timer interrupt 0 is enabled so that a hardware interrupt will occur each time THO overflows. An eight-bit variable in the bit-addressable RAM array will be needed to further subdivide the interrupts via software. The lowest-order bit of this counter toggles very fast to modulate the parking lights: bit 7 will be 2-57 PSW.l ;DECLARE TEMP ;STORAGE FLAG MOV C,PARK ANL HLFREQ MOV DIM,C ;GATE PARKING ;LIGHT SWITCH ;WITH HIGH ;FREQUENCY ;SIGNAL ;AND SAVE IN ;TEMP. VARIABLE This simple three-line section of code illustrates a remarkable point. The software indicates in very abstract terms exactly what function is being performed, inde- AP-70 pendent of the hardware configuration. The fact that these three bits include an input pin, a bit within a program variable, and a software flag in the PSW is totally invisible to the programmer. ORL C,DIM 'MOV L_REAR, C Now generate and output the dashboard left tum signal. MOV C,L_TURN Now we have to go through a similar sequence for the right-hand equivalents to all the left-tum lights. This also gives us a chance to see how the code segments . above look when combined. ;SET CARRY IF ; TURN ;OR EMERGENCY ;SELECTED ;GATE IN 1 HZ ;SIGNAL ;AND OUTPUT TO ;DASHBOARD ORL C,EMERG ANL C,LO_FREQ MOV LDASH,C MOV C.R_TURN ORL ANL MOV To generate the left front tum signal we only need to add the parking light function in FO. But notice that the function in the carry will also be needed for the rear signal. We can save effort later by saving its current state in FO. MOV ORL MOV MOV FO,C MOV ;SAVE FUNCTION :SO FAR :ADD IN PARKING ;LIGHT FUNCTION ;AND OUTPUT TO :TURN SIGNAL ORL C,DIM MOV L_FRNT,C ANL ORL ORL Finally, the rear left tum signal should also be on when the brake pedal is depressed, provided a left tum is not in progress. MOV C,BRAKE ANL C,L_TURN ORL C,FO ;AND PARKING ;LIGHT FUNCTION ;AND OUTPUT TO ;TURN SIGNAL MOV ;SET CARRY H;TURN C.EMERG ;OR EMERGENCY ;SELECTED C,LO_FREQ ;IF SO. GATE IN 1 ;HZ SIGNAL R_DASH.C ;AND OUTPUT TO ;DASHBOARD . FO.C ;SAVE FUNCTION ;SO FAR C.DIM ;ADD ni PARKING. ;LIGHT FUNCTION R_FRNT.C ;AND OUTP~T TO ;TURN SIGNAL C.BRAKE ;GATE BRAKE :PEDAL SWITCH C. R_TURN' ;WITH TURN ;LEVER C.FO ;INCLUDE TEMP. ;VARIABLE FROM ;DASH C.DIM ;AND PARKING ;LIGHT FUNCTION R_REAR.C ;AND OUTPUT TO ;TURN SIGNAL (The perceptive reader may notice that simply rearrapging the steps could eliminate one instruction from each sequence.) ;GATE BRAKE ;PEDAL SWITCH ;WITH TURN ;LEVER ;INCLUDE TEMP. ;VARIABLE FROM DASH Now that all six bulbs are in the proper states, we can return from the interrupt routine, and the program is finished. This code essentially needs to reverse the status saving steps at the beginning of the interrupt. Table 7 Non-Trivial Duty Cycles Sub_Div Bits 7 X X X X X X X X 6 X X X X X X X X 5 X X X X X X X X 4 X X X X X X X X 3 X X X X X X X X 12.5% 25.0% 37.5% 1 Off Off Off Off Off Off 0 Off Off Off Off Off Off Off On On Off Off Off Off Off On On On 2 0 0 0 0 1 0 0 1 0 1 0 0 1 1 1 1 1 On 1 1 0 0 1 0 1 2-58 Duty Cycles 50.0% 62.5% Off Off Off Off On On On On Off Off Off On On On On On 75.0% 87.5% Off Off On On On On On On Off On On On On On On On infef POP B AP-70 driver circuits combining shift-register inputs with high drive level outputs have been introduced recently. ;RESTORE CPU ;REGISTERS. POP ACC POP psw RETI Cascading multiple shift registers end-to-end will expand the number of outputs even further. The data rate in the I/O expansion mode is one megabaud, or 8 fLs. per byte. This is the mode which the serial port defaults to following a reset, so no initialization is required. Program Refillemellts. The luminescence of an incandescent light bulb filament is generally non-linear: the' 50% duty cycle of HI_FREQ may not produce the desired intensity. If the application requires, duty cycles of 25%, 75%, etc. are easily achieved by ANDing and ORing in additional low-order bits of SUB_DIY. For example, 30 H/ signals of seven different duty cycles could be produced by considering bits 2-0 as shown in Table 7. The only software change required would be to the code which sets-up variable DIM; MOV C,SUB_DIV.l;START WITH 50 ;PERCENT ANL C,SUB_DIV.O;MASK DOWN TO 25 , ;PERCENT ORL C,SUB_DIV.2;AND BUILD BACK TO ;62 PERCENT MOV DIM,C ;DUTY CYCLE FOR ;PARKING LIGHTS. The software for this technique uses the B register as a "map" corresponding to the different output functions. The program manipulates these bits instead of the output pins. After all functions have been calculated the B register is shifted by the serial port to the shift-register driver. (While some outputs may glitch as data is shifted through them, at 1 Megabaud most people wouldn't notice. Some shift registers provide an "enable" bit to hold the output states while new data is being shifted in.) This is where the earlier decision to address bits symbolically throughout the program is going to payoff. This major I/O restructuring is nearly as simple to implement as rearranging the input pins. Again, only the bit declarations need to be changed. LFRNT BIT B.O ;FRONT LEFT-TURN ;INDICATOR R_FRNT BIT B.l ;FRONT RIGHT-TURN ;INDICATOR LDASH BIT B.2 ;DASHBOARD LEFT-TURN ;INDICATOR R_DASH BIT B.3 ;DASHBOARD RIGHT-TURN ;INDICATOR LREAR BIT B.4 ;REAR LEFT-TURN ;INDICATOR R_REAR BIT B.5 ;REAR RIGHT-TURN ;INDICATOR Interconnections increase cost and decrease reliability. The simple buffered pin-per-function circuit in Figure 16 is insufficient when many outputs require higherthan-TTL drive levels. A lower-cost solution uses the 8051 serial port in the shift-register mode to augment I/O. In mode 0, writing a byte to the serial port data buffer (SBUF) causes the data to be output sequentially through the "RXD" pin while a burst of eight clock pulses is generated on the "TXD" pin. A shift register connected'to these pins (Figure 17) will load the data byte as it is shifted out. A number of special peripheral +12V 8051 P3.0 I------""i DATA 07 P3.1 I - - - -.....~ eLK 01 00 8·BIT SHIFT REGISTER 203830-17 Figure 17. Output Expansion Using Serial Port 2-59 AP-70 The original program to compute the functions need not change. After computing the output variables, the control map is transmitted to the buffered shift register through the serial port. MOV SBUF,B ;LOAD BUFFER AND TRANSMIT The Boolean Processor solution holds a number of advantages over older methods. Fewer switches are re. quired. Each is simpler, requiring fewer poles and lower current contacts. The flasher relay is eliminated entirely. Only six filaments are driven, rather than 10. The wiring harness is therefore simpler and less expensive-one conductor for each of the six lamps and each of the five sensor switches. The fewer conductors use far fewer connectors. The whole system is more reliable. And since the system is much simpler it would be feasible to implement redundancy and or fault detection on the four main turn indicators. Each could still be a standard double filament bulb, but with the filaments driven in parallel to tolerate single-element failures .. Even with redundancy, the lights will eventually fail. To handle this inescapable fact current or voltage sensing circuits on each main drive wire can verify that each bulb and its high-current driver is functioning properly. Figure 1~ shows one such circuit. Assume all of the lights are turned on except one: i.e., all but one of the collectors are grounded. For the bulb which is turned off, if there is continuity from + 12V through the bulb base and filament, the control wire, all connectors, and the P.C. board traces, and if the transistor is indeed not shorted to ground, then the collector will be pulled to + 12V. This turns on the base of Q8 through the corresponding resistor, and grounds the input pin, verifying that the bulb circuit is operational. The continuity of each circuit can be checked by software in this way. WIRING HARNESS +12V I P1.5 ~-+-i'" P1.6 ~--+- PH I--+--r P2.0 1--+-('" .... P2.1 P2.2 ~-+-t' +5V TO I------t.-_ 203830-18 Figure 18 2-60 AP-70 The complete assembled program listing is printed in Appe~dix A. The resulting code consists of 67 program statements, not counting declarations and comments, which assemble into 150 bytes of object code. Each pass through the service routine requires (coincidently) 67 /-Ls plus 32 /-Ls once per second for the electrical test. If executed every 4 ms as suggested this software would typically reduce the throughput of the background program by less than 2%. Now turn all the bulbs on, grounding all the collectors. Q7 should be turned off, and the Test pin should be high. However, a control wire shorted to + 12V or an open-circuited drive transistor would leave one of the collectors at the higher voltage even now. This too would turn on Q7, indicating a different type offailure. Software could perform these checks once per second by executing the routine every time the software counter SUB_DIV is reloaded by the interrupt routine. Once a microcomputer has been designed into a system, new features suddenly become virtually free. Software could make the emergency blinkers flash alternately or at a rate faster than the turn signals. Turn signals could override the emergency blinkers. Adding more bulbs would allow multiple taillight sequencing and syncopation-true flash factor, so to speak. DJNZ SUB_DIV,TOSERV MOV SUB_DIV,#244 ;RELOAD COUNTER ;SET CONTROL ORL Pl,#lllOOOOOB ;OUTPUTS HIGH ORL P2,#00000111B CLR LFRNT ;FLOAT DRIVE ;COLLECTOR JB TO ,FAULT ;TO SHOULD BE ;PULLED LOW SETB L_FRNT ;PULL COLLECTOR ;BACK DOWN CLR L_DASH JB TO ,FAULT SETB L_DASH CLR L_REAR JB TO ,FAULT SETB L_REAR CLR R_FRNT JB TO ,FAULT SETB R_FRNT CLR R_DASH JB TO ,FAULT SETB R_DASH CLR R_REAR JB TO ,FAULT SETB R_REAR Design Example # 5-Complex Control Functions Finally, we'll mix byte and bit operations to extend the use of 8051 into extremely complex applications. Programmers can arbitrarily assign I/O pins to input and output functions only if the total does not exceed 32, which is insufficient for applications with a very large number of input variables. One way to expand the number of inputs is with a technique similar to multiplexed-keyboard scanning. Figure 19 shows a block diagram for a moderately complex programmable industrial controller with the following characteristics: • 64 input variable sensors: • 12 output signals: • Combinational and sequential logic computations: • Remote operation with communications to a host processor via a high-speed full-duplex serial link: • Two prioritized external interrupts: • Internal real-time and time-of-day clocks. ;WITH ALL COLLECTORS GROUNDED. TO SHOULD BE HIGH . ;IF SO. CONTINUE WITH INTERRUPT ROUTINE. . JB TO,TOSERV FAULT: ;ELECTRICAL ;FAILURE ;PROCESSING ;ROUTINE ;(LEFT TO ;READER'S ;IMAGINATION) TOSERV: ;CONTINUE WITH ; INTERRUPT ;PROCESSING While many microprocessors could be programmed to provide these capabilities with assorted peripheral support chips, an 8051 microcomputer needs no other integrated circuits! The 64 input sensors are logically arranged as an 8x8 matrix. The pins of Port 1 sequentially enable each column of the sensor matrix: as each is enabled Port 0 reads in the state of each sensor in that column. An eight-byte block in bit-addressable RAM remembers the data as it is read in so that after each complete scan . cycle there is an internal map of the current state of all sensors. Logic functions can then directly address the elements of the bit map. 2-61 intJ AP-70 +5V I"" fl.0UF 12M~Z ~ ~ XTAL2 )., 32 40 48 56 57 PO.l 2 - ~rss 58 PO.2 60 PO.4 61 PO.5 62 PO.6 8.8 f-~ 4 rs~ I- SENSOR MATRIX P3.5 P3.6 P3.7 PO.3 P2.0 P2.1 6 7 ASYNCHRONANS INTERRUPTS P3.4 PO.O 1 ~~ I I NTl 8051 RETURN LINES 16 24 I INTO - TXD I 8 - RXD SERIAL \ LINK 0 VCC RST XTALl 15 23 31 39 47 55 63 MACHINE ACTUATORS P2.2 PO.7 P2.3 t P2.4 ~ Pl.0 P2.5 Pl.l P2.6 Pl.2 P2.7 Pl.3 Pl.4 Pl.5 ALE Pl.6 PSEN f--- r--- N.C N.C. Pl.7 /~ VSS EA 'J:J SCAN LINES 203830-19 Figure 19. Block Diagram of 64-lnput Machine Controller The computer's serial port is configured as a nine-bit UART, transferring data at 17,000 bytes-per-second. The ninth bit may distinguish between address and data bytes. The 8051 serial port can' be configured to detect bytes with the address bit set, automatically ignoring all others. Pins INTO and INTI are interrupts configured respectively as high-priority, falling-edge triggered and low-priority, low-level triggered. The remaining 12 I/O pins output TTL-level control signals to 12 actuators. 2-62 There are several ways to implement the sensor matrix circuitry, all'logically similar. Figure 20a shows one possibility. Each of the 64 sensors consists of a pair of simple switch contacts in series with a diode to permit multiple contact closures throughout the matrix. The scan lines from Port 1 provide eight un-encoded active-high scan signals for enabling columns of the matrix. The return lines on rows where a contact is closed are pulled high and read as logic ones. Open return lines are pulled to ground by one of the 40 kfl. resistors and are read as zeroes. (The resistor values must be chosen to ensure all return lines are pulled above the 2.0V logic threshold, even in the worst-case, inter AP-70 where all contacts in an enabled column are closed.) Since PO is provided open-collector outputs and highimpedance MOS inputs its input loading may be considered negligible. The circuits in Figures 20b-20d are variations on this theme. When input signals must be electrically isolated from the computer circuitry as in noisy industrial environments, phototransistors can replace the switch diode pairs and provide optical isolation as in Figure 20b. Additional opto-isolators could also be used on the control output and special signal lines. Example 3. INPUT_SCAN: MOV MOV MOV SCAN; MOV The other circuits assume that input signals are already at TTL levels. Figure 20c uses octal three-state buffers enabled by active-low scan signals to gate eight signals onto Port o. Port 0 is available for memory expansion or peripheral chip interfacing between sensor matrix scans. Eight-to-one multiplexers in Figure 20d select one of eight inputs for each return line as determined by encoded address bits output on three pins of Port I. (Five more output pins are thus freed for more control functions.) Each output can drive at least one standard TTL or up to 10 low-power TTL loads without additional buffering. RR MOV MOV XCH MOV Going back to the original matrix circuit, Figure 21 shows the mediod used to scan the sensor matrix. Two complete bit maps are maintained in the bit-addressable region of the RAM: one for the current state and one for the previous state read for each sensor. If the need arises, the program could then sense input transitions and or debounce contact closures by comparing each bit with its earlier value. INC INC MOV JNB RET The code in Example 3 implements the scanning algorithm for the circuits in Figure 20a. Each column is enabled by setting a single bit in a field of zeroes. The bit maps are positive logic: ones represent contacts that are closed or isolators turned on. 2-63 ;SUBROUTINE TO READ ;CURRENT STATE ;OF 64 SENSORS AND ;SAVE IN RAM 20H-27H ;INITIALIZE RO.#20H ;POINTERS RI,#28H ;FOR BIT MAP ;BASES . ;SET FIRST BIT A,#80H ;IN ACC ;OUTPUT TO SCAN PI,A ;LINES ;SHIFT TO ENABLE A ;NEXT COLUMN ;NEXT R2,A ;REMEMBER CUR;RENT SCAN ;POSITION ;READ RETURN A,PO ;LINES A.@RO ;SWITCH WITH ;PREVIOUS MAP ;BITS @RI,A ;SAVE PREVIOUS ;STATE AS WELL RO ;BUMP POINTERS RI A,R2 ;RELOAD SCAN ;LINE MASK ACC,7;SCAN;LOOP UNTIL ALL ;EIGHT COLUMNS ; READ inter AP-70 + SV J "0" ...J...... ~ ~~ - ~...L.S!z "57" ......I.- ~...L.S7 I I - +-4 PO.l PO.2 1 PO.3 I 1 '-+ I --L- ...... T r- I~ 1+ "15" ' ~SZ 1 "7" r,lllNES PO.O "9" I I RETURN I- - ......~ 8051 "56" "8" "1" ~-1- +8x4K PO.4 I PO.S PO.& "63" -L... ,~~ ~ f0- 8x40K r PO.7 =:.;-Pl.0 Pl.l Pl.2 Pl.3 Pl.4 Pl.S Pl.& Pl.7 SCAN LINES 203830-20 a.) Using Switch Contact/Diode Matrix Figure 20. Sensor Matrix Implementation Methods 2-64 infef AP-70 +SV +8.4K ~ * ~, ~'l" .- C)lA'~ .... "0" r- r=-- Cr~l , , *' ( PO.O -r--- - t-- ~ PO.l PO.2 I I ~A'~"lS" f- ~'*}S7" 1 n.r-I C .,... -- RETURN "LINES ~ I I~I '+1+1 1 1 r- .-. 1 .r- ~¥:rJ"56" T L~ ~ PO.3 I PO.4 I po.s PO.6 IC ~¥¥)"63" 1 t- -C8.40K *~ PO.7 ;. Pl.0 Pl.l Pl.2 Pl.3 Pl.4 Pl.S Pl.6 PH SCAN LINES 203830-21 b.) Using Optically-Coupled Isolators Figure 20. Sensor Matrix Implementation Methods (Continued) 2-65 intJ AP-70 ilIiiiii iit!t!!! ;: '"~ .., . ;: ~ ~ .. .., >'" >- >'" '" '" '" ;: '" ~ .., ~ .. .., >'" '" '" ;: '" >- ~ . ~ Itrnnr ..,C! '" >0 N _ > M _ > .., _ 805 .. C! '" ..N > > 1 I~r-+-+-+-4-4-4-4-~~~-+-+-+-+~----4-~I~+-+-+-4-4-~~---~POO ~+-+-+-4-4-4-4---~~-+-+-+-+~----4-----~+-+-4-4-~~--~po, ~r-+-+-+-4-+-----~~~-+-+-+----+-------~+-+-+-rl-4---~P02 ~+-+-+-4-+-------~~-+-+-+----4---------~+-4-4-~--~P03 PO.4 po.s ~+-I-------------~-+----r_----------~+--_l PO.6 ~r_--------------......----r_-------------~--_l PO.7 ~+-+-+-+---------~~~-+----+-----------o~+-4-4----I L..-r_r_r_----------....+4-----r_------------o...-+-+--_l I I I I I I 11l1_ _~~~.~ E eo .• ----------------------1 Pl.S ~-----------------------------------------------------_l Pl.7 L-..-- 203830-22 c.) Using TTL Three-State Buffers Figure 20. Sensor Matrix Implementation Methods (Continued) AP-70 rrlll!)! DO 01 02 03 04 05 06 07 nrrnn rrrri!it DO 01 02 03 04 05 06 07 74151 C 74151 74151 BAY S C' B A - Y 5 C B A Y S l~ '--------I---I--+--+--------+-+-+--I-------l PO.O '----------+-++-+------1 PO.l '--t-r+rH---t--t--t---+-------i PO.2 4-+-+---Hf----f----l------i PO.3 '-i-t-----+-++-+-------<~ PO.4 I '-+---+--+--+---+------1 PO.5 '----t-t-t--+------J '-------J PO.6 II 11 II 11 Il ' - - - - - - - - - t......- ' - -_ _ _ _ _ _ _......_ 1 1 1 1 ~- ~ .......-+~_+~_+<~--+4~-H~----<~ .........L -......_ ......._ ......._ PO.7 ......._~~-----_<~ Pl.0 Pl.l Pl.2 203830-23 d.} Using TTL Data Selectors Figure 20. Sensor Matrix Implementation Methods (Continued) 2-67 inter AP-70 venting some artificial design problem, software corre· sponding to commonplace logic elements will be discussed. Combinatorial Output Variables. An output variable ,,:,hich is a simple (or not so simple) combinational function of several input variables is computed in the spirit of Design Example 3. All 64 inputs are represented in the bit maps: in fact, the sensor numbers in Figure 20 correspond to the absolute bit addresses in RAM! The code in Example 4 activates an actuator connected to P2.2 when sensors 12, 23, and 34 are closed and sensors 45 and 56 are open. . INITIALIZE MAP BUFFER POINTERS AND SCAN MASK OUTPUT SCAN MASK TO SCAN LINES; STORE SHIFTED MASK Example 4. Simple Combinatorial Output Variabl~s. ;SET P2.2=(12) (23) (34) ( 45) ( 56) MOV C,12 ANL C,23 ANL C,34 ANL C, 45 ANL C, 56 MOV P2.2,C READ RETURN LINES AND UPDATE BIT MAPS Intermediate Variables. The examination of a typical relay-logic ladder diagram will show that many of the rungs control not outputs but rather relays whose contacts figure into the computation of other fjlnctions. In effect, these reiays indicate the state of intermediate variables of a computation. The MCS-51 solution can use any directly addressable bit for the storage of such iptermediate variables. Even when all 128 bits of the RAM array are dedicated (to input bit maps in this example), the accumulator, PSW, and B register provide 18 additional flags for intermediate variables. 203830-24 Figure 21. Flowchart for Reading in Sensor Matrix For example, suppose switches 0 through 3 control a safety interlock system. Closing any of them should deactivate certain outputs. Figure 22 is a ladder diagram for this situation. The interlock function could be recomputed for every output affected, or it may be computed once and save (as implied by the diagram). As - the program proceeds this bit can qualify each output. What happens after the sensors have been scanned depends on the individual application. Rather than in- 2-68 inter AP-70 Latching Relays. A latching relay can be forced into either the ON or OFF state by two corresponding input signals, where it will remain until forced onto the opposite state-analogous to a TTL Set/Reset flip-flop. The relay is used as an intermediate variable for other calculations. In the previous example, the emergency condition could be remembered and remain active until an "emergency cleared" button is pressed. Example 5. Incorporating Override signal into actuator outputs. CALL INPUT_SCAN MOV C,O ORL C,l ORL C,2 ORL C,3 MOV FO,C Any flag or addressable bit may represent a latching relay with a few lines of code (see Example 6). COMPUTE FUNCTION 0 ANL C, FO MOV PLO,C Example 6. Simulating a latching relay. COMPUTE FUNCTION 1 ;I_SET SET FLAG 0 IF C=l LSET: ORL C,FO MOV FO,C ANL C, FO MOV Pl,l,C COMPUTE FUNCTION 2 ;I_RSET RESET FLAG 0 IF C=l LRSET: CPS C ANL C,FO MOV FO,C ANL C, FO MOV Pl,2,C Time Delay Relays. A time delay relay does not respond to an input signal until it has been present (or absent) for some predefined time. For example, a ballast or load resistor may be switched in series with a D.C. motor when it is first turned on, and shunted from the circuit after one second. This sort of time delay may be simulated by an interrupt routine driven by one of the two 8051 timer counters. The procedure followed by the routine depends heavily on the details of the exact function needed: time-outs or time delays with resettable or non-resettable inputs are possible. If the interrupt routine is executed every 10 milliseconds the code in Example 7 will clear an intermediate variable set by the background program after it has been active for two seconds. "0" 1 "1" .--~ I---+-----i "2" "3" Example 7. Code to clear USRFLG after a fixed time delay. JNB DJNZ CLR MOV NXTTST; , .. 203830-25 Figure 22. Ladder Diagram for Output Override Circuitry 2-69 USR_FLG,NXTTST DLAY_COUNT,NXTTST USR_FLG DLAY_COUNT,#200 intJ AP-70 Serial Interface to Remote Processor. When it detects emergency conditions represented by certain input combinations (such as the earlier Emergency Override), the controller could shut down the machine immediately and/or alert the host processor via the serial port. Code bytes indicating the nature of the problem could be transmitted to a central computer. In fact, at 17,000 bytes-per-second, the .entire contents of both bit maps could be sent to the host processor for further analysis in less than a millisecond! If the host decides that conditions warrant, it could alert other remote processors in the system that a problem exists and specify which shut-down sequence each should initiate. For more information on using the serial port, consult the MCS-51 User's ManuaL A programmed controller which simulates each Boolean function with a subroutine would be less efficient by at least an order of magnitude. Extra software is needed for the simulation routines, and each step takes longer to execute for three reasons: several byte-wide logical instructions are executed per user program step (rather than one Boolean operation): most of those instructions take longer to execute with microprocessors performing mUltiple off-chip accesses: and calling and returning from the various subroutines requires overhead for stack operations. In fact, the speed of the Boolean Processor solution is likely to be much faster than the system requires. The CPU might use the time left over to compute feedback' parameters, collect and analyze execution statistics, perfoTm system diagnostics, and so forth. Response Timing One difference between relay and programmed industrial controllers (when each is considered as a "black box") is their respective reaction times to input changes. As reflected by a ladder diagram, relay systems contain a large number of "rungs" operating in paralleL A change in input conditions will begin propagating through the system immediately, possibly affecting the output state within milliseconds. Software, on the other hand, operates sequentially. A change in input states will not be detected until the next time an input scan is performed, and will not affect the outputs until that section of the program is reached. For that reason the raw speed of computing the logical functions is of extreme importance. Here the Boolean processor pays off. Every instruction mentioned in this Note completes in one or two microseconds-the minimum instruction execution time for many other microcontrollers! A ladder diagram containing a hundred rungs, with an average of four contacts per rung can be replaced by approximately five hundred lines of software. A complete pass through the entire matrix scanning routine and all computations would require about a millisecond: less than the time it takes for most relays to change state. . Additional Functions and Uses With the building-block basics mentioned above many more operations may be synthesized by short instruction sequences. Exclusive-OR. There are no common mechanical devices or relays analogous to the Exclusive-OR operation, so this instruction was omitted from the Boolean Processor. However, the Exclusive-OR or ExclusiveNOR operation may be performed in two instructions by conditionally complementing the carry or a Boolean variable based on the state of any other testable bit. ;EXCLUSIVE-;OR FUNCTION IMPOSED ON CARRY ;USING FO IS INPUT VARIABLE. ;XOR_FO: JNB FO,XORCNT ;("JB" 'FOR X-NOR) CPL C ;XORCNT: •••••••• XCH. The contents of the' carry and some other bit may be exchanged (switched) by using the accumulator as temporary storage. Bits can be moved into and out of the accumulator simultaneously using the Rotate- 2-70 inter AP-70 through-carry instructions, though this would alter the accumulator data. ;EXCHANGE CARRY WITH USRFLG XCHBIT: RLC A MOV C,USR_FLG RRC A MOV USR_FLG,C RLC A Extended Bit Addressing. The 8051 can directly address 144 general-purpose bits for all instructions in Figure 3b. Similar operations may be extended to any bit anywhere on the chip with some loss of efficiency. Design Example 2 can be extended quite readily to 16 or more bits by using multi-byte input and output buffers. Many mass data storage peripherals and serial communications protocols include Cyclic Redundancy (CRC) codes to verify data integrity. The function is generally computed serially by hardware using shift registers and Exclusive-OR gates, but it can be done with software. As each bit is received into the carry, appropriate bits in the multi-byte data buffer are conditionally complemented based on the incoming data bit. When finished, the CRC register contents may be checked for zero by ORing the two bytes in the accumulator. 4.0 SUMMARY The logical operations AND, OR, and Exclusive-OR are performed on byte variables using six different addressing modes, one of which lets the source be an immediate mask, and the destination any directly addressable byte. Any bit may thus be set, cleared, or complemented with a three-byte, two-cycle instruction if the mask has all bits but one set or cleared. Byte variables, registers, and indirectly addressed RAM may be moved to a bit addressable register (usually the accumulator) in one instruction. Once transferred, the bits may be tested with a conditional jump, allowing any bit to be polled in 3 microseconds-still much faster than most architectures-or used for logical calculations. (This technique can also simulate additional bit addressing modes with byte operations.) Parity of bytes or bits. The parity of the current accumulator contents is always available in the PSW, from whence it may be moved to the carry and further processed. Error-correcting Hamming codes and similar applications require computing parity on groups of isolated bits. This can be done by conditionally complementing the carry flag based on those bits or by gathering the bits into the accumulator (as shown in the DES example) and then testing the parallel parity flag. Multiple byte shift and CRC codes Though the 8051 serial port can accommodat~ eight- or nine-bit data transmissions, some protocols involve much longer bit streams. The algorithms presented in A truly unique facet of the Intel MCS-51 microcomputer family design is the collection of features optimized for the one-bit operations so often desired in real-world, real-time control applications. Included are 17 special instructions, a Boolean accumulator, implicit and direct addressing modes, program and mass data storage, and many I/O options. These are the world's first singlechip microcomputers able to efficiently manipulate, operate on, and transfer either bytes or individual bits as data. This Application Note has detailed the information needed by a microcomputer system designer to make full use of these capabilities. Five design examples were used to contrast the solutions allowed by the 8051 and those required by previous architectures. Depending on· the individual application, the 8051 solution will be easier to design; more reliable to implement, debug, and verify, use less program memory, and run up to an order of magnitude faster than the same function implemented on previous digital computer architectures. Combining byte- and bit-handling capabilities in a single microcomputer has a strong synergistic effect: the power of the result exceeds the power of byte- and bitprocessors laboring individually. Virtually all user applications will benefit in some way from this duality .. Data intensive applications will use bit addressing for test pin monitoring or program control flags: control applications will use byte manipulation for parallel I/O expansion or arithmetic calculations. It is hoped that these design examples give the reader an appreciation of these unique features and suggest ways to exploit them in his or her own application. 2-71 ISIS-II MCS-51'MACRO ASSEMBLER VI.O MODULE PLACED IN FO AP70 HEX ASSEMBLER INVOKED BY' F1.asm51 ap70 sre LOC OB~ LINE SOURCE l OB~ECT 2 d~te(328) $XREF TITLE(AP-70 APPENDIX) .******************************************************** 3 4 THE FOLLOWING PROGRAM USES THE BOOLEAN INSTRUCTION SET OF THE INTEL E051 MICROCOMPUTER TO PERFORM A ~UMBER OF AUTOMOTIVE DASHBOARD CONTROL FUNCTIONS RELATING TO TURN SIGNAL CONTROL. EMERGENCY BLINKERS. BRAKE LIGHT CONTROL. AND PARKING LIGHT OPERATION. THE ALGORITHMS AND HARDWARE ARE DESCRIBED IN DESJGN EXAMPLE .4 OF INTEL. APpLICATION NOTE AP-70. "USING THE INTEL MCS-51< m. 35'» a. 1_. -·n !Lm -.- ::so cc-. INTERNAL VARIABLE.DEFINITIONS· SUB DIV DATA HI_FREG BIT LO_FREG. BIT 20H SUB DIV 0 SUB_DIV 7 INTERRUPT·RATE SUBDIVIDER HIGH-FREGUENCY OSCILLATOR BIT LOW-FREGUENCY OSCILLATOR BIT' DIM PSW I PARKING LIGHTS ON FLAG BIT &0» ~2:"'O m ......... z Oce OUTPUT PIN DECLARATIONS' (ALL OUTPUTS ARE POSITIVE TRUE LOGIC BULB IS TURNED ON'WHEN OUTPUT PIN IS HIGH. ) BIT BIT BIT BIT BIT BIT -0 "'OCD BRAKE PEDAL DEPRESSED EMERGENCY BLINKER ACTIVATED PARKING LIGHTS ON TURN LEVER DOWN TURN LEVER UP L_FRNT RJRNT L_DASH R_DASH L_REAR R_REAR ::s- "'3 i**"'**************************************.*********** **** BRAKE EMERG PARK L_TURN R_TURN 0» Or:: j===================================================== == $E~ECT 203830-26 » l' ..... o LOC ODJ 0000 020040 0000 OOOB 7:18CFO OOOE CODO 0010 0154 0040 0040 758AOO 0043 758CFO 0046 758961 0049 004C 004E 0050 0052 7520F4 D2A9 D2AF D28C 80FE 0054 D52038 0057 7520F4 I\) ~ 005A 4390EO 005D 43A007 0060 C295 0062 20S428 0065 D295 0067 C297 0069 208421 006C D297 006E C2Al 0070 20B41A 0073 D2Al 0075 C296 0077 20B413 007A D296 007C C2AO 007E 20B40C 0081 D2AO 00B3 C2A2 00B5 20B405 OOBB D2A2 LINE l SOURCE 49 50 51 ORG LJMP OOOOH INIT RESET VECTOR 5~ ORG MOV PUSH AJMP OOOBH THO. 11-16 PSW UPDATE TIMER 0 SERVICE VECTOR HIGH TIMER BYTE ADJUSTED TO CONTROL INT RATE EXECUTE CODE TO SAVE ANY REGISTERS USED BELOW (CONTINUE WITH REST OF ROUTINE) ORG MOV MOV MOV 0040H TLO.1I0 THO.1I-16 TMOD.1I01100001B 53 54 55 56 57 5B 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 7B INIT UPDATE 79~ BO Bl B2 B3 84 85 B6 87 BB B9 90 91 ~ MOV SETB SETB SEHI SJMP SUB_DIV.1I244 ETO EA TRO DJNZ MOV SUB_DIV. TOSERV SUB_DIV.1I244 ORL ORL CLR JB SETB CLR JB SETB CLR JB SETB CLR JB SETB CLR JB SETB CLR JB SETB PI.llll100000B P2.1I00000IIIB L_FRNT TO. FAULT L_FRNT L_DASH TO. FAULT L_DASH L_REAR TO. FAULT L_REAR RJRNT TO. FAULT R_FRNT R DASH TO. FAULT R_DASH R_REAR TO. FAULT R_REAR $ ZERO LOADED INTO LOW-ORDER BYTE AND -16 IN HIGH-ORDER BYTE GIVES 4 MSEC PERIOD B-BIT AUTO RELOAD COUNTER MODE FOR TIMER I. 16-BIT TIMER MODE rOR TIMER 0 SELECTED SUBDIVIDE INTERRUPT RATE BY 244 FOR I HZ USE TIMER 0 OVERFLOWS TO INTERRUPT PROGRAM CONFIGURE IE TO GLOBALLY ENABLE INTERRUPTS 'KEEP INSTRUCTION CYCLE COUNT UNTIL OVERFLOW START BACKGROUND PROGRAM EXECUTION EXECUTE SYSTEM TEST ONLY ONCE PER SECOND GET VALUE FOR NEXT ONE SECOND DELAY AND GO THROUGH ELECTRICAL SYSTEM TEST CODE SET CONTROL OUTPUTS HIGH l> ." I ...... FLOAT DRIVE COLLECTOR TO SHOULD BE PULLED LOW PULL COLLECTOR BACK DOWN REPEAT SEQUENCE FOR L_~DASH. o L REAR. R_FRNT. R__ DASH. AND R _REAR 92 aOSA 200402 OOBD B2A3 93 94 95 96 97 98 99 +1 WITH ALL COLLECTORS GROUNDED. TO SHOULD BE HIGH IF 50. CONTINUE WITH INTERRUPT ROUTINE FAULT~ JB CPL TO. TOSERV S_FAIL ELECTRICAL FAILURE PROCESSING ROUTINE (TOGGLE INDICATOR ONCE PER SECOND) SEJECT 203830-27 _. LOC OB.! 008F 0091 0093 0095 0097 A201 8200 7202 B292 92Dl 0099 009B 009D 009F A293 7291 8207 9297 OOAI 92D5 00A3 7201 00A5 9295 I\J ~ 00A7 00A9 OOAB OOAD OOAF 00B1 00B3 00B5 00B7 OOB? OOBB OOBD OOBF 00C1 00C3 00C5 00C7 A2?0 BO'13 7205 72D1 92Al A294 72'11 8207 ?2AO '1205 7201 ?2?b A2?O BO?4 72D5 72DI 92A2 OOC? DODO OOCD 32- LINE 100 101 102 103 104 105 lOb 107 108 109 110 III 112 113 114 115 lib 117 liB 119 120 121 122 123 124 125 SOURCE TOSERV. 2) 3) 143 144 145 14b 147 148 14'1 150 :51 MOV ANL ORL ANL MOV 4) START WITH 50 PERCENT. MASK DOWN TO 25 PERCENT. BUILD BACK TO b2. 5 PERCENT. GATE WITH PARKING LIGHT SWITCH. AND SAVE IN TEMP. VARIABLE C. L_TURN C.EMERG C.LO_FREQ L_DASH.C SET CARRY IF TURN OR EMERGENCY SELECTED. IF SO. 'GATE IN 1 HZ SIGNAL AND OUTPUT TO DASHBOARD COMPUTE AND OUTPUT LEFT-HAND FRONT TURN SIGNAL FO.C C.DIM L_FRNT. C SAVE FUNCTION SO FAR ADD IN PARKING LIGHT FUNCTION AND OUTPUT TO TURN SIGNAL COMPUTE AND OUTPUJ LEFT-HAND REAR TURN SIGNAL MOV ANL ORL ORL MOV 5) C. SUB_DIV I C. SUB_DIV 0 C.SUB_DIV 2 C.PARK DIM.C t COMPUTE AND OUTPUT LEFT-HAND DASHBOARD INDICATOR MOV ORL MOV 128 142 COMPUTE LOW BULB INTENSITY WHEN PARKING LIGHTS ARE ON MOV ORL ANL MOV 126 127 129 130 131 132 133 134 135 13b 137 138 139 140 141 II CONTINUE WITH INTERRUPT PROCESSING 1> C.BRAKE C./L_TURN C.FO C.DIM L_REAR. C II GATE BRAKE PEDAL SWITCH WITH TURN LEVER INCLUDE TEMP VARIABLE FROM DASH AND PARKING LIGHT FUNCTION AND OUTPUT TO TURN SIGNAL. REPEAT ALL OF ABOVE FOR RIGHT-HAND COUNTERPARTS MOV ORL ANL MOV MOV ORL MOV MOV ANL ORL ORL MOV C. R_TURN C.EMERG C. LO_FREQ R_DASH.C FO.C C.DIM R FRNT. C C:-ORAKE C./R_TURN C.FO C.DIM R_REAR. C SET CARRY IF TURN OR EMERGENCY SELECTED IF SO. GATE IN I HZ SIGNAL AND OUTPUT TO DASHBOARD. SAVE FUNCTION SO FAR. ADD IN PARKING LIGHT FUNCTION AND OUTPUT TO TURN SIGNAL. GATE BRAKE PEDAL SWITCH WITH TURN LEVER INCLUDE TEMP VARIADLE FROM DASH AND PARKING LIGHT FUNCTION AND OUTPUT TO TURN SIGNAL. RESTORE STATUS REGISTER AND RETURN POP RETI PSW RESTORE PSW AND RETURN FROM INTERRUPT ROUTINE END 203830-28 » "U I "'0 " _. t XREF SYMBOL TABLE LISTING NAME I\) .!.J 01 TYPE BRAKE N BSEG DIM N BSEG EA N BSEG EMERG N BSEG ETO N BSEG FO N BSEG FAULT L CSEG HI_FRECl N BSEG INlT L CSEG N BSEG L_DASH L_FRNT N BSEG L_REAR. N IlSEG L_TURN N IlSEG LO_FRECl "N IlSEC PI N DSEG P2 N DSEG PARK N IlSEG PSW N DSEG R_DASH N IlSEG N BSEG RJRNT R_REAR N BSEG R_TURN N IlSEG SJAIL. N IlSEG SUB_DIV N DSEG TO N IlSEG TOSERV L CSEG THO N DSEG TLO N DSEG TMOD N DSEG TRO N BSEG UPDATE L CSEG VALUE AND REFERENCES 0090H . OODIH OOAFH 0091H 00A9H 00D5H OOBDH OOOOH 0040H 0097H 0095H OOAIH 0093H 0007H 0090H OOAOH 0092H OODOH OOAOH 0096H OOA2H 0094H 00A3H ASSEMBLY COMPLETE. 204* 125 140 4511 lOB 120 12B 13B 143 611 2111 113 134 63 119 127 137 142 75 7B BI B4 B7 90 9711 42. 50 5BII 3211 77 79 115 30 .. 74 76 121 34 .. 80 82 129 23. 112 126 4311 114 135 20 21 22 23 24 30 31 32 72 33 34 35 37 73 22.. 107 45 54 14B 3311 B6 BB 136 3U B3 B5 139 3511 B9 91 144 2411 133 141 3711 97 l> II 0020H 41 .. 42 43 62 69 70 104 105 106 00B4H OOBFH OOBCH OOBAH 00B9H OOBCH 00548 75 69 53 5B 60 65 55 7B Bl B4 B7 90 96 96 10411 59 6911 NO ERRORS FOUND 203830-29 "'CI I ..... 0 APPLICATION NOTE AP-223 October 1984 ~INTEL CORPORATION, 1984 2-76 ORDER NUMBER: 270032-001 Ap·223 1.0 INTRODUCTION This is the third application note that Intel has produced on CRT terminal controllers. The first Ap Note (ref. I), written in 1977, used the 8080 as the CPU and required 41 packages including 11 LSI devices. In 1979, another application note (ref. 2) using the 8085 as the controller was produced and the chip count decreased to 20 with 11 LSI devices. br-------, --~-------t Advancing technology has integrated a complete system onto a single device that contains a CPU, program memory, data memory, serial communication, interrupt controller, and lIO. These "computer-on-a-chip" devices are known as microcontrollers. Intel's MCS®-51 microcontroller was chosen for this application because of its highly integrated functions. This CRT terminal design uses 12 packages with only 4 LSI devices. This application note has been divide" into five general sections: 1) CRT Terminal Basics 2) 8051 Description 3) 8276 Description 4) Design Background 5) System Description 2.0 CRT TERMINAL BASICS A terminal provides a means for humans to communicate with a computer. Terminals may be as simple as a LED display and a couple of push buttons, or it may be an elaborate graphics system that contains a full function keyboard with user programmable keys, color CRT and several processors controlling its functions. This application note describes a basic low cost terminal containing a black and white CRT display, full function keyboard and a serial interface. 2.1 CRT Description A raster scan CRT displays its images by generating a series of lines (raster) across the face of the tube. The electron beam usually starts at the top left hand comer moves left to right, back to the left of the screen, moves down one row and continues on to the right. This is repeated until the lower right hand of the screen is reached. Then the beam returns to the top left hand corner and refreshes the screen. The beam forms a zigzag pattern as shown in Figure 2.1.0. Two independent operating circuits control this movement across the screen. The horizontal oscillator controls the left to right motion of the beam while the vertical controls the top to bottom movement. The vertical oscillator also tells the beam when to return to the upper left hand comer or "home" position. . - Figure 2.1.0 - RETRACE LINES DISPLAYED LINES Raster Scan As the electron beam moves across the screen under the control of the horizontal oscillator, a third circuit controls the current entering the electron gun. By varying the current, the image may be made as bright or as dim as the user desires. This control is also used to tum the beam off or "blank the screen". When the beam reaches the right hand side of the screen, the beam is blanked so it does not appear on the screen as it returns to the left side. This "retrace" of the beam is at a much faster rate than it traveled across the screen to generate the image. The time it takes to scan the whole screen and return to the home position is referred to as a, "frame". In the United States, commercial television broadcast uses a horizonal sweep frequency of 15,750Hz which calculates out to 63.5 microseconds per line. The frame time is equal to 16.67 milliseconds or 60Hz vertical sweep frequency. Although this is the commercial standard, many CRT displays operate from 18KHz to 30KHz horizonatal frequency. As the horizontal frequency increases, the number of lines per frame increases. This increase in lines or resolution is needed for graphic displays and on special text editors that display many more lines of text than the standard 24 or 25 character lines. Since the United States operates on a 60Hz A.C. power line frequency, most CRT monitors use 60Hz as the vertical frequency. The use of 60Hz as the vertical frequency allows the magnetic and electrical variations that can modulate the electron beam to be synchronized with the display, thus they go unnoticed. If a frequency other than 60Hz is used, special shielding and power supply regu- 2-77 AP·223 lating is usually required. Very few CRTs operate on a vertical frequency other than 60Hz due to the increase in the overall system,cost. The following equation can be used to figure 'the number of lines per frame: L=(H*Z)+V The CRT controller must generate the pulses that define the horizontal and vertical timings. On most raster scan CRTs the horizontal frequency may vary as much as 500Hz without any noticeable effect on the quality of the display. This variation can change the number of horizontal lines from 256 to 270 per frame. The CRT controller must also shift out the information to be displayed serially to the circuit that controls the electron· beam's intensitY as it scans across the screen. The circuits that control the timing associated with the shifting of the information are known as the dot clock and the character clock. The character clock frequency is equal to the dot clock frequency divided by the number of dots it takes to form a character in the horizontal axis. The dot clock frequency is calculated by the following equation: Dot Clcok (Hz) = (N + R)*D*L *F where N is the number of displayed characters per row, R is the number of character times for the retrace, D is the number ·of dots per character in the horizontal axis, L is the number of horizontal lines per frame, F is the frame rate in Hz.' In this design N = 80, R = 20, D = 7, L = 270, and F = 60Hz. Plugging in the numbers results in a dot clock frequency of 11.34MHz. The retrace number may vary on each design because it is used to set the left and right hand margins on the CRT. The number of dots per character is chosen by the designer to meet the system needs. In this design, a 5 x 7 dot matrix and 2 blank dots between each character (see Figure 2.1.1) makes D equal to 5+2=7. where H is the number of horizontal lines per character, Z is the number of character lines per frame, V ,is the number of horizontal line times during the vertical retrace In this design H is equal to the 7 horizontal dots per character plus 3 blank dots between each row which adds up to 10. Also 25 lines of characters are displayed, so Z = 25. The vertical retrace time is variable to set the top and bottom margins on the CRT and in this design is equal . to 20. Plugging in the numbers gives L=270 lines per frame. 2.2 Keyboard A keyboard is the common way a human enters commands and data to a computer. A keyboard consists of a matrix of switches that are scanned every couple of milliseconds by a keyboard controller to determine if one of the keys has been pressed. Since the keyboard is made up of mechanical switches that tend to bounce or "make and break" contact everytime they are pressed, debouncing of the switches must also be a function of the keyboard controller. There are dedicated keyboard controllers available that do everything from scanning the keyboard, deb~uncing the keys, decoding the ASCII code for that key closure to flagging the CPU that a valid key has been depressed. The keyboard controller may present the information to the CPU in parallel form or in a serial data stream. This Application Note integrates the function of the keyboard controller into the 8051 which.is also the terminal controller. Provisions have been made to interface the 8051 to a keyboard that uses a dedicated keyboard controller. The 8051 can accept data from the keyboard controller in either parallel or serial format. 2.3 Serial Communications Communication between a host computer and the CRT terminal can be in either parallel or serial data format. Parallel data transmission is needed in high end graphic terminals where great amounts of information must be transferred. Figure 2.1.1 5 x 7 Dot Matrix One can rarely type faster than 120 words per minute, which corresponds to 12 characters per second or 1 character per 83 milliseconds. The utilization of a parallel port cannot justify the cost associated with the drivers and the amount of wire needed to perform this transmission. Full duplex serial data transmission requires 3 wires and. two AP-223 IICC r---------- -------------, I I I ~ I I I I I I I I I I I I I I I I I I I I I I I I I I Figure 3.0.0 ________ Vee P1.1 PO.O/ADO PO.I/ADI PO.21AD2 PO.31AD3 PO.4/AD4 PO.S/ADS Pl.3 Pl.4 Pl.5 Pl.6 Pl.7 RST P3.0/RXD P3.11TXD P3.21INTO P3.311NTI P3.41TO P3.51TI I ~_,/l_"="_' Pl.0 P1.2 P3.6JWR P3.7/Ro XTAL2 XTALI VSS PO.61AD6 PO.7/AD7 EAtvPP ALElPRDG PSEN P2.7/A15 P2.61AI4 P2.5/A13 P2.4/A12 P2.31All P2.21AI0 P2.1/A9 P2.0/A8 JI 8051 Block Diagram 3.1 drivers to implement the communication channel between the host computer and the terminal. The data rate can be as high as 19200 BAUD in the asynchronous serial format. BAUD rate is the number of bits per second received or transmitted. In the asynchronous serial format, 10 bits of information is required to transmit one character. One character per 500 microseconds or 1,920 characters per second would then be trasmitted using 19.2 KBAUD. CPU Efficient use of program memory results from an instruction set consisting of 49 single-byte, 45 two-byte and 17 three-byte instructions. Most arithmetic, logical and branching operations can be performed using an instruction that appends either a short address or a long address. For example, branches may use either an offset that is relative to the program counter which takes two bytes or a direct 16-bit address which takes three bytes to perform. As a result, 64 instructions operate in one machine cycle, 45 in two machine cycles, and the multiply and divide instruction execute in 4 machine cycles. This application note uses the 8051 serial port configured for full duplex asynchronous serial data transmission. The software for the 8051 has been written to support variable BAUD rates from ISO BAUD up to 9.6 KBAUD. 3.0 8051 DESCRIPTION The 8051 is a single chip high-performance microcontroller. A block diagram is shown in figure 3.0.0. The 8051 combines CPU; Boolean processor; 4K x 8 ROM: 128 x 8 RAM; 32 110 lines; two 16-bit timer/ event. counters; a five-source, two-priority-level, nested interrupt structure; serial I/O port for either mUltiprocessor communications, I/O· expansion, or full duplex UART; and on-chip oscillator and clock circuits. The 8051 has five addressing modes for source operands: Register, Direct, Register-Indirect, Immediate, and Based-Register-plus Index-Register-Indirect Addressing. The Boolean Processor can be thought of as a separate one-bit CPU. It has its own accumulator (the carry bit), instruction set for data moves, logic, and control transfer, and its own bit addressable RAM and 110. The bitmanipulating instructions provide optimum code and speed efficiency for handling on chip peripherals. The 2-79 AP-223 Boolean processor also provides a straight forward means of converting logic equations directly into software.' Complex combinational logic functions can be resolved without extensive data movement, byte masking, and test-andbranch trees. and RXD pins and to generate control signals used for writing and reading external peripherals. 3.4 Interrupt System External events and the real-time-driven on-chip peripherals require service by the CPU asynchronous to the execution of any particular section of code. A five-source, two-level, nested interrupt system ties the real time events to the normal program execution. 3.2 On-Chip Ram The CPU manipulates operands in four memory spaces. These are the 64K-byte Program Memory, 64K-byte External Data Memory, I 28-byte Internal Data Memory, and 128-byte Special Function Registers (SFRs). Four Register Banks (each with 8 registers), 128 addressable bits, and the Stack reside in the internal Data RAM. The Stack size is limited only by the available Internal Data RAM and its location is determined by the 8-bit Stack Pointer. All registers except for the Program Counter and the four 8-Register Banks reside in the SFR address space. These memory mapped registers include arithmetic registers, pointers, I/O ports, and registers for the interrupt system, timers, and serial channel. The 8051 has two external interrupt sources, one interrupt from each of the two timer/counters, and an interrupt from the serial port. Each interrupt vectors the program execution to its own unique memory location for servicing the interrupt. In addition, each of the fi~e sources can be individually enabled or disabled as well as assigned to one of the two interrupt priority levels available on the 8051. Up to two additional external interrupts can be created by configuring a timer/counter to the event counter mode. In this mode the timer/counter increments on command by either the TO or Tl pin.' An interrupt is generated when the timer/counter overflows. Thus if the timer/counter is loaded with the maximum count, the next high-to-Iow transition of the event counter input will cause an intenupt to be generated. Registers in the four 8-Register Banks can be addressed by Register, Direct, or Register-Indirect Addressing modes. The 128 bytes of internal Data Memory can be addressed by Direct or Register-Indirect modes while the SFRs are only addressed directly. 3.3 1/0 Ports 3.5 Serial Port The 8051 has instructions that can treat the 32 I/O lines as 32 individually addressable bits or as 4 parallel 8-bit ports addressable as Ports 0, 1,2, and 3. Resetting the 8051 writes a logical 1 to each pin on port 0 which places the output drivers into a high-impedance mode. Writing a logical 0 to a pin forces the pin to ground. and sinks current. Re-writing the pin high will place the pin in either an open drain output or high-impedance input mode. Ports 1, 2, and 3 are known as quasi-bidirectional I/O pins. Resetting the device writes a logical one to each pin. Writing a logical 0 to the pin will force the pin to ground and sink current. Re-writing the pin high will place the pin in an output mode with a weak depletion pullup FET or in the input mode. The weak pullup FET is easily overcome by a TTL output .. Ports 0 and 2 can also be used for off-chip peripheral expansion. Port 0 provides a multiplexed low-order address and data bus while Port 2 contains the high-order address when using external Program Memory or more than 256 byte external Data Memory. Port 3 pins can also be used to provide external interrupt request inputs, event cpunier inputs, the serial port TXD The 8051' s serial port is useful for linking peripheral devices as well as multiple 8051 s through standard asynchronous protocols with full duplex operation. The serial port also has a synchronous. mode for expansion of I/O lines using shift registers. This hardware serial port saves ROM code and permits a much higher transmission rate than could be achieved through software. The processor merely needs to read or write the serial buffer in response to an interrupt. The receiver is double buffered to eliminate the possibility of overrun if the processor failed to read the buffer before the beginning of the next frame. The full duplex asynchronous serial port provides the means of communication with standard UART devices such as CRT terminals.and printers. The reader should refer to the microcontroller handbook for a complete discussion of the 8051 and its various modes of operation. 4.0 8276 DESCRIPTION The 8276's block diagram and pin configuration are shown in Figure 4.0.0. The following sections describe the general capabilities of the 8276. 2-80 AP-223 LC3 LC2 LC1 LCO BDRY DATA BUS BUFFER US UNE COUNTER ROW COUNTER MRTC VRTC MLGT RVV LTEN VSP RASTER TIMING AND VIDEO CONTROL Figure 4.0.0 4.1 HRTC VRTC ltD WR NC DBa DB1 DB2 DB3 DB4 DBs DBs DB7 GND VCC NL NC LTEN RVV VSP GPA1 GPAo HLGT INT CCLK CC6 CCs CC4 CC3 CC2 CC1 CCo C! C/P 8276 Block Diagram CRT Display Refreshing is used by the 8051 system controller to reinitialize its load buffer pointers for the next display refresh cycle. The 8276, having been programmed by the system designer for a specific screen format, generates a series of Buffer Ready signals. A row of characters is then transferred by the system controller from the display memory to the 8276's row buffers. The row buffers are filled by deselecting the 8276 CS and asserting the BS and WR signals. The 8276 presents the character codes to an external character generator ROM by using outputs CCO-CC6. The parallel data from the outputs of the character generator is converted to serial information that is clocked by external dot timing logic into the video input of the CRT. Proper CRT refreshing requires that certain 8276 parameters be programmed at system initialization time. The 8276 has two types of internal registers; the write only Command (CREG) and Parameter (PREG) Registers, and the read only Status Register (SREG). The 8276 expects to receive a command followed by 0 to 4 parameter bytes depending on the command. A summary of the 8276's instruction set is shown in Figure 4.1:1. To access the registers, CS must be asserted along with WR or RD. The status of the C/P pin determines whether the command or parameter registers are selected. The character rows are displayed on the CRT one line at a time. Line count outputs LCO-LC3 select the current line information from the character generator ROM. The display process is illustrated in Figure 4.1.0. This process is repeated for each display character row. At the beginning of the last display row the 8276 generates an interrupt request by raising its INT output line. The interrupt request The 8276 allows the designer flexibility in the display format. The display may be from I to 80 characters per row, I to 64 rows per screen, and 1 to 16 horizontal lines per character row. In addition, four curser formats are available; blinking, non-blinking, underline, and reverse video. The curser position is programmable to anywhere on the screen via the Load Curser command. 2-81 AP-223 1st Character 2nd Character 3,d Character 4th Character 5th Character 6th Character 7th Character 5th Character 6th Character 7th Character First Line of a Character Row 1st Character 2nd Character 3,d Character 4th Character oo ••• ooo.ooo.oo ••••• oooooooob •••• oooo ••• ooo.ooo.o 0.000.00 •• 00.00.0000000000000.000.00.000.00.000.0 Second Line of a Character Row 1st Character 2nd Character 3,d Character 5th Character 6th Character 7th Character 4th 5th Charlcter Character 6th Character Character 4th Character Third Line of a Character Row • •• 1st 2nd Character Character 3rd Character 7th Seventh Line 01 a Character Row Figure 4.1.0 8276 Row Display 4.2 CRT Timing The 8276 provides two timing outputs for controlling the CRT. The Horizontal Retrace Timing and Control (HRTC) and Vertic·al Retrace Timing and Control (VRTC) signals are used for synchronizing the CRT horizontal and vertical oscillators. A third output, VSP (Video Suppress), provides a signal to the dot timing logic to blank the video signal during the horizontal and vertical retraces. LTEN (Light Enable) is used to provide the ability to force the video output high regardless of the state of the VSP signal. This feature is used to place the cursor on the screen and to control attribute functions. RVV (Reverse Video) output, if enabled, will cause the system to invert its video output. The fifth timing signal output, HLGT (highlight) allows the flexibility to increase the CRT beam intensity to a greater than normal level. 2-82 AP-223 COMMAND NO. OF PARAMETER BYTES NOTES RESET 4 Display format parameters required START DISPLAY 0 DMA operation parameters included in command STOP DISPLAY 0 - RED LIGHT PEN 2 - LOAD CURSOR 2 ENABLE INTERRUPT 0 - DISABLE INTERRUPT 0 - PRESET COUNTERS 0 Figure 4.1.1 Cursor X, Y position parameters required 4.3.4 Clears all internal counters 8276 Instruction Set Special Codes The 8276 recognizes four special codes that may be used to reduce memory, software, or system controller overhead. These characters are placed within the display memory by the system controller. The 8276 performs certain tasks when these codes are received in its row buffer memory. 1) End of Row Code - Activates VSP. VSP remains active until the end of the line is reached. While VSP is active the screen is blanked. 2) End Of Row-Stop Buffer Loading Code - Causes the Buffer Ready control logic to stop requesting buffer " transfers for the rest of the row. It affects the display the same as End of Row Code. 3) End Of Screen Code - Activates VSP. VSP remains active until the end of the frame is reached. Programmable Buffer Loading Control The 8276 can be programmed to request 1, 2, 4, or 8 characters per Buffer load. The interval between loads is also programmable. This allows the designer the flexibility to tailor the buffer transfer overhead to fit the system needs. Each scan line "requires 63.5 microseconds. A character line consists of 10 scan lines and takes 635 microseconds to form. The 8276 row buffer must be filled within the 635 microseconds or an under run condition will occur within the 8276 causing the screen to be blanked until the next vertical retrace. This blanking will be seen as a flicker in the display. 5.0 4.3 Special Functions 4.3.1 4) End Of Screen-Stop Buffer Loading Code - Causes the Buffer Ready control logic to stop requesting buffer transfers until the end of the frame is reached. It affects the display the same way as the End of Screen code. DESIGN BACKGROUND A fully functional, microcontroller-based CRT terminal was designed and constructed using the 8051 and the 8276. The terminal has many of the functions that are found in commercially available low cost terminals. Sophisticated "features such as programmable keys can be added easily with modest amounts of software. The 8051 's functions in this application note include: up to 9.6K BAUD full duplex serial transmission; decoding special messages sent from the host computer; scanning, debouncing, and decoding a full function keyboard; writing to the 8276 row buffer from the display RAM without the need for a DMA controller; and scrolling the display. The 8276 CRT controller's functions include: presenting the data to the character generator; providing the timing signals needed for horizontal and vertical retrace; and providing blanking and video information. 5.1 Design Philosophy Since the device count relates to costs, size, and reliability of a system, arriving at a minimum device count without degrading the performance was a driving force for this application note. LSI devices were used where possible to maintain a low chip count and to make the design cycle as short as possible. PUM-51 was chosen to generate the majority of the "software for this application because it models the human thought process more closely than assembly language. Consequently it is easier and faster to write programs using PLlM-51 and the code is more likely to be correct because less chance exists to introduce errors. 2-83 AP-223 PUM-51 programs are easier to read and follow than assembly language programs, and thus are easier to modify and customize to the end user's application. PUM-51 also offers lower development and maintenance costs than assembly language programming. PUM-51 does have a few drawbacks. It is not as efficient in code generation relative to assembly language and thus may also run slower. This application note uses'the 8051's interrupts to control the servicing of the various peripherals. The speed of the main program is less critical if interrupts are used. In the last two application notes on terminal controllers, a criterion of the system was the time required for receiving an incoming serial byte, decoding it, performing the function requested, scanning the keyboard, debouncing the keys, and transmitting the decoded ASCII code must be less than the vertical refresh time. Using the 8051 and its interrupts makes this time constraint irrelevant. 5.2 System Target ,Specifications The design specifications for the CRT terminal design is as follows: Characters Transmitted • • • • Display Memory • 2K x 8 static RAM Data Rate • Variable rate from 150 to 9600 BAUD CRT Monitor • Ball Bros TV-12, 12MHZ Black and White Keyboard • Any standard undecoded keyboard (2 key lock-out) • Any standard decoded keyboard with output enable pin • Any standard decoded serial keyboard up to 150 BAUD Scrolling Capability Compatible With Wordstar Display Format 6.0 • 80 characters/display row • 25 display lines 5 x 7 character contained within a 7 x 10 frame First and 'seventh columns blanked Ninth line curser position Programmable delay blinking underline curser The "brains" of the CRT terminal is the 8051 microcontroller. The 8276 is the CRT controller in the system, and a 2716 EPROM is used as the character generator. To handle the high speed portion of the CRT, the 8276 is surrounded by a handful of TTL devices. A 2K x 8 static RAM was used as the display memory. Control Characters Recognized • • • • Backspace Linefeed Carriage Return Form Feed I Following the system reset, the 8276 is initialized for curser type, number of characters per line, number of lines, and character size. The display RAM is initialized to all "spaces" (ASCII 20H). The 8051 then writes the "start display" command to the 8276. The localliine input is sampled to determine the terminal mode. If the terminal is on-line, the BAUD rate switches are read and the serial ' port is set up for full duplex UART mode. The processor then is put into a loop waiting to service the serial port fifo or the 8276. Escape Sequences 'Recognized • • • • • • .• • • ESC ESC ESC ESC ESC ESC ESC ESC ESC SYSTEM DESCRIPTION A block diagram of the CRT terminal is shown in figure 6.0.0. The diagram shows only the essential system features. A detailed schematic of the CRT terminal is contained in the Appendix 7. I. Character Format • • • • 96 ASCII Alphanumeric Characters ASCII Control Character Set ASCII Escape Sequence Set Auto Repeat A, Curser up B, Curser down C, Curser right D, Curser left E, Clear screen F, Move addressable curser H, Home curser J, Erase from curser to the end the screen K, Erase the current line The serial port is programmed to have the highest priority interrupt. If the serial port generates an interrupt, the processor reads the buffer, puts the character in a generated fifo that resides in the 8051's internal RAM, increments the fifo pointer, sets the serial interrupt flag and returns. Characters Displayed • 96 ASCII Alphanumeric Characters 2-84 AP-223 SERIAL COMMUNICATIONS CHANNEL Figure 6.0.0 CRT Terminal Controller Block Diagram The main program determines if it is a displayable character, a Control word or an ESC sequence and either puts the character in the display buffer or executes the appropriate command sent from the host computer. If the 8276 needs servicing, the 8051 fills the row buffer for the CRT display's next line. If the 8276 generates a vertical retrace interrupt, the buffer pointers are reloaded with the display memory location that corresponds to the first character of the first display line on the CRT. The vertical retrace also signals the processor to read the keyboard for a key closure. . 6.1 Three general cases can be explored; reading and writing the display RAM, writing to the 8276 row buffers, and reading and writing the 8276's control registers. As mentioned previously the 8051 fills the 8276 row buffer without the need of a DMA controller. This is accomplished by using a Quad 2-input mUltiplexor (Figure 6.1.0) as the transfer logic shown in the block diagram. The address line, P2.3, is used to select either of the two inputs. When the address line is low the RD and WR lines perform their normal functions, that is read and write the Hardware Description 8051 P2.3~ The following section describes the unique characteristics of this design. 6.1.1 8051 WR 1A 8051 RD 1B - Peripheral Address Map 2A +5V The display RAM, 8276 registers, and the 8276 row buffers are memory mapped into the external data RAM address area. The addresses are as follows: SEL - Y1 1--8276 WR Y2 1--8276 BS >---- 2B - 3A Y3 1--8276 RD 3B Read and Write External Display RAM Write to 8276 row buffers from Display RAM Write to 8276 Command Register (CREG) Write to 8276 Parameter Register (PREG) Read from 8276 Status Register (SREG) - - Address 1000H to 17CFH Address 1800H to IFCFH P2.4 Address OOOIH If>- DISPLAY RAM CS Address OOOOH Figure 6.1.0 Simplified Version Of The Transfer Logic Address 0001H 2-85 AP-223 6.1.2.1 8276 or the external display RAM depending on the states of their re~ctive chip selects. If the address line is high, the 8051 RD line is transfonned into BS and WR signals for the 8276. While holding the address line high, the 8051 executes an external data move (MOVX) from the display RAM to the accumulator which causes the display RAM to output the addressed byte pnto the data bus. Since the multiplexor turns the same 8051 RD pulses into BS and WR pulses to the 8276, the data bus is thus read into the 8276 as a Buffer transfer. This scheme allows 80 characters to be transferred from the display RAM into the 8276 within the required character line time of 635 microseconds. The 8051 easily meets this requirement by accomplishing the task within 350 microseconds. Undecoded Keyboard Incorporating an undecoded keyboard controller into the other functions of the 8051 shows the flexibility and over all CPU power that is available. The keyboard in this case is a full function, non-buffered 8 x 8 matrix of switches for a total of 64 possible keys. The 8 send lines are connected to a" 3-to-8 open-collector decoder as shown in Figure 6.1.1. Three high order address lines from the 8051 are the decoder inputs. The enabling of the decoder is accomplished through the use of the PSEN signal from the 8051 which makes the architecture of the separate address space for the program memory and the external data RAM work for us to eliminate the need to decode addresses externally. The move code (MOVC) instruction allows each scan line of the keyboard to be read with one instruction. 6.1.2 Scanning The Keyboard Throughout this project, provision have been made to make the overall system flexible. The software has been written for various keyboards and the user simply needs to link different program modules together to suit their needs. The keyboard is read by bringing one of the eight scan lines low sequentially while reading the return lines which are pulled high by an external resistor. If a switch is 5V ,- 10kO PO.7 8051 DATA BUS PO.O 1N4305~ , ~ , , ~ ~, ~ 74156 2YO '< '< '< '< '< '< '< '< P2.1 - B 2Y1 '< P2.2 1C 2Y2 '< '< '< '< '< '< '< '< 2C 2Y3 '< '< '< '< '< '< '< '< 1G 1YO '< '< '< '< '< '< '< '< 2G 1Y1 '< '< '< '< '< '< '< '< 1Y2 '< '< '< '< '< '< '< '< 1Y3 '< '< '< '< '< '< '< '< P2.0 - A FROM 8051 , L L '< '< '< '< '< '< '< SWITCH MATRIX Figure 6.1.1 Keyboard 2-86 AP-223 COMMAND NO. OF PARAMETER BYTES NOTES RESET 4 Display format parameters required START DISPLAY 0 DMA operation parameters included in command STOP DISPLAY 0 - RED LIGHT PEN 2 - LOAD CURSOR 2 ENABLE INTERRUPT 0 - DISABLE INTERRUPT 0 - PRESET COUNTERS 0 4.3.1 4.3.4 Clears all internal counters 8276 Instruction Set Special Functions Special Codes The 8276 recognizes four special codes that may be used to reduce memory, software, or system controller overhead. These characters are placed within the display memory by the system controller. The 8276 performs certain tasks when these codes are received in its row buffer memory. 1) End of Row Code - Activates VSP. VSP remains active until the end of the line is reached. While VSP is active the screen is blanked. 2) End Of Row-Stop Buffer Loading Code - Causes the Buffer Ready control logic to stop requesting buffer transfers for the rest of the row. It affects the display the same as End of Row Code. 3) End Of Screen Code - Activates VSP. VSP remains active until the end of the frame is reached. Programmable Buffer Loading Control The 8276 can be programmed to request I, 2, 4, or 8 characters per Buffer load. The interval between loads is also programmable. This allows the designer the flexibility to tailor the buffer transfer overhead to fit the system needs. Each scan line'requires 63.5 microseconds. A character line consists of 10 scan lines and takes 635 microseconds to form. The 8276 row buffer must be filled within the 635 microseconds or an under run condition will occur within the 8276 causing the screen to be blanked until the next vertical retrace. This blanking will be seen as a flicker in the display. 5.0 Figure 4.1.1 4.3 Cursor X, Y position parameters required 4) End Of Screen-Stop Buffer Loading Code - Causes the Buffer Ready control logic to stop requesting buffer transfers until the end of the frame is reached. It affects the display the same way as the End of Screen code. DESIGN BACKGROUND A fully functional, microcontroller-based CRT terminal was designed and constructed using the 8051 and the 8276. The terminal has many of the functions that are found in commercially available low cost terminals. Sophisticated features such as programmable keys can be added easily with modest amounts of software. The 8051's functions in this application note include: up to 9.6K BAUD full duplex serial transmission; decoding special messages sent from the host computer; scanning, debouncing, and decoding a full function keyboard; writing to the 8276 row buffer from the display RAM without the need for a DMA controller; and scrolling the display. The 8276 CRT controller's functions include: presenting the data to the character generator; providing the timing signals needed for horizontal and vertical retrace; and providing blanking and video information. 5.1 DeSign Philosophy Since the device count relates to costs, size, and reliability of a system, arriving at a minimum device count without degrading the performance was a driving force for this application note. LSI devices were used where possible to maintain a low chip count and to make the design cycle as short as possible. PUM-51 was chosen to generate the majority of the 'software for this application because it models the human thought process more closely than assembly language. Consequently it is easier and faster to write programs using PUM-51 and the code is more likely to be correct because less chance exists to introduce errors. 2-83 AP-223 Characters Transmitted PUM-51 programs are easier to read and follow than assembly language programs, and thus are easier to modify and customize to the end User's application. PUM-5l also offers lower development and maintenance costs than assembly language programming. • • • • PUM-51 does have a few drawbacks. It is not as efficient in code generation relative to assembly language and thus may also run slower. • 2K x 8 static RAM This application note uses' the 8051's interrupts to control the servicing of the various peripherals. The speed of the main program is less critical if interrupts are used. In the last two application notes on terminal controllers, a criterion of the system was the time required for receiving an incoming serial byte, decoding it, performing the function requested, scanning the keyboard, debouncing the keys, and transmitting the decoded ASCII code must be less than the vertical refresh time. Using the 8051 and its interrupts makes this time constraint irrelevant. 5.2 System Target Specifications The design specifications for the CRT terminal design is as follows: Display Format • 80 characters/display row • 25 display lines Character Format • • • • 5 x 7 character contained within a 7 x 10 frame First and 'seventh columns blanked Ninth line curser position Programmable delay blinking underline curser Display Memory Data Rate • Variable rate from 150 to 9600 BAUD CRT Monitor • Ball Bros TV-12, 12MHZ Black and White Keyboard • Any standard undecoded keyboard (2 key lock-out) • Any siandard decoded keyboard with output enable pin • Any standard decoded serial keyboard up to 150 BAUD Scrolling Capability Compatible With Wordstar 6.0 The "brains" of the CRT terminal is the 8051 microcontroller. The 8276 is the CRT controller in the system, and a 2716 EPROM is used as the character generator. To handle the high speed portion of the CRT, the 8276 is surrounded by a handful of TTL devices. A 2K x 8 static RAM was used as the display memory. Backspace Linefeed Carriage Return Form Feed I Following the system reset, the 8276 is initialized for curser type, number of characters per line, number of lines, and character size. The display RAM is initialized to all "spaces" (ASCII 20H). The 8051 then writes the "start display" command to the 8276. The locallline input is sampled to determine the terminal mode. If the terminal is on-line, the BAUD rate switches are read and the serial . port is set up for full duplex UART mode. The processor then is put into a loop waiting to service the serial port fifo or the 8276. Escape Sequences 'Recognized • • • • • • '. • • ESC ESC ESC ESC ESC ESC ESC ESC ESC SYSTEM DESCRIPTION A block diagram of the CRT terminal is shown in figure 6.0.0. The diagram shows only the essential system features. A detailed schematic of the CRT terminal is contained in the Appendix 7.1. Control Characters Recognized • • • • 96 ASCII Alphanumeric Characters ASCII Control Character Set ASCII Escape Sequence Set Auto Repeat A, Curser up B, Curser down C, Curser right D, Curser left E, Clear screen F, Move addressable curser H, Home curser, J, Erase from curser to the end the screen K, Erase the current line The serial port is programmed to have the highest priority interrupt. If the serial port generates an interrupt, the processor reads the buffer, puts the character in a generated fifo that resides in the 8051's internal RAM, increments the fifo pointer, sets the serial interrupt flag and returns. Characters Displayed • 96 ASCII Alphanumeric Characters 2-84 Ap·223 SERIAL COMMUNICATIONS CHANNEL Figure 6.0.0 CRT Terminal Controller Block Diagram The main program determines if it is a displayable character, a Control word or an ESC sequence and either puts the character in the display buffer or executes the appropriate command sent from the host computer. Three general cases can be explored; reading and writing the display RAM, writing to the 8276 row buffers, and reading and writing the 8276's control registers. If the 8276 needs servicing, the 8051 fills the row buffer for the CRT display's next line. If the 8276 generates a vertical retrace interrupt, the buffer pointers are reloaded with the display memory location that corresponds to the first character of the first display line on the CRT. The vertical retrace also signals the processor to read the keyboard for a key closure. . 6.1 As mentioned previously the 8051 fills the 8276 row buffer without the need of a DMA controller. This is accomplished by using a Quad 2-input multiplexor (Figure 6.1.0) as the transfer logic shown in the block diagram. The address line, P2.3, is used to select either of the two inputs. When the address line is low the RD and WR lines perform their normal functions, that is read and write the Hardware Description 8051 P2.3~ The following section describes the unique characteristics of this design. 6.1.1 8051 RD 1A 8051 WR Peripheral Address Map 2A +5V The display RAM, 8276 registers, and the 8276 row buffers are memory mapped into the external data RAM address area. The addresses are as follows: SEL Y1 -8276WR 18 ~ Y2 -8276 BS 2B L....- 3A Y3 f--8276 RD 3B Read and Write External Display RAM Write to 8276 row buffers from Display RAM Write to 8276 Command Register (CREG) Write to 8276 Parameter Register (PREG) Read from 8276 Status Register (SREG) - - Address 1000H to 17CFH Address 1800H to IFCFH P2.4 Address OOOIH Address OOOOH l{>- DISPLAY RAM CS Figure 6.1.0 Simplified Version Of The Transfer Logic Address OOOIH 2-85 AP-223 6.1.2.1 8276 or the external display RAM depending on the states of their re~ctive chip selects. If the address line is high, the 8051 RD line is transfonned into BS and WR signals for the 8276. While holding the address line high, the 8051 executes an external data move (MOVX) from the display RAM to the accumulator which causes the display RAM to output the addressed byte _onto the data bus. Since the multiplexor turns the same 8051 RD pulses into BS and WR pulses to the 8276, the data bus is thus read into the 8276 as a Buffer transfer. This scheme allows 80 characters to be transferred from the display RAM into the 8276 within the required character line time of 635 microseconds. The 8051 easily meets this requirement by accomplishing the task within 350 microseconds. 6.1.2 Undecoded Keyboard Incorporating an undecoded keyboard controller into the other functions of the 8051 shows the flexibility and over all CPU power that is available. The keyboard in this case is a full function, non-buffered 8 x 8 matrix of switches for a total of 64 possible keys. The 8 send lines are connected to a- 3-to-8 open-collector decoder as shown in Figure 6.1.1. Three high order address lines from the 8051 are the decoder inputs. The enabling of the decoder is accomplished through the use of the PSEN signal from the 8051 which makes the architecture of the separate address space for the program memory and the external data RAM work for us to eliminate the need to decode addresses externally. The move code (MOVC) instruction allows each scan line of the keyboard to be read with one, instruction. Scanning The Keyboard Throughout this project, provision have been made to make the overall system flexible. The software has been written for various keyboards and the user simply needs to link different program modules together to suit their needs. The keyboard is read by bringing one of the eight scan lines low sequentially while reading the return lines which are pulled high by an external resistor. If a switch is 5V - 10kO ~ PO.7 8051 DATA BUS po.o 1N4305 --,.. .~, , , , " 74156 P2.0 - A 2YO P2.1 - B 2Y1 P2.2 L 1C 2Y2 2C 2Y3 --L 1G 1YO 2G 1Y1 FROM 8051 PSEN '< '< '< '< '< '< '< '<, '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< 1Y2 1Y3 '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< '< SWITCH MATRIX Figure 6.1.1 Keyboard 2-86 AP-223 closed, the data bus line is connected through the switch to the low output of the decoder and one of the data bus lines will be read as a O. By knowing which scan line detected a key closure and which data bus line was low, the ASCII code for that key can easily be looked up in a matrix of constants. PUM-51 has the ability to handle arrays and structured arrays, which makes the decoding of the keyboard a trivial task. Since the Shift, Cap Lock, and Control keys may change the ASCII code for a particular key closure, it is essential to know the status of these pins while decoding the keyboard. The Shift, Cap Lock, and Control keys are therefore not scanned but are connected to the 8051 port pins where they can be tested for closure directly. The 8 receive lines are connected to the data bus through germanium diodes which chosen for their low forward voltage drop. The diodes keep the keyboard from interfering with the data bus during the times the keyboard is not being read. The circuit consisting of the 3-to-8 decoder and the diodes also offers some protection to the 8051 from possible Electrostatic Discharge (ESD) damage that could be transmitted through the keyboard. 6.1.2.2 Decoded Keyboard A decoded keyboard can easily be connected to the system as shown in Figure 6.1.2. Reading the keyboard can be evoked either by interrupts or by software polling. The software to periodically read a decoded keyboard was not written for this application note but can be accomplished with one or two PUM-51 statements in the READER routine. A much more interesting approach would be to have the servicing of the keyboard be interrupt driven. An additional external interrupt is created by configuring timer/ counter 0 into an event counter. The event counter is SCAN initialized with the maximum count. The keyboard controller would inform the 8051 that a valid key has been depressed by pulling the input pin TO low. This would overflow the event counter, thus causing an interrupt. The interrupt routine would simply use a MOVC (PSEN is connected to the output enable pin of the keyboard controller) to read the contents of the keyboard controller onto the data bus, reinitialize the counter to the maximum count and return from the interrupt. 6.1.2.3 Serial Decoded Keyboard The use of detachable keyboards has become popular among the manufacturers of keyboards and personal computers. This terminal has provisions to use such a keyboard. The keyboard controller would scan the keyboard, debounce the key and send back the ASCII code for that key closure. The message would be in an asynchronous serial format. The flowchart for a software serial port is shown in Figure 6.1.3. An additional external interrupt is created as discussed for the decoded keyboard but the use in this case would be to detect a start bit. Once the beginning of the start bit has been detected, the timer/counter 0 is configured to become a timer. The timer is initialized to cause an interrupt one-half bit time after the beginning of the start bit. This is to validate the start bit. Once the start bit is validated, the timer is initialized with a value to cause an interrupt one bit time later to read the first data bit. This process of interrupting to read a data bit is repeated until all eight data bits have been received. After all 8 data bits are read, the software serial port is read once more to detect if a stop bit is present. If the stop bit is not present, an error flag is set, all pointers and flags are reset to their initial values, and the timer/counter is reconfigured to an event counter to detect the next start bit. If the stop bit is present, a valid flag is set and the flags and counter are reset as previously discussed. KEYBOARD CONTROLLER BUS KEYBOARD 8051 " I RECEIVE DATA READY "v FIgure 6.1.2 CS v PORTO TO PSEN Using A Decoded Keyboard 2-87 AP-223 RETURN RETURN RETURN Figure 6.1.3 Flowchart for the Software Serial Port 6.1.4 System Timings The requirements for the BALL BROTHERS. TV-12 monitor's operation is shown in table 6.1.0. From the monitor's parameters, the 8276 specifications and the system target specifications the system timing is easily calculated. 500 Hz of 15,750 Hz, we 'must choose either one or two character line times for horizontal retrace. To allow for a little more margin at the top and bottom of the screen, two character line times was chosen for the vertical retrace. This choice yields 250 + 20 = 270 total character lines per frarr. r . Assuming 60 Hz vertical retrace frequency: The 8276 allows the vertical retrace to be only an integer mUltiple of the horizontal character lines. Twenty-five display lines and a character frame of 7 x 10 are required from, the target specification which will require 250 horizontal lines. If the horizontalfrequency is to be within 60 Hz * 270 = 16,200 Hz horizontal frequency and 1116,200 Hz * 20 horizontal sync times = 1.2345 milliseconds 2-88 AP-223 Table 6.1.0 CRT Monitor's Operational Requirements PARAMETER RANGE Vertical Blanking Time (VRTC) 800 /-Lsec nominal Vertical Drive Pulsewidth 300 /-Lsec "" PW "" 1.4 ms Horizontal Blanking Time (HRTC) 11 JLsec nominal Horizontal Drive Pulsewidth 25 JLSec "" PW "" 30 /-Lsec 15,750 +500 pps Horizontal Repetition Rate The 1.2345 milliseconds of retrace time meets the nominal VRTC and vertical drive pulse width time of .3mSec to 1.4mSec for the Ball monitor. 6.2 Software Description The next parameter to find is the horizontal retrace time which is wholly dependent on the monitor used. Usually it lies between 15 and 30 percent of the total horizontal line time. The software for this application was written in a "foreground-background" format. The background programs are all interrupt driven and are written in assembly language due to time constraints. The foreground programs are for the most part written in PUM-51 to ease the programming effort. A number of subroutines are written in assembly language due to time constraints during execution. Subroutines such as clearing display lines, clearing the screen, and scanning the keyboard require a great deal of 16 bit adds and compares and would execute much slower and would require more code space if written in PUM-51. The background and foreground programs talk to each other through a set of flags. For ~xample, the PUM-51 foregrounp program tests "SERIAL$INT" to determine if a serial port interrupt had occurred and a character is waiting to be processed. 6.2.1 Since most designs display a fixed number of characters per line it is useful to express the horizontal retrace time as a given number of character times. In this design, 80 characters are displayed, and it was experimentally found that 20 character times for the horizontal retrace gave the best results. It should be noted if too much time was given for retrace, there would be less time to display the characters and the display would not fill out the screen. Conversely, if not enough time is given for retrace, the characters would seem to run off the screen. One hundred character times per complete horizontal line means that each character needs: Software Overview 6.2.2 The Background Program (1116,200 Hz) 1100 character times = 617.3 nanoseconds If we multiply the 20 character times needed to retrace by 617.3 nanoseconds needed for each character, we find 12.345 microseconds are allocated for retrace. This value falls short of the 25 to 30 microseconds required by the horizontal drive of the Ball monitor. To correct for this, a 74LS 123 one-shot was used to extend the horizontal drive pulse width. The dot clock frequency is easy to calculate now that w~ know the horizontal frequency. Since each character is formed by seven dots in the horizontal axis, the dot clock period would be the character clock (617.3 nanoseconds) divided by the 7 which is equal to 11.34 MHz. The basic dot timing and CRT timing are shown in the Appendix. Two interrupt driven routines, VERT and BUFFER, (see Fig. 6.2.0) request service every 16.67 milliseconds and 617 microseconds respectively. VERT's request comes during the last character row of the display screen. This routine resets the buffer pointers to the first CRT display line in the display memory. VERT is also used as a time base for the foreground program. VERT sets the flag, SCAN, to tell the foreground program (PUM-51) that it is time to scan the Keyboard. VERT also increments a counter used for the delay between transmitting characters in the AUTO$REPEAT routine. The BUFFER routine is executed once per character row. BUFFER uses the multiplexor discussed earlier to fill the 8276's row buffer by executing 80 external data moves and incrementing the Data Pointer between each move. 2-89 AP·223 as discussed earlier. After all variables and flags are initialized, the processor is put into a loop waiting for either VERT to set SCAN so the program can scan the keyboard, or for the serial port to set SERIAL$INT so the program can process the incoming character. RE-INITIALIZE 8278 ROW BUFfER POINTER TO THE The vertical retrace is used to time the delay between keyboard scans. When VERT gets set, the assembly language routine READER is called. READER scans the keyboard, writing each scan into RAM to be processed later. READER controls two flags, KEYO and SAME. KEYO is set when all 8 scans determine that no key is pressed. SAME is set when the same key that was pressed last time the keyboard was read is still pressed. TOP OF THE DISPLAY After READER returns execution to the main program, the flags are tested. If the KEYO flag is set the main program goes back to the loop waiting for the vertical retrace or a serial port interrupt to occur. If the SAME flag is set the main program knows that the closed key has been debounced and decoded so it sends the already known ASCII code to the AUTO$REPEAT routine which determines if that character should be transmitted or not. RETURN RETURN Figure 6.2.0 Flowcharts For VERT and BUFFER Routine The MOVX reads the display RAM and writes the character into the row buffer during the same instruction. SERBUF is an interrupt driven routine that is executed each time a character is received or transmitted through the on-chip serial port. The routine first checks if the interrupt was caused by the transmit side of the serial port, signaling that the transmitter is ready to accept another character. If the transmitter caused the interrupt, the flag "TRANSMIT$INT" is set which is checked by the foreground program before putting a character in the buffer for transmission. If the receiver caused the interrupt, the input buffer on the serial port is read and fed into the fifo that has been manufactured in the internal RAM and increments the fifo pointer ."FIFO." The flag "SERIAL$INT" is then set, telling the foreground program that there is a character in the fifo to be processed. If the read character is an ESC character, the flag "ESCSEQ" is set to tell the foreground program that an escape sequence is in the process of being received. If KEYOand SAME are not set, signifying that a key is pressed but it is not the same key as before, the foreground program determines if the results from the scan are valid. First all eight scans are checked to see if only one key was closed. If only one key is closed, the ASCII code is determined, modified if necessary by the Shift, Cap Lock, or Control keys. The NEW$KEY and VALID flags are then set. The next time READER is called, .if the same key is still pressed, the SAME flag will be set, causing the AUTO$REPEAT subroutine to be called as just discussed. Since the keyboard is read during the vertical retrace, 16.67 milliseconds has elapsed between the detection of the pressed key and reverifying thai the key is still pressed before transmitting it, thus effectively debouncing the key. The AUTO$REPEAT routine is written to transmit any key that the NEW$KEY flag is set for. The counter that is increl1}ented each time the vertical refresh inteIplpt is serviced causes a programmable delay between the first transmission and subsequent auto repeat transmission. Once the NEW$KEY character is. sent, the counter is initialized. Each time the AUTO$REPEAT routine is called, the counter is checked. Only when the counter overflows will the next character be transmitted. After the initial delay, a character will be transmitted every other time the routine is called as long as the key remains pressed. 6.2.3.1 6.2.3 The Foreground Program Handling Incoming Serial Data One of the criteria for this application note was to make the software less time dependent. By creating a fifo to store incoming characters until the 8051 has time to pro- The foreground program is documented in the Appendix. The foreground progra~ starts off by initializing the 8276 2-90 AP·223 cess them, software timing becomes less critical. This application note uses up to 8 levels of the fifo at 9.2KBAUD, and I level at 4.8KBAUD and lower. As discussed earlier, the interrupt service routine for the serial port uses the fifo to store incoming data, increments the fifo pointer, "FIFO", and sets SERIAL$INT to tell the main program that the fifo needs servicing. Once the main program detects that SERIAL$INT is set the routine DECIPHER is executed. When DECIPHER is executed, the first block begins looking at the first character of the fifo for a displayable character. If the character is displayable, it is placed into the display RAM and the software pointer "TOP" that points to the character that is being processed is incremented to the next character. The character is then looked at to see if it too is displayable and if it is, it's placed in the display RAM. The process of checking for displayable characters is continued until either the fifo is empty or a non-displayable character is detected. In our example, three characters are placed into the display RAM before a nondisplayable character is detected. At this point the fifo looks like figure 6.2.I-B. DECIPHER has three separate blocks; a block for decoding displayable characters, a block for processing Escape sequences, and a block for processing Control codes. Each block works on the fifo independently. Before exiting a block, the contents of the fifo are shifted up by the amount of characters that were processed in that particular block. The shifting of the characters insures that the beginning of the fifo contains the next character to be processed. FIFO is then decremented by the number of characters processed. Before entering the next block, the remaini'ng contents of the fifo between TOP, that is now pointing to I BH and (FIFO-I) are moved up in the fifo by the amount of characters processed, in this example three. TOP is reset to 0 and FIFO is decremented by 3. The serial port interrupt is inhibited during the time the contents of the fifo and the pointers are being manipulated. The fifo now looks like figure 6.2.I-C. Let's look at this process more closely. Figure 6.2.I-A shows a representation of a fifo containing 5 characters. The first three characters in the fifo contain displayable characters, A, B, and C respectively with the last two characters being an ESC sequence for moving the curser up one line (ESC A) and FIFO points to the next available location to be filled by the serial port interrupt routine, in this case,S. TOP-.. 41H (A) 41H (A) 42H (B) 42H(B) 43H(C) 43H (C) 1BH (ESC) TOP-" 1BH (ESC) If at the end of the DECIPHER routine, FIFO contains a 0, the flag SER$INT is reset. If SER$INT remains set, DECIPHER will be executed immediately after returning to the main program if SCAN had not been set during the execution of the DECIPHER routine, otherwise DECIPHER will be called after the keyboard is read. 41H (A) 41H (A) FIFO-. The execution is now passed to the next block that processes ESC sequences. The first location of the fifo is examined to see if it is an ESC character (lBH). If not, the execution is passed to the next block of DECIPHER that processes Control codes. In this case the fifo does contain an ESC code. The flag ESC$SEQ is checked to see if the 8051 is in the process of receiving an ESC sequence thus signifying that the next byte of the sequence has not been received yet. If the ESC$SEQ is not set, the next character in the fifo is checked for a valid escape code and the proper subroutine is then called. The fifo contents are then shifted as discussed for the previous block. Due to the length of time that is needed to execute an ESC code sequence or a Control code, only one ESC code and/or Control code can be processed each time DECIPHER is executed. FIFO-.. (A) (8) TOP-.. 1BH (ESC) 6.2.4 41H(A) Memory Pointers and ScrOlling FIFO-.. The curser always points to the next location in display memory to be filled. Each time a character is placed in the display memory, the curser position needs to be tested to determine if the curser should be incremented to the beginning of the next line of the display or simply moved to the next position on the current display line. The curser position pointers are then updated in both the 8276 and the internal registers in the 8051. (C) FIGURE 6.2.1 FIFO 2-91 AP-223 When the 2000th character is entered into the display 'memory, a full display page has been reached signaling the need for the display to scroll. The memory pointer that points to the display memory that contains the first character of the first display line, LINEO, prior to scrolling contains 1800H which is the starting address of the dIsplay memory. Each scrolling operation adds 80 (SOH) to LINEO which will now point to the following row in memory as shown in figure 6.2.2-B. LINEO is used during the vertical MEMORY LOCATION 18DDH refresh routine to re-initialize the pointers associated with filling the 8276 row buffers. The display memory locations that were the first line of the CRT display now becomes the last line of the CRT display. Incoming characters are now .entered into the display memory starting with 1800H, which is now the first character of the last line of the display screen. MEMORY LOCATION 184FH MEMORY LOCATION 1800H NEW TEXT INSERTED HERE LINED LINED '"---t- ROW (80 CHAR) MEMORY LOCATION 1850H DURING FIRST PAGE MEMORY LOCATION lF80M B) AFTER 1ST SCROLLING OPERATION A) BEFORE SCROLLING LINEO - MEMORYLOCATIO N 18ADH ~ I NEW TEXT INSERTED HERE fj' LINEO - MEMORY LOCATION 18FOH C) AFTER 2ND SCROLLING OPERATION - ~ NEW TEXT I f.- INSERTED HERE D) AFTER 3RD SCROLLING OPERATION MEMORY LOCATION 1800H LINED LINED NEW TEXT INSERTED HERE NEW TEXT INSERTED HERE F) AFTER 25TH SCROLLING OPERATION E) AFTER 24TH SCROLLING OPERATION Figure 6.2.2 Pointer Manipulation During Scrolling 2-92 Ap·223 6.2.5 Software Timing The use of interrupts to tie the operation of the foreground program to the real-time events of the background program has made the software timing non-critical for this system. 6.3 System Operation Following the system reset, the 8051 initializes all onchip peripherals along with the 8276 and display ram. After initialization, the processor waits until the fifo has a character to process or is flagged that it is time to scan the keyboard. This foreground program is interrupted once every 617 microseconds to service the 8276 row buffers. The 8051 is also interrupted each 16.67 milliseconds to re-initialize LINEOand to flag the foreground program to read the keyboard. 2-93 As discussed earlier, a special technique of rapidly moving the contents of the display RAM to the 8276 row buffers without the need of a DMA device was employed. The characters are then synchronously transferred to the character generator via CCO-CC6 and LCO-LC2 which are used to display one line at a time. Following the transfer of the first line to the dot timing logic, the line count is incremented and the second line is selected. This process continues until the last line of the character is transferred. The dot timing logic latches the ouput of the character ROM in a parallel in, serial out synchronous shift register. The shift register's output constitutes the video information to the CRT. AP-223 Appendix 7.1 CRT Schematics ~¢ ,,~D~;-:. +5V ~~ vce ~ ~ \ AST BO~_-:3:fI: :~ JDN~n t L39::::-_D_BI-7+++-+-+-I-D ... ·38 37 4 7 ~ 5V~ EA ALE a , 9 5 35 34 33 13 14 17 L S 3 12 15 18 • 3 2 30 ~ SHFTCDNTROL_ - LOCAL- GND '-------------:,~: 00 6051 11 13 o 74156--2! BAUDBAUDaAUDCAP LOCKCLEAR TO SENDREADY- 12~ 2K )( B STATIC RAM '\7' INT1 RXD TXO vee t"""c.....__"';''iA7 11 E ~ INTO ~ 7 AO 6 38 pO.7 t'3=2c.....-'H-t-t-t-+++--,,16'i .---..............-fGND SERIALIN~ SERIALDUT~ 7 5 6 P10 P11 15 P12 16 P13 .,4 17 ~---------------------__tD7 A10tii- Alt;.AI P15 AD r.-;'7,..-_______________________-r:'8:......J20 P1. P17 WR TO 11 .2.0 1& P2A 26 I 5V ...! p..--.! +5V 5 --+-t---i t6 1AVCC SEC 18 2A 1/2 ~ 1/2 r----- as em 113 ~iii8276 7'157 10 '---;3B 4A 4D Wii.2n 7 8TB GND 15~ 2-94 J21 AP·223 1"817'61514'3'2 hD1 DO ceo vee 21 ...." .. ", 3 7 " -E-AO --.!.Ri) ~Wii • ee, • ~ 2 7 ~cs ---!iiS co . ·· " .. • · 5 Vee GHD_ co Oe 2 , • 7 7 eLK !,: ~: 11 11 co , 1'2 10 ~ •• I"~, L . 1G 'G '" , '" GND '" . '( '( '( '( '( '( '( '( '( '( '( '( '( '( '{ '( '( '( '( '{ '( '( '( '( V l ,[ 14 Rl I CEXT! GO R2 - - f ~~XT2 '_V---"--+":'l:~ Q' _ _ _ 9 AI ::c ~ CLR 11 eLK 74123 GHD 2-95 :~ eH GNO : 10~n ~".~~"30a .1A~i'l~30 B'MIM 0"33("~3CAr-lA11"A~ 3F : HUI7;MI'lI'l~~il~1"'~IJ"aI'l18:l :1"3201 ~:lA 'M ~23~~nq :1~31BJ331C22322A2~221C03A93CA~1A~~131C~~21 :lAAI913:'lC222~lC02A23E1~3E2~1~lq2~221C0I'lRF : 1~l'llM3:n:.n 81412 3~1 '-'HI;'03::021 t::2A2~221CW~:7 : 10Jlt:H~~338.H~~21E22221:"'''3E2rnw:,g14 ~4 !W~":n :1~~IC~3~lC22221C22221cnAIC22223C2"13qEq17q :lA31D0A~a~~3A~01A11q1a~1J3~3~R~1~1JB1q~4f3 :10alE~1~1033~402~~AR130~M3103E~~3~9~1A3~59 :10~lfJa~14AqI02~1~~9~4A~lC222"'19I'lq18AA0~21 : 10n:i:'3tHC222A3A. lM23:W~ar:!l422223e22221'l/n2 :lA321~~::31E24241C24241E11'lIC22~2A2A2221Cg"74 :lA~22"a~lE24242424241~A03~~202~~A2~23E~14: : 1 (i::32 3~'A131::ri2020S"2A2~2~;nC(l2A2 3.lI.22223C03r;~ : 1~~J24{~~1l2222223i222222J~lC!B;'R!' 9'~R 131Cfl~44 : H'325:n17:~2 02f12~2i~221C!1:l2212Clll.W)1A1222:~~E€ : lli:W;~a~A2 ;.'l2~ ;112(-\2 i~23F.:'il('J223')2A2A2?2?22W~ 32 :10~27J~3222~2~32222222~OlC22222222221:~192 : l:~(~28·.~;'~1t:::22221 E~2\'2'~2r~~IC2222?22A122:"'~r'E : 101J29!l ~~1 t:: 22221 i::'~A 1222M3'::Cl2"21C2~2~lE3~Er.; : HM2AI1 ~"3E';B("8.H~ '~a B:' 3'l;12222222222221CCneq :lOIJ2~~~~222222222214~qAJ222222222A3r.;220~~E : llia2C;,j"~222214W:H42222.J:'l22222214!i813:.' 9 ~~t::4 : 1('J32D!~A:'13t:: 2{n ~lagli4"23r:~:nCA·1:14041'l4 A.llCA11R : lIi1'l2t::W-lMl il:'2Cl40':H~2 ;,):'lW1"392~2 ;1 2 i'2 ~ 2"3 ~.l":;(IJ :1~32f~~0~81C2A~3~BJR~3~~3~~~~A~~A~~~~17~12 : 1 !1~30;lOt'l1~9~n 1 (~Yl:IY'3:1(l:1::l:1~~'~:~ 3'::2(nC22'3:"~4i:: :10~31~~0~2A21A2G22221E~~~",a038~4~4A~3q~~3~ : 13ti32Wl:12i-l202:::322222 '3CrH~"~::l113q24aC~4dq ~~')~ : 10"330il03R24040t::iH ~4"4 r'iI~f'l:1:HC22?23C2!lI3CM : H~I.n400('Ja2!' 21 ~2t;222222i100 8(i111 ~:H~;'R ";J~9'Htl4:i : 11l~35~:'ln'''''''02~2:i21lA42418(12(122212.";J~1~?2('J:;'::3 : 10.,3t):M:Hl ~m8(~8~ 3~8~39;'/,.,a'~\~3 3~2A21\2222(~~7f :10337A~A::3~l~11\2;222222~~~a~('JIR2424241R~~3~ : 1 ("03B':1:13~~A:~ It:22221t:(.'l2"2"'~l'la lC2 2223'::2~20"J : 10~39;M~~33;nA2r,32:'2;;'2:.l3:":l~~3q141A2rHC~1q7 : 1 ""3M' J~~~;'RICA ~(-IR" q9~:l(l~~':l~ 22222232 4C"~"9'; :10i13~003;'3~"222222140~"~~J~~22222A1EI4f'l:l~~ : 1 ~1~' 3Cvl:~3a:, ~!12214!1 'U 42 2~lil" ;m:l22? 2 22 3(: 2J3A~f : 1"~3D!'~'MW~(Br: 10:"8l'4 3t::~:;j188qA9'Bq9R91 ~H2f : 10:n~~;,a:'BAS~" 3lB Atl$iA ..,338 ~C9.~91219~9100:M51 :IYla3f0~3393i19C2dd0~1~a~a3~~3~~A00~~~00:l~95 2-100 AP-223 Appendix 7.7 Composite Video In this design it was assumed that the CRT monitor required a separate horizontal drive, vertical drive, and video input. Many monitors require a composite video signal. The schematic shown in Figure 7.7.0 illustrate how to generate a composite video from the output of the 8276. 5OK :J The dual one-shots are used to provide a small delay and the proper horizontal and vertical pulse to the composite video monitor. The delay introduced in the horizontal and vertical timing is used to center the display. The 7486 is used to mix the vertical and horizontal retrace. Ql mix the video and retrace signals along with providing the proper D.C. levels. 4.7K 2 HRTe 1 .f"" 2.2 K 2Q 15 4 I 5 5 3 t--5Y 470pF 14 " 74LS221 2Q B, A, ex ex - Rxex- 0, L 10K 74LS221 6 7 B2~ 5y2 .001"F .1"F II II 6 " " 7 7486~ 5Y I 2 B, 1 A, ex -RXCX 0 ./ VRTC ~ ~ cx 5OK 2.2K .05 14 II 15 " B2~ +5 7486 6800 1KO +5 1KO COMPOSITE VIDEO OUT VIDEO 1500 -= Figure 7.7.0 Composite Video 2-101 AP-223 Appendix 7.8 Software Documentation /**********************************************************.*.***************** ******************.*.****.****.*.*********.******************.***************** .t*t ••• ******* ***.* •• SOF"lWARE ***.*** .****** *.***.* *.***** IXJC(roNTATIl~ TEIfo\INAL aJn'R)LLER roR TIlE 8051 APPLICATICN 00l'E **** ••• ************************.*.**********************.*******.*.********.**.*** •••• *********.* •• ***.******.****************** •• ***********************.* •••• ****** MIMlRi MAP ASSOCIATED WITH PERIPHERAL DMCES (USING tOJX): 8051 8051 8276 8276 8276 WR AND READ DISPLAY Rl\MADDRESS 100OH'ro 17CE1f WR DISPIAY R!\M TO TIlE 8276- ADDRESS 1800H TO lR:EH CXMWID ADDRESSADDRESS OOOlH PARlIMI!lrER ADDRESSADDRESS OOOOH srATUS RIDISl'ERADDRESS OOOlH MIMlR':( MAP roR READIm TIlE KElOOARl) (USING MJI.lI:): KElOOARl) ADDRESS- ADDRESS 10FFH'ro 17FFH /*******~*****~**.*** BrARl' MAIN PIOORAM. **.**** •• ******* •••• **.****/ /* BEGIN B'f FUlTING TIlE AOCII CODE roR BLANK IN TIlE DISPLAY R!\M* / INIT: {nu. . 2000I.o::ATICNS IN TIlE DISPLAY R!\M WITH SPJ!C:!;S (AOCII 20H)} /* I INITIALIZE FOINl.'ERS, R!\M BITS, Ell'C. INITIALIZE INITIALIZE INITIALIZE INITIALIZE */ FOINI'ERS AND FLAGS} TOP OF TIlE CRr DISPIAY "LINEO"=180OH} 8276 BUFFER POINl'ER "RASTER" =180OH} DISPIAY$R!\M$POINTER=OOOOH} /* INITIALIZE TIlE 8276 */ RESEr TIlE 8276} . INITIALIZE 8276 ro 80 ClIARl\C1'E1VRJ } INITIALIZE 8276 'ro 25,R:MS PER FRAME} INITIALIZE 8276 'ro 10 LINES PER lO'I} INITIALIZE 8276 oro NCN-BLIIIONG UNDERLINE aJRSER} INITIALIZE aJRSER TO IDlE FOSITICN (00,00) (UPPER LEFt' HAND CORNER)} mARl' DISPIAY} ENABLE 8276 lNl'ERlIJPl'} \ \ I /* SET UP 8051 lNl'ERlIJPl'S AND PRlORITIFS SERIAL roRl' HAS HIGHEsr lNl'ERlIJPl' PRloRi:~} IN!'ERHlPl'S ARE EDGE SENSITIVE} , ENABLE 'ro Nm CHARl\CTER 3m> THRXJGH Nl'3 CHARl\CTER */ */ END; ];lID; /* PRX:EWRE TRANiMIT- CN::E THE Hoor a:MP!1I'ER SIGNALS THE 8051H BY' BRINGING - THE CIEAR-ro-SEND LINE IDN, THE AOCII CIlARl\CTER IS R1l' mro THE SERIAL PORT.*/ TRlINiMIT : PR:cEWRE; IF {THE TER-IINAL IS Cti-LINE} THEN 00; I . ' WAIT um'IL THE CLEAR$'ro~SEND LINE IS IDN AND um'IL THE 8051 SERIAL PORl' TX IS !Ul' BUS{ (TRANiMIT$INT=l) } TRANSMIT THE ASCII CODEI CLFAR THE FLAG "TRANSMIT$mr~. THE SERIAL PORl' SERVICE lO1l'INE WILL 8m' THE FLAG WHEN THE SERIAL PORT IS FINISHED TRlINiMITTING} END; ELSE {THE TER-IINAL IS IN THE LOCAL KlIlE} 00; ! R1l' THE AOCII COIlE IN THE FIFO} INCREMEN!' THE FIFO POINl'ER} 8m' SERIAL$mr} END; END TRANSMIT; . 2-104 AP-223 /* PKlCELURE DEX:!IP!lER: THIS PKlCELURE DEIXlDES THE HOSl' CCMPUTER' S MESSAGES AND DEl'ER>\.INES WHEl'HER IT IS A DISPLAYABLE CHAAACTER, CXJNl'IDL SEX;;lUENCE, OR AN ESCAPE S~ THE PKlCELURE THEN N:l'S l\OX)RDINGLY */ DEX:!IPHER: STARl'$DEX:!IPHER: VALID$RECEPTION=O; 00 WHILE {THE FIFO IS NO!' EMPl"i AND THE CHAAACTER IS DISPLAYABLE) ROCEIVE={ASCII CODE) CALL DISPLAY, {NEXT CHAAACTER) END, IF IF CI!ARACl'ERS WERE DISPLAYED) '!HEN DlSABIE SERIAL PORT INl'ERRlPr) M:lVE THE REMAINING CXlmNI'S OF THE FIFO UP 'lXl THE BmINNING OF THE FIR)) ENABLE SERIAL PORT INl'ERRlJPI'1 SE:r THE VALID$RECEPTION FLAG {nm FIR) IS EMPl"i) THEN {CLEAR THE "SERIAL$Im FLAG AND REll.'URN) IF I'lliE NEXT CHARACl'ER IS AN "ESC" CODE } THEN 00: {I£lCK AT THE CHAAACTER IN THE FIR) AFI'ER 'lliE ESC CODE AND CALL THE CDRREX:!T SUBR:Ul'INE} b..u. UP$lATICN FULLCMED Blr TIlE CXlUJ:IN INFU!W.TICN */ MJV$CURSER: WAIT UNTIL TIlE FIR> lIAS REX:ElVED THE NEXT TW) CHARl'Cl'ERS} {MJ\IE TIlE ClIIQ:R ro THE LOCM'ICN SPECIFIED IN THE ESCAPE sa;;oFNCE}. MJ\IE TIlE DISPLAY$RAM$POINTER ro THE Hi TW)} mABLE TIlE SERIAL PORl' INl'ERlIlPl'} /* TW) LOCM'ICNS IN MEM)R{} PR:lCEIlJRE LEFl' Cl1IQ:R: 'IlIIS PR:lCEIlJRE MJ\IES THE Cl1RSER LEFr Rl MAP AS~IA'I'ED WITH PERIPHERAL I>INICES (USING MO\Il(): 8051 8051 8276 8276 8276 WR AND READ DISPlAY RIlMWR DISPlAY RIlM 'l'O THE 8276-O»IAND ADDR&S5PARI\ME:l'ER ADDR&S591'A'lUS REIiISl'ER- ADDR&SS ADDR&SS ADDR&SS ADDR&SS ADDR&SS 1000H 'l'O 17CFH 1800H oro 1mB OOOlH 000011 OOOlH oro' 17FFH NXORDn«; oro THE 'l'iPE ADDR&SS 10FFH THE FOLI.amiIG SOFlWARE SWl'l'CIIES Kl91' BE SJ!:r '!HAT IS ron«; oro BE USED. ~1KlMD Slfl- SEll' WHm usm:; AN tJNDJOCXlIlEo ~1KlMD IS oro BE USED SW2- SJ!:r WHm usn«; A 0E:XlDID OR A SERIAL 'l'iPE OF Im:iOOMD tJNDIiXDDED ~BOf\H)- CRrPrM.OB.1 ,CRrASM.OBJ ,KElCBD.OBJ ,PI.H5l.LIlI , DEXDDED KE:lllClMI>-CIm'lM.OB.1 ,CRrASM.OB.1 ,DEXXDE.OB.1 ,P1H51.LIB 0Erl\CHED KElCBOIIRO-CRl'PIM.OB.1 ,CRrASM.OB.1 ,DEll'ACH',OB.1 ,PI.H5l.LIB */ $SJ!:r (SWl) $l\ESEr (SW2) 2·112 OF AP-223 PLjM- 51 cnlPILER CRl'$CXJNTR)LLER: 1 1 00; I*t •••• _••* ••••••• DECLARE LITERALS *•••• ******* •••• *******./ 2 3 4 5 6 1 1 1 1 1 7 8 9 1 1 1 10 1 11 12 1 1 O&:U\RE LI£ LI'l'ERALI.Il 'L' ,OOH,3El1,OOH,00H,00H, /* SCAN 3, SHIFl' =1; M,<,>,? *1 1* *1 OOH, 'AZXCVBN' , SCAN 4, SHIFl' =1; A,Z,X"C,V,S,N *1 .1* 'Y' ,OOH,OOH,' DFGH', SCAN 5, SHIFl' =1; Y, SPACE, D,F ,G,H 1* 09H, '~' ,OOH, SCAN 6, SHIFl' =1; TAB, Q,W,S,E,R,T I" lBH,' 1"t$%&' ,OOH); SCAN 7, SHIFl' =1; ESC, 1,',i ,$,%,& ·1 *1 *1 $ENDIF 2-115 *1 *1 *1 *1 AP-223 PL;M-51 IaI; aJRSER$OOlllMN=O; aJRSER$CII=l; CALL LOI\D$aJRSER; END CARRIAGE$REl1'URN; 2·119 */ AP·223 PL/M- 51 cnu>ILER CRl'CXJNI'R:lLLER /* PRJCEIlJRE!O'IN CURSER: THIS PKlCEllJRE tOJES TIlE CURSER !O'IN OOE IDI B'i AlIlING 1 TO TIlE CURSER lUI RlIM LOCATICN TIlEN C1ILL UlN) CURSER */ 64 1 65 66 67 68 2 3 3 3 IX)iN$CURSER: PKlCEllJRE : IF CURSER$RJW < 18H THEN DO; 0 TIlEN 3 DO, 84 3 3 85 86 87 88 89 3 3 3 3 CURSER$1Ol=CURSER$1DI _. 1; aJRSER$CN=1; C1ILL UlI\D$C1JRSER; IF DISPIAY$Rl\M$FOINTER<5OH THEN DISPIIIY$Rl\M$FOIN1'ER=DISPIIIY$Rl\M$POIN1'ERI-78011; ELSE DISPIIIY$Rl\M$FOINTER=DISPIAY$Rl\M$POINTER - SOlI; L=DISPIAY$Rl\M$POIN'l'ER-CURSER$(X)UJoIN; IF DISPIAY$RlIM(L)=OFlH '!'HEN /* 91 3 3 92 4 00; 93 94 4 C1ILL FILL; DISPIIIY$RAM (L) =2011; END; 90 4 95 4 96 3 1 97 LQCl{ POR END OF LINE*/ /* CiIl'JIl\C'lER */ /* IF TRUE FILL WITH /* SPACES */ ENO; END UP$CURSER; 2-120 */ AP·223 PLjM- 51 CD1PlLER CRl'CCNl'RJLLER /* PRX:EIl.JRE RIGHI' aJRSER: THIS PRX:EIl.JRE !ofJVES THE aJRSER RIGHI' ONE COLUMN B'f AIDING 1 ro THE aJRSER COLUMN RAM ID:ATION THEN CALL WAD aJRSER */ 98 1 99 2 100 101 102 103 104 105 106 3 3 3 3 3 3 1 RIGIfl'$CURSER: PRX:E!lJRE; IF aJRSER$OJLUMN < 4m THEN 00; 0 THEN 00; , TEMP 1'IIm 001 L=DISPLAY$RAM$POINTE:RI- ( (OJRSER$!O'l-TEMP)· SOH) 1 IF L> 7CE1l 1'IIm 1* IF OOT OF RAM RI\OOE *1 DISPLAY$RAM$POINTER=L-7DOHl 1* RAP AmlND ro BEGINNING ~ ~~RIIM~ *1 DISPLAY$RIIM$POINTER=Ll 127 12B 3 2 ENDl ~ 001 129 130 131 132 133 134 3 4 4 4 4 4 135 136 137 13B 139 140 141 4 3 2 2 2 2 2 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 2 2 2 2 3 3 3 3 2 3 3 3 2 2 1 IF OJRSER$R:MTEMP 1'IIm DISPLAY$RI\M$POINrER=DISPIAY$RI\M$POINTER+ (~) i ELSE DISPLAY$RIIM$FOINrER=DISPIAY$RI\M$POINTER- (TEMP-O.lRSER$COUlMN) 1 aJRSER$CN=11 CALL LOAD$OJRSERi L=DISPLAY$RI\M$POINTER-aJRSER$COUJoINl IF DISPLAY$RIIM(L)=OFlH 1'IIm 1* UXI< FOR END FO LINE CIIARl\CTER*1 001 CALL FILLl 1* IF TRlE FILL WTI'H SPl\CES *1 01 SPLAY $RIIM (L) =2OHl ENDl ES=Oi 00 1=2 ro FIFO-21 SERIAL (I) =SERIAL (1+2) 1 ENDl FlFO=FIFO-21 ES=ENSPl END MO\I$OJRSERi 2-122 AP-223 PL/M-51 CCMPILER /* CRl'CXNI'IVILER PR:X:EllJRE ERASE FlU! CURSER 'IO END OF S::~: 157 1 ERASE$FI01SCURSER$TO$END$OF$SC~: i58 159 160 161 162 163 164 165 166 167 168 169 170 171 172 2 2 3 3 4 4 4 4 3 4 4 4 4 3 1 CALL BLINE; */ POCCELURE; /* ERASE QJRRENl' LINE IF CURSER$lO'l < lSH THEN 00; L=DISPLAY $ RIIM$POINrER-aJRSER$(X)IlJMNt SOH; /* GEr NEXT LINE */ 00 WHILE (L < 7DOH) AND (L <> (LINEO AND 7FFH)); DISPLA¥$RIIM(L)=OFlH; /* ERASE UNTIL LINEO OR */ L=LT50H; /* END OF DISPLAY RAM*/ END; L=O; 00 WHILE L <> (LINEO AND 7FFH); /* ERASE UNTIL LINEO */ DISPLA¥$RAM(L)=OFlH; L=LT5OH; END; END; END ERASE$FI01SCURSER$TO$END$OF$S::~; /* PR:X:EllJRE */ IDlE: THIS PR:X:EllJRE mvES THE QJRSER'IO THE 0,0 POSITIai 173 1 174 175 176 2 2 2 QJRSER$Qi=l; 177 2 CALL 178 179 2 1 DISPLAY$RAM$POINl'ER=(LINEO AND 7mI); END IDlE; IDlE: POCCELURE; QJRSER$RJit-:00 I QJRSER$CX)llJoIN=OO; I.O.>!D$O.JRSER; 2-123 */ AP-223 PL/M-51 77ftf THEN DISPIAY$RAM$POINl'ER=DISPLAY$RAM$POINl'ER-78OH; ELSE DISPLAY$RAM$POINl'ER=DISPLAY$RAM$POIN.l'ERI-5OH; L=DISPLAY$RAM$POINl'ER-CURSE:R$I1m; IF DISPIAY$RAM(L)=OFlH THEN /* UXJ( IDR END OF LINE OIARI\CTER*/ 00; CALL FILL; /* IF THJE FILL WITH SPACES */ DISPLAY$RAM(L)=2OH; END; END LINE$FEED; 2-124 AP-223 /* 210 1 211 212 213 214 2 2 2 2 215 216 217 218 219 220 221 222 223 224 225 226 2 3 3 3 3 4 4 4 4 227 228 3 2 229 230 231 2 2 1 3 3 3 PRlCEIlJRE DISPLAY: THIS PRlCEIlJRE WILL TAKE TIlE B:iTE IN !WI LABELED Ra::ElVE AND PUT IT INID TIlE DISPLAY !WI. */ DISPLAY: PRlCEIlJRE; DISPLAY$!WI(DISPLAY$RAM$POINTER)=Ra::EIVE; IF DISPLAY$!WI$POINTER=7CEll THEN /* IF END OF !WI */ DISPLAY$IWI$POINTER=OOOH; /* RAP AIOJND ro BEJGINNI~ ELSE DISPLAY$RAM$POINTER=DISPLAY$!WI$POINl'ERf-l; IF aJRSER$COLlM/=4Ell THEN 00; ClJRSER$COlllMN=OOH ; L=DISPLAY$RAM$POINTER; IF DISPLAY$!WI(L)=OFlH THEN 00; CALL FILL; DISPLAY$IWI(L)=2OH; END; IF aJRSER$RlW=18H THEN CALL SCOOLL; ELSE aJRSER$RlW=OJRSER$HlW+-l; END; ELSE aJRSER$COlllMN=CURSER$COUMfT1; C!JRSER$(N=1; CALL uwx::uRSER; END DISPLAY; 2-125 */ $E.JECl' /* PRlCEIlJRE DEX:IPHER: 'nUS PR:lCEnJRE DEXXlDES THE HOSl' CCMPUTER'S MESSAGES AND DE:I'ERUNES WIIE1'HER IT IS A DISPLAYABLE CHARACl'ER, a:Nl'lVL ~, OR AN EOCAPE SIQJENCE THE PRlCEIlJRE THEN 1CrS lIOCQRDIWIN */ 232 1 233 2 234 235 236 237 2 3 3 238 DECIPHER: PRlCEIlJRE; srARl'$DECIPHER: ~ID$ReCEPTION=O; 3 1=0; 00 WHIloE (I0 THEN 00; ES=O; K=FIFO-II 00 J=O 'lO KI SERIAL(J)=SERIAL(I); 1=1+11 241 242 243 244 245 3 4 4 /* DISIIBLE SERIAL INTE:RRJPl' NJIloE IIJVItC FIro /* KlVE FIro /* DII\BLE sERIAL INTE:RRJPl' 246 4 247 4 248 249 3 3 250 3 251 3 2 3 3 3 3 END; 2 3 IF (SERIAL (0) =lBH) THEN 00; IF (ESC$SSQ=1) AND (FIro<2) THEN ooro END$DECImER; K=(SERIAL(l) AND sm)-4OH; IF (K >0111) AND (K OOH THEN DO; TRl\N!MlT$CXJUNI''''l'Rl\N!MlT$COONl't1; , IF TR!IN!MlT$CXJUNI'=OFm THEN /*TSAY BImiEEN FIRSl' CHARACTER AND THE SBnID */ 00; /*SBnID CHARACTER */ CALL TR!IN!MlT; TR!IN!MlT$CXXJNl'=00; mo, ENO; ELSE ~I 4 4 4 4 4 3 1 0JRSER$QI=1; ClJRSER$CnlNr=O, IF TR!IN!MlT$'l'ClOOLE 1 THEN /* 2 VERt' Fl1l\Im3 BEll'WI!iSN 3m CALL TR!IN!MlT; /* 3m TIIRXJGH tmI CHARACTER TRlIN!MlT$'l'ClOOLE= 1m' TRl\N9UT$'l'ClOOLE; , = mo, ENO; mo Ai1ro$REPFAT; 2-128 ro Nl'H CHARACTER */ */ AP-223 PL/M- 51 a:MPILER /***** •••••• ********* STARr MAIN /* 363 1 364 365 2 2 INIT: 00 L=O 1 1 1 1 1 1 1 1 1 1 1 1 ***********.*****.*********/ ro 7Cm; DISP~$Rl\M(L)=20H; aID; /* 366 367 368 369 370 371 372 373 374 375 376 377 PRDG~ BmIN Erl FU'lTING J\SCII CODE FOR BlANK IN TIlE DISPLAY Rl\M; */ INITIALI ZE roINl'ERS, Rl\M BITS, El'C. */ ESC$SEQ=O; SCAN$INT=O; SERIAL$INT=O; FIFO=O; ClJRSER$COONl'=O; IU:=O; DATA$TEa!INAL$RFAD'i=1; Ta:tI=OSH; LINEO=180OH; RASl'ER=180OH; DISP~$Rl\M$roINTER=OOOOH; TRANSMIT$INT=l; $IF SWl 378 379 380 2 2 2 00 1=0 ro 7; 381 382 383 384 1 1 1 1 VALI~=O; LAST~(I)=OOH; aID; LAST$SlUfT$KRi=l; LAST$COO1'R:)L~=1; LAST$CAP$UXX=1; $ENDIF $IF SW2 lCVFLG=0; S'lIC=O; ErlFIN=O; KBDINT=O; ERlVR=O; $ENDIF /* INITIALIZE TIlE 8276 387 1 1 1 CCMWID$AIDRESS=OOH; PARAMEll'ER$AlDRESS=4Eli; PARI\MEll'ER$AlDRESS=58H; 388 1 PARAMEll'ER$AlDRESS=89H; 389 1 PARAMEll'ER$AlDRESS=0F9H; 385 386 */ RESEr TIlE 8276 */ NORW. lOiS, 80 CIIARl\Cl'ElVlUi */ 2 lUi CXlJNl'S PER VERrICAL RETRI\CE 25 lOiS PER FRl\ME */ /* LINE 9 IS TIlE UNDERLINE lOSITIOO 10 LIN&S PER lUi */ /* OFFSET LINE CXlUN1'ER, N:II-'l'RANSPARml' FIElD ATl'RIBl1l'E /* /* /* 2-129 Ap·223 PL/M-51 CXMPILER CRrIOCAL$LINE THEN DOl IF IOCAL$LINE=O THEN DOl ENSP=OI ES=OI ENDI /* PRJGRl\IoMABLE aJRSER BLINK /* IF IlXAL/LINE */ lIAS CHANGED srAIDS */ E£.SE CALL CHEII<$IWJD$RATEI LIC=IOCAL$LINEI END 1 $IFSWl DO WHILE OCAN$INT=O, IF SERIAL$INT=l THEN CALL DEX:IFHERI END 1 /* WAIT UNITL VERl'ICAL RE'l'RI\CE BEroRE /* SClINNIm THE KEl{BWlD*/ 2-130 */ AP-223 PL/M-51 mlPILER 427 428 1 1 429 430 1 1 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 2 3 3 3 4 4 4 3 4 4 4 3 4 4 5 5 5 5 4 5 5 5 5 4 455 456 457 5 5 5 458 459 460 6 6 6 461 462 463 464 465 466 467 468 7 7 7 7 8 8 8 8 469 470 471 472 473 474 475 476 477 478 479 8 7 6 5 5 5 5 5 5 CRl'ONl'IDLLER CALL READER; IF VALID$KEX =1 AND SIIME=1 AND (IASl'$SHIFl'~E'l=SHIFl'$KEX) AND (IASl'$CAP$LOCK=CAP$LOCK) AND (IASl'$O:lNTIVL$KEX=1 THEN 00; VALID$KEX=O; NEW$KE'l=0; END; ELSE 00; IF CCNl'HJL$KEX=0 TmN ASCII$KEX= (IDW$SCAN (K) .KE'{ (J» lIND 1m; ELSE 00; IF SHIFl'$KEX=O TmN ASCII$KEX=IDW$SCAN (K+OSH).KE'{ (J); ELSE 00; 4 3 ASCII$KEX=IDW$SCAN (K).KE'{ (J); IF (CAP$LOCK=O) lIND (ASCII$KEX>6OH) lIND (ASCII$KEX<7BII) THEN ASCII$KEX=ASCII$KEX-2OH; IF LIC=O THEN 00; IF ASCII$KEX=lBH THEN F.'lC$SEQ=1; ELSE F.'lC$SEQ=0; END; END; END; IASl'$SHIFl'$KEX =SHIFl'$KEX ; IASl'$CAP$LOCK=CAP$LOCK ; IASl'$CCNl'HJL$KE'l=CCNrIDL$KEX ; VALID$KEX=1; NEW$KE'l =1; END; END; ELSE 00; 480 481 482 483 484 4 4 4 3 2 VALID$KEX=O; NEW$KE'l =0; END; END; END; $ENDIF 2-131 AP-223 priM-51 CDlPILER CRl'CXNrH)LLER $E.Ja:T $IF SW2 . IF SERIAL$INT=1 THEN CALL OEI:IPHER, IF KBDINr =1 THEN 00, IF ERROR =0 THEN 00, ASCII~=LST~(1), .N&i$KE'{=1, CALL l\l1lO$REPFAT, KIlDINr=O, END; ERROR=O, KBDINr=O, END; $ENDIF 485 486 1 1 ooro SCANNER; END; KnlLE ~IOO: CXDE SIZE CCN9l'ANl' SIZE DIRECr VARIABLE SIZE INDIRECr VARIABLE SIZE BIT SIZE BIT-AOORESSABLE SIZE AllXILIARi VARIABLE SIZE MAXlMM Sl'l\£]( SIZE RmISl'ER-BANK (S) USED: 1056 LINES RFAD o PRJGRI\M ERROR(S) END OF PL/M-51 CDlPILATICl'I (Sl'ATIC+OIIERlAYAIILE) .. 08E6H 22780 .. 0080R 2IHI-00il 00Ht-00il . 108+0011 OIlHtOOH .. 000011 =OOOCH o l2BD 450100t160+ 00t00 120 2-132 00 00 00 00 AP·223 CrH PUSM PU5M MOV MOV MOY MOYX lr.tC 37 :iElB 311 1'01' POP POP H 4(1 U~Eu ,FILL ai76 Ruw BUFFEH ~EhBUF ,STICK SI;RIAL INFOHMATIOr.t INTO THE FIFU 1'81\ ,PUSH HEw USt:D B1 I'LM51 ACt; OOH HA:>1IiR,L1NI;O ,REINITIALIZI; NA~TER TO LINEO nAliT~Rt 1, L~r.tt.O+1 HO,.OlH leLR 81!76 INTEriRUPl rLAG A,ARII ,INCH CUHSER CUUNT R~GlSTEH COU~ r SCA~ ,FOR DEBOUNCt: HOuTINE UOH IPOP RIiGlSTEHS AC!; pSiI ~ErI 41 lie! III tlUH~1l1 .. U:iM .. us .. PSiI 4~ lib PU:. .. IiFL "US~ ",p" 411 15 CSEG 21 OU2~ IIUfFER IF CSfG Af( U2,5Hl 24 OU2J !lOe!D ATCOI3H~ ,N~EUEU 117 AC~ ACALL II~A IF~LL 1'01' 1'01' uP" ,POP Rf.GISIEHS 51 51! POt' AC~ I"S~ 5J 1'01" uPL riEII s~ '3':i .1 :.EJELT 2-133 ~216 RUW Ii II 110; 511 BuF~EH AP-223 M~S-51 LUC ,.,A\.RiJ AS~EI"ALE" OBJ LH\t. Ou5o! 30'lqull Ou5~ ~2'1q Ou57 0115'1 0051; 0115" OU&II Oubi! 0064 F u2UO 20"@o!8 61 Aq9q ~c 6~ (;298 ~OUo (;0':'0 COuo 0060 L2110 OUbA 111uO Ou&e eSOO Ou6E 1'8 006F tq OU7U 1;2,,7 OU7o! FE> oun b41BII2 007b U200 011711 u5vO OU7A u2UO OU7e UOIiO Ov7E UO~O 01/8u UOUO 01182 UOUI 0i/811 ,32 F F F F F F uOUO OOb3 uOb2 OOt.O uOuo OuAI o!2 :'OuH!.:E liEreBuFI JNd CL~ SEre liVER; JB 1'0liH MOV CL~ U 6'1 PUSH I'U:l1i PU:lH CLI( MOV AOU H MO~ 6~ 65 OU8~ COUO 0081 CO~O oue'l COll2 00811 COel3 008u eouo 0~8F 85UOll2 F 00'1.: 65110b3 F O~'I~ 78S0 00'17 (4eO Ou'l'l FO OU'lA A3 Ou'la UetA OuA~ S~ 6U ~OUI OU611 ou'lu Ou'lF OOAl OuA5 510 51 5a CIH ASM 6b 67 ,n lHAN:'MII Bll ~Ul S~l THE~ !.:HEC~ HE~EIV~ ,eLR T~A~8MIliSI0~ INIEIiRUPT FLAG lS~Tb TRA~S INl FOt( PLM51 :'TATUS CHECK 'Iel<,IiCdA\.K ,IF HI NOT SliT GuBACK uq~~,eVEIi "C;q~ 1 ~I\ 11,1 III I(1,8ul:l' Uqll~ P5~ At!.: 001< t.scSt.G A, UtR HL A,r II'C HO,A A, HI UE711 GiRU," A,t1taH,OvEHl MOV CLH MOV CJNE :lETB ~SC8r;g 7~ 7b \lVtRll INC FIfe 71 SETB Shlr.T 111 POP OOH 1'1 POP -'CC 8U POI' PU t>OP 0111 81' 82 60tlACKI HETI 83 811 alANKI t>USH PBrI .,~ PUSH ACe PU5~ 811 UPL PUSH IlPH 87 PUSH 0011 811 ~10V UPl,I.INEU+l 89 I)Pn,lINEO MOV 'Iv ft,OV HO,.SOH '11 'I': I~OTYE Tl MOV A,.2011 MOVX .ePTR,A 93 INC LlPTR q" UJNZ HO ,~UlYE'l 'l~ '1b '17 POP UOtl POP '16 LIP 11 POP '19 OPL POP ACC lOU POP 101 Ph IOo:! HET 103 +1 ~EJECT 71 7a 13 741 2-134 ,R~Au liSuF ,CLEAR RI a IT ,PUSH HEGIUIiRII US~O BY PLM51 , ,CLR EliC S~QUENCt. fLAG ,GEl StRIAl rlfO RAM STAHT LUCATION ,AI'IO FI~u HO~ fAI( INTO THE FIFU I'1E ARE ,PuT IT 1I1T0 RU ,CLR Bn 7 OF AC~ ,PUT DATA IN FIFO ,IF OATA IS NOT A ESC KEY THEN GO UV~R ,S~l EliC SEQUENCt. fLAG ,MOV FIF~ TO NtXT LOCATION ,SET StRIAL INT bIT FOW PLM51 5T4TUS CHECK ,PQP R~G18lEHS' ,PUSH HE. USED BY I'LM51 ',GET l1NEO INFU ,AND PUT IT INTO DHH , ,NUMbER OF CHAHA(;T~RS IN A lINE ,ASCII SPAcE CHAHACTER ,MOV Te DISPLAY HAM ,IriCR TO ~~XT UI~PI.AY HAM lOCATION ,IF ALI. 5011 lOCATIUNS ARE I';OT FILLEO ,GU DO MORI: IPUP REGISTEWS AP·223 M(;S-Sl "'A~RII LUC uBJ OUAa OUAA OUAI.: OUAt OUBII (;OuO 1.01::0 1.0d2 L1M. 10~ 10d 109 l1u 111 111: l1J 11~ 111 1111 1l'i 12U 121 12c 12J 1211 OuDCI OuOo! OClOli ouOo OUOII OIlOA OuOIl 00011. DuEl a liE It OIlEo ouE1 OOE'I OIlEA OuEII COUO L.OtO COll2 coa3 COUO C3 0500113 F lISCl082 F 43 140 141 Ll8~A 140t OvEu OuEf 0llF1 OuF3 OuF!i OVF1 LlOUO uOU UOui! \l01i0 UOuo o!2 1411 1~C!O ~ohTlI lib 1I0UO ",Od3 uOel2 uO':;O LlOUO o!2 FO PU~11 ,.S~ PU:;" ACL. PliO)" liPL. PU:;" uP" PU~H uOn MOV uPr., rC IN I MOV IlPL,,.C!~r+l URL uPI1,lfl0H MOV ~O,CIjR~Ek 1111 OuCS OUC7 OuC9 OUCII OUCu OuCF {811F A3 ~L1Nt.: 1011 lQ1 (;Oll~ OuBu /4o!O OUBf- rO OuCU A3 OUCl ~8 OUCo! a8~OF8 ~OuRL.E 1011 COuO 008~ 115UOb3 F OOB:! IISUOll2 F Ou811 113d310 F OuBd ABUO 16311310 CHTAS,', AS.:iE~BL.Eh 12~ 1211 121 12d FILL: 129 1311 131 13o! 13J 134 13~ 130 131 1311 13'1 CaNTi!l 14~ 141 1l1li 14'1 l!iu 151 ,Sot +I ,Gt::T kEijISTtR~ CURHE~T PUSH PUSH PUSH PUSH PUSH CLR t'h POP POP POP POI' POP UOh OPh LiPL. II'CI. PSII LUCAT10~ ;StT BiT 1~ ~OH hAM ADuRC:SS UECOul~G ,GtT CUR:;Ek ~OLUMN I~FO 10 Tt::LL HO~ ,FAR I~TO THt kO~ YOU ARE ,ASC1I S~A~E ChAKACT~R ,MOV TU UISPLAy HAM ,INCH TO ~t::XT UI~PLAY HAM LoCATlUJII EI~D O~ THt. LII~E ,PUIH HE&ISTtRS UltD BY PLM5l ACC UPL. IIPH UOh C LiPI1,L. MO~ MOW LlPL,L+l URL IIPh,UuH MOY HO,IIIFH INC LlPTR MOV A,.2uH MOVX .Of'TH,A INc LlP1R DJNZ HO,Cut.T2 HEr UStD BT PLMSl OlSPLAY HAM MO~ A,*2UH MOVX .1lr'TH,A tNC UPIR .IN' HO CJNE HO,.~OH,'O'~Tl ,IF NOT AT THE , CONTINIJE POP UOI1 ,PUP RtGlS1EHS POP UP., POP UPL 1'01' ACC POP PS~ HET ,GET BtGINNING Or L.INE RAM LOCATION ,CALCUL.ATEU ~y PLM~l ,lET BIT l~ FON UIIiPLAY RAM AOUREU UECOuE ,lET UP COUNTE" FON SOH LOCATIUNS ' ,GO PAST THE OF1" ,ASCII IPACE CHAHACTtR ,MUVE 10 DII~LAY RAM ,INCH TO NEXT uISPL.AY HAM LOCATION IIF ALL 19 LUCATIO~I HAVE NOT SEEN FILL.Eu ,THEN CO~TINuE ,PUP R~GUTEHS ll1j 140 ,PIISH iIIEJEcT 2-135 AP-223 "loS-51 LuC 1'1 AI,; 11", ASlIEpeLEh ",eJ u,.,~ 15J 15" 15:. ISb OuFo ~IDI! OuFA "5UO~3 OuFIJ 0500112 OIOv c.O 0104 1<3 010~ 010~ ~Oa31'3 j,O A3 to A3 to OIOb 0107 010& 0101j OIOA A3 OIOb to OIOC A3 010~ j,0 0101:. A3 0101' to 011u A3 0111 iO Oll~ 01U 011'1 011:a o lib 0117 01111 0119 OILA 01111 A3 to A3 H:~ 1605 16 .. 171 17~ 173 17 .. 17~ 1711 177 170' 183 18'1 01U A3 to 0124 A3 012~ 100 012b A3 0121 iO 012b A3 012'1 j,0 01U A3 01211 EO 012t; A~ 01211 to 012t. A3 012~ 1:.0 MO~X 1711 EO 18~ 1811 1117 18~ 189 l'1U II/I I 'I.:! 1'1l 111 .. 1 MOVX INC MOVX INC MOVX INC MQVX INC MOVX INC MOVX INC MOVX INC MOVX INC vP1R A, .. CPT" UP1R A, .. Cr'T~ IIP1R A, .. OP1" LlP1R A, .. 0i'1tc UP 1R A, .. 01'11( UPIR A, .. OPTIl UP1R A, .. OP1iC UPIR A3 ~2d .:2~ OIS~ A, .. Ct'1~ ",PIR A, .. O~l~ IIPlR .:21 to ,20 01511 015:; OISb 0157 015b 015'1 015A OIStl 015(, 015U A,~Ct'1K ~P1R A3 t.O A3 ~21 Ols~ 015~ IN(; .:\" 43 0111~ A,~C"1~ "D ';0 0150 0151 uF1R uFIR A, .. Ot'l" uP I R A, .. C~1 .. .:10 .:11 Olll~ 014t ~OuRI,;E cOb 014~ Olllij Olll!:> 01110 01111 01411 014'1 014A 014b OLlie 014U C~TASI'; t.0 A3 eO A3 t.0 A3 100 43 t.0 A3 t.o A3 t.0 A3 1:.0 A3 t.O A3 t.O A3 INC 23U ,,3~ ,3i: ,3:S e311 23~ <30 231 ii3b c39 cliV ;:41 cae eaJ 24'1 fOl4 A3 Ol/>~ t.0 0160 A3 INC MOVX INC MOVX INC e5~ MCVX ,51> ':51 .:5ij MOVX INC A,~Ot'l~ It>iC ,,5~ ,;0 vx ,,6~ l~C ,61 .:6c f HTY: IiPIR A,~Ct'l~ ~P1~ ';0 vx A,~Ol"lK lNI,; UPIR 2-137 AP·223 r.t~S·51 Lue ~,A~RU U~J ASbE~PL.Et< L.~~ CITI( uPTR A... Ol'll( UPIR 1I •• 01'1IC UPIR 1I, .. OI'TIC OPTR A, .. Ol'lH UPIR A... CPTH OP 1 R' 11 ... 01'11( upa ..... OI'TI( uP1R 1I,,,OI'T" A, .. C~TK 2-138 AP-223 "'1.8-'51 MALRu AS:.E,'Hl.t" Lue uBJ L1~t. 01Qt. A3 01QF t.O OlAv A3 01Al t.O OIAe! A3 o1IIj !!',I: ,2u J21 t.lbHTY ; J2~ '2J ,)2~ D~IFuC ~5112 01Ao OIAA tlQuOu7 01AI) 15U018 011:10 1500uO ~OuRLE Jill Jl'i OIA') i:.'5t13 OlA~ C"TAS~. F F ~2 I.Ht'.C,,: .)2::> 32b 327 J2u J2~ BU ~~ 1" ,-,0 vX A,~C~TK U~I: ~F ~,O VX Ih A,~C~lH 11\1- "Pl. MOV (;Jt;E A,UFI1 ~,OV A,L-PL ~,#l~."DuNt'. (;Ji;E A,~OIJOM,uC"E MO~ ~,Ov .ont.R,#18n ,U~Tt.Ii+1 ,#yOh riET 331 u5u3uO 01B1 b5112uO OlBA i!2 01B~ F F J3~ J3~ 3!~ 33~ 01BII OIBC OIBi:. OlCu 01Cc: OlC .. OICb (;3 t'.5112 HI c!QQF HIS F'5u2 33~ ~OOF JQU u'5113 1101)8 1l0NE: Bo kAtlTt.R,Dt'H "A~Ti:Ii+l,Di'L IlMADNEI CLR MOV ADLl MOV JNC 1NC :iJMP ~41 J4e! 34,S jD" j"::> MO~ MOV IiET C A,LlFI. A,IIHD I)PL,A 110 GI;; T Tu L~tCI\ lIN THE DISFLAY Mt.MURY uPH CH:CII tNLI 2-139 IADU 7'1 Tu tlUFFt.R ~EXT PUINT~R 018~I.AY LiNE AP·223 "I,;S~51 I~A .. Ru AS:.E~BLf Ct!' OUAIIM A OU3~M A 01AJM aI/Bull OuEll' A A A PuB A PUB A HT EXT OuFIlM OuFAM A A 048111'1 A A 01SOIIl OU!31l OU8ell ,OU1M A A A 016~M A !lOCUM 015111 oueOiM A PuB OUHM OU5'lM OuHI! A A A OUOl/H A OU"9M A OUSc!M A EXT ExT A A ExT EXT ExT ExT OleUM 017'lM 011:iH 013uH Ol"~H Ou2:>H R~GlSTEIt IjAI\IKlSJ UStO: u ASS~"ljLY ~O~PLEre, he e"ROR~ EXT EXT ExT A A A A A A EAT ~OUNIJ 2-140 ~ S AP-223 K~Ybfl .2.1 I~I~-lI '~S-S1 ~A~R~ C~J~Cl MOUULE PLALE~ A~S~'DL~R I~VuK~~ e,: LuC uBJ l1~t A5~E~BLEK 1~ :~l;K~Y~D.ODJ :Fl:~EIBU.~N~ ASPS1 ~OURL.E ~ j ~ ~ b 1 d 9 IV II Ie I~ Iq 15 1& II Ib ,****************************************************t •• * •• i****tt- •• .... **_**_._.,._._._ ... _.... __ ****_. __ •• __ *_* __ .*_ .. ; •• *- , ;._.. ~OrTnA~E ; ••• t FuR RtAUI~G K~YIIO"Ru AN _._.*._._*._ _____ ...• __ ... - i ••••• UNuE~OUEu t.t_ * ••• *t._ , ... *----_._-_.* .. _--.--._ .. **_._ .. _.*-** ••••••• _._._---*.* .... _*.-._ . _-. ,i'-**-.*-_.-._.'*--_.' .. _--*._ ... ------_.-._-_ .. -... *. tt_._* ___ •• __ _ , t •••• 1 1 fHlS THIS CU~lAl~b lHt P"CG~A~ ~uSI bOfTwAkE NtEUEu '0 S~A~ AN UNDtCuO~O KtY!lOARu LI~~EU TO THE ~Arh PRUGkAMS Tu FUNCTION ~E 1'1 2U 21 M~~URY AOURcS~ U 23 MA~ FOH KEA01NG rCH KEY ~OARU ~EY !lOARD (UerhG ~UV~) 10FFH TO 17FFH 2~ 2~ 2& 27 I'UbLlC REAL/Ell ~XTRh (LSTKfYJ tXTRN lilT (KtYU,~AME) u_,_ 211 29 3V !I , ••• *••• *.***** ••••••••••• **** •• ******.*********.*********************** !~ 1* 3e 341 3~ !b +1 I i* * ·R~"CEH·HOUTINE.· J ~*********.***********ft******************************* **_ •• ~EJE~T 2-141 * * * *._.**_. •• **** AP-223 ~~5-51 LIlC MAI..RU AS~H~I.E" L!~t lJ8J K~Y",O ~OuRI.E ! I !~ .-.- 3~ ~NUEI..OuEu_KEYBuA"C 8~G~ENT U~D~CuO~O_K~YUCAR~ CuD~ "StG U\I QI 4" OuOU COuO U.s rcEADtRI I'USH OuO~ ~O~O 4~ OuOu OVOb OUOIl ,0vOA ovOC OuOt 0010 COll2 4:1 4" 1..01l! cava caul COv2 COv3 9010fF O,v3~ 003~ Ov40 Ou4i! OU4Q Ou40 004ij OuliA Ou411 UII 4'1 Ou4~ 11005 v501 1i50i!ID us v5113 URtA b'lllSII4 F u2110 Ci!OO F 1)003 CiOUe! U001 IJOVO 1)0113 1.10112 1)0100 uOuo a C2uO 50 51 50! 53 54 MOV '5b 51 511 MOIlEI 59 60 &1 6" 63 64 6~ 6b 61 lEHOI 611 69 I;QUALI 7U 71 U. 7.5 711 7::; DACK; 1b 71 711 79 8u e1 tlr!' 8::0 F PUSH 5~ 8J 84 ,.." OU4t IIOU£ ~U:;~ PUS .. I'US .. PUS .. I'US .. 41 001'3 l'IuO F OUI~ 1800 0017 '/llve Oul'l L2UO F F Oull! D2\10 ovlll b&U2 Oull' 104 Ov20 93 0021 F4 002~ bOv5 OU2~ tl5vU4 OU21 OU29 OU2D QU2t 002F ov31 0113.3 OU36 011311 Ou3A PUll!; SJMP INC CJNE INC INC LlJNZ CJNE SETB Cll< POP POP PDP PDP PDP POP PDP POP kET NTSAME; 1'10'1 8" 81 80 89 9U 91 MOV MOV MOV ClR SETB MOv ClH MOVC CPL JZ CJNE Clk SJMP t'S~ ACI.. IiFL. UPh UOn Vlh v21i V3H uPH,HOfFH KI,.OOI1 itO, ilLS IKI'.Y 1;3,110811 KEYO ;PUSH "Eb USED BY ~LM51 uPTR TU KEY80ARD , AIlDWESS ,CL.R ltRO COUNTEN ,GET KEYIiOARu HAM ~OlNTEH ,INITIAL1Zt LOUP CUUNTfR ,INITtAlIZt PlM51 STATUS 81TS ,INITIALIZ~ SAI',E 0211,GiRO A A,,,AtDPTH ,MUV LAST ~EYBUAKO SCAN 10 OeH ,SCAN KEYBUAHO A ,INVERT ,IF SCAN ~AS lERU ~O INCREMENT lERU COUNTER lEHD A,u2H,NTUME ,CUMPAHE ~ITH LA5T SCAN IF NOT THE SA~E ,THEN ClR 5AME B1T AND ~HITE NE~ INFURMATIO~ ,TU HA~ IIF EQUAL. JMP uVER INCH OF ZERU !:OuNIEH i:GLJAL. lINCH ZERO CUUNTtR 01H A,1I2H,rHUME ,STEP TO ~tXT 5CAN RAM lOCATION kO INtXT KEYBOAHD lUOREua liP" IIF LOOP COUNTER NUT 0, 5CAN A~AIN H3,IIURt kl,.OSH,bACK ,CHECK TO aEt 1F ALL 8 SCANS WHERE 0 ,IF YE3 5E1 KEYO BIT liE YO II Ar',f UlH ,POP RtGlSTEHS v211 01H 0011 UPIi OPL Ace t'S~ ,IF ~CAN ~Ai NUT THE' SAME ,SCAN INtO I~TU NAM ; CLR BAh ~ IT ,GU UD "UR~ GRO,A lj~I"E ttUAL. tNU 2-142 TH~N PUT NE~ AP-223 YP E A(.C. BAC" • Dt'H •• Of'L.. EWUAL.. K~Yv • • • • • • • L:iTI\EY IIURt;. • N1SAM~ P~\\ •• ••• Ilf.ALiEk SAMt;. • U~D~C~Dt;.D_KtY~OARU Z~RU • • • • • • • R~GlSTEH ~A~K(5l A~Sl~~L.Y COMPLETE, o C o AIJC" AuCk AUC" o AUCH C AI-Cil e AUCH o AIJCH C AUOH C AUC" o ALiC" C AUCk e AUC" C St;.G CAliOn U5~CI ~C V A L. U E OuE~H Ou2EH A R A A fI Ol/lUH R Ou3AH Ou8.1H Ou8~~ A T T RIB UTE 5 EXT EXT OUlltiH Ol/DOH OuOUH Ol/SUH OU29H St.G=L~OtCuDt.D_Kt.Y~OARLi StG=L~DtCUD~D_KEYDOAR~ R A R PUB EXT R StG=LNDtCUDtD_KEY~OARU r;tL.=LNII StG;L~Dt.CUDEO_KtYpOAR~ u E"RUR~ fOuNu ·2-143 AP·223 vc.1 l~r~·,r ~~S·51 ~A~~~ ~S~E~eLEK O~JtCT ~OUULE PL-~EU ,~ IfIIOtCUOt.uSJ A'St~bLtR r~VuKtD ~'I AS~51 ;FlluECOUE.SkC LUC UeJ 1.1t.t .OlJR~E ~ ~ . ~ b I ~ 'I 10 *.*.-*.,_.-.,.,, ____ .. ,._*,t**"'" *.-.a.",_.**-_ .. -.*-.. _--*-._.---.- .. __ .. -----**"'t'*' i,*-*._a_*_** •• *_ •• *_ .. _.... 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IU~ELI 3J I'US~ t'l!S~ uF ... 34 MCV CLI< Move MOV .lETS Mall MOV 1'01' 1'01' POP 1'01' riElI 3~ 10 4 30 '13 1-5110 F U2110 15<1CfF ISoArF UOIoO F 31 311 !9 4U 41 ~~ uOCl3 ~~ uOTIIEY C AUOh 0 HOI< 0 A~Dh P A~C" 0 A~OI< P:'.I'< • 0 THO. AIiOh 0 AL.OI< ·· .... · n.o. · · OI'L. 0 RI;GU rEh tlANKlS) A:.SI;~!dL y COI~PLE A~C" US~DI IE. lie AL U E OUEUH OV2oJH OvOUH Ou6jH OV6.!H A V A T R~L;Lld fI PUB A EXT EAT OUaUH oue .. H Ou6AH V EkRURS faUNu T R I A A B U T E 5 I 5"G;DtC~D~O_KtYDaARu AP·223 O~TACM I~I~·lI ObJ~CI ~~S·51 M1Ulll.E A~S~~uL~R Lue uBJ ~A~w~ PL~~EIJ I~VuKtD HI: ~S~t~HLEk .11\ V2.1 H);OtTACtt.UAJ AS,S1 :FI:uEIA~H.S~C Ll!\t 1 C oS ,i.**.-.-•.. .. *.-----..._.._.*.-... -.-.... -_ ...._--.--_._-_ _-.-.---._ ...... ... -._._.-.-----_._.-._---.. ---. ,fI**. ., ~ .... , b I 0 ~C~T~AKE FuR A StRIAL OR ~EYBIJAI 31 311 ]Ii IIU IIAUD III 110 llii 1511 STAHT BLT Dt:;T!:CT UirAo!H OFQOIlH M':SliAliE DHt.C r ODF4l:1H OEIIOIIH ~J 441 II!'! lib OUOU OVF4I OuOu OuEIl lUI 119 511 51 1'1 t:;QU Ulu "Qu EQu STARTO STARTl MES8AGtO MESSAGtl 117 iiEJECT 2-148 UOIiH IIF"H UOUH UEIIH ,LOw BYT!: FON 150 IIAUD ,HIGH dV,TE FUR 150 BAUD ,LUW BYT, FDN 15u IIAuD ,HIGH uY.lE FOR 150 BAUD ~~5-51 lliC ~A~RII Dt HCn AS~E'B~E~ l.L ~ t _UBJ bOURLE 5, SJ 5~ ,**-******.*.**. __ ._ •••• _ •• _******_*_**_ •• *.*_.* •• * __ .***_.** •• * 51>;* 51 ;* _.a __ •__ ._** ___ * * * • S!:I ; 5ti ;***********************************************_*****'a**,.a*"*"'t.tt*,,_.,. 59 "Co;lACH" IftltHkU~T RUU1I~E FUR Ot:.TACHAdlt ~EYBUA~D~ 6U ,~I ~c 6~ uEIALHABLE_KtYIIOARu ~E~~t:.NI COllE HStG DETACHAlIlt~KEYBIIA~D 64 OuOU OuOe OU04 OuOl OUOA L;OuO cOuOl! eOll44A 1;2uO oooe 15tjCf4 I}' t: co 6~ !:0o;0 61> F 61 F 6b 6<; OOOF 7511AuO OUli:: t589 001'1 7U 1'10 V 71 MOV 7c ~2t:.i! OUl& F5b'l 74 75 76 ~OIlOlO eOIl4:S11 L1i!UO 7500110 7511Ct8 7511AUO F 77 7& F F , VALIIII 79 eu B1 Be S;S 01/211 11018 SII 01/2L1 15C1Ct8 S5 eb 01/31/ 7511AOO Ou3;S cOUOlll 0113& t5uO 00311 1021:14 Ou3A 13 OU311 f5uO Ou3u :.Ou6 OU3f li21/0 OUII1,C2t7 OUll3 f5UO Oull5 1100;0 OU47 \JOuO OUII'I 32 ~.OV 73 oull1 bOeB OUIA OUILI OIli!U OU2e 0025 Ou211 UEIALHI PUSH I'U51< JB JB liETB F F Sf 811 89 'IV F ell F 'Ie qJ F 97 'Ill fII~lI HC vFLG, IIAUD !M'LI,HSl "CvF~G HO,IISIAHTl TlU,1IS 'AHTU A,Hue :PUSH kEfi15TtR:. ,UStO BY I'LM51 ,IF HEI:Elllt flAG S~T G~T NtXT IlIT :11' TO IS A 1 THtN NUT A STAHT BIT ,IF 10 18 U THtN 11 A IiTART bIT ISET TIMER TU IN1EkRUPT IN THE "IOOlt UF STAHT BIT UEe~ T~I.iD,A 18tT 1'11\1 IGU tlACK TU PRUGt4u5 Ou4u u2uO Ou4f u20000 F F q'j lOU 101 AOe 10j OuS~ ui!oO 00S4 005b Ou50 OuSA Ou5e OuSt. Ou6u (;2uO 1:2uo C2uO I;SIlQ .,21:2 "Soq 151:1CtF Ooe.:s 15dAf'F 006& 1:I0u" ... ~ C11 0 F F F F DI:TACH :;OUR(;E I :iTuP; JMP 10~ I I;RI SETS t.N" SETB ell< ClH ell( MOv :lEIB MOv ~~I'l 1 ,t.R" IIBu II,T 1<51 t~"C" kCvFLG .IIF NOT 1 IHI:N NuT A VALID STOP ;Tt.LL PL~ A ~YrE I~ HEADY lAND GO ~A~K TU ~A1N PIEU •• "t:.S:'At;El •• ~H~IT. p~~ • tI STAHTU • • STAHTI •• Nl:I'B STOI' • • I: AOUR SYNC. tI AOUR II AOOR U AOuR U ACUR U AOUR I: ADOR Tu • • • THO • TI.O • • TMOll. VALID c;X\ UOt.8H VOc!OH UOUOIi H UO!i.4H UOOOH UOF4H 004AH &Eb=UE\AC~ABI.E_KtYbOARil tXT t:XT A A H A ACUR NL~B A I \ " I tI U T t:. :, t ,Xl R A A H tXl OOtlOH." A uoseH A U08AH U089H UOIAH A A R RfGIS1EH bANK(S) UStOl U A5St~IlLY ~OMPLETE, NO EKROR~ FOUNU 2-151 AP-223 APPENDIX B REFERENCES 1. John Murray and George Alexy, CRT Terminal Design Using The Intel 8275 and 8279, Intel Application Note AP-32, Noy., 1977. 2. John Katausky, A Low Cost CRT Terminal Using The 8275, Intel Application Note AP-62, Noy., 1979. 2-152 APPLICATION BRIEF AS-38 September 1989 Interfacing the 82786 Graphics Coprocessor to the 8051 RICK SCHUE REGIONAL APPLICATIONS SPECIALIST INDIANAPOLIS, INDIANA @ Intel Corporation, 1989 Order Number: 270528-002 2-153 AB-3S Interfacing the 82786 to the 8051 presents some interesting challenges, but can be accomplished with a little additional logic and software. Since the 82786 looks like a DRAM controller to the host CPU, wait states are often required when accessing the coprocessor. Since wait states are not supported by the 8051, latching transceivers and dummy read and write cycles are used to communicate with the 82786. Byte swapping is also required in the external logic to allow the 8 bit 8051 to read an~ write the 16 bit graphics memory supported by the 82786. This byte swapping is accomplished with the latching transceivers as well. All of the control logic is implemented in an Intel 5C060 EPLD, allowing the entire interface to fit into three 24 pin DIPs. HARDWARE Figure I shows the interface between the 8051 bus and the 82786. Figure 2 shows a typical 8051 CPU design needed to complete the circuit. In this design the 82786 is mapped into an 8K byte window in 8051 data memory space. ~he upper address bits are used as a "page select" and are provided by 1/0 pins on the 8051. The 5C060 EPLD contains the control logic for the transceivers and address decoding for the 82786. An equivalent circuit for the EPLD is shown in Figure 3; the ".ADF" file is shown in Figure 4. The 82786 data memory is mapped into one 8K block (AOOOHBFFEH), the 82786 registers are mapped into another (8000H-807EH), and the transceivers are mapped into a third block of memory (COOOH-COOIH). OPERATION Operation. of the interface is as follows. For reading the graphics memory, the 8051 sets the upper address bits (PORT 1.0-1.3) and then performs a dummy read operation to the desired location in graphics memory (AOOOH thru BFFEH). The dummy read cycle pro- vides the address and RD/WR information to the 82786, which runs a cycle and deposits the 16 bit result into the latching transceivers at the end of the read cycle, as indicated by SEN. This event clears the BUSY flip flop in the EPLD. When the BUSY signal goes inactive, the 8051 reads the low byte from the latching transceiver at address COOOH and the high byte free address COOIH. For write cycles, the 8051 writes the low byte of the word into the latch at address COOOH and the high byte into address COOIH. Next the upper address bits are set with PORTl and a dummy write cycle is performed in graphics memory at the desired address (AOOOHBFFEH). Like in the read example, the 82786 runs a memory cycle at this point, enabling the outputs of the latching transceivers at the proper time in the write cycle, as indicated by SEN going active. Accessing the registers inside the 82786 is done in exactly the same fashion, except that the 82786 is addressed in locations 8000H through 807EH. This causes the EPLD to drive the MIlO pin low during these cycles. DESIGN NOTES 74F543's are used for the latching transceivers in this design, although 74HCT646's could be used to reduce the total power consumption. Some changes to the EPLD would be required in this case. The interface assumes that all memory accesses to the 82786 are word references; accordingly, BHE is grounded at the 82786. All addresses generated by the 8051 must be even byte addresses, the only byte operations allowed are the reads and writes to the latching transceivers. The design shown here incorporates hardware workarounds for the earlier "C-step" 82786; the current "D-step" part will work in the design as well. Additional information regarding the 82786 can be found in the "82786 Graphics Coprocessor User's Manual", Intel publication number 231933. 2-154 inter AB-38 , .- . I g ~ ~ I!S IOCI~ ~ "" . .. -\ .. - , v,vl .\-\" " " - - 0- ""'1')"'1/') +1- =: ~ ~ : 2 '" -.. r 0 - t-;< ~i~r--111 "li ~ ij Q °IB - iiil e .'~HEaHq ~H~H~P~· r-- t--;c: 'l ~ ft ~W~Slil~ ~ Ii; ~ >'d~ :c :c i II . lll~ HH 55 ~F· z: ::I Z :Ii: >'a >'a~; ~ ~~;;S;;;S;;'=~~~~~~~.~~d~~ Ii i ~ il ~ ~il ~ilii88§Seii~1i~ tl1tt, Hhiiid~~ ; ; a; Ci"'~I i:i:C II ~ ::I .. ::! f;2 N 2 =~ ~ too'ii'Taij"'. ~ ~~~l:;!~c=J1 II ~5uunHU~ ~ B!8~SS.8 ::; i i <; 6 i: i: i:O ~I~rll -l~l =-"=.~~ ~ ~= j "t t t t ~ ....-- -~~,,~. ~ ~ B o ... =; -"·"~i~rll ~; ~;;:i,\l! ; $ g~~;~;~~.~ee ~ ~~II ~l"f" .".... =1:L,1 , § ~ ~ ~~S~d~; ;l :! =- " - >'d 1- ~!~'-ill o • ~ ~. ~~~~~:2~~~~~~:l~<~ UU'" ~ ~ ii ,, :c:c:c Figure 1 2-155 ~ ; II I •H;jg "~l·A ~ ::: N UB ,.oa~ ~l~l~lHI~ i H ~~~~ ~~ "~l :1:1:1:1:1:1:lr~~1 3~~~~;~~.~e~ I~~ t'oo'7i"""'i"ia" LtIO"i"""i"iO' ~ ~ ~3~=;;;~·S,\l! o ~ ~ too'iT"7i'iO"'\ zoo"i""'7io'" ~~~ii~&:!t8 ~ T""'iQ""\ ~I·I·I·I =1 ~I ~I ~1·rr~11 i """" i i :i :ii<; :; CD 'Li"'7a""" tDa'i""""'ii" ~ ~~~l:l~:i~>H M f-r "" " "ii""'iO"o tOO 100' ~ -, II 'OG "r TITITr Ttr~11 "J ~ ~=:!l:2~:C!ig~ = . ~~~~~~.~,\I "" : :O:~::;::.1D:il>H~ zoo TSi" ~ ~ • .~ ?oa~ LOOTt'(j""\ ~ "" -, ... '" ... 2: "1"1" • .. " -TeT ~=:;!l:;!~c~>H .- . II ~ ~ *. ~ ~ 7""'i(j"'"\ [oa~ "1 ~ITITIT ~1·rr~11 ~~;=~~~~i! u ~I vv' ~oa II ~ B88~SS.8 ( P1.7 ~ P1.6 ; P 1.5 Pl.4 1.3 1-+-.....-tXTAL2 PP1.1 P1.2 !f- P1.0 RESET 9 PORTl.3} ___ PORT1.2 BANK SELECT "'" --'"" PORTl.l PORTl.O ' . J " o ...L..+5 10ul 'l5'Y T+ * RESET :~ ~~ RO- WR- PSEN A15 A14 26 A13 A12 2! All 3 A!g AS I}>~ SOC31 +h ~I ;,~~ ... ... ... ...o _ <> A12 21 All 4!~O ~025 2N79~5K .... Il'TxO AS 10 A12 All Al0 A9 AS ~ m I w CO ~=::gA6 IA5 ~ ~=::gA4 IA3 ~=::gA2 IAl ::l !~ t::::--_:>AO Vee +5 .... § NCj1.. 1---_:>A7 ~A2'" ~ 0 !~O AS 1 5K ~ A12 All 07 9 ~ A7 06 5 5 A6 .., 05 AS ... ::;04 6A4~ t;03 6 7 A3.... I\) - A15 --'"" A14 A13 91 ~UU ~. ~. tJ ...... c ~ ; ~ II I CE2 Vss 1.B:K AS-232 +5 19 07 - 2 5K 1------....wlr-f""1 lN4148 07 06 05 04 g~ 18 06 17 05 16 04 :~ 03 12 ~ 1 00 g~ 00 I" _ 06 05 04 03 02 01 DO BUSY 270528-2 intJ AB-38 786esn rdn wrn 015 014 786rdn 786rdn 10--+---. hlbonkn 013n NANDJO----+_t-1~_OI ~o--~-+_t~~i-..; rdn oehn 00 lehn oeln leln t----t \OS FQ .....t---iR r--.....--t ~)---i... ·~IJO_ _ _ _ _ _o_e_w_n_ _-{ sen @D-elk S 786rdwr L -_ _ ~~ >-':"::'::;"::'::':"-'--1 Q~_b_u~sY~_ _ _ _ _ _ _ _ _ _ _ _~BUSYl SON F R __ ~ ~ 270528-3 Figure 3. 8051182786 Control EPLD (5C060-55) Equivalent Circuit 2-157 AB-38 INTEL August 11, 1987 1-003 o 5C060 8051/82786 Control Logie for 8051 Demo .Board 786 I/O 8000H-807FH 786 Memory AOOOH-BFFFH Registers COOOH,COOIH OPTIONS: TURBO=ON PART: 5C060 INPUTS: A15@23,A14@14,A13@11,AO@2,RD/@10,WR/@9,SEN@8,CKK OUTPUTS: 786CS/@15,786RD/16,OEH/@17,LEH/@18,OEL/@19,LEL/@20, LEW/@21,OEW/@22,READ@4,BUSY@3 NETWORK: a15 INP (A15) a14 INP (A14) a13 INP (A13) aO INP (AO) rdn INP (RDIl wrn INP (WRIl sen INP (SEN) elk INP (CLK) a14n NOT (a14) a13n NOT (a13) aOn NOT (aO) . 786esn NAND (a15,a14n) 786CS/ CONF (786esn,VCC) 786rdn = OR (786esn,rdn) 786RD/ CONF (786rdn,VCC) hibankn NAND (a15,a14,a13n,aO) 10ba.nkn NAND (a15,a14,a13n,aOn) oehn OR (hiba.nkn,rdn) . OEH/ CONF (oeh.n,VCC) lehn OR (hiba.nk.n,wrn) LEH/ CONF (leh.n,VCC) oeln OR (lobankn,rdn) OEL/ CONF (oeln,VCC) leln OR (lobankn,wrn) LEL/ CONF (leln,VCC) oewn NAND (sen,write) OEW/ =' CONF (oewn,VCC) lew = AND (sen, read) qO NORF (lew,elk,GND,GND) ql NORF (qO,elk,GND,GND) q2 NORF (ql,elk,GND,GND) q2n NOT (q2) lewn NAND (ql,q2n) LEW/ CONF (lewn,VCC) 786wr NOR (786esn,wrn) 786rd NOT (786rdn) READ, read SOSF (786rd,elk,786wr,GND,GND,VCC) wr.ite NOT (read) 786rdwr OR (786rd,786wr) BUSY SONF (786rdwr,elk,sen,GND,GND,VCC) END$ = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = Figure 4. 2-158 intJ APPLICATION BRIEF AB-39 December 1987 Interfacing the Densitron LCD to the 8051 RICK SCHUE REGIONAL APPLICATIONS SPECIALIST INDIANAPOLIS, INDIANA @ Intel Corporation, 1987 Order Number: 270529-001 2-159 AB-39 INTRODUCTION This application note details the interface between an 80C31 and a Densitron two row by 24 character LM23A2C24CBW display. This combination provides a very flexible display foot format (2x24) and a cost effective, low power consumption microcontroller suitable for many industrial control and monitoring functions. Although this applications brief concentrates on the 80C31, the same software and hardware techniques are equally valid on other members of the 80S 1 family, including the 8031, 87S1, and the 8044. HARDWARE DESIGN The LCD is mapped into external'data memory, and looks to the 80C31 just like ordinary RAM. The register select (RS) and the read/write (R/W) pins are connected to the low order address lines AO and AI. Connecting the R/W pin to an address line is a little unorthodox, but since the R/W line has the same set-up time requirements as the RS line, treating the R/W pin as an address kept this pin from causing any timing problems. The enable (E) pin of the LCD is used to select the device, and is driven by the logical OR of the 80C31 's RD and WR signals AND'ed with the MSB of the address bus. This maps the LCD into the upper half of the 64 KB external data space. If this seems a little wasteful, feel free to use a more elaborate address decoding scheme. With the address decoding shown in the example, the LCD is mapped as follows: Address Function Read/Write? 8000H 8001H 8002H 8003H 8004H Write Command to LCD Write Data to LCD Read Status from LCD Read Data from LCD Write Only Write Only Read Only Read Only to No Access Undefined results may occur if the software attempts to read address 8000H or 8oo1H, or write to address 8oo2H or 8003H. TIMING REQUIREMENTS The timing requirements of the Densitron LCD are a little slow for a full speed 80C3I. The critical timing parameters are the enable pulse width (PW E) of 4S0 ns, and the data delay time during read cycles (tDDR) of 320 ns. The 8OC31 is available at clock speeds up to 16 MHz, but at this speed these parameters are violated. Since the 80C31 lacks a READY pin, the only way to satisfy the LCD timing requirements is to slow the clock down to 10 MHz or lower. A convenient crystal frequency is 7.3728 MHz since it allows all standard baud rates to be generated with the internal timers. SOFTWARE The code consists of a main module and a set of utility procedures that talk directly to the LCD. This way the application code does not have to be concerned with where the LCD is mapped, 'or the exact bit patterns needed to control it. The mainline consists of a call to initialize the LCD, and then it writes a message to the screen, waits, and then erases it. It repeats this indefinitely. The utility procedures include functions to initialize the display, send data and ads to the LCD, home the cursor, clear the display, set the cursor to a given row and column, turn thl? cursor on and off, and print a string of characters to the display. Not all the functions are used in the software example. REFERENCES INTEL Embedded Controller Handbook, 210918 INTEL PL/M-Sl User's Guide, 121966 DENSITRON Catalog LCDMD-C FFFFH 2-160 t +5 Vee GND I\) , ..... (j) ..... ~ ... !! .. . (.) CD C l> N II) :'" +5 ~ 5- 116 6 15 9 ._ 4 o l1J '" CD ~ A7 A6 66 AS (.0) N ~ ~ -12 7 A4 8 A3 9 A2 ~Al -AO +5 27C64 6264LP (OPTIONAL) 270529-1 inter Main_module: AB·39 DO: Delay: PROCEDURE (count) EXTERNAL: DECLARE count WORD: END Delay: Initialize_LCD: PROCEDURE EXTERNAL: END Initialize_LCD: Clear display: PROCEDURE EXTERNAL: END Clear_display: LCD_print: PROCEDURE EXTERNAL: END LCD_print: ' DECLARE LCD_buffer (48) BYTE sign_on_message (*) BYTE ('INTEL 8051 DRIVES LCD - , '2 ROWS BY 24 CHARACTERS '). i BYTE: PUBLIC. CONSTANT /* This is the start of the program */' /* Initialize the LCD */ CALL Initialize_LCD: CALL Clear_display: /* Now enter an endless,loop to display the message */ DO WHILE 1: /* Copy the message to the buffer */ DO i = 0 to 47: LCD_buffer(i) sign_on_message (i) : END: = /* Now print out the buffer to the LCD */ CALL LCD_print: /* wait a while */ CALL Delay(2000) ; /* now clear the screen */ CALL Clear_display: ' END: /* of DO WHI~E */ END Main_module: Main Module 2-162 inter AB-39 LCD_IO_MODULE: DO; DECLARE LCD_buffer (48) LCD_command LCD_data LCD_status LCD_busy i BYTE EXTERNAL, BYTE AT (08000H) AUXILIARY, BYTE AT (08001H) AUXILIARY, BYTE AT (08002H) AUXILIARY, LITERALLY'lOOO$OOOOB', BYTE; Delay: PROCEDURE (msec) PUBLIC; /* This procedure causes a delay of n msec */ DECLARE msec i IF'msec> 0 THEN DO; DO i 0 to msec - 1; CALL Time(5) ; END; = WORD, WORD; /* .2 msec delay */ END Delay; LCD_out: PROCEDURE (char) PUBLIC; DECLARE char BYTE; /* wait for LCD to indicate NOT busy */ DO WHILE (LCD_status AND LCD_busy) < > 0; END; /* nOW send the data to the LCD */ LCD_data char; = END LCD out; LCD Driver Module 2-163 inter AB·39 LCD_command_out: PROCEDURE (char) PUBLIC; DECLARE char BYTE; /* wait for LCD to indicate NOT busy */ DO WHILE (LCD_status AND LCD_busy) < > 0; END; /* now send the command to the LCD */ LCD_command char; = Home_cursor: PROCEDURE PUBLIC; CALL LCD_command_out(OOOO$OOlOB) ; END Home_cursor; Clear_display: PROCEDURE PUBLIC; CALL LCD_command_out (OOOO$OOOlB); END Clear_display; Set_cursor: PROCEDURE (position) PUBLIC; DECLARE position BYTE; = IF position> 47 THEN position 47; IF position < 24 THEN CALL LCD_commapd_out(080H + position) ; ELSE CALL LCD_command_out(OCOH + (position - 24)); END Set_cursor; C~rsor_on: CALL PROCEDURE PUBLIC; LCD~command_out(OOOO$llllB) ; END Cursor_on; Cursor_off: PROCEDURE PUBLIC; CALL LCD_command_out(OOOO$llOOB); END Cursor_off; LCD Driver Module (Continued) .2-164 inter AB·39 LCD_print: PROCEDURE PUBLIC; /* This procedure copies the contents of the LCD_buffer to the display */ CALL SeLcursor(O) ; DO i 0 to 23; CALL LCD_out(LCD_buffer(i}); END; CALL Set_cursor(24) ; DO i 24 to 47; CALL LCD_out(LCD_buffer(i)); END; = = END LCD_print; Initialize_LCD: PROCEDURE PUBLIC; CALL CALL CALL CALL CALL CALL CALL CALL Delay(lOO) ; LCD_command_out(38H) ; LCD_command_out(38H) ; LCD_command_out(06H) ; Clear_display; Home_cursor; Cursor_off; Set_cursor(O} ; /* Function Set */ /* entry mode set */ END Initialize_LCD; LCD Driver Module (Continued) 2-165 APPLICATION BRIEF AB-40 December 1987 32-Bit. Math Routines for the 8051 RICK SCHUE REGIONAL APPLICATIONS SPECIALIST INDIANAPOLIS, INDIANA Order Number: 270530-001 ® Intel Corporation, 1987 2~166 inter AB-40 Here are some easy to use 16- and 32-bit math routines that take the pain out of calculations such as PID loops, AID calibration, linearization calculations and anything else that requires 32-bit accuracy. , The package is written to interface with PL/M-51. Parameters are passed as 16-bit words to the routines, which perform operations on a 32-bit "accumulator" resident in memory. The foJlowing functions are performed: Load_16 (word_param) Loads a 16-bit -RD into the low half of the 32-bit "accumulator", zeros upper 16 bits of accumulator. Load_32 (word_hi,word_lo) Loads word_hi into upper 16 bits of accumulator, word lo_into Lower 16 bits. Low_16 Returns the lower 16 bits of the accumulator, bits 0 through 15. Sub_16 (word_param) Similar to Add_16 but for subtraction. Add_32 (word_hi,word_lo) Forms a 32-bit value for word_hi and word_lo and adds it to the accumulator. Sub_32 (word_hi,word_lo) Similar to Add_32 but for subtraction. APPLICATION Typical applications have 16-bit "input" values and produce 16-bit "output" values, but require 32-bit values for intermediate results. An example would be reading a 12-bit AID, performing some gain and offset calculation on the raw AID data to produce a calibrated 16 bit result. Doing this is a simple task with this math package. CALL Add_16 (offset_value); Mid_16 Returns the middle 16 bits of the accumulator, bits 8 through 23. CALL Mul_16 (gain_factor); ,. gain is in units of 1,256 ., High_16 Returns the upper 16 bits of the accumulator, bits 16 through 31. MuLl6 (word_param) Multiplies the 32-bit accumulator by the 16-bit word supplied, result left in accumulator. Div_16 (word_pararn) Divides the 32-bit accumulator by th~ 16-bit word supplied, result left in accumulator. Add_16 (word_param) Adds the 16-bit word supplied to the 32-bit accumulator. result = Mid_16; In this example the accumulator was loaded with the raw AID value and then the offset was applied. The gain3actor was "pre-multiplied" by 256 (8 bits), giving it a granularity of 11256. The result was extracted from the "middle" 16 bits of the accumulator (bits 8 to 23) to account for the scaling factor of 256 introduced in the multiply step. The package requires about 384 bytes of ROM and 30 bytes of RAM. Individual routines can be deleted to conserve RAM if they are not used. 2-167 intJ AB·40 CODE SOURCE LISTINGS CODE SOUICE LISTINGS , PUBLIC PUBLIC PUBLIC PUBLIC PUBLIC PUBLIC PUBLIC PUBLIC PUBLIC ; Load_16, ?Load_16?byte Load 32, ?Load 32?byte Mul 16, ?Mul 16?byte Div-16, ?Div-16?byte Add-16, ?Add-16?byte Sub-16, ?Sub-16?byte Add-32 , ?Add-32?byte Sub-32, ?Sub-32?byte r.ow:16, Mid~16, High_16 Math 32 Data Math:32:Code DATA COOE ; RSEG Math 32 Data ?Load 16?byte: -OS 2 ?Load:32?byte: OS 4 ?ml_16?byte: OS 2 ?Div_16?byte: OS 2 OS 2 ?Add_16?byte: ?Sub_16?byte: OS 2 ?Add 32?byte: OS 4 ?Sub:32?byte: OS 4 OP 0:' OS 1 ap-l: OS 1 OP-2: OS 1 ap-3: OS 1 'IMP 0 'IMP-l 'IMP-2 'IMP:3 ; OS OS OS OS 1 1 1 1 RSEG 270530-1 2-168 inter AB-40 Load 16: ;Lead the lower 16 bits of the OP registers with OP 3,fO I'fJV OP-2,fO MOV ~V O(), ?Load_16?byte OP_O,?Load_i6?byte + 1 I'fJV ~~e value supplied RE:l' Load 32: ;Lead MOV MeV MOV MeV RE:l' all the OP registers with the value supplied OP 3,?Load 32?byte OP-2,?Load-32?byte + 1 OP-l,?Load-32?byte + 2 OP-0,?Lead-32?byte + 3 - - Low 16: -iReturn the lower 16 bits of the OP registers MOV R6,OP 1 MOV R7,OP-0 RE:l' - Mid 16: -;Return the middle 16 bits of the OP registers MeV R6,OP 2 MeV R7,OP:) RE:l' High 16: ;Return the high 16 bits of the OP registers MOV R6,OP 3 MOV R7,OP=Z RE:l' Add 16: -iAdd the 16 bits supplied by the caller to the OP registers CLR mv ADDC MOV MeV ADOC MOV MOV AOOC MOV MOV /\DOC I!IJV C A,OP 0 A,?Add_16?byte + 1 OP O,A A,'OP 1 A,?Add_16?byte OP I,A A,OP 2 1'.,40OP 2,1'. A,OP 3 1'.,40OP_3,A ;1ow byte first ;high byte + carry ;propagate carry only ;propagate carry only RE:l' 270530-2 2-169 inter AB-40 Add 32: -;Add the 32 bits supplied_ by the caller to tne OP registers CLR C ADOC A,OP 0 A,?Add 32?byt= + 3 OP O,A- rov I'IJV I:'IJV AOOC I'CN I'DV AOOC I'DV I'CN ACre I'CN ;lowest byte flrst A,OP 1 A,?Add 32?byte + 2 OP 1,A- ;mid-lowest byte + carry A,OP 2 A,?Add 32?byte + 1 OP 2,AA,OP 3 A,?Add 32?byte OP_3,A- ;mid-highest byte + carry ;highest byte + carry RET Sub 16: -;Subtract the 16 bits supplied by the caller from the OP registers CLR I:'IJV C SUBS A,?sUb 16?byte + 1 OP O,A- I'DV I'DV SUBS l"I:N I'CN SUBB l"I:N l'DV A,OP 0 ;low byte first A,OP 1 A, ?SUb 16?byte OP 1,A- A,OP 2 A,tO- ; high byte + carry ;propagate carry only OP 2,A SUBB A,OP 3 A,.O- I'CN OP_3,A ;propagate carry only RET Sub 32: -;Subtract the 32 bits supplied by the caller fran the OP registers CLR C I'CN I'CN A,OP 0 A,?SUb 32?byte + 3 OP O,A- I:'IJV A,OP 1 SUBS A,?SUb 32?byte + 2 OP l,le SUBB I'CN I:'IJV SUBS I:'IJV I'CN SUBB I'CN ;lowest byte first ;mid';lowest byte + carry A,OP 2 A,?SUb 32?byte + 1 OP 2,AA,OP 3 A,?SUb 32?byt; OP_3,A- ;mid-highest byte + carry ;highest byte + carry RET 270530-3 2-170 AB-40 Mul 16: -iMultiply the 32 bit OP with the 16 value supplied I:'DV 'll1P 3,10 iclear out upper 16 bits I:'DV niP-2, to ;Genecate the lowest byta of the result I:'DV S,OP a MaV A,?HUl l6?byte+l MlJL lIB - I:'DV 'll1P a,A ilow-order result I:'DV 'll1P-l,a ihigh order result iNa.I generate the next higher order byte I:'DV a,op I:'DV A, ?Mill 16?byte+l !f1L ADD I:'DV lIB 1 - A, 'll1P 1 ilow-order result niP l-;A save I:'DV A,aget high-order result ADOC A,niP 2 include carry from previous operation I:'DV niP 2-;A save JNC Mul-loopl INC niP-3 propagate carry into niP_3 Mul loopl: -I:'DV S,OP a I:'DV A,?HUl l6?byte !ilL lIB ADO A,niP 1 'll1P l-;A A,aA, 'll1P 2 'll1P 2-;A Mul-loop2 'll1P:) I:'DV I:'DV ADOC I:'DV JNC INC Mul loop2: -; Now - i la.l-order result save get high-order result include carry from previous operatioo save propagate carry into 'll1P_3 start IoOrking on the 3rd byte I:'DV S,OP 2 MaV A,?HUl l6?byte+l MUL ADD I:'DV I:'DV A, 'll1P 2 'll1P 2-;A A, a- ADOC A,'IMP 3 I:'DV i Now I:'DV I:'DV lIB - niP 3-;A the other half S,OP 1 A,?HUl_16?byte MlJL AS ADO MaV MaV ADOC 'IMP ;low-order result save get high-order result include carry from previous operation save A,niP 2 ;low-order result 2-;A ; save A,Si get high-order ,result A, 'll1P_ 3 ; include carry from previous operation I:'DV 'll1P 3, A ; save ; Now finish off the highest order byte /!IN S,OP 3 I:'DV A,?Mul_16?byte+l 270530-4 2-171 AB-40' ~ AS ADD A,TMP_3 ;low-order result TMP 3,A ; save ; Forget about the high-order result, this is only 32 bit math! HOV I'DV I'DV ~ a,op 2 A,?MUl l6?byte AS - ADD A,TMP 3 ;low-order result I'DV ' 'IMP 37A ; save ; Now 'ole are all done, nove the TMP values back into OP HOV OP O,'IMP 0 HOV OP-l,'iMP-l HOV OP-2,TMP-2 HOV OP-3,'IMP-3 REI' - 270530-5 2-172 AB-40 Div 16: -;This divides the 32 bit OP register by the value supplied I:'OV R7,.0 :-OV R6,fO ; zero out partial r~mainder I:'OV 'IMP 0,.0 :-OV 'IMP-l,iO l"l:N 'IMP-2,fO I:'OV 'IMP-3, to I:'OV Rl,?Div 16?byte ;load divisor I:'OV RO,?Div-16?byte+l l"l:N RS,'32 ;loop count ;This begins the loop Div loop: -CALL tiN RU: I'PV I'PV Shift 0 A,R6 - ;shift the dividend and return MSB in C ;shift carry into LSB of partial remainder A R6,A A,R7 au:: A l"l:N R7,A ;now test to see if R7:R6 >= Rl:RO CLR I'PV C CLR C A,R7 ; subtract Rl from R7 to see if Rl < R7 A,Rl ; A = R7 - Rl, carry set 1f R7 < Rl JC Cant sub oat this poInt R7>Rl or R7=Rl JNZ Can sub ;junp if R7>Rl ;if R7 .. aI, test for R6>=RO suea A,R6 A,RO ; A = R6 - RO, carry set if R6 < RO JC Cant sub Can sub: -;subtract the divisor from the partial remainder l"l:N SUBS CLR C I:'OV A,R6 A,RO R6,A A,R7 A,Rl R7,A SUBB I'PV I'PV SUBB l"l:N SE'I'B JMP A = R7 - Rl - Borrow shift a 1 into the quotient C Quot Cant sub: ;shift a CLR A=R6-RO a into the quotient C Quot: ;shift the carry b1: lnto the quotient Shift Q ; Test for COmpetlcn DJNZ RS,Div loop ; Now we are done, rove the 'IMP values back into OP l"l:N OP O,TMP 0 I'PV OP:l,'IMP:l CALL all 270530-6 2-173 infef I'DV I'DV RET AB-40 OP 2,'IMP 2 O(),'IMP:) Shift D: ;shift the dividend one bit to the left and return the ~B in C CLR C I'DV RLC I'DV 1'01 RLC I'DV A,OP 0 A OP O,A A OP 1,A I'J)V . A,OP 2 RLC 1'01 1'01 RLC 1'01 A OP 2,A A,OP 1 A,OP 3 A OP_3,A RET Shift Q: ;shift the quotent one bit to the left and shift the C into LSB 1'01 RIC I'DV 1'01 RIC 1'01 I'DV RLC I'DV A,'IMP 0 A 'IMP O,A A,'lMP 1 A 'IMP 1,A A,'lMP 2 A 'IMP 2,A RLC A,'lMP 3 A - I'DV 'IMP_3,A I'J)V RET 270530-7 2-174 APPLICATION BRIEF AB-12 October 1987 Designing a Mailbox Memory for Two 80C31 Microcontrollers Using . EPLDs K. WEIGL & J. STAHL INTEL CORPORATION MUNICH, GERMANY © Intel Corporation, 1987 Order Number: 292016-002 2-175 AB-12 INTRODUCTION Very often, comple;x systems involve two or more microcontrollers to fulfill the requirements defined by a given objective. Since the nature of microcontrollers does not allow for easy dual-port memory design (no "READY" input; no "HOLD/HLDA" interface; portoriented I/O etc.), design engineers are faced with the problem of interchanging information (data and status) between those microcontrollers. This application brief describes the design of a mailbox for exchanging information between two 80C3ls, using a SC060 H-EPLD as a "back-to-back" register, and a SC031 H-EPLD as an arbitration vehicle to control the actions of the CPUs. THE 5COGO MAILBOX The SC060 allows for independent clocking of 8 macrocells on each side of the chip, the two clock inputs are used to clock data from the microcontroller bus into the chip. To read the data written into the mailbox by one of the controllers, the RDA- (controller A is reading) or RDB- (controller B is reading) line must be pulled low by activating the read command (IRD). In order to avoid spurious read-cycles, the /RD commands from both microcontrollers are logically "ORed" together with an active high CS-signal (Chip Select) inside the SC060. The CS-signal for both ports is derived from address line AI5. Therefore, whenever AI5 becomes a logic "I" (true), the mailbox is activated and ready to take or submit data. Address range for the mailbox: FOOO Hex to FFFF Hex (Upper 12 kbyte) In this application, the 16 macrocells of the SC060 are grouped into two sets of 8 so called "ROlF" (register output with input feedback) primitives to implement the two 8 bit bus interfaces needed. The grouping is done according to the following picture. 5C060 2-176 inter AB-12 THE 5C031 "MAILBOX CONTROLLER" To keep the two microcontrollers informed about the status of their mailbox, the 5C031 is programmed to supply the following signals to both controllers: /OBFA: "OUTPUT BUFFER FULL" FOR Me A /OBFB: "OUTPUT BUFFER FULL" FOR Me B /IBEA: "INPUT BUFFER EMPTY" FOR Me A /IBEB: "INPUT BUFFER EMPTY" FOR Me B /INTA: INTERRUPT TO Me A /INTB: INTERRUPT TO Me B The next section will discuss the meanings of these signals in more detail. Output Buffer Full: This flag is set whenever the controller writes into its own output buffer. The flag remains valid, until the second controller has read the data. The flag is automatically reset to its inactive state when this read cycle is accomplished. NOTE: Both controllers can access (read or write) the mailbox simultaneously. Input Buffer Empty: This flag indicates that there is no message in the mailbox. The flag will become inactive as soon as one microcontroller places a message for the other one (or vice versa). Example: IIBEA remains "LOW" until microcontroller B places a message for controller A into the mailbox for A. IIBEA will go "HIGH" as soon as controller B has accomplished its write cycle, and will not go "LOW" again until microcontroller A has read the message. Interrupt: The 5C031 is programmed to supply interrupts to both microcontrollers involved, on one of the following events. 1. The IOBF flag of the opposite microcontroller becomes active; e.g. if controller A is placing a message for controller B, controller B receives an interrupt the same time as IOBFA becomes valid or vice versa. 2. The IIBE flag of the opposite microcontroller goes active, indicating that this controller has received the message; e.g. if controller B reads the message stored by controller A, its IIBEB flag goes active and controller receives an interrupt indicating that the buffer is empty. The signals described above are necessary to accomplish a secure handshake without overwriting messages accidentally. In addition to that, the 5C031 is issuing the actual write commands for the two register sets inside the 5C060. The /WRA and /WRB signals are results oflogical "AND" functions between the appropriate CS- and /WR signals from the microcontrollers. Therefore, spurious write cycles are unlikely to happen. NOTE: This design can also be efficiently implemented in a single 5CBIC EPLD. 2-177 AB-12 B A AOO-A07 PO " ill i'r L. 74HCT373 ~ ~-~~ ~r CE OE ALE A8-A15 P2 PSEN r- " I' - - ill 00-07 00-07 AO-A7 AO-A7 .~ ~ 027C64 027C64 A8-12 A8-12 OECS CSOE ~ . ~r ~~ OE CE ~ ~L. ~~ 74HCT373 AOO-A07 .:"\1 PO . - ~ ALE A8-A15 P2 I---:- l- PSEN A 00-07 ~ P80C31BH 00-07 AO-A7 AO-A7 RAM RAM ~ P80C31BH It A15 A8-12 iID WR A8-12 CS CS WR I II Rii P3.7 WRP3.6 A15 iID II- RDP3.7 WRP3.6 5C060 lOA 0-7 lOB 0-7 ROA CSA WA I"'" ROB CSB WB ~- I----' f- 5C031 - WA WRA ' - - - ROA RST -- P3.4 P3.5 P3.2INTO RESET r WB WRB ROB CSA CSB OBrA OBrB IBEA IBEB INTA INTB RST OE Block Diagram 2-178 -P3.4 P3.5 INTOP3.2 1 RESET 292016-1 AB-12 5C060 "BACK TO BACK REGISTER" WB lOAD ~~ -r- t- L ~ o- 10Al ~- _~ ~ r.. 1 A L ~ - _L ~ r.. - '- IOA3 10M 10AS IOA6 1. . . r.. 1 1 1 A t.... A L A -- L 1 - -r- L r-r-- _ .... 1/ -r- _.... r--r- L A -- - ~ ... L " 10Bl " IOB2 " IOB3 ~ ~ ~ .... IOB4 .... IOB5 .... IOB6 ....:r .... 0 - L r-r-~I-- ....:r ... 0 - L r-~ ...1 ... ' - 0 - ... IOA7 lOBO '- '- IOA2 ~~ L ... '-- ~ .... IOB7 ~ -"-, WA ROA CSA La: :V- 2-179 ROB CSB 292016-2 AB-12 5C031 "MAIL BOX CONTROLLER" WRA CSA -_:::;~~'-""J---"""--------------D- WA JO--IBEB ROB OBrA INTA RST INTB OBrB ROA IBEA CSB WRB WB OE 292016-3 2-180 inter AB-12 5C060 REGISTER ADF JUERG INTEL March 80C31 STAHL ZUERICH 27, 1986 MAILBOX MEMORY USING 5C060 / 5C031 1 ******************** ** EXAMPLE .ADF ** ******************** 5C060 LB Version 3.0, Baseline 17x, 9/26/85 PART: 5COSO INPUTS: WB81, CSA82, CSB814, nRDA811, nRDB823, WA813 OUTPUTS: 1087815, IOA7810, IOBS81S, IOAS89, rOB5817, IOA588, IOB4818, IOA487, IOB3819, IOA386, IOB2820, IOA285, IOB1821, IOA184, IOB0822, IOA083 NETWORK: IOB7,DB7 ROlF (DA7,WAC,GND,GND,RDBC) IOA7,DA7 ROlF (DB7,WBC,GND,GND,RDAC) IOB6,DB6 ROlF (DA6,WAC,GND,GND,RDBC) IOA6,DA6 ROlF (DBS,WBC,GND,GND,RDAC) IOB5,DB5 ROlF (DA5,WAC,GND,GND,RDBC) IOA5,DA5 ROlF (DB5,WBC,GND,GND,RDAC) IOB4,DB4 ROlF (DA4,WAC,GND,GND,RDBC) IOA4,DA4 ROlF (DB4,WBC,GND,GND,RDAC) IOB3,DB3 ROlF (DA3,WAC,GND,GND,RDBC) IOA3,DA3 ROlF (DB3,WBC,GND,GND,RDAC) IOB2,OB2 ROlF (DA2,WAC,GND,GND,RDBC) IOA2,DA2 ROlF (DB2,WBC,GND,GND,RDAC) IOB1,OBl ROlF (DA1,WAC,GND,GND,RDBC) rOA1,OAl ROlF (DB1,WBC,GND,GND,RDAC) IOBO,DBO ROlF (DAO,WAC,GND,GNO,RDBC) IOAO,DAO ROlF (DBO,WBC,GND,GND,RDAC) WAC = INP (WA) RDBC = AND(CSBI,RDBI) WBC INP (WB) RDAC = AND(CSAI,RDAI) CSB! = INP (CSB) nRDBI INP(nRDB) nRDAI INP(nRDA) CSA! INP(CSA) RDAI NOT(nRDAI) RDBI NOT(nRDBI) = = = = END$ 292016-4 2-181 intJ AB-12 5C060 REGISTER LEF JUERG INTBL March 80C31 STAHL ZUERICH 27, 1985 MAILBOX MEMORY USING 5COSO / 5C031 1 ******************** ** BXAMPLE .LEF ** ******************** 5COSei LB Version 3.0, Basel iDe 17x, 9/2S/85 LEF VersioD 1.0 BaseliDe 1.51 02 Feb 1987 PART: 5COSO INPUTS: WB81, CSA82, CSB814, nRDA811, nRDB823, WA813 OUTPUTS: IOB7815, IOA7810, IOB6816, IOA689, IOB5817, IOA588, IOB4818, IOA487, IOB3819, IOA386, IOB2820, IOA285, .IOB1821, IOA184, IOB0822, IOA083 NETWORK: WBC = INP(WB) WAC = IHP(WA) CSAI = INP(CSA) CSBI = INP(CSB) nRDAI = INP(nRDA) nRDBI = INP(nRDB) IOB7, DB7 ROIF(DA7, WAC, GND, GND, RDBC) IOA7, DA7 ROIF(DB7, WBC, GND, GND, RDAC) lOBS, DBS ROIF(DA6, WAC, GND, GND, RDBC) IOAS, DAS ROIF(DB6, WBC, GND, GND, RDAC) IOB6, DB5 ROIF(DA5, WAC, GND, GND, ROBC) IOA6, DA6 ROIF(DB5, WBC, GND, GND, RDAC) IOB4, DB4 ROIF(DA4, WAC, GND; GND, RDBC) IOA4, DA4 ROIF(DB4, WBC, GND, GND, RDAC) I,OB3, DB3 ROIF(DA3, WAC, GND, GND, RDBC) IOA3, DA3 ROIF(DB3, WBC, .GND, GND, RDAC) IOB2, DB2 ROIF(DA2, WAC, GND, GND, RDBC) IOA2, DA2 ROIF(DB2, WBC, GND, GND, RDAC) lOBI, DB1 ROIF(DA1, WAC, GND, GND, ·RDBC) IOA1, DA1 ROIF(DB1, WBC, GND, GND, RDAC) lOBO, DBO ROIF(DAO, WAC, GND, GND, RDBC) 10AO, DAD ROIF(DBO, WBC, GND, GND, RDAC) EQUATIONS: RDAC CSAI nRDAI'; * RDBC CSB~ * nRDBI'; END$ 292016-5 2-182 inter AB-12 5C060 REGISTER UTILIZATION REPORT Logic Optimizing Compiler Utilization Report FIT Ve~aion 1.0 Baseline 1.Oi 2/6/87 ***** Design implemented successfully JUBRG STAHL INTEL ZUERICH Ma~ch 27, 1986 80C31 MAILBOX MEMORY USING 5C060 / 5C031 1 5C060 """""""""""'" " EXAMPLE .RPT FILE " """""""'*"""'" LB Veraion 3.0, Baseline 17x, 9/26/85 5C060 WB CSA 10AO lOA! IOA2 IOAJ 10A4 10A5 IOA6 IOA7 nRDA GND - I 2 3 - 4 - 5 - 6 - 7 - 8 - 9 -:10 -: II -:12 - 24:23:22:21: 20:19:18:17:16:15:14: 13:- Vcc nRDB lOBO lOBI IOB2 IOB3 10B4 IOB5 IOB6 10B7 CSB WA '*INPUTSU Na.e Pin WB Resource MCell II PTerms MCella Feeds: Oil Clea~ INP Clock CLKI CSA 2 INP 9 10 11 12 13 14 15 16 nRDA 11 IMP 9 10 11 12 13 14 15 16 GND 12 GND 1 2 3 4 5 6 7 8 9 292016-6 2-183 inter AB·12 5C060 REGISTER UTILIZATION REPORT (Continued) 10 11 12 13 14 15 16 WA 13 INP CSB 14 INP CLK2 1 2 3 4 5 6 7 8 nRDB 23 INP 1 2 3 4 5 6 7 8 Vee 24 Vee Na.e Pin Resource IOAO 3 10Al IOA2 IOA3 "OUTPUTSn , PTerm. ROlF 9 1/ 8 4 ROlF 10 1/ 8 5 ROlF 11 1/ 8 3 6 ROlF 12 1/ 8 4 IOA4 7 ROlF 13 1/ 8 5 IOA5 8 ROlF 14 1/ B 6 IOA6 9 ROlF 15 1/ B 7 IOA7 10 ROlf 16 1/ B 8 IOB7 15 ROlF 8 1/ 8 16 IOB6 16 ROlf 7 1/ 8 15 14 HCell Feeds: MCells lOBS 17 ROlf 6 1/ B 18 ROlf 5 1/ 8 13 1083 19 ROlF 4 1/ 8 12 1082 20 ROlf 1/ 8 11 lOBI 21 ROlf 2 1/ 8 10 11 8 9 22 ROlF Clear Clock 2 1084 [080 OB 292016-7 . All Resources used nPART UTILIZATIONn 100lr 100lr 12' Pine MacroCelb Ptera. 292016-8 2-184 inter AB-12 5C031 ARBITER ADF JUBRG INTBL Msrch 80e31 STAHL ZUBRICH 28, 1986 MAILBOX MBMORY USING 5C06Q / 5C031 ******************** ** BXAMPLE .ADF ** ******************** 2 5C031 LB Version 3.0, Baseline 17x, 9/26/85 PART: 5C031 INPUTS: RST,nWRA,nRDB,CSA,nRDA,nWRB,eSB,nOB OUTPUTS: WA,nOBrA,nIBBB,nINTA,nINTB,nOBFB,nIBBA,WB NBTWORK: nWRA = INP(nWRA) nRDB = INP(nRDB) RST = INP(RST) eSA = INP(CSA) nRDA = INP(nRDA) nWRB = INP(nWRB) eSB INP(eSB) nOB INP(nOB) WRA NOT(nWRA) WRB NOT(nWRB) RDA NOT(nRDA) RDB NOT(nRDB) OE = NOT(nOE) nRST = NOT(RST) WA = CONF(WAd,YCC) WAd = AND(CSA,WRA) WB = eONF(WBd,YeC) WBd = AND(eSB,WRB) nRB = NAND(RDB,eSB) nRA = NAND(RDA,eSA) nWAd = NOT(WAd) nWBd = NOT(WBd) nOBFA,nOBFA COCF(nOBFAd,OE) nOBrB,nOBFB = COer(nOBFBd,OE) nIBEA,nIBEA COCF(nIBBAd,OE) nIBBB,nIBBB = COCF(nIBBBd,OE) nINTA = CONF(nINTAd,OE) nINTB = eONF(nINTBd,OB) nINTAd AND(nOBFA,nIBBA) nINTBd AND(nOBFB,nIBBB) nOBFBd NAND(nRA,nIBBA,nRST) nOB FAd NAND(nRB,nIBBB,nRST) NAND(nWAd,nOBFA) nIBEBd nIBBAd NAND(nWBd,nOBFB) = ENDS 292016-9 2-185 AB-12 5C031 ARBITER LEF JUBRG INTEL March 80C31 STAHL ZUERICH 2B, 1986 MAILBOX MEMORY USING 5C060 / 5C031 ************"**'*** " BXAMPLE .LBF " """'**"**'*"'*' 2 5C031 LB Version 3.0, Baseline 17x, 9/26/85 LBF Yersion 1.0 Baseline 1.5i 02 Feb 1987 PART: 5C031 INPUTS: RST, nWRA, nRDB, CSA, nRDA, nWRB, CSB, nOB OUTPUTS: WA, nOBFA, nIBBB, nINTA, nINTB, nOBFB, nIBEA, WB NITWORK: RST = INP(RST) nWRA = INP(nWRA) nRDB = INP(nRDB) CSA = INP(CSA) nRDA = INP(nRDA) nWRB = INP(nWRB) CSB = INP(eSB) nOE = INP(nOI) WA = CONF(WAd, VCC) nOBFA, nOBFA = COeF(nOBFAd, 01) nIBBB, nIBIB = eOCF(nIBBBd, OB) nINTA = CONF(nINTAd, OB) nINTB = CONF(nINTBd, 01) nOBFB, nOBFB = COCF(nOBFBd, 01) nIBBA, nIBBA = COCF(nIBEAd, OB) WB = CONF(WBd, YCC) EQUATIONS: WBd = CSB * DWRB'; nlBEAd CSB * nWHB' + nOBFB '; nOBFDd + nOBFB nINTBd nlNTAd nIBKBd (nIBIA nIDBA * RST' * CSA' * RST' * nRDA)'; * nIBBB; nOBFA ,_ nIBEA; CSA' nWRA' + nOBFA'; OK = ~OB'; nOBFAd WAd = (nIBBB + = eSA nIBBB * RST' *, CSB' nRDB)'; * RST' , nWRA'; IINDS 292016-10 2-186 inter AB·12 5C031 ARBITER LEF (Continued) Logic Optimizing Compiler Ut'ilization Report FIT Version 1.0 Baseline 1.0i 2/6/87 ****. JUERG INTEL Mareh 80C31 Design i.plemented successfully STAHL ZUERICH 28, 1986 MAILBOX MEMORY USING 5C060 / 5C031 ************************* ** EXAMPLE .RPT FILE ** ************************* Z 5C031 LB Version Baseline 17x, 9/26/85 3.0~ 5C031 GND GND nOI! CSB nWRB nRDA CSA nRDB nWRA GND -: - - 1 2 3 4 5 6 7 B 9 10 20:19:18:17:16:15:14: 13:12: - Vee WB WA nOBFB nINTB nINTA nIBBS nOBFA nIBEA 11: - RST nINPUTsn Naae Pin Reeource nOB 3 INP Meell • PTeras MCells Feeds: OJ! Clear Preset 3 4 5 6 7 B CSB 4 INP nWRB 5 INP I 7 B 1 B nRDA 6 INP 3 CSA 7 INP 2 3 DRDB 8 INP nWRA 9 INP 6 7 2 6 GND 10 GND RST 11 INP 3 7 Vee 20 Vee 1 2 292016-11 2-187 infef AB·12 5C031 ARBITER UTILIZATION REPORT UOUTPUTS** , PTer•• MCe11. cocr a 2/ a 3 cocr 7 2/ a 5 6 2/ a Na.e Pin Resource nIBEA 12 nOarA 13 MCell Feed.: OE Clear Pre.et 5 6 nIBEB 14 cocr nINTA 15 CONr 5 1/ a nINTB 16 CONr 4 1/ a nOBra 17 cocr 3 2/ 8 WA 1a CONr 2 1/ a WB 19 CONr ..7 4 a 1/ a **UNUSED RESOURCES** Na.e Pin Resource MCell PTer•• 1 2 **PART UTILIZATIONn 88. 100. 1a. Pina MacroCe11s pter•• 292016-12 2-188 inter APPLICATION NOTE AP-252 September 1987 Designing With The 80C51BH TOM WILLIAMSON MCO APPLICATIONS ENGINEER Order Number: 270068·002 2·189 AP·252 CMOS EVOLVES The original CMOS logic families were the 4000-series and the 74C-series circuits. The 74C-series circuits are functional equivalents to the corresponding numbered 74-series TTL circuits, but have CMOS logic levels and retain the other well known characteristics of CMOS logic. These characteristics are: low power consumption, high noise immunity, and slow speed. The low power consumption is inherent to the nature of the CMOS circuit. The noise immunity is due partly to the CMOS logic levels, and partly to the slowness of the circuits. The slow speed is due to the technology used to construct the transistors in the circuit. The technology used is called metal-gate CMOS, because the transistor gates are formed by metal deposition. More importantly, the gates are formed after the drain and source regions have been defined, and must overlap the source and drain somewhat to allow for alignment tolerances. This overlap plus' the relatively large size of the transistors themselves result in high electrode capacitance, and that is what limits the speed of the circuit. High speed CMOS became feasible with the development of the self-liligning silicon gate technology. In this process polysilicon gates are deposited before the source and drain regions are defined. Then the source and drain regions are formed by ion implantation using the gate itself as a mask for the implantation. This eliminates most of the overlap capacitance. In addition, the' process allows smaller transistors. The result is a significant increase in circuit speed. The 74HC-series of CMOS logic circuits is based on this technology, and has speeds comparable to LS TTL, which is to say about 10 times faster than the 74C-series circuits. The size reduction that contributes to the higher speed also demands an accompanying reduction in the maximum supply voltage. High-speed CMOS is generally limited to 6V. WHAT IS CHMOS? CHMOS is the name given to Intel's high-speed CMOS processes. There are two CHMOS processes, one based on an n-well structure and one based on a powell structure. In the .n-well structure, n-type wells are diffused into a p-type substrate. Then the n-channel transistors. (nFETs) are built into the substrate and pFETs are built into the n-wells. In the p-well structure, p-type wells are diffused into an n-type substrate. Then the nFETs are built into the wells and pFETs, into the substrate. Both processes have their advantages and disadvantages, which are largely transparent to the user. Lower operating voltages are easier to obtain with the powell structure than with the n-well structure. But the powell structure does not easily adapt to an EPROM which would be pin-for-pin compatible with HMOS EPROMs. On the other hand the n-well structure can be based on ,the solidly founded HMOS process, in Wllich nFETs are built into a p-type substrate. This allows somewhat more than half of the transistors in a CHMOS chip to be constructed by processes that are already well characterized. Currently Intel's CHMOS microcontrollers and memory products are n-well devices, whereas CHMOS microprocessors are powell devices. Further discussion of the CHMOS technology is provided in References I and 2 (which are reprinted in the Microcontroller Handbook). THE MCS®·51 FAMILY IN CHMOS The 80C51BH is the CHMOS version of Intel's original 8051. The 80C31BH is the ROMless 80C51 BH, equivalent to the 8031. These CHMOS devices are architecturally identical with their HMOS counterparts, except that they have two added features for reduced power. These are the Idle and Power Down modes of operation. In most cases, an 80C51BH can directly replace the 8051 in existing applications. It can execute the same code at the same speed, accept signals from the same sources, and drive the same loads. However, the 80C51BH covers a wider range of speeds, will emit CMOS logic levels to CMOS loads, and will draw about 1/10 the current of an 8051 (and less yet in the reduced power modes). Interchangeability between the HMOS and CHMOS devices is discussed in more detail in the final section of this Application Note. It should be noted that the 80C51BH CPU is not static. That means if the clock frequency is too low, the CPU might forget what it was doing. This is because the circuitry uses a number of dynamic nodes. A dynamic node is one that uses the note-to-ground capacitance to form a temporary storage cell. Dynamic nodes are used to reduce the transistor count, and hence the chip area,' thus to produce a more economical device. This is not to say that the on-chip RAM in CHMOS microcontrollers is dynamic. It's not. It's the CPU that is dynamic, and that is what imposes th, minimum clock frequency specification. 2-190 intJ AP-252 LATCHUP Latchup is an SCR-type turn-on phenomenon that is the traditional nemesis of CMOS systems. The substrate, the wells, and the transistors form parasitic pnpn structures within the device. These parasitic structures turn on like an SCR if a sufficient amount of forward current is <;Iriven through one of the junctions. From the circuit designer's point of view it can happen whenever an input or output pin is externally driven a diode drop above Vee or below Vss, by a source that is capable of supplying the required trigger current. However much of a problem latchup has been in the past, it is good to know that in most recently developed CMOS devices, and specifically in CHMOS devices, the current required to trigger latchup is typically well over 100 rnA. The 80C5IBH is virtually immune to latchup. (References 1 and 2 present a discussion of the latchup mechanisms and the steps that are taken on the chip to guard against it.) Modern CMOS is not absolutely immune to latchup, but with trigger currents in the hundreds of rnA, latch up is certainly a lot easier to avoid than it once was. A careless power-up sequence might trigger a latchup in the older CMOS families, but it's unlikely to be' a major problem in high-speed CMOS or in CHMOS. There is still some risk incurred in inserting or removing chips or boards in a CMOS system while the power is on. Also, severe transients, such as inductive kicks or momentary short-circuits, can exceed the trigger current for latchup. For applications in which some latchup risk seems unavoidable, you can put a small resistor (lOOn or so) in series with signal lines to ensure that the trigger current will never be reached. This also helps to control overshoot and RFI. LOGIC LEVELS AND INTERFACING PROBLEMS CMOS logic levels differ froin TTL levels in two ways. First, for equal supply voltages, CMOS gives (and requires) a higher "logic I" level than TTL. Secondly, CMOS logic levels are Vee (or VDD) dependent, whereas guaranteed TTL logic levels are fixed when Vee is within TTL specs. Standard 74HC logic levels are as follows: VIHMIN = 70% of Vee VILMAX = 20% of Vee VOHMIN = Vee - O.lV, IIOHI :s; 20/LA VOLMAX = O.lV, Ilod :s; 20 /LA Figure I compares 74HC, LS TTL, and 74HCT logic levels with those of the HMOS 8051 and the CHMOS 80C5IBH for Vee = 5V. Output logic levels depend of course on load current, and are normally specified at several load currents. When CMOS and TTL are powered by the same Veo the logic levels guaranteed on the data sheets indicate that CMOS can drive TTL, but TTL can't drive CMOS. The incompatibility is that the TTL circuit's VOH level is too low to reliably be recognized by the CMOS circuit as a valid VIH. Since HMOS circuits were designed to be TTL-compatible, they have the same incompatibility. Fortunately, 74HCT-series circuits are available to ease these interfacing problems. They have TTL-compatible logic levels at the inputs and standard CMOS levels at the outputs. The 80C5IBH is designed to work with either TTL or CMOS. Therefore its logic levels are specified very much like 74HCT circuits. That is, its input logic levels are TTL-compatible, and its output characteristics are like standard high-speed CMOS. NOISE CONSIDERATIONS One of the major reasons for going to CMOS has traditionally been that CMOS is less susceptible to noise. As previously noted, its low susceptibility to noise is Vee Logic State = 5V 74HC 74HCT LSTTL VIH VIL 3.5V 1.0V 2.0V O.8V 2.0V O.8V 2.0V 0.8V 1.9V 0.9V VOH VOL 4.9V O.1V 4.9V O.1V 2.7V O.5V 2.4V O.45V 4.5V 0.45V 8051 80C51BH Figure 1. Logic Level Comparison. (Output voltage levels depend on load current. Data sheets list guaranteed output levels for several load currents. The output levels listed 'here are for minimum loading.) 2-191 inter AP·252 partly due to superior noise margins, and partly due to its slow speed. , Noise margin is the difference between VOL and VIL, or between VOH and VIH. IfVOH from a driving circuit is 2.7V and VIH to the driven circuit is 2.0V, then the driven circuit has 0.7V of noise margin at the logic high level. These kinds· of comparisons show that an all-CMOS system has wider noise margins than an allTTL system. Figure 2 shows noise margins in CMOS and LS TTL systems when both have Vee = 5V. It can be seen that CMOS/CMOS and CMOS/CHMOS systems have an edge over LS TTL in this respect. Noise margins can be misleading, however, because they don't say how much noise energy it takes to induce in the circuit a noise voltage of sufficient amplitude to cause a logic error. This would involve consideration of the width of the noise pulse as compared with the circuit's response speed, and the impedance to ground from the point of noise introduction in the circuit. When these considerations are included, it is seen that using the slower 74C- and 4OOO-series circuits with a 12 or 15V supply voltage does offer a truly improved level of noise immunity, but that high-speed CMOS at 5V is not significantly Better than TTL. current in extremely sharp spikes at the clock edges. The VHF and UHF components of these spikes are not drawn from the power supply, but from the decoupling capacitor. If the decoupling circuit is not sufficiently low in inductance, Vee will glitch at each clock edge. We suggest that a 0.1 p.F decoupler cap be used in a minimum-inductance configuration with the microcontroller. A minimum-inductance configuration is one that minimizes the area of the loop formed by the chip (Vee to Vss), the traces to the decoupler cap, and the decoupler cap. PCB designers too often fail to understand that if the traces that connect the decoupler cap to the Vee and Vss pins aren't short and direct, the decoupler loses much of its effectiveness. Overshoot and ringing in signal lines are potential sources of logic upsets. These can largely be controlled by circuit layout. Inserting small resistors (about lOOn.) in series with signal lines that seem to need them will . also help. The sharp edges produced by high-speed CMOS can cause RFI problems. The severity of these problems is largely a function of the PCB layout. We don't mean to imply that all RFI problems can be solved by a better PCB layout. It may well be, for example, that in some RFI-sensitive designs high-speed CMOS is simply not the answer. But circuit layout is a critical factor in the noise performance of any electronic system, and more so in high-speed CMOS systems than others. One should not mistake the wider supply voltage tolerance of high-speed CMOS for Vee glitch immunity. Supply voltage tolerance is a DC rating, not a glitch rating. Circuit layout techniques for minimizing noise susceptibility and generation are discussed in References 3 throllgh 6. For any clocked CMOS, and most especially for VLSI CMOS, Vee decoupling is critical. CHMOS draws UNUSED PINS Interface Noise Margin for Vee = 5V Logic Low VIL-VOL Logic High VOH-VIH 74HCto 74HC 0.9V 1.4V LSTTL to LSTTL 0.3V 0.7V LSTTL to 74HCT 0.3V 0.7V LSTTL to 80C51 BH 0.3V 0.7V 74HCt080C51BH O.SV 3.0V SOC51BH to 74HC O.SV 1.0V Figure 2. Noise Margins for CMOS and LS TTL Circuits CMOS input pins should not be left to float, but should always be pulled to one logic level or the other. If they float, they tend to float into the transition region between 0 and I, where the pullup and pulldown devices in the input buffer are both conductive. This causes a significant increase in ICC. A similar effect exists in HMOS circuits, but with less noticeable results. In 80C51BH and 80C31BH designs, unused pins of Ports 1, 2, and 3 can be.ignored, because they have internal pullups that will hold them at a valid Logic 1 level. Port 0 pins are different, however, in not having internal pullups (except during bus operations). When the 80C51BH is in reset, the Port 0 pins are in a float state unless they are externally pulled up or down. If it's going to be held in reset for just a short time, the transient float state can probably be ignored. When it comes out of reset, the pins stay afloat unless 2-192 AP-252 they are externally pulled either up or down. Alternatively, the software can internally write Os to whatever Port 0 pins may be unused. The same considerations are applicable to the 80C3IBH with regards to reset. But when the 80C3lBH comes out of reset, it commences bus operations, during which the logic levels at the pins are always well defined as high or low. Consider the 80C3IBH in the Power Down or Idle modes, however. In those modes it is not fetching instructions, and the Port 0 pins will float if not externally pulled high or low. 1'he choice of whether to pull them high or low is the designer's. Normally it is sufficient to pull them up to Vee with 10k resistors. But if power is going to be removed from circuits that are connected to the bus, it will be advisable to pull the bus pins down (normally with 10k resistors). Considerations involved in selecting pullup and pulldown resistor values are as follows. vee PULLUP RESISTORS If a pullup resistor is to be used on a Port 0 pin, its minimum value is determined by IOL requirements. If the pin is trying to emit a 0, then it will have to sink the current from the pullup resistor plus whatever other current may be sourced by other loads connected to the pin, as shown in Figure 3a, while maintaining a valid output low (VOL)' To guarantee that the pin voltage will not exceed 0.45V, the resistor should be selected so that IOL doesn't exceed the value specified on the data sheet. In most CMOS applications, the minimum value would be about 2k n. The maximum value you could use depends on how fast you want the pin to pull up after bus operations have ceased, and how high you want the VOH level to be. The smaller the resistor the faster it pulls up. Its effect on the VOH level is that VOH = Vee - (ILl + IIH) X R. ILl is the input leakage current to the Port 0 pin, and IIH is the input high current to the external loads, as shown' in Figure 3b. Normally VOH can be expected to reach 0.9 Vee if the pullup resistance does not exceed about 50k n. 80e51BH R ..JQh. ....!!!:... po.x 1-------E~1Ef~ll vee IOl=R+ lIl 270068-1 Figure 3a. Conditions defining the minimum value for R. PO.X is emitting a logic low. R must be large enough to not cause IOL to exceed data sheet specifications. Pulldown Resistors If a pulldown resistor is to be used on a Port 0 pin, ,its minimum value is determined by VOH requirements during bus operations, and its maximum value is in most cases determined by leakage current. During bus operations the port uses internal pullups to emit Is. The D.C. Characteristics in the data sheet list guaranteed VOH levels for given IOH currents. (The "-" sign in the IOH value means the pin is sourcing that current to the external load, as shown in Figure 4,) To ensure the VOH level listed in the data sheet, the resis- Yep: 80C51BH 80C51BH R ..J!!!.. ~ pO.x: .... ...!!!i. .J!d... ----;r_--- po.x r----<----ExL.-g:lI~rL E~-g::C:L R YOH = yce -(IL.l + IIH) ~ xR IOH 270068-2 = YOH + IIH R 270068-3 Figure 3b. Conditions defining the maxilTlum value for R. PO.X is in a high impedance state. R must be small enough to keep VOH acceptably high. Figure 4a. Conditions defining the minimum value for R. PO.X is emitting a 1 in a bus operation. R must be large enough to not cause IOH to exceed data sheet specifications. 2-193 AP-252 VOH I I 1'1+ IIHS:: IOH DRIVE CAPABILITY OF THE INTERNAL PULLUPS tor has to satisfy where IIH is the input high current to the external loads. When the pin goes into a high impedance state, the pulldown resistor will have to sink leakage current from the pin, plus whatever other current may be sourced by ,other loads connected to the pin, as shown in Figure 4b. The Port 0 leakage, current is ILl on the data sheet. The resistor should be selected so that the voltage developed across it by these currents will be seen as a logic low by whatever circuits are connected to it (including the 80CSIBH). In CMOS/CHMOS applications, SOk n is normally a reasonable maximum value. aOCS1BH ~ Po.xt---_---- E~1J':JitL R VOL =(Ill + IIL)xR 270068-4 Figure 4b. Conditions defining the maximum value for R. PO.X is in a high impedance state. R must be small enough to keep VOL acceptably low. There's an important difference between HMOS and CHMOS port drivers. The pins of Ports 1,2, and 3 of the CHMOS parts each have three pullups: strong, normal, and weak, as shown in Figure S. The strong pullup (p I) is only used during O-to-l transitions, to hasten the transition. The weak pullup' (p2) is on whenever the bit latch contains a 1. The "normal" pullup (p3) is controlled by the pin voltage itself. The reason that p3 is controlled by the pin voltage is that if the pin is being used as an input, and the external source pulls it to a low, then turning offp3 makes for a lower IlL. The data sheet shows an "ITL" specification. This is the current that p3 will source during the time the pin voltage is making its I-to-O transition. This is what IlL would be if an input low at the pin didn't tum, p3 off. Note, however, that this p3 tum-off mechanism puts a restriction on the drive capacity of the pin if it's being used as an output. If you're trying to output a logic high, and the external load pulls the pin voltage below the pin's YIHMIN spec, p3 might tum off, leaving only the weak p2 to provide drive to the load. To prevent this happening, you need to ensure that the load doesn't draw more than the IOH spec for a valid YOH. The idea is to make sure the pin voltage never falls below its own YIHMIN specification. VCC VCC VCC Q FROM PORT LATCH READ PORT PIN 270068-5 Figure 5. 80C51BH Output Drivers for Ports 1, 2 and 3 2-194 AP-252 POWER CONSUMPTION The main reason for going to CMOS, of course, is to conserve power. (There are other reasons, but this is the main one.) Conserving power doesn't mean just reducing your electric bill. Nor does it necessarily relate to battery operation, although battery operation without CMOS is pretty unhandy. The main reason for conserving power is to be able to put more functionality into a smaller space. The reduced power consumption allows the use of smaller and lighter power supplies, and less heat being generated allows denser packaging of circuit components. Expensive fans and blowers can usually be eliminated. A cooler running chip is also more reliable, since most random and wearout failures relate to die temperature. And finally, the lower power dissipation will allow more functions to be integrated onto the chip. The reason CMOS consumes less power than NMOS is that when it's in a stable state there is no path of conduction from Vee to Vss except through various leakage paths. CMOS does draw current when it's changing states. How much current it draws depends on how often and how quickly it changes states. \ ~ SIINN:;USOIDAL ~ CLOCK SIGNAL --Y . IY -l.SMHz RECTANGULAR CLOCK SIGNAL CLOCK FREQ 270068-6 CMOS circuits draw current in sharp spikes during logical transitions. These current spikes are made up of two components. One is the current that flows during the transition time when pullup and pulldown FETs are both active. The average (DC) value of this component is larger when the transition times of the input signals are longer. For this reason, if the current draw is a critical factor in the design, slow rise and fall times should be avoided, even when the system speed doesn't seem to justify a need for nanosecond switching speeds. The other component is the current that charges stray and load capacitance at the nodes of a CMOS logic gate. The average value of this current spike is its area (integral over time) multiplied by its rep rate. Its area is the amount of charge it takes to raise the node capacitance, C, to Vee. That amount of charge is just C x Vee. So the average value of the current spike is C x Vee x f; where f is the clock frequency. This component of current increases linearly with clock frequency. For minimal current draw, the 80C52BH-2 is spec'd to run at frequencies as low as 500 kHz. Keep in mind, though, that other component of current that is due to slow rise and fall times. A sinusoid is not the optimal waveform to drive the XTALI pin with. Yet crystal oscillators, including the one on the 80C51BH, generate sinusoidal waveforms. Therefore, if the on-chip oscillator is being used, you can expect the device to draw more current at 500 kHz, than it does at 1.5 MHz, as shown in Figure 6. If you derive a good sharp square wave from an external oscillator, and use that to drive XTALl, then the microcontroUer will draw less current. But the external oscillator will probably make up the difference. The 80C5IBH has two power-saving features not available in the HMOS devices. These are the Idle and Power Down modes of operation. The on-chip hardware that implements these reduced power modes is shown in Figure 7. Both modes are invoked by software. Figure 6. 80C51BH ICC vs. Clock Frequency CPU INTERRUPT SERIAL PORT TIMER/COUNTERS 270068-7 Figure 7. Oscillator and Clock Circuitry Showing Idle and Power Down Hardware 2-195 inter AP-252 Idle: In the Idle Mode (IDL = 0 in Figure 7), the CPU puts itself to sleep by gating off its own clock. It doesn't stop the oscillator. It just stops the internal clock signal from getting to the CPU. Since the CPU draws SO to 90 percent of the chip's power, shutting it off represents a fairly significant power savings. The on-chip periperals (timers, serial port, interrupts, etc.) and RAM continue to function as normal. The CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during Idle. There are two ways to terminate Idle. Activation of any enabled interrupt will cause the hardware to clear bit 0 of the PCON register, terminating the Idle mode. The interrupt will be serviced, and following RET! the next instruction to be executed will be the one following the instruction that .invoked Idle. The other way is with a hardware reset. Since the clock oscillator is still running, RST only needs to be held active for two machine cycles (24 oscillator periods) to complete the reset. Note that this exit from Idle writes Is to all the ports, initializes all SFRs to their reset values, and restarts program execution from location O. The Idle Mode is invoked by setting bit 0 (IDL) of the PCON register. PCON is not bit-addressable, so the bit has to be set by a byte operation, such as Power Down: In the Power Down Mode (PD = 0 in Figure 7), the CPU puts the whole chip to sleep by turning off the oscillator. In case it was running from an external oscillator, it also gates off the path to the internal phase generators, so no internal clock is generated even if the external oscillator is still running. The on-chip RAM, however, saves its data, as long as Vee is maintained. In this mode the only Icc that flows is leakage, which is normally in the micro-amp range. ORL PCON.#l The PCON register also contains flag bits GFO and GFl, which can be used for any general purposes, or to give an indication if an interrupt occurred during normal operation or during Idle. In this application, the instruction that invokes Idle also sets one or both of the flag bits. Their status can then be checked in the interrupt routines. The Power Down Mode is invoked by setting bit 1 in the PCON register, using a byte instruction such as While the device is in the Idle Mode, ALE and PSEN emit logic high (VOH), as shown in Figure S. This is so external EPROM can be deselected and have its output disabled. ORL While the device is in Power Down, ALE and PSEN emit lows (VOL), as shown in Figure S. The reason they are designed to emit lows is so that power can be removed from the rest of the circuit, if desired, while the SOCS5IBH is in its Power Down mode. The port pins hold the logical states they had at the time the Idle was activated. If the device was executing out of external program memory, Port 0 is left in a high impedance state and Port 2 continues to emit the high byte of the program counter (using the strong pullups to emit Is). If the device was executing out of internal program memory, Ports 0 and 2 continue to emit whatever is in the PO and P2 registers. PSENI The port pins continue to emit whatever data was written to them. Note that Port 2 emits its P2 register data even if execution was from external program memory. External Execution Internal Execution Pin ALE PCON.#2 Idle Power Down Idle Power Down 1 0 1 0 1 0 1 0 PO SFR Data SFR Data High-Z High-Z P1 SFR Data SFR Data SFR Data SFR Data P2 SFR Data SFR Data PCH SFR Data P3 SFR Data SFR Data SFR Data SFR Data Figure 8. Status of Pins iO Idle and Power Down Modes. "SFR data" means the port pins emit their internal register data. "PCH" Is the high byte of the Program Counter. 2-196 AP-252 Port 0 also emits its PO register data, but if execution was from external program memory, the PO register data is FF. The oscillator is stopped, and the part remains in this state as long as Vee is held, and until it receives an external reset signal. The only exit from Power Down is a hardware reset. Since the oscillator was stopped, RST must be held active long enough for the oscillator to re-start and stabilize. Then the reset function initializes all the Special Func'tion Registers (ports, timers, etc.) to their reset values, and re-starts the program from location O. Therefore, timer reloads, interrupt enables, baud rates, port status, etc. need to be re-established. Reset does not affect the content of the on-chip data RAM. If Vee was held during Power Down, the RAM data is still good. USING THE POWER DOWN MODE The software-invoked Power Down feature offers a means of reducing the power consumption to a mere trickle in systems which are to remain dormant for some period of time, while retaining important data. The user should give some thought to what state the port pins should be left in during the time the clock is stopped, and write those values to the port latches before invoking Power Down. If Vee is going to be held to the entire circuit, one would want to write values to the port latches that would deselect peripherals before invoking Power Down. For example, if external memory is being used, the P2 SFR should be loaded with a value which will not generate an active chip select to any memory device. In some applications, Vee to part of the system may be shut off during Power Down, so that even quiescent and standby currents are eliminated. Signal lines that connect to those chips must be brought to a logic low, whether the chip in question is CMOS, NMOS, or TTL, before Vee is shut off to them. CMOS pins have parasitic pn junctions to Vee, which will be forward biased if Vee is reduced to zero whfle the pin is held at a logic high. NMOS pins often have FETs that look like diodes to Vee. TTL circuits may actually be damaged by an input high if Vee = O. That's why the 80C51BH outputs lows at ALE and PSEN during Power Down. Figure 9 shows a circuit that can be used to turn Vee off to part of the system during Power Down. The circuit will ensure that the secondary circuit is not de-energized until after the 80C31BH is in Power Down, and that the 80C3lBH does not receive a reset (terminating the Power Down mode) before the secondary circuit is re-energized. Therefore, the program memory itself can be part of the secondary circuit. VCCI CI 1,..1 R VCC2 1,..1 20K 270068-8 Figure 9. The 80C318H de-energizes part of the circuit (VCC2) when it goes into Power Down. Selections of Rand Q2 depend on VCC2 current draw. 2-197 AP-252 In Figure 9, when Vee is switched on to the 80C3lBH, 'capacitor CI provides a power-on reset. The reset function writes Is to all the port pins. The 1 at P2.6 turns Qlon, enabling Vee to the secondary circuit through transistor Q2. As the 80C31 BH comes out of reset, Port 2 commences emitting the high byte of the Program Counter, which results in the P2.7 and P2.6 pins outputting Os. The 0 at P2.7 ensures continuation of Vee to the secondary circuit. The system software must now write·a I to P2.7 and a 0 to P2.6 in the Port 2 SFR, P2. These values will not appear at the Port 2 pins as long as the device is retching instructions from external program memory. However, whenever the 80C31BH goes into Power Down, these values will appear at the port pins, and will shut off both' transistors, disabling Vee to the secondary circuit. Closing the switch Sire-energizes the secondary circuit, and at the same time sends a reset through C2 to the 80C3lBH to wake it up. The diode DI is to prevent CI from hogging current from C2 during this'secondary reset. D2 prevents C2 from discharging through the RST pin when Vee to the secondary .circuit goes to zero. ~, J' ::::--'VIh--"'-"""-~1_ 270068-9 a. Using a pFET +12V USING POWER MOSFETs to CONTROL Vee Power MOSFETs are gaining in popularity (and availability), The easiest way to control Vee is with a Logic Level pFET, as shown in .Figure lOa. This circuit allows the full Vee to be used to turn the device on. Unfortunately, power pFETs are not economically competitive with bipolar transistors of comparable ratings. Power nFETs are both economical and available, and can be used in this application if a DC supply of higher voltage is available to drive the gate. Figure lOb shows how to implement a Vee switch using a power nFET and a (nominally) + 12V supply. The problem here is that if the device is on, its source voltage is + SV. To maintain the on state, the gate has to be another 5 or lOY above that. The "12V" supply is not particularly critical. A miniinally filtered, unregulated rectifier will suffice, BATTERY BACKUP SYSTEMS' Here we consider drcuits that normally draw po}Ver from the AC line, but switch to battery operation in the event 'of a power failure. We assume that in battery operation high-current loads will be allowed to die along with the AC power. The system may continue then with reduced functionality, monitoring a control transducer, perhaps, or driving an LCD. Or it may go into a bare-bones survival mode, in which critical data is saved but nothing else happens till AC power is restored. In any case it is necessary to have some early warning of an impending power failure so that the system can arrange an orderly transfer to battery power. Early warning systems can operate by monitoring either the AC line voltage or the unregulated rectifier output, or even by monitoring the regulated DC voltage. . Monitoring the AC line voltage gives the earliest warning. That way you can know within one or two half-cycles of line frequency that AC power is down. In most cases you then have at least another half-cycle of line frequency before the regulated Vee starts to fall. In a half-cycle of line frequency an 80CSIBH can execute about 5,000 instructions-plenty of time to arrange an orderly transfer of power. 12K 2N3904 P2.7'-'lM,--...,..-_---1 P2.6 270068-28 b. Using an nFET Figure 10. Using Power MOSFETs to Control VCC2 The circuit in Figure II uses a Zener diode to test the line voltage each half-cycle, and a junction transistor to pass the information on to the 80CS lBH. (Obviously a voltage comparator with a suitable reference source can 2-198 AP-252 ~II~ VCC2 = BACKUP :::=:BATTERY VCC 80C51BH 80C31BH <-i I-~----t INTO .011'1 VSS 270068-10 Figure 11. Power Failure Detector with Battery Backup. When AC power falls, VCC1 goes down and VCC2 is held. perform the same function, if one prefers.) The way it works is if the line voltage reaches an acceptably high level, it breaks over Zl, drives Ql to saturation, and interrupts the 80C5IBH. The interrupt would be transition-activated, in this application. The interrupt service routine reloads one of the C5IBH's timers to a value that will make it roll over in something between one and two half-cycles of line frequency. As long as the line voltage is healthy, the timer never rolls over, because it, is reloaded every half-cycle. If there is a single half-cycle in which the line voltage doesn't reach a high enough level to generate the interrupt, the timer rolls over and generates a timer interrupt. The timer interrupt then commences the transition to battery backup. Critical data needs to be copied into protected RAM. Signals to circuits that are going to lose power must be written to logic low. Protected circuits (those powered by Vee2) that communicate with unprotected circuits must be deselected. The microcontroller itself may be put into Idle, so that it can continue some level of interrupt-driven functionality, or it may be put into Power Down. Note that if the CPU is going to invoke Power Down, the Special Function Registers may also need to be copied into protected RAM, since the reset that terminates the Power Down mode will also intialize all the SFRs to their reset values. The circuit in Figure II does not show a wake-up mechanism. A number of choices are available, however. A pushbutton could be used to generate an interrupt, if the CPU is in Idle, or to activate reset, if the CPU is in Power Down. Automatic wake-up on power restoration is also possible. If the CPU is in Idle, it can continue to respond to any interrupts that might be generated by QI. The interrupt service routine determines from the status of flag bits GFO and GFI in PCON that it is in Idle because there was a power outage. It can then sample Veel through a voltage comparator similar to ZI, Ql in Figure 11. A satisfactory level of Veel would be indicated by the transistor being in saturation. But perhaps you can't spare the timer that is the key to the operation of the circuit in Figure 11. In that case a retriggerable one-shot, triggered by the AC line voltage, can perform essentially the same function. Figure 12 shows an example of this type of power failure detector. A retriggerable one-shot (one halfofa 74HC123) monitors the AC line voltage through transistor Q 1. Q I retriggers the one-shot every half-cycle of line frequency. If the output pulse width is between one and two halfcycles of line frequency, then a single missing or low half-cycle will generate an active low warning flag, which can be used to interrupt the microcontroller. The interrupt routine takes care of the transition to battery backup. From this point Veel mayor may not actually drop out. The missing half-cycle of line voltage that caused the power down sequence may have been nothing more than a short glitch. If the .i\C line comes back strong enough to trigger the one-shot while Vee I is still up (as indicated by the state of transistor Q2), then the other half of the 74HCI23 will generate a wake-up signal. 2-199 intJ .AP-252 VCC2 VCC1 BACKUP BATTERY 1/1/1/1 20K 12K 12K 1,.1 47K VCC2 . A 1f.!74HC123 VCC Q RIC CLR C Q WAKE-iiP Q WAKE-UP B A V99 1f.!74HCl23 iNTo (BOC51BH) 270068-11 Figure 12. Power Failure Detector uses retriggerable one-shots to flag Impending power outage and generate automatic wake-up when power returns. . Having been awakened, the 80C5IBH will stay awake for at least another half-cycle of line frequency (another 5,000 or so instructions) before possibly being told to arrange another transfer of power. Consequently, if the line voltage is. jittering erratically around the switchover point (determined by diode Zl), the system will limp along ex.ecuting in half-cycle ,units of line frequency. POWER SWITCHOVER CIRCUITS Battery backup systems need to have a way for the protected circuits to draw power from the line-operated power supply when that source is available; and to switch over to battery power when required. The switchover circuit is simple if the entire system is to be battery powered in the event of a line power outage. In that case a pair of diodes suffice, as shown in Figure 12, provided VccMIN specs are still met after the diode drop has been subtracted from its respective power source. On the other hand, if the power outage is real and lengthy, Veel will eventually fall below the level at which the backup battery takes over. The backup battery maintains power to the 8OC5IBH, and to the 74HC123, and to whatever other circuits are being protected during this outage. The battery voltage must be high enough to maintain VcCMIN specs to the 80C5IBH. The situation becomes more complicated when part of the circuit is going to be allowed to die when the AC power goes out. In that case it is difficult to maintain equal Vccs to protected and unprotected circuits (and possibly dangerous not to). If the microcontroller is an 80C3l BH, executing out of external ROM, and if the C3IBH is put into Idle during the power outage, then the external ROM must also be supplied by the battery. On the other hand, if the C31BH is put into Power Down during the outage, then the ROM can be allowed to die with the AC power. The considerations here are the same as in Figure 9: Vee to the ROM is still up at the time Power Down is invoked, and we must ensure (through selection of diode Z2 in Figure 12) that the 80C3IBH is not awakened till ROM power is back in spec. The problem can be alleviated by using a Schottky diode instead of a lN400l, for its lower forward voltage drop. The lN5820, for example, has a foward drop of about O.35V at lAo Other solutions are to use a transistor or power MOSFET switch, as shown in Figure 13. With minor modifications this switch can be controlled by port pins. 2-200 inter AP-252 VCC2 vcel I1 270068-27 a. Using a pnp Transistor VCC2 -TILril ~ II 270068-12 b. Using a Power MOSFET Figure 13. Power Switchover Ckts. 80C31BH + CHMOS EPROM The 27C64 and 87C64 are Intel's 8K byte CHMOS EPROMs. The 27C64 requires an external address latch, and can be used with the 80C3IBH as shown in Figure 14a. In most 8031 + 2764 (HMOS) appli- cations, the 2764's Chip Enable (CE) pin is hardwired to ground (since it's normally the only program memory on the bus). This can be done with the CHMOS versions as well, but there is some advantage in connecting CE to ALE, as shown in Figure 14a. The advantage is that if the 80C3IBH is put into Idle mode, since ALE goes to a 1 in that 'mode, the 27C64 will be deselected and go into a low current standby mode. The timing waveforms for this configuration are shown in Figure 14b. In Figure 14b the signals and timing parameters in parenthesis are those of the 27C64, and the others are of the 80C31BH, except Tprop is a parameter of the address latch. The requirements for timing compatibility are TAVIV - Tprop > tACC TLlIV> tCE TPLlV> tOE TPXIZ> tDF If the application is going to use the Power Down mode then we have another consideration: In Idle, ALE = PSEN = I, and in Pow~r Down, ALE = PSEN = O. In a realistic application there are likely to be more chips in the circuit than are shown in Figure 14, and it is likely that the nonessential ones will have their Vee removed while the CPU is in Power Down. In that case the EPROM and the address latch should be among the chips that have Vee removed, and logic lows are exactly what are required at ALE and PSEN. But if Vee is going to be maintained to the EPROM during Power Down, then it will be necessary to de- PSENr---------------------~Oi 270068-26 Figure 14a. 80C31BH 2-201 + 27C64 intJ AP-252 The 87C64 is like the 27C64 except that it has an onchip address latch. The Port 0 pins are tied to both address and data pins of the 87C64, as shown in Figure 16a. ALE drives the EPROM's ALE/CS input. During ALE high, the address information is allowed to flow into the EPROM and begin accessing the code byte. On the falling edge of ALE the address byte is internally latched. The AO-A7 inputs are then ignored and the same bus lines are used to transmit the fetched code .byte from the 00-07 pins back to the 80C31 BH. The timing waveforms for this configuration are shown in Figure 16b. In Figure 16b the signals and timing parameters in parentheses are those of the 87C64, and the others are of the 80C31BH. The requirements for timing compatibility are 270068-13 Figure 14b. Timing Waveforms for aoC31BH . 27C64 TLHLL> tLL + TAVLL> tAL TLLAX> tLA select the EPROM when the CPU is in Power Down. If Idle is never invoked, CE of the EPROM can be connected to P2.7 of the 80C31BH, as shown in Figure 15a. In normal operation, P2.7 will be emitting the MSB of the Program Counter, which is 0 if the program contains less than 32K of code. '!)ten when the CPU goes into Power Down, the Port 2 pins emit P2 SFR data, which puts a 1 at P2.7, thus deselecting the . EPROM. If Idle and Power Down are both going to be used, CE of the EPROM can be driven by the logical OR of ALE and P2.7, as shown in Figure 15b. In Idle, ALE = 1 will deselect the EPROM, and in Power Down, P2.7 = 1 will deselect it. TLLlV> tACL TPLlV> tOE TLLPL> tCOE TPXIZ> tOHZ The same considerations apply to the 87C64 as to the 27(:64 with regards to the Idle and Power Down modes. Basically you want CS = 1 if Vee is maintained to the EPROM, and CS = OE = 0 if Vee is . removed. SCANNING A KEYBOARD CE P2.7 OOCmBH-----------~~27~64 270068-14 a. Power Down is used but not Idle. 01 80C31BH {ALE~. _ CE P2.7~ 27':164 270068-15 b. Idle and Power Down both used. Figure 15. Modifications to 80C31BH/27C64 Interface Pulldown resistors are shown in Figure 14a under the assumption that something on the bus is going to have its Vee removed during Power Down. If this is not the case~ pullups can be used as well as pulldowns. There are many different kinds of keyboards, but alphanumeric keyboards generally consist of a matrix of 8 scan lines and 8 receive lines as shown in Figure 17. Each set of lines connects to one port of the microcontroller. The software has written Os to the scan lines, and Is to the receive lines. Pressing a key connects a scan line to a receive line, thus pulling the receive line to a logic low. The 8 receive lines are ANDed to one of the external interrupt pins, so that pulling any of the receive lines low generates an interrupt. The interrupt service routine has to identify the pressed key, if only one key is down, and convert that information to some useful output. If more than one key in the line matrix is found to be pressed, no action is taken. (This is a "two key lockout" scheme.) 2-202 inter Ap·252 On some keyboards, certain keys (Shift, Control, Escape, etc.) are not a part of the line matrix. These keys would connect directly to a port pin on the microcontroller, and would not cause lock-out if pressed simultaneously with a matrix key, nor generate an interrupt if pressed singly. Normally the microcontroller would be in idle mode when a key has not been pressed, and another task is not in progress. Pressing a matrix key generates an in- r 10K PO terrupt, which terminates the Idle. The interrupt service routine would first call a 30 ms (or so) delay to debounce the key, and then set about the task of identifying which key is down. First, the current state of the receive lines is latched into an internal register. If a single key is down, all but one of the lines would be read as Is. Then Os are written to the receive lines and Is to the scan lines, and the scan lines are read. If a single key is down, all but one of XS /s ~ 0,,-07 S7C64 SOC31BH 1s P2 /5 -" / Ao- A7 ) A,.-A'2 ALE CE PSEN OE 270068-16 Figure 16a. 80C31BH + 87C64 270068-17 Figure 16b. Timing Waveforms for 80C31BH 2-203 + 87C64 inter AP-252 RESPONSE_TO_KEY_CLOSURE: CALL DEBOUNCE_DELAY MOV LINE, PI; ;See Figure 17. CALL SCAN DJNZ ZERO_COUNTER ,REJECT MOV ADDRESS ,ZERO_BIT MOV P2,#OFFH; ;See Figure 17. MOV P1,#0 MOV LINE,P2 CALL SCAN DJNZ ZERO_COUNTER ,REJECT XCH A,ZERO_BIT SWAP A ORL' ADDRESS ,A XCH A,ZERO_BIT MOV P1,#OFFH MOV P2,#O REJECT: CLR EXO RETI these lines would be read as Is. By locating the single 0 in each set of lines, the pressed key-can be identified. If more than one matrix key is down, one or both sets of lines will contain multiple Os. A subroutine is used to determine which of 8 bits in either set of lines is 0, and whether more than one bit is O. Figure 18 shows a subroutine (SCAN) which does that using the 8051 's bit-addressing capability. To use the subroutine, move the line data into a bit-addressable RAM location named LINE, and call the SCAN routin~. The number of LINE bits which are zero is returned in ZERO_COUNTER. If only one bit is zero, its number (1 through 8) is returned in ZERO_ BIT. The interrupt service routine that is executed in response to a key closure might then be as follows: SCAN UNES ._---A.----_, - rC RECEIVE UNES '-'--- 80C51BH f---" i------" PI P2 INTO 270068-18 Figure 17. Scanning a Keyboard 2-204 AP-252 SCAN: ONE: TWO: THREE: FOUR: FIVE: SIX: SEVEN: EIGHT: ZEROSOUNTER, .0 LINE. 0, ONE ZERO_COUNTER ZERO_BIT, .1 LINE.I,TWO ZEROSOUNTER ZERO_BIT,82 LINE.2,THREE ZERO_COUNTER ZERO_BIT,83 LINE. 3, FOUR ZERO_COUNTER ZERO_B IT, .4 LINE. 4, FIVE ZEROSOUNTER ZERO_B IT, .5 LINE.5,SIX ZERO_COUNTER ZERO_B IT, 86 LINE. 6, SEVEN ZERO_COUNTER ZERO_BIT,87 LINE. 7, EIGHT ZERO_COUNTER ZERO_BIT, fiB MOV .JB INC MOV .JB INC MOV .JB INC MOV .JB INC MOV .JB INC MOV .JB INC MOV JB INC MOV JB INC MOV RET ZERO_COUNTER counts the number of Os in LINE. Tost LINE bit O. If LINE 0 = 0, inc~ement ZERO_COUNTER and record that line number I is active. Procedure continues for other LINE bits. Line number 2 is active. Line number :3 is active. Line number 4 is active. Line number 5 .. active. Line number 6 is active Line number 7 is active. Line number B is active. 270068-19 Figure 18. Subroutine SCAN Determines Which of 8 Bits in LINE is Zero Notice that RESPONSE_TO_KEY_CLOSURE does not change the Accumulator, the PSW, nor any of the registers RO through R7. Neither do SCAN or DEBOUNCE_DELAY. What we corne out with then is a one-byte key address (ADDRESS) which identifies the pressed key. The key's scan line number is in the upper nibble of ADDRESS, and its receive line number is in the lower nibble. ADDRESS can be used in a look-up table to generate a key code to transmit to a host computer, andlor to a display device. The keyboard interrupt itself must be edge-triggered, rather than level-activated, so that the interrupt routine is invoked when a key is pressed, and is not constantly being repeated as long as the key is held down. In edgetriggered mode, the on-chip hardware clears the interrupt flag (EXO, in this case) as the service routine is being vectored to. In this application, however, contact bounce will cause several more edges to occur after the service routine has been vectored to, during the DEBOUNCE~ELA Y routine. Consequently it is necessary to clear EXO again in software before executing RETI. . The debounce delay routine also takes advantage of the Idle mode. In this routine a timer must be preloaded with a value appropriate to the desired length of delay. This would be For example, with a 3.58 MHz oscillator frequency, a 30 ms delay could be obtained using a preload value of - 8950, or DDOA, in hex digits. In the debounce delay routine (Figure 19), the timer interrupt is enabled and set to a higher priority than the keyboard interrupt, because as we invoke Idle, the keyboard interrupt is still "in progress". An interrupt of the same priority will not be acknowledged, and will not terminate the Idle mode. With the timer interrupt set to priority I, while the keyboard interrupt is a priority 0, the timer interrupt, when it occurs, will be acknowledged and will wake up the CPU. The timer interrupt service routine does not itself have to do anything. The service routine might be nothing more than a single RETI instruction. RET! from the timer interrupt service routine then returns execution to the debounce delay routine, which shuts down the timer and returns execution to the keyboard service routine. DRIVING AN LCD An LCD (Liquid Crystal Display) consists of a backplane and any number of segments or dots which will be used to form the image being displayed. Applying a voltage (nominally 4 or 5V) between any segment and the backplane causes the segment to darken. The only catch is that the polarity of the applied voltage has to be periodically reversed, or else a chemical reac- . I d (osc kHz) x (delay time ms) timer pre oa = 12 , 2-205 intJ AP-252 DEBOUNCE_DELAV: MOV , . TL!, ITL! J'RELOAD , Preload law bvte. MOV TH1, ltTHIJ'RELOAD , PTeload high b~te. Enable Timer 1 inteT'T'upt. SETB ETI Set Timer 1 interrupt to hlgh pT'ioT'ity. SETB PTI Start tlmer 1'unning. SETB TRI ORL peON, II Invoke Idle mode. The next instruction wl11 not be executed until' the delay time'l out. CLR CLR CLR RET TRI PTI ETI Stop th e t 1me". Back to priority 0 (if desired). Disable Timer 1 inter1'upt (if desired>. Continue keyboard scan. 270068-20 Figure 19. Subroutine DEBOUNCE_DELAY Puts the 80C51BH into Idle During the Delay Time tasks are not requiring servicing. When the timer rolls over it generates an interrupt, which brings the 80CSIBH out ofldle. The service routine reloads the timer (for the next rollover), and inverts the logic levels of all the pins that are connected to the LCD. It might look like this: tion takes place in the LCD which causes deterioration and eventual failure of the liquid crystal. To prevent this happening, the backplane and all the segments are driven with an AC signal, which is derived from a rectangular voltage waveform. If a segment is to be "oft" it is driven by the same waveform as the backplane. Thus it is always at backplane potential. If the segment is to be "on" it is driven with a waveform that is the inverse of the backplane waveform. Thus it has about 5V of periodically changing polarity between it and the backplane~ LCD_DRIVE_INTERRUPT: MOV TL1.#LOW( - XTAL_FREQ) MOV TH1.#HIGH( - XTAL_FREQ) XRL TENS_DIGIT.#OFFH XRL ONES_DIGIT.#OFFH RETI With a little software overhead, the 80C51BH can perform this task without the need for additional LCD drivers. The only drawback is that each LCD segment uses up one port pin, and the backplane uses one more. If more than, say, two 7-segment digits are being driven, there aren't many port pins left for other tasks. Nevertheless, assuming a given application leaves enough port pins available to support this task, the considerations for. driving the LCD are as follows. Suppose, for example, it is a 2-digit display with a deci-' mal point. One port (TENS_DIGIT) connects to the 7 segments of the tens digit plus the backplane. Another port (ONES_DIGIT) connects to a decimal point plus . , the 7 segments of the ones digit. To update the display, one would use a look-up.table to generate the characters. In the table, "on" segments are represented as. Is, and "off" segments as Os. The backplane bit is represented as a 0.. The quantity to be displayed is stored in RAM as a BCD value. The look-up table operates on the low nibble of the BCD value, and produces the bit pattern that is to be written to either the ones digit or the tens digit. Before the new patterns can be written to the LCD, the LCD drive interrupt has to be disabled. That is to prevent a polarity reversal from taking place between the times the two digits are written. An update subroutine is shown in Figure 20. USING AN LCD DRIVER One of the 80C51 BH's timers is used to mark off halfperiods of the drive voltage waveform. The LCD drive waveform should have a rep ·rate between 30 and 100 Hz, but it's not very critical. A half-period of 12 ms will set the rep rate to about 42 Hz. The preload/reload value to get 12 ms to rollover is the 2's complement negative of the oscillator frequency in kHz: if the oscillator frequency is 3.58 MHz, the reload value is - 3580, or F204 in hex digits. Now, the 80C51BH would normally be in Idle, to conserve power, during the time that the LCD and other As was noted, driving an LCD directly with an 80C51BH uses a lot of port pins. LCD drivers are available in CMOS to interface an 80CS1BH to a 4-digit display using only 7 of the CS1BH's I/O pins. Basically, the C51BH tells the LCD driver what digit is to be displayed (4 bits) and what position it is to be displayed in (2 bits), and toggles a Chip Select pin to tell the driver to latch this information. The LCD driver generates the display characters (hex digits), and takes care of the polarity reversals using its own RC oscillator to generate the timing. 2-206 intJ AP-252 Figure 25 shows an 80CSlBH working with an ICM72IIM to drive a 4-digit LCD, and the software that updates the display. One could equally well send information to the LCD driver over the bus. In that case, one would set up the Accumulator with the digit select and data input bits, and execute a MOVX@ RO,A instruction. The LCD driver's chip select would be driven by the CPU's WR signal. This is a little easier in software than the direct bit manipulation shown in Figure 21. However, it uses more I/O pins, unless there is already some external memory involved. In that case, no extra pins are used up by adding the LCD driver to the bus. RESONANT TRANSDUCERS Analog transducers are often used to convert the value of a physical property, such as temperature, pressure, etc., to an analog voltage. These kinds of transducers then require an analog-to-digital converter to put the measurement into a form that is compatible with a digital control system. Another kind of transducer is now becoming available that encodes the value of the physical property into a signal that can be directly read by a digital control system. These devices are called resonant transducers. Resonant transducers are oscillators whose frequency depends in a known way on the physical property being measured. These devices output a train of rectangular pulses whose repetition rate encodes the value of the quantity being measured. The pulses can in most cases be fed directly into the 80CSlBH, which then measures either the frequency or period of the incoming signal, basing the measurement on the accuracy of its own clock oscillator. The 80C51BH can even do this in its sleep; that is, in Idle. UPDATE_LCD' CLR MOV MOV SWAP ANL MOVC MOV MOV ANL MOVC MOV MOV MOV SETB RET When the frequency or period measurement is completed, the CSlBH wakes itself up for a very short time to perform a sanity check on the measurement and convert it in software to any scaling of the measured quantity that may be desired. The software conversion can include corrections for nonlinearities in the transducer's transfer function. Resolution is also controlled by software, and can even be dynamically varied to meet changing needs as a situation becomes more critical. For example, in a process controller you can increase your resolution ("fine tune" the control, as it were) as the process approaches its target. The nominal reference frequency of the output signal from these devices is in the range of 20 Hz to SOO kHz, depending on the design. Transducers are available that have a full scale frequency shift 2 to 1. The transducer operates from a supply voltage range of 3V to 20V, which means it can operate from the same supply voltage as the 80CSlBH. At 5V, the transducer draws less than S rnA (Reference 7). It can normally be connected directly to one of the CSlBH's port pins, as shown in Figure 22. FREQUENCY MEASUREMENTS Measuring a frequency means counting pulses for a known sample time. Two timer/counters can be used, one to mark off the sample time and one to count pulses. If the frequency being counted doesn't exceed SO kHz or so, one may equally well connect the transducer signal to one of the external interrupt pins, and count pulses in software. That frees up one timer, with very little cost in CPU time. The count that is directly obtained is TxF, where T is the sample time and F is the frequency. The full scale ETI Disable LCD drive Interrupt. DPTR. #TABLE_ADDRESS A, BCD_VALUE A Look-up table begins at TABLE_ADDRESS A. lIOFH Digits to be displaqed. Move tens digit to low nibble Mask off high nibble Tens digit pattern to accumulator Update LCD tens digit. Digits to be displayed Mask of' tens digit A. (!A+DPTR Ones digit pattern to accumulator c. DEC lMAL]OJ NT Add decimal point to segment pattern. Update LCD dec imal pOint and ones digit Re-enable LCD drive 1nterrupt. A.IOFH A.@A+DPTR TENS_DIGIT. A A. BCD_VALUE ACC. 7. C ONES_DIGIT. A" ETI 270068-21 Figure 20. UPDATE_LCD Routine Writes Two Digits to an LCD 2-207 AP-252 range is Tx(Fmax-Fmin). For n-bit resolution For example, 8-bit resolution in the measurement of a frequency that varies between 7 kHz and 9 kHz would require, according to this formula, a sample time of 128 ms. The maximum acceptable frequency count would be 128 ms X 9 kHz = 1152 counts. The minimum would be 896 counts. Subtracting 896 from each frequency count (or presetting the frequency counter' to - 896 = OFC80H) would allow the frequency to be reported on a scale of 0 to FF in hex digits. 1 LSB = Tx(Fmax-Fmin) 2n Therefore the sample time required for n-bit resolution is 2n T = ""Fm-ax--F:::-m-i'-n aOC51BH ~,{ '\ 1 } DIGIT 2 SELECT M} PORT 81 82 L. C. D. '\ DATA INPUT 83 CS ." 270068-22 Figure 21a. Using an LCD Driver UPDATE_LCD: MOV SETa SETS CALL CLR CALL MOV CLR SETS CALL CLR CALL RET A. DISPLAY_HI DIGIT _SELECT_2 DIGIT _SELECT_1 SH I FT _AND _LOAD DIGIT _SELECT_1 SHIFT_AND_LOAD A.DISPLAY_LO DIGIT _SELECT_2 DIGlT_SELECT_1 SHIFT _AND_LOAD DIGIT_SELECT_1 SHIFT_ANO_LOAD High b~te of 4-dig.t disp1a~. Select leftmost digit 09 LCD. (Digit address = lIB. ) High nibble of high byte to selected digit Select second digit of LCD (address = 10D) Low nibble of high byte to selected digit. 4. Low by teo of 4-dlgit d1splay. Select third digit LCD. (Oig1t address = 01B. ) Hlgh nibble of low byte to seletted dLg!t. Select fourth digit (address = OOB), Low nibble of low byt,e to selec:ted dIgit. SHIFT _AN~L~OAD MOV DATA_iNPUT _B3. C MS8 to carr~ bit (CV) CV to Data Input pin 83. RLC A Next bit to CV. MOV A DATA_INPUT _B2. C tv to Data Input pin RLC A Next bit to CV MOV DATA_INPUT_BI.C CV to Data Input pin 91 Last bit to cv. CV to Data Input pin BO. Toggle Chip Select. O-to-l transition latches info. RLC A MOV DATA_INPUT _BO. C CHIP _SELECT CHIP _SELECT CLR SETB RET B2 270068-23 Figure 21b. UPDATE_LCD Routine Writes 4 Digits to an LCD Driver 2-208 AP-252 At this point the value of the frequency of the transducer signal, measured to 8 bit resolution, is contained in FREQUENCY. Note that the timer can be reloaded on the fly. Note too that the timer can be reloaded on the fly. Note too that for 8-bit resolution only the low byte of the frequency counter needs to be read, since the high byte is necessarily 0. However, one may want to test the high byte to ensure that it is zero, as a sanity check on the data. Both bytes, of course must be reloaded, VCC vcc tRESONANT TRANSDUCER t- aOC51BH INTO OR TO \-'" PERIOD MEASUREMENTS 270066-24 Figure 22. Resonant Transducer Does Not Require an AID Converter To implement the measurement, one timer is used to establish the sample time. The timer is preset to a value that causes it to roll over at the end of the sample time, generating an interrupt and waking the CPU from its Idle mode. The required preset value is the 2's complement negative of the sample time measured in machine cycles. The conversion from sample time to machine cycles is to mUltiply it by 1/12 the clock frequency. For example, if the clock frequency is 12 MHz, then a sample time of 128 ms is (128 ms) x (12000 kHz)/12 =' 128000 machine cycles. Measuring the period of the transducer signal means measuring the total elapsed time over a known Dumber, N, of transducer pulses. The quantity that is directly measured is NT, where T is the period of the transducer signal in machine cycles. The relationship between T in machine cycles and the transducer frequency F in arbitrary frequency units is Fxtal T = -F- x (1/12), where Fxtal is the 80C51BH clock frequency, in the same units as F. The full scale range then is Nx (Tmax-Tmin). For n-bit resolution. 1LSB= Then the required preset value to cause the timer to roll over in 128 ms is Therefore the number of periods over which the elapsed time should be measured is -128000 = FEOCOO, in hex digits. Note that the preset value is 3 bytes wide whereas the timer is only 2 bytes wide. This means the timer must be augmented in software in the timer interrupt routine tlil three bytes. The 80C5IBH has a DJNZ instruction (decrement and jump if not zero) that makes it easier to code the third timer byte to count down instead of up. If the third timer byte counts down, its·reload value is the 2's complement of what it would be for an up-counter. For example, if the 2's complement of the sample time is FEOCOO, then the reload value for the third timer byte would be 02, instead of FE. The timer interrupt routine might then be: TIMER_INTERRUPT_ROUTINE: DNJZ THIRD_TIMER_BYTE,OUT MOV TLO,#O MOV THO,#OCH MOV THIRD_TIMERBYTE,#2 MOV FREQUENCy,COUNTER_LO ;Preset COUNTER to -896: MOV COUNTER_LO,#80H MOV COUNTER_HI,#OFCH OUT: RETI Ns(Tmax-Tmin) 2" 2" N=--Tmax-Tmin However, N must also be an integer. It is logical to evaluate the above formula (don't forget Tmax and Tmin have to be in machine cycles) and select for N the next higher integer. This selection gives a period measurement that has somewhat more than n-bit resolution, but it can be scaled back if desired. For example, suppose we want 8-bit resolution in the measurement of the period of a signal whose frequency varies from 7.1 kHz to 9 kHz. If the clock frequency is 12 MHz, then Tmax is (12000 kHz/7.1 kHz) x (1/12) = 141 machine cycles. Tmin is II ~ machine cycles. The required value for N, then, is 256/(141-111) = 8.53 periods, according to the formula. Using N = 9 periods will give a maximum NT value of 141 x 9 = 1269 machine cycles. The minimum NT will be III X 9 = 999 machine cycles. A lookup table can be used to 2-209 inter AP-252 ADDC MOV CLR MOVC MOV POP POP RET scale these values back to a range of 0 to 255, giving precisely the 8-bit resolution desired. To implement the measurement, one timer is used to measure the elapsed time, NT. The transducer is connected to one of the external interrupt pins, and this interrupt is configured to the transition-activated mode. In the transition-activated mode every I-to-O transition in the transducer output will generate an interrupt. The interrupt routine counts transducer pulses, and when it gets to the predetermined N, it reads and clears the timer. For the specific example cited above, the interrupt routine might be: OUT: DJNZ MOV CLR CLR MOV MOV MOV MOV SETB SETB CALL RETI N,OUT N,#9 EA TRI NT_LO,TLI NT_HI,THI TLl,#9 THl,#O TRI EA LOOKUP_TABLE The subroutine LOOKUP-,-TABLE is used to scale the measurement back to the desired 8-bit resolution. It can also include built-in corrections for errors or nonlinearities in the transducer's transfer function. The subroutine uses the MOVC A, @ A + DPTR instruction to access the table, which contains 270 entries commencing at the 16-bit address referred to as TABLE. The subroutine must compute the address of the table entry that corresponds to the measured value of NT. This address is + NT - NTMIN, where NTMIN = 999, in this specific example. LOOKUP_TABLE: PUSH PUSH MOV ADD MOV MOV A,@A+DTPR PERIOD,A PSW ACC At this point the value of the period of the transducer signal, measured to 8 bit resolution, is contained in PERIOD. The 80C51BH timers have an operating mode which is particularly suited to pulse width measurements, and will be useful in these applications if the transducer signal has a fixed duty cycle. In this routine a pulse counter N is decremented from its preset value, 9, to zero. When the counter gefs to zero it is reloaded to 9. Then all interrupts are blocked for a short time while the timer is read and cleared. The timer is stopped during the read and clear operations, so "clearing" it actually means presetting it to 9, to make up for the 9 machine cycles that are missed while the timer is stopped. DPTR = TABL A PULSE WIDTH MEASUREMENTS INTERRUPT~RESPONSE: . A,NLHI DPH,A ACC PSW A,#LOW(TABLE-NTMIN) A,NT_LO DPL,A A,#HIGH(TABLE-NMTIN) In this mode the timer is turned on by the on-chip circuitry in response to an input high at the external interrupt pin, and off by an input low, and it can do this while the 80C5IBH is in Idle. (The "GATE" mode of timer operation is described in the Intel Microcontroller Handbook.) The external interrupt itself can be enabled, so the same I-to-O transition from the transducer that turns off the timer also generates an interrupt. The interrupt routine then reads and resets the timer. The advantage of this method is that the transducer signal has direct access to the timer gate, with the result that variations in interrupt response time have no effect on the measurement. Resonant transducers that are designed to fully exploit the GATE mode have an internal divide-by-N circuit that fixes the duty cycle at 50% and lowers the output frequency to the range of 250 to 500 Hz (to control RFI). The transfer function between transducer period and measurand is approximately linear, with known and repeatable error functions. HMOS/CHMOS Interchangeability The CHMOS version of the 8051 is architecturally identical with the HMOS version, but there are nevertheless some important differences between them which the designer should be aware of. In addition, some applications require. interchangeability between HMOS and CHMOS parts. The differenceS that need to be considered are as follows: External Clock Drive: To drive the HMOS 8051 with an external clock signal, one normally grounds the XTALI pin and drives the XTAL2 pin. To drive the CHMOS 8051 with an external clock signal, one must drive the XTALl pin and leave the XTAL2 pin unconnected. The reason for the difference is that in the 2-210 intJ AP-252 HMOS 8051, it is the XTAL2 pin that drives the internal clocking circuits, whereas in the CHMOS version it is the XTALl pin that drives the internal clocking circuits. CMOS~I!_ HMOS TTL VIH There are several ways to design an external clock drive to work with both types. For low clock frequencies (below 6 MHz), the HMOS 8051 can be driven in the same way as the CHMOS version, namely, through XTALI with XTAL2 unconnected. Another way is to drive both XTALl and XTAL2; that is, drive XTALl and use and external inverter to derive from XTALI a signal with which to drive XTAL2. In either case, a 74HC or 74HCT circuit makes an excellent driver for XTALI and/or XTAL2, because neither the HMOS nor the CHMOS XTAL pins have TTL-like input logic levels. Unused Pins: Unused pins of Ports I, 2 and 3 can be ignored in both HMOS and CHMOS designs. The internal pullups will put them into a defined state. Unused Port 0 pins in 8051 applications can be ignored, even if they're floating. But in 80C5IBH applications, these pins should not be left afloat. They can be externally pulled up or down, or they can be internally pulled down by writing Os to them. 8031/80C31BH designs mayor may not need pullups on Port O. Pullups aren't needed for program fetches, because in bus operations the pins are actively pulled high or low by either the 8031 or the external program memory. But they are needed for the CHMOS part if the Idle or Power Down mode is invoked, because in these modes Port 0 floats. Logic Levels: If Vee is between 4.5V and 5.5V, an input signal that meets the HMOS 8051's input logic levels will also meet the CHMOS 80C5IBH's input logic levels (except for XTALl/XTAL2 and RST). For the same Vee condition, the CHMOS device will re~ch or surpass the output logic levels of the HMOS device. The HMOS device will not necessarily reach the output logic levels of the CHMOS device. T~is is an impo~~nt consideration if HMOS/CHMOS mterchangeablhty must be maintained in an otherwise CMOS system. HMOS 8051 outputs that have internal pullups (Ports 1,2, and 3) "typically" reach 4V or more if IOH is zero, but not fast enough to meet timing specs. Adding an external pullup resistor will ensure the logic l~ve!, b~t still not the timing, as shown in Figure 23. If tImmg IS an issue, the best way to interface HMOS to CMOS is through a 74HCT circuit. 270068-25 Figure 23. O-to-1 Transition Shows Unspec'd Delay (Llt) in HMOS to 74HC Logic wishes to pre&erve the capability of interchanging HMOS and CHMOS 8051s the software has to be designed so that the HMOS parts will respond in an acceptable manner when a CHMOS reduced power mode is invoked. For example, an instruction that invokes Power Down can be followed by a "JMP $": CLR ORL JMP EA PCON.#2 $ The CHMOS and HMOS parts will respond to this sequence of code differently. The CHMOS part: going into a normal CHMOS Power Down Mode, will stop fetching instructions until it gets a ha~dware reset. ~he HMOS part will go through the motIons of executmg the ORL instruction, and then fetch the JMP instruction. It will continue fetching and executing JMP $ until hardware reset. Maintaining HMOS/CHMOS 8051 interchangeability in,response to Idle requires more planning. The HMOS part will not respond to the instruction that puts the CHMOS part into Idle, so that instructionneeds.to.be followed by a software idle. This would be an Idhng loop which would be terminated by the same conditions that would terminate the CHMOS's hardware Idle. Then when the CHMOS device goes into Idle, the HMOS version executes the idling loop, until either a hardware reset or an enabled interrupt is received. Now if Idle is terminated by an interrupt, execution for the CHMOS device will proceed after RETI from the instruction following the one that invoked Idle. The instruction following the one that invoked Idle is the idling loop that was inserted for the HMOS d.evice. At this point, both the HMOS and CHM~S devices ~ust be able to fall through the loop to contmue executIOn. Idle and Power Down: The Idle and Power Down modes exist only on the CHMOS devices, but if one 2-211 intJ AP-252 One way to achieve the desired effect is to define a "fake" Idle flag, and set it just before going into Idle. The instruction that invoked Idle is followed by a software idle: SETB ORL JB IDLE PCON,#l IDLE,$ Now the interrupt that terminates the CHMOS's Idle must also break the software idle. It does so by clearing the "Idle" bit: REFERENCES I. Pawlowski, Moroyan, Alnether, "Inside CMOS 2. 3. 4. CLR RETr IDLE Note too that the PCON register in the HMOS 8051 contains only one bit, SMOD, whereas the PCON register in CHMOS contains SMOD plus four other bits. Two of those other bits are general purpose flags. Maintaining HMOS/CHMOS interchangeability requires that these flags not be used.' ' 5. Technology," BYT$ magazine, Sept., 1983. Available as Article Reprint AR-302. Kokkonen, Pashley, "Modular Approach to C-MOS Technology Tailors Process to Application," Electronics, May, 1984. Available as Article Reprint AR-332. Williamson, T., Designing Microcontroller Systems for Electrically Noisy Environments, Intel Application Note AP-125, Feb. 1982. Williamson, T., "PC Layout Techniques for Minimizing Noise," Mini-Micro Southeast, Session 9, Jan., 1984. Alnether, J., High Speed Memory System Design Using 2147H, Intel Application Note AP-74, March 1980. 6. Ott, H., "Digital Circuit Grounding and Interconnection," Proceedings of the IEEE Symposium on Electromagnetic Compatibility, pp. 292-297, Aug. 1981. 7. Digital Sensors by Technar, Technar Inc., 205 North 2nd Ave., Arcadia, CA 91006. 2-212 AP-410 APPLICATION NOTE November 1987 Enhanced Serial Port on the 83C51FA BETSY JONES ECO APPLICATIONS ENGINEER © Intel Corporation, 1987 Order Number: 270490-001 2-213 AP-410 The serial port on the 8051 has been enhanced on the 83CSIFA with the addition of two new features: Automatic Address Recognition and Framing Error Detection. Automatic Address Recognition facilitates multiprocessor communications by reducing CPU overhead. Framing Error Detection increases communication reliability by checking each reception for a valid stop bit. This Application Note explains how to use these new features with samples of code for typical applications. A section is also included which reviews how to set up the serial port for multiprocessor applications. MULTIPROCESSOR COMMUNICATIONS' In applications where multiple controllers jointly perform a task, the master controller must be able to communicate selectively with individual slaves. To do this, the master first identifies the target slave (or slaves) with an address byte and then transmits a block of data. The target slaves must be able to identify their own address before receiving any dat~ bytes. The serial port on the 8051 provides a 9-bit mode to facilitate multiprocessor communication. The 9th bit allows the controller to distinguish between address and data bytes. In this mode, a total of II bits are received or transmitted: a ~tart bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (I). See Figure below. The 9th bit is set to I to identify address bytes and set to' 0 for data bytes. A typical data stream is seen below: ADDRESS BYTE 08 = 1 DATA BYTE 08 = 0 DATA BYTE I 08 = 0 ... Initially the slave is set up to only receive address bytes. Once it receives its own address, the slave reconfigures itself to receive data. On the 8051 serial port, an address byte interrupts all slaves for an address comparison. On the 83C5IFA, however, Automatic Address Recognition allows the addressed slave to be the only one interrupted; that is, the address comparison occurs in hardware, not software. With this feature, the master controller can establish communication with one or more slaves without all the slaves having to respond to the transmission. AUTOMATIC ADDRESS RECOGNITION Automatic Address Recognition reduces the CPU time required to service the serial port. Since the CPU is only interrupted when it receives its own address, the software overhead to compare addresses is eliminated. This would also effectively reduce the sophistication of the serial protocol when numerous controllers are sharing the same serial link. This same feature can also be used in conjunction with the Idle Mode to reduce the system's overall power consumption. For instance, a master may need to communicate with only one slave at a time. With all slaves in Idle Mode, only that one slave would be interrupted to respond to the master's transmission. Without Automatic Addressing, each slave would have to "wake up" to check for its address. Limiting the interruptions reduces the amount of current drawn by the system and thus reduces the power consumption. In multiprocessor applications the serial port is configured in either of the 9-bit modes (Mode 2 or 3). Mode 2 has a fixed baud rate whereas Mode 3 is variable. For more information on the different serial port modes re. fer to the "Serial Port Set Up" section. Aufomatic Address Recognition is enabled by setting the SM2 bit in SCaN. Each slave has its SM2 bit set waiting for an address byte (9th bit = I). The Receive Interrupt (RI) flag will get set when the received byte corresponds to either a Given or Broadcast Address. The slave then clears its SM2 bit to enable reception of data bytes (9th bit = 0) from the master. The master can selectively communicate with groups of slaves by using the Given Address. Addressing all slaves at once is possible with the Broadcast Address. These addresses are defined for each slave by two new' Special Function Registers: SADDR and SADEN. A slave's individual address is specified in SADDR. SADEN is a mask byte that defines don't-cares to form the Given Address. These,don't-cares allow flexibility in the user-defined protocol to address one or more slaves. The following is an example of how to define Given Addresses and selectively address different slaves. STOP BIT NINTH DATA BIT 270490-1 inter AP-410 FRAMING ERROR DETECTION Slave 1 SAOOA SAOEN 1111 1111 0001 101Q GIVEN 1111 OXOX Slave 2 SAOOA SAOEN 1111 1111 0011 1001 GIVEN 1111 OXX1 Framing Error Detection is another new feature on 83C51FA serial port which allows the receiving controller to check for valid stop bits in Modes I, 2, or 3. A missing stop bit can be caused, for example, by noise on the serial lines or transmission by two CPUs simultaneously. The SADEN bytes have been selected such that bit 1 (LSB) is a don't-care for Slave I's Given Address, but bit 1 = 1 for Slave 2. Thus, to selectively communicate with just Slave 1 an address with bit 1 = 0 would be used (e.g. 1111 0000). Similarly, bit 2 = 0 for Slave I, but is a don't-care for Slave 2. Now to communicate with just Slave 2 an address with bit 2 = I would be used (e.g. 1111 0111). Finally, to communicate with both slaves at once the address must have bit I = I and bit 2 = O. Notice, however, that bit 3 is a "don't-care" for both slaves. This allows two different addresses to select both slaves (1111 0001 or III I 0101). If a third slave was added that required its bit 3 = 0, then the latter address could be used to communicate with Slave I and 2 but not Slave 3. The master can also communicate with all slaves at once with the Broadcast Address. It is formed from the logical OR of SADDR and SADEN with zeros defined as don't-cares. For example, the Broadcast address for Slave I would be formed as follows: SADDR SADEN = 1111 0001 = 11111010 =D- BROADCAST =1111 lXll 270490-2 The don't-cares also allow flexibility in defining the Broadcast Address, but in most applications a Broadcast Address will be OFFH. SADDR and SADEN are located at address A9H and B9H, respectively. On Reset, SADDR and SADEN are initialized to OOH which defines the Given and Broadcast Addresses as XXXX XXXX (all don't-cares). This assures the 83C51FA serial port to be backwards compatible with the other MCS®~51 products which do not implement Automatic Addressing. If a stop bit is missing a Framing Error bit FE will be set. This bit can then be checked in software after each reception to detect communication errors. Once set, the FE bit must be cleared in software. A valid stop bit will not clear FE. The FE bit is located in SCON and shares the same bit address as SMO. To determine which is accessed, a new control bit called SMODO has been added in the PCON register (see figures below). If SMODO = 0, then accesses to SCON.7 are to SMO. If SMODO = I, then accesses to SCON.7 are to FE. PCON: Power Control Register (Not Bit Addressable) I SM001 I SMODO I-I POF I GF1 I GFO I PO IIOL I Address = 87H SCON: Serial Port Control Register (Bit Addressable) I SMO/FE I SM1 I SM2,I AEN I TBSI ABSI TI I All Address = 98H SERIAL PORT SOFTWARE The following sections of code show examples of how to invoke Automatic Addressing and Framing Error Detection. Routines for both the slave and master are given. Code is also included to initialize both serial ports; however, for more information on setting up the serial port refer to the next section. For this example, the master and slave are transmitting/receiving at 9600 baud with a 12 MHz crystal frequency. To obtain this baud rate, the serial port is configured in Mode 3 and Timer 2 is used as the baud-rate generator. Listing I shows the initialization for the slave. Notice that Automatic Addressing and Framing Error Detection are enabled. The Given and Broadcast addresses for this slave are taken from Slave I in the previous example. A temporary byte has also been defined to store the incoming data byte. The slave will remain in Idle Mode until it is interrupted by its own address. At that point, it clears the SM2 2-215 inter AP·410 Listing 1. Initialization Routine for the Slave ORG LJMP OOH INIT ORG LJMP 0023H SERIAL_PORT_INTERRUPT TEMP DATA 30H Temporary storage byte INIT: MOV SCON, #OFOH ORL MOV MOV MOV PCON, #40H RCAP2H, #OFFHRCAP2L, #OD9H T2CON, #34H Mode 3, enable Auto Addressing and reception FE bit accessed (SMODO 1) Reload values for 9600 Baud = Timer 2 set up, TR2 timer on =1 turns INTERRUPTS: SETB EA SETB ES Enable global interrupt Enable serial port interrupt ADDRESSES: MOV SADDR, # 11110001 MOV SADEN, # 11111010 Define Given & Broadcast Addresses GIVEN 1l1l0XOX BROADCAST 11111X11 ORL PCON, #OlH Invoke Idle Mode = = Listing 2. Receive Routine for the Slave SERIAL_PORT INTERRUPT: PUSH PSW CLR RI CLR SM2 RECEIVE_DATA: JNB RI, $ MOV C, SCON.7 JC FRAMING_ERROR MOV TEMP, SBUF CLR RI SETB 5M2 RI set when address is recognized & must be cleared in software Reconfigure slave to receive data bytes Wait for RI to be set Check for framing error Receive data byte & store in temporary location Clear flag for next reception Re-enable Automatic Addressing POP PSW RETI FRAMING_ERROR: CLR SCON.7 CLR C ' • • • Clear FE bit Error routine left up to the user POP PSW RETI 2-216 inter AP-410 Listing 3. Initialization and Transmit Routines for the Master GIVEN_l MESSAGE_l INIT: MOV MOV MOV MOV equ data 1l1l0001B 30H SCON, #ODOH RCAP2H, #OFFH RCAP2L, #OD9H T2CON, #34H TRANSMIT_ADDRESS: CLR TI SETB TBB MOV SBUF, #GIVEN_l JNB TI, $ CLR TI TRANSMIT_DATA: CLR TBB MOV SBUF, MESSAGE_l JNB TI, $ CLR TI Mode 3, REN 9600 Baud =1 Timer 2 set up, TR2 =1 Mark 1st byte as an address byte (9th bit 1) Send address Wait for transmission complete Clear flag for next transmission = Mark 2nd byte as a data byte (9th bit 0) Send data byte = bit to enable reception of data bytes. Depending on the user's protocol, more than one data byte may actually be received. This example, however, assumes only one byte of data follows each address byte. Listing 2 shows the receive routine. Notice that when the data byte is received, the software checks for a framing error. The error routine could, for example, send an error message to the master and ask the master to re-transmit the last message. Before exiting the routine the SM2 is set to I to reenable Automatic Addressing. Once the slave has responded to the master's command, it could also put itself back into Idle Mode to wait for, the next message. The initialization routine for the master in Listing 3 is very similar to the slave. In this example, however, the master does not need Automatic Addressing; it is simply transmitting address and data bytes. GIVEN_l is a byte to address the slave in the above example. MESSAGE_l is a register that contains the data byte sent to this slave. Its value is arbitrary for the sample code. SERIAL PORT SET UP This section describes how to initialize the 83C51FA serial port for multiprocessor applications. Two different modes are available which provide 9-bit operation: Mode 2 which has a fixed baud rate and Mode 3 which has a .variable baud rate. Baud rates can be generated by either Timer 1 or Timer 2 (available on the 83C51FA but not the 8051). Deciding which mode and timer to use is determined by the desired baud rate and clock frequency of the particular application. Another consideration is the tolerance needed between serial ports. Since the serial port re-synchs its receiver at every start bit, only 8 or 9 bit-times are available to accumulate timing errors. As a result, the receiver and transmitter only have to be within about 5% of each other's baud rate. Allowing equal error to both transmitter and receiver, only about 2% accuracy is actually needed. Following is a discussion of both Modes 2 and 3 and examples of how to program each. The mode selection bits (SMO and SMl) are located in SCON. The REN bit must also be set to enable reception. SCON: Serial Port Control Register (Bit Addressable) ISMO I SM1 15M2 I REN I TBB I ABB I TI I AI Address = 98H Mode SMO 2 1 2-217 3 SMl o Baud Rate Fosc/64 or Fosc/32 Variable intJ Ap·410 Example 1. Serial Port Mode 2 Frequency Desired Baud Rate MOV SCON, #OBOH = 12 MHz = 1/32 (Osc =375 kBaud Freq) Serial port Mode 2 Automatic Addressing (SM2 1), reception enabled (REN 1) SMODl 1 to double baud rate = = ORL PCON, #80H = Mode 2 Mode 2 uses a fixed baud rate of 1/32 or 1/64 of the oscillator frequency depending on the value of the SMODI bit in PCON. This mode basically offers a choice of two high-speed baud rates. With a 12 MHz clock frequency, baud rates of 187.5 kbaud or 375 kbaud can be obtained. are Ml and MO located in TMOD. To turn on Timer 1 the TR1 bit in TCON must be set. Also, the Timer 1 interrupt should be disabled in this application so that when the timer overflows it does not generate an interrupt. None of the timer/counters need to be set up for Mode 2. Only the SFRs SCON and PCON need to be defined. IGATEI CIT I M1 I MO IGATEI CIT IM1 I MO PCON: Power Control Register (Not Bit Addressable) Timer 1 Address = 89H I SMOD1 I SMOOO I-I PDF I GF1 I GFO I PO IIOL I The baud rate in this mode is calculated by: Mode 2 Baud Rate = = 0, 1, \, I\, I I Timer 0 TCON: Timer/Counter Control Register (Bit addressable) Address = 87H SMOD1 SMOD1 TMOD: Timer/Counter' Mode Control Register (Not bit addressable) 2SMODl = Baud Rate Baud Rate = = I TF1 I TR1 I TFO I TRO IIE1 Osc Freq 64 X IT1 I lEO liTO I Address = 88H The formula for calculating the baud rate is given below. THI is the reload value for Timer 1 when it overflows. 1/64 Osc Freq 1/32 Osc Freq Mode 3 Mode 3 of the serial port has a variable'baud rate generated by either Timer 1 or Timer 2. The baud rate is generated by the rollover rate of the selected timer. The timer is operated in an auto-reload mode so it will roll over to the- reload value selected in software. Baud rates based otT Timer 2 have less granularity so that almost any baud rate can be obtained at a given clock frequency. However, Timer 1 is sufficient if the desired baud rate can be obtained at the specified clock frequency. Remember baud rates only need about 2% accuracy. Timer 1 Set Up To generate baud rates Timer I is usually configured in 8-bit auto-reload mode (Mode 2). The mode select bits Baud Rate = K x Osc Freq 32 x 12 x [256 - (TH1)1 K = 1 if SMOD1 ,;. o. K = 2 if SMOD1 = 1. (SMOD1 is at peON.7) If the baud rate is known, the reload value THI can be calculated by: TH1 = 256 _ K x Osc Freq 384 x Baud Rate THI must be an integer value. Rounding off THI to the nearest integer may not produce the desired baud rate with the 2% accuracy required. In this case, another crystal frequency may have to be chosen. Refer to Table 1 for timer reload values for commonly used baud rates. 2-218 intJ AP-410 Table 1. Commonly Used Baud Rates Generated by Timer 1 OscFreq Baud Rate 62.5K 19.2K 9.6K 4.BK 2.4K 1.2K 300 110 Timer 1 SMOD1 12 MHz 11.06 MHz 11.06 MHz 11.06 MHz 11.06 MHz 11.06 MHz 6MHz 6MHz TMOD Reload Value 20 20 20 20 20 20 20 20 FFH FDH FDH FAH F4H EBH CCH 72H 1 1 0 0 0 0 0 0 Example 2. Serial Port Mode 3, with Timer 1 as Baud-Rate Generator Frequency Desired Baud Rate = 11.0 MHz = 19.2 kBaud 6 TH1 = 256 _ (2) x (11.0 x 10 ) (32) x (12) x (19200) = 253 = FDH MOV SCON, #OFOH ORL PCON, #BOH MOV TMOD, #20H MOV TH1, #OFDH SETB TR1 Serial port Mode 3, SM2 = 1, .,REN=l SMOD1 1 Timer 1 Mode 2 Reload value for desired baud rate Turn on Timer 1 = It can be seen that the exact frequency to generate the standard baud rates (19.2K, 9600, 4800, etc.) is 11.06 MHz. However, it is not necessary to use this exact frequency. With a 2% tolerance any crystal value from 10.8 MHz to 11.3 MHz is sufficient. interrupt then becomes available as a third external interrupt. (For more information on external interrupts, refer to the chapter "Hardware Description of the 8051" in the Embedded Controller Handbook.) T2CON: Timer/Counter 2 Control Register (Bit Addressable) Timer 2 Set Up Timer 2 has a special baud-rate generator mode which transmits and receives at the same baud rate. This mode is invoked by setting both the RCLK and TCLK bits in T2CON. To turn Timer 2 on the TR2 bit should also be set. Unlike Timer 1, this mode does not require that the timer overflow interrupt be disabled. That is, when Timer 2 is in the baud-rate generator mode, its interrupt is disconnected froin the Timer 2 overflow. This ITF2IEXF2IRCLKITCLKIEXEN2ITR2Ic/T2lcP/RL21 Address = C8H This formula for calculating the baud rate is given below. (RCAP2H, RCAP2L) is the 16-bit reload value when Timer 2 overflows. B au d R te = a Gsc Freq 32 x [65536 - (RCAP2H, RCAP2L)) where (RCAP2H, RCAP2L) is a 16-bit unsigned integer. 2-219 intJ AP-410 To obtain the reload value for RCAP2H and RCAP2L the above equation can be rewritten as: (RCAP2H. RCAP2L) = 65536 - 32 ~S::U~ate Table 2. Commonly Used Baud Rates Generated by Timer 2 Baud Rate Refer to Table 2 for reload values' for commonly used baud rates. Notice that when using Timer 2, most standard baud rates can be .obtained at 12 MHz. 375K 9.6K 4.SK 2.4K 1.2K 300 110 300 110 Timer 2 OscFreq 12MHz 12 MHz 12MHz 12MHz 12MHz 12MHz 12MHz 6MHz 6MHz RCAP2H RCAP2L FF FF FF FF FE FB F2 FO F9 FF 09 B2 64 CS 1E AF SF 57 Example 3. Serial Port Timer with Timer 2 as Baud-Rate Generator Frequency Desired Baud Rate (RCAP2H, RCAP2L) MOV SCON, #OFOH MOV RCAP2H, #OFFH MOV RCAP2L, #OD9H MOV T2CON, #34H 12 MHz = 9600 = Baud (12 x 10 6 ) = 65536 - (32) x (9600) = 65497 = FFD9H Serial port Mode 3, SM2 = 1, REN = 1 Reload values for de.sired baud rate Timer 2 as baud rate generator, turn on Timer 2 2-220 inter APPLICATION BRIEF AB-41 September 1988 Software Serial Port Implemented with the peA BETSY JONES ECO APPLICATIONS ENGINEER @ Intel Corporation, 1988 2-221 Order Number: 270531-002 intJ AB-41 For microcontroller applications which require more than one serial port, the 83C51FA Programmable Counter Array (PCA) can implement additional halfduplex serial ports. If the on-chip UART is being used as an inter-processor link, the PCA can be used to interface the 83C51FA to additional asynchronous lines. This application uses several different Compare/Capture modes available on the PCA to receive or transmit bytes of data. It is assumed the reader is familiar the PCA and ASM51. For more information on the PCA refer to the "Hardware Description of,the 83C51FA" chapter in the Embedded Controller Handbook (Order No. 210918). Introduction The figure below shows the format of a standard IO-bit asynchronous frame: I start bit (0), 8 data bits, and I stop bit (I). The start bit is used to synchronize the receiver to the transmitter; at the leading edge of the start bit the receiver must set up its timing logic to sample the incoming line in the center of each bit. Following the start bit are eight data bits which are transmitted least significant bit first. The stop bit is set to the opposite state of the start bit to guarantee that the leading edge of the start bit will cause a transition on the line. It also provides a dead time on the line so that the receiver can maintain its synchronization. Two of the Compare/Capture modes on the PCA are used in receiving and transmitting data bits: When receiving, the Negative-Edge Capture mode allows the PCA to detect the start bit. Then using the Software , Timer mode, interrupts are generated to sample the incoming data bits. This same mode is used to clock out bits when transmitting. This Application Note contains four sections of code: (3) Receive routine (4) Transmit routine. A complete listing of the routines and the test loop which was used to verify their opera~ion is found in the Appendix. A total of three half-duplex channels were run at 2400 Baud in the test program. The listings shown here are simplified to one channel (Channel 0). Variables Listing I shows the variables used in both the receive and transmit routines. Flags are defined to signify the status of the reception or transmission of a byte (e.g. RCVJTARTJIT, TXM-START_BIT). RCVJUF and TXM_BUF simulate the on-chip serial port SBUF as two separate buffer registers. The temporary registers, RCV_REG and TXM_REG, are used to save bits as they are received or transmitted. Finally, two counter registers keep track of how many bits have been received or transmitted. Variables are also needed to define one-half and one-' full bit times in units of PCA timer ticks. (One bit time = I / baud rate.) With the PCA timer incremented every machine cycle, the equation to calculate one bit time can be written as: ( Osc. Freq. ) = 1 billime (in PCA , 12) X (baud r a l e ' li~er licks) In this example, the baud rate is 2400 at 16 MHz. 16MHz (12) X (2400) = 556 counls = 22C Hex The high and low byte of this value is placed in the variables FULL_BIT_HIGH and FULL_BIT_LOW, respectively. 115H is the value loaded into HALFJIT~IGH and HALFJIT_LOW. (I) List of variables (2) Initialization routine STOP .1 2-222 270531-1 inter AB-41 Listing 1. Variables used by the software serial port. Channel 0 , Receive Routine RCV_START_BIT_O BIT RCV_DONE_O BIT 20H.1 DATA 30H DATA 31H DATA 32H RCV BUF RCV REG ° ° 20H.O Indicates start bit has been received Indicates data byte has been received Software Receive nSBUF" Temporary register for receive bits Counter for receiving bits Transmit Routine: TXM_START_BIT_O BIT TXM IN PROGRESS_O BIT ° 20H.3 20H.4 DATA 34H TXM_REG_O DATA 35H TXM COUNT_O DATA 36H DATA 0 DATA 37H NEG EDGE S W-TIMER EOU EOU 49H HALF BIT HIGH HALF-BIT-LOW FULL-BIT-HIGH FULL-BIT-LOW EOU EOU EOU EOU 01H I5H 02H 2CH TXM BUF llH Indicates start bit has been transmitted Indicates transmit is in progress Software transmit "SBUF" Temporary register for transmitting bits Counter for transmitting bits Register used for the test program Two modes of operation for compare/capture modules Half bit time 115H Full bit time 22CH 2400 Baud at 16 MHz 270531-4 2-223 infef AB-41 InitiaJization Listing 2 contains the intialization code for the receive and transmit process. Module 0 of the PCA is used as a receiver and is first &et up to detect a negative edge from the start bit. Modules 2 and 3 are used for the additional 2 channels (see the Appendix). Module 3 is used as a separate software timer to transmit bits. Listing 2. Initialization Routine ORG OOOOH LJMP INITIALIZE ORG OOlBH LJMP RECEIVE_DONE ORG 0033H LJMP RECEIVE , INITIALIZE: MOV SP, #5FH INIT_PCA: MOV CMOD, #OOH MOV CCON, #OOH MOV CCAPMO, #NEG~EDGE MOV CCAPM3, #S_W_TlMER MOV CL, #OOH MOV CH, #OOH MOV IE, #OD8H SETB CR Timer 1 overflow simulates "RI" interrupt PCA interrupt Initialize stack pointer (specific to test program) Increment PCA timer @ 1/12 Osc Frequency Clear all status flags Module 0 in negative-edge trigger mode (Pl.3) Module 3 as software timer mode Init all needed interrupts EA, EC, ES, ET1 Turn on PCA Counter 270531-5 All flags and registers from Listing 1 should be' cleared in the initialization process. Receive Routine Two operating modes of the PCA are needed to receive bits. The module must first be able to detect the leading edge of a start bit so it is initially set up to capture a I-to-O transition (i.e. Negative-Edge Capture mode). The module is then reconfigured as a software tiiner to cause an interrupt at the center of each bit to deserialize the incoming data. The flowchart for the receive routine is given in Figure 1. 2-224 AB-41 NO YES Add 1 bit Add 1 bit time to compare/capture registers time to compare/capture registers NO Reconfigure PC4 module to capture 1 - 0 transitions Reconfigure PCA module to capture 1 - 0 transitions 270531-2 Figure 1. Flowchart for the Receive Routine 2-225 intJ AB-41 Listing 3.1 shows the code needed to detect a start bit. Notice that the first software timer interrupt will occur onehalf bit time after the leading edge of the start bit to check its validity. If it is valid. the RCV_START_BIT is set. The rest of the samples will occur a full bit time later. The RCV_COUNT register is loaded with a value of 9 which indicates the number of bits to be sampled: 8 data bits and 1 stop bit. Listing 3.1. Receive Interrupt Routine RECEIVE: , PUSH ACC PUSH PSW MODULE_O: CLR CCFO Assume reception on Module 0 MOV A, CCAPMO Check mode of module. If ANL A, #OlllllllB ; set up to receive negative CJNE A,#NEG_EDGE, RCV START edges, then module - ; is-waiting for a start bit °; CLR C MOV A, #HALF BIT LOW ADD A, CCAPOL MOV CCAPOL, A MOV A, #HALF BIT HIGH ADDC A, CCAPOH MOV CCAPOH, A MOV CCAPMO, #S W TIMER POP PSW - POP ACC RETI Update compare/capture registers for half bit time to sample start bit Half bit time = l15H ° Reconfigure module as a software timer to sample bits °; °; RCV START_O: CJNE A, 'is' W TIMER, ERROR Check module is -T ; configured as a sO,ftware ; timer, otherwise error. JB RCV_START_BIT_O, RCV BYTE Check if start bit T is received yet. JB P1.3, ERROR_O Check that start bit = 0, otherwise error. SETB RCV_START_BIT_O Signify valid start bit was received MOV RCV_COUNT_O, #09H Start counting bits sampled CLR C MOV A, #FULL BIT LOW ADD A, CCAPOL MOV CCAPOL, A MOV A, #FULL BIT HIGH ADDC A, CCAPOH MOV CCAPOH, A POP PSW POP ACC RETI Update compare/capture registers to sample incoming bits Full bit time = 22CH 270531-6 2-226 intJ AB-41 The next 8 timer interrupts will receive the incoming data bits; the RCV_COUNT register keeps track of how many bits have been sampled. As each bit is sampled, it is shifted through the Carry Flag and saved in RCV _REG. The ninth sample checks the validity of the stop bit. If it is valid, the data byte is moved into RCV _BUF. The main routine must have a'way to know that a byte has been received. With the on-chip UART, the RI (Receive Interrupt) bit is set whenever a byte has been received. For the software serial port, any unimplemented interrupt vector can be used to generate an interrupt when a byte has been 'received. This routine uses the Timer I Overflow interrupt (its selection is arbitrary). A routine to test this interrupt is included in the listing in the Appendix. Listing 3.2. Receive Interrupt Routine (Continued) RCV BYTE 0: DJNZ RCV COUNT 0, RCV DATA a ; On 9th sample, ; check for valid stop bit RCV STOP 0: JNB Pl.3, ERROR a MOV RCV_BUF_O, RCV_REG_O ; Save received byte in receive "5BUF" SETB RCV DONE a Flag which module received a byte Generate an interrupt so SETB TFl main program knows a byte has been received (Note: selection of TFl is arbitrary) MOV CCAPMO, #NEG_EDGE Reconfigure module a for Reception of a start bit POP PSW POP ACC RETI RCV DATA 0: MOV C, Pl.3 MOV A, RCV REG 0 RRC A -- MOV RCV_REG_O, A CLR C MOV A, #FULL BIT LOW ADD A, CCAPOL MOV CCAPOL, A MOV A, #FULL BIT HIGH ADDC A, CCAPOH MOV CCAPOH, A POP PSW POP ACC RETI Sampling data bits Shifts bits thru CY into ACC Save each reception in temporary register Update c/c register for next sample time 270531-7 In addition, an error routine (Listing 3.3) is included for invalid start or stop bits to offer some protection against noise. If an error occurs, the module is re-initialized to look for another start bit. Listing 3.3 Error Routine for Receive Routine ERROR 0: MOV CCAPMO, #NEG_EDGE CLR RCV_START_B~T_O Reset module to look for start bit Clear flags which might have been set POP PSW POP ACC RETI 270531-8 2:227 inter AB-41 Transmit Routine Another peA module is configured as a software timer to interrupt the CPU every bit' time. With each timer interrupt one or more bits can be transmitted through port pins. In the test program three channels were operated simultaneously, but in the· listings below, one channel is shown for simplicity. The selection of port pins is user programmable. The flowchart for the transmit routine is given in Figure 2. Figure 2. Flowchart for the Transmit Routine When a byte is ready to be transmitted, the main program moves the" data byte into the TXM_BUF register and sets the corresponding TX~IN_PROGRESS bit. This bit informs the interrupt routine which channel is transmitting. The data byte is then moved in the storage register TX~EG, and the TX~COUNT is loaded. This main routine is shown in Listing 4.1. Listing 4.1 Transmit Set Up Routine. Channel O. TXM_ON_O: CLR TXM_START_BIT_O Clear status flag from previous transmission MOV TXM BUF 0, DATA 0 Load "SBUF" with data byte MOV TXM-REG-O, TXM BUF 0 MOV TXM-COUNT 0, #09 8 data bits + 1 stop bit ~ETB TXM_IN_PROGRESS_O 270531-9 2-228 inter AB-41 Listing 4.2 shows the transmit interrupt routine. The first time through, the start bit is transmitted. As each successive interrupt outputs a bit, the contents of TXM_REG is shifted right one place into the Carry flag, and the TXM_COUNT is decremented. When TXM_COUNT equals zero, the stop bit is transmitted. Listing 4.2. Transmit Interrupt Routine TRANSMIT: PUSH ACC PUSH PSW CLR CCF3 ; Clear s/w timer interrupt ; for transmitting bits TRANSMIT 1 ; Check which ; channel is transmitting. ; "TRANSMIT 1" is listed in ; the Appendix , °; TRANSMIT_O: JB TXM_START_BIT_O, TXM BYTE If start bit has been sent, continue transmitting bits. CLR P3.2 Otherwise transmit start bit SETB TXM START BIT Signify start bit sent JMP TXM EXIT ° °; TXM BYTE 0: DJNZ TXM COUNT_O, TXM DATA If bit count equals 1 thru 9, transmit data bits (8 total) TXM STOP_O: SETB P3.2 CLR TXM IN PROGRESS , TXM DATA 0: MOV A, TXM REG - RRC A - ° ° MOV P3.2, C MOV TXM_REG_O, A TXM_EXIT: CLR C MOV A, *FULL_BIT_LOW ADD A, CCAP3L MOV CCAP3L, A MOV A, *FULL BIT HIGH ADDC A, CCAP3H MOV CCAP3H, A POP PSW POP ACC RET I When bit count = 0, transmit stop bit Indicate transmission is finished and ready for next byte Transmit one bit at a time through the carry bit Save what's not been sent Update compare value with Full bit time = 22CH 270531-10 Conclusion The software routines in the Appendix can be altered to vary the baud rate and number of channels to fit a particular application. The number of channels which can be implemented is limited by the CPU time required to service the PCA interrupt. At higher baud rates, fewer channels can be run. The test program verifies the simultaneous operation of three half-duplex channels at 2400 Baud and the on-chip full-duplex channel at 9600 Baud. Thirty-three percent of the CPU time is required to operate all four channels. The test was run for several hours with no apparent malfunctions. 2-229 MCS-51 !!ACRO ASSEMBLER SWPORT 01101/80 ( PAGE DOS 3.20 (038-N) IICS-51 MACRO ASSEMBLER, V2.2 OBJECT MODULE PLACED IN SWPORT. OBJ ASSEMBLER INVOKED BY: C: \AEDIT\ASM51. EXE SliPORT. RCV LOC OBJ LINE I 2 0000 0000 020036 ~ - 001B 001B 02025C ~ 0023 0023 020282 N 0033 0033 D200DC 3 152 153 154 155 156 151 158 159 160 161 162 163 164 165 166 161 168 169 110 111 112 113 114 115 116 171 118 179 SOURCE $NOMaDSI SNOSYMBOLS $NOLIST ~;:eP~~~i~~u~!:;S c~~~n;r;e!~: I~~t!~~t~a tn S~~i~:~~e s~~i~~n p~~t. ~~036g~ugaJ~~HlIihirt~~~h~~;c~~~c~~~i~! m\~~ ~t: f~n~!~i;~~lt~U~~~X all four ports simultaneously. To test the receive routines, Wdummy· terminals transmit 00 - FF hex continually to the PCA. When the hrst byte is received, it is ~~~:~~t:at~nSOihe Iio;~rn~O:~f~!S~g ;:c:f;!dfh;h~ei~';~:. vai~~o~s ; 3 ~~Urln:~ i~~~ird v:£~~~sbi~r~r sf~~Sbt~ r~ ~~~:f!:d~omparison CRG OOIBR LJIIP RECEIVE_DONE Timer 1 Overflow - simulates 'RI' interrupt ~ "'0 "'0 bRG 00238 LJMP SERIAL_PORT Serial port interrupt Z bRG 0033H LJMP RECEIVE PCA interrupt 180 0000 0008 0010 0001 0009 0011 0002 OOOA 0012 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 Occurs CRG DOH LJIIP INITIALIZE m ->< C VARIABLES USED BY THE SOFTIIARE SERIAL PORT ; RECEIVE ROUTINE: --------------- kcv START BIT 0 RCV-STARTllIrl ~CV::STARryIor:2 RCV DONE 0 RCV-DON~1 Rev-DONE-2 kcv-oN- 0Rev-Olrl RCV::0~2 BIT BIT BIT 20B.0 21B.O 22H.0 received BIT BIT BIT 20B.l 21H.l 22B.l Indicates data byte has been received -BIT 20B.2 218.2 229.2 Used in IM.in test program to check for a received byte BIT BIT Indicates start bit has been 270531-11 ):0 q:J .... .0. _. MeS-51 HACRO ASSEIIBLER LOC OBJ 0030 0040 0050 0031 0041 0051 0032 0042 0052 gg:~ 0053 0011 0049 0015 0001 002C 0002 Rev BUF 0 Rcv-aurl RCV"l!Or2 • Rev REG 0 RCV""REC>1 RCIr1!EC>2 • RCV COUNT 0 RCV-COUNrl RCV-COUNr2 ; - 213 COUNr2 m 214 215 0036 75815F 0039 003C 003F 0042 0045 75D900 75D800 75DAlI 75DBlI 75DClI 0048 75E900 004B 75F900 D8 gg~f m: 0053 0056 0059 005C 759850 75CBFF 75CACC 75CB34 OOSF C200 0061 C208 0063 C210 0065 C201 ggg~~ • DATA DATA DATA 3 0 R ; Software receive 'SBUF' 40B SOH DATA DATA DATA 4 1 f t ; receiving bits DATA DATA DATA 3 2 B ; Counter for receiving bits 42H 52R 51R DATA 53B m g;~~s i~e~~~t r~~~~:~ g~i~ - to check ~_QIHER NEG EDGE EOO EgO liB 49B Two modes of operation for the ComparelCapture modules 218 219 220 221 222 223 224 225 HALF BIT LOll BALFI!ITIIIGR FULLIIIT. .OW FOLL'IITIIIGB - EOO EOU EgU EOU ISH 01R2CB 02B Full bit time m 242 243 244 245 246 247 248 249 250 251 252 253 CR.. 3 1 B ; Temporary register for ~l~ 228 229 230 231 232 233 234 235 236 237 238 239 I Ia PAGE SOURCE 199 200 201 202 203 204 205 206 207 20B 209 210 ~~~ I\J N ~ 01/01/80 SIiPORT LINE : • HOV SP, 15FB INIT PCA: - MOV I!OV HOV HOV HOV I ; INIT FLAGS: - = 22CB 2400 Baud @ 16MBz II> INITIALIZATION ROUNTINE ======================a ~ INITIALIZE: INIT SP: - Balf bit time = 1I5B eKOD, 100H CCON, 100B CCAPMO, lNEG EDGE CCAPM1, INEC>EDGE CCAPM2, INEC>EDGE MOV CL, ,OOH HOV CH, 100H ~g~BI~R IOD8B HOV HOV MOV HOV SCON. ,50H RWlH, 10FFH RCAP2L, 10CCR T2CON, 134H IJI I ~ I Initialize stack pointer ; ; ; ; ; ; ; (specific to the test program) Increment PCA clock @ 1/12 Osc Freq Clear all status flags Module 0 in Neg-edge capture mode (PI. 31 Module l ' IPl.4 Module 2 ' PI. 5 ~~;i~~i~b.n~~~~~e~nterruPt: EA,EC,ES,ETI Serial port in mode 1 (8-Bit UART) Reload values for 9600 Baud @ 16 MHz Timer 2 as a baud-rate generator, turn on timer 2 CLR Rev START BIT 0 CLR RCV-STARTIIIT-l eLR RCV-ST'>.RrBIr2 -CLR RCV_DONE_O 270531-12 IICS-51 MACRO ASSEllBLER LOC OBJ 0067 C209 0069 C211 0068 C202 006D C20A 006F C212 LINE 254 255 256 257 258 259260 261 0071 D2B2 0073 02B3 0075 D2B4 0077 02B5 0079 0286 007B D2B7 0070 753000 0080 754000 0083 755000 0086 753200 0089 754200 008C 755200 I):> I\) w I\) OOaF 753100 0092 754100 0095 755100 0098 753300 0098 154300 009E 755300 262 263 _ 264 265 266 267 268 269 01/01/80 SHPI)RT SI)VRCE CLR -RCV DONE 1 CLR RCV::DONE:2 CLR-RCV ON 0 CLR RCv-ON"'l CLR RCV::O~2 Port 3 pins used in test program for error routines llain proqram: SETB P3.2 SETB Pl.3 Interrupt Iout~~i~: P3. 5 2Tl MOV RCV BUF 0, ,OOH MOV RC"VBVrl, 'DOH MOV Rcv:aUr:2, tOOH 1I0V RCV COUNT 0, lOOH MOV RC1rCOUNrI, 100H MOV RCV:C0VNr:2, 'DOH 281 HOV RCV BEG 0, 'DOH MOV lICV"llEG""l, 'DOH MOV Rcv:HE~2, 'DOH 282 283 284 285 286 287 288 289 OOAD 00110 00B2 00B5 0087 300A09 &540 B54319 C20A 0543 00B9 3012E5 OOBC E550 008E B55314 MAIN nSf ROUTINE - BECEIVE BITS CHEC!(_O: ~ ~CVRg}g6rC~ECK_1 t CLR RCV CJNE COUNr 17, ERRORO ON 0 INC COUNT_V 298 30S 306 307 308 .. HOV COVNrl, t008 MOV COUNr:2, tOOH 290 299 300 301 302 303 304 J> m ;.. IIOV COUNT 0, 'DOH 291 300209 E530 B5331E C202 OOAB 05H Error in reception on module 0 Error in reception on module 1 Error in reception on module 2 SErB P3.6 SETS P3.7 274 275 216 277 278 279280 00A1 OOM 00A6 DOA9 Error in comparison on module 0 ; Error in comparison on module 1 i ; Error in comparison on module 2 SETB P3.4 270 271 272 292 293 294 295 296 297 l PAGE ~HECK_I: Main proqram continually checks each channel for a recelved byte. e~~~ ~h~Y~~r~:n~·;:1~:dtn i~h~s .ggWr;ed register ~ ~~R~CfEc!(_2 CJNE A, COUNT !, ERROR1 CLR RCV ON 1 INC COUIIT_! b!ECK_2: JNB RCV ON 2, CHEc!( If IIOV A, RCV-BVF 2 CJNE A, COUNT_'2, ERROR2 270531-13 IICS-51 IlACRO ASSEIIBLER LOC OBJ OOCI C212 00C3 0553 DOCS 800A 00C7 C2B2' 00C9 750AOO OOCC 800f OOCE C2B3 DODO 750BOO 0003 80E4 0005 C2B4 0007 750COO OODA 80C5 OODC COED OODE CODO I\) ~ (.,) (.,) OOEO 00E3 00E6 00E9 OOEB OOEO 200811 200908 200AOB DODO ODED 32 OOEE 02016C OOFI 020lE4 00F4 00F6 00F8 OOFA C208 E50A 547F B41115 OOFO OOFE 0100 0102 0104 0106 0108 010A C3 7415 25EA FsEA 7401 35fA F5FA 75DA49 0100 DODO OlaF DOEO LINE 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 33B 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 SHPORT 01/01/80 l PAGE SOURCE CLR" RCV ON 2 INC COUIIT Z JIIP CHECK:O ~RRORO: ERRORI : ~RROR2: CLR P3.2 ~~ g~~~~~1 lOOH Error in comparison on module Discontinue receiving bytes CLR P3.3 MOV CCAPMl L 10 OH JIIP CHECK_l Error in comparison on module 1 CLR P3.4 Error in comparison on module 2 ~ g~~~~~6 100H PCA INTERRUPT ROUNTINE - RECEIVE BITS ,i hCEIVE: PUSH ACC PUSH PSH JB CCFO, MODULE a JB CCFl, JUMP 1JB CCF2, JUIIP-2 POP PSII POP ACC RETI ~UHP 1: JUIIP-2: - » til I .... 0l:Io LJIIP MODULE 1 LJIIP MODULE:2 CHANNEL 0 ; hOOULE_O: Check which module caused PCA interrupt and jump to appropriate routine CLR CCFO MOV A, CCAPMO ANL A, 101111111B CJNE A, INEG_EDGE, RCV_START _ 0 Reception on module a Check mode of module. If set up to receive negative edges, then module is waiting for a start bit CLR C MOV A, 'HALF BIT LON Update Compare/Capture registers for half a bit time to sam~le start bit Half blt time' 115H ~g~ ~bJ~t~O~ - ~Xch., '~~~uaIT_HIGH MOV CCAPOH, A MOV CCAPMO, IS_H_TIMER POP PSI! POP ACC Reconfigure module 0 as a software timer to sample bits 270531-14 -- MCS-51 MACRO ASSEMBLER LOC OBJ 0111 32 0112 B44948 0115 20001A 0118 209345 OllB 0200 0110 153209 0120 0121 0123 0125 0127 0129 0128 0120 012F 0131 C3 742C 25EA F5EA 1402 35FA F5FA 0000 OOEO 32 0132 053212 ~ (,J ./>. 0135 0138 013B 0130 309328 853130 0201 D28F 013F 0142 0144 0146 150All DODO OOEO 32 0147 0149 014B 014C A293 E531 13 F531 014E 014F 0151 0153 0155 0157 0159 0158 015D 015r C3 142C 25EA F5EA 7402 35FA F5FA DODO DOEO 32 0160 C2B5 LINE 364 365 366 367 368 369 370 371 372 313 374 315 316 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 401 408 409 410 411 412 413 414 415 416 417 01101/80 SWPORT PAGE II SOURCE RETI kcv-START- 0, CJNE A, 'S_Ii_ TIKER, ERROR_0 JB RCV_START_BIT_O, RCV_BYTE_O JB Pl.3, ERROR_O SETB RCV_START_BIT_O MOV RCV_COUNT_O, '09B cf Check module is configured as a software timer, otherwise errOl. Check if start bit has been Ieee i ved yet Check that start blt • 0, otherwise. error. Signify valid start bit was Ieee! ved Start counting bits sampled Update C/C registers to sample CLR C HOV A, 'FULL BIT LOW ~g~ ~~~ijEO~ - i~~~m~~~ ~t~ . 22CH ~g~cAA '~gk¥l1~IT_HIGH MOV CCAPOH, A POP PSI! POP ACC RETI ~CV BUE 0, - - - RCV STOP 0, DJNZ RCV_COUJIT_O, RCV_DATA 0 ~~ ~~3BU~R~?RR~ SETB RCV OOIlE_O SETB TFl- - REG - HOV CCAPMO, 'NEG EDGE POP PSI! POP ACC RETI kcv-DATA-0, MOV C, Pl.3 ~g~, RCV_REG_O HOV RCV_REG_O, A CLR C HOV A, 'FULL BIT LOll MOV A, 'FuLL BIT HIGH ADDC A, CCAP1JB HOV CCAPOH, A POP PSW POP ACe RETI ~~ ~~A~~PO~ hROR 0, - CLR P3.5 ° On 9th sample, check for valid stop bit ~r~; ;g~~~ v:.gd~r;e r!ge~~;ai ~eb;~:UF' ;s.. Generate an interrupt so main program ~~g;~, a s~r~~t~g~ ~rMer:i~~gitrary) Reconfigure module 0 for next reception of a start bit ~~Twg~t~a~~r~~~~ a:I I I I ..."" CY into ACC Save each reception in temporary register Update C/C register for next sample time Error routine for invalid start or stop bit or invalid mode comparison 270531-15 _. IICS-51 KACRO ASSEMBLER LOC LI~E OBJ gm tm l1 016C C2D9 016E E50B 8m ~m15 0115 C3 0116 1415 8m ~~g 8m i~?a Ol1C 1401 0182 150849 0185 0000 0181 ODED ro ffl I\) 0189 018A 0180 0190 32 84494B 20081A 209445 0193 0208 m 421 422 423 424 425 426 421 428 429 430 m CR.. ~~ ~g¢P~~AA~N~YTEgGE POP PSWPOP ACC RETI ~~~ll, '~iW~, - RCV START 1 -- aJiflf ~~c~r~~AH NOV CCAPMl, IS II TIMER ~~ 438 MOV A, 'HALF BIT HIGH 441 442 443 PDP PSI! POP ACC m, Rev START 1: - - - 0195 154209 1~~ 0198 e3 0199 142C 019B 25EB 453 454 455 eLR C MOV A, 'FULL BIT LOll ADD A, CCAPlI; - 01A5 DODO 01A1 ODED 01A9 32 DIM D542l2 01AD OlBO 01B3 01B5 01B1 01BA 01 BC 309428 854140 0209 D28F 75DB11 DODO DDEO m m 460 461 462 463 lt~ 466 461 468 469 410 471 472 I I .. RETI CJNE A, 'S II TlKER, ERROR 1 JB Rev STARTI!IT I, RCV BYTE 1 JB Pl."" ERROR_lSETB Rev START BIT 1 HOV Rev_COUNT_I, '119H m~ m~ m:~ m~!ev~~C~o~g~~'b:;:rge~~\et Similar to module 0 CLR CCFl IIOV A, CCAPKI 450 8m m= ; -- CLR C HOV A, 'HALF BIT LOll m m m ; Port pin used for debug only CHANNEL 1 , KODULE I: - 433 434 435 446 441 IIa PAGE SOURCE 418 0161 DODO. 0169 00&0 016B 32 01lf1/80 SKPORT :::; ... ~ .... ::g~ ~?1~5LLABIT HIGH ~~cc~Apr~~AH - , POP PSII POP ACC RETI ~CV_BYTE_l: OJNZ Rev_COUNT_l, RCV_OATA_1 Rev STOP 1: - JNB Pl.4, ERROR 1 HOV RCV BUF 1, Rev REG 1 SETB Rev DONE 1 SETB TFlHOV CCAPKl, 'NEG EDGE POP PSW POP ACC 270531-16 HCS-51 MACRO ASSEMBLER LOC OBJ OIBE 32 O}BF 01Cl 01C3 01C4 A294 E541 13 . F54l 01C6 01C1 0lC9 OICB OICD OlCF 0101 0103 0105 0101 C3 742C 25EB F5EB 7402 35FB F5FB DODO DOEO 32 0108 OloA 0100 01DF OIEI 0lE3 C2B6 75DBll C20B DODO OOEO 32 I\J N Co) m 0lE4 0lE6 0lE8 OlEA C20A ESDC 541F B41115 OlEO OIEE OIFO 0lF2 0lF4 0lF6 0lr8 01FA 01FD 01FF 0201 C3 1415 25EC FSEC 1401 35FC F5rc 15OC49 DODO oOEO 32 0202 84494B 0205 2010lA 0208 209545 020B 0210 0200 755209 LINE 413 474 415 416 471 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 491 498 499 500 SOl 502 503 504 505 506 501 508 509 510 511 512 513 514 SIS 516 517 518 519 520 521 522 523 524 525 526 521 01/01/80 SIIPORT ( PAGE SOURCE RETI Rev DATA I, - - MOV C, Pl.4 ~~ ~, RCV_REG_I HOV RCV_REG_I, A CLR C MOV A, 'FULL BIT LON ~g~ ~I:A~It:I~ - MOV A, 'FULL BIT HIGH AoOC A, CCAPTH MOV CCAPIH, A POP PSII POP ACC RETI ERROR I, CLR Pl.6 MOV CCAPHI, tNEG EDGE CLR RCV START BIT 1 POP PSII'" -POP ACC RETI - » q:J .... "" CHANNEL 2 ~OOULE- 2, CLR ccr2 MOV A, CCAPMl ANL A, ,01111111B CJNE A, 'NEG_EoGE, RCV_START_2 . Similar to module 0 CLR C HOV A, 'HALF BIT LOll ~g3 ~CA~~2~ MOV A, 'OALF BIT HIGH ACoC A, CCAPZ8 MOV CCAP2H, A ~g~ ~~QPM2, IS_II_TIllER POP ACC RETI - Rev START 2, - CJNE A, IS II TIllER, ERROR 2 ~~ ~r~s~T~~~~~~_2, RCV_BYTE_2 SETB RCV START BIT 2HOV RCV_COUNT _Z, '11'90 270531-17 MCS-51 MACRO ASSEMBLER LOC OBJ LINE 0210 0211 0213 0215 0217 0219 021B 0210 021F 0221 C3 742C 25EC F5EC 740t 35FC F5FC DODO OOEO 32 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 . 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 561 568 569 510 51\ 0222 055212 I\J ~ -..J 0225 0228 022B 0220 022F 0232 0234 0236 309528 855150 0211 028F 75DC11 DODO OOEO 0237 0239 023B 023C 023E 023F 0241 0243 0245 0247 0249 024B 0240 024F A295 E551 13 F551 C3 742C 25EC F5EC 7402 35FC F5FC DODO ODED 32 0250 0252 0255 0257 0259 025B C2B7 750C11 C210 DODD OOEO 32 32 01/01/80 SIiPORT l PAGE SOURCE CLR C MOV A, 'FULL BIT LOll ~g~ ~1:A~~tt'2~ - MOV AI. 'FuLL BIT HIGH ~g~cCCJ.p~~~~H POP PSH POP ACC RETI kcv BYTE 2: kCV=STOP=2: OJNZ RCV_COUNT_2, RCV_OATA_2 JNB P1.5, ERROR 2 ~~~l~~BgbR~' lCV_REG_2 SETB TFr HOV CCAPM2, 'NEG EDGE POP PSH POP ACC RETI RCV_DATA_2: HOV HOV RRC ~~ HOV ADD C, Pl.5 A, RCV REG 2 A -~CV_REG_2, A A, 'FULL BIT LOil A, CCAP 2'[; - =g~ i;Aj~~tL\IT AODC A, CCAP2H MOV CCAP 2H, A POP PSH POP Ace RETI ERaOR_2: » m ....• HIGH ~ CLR P3.1 MOV CCAPM2, 'NEG EDGE CLR RCV START BIT 2 POP PSlf'" -POP ACC RETI 512 513 514 575 When a byte is received on one ate set so the main , ~~un~eC~~~~:l:~i~ti~h~~~:i[~~~el:eae~e~~~:~. Bits ; , 580 581 582 kECEIVE_DONE: 519 025C CO EO 025E CO DO 0260 C28F ; This routine simulates the ·RI- interrupt. 576 511 518 PUSH ACe PUSH PSli CLR TFI 270531-18 HCS-51 HACRO ASSEMBLER LOC OBJ 0262 300106 0265 C201 0267 C200 0269 0202. 026B 026E 0270 0272 300906 C209 C208 020A 0274 0271 - 0279 027B 301106 C211 C2l0 0212 0270 0000 027F OOEO 0281 32 LINE 583 584 585 586 587 588 589 590 SWPORT JNB RCV DONE 0, RCV 1 CLR RCV-OONE-O CLR RCV-STAR! BIT 0 SETB RCV_ON_ORCV_l: JNB RCV DOllE I, RCV 2 CLR RCV-DONE-l CLR RCV-START BIT 1 SETB RCV_ON_l- RCV_2: JNB RCV DONE 2, RETURN CLR Rev-DONE-2 . CLR Rev-START BIT 2 SETB RCV_ON_, - hTUHN: POP PSi! POP Ace RET! 591 592 593 594 595 596 591 598 599 01/01/80 ( PAGE SOURCE 600 601 Check which module Ieceived a byte Clear flags needed for next reception Tell main routine which channel received a byte 602 603 604 605 606 607 608 609 610 N ~ CO 0282 0284 0286 0289 028B 0280 028F 0291 0293 COED COOO 30980B E599 C298 F599 DODD ODED 32 0294 0296 0298 029A C299 DODO ODED 32 611 612 613 614 615 616 617 618 619 620 621 '622 623 624 SERIAL PORT IN'rERRUPT j When a byte is received on the full-duplex serial Jort, it is then ;; £~~~STt t~~~n~~~~t~~ ~o '~~:"'~~AtI~~g:l.a~h~!I~~\ t n~~c~~~~~\~~~~ SERIAL]ORT: ~~X ~I SBUF 628 . ~ m ...."" Check whetbeI RI OI TI caused the interrupt MOV SBUF, A POP PSII POP ACC RETI fXM: 625 626 627 POSH ACe PUSH PSli JNB RI, TXH the CLR TI POP PSW POP ACC RETI fND REGISTER BANK (5) USED: 0 ASSEMBLY CO/olPLETE, NO ERRORS FOUND 270531-19 MeS-51 MACRO ASSEMBLER SWPORT 01/01/80 cl PAGE DOS 3.20 (038-N) MeS-51 MACRO ASSEMBLER, V2.2 OBJECT MODULE PLACED IN SWPORT.OBJ ASSEMBLER INVOKED BY: C: IAEDITIASM51.EXE SWPORT. TR LOC OBJ LINE 1 2 0000 0000 020036 f\) N w <0 0023 0023 02014B 0033 0033 0200DO 0003 OOOB 0013 0004 00 DC 0014 0034 0044 0054 0035 0045 0055 0036 0046 0056 0037 0041 3 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 IB4 185 186 187 IBB 189 190 191 192 193 194 195 196 197 198 SOURCE I NOMOD51 NOSYMBOLS NOLIST This ll[ogram tests the transmit routines for the software serial port. To inItialize the first transmission, the compare values are loaded before the peA timer is started. Successive interrupts are generated every bit time by the software timer. , For test purposes, the data transmitted increments from 00 to FF hex. -Dummy· termInals receive these bytes and display the bytes as they are incremented. 6RG DOH LJHP INIT_TXM 6RG 0023H LJHP SERIAL PORT Serial port interrupt 6RG 0033H LJHP TRANSMIT peA . » .... m ~ software timer interrupt VARIABLES USED BY THE SOFTWARE SERIAL PORT fxH START BIT 0 BIT BIT BIT 20H.3 21H.3 22H.3 Indicates start bit has been transmitted BIT BIT BIT 20H.4 21H.4 22H.4 Indicates transmit is in progress DATA DATA DATA 34H 44H 54H Software transmit -SBUF- DATA DATA DATA 35H 45H 55H Temporary register for transmitting bits TXICREG:2 TxM COUNT 0 TXH-COUNT-l TXM:COUNT::2 DATA DATA DATA 36H 46H 56H Counter for transmitting bits 6ATA 0 DATA:l DATA DATA 37H 47H Register used for the test program TX~START"Hrl TXICSTART:BIT:2 TXM IN PROGRESS 0 TX~IN"'ROGRESS-l TXICIDROGRESS:2 hH BUF 0 TX~BUrl TXICBUC 2 fxH REG 0 TX~RE<>1 270531-20 HCS-51 MACRO ASSEHBLER LOC OBJ 0057 0049 002C 0002 0036 75815F 0039 003C 003F 0042 0045 150900 750800 75F900 15E900 750049 0048 15A8D8 I\J N 0 """ 004B 004E 0051 0054 159850 15CBFF 15CACC 15C834 0051 C203 0059 C20B 005B C213 0050 C204 005F C20C 0061 C214 0063 153400 0066 154400 0069 155400 006C 153500 006F 154500 0012 755500 0015 153600 0078 754600 007B 755600 007& 7537FF 0081 7547FF 0084 7557FF 0087 75E02C 008A 75FD02 0080 020E SWPORT 01/01/80 LINE SOURCE 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 211 218 219 220 221 222 223 224 225 226 221 228 229 230 231 232 233 234 235 236 231 238 239 240 241 242 243 244 245 246 241 248 249 250 251 252 253 DATA 2 DATA 57H ~- W- TIMER EQU 49H FULL BIT LOW FULL-BITI!IGH EOU EOU 2CH 02H - - - cl PAGE Software timer mode for the ~~Tla~r{C~l~C~ 22g~le 2400 Baud at 16 HHz INITIALIZATION {NIT TXH: - HOV SP, 15FH (Compatible with receive routines) HOV CHOD, lOOH Increment PCA timer @ 1/12 osc. freq. Clear all status flags HOV CL, lOOH HOV CCAPH3, IS_W_TlHER Module 3 configured as software timer Wo~ g~~N~O~~OH IN IT SP: - HOV IE, lOD8H Initialize all needed interrupts ~g~ ~m~H~5~gFFH Serial port in mode 1 (a-bit UART) Reload values for 9600 Baud @ 16 MHz HOV RCAP2L, lOCCH HOV T2CON, f34H iNIT- FLAGS: ):00 Timer 2 as a baud-rate generator, turn Timer 2 on m I .... ~ CLR TXM START BIT 0 CLR TXtrSTARTI!IT-1 CLR TXICSTART:BlT:2 CLR TXM IN PROGRESS 0 CLR TXtrIN-PROGRESS-1 CLR TXICIN~ROGRESS:2 MOV TXM BUF 0, lOOH MOV TXtrBU,l, lOOH HOV TXICBUr:2, lOOH MOV TXM REG 0, lOOH MOV TXtrREb"l._ lOOH HOV TXICRE~2, lOOH MOV TXH COUNT 0, lOOH MOV TxtrCouNrl, lOOH HOV TXH:COUNT:2, lOOH HOV DATA 0, JOFFH HOV DATA-I, JOFFH HOV DATA:2, 10FFH HOV CCAP3L, 12CH HOV CCAP3H, 102H SETB CR Cause the first software timer to interrupt one bit time after peA timer is started 270531-21 ( MCS-51 HACRO ASSEMBLER LOC OBJ 008F 02009D I\:) '" ::: 0092 0095 0098 009B 300408 300C16 301424 80F5 009D 009F OOAI OOM 00A1 OOM OOAC C203 0531 853134 853435 153609 D204 80E4 OOAE OOBa 00B2 00B5 00B8 OOBB OOBD C20B 0541 854744 854445 154609 D20C 80D3 OOBF OOCI 00C3 00C6 00C9 OOCC OOCE C213 0551 855754 855455 155609 D214 80C2 0000 0002 0004 0006 COED COOO C20D 30041E 0009 200301 oooe e2B2 OODE 0203 ODED 0200n LINE 254 255 256 251 258 259 260 261 262 263 264 265 266 261 268 269 210 211 212 273 274 275 276 277 278 279 280 281 282 283 284 285 286 281 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 301 308 SWPORT 01/01/80 PAGE SOURCE HAIN TEST ROUTINE - TRANSMIT BITS ; fIRST_TXM: ~IN- TXM: JHP T)'M_ON_O JNB JNB JNB JHP TXM IN PROGRESS 0, TXM ON 0 TXtrINt>ROGRESS-l, TXtrO"l TXtrINt>ROGRESS-2, TXtrON-2 HAIR_TIM - - Determine if ready to send next byte. (Le. transmit 'not' in pro~ress) Waiting for TI' flag ; TIM ON 0: - - fxM_ON_l: fXM_ON_2: eLR TXM START BIT 0 INC OATlt 0 MOV TXM BUr 0, DATA 0 MOV TXtrREG""O, TXM Bur 0 HOV TxtreOURT 0, .U9H SETB TXII IN PROGRESS 0 JHP HAIICTXH - ~~:~~mf!:ro~rom previous Load 'SBur' with data byte 8 data bits + 1 stop bit CLR INC MOV MOV TXM START BIT 1 DATA 1 TXM Bur I, DATA 1 TXtrREG""l, TXM BUr 1 ~~BT~fRC~gw~R~GJ~~H 1JMP HAIN:TXH - CLR INC HOV HOV » aJ I ...""" TXM START BIT 2 OATlt 2 TXM BUr 2, DATA 2 TXtrREG""2, TXM BUr 2 ~BT~fRc~gwM/;J~~H2- JMP HAIICTXII - PCA INTERRUPT ROUTINE - TRANSMIT BITS fRANSMIT: PUSH ACC PUSH PSII Clear s/v timer interrupt CLR CCF3 JNB TXH_IN]ROGRESS_O,TRANSHIT 1 ; Check which channel is transmitting CHANNEL 0 TRANSMIT 0: - JB TXM_START_BIT_O, TXM_BYTE_O CLR P3.2 SETB TXH START BIT 0 JHP TRANSMIT_J- - If start bit has been sent, continue transmitting data bits, otherwise transmit start bit Signify start bit sent Check next transmit pin 270531-22 HCS-51 MACRO ASSEMBLER LaC OBJ 00E3 053601 00E6 02B2 00E8 C204 OOEA 0200F1 OOEO OOEF OOFO 00F2 00F4 00F1 OOFA OOFD DOFF 0101 E535 13 92B2 F535 0200n 300CI! 200B07 C2B3 D20B 020118 0104 054601 I\) , ~ I\) 0107 D2B3 0109 C20C 010B 020118 010E 0110 0111 01U Oll5 • 0118 011B 011E 0120 0122 E545 13 92B3 F545 020118 30141E 201301 C2B4 D213 020139 0125 D55607 0128 D2B4 012A C2l4 012C 020139 o12F OIlI 0132 0114 0136 E555 13 92B4 F555 020139 SIIPORT LINE 309 310 311 312 313 314 315 316 311 318 319 320 321 322 323 324 325 326 321 328 329 330 331 332 333 334 335 ill 331 338 339 340 341 342 343 01/01/80 l PAGE SOURCE TXM B~TE 0: -TXM STOP 0: -i TXM DATA 0: -; ; i i TRANSMIT 1: - OJNZ TXM_COUNT_O, TXM_DATA_O SETB P3.2 CLR TXM_IN_PROGRESS_O If bit count eguals I thru 9, Transmit data tiits (8 total) When bit count = D( transmit stop bit Indicate transmisSlon is finishea and JHP TRANSMIT_I ~~:~I !~~t n~~~n~~I~ HOV A, TXM REG 0 -RRCA HOV P3.2, C Transmit one bit at a time through the carry !>it ~.J mll~¥T~i A pin Save what I s not been sent Check next transmit pin CHANNEL 1 JNB TXM IN PROGRESS 1, TRANSMIT 2 ; Similar to TRANSMIT_O ~l~-;~TART_BIT_l, -TXM_BYTE_I - SETB TXM START BIT 1 JHP TRANSMIT_ai TXM BYTE 1: ,TXM STOP 1: -i TXM DATA 1: -- OJNZ TXM_COUNT_I, TXM_DATA_I l> OJ SETB Pl.3 CLR TXM IN PROGRESS 1 JHP TRAlISMIT_ 2 - ....;.. HOV A, TXM REG 1 RRCA -MOV P3.3, C ~ ~~M~¥T~~ A CHANNEL 2 344 i 346 341 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 TRANSMIT 2: - M5; , TXM BYTE 2: ; TXM STOP 2: -i TXM DATA 2: -- :::BTi~KSiMR~~~~~XHT~MXF CLR P374 SETB TXM START BIT 2 JHP TXM_EXIT - i Similar to TRANSMIT_O -- DJNZ TXM_COUNT_2, TXM_DATA_2 SETB P3.4 CLR TXM IN PROGRESS 2 JHP TXJCEXIT ~~ ~, TXM_REG_2 HOV P3.4, C HOV TXM REG 2, A JHP TXICEXIT 270531-23 ( MCS-51 MACRO ASSEMBLER * LOC OBJ LINE 0139 013A 013C OI3E 0140 0142 0144 0146 0148 OHA C3 742C 25Eo F5Eo 7402 35FD F5Fo DODO ODED 32 364 365 366 367 368 369 370 014B 0140 OHF 0152 0154 0156 0158 015A 015C COED COOO 30980B E599 C298 F599 DODO ODED 32 0150 015F 0161 0163 C299 DODO ODED 32 SWPORT ~OO PAGE SOURCE TXH_EXIT: CLR C HOV A, 'FULL BIT LOW ~ge ~CA~~t; 3i - Update coml'are value with full bit tUIe = 22CH HOV A, 'FULL BIT HIGH AoDC A, CCAP3H HOV CCAP3H, A POP PSW POP ACC RETI 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 01/01/80 , SERIAL PORT INTERRUPT ; When a byte is received on the full-duplex serial port, it is then ; transmitted back to -a -dummy· terminal. This terminal checks that the byte it transmitted to the PCA is the same value it receives back. .... ~ ~ SERIAL PORT: - PUSH ACC PUSH PSW JNB RI, TXH HOV A, SBUF CLR RI HOV SBUF, A POP PSW POP ACC RETI TXK: CLR TI POP PSW POP ACC RETI , OJ ".. Check whether RI or TI caused the interrupt END REGISTER BANK(S) USED: 0 ASSEMBLY COMPLETE, NO ERRORS FOUND 270531-24 inter APPLICATION NOTE AP-415 July 1988 83C51FA/FB PCA Cookbook . . BETSY JONES ECO APPLICATIONS ENGINEER @ Intel Corporation, 1988 Order Number: 270609-001 2-244 inter AP·415 This application note illustrates the different functions of the Programmable Counter Array (PCA) which are available on the 83C51FA and 83C51FB. Included are cookbook samples of code in typical applications to simplify the use of the PCA. Since all the examples are written in assembly language, it is assumed the reader is familiar with ASM51. For further information on these products or ASM5l refer to the Embedded Controller Handbook (Vol. I). Each of the five modules can be programmed in any one of the following modes: - Rising and/or Falling Edge Capture - Software Timer - High Speed Output - Watchdog Timer (Module 4 only) - Pulse Width Modulator. PCA OVERVIEW All of these modes will be discussed later in detail. However, let's first look at how to set up the PCA timer and modules. The major new feature on the 83C51FA and 83C51FB is the Programmable Counter Array. The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improVed accuracy. The PCA consists of a dedicated timer/counter which serves as the time base for an array of five compare/ capture modules. Figure I shows a block diagram of the PCA. Notice that the PCA timer and modules are all 16-bits. If an external event is associated with a module, that function is shared with the corresponding Port 1 pin. If the module is not using the port pin, the pin can still be used for standard I/O. PCA TIMER/COUNTER The timer/counter for the PCA is a free-running 16-bit timer consisting of registers CH and CL (the high and low bytes of the count values). It is the only timer which can service the PCA. The clock input can be selected from the following four modes: . oscillator frequency -;- 12 (Mode 0) - oscillator frequency -;- 4 (Mode 1) '- Timer 0 overflows (Mode 2) - external input on P1.2 (Mode 3) - 16 BITS EACH ..... MODULE 0 P1.3 MODULE 1 PIA MODULE 2 P1.5 MODULE 3 P1.6 MODULE 4 Pl.7 -16BITS-PCA TIMER/COUNTER 270609-1 Figure 1. PCA Timer/Counter and Compare/Capture Modules 2-245 inter AP-415 The table below summarizes the various clock inputs for each mode' at two common frequencies. In Mode 0, the clock input is simply a machine cycle count, whereas in Mode 1 the input is clqcked three times faster. In Mode 2, Timer 0 overflows are counted allowing for a range of slower inp~ts to the timer. And finally, if the input is external the PCA timer counts I-to-O transitions with the maximum clock frequency equal to 1/. x oscillator frequency. Table 1. PCA Timer/Counter Inputs Clock Increments PCA Timer/Counter Mode 12MHz 16 MHz Mode 0: fosc 112 1 p.sec 0.75 p.sec Mode 1: fosc 14 330 nsec 250 nsec Mode 2*: Timer 0 Overflows Timer 0 programmed in: B-bitmode 16-bit mdoe B-bit auto-reload 256 p.sec 65 msec 1 to 255 p.sec 192 p.sec 49 msec 0.75 to 191 p.sec Mode 3: External Input MAX 0.66 p.sec 0.50 p.sec "In Mode 2, the overflow interrupt for Timer 0 does not need to be enabled. Special Function Register CMOD contains the Count Pulse Select bits (CPS! and CPSO) to specify the PCA timer input. This register also contains the ECF bit which enables an interrupt when the counter overflows. In addition, the user has the option of turning ofT the PCA timer during Idle Mode by setting the Counter Idle bit (CIDL). This can further redl!ce power consumption by an additional 30%. . CMOD: Counter Mode Register I CIDL I WOTE I CPS1 Address = 009H Not Bit Addressable CPSO ECF Reset Value = OOXX XOOOB NOTE: The user should write Os to unimplemented bits. These bits may be used in future MeS-51 products to invoke new features, and in that case the inactive value of the new bit will be O. When read, these bits must be treated as don't-cares. Table 2 lists the values for CMOD in the four possible timer modes with and without the overflow interrupt enabled. This list assumes that the PCA will be left running during Idle Mode. Tabie 2. CMOD Values CMODvalue PCA Count Pulse Selected without interrupt enabled with interrupt enabled Internal clock, Fosc/12 OOH 01 H Internal clock, Foscl 4 02H 03H Timer 0 overflow 04H 05 H External clock at P1.2 06H 07H 2-246 AP-415 The CCON register shown below contains the Counter Run bit (CR) which turns the timer on or off. When the PCA timer overflows, the Counter Overflow bit (CF) gets set. CCON also contains the five event flags for the PCA modules. The purpose of these flags will be discussed in the next section. CCON: Counter Control Register I CF I CR I CCF4 CCF3 CCF2 CCF1 Address = 008H Bit Addressable CCFO Reset Value = OOXO OOOOB The PCA timer registers (CH and CL) can be read and written to at any time. However, to read the full 16-bit timer value simultaneously requires using one of the PCA modules in the capture mode and toggling a port pin in software. More information on reading the PCA timer is provided in the section on the Capture Mode. COMPARE/CAPTURE MODULES Each of the five compare/capture modules has a mode register called CCAPMn (n = 0, 1,2,3,or 4) to select which function it will perform. Note the ECCFn bit which enables an interrupt to occur when a module's event flag is set. CCAPMn: Compare/Capture Mode Register I I ECOMn I CAPPn I MATn CAPNn TOGn PWMn ECCFn Reset Value = XOOO OOOOB Address = OOAH (n = 0) OOBH (n= 1) OOCH (n=2) OOOH (n=3) OOEH (n=4) Table 3 lists the CCAPMn values for each different mode with and without the PCA interrupt enabled; that is, the interrupt is optional for all modes. However, some of the PCA modes require software servicing. For example, the Capture modes need an interrupt so that back-to-back events can be recognized. Also, in most applications the purpose of the Software Timer mode is to generate interrupts in software so it would be useless not to have the interrupt enabled. The PWM mode, on the other hand, does not require CPU intervention so the interrupt is normally not enabled. Table 3. Compare/Capture Mode Values CCAPMn Value Module Function Capture Positive only without interrupt enabled with interrupt enabled 20H 21 H Capture Negative only 10H 11 H Capture Pos. or Neg. 30H 31 H Software Timer 48H 49H High Speed Output 4CH 40H Watchdog Timer Pulse Width Modulator 48 or4C H - 42H 43H 2-247 AP·415 It should be mentioned that a particular module can change modes within the program. For example, a module might be,used to sample incoming data. Initially it could be set up to capture a falling edge transition. Then the same module can be reconfigured as a software timer to interrupt the CPU-at regular intervals and sample the pin. Each module also has a pair of 8-bit compare/capture registers (CCAPnH, CCAPnL) associated with it. These registers are used to store the time when a capture event occurred or when a compare event should occur. Remember, event times are based on the free-running PCA timer (CH and CL). For the PWM mode, the high byte register CCAPnH controls the duty cycle of the waveform. When an event occurs, a flag in CCON is set for the appropriate module. This register is bit addressable so that event flags can be checked individually. CCON: Counter Control Register CF I CR Address = 008H Bit Addressable I CCF3 CCF4 1 CCF2 CCF1 CCFO ResetValue = OOXO OOOOB These five event flags plus the PCA timer overflow flag share an interrupt vector as shown below. These flags are not cleared when the hardware vectors to the PCA interrupt address (OO33H) so that the user can determine which event caused the interrupt. This also allows the user to defme the priority of servicing each module. cr~ ccrn ~ PCA INTERRUPT 5 270609-2 Figure 2. PCA Interrupt An additional bit was added to the Interrupt Enable (IE) register for tlie PCA interrupt. Similarly, a high priority bit was added to the Interrupt Priority (IP) register. IE: Interrupt Enable Register I EA 1 EC 1 ET2 ES ET1 EX1 Address = OA8H Bit Addressable ETa Reset Value I= EXO 0000 OOOOS IP: Interrupt Priority Register I 1 PPC Address = OB8H Sit Addressable 1 PT2 PS PT1 PX1 PTa PXO Reset Value = XOOO OOOOB Remember, each of the six possible sources for the PCA interrupt must be individually enabled as well-in the CCAPMn register for the modules and in the CCON register for the timer. 2-248 inter AP-415 CAPTURE MODE Measuring Pulse Widths Both positive and negative transitions can trigger a capture with the PCA. This allows the PCA flexibility to measure periods, pulse widths, duty cycles, and phase differences on up to five separate inputs. This section gives examples of all these different applications. To measure the pulse width of a signal, the PCA module must capture both rising and falling edges (see Figure 4). The module can be programmed to capture either edge if it is known which edge will occur first. However, if this is not known, the user can select w'hich edge will trigger the first capture by choosing the proper mode for the module. Figure 3 shows how the PCA handles a capture event. Using Module 0 for this example, the signal is input to PJ.3. When a transition is detected on that pin, the 16bit value of the PCA timer (CH,CL) is loaded into the capture registers (CCAPOH,CCAPOL). Module O's event flag is set and an interrupt is flagged. The interrupt will then be generated if it has been properly enabled. In the interrupt service routine, the l6-bit capture value must be saved in RAM before the next event capture occurs; a subsequent capture will write over the first capture value. Also, since the hardware does not clear the event flag, it must be cleared in software. Listing 1 shows an example of measuring pulse widths. (It's assumed the incoming signal matches the one in Figure 4.) In the interrupt routine the first set of capture values are stored in RAM. After the second capture, a subtraction routine calculates the pulse width in units of PCA timer ticks. Note that the subtraction does not have to be completed in the interrupt service routine. Also, this example assumes that the two capture events will occur within 216 counts of the PCA timer, i.e. rollovers of the PCA timer are not counted. ~ t t The time it takes to service this interrupt routine determines the resolution of back-to-back events with the same PCA module. To store two 8-bit registers and clear the event flag takes at least 9 machine cycles. That includes the call to the interrupt routine. At 12 MHz, this routine would take less than 10 microseconds. However, depending on the frequency and interrupt latency, the resolution will vary with each application. CAPTURE 1 CAPTURE 2 270609-4 Time (Capture 2) - Time (Capture 1) = Pulse Width Figure 4. Measuring Pulse Width PCA TIMER MODULE 0 PCA INTERRUPT INTERRUPT SERVICE ROUTINE EXIT Figure 3. PCA Capture Mode (Module 0) 2-249 270609-3 AP-415 Listing 1. Measuring Pulse Widths , RAM locations to store capture values DATA 30H CAPTURE PULSE_WIDTH DATA 32H FLAG BIT 20H.0 ORG OOOOH JMP PCA_INIT ORG 0033H JMP PCA~INTERRUPT , PCA-INIT: MOV CMOD, #OOH MOV CH, #OOH MOV CL, #OOH Initialize PCA timer Input to timer 1/12 X Fosc = Initialize Module 0 in capture mode ' MOV CCAPMO, #21H Capture positive edge first for measuring pulse width SETB EC SETB EA SETB CR CLR FLAG Enable PCA interrupt Turn PCA timer on clear test flag •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• Main program goes here ** •••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••• , This example assumes Module 0 is the only PCA module being used. If other modules are used, software must check which module's event caused the interrupt. PCA_INTERRUPT: CLR CCFO JB FLAG, SECOND_CAPTURE FIRST_CAPTURE: MOV CAPTURE, CCAPOL MOV CAPTURE+l, CCAPOH MOV CCAPMO, #llH , SETB FLAG RETI SECOND_CAPTURE: PUSH ACC PUSH PSW CLR C MOV A, CCAPOL SUBB A, CAPTURE MOV PULSE_WIDTH, A MOV A, CCAPOH SUBB A, CAPTURE+l MOV PULSE_WIDTH+l, A Clear Module O's event flag Check if this is the first capture or second Save la-bit c'apture value in RAM Change module to now capture falling edges Signify 1st capture complete la-bit subtract la-bit result stored in two a-bit RAM locations , MOV CCAPMO, #21H CLR FLAG POP PSW POP ACC RETI Optional--needed if user wants to measure next pulse width 2-250 AP-415 Measuring Periods Measuring Frequencies Measuring the period of a signal with the peA is similar to measuring the pulse width. The only difference will be the trigger source for the capture mode. In Figure 5, rising edges are captured to calculate the period. The code is identical to Listing I except that the capture mode should not be changed in the interrupt routine. The result of the subtraction will be the period. Measuring a frequency with the peA capture mode involves calculating a sample time for a known number of samples. In Figure 6, the time between the first capture and the "Nth" capture equals the sample time T. Listing 2 shows the code for N = 10 samples. It's assumed that the sample time is less than 216 counts of the peA timer. s-L..rL j.-------.j t CAPTURE 1 ~---------- t CAPTURE 2 T ----------~ t t CAPTURE 1 CAPTURE N 270609-6 Time (Capture N) - Time (Capture 1) = T N # of Samples 270609-5 Time (Capture 2) - Time (Capture 1) = Period Figure 5. Measuring Period Frequency = T = Sample Time Figure 6. Measuring Frequency 2-251 inter AP-415 Listing 2. Measuring Frequencies RAM locations to store capture values DATA CAPTURE 30H DATA PERIOD 32H SAMPLE_COUNT DATA 34H FLAG BIT 20H.0 ORG JMP ORG JMP OOOOH PCA_INIT 0033H PCA_INTERRUPT PCA_INIT: Initialization of PCA timer, Module 0, and interrupt is the same as in Listing 1. Also need to initialize the sample count. = MOV SAMPLE_COUNT, #lOD ; N 10 for this example ' . *_._ ......... _................ _-_. , __ ._ .... * •••••• _•••••• _•• -_ •• ............... , program goes here -.............. .. -•..•....•..•• -........ ... ... ...... ........... _._Main........ ; _ _ _ This code assumes only Module 0 is being used. PCA_INTERRUPT: CLR CCFO ; Clear module O's event flag JB FLAG, NEXT_CAPTURE FIRST_CAPTURE: MOV CAPTURE, CCAPOL MOV CAPTURE+l, CCAPOH SETB FLAG RETI NEXT_CAPTURE: DJNZ SAMPLE_COUNT, EXIT PUSH ACC PUSH PSW CLR C ' MOV A, CCAPOL SUBB A, CAPTURE MOV PERIOD, A MOV A, CCAPOH SUBB A, CAPTURE+l MOV PERIOD+l, A MOV ~AMPLE_COUNT. #lOD CLR FLAG POP PSW POP ACC EXIT: RET I Signify first capture complete IS-bi t subtraction Reload for next period 2-252 _ inter AP-415 The user may instead want to measure frequency by counting pulses for a known sample time. In this case, one module is programmed in the capture mode to count edges (either rising or falling), and a second module is programmed as a software timer to mark the sample time. An example of a software timer is given later. For information on resolution in measuring frequencies, refer to Article Reprint AR-517, "Using the 8051 Microcontroller with Resonant Transducers," in the Embedded Controller Handbook. Measuring Duty Cycles To measure the duty cycle of an incoming signal, both ri~ing and falling edges need to be captured. Then the duty cycle must be calculated based on three capture values as seen in Figure 7. The same initialization routine is used from the previous example. Only the peA interrupt service routine is given in Listing 3. ~ t t t CAPTURE 1 CAPTURE 2 CAPTURE 3 270609-7 pt;.:u;..;re;..;2o:.l_--:::T;;.im;;.e-,(,=C.:;aP im;;.e;;.(:,:C,.:;a:::. Tc:::..t.:;ur;.:e--:-:-1l I = = pulse width = dutycyce Time (Capture 3) - Time (Capture 1) period Figure 7. Measuring Duty Cycle Listing 3. Measuring Duty Cycle RAM locations to store capture CAPTURE DATA PULSE_WIDTH DATA PERIOD DATA FLAG_I BIT FLAG_2 BIT ORG JMP ORG JMP values 30H 32H 34H 20H.0 20H.I OOOOH PCA_INIT 0033H PCA_INTERRUPT PCA_INIT: Initialization for PCA timer, module, and interrupt the same as in Listing 1. Capture positive edge first, then either edge. ....... ... ,..••••...••.•........• - _ _..•....•..•.•............••.....•.•..• ; Main program goes here ,•• *•• ****.***.* ••• *.*.*** •••• *•• ** ••• *****.*~.****.*** ••••••••••••••••••• , , ; This code assumes only Module 0 is being used. PCA_INTERRUPT: CLR CCFO Clear Module O's event flag JB FLAG_I, SECOND_CAPTURE FIRST_CAPTURE: MOV CAPTURE, CCAPOL MOV CAPTURE+I, CCAPOH SETB FLAG_I MOV CCAPMO, #31H RETI Signify first capture complete Capture either edge now 2-253 inter AP-415 Listing 3. Measuring Duty Cycle (Continued) SECOND_CAPTURE: PUSH ACC PUSH PSW . JBFLAG_2', THIRD_CAPTURE CLR C Calculate pulse width MOV A, CCAPOL rlS-bit subtract SUBB A, CAPTURE MOV PULSE_WIDTH, A MOV A, CCAPOH SUBB A, CAPTURE+I MOV PULSE_WIDTH+I, A SETB FLAG_2 Signify second capture complete POP PSW POP ACC RETI THIRD_CAPTURE: CLR C MOV A, CCAPOL SUBB A, CAPTURE MOV PERIOD, A MOV A, CCAPOH SUBB A, CAPTURE+I MOV PERIOD+I, A MOV CCAPMO, #21H CLR FLAG_I CLR FLAG_2 POP PSW POP ACC RETI Calculate period IS-bit subtract Optional - reconfigure module to capture positive edges 'for next cycle After the third capture, a 16-bit by 16-bit divide routine needs to be executed. This routine is located in Appendix B. Due to its length, it's up te the user whether the divide routine should be cdmpleted in the interrupt routine or be called as a subroutine .from the main program. between twe or more signals. Fer this example, two signals are input to Modules 0 and 1 as seen in Figure 8. Both modules are programmed to capture rising edges only. Listing 4 shows the code needed to measure the difference between these two signals. This code does not assume .one signal is leading or lagging the other. Measuring Phase Differences Because the PCA modules share the same time base, the PCA is useful for measuring the phase difference t.40DULE 0 --I CAPTURE 1 MODULE 1 r" U L CAPTURE 2 - 270609-8 ASS [Time (Capture 2) - Time (Capture 1)1 = Phase Difference Figure 8. Measuring Phase Differences 2-254 AP-415 Listing 4. Measuring Phase Differences RAM locations to store capture CAPTURE_O DATA CAPTURE_l DATA DATA PHASE FLAG_O BIT FLAG_l BIT ORG JMP ORG JMP values 30H 32H 34H 20H.0 20H.l OOOOH PCA_INIT 0033H PCA_INTERRUPT PCA_INIT: Same initialization for PCA timer, and interrupt as in Listing 1. Initialize two PCA modules as follows: , MOV CCAPMO, #2lH MOV CCAPMl, #2lH Module 0 capture rising edges Module 1 same ,.************************************************************************************** ; Main program goes here ,.************************************************************************************** ; This code assumes only Modules 0 and 1 are being used. PCA_INTERRUPT: JB CCFO, MODULE_O Determine which module's JB CCFl, MODULE_l event caused the interrupt MODULE_O: CLR CCFO MOV CAPTURE_O, CCAPOL MOV CAPTURE_O+l, CCAPOH JB FLAG_I, CALCULATE_PHASE SETB FLAG_O RETI Clear Module O's event flag Save l6-bit capture value If capture complete on Module I, go to calculation Signify capture on Module 0 2-255 inter AP-415 LIsting 4. Measuring Phase Differences (Continued) MODULE_l: CLR CCF_l MOV CAPTURE_l, CCAP1L MOV CAPTURE_l+l, CCAP1H JB FLAG_O, CALCULATE_PHASE SETB FLAG_l RET! Clear Module l's event flag If oapture oomplete on ; Module 0, go to oaloulation ; Signify oapture on Module 1 ; CALCULATE_PHASE: PUSH ACC PUSH PSW CLR C ; This oaloulation does not ; have to be oompleted in the ; interrupt servioe routine JB FLAG_O, MODO_LEADING JB FLAG_l, MOD1_LEADING ; MODO_LEADING: MOV'A, CAPTURE_l SUBB A, CAPTURE_O MOV PHASE, A MOV A, CAPTURE_l+l SUBB A, CAPTURE_O+l MOV PHASE+l, A CLR FLAG_O JMP EXIT ; MOD;L_LEADING: MOV A,CAPTURE_O SUBB A, CAPTURE_l MOV PHASE, A MOV A, CAPTURE_O+l SUBB A, CAPTURE_l+l MOV PHASE+l, A CLR FLAG_l EXIT: POP PSW POP ACC RETI 2-256 inter AP-415 Readjng the PCA Timer SOFTWARE TIMER Some applications may require 'that the PCA timer be read instantaneously as a real-time event. Since the timer consists of two 8-bit registers (CH,CL), it would normally take two MOV instructions to read the whole timer. An invalid read could occur if the registers rolled over in the middle of the two MOVs. In most applications a software timer is used to trigger interrupt routines which must occur at periodic intervals. Figure 9 shows the sequence of events for the Software Timer mode. The user preloads a l6-bit value in a module's compare registers. When a match occurs between this compare value and the PCA timer, an event flag is set and an interrupt is flagged. An interrupt is then generated if it has been enabled. However, with the capture mode a l6-bit timer value can be loaded into the capture registers by toggling a port pin. For example, configure Module 0 to capture falling edges and initialize P1.3 to be high. Then when the user wants to read the PCA timer, clear P1.3 and the full l6-bit timer value will be saved in the capture registers. It's still optional whether the user wants to generate an interrupt with the capture. Ifnecessary, a new l6-bit compare value can be loaded into (CCAPOH, CCAPOL) during the interrupt routine. The user should be aware that the hardware temporarily disables the comparator function while these registers are being updated so that an invalid match will not occur. That is, a write to the low byte (CCAPnO) dis- ables the comparator while a write to the high byte (CCAPOH) re-enables the comparator. For this reason, user software must write to CCAPOL first, then CCAPOH. The user may also want to hold off any interrupts from occurring while these registers are being updated. This can easily be done by clearing the EA bit. See the code example in Listing 5. COMPARE MODE In this mode, the l6-bit value of the PCA timer is compared with a l6-bit value pre-loaded in the module's compare registers. The comparison occurs three times per machine cycle in order to recognize the fastest possible clock input, i.e. 'I. x oscillator frequency. When there is a match, one of three events can happen: (1) an interrupt - Software Timer mode (2) toggle of a port pin - High Speed Output mode (3) a reset - Watchdog Timer mode. Examples of each compare mode will follow. CH CL ~ COMPARATOR it.. ....._C_H..........._C_L....... 1I ,--C_H--L_CL...... COMPARATOR PCA TIMER MATCH i I PERIOD. ;'*** •••••••• **••• ****,.***...................... ,*............................................,**, •••• DUTY_CYCLE_CALCULATION: MOV A,PERIOD+1 CJNE A,PUlSE_WIDTH+1,NOT_EQUAl MOV A,PERIOD CJNE A,PUlSE_WIDTH,NOT_EQUAl 270609-35 2-283 inter AP-415 EQUAL: SETB C MOV DUTY_CYCLE~ CLR OV RET NOT EQUAL: - JNC CONTINUE SETB OV RET CONTINUE: MOV MOV MOV R2,#8 DUTY_CYCLE~O R3,1IO TIMES_lWO: MOV A,PULSE_WIDTH RLC A MOV PULSE_WIDTI'I,A MOV A,PULSE_WIDTH+1 RLCA MOV PULSE_WIDTH+1,A MOV A,R3 RLC A ,",OV R3,A COMPARE: CJNE RS,IIO,DONE MOV A,PULSE_WIDTH+1 CJNE A,PERIOD+1,DONE MOV A,PULSE_WIDTH CJNE A,PERIOD,DONE DONE: CPL C BUILD_DUTY_CYCLE: MOV A,DUTY_CYCLE RLC A MOV DUTY_CYCLE,A JNB ACC.O,LOOP CONTROL SUBTRACT: MOV A,PULSE_WIDTH SUBB A,PERIOD MOV PULSE_WIDTH,A MOV A,PULSE_WIDTH+1 SUBB A,PERIOD+1 MOV PULSE_WIDTH+1,A MOV A,R3 SUBB A,IIO MOV R3,A LOOP_CONTROL: DJNZ R2,TIMES_lWO 270609-36 2-284 inter AP·415 FINAL TIMES TWO: -MOV -A,PULSE_WIDTH RLC A MOV PULSE_WIDTH,A MOV A,PULSE_WIDTH+l RLC A MOV PULSE_WIDTH+l,A MOV A,R3 RLC A MOV R3,A FINAL_COMPARE: CJNE R3,11O,FINAL_DONE MOV A,PULSE_WIDTH+l CJNE A,PERIOD+l,FINAL_DONE MOV A,PULSE_WIDTH CJNE A,PERIOD,FINAL_DONE FINAL_DONE: JC CONVERT_TO_BCD MOV A,DUTY_CYCLE ADD A,1II1 MOV DUTY CYCLE,A JNC CONVERT_TO_BCD CLR OV RET CONVERT_TO_BCD: MOV A,DUTY_CYCLE MOV B,1II10 MUL AB XCH A,B SWAP A MOV DUTY_CYCLE,A MOV A,1II10 MUL AB XCH A,B ORL DUTY_CYC