1990_Intel_Embedded_Applications_Handbook 1990 Intel Embedded Applications Handbook
User Manual: 1990_Intel_Embedded_Applications_Handbook
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Intel the Microcomputer Company:
When Intel invented the microcomputer in 1971, it created the era of microcomputers. Whether
used in embedded applications such as automobifes or microwave ovens, or as the CPU in
personal computers or supercomputers, Intel's microcomputers have always offered leading-edge
technology. Intel continues to strive for the highest standards in memory, microcomputer
components, modules and systems to give its customers the best possible competitive advantages.
EMBEDDED APPLICATIONS
HANDBOOK
1990
-
Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may
appear In this document nor does it make a commitment to update the information contained herein.
Intel retains the right to make changes to these specifications at any time, without notice.
Contact your local sales office to obtain the laiest specifications before placing your order.
The following are trademarks of Intel Corporation and may only be used to identify Intel pro~ucts:
376, 386, 387,486, 4-SITE, Above, ACE51, ACE96, ACE186, ACE196, ACE960,
BITBUS, COMMputer, CREDIT, Data Pipeline, DVI, ETOX, FaxBACK, Genius, i, t,
i486, i750, i860, ICE, iCEL, ICEVIEW, iCS, iDBP, iDIS, 12 1CE, iLBX, iMDDX, iMMX,
Inboard, h;site, Intel, intel, Intel386, intelBOS, Intel Certified, Intelevision, in!aligent
Identifier, inteligent Programming, Intellec, Intellink, iOSP, iPAT, iPDS, iPSC, iRMK,
iRMX, iSBC, iSBX, iSDM, iSXM, Ubrary Manager, MAPNET, MCS, Megachassis,
MICROMAINFRAME, MULTI BUS, MULTICHANNEL, MULTIMODULE, MultiSERVER,
ONCE, OpenNET, OTP, PR0750, PROMPT, Promware, QUEST, QueX, Quick-Erase,
Quick-Pulse Programming, Ripplemode, RMx/80, RUPI, Seamless, SLD,
SugarCube, ToolTALK, UPI, Visual Edge, VLSiCEL, and ZapCode, and the combination of ICE, iCS, iRMX, iSBC, iSBX, iSXM, MCS, or UPI and a numerical suffix.
MDS is an ordering code only and is not used as a product name or trademark. MDS® is a registered trademark of Mohawk
Data Sciences Corporation.
MULTI BUS is a patented Intel bus.
CHMOS and HMOS are patented processes of Intel Corp.
Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark or products.
Additional copies of this manual or other Intel literature may be obtained from:
Intel Corporation
Literature Sales
P.O. Box 7641
Mt. Prospect, IL 60056-7641
©INTEL CORPORATION 1989
CG·l01789
.,..
CUSTOMER SUPPORT
INTEL'S COMPLETE SUPPORT SOLUTION WORLDWIDE
Customer Support is Intel's complete support serVice that provides Intel customers with hardware support,
software support, customer trainin(l, consulting services and network management services. For detailed information contact your local sales offIces.
After a customer purchases any system hardware or software product, service and support become major
factors in determining whether that product will continue to meet a customer's expectations. Such support
requires an international support organization and a breadth of programs to meet a variety of customer needs.
As you might expect, Intel's customer support is quite extensive. It can start with assistance during your
development effort to network management. 100 Intel sales and service offices are located worldwide-in the
U.S., Canada, Europe and the Far East. So wherever you're using Intel technology, our professional staff is
within close reach.
HARDWARE SUPPORT SERVICES
Intel's hardware maintenance service, starting with complete on-site installation will boost your productivity
from the start and keep you running at maximum efficiency. Support for system or board level products can be
tailored to match your needs, from complete on-site repair and maintenance support to economical carry-in or
mail-in factory service.
Intel can provide support service for not only Intel systems and emulators, but also support for equipment in
your development lab or provide service on your product to your end-user/customer.
SOFIWARE SUPPORT SERVICES
Software products are supported by our Technical Information Service (TIPS) that has a special toll free
number to provide you with direct, ready information on known, documented problems and deficiencies, as
well as work-arounds, patches and other solutions.
Intel's software support consists of two levels of contracts. Standard support includes TIPS (Technical Information Phone Service), updates and subscription service (product-specific troubleshootmg guides and;
COMMENTS Magazine). Basic support consists of updates and the subscription service. Contracts are sold in
environments,which represent product groupings (e.g., iRMX® environment).
CONSULTING SERVICES
Intel provides field system engineering consulting services for any phase of your development or application
effort. You can use our system engineers in a variety of ways ranging from assistance in using a new product,
developing an application, personalizing training and customizing an Intel product to providing technical and
management consulting. Systems Engineers are well yersed in technical' areas such as microcommunications,
real-time applications, embedded microcontrollers, and network services. You know your application needs;
we know our products. Working together we can help you get a successful product to market in the least
possible time.
CUSTOMER TRAINING
Intel offers a wide range of instructional programs covering various aspects of system design and implementation. InJ·ust three to ten days a limited number of individuals learn more in a single workshop than in weeks of
self-stu y. For optimum convenience; workshops are scheduled regularly at Training Centers worldwide or we
can take our workshops to you for on-site instruction. Covering a wide variety of topics, Intel's major course
categories include: architecture and assembly language, programming and operating systems, BITBUS and
LAN applications.
TN
NETWORK. MANAGEMENT SERVICES
Today's networking products are powerful and extremely flexible. The return they can provide on your investment via increased productivity and reduced costs can be very substantial.
Intel offers complete network support, from definition of your network's physical and functional design, to
implementation, installation and maintenance. Whether installing your first network or adding to an existing
one, Intel's Networking Specialists can optimize network performance for you.
CG/CUSTSUPP/100389
-
-.
Table of Contents
MCS®-48 FAMILY
Chapter 1
MCS®-48 APPLICATION NOTES
AP-24
AP-40
AP-49
AP-55A
AP-91
Application Techniques for the MCS®-48 Family.. .... ...... ....... .... ...... ...... ... ....
Keyboard/Display Scanning with Intel's MCS®-48 Microcomputers. .... .........
Serial I/O and Math Utilities for the 8049 Microcomputer .... ........................
A High-Speed Emulatorforthe Intel MCS®-48 Microcomputers ...................
Using the 8049 as an 80 Column Printer Controller .. ...... ....... ..... ..... .... ... ... ...
1-1
1-25
1-50
1-73
1-173
MCS®-S1 FAMILY
Chapter 2
MCS®-S1 APPLICATION NOTES & ARTICLE REilRINTS
AP-69
AP-70
AP-223
AB-38
AB-39
AB-40
AB-12
AP-252
AP-410
AB-41
AP-415
AP-425
AP-429
An Introduction to the Intel MCS®-51 Single-Chip Microcomputer ....... ..........
Using the Intel MCS®-51 Boolean Processing Capabilities ...........................
8051 Based CRT Terminal Controller ........................... :..............................
Interfacing the 82786 Graphic Coprocessor to the 8051 ...............................
Interfacing the Densitron LCD to the 8051 .............................. ,....................
32-Bit Math Routines for the 8051 ...............................................................
Designing a Mailbox Memory for Two 80C31 Microcontrollers Using EPLDs
Designing with the 80C51 BH .......................................................................
Enhanced Serial Port on the 83C51 FA .............. ;.........................................
Software Serial Port Implemented with the PCA ..... ... ....... ..... ... ..... ....... .......
83C51 FAlFB PCA Cookbook ......................................................... :............
Small DC Motor Control . ... .............. ... .......... ..... ... ............ ... ... ....... ...... ... .....
Application Techniques for the 83C 152 Global Serial Channel in.
CSMAlCD Mode .. ... ....... ... .... ...... ....... ............ ....... ....... ................. .... ..... .....
AR-517 Using the 8051 Microcontrollerwith ResonantTransducers .........................
AR-526 Analog/Digital Processing with Microcontrollers .... :......................................
Chapter 3
.
2-1
2-31
2-76
2-153
2-159
2-166
2-175
2-189
2-213
2-221'
2-244
2-287
2-301
2-369
2-374
.
ASIC FAMILY APPLICATION NOTE & ARTICLE REPRINT
AP-413 Using Intel's ASIC Core Cell to Expand the Capabilities of an 80C51
Based System ........................... :... .... ..... .... ..... ... .......... ..... ....... ... ..... ...........
AR-537 A Fast-Turnaround, Easily Testable ASIC Chip for Serial Bus Control..........
3-1
3-11
THE RUPITM FAMILY
Chapter 4
RUPITM APPLICATION NOTES
AP-281 UPI-452 Accelerates 80286 Bus Perlormance .............................................
AP-283 RUPITM/Flexibility in Frame Size with the 8044 ................................:...........
80186/80188 FAMILY
ChapterS
80186/188 APPLICATION NOTES
AP-186
AP-258
AP-286
AB-36
AB-37
AB-31
AB-35
4-1
4-21
.
Using the 80186/188/C186/C188 Microprocessor ........................................
High Speed Numerics with the 80186/80188 and 8087 ................................
80186/188 Interface to Intel Microcontrollers ...............................................
80186/80188 DMA Latency ................. ,.......................................................
80186/80188 EFI Drive and Oscillator Operation .. ........ ..... ...... ....................
The 80C186/80C188 Integrated Refresh Control Unit ..................................
DRAM Refresh/Control with the 80186/188 '" ..... ..... ..... ...............................
vii
5-1
5-83
'5-99
5-129
5-132
5-134
5-147
.
Table of Contents (Continued)
MCS®-96 FAMILY
Chapters
MCS®-96 APPLICATION NOTES & ARTICLE REPRINT
AP-248 Using the 8096 ... ;.,......................................................................................
AP-275 An FFT Algorithm with the MCS®-96 Products
.
Including Supporting Routines and Examples ........ .................... ...... ............
AB-32 Upgrade Path from 8096-90 to 8096BH to 80C196 ................ ~.....................
AB-33 Memory Expansion for the 8096 ............ ........ ............. ............ ........ .............
AB-34 Integer Square Root Routjne for the 8096 ........... :................................. ;......
AP-406 MCS®-96 Analog Acquisition Primer .... .................... ............ ...... ..................
AP-428 Distributed Motor Control Using the 80C 196KB ...........................................
AR-515 A Single-Chip Image Processor .......... :........................................................
Chapter 7
MCS®-96 Diagnostic Library ............................................................ .................. .......
Chapter 8
6-1
6-103
6-178
6-181
6-193
6-197
6-296
6-325
7-1
80960 ARTICLE REPRINTS
AB-42 80960KX Self-Test ...............................................:......................................
AR-541 Intel's 80960: An Architecture Optimized for Embedded Control ................ ,..
AR-551 Embedded Controllers Push Printer Performance ............................ ,...........
AR-557 A Programmer's View of the 80960 Architecture .................... ........ ...... ........
8-1
8-4
8-18
8-24
GENERAL MICROCONTROLLER
Chapter 9
APPLICATION NOTES
AP-125
AP-155
AP-318
AP-315
Designing Microcontroller Systems for Electrically N9isy Environments .......
Oscillators for Microcontrollers ..... :...............................................................
Intel's 87C75PF Port Expander Reduces System Size & Design Time .........
Latched EPROMs Simplify Microcontroller Designs .....................................
viii
9-1
9-23
9-55
9-80
-
MCS®-48 Application Notes
1
-
_
v
.inter
AP-24
APPLICATION
NOTE
.
© Intel Corporation, 1977
February 1977
98413A
1-1
AP-24
INTRODUCTION
The INTEL ® MCS-48™ family consists of a series
of seven parts, including three processors, which take
advantage of the latest advances in silicon technology to provide the system designer with an effective solution to a wide variety of design problems.
The significant contribution of the MCS-48 family
is that instead of consisting of integrated microcomputer components it consists of integrated
microcomputer systems. A single integrated circuit
contains the processor, RAM, ROM (or PROM), a
timer, and I/O.
This application note suggests a variety of application techniques which are useful with the MCS-48.
Rather than presenting the design of a complete
system it describes the implementation of "subsystems" which are common to many micropro-
cessor based systems. The subsystems described are
analog input and output, the use of tables for
function evaluation, receiving serial code, transmitting serial code, and parity generation. After an
overview of the MCS-48 family these areas are discussed in a more or less independent manner.
THE MCS-48™ FAMILY
The processors in the MCS-48 family all share an
identical architecture. The only significant difference is the type of on board program storage which
is provided. The 8748 (see Figure I) includes 1024
bytes of erasable, programmable, ROM (EPROM),
the 8048 replaces the EPROM with an equivalent
amount of mask programmed ROM, nd the 8035
provides the CPU function with no on board
program storage. All three of these processors
VOO
~PAOGRAMSUPPLY
POWER
SUPPLY
{
~
V
+5V (LOW POWER
STANDBYI
~GND
--
TEST 0
TEST 1
REGISTER
REGISTER
-
,NT
-,.-FLAG
a
TIMER FLAG
;>
3
REGISTER
4
REGISTER
5
REGISTER
6
REGISTER
7
8lEVEL STACK
(VARIABLE LENGTHI
OPTIONAL SECOND
REGISTER BANK
DATA STORE
REStDENT
RAM ARRAY
64 ~ 8
PROM
EXPANDER
CPU
MEMORY
STROBE
SEPARATE
MCS4s™ Internal Structure
1-2
AP-24
INSTRUCTION SET
S
~
:;
E
11
~
~
'5
~
~
g
~
c.
E
~
la:=
Bytes
Mnemonic
Description
ADD A.R
ADD A.@R
ADD A. =data
ADDC A. R
ADDC A.@R
ADDC A. =data
ANL A. R
ANL A.@R
ANL A. =data
DRL A. R
DRL A.@R
ORL A. =data
XRL A. R
XRL A.@R
XRL A, =data
INCA
DEC A
CLR A
CPL A
DAA
SWAP A
RL A
RLC A
RR A
RRCA
Add register to A
Add data memory to A
,,
,,
,
,
2
Add immediate to A
Add register with carry
Add data memory with carry
Add immediate with carry
And register· to A
And data memory to A
And immediate to A
Or register to A
Or data memory to A
Or immediate to A
Exclusive Or register to A
Exclusive or data memory to A
Exclusive or immediate to A
Increment A
Decrement A
Clear A
Complement A
Decimal Adjust A
Swap nibbles of A
Rotate A left
Rotate A left through carry
Rotate A right
Rotate A right through carry
IN A. P
OUTL p. A
ANL P. =data
ORL P, =data
INS A. BUS
OUTL BUS, A
ANL BUS, =data
OR L BUS, =data
MOVD A, P
MOVD P,A
ANlDP,A
ORlD P. A
And A to Expander port
Or A to Expander port
INC R
INC@R
DEC R
Increment register
Increment data memory
Decrement register
JMP add,
JMPP@A
DJNZ R, addr
JC add,
JNC addr
J Z add,
JNZ add,
JTO add'
JNTO addr
JTl add,
JNTl addr
JFO addr
JF' addr
JTF addr
JNI addr
JBb add,
Jump unconditional
Jump indirect
Decrement register and skip
Jump on Carry:::: 1
Jump an Carry:::: 0
Jump on A Zero
Jump on A not Zero
I nput port to A
Output A to port
And immediate to port
2
,,
,,
2
2
,
,
2
,,
,,
,,
,,
,,
2
2
,,
Or immediate to port
Input BUS to A
Output A to BUS
And immediate to BUS
Or immediate to BUS
Input Expander port to A
Output A to Expander port
Cycle
'S
2
.c
~
2
2
2
2
~
>
,
0
:;
~
,,
,
,
C
,
,
2
2
2
2
2
,,
,,
23c
~
0
,tJ
"';::
=
E
i=
,
, g
,
2
2
2
2
2
2
c
.c
~
c
~
III
Jump on TO
Jump on TO
=,
=0
Jump on T1 = 1
Jump on T'
Jump on FO
=0
=,
Jump on Fl = 1
Jump on timer flag
Jump on
iNT = 0
Jump on Accumulator Bit
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Mnemonic
Description
CALL
RET
RETR
Jump to subroutine
Return
CLR C
CPL C
CLR FO
CPL FO
CLR F'
CPL F'
Clear Carry
Bytes
0
tJ
MDV A. R
MOV A.@R
MDV A. =dat~
MOV R, A
MDV@R,A
MOV R. =data
MOV@R, =data
MDV A, PSW
MDV PSW, A
XCH A, R
XCH A,@R
XCHD A,@R
MDVX A,@R
MDVX@R,A
MOVPA,@A
MDVP3A,@A
2
2
2
immediate to A
2
A to register
A to data memory
immediate to register
2
immediate to data memory 2
2
Complement Carry
Clear Flag 0
Complement Flag 0
Clear I'Ia9 ,
Complement Flag'
Move register to A
Move data memory to A
Move
Move
Move
Move
Move
Move PSW to A
Move A to PSW
,,,
, ,
, ,
, ,
,, ,,
,, ,,
,
,,
,
,
,,
2
2
,,,
,,
'2
2
2
2
,,
,,
,
,,
,,,
,,
,,
Enable external interrupt
Disable external interrupt
Select register bank 0
Select register bank 1
Select memory bank 0
Select memory bank 1
Enable Clock output on TO
,
,
,
,
,
,,
,,
,,,
,,
No Operation
,
,
Read Timer/Counter
Load Timer/Counter
Start Timer
Start Counter
Stop Timer/Counter
Enable Timer/Counter 'Interrupt
Disable Timer/Counter Interrupt
EN I
DIS I
SEL RBO
SEL RB'
SEL MBO
SEL MB'
ENTO CLK
NOP
2
2
Mnemonics copyright Intel Corporation 1976
1-3
,,
,
,
MOV A, T
MOV T,A
STRTT
STRT CNT
STDP TCNT
EN TCNTI
DIS TCNTI
Figure 2. 8048/8748/8035 Instruction Set
2
Exchange A and register
Exchange A and data memory
Exchange nibble of A and register 1
Move external data memory to A
Move A to external data memory
Move to A from current page
Move to A from Page 3
2
2
2,
2
2
2
2
2
Cycles
,
,
Return and restore status
III
,,,
2
2
~
e
,,
,, u::~
,,
,,
,,, .
2
2
2
2
2
2
2
,
.
,,
AP-24
operate from a single 5-volt power supply. The
8748 requires an additional 25-volt supply only
while the on board EPROM is.being programmed.
When installed in a system only' the 5-volt supply is
needed. Aside from program storage, these chips
include 64 bytes of data storage (RAM), an eight
bit timer which can also be used to count external
events, 27 programmable I/O pins and the processor
itself. The processor offers a wide range ofinstruction capability including many designed for bit,
nibble, and byte manipulation. The instruction set
is summarized in Figure 2.
Aside from the processors, the MCS48 family
includes 4 devices: one pure I/O device and 3 combination memory and I/O devices. The pure I/O
device is the 8243, a device which is connected to a
special 4 bit bus provided by the MCS48 processors
and which provides 16 I/O pins which can be programmatically controlled.
The combination memory and I/O devices consist
of the 8355, the 8755, and the 8155. The 8355
and the 8755 both provide 2,048 bytes of program
storage and two eight bit data ports. The only
difference between these devices is that the 8355
contains masked program ROM and the 8755 contains EPROM. The 8155 combines 256 bytes of
data storage (RAM), two eight bit data ports, a six
bit control port, and a 14 bit programmable timer.
[ ) Number of Available Timers
( ) Number of Available I/O Lines
1088
lK I8035
8048
8035
8355
8048
8355
2-8355
4·8155
4·8155
4-8155
4-8155
(101) [5)
(116) [5J
[5J
(116) [5J
(131)
832
768 r-'
8035
8048
8035
8355
8048
8355
2-8355
3-8155
,3·8155
3-8155
3·8155
(4)
(80) (4)
(95) (4)
(95) [4J
(110)
r8048
2-8155
[3)
(59)
8035
8048
8035
8355
8355
2·8355
2-8155
2-8155
2-8155
(3)
(74) (3)
(74) [3J
(89)
f8035
8048
8035
8048
8355
8355
2·8355
8155
8155
8155
8155
(38) (2)
(53) [2J
[2J
(53) [2J
(68)
64
8035
8048
8035
8048
8355
8355
2·8355
(1)
(24) [lL
(28) [lJ
(28) [lJ
(43)
lK
2K
3K
4K
PROGRAM MEMORY (ROM)
Figure 3 shows the various system configurations
which can be achieved using the MCS48 family of
parts. It should also be noted that eight of the processors' I/O lines have been configured as a bidirectional bus which can be used to interface to standard Intel peripheral parts such as the 8251 USART
(for serial I/O), the 8255A PPI (provides 24 I/O
lines) and the complete range of memory compo·nents.
. More detailed information concerning the MCS48·
family can be obtained from the "MCS48 Microcomputer User's Manual" which provides a complete description of the MCS48 family and its
.members. A general familiarity with this document
will make the application techniques which follow
easier to understand.
Figure 3. The Expanded MCS48 TM System
specifically designed to interface with microprocessors_
A block diagram oftheMP-IO is shown in Figure 4.
It consists of two eight bit digital to analog conver-
ters, two eight bit latches which are loaded from
the data bus, and address decoding logic to determine when the latches should be loaded. The 0/ A
converters each generate an analog output in the
range of 10 volts with an output impedance of In.
Accuracy is ±0.4% of full scale and the output is
stable 25~sec after the eight bit binary data is
loaded into the appropriate latch. The latches are
loaded by the write pulse (WR) whenever the
proper address is presented to the MP-IO. The
lower two addresses (AO and AI) are used internally by the device. Addresses A2 & A3 are compared with the address determination inputs B2
and B3. If their signals are found to be equal, and
if addresses A4-A 13 are all high, then the device
is selected and one of the latches will be loaded.
Address bit Al selects between output I and output 2. If address bit AO is set then the initialization channel of the DIA is selected. In order to
prepare for operation a data pattern of 80H must
ANALOG I/O
If analog I/O is required for a MCS48™ system
there are many alternatives available from the
makers of analog I/O modules. By searching through
their catalogs it is possible to find almost any combination of features which is technically feasible. Perhaps the best example of such modules are the MP10 and MP-20 hybrid modules recently introduced
by Burr-Brown Research Corporation. The MP-IO
provides two analog outputs and the MP-20 provides 16 analog inputs. Both of these units were
1-4,
AP-24
A,A,A,
.,.,
ADDRESS
LOGIC
AO
With no Rext (Rext = 00) thl! gain is two and the
input is 0-5 or ±5 volts full scale. Adding an I!xternal resistor results in higher gain so that low level
(±50mV) signals from thermocouples and strain
gauges can be accommodated. The output from
the amplifier is applied to the actual A/D converter which provides an eight bit output with
guaranteed monotonicity and an accuracy of ±0.4~
of full scale. Note that this accuracy is specitied
for the entire module, not just for the converter
itself. The control logic monitors address lines
A 15 through A4 to determine when the address of
the unit has been selected. An address that the unit
will respond to is determined by II address control
pins, labeled A4 through A 14. If one of these pins
is tied to a logic 0 then the corresponding address
pin must be high in order for the unit to be selected.
If the pin is tied to a logic I then the corresponding
address pin must be low. If the address of the
module is selected when MEMR pulse occurs, the
lower four addresses (A3-AO) are stored in a latch
which addresses the multiplexer. The coincidence
of the proper address and MEMR also initiates a
conversion and gates the output of the converter
on to the eight bit data bus.
w"R---Q
LOAD 2
DB 70'
REG 1
A'G'~
,
OA
ANALOG OUT
DA
ANALOG OUT
,
Figure 4. Mp·10 Block Diagram
be output to this channel folJowing the reset of the
device.
A block diagram of the MP-20 analog to digital
converter is shown in figure 5. This unit consists
of a 16 input analog multiplexer, an instrumentation amplifier, an eight bit successive approximation analog to digital converter, and control logic.
~he 16 inp~t multiplexer can be used to input
eIther 16 smgle ended or 8 differential inputs.
The output from the mUltiplexer is fed into the
instrumentation amplifier which is configured so
that it can easily be strapped for single ended 0-5
volt inputs, single ended ±5 volt inputs, or differential 0-5 volt signals. Provisions are made for an
external gain control resistor on the amplifier. The
gain control equation is:
The control logic of the MP-20 was designed to
operate directly with an MCS-80™ system. When a
MEMR occurs and a conversion is initiated the MP20 generates a READY signal which is used to
extend the cycle of the 8080A for the duration of
the conversion. READY is brought high after the
conversion is complete which allows the 8080A
to initiate a conversion and read the resulting data
in a single, albeit long, memory or I/O cycle. The
conversion time of the MP-20 depends on the gain
selected for the amplifier. With no external resistor
(R = 00) the gain is two and the conversion time is
35 Jlsec. For R = 5 IOn the gain is:
G = 2 + 50kn
Rext
EXTERNAL
GAIN CONTROL
A,.
A"
A15
G=2+ 50kn
.51kn -
RESISTER
100
A"
A"
A,O
A 9
A 8
A 7
A 6
A 5
and the conversion time becomes 100Jlsec. These
settling times are specified in the MP-20 data sheet
and range from 35 to 175 microseconds. The
READY timing is controlled by an external capacitor. For a gain of 2 no external capacitor is
required but if higher gains are selected a capacitor
is needed to extend .the timing.
A.
A,
A 2
A ,
A 0
A schematic showing both the MP-IO D/A and the
MP-20 A/D connected to the 8748 is shown in
Figure 6. This configuration, which consists of
only four major components, gives an excellent
example of what modern technology can do for
Figure 5. MP·20 Analog Subsystem
1-5
inter
AP-24
IK
-5V
I~ l:>llt;: l:gJ::d~ I:s: li;l I!: I~
~.J'J>~t!-!tlt
~
~r----!I'
Ai2 1!..
Ail ~
1L
..
A;O
'I~
••
~
lKH
·.V
~
cit
?OpF
ffi
XTAl2
cit
••
B
59
5B
57
~
~
~
~
~
TO
56
'55
T,
iNT
----E.
-----'!
"
'0
Mes 48"~
'B
,
,•
P"
p,.
~
P"
ALE
PROG
P"
"
r!L-
"
-a
~
~
StN/DIFF
IN,
MfM'R
IN6
DO
0,
IN,
0;
IN,
03
0,
IN,
~'
.
~l~ ~
06
-i
,
006
,~
01 3
01,
DO,
01,
DO,
DO,
15
14
4
9602
12
9'
~
»
I,,7l
17
•
6
4
~
~
~
tj ~ ~
~
06
OUT 1
05
D.
MP 10
0,
Do
OUT.2
~~J';gl;tt
,
.
MCS-48™ Based Analo9 Processor
1-6
1161
,!,-
,.
-
-
9602
~
ANA LOG
INPU TS
~ ~
rnJ'l",.!"J"l'J"
_
611
5
~
BS1
fJ~
£,., ~1a8~""
2.
~
OS>
RESET
1
~-
DO.
10
8212
DO,
0,
PSeN
Vss
EA
DO,
,
• 0,
VDD
SS
l>
"'"
~
a ~~
DO
~D7
,
):0
W
~l!l
[" ,
01 6
P"
Vee
):>
t.J
~
72
R
DIB
01,
01 5
01,
_
~
~
~
~
INO
0,
~
~
+0-
IN,
~'
~ PIO
5
IN9
INB
1>
P'17
P"
"
Qur LO
MUX ENAB2
MD
P"
P21
----2!.
---22
.
1N1O
lKH
e
'SV
INn
.5V
'6
----'.[
IA IN HI
MUX OUT HI
P"
~ P,o
~
~
--------B
IN 3
'
INT?
P"
P2S
~ P,.
----1!
IN'4
Mp·20
lAIN LO
05
54
~
P"
~
IN.
60
--1
IN , S
MUX
15
Rli
..
BPO
IA OUT
II~
-:f-f~ol1,~
, XTALI
CQMPIN
R'
6B
6 MHz
"
,.
JI
-"'-
As 1.!..As ~
OBIN
OUTPUT SELECT
65
20pF
Ajj
A,
'1·2
".I
CD
"l
--.j
"-I
co
I\J
(t)
-
~
~
~
~
0
-
~}
ANAL DG
QUTP UTS
121
~.
'K
-.
AP-24
be written to following a reset to initialize its
internal logic) all channels involve some form of
data transfer.
As was mentioned previously, the MP-:!o was
designed to use the READY line of the 8080A.
Obviously this presents a problem since the MeS48 does not support a READY line (with its
attendant requirement of entering WAIT state).
The necessity of a READY input can be overcome
by performing a read operation to set the channel
address, waiting the required delay (35 J.lsec for a
gain of two) and then performing a second read to
actually obtain the data. The second read will read
in the data from the channel selected by the first
read irrespective of the channel selected for the
second read. Thus it is possible to use the second
read to set up the channel for the third read. Each
read can read in the current channel and select the
next channel for conversion.
The MP-20 is shown in Figure 6 strapped to input
16 single ended ±5 volts signals. Programs which
were used to test this configuration are shown in
Figure 7. The first of these programs uses the D/ A
converter to generate sawtooth waveforms by
outputting an incrementing value to the D/ A
converters. The second program scans the analog
inputs and stores their digital values in a table
located in RAM.
the system designer. The four components provide:
a.
b.
c.
d.
e.
f.
g.
h.
i.
An eight bit microprocessor
64 bytes of RAM
1024 bytes of UV erasable PROM
A timer/event counter
16 digital I/O pins
2 testable input pins
An interrupt capability
16 eight bit analog inputs
2 eight bit analog outputs
The MCS48 communicates with the D/ A and AID
converters in a memory mapped mode (i.e., it treats
the devices as if they were external RAM). By setting an address in either RO or R I and then executing a MOVX the software can transfer data between
the accumulator' and the analog I/O. When the
MCS48 executes the MOVX instruction it first
sends the eight bit address out on the bus and
strobes it into the 82121atch with the ALE (Address
Latch Enable) signal. After the address is latched,
the MCS48 uses the same bus to transfer data to
or from the accumulator. If data is being sent out
(MOVX oRj, A) the WR strobe is used; if the data
is being moved into the accumulator (MOVX A,
oRj) the RD strobe is used. The one shots on the
WR line are used to delay the write strobe of the
MCS48 to meet the data set up specifications of
the MP-IO.
In order to provide reset capability for the analog
devices without dedicating an I/O pin from the
MCS48, special addresses are used as reset channels.
Executing any MOYXwith anaddressofOXXXXXXX
will reset the A/D module; a similar operation with
an address of X I XXXXXX will reset the D/ A; a
MOVX with an address of OIXXXXXX will reset
both devices. All data transfers are accomplished
with the upper two bits of the address field equal
to 10. A summary of the addressing of the analog
devices is shown in Table I. Notice that except for
an initialization channel for the D/A (which must
LaC
OBJ
2: •••.•. -----.-----------------3 ; TEST PROGRAM FOR AHALOG OUTPUT
"':
THIS PROGRAM OUTPUTS A SAWS;
TOOTH WAVEFORM BY C1UTPUTING
6;
AN IHCREM(NTIHG PATTERN.
. UBI
II'.
Reset AID
Reset D/A
INPUT
Read p,ID Channel
.
";
-------
7; -------.-----------.---.------
INPUT OR OUTPUT
nnnn
.
9 ; ------18 ; EQUATES
Table 1. Analog Interface Addresses
001 1
SOURCE STATEf'lEtH
•,
ilIB3
11181
OXXX XXXX
X1XX XXXX
SEQ
12
13 (HITCH
'''' INITDT
15 MTCH'
,.
IB3H
; D/A INITIALIZATION CHANNEL
EGU
BSH
IBIH
: D/A INITIALIZATION DATA
lOlA DATA CHANNEL
EGU
17; ------------19 ; START OF TEST
19 ; ------------21
ORG
l11H
"
Ilill 2391
11112 BBB3
III" 91
22 START:
23
24
2S
IllS BBBI
B11717
111B 9.
111192415
26 LOOP;
MOV
2.
"
2.
M!lVX
"
(HD
31
nnnn
EGU
/'IOV
MOV
.J!!IlVll
ONe
.....
; IHITIALIZE O/A
A,#IN/TOT
RI,ttIHITCH
@RO,A
I TEST lOOP-OUTPUT SAWTOOTH
RI. ItDATCH
A
@tRI.A
lOOP
; [HO or PROC.RAM
OUTPUT
1 01 1 0001
101 1 0000
101 1 0010
Initialize D/A
Write Channel 1
Write Channel 2
All mnemonics copyrighted © Intel Corporation 1976.
Figure7a. D/A Exercise Program
1-7
inter
LaC
OBJ
AP-24
SEQ
The above calculation, although conceptually
simple, would be time consuming and would
severely limit the possible output frequencies which
could be obtained. As an alternative to calculating
these values in real time, the values could be precalculated off line and stored in a table. Upon each
interrupt the MCS-48 would merely have to retrieve
the appropriate value from the table and output
it to the D/A converter. the MCS-48 provides a
special instruction which can be used to access
data in a table. If'the table is stored in the last 256
bytes of the first kilobyte of MCS-48 memory
then the table lookup can be performed by loading
the independent variable (time in this case) into
the accumulator and executing the instruction .
SOURe[ STATEJI£HT
•,
2
3
-------------------------------. ______ _
T[ST PROGRAM fOR ANAlOG IHPUT
TH"IS PROCiRAf'I SCAMS THE INPUT CHAtttElS
AHD STORtS THE R[ADINGS IN A TAkE
STARTltIG AT IU'f.
---------------------------------------
•
S
•
•
7
9 ; ------I' ; EQUATES
•• 2.
....
,,"5
.lIr
""
;
.------
138JF"f
14 P1AXCH
IS AIHCH
IS TlCIC
EOU
EOU
EOU
EOU
IBIH
i START OF 9JF'f[R
; HO or ANAl.OG I HPUTS
; BAst ADDRESS OF ANALOG INPUTS
S
; EXECUTION TlfIE
2 ••
IS
or
DJN2
"
18 ; -------------
"
..
1,lIlI92f
"'2 IB'f
"'48BBF"
"16 8.
..
..
19 ; START Of TEST
2' ; ------------23 START:
2S
26
27
.
.
20
"17 scla
"19 fet9
"'8 ca
",e 8.
'"0 AI
"IEG
".F SCI..
11il EC1'
1"3 [Bl8
IllS 2"'''
ORG
22
3t
31
32 LOOP:
33
3S
36
37
30
39
......
.....
.,
'"'"
"""
"'"
l11H
J 5[nP TO SCAN ANALOG UtPUTS
Ii 1 • "BlFr .I'IAXCH
R3,tlMAXCH
R,.#(AIHCH.I'!AX(;H)
; SEl.ECT CHAH/'IEL 'S
'"""
A,ORI
"'"
li!4, "",/TICK
DJItZ
DEC
; WAIT
••
'"""
A.OR'
"'"
.,
DEC
»". MICROSECOHDS
MOVP3 A,@A
Ii",$
;
~
SCAN AHALDGS
This instruction uses the initial contents of the
accumulator to index into page 3 of program
storage. The location pointed to is read and the
contents placed in the accumuhitor. If (as is often
the case) a table of fewer than 256 entries is
required, then the table can be located in any page
of program mel110ry and the instruction:
; GET OATA
; IOJE INTO 9JF'FER
ORI,A
j
D£CRtr:£HT BUF'fER PO I NT
; PAD 2. I'IJCROSEC
"'"
R4,#2'/TlCK
OJH2
R"',$
OJHZ
R3,LOOP
JI'P
START
! LOOP UNTIL DCIHE
! REPEAT TEST F'OREVER
; END
or
MOVPA,@A
PRQGRAI'I
EHI)
can be used to retrieve data from the table. This
instruction operates in the same manner as does
the previous instruction' except that the current
page of program storage is ass4med to contain
the table.
Figure 7b. AID Exercise Program
If it is possible to devote slightly more of the
microprocessor's time to tile table look up process,
then a much smaller table can often be utilized by
taking advantage of interpolation to determine
values of the function between values which are
actual entries in the table. As all example of this
TABLE lOOKUP TECHNIQUES
111 the previous section the interface between analog
I/O devices and the MCS-48™ was discussed. In
many applications involving analog I/O one quickly
finds that nature is inherently nonlinear, and the
mathematics involved in 'linearizing it' can tax the
cOJ11putational power of the microprocessor, particularly if it has other tasks to perform. Problems
of this nature are good candidates for the use of
tables.
FLOWMETER
As an example of how tables can be used as part of
an analog output scheme, consider a system which
requires an MCS-48 to output a variable frequency
sinusoidal waveform. One method of performing
this function would be to use the timer to generate
an interrupt at a fixed rate of 256 times the desired
output frequency. At each interrupt the appropriate
vahieof the sine function could be calculated from
the Maclaurin series:
----1
FLOWMETER
AD
----l
FLOWMETER
.
' x3
x5
x7
Sm x = x - 3! + 5! - 7T
MCS48
LJ
(_1)k x 2k +1
(2K + I)!
Where K is chosen to be large enough to provide
th~ required accuracy.
All mnemonics copyrighted
LJ
@ Intel Corporation 197ft
Figure 8. Flow Monitoring System
1-8
COFltTROL
PANEL
inter
AP-24
process consider the hypothetical system shown in
Figure 8. The purpose of this system is to measure
the flow through the three pipes, add them, and
display the total flow on the control panel. The
system consists of three flow meters which generate
a differential voltage which is some function of
flow, an A/D system with at least three differential
inputs, an MCS48, and a control panel. The
schematic sho\Vn in Figure 6 could easily become
part of this system, with the spare digital I/O of
the MCS48 used as an interface to the control
panel. The simplicity of this system is clouded by
the flow transducers, which are assumed to be not
only nonlinear but also to require individual calibration (this is not an unreasonable assumption for
a flow transducer). By usinga table look up process
and an 8748 the flow transducers can be calibrated
and the results of the calibration tests stored
directly in tables in the 8748. (The 8748 has a
PROM in place of the ROM of the 8048 and thus
makes such 'one off' programmin, oractical.)
The results which might be obtained from calibrating one of the flow meters is shown in Figure 9.
The results are plotted as gals/hour versus the
measured voltage generated by the transducer. The
voltage is shown in hexadecimal form so that it
corresponds directly to the digital output of the
analog to digital converter. The flow required to
generate seventeen evenly spaced voltages (OH-l bOH
in steps of 10H) has been measured and plotted.
This information is shown in tabular form in
Figure 10. It is necessary to generate a program
which will convert any measured input from OOH
to FFH into the flow in units which can be interpreted by a human operator. This can easily be
done by simple interpolation.
The eight bits of independent variable (voltage) can
be looked on as two four bit fields. The most significant four bits (7-4) will be used to retrieve one of
the table values. The lower four bits (3-0) will be
used to interpolate between this value and the
value retrieved from the next higher location in lhe
table. If the upper four bits are given the symbol I
and the lower four bits the symbol N, then lhe
interpolation can be expressed as:
F(x)
= F(I)
+
ii,
[F(I+I) - F(I)]
Where x is the measured voltage and F(x) is the
corresponding flow.
If, as an example, the transducer voltage was
measured as 48H then the flow (ref. Figure 10)
would be:
F
= 30
+
8
16
(34-30)
= 32
A subroutine which implements this caiculalJIIII is
shown in Figure II. Before it is called the indl·I"·1I
dent variable (V) is placed in the accumulator and
register R I is set to point at the first value in the
table. Aside from simple additions and subtractions
the only arithmetic required is to multiply two
values and then divide them by 16. The multiplication is handled via a subroutine which is also
shown in Figure II. The division by 16 can be performed by a four place right shift followed hy a
rounding operation. The routine shown will handle
a monotonic increasing function of a single independent variable. Fairly simple modifications are
required for nonmonotonic functions. Functions
of two variables can be handled by interpolating on
a plane rather than along a straight line. Although
this is more time consuming, requiring an interpolation for each of the independent variables and
a third to in terpola te the final answer, it still
provides a simple means of quickly calculating the
required function. The use of tables can offer a
powerful technique for function evaluation to the
designer.
60,------------------
'0
RECEIVING SERIAL CODE-BASIC
APPROACHES
Many microprocessor based systems require some
form of serial communication. Serial communication is extensively used because it allows two or
more pieces of equipment to exchange information
with a minimal number of interconnecting wires.
The minimization of interconnecting wires results
in simpler, cheaper, interconnects because fewer
(or smaller) cables and connectors are required.
Since the required number of drivers and receivers
required is reduced, it can become economically
feasible to provide much higher noise immunity
10
Figure 9. Flow Calibration Curve
TRANSDUCE R , . . - , - , - , - - , - , - , - , - , - - , . - - , . - - , . - - - - , - - - - - , - - , - - , - - - . - - .
VOLTAGE IHfX! 00 10
MEASURED FLOW
HHHH-I-I-I-I-I-+-+-+-+-+-+-+-1
IGA l HOURI '----''----''----'--'--'--'--'---'---'---'-----'-----'----'-----'-----'-----'-----'
Figure 10. Tabulated Flow Data
1-9
inter
Loe
OBJ
AP-24
. .0
SOURCE. STATEMENT
I
LaC
•••••••••.••••••••••••••••••••••••••••••••••
.•, ...........................................
OBJ
I"C 83
"10 BElie
,,,r
BAl.
9 1 EQUATES
'11'
...2
.113
'11'"
I I : ':'-----11
12 RXI
EOU
13 AXI
EOU
,,, AEX
EQU
15 COUNT
EOU
16 TEI'F
EOU
17
"21 97
R'
R'
R,
R3
R'
j POINTER I
I POINTER!
I E:xTENSIOH
or
A REGISTER
.,••
"22 1228
.,204 2A
112567
; COUNTER
.,26 2A
; IT"" STORAGE
112767
"28 EB22
112A 83
21; -------------
11,. IBI'"
1,.2 Bill
.,1431
IllS "17
111669
•,,7 A9
1118 E3
111929
IliA 17
111B E3
,tiC 37
111069
111E37
"282A
ORO
'3
2'1 APPROX: fI10V
'5
26
i'1OII
28
XCHD
",",P
29
.,
31
31
3•
33
3<
35
36
3'
.,
.....,
..,..
3B
II'H
112C 61
; POINT RXI AT TEI'F
RXI.#TEfIF
"2067
; TEI'P-N AND IfH
; A"P AHD IFH
@RXI,#I
A,ORXI
111B 69
••••
51
A,RXI
RXI,A
AIlD
CPl
A,OA
A,AXl
A
A,@A
A
A,AXl
A
CALL
'''IT
i'1OII
XCHD
SWAP
XCH
JB3
XCH
Rxt,#AEX
A.@iRXI
A
A,AEX
ADJUST
A,AEX
A,AEX
A
; A-A. TABLE(PJ
A,RXl
: AETURN
IHe
54
ADD
"'"
66 LOOPA:
CLA
68 LOOPB:
69
71
71
72
JB.
XCH
RRC
XCH
RRC
63 I>IUl.T:
f'IDV
",.
7S
DJN2
RET
77 ssli>1:
78
79
81
81
XCH
ADD
ARC
XCH
RRC
B3
DJNZ
RET
8.
.
8'
.,
; SET UP COUNT AND AEX
COUNT, #8
AEX.#I
; CLEAR CARRY
"1>1
; If MUlTIPLIER (I) () 1 THEN SflIFT PRODUCT
A,AEX
A
A,AEX
A
; LOOP UNTIL DONE
COUNT,LOOPB
; ELSE ADD f'>lJLTIPLIER AND SHIFT PRODUCT
A,AEX
A,@IU.
A
A,ArX
A
; LOOP' UNTIL DONE
COUNT,LOOPA
89 ; --------------------'
1381
; A-H-A/16
51 ADJUST: XCH
.5
87 I --------------------sa ; TABLE TO TEST PROGAAM
: A-TABLE (P.U-TABLECPJ
CPl
..,6'
8!i
; RX ,·TABlEIULTIPLY
61 ; --------
5
I ...
56
57
58
APPR[]X
AT ENTRY RI POIHTSAT TAkE
A HAS IHOCPEHOENT IIARIAB..E
8 I -------
SEO
1381 II
138t IA
1382 16
1383 lA
138'" lE
138522
1386 26
138728
1388 29
1399 2A
138A 2B
13aB 20
I38C 31
I3&D 31
I38E 35
l3Bf 38
1391 3F
91
ORG
93 TABl-E:
DB
94
DB
••
.,.
9S
DB
96
DB
DB
DB
DB
99
"'
"'
"'
113
".
1IS
'86
'87
"8
11.
'"
"'
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
.
38IH
; THIS TABlE: IS FROM FJG HI
11
••
26
31
.
34
38
.,
.,••
..
4S
.8
53
56
.3
EMD
Figure 11. Table Lookup With Interpolation
eighth data bit usually consists of even parity on
the remaining seven data bits; for the purposes of
this discussion the eighth bit will be considered
only as data. A m'inor variation of this fonnat
deletes one of the STOP bits. An algorithm which
might be used to sample serial data under software
control using a microprocessor is shown in Figure
13. Th~ basic intent of this algorithm is to minimize the effects of distortion and transmission rate
variations on the reliability of the communication
by sampling each data bit as close to its center as
possible. Upon entry to this routine the software
first samples the incoming data in a tight loop until
it is sensed as a MARK (logical one). As soon as a
MARK is detected, a second loop is entered during
which the software waits until the received data
goes to a SPACE (logical zero). The purpose of this
construction is to detect as accurately as possible
the leading edge of the START bit. This instant of
time will be used as a reference point for sampling
all of the following bits in the character. After
sensing the leading edge of the START bit a wait
of one half the expected bit time is implemented.
The period of the incoming signal is called P for
convenience. At the end of this wait the serial line
is tested-if it is MARK then the START bit was
with more sophisticated (and expensive) line
tenninators. The final, and usually most persuasive, argument in favor of serial communication
is that it may be the only method available to
accomplish the job. The obvious example of
this is telecommunications where it is necessary
to encode parallel infonnation into serial fonnat
in order to communicate via the telephone network. The intent of this section is to show how
the facilities of the MCS-48™ can be brought to
bear on the problem of serial communication.
Figure 12. Serial ASCII Code
Probably the most common form of serial communication is that used by the obiquitous Teletypeserial ASCII. This fonnat, shown in Figure 12, consists of a START bit (0 or SPACE) followed by
eight data bits which are in tum followed by two
STOP bits (I or MARK). In actual practice the
All mnemonics copyrighted © Intel Corporation 1976,
1-10
inter
AP-24
the processor will spend only a I OO~secs or so processing data and the rest of the 100 millisecs waiting to do the processing at the right time. This lack
of efficiency (approximately 0.1 %) in the utilization
of processing power is why devices such as the
8251 USART find broad application in microprocessor systems.
LOC
OSJ
5ClIRCE STATEMENT
5EO
";
, , ..............................
,,2 ,,,
SIf'FLE SERIAL II'IPUT
.THIS CODE ASSll'IES RltO IS
CONNECTED TO PIN TI
5 ,
6 ; ••••••••••••••••••••••••••••••
7
8; _______
'3 ; [QUATES
11:
"liZ
IU8
8182
I,M
lUI
"
-------
12 COUNT
13 BITHO
14 DlVH!
,.
15 DLYLD
"
,ou
,ou
,ou
'ou
OR.
"
8
IA4N
: LOOP, UNTIL IUD-MARl(
19 SEAIN: JNTI
; HOW LOOP UHTlL RXO-SPACE
20
.,123612
JTO
CALL
HBIT
a116 3611
"
"
25
26
JTO
SER(H
1118 BIllS
27
"~
"11'" 341C
'IIA 341C
.11C341C
22
23
28
29 LOOP:
""32
,.
,
.
: WAIT 112 BIT TIME
CALL
33
"IEEAIS
'11897
• ,11 3614
1,,3A7
811483
3S
37
38 EXIT:
DJHZ
CLR
JT.
CeL
R'T
.11597
"'62619
41 LOAD:
"18 A7
"1967
"
IliA 24'A
43 LLLA:
"0. The
USART requires a reset of approximately 6 CLK
periods so DELAY is chosen to be I which ensures
adequate reset timing. Note that for delays this
short, NOP instructions could also be used to time
the pulse.
19968
MH,
The data clocks required by the USART are provided by the modem if the USART is operated in
the synchronous mode. In the more common
asynchronous mode, however, these clocks must
be provided by circuitry associated with the 8251.
The 5.9904 MHz crystal was chosen because the
resulting 1.9968 MHz clock to the USART can be
evenly divided to provide transmit and receive
clocks to the USART. Assuming the USART is in
the x 16 mode (i.e. it requires data clocks 16 times
the baud rate) the 1.9968 MHz signal can be divided
by 13 to generate the proper clock rate for 9600
baud operation. This 9600 baud .clock can be
further divided to give 4800, 2400, 1200, 600, and
300 baud signals. The 1200 baud signal can be
divided by II to give a 109.1 baud signal which is
within I % of the 110 baud required by Teletypes.
'Install Jumper for 110 Baud OperatiOn (-111
Figure 15. MCS-48™ to 8251 Interface
necting the CLK signal of the USART to the TO
pin of the MCS-48. The TO pin of the MCS-48
can either be used as a directly testable input pin
or it can become, under program control, an out. put pin which oscillates at one third of the crystal
frequency. (Note that once this pin is designated
by the software to be ali output it will remain so
until the system is reset.) In Figure IS the crystal
frequency is 5.9904 MHz so the clock provided to
the 8251 is 1.9968 MHz, which conforms to its
specifications.
The initialization signal to the USART (RESET) is
provided ·programmatically by manipulation of bit
5 of port 2. It was-necessary to place the reset of
the 8251 under program control for two reasons.
The first reason is that the MCS-48 does not supply
a reset signal to other devices. The reason for this is
that it was felt to be more useful to provide another
pin of I/O function instead ofa RESET OUT signal
The MCS-48 communicates with the 8251 in a
memory mapped mode (i.e. as if the 8251 were
external RAM). The instructions available to do
this are MOVX aRj, A which stores the contents of
the accumulator at the external RAM location
addressed by Rj U=O or I), and its complement,
the MOVx' A, @ Rj instruction which moves data
from the external RAM into the accumulator.
Since the MCS-48 multiplexes addresses and data
on the same eight bit bus an external latch would
be required in order to address the USART with
1-12
AP-24
Lac
DIlJ
SEQ
to add the circuitry necessary to use RO or R I to
address the peripheral devices. The circuitry which
has to be added to Figure 15 in order to make use
of RO or RI to address the USART is shown in
Figure 17. Note that only the changes to Figure 15
are shown. The additional component required is
the 8212 eight bit latch. This latch is loaded, whenever a valid address is on the bus by the Address
Latch Enable (ALE) signal provided by the MCS48. During an ex ternal read or wri te cycle this
address is used to address the 8251 in a linear
select mode. In the circuit shown, the 8251 will be
.selected by any address with bit I a logical zero
(XXXXXXOX) and the selection of control or data
transfer (C/O) will be based on bit zero of the
address obtained from RO or R I. Figure 18 shows
the program of Figure 16 modified to utilize the
addressing inherent in the MOVX instructions.
SOURCE STATEMEMT
S[R[ALT[ST
TH[S
cooe:
ItHIALIZES TI1E USART
AND TRANSMITS AN IHCREMfNTlNG
PATTERN. HARr:wAR£ SH~ IF riG 15.
7; ---- __ _
8; EQUATES
9; -------
liZ'
ue,
UDF
UCE
1117F
11"
"Bf
"
11 MCLR
12
13
14
15
16
DLV
ueON
[au
[au
lilH
81H
[QU
[au
BeEH
; USAIH f'1JD(
eMD
STAT
[IlU
£QU
211,
; USART CMt)
7FH
(au
[au
; USAInSTATU5
; TEST VALUE
'SFH
; CHAt1VES eND TO DATA CHANNEL
ORO
lUSH
22
23 TEST;
Etne
eLK
24
ORL
2S
"""
P2,:tMCLR
R2,:tDLY
R2,LOOP
17 VAL
18 MASK
; TURHOHCLDCK
21
8187 9ADF
8119237F
81883A
S18el3eE
lilliE 98
IIUF2321
8111 9&
; USART RESET DELAY
; USART CONTROL ADDRESS
/'{JOE:
8188
8118 75
8!118AZI
ill13 BAil
illllSEAIS
; USART RESET ADDRESS
26 LOOP:
27
,.
; AHDR[SET USAIH
DJHZ
ANL
38
"
,.
P2,#(HOTMCLlU
; SELECTUSARTCOHTROL
A,#UCON
29
DUlL
32
33
MOVX
35
MOVX
3.
.
P2,A
SEND 1'l]D£ AND CCI'T'1AND
A,#MOD£
@RS,A; (CONTENTS OF Re UN[I'F'ORTANT)
A,#CMD
@RiI,A
; [)(] FOREVER
SELECT UsART STATUS
IF TXRDY-' THEN
3S
1112237f
1114 3A
042
043
0404 TLP;
045
046
lIlA 9AB(
....
""G
9'
8110 19
51
52
ill1s 88
111667
11117 [612
1119 F9
8"[2412
OUTPUT VALUE;
INCREMENT VALUE;
END;
P2,A
A,@RB
;
(CONTENTS OF RS UNII'F'ORTANT)
INC
53
JI'P
END
os,
'0
A
AHL
os,
13
22
'8
JHe
M!JVX
'I~
ALE ~-------"'l
A,#STAT
OUTl
"
55
'5V
END;
.,
"
WR~----------------------~
WR
R-a
00,
A,VAL
P2,#MASK
@RS,A
VAL
TLP
; END OF PROVRAM
16
U748
MO
00 8
DO,
I-
0'6
00 6
015
005
III-
00 4
I-
00 3
I-
~ DO,
------2
8212
0',
01 8
0'3
~3 00,
00,
DO, ~
DO, ~
8251
cs
c/o
D,~-+-t~+-~r+----------~ D.,
06~-+-r1-~~~-----------; 08 6
D5r---~1-~~~-----------; 08 5
D4~----~~~~-----------; 08 4
D3~------~~r+-----------; 08 3
D,r---------+-r+----------~ 08,
0, ~--------~~----------_1
Figure 16. 8251 Test Program
D.,
DO~----------~----------_1 0. 0
L..-_ _- '
RO or R I. In order to Immmize the circuitry in
Figure 15 an approach utilizing some of the I/O
pins of the MCS-48 to address the 8251 was chosen
instead. By connecting the chip select (CS) input
of the 8251 to bit 7 of port 2 (P27) and similarly
connecting the C/O address line of the 8251 to bit
6 of port 2 (P26) it is possible to address the 8251
without using RO or RI. The instruction sequence
to access the 8251 is to first reset P27 and set P26
to the appropriate state, use a MOVX instruction to
perform the appropriate operation, and then
finally set P27 to deselect the 8251. As a concrete
example of this addressing, Figure 16 shows the
code necessary to initialize the 8251 and output an
incrementing test pattern on a status driven basis.
If more than one 8251 were to be added to the
MCS-48, or if other types of peripheral circuitry
would be required (e.g. an 8253 timer to generate
the data clocks) it would probably become desirable
AU mnemonics copYrIghted © Intel Corporation 1976.
'-_ _- - '
Figure 17. Modified MCS48 to 8251 Interface
RECEIVING SERIAL CODE-A MORE
SOPHISTICATED ALGORITHM
Although the USART does an admirable job of
performing the serial I/O function for the MCS48™, there are some situations where it can not be
used. These situations may be caused by economic
factors, such as an extremely cost sensitive design,
or because the code which must be utilized cannot
be accommodated by the USART. An example of
of such a code will be discussed later. Recall that
the principal objection to the approach to serial
input shown in Figure 13 was that it consumes
much of the processor's power by merely spinning
in loops in order to wait preset time delays.
1-13
inter
LaC
AP-24
SEQ
OBJ
interrupt occurred. If the serial line has returned to
the MARK state, a status flag is set to indicate an
error and a return is made. On subsequent interrupt
detection, the data is sampled, the timer is reinitiated, and control is returned to the program which
was running when the interrupt occurred. When
the last (Le. STOP) bit is detected a completion
flag is set and a return is made to the program
running when the timer overflow occurred. By
periodically, checking the error and completion
flags the running program can determine when the
interrupt driven receive program has a character
assembled for it.
SOURCE STATEMENT
•........... __ ._----_._------------S[RIALT(ST
THIS CODE INTIALIZES THE USAAT
AND TRANSMITS AN INCREMENTiNG
"
PATTERN. HARDoIARE SHCIoIH IF FIG 17.
5
--------------------.--.----------6
7: ------8: EQUATES
9; -.-----
"
fl21
[DU
211'1
1 USART RESET ADDRESS
12 Dl..V
[QU
1183
liCE
1121
.111
13 UCON
14 I1JDE
[au
.,H
.3H
1 U5ART RESET DELAY
1 USAAT CONTROL ADDRESS
[DU
ICEH
; USART I'IDDE
IS Cf'ID
16 STAT
[QU
[OU
21H
13M
1111
1111
17 VAL
[DU
18 DATA
[OU
III
81
; USAATCfIID
; USART STATUS
I TEST VALUE
I USART DATA ADDRESS
21
ORO
1nM
EHTI
DRt.
eLK
"
''',
P'CLR
,.
1111
21
22,
23 TEST:
2<1
25
111. 7S
1111 8A21l
1113 BAI'
1115 EAtS
I TURN ON CLOCK
; AND RESET USART
1'IlII
26 LOOP
27
DJNZ
"17 SADF'
2.
11.92313
29
3'
1'IlII
31
32
1'IlII
11109'
1,.[ 2321
33
1'IlII
34
35
36
37
38
39
MOVX
.,ta2leE
"11 9,
AtiL
MOYX
"
""
1111 2313
111381
.,1467
'115 ES1'
'117 F'9
'118 BBl'
lilA 9.
",S 19
43 TLP:
44
45
46
MOV
MCJI.IX
RRC
JNC
.,
48
51
MQV
MOV
f'lQVx
INC
51
"'"
49
I"C 24"
52
53
P2,"MCLR
R2,#DLY
R2,LOOP
P2,It(NOTI'1CLR)
; SELECT USART CONTROL
A,ItUCON
; SEND !"ODE AND CCJ1'1AHD
A,#I'IJOE
ORI,A I (CONTENTS Of RI UNIMPORTANT)
A,ltCf'ID
@RI,A
; DO FORE\lER
SELECT USART STATUS
If TXRDY-1 mEN
!Xl;
OUTPUT VALUE;
INCR(II£HT VALUE;
END:
;
END:
A,#STAT
A,@RI : (COHTENTS OF RI UNIMPORTANT>
A
TIMER
OVERFLOW
TLP
A,VAL
RI,#DATA
ORI,A
VAL
TLP
; END Of PROGRAM
END
Figure 18. Modified 8251 Test Program
The timer resident on the MCS48 provides a solution to this problem. Instead of spinning in a loop
the program can set the timer for a given interval,
start it, and proceed to other tasks. When the timer,
overflows, an interrupt will be generated to notify
the software that the present time period has
elapsed. An e~tension of the algorithm of Figure
13 which uses the timer in this fashion in shown in
Figure 19. This algorithm is identical to the preceding one ,up until the detection of the leading edge
of the start bit. At this point the timer is set to one
half of the bit time (P) and a return is made to the
calling program which can start additional processing. At the completion of this time interval a
timer overflow interrupt is generated. When the
first interrupt is detected, the serial line is checked
to ensure that it is in a spacing condition (valid
START bit). If it is, the timer is set to P (to sample
the middle of the first data bit) and a return is
made to the program which was running when the,
All
mnemon~cs
copyrighted @ Intel Corporation 1976.
Figure 19. Improved Serial Input Routine
Using the timer to implement time delays as shown
in Figure 19 results in considerable savings in
processing time; two p,roblems remain, however,
which must be solved before an adequate software
solution to the problem ofreceiving serial code can
be found. The first problem is that even though the
delays between bit samples are implemented via
the timer rather than program loops the loop construction is still used to detect the leading edge of
1-14
AP-24
the START bit. Although this results in the waste
of processing power, the second problem is even
more serious. For longer messages the required
accuracy of the clocks becomes more and more
stringent. Using the sampling technique discussed
a cumulative error of one half a bit time in the
time at which a bit sample is taken will result in
erroneous reception. The maximum timing error
which can be tolerated and yet still allow proper
detection of an II bit ASCII character is then:
Both efficient detection of the start bit and increased timing accuracy can be obtained if the MCS48
can detect edges on the incoming received data
(RxD). A hardware construct which allows this
is shown in Figure 20.
The received data (RxD) is Exclusive NORed with
bit seven of port two and fed into the TEST (T I)
pin of the MCS48. By manipulating P27 the program can now cause TI to be either RxD or RxD.
(If P27 = I then TI = RxD; if P27 = 0 then TI =
RxD.) Note that not only can TI be tested directly
by the software but that it is the input which is
used when the MCS48 timer is in the event counter
mode. The significance of this will be discussed
later. The relationship between TI, P27, and RxD
is given by the Boolean expression:
O.SP
O.s*BIT TIME
Emax = CHARACTER TIME - TiP = 4.5%
where P is the period of single bit. The corresponding calculation for a 32 bit character yields:
Emax =
~i~
= 1.6%
TI
Since this calculation does not allow for distortion
on the signals, it is obvious that either extremely
stable clocks will be required or a more tolerant
algorithm must be devised. This problem is particularly serious at relatively high baud rates where
the resolution of the counter (80J.lsecs with a 6 MHz
crystal) becomes a significant percentage of the
period of the received signal. At the 110 baud rate
of the Teletype the 80J.lsec resolution of the clock
allows a maximum accuracy of 0.33%; at 2400
baud this figure is reduced to 3.8%.
PROG
T1
Figure 2 I flowcharts a means of utilizing this hardware construct to avoid the necessity of wasting
time in program loops to detect the leading edge of
the start bit. The receive operation is initialized
when the program desiring to receive serial data
calls the INIT subroutine (Figure 2Ia). Since INIT
is going to manipulate the timer the first action it
performs is to disable the timer overflow interrupt.
Its next step is to set P27 to a logical 1. Setting
P27 in this manner causes the TEST 1 input to the
MCS48 to follow RxD. By setting up the receive
circuitry in this manner a high to low transition
will occur on TEST 1 when the RxD goes from
the MARKING to SPACING state (Le. the START
WR
ALE
P17
P27
P26
P25
P24
P23
P21
P20
P16
P15
P14
P13
P12
Pll
PlO
TO
°7
06
Vcc
V OO
°5
04
03
ss
PSEN
°2
°1
DO
Vss
EA
-=
• RxD + P27 • RxD
AD
tNT
RxO
+5V
= P27
}~'"
},"
.::r::
Figure 20. Detecting RxD Edges
Figure 21a. Interrupt Driven Serial Receive Flowchart
1-15
intJ
AP-24
bit, occurs). By setting the timer to OFFH and
enabling it in the event count mode, the, .INIT
routine sets up the, MCS48 to generate a timer
overflow interrupt on the next MARK to SPACE
transition of RxD (the TEST I input doubles as
the event counter input). Before returning to the
calling program the INIT routine sets a flag (RDF)
which will be cleared by the receive program when
the requested receive operation is complete. INIT
also sets a value into a register called BCOUNT.
The receive program interprets BCOUNl as follows:
Number of bits remaining
to receive
If set indicates that the
ST A RT bit has not yet been
detected
NO
__2 -__________~~____~~
If set indicates that the
START bit has not yet bee'n '
verified
Figure 21 b. Interrupt Driven Serial Receive Flowchart
In order to request the reception of the II bit
ASCII code INIT would set BCOUNT to 1100101 lB.
The start bit has been neither verified nor detected
and II bits (lOIIB) are required.
After INIT is called the reception of the individual
serial data bits will proceed on an interrupt driven
basis until a complete character has been assemble~.
When this occurs the interrupt driven program will
set the RDF (Receive Done Flag) to a zero to indicate that it has completed the requested operation
and then terminate itself. The procedure which is
used to accomplish this is shown in Figures 21 b
and 21c.
Since all operations of this program are the result
of the occurence of a timer overflow interrupt, it
is necessary to briefly review the interrupt structure
of the MCS48, There are two sources of interrupt;
an external interrupt which is the result of a logical
zero signal applied to the INT pin of the MCS48,
and an internal interrupt which is caused by a
timer overflow condition. The timer overflow
occurs whenever the timer is incremented from
OFF H to zero whether it be in the timer or event
count mode, When one of these events occurs the
hardware in the MCS48 forces the execution of a
CALL. This CALL has a preset address of location
3 if it is due to the external interrupt and location
7 if it is due to a timer overflow. If both of these
Figure 21c. Interrupt Driven Serial Receive Flowchart
1-16
AP-24
RETR is executed. Note that since the state of
the flip flop which selects RB I is saved as part of
the PSW, the execution of RETR automatically
selects the register bank which was active when
the interrupt occurred.
events occur simultaneously the external interrupt
will take' precedence. The CALL automatically
saves the contents of the program counter for the
running program and its PSW (program status
word) on a stack the hardware maintains in RAM
locations 8-23. Although the hardware saves the
program counter and PSW, it remains the responsibility of any interrupt driven software to make
absolutely certain that it does not modify any
memory locations or registers which are being
used by the main program. The most convenient
way of ensuring this in the MCS48 is to dedicate
the second bank of registers (RB 1) to the interrupt
driven program. One of these registers has to be
used to save the accumulator (which is not part of
the register bank) but seven registers remain;
including two which can be used as pointers to the
rest of the RAM (RO and R I). Note that if this
approach is taken then these registers have to be
allocated between the program which services the
external interrupt and the one which services the
timer overflow. This problem is somewhat alleviated
by a hardware lockout which prevents the timer
overflow interrupt from interrupting the external
interrupt service routine and vice versa. This is
implemented by locking out new interrupts between
the time an interrupt is recognized and the time a
RETR instruction is executed. The RETR instruction is like a normal RET (return from subroutine)
except that the PSW as well as the program counter
is restored. The RETR instruction can be very
much thought of as a return from interrupt instruction in the MCS48.
If BCOUNT [7] is still set when it is tested, control is passed to START (Figure 21c) where bit 6
is tested to determine if the START has been
detected yet. If BCOUNT [6] is set it indicates
that this is the first occurrence of a timer overflow
since the receive process was initialized by the
INIT subroutine. If this is so, the program assumes
that the START bit has just started and therefore
it sets the timer to one-half of a bit time (1/2 P),
starts the timer in the timer mode, and clears
BCOUNT [6] to indicate that the START bit has
been detected. The next overflow will again result
in the execution of the program in Figure 21 band
again BCOUNT [7] will be found to be set. This
time, however, BCOUNT [6] will be reset and the
program will know that it should test the START
bit to ensure that it is still a SPACE. This test is
performed and if successful the timer is set for a
bit period P and BCOUNT [7] is reset so that on
the next occurrence of a timer overflow the program will know that it should start assembling
serial bits into a character. If the test is unsuccessful, the subroutine INIT is used to reinitialize the
receive program. In either case control is passed to
EXIT where a return from interrupt mode occurs.
This receive program, listings of which appear in
Figure 22, allows the reception of serial characters
transparently to the main running software. After
INIT is called the main program has only to check
RDF periodically to find out if there is data in the
buffer for it. It would be fairly easy to 'double
buffer' this operation by providing a buffer which
the receive program uses to deserialize the incoming code and a second buffer to store the assembled
character. If the program would reinitialize itself
upon completion, the reception of a string of
characters could proceed in much the same way as
it would if a status driven USART were being used.
The receive program under discussion uses register
bank I in the manner described. Whenever a timer
overflow occurs (e.g. on the next MARK to SPACE
transition of RxD after INIT is called), control is
passed (by the hardware generated CALL) to the
point labled TIMER OFLO in Figure 21 b. This
program segment immediately selects register bank
I (RB I) and then saves the accumulator (A) in a
location called ATEMP which is actually R7 of
RB I. The program then tests bit seven of BCOUNT
(R6 of RB 1) to find out if a START bit has been
verified (Le. the edge of the START bit has first
been detected and then verified to still be a SPACE
one-half a bit time later. If BCOUNT [7] is a zero
the START has been verified and the program proceeds to set the timer to P (the period of the serial
bit), get the current serial data into the carry bit,
and then shift the carry bit into a buffer. After
saving the data the program decrements BCOUNT
and tests it for zero. If BCOUNT is zero the receive
operation is complete so the program sets RDF to
a zero and disables timer overflow interrupts.
Whether or not BCOUNT is zero, control is passed
to EXIT where A is loaded with ATEMP and a
Although this program solves the first problem of
software controlled reception (lack of efficiency)
the second problem-sensitivity to frequency
variations-remains. An example of a code which
would be susceptible to this problem is the 3 I ,26
BCH code commonly used in supervisory control
systems. (A supervisory control system is, in
essence, a remote control system which allows a
human or computer operator the control of a
system via a serial communications link.) The BCH
codes are used because of their error detection
capabilities and are a class of cyclical redundancy
1-17
inter
,'DC
OBJ
Ap·24
SOURCE 5TAT£I'£HT
. .0
•• 23 FE
"2~ 0237
........................................
SERiAl INPUT U5IHG,TH[ I'ICS-48
THIS CDtlE ASS\K.S HARtIoIARE
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...
TJ!iRD
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PROCEDURE;
'2'
'"SHIfT CAI5!V INTO BJFf"ER·'
RX'-SERBUF;
,
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STAT
"S
115 ; INTJALJzt ROlITIHESTARTS RECEIV£ PROCESS
116 ;
It ? ~ - - - - - - - - - - - - - - - - - - - - - - - - - - - -
C
CD,
123
DISABLE INTERRUPTS.
P27·';
RX',#S[fmUf
A,ORXI
A
'"
,,.
START [VENT COUNT:
RQF-,;
A,ORI'
127
'22
RSHrT MEf'IHUI);
,
TiMER Ow 1;
"S
BCOUHT-SCOUNT-l ;
IF BCDUNT-' THEN
BCOut4T,S(K1T
,
....
P27".;
••
••••
.7
114 ;
A,P2
A
114135
DO,
l'1l\I
ecR
l'1l\I
DIS
START TlI'IER;
113
'''CARRY-RIO'll
CARRY ..P27 XHOR T[ST1:
JT'
TJI'£R"P;
7.
112
58
62
1135''''41
'TOT
CP,
DO,
os
I SERIAL BUFFeR
; REtE I'VE DOH£. FLAG
Tlf'£R-P;
IN
OLC
SLLD
71
92
93
; HLl'l8ER OF' BITS
OB'
ATEf'F,A
S'
IflC 882"
litE 27
1133 .43f
1 POI"TER
; 00;
I'II\I
SI
51 TISR'D: I'lOl/
52 SLOOP: xeM
RRC
S'
.S<
'C"
SS
56
DJHZ
"
••
••••
,132 AS
17H
••
"'5882'
1117 2'
1131 537F
; ,"ENTER INTERRUPT MODE·'
'S
os
R2
R'
•..
; STORAGE FOR A DURIHG IMTtRUf'T
; COHTAINS HtJIIBER or BITS IN MSG
1 UTILITY COUNTER
; -------------------------.----------------
28
29
31
..
.
..
..
R7
112F FE
; CDHTAOL. PASSED HERE IofoI[H TIMER ORO OCCURS
; ------------------------------------------
,
'119-FE
IliA 1'223
.
IF' T[5T1-' THEN
J"
82
12 ; ------'4; ------'S
16 ATEJII' 'OU
17 BCOUHT [QU
DO,
7<
7S
7.
,.
SJDIoI IN FIG 2 •• TO USE
THIS ROUTIHE,CALl INIT.
IrI£N Ror·, THE ASSEI'Il.ED
CHARACTER WILL BE IN SERBUF
S
A,SCOUl'tT
SLLC
13
1126 563S
•
••
71 START: IIIDY
72
JB6
111"'2 BABI
RI)F'-';
11"'4231'".
DISAIl.E EX INT:
l1li4662
EtlDI
'1"745
RltI,#RDf
A
1148882<1
OIUI.A
18"C 881t
TCtITI
"<1£
8.4A Bill
Its.
; [fOlD;
sice
25
US183
SEX IT
I ELSE
; 00;
".".
BCOUHT·IC,H OR BITHO
END;
END HilT;
l!~iT:
DIS
TeNTl
'"
133
DO,
MIIV
MDV
Pl,#8I1H
"S
51R1
MOIl
131
...
,.
...'"
,....
132
142
14'
IF BCDUHTl6J-' Tf£N
Mav
MOIl
MOV
'N
RET
A,It-1
T,A
eNT
IU',#RDf
@lRXI,#B1H
; POI NT AT BCOUHT
RXIJ."'[H
@RU.#UCIH OR BITMO}
TCNTT
; EHD
or
PROGRAM
'NO
Figure 22. Interrupt Driven Serial Receive Program
codes such as those used in synchronous data communications (e.g. BISYNC or SDLC). BCH codes,
named for their originators Bose, Chaudhuri, and
Hocquenghem, are characterized by having a length
of n=2m-l, The number of redundant check bits
can be mt where t is a positive integer (clearly mt
';;;;n), The 31,26 code fits this format with m=5 and
and t= I. The length of each message is n=2 5-1 =31
with 5* I redundant bits, leaving 26 bits available
for. data transmission, With an appropriate polyAll mnemonics copyrighted @ Intel Corporation 1976.
nominal BCH codes can detect all errors consisting
of 2t error bits and all burst errors of mt or fewer
bits. The 31,26 BCH code will therefore detect any
erroneous messages with I or i errors or bursts of
errors of less th~n 5 bits, The 31,26 format (shown
in Figure 23) requires the reception of a start bit
followed by 31 infonnation bits, clearly beyond
the cap;:tbility of the USART but perhaps within
reach of a program controlled approach using the
MCS-48 itself.
'
.
1-18
inter
AP-24
Figure 23. 31,26 BCH Code
A concept which reduces sensitivity to frequency
deviations and thus allows the reception of longer
codes is shown pictorially in Figure 24. The first
line of this timing chart shows an alternative ones
and zeros pattern on the RxD with a period of S
milliseconds. The second line shows that by
sampling at a period of exactly S milliseconds the
data can be properly interpreted. The third and
fourth lines show the effects of sampling with a
period of six and four milliseconds respectively. In
either case, an error occurs at the third sample
where both periods result in sampling on an edge
of the RxD signal. The third line of Figure 24
shows a hybrid sampling scheme which, based on
some additional information, switches sampling
periods between the two values. As can be seen in
Figure 24, the data is sampled with a 4 milli~econd
period until the sampling begins to fall behmd the
data; at this point the sampling period is increased
to six milliseconds and the sampling first catches
up and then passes the center point of the data. As
soon as this happens, the sampling period reverts
to the 4 millisecond period and the cycle repeats.
It can be seen that this scheme sets up a pattern
which repeats indefinitely and the data can be
successfully sampled. Note that the sampling pattern
established is alternating periods of four and six
milliseconds. The average period of this pattern, as
might be expected, is Smsec. Line 5 of Figure 24
shows the effect of a change in transmission speed
to a period of S.5 msec with no change in the
sampling time. The sampling is again successful but
the new sampling pattern is 4-6-6-6; 4-6-6-6, etc.
Note that the average sample is again equal to the
period of the received data (S .S). While this scheme
1
does seem to work, the question of what additional
information is needed remains.
The MSC48 must somehow decide when it is drifting out of synchronization and take corrective
action. By referring back to Figure 24 it can be
seen that if the MCS48 could determine where the
edges of RxD occurred with respect to its sampling
times then the additional information would be
available. As can be seen in the figure the choice of.
sampling period can be based on the following rule:
If an edge on the RxD line occurs during the
first half of the current sampling period, then
use the short period for the next sample. If an
edge occurs during the second halfof the period,
then use the long sampling period for the next
sample.
If the data on the RxD line does not change, of
course, the MCS-48 will drift out of synchronization
just as the original algorithum did. As long as edges
occur on TxD, however, synchronization· can be
maintained. To maximize the allowable time
between edges, the following addition could be
made to the above rule:'
If no edge occurs on the RxD line during a
sample, then change sampling period from short
to long or vice versa.
Note that this addition to the rule will result in
using an average of the two sampling periods when
no edge occurs for several bit times.
The edges of RxD can be easily detected by the use
of the same structure (the Exclusive - NOR gate)
which was added to the MCS48 in Figure 20. This
gate, which .is used to detect the edge on RxD
which begins the START bit, can naturally be used
to detect any edge. Since the timer is being used to
time the bit period, however, the event count input
(T I) is not useful during the receive itself. By connecting the output of this gate, however, to the
00 input to the MCS48 (see Figure 2S)' it is
possible to detect edges on RxD with the event
counter when the program is trying to detect the
START bit and by the external interrupt when the
program is using the timer to control the sampling
times.
Smsec PERIOD
5msecSAMPLE
2. 5msecPERIOD
6msecSAMPLE
3
Smsee PERIOD
4msecSAMPLE
4
5msecPERIOD
HYBRID SAMPLE
-l~~~--1.-'..J.....!!....I...'-'-.!C.J..::..J..--"-J...::..J-"-...I..
5. 55msecPERIOO
HYB RIO SAMPLE
-l..:...J..cc...L...::...L."--'-"'::""'.L...::....L.:-'....::....J....::....J'--'.....L..'--'-;-
Figure 24. Various Sampling Alternatives
1-19
inter
AP-24
Because of this edge detection it is important to
condition RxD with hardware filters to ensure that
the edges of RxD are clean. Any ringing will cause
repeated CALLs to XISR and probable erroneous
operation. The changes to the START process
(Figure 26c) are two-fold; first the TIMER is set to
one half the average of the two sample periods
when the START bit is first detected (BCOUNT
[6) = I), and second the processing of the edge
information, is initialized by presetting SNAP and
clearing P27 .
SNAP is preset so that when the reception of data
actually begins (Figure 26b BCOUNT [7) = 0), the
decision block which tests SNAP against LIMIT
will be initialized. This block actually compares the
value in SNAP with a LIMIT value which is used to
determine if the sampling point is ahead or behind
the actual midpoint of the serial' data. If the
sampling is ahead then the timer is set for TMIN;
if the sampling is behind then the timer is set for
0
x,
x,
AD
'NT
R,O
D
T,
WR
PAOG
ALE
P"
P'B
P'5
P"
P'B
P'5
p,.
p,.
P"
P"
P"
P,O
P"
P"
P,o
0,
DB
05
D.
03
0,
0,
00
TO
'5V
·V ee
Voo
ss
PSEN
Vss
EA
}.~
}..
RESET
Figure 25. Modified Edge Detection
A modification to the program of Figure 21 which
implements this new sampling algorithm is shown
in Figure 26. The first deviation from the original
program is the addition of a routine (XISR, Figure
26a which is called when an external interrupt
occurs (Le. when an edge occurs on RxD). This
routine saves the status of the running program and
then stores the current value of the timer register
in a location called SNAP (R5 of RB I). After
doing these operations the program complements
bit 7 of port 2. Manipulating P27 in this manner
will cause the Exclusive NOR gate to turn off the
'external 'interrupt' and will set it up to generate
another interrupt when the RxD line changes again
(has another edge).
NO
-L__________- L__~~.
Hybrid Sampling Flowchart
Hybrid Sampling Flowchart
1-20
AP-24
lOC
OBJ
SOURCE STATEMENT
SEQ
SERIAL INPUT USIHG MCS-48
THIS CODE ASSlA'IES HARDoIARE
SH[WoI IN fie. 25. PROGRAI'I
IS SIMILAR TO PREVIOUS
ONE. A I'IIJRE S(J'HISTICATED
SAI'f'L INC, AL(iDRITI-t'I IS USED
YES
,.
11
NOTE;
A PLII'I II KE LANGUAGE WAS USED
TO CD"I'IEt'lT THIS LISTING AND
SEVERAL OTHERS '1'4 THIS NOTE. NO
C(J'f'ILER EXISTS fOR THE MCS-48.
12
13
14
THE CIl1'lENTS WERE 'HAtm
IS
CiM'ILEO' 11'410 ASSEMBLY COD[
16
17
••••••••••••••••••••••••••••••••••••••
I.
19 : ------21 ; EQUATES
....
,117
1115
"12
nla
liZ'
11'<11
"05
"09
frEe
IIZI
1124
21 : ----.-22
23 ATE/'P
[OU
2"
25
2G
27
28
[au
BCOUHT
SNAP
COUNT
R.IIO
SITNO
[QU
[OU
[OU
EOU
29 liMIT
EOU
31
31
32
33
3<11
[OU
[OU
EOU
[OU
EOU
mAX
TMIN
HALF
SER9Jr
RDr
.7
os
; STQRA(;( FOR A DUR I HG I NT(RUPT
j CONTAINS NlJfII9ER Of BiTS IN M5G
.5
; TAICES TlI'ER SNAP SHOT ON IUD EDGE
.2
21
;
;
;
;
·43
; MAX SAl'PLE PERIOD
-39
; MIN!,.."... SAl'PLE PERIOD
; HALF HOI'IIHAL PERIOD
••
32
-21
21H
2OTQN[: MOV
"
A,caWH
10'-'
A,PTOS
,
A, :tellH
PTOS,A
COI..INT
CL'
MIlV
.3
""
; SET TXD TO CARRV
, .--------------------------_.--
"
MOV
M()V
MOV
A,CHAR'AV
GOTOHE
e
A,Burr
PTOS,A
COUNT,tlU
CHARAV, liB
'ET
; END Of PROGRAM
,"0
AP-24
CONCLUSION
This Application Note has presented a very small
sampling of the application techniques possible
with the MCS-4S™ family. The application of this
new single chip computer system to tasks which
have not yet yielded to the power of the micro:processor Will present a fascinating challenge to the
system designer.
GENERATING PARITY
Many communications schemes require the generation and checking of parity. If a USART is used
it can be programmed to automatically generate
and check parity. If the communications is handled
by software within the MCS-4S™ then the program
must perform parity calculations. Calculating
parity is easy if one remembers what parity really
means. A character has even parity if the number
of one bits in it is even. A character has odd parity
if it has an odd number of ones. The program segment shown in Figure 29 can be caused to calculate
parity. It starts by setting a loop count to eight and
lOC
OBJ
SEQ
SOURCE STATEI"£I'IT
2 ; ••••••••••••••
3 :
.tIj
;
.
PARITY
5 1
THIS PROGRAM GENERATES PARITY
6;
ON THE ACCLnllATOR
7 1
CARRY WILL BE SET IF A HAS ODD PARITY
:
'3 \ ••••••••••••••
""
12 ; .-----13 : EQUATES
'"; ._-----
IS
1112
111.
.'81 BAIB
111297·
16 COUttT
17
Ie PAR:
"22"
[QU
OR.
MOIl
CL.
. ..
11tH
COUHT I # 8
C
21
1183 77
.'."'217
"16 A7
23 LOOP:
J.t
25
27
2.
ePl
•
: SET LOOP COUNT
; INITIALIZE CARRY
: fOR EACH ZERO BIT IN A
; CQrlFLEf'llENT THE CARRY FLAG
OVER
e
; £I'ID OF PROGRAM
'""
Figure 29. Parity Generation
clearing the CARRY flag. After this initialization a
loop is executed eight times. During each execution
the accumulator is rotated and the least significant
bit is tested. If the bit is a zero the CARRY flag is
complemented, if the bit is a one no further action
is taken. Since an even number of zeros implies an
even number of ones for an eight bit character,
after all eight loops have been accomplished the
CARRY bit will be set if an odd number of ones
were encountered; it will be reset if the number
were even. Since the RR instruction does not
involve CARRY the net result of executing this
program loop is to set CARRY if parity is odd
without effecting the character in the accumulator.
All mnemonics copyrighted @ Intel Corporation 1976.
1-24
-
-
inter
APPLICATION
NOTE
Ap·40
June 1978
• Intel Corporation, 1978
1·25
9800755
intJ
AP·40
INTRODUCTION
This application notes presents a software package for
,interfacing members of Intel's MCS-48™ family of
single-chip microcomputers with keyboards and displays using a minimum of external components. Because of the similarity of the architectures of the various members of the family (the 8035, 8048, 8748, 8039,
8049,8021, and 8022 microcomputers; also the 8041 and
8741 universal peripheral interfaces in the UPI-41'"
family), the code included here could run with minor
modifications on any member of the family.
Since keyboard and display logic can be just one of
several functions handled by a microprocessor, the
added cost of including these functions in a system is
minimal. In fact, considering the extremely low cost of
standard X-V matrix keyboards and integrated displays,
their use is often more cost effective than even a handful of discrete switches and indicators. Thus, the additional flexibility of keyboard input and display output
can be added to inexpensive consumer products (such
as games, clocks, thermostats, tape recorders, etc.),
while producing a net savings in system cost.
In traditional digital system deSign, various hardware
registers or counters were used to hold binary or BCD
values which had to be conveyed to the user. The standard way of presenting this information was by connecting each register to a seven-segment encoder (such as
the 7447) driving a single display character, as represented by Figure 1. Thus, two ICs, seven current limiting
resistors, and about 45 solder joints were required for
each digit of output. Consider how traditional techniques might be (mis-)applied in designing a microprocessor system: the designer c )uld add a latch, encoder,
and reSistors for each digit of the display. Still another
latch and decoder could be used to turn on one of the
decimal points (if used). The characiers displayed could
only be a sequence of decimal digits. In the same vein, a
large matrix of key switches could be read by installing
an MSI TTL priority encoder read by an additional input
port. Not only would all this use a lot of extra I/O ports
and increase the system price and part count drastically, but the flexibility and reliability of the system
would be greatly reduced.
+V
Since each potential application will have its own
unique combination of keys and display characters, the
program is written so that very little modification is
needed to interface it with a wide variety of hadware
configurations. In general, the only changes required
are within the set of initial EQUates at the beginning of
the program.
a
Along with the basic software for driving a multiplexed
display andlor scanning and debouncing an X-V matrix
of key switches, a collection of utility subroutines is
also included for implementing the most commonly
used keyboard and display utility functions, such as
copying simple messages onto the display or determining the encoded value of each key in the key matrix. As a
result of the versatile architecture and applications"
oriented instruction set of the MCS-48 family, the entire
package fits into about 250 bytes of internal program
ROM or EPROM, leaving the rest of the ROM space for
the program to cook the perfect piece of toast, or whatever. By tailoring the software to match a known hardware configuration, or by selecting only those functions
needed for a given application, the' program size could
be even further reduced.
Since what is being presented in this application note is
a software package, rather than the usual hardwarel
software system deSign, the format of this note is somewhat different from most - it conSists primarily of a
long program listing reproduced in the following pag,es.
For the most part, the listing is self-explanatory, with
comments introducing each subroutine and major code
segment. Some parts of this introduction are repro, duced in the program listing itself, explaining the configuration of the prototype system. However, an additional bit of explanation would make the listing easier to
understand, especially for those readers unfamiliar with
the concept of multiplexed displays and keyboards.
CIRCUIT REPEATED FOR EVERY DIGIT OF DISPLAY
(DOTS USED TO INDICATE SOLDER JOINTS)
, Figure 1. Wrong Way 10 Design Multiple Digil Displays lor
Microcomputer Systems
1-26
AP·40
Instead, a scheme of time·multiplexing the display can
be used to decrease costs, part count, and interconnec·
tions, while allowing a wider range of character types to
be used on the display. The techniques used here are
fairly typical of today's integrated subsystems designed
especially for controlling keyboards and displays (such
as in calculators or the Intel@> 4269,8278, and 8279 Key·
boardlDisplay Controller Devices).
to be displayed, and turns on the appropriate segments.
With the next character now turned on, the processor
may now resume whatever it had been doing before. The
whole display updating task consumes only a small frac·
tion of the processor's time.
In a multiplexed display, all the segments of all the
characters are interconnected in a regular two·dimen·
sional array. One terminal of each ,segment is in com·
man with the other segments of the same character; the
other terminal is connected with the same segments of
the other characters. This is represented schematically
in Figure 2. A digit driver or segment driver is needed for
each of these common lines.
1SEGMENT
J DRIVERS
_m __ __ __ __
__
w
_
~
~
~
~
SEGMENTS SEGMENTSSEGMEflHSSEGMENT5 SEGMENTS SEGMENTS
D~T_
~!!...
~c!!...
~~
_D~T
_~IT
1DIGIT
I "a" SEGMENTS OF
J All
J DRIVERS
DIGITS
~;-t-"",-:+-"",-:+-"",-:+~-:+~d-l"b"sEGMENTSOF
J ALL
DIOlrs
~;-,-t~;-,-t~rl-~t-"-'"t-""""-+- !"C"SECMENTSOF
J ALlDIGLTS
CURRENT
SOURCED
"
Figure 3. Segment and Digit Drivers used with 6·Posltlon, 7.Segment
LED Display
-'<":'""r--'C':""r--=-t-"'C:"-+-""'"-+-"""+- 1"d"SEQMENTSDF
J ALL DIGITS
SEGMENT
DRIVERS
~-::.rl~-::.rl~c1-,-""!-","+---=+- j ..... SEGMENTSOF
JOIGITS
-rir--,--1r--=-r--"'"'"+-"'"+-"""+-I"'''SEGMENTSOF
I DIGITS
-~!-~f-'-""!-"""+-""O':-+-~+-l "g"SEGMENTSOF
J ALLOIOITS
-ri-rir--;;:-:-r--"'"'"t-"'"'"+-",,-"+-
I
DECIMAL POINTS
, ALL DIGITS
OF
Moreover, since the computer rather than a standard
decoder circuit is used to turn the segments off and on,
patterns for characters other than decimal digits may be
included in the display. Hexadecimal characters, spe·
cial symbols, and many letters of the alphabet are pas·
sible. With sufficient imagination this feature can be ex·
plaited for some applications, as suggested by the
examples in Figure 4.
CURRENT SUNK BY
DIGIT DRIVERS
Figure 2. Schematic Representation 016·01gll, 7·Segment
Common·Cathod LED Multiplexed Display
,L"-'
,'- '- '-, '-,,-,
The various characters of the display are not all on at
once; rather, only one character at a time is energized.
As each character is enabled, some combination of seg·
ment drivers is turned on, with the result that a digit
appears on the enabled character. (For example, In Fig·
ure 3, if segment drivers 'a', 'b', and 'c' were on when
character position #6 was enabled, the digit '7' would
appear in the left·most place.) Each character is enabled
in this way, in 'sequence, at a rate fast enough to ensure
that the display characters seem to be on constantly,
with no appearance of flashing or flickering.
'I
L
, L'L
'I I I
,-, L/Il ,
In the system presented here, these rapid mOdifications
to the display are all made under the control of the MeS·
48™ microcomputer. At periodic intervals the com·
puter quickly turns off all display segments, disables
the character now being displayed and enables the next,
looks up the pattern of segments for the next character
,-,-, , 'I
'
'-'-'-, ___ -
/,- 1,/,
d=
III
Figure 4. Examples '01 Typical Messages ,Possible with Simple
7·Segment Displays
1-27
AP·40
As each character of the display is turned on, the same
signal may be used to enable one row of the key matrix.
Any keys in that row which are being pressed at the time
will then pass the Signal on to one of several "return
lines", one corresponding to each column of the matrix.
(Sell Figure 5.) By reading the state of these control
lines, and knowing which row is enabled, it is possible
to compute which (if any) of the keys are down. Note
that the keys need not be physically arranged in a rectangular array; Figure 5 is merely a schematic.
COLUMN 1 COLUMN 2 COLUMN 3 COLUMN 4
REtURN
RETURN
RETURN
RETURN
LINE
LINE
LINE
LINE
TO SWITCHES
ON ADDITIONAL
RETURN LINES
FROM SWITCHES ON
ADDITIONAL SCAN LINES
machine cycles. :One machine cycle occurs every 30
crystal oscillations for the 8021 and 8022, or every 15
oscillations for all other members of the family.) A more
detailed explanation of these variables is included in the
listing.
Port assignment is also at the discretion of the user all port references' in the listing are "logical" rather than
physical port names. The port used to specify which
character is enabled is referred to as "PDIGIT". The output segment pattern is written 1-0 "PSGMNT" and the
keyboard return lines are read by "PINPUT". These
logical port names may be assigned to whichever ports
the user pleases.
By way of example, the breadboard used to develop and
debug' this software used a matrix of 16 Single-pole
push buttons and an 8·character common-cathode LED
display with right·hand decimal point. No decoders external to the 8748 microcomputer were used; all logic
was handled through software. PDIGIT was the 8-bit
DUS, PSGMNT was port 1, and PINPUT was port 2. The
drivers used were 75491 and 75492 logically noninverting buffers: high level inputs were used to turn a
segment or character on. Pull-up resistors were used on
the 8748.output lines to source the current levels
needed by the buffers. The 8748 was socketed on the
breadboard, and was driven with an inexpensive 3.59
MHz television crystal. The short test program included
in this listing was used to echo key depressions as they
were detected, and ·to invoke four demonstration subroutines. A summary of the subroutines included in this
listing with a short explanation of the function of each is
included in Figure 6; Figure 7 shows how the various
utilities interact.
Figure 5. Schema'ic of X- Y Ma'rix Mulliplexed Keyboard
KBDIN
Since each character Is on for only a small fraction of
the total display cycle, its segments must be driven with
a proportionately higher current so that their brightness
averages out over time. This requires character and seg·
ment drivers which can handle higher than normal levels
of current. Various types of drivers can be used, ranging
from specially designed circuits to integrated or dis·
crete transistor arrays. The selection depends on
several factors, including the type of display being used
(LED, vacuum flourescent, neon, etc.), its size, the
number of characters, and the polarity of the individual
segments. Some drivers have'active high inputs, some
active low. Some invert their input logic levels, some do
not. Some require insignificant input currents, some
present a considerable load. Some systems use externallogic to enable one of N characters or to produce the
appropriate segment pattern for a given digit, some systems implement these functions through software.
CLEAR
ENCACC
WDISP
RENTRY
PRINT
FILL
ECHO
RDPADD
HDLD
Because of these and the other variables which make
each application unique, provisions are made in the first
page of symbol EQUates to allow the user to specify
such things as the number of characters In the display
or the polarity of the drivers used, and the program will
be assembled accordingly. The display is refreshed on
each timer interrupt, which occurs every 32 x (TICK)
DELAY
Keyboard Input. WBits until one keystroke input has been received
from the keyboard. determmes the meaning or legend 01 that key and
returns with the encoc:led value In the accumulator.
Blank out the display
Encode accumulator with bit pallern corresponding to the segment
pattern needed by the dIsplay to represent that symbol or character.
Uses the value of the accumulator when called to access a table can·
talnlng the patterns for all legal mput values.
Write into Display. Writes the bit paltern In the accumulator mto the
next character pOSition of the display Maintains a character position
counter so thaI repeated calls Will automatically write characters inlo
seQuenttal pOSItions
Righl·hand Entry. Siores the accumulator segment pattern In the
display In the rlghl·most character position. ShIfts all other characters
to the lell one place
Print a siring of arbItrary characters onlo the display. Useful for pro·
mpt.ng messages warnings. etc Uses a lable 01 segment patterns In
ROM. so thaI messages Will not be restncted to numbers. letters. elc.
Fill the display With the character pattern In the accumulator. Useful
lor writing dashes. segment test patterns. etc .• IOta all character posi·
tlOns
Walt for a key to be pressed by the operator and wrile that key onlo
the display Used for providing feedback to the operator when enter·
Ing numeric data. etc
Adds or deletes a deCimal POint to the character at the tlght·hand Side
of the display. lor entering lIoating pOint numbers
Called when a key IS known to be down Does not return until all keys
have been released. Used lor organ· type keyboards. or when some ac·
I.on should not be Inlflated unltl the key invoking that acllon has been
released
PrOVides a crude real·tlme delay corresponding to the value of the ac·
cumulator when called. Can be used 10 cause d.splay characters 10
blink. to momentarily flash Information. to enable a buzzer. elc Could
also be used by the program when delays are needed. such as to slow
down the computer reaction rate while playing a g:ame againsl the
human operator.
Figure 6. U'lII'y Subroutine Deflnilions
1-28
AP·40
MAIN BACKGROUND PROGRAM
I
CLEAR
I
FILL
I
I
.J+
I
PRINT
ECHO
RDPADD
KBDIN
ENCACC
RENTRY
DELAY
HOLD
Figure 7. Subroutine Interrelationships
I
2"[,lsf,otJ
•
•
J~
~CC VDO
75491
.13
"
f"F
~
."d" . .,..I.,... j"d'P."j
F'E'ElPr'F'F'r'l
=1. -'. _. ~. ~. ='. !:i. ='.
."S"
_"b'
"~"
_lEF!:~,?~!
'------'
I.
~
~
15492
0@@J:
@@}@D
I I
II
ALE
3<
! ! 1
"
pli
"
"
"
I.
I.
"·~"(E
I.
~
~::~:
N.C.~
.!!
N.C •
~
I
P20
P21
EXPAN~g: ,~ P••
13
75492
8748
13
II
II.
•
':: I!-
33
I'
P••
35
38
I
3'
38
--"~-""-
l~
Flgu"; 8 Prototype System Schematic
1-29
~~fN.C.
:::~
31
32
~
CD@@JD
T1
iNT
30
"
I~\\'::A~~:~
TO
211
;5491
55
2'
20
---'
N.C.-:
N.C..2
0®®=
-=
j
-l1l.!.\,J,J
"e'
h~~ T' 'y....
AP·40
1515-11 H(;S-48/1j;"1-41
MAC~J >\SSEf1lllE~,
'.12 [J
ANfJ lNfEl 11(5-48 fH'BllftFL'tl5F'LH" Hl'PLl(AllOll NC,TE APPElt',!,:
LOC iJBJ
1 SHAU'oF I LE ~\~'EF
2 nITLE' 'AF'40, WTEL
M(~:-48 I:E~Bl;HflD,'['ISPLH"
HPF'LII)ITIOtI NOTE APPENDIX",
4 ,THE FOLLi.MING SOFTIoiAPE P~iClAGE PP.O,,'WE5 fI 51:VEN SEliI1ENT [,ISF'Lfili
5 ,INrEP.F~Cr. Hili mC~~(lCO~1FIJTER~ iN THE lNTtl ;n-4S Fflt'!IL'y'
,; ,THE CODE IS WP.I HEN SO THAT VAl<' lOLlS HHFfll4APE
7 ,CI.lltFIGIJF.'fl1 IONS CAN f>E Al);.)t10(!ATE.[' 8'T' F.E[l£I' !t.JIIIj [HE HlI lIill "'~:IABLES
8 , IN MOS r 5ITUftTiONS, THE ~E','80Aj;'t'/IiL5FLH1' lUTERFFtCE WILL BE ~'W.lIRE[\ '\G
9 ,iMF'lHIEln MO.E. SOPfHSTIGfiTE[; ,:INGLE-CHiP Sl'5IEMS (c.~LL'lJuno~':;:, ,fflLE.S, CLUI.'f..5,
19 ,!:.Te, ), WITH SE('T!()NS OF THE FGLLl.lWINb un 3E'LECTEIJ AND i'liHF!E[> AS NECESSAfI"
11 ,FO~' mCH tlPPLl CATION
1<: '
~: ,A SINGLE SUflPWllNE «(fUEi) f;UJ.'SH! IS CISEu TO IMf'WlENi BOTH THE DISf-'Lkl'
14 ,joJIJLTIPLD:INlj AN[, ~E'y'BOftRt' SC,lUN1Nlj. 1J<,1N(' THE SRt11: ~j(jNAl BorH TO EIlABLe
15 ,ONE CHfiI?AClt~' OF THE DISFLA',' F1f4\ ,0 STROBE ONf ;;'0101 OF ,fit i(-Y ~'E'" tlffTPlt!
16 ,IHE SUIWOUTIPlE MI.I5T BE CfiLl,£[; ';lIFf'l,:mHL,' 0HEU 11) HISIJIlF. rH~ vISI'Lfl'i
r' ,CHf1F:AC1E~':, riO NOT FLlCKH'- Ai LEAS T 5.,1 tt)I1F'LETE DISPl.A" SefiPlS PER ~.ECONv
1:3 ,TO Hl(Wl0[JATE SWITCHES (If Aj;'t>lTRH~Y CflEFtPNESS, [HE DElMJNCE TIME GAP! BE
19 ,sn T,) BE ANI' [>tSIPED NI.lMBER or CONFUTE SlANS
28 ,THUS THE llEBi)IJNCE THfE IS H FUUCTION OF 80TH ,HE SCHN kFilE AND ,HE VALlJ!:.
i1 .,0F CtJNS rANT 'VEBNCE'
2i .'
~~ ; It! THIS Ll~T1NG, THE INTE~NAL ilME~' IS I)SE~TQ IjEt;EPAIE INTERRLlP'I5 THAT
24 ,SERVE AS A TIME BASE FOR THE PEFP[SH 5UBPOllTltlE
<:5 ,ALTERNATE mlE BASES MIGHT BE fiN EXTEPNAL u';CILLAi..w q)~I'JWI.l THE It-llERI TlRET
]0, mINT ~ElURN) GOIJl[, STilL BE I,;SE[1 TO ::;AVE AND "ESlOPE A(CtiMULflTOt.' CONTENTS
}1, THE INTEPFUF'l SEF.'\'ICIN(; flOI)TINE SELECTS J.'EGlSTE.' BANK 1
n ,FOP 1HE NEEVEli REGISTERS
2.3 '
A',
0:5 "Wi"lTWI I::Y JOHN WHfIRTUN, INTEL SIIl(;LE-CHIP COt'lf'UTER ftPPLlCATIOr4S
]6 '
'j,i !EmT
All mnemonics copyrighted @ Intel Corporation 1976.
1·30
AP-40
ISIS-II r1(,s-48.'UPI-41 i'fHCPO flSSEMBLER, V';: B
INTEl MCS-48 KEYBOAl1[,/IiISPLfi',' RPPLlCAflON,NOTE APPENIiIX
flP48
LO(' CIB]
SEO
SOUIICE STATEMENT
s8 ,IN iHIS Ii1PLEMEtHtil WN 'jF THE [015PUI'~ SCAN. IT 15 ASSUMED "iHfH THEilE WILL
:;9 "BE I"El.AlI','EL" L1TTl.E 1/0 OTHEII THAN ~,)", THE KE'r'BOfW[i/[OISf'LA',
4e ; IF HHS 15 THE CASE. THEtl THERE I~ NO NEED FOil FI.l~ RN'" AWIiIONAL EXtEPNAL
41 ,LOGIC (SUCH f6 ONE-of-ElGH1 DEW[OEI"S 011 :;E'~EN-SEGt1Hn ENCODERS), THOUGH
4~ ,THE~'E
43
44
45
46
47
48
49
5e
51
52
5~
:,4
55
16
'i,
58
59
6@
61
62
6,
64
65
66
WILL STILL BE A HEEl) FO~' CU~'REN1 OR VOLTAGE Dl HAT!,:!,', WEIi:E tlECTi<'ICftLL',' OPGANI:;ED
92 '
IN A 2:<8 ARRAY, ONLY TWO RETURN L1tlES Wt)IU BE NEEDED.
93 ;
i1N THis CASE, PEPHAPS Tii it,ll" 11 COllLD BE I)sE[J FOR INF1JT BIT::' "
94,
95 ,PULL -uP I<'ESISTfJRS ON THE
IIETI~N
LINES I'IIGHT BE III ORDEI< IF
THE~f
15 AN"
96, POSSIBILITY Of A HIGH-li'1PEDENtE CONDUCTIVE PHTH THRW(,H THE SWITCH WHEN
9, ,IT 15 SlIPF'OSED TO BE 'OPEPI'.
98 ,(THIS PHEHOI'1ENON HAS ACTlIALL'1 BE!:N (.BSERVEL· ;.
99 ;
10!:l , THE r~I"'ER5 USED IN THE pFiOTOlYPE HEf.'E ALL NON- INVERTING IN THAT
1~1 ; A HIGH LEVEL ON tlN WTPUT lINE b USED TO TIJRN Ii CHflRRCTEfi OP SEGMENT ON
192 . THERE ARE A TOTAl. OF SEVEN 1/9 LINES LEn (lVE~
1tl?
104
195
106
;
.
• THE ALOORlTHII FOIi: Llff'ECTl VEL ~'J
122 ,
123 ; THE K~YBOAR(l SCANNING ALGORITHM SHOWN HERE REQUIRES fl ~EY BE DOWN FOR
124 ; SOlE NlIHBER OF CO/1PLETE DISPLAY SCAN::' m BE ACKNOIoILEGED. SINCE IT IS
125 ; INTENDEv FOR '()£-F INGEll' OPERATIVN, Two-KEi' ROLLOI/ER/N-KEi' LOCKOUT HAS
126 ; BEEN IIIPLEMENTED HOIoIEVEFI, MOOIF (CATIONS IoIOll.D BE POSSIBLE Til ALLOW. FOR
127 ,EXAI1PLE, ONE KEY IN THE MATR1:, TO BE USID AS A SHIFT KEi' OR CONTROL KEY
128 • TO BE HELl) DOWN IoiiILE ANOTHE~ KEi' IN THE MATRI~ 15 PRES5Ev (SEE HuTE WITHIN
1~9, THE BOO',' OF THE LISTING, )
130;
131 SEJECT
All mnemonics copyrighted @ Intel Corporation 1976.
1-32
inter
AP·40
~~
PAGE
INTEL I'IC5-48 KE't'EOAFDlvI5PLAY APPLICi1TION NOTE APPENDiX
ISIS-II I'1CS-48/UPI-41 MACRO ASSEtlBm', '<'2
AP49
Loe OSJ
SEQ
4
SOIJRCE STATEt1EIlT
122 ; (BE flWARE THAT NO t'10~:E THAll TWO fl',':; CAN ~VEP BE D(j,IN UNlESS (,lODES
13:; ,ARE !'LACEr' IN SEkIES WITH ALL OF THE ~WITCHE5- CERTiHNl\' NOT THE CASE FOR EL
134 ,CHEAPO I\E't'BOARDS- BECAUSE SOME C,IMBINATIONS OF THREE KEYS ['oWN WILL RESULT
135 ; IN A 'PHAtHIJI'I FOURTH m' BEING p~RCm,'f.[,
136 ,THE PHANTOM rE',' I~OIJlD BE THE FOURTH CORNH" WHeN I HPEE KE'iS FORrmlG
E7 ,A "'ECTANGIJLftP PATIERN I IN THE ;':-'i ~E'r' /-IATRIX', ARE IXlWN \
E8 ,IF (HOOES H!<'E PLACE!: III THE SCrilllllNG MRRA'i, CONSiDERATIONS MUST BE NAvE
139 ,AfiOliT HOW THE DIODE VOL TAGE D~:OF' WILL fiFFEcr lHf'UT LOGIC LEVELS
140,
141 ; WHEN f, [iEBOIJNCEI> tH 15 DETECTE(', THE NUMBER 01' ITS POSITION IN THE f'El'
14~ ,MATRIX (lEFT-TO-I1IGHT., Bonurl-TO-TOP, STARTING FROM ell) IS PLACED INTO
143 ,PAM LOCATION '~B['I!IJF' AN INPUT SlJB~OIJTlNE THeN NEED ONL ... READ THIS LOCATION
144 ,I"EPEATE[I\. ... TO ~lERMINE WHEN H f:E',' HAS BEEN PIIESSED WHEN A ~El' IS DETECTE[,·
145 ,A SPECIAL COOE BYTE ~HOULD BE WRITTEN BAC~ TO INTO 'KBDBlIF' TO PI/EVENT
146 ; REf'EftrEf' fHE(! IONS OF THE SAt1£.KEI'
147 ; THE "'OUTINE 'KBDIN' DEf'lOI15TP.fliE A Tl'PICFt!. INPlIl F'ROlOCOL. ALONG WITH f1 METH(I[I
148 ,FOR TRANSLATINu A KEY posmON fO ITS ASSOCIA1ED SIGNIFICfiNCE SI' AC(b~,INJ.j
149 ; TABLE 'LEGN(;S' HI P.Ol'1.
150 '
151 SEJECT
All mnemonics copyrighted © Intel Corporation 1976.
1-33
inter
Ap·40
ISIS-II l'lCS-4~/UPHl MACIIO ASSEt·1EUR, 112. tI
PIIIjE
flP4/3' INTtL 1'1(5-48 kEI'BOAPMHSI'Lft\' APPLICATION NOTE APPENIH:\
Lor liBJ
ae10
eOOB
0009
SOIJPCE STATEtlENT
SEQ
152 ,*'U HA ."'...'" ~ 1*"'*... ·H.t<*.j<****~***.**.t**********"'************** .
!'5} •
1'54, ' - INITIAL EQUATES TO DEFINE SYSTB'I CONFIGURATION
155 .
156 ; ******H"..t***.t<*",,,,**.t<**.********.t<*** .., ,..********************
157 ;
158 PD!GIT W)
; USED TO ENABLE CHARACTERS ANI) STROBE ROWS OF KE'IBOARD
BUS
159 P5Gt1NT EOli
,USED TO TURN ON SEGHENTS OF CURRENTLY ENABLED DIGIT
F1
1613 PINPUT WJ
P2
,PQF:T USED TO SCAN FOR KEY CLOSURES
; (NOTE THAT THIS POIIT ALLOCAllON USES THE HIGHER
161
; CURRENT SOIJRCING ABILlT'r' OF THE BUS TO SWITCH ON THE
162
; DIGIT DR I '/ER5, AND LEAVES P23-P20 FkEE FOR USING
163
• AN 8243 PORT EXPAN\)E~' I H !HE S'~STEt1. )
164
165 ;
166 POSLOG tOU
167 NEfiUXi EllIJ
168 .
POSLOG ; DEFINES WHETHER OUTPUT LINES ARE ACTIVE HI OR LOW
E9 CH~FfJL. Ef,iIJ
1iO SEGPOl . COl)
POSLOfj ,\FOR [:'RI','lNG CHAIIACTERS fIN!) SEG1'IENT PATlERIIS
0HII-i
,ru INES 8lT5 IJSED AS INPUT
171 INPHSK Erill
1('2
I
1n CHARNO EOIJ
~0F
5
174
flllO~1S
175
176
1;7
178
1,9
188
181
182
183
184
185
1-lC~LS
6
E"QU
.
TICK
WJ
['EBNf..E b)lI
8LAttr. WU
;
ENCI'l5k EW
.
SEJECT
; NUt1BEI1 OF (llGllS IN OISf'LA't'
t'F KEYS ,LESS THffN OR EQUAL TO CHARNQ)
,LE5SEf' DHiENSION OF KEYBffiRD MATRIX
,~·ows
E,tU
-1SH
4
00"l
• [:ETEliI'1lt1ES INTERRUPT INTERVAL
. NUMBER OF SUCESSIVE SCANS BEFORE KEY CLOSURE ACCEPTED
.' CODE TO BLANI<' 0I SPLAY CHARACTERS.
. (lo!WlD BE 20H IF ASCII DECODING ROO USED OR flFH IF
.7447-WPE SEVEN-SEGMENT DEC1JDER EXTERNAL TO 8748)
0FH
,SELECTS WHICH BITS ARE RELEVANT TO ENGACC SUBROUTINE
All mnemonics copyrighted © Intel Corporation 1976.
1-34
-Ap·40
I SIS-II HCS-48/l1P I -41 t1IlCRO ASSEMBLER, V2. e
PAGE
AP49: INTEL HCS-48 KE'r'BOARD/DISPLAY ftPPLICAfIGN NOTE APPENDIX
LOC OBJ
SEQ
6
SOURC,E STATEMENT
186 ,~**********,,***********.j 39
299
HOII
ftOD
MOil
291
MOY
A, ISEGMfif'
A.• CURDI(j
PNTR1. A
fl, @PNTk1
292
293 ,
OIJTL
P5Gt1NT, it
288
289
; LOAf) Ace 101/ NEXT SEGMENT PATTERN
,ENABLE APPROPRIATE SEGtlENTS
294 ; *******.~********,.***************~~**********~**~********~*
295 ;
296 ;
297 ;
901£ B821
002a 9A
THE NEXT CHARACTER IS NOW BEING DISPLAYED.
THE KEYBOARD SCAN R(JIJTINE IS INTEGliHTED INTO lHE DISPLAY SCAN.
WITH THE CURRENT ROW ENERGIZED. CHECK IF THERE AilE ANY INPU1S
298 ; **************************************~***.j<***.j<.j<***********
299.:
309 SCAN.
MOY
PNTRe, tKEYLOC ,SET POINTER FOR SEVERAL KE'r'l.OC REFEIIENCES
391
IN
/1, PINPUT
; LOAD ANY SWITCH CLOSURES
302 ;
303 ; ..................................................#...................... .
304 ; III
THIS BLOCK (IF CODE IS NOT NEEDED 8Y THE KE ....BOApr' SCAN LOGIC
•••
305 .'"
HOWEVEfI, ITS INCLIJ5ION WOULD SPEED THINGS UP A Bll BY
...
3lJ6 ,II
SKIPPING OVER ROWS IN WHICH NO KEYS AilE DOWN.
II.
397 ;..
IT WAS OMITTED HERE TO CONSERVE ROH SPACE, BUT 11lGHl BE
...
30a ,..
RESTORED IF IIEIIY LARGE KEYBOARDS (ESPECIRLL'r THOSE WITH EIGHl
•••
309 ,..
KEYS PER ROW) ARE TO BE USED WITH THIS ALGORITHM
•••
31B: ........................................................... tItI.............
311 ;..
eft
A
; ANY CLOSURES [.oI::TECTED ARE 1m'", ONE 81 T5 tI..
312 ,.11
ANL
A, • I NPMSK
•••
313 ; ttl
JHZ
SCAN!; -IF A K~Y HI THE CURRENTL"r ENABLED ROW IS DOWN •••
314 ,it;
NO KEY 15 NOW OOWN SO THE KE'~LOr COIJNT l'tA',' BE IJPDAIED DIRECTLY ...
:1l5 ;..
~lOV
A. @PHTR0
...
316 ;..
ROO
A, .NCOLS
•••
:m ; it
MOil
@PNTRl!, A
III
318 :..
.IMP
SCAN6
Ill.
319 ; ........................................tItI••••• tll •••••m .................
329 ;..
IF THIS (;ODE IS USED, SUBSTITUTE THE ; Je SCANS' FuUR LINES
...
321: ••
HENCE WITH 'JNC SCANS· TO A(;COI1ODATE THE I HI/ERTED POL~ 1T'r'
•••
322 : ..........................................................................
323 sEJECT
All mnemonics copyrighted © Intel Corporation 1976.
1-37
inter
Ap·40
ISIS-II IICS-48/UPI-41 I1ACRO ASSEt1BLER, 112.8
PAGE
9
ff49. INTEL IICS-48 KEYBOARD/DISPLAY APPLICATION NOTE APPENDIX
LOC OSJ
SEQ
SOORCE STATEI1ENT
.*"'*"'*"'***************************."'***********************
ROTATE BITS THWl/I'JH THE CY WHILE INCREMENTING KEVlOC
326 .; .**********************************************************
327 ,
324 i
325 ;
8921 8004
8923 F7
0924 AC
0025 F63F
328 SCANt: 1101/
329 NXTLOC: RLC
I10V
338
JC
m
ROTt.'NT, IINCOLS
A
I"OTPAT, A
SCANS
; SET UP FOR (NCOLS) LO(fS THFOUGH 'NXTLOC'
SAllE SHIFTED BIT PATTEI1N
; ONE BIT IN CY INDICATES KEY NOT DOWN
i
:>32;
313 ,***************************-1<****************************"'**
334 ;
335 ;
HT THIS POINT IT HftS JUST BEEN DETERMINED THAT THE VALUE
336 ;
OF KEYLOC IS THE POSITION OF A KEY WHICH IS NOW DOWN
I~;' ;
THE FOLLOWING CODE DEBOUNCES THE KE'r', ETC.
33S ,
IF MODIFICATIONS TO THE KlYBOARl> LOGIC, l. E. THE INCLUSION
:m ;
Of A SHIFT, CONTI"OL.. OR MODE KEY Itl THE KEY HATRIX ITSELF)
349 ;
ARE DESIRED, THEY SHOllD BE MADE AT THIS POINT, BEFORE
341 ';
THE DEBOUNCE LOGIC BEGINS. FOI" EXAI1PLb AT THIS POINT
342 .;
KEI'LOC COULD BE COMPARED AGAINST THE POSITION OF THE. I100E
343 ;
KEY, AND IF THEY MATCH SET SOME FLAG BIT AI{) JUMP TO
344 ;
LABEL 'SCANS'. OR, BY COI'fPftRING KEYLOC AGAINST THE LAST
345 i
KEt' DEBOUNCED, IHMIODIATE TWO-KE',' ROLLOVER COULD BE
346 i
IIIPLEl'fENTED.
347 .;
9027 AS
0028 B5
348
349
350
351
,*****************>t-**************************.fc**************
i
(;LR
(''PL
; MARK THAT AT LEAST ONE KEY WAS DETECTED
; \ III THE CURRENT SCAN
F1
.Fi
352 ;
353
i
3S4 ;
355 i
0029 F9
002A 2E
002B DE
002C ·8820
002E C634
*******01<***************************************************
A KEYSTROKE WAS DETECTE!> FOR THE CURRENT COLIJIN. ITS
POSITION IS IN REGIS1ER KEI'LOC.
SEE If SAME I787
!le38 AiJ
0039 963F
8938 FE
893C 8822
003E A9
378
379 ;
389 SCAN~.
381
382
383
384
385
366
387
110Y
JZ
DEC
I10V
JHZ
11011
HOY
1'101/
A,~NTR8
SCANS
A
@f'NTRIl.A
SCANS
A, LflSTl'Y
PNTR9, *VB£i8iJF
@PNTRll,A
388 ;
003F 8821
904118
9tf42 Fe
!.III43 ED2:;
9945 EFS7
389 SCANS.
:;90
:m
1'1011
392
393 .
394 ;
395 SCAN6.
DJNZ
PNTRI.!. IKEYLOC
@PNTR0
fI, ~OTPAT
ROTCUT, NXTLOC
D.JNZ
CURD I 1], SCAN3
1'10','
INC
;96 ;
397 fEJECT
All mnemonics copyrighted © Intel Corporation 1976.
1-39
; I F AL~EAO't' ZE~O
• INDICATE ONE tl()~E
SUCr.ESI~'E
'H liUECTlON
dF DECREMENT DOES NOT RESULT IN
; TO MARK NEW KE.Y
CLOSIJ~'E
;::E~'O
Ap·40
ISIS-II MCS-48/UPI -41 t1ACRO ASSEMBlER, ',12. (I
PAGE' 11
RP4(1: INTEL HCS-48 KE'r'BOARD/DISPLfl'r' flPF'lICRTIONNOTE flPPENDnl
LOC OBJ
SEQ
SOURCE STATEI'1t:.1l7
398 ;
399 ; *************"'***********"*";**********'~*******"'*"'**********
490 ;
THE FOLLOWING CODE SEGI'lENT IS USED BV THE KE'r'BOAR[! SCANNING f"OIJTlNE
401'
IT I 5 EXECUTED ONLV AFTER A REFRESH SEQUENCE OF ALL
492 ;
THE CHAFACTERS IN THE DISPLAY IS COMPLETED
493 :
404 ;
0047
8049
0048
004D
904F
BFOO
8900
764F
BEFF
A5
0050 B923
0052 Fl
0053 COS7
9955 97
9056 Ai
495
496
497
408
409
410
411
412
413
414
415
416
417
418
419
****************************'1<*********"'''''1-*'''***'''****'''***.''''1<''
MOil
MOV
JF1
MOV
SCANS: CLR
CURDIG,IICHflRNO
,PNTR0 STILL CONTAINS IIk'E~'LOC
@PNTR0·110
; JUMP IF ANV KEVS WERE DETECT!:.D
SCAN8
,CHANGE (LASTK'f) WHEN NO KEYS ARE DOWN
LASTK'r' .lI0FFH
F1
;
.' **********************"'*********t**************************
.:
THE NE~:r CODE SEGMENT IS THE INTERRUPT-DRIVEN PORTION OF THE 'DELA'T"
.:
UTILlW IT DECREMENTS RAM LOCATION "RDELAV' ONCE PER OI5PLAY SCAN
.:
IF 'RDELAY' IS NOT ALREADY ZERO
,; *******~**************************U,~~***'I<*"'***"**********"
•
PNTR1,IIRDELfI't'
MOil
, MOV
A.@PNTR1
SCAN9
JZ
[lEC
A
429
@PNTR1,A
MOV
421
422 ;
9957 83
423 SCAN9' RET
424 .
425 ; *"'**i:**************,....**,.+·'H*·"i·t·I~:i~·*j:~*"'i<** ..*t**..***ot,***..
**
426 ;
0057
0058 01
0059 '.1~
f.ju5A 04
0(l5E! 08
B0se 1(1
(U)5!i 2('
flf:!:oE 40
1:01<: CHRPOl)
c'
-i-JI
,'I;.
,(10003<110[: :~i)f. CHRPOL J
,Oeljc.l01tXlE· xO!': !~HRPOL)
r..1;
4:1
tIE
1300:)10000 mR CHRPOL)
.tJ2
J?:"f:
,0l3li100€JOB XOR CHRPOU
!)f:
4:?4
13(11000000 XOR CHRPOU
<010000008 ~)R CHRPOL)
41'5
r'8
f'f:
(100090996 XOR CHRP(JL)
4:6
437
438 fETECT
All mnemonics copyrighted @ Intel Corporation 1976.
1·40
intJ
Ap·40
ISI5-1i HCS-48.!UF'I-41 IW:~'O ~<:~,Et4BLE~, V2 Q
PAGE
AP40' INTEL I'ICS-48 l'fYBOIlPM\ISPLfI\I APPLICATION NOTE APPENtoIX
LOC OB)
SEt)
SOIJRCE STATEHENT
0(160 D5
m ,Hm
44q INlT
O~q BF08
006;: B:322
442
0065 BOFF
J4}
441
'313,,7
B~21
4~4
0069
BO~t0
4d 5
44t
447
448
(t06B 23Ht
3fl
9(t6E C5
006F 149E
,*161)
(tIm A5
0072 2,F(t
00?4 62
(1075 ~5
0Et76 25
12
INITlilL 12E5 PF.CiCE5S0.' REGiSTERS
SEL
RBi
~IOV
CI.IRD1G,ICHAPNO
i10V
PNTR~qWB[ oBUF
t,to'.!
@F'tm:o, 1I0FF H
1'10','
F'NTF:e, IltEYLOC
i'lO'!
@p~m.B,
t1CIV
'.I IJTL
ft, UNPI1SK
"INPUT. R
SEl
RBO
449
CALL
450
451
452
451
CL~
~10\1
CLEAA
fl
R., niCK
1. A
STF.'l
T
Ell
Term
r~ov
454
455 '
10
,SET BWIRECT IONAL INPUl LINES
,OTlLIT'r' FO", SETTING INITIAl.. DISPLAY REGISTERS.
; LOAD INTEFRIJPT RATE VALUE
; ENABLE lIMER INTERRUPTS
456 ;
457
458
459
46\1
461
,**~.* <*I *.•*~** .~*." ~*"'*.foH****"'***.fo**"***"'*******************
:
; ECHO
'
;
cllm.
FOF.' AN\' NEW KI::YSTROKES DETECTED
TRANSLATE EACH KEYSTROKE INTO ft SEGMENT PATTERN
HN[.' WPlTE IT INTO THE APPI"OPRIATE DISPLA'r' REGISTER
46} . .u t ~ ~ ..***~**-t.***'*~·******H********·~*********""'**.'.*"'*.*
4';4 ;
*
0077 148:;
"'*
007D 14DB
007F 0477
469
470
471
CALL
KBD IN
.' GE.T NEXT KE~'5TROKE
.JB5
F~E~'
'JUMP IF rEI' IN RIGHTHANI) COLUMN.
SINCE THE ACG IS USE~ !:ill ENrACe AND RENTR~', ns CONTENT 5 MUST
BE PROCESSED OR SAVEv E:EFORE ENCAGC 15 CflLLED
CALL
ENeAce
,FORt'1 APPROPRlftTE SEGMENT PATTERN
CALL
RENTP't'
: WIi (~'ATHER THAN ITS POSITION IN SWITCH MATRIX) IS
.lS9 .
FHiJRNED Ttl lHE AGCUt1IJLAlGF.' .
11011
PNT!?!' lWBDBl.f
~90 KBDIN
494
flDC,
f1 . lIBftli
'1. 1!F'NTR1
KBDIN
fl.. lIlEGNDS
I'{,
~95
110VP
A.I~A
008D ·9]
496
RET
491
111),.1
. 0987 21
@tl88 .28:
4~'"
;-·:CfI
4"'~
.JE·~
008A €G8E
ewe
; KBDSUF WILL BE MARKED AS CLEAR
,LOAe BUFFER
~ALUE
,ADD BASE OF KEY ENCODING TABLE
: OBTAIN BYTE REPRESENTING KEY SIGNIFIUlNCE
437 .
4?a ;
49, : WiNDS IS THE BflSE FOR TABLE SHOWING !:.E',' MATRIX SIGNIFICANCE
5€1A .
FOP THE V.El'BOA~·D lISED IN THE f'ROTOTT'PE.
501:
IT~ LA't'OIJT 15 AS SHOWN TO THE RIGHT.
50~
501
!~OTE
~;04
~05
5(i€;
TIiAT BIT ti-B!T4 MAY BE USED TO ENCODE KEY TYPE. IN THIS CASE:
BI14 INDICATES REGULAR DECIMAL DIGITS,
lIlT5 :NulCA7ES RIGHT-COLUI1N FUNCTION KE'iS,
8m INfoiCATES PUNCTUATION HARKS ( * AND I ),
507
t1138E
B08E 4F
0Q8F 11?
'13€19tl 4E
~€1~1
01392
28
17
0139:': 18
~B94 19
OO~5 24
f.l0~6
14
~B97 15
0€198 16
tt099 22
fitl9A 11
~09B 12
£1139( :1.3
01cl9D 21
508 LEGNDS
.$ AND eFFH\
5139
5113
4FH
Hlli
4EH
2SH
17Ii
1SH
19H
24H
14H
511
512
51:;
514
515
516
517
518
15H
519
5213
521
[is
22H
[.f;
522
vB
llH
12H
5~'~
DB
DB
~;24
.' USE LOW ORDER BITS .AS TABLE INDEX
PL>IGIT4==}
1
f'DIGlT5==)
4
PDIGIT6==)
7
8
PDIG\T7=)
.f
9
16H
2
(3)
•
(4)
II
V
Y
V
PINP1JT7 f'INPIJT6 PINPUT5 PlNPIJT4
EH
21H
525 $LTECi
All mnemonics copyrighted © Intel Corporation 1976.
1-42
AP·40
ISIS-II I1CS-48 J UPH1 ~IH(FO flSSEMBLER, 112. iii
AN0 INTEL ~ICS-4S r:E'T'BOft~:[);DISPLAY HPPllUHlON NOTE
LOC Of.J
PAGE
14
RPPEN[JI:~
SOIJRCE SlATEfiENT
c .... '7
.•
'~;
f.it!9E 2:'131;1
013140 B938
@13142 BF(tS
OOft4 A1
~1(IA5 19
B0A6 EFfl4
00A8 BF€t8
€tORFi 8:;
BORS F8
~OFIC A3
00AD C6B4
fJ0AF 14D9
00Bl 18
0@B2 fJ4AB
0€184 83
52B ;CUfiR WRITES 'BLANr:' CHARACTERS INTO ALL DISPLAY REGI5TEI79
5ee
581
582
583
584
585
586
MOvi>
4F
66
6D
7D
97
7F
587
61'
OOCA 77
593
geCB 7C
OO(,C 39
oocr. 5E
99CE 79
OOCF 71
588
589
590
591
592
1l,IOOPIHS
ft, @R
~'H
,C'Gf'ATS IS THE ~ASE FOR THE TABLE OF SEGMENT PATTERNS FOR THE BASIC
. DIGITS HERE '!HE FULL HEX SET (0-Fi IS lIlCLUDED.
; F& MANY USE", f;Pt'L1CATIOIIS, THE CHARflCTl£.' SET MAY BE AMEIIDED OR AUGJ1E,.TED
,TO !NCLlJDE AOOlTlOtIAL SPEClft PURPOSE PATTEPNS.
; FORMAT IS
PUFEDCBA
IN STAIIDARD SEVEN-SEGMENT ENCOOHIG CONVENTION
;
WHE~'E P ",EPRESENT~ THE DECIMAL POINT
DGPATS EQIJ
J AND flFf'H
DB
00111111B XOR 5EIJPOL
DB
000001108 '3!91:l1113B :~OR SEGPOL
011:1.1001B ;:OR SEGPOL
01110001B XOR SEGPOL
601 ; ********i:,f<:lo*1o:l<+..***i<**+************************************
602 ;
603 ;!{llSP WP.!TES BIT PATTERN NOW IN ACe INTO NEXT CHARACTEI? POSITION
604 ;
OF THE DISPLAY (NEf.TPLI.. ADJUSTS NEXTPL POINTEr? VALUE.
605 ;
IJ0D0 A9
OOD1 FF
OOD2
e:m
. OOD4 29
eros Ai
00D6 EFDA
8!ID8 BF98
OODA 83
IIESlllS IN DISPLAY BEING FILLED LEFT TO RIGHT. THEN RESTARTING
606 WDISP' 110...
60,
HOY
ROO
698
XCH
699
PNTRl, A
A, NEXTPL
A, IISEGMAP
A, PHTR!
610
MOil
~lR1.A
611
DJN~
NEXTPL/ WISP1
NEXTPL, .CHARNO
1'1(1\1
612
6B WDISPl RET
614 .:
615 $EJECT
All mnemonics copyrighted @ Intel Corporation 1976.
1-44
inter
AP·40
ISIS-II I'lCS-4S,'I.IFH! l'lAC:~1) AS5EHBlE~', V2. II
PAGE
Af'40 INTEL M(:5-43 I;E'r'BOAliD/DI5PLAY Af'PlICATION NOTE APPENDIX
LOC OB.T
5I)IJRCf
SEQ
16
STATE~1ENT
"'*..
616 ,*~~*~**~",****~*~' "'* ~***",.~>t-***'" ••.t***t**.t<*************>t-**",
617 '
61~ RErITR'r' SIJBROOTIlJE TO ENTER ACC CONTENTS INTO THE RWHTHOST uIGIT
619 .
qt.jD SHIFT EYE[(YTHING ELSE ONE PLftCE TO THE LEFT
629 ~'ENTj;"I' '10','
f'lITR1, JSEGI1AP+1
00DB B938
OO[l[l BFEtS
621
MOV
NE'~TPL.
a0DF 2i
622 RENm
:~tH
A. I!PtlTPl
e~a
62:
iii':
624
D.1HZ
62'5
MOV
RET
P'lTII1
NElITf'L .IIENTR1
NEnFL, ICHARNO ; POINT TO LEFTI'10Sr CHARftCTER
19
00E1 EFDF
00E3 BF9S
fJ0E5 83
f..26
627 '
ICHARNO
628 ; ~t l<.U "'.",fIB••'" •t"'***1"'''' .*~u ~~ io.H**",*'.*******,.",*********>t-•.t<
6~~ ;
630 ,f,'UPtIDD TOGGLE uEC!MAL poI'lT HI LAST CHAPACTER DISPLAY CHARACTER
6}1 • [)PR[l[l TOGGLES [>EC!l'IfIl. POINT IN THE CHARACTER POINTED TO ElY THE ACe
6::2 .
6?5 PDPAUD I'lIJ\'
634 UPA[l[" ADD
MOil
6J5
M!jV
6:;'"
ooE6 2391
00E8 0337
0aEf1 ft9
~J0EB F1
00EC D,81J
OOEE Ai
tll3EF ,n
:'l;oL
MO'l
637
638
6,9
640 .
,SET INDEX TO j;'IGHTllOST POSITION
; ACCESS DISPLA'r' REGISTER FOR [)£SI~ED PLACE
fl.i91H
A, iSEIjMAP
PNTR1, "I
tI,!!/'NTR1
11,IS0H
@PNTR1,1i
RE~
••••**.j<**********.**.*******.**"**
00ff3
641 . '*·H~. '~*."***************
•. 42 .
64~ ; HOl[l
SlJSl(OUTlNE CALLED WHEN KEY IS KNOWN TO BE DOWN.
644 ;
WilL NOT I1ETURN UNTIL KEl' IS RELEASED.
64S HOLD' SEL
R~t
f10li
FI, LASTK'r'
; {LASTKY)=0FFH IFF NO KEYS DOWN
646
647
SEL
IIEIB
64B
CPL
A
649
IN<:
HOLD
[is
001'1 FE
OOF2 C5
OOF3 37
0~F4
96F13
RET
"~9
OOF6 83
6'51 .
652 ;
653.;
*'" ~***************"'*************.*****************.j:********
654 . DELAl' SIJBROiJTlNE HANGS iJP FOIl THE NiJMBER OF COHPLETE DISPLAY SCANS EQUAL
655 ;
TO THE CONTENTS OF THE ACr:oHllATO~ WHEN CALLED.
656 DELAY' HOV
PNTR1, IRDELfll'
00F7 8923
657
1'1011
658 DELAY1. 110\1
659
JNZ
€.r50
IlET
00f9 At
90FA F1
OOFB 96FA
0ltFD 83
@PNTR1. fl
fl. @PNTlll
(lfLA'r'l
661 tEJECT
All mnemonics copyrighted
@
Intel Corporation 1976.
1-45
Ap·40
1515-II MC!'-481lIPl-41 Mi'lCRO "SSEMBlEI"· V2 f.i
PAGE
AP40. INTEL I'1CS-41'i I:EYBOAIMDI5PLflY APPLICATION tl01E APPEtlHX
LOC OBI
0100
17
SOURCE STATEMENT
5E(1
662 O~'1j
661 .
l00H
6£,4 . l·t~·''f<*.*~*·~H*~**t~**~.**t***'t*'f<*.t*~*****'"*,******'''********
665 ;'
666 ; TilE CODE ON THIS PAGE IS FOP. [;EMONSTFATlON PURPOSES ONLY667 . I T~UEL Y DOUBT iJHE THH Rl'N END IJSEPS HOIJLD LI KE TO SEE A NAtlE
66S ,POPPING 1.If· ON TIiEll" CAU).lLATOP SCl1EENS
6~9 .; HOWEvER. TIiE CODE SIl(~lN HEj;l DOES INDICATE HOW THE UTILITY SUBROIJTINES
';713 ; ItIfU.lDE[· IiEPE C(IIJLfo E:E FtCCESSED
67i . THE Io'OIJTItIES T'lEMSELI,IES ftF.:E CALLED WHEN ONE OF THE FOUR BUTTONS
Eo;'2 . 01/ Of H~ ~ IGIiT -Hfl"I£; 5I[IE OF THE PPOl (in'PE KEVBORI'D IS PFESSE(),
6(":
I
•. 74 ; *~ H·****.H:t **tt .***..t*··~ .****·*********t~.'t<"'* u"'.*'" ** ***.***'"
0100 1212
81iJ2 320E
0104 528A
010614H
fJ108 04,7
675
676
677
678
679
6813
681
682
683
684
WIA 342E
010e 9477
685
f,86
'
.•UN':TN PO'JTlNE TO 1I1PlEI'lENT OllE 0'" "'OUR DEi'll) UTILI TIES, ACCORDING
•
TO W~I(:H OF 'l'HE FOLl" FI.~f(TION KE~'S WAS P~E55EI)
FIJNCfN:JB0.
FIJNCTl
.)81
. FIJNCT2
FIJNen
.
JB2
'
FUIlCR (ALL
RDPADD
ECHO
JI>1P
.
FUNCB CHLL
TES13
Jt1P
ECHO
687 ;
Etl8E 3424
911B 94;7
688 FIJNCT2: CALL
JI1P
68~
1E5T2
ECHO
690 ;
TESTl
691 FllNCT1' CALL
JI1P
ECHO
693 ;
694 ; **~****.****.********~******"'****.j<~t****~***********.*****'*
0112 3416
0114 0477
692
9116 BF98
695,
696; 1E511 CODE SEGMENT TO FILL DISPLAY PfGlS1EI02
703
1'11)\1
MOI/
CRLl
CALL
[)..TN2
/'101/
RET
PNTR0,IICHARNO; SET FOR EIGHT LOOP REPETI1 IONS
f\. NEXTPL
ENCRce
W[lISP
PNTR0, Tsm
NElI'TPL IICHARNO
705 •
786 SEJELT
All mnemonics copyrighted @ Intel Corporation 1976.
1-46
; COP~I NEXT DIGIT INTO DISPLAY REGISTERS
inter
Ap·40
ISIS-II I'1('S-48.'UP1-41 HAC~O ASSEMBLER. Y2. (I
PAGE
AP48: INTEL MG5-48 m'BOAAD/D ISF'LA'r' APPLICATION NOTE APPEl'll) I X
SEQ
LOC OSJ
SOURCE STATEMENT
737 ,**~*****,~'io**~**~*******.j<*********.f<************"'**",*********
70S·
7~9 : TE5T2 WRITES THE SEGMENT PATTERN FOR 'JOHN' ONTO THE DISPLA',I.
719 ;
IdfiITS FOR ~ WHILE, AIID THEN CLEAPS THE DISPLAY
711 TE5T2: HOII
PNTR0, i,JOHN
CALL
PPINT
712
MOV
A.1100 , SCAN DISPLAV FOR 19a CYCLES
713
;'14
GALL
DELAY
,JI1P
GLEAP
m
716 '
717 : ~*·ft *~*.t*~1'*·~*"'Y*~**~*~***~'*-~* *****************************
718 •
';'19 ,: lESE ~JJB~'OlJTINE TO -ILL DISPLfiY WIlH DASHES
72(1 ;
JI.IMf'5 INTO SUBROUTINE 'CLEAR'
721 '
I1S SOON AS 1HE KE,' IS RELEflSED.
722 TESE mv
fl. ~91ee00e0B :~OR 5EGPOI. ; PATTE~N FOR '-'
72:;
CALL
FILL
;'24
CALL
HOLf'
l25
JMP
CLEAR
72f ;
0124 B8B5
0126 HAB
0123 2364
012A 14F7
012C 049E
012E 2340
ano
18
HAB
BE214F0
0134049E
727 ,.' I< ~*,.*** .•*·*:t .j<****~****:j.*********************.j<**************
728 '
729 END
LlSER S'T'MBOlS
ASFIYE 0902
DEBNCE 0004
FILL !JeRe
INn 8960
HCOlS 0004
PNTR0 0000
I"EFPl eel?
S(;AN~
01.134
TE5T2 0124
BLAN¥.
liE LA','
Fm'
lHPMSK
HEGlOG
PNTR1
REFRSH
SCAtl5
TESE
ASSEMBL Y COI'1PLETE,
9000
00F?
131381
00FB
00FF
0001
CHARNO
DELAY1
FIJHCT1
JOHN
NE>:TPl
POSLOG
0008
0eFF!
13112
0005
0007
0000
0010
~ENTI?1 00DF
003F ' SCAN6 131345
012E
TICK
FFF0
CHRPOL
DGPATS
FIJII(;T2
V-BDBUF
NREPT5
PliiNT
RENT,,"Y
SCANS
mNT
0000
BOCa
lUBE
0022
002'"
9BAB
130LlB
004F
0007
NO ERRORS
All mnemonics copyrighted © Intel Corporation 1976.
1-47
CHRS1B
DPADD
FUNCB
KBDIN
HROWS
PRNTi
ROTeNT
SCAN9
T1RET
0057
00E8
€110ft
a083
9004
0084
0005
0057
fJOOE
ClEAP.
ECHO
FLINCH
KEYlOC
NXTLOC
PSGl'INT
ROTPAT
SEGl'IAP
TST11
099E
mm
0106
0921
0023
0008
00134
0037
911A
ClRl
ENCAce
FUNC1N
LASTKY
PIHGlT
RDELAY
SCAN
SEGPOl
WISP
9BA4
BBBA
9100
0806
0919
0023
00lE
0000
001)0
CURDIG
ENCMSK
HOlD
LEGHOS
PII/PUT
8007
800F
OOFC
008E
9009
R()f'fl()D 119E6
SCAN1 0021
TEST1 9116
WDlSPl OODA
intJ
AP·40
1515-II RsSEf1BlE~ S'r'1tBOl. (:~s REFEm/CE, ..,2 8
ASA\IE
BlAtl<
292.
179.
CHARNO In.
CHFPOL 169.
CHRSTB 282
CLEAI1 449
5:'>4l1
CIJRDIG 286.
DEaNeE 178.
[)flAY 656.
[.oELR'.'l 658.
[IGPAiS· 574
CL~l
DPflOC'
ECHO
ENCAce
ENC/'ISK
FILL
FKEY
HOLD
532.
723
4731
6911
6881
68511
466
679
688
682.
47:.>
645.
465
2m
205.
494
175.
1671
2121
174.
329.
158.
1681
1911
549
1921
POSLOO 1661
~NTl
PSGtlNT
I1DELA'r'
RDPAOO
REFill
REFRSH
RElITRl
REIfTR'r'
441
431
715
725
289
683
405
5n
432
537
433
395
485
441
686
689
692
612
434
621
435
625
436
697
698
783
5491
551
15911
2161
633.
2821
268
622.
470
700
573
678#
649
448.
724
446
711
386
499.
300
359
508.
328
1m 533
623
PRINT
430
714
659
5831
471
573J
562.
JOHN
KBDBlJF 214.
PNTR1
269
531
:m
465.
469
lSs'
236
INIT
INPHSK 171.
KBDUI
KE'r'LOC
LRSTKV
LEONeIS
NCOL5
NEGLOG
NEXTPL
NFEPTS
NFOWS
NXTLOC
PDIGIT
PINPUT
PNTRIl
1
534.
FUNCl1 678
PJNCT2
FIJNCT3
FIJNCT4
FIJNenl
249
288
228
429
4281
5311
536
283
PAGE
442
493
389
368
499
444
365
486
646
536
537
697
611
612
621
624
625
697
699
783
361
379
711
418
656
388
383
386
367
389
399
486
442
443
444
445
421
657
499
658
492
532
534
535
696
689
619
628
622
361
392
285
381
309
554
299
635
169
555
5561
281
417
682
447
356
698
291
636
170
712
m
417
636
292
656
288.
624
620.
All mnemonics copyrighted © Intel Corporation 1976.
1·48
inter
Ap·40
ISIS-I I ASSEHBLER SYMBOL CROSS
2l'!411
328
R01Pfli 293.
StfiN
300.
:;30
392
391
380.
371
]131
~OTCNT
SCAN1
SCANs
SCANS
SCAN6
SCANS
SCftN9
SEGflAP
5E~OL
rEST1
TEST2
TESE
TICK
328.
362
331
395.
497
395
220.
17911
593
691
688
685
177.
T!lHT
TlRET
T5TH
W['lSf'
WDISP1
269.
699.
552
611
CROSS
REFE~ENCE
409.
419
REFE~ENCE.
384
389.
629
564
597
V2 fJ
PfiGE
423.
2&8
m
280
594
697.
m
698
563
595
596
634
565
598
566
599
584
722
7111
722.
250
451
248'
792
606.
2
,(11
6131
COMI'Lf.TE
All mnemonics copyrighted @ Intel Corporation 1976.
1-49
585
586
587
588
589
590
591
!l92
--
inter
APPLICATION
NOTE
Ap·49
January 1979
9800904
© Intel Corporation 1979
1-50'
AP·49
INTRODUCTION
however, is more economic than technical; these same
peripheral chips which are such a bargain when coupled
to a microprocessor such as the MCS-85 or 86, have a
significant cost impact on a single chip microcomputer
based system. The high speed of the 8049, however,
makes it feasible to implement a serial link under software control with no hardware requirements beyond two
of the I/O pins already resident on the microcomputer.
The Intel'" MCS-48 family of microcomputers marked
the first time an eight bit computer with program
storage, data storage, and I/O facilities was available on
a single LSI chip. The performance of the initial
processors in the family (the 8748 and the 8048) has
been shown to.meet or exceed the requirements of most
current applications of microcomputers. A new member
of the family, however, has been recently introduced
which promises to allow the use of the single chip
microcomputer in many application areas which have
previously required a multlchip solution. The Intel'" 8049 virtually doubles ·processing power available
to the systems designer. Program storage has been increased from 1K bytes to :ilK. bytes, data storage has
been increased from 64 bytes to 128 bytes, and processing speed has been increased by over 80%. (The 2.5
microsecond instruction cycle of the first members of
the family has been reduced to 1.36 microseconds.)
There are many techniques for implementing serial I/O
under software control. The application note "Application Techniques for the MCS-48 Family" describes
several alternatives suitable for half duplex operation.
Full duplex operation is more difficult, however, since it
requires the receive and transmit processes to operate
concurrently. This difficulty is made more severe if it is
necessary for some other process to also operate while
serial communication is occurring. Scanning a keyboard
and display, for example, is a common operation of
single chip microcomputer based system which might
have to occur concurrently with the serial receive/transmit process. The next section will describe an algorithm
which implements full duplex serial communication to
occur concurrently with other tasks. The deSign goal
was to allow 2400 baud, full duplex, serial communication while utilizing no more than 50% of the available
processing power of the high speed 8049 microcomputer.
The format used for most asynchronous communication,
is shown in Figure 1. It consists of eight data bits with a
leading 'START' bit and one or more trailing 'STOP' bits.
The START bit is used to establish synchronization between the receiver and transmitter. The STOP bits ensure that the receiver will be ready to synchronize itself
when the next start bit occurs. Two stop bits are normally used for 110 baud communication and one stop
bit for higher rates.
It is obvious that this Increase in performance Is going
to result in far more ambitious programs being written
for execution in a Single chip microcomputer. This article will show how several program modules can be
designed using the 804g. These modules were chosen
to illustrate the capability of the 8049 In frequently encountered design situations. The modules included are
full duplex sarialllO, binary multiply and divide routines,
binary to BCD conversions, and BCD to binary conversion. It should be noted that since the 8049 is totally
software compatible with the 8748 and 8048 these
routines will also be useful directly on these processors. In addition the algorithms for these programs
are expressed in a program design language format
which should allow them to be easily understood and
extended to suit individual applications with minimal
problems.
FULL DUPLEX SERIAL
COMMUNICATIONS
I
Serial communications have always been an important
facet in the application of microprocessors. Although
this has been partially due to the necessity of connecting a terminal to the microprocessor based system
for program generation and debug, the main impetus
has been the simple fact that a large share of microprocessors find their way into end products (such as inteliigent terminals) which themselves depend on serial
communication. When it is necessary to add a serial link
to a microprocessor such as the Intel'" MCS-85 or 86 the
solution is easy; the Intel'" 8251A USART or 8273 SOLC
chip can easily be added to provide the necessary protocol. When It is necessary to do the same thing to a
single chip microcomputer, however, the situation
becomes more difficult.
BIT
01
02
03
04
05
06
07
08
BIT
Figure 1.
The algorithm used for reception of the serial data is
shown in Figure 2. It uses the on board timer of the 8049
to establish a sampling period of four times the desired
baud rates. For 2400 baud operation a crystal frequency
of 9.216 M Hz was chosen after the following calculation:
f = 480N(2400)(4)
where 480 is the factor by which the crystal frequency is divided within the processor
to get the basic interrupt rate
2400 is the desired baud rate
4 is the required number of samples per
bit time
N is the value loaded into the MCS-48
timer when it overflows
Some microcomputers, such as the Intel 8048 and 8049
have a complete bus interface built into them which
aliows the Simple connection of a USART to the processor chip. Most other Single chip microcomputers,
although lacking such a bus, can be connected to a
USART with various artificial hardware and software
constructs. The difficulty with using these chips,
00670A
STOP
START
1·51
AP·49
The value N was chosen to be two (resulting in f = 9.216
MHz) so that the operating frequency of the 8049 could
be as high as possible without exceeding the maximum
frequency specification of the 8049 (11 MHz).
I
STIRT IF RECEIVE ROOTII£
11 IF RECEIVE FlOO=e ll£N
;2
IF SERIAL Itf'IJT=SPfn ll£N
13
RECEIVE FlAG:=1
13
BYTE FINISI£)) FlAG:=8
12
OOIF
I 1 ELSE
SINCE RECEIVE FlAG=1 ll£N
:2
IF SVI«: FlOO=e TI£N
;3
IF SERIAL 11f'UT=SPfn ll£N
14
SVI«: FI.J1G:=1
;4
DATA: =88H
;4
SffIPLE CNTR:=4
;3
;4
ELSE
SINCE SERIAL 1If'UT=ItfRK l"1£N
RECEIVE FlOO:=8
;3
OOIF
; 2 ELSE
SINCE SVI«: FLAG=1 ll£N
SRlf>LE ro.M£II: =SRIf>LE CtlWTER-1
;3
;3
IF SRlf>LE ro.M£II=8 ll£N
SRlf>LE COUNTER: =4
:4
;4
IF BYTE FINISIED FlOO=e ll£N
;5
CARRY: =SERIAL IIf'UT
;5
SHIFT DATA RIGHT WITH CARRY
:5
IF CAR!1Y=1 ll£N
:6
(J(DfITA: =DATA
:6
IF DATA REf¥)\' FlOO=e THEN
;7
ME FINISI£)) FLAG=1
16
ELSE
;7
BYTE FINISNED FLAG:=1
;7
OYEl/Rlll FlAG: =1
;6
OOIF
15
OOIF
14
ELSE
slta ME FINISNED FlAG=1 ll£N
15
IF SERIAL 1If'UT=IIfIRK ll£N
,6
DATA REf¥)\' FlAG: =1
;5
ELS!:
SINCE SERIAL IIf'UT=SPACE TI£N
;6
ERROR FlAG: =1
15
OOIF
15
RECEIVE FLRG:=8
:5
SYNC FlAG: =8
;4
OOIF
:3
ENOIF
12
ENOIF
; 1 ENOIF
Once the meaning of these flags are understood the
operation of the algorithm should be clear. The Rece/lfe
Flag is set whenever the program is hi the process of
receiving a character. The Synch Flag is set when the
center of the start bit has been checked and found to be
a SPACE (if a MARK is detected at this point the receiver
process has been triggered by a noise pulse so the program clear!. the Receilfe Flag and returns to the idle
state). When the program detects synchronization it
loads the variable DATA with 80H and starts sampling
the serial line every four counts. As the data is received
it is right shifted into variable DATA; after eight bits
have been received the initial one set into DATA will
result in a carry out and the program knows that it has
received all eight bits. At this point it will transfer all
eight bits to the variable OKDATA and set the Byte
Finished Flag so that on the nextsample it will test for a
valid stop bit instead of shifting in data. If this test Is
successful the Data Ready Flag will be set to indicate
that the data is available to the main process. If the test
is unsuccessful the Error Flag will be set.
The transmit algorithm is shown in Figure 3. It is executed immediately following the receive process. It is a
simple prograr:n which divides the free running clock
down and transmits a bit every fourth clock. The variable
TICK COUNTER is used to do the division. The Transmitting Flag indicates when a character transmission is in
progress and is also used to determine when the START
bit should be sent. The TICK COUNTER is used to determine when to send the next bit (TICK COUNTER MODULO 4
0) and also when the STOP bits should be sent
(TICK COUNTER = 9 4). After the transmit routine completes any other timer baseq routines, such as a keyboard/dispJ'ay scanner or a real time clock, can be
executed.
=
; STfRT IF TRIIISIIIT ROOTII£
11
; 1 TIC!( CIXM'ER:=T1CK CIXM'ER+1
; 1 IF TICK ro.M£II IQ) 4=8 THEN
;2
IF TRIIISIIITIlt«l FlAG=1 ll£N
;3
IF TICK CWITEA=88 1818 88 BINfRY ll£N
;4
TRANSJ1IlTlt«l FlAG: =41
I3
ELSE
IF TICK CWITEA=88 1981 88 BINfRY THEN
;4
SEll> 00 IR!K
I oj
TRIIISIIITIlt«l FlAG: =8
I3
ELSE
SINCE TICK ClXM'EROTHE fIIOYE COUNT 'll£N
14
SEll> NEXT BIT
;3
OOIF
; 2 ELSE
SINCE TRANSJ11TT1t«l FlOO=e THEN
I3
IF TRIIISIIIT REIllEST FlAG-"1 THEN
;4
XIITBVT: =NXTBYT
;4
TRANSIIIT REUST FlAG: =8
;4
TRANSJ1ITTlt«l FlAG: =1
I 4
TICK COUNTER: =8
; oj
SEll> SYNC BIT (SPACE)
13
ENOIF
;2
ENOIF
;100IF
Figure 2
The timer interrupt service routine always loads the
timer with a constant value. In effect the timer Is used to
generate an independent time base of four times the reo
quired baud rate. This time base. is free running and is
never modified by either the receive or transmit programs, thus allowing both of them to use the same
timer. Routines which do other time dependent tasks
(such as scanning keyboards) can also be called periodically at some fixed multiple of this basic time unit.
The algorithm shown in Figure 2 uses this basic clock
plus a handful of flags to process the serial input data.
Figure 3
All mnemonics copyrighted CO Intel Corporation 1979.
1-52
inter
Ap·49
the 8049. Also included in Fig. 4 is a short routine which
was used to test the algorithm.
Figure 4 shows the complete receive and transmit pro·
grams as they are implemented in the instruction set of
ISIS-ll P1C5-48.'IJPH1 "AeF:) ASSEMBLER, Y2.
lOC OBJ
SEg
SOURCE
e
STATE~lEm
-l<
THIS f'ROORAtl TESTS THE FUlL l~JPLE;, COMMIJIHCATIOI-I :,UFTWARE
*
*
5 .; *****-t<**·t,..**tt*·H*-t<**$** .. **·~t**tt*·~*·~i4~·*-t"t********:t***-t<**·!:.f<:l>*******-t<**'i'****-t:*
6.
7 $INCLur'E( :F1.UPTEST PDl)
8 ;
9 ;
11) i
START OF '1 EST POUT! HE
====================
11.
12 .
13 '
14 ;
15 .
16 ,1 ERROR COLINT =8
G
18
19
20
21
91300
0000 C5
0001 2400
;1 REPEAT
;2
PATTERN Al
:2
lNHlALIZE TIMER
.2
CLEAFI FLAGB'm
,2
FLAG1 =t1AP.r.
22:2
REPEAT
23 ; 3
IF TRflNS~lIT REQUEST FLAG=9 THEN
24 ; 4
rmB'T'TE: =PATTERN
2~. ,4
rPAN5M n REQUEST FLAG=1
26 ; 7
ENDIF
27 : ~
IF DATA READ'" FLAG=1 THEN
28 ,4
PATTERN. =O¥l)ATA
29 ; 4
[*ITA FIEADI' FLAG =0
J0 ; 3
E"'[lJF
31. 2
UNTIL ERPOR FLAG OR OVERRUN FLAG
32 ; ~
mCPEMENT ERROR COUNT
n, 1 I),.,TIL FOREVEF!
34 . EOF
:>5 tEJECT
36
ORG
0
37 .1 SELECT REGISTER BAt,'K B
33
SEL
IiS9
:>9 ; 1 OOTO TEST
40
.IMP
TEST
41 $
INCLU(JE<.F1·UAIITI
42.
4:1 ,
44 ;
A5'ltlCHRONOU5 FIECEIIiE/TRANSMIT ROUlINE
45 ;
===================================
46 ;
THIS ROIJTINE RECEIVES SH:IflL COOE USING PIN TO AS R;,1)
47,
AND CONCIJRREtllLY TRANSMITS USING PIN P27
48;
NOTE.
49 ;
THIS ROUTINE USES FLAG 1 TO BUFFER THE TRANSMITTED
Figure 4
All mnemonics copyrighted © Intel Corporation 1979.
1-53
inter
LOC OSJ .
Ap·49
SEQ
SOURCE STRTEItENT
59 ; 1 [lATA LINE. THIS flIlHNflTE5 THE JITTER THAT
51 ,1 WIll.D BE CRUSEll BY YAFIATlOIIS IN THE RECEIVE
= 52 ,1 T1I'1ING. NO OTHER Pf,'1BA14 11AY USE FLfIf.i 1 WHILE
53 ,1 THE TIMEii' IrITERPUPT IS ENABLED
54 ;
55 ;
56;
'57 '
58,
59 .
60 i
61
PfGlSTEP. ASSIGllIft:.NTS-8Alt:l
=============__T~_==
i
0007
0006
= 62;
= 63 ATEMP EQIJ
= 64 FLGBYl EQU
9005
0004
0000
65
66
67 SAl4CTI1 EOU
= 68 TCKCTF EOU
=. 69 REGe Eoo
R7
116
f;'S,
114
R0
;
;
;
;
;
;
;
USED TO SAllE Af..ctJ'IULA' ~ CONtENTS WRiNG INTERRII'T
CONTAINS YfII;lOUS FLAGS 1.&0 10 COIITRQ.
f(£CEI'fi
AlID TAAIl5t11T Pf.:Qr.£SS. SEE CON5TANT DtflNITIOOS FOR
THE I1EfIIHNG OF EACH BIT
SAl'lf'LE CtlJlTEI1 F~ THE RECIEYE f'ROCES!:I
SAl'lf'LE CtlJNTEP FOIl THE TRANSI'IIT PROU:S!i
USEr, ~ POINTER Rl:G1STER
;
.'
,
;
I1EcmE RETlJINS Yf1L1D MTA IN THIS BYIE
RECEIIri ACctll1llATES DATA IN THIS BYTE
CONTAINS BYTE llElMjTRANSI1JlTED
COIlTAIt.'5 Tit: NEXT BVTE TO BE TRANSI1ITlED
'1£
70 ;
0029
0021
9022
9923
=
=
=
=
=
71 ;
Ii'A14 ASSIGltlENTS
72 ;
======:========
n;
74 I'IOt::DAT EQlJ
?S I'II)ftTA Eoo
76 IIXI1TBY EQlJ
77 ItI'..lTBY EOO
= 78 $EJECT
201i
21H
22H
23H
= 79 :
=
=
=
=
80;
81 ;
S2:
83 :
= 84 .;
0091
0002
Il904
0098
0019
0029
0049
0089
=
=
=
=
85;
86;
CONSTANTS
=======
THE FOLLOWING COOSTANTS ARE USED TO ACCESS THE FLAG BIlS CONTItINED
IN REGISTER FLGM
RCYFLG EQlJ
91H
SYNFLG EQIJ
92H
B't'FIfL EQlJ
94H
ctJu
08H
95 ERRFLG EOIJ
96
= 97 TRRQFL EQU
= 98
99
llJH
87
88
89
= 99
91
= 92
93
94
DRlWFL
= 199 .
= 191 TRNGFL EQU
= 102
= 19l OYRUN EOU
= 104
29H
40H
:
:
;
;
;
;
;
;
i
;
,
;
;
;
i
I
80H
;
;
5I:T WI£N START Bll IS FIIIST OETEm.D
RESET WHEN RECEIVE PROCESS IS COI1Pl.ETE
SET IoIHEN STAPT flIT 15 IIERIFIED
RESET WHEN RECEIVE PROCESS IS COI'IPLETE
RESET IlfEN STA.~T fjIT IS FIRST DETECTED
SET HN THE EIGHT !!ATA BIlS IfIYE fU BEEN kECEIVED
SHOULD BE RESET BY I'IfIIN PR~API WHEN DATA IS Att;EPTED
SET BY RECEIVE PROCESS WHEN STOP 8IHS) ARE VERIFIED
SHOULD BE RESET BV I1IIN I'ROORAPI WHEN SRIIPLEIJ
SET BY RECEIVE PIWI'.£SS IF A ~RAtlII«l Ekkill IS DETECTED
TESTED BY tIfliN PROCiRRI'I TO DETERftH£ I~ Rl:Ill>Y 10
TAANsI'IIT A rlEW BYTE-SET TO INDICATE 1HAT NXTBYT
HAS BEEN LOADED
I1ESET BY TRANSI1IT PROCESS IHN BYTE IS ACCEPTED
SET WHEN TRANSI!ISSION OF A BYTE STARTS
RESET WHEN STOP fjlT IS TRANSIItnED
SET BY RECEIVE PROCESS WHEN OYERUN OCCURRS
SHOULD BE RESET BY PlAIN PliOORAl'! IIIlN SAlRE:D
Figure 4 (continued)
All mnemonics copyrighted Intel Corporation 1979.
1·54
inter
AP·49
LOC 08.1
90S9
FF7F
9900
SEQ
= 105
= 106
= 107
= 198
= 199
= 119
= 111
= 112
= 113
= 114
SOIJRCE STATEMENT
i
;
;
GENERRL COrlSTANTS
=================
i
E(lU
MARK
SPACE EQlJ
STPBTS EQlJ
80H
USED TO GENEFATED A !'lARK
NOT OOH ; lISED TO GENERATE A SPACE
9
COtlTROLS lHE NUMBER OF SWP BITS
9 GENERRTI;S ONE STOP BII
1 GEUERATES TI.'O SlOP BITS
i
= 115 $EJECT
= 116 ;
0097
0997 160A
0009 93
eallA 1)5
0fI0Il AF
000c 23FE
000E 62
= If?
= 118
= 119
= 129
= 121
= 122
= 123
= 124
= 125
;
;
;
ORO
9911 9A7F
9013 0417
9015 BAS0
0017 FE
0018 1224
001F1 3664
00lC FE
9010 4301
00lF 53FB
0021 AE
8022 13464
0I:l07H
i1
ENTER I NTERRUPT MODE
JTF
UART
RETR
UART: SEL
RB1
= 126 ; 1 SAYE ACCUMl.lATOR CONTENTS
= 127
1'101'
ATEtlP, A
= 128 ; 1 RELOAD TIMER
TI SR .
= 129
= 130
= 131 ;
1'1011
A, ITIHCNl
MOIl
T,11
= 132
OUTPUT Txt> BUFFER (Fl) TO TXD 110 LINE (P27)
=================================
;
= 133.,
ooeF 7615
START OF RECEIVE/TRANSMIT INTERRUPT SERVICE ROUTINE
= 134 ;
= 135
= 136
= 137
= 138
= 139
= 140
= 141
JF1
OMARK
OSPACE' ANL
P2, tlSPACE
JI1P
RCYOO0
O~1ARf(
ORL
P2, IHARK
;
;
START OF RECE lYE ROUTINE
=================
;
= 142
i
= 143
= 144
= 145
= 146
= 147
= 148
= 149
= 150
= 151
= 152
= 153
= 154
; 1 IF RECEIVE FLAG=0 THEN
RCVOO0: ItOIi
A, FLGBYT
JB9
RCV~19
;2
IF SEFI AL IIlPUT=SPACE THEN
JTfl
XMIT
;3
RECEII/E FLAG:=!
MOV
A, FlGBYT
ORL
A. tlRCIIFLG
.' 3
BYTE FINISHED FLAG: =8
AIIL
A,
BYFNFL
;2
ENDIF
MOl!
FLGB'r'T. A
.,m
= iSS
= 156
= 157
= 158
= 159
JMP
XMIT
; 1 1:15£
SINCE RECEIVE FLAG=1 THEN
;2
IF SYNC FLAG=8 THEN
RCW310. JB1
RCV939
d
IF SEFIAL INPUT=SPACE 1HEN
Figure 4 (continued)
All mnemonics copyrighted © Intel Corporation 1979.
1·55
inter
Ap·49
Loe OSJ
0026 3633
S()I.P.CE STATEMENT
SEQ
JTe
= 160
= 161 ; 4
RCI/029
5YOC FLAG' =1
m.
802F 0094
:: 162
= 163
= 164 . 4
= 165
= 166
= 167 ; 4
= 168
00?1 0464
= 169
JMf'
ELSE
0028 4302
oo2A HE
0028 8821
002D B0S0
= 170 .:,
0033 53FE
0035 AI:
0036 0464
00313 ED64
903A 8004
003(' 5259
903E 97
903F
0041
0042
9044
2642
A7
BS21
Fe
0045 67
0046 AO.
0947 E664
SlKTIi', 14
~y
XI1 IT
SINCE SERIftL INPUT=I'1ARK THEN
k,[CEI~'E FLfI(i.=0
= 171; 4
. = 172 Ii'CI/029'
ANL
AdlNOT RCYFU;
ENOIF
1'101,'
FLGf:I'L A
= 17'5
JMf'
XI1lT
= 176; 2 ELSE
SINGE SYNC ~LAG=l THEN
= 177 .3
SAMPLE COlINTEIi' =SAf1PLE COUNTEP.-l
= 178 I1CI/030 DJNZ
SAt1CTR, >''1'1 IT
= 179 ,3
IF SP.llPLE (,OlINl Er;:=e frifN
= 189 ; 4
SAI'lPLE COUNTER: =4
SAI1CTR,14
HOV
= 181
= ~82 ;4
I F B~'TE FItll SHED FLAG=0 THEN
RCI/950
= 183
= 184
CLR
!.'\
= 185 ; 5
CARR'T" =SERlftL INP/Jl
JNTO
I?CI/040
= 186
CPL
C
= 187
R0, .HDATA
= 188 I1C\l940 I'IOV
= 173 ;].
= 174
m:;:
= IS9
= 199 ; 5
= 191
= 192
= 193 ; 5
PlOY
RRC
!'lOY
.INC
=194
= 195
!6
0049 BS29
9048 A0
=196
= 19(
1'I0V
004C FE
004D 7254
= 199
= 200
I'IOV·
JB3
=201.,
= 202
= 203
OK
904F 4304
9951 AE
0052 0464
A, lIS'ltflG
FLGBYT. R
DATR: =80H
MOl,'
Re, OOATA
PlOY
@R0 ••8011
SAI'IPLE CNTR' =4
19)'.,'
=1913 ,;6
= 2134
= 295 ;6
I'IOV
A,~Re
SHIFT DATA "'1(jBT WI1H CARR..'
A
@F0,A
IF CARRI'=1 THEil
;':MIT
(}KOATA . =DATO
110.II'1OKDAT
~RO, A
IF [lATA RElICI,'
1'I0V
1MP
= 209
= 210
=211
Bt'lE FINISHED FLRG=1
A,tBYFNFL
FLGBYT, A
xrm
ELSE
BYTE FINISHED FLfiG: =1
OVERRIJN FLAG, =1
; 1'1(1','
ORL
I'IOY
= 212 ; 6
=213.;5
0057 9464
= 214
JI1P
A, FLGBYT
A, «(Bl'FNFL OR Ol/RUN)
FLGBYT,A
ENDIF
ENDIF
XMIT
. Figura 4 (conllnued)
All mnemonics copyrighted © Intel Corporation 1979.
lHEf'
[lCV045
=296;1'
= 207 ; 7
= 298 RC1I045:
0054 4384
0056 AE
FLAG=~
A.. FLGBYT
1-56
inter
AP·49
LOG OBJ
0059 26SF
0058 4308
eosl) 0461
0961 53FC
0963 AE
SEQ
= 215
= 216
= 217
= 218
SOLIRCE STATEI'1ENT
;4
;5
elSE,
SINCE BYTE FINISHED FLAG=1 THEN
IF SERIAL IHPUT=MARK THEN
RCY!I50: JNT0
RCV060
DATA READ',' FLAU: =1
A;'DRD'T'FL
= 219
OPL
ReVEl70
= 229
.IMP
ELSE
SINCE SERIAL INPUT=5PACE THEN
=221;5
eRROR FLAG. =1
=222;6
A••ERRFLG
= 223 Rel/a60: ORL
ENDIF
= 224 ,;5
= 225 ; 5
RECEI','\: ~LAG. =9
= 226 ; 5
5'r'NC FLOO:=!!
= 227 ReVEl7e. AHL
A.llroT(SVNFLG OR Rel/FLG)
= 228
MOV
FLGB'n. A
= 229 ; 4
END IF
= 2~9 ;:?
ENDIF
= 231 ; 2 EIIDIF
= 232 ,1 ENDIF
= 2:£3 rEJECT
= 234 ;
= 235 ;
STAin OF TRANSM IT POUTI NE
;6
= 236 ;
= 237 ;
=======================::
= 238 ; 1
0064 1C
006S 2303
0867 SC
0068 9697
006A FE
006B 37
006C 0286
006E 2324
0070 ric
0071 96;'B
ean
A5
0074 8'5
= 239
; TRANSMITTER OUTPUT BIT IS P2-7
= 240 ; 1 TICK COUNTER. =TICK COUHTER+1
= 241 XMIT: INC
TCKCTR
= ~42 ;1 IF TICK (;QUNTER "00 4=0 THEN
= 243
tolOV
A, .03H
= 244
ANL
A. TCKCTR
= 245
JNZ
RETURN
= 246 ; 2
IF TRRNSI'1ITTING FLOO=l THEN
= 247
MOV
A. FLGB'r'T
= 248
CPL
A
= 249
JB6
XI'1T040
= 259
IF STPBTS EQ 1
= 251 ; 3
IF TICK COUNTER=09 1910 00 BINARY lHEN
= 252
"011
A••28H
; CONDITIONAL ASSEMBL I'
= 253
XRL
A. TCKCTk
= 254
.JNZ
XI'ITB19
= 255 ; 4
TRANSMlTIING FLAG: =0
= 256
MO\I
A. FLGBYT
= 257
AHL
A. tNOT TRNGfL
= 258
1'1011
FLGBYT. A
= 2'59
JMP
RETURN
= 269
ENDIF
= 261 ,3
ELSE
IF TICK COUNTER=OO 1001 00 BINARY THEN
= 262 Xl'fT910: MOY
A••24M
= 263
XRL
A. TCKCTR
= 264
1HZ
('I'IT020
= 265 ,4
SEND 00 MARK
= 266
CLR
F1
; SET FLAGl TO MARK
= 267
CPL
F1
= 268
IF STPBTS EQ 9
= 269 ; 4
TRANSMITTING FLAG:=0
Figure 4 (continued)
All mnemonics copyrighled
e Inlel Corporation 1979.
1-57
intJ
Ap·49
LOC OB'!
9075 FE
9076538F
8878 AE
8879 9497
SEQ
SOORCE STATEI'IENT
= 270'
= 271
= 272
007D F0
907E 67
907F All
!l080 AS
0881 E697
0883 B5
0084 9497
=2?3
= 274
~TURN
ENDIF
ELSE
sna
TICK COOO'ER C)THE ABOI/E COUNT THEN
CLR
F1
JtIC
CPL
RETURN ; GO TO
JMP
RETURN
8823
-= 284
= 285
-= 286
= 287
= 288
-= 289
-= 290
F0
-= 291
BS22
A0
0097 FF
0098 93
F1
ENDIF
ELSE
SIt«:E TRANSMITTING H.AG=0 THEN
;3
IF TR~IS11I! REQUEST FlAG=l THEN
X1'1T940: JB5
R E T U R N ' FLAG BYTE THERE
,4
XIITBYT :=NXTBVT
= 292
MOil
1'10\1
1'1011
R0, IIIIIXTBY
A, @RO
RIl.• I/'IXIITlW
-=
MOY
@RIl,A
m
-= 296
0094 BC00
; FLltO 1 Will BE USED TO BlfFER 00
Rm~N PO nIT IF TXD=SI'I1CE (9)
; ELSE COMPLEI1EIIT FlAG 1 TO A tlARK
;:1
;2
= 294 ; 4
= 295
0091 4340
8893 fIE
= 297
= 298
= 299
= 390
-= 391
= 392
= 393
= 394
= 305
,4
.
. TRAIlSI1IT REQl(ST FLAG: =0
I'IOY
A, FUlBYT
Ali.
A, fNOT TRRQFl
TI"ANSl'IITTIIIG FlA(;: =1
ORL
A,ITRtIGFl
I'l0\l. FlGBYT, A
,4
TI CK COUNTER' =0
TCKCTR,1I0
;4
SEN!) S~'NC BIT (SPftCE) .
Cll!
F1
; SET FLAG 1 TO CAUSE A SPACI:
;~
ENDIF
;2
ENDIF
=396 ; 1 ENDIF
= 307 I1ETURN:
-= 308 ; 1 RESTORE ACCut1I.lATOR
= 399
t1O\I .' .A, ATEI'If'
= 310
RETR
311 $EJECT
P'.oy
]12 ;
9190
FFFE
901E
00lD
OO1C
0007
0006
; CONDITIONAL ASSEI'IBlY
= 276 ,4
SEND NEXT BIT
= 277 00920: i'KlY . RIl,II'IXItTBY
= 278
i'KlY .
A,fRO
= 279
~RC
A
@RIl,A
= 280
MOIl
= 281
= 282
= 283
00S6 8297
0988
008R
008B
. 9900
JI'I'
Ali.
= 275 ;3
8878 8822
I10V
A, FLGB'r'T
A, IINlT TRNGFL
FlGB'r'T, A .
f'tOY
3B;
START OF TEST ROUTINE
314 ;
315 '
316
m T1MCNT
318 HFLGBY
319 115A11CT
=============
320
321
322
323
324
ORG
EQIJ
EOO
EQIJ
"TCKCT EQIJ
;
ERRCNT EQU
PAn
EQU
;
019011
:-2
lEH
100
lCH
R7
R6
Figure 4 (continued)
All mnemonics copyrighted <0 Intel Corporation 1979.
1·58
Ap·49
LOt OBJ
9199 BFOO
91!12 BEOO
9194 23FE
01% 62
9107 55
9100 25
9199 881E
9UIB
aeee
8190 A5
911lE 85
81eF 881E
8111 Fe
9112 8224
0114 B923
9116 FE
8117 Al
SfJJRCE STATEI1ENT
SEQ
325
326
327
328
329
;
;
,; 1 ERR~ COONT: =9
TEST: I10Y
ERRCNT, III
; 1 REPEAT
339 TLOP
331 ; 2
PATTERN: =9
332
I10Y
PAn, .90
333 ; 2
INITIALIZE T!IIER
334
MO\I
A, ITlIDT
335
f1O\I
T, A
336
5TRT
T
:m
EN
TCNT!
:na .: 2 CLEAR FLAGBYTE
339
f'IOI,'
1/0, .HFLGBY
349
341 ,,2
242
343
I'IOV
~e,
III
FLAG1=MARK
CLF.'
F1
CPL
Fl
REPEAT
344 .: 2
345 TILOf':
346 ;3
IF TRAHSI1IT REQUEST FLAG--9 THEN
110\1
R8, WLGBY
347
f1O\I
ft @118
348
349
J85
TREC
350 ;4
NXTBYTE : =PATTERN
351
352
353
354.:4
355
356
357
358
359
360
HOY
I'lO\l
MO\l
Rl, II'tNXTBY
A,PAn
0128 8920
@R1.A
TRANSI1 IT REQUEST FLAG=l
DIS
TCNT!; LOCK OUT TIPlER INTERRUPT
; SO THAT MUTUAL EXCLUSION IS I'IAINTftINC.D WHILE
.: 'IHE FLAG B\'TE IS BEING MODIFIED
I'IOY
R,@R!j
ORL
A, tTRRQFL
@R!j,A
MOil
361
EN
TCNT!
TES1A
362
JTF
JriP
TREC
363
364 TESTA: CALL
IJART
.: CALL IJART BECAUSE TIMER OVERFLOWED Dl.JRIN(j LOCKOUl
365 ;3
ENDIF
366 ;3
IF DATA READ.,. FLAG=l THEN
367 TREC:
HOY
A,@R0
368
369
CPL
A
370
JBJ
TRECE
371 .:4
PATTERN: =OKDATA
J1O\I
R1, lMOKDAT
372
912A Fl
373
374
MOY
I'IOY
A,@Rl
912B AE
9118 35
0119 Fe
911A 4329
el1C A9
811D 25
011El622
(1120 2424
0122 149A
9124 F9
9125 37
9126 7238
812C 35
012D Fe
375 ;4
376
377
378
PATT, A
DATA READY FLAG: =II
DIS
TCNT!.: LOCK OUT TIMER INTERRUPT
; so THAT ItJTlR. EXCLUSION 15 MAINTIANED WHILE
; THE FLAG B't'TE IS BEING I'IOOIFIED
379
MOY
Figura 4 (continued)
All mnemonics copyrighted Intel Corporation 1979,
1-59
AP"49
LOC OOJ
~
SEQ
912E 53F7
All.
0139 A9
I'IO't'
EN
9131 25
9132 1636
flB42438
9B6 149A
383
JTF
384
JMP
CRlL
385 TESTS:
J86 TRECE:
3117 ;]
388 ; 2
A, lOOT DRDYFl
@F1l.II
TeNT!
TESTB
TRECE '
UAIIT
; CALL UART IF T!MER OVERFLOWED DURING LOCKOllT
ENDIF
UNTIL ERROR FLAG OR OVERRUN FLRG
389
390
391
392 ; 2
/'10'.'
R,@R9
RNl
A.I(O't'RUN OR ERRFLG)
J2
llLOP
INCREMENT EIIROR COUNT
:m
INC
E~CNT
394 i 1 UNTIL FOREVER
913S F9
9139 5:>'99
913B C69F
0131) 1F
913E 2402
USER S'r'/'IBOlS
ATEI1/' 9997
If'LGBY 991E'
OVRUN 00S0
P.C\1050 9059
STPBTS 0099
TJ5R 9997
iiMTB11j fl06E
SlRTEl'ENT
395
Jt4P
396 iEOF
397
END
BI'Flfl
I1NXTBY
PATT
RC\1960
SVNFLG
TLOP
iiI'IT020
A55EMBlV COI1l'lETE,
0094
9023
0096
OO'5F
0002
0192
9978
JlOP
DRDI'FL
HOKDRT
RCI/900
RCV070
TCKCTR
TREC
XKT940
0098
9020
0017
0061
0004
9124
ERRCHT 0007
/'ISAI1CT 0011>
kl.'V010 9924
RCVFLG 0001
TEST 9100
TRECE91J8
ERRFLG
MTCKCT
RCY020
REG0
TESTA
TRNGfl
0010
091(;
0033
9899
9122
994IJ
FLGBI'T 901j6
HXI'ITB't' 9rra
RCY030 .9038
RETURN 999i'
lESTB 1j136
TRRIlFL 0020
MARK
OJ1ARK
RCY040
SAMCTk
llLOP
UART
0000
r1()RTA 9921
0015
OSPACE 9911
9942
kCII945
SPACE
1I11CNT
Xl'll)
0005
0191'
99IjA
0954
FF7F
mE
0064
0086
NO ERRORS
Figure 4 (continued)
All mnemonics copyrighted © Intel Corporation 1979.
MULTIPLY ALGORITHMS
Most microcomputer programmers have at one time or
another I'mplemented a multiply routine as part of a
larger program. The usual procedure is to find an algorithm that works and modify it to work on the machine
being used. There is nothing wrong with this approach.
If engineers felt that they had to reinvent the wheel
every time a new design is undertaken, that's probably
what most of us would be doing-designing wheels. If
the efficiency of the multiply algorithm, either in terms
+
of code size or execution time is Important, however, it
is necessary to be reasonably familiar with the multiplication process so that appropriate optimizations for the
machine being used can be made.
To understand how multiplication operates in the binary
number system, consider the multiplication of two four
bit operands A and B. The "ones and zeros" in A and B
represent the coefficients of two polynomials. The
operation A x B can be represented as the following
multiplication of polynomials:
BOA3*~
B1A3*24 + B1A2*~.
+ B2A2*24 + B2A1*23 +
B3A 1*~ + B3AO*23'
+
+
+ B3A3*26
+
B2A3*25
B3A2*25 +
1·60
BOA2"22
B1A 1*22 +
B2AO*22
+
+
+
BOA1"2 1
B1AO*2'
+
BOAO"2°
AP·49
The sum of all these terms represents the product of A
and B. The simplest multiply algorithm factors the
above terms as follows:
A * B = BO*(A)*20 + B1 *(A)*21 + B2*(A)*22 + B3*(A)*2 3
Since the coefficients of B (Le., BO, B1, B2, and B3) can
only take on the binary values of 1 or 0, the sum of the
products can be formed by a series of simple adds and
multiplications by two. The simplest implementation of
this would be:
MULTIPLY:
PRODUCT = 0
IF BO= 1 THEN
IF B1 = 1 THEN
IF B2= 1 THEN
IF B3 = 1 THEN
END MULTIPLY
PRODUCT: = PRODUCT + A
PRODUCT: = PRODUCT + 2* A
PRODUCT:=PRODUCT+4*A
PRODUCT: = PRODUCT + 8* A
In order to conserve memory, the above straight line
code is normally converted to the following loop:
MULTIPLY:
PRODUCT:=O
COUNT:=4
REPEAT
IF B[O] = 1 THEN PRODUCT: = PRODUCT + A ENDIF
A:=2*A
B:= B/2
COUNT: = COUNT-1
UNTIL COUNT:= 0
END MULTIPLY
The repeated multiplication of A by two (which can be
performed by a simple left shift) forms the terms 2* A,
4 * A, and 8* A .. The variable B is divided by two (performed by a simple right shift) so that the least significant bit can always be used to determine whether the
addition should be executed during each pass through
the loop. It is from these shifting and addition opera-
ISIS- II
~IC5-48/UPI-41
lOC 08.J
tions that the "shift and add" algorithm takes Its com·
mon name.
The "shift and add" algorithm shown above has two
areas where efficiency will be lost if implemented in the
manner shown. The first problem is that the addition to
the partial product is double precision relative to the
two operands. The other problem, which is also related
to double precision operations, is that the A operand is
double precision and that it must be left shifted and
then the B operand must be right shifted. An examina·
tion of the "longhand" polynomial multir Ication will
reveal that, although the partial product is Indeed dou·
ble precision, each addition performed is only single
precision. It would be desirable to be able to shift the
partial product as it is formed so that only single preci·
sion additions are performed. This would be especially
true if the partial product could be shifted into the "B"
operand since one bit of the partial product is formed
during each pass through the loop and (happily) one bit
of the "B" operand is vacated. To do this, however, it is
necessary to modify the algorithm so that both of the
shifts that occur are of the same type.
To see how this can be done one can take the basic
multiplication equation already presented:
and factoring 24 from the right side:
A*B=24[BO*(A*2- 4)+ B1*(A*2- 3 )
. + B2*(A*2- 2)+B3*CA*2- 1)]
This operation has resulted in a term (within the
brackets) which can be formed by right shifts and adds
and then multiplied by 24 to get the final result. The
resulting algorithm, expanded to form an eight by eight
multiplication, is shown in figure 5. Note that although
the result is a full sixteen bits, the algorithm only performs eight bit additions and that only a single sixteen
bit shift operation is involved. This has the effect of
reducing both the code space and the execution time
for the routine.
t1fICRO ASSEMBLER, V2. Il
SEQ
SOURCE STAmalT
1 $MACROFIlE
2 $INClUDKF1.t1Pi'S. Hm
j .:
***************************************"**************************************,.
4.:*
5 .: '"
HPY8X8
'"
i ; *==========--================--============*'"
B i*
,.*
THIS UTllITI' PROVIDES AN 8 BI' a UNSIGNED MULTlPLI'
9 i*
AT ENTR... :
10 i*
*
A = lOWER EIGHT BITS OF DESTINIITION OPERAND
11 i*
.'"
XA= DON'T CARE
12 i*
R1= POINTER TO SOURCE OPERAND (t'IUI.. TIPLIER) IN IN1ERNIII. MEMEORI'
13 .:*
*
Figura 5
All mnemonics copyrighted © Intel Corporation 1979.
1-61
inter
AP·49
SOURCE STATEl£NT
LOC 08.1
= 14;*
=
AT EXIT,
15 i*
16 i*'
17
18 ;*
19 i*
,i.
29 ;
A = LOWER EIGHT BITS OF RESllT
XA= UPPER EIGHT EIlTS OF RESUL r
C = SET IF OVERFLOW ELSE CLEARED
24 ; 1 MP'r'8X3,
25 ,1 I'IULTiFLICAND[ 15-8 J =0
: 26 .·1 CLiUNT. =8
27 i 1 REPEAT
23 i 2
IF I'lULTIPLICANV[0J=0 THai BEGIN
29 .:>
MULTIPLlCAND,=MULTIPlICANro/Z
i;1
:11 d
32,:
]} ,; 2
ELSE
MlILTlPLICRND[ 15-8], =t1ll T1PLItAN{)[15-S J+PlUL TIPLIER
MULTIPLlOINr':=I'1ULTIPLICAND/2
ENDIF
f4 i 2
~OOtlT =COIJNT-1
]5 ; 1 UNTIL COUIIT=0
~s ,lEN£, MP'J3XS
:·7 :
?8 EQIJATES
J9 i
4B ;
41 XA
EQIJ
9002
000?
9004
EQU
42 COuNT
R2
R3
R4
43lOIT
EQIJ
44 ;
45 OII3PR EQlJ
3
46 ;
47 $EJECT
48 $INCLlIDE<: F1: MP'r'8)
49 ; 1 MP'r'8X8'
9003
50 MP~'8l<:B:
51 ,.1 t1llTIPLIC.ANI)[15-81:=9
52
I10V
53 ; 1 COONT:=S
54
I'IOV
0000 BA00
0092 B!l9B
XA, 100
COUNT, tIS
55 ;1 REPEAT
56 I'IPYSLP.
9004 120E
=
9096 2A
aile?
9"1
Il008 67
OO~
2A
000A 67
0098 E894
900D 83
*
*".
**************••******.**********"'***~*******"'**"'**t******.t***••",...**********
21 ;
22 ;
23 $INCLUDE( :F1:t'lPVS POL)
:10
*
57 i 2
IF MlILTJPLlCAND[llJ=9 THEN BEGIN
58
59 i 3
JB0
I'1f'YSA
MIJL TIPLl CAND : =MIJL TIPLICAND/2
69
61
XCH
CLR
A, XA
C
62
63
RRC
XCH
154
RIle
A
A. XA
fI
65
orNZ
COUNT. MP'r'8LP
66
6;' ,;2
RET
ELSE
Figure 5 (contlnuad)
All mnemonics copyrighted © Intel Corporation 1979.
1-62
AP·49
LOC· OBJ
SEQ
SOURCE STATEMENT
68 I'lP'r'BA:
69 ,3
= 70
71
72
ewE 2A
000F 61
0018 67
13011 2A
0012 67
ADD
73
74
7!;
76
i7 ; 1
78 ,2
79 ; 2
0013 EB94
0015 83
sa .: 1
~~1
82
USER S'l't'1BOLS
COUNT iJ!.lO?
MIJLTlPLICAND[15-SJ:=I1IJLTlPLICI-lU(){15-S]+I'IULTlPLIER
XCH
A~ XA
;1
E~[i
DlGPP 0003
A5SEI1BL't' COMPLETE.
A, @111
RfiC
A
XCH
A, XA
Rr;'C
A
DJNZ
COUNT, HP't'8LP
RET
MIJL TIPLICANI): =I'IIJL TIPLICANI)/2
ENDIF
COUNT· =COUNT-1
UNTIL COUNT=0
END 11P~'3:<3
leNT
9004
MP'~SA
00iJE
MF'~8LP
0004
MPV8X8 !lOO!l
XA
tlO EJIRORS
All mnemonics copyrighted © Intel Corporation 1979.
DIVIDE ALGORITHMS
In order to understand binary division a four bit operation will again be used as an example. The following
algorithm will perform a four by four division:
DIVIDE:
IF 16*DIVISOR>= DIVIDEND THEN
SET OVERFLOW ERROR FLAG
ELSE
IF 8*DIVISOR>= DIVIDEND THEN
QUOTlENT[3]:= 1
DIVIDEND: = DIVIDEND - 8* DIVISOR
ELSE
QUOTlENT[3]: = 0
ENDIF
IF 4*DIVISOR>= DIVIDEND THEN
QUOTlENT[2]: = 1
DIVIDEND: = DIVIDEND- 4*DIVISOR
ELSE
QUOTlENT[2]: = 0
ENDIF
IF 2* DIVISOR> = DIVIDEND THEN
QUOTIENT[1]: = 1
DIVIDEND: = DIVIDEND - 2*DIVISOR
ELSE
QUOTIENT[1]: = 0
ENDIF
IF 1 *DIVISOR> = DIVIDEND THEN
QUOTIENT[O]: = 1
DIVIDEND: = DIVIDEND - 1 *DIVISOR
ELSE
QUOTIENT[O]: = 0
ENDIF
ENDIF
END DIVIDE
The algorithm is easy to understand. The first test asks
if the division will fit into the dividend Sixteen times. If it
will, the quotient cannot be expressed in only four bits
so an overflow error flag is set and the divide algorithm
ends. The algorithm then proceeds to determine if eight
times the divisor fits, four times, etc. After each test It
either sets or clears the appropriate quotient bit and
modifies the dividend. To see this algorithm in action,
consider the division of 15 by 5:
00001111
- 01010000
(15)
(16*5)
00001111
- 00101000
(15)
Doesn't fit-no overflow
(8*~)
Doesn't lit-Q[3] = 0
00001111
- 00010100
·(15)
(4*5)
00001111
- 00001010
(15)
(2*5)
Doesn't lit-Q[2]=0
00000101
00000101
- 00000101
00000000
Fits-Q[1] = 1
(15-2*5)
(1 *5)
Fits-Q[O] = 1
The result is ci = 0011 which is the binary equivalent 01
3-the correct answer. Clearly this algorithm can (and
has been) converted to a loop and used to perlorm divisions. An examination 01 the procedure, however, will
show that it has the same problems as the original multiply algorithm.
1·63
Ap·49
The first problem is that double precision operations are
involved with both the comparison of the division with
the dividend and the conditional subtraction. The
second problem is that as the quotient bits are derived
they must be shifted into a register. In order to reduce
the register requirements, it would be desirable to shift
them into the divisor register as they are generated
since the divisor register gets shifted anyway. Unfortunately the quotient bits are derived most significant
bits first so doing this will form a mirror image of the
quotient-not very useful.
When this algorithm is implemented on a computer
which does not have a direct compare instruction the
comparison is done by subtraction and the inner loop of
t,he algorithm is modified as follows:
REPEAT
DIVIDEND:= DIVIDEND*2
QUOTIENT: = QUOTIENT*2
DIVIDEND: = DIVIDEND - DIVISOR
IF BORROW=O THEN
QUOTIENT: = QUOTIENT + 1
ELSE
DIVIDEND: = DIVIDEND + DIVISOR
ENDIF
COUNT: = COUNT - 1
UNTIL COUNT = 0
Both of these problems can be solved by observing that
the algorithm presented for divide will still work if both
sides of all the "equations" involving the dividend are
divided by sixteen. The looping algorithm then would
proceed as follows:
DIVIDE:
QUOTIENT: = 0
COUNT:=4
DIVIDEND: = DIVIDEND/16
IF DIVISOR>=DIVIDEND THEN
OVERFLOW FLAG: = 1
ELSE
REPEAT
DIVIDEND:= DIVIDEND*2
QUOTIENT: = QUOTIENT*2
IF DIVISOR> = DIVIDEND THEN
QUOTIENT: = QUOTIENT + 1/*SET QUOTIENTIO]*/
.
DIVIDEND:= DIVIDEND- DIVISOR
ENDIF
COUNT: = COUNT - 1
UNTIL COUNT = 0
ENDIF
END DIVIDE
An implementation of this algorithm using the 8049 instruction set is shown in figure 6. This routine does an
unsigned divide of a 16 bit quantity by an eight bit quantity. Since the multiply algorithm of figure 5 generates a
16 bit result from the multiplication of two eight bit
operands, these two routines complement each other
and can be used as part of more complex computations.
ISiS- II HC5-4B/UPHl t1ACFO ASSEMBlER, Y2. 9
Lor 08,]
S(NJRCf STATEMENT
SEQ
1 tl'lACROFILE
;: tINCUJ[lE{ :F1·[lIII16. HED)
:: ,.~*~",,,,**.*~*******************************************. .************************
i*
*
:*
DIV1b
*
.*
,.
4
'5
6
7
S
9
19
11
12
13'
.14
1'5
16
17
.: *==============================================?========*
>I<
;*
,..
THIS UTILITY PRO\IIDES' AN 16 BY S UNSIGNED DIVIDe
;*
>I<
;*
AT ENTRY:
p~
A = LOWER ElGtH BITS OF DESTINATION OPERAND
*>I<
XA= UPPEI1 EIGHT BIT5 Of DIVIDEND
.
;*
R1= POIllTER TO DIVISOR IN INTERNAL MEMORY
>I<
; '"
AT EXIT:
:*
*
;*
A = LOWER EIGHT BITS· OF RESUL1
...
;*
XA= JlEt1AINDER
*
'"
*
Figure 6
All mnemonics copyrighled (0 Inlel Corporalion 1979.
1-64
inter
LOC OBJ
Ap·49
SEQ
SOURCE STATEMENT
C = SET IF OVERFLOW ELSE CLEARED
,.
'"
29 .' **~***** N .**~~ _* H~ '~*.j.*~·*f··.*******,H*****",*******.I<*********"'***~**"'*~,*******
21 ,
22 ;
2,
24
25
26
27
28
29
tINCLUDE(F1:DIV16 PDLl
; 1 [\11116
; 1 rOUrn·=3
; 1 ['JVJ[lEN~[15-8J=[JJVJDEN[U~H3H)lVI50~'
; 1 IF BORROIol=0 THEN l* IT FITS.:,'
;2
SET OVERFlOIJ "LAO
; 1 ELSE
30 ; ~
~ESTO~E
31
12
13
34
35
?6
PEPEAT
DIVlDEND:=DIVIDENU*2
OIJOTJENT =QIJOTIENT*2
;2
,3
;?
;:;
.: 1.
;4
:7 ; 3
38 :4
19 .:,.
0002
000:5
!lael BB0e.
0903 37
0004 61 .
8905 37
0996 F60B
m~e8 117
<1!llJ9 0424
0008 61
[Il'JlDENll
[;!V!I)END[15-8J:=~IV!l)END[1~-SHIVISOP
BOR~OH=l THEN
RESTORE DIVIDEND
ELSE
IF
;}UOTJENf[0] =1
ENDIF
411 ; -,
t:ourn . =COUNT-1
41 ;"2
IJPHIL COIJNT=0
42 .: 2
CLEAR OVERFLOW FLAG
4:5 ; 1 END:F
44 :1·ENDDmDE
45 ;
45 . EQUATES
47 .'
43 "
49 >:11
EGIJ
R2
f(!
59 COUNT EGU
51 ;
52 $EJECT
53 sJNCLlIDE< :F1:I!IV16)
54 ,1 DIVi6.
55DIVlt:. XCH
A,XA
,,"OOTlNE WORKS MOSTLY WITH BIl5 15-8
=.56 ;1 COllIIT:=8
57
t10V
COONT, #~o
58 ·1 DIVIDEN[I[1S-8l:=DIVIDEN[H5-SJ-DIVISOR
59
CF'L
A
60
ADf'
A. @R1
61
CPL
A
" 62; 1 IF BORROH=ll THEN /* IT m 5"'/
6"1
Ie
[)I VIA
64 ; 2
SET OVERFLOW FLAG
65
CPL
C
JMP
DIVIS
66
67 ; 1. ELSE
61'1 [)I','lft:
69 ·2
IJ=l THEN
90
,"'Ie
Dlvre
-. 91 ,4
PE5TOI3
0019
00lA
0018
;<(,H
110V
'55
O(l!:l5 8100
eaec
1'10'1
eCD' =BCD*2tC~R\'
~Ol
H.R9
R1.A
HOII
XCH
A.R9
11011
ICNT.IDIGPR
TEMP!. Ii
MOil
MOY
f100C
A·@R1
[lfl
MOil
A
@j;'LA
INC
Rl
~.@Rl
leNT. BCDOC
>31
MOY
A. TEMP1
82 .2 . IF CARRY FPCit'! BC[lACC GOTO ERROR EXIT
83
Je
BCOCOD
84 .' 2 couln .=COIJNT-1
85 ; 1 UNTIL GOUNT=!!
06
r, JNZ COUNT. BCOCOB
091F F624
0021 EBOC
8823 97
DJN2
G7
CLR
C
88 ; 1 END CONVERT-TO_BCD
89 ewcOD RET
90 END
0024 83
USER SYMBOLS
BWCOA il005
BCDCOI3 OOOC
TEMPi 0(,'.0'5
l:A
M55EMBL',' cot-RETE.
BC[JCOD 0024
; CLEAR CARRY TO ltIDICATE NORMAl.. TERHINftTlOtl
BCDOC 0017CNBC[1 0000
0W2
/10 ERI"OR5
Figure 7 (conllnuld)
All mnemonics copyrighted Intel Corporation 1979.
1-68
COUNT 0003
DI (jPR e003
1(;NT
9004
intJ
Ap·49
The conversion of a BCD value to binary is essentially
the same process as converting a binary value to BCD.
CONVERT_TO..BINARY
BIN:=O
COUNT:= DIGNO
REPEAT
BCDACCUM: = BCDACCUM • 10
BIN:= 10· BIN + CARRY DIGIT
COUNT: = COUNT - 1
UNTIL COUNT=O
END CONVERLTO_BINARY
The only complexity is the two multiplications by ten.
The BCDACCUM can be multiplied by ten by shifting it
left four places (one digit). The variable BIN could be
multiplied using the multiply algorithm already dis·
cussed, but it is usually more efficient to do this by mak·
ing the following substitution:
BIN=10· BIN=(2)· (5)· (BIN)=2· (2·2+1)· BIN
This implies that the value 10 • BIN can be generated by
saving the value of BIN and then shifting BIN two places
left. After this the original value of BIN can be added to
the new value of BIN (forming 5 • BIN) and then BIN can
be multiplied by two. It is often possible to implement
the multiplication of a value by a constant by using such
techniques. Figure 8 shows an 8049 routine which con·
verts BCD values to binary. This routine differs slightly
from the algorithm above in that the BCD digits are read,
and converted to binary, two digits at a time. Protection
has also been added to detect BCD operands which, if
converted, would yield binary values beyond the range
of the result.
151:-!! I1CS-4:3!IJPI -41 MACI"O ASSEMBLEP, \(2. 0
lOC OBJ
SEQ
501JRCE: STATEMENT
1 Si'1HCROFILE
2 >INCLUDE( F1:CONIlIN. Hm)
] .: *************_.****-1<****** ~.~*.~*********************",***************.*******",*~,*
4 ;t
5.*
'"
CONBIN
'"
'"
7 ; *==================================================================*
B .:t
,..
THIS UIILlW CON'/EIHS A 6 DIGIT BCD '~ALUE TO B1NARI'
9 :*
10,.
11 :.~
12 :j<
13 j t
14.:*
1~
:*
16 :*
AT ENT,..... ·
RO= POINTER TO II PACKED BCD STFING
AT EXIT:
H = LOWER EHiHf BITS OF THE BINARY RESULl
l\f:= tiPPER EIGHT BITS OF THE BINARY RESIJl T
C = SET IF OVERFLOJ,l ELSE CLEARED
'"
'"
'"
'"
'"
'"
'"
'"
V.:*
'"
18 : ************"'i·'f<*~**.~*,'·t-*'f<**~*****""*"'***"'**t.j<************"'*"'***********"'*******
19.:
29 :
21 $INClUDE( ·F1:CONBW. POl)
22 ;
23.
24 .: 1 1.:ot·WERLTO_BINAR'r'
25 .: 1 POINTER0:=POHlTER0+DIGITPAIR-i
26 : 1 COlIIIT: =DIGITPAIR
27 ; 1 BIN:=~
23 : 1 REPEAT
29 : 2
BIN: =BIN"'W
:m:2 BIN:=BIN+MEM(RM7-4J
31:2
BIN:=8IN*10
12 .: 2
BIN. =BIN+r1EWR0)D-01
All mnemonics copyrighted © Intel Corporation t 979.
1·69
intJ
AP·49
lOC 08J
soo;:CE STRTEIENT
SEQ
3J ; 2
34.2
POJtIT~
=POINTER8-1
COUNT:=COUNT-l
~5 •1 UNTIL WUtH =~
36 ; 1 EN!) CON"'Ej;'L TO_BlNAI?Y
33 . EOIJRTES
39 .
40.:
41 XA
42 COUNT
43 leNT
44 ;
45 DIGPR
9003
EQIJ
EQU
EQU
R2
R3
R4
EQU
3
46;
47 fEJECT
43 $INCLUDE ( 'F1. CONBIN)
49 .
59 TEMPi
51 TEMP~
SET
SET
R5
R6
52 ;
9000 Fa
8001 11302
9003
~8
8W4 BSIl3
0006 27
8W7 AA
0008 142B
009A F62A
ttOOC AD
BOOD
000E
OOBF
0011
; 1 COt/VERLTO_BINARY
COIlBIN:
; i POINTER0:=POINTER0+DIGITPAIR-l
1'10'./
A, RIl
ROO
A,I01GPR-i
t'f()V
RB.• A
; 1 COllNT:=DIGITPAIR
69
1'1
6D
74
;'5
76
77
78
79 ;2
80
81
82 :2
0015 2Fl
0016 F62A
0018 142B
001A F62A
AD
Fe
72
73
3?
84
5~0F
as
61)
B6
37
2A
All mnemonics copyrighted CO Intel Corporation 1979.
MOV
COI.JNT, If) IGPR
61 .,1 BIN =0
62
elF:
A
E::
MOil
i(il, A
64 . i REPEAT
65 CGNBlP:
66,2
BIN:=BIN*10
67
CALL
CONB10
68
.Ie
CONSER
69 ,2
BIN. =BIN+MEM(R0)[ 7-41
79
MO\!
TEMP1, A
F9
47
530F
. 0012 2A
0013 1399
901C
0010
001E
B020
9021
53
54
55
56
57
58
59
!1OV
R, @RO
SWAP
A
A,#iJFH
ANl
AI)[>
Fl, TEI1Pi
A, XA
XCH
A,too
AOOC
;':CH
A. XA
K
CONBER
~IN =BItM0
CALL
CONB10
JC
CONBER
BIN =B IN+t1EH (RBi[ HlJ
MOV
TEt1Pl, A
A..@RQ
MOV
ANL
A,10FH
AOO
A, TEMPi
A, XA
XCH
1·70
intJ
Ap·49
LOC 00)
SOURCE STATEI'IENT
SEQ
88
89
0022 BOO
0024 2A
1l1l2'3 ~62R
AOOC
XCH
90
91 ; 2
92
0027 CS
A, 100
ft,XA
JC
COIISEII
POI'lTER9. =POINTER0-1
DEC
R0
93 ,2
COUlIT :=COUNT-l
94 ; 1 UN1IL COIJllT=e
95
002S EBBS
D.JNZ
CO'JIlT, CONBLP
96 ; 1 END CONVERLTO_BIHAR'I
97 COIl8ER: !lET
9S SEJECT
99
002A 83
=100 ;
= 101
= 102
= HIS ;
= 104 CONBl9. MO~'
= 105
XCH
002B All
902C 21'1
= 106
= 197
= 10S
= 109
= 119
= 111
= 112
= 113
= 114
= 115
= 116
= 117
= 118
902D AE
002E 2A
00'5 97
003B F7
0031 2A
0032 F7
0033 2A
00:14 F646
9036
00:?7
0038
0039
UTILI T'1' TO I'IIJLTIPL.,.. BIN BI' 10
CARR~' WILL BE SET IF OVERFLOW OCCURS
F7
2A
F7
2fl
I1(IV
TEMPi. A , SAVE A
A, XA
!>AVE XA
TEl'lnA
XCH
A,XA
CLR
PLC
C
XCH
RlC
A
A.Xft
JC
CONBIE ; ERROR 011 OVERFLOW,
RLC
A
A.XA
XCH
RLC
803ft F646
003C 6D
903& 2ft
883E lE
= 121
= 122
= 123
= 124
ADDe
=125
XCH
= 126
= 127
JC
= 128
RLt
XCH
2A
0040F646
0042
9043
9044
9045
F7
2A
F7
2A
0046 83
USER SYMBOLS
CONB10 0028
TEl1Pl 0095
CONBIE 0046
TEt1P2 0006
ASSEMBLV COMPLETE,
NO
; BIN: =BIIO*4
ft
XCH
A,XA
.Ie
CONBIE ; ERROR ON OVERrLOW
AI.lO
XCH
= 129
= 130
= H1
= B2 ;
= 133 CONalE:
= 134
= 135
136 ~N!)
; BIN: =BIN*2
;{r)l
= 119
= 120
OO~F
A
RLC
XCH
A. IDtf'1 ; BIN:=BIN*S
A, l(A
A, TEMP2
A. XA
COIIBIE ; ERROR ON OVERFLOW
A
; BIN: =8110*10
A. XA
A
A.XA
RET
CONSER 902A
i:A
0902
COIIBIN 0000
CONBLP 0008
E~:ROR5
All mnemonics copyrighted © Intel Corporation 1979.
1-71
COUNT 9003
DIGPR 0003
ICNT
0004
inter
Ap·49
CONCLUSION
The design goals of the full duplex serial communIcations software were realized; if transmission and reception are occurring concurrently, only 42 percent of the
real time available to the 8049 will be consumed by the
serial link. This Implies that an 8049 running full duplex
serial I/O will still outperform earlier members of the
family running without the serial I/O requirement. It is
also possible to run this program in an 8048 or 8748 at
1200 baud with the same 42 percent CPU utilization.
the highest performance microcomputer available to
date, the performance advantage of the 8049 should
allow the cost benefits of a single chip microcomputer
',to be realized in many applications which up until now
have required too much "computer power" for a'single
chip approach.
EXEC!JTION TIME
(MICROSECONDS)
The execution times for the other routines that have
been discussed have been summarized in Table 1. All of
these routines were written to maintain maximu'm useability rather than minimum code size or execution time.
The resulting execution times and code size are therefore what the user can expect to see in a real application. The results that were obtained clearly show the efficiency and speed of the 8049. The equivalent times for
the 8048 are also shown. It is clear that the 8049 represents a substantial performance advantage over the
8048. Considering, in most applications, that the 8048 is
BYTES
8049
8048
MPY8
21
109
200
DIV 16
37
183,MIN
204 MAX
335 MIN
375 MAX
CON BCD
36
733
1348
CONBIN
70
388
713
Table 1. Program Performance
1·72
intJ
APPLICATION
NOTE
AP·55A
August 1979
INTEL CORPORATION ASSUMES NO RESPONSIBILITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EII80DIED IN AN INTEl PRODUCT. NO OTHER CIRCUIT PATE.n utENSES ARE IMPLIED.
©INTELCDRPORATlDN.1979
1-73
9801007-<)1
AP·55A
I. PURPOSE AND SCOPE
• Breaks may be triggered by either program or external data RAM accesses;
This Application Note presents a description of the
design and operation of a high·speed emulator for the
Intel'" MCS·48™ family of single chip microcomputers.
The HSE·49™ emulator provides a simple and inexpen·
sive means for executing and debugging 8049 programs
which require the full 11·MHz operating speed of the
part.
• Any number of breakpoints may be used in any
combination;
• "Auto-Step" operation causes the current program
counter and Accumulator contents to be printed on
the display for a short time on every instruction
cycle;
Section II of this Application Note describes some of
the features of this development tool and how it may be '
used. Section III briefly discusses the hardware used to
implement these features, while Section IV describes
the manner in which program execution status is made
available to the operator.
• "Auto-Break" provides the above display only when
a break flag is encountered, with real time operation otherwise;
• While running in non-break mode, a TTL-level pulse
is generated whenever a break flag is encoun'tered.
This signal may be used to trigger an oscilloscope
or Logic Analyzer to assist in hardware and software debug.
A detailed description of all of the operator commands,
is presented in Section V of this note, along with the
modifiers and options which may be specified for each
command. Known restrictions and limitations of the
HSE·49 system are listed and explained in Section VI.
Section VII shows how the basic circuit may be
modified to provide options on memory organization, I/O
configurations, etc.
Full schematics of the system hardware, as well as
monitor software listings, are presented in Appendices
: A and B, respectively. A short summary of the command
syntax is presented in Appendix C,. Appendix D ex·
plains the error message codes which may appear duro
ing use.
It is assumed that the reader is already familiar with the
operation of the 8048 or 8049 microcomputers. Some
knowledge of the 8048 architecture is needed to under·
stand sections of the command and modifier descrip·
tions. Most users will already have this background.
Other readers are referred to the MCS·48 Microcom·
puter User's Manua/, Intel publication number 9800270.
• While running in any mode, the keyboard and
display are "alive". Execution may be suspended or
terminated by commands from the keyboard.
Intent of this Note
While the HSE-49 emulator can assist a new microcomputer user in becoming familiar with the 8048 and 8049
microcomputers, its inherent debug capabilities will
also prove helpful to design engineers. The design'
could be used for new system development and verification or adapted for prototype production.
The main concern in designing the HSE-49 emulator was
to keep the basic design simple, while maximizing the
system's flexibility. The design allows the use of
jumpers, hardware and software switches, etc. to allow
the user to reconfigure the system according to the way
he dedicates chip-select pins, 110, etc. The emulator can
be changed to fit each user's unique needs, rather than
forcing the user to alter his needs to what is provided ..
The primary intent of note is to provide the reader with
the information needed to reconstruct and make full use
of the HSE-49 emulator. Less emphasis is placed on
describing how the hardware operates or how the commands are implemented. This information may be found
in the schematic diagrams and software listings inCluded in the Appendices.
II. THE HSE·49 DEVELOPMENT TOOL
In essence, the HSE-49 emulator provides the user a
means for executing an MCS-48 program located in ex·
ternal RAM rather than internal ROM or EPROM. This
allows programs being debugged to be modified easily
and quickly during the debug cycle. A user's program
. may be entered into system RAM either manually or via
a serial link from a host computer such as an In·
tellec'" Microcomputer Development System. Once
loaded, the program can be modified using an on-board
keyboard and display, and executed in real-time in a
. number of breakpoint modes. The internal state of the
processor, including RAM,:accumulator, timer/counter,
and status register contents, can also be read and
modified through the keyboard.
'
Breakpoinf and 'debug facilities are extremely fl,exible.
The following execution modes are provided.
• Programs may be run in full (11 MHz) real time;
• Programs may be single-stepped;
• In break mode, programs run in full real time until
break occurs;
III. GENERAL HARDWARE OVERVIEW
User Program Emulation
The actual emulation of the user's program is done
using an 8039 microcomputer (IC29 on the schematics
in Appendix A) executing a program stored in external
RAM. The basic minimum configuration includes the
8039 microcomputer, an 8282 address latch (IC19), and
2K bytes of 2114 RAM to use for program development
and real-time,execution (ICs B1, C1, B2, and C2). Additional RAM may be added to allow the user to expand
his program and data memory to 4K each. (If an 11-MHz
crystal is used with the microcomputer, tYPE! 2114-3
RAMs must be used.)
1-74
intJ
AP·S5A
System Supervision
familiar with the PROMPT-48™ debug tool for the 8048
will find that 25 of the HSE-49 emulator keys are identical in function and layout to the PROMPT-48 keyboard,
and use the PROMPT-48 command syntax. The eight additional keys are used to generalize and augment the
PROMPT·48 capabilities, as described in Section V.
A second microcomputer - another 8039 (IC25) with an
8282 address latch (ICI6) and off-chip program memory
in a 2716 EPROM (iCI5) - is used to scan the on-board
keyboard and display, interpret and implement commands, drive serial interfaces, etc. In general, the
master processor is used to interface the execution
processor's memory spaces with the outside world and
control the operation of the execution processor. In this
note the two processors will be abbreviated "MP" and
"EP", respectively. Figure 1 shows how the two processors interrelate with the rest of the system.
system.
The eight-character seven-segment display (DS1-DS8)
is used for displaying addresses, data, and pseudoalphanumeric messages_ The display responses printed
in Section V and throughout this note use a mix of upper
and lower case letters to indicate what seven-segment
patterns appear. An 8243 (IC9) and eight DIP packages
(resistor packs, current buffers, etc_) are used for
multiplexing the display and scanning the keyboard_
Keyboard/Display
Breakpoint Detection
The 33-key keyboard shown in Figure 2 includes a 16-key
hexidecimal keypad and 17 special function keys for
specifying commands and modifiers. Readers already
Breakpoints are specified and detected using a 2102A
lK x 8 RAM corresponding to each pair of 21145 (ICs AI
USER
SYSTEM
PROTOTYPE
HOST
COMPUTER
SYSTEM
(INTELLEC)
DODOOE/e/D
O.O.O.c.I.D.C .Ll.O
C
D
E
F
CRT
A B
4
5
6
7
o
1
2
3
Figure 1. HSE49™ Emulator Signal Flow Diagram
B I
GO/RESET
I
I II
UPLOAD
SYS RST
DNLOAD
IG
I
I
I
EXAM/CHA
I
CLR/PREV
B I
HARD REG
IB
B
DDD0
DDDD
I DDD0
DODD
I
Figure 2. HSE_49™ Emulator Command Keyboard Organization
1-75
AP·55A
and A2). In effect, each program or data address accesses a 9-bit word. Eight bits are used normally for
code or data storage. The ninth bit, accessed in parallel
with the other eight, is used to indicate if a breakpoint
has been set for that address. This output, when
asserted, is latched {IC27 and IC36) and used to halt the
execution processor via the single-step input. (In other
modes, the break logic can be reconfigured to set the
break requested flip-flop on any EP machine cycle or
any EP "MOVX" instruction.)
baud from the on-board keybad. Blocks of data may be
transmitted to a CRT or printer and displayed in a
tabular format.
IV. INTERPROCESSOR COMMUNICATION
Program Break Sequence
When the MP detects that the EP has been halted by the
breakpoint hardware, or when the operator presses a
key while the program Is executing, the program break
sequence is initiated. The low-order 23. bytes of user program memory is read into a buffer within' the internal
RAM of the MP. A short program for reading and
transmitting internal EP status is written over the loworder program memory. (This is one of several "minimonitors" overlayed over the user program area.) The
link register is mapped logically over the user program
memory, and loaded with the 8049 machine code for a
"CALL" instruction to the mini-monitor program area
The EP is then allowed to fetch Ii single instruction fro~
the link, i.e., the "CALL" to the mini-monitor is forced
onto the EP data bus.
Link Register
An 8212 8-bit latch (IC18) is used to communicate data
and commands between the master and control processors. Under control of the MP, this register, called the
"Link" register, may be logically mapped into either the
program or data RAM address spaces. When this is
done, the 2114s in the respective memory space are
disabled and the link responds to all accesses.regardless of address. The link will be discussed in
greater detail in Section IV.
Control Logic
From this point on, the EP elfecutes code contained in
the mini-monitor. The link is logically mapped over the
data RAM address. space (whether or not any 2114 data
RAMs are present). A block diagram of the system at
this point is shown in Figure 3. The break logic is reconfigured so that any "MOVX" (RD or WR) operation executed by ttie EP will cause it to halt.
In addition to the devices mentioned above the
minimum configuration requires about 10 addition~IICs
for bus arbitration, system control, and breakpoint and
single-step logic; Additional parts may be optionally
added for serial port interfacing, I/O reconstruction, etc.
MP Monitor
For example, after entering the first mini-monitor, the
EP executes a "MOVX @RO,A" Instruction. This writes
the contents of the accumulator prior to the execution
termination into the link, and causes the EP to halt. The
MP may then read and retain the link contents to determine the EP accumulator value. The EP timer/counter
and PSW are preserved in the same manner.
The monitor program executed by the MP includes commands for filling, reading, or writing the various memory
spaces, including the execution processor's program
RAM, external ("MOVX") data RAM, accumulator, PSW,
PC, timer/counter, working registers, and internal RAM;
to execute the user's program from arbitrary addresses
in various debugging modes; and to upload or download
object or data files from diskettes using an Intellec@ development system. No special software is
needed for the Intellec@ other than ISIS Version 3.4 or
later. The data format is compatible with the standard
Intel hex file format produced by ASM-4; the baud rate
may be altered from 110 baud (default state) up to 2400
Accessing EP Internal RAM
After reading and saving EP internal status, the MP
loads a different mini-monitor into the same RAM area.
This monitor allows the internal RAM of the EP to be
read and written by the MP by passing address and data
EXECUTION"
PROCESSOR
MASTER
PROCESSOR
Figure 3. Communication between EP • MP
All mnemonics copyrlghled© Inlel Corporation 1976.
1-76
inter
AP·55A
values between the two processors using the link
register.
This is needed for two reasons. First, the EP program
counter prior to the forced "CALL" instruction may be
derived from the EP stack contents, and may be
modified to cause the EP to resume execution at any
desired address. Secondly, the internal RAM of the EP
may then be accessed and modified in the process of
executing a number of the monitor commands.
Resuming User Program Execution
In order to resume user program execution, a statusrestoration mini-monitor is overlayed. This restores the
EP internal status using a scheme analogous to the one
in which the status was originally saved. The final step
of the last mini-monitor is an "RETR" instruction, after
which the EP is again halted. The low-order program
memory saved earlier is rewritten into the appropriate
area, the break logic is reconfigured for the desired execution mode, and the EP is released to run at full speed
until the next break situation is encountered.
Note that all commands are implemented using
"logical" rather than "physical" addressing. Thus the
operator need not be concerned with the intricacies of
the system design. For example, when any monitor command refers to low-order user program memory, the appropriate byte of storage within the MP internal RAM is
accessed instead. If the location is altered, the internal
RAM is modified appropriately. When program memory
is reloaded prior to resuming user program execution,
the modified version of the user program will be the one
loaded.
low order part of a parameter; i.e., a command incorporating a data byte (such as [FILL]) will use only the
low-order 8 bits of the corresponding parameter; Internal RAM and hardware register addr,essing uses only
seven. In each case, higher order bits are ignored.
A command string is terminated and the command invoked by pressing the [END/.] key. The command will
also be invoked by pressing the [NEXT/,] key when no additional parameters are allowed. A command string may
be aborted at any point before the command is invoked
by pressing the [CLEAR/PREV] key, and the sign-on
message will appear.
Errors
An illegal command string, command terminator, or
hardware failure will cause an error message and error
code number to appear on the display (e.g., "Error-.3").
When this occurs, the monitor can be returned to command mode by preSSing the [CLEAR] or [END/.] keys. An
explanation of the various error codes is given in Appendix D.
Command Classes
Commands for the HSE-49 emulator are divided into
general classes, where all commands in each class have
the same choice of options or modifiers. A brief description of each command, followed by a description of the
allowed options, is presented below by class.
Data Manipulation/Control Command Group
Commands:
[EXAM/CHA]
Baud
HR06
HR07
110
150
300
600
1200
2400
93H
96H
45H
9DH
44H
1AH
04H
03H
02H
01H
01H
01H
Display Response Function -
Causes the memory address specified to be read
and presented on the display. New data may be
entered (if desired) from the hexidecimal keypad.
New data is verified before appearing on the
display. Subsequent or previous locations may be
read by pressing the [NEXT/,] or [PREY] keys,
respectively. Command terminated with [END/.]
key.
Table 1. Serial Interface Data Rate Parameters
v.
"ECh."
Examine/change memory location.
HSE-49 COMMAND DESCRIPTION
Whenever the characters "HSE-49" are present on the
system display, a command string may tie entered by
the operator. In general, all command strings consist of
a basic command initiator, an optional command
modifier or type-designator, and a number of parameters
or delimiters entered as hexidecimal digits. A command
is executed, or a command in progress terminated, by
pressing the [END/.] key. Logical default values are
assumed for the modifier and parameters if either (or
both) are omitted. A defualt parameter assumed for the
command modifier will be presented on the display
when the first parameter is entered.
[FILL]
Display Response -
"FIL."
Function - Fill range of memory addresses with a
single data value.
Fill the appropriate memory space between the addresses specified by the first two parameters with
the low-order byte of the third parameter. If second
parameter less than first, only the location
specified by the first is affected. IT third parameter
omitted, zero is assumed. If second and third
parameters omitted, individual address specified is
cleared. Command is useful for setting a large
range of breakpoints; e.g., all of page 3 may be
enabled for break with the command:.
Each parameter is a string of up to three hexidecimal
digits. If more than three digits are entered, only the
most recent three are considered. This allows an erroneous digit to be corrected without respecifying the
entire command. A parameter is completed by pressing
the [NEXT/,] key. Some commands may only need. the
[FILL][PROG BRK]<300>[,]<3FF>[,]<1>[.]
All mnemonics copyrighted©lntel Corporation 1976.
1-77
AP·55A
Function -
[LIST]
Display Response -
Register memory and RAM.
Internal RAM of execution processor. Locations
0-7 are working register bank 0; 18-1F are working
register bank 1. Only the low·order 7 bits of an ad·
dress are considered.
"LSI."
Function - List memory to output device through
HSE·49 serial port.
Display the contents of a range of addresses given
by two parameters to a, teletype or CRT screen.
Data,is formatted, 16 separated bytes per line, with
the starting address of each ,line printed. If used
with an Intellec'" system, the operator first uses
ISIS·II to transfer the TIY input to the CRT output
("COpy :TI: TO :CO:") then invokes this command
from the keypad. Alternatively, any ISIS device or
disk file name(:TO:, :LP:, :F1:HRDREG.SAV, etc.)
may be used as the destination.
[DATA MEM]
Display Response Function -
"dA."
External data memory (if installed).
Memory accessed by execution processor "MOVX
A;@Rr" or "MOVX @Rr,A" instructions. High·order
4 bits rr,ay or may not be relevant, depending on
jumpering option selected (explained in Section VII
of this note).
[DNLOAD]
Display Response -
[HARD REG]
"dnL."
Display Response -
Function - Download' memory through HSE·49 serial
port
Function -
"Hr."
Hardware registers.
Load data in hex file format through the serial input
port. If used with Intellec'" system, the operator
first invokes this command from the keypad, then
uses ISIS·II to transfer a disk file to the teletype
port ("COPY: Fn:file.HEX TO :TO:").
The execution processor (EP) hardware registers
(accumulator, timer/counter, etc.), as well as
several parameters for controlling HSE·49 system
status, are accessible through this catch·all
memory space. Addresses are as follows:
The use of the checksum field for the download
command is expanded slightly ,over the Intel hex
file format standard. If the first character of the
checksum field ,is a question mark ("?"), the
checksum for that record will not be verified. This
allows large object files produced by the assembler
to be patched using the ISIS text editor without the
necessity of manually recomputing the checksum
value.
00 -
EP accumulator.
01 -
EP PSW.
Bits correspond to 8049 PSW except that bit
3 (unused in the 8049) is u,sed to monitor and
alter the state of F1. Bits 2-0 correspond to
the stack pointer value after the EP executes
a CALL to the mini·monitor; i.e., one greater
than when EP was running the user's pro·
gram.
02 -
EP timer/counter.
03 -
EP internal RAM location 00.
(This value is also accessible through
[REGISTER] space.)
04 -
EP program counter (low byte).
05 -
EP program
[UPLOAD]
Display Response Function port.
"UPL."
Upload memory through HSE·49 serial
Output the contents of a range of addresses
specified by the two. parameters through the
HSE·49 serial port in standard Intel hex file format.
If used with Intellec'" system, the operator first
uses ISIS·II to transfer the TTY input to a disk file
("COPY :TI: TO :Fn:file.HEX"), then invokes this
command from the keypad.
HSE·49 automatic sequencing rate
parameter. Used in [GO][AUTO STP] and
[GO][AUTO BRK] execution commands. 00 fastest; FF - slowest. Defaults to 20H; ap·
proximately two steps per second.
09 -
Monitor version/release number (packed
BCD).
[PROG MEM]
Function -
"Pr."
User program memory.
Memory used to develop and execute user program.
Addresses 000 through 7FF are the execution proc·
essor's memory bank 0; 800 through FFF are
memory bank 1.
(lA-OF - Currently unused by the monitor program.
10-7F - Variables used by master processor (MP)
monitor. Should not be altered by operator.
[REGISTER]
Display Response -
(high nibble).
08 -
Data types allowed:
Display Response -
\~ounter
06-07 - HSE·49 serial interface baud rate paramo
eters. Defaults to 110 baud; other rates may
be selected by loading the values listed in
Table 1.
[PROG BRK]
"rG."
Display Response -
All mnemonics copyrighted© Intel Corporation 1976.
1-78
"Pb."
Ap·55A
Function -
Function - Go from reset state.
User program breakpoint memory.
Memory space used to indicate points where program execution should halt when running in a mode
with breakpoints enabled ([GO][W/ SRK) and
[GO][AUTOSRK)). Break will occur if enabled byte is
read as the first or last byte of a 2·byte instruction,
or read in executing a MOVP, MOVP3, or JMPP instruction. Memory is only 1 bit per location; 00 in·
dicates continue, 01 causes a hal!. Addresses 000
through 7FF are the execution processor's memory
bank 0; 800 through FFF are memory bank 1.
EP is hardware· reset and released to execute the
user's program from location OOOH. No parameters
are allowed. FO, F1, PSW, stack printer, memory
bank flip-flop, etc., are cleared.
Note that this command does not require the use of
mini·monitors to initiate program execution. As the
last phase of the program development cycle, the
2114 program RAMs and address decoder may be
removed and replaced by a ROM or EPROM part
(not shown in schematics). This command may be
used to start execution when the program RAM has
been removed. No interrogation of EP status or internal RAM may be done, nor are break or single·
step modes allowed in this case, though the 2102A
breakpoint RAM outputs may still be used to trigger
a logic analyzer.
[DATA SRK)
Display Response Function -
"db."
External data RAM breakpoint memory.
Memory space used to indicate points where data
accesses should halt when running in a mode with
breakpoints enabled ([GO)[W/ BRK) and
[GO][AUTOBRK)). Memory is only 1 bit per location;
00 indicates continue, 01 causes a hal!. High·order
4 bits of breakpoint address mayor may not be rele·
vant, dependent on jumpering option selected for
the corresponding data RAM (explained in Section
VII of this note).
Execution modes allowed:
[NO BRK]
Display Response Function -
Full-speed execution without breakpoints enabled.
Does not affect the state of the breakpoint
memories.
User Program Execution Control Group
[SING STP)
Commands:
Display Response -
[GO)
Display Response Function -
"nb."
Without breakpoints.
"Go."
Function -
"SSt."
Single Step.
Step through program one instruction at a time.
After each instruction is executed, execution halts
with the current value of the Execution Processor
Program Counter and Accumulator appearing on
the display in the form "PC.234-56". System status
is saved in the appropriate Hardware Registers. At
the pOint, [NEXT/,) will cause the program to ex·
ecute one more instruction, or any other command
may be invoked by pressing the appropriate com·
mand string. Does not affect the state of the Breakpoint Memories.
Begin execution.
If a parameter is given as part of the command
string, execution will begin at that address. Other·
wise, the EP program counter (hardware registers
04 and 05) will be used. These will contain the pro·
gram counter from an earlier program execution
break unless they have since been explicitly
modified by the operator.
If command is terminated by [END/.), the EP's F1,
PSW and stack pointer will be cleared. If command
string is terminated by [NEXT/,), PSW will be taken
from the EP PSW contents (hardware register 01).
[W/BRK]
Display Response - "br."
While running the' user's program, the characters
"-run-." are written on the display. Execution may
be halted and another command initiated by press·
ing the appropriate command key. Execution may
be suspended at any time in any mode by pressing
the [END/.) key. This will cause the current value of
'the execution processor program counter and accumulator to appear on the display in the form
"PC.234·56". System status is saved in the
appropriate hardware registers. At this point, or
when an enabled breakpoint is encountered, press·
ing the [NEXT/,) key will cause the program to con·
tinue in the same mode as before. Any other command may be invoked by pressing the appropriate
command string.
Function - With breakpoints.
Full·speed execution with breakpoints enabled.
When a breakpoint is encountered, execution halts
with the current value of the execution processor
program counter and accumulator appearing on the
display in the form "PC.234-56". System status is
saved in the appropriate hardware registers. At this
point, [NEXT.,) will cause the program to continue
until the next breakpoint is reached, or any other
command may be invoked by pressing the ap·
propriate command string.
[AUTO STP)
Display Response - "AS!'''
[GO/RESET)
Display Response -
Function - Automatically sequence through a series
of instructions.
"Gr."
All mnemonics copyrighted© Intel Corporation 1976.
1-79
AP·55A
Step through program one inst~uction at a time.
After each instruction is executed, execution halts
with the current value of the execution processor
program counter and accumulator appearing on the
display in the form "PC.234-56". System status is
saved in the appropriate hardware registers. Execution resumes after a time determined by contents
of hardware register 08. Does not affect the state of
the breakpoint memories.
System Control Command Group
Command:
[SYS RSn
Display Response Function -
Reset both the MP and EP and clear all preakpoints
(requires approximately one second). CAUTION If reset while EP is executing the user's program,
the low order,section of program memory (about 23
bytes) will be altered.
[AUTOBRK)
Display Response - "Abr."
Function points.
Automatically sequence between breakVI. SYSTEM LIMITATIONS
Execute a series ,of instructions in real time
between breakpoints. When breakpoint is en·
countered, halt EP temporarily while program
counter and accumulator contents are displayed,
then continue. Display is sustained after execution
resumes. Does not affect the state of the break·
point memories.
Breakpoint Control Command Group
Commands:
[B)
Display Response Function -
"Stb."
Breakpoint set.
Set breakpoint for the address given. Multiple
breakpoints may be set by entering additional addresses, separated by the [NEXT/,) key. Command
terminated by pressing [END/.). Action taken is to
fill the appropriate breakpoint memory locations
with logical ones.
[C)
Display Response -
"CLb."
Function - Clear breakpoint.
Clear breakpoint for the address given. Multiple
breakpoints may be cleared by entering additional
addresses, separated by the '[NEXT/;) key. Command terminated by pressing [END/.). Action taken
is to fill the appropriate breakpoint memory locations with logical zeroes.
Data types allowed:
[PROG MEM)
Display Res'ponse Function -
"Pr."
Break on program memory fetch.
Applies command to the program breakpoint
memory space.
[DATA MEM)
Display Response Function -
"HSE-49."
System reset.
"dA."
Break on data memory access.
Applies command to the external data breakpoint
memory space.
In designing the HSE-49 emulator, certain compromises
were made in an attempt to maximize the usefulness of
the'emulator while keeping the circuitry simple and inexpensive. As a result, the following limitations exist
and must be taken into account when using the system.
1. As explained in Section IV, user program execution
is terminated (by Single-stepping, breakpoints, press·
ing the [END/.) key, etc.) by forcing the execution
processor to execute a "CALL" instruction to the
mini-monitor. This uses one level of the EP
subroutine stack. The EP PSW reflects the value of
the stack pointer after processing this CALL. As a
result, the value indicated for stack depth ,by examining the EP PSW (hardware register 01) is one greater
than the depth when the break was initiated. The user
program must not be using all eight levels of stack
when a break is initiated or the bottom level will be
destroyed.
2. User program is initiated (by the [GO) command or
when resuming execution after a breakpoint, singlestepping, etc.) by forcing the EP to execute an
"RETR" instruction. This will clear the EP interruptin-progress flip-flop. If the user program allows both
external and timer interrupts to be enabled at the
same time, care must be taken to avoid causing a
break while the EP is within an interrupt servicing
routine. No limitation is placed on breakpoints or
Single-stepping in the background program because
of this.
'
3. When the user program execution is terminated (by a
break, single-stepping, etc.) and later resumed, the
EP timer/counter is restored to its value when the
break occurred (unless modified by the user)_ The
prescaler, however, will have changed. Thus, up to 31
machine cycles may be "lost" or "gained" if a break
occurs while the timer is running.
4. Timer interrupts occurring at the same time as an EP
break may be ignored if the timer overflow occurs
afler breaking user program execution be(orEl the
timer value is saved.
5. The 8049 "RET" and "RETR" instructions are each
1·byte, 2-cycle instructions. During the second cycle
the byte following the return instruction is fetched
and ignored. If a program breakpoint is set for a loca·
tion fe>lIowing a "RET" or "RETR" instruction, a break'
will be initiated when the return is executed ..
All mnemonics copyriQhted© Intel Corporation 1976.
1-80
Ap·55A
6. Breakpoints should not be placed in the last 3 bytes
of an EP memory bank (locations 7FDH-7FFH and
OFFDH-OFFFH). User program should not be single·
stepped or auto·stepped through these locations.
current·loop or RS·232C current buffers, but not both at
one time.
Standard Operating Configuration
(Minimum system configurations - up to 4K program
RAM; no data RAM; no serial interfaces; no execution
processor 110 reconstruction.)
7. Since 110 configuration is determined by external
hardware rather than software, 110 modes may not be
altered while a program is executing. (See Section VII
for further details.)
A. Basic 2K monitor from Appendix B:
8. The "ANL BUS,#nn" and "ORL BUS,#nn" instruc·
tions may not be used in the user program, as exter·
nal hardware cannot properly restore these func·
tions.
Install
Install
Install
Install
Install
Install
Install
Install
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Install
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9. The memory bank select flag is not affected by the
user program break sequence. Upon resuming execu·
tion with the [GO) command this flag will remain in
the same state as before the preceding break. The
flag may be cleared only by executing the
[GOIRESET) or [SYS RST] commands.
VII. HARDWARE CONFIGURATIONS
A number of control and status lines are available to the
user. All are low·power Schottky TTL·compatible
signals.
TP1 -
Unused MP input.
TP2 - Unused MP output.
TP3 - User program suspended. Low when EP run·
ning user code. High when halted or running mini·
monitors.
B. Expansion 2K monitor:
Install IC14
Remove jumper 17
TP4 - Breakpoint encountered. Normally low. High·
level pulse generated when breakpoint passed. Useful
for triggering logic analyzers, oscilloscopes, etc.
Serial Interface Buffer Selection
TP5 & TP6 - Memory matrix mode control. Select
program vs. data RAM, link mapping configuration,
etc. (See Appendix B for details.)
A. Current loop serial interfaces (4N46s) installed for
use with full Intellec'" Model 800 development
system TTY port.
TP7 - Bus control. Low when MP controls common
memory buses. High when EP controls memory
buses.
Install IC21-IC22
Install resistor R1-R3
Install jumpers 4-9
(Remove RS·232 jumpers)
The HSE·49 emulator hardware is designed to allow the
user to reconfigure the system for a wide variety of dif·
ferent applications by installing or removing jumper
wires or additional components. The schematics in Ap·
pendix A show the components needed for a variety of
different configurations. In general, not all of the
devices are required (or allowed) for anyone configura·
tion. The devices which are required are included in the
following description.
B. RS·232C serial interfaces (MC1488 and MC1489) in·
stalled for use with CRT as output device for data
dumps:
Install IC23-IC24
Install jumpers 1-3
Install jumpers 10-11
(Remove current·loop jumpers)
The types of options allowed are divided below into
several general classes and subdivided into mutually·
independent features. Within some of these features
there are numbered, mutually exclusive configurations;
i.e., the serial interface (if desired) may use either
All mnemonics copyrighted © Intel Corporation 1976.
resistors R4-R6
transistor Q1
crystals Y1-Y2
capacitors C5-C38
switches S1-S33
displays DS1-DS8
IC1-IC2
RP3-RP5
IC6-IC7
RP8
IC9
IC15-IC20
IC25-IC30
IC34
IC36-IC38
A1-A2
B1-B2
C1·C3
jumpers 13-15
jumpers 17-18
jumper 20
External Data RAM Address Decoding Scheme for Ex·
ecution Processor
A. Up to 16 pages of on·board external data RAM in·
stalled for execution processor (addresses 0 through
1·81
AP·55A
=
OFFFH 4K bytes); port 2 used for addressing pages
. 0 through 15:
Install
Install
Install
Install
Install
Reconstructing 110 for Execution Processor
A. Application of port 2, pins P23-P20:
jumpers 21-25
jumper 27
A5-A8
B5-B8
C5-C8
(1) Using P23-P20 for latched output data (used with
"OUTL P2,A", "ANL P2,#data", and "ORL
P2,#data" instructions):
Install IC31
B. One page of on·board external data RAM installed
for execution processor (addresses 0 through OFFH);
port 2 not used for data addressing:
(2) Using P23-P20 for interfacing to an 8243 in user's
prototype:
Install jumper 26
Install jumper 28
Install A5
Install B5
Install C5
Connect the outputs of IC20 .. pins 7, 9, 10, & 11 to
the inputs of a 74LS21 AND gate (not shown). Connect the output to CE and CS inputs of A5-C5.
(Note: these signals are all present at jumpers
21-24 on the schematics.)
All mnemonics copyrighted @ Intel Corporation 1976.
Connect 03-00 pins on IC31 socket to corresponding 03-00 pins.
B. Application of execution processor BUS:
(1) Use of BUS as latched output port ("OUTL
BUS,A"):
InstalllC32
1-82
AP·55A
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32; PPO[lIJCE fltf,' 08'][CT CODE ARE PRO(:E!;SEO BV HIE ASSEi'lBLER
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8(, ;
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88 ;
39.: ·~O\.lRr.:[-LINE" REFERS TO THl DEWlft NIJIf;£RS m T OF 1:J'l(;H INSTRUCTION.
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!11 ; lliE SEQLUITlflL !.-OIJRCE-UNE NUMBEf< OF RLL INSTANCES WHI:RE:. AN'r' VARIflBLE
92; IS vEFINED OR REFEr;'ENCED. )HIS WILL BE:. or CRUlT fl5S15'IRNCE IN
93 ; LOC.fll ING SPECIFI C SliSROIJTIN[j, ETC. IN TflE LISTING.
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1-87
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= 195
= 106
" 197
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8002
0893
9094
0093
11004
0085
0006
0087
0008
0982
SET
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= 113 ?OOPS
= 114 ?B0P6
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2
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3
4
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58
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= 116 •
9093
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= 119 ?BIR2
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= 121 ?B1F4
91.!86
9087
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8898
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=127 ;
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6
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0500
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50911
0100
0688
8700
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mnemonic~
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=132 ORGrG4
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= 135 ORGPG7 SET
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= 137 $EJECl
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copyrighled © Inlel Corporalion 1976.
1·88
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= 140
= 141
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= 159 $
:: WI
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:: 162 ?I'IINDX SET
:: IE;3 [NOM
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= 16'5 nocl( MACRO S'Il'IEOL, LENGTfI
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= IG6 ?&~""MIlOL
:: 167
?MSflVE S\'l'llJOL, LENGTH, ??i'lINDX
= 168 ENDI'I
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= 170 [)[CLfl~E MOCRO S'r'MBOL, TYPE.
= 171 ?&S'r'MDOL
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= 177
= 171]
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= 179 ENDIF
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:: 100 IF
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= IS1
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= 183 ENOlr
= 134
= 1('.5,
= 186 $
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All mnemonics copyrighted © Intel Corporation 1976.
1-89
Ap·55A
Lot
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(is,}
SOORCE STATEI1ENT
= 187 -'
= lDe -' P.l:QRG MACRO TO RESET THE INS1 RltTION LOCRTION COIJlT[R
= 11Y.) i
TO THE nr.:ST rllE[ LOCATION ON TIE FIRST PAGE IIODUI.E WILL
FIT WilHItI.
=190 -'
= 191 R[ORG PlACRO LOCHTION
= 192 $5AYE GEN
= 193
ORe
LOCATION
= ,194 tl\'ESTORE
= 19'5
ENDII
= 196 ,
= 197 ; rOOCDU(
"AeRO TO rIt(l fI PFIOC OF ROI'I
= 198 ;
IflICII TIllS BLOCK or CODE WILL fI1 WITHIN
= 199 COOCDLK I'IfICRO
LENGTIl
= 20e '-'lENGTH 5['1
L[NGTfI
= 201 IF
IIIGHll
= 243 ,l1f'TABLK
= 244
= 245
= 246
= 247
= 248
= 249
INSERTS ONTO PAGE 3
DflTflBlK IVlCm
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lENGl H
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fIIG1HORGI"G3ilEOOTH-1l EQ 3
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= ~:l i ?SIZE PRINTS A LINE TO lIlE SOURCE riLE (jIYIOO E!LOCK SIZE.
= 254 ;
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= 256 t5flYE (lEN
= 25;'
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= 253 ;
= 25:) i *~,.~~**.j<*'*************************~,******.***********-**
= 260 IF "lENGTII l T SIZE
= 261
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= 265
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= 271
[M)l'I
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= 273 ;
= 274 .;
= 275 i RSOURCE
CHECKS SIZE OF I'RECEDII¥.i BLOCK, PRINTS SIZE 10 . lS'1 FIll
r.($··?START>., f.fIIGI·I(?!'IART>
CODE SP1lCE ALLOCATION
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PGSIZE SET ~.iI'Ci0-800\1
= 279
PCi5IZE SET OR(,'PG1-100H
PGSIZE !..ET 0I\'GPG2'-209f1
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PGSIZE SEl
= 2e1
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=282
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= 283
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=284
PGSIZE 5[1 ORGPGi" 709H
=2S5
= 2S6 $EJECT
=207 $RESTORE
= 283
ENDM
= 2fJ9 $l:.JECT
All mnemonics copyrighted @ Intel Corporation 1976.
1-91
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3
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298
291
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= 293
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= 298
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=310 $
=311
= 312
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= 314 ENDIf
= :U5
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= 316 EhWI
= 317 ;
=318 i ?HJRI'I2 If1CRO
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= 321 $
= J22
= 323
= 324
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= :rolS
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;
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All mnemoniCS copyrighted @ Intel Corporation 1976.
1-94
inter
lOC OIlJ
Ap·55A
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SOURCE
= 455 MXCH I'fRCRO
'1S1f()P
= 456
=457
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=459 ':'UNflR't' MACRO
~"'RTEIt:.1ll
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= 460
= 461 $SAllE (lEN
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=464
= 46.'5
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= 466';
=46'1 MINC IlACRO DEST
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?I..IIflRY INC,IET
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=479 ;
= 471 II[l[C I'IACRO OCSl
?UNIlRY DEC,DEST
= 472
= 473
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= 474 ;
= 475 MDJNZ I'IfICRO DEST, AllOR
= 476
?UNAR't' DEC,DEST
= 477 $SAllE GEN
=478
.JNZ
ADDR
= 479 :m:STORE
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=489
= 481 ;
PlfiCRO I>E5T
= #'.02 I'IRl
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= 484
= 485
= 4~ MRF
=43'1
,i
= 4!l8
=489 ;
= 49IJ MFRC
=491
=492
!'IRCRO
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MACf.'O DEST
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= 493 ;
= 494 MRlC
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= 496
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= 497 ;
= 498 $EJECT
All mnemonics copyrighted @ Intel Corporation t976,
1-95
intJ
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AP·55A
LINE
SOURCE STATEI£NI
499 .:
508 ; ================-------:;--::-:::-====
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584 ; ===========--=====:--=--====--==
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5111 ;
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512 ;
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516,
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519 PSEGLO WU
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528 rINPUl EQlI
1'4
!l21 ;
5<12 i
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524 ;
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; USED AS INDIVIDUflL CONTROL OUTr1JTS fN) BREAK LOGIC
; IHIJIHJRDER ADDRE~S AND ADDReSS SPP.CE SELE(;lION
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529 ENBLNK lQlJ
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531
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m
0018
8828
5j4 CLRElfF [00
535
t>36 EPRSET EQU
537 I'IODOUT EQU
88OO1.9OOC
08011188eB
li!II1e811ooe
538
539 lTYOUT EQU
549
541 ;
01900000B
; r10 - III ENABLES BREfl{ ON BkERK RAIl OUTPI.Il SIIHl.
,P11 .' HI ENflBLES BIED
542 $EJE.CT
All mnemonics copyrighted @ Intel Corporation 1976.
1-96
inter
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AP·55A
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545
'546
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551 Me
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553 Mf'USEL [()I.I
554
555 [xrOON [QIJ
556
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1-97
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341;
844
845
846
847
0002
0003
0004
0006
,:
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"
: *~,** ~****t.*~.**~.****** ~.,***********:~******************",***~
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066+
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S90 DECLBRE UlSW.".IIB1
; HOLDS KEY POSITION or LAST KEV DEPRESSION DUEtTED
907·1
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911 OCCLIlRE CURDIG. RIl1
; HOLD!> "OSITION or NCXl CHAARCTER "iO BE DI~'LAYED
928+
WRDIG SET R5
n2 DECLtlRE m'rLG,f~B1
;FU1G TO DrlECT WIlEN AlL Kl."S f1RE. f~[UFlSE[l
949+
m'FLG SET R6
:153
; (k'EGI:;1~ ? NOT USED I'Ok Pkli'lflR't' MONITOR)
9S4 ;
95S ,; ******,~***:~****************;,**t******~,*********************
956 tEJ[CT
All mnemonics copyrighted @ Intel Corporation 1976.
1·99
Ap·55A
LOC OOJ
LINE
SOI.Jl<'C€ S1 ATEIOT
957 ;
958 ,*1-***.*i:*******.****.*~:*~'*******~.*
0920
80'.:1
0922
11023
0024
9025
0E!2G
0027
9II'.IS
0929
902A
002Il
002C
002D
802[
0021·
0030
9831
0032
0033
0034
0935
1l03G
00:>7
963 ;
YA DECLfft: [PAce, Rrd'l
; !:ltJ'flfJl IN 111' FOIl EF' f1l;CUl'lULf1TOr.
EQU 32
969+
~I'ACC
973 DECUiRE EPf'SW, ~'AM
; STORAGE IN Mr rOR EI' PROGRflM STATUS WORD
97(:+
[PPSW mu '13
932 DECLARE EPm!!?, ~RI1
; SlomOE IN MF' rOf.: [f' T1I'1EI"ICOUNU:I< RlGIS1ER
907+
[F'Tl~
E(lt)
:>4
991 DEcu:rE EPRS,~:FlI'I
' SlORfiGE IN Mr rOR EP FlEG 15Ttl1 0 OF BRNK {j
E.(JU 35
996.
El'\':0
1000 DECLARE EPI'CLO, (.'fl!'1
; S1OI1FlGE IN 111' rOR LOW VI'l ( or EP rROGRAtI WOOER
ErpCLO EOO 36
1005+
109~ I)[CLA~ EF'PCfII. FAM
'STOIIfli.lE IN 1If' FOR HIGH NIBBLE OF EP I-'~OORfII'1 COUNT!:./.:
[/'PCllI mll :)('
1914.
. rRROMETER 1 FOR <,;EPIAL LlN~ Df11A RflTl G[NERnTOR
1018 DECLfIFlE' HBITLO, Ff1'"
1023+
HBITLO E'.l1J 38
,PMllM[TEI1 2 rOF 5E.RIAL Ll~ DMA RATE GENERA10R
1021' DECLflRE flS ITIi I ,PAl'!
1032·.
f:CITHI EQU '.'
; rfWflf'l T[P f Of.' AUTo-STI;P flN(l AUl 0- BREflK SlQUENCIt«i wnn:
1936 ~CLfw.C DSPTlti, rAM
DSPTII'I [QU 4ij
184H
1845 DECLARE IlERSNQ, RAM
' MON ITOr;' '.'EP~·I ON NUI1BEJ<
YE~SNO [QU 41
t05~+
(UNUSED)
1054 OECLME I-IREGA, RnM
. f:REGil EW 42
1{!5~+
(uPUSED)
1063 OCCLn~'[ IIREGD, RAM
196(a
. IlREGC EQlJ 43
(lJNI.)<'.1:D)
;
107<: llECLAr;'E flREGC,lIfl1'1
i07?·}
HREGC EQIJ 44
(1HY'.1:D) .
1981 OCCLfif HREGD, RrlM
1986-1
BREGD EGU 45
(UNUSED)
1090 DlCLflJ;'l 11RE1lE, FAM
i
1095.
flREGE [00 46
(UNIJ<~D)
11!99 DECLARE 1fREGF. RAM
110H
HREGF EQU 47
,f'Rll'IAR~'. ComlND Slr~TINGI'IE.t1OR'" HOOR135 (L~ INTE)
1100 DECLf1RE SHRLO, Rrd'l
-•.
.
111J+
SI'IflLU
EQU
1117 DECLARE SIflHI, RAM
1122'~
SMAIl! EOO
1126 DECLflRE EI'IflLO, RAil
1131+
lIRO HllJ
1135 DECLAI1E· EI'IAI-Il.. RAI'I
1148+
EI'IflHI [QIJ
1144 DlCLARE I1El'II..O, RAM
I1EIILO EW
114'+
115:1 DECLARE MEltl!, RM
115tH
MEIIIII EPU
1162 DlCLARE ElCODE. Rf1I'I
l1G'?+
BCODE £:QIJ
1171 DECLARE TYPE, RflI'I
EQU
TI'PE
1176+
48
; PRllf'oRY ComlNl>
~TARIWO
MEIU\' flOOK'l!>S (HIGI: BYlE)
49
; PI"IMflk".' C.IJMIIANI) ENt'IN(;
I'IE~\'
ADDRES::; (LOW al'TE)
50
; PRIMAt;",' COMMANI) ENDING MEI'IOR\' ADDRE.S!:> (HIGH BYlD
51
; UIIRD PWSlI? PRRAMETER & HEX RECORD ADDRESS (LOW)
S2
; TIII~D PfP.SER PflRAMEW:': 8 HLX RECOOD AOORESS (HIGH)
53
; PI1II'1flR't' COMMAND NUMBER FROM rff;:5[R HlBLES (lHJ)
~
; f'RIMfIRY COi'II'IAND I'IODlrIER/OF'lION (0-5)
55
All mnemonics copyrighted © Intel Corporation 1976.
1-100
inter
LOC OBJ
9939
9931l
993B
993C
993l)
993E
OO4Il
0041
1l!l42
9843
994[
Ap·55A
LINE
5tUICE 5TATB1[NT
111l1l DECLARE /lJI'tON, ~'flI'I
1185+
NlKOO [QU
11e9 DI:(.tflRE OPT! ON. RflI!
1194l
OPTION EP.U
1198 OCCLR~E r£XTPL, RAM
1293+
IEXTPL EQIJ
12117 DECLflRE KBOEUF, RAM
1212+
KOOIllf EOO
1216 DECLRRE KEYLOC, RAM
1221+
KE\'LOC EQU
12'~S I!lCLARE ~PTS, RAM
1230+
NREPTS lQU
1234 DECL~ fI<"•..IWL Rf1I'I
1239;·
flSflY[
EQU
1243 D[CLAPE RDELRI', R!iM
124fB
RDELfll' [QlJ
1252 DEGlfiRE STFTMP, mM
1~7+
STRTI'IP EQI)
1261 DECLflRE BlfrNl, RAM
12(,(:+
BlfCNT EDIJ
1270 DECLRR[ RECTI,!" RAM
1275+
R£CTYP EQI)
1279 OCCLARE B, RAM
; IR<. IM'IOCR or PflRMTERS PUOWI:D FOR SELI;(;TED CO/I'IAN)
56
; II«X f'OIN'IER lJS[D IN S£mCllIN6 rARSER TABlES
57
; ClfARACTER
f"~ITION
rOR DISPLRI' UTiLlHES TO WRITE Pl.Xl
58
.; rtlSIl ION or 1((\' OCBOlllCED BY SCAlflING stfJRWTIPl.
~9
; IM:R[tlEN1ED
ns
; KEEPS TRACK
or SUCCESSIVE REnDS or SAI'IE I([I'STROKE
69
SlJCCE!>SIYE KEY LOCATIONS SCANlED
(;1
; HOlDS OCtltU.ATOR WIUJE DlJFINIi SERVICE RotJl INE.
62
; (.'(UfiER DECRDlENTED WIIlN flUTO'SlEP OlLfl'l' IN F'I\'tG.'ESS
(;3
; IPllEX POINTER FIJ<:
DI~LfiY
GflflRftCm: STRIN!i ACCESSING
64
,COUNl or llt1TA BmS IN llEX FORI'IflT RECORO BUFFU:
65
; lYrE OF flEX FORI'Ifll RECORD (9 OR 1)
E.6
;!llT COUNlER FOR flSCIl !>ERIP.L 110 UTILIW SlllROUlIPES
B
EQIJ 6r
; CHARriCTER BEING SHIH[J) DURING SERIAL 110 rROCESS
1288 DECLARE REGe, Rfil'l
1293+
REGC
[til) C8
; COUNTER IN SorTWfft: DELn'I DAm RATE GENERATOR
1297 DECLARE H, RAM
[00 G9
1392~
H
1306 ;
1284·~
B97 MBlOCK
1311i
1314 ;
1315 MOCK
1319+
1322;
1323 MBLOCK
1327+
1330 ;
1331 SEJECT
:.EGI1flP, ClIflRNO ; REGISTER flRRfI'I FOR DISPLf''t' PfllTERNS
5[GMflP [00 79
O\IIJUF,OVSIZE
; LOIHIFDlR IJSER PROGRAII DURING PHNHIONITOR OVERl/lYS
OYBlf /:.QIJ fS
HEXBIJF, BlfLEN ; ALLOCATE BLOCK or RAM I·OR lJ<.A: AS HEX
liEXBIJF EQIJ 191
All mnemonic. copyrighted © Intel Corporation 1976.
1-101
REC~D
btfFER
intJ
lOC Oil)
0300
0300 00
0301 00
0:;02 00
AP·55A
LINE
S(lIJ!CE STRTEI'[IIT
1332
13:>71
1341 ; INVf1LS
1142,
134:$,
1344.'
1345 ,
1346 INVfll5:
DATflJlK 4'1
1347
ORG
INITIAL VliLlIt
====== .:::.==
DB
00H
9393 a3
9394 00
1350
0:ros 00
B51
00
DB
00
00
DI:!
!J31l(; 00
0307 01
0308 00
0309 00
0300 00
031:10 00
030C 93
9500 04
B39E 20
039F 25
0310 00
0311 00
0312 00
0313 00
8314 00
0315 00
13316 00
0317 00
0318 rF
9319 OF
031A 00
031B 00
1352
DB
1353
1354
00
~!31C
~l31D
031E
031F
0329
13321
13]22
3023
8023
00
04
01
00
a3
IT
00
1348
1349
DB
1355
Of;
1356
DB
1357
135f.)
DB
DB
1S59
1369
1361
1362
1363
1364
1360
DC
DEl
DB
DB
DB
Oil
DB
DB
DB
DB
DB
00
DB
DB
DB
00
DB
DB
DB
00
DIl
08
1366
1367
1368
1369
1370
1371
1372
1373
13i'4
1315
1376
1377
1378
768
Tfll)lE OF CON::;Tf1NT~ 10 BE LOAOCD INTO ~ INTERIR. f RAI1 LOCATIONS "10 DEFIlED Yfl.OCS.
INIT: SlL
ROO
Xl'COO[' 19
i'IOY
Xl'TEST
CALL
A
CLR
lIO\II)
PSE(llO, fl
PSEGlII, R
IUID
RI!, 11AH ; START AT 1/01 (REG2) = RflII LOC lA1I
i'IOY
R1, ILOW NOVRLS
lIlY
R2, ILOW INYfl.5
i'IOY
A,R2
INITLP: i'IOY
=1497
=1498
=1499
=1410
=1411
=1412
=14B
=1414
=1415
=1416
=1417
=141B
=1419
I'IOYPJ A,~
@R9,1I
=1429
I10Y
=1421
INC
R9
=1422
INC
k2
1d.,INIlLP
=1423
DJNZ
=1424
STRT
"I
=1425
CALL
EPI.:RK
R9, ILOW(OV1BAS+QYSIZE)
=1426
i'IOY
=1427
Cf1Ll.
OYlOAD
=1428
CALl
COI'IFIl
R1,ITI'PE
=1429
MOV
@R1
=1439
INC
=1431
CftLl
INCSI'IA
=1432
au COIf'll
PL 1lflERJ
; WIlTR I'EPIORI' I100IFIERl
; [ (;LCflR/PREVIOOS 1
; [IJ'LOAD C!1II1AND J
;[AU10S11P I1OOIFIER]
; [PROGRAI1 I'(~I' MQ() IHER J
;[REGISTER ME.~' rfJDUIERJ
; [FORI'IfITTED DATIl OUTPUT COI1IflHI) J
; [GO FRm REstT STATe t'atlAN»
, [GO COItlRNri J
; [~XflI'lINE/I'IOOIF',' COI'IIfN) J
; [SET BIlEff(POINT COI'II'IflM) J
; [CLEAR IlREAKPOINT COI1IflN() J
EQlJ
(QU
1911
151-1
1111
100
WI
tr.H
;[f'ROORRI'I BREflKf'OINT 11E~' I'IODIFIERJ
.; [DATA BR£AKPOINT MEI1OR'r' I100IFlER 1
; [IIARDWARE REGiS1ER I'IEI1ORI' MODlFIER]
;[lmllOUT CREAKf'OlNTS I'IOOlrIER]
; [WITH ERl:AKPOINTS ENRIlLEI> 11OO1f1ER]
;(SmGLE STEP I'IOOIf lERl
(00
Eoo
EQU
EOO
EQU
EQlJ
EtlU
EQU
Eoo
EOO
EOO
(00
EQU
EQU
[00
EQU
mu
[00
EQlJ
EQU
All mnemonics copyrighted @ Intel Corporation 1976.
1-105
Ap·55A
LOC OOJ
9929 111"01
ll02B "(401
Il020 2381
8Il2r 3400
001114EC
!Jell f'B
11834 DJ13
11836 eG2S
11838 EC23
118311 B936
1183C B1111l
1IIl3E B937
9840B1lt11
9842 FC
11843, EJ
11844 B28C
11846 00
1184i' C652
11849 Fe
1184ft 0303
!I04C RC
B936
II84F 11
l1li58 11442
11841)
0952
11854
0055
11857
B936
F1
011D
3482
LItE
!am STRTDENT
=1526
COOEBLK 168
=1531+
ORG
41
:1535 ;lIAIN OUTPUTJtE5Sf&:(C(MN)~T)
CfLL IIf'ULIJVTE(KEY)
=1536 ;
=1537 ;1Ifl1N2 IF THE KEV=lND GO TO IfllN.
=1518 ;
=1539 f1flIN: IIOV
XPCOOE.11
=1540
CflL
:0
ICTRE EXHlIUSTEDI
=1552 ;
IF CTAIl< ITIf')=KEY GOTO IfIIIIl ICOItIflND lNTRY f'Wt> IN CTAB!
=1553 ;
ELSE
lllf':=lTIIP+COltIRIlUNlR'l'..sm
=1554 ;
BCOOE: =!lCOOE+1
=1555 ;
ENDIfIILE
=1556 ;
GOTO !»'OF
=1557
lIlY
1111', ICTIlIl
=1558
ItIOY
1lCODE, ZlRO .
=1569+
IIOY
Ri, ISCOOE
=1570~
=1574
=1585+
=1586+
=15911 FINDOf'.
=1591
=1592
=1593
=1594
=1595
=1596
=1597
=159S
=1599
, =1699
=1601 ;
=16112 ;
=1(;03 i
=1604 ;
lIlY
lIllY
IlO\l
lIlY
lIlY
1IOYI'3
JaS
XRI.
J't:
lIlY
fI)()
IIOV
lIlY
(IR1, lZERO
TYPE, Z[RO
rd., ITYf'[
IW,'O
FI, ITW
A, @fI
I£RROR
A, KEY
IfIllfI
A, 1TIIP
ft,lCOllSIZ
ITIt', A
R1, IBCOOE
@Rj"
It«:
@R1
.mP
FlNlOP
OOTI"ULI[SSOOE(5TRCOI'I«(;(;oo(»
I: =H1
OPTION:::IEII(I>
=1605 ;
I :=['~1
=1696 ;
NO_(J'J'ARAI'IETERS: =IEIf( I)
=1607 i
1:=3
=1608;
fl,BCOOl
=1689 I'IAINfl:
Ri,IIlCOOE
=16113'1
fI,@R1
=1619+
n,15TRCOI'I
=1623
=1624
OOTCLR
All mnemonics copyrighled
@
Inlel Corporalion 1976.
1-106
I*fmf'T FOR
T~ C~£NT
UJI/IFII)*I
infel'
LOC 00,]
9959 lC
0Il5A F(;
0058 E3
905C 1i939
005E fl1
W5f 1C
0060 rc
OOC1 D
9062 89313
9064 R1
0965
0067
0069
006B
006C
006E
B9BC
fl8:?0
0000
18
E96!1
14EC
9079 8939
0072 1"1
0073 nc
00;>41C
0015
0076
0077
0078
rc
E3
97
F7
0079 77
89lA Dr,
0078 C693
0071) r687
0071 LOS37
0W1 H
OOG2 17
0083 A1
9984 1C
0085.0475
0087 B937
.0B89 B100
AP·55A
LINE
~CE
=1625
=1626
=1627
=1628
=1641+
=1642+
=1646
=1647
=1648
=1649
=1662t
=1663+
=1667 ;
=1668 ;
=1669 ;
=1670
=1671
=1672 I1fllNB:
=1673
=1674
=1675
=1676 ;
=1677 .
=1673 ..
=1679 ;
=1680 ;
=1681 "
=16B2
=1(91)+
=1699'1
=1i'12+
=1715
=1f1C MAl NC1'
=1732~
=173(;
=17S7
=1f38
=1739
=1749
=1741
=1742
=1743
=1748+
=1749+
=1?S3+
=1?S8l
=1761
=1762
=1763 ..
=1764 i
=1765 "
=1766 MAI1ID1
=177(-1
=1778+
=1782
INC
I'lO\l
I'IOIJF'J
!II1OV
!'IOV
rov
STflTEMENT
ITttP
R, 1lI1f'
R,@fl
INC
mil'
I'lO\l
A,11111'
fI,@A
MOVr3
MI'IOV
/'fOIl
MOV
; GEl OPTI ON PO INrrR
OPTION, A
R1, IOPTION
@R1.A
OCT NO OF f'fiRfll'lETtRS
NltICQN, A
R1, lNUl'lCON
~R1, n
rnr.rn;TER_EtHER(9=)5). =9
MOil
r1,1t;
/'IOV
/'IOV
RII,ISMALO
~'0, .99H
INC
OJNZ
CALL
R9
1<1.I1flINE
i E.ACH I'fiRAI'I IS 2 INl ES
; START (f PARflI'I E'.tJfFERS
INPKEY
WlIILE KEYOMEM(OPTHRliTI'P[)[ 6-9] DO
IF t1El'f(OPTlON+T'IF,[)[ 7]=1 GOTO MAlND1
TYPE .=TI'I'E +1
ENDIoIIHLE
I1I'IOY
MOIl
MQI}
MOY
INC
MI'IOV
MOIl
I1OW3
(;LR
f.'L(;
RR
XRL
J2
JC
MINe
MOY
I'lO\l
INC
/'lOY
INC
JI'/f'
ITMP, OPTION
Ri, 1I000TI ON
A,@R1
ITMI"A
Imp
A, ITI'IP
A,ITMP
A,@A
C
A
R
fl, KEI'
''lUND
. STRIP BIT SEVEN INTO CAF.'k1'
1'Ifl1M>1
TI'PE
1,:1, '1i'P~
A,@Rl
A
@Rl,A
ITI'IP
/'tIlINC1
MODIfIER NOT FOUNO so RESET TlfE INOEX TO DEf'AUlT CASE. (ZERO),
MMOV
MOIl
MOV
MI'IOV
1\'P[,ZERO
R1.ITi'PE
flOR1,IZERO
A,OPTION
All mnemonics copyrighted © Intel Corporation 1976
1-107
inter
LOC (J)J
I!8SB
~39
Fl
908£ B
800F 3494
0091 049E
998()
!lII93 8939
999S Fl
999(; B
8897 8937
9899 61
889R3484
989C '14EC
Il99E 0C0II
0000 2330
00A2 6C
llIIfl36C
88fI4 AS
IlIIA5 14C9
9IIfl7 FGBlI
Il0fl9 1C
09RA 8938
9IIRC F1
9IlAI)
87
80RE R1
818· C68ft
8IlB1 FB
0002 D313
9084 CGBf1
88B6 14EC
8IlB8 84fl8
09BC Bfl01
8IlBE 249A
8897
AP·55A
LINE
SOI.RCE STRTEllENl
=1791+
I'm Rl,IOf'T1~
A,@Rj,
=1792+
ItOY
=17%
ItJ\IP3 fl,flIfl
=1797
CALL
OUTIISG
=1798
Jt1P
I'tRIN80
=1799 :
=18911 i
CfU OOTPUT..I£SSOOHImIFIl'R)
A, OPTI(Jj
=1881 /ifill{) ItKJY
R1, 'Of'TI(Jj
=181IH
IIOV
1101,1
A, I!Rl
=1811+
=1815
IIOYf'J A,@fl
R, TYPE
=1816
~
=1822·t
Ri, .TYPE
IIOV
=1823+
fl, 8:1
flOO
CAlL
=1827
OOTIISG
=1828
CIlLL
1If'KE\'
=1!l29i
ITl'IP,10
=1830 I'IAIN£lII: MO\I
A, ISIIILO
=1831 ml1NB1: ItOV
A,ITI1P
=1832
ADD
A,ITI1P
=1833
roo
R8,R
=1834
\'lII/
IIffl)F:
CAlL
=1835
JC
Cl'lDINT
=1836
=1837
Illf'
INC
=1638
1m
RL INlJII:ON
A,~1
=1839
ItOV
=1840
R
DEC
1R1, A
=1841
IIOV
=1842
JZ
CllDINT
/{I\I
A,KE\'
=1843
A,IKE\'END
=1844
XRL
Cll[)INT
=1845
12
=1846
CALL
INPKE\'
=1847
JIll'
KAINBl
=1848 i
=1649 i CllDINT ENTER TI£ ctM1N) PROCESSOR WITIl:
=1S511 .:
BfISLCOOf.=TfE KAIN rotIfIN) noPE
=1851 i
WF'E"'SUBCOIII'IAND TYPE
=1852 ;
PARRl'lETER(1)=rIRST I'IDDIIESS
=11.'53 ;
PRRfI'IETEI!(2)=SECOND flOORESS
=1854 i
PAm'ETERO>=DATA
=1855 CIID INT: JIt'
lIf'LE"
=1856 i
=18~7 i 1'l"RROR [~ ENCOUNTERED IN /lAIN PfJ.SINl kOlITINE.
.=1858 IlERROR: 1m
LOOTA, 11 .
=1859
JII'
PERROR
=1860
SIZECHK
=1863+ SIZE SET 151
.=11l64t:
=1L'65ti*-"'-*----*******"''*****---**
=1S74 '$EJECT
All mnemonics copyrighted @) Intel Corporation 1976.
1-108
inter
LOC
OOJ
8323
AP·55A
LINE
5ru!C(STnTEtENT
=1875
=1889+
=1884 ;
DATfllLK 59
ORG
SIB
=1885 ;
=1886;
=1887 ;
=1!J88 ;
9923
0093
8323 if
0324 ~F
8325 91
8J2G 1E
11327 49
832tl 91
8329 18
1132A :sf
832B 83
932C 1C
8J21) 3F
832E 92
832F 18
8:n83F
8:m 92
11332 14
8m 3F
8334 Il8
8335 lIE)
11336 46
8337 91
8lla OC
8m 46
9331\ 01
83Jl1 11>
113~ 49
SJID Iil8
833E IT
*****_****************************>I-"*****l,*****************
TflBlES
F~
PAR'.1.R
=1SC9 ; *****.~********-****-_*_***********************.*
=1fJ90;
=1091 ;
TIE C1AB TABLE CONTAINS (C1JISIz) EN1RIE5 FOR EflCll COI1I'IflND. TIl: PlANING
=1C92 ;
or THE Eimms IS flS FOLLOWS:
=1C93 ;
=1894 ;
ENTR'l' 8 COI9IftND KC'I' TO INITIATE
=1895 ;
ENTR'l' 1. POINTER TO HIE LIST or OPTlCtlS APPLICAELE 10 THIS COittANO
=1896;
ENTRY 2. NUMB[R OF NUI1ERIC f'ftRlllETERS I~QtJIRED "'..,. 1Hl rowHl
=1C97 ;
$ AN) BFFH
EQU
=1&'98 CTAB
=1899 COMSll [QU
1
=1989 ;
K(:\'i'IOI), LOW OPTAB1,1
; EXAI!
=1991
00
.=1992
DB
KEYOO, LOW 01'1003, 1
;GO
=1983
DB
KEYFIL, LOll (J'1A1l1.3
; fILL
=1984
OB
KEYL5T, LOll (FTAB1,2
;iXJI'IP
=1985
l>B
KC'I'REC, LOll OPTAEL 2
; RECORD
=1986
=
DB
KEI'REL, LOW OPTflB1. 8
; kE.l.UAD
=1987
OB
i8
991B
9119
Il11A
9118
811C
991D
9110
911E
911f
9129
9121
9122
9123
9124
912S
31
37
3E
44
46
49
48
4E
51
54
57
SA
so
9926
9126 SF
9127 61
912!l 63
=199lH
=1$'94 PRNT2:
=2004i
=2Il98
=29119
=2919
=2911
=2916+
=2917+
=2921i
=2926+
=29'.!9
=2939 PRNT1:
=2931 i
=2932 STRUTL
=2933
=2934
=2935
=2936
='.!037 STRmt
=2931)
=2939
=2949
=2841
=2942
=2943
=2944
=2945
=2946
COOEBLK 139
ORG
2:!6
OOlPUT (If: (f' F~ UTILlW DISPLA'/ PRM'TS (LEFT JUSlIFILD)
fl.'C(RDII«l TO ACC ctIlTENTS (8-3).
CLEff( DISPLAY All) OOIPUT CIflRACTER SlRIIIl STAATII«l
AT Tl-E flOORESS POINTED TO I:IY BYTE itT roDRE.SS IN flCUJU.RT~.
~IIf. TO COP\' n STRIIIl (f OIl f'ATTI:RNS Fm! ROt! TO Tff.
DISPLAY R[GI!.TERS.
5TRIIIl SIl.ECTED IS DETEF.IIII£D 8\' nee raN cnw.D.
ON ENTERIIil OOTIf'..G, ACe CONTENTS lIRE USED TO ADDRESS A Il\'TE IN A
LOOKlf TABLE ON TIlE ru:RENT PflOC IlllCiI CONTAINS
f~SS OF
A STRING IF SEGl'lENT PATTERN llflTA 8\'1 ES TO DE PRINlED ONIO Til.
DISftAl'.
TIE END OF TIlE STRING IS IN>ICHTED IfIEH 0I17 =1
CALLS SlIBROUTII£ 'IG)ISP'
TO flCTlRLY EFFECT WRITING INTO Tl-E DI5PLAY REGISTERS.
ft, 1STRU1L
ADD
CLEAR
CALL
A,@fl
i'IOYf'
5TRTIf', A
III'IOV
R1, ISTRTI'IP
I10Y
@R1,A
MOV
; LOll) NEXT CIIRRflCIIR LOCATI ON
A, STRTII'
I'KJY
Ri, ISTRTI1P
ItOY
A,@R1
i'IOY
A,@A
i LOAD BIT PAllERN IN>IRl::CT
KOVP
JB7
PRNT1
; OUTPUT TO NEXT CllARflClER POSITION
CALL
II>ISP
STRTI1P
; I~X POINTER
I'IINC
R1, ISTRTIIP
MOY
fL@Ri
I10Y
A
INC
@R1,A
I'KlV
JIf'
PRNT2
II>ISP
JII'
iDONE
n:I,
EQU
1>8
DB
DB
DB
EQU
DfJ
DB
DB
DB
00
DB
DB
00
DE;
=2947 STRME" EQU
DB
=2848
=2tI49
DB
=2959
DB
LOW $
LOW(DERRQR)
LOW(~)
LOII(DRUIO
LOW(DBPNl)
LOll $
UJII(DIIOI)
LOW(OOO)
LOW(DF1LL>
LOW(DLST)
LOW(DREC)
LOW(DREL)
LOW(DSB)
LOW(OCS)
LOW(OOR)
LOll $
LOW(DPRfllt>
LOW (DDAI'IEI'I)
LOW(IJRI1)
All mnemonics copyrighted © Intel Corporation 1976.
i UTILITY
;U1ILlW
; UTILIW
i UTILl T\'
I'ESSAGE
I1E5SAGE
I£SgJOE
I£SSIU:
9
1
2
3
ADDRESS
AI.JI)R[SS
roDRESS
ADDRESS
i I:flSIC COI'II'fAN)
9 RESPONSE fIOORI:SS
; !!ASIC COI'IIflN) 1 RESPOOSE ADDRESS
; BASIC COI'IIfH) 2 RESPONSE ADDRESS
i ElASIC cat1AND 3 RESPONSE fIOORESS
i BASIC CO/II'ffl) 4 RE!.PONSE ROORESS
i BASIC COItIAM) 5 RESPONSE flIlORESS
; BASIC COIfIAN) 6 RESI'ONSI: flD£*.tSS
; BASIC COI'\I'IIlN) .( RESPONSE ADDRESS
.; IlfISIC COI'IIfH) 8 RESPONSE RlIlRESS
; DATA T't'I'E IIlDIFIt:R 9 RESPIWSE flDI)RESS
; DlfTA n'PE IQ>IFIER 1 Rt:SPOOSE roDRESS
; DATA lYrE IIODIFlt:R 2 RESPONSE AOORESS
1-111
inter
AP·55A
LOC (.(jJ
LINE
11129 69
=2051
=2952
=295J
=2Il54
=2855
=21!56
=2857
=2858
=2859
812A 65
912f) 67
9II2C
ei2ca:
11121> 60
II12E
E}"
1112f" 72
11139 75
!lOURCE STRTEI1ENl
DB
DB
DB
s) RGOC
1;00
DB
DB
DB
00
D8
L~(DINTRG)
L~(DPRIJRK)
LIII(OOlll'lJ:IO
LIII $
L~(DI«lIRK)
L~(DWBIIKt
LOII(DSS)
!:0II«()Pf\)
LOW(DTR)
; DATA TVf'l IU>IFIER 3 RESPOlSE fWRESS
; DRTA TYPE IUlIFIEk 4 RESPONSE ROORESS
; llfiTR TYPE IUlIFlER ~ RESPONSE ftIDRlSS
;EXECUnOO ~ IIOOIFII:R
; EXECUTION ~ IUlIFIER
; EXECUTION IG)E 1IOO1fIER
.: lXIDJTION I'IODE IUlIFIER
; fXCUTION I100E IU)IFIER
=2868 .:
0131
0132
0133
0134
0135
01JG
79
50
50
5C
50
C0
1I1J7
013S
01J9
II1JR
00
76
GD
79
8flB 40
1113C 66
!lB!> E7
1113E !l0
!l1Jt 41!
0148 50
01411C
11142 54
11143 (,'0
8144 7J
0145 B9
=2061 ;
=2062 ;
=21163 DEf(R(JR:
=21164
=2065
=2066
=21167
=2968 .
=2069
=21170 DSGNON:
=2071
=2072
=2073
=2074
=2075
=2076
=2077
=2078 DRUN:
=2079
=20C9
=2081
=2982
=2003
=2084
=2085 OOfm:
=2086
=2007
UTILITV OUTPUT I'ItSSFlGES
00
00
DB
DB
00
DB
00
00
DB
00
DB
DB
DB
DB
00
8111101118
1I101110ilefJ
111010000[1
010111001)
0101001l1l8
11001111008
i
'R'
j
'0'
;
;
......
.~.
.
00000008B
011101198
01101101B
011110111[1
01000000B
011001100
111001118
;'
~
,." "
00
1110001l1.10B
1I1010001l1l
01101118
010181!l11E
111l1l01100B
DB
DB
11111811118
101111101B
DB
00
00
; IE'
; 'R'
.i
"H"
; '5'
; IE"
ii_"
; 14"
; "9. "<1")
; I.'
; IR'
i 'U'
; fiN'
; I .. •
;ara
; ·C.•
=2088 mECT
All mnemonics copyrighted @ Intel Corporation 1976. '
1-112
II
1
2
3
4
infel'
LOC OI)J
9146 ·,9
0147 J9
0148 F4
8149 31)
914A De
1l14E 71
814C :l0
014D IlS
014E. 38
1!14f 60
9158 Fa
9151 3E
0152 7J
915J Be
0154 5E
9155 ~4
9156 sa
0157 6D
0158 78
9159 Fe
91SA 39
015E J8
915C FC
01SD JD
915E 00
AP·55A
LINE
SOURCE STATEIf:NT
=2089 ;
=2990 ;
=~1 ;
=2092 DMOO:
=2093
PF:11'flRY
C~
[Jf;
911110018, 001119918, 11110190IJ
, "EClt •
=2094 000·
=2095
DB
801111818, 110111888
; -GO.
00
011108918, 081191.!1!0E), 10111000B
; 'HL.'
=2098 DLST:
=2099
DB
00111000B, 911011818, 11111988B
; 'LST. •
=2190 DF:EC:
=2191
00
901111100, 91119811E, 101111l09B
j
=2102 DREL:
=210:1
/.l£I
010111100, 9191919011, 19111000B
; aDNl.
=2194 DS&.
=2105
OB
0111l11018, 011110Il00, 11111100£:
; "SIB.•
=2106 DeC:
=210,
D8
0811111011), 00111900B, l1111100E
; 0ClO.
=2108 DGR:
=2109
OIl
1l0111191B, 11919001lE
i
=20% Df"ILL:
=21197
=
RESPONSE STRING f'RTTERN$
=2119 $EJECT
All mnemonics copyrighted © Intel Corporation 1976.
1-113
u
HlPL.•
RGR.
II
II
II
Ap·55A
lOC OBJ'
8151' 73
0168 00
8161 5[
0162 F7
916:> 50
8164 00
9165 73
9166 rc
81e? 5E
9W) FC'
-8169 76
8161l 00
816B 54
816C Fe
01GD lC
81GE 00 .
91er
ro
LINE
~
51RTEI'IENT
=2111 ;
=2112 .;
OOR',' srACE IU)IFIER OPTION
=2113,
=2114 DF'RI1EM'
=2115
01119811[1, 119100e00
=2116 OOAI'IE.M:
=2111'
~5PONSE
STRINGS'
,"PR'
910111100, 11110111B
.' -Dn. ..
8191I!BB0B, 10111101B
,'RG.•
91111!9118, 11111100B
j
DB
019111198, 111111008
i.OO
=2124 DI NTRG .
=2125
00
911191100, 119100WB
()[;
=2111: DRI'I:
=2119
'00
=
=2120 DF'RBI':K'
=2121
DB
=2122
=2123
=2126
=2127
=2121:
=2129
=2139
IPr:! .•
~I~'
;
RESPOI6E MESSAGES rOR GO CONI) ITI ON MOO I FJ t~.
;
;
DNOIlRI(:
; 1m
019191000, 111111900
I>B
II
-
M
=2131 IIIIIlRK:
=2132
DB
911111008, 1111199008
; "BR •
=2133 D!;S:
=2134
DB
011911918, 91191101[;, 11111000B
; 'SS1 •
=2135 DPA:
=2136
DB
01110111[l, 01111190E, 1101B0II0IJ'
, "flBR. "
=2B70TR:
=2138
00
01110111B, 011011!!1El, 11111B90B
; "AST.•
9170 E;[)
8171 Fe
0172 77
9173 7C
9174 00
9175 77
9176 GI>
11177 F8
9978
=2B9 ;
=2140
SIZECIi<
=214J+ SIZE SET 120
=2144+;
******************************-***************************
=2145+;
=2154 $EJECT
All mnemonics copyrighted © Intel Corporation 1976.
1-114
AP·55A
LOC OOJ
1IOC9 97
9OC1 R;'
99C2 B9JS
89C4 rt
90C5 C6D7
911C7 FB
99C892D7
99Cfl 29
89CEJ 47
OOCC 20
9OCO 39
09CE 1S
OOCF 39
9IlD9 3478
99D214EC
99D4 97
991)5 94C7
.0007 FEJ
eros 1>312
000Il C6E!i
900C Fa
9000 1)313
09I)f'
Cf1:5
·9OC1 BAIl2
99E3 24911
99[5 EJ846
9I!E7 8993
00E9 B4f5
99ED fJ3
992C
LII£
sotJ/C(
STATEI'ENT
=2155
Coom.K 45
=21G0+
1]10
192
=2164 ; INI'fIDR 1tf'UT DATIl INTO TI/O"BYTE PARlKTER IlIFFER ItlllCATED BY RB.
=2165 ;
RECEIYl lUDIC KEYS rRCfl KE'I'BOfWW !mIL '.' OR '. '.
=2166 ;
SHIH INTO I€lDRES!; B\.rFEI";
=2167 ;
RE-WRnE I)ISPlfl'r'.
=2168 ;
IF I01BCR OF CONSTIIlTS 1£[1)[1) IS ZERO. t«J 1£1/ I'AfIfft:1U:S ff1E fUM!).
=2169 ;
=2178 IIf'ADR: CLR
C
=2171
Cf'I..
C
=2172
!mY
A.NIKON
=2181+
I'm
Ri. I/lftXlN
=2182j·
I'IOV
1I.@R1
=2186
12
ELSIrt
=2187 1NPAD1: I'IOV
A.KEY
=2100
J84
EL!:.IF1
=21t.'9
XCH
A. @R8
=2199
SIIlP
A
=2191
XCH
A.i!R9
=2192
)(011)
ILI!R8
=219:l
INC
R9
=2194
XCHD
lURe
lI'Dfl)R
=2195
Cfll
=2196
Cfl.L
INPKEY
=2197
CU:
G
Itf'fI)1
=2198
JI'IP
=2199 ;
=2290 ; El!.If1 IF KEY='. I ~ '. I TI£N RE'fmN.
=2291 ;
='~a12 lLSIf1: I'IOV
A..KE\'
A.II(EYNXT
=2293
XRI.
=2294
12
ELSIF2
=2295
I'IOV
ILKE\'
=2206
XRl
A.IKEYOI>
=2207
J2 .
illlF2
=2298 ;
=2299 ;
EL!.E GOI0 PERROR.
=2219 ;
=2'dl
!lOY
LDATA.'2
=2212·
Jl'I'
PERROR
=2213 ELSIF2: PlOY
R0.ISEIM'
=2214
I'm
Ri.13
=2215
CflLL
OOI..ANK
=2216
RET
=2217
SIZECHK
=2229+ SIZE SET 44
=2221+;
=2222+;**-_**_ _ *~**********
=2231 $EJECT
__
All mnemonics copyrighted @ Intel Corporation 1976.
1-115
inter
LOC OOJ
8178 D93A
917A 0193
817C F9
(;8
8171. 539F
9189 96CE
9182 D4D8
91fJ4 Fe
9185 47
9186 5301"
9188 9692
91SA D4D!l
BlOC 2494
81SE D4DJ
!l198
F~
9191 47
9192 D4Dl
9194 F0
9195 D4Dl
0197 93
9920
L1/£
S(XEE
STRTEI'II:NT
COD£BLK J5
ORG
376
=2246 ; ~ tJ1)AT[ OODRESS FIELD
=2247 ;
(LAST nm CHf~TERS OF DISPLAY) WillI flOOfI'HI
=2269
Cfl.L
WOI5/'
=2279
!'lOY
fl, flIR9
=2211
ZIoIlI'
/l
=2272
ANI.
A, tefH
=2273
JNZ
DSP!'I1
"2274
CRLL
MOl51'
=2275
JMP
DSPLO
=2276 DSPIII, CALL
DSPACC
=2277 DSPf1ID: I'IOV
Il, tIR0
=2276
SWAP
R
=2279 DSPf11 CfLL
DSPRCC
=2'.169 DSPLO: I'IOV
A, ~8
=2231
CfLL
DSI'RCC
=22C2
RET
=221.13
SIZECIIK
=2206-1 SIZl! !.ET 12
=2232
=2242+
8178
9170
AP·55A
=2'.!B7{ ;
=2280+;
=2297 $EJECT
***********-_**_*******____**___
All mnemonicS copyrighted C9 Intel Corporation 1976.
1-116
AP·55A
Loe OBJ
8198
11198
1I19A
019C
019E
01!11"
eIRe
IlOO4
Er02
74D1
27
l>7
FEl
01Al D317
01A3 C6I)G
01AS 27
01AC 3400
01r.s FA
I!lA9 041)3
01R!)
01AD
alAr
01El
0182
01114
01£16
B93El
611F
14EC
FD
D3E
9698
0429
LINE
SOURCE STATEMEN1
=22')8
CODEBLK 35
=2303+
ORG
408
=2312 ; r'ERROR .
REPEAT
=2313 ;
OUTPUT J'/[SSAGl:(P~R()IU'ROI'IPT)
=2314 •
OIJTPUHLDATAl
=2315;
CAlL INPUUlI'lE(K[Y)
=231G ;
UNTIL KEI'='a.EIlRt'f'k'EII!OIJ.j'
=2317 RCRflOR' MOil
LI!ATn.14
=2313 PERROI"<- IIOV
XPCOOE••2
=2m
lkLL
xrrrsT
=2328
a.R
A
=2321
I'KJV
P~. A
=2322
II()\/
A. KEI'
=2323
XRL
A.IKE\'CLR
=2324
JZ
E.I1R0R2
=2325
CLR
A
=2326
CALL
OUTUl L
=2327
ItOV
A, LDRTR
=2328
CfU
DSPOCC
=2329
MMOIl
KBOOUF. NEGl
=2340+
PIOV
Rl. IKCDClUF
=2341t
MOIl
@R1. HGl
=2345
CALL
1Nf'1(fI'
=2346
MOil
fl. KIY
=234;'
XRL
fl.IKEI'E/{'l
=2348
JNZ
RERROR
=2349 ERROR.,: JMP
/'lAIN
=2350
SIZI:.CIIK
=2353+ SIZE Sf.T :s2
=2354+ ;
**************',***************",***********************"*****
0200 2306
0202 8936
0204 61
020S 83
8206
er
Irll!7 28
11288 22
021!9 lR
821!fl 11
0200 16
820C 2C
02I!D 2&
02I!E 2(;
82I!r 444f
9211 85
=2355i ;
=2364 ;
=236!J
=2330+
=2384 ; IREM
=2385 II'II'LE.I1:
=2336
=2392+
=2393+
=2397
=2398 ;
CODEDLK 80
oro
512
IIf'lU'[NT COMMfINI)
1l..ILOW(JI'II'TllL>
/'/ROO
A. OClJD(
/'lOll
Rl, .BCOOE
1100
fl, ~
JI'tPP
(ffl
/'lOll
=2399 Jlf'Tl'.t.:
=24118
=2481
=2482
=2483
=2484
=2485
=2486
=2487
=2483
=2409
=2410
=2411
=2412
DIJ
LOW(JTO/'I()/)
00
LOW(JTOOO)
LOW (JTOF"IU
LOIHJTOLST)
DIJ
DB
·DB
00
D!l
00
DB
;
JTOI1O[l: JMI'
;
nOR[c' CLR
LOW(JTOREC)
LOWOTOREU
LOW(COI'IS[:R)
LOW(C~BR)
LOW(JGORES)
foXfl/'lIN
Fe
All mnemonics copyrighted © Intel Corporation 1976.
; r 0=8 ==) lEX FORmT DR1 A DU/'IP
1-117
Ap·55A
LOC OIlJ
0212 B472
0214 0429
9216 5497
0218 042'.3
921A 85
0218 9S
021C B472
921E 0429
9229 8499
9222 W5
9224 9429
9226 8461
9228 BFI99
822!1 442E
922C 1JA01
922E 2304
0239
0232
i!233
0234
8236
0237
9239
023B
El9J7
61
A1
F400
FB
Dm
0230
023F
0241
i!243
0938
0191
OSSll
0090
9245
9247
0249
1r.!4B
024D
C64D
14EC
0931
8199
14C0
E634
0429
LINE
sotnE STATEPENT
=2413
CALL
flFILEO
=2414
JMI'
MAIN
=2415 ;
=2416 J10RR CALL
f:ReCIN
=2417
Jrt'
MAIN
=2418 ;
=2419 JTfl..ST: CLR
F0
=2420
CPL
F9
=2421
HFILEO
=2422
Jrt'
MAIN
=2423 ;
=2424 JTOGO: Jrf'
EPRUN
=2425 ;
=2426 JlOFIL: c/u
COI'IFIL
=2427
Jrt'
MAIN
=2428 ;
=2429 JGORES: Jrt>
COI'IGOR
=2439 ;
=2431 ; CCIIUlR C~ TO CLEAR BREAKPOINTS
=2432 C!JICDR: I'KJY
LDflH1I9
=2431
JIf'
BRKfIL
=2434 ;
=2435 ; ctmSBR COItVlND TO SET BREAKI1JINl S
=2436 COI'ISCR I'KJY
LDftTfl•• 1
=2437 BRKFIL: !'lOY
A..'4
=2438
I'troD
T'lP1J n
=2t48+
I10Y
R1.'TVPE
=24491
AOO
n. @R1
=2455-1
I'1OV
@rd. n
=2459 BRKNXT: CALL
L5TORE
=246e
110\1
A, KEI'
=2461
XRL
A. IKEI'END
=2462
Ji
lJRKOO
=2463
CALL
IWKEI'
=2464
ItIOV
NUI'ICON. PLI.I$1
=2475+
!'lOY
RL INI.JIUtI
=2476+
I'KlV
@Ri. IPlI.I$1
=2489
MOY
RO. ISI'IflO
=2481
!'lOY
il'R0, 19
=2482
I'l'101/
51'1A1H. ZERO
=2493-1
I10V
RL .2ftl1
=2494+
MOY
@Ri.'ZERO
=2498
CALL
I NPRDR
=2499
JNC
DRKI«T
=2""...00 BRl(END· JI'I'
MAIN
=2501
SIZECIlK
=2504·f <:;Ize 51:.1 79
=2595+;
cru
************************************************************
=2506+;
=2515 $[JECT
All mnemonics copyrighted @ Intel Corporation 1976.
1-118
AP·55A
LOC 08J
LINE
=2516
=2531'1
924F
5~CE
STATEl'ENT
COOCBLK 75
ORG
591
=~35
; EXAI'IIN EXAI'IINEII1OOIF'!' I'[~' COItIAND.
=2536 ;
DISPLAYS ME110RV f1ODRE55 SPACE OPT! ON, f'lDDfBS VALUE, AND CURRENT DflTA.
=2537 ;
READ!; 1([','BOflR() fIN) INTERPRETS RESPONSL
024F
as
9250
am
0252 F1
0253 0326
9255 3492
0257 EB31
9259 347C
02".Al 2348
025D D400
lJ25F 14FC
1I261 FA
02(.2
9263
9265
92£6
926!)
47
D4D3
FA
D4D3
14EC
. 926A FE)
9268 9278
II:!6/)
026E
926f
11271
9273
0274
0275
9276
9277
9279
FA
47
5JF9
B675
27
95
68
AA
F409
4459
=2538 ;
=2539 ;
OUTT'1JT_MES5AG( ( (1'II:roR\'_SPRCE_Of'n OH)(SMflY =' (DRTfLBVI E> )
=2549 EXAMIN: CLR
F0
=2541 EXR/'I0: mlV
A. TI'PE
. =255fji
1'1011
R1,ITl'PE
=2551+
MOV
A, @R1
=~55
=2556
=2557
=255lJ
=2559
=2!:>G9
=2561
=25&2
=2563
=2564
=25(;5
=2566
=2567 .:
=2568 1
=2569 .:
=2579 .:
=2571 .:
=2572 .:
=2573 .:
=2574 .:
=2575 .:
=2576 .:
=2'577 .:
=257C .:
=2579 .:
=2589
=2581
=2597+
=2601
=2692 .:
=2693 .:
=2694 .:
=2[.e5 .:
=2696 ;
=2697
=2600
=2(;99
=2610
=2611
=2612
=2613 I,J Er wmt SYSTEM STATUS AND RELEflC...E.
SEQlENCE IS AS FOLLOWS'
IF L1J1tfIND WAS TERIIINffTEl) 8Y TIE 'NEXT' KEY:
$lORE SI'IfI INTO EP PC;
STORE EP PC INTO TOP··QF-STOC.K (RELATIVE. '/0 Er P'--U);
PfiSS EP Re;
PASS EP PSW;
Pf\5S Er TIMER;
PASS EP ACClKlATOR;
MOV
GILL
n,12
OOTUTL
~Y
A,NIJ1CON
Ri, 1/UIC!14
A,@Ri
EPC!I4T
E.PrClO, 5Ift.O
I10V
i'IOY
JNZ
I'II'fO\I
MOV
I10V
PlOY
i'IOY
MmY
i'IOY
I'IOY
MOY
Ri,ISlft.O
A,@R1
R1, 1EI'PCl0
@Ri,A
EPrCllI,5If1III
RL IS/'IAHI
A,@R1
RL IEPPCIII
@R1,R
!'lOY
I'IOY . R,KE\'
ftll
0YSIfIP
SET If BREAK LOOIC FOR APPROPRIRTE
Df."PEND ING 00 COOENTS IF '"M'('.
III)Y
I'IOY
l'IO'II
A,lWE
RL.TVPE
fl,@R1
AOO
R,ILI»! GOTBL
JII'I'
(If!
00
LI»!(CGOtIl)
All mnemonics copyrighted © Inlel Corporalion 1976.
1-122
BI\tfII(
COtI)ITIIIIS,
Ap·55A
LOC ODJ
0472
8473
0474
0475
76
80
76
80
8476 99fD
11478 8~'91
047A 8482
947C 99F"C
847E 8482
0482
8484
9486
04eS
ffi29
9flEF
991)1'
F4F4
948f1 F4AC
948C r4flF
948E 37
84er F2!15
8491 86S9
0493 8400
9495 0499
9497 84ln
0499-B400
9498 8937
049D Fl
849E 93A!
9400 113
94Al A6
84A2
94A3
84R4
04A5
SA
SA
Afl
All
LIN[
=3929
=3921
=3922
=3923
=31124
=3025
=302G
=3927
=3028
=3929
=3030
=3931
=3032
=31G3
=3034
=3035
=3936
=3917
=3938
=3939
=3049
=3941
=3042
=3843
=-3944
=3845
=3946
=3847
=3848
=3849
=3959
=3951
SOLm: STATEIt::NT
00
00
DB
DB
;
cGOpnr:
CGOWO· AIIl..
OM_
Ji'tP
LOW(CGQIoIl)
LOW(CGOSS)
L~(CGOPAT)
LOW(CG()TRA)
Pi, INOT Il90099100
Pi. 1990099911)
Ept;>lJI4
;
CGOIID·
ANI..
JI1P
Pi, INOT 9IlIlOO911B
EPRUN4
;
CGOTRA:
CGOSS· In
Pl, .il8OO9911B
;
; EPRUN4 SE1 Uf' CONTROL LOGIC TO RUN USER'S I'ROGRAI'I.
,
~'ELEASE PROCESSOR TO f.
BREAK EI'IUlf1TJON /100£,
CONTINUE ACCORDING TO GO COItIAND TYPE .
CfilL
STSAVE
i'II'JJV
MOV
I10V
A, WI'E
R1, ITYPE
A, @Rl
fl, 'UlII CNTmL
flIA
fllD
JI'1PP
DB
00
DB
00
DB
LOW(BRKERR)
LOW(EPRUN6)
LOW(EPIWN6)
LOW(CNTTRA)
LOW(CNTTRA)
All mnemOnics copyrighted © Intel Corporation 1976.
1-123
Ap·55A
LOC 08J
LINE
SWlCE STRIDENT
=3986 ; ~ BREAKPOINT LATCH IllS SE"I TllOOOH BREflKPOINl 5 NoT EIflBLED.
=3987;
DISPLAY
=J9S8 1lRKERR: !lOY
Il4fI6 BIl8Il
94IlS 249A
=J009 '
94AA om
94AC F1
=31!99 ;
=3991 CNTTRA: I'II1OY
=3193+
!lOY
=3191+
!lOY
94AD 94F2
04flF F4fIF
94Il1 F241
, 0483 14EC
84B5 Fa ,
94~ DlD
9488 96C7
94IlA 14EC
94BC FE
9400 D112
94Ef 96C7
94C1 2382
94Cl 3499
94C5 8441
94C7 9433
.M'
I~ ~'a1I1ESSAGE.
LOflTA, I9EII
rH'J/OR
A,DSI'll"
Ri,'DSf'TIII
fl,lIR1
=3195
CIU
DElAY
KOOI'(l.
=3196
CALL
=3197
JB7
; Bi' SET INDICATf:S NO KEYSTRM.
EPCNT
=3198 ;
=3109 ; Ef'RlK) IIf'UTCKEY),
=3119 ;
Ir KEY--OO GO TO PARSER,
=3111 ;
It.fUT KEY,
=3112 ;
IF KlY()1£l(T GO TO f'Al&R,
=:!113 ;
CONTINI..( IN SAI'IE 11ODE.
=3114 ;
=3115 EI'RI.Ki: CALL
INPKEY
A,KE\'
=3116
MOY
A,IKEYOO
=3117
XRl
=3118
JHZ
EPREl
=3119 EPRI.Il6: CALL
IIf'KEY
fl,KEY
=3128
lIllY
/I, IKEYNXT
=3121
XRL
=3122
JNZ
L1'RET
/1,12
=3123
I'tOY
=3124
CAlL
runm.
=3125
Jill'
Ef'CNT
=3126 ;
=3127 ; EPRET EXECUTIIIl I'IOOE IS TO BE TtRI'IIIflTl:l),
=3128 ;
JIJtP IN10 PARSER TO INTERPRET KE\' ALREADY DETECTED.
=3129 EPRET: JItP
1lA1N2
=3139 ;
=3131
SIZECHK
=3134+ SIZE SET 291
=:1135+;
=3BGi'; **t_**~,******._*_*_*_********_t
"*
=3145 $EJECT
__
All mnemonics copyrighted © Intel Corporation 1976.
1-124
intJ
LOC OOJ
85IlII
85IlII 74418S82 2383
85843488
858G 74511
8588 1lS8I:
858fl 746A
858C 8A28
Il5IE 2314
8518 91
8511 9fIOF
!!:i13 8983
8515 F40B
8517 eA20
85199fU
8518 8903
851DF400
8!!1F B!lA5
8521 7461-1
1!523 F4D8
B928
8527 Ai
8:)25
8528 F400
852A 8922
852C Ai
852D F4D8
852F 8921
8531 A1
8532 1:400
8534
8536
!!:i37
8539
8923
Ai
C8IlB
746A
8538 b'921
8531) F1
1153£ 87
853f 5387
AP-55A
LINE
sotm 51 ATEI£NT
=3146
=3171+
=3175 ; STSAYE
=3176 ;
=3177 ;
=3178 ;
=$179 ;
=3188 ;
=3181 ;
=3182 ;
·=3183 STSAVE:
=3184
=3185
=3136
=3187
=3188
=3189
=3198
=3191
=3192
=3193
=3194
=3195
=31%
=3197
=3198
=3199 ;
=3288 ;
=3281 ;
=3282 ;
=:a83
=3284
=:1285
=3286
=3219+
=S22B+
=3224
=3225
=3238+'
=32$9+
=3243
=3244
=3257+
=3~O+
=3262
=32G3
=3276+
=3277+
=J281
=3282
=3283
=3292+
=3293+
COOEBLK 115
IE
1280
EP STATUS SAVE 9JlROOTlI£.
F(gE CALL TO LOC 814H;
SAVE EP ACC;
$AYE Er TII£R;
Sf1Yf:. EP P$II;
SAVE EP Re;
SA'IE EP lW-(F-5TACK IN EP PC;
kE1U!N.
EPfJRt(
CALL
R,13
/'lOY
CAl.L
OOTUll
CALL
OVSIR'
1\'8, 1l000(OY8OOS+OYSIZD
/'lOY
(M.0fl)
CALL
P2, 1II81!18OO81l
Il
EPt'ASS
EPACC,f}
1\'1,tEM;C
I!RLR
EPPASS
EPTlI1R, A
R1,I£PTI~
@Rj.,A
EPPASS
EPPSW,R
RLIEPPSW
PRLA
B'PflSS
EPR8,R
R1,1EPR8
@R1,A
R8, 1l000(0Y1BAS'IOYSIZE>
OYLOflD
R,EPPSW
fd.,1EPPSW
A, f!fd.
A
A. 18711
All mnemonics copyrighted © Intel Corporation 1976.
1-125
inter
AP·55A
lOC OBJ
LINE
9541 E7
85428388
=3299
=1J88
=3J81
=3J14.
=J:U5+
=3119
=1128
=1121
::JJ22
::11J5+
11544
854G
8547
8549
854B
B9J8
Ai
F487
93ft
AA
II54C 11924
Il54E Ai
854F
8551
11553
8554
85!J6
8557
0559
Il55A
F4C1
B9J8
11
F487
fVl
5JF9
2A
1JFF
055C~
Il55E Il925
Il568 Ai
8561 4A
IlS62 fIA
Il56J F4C1
8565 Il825
8:i67 347C
9569 2348
056B D4DS
056() B82Il
Il56F 3498
8571 03
8872
SW!CE STATEtt:NT
RL
roo
/'IllY
IIJV
IIOY
=:S~lG'1
=3348
=3341
=3342
=3343
=3344
=3345
, =3346
=3347
=3348
=3349
=3362+,
=3363+
=1367
=3368
=3J69
=n78
'
=3371
=3372·
=3173
=3374
=3375
=3376
=3377
,
=3J88+ SIZE
=3381+;
II
A.10SH
SIIfl.O, A
R1.ISIR.O
8RLA
Cfl.l
roD
!lOY
Ef'FET
I'RlY
IIOY
El'PCl.O, A
Rj"IEPPClO
I!OV
Cfl.l
EPST~
I'KlY
INC
C/U
/lOY
All.
XCI!
AOOC
AtL
/'IllY
IIJV
IIOY
0Rl
IIJV
CAll
IIJV
CAll
IU-2
WfllA,1I
8RLA
RLISIR.O
lIR1
E1'FET
lDflTA. n
A. 1111188888
A, looTA
A.'-1
fl.18IlII811118
ErPCHI,A
R1. IU'PCIII
I!RLA
A.lDflTA
lDflTA.1l
EPSTOR
Re,1EPPcH1
lIf'1)fI)1'
1819888888
I'IOV
fI,
Cflll
IIJV
CfLl
WDISP
; "-" ~ DISPlAY
R8,IEPfJX
DSF1IID
RET
SIZECII<
114
S£:.T
***-**********---*********--*-****
=3382+;
=3391 $EJECT
All mnemonics copyrighted @ Intel Corporation 1976.
1-126
intel'
LOC OOJ
11090
90IIA
991A
9297
9297 34CD
9299 D31A
929B C6E9
929() D31A
829F 033A
92A1 9697
92A3 rooo
92A5 14F9
92fl7 E941
92A~ A1
92AA 14F9
92AC 9931
92AE A1
92flF 14F9
92E1 B938
92E3 fl1
9284 14f0
02868942
92B8 A1
92E9 8941
9200 F1
92b'C W:C
92BE 14F0
92C9 AA
92C1r490
92C3 341'2
92C5 B941
92C7 F1
92Cll 97
92(,'9 A1
92CA 4489
0:iCC
92CE
92D9
9202
92D4
II2D6
34CD
0331C6DB
033F
348/l
14F2
AP·55A
LItE
sotm STnTEI'ENT
IIUOO£( :~9:HfILE.I'O)
3392 $
; (CR)
=3393 CHf1RCR EOO
0011
; (Lf)
=3394 CIm..F Et;'U
9FIl
; CONTROL-Z
=3395 CNTRLZ [00
1P.H
=3396 ;
=3397
COOEBLK S9
=3412+
ORG
663
=3416 ; tlRECIN IlEXFILE RECORD IIf'UT ROUTINE
=3417 Ift:CIN' CALL
CHRRIN
A, ICNTRI.2
=3418
XRL
=3419
JZ
DONE
A, ICNTRLZ
=3429
Xli'L
R, ,(': ')
=3421
XRL
tRECIN
=3422
JNZ
CHKSUI1, ZERO
=3423
ItIOV
CH FOlR BIT VALlE.
NOTE,· ~ ClECKING I.lOI£ TO VERIFY I£XIDECIIR. VALlDIT\'
C/U
CHARIN
; OCC=0F6-8FF FOR CllAROCTERS '8'-'9'
ROO
/l.. .-~
; CHARACTERS ) '9' f'ROOlJCE OYEkfL~
1M:
NIBB
ADD
; ACC=8"'5 FOR CIfIRIlCU:RS 'A' -'I·'
; ~ IF CHARRCTER BEllEEN 'S' IN> 'A'
me
ACC=0F61Hl5H FOR ClflRACTERS '8''''F'
All mnemonics copyrighted @ Intel Corporation 1976.
1-128
intel'
LOC OGJ
91C2 !!3FA
91C4 0310
91C6 E6C9
B1GS 83
91C9 E:Aen
B1C1l 249fl
0015
AP-55A
LIt£
SOURCE STATEtENT
=3708 NIBI3:
=37l.l9
=3710
=3711
=3712
=3713 ;
=3"114 ; fl'IERR
=$715 ASCERR
=3716
=3717
=372l1t SIZE
=3721+;
n.I-·6
ADD
ADO
. A.I1BH
JNC
A'IfJ'F:
;ACC=0fflt·0fFfl for.: CHfIkflC1ERS '€I'-'F'
;f1CC=OOfHlFlI FOR CHARACTlRS '0'-'F';
; OV£.f..'FLflI If f1IlO\J[ 15 JR!.(.
RET
ILLEGFt f£XIDECIMfll CfffllCTER
i'KN
LDAIn. leAH
JI'IP
PERROR
SI2ECHK
SET 21
~,[CEIV£D
=3722+; ******************~'************************'I"****************
=31'31 ;
=3,32 ;
01CD
B1L!) 1)449
1l1eF 537F
01D1 83
=3733
=:>743+
=3747 ; CUMIN
=3748;
=3749 Ch'ARIN'
=3753
CODE81K 5
ORG
461
CHARACTER IIf'U) ROUTINE.
RECEI't'[S 01£ fl'".>CII CHARACTER FROI'1 11£ LOGICft READER DEVICE.
CAU
CIN
ANI..
n••7FH
RET
=1.752
SIZECHK
=375S'f SI2[ 51: T ~
=~Z751
=3756+ •
=3757+; t****************************~'***********************t******
=3l66 ;
=3767 ;
=3768 $EJECT
All mnemonics copyrighted © Intel Corporation 1976.
1-129
inter
LOC· 00,1
8572
9572
9574
9575
9S7?
8931
957lJ
957A
9S7B
1I!!711
8939
F1
8934
A1
9S7E
rooo
1'1
8935
fl1
9SOO B865
Il582 14FC
9S84 1'1\
9S8S All
9S86 18
8587 84£2
9589 E696
958B 34F2
FB
9388
E682
D49Il
0594 A472
95ro
II5SE
9599
9592
Ap·55A
SOO«I 5TATElENT
LIIf:
=3769
=3794i
=3798 ; !-fILEO
=3799 ;
=J009 ;
=3881 HFILEO:
=3B17+
=3S1e+
=3B24t
=3825+
=3820
=3S44+
=3S45i·
=3851+
=3852+
=38:iS
=3860+
=3864
=3865 ;
=3866 ; LDB\'TE
=3867 LOOVTE:
=3868
=3869
=3879
=:ro71
=3B72
=3873
=3874
=387S
=3f;76
=3877
=387S
=3879 ;
COO[[lLK 190
C»1G
1394
HEX FILE ooTPUT SlIlROUTIIf:
lIEN CALLED WITH F9=9 OOTPUT IS STfHJflRO lEX FILE FORPIflT.
WHEN CRLLED 101m: F0=1 ooll,\.IT IS rORllAlTED DA1A DUMP TO CRT
I'II'IOY
~w
MO\I
MOV
1E11H1.. SPfAHI
R1, tsI1flHl
n, @R1
Ri, lIIEIVII
A
I'£I'ILO, SIRO
Ri, 1Slft.0
A, toR1
MO\I~,
I'mV
MO\I
MO\I
'ItJY
MOY
ItIOY
MO\I
MOV
R1, 1tE1L0
@R1, A
Clf(SU/'I, ~
CllKSUI'I, lZERO
1"9, 1HEX8lf
LOAD /£XT B'r'TE FROI1 I'EI'IOR\' INTO lEX BLfFER
CIU
LFETt:f1
110V
It, LDflTA
MOV
INC
@Re, A
CALL
,Ill:
CllPI'IAS
OOFIL
CPU
110''
OOD
JNC
CAlL
JMP
R0
1NC'"J1A
A, R9
A, t· (IllRlN+HEXBlf)
L()[l\'TE
HRECO
IFILEO
=3889 ; BUll 00 f£X FILE TRflNSI1ISSION·
PRINT OUT BlfFIR FOR LAST DArn RECORD
PRI NT OUT CAlf£D 'EOO-or· -FILE' RECORD
95%
959S
9S9A
959C
959E
9S9F
95A0
95A2
=3881 ;
=3882 .;
=3W3 ;
RE1LRN.
D400
=3884
CAlL
IRECO
B6/l7
34D2
B8AE
1'8
fl3
CCA7
=300S
=38CG
=3887
=300S E1I>F1:
=300s
=3899
=3891
=3892
=3893
=3894 HFOO/£:
=3895
=3896
=3897
=3898 ;
JFe·
CIU
ffDOl£
TCRlFO
~.'8, I(L(Io/ EOFREC)
B4flI)
. 95A4 18
85A5 A49E
~7 34D2
95A9 2310
9SAB S48D
0SfID 83
oom.
MOV
MOY
I1OYI'
JZ
CALL
Ill:
Ji'IF'
CALL
I'IOY
CllLL
f\,@A
ffOONE
ClfIRO
R0
[N>f1
TCRLFO
fl, ICNTRLZ
CfflRO
RET
=:r099 ; EOFREC CHARACTER SkTING FC»1 t'fllH:D END-{f-fILE RECORD rOR
=3909 ;
INT[l lEX rILE FORIIAT STf1NDARD.
95AE 293A3838
=3901 [OFREC: 00
' :OO000091Fr'
All mnemonics copyrighted @ Intel Corporation 1976.
1-130
inter
LOC OOJ
05B2 39393939
95B6 30314646
9SBA 00
0049
AP·55A
LINE
SOlJ:CE STRTEI'lNT
; EIIl Of STR II«.i COO[ BVTl
=3902
DB
9
=39113
51ZECH<
=3ge6l S12E SET 73
=3997+;
=3988+; ""***********************""*~-'''******.**-************'I''*
=3917 ;
=3918;
II68Il
Il689 FB
9601 9398
11603 8941
9605 A1
9606 3402
8688 2329
9600 B4CO
960C 8617
96IIE 233f\
9WI II4BI>
11612 8941
9614 F1
9615 3400
9617 8935
11619 F1
1161A34DB
961C 13934
961E F1
1161F34DB
11621 B62B
11623 27
11624 3408
962(; C42C
9(;28 2330
~B4BD
962C [:865
1162[ 8(;32
9630 C436
11632 2329
0634 E4BD
9&36 Fe
9m 3400
1lG391S
963A 13941
963C F1 .
11630 97
=J919
=j94!1+
=3953 ;~IIIECO
=3954 ;
=3955 URECO'
=3956
=3957
=3970+
=3971l
=3975
=3976
=3977
=J978
=3979
=3989
=3981
=3990+
=3991+
=J995
=3996 rDUl'\P1:
=4005+
=4006+
=4019
=4011
=4929+
COOEBlK99
ORG
1536
HEXIDECIIR. REcoo) OOTPUT SEQlBa.
lEX BlfFER ALREAD\' LOOOCD.
A,RQ
MOV
A,I-fEXBlf
flOO
BlfCNT, A
MtIOV
Ri, IBUFCNT
I'IOV
~,R
MOV
TCRLFO
CALL
fl, I' ,
/lOY
CALL
!lAW
Jf9
FOOf'1
A,I' :'
MOV
CIU
CIlARO
ItIOY
A, IllFCNT
RL IBUFCNT
A, @l.:1
()'{fEO
CALL
R, I'EI'IHI
tmV
Ri, tl'lEl'IHl
I'IOIJ
A,@R1
!'IOV
CALL
B't'TE0
A, 1'E1'l0
ItIOY
MOV
R1, II'IEIt.ll
A,@R1
=4921+
!'lOY
=4825
C/lLl
BYTEO
=4926
Jf9
FOUI'IF'2
=4927
CLR
A
=4112!l
CRI.L
B'fTEO
JIll
ooTO
=4929
=4039 FDltIP2: /lOY
A, 1'='
=4031
CAll
CHARO
=4932 ;ooTO DAHl OUTPUT
=4933 ooTO: MOV
RfU/lEXBlF
=4034 ooT01: JF9
FDUIf'5
=4035
Jl'IP
f-0UI'IP3
A,l' ,
=403& F/.lUI'IP5: MOV
=49:17
CIU
CHARO
A,@RIj
=4038 FllUI'If'3: /'lOY
=4039
CI1I.L
BYTEO
=4040
INC
R9
=4041
1'IOJN2 BtfCNTI DAT01
=4046+
/lOY
RLIBlfCNT
A,@R1
=4047+
/lOY
I)£C
=4051+
A
All mnemonics copyrighled
©
MOV
MOV
Inlel Corporation
1976.
1-131
inter
LO:; OOJ
063£ Ai
8QF 962E
9641 B648
9643 fI)
8644 37
8645 17
964(;
3400
9648 83
9849
AP·55A
LINE
=4956+
11)\1
I!R1., A
=496&+
JNZ
DAT01
=4062 ;
=4IJ6J ; EN>REC EN) RECORD BEll«] TRANSMInEO
=4964 EIMC: JF9
FDUI1I'4
=4965
.=4IlB1+
Ift)Y
11)\1
A, (;III(SIJI
A, CfI(SIJI
=4885
CPL
A
=4006
II«:
A
=4987
Cfll
BVTEO
=41J88 FDI..I?I'4: I5
94E9 83
9918
AU mnemonics copyrighted © Intel Corporation 1976.
1-133
intJ
LOC OOJ
II5IlB
95B8 34EG
85BD 11944
II5IlF /l1
85CII fl94J
95C2 BiIlB
95C4 97
~F6CB
95C7 9geF
95C9 fl4CF
95CB 8948
~
95CE
Il5CF
851>1
851>l
Il5D4
011
011
94C9
94C9
97
A7
8944
951)7 F1
85DS G7
85D9 ft1
85J)S
AP·55~
LII£
=4358
=4383+
=4387 ; NIIJO
=4388 NIBO:
=4389;
=4398 ; 0fIR0
=4391 ;
=4392 ClfRO:
=4485+
, =4496+
=4419
=4421+
=4422.
=4426
=4427 C01:
=4428
=4429
=4439 CO2:
=4431
=4432
=4433 COl:
=4434
=4435
=4436
=4437
=4442+
=4443+
=4447'1
=4452+
=4455
=4456
95DR 8943
II50C f1
9500 97
050C R1
05DF 96C5
05E1 8l
11827
S(lf
cle
cle
CI1
el1
~'
CI1
1B>I.A't'
All mnemonics copyrighted © Intel Corporation 1976.
1-134
intel'
LOC
OIIJ
965B
IIG5D
965F
9668
96G2
9663
94C9
5662
97
C465
97
A7
0664 90
fIG65 98
0666 ee
9667 ee
9668 8944
Il6GA F1
0C6B 67
966C R1
11661)
8943
9W" F1
9679 97
9671 A1
1lG72 %59
9674 B944
11676 F1
9677 83
IlIJ2F
AP·55A
sotm STAIDIEHT
LIN:
=4538
=45"".$9
=4549
=4541
=4542 CIl:
=4543
=4544
=4545 C14:
=4546
=4547
=4548
=4553+
=4554+
=4~-I
=4563-1
=4566
=4571+
=4572+
=4576+
=4581+
=4585+
=4587
=45%+
=4597+
CfU
IflDI..RY
JT1
CLR
JII'
CIJ
; C1£CK SID LIN: LEII[l
C
Cl4
C
C
; DATfI BIT IN C'!'
CLI!
(;f'l
to'
10'
NOr
I«lP
m1C
I'IOV
IIOV
REGC
R1,IREGC
RRC
IIOV
tl)JNZ
IIOV
A
@I/1,A
El. CI2
R1,1B
A..@R1
A
@fU,A
CI2
A..REGC
R1,IREGC
A..@R1
; CIIRRACTER CO/fl.E1E
IIOV
DEC
IIOV
1HZ
ItIOY
IIOV
IIOV
=4691
RET
SIZECl-1<
=46112
=4695t SIZE SET 47
=4696+;
=46117i;
; EVEN OUT BmOf EXECUllOO TIlES
A,~
*******_ _ _ _ _ _ _ _ _**'.:**
=4616 $EJECT
All mnemonics copyrighted © Intel Corporation 1976.
1-135
inter
LOC
ooJ
AP·55A
L11£
4617 $
=4618
82E~
B9J4
92E7 F1
I12ES RfI
82E9 F489
82EB B4E2
82ED E6FJ
82EF J4F2
82F1 44E9
82FJ 8J
=46JJt
=4637 ; COIFIL
=46JS ;
=4619 mtrIL:
=4655i
=4656+
=4669+
=4672 LrILL:
=4673
=4674
=4675
=4676
=4677 LFILL1:
=4678
=4681+ SIZE
ItnUllE( :~9:1EPI!Er.ID»
COOEBLK 15
ORO
CIltRI)
IN LOll
I1IKlY
I'IOY
I'IOY
I'IOY
CII.1
741
TO riLL fl)l)RESS SPfa: OCllEEN SIfl
BYTE (f /'IEPl
LDATA, 1ElL0
RL 1tElL0
A, I!R1
LDA·, A, A
LSTORE
III)
EIII .. mlllRTft
CfLL
CI'fIft)
JlI:
LrILL1
CfLL
INCSIfl
JIf'
U"ILL
RET
SIZECII{
SET . 15
=4682+;
=468J+;**_*1..._IIIIII ..._*_ .. I _ _ _***II .. IIIIII .. 44
09FC D478
eerE flA
09FF 8J
=4692 ;
=4693
=4698+
=4792 ; LmCH
=479J ;
=4794 LFETCH:
=4795
=4786
=4797
=4718+ SIZE
=4711-1;
COOEIlI..K 4
ORG
252
FETCI£S CIIlTENTS IF LOGICfl. 1£Im,' mDl. INTO
872F
8lS8
9732
8733
8938
Fl
5s7F
C62f'
E4C3
FA
11923
Ai
83
AP·55A
LItE
SMCE STRTEIENT
=4915
=4958f
=4954;
=4955 ; LSTIJ:E
=4956;
=4957 LSTIIIE:
=4966+
=4967+
=4971
=4972
=4973 ;
=4974 LSTIIJI.:
=4975
=4976
=4977
=4978
=4979
=4988;
=4981 LSTI'tI:
=4998+ .
=4991+
=4995
=4996
=5885+
=5986+
=5818
=5811
=5912
=5821+
=5822+
=5826
=5827
=5828
=5829
=5838
=5831 ;
=5832 LSTDII:
=5833
COOEBLKSS
am
1792
LOOICII. STIllE SlIJROOTItE
STIllES cam:NTS (J LDfIm INTO YRRIOOS 1EIDl\' SM:ES.
fl,TYPE
IftJY
..w R1,I'M'[
..w A, (IR1
fI)I)
A, ILOW LSTTBL
I!fl
JII>P
DB
LOW
LOW
LOW
LOll
LOW
LOW
DB
DB
DB
DB
00
/I'KlY
..w
..w
JNZ
/I'KlY
IllY
..w
fI)I)
Je
/ftlY
IllY
IIOY
fI)I)
IllV
IllV
IllY
LSTPI1
LSTDII
LSTREG
LSTINl
LSTBRI(
LSTiiRl<
fl,SlDtI
RL ISIftfI
'URl
LSTDII
A, SlR.O
RLISlR.O
A, (IR1
Itl-OYSIZI:
LSTDII
ItS/R.O
RLISIft..O
. fI, I!R1
It IOYIltf
RLA
ItLDflTA
f!R1, A
RET
ClLL
lIlY
=5834
11M(
=5835
;'5836 ;
=5837 LSTREG:
=5846+
=!IIM7+
=5851
=5852
=5853
=5854 ;
.=5955 LSTR8:
=5878" .
=5884+
=5885+
=5888
=51189 ;
=5898 LSTINl:
Rtf
PKIY
IllV
mY
IN..
12
JI1P
/I'KlY
mY
IllV
IllV
LPGSEL
A,LDflm
!!H1, A
It SlR.O
R1.ISIR.O
A, I!Rl
A, 181lli111f1
LSTh'8
EPSTIR
; CI£CK IF LOW IJ.'DER BITS = 8
EPR8,LOATA
ItLDflm
RLID'R8
f!R1, A
RET
IftIY
ItSIR.O
All mnemonics copyrighted @ Intel Corporation 1976.
1-138
AP·55A
LOC IEJ
07148930
0736 F1
0737 0320
97J9 A9
97JA rR
0738 Ai
073C 03
973D
073F
0740
0742
9744
9746
9749
974A
0749
9740
94£1
FA
1246
9ge1
E448
99FE
991'7
81
890B
03
004E
94E1
04E1
94E3
94E4
94E6
8937
r1
5301
47
94E7 8931
!l4E9 41
94EJl 4340
84EC 3A
94EI) 8930
94EF F1
WI! A9
94F1 93
9011
LINE
SIX.m: STATEIEHT
=5099-1
Ri,IS/ft.O
I10V
A,@R1
=5100+
1m
A,IEPOCC
=5104
ADD
Ri,A
=5195
IIOY
A,LOAm
If.J\I
=5196
@R1,A
=5197
PlOY
=5199
RET
=5199 ;
=5110 ; LSTIlRK LOGICRL STORE !W BmlK-POINT DATA
=5ill LSTBRK: CALL
Lf'GSEL
=5112
t10V
Ii, LOATA
=5113
JOO
LSTBR1
=5114
0Rl·
Pi, t999ll09918
=5115
JIf'
LSTBR2
=5116 LSTBR1: ANI.
Pi, INO r 1IIl0IIIlIl01B
=5117 L!::TBR2: AtI.
11., INOT 1l0Il011l01l0
=5119
I'KJ\IX
A, @R1
=5119
OR!.
Pi, tIl0Il0199IIB
=5129
RET
=5121
SIZECH<
=5124+ SIZE SET 7S
=5125+;
=5126+; ***----"*****_*_******_*_ _*****
=51~ ;
=5136
COOEBl.I( 17
=5156+
ORG
1249
=5160 ; LPGSEL LOGICAL PAGE SELIOCI.
=5161 ;
SETS lJ' PORT 2 TO AOORf.SS Af'I'RtrRIATE BYTE !W RfIPI BLOCK.
=5162 LPGSEL: I'II1OV
A, TVPE
=5171+
IIOV
RUnoPE
=5172·.
I10Y
fl, @R1
=5176
IN.
fl, t090Il0II81B
; tfASI( Off DlITR noPE SElECTIII BIT
=5177
SI«lP
A
=5178
IQ\.
A, SIflHI
=~104i
roy
R1, ISlftIi
=5195+
OR!.
A, f!R1
~1!)9
ORL
fl, 1019000098
=5199
=5191
OUTL
I'II'IOV
/lOY
/lOY
P2, A
n, SlfLO
Ri, 1Slft.0
A, @R1
RL A
=5200+
=5291+
=5205
=5296
=5207
=5219-1 SIZE
I'IOV
. RET
SIZECHK
SET 17
=52W;
=5212+;**-**_ _**********_ _ _*****=5221 ;
=5222 $EJECT
All mnemonics copyrighted © Intel Corporation 1976.
1-139
AP·SSA
LOC OOJ
LII£
SOO1CE STRTEl£NT .
=5223
COOEBLK 11
=523".$~
1I1F2
91F2
01F4
01.F5
01F6
8938
11
F1
96Ft
81f8
01F9
01FR
01FB
91fC
19
F1
17
31
83
OF:G
=5237 ; IN;!;I1A
=5238 IN;!;I1A:
=5239 11«:11:
=5240
=5241
=5242
=5243
=5244
=5245
498
11«:REl£NT ST~TII~ 1'E/IlR't' fl>DRESS WORD.
I'KlY
Ri, ISM.O
It«:
I«lY
JN2
It«:
I'KlY
It«:
XCII)
@R1
R. @R1
11«:111
Ri
A. @R1
A
A. @R1
~46
11011: RET
=5247
SIZECII<
=5250+ SIZE SET 11
=5251+;
******.----..
02F4
02F4 8938
1l2f6 F1
02F7 07
02F8 21
Il2F9 96FF
02FD 19
02FC F1
07
02FE 31
02FF 83
Il2fl)
=5252+;
=5261 ;
=5262
=5277f
=5281 ; DECSIII
=5282 DECSIIA:
=5283
~*******"*-**-**-**
COOEBLK '12
(RG
i'56
DECREI£NT SIIfl lOW.
I'KlY
Ri,
IllY
A. I!R1
~
DEC' A
=52re
XCII
A.1!R1
=5286
JNZ
DECSIU
=5287
INC
Ri
=52S8
I'KlY
Pu I!R1
=5289
DEC
'A
=52ge
XCII>
II. IR1
=5291 DECSItt: RET
=5292
SIZECHK
=5295+ SIZE SET 12
=5296+;
mo
=52S7·~;~**
=5386 ;
=5387
=5l32~
_ _**._ _ _
COOEBLK 15
(RG
1~
=5336 i CIf'IfIS COI1PARE I£IllRY ADI1RESSES
=5337 i
CIII'fRE SIfl BVTES WIlli BIA BYTES TO DETmlII£ RD.ATIYE IRlNlTWE.
=5338 i
RETIIlNS WITH CfflRY=1 IFF (SIIfl) )= DC
It ElRiI
ItlY
flOOC
RL IEIIIlI
A, I!R1
RET
SlZECII<
SCT 15
=5481+;*.*'I:*.*********_ _ _ _ _* * - _
=54111 $EJECT
All mnemonics copy'ighled @ Inlel Co'po,alion 1976.
1-141
inter
lOC OOJ
Ap·55A
LIIE
SIUCE STRIDENT
5411 $
IlUl.OC( :F9:KOO.I'ro)
CODEBLK 199
=5412
974E
=5447+
OOG
=5451 ;
=5452 ;
974E
os
974F B93E
97~1 A1
975223f9
975462
8755 27
9756 3E
9757 3D
9758 FD
9759 97
07SA 3f
0758 OC
975C AA
0750
07Sl
0?Sf
0761
9762
9763
0764
9765
FD
97
0346
~ AM)
=5453 ;
=5454 TIINT:
=5455
=5468+
=5469+
DISPLA\' PROCESSINl ROOTII£
I'ERIOOIClLl \' loRN KIlO fH) DISPLAY fl.'E "fO BE fl.IYE.
5El
R81
ItKJV
AS/lYE, /1
~
R1,1ASf1Y[
IlO\l
@I/1,A
CfU[J)
~
=5473
=5474
=5475
=5476
=5477
=547lJ
=5479
~
QR
llOYD
llOYD
~
DEC
/'lOYD
=5489
=5481
=54!J2
=5483
=5484
A,'(-19H)
I, A
R
PSEGHI, A
PSEGlO, A
R,ruIDIG
I'IOY
IlO\l
R, ~D JG
DEC
AOO
1'10'1
R, t<"...EGIR'
f'IO\II)
; REUB> TIllER INTEIt-1<*******~'***********************************************
=5549 ;
076F B93C
9771 F1
=5541
=5550+
A, mtOC
=55~1+
A,~1
Rl, tKE'r'lOC
All mnemonics copyrighted © Intel Corporation 1976.
1-142
AP·55A
LOC OEJ
LIIE
em 2C
em DC
=5556
e774 C67C
5O.E[ STATEI1ENT
=5557
=555e ;
=5559 ;
=5568 ;
=~561 ;
=5562 ;
=5563 ;
0776 B9JD
=5564
9778 8106
I177A 1:488
=5SGS
=5566
=5567 ;
=5560
=5569
=5578
. =5571
=5572
8nc B93D
8nE F1
ilIfF C6BB
9781 07
0782 !J93D
8784 Al
07ElS 968B
XCH
XRL
J2
=5555
. A. LHSTK'r'
A. LASTK'r'
SCAN3
***********-***************-*-**-**
A DIFFERENT KEY If1S R£AI) ON THIS C\'CLI:. THAN III THE PREVIOUS C\'CLE..
;
;
;
;
;
SET NREPTS TO THE OCIlOONC[ PARAME1Ell FOR A NEW COUNTDOWN.
*****___ t***********_*_*****ot-******,t,***~:*****
mil
I10V
JI1P
Rl.INREPTS
@R1.1G
SCAN5
*****__**,t:*_-************_*******************_**
SAI1E KE\' WAS DETECTED 3S III PREYIOOS CYCLE
L()()I( AT Nro'TS: IF ALREAD\' ZERO, DO NOTHING.
•ELSE DECREI'IENT NRCPT!;.
IF THIS R£SIUS IN ZERO, /'lOVE LASTKY INTO KOOCUF.
=5573 ; ***:t:***_**~·*********-~******************************_***
=5574 ;
A.NR[PTS
=5575 SCflNJ: I'IMOV
R1,INREPTS
=5584+
MOY
A,~1
=5585+
I10Y
; IF flLREflD\' ZERO
=5589
12
WlN5
; INDICATE ONE I'IORE SOCCESIVE KE.Y DETECTION
=5590
A
DEC
I'ItlOV
NREl'T5. A
=5591
RLINREPTS
=5684+
MOY
=5685~
I10V
~1.A
=5689
=56HJ
=5633+
JHZ
SCANS
I'II'IOV
!'lOY
KBD8UF. LASTK\'
07se
=5639·~
I10Y
97SA 111
=5649+
=5643 ;
=5644 SCIlN5:
=5645
=5646
=5647
=5643
=5649 ;
MOY
0787 Fe
B93B
0788 B93C
0780 11
07aE EC63
0790 EDIlS
iJ,'92 t;OOS
MOV
INC
DlNZ
DJNZ
I10Y
; IF DECREMENT DOES NOl RESlU IN ZERO
; TO MflRK NEW KEY CUYJ.JRE
/), LflSTKY
R1,IKBOOUF
@FILA
Ri.IKEYLOC
@R1
ROTCNT, NXTLOC
CURDIG, TIRET1
CURDIG. lICHf1RNO
=5650 ; ******~:*****~::{:*****_***********,t,*********_*_*~:*****
=5651 ;
THE FOLLOWING CODE SEG/'IENT IS IJSEl) L.... UIE KEYBOflRD SCAItlING ROUTINE;.
=5652 ;
IT IS EXECUTED ONL \' AFTlR r. REfRESH SEQUENCE IS COI'IPLETEO
=5G53 ;
=5654 ;
=5655
****************************......*****'t:********'t"t.*_**-..
9794 B9:>C
0/96 Bllil0
=5666~
lIns rl:
=5671
=5672
=5673
=56j'8+
=5632 ~ANS:
=5683 ;
0799 969D
079B BCFf079D BE90
=5667·~
I'II'IOV
!'lOY
I10Y
I10Y
JHZ
MMOY
MOil
I10Y
KEYLOC, ZERO
R1, lIKEYLOC
@RL.ZERO
11, KEYFLG
; JUI1P IF AN\' KEYS WERE DHECl ED
SCANS
; CHANGE (LASTK\') WHEN NO KE\'5 lIRE DOWN
LAST((Y. NEG1
LAS1 K',', llNEG1
KE\fLG.1I0
All mnemonics copyrighted @ tntet Corporation 1976.
1·143
inter
LOC
()(jJ
AP·55A
SOIJ!CE STAT£]'I[NT
lifE
=5G85
!
=5636 ;
KOOIDISP RETURN COO[- RESTIMS SYSTE" ~TATUS.
A, RtlELA't'
I'II'IOIJ
=5696+
Rj., IRDELflV
!'lOY
R,@R1
=569;'+
I'IOV
=5791
JZ
lIRETi
=5782
DEC
A
k'OCLAI', A
=5793
I'IMO\I
=5716-1
I'KlY
R1, IRDELA\'
@RLR
=5i'17+
tIOY
=5121 TIRETi: I'II1OY
A,AS/We
=57J3-I
!'lOY
RLWJlYE
A, INd.
=5731'1
I'IOY
=5735
RETR
=5736 ;
=5737 ;
=5738 ; TOFPOl. TIIa OVERFLOW POLLING sueROOTINE.
=5739 ;
CfUED REl'EATEl'il..Y FROI'I IKID'ER I(BllIDISr /'lUST BE. fiLlYC.
=5740 ;
I'OIITOR!; mE TIIG OYERF1.1101 FLAG 3 5:;or
06D5 83EF
0607 A3
0600 AE
=5907
=5937+
=5941 ; OSF'ACC
=5942 DSPACC:
=5943
=5944
=5945 ; WDISP
=5946 ;
=5947 ;
=5940 WDISP:
__
COOECLK 44
ORG
1747
DISPLAY VALUE or LOW NIBBLE Of IICC
ANt.
fl. IffH
ADD
A, #OOPATS
MOVP
A. @A
WRITES BIT f-'AlTERN IJOW IN ilCC INTO NEXT UiARfICTER rOSITlON
OF THE DISPLAY (NEXTPl). INCREMEN1S NEX1PL
RESULTS IN DI$PLA~' BEING FILLED LEFT TO RIGH"f. lHEN RESTARTING
MOV
DSPTMP. A
All mnemonics copyrighted @ Intel Corporation 1976.
1-145
inter
LOC
OOJ
0609 BF04
9600 7401
AP·55A
LINE
=~949
=59~
=5951
96DD
0CDF
061:9
06£2
960
96E4
893R
F1
9345
R9
FE
A1
96E5
96E7
96ES
96E9
96EA
093A
Fl
97
A1
96EE
9(;[C !l10S
06EE 83
IlIlEF
96EF
0Cf9
96F1
116F2
116F3
06F4
96F5
96F6
06F7
06f8
96F9
86rA
86rE
96FC
96FD
06FE
3F
96
5E
4F
66
61)
7D
97
7F
6"?
77
7C
39
5E
79
71
882C
=5960+
=5961+
=5965
=5966
=5967
=5968
=5969
=5974+
=5~75+
=5979+
=5984-1
=598S~
SOlJ.'CE $TRTIJENT
I10Y
CflLL
MMOY
/'f0','
110','
000
tm
!'lOY
!'lOY
Ml)JN£
I'IOY
I10Y
DEC
110','
JNZ
=59'"j9
MOOf
=5991 WDISP1: RET
=5992 .;
=5993 ; OOPAT$ IS TI:E
=5994 ; I-IERE. THE FULL
=5995 ;
=5996 DGPAT$ EQU
=5997 ;
=5998 ; FORI'IAT 1$
=5m;
DB
=600Il
=6091
DB
=6092
DB
=6003
DB
xrcOOE,14
XPTEST
Il,NEXTPL
R1, INEXTPL
iI; ~1\'1
Il, #$EGMflP·1
R1,fl
A, D5PTMf'
@ld,A
NEXTI'L, WI) ISPi
R1.iNEXTPL
A,@R1
R
@R1,A
WDISP1
@Rl, .CHARNO
BASE FOR THE TAIlI.( OF $EGMENT PATTERNS FOR HEX DIGITS.
I-lEX SET (0··n IS INCllVED.
f AND 0fFH
PGFEDCBA
1l8111111B
eee09110C
01111191113
91091111&
DB
01109111113
=6004
01}
01101101&
=6995
Of)
=6006
91111191El
Of)
=6807
00009111B
91111111B .
=6900
I.lfl
01100111B
=6999
DB
=6010
00
911191110
Of)
=6011
91111100E:
=6012
011
001110018
Of)
=6013
019111100
=6914
DB
011110018
.811100018
=6915
00
$IZECHI(
=6016
=6919+ SIZE. SET 44
=6920+;
IN STANOORO SEY[N-Sl(i1'lENT ENCODINU C(JI\IENl ION
WHERE r REPRESEN1S TIlE DCCIIR POINT
; SEGMENT PATTERN FOR DIGIT '9'
; SEGl'ENT r'ATTERN FOR DIGIT '1'
j ~EG1'IENT PAT! ERN FOR DIG IT '2'
; SEGMENT PATTERN HlR 0IG n '3'
; SEMNT PATTERN FII: 0IG IT ' 4'
; SEGMENT PATTERN FOR DIGIT '5'
; SEGI1ENT PRTlERN FOR DIGIT '6'
; SEGl'lENT PflTTERN FOR DIGIT '7'
; SEGl'ENT f'fITTERN FOR DIGn 's'
; !;EGIlENT PATTERN FOR DIGIT '9'
; SEGI1ENT PATTERN FOR DIGIT 'n'
; SEGI'fENT PATTERN FOR DIGIT 'B'
; SEMNT PATTERN FOR DIGIT 'c'
; $EGI1[NT PftTTE.RNTOR Dlull 'D'
; SEGMENT PATTERN FOk OIGIT 'E'
; SEGrlENT PATTERN rll: DIGIT 'F'
******************************-********************
94F2
94F2 893F
94F4 Ai
=6921t;
=6039 ;
CODEEllK 12
=6031
1266
=6051+
ORG
=6055 ; DELAY SUBROUTINE IofIITS FOR TIlE NltIBER OF COItPLETE
=6056 ;
DISPLAY SCANS CORRESPONDING TO THE ACC CllfTENTS.
USE!) WITH CRUDE Ill..l'Im INTI:RrRCES- AS WHEN OPERATOR SlW..D SEE
=6057 ;
=6958 ;
SOI'IE DISPLAY CHANGE IoIIIU: IT IS CHANGING:
ROELAY, It
=6959 DELI1Y: /'fI1OV
=6072~
1'10\1
R1, 'RI>ElR'o'
@R1,A
=6073+
I'lO\l
All mnemonics copyrighted © Intel Corporation 1976.
. 1-146
AP·55A
LOC OBJ
84F5 F4AC
9417 D93F
114F9 F1
I14FA 96F~
I14FC 83
LIM:
SlUCE STATEPENT
=6877 ocLAI'1: CALL
lOITOL
=697B
A, ROCLAI'
=6987+
=6888 f
=699'.1
m:lV
MOV
RLtRDELR\'
I'tOV
fi,~1
JNZ
DELAY1
=6993
RET
=6B94
5IZECHK
=6097+ SIZE SET 11
=6998+;
=6899+;
=6198 ;
=6199
**...*******~,*"......**_**********...**..***...._***..
COO[8LK 8
87fIF
=6144+
87fIF 8F95
=6148 ; KeDl'OL POlL STATUS (f KE.I'SOARD INPUT ROOllNE.
=6149 ;
RETURN loin II ACC BIT 7 =, 0 IF KEI'SOfIRD IWUT HIlS BEEN RECEIYED.
=6159 KBDI'OL. I'tOV
XPCQDE, 115
9781 7401
07B3 B93B
9785 F1
97EJ6 113
=6151
=6152
=616H
=6162+
=6166
=6167
(IlG
CflL
I'IIIOY
I10Y
MOY
1967
XPTEST
n, K8DBI.Jf
I~L .KElDBlf
A, ~1
RET
SlZECHK
=(;179+ SIZE 5[1 B
=6171+;
=6172+; ***",*.*~,**",*******,,*************-**********--****~,
=6181 SEJECT
All mnemonics copyrighted © Intel Corporation 1976.
1-147
inter.
LOC OOJ
AP·55A
LINE
SCdJRC[ STATEI£NT
6182 $
=6183
=6218.
97E7
97E7
9789
971lR
97BC
971£
97C9
97C2
IInUDE( :F9:LINK.I1OO)
COOECLK 15
ORG
1975
B9J9
F1
F4DO
2389
F4D0
F4D9
83
900C
97C3
=6222 ) Ef'fET
=6223 EPFET:
=6212+
=6233+
=6237
=6238
=6239
=6249
=6241
=6242
=6245{ SIZE
=624&+)
FETCH DflTIl B\'TE FROM Er INTERIft. RAP! ADDRESSED B\' 5IR.O.
I1I1OV
A, Sl'lALO
MOY
R1.. tSI'R.O
MOY
1l.@R1
CALL
EPrASS
MOY
CALL
CALL
A••19999080B
£l'PA5S
EPPASS
RET
SIZECH<
!.El 12
=6247+; ~. *****>t.***_",,**_**********_"'******'I"*****~"************
=6256 ;
=6257
COOEBLK 15
=6292~
ORO
1987
=6296 ) EPSTOR STORE DATA IN Loom IN EP INTERIR. RAt! AT (SIflO)
97C3 rA
97C4 F4D0
97C6 8939
9i'C8 F1
97C9 5371"
=6297' EPSTOR:
=6298
=6299
=6300+
=6399+
=6313
07CB F4D0
=6~14
1l7Cl> F4D9
07CF 83
=6315
=6316
MOY
Cill
I'II'IOV
A. LOOTA
El'PASS
A. SIfl..O
RL .SMALO
!«)II
A. @R1
/'lOY
AN.
CALL
CALL
A, 1011111111)
EI'Pf1S5
EPPAS5
RET
SIZECUK
=6329+ SIZE Sll 13
=6~17
=6121+)
*-*****"'****"''''************'''************-************
=6122+)
=6331 $EJECT
All mnemonics copyrighted @ Intel Corporation 1976.
1-148
intJ
LOC OIlJ
9700
AP·55A
LINE
!>OI.RCE !il flTEMENT
=63J2 ;
=6333 ;
THE rOlLOIolING UTILITIES IN'r'Ol't'E INTERCIfINGES IlETloEEN TI£ 1'If'
=6334
COOEIlLK 11
=6369-1
All)
[Po
ORG;:'000
=6373 ; EPPASS PASSES II SINGLE f'fII'7F400
9709 81
9700 BJ
=6377 ;
RET~N.
=6370 EPPASS: OI\t
P2••99110099B
=637S
1'10'(;(
liR1.fI
=6300
=6381
OR\.
AIL
=6382
=63!B
CAlL
IIOYX
=6J84
RET
; lNABlE llNK WRITES.
; WRITE ACe '10 LIN(.
; OI5ABll BREAKPOINTS.
; SET TO EREIlK ON LINK RlFERUU.
Pl. INOT ENIlRPoPI
P1.ICNIlLNK
~f'51 EP
fl. @Rl
=638:>
SIZECflK
=6333+ SIze SE.T 11
=6389-1;
=6399+; **********.*************~.~,****'1"**-"'I-.******
=6399 ;
=6499
9700
9700 F4f4
9700 Il99A
97Df 861"1
97E1 E9I)~
9788919
97E5 744f
97E7 B8BB
97E9 746R
97ED 99EF
97m Ilfl9E
97EF 249R
9i'Fl 744f
•••" ••*.*
COOCBlK 2J
=6435+
ORG
2011
=6439 ; EPS1Er RELEASES EP TO RUN IN PRESENT "00[ lRlTIL AN f1NTICIPAlm
=6449 ;
IfflROWARE BREAK OCCURS.
=6441 ;
(DUE TO SINGLl STEPPING, UNK Il'Coo[ FETCH. ~ LINk DPoTA mCH. )
=6442 ;
I'IUST OC~ WIlHIN fI FINITE NUlt3ER Of ClUES «49 I1f' CYClES)
=6443 ;
OR IoIATCHDOG TIMER WILL RSSUME A COMtlUHICATIONS [R~OR
=6444 ;
BETWEEN TI[ If' I1lD EP.
=6445 EPSTEP: CALL
EPREl
=6446
I'IOV
R1, 119
=6447 EPSTE1: JNI
EPSTE2
=6448
DJNZ
Ri, EPSTEt
=6449
ORL
Pl. iEPRSET
=6450
CtlLL
EPERK
=6451
MOIJ
[,\1, ilOlolWY1BA5+0IlS1ZE)
=6452
Cflll
O't'LOAD
=6453
ANI..
Pi, INOT EPRSET
=6454
1'1011
LDATA, .9E1l
=6455
JIf'
PERROR
E~'IlRK
=6456 trSTE2: CALL
97f3 83
=6457
=6458
9919
=6461+ SIZE SI:."T
=6462+;
=6463+;
RET
SIZECHK .
25
**"'******************_*'1"'****__**_*********_
=6472 ;
=6473 ;
=6474 *EJECT
All mnemonics copyrighted @ Intel Corporation 1976.
1-149
intJ
LOC OOJ
AP·55A
LINE
SOlE[
=6475
COOEBLK 9
=6510~'
1l7F4
07r4
07F6
07F8
07FA
07FC
STflTEI£NT
ORG
2036
=6514 ; fJ'REL RELEASES Er TO
IN PRESENT 1I00I:.
=6515 ;
Sl:QUENCE IS AS FOLLOWS:
=6:116 ;
PUT 1'IEI'llR\' flRRA',' IN EP I'IOOE;
99f7
890S
9fI3F"
8904
83
m.
=6517 ;
RAISE ISSTEP;
=6518 ;
RETURN.
=6519 EPREL: fK.
Pi. lOOT CLREFF
=6529
P1,ICLRBFF
OR\..
=6521
IK.
P2. lOOT 010II08II0B
=6522
ORL
PL 10000010011
=6523
RET
=6524
SIZECH<
=6527+ SIZE SET 9
; CLEAR BREAK FIF.
; RE-OHlLE BREAK f IF.
; ElflBLE Er COOTRll. IF IEII fRRtW
; fREE EP TO RUN tllTIL 1J.'EflK.
=652St;
=65:ro ;
=6519 ;
034f
034F 99FB
03:51 8929
8353 B995
0355 E955
0357 9A48
0359 83
11
=6540
=6588+
COOEBI.J(
=G5B4 ; EPBRK
=6565 ;
=6586 ;
~7 ;
REGAIN COOTROL Cf I'EJ'IOR',' ARRftY FRa'I EP.
DROP ISS1EP;
IIIIT 30 USECS.;
PUT IDORY ARRfI\' IN If' i'IOOE;
=6508 ;
RETLm
ORG
=6589 EPBRK: fK.
=65S0
0I\'l
=6591
t«lY
=6592
=6593
=6594
=6595
=6598+ SIZE
=6599";
()JNZ
047
PL lOOT 000001000
Pi. II'IOOOUT
Ri. 15
R1, $
P2,I010001l001l
ORL
REl
SIZECHK
SET 11
; FRlEZE ElU.ATION PROCES!;(R.
; SIGIR. EI' IS ooT RIHIING USER COOE.
; 1>EUl\' FOR Ef' TO FINISH INSTROCTION.
; SEIZE CONTROL or I'IEJ'I ARRfl','.
=6609 ;
9351: 0917
=6610 ;
=6611
=6651+
=6655 ; OYSWAP
=665C ;
=6657 0\I5IflP:
=665S
835E 2340
=6659
0:s60 3A
0361 ca
=6G60
=6661 OYSWi:
=6662
DEC
I)(C
R1
=,6663
I1OY'O<
Ii, @R1
ItJV;<
fl, @R0
@R1. A
0351\
8J5A B865
8362 C9
0363 81
0364 20
0365 91
0366 F9
83679661
8369 83
=66(;4
=6665
=6666
=6667
=6668
=6669
COOEBLK 16
ORG
S5fJ
OVERLAY !;Wff.
SWAPS BLOCK OF DAlf1B','TES (USER'S
/'lOY
RIl,IOYIlI..f+OIlSIZE
I10V
Ri. IOYSIZE
/'lOY
R. l01i10OO0eB
OUTL
Fr.?, A
xi:H
R0
I'IOV
A, Rl
JHZ
RET
OYSII1
SIZ[CHI{
=6672+ SIZE SET 16
All mnemonics copyrighted @ Intel Corporation 1976.
1-150
~)
BETIEEN '" RAI'I & EP PIt
AP·55A
LOC OOJ
LINE
S(uCE
~TRT[Il.NT
=6673+;
8361l
8J6A
936C
9J6E
936r
8370
8371
93"12
9373
8374
8375
8377
=6674+; ***-.*****-****~:*********~:*************-*********.*.
=6603 ;
=li684
COOEBLK 14
=6724+
(J.'G
874 .
=6728 ;
OYERLA'I' LOAD.
=6729 ;
I'KM$ IlLOCK Of OOTAEYTES (flSSlllliD ~(''E) fRc.I PG3 10 EP PII.
=6739 ;
TOP Of DIlTA BLOCK LOAI)(]) AI«) BLOCK lEMlTIl DETERtlIIf:D B\' 1!9 IliI Ri.
=67J1 OYLOOD: IIOY
R1.IOYSIZE
=67J2
tIOV
A, 1019080000
=e7J3
OUTl
f'2, A
=6734 IIL01: DEC
R8
=6735 '
DEC
R1
=6736
MOY
fl, R9
=G737
MOYP3 fI, @A
=6738
I'XJYX
~1, A
=6739
MOY
fk R1
=6740
JNZ
191..01
=6741
RET
=6742
SIZECI-IK
=6745+ SIZE SET 14
=6746+;
ovum
1l91i'
2340
3f!
C9
C9
Fa
EJ
91
F9
9G6f
83
_****_********__*************11:****_************
=6747+;
=6756 $EJECT
All mnemonics copyrighted © Intel Corporation 1976.
1-151
inter
lOC OOJ
AP·55A
Uti:
SOO!CE STRTDENT
=OlS7 ;
,=6758 ;
=6759 ;
=6768 ;
=6761 ;
=6762;
=6763 ;
=6764 ;
=6765 ;
=6766
=6771+
8178
=6775 ;
=6776 ;0Y8~mi
=6778 ;
=6779 ;
=6789;
8378
8378
8378 1489
rnA 88
8378
8378 1489
837D 88
837E 88
837F
837F
8381
8382
8383
1489
88
88
88
8384 88
8385
8386
8387
8388
8389
118
88
88
88
88
83SR 88
8388 88
838C
838C
8816
84w.)
11£ REST (f lHIS PIOOllE COO'A1NS THE "INI-fOUTIJ1S IfIICH OYm.R'1'
11£ EIllRTIIII f'ROCESSG< PI\'OG:RIf RfII 10 GIVE 11£
/lASTER PROCESSCJ: ACCESS 10 INlERIR. REGISTERS IN> RAIl IX- 11£ Ef'.
DflTfW(
22
~
80S
OYERI.RY 10
IIREfI( EP EXECU"l11II fIN) JlJIP TO lOCRTIIII 8II9H.
lOCRTIIII II8SII REfICIEI) WITH T(J'-(f"-STfO. = RETWI OODRESS+2
DIE TO FIJ1CEI) "CAll" DURING IfIICH PC IllS INCREII.NTED.
lOC!; 88JH & 887H CfLll!99H TO SIIUlITE ~ ctN>1TI0N
IF BREAK ~ DURING INll"Rru'T C\'Cl.E.
SOl(!CE CODE FIJ:1 mNI--IDInm 0YERlA\'ED OYER lOll ImDER PROOkRII RAIl. .
=67!l1;
=6782 ;
$
=6783 0\IIl8RS EQU
=67fJ4 ~
OYIIBRS
=6785
CAll
089H
=6786
=6787
=6788
=6789
10>
i
~
=6798
0Y9IIRS+883H
CIU
8891-1
10>
=6791
=6792;
=6793 ~
I«JI'
~f94
CIlll
10>
=6795
=6796
=6797
=6798
=6(99
=6S08
=6881
0V9BflS+887H
N(J'
I«JI'
to'
NO!'
NOP
=6882
10>
NO/'
=6883
NO!'
=6884
=6885
=6Il86 ;
10>
=6S87 ORG·
=6888
=6889 i
=6818
=6813+ SIZE
8891-1
NOP
OY8IIRS+814H
8891-1.
JI1I'
SIi::ECII<
SET 22
=6814+;
=6815+;-**=61124 $EJECT
All mnemonics copyrighted @ Intel Corporation t976.
1-152
inter
LOC OOJ
838E
838E
83CE
938E 9499
8399 09
AP·55A
LINE
=6825
=68J9+
=6834 ;
=6835 ;fRJ=6IlJ6 ;
=68J7 ;
=6839 ;
=68J9 ;
=6Il49OVJBAS
=6841 ORG
=6842
=684J
SWkC[
STATEI'ENT
DflTIIlLK 22
919
ORG
OYERLR't' TO SAVE STATUS DflTA IFTER 1lREfJ<,
fICC. TIPlER/COUNTER. PSW (WITH F1). & RflII LOC 9 PASSED SEQl(If1 IfillY
10 1'1'.
Slm:E COOE FOR "INI -IIlNITOR OVERLA\,ED OYER LOll ORDER I'ROGRffI RIll.
EQU
$
O'r'3IlAS
JI'IP
MH
NOr
=6844 ;
8391
8391
9392
9393
8394
83
09
09
09
9395
9395 83
85% 09
8'397
839799
8398 42
8399 99
8l9f1 C7
8398 7611
8390 53F7
8311
939F 99
83A9 C5
83A1 Fe
83R2 9499
9916
=6845 ORO,
=6846
=6847
=6Il48
=6849
=6S59 ;
=6851 OOG
=6852
=6B53
=CS54 ;
=6S55 ORG
=6856
=6857
=6858
=6859
=CS69
=C861
=6862 0Y3Il1
=6863
=6864
OV3IlAS+99JH
RET
NO!'
NOI'
Na'
fR3BAStll97H
RET
NOf'
0Y3IIA5+1l99H
tIOVX
~.A
I'IOY
I'KlYX
I'IOY
@R8.A
A. T
A./'SW
JF1
fR3B1
11. 1111191118
(LOW 0Y3IlfIS)
IN..
*-
roo
I'IOYX
~.fl
=C865
I'IOY
RB0
A.Re
=C866
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DINTRG 8169
DlST 914E
DREC 9151
DREL 0154
DSFtO 0194
DSPI'I1 B192
ELSIF1 9007
ELSlf2 09£5
ENOREC 9641
EOfREC 05AE
EPPflSS 9709
EPPClII 9925
EPRUN1 848A
EPRUN 9489
EPSTEi 87DF
EPm207F1
EXAPI2 92£:1
EXAH3 028fl
rDUl'l'4 064S
FDUlf'3 9C36
flBlTHI 8927
HBDlflY 94C9
HFILEO 9572
HRECIN 9297
IR:GF 1182F
II'IPLEI'I 0200
1NPf:DR 9IlC9
INPKE'r' OOEC
JTOLST 921Il
JTImOD 029F
KCLRIl 999C
KE'1'
0093
rntoc 983(; KEYLST 981C
KEYREL 9814
KI.'YTRfi 0919
LFEBRK 86B1 . Lr~ 11698
LfILL 92E9
LFILLl 1k"f3
LSTORE 8789
LSTPII !l79C
IflDOC 8925
MAIN 8929
I'IAIND 9993
I'IAIN>l 8007
I'IERROR Il9IlC
MINC 89211
I1RLC 0931
IIRR
002F
NIBI3 81C2
NIBIN 9188
NXTLOC 87CS
OPTAB1 933f
ORGPG3 93E9
0RGI'G4 84fD
0V9ElAS 9378
OV1B1 89!lR
0VBlF 004E
OYLOflD 936A
PGSIZE OOFD
PINPUT 999lJ
All mnemonics copyrighted © Intel
?B
?BiPNT
?IlllO'
?DEBNC
?EPPSW
?H
Corporati~n
?BIlf'NT eeec
?B1R2 9993
?BITSO 9003
?I)<".,/'n
?IlI'IR2
?B1R3
?BtfCN
?DSPTI1
?EJ'TlI'I
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0002
e994
9982
8900
09Il2
0092
?ITII' 0009
?IJ'R0 ilOO2
?IIH"iH 0082
?I-REGF 99Il2
?LE:t«iT 99EII)
?NREPT Il9Il2
?lE1II1
?tu1CO
?Rf!8
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?YERSN
ElITSO
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0002
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SCOOE
BVTEl1
CGOIIl
CI9
CLRBFr
CO2
CTAB
009Il
992A
89j6
99F2
DCB
915A
94F5
9146
91C3
81S1l
003J
9929
0024
9499
970B
0293
11632
11026
8699
01F2
0389
9211
0017
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DI'IOD
Dim
DSPI'IID
Emf-II
EPACC
Erf'CLO
EPRUN2
EPSTEP
EXIlI4
FDIJf'S
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INCSl'IA
INVALS
JTOREC
KE'lCLR
8993
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0000
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LFtlNT 96AS
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NIBIN2 91BA
OPTAB2 9346
ORGPG5 95FF
0Y1B2 8313
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PLUS1 0091
8002
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8Il89
9083
8002
9900
II~'TEIN 99F9
CHARC~ il90D
9651
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CMl>INT 89I3A
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OCRROR 9131
DNOBRK 9168
DRUN 8m
DSPTlII 0028
EI'1AI..O 0!l32
EPElRI( 834F
EPPSW 0021
EPRUN3 9495
H'STIJI 97C3
\:XAI'IS 9275
FINDOI' 0942
HDATIN 82B9
HREGA 11021-1
INCW 91F4
lTl'1I'
99Il4
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KE'r'DI1 9916
KE'r'NXI 9912
KSETB 9Il9B
LFEPI'I 11684
LSTBR1 9746
~lREG 8726
IflINA 11052
IIllOCK 9Il82
I'IIOY 8928
I1XCH 8929
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OPTAIB 8349
0RGP66 96FF
OV1BAS 93A4
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1-171
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m'PAT 9815
LASTKY 9Il94
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0\I3t'1 9311
I'DIGIT 898t
f'C..EGlil I!9!j()
intJ
AP·55A
APPENDIX C
COMMAND SUMMARY
Program execution commands:
The following is a summary of the commands implemented by the HSE-49 emulator monitor. Within each
command group, tokens in each column indicate options the user has when invoking those commands.
Tokens in square brackets indicate dedicated keys on
the keyboard (some keys having shared functions);
angle brackets enclose hex digit strings used to specify
an address or data parameter. Parameters in parentheses are optional, with the effects explained above.
The notation used is as follows:
Program/data entry and verific;ation commands:
[EXAMI
[PROG MEMJ" [.) [NEXl]
[DATA MEM)
[PREy]
[REGISTER)
[.)
[HWRE REG)
[PROG BRK)
[DATA BRK)
Program/data initialization commands:
[FILL)
[PROG MEM)- [.) [,I [.)
[DATA MEM)
[REGISTER)
[HWRE REG)
[PROG BRK)
[DATA BRK)
Intellec@ development system or TTY interface commands (for transferring HEX format files):
[UPLOAD)
.[DNLOAD)
[PROG MEM)' [,) [.)
[DATA MEM)
[REGISTER)
[HWRE REG)
[PROG BRK)
[DATA BRK)
[PROG MEM)' [.)
[DATA MEM)
[REGISTER)
[HWRE REG)
[PROG BRK)
[DATA BRK)
Formatted data dump t9 TTY or CRT:
[LIST]
[PROG MEM)' [,) [.)
[DATA MEM)
[REGISTER)
[HWRE REG)
[PROG BRK)
[DATA BRK)
[NO BREAK)' «SMA» [.)
[WI BREAK)
[,)
[SING STp)
[AUTO BRK)
[AUTO STp)
[GO/RSl]
[NO BREAK)' [.)
[WI BREAK)
[SINGSTP)
[AUTO BRK)
[AUTO STP)
Breakpoint setting and c[earing:
[SET BRK)
- Starting Memory Address for block command,
- Ending Memory Address for block command,
- LOCation for Individual accesses,
- DATA byte.
Asterisks (*) indicate the default condition for each
command; thus that token is optional and serves to
regularize the command syntax.
[GO)
[PROG MEMJ" «,) ... ) [.J
[DATAMEMJ
.
[CLR BRKJ [PROG MEMJ' ([,J ... ) [.J
[DATA MEM)
APPENDIX 0
ERROR MESSAGES
The following error message codes are used by the
monitor software to report an operator or hardware error. Errors may be c[eared by pressing [CLR/PREV] or
[END/.]. The format used for reporting errors is
"Error- .n" where "n" is a hex digit.
Operator Errors
1. IIlega[ command initiator.
2. Illegal command modifier or parameter digit.
3. Illegal terminator for Examine command.
4. Illegal attempt to c[ear Error mode.
5-9. Not used.
Hardware Errors
A. ASCII error - non-hex digit encountered in data
field of hex f9rmat record.
B. Breakpoint error. Break logic activated though breakpOints not enabled.
C. Hex format record checksum error. Note - the
checksum will not be verified if the first character of
the checksum field is a question mark ("?") rather
than a hexidecimal digit. This allows object files to
be patched using the ISIS text editor without the
necessity of manually recomputing the checksum
value.
D. Not used.
E. Execution processor failed to respond to a command
or parameter passed to it by the master processor.
EP automatically reset. EP internal status may be
lost. Program memory not affected.
F. Not used.
All mnemonics copyrlghted©lntel Corporation 1976.
1-172
APPLICATION
NOTE
Ap·91
INTEL CORPORATION ASSUMES NO RESPONSIBIlITY FOR THE USE OF ANY CIRCUITRY OTHER THAN CIRCUITRY EMBODIED IN AN INTEL PRODUCT. NO OTHER CIRCUIT PATENT LICENSES ARE IMPLIED.
©INTElCORPORATlON.1979
AFN.(J1364A..()1
1-173
i~
AP·91
USING THE 8049 AS AN 80 COLUMN
PRINTER CONTROLLER
I. INTRODUCTION
This Application Note details using INTEL's 8049
microcomputer as a dot matrix printer controller.
Previous INTEL Application notes, (e.g. AP-27 and
AP-54) described using intelligent processors and peripherals to control single printer mechanisms. This
Application note expands upon the theme established
in these prior notes and extends the concept to include
a complete bi-directional 80 column printer using a
single line buffer. For convenience this application
note is divided into six sections:
1. INTRODUCTION
2. ·PRINT MECHANISM DESCRIPTION
3. INTERFACE CIRCUITRY
4. SOFTWARE
. 5. CONCLUSION
6. APPENDIX
Over the last few years 80 column output devices have
become· somewhat of a defacto output standard forbusiness and some data processing applications. It
should be mentioned that by no means is the 80
column format a "new" standard. 80 column computer
cards have been around for more than 20 years and
perhaps the existence of these cards in the early days
of computers is why the 80 column format is a standard
today.
Many CRT terminals use the 80 by N format and
to complement this a number of printers use this same
format. One reason, aside from those historic in
nature, for the 80 column standard is that 80 columns
of 12 pitch text on standard typewritten 8.5 inch by
11 inch paper completely fills up an entire line and allow ample room for margins. So, the 80 column format
is an aesthetically convenient format.
Printers are usually divided into either impact or nonimpact and a character or line oriented device. Impact
printers actually use some type of "striker" to place
ink on the paper. More often than not the ink is
contained on a ribbon which is placed between the
striker and the paper. ·Non-impact printers use some
means· other than direct pressure to place the characters on the paper. This type of printer is very fast because there is very little mechanical motion associated
with placing the characters on the paper.. However,
because the paper is required to be treated with a
special substance, it is not as convenient as an impact
.
printer.
Character printers are capable of printing one character at a time. (Any standard home typewriter is in
effect a character printer.) Line printers must print an
1-174
entire line at a time. Line printers are usually quite
a bit faster than character printers, but they usually
don't offer the print quality of character printers.
In recent years, the "computer boom" has caused the
price of printers to tumble markedly.. High volume
production, competition, and the tremendous demand
for reliable print mechanisms have all corttributed to
the decrease in price. Because of their simplicity, line
printer mechanisms have decreased in price faster
than other mechanisms. Therefore, when high quality
print is not needed, a line printer is a very attractive
choice.
This application note describes how to control all 80
column impact-line printer with an 8049/8039. The
complete software listing is included in the appendix.
The 8049 is the high-performance member of the MCS48TM microcontroller family. The Processor has all of
the features of the 8048 plus twice the amount of pro-·
gram and data memory· and an llMHz clock speed.
For details about the 8049, please refer to the MCS-48
user's manual.
II. PRINT MECHANISM DESCRIPTION
The model 820 printer is available from C. .ITOH
ELECTRONICS (5301 BEETHOVEN STREET, LOS
ANGELES, CA 90066). This inexpensive and simple
printer is ideal for applications requiring 80 columns
of dot matrix alpha-numeric information.
The model 820 printer is comprised of three basic
sub-assemblies; the chassis or frame, the paper feed .
mechanism, and the print head. The diagram in Figure 2.1 ~ves the physical dimensions of the basic print .
mechanis~. The basic chassis for the printer is constructed out of four sheet metal stampings. These
stampings are screwed together to form a sturdy base
on which all other components of the printer are
mounted.
The paper feed mechanism consists of a toothed wheel,
a solenoid, a tension spril)g, and a "catcher." When the
solenoid is activated, the arm of the solenoid pulls
against the spring and drags over the toothed wheel.
When the solenoid is released, its arm is pulled by the
spring, but this time the arm grabs a tooth on the
wheel and pulls the wheel forward which advances the
paper. A "catcher," which is merely a piece of plastic
held against the toothed wheel, is added. to assure
that the paper is advanced only one "tooth" position
each time the solenoid is activated.
The print head is comprised of seven solenoids which
are mounted in a common housing. The solenoids are
physically mounted in a circle, but their hammers are
positioned linearly along the vertical axis. These
seven vertically positioned hammers are the strikers
that actually do the printing.
.
intJ
Ap·91
~
649(164'8):~
5.63 (143.0)·~
~2~1463(117.6)
..L
T
_
'1
"
:'.,.,
""
9B8~0015
(251 0
~
1038
(263.6)
04)
r--gL
025
(64)
I
fu2~.
--1
Q,
I
~-4 77 (121 2)~
j3)
3.32.
___
H
MARGIN FOR HEAD
CABLE ROUTING'
--~-.1132(287.5),----------I
__ ~ _ _ _ ".82 ± 0.015
(3002 ± 0.4)
1-----6.18(157.0)----
UNIT INCH (MM)
DIMENSIONS IN INCH GOVERN
Figure 2.1 Physical Dimensions of C. ITOH Model
820 Printer
~~~~~
~
~
~.~~~
~
~
~~~~rx1
Figure 2.2 "Formation" of a Character by a Dot
, Matrix Printer
PRINT
WIRE
2
3
4
5
6
7
A motor. mounted toward the back of the print mechanism. drives a rubber toothed belt which turns a roller guide. A motor turns a guide that moves the
print head from right to left and left to right. By properly timing the current flow through the solenoids
while the print head is moving across the paper, char·
acters can be formed. Figure 2.2 illustrates how the
dot matrix printer "forms" its characters.
The timing pulses for the print head mechanism are
generated by an opto-electronic sensor. This sensor,
located on the left side plate of the printer, informs
the print controller.when to apply current to the print
head mechanism. This "on-board timing wheel" assures
that all characters will be properly spaced and that
they will all be "in-line" in a vertical sense.
The print mechanism is also equipped with two additional sensors. Th~se are the left home position
sensor. located near the left front of the mechanism.
and the right home position sensor, located near the
right front of the print mechanism. These sensors
simply tell the controller when the print head is in
either the left or right home position. A complete
timing chart for the printer is shown in Figure 2.3.
III. INTERFACE CIRCUITRY
The manual supplied with the printer recommends
some specific interface circuitry. For the most part
the circuitry used in this Application Note followed
these suggestions. The circuitry needed to drive the
print head solenoid is shown in Figure 3.1. This same
1-175
intJ
AP·91
MOTOR POWER
LEFT HOME FLAG
~:F
-I
,
I
1-
~--------
75-1(10 ms
(IN CASE MOTOR OFFl ::: -
~::~-----,~----------------------------------------------~------~
DARK
RIGHT HOME FLAG
-.J
I
LIGHT -----.,;----------------------......11
I
~
'ms._
L TO R PAINT
53BmsNOMINAl
-
TIMING PULSES
ISCALENOTPROPORTIONALI
PAPER FEED POWER
OFF
1_
J1
'-------!I--------- M
t
t
1-
"7"""---------------------------------
-I -,
I
5ms(DELAYFORALlGNMENn
R TO L PRINT
538msNOMINAl
-
--t 1- ~gM~~AI
--~
J\M
t
------~r-------
M
,
-~S_--
T~""
T,
T480
-I
~
1..
179 m$
--NOMINAl--
Tt
ON
-I Nb~,o;;~L
r-----1
1-'S-20ms
-I
__________---'n
I_lOoms
nnFL_f1_
(PAPER SLEWINGl
Figure 2.3 Timing Diagram of C. ITOH
Model 820 Printer
+ 5V
and converted to TTL levels in order to interface to
the controller. This conversion is accomplished with a
simple voltage comparator. Figure 3.2 'is a schematic
of the sensor interface circuitry. Note that hysterisis
is employed on the voltage comparators. This eliminates "false" sensing,
~ 5%
S'
SOLENOID
Tr,
A,
250633
33OQ.lIBW
R2
13Q::t5°'o.5W
RJ
lkO,l12W
o
38Z61
C
G
l",F l00V
SN74060A EQUIVALENT
33K
>"'1-.,.--0
OUTPUT
Figure 3.1 Solenoid Drive Circuit
(Eliminate R2 for Line Feed Solenoid)
circuit is used to drive the line feed solenoid except
that the current limiting resistor R2 is eliminated.
This resistor is not needed because the line feed solenoid is physically much larger than the print head solenoids and can'tolerate much higher levels of current.
The print head drivers are connected to an 8212
latch. The latch is interfaced to the BUS PORT on the
8049 and is enabled whenever the WR pin and the BIT 4
of PORT 1 are coincidentally low. The line feed driver
is connected to PORT 1 BIT 1 of the 8049.
Note that the driver is simply a Darlington transistor
that is driven by an open collector TTL gate. Resistor
R2 is the current limiting resistor and diode D. capacitor C. and resistor R3 are used to "dampen" the inductive spike that occurs when driving solenoid S.
This circuit is repeated for each of the seven solenoids
in the print head. It should be mentioned that. although the type of Darlington transistor needed to
drive the print head is not critical. a collector current
rating of at least 5 amps and a breakdown voltage
(Vceo) of at least 100 volts is needed. Transistors that
do not meet these requirements will, be damaged by
the inductive kickback of the solenoids.
As mentioned in Section 2. the printer provides some
sensor interface signals that are derived via three opt(}electronic sensors. These signals must be amplified
56K
Figure 3.2 Example of Sensor Circuit
Motor control is accomplished by using a Monsanto'
MCS-6200 optically-coupled TRIAC. This part is ideal
in this kind of application because it provides a simple
means of controlling a line-operated motor without
sacrificing the isolation needed for safe and reliable
operation. Figure 3.3 is a schematic of the motor driving circuit.
+5
YELLOW
\
soov
7
TOR
rBLK/RED
NEU
HOT
'---..--/
,'SVAC60HZ
Figure 3.3 Motor Driving Circuit
1-176
Ap·91
To interface 8049 to the outside world one 8212 latch
was used. This latch was connected to the BUS PORT
and is enabled by an INS or MOVX instruction coincident with BIT 4 of PORT 1 being in a logical zero
state. In this configuration, the 8212 was used to hold
the data until read by the 8049. The connection of
the 8212 to the 8049 is shown in Figure 3.4 and the
parallel port timing diagram is shown in Figure 3.5.
The 8212 parallel port was connected to the LINE
PRINTER OUTPUT of an INTELLEC MICROCOMPUTER DEVELOPMENT SYSTEM.
C
~
010
0"
--i; Db
INPUT
LINE
S
-fa 0:01,
~
01.
20 Db
~~ 01.
8212
gg; :
DEl<>
DB.
DB,
DB,
DB.
DB,
De.
DB,
00,
Db~ 10
DO~ 1
DO.
00,14
DOa 21
OS.
This routine also initializes all of the variables used by
the printer.
The INPUT ROUTINE reads the characters that are
present in the 8212 input port and writes them into the
8049's buffer memory. The routine then checks the
characters to see if a CARRIAGE RETURN (ASCII
OCH) has been transmitted. If a CR is detected, the
input routine automatically inserts a LINE FEED as
the next character. When the input routine detects a
LINE FEED, it stops reading characters and sets the
direction bits and the print bit in the status register.
This action evokes the OUTPUT ROUTINE. A detailed
flowchart of the INPUT ROUTINE is shown in Figure
4.1.
8049
RO
OS,
<}-- PI.
INT
TO
I
BUSY
Figure 3.4 Connection of the 8212
Input Port to the 8049
DATA
~~------------------U
BUSY
ACKNLG
~r-------------,~___
--'----------L-S
I----VARIABLE T I M E : - - - - I
Figure 3.5 Parallel Port Timing
IV. SOFTWARE
As mentioned in Section 2, the bulk of the timing
needed to control the printer is actually generated by
the printer itself. Therefore, all the software must do
is harness these timing signals and turn on and off the
right solenoids at the right time.
To make things easy, the software needed to drive
the printer is broken into four separate routines.
These are:
1. INITIALIZATION ROUTINE
2. INPUT ROUTINE
3. OUTPUT ROUTINE
4. LOOKUP ROUTINE
The INITIALIZATION ROUTINE turns the motor on
and checks the opto-electronic sensors. If a failure is
found, the routine turns off the motor and loops on itself. This insures that the print mechanism is cycled
properly before characters are accepted for printing.
Figure 4:1 Input Routine Flowchart
1-177
AP·91
The OUTPUT ROUTINE initializes both the input and
output buffer pointers and then reads the characters
from the 8049's buffer memory. After a character
is read the OUTPUT ROUTINE calls the LOOKUP
ROUTINE which reads the proper bit pattern to form
that character. This bit pattern is then used to strobe
the solenoids. After each character is printed, the
OUTPUT ROUTINE calls the INPUT ROUTINE and
another character is placed into the buffer memory.
This type of operation guarantees that the input buffer
cannot "overrun" the output buffer. A flowchart
of the OUTPUT ROUTINE is shown in Figure 4.2.
Initially the input buffer pointer is loaded with the ad·
dress of the first location in the buffer memory. As
characters are read, the input buffer pointer incre·
ments and fills the buffer memory as shown in Figure
4.3(b) through 4.3(f). When a CARRIAGE RETURNLINE FEED (CRLF) is encountered the input buffer
pointer and the output buffer pointer are reset back to
the first location. The OUTPUT ROUTINE then reads
the character from the first location in the buffer memory, increments the output buffer pointer and calls the
INPUT ROUTINE, which reads another character
from the parallel input port.
The OUTPUT ROUTINE, reads the e,ntire buffer, inserting space codes (20H) after a CR is detected,
and the input buffer pointer follo~s the output buffer
pointer as they "increment" up to the buffer memory.
When the OUTPUT ROUTINE has printed the last
character or space, the output buffer pointer and the
input buffer pointer are set to point at the last location
of the buffer memory. The OUTPUT ROUTINE then
reads the character from the last location of the buffer
memory and proceeds to "decrement" down the buffer
memory. Space codes are inserted until a CR is found.
Figure 4.3(1) to 4.3(0).
The input buffer pointer follows the output buffer
. pointer just as in the previous case. When the last,
or in this case the first character is printed, the output
buffer pointer and the input buffer pointer are set to'
point at the last location of the buffer memory. Now
the pointers are "decrementing" down the buffer
memory, but the printer is actually printing in a "normal" left to right fashion.
When the last character or space is printed, the output
buffer and the input buffer pointer are set to the first
location of the buffer memory and printing takes place
in a reverse or right to left manner. After this line
is printed, the print head and both buffer pOinters are
in the same position as they were initially. So, four
lines must be printed before the buffer pointers and
the print head complete a cycle. Each of these situations is handled separately by four different subroutines: CAS EO, CASEl, CASE2, and CASE3.
IV·II. TIMING
Figure '4.2 Output Routine Flowchart
IV·I. HANDLING THE 1/0 BUFFER
Since the C. ITOH Model 820 printer is capable of
printing in both directions the 80 character buffer
must be manipulated in a manner as to allow maximum
input-output efficiency. This is accomplished by reversing the "direction" of the buffer memory each time
the printer is printing from right to left. For simplicity, if it is assumed that the buffer is only five bytes
long, Figure 4.3 can be used to help explain the buffer
operation.
All critical timing for the printer controller came from
two basic sources; the timing sensors on the printer
and the internal eight-bit timer of the 8049.
The internal timer of the 8049 was used to control
the length of time the solenoids, were fired (600
microseconds) and was also used as a "one-shot" to
align the printer. This alignment is needed to make
the "backward" printing line up vertically with the
normal or forward printing. The "one-shot" is used to
measure the time from the last column of the last
character position until the right sensor flag is covered.
1-178
inter
4.3A
Ap·91
BUFFER MEMORY
INPUT BUFFER
4.38
4.3P
OUTPUT BUFFER
OUTPUT BUFFER
1: 1
,
INPUT BUFFER
4.30
BUFFER MEMORY
INPUT BUFFER
4.3R
OUTPUT BUFFER
BUFFER MEMORY
INPUT BUFFER
4.30
4.3E
,
BUFFER MEMORY
A
1
I Ic
INPUT BUFFER
4.35
1
INPUT BUFFER
4.3T
BUFFER MEMORY
4.3F
4.3G
4.3H
4.31
4.3J
4.3K
4.3L
4.3M
INPUT BUFFER
4.3U
OUTPUT BUFFER
BUFr:ER MEMORY
BUFFER MEMORY
INPUT BUFFER
INPUT BUFFER
4.3V
OUTPUT BUFFER
OUTPUT BUFFER
BUFFER MEMORY
BUFFER MEMORY
INPUT BUFFER
INPUT BUFFER
4.3W
OUTPUT BUFFER
OUTPUT BUFFER
BUFFER MEMORY
BUFFER MEMORY
INPUT BUFFER
INPUT BUFFER
4.3X
OUTPUT BUFFER
OUTPUT BUFFER
BUFFER MEMORY
BUFFER MEMORY
INPUT BUFFER
INPUT BUFFER
4.3Y
OUTPUT BUFFER
OUTPUT BUFFER
BUFFER MEMORY
BUFFER MEMORY
INPUT BUFFER
INPUT BUFFER
4.3Z
OUTPUT BUFFER
OUTPUT BUFFER
BUFFER MEMORY
BUFFER MEMORY
INPUT BUFFER
INPUT BUFFER
4.3AA
OUTPUT BUFFER
OUTPUT BUFFER
BUFFER MEMORY
BUFFER MEMORY
INPUT BUFFER
INPUT BUFFER
4.388
OUTPUT BUFFER
INPUT BUFFER
4.30
OUTPUT BUFFER
BUFFER MEMORY
1
OUTPUT BUFFER
BUFFER MEMORY
4~3N
OUTPUT BUFFER
BUFFER MEMORY
B
OUTPUT BUFFER
INPUT BUFFER
OUTPUT BUFFER
BUFFER MEMORy
OUTPUT BUFFER
INPUT BUFFER
OUTPUT BUFFER
BUFFER MEMORY
1
INPUT BUFFER
4.3C
OUTPUT BUFFER·
BUFFER MEMORY
I
IJ
OUTPUT BUFFER
BUFFER MEMORY
1
INPUT BUFFER
4.3CC
OUTPUT BUFFER
OUTPUT BUFFER
BUFFER MEMORY
BUFFER MEMORY
INPUT BUFFER
INPUT BUFFER
4.300
OUTPUT BUFFER
OUTPUT BUFFER
BUFFER MEMORY
BUFFER MEMORY
INPUT BUFFER
INPUT BUFFER
Figure 4.3 1/0 8uffer Handler
1-179
a
AP·91
When the print head reverses direction and the right
sensor flag is uncovered. the timer is then used to
determine where to start printing in the reverse
direction.
The timer and the print wheel on the printer are used
to determine when to place a character. The strobe
from the print wheel informs the 8049 when to fire the
solenoids and the timer allows the proper spacing
between the characters .
. V. CONCLUSION
Although the full speed of the 8049 was not used
in this application. the high speed of the 8049 makes it
possible to "fine·tune" any critical timing parameters.
Additionally. the extra available CPU time could be
used to add an interrupt driven keyboard and display.
such as the ones discussed in AP-40. to the printer.
This would allow the printer to function as a complete
"terminal".
Very little attempt was made to optimize the software.
but still the entire program fits easily in 1.25K of
memory; 750 bytes for printer control and 500 bytes
for character lookup. Adding lower case to the printer
would require an additional 500 bytes of lookup table.
·The remaining 250 bytes should be used to add "user"
features such as tabs. double width printing. etc.
The high speed of the 8049 combined with its hardware and software architecture make it an ideal choice
for controlling an 80 column. bi-directionalline printer.
The 1/0 structure of the 8049 minimizes the amount
of external hardware needed to control the printer and
the large amount of on-board program and data memory allow quite a sophisticated control program to be
implemented.
1-180
APPENDIX A. SCHEMATIC DIAGRAM
(
+ 5 VOLTS
~
11.0 MHZ
XTAL
2 XTAL 1
=
I
,.
I
,
,
15pF
P11~
2,uF
2716
PlO 27
rlRESET
I
OPTO·TRIAC
MOTOR DRIVER ~
r---------------------------------,
3 XTAL 2
8049
8039
P20~
P21 ~ ...
P23
TO
PSEN
WR
RD
DBa
DB1
DB2
DB3
DB.
DB5
DB6
DB7
......
,
......
~
<0
1
9
10
8
12
13
14
15
16
17
18
19
I
21
19
17
15
10
8
6
4
008
007
006
005
004
003
002
DO,
8212
018 22
017 20
016 18
0151-1:..::..---,
014 9
013 7
012 5
Db 3
L
THE 8212 AND THE 2716
WOULD NOT BE NEEDED IF
AN 8049 WAS USED INSTEAD
OF AN 8039
~-----ll SOLENOID DRIVER #11
r---i
SOLENOID DRIVER #21
r---1S0LENOID DRIVER #31
DS2
J~"UV"
1
2
3
4
5
6
7
8
l
1 23
D01DS1 INT
DO,
003
004
L.---:~D05 8212
L._ _ _1~5HD06
L.._ _ _--.;.1;M7 007
L-_ _ _ _~1~~~D08
~
A7
A6
As
A4
AJ
A2
A1
LINE FEED
DRIVER
~2
011
012
013
014
0,5
016
017
3
5
7
9
16
18
20
r-
{>o-- BUSY
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
SOLENOID DRIVER #41
SOLENOID DRIVER #51
8212
ll.i:=
ISOLENOID DRIVER #61
L-----IISOLENOID DRIVER #71
>
~
....
inter
AP·91
APPENDIX B. MONITOR LISTING
dl (
08 J
~Eg
,"I,
,P.O.P.."
IMPLE"ENTS CONTROL OF THE C ITDH "ODEL 82B
THE H"ROWARE CONFIGURATIDN IS AS SUCH:
,'PINTER
:8212 INPUT PORT ON 8us • DATA INPUT
16
;8212 OUTPUT PORT DN BUS' OUTPUT TO SOLENOID HAM"ERS
;TI !HPUT • CHARACTER POSITIONING SENSOR ON PRINTER
,TB :HPU! • iNTERRUPT FRO" 8212 INPUT PORT
;PORT IB
MOTOR ON, LOW' ON
,PORT 11
LIME FEED STROBE, LOW' ON
'PORT 16 • LEFT HARGIN SENSOR, LOW WNEN COYERED, HIGH WHEN OPEN
:PORT ,7 • RIGHT MARGIN SENSOR. LDU UHEN COVERED, HIGH UHEN OPEN
;TI • PIM 2 OF L"339, PRINT WHEEL SENSOR
:PORT 16
PIN 13 OF LM339
:PORT 17 • PIN \4 OF LH33'
17
13
:.~
s
~
10
J.I
12
13
14
15
19
20
21
OBBa
B8BI
0811~
BD B3
~
~.*
STBCHT
9804
26 TEMPI
BOO~
27
STATLIS
E9U
E9U
E9U
EgU
EDU
egU
;POINTS
:POINTS
;STATUS
: STROBE
P.B
Rl
~,;!
R3
38
3I
32
33
34
35
36
37
aBOF
aS26
38
3q LI HCH T
4B ,IUNK 1
41 "AX
42 FI P. ST
43 SEJE['T
egU
egU
EQU
EQU
AT INPUT LOCATION
AT OUTPUT LOCATION
FOR PRINTING
COUNTER
;BIT
LINE FEED SET
;BIT
PRINT
:BIT
CONTINUE
;BIT
• CR FOUND
:BIT
LF FOUND
:BIT
LF FOUND IN PRINTING
;BIT 6
PRINT DIRECTION
;9 = RIGHT TO LEFT
:\ = LEFT TO RIGHT
:BIT 7 • BUFFER LOAD DIRECTION
;B = FIRST TO "AX
:\ = MAX TO FIRST
:THE LIKE COUNTER
29
Bsa,
••••••••••••••••••••• •••••••••••
R4
R5
2S
BBB6
~.~
: SYP EM EOLIATES
22 i IlB UF
23 OUTBUF
24 SAIIPHT
2S
.•.• .. -.... •• * •••••••••
R6
~7
6FH
:"AX BUFFER LOCATION
:BOTTOM OF BUFFER
~BH
1-182
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:BEGIH THE PROGRA"
BAH
:START THE PROGRAH
55
56
57
BBBA FD
DB OF 3211
BBBD 340B
OB BF 04 BA
58
'L O(IP
PRHT,
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60
61
62
63
64
65
67
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69 LPRHT: ,IHP
: GO F I X UP TH E STATUS
6~ LPRIH l'
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[.~SE23
70
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( ~ SE 8J
7I
72
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,
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98
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92 HHC-T
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: GE T THE STATUS
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FIP.~T
SA 'JE S THE STATUS
,AHD THEH DE~ER"IHES WHHH DIRECTIOH TO PRIHT
'AHP HCI!4 a MAHIPULATE THE BUFFER
8019
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THE BUFFER F lLL S UP
A,saTUS
lPRl1T
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6.
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LIN T I I
HOV
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CALL
J"P
"[)TON
( t-I SE 1
PP.HTBK
( "SE 0
.
:SET UP OUTBUF
:SET UP IHBUF
:GET THE SAYED STATU S
;TURN OH TNE MOTOR
:PRINT F OW ARD
:GET REAOV TO PRINT BACKWARDS
;PRIHT BACKWARDS
LOA[II HG BUFFER FRDH MAX TO FIRST
Ol! TaUF ""AX
,HBUF, 'HAX
A '; !1'Jp NT
HOHlIl
C""E 3
P~llTBK
( H 5E 2
1-183
: SE T UP OUTBUF
:SET UP IN8UF
; GE T THE PRINT STATUS
,: TURN OH THE HDTOR
; PR I NT LEFT TO RIGNT
:GET READY TO PRINT BACKWARDS
,PP.INT RIGHT TO LEFT
inter
loe
OBJ
Bnl FI
8132
8134
·1136
1138
lilA
IIlC
813E
1141
1142
1144
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8146 945E
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816B 945E
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AP·91
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9J
H
SOURCE STATEIIENT
CASEI'
95
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112 FOC'
183 FOC I'
184
115
186
187
188
IB'
118 "
111
112
113
114
115
116 CASEI'
117
liB
119
121,
121
122
12l
124
125 CRFOKD.
126
127
12B
129
131
131
Il2
133 tEJECT
IIOY
CAlL
HOY
JB7
CALL
JZ
"OY
CALL
JIIP
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CAlL
CAlL
JZ
"OY
"OY
CALL
HOY
Jill'
A, .OUTBUF
FKPRHT
.OUTBUF,12IH
FOC
I NCT ST
WATCHD
JUNK L 128H
GTPRHT
CASEI
J UNU, 128H
GTPRNT
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WATCHD
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tDUTBUF,12IH
FKPRHT
JUNU,A
FOCI
IGET THE CHARACTER
IADJUST FOR PRINTING
,PUT A SPACE IN BUFFER RAN
'FOUND A CR
'UPDATE OUTBUF
I WAIT FOR" END
ICET A SPACE TO PRINT
IGO PRINT A SPACE
IlOOP
IGO PRINT THE LAST SPACE
IGO PRINT A CHARACTER
)CHECK OUT BUFFER
IWAIT FOR THE END
)GET THE CHARACTER'
,PUT A SPACE THERE
IFIX THE CHARACTER UP
) SAYE IT
,LOOP
)
:CASE I. PRI NT! NG LEFT TO RIGHT. LOADING 8UFFER FRO"
)FIRST TO UX
"OY
CAlL
"OY
"OY
JB7
CAlL
CALL
JZ
J"P
"OY
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CALL
CAlL
J2
"DY
CALL
JIIP
A.IOUTBUF
FKPRNT
JUHU.A
.OUTBUF,128H
CRFOHD
GT PRHT
INCTST
. YATCH
CASE I
tDUTBUF .128H
J UKK I •• 28H
GTPRHT·
IHCTST
YATCH
A, lOUT BUF
FXPRHT
CRFOHD
1-184
eET THE CHARACTER
ADJUST FOR PRINTING
SAYE Ace
PUT A SPACE IN THE BUFFER
FOUND A CR?
GO PRINT THE CHARACTER
CHECK THE BUFFER
IS THE LAST CHARACTER BEING PRINTED?
LOOP
PUT A SPACE IN THE BUFFER"IIEIIORY
PUT A SPACE IH TEIIP LOCAT 10K
GO PRINT THE SPACE
CHECK THE BUFF ER
LAST CHARACTER PRIHTtD?
GET THE NEXT CHARACTER
ADJUST IT
LOOP
intJ
Lot
OBJ
AP·91
SEll
SOURCE STATE"ENT
I J4
lI?l 947B
BB73 148A
BI75
8876
Bl77
Bl7B
887A
887B
8170
887E
117F
27
62
55
3488
.,
F27A
65
FD
5285
8881 '4DF
8883 53FD
8185 53F8
8187 AD
IBBB FA
IIU B271
BBBB B4BA
135
136
137 DOLF.
138
139
141
141
142
143 WATCN.
144
145
146
147 LOOPY.
14B
149
151
151
152
153
154 OYRI.
155
I"
157
158
159
JTHIS ROUTINE CALLS THE LINE FEED
;STROBE LINE FEED SOLENOID
;GO BACK TO THE PRINT ROUTINE
L1HEFD
PRHT
:THIS ROUTINE CO"PLETES A LINE WHEN THE PRINT
:NEAD IS "OYING LEFT TO RIGHT
CLR
"OY
STRT
CALL
IN
J87
STOP
noy
JB2
CALL
ANL
ANL
nOY
nOy
JB5
J"P
: ZERO Aci;
:ZERO TI"ER
:START THE TInER
:GO READ TNE LAST CHARACTER
:EXAnIH PORT ONE
:CNECK RICNT NAND SENSOR
) SlOP THE TI"ER
;GET THE STATUS
:JUHP IF CONTINUE IS SET
; TURN "DTOR OFF
:RESET BIT ONE
:RESE~ CONTINUE BIT
; RESTORE STATUS
ICET THE SAYE_ STATUS
:00 A LINE FEED IF BIT IS SET
IGO BACk TO PRINT ROUTIHE
A
T, A
T
LDBUF
A, PI
LDOPW
TCNT
A,STATUS
OYRI
"OTOF
A,IBFDH
A,'BFBN
STATUS,A
A,SAYPNT
DOLF
PRNT
I6B
BaeD FI
U8E 34'1
.891 8121
8892 F2'E
8894 9472
8896 t6AE
889B 8F28
189A 9463
IUC 8480
189E 8F 21
llAl '463
81A2 ,. 72
IIA4 .t6AE
llA6 F I
BlA?
BlA'
IUA
BlAC
3491
AF
BI28
BUB
161
162
163
164
;CASE 2, PRIHTING RIGHT TO LEFT, LOADING BUFFER FRO"
)"AK TO FIRST
165 CASE2.
"OY
CALL
166
167
168
169
178
171
172
173
174 FDCA'
1?5 FHRI'
176
177
178
179
188
181
182
183 $EJECT
noy
JB7
CALL
JZ
"OY
CALL
JftP
noy
CALL
CALL
JZ
noy
CALL
noy
"OY
J"P
A.eOUTBUF
FXPRNT
tOUTBUF, '28H
HCR
T>ECTST
WATCHD
JUHKI,128H
GTPRHT
CASE2
.1 UNK J, .2BH
GTPRNT
DE CrsT
WATCHD
~,UUTBUF
FXPRNT
JUNKI, ~
POUTBUF,128H
FDCRI
1-185
GET THE CHARACTER
ADJUST FOR PRINTING
PUT ~ SPACE IN BUFFER RA"
FIND A CR YET
CHECK THE BUFFER
IF ZERO YAIT FOR SENSOR FLAG
PUT SP~CE IN TE"P LOCATION
GD PRIHT SP~CE
LOOP
GET A SPACE
GD PRIHT THE CHARACTER
CHECK THE BUFFER
LEAH IF DDHE
GET A CHARACTER
ADJUST THE CHARACTER FOR PRINTING
SAYE IT
PUT A SPACE WHERE THE CHARACTER WAS
LOOP
inter
LDC
IIAE
1188
IIBI
1183
1184
D8J
.,3411
IUA
118C
IIBD
Bl8E
BlCI
02AE
FD
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53FB
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FA
8271
IUA
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IIC5
.IC6
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8101
1802
BI04
1106
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810A
BlOC
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FI
3491
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9472
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BF28
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9472
C675
FI
3491
8402
I."
IIB8
Ap·91
SEa
SOURCE SUTUENT
184
: THI S ROUTINE WAITS FOR THE SEHSOR,FLAGS TO BE COYEREO
185
:IIHEN PRINTIHG RIGHT TO LEFT
186
187
188 WATCHO: CALL
LDBUF
:GD READ THE LAST CHARACTER
A, PI
IN
JCET SENSOR IHFOR"ATION
18'
191
JU
IIAltHD
:'LOOP IF SEHSOR IS NOT COYERED
A,STATUS
191
HOY
JCET THE STATUS
OYR
:SEE IF CONTI HUE IS SET
192
J82
193
CALL
:TURN THE ROTOR OFF
"OTOF
A,IIFOH
:RESET BIT I
194
ANL
A,IIFBH
:RESET BIT 3
195 OYR :
ANL
STATUS,A
196
HOY
:RESTORE STATUS
A,SAYPHT
:CET
THE SAYED STATUS
197
"DY
DOLF
J DO A LI HE FEED
198
JB5
JRP
PRHT
J HIT
199
288
:CIISE l, PRIHTlNG LEFT TO RIGHT, LOADING BUFFER FRO"
211
282
:"IIK TO FIRST
283
I
214 CASEl : "OY
A,'OUT8UF
GET A CHARACTER
FKPRHT
FIX FOR PRINTIHG
285
CALL
S'AYE CHARACTER
216
JUHK),A
"OY
tOUTBUF,12BH
287
HOY
PUT A SPACE IN THE 8UFFER
JB7
LEAVE IF A CR IS FOUND
288
CR'FNO
219
GTPRHT
GO PRINT THE CHARACTER
CALL
21B
CALL
DECTST
CHECK THE BUFFER
211
WATCH
LEAVE IF DONE
JZ
LOOP,
212
CASEl
J"P
POUTBUF,128H
213 CRF NO: HOY
PUT II SPACE IN THE BUFFER RA"
214
HOY
JUHK1,'2BH
GET A SPACE
215
CALL
GTPRHT
PRINT A SPACE
216
CALL
DE CT S T
CHECK THE BUFFER
217
JZ
WATCH
LEAYE IF DONE
,2.18
A,tOUTBUF
GET NEXT CHARACTER
"OY
219
CALL
FXPRNT
ADJUST IT
228,
CRFNO
LOOP
J"P
221 SEJECT
1-186
AP·91
LOC
OBJ
BIBB
BIBB
BIBI
BIB3
8115
IIB7
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BIBD
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8118
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8981
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FE
438B
AE
23FF
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19
721A
'JZU
2413
2488
SE Q
222
223
224 L08UF:
225
ORG
I BBH
IN
A. PI
READ PORT I
JB5
IN"ODE
8IT 5 = H = LINE "ODE
226
J81
ARNP
JU"P AROUHD IF "OTOR IS ON
227
PI. 181 H
ORL
TURN TNE "OTOR OFF
J84
NOFF
228 ARHD'
NO F OR" FEED
KOY
229
A.L1NCNT
GET TNE LINE COUNTER
231
ORL
A.188N
SET KS8
231
KOY
L1HCHT.-A
RESTORE THE LIHE COUHTER
A,IBFFN
KOY
232
SET ACC
J83
233 HOFF:
NOlF
JUKP IF NO lINE FEED
234
CALL
llHEFD
GO DO A IF DR FF
235 8UTlOP: IN
READ THE PORT
A. PI
WAIT FOR SWITCH TO 8E RELEASED
236
JB3
NOLF
237
WAIT FOR SWITCH TO 8E RELEASED
JB4
NOlF
8UTLOP
LOOP
238
J"P
lOOP
2H HOlF'
LDBUF
J"P
248
241
,FIRST SEE IF A CHARACTER IS PRESENT IN THE BUFFER
242
IIIC 261F
III E 83
BlI F FD
Bl2B 5249
1122 9249
BI24 724A
1126 9406
B128 3461
BI2A A8
8128 FD
112C F239
812E 18
812F 2378
8131 08
8132 %49
BI J4 F8
8135 17
1136A8_
BI37 2449
BI39 F8
BI3A B7
BI38 A8
BI3t 231F
BI3E 08
BI3F %49
BI41 18
1142 2449
BI44 FO
BI45 1249
BIH 9258
BI49 83
243 lNHOPE' JNTlI
:IF CHARACTER PRESENT. READ IT
CHAR
244
; IF NOT. EXIT ROUTINE
RET
245
2H
,IF THERE IS
CHARACTER. READ IT
247
248 CHAR:
A.STATUS
:GET THE STATUS
"OY
: IF COHTINUE IS SET. DON'T LOAD
249
ARHDJP
JB2
258
:IF IF IS SET, DON'T LOAD
JB4
ARHDJP
JBl
LFCRCK
'WAS CR SET. SEE IF NEXT CHAR IS LF
251
252
CAll
GTeAR
'CD ~EAD A CHARACTER
253 GOOD:
CALL
FXCHAR
:"AKE SURE IT IS OK
254
KOY
;SAYE CHARACTER IN BUFFER "EHORY
PIHBUF.A
255
HOY
A, STATUS
:GET THE STATUS
256
J87
SUBI
:IF BIT 7 IS SET DECRE"ENT BUFFER
257
INC
IH8UF
:UPDATE IH8UF
HOY
258
A,I"A~.I
:CET TOP
259
XRL
A"IllBUF
:ARE WE AT THE TOP?
268
JNZ
ARHDJP
: IF HOT ,GET THE STATUS
Koy
261
A.INBUF
:GET IHBUF
262
DEC
A
: CHANGE 8V ONE
IH8UF,A
263
KOY
:PUT IT 8AC~
264
ARHOJP
:GET THE STATUS
J"P
265 SUBI:
"OY
A.IHBUF
'GET IN8UF
;CHAHGE
BY OHE
DEC
A
2"
;PUT INBUF BACK
267
KOY
IHBUF.A
268
:GET THE BOTTO" OF THE 8UFFER
HOY
A.IFIRST-I
A,INBUF
;TEST THE BUFFER
269
XRL
,INZ
'IF HOT ZERO READ THE STATUS
271
ARHDJP
271
INC
I HBUF
:"DVE INBUF BACK
272
ARNOJP
:CO GET STATUS
J"P
273 CETSTA: Koy
A,STATUS
'CET THE STATUS
274
ARHDJP
JBB
:IF BIT B SET. BYPASS
275
JB4
~TBlTl
'IF LF IS FOUHD. SET THE STATUS
276 ARNDJP' RET
: EXIT
277
278
279
BI4A 9406
814C 2J8A
814E 2428
;THIS ROUTINE "FORCES· A LF AFTER A CR
281 LF CRCK: CALL
281
KDY
282
283
284
J"P
FP
3259
4382
8348
AD
83
5268
4384
1348
AD
1168 83
286 STBITI' "OY
287
288
J8I
ORL
ADD
Koy
291
RET
292 STPRHT: JB2
293
ORL
294
ADD
HOY
8VEBVE: RET
289
298
2"
2"
297
;REAO A CHARACTER
;CET A lINE FEED
:JUMP BACK
;THIS ROUTIHE SETS THE STATUS BITS
285
815B
BI51
8153
81SS
BI57
1158
8159
8158
8,150
815F
GreAR
A,I8AH
GOOD
A.STATUS
STPRNT
A.182H
A.I48H
STATUS,A
BYE8YE
A. tB4H
A. t48H
STATUS. A
1-187
LOAD 'tHE STATUS
IF STILL PRINTIHG, LEAYE
SET PRINT'8IT
UPDATE POSITION COUNTER
PUT STATUS BACK
EX IT ROUT! NE
CHECK CONTINUE 81T
SET COHTINUE BIT
UPDATE PRINT DIRECTION
~UT THE STATUS 8ACK
EX IT
inter
LOC
OB,I
AP·91
SOUHE
SE"
~,lH~E"'EHT
;THIS ROUTIHE 'CONYERTS' LOWER CASE LET TERS TO
;UPPER CASE
2'8
299
HI
8161
8162
8164
8165
BI67
81 "
8UA
BI69
8160
BHE
Bl7B
BI71
8173
BI74
8175
BI77
817'
BI7A
BI7C
BHD
BI7F
BI88
BI82
8184
8185
'7
537F
AF
B3AB
E678
FF
37
8328
37
2474
J7
B3AB
37
AF
D3 BD
,67F
FD
HB8
AD
248F
FF
038A
C689
FF
D3ac
8187 '68F
8189 FD
BIeA 4318
81SC AD
8180 3458
818F FF
LOC 08,1
8198 83
81~1
8192
8134
BI96
BU?
8199
BI9B
819C
BI9E
BlAB
81AI
BIA3
BIA5
BIA?
BlAB
BIAA
BlAB
BIAe
BIAE
BIAF
81Bl
8182
BIS3
BIB~
UI B6
BIB7
81B9
BIBA
BIBC
BIBD
BIBE
BICB
H
03ac
C682
FF
3BI
3B2
383
3B4
3B5
386
3B7
388
3B'
31B
311
312
313
314
315
316
317
318
319
328
321
322
323
324
325
326
321
328
32'
338
331
SEg
FKCHAR': CLR
AIIL
A.17FH
HDY
JUH~J., A
ADO
A,IBABH
JHC
F I HE
A, ,I UH~ I
"DY
ePL
ADD
A,128H
CP L
A
FIXDUH
J"P
FIHE:
CPL
A
ADO
A,taASH
CP L
A
FIXDUH: HOY
JUHKI,.A
XRL
A,teOH
JHZ
LFTEST
A.STATUS
"DY
OH
A,IBSH
HOY
STATUS, A
F I XF I H
J"P
LFTEST: HOY
A,JlIHY.1
XR L
A, IBAH
J2
FIXUP
HOY
A.JUHKI
XRL
A,18CH
JII2
F I XF I H
F I XUP:
HOY
A,. STATUS
ORL
A,IIBH
HOY
STATUS,A
CALL
STBIlI
F I XF I H: HOY
A. ,IUH~ 1
SOURCE STATEMEHT
"
RET
3H FXPRHT:
HOY
XRL
J2
HO',
,IUHKJ, A
A, UCH
FFFIX
A. taOH
CRFIX
343
XU
J2
HOY
FF
344
345
346
347
348
HOY
AIIL
,IH2
358
351
HOY
352
RET
353 CRFIX' ORt
354
RET
355 l F F IK'
HOY
356
ORt
357
HOY
359
HOY
RE T
35'
HB FFF IX:
HOY
361
ORL
362
HOY
363
HOY
364
ORL
365
PiOY
,HOY
366
RET
367
368 lSCHAR' KOY
AHL
369
37B
RET
33
FF
533F
93
34~
; SAY( A
,: IS CHAR~CTER A CR
; IF IT IS HOT TEST LF
; CE T THE STATUS
J SE T BIT 3
:RESTORE THE STATUS
,: LEAYE
:CET CHARACTER BACK
; IS IT A L F
; TF ITS HOT, WE ARE DOHE
:CET THE CHARACTER BAC~
; IS IT A FOR" FEED
; IF HOT FOR" FEED, JUMP
; CE T THE STATUS
; SE T BIT 4
,:RETURH TH E STAT US
; SE T THE STATUS
;CET THE CHARACTER
.: THI S ROUTIHE RECOGNIZES A LF, FF. AN[' CR
;DURING THE PR I HT OPERATIOH
.: I T ALSO FORCES A SPACE IF A CHARACTER FOUHD
,: I H THE SUFFER IS HOT I H THE LOOKUP TABLE
03BD
C6AB
FF
03BA
C6AB
53EB
%BD
232B
83
4398
83
FO
4328
AO
2328
83
FO
4328
AO
FE
4398
AE
2328
:JUHP TO TEST CR LF
!HOW SUBTRACT ABH FRO" AC C
:EKIT FIx('HAR
332
333
334
335
336
337
338
34B
341
342
CLEAR THE CARRV
SYRI P "S8
SAYE ACC
SEE IF HUI/BER IS 6BH
: IF CARRV IS~'T SEL ,IU"P
; CE T Ace BACK
; SUBTRACT 2BH FROI/ THE ACe
XP.L
J2
ACC
:FDRM FEED
,: CO SET FOR" FEED
:RESTORE CHARACTER
:SEE IF IT IS A CR
:LEAYE IF IT IS
;GET ACC BACK
:SEE IF IT IS A IF
'LEAH IF IT IS
:CET CHARACTER BACK
.: SE E IF IT IS A CHARACTER
;IF IT IS JUHP
:PUT A SPACE I H ACC
; SA liE
A ••.1 UHK 1
A,JUNK!
A,IBAH
LFFIX
A, ,I UHK 1
A,IBEBH
I SCHAR
A.12BI!
;HIT
>.BBH
A.STATUS
A,laH
STATUS, A
A,12BH
A.STATLIS
A.12UH
STATUS, A
A,LlHCHT
A,18BH
L1HCHl,. A
A,12BH
A J LINk 1
A,I3FH
; SE T 81T 7
: EX I T
:CET THE STATUS
:SET LF BI T I II STATUS
:PlIT THE STATUS BACK
: CE T A SPACE
; EXI T
:CET THE STATUS
,: SE T L1HE F fED BIT
:PlIT THE STATUS BACK
; GE T THE LI HE COUHT
: SE T BIT 7
,: PU T L1HE COUNT BAC~
:CET A SPA CE
:EXIT
:GET CHARACTER BACK
:STRIP THE TWO "SB
: HIT
1-188
intJ
LOt
08,1
Ap·91
~H
371
H2
!.OURCE STHTE"EHT
:THIS ROLITlHE PRIHTS THE
373
AC
E7
E7
BICI
BIC2
BIC3
BIC4
6C
BICS
BIC.
81 CB
BICA
2C
82CA
44AB
6U8
BICC
BICD
BICE
BlOB
BID2
BID4
8106
DID7
AF
FD
0204
5608
2406
4604
BI08
BIDA
BIDB
BlOC
81 DE
81 EB
BIEI
81 E2
81 E3
23F3
FF
9B
62
55
I6EB
24 DC
27
9B
65
83
CH~p.AeTER
1 H THE ACe
TEftPI.A
; SA'H CHARACTER
PRHTIT: HOY
A
:"ULTlPLY BY TWO
RL
37S
:"ULTIPLY BY FOUR
RL
A
376
A,'TEHPI
:ADO OHCE TO HULTIPLY BY 5
ADD
377
378
;HOU SEE WHAT PAR T OF THE LO[o':UP TABLE TO USE
379
388
:PUT CHARAC'TER I H A, TAR~ET IH TE"P I
XCH
381
A.TE"PI
,185
SHORT
: ,IU"P TO HI CH A[IDRESS IF BIT 5 SET
382
:CO TO FIRST PART OF LOOKUP TABLE
PACEI
3B3
J"P
;GO TO SHOHD PACE OF LOOr.UP TABLE
PAGE2
384 SHORT: J"P
3B5
:THIS ROUTIHE TRIC~ERS THE SOLEHOIDS FOR 6BB "ICROSECOHDS
3B6
; AF TEP. WAITJH~ FOR THE HIGGER SI~HAL FRO" THE PRINTER
387
:
3BS
3B9 FIRE:
HOY
JUHKI,A
: SAYE THE ACC
39B
HOY
A,STATUS
:GET THE STATUS
391
JB6
HTI
: SEE IF FORWARD OR BACKWARDS
392 FIREX:
JTl
; WA IT FOR T1
F I REX
393
FIREY
: LEAVE
J"P
394 NT 1 :
NTI
JHTI
'lOOP
395 FIREY:
A.JUNKI
:GET ACC BACK
HOY
396
PRB,A
:TRIGGER THE SOLEHOID
HOYX
397
398
:HOW ~ILL .BD HICROSECONOS
399
A, IBF3H
:LOAD DELAY HUnBER
4BB
HOY
T.A
: PU T IT IH TI"ER
4BI
HDY
T
; START THE TIHER
482
STRT
;LOOP OH TlftER FLAG
JTF
KrDUN
4B3 TSJTF:
TSJTF
4B~
J"P
;ZERO ACC
4B5 ~TDUH:
CLR
A
UB., A
;TURN OFF SOLEHOIDS
HDYK
486
TCHT
;STOP THE TI"ER
4B7
STOP
.:
EX I T FIRE ROUTIHE
48S
RET
4B9 tE J ECT
374
.
1-189
inter
LOC
OBJ
AP·91
SEQ
418
411
412
413
8288
8211
8281
8212
·8213
8284
n
8215
8216
8287
8288
828'
?C
12
II
12
7C
828A
8UB
828C
8280
821E
7F
49
H
H
36
828F
8218
8211
8212
8213
3E
41
41
41
22
8214
8215
8216
1217
12J8
41
41
41
3E
3E
41
SO
59
7F
.,
.,
121' 7F
821A
821B H
821C
8210 41
414
415
416
417
418
419
428
421 TABLE I'
422
423
424
425
426
427
428
429
438
431
432
433
434
435
436
437
438
439
448
441
442
443
4"
445
446
447
448
449
451
451
452
453
454
455
456 IEJECT
SOURCE STATEKENT
; ••••
~.~
•••••••
~.~
•• •••• ••••
~
~
~.*
•• •••••• * •• ••••••
~
~
*.*~
•••••• *.
-
!THIS IS THE LOOkUP TABLE. THE "sa IS HOT USED; THE "SB
I
liS THE DOT TNAT IS THE TOP OF AHY GIVEN CHARACTER AHD THE
!LSB IS THE ['OT THAT IS THE BOTTOK OF ANY GIVEN CHARACTER
; •••••••• **.* •• ~.*.~~
.
ORC
)
...... .. ......
~
288H
DB
DB
DB
DB
DB
3EH
41H
SOH
59H
4EH
DB
DB
DB
DB
08
7tH
12H
II H
12H
DB
DB
DB
DB
DB
7FH
49H
49H
36H
DB
DB
DB
DB
08
HH
41H
41H
41H
22H
DB
DB
08
DB
DB
7FH
41H
41H
41H
lEN
DB
DB
DB
DB
DB
7FH
49H
49H
49H
41H
~
.... -
......
•••
... "
.....
_
nH·
............
4~H
•• ••
......
•
.......
......
........
1-190
*•• * •••• ~.*
....
*.* ••••• ~ •••
inter
LOC
OBJ
02lE
021F
0228
8221
8222
7F
89
B9
89
81
JE
41
8223
8224
0225
8226
8227
41
8228
8229
122A
822B
822C
7F
88
OB
8B
7F
822D
822E
B22F
823B
8231
88
41
7F
41
HI
8232
8233
8234
8235
8236
21
48
48
41
3F
8237
8238
82l!
82JA
123B
7F
18
14
22
41
823&
823D
823E
823F
8248
7F
41
48
48
48
1241
8242
8243
B244
8245
7F
82
Be
82
7F
8246
8247
824B
824'
024A
7F
84
88
IB
7F
51
71
AP·91
SE g
457
458
45'
468
461
462
463
464
465
466
467
468
4"
478
471
472
473
4H
475
476
477
478
47'
4B8
481
482
4B3
484
4B5
4B6
487
4B8
4 B'
498
4'1
4 ~2
H3
494
4'5
4%
497
498
499
58B
501
502
58l
584
585
506
587
508
50'
SIB
SOURCE
DB
DB
DB
DB
DB
ST~TE"EHT
7FH
O~H
8~H
8~H
BIH
DB
DB
DB
DB
DB
JEH
4IH
41 H
51H
71H
D8
DB
DB
DB
DB
7FH
8SH
BBH
BBH
DB
DB
DB
DB
DB
B8H
41 H
7FH
41 H
BOH
DB
DB
D8
DB
DB
28H
48H
4BH
4BH
3FH
DB
DB
DB
DB
DB
7FH
88H
I4H
22H
41H
D8
DB
08
DB
DB
7FH
4BH
4BH
48H
48H
DB
DB
DB
DB
DB
82H
BCH
82H
7FH
DB
DB
DB
DB
DB
7FH
84H
88H
18H
7FH
... "...
.......
"
7FH
. . . . . . . III
.......
... "..
.........
.•
.......
...... ,.
.... "..
7FH
........
...... :t • •
511 HJECT
1-191
inter
lOC
OBJ
124B
824C
8240
B24E
B24F
JE
41
41
41
8258
12'1
1252
8253
8254
7F
89
8'
89
1255
8256
8257
8258
82"
3E
41
51
21
5E
3E
B6
825A 7F
825B 89
USC
U
8250 29
B25E 46
825F 2i
U68
82U
8262 49
826l 32
4'4'
8264
8265
82"
8267
826B
81
81
7F
81
81
82" 3F
826A 48
826B 48
BUt 48
8260 3F
8HE
826F
8278
8271
8272
IF
28
48
28
8273
8274
8275
8276
8277
7F
28
18
28
7F
IF
AP·91
SEQ
512
51J
514
515
516
517
518
519
528
521
522
523
524
525
526
527
528
529
518
531
532
53.
534
535
53.
537
538
539
548
541
542
543
544
545
546
547
548
549
558
551
552
55.
554'
555
556
557
558
55'
56D
561
562
563
564
565
566 fEJECT
SOURCE STATE"ENT
•• :fI".
DB
08
DB
DB
DB
lEH
41H
41H
41H
lEH
DB
DB
DB
DB
08
7FM
89M
89M
89M
86H
08
DB
08
DB
lEH
41M
SIH
.21H
DB
5EH
" * ....
DB
DB
DB
DB
DB
7FH
B9H
19H
••••• ,,*
08
DB
DB
08
08
......
........
•
••
..
29H
••
••
46"
26H
49"
49"
49H
32H
08
DB
DB
DB
08
81H
81H
08
DB
DB
DB
DB
3FH
48H
48H
48H
lFH
08
08
DB
08
DB
IFH
28H
48H
28H
IFH
DB
08
DB
DB
08
~FH
••
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7FH
81H
81H
........
......
....
..
:
"
. " "."fI:
.........
28H
18H
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2BH
7FH
1-192
inter
lOC
08J
827B
827'
827A
8278
B27C
as
63
14
B27D
B27E
B27F
828B
8281
83
84
7B
84
B3
8282
8283
8284
B285
8286
61
51
4'
45
43
14
63
8287 7F
8288 7F
un
H
828A 41
828B 41
82SC
8280
828E
828F
8298
82
84
88
18
28
8291
8292
8293
8294
829'-
41
41
41
7F
7F
B296
8297
8298
B2"
829A
18
DB
B29B
829C
8290
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.29F
4.
4.
4B
B4
DB
18
4B
4.
AP·91
SEg
567
568
569
578
571
572
573
574
575
576
577
518
579
58B
581
582
5B3
584
585
586
5B7
588
589
"8
"I
B2
593
"4
595
5"
"7
598
599
68D
681
682
6BJ
6B4
6B5
6B6
6B7
688
6B9
618
611
612
613
614
615 .EJECT
SOURCE SHTE"EHT
08
08
DB
DB
08
63H
I4H
88H
14H
63H
DB
DB
DB
DB
DB
B3H
B4H
78H
B4H
B3H'
DB
DB
DB
08
DB
61H
51H
49H
45H
43H
08
08
DB
DB
DB
7FH
••
••
..
••
....
••
..
••
..
••
.........
7FH
41H
41H
41H
DB
DB
DB
DB
DB
B4H
B8H
18H
28H
DB
08
DB
DB
DB
41H
41H
41H
7FH
7FH
DB
DB
08
DB
DB
IBH
B8H
84H
B8H
IBH
DB
DB
08
DB
DB
48H
4BH
4BH
UH
4BH
B2H
.......
.........
.
1-193
inter
loe
12A8
12A2
12A3
IU4
12A6
BU7
IUB
IUR
12AB
B2AC
B2AD
UAF
,8281
OBJ
8811
FA
37
0283
Fe
A3
Hce
IC
18
FB
0385
"A6
84AE
1283 FC
1284
1286
8287
12BB
B289
1288
Inc
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82BE
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I2C2
I2C4
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AC
FC
A3
HCC
FC
87
AC
IB
FB
OU5
"B7
84AE
AP·91
SEQ
616
617
618
619
628
621
622
623
624
625
6a
627
628
629
638
631
632
6ll
634
635
63'
637
638
639
648
641
642
SOURCE STATE"EHT
PAGEl:
lHO:
"OY
"OY
CPl
J86
"OY
"OYP
CALL
INC
INC
HOY
XRL
JHZ
Jilp
BAKWRD: "OY
ADD
"OY
LKLOI: "OY
"OYP
CALL
"DY
DEC
KOY
IHC
HOY
XRL
JNZ
643
J"P
644 fEJECT
STBCHT. nIH
A.·SAYPHT
A
BAKWRD
A. TE"PI
A U
FIRE
TE"P I
STaCHT'
A,STBCHT
A·185H
LHO
SETTI"
A. TE"PI
A.184H
TEKP LA
A.,TE"PI
A. IA
FIRE
A·TEKPI
A
TE"P J.. A
STBCHT
A,STBCHT
A,185H
LKLOI
SETTI"
1-194
ZERO STROBE COUNTER
GET DIRECTIOH
FLIP BITS
IF BACKWARD JUHP OUT
GET THE TARGET
GE T THE DATA
STROBE THE SOLENOIDS
IHCRE"EHT THE POI HTER
IHCRE"ENT THE STROBE COUNTER
GET THE STROBE COUNTER
IS IT FIH
REPEAT IF NOT FIYE
GO BACK
GE T THE TARGET
COKPEHSATE FOR GOING BACKWARDS
SAYE IT
GET THE TARGET
GET THE DATA
STROBE THE SOLENOIDS
GE T TE"PI
DECREASE BY ONE
PUT IT BACK
IHCREftEHT TNE STROBE CDUNTER
GE T THE STROBE COUNTER
IS IT FIH
REPEAT IF NOT FIYE
GO BACK, CHARACTER IS DONE
inter
lOC
OBJ
a385
1386
8Ja7
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MCS® .. 51 Application Notes &
Article Reprints
2
inter
APPLICATION
NOTE
AP-69
May 1980
~
AFN-01S02A-01
Intel Corporation 1980
2-1
intJ
AP-69
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AD
Figure la. 8051 Microcomputer Pinout Diagram
~}~M'.
Figure lb. 8051 Microcomputer Logic Symbol
1. INTRODUCTION
some microprocessor (preferably Intel's, of course) or
have a background in computer programming and digital
logic.
In 1976 Intel introduced the MCS-48'· family. consisting
of the 8048. 8748. and 8035 microcomputers. These parts
marked the first time a complete microcomputer system,
including an eight·bit CPU. 1024 8·bit words of ROM
or EPROM program memory. 64 words .of data memory.
I 0 ports and an eight-bit timertcounter could be integrated onto a single silicon chip. Depending only on the
program memory contents. one chip could control a
limitless variety of products. ranging from appliances or
automobile engines to text or data processing equipment.
Follow-on products stretched the M CS-48'· architecture
in several directions: the 8049 ami 8039 doubled the
amount of on-chip memory and ran 83'ff faster; the 8021
reduced costs by executing a subset of the 8048 instructions with a somewhat slower clock; and the 8022 put a
unique two-channel 8-bit analog-to-digital converter on
the same NMOS chip as the computer, letting the chip
interface directly with analog transducers.
Family Overview
Pinout diagrams for the 8051. 8751. and 8031 are shown
in Figure I. The devices include the following features:
Now three !lew high-performance singlecchip microcomputers .. the Intel® 8051, 8751. and 8031-extend the
advantages of Integrated Electronics to whole new product areas. Thanks to Intel's new HMOS technology, the
MCS-5I'· family provides four tli 'es the program'
memo'ry and twice the data memory as the 8048 on a
single chip. New I/O and peripheral capabilities both '
increase the' range of applicability and reduce total system
cost. Depending on the use, processing throughput
increases by two and one-half to ten times.
This Application Note is intended to introduce the reader
to the MCS-51'· architecture and features. While it does
not assume intimacy with the MCS-48'· product line on
the part of the reader. he/she should be familiar with
• Single-supply 5 volt operation using HMOS technology.
• 4096 bytes program memory on-chip (not on 8031).
• 128 bytes data memory on-chip.
• Four register banks.
• 128 User-defined software flags.
• 64 Kilobytes each program and external RAM
addressability.
• One microsecond instruction cycle with 12 MHz
crystal.
• 32 bidirectional I/O lines organized as four 8-bit
ports (16 lines on 8031).
• Multiple mode, high-speed programmable Serial
Port.
• Two multiple mode. 16-bit Timer/Counters.
• Two-level prioritized interrupt structure.
• Full depth stack for subroutine return linkage and
data storage.
• Augmented MCS-48'· instruction set.
• Direct Byte and Bit addressability.
• Binary or Decimal arithmetic.
• Signed-overflow detection and parity computation.
• Hardware Multiple and Divide in 4usec.
• Integrated Boolean Processor for control applications.
• Upwardly comp~tible with existing 8048 software.
AFN-01502A-04
2-2
intJ
AP-69
All three devices come in a standard 40-pin Dual InLine Package, with the same pin-out, the same timing,
and the same electrical characteristics. The primary
difference between the three is the on-chip program
memory --different types are offered to satisfy differing
user requirements.
ware application examples illustrate many of the concepts.
Several isolated tasks (rather than one complete system
design example) are presented in the hope that some of
them will apply to the reader's experiences or needs.
A document this short cannot detail all of a computer
system's capabilities. By no means will all the 8051 instructions be demonstrated; the intent is to stress new or
unique MCS-51'· operations and instructions generally
used in conjunction with each other. For additional hardware information refer to the Intel MCS-S\'· Family
User's Manual. publication number 121517. The assembly
language and use of ASM51. the MCS-51'· assembler,
are further described in the MCS-S\'· Macro Assembler
User's Guide, publication number 9800937.
The 8751 provides 4K bytes of ultraviolet-Erasable,
Programmable Read Only Memory (EPROM) for
program development, prototyping, and limited production runs. (By convention, I K means 2'" = 1024.
I k·-with a lower case "k"-equals IOJ = 1000.) This part
may be individually programmed for a specific application using Intel's Universal PROM Programmer (UPP).
If software bugs are detected or design specifications
change the same part may be "erased" in a matter of
minutes by exposure to ultraviolet light and reprogrammed with the modified code. This cycle may be
repeated indefinitely during the design and development
phase.
The next section reviews some of the basic concepts
of microcompu\er design and use. Readers familiar
with the 8048 may wish to skim through this section
or skip directly to the next. "ARCHITECTURE AND
ORGANIZATION."
The final version of the software must be programmed
into a large number of production parts. The 8051 has
4K bytes of ROM which are mask-programmed with the
customer's order when the chip is built. This part is considerably less expensive, but cannot be erased or altered
after fabrication.
MIcrocomputer Background Concepts.
Most digital cdmputers use the binary (base 2) number
system internally. All variables. constants, alphanumeric
characters, program statements, etc .• are represented by
groups of binary digits ("bits"), each of which has the
value 0 or I. Computers are classified by how many bits
they can move or process at a time.
The 8031 does not have any program memory on-chip,
but may be used with up to 64K bytes of external standard
or multiplexed ROMs, PROMs, or EPROMs. The '8031
fits well in applications requiring significantly larger or
smaller amounts of memory than the 4K bytes provided
by its two siblings.
The MCS-51'" microcomputers contain an eight-bit
central processing unit (CPU). Most operations process
variables eight bits wide. All internal RAM and ROM.
and virtually all other registers are also eight bits wide.
An eight-bit ("byte") v'ariable (shown in Figure 2) may
assume one of 2" = 256 distinct values. which usually
represent integers between 0 and 255. Other types of
numbers. instructions. and so forth are represented by
one or more bytes using certain conventions.
(The 8051 and 8751 automatically access external program memory for all addresses greater than the 4096 bytes
on-chip. The External Access input is an override for
all internal program memory-the 8051 and 8751 will
each emulate an 8031 when pin 31 is low.)
Throughout this Note, "8051" is used as a generic term.
Unless specifically stated otherwise, the point applies
equally to all three components. Table I summari7.es the
quantitative differences between the members of the
MCS-48'· and MCS-51'· families.
For example, to represent positive and negative values.
the most significant bit (D7) indicates the sign of the other
seven bits-O if positive. I if negative-allowing integer
variables. between -128 and +127. For integers with
extremely large magnitudes. several bytes are manipulated together as "multiple precision" signed or unsigned
integers-16. 24. or more bits wide.
The remainder of this Note discusses the various MCS-51'·
features and how they can be used. Software and/or hard-
Table 1. Features of Intel's Single-Chip Microcomputers
EPROM
Program
Memory
ROM
Program
Memory
External
Program
Memory
Program
Memory
(Int/Max)
Data
Memory
(Bytes)
Instr.
Cycle
Time
Inputl
Output
Pins
Interrupt
Sources
Reg.
Banks
--
8021
8022
8048
8049
8051
--
IK!IK
2K'2K
IK:4K
2K,4K
4K,64K
64
64
64
8.41,Sec
8. 4 "Sec
2.5"Sec
1.36,ISec
1.0"Sec
21
28
27
27
32
0
2
2
2
5
I
I
2
2
4
8748
8751
8035
8039
8031
128
128
AFN-01S02A-05
2-3
intJ
Ap·69
The letters "MCS" have traditionally indicated
a system or family of compatible Intel@> microcomputer components, including CPUs, memories, clock generators, I/O expanders, and so
forth. The numerical suffix indicates the microprocessor or· microcomputer which serves as
the cornerstone of the family. Microcomputers
in the MCS-48'· family currently include the
8048-series (8035,8048, & 8748). the 8049-series
(8039 & 8049), and the 8021 and 8022; the
family also includes the 8243, an I/O expander
compatible with each of the microcomputers.
Each computer's CPU is derived from the 8048,
with essentially the same architecture, addressing modes, and instruction set, and a single
assembler (ASM48) serves each.
a single character. and a word or sequence of letters may
be represented by a series (or "string") of bytes. Since the
ASCII code only uses 128 characters. the most significant
bit of the byte is not needed to distinguish between characters. Often D7 is set to 0 for all characters. In some
coding schemes, D7 is used to indicate the "parity" of the
other seven bits--set or cleared as necessary to ensure
that the total number of "I" bits in the eight-bit code is
even ("even parity") or odd ("odd parity"). The KOSI
includes hardware to compute parity when it is needed.
, A computer program consists of an ordered sequence of
specific, simple steps io be executed by the CPU one-ata-time. The method or sequence of steps used collectively
to solve the user's application is called an ··,algorithm."
The program is stored inside the computer as a sequence
of binary numbers. where each number correspond~ to
one of the basic oper,ations ("opcodes") which the CPU
is capable of executing. In the 80S I. each program
memory location is one byte. A complete instr.uction
consists of a sequence of one or more bytes. where the
first defines the operation to be executed and additional
bytes (if needed) hold additional information. such as
data values or variable addresses. No instruction is longer
than three bytes.
The first members of the MCS-51'· family are
the 8051, 8751, and 8031. The architecture of
the 8051-series, while derived from the 8048,
is not strictly compatible; there are more
addressing modes, more instructions, larger
address spaces, and a few other hardware differences. In this Application Note the letters
"MCS-51" are used when referring to architectural features of the 8051-series-features
which would be included on possible future
microcomputers based on the 8051 CPU. Such
products could have different ·amounts of
memory (as in the 8048/8049) or different
peripheral functions (as in the 8021 and 8022)
while leaving the CPU and instruction set
intact. ASM51 is the assembler used 9Y all
microcomputers in the 8051 family.
The way in which binary opcodes and modifier bytes are
assigned to the CPU's operations is called the computer's
"machine language." Writing a program directly in
machine language is time-consuming and tedious. Human
beings think in words and concepts rather than encoded
numbers. so each CPU operation and resource is given a
name and standard abbreviation ("mnemonic"). Programs
are more easily discussed using these standard mnemonics.
or "assembly language." and may be typed into an Intei'·
Intellec® 800 or Series Il® microcomputer development
system in this form. The development system can mechanically translate the program from assemhly language
"source" form to machine language' "object" code using a
program called an "assembler." The MCS-SI'· assemhler
is called ASMSI.
Two digit decimal numbers may be "packed" in an eightbit value, using four bits for the binary code of each digit.
This is called Binary-Coded Decimal (BCD) representation, and is often used internally in programs which
interact heavily with human beings.
There are several important differences between a computer's machine language and the assembly language used
as a tool to represent it. The machine language or instruction set is the set of operations which the CPU can
perform while a program is executing ("at run-time"). and
is strictly determined by the microcomputer hardware
design.
Alphanumeric characters (letters, numbers, punctuation
marks, etc.) are often represented using the American
Standard Code for Information Interchange (ASCII)
convention. Each character is associated with a unique
seven-bit binary number. Thus one byte may represent
I
The assembly language is a standard (though more-orless arbitrary) set of symbols including the instruction ,et
mnemonics, but with additional features which further
simplify the program design process. For example.
ASMSI has controls for creating and formaning a program listing. and a number of directives for allocating
variable storage and inserting arbitrary hytes of data into
the ohject code for creating table> of con,tants.
0
07
06
05
04
03
02
01
DO
Figure 2. Representation of Bits Within an Eight-Bit
"Byte" (Value shown = 01010001 Binary =
81 decimal).
AFN-01502A·06
2-4
AP-69
In addition. ASM51 can perform sophisticated mathematical operations. computing addresses or evaluating
arithmetic expressions to relieve the programmer from
this drudgery. However. these calculations can only use
information known at "assembly time."
assembly language by a series of ones and zeros
(naturally). followed by the letter "B" (for Binary); octal
numbers as a series of octal digits (0-7) followed by the
letter "0" (for Octal) or "Q" (which doesn't stand for anything. but looks sort of like an "0" and is less likely
to be confused with a zero).
For example. the 8051 performs arithmetic calculations
at run-time. eight bits at a time. ASM51 can do similar
operations 16 bits at a time. The 8051 can only do one
simple step per instruction. while ASM51 can perform
complex calculaiions in each line of source code. However. the operations performed by the assembler may only
use parameter values fixed at assembly-time. not variables
whose values are unknown until program execution
begins.
Hexadecimal numbers are represented by a series of hexadecimal digits (0-9,A-F). followed by (you guessed it) the
letter "H." A "hex" number must begin with a decimal
digit; otherwise it would look like a user-defined symbol
(to be discussed later). A "dummy" leading zero may be
inserted before the first digit to meet this constraint. The
character string "BACH" could be a legal label for a
Baroque music synthesis routine; the string '~OBACH" is
the hexadecimal constant BAC,.. This is a case where
adding 0 makes a big difference.
For example. when the assembly language source line,
ADD
A,#(LOOP_COUNT + I) * 3
Decimal numbers are represented by a sequence of decimal
digits. optionally followed by a "D." If a number has no
suffix. it is assumed to be decimal-so it had better not
contain any non-decimal digits. "OBAC" is not a legal
representation for anything.
is assemhled. AS M51 will find the value of the previously-defined constant "LOOP_COUNT" in an internal
symbol table. increment the value. mUltiply the sum by
three. and (assuming it is between -256 and 255 inclusive)
truncate the product to eight bits. When this instruction
is executed. the 8051 ALU will just add that resulting
constant to the accumulator.
When an ASCII code is needed in a program. enclose the
desired character between two apostrophes (as in 'W) and
the assembler will convert it to the appropriate code (in
this case 23H). A string of characters between apostrophes is translated into a series of constants; 'BACH'
becomes 42H. 41 H, 43H. 48H.
Some similar differences exist to distinguish number
system ("radix") specifications. The 8051 does all computations in binary (though there are provisions for then
converting the result to decimal form). In the course of
writing a program, though. it may be more convenient
to specify constants using some other radix, such as base
Hr.,On other occasions.it is desirable to specify the ASCII
code for some character or string of characters without
refering to tables. ASM51 allows several representations
for constants. which are converted to binary as each
instruction is assembled.
These same conventions are used throughout the associated Intel documentation. Table 2 illustrates some of the
different number formats.
2. ARCHITECTURE AND ORGANIZATION
Figure 3 blocks out the MCS-51'· internal organization.
Each microcomputer combines a Central Processing
Unit, two kinds of memory (data RAM plus program
ROM or EPROM), Input/Output ports. and the mode.
For example. binary numbers are represented in the
Table 2. Notations Used to Represent Numbers
Bit Pattern
00000000
00000001
...............
00000111
00001000
00001001
00001010
...............
0000 1 1 1 1
00010000
...............
o1
1 1 1 1 1 1
10000000
10000001
...............
1 1 1 1 1 1 10
111111 I I
Binary
Octal
HexaDecimal
Decimal
OB
IB
OQ
IQ
OOH
OIH
IIIB
1000B
100lB
10 lOB
7Q
IOQ
IIQ
12Q
07H
08H
09H
OAH
IIIIB
looOOB
17Q
20Q
OFH
IOH
15
16
177Q
200Q
20lQ
127
128
129
........
...
7FH
80H
81H
1l111l10B
IIIIIIIIB
376Q
377Q
OFEH
OFFH
254
255
..
..
..
lllllllB
10000000B
1000000lB
'"
. ..
0
I
Signed
Decimal
0
+1
...
..
. ...
...
..
. ...
...
...
7
8
9
10
"
...
+7
+8
+9
+10
+15
+16
....
+127
-128
-127
....
-2
-I
AFN·01502A·07
2-5
AP-69
TIMER
CONTROL
Figure 3. Block Diagram of 8051 Internal Structure
status. and data registers and random logic needed for
a variety of peripheral functions. These elements communicate through an eight-bit data bus which runs
throughout the chip. somewhat akin to indoor plumbing.
This bus is buffered to the outside world through an I/O
port when memory or I/O expansion is desired.
Let's summarize what each block does: later chapters dig
into the CPU's instruction set and the peripheral registers
in much greater detail.
Central Processing Unit
The CPU is the "brains" of the microcomputer. reading
the user's program and executing the instructions stored
therein. Its primary elements are an eight-bit Arithmetic/
Logic Unit with associated registers A. B, PSW. and SP.
and the sixteen-bit Program Counter and "Data Pointer"
registers.
2-6
intJ
AP-69
Arithmetic Logic Unit
•
•
•
•
•
The ALU can perform (as the name implies) arithmetic
and logic functions on eight-bit variables. The former
include basic addition. subtraction. multiplication. and
division; the latter include the logical operations AND.
OR. and Exclusive-OR. as well as rotate. clear. complement. and so forth. The ALU also makes conditional
branching decisions. and provides data paths and temporary registers used for data transfers within the system.
Other instructions are built up from these primitive functions: the addition capability can increment registers or
automatically compute program. destination addresses;
subtraction is also used in decrementing or comparing the
magnitude of two variables:
Arithmetic Operations
Logical Operations for Byte Variables
Data Transfer Instructions
Boolean Variable Manipulation
Program Branching and Machine Control
MCS-48'· programmers perusing Table 4 will notice the
absence of special categories for Input/Output. Timer!
Counter. or Control instructions. These functions are all
still provided (and indeed many new functions are added).
but as special cases of more generalized operations in
other categories. To explicitly list all the useful instructions involving I/O and peripheral registers would require
a table approximately four times as long.
Observant readers will also notice that all of the 8048's
page-oriented instructions (conditional jumps. JMPP.
MOVP. MOVP3) have been replaced with corresponding
but non-paged instructions. The 8051 instruction set is
entirely /loll-page-oriented. The MCS-48'· "MOVP"
instruction replacement and all conditional jump instructions operate relative to the program counter. with the
actual jump address computed by the CPU during instruction execution. The "MOVP3" and "JM PP" replacements
are now made relative to another sixteen-bit register.
which allows the effective destination to be anywhere in
the program memory space. regardless of where the
instruction itself is located. There are even three-byte
jump and call instructions allowing the destination to be
an,l'll'here in the 64K program address space.
These primitive operations are automatically cascaded
and combined with dedicated logic to build complex
instructions such as incrementing a sixteen-bit register
pair. To execute one form of the compare instruction. for
example. the 8051 increments the program counter three
times. reads three bytes of program memory. computes a
register address with logical operations. reads internal
data memory twice. makes an arithmetic comparison of
two variables. computes a sixteen-bit destination address.
and decides whether or not to make a branch-all in two
microseconds!
An important and unique feature of the MCS-51 architecture is that the ALU can also manipulate one-bit as
well as eight-bit data types. Individual bits may be set.
cleared. or complemented. inoved. tested. and used in
logic computations. While support for a more primitive
data type may initially seem a step backwards in an era
of increasing word length. it makes the 8051 especially
well suited for controller-type applications. Such algorithms inherent~1' involve Boolean (true/false) input
and output variables. which were heretofore difficult to
implement with standard microprocessors. These features
are collectively referred to as the MCS-51'· "Boolean
Processor." and are described in the so-named chapter
to come.
The instruction set is designed to make programs efficient
both in terms of code size and execution speed. No
instruction requires more than three bytes of program
memory. with the majority requiring only one or two
bytes. Virtually all instructions execute in either one or
two instruction cycles-one or two microseconds with
a 12-MH7. crystal-with the sole exceptions (multiply
and divide) completing in four cycles.
Many instructions such as arithmetic and logical functions or program control. provide both a short and a long
form for the same operation. allowing the programmer
to optimi7.e the code produced for a specific application.
The 8051 usually fetches two instruction bytes per instruction cycle. so using a shorter form can lead to faster
execution as well.
Thanks to this powerful ALU. the 8051 instruction set
fares well at both real-time control and data intensive
algorithms. A total of 51 separate operations move and
manipulate three data types: Boolean (I-bit). byte (8-bit).
and address (16-bit). All told. there are eleven addressing
modes-seven for data. four for program sequence control (though only eight are used by more than just a few
speciali7.ed instructions). Most operations allow several
addressing modes. bringing the total number of instructions (operation/addressing mode combinations) to III.
encompassing 255 of the 256 possible eight-bit instruction opcodes.
For example. any byte of RAM may be loaded with a
constant with a three-byte. two-cycle instruction. but the
commonly used "working regi~ters" in RAM may be
initiali7.ed in one cycle with a two-byte form. Any bit
anywhere on the chi p may be set. cleared. or complemented by a single three-byte logical instruction using
two cycles. But critical control bits. I/O pins. and software flags may be controlled by two-byte. single cycle
instructions. While' three-byte jumps and calls can "go
anywhere" in program memory. nearby sections of code
may be reached by shorter relative or absolute versions.
Instruction Set Overview
Table 4 lists these III instructions classified into five
groups:
AFN-Q1502A-09
2-7
inter
AP-69
(MSB)
I I
Cy
'(LSB)
AC
FO
Symbol Position
CY
PSW 7
RS1
I I
RSO
Symbol Position Name and Significance
OV
PSW2
Overflow flag.
Set/cleared by hardware during arithmetic instructions to indicate overflow
conditions.
OV
Name and Significance
Carry flag.
Set/cleared by hardware or software
during certain arithmetic and logical
PSW.I
(reserved)
PSWO
Parity flag.
Set/cleared by hardware each instruction cycle to indicate an odd/even
number of "one" bits in the accumulator. i.e .• even parity.
Note-
the contents of(RSI. RSO) enable the
instructions.
P
AC
PSW6
Auxiliary Carry flag.
Set/cleared by hardware during addition
or subtraction instructions to indicate
carry or borrow out of bit 3.
FO
PSW5
Flag 0
Set/cleared/tested by software as a
user-defined status flag.
RSI
PSW.4
RS
PSW.3
working register banks as follows:
(0.0) .. Bank
(0.1) . Bank
(I,O)---Bank
(1.1) -Bank
Register bank Select control bits I & O.
Set/cleared by software to determine
working register bank (see Note).
0
I
2
3
(OOH-07H)
(OSH-OFH)
(IOH-I7H)
(ISH-IFH)
Figure 4. PSW-Program Status Word Organization
A significant side benefit of an instruction set more
powerful than those of previous single-chip microcomputers is that it is easier to generate applications-oriented
,software. Generalized addressing modes for byte and bit
instructions reduce the number of source code lines
written and debugged for a given application. This leads
in turn to proportionately lower software costs. greater
reliability. and faster design cycles.
and rotates. The carry also serves as a "Boolean accumulator" for one-bit logical operations and bit manipulation.
instructions. The overflow flag (OV) detects when arithmetic overflow occurs on signed integer operand~, making
two's complement arithmetic possible. The parity flag
(P) is updated after every instruction cycle with the evenparity of the accumulator contents.
The CPU does not control the two register-bank select
bits, RS I and RSO. Rather, they are manipulated by
software to enable one of the four register banks. The
usage of the PSW flags is demonstrated in the Instruction Set chapter of,this Note.
Accumulator and PSW
The 8051, like its 8048 predecessor, is primarily an
accumulator-based 'architecture: an eight-bit register
called the accumulator ("A") holds a sour.ce operand and
receives the result of the arithmetic instructions (addition.
subtraction, multiplication, and division). The accumulator can be the source or destination for logical operations
and a number· of special data movement instructions.
including table look-ups and external RAM expansion.
Several functions apply exclusively to the accumulator:
rotates, parity computation, testing for zero, and so on.
Even though the architecture is accumulator-based, provisions have been made to bypass the accumulator in
common instruction situations. Data may be moved from
any location on-chip to any register. address, or indirect
address (and vice versa), any register may be loaded with
a constant, etc., all without affecting the accumulator.
Logical operations may be performed against registers or
variables to alter fields of bits-without using or affecting
the accumulator. Variables may be incremented, decremented, or tested without using the accumulator. Flags
and control bits may be manipulated and tested without
affecting anything else.
Many instructions implicitly or eXp'licitly affect (or are
affected by) several status 'flags, which are grouped
together to form the Program Status Word shown in
Figure 4.
(The period wiihin entries under the Position column is
called the "dot operator," and indicates a particular bit
position within an eight-bit byte. "PSW.5" specifies bit 5
of the PSW. Both the documentation and ASM51 use
this notation.)
Other CPU Registers
A special eight-bit register ("B") serves in the execution of
the multiply and divide instructions. This register is used
in, conjunction with the accumulator as the second input
operand and to return eight-bits of the result.
The mos!'''active'' statuS bit is called the carry flag (abbreviated "C"). This bit makes possible multiple precision
arithmetic 6perations including addition, subtraction,
The MCS-51 family processors include a hardware stack
within internal RAM, useful for subroutine linkage,
AFN-01S02A-10
2-8
infef
AP-69
passing parameters between routines, temporary variable
storage, or saving status during interrupt service routines.
The Stack Pointer (SP) is an eight-bit pointer register
which indicates the address of the last byte pushed onto
the stack. The stack pointer is automatically incremented
or decremented on all push or pop instructions and all
subroutine calls and returns. [n theory, the stack in the
8051 may be up to a full 128 bytes deep. (In practice, even
simple programs would use a handful of RAM locations
for pointers, variables, and so forth-reducing the stack
depth by that number.) The stack pointer defaults to 7 on
reset, so that the stack will start growing up from location
8,just like in the 8048. By altering the pointer contents the
stack may be relocated anywhere within internal RAM.
are addressed using the Program Counter or instructions
which generate a sixteen-bit address.
To stretch our analogy just a bit, data memory is like a
mouse: it is smaller and therefore quicker than program
memory, and it goes into a random state when electrical
power is applied. On-chip data RAM is used for variables
which are determined or may change while the program
is running.
A computer spends most of its time manipUlating variables, not constants, and a relatively small number of
variables at that. Since eight-bits is more than sufficient
to uniquely address 128 RAM locations, the on-chip
RAM address register is only one byte wide. [n contrast
to the program memory, data memory accesses need a
single eight-bit value-a constant or another variableto specify a unique location. Since this is the basic width
of the ALU and the different memory . types, those
resources can be used by the addressing mechanisms,
contributing greatly to the computer's operating efficiency.
Finally, a 16~bit register' called the data pointer (DPTR)
serves as a base register in indirect jumps, table look-up
instructions, and external data transfers. The high- and
low-order halves 'Of the data pointer may be manipulated
as separate registers (DPH and DPL, respectively) or
together using special instructions to load or increment
all sixteen bits. Unlike the 8048, look-up tables can therefore start anywhere in program memory and be of
arbitrary length.
The partitioning of program and data memory is extended
to off-chip, memory expansion. Each may be added
independently, and each uses the same address and data
busses, but with different control signals. External program memory is gated onto the external data bus by the
PSEN (Program Store Enable) control output, pin 29.
External data memory is read onto the bus by the RD
output, pin 17, and written with data supplied from the
microcomputer by the WR output, pin 16. (There is no
control pin to write external program ROM, which is by
definition Read Only.) While both types may be expanded
to up to 64K bytes, the external data memory may
optionally be expanded in 256 byte "pages" to preserve
the use of P2 as an I}O port. This is useful with a relatively
small expansion RAM (such as the [ntel® 8155) or for
addressing external peripherals.
Single-chip controller programs are finalized during the
project design cycle, and are not modified after production. [ntel's single-chip microcomputers are not "von
Neumann" architectures common among main-frame
and miniccomputer systems: the MCS-51 ,. processor
dala memory-on-chip and external-may 1101 be used
for program code. Just as there is no write-control signal
for program memory, there is no way for the CPU to
execute instruct-ions out of RAM. [n return, this concession allows an architecture optimized for efficient
controller applications: a large, fixed program located in
ROM, a hundred or so variables in RAM, and different
methoils for efficiently addressing each.
Memory Spaces
Program memory is separate and distinct from data
memory. Each memory type has a different addressing
mechanism, different control signals, and a different
function.
The program memory array (ROM or EPROM), like an
elephant, is extremely large and never forgets information, even when power is removed. Program memory is
used for information needed each time power is applied:
initiali7.ation values, calibration constants, keyboard
layout tables, etc., as well as the program itself. The program memory has a sixteen-bit address bus; its elements
(Von Neumann machines are.helpful for software development and debug. An 8051 system could be modified to
have a single off-chip memory space by gating together
the two memory-read controls (PSEN and RD) with a
two-input AND gate (Figure 5). The CPU could then
write data into the common memory array using W Rand
AFN-01S02A-l t
2-9
inter
8051
AP-69
WI!
~ 1miWII}
L-_ _ _
I'mi_IIII-I
IiEIIliII
TO
MEMORY
ARRAY
Figure 5. Combining External Program and Data
Memory Arrays
external data transfer instructions, and read instructions
or data with the AND gate output and data transfer or
program memory look-up instructions.)
In addition to the memory arrays, there is (yet) another
(albeit sparsely populated) physical address space. Connected to the internal data bus are a score of specialpurpose eight-bit registers scattered throughout the chip.
Some of these-B, SP, PSW, DPH, and DPL-have
been discussed above. Others-I/O ports and peripheral
function registers-will be introduced in the following
sections. Collectively, these registers are designated as the
"special-function register" address space. Even the accumulator is assigned a spot in the special-function register
address space for additional flexibility and uniformity.
Input/Output Ports
The MCS-SI'· I/O port structure is extremely versatile.
The 80S1 and 87S1 each have 32 I/O pins configured as
four eight-bit parallel ports (PO, PI, P2, and P3). Each pin
will 'input or output data (or both) under software control, and each may be referenced by a wide repertoire of
byte and bit operations.
Thus, the M CS-SI'· architecture supports several distinct
"physical" address spaces, functionally separated at the
hardware level by different addressing mechanisms, read
and write control signals, or both:
•
.•
•
•
•
On-chip program memory;
On-chip data memory;
Off-chip program memory;
Off-chip data memory;
On-chip special-function registers.
In various operating or expansion modes, some of these
I/O pins are also used for special input or output functions. Instructions which access external memory use'
Port 0 as a multiplexed address/data bus: at the beginning
of an external memory cycle eight bits of the address are
output on PO; later data is transferred on the same eight
pins. External data transfer instructions which supply
a sixteen-bit address, and any instruction accessing
external program memory, output the high-order eight
bits on P2 during the access cycle. (The 8031 alll'ays uses
the pins of PO and P2 for external addressing, but P I and
P3 are available for standard I/O.)
What the programmer sees, though, are "logical" address
spaces. For example, as far as the programmer is
concerned,. there is only one type of program memory,
64K bytes in length. The fact that it is formed by combining on- and off-chip arrays (split 4K/60K on the 80S1
and 87S1) is "invisible" to the programmer; the CPU
automatically fetches each byte from the appropriate
array, based on its address.
(Presumably, future microcomputers based on the
MCS-SI ,. architecture may have a different physical split,
with more or less of"the 64K total implemented on-chip.
Using the' MCS-48'· family as a precedent, the 8048's 4K
potential program address space was split I K/ 3K between
on- and off-chip arrays; the 8049's was split 2KJ2K.)
The eight pins of Port 3 (P3) each have a special function.
Two external interrupts, two counter inputs, two serial
data lines, and two timing control strobes use pIns of P3
as described in Figure 6. Port 3 pins corresponding to
functi9ns not used are available for conventional 1/0.Even within a single port, I/O functions may be combined
in many ways: input and output may be performed using
different pins at the same time, or the same pins at different
times; in parallel in some cases, and in serial in others; as
test pins, or (in the case of Port 3) as additional special
functions.
Why go into such tedious details about address spaces?
The logical addressing modes are described in the Instruction Set chapter in terms of physical address spaces.
Understanding their differences now will payoff in understanding and using the chips later.
2-10
AP-69
(MS8)
I I I
RD
WR
(LS8)
Tl
Symbol Position
1'3.7
RD
WR
1'3.6
TO l'Nn
I I I I
INTO
TXD
RXD
Name and Significance
Read data control output. Active low
pulse generated by hardware when
external data memory is read.
Symbol Position
INTI
1'3.3
Name and Significance
Interrupt I input pin. Low-level or
falling-edge triggered.
INTO
1'3.2
Interrupt 0 input pin. Low-level or
falling-edge triggered.
TXD
1'3.1
Transmit Data pin for serial port in
Write data control output. Active low
pulse generated by hardware when
external data memory b wriucn.
UART mode. Clock output in shift
Tl
1'3.5
Timer/counter I external input or test
register mode.
pin.
RXD
TO
PH
Timer/counter 0 external input or test
1'3.0
Receive Data pin fo'r serial port in
UART mode. Data I/O pin in shift
register mode.
pin.
Figure 6. P3-Alternate Special Functions of Port 3
software-accessible). These registers are called. naturally
enough. THO. TLO. TH I. and TLI. Each pair may be
independently software programmed to any of a d07en
modes with a mode register designated TMOD (Figure
7). and controlled with register TCON (Figure 8).
The timer modes can be used to measure time intervals.
determine pulse widths. or initiate events. with one-microsecond resolution. up to a maximum interval of 65.536
instruction cycles (over 65 milliseconds). Longer delays
may easily be accumulated through software. Configured
as a counter. the same hardware will accumulate external
events at frequencies from D.C. to 500 KHz. with up to
sixteen bits of precision.
Serial Port Interface
Until now, microprocessor systems needed peripheral
chips such as timer/counters. USARTs. or interrupt controllers to meet these needs. The 8051 integrates all of
these capabilities on-chip!
Each microcomputer contains a high-speed, full-duplex.
serial port which is software programmable to function
in' four basic modes: shift-register I/O expander. 8-bit
UART. 9-bit UART. or interprocessor communications
link. The UART modes will interface with standard I/O
devices (e.g. CRTs. teletypewriters. or modems) at data
rates from 122 baud to 31 kilobaud. Replacing the
standard 12 MHz crystal with a 10.7 MHz crystal allows
110 baud. Even or odd parity (if desired) can be included
with simple bit-handling software routines. Inter-processor
communications in distributed systems takes place at 187
kilobaud with hardware for automatic add.ress/data
message recognition. Simple TTL or CM OS shift registers
provide low-cost I/O expansion at a super-fast I Megabaud. The serial port operating modes are controlled by
the contents of register SCON (Figure 9).
Timer/Counters
Interrupt Capability and Control
There are two sixteen-bit multiple-mode Timer/Counters
on the 8051. each consisting of a "High" byte (corresponding to the 8048 "T" register) and a low byte (similar to· the
8048 prescaler. with the additional flexibility of being
(Interrupt capability is generally considered a CPU
function. It is being introduced here since. from an applications point of view, interrupts relate more closely to
peripheral and system interfacing.)
Special Peripheral Functions
There are a few special needs common among controloriented computer systems:
• keeping track of elapsed real-time;
• maintaining a count of signal transitions;
• measuring the precise width of input pUlses;
• communicating with other systems or people;
• closely monitoring asynchronous external events.
AFN-01S02A-13
2-11
AP-69
(MSB)
I
GATE
(LSB)
I I
CIT
M1
MO
I
GATE
I
CIT
M1
MD
I
M1
MO
o
o
~\
TIMER 1
Operating Mode
MCS-48 Timer. "TLx" serves as fivebit prescaler.
TIMER 0
o
16-bit timer· counter. "THx" and "TLx"
are cascaded~ there is 'no presca'ier.
o
GATE
Gating control. When set, Timer/counter
"x"·is enabled only while "INTx" pin is
high and "TRx" control bit is set. When
cleared, timer/counter is enabled
whenever "TRx" control bit is set.
CjT
Timer or Counter Selector. Cleared for
Timer operation (input from internal
system clock). Set for Counter operation (input from "Tx" input pin).
8-bit auto-reload timer counter. "THx"
holds a value which is to be reloaded
into ··TLx·· each time it overflows.
(Timer 0)
TLO is an eight-bit timer
counter controlled bv the
standard Timer 0 co~trol
bits.
.
THO is an eight-bit timer
only controlled by Timer I
control bits.
(Timer I)
Timer,counter I stopped.
Figure 7. TMOD-Timer/Counter Mode Register
(MSB)
I
TF1
I
TR1
TFO
I
(LSB)
TRO
IE1
IT1
lEO
I
ITO
Symbol Position Name and Significance
lEI
TCON.3 Interrupt I Edge flag. Set by hardware
when external interrupt edge detected.
Cleared when interrupt processed.
Symbol Position Name and Significance
TFI
TCON.7 Ti.mer I overflow Flag. Set by hardware
on timer/counter overflow. Cleared
when interrupt processed.
TRI
TCON.6
Timer I Run control bit. Set/cleared
by software to turn timer/counter
on/off.
TFO
TCON.5
Timer 0 overflow Flag. Set by hardware
on timer/counter overflow. Cleared
when interrupt processed.
TRO
TCON.4
Timer 0 Run control bit. Set/cleared by
software to tUTn timer/counter on/off.
ITI
TCON.2
Interrupt I Type control bit. Sct cleared
by software to specify falling edge low
level triggered external interrupts.
I Ell
TCON.I
Interrupt 0 Edge flag. Set by hardware
when external interrupt edge detected.
Cleared when interrupt processed.
ITO
TCON.O
Interrupt 0 Type control bit. Set 'cleared
by software to specify falling edge low
level lriggered external interrupts.
Figure 8. TCON-Timer/Counter Control/Status Register
AFN-01502A-14
2-12
AP-69
Symbol Posillon Name and Significance
Symbol Position Name and Significance
SMO
SCON.7
Serial port Mode control bit O.
Sct/cleared by software (sce note).
RB8
SCON.2
Receive Bit 8. Set/c1cared by hardware
to indicate stale of ninth data bil
SMI
SCON.6
Serial port Mode control bit I.
Set/cleared by software (see note).
TI
SCON.I
Scrial port Modc control bit 2. Set by
softwarc to disable reception of frames
for which bit 8 is zero.
Transmit Intcrrupt flag. Set by hardware when byte transmitted. C1cared
by software after servicing.
RI
SCON.O
Received Inlerrupt flag. Set by hardware when byte received. Cleared by
Note-
the state of (SMO.SM I) "Ieets:
(0,0) --Shift register 110 expansion
(0.1)·-8 bit UART. variable data rate.
(1.0)--9 bit UART. fixed data rate.
(1.1)--9 bit UART. variable data rate.
received.
SM2
REN
TB8
SCON.5
SCON.4
SCON.3
Receiver Enable control bit. Set/clcared
by software to enable/disable serial
data reception.
software after servicing.
Transmit Bit 8. Set/clcared by hardware to determine state of ninth data
bit transmitted in 9-bit UART modc.
Figure 9. SCON-Serial Port Control/Status Register
These peripheral functions allow special hardware to
monitor real-time signal interfacing without bothering
the CPU. For example, imagine serial data is arriving from
one CRT while being transmitted to another, and one
timer/counter is tallying high-speed input transitions
while the other measures input pulse widths. During all
of this the CPU is thinking about something else.
But how does the CPU know when a reception, transmission, count, or pulse is finished? The 8051 programmer
can choose from three approaches.
TCON and SCON contain status bits set by the hardware
when a timer overflows or a serial port operation is completed. The first technique reads the control register into
the accumulator, tests the appropriate bit, and does a
conditional branch based on the result. This "polling"
scheme (typically a three-instruction sequence though
additional instructions to save and restore the accumulator may sometimes be needed) will surely be
familiar to programmers used to multi-chip microcomputer systems and peripheral controller chips. This
process is rather cumbersome, especially when monitoring
multiple peripherals.
background task long enough to handle the appropriate
device, then return to the point where it left off.
This is the basis of the third and generally optimal solution, hardware interrupts. The 8051 has five interrupt
sources: one from the serial port when a transmission or
reception is complete, two from the timers when overflows occur, and two from input pins INTO and INTI.
Each source may be independently enabled or disabled
to allow polling on some sources or at some times, and
each may be classified as high or low priority. A high
priority source can interrupt a low priority service
routine; the manager's boss can interrupt conferences
with subordinates. These options are selected by the interrupt enable and priority control registers, IE and IP
. (Figures 10 and II).
Each source has a particular program memory address
associated with it (Table 3), starting at 0003H (as in the
8048) and continuing at .eight-.byte intervals. When an
event enabled for interrupts occurs the CPU automatically
executes an internal subroutine call to the corresponding
address. ·A us_er subroutine starting at this location (or
jumped to from this location) then performs the instructions to service that particular source. After completing
the interrupt service routine, execution returns to the
background program.
As a second approach, the 8051 can perform a conditional
branch based on the state of any control or status bit or
input pin in a single instruction; a four instruction
sequence could poll the four simultaneous happenings
mentioned above in just eight microseconds.
Table 3. 8051 Interrupt Sources and Service Vectors
Unfortunately, the CPU must still drop what it's doing
to test these bits. A manager cannot do his own work
well if he is continuously monitoring his subordinates;
they should interrupt him (or her) only when they need
attention or guidance. So it is with machines: ideally, the
CPU would not have to worry about the peripherals until
they require servicing. At that time, it would postpone the
Interrupt
Source
Service Routine
Starling Address
(Reset)
External 0
Timer/Counter 0
External I
Timer/ Counter I
Serial Port
OOOOH
0OO3H
OOOBH
OOl3H
OOIBH
0023H
AFN-01502A-1S
2-13
inter
AP-69
IMSB)
ILSB)
ES
ET1
EX1
ETO
I
EXO
I
Symbol Position Name and Significance
EA
IE.7
Enable All control bit. Cleared by
software to disable all interrupts.
independent of the stale of IE.4-IE.O.
ES
ETI
Symbol Position Name and Significance
EXI
IE.2
Enable External interrupt I control bit.
Set cleared by software to enable
disable interrupts from INTI.
IE.6
IE.5
(reserved)
(reserved)
ETO
IE.I
Enable Timer 0 control bit. Set cleared
by software to enable disable interrupts
from timer counter 0
IE.4
Enable Serial port control bit.
Set/cleared by software to enable
disable interrupts from TI or RI flags.
EXO
IE.O
Enable External interrupt 0 control bit.
Set cleared by software to enable
disable interrupts from INTO.
IE.3
Enable Timer I control bit. SeUcieared
by software to enable/disable interrupts
from timer/counter I.
Figure 10. IE-Interrupt Enable Register
IMSB)
I-
ILSB)
PS
1
Symbol Position
IP.7
IP.6
IP.5
PS
PTI
IP.4~
JP.3
PT1
I, px, 1PT. I px. I
Name and Significance
(reserved)
(reserved)
(reserved)
Symbol POSition Name and Significance
PXI
IP.2
External interrupt I Priority control
bit. Set cleared by software to specify
high low priority interrupt, for INTI.
Serial port Priority control bit.
Set/cleared by software to specify
high/low priority interrupts for Serial
port.
PTO
Timer I Priority control bit.
Set/cleared by software to specify
high/low priority interrupts for
timer/counter I.
PXO
IP.I
Timer 0 Priority control bit.
Set cleared by software to specify
high low priority interrupts for
timer counter O.
IP.O
External interrupt 0 Priority control
bit. Set cleared by software to specify
high low priority interrupts for INTO.
Figure 11. IP-Interrupt Priority Control Register
AFN-OtS02A-16
2-14
inter
AP-69
Table 4. MCS-51'" Instruction Set Description
DATA TRANSFER (conI.)
ARIIIIMHIC OPERA1IONS
!\tnernnnic
.\1)))
A.Rn
AIlD
·\.dITCct
A.lQ1RI
ADD
AD))
.\.udJta
AnnC '\.Rn
ADDC A.dlrcct
A))))C
·\.Ca1 RI
,\nlle ,\.Ud.II.1
SllBB
A.Rn
SllHB
'\,dm:cl
SllBB
A.@'Ri
A)tdata
SUnB
A
I"C
I'\;C
Rn
direct
I'C
(a\RI
I'\C
me
mc
I)fT
!lIT
I'\;C
.\1(11
I>IV
J):\
A
Rn
dllect
~I\RI
DPI R
AI!
AU
A
I),,\cription
Add rcgl'lcf 10 Ac,"umul.llnT
Add dlreCl tntc 1U ,\n.'UIl1Ulalor
Add mUlrcct"RA\11ll Acculllul,l(nr
Add Immcdl:!lC data tn Accumulator
Add regl~tcr to Accumulatnr vdth c.lrr)
Add direct h~(c (() A "Ith c.!rr~ n.lg
Add mdm'ct R,\ M III A \Hlh c.trr~ flenement ,\n:ulllul.llor
Decrement reg"ter
Decrement due!:t b\le
Dc!:remcnt Indlrct:,'RAM
Im'rement Daw P(lmter
Mu!tlpl~ A & B
1l1\ldc A h\ B
Ilct:llllal Adlu,t Accumulator
Byte C)C
I
I
I
I
I
I
I
I
I
I
I
I
Or..tinatiun
A'\;i) rel!l~ler to Accut1lul.llor
A .....·f) dl;eci h\le to Accumulator
" . . .·1> Indlrect'RAM In Accurnul.ltor
MOVX
(wDPI R.A
PliSH
POP
XCH
direct
direct
A.Rn
XCH
XCH
A,dlrt'c!
A.@lR,
X('HI)
A.@lRI
8~te ('~c
I
I
I
I
I
I
ASD Immediate datil to Accul\lul.tlnr
A \;D AccuTl1ulator 10 direct b\'le
A 'iD Immedl..lte datJ to dln!ci byte
OR rt:gl~tt'r tll Accumulator
OR dm.'ct h\te to Accumul..llor
OR mdlrelt'RAM to Accul\lul... I<)f
OR Imrncdl.Jle data 10 Act:umulator
OR Accumulator to dIrect h\'tc
OR Immcdlatc dat.1 to dlrcct h\ tc
Exc!u,,\e-OR rCJP~t~'r 10 AClllmuJatnr
Exclu'-I\e-OR duect h\le to Accumulator
Exciu"\e-OR IndirecI'RAM to A
Exclu~l\e-OR Immediate data to A
E'{clu~l\e-()R Accumulator 10 dlrccl b\te
E'(clu~ne-OR zmmcc.llate data to dlrec!
Clear Accumulator
Complement Accumulator
Ro{att· Accumulator I cit
Rotale A I.ef! through the Carr) nag
Rotate Accumulator Right
Rolate A Right through Cany nag
Swap mhhlc' Within the Accumulator
Oe ..cription
M()\e regl~ter to Accumulator
Mtl\e direct b\'te to Accunmlalor
M(J\e inum:cl'RAM 10 Accumulaltlr
MO\t! lmmedlale d.lta to Accumuloltor
Mo\e Accumulator \l) Icg"tel
Mo\e direct h~\c 10 reg"lef
Mo\e Immcdl.Jte Juta 10 regl,ler
Mme Accumulator 10 d!r~'c! h~le
Mine regl ..tef to direct hyle
Mo\t! direct h\'te to dIrect
Mo\e Indlrcct'RAM to direct b\tc
M(l\e ImmedlJlc data to dllecl inte
M(He Accumulator to mdllecl IfAM
M<)\c dlfect h\te to mdlrect RAM
MO\e Immedl:ltc data III mdlrect RAM
I.oad Data Pmnter wllh a ](I-blt comtant
De..eriplion
Clear ('arr~ nag
Clear direct hu
Set Cm~ !lag
Sel direct BII
Cumplement Carr~ tlJg
Complt'ment dln:ct hll
A'\; I) direct bll to C;.rr~ IIJ!,!
A '\;1> wmpkment ul dlfect hl1to Colrr~
OR direct hll ttl CJrr~ nag
OR cmnplemcTlt 01 direct hit tn Carr~
Mmc e ..criprion
Subroutine ('a11
long: Suhroulllle ('.til
Return from ~uhroutlllt:
Return trnm mtcrrupt
Ah,olute .lump
IOl1g.l um r
Shorl .lump (relatne Jddr)
Jump IIldlfect rc\atl\e 10 the DPT R
Jump 11 Accumulalor" Zero
.lump II A<:cumulalnr l\ "I;tlt Zero
Jump II C.. rr:. nag" ~et
.lump II !'io ('arr~ flag
.lump J! dlreCI Bit ~et
.lump d dlfect Bit \l"ot ,et
Jump tI direct Hit 1\ ~et & Ck.. r hll
Compare direct 10 A & .lump II :"oiot Equal
CUTlIP Immed to A & Jump If '\;ot Equal
Comp Immed tu reg & Jump If "iol Equal
Comp Immed In Ind & Jump if :\lot Equal
Decrcment reg,,,[er & Jumr If '\;01 Zero
l>ecremenl direct & .lum" II '\;ot I.ero
'n nper.llllln
"h~olult'
data addre.... in~ mode.. :
Wnfl.lng reg"ter RO R 7
12X Inlern:iI RAM locatlon~, an~ I 0 port. conlrol or ~Iatu~ rcgl~ter
Inthrectilltermt! RAM iocatlUn addre~~ed h~ reg"ter RII or RJ
X-bit cnn,tJnt mduded In in,tructlllll
16-hll con~tant mduded a~ h\te~ ~ &.' of In~tructmn
12X ,ottv.arc nag~. an~ I 0 pm. conlrol or ,{.tIU, hl\
'op
I
I
I
I
I
,I
:\'ote" un
Rn
dITecl
(a)RI
;idata
#datal!l
hit
C.I~E
I
2
I
I
I
I
I
I
1l.l",Z
f).I'Z
C.I'\E
eJ",E
C)C
()c
rei
hlud
hll.rcl
bll.rel
A.d.rect.rd
A.*'dJla.ld
Rn.udata.rel
(wRI.#data.rel
Rn.rel
dlrel.'t.rel
.IB
.I",n
.I Be
CJ'\;F.
8)te
B)te
I
PROGRAM A:'On MAClII:'OI: CONTROL
[)AT·\ TRA \;~FER
VJnemunic
'l0V
A,Rn
MOV
A.l.llrect
M()V
A.(aIRI
MOV
\.tidala
\10V
Rn.A
MOV
H,n.dlfect
\10\'
Rn.*'d.II.1
MOV
dlfCCt.A
."-IO\'
dlrcct.Rn
\1()V
dllcct.dlrect
dlrect,(,alRI
MOV
MOV
I.hrect.tidata
(aIRI.A
MOV
(a1Rz,dlrect
MOV
M()V
«(lIRI.tidat ••
MOV
IlP I R.#datll l!l
De\cription
B)le (')'C
MIne Code hvtc reiatl\C to [)PfR 10 A
I
2
\10\C Code ",Ie rclatl\C to PC In A
I
Mmc E'I(,lcro.il RAM (1(·011 dddrlin A
I
Mmc E'(lcrn,J1 RAM (16·bn addr) to A
I
MO\~' A In E,lernoil RAM (H-hLt aodr)
I
Mmc A ttl r,lcrnal RAM (16-bll addr)
I
Pu,h direct tl\ Ie onto ,lac\..
Pop dIrect h~ic ]rom ,tad..
[,(change rcg.'\l'r "11h Accumulalm
F,(changt' direct h~lc "11h AccumulalOr
E'(changc mdlrect RAM '\dlh A
Exch.angl' hl\\-nrdcr DIg:lIlnU RAM .... A
8()()I.EAN VARIARU: .I\IASIPt·I.ATlON
I.O(;iCAI. OPERATIONS
:\Inernonic
A\;I
A.Rn
A'\; 1
A,dlrecl
A\;/.
A.@RI
A\;I
A.Mata
A\;L
dlrect.A
A'\; 1
dlrect.#data
ORI
A.Rn
ORI
A.dlrect
A,@JRI
ORI
A.#data
ORI
ORI
duec1.A
dlrec\.*tdata
ORI
XRI
A.Rn
XRI
A.dlfl'cl
A.(fURI
.xRI
XRI
A.*"data
xRI
t.hrect.A
dlrect.#dala
.XRI
CI R
A
CPI
~
RI
A
RIC
A
A
RR
A
RRe
SWAP A
Mnemonic
MOVe A.CWA+DP"J R
Move A.@A+I'C
MOVX A.@lRo
MOVX A.@IJPrR
MOVX @RJ.A
J
:'\iote.. on program addre....in2 mode .. :
addrl!l
De'tlTl.ltmn addre~~ tm I CAlI & I.lMP ma\ he otll\v.here "!lhm
the M-Kllnh~tl' prngrJm memnr~ Jddrc" ~pac~"
.
addrll
De~t1natHln addre .. , for ACAI I & A.lMP "II! rn: "!thm tht' 'arne
2-Klioh)IC pa!!t· 01 program m~'mor~ a, the tIT" h~le 01 the Inlhmlng
IIl~trLlctltln
rei
All
3. INSTRUCTION SET AND ADDRESSING MODES
S.lMP and all condillonJI tump~ mdude an X-hll ott,et h~,e R.Jn~e
+ 127 12X h~le, rel,ltl\C to flr,t byte 01 the fnllnv.mg lil,tructllln
mnemonlc~
I~
copynghted © Intel Corpnralmn 1979
group. this chapter starts with the addressing mode
classes and builds 10 include the related instructions.
The 8051 instruction set is extremely regular. in the sense
that most instructions can operate with variables from
several different physical or logical address spaces. Before
getting deeply enmeshed in the instruction sct proper. it
is important to understand the details of the most
common data addressing modes. Whereas Table 4 summari7es Ihe instructions set broken down by functional
Data Addressing Modes
MCS-51 assembly language instructions consist of an
operalion mnemonic and 7ero to three operands separated
by commas. In two operand instructions the destination
is specified first. then the source. Many byte-wide data
AFN·01502A-17
2-15
inter
AP-69
. operations (such as ADD or MOV) inherently use the
accumulator as a source operand and/or to receive the
result. For the sake of clarity the letter "A" is specified in
the source or destination field in all such instructions.
For example, the instruction,
ADD
hardware reset enables register bank 0; to select a
different bank the programmer modifies PSW bits 4 and
3 accordingly.
Example 2-Selecting Alternate Memory B.anks
PSW ••000100008
A.
will add the variableto the accumulator, leaving
the sum in the accumulator.
Register addressing in the 8051 is the same as in the 8048
family, with two enhancements: there are four banks
rather than one or two, and 16 instructions (rather than
12) can access them.
The operand designated "" above may use any
of four common logical addressing modes:
• Register-one of the working registers in the currently enabled bank.
• Direct-an internal RAM location, I/O port, or
special-function register.
• Register-indirect-an internal RA M location,
pointed to by a working register.
• Immediate data-an eight-bit constant incorporated
into the instruction.
Direct Byte Addressing
Direct addressing can access anyon-chip variable or
hardware register. An additional byte appended to the
opcode specifies the location to be used (Figure 12.b).
Depending on the highest order bit of the direct address
byte, one of two physical memory spaces is selected.
When the direct address is between 0 and 127 (00H-7FH)
one of the 128 low-order on-chip RAM locations is used.
(Future microcomputers based on the MCS-51'· architecture may incorporate more than 128 bytes of on-chip
RAM. Even if this is the case, only the low-order 128
bytes will be directly addressable. The remainder would·
be accessed indirectly or via the stack pointer.)
The first three modes provide access to the internal RA M
and Hardware Register address spaces, and may therefore
be used as source or destination operands; the last mode
accesses program memory and may be a source operand
only.
(It is hard to show a "typical application" of any instruc-
tion without involving instructions not yet described. The
following descriptions use only the self-explanatory ADD
and MOV instructions to demonstrate how the four
addressing modes are specified and used. Subsequent
examples will become increasingly complex.)
Example 3 - Adding RA M Location Contents
.DIRADR ADD CONTENTS OF RAM LOCATION 41H
TO CONTENTS OF RAN LOCATION 40H
OIRADR
ADD
MOV
The 8051 programmer has access to eight "working registers," numbered RO-R 7. The least-significant three-bits of
the instruction. opcode indicate one register within this
logical address space. Thus, a function code and operand
address can be combined to form a short (one byte)
instruction (Figure 12.a).
The 805 I assembly language indicates register addressing
with the symbol Rn (where n is from 0 to 7) or with a
symbolic name previously defined as a register by the
EQUate or SET directives. (For more information on
assembler directives see the Macro Assembler Reference
Manual.)
Example
PRTADR
• REGAO~ ADD CONTENTS OF REGISTER 1
TO CONTENTS OF REGISTER (]
MOV
A. RO
A, RI
flO. A
4-Adding Input Port Data to Output Port
Data
.
,PRTADR ADD DATA INPUT ON PORT J
TO DATA PREVl'OUSLY OUTPUT
ON PORT (]
Example I-Adding Two Registers Together
ADD
Mav
40H. A
All I/O ports and special function, control, or status
registers are assigned addresses between 128 and 255
(80H-OFFH). When the direct address byte is between
these limits the corresponding hardware register is
accessed. For example, Ports 0 and I are assigned direct
addresses 80H and 90H, respectively. A complete list is
presented in Table 5. Don't waste your time trying to
memorize the addresses in Table 5. Since programs using
absolute addresses for function registers would be difficult
to write or understand, AS M51 allows and understands
the abbreviations listed instead.
Register Addressing
REGADR
• SELECT BANI!. :2
MOV
A, PO
ADD
A. PI
MOV
PO. PI
Direct addressing allows all special-function registers in
the 8051 to be read, written, or used as instruction
operands. In general, this is the only method used for
accessing I/O ports and special-function registers. Ifdirect
addressing is used with special-function register addresses
other th(ln those listed, the result of the instruction is
undefined.
There are four such banks of working registers, only one
of which is active at a time. Physically, they occupy the
first 32 bytes of on-chip data RAM (addresses 0-1 FH).
PSW bits 4 and 3 determine which bank is active. A
AFN-01502A-1a
2-16
AP-69
The 8048 does nOl haye or need any generali/ed direct
addressing mude. since there arc only five special registers
(BUS. PI. P2. PSW. & T) rather than twenty. Instead. 16
special 8048 opcodes control output bits or read or write
each register to the accumulator. These functions arc all
subsumed by four of the 27 direct addressing instructions
of the 8051.
Indirect addressing on the 805 I is the same as in the
8048 family. except that all eight bits of the pointer register
contents are significant; if the contents point to a nonexistent memory location (i.e .. an address greater than
7FH on the 8051) the result of the instruction is undefined.
(Future microcomputers based on the MCS-5I'· architecture could implement additional memory in the
on-chip RAM logical address space at locations above
7FH.) The 8051 uses register-indirect addressing for five
new instructions plus the 13 on the 8048.
Table 5. 8051 Hardware Register Direct Addresses
Register
Address
KOH*
KI H
K2H
H.'H
HHH*
H9H
HAH
KBH
XCH
HDH
90H*
9XH*
99H
OAOH*
OAXH*
OBOH*
OBXH*
ODOH*
OEOH*
OFOH*
1'0
SP
1>1'1.
DPH
'ICO~
TMOD
11.0
11.1
rHO
rHI
1'1
SCO:'>:
SHliF
P2
IF
1'.'
II'
PSW
ACe
B
Function
Port 0
Immediate Addressing
Stack Pointer
Data Pointer (l.ow)
Data Pointer (High)
When a source operand is a constant rather than a variable (i.e. ~·the instruction uses a value known at assembly
time). then the constant can be incorporated into the
instruction. An additional instruction byte specifics the
value used (Figure 12.d).
Timer register
Timer Mode register
Timer 0
Timer I
Timer 0
Timer I
Port I
Low byte
Low byte
High byte
High byte
Port 3
The value used is fixed at the time of ROM manufacture
or EPROM programming and may not be altered during
program execution. In the assembly language immediate
operands are preceded by a number sign ("II"). The
operand may be either a numeric string. a symbolic
variable. or an arithmetic expression using constants.
I ntcrrupt Prionty rcgi~ter
Program Statu~ Word
Example
Serial Port Control regi~ter
Serial Port data Buffer
Port 2
Interrupt Enable regi!ttcr
Accumulator (direct addre,,)
B rcgi!tter
6 -~ Adding Constants Using Immediate
Addressing
• IMMADR ADO THE CONSTANT 12 IDECIMAL)
TO THE CONSTANT 34 (DECIMAL)
LEAVE SUM 1N ACCUMULATOR
• = hit addn:v.. :'lhlc: rcgl\lCr
IMMADR
MOV
A •• 12
A. _34
Register-Indirect Addressing
The preceding example was included for consistency; it
has little practical value. Instead. ASM51 could compute
the sum of two constants at assembly time.
How can you handle variables whose locations in RAM
arc determined. computed. or modified while the program
j; running? This situation arises when manipulating
se4uential memory locations. indexed entries within tables
in RAM. and mUltiple precision or string operations.
Regi,ter or Direct addressing cannot be used. since their
operand addresses are fixed at assembly time.
Example
,ASMSUM LOAD ACC WITH THE SUM OF
THE CONSTANT 12 (DECIMAL) AND
THE CONSTANT 34 (DECIMAL)
ASMSUM
The 8051 solution is "register-indirect RAM addressing:'
RO and R I of each register bank may operate as index
or pointer registers. their contents indicating an address
into RAM. The internal RAM location so addressed is
the actual operand used. The least significant bit of the
instruction opcode determines which register is used as
the "pointer" (Figure 12.c).
ADD
A,R
b.) Direct AddreSSing:
I : : >+.:
ADD
A.
: : /I : >+.++< : I
direct
c.) Register-Indirect Addressing:
I : : +.+
ADD
Example 5 -I ndirect Addressing
: : I; I
A.@R
d.) Immediate Addressing:
I : : >+.:
. INOAOR ADD CONTENTS OF MEMORY LOCATJON
ADDRESSED BY REGISTER 1
TO CONTENTS OF RAM LOCATION
ADDRESSED av REGISTER 0
MOV
ADD
MOV
MCV
a.) Register Addressing:
In the 8051 assembly language. register-indirect addressing
is represented by a commercial "at" sign ("@") preceding
RO. R I. or a symbol defined by the user to be e4ual to
RO or R I.
tNDADR
7 -Adding Constants Using ASM5 I
Capabilities
ADD
A. @Rl
: : II
A.#
: : :-~..: : : I
data
Figure 12. Data Addressing Machine Code Formats
+.: : :
Secondly, the interrupt logic is disabled from accepting
any other interrupts from the same or lower priority.
After completing the interrupt service routine, executing
an RETI (Return from Interrupt) instruction will return
execution to the point where the background program
was interrupted -- just like RET ~ while restoring the
interrupt logic to its previous state.
c.) Short Jump (SJMP rei):
1
:
:
II.-.I_ , e l . _
.. "
OI_I.el- - - '
Figure 15. Jump Instruction Machine Code
Formats
AFN-Ot502A-23
2-21
AP-69
Operate-and-branch instructions -
CJNE, DJNZ
Two groups of instructions combine a byte operation
with a conditional jump based on the results.
CJNE (Compare and Jump if Not Equal) compares two
byte operands and executes a jump if they disagree. The
carry flag is set following the rules for subtraction: if the
unsigned integer value of the first operand is less than
that of the second it is set; otherwise. it is cleared.
However. neither operand is modified.
The dollar sign in this example is a special character
meaning "the address of this instruction." It is useful in
eliminating instruction labels on the same or adjacent
source lines. CJNE and DJNZ (like all .conditional
jumps) use program-counter relative addressing for the
destination address.
Stack Operations -
PUSH, POP
The PUSH instruction increments the stack pointer by
one. then transfers the contents of the single byte variable
indicated (direct addressing only) into the internal RA M
location addressed by the stack pointer. Conversely.
POP copies the contents of the internal RAM location
addressed by the stack pointer to the byte variable
indicated. then decrements the stack pointer by one.
The C.INE instruction provides. in effect. a oneinstruction "case" statement. .This instruction may be
executed repeatedly. comparing the code variable to a list
of "special case" value: the code segment following the
instruction (up to the destination label) will be executed
only if the operands match. Comparing the accumulator
or a register to a series of constants is a convenient way to
check for special handling or error conditions; if none of
the cases match the program will continue with "normal"
processing.
(Stack Addressing follows the same rules. and addresses
the same locations as Register-indirect. Future microcomputers based on the MCS-51 ,. CPU could have up to
256 bytes of RAM for the stack.)
A typical example might be a word processing device
which receives ASCII characters through the serial port
and drives a thermal hard-copy printer. A standard
routine translates "printing" characters to bit patterns.
but control characters «DEL>' . . .
·. orvalue.
~OH. and processed with the printing characters.
Interrupt service routines must not change any variable
or hardware registers modified by the main program. or
else the program may not resume correctly. (Such a
change might look like a spontaneous random error.)
Resources used or altered by the service routine
(Accumulator. PSW. etc.) must be saved and restored to
their previous value before returning from the service
routine. PUSH and POP provide an efficient and
convenient way to save register states on the stack.
Example 16-Case Statements Using CJNE
Example 18 - Use of the Stack for Status Saving on
Interrupts
R7
CHAR
INTERP
CJNE
INTP
RET
CJNE
• CHARACTER. CODE VARIABLE
CHAR. '7FH. INTP __ 1
L.OC_TMP EQU
• REMEMBER LOCATION COUNTER
(SPECIAL ROUTINE FOR RUDOUT CODE)
-I
OR.
CHAR. tIo07H. INTP __2
(SPECIAL ROUTINE FOR BELL CODE)
L.JI'1P
0003H
SERVER
• STARTING ADDRESS FOR INTERRUPT ROUTINE
,.JUMP TO ACTUAL SERVICE ROUT INE LOCATEU
RET
INTP _2
C"'NE
INTP _:3
RET
CJNE
CHAR. 4tOAH. INTP __3
OR.
(SPECIAL ROUTINE FOR L.FEED CODE)
SERVER
INTP - 4
tNTP -
•
INTP _6
RET
CJNE
RET
CJNE
psw
PUSH
PUSH
PUSH
B
CHAR. IODH. INTP_4
<:)OH
• NULL CODE
POP
POP
• PROCESS STANDARD PRINTING
, CHARACTER
RETI
RET
DJNZ (Decrement and Jump if Not Zero) decrements
the register or direct address indicated and jumps if the
result is not zero. without affecting any flags. This
provides a simple means for executing a program loop a
given number of times. or for adding a moderate time
delay (from 2 to 512 machine cycles) with a single
instruction. For example. a 99-usec. software delay loop
can be added to code forcing an 110 pin low with only
two instructions.
ACC
• SAVE ACCUMUL.ATOR (NOTE DIRECT ADDRESSING
, NOTATION)
• SAVE B REGISTER
DPL
• SAVE DATA POINTER
DPH
,
PSW, '0000100013
• SELECT REGISTER IlANK 1
OPH
DPL
B
ACC
psw
,RESTORE REGISTERS
IN REVERSE ORnER
· RESTORE PSW AND RE-SELE'CT OR IGINAL.
, REGISTER BANK
· RETURN TO MAIN PROGRAM AND RESTORE
• INTERRUPT L.OGIC
If the SP register held I FH when the interrupt was
detected. then while the service routine was in progress
the stack would hold the registers shown in Figure 16; SP
would contain 26H.
The example shows the most general situation; if the
service routine doesn't alter the B-register and data
pointer. for example. the instructions saving and
restoring those registers would not be necessary.
The stack may also pass parameters to and from
subroutines. The subroutine can indirectly address the
parameters derived from the contents of the stack
pointer.
Example 17-lnserting a Software Delay with DJNZ
CL.R
1'10V
D.JNZ
SETB
L.OC_TMP ,RESTORE L.OCATION COUNTER
PUSH
PUSH
WR
R2, .49
R2."
WR
AFN-01S02A-24
2-22
AP-69
If the position of the motor is determined by the contents
of variable POSM I (a byte in internal RAM) and the
position of a second motor on Port 2 is determined by the
data input to the low-order nibble of Port 2. a sixinstruction sequence could update them both.
RAM
ADDR
7FH
26H
OPH
25H
OPL
2.H
"
23H
POSI11
ACC
22H
PSW
21H
PC (HIGH)
20H
PC (LOW)
.ou
51
PUSH
CALL
POSI11
NXTPOS
POP
PI
P'
PUSH
CALL
pap
IFH
NXTPOS
P2
Data Pointer and Table Look-up instructions MOV, INC, MOVC, JMP
DOH
Figure 16. Stack contents during interrupt
One advantage here is simplicity. Variables need not be
allocated for specific parameters. a potentially large
number of parameters may be passed. and different
calling programs may use different techniques for
determining or handling the variables.
For example. the following subroutine reads out a
parameter stored on the stack by the calling program.
uses the low order bits to access a local look-up table
holding bit patterns for driving the coils of a four phase
stepper motor. and stores the appropriate bit pattern
back in the same position on the stack before returning.
The accumulator contents are left unchanged.
Example 19 - Passing Variable Parameters to Subroutines Using the Stack
NXTPOS
Example 21 - Loading and Unloading Stack Direct
from 1/0 Ports
..-(SP)
MOV
DEC
DEC
RO. SP
XCH
A.@RO
ANL
ADO
A •• 2
Move
A. C!A .... PC ,READ LOOK-UP TABLE ENTRY
• ACCESS LOCATION PARAMETER PUSHED INTO
The data pointer can be loaded with a 16-bit value using
the instruction MOV DPTR. #dataI6. The data used is
stored in the second and third instruction bytes. highorder byte first. The data pointer is incremented by INC
DPTR. A 16-bit increment is performed; an overflow
from the low byte will carry into the high-order byte.
Neither instruction affects any flags.
The MOVC (Move Constant) instructions (MOVC
A.@A+DPTR and MOVC A.@A+PC) read into the
accumulator bytes of data from the program memory
logical address space. Both use a form of indexed
addressing: the former adds the unsigned eight-bit
accumulator contents with the sixteen-bit data pointer
register. and uses the resulting sum as the address from
which the byte is fetched. A sixteen-bit addition is
performed; a carry-out from the low-order eight bit, may
propagate through higher-order bits. but the contents of
the DPTR are not altered. The latter form uses the incremented program counter as the "base" value instead of
the DPTR (figure 17). Again. neither version affects the
flags.
• READ INPUT PARAMETER AND SAVE
• ACCUMULATOR
,MASK ALL nUT LOW-ORDER
TWO BITS
• ALLOW FOR OFFSET FROM Move TO TABLE
• PASS BACK TRANSLATED VALUE
MOVC A @ A + PC
(LOCAL TABLE
LOOK-UP)
a)
AND RESTORE
· Ace
RET
5TPTBL
DB
D.
D.
D.
• RETURN TO BACJI,GROUND PROGRAM
0110111113
,POSITION 0
010111l1B
10011111B
lO1011l1B
,POSITION 1
• POSITION 2
,POSITION 3
b)
A
Ace
NXTPOS
PI
PC
~ACC
MOVC A @l A+ DPTR
(GLOBAL TABLE
LOOK-UP)
16-81T
I
c)
JMP @ A+ OPTR
(GLOBAL INDIRECT
JUMP)
~~~~~I~~RESS
DPTR
~ACC
,-___'_6-_B'..!,T.J1
Example 20-Sending and Receiving Data Parameters
Via the Stack
CALL
PDP
I
' -_ _ _'6_-_"_,_T..1
The background program may reach this subroutine with
several different calling sequences. all of which PUSH a
value before calling the routine and POP the result after.
A motor on Port I may be initialized by placing the
desired position (zero) on the stack before calling the
subroutine and outputing the results directly to a port
afterwards.
PUSH
16-BIT
16-81T
~~~~~~~RESS
1 OPTR
~ACC
' -_ _ _'_6-_6'_T..) LOADED INTO PC
Figure 17. Operation of MOVC instructions
AFN-01S02A-2S
2-23
AP-69
Each can be part of a three step sequence to access lookup tables in ROM. To use the DPTR-relative version .
. load the Data Pointer with the starting address ofa lookup table; load the accumulator with (or compute) the
index of the entry desired; and execute MOVC
A.@A+DPTR. Unlike the similar MOVP3 instructions
in the 8048. the table may be located anywhere in
program memory. The data pointer may be loaded with a
constant for short tables. Or to allow more complicated
data structures. or tables with more than 256 entries. the
values for DPH and DPL may be computed or modified
with the standard arithmetic instruction set.
The PC-relative version has the advantage of not
affecting the data pointer. Again. a look-up sequence
takes three steps: load the accumulator with the index;
compensate for the offset from the look-up instruction to
the start of the table by adding the number of bytes
separating them to the accumulator: then execute the
MOVC A.@A+PC instruction.
Let's look at a non-trivial situation where this instruction
would be used. Some applications store large multidimensional look-up tables of dot matrix patterns. nonlinear calibration parameters. and so on in a linear (onedimensionali) vector in program memory. To retrieve
data from the tables. variables representing matrix
indices must be converted to the desired entry's memory
address. For a matrix of dimensions (MDIMEN x
NDIMEN) starting at address BASE and respective
indices INDEX I and INDEXJ. the address of clement
(INDEX!. INDEXJ) is determined by the formula.
Entry Address = BASE + (NDIMEN x INDEXI) +
INDEXJ
The code shown below can access any array with less than
255 entries (i.e .. an IIx21 array with 231 elements). The
table entries are defined using the Data Byte ("DB")
dire~tive. and will be contained in the assembly object
code as part of the accessing subroutine itself.
There are several different means for hranching to
sections of code determined or selected at run time. (The
single destination addresses incorporated into
conditional and unconditional jumps, are. of course.
'determined at assembly time). Each has ad\'antages for
different applications.
The most common is an N-way conditional jump based
on some variable. with all of the potential destinations
known at assembly time. One of a numb~r of small
routines is selected according to ,the \'alue of an index
variable determined while the program is running. The
most efficient way to solve this problem is \\ ith the
MOVe and an indirect jump instruction. ming a short
table of one byte offset values in ROM to indicate the
relative starting addresses of the several routines.
.IMP @A+DPTR is an instruction which performs an
indirect jump to an address determined during program
execution. The instruction adds the eight-bit unsigned
accumulator contents with the contents of the sixteen-hit
data pointer. just like MOVC A.@A+DPTR. The
resulting sum is loaded into the program counter and is
used as the address for subsequent instruction fetches.
Again. a sixteen-bit addition is performed; a carry out
from the low-order eight bits may propagate through the
higher-order bits. In this case. neither the accumulator
contents nor the data pointer is altered.
The example subroutine below reads a byte of RA Minto
the accumulator from one of four alternate addre"
spaces. as selected by the contents of the \ariable
MEMSEI.. The address of the byte to he read is
determined by the contents of RO (and optionally R I). It
might find use in a printiniperminal application. where
four different model printers all use the same ROM code
but use diffcrent types and SiICS' of buffer memory for
different speeds and options.
Example 23 -- N-Way Branch and Computed Jump
Instructions via JMP @ ADPTR
Example 22-Use of MPY and Data Pointer Instructions to Access Entries from a Multidimensional Look-Up Table in ROM
,MATRXI LOAD CONSTANT READ FROM TWO DIMENSIONAL LOOK-UP
TABLE IN PROGRAM MEMORY INTO ACCUMULATOR
USING LOCAL. TADLE LOOK-UP INSTRUCl ION. 'Move
A, (!A+P(
THE TOTAL NUMBER OF TABLE ENTRIES IS ASSUMED TO
BE SMALL. 1 E
LESS THAN ABOUT 250 ENTRIeS)
TABLE USED IN THIS EXAMPLE IS ( 11 )( 21 )
DESIRED ENTRY ADDRESS IS GIVEN BY THE FORMULA,
r (BASE ADDRESS) + (21 )( INDEXI) + (INDEXJl ]
INDEXI
INDEXJ
I'IATRXI
EOU
EOU
Rb
23H
MOV
MOV
MUl.
ADD
A. INDEX I
*21
INC
Eau
R3
JUMP _4
MOV
HOV
MOVC
A, MEMSEL
OPTR, *"MPTBL
A, \tA"'OPTR
JHP
JMPTaL
DB
DB
DB
DB
@A ... OPTR
MEMSPO-JMPTBL
MEMSPI-JMPl"BL
MEMSP2-JMPTBL
MEMSP3-JMPTaL
MEMSPO
MOV
A. GlRD
• READ FROM
MEMSPI
MOVX
A, \tRO
,READ FROM 256 BYlES OF EXl"ERNAL RAM
MEMSP2
RET
MOV
DPL. RO
Mav DPH, RI
,FIRST COORDINATE OF ENTRY (0-10)
,SECOND COORDINATE OF ENTRY
INTERNAL RAM
RET
10-20)
n.
AD
A.INDEXJ
ALLOW FOR INSTRUCTION B'fTE BETWEEN "MOVC"
ENTRY (0. OJ
Move
MEMSEL
MEI"ISP3
A
A. (fA+PC
MOVX
RET
A. eOPTR ,READ FROM b4K BYTES OF EXTERNAL RAM
•
MOV
ANL
ANL
ORL
I10VX
P1.*llI11000n
A. RI
A. *07H
PI. A
A,@RO
• READ FROM 41'. BYTES OF EXl"ERNAL RAM
RET
RET
BASEl
DB
DB
• (ef1tr~ 0.0)
, (entry 0,1)
DB
DB
, (entr~ 0,20)
• (entry 1.0)
22
'
DB
DB
231
(f'f1tr~
1.20)
, (entry 10,20)
Note that this approach is suitable whenever the sile of
jump table plus the length of the alternate routines is Ie"
than 256 bytes. The jump table and routines may he
located anywhere in program memory. independent of
256-byte program memory pages.
AFN-Ol ~02A-26
2-24
AP-69
For applications where up to 12K destinations must be
,elected. all of which reside in the same 2K page of
program memory which ma5' be reached by the two-byte
ab,olute jump instructions. the following techni4ue may
be u,ed. In the above mentioned printing terminal
example. this se4uence could "parse" 12K different codes
for ASCII character, arriving via the X()SI serial port.
Example 24·- N- Way Branch with 128 Optional
Destinations
OPTION
EOU
MDv
R3
A. OPTION
Rl
INSTilL
,MULTIPLY DV 2 FOR
MDV
JMP
DPTR •• INsrDL
lM+DPTR
A,JMP
PROCOQ
rRQCOl
A.)Mf'
~
!lyrE .JlJMP TI\IiI.E
,FIRST ENrR"I' IN ,JUMP TAlliE
,JUMP INTO ,JUMP TABLE.
• 128 CONSECUT I VE
,AJMP INSTRUCTIONS
A,JMP
A,JMP
A,JMP
PROC7E
PRQC7F
The de,tination, in the jump table (PROCOOPROC7F) are not all necc"arily uni4ue routine,. A large
number of 'pecial control codes could each be processed
with their own uni4uc routine. with the remaining
printing characters all causing a branch to a common
routine for entering the character into the output 4ueue.
In those rare situations where even 12K options arc
insufficient. or where the de,tination routines may cross a
2K page boundary. the above approach may be modified
slightly as shown below.
Example 25-256-Way Branch Using Address LookUp Tables
RTEMP
EGU
JMP25b
MDV
MDv
DPTR •• AORTDl
A, OPTION
elR
Rle
, FIRST ENTRY IN TABLE OF ADDRESSES
,MULTIPLY BY 2
rOR 2
INC
MDv
Move
DPH
RTEMP, A
A.@'A+DPTR
leCH.
INC
MOVC
A. 'HEMP
OW
PRocoa
PRDCOl
• SAVE Ace FOR HIGH I)YTE READ
• READ LOW In'TE FROM JUMP TADLE
A
A, @A+DPTR
, GET LOW-ORDER BYTE FROM TABLF"
PUSH
ACC
A, RTEMP
MDV
A, eA+[JPTR
Move
• GET HIGH--ORDER B't'TE FoROM TABLE
PUSH
ACC
THE TWO ACC PUSHES HAVE PRODUCED
A "RETURN ADDRESS" ON THE STACK WHICH CORRE5PO"lDS
TO THE DESIRED STARTING ADDRESS
IT MAY BE REACHED BY POPPING THE STACK
INTO THE PC
ADRTBL
DW
,UP TO 256 CONSECUTIVE DATA
,WORDS INDICATING STARTING ADDRESSES
PRDCFF
DUMNY CODE ADDRESS DEFINITIONS NEEDED BY ABOVE
TWO EXAMPLES
PRDcaa
PRDcal
PRDca2
PRDC7E:
PRDC7F
PROCFF"
Direct Bit Addressing
A number of instructIOns operate on Boolean (one-bit)
variables. using a direct bit addressing mode comparable
to direct byte addressing. An additional byte appended to
the opeode specifics the Boolean variable. I 0 pin. or
control bit used. The state of any of these bits may be
tested for "true" or "false" with the conditional branch
instructions .IB (.lump on Bit) and .INB (Jump on Not
Bit). The JBC (Jump on Bit and Clear) instruction
combines a test-for-true with an unconditional clear.
As in direct byte addressing. bit 7 of the address byte
switches between two physical address spaces. Values
between 0 and 127 (00H-7FH) define bits in internal
RA M locations 20H to 2FH (Figure IXa); address bytes
between 128 and 255 (XOH-OFFH) define bits in the 2 x
"special-function" register address space (Figure I Xb). If
no 2 x "special-function" register corresponds to the
direct bit address used the result of the instruction is
undefined.
Bits so addressed have many wondrous properties. They
may be set. cleared. or complemented with the two byte
instructions SETB. CLR. or CPI.. Bits may be moved to
and from the carry flag with MOV. The logical ANL and
ORL functions may be performed between the carry and
either the addressed bit or its complement.
DYTE ,JUMP TAULE
LDW128
LQW128
Prior to the introduction of the MCS-51'· family. nice
number-crunchers made bad bit-bangers and vice versa.
The X051 is the industry's first single-chip microcomputer designed to crunch and bang. (In some circles.
the latter techni4ue is also referred to a, ··bit.-twiddling".
Either is correct.)
NDP
NOP
NOP
NOP
NOP
NOP
4. BOOLEAN PROCESSING INSTRUCTIONS
The commonly accepted terms for tash at either end of
the computational vs. control application spectrum are.
respectively. "number-crunching" and "bit-banging".
Bit Manipulation Instructions -
MOV
The "MOV" mnemonic can be used to load an
addressable bit into the carry flag ("MOV C. bi!"') or to
copy the state of the carry to ,uch a bit ("MOV bit. C').
These instructions are often used for implementing serial
110 algorithms via software or to adapt the standard I 0
port structure.
It is sometimes desirable to ··re .. arrange·· the order of I 0
pins because of considerations in laying out printed
circuit boards. When interfacing the X051 to an
immediately adjacent device with "weighted:' input pins.
such as keyboard column decoder. the corresponding
pins are'lik~ly to be ,not aligned (Figure 19).
There is a trade-off in "scrambling" the interconnections
with either interwoven circuit board traces or through
software. This is extremely cumbersome (if not
impossible) to do with byte-oriented computer
architectures. The 8051"s unique set of Boolean
instructions makes it simple to move indiVidual bits
between arbitrary locations.
AFN·Q1502A-27
2-25
infef
AP-69
RAM
BYTE
7FH
-....
b.) Hardware Register Bit Addresses .
••) RAM BII Addresses.
Direct
(MSB)
(LSB)
1
1
E71E61ESIE41ul
E21E11EO
ACC
OOOH
D71
D61
Dsl
D41
D21D11DO
PSW
SO
DOSH
-
I
-
I
-
I
BC I DB
I BA
I
B9
I
BB
IP
OBOH
B7
I
B6
I
BS
I
8.
I
83
I
B2
I
81
I
80
P3
DASH
AF
I- I- I
AC
I
AB
I
AA
I J
AB
IE
I
AD
P2
7E
7D
7C
7B
7A
79
7B
77
76
75
74
73
72
71
70
2DH
6F
6E
6C
6B
6A
69
6B
67
..
6D
2CH
63
62
61
50
58
28H
SF
SE
SD
SC
58
SA
59
2AH
57
56
55
54
53
52
51
29H
4F
4E
4D
4C
4B
4A
49
43
42
41
40
3E
3D
3C
3B
3A
3.
38
47
27H
3F
..
4S
.
..
26H
37
36
35
34
33
32
31
30
2SH
2F
2E
2D
2C
2B
2A
29
2.
FO
D31
A9
2.H
27
26
25
24
23
22
21
20
A7
I
AS
I
AS
I
A4
I
A3
I
A2
I
1F
1E
1D
1C
1B
1A
19
,.
OAOH
23H
9BH
.F
I
9E
I
9D
I
9C
I
••
I
.A
I •• 1 ••
90H
. 7 1 " 1 .5
1 " 1 .3
1 .2
1"1
BBH
BF
I
BE
I
BD
I BC
I
BB
I
BA
I
B.
I
BOH
B7
I
..
I
BS
I
I
83
I
B2
I
B1
I
22H
17
16
15
14
13
12
11
10
21H
OF
DE
OD
DC
DB
OA
09
O.
20H
07
06
OS
04
03
02
01
50
1FH
Register
Symbol
OFFH
OEOH
7F
.
(LSB)
F7
2FH
65
Hardware
BII Addresses
(MSB)
OfOH
2EH
2BH
Byle
A1
Bank 3
1BH
17H
90
..
SCON
P1
TeON
Bank 2
10H
B.
BD
PO
DFH
Bank 1
DSH
D7H
Bank 0
DOH
Figure 18. Bit Address Maps
Example 26-Re-ordering I/O Port Configuration
ALE
PSEN
P2.7
P2.6
8351
8751
J
J
J
-,
OUT _PI
[
(LSB)
-'
.'-
--,
r
-'
'-
'-
-'
A2
P2.3
--,
r
-'
'-
A3
P2.2
-'
P2.1
J
J
P2.5
P2.4
-'
'-
~
P2.D
Figure
AD
19. "Mismatch"
Decoder
(MSB)
'-
RRC
MOV
RRC
MOV
RRC
MOV
RRC
MOV
RRC
MOV
A
P2 6. C
A
,MOVE ORIGINAL Ace 0 INTO CV
,STORE CARRY TO PIN P26
• MOVE ORIGINAL Ace 1 INTO CY
p;, :i. C
• STORE CARRY TO PIN P25
A
,MOVE ORIGINAL Ace 2 INTO CY
• STORE CARRY TO PIN P24
,MOVE ORIGINAL Ace 3 INT~ CY
PO! 4. C
A
P2 3. C
A
• STORE CARRY TO PIN P23
, MOVE ORIGINAL ACC 4 INTO CY
P2 2. C
•
5TO~E
CAF<~Y
TO PIN P22
A1
DECODER
Solving Combinatorial Logic Equations - ANL, ORL
A4
[
[
Between
110
port
and
Virtually all hardware designers are familiar with the
problem of solving complex functions using
combinatorial logic. The (.echnologies involved may vary
greatly. from IT. dtiple contact relay logic. \acuum tubes.
TTL. or CMOS fo more esoteric approache, likc fluidic,.
but in each case the goal is (he same: a Boolean
(true false) function is computed on a number of
Boolean \ ariables.
AFN-01502A-28
2-26
inter
AP-69
b.} Relay logic.
a.) TTL
CR.
Q ~
(U • (V + W) + eX • Y) + Z
z
Figure 20. Implementations of Boolean functions
INPUT. OUTPUT. l.OAD, STORE. etc .. instead of the
uni\er,al MOV.
Figure 20 shows the logic diagram for an arbitrary
function of six variables named U through Z using
,tandard logic and relay logic symbols. Each is a solution
of the eljuation.
Q = (U • (V + W» + (X.
Y) + Z
(While this eljuation could be reduced using Karnaugh
Map' or algebraic techniljues. that is not the purpose of
this example. Even a minor change to the function
cljuation would reljuire re-reducing from scratch.)
Mo,t digital computers can solve eljuations of this type
with ,tandard word-wide logical in,tructions and
conditional jumps. Still. such software solutions seem
,omewhat sloppy because of the many paths through the
program thc computation can take.
A"umc U and V arc input pins being read by different
input ports. Wand X are stutus bit, for two peripheral
controllers (read as I 0 ports). and Y and Z are software
Ilag' set or cleared earlier in the program. The end re,ull
must bc written to an output pin on some third port.
For the sake of comparison we will implement this
function with ,oftware drawn from thrce proper suhsets
of the MCS-SI ,. instruction set. The first two
implcmentations follow the flow chart shown in Figure
21. Program flow would embark on a route down a testand-branch tree and leaves either the "Truc" or "Not
rruc" cxit ASAP. These exits then write the output port
"ith the data previously written to the,ame port with the
re,ull bit respectivcly one or lero.
In the first case. we assume there are no instructions for
addrc"ing individual bits other than special flags like the
carry. Thi, b typical of many older microproce!>Sors and
mainframe computers designed for number-crunching.
MCS-SI'· mnemonics arc u,ed hcre. though for most
othcr machines thc issue would be even further clouded
h~ thcir usc of operation-specific mnemonic, like
(CONTINUE)
Figure 21. Flow chart for tree-branching logic
implementation
2-27
inter
AP-69
Example 27 - Software Solution to Logic Function of
'Figure 20, Using only Byte-Wide Logical
Instructions
• BFUNCI SOL ....e Po RANDOM LOGIC FUNCTION OF b
V~RIABLES BY L.OADING AND MASKING THE APPROPRIATE
BJTS IN THE ACCUMULATOR. THEN EXeCUTING CONDITIONAL
..rUMPS BASED ON ZERO CONDITION
(APPROACH useD BY BYTE-ORIENTED ARCHITECTURES)
BYTE AND MASK VALUES CORRESPOND TO RESPECTIVE
BYTE ADDRESS AND BIT POSITION
OUTBUF
EOU
22H
TESTV
"OV
ANL
JNl
"OV
ANL
JZ
"OV
ANL
IN'
MOV
ANL
JZ
HOV
ANL
J'
A. P2
A ••00000100B
TESTU
Po. TCON
TESTU
• OUTPUT PIN STATE MAP
These instructions may be "strung together" to simulate a
multiple input logic gate. When finished, the carry flag
contains the result, which may be moved directly to the
destination or output pin. No flow chart is needed - it is
simple to code directly from the logic diagrams in Figure
20.
Example 29-Software Solution to Logic Function of
Figure 20, Using the MCS-51 (TM)
Unique Logical Instructions on Boolean
Variables
A•• OOloaaoon
.IJFUNC3 SOLI,IE A RANDOM LOGIC FUNCTION OF 6
VARIAIKES USINQ STRAIGHT-LINE LOGICAL INSTRUCTIONS
ON MCS-51 BOOLEAN VARIABLES
TEST](
A. PI
A.4tOOOOODIOD
sera
MOV
ORL
ANL
HOV
MOV
ANL
ORL
ORL
"OV
A. TCON
A ••000010000
TESTZ
A.20H
A ••00000001B
SETO
.",ov
A.2IH
I'll, .000000100
SETG
ANL
JZ
eLRO
aUTa
Fa, C
c. x
C,IY
C, FO
C,/Z
,OUTPUT OF OR GATE
• OUTPUT OF TOP AND GATE
,SAVE INTERMEDIATE STATE
,OUTPUT OF BOTTOM AND GATE
, INCL.UDE VAL.UE SAVED ABOVE
,INCLUDE LAST INPUT VARIABLE
,OUTPUT COMPUTED RESULT
A. CUTBUF
A •• lll10111D
Duro
SEra
c. v
c.u
"OV
ORL
HOV
"OV
Simplicity itself. Fast, flexible, reliable, easy to design,
and easy to debug.
'A.OUTBUF
A •• 00001000B
OUTBUF, A
P;3. Po
The Boolean features are useful and unique enough to
warrant a complete Application Note of their own .
Additional uses and ideas are presented in Application
Note AP-70, Using the Intel" MCS~51" Boolean
Processing Capabilities, publication number 121519.
. Cumbersome, to say the least, and error prone. It would
be hard to prove the above example worked in all cases
without an exhaustive test.
Each move/mask/conditional jump instruction
sequence may be replaced by a single bit-test instruction
thanks to direct bit addressing. But the algorithm would
be equally convoluted.
5. ON-CHIP PERIPHERAL FUNCTION
OPERATION AND INTERFACING
1/0 Ports
Example 28 - Software Solution to Logic Function of
Figure 20, Using only Bit-Test
Instructions
The I/O port versatility results from the "quasibidirectional" output structure depicted in Figure 22.
(This is effectively the structure of ports I, 2, and 3 for
normal I/O operations. On port 0 resistor R2 is disabled
except during multiplexed bus operations, providing
• BFUNC2 SOLVE A RANDOM LOGIC FUNCTION OF £,
VARIABLES BY DIRECTLY POLLINO EACH BIT
(APPROACH USINC MCS-51 UNIQUE BIT-TEST
INSTRUCTION CAPABILITY)
SYMBOLS USED IN LOGIC DIAGRAM ASSIGNED TO
CORRESPONDING 80:51 BIT ADDRESSES
BIT
PI 1
BIT
BIT
P2 2
TFO
BIT
BIT
BIT
lEI
20H 0
21H 1
P3 3
BIT
TEST _V
TEST U
TEST=:X
TEST_Z
CLR_O
SET _0
NXTTST
..18
JNB
..IS
..INB
JNB
,JNB
CLR
V. TEST_U
w. TEST_J(
U. SET_O
TEST_Z
Y.SET_Q
Z. SET_O
J"P
SETB
NXTlST
READ/MODIFY I
WRITE
x.
INTERNAL
BUS
G
o
, (CONTINUATION OF PROGRAM)
A more elegant and efficient 8051 implementation uses
the Boolean ANL and ORL functions to generate the
output function using straight-line code. These
instructions perform the corresponding logical
operations between the carry flag ("Boolean
Accumulator") and the addressed bit, leaving the result in
the carry. Alternate forms of each instruction (specified
in the assembly language by placing a slash before the bit
name) use the complement of the bit's state as the input
operand.
WRITE
PULSE
BUS
CYCLE
TIMING
REAO
Figure 22, Pseudo-bidirectional 1/0 port circuitry
AFN-01502A-30
2-28
AP-69
e"entially open-collector output>. ror full electrical
characteri,tic, ,ee the lber', Manual.)
Example 30 -- Mixing Parallel Output. Input. and
Control Strobes on Port 2
'rm24~1
An output latch bit a>sociated with each pin is updated by
direct addre\Sing instruction, when that port i, the
de,tination. The latch ,tate is buffcred to the oUbide
world by R I and 0 I. which may drive a ,tandard TTL
input. (in TTL term,. 01 and R I resemblc an opcncollector output with a pull-up re,istor to Vcc.)
"
J
I
I
,,~
.f·Ar~Df ~
1t1l01001""","
I',' A
. OUTPuT INSTfllJCl HITI ell!.!!
..
~ AI L INC f:Dr.E f1F.
PIH1(,
1'.:!.4IOOOClII!IB
.SET FO,", IN!,1,"
!','
Ijlll
u"r.\
.t'
~t_AI'
INI-IJ!
Il[T<}i-JN I-I_U" HI
I-It!
.f '
ror-,>nr;"
.;11\1'
Serial Port and Timer applications
R2 and 02 represent an "activc pull-up" deviec enablcd
momentarily when a 0 previously output changes to a I.
Thi, "jerb"thc output pin to a I level morc 4uickly than
thc paS\i,'c pull-up. improving ri,c-time significantly if
thc pin i, driving a capacitive load. Note thattne active
pull-up i, only activated on (}-to-I transitions at the
output latch (unlike thc X04X. in which 02 i, acti,ated
whcncver a I i, writtcn out).
Opcration, u,ing an input port or pin a, the sourcc
operand usc the logic level of the pin itself. rather than the
output latch contents. This level is affected by both the
microcomputer it,elf and whatever device the pin is
connected to externallv. The value read is cssentiallv the
"OR-tied" function of'O I and the cxternal device. if the
extcrnal device is high-impedencc. such as a logic gate
input or a 1hree state output in thc third state. then
reading a pin will rencctthe logic level previously output.
To u,e a pin for input. the corresponding output latch
mu,t be ,ct. The external device may then drive the pin
with cithcr a high or low logic signal. Thus the same port
may be u,cd a, both input and output by writing ones to
all pin,,,used as input' on output operations. and ignoring
all pin, u,ed a, output on an input operation.
IN~'I'l
r,,\T.\ ~1"'f1 t,~J 8 •.;
COM,Eer; oj TO f','.l-P r'"
Po.!" • I' '·1 MIMIC CS
P;' I -p -~ lJ"::E"D AS iNP'JTS
To: 'H ~£AD /rJ l,,".
Configuring thc 8051's Scrial Port for a given data ratc
and prolocol re4uirc> cs>cntially thrce short ,cclions of
software. On power-up or hardware resel the serial port
and timer control word, mu,t bc initiali/cd to thc
appropriate value,. Additional software i, abo needed in
the transmit routine to load thc ,erial port data rcgister
and in the receive roulinc to unload the data a, it arrives.
This i, be,t illu,trated through an arbitrary example.
A"umc the 80S1 will communicate "ith a CRT
operating at 2400 baud (bits per second)_ Each character
b transmitted as ,even data bits. odd parity. and one stop
bit. This re,ult, in a character rale of 2400 10=240
characters per second.
For the sake of clarity. the transmit and rcceive
subroutines arc driven by simple-minded soflware status
polling code ralher than interrupts. (It might heir 10 refer
back to Figures 7-9 showing the control word formats.)
The serial port must be iniliali7cd to 8-bit UART mode
(MO. M 1=01). enabled to receivc all messages (M2=O.
REN=I). The nag indicating that the transmit register i,
free for more data will be artificially ,et in order tolctthe
output software know the output register is av'ailable.
This can all be set up with one instruction. .
In one operand instructions (INC, DEC, DJNZ and the
Boolean CPL) the output latch rather than thc input pin
Ic\cl i, u,ed a, the source data. Similarly. two operand
in,tructions using the port as both one source and the
dc,tination (AN\.. OR\.. XRL) u,c the output latches.
Thi, cn,urc, that latch bits corresponding to pins used a,
inputs will not bc cleared in the proces> of executing these
Example 31 -- Serial Port Mode and Control Bits
,SPINlT INITIALIZE SERIAL PORT
FOR B-B r T UART MO[lF
r.
seT TRANSMIT READY FLAG
SCON. "010100103
in~tructi{)ns.
8351
8751
The Boolean operation JBC tests the output latch bit.
rathcr than the input pin. in deciding whether or not to
jump. Like the byte-wise logical operations. Boolean
operations which modify individual pins of a port leave
the other bits of the output latch unchanged.
8243
P'
P2.7
P2.&
P2.5
P2.4
P2.3
P2.2
P2.1
A good example of how these modes may play together
may be taken from the hosl-processor interface expected
by an X243 I 0 expander. Even though the 8051 does not
include X048-type instructions for interfacing with an
8243. the parts can be interconnected (Figure 23) and the
rrotocol may be emulatcd with simplc software.
P2.0
} INPUTS
CS
PS
PROG
P23
P'
P22
P21
P2.
P7
F.igure 23. Connecting an 8051 with an 8243
I/O Expander
AFN-01502A-31
2-29
inter
AP-69
Timer I will be used in auto-reload mode as a data rate
generator. To achieve a data rate of 2400 baud. the timer
must divide the I M Hz internal clock by 32 x (desired
data rate):
I x H)"
(32) (2400)
which equals 13.02 rounded down to 13 instruction
cycles. The timer must reload the value -13. or OF3H.
(ASMSI will accept both the signed decimal or hexadecimal representations.)
Example 32 -Initializing Timer Mode and Control BiH
• TllNIT INITIALIZE TII'tER 1 FOR
AUTO-RELOAD AT 32*2400 HZ
eTa USED AS GATED lib-BIT COUNTER)
TIINIT
MOY
"OV
SEn
TeoN. _110100108
THI. "-13
TRI
A ~imple subroutine to transmit the character passed to it
in the accumulator must first compute the parity bit.
insert it into the data byte. wait until the transmitter is
available. output the character. and return. This is nearly
as easy said as done.
Example 33 -Code for UART Output. Adding Parity.
Transmitter Loading
,SP OUT ADD 000 PARITY TO Ace AND
TRANSMIT WHEN SER I AL PORT READY
SP_OUT
MOV
ePl
MOV
JNB
elR
MOV
RET
e. P
e
Ace 7, c
TI ••
11
SBUF. A
A simple minded routine to wait until a character is
received. set the carry flag if there is an odd-parity error.
and return the masked seven-bit code in the accumulator
is equally short.
Example 34-Code for UART Reception and Parity
Verification
.SP_IN
INPUT NEXT CHARACTER FROM SERIAL PORT
SET CARRY IFF ODD-PARITY ERROR
5P _IN
JNB
ClR
MOV
MOV
CPl
ANl
RET
RI. f;
Rl
A.SBUF
C. P
C
A. "7FH
6. SUMMARY
This Application Note has described, the architecture.
instruction set. and on-chip peripheral features of the
first three members of the MCS-SI T• microcomputer
family. The examples used throughout were admittedly
(and necessarily) very simple. Additional examples and
techniques may be found in the MCS-SI ,. User's Manual
and other application notes written for the MCS-48'· and
MCS-SI T• families.
Since its introduction in 1977. the MCS-48'· family has
become the industry standard single-chip
microcomputer. The MCS-.5IT. architecture expands the
addressing capabilities and instruction set of its
predecessor while ensuring flexibility for the future. and
maintaining basic software compatability with the past.
Designers already familiar with the 8048 or 8049 will be
able to take with them the education and experience
gained from past designs as ever-increasing system
performance demands force them to move on to state-of-"
the-art products. Newcomers will find the power and
regularity of the 80S I instruction set an advantage in
streamlining both the learning and design processes.
Microcomputer system designers will appreciate the 80S I
as basically a single-chip solution to many problems
which previouslv required board-level computers.
Designers of real:time control systems will find the high
execution speed. on-chip peripherals. and interrupt
capabilities vital in meeting the timing constraints of
products previously requiring discrete logic designs. And
designers of industrial controllers will be able to convert
ladder diagrams directly from testcd-and-true TTL or
relay-logic designs to microcomputer'software. thanks to
the unique Boolean processing capabilities.
11 has not been the intent of this note to gloss over the
difficulty of designing microcomputer-based systems. To
be sure. the hardware and software design aspects of any
ncw computer system are nontrivial tasks. Howevcr. the
system speed" and level of integration of the MCS-SI'·
microcomputers. the power and flexibility of the
instruction set. and the sophisticated assembler and other
support products combine to give both the hardware and
software designer as much of a head start on the problem
as possible.
AFN-01502A-32
2-30
APPLICATION
NOTE
AP-70
April 19BO
Using the Intel MCS®-51 Boolean
Processing Capabilities
JOHN WHARTON
MICROCONTROLLER APPLICATIONS
@ Intel Corporation, 1988
2-31
Order Number: 203830-001
intJ
AP-70
1.0 INTRODUCTION
The Intel microcontroller family now has three new
members: the Intel® 8031, 8051, and 8751 single-chip
microcomputers. These devices, shown in Figure 1, will
allow whole new classes of products to benefit from
recent advances in Integrated Electronics. Thanks to
Intel's new HMOS technology, they provide larger program and data memory spaces, more flexible I/O and
peripheral capabilities, greater speed, and lower system
cost than any previous-generation single:chip microcomputer.
- yee
Pl.0 Pl.l-
- PO.O
Pl.2-
- PO.l
Pl.3 -
- PO.2
P1.4 -
- PO.3
Pl.S-
- PO.4
Pl.6-
- PO.S
Pl.7 -
- PO.6
- PO.7
RST P3.0lRXD -
- YPP/EA
P3.lITXD -
- PI'!O'G/ALE
P3.21iNTo -
- PSEN
P3.3/1NTI -
- P2.7
P3.41TO -
- P2.6
P3.S/TI -
- P2.S
P3.6/WR -
- P2.4
P3.7/AD -
- P2.3
XTAL2 -
- P2.2
XTALl -
- P2.1
YSS -
- P2.0
203830-1
Figure 1.8051 Family Pinout Diagram
Table 1 'summarizes the quantitative differences between the members of the MCS®-48 and 8051 families.
The 8751 contains 4K bytes of EPROM program memory fabricated on-chip, while the 8051 replaces the
EPROM with 4K bytes of lower-cost maskprogrammed ROM. The 8031 has no program memory
on-chip; instead, it accesses up to 64K bytes of program
memory' from external memory. Otherwise, the three
new family members are identical. Throughout this
Note, the term "8051" will represent all members of the
8051 Family, unless specifically statecI otherwise.
The CPU iIi each microcomputer is one of the industry's fastest and most efficient for numerical calculations on byte operands. But controllers often deal with
bits, not bytes: in the real world, switch contacts can
only be open or closed, indicators should be either lit or
dark, motors are either turned on or off, and so forth.
For such control situations the most significant aspect
of the MCS®-51 architecture is its complete hardware
support for one-bit, or Boolean variables (named in
honor of Mathematician George Boole) as a separate
data type.
The 11051 incorporates a number of special features
which support the direct manipulation and testing of
individual bits and allow the use of single-bit variables
in performing logical operations. Taken together, these
features are referred to as the MCS-51 Boolean Processor. While the bit-processing capabilities alone would be
adequate to solve many control applications, their true
power comes when they are used in conjunction with
the microcomputer's byte-processing and numerical capabilities.
Many concepts embodied by the Boolean Processor will
certainly be new even to experienced microcomputer
system designers. The purpose of this Application Note
is to explain these concepts and show how they are
used.
For detailed information on these parts refer to the
Intel Microcontroller Handbook, order number
210918. The instruction set, assembly language, and use
'of the 8051 assembler (ASM51) are further described in
the MCS®-Sl Macro Assembler User's Guide for DOS
Systems, order number 122753.
Table 1. Features of Intel's Single-Chip Microcomputers
EPROM
Program
Memory
ROM
Program
Memory
External
Program
Memory
Program
Memory
(InttMax)
Data
Memory
(Bytes)
Instr.
Cycle
Time
Inputt
Output
Pins
Interrupt
Sources
Reg.
Banks
8748
8048
8049
8051
8035
8039
8031
1K4K
2K4K
4K64K
64
128
128
2.5/Jos
1.36/Jos
1.0/Jos
27
27
32
2
2
5
2
2
4
8751
2-32
-
inter
AP-70
plex (albeit slower) ones, which in turn link together
eventually solving the problem at hand. A four-bit CPU
executing multiple precision subroutines can, for example, perform 64-bit addition and subtraction. The subroutines could in turn be building blocks for floatingpoint multiplication and division routines. Eventually,
the four-bit CPU can simulate a far more complex "virtual" machine.
2.0 BOOLEAN PROCESSOR
OPERATION
The Boolean Processing capabilities of the 8051 are
based on concepts which have been around for some
time. Digital computer systems of widely varying designs all have four functional elements in common (Figure 2):
• a central processor (CPU) with the control, timing,
and logic circuits needed to execute stored instructions:
• a memory to store the sequence of instructions making up a program or algorithm:
In fact, any digital computer with the above four functional elements can (given time) complete any algorithm (though the proverbial room full of chimpanzees
at word processors might first re-create Shakespeare's
classics and this Application Note)! This fact otTers little consolation to product designers who want programs to run as quickly as possible. By definition, a
real-time control algorithm must proceed quickly
enough to meet the preordained" speed constraints of
other equipment.
• data memory to store variables used by the program:
and
• some means of communicating with the outside
world.
One of the factors determining how long it will take a
microcomputer to complete a given chore is the number of instructions it must execute. What makes a given
computer architecture particularly well- or poorly-suited for a class of problems is how well its instruction set
matches the tasks to be performed. The better the
"primitive" operations correspond to the steps taken by
the control algorithm, the lower the number of instructions needed, and the quicker the program will run. All
else being equal, a CPU supporting 64-bit arithmetic
directly could clearly perform floating-point math faster than a machine bogged-down by multiple-precision
subroutines. In the same way, direct support for bit
manipulation naturally leads to more efficient programs handling the binary input and output conditions
inherent in digital control problems.
The CPU usually includes one or more accumulators or
special registers for computing or storing values during
program execution. The instruction set of such a
processor generally includes, at a minimum, operation
classes to perform arithmetic or logical functions on
program variables, move variables from one place to
another, cause program execution to jump or conditionally branch based on register or variable states, and
instructions to call and return from subroutines. The
program and data memory functions sometimes share a
single memory space, but this is not always the case.
When the address spaces are separated, program and
data memory need not even have the same basic word
width.
A digital computer's flexibility comes in part from
combining simple fast operations to produce more com-
TIMING &
CONTROL
PROGRAM
MEMORY
ACCUMULATOR
& REGISTERS
INPUTI
OUTPUT
PORTS
DATA
MEMORY
REAL
WORLD
CENTRAL
PROCESSING
UNIT
203830-2
Figure 2. Block Diagram for Abstract Digital Computer
2-33
AP-70
Processing Elements
The introduction stated that the 8051's bit-handling capabilities alone would be sufficient to solve some control applications. Let's see how the four basic elements
of a digital computer-a CPU with associated registers,
program memory, addressable data RAM, and I/O capability-relate to Boolean variables.
cpu. The 8051 ·CPU incorporates special logic devoted
to executing several bit-wide operations. All told, there
are 17 such instructions, all listed in Table 2. Not
shown are 94 other (mostly byte-oriented) 8051 instructions.
tions of Table 2, several sophisticated program control
features like multiple addressing modes, subroutine
nesting, and a two-level interrupt structure are useful in
structuring Boolean Processor-based programs.
Boolean instructions are one, two, or three bytes long,
depending on what function they perform. Those involving only the carry flag have either a single-byte
opcode or an opcode followed by a conditional·branch
destination byte (Figure 3a). The more general instructions add a "direct address" byte after the opcode to
specify the bit affected, yielding two or three byte encodings (Figure 3b). Though this format allows potentially 256 directly addressable bit locations, not all of
them are implemented in the 8051 family.
Program Memory. Bit-processing instructions are
fetched from the same program memory as other arithmetic and logical operations. In addition to the instruc-
opcode
Table 2. MCS-S1TM Boolean
Processing Instruction Subset
Mnemonic
Description
SETB
SETB
CLR
CLR
CPL
CPL
C
bit
C
bit
C
bit
Set Carry flag
Set direct Bit
Clear Carry flag
Clear direct bit
Complement Carry flag
Complement direct bit
MOV
MOV
C.bit
bit.C
ANL
ANL
C.bit
C.bit
ORL
ORL
C.bit
C.bit
JC
JNC
JB
JNB
JBC
rei
rei
bit.rel
bit.rel
bit.rel
2
1
1
1
1
1
1
Move direct bit to Carry flag
Move Carry flag to direct bit
2
2
2
AND direct bit to Carry flag
AND complement of direct
bit to Carry flag
OR direct bit to Carry flag
OR complement of direct
bit to Carry flag
2
2
2
2
2
2
2
2
2
2
3
3
3
2
2
2
2
2
Jump if Carry is flag is set
Jump if No Carry flag
Jump if direct Bit set
Jump if direct Bit Not set
Jump if direct Bit is set &
Clear bit
SETBC
CLRC
CPLC
Byte eyc
1
2
1
2
1
1
opcode
Idisplacement I
JC
JNC
rei
rei
a.) Carry Control and Test Instructions
opcode
SETB
CLR
CPL
ANLC,
ANLC,!
ORLC,
ORLC,!
MOVC,
MOV
Address mode abbreviations
C-Carry flag.
bit-12B software flags, any 110 pin, control or status
bit.
rei-Ali conditional jumps include an B·bit offset byte.
Range is + 127 -12B bytes relative to first byte of the
following instruction.
opcode
JB
JNB
JBC
All mnemonics copyrighted@ Intel Corporation 1980.
I I bit address
bit
bit
bit
bit
bit
bit
bit
bit
bit,C
I I bit address Idisplacement I
bit,
bit,
bit,
rei
rei
rei
b.) Bit Manipulation and Test Instructions
Figure 3. Bit Addressing Instruction Formats
2-34
AP-70
RAM
Byte
Direct
7FH~
Bit Addre.le.
B~t.
(LSB)
(MSB)
Addre•• (MSB)
(LSB)
Hardware
Regl.ter
Symbol
OFFH
-...:..
I~
2FH
7F
7E
70
7C
7B
7A
79
78
2EH
77
76
75
74
73
72
71
70
20H
6F
6E
60
6C
6B
6A
69
68
2CH
67
66
65
64
63
62
61
60
2BH
SF
5E
50
5C
5B
SA
59
58
2AH
57
56
55
54
53
52
51
50
29H
4F
4E
40
4C
4B
4A
49
48
28H
47
46
45
44
43
42
41
40
27H
3F
3E
3D
3C
3B
3A
39
38
26H
37
36
35
34
33
32
31
30
25H
2F
2E
20
2C
2B
2A
29
28
24H
27
26
25
24
23
22
21
20
23H
1F
1E
10
1C
1B
1A
19
18
22H
17
16
15
14
13
12
11
10
'21H
OF
OE
00
OC
OB
OA
09
08
20H
07
06
05
04
03
02
01
00
OFOH
F7
FO
B
OEOH
E7
EO
ACC
OOOH
07
DO
PSW
B8
IP
OB8H
OBOH
B7
BO
P3
OA8H
AF
A8
IE
OAOH
A7
AO
P2
98H
9F
98
SCON
90H
97
90
P1
88H
8F
88
TCON
80H
87
80
PO
lFH
18H
17H
10H
Bank 3
Bank 2
OFH
08H
07H
00
Bank 1
Bank 0
203830-3
a.) RAM Bit Addresses
b.) Special Function Register Bit Addresses
Figure 4. Bit Address Maps
Data Memory. The instructions in Figure 3b can operate directly upon 144 general purpose bits forming the
Boolean processor "RAM." These bits can be used as
software flags or to store program variables. Two operand instructions use the CPU's carry flag ("C") as a
special one-bit register: in a sense, the carry is a "Boolean accumulator" for logical operations and data transfers.
Input/Output. All 32 I/O pins can be addressed as individual inputs, outputs, or both, in any combination.
Any pin can be a control strobe output, status (Test)
input, or serial I/O link implemented via software. An
additional 33 individually addressable bits reconfigure,
control, and monitor the status of the CPU and alI onchip peripheral functions (timer counters, serial port
modes, interrupt logic, and so forth).
2-35
intJ
AP-70
(MSB)
I CY ! AC ! FO
(LSB)
RS1
RSO
OV
PSW.2
P
PSW.1
PSW.O
OV
Symbol Position Name and Significance
CY
PSW.7 Carry flag.
Set/ cleared by hardware or
software during certain arithmetic and logical iristructions.
AC
PSW.6 Auxiliary Carry flag.
Set/cleared by hardware during addition or subtraction instructions to indicate carry or
borrow out of bit 3.
FO
PSW.5 Flag O.
Set/cleared/tested by software as a user-defined status
flag.
RS1
PSW.4 Register bank Select control
bits.
RSO
PSW.3 1 & O. Set/cleared by software
to determine working register
bank (see Note).
Note-
Overflow flag.
Set/cleared by hardware during arithmetic instructions to
indicate overflow conditions.
(reserved)
Parity flag.
Set/cleared by hardware each
instruction cycle to indicate an
odd/even number of "one"
bits in the accumulator, i.e.,
even parity.
the contents of (RS1, RSO)
enable the working register
banks as follows:
(0,0) - Bank 0
(00H-07H)
(0,1) - Bank 1
(OBH-OFH)
(1,0) - Bank 2
(10H-17H)
(1,1)-Bank3
(1BH-1FH)
Figure 5. PSW-Program Status Word Organization
(MSB)
(LSB)
INT1
P3.3
INTO
P3.2
TXD
P3.1
RXD
P3.0
!RD.! WR! T1! TO !INT1!INTO! TXD I RXDI
Symbol Position Name and Significance
RD
P3.7
Read data control output.
Active low pulse generated by
hardware when external data
memory is' read.
WR
P3.6
Write data control output.
Active low pulse generated by
hardware when external data
memory is written.
P3.5
T1
Timerlcounter 1 external input
or test pin.
P3.4
TO
Timerlcounter 0 external input
or test pin.
Interrupt 1 input pin.
Low-level or falling-edge triggered.
Interrupt 0 input pin.
Low-level or falling-edge triggered.
Transmit Data pin for serial
port in UART mode. Clock output in shift register mode.
Receive Data pin for serial
port in UART mode. Data 110
pin in shift register mode.
Figure 6. P3-Alternate 1/0 Functions of Port 3
Direct Bit Addressing
The most significant bit of the direct address byte selects one of two groups of bits. Values between 0 and
127 (DOH and 7FH) define bits in a block of 32 bytes of
on-chip RAM, between RAM addresses 20H and 2FH
(Figure 4a). They are numbered consecutively from the
lowest-order byte's lowest-order bit through the highest-order byte's highest-order bit.
2-36
Bit addresses between 12S and 255 (SOH and OFFH)
correspond to bits in a number of special registers,
mostly used for I/O or peripheral control. These positions are numbered with a different scheme than RAM:
the five high-order address bits match those of the register's own address, while the three low-order bits identify the bit position within that register (Figure 4b).
AP-70
Notice the column labeled "Symbol" in Figure 5. Bits
with special meanings in the PSW and other registers
have corresponding symbolic names. General-purpose
(as opposed to carry-specific) instructions may access
the carry like any other bit by using the mnemonic CY
in place of C, PO, Pt, P2, and P3 are the 805t's four
I/O ports: secondary functions assigned to each of the
eight pins of P3 are shown in Figure 6.
Figure 7 shows the last four bit addressable registers.
TCON (Timer Control) and SCON (Serial port Control) control and monitor the corresponding peripherals, while IE (Interrupt Enable) and IP (Interrupt Priority) enable and prioritize the five hardware interrupt
sources. Like the reserved hardware register addresses,
the five bits not implemented in IE and IP should not
be accessed: they can not be used as software flags.
Addressable Register Set. There are 20 special function
registers in the 805t, but the advantages of bit addressing only relate to the 11 described below. Five potentially bit-addressable register addresses (OCOH, OC8H,
OD8H, OE8H, & OF8H) are being reserved for possible
future expansion in microcomputers based on the
MCS-51 architecture. Reading or writing non-existent
registers in the 8051 series is pointless, and may cause
unpredictable results. Byte-wide logical operations can
be used to manipulate bits in all non-bit addressable
registers and RAM.
2-37
intJ
(MSB)
AP-70
(LSB)
IE1
I TF1 I TR1 I TFO I TRO IIE1 1,IT1 IlEa liTO I
Symbol Position Name and Significance
TF1
TCON.7 Timer 1 overflow Flag.
Set by hardware on timer/
counter overflow.
Cleared
when interrupt processed.
TR1
TCON.6 Timer 1 Run control bit.
Set!cleared by software to turn
timer/counter on/off.
TFO
TCON.S Timer 0 overflow Flag.
Set by hardware on timer/
counter overflow.
Cleared
when interrupt processed.
TRO
TCONA Timer 0 Run control bit.
Set! cleared by software to turn
timer/counter on/off.
IT1
lEO
ITO
TCON.3 Interrupt 1 Edge flag.
Set by hardware when external interrupt edge detected.
Cleared when interrupt pro"
cessed.
TCON.2 Interrupt 1 Type control bit.
Set!cleared by software to
specify falling edgellow level
triggered external interrupts.
TCON.1 Interrupt 0 Edge flag.
Set by hardware when external interrupt edge detected.
Cleared when interrupt processed.
TCON.O Interrupt 0 Type control bit.
Set!cleared by software to
specify falling edgellow level
triggered external interrupts.
a.) TCON-Timer/Counter Control/Status Register
(MSB)
(LSB)
RB8
I SMa I SM1 I SM2 I REN I TBS I RBSI TI I RI I
SCON.2 Receive Bit B.
Set/cleared by hardware to indicate state of ninth data bit
received.
Symbol Position Name and Significance
SMO
SCON.7 Serial port Mode control bit o.
TI
SCON.1 Transmit Interrupt flag.
Set! cleared by software (see
Set by hardware when byte
note).
transmitted. 'Cleared by software after serviCing.
SM1
SCON.6 Serial port Mode control bit 1.
Set!cleared by software (see
RI
SCON.O Receive Interrupt flag.
note).
Set by hardware when byte received. Cleared by software
SM2
SCON.S Serial port Mode control bit 2.
after servicing.
Set by software to disable reception of frames for which bit
Notethe state of (SMO, SM1)
B is zero.
selects:
(O,O)-8hift register I/O
REN
SCONA Receiver Enable control bit.
expansion.
Set/cleared by software to en(O,1)-8-bit UART, variable
able/disable serial data recepdata rate.
tion.
(1,O)-9-bit UART, fixed data
TBB
SCON.3 Transmit Bit B.
rate.
Set! cleared by hardware to de(1,1 )-9-bit UART, variable
termine state of ninth data bit
data rate.
transmitted in 9-bit UART
mode.
b.) SCON--5erial Port Control/Status Register
Figure 7. Peripheral Configuration Registers
2-38
inter
AP-70
(MSa)
(lSa)
I EA I - I - I ES I En
EX1
ET1
I EXO I
Symbol Position Name and Significance
1E.2
EX1
EA
IE. 7
Enable All control bit.
Cleared by software to disable
all interrupts, independent of
the state of IE.4-IE.O.
ETO
1E.1
(reserved)
IE.6
1E.5
ES
IE.4
Enable Serial port control bit.
EXO
lE.O
Set! cleared by software to enable/disable interrupts from TI
or RI flags.
Enable Timer 1 control bit.
ET1
IE.3
Set! cleared by software to enable/disable interrupts from
timer/counter 1.
c.) IE-Interrupt Enable Register
(MSa)
(lSa)
I - I - I - I PS
Symbol Position
IP.7
IP.6
IP.5
PS
IP.4
PT1
Enable External interrupt 1
control bit. Set! cleared by
software to enable/disable interrupts from INT1.
Enable Timer 0 control bit.
Set! cleared by software to enable/disable interrupts from
timer/counter o.
Enable External interrupt 0
control bit. Set! cleared by
software to enable/disable interrupts from INTO.
IP.3
PT1
PX1
I PTO I PXO I
Name and Significance
(reserved)
(reserved)
(reserved)
Serial port Priority control bit.
Set/cleared by software to
specify high/low priority interrupts for Serial port.
Timer 1 Priority control bit.
Set!cleared by software to
specify high/low priority interrupts for timer/counter 1.
PX1
IP.2
PTO
IP.1
PXO
IP.O
External interrupt 1 Priority
control bit. Set! cleared by
software to specify high/low
priority interrupts for INT1.
Timer 0 Priority control bit.
Set/ cleared by software to
specify high/low priority interrupts for timer/counter O.
External interrupt 0 Priority
control bit. Set!cleared by
software to specify high/low
priority interrupts for INTO.
d.) IP-Interrupt Priority Control Register
Figure 7. Peripheral Configuration Registers (Continued)
The accumulator and B registers (A and B) are normally involved in byte-wide arithmetic, but their individual
bits can also be used as 16 general software flags. Added with the 128 flags in RAM, this gives 144 general
purpose variables for bit-intensive programs. The program status word (PSW) in Figure 5 is a collection of
flags and machine status bits including the carry flag
itself. Byte operations acting on the PSW can therefore
affect the carry.
Instruction Set
Having looked at the bit variables available to the Boolean Processor, we will now look at the four classes of
2-39
instructions that manipulate these bits. It may be helpful to refer back to Table 2 while reading this section.
State Control. Addressable bits or flags may be set,
cleared, or logically complemented in one instruction
cycle with the two-byte instructions SETB, CLR, and
CPL. (The "B" affixed to SETB distinguishes it from
the assembler "SET" directive used for symbol definition.) SETB and CLR are analogous to loading a bit
with a constant: 1 or O. Single byte versions perform the
same three operations on the carry.
The MCS-5l assembly language specifies a bit address
in any of three ways:
• by a number or expression corresponding to the direct bit address (0-255):
AP-70
Logical Operations. Four instructions perform the logical-AND and logical-OR operations between the carry
and another bit, and leave the results in the carry. The
instruction mnemonics are ANL and ORL; the absence
or presence of a slash mark ("/") before the source
operand indicates whether to use the positive-logic value or the logical complement of the addressed bit. (The
source operand itself is never affected.)
• by the name or address of the register containing the
bit, the dot operator symbol (a period: "."), and the
.
bit's position in the register (7 -0):
• in the case of control and status registers, by the
predefined assembler symbols listed in the first columns of Figures 5-7.
Bits may also be given user-defined names with the as.sembler "BIT" directive and any of the above techniques. For example, bit 5 of the PSW may be cleared
by any of the four instructions.
USR_FLG BIT
PSW.5
User Symbol Definition
CLR
CLR
CLR
OD5B
PSW.5
FO
CLR
USR_FLG
Absolute Addressing
Use of Dot Operator
Pre-Defined Assembler
Symbol
User-Defined Symbol
Data Transfers. The two-byte MOY instructions can
transport any addressable bit to the carry in one cycle,
or copy the carry· to the bit in two cycles. A bit can be
moved between two arbitrary locations via the carry by
combining the two instructions. (If necessary, push and
pop the PSW to preserve the previous contents of the
carry.) These instructions can replace the multi-instruction sequence of Figure 8, a program structure appearing in controller applications whenever flags or outputs
are conditionally switched on or off.
All 8051 conditional jump instructions use program
counter-relative addressing, and all execute in two cycles. The last instruction byte encodes a signed displacement ranging from -128 to + 127. During execution, the CPU adds this value to the incremented program counter to produce the jump destination. Put another way, a conditional jump to the immediately following instruction would encode OOH in the offset byte.
A section of program or subroutine written using only
relative jumps to nearby addresses will have the same
machine code independent of the code's location. An
assembled routine may be repositioned anywhere in
memory, even crossing memory page boundaries, without having to modify the program or recompute destination addresses. To facilitate this flexibility, there is an .
unconditional "Short Jump" (SJMP) which uses relative addressing as well. Since a programmer would have
quite a chore trying to compute relative offset values
from one instruction to another, ASM51 automatically
computes the displacement needed given only the destination address or label. An error message will alert the
programmer if the destination is "out of ~ange."
ISOLATE
SOURCE
BIT
NO
SET
DESTINATION
BIT
Bit-test Instructions. The conditional jump instructiolls
"JC rei" (Jump on Carry) and "JNC rei" (Jump on
Not Carry) test the state of the carry flag, branching if
it is a one or zero, respectively. (The letters "rei" denote relative code addressing.) The three-byte instructions "JB bit.rel" and "JNB bit. rei" (Jump on Bit and
Jump on Not Bit) test the state of any addressable bit in
a similar manner. A fifth instruction combines the
Jump on Bit and Clear operations. "JBC bit. rei" conditionally branches to the indicated address, then clears
the bit in the same two cycle instruction. This operation
is the same as the MCS-48 "JTF" instructions.
CLEAR
DESTINATION
. BIT
The so-called "Bit Test" instructions implemented on
many other microprocessors simply perform the logical-AND operation between a byte variable and a constant mask, and set or clear a zero flag depending on
the result. This is essentially equivalent to the 8051
"MOY C.bit" instruction. A second instruction is then
needed to conditionally branch based on the state of the
zero flag. This does not constitute abstract bit-addressing in the MCS-51 sense. A flag exists only as a field
203830-4
Figure 8. Bit Transfer Instruction Operation
2-40
AP·70
within a register: to reference a bit the programmer
must know and specify both the encompassing register
and the bit's position therein. This constraint severely
limits the flexibility of symbolic bit addressing and reduces the machine's code-efficiency and speed.
Table 3. Other Instructions Affecting
the Carry Flag
Byte eyc
Mnemonic
Description
ADD A,Rn
Add register to
1
Accumulator
Add direct byte to
2
ADD A,direct
Accumulator
ADD A,@Ri
Add indirect RAM to
Accumulator
ADD A,#data
Add immediate data
2
to Accumulator
Add register to
ADDC A,Rn
Accumulator with
Carry flag
Add direct byte to
AD DC A,direct
2
Accumulator with
Carry flag
ADDC A,@Ri
Add indirect RAM to
Accumulator with
Carry flag
AD DC A,#data
Add immediate data
2
to Acc with Carry flag
Subtract register from
SUBB A,Rn
Accumulator with
borrow
Subtract direct byte
2
SUBB A,direct
from Acc with borrow
SUBB A,@Ri
Subtract indirect RAM
from Acc with borrow
SUBB A, # data
Subtract immediate
2
data from Acc with
borrow
Multiply A & B
4
MUL AB
DIV
AB
Divide A by B
4
DA
A
Decimal Adjust
1
Accumulator
Interaction with Other Instructions., The carry flag is
also affected by the instructions listed in Table 3. It can
be rotated through the accumulator, and altered as a
side effect of arithmetic instructions. Refer to the User's Manual for details on how these instructions operate.
Simple Instruction Combinations
By combining general purpose bit operations with certain addressable bits, one can "custom build" several
hundred useful instructions. All eight bits of the PSW
can be tested directly with conditional jump instructions to monitor (among other things) parity and overflow status. Programmers can take advantage of 128
software flags to keep track of operating modes, resource usage, and so forth.
The Boolean instructions are also the most efficient
way to control or reconfigure peripheral and I/O registers. All 32 I/O lines become "test pins," for example,
tested by conditional jump instructions. Any output pin
can be toggled (complemented) in a single instruction
cycle. Setting or clearing the Timer Run flags (TRO and
TRI) turn the timer/counters on or off; poIling the
same flags elsewhere lets the program determine if a
timer is running. The respective overflow flags (TFO
and TFI) can be tested to determine when the desired
period or count has elapsed, then cleared in preparation
for the next repetition. (For the record, these bits are all
part of the TCON register, Figure 7a. Thanks to symbolie bit addressing, the programmer only needs to remember the mnemonic associated with each function.
In other words, don't bother memorizing control word
layouts.)
In the MCS-48 family, instructions corresponding to
some of the above functions require specific opcodes.
Ten different opcodes serve to clear complement the
software flags FO and FI, enable/disable each interrupt, and start/stop the timer. In the 8051 instruction
set, just three opcodes (SETB, CLR, CPL) with a direct
bit address appended perform the same functions. Two
test instructions (JB and JNB) can be combined with
bit addresses to test the software flags, the 8048 I/O
pins TO, TI, and INT, and the eight accumulator bits,
replacing IS more different instructions.
RLC
A
RRC
A
Rotate Accumulator
Left through the Carry
flag
Rotate Accumulator
Right through Carry
flag
Compare,direct byte
to Acc & Jump if Not
Equal
Compare immediate
CJNE A, #data.rel
to Acc & Jump if Not
Equal
CJNE Rn, # data. rei Compare immed to
register & Jump if Not
Equal
CJNE @Ri,#data.rel Compare immed to
indirect & Jump if Not
Equal
CJNE A,direct.rel
Table 4a shows how 8051 programs implement software flag and machine control functions associated
with special opcodes in the 8048. In every case the
MCS-51 solution requires the same number of machine
cycles, and executes 2.5 times faster.
All mnemonics copyrighted
2-41
@
3
2
3
2
3
2,
3
2
Intel Corporation 1980.
inter
AP-70
Table 4a. Contrasting 8048 and 8051 Bit Control and Testing Instructions
8048
Instruction
Flag Control
CLR
C
CPL
FO
8x51
Instruction
Bytes
Cycles
,...Sec
1
1
1
1
2.5
2.5
CLR
CPL
C
FO
2
Flag Testing
_JNC
offset
JFO
offset
JB7
offset
2
2
2
2
2
2
5.0
5.0
5.0
JNC
JB
JB
rei
FO.rel
ACC.7.rel
3
3
2
2
2
Peripheral Polling
JTO
offset
JN1
offset
JTF
offset
2
2
2
2
2
2
5.0
5.0
5.0
JB
JNB
JBC
TO.rel
INTO.rel
TFO.rel
3
3
3
2
2
2
1
1
1
2.5
2.5
2.5
SETB
SETB
CLR
TRO
EXO
ETO
2
2
2
1
1
1
Machine and Peripheral Control
STRT
T
1
EN
1
1
DIS
TCNT1
1
Bytes
Cycles & ,...Sec
1
1
1
2
Table 4b. Replacing 8048 Instruction Sequences with Single 8x51 Instructions
8048
Instruction
Flag Control
Set carry
CLR
C
CPL
C
Set Software Flag
CLR
FO
CPL
FO
Bytes
Cycles
p.Sec
8051
Instruction
Bytes
Cycles & ,...Sec
=
2
2
5.0
SETB
C
1
1
=
2
2
5.0
SETB
FO
2
1
Turn Off Output Pin
P1.#OFBH
ANL
=
2
2
5.0
CLR
P1.2
2
1
Complement Output Pin
IN
A.P1
A.#04H
XRL
OUTL P1.A
=
4
6
15.0
CPL
P1.2
2
1
Clear Flag in RAM
RO.#FLGADR
MOV
A.@RO
MOV
A.#FLGMASK
ANL
@RO.A
MOV
=
6
6
15.0
CLR
USER
2
1
2·42
FLG
AP-70
Table 4b. Replacing 8048 Instruction Sequences with Single 8x51 Instructions (Continued)
8048
Instruction
Bytes
8x51
Instruction
Bytes
Cycles & ].LSec
FO.rel
3
2
JNB
ACC.7.rel
3
2
12.5
JNB
P1.3.rel
3
2
10.0
JB
INTO.rel
3
2
Cycles
].LSec
Flag Testing:
Jump if Software Flag is 0
JFO
$+4
JMP
offset
= 4
4
10.0
JNB
Jump if Accumulator bit is 0
CPL
A
JB7
offset
CPL
A
= 4
4
10.0
Peripheral Polling
Test if Input Pin is Grounded
IN
A.P1
CPL
A
JB3
offset
= 4
5
Test if Interrupt Pin is High
JN1
$+4
offset
JMP
= 4
4
3.0 BOOLEAN PROCESSOR
APPLICATIONS
So what? Then what does all this buy you?
Qualitatively, nothmg. All the same capabilities could
be (and often have been) implemented on other machines using awkward sequences of other basic operations. As mentioned earlier, any CPU can solve any
problem given enough time.
Quantitatively, the differences between a solution allowed by the 80S I and those required by previous architectures are numerous. What the 8051 Family buys
you is a faster, cleaner, lower-cost solution to microcontroller applications.
Combining Boolean and byte-wide instructions can
produce great synergy. An MCS-SI based application
will prove to be:
o simpler to write since the architecture correlates
more closely with the problems being solved:
• easier to debug because more individual instructions
have no unexpected or undesirable side-effects:
• more byte efficient due to direct bit addressing and
program counter relative branching:
• faster running because fewer bytes of instruction
need to be fetched and fewer conditional jumps are
processed:
• lower cost because of the high level of system-integration within one component.
These rather unabashed claims of excellence shaH not
go unsubstantiated. The rest of this chapter examines
less trivial tasks simplified by the Boolean processor.
The first three compare the 8051 with other microprocessors; the last two go into 80S I-based system designs in much greater depth.
The opcode space freed by condensing many specific
8048 instructions into a few general operations has been
used to add new functionality to the MCS-51 architecture-both for byte and bit operations. 144 software
flags replace the 8048's two. These flags (and the carry)
may be directly set, not just cleared and complemented,
and all can be tested for either state, not just one. Operating mode bits previously inaccessible may be read,
tested, or saved. Situations where the 80S I instruction
set provides new capabilities are contrasted with 8048
instruction sequences in Table 4b. Here the 80S I speed
advantage ranges from Sx to ISx! \
Design Example # 1-Bit Permutation
First off, we'll use the bit-transfer instructions to permute a lengthy pattern of bits.
2-43
AP-70
Different microprocessor architectures would best implement this type of permutation in different ways.
Most approaches would share the steps of Figure lOa:
• Initialize the Permutation Buffer to default state
(ones or zeroes):
A steadily increasing number of data communication
products use encoding methods to protect the security
of sensitive information. By law, interstate financial
- transactions involving the Federal banking system must
be transmitted using the Federal Information Processing Data Encryption Standard (DES).
• Isolate the state of a bit of a byte from the Key
Buffer. Depending on the, CPU, this might be accomplished by rotating a word of the Key Buffer
through a carry flag or. testing a bifin memory or an
accumulator against a,mask byte:
• Perform' a conditional jump based on the carry or
zero flag if the Permutation Buffer default state is
correct:
Basically, the DES combines eight bytes of "plaintext"
data (in binary, ASCII, or any other format) with a 56bit "key", producing a 64-bit encrypted value for transmission. 'At the receiving end the same algorithm is
applied to the incoming data using the same key, reproducing the original eight byte message. The algorithm
used for these permutations is fixed; different user-defined keys ensure data privacy.
• Otherwise reverse the corresponding bit in the permutation buffer with logical operations and mask
bytes.
It is not the purpose of this note to describe the DES in
any detail. Suffice it to say that encryption/decryption
is a long, iterative process consisting of rotations, exclusive -OR operations, function table look-ups, and an
extensive (and quite bizarre) sequence of bit permutation, packing, and unpacking steps. (For further details
refer to the June 21, 1979 issue of Electronics magazine.) The bit manipulation steps are included, it is rumored, to impede a general purpose digital supercomputer trying to "break" the code. Any algorithm implementing the DES with previous' generation microprocessors would spend virtually all of its time diddling
bits.
Each step above may require several instructions. The
iast three steps must be repeated for all 48 bits. Most
microprocessors would spend 300 to 3,000 microseconds 'on each of the 16 iterations.
Notice, though, that this flow chart looks a lot like
Figure 8. The Boolean Processor can permute bits by
simply moving them from the source to the carry to the
destination-a total of two instructions taking four
bytes and three microseconds per bit. Assume the Shifted Key Buffer and Permutation Buffer both reside in
bit-addressable RAM, with the bits of the former assigned symbolic names SKB_1, SKB_2, ... SKB_
56, and that the bytes of the latter are named PB_1,
... PB_8. Then working from Figure 9, the software
for the permutation algorithm would be that of Example 1a. The total routine length would be 192 bytes,
requiring 144 microseconds.
The bit manipulation performed is typified by the Key
Schedule Calculation represented in Figure 9. This step
is repeated 16 times for each key used in the course of a
transmission. In essence, a seven-byte, 56-bit "Shifted
Key Buffer" is transformed into an eight-byte, "Permutation Buffer" without altering the shifted Key. The
arrows in Figure 9 indicate a few of the translation
steps. Only six bits of each byte of the Permutation
Buffer are used; the. two high-order bits of each byte are
cleared. This means only 48 of the 56 Shifted Key Buffer bits are used in anyone iteration.
Permuted and Shifted 56-Bit Key Buffer
~
~
-----------------~-----------------~" "------------------~-----------------14151117
PERMUTATION BYTE 1
PERM BYTE 2
21
PERM BYTE 3
3233:M
PERM BYTE 4
BYTE 5
BYTEe
PERM BYlEr
PERM 8YlE8
203830-5
48-Bit Key Kr
Figure 9. DES Key Schedul,e Transformation
2-44
AP·70
REPEAT
FOR EACH
alTOF
SHinED
KEY
BUFFER
SET PERMUTATION
(LEAVE PERMUTATION
BUFFER BIT
PC2111
BUFFER BIT
148 TIMESI
CLEAREDI
203830-6
Figure 10a. Flowchart for Key Permutation Attempted with a Byte Processor
2-45
inter
AP-70
I
~
I
CLEAR ACCUMULATOR
LOAD BIT MAPPED ONTO BIT 5 OF
PERMUTATION BYTE INTO CARRY
I
I
ROTATE LEFT INTO ACC.
LOAD BIT MAPPED ONTO BIT 4
OF PERMUTATION BYTE INTO CARRY
I
I
ROTATE LEFT INTO ACC.
,
REPEAT
FOR EACH
BYTE OF
PERMUTATION
BUFFER
(8 TIMES)
,
LOAD BIT MAPPED ONTO BIT 0
OF PERMUTATION BYTE INTO CARRY
I
,
,
J
ROTATE LEFT INTO ACC.
STORE ACC. INTO PERMUTATION
BUFFER
I
203830-7
Figure 10b. DES Key Permutation with Boolean Processor
2-46
infef
Ap·70
The algorithm of Figure lOb is just slightly more efficient in this time-critical application and illustrates the
synergy of an integrated byte and bit processor. The
bits needed for each byte of the Permutation Buffer are
assimilated by loading each bit into the carry (1 J.l.s.)
and shifting it into the accumulator (1 J.l.s.). Each byte
is stored in RAM when completed. Forty-eight bits
thus need a total of 112 instructions, some of which are
listed in Example lb.
Example I. DES Key Permutation Software.
a.) "Brute Force" technique
Worst-case execution time would be 112 microseconds,
since each instruction takes a single cycle. Routine
length would also decrease, to 168 bytes. (Actually, in
the context of the complete encryption algorithm, each
permuted byte would be processed as soon as it is assimilated-saving memory and cutting execution time
by another 8 J.l.s.)
To date, most banking terminals and other systems using the DES have needed special boards or peripheral
controller chips just for the encryption/decryption process, and still more hardware to form a serial bit stream
for transmission (Figure Ila). An 8051 solution could
pack most of the entire system onto the one chip (Figure lib). The whole DES algorithm would require less
than one-fourth of the on-chip program memory, with
the remaining bytes free for operating the banking terminal (or whatever) itself.
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
C,SKB_I
PB_I.I, C
C,SKB_2
PB_4.0,C
C,SKB_3
PB_2.5,C
C,SKB_4
PB_I.O,C
MOV
MOV
MOV
MOV
C,SKB_55
PB_5.0,C
C,SKB_56
PB_7.2,C
b.) Using Accumulator to Collect Bits
Moreover, since transmission and reception of data is
performed through the on-board UART, the unencrypted data (plaintext) never even exists outside the
microcomputer! Naturally, this would afford a high degree of security from data interception.
2-47
CLR
MOV
RLC
MOV
RLC
MOV
RLC
MOV
RLC
MOV
RLC
MOV
RLC
MOV
A
C,SKB_14
A
C,SKB_17
A
C, SK1Lll
A
C,SKB_24
A
C,SKB_I
A
C,SKB_5
A
PB_I,A
MOV
RLC
MOV
RLC
MOV
C,SKB_29
A
C,SKB_32
A
PB_B,A
AP·70
CONTROL AND ADDRESS BUSSES
DISPLAY
CPU
RAM
DATA
ENCRY'
PTiON
UNIT
ROM
KEYBOARD
l
I
I
TO
MODEM
SYSTEM DATA BUS
203830-8
a.) Using Multi-Chip Processor Technology
DISPLAY
r'"..
P2
T.D
8051
PO
r
R.D
...
TO
MODEM
KEYBOARD
~
.
P1
203830-9
b.) Using One Single-Chip Microcomputer
Figure 11. Secure Banking Terminal Block Diagram
Design Example # 2-Software
Serial 1/0
An exercise often imposed on beginning microcomputer students is to write a program simulating a UART.
Though doing this with the 8051 Family may appear to
be a moot point (given that the hardware for a full
UART is on-chip), it is still instructive to see how it
would be done, and maintains a product line tradition.
As it turns out, the 8051 microcomputers can receive or
transmit serial data via software very efficiently using
the Boolean instruction set. Since any I/O pin may be a
serial input or output, several serial links could be
maintained at once.
2-48
Figures 12a and 12b show algorithms for receiving or
transmitting a byte of·data. (Another section of program would invoke this algorithm eight times, synchronizing it with a start bit, clock signal, software delay, or
timer interrupt.) Data is received by testing an input
pin, setting the carry to the same state, shifting the
carry into a data buffer, and saving the partial frame in
internal RAM. Data is transmitted by shifting an output buffer through the carry, and generating each bit
on an output pin.
A side-by-side comparison of the software for this common "bit-banging" application with three different microprocessor architectures is shown in Table Sa and 5b.
The 8051 solution is more efficient. than the others on
every count!
AP-70
PIN
SET CARRY
CLEAR CARRY
203830-10
a.) Reception
203830-11
b.) Transmission
Figure 12. Serial 110 Algorithms
2-49
AP-70
Table 5. Serial 1/0 Programs for Various Microprocessors
a.) Input Routine.
BOBS
I~
A"I
.IZ
CMC
10. I XI
MOV
RR
MOV
8051
B04B
SFRI'OR I
MASK
10
CI R
.1"10
CPI
MOV
MOV
RRC
MOV
HI..SERBlIF
A.M
M.A
C
10
("
RfI .• SFRBI'r
A.@RO
A
@RfI.A
MO\'
C.SERI'I"
MOV
RRC
MOV
A.S[RBl·r
A
SERBIIF.A
RFSlll TS:
K I"STRITTiO~S
14 BYTES
56 S rATES
19 uSEC
7 I~S I R l TTlO~S
9 BY I FS
9 CYCI.ES
12.5 uSFC
4 I,\S rRl'CTIO'\S
7 BYTES
4 CYCI.FS
4 uSFC
B048
8051
b.) Output Routine.
BOBS
I XI
MOV
RR
MOV
1:-;
.IC
10. A:-;I
.IMP
HI: ORI
O'"l:OIIT
HI .SfRBlI~
A.M
M.A
SERPORT
HI
'lOT MASK
C'IT
MASK
SFRI'OR r
HI:
("'"
RO.'SERBII~
MOV
MOV
RRC
MOV
A.@RO
A
@RO.A
.IC
A'\1.
.IMP
ORI.
HI
SERPRT.• '\oT MASK
C:-;T
SERPRT.'MASK
MOV
RRC
MOV
A.sERBl'F
A
SERBl'F.A
MOV
SERPI'\.C
RESULTS:
10lNSTRUCTIO)l;S
20 BYTES
72 STATES
24 uSEC
K I)I;STRlICTiONS
13 BYTES
II CYCLES
27.5 uSEC
Design Example # 3-Combinatorial
Logic Equations
Next we'll look at some simple uses for bit-test instructions and logical operations. (This example is also pre,sented in Application Note AP-69.)
Virtually all hardware designers have solved complex
functions using combinatorial logic. While the hardware involved may vary from relay logic, vacuum
tubes, or TTL or to more esoteric technologies like fluidics, in each case the goal is the same: to solve a problem represented by a logical function of several Boolean
variables.
4 INSTR UCTIONS
7 BYTES
5 CYCLES
5 uSEC
203830-30
Figure 13 shows TTL and relay logic diagrams for a
function of the six variables U through Z. Each is a
solution of the equation.
Q. = (U • (V
+ W)) +
(X. '1)
+Z
Equations of this sort might be reduced using Karnaugh Maps or algebraic techniques, but that is not the
purpose of this examp1e. As the logic complexity increases, so does the difficulty of the reduction process.
Even a minot; change to the function equations as the
design evolves would require tedious re-reduction from
scratch.
2-50
AP-70
u
v
w
x
r----a
y
z
Q
= (U •
(V
203830-12
+ W)) + (X. Y) + Z
a.) Using TTL
v
u
y
CR1
CR2
a
z
203830-13
b.) Using Relay Logic
Figure 13. Hardware Implementations of Boolean Functions
For the sake of comparison we will implement this
function three ways, restricting the software to three
proper subsets of the MCS-Sl instruction set. We will
also assume that U and V are input pins from different
input ports, Wand X are status bits for two peripheral
controllers, and Y and Z are software flags set up earli·
er in the program. The end result must be written
to an output pin on some third port. The first two implementations follow the flow-chart shown in Figure
14. Program flow would embark on a route down a
test-and-branch tree and leaves either the "True" or
"Not True" exit ASAP-as soon as the proper result
has been determined. These exits then rewrite the output port with the result bit respectively one or zero.
2-51
AP-70
The code which results is cumbersome and error prone.
It would be difficult to prove whether the software
worked for all input combinations in programs of this
sort. Furthermore, execution time will vary widely with
input data.
Thanks to the direct bit-test operations, a single instruction can replace each move mask conditional jump
sequence in Example 2a, but the algorithm would be
equally convoluted (see Example 2b). To lessen the
confusion "a bit"' each input variable is assigned a symbolic name .
. A more elegant and efficient implementation (Example
2c) strings together the Boolean ANL and ORL functions to generate the output function with straight-line
code. When finished, the carry flag contains the result,
which is simply copied out to the destination pin. No
flow chart is needed-<:ode can be written directly from
the logic diagrams in Figure 14. The result is simplicity
itself: fast, flexible, reliable, easy to design, and easy to
debug.
FUNCTION
IS FALSE
CLEAR
FUNCTION
IS TRUE
An 8051 program can simulate an N-input AND or·
OR gate with at most N + 1 lines of source programone for each input and one line to store the results. To
simulate NAND and NOR gates, complement the carry after computing the function. When some inputs to'
the gate have "inversion bubbles", perform the ANL or
ORL operation on inverted operands. When the first
input is inverted, either load the operand into the carry
and then complement it, or use DeMorgan's Theorem
to convert the gate to a different form.
Example 2. Software Solutions to Logic Function of
Figure 13.
a
a.) Using only byte-wide logical instructions
:BFUNCI
203830-14
Figure 14. Flow Chart for
Tree-Branching Algorithm
Other digital computers must solve equations of this
type with standard word-wide logical instructions and
conditional jumps. So for the first implementation, we
won't use any generalized bit-addressing instructions.
As we shall soon see, being constrained to such an instruction subset produces somewhat sloppy software
solutions. MCS-51 mnemonics are used in Example 2a:
other machines might further cloud the situation by
requiring operation-specific mnemonics like INPUT,
OUTPUT, LOAD, STORE, etc., instead of the MOV
mnemonic used for all variable transfers in the 8051
instruction set.
SOLVE RANDOM LOGIC
FUNCTION OF 6 VARIABLES
BY LOADING AND MASKING
THE APPROPRIATE BITS IN
THE ACCUMULATOR. THEN
EXECUTING CONDITIONAL
JUMPS BASED ON ZERO
CONDITION. (APPROACH USED
BY BYTE-ORIENTED
ARCHITECTURES. 1 BYTE AND
MASK VALUES CORRESPOND TO
RESPECTIVE BYTE ADDRESS
AND BIT POSITIONS.
OUTBUF DATA 22H
;OUTPUT PIN STATE MAP
2-52
inter
TESTV:
TESTU:
TESTX:
TESTZ:
CLRQ:
SETQ:
OUTQ:
AP-70
MOV A,P2
ANL A,#OOOOOlOOB
JNZ TESTU
MOV A,TCON
ANL A,#OOlOOOOOB
JZ
TESTX
MOV A,Pl
ANL A,#OOOOOOlOB
JNZ SETQ
MOV A,TCON
ANL A,#OOOOlOOOB
JZ
TESTZ
MOV A,20H
ANL A,#OOOOOOOlB
JZ
SETQ
MOV A,21H
ANL A,#OOOOOOlOB
JZ
SETQ
MOV A,OUTBUF
ANL A,#llllOlllB
JMP OUTQ
MOV A,OUTBUF
ORL A,#OOOOlOOOB
MOV OUTBUF,A
MOV P3,A
U
V
W
X
Y
Z
Q
BIT
BIT
BIT
BIT
BIT
BIT
BIT
,
Pl.l
P2.2
TFO
IEl
20H.O
21H.l
P3.3
TEST_V: JB
V,TEST_U
JNB
W,TEST_X
TEST_U: JB
U,SET_Q
TEST_X: JNB
X,TEST_Z
JNB
Y,SET_Q
TEST_Z: JNB
Z,SET_Q
CLR_Q: CLR
Q
JMP
NXTTST
SET_Q: SETB Q
NXTTST:(CONTINUATION OF
: PROGRAM)
c.) Using logical operations on Boolean variables
:FUNC3 SOLVE A RANDOM LOGIC
FUNCTION OF 6 VARIABLES
USING STRAIGHT_LINE
LOGICAL INSTRUCTIONS ON
MCS-51 BOOLEAN VARIABLES.
b.) Using only bit-test instructions
;
:BFUNC2 SOLVE A RANDOM LOGIC
FUNCTION OF 6 VARIABLES
BY DIRECTLY POLLING EACH
BIT. (APPROACH USING
MCS-51 UNIQUE BIT-TEST
INSTRUCTION CAPABILITY.)
SYMBOLS USED IN LOGIC
DIAGRAM ASSIGNED TO
CORRESPONDING 8x51 BIT
ADDRESSES.
MOV
ORL
ANL
MOV
MOV
ANL
ORL
ORL
C,V
C,W
C,U
FO,C
C,X
C,Y
C,FO
C,Z
MOV Q,C
2-53
;OUTPUT OF OR GATE
;OUTPUT OF TOP AND GATE
;SAVE INTERMEDIATE STATE
;OUTPUT OF BOTTOM AND GATE
;INCLUDE VALUE SAVED ABOVE
;INCLUDE LAST INPUT
;VARIABLE
;OUTPUT COMPUTED RESULT
inter
AP-70
An upper-limit can be placed on the complexity of software to simulate a large number of gates by summing
the total number of inputs and outputs. The actual total
should be somewhat shorter, since calculations can be
"chained," as shown. The output of one gate is often
the first input to another, bypassing the intermediate
variable to eliminate two lines of source.
Imagine the three position turn lever on the steering
column as a single-pole, triple-throw toggle switch. In
its central position all contacts are open. In the up or
down positions contacts close causing corresponding
lights in the rear of the car to blink. So far very simple.
Two more turn signals blink in the front of the car, and
two others in the dashboard. All six bulbs flash when
an emergency switch is closed. A thermo-mechanical
relay (accessible under the dashboard in case it wears
out) causes the blinking.
Design Example # 4-Automotive
Dashboard Functions
Now let's apply these techniques to designing the software for a complete controller system. This application
is patterned after a familiar real-world· application
which isn't nearly as trivial as it might first appear:
automobile turn signals.
Applying the brake pedal turns the tail light filaments
on constantly ... unless a turn is in progress, in which
case the blinking tail light is not affected. (Of course,
the front turn signals and dashboard indicators are not
affected by the brake pedal.) Table 6 summarizes these
operating modes.
Table 6. Truth Table for Turn-Signal Operation
Input Signals
Output Signals
Right
Turn
Switch
Left
Front
& Dash
Right
Front
& Dash
Left
Rear
Right
Rear
Off
Off
Blink
Blink
Blink
Blink
Off
Off
Blink
Blink
Blink
Blink
Off
Blink
Off
Blink
Blink
Blink
Off
Blink
Off
Blink
Blink
Blink
' Off
Off
Blink
Blink
Blink
Blink
On
On
Blink
On
On
Blink
Off
Blink
Off
Blink
Blink
Blink
' On
Blink
On
On
Blink
On
Brake
Switch
Emerg.
Switch
Left
Turn
Switch
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
0
0
1
0
1
0
1
1
1
0
0
0
0
0
1
0
1
0
1
1
1
1
0
0
1
0
1
1
1
0
1
0
2-54
Ap·70
But we're not done yet. Each of the exterior turn signal
(but not the dashboard) bulbs has a second, somewhat
dimmer filament for the parking lights. Figure 15
shows TTL circuitry which could control all six bulbs.
The signals labeled "High Freq." and "Low Freq." represent two square-wave inputs. Basically, when one of
the turn switches is closed or the emergency switch is
activated the low frequency signal (about 1 Hz) is gated
through to the appropriate dashboard indicator(s) and
turn signal(s). The rear signals are also activated when
the brake pedal is depressed provided a turn is not being made in the same direction. When the parking light
switch is closed the higher frequency oscillator is gated
to each front and rear turn signal, sustaining a low-intensity background level. (This is to eliminate the need
for additional parking light filaments.)
In most cars, the switching logic to generate these functions requires a number of multiple-throw contacts. As
many as 18 conductors thread the steering column of
some automobiles solely for turn-signal and emergency
blinker functions. (The author discovered this recently
to his astonishment and dismay when replacing the
whole assembly because of one burned contact.)
A multiple-conductor wiring harness runs to each corner of the car, behind the dash, up the steering column,
and down to the blinker relay below. Connectors at
L. TURN
EMERG
each termination for each filament lead to extra cost
and labor during construction, lower reliability and
safety, and more costly repairs. And considering the
system's present complexity, increasing its reliability or
detecting failures would be quite difficult.
There are two reasons for going into such painful detail
describing this example. First, to show that the messiest
part of many system designs is determining what the
controller should do. Writing the software to solve
these functions will be comparatively easy. Secondly, to
show the many potential failure points in the system.
Later we'll see how the peripheral functions and intelligence built into a microcomputer (with a little creativity) can greatly reduce external interconnections and
mechanical part count.
The Single-Chip Solution
The circuit shown in Figure 16 indicates five input pins
to the five input variables-left-turn select, right-turn
select, brake pedal down, emergency switch on, and
parking lights on. Six output pins turn on the front,
rear, and dashboard indicators for each side. The microcomputer implements all logical functions through
software, which periodically updates the output signals
as time elapses and input conditions change.
1---....- - - - - - L. DASH
L. FRNT
BRAKE
L. REAR
R.TURN
}--....+----- R. DASH
R.FRNT
R.REAR
PARK --------------~---~~
LO.
FREO.
OSCILLATOR
HI.
FREO.
OSCILLATOR
Figure 15. TTL Logic Implementation of Automotive Turn Signals
2-55
203830-15
inter
AP-70
+12V
+12V
8051
LE"
FRONT
BRAKE
PEDAL
Pl.0
EMERGENCY
SWITCH
Pl:l
PARKING
LIGHTS
Pl.2
LE"
TURN
SWITCH
Pl.5
RIGHT
FRONT
P1.I
LE"
OASHIOA.IID
P1.7
RIGHT
DASHBOARD
Pl.3
P2.0
RIGHT
Pl.4
....
LE"
REAR
P2.1
P2.2
.)r--~~--'
RIGHT
REAR
•
MODE
SENSORS
CONTROLLER
SIGNAL
CONDITIONING
OUTPUT
BUFFERS
SIGNAL
BULBS
203830-16
Figure 16. Microcomputer Turn-Signal Connections
Design Example # 3 demonstrated that symbolic addressing with user-defined bit names makes code and
documentation easier to write and maintain. Accordingly, we'll assign these I/O pins names for use
throughout the program. (The format of this example
will differ somewhat from the others. Segments of the
overall program will be preSented in sequence as each is
described.)
INPUT PIN DECLARATIONS:
;(ALL INPUTS ARE POSITIVE-TRUE LOGIC)
BRAKE
BIT Pl.O ;BRAKE PEDAL
;DEPRESSED
EMERG BIT Pl.l ;EMERGENCY BLINKER
;ACTIVATED
PARK
BIT Pl.2 ;PARKING LIGHTS ON
I_TURN BIT Pl.3 ;TURN LEVER DOWN
R_TURN BIT P1.4 ;TURN LEVER UP
OUTPUT PIN DECLARATIONS:
BIT Pl.5 ;FRONT LEFT-TURN
;INDICATOR
R_FRNT BIT Pl.6 ;FRONT RIGHT-TURN
;INDICATOR
I_DASH BIT Pl.7 ;DASHBOARD LEFT-TURN
;INDICATOR
I~FRNT
R_DASH BIT P2.0 ;DASHBOARD RIGHT;TURN INDICATOR
I_REAR BIT P2.l.;REAR LEFT-TURN
;INDICATOR
R_REAR BIT P2.2 ;REAR RIGHT-TURN
;INDICATOR
Another key advantage of symbolic addressing will appear further on in the design cycle. The locations of
cable connectors, signal conditioning circuitry, voltage
regulators, heat sinks, and the like all affect P.C. board
layout. It's quite likely that the somewhat arbitrary pin
.assignment defined early in the software design cycle
will prove to be less than optimum; rearranging the I/O
pin assignment could well allow a more compact module, or eliminate costly jumpers on a single-sided board.
(These considerations apply especially to automotive
and other. cost-sensitive applications needing singlechip controllers.) Since other architectures mask bytes
or use "clever" algorithms to isolate bits by rotating
them into the carry, re-routing an input signal (from bit
I of port I, for example, to bit 4 of port 3) could require
. extensive modifications throughout the software.
The Boolean Processor's direct bit addressing makes
such changes absolutely trivial. The number of the port
containing the pin is irrelevent, and masks and complex
2-56
intJ
AP-70
program structures are not needed. Only the initial
Boolean variable declarations need to be changed;
ASM51 automatically adjusts all addresses and symbolic references to the reassigned variables. The user IS
assured that no additional debugging or software verification will be required.
;INTERRUPT RATE SUBDIVIDER
SUB_DIV
DATA
20H
;HIGH-FREQUENCY OSCILLATOR BIT
HLFREQ
BIT
SUB_DIV,O
;LOW-FREQUENCY OSCILLATOR BIT
LO_FREQ
BIT
SUB_DIV,7
JMP
ORG
INIT
"tuned" to approximately I Hz for the turn- and emergency-indicator blinking rate.
Loading THO with -16 will cause an interrupt after
4.096 ms. The interrupt service routine reloads the
high-order byte of timer 0 for the next interval, saves
the CPU registers likely to be affected on the stack, and
then decrements SUB_DIY. Loading SUB_DIY.
with 244 initially and each time it decrements to zero
will produce a 0.999 second period for the highest-order bit.
ORG
MOV
PUSH
PUSH
PUSH
DJNZ
MOV
OOOOH
ORG
lOOH
;PUT TIMER 0 IN MODE 1
INIT;
MOV
TMOD,#OOOOOOOlB
;INITIALIZE TlMER REGISTERS
MOV
TLO,#O
MOV
THO,#-l6
;SUBDIVIDE INTERRUPT RATE BY 244
MOV
SUB_DIV,#244
;ENABLE TIMER INTERRUPTS
SETB
ETO
;GLOBALLY ENABLE ALL INTERRUPTS
SETB
EA
;START TIMER
SETB
TRO
OOOBH
;TIMER 0 SERVICE VECTOR
THO,#-l6
PSW
ACC
B
SUB_DIV,TOSERV
SUB_DIV,#244
The code to sample inputs, perform calculations, and
update outputs-the real "meat" of the signal controller algorithm-may be performed either as part of the
interrupt service routine or as part of a background
program loop. The only concern is that it must be executed at least serveral dozen times per second to prevent parking light flickering. We will assume the former case, and insert the code into the timer 0 service
routine.
First, notice from the logic diagram (Figure 15) that
the subterm (PARK • H_FREQ), asserted when the
parking lights are to be on dimly, figures into four of
the six output functions. Accordingly, we will first
compute that term and save it in a temporary location
named "DIM". The PSW contains two general purpose
flags: FO, which corresponds to the 8048 flag of the
same name, and PSW.l. Since the PSW has been saved
and will be restored to its previous state after servicing
the interrupt, we can use either bit for temporary storage.
;(CONTINUE WITH BACKGROUND PROGRAM)
;PUT TIMER 0 IN MODE 1
;INITIALIZE TIMER REGISTERS
;SUBDIVIDE INTERRUPT RATE BY 244
;ENABLE TIMER INTERRUPTS
;GLOBALLY ENABLE ALL INTERRUPTS
;START TIMER
DIM BIT
Timer 0 (one of the two on-chip timer counters) replaces the thermo-mechanical blinker relay in the dashboard controller. During system initialization it is configured as a timer in mode 1 by setting the least significant bit of the timer mode register (TMOD). In this
configuration the low-order byte (TLO) is incremented
every machine cycle, overflowing and incrementing the
high-order byte (THO) every 256 J.Cos. Timer interrupt 0
is enabled so that a hardware interrupt will occur each
time THO overflows.
An eight-bit variable in the bit-addressable RAM array
will be needed to further subdivide the interrupts via
software. The lowest-order bit of this counter toggles
very fast to modulate the parking lights: bit 7 will be
2-57
PSW.l ;DECLARE TEMP
;STORAGE FLAG
MOV C,PARK
ANL HLFREQ
MOV DIM,C
;GATE PARKING
;LIGHT SWITCH
;WITH HIGH
;FREQUENCY
;SIGNAL
;AND SAVE IN
;TEMP. VARIABLE
This simple three-line section of code illustrates a remarkable point. The software indicates in very abstract
terms exactly what function is being performed, inde-
AP-70
pendent of the hardware configuration. The fact that
these three bits include an input pin, a bit within a
program variable, and a software flag in the PSW is
totally invisible to the programmer.
ORL C,DIM
'MOV L_REAR, C
Now generate and output the dashboard left tum signal.
MOV C,L_TURN
Now we have to go through a similar sequence for the
right-hand equivalents to all the left-tum lights. This
also gives us a chance to see how the code segments
. above look when combined.
;SET CARRY IF
; TURN
;OR EMERGENCY
;SELECTED
;GATE IN 1 HZ
;SIGNAL
;AND OUTPUT TO
;DASHBOARD
ORL C,EMERG
ANL C,LO_FREQ
MOV LDASH,C
MOV C.R_TURN
ORL
ANL
MOV
To generate the left front tum signal we only need to
add the parking light function in FO. But notice that the
function in the carry will also be needed for the rear
signal. We can save effort later by saving its current
state in FO.
MOV
ORL
MOV
MOV FO,C
MOV
;SAVE FUNCTION
:SO FAR
:ADD IN PARKING
;LIGHT FUNCTION
;AND OUTPUT TO
:TURN SIGNAL
ORL C,DIM
MOV L_FRNT,C
ANL
ORL
ORL
Finally, the rear left tum signal should also be on when
the brake pedal is depressed, provided a left tum is not
in progress.
MOV C,BRAKE
ANL C,L_TURN
ORL C,FO
;AND PARKING
;LIGHT FUNCTION
;AND OUTPUT TO
;TURN SIGNAL
MOV
;SET CARRY H;TURN
C.EMERG
;OR EMERGENCY
;SELECTED
C,LO_FREQ ;IF SO. GATE IN 1
;HZ SIGNAL
R_DASH.C
;AND OUTPUT TO
;DASHBOARD .
FO.C
;SAVE FUNCTION
;SO FAR
C.DIM
;ADD ni PARKING.
;LIGHT FUNCTION
R_FRNT.C
;AND OUTP~T TO
;TURN SIGNAL
C.BRAKE
;GATE BRAKE
:PEDAL SWITCH
C. R_TURN' ;WITH TURN
;LEVER
C.FO
;INCLUDE TEMP.
;VARIABLE FROM
;DASH
C.DIM
;AND PARKING
;LIGHT FUNCTION
R_REAR.C
;AND OUTPUT TO
;TURN SIGNAL
(The perceptive reader may notice that simply rearrapging the steps could eliminate one instruction from
each sequence.)
;GATE BRAKE
;PEDAL SWITCH
;WITH TURN
;LEVER
;INCLUDE TEMP.
;VARIABLE FROM DASH
Now that all six bulbs are in the proper states, we can
return from the interrupt routine, and the program is
finished. This code essentially needs to reverse the
status saving steps at the beginning of the interrupt.
Table 7 Non-Trivial Duty Cycles
Sub_Div Bits
7
X
X
X
X
X
X
X
X
6
X
X
X
X
X
X
X
X
5
X
X
X
X
X
X
X
X
4
X
X
X
X
X
X
X
X
3
X
X
X
X
X
X
X
X
12.5%
25.0%
37.5%
1
Off
Off
Off
Off
Off
Off
0
Off
Off
Off
Off
Off
Off
Off
On
On
Off
Off
Off
Off
Off
On
On
On
2
0
0
0
0
1
0
0
1
0
1
0
0
1
1
1
1
1
On
1
1
0
0
1
0
1
2-58
Duty Cycles
50.0%
62.5%
Off
Off
Off
Off
On
On
On
On
Off
Off
Off
On
On
On
On
On
75.0%
87.5%
Off
Off
On
On
On
On
On
On
Off
On
On
On
On
On
On
On
infef
POP
B
AP-70
driver circuits combining shift-register inputs with high
drive level outputs have been introduced recently.
;RESTORE CPU
;REGISTERS.
POP ACC
POP psw
RETI
Cascading multiple shift registers end-to-end will expand the number of outputs even further. The data rate
in the I/O expansion mode is one megabaud, or 8 fLs.
per byte. This is the mode which the serial port defaults
to following a reset, so no initialization is required.
Program Refillemellts. The luminescence of an incandescent light bulb filament is generally non-linear: the'
50% duty cycle of HI_FREQ may not produce the
desired intensity. If the application requires, duty cycles of 25%, 75%, etc. are easily achieved by ANDing
and ORing in additional low-order bits of SUB_DIY.
For example, 30 H/ signals of seven different duty cycles could be produced by considering bits 2-0 as
shown in Table 7. The only software change required
would be to the code which sets-up variable DIM;
MOV C,SUB_DIV.l;START WITH 50
;PERCENT
ANL C,SUB_DIV.O;MASK DOWN TO 25
,
;PERCENT
ORL C,SUB_DIV.2;AND BUILD BACK TO
;62 PERCENT
MOV DIM,C
;DUTY CYCLE FOR
;PARKING LIGHTS.
The software for this technique uses the B register as a
"map" corresponding to the different output functions.
The program manipulates these bits instead of the output pins. After all functions have been calculated the B
register is shifted by the serial port to the shift-register
driver. (While some outputs may glitch as data is shifted through them, at 1 Megabaud most people wouldn't
notice. Some shift registers provide an "enable" bit to
hold the output states while new data is being shifted
in.)
This is where the earlier decision to address bits symbolically throughout the program is going to payoff.
This major I/O restructuring is nearly as simple to implement as rearranging the input pins. Again, only the
bit declarations need to be changed.
LFRNT BIT B.O ;FRONT LEFT-TURN
;INDICATOR
R_FRNT BIT B.l ;FRONT RIGHT-TURN
;INDICATOR
LDASH BIT B.2 ;DASHBOARD LEFT-TURN
;INDICATOR
R_DASH BIT B.3 ;DASHBOARD RIGHT-TURN
;INDICATOR
LREAR BIT B.4 ;REAR LEFT-TURN
;INDICATOR
R_REAR BIT B.5 ;REAR RIGHT-TURN
;INDICATOR
Interconnections increase cost and decrease reliability.
The simple buffered pin-per-function circuit in Figure
16 is insufficient when many outputs require higherthan-TTL drive levels. A lower-cost solution uses the
8051 serial port in the shift-register mode to augment
I/O. In mode 0, writing a byte to the serial port data
buffer (SBUF) causes the data to be output sequentially
through the "RXD" pin while a burst of eight clock
pulses is generated on the "TXD" pin. A shift register
connected'to these pins (Figure 17) will load the data
byte as it is shifted out. A number of special peripheral
+12V
8051
P3.0
I------""i
DATA 07
P3.1
I - - - -.....~
eLK
01
00
8·BIT SHIFT REGISTER
203830-17
Figure 17. Output Expansion Using Serial Port
2-59
AP-70
The original program to compute the functions need
not change. After computing the output variables, the
control map is transmitted to the buffered shift register
through the serial port.
MOV SBUF,B ;LOAD BUFFER AND TRANSMIT
The Boolean Processor solution holds a number of advantages over older methods. Fewer switches are re. quired. Each is simpler, requiring fewer poles and lower
current contacts. The flasher relay is eliminated entirely. Only six filaments are driven, rather than 10. The
wiring harness is therefore simpler and less expensive-one conductor for each of the six lamps and each of the
five sensor switches. The fewer conductors use far fewer connectors. The whole system is more reliable.
And since the system is much simpler it would be feasible to implement redundancy and or fault detection on
the four main turn indicators. Each could still be a
standard double filament bulb, but with the filaments
driven in parallel to tolerate single-element failures ..
Even with redundancy, the lights will eventually fail.
To handle this inescapable fact current or voltage sensing circuits on each main drive wire can verify that
each bulb and its high-current driver is functioning
properly. Figure 1~ shows one such circuit.
Assume all of the lights are turned on except one: i.e.,
all but one of the collectors are grounded. For the bulb
which is turned off, if there is continuity from + 12V
through the bulb base and filament, the control wire, all
connectors, and the P.C. board traces, and if the transistor is indeed not shorted to ground, then the collector will be pulled to + 12V. This turns on the base of
Q8 through the corresponding resistor, and grounds the
input pin, verifying that the bulb circuit is operational.
The continuity of each circuit can be checked by software in this way.
WIRING
HARNESS
+12V
I
P1.5
~-+-i'"
P1.6
~--+-
PH
I--+--r
P2.0
1--+-('"
....
P2.1
P2.2
~-+-t'
+5V
TO
I------t.-_
203830-18
Figure 18
2-60
AP-70
The complete assembled program listing is printed in
Appe~dix A. The resulting code consists of 67 program
statements, not counting declarations and comments,
which assemble into 150 bytes of object code. Each pass
through the service routine requires (coincidently)
67 /-Ls plus 32 /-Ls once per second for the electrical test.
If executed every 4 ms as suggested this software would
typically reduce the throughput of the background program by less than 2%.
Now turn all the bulbs on, grounding all the collectors.
Q7 should be turned off, and the Test pin should be
high. However, a control wire shorted to + 12V or an
open-circuited drive transistor would leave one of the
collectors at the higher voltage even now. This too
would turn on Q7, indicating a different type offailure.
Software could perform these checks once per second
by executing the routine every time the software counter SUB_DIV is reloaded by the interrupt routine.
Once a microcomputer has been designed into a system,
new features suddenly become virtually free. Software
could make the emergency blinkers flash alternately or
at a rate faster than the turn signals. Turn signals could
override the emergency blinkers. Adding more bulbs
would allow multiple taillight sequencing and syncopation-true flash factor, so to speak.
DJNZ SUB_DIV,TOSERV
MOV SUB_DIV,#244
;RELOAD COUNTER
;SET CONTROL
ORL Pl,#lllOOOOOB
;OUTPUTS HIGH
ORL P2,#00000111B
CLR LFRNT
;FLOAT DRIVE
;COLLECTOR
JB TO ,FAULT
;TO SHOULD BE
;PULLED LOW
SETB L_FRNT
;PULL COLLECTOR
;BACK DOWN
CLR L_DASH
JB
TO ,FAULT
SETB L_DASH
CLR L_REAR
JB
TO ,FAULT
SETB L_REAR
CLR R_FRNT
JB
TO ,FAULT
SETB R_FRNT
CLR R_DASH
JB
TO ,FAULT
SETB R_DASH
CLR R_REAR
JB
TO ,FAULT
SETB R_REAR
Design Example # 5-Complex Control
Functions
Finally, we'll mix byte and bit operations to extend the
use of 8051 into extremely complex applications.
Programmers can arbitrarily assign I/O pins to input
and output functions only if the total does not exceed
32, which is insufficient for applications with a very
large number of input variables. One way to expand the
number of inputs is with a technique similar to multiplexed-keyboard scanning.
Figure 19 shows a block diagram for a moderately complex programmable industrial controller with the following characteristics:
• 64 input variable sensors:
• 12 output signals:
• Combinational and sequential logic computations:
• Remote operation with communications to a host
processor via a high-speed full-duplex serial link:
• Two prioritized external interrupts:
• Internal real-time and time-of-day clocks.
;WITH ALL COLLECTORS GROUNDED. TO
SHOULD BE HIGH .
;IF SO. CONTINUE WITH INTERRUPT
ROUTINE.
.
JB
TO,TOSERV
FAULT:
;ELECTRICAL
;FAILURE
;PROCESSING
;ROUTINE
;(LEFT TO
;READER'S
;IMAGINATION)
TOSERV:
;CONTINUE WITH
; INTERRUPT
;PROCESSING
While many microprocessors could be programmed to
provide these capabilities with assorted peripheral support chips, an 8051 microcomputer needs no other integrated circuits!
The 64 input sensors are logically arranged as an 8x8
matrix. The pins of Port 1 sequentially enable each column of the sensor matrix: as each is enabled Port 0
reads in the state of each sensor in that column. An
eight-byte block in bit-addressable RAM remembers
the data as it is read in so that after each complete scan .
cycle there is an internal map of the current state of all
sensors. Logic functions can then directly address the
elements of the bit map.
2-61
intJ
AP-70
+5V
I""
fl.0UF
12M~Z
~
~
XTAL2
).,
32 40 48 56
57
PO.l
2
- ~rss
58
PO.2
60
PO.4
61
PO.5
62
PO.6
8.8
f-~
4
rs~
I-
SENSOR
MATRIX
P3.5
P3.6
P3.7
PO.3
P2.0
P2.1
6
7
ASYNCHRONANS
INTERRUPTS
P3.4
PO.O
1
~~
I
I NTl
8051
RETURN
LINES
16 24
I
INTO
-
TXD
I
8
-
RXD
SERIAL \
LINK
0
VCC RST
XTALl
15 23 31 39 47 55 63
MACHINE
ACTUATORS
P2.2
PO.7
P2.3
t
P2.4
~
Pl.0
P2.5
Pl.l
P2.6
Pl.2
P2.7
Pl.3
Pl.4
Pl.5
ALE
Pl.6
PSEN
f---
r---
N.C
N.C.
Pl.7
/~
VSS
EA
'J:J
SCAN
LINES
203830-19
Figure 19. Block Diagram of 64-lnput Machine Controller
The computer's serial port is configured as a nine-bit
UART, transferring data at 17,000 bytes-per-second.
The ninth bit may distinguish between address and data
bytes.
The 8051 serial port can' be configured to detect bytes
with the address bit set, automatically ignoring all others. Pins INTO and INTI are interrupts configured respectively as high-priority, falling-edge triggered and
low-priority, low-level triggered. The remaining 12 I/O
pins output TTL-level control signals to 12 actuators.
2-62
There are several ways to implement the sensor matrix
circuitry, all'logically similar. Figure 20a shows one
possibility. Each of the 64 sensors consists of a pair of
simple switch contacts in series with a diode to permit
multiple contact closures throughout the matrix.
The scan lines from Port 1 provide eight un-encoded
active-high scan signals for enabling columns of the
matrix. The return lines on rows where a contact is
closed are pulled high and read as logic ones. Open
return lines are pulled to ground by one of the 40 kfl.
resistors and are read as zeroes. (The resistor values
must be chosen to ensure all return lines are pulled
above the 2.0V logic threshold, even in the worst-case,
inter
AP-70
where all contacts in an enabled column are closed.)
Since PO is provided open-collector outputs and highimpedance MOS inputs its input loading may be considered negligible.
The circuits in Figures 20b-20d are variations on this
theme. When input signals must be electrically isolated
from the computer circuitry as in noisy industrial environments, phototransistors can replace the switch diode
pairs and provide optical isolation as in Figure 20b.
Additional opto-isolators could also be used on the control output and special signal lines.
Example 3.
INPUT_SCAN:
MOV
MOV
MOV
SCAN; MOV
The other circuits assume that input signals are already
at TTL levels. Figure 20c uses octal three-state buffers
enabled by active-low scan signals to gate eight signals
onto Port o. Port 0 is available for memory expansion
or peripheral chip interfacing between sensor matrix
scans. Eight-to-one multiplexers in Figure 20d select
one of eight inputs for each return line as determined
by encoded address bits output on three pins of Port I.
(Five more output pins are thus freed for more control
functions.) Each output can drive at least one standard
TTL or up to 10 low-power TTL loads without additional buffering.
RR
MOV
MOV
XCH
MOV
Going back to the original matrix circuit, Figure 21
shows the mediod used to scan the sensor matrix. Two
complete bit maps are maintained in the bit-addressable
region of the RAM: one for the current state and one
for the previous state read for each sensor. If the need
arises, the program could then sense input transitions
and or debounce contact closures by comparing each
bit with its earlier value.
INC
INC
MOV
JNB
RET
The code in Example 3 implements the scanning algorithm for the circuits in Figure 20a. Each column is
enabled by setting a single bit in a field of zeroes. The
bit maps are positive logic: ones represent contacts that
are closed or isolators turned on.
2-63
;SUBROUTINE TO READ
;CURRENT STATE
;OF 64 SENSORS AND
;SAVE IN RAM 20H-27H
;INITIALIZE
RO.#20H
;POINTERS
RI,#28H
;FOR BIT MAP
;BASES
.
;SET FIRST BIT
A,#80H
;IN ACC
;OUTPUT TO SCAN
PI,A
;LINES
;SHIFT TO ENABLE
A
;NEXT COLUMN
;NEXT
R2,A
;REMEMBER CUR;RENT SCAN
;POSITION
;READ RETURN
A,PO
;LINES
A.@RO
;SWITCH WITH
;PREVIOUS MAP
;BITS
@RI,A
;SAVE PREVIOUS
;STATE AS WELL
RO
;BUMP POINTERS
RI
A,R2
;RELOAD SCAN
;LINE MASK
ACC,7;SCAN;LOOP UNTIL ALL
;EIGHT COLUMNS
; READ
inter
AP-70
+ SV
J
"0"
...J......
~
~~
-
~...L.S!z
"57"
......I.-
~...L.S7
I
I
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PO.l
PO.2
1
PO.3
I
1
'-+ I
--L-
......
T
r-
I~
1+
"15"
'
~SZ
1
"7"
r,lllNES
PO.O
"9"
I
I
RETURN
I-
-
......~
8051
"56"
"8"
"1"
~-1-
+8x4K
PO.4
I
PO.S
PO.&
"63"
-L...
,~~
~
f0-
8x40K
r
PO.7
=:.;-Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.S
Pl.&
Pl.7
SCAN
LINES
203830-20
a.) Using Switch Contact/Diode Matrix
Figure 20. Sensor Matrix Implementation Methods
2-64
infef
AP-70
+SV
+8.4K
~
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~,
~'l"
.-
C)lA'~ ....
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r-
r=-- Cr~l
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PO.O
-r---
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~
PO.l
PO.2
I
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f-
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1
n.r-I
C
.,...
--
RETURN
"LINES
~
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1
1
r-
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T L~
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PO.3
I
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PO.6
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;.
Pl.0
Pl.l
Pl.2
Pl.3
Pl.4
Pl.S
Pl.6
PH
SCAN
LINES
203830-21
b.) Using Optically-Coupled Isolators
Figure 20. Sensor Matrix Implementation Methods (Continued)
2-65
intJ
AP-70
ilIiiiii iit!t!!!
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I~r-+-+-+-4-4-4-4-~~~-+-+-+-+~----4-~I~+-+-+-4-4-~~---~POO
~+-+-+-4-4-4-4---~~-+-+-+-+~----4-----~+-+-4-4-~~--~po,
~r-+-+-+-4-+-----~~~-+-+-+----+-------~+-+-+-rl-4---~P02
~+-+-+-4-+-------~~-+-+-+----4---------~+-4-4-~--~P03
PO.4
po.s
~+-I-------------~-+----r_----------~+--_l PO.6
~r_--------------......----r_-------------~--_l PO.7
~+-+-+-+---------~~~-+----+-----------o~+-4-4----I
L..-r_r_r_----------....+4-----r_------------o...-+-+--_l
I
I I I I
I 11l1_ _~~~.~
E
eo .•
----------------------1 Pl.S
~-----------------------------------------------------_l Pl.7
L-..--
203830-22
c.) Using TTL Three-State Buffers
Figure 20. Sensor Matrix Implementation Methods (Continued)
AP-70
rrlll!)!
DO 01 02 03 04 05 06 07
nrrnn
rrrri!it
DO 01 02 03 04 05 06 07
74151
C
74151
74151
BAY
S
C' B
A
-
Y 5
C B A
Y S
l~
'--------I---I--+--+--------+-+-+--I-------l PO.O
'----------+-++-+------1 PO.l
'--t-r+rH---t--t--t---+-------i PO.2
4-+-+---Hf----f----l------i PO.3
'-i-t-----+-++-+-------<~ PO.4
I
'-+---+--+--+---+------1
PO.5
'----t-t-t--+------J
'-------J
PO.6
II 11 II 11 Il
' - - - - - - - - - t......-
' - -_ _ _ _ _ _ _......_
1
1
1
1
~-
~
.......-+~_+~_+<~--+4~-H~----<~
.........L -......_
......._
......._
PO.7
......._~~-----_<~
Pl.0
Pl.l
Pl.2
203830-23
d.} Using TTL Data Selectors
Figure 20. Sensor Matrix Implementation Methods (Continued)
2-67
inter
AP-70
venting some artificial design problem, software corre·
sponding to commonplace logic elements will be discussed.
Combinatorial Output Variables. An output variable
,,:,hich is a simple (or not so simple) combinational
function of several input variables is computed in the
spirit of Design Example 3. All 64 inputs are represented in the bit maps: in fact, the sensor numbers in Figure
20 correspond to the absolute bit addresses in RAM!
The code in Example 4 activates an actuator connected
to P2.2 when sensors 12, 23, and 34 are closed and
sensors 45 and 56 are open. .
INITIALIZE MAP
BUFFER POINTERS
AND SCAN MASK
OUTPUT SCAN
MASK TO SCAN
LINES;
STORE SHIFTED
MASK
Example 4.
Simple Combinatorial Output
Variabl~s.
;SET P2.2=(12) (23) (34) ( 45) ( 56)
MOV C,12
ANL C,23
ANL C,34
ANL C, 45
ANL C, 56
MOV P2.2,C
READ RETURN
LINES AND UPDATE
BIT MAPS
Intermediate Variables. The examination of a typical
relay-logic ladder diagram will show that many of the
rungs control not outputs but rather relays whose contacts figure into the computation of other fjlnctions. In
effect, these reiays indicate the state of intermediate
variables of a computation.
The MCS-51 solution can use any directly addressable
bit for the storage of such iptermediate variables. Even
when all 128 bits of the RAM array are dedicated (to
input bit maps in this example), the accumulator, PSW,
and B register provide 18 additional flags for intermediate variables.
203830-24
Figure 21. Flowchart for
Reading in Sensor Matrix
For example, suppose switches 0 through 3 control a
safety interlock system. Closing any of them should deactivate certain outputs. Figure 22 is a ladder diagram
for this situation. The interlock function could be recomputed for every output affected, or it may be computed once and save (as implied by the diagram). As
- the program proceeds this bit can qualify each output.
What happens after the sensors have been scanned depends on the individual application. Rather than in-
2-68
inter
AP-70
Latching Relays. A latching relay can be forced into
either the ON or OFF state by two corresponding input
signals, where it will remain until forced onto the opposite state-analogous to a TTL Set/Reset flip-flop. The
relay is used as an intermediate variable for other calculations. In the previous example, the emergency condition could be remembered and remain active until an
"emergency cleared" button is pressed.
Example 5. Incorporating Override signal into actuator outputs.
CALL INPUT_SCAN
MOV C,O
ORL C,l
ORL C,2
ORL C,3
MOV FO,C
Any flag or addressable bit may represent a latching
relay with a few lines of code (see Example 6).
COMPUTE FUNCTION 0
ANL C, FO
MOV PLO,C
Example 6. Simulating a latching relay.
COMPUTE FUNCTION 1
;I_SET SET FLAG 0 IF C=l
LSET: ORL C,FO
MOV FO,C
ANL C, FO
MOV Pl,l,C
COMPUTE FUNCTION 2
;I_RSET RESET FLAG 0 IF C=l
LRSET: CPS C
ANL C,FO
MOV FO,C
ANL C, FO
MOV Pl,2,C
Time Delay Relays. A time delay relay does not respond to an input signal until it has been present (or
absent) for some predefined time. For example, a ballast or load resistor may be switched in series with a
D.C. motor when it is first turned on, and shunted from
the circuit after one second. This sort of time delay may
be simulated by an interrupt routine driven by one of
the two 8051 timer counters. The procedure followed
by the routine depends heavily on the details of the
exact function needed: time-outs or time delays with
resettable or non-resettable inputs are possible. If the
interrupt routine is executed every 10 milliseconds the
code in Example 7 will clear an intermediate variable
set by the background program after it has been active
for two seconds.
"0"
1
"1"
.--~
I---+-----i
"2"
"3"
Example 7. Code to clear USRFLG after a fixed
time delay.
JNB
DJNZ
CLR
MOV
NXTTST; ,
..
203830-25
Figure 22. Ladder Diagram for
Output Override Circuitry
2-69
USR_FLG,NXTTST
DLAY_COUNT,NXTTST
USR_FLG
DLAY_COUNT,#200
intJ
AP-70
Serial Interface to Remote Processor. When it detects
emergency conditions represented by certain input
combinations (such as the earlier Emergency Override),
the controller could shut down the machine immediately and/or alert the host processor via the serial port.
Code bytes indicating the nature of the problem could
be transmitted to a central computer. In fact, at 17,000
bytes-per-second, the .entire contents of both bit maps
could be sent to the host processor for further analysis
in less than a millisecond! If the host decides that conditions warrant, it could alert other remote processors
in the system that a problem exists and specify which
shut-down sequence each should initiate. For more information on using the serial port, consult the MCS-51
User's ManuaL
A programmed controller which simulates each Boolean function with a subroutine would be less efficient by
at least an order of magnitude. Extra software is needed
for the simulation routines, and each step takes longer
to execute for three reasons: several byte-wide logical
instructions are executed per user program step (rather
than one Boolean operation): most of those instructions
take longer to execute with microprocessors performing
mUltiple off-chip accesses: and calling and returning
from the various subroutines requires overhead for
stack operations.
In fact, the speed of the Boolean Processor solution is
likely to be much faster than the system requires. The
CPU might use the time left over to compute feedback'
parameters, collect and analyze execution statistics,
perfoTm system diagnostics, and so forth.
Response Timing
One difference between relay and programmed industrial controllers (when each is considered as a "black
box") is their respective reaction times to input changes. As reflected by a ladder diagram, relay systems contain a large number of "rungs" operating in paralleL A
change in input conditions will begin propagating
through the system immediately, possibly affecting the
output state within milliseconds.
Software, on the other hand, operates sequentially. A
change in input states will not be detected until the next
time an input scan is performed, and will not affect the
outputs until that section of the program is reached.
For that reason the raw speed of computing the logical
functions is of extreme importance.
Here the Boolean processor pays off. Every instruction
mentioned in this Note completes in one or two microseconds-the minimum instruction execution time for
many other microcontrollers! A ladder diagram containing a hundred rungs, with an average of four contacts per rung can be replaced by approximately five
hundred lines of software. A complete pass through the
entire matrix scanning routine and all computations
would require about a millisecond: less than the time it
takes for most relays to change state.
.
Additional Functions and Uses
With the building-block basics mentioned above many
more operations may be synthesized by short instruction sequences.
Exclusive-OR. There are no common mechanical devices or relays analogous to the Exclusive-OR operation,
so this instruction was omitted from the Boolean
Processor. However, the Exclusive-OR or ExclusiveNOR operation may be performed in two instructions
by conditionally complementing the carry or a Boolean
variable based on the state of any other testable bit.
;EXCLUSIVE-;OR FUNCTION IMPOSED ON CARRY
;USING FO IS INPUT VARIABLE.
;XOR_FO: JNB FO,XORCNT ;("JB" 'FOR X-NOR)
CPL C
;XORCNT: ••••••••
XCH. The contents of the' carry and some other bit may
be exchanged (switched) by using the accumulator as
temporary storage. Bits can be moved into and out of
the accumulator simultaneously using the Rotate-
2-70
inter
AP-70
through-carry instructions, though this would alter the
accumulator data.
;EXCHANGE CARRY WITH USRFLG
XCHBIT: RLC
A
MOV
C,USR_FLG
RRC
A
MOV
USR_FLG,C
RLC
A
Extended Bit Addressing. The 8051 can directly address
144 general-purpose bits for all instructions in Figure
3b. Similar operations may be extended to any bit anywhere on the chip with some loss of efficiency.
Design Example 2 can be extended quite readily to 16
or more bits by using multi-byte input and output buffers.
Many mass data storage peripherals and serial communications protocols include Cyclic Redundancy (CRC)
codes to verify data integrity. The function is generally
computed serially by hardware using shift registers and
Exclusive-OR gates, but it can be done with software.
As each bit is received into the carry, appropriate bits
in the multi-byte data buffer are conditionally complemented based on the incoming data bit. When finished,
the CRC register contents may be checked for zero by
ORing the two bytes in the accumulator.
4.0 SUMMARY
The logical operations AND, OR, and Exclusive-OR
are performed on byte variables using six different addressing modes, one of which lets the source be an immediate mask, and the destination any directly addressable byte. Any bit may thus be set, cleared, or complemented with a three-byte, two-cycle instruction if the
mask has all bits but one set or cleared.
Byte variables, registers, and indirectly addressed RAM
may be moved to a bit addressable register (usually the
accumulator) in one instruction. Once transferred, the
bits may be tested with a conditional jump, allowing
any bit to be polled in 3 microseconds-still much faster than most architectures-or used for logical calculations. (This technique can also simulate additional bit
addressing modes with byte operations.)
Parity of bytes or bits. The parity of the current accumulator contents is always available in the PSW, from
whence it may be moved to the carry and further
processed. Error-correcting Hamming codes and similar applications require computing parity on groups of
isolated bits. This can be done by conditionally complementing the carry flag based on those bits or by gathering the bits into the accumulator (as shown in the DES
example) and then testing the parallel parity flag.
Multiple byte shift and CRC codes
Though the 8051 serial port can accommodat~ eight- or
nine-bit data transmissions, some protocols involve
much longer bit streams. The algorithms presented in
A truly unique facet of the Intel MCS-51 microcomputer family design is the collection of features optimized
for the one-bit operations so often desired in real-world,
real-time control applications. Included are 17 special
instructions, a Boolean accumulator, implicit and direct
addressing modes, program and mass data storage, and
many I/O options. These are the world's first singlechip microcomputers able to efficiently manipulate, operate on, and transfer either bytes or individual bits as
data.
This Application Note has detailed the information
needed by a microcomputer system designer to make
full use of these capabilities. Five design examples were
used to contrast the solutions allowed by the 8051 and
those required by previous architectures. Depending on·
the individual application, the 8051 solution will be easier to design; more reliable to implement, debug, and
verify, use less program memory, and run up to an order of magnitude faster than the same function implemented on previous digital computer architectures.
Combining byte- and bit-handling capabilities in a single microcomputer has a strong synergistic effect: the
power of the result exceeds the power of byte- and bitprocessors laboring individually. Virtually all user applications will benefit in some way from this duality ..
Data intensive applications will use bit addressing for
test pin monitoring or program control flags: control
applications will use byte manipulation for parallel I/O
expansion or arithmetic calculations.
It is hoped that these design examples give the reader
an appreciation of these unique features and suggest
ways to exploit them in his or her own application.
2-71
ISIS-II MCS-51'MACRO ASSEMBLER VI.O
MODULE PLACED IN FO AP70 HEX
ASSEMBLER INVOKED BY'
F1.asm51 ap70 sre
LOC OB~
LINE
SOURCE
l
OB~ECT
2
d~te(328)
$XREF TITLE(AP-70 APPENDIX)
.********************************************************
3
4
THE FOLLOWING PROGRAM USES THE BOOLEAN INSTRUCTION SET
OF THE INTEL E051 MICROCOMPUTER TO PERFORM A ~UMBER OF
AUTOMOTIVE DASHBOARD CONTROL FUNCTIONS RELATING TO
TURN SIGNAL CONTROL. EMERGENCY BLINKERS. BRAKE LIGHT
CONTROL. AND PARKING LIGHT OPERATION.
THE ALGORITHMS AND HARDWARE ARE DESCRIBED IN DESJGN
EXAMPLE .4 OF INTEL. APpLICATION NOTE AP-70.
"USING THE INTEL MCS-51<
m.
35'»
a.
1_.
-·n
!Lm
-.-
::so
cc-.
INTERNAL VARIABLE.DEFINITIONS·
SUB DIV DATA
HI_FREG BIT
LO_FREG. BIT
20H
SUB DIV 0
SUB_DIV 7
INTERRUPT·RATE SUBDIVIDER
HIGH-FREGUENCY OSCILLATOR BIT
LOW-FREGUENCY OSCILLATOR BIT'
DIM
PSW I
PARKING LIGHTS ON FLAG
BIT
&0»
~2:"'O
m
.........
z
Oce
OUTPUT PIN DECLARATIONS'
(ALL OUTPUTS ARE POSITIVE TRUE LOGIC
BULB IS TURNED ON'WHEN OUTPUT PIN IS HIGH. )
BIT
BIT
BIT
BIT
BIT
BIT
-0
"'OCD
BRAKE PEDAL DEPRESSED
EMERGENCY BLINKER ACTIVATED
PARKING LIGHTS ON
TURN LEVER DOWN
TURN LEVER UP
L_FRNT
RJRNT
L_DASH
R_DASH
L_REAR
R_REAR
::s-
"'3
i**"'**************************************.*********** ****
BRAKE
EMERG
PARK
L_TURN
R_TURN
0»
Or::
j===================================================== ==
$E~ECT
203830-26
»
l'
.....
o
LOC
ODJ
0000 020040
0000
OOOB 7:18CFO
OOOE CODO
0010 0154
0040
0040 758AOO
0043 758CFO
0046 758961
0049
004C
004E
0050
0052
7520F4
D2A9
D2AF
D28C
80FE
0054 D52038
0057 7520F4
I\)
~
005A 4390EO
005D 43A007
0060 C295
0062 20S428
0065 D295
0067 C297
0069 208421
006C D297
006E C2Al
0070 20B41A
0073 D2Al
0075 C296
0077 20B413
007A D296
007C C2AO
007E 20B40C
0081 D2AO
00B3 C2A2
00B5 20B405
OOBB D2A2
LINE
l
SOURCE
49
50
51
ORG
LJMP
OOOOH
INIT
RESET VECTOR
5~
ORG
MOV
PUSH
AJMP
OOOBH
THO. 11-16
PSW
UPDATE
TIMER 0 SERVICE VECTOR
HIGH TIMER BYTE ADJUSTED TO CONTROL INT RATE
EXECUTE CODE TO SAVE ANY REGISTERS USED BELOW
(CONTINUE WITH REST OF ROUTINE)
ORG
MOV
MOV
MOV
0040H
TLO.1I0
THO.1I-16
TMOD.1I01100001B
53
54
55
56
57
5B
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
7B
INIT
UPDATE
79~
BO
Bl
B2
B3
84
85
B6
87
BB
B9
90
91
~
MOV
SETB
SETB
SEHI
SJMP
SUB_DIV.1I244
ETO
EA
TRO
DJNZ
MOV
SUB_DIV. TOSERV
SUB_DIV.1I244
ORL
ORL
CLR
JB
SETB
CLR
JB
SETB
CLR
JB
SETB
CLR
JB
SETB
CLR
JB
SETB
CLR
JB
SETB
PI.llll100000B
P2.1I00000IIIB
L_FRNT
TO. FAULT
L_FRNT
L_DASH
TO. FAULT
L_DASH
L_REAR
TO. FAULT
L_REAR
RJRNT
TO. FAULT
R_FRNT
R DASH
TO. FAULT
R_DASH
R_REAR
TO. FAULT
R_REAR
$
ZERO LOADED INTO LOW-ORDER BYTE AND
-16 IN HIGH-ORDER BYTE GIVES 4 MSEC PERIOD
B-BIT AUTO RELOAD COUNTER MODE FOR TIMER I.
16-BIT TIMER MODE rOR TIMER 0 SELECTED
SUBDIVIDE INTERRUPT RATE BY 244 FOR I HZ
USE TIMER 0 OVERFLOWS TO INTERRUPT PROGRAM
CONFIGURE IE TO GLOBALLY ENABLE INTERRUPTS
'KEEP INSTRUCTION CYCLE COUNT UNTIL OVERFLOW
START BACKGROUND PROGRAM EXECUTION
EXECUTE SYSTEM TEST ONLY ONCE PER SECOND
GET VALUE FOR NEXT ONE SECOND DELAY AND
GO THROUGH ELECTRICAL SYSTEM TEST CODE
SET CONTROL OUTPUTS HIGH
l>
."
I
......
FLOAT DRIVE COLLECTOR
TO SHOULD BE PULLED LOW
PULL COLLECTOR BACK DOWN
REPEAT SEQUENCE FOR L_~DASH.
o
L REAR.
R_FRNT.
R__ DASH.
AND R _REAR
92
aOSA 200402
OOBD B2A3
93
94
95
96
97
98
99 +1
WITH ALL COLLECTORS GROUNDED. TO SHOULD BE HIGH
IF 50. CONTINUE WITH INTERRUPT ROUTINE
FAULT~
JB
CPL
TO. TOSERV
S_FAIL
ELECTRICAL FAILURE PROCESSING ROUTINE
(TOGGLE INDICATOR ONCE PER SECOND)
SEJECT
203830-27
_.
LOC
OB.!
008F
0091
0093
0095
0097
A201
8200
7202
B292
92Dl
0099
009B
009D
009F
A293
7291
8207
9297
OOAI 92D5
00A3 7201
00A5 9295
I\J
~
00A7
00A9
OOAB
OOAD
OOAF
00B1
00B3
00B5
00B7
OOB?
OOBB
OOBD
OOBF
00C1
00C3
00C5
00C7
A2?0
BO'13
7205
72D1
92Al
A294
72'11
8207
?2AO
'1205
7201
?2?b
A2?O
BO?4
72D5
72DI
92A2
OOC? DODO
OOCD 32-
LINE
100
101
102
103
104
105
lOb
107
108
109
110
III
112
113
114
115
lib
117
liB
119
120
121
122
123
124
125
SOURCE
TOSERV.
2)
3)
143
144
145
14b
147
148
14'1
150
:51
MOV
ANL
ORL
ANL
MOV
4)
START WITH 50 PERCENT.
MASK DOWN TO 25 PERCENT.
BUILD BACK TO b2. 5 PERCENT.
GATE WITH PARKING LIGHT SWITCH.
AND SAVE IN TEMP. VARIABLE
C. L_TURN
C.EMERG
C.LO_FREQ
L_DASH.C
SET CARRY IF TURN
OR EMERGENCY SELECTED.
IF SO. 'GATE IN 1 HZ SIGNAL
AND OUTPUT TO DASHBOARD
COMPUTE AND OUTPUT LEFT-HAND FRONT TURN SIGNAL
FO.C
C.DIM
L_FRNT. C
SAVE FUNCTION SO FAR
ADD IN PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL
COMPUTE AND OUTPUJ LEFT-HAND REAR TURN SIGNAL
MOV
ANL
ORL
ORL
MOV
5)
C. SUB_DIV I
C. SUB_DIV 0
C.SUB_DIV 2
C.PARK
DIM.C
t
COMPUTE AND OUTPUT LEFT-HAND DASHBOARD INDICATOR
MOV
ORL
MOV
128
142
COMPUTE LOW BULB INTENSITY WHEN PARKING LIGHTS ARE ON
MOV
ORL
ANL
MOV
126
127
129
130
131
132
133
134
135
13b
137
138
139
140
141
II
CONTINUE WITH INTERRUPT PROCESSING
1>
C.BRAKE
C./L_TURN
C.FO
C.DIM
L_REAR. C
II
GATE BRAKE PEDAL SWITCH
WITH TURN LEVER
INCLUDE TEMP VARIABLE FROM DASH
AND PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.
REPEAT ALL OF ABOVE FOR RIGHT-HAND COUNTERPARTS
MOV
ORL
ANL
MOV
MOV
ORL
MOV
MOV
ANL
ORL
ORL
MOV
C. R_TURN
C.EMERG
C. LO_FREQ
R_DASH.C
FO.C
C.DIM
R FRNT. C
C:-ORAKE
C./R_TURN
C.FO
C.DIM
R_REAR. C
SET CARRY IF TURN
OR EMERGENCY SELECTED
IF SO. GATE IN I HZ SIGNAL
AND OUTPUT TO DASHBOARD.
SAVE FUNCTION SO FAR.
ADD IN PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.
GATE BRAKE PEDAL SWITCH
WITH TURN LEVER
INCLUDE TEMP VARIADLE FROM DASH
AND PARKING LIGHT FUNCTION
AND OUTPUT TO TURN SIGNAL.
RESTORE STATUS REGISTER AND RETURN
POP
RETI
PSW
RESTORE PSW
AND RETURN FROM INTERRUPT ROUTINE
END
203830-28
»
"U
I
"'0 "
_.
t
XREF SYMBOL TABLE LISTING
NAME
I\)
.!.J
01
TYPE
BRAKE
N BSEG
DIM
N BSEG
EA
N BSEG
EMERG
N BSEG
ETO
N BSEG
FO
N BSEG
FAULT
L CSEG
HI_FRECl N BSEG
INlT
L CSEG
N BSEG
L_DASH
L_FRNT
N BSEG
L_REAR.
N IlSEG
L_TURN
N IlSEG
LO_FRECl "N IlSEC
PI
N DSEG
P2
N DSEG
PARK
N IlSEG
PSW
N DSEG
R_DASH
N IlSEG
N BSEG
RJRNT
R_REAR
N BSEG
R_TURN
N IlSEG
SJAIL.
N IlSEG
SUB_DIV N DSEG
TO
N IlSEG
TOSERV
L CSEG
THO
N DSEG
TLO
N DSEG
TMOD
N DSEG
TRO
N BSEG
UPDATE
L CSEG
VALUE AND REFERENCES
0090H
. OODIH
OOAFH
0091H
00A9H
00D5H
OOBDH
OOOOH
0040H
0097H
0095H
OOAIH
0093H
0007H
0090H
OOAOH
0092H
OODOH
OOAOH
0096H
OOA2H
0094H
00A3H
ASSEMBLY COMPLETE.
204* 125 140
4511 lOB 120 12B 13B 143
611
2111 113 134
63
119 127 137 142
75 7B BI B4 B7 90 9711
42.
50 5BII
3211 77 79 115
30 .. 74 76 121
34 .. 80 82 129
23. 112 126
4311 114 135
20 21 22 23 24 30 31 32 72
33 34 35 37 73
22.. 107
45 54 14B
3311 B6 BB 136
3U B3 B5 139
3511 B9 91 144
2411 133 141
3711 97
l>
II
0020H
41 .. 42 43 62 69 70 104 105 106
00B4H
OOBFH
OOBCH
OOBAH
00B9H
OOBCH
00548
75
69
53
5B
60
65
55
7B Bl B4 B7 90 96
96 10411
59
6911
NO ERRORS FOUND
203830-29
"'CI
I
.....
0
APPLICATION
NOTE
AP-223
October 1984
~INTEL
CORPORATION, 1984
2-76
ORDER NUMBER: 270032-001
Ap·223
1.0 INTRODUCTION
This is the third application note that Intel has produced
on CRT terminal controllers. The first Ap Note (ref. I),
written in 1977, used the 8080 as the CPU and required
41 packages including 11 LSI devices. In 1979, another
application note (ref. 2) using the 8085 as the controller
was produced and the chip count decreased to 20 with 11
LSI devices.
br-------,
--~-------t
Advancing technology has integrated a complete system
onto a single device that contains a CPU, program memory, data memory, serial communication, interrupt controller, and lIO. These "computer-on-a-chip" devices are
known as microcontrollers. Intel's MCS®-51 microcontroller was chosen for this application because of its highly
integrated functions. This CRT terminal design uses 12
packages with only 4 LSI devices.
This application note has been divide" into five general
sections:
1) CRT Terminal Basics
2) 8051 Description
3) 8276 Description
4) Design Background
5) System Description
2.0 CRT TERMINAL BASICS
A terminal provides a means for humans to communicate
with a computer. Terminals may be as simple as a LED
display and a couple of push buttons, or it may be an
elaborate graphics system that contains a full function
keyboard with user programmable keys, color CRT and
several processors controlling its functions. This application note describes a basic low cost terminal containing
a black and white CRT display, full function keyboard
and a serial interface.
2.1
CRT Description
A raster scan CRT displays its images by generating a
series of lines (raster) across the face of the tube. The
electron beam usually starts at the top left hand comer
moves left to right, back to the left of the screen, moves
down one row and continues on to the right. This is repeated until the lower right hand of the screen is reached.
Then the beam returns to the top left hand corner and
refreshes the screen. The beam forms a zigzag pattern as
shown in Figure 2.1.0.
Two independent operating circuits control this movement
across the screen. The horizontal oscillator controls the
left to right motion of the beam while the vertical controls
the top to bottom movement. The vertical oscillator also
tells the beam when to return to the upper left hand comer
or "home" position.
.
-
Figure 2.1.0
-
RETRACE LINES
DISPLAYED LINES
Raster Scan
As the electron beam moves across the screen under the
control of the horizontal oscillator, a third circuit controls
the current entering the electron gun. By varying the current, the image may be made as bright or as dim as the
user desires. This control is also used to tum the beam
off or "blank the screen".
When the beam reaches the right hand side of the screen,
the beam is blanked so it does not appear on the screen
as it returns to the left side. This "retrace" of the beam
is at a much faster rate than it traveled across the screen
to generate the image.
The time it takes to scan the whole screen and return to
the home position is referred to as a, "frame". In the
United States, commercial television broadcast uses a horizonal sweep frequency of 15,750Hz which calculates out
to 63.5 microseconds per line. The frame time is equal
to 16.67 milliseconds or 60Hz vertical sweep frequency.
Although this is the commercial standard, many CRT displays operate from 18KHz to 30KHz horizonatal frequency. As the horizontal frequency increases, the number
of lines per frame increases. This increase in lines or
resolution is needed for graphic displays and on special
text editors that display many more lines of text than the
standard 24 or 25 character lines.
Since the United States operates on a 60Hz A.C. power
line frequency, most CRT monitors use 60Hz as the vertical frequency. The use of 60Hz as the vertical frequency
allows the magnetic and electrical variations that can modulate the electron beam to be synchronized with the display, thus they go unnoticed. If a frequency other than
60Hz is used, special shielding and power supply regu-
2-77
AP·223
lating is usually required. Very few CRTs operate on a
vertical frequency other than 60Hz due to the increase in
the overall system,cost.
The following equation can be used to figure 'the number
of lines per frame:
L=(H*Z)+V
The CRT controller must generate the pulses that define
the horizontal and vertical timings. On most raster scan
CRTs the horizontal frequency may vary as much as
500Hz without any noticeable effect on the quality of the
display. This variation can change the number of horizontal lines from 256 to 270 per frame.
The CRT controller must also shift out the information to
be displayed serially to the circuit that controls the electron·
beam's intensitY as it scans across the screen. The circuits
that control the timing associated with the shifting of the
information are known as the dot clock and the character
clock. The character clock frequency is equal to the dot
clock frequency divided by the number of dots it takes to
form a character in the horizontal axis. The dot clock
frequency is calculated by the following equation:
Dot Clcok (Hz) = (N + R)*D*L *F
where
N is the number of displayed characters per row,
R is the number of character times for the retrace,
D is the number ·of dots per character in the horizontal axis,
L is the number of horizontal lines per frame,
F is the frame rate in Hz.'
In this design N = 80, R = 20, D = 7, L = 270, and
F = 60Hz. Plugging in the numbers results in a dot clock
frequency of 11.34MHz.
The retrace number may vary on each design because it
is used to set the left and right hand margins on the CRT.
The number of dots per character is chosen by the designer
to meet the system needs. In this design, a 5 x 7 dot matrix
and 2 blank dots between each character (see Figure 2.1.1)
makes D equal to 5+2=7.
where
H is the number of horizontal lines per character,
Z is the number of character lines per frame,
V ,is the number of horizontal line times during the
vertical retrace
In this design H is equal to the 7 horizontal dots per
character plus 3 blank dots between each row which adds
up to 10. Also 25 lines of characters are displayed, so
Z = 25. The vertical retrace time is variable to set the top
and bottom margins on the CRT and in this design is equal
. to 20. Plugging in the numbers gives L=270 lines per
frame.
2.2 Keyboard
A keyboard is the common way a human enters commands
and data to a computer. A keyboard consists of a matrix
of switches that are scanned every couple of milliseconds
by a keyboard controller to determine if one of the keys
has been pressed. Since the keyboard is made up of mechanical switches that tend to bounce or "make and
break" contact everytime they are pressed, debouncing
of the switches must also be a function of the keyboard
controller. There are dedicated keyboard controllers
available that do everything from scanning the keyboard,
deb~uncing the keys, decoding the ASCII code for that
key closure to flagging the CPU that a valid key has been
depressed. The keyboard controller may present the information to the CPU in parallel form or in a serial data
stream.
This Application Note integrates the function of the keyboard controller into the 8051 which.is also the terminal
controller. Provisions have been made to interface the
8051 to a keyboard that uses a dedicated keyboard controller. The 8051 can accept data from the keyboard controller in either parallel or serial format.
2.3 Serial Communications
Communication between a host computer and the CRT
terminal can be in either parallel or serial data format.
Parallel data transmission is needed in high end graphic
terminals where great amounts of information must be
transferred.
Figure 2.1.1
5 x 7 Dot Matrix
One can rarely type faster than 120 words per minute,
which corresponds to 12 characters per second or 1 character per 83 milliseconds. The utilization of a parallel port
cannot justify the cost associated with the drivers and the
amount of wire needed to perform this transmission. Full
duplex serial data transmission requires 3 wires and. two
AP-223
IICC
r----------
-------------,
I
I
I
~
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Figure 3.0.0
________
Vee
P1.1
PO.O/ADO
PO.I/ADI
PO.21AD2
PO.31AD3
PO.4/AD4
PO.S/ADS
Pl.3
Pl.4
Pl.5
Pl.6
Pl.7
RST
P3.0/RXD
P3.11TXD
P3.21INTO
P3.311NTI
P3.41TO
P3.51TI
I
~_,/l_"="_'
Pl.0
P1.2
P3.6JWR
P3.7/Ro
XTAL2
XTALI
VSS
PO.61AD6
PO.7/AD7
EAtvPP
ALElPRDG
PSEN
P2.7/A15
P2.61AI4
P2.5/A13
P2.4/A12
P2.31All
P2.21AI0
P2.1/A9
P2.0/A8
JI
8051 Block Diagram
3.1
drivers to implement the communication channel between
the host computer and the terminal. The data rate can be
as high as 19200 BAUD in the asynchronous serial format.
BAUD rate is the number of bits per second received or
transmitted. In the asynchronous serial format, 10 bits of
information is required to transmit one character. One
character per 500 microseconds or 1,920 characters per
second would then be trasmitted using 19.2 KBAUD.
CPU
Efficient use of program memory results from an instruction set consisting of 49 single-byte, 45 two-byte and 17
three-byte instructions. Most arithmetic, logical and
branching operations can be performed using an instruction that appends either a short address or a long address.
For example, branches may use either an offset that is
relative to the program counter which takes two bytes or
a direct 16-bit address which takes three bytes to perform.
As a result, 64 instructions operate in one machine cycle,
45 in two machine cycles, and the multiply and divide
instruction execute in 4 machine cycles.
This application note uses the 8051 serial port configured
for full duplex asynchronous serial data transmission. The
software for the 8051 has been written to support variable
BAUD rates from ISO BAUD up to 9.6 KBAUD.
3.0 8051 DESCRIPTION
The 8051 is a single chip high-performance microcontroller. A block diagram is shown in figure 3.0.0. The
8051 combines CPU; Boolean processor; 4K x 8 ROM:
128 x 8 RAM; 32 110 lines; two 16-bit timer/ event.
counters; a five-source, two-priority-level, nested interrupt structure; serial I/O port for either mUltiprocessor
communications, I/O· expansion, or full duplex UART;
and on-chip oscillator and clock circuits.
The 8051 has five addressing modes for source operands:
Register, Direct, Register-Indirect, Immediate, and
Based-Register-plus Index-Register-Indirect Addressing.
The Boolean Processor can be thought of as a separate
one-bit CPU. It has its own accumulator (the carry bit),
instruction set for data moves, logic, and control transfer,
and its own bit addressable RAM and 110. The bitmanipulating instructions provide optimum code and
speed efficiency for handling on chip peripherals. The
2-79
AP-223
Boolean processor also provides a straight forward means
of converting logic equations directly into software.' Complex combinational logic functions can be resolved without
extensive data movement, byte masking, and test-andbranch trees.
and RXD pins and to generate control signals used for
writing and reading external peripherals.
3.4 Interrupt System
External events and the real-time-driven on-chip peripherals require service by the CPU asynchronous to the execution of any particular section of code. A five-source,
two-level, nested interrupt system ties the real time events
to the normal program execution.
3.2 On-Chip Ram
The CPU manipulates operands in four memory spaces.
These are the 64K-byte Program Memory, 64K-byte External Data Memory, I 28-byte Internal Data Memory, and
128-byte Special Function Registers (SFRs). Four Register Banks (each with 8 registers), 128 addressable bits,
and the Stack reside in the internal Data RAM. The Stack
size is limited only by the available Internal Data RAM
and its location is determined by the 8-bit Stack Pointer.
All registers except for the Program Counter and the four
8-Register Banks reside in the SFR address space. These
memory mapped registers include arithmetic registers,
pointers, I/O ports, and registers for the interrupt system,
timers, and serial channel.
The 8051 has two external interrupt sources, one interrupt
from each of the two timer/counters, and an interrupt from
the serial port. Each interrupt vectors the program execution to its own unique memory location for servicing
the interrupt. In addition, each of the fi~e sources can be
individually enabled or disabled as well as assigned to
one of the two interrupt priority levels available on the
8051.
Up to two additional external interrupts can be created by
configuring a timer/counter to the event counter mode. In
this mode the timer/counter increments on command by
either the TO or Tl pin.' An interrupt is generated when
the timer/counter overflows. Thus if the timer/counter is
loaded with the maximum count, the next high-to-Iow
transition of the event counter input will cause an intenupt
to be generated.
Registers in the four 8-Register Banks can be addressed
by Register, Direct, or Register-Indirect Addressing
modes. The 128 bytes of internal Data Memory can be
addressed by Direct or Register-Indirect modes while the
SFRs are only addressed directly.
3.3 1/0 Ports
3.5 Serial Port
The 8051 has instructions that can treat the 32 I/O lines
as 32 individually addressable bits or as 4 parallel 8-bit
ports addressable as Ports 0, 1,2, and 3.
Resetting the 8051 writes a logical 1 to each pin on port 0
which places the output drivers into a high-impedance
mode. Writing a logical 0 to a pin forces the pin to ground.
and sinks current. Re-writing the pin high will place the
pin in either an open drain output or high-impedance input
mode.
Ports 1, 2, and 3 are known as quasi-bidirectional I/O
pins. Resetting the device writes a logical one to each pin.
Writing a logical 0 to the pin will force the pin to ground
and sink current. Re-writing the pin high will place the
pin in an output mode with a weak depletion pullup FET
or in the input mode. The weak pullup FET is easily
overcome by a TTL output ..
Ports 0 and 2 can also be used for off-chip peripheral
expansion. Port 0 provides a multiplexed low-order address and data bus while Port 2 contains the high-order
address when using external Program Memory or more
than 256 byte external Data Memory.
Port 3 pins can also be used to provide external interrupt
request inputs, event cpunier inputs, the serial port TXD
The 8051' s serial port is useful for linking peripheral devices as well as multiple 8051 s through standard asynchronous protocols with full duplex operation. The serial
port also has a synchronous. mode for expansion of I/O
lines using shift registers. This hardware serial port saves
ROM code and permits a much higher transmission rate
than could be achieved through software. The processor
merely needs to read or write the serial buffer in response
to an interrupt. The receiver is double buffered to eliminate
the possibility of overrun if the processor failed to read
the buffer before the beginning of the next frame.
The full duplex asynchronous serial port provides the
means of communication with standard UART devices
such as CRT terminals.and printers.
The reader should refer to the microcontroller handbook
for a complete discussion of the 8051 and its various
modes of operation.
4.0 8276 DESCRIPTION
The 8276's block diagram and pin configuration are shown
in Figure 4.0.0. The following sections describe the general capabilities of the 8276.
2-80
AP-223
LC3
LC2
LC1
LCO
BDRY
DATA
BUS
BUFFER
US
UNE
COUNTER
ROW
COUNTER
MRTC
VRTC
MLGT
RVV
LTEN
VSP
RASTER TIMING
AND
VIDEO CONTROL
Figure 4.0.0
4.1
HRTC
VRTC
ltD
WR
NC
DBa
DB1
DB2
DB3
DB4
DBs
DBs
DB7
GND
VCC
NL
NC
LTEN
RVV
VSP
GPA1
GPAo
HLGT
INT
CCLK
CC6
CCs
CC4
CC3
CC2
CC1
CCo
C!
C/P
8276 Block Diagram
CRT Display Refreshing
is used by the 8051 system controller to reinitialize its
load buffer pointers for the next display refresh cycle.
The 8276, having been programmed by the system designer for a specific screen format, generates a series of
Buffer Ready signals. A row of characters is then transferred by the system controller from the display memory
to the 8276's row buffers. The row buffers are filled by
deselecting the 8276 CS and asserting the BS and WR
signals. The 8276 presents the character codes to an external character generator ROM by using outputs
CCO-CC6. The parallel data from the outputs of the character generator is converted to serial information that is
clocked by external dot timing logic into the video input
of the CRT.
Proper CRT refreshing requires that certain 8276 parameters be programmed at system initialization time. The
8276 has two types of internal registers; the write only
Command (CREG) and Parameter (PREG) Registers, and
the read only Status Register (SREG). The 8276 expects
to receive a command followed by 0 to 4 parameter bytes
depending on the command. A summary of the 8276's
instruction set is shown in Figure 4.1:1. To access the
registers, CS must be asserted along with WR or RD. The
status of the C/P pin determines whether the command or
parameter registers are selected.
The character rows are displayed on the CRT one line at
a time. Line count outputs LCO-LC3 select the current
line information from the character generator ROM. The
display process is illustrated in Figure 4.1.0. This process
is repeated for each display character row. At the beginning of the last display row the 8276 generates an interrupt
request by raising its INT output line. The interrupt request
The 8276 allows the designer flexibility in the display
format. The display may be from I to 80 characters per
row, I to 64 rows per screen, and 1 to 16 horizontal lines
per character row. In addition, four curser formats are
available; blinking, non-blinking, underline, and reverse
video. The curser position is programmable to anywhere
on the screen via the Load Curser command.
2-81
AP-223
1st
Character
2nd
Character
3,d
Character
4th
Character
5th
Character
6th
Character
7th
Character
5th
Character
6th
Character
7th
Character
First Line of a Character Row
1st
Character
2nd
Character
3,d
Character
4th
Character
oo ••• ooo.ooo.oo ••••• oooooooob •••• oooo ••• ooo.ooo.o
0.000.00 •• 00.00.0000000000000.000.00.000.00.000.0
Second Line of a Character Row
1st
Character
2nd
Character
3,d
Character
5th
Character
6th
Character
7th
Character
4th
5th
Charlcter
Character
6th
Character
Character
4th
Character
Third Line of a Character Row
•
••
1st
2nd
Character
Character
3rd
Character
7th
Seventh Line 01 a Character Row
Figure 4.1.0
8276 Row Display
4.2 CRT Timing
The 8276 provides two timing outputs for controlling the
CRT. The Horizontal Retrace Timing and Control (HRTC)
and Vertic·al Retrace Timing and Control (VRTC) signals
are used for synchronizing the CRT horizontal and vertical
oscillators. A third output, VSP (Video Suppress), provides a signal to the dot timing logic to blank the video
signal during the horizontal and vertical retraces. LTEN
(Light Enable) is used to provide the ability to force the
video output high regardless of the state of the VSP signal.
This feature is used to place the cursor on the screen and
to control attribute functions.
RVV (Reverse Video) output, if enabled, will cause the
system to invert its video output. The fifth timing signal
output, HLGT (highlight) allows the flexibility to increase
the CRT beam intensity to a greater than normal level.
2-82
AP-223
COMMAND
NO. OF
PARAMETER
BYTES
NOTES
RESET
4
Display format
parameters required
START
DISPLAY
0
DMA operation
parameters included in
command
STOP
DISPLAY
0
-
RED LIGHT
PEN
2
-
LOAD
CURSOR
2
ENABLE
INTERRUPT
0
-
DISABLE
INTERRUPT
0
-
PRESET
COUNTERS
0
Figure 4.1.1
Cursor X, Y position
parameters required
4.3.4
Clears all internal
counters
8276 Instruction Set
Special Codes
The 8276 recognizes four special codes that may be used
to reduce memory, software, or system controller overhead. These characters are placed within the display memory by the system controller. The 8276 performs certain
tasks when these codes are received in its row buffer
memory.
1) End of Row Code - Activates VSP. VSP remains
active until the end of the line is reached. While VSP
is active the screen is blanked.
2) End Of Row-Stop Buffer Loading Code - Causes the
Buffer Ready control logic to stop requesting buffer
" transfers for the rest of the row. It affects the display
the same as End of Row Code.
3) End Of Screen Code - Activates VSP. VSP remains
active until the end of the frame is reached.
Programmable Buffer Loading
Control
The 8276 can be programmed to request 1, 2, 4, or 8
characters per Buffer load. The interval between loads is
also programmable. This allows the designer the flexibility
to tailor the buffer transfer overhead to fit the system
needs.
Each scan line "requires 63.5 microseconds. A character
line consists of 10 scan lines and takes 635 microseconds
to form. The 8276 row buffer must be filled within the
635 microseconds or an under run condition will occur
within the 8276 causing the screen to be blanked until the
next vertical retrace. This blanking will be seen as a flicker
in the display.
5.0
4.3 Special Functions
4.3.1
4) End Of Screen-Stop Buffer Loading Code - Causes
the Buffer Ready control logic to stop requesting buffer
transfers until the end of the frame is reached. It affects
the display the same way as the End of Screen code.
DESIGN BACKGROUND
A fully functional, microcontroller-based CRT terminal
was designed and constructed using the 8051 and the 8276.
The terminal has many of the functions that are found in
commercially available low cost terminals. Sophisticated
"features such as programmable keys can be added easily
with modest amounts of software.
The 8051 's functions in this application note include: up
to 9.6K BAUD full duplex serial transmission; decoding
special messages sent from the host computer; scanning,
debouncing, and decoding a full function keyboard; writing to the 8276 row buffer from the display RAM without
the need for a DMA controller; and scrolling the display.
The 8276 CRT controller's functions include: presenting
the data to the character generator; providing the timing
signals needed for horizontal and vertical retrace; and providing blanking and video information.
5.1
Design Philosophy
Since the device count relates to costs, size, and reliability
of a system, arriving at a minimum device count without
degrading the performance was a driving force for this
application note. LSI devices were used where possible
to maintain a low chip count and to make the design cycle
as short as possible.
PUM-51 was chosen to generate the majority of the "software for this application because it models the human
thought process more closely than assembly language.
Consequently it is easier and faster to write programs using
PLlM-51 and the code is more likely to be correct because
less chance exists to introduce errors.
2-83
AP-223
PUM-51 programs are easier to read and follow than
assembly language programs, and thus are easier to modify and customize to the end user's application. PUM-51
also offers lower development and maintenance costs than
assembly language programming.
PUM-51 does have a few drawbacks. It is not as efficient
in code generation relative to assembly language and thus
may also run slower.
This application note uses'the 8051's interrupts to control
the servicing of the various peripherals. The speed of the
main program is less critical if interrupts are used. In the
last two application notes on terminal controllers, a criterion of the system was the time required for receiving
an incoming serial byte, decoding it, performing the function requested, scanning the keyboard, debouncing the
keys, and transmitting the decoded ASCII code must be
less than the vertical refresh time. Using the 8051 and its
interrupts makes this time constraint irrelevant.
5.2
System Target ,Specifications
The design specifications for the CRT terminal design is
as follows:
Characters Transmitted
•
•
•
•
Display Memory
• 2K x 8 static RAM
Data Rate
• Variable rate from 150 to 9600 BAUD
CRT Monitor
• Ball Bros TV-12, 12MHZ Black and White
Keyboard
• Any standard undecoded keyboard (2 key lock-out)
• Any standard decoded keyboard with output enable pin
• Any standard decoded serial keyboard up to 150 BAUD
Scrolling Capability
Compatible With Wordstar
Display Format
6.0
• 80 characters/display row
• 25 display lines
5 x 7 character contained within a 7 x 10 frame
First and 'seventh columns blanked
Ninth line curser position
Programmable delay blinking underline curser
The "brains" of the CRT terminal is the 8051 microcontroller. The 8276 is the CRT controller in the system, and
a 2716 EPROM is used as the character generator. To
handle the high speed portion of the CRT, the 8276 is
surrounded by a handful of TTL devices. A 2K x 8 static
RAM was used as the display memory.
Control Characters Recognized
•
•
•
•
Backspace
Linefeed
Carriage Return
Form Feed
I
Following the system reset, the 8276 is initialized for
curser type, number of characters per line, number of
lines, and character size. The display RAM is initialized
to all "spaces" (ASCII 20H). The 8051 then writes the
"start display" command to the 8276. The localliine input
is sampled to determine the terminal mode. If the terminal
is on-line, the BAUD rate switches are read and the serial '
port is set up for full duplex UART mode. The processor
then is put into a loop waiting to service the serial port
fifo or the 8276.
Escape Sequences 'Recognized
•
•
•
•
•
•
.•
•
•
ESC
ESC
ESC
ESC
ESC
ESC
ESC
ESC
ESC
SYSTEM DESCRIPTION
A block diagram of the CRT terminal is shown in figure
6.0.0. The diagram shows only the essential system features. A detailed schematic of the CRT terminal is contained in the Appendix 7. I.
Character Format
•
•
•
•
96 ASCII Alphanumeric Characters
ASCII Control Character Set
ASCII Escape Sequence Set
Auto Repeat
A, Curser up
B, Curser down
C, Curser right
D, Curser left
E, Clear screen
F, Move addressable curser
H, Home curser
J, Erase from curser to the end the screen
K, Erase the current line
The serial port is programmed to have the highest priority
interrupt. If the serial port generates an interrupt, the processor reads the buffer, puts the character in a generated
fifo that resides in the 8051's internal RAM, increments
the fifo pointer, sets the serial interrupt flag and returns.
Characters Displayed
• 96 ASCII Alphanumeric Characters
2-84
AP-223
SERIAL
COMMUNICATIONS
CHANNEL
Figure 6.0.0 CRT Terminal Controller Block Diagram
The main program determines if it is a displayable character, a Control word or an ESC sequence and either puts
the character in the display buffer or executes the appropriate command sent from the host computer.
If the 8276 needs servicing, the 8051 fills the row buffer
for the CRT display's next line. If the 8276 generates a
vertical retrace interrupt, the buffer pointers are reloaded
with the display memory location that corresponds to the
first character of the first display line on the CRT. The
vertical retrace also signals the processor to read the keyboard for a key closure.
.
6.1
Three general cases can be explored; reading and writing
the display RAM, writing to the 8276 row buffers, and
reading and writing the 8276's control registers.
As mentioned previously the 8051 fills the 8276 row buffer
without the need of a DMA controller. This is accomplished by using a Quad 2-input mUltiplexor (Figure 6.1.0)
as the transfer logic shown in the block diagram. The
address line, P2.3, is used to select either of the two
inputs. When the address line is low the RD and WR lines
perform their normal functions, that is read and write the
Hardware Description
8051 P2.3~
The following section describes the unique characteristics
of this design.
6.1.1
8051 WR
1A
8051 RD
1B
-
Peripheral Address Map
2A
+5V
The display RAM, 8276 registers, and the 8276 row buffers are memory mapped into the external data RAM address area. The addresses are as follows:
SEL
-
Y1 1--8276 WR
Y2 1--8276 BS
>---- 2B
-
3A
Y3 1--8276 RD
3B
Read and Write External
Display RAM Write to 8276 row buffers
from Display RAM Write to 8276 Command
Register (CREG) Write to 8276 Parameter
Register (PREG) Read from 8276 Status
Register (SREG) -
-
Address 1000H to 17CFH
Address 1800H to IFCFH
P2.4
Address OOOIH
If>-
DISPLAY RAM CS
Address OOOOH
Figure 6.1.0
Simplified Version Of The Transfer Logic
Address 0001H
2-85
AP-223
6.1.2.1
8276 or the external display RAM depending on the states
of their re~ctive chip selects. If the address line is high,
the 8051 RD line is transfonned into BS and WR signals
for the 8276. While holding the address line high, the
8051 executes an external data move (MOVX) from the
display RAM to the accumulator which causes the display
RAM to output the addressed byte pnto the data bus. Since
the multiplexor turns the same 8051 RD pulses into BS
and WR pulses to the 8276, the data bus is thus read into
the 8276 as a Buffer transfer. This scheme allows 80
characters to be transferred from the display RAM into
the 8276 within the required character line time of 635
microseconds. The 8051 easily meets this requirement by
accomplishing the task within 350 microseconds.
Undecoded Keyboard
Incorporating an undecoded keyboard controller into the
other functions of the 8051 shows the flexibility and over
all CPU power that is available. The keyboard in this case
is a full function, non-buffered 8 x 8 matrix of switches
for a total of 64 possible keys. The 8 send lines are connected to a" 3-to-8 open-collector decoder as shown in
Figure 6.1.1. Three high order address lines from the 8051
are the decoder inputs. The enabling of the decoder is
accomplished through the use of the PSEN signal from
the 8051 which makes the architecture of the separate
address space for the program memory and the external
data RAM work for us to eliminate the need to decode
addresses externally. The move code (MOVC) instruction
allows each scan line of the keyboard to be read with one
instruction.
6.1.2 Scanning The Keyboard
Throughout this project, provision have been made to
make the overall system flexible. The software has been
written for various keyboards and the user simply needs
to link different program modules together to suit their
needs.
The keyboard is read by bringing one of the eight scan
lines low sequentially while reading the return lines which
are pulled high by an external resistor. If a switch is
5V
,-
10kO
PO.7
8051
DATA
BUS
PO.O
1N4305~
,
~
, ,
~
~,
~
74156
2YO
'< '< '< '< '< '< '< '<
P2.1 - B
2Y1
'<
P2.2
1C
2Y2
'< '< '< '< '< '< '< '<
2C
2Y3
'< '< '< '< '< '< '< '<
1G
1YO
'< '< '< '< '< '< '< '<
2G
1Y1
'< '< '< '< '< '< '< '<
1Y2
'< '< '< '< '< '< '< '<
1Y3
'< '< '< '< '< '< '< '<
P2.0 - A
FROM
8051
,
L
L
'< '< '< '< '< '< '<
SWITCH MATRIX
Figure 6.1.1
Keyboard
2-86
AP-223
COMMAND
NO. OF
PARAMETER
BYTES
NOTES
RESET
4
Display format
parameters required
START
DISPLAY
0
DMA operation
parameters included in
command
STOP
DISPLAY
0
-
RED LIGHT
PEN
2
-
LOAD
CURSOR
2
ENABLE
INTERRUPT
0
-
DISABLE
INTERRUPT
0
-
PRESET
COUNTERS
0
4.3.1
4.3.4
Clears all internal
counters
8276 Instruction Set
Special Functions
Special Codes
The 8276 recognizes four special codes that may be used
to reduce memory, software, or system controller overhead. These characters are placed within the display memory by the system controller. The 8276 performs certain
tasks when these codes are received in its row buffer
memory.
1) End of Row Code -
Activates VSP. VSP remains
active until the end of the line is reached. While VSP
is active the screen is blanked.
2) End Of Row-Stop Buffer Loading Code - Causes the
Buffer Ready control logic to stop requesting buffer
transfers for the rest of the row. It affects the display
the same as End of Row Code.
3) End Of Screen Code - Activates VSP. VSP remains
active until the end of the frame is reached.
Programmable Buffer Loading
Control
The 8276 can be programmed to request I, 2, 4, or 8
characters per Buffer load. The interval between loads is
also programmable. This allows the designer the flexibility
to tailor the buffer transfer overhead to fit the system
needs.
Each scan line'requires 63.5 microseconds. A character
line consists of 10 scan lines and takes 635 microseconds
to form. The 8276 row buffer must be filled within the
635 microseconds or an under run condition will occur
within the 8276 causing the screen to be blanked until the
next vertical retrace. This blanking will be seen as a flicker
in the display.
5.0
Figure 4.1.1
4.3
Cursor X, Y position
parameters required
4) End Of Screen-Stop Buffer Loading Code - Causes
the Buffer Ready control logic to stop requesting buffer
transfers until the end of the frame is reached. It affects
the display the same way as the End of Screen code.
DESIGN BACKGROUND
A fully functional, microcontroller-based CRT terminal
was designed and constructed using the 8051 and the 8276.
The terminal has many of the functions that are found in
commercially available low cost terminals. Sophisticated
features such as programmable keys can be added easily
with modest amounts of software.
The 8051's functions in this application note include: up
to 9.6K BAUD full duplex serial transmission; decoding
special messages sent from the host computer; scanning,
debouncing, and decoding a full function keyboard; writing to the 8276 row buffer from the display RAM without
the need for a DMA controller; and scrolling the display.
The 8276 CRT controller's functions include: presenting
the data to the character generator; providing the timing
signals needed for horizontal and vertical retrace; and providing blanking and video information.
5.1
DeSign Philosophy
Since the device count relates to costs, size, and reliability
of a system, arriving at a minimum device count without
degrading the performance was a driving force for this
application note. LSI devices were used where possible
to maintain a low chip count and to make the design cycle
as short as possible.
PUM-51 was chosen to generate the majority of the 'software for this application because it models the human
thought process more closely than assembly language.
Consequently it is easier and faster to write programs using
PUM-51 and the code is more likely to be correct because
less chance exists to introduce errors.
2-83
AP-223
Characters Transmitted
PUM-51 programs are easier to read and follow than
assembly language programs, and thus are easier to modify and customize to the end User's application. PUM-5l
also offers lower development and maintenance costs than
assembly language programming.
•
•
•
•
PUM-51 does have a few drawbacks. It is not as efficient
in code generation relative to assembly language and thus
may also run slower.
• 2K x 8 static RAM
This application note uses' the 8051's interrupts to control
the servicing of the various peripherals. The speed of the
main program is less critical if interrupts are used. In the
last two application notes on terminal controllers, a criterion of the system was the time required for receiving
an incoming serial byte, decoding it, performing the function requested, scanning the keyboard, debouncing the
keys, and transmitting the decoded ASCII code must be
less than the vertical refresh time. Using the 8051 and its
interrupts makes this time constraint irrelevant.
5.2
System Target Specifications
The design specifications for the CRT terminal design is
as follows:
Display Format
• 80 characters/display row
• 25 display lines
Character Format
•
•
•
•
5 x 7 character contained within a 7 x 10 frame
First and 'seventh columns blanked
Ninth line curser position
Programmable delay blinking underline curser
Display Memory
Data Rate
• Variable rate from 150 to 9600 BAUD
CRT Monitor
• Ball Bros TV-12, 12MHZ Black and White
Keyboard
• Any standard undecoded keyboard (2 key lock-out)
• Any siandard decoded keyboard with output enable pin
• Any standard decoded serial keyboard up to 150 BAUD
Scrolling Capability
Compatible With Wordstar
6.0
The "brains" of the CRT terminal is the 8051 microcontroller. The 8276 is the CRT controller in the system, and
a 2716 EPROM is used as the character generator. To
handle the high speed portion of the CRT, the 8276 is
surrounded by a handful of TTL devices. A 2K x 8 static
RAM was used as the display memory.
Backspace
Linefeed
Carriage Return
Form Feed
I
Following the system reset, the 8276 is initialized for
curser type, number of characters per line, number of
lines, and character size. The display RAM is initialized
to all "spaces" (ASCII 20H). The 8051 then writes the
"start display" command to the 8276. The locallline input
is sampled to determine the terminal mode. If the terminal
is on-line, the BAUD rate switches are read and the serial .
port is set up for full duplex UART mode. The processor
then is put into a loop waiting to service the serial port
fifo or the 8276.
Escape Sequences 'Recognized
•
•
•
•
•
•
'.
•
•
ESC
ESC
ESC
ESC
ESC
ESC
ESC
ESC
ESC
SYSTEM DESCRIPTION
A block diagram of the CRT terminal is shown in figure
6.0.0. The diagram shows only the essential system features. A detailed schematic of the CRT terminal is contained in the Appendix 7.1.
Control Characters Recognized
•
•
•
•
96 ASCII Alphanumeric Characters
ASCII Control Character Set
ASCII Escape Sequence Set
Auto Repeat
A, Curser up
B, Curser down
C, Curser right
D, Curser left
E, Clear screen
F, Move addressable curser
H, Home curser,
J, Erase from curser to the end the screen
K, Erase the current line
The serial port is programmed to have the highest priority
interrupt. If the serial port generates an interrupt, the processor reads the buffer, puts the character in a generated
fifo that resides in the 8051's internal RAM, increments
the fifo pointer, sets the serial interrupt flag and returns.
Characters Displayed
• 96 ASCII Alphanumeric Characters
2-84
Ap·223
SERIAL
COMMUNICATIONS
CHANNEL
Figure 6.0.0 CRT Terminal Controller Block Diagram
The main program determines if it is a displayable character, a Control word or an ESC sequence and either puts
the character in the display buffer or executes the appropriate command sent from the host computer.
Three general cases can be explored; reading and writing
the display RAM, writing to the 8276 row buffers, and
reading and writing the 8276's control registers.
If the 8276 needs servicing, the 8051 fills the row buffer
for the CRT display's next line. If the 8276 generates a
vertical retrace interrupt, the buffer pointers are reloaded
with the display memory location that corresponds to the
first character of the first display line on the CRT. The
vertical retrace also signals the processor to read the keyboard for a key closure.
.
6.1
As mentioned previously the 8051 fills the 8276 row buffer
without the need of a DMA controller. This is accomplished by using a Quad 2-input multiplexor (Figure 6.1.0)
as the transfer logic shown in the block diagram. The
address line, P2.3, is used to select either of the two
inputs. When the address line is low the RD and WR lines
perform their normal functions, that is read and write the
Hardware Description
8051 P2.3~
The following section describes the unique characteristics
of this design.
6.1.1
8051 RD
1A
8051 WR
Peripheral Address Map
2A
+5V
The display RAM, 8276 registers, and the 8276 row buffers are memory mapped into the external data RAM address area. The addresses are as follows:
SEL
Y1 -8276WR
18
~
Y2 -8276 BS
2B
L....- 3A
Y3 f--8276 RD
3B
Read and Write External
Display RAM Write to 8276 row buffers
from Display RAM Write to 8276 Command
Register (CREG) Write to 8276 Parameter
Register (PREG) Read from 8276 Status
Register (SREG) -
-
Address 1000H to 17CFH
Address 1800H to IFCFH
P2.4
Address OOOIH
Address OOOOH
l{>-
DISPLAY RAM CS
Figure 6.1.0
Simplified Version Of The Transfer Logic
Address OOOIH
2-85
AP-223
6.1.2.1
8276 or the external display RAM depending on the states
of their re~ctive chip selects. If the address line is high,
the 8051 RD line is transfonned into BS and WR signals
for the 8276. While holding the address line high, the
8051 executes an external data move (MOVX) from the
display RAM to the accumulator which causes the display
RAM to output the addressed byte _onto the data bus. Since
the multiplexor turns the same 8051 RD pulses into BS
and WR pulses to the 8276, the data bus is thus read into
the 8276 as a Buffer transfer. This scheme allows 80
characters to be transferred from the display RAM into
the 8276 within the required character line time of 635
microseconds. The 8051 easily meets this requirement by
accomplishing the task within 350 microseconds.
6.1.2
Undecoded Keyboard
Incorporating an undecoded keyboard controller into the
other functions of the 8051 shows the flexibility and over
all CPU power that is available. The keyboard in this case
is a full function, non-buffered 8 x 8 matrix of switches
for a total of 64 possible keys. The 8 send lines are connected to a- 3-to-8 open-collector decoder as shown in
Figure 6.1.1. Three high order address lines from the 8051
are the decoder inputs. The enabling of the decoder is
accomplished through the use of the PSEN signal from
the 8051 which makes the architecture of the separate
address space for the program memory and the external
data RAM work for us to eliminate the need to decode
addresses externally. The move code (MOVC) instruction
allows each scan line of the keyboard to be read with one,
instruction.
Scanning The Keyboard
Throughout this project, provision have been made to
make the overall system flexible. The software has been
written for various keyboards and the user simply needs
to link different program modules together to suit their
needs.
The keyboard is read by bringing one of the eight scan
lines low sequentially while reading the return lines which
are pulled high by an external resistor. If a switch is
5V
-
10kO
~
PO.7
8051
DATA
BUS
po.o
1N4305 --,..
.~,
,
,
,
"
74156
P2.0 - A
2YO
P2.1 - B
2Y1
P2.2
L
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2Y2
2C
2Y3
--L
1G
1YO
2G
1Y1
FROM
8051
PSEN
'< '< '< '< '< '< '< '<,
'< '< '<
'< '< '<
'< '< '<
'< '< '<
'< '< '<
'< '< '<
'< '< '<
1Y2
1Y3
'< '< '< '< '<
'< '< '< '< '<
'< '< '< '< '<
'< '< '< '< '<
'< '< '< '< '<
'< '< '< '< '<
'< '< '< '< '<
SWITCH MATRIX
Figure 6.1.1
Keyboard
2-86
AP-223
closed, the data bus line is connected through the switch
to the low output of the decoder and one of the data bus
lines will be read as a O. By knowing which scan line
detected a key closure and which data bus line was low,
the ASCII code for that key can easily be looked up in a
matrix of constants. PUM-51 has the ability to handle
arrays and structured arrays, which makes the decoding
of the keyboard a trivial task.
Since the Shift, Cap Lock, and Control keys may change
the ASCII code for a particular key closure, it is essential
to know the status of these pins while decoding the keyboard. The Shift, Cap Lock, and Control keys are therefore not scanned but are connected to the 8051 port pins
where they can be tested for closure directly.
The 8 receive lines are connected to the data bus through
germanium diodes which chosen for their low forward
voltage drop. The diodes keep the keyboard from interfering with the data bus during the times the keyboard is
not being read. The circuit consisting of the 3-to-8 decoder
and the diodes also offers some protection to the 8051
from possible Electrostatic Discharge (ESD) damage that
could be transmitted through the keyboard.
6.1.2.2
Decoded Keyboard
A decoded keyboard can easily be connected to the system
as shown in Figure 6.1.2. Reading the keyboard can be
evoked either by interrupts or by software polling.
The software to periodically read a decoded keyboard was
not written for this application note but can be accomplished with one or two PUM-51 statements in the
READER routine.
A much more interesting approach would be to have the
servicing of the keyboard be interrupt driven. An additional external interrupt is created by configuring timer/
counter 0 into an event counter. The event counter is
SCAN
initialized with the maximum count. The keyboard controller would inform the 8051 that a valid key has been
depressed by pulling the input pin TO low. This would
overflow the event counter, thus causing an interrupt. The
interrupt routine would simply use a MOVC (PSEN is
connected to the output enable pin of the keyboard controller) to read the contents of the keyboard controller onto
the data bus, reinitialize the counter to the maximum count
and return from the interrupt.
6.1.2.3
Serial Decoded Keyboard
The use of detachable keyboards has become popular
among the manufacturers of keyboards and personal computers. This terminal has provisions to use such a keyboard.
The keyboard controller would scan the keyboard, debounce the key and send back the ASCII code for that
key closure. The message would be in an asynchronous
serial format.
The flowchart for a software serial port is shown in Figure
6.1.3. An additional external interrupt is created as discussed for the decoded keyboard but the use in this case
would be to detect a start bit. Once the beginning of the
start bit has been detected, the timer/counter 0 is configured to become a timer. The timer is initialized to cause
an interrupt one-half bit time after the beginning of the
start bit. This is to validate the start bit. Once the start bit
is validated, the timer is initialized with a value to cause
an interrupt one bit time later to read the first data bit.
This process of interrupting to read a data bit is repeated
until all eight data bits have been received. After all 8
data bits are read, the software serial port is read once
more to detect if a stop bit is present. If the stop bit is
not present, an error flag is set, all pointers and flags are
reset to their initial values, and the timer/counter is reconfigured to an event counter to detect the next start bit.
If the stop bit is present, a valid flag is set and the flags
and counter are reset as previously discussed.
KEYBOARD
CONTROLLER
BUS
KEYBOARD
8051
"
I
RECEIVE
DATA
READY
"v
FIgure 6.1.2
CS
v
PORTO
TO
PSEN
Using A Decoded Keyboard
2-87
AP-223
RETURN
RETURN
RETURN
Figure 6.1.3
Flowchart for the Software Serial Port
6.1.4 System Timings
The requirements for the BALL BROTHERS. TV-12
monitor's operation is shown in table 6.1.0. From the
monitor's parameters, the 8276 specifications and the system target specifications the system timing is easily calculated.
500 Hz of 15,750 Hz, we 'must choose either one or two
character line times for horizontal retrace. To allow for a
little more margin at the top and bottom of the screen,
two character line times was chosen for the vertical retrace. This choice yields 250 + 20 = 270 total character
lines per frarr. r . Assuming 60 Hz vertical retrace frequency:
The 8276 allows the vertical retrace to be only an integer
mUltiple of the horizontal character lines. Twenty-five display lines and a character frame of 7 x 10 are required
from, the target specification which will require 250 horizontal lines. If the horizontalfrequency is to be within
60 Hz * 270 = 16,200 Hz horizontal frequency
and
1116,200 Hz * 20 horizontal sync times = 1.2345 milliseconds
2-88
AP-223
Table 6.1.0 CRT Monitor's Operational Requirements
PARAMETER
RANGE
Vertical Blanking Time
(VRTC)
800 /-Lsec nominal
Vertical Drive Pulsewidth
300 /-Lsec "" PW "" 1.4 ms
Horizontal Blanking Time
(HRTC)
11 JLsec nominal
Horizontal Drive Pulsewidth
25 JLSec "" PW "" 30 /-Lsec
15,750 +500 pps
Horizontal Repetition Rate
The 1.2345 milliseconds of retrace time meets the nominal
VRTC and vertical drive pulse width time of .3mSec to
1.4mSec for the Ball monitor.
6.2 Software Description
The next parameter to find is the horizontal retrace time
which is wholly dependent on the monitor used. Usually
it lies between 15 and 30 percent of the total horizontal
line time.
The software for this application was written in a "foreground-background" format. The background programs
are all interrupt driven and are written in assembly language due to time constraints. The foreground programs
are for the most part written in PUM-51 to ease the programming effort. A number of subroutines are written in
assembly language due to time constraints during execution. Subroutines such as clearing display lines, clearing
the screen, and scanning the keyboard require a great deal
of 16 bit adds and compares and would execute much
slower and would require more code space if written in
PUM-51. The background and foreground programs talk
to each other through a set of flags. For ~xample, the
PUM-51 foregrounp program tests "SERIAL$INT" to
determine if a serial port interrupt had occurred and a
character is waiting to be processed.
6.2.1
Since most designs display a fixed number of characters
per line it is useful to express the horizontal retrace time
as a given number of character times. In this design, 80
characters are displayed, and it was experimentally found
that 20 character times for the horizontal retrace gave the
best results. It should be noted if too much time was given
for retrace, there would be less time to display the characters and the display would not fill out the screen. Conversely, if not enough time is given for retrace, the characters would seem to run off the screen.
One hundred character times per complete horizontal line
means that each character needs:
Software Overview
6.2.2 The Background Program
(1116,200 Hz) 1100 character times = 617.3 nanoseconds
If we multiply the 20 character times needed to retrace
by 617.3 nanoseconds needed for each character, we find
12.345 microseconds are allocated for retrace. This value
falls short of the 25 to 30 microseconds required by the
horizontal drive of the Ball monitor. To correct for this,
a 74LS 123 one-shot was used to extend the horizontal
drive pulse width.
The dot clock frequency is easy to calculate now that w~
know the horizontal frequency. Since each character is
formed by seven dots in the horizontal axis, the dot clock
period would be the character clock (617.3 nanoseconds)
divided by the 7 which is equal to 11.34 MHz. The basic
dot timing and CRT timing are shown in the Appendix.
Two interrupt driven routines, VERT and BUFFER, (see
Fig. 6.2.0) request service every 16.67 milliseconds and
617 microseconds respectively. VERT's request comes
during the last character row of the display screen. This
routine resets the buffer pointers to the first CRT display
line in the display memory. VERT is also used as a time
base for the foreground program. VERT sets the flag,
SCAN, to tell the foreground program (PUM-51) that it
is time to scan the Keyboard. VERT also increments a
counter used for the delay between transmitting characters
in the AUTO$REPEAT routine.
The BUFFER routine is executed once per character row.
BUFFER uses the multiplexor discussed earlier to fill the
8276's row buffer by executing 80 external data moves
and incrementing the Data Pointer between each move.
2-89
AP·223
as discussed earlier. After all variables and flags are initialized, the processor is put into a loop waiting for either
VERT to set SCAN so the program can scan the keyboard,
or for the serial port to set SERIAL$INT so the program
can process the incoming character.
RE-INITIALIZE
8278
ROW BUFfER
POINTER TO THE
The vertical retrace is used to time the delay between
keyboard scans. When VERT gets set, the assembly language routine READER is called. READER scans the
keyboard, writing each scan into RAM to be processed
later. READER controls two flags, KEYO and SAME.
KEYO is set when all 8 scans determine that no key is
pressed. SAME is set when the same key that was pressed
last time the keyboard was read is still pressed.
TOP OF THE
DISPLAY
After READER returns execution to the main program,
the flags are tested. If the KEYO flag is set the main
program goes back to the loop waiting for the vertical
retrace or a serial port interrupt to occur. If the SAME
flag is set the main program knows that the closed key
has been debounced and decoded so it sends the already
known ASCII code to the AUTO$REPEAT routine which
determines if that character should be transmitted or not.
RETURN
RETURN
Figure 6.2.0
Flowcharts For
VERT and BUFFER Routine
The MOVX reads the display RAM and writes the character into the row buffer during the same instruction.
SERBUF is an interrupt driven routine that is executed
each time a character is received or transmitted through
the on-chip serial port. The routine first checks if the
interrupt was caused by the transmit side of the serial port,
signaling that the transmitter is ready to accept another
character. If the transmitter caused the interrupt, the flag
"TRANSMIT$INT" is set which is checked by the foreground program before putting a character in the buffer
for transmission.
If the receiver caused the interrupt, the input buffer on
the serial port is read and fed into the fifo that has been
manufactured in the internal RAM and increments the fifo
pointer ."FIFO." The flag "SERIAL$INT" is then set,
telling the foreground program that there is a character in
the fifo to be processed. If the read character is an ESC
character, the flag "ESCSEQ" is set to tell the foreground
program that an escape sequence is in the process of being
received.
If KEYOand SAME are not set, signifying that a key is
pressed but it is not the same key as before, the foreground
program determines if the results from the scan are valid.
First all eight scans are checked to see if only one key
was closed. If only one key is closed, the ASCII code is
determined, modified if necessary by the Shift, Cap Lock,
or Control keys. The NEW$KEY and VALID flags are
then set. The next time READER is called, .if the same
key is still pressed, the SAME flag will be set, causing
the AUTO$REPEAT subroutine to be called as just discussed. Since the keyboard is read during the vertical
retrace, 16.67 milliseconds has elapsed between the detection of the pressed key and reverifying thai the key is
still pressed before transmitting it, thus effectively debouncing the key.
The AUTO$REPEAT routine is written to transmit any
key that the NEW$KEY flag is set for. The counter that
is increl1}ented each time the vertical refresh inteIplpt is
serviced causes a programmable delay between the first
transmission and subsequent auto repeat transmission.
Once the NEW$KEY character is. sent, the counter is
initialized. Each time the AUTO$REPEAT routine is
called, the counter is checked. Only when the counter
overflows will the next character be transmitted. After the
initial delay, a character will be transmitted every other
time the routine is called as long as the key remains
pressed.
6.2.3.1
6.2.3 The Foreground Program
Handling Incoming Serial Data
One of the criteria for this application note was to make
the software less time dependent. By creating a fifo to
store incoming characters until the 8051 has time to pro-
The foreground program is documented in the Appendix.
The foreground progra~ starts off by initializing the 8276
2-90
AP·223
cess them, software timing becomes less critical. This
application note uses up to 8 levels of the fifo at
9.2KBAUD, and I level at 4.8KBAUD and lower. As
discussed earlier, the interrupt service routine for the serial
port uses the fifo to store incoming data, increments the
fifo pointer, "FIFO", and sets SERIAL$INT to tell the
main program that the fifo needs servicing. Once the main
program detects that SERIAL$INT is set the routine
DECIPHER is executed.
When DECIPHER is executed, the first block begins looking at the first character of the fifo for a displayable character. If the character is displayable, it is placed into the
display RAM and the software pointer "TOP" that points
to the character that is being processed is incremented to
the next character. The character is then looked at to see
if it too is displayable and if it is, it's placed in the display
RAM. The process of checking for displayable characters
is continued until either the fifo is empty or a non-displayable character is detected. In our example, three characters are placed into the display RAM before a nondisplayable character is detected. At this point the fifo
looks like figure 6.2.I-B.
DECIPHER has three separate blocks; a block for decoding displayable characters, a block for processing Escape
sequences, and a block for processing Control codes. Each
block works on the fifo independently. Before exiting a
block, the contents of the fifo are shifted up by the amount
of characters that were processed in that particular block.
The shifting of the characters insures that the beginning
of the fifo contains the next character to be processed.
FIFO is then decremented by the number of characters
processed.
Before entering the next block, the remaini'ng contents of
the fifo between TOP, that is now pointing to I BH and
(FIFO-I) are moved up in the fifo by the amount of characters processed, in this example three. TOP is reset to 0
and FIFO is decremented by 3. The serial port interrupt
is inhibited during the time the contents of the fifo and
the pointers are being manipulated. The fifo now looks
like figure 6.2.I-C.
Let's look at this process more closely. Figure 6.2.I-A
shows a representation of a fifo containing 5 characters.
The first three characters in the fifo contain displayable
characters, A, B, and C respectively with the last two
characters being an ESC sequence for moving the curser
up one line (ESC A) and FIFO points to the next available
location to be filled by the serial port interrupt routine, in
this case,S.
TOP-..
41H (A)
41H (A)
42H (B)
42H(B)
43H(C)
43H (C)
1BH (ESC)
TOP-" 1BH (ESC)
If at the end of the DECIPHER routine, FIFO contains a
0, the flag SER$INT is reset. If SER$INT remains set,
DECIPHER will be executed immediately after returning
to the main program if SCAN had not been set during the
execution of the DECIPHER routine, otherwise DECIPHER will be called after the keyboard is read.
41H (A)
41H (A)
FIFO-.
The execution is now passed to the next block that processes ESC sequences. The first location of the fifo is
examined to see if it is an ESC character (lBH). If not,
the execution is passed to the next block of DECIPHER
that processes Control codes. In this case the fifo does
contain an ESC code. The flag ESC$SEQ is checked to
see if the 8051 is in the process of receiving an ESC
sequence thus signifying that the next byte of the sequence
has not been received yet. If the ESC$SEQ is not set, the
next character in the fifo is checked for a valid escape
code and the proper subroutine is then called. The fifo
contents are then shifted as discussed for the previous
block. Due to the length of time that is needed to execute
an ESC code sequence or a Control code, only one ESC
code and/or Control code can be processed each time
DECIPHER is executed.
FIFO-..
(A)
(8)
TOP-.. 1BH (ESC)
6.2.4
41H(A)
Memory Pointers and ScrOlling
FIFO-..
The curser always points to the next location in display
memory to be filled. Each time a character is placed in
the display memory, the curser position needs to be tested
to determine if the curser should be incremented to the
beginning of the next line of the display or simply moved
to the next position on the current display line. The curser
position pointers are then updated in both the 8276 and
the internal registers in the 8051.
(C)
FIGURE 6.2.1
FIFO
2-91
AP-223
When the 2000th character is entered into the display
'memory, a full display page has been reached signaling
the need for the display to scroll. The memory pointer
that points to the display memory that contains the first
character of the first display line, LINEO, prior to scrolling
contains 1800H which is the starting address of the dIsplay
memory. Each scrolling operation adds 80 (SOH) to LINEO
which will now point to the following row in memory as
shown in figure 6.2.2-B. LINEO is used during the vertical
MEMORY LOCATION
18DDH
refresh routine to re-initialize the pointers associated with
filling the 8276 row buffers.
The display memory locations that were the first line of
the CRT display now becomes the last line of the CRT
display. Incoming characters are now .entered into the
display memory starting with 1800H, which is now the
first character of the last line of the display screen.
MEMORY
LOCATION
184FH
MEMORY LOCATION
1800H
NEW TEXT
INSERTED HERE
LINED
LINED
'"---t- ROW (80 CHAR)
MEMORY
LOCATION
1850H
DURING FIRST
PAGE
MEMORY
LOCATION
lF80M
B) AFTER 1ST SCROLLING OPERATION
A) BEFORE SCROLLING
LINEO
-
MEMORYLOCATIO N
18ADH
~
I
NEW TEXT
INSERTED HERE
fj'
LINEO
-
MEMORY
LOCATION
18FOH
C) AFTER 2ND SCROLLING OPERATION
- ~
NEW TEXT
I
f.- INSERTED HERE
D) AFTER 3RD SCROLLING OPERATION
MEMORY LOCATION
1800H
LINED
LINED
NEW TEXT
INSERTED HERE
NEW TEXT
INSERTED HERE
F) AFTER 25TH SCROLLING OPERATION
E) AFTER 24TH SCROLLING OPERATION
Figure 6.2.2 Pointer Manipulation During Scrolling
2-92
Ap·223
6.2.5 Software Timing
The use of interrupts to tie the operation of the foreground
program to the real-time events of the background program
has made the software timing non-critical for this system.
6.3 System Operation
Following the system reset, the 8051 initializes all onchip peripherals along with the 8276 and display ram.
After initialization, the processor waits until the fifo has
a character to process or is flagged that it is time to scan
the keyboard. This foreground program is interrupted once
every 617 microseconds to service the 8276 row buffers.
The 8051 is also interrupted each 16.67 milliseconds to
re-initialize LINEOand to flag the foreground program to
read the keyboard.
2-93
As discussed earlier, a special technique of rapidly moving
the contents of the display RAM to the 8276 row buffers
without the need of a DMA device was employed. The
characters are then synchronously transferred to the character generator via CCO-CC6 and LCO-LC2 which are
used to display one line at a time. Following the transfer
of the first line to the dot timing logic, the line count is
incremented and the second line is selected. This process
continues until the last line of the character is transferred.
The dot timing logic latches the ouput of the character
ROM in a parallel in, serial out synchronous shift register.
The shift register's output constitutes the video information to the CRT.
AP-223
Appendix 7.1
CRT Schematics
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2-94
J21
AP·223
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: lIi1'l2t::W-lMl il:'2Cl40':H~2 ;,):'lW1"392~2 ;1 2 i'2 ~ 2"3 ~.l":;(IJ
:1~32f~~0~81C2A~3~BJR~3~~3~~~~A~~A~~~~17~12
: 1 !1~30;lOt'l1~9~n 1 (~Yl:IY'3:1(l:1::l:1~~'~:~ 3'::2(nC22'3:"~4i::
:10~31~~0~2A21A2G22221E~~~",a038~4~4A~3q~~3~
: 13ti32Wl:12i-l202:::322222 '3CrH~"~::l113q24aC~4dq ~~')~
: 10"330il03R24040t::iH ~4"4 r'iI~f'l:1:HC22?23C2!lI3CM
: H~I.n400('Ja2!' 21 ~2t;222222i100 8(i111 ~:H~;'R ";J~9'Htl4:i
: 11l~35~:'ln'''''''02~2:i21lA42418(12(122212.";J~1~?2('J:;'::3
: 10.,3t):M:Hl ~m8(~8~ 3~8~39;'/,.,a'~\~3 3~2A21\2222(~~7f
:10337A~A::3~l~11\2;222222~~~a~('JIR2424241R~~3~
: 1 ("03B':1:13~~A:~ It:22221t:(.'l2"2"'~l'la lC2 2223'::2~20"J
: 10~39;M~~33;nA2r,32:'2;;'2:.l3:":l~~3q141A2rHC~1q7
: 1 ""3M' J~~~;'RICA ~(-IR" q9~:l(l~~':l~ 22222232 4C"~"9';
:10i13~003;'3~"222222140~"~~J~~22222A1EI4f'l:l~~
: 1 ~1~' 3Cvl:~3a:, ~!12214!1 'U 42 2~lil" ;m:l22? 2 22 3(: 2J3A~f
: 1"~3D!'~'MW~(Br: 10:"8l'4 3t::~:;j188qA9'Bq9R91 ~H2f
: 10:n~~;,a:'BAS~" 3lB Atl$iA ..,338 ~C9.~91219~9100:M51
:IYla3f0~3393i19C2dd0~1~a~a3~~3~~A00~~~00:l~95
2-100
AP-223
Appendix 7.7 Composite Video
In this design it was assumed that the CRT monitor required a separate horizontal drive, vertical drive, and
video input. Many monitors require a composite video
signal. The schematic shown in Figure 7.7.0 illustrate how
to generate a composite video from the output of the 8276.
5OK
:J
The dual one-shots are used to provide a small delay and
the proper horizontal and vertical pulse to the composite
video monitor. The delay introduced in the horizontal and
vertical timing is used to center the display. The 7486 is
used to mix the vertical and horizontal retrace. Ql mix
the video and retrace signals along with providing the
proper D.C. levels.
4.7K
2
HRTe
1
.f""
2.2 K
2Q
15
4
I
5
5
3
t--5Y
470pF 14
"
74LS221
2Q
B,
A,
ex
ex
- Rxex-
0,
L
10K
74LS221
6
7
B2~
5y2
.001"F
.1"F
II
II
6
"
"
7
7486~
5Y
I
2
B,
1
A,
ex
-RXCX
0
./ VRTC
~
~
cx
5OK
2.2K
.05
14
II
15
"
B2~
+5
7486
6800
1KO
+5
1KO
COMPOSITE
VIDEO
OUT
VIDEO
1500
-=
Figure 7.7.0 Composite Video
2-101
AP-223
Appendix 7.8
Software Documentation
/**********************************************************.*.*****************
******************.*.****.****.*.*********.******************.*****************
.t*t •••
*******
***.* ••
SOF"lWARE
***.***
.******
*.***.*
*.*****
IXJC(roNTATIl~
TEIfo\INAL aJn'R)LLER
roR TIlE 8051
APPLICATICN 00l'E
**** •••
************************.*.**********************.*******.*.********.**.*** ••••
*********.* •• ***.******.****************** •• ***********************.* •••• ******
MIMlRi MAP ASSOCIATED WITH PERIPHERAL DMCES (USING tOJX):
8051
8051
8276
8276
8276
WR AND READ DISPLAY Rl\MADDRESS 100OH'ro 17CE1f
WR DISPIAY R!\M TO TIlE 8276- ADDRESS 1800H TO lR:EH
CXMWID ADDRESSADDRESS OOOlH
PARlIMI!lrER ADDRESSADDRESS OOOOH
srATUS RIDISl'ERADDRESS OOOlH
MIMlR':( MAP roR READIm TIlE KElOOARl) (USING MJI.lI:):
KElOOARl) ADDRESS-
ADDRESS 10FFH'ro 17FFH
/*******~*****~**.*** BrARl' MAIN PIOORAM.
**.**** •• ******* •••• **.****/
/* BEGIN B'f FUlTING TIlE AOCII CODE roR BLANK IN TIlE DISPLAY R!\M* /
INIT:
{nu.
.
2000I.o::ATICNS IN TIlE DISPLAY R!\M WITH SPJ!C:!;S (AOCII 20H)}
/*
I
INITIALIZE FOINl.'ERS, R!\M BITS, Ell'C.
INITIALIZE
INITIALIZE
INITIALIZE
INITIALIZE
*/
FOINI'ERS AND FLAGS}
TOP OF TIlE CRr DISPIAY "LINEO"=180OH}
8276 BUFFER POINl'ER "RASTER" =180OH}
DISPIAY$R!\M$POINTER=OOOOH}
/*
INITIALIZE TIlE 8276
*/
RESEr TIlE 8276}
.
INITIALIZE 8276 ro 80 ClIARl\C1'E1VRJ }
INITIALIZE 8276 'ro 25,R:MS PER FRAME}
INITIALIZE 8276 'ro 10 LINES PER lO'I}
INITIALIZE 8276 oro NCN-BLIIIONG UNDERLINE aJRSER}
INITIALIZE aJRSER TO IDlE FOSITICN (00,00) (UPPER LEFt' HAND CORNER)}
mARl' DISPIAY}
ENABLE 8276 lNl'ERlIJPl'}
\
\
I
/*
SET UP 8051 lNl'ERlIJPl'S AND PRlORITIFS
SERIAL roRl' HAS HIGHEsr lNl'ERlIJPl' PRloRi:~}
IN!'ERHlPl'S ARE EDGE SENSITIVE}
,
ENABLE 'ro Nm CHARl\CTER
3m> THRXJGH Nl'3 CHARl\CTER */
*/
END;
];lID;
/* PRX:EWRE TRANiMIT- CN::E THE Hoor a:MP!1I'ER
SIGNALS THE 8051H BY' BRINGING
- THE CIEAR-ro-SEND LINE IDN, THE AOCII CIlARl\CTER IS R1l' mro THE SERIAL PORT.*/
TRlINiMIT :
PR:cEWRE;
IF {THE TER-IINAL IS Cti-LINE} THEN
00;
I
. '
WAIT um'IL THE CLEAR$'ro~SEND LINE IS IDN AND um'IL THE 8051 SERIAL PORl' TX IS !Ul' BUS{ (TRANiMIT$INT=l) }
TRANSMIT THE ASCII CODEI
CLFAR THE FLAG "TRANSMIT$mr~. THE SERIAL PORl' SERVICE lO1l'INE WILL 8m' THE FLAG
WHEN THE SERIAL PORT IS FINISHED TRlINiMITTING}
END;
ELSE {THE TER-IINAL IS IN THE LOCAL KlIlE}
00;
!
R1l' THE AOCII COIlE IN THE FIFO}
INCREMEN!' THE FIFO POINl'ER}
8m' SERIAL$mr}
END;
END TRANSMIT;
.
2-104
AP-223
/*
PKlCELURE DEX:!IP!lER: THIS PKlCELURE DEIXlDES THE HOSl' CCMPUTER' S MESSAGES AND DEl'ER>\.INES
WHEl'HER IT IS A DISPLAYABLE CHAAACTER, CXJNl'IDL SEX;;lUENCE, OR AN ESCAPE S~
THE PKlCELURE THEN N:l'S l\OX)RDINGLY */
DEX:!IPHER:
STARl'$DEX:!IPHER:
VALID$RECEPTION=O;
00 WHILE {THE FIFO IS NO!' EMPl"i AND THE CHAAACTER IS DISPLAYABLE)
ROCEIVE={ASCII CODE)
CALL DISPLAY,
{NEXT CHAAACTER)
END,
IF
IF
CI!ARACl'ERS WERE DISPLAYED) '!HEN
DlSABIE SERIAL PORT INl'ERRlPr)
M:lVE THE REMAINING CXlmNI'S OF THE FIFO UP 'lXl THE BmINNING OF THE FIR))
ENABLE SERIAL PORT INl'ERRlJPI'1
SE:r THE VALID$RECEPTION FLAG
{nm FIR) IS EMPl"i) THEN
{CLEAR THE "SERIAL$Im FLAG AND REll.'URN)
IF I'lliE NEXT CHARACl'ER IS AN "ESC" CODE } THEN
00:
{I£lCK AT THE CHAAACTER IN THE FIR) AFI'ER 'lliE ESC CODE AND CALL THE CDRREX:!T SUBR:Ul'INE}
b..u. UP$lATICN FULLCMED Blr TIlE CXlUJ:IN INFU!W.TICN */
MJV$CURSER:
WAIT UNTIL TIlE FIR> lIAS REX:ElVED THE NEXT TW) CHARl'Cl'ERS}
{MJ\IE TIlE ClIIQ:R ro THE LOCM'ICN SPECIFIED IN THE ESCAPE sa;;oFNCE}.
MJ\IE TIlE DISPLAY$RAM$POINTER ro THE Hi TW)}
mABLE TIlE SERIAL PORl' INl'ERlIlPl'}
/*
TW)
LOCM'ICNS IN
MEM)R{}
PR:lCEIlJRE LEFl' Cl1IQ:R: 'IlIIS PR:lCEIlJRE MJ\IES THE Cl1RSER LEFr Rl MAP AS~IA'I'ED WITH PERIPHERAL I>INICES (USING MO\Il():
8051
8051
8276
8276
8276
WR AND READ DISPlAY RIlMWR DISPlAY RIlM 'l'O THE 8276-O»IAND ADDR&S5PARI\ME:l'ER ADDR&S591'A'lUS REIiISl'ER-
ADDR&SS
ADDR&SS
ADDR&SS
ADDR&SS
ADDR&SS
1000H 'l'O 17CFH
1800H oro 1mB
OOOlH
000011
OOOlH
oro' 17FFH
NXORDn«; oro THE 'l'iPE
ADDR&SS 10FFH
THE FOLI.amiIG SOFlWARE SWl'l'CIIES Kl91' BE SJ!:r
'!HAT IS ron«; oro BE USED.
~1KlMD
Slfl- SEll' WHm usm:; AN tJNDJOCXlIlEo ~1KlMD IS oro BE USED
SW2- SJ!:r WHm usn«; A 0E:XlDID OR A SERIAL 'l'iPE OF Im:iOOMD
tJNDIiXDDED ~BOf\H)- CRrPrM.OB.1 ,CRrASM.OBJ ,KElCBD.OBJ ,PI.H5l.LIlI
, DEXDDED KE:lllClMI>-CIm'lM.OB.1 ,CRrASM.OB.1 ,DEXXDE.OB.1 ,P1H51.LIB
0Erl\CHED KElCBOIIRO-CRl'PIM.OB.1 ,CRrASM.OB.1 ,DEll'ACH',OB.1 ,PI.H5l.LIB
*/
$SJ!:r (SWl)
$l\ESEr
(SW2)
2·112
OF
AP-223
PLjM- 51 cnlPILER
CRl'$CXJNTR)LLER:
1
1
00;
I*t •••• _••* ••••••• DECLARE LITERALS *•••• ******* •••• *******./
2
3
4
5
6
1
1
1
1
1
7
8
9
1
1
1
10
1
11
12
1
1
O&:U\RE LI£ LI'l'ERALI.Il 'L' ,OOH,3El1,OOH,00H,00H,
/* SCAN 3, SHIFl' =1; M,<,>,? *1
1*
*1
OOH, 'AZXCVBN' ,
SCAN 4, SHIFl' =1; A,Z,X"C,V,S,N
*1
.1*
'Y' ,OOH,OOH,' DFGH',
SCAN 5, SHIFl' =1; Y, SPACE, D,F ,G,H
1*
09H, '~' ,OOH,
SCAN 6, SHIFl' =1; TAB, Q,W,S,E,R,T
I"
lBH,' 1"t$%&' ,OOH);
SCAN 7, SHIFl' =1; ESC, 1,',i ,$,%,&
·1
*1
*1
$ENDIF
2-115
*1
*1
*1
*1
AP-223
PL;M-51 IaI;
aJRSER$OOlllMN=O;
aJRSER$CII=l;
CALL LOI\D$aJRSER;
END CARRIAGE$REl1'URN;
2·119
*/
AP·223
PL/M- 51
cnu>ILER
CRl'CXJNI'R:lLLER
/* PRJCEIlJRE!O'IN CURSER: THIS PKlCEllJRE tOJES TIlE CURSER !O'IN OOE IDI
B'i AlIlING 1 TO TIlE CURSER lUI RlIM LOCATICN TIlEN C1ILL UlN) CURSER */
64
1
65
66
67
68
2
3
3
3
IX)iN$CURSER:
PKlCEllJRE :
IF CURSER$RJW < 18H THEN
DO;
0 TIlEN
3
DO,
84
3
3
85
86
87
88
89
3
3
3
3
CURSER$1Ol=CURSER$1DI _. 1;
aJRSER$CN=1;
C1ILL UlI\D$C1JRSER;
IF DISPIAY$Rl\M$FOINTER<5OH THEN
DISPIIIY$Rl\M$FOIN1'ER=DISPIIIY$Rl\M$POIN1'ERI-78011;
ELSE
DISPIIIY$Rl\M$FOINTER=DISPIAY$Rl\M$POINTER - SOlI;
L=DISPIAY$Rl\M$POIN'l'ER-CURSER$(X)UJoIN;
IF DISPIAY$RlIM(L)=OFlH '!'HEN
/*
91
3
3
92
4
00;
93
94
4
C1ILL FILL;
DISPIIIY$RAM (L) =2011;
END;
90
4
95
4
96
3
1
97
LQCl{
POR END OF LINE*/
/*
CiIl'JIl\C'lER */
/* IF TRUE FILL WITH
/* SPACES */
ENO;
END UP$CURSER;
2-120
*/
AP·223
PLjM- 51 CD1PlLER
CRl'CCNl'RJLLER
/* PRX:EIl.JRE RIGHI' aJRSER: THIS PRX:EIl.JRE !ofJVES THE aJRSER RIGHI' ONE COLUMN
B'f AIDING 1 ro THE aJRSER COLUMN RAM ID:ATION THEN CALL WAD aJRSER */
98
1
99
2
100
101
102
103
104
105
106
3
3
3
3
3
3
1
RIGIfl'$CURSER:
PRX:E!lJRE;
IF aJRSER$OJLUMN < 4m THEN
00;
0 THEN
00;
,
TEMP 1'IIm
001
L=DISPLAY$RAM$POINTE:RI- ( (OJRSER$!O'l-TEMP)· SOH) 1
IF L> 7CE1l 1'IIm
1* IF OOT OF RAM RI\OOE *1
DISPLAY$RAM$POINTER=L-7DOHl
1* RAP AmlND ro BEGINNING
~
~~RIIM~
*1
DISPLAY$RIIM$POINTER=Ll
127
12B
3
2
ENDl
~
001
129
130
131
132
133
134
3
4
4
4
4
4
135
136
137
13B
139
140
141
4
3
2
2
2
2
2
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
2
2
2
2
3
3
3
3
2
3
3
3
2
2
1
IF OJRSER$R:MTEMP 1'IIm
DISPLAY$RI\M$POINrER=DISPIAY$RI\M$POINTER+ (~) i
ELSE
DISPLAY$RIIM$FOINrER=DISPIAY$RI\M$POINTER- (TEMP-O.lRSER$COUlMN) 1
aJRSER$CN=11
CALL LOAD$OJRSERi
L=DISPLAY$RI\M$POINTER-aJRSER$COUJoINl
IF DISPLAY$RIIM(L)=OFlH 1'IIm
1* UXI< FOR END FO LINE CIIARl\CTER*1
001
CALL FILLl
1* IF TRlE FILL WTI'H SPl\CES *1
01 SPLAY $RIIM (L) =2OHl
ENDl
ES=Oi
00 1=2 ro FIFO-21
SERIAL (I) =SERIAL (1+2) 1
ENDl
FlFO=FIFO-21
ES=ENSPl
END MO\I$OJRSERi
2-122
AP-223
PL/M-51 CCMPILER
/*
CRl'CXNI'IVILER
PR:X:EllJRE ERASE FlU! CURSER 'IO END OF S::~:
157
1
ERASE$FI01SCURSER$TO$END$OF$SC~:
i58
159
160
161
162
163
164
165
166
167
168
169
170
171
172
2
2
3
3
4
4
4
4
3
4
4
4
4
3
1
CALL BLINE;
*/
POCCELURE;
/* ERASE QJRRENl' LINE
IF CURSER$lO'l < lSH THEN
00;
L=DISPLAY $ RIIM$POINrER-aJRSER$(X)IlJMNt SOH;
/* GEr NEXT LINE */
00 WHILE (L < 7DOH) AND (L <> (LINEO AND 7FFH));
DISPLA¥$RIIM(L)=OFlH;
/* ERASE UNTIL LINEO OR */
L=LT50H;
/* END OF DISPLAY RAM*/
END;
L=O;
00 WHILE L <> (LINEO AND 7FFH);
/* ERASE UNTIL LINEO */
DISPLA¥$RAM(L)=OFlH;
L=LT5OH;
END;
END;
END ERASE$FI01SCURSER$TO$END$OF$S::~;
/* PR:X:EllJRE
*/
IDlE: THIS PR:X:EllJRE mvES THE QJRSER'IO THE 0,0 POSITIai
173
1
174
175
176
2
2
2
QJRSER$Qi=l;
177
2
CALL
178
179
2
1
DISPLAY$RAM$POINl'ER=(LINEO AND 7mI);
END IDlE;
IDlE:
POCCELURE;
QJRSER$RJit-:00 I
QJRSER$CX)llJoIN=OO;
I.O.>!D$O.JRSER;
2-123
*/
AP-223
PL/M-51 77ftf THEN
DISPIAY$RAM$POINl'ER=DISPLAY$RAM$POINl'ER-78OH;
ELSE
DISPLAY$RAM$POINl'ER=DISPLAY$RAM$POIN.l'ERI-5OH;
L=DISPLAY$RAM$POINl'ER-CURSE:R$I1m;
IF DISPIAY$RAM(L)=OFlH THEN
/* UXJ( IDR END OF LINE OIARI\CTER*/
00;
CALL FILL;
/* IF THJE FILL WITH SPACES */
DISPLAY$RAM(L)=2OH;
END;
END LINE$FEED;
2-124
AP-223
/*
210
1
211
212
213
214
2
2
2
2
215
216
217
218
219
220
221
222
223
224
225
226
2
3
3
3
3
4
4
4
4
227
228
3
2
229
230
231
2
2
1
3
3
3
PRlCEIlJRE DISPLAY: THIS PRlCEIlJRE WILL TAKE TIlE B:iTE IN !WI LABELED
Ra::ElVE AND PUT IT INID TIlE DISPLAY !WI. */
DISPLAY:
PRlCEIlJRE;
DISPLAY$!WI(DISPLAY$RAM$POINTER)=Ra::EIVE;
IF DISPLAY$!WI$POINTER=7CEll THEN
/* IF END OF !WI */
DISPLAY$IWI$POINTER=OOOH;
/* RAP AIOJND ro BEJGINNI~
ELSE
DISPLAY$RAM$POINTER=DISPLAY$!WI$POINl'ERf-l;
IF aJRSER$COLlM/=4Ell THEN
00;
ClJRSER$COlllMN=OOH ;
L=DISPLAY$RAM$POINTER;
IF DISPLAY$!WI(L)=OFlH THEN
00;
CALL FILL;
DISPLAY$IWI(L)=2OH;
END;
IF aJRSER$RlW=18H THEN
CALL SCOOLL;
ELSE
aJRSER$RlW=OJRSER$HlW+-l;
END;
ELSE
aJRSER$COlllMN=CURSER$COUMfT1;
C!JRSER$(N=1;
CALL uwx::uRSER;
END DISPLAY;
2-125
*/
$E.JECl'
/* PRlCEIlJRE DEX:IPHER: 'nUS PR:lCEnJRE DEXXlDES THE
HOSl' CCMPUTER'S MESSAGES AND DE:I'ERUNES
WIIE1'HER IT IS A DISPLAYABLE CHARACl'ER, a:Nl'lVL ~, OR AN EOCAPE SIQJENCE
THE PRlCEIlJRE THEN 1CrS lIOCQRDIWIN */
232
1
233
2
234
235
236
237
2
3
3
238
DECIPHER:
PRlCEIlJRE;
srARl'$DECIPHER:
~ID$ReCEPTION=O;
3
1=0;
00 WHIloE (I0 THEN
00;
ES=O;
K=FIFO-II
00 J=O 'lO KI
SERIAL(J)=SERIAL(I);
1=1+11
241
242
243
244
245
3
4
4
/*
DISIIBLE SERIAL INTE:RRJPl' NJIloE IIJVItC FIro
/*
KlVE FIro
/*
DII\BLE sERIAL INTE:RRJPl'
246
4
247
4
248
249
3
3
250
3
251
3
2
3
3
3
3
END;
2
3
IF (SERIAL (0) =lBH) THEN
00;
IF (ESC$SSQ=1) AND (FIro<2) THEN
ooro END$DECImER;
K=(SERIAL(l) AND sm)-4OH;
IF (K >0111) AND (K OOH THEN
DO;
TRl\N!MlT$CXJUNI''''l'Rl\N!MlT$COONl't1;
,
IF TR!IN!MlT$CXJUNI'=OFm THEN
/*TSAY BImiEEN FIRSl' CHARACTER AND THE SBnID */
00;
/*SBnID CHARACTER */
CALL TR!IN!MlT;
TR!IN!MlT$CXXJNl'=00;
mo,
ENO;
ELSE
~I
4
4
4
4
4
3
1
0JRSER$QI=1;
ClJRSER$CnlNr=O,
IF TR!IN!MlT$'l'ClOOLE
1 THEN
/* 2 VERt' Fl1l\Im3 BEll'WI!iSN 3m
CALL TR!IN!MlT;
/* 3m TIIRXJGH tmI CHARACTER
TRlIN!MlT$'l'ClOOLE= 1m' TRl\N9UT$'l'ClOOLE;
,
=
mo,
ENO;
mo
Ai1ro$REPFAT;
2-128
ro Nl'H CHARACTER */
*/
AP-223
PL/M- 51 a:MPILER
/***** •••••• ********* STARr MAIN
/*
363
1
364
365
2
2
INIT:
00 L=O
1
1
1
1
1
1
1
1
1
1
1
1
***********.*****.*********/
ro
7Cm;
DISP~$Rl\M(L)=20H;
aID;
/*
366
367
368
369
370
371
372
373
374
375
376
377
PRDG~
BmIN Erl FU'lTING J\SCII CODE FOR BlANK IN TIlE DISPLAY Rl\M; */
INITIALI ZE roINl'ERS, Rl\M BITS, El'C.
*/
ESC$SEQ=O;
SCAN$INT=O;
SERIAL$INT=O;
FIFO=O;
ClJRSER$COONl'=O;
IU:=O;
DATA$TEa!INAL$RFAD'i=1;
Ta:tI=OSH;
LINEO=180OH;
RASl'ER=180OH;
DISP~$Rl\M$roINTER=OOOOH;
TRANSMIT$INT=l;
$IF SWl
378
379
380
2
2
2
00 1=0 ro 7;
381
382
383
384
1
1
1
1
VALI~=O;
LAST~(I)=OOH;
aID;
LAST$SlUfT$KRi=l;
LAST$COO1'R:)L~=1;
LAST$CAP$UXX=1;
$ENDIF
$IF SW2
lCVFLG=0;
S'lIC=O;
ErlFIN=O;
KBDINT=O;
ERlVR=O;
$ENDIF
/*
INITIALIZE TIlE 8276
387
1
1
1
CCMWID$AIDRESS=OOH;
PARAMEll'ER$AlDRESS=4Eli;
PARI\MEll'ER$AlDRESS=58H;
388
1
PARAMEll'ER$AlDRESS=89H;
389
1
PARAMEll'ER$AlDRESS=0F9H;
385
386
*/
RESEr TIlE 8276 */
NORW. lOiS, 80 CIIARl\Cl'ElVlUi */
2 lUi CXlJNl'S PER VERrICAL RETRI\CE
25 lOiS PER FRl\ME */
/* LINE 9 IS TIlE UNDERLINE lOSITIOO
10 LIN&S PER lUi */
/* OFFSET LINE CXlUN1'ER, N:II-'l'RANSPARml' FIElD ATl'RIBl1l'E
/*
/*
/*
2-129
Ap·223
PL/M-51 CXMPILER
CRrIOCAL$LINE THEN
DOl
IF IOCAL$LINE=O THEN
DOl
ENSP=OI
ES=OI
ENDI
/*
PRJGRl\IoMABLE aJRSER BLINK
/* IF IlXAL/LINE
*/
lIAS CHANGED srAIDS
*/
E£.SE
CALL CHEII<$IWJD$RATEI
LIC=IOCAL$LINEI
END 1
$IFSWl
DO WHILE OCAN$INT=O,
IF SERIAL$INT=l THEN
CALL DEX:IFHERI
END 1
/*
WAIT UNITL VERl'ICAL RE'l'RI\CE BEroRE
/* SClINNIm THE KEl{BWlD*/
2-130
*/
AP-223
PL/M-51 mlPILER
427
428
1
1
429
430
1
1
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
2
3
3
3
4
4
4
3
4
4
4
3
4
4
5
5
5
5
4
5
5
5
5
4
455
456
457
5
5
5
458
459
460
6
6
6
461
462
463
464
465
466
467
468
7
7
7
7
8
8
8
8
469
470
471
472
473
474
475
476
477
478
479
8
7
6
5
5
5
5
5
5
CRl'ONl'IDLLER
CALL READER;
IF VALID$KEX =1 AND SIIME=1 AND (IASl'$SHIFl'~E'l=SHIFl'$KEX) AND
(IASl'$CAP$LOCK=CAP$LOCK) AND (IASl'$O:lNTIVL$KEX=1 THEN
00;
VALID$KEX=O;
NEW$KE'l=0;
END;
ELSE
00;
IF CCNl'HJL$KEX=0 TmN
ASCII$KEX= (IDW$SCAN (K) .KE'{ (J» lIND 1m;
ELSE
00;
IF SHIFl'$KEX=O TmN
ASCII$KEX=IDW$SCAN (K+OSH).KE'{ (J);
ELSE
00;
4
3
ASCII$KEX=IDW$SCAN (K).KE'{ (J);
IF (CAP$LOCK=O) lIND (ASCII$KEX>6OH) lIND (ASCII$KEX<7BII) THEN
ASCII$KEX=ASCII$KEX-2OH;
IF LIC=O THEN
00;
IF ASCII$KEX=lBH THEN
F.'lC$SEQ=1;
ELSE
F.'lC$SEQ=0;
END;
END;
END;
IASl'$SHIFl'$KEX =SHIFl'$KEX ;
IASl'$CAP$LOCK=CAP$LOCK ;
IASl'$CCNl'HJL$KE'l=CCNrIDL$KEX ;
VALID$KEX=1;
NEW$KE'l =1;
END;
END;
ELSE
00;
480
481
482
483
484
4
4
4
3
2
VALID$KEX=O;
NEW$KE'l =0;
END;
END;
END;
$ENDIF
2-131
AP-223
priM-51 CDlPILER
CRl'CXNrH)LLER
$E.Ja:T
$IF SW2
. IF SERIAL$INT=1 THEN
CALL OEI:IPHER,
IF KBDINr =1 THEN
00,
IF ERROR =0 THEN
00,
ASCII~=LST~(1),
.N&i$KE'{=1,
CALL l\l1lO$REPFAT,
KIlDINr=O,
END;
ERROR=O,
KBDINr=O,
END;
$ENDIF
485
486
1
1
ooro
SCANNER;
END;
KnlLE ~IOO:
CXDE SIZE
CCN9l'ANl' SIZE
DIRECr VARIABLE SIZE
INDIRECr VARIABLE SIZE
BIT SIZE
BIT-AOORESSABLE SIZE
AllXILIARi VARIABLE SIZE
MAXlMM Sl'l\£]( SIZE
RmISl'ER-BANK (S) USED:
1056 LINES RFAD
o PRJGRI\M ERROR(S)
END OF PL/M-51 CDlPILATICl'I
(Sl'ATIC+OIIERlAYAIILE)
.. 08E6H
22780
.. 0080R
2IHI-00il
00Ht-00il .
108+0011
OIlHtOOH
.. 000011
=OOOCH
o
l2BD
450100t160+
00t00
120
2-132
00
00
00
00
AP·223
CrH
PUSM
PU5M
MOV
MOV
MOY
MOYX
lr.tC
37
:iElB
311
1'01'
POP
POP
H
4(1
U~Eu
,FILL ai76 Ruw BUFFEH
~EhBUF
,STICK SI;RIAL INFOHMATIOr.t INTO THE FIFU
1'81\
,PUSH HEw USt:D B1 I'LM51
ACt;
OOH
HA:>1IiR,L1NI;O
,REINITIALIZI; NA~TER TO LINEO
nAliT~Rt 1, L~r.tt.O+1
HO,.OlH
leLR 81!76 INTEriRUPl rLAG
A,ARII
,INCH CUHSER CUUNT R~GlSTEH
COU~ r
SCA~
,FOR DEBOUNCt: HOuTINE
UOH
IPOP RIiGlSTEHS
AC!;
pSiI
~ErI
41
lie!
III
tlUH~1l1
.. U:iM
.. us ..
PSiI
4~
lib
PU:. ..
IiFL
"US~
",p"
411
15
CSEG
21
OU2~
IIUfFER
IF
CSfG Af( U2,5Hl
24
OU2J !lOe!D
ATCOI3H~
,N~EUEU
117
AC~
ACALL
II~A
IF~LL
1'01'
1'01'
uP"
,POP Rf.GISIEHS
51
51!
POt'
AC~
I"S~
5J
1'01"
uPL
riEII
s~
'3':i .1
:.EJELT
2-133
~216
RUW
Ii II
110;
511
BuF~EH
AP-223
M~S-51
LUC
,.,A\.RiJ
AS~EI"ALE"
OBJ
LH\t.
Ou5o! 30'lqull
Ou5~
~2'1q
Ou57
0115'1
0051;
0115"
OU&II
Oubi!
0064
F
u2UO
20"@o!8
61
Aq9q
~c
6~
(;298
~OUo
(;0':'0
COuo
0060 L2110
OUbA 111uO
Ou&e eSOO
Ou6E 1'8
006F tq
OU7U 1;2,,7
OU7o! FE>
oun b41BII2
007b U200
011711 u5vO
OU7A u2UO
OU7e UOIiO
Ov7E UO~O
01/8u UOUO
01182 UOUI
0i/811 ,32
F
F
F
F
F
F
uOUO
OOb3
uOb2
OOt.O
uOuo
OuAI o!2
:'OuH!.:E
liEreBuFI JNd
CL~
SEre
liVER;
JB
1'0liH
MOV
CL~
U
6'1
PUSH
I'U:l1i
PU:lH
CLI(
MOV
AOU
H
MO~
6~
65
OU8~ COUO
0081 CO~O
oue'l COll2
00811 COel3
008u eouo
0~8F 85UOll2 F
00'1.: 65110b3 F
O~'I~ 78S0
00'17 (4eO
Ou'l'l FO
OU'lA A3
Ou'la UetA
OuA~
S~
6U
~OUI
OU611
ou'lu
Ou'lF
OOAl
OuA5
510
51
5a
CIH ASM
6b
67
,n
lHAN:'MII Bll ~Ul S~l THE~ !.:HEC~ HE~EIV~
,eLR T~A~8MIliSI0~ INIEIiRUPT FLAG
lS~Tb TRA~S INl FOt( PLM51 :'TATUS CHECK
'Iel<,IiCdA\.K ,IF HI NOT SliT GuBACK
uq~~,eVEIi
"C;q~
1 ~I\ 11,1
III
I(1,8ul:l'
Uqll~
P5~
At!.:
001<
t.scSt.G
A, UtR HL
A,r II'C
HO,A
A, HI
UE711
GiRU,"
A,t1taH,OvEHl
MOV
CLH
MOV
CJNE
:lETB ~SC8r;g
7~
7b \lVtRll
INC
FIfe
71
SETB Shlr.T
111
POP
OOH
1'1
POP
-'CC
8U
POI'
PU
t>OP
0111
81'
82 60tlACKI HETI
83
811 alANKI t>USH PBrI
.,~
PUSH ACe
PU5~
811
UPL
PUSH IlPH
87
PUSH 0011
811
~10V
UPl,I.INEU+l
89
I)Pn,lINEO
MOV
'Iv
ft,OV
HO,.SOH
'11
'I': I~OTYE Tl MOV
A,.2011
MOVX .ePTR,A
93
INC
LlPTR
q"
UJNZ HO ,~UlYE'l
'l~
'1b
'17
POP
UOtl
POP
'16
LIP 11
POP
'19
OPL
POP
ACC
lOU
POP
101
Ph
IOo:!
HET
103 +1 ~EJECT
71
7a
13
741
2-134
,R~Au liSuF
,CLEAR RI a IT
,PUSH HEGIUIiRII
US~O
BY PLM51
, ,CLR EliC S~QUENCt. fLAG
,GEl StRIAl rlfO RAM STAHT LUCATION
,AI'IO FI~u HO~ fAI( INTO THE FIFU I'1E ARE
,PuT IT 1I1T0 RU
,CLR Bn 7 OF AC~
,PUT DATA IN FIFO
,IF OATA IS NOT A ESC KEY THEN GO UV~R
,S~l EliC SEQUENCt. fLAG
,MOV FIF~ TO NtXT LOCATION
,SET StRIAL INT bIT FOW PLM51 5T4TUS CHECK
,PQP R~G18lEHS'
,PUSH HE. USED BY I'LM51
',GET l1NEO INFU
,AND PUT IT INTO DHH ,
,NUMbER OF CHAHA(;T~RS IN A lINE
,ASCII SPAcE CHAHACTER
,MOV Te DISPLAY HAM
,IriCR TO ~~XT UI~PI.AY HAM lOCATION
,IF ALI. 5011 lOCATIUNS ARE I';OT FILLEO
,GU DO MORI:
IPUP REGISTEWS
AP·223
M(;S-Sl
"'A~RII
LUC
uBJ
OUAa
OUAA
OUAI.:
OUAt
OUBII
(;OuO
1.01::0
1.0d2
L1M.
10~
10d
109
l1u
111
111:
l1J
11~
111
1111
1l'i
12U
121
12c
12J
1211
OuDCI
OuOo!
OClOli
ouOo
OUOII
OIlOA
OuOIl
00011.
DuEl
a liE It
OIlEo
ouE1
OOE'I
OIlEA
OuEII
COUO
L.OtO
COll2
coa3
COUO
C3
0500113 F
lISCl082 F
43
140
141
Ll8~A
140t
OvEu
OuEf
0llF1
OuF3
OuF!i
OVF1
LlOUO
uOU
UOui!
\l01i0
UOuo
o!2
1411
1~C!O
~ohTlI
lib
1I0UO
",Od3
uOel2
uO':;O
LlOUO
o!2
FO
PU~11
,.S~
PU:;" ACL.
PliO)" liPL.
PU:;" uP"
PU~H
uOn
MOV uPr., rC IN I
MOV IlPL,,.C!~r+l
URL uPI1,lfl0H
MOV ~O,CIjR~Ek
1111
OuCS
OUC7
OuC9
OUCII
OUCu
OuCF
{811F
A3
~L1Nt.:
1011
lQ1
(;Oll~
OuBu /4o!O
OUBf- rO
OuCU A3
OUCl ~8
OUCo! a8~OF8
~OuRL.E
1011
COuO
008~ 115UOb3 F
OOB:! IISUOll2 F
Ou811 113d310
F
OuBd ABUO
16311310
CHTAS,',
AS.:iE~BL.Eh
12~
1211
121
12d FILL:
129
1311
131
13o!
13J
134
13~
130
131
1311
13'1 CaNTi!l
14~
141
1l1li
14'1
l!iu
151
,Sot +I
,Gt::T
kEijISTtR~
CURHE~T
PUSH
PUSH
PUSH
PUSH
PUSH
CLR
t'h
POP
POP
POP
POI'
POP
UOh
OPh
LiPL.
II'CI.
PSII
LUCAT10~
;StT BiT 1~ ~OH hAM ADuRC:SS UECOul~G
,GtT CUR:;Ek ~OLUMN I~FO 10 Tt::LL HO~
,FAR I~TO THt kO~ YOU ARE
,ASC1I S~A~E ChAKACT~R
,MOV TU UISPLAy HAM
,INCH TO ~t::XT UI~PLAY HAM LoCATlUJII
EI~D O~
THt.
LII~E
,PUIH HE&ISTtRS UltD BY PLM5l
ACC
UPL.
IIPH
UOh
C
LiPI1,L.
MO~
MOW LlPL,L+l
URL IIPh,UuH
MOY HO,IIIFH
INC LlPTR
MOV A,.2uH
MOVX .Of'TH,A
INc LlP1R
DJNZ HO,Cut.T2
HEr
UStD BT PLMSl
OlSPLAY HAM
MO~
A,*2UH
MOVX .1lr'TH,A
tNC UPIR
.IN' HO
CJNE HO,.~OH,'O'~Tl ,IF NOT AT THE
, CONTINIJE
POP UOI1
,PUP RtGlS1EHS
POP UP.,
POP UPL
1'01' ACC
POP PS~
HET
,GET BtGINNING Or L.INE RAM LOCATION
,CALCUL.ATEU ~y PLM~l
,lET BIT l~ FON UIIiPLAY RAM AOUREU UECOuE
,lET UP COUNTE" FON SOH LOCATIUNS
' ,GO PAST THE OF1"
,ASCII IPACE CHAHACTtR
,MUVE 10 DII~LAY RAM
,INCH TO NEXT uISPL.AY HAM LOCATION
IIF ALL 19 LUCATIO~I HAVE NOT SEEN FILL.Eu
,THEN CO~TINuE
,PUP R~GUTEHS
ll1j
140
,PIISH
iIIEJEcT
2-135
AP-223
"loS-51
LuC
1'1 AI,; 11",
ASlIEpeLEh
",eJ
u,.,~
15J
15"
15:.
ISb
OuFo
~IDI!
OuFA "5UO~3
OuFIJ 0500112
OIOv c.O
0104 1<3
010~
010~
~Oa31'3
j,O
A3
to
A3
to
OIOb
0107
010&
0101j
OIOA A3
OIOb to
OIOC A3
010~ j,0
0101:. A3
0101' to
011u A3
0111 iO
Oll~
01U
011'1
011:a
o lib
0117
01111
0119
OILA
01111
A3
to
A3
H:~
1605
16 ..
171
17~
173
17 ..
17~
1711
177
170'
183
18'1
01U A3
to
0124 A3
012~ 100
012b A3
0121 iO
012b A3
012'1 j,0
01U A3
01211 EO
012t; A~
01211 to
012t. A3
012~ 1:.0
MO~X
1711
EO
18~
1811
1117
18~
189
l'1U
II/I
I 'I.:!
1'1l
111 ..
1
MOVX
INC
MOVX
INC
MOVX
INC
MQVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
MOVX
INC
vP1R
A, .. CPT"
UP1R
A, .. Cr'T~
IIP1R
A, .. OP1"
LlP1R
A, .. 0i'1tc
UP 1R
A, .. 01'11(
UPIR
A, .. OPTIl
UP1R
A, .. OP1iC
UPIR
A3
~2d
.:2~
OIS~
A, .. Ct'1~
",PIR
A, .. O~l~
IIPlR
.:21
to
,20
01511
015:;
OISb
0157
015b
015'1
015A
OIStl
015(,
015U
A,~Ct'1K
~P1R
A3
t.O
A3
~21
Ols~
015~
IN(;
.:\"
43
0111~
A,~C"1~
"D
';0
0150
0151
uF1R
uFIR
A, .. Ot'l"
uP I R
A, .. C~1 ..
.:10
.:11
Olll~
014t
~OuRI,;E
cOb
014~
Olllij
Olll!:>
01110
01111
01411
014'1
014A
014b
OLlie
014U
C~TASI';
t.0
A3
eO
A3
t.0
A3
100
43
t.0
A3
t.o
A3
t.0
A3
1:.0
A3
t.O
A3
t.O
A3
INC
23U
,,3~
,3i:
,3:S
e311
23~
<30
231
ii3b
c39
cliV
;:41
cae
eaJ
24'1
fOlTI(
uPTR
A... Ol'll(
UPIR
1I •• 01'1IC
UPIR
1I, .. OI'TIC
OPTR
A, .. Ol'lH
UPIR
A... CPTH
OP 1 R'
11 ... 01'11(
upa
..... OI'TI(
uP1R
1I,,,OI'T"
A, .. C~TK
2-138
AP-223
"'1.8-'51 MALRu AS:.E,'Hl.t"
Lue
uBJ
L1~t.
01Qt. A3
01QF t.O
OlAv A3
01Al t.O
OIAe! A3
o1IIj
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,2u
J21
t.lbHTY ;
J2~
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F
F
~2
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327
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~~
1"
,-,0 vX
A,~C~TK
U~I:
~F
~,O
VX
Ih
A,~C~lH
11\1-
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MOV
(;Jt;E
A,UFI1
~,OV
A,L-PL
~,#l~."DuNt'.
(;Ji;E
A,~OIJOM,uC"E
MO~
~,Ov
.ont.R,#18n
,U~Tt.Ii+1 ,#yOh
riET
331
u5u3uO
01B1 b5112uO
OlBA i!2
01B~
F
F
J3~
J3~
3!~
33~
01BII
OIBC
OIBi:.
OlCu
01Cc:
OlC ..
OICb
(;3
t'.5112
HI
c!QQF
HIS
F'5u2
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JQU
u'5113
1101)8
1l0NE:
Bo
kAtlTt.R,Dt'H
"A~Ti:Ii+l,Di'L
IlMADNEI CLR
MOV
ADLl
MOV
JNC
1NC
:iJMP
~41
J4e!
34,S
jD"
j"::>
MO~
MOV
IiET
C
A,LlFI.
A,IIHD
I)PL,A
110 GI;; T Tu
L~tCI\
lIN THE DISFLAY Mt.MURY
uPH
CH:CII
tNLI
2-139
IADU 7'1 Tu tlUFFt.R
~EXT
PUINT~R
018~I.AY
LiNE
AP·223
"I,;S~51
I~A
.. Ru
AS:.E~BLf
Ct!'
OUAIIM
A
OU3~M
A
01AJM
aI/Bull
OuEll'
A
A
A PuB
A PUB
A
HT
EXT
OuFIlM
OuFAM
A
A
048111'1
A
A
01SOIIl
OU!31l
OU8ell
,OU1M
A
A
A
016~M
A
!lOCUM
015111
oueOiM
A PuB
OUHM
OU5'lM
OuHI!
A
A
A
OUOl/H
A
OU"9M
A
OUSc!M
A
EXT
ExT
A
A
ExT
EXT
ExT
ExT
OleUM
017'lM
011:iH
013uH
Ol"~H
Ou2:>H
R~GlSTEIt
IjAI\IKlSJ UStO: u
ASS~"ljLY
~O~PLEre,
he
e"ROR~
EXT
EXT
ExT
A
A
A
A
A
A
EAT
~OUNIJ
2-140
~
S
AP-223
K~Ybfl
.2.1
I~I~-lI '~S-S1 ~A~R~
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A~S~'DL~R I~VuK~~
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uBJ
l1~t
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~
j
~
~
b
1
d
9
IV
II
Ie
I~
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15
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II
Ib
,****************************************************t •• * ••
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; •• *-
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FuR
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i •••••
UNuE~OUEu
t.t_
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2-151
AP-223
APPENDIX B
REFERENCES
1. John Murray and George Alexy, CRT Terminal Design
Using The Intel 8275 and 8279, Intel Application Note
AP-32, Noy., 1977.
2. John Katausky, A Low Cost CRT Terminal Using The
8275, Intel Application Note AP-62, Noy., 1979.
2-152
APPLICATION
BRIEF
AS-38
September 1989
Interfacing the 82786 Graphics
Coprocessor to the 8051
RICK SCHUE
REGIONAL APPLICATIONS SPECIALIST
INDIANAPOLIS, INDIANA
@ Intel Corporation, 1989
Order Number: 270528-002
2-153
AB-3S
Interfacing the 82786 to the 8051 presents some interesting challenges, but can be accomplished with a little
additional logic and software. Since the 82786 looks
like a DRAM controller to the host CPU, wait states
are often required when accessing the coprocessor.
Since wait states are not supported by the 8051, latching transceivers and dummy read and write cycles are
used to communicate with the 82786. Byte swapping is
also required in the external logic to allow the 8 bit
8051 to read an~ write the 16 bit graphics memory
supported by the 82786. This byte swapping is accomplished with the latching transceivers as well. All of the
control logic is implemented in an Intel 5C060 EPLD,
allowing the entire interface to fit into three 24 pin
DIPs.
HARDWARE
Figure I shows the interface between the 8051 bus and
the 82786. Figure 2 shows a typical 8051 CPU design
needed to complete the circuit. In this design the 82786
is mapped into an 8K byte window in 8051 data memory space. ~he upper address bits are used as a "page
select" and are provided by 1/0 pins on the 8051. The
5C060 EPLD contains the control logic for the transceivers and address decoding for the 82786. An equivalent circuit for the EPLD is shown in Figure 3; the
".ADF" file is shown in Figure 4. The 82786 data
memory is mapped into one 8K block (AOOOHBFFEH), the 82786 registers are mapped into another
(8000H-807EH), and the transceivers are mapped into
a third block of memory (COOOH-COOIH).
OPERATION
Operation. of the interface is as follows. For reading the
graphics memory, the 8051 sets the upper address bits
(PORT 1.0-1.3) and then performs a dummy read operation to the desired location in graphics memory
(AOOOH thru BFFEH). The dummy read cycle pro-
vides the address and RD/WR information to the
82786, which runs a cycle and deposits the 16 bit result
into the latching transceivers at the end of the read
cycle, as indicated by SEN. This event clears the BUSY
flip flop in the EPLD. When the BUSY signal goes
inactive, the 8051 reads the low byte from the latching
transceiver at address COOOH and the high byte free
address COOIH.
For write cycles, the 8051 writes the low byte of the
word into the latch at address COOOH and the high byte
into address COOIH. Next the upper address bits are set
with PORTl and a dummy write cycle is performed in
graphics memory at the desired address (AOOOHBFFEH). Like in the read example, the 82786 runs a
memory cycle at this point, enabling the outputs of the
latching transceivers at the proper time in the write
cycle, as indicated by SEN going active.
Accessing the registers inside the 82786 is done in exactly the same fashion, except that the 82786 is addressed in locations 8000H through 807EH. This causes the EPLD to drive the MIlO pin low during these
cycles.
DESIGN NOTES
74F543's are used for the latching transceivers in this
design, although 74HCT646's could be used to reduce
the total power consumption. Some changes to the
EPLD would be required in this case. The interface
assumes that all memory accesses to the 82786 are
word references; accordingly, BHE is grounded at the
82786. All addresses generated by the 8051 must be
even byte addresses, the only byte operations allowed
are the reads and writes to the latching transceivers.
The design shown here incorporates hardware workarounds for the earlier "C-step" 82786; the current
"D-step" part will work in the design as well. Additional information regarding the 82786 can be found in the
"82786 Graphics Coprocessor User's Manual", Intel
publication number 231933.
2-154
inter
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~
B88~SS.8
(
P1.7 ~
P1.6 ; P 1.5
Pl.4
1.3
1-+-.....-tXTAL2 PP1.1
P1.2
!f-
P1.0
RESET
9
PORTl.3}
___ PORT1.2 BANK SELECT
"'"
--'"" PORTl.l
PORTl.O
' . J " o
...L..+5 10ul
'l5'Y
T+
*
RESET
:~ ~~
RO-
WR-
PSEN
A15
A14 26
A13
A12 2!
All 3
A!g
AS
I}>~
SOC31
+h
~I
;,~~
... ... ...
...o
_ <>
A12
21 All
4!~O
~025
2N79~5K
....
Il'TxO
AS
10
A12
All
Al0
A9
AS
~
m
I
w
CO
~=::gA6
IA5
~
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IA3
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IAl
::l
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All
07 9
~ A7
06 5
5 A6
.., 05
AS ...
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6A4~
t;03 6 7 A3....
I\)
- A15
--'""
A14
A13
91 ~UU
~. ~.
tJ
...... c
~ ;
~
II
I
CE2
Vss
1.B:K
AS-232
+5
19 07
-
2
5K
1------....wlr-f""1
lN4148
07
06
05
04
g~
18 06
17 05
16 04
:~ 03
12
~
1
00
g~
00
I"
_
06
05
04
03
02
01
DO
BUSY
270528-2
intJ
AB-38
786esn
rdn
wrn
015
014
786rdn
786rdn
10--+---.
hlbonkn
013n NANDJO----+_t-1~_OI
~o--~-+_t~~i-..;
rdn
oehn
00
lehn
oeln
leln
t----t \OS FQ
.....t---iR
r--.....--t ~)---i... ·~IJO_ _ _ _ _ _o_e_w_n_ _-{
sen
@D-elk
S
786rdwr
L -_ _
~~
>-':"::'::;"::'::':"-'--1
Q~_b_u~sY~_ _ _ _ _ _ _ _ _ _ _ _~BUSYl
SON F
R
__
~
~
270528-3
Figure 3. 8051182786 Control EPLD (5C060-55) Equivalent Circuit
2-157
AB-38
INTEL
August 11, 1987
1-003
o
5C060
8051/82786 Control Logie for 8051 Demo .Board
786 I/O
8000H-807FH
786 Memory
AOOOH-BFFFH
Registers
COOOH,COOIH
OPTIONS: TURBO=ON
PART: 5C060
INPUTS: A15@23,A14@14,A13@11,AO@2,RD/@10,WR/@9,SEN@8,CKK
OUTPUTS: 786CS/@15,786RD/16,OEH/@17,LEH/@18,OEL/@19,LEL/@20,
LEW/@21,OEW/@22,READ@4,BUSY@3
NETWORK:
a15
INP (A15)
a14
INP (A14)
a13
INP (A13)
aO
INP (AO)
rdn
INP (RDIl
wrn
INP (WRIl
sen
INP (SEN)
elk
INP (CLK)
a14n
NOT (a14)
a13n
NOT (a13)
aOn
NOT (aO)
. 786esn
NAND (a15,a14n)
786CS/
CONF (786esn,VCC)
786rdn = OR (786esn,rdn)
786RD/
CONF (786rdn,VCC)
hibankn
NAND (a15,a14,a13n,aO)
10ba.nkn
NAND (a15,a14,a13n,aOn)
oehn
OR (hiba.nkn,rdn)
.
OEH/
CONF (oeh.n,VCC)
lehn
OR (hiba.nk.n,wrn)
LEH/
CONF (leh.n,VCC)
oeln
OR (lobankn,rdn)
OEL/
CONF (oeln,VCC)
leln
OR (lobankn,wrn)
LEL/
CONF (leln,VCC)
oewn
NAND (sen,write)
OEW/ =' CONF (oewn,VCC)
lew = AND (sen, read)
qO
NORF (lew,elk,GND,GND)
ql
NORF (qO,elk,GND,GND)
q2
NORF (ql,elk,GND,GND)
q2n
NOT (q2)
lewn
NAND (ql,q2n)
LEW/
CONF (lewn,VCC)
786wr
NOR (786esn,wrn)
786rd
NOT (786rdn)
READ, read
SOSF (786rd,elk,786wr,GND,GND,VCC)
wr.ite
NOT (read)
786rdwr
OR (786rd,786wr)
BUSY
SONF (786rdwr,elk,sen,GND,GND,VCC)
END$
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Figure 4.
2-158
intJ
APPLICATION
BRIEF
AB-39
December 1987
Interfacing the Densitron LCD to
the 8051
RICK SCHUE
REGIONAL APPLICATIONS SPECIALIST
INDIANAPOLIS, INDIANA
@ Intel Corporation, 1987
Order Number: 270529-001
2-159
AB-39
INTRODUCTION
This application note details the interface between an
80C31 and a Densitron two row by 24 character
LM23A2C24CBW display. This combination provides
a very flexible display foot format (2x24) and a cost
effective, low power consumption microcontroller suitable for many industrial control and monitoring functions.
Although this applications brief concentrates on the
80C31, the same software and hardware techniques are
equally valid on other members of the 80S 1 family, including the 8031, 87S1, and the 8044.
HARDWARE DESIGN
The LCD is mapped into external'data memory, and
looks to the 80C31 just like ordinary RAM. The register select (RS) and the read/write (R/W) pins are connected to the low order address lines AO and AI. Connecting the R/W pin to an address line is a little unorthodox, but since the R/W line has the same set-up
time requirements as the RS line, treating the R/W pin
as an address kept this pin from causing any timing
problems.
The enable (E) pin of the LCD is used to select the
device, and is driven by the logical OR of the 80C31 's
RD and WR signals AND'ed with the MSB of the address bus. This maps the LCD into the upper half of the
64 KB external data space. If this seems a little wasteful, feel free to use a more elaborate address decoding
scheme.
With the address decoding shown in the example, the
LCD is mapped as follows:
Address
Function
Read/Write?
8000H
8001H
8002H
8003H
8004H
Write Command to LCD
Write Data to LCD
Read Status from LCD
Read Data from LCD
Write Only
Write Only
Read Only
Read Only
to
No Access
Undefined results may occur if the software attempts to
read address 8000H or 8oo1H, or write to address
8oo2H or 8003H.
TIMING REQUIREMENTS
The timing requirements of the Densitron LCD are a
little slow for a full speed 80C3I. The critical timing
parameters are the enable pulse width (PW E) of
4S0 ns, and the data delay time during read cycles
(tDDR) of 320 ns. The 8OC31 is available at clock
speeds up to 16 MHz, but at this speed these parameters are violated. Since the 80C31 lacks a READY pin,
the only way to satisfy the LCD timing requirements is
to slow the clock down to 10 MHz or lower. A convenient crystal frequency is 7.3728 MHz since it allows all
standard baud rates to be generated with the internal
timers.
SOFTWARE
The code consists of a main module and a set of utility
procedures that talk directly to the LCD. This way the
application code does not have to be concerned with
where the LCD is mapped, 'or the exact bit patterns
needed to control it. The mainline consists of a call to
initialize the LCD, and then it writes a message to the
screen, waits, and then erases it. It repeats this indefinitely.
The utility procedures include functions to initialize the
display, send data and ads to the LCD, home the cursor, clear the display, set the cursor to a given row and
column, turn thl? cursor on and off, and print a string of
characters to the display. Not all the functions are used
in the software example.
REFERENCES
INTEL Embedded Controller Handbook, 210918
INTEL PL/M-Sl User's Guide, 121966
DENSITRON Catalog LCDMD-C
FFFFH
2-160
t
+5
Vee
GND
I\)
,
.....
(j)
.....
~
...
!!
..
.
(.)
CD
C
l>
N
II)
:'"
+5
~ 5-
116
6
15
9
._
4
o
l1J
'"
CD
~
A7
A6
66 AS
(.0)
N
~
~
-12
7 A4
8 A3
9 A2
~Al
-AO
+5
27C64
6264LP
(OPTIONAL)
270529-1
inter
Main_module:
AB·39
DO:
Delay: PROCEDURE (count) EXTERNAL:
DECLARE
count
WORD:
END Delay:
Initialize_LCD: PROCEDURE EXTERNAL:
END Initialize_LCD:
Clear display: PROCEDURE EXTERNAL:
END Clear_display:
LCD_print: PROCEDURE EXTERNAL:
END LCD_print:
'
DECLARE LCD_buffer
(48)
BYTE
sign_on_message
(*)
BYTE
('INTEL 8051 DRIVES LCD - ,
'2 ROWS BY 24 CHARACTERS ').
i
BYTE:
PUBLIC.
CONSTANT
/* This is the start of the program */'
/* Initialize the LCD */
CALL Initialize_LCD:
CALL Clear_display:
/* Now enter an endless,loop to display the message */
DO WHILE 1:
/* Copy the message to the buffer */
DO i = 0 to 47:
LCD_buffer(i)
sign_on_message (i) :
END:
=
/* Now print out the buffer to the LCD */
CALL LCD_print:
/* wait a while */
CALL Delay(2000) ;
/* now clear the screen */
CALL Clear_display: '
END:
/* of DO
WHI~E
*/
END Main_module:
Main Module
2-162
inter
AB-39
LCD_IO_MODULE: DO;
DECLARE LCD_buffer (48)
LCD_command
LCD_data
LCD_status
LCD_busy
i
BYTE
EXTERNAL,
BYTE
AT (08000H) AUXILIARY,
BYTE
AT (08001H) AUXILIARY,
BYTE
AT (08002H) AUXILIARY,
LITERALLY'lOOO$OOOOB',
BYTE;
Delay: PROCEDURE (msec) PUBLIC;
/* This procedure causes a delay of n msec */
DECLARE msec
i
IF'msec> 0 THEN DO;
DO i
0 to msec - 1;
CALL Time(5) ;
END;
=
WORD,
WORD;
/* .2 msec delay */
END Delay;
LCD_out: PROCEDURE (char) PUBLIC;
DECLARE char BYTE;
/* wait for LCD to indicate NOT busy */
DO WHILE (LCD_status AND LCD_busy) < > 0;
END;
/* nOW send the data to the LCD */
LCD_data
char;
=
END LCD out;
LCD Driver Module
2-163
inter
AB·39
LCD_command_out: PROCEDURE (char) PUBLIC;
DECLARE char BYTE;
/* wait for LCD to indicate NOT busy */
DO WHILE (LCD_status AND LCD_busy) < > 0;
END;
/* now send the command to the LCD */
LCD_command
char;
=
Home_cursor: PROCEDURE PUBLIC;
CALL LCD_command_out(OOOO$OOlOB) ;
END Home_cursor;
Clear_display: PROCEDURE PUBLIC;
CALL LCD_command_out (OOOO$OOOlB);
END Clear_display;
Set_cursor: PROCEDURE (position) PUBLIC;
DECLARE
position
BYTE;
=
IF position> 47 THEN position
47;
IF position < 24 THEN CALL LCD_commapd_out(080H + position) ;
ELSE CALL LCD_command_out(OCOH + (position - 24));
END Set_cursor;
C~rsor_on:
CALL
PROCEDURE PUBLIC;
LCD~command_out(OOOO$llllB)
;
END Cursor_on;
Cursor_off: PROCEDURE PUBLIC;
CALL LCD_command_out(OOOO$llOOB);
END Cursor_off;
LCD Driver Module (Continued)
.2-164
inter
AB·39
LCD_print: PROCEDURE PUBLIC;
/* This procedure copies the contents of the LCD_buffer
to the display */
CALL SeLcursor(O) ;
DO i
0 to 23;
CALL LCD_out(LCD_buffer(i});
END;
CALL Set_cursor(24) ;
DO i
24 to 47;
CALL LCD_out(LCD_buffer(i));
END;
=
=
END LCD_print;
Initialize_LCD: PROCEDURE PUBLIC;
CALL
CALL
CALL
CALL
CALL
CALL
CALL
CALL
Delay(lOO) ;
LCD_command_out(38H) ;
LCD_command_out(38H) ;
LCD_command_out(06H) ;
Clear_display;
Home_cursor;
Cursor_off;
Set_cursor(O} ;
/* Function Set */
/* entry mode set */
END Initialize_LCD;
LCD Driver Module (Continued)
2-165
APPLICATION
BRIEF
AB-40
December 1987
32-Bit. Math Routines for the 8051
RICK SCHUE
REGIONAL APPLICATIONS SPECIALIST
INDIANAPOLIS, INDIANA
Order Number: 270530-001
® Intel Corporation, 1987
2~166
inter
AB-40
Here are some easy to use 16- and 32-bit math routines
that take the pain out of calculations such as PID
loops, AID calibration, linearization calculations and
anything else that requires 32-bit accuracy.
, The package is written to interface with PL/M-51. Parameters are passed as 16-bit words to the routines,
which perform operations on a 32-bit "accumulator"
resident in memory. The foJlowing functions are performed:
Load_16 (word_param)
Loads a 16-bit -RD into the low half of the 32-bit "accumulator", zeros upper 16 bits of accumulator.
Load_32 (word_hi,word_lo)
Loads word_hi into upper 16 bits of accumulator, word
lo_into Lower 16 bits.
Low_16
Returns the lower 16 bits of the accumulator, bits 0
through 15.
Sub_16 (word_param)
Similar to Add_16 but for subtraction.
Add_32 (word_hi,word_lo)
Forms a 32-bit value for word_hi and word_lo and
adds it to the accumulator.
Sub_32 (word_hi,word_lo)
Similar to Add_32 but for subtraction.
APPLICATION
Typical applications have 16-bit "input" values and
produce 16-bit "output" values, but require 32-bit values for intermediate results. An example would be
reading a 12-bit AID, performing some gain and offset
calculation on the raw AID data to produce a calibrated 16 bit result. Doing this is a simple task with this
math package.
CALL Add_16 (offset_value);
Mid_16
Returns the middle 16 bits of the accumulator, bits 8
through 23.
CALL Mul_16 (gain_factor);
,. gain is in units of 1,256 .,
High_16
Returns the upper 16 bits of the accumulator, bits 16
through 31.
MuLl6 (word_param)
Multiplies the 32-bit accumulator by the 16-bit word
supplied, result left in accumulator.
Div_16 (word_pararn)
Divides the 32-bit accumulator by th~ 16-bit word supplied, result left in accumulator.
Add_16 (word_param)
Adds the 16-bit word supplied to the 32-bit accumulator.
result = Mid_16;
In this example the accumulator was loaded with the
raw AID value and then the offset was applied. The
gain3actor was "pre-multiplied" by 256 (8 bits), giving
it a granularity of 11256. The result was extracted from
the "middle" 16 bits of the accumulator (bits 8 to 23) to
account for the scaling factor of 256 introduced in the
multiply step.
The package requires about 384 bytes of ROM and 30
bytes of RAM. Individual routines can be deleted to
conserve RAM if they are not used.
2-167
intJ
AB·40
CODE SOURCE LISTINGS
CODE SOUICE LISTINGS
,
PUBLIC
PUBLIC
PUBLIC
PUBLIC
PUBLIC
PUBLIC
PUBLIC
PUBLIC
PUBLIC
;
Load_16, ?Load_16?byte
Load 32, ?Load 32?byte
Mul 16, ?Mul 16?byte
Div-16, ?Div-16?byte
Add-16, ?Add-16?byte
Sub-16, ?Sub-16?byte
Add-32 , ?Add-32?byte
Sub-32, ?Sub-32?byte
r.ow:16, Mid~16, High_16
Math 32 Data
Math:32:Code
DATA
COOE
;
RSEG
Math 32 Data
?Load 16?byte: -OS 2
?Load:32?byte: OS 4
?ml_16?byte:
OS 2
?Div_16?byte:
OS 2
OS 2
?Add_16?byte:
?Sub_16?byte:
OS 2
?Add 32?byte:
OS 4
?Sub:32?byte:
OS 4
OP 0:'
OS 1
ap-l:
OS 1
OP-2:
OS 1
ap-3:
OS 1
'IMP
0
'IMP-l
'IMP-2
'IMP:3
;
OS
OS
OS
OS
1
1
1
1
RSEG
270530-1
2-168
inter
AB-40
Load 16:
;Lead the lower 16 bits of the OP registers with
OP 3,fO
I'fJV
OP-2,fO
MOV
~V
O(), ?Load_16?byte
OP_O,?Load_i6?byte + 1
I'fJV
~~e
value supplied
RE:l'
Load 32:
;Lead
MOV
MeV
MOV
MeV
RE:l'
all the OP registers with the value supplied
OP 3,?Load 32?byte
OP-2,?Load-32?byte + 1
OP-l,?Load-32?byte + 2
OP-0,?Lead-32?byte + 3
-
-
Low 16:
-iReturn the lower 16 bits of the OP registers
MOV
R6,OP 1
MOV
R7,OP-0
RE:l'
-
Mid 16:
-;Return the middle 16 bits of the OP registers
MeV
R6,OP 2
MeV
R7,OP:)
RE:l'
High 16:
;Return the high 16 bits of the OP registers
MOV
R6,OP 3
MOV
R7,OP=Z
RE:l'
Add
16:
-iAdd the 16 bits supplied by the caller to the OP registers
CLR
mv
ADDC
MOV
MeV
ADOC
MOV
MOV
AOOC
MOV
MOV
/\DOC
I!IJV
C
A,OP 0
A,?Add_16?byte + 1
OP O,A
A,'OP 1
A,?Add_16?byte
OP I,A
A,OP 2
1'.,40OP 2,1'.
A,OP 3
1'.,40OP_3,A
;1ow byte first
;high byte + carry
;propagate carry only
;propagate carry only
RE:l'
270530-2
2-169
inter
AB-40
Add 32:
-;Add the 32 bits supplied_ by the caller to tne OP registers
CLR
C
ADOC
A,OP 0
A,?Add 32?byt= + 3
OP O,A-
rov
I'IJV
I:'IJV
AOOC
I'CN
I'DV
AOOC
I'DV
I'CN
ACre
I'CN
;lowest byte flrst
A,OP 1
A,?Add 32?byte + 2
OP 1,A-
;mid-lowest byte + carry
A,OP 2
A,?Add 32?byte + 1
OP 2,AA,OP 3
A,?Add 32?byte
OP_3,A-
;mid-highest byte + carry
;highest byte + carry
RET
Sub 16:
-;Subtract the 16 bits supplied by the caller from the OP registers
CLR
I:'IJV
C
SUBS
A,?sUb 16?byte + 1
OP O,A-
I'DV
I'DV
SUBS
l"I:N
I'CN
SUBB
l"I:N
l'DV
A,OP 0
;low byte first
A,OP 1
A, ?SUb 16?byte
OP 1,A-
A,OP 2
A,tO-
; high byte + carry
;propagate carry only
OP 2,A
SUBB
A,OP 3
A,.O-
I'CN
OP_3,A
;propagate carry only
RET
Sub 32:
-;Subtract the 32 bits supplied by the caller fran the OP registers
CLR
C
I'CN
I'CN
A,OP 0
A,?SUb 32?byte + 3
OP O,A-
I:'IJV
A,OP 1
SUBS
A,?SUb 32?byte + 2
OP l,le
SUBB
I'CN
I:'IJV
SUBS
I:'IJV
I'CN
SUBB
I'CN
;lowest byte first
;mid';lowest byte + carry
A,OP 2
A,?SUb 32?byte + 1
OP 2,AA,OP 3
A,?SUb 32?byt;
OP_3,A-
;mid-highest byte + carry
;highest byte + carry
RET
270530-3
2-170
AB-40
Mul 16:
-iMultiply the 32 bit OP with the 16 value supplied
I:'DV
'll1P 3,10
iclear out upper 16 bits
I:'DV
niP-2, to
;Genecate the lowest byta of the result
I:'DV
S,OP a
MaV
A,?HUl l6?byte+l
MlJL
lIB
-
I:'DV
'll1P a,A
ilow-order result
I:'DV
'll1P-l,a
ihigh order result
iNa.I generate the next higher order byte
I:'DV
a,op
I:'DV
A, ?Mill 16?byte+l
!f1L
ADD
I:'DV
lIB
1
-
A, 'll1P 1
ilow-order result
niP l-;A
save
I:'DV
A,aget high-order result
ADOC A,niP 2
include carry from previous operation
I:'DV
niP 2-;A
save
JNC
Mul-loopl
INC
niP-3
propagate carry into niP_3
Mul loopl:
-I:'DV
S,OP a
I:'DV
A,?HUl l6?byte
!ilL
lIB
ADO
A,niP 1
'll1P l-;A
A,aA, 'll1P 2
'll1P 2-;A
Mul-loop2
'll1P:)
I:'DV
I:'DV
ADOC
I:'DV
JNC
INC
Mul loop2:
-; Now
-
i la.l-order
result
save
get high-order result
include carry from previous operatioo
save
propagate carry into 'll1P_3
start IoOrking on the 3rd byte
I:'DV
S,OP 2
MaV
A,?HUl l6?byte+l
MUL
ADD
I:'DV
I:'DV
A, 'll1P 2
'll1P 2-;A
A, a-
ADOC
A,'IMP 3
I:'DV
i Now
I:'DV
I:'DV
lIB
-
niP 3-;A
the other half
S,OP 1
A,?HUl_16?byte
MlJL
AS
ADO
MaV
MaV
ADOC
'IMP
;low-order result
save
get high-order result
include carry from previous operation
save
A,niP 2
;low-order result
2-;A
; save
A,Si get high-order ,result
A, 'll1P_ 3
; include carry from previous operation
I:'DV
'll1P 3, A
; save
; Now finish off the highest order byte
/!IN
S,OP 3
I:'DV
A,?Mul_16?byte+l
270530-4
2-171
AB-40'
~
AS
ADD
A,TMP_3
;low-order result
TMP 3,A
; save
; Forget about the high-order result, this is only 32 bit math!
HOV
I'DV
I'DV
~
a,op
2
A,?MUl l6?byte
AS
-
ADD
A,TMP 3
;low-order result
I'DV '
'IMP 37A
; save
; Now 'ole are all done, nove the TMP values back into OP
HOV
OP O,'IMP 0
HOV
OP-l,'iMP-l
HOV
OP-2,TMP-2
HOV
OP-3,'IMP-3
REI'
-
270530-5
2-172
AB-40
Div 16:
-;This divides the 32 bit OP register by the value supplied
I:'OV
R7,.0
:-OV
R6,fO
; zero out partial r~mainder
I:'OV
'IMP 0,.0
:-OV
'IMP-l,iO
l"l:N
'IMP-2,fO
I:'OV
'IMP-3, to
I:'OV
Rl,?Div 16?byte
;load divisor
I:'OV
RO,?Div-16?byte+l
l"l:N
RS,'32 ;loop count
;This begins the loop
Div loop:
-CALL
tiN
RU:
I'PV
I'PV
Shift 0
A,R6 -
;shift the dividend and return MSB in C
;shift carry into LSB of partial remainder
A
R6,A
A,R7
au:: A
l"l:N
R7,A
;now test to see if R7:R6 >= Rl:RO
CLR
I'PV
C
CLR
C
A,R7
; subtract Rl from R7 to see if Rl < R7
A,Rl
; A = R7 - Rl, carry set 1f R7 < Rl
JC
Cant sub
oat this poInt R7>Rl or R7=Rl
JNZ
Can sub
;junp if R7>Rl
;if R7 .. aI, test for R6>=RO
suea
A,R6
A,RO
; A = R6 - RO, carry set if R6 < RO
JC
Cant sub
Can sub:
-;subtract the divisor from the partial remainder
l"l:N
SUBS
CLR
C
I:'OV
A,R6
A,RO
R6,A
A,R7
A,Rl
R7,A
SUBB
I'PV
I'PV
SUBB
l"l:N
SE'I'B
JMP
A =
R7 - Rl - Borrow
shift a 1 into the quotient
C
Quot
Cant sub:
;shift a
CLR
A=R6-RO
a into
the quotient
C
Quot:
;shift the carry b1: lnto the quotient
Shift Q
; Test for COmpetlcn
DJNZ RS,Div loop
; Now we are
done, rove the 'IMP values back into OP
l"l:N
OP O,TMP 0
I'PV
OP:l,'IMP:l
CALL
all
270530-6
2-173
infef
I'DV
I'DV
RET
AB-40
OP 2,'IMP 2
O(),'IMP:)
Shift D:
;shift the dividend one bit to the left and return the ~B in C
CLR
C
I'DV
RLC
I'DV
1'01
RLC
I'DV
A,OP 0
A OP O,A
A OP 1,A
I'J)V
. A,OP 2
RLC
1'01
1'01
RLC
1'01
A OP 2,A
A,OP 1
A,OP 3
A OP_3,A
RET
Shift Q:
;shift the quotent one bit to the left and shift the C into LSB
1'01
RIC
I'DV
1'01
RIC
1'01
I'DV
RLC
I'DV
A,'IMP 0
A
'IMP O,A
A,'lMP 1
A 'IMP 1,A
A,'lMP 2
A
'IMP 2,A
RLC
A,'lMP 3
A
-
I'DV
'IMP_3,A
I'J)V
RET
270530-7
2-174
APPLICATION
BRIEF
AB-12
October 1987
Designing a Mailbox Memory for
Two 80C31 Microcontrollers Using
.
EPLDs
K. WEIGL & J. STAHL
INTEL CORPORATION
MUNICH, GERMANY
© Intel Corporation, 1987
Order Number: 292016-002
2-175
AB-12
INTRODUCTION
Very often, comple;x systems involve two or more microcontrollers to fulfill the requirements defined by a
given objective. Since the nature of microcontrollers
does not allow for easy dual-port memory design (no
"READY" input; no "HOLD/HLDA" interface; portoriented I/O etc.), design engineers are faced with the
problem of interchanging information (data and status)
between those microcontrollers. This application brief
describes the design of a mailbox for exchanging information between two 80C3ls, using a SC060 H-EPLD
as a "back-to-back" register, and a SC031 H-EPLD as
an arbitration vehicle to control the actions of the
CPUs.
THE 5COGO MAILBOX
The SC060 allows for independent clocking of 8 macrocells on each side of the chip, the two clock inputs are
used to clock data from the microcontroller bus into
the chip. To read the data written into the mailbox by
one of the controllers, the RDA- (controller A is reading) or RDB- (controller B is reading) line must be
pulled low by activating the read command (IRD). In
order to avoid spurious read-cycles, the /RD commands from both microcontrollers are logically
"ORed" together with an active high CS-signal (Chip
Select) inside the SC060. The CS-signal for both ports is
derived from address line AI5. Therefore, whenever
AI5 becomes a logic "I" (true), the mailbox is activated and ready to take or submit data.
Address range for the mailbox: FOOO Hex to FFFF
Hex
(Upper 12 kbyte)
In this application, the 16 macrocells of the SC060 are
grouped into two sets of 8 so called "ROlF" (register
output with input feedback) primitives to implement
the two 8 bit bus interfaces needed. The grouping is
done according to the following picture.
5C060
2-176
inter
AB-12
THE 5C031 "MAILBOX CONTROLLER"
To keep the two microcontrollers informed about the
status of their mailbox, the 5C031 is programmed to
supply the following signals to both controllers:
/OBFA: "OUTPUT BUFFER FULL" FOR Me A
/OBFB: "OUTPUT BUFFER FULL" FOR Me B
/IBEA: "INPUT BUFFER EMPTY" FOR Me A
/IBEB: "INPUT BUFFER EMPTY" FOR Me B
/INTA: INTERRUPT TO Me A
/INTB: INTERRUPT TO Me B
The next section will discuss the meanings of these signals in more detail.
Output Buffer Full: This flag is set whenever the controller writes into its own output
buffer. The flag remains valid, until
the second controller has read the
data. The flag is automatically reset to its inactive state when this
read cycle is accomplished.
NOTE:
Both controllers can access (read or write) the mailbox simultaneously.
Input Buffer Empty: This flag indicates that there is no
message in the mailbox. The flag
will become inactive as soon as
one microcontroller places a message for the other one (or vice versa).
Example:
IIBEA
remains
"LOW" until microcontroller B
places a message for controller A
into the mailbox for A. IIBEA
will go "HIGH" as soon as controller B has accomplished its
write cycle, and will not go
"LOW" again until microcontroller A has read the message.
Interrupt: The 5C031 is programmed to supply interrupts to both microcontrollers involved, on
one of the following events.
1. The IOBF flag of the opposite microcontroller becomes active; e.g. if controller A is
placing a message for controller B, controller
B receives an interrupt the same time as
IOBFA becomes valid or vice versa.
2. The IIBE flag of the opposite microcontroller goes active, indicating that this controller has received the message; e.g. if controller B reads the message stored by controller A, its IIBEB flag goes active and controller receives an interrupt indicating that
the buffer is empty.
The signals described above are necessary to accomplish a secure handshake without overwriting messages
accidentally. In addition to that, the 5C031 is issuing
the actual write commands for the two register sets inside the 5C060. The /WRA and /WRB signals are results oflogical "AND" functions between the appropriate CS- and /WR signals from the microcontrollers.
Therefore, spurious write cycles are unlikely to happen.
NOTE:
This design can also be efficiently implemented in a
single 5CBIC EPLD.
2-177
AB-12
B
A
AOO-A07
PO
"
ill
i'r
L.
74HCT373
~
~-~~ ~r
CE OE
ALE
A8-A15
P2
PSEN
r-
"
I'
-
-
ill
00-07
00-07
AO-A7
AO-A7
.~
~
027C64
027C64
A8-12
A8-12
OECS
CSOE
~
.
~r ~~
OE CE
~
~L.
~~
74HCT373
AOO-A07
.:"\1 PO
.
-
~
ALE
A8-A15
P2
I---:- l-
PSEN
A
00-07
~
P80C31BH
00-07
AO-A7
AO-A7
RAM
RAM
~
P80C31BH
It
A15
A8-12
iID
WR
A8-12
CS
CS
WR
I II
Rii P3.7
WRP3.6
A15
iID
II-
RDP3.7
WRP3.6
5C060
lOA
0-7
lOB
0-7
ROA
CSA
WA
I"'"
ROB
CSB
WB
~-
I----'
f-
5C031
-
WA
WRA
' - - - ROA
RST
--
P3.4
P3.5
P3.2INTO
RESET
r
WB
WRB
ROB
CSA
CSB
OBrA OBrB
IBEA IBEB
INTA INTB
RST
OE
Block Diagram
2-178
-P3.4
P3.5
INTOP3.2
1
RESET
292016-1
AB-12
5C060 "BACK TO BACK REGISTER"
WB
lOAD
~~ -r-
t-
L
~
o-
10Al
~-
_~
~
r..
1
A
L
~
-
_L
~
r..
-
'-
IOA3
10M
10AS
IOA6
1. . .
r..
1
1
1
A
t....
A
L
A
--
L
1
-
-r-
L r-r--
_ ....
1/
-r-
_....
r--r-
L
A
--
-
~
...
L
"
10Bl
"
IOB2
"
IOB3
~
~
~
....
IOB4
....
IOB5
....
IOB6
....:r
.... 0 -
L
r-r-~I--
....:r
... 0 -
L
r-~
...1
... ' -
0 - ...
IOA7
lOBO
'-
'-
IOA2
~~
L ...
'--
~
....
IOB7
~
-"-,
WA
ROA
CSA
La:
:V-
2-179
ROB
CSB
292016-2
AB-12
5C031 "MAIL BOX CONTROLLER"
WRA
CSA
-_:::;~~'-""J---"""--------------D- WA
JO--IBEB
ROB
OBrA
INTA
RST
INTB
OBrB
ROA
IBEA
CSB
WRB
WB
OE
292016-3
2-180
inter
AB-12
5C060 REGISTER ADF
JUERG
INTEL
March
80C31
STAHL
ZUERICH
27, 1986
MAILBOX MEMORY USING 5C060 / 5C031
1
********************
** EXAMPLE .ADF **
********************
5C060
LB Version 3.0, Baseline 17x, 9/26/85
PART: 5COSO
INPUTS: WB81, CSA82, CSB814, nRDA811, nRDB823, WA813
OUTPUTS: 1087815, IOA7810, IOBS81S, IOAS89,
rOB5817, IOA588, IOB4818, IOA487,
IOB3819, IOA386, IOB2820, IOA285,
IOB1821, IOA184, IOB0822, IOA083
NETWORK:
IOB7,DB7
ROlF (DA7,WAC,GND,GND,RDBC)
IOA7,DA7
ROlF (DB7,WBC,GND,GND,RDAC)
IOB6,DB6
ROlF (DA6,WAC,GND,GND,RDBC)
IOA6,DA6
ROlF (DBS,WBC,GND,GND,RDAC)
IOB5,DB5
ROlF (DA5,WAC,GND,GND,RDBC)
IOA5,DA5
ROlF (DB5,WBC,GND,GND,RDAC)
IOB4,DB4
ROlF (DA4,WAC,GND,GND,RDBC)
IOA4,DA4
ROlF (DB4,WBC,GND,GND,RDAC)
IOB3,DB3
ROlF (DA3,WAC,GND,GND,RDBC)
IOA3,DA3
ROlF (DB3,WBC,GND,GND,RDAC)
IOB2,OB2
ROlF (DA2,WAC,GND,GND,RDBC)
IOA2,DA2
ROlF (DB2,WBC,GND,GND,RDAC)
IOB1,OBl
ROlF (DA1,WAC,GND,GND,RDBC)
rOA1,OAl
ROlF (DB1,WBC,GND,GND,RDAC)
IOBO,DBO
ROlF (DAO,WAC,GND,GNO,RDBC)
IOAO,DAO
ROlF (DBO,WBC,GND,GND,RDAC)
WAC = INP (WA)
RDBC = AND(CSBI,RDBI)
WBC
INP (WB)
RDAC = AND(CSAI,RDAI)
CSB! = INP (CSB)
nRDBI
INP(nRDB)
nRDAI
INP(nRDA)
CSA!
INP(CSA)
RDAI
NOT(nRDAI)
RDBI
NOT(nRDBI)
=
=
=
=
END$
292016-4
2-181
intJ
AB-12
5C060 REGISTER LEF
JUERG
INTBL
March
80C31
STAHL
ZUERICH
27, 1985
MAILBOX MEMORY USING 5COSO / 5C031
1
********************
** BXAMPLE .LEF **
********************
5COSei
LB Version 3.0, Basel iDe 17x, 9/2S/85
LEF VersioD 1.0 BaseliDe 1.51 02 Feb 1987
PART:
5COSO
INPUTS:
WB81, CSA82, CSB814, nRDA811, nRDB823, WA813
OUTPUTS:
IOB7815, IOA7810, IOB6816, IOA689, IOB5817, IOA588, IOB4818, IOA487,
IOB3819, IOA386, IOB2820, IOA285, .IOB1821, IOA184, IOB0822, IOA083
NETWORK:
WBC = INP(WB)
WAC = IHP(WA)
CSAI = INP(CSA)
CSBI = INP(CSB)
nRDAI = INP(nRDA)
nRDBI = INP(nRDB)
IOB7, DB7
ROIF(DA7, WAC, GND, GND, RDBC)
IOA7, DA7
ROIF(DB7, WBC, GND, GND, RDAC)
lOBS, DBS
ROIF(DA6, WAC, GND, GND, RDBC)
IOAS, DAS
ROIF(DB6, WBC, GND, GND, RDAC)
IOB6, DB5
ROIF(DA5, WAC, GND, GND, ROBC)
IOA6, DA6
ROIF(DB5, WBC, GND, GND, RDAC)
IOB4, DB4
ROIF(DA4, WAC, GND; GND, RDBC)
IOA4, DA4
ROIF(DB4, WBC, GND, GND, RDAC)
I,OB3, DB3
ROIF(DA3, WAC, GND, GND, RDBC)
IOA3, DA3
ROIF(DB3, WBC, .GND, GND, RDAC)
IOB2, DB2
ROIF(DA2, WAC, GND, GND, RDBC)
IOA2, DA2
ROIF(DB2, WBC, GND, GND, RDAC)
lOBI, DB1
ROIF(DA1, WAC, GND, GND, ·RDBC)
IOA1, DA1
ROIF(DB1, WBC, GND, GND, RDAC)
lOBO, DBO
ROIF(DAO, WAC, GND, GND, RDBC)
10AO, DAD
ROIF(DBO, WBC, GND, GND, RDAC)
EQUATIONS:
RDAC
CSAI
nRDAI';
*
RDBC
CSB~
* nRDBI';
END$
292016-5
2-182
inter
AB-12
5C060 REGISTER UTILIZATION REPORT
Logic Optimizing Compiler Utilization Report
FIT Ve~aion 1.0 Baseline 1.Oi 2/6/87
*****
Design implemented successfully
JUBRG STAHL
INTEL ZUERICH
Ma~ch 27, 1986
80C31 MAILBOX MEMORY USING 5C060 / 5C031
1
5C060
"""""""""""'"
"
EXAMPLE .RPT FILE "
"""""""'*"""'"
LB Veraion 3.0, Baseline 17x, 9/26/85
5C060
WB
CSA
10AO
lOA!
IOA2
IOAJ
10A4
10A5
IOA6
IOA7
nRDA
GND
-
I
2
3
- 4
- 5
- 6
- 7
- 8
- 9
-:10
-: II
-:12
-
24:23:22:21: 20:19:18:17:16:15:14: 13:-
Vcc
nRDB
lOBO
lOBI
IOB2
IOB3
10B4
IOB5
IOB6
10B7
CSB
WA
'*INPUTSU
Na.e
Pin
WB
Resource
MCell II
PTerms
MCella
Feeds:
Oil
Clea~
INP
Clock
CLKI
CSA
2
INP
9
10
11
12
13
14
15
16
nRDA
11
IMP
9
10
11
12
13
14
15
16
GND
12
GND
1
2
3
4
5
6
7
8
9
292016-6
2-183
inter
AB·12
5C060 REGISTER UTILIZATION REPORT (Continued)
10
11
12
13
14
15
16
WA
13
INP
CSB
14
INP
CLK2
1
2
3
4
5
6
7
8
nRDB
23
INP
1
2
3
4
5
6
7
8
Vee
24
Vee
Na.e
Pin
Resource
IOAO
3
10Al
IOA2
IOA3
"OUTPUTSn
,
PTerm.
ROlF
9
1/ 8
4
ROlF
10
1/ 8
5
ROlF
11
1/ 8
3
6
ROlF
12
1/ 8
4
IOA4
7
ROlF
13
1/ 8
5
IOA5
8
ROlF
14
1/ B
6
IOA6
9
ROlF
15
1/ B
7
IOA7
10
ROlf
16
1/ B
8
IOB7
15
ROlF
8
1/ 8
16
IOB6
16
ROlf
7
1/ 8
15
14
HCell
Feeds:
MCells
lOBS
17
ROlf
6
1/ B
18
ROlf
5
1/ 8
13
1083
19
ROlF
4
1/ 8
12
1082
20
ROlf
1/ 8
11
lOBI
21
ROlf
2
1/ 8
10
11 8
9
22
ROlF
Clear
Clock
2
1084
[080
OB
292016-7
. All Resources used
nPART UTILIZATIONn
100lr
100lr
12'
Pine
MacroCelb
Ptera.
292016-8
2-184
inter
AB-12
5C031 ARBITER ADF
JUBRG
INTBL
Msrch
80e31
STAHL
ZUBRICH
28, 1986
MAILBOX MBMORY USING 5C06Q / 5C031
********************
** BXAMPLE .ADF **
********************
2
5C031
LB Version 3.0, Baseline 17x, 9/26/85
PART: 5C031
INPUTS: RST,nWRA,nRDB,CSA,nRDA,nWRB,eSB,nOB
OUTPUTS: WA,nOBrA,nIBBB,nINTA,nINTB,nOBFB,nIBBA,WB
NBTWORK:
nWRA = INP(nWRA)
nRDB = INP(nRDB)
RST = INP(RST)
eSA = INP(CSA)
nRDA = INP(nRDA)
nWRB = INP(nWRB)
eSB
INP(eSB)
nOB
INP(nOB)
WRA
NOT(nWRA)
WRB
NOT(nWRB)
RDA
NOT(nRDA)
RDB
NOT(nRDB)
OE = NOT(nOE)
nRST = NOT(RST)
WA = CONF(WAd,YCC)
WAd = AND(CSA,WRA)
WB = eONF(WBd,YeC)
WBd = AND(eSB,WRB)
nRB = NAND(RDB,eSB)
nRA = NAND(RDA,eSA)
nWAd = NOT(WAd)
nWBd = NOT(WBd)
nOBFA,nOBFA
COCF(nOBFAd,OE)
nOBrB,nOBFB = COer(nOBFBd,OE)
nIBEA,nIBEA
COCF(nIBBAd,OE)
nIBBB,nIBBB = COCF(nIBBBd,OE)
nINTA = CONF(nINTAd,OE)
nINTB = eONF(nINTBd,OB)
nINTAd
AND(nOBFA,nIBBA)
nINTBd
AND(nOBFB,nIBBB)
nOBFBd
NAND(nRA,nIBBA,nRST)
nOB FAd
NAND(nRB,nIBBB,nRST)
NAND(nWAd,nOBFA)
nIBEBd
nIBBAd
NAND(nWBd,nOBFB)
=
ENDS
292016-9
2-185
AB-12
5C031 ARBITER LEF
JUBRG
INTEL
March
80C31
STAHL
ZUERICH
2B, 1986
MAILBOX MEMORY USING 5C060 / 5C031
************"**'***
"
BXAMPLE .LBF "
"""'**"**'*"'*'
2
5C031
LB Version 3.0, Baseline 17x, 9/26/85
LBF Yersion 1.0 Baseline 1.5i 02 Feb 1987
PART:
5C031
INPUTS:
RST, nWRA, nRDB, CSA, nRDA, nWRB, CSB, nOB
OUTPUTS:
WA, nOBFA, nIBBB, nINTA, nINTB, nOBFB, nIBEA, WB
NITWORK:
RST = INP(RST)
nWRA = INP(nWRA)
nRDB = INP(nRDB)
CSA = INP(CSA)
nRDA = INP(nRDA)
nWRB = INP(nWRB)
CSB = INP(eSB)
nOE = INP(nOI)
WA = CONF(WAd, VCC)
nOBFA, nOBFA = COeF(nOBFAd, 01)
nIBBB, nIBIB = eOCF(nIBBBd, OB)
nINTA = CONF(nINTAd, OB)
nINTB = CONF(nINTBd, 01)
nOBFB, nOBFB = COCF(nOBFBd, 01)
nIBBA, nIBBA = COCF(nIBEAd, OB)
WB = CONF(WBd, YCC)
EQUATIONS:
WBd = CSB * DWRB';
nlBEAd
CSB
* nWHB'
+ nOBFB ';
nOBFDd
+
nOBFB
nINTBd
nlNTAd
nIBKBd
(nIBIA
nIDBA
* RST' * CSA'
* RST' * nRDA)';
* nIBBB;
nOBFA ,_ nIBEA;
CSA' nWRA'
+ nOBFA';
OK = ~OB';
nOBFAd
WAd
= (nIBBB
+
= eSA
nIBBB
* RST' *, CSB'
nRDB)';
* RST'
, nWRA';
IINDS
292016-10
2-186
inter
AB·12
5C031 ARBITER LEF (Continued)
Logic Optimizing Compiler Ut'ilization Report
FIT Version 1.0 Baseline 1.0i 2/6/87
****.
JUERG
INTEL
Mareh
80C31
Design i.plemented successfully
STAHL
ZUERICH
28, 1986
MAILBOX MEMORY USING 5C060 / 5C031
*************************
** EXAMPLE .RPT FILE **
*************************
Z
5C031
LB Version
Baseline 17x, 9/26/85
3.0~
5C031
GND GND
nOI!
CSB
nWRB
nRDA
CSA
nRDB
nWRA
GND -:
-
-
1
2
3
4
5
6
7
B
9
10
20:19:18:17:16:15:14: 13:12: -
Vee
WB
WA
nOBFB
nINTB
nINTA
nIBBS
nOBFA
nIBEA
11: - RST
nINPUTsn
Naae
Pin
Reeource
nOB
3
INP
Meell •
PTeras
MCells
Feeds:
OJ!
Clear Preset
3
4
5
6
7
B
CSB
4
INP
nWRB
5
INP
I
7
B
1
B
nRDA
6
INP
3
CSA
7
INP
2
3
DRDB
8
INP
nWRA
9
INP
6
7
2
6
GND
10
GND
RST
11
INP
3
7
Vee
20
Vee
1
2
292016-11
2-187
infef
AB·12
5C031 ARBITER UTILIZATION REPORT
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292016-12
2-188
inter
APPLICATION
NOTE
AP-252
September 1987
Designing With The 80C51BH
TOM WILLIAMSON
MCO APPLICATIONS ENGINEER
Order Number: 270068·002
2·189
AP·252
CMOS EVOLVES
The original CMOS logic families were the 4000-series
and the 74C-series circuits. The 74C-series circuits are
functional equivalents to the corresponding numbered
74-series TTL circuits, but have CMOS logic levels and
retain the other well known characteristics of CMOS
logic.
These characteristics are: low power consumption, high
noise immunity, and slow speed. The low power consumption is inherent to the nature of the CMOS circuit.
The noise immunity is due partly to the CMOS logic
levels, and partly to the slowness of the circuits. The
slow speed is due to the technology used to construct
the transistors in the circuit.
The technology used is called metal-gate CMOS, because the transistor gates are formed by metal deposition. More importantly, the gates are formed after the
drain and source regions have been defined, and must
overlap the source and drain somewhat to allow for
alignment tolerances. This overlap plus' the relatively
large size of the transistors themselves result in high
electrode capacitance, and that is what limits the speed
of the circuit.
High speed CMOS became feasible with the development of the self-liligning silicon gate technology. In this
process polysilicon gates are deposited before the
source and drain regions are defined. Then the source
and drain regions are formed by ion implantation using
the gate itself as a mask for the implantation. This eliminates most of the overlap capacitance. In addition, the'
process allows smaller transistors. The result is a significant increase in circuit speed. The 74HC-series of
CMOS logic circuits is based on this technology, and
has speeds comparable to LS TTL, which is to say
about 10 times faster than the 74C-series circuits.
The size reduction that contributes to the higher speed
also demands an accompanying reduction in the maximum supply voltage. High-speed CMOS is generally
limited to 6V.
WHAT IS CHMOS?
CHMOS is the name given to Intel's high-speed CMOS
processes. There are two CHMOS processes, one based
on an n-well structure and one based on a powell structure. In the .n-well structure, n-type wells are diffused
into a p-type substrate. Then the n-channel transistors.
(nFETs) are built into the substrate and pFETs are
built into the n-wells. In the p-well structure, p-type
wells are diffused into an n-type substrate. Then the
nFETs are built into the wells and pFETs, into the
substrate. Both processes have their advantages and
disadvantages, which are largely transparent to the
user.
Lower operating voltages are easier to obtain with the
powell structure than with the n-well structure. But the
powell structure does not easily adapt to an EPROM
which would be pin-for-pin compatible with HMOS
EPROMs. On the other hand the n-well structure can
be based on ,the solidly founded HMOS process, in
Wllich nFETs are built into a p-type substrate. This
allows somewhat more than half of the transistors in a
CHMOS chip to be constructed by processes that are
already well characterized.
Currently Intel's CHMOS microcontrollers and memory products are n-well devices, whereas CHMOS microprocessors are powell devices.
Further discussion of the CHMOS technology is provided in References I and 2 (which are reprinted in the
Microcontroller Handbook).
THE MCS®·51 FAMILY IN CHMOS
The 80C51BH is the CHMOS version of Intel's original
8051. The 80C31BH is the ROMless 80C51 BH, equivalent to the 8031. These CHMOS devices are architecturally identical with their HMOS counterparts, except
that they have two added features for reduced power.
These are the Idle and Power Down modes of operation.
In most cases, an 80C51BH can directly replace the
8051 in existing applications. It can execute the same
code at the same speed, accept signals from the same
sources, and drive the same loads. However, the
80C51BH covers a wider range of speeds, will emit
CMOS logic levels to CMOS loads, and will draw about
1/10 the current of an 8051 (and less yet in the reduced
power modes). Interchangeability between the HMOS
and CHMOS devices is discussed in more detail in the
final section of this Application Note.
It should be noted that the 80C51BH CPU is not static.
That means if the clock frequency is too low, the CPU
might forget what it was doing. This is because the
circuitry uses a number of dynamic nodes. A dynamic
node is one that uses the note-to-ground capacitance to
form a temporary storage cell. Dynamic nodes are used
to reduce the transistor count, and hence the chip area,'
thus to produce a more economical device.
This is not to say that the on-chip RAM in CHMOS
microcontrollers is dynamic. It's not. It's the CPU that
is dynamic, and that is what imposes th, minimum
clock frequency specification.
2-190
intJ
AP-252
LATCHUP
Latchup is an SCR-type turn-on phenomenon that is
the traditional nemesis of CMOS systems. The substrate, the wells, and the transistors form parasitic pnpn
structures within the device. These parasitic structures
turn on like an SCR if a sufficient amount of forward
current is <;Iriven through one of the junctions. From
the circuit designer's point of view it can happen whenever an input or output pin is externally driven a diode
drop above Vee or below Vss, by a source that is capable of supplying the required trigger current.
However much of a problem latchup has been in the
past, it is good to know that in most recently developed
CMOS devices, and specifically in CHMOS devices, the
current required to trigger latchup is typically well over
100 rnA. The 80C5IBH is virtually immune to latchup.
(References 1 and 2 present a discussion of the latchup
mechanisms and the steps that are taken on the chip to
guard against it.) Modern CMOS is not absolutely immune to latchup, but with trigger currents in the hundreds of rnA, latch up is certainly a lot easier to avoid
than it once was.
A careless power-up sequence might trigger a latchup
in the older CMOS families, but it's unlikely to be' a
major problem in high-speed CMOS or in CHMOS.
There is still some risk incurred in inserting or removing chips or boards in a CMOS system while the power
is on. Also, severe transients, such as inductive kicks or
momentary short-circuits, can exceed the trigger current for latchup.
For applications in which some latchup risk seems unavoidable, you can put a small resistor (lOOn or so) in
series with signal lines to ensure that the trigger current
will never be reached. This also helps to control overshoot and RFI.
LOGIC LEVELS AND INTERFACING
PROBLEMS
CMOS logic levels differ froin TTL levels in two ways.
First, for equal supply voltages, CMOS gives (and requires) a higher "logic I" level than TTL. Secondly,
CMOS logic levels are Vee (or VDD) dependent,
whereas guaranteed TTL logic levels are fixed when
Vee is within TTL specs.
Standard 74HC logic levels are as follows:
VIHMIN = 70% of Vee
VILMAX = 20% of Vee
VOHMIN = Vee - O.lV, IIOHI :s; 20/LA
VOLMAX = O.lV, Ilod :s; 20 /LA
Figure I compares 74HC, LS TTL, and 74HCT logic
levels with those of the HMOS 8051 and the CHMOS
80C5IBH for Vee = 5V.
Output logic levels depend of course on load current,
and are normally specified at several load currents.
When CMOS and TTL are powered by the same Veo
the logic levels guaranteed on the data sheets indicate
that CMOS can drive TTL, but TTL can't drive
CMOS. The incompatibility is that the TTL circuit's
VOH level is too low to reliably be recognized by the
CMOS circuit as a valid VIH.
Since HMOS circuits were designed to be TTL-compatible, they have the same incompatibility.
Fortunately, 74HCT-series circuits are available to ease
these interfacing problems. They have TTL-compatible
logic levels at the inputs and standard CMOS levels at
the outputs.
The 80C5IBH is designed to work with either TTL or
CMOS. Therefore its logic levels are specified very
much like 74HCT circuits. That is, its input logic levels
are TTL-compatible, and its output characteristics are
like standard high-speed CMOS.
NOISE CONSIDERATIONS
One of the major reasons for going to CMOS has traditionally been that CMOS is less susceptible to noise. As
previously noted, its low susceptibility to noise is
Vee
Logic State
=
5V
74HC
74HCT
LSTTL
VIH
VIL
3.5V
1.0V
2.0V
O.8V
2.0V
O.8V
2.0V
0.8V
1.9V
0.9V
VOH
VOL
4.9V
O.1V
4.9V
O.1V
2.7V
O.5V
2.4V
O.45V
4.5V
0.45V
8051
80C51BH
Figure 1. Logic Level Comparison. (Output voltage levels depend on load current.
Data sheets list guaranteed output levels for several load currents. The output
levels listed 'here are for minimum loading.)
2-191
inter
AP·252
partly due to superior noise margins, and partly due to
its slow speed.
,
Noise margin is the difference between VOL and VIL,
or between VOH and VIH. IfVOH from a driving circuit is 2.7V and VIH to the driven circuit is 2.0V, then
the driven circuit has 0.7V of noise margin at the logic
high level. These kinds· of comparisons show that an
all-CMOS system has wider noise margins than an allTTL system.
Figure 2 shows noise margins in CMOS and LS TTL
systems when both have Vee = 5V. It can be seen that
CMOS/CMOS and CMOS/CHMOS systems have an
edge over LS TTL in this respect.
Noise margins can be misleading, however, because
they don't say how much noise energy it takes to induce
in the circuit a noise voltage of sufficient amplitude to
cause a logic error. This would involve consideration of
the width of the noise pulse as compared with the circuit's response speed, and the impedance to ground
from the point of noise introduction in the circuit.
When these considerations are included, it is seen that
using the slower 74C- and 4OOO-series circuits with a 12
or 15V supply voltage does offer a truly improved level
of noise immunity, but that high-speed CMOS at 5V is
not significantly Better than TTL.
current in extremely sharp spikes at the clock edges.
The VHF and UHF components of these spikes are not
drawn from the power supply, but from the decoupling
capacitor. If the decoupling circuit is not sufficiently
low in inductance, Vee will glitch at each clock edge.
We suggest that a 0.1 p.F decoupler cap be used in a
minimum-inductance configuration with the microcontroller. A minimum-inductance configuration is one
that minimizes the area of the loop formed by the chip
(Vee to Vss), the traces to the decoupler cap, and the
decoupler cap. PCB designers too often fail to understand that if the traces that connect the decoupler cap
to the Vee and Vss pins aren't short and direct, the
decoupler loses much of its effectiveness.
Overshoot and ringing in signal lines are potential
sources of logic upsets. These can largely be controlled
by circuit layout. Inserting small resistors (about lOOn.)
in series with signal lines that seem to need them will .
also help.
The sharp edges produced by high-speed CMOS can
cause RFI problems. The severity of these problems is
largely a function of the PCB layout. We don't mean to
imply that all RFI problems can be solved by a better
PCB layout. It may well be, for example, that in some
RFI-sensitive designs high-speed CMOS is simply not
the answer. But circuit layout is a critical factor in the
noise performance of any electronic system, and more
so in high-speed CMOS systems than others.
One should not mistake the wider supply voltage tolerance of high-speed CMOS for Vee glitch immunity.
Supply voltage tolerance is a DC rating, not a glitch
rating.
Circuit layout techniques for minimizing noise susceptibility and generation are discussed in References 3
throllgh 6.
For any clocked CMOS, and most especially for VLSI
CMOS, Vee decoupling is critical. CHMOS draws
UNUSED PINS
Interface
Noise Margin for
Vee = 5V
Logic Low
VIL-VOL
Logic High
VOH-VIH
74HCto 74HC
0.9V
1.4V
LSTTL to LSTTL
0.3V
0.7V
LSTTL to 74HCT
0.3V
0.7V
LSTTL to 80C51 BH
0.3V
0.7V
74HCt080C51BH
O.SV
3.0V
SOC51BH to 74HC
O.SV
1.0V
Figure 2. Noise Margins for CMOS
and LS TTL Circuits
CMOS input pins should not be left to float, but should
always be pulled to one logic level or the other. If they
float, they tend to float into the transition region between 0 and I, where the pullup and pulldown devices
in the input buffer are both conductive. This causes a
significant increase in ICC. A similar effect exists in
HMOS circuits, but with less noticeable results.
In 80C51BH and 80C31BH designs, unused pins of
Ports 1, 2, and 3 can be.ignored, because they have
internal pullups that will hold them at a valid Logic 1
level. Port 0 pins are different, however, in not having
internal pullups (except during bus operations).
When the 80C51BH is in reset, the Port 0 pins are in a
float state unless they are externally pulled up or down.
If it's going to be held in reset for just a short time, the
transient float state can probably be ignored. When it
comes out of reset, the pins stay afloat unless
2-192
AP-252
they are externally pulled either up or down. Alternatively, the software can internally write Os to whatever
Port 0 pins may be unused.
The same considerations are applicable to the
80C3IBH with regards to reset. But when the
80C3lBH comes out of reset, it commences bus operations, during which the logic levels at the pins are always well defined as high or low.
Consider the 80C3IBH in the Power Down or Idle
modes, however. In those modes it is not fetching instructions, and the Port 0 pins will float if not externally pulled high or low. 1'he choice of whether to pull
them high or low is the designer's. Normally it is sufficient to pull them up to Vee with 10k resistors. But if
power is going to be removed from circuits that are
connected to the bus, it will be advisable to pull the bus
pins down (normally with 10k resistors). Considerations involved in selecting pullup and pulldown resistor
values are as follows.
vee
PULLUP RESISTORS
If a pullup resistor is to be used on a Port 0 pin, its
minimum value is determined by IOL requirements. If
the pin is trying to emit a 0, then it will have to sink the
current from the pullup resistor plus whatever other
current may be sourced by other loads connected to the
pin, as shown in Figure 3a, while maintaining a valid
output low (VOL)' To guarantee that the pin voltage
will not exceed 0.45V, the resistor should be selected so
that IOL doesn't exceed the value specified on the data
sheet. In most CMOS applications, the minimum value
would be about 2k n.
The maximum value you could use depends on how
fast you want the pin to pull up after bus operations
have ceased, and how high you want the VOH level to
be. The smaller the resistor the faster it pulls up. Its
effect on the VOH level is that VOH = Vee - (ILl +
IIH) X R. ILl is the input leakage current to the Port 0
pin, and IIH is the input high current to the external
loads, as shown' in Figure 3b. Normally VOH can be
expected to reach 0.9 Vee if the pullup resistance does
not exceed about 50k n.
80e51BH
R
..JQh.
....!!!:...
po.x 1-------E~1Ef~ll
vee
IOl=R+ lIl
270068-1
Figure 3a. Conditions defining the minimum
value for R. PO.X is emitting a logic low. R must
be large enough to not cause IOL to exceed
data sheet specifications.
Pulldown Resistors
If a pulldown resistor is to be used on a Port 0 pin, ,its
minimum value is determined by VOH requirements
during bus operations, and its maximum value is in
most cases determined by leakage current.
During bus operations the port uses internal pullups to
emit Is. The D.C. Characteristics in the data sheet list
guaranteed VOH levels for given IOH currents. (The "-"
sign in the IOH value means the pin is sourcing that
current to the external load, as shown in Figure 4,) To
ensure the VOH level listed in the data sheet, the resis-
Yep:
80C51BH
80C51BH
R
..J!!!..
~
pO.x: ....
...!!!i.
.J!d...
----;r_---
po.x r----<----ExL.-g:lI~rL
E~-g::C:L
R
YOH =
yce
-(IL.l + IIH)
~
xR
IOH
270068-2
= YOH + IIH
R
270068-3
Figure 3b. Conditions defining the maxilTlum
value for R. PO.X is in a high impedance
state. R must be small enough to keep
VOH acceptably high.
Figure 4a. Conditions defining the minimum
value for R. PO.X is emitting a 1 in a bus
operation. R must be large enough to not cause
IOH to exceed data sheet specifications.
2-193
AP-252
VOH
I I
1'1+
IIHS:: IOH
DRIVE CAPABILITY OF THE
INTERNAL PULLUPS
tor has to satisfy where IIH is the input high current to
the external loads.
When the pin goes into a high impedance state, the
pulldown resistor will have to sink leakage current
from the pin, plus whatever other current may be
sourced by ,other loads connected to the pin, as shown
in Figure 4b. The Port 0 leakage, current is ILl on the
data sheet. The resistor should be selected so that the
voltage developed across it by these currents will be
seen as a logic low by whatever circuits are connected
to it (including the 80CSIBH). In CMOS/CHMOS applications, SOk n is normally a reasonable maximum
value.
aOCS1BH
~
Po.xt---_---- E~1J':JitL
R
VOL
=(Ill + IIL)xR
270068-4
Figure 4b. Conditions defining the maximum
value for R. PO.X is in a high impedance state.
R must be small enough to keep VOL
acceptably low.
There's an important difference between HMOS and
CHMOS port drivers. The pins of Ports 1,2, and 3 of
the CHMOS parts each have three pullups: strong, normal, and weak, as shown in Figure S. The strong pullup
(p I) is only used during O-to-l transitions, to hasten the
transition. The weak pullup' (p2) is on whenever the bit
latch contains a 1. The "normal" pullup (p3) is controlled by the pin voltage itself.
The reason that p3 is controlled by the pin voltage is
that if the pin is being used as an input, and the external
source pulls it to a low, then turning offp3 makes for a
lower IlL. The data sheet shows an "ITL" specification.
This is the current that p3 will source during the time
the pin voltage is making its I-to-O transition. This is
what IlL would be if an input low at the pin didn't tum,
p3 off.
Note, however, that this p3 tum-off mechanism puts a
restriction on the drive capacity of the pin if it's being
used as an output. If you're trying to output a logic
high, and the external load pulls the pin voltage below
the pin's YIHMIN spec, p3 might tum off, leaving only
the weak p2 to provide drive to the load. To prevent
this happening, you need to ensure that the load doesn't
draw more than the IOH spec for a valid YOH. The idea
is to make sure the pin voltage never falls below its own
YIHMIN specification.
VCC
VCC
VCC
Q
FROM PORT
LATCH
READ
PORT PIN
270068-5
Figure 5. 80C51BH Output Drivers for Ports 1, 2 and 3
2-194
AP-252
POWER CONSUMPTION
The main reason for going to CMOS, of course, is to
conserve power. (There are other reasons, but this is the
main one.) Conserving power doesn't mean just reducing your electric bill. Nor does it necessarily relate to
battery operation, although battery operation without
CMOS is pretty unhandy. The main reason for conserving power is to be able to put more functionality into a
smaller space. The reduced power consumption allows
the use of smaller and lighter power supplies, and less
heat being generated allows denser packaging of circuit
components. Expensive fans and blowers can usually be
eliminated.
A cooler running chip is also more reliable, since most
random and wearout failures relate to die temperature.
And finally, the lower power dissipation will allow
more functions to be integrated onto the chip.
The reason CMOS consumes less power than NMOS is
that when it's in a stable state there is no path of conduction from Vee to Vss except through various leakage paths. CMOS does draw current when it's changing
states. How much current it draws depends on how
often and how quickly it changes states.
\
~
SIINN:;USOIDAL
~
CLOCK SIGNAL
--Y
.
IY
-l.SMHz
RECTANGULAR CLOCK SIGNAL
CLOCK FREQ
270068-6
CMOS circuits draw current in sharp spikes during logical transitions. These current spikes are made up of
two components. One is the current that flows during
the transition time when pullup and pulldown FETs are
both active. The average (DC) value of this component
is larger when the transition times of the input signals
are longer. For this reason, if the current draw is a
critical factor in the design, slow rise and fall times
should be avoided, even when the system speed doesn't
seem to justify a need for nanosecond switching speeds.
The other component is the current that charges stray
and load capacitance at the nodes of a CMOS logic
gate. The average value of this current spike is its area
(integral over time) multiplied by its rep rate. Its area is
the amount of charge it takes to raise the node capacitance, C, to Vee. That amount of charge is just C x
Vee. So the average value of the current spike is C x
Vee x f; where f is the clock frequency.
This component of current increases linearly with clock
frequency. For minimal current draw, the 80C52BH-2
is spec'd to run at frequencies as low as 500 kHz.
Keep in mind, though, that other component of current
that is due to slow rise and fall times. A sinusoid is not
the optimal waveform to drive the XTALI pin with.
Yet crystal oscillators, including the one on the
80C51BH, generate sinusoidal waveforms. Therefore, if
the on-chip oscillator is being used, you can expect the
device to draw more current at 500 kHz, than it does at
1.5 MHz, as shown in Figure 6. If you derive a good
sharp square wave from an external oscillator, and use
that to drive XTALl, then the microcontroUer will
draw less current. But the external oscillator will probably make up the difference.
The 80C5IBH has two power-saving features not available in the HMOS devices. These are the Idle and Power Down modes of operation. The on-chip hardware
that implements these reduced power modes is shown
in Figure 7. Both modes are invoked by software.
Figure 6. 80C51BH ICC vs. Clock Frequency
CPU
INTERRUPT
SERIAL PORT
TIMER/COUNTERS
270068-7
Figure 7. Oscillator and Clock Circuitry Showing Idle and Power Down Hardware
2-195
inter
AP-252
Idle: In the Idle Mode (IDL = 0 in Figure 7), the CPU
puts itself to sleep by gating off its own clock. It doesn't
stop the oscillator. It just stops the internal clock signal
from getting to the CPU. Since the CPU draws SO to 90
percent of the chip's power, shutting it off represents a
fairly significant power savings. The on-chip periperals
(timers, serial port, interrupts, etc.) and RAM continue
to function as normal. The CPU status is preserved in
its entirety: the Stack Pointer, Program Counter, Program Status Word, Accumulator, and all other registers maintain their data during Idle.
There are two ways to terminate Idle. Activation of any
enabled interrupt will cause the hardware to clear bit 0
of the PCON register, terminating the Idle mode. The
interrupt will be serviced, and following RET! the next
instruction to be executed will be the one following the
instruction that .invoked Idle.
The other way is with a hardware reset. Since the clock
oscillator is still running, RST only needs to be held
active for two machine cycles (24 oscillator periods) to
complete the reset. Note that this exit from Idle writes
Is to all the ports, initializes all SFRs to their reset
values, and restarts program execution from location O.
The Idle Mode is invoked by setting bit 0 (IDL) of the
PCON register. PCON is not bit-addressable, so the bit
has to be set by a byte operation, such as
Power Down: In the Power Down Mode (PD = 0 in
Figure 7), the CPU puts the whole chip to sleep by
turning off the oscillator. In case it was running from
an external oscillator, it also gates off the path to the
internal phase generators, so no internal clock is generated even if the external oscillator is still running. The
on-chip RAM, however, saves its data, as long as Vee
is maintained. In this mode the only Icc that flows is
leakage, which is normally in the micro-amp range.
ORL PCON.#l
The PCON register also contains flag bits GFO and
GFl, which can be used for any general purposes, or to
give an indication if an interrupt occurred during normal operation or during Idle. In this application, the
instruction that invokes Idle also sets one or both of the
flag bits. Their status can then be checked in the interrupt routines.
The Power Down Mode is invoked by setting bit 1 in
the PCON register, using a byte instruction such as
While the device is in the Idle Mode, ALE and PSEN
emit logic high (VOH), as shown in Figure S. This is so
external EPROM can be deselected and have its output
disabled.
ORL
While the device is in Power Down, ALE and PSEN
emit lows (VOL), as shown in Figure S. The reason they
are designed to emit lows is so that power can be removed from the rest of the circuit, if desired, while the
SOCS5IBH is in its Power Down mode.
The port pins hold the logical states they had at the
time the Idle was activated. If the device was executing
out of external program memory, Port 0 is left in a high
impedance state and Port 2 continues to emit the high
byte of the program counter (using the strong pullups
to emit Is). If the device was executing out of internal
program memory, Ports 0 and 2 continue to emit whatever is in the PO and P2 registers.
PSENI
The port pins continue to emit whatever data was written to them. Note that Port 2 emits its P2 register data
even if execution was from external program memory.
External Execution
Internal Execution
Pin
ALE
PCON.#2
Idle
Power Down
Idle
Power Down
1
0
1
0
1
0
1
0
PO
SFR Data
SFR Data
High-Z
High-Z
P1
SFR Data
SFR Data
SFR Data
SFR Data
P2
SFR Data
SFR Data
PCH
SFR Data
P3
SFR Data
SFR Data
SFR Data
SFR Data
Figure 8. Status of Pins iO Idle and Power Down Modes. "SFR data" means the port pins emit their
internal register data. "PCH" Is the high byte of the Program Counter.
2-196
AP-252
Port 0 also emits its PO register data, but if execution
was from external program memory, the PO register
data is FF. The oscillator is stopped, and the part remains in this state as long as Vee is held, and until it
receives an external reset signal.
The only exit from Power Down is a hardware reset.
Since the oscillator was stopped, RST must be held active long enough for the oscillator to re-start and stabilize. Then the reset function initializes all the Special
Func'tion Registers (ports, timers, etc.) to their reset
values, and re-starts the program from location O.
Therefore, timer reloads, interrupt enables, baud rates,
port status, etc. need to be re-established. Reset does
not affect the content of the on-chip data RAM. If Vee
was held during Power Down, the RAM data is still
good.
USING THE POWER DOWN MODE
The software-invoked Power Down feature offers a
means of reducing the power consumption to a mere
trickle in systems which are to remain dormant for
some period of time, while retaining important data.
The user should give some thought to what state the
port pins should be left in during the time the clock is
stopped, and write those values to the port latches before invoking Power Down.
If Vee is going to be held to the entire circuit, one
would want to write values to the port latches that
would deselect peripherals before invoking Power
Down. For example, if external memory is being used,
the P2 SFR should be loaded with a value which will
not generate an active chip select to any memory device.
In some applications, Vee to part of the system may be
shut off during Power Down, so that even quiescent
and standby currents are eliminated. Signal lines that
connect to those chips must be brought to a logic low,
whether the chip in question is CMOS, NMOS, or
TTL, before Vee is shut off to them. CMOS pins have
parasitic pn junctions to Vee, which will be forward
biased if Vee is reduced to zero whfle the pin is held at
a logic high. NMOS pins often have FETs that look
like diodes to Vee. TTL circuits may actually be damaged by an input high if Vee = O. That's why the
80C51BH outputs lows at ALE and PSEN during Power Down.
Figure 9 shows a circuit that can be used to turn Vee
off to part of the system during Power Down. The circuit will ensure that the secondary circuit is not de-energized until after the 80C31BH is in Power Down, and
that the 80C3lBH does not receive a reset (terminating
the Power Down mode) before the secondary circuit is
re-energized. Therefore, the program memory itself can
be part of the secondary circuit.
VCCI
CI
1,..1
R
VCC2
1,..1
20K
270068-8
Figure 9. The 80C318H de-energizes part of the circuit (VCC2) when it goes into Power Down.
Selections of Rand Q2 depend on VCC2 current draw.
2-197
AP-252
In Figure 9, when Vee is switched on to the 80C3lBH,
'capacitor CI provides a power-on reset. The reset function writes Is to all the port pins. The 1 at P2.6 turns
Qlon, enabling Vee to the secondary circuit through
transistor Q2. As the 80C31 BH comes out of reset, Port
2 commences emitting the high byte of the Program
Counter, which results in the P2.7 and P2.6 pins outputting Os. The 0 at P2.7 ensures continuation of Vee
to the secondary circuit.
The system software must now write·a I to P2.7 and a 0
to P2.6 in the Port 2 SFR, P2. These values will not
appear at the Port 2 pins as long as the device is retching instructions from external program memory. However, whenever the 80C31BH goes into Power Down,
these values will appear at the port pins, and will shut
off both' transistors, disabling Vee to the secondary circuit.
Closing the switch Sire-energizes the secondary circuit, and at the same time sends a reset through C2 to
the 80C3lBH to wake it up. The diode DI is to prevent
CI from hogging current from C2 during this'secondary reset. D2 prevents C2 from discharging through the
RST pin when Vee to the secondary .circuit goes to
zero.
~,
J'
::::--'VIh--"'-"""-~1_
270068-9
a. Using a pFET
+12V
USING POWER MOSFETs to
CONTROL Vee
Power MOSFETs are gaining in popularity (and availability), The easiest way to control Vee is with a Logic
Level pFET, as shown in .Figure lOa. This circuit allows the full Vee to be used to turn the device on.
Unfortunately, power pFETs are not economically
competitive with bipolar transistors of comparable ratings.
Power nFETs are both economical and available, and
can be used in this application if a DC supply of higher
voltage is available to drive the gate. Figure lOb shows
how to implement a Vee switch using a power nFET
and a (nominally) + 12V supply. The problem here is
that if the device is on, its source voltage is + SV. To
maintain the on state, the gate has to be another 5 or
lOY above that. The "12V" supply is not particularly
critical. A miniinally filtered, unregulated rectifier will
suffice,
BATTERY BACKUP SYSTEMS'
Here we consider drcuits that normally draw po}Ver
from the AC line, but switch to battery operation in the
event 'of a power failure. We assume that in battery
operation high-current loads will be allowed to die
along with the AC power. The system may continue
then with reduced functionality, monitoring a control
transducer, perhaps, or driving an LCD. Or it may go
into a bare-bones survival mode, in which critical data
is saved but nothing else happens till AC power is restored.
In any case it is necessary to have some early warning
of an impending power failure so that the system can
arrange an orderly transfer to battery power. Early
warning systems can operate by monitoring either the
AC line voltage or the unregulated rectifier output, or
even by monitoring the regulated DC voltage.
.
Monitoring the AC line voltage gives the earliest warning. That way you can know within one or two half-cycles of line frequency that AC power is down. In most
cases you then have at least another half-cycle of line
frequency before the regulated Vee starts to fall. In a
half-cycle of line frequency an 80CSIBH can execute
about 5,000 instructions-plenty of time to arrange an
orderly transfer of power.
12K
2N3904
P2.7'-'lM,--...,..-_---1
P2.6
270068-28
b. Using an nFET
Figure 10. Using Power MOSFETs
to Control VCC2
The circuit in Figure II uses a Zener diode to test the
line voltage each half-cycle, and a junction transistor to
pass the information on to the 80CS lBH. (Obviously a
voltage comparator with a suitable reference source can
2-198
AP-252
~II~
VCC2
=
BACKUP
:::=:BATTERY
VCC
80C51BH
80C31BH
<-i
I-~----t INTO
.011'1
VSS
270068-10
Figure 11. Power Failure Detector with Battery Backup. When AC power falls,
VCC1 goes down and VCC2 is held.
perform the same function, if one prefers.) The way it
works is if the line voltage reaches an acceptably high
level, it breaks over Zl, drives Ql to saturation, and
interrupts the 80C5IBH. The interrupt would be transition-activated, in this application. The interrupt service routine reloads one of the C5IBH's timers to a value
that will make it roll over in something between one
and two half-cycles of line frequency. As long as the
line voltage is healthy, the timer never rolls over, because it, is reloaded every half-cycle. If there is a single
half-cycle in which the line voltage doesn't reach a high
enough level to generate the interrupt, the timer rolls
over and generates a timer interrupt.
The timer interrupt then commences the transition to
battery backup. Critical data needs to be copied into
protected RAM. Signals to circuits that are going to
lose power must be written to logic low. Protected circuits (those powered by Vee2) that communicate with
unprotected circuits must be deselected. The microcontroller itself may be put into Idle, so that it can continue some level of interrupt-driven functionality, or it
may be put into Power Down.
Note that if the CPU is going to invoke Power Down,
the Special Function Registers may also need to be copied into protected RAM, since the reset that terminates
the Power Down mode will also intialize all the SFRs
to their reset values.
The circuit in Figure II does not show a wake-up
mechanism. A number of choices are available, however. A pushbutton could be used to generate an interrupt, if the CPU is in Idle, or to activate reset, if the
CPU is in Power Down.
Automatic wake-up on power restoration is also possible. If the CPU is in Idle, it can continue to respond to
any interrupts that might be generated by QI. The interrupt service routine determines from the status of
flag bits GFO and GFI in PCON that it is in Idle because there was a power outage. It can then sample
Veel through a voltage comparator similar to ZI, Ql
in Figure 11. A satisfactory level of Veel would be
indicated by the transistor being in saturation.
But perhaps you can't spare the timer that is the key to
the operation of the circuit in Figure 11. In that case a
retriggerable one-shot, triggered by the AC line voltage,
can perform essentially the same function. Figure 12
shows an example of this type of power failure detector.
A retriggerable one-shot (one halfofa 74HC123) monitors the AC line voltage through transistor Q 1. Q I retriggers the one-shot every half-cycle of line frequency.
If the output pulse width is between one and two halfcycles of line frequency, then a single missing or low
half-cycle will generate an active low warning flag,
which can be used to interrupt the microcontroller.
The interrupt routine takes care of the transition to
battery backup. From this point Veel mayor may not
actually drop out. The missing half-cycle of line voltage
that caused the power down sequence may have been
nothing more than a short glitch. If the .i\C line comes
back strong enough to trigger the one-shot while Vee I
is still up (as indicated by the state of transistor Q2),
then the other half of the 74HCI23 will generate a
wake-up signal.
2-199
intJ
.AP-252
VCC2
VCC1
BACKUP
BATTERY
1/1/1/1
20K
12K
12K
1,.1
47K
VCC2
. A
1f.!74HC123
VCC
Q
RIC
CLR
C
Q
WAKE-iiP
Q
WAKE-UP
B
A
V99
1f.!74HCl23
iNTo
(BOC51BH)
270068-11
Figure 12. Power Failure Detector uses retriggerable one-shots to flag Impending power outage and
generate automatic wake-up when power returns.
.
Having been awakened, the 80C5IBH will stay awake
for at least another half-cycle of line frequency (another
5,000 or so instructions) before possibly being told to
arrange another transfer of power. Consequently, if the
line voltage is. jittering erratically around the switchover point (determined by diode Zl), the system will
limp along ex.ecuting in half-cycle ,units of line frequency.
POWER SWITCHOVER CIRCUITS
Battery backup systems need to have a way for the
protected circuits to draw power from the line-operated
power supply when that source is available; and to
switch over to battery power when required. The
switchover circuit is simple if the entire system is to be
battery powered in the event of a line power outage. In
that case a pair of diodes suffice, as shown in Figure 12,
provided VccMIN specs are still met after the diode
drop has been subtracted from its respective power
source.
On the other hand, if the power outage is real and
lengthy, Veel will eventually fall below the level at
which the backup battery takes over. The backup battery maintains power to the 8OC5IBH, and to the
74HC123, and to whatever other circuits are being protected during this outage. The battery voltage must be
high enough to maintain VcCMIN specs to the
80C5IBH.
The situation becomes more complicated when part of
the circuit is going to be allowed to die when the AC
power goes out. In that case it is difficult to maintain
equal Vccs to protected and unprotected circuits (and
possibly dangerous not to).
If the microcontroller is an 80C3l BH, executing out of
external ROM, and if the C3IBH is put into Idle during the power outage, then the external ROM must also
be supplied by the battery. On the other hand, if the
C31BH is put into Power Down during the outage,
then the ROM can be allowed to die with the AC power. The considerations here are the same as in Figure 9:
Vee to the ROM is still up at the time Power Down is
invoked, and we must ensure (through selection of diode Z2 in Figure 12) that the 80C3IBH is not awakened till ROM power is back in spec.
The problem can be alleviated by using a Schottky diode instead of a lN400l, for its lower forward voltage
drop. The lN5820, for example, has a foward drop of
about O.35V at lAo
Other solutions are to use a transistor or power MOSFET switch, as shown in Figure 13. With minor modifications this switch can be controlled by port pins.
2-200
inter
AP-252
VCC2
vcel
I1
270068-27
a. Using a pnp Transistor
VCC2
-TILril
~
II
270068-12
b. Using a Power MOSFET
Figure 13. Power Switchover Ckts.
80C31BH
+
CHMOS EPROM
The 27C64 and 87C64 are Intel's 8K byte CHMOS
EPROMs. The 27C64 requires an external address
latch, and can be used with the 80C3IBH as shown in
Figure 14a. In most 8031 + 2764 (HMOS) appli-
cations, the 2764's Chip Enable (CE) pin is hardwired
to ground (since it's normally the only program memory on the bus). This can be done with the CHMOS
versions as well, but there is some advantage in connecting CE to ALE, as shown in Figure 14a. The advantage is that if the 80C3IBH is put into Idle mode,
since ALE goes to a 1 in that 'mode, the 27C64 will be
deselected and go into a low current standby mode.
The timing waveforms for this configuration are shown
in Figure 14b. In Figure 14b the signals and timing
parameters in parenthesis are those of the 27C64, and
the others are of the 80C31BH, except Tprop is a parameter of the address latch. The requirements for timing compatibility are
TAVIV - Tprop > tACC
TLlIV> tCE
TPLlV> tOE
TPXIZ> tDF
If the application is going to use the Power Down mode
then we have another consideration: In Idle, ALE =
PSEN = I, and in Pow~r Down, ALE = PSEN = O.
In a realistic application there are likely to be more
chips in the circuit than are shown in Figure 14, and it
is likely that the nonessential ones will have their Vee
removed while the CPU is in Power Down. In that case
the EPROM and the address latch should be among
the chips that have Vee removed, and logic lows are
exactly what are required at ALE and PSEN.
But if Vee is going to be maintained to the EPROM
during Power Down, then it will be necessary to de-
PSENr---------------------~Oi
270068-26
Figure 14a. 80C31BH
2-201
+
27C64
intJ
AP-252
The 87C64 is like the 27C64 except that it has an onchip address latch. The Port 0 pins are tied to both
address and data pins of the 87C64, as shown in Figure
16a. ALE drives the EPROM's ALE/CS input. During
ALE high, the address information is allowed to flow
into the EPROM and begin accessing the code byte. On
the falling edge of ALE the address byte is internally
latched. The AO-A7 inputs are then ignored and the
same bus lines are used to transmit the fetched code
.byte from the 00-07 pins back to the 80C31 BH.
The timing waveforms for this configuration are shown
in Figure 16b. In Figure 16b the signals and timing
parameters in parentheses are those of the 87C64, and
the others are of the 80C31BH. The requirements for
timing compatibility are
270068-13
Figure 14b. Timing Waveforms for aoC31BH
. 27C64
TLHLL> tLL
+
TAVLL> tAL
TLLAX> tLA
select the EPROM when the CPU is in Power Down. If
Idle is never invoked, CE of the EPROM can be connected to P2.7 of the 80C31BH, as shown in Figure
15a. In normal operation, P2.7 will be emitting the
MSB of the Program Counter, which is 0 if the program contains less than 32K of code. '!)ten when the
CPU goes into Power Down, the Port 2 pins emit P2
SFR data, which puts a 1 at P2.7, thus deselecting the
.
EPROM.
If Idle and Power Down are both going to be used, CE
of the EPROM can be driven by the logical OR of ALE
and P2.7, as shown in Figure 15b. In Idle, ALE = 1
will deselect the EPROM, and in Power Down, P2.7 =
1 will deselect it.
TLLlV> tACL
TPLlV> tOE
TLLPL> tCOE
TPXIZ> tOHZ
The same considerations apply to the 87C64 as to the
27(:64 with regards to the Idle and Power Down
modes. Basically you want CS = 1 if Vee is maintained to the EPROM, and CS = OE = 0 if Vee is
.
removed.
SCANNING A KEYBOARD
CE
P2.7
OOCmBH-----------~~27~64
270068-14
a. Power Down is used but not Idle.
01
80C31BH
{ALE~.
_
CE
P2.7~ 27':164
270068-15
b. Idle and Power Down both used.
Figure 15. Modifications to 80C31BH/27C64
Interface
Pulldown resistors are shown in Figure 14a under the
assumption that something on the bus is going to have
its Vee removed during Power Down. If this is not the
case~ pullups can be used as well as pulldowns.
There are many different kinds of keyboards, but alphanumeric keyboards generally consist of a matrix of 8
scan lines and 8 receive lines as shown in Figure 17.
Each set of lines connects to one port of the microcontroller. The software has written Os to the scan lines,
and Is to the receive lines. Pressing a key connects a
scan line to a receive line, thus pulling the receive line
to a logic low.
The 8 receive lines are ANDed to one of the external
interrupt pins, so that pulling any of the receive lines
low generates an interrupt. The interrupt service routine has to identify the pressed key, if only one key is
down, and convert that information to some useful output. If more than one key in the line matrix is found to
be pressed, no action is taken. (This is a "two key lockout" scheme.)
2-202
inter
Ap·252
On some keyboards, certain keys (Shift, Control, Escape, etc.) are not a part of the line matrix. These keys
would connect directly to a port pin on the microcontroller, and would not cause lock-out if pressed simultaneously with a matrix key, nor generate an interrupt if
pressed singly.
Normally the microcontroller would be in idle mode
when a key has not been pressed, and another task is
not in progress. Pressing a matrix key generates an in-
r
10K
PO
terrupt, which terminates the Idle. The interrupt service routine would first call a 30 ms (or so) delay to
debounce the key, and then set about the task of identifying which key is down.
First, the current state of the receive lines is latched
into an internal register. If a single key is down, all but
one of the lines would be read as Is. Then Os are written
to the receive lines and Is to the scan lines, and the scan
lines are read. If a single key is down, all but one of
XS
/s
~
0,,-07
S7C64
SOC31BH
1s
P2
/5
-"
/ Ao- A7
)
A,.-A'2
ALE
CE
PSEN
OE
270068-16
Figure 16a. 80C31BH
+
87C64
270068-17
Figure 16b. Timing Waveforms for 80C31BH
2-203
+
87C64
inter
AP-252
RESPONSE_TO_KEY_CLOSURE:
CALL DEBOUNCE_DELAY
MOV
LINE, PI; ;See Figure 17.
CALL SCAN
DJNZ ZERO_COUNTER ,REJECT
MOV
ADDRESS ,ZERO_BIT
MOV
P2,#OFFH; ;See Figure 17.
MOV
P1,#0
MOV
LINE,P2
CALL SCAN
DJNZ ZERO_COUNTER ,REJECT
XCH
A,ZERO_BIT
SWAP A
ORL' ADDRESS ,A
XCH
A,ZERO_BIT
MOV
P1,#OFFH
MOV
P2,#O
REJECT: CLR
EXO
RETI
these lines would be read as Is. By locating the single 0
in each set of lines, the pressed key-can be identified. If
more than one matrix key is down, one or both sets of
lines will contain multiple Os.
A subroutine is used to determine which of 8 bits in
either set of lines is 0, and whether more than one bit is
O. Figure 18 shows a subroutine (SCAN) which does
that using the 8051 's bit-addressing capability. To use
the subroutine, move the line data into a bit-addressable RAM location named LINE, and call the SCAN
routin~. The number of LINE bits which are zero is
returned in ZERO_COUNTER. If only one bit is
zero, its number (1 through 8) is returned in ZERO_
BIT.
The interrupt service routine that is executed in response to a key closure might then be as follows:
SCAN UNES
._---A.----_,
-
rC
RECEIVE
UNES
'-'---
80C51BH
f---"
i------"
PI P2
INTO
270068-18
Figure 17. Scanning a Keyboard
2-204
AP-252
SCAN:
ONE:
TWO:
THREE:
FOUR:
FIVE:
SIX:
SEVEN:
EIGHT:
ZEROSOUNTER, .0
LINE. 0, ONE
ZERO_COUNTER
ZERO_BIT, .1
LINE.I,TWO
ZEROSOUNTER
ZERO_BIT,82
LINE.2,THREE
ZERO_COUNTER
ZERO_BIT,83
LINE. 3, FOUR
ZERO_COUNTER
ZERO_B IT, .4
LINE. 4, FIVE
ZEROSOUNTER
ZERO_B IT, .5
LINE.5,SIX
ZERO_COUNTER
ZERO_B IT, 86
LINE. 6, SEVEN
ZERO_COUNTER
ZERO_BIT,87
LINE. 7, EIGHT
ZERO_COUNTER
ZERO_BIT, fiB
MOV
.JB
INC
MOV
.JB
INC
MOV
.JB
INC
MOV
.JB
INC
MOV
.JB
INC
MOV
.JB
INC
MOV
JB
INC
MOV
JB
INC
MOV
RET
ZERO_COUNTER counts the number of Os in LINE.
Tost LINE bit O.
If LINE 0 = 0, inc~ement ZERO_COUNTER
and record that line number I is active.
Procedure continues for other LINE bits.
Line number 2 is active.
Line number :3 is active.
Line number 4 is active.
Line number 5
..
active.
Line number 6 is active
Line number 7 is active.
Line number B is active.
270068-19
Figure 18. Subroutine SCAN Determines Which of 8 Bits in LINE is Zero
Notice that RESPONSE_TO_KEY_CLOSURE
does not change the Accumulator, the PSW, nor any of
the registers RO through R7. Neither do SCAN or DEBOUNCE_DELAY.
What we corne out with then is a one-byte key address
(ADDRESS) which identifies the pressed key. The
key's scan line number is in the upper nibble of ADDRESS, and its receive line number is in the lower
nibble. ADDRESS can be used in a look-up table to
generate a key code to transmit to a host computer,
andlor to a display device.
The keyboard interrupt itself must be edge-triggered,
rather than level-activated, so that the interrupt routine
is invoked when a key is pressed, and is not constantly
being repeated as long as the key is held down. In edgetriggered mode, the on-chip hardware clears the interrupt flag (EXO, in this case) as the service routine is
being vectored to. In this application, however, contact
bounce will cause several more edges to occur after the
service routine has been vectored to, during the DEBOUNCE~ELA Y routine. Consequently it is necessary to clear EXO again in software before executing
RETI.
.
The debounce delay routine also takes advantage of the
Idle mode. In this routine a timer must be preloaded
with a value appropriate to the desired length of delay.
This would be
For example, with a 3.58 MHz oscillator frequency, a
30 ms delay could be obtained using a preload value of
- 8950, or DDOA, in hex digits.
In the debounce delay routine (Figure 19), the timer
interrupt is enabled and set to a higher priority than the
keyboard interrupt, because as we invoke Idle, the keyboard interrupt is still "in progress". An interrupt of
the same priority will not be acknowledged, and will
not terminate the Idle mode. With the timer interrupt
set to priority I, while the keyboard interrupt is a priority 0, the timer interrupt, when it occurs, will be acknowledged and will wake up the CPU. The timer interrupt service routine does not itself have to do anything. The service routine might be nothing more than
a single RETI instruction. RET! from the timer interrupt service routine then returns execution to the debounce delay routine, which shuts down the timer and
returns execution to the keyboard service routine.
DRIVING AN LCD
An LCD (Liquid Crystal Display) consists of a backplane and any number of segments or dots which will
be used to form the image being displayed. Applying a
voltage (nominally 4 or 5V) between any segment and
the backplane causes the segment to darken. The only
catch is that the polarity of the applied voltage has to
be periodically reversed, or else a chemical reac-
.
I d
(osc kHz) x (delay time ms)
timer pre oa =
12
,
2-205
intJ
AP-252
DEBOUNCE_DELAV:
MOV ,
. TL!, ITL! J'RELOAD , Preload law bvte.
MOV
TH1, ltTHIJ'RELOAD , PTeload high b~te.
Enable Timer 1 inteT'T'upt.
SETB
ETI
Set Timer 1 interrupt to hlgh pT'ioT'ity.
SETB
PTI
Start tlmer 1'unning.
SETB
TRI
ORL
peON, II
Invoke Idle mode.
The next instruction wl11 not be executed until' the delay time'l out.
CLR
CLR
CLR
RET
TRI
PTI
ETI
Stop th e t 1me".
Back to priority 0 (if desired).
Disable Timer 1 inter1'upt (if desired>.
Continue keyboard scan.
270068-20
Figure 19. Subroutine DEBOUNCE_DELAY Puts the 80C51BH into Idle During the Delay Time
tasks are not requiring servicing. When the timer rolls
over it generates an interrupt, which brings the
80CSIBH out ofldle. The service routine reloads the
timer (for the next rollover), and inverts the logic levels
of all the pins that are connected to the LCD. It might
look like this:
tion takes place in the LCD which causes deterioration
and eventual failure of the liquid crystal.
To prevent this happening, the backplane and all the
segments are driven with an AC signal, which is derived from a rectangular voltage waveform. If a segment is to be "oft" it is driven by the same waveform as
the backplane. Thus it is always at backplane potential.
If the segment is to be "on" it is driven with a waveform that is the inverse of the backplane waveform.
Thus it has about 5V of periodically changing polarity
between it and the backplane~
LCD_DRIVE_INTERRUPT:
MOV
TL1.#LOW( - XTAL_FREQ)
MOV
TH1.#HIGH( - XTAL_FREQ)
XRL
TENS_DIGIT.#OFFH
XRL
ONES_DIGIT.#OFFH
RETI
With a little software overhead, the 80C51BH can perform this task without the need for additional LCD
drivers. The only drawback is that each LCD segment
uses up one port pin, and the backplane uses one more.
If more than, say, two 7-segment digits are being driven, there aren't many port pins left for other tasks.
Nevertheless, assuming a given application leaves
enough port pins available to support this task, the considerations for. driving the LCD are as follows.
Suppose, for example, it is a 2-digit display with a deci-'
mal point. One port (TENS_DIGIT) connects to the 7
segments of the tens digit plus the backplane. Another
port (ONES_DIGIT) connects to a decimal point plus
. ,
the 7 segments of the ones digit.
To update the display, one would use a look-up.table to
generate the characters. In the table, "on" segments are
represented as. Is, and "off" segments as Os. The backplane bit is represented as a 0.. The quantity to be displayed is stored in RAM as a BCD value. The look-up
table operates on the low nibble of the BCD value, and
produces the bit pattern that is to be written to either
the ones digit or the tens digit. Before the new patterns
can be written to the LCD, the LCD drive interrupt has
to be disabled. That is to prevent a polarity reversal
from taking place between the times the two digits are
written. An update subroutine is shown in Figure 20.
USING AN LCD DRIVER
One of the 80C51 BH's timers is used to mark off halfperiods of the drive voltage waveform. The LCD drive
waveform should have a rep ·rate between 30 and 100
Hz, but it's not very critical. A half-period of 12 ms will
set the rep rate to about 42 Hz. The preload/reload
value to get 12 ms to rollover is the 2's complement
negative of the oscillator frequency in kHz: if the oscillator frequency is 3.58 MHz, the reload value is
- 3580, or F204 in hex digits.
Now, the 80C51BH would normally be in Idle, to conserve power, during the time that the LCD and other
As was noted, driving an LCD directly with an
80C51BH uses a lot of port pins. LCD drivers are available in CMOS to interface an 80CS1BH to a 4-digit
display using only 7 of the CS1BH's I/O pins. Basically, the C51BH tells the LCD driver what digit is to be
displayed (4 bits) and what position it is to be displayed
in (2 bits), and toggles a Chip Select pin to tell the
driver to latch this information. The LCD driver generates the display characters (hex digits), and takes care
of the polarity reversals using its own RC oscillator to
generate the timing.
2-206
intJ
AP-252
Figure 25 shows an 80CSlBH working with an
ICM72IIM to drive a 4-digit LCD, and the software
that updates the display.
One could equally well send information to the LCD
driver over the bus. In that case, one would set up the
Accumulator with the digit select and data input bits,
and execute a MOVX@ RO,A instruction. The LCD
driver's chip select would be driven by the CPU's WR
signal. This is a little easier in software than the direct
bit manipulation shown in Figure 21. However, it uses
more I/O pins, unless there is already some external
memory involved. In that case, no extra pins are used
up by adding the LCD driver to the bus.
RESONANT TRANSDUCERS
Analog transducers are often used to convert the value
of a physical property, such as temperature, pressure,
etc., to an analog voltage. These kinds of transducers
then require an analog-to-digital converter to put the
measurement into a form that is compatible with a digital control system. Another kind of transducer is now
becoming available that encodes the value of the physical property into a signal that can be directly read by a
digital control system. These devices are called resonant transducers.
Resonant transducers are oscillators whose frequency
depends in a known way on the physical property being
measured. These devices output a train of rectangular
pulses whose repetition rate encodes the value of the
quantity being measured. The pulses can in most cases
be fed directly into the 80CSlBH, which then measures
either the frequency or period of the incoming signal,
basing the measurement on the accuracy of its own
clock oscillator. The 80C51BH can even do this in its
sleep; that is, in Idle.
UPDATE_LCD'
CLR
MOV
MOV
SWAP
ANL
MOVC
MOV
MOV
ANL
MOVC
MOV
MOV
MOV
SETB
RET
When the frequency or period measurement is completed, the CSlBH wakes itself up for a very short time to
perform a sanity check on the measurement and convert it in software to any scaling of the measured quantity that may be desired. The software conversion can
include corrections for nonlinearities in the transducer's transfer function.
Resolution is also controlled by software, and can even
be dynamically varied to meet changing needs as a situation becomes more critical. For example, in a process
controller you can increase your resolution ("fine tune"
the control, as it were) as the process approaches its
target.
The nominal reference frequency of the output signal
from these devices is in the range of 20 Hz to SOO kHz,
depending on the design. Transducers are available that
have a full scale frequency shift 2 to 1. The transducer
operates from a supply voltage range of 3V to 20V,
which means it can operate from the same supply voltage as the 80CSlBH. At 5V, the transducer draws less
than S rnA (Reference 7). It can normally be connected
directly to one of the CSlBH's port pins, as shown in
Figure 22.
FREQUENCY MEASUREMENTS
Measuring a frequency means counting pulses for a
known sample time. Two timer/counters can be used,
one to mark off the sample time and one to count pulses. If the frequency being counted doesn't exceed SO
kHz or so, one may equally well connect the transducer
signal to one of the external interrupt pins, and count
pulses in software. That frees up one timer, with very
little cost in CPU time.
The count that is directly obtained is TxF, where T is
the sample time and F is the frequency. The full scale
ETI
Disable LCD drive Interrupt.
DPTR. #TABLE_ADDRESS
A, BCD_VALUE
A
Look-up
table begins at TABLE_ADDRESS
A. lIOFH
Digits to be displaqed.
Move tens digit to low nibble
Mask off high nibble
Tens digit pattern to accumulator
Update LCD tens digit.
Digits to be displayed
Mask of' tens digit
A. (!A+DPTR
Ones digit pattern to accumulator
c. DEC lMAL]OJ NT
Add decimal point to segment
pattern.
Update LCD dec imal pOint
and ones digit
Re-enable LCD drive 1nterrupt.
A.IOFH
A.@A+DPTR
TENS_DIGIT. A
A. BCD_VALUE
ACC. 7. C
ONES_DIGIT. A"
ETI
270068-21
Figure 20. UPDATE_LCD Routine Writes Two Digits to an LCD
2-207
AP-252
range is Tx(Fmax-Fmin). For n-bit resolution
For example, 8-bit resolution in the measurement of a
frequency that varies between 7 kHz and 9 kHz would
require, according to this formula, a sample time of 128
ms. The maximum acceptable frequency count would
be 128 ms X 9 kHz = 1152 counts. The minimum
would be 896 counts. Subtracting 896 from each frequency count (or presetting the frequency counter' to
- 896 = OFC80H) would allow the frequency to be
reported on a scale of 0 to FF in hex digits.
1 LSB = Tx(Fmax-Fmin)
2n
Therefore the sample time required for n-bit resolution
is
2n
T = ""Fm-ax--F:::-m-i'-n
aOC51BH
~,{
'\
1 } DIGIT
2
SELECT
M}
PORT
81
82
L.
C.
D.
'\
DATA
INPUT
83
CS
."
270068-22
Figure 21a. Using an LCD Driver
UPDATE_LCD:
MOV
SETa
SETS
CALL
CLR
CALL
MOV
CLR
SETS
CALL
CLR
CALL
RET
A. DISPLAY_HI
DIGIT _SELECT_2
DIGIT _SELECT_1
SH I FT _AND _LOAD
DIGIT _SELECT_1
SHIFT_AND_LOAD
A.DISPLAY_LO
DIGIT _SELECT_2
DIGlT_SELECT_1
SHIFT _AND_LOAD
DIGIT_SELECT_1
SHIFT_ANO_LOAD
High
b~te
of 4-dig.t
disp1a~.
Select leftmost digit 09 LCD.
(Digit address = lIB. )
High nibble of high byte to selected digit
Select second digit of LCD (address = 10D)
Low nibble of high byte to selected digit.
4.
Low by teo of 4-dlgit d1splay.
Select third digit
LCD.
(Oig1t address = 01B. )
Hlgh nibble of low byte to seletted dLg!t.
Select fourth digit (address = OOB),
Low nibble of low byt,e to selec:ted dIgit.
SHIFT _AN~L~OAD
MOV
DATA_iNPUT _B3. C
MS8 to carr~ bit (CV)
CV to Data Input pin 83.
RLC
A
Next bit to CV.
MOV
A
DATA_INPUT _B2. C
tv to Data Input pin
RLC
A
Next bit to CV
MOV
DATA_INPUT_BI.C
CV to Data Input pin 91
Last bit to cv.
CV to Data Input pin BO.
Toggle Chip Select.
O-to-l transition latches info.
RLC
A
MOV
DATA_INPUT _BO. C
CHIP _SELECT
CHIP _SELECT
CLR
SETB
RET
B2
270068-23
Figure 21b. UPDATE_LCD Routine Writes 4 Digits to an LCD Driver
2-208
AP-252
At this point the value of the frequency of the transducer signal, measured to 8 bit resolution, is contained in
FREQUENCY. Note that the timer can be reloaded on
the fly. Note too that the timer can be reloaded on the
fly. Note too that for 8-bit resolution only the low byte
of the frequency counter needs to be read, since the
high byte is necessarily 0. However, one may want to
test the high byte to ensure that it is zero, as a sanity
check on the data. Both bytes, of course must be reloaded,
VCC
vcc tRESONANT
TRANSDUCER
t-
aOC51BH
INTO
OR
TO
\-'"
PERIOD MEASUREMENTS
270066-24
Figure 22. Resonant Transducer Does Not
Require an AID Converter
To implement the measurement, one timer is used to
establish the sample time. The timer is preset to a value
that causes it to roll over at the end of the sample time,
generating an interrupt and waking the CPU from its
Idle mode. The required preset value is the 2's complement negative of the sample time measured in machine
cycles. The conversion from sample time to machine
cycles is to mUltiply it by 1/12 the clock frequency. For
example, if the clock frequency is 12 MHz, then a sample time of 128 ms is
(128 ms) x (12000 kHz)/12 =' 128000 machine cycles.
Measuring the period of the transducer signal means
measuring the total elapsed time over a known Dumber,
N, of transducer pulses. The quantity that is directly
measured is NT, where T is the period of the transducer signal in machine cycles. The relationship between T
in machine cycles and the transducer frequency F in
arbitrary frequency units is
Fxtal
T = -F- x (1/12),
where Fxtal is the 80C51BH clock frequency, in the
same units as F.
The full scale range then is Nx (Tmax-Tmin). For
n-bit resolution.
1LSB=
Then the required preset value to cause the timer to roll
over in 128 ms is
Therefore the number of periods over which the elapsed
time should be measured is
-128000 = FEOCOO, in hex digits.
Note that the preset value is 3 bytes wide whereas the
timer is only 2 bytes wide. This means the timer must
be augmented in software in the timer interrupt routine
tlil three bytes. The 80C5IBH has a DJNZ instruction
(decrement and jump if not zero) that makes it easier to
code the third timer byte to count down instead of up.
If the third timer byte counts down, its·reload value is
the 2's complement of what it would be for an up-counter. For example, if the 2's complement of the sample
time is FEOCOO, then the reload value for the third
timer byte would be 02, instead of FE. The timer interrupt routine might then be:
TIMER_INTERRUPT_ROUTINE:
DNJZ
THIRD_TIMER_BYTE,OUT
MOV
TLO,#O
MOV
THO,#OCH
MOV
THIRD_TIMERBYTE,#2
MOV
FREQUENCy,COUNTER_LO
;Preset COUNTER to -896:
MOV
COUNTER_LO,#80H
MOV
COUNTER_HI,#OFCH
OUT:
RETI
Ns(Tmax-Tmin)
2"
2"
N=--Tmax-Tmin
However, N must also be an integer. It is logical to
evaluate the above formula (don't forget Tmax and
Tmin have to be in machine cycles) and select for N the
next higher integer. This selection gives a period measurement that has somewhat more than n-bit resolution, but it can be scaled back if desired.
For example, suppose we want 8-bit resolution in the
measurement of the period of a signal whose frequency
varies from 7.1 kHz to 9 kHz. If the clock frequency is
12 MHz, then Tmax is (12000 kHz/7.1 kHz) x (1/12)
= 141 machine cycles. Tmin is II ~ machine cycles.
The required value for N, then, is 256/(141-111) =
8.53 periods, according to the formula. Using N = 9
periods will give a maximum NT value of 141 x 9 =
1269 machine cycles. The minimum NT will be III X
9 = 999 machine cycles. A lookup table can be used to
2-209
inter
AP-252
ADDC
MOV
CLR
MOVC
MOV
POP
POP
RET
scale these values back to a range of 0 to 255, giving
precisely the 8-bit resolution desired.
To implement the measurement, one timer is used to
measure the elapsed time, NT. The transducer is connected to one of the external interrupt pins, and this
interrupt is configured to the transition-activated mode.
In the transition-activated mode every I-to-O transition
in the transducer output will generate an interrupt. The
interrupt routine counts transducer pulses, and when it
gets to the predetermined N, it reads and clears the
timer. For the specific example cited above, the interrupt routine might be:
OUT:
DJNZ
MOV
CLR
CLR
MOV
MOV
MOV
MOV
SETB
SETB
CALL
RETI
N,OUT
N,#9
EA
TRI
NT_LO,TLI
NT_HI,THI
TLl,#9
THl,#O
TRI
EA
LOOKUP_TABLE
The subroutine LOOKUP-,-TABLE is used to scale
the measurement back to the desired 8-bit resolution. It
can also include built-in corrections for errors or nonlinearities in the transducer's transfer function.
The subroutine uses the MOVC A, @ A + DPTR
instruction to access the table, which contains 270 entries commencing at the 16-bit address referred to as
TABLE. The subroutine must compute the address of
the table entry that corresponds to the measured value
of NT. This address is
+ NT
- NTMIN,
where NTMIN = 999, in this specific example.
LOOKUP_TABLE:
PUSH
PUSH
MOV
ADD
MOV
MOV
A,@A+DTPR
PERIOD,A
PSW
ACC
At this point the value of the period of the transducer
signal, measured to 8 bit resolution, is contained in PERIOD.
The 80C51BH timers have an operating mode which is
particularly suited to pulse width measurements, and
will be useful in these applications if the transducer
signal has a fixed duty cycle.
In this routine a pulse counter N is decremented from
its preset value, 9, to zero. When the counter gefs to
zero it is reloaded to 9. Then all interrupts are blocked
for a short time while the timer is read and cleared. The
timer is stopped during the read and clear operations,
so "clearing" it actually means presetting it to 9, to
make up for the 9 machine cycles that are missed while
the timer is stopped.
DPTR = TABL
A
PULSE WIDTH MEASUREMENTS
INTERRUPT~RESPONSE:
.
A,NLHI
DPH,A
ACC
PSW
A,#LOW(TABLE-NTMIN)
A,NT_LO
DPL,A
A,#HIGH(TABLE-NMTIN)
In this mode the timer is turned on by the on-chip
circuitry in response to an input high at the external
interrupt pin, and off by an input low, and it can do this
while the 80C5IBH is in Idle. (The "GATE" mode of
timer operation is described in the Intel Microcontroller Handbook.) The external interrupt itself can be enabled, so the same I-to-O transition from the transducer
that turns off the timer also generates an interrupt. The
interrupt routine then reads and resets the timer.
The advantage of this method is that the transducer
signal has direct access to the timer gate, with the result
that variations in interrupt response time have no effect
on the measurement.
Resonant transducers that are designed to fully exploit
the GATE mode have an internal divide-by-N circuit
that fixes the duty cycle at 50% and lowers the output
frequency to the range of 250 to 500 Hz (to control
RFI). The transfer function between transducer period
and measurand is approximately linear, with known
and repeatable error functions.
HMOS/CHMOS Interchangeability
The CHMOS version of the 8051 is architecturally
identical with the HMOS version, but there are nevertheless some important differences between them which
the designer should be aware of. In addition, some applications require. interchangeability between HMOS
and CHMOS parts. The differenceS that need to be considered are as follows:
External Clock Drive: To drive the HMOS 8051 with
an external clock signal, one normally grounds the
XTALI pin and drives the XTAL2 pin. To drive the
CHMOS 8051 with an external clock signal, one must
drive the XTALl pin and leave the XTAL2 pin unconnected. The reason for the difference is that in the
2-210
intJ
AP-252
HMOS 8051, it is the XTAL2 pin that drives the internal clocking circuits, whereas in the CHMOS version it
is the XTALl pin that drives the internal clocking circuits.
CMOS~I!_
HMOS
TTL VIH
There are several ways to design an external clock drive
to work with both types. For low clock frequencies (below 6 MHz), the HMOS 8051 can be driven in the same
way as the CHMOS version, namely, through XTALI
with XTAL2 unconnected. Another way is to drive
both XTALl and XTAL2; that is, drive XTALl and
use and external inverter to derive from XTALI a signal with which to drive XTAL2.
In either case, a 74HC or 74HCT circuit makes an excellent driver for XTALI and/or XTAL2, because neither the HMOS nor the CHMOS XTAL pins have
TTL-like input logic levels.
Unused Pins: Unused pins of Ports I, 2 and 3 can be
ignored in both HMOS and CHMOS designs. The internal pullups will put them into a defined state. Unused Port 0 pins in 8051 applications can be ignored,
even if they're floating. But in 80C5IBH applications,
these pins should not be left afloat. They can be externally pulled up or down, or they can be internally
pulled down by writing Os to them.
8031/80C31BH designs mayor may not need pullups
on Port O. Pullups aren't needed for program fetches,
because in bus operations the pins are actively pulled
high or low by either the 8031 or the external program
memory. But they are needed for the CHMOS part if
the Idle or Power Down mode is invoked, because in
these modes Port 0 floats.
Logic Levels: If Vee is between 4.5V and 5.5V, an
input signal that meets the HMOS 8051's input logic
levels will also meet the CHMOS 80C5IBH's input logic levels (except for XTALl/XTAL2 and RST). For
the same Vee condition, the CHMOS device will re~ch
or surpass the output logic levels of the HMOS device.
The HMOS device will not necessarily reach the output
logic levels of the CHMOS device. T~is is an impo~~nt
consideration if HMOS/CHMOS mterchangeablhty
must be maintained in an otherwise CMOS system.
HMOS 8051 outputs that have internal pullups (Ports
1,2, and 3) "typically" reach 4V or more if IOH is zero,
but not fast enough to meet timing specs. Adding an
external pullup resistor will ensure the logic l~ve!, b~t
still not the timing, as shown in Figure 23. If tImmg IS
an issue, the best way to interface HMOS to CMOS is
through a 74HCT circuit.
270068-25
Figure 23. O-to-1 Transition Shows Unspec'd
Delay (Llt) in HMOS to 74HC Logic
wishes to pre&erve the capability of interchanging
HMOS and CHMOS 8051s the software has to be designed so that the HMOS parts will respond in an acceptable manner when a CHMOS reduced power mode
is invoked.
For example, an instruction that invokes Power Down
can be followed by a "JMP $":
CLR
ORL
JMP
EA
PCON.#2
$
The CHMOS and HMOS parts will respond to this
sequence of code differently. The CHMOS part: going
into a normal CHMOS Power Down Mode, will stop
fetching instructions until it gets a ha~dware reset. ~he
HMOS part will go through the motIons of executmg
the ORL instruction, and then fetch the JMP instruction. It will continue fetching and executing JMP $ until hardware reset.
Maintaining HMOS/CHMOS 8051 interchangeability
in,response to Idle requires more planning. The HMOS
part will not respond to the instruction that puts the
CHMOS part into Idle, so that instructionneeds.to.be
followed by a software idle. This would be an Idhng
loop which would be terminated by the same conditions
that would terminate the CHMOS's hardware Idle.
Then when the CHMOS device goes into Idle, the
HMOS version executes the idling loop, until either a
hardware reset or an enabled interrupt is received. Now
if Idle is terminated by an interrupt, execution for the
CHMOS device will proceed after RETI from the instruction following the one that invoked Idle. The instruction following the one that invoked Idle is the
idling loop that was inserted for the HMOS d.evice. At
this point, both the HMOS and CHM~S devices ~ust
be able to fall through the loop to contmue executIOn.
Idle and Power Down: The Idle and Power Down
modes exist only on the CHMOS devices, but if one
2-211
intJ
AP-252
One way to achieve the desired effect is to define a
"fake" Idle flag, and set it just before going into Idle.
The instruction that invoked Idle is followed by a software idle:
SETB
ORL
JB
IDLE
PCON,#l
IDLE,$
Now the interrupt that terminates the CHMOS's Idle
must also break the software idle. It does so by clearing
the "Idle" bit:
REFERENCES
I. Pawlowski, Moroyan, Alnether, "Inside CMOS
2.
3.
4.
CLR
RETr
IDLE
Note too that the PCON register in the HMOS 8051
contains only one bit, SMOD, whereas the PCON register in CHMOS contains SMOD plus four other bits.
Two of those other bits are general purpose flags. Maintaining HMOS/CHMOS interchangeability requires
that these flags not be used.'
'
5.
Technology," BYT$ magazine, Sept., 1983. Available as Article Reprint AR-302.
Kokkonen, Pashley, "Modular Approach to C-MOS
Technology Tailors Process to Application,"
Electronics, May, 1984. Available as Article Reprint
AR-332.
Williamson, T., Designing Microcontroller Systems
for Electrically Noisy Environments, Intel Application Note AP-125, Feb. 1982.
Williamson, T., "PC Layout Techniques for Minimizing Noise," Mini-Micro Southeast, Session 9,
Jan., 1984.
Alnether, J., High Speed Memory System Design Using 2147H, Intel Application Note AP-74, March
1980.
6. Ott, H., "Digital Circuit Grounding and Interconnection," Proceedings of the IEEE Symposium on
Electromagnetic Compatibility, pp. 292-297, Aug.
1981.
7. Digital Sensors by Technar, Technar Inc., 205 North
2nd Ave., Arcadia, CA 91006.
2-212
AP-410
APPLICATION
NOTE
November 1987
Enhanced Serial Port
on the 83C51FA
BETSY JONES
ECO APPLICATIONS ENGINEER
© Intel Corporation, 1987
Order Number: 270490-001
2-213
AP-410
The serial port on the 8051 has been enhanced on the
83CSIFA with the addition of two new features: Automatic Address Recognition and Framing Error Detection. Automatic Address Recognition facilitates multiprocessor communications by reducing CPU overhead.
Framing Error Detection increases communication reliability by checking each reception for a valid stop bit.
This Application Note explains how to use these new
features with samples of code for typical applications.
A section is also included which reviews how to set up
the serial port for multiprocessor applications.
MULTIPROCESSOR
COMMUNICATIONS'
In applications where multiple controllers jointly perform a task, the master controller must be able to communicate selectively with individual slaves. To do this,
the master first identifies the target slave (or slaves)
with an address byte and then transmits a block of data.
The target slaves must be able to identify their own
address before receiving any dat~ bytes.
The serial port on the 8051 provides a 9-bit mode to
facilitate multiprocessor communication. The 9th bit
allows the controller to distinguish between address
and data bytes. In this mode, a total of II bits are
received or transmitted: a ~tart bit (0), 8 data bits (LSB
first), a programmable 9th bit, and a stop bit (I). See
Figure below.
The 9th bit is set to I to identify address bytes and set
to' 0 for data bytes. A typical data stream is seen below:
ADDRESS BYTE
08 = 1
DATA BYTE
08 = 0
DATA BYTE I
08 = 0
...
Initially the slave is set up to only receive address bytes.
Once it receives its own address, the slave reconfigures
itself to receive data. On the 8051 serial port, an address byte interrupts all slaves for an address comparison. On the 83C5IFA, however, Automatic Address
Recognition allows the addressed slave to be the only
one interrupted; that is, the address comparison occurs
in hardware, not software. With this feature, the master
controller can establish communication with one or
more slaves without all the slaves having to respond to
the transmission.
AUTOMATIC ADDRESS
RECOGNITION
Automatic Address Recognition reduces the CPU time
required to service the serial port. Since the CPU is
only interrupted when it receives its own address, the
software overhead to compare addresses is eliminated.
This would also effectively reduce the sophistication of
the serial protocol when numerous controllers are sharing the same serial link.
This same feature can also be used in conjunction with
the Idle Mode to reduce the system's overall power
consumption. For instance, a master may need to communicate with only one slave at a time. With all slaves
in Idle Mode, only that one slave would be interrupted
to respond to the master's transmission. Without Automatic Addressing, each slave would have to "wake up"
to check for its address. Limiting the interruptions reduces the amount of current drawn by the system and
thus reduces the power consumption.
In multiprocessor applications the serial port is configured in either of the 9-bit modes (Mode 2 or 3). Mode 2
has a fixed baud rate whereas Mode 3 is variable. For
more information on the different serial port modes re.
fer to the "Serial Port Set Up" section.
Aufomatic Address Recognition is enabled by setting
the SM2 bit in SCaN. Each slave has its SM2 bit set
waiting for an address byte (9th bit = I). The Receive
Interrupt (RI) flag will get set when the received byte
corresponds to either a Given or Broadcast Address.
The slave then clears its SM2 bit to enable reception of
data bytes (9th bit = 0) from the master.
The master can selectively communicate with groups of
slaves by using the Given Address. Addressing all
slaves at once is possible with the Broadcast Address.
These addresses are defined for each slave by two new'
Special Function Registers: SADDR and SADEN.
A slave's individual address is specified in SADDR.
SADEN is a mask byte that defines don't-cares to form
the Given Address. These,don't-cares allow flexibility
in the user-defined protocol to address one or more
slaves. The following is an example of how to define
Given Addresses and selectively address different
slaves.
STOP BIT
NINTH DATA BIT
270490-1
inter
AP-410
FRAMING ERROR DETECTION
Slave 1
SAOOA
SAOEN
1111
1111
0001
101Q
GIVEN
1111
OXOX
Slave 2
SAOOA
SAOEN
1111
1111
0011
1001
GIVEN
1111
OXX1
Framing Error Detection is another new feature on
83C51FA serial port which allows the receiving controller to check for valid stop bits in Modes I, 2, or 3. A
missing stop bit can be caused, for example, by noise on
the serial lines or transmission by two CPUs simultaneously.
The SADEN bytes have been selected such that bit 1
(LSB) is a don't-care for Slave I's Given Address, but
bit 1 = 1 for Slave 2. Thus, to selectively communicate
with just Slave 1 an address with bit 1 = 0 would be
used (e.g. 1111 0000).
Similarly, bit 2 = 0 for Slave I, but is a don't-care for
Slave 2. Now to communicate with just Slave 2 an address with bit 2 = I would be used (e.g. 1111 0111).
Finally, to communicate with both slaves at once the
address must have bit I = I and bit 2 = O. Notice,
however, that bit 3 is a "don't-care" for both slaves.
This allows two different addresses to select both slaves
(1111 0001 or III I 0101). If a third slave was added
that required its bit 3 = 0, then the latter address could
be used to communicate with Slave I and 2 but not
Slave 3.
The master can also communicate with all slaves at
once with the Broadcast Address. It is formed from the
logical OR of SADDR and SADEN with zeros defined
as don't-cares. For example, the Broadcast address for
Slave I would be formed as follows:
SADDR
SADEN
= 1111 0001
= 11111010
=D-
BROADCAST
=1111
lXll
270490-2
The don't-cares also allow flexibility in defining the
Broadcast Address, but in most applications a Broadcast Address will be OFFH.
SADDR and SADEN are located at address A9H and
B9H, respectively. On Reset, SADDR and SADEN are
initialized to OOH which defines the Given and Broadcast Addresses as XXXX XXXX (all don't-cares). This
assures the 83C51FA serial port to be backwards compatible with the other MCS®~51 products which do not
implement Automatic Addressing.
If a stop bit is missing a Framing Error bit FE will be
set. This bit can then be checked in software after each
reception to detect communication errors. Once set, the
FE bit must be cleared in software. A valid stop bit will
not clear FE.
The FE bit is located in SCON and shares the same bit
address as SMO. To determine which is accessed, a new
control bit called SMODO has been added in the PCON
register (see figures below). If SMODO = 0, then accesses to SCON.7 are to SMO. If SMODO = I, then
accesses to SCON.7 are to FE.
PCON: Power Control Register (Not Bit Addressable)
I SM001 I SMODO I-I POF I GF1 I GFO I PO IIOL I
Address = 87H
SCON: Serial Port Control Register (Bit Addressable)
I SMO/FE I SM1 I SM2,I AEN I TBSI ABSI TI I All
Address = 98H
SERIAL PORT SOFTWARE
The following sections of code show examples of how
to invoke Automatic Addressing and Framing Error
Detection. Routines for both the slave and master are
given. Code is also included to initialize both serial
ports; however, for more information on setting up the
serial port refer to the next section.
For this example, the master and slave are transmitting/receiving at 9600 baud with a 12 MHz crystal frequency. To obtain this baud rate, the serial port is configured in Mode 3 and Timer 2 is used as the baud-rate
generator.
Listing I shows the initialization for the slave. Notice
that Automatic Addressing and Framing Error Detection are enabled. The Given and Broadcast addresses
for this slave are taken from Slave I in the previous
example. A temporary byte has also been defined to
store the incoming data byte.
The slave will remain in Idle Mode until it is interrupted by its own address. At that point, it clears the SM2
2-215
inter
AP·410
Listing 1. Initialization Routine for the Slave
ORG
LJMP
OOH
INIT
ORG
LJMP
0023H
SERIAL_PORT_INTERRUPT
TEMP
DATA
30H
Temporary storage byte
INIT: MOV SCON, #OFOH
ORL
MOV
MOV
MOV
PCON, #40H
RCAP2H, #OFFHRCAP2L, #OD9H
T2CON, #34H
Mode 3, enable Auto Addressing
and reception
FE bit accessed (SMODO
1)
Reload values for 9600 Baud
=
Timer 2 set up, TR2
timer on
=1 turns
INTERRUPTS:
SETB EA
SETB ES
Enable global interrupt
Enable serial port interrupt
ADDRESSES:
MOV SADDR, # 11110001
MOV SADEN, # 11111010
Define Given & Broadcast
Addresses
GIVEN
1l1l0XOX
BROADCAST
11111X11
ORL PCON, #OlH
Invoke Idle Mode
=
=
Listing 2. Receive Routine for the Slave
SERIAL_PORT INTERRUPT:
PUSH PSW
CLR RI
CLR SM2
RECEIVE_DATA:
JNB RI, $
MOV C, SCON.7
JC FRAMING_ERROR
MOV TEMP, SBUF
CLR RI
SETB 5M2
RI set when address is
recognized & must be cleared
in software
Reconfigure slave to receive
data bytes
Wait for RI to be set
Check for framing error
Receive data byte & store
in temporary location
Clear flag for next
reception
Re-enable Automatic
Addressing
POP PSW
RETI
FRAMING_ERROR:
CLR SCON.7
CLR C '
•
•
•
Clear FE bit
Error routine left up to
the user
POP PSW
RETI
2-216
inter
AP-410
Listing 3. Initialization and Transmit Routines for the Master
GIVEN_l
MESSAGE_l
INIT:
MOV
MOV
MOV
MOV
equ
data
1l1l0001B
30H
SCON, #ODOH
RCAP2H, #OFFH
RCAP2L, #OD9H
T2CON, #34H
TRANSMIT_ADDRESS:
CLR TI
SETB TBB
MOV SBUF, #GIVEN_l
JNB
TI, $
CLR TI
TRANSMIT_DATA:
CLR TBB
MOV SBUF, MESSAGE_l
JNB TI, $
CLR TI
Mode 3, REN
9600 Baud
=1
Timer 2 set up, TR2
=1
Mark 1st byte as an address
byte (9th bit
1)
Send address
Wait for transmission
complete
Clear flag for next
transmission
=
Mark 2nd byte as a data
byte (9th bit
0)
Send data byte
=
bit to enable reception of data bytes. Depending on the
user's protocol, more than one data byte may actually
be received. This example, however, assumes only one
byte of data follows each address byte.
Listing 2 shows the receive routine. Notice that when
the data byte is received, the software checks for a
framing error. The error routine could, for example,
send an error message to the master and ask the master
to re-transmit the last message. Before exiting the routine the SM2 is set to I to reenable Automatic Addressing. Once the slave has responded to the master's command, it could also put itself back into Idle Mode to
wait for, the next message.
The initialization routine for the master in Listing 3 is
very similar to the slave. In this example, however, the
master does not need Automatic Addressing; it is simply transmitting address and data bytes. GIVEN_l is
a byte to address the slave in the above example.
MESSAGE_l is a register that contains the data byte
sent to this slave. Its value is arbitrary for the sample
code.
SERIAL PORT SET UP
This section describes how to initialize the 83C51FA
serial port for multiprocessor applications. Two different modes are available which provide 9-bit operation:
Mode 2 which has a fixed baud rate and Mode 3 which
has a .variable baud rate. Baud rates can be generated
by either Timer 1 or Timer 2 (available on the
83C51FA but not the 8051). Deciding which mode and
timer to use is determined by the desired baud rate and
clock frequency of the particular application.
Another consideration is the tolerance needed between
serial ports. Since the serial port re-synchs its receiver
at every start bit, only 8 or 9 bit-times are available to
accumulate timing errors. As a result, the receiver and
transmitter only have to be within about 5% of each
other's baud rate. Allowing equal error to both transmitter and receiver, only about 2% accuracy is actually
needed.
Following is a discussion of both Modes 2 and 3 and
examples of how to program each. The mode selection
bits (SMO and SMl) are located in SCON. The REN
bit must also be set to enable reception.
SCON: Serial Port Control Register (Bit Addressable)
ISMO I SM1 15M2 I REN I TBB I ABB I TI I AI
Address = 98H
Mode
SMO
2
1
2-217
3
SMl
o
Baud Rate
Fosc/64 or
Fosc/32
Variable
intJ
Ap·410
Example 1. Serial Port Mode 2
Frequency
Desired Baud Rate
MOV SCON, #OBOH
= 12 MHz
= 1/32 (Osc
=375 kBaud
Freq)
Serial port Mode 2
Automatic Addressing (SM2
1),
reception enabled (REN
1)
SMODl
1 to double baud rate
=
=
ORL PCON, #80H
=
Mode 2
Mode 2 uses a fixed baud rate of 1/32 or 1/64 of the
oscillator frequency depending on the value of the
SMODI bit in PCON. This mode basically offers a
choice of two high-speed baud rates. With a 12 MHz
clock frequency, baud rates of 187.5 kbaud or 375
kbaud can be obtained.
are Ml and MO located in TMOD. To turn on Timer 1
the TR1 bit in TCON must be set. Also, the Timer 1
interrupt should be disabled in this application so that
when the timer overflows it does not generate an interrupt.
None of the timer/counters need to be set up for Mode
2. Only the SFRs SCON and PCON need to be defined.
IGATEI CIT I M1 I MO IGATEI CIT IM1 I MO
PCON: Power Control Register (Not Bit Addressable)
Timer 1
Address = 89H
I SMOD1 I SMOOO I-I PDF I GF1 I GFO I PO IIOL I
The baud rate in this mode is calculated by:
Mode 2 Baud Rate
=
=
0,
1,
\,
I\,
I
I
Timer 0
TCON: Timer/Counter Control Register
(Bit addressable)
Address = 87H
SMOD1
SMOD1
TMOD: Timer/Counter' Mode Control Register
(Not bit addressable)
2SMODl
=
Baud Rate
Baud Rate
=
=
I TF1 I TR1 I TFO I TRO IIE1
Osc Freq
64
X
IT1 I lEO liTO
I
Address = 88H
The formula for calculating the baud rate is given below. THI is the reload value for Timer 1 when it overflows.
1/64 Osc Freq
1/32 Osc Freq
Mode 3
Mode 3 of the serial port has a variable'baud rate generated by either Timer 1 or Timer 2. The baud rate is
generated by the rollover rate of the selected timer. The
timer is operated in an auto-reload mode so it will roll
over to the- reload value selected in software.
Baud rates based otT Timer 2 have less granularity so
that almost any baud rate can be obtained at a given
clock frequency. However, Timer 1 is sufficient if the
desired baud rate can be obtained at the specified clock
frequency. Remember baud rates only need about 2%
accuracy.
Timer 1 Set Up
To generate baud rates Timer I is usually configured in
8-bit auto-reload mode (Mode 2). The mode select bits
Baud Rate
=
K x Osc Freq
32 x 12 x [256 - (TH1)1
K = 1 if SMOD1 ,;. o.
K = 2 if SMOD1 = 1. (SMOD1 is at peON.7)
If the baud rate is known, the reload value THI can be
calculated by:
TH1
=
256 _
K x Osc Freq
384 x Baud Rate
THI must be an integer value. Rounding off THI to
the nearest integer may not produce the desired baud
rate with the 2% accuracy required. In this case, another crystal frequency may have to be chosen.
Refer to Table 1 for timer reload values for commonly
used baud rates.
2-218
intJ
AP-410
Table 1. Commonly Used Baud Rates Generated by Timer 1
OscFreq
Baud Rate
62.5K
19.2K
9.6K
4.BK
2.4K
1.2K
300
110
Timer 1
SMOD1
12 MHz
11.06 MHz
11.06 MHz
11.06 MHz
11.06 MHz
11.06 MHz
6MHz
6MHz
TMOD
Reload Value
20
20
20
20
20
20
20
20
FFH
FDH
FDH
FAH
F4H
EBH
CCH
72H
1
1
0
0
0
0
0
0
Example 2. Serial Port Mode 3, with Timer 1 as Baud-Rate Generator
Frequency
Desired Baud Rate
= 11.0 MHz
= 19.2 kBaud
6
TH1 = 256 _ (2) x (11.0 x 10 )
(32) x (12) x (19200)
= 253 = FDH
MOV SCON, #OFOH
ORL PCON, #BOH
MOV TMOD, #20H
MOV TH1, #OFDH
SETB TR1
Serial port Mode 3, SM2 = 1,
.,REN=l
SMOD1
1
Timer 1 Mode 2
Reload value for desired baud
rate
Turn on Timer 1
=
It can be seen that the exact frequency to generate the
standard baud rates (19.2K, 9600, 4800, etc.) is
11.06 MHz. However, it is not necessary to use this
exact frequency. With a 2% tolerance any crystal value
from 10.8 MHz to 11.3 MHz is sufficient.
interrupt then becomes available as a third external interrupt. (For more information on external interrupts,
refer to the chapter "Hardware Description of the
8051" in the Embedded Controller Handbook.)
T2CON: Timer/Counter 2 Control Register
(Bit Addressable)
Timer 2 Set Up
Timer 2 has a special baud-rate generator mode which
transmits and receives at the same baud rate. This
mode is invoked by setting both the RCLK and TCLK
bits in T2CON. To turn Timer 2 on the TR2 bit should
also be set.
Unlike Timer 1, this mode does not require that the
timer overflow interrupt be disabled. That is, when
Timer 2 is in the baud-rate generator mode, its interrupt is disconnected froin the Timer 2 overflow. This
ITF2IEXF2IRCLKITCLKIEXEN2ITR2Ic/T2lcP/RL21
Address = C8H
This formula for calculating the baud rate is given below. (RCAP2H, RCAP2L) is the 16-bit reload value
when Timer 2 overflows.
B
au
d R te =
a
Gsc Freq
32
x
[65536 - (RCAP2H, RCAP2L))
where (RCAP2H, RCAP2L) is a 16-bit unsigned integer.
2-219
intJ
AP-410
To obtain the reload value for RCAP2H and RCAP2L
the above equation can be rewritten as:
(RCAP2H. RCAP2L) = 65536 - 32
~S::U~ate
Table 2. Commonly Used Baud Rates
Generated by Timer 2
Baud Rate
Refer to Table 2 for reload values' for commonly used
baud rates.
Notice that when using Timer 2, most standard baud
rates can be .obtained at 12 MHz.
375K
9.6K
4.SK
2.4K
1.2K
300
110
300
110
Timer 2
OscFreq
12MHz
12 MHz
12MHz
12MHz
12MHz
12MHz
12MHz
6MHz
6MHz
RCAP2H
RCAP2L
FF
FF
FF
FF
FE
FB
F2
FO
F9
FF
09
B2
64
CS
1E
AF
SF
57
Example 3. Serial Port Timer with Timer 2 as Baud-Rate Generator
Frequency
Desired Baud Rate
(RCAP2H, RCAP2L)
MOV SCON, #OFOH
MOV RCAP2H, #OFFH
MOV RCAP2L, #OD9H
MOV T2CON, #34H
12 MHz
= 9600
= Baud
(12 x 10 6 )
= 65536 - (32) x (9600)
= 65497 = FFD9H
Serial port Mode 3, SM2 = 1,
REN = 1
Reload values for de.sired
baud rate
Timer 2 as baud rate
generator, turn on Timer 2
2-220
inter
APPLICATION
BRIEF
AB-41
September 1988
Software Serial Port Implemented
with the peA
BETSY JONES
ECO APPLICATIONS ENGINEER
@ Intel Corporation, 1988
2-221
Order Number: 270531-002
intJ
AB-41
For microcontroller applications which require more
than one serial port, the 83C51FA Programmable
Counter Array (PCA) can implement additional halfduplex serial ports. If the on-chip UART is being used
as an inter-processor link, the PCA can be used to interface the 83C51FA to additional asynchronous lines.
This application uses several different Compare/Capture modes available on the PCA to receive or transmit
bytes of data. It is assumed the reader is familiar the
PCA and ASM51. For more information on the PCA
refer to the "Hardware Description of,the 83C51FA"
chapter in the Embedded Controller Handbook (Order
No. 210918).
Introduction
The figure below shows the format of a standard IO-bit
asynchronous frame: I start bit (0), 8 data bits, and I
stop bit (I). The start bit is used to synchronize the
receiver to the transmitter; at the leading edge of the
start bit the receiver must set up its timing logic to
sample the incoming line in the center of each bit. Following the start bit are eight data bits which are transmitted least significant bit first. The stop bit is set to the
opposite state of the start bit to guarantee that the leading edge of the start bit will cause a transition on the
line. It also provides a dead time on the line so that the
receiver can maintain its synchronization.
Two of the Compare/Capture modes on the PCA are
used in receiving and transmitting data bits: When receiving, the Negative-Edge Capture mode allows the
PCA to detect the start bit. Then using the Software
, Timer mode, interrupts are generated to sample the incoming data bits. This same mode is used to clock out
bits when transmitting.
This Application Note contains four sections of code:
(3) Receive routine
(4) Transmit routine.
A complete listing of the routines and the test loop
which was used to verify their opera~ion is found in the
Appendix. A total of three half-duplex channels were
run at 2400 Baud in the test program. The listings
shown here are simplified to one channel (Channel 0).
Variables
Listing I shows the variables used in both the receive
and transmit routines. Flags are defined to signify the
status of the reception or transmission of a byte
(e.g. RCVJTARTJIT, TXM-START_BIT).
RCVJUF and TXM_BUF simulate the on-chip serial port SBUF as two separate buffer registers. The
temporary registers, RCV_REG and TXM_REG,
are used to save bits as they are received or transmitted.
Finally, two counter registers keep track of how many
bits have been received or transmitted.
Variables are also needed to define one-half and one-'
full bit times in units of PCA timer ticks. (One bit time
= I / baud rate.) With the PCA timer incremented
every machine cycle, the equation to calculate one bit
time can be written as:
(
Osc. Freq. ) = 1 billime (in PCA
,
12) X (baud r a l e '
li~er licks)
In this example, the baud rate is 2400 at 16 MHz.
16MHz
(12) X (2400)
= 556 counls = 22C Hex
The high and low byte of this value is placed in the variables FULL_BIT_HIGH and FULL_BIT_LOW,
respectively. 115H is the value loaded into
HALFJIT~IGH and HALFJIT_LOW.
(I) List of variables
(2) Initialization routine
STOP
.1
2-222
270531-1
inter
AB-41
Listing 1. Variables used by the software serial port. Channel 0
,
Receive Routine
RCV_START_BIT_O
BIT
RCV_DONE_O
BIT
20H.1
DATA
30H
DATA
31H
DATA
32H
RCV BUF
RCV REG
°
°
20H.O
Indicates start bit
has been received
Indicates data byte
has been received
Software Receive
nSBUF"
Temporary register
for receive bits
Counter for receiving
bits
Transmit Routine:
TXM_START_BIT_O
BIT
TXM IN PROGRESS_O BIT
°
20H.3
20H.4
DATA
34H
TXM_REG_O
DATA
35H
TXM COUNT_O
DATA
36H
DATA 0
DATA
37H
NEG EDGE
S W-TIMER
EOU
EOU
49H
HALF BIT HIGH
HALF-BIT-LOW
FULL-BIT-HIGH
FULL-BIT-LOW
EOU
EOU
EOU
EOU
01H
I5H
02H
2CH
TXM BUF
llH
Indicates start bit
has been transmitted
Indicates transmit is
in progress
Software transmit
"SBUF"
Temporary register
for transmitting bits
Counter for transmitting bits
Register used for the
test program
Two modes of operation
for compare/capture
modules
Half bit time
115H
Full bit time
22CH
2400 Baud at 16 MHz
270531-4
2-223
infef
AB-41
InitiaJization
Listing 2 contains the intialization code for the receive and transmit process. Module 0 of the PCA is used as a
receiver and is first &et up to detect a negative edge from the start bit. Modules 2 and 3 are used for the additional 2
channels (see the Appendix). Module 3 is used as a separate software timer to transmit bits.
Listing 2. Initialization Routine
ORG OOOOH
LJMP INITIALIZE
ORG OOlBH
LJMP RECEIVE_DONE
ORG 0033H
LJMP RECEIVE
,
INITIALIZE: MOV SP, #5FH
INIT_PCA: MOV CMOD, #OOH
MOV CCON, #OOH
MOV CCAPMO, #NEG~EDGE
MOV CCAPM3, #S_W_TlMER
MOV CL, #OOH
MOV CH, #OOH
MOV IE, #OD8H
SETB CR
Timer 1 overflow simulates "RI" interrupt
PCA interrupt
Initialize stack pointer
(specific to test program)
Increment PCA timer
@ 1/12 Osc Frequency
Clear all status flags
Module 0 in negative-edge
trigger mode (Pl.3)
Module 3 as software timer
mode
Init all needed interrupts
EA, EC, ES, ET1
Turn on PCA Counter
270531-5
All flags and registers from Listing 1 should be' cleared in the initialization process.
Receive Routine
Two operating modes of the PCA are needed to receive bits. The module must first be able to detect the leading edge
of a start bit so it is initially set up to capture a I-to-O transition (i.e. Negative-Edge Capture mode). The module is
then reconfigured as a software tiiner to cause an interrupt at the center of each bit to deserialize the incoming data.
The flowchart for the receive routine is given in Figure 1.
2-224
AB-41
NO
YES
Add 1 bit
Add 1 bit
time to
compare/capture
registers
time to
compare/capture
registers
NO
Reconfigure PC4
module to
capture 1 - 0
transitions
Reconfigure PCA
module to
capture 1 - 0
transitions
270531-2
Figure 1. Flowchart for the Receive Routine
2-225
intJ
AB-41
Listing 3.1 shows the code needed to detect a start bit. Notice that the first software timer interrupt will occur onehalf bit time after the leading edge of the start bit to check its validity. If it is valid. the RCV_START_BIT is set.
The rest of the samples will occur a full bit time later. The RCV_COUNT register is loaded with a value of 9 which
indicates the number of bits to be sampled: 8 data bits and 1 stop bit.
Listing 3.1. Receive Interrupt Routine
RECEIVE:
,
PUSH ACC
PUSH PSW
MODULE_O: CLR CCFO
Assume reception on
Module 0
MOV A, CCAPMO
Check mode of module. If
ANL A, #OlllllllB
; set up to receive negative
CJNE A,#NEG_EDGE, RCV START
edges, then module
- ; is-waiting for a start bit
°;
CLR C
MOV A, #HALF BIT LOW
ADD A, CCAPOL
MOV CCAPOL, A
MOV A, #HALF BIT HIGH
ADDC A, CCAPOH MOV CCAPOH, A
MOV CCAPMO, #S W TIMER
POP PSW
- POP ACC
RETI
Update compare/capture
registers for half bit time
to sample start bit
Half bit time = l15H
°
Reconfigure module
as
a software timer to sample
bits
°;
°;
RCV START_O: CJNE A, 'is' W TIMER, ERROR
Check module is
-T ; configured as a sO,ftware
; timer, otherwise error.
JB RCV_START_BIT_O, RCV BYTE
Check if start bit
T is received yet.
JB P1.3, ERROR_O
Check that start bit = 0,
otherwise error.
SETB RCV_START_BIT_O
Signify valid start bit
was received
MOV RCV_COUNT_O, #09H
Start counting bits sampled
CLR C
MOV A, #FULL BIT LOW
ADD A, CCAPOL
MOV CCAPOL, A
MOV A, #FULL BIT HIGH
ADDC A, CCAPOH MOV CCAPOH, A
POP PSW
POP ACC
RETI
Update compare/capture
registers to sample
incoming bits
Full bit time = 22CH
270531-6
2-226
intJ
AB-41
The next 8 timer interrupts will receive the incoming data bits; the RCV_COUNT register keeps track of how many
bits have been sampled. As each bit is sampled, it is shifted through the Carry Flag and saved in RCV _REG. The
ninth sample checks the validity of the stop bit. If it is valid, the data byte is moved into RCV _BUF.
The main routine must have a'way to know that a byte has been received. With the on-chip UART, the RI (Receive
Interrupt) bit is set whenever a byte has been received. For the software serial port, any unimplemented interrupt
vector can be used to generate an interrupt when a byte has been 'received. This routine uses the Timer I Overflow
interrupt (its selection is arbitrary). A routine to test this interrupt is included in the listing in the Appendix.
Listing 3.2. Receive Interrupt Routine (Continued)
RCV BYTE 0: DJNZ RCV COUNT 0, RCV DATA a ; On 9th sample,
; check for valid stop bit
RCV STOP 0: JNB Pl.3, ERROR a
MOV RCV_BUF_O, RCV_REG_O ; Save received byte in
receive "5BUF"
SETB RCV DONE a
Flag which module received
a byte
Generate an interrupt so
SETB TFl
main program knows a byte
has been received
(Note: selection of TFl is
arbitrary)
MOV CCAPMO, #NEG_EDGE
Reconfigure module a for
Reception of a start bit
POP PSW
POP ACC
RETI
RCV DATA 0: MOV C, Pl.3
MOV A, RCV REG 0
RRC A
--
MOV RCV_REG_O, A
CLR C
MOV A, #FULL BIT LOW
ADD A, CCAPOL
MOV CCAPOL, A
MOV A, #FULL BIT HIGH
ADDC A, CCAPOH MOV CCAPOH, A
POP PSW
POP ACC
RETI
Sampling data bits
Shifts bits thru CY into
ACC
Save each reception in
temporary register
Update c/c register for
next sample time
270531-7
In addition, an error routine (Listing 3.3) is included for invalid start or stop bits to offer some protection against
noise. If an error occurs, the module is re-initialized to look for another start bit.
Listing 3.3 Error Routine for Receive Routine
ERROR 0:
MOV CCAPMO, #NEG_EDGE
CLR
RCV_START_B~T_O
Reset module to look for
start bit
Clear flags which might
have been set
POP PSW
POP ACC
RETI
270531-8
2:227
inter
AB-41
Transmit Routine
Another peA module is configured as a software timer to interrupt the CPU every bit' time. With each timer
interrupt one or more bits can be transmitted through port pins. In the test program three channels were operated
simultaneously, but in the· listings below, one channel is shown for simplicity. The selection of port pins is user
programmable. The flowchart for the transmit routine is given in Figure 2.
Figure 2. Flowchart for the Transmit Routine
When a byte is ready to be transmitted, the main program moves the" data byte into the TXM_BUF register and sets
the corresponding TX~IN_PROGRESS bit. This bit informs the interrupt routine which channel is transmitting. The data byte is then moved in the storage register TX~EG, and the TX~COUNT is loaded. This main
routine is shown in Listing 4.1.
Listing 4.1 Transmit Set Up Routine. Channel O.
TXM_ON_O: CLR TXM_START_BIT_O
Clear status flag from
previous transmission
MOV TXM BUF 0, DATA 0
Load "SBUF" with data byte
MOV TXM-REG-O, TXM BUF 0
MOV TXM-COUNT 0, #09 8 data bits + 1 stop bit
~ETB TXM_IN_PROGRESS_O
270531-9
2-228
inter
AB-41
Listing 4.2 shows the transmit interrupt routine. The first time through, the start bit is transmitted. As each
successive interrupt outputs a bit, the contents of TXM_REG is shifted right one place into the Carry flag, and the
TXM_COUNT is decremented. When TXM_COUNT equals zero, the stop bit is transmitted.
Listing 4.2. Transmit Interrupt Routine
TRANSMIT: PUSH ACC
PUSH PSW
CLR CCF3
; Clear s/w timer interrupt
; for transmitting bits
TRANSMIT 1 ; Check which
; channel is transmitting.
; "TRANSMIT 1" is listed in
; the Appendix
,
°;
TRANSMIT_O: JB TXM_START_BIT_O, TXM BYTE
If start bit
has been sent, continue
transmitting bits.
CLR P3.2
Otherwise transmit start
bit
SETB TXM START BIT
Signify start bit sent
JMP TXM EXIT
°
°;
TXM BYTE 0: DJNZ TXM COUNT_O, TXM DATA
If bit count
equals 1 thru 9, transmit
data bits (8 total)
TXM STOP_O: SETB P3.2
CLR TXM IN PROGRESS
,
TXM DATA 0: MOV A, TXM REG
-
RRC A
-
°
°
MOV P3.2, C
MOV TXM_REG_O, A
TXM_EXIT: CLR C
MOV A, *FULL_BIT_LOW
ADD A, CCAP3L
MOV CCAP3L, A
MOV A, *FULL BIT HIGH
ADDC A, CCAP3H MOV CCAP3H, A
POP PSW
POP ACC
RET I
When bit count = 0,
transmit stop bit
Indicate transmission is
finished and ready for
next byte
Transmit one bit at a time
through the carry bit
Save what's not been sent
Update compare value with
Full bit time = 22CH
270531-10
Conclusion
The software routines in the Appendix can be altered to vary the baud rate and number of channels to fit a particular
application. The number of channels which can be implemented is limited by the CPU time required to service the
PCA interrupt. At higher baud rates, fewer channels can be run.
The test program verifies the simultaneous operation of three half-duplex channels at 2400 Baud and the on-chip
full-duplex channel at 9600 Baud. Thirty-three percent of the CPU time is required to operate all four channels. The
test was run for several hours with no apparent malfunctions.
2-229
MCS-51 !!ACRO ASSEMBLER
SWPORT
01101/80
(
PAGE
DOS 3.20 (038-N) IICS-51 MACRO ASSEMBLER, V2.2
OBJECT MODULE PLACED IN SWPORT. OBJ
ASSEMBLER INVOKED BY: C: \AEDIT\ASM51. EXE SliPORT. RCV
LOC
OBJ
LINE
I
2
0000
0000 020036
~
- 001B
001B 02025C
~
0023
0023 020282
N
0033
0033 D200DC
3
152
153
154
155
156
151
158
159
160
161
162
163
164
165
166
161
168
169
110
111
112
113
114
115
116
171
118
179
SOURCE
$NOMaDSI
SNOSYMBOLS
$NOLIST
~;:eP~~~i~~u~!:;S c~~~n;r;e!~: I~~t!~~t~a tn S~~i~:~~e s~~i~~n p~~t.
~~036g~ugaJ~~HlIihirt~~~h~~;c~~~c~~~i~! m\~~ ~t: f~n~!~i;~~lt~U~~~X
all four ports simultaneously.
To test the receive routines, Wdummy· terminals transmit 00 - FF hex
continually to the PCA. When the hrst byte is received, it is
~~~:~~t:at~nSOihe Iio;~rn~O:~f~!S~g ;:c:f;!dfh;h~ei~';~:. vai~~o~s
;
3
~~Urln:~ i~~~ird v:£~~~sbi~r~r sf~~Sbt~ r~ ~~~:f!:d~omparison
CRG OOIBR
LJIIP RECEIVE_DONE
Timer 1 Overflow - simulates 'RI' interrupt
~
"'0
"'0
bRG 00238
LJMP SERIAL_PORT
Serial port interrupt
Z
bRG 0033H
LJMP RECEIVE
PCA interrupt
180
0000
0008
0010
0001
0009
0011
0002
OOOA
0012
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
Occurs
CRG DOH
LJIIP INITIALIZE
m
-><
C
VARIABLES USED BY THE SOFTIIARE SERIAL PORT
;
RECEIVE ROUTINE:
---------------
kcv START BIT 0
RCV-STARTllIrl
~CV::STARryIor:2
RCV
DONE 0
RCV-DON~1
Rev-DONE-2
kcv-oN- 0Rev-Olrl
RCV::0~2
BIT
BIT
BIT
20B.0
21B.O
22H.0
received
BIT
BIT
BIT
20B.l
21H.l
22B.l
Indicates data byte has been
received
-BIT
20B.2
218.2
229.2
Used in IM.in test program to check
for a received byte
BIT
BIT
Indicates start bit has been
270531-11
):0
q:J
....
.0.
_.
MeS-51 HACRO ASSEIIBLER
LOC
OBJ
0030
0040
0050
0031
0041
0051
0032
0042
0052
gg:~
0053
0011
0049
0015
0001
002C
0002
Rev BUF 0
Rcv-aurl
RCV"l!Or2
• Rev REG 0
RCV""REC>1
RCIr1!EC>2
• RCV COUNT 0
RCV-COUNrl
RCV-COUNr2
; -
213
COUNr2
m
214
215
0036 75815F
0039
003C
003F
0042
0045
75D900
75D800
75DAlI
75DBlI
75DClI
0048 75E900
004B 75F900
D8
gg~f
m:
0053
0056
0059
005C
759850
75CBFF
75CACC
75CB34
OOSF C200
0061 C208
0063 C210
0065 C201
ggg~~
•
DATA
DATA
DATA
3 0 R ; Software receive 'SBUF'
40B
SOH
DATA
DATA
DATA
4 1 f t ; receiving bits
DATA
DATA
DATA
3 2 B ; Counter for receiving bits
42H
52R
51R
DATA
53B
m
g;~~s i~e~~~t r~~~~:~
g~i~
-
to check
~_QIHER
NEG EDGE
EOO
EgO
liB
49B
Two modes of operation for the
ComparelCapture modules
218
219
220
221
222
223
224
225
HALF BIT LOll
BALFI!ITIIIGR
FULLIIIT. .OW
FOLL'IITIIIGB
-
EOO
EOU
EgU
EOU
ISH
01R2CB
02B
Full bit time
m
242
243
244
245
246
247
248
249
250
251
252
253
CR..
3 1 B ; Temporary register for
~l~
228
229
230
231
232
233
234
235
236
237
238
239
I Ia
PAGE
SOURCE
199
200
201
202
203
204
205
206
207
20B
209
210
~~~
I\J
N
~
01/01/80
SIiPORT
LINE
:
•
HOV SP, 15FB
INIT PCA:
-
MOV
I!OV
HOV
HOV
HOV
I
;
INIT FLAGS:
-
= 22CB
2400 Baud @ 16MBz
II>
INITIALIZATION ROUNTINE
======================a
~
INITIALIZE:
INIT SP:
-
Balf bit time = 1I5B
eKOD, 100H
CCON, 100B
CCAPMO, lNEG EDGE
CCAPM1, INEC>EDGE
CCAPM2, INEC>EDGE
MOV CL, ,OOH
HOV CH, 100H
~g~BI~R IOD8B
HOV
HOV
MOV
HOV
SCON. ,50H
RWlH, 10FFH
RCAP2L, 10CCR
T2CON, 134H
IJI
I
~
I Initialize stack pointer
;
;
;
;
;
;
;
(specific to the test program)
Increment PCA clock @ 1/12 Osc Freq
Clear all status flags
Module 0 in Neg-edge capture mode (PI. 31
Module l '
IPl.4
Module 2 '
PI. 5
~~;i~~i~b.n~~~~~e~nterruPt: EA,EC,ES,ETI
Serial port in mode 1 (8-Bit UART)
Reload values for 9600 Baud @ 16 MHz
Timer 2 as a baud-rate generator,
turn on timer 2
CLR Rev START BIT 0
CLR RCV-STARTIIIT-l
eLR RCV-ST'>.RrBIr2
-CLR RCV_DONE_O
270531-12
IICS-51 MACRO ASSEllBLER
LOC
OBJ
0067 C209
0069 C211
0068 C202
006D C20A
006F C212
LINE
254
255
256
257
258
259260
261
0071 D2B2
0073 02B3
0075 D2B4
0077 02B5
0079 0286
007B D2B7
0070 753000
0080 754000
0083 755000
0086 753200
0089 754200
008C 755200
I):>
I\)
w
I\)
OOaF 753100
0092 754100
0095 755100
0098 753300
0098 154300
009E 755300
262
263
_ 264
265
266
267
268
269
01/01/80
SHPI)RT
SI)VRCE
CLR -RCV DONE 1
CLR RCV::DONE:2
CLR-RCV ON 0
CLR RCv-ON"'l
CLR RCV::O~2
Port 3 pins used in test program for error routines
llain proqram:
SETB P3.2
SETB Pl.3
Interrupt Iout~~i~: P3. 5
2Tl
MOV RCV BUF 0, ,OOH
MOV RC"VBVrl, 'DOH
MOV Rcv:aUr:2, tOOH
1I0V RCV COUNT 0, lOOH
MOV RC1rCOUNrI, 100H
MOV RCV:C0VNr:2, 'DOH
281
HOV RCV BEG 0, 'DOH
MOV lICV"llEG""l, 'DOH
MOV Rcv:HE~2, 'DOH
282
283
284
285
286
287
288
289
OOAD
00110
00B2
00B5
0087
300A09
&540
B54319
C20A
0543
00B9 3012E5
OOBC E550
008E B55314
MAIN nSf ROUTINE - BECEIVE BITS
CHEC!(_O:
~ ~CVRg}g6rC~ECK_1
t
CLR RCV
CJNE
COUNr 17, ERRORO
ON 0 INC COUNT_V
298
30S
306
307
308
..
HOV COVNrl, t008
MOV COUNr:2, tOOH
290
299
300
301
302
303
304
J>
m
;..
IIOV COUNT 0, 'DOH
291
300209
E530
B5331E
C202
OOAB 05H
Error in reception on module 0
Error in reception on module 1
Error in reception on module 2
SErB P3.6
SETS P3.7
274
275
216
277
278
279280
00A1
OOM
00A6
DOA9
Error in comparison on module 0
; Error in comparison on module 1
i
; Error in comparison on module 2
SETB P3.4
270
271
272
292
293
294
295
296
297
l
PAGE
~HECK_I:
Main proqram continually checks
each channel for a recelved byte.
e~~~ ~h~Y~~r~:n~·;:1~:dtn i~h~s .ggWr;ed
register
~ ~~R~CfEc!(_2
CJNE A, COUNT !, ERROR1
CLR RCV ON 1 INC COUIIT_!
b!ECK_2:
JNB RCV ON 2, CHEc!( If
IIOV A, RCV-BVF 2
CJNE A, COUNT_'2, ERROR2
270531-13
IICS-51 IlACRO ASSEIIBLER
LOC
OBJ
OOCI C212
00C3 0553
DOCS 800A
00C7 C2B2'
00C9 750AOO
OOCC 800f
OOCE C2B3
DODO 750BOO
0003 80E4
0005 C2B4
0007 750COO
OODA 80C5
OODC COED
OODE CODO
I\)
~
(.,)
(.,)
OOEO
00E3
00E6
00E9
OOEB
OOEO
200811
200908
200AOB
DODO
ODED
32
OOEE 02016C
OOFI 020lE4
00F4
00F6
00F8
OOFA
C208
E50A
547F
B41115
OOFO
OOFE
0100
0102
0104
0106
0108
010A
C3
7415
25EA
FsEA
7401
35fA
F5FA
75DA49
0100 DODO
OlaF DOEO
LINE
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
33B
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
SHPORT
01/01/80
l
PAGE
SOURCE
CLR" RCV ON 2
INC COUIIT Z
JIIP CHECK:O
~RRORO:
ERRORI :
~RROR2:
CLR P3.2
~~ g~~~~~1
lOOH
Error in comparison on module
Discontinue receiving bytes
CLR P3.3
MOV CCAPMl L 10 OH
JIIP CHECK_l
Error in comparison on module 1
CLR P3.4
Error in comparison on module 2
~ g~~~~~6 100H
PCA INTERRUPT ROUNTINE - RECEIVE BITS
,i
hCEIVE:
PUSH ACC
PUSH PSH
JB CCFO, MODULE a
JB CCFl, JUMP 1JB CCF2, JUIIP-2
POP PSII
POP ACC
RETI
~UHP 1:
JUIIP-2:
-
»
til
I
....
0l:Io
LJIIP MODULE 1
LJIIP MODULE:2
CHANNEL 0
;
hOOULE_O:
Check which module caused
PCA interrupt and jump to
appropriate routine
CLR CCFO
MOV A, CCAPMO
ANL A, 101111111B
CJNE A, INEG_EDGE, RCV_START _ 0
Reception on module a
Check mode of module. If set up to
receive negative edges, then module
is waiting for a start bit
CLR C
MOV A, 'HALF BIT LON
Update Compare/Capture registers for
half a bit time
to sam~le start bit
Half blt time' 115H
~g~ ~bJ~t~O~
-
~Xch., '~~~uaIT_HIGH
MOV CCAPOH, A
MOV CCAPMO, IS_H_TIMER
POP PSI!
POP ACC
Reconfigure module 0 as
a software timer to sample bits
270531-14
--
MCS-51 MACRO ASSEMBLER
LOC
OBJ
0111 32
0112 B44948
0115 20001A
0118 209345
OllB 0200
0110 153209
0120
0121
0123
0125
0127
0129
0128
0120
012F
0131
C3
742C
25EA
F5EA
1402
35FA
F5FA
0000
OOEO
32
0132 053212
~
(,J
./>.
0135
0138
013B
0130
309328
853130
0201
D28F
013F
0142
0144
0146
150All
DODO
OOEO
32
0147
0149
014B
014C
A293
E531
13
F531
014E
014F
0151
0153
0155
0157
0159
0158
015D
015r
C3
142C
25EA
F5EA
7402
35FA
F5FA
DODO
DOEO
32
0160 C2B5
LINE
364
365
366
367
368
369
370
371
372
313
374
315
316
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
401
408
409
410
411
412
413
414
415
416
417
01101/80
SWPORT
PAGE
II
SOURCE
RETI
kcv-START- 0,
CJNE A, 'S_Ii_ TIKER, ERROR_0
JB RCV_START_BIT_O, RCV_BYTE_O
JB Pl.3, ERROR_O
SETB RCV_START_BIT_O
MOV RCV_COUNT_O, '09B
cf
Check module is configured
as a software timer, otherwise errOl.
Check if start bit
has been Ieee i ved yet
Check that start blt • 0,
otherwise. error.
Signify valid start bit
was Ieee! ved
Start counting bits sampled
Update C/C registers to sample
CLR C
HOV A, 'FULL BIT LOW
~g~ ~~~ijEO~ -
i~~~m~~~ ~t~
. 22CH
~g~cAA '~gk¥l1~IT_HIGH
MOV CCAPOH, A
POP PSI!
POP ACC
RETI
~CV BUE 0,
- - -
RCV STOP 0,
DJNZ RCV_COUJIT_O, RCV_DATA 0
~~ ~~3BU~R~?RR~
SETB RCV OOIlE_O
SETB TFl-
-
REG
-
HOV CCAPMO, 'NEG EDGE
POP PSI!
POP ACC
RETI
kcv-DATA-0,
MOV C, Pl.3
~g~, RCV_REG_O
HOV RCV_REG_O, A
CLR C
HOV A, 'FULL BIT LOll
MOV A, 'FuLL BIT HIGH
ADDC A, CCAP1JB HOV CCAPOH, A
POP PSW
POP ACe
RETI
~~ ~~A~~PO~
hROR 0,
-
CLR P3.5
°
On 9th sample, check for
valid stop bit
~r~; ;g~~~ v:.gd~r;e r!ge~~;ai ~eb;~:UF'
;s..
Generate an interrupt so main program
~~g;~, a s~r~~t~g~ ~rMer:i~~gitrary)
Reconfigure module 0 for next
reception of a start bit
~~Twg~t~a~~r~~~~
a:I
I
I I ...""
CY into ACC
Save each reception in temporary
register
Update C/C register for next
sample time
Error routine for invalid start or
stop bit or invalid mode comparison
270531-15
_.
IICS-51 KACRO ASSEMBLER
LOC
LI~E
OBJ
gm tm
l1
016C C2D9
016E E50B
8m ~m15
0115 C3
0116 1415
8m ~~g
8m i~?a
Ol1C 1401
0182 150849
0185 0000
0181 ODED
ro
ffl
I\)
0189
018A
0180
0190
32
84494B
20081A
209445
0193 0208
m
421
422
423
424
425
426
421
428
429
430
m
CR..
~~ ~g¢P~~AA~N~YTEgGE
POP PSWPOP ACC
RETI
~~~ll, '~iW~,
-
RCV START 1
--
aJiflf ~~c~r~~AH NOV CCAPMl, IS II TIMER
~~
438
MOV A, 'HALF BIT HIGH
441
442
443
PDP PSI!
POP ACC
m,
Rev START 1:
-
- -
0195 154209
1~~
0198 e3
0199 142C
019B 25EB
453
454
455
eLR C
MOV A, 'FULL BIT LOll
ADD A, CCAPlI;
-
01A5 DODO
01A1 ODED
01A9 32
DIM D542l2
01AD
OlBO
01B3
01B5
01B1
01BA
01 BC
309428
854140
0209
D28F
75DB11
DODO
DDEO
m
m
460
461
462
463
lt~
466
461
468
469
410
471
472
I I ..
RETI
CJNE A, 'S II TlKER, ERROR 1
JB Rev STARTI!IT I, RCV BYTE 1
JB Pl."" ERROR_lSETB Rev START BIT 1
HOV Rev_COUNT_I, '119H
m~ m~
m:~ m~!ev~~C~o~g~~'b:;:rge~~\et
Similar to module 0
CLR CCFl
IIOV A, CCAPKI
450
8m m=
;
--
CLR C
HOV A, 'HALF BIT LOll
m
m
m
; Port pin used for debug only
CHANNEL 1
,
KODULE I:
-
433
434
435
446
441
IIa
PAGE
SOURCE
418
0161 DODO.
0169 00&0
016B 32
01lf1/80
SKPORT
:::;
...
~
....
::g~ ~?1~5LLABIT HIGH
~~cc~Apr~~AH -
,
POP PSII
POP ACC
RETI
~CV_BYTE_l:
OJNZ Rev_COUNT_l, RCV_OATA_1
Rev STOP 1:
-
JNB Pl.4, ERROR 1
HOV RCV BUF 1, Rev REG 1
SETB Rev DONE 1
SETB TFlHOV CCAPKl, 'NEG EDGE
POP PSW
POP ACC
270531-16
HCS-51 MACRO ASSEMBLER
LOC
OBJ
OIBE 32
O}BF
01Cl
01C3
01C4
A294
E541
13 .
F54l
01C6
01C1
0lC9
OICB
OICD
OlCF
0101
0103
0105
0101
C3
742C
25EB
F5EB
7402
35FB
F5FB
DODO
DOEO
32
0108
OloA
0100
01DF
OIEI
0lE3
C2B6
75DBll
C20B
DODO
OOEO
32
I\J
N
Co)
m
0lE4
0lE6
0lE8
OlEA
C20A
ESDC
541F
B41115
OlEO
OIEE
OIFO
0lF2
0lF4
0lF6
0lr8
01FA
01FD
01FF
0201
C3
1415
25EC
FSEC
1401
35FC
F5rc
15OC49
DODO
oOEO
32
0202 84494B
0205 2010lA
0208 209545
020B 0210
0200 755209
LINE
413
474
415
416
471
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
491
498
499
500
SOl
502
503
504
505
506
501
508
509
510
511
512
513
514
SIS
516
517
518
519
520
521
522
523
524
525
526
521
01/01/80
SIIPORT
(
PAGE
SOURCE
RETI
Rev DATA I,
- -
MOV C, Pl.4
~~ ~, RCV_REG_I
HOV RCV_REG_I, A
CLR C
MOV A, 'FULL BIT LON
~g~ ~I:A~It:I~
-
MOV A, 'FULL BIT HIGH
AoOC A, CCAPTH MOV CCAPIH, A
POP PSII
POP ACC
RETI
ERROR I,
CLR Pl.6
MOV CCAPHI, tNEG EDGE
CLR RCV START BIT 1
POP PSII'"
-POP ACC
RETI
-
»
q:J
....
""
CHANNEL 2
~OOULE- 2,
CLR ccr2
MOV A, CCAPMl
ANL A, ,01111111B
CJNE A, 'NEG_EoGE, RCV_START_2
.
Similar to module 0
CLR C
HOV A, 'HALF BIT LOll
~g3 ~CA~~2~ MOV A, 'OALF BIT HIGH
ACoC A, CCAPZ8 MOV CCAP2H, A
~g~ ~~QPM2, IS_II_TIllER
POP ACC
RETI
-
Rev START 2,
-
CJNE A, IS II TIllER, ERROR 2
~~ ~r~s~T~~~~~~_2, RCV_BYTE_2
SETB RCV START BIT 2HOV RCV_COUNT _Z, '11'90
270531-17
MCS-51 MACRO ASSEMBLER
LOC
OBJ
LINE
0210
0211
0213
0215
0217
0219
021B
0210
021F
0221
C3
742C
25EC
F5EC
740t
35FC
F5FC
DODO
OOEO
32
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
. 548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
561
568
569
510
51\
0222 055212
I\J
~
-..J
0225
0228
022B
0220
022F
0232
0234
0236
309528
855150
0211
028F
75DC11
DODO
OOEO
0237
0239
023B
023C
023E
023F
0241
0243
0245
0247
0249
024B
0240
024F
A295
E551
13
F551
C3
742C
25EC
F5EC
7402
35FC
F5FC
DODO
ODED
32
0250
0252
0255
0257
0259
025B
C2B7
750C11
C210
DODD
OOEO
32
32
01/01/80
SIiPORT
l
PAGE
SOURCE
CLR C
MOV A, 'FULL BIT LOll
~g~ ~1:A~~tt'2~
-
MOV AI. 'FuLL BIT HIGH
~g~cCCJ.p~~~~H POP PSH
POP ACC
RETI
kcv BYTE
2:
kCV=STOP=2:
OJNZ RCV_COUNT_2, RCV_OATA_2
JNB P1.5, ERROR 2
~~~l~~BgbR~' lCV_REG_2
SETB TFr
HOV CCAPM2, 'NEG EDGE
POP PSH
POP ACC
RETI
RCV_DATA_2:
HOV
HOV
RRC
~~
HOV
ADD
C, Pl.5
A, RCV REG 2
A
-~CV_REG_2, A
A, 'FULL BIT LOil
A, CCAP 2'[; -
=g~ i;Aj~~tL\IT
AODC A, CCAP2H MOV CCAP 2H, A
POP PSH
POP Ace
RETI
ERaOR_2:
»
m
....•
HIGH
~
CLR P3.1
MOV CCAPM2, 'NEG EDGE
CLR RCV START BIT 2
POP PSlf'"
-POP ACC
RETI
512
513
514
575
When a byte is received on one
ate set so the main
, ~~un~eC~~~~:l:~i~ti~h~~~:i[~~~el:eae~e~~~:~. Bits
;
,
580
581
582
kECEIVE_DONE:
519
025C CO EO
025E CO DO
0260 C28F
; This routine simulates the ·RI- interrupt.
576
511
518
PUSH ACe
PUSH PSli
CLR TFI
270531-18
HCS-51 HACRO ASSEMBLER
LOC
OBJ
0262 300106
0265 C201
0267 C200
0269 0202.
026B
026E
0270
0272
300906
C209
C208
020A
0274
0271
- 0279
027B
301106
C211
C2l0
0212
0270 0000
027F OOEO
0281 32
LINE
583
584
585
586
587
588
589
590
SWPORT
JNB RCV DONE 0, RCV 1
CLR RCV-OONE-O
CLR RCV-STAR! BIT 0
SETB RCV_ON_ORCV_l:
JNB RCV DOllE I, RCV 2
CLR RCV-DONE-l
CLR RCV-START BIT 1
SETB RCV_ON_l-
RCV_2:
JNB RCV DONE 2, RETURN
CLR Rev-DONE-2
.
CLR Rev-START BIT 2
SETB RCV_ON_,
-
hTUHN:
POP PSi!
POP Ace
RET!
591
592
593
594
595
596
591
598
599
01/01/80
(
PAGE
SOURCE
600
601
Check which module Ieceived a byte
Clear flags needed for next reception
Tell main routine which channel received
a byte
602
603
604
605
606
607
608
609
610
N
~
CO
0282
0284
0286
0289
028B
0280
028F
0291
0293
COED
COOO
30980B
E599
C298
F599
DODD
ODED
32
0294
0296
0298
029A
C299
DODO
ODED
32
611
612
613
614
615
616
617
618
619
620
621
'622
623
624
SERIAL PORT IN'rERRUPT
j
When a byte is received on the full-duplex serial Jort, it is then
;; £~~~STt t~~~n~~~~t~~ ~o '~~:"'~~AtI~~g:l.a~h~!I~~\ t n~~c~~~~~\~~~~
SERIAL]ORT:
~~X ~I SBUF
628
.
~
m
....""
Check whetbeI RI OI TI
caused the interrupt
MOV SBUF, A
POP PSII
POP ACC
RETI
fXM:
625
626
627
POSH ACe
PUSH PSli
JNB RI, TXH
the
CLR TI
POP PSW
POP ACC
RETI
fND
REGISTER BANK (5) USED: 0
ASSEMBLY CO/olPLETE, NO ERRORS FOUND
270531-19
MeS-51 MACRO ASSEMBLER
SWPORT
01/01/80
cl
PAGE
DOS 3.20 (038-N) MeS-51 MACRO ASSEMBLER, V2.2
OBJECT MODULE PLACED IN SWPORT.OBJ
ASSEMBLER INVOKED BY: C: IAEDITIASM51.EXE SWPORT. TR
LOC
OBJ
LINE
1
2
0000
0000 020036
f\)
N
w
<0
0023
0023 02014B
0033
0033 0200DO
0003
OOOB
0013
0004
00 DC
0014
0034
0044
0054
0035
0045
0055
0036
0046
0056
0037
0041
3
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
IB4
185
186
187
IBB
189
190
191
192
193
194
195
196
197
198
SOURCE
I
NOMOD51
NOSYMBOLS
NOLIST
This ll[ogram tests the transmit routines for the software serial port.
To inItialize the first transmission, the compare values are loaded before
the peA timer is started. Successive interrupts are generated every bit
time by the software timer.
,
For test purposes, the data transmitted increments from 00 to FF hex.
-Dummy· termInals receive these bytes and display the bytes as they
are incremented.
6RG DOH
LJHP INIT_TXM
6RG 0023H
LJHP SERIAL PORT
Serial port interrupt
6RG 0033H LJHP TRANSMIT
peA
.
»
....
m
~
software timer interrupt
VARIABLES USED BY THE SOFTWARE SERIAL PORT
fxH START BIT 0
BIT
BIT
BIT
20H.3
21H.3
22H.3
Indicates start bit has been
transmitted
BIT
BIT
BIT
20H.4
21H.4
22H.4
Indicates transmit is in progress
DATA
DATA
DATA
34H
44H
54H
Software transmit -SBUF-
DATA
DATA
DATA
35H
45H
55H
Temporary register for
transmitting bits
TXICREG:2
TxM COUNT 0
TXH-COUNT-l
TXM:COUNT::2
DATA
DATA
DATA
36H
46H
56H
Counter for transmitting bits
6ATA 0
DATA:l
DATA
DATA
37H
47H
Register used for the test
program
TX~START"Hrl
TXICSTART:BIT:2
TXM IN PROGRESS 0
TX~IN"'ROGRESS-l
TXICIDROGRESS:2
hH BUF 0
TX~BUrl
TXICBUC 2
fxH REG 0
TX~RE<>1
270531-20
HCS-51 MACRO ASSEHBLER
LOC
OBJ
0057
0049
002C
0002
0036 75815F
0039
003C
003F
0042
0045
150900
750800
75F900
15E900
750049
0048 15A8D8
I\J
N
0
"""
004B
004E
0051
0054
159850
15CBFF
15CACC
15C834
0051 C203
0059 C20B
005B C213
0050 C204
005F C20C
0061 C214
0063 153400
0066 154400
0069 155400
006C 153500
006F 154500
0012 755500
0015 153600
0078 754600
007B 755600
007& 7537FF
0081 7547FF
0084 7557FF
0087 75E02C
008A 75FD02
0080 020E
SWPORT
01/01/80
LINE
SOURCE
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
211
218
219
220
221
222
223
224
225
226
221
228
229
230
231
232
233
234
235
236
231
238
239
240
241
242
243
244
245
246
241
248
249
250
251
252
253
DATA 2
DATA
57H
~- W- TIMER
EQU
49H
FULL BIT LOW
FULL-BITI!IGH
EOU
EOU
2CH
02H
-
-
-
cl
PAGE
Software timer mode for the
~~Tla~r{C~l~C~ 22g~le
2400 Baud at 16 HHz
INITIALIZATION
{NIT TXH:
-
HOV SP, 15FH
(Compatible with receive routines)
HOV CHOD, lOOH
Increment PCA timer @ 1/12 osc. freq.
Clear all status flags
HOV CL, lOOH
HOV CCAPH3, IS_W_TlHER
Module 3 configured as software timer
Wo~ g~~N~O~~OH
IN IT SP:
-
HOV IE, lOD8H
Initialize all needed interrupts
~g~ ~m~H~5~gFFH
Serial port in mode 1 (a-bit UART)
Reload values for 9600 Baud @ 16 MHz
HOV RCAP2L, lOCCH
HOV T2CON, f34H
iNIT- FLAGS:
):00
Timer 2 as a baud-rate generator,
turn Timer 2 on
m
I
....
~
CLR TXM START BIT 0
CLR TXtrSTARTI!IT-1
CLR TXICSTART:BlT:2
CLR TXM IN PROGRESS 0
CLR TXtrIN-PROGRESS-1
CLR TXICIN~ROGRESS:2
MOV TXM BUF 0, lOOH
MOV TXtrBU,l, lOOH
HOV TXICBUr:2, lOOH
MOV TXM REG 0, lOOH
MOV TXtrREb"l._ lOOH
HOV TXICRE~2, lOOH
MOV TXH COUNT 0, lOOH
MOV TxtrCouNrl, lOOH
HOV TXH:COUNT:2, lOOH
HOV DATA 0, JOFFH
HOV DATA-I, JOFFH
HOV DATA:2, 10FFH
HOV CCAP3L, 12CH
HOV CCAP3H, 102H
SETB CR
Cause the first software timer to
interrupt one bit time after
peA timer is started
270531-21
(
MCS-51 HACRO ASSEMBLER
LOC
OBJ
008F 02009D
I\:)
'"
:::
0092
0095
0098
009B
300408
300C16
301424
80F5
009D
009F
OOAI
OOM
00A1
OOM
OOAC
C203
0531
853134
853435
153609
D204
80E4
OOAE
OOBa
00B2
00B5
00B8
OOBB
OOBD
C20B
0541
854744
854445
154609
D20C
80D3
OOBF
OOCI
00C3
00C6
00C9
OOCC
OOCE
C213
0551
855754
855455
155609
D214
80C2
0000
0002
0004
0006
COED
COOO
C20D
30041E
0009 200301
oooe e2B2
OODE 0203
ODED 0200n
LINE
254
255
256
251
258
259
260
261
262
263
264
265
266
261
268
269
210
211
212
273
274
275
276
277
278
279
280
281
282
283
284
285
286
281
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
301
308
SWPORT
01/01/80
PAGE
SOURCE
HAIN TEST ROUTINE - TRANSMIT BITS
;
fIRST_TXM:
~IN- TXM:
JHP T)'M_ON_O
JNB
JNB
JNB
JHP
TXM IN PROGRESS 0, TXM ON 0
TXtrINt>ROGRESS-l, TXtrO"l
TXtrINt>ROGRESS-2, TXtrON-2
HAIR_TIM
- -
Determine if ready to send
next byte. (Le. transmit
'not' in pro~ress)
Waiting for TI' flag
;
TIM ON 0:
- -
fxM_ON_l:
fXM_ON_2:
eLR TXM START BIT 0
INC OATlt 0 MOV TXM BUr 0, DATA 0
MOV TXtrREG""O, TXM Bur 0
HOV TxtreOURT 0, .U9H SETB TXII IN PROGRESS 0
JHP HAIICTXH
-
~~:~~mf!:ro~rom previous
Load 'SBur' with data byte
8 data bits + 1 stop bit
CLR
INC
MOV
MOV
TXM START BIT 1
DATA 1 TXM Bur I, DATA 1
TXtrREG""l, TXM BUr 1
~~BT~fRC~gw~R~GJ~~H 1JMP HAIN:TXH
-
CLR
INC
HOV
HOV
»
aJ
I
..."""
TXM START BIT 2
OATlt 2 TXM BUr 2, DATA 2
TXtrREG""2, TXM BUr 2
~BT~fRc~gwM/;J~~H2-
JMP HAIICTXII
-
PCA INTERRUPT ROUTINE - TRANSMIT BITS
fRANSMIT:
PUSH ACC
PUSH PSII
Clear s/v timer interrupt
CLR CCF3
JNB TXH_IN]ROGRESS_O,TRANSHIT 1 ; Check which channel is
transmitting
CHANNEL 0
TRANSMIT 0:
-
JB TXM_START_BIT_O, TXM_BYTE_O
CLR P3.2
SETB TXH START BIT 0
JHP TRANSMIT_J- -
If start bit has been sent,
continue transmitting data bits,
otherwise transmit start bit
Signify start bit sent
Check next transmit pin
270531-22
HCS-51 MACRO ASSEMBLER
LaC
OBJ
00E3 053601
00E6 02B2
00E8 C204
OOEA 0200F1
OOEO
OOEF
OOFO
00F2
00F4
00F1
OOFA
OOFD
DOFF
0101
E535
13
92B2
F535
0200n
300CI!
200B07
C2B3
D20B
020118
0104 054601
I\)
,
~
I\)
0107 D2B3
0109 C20C
010B 020118
010E
0110
0111
01U
Oll5
•
0118
011B
011E
0120
0122
E545
13
92B3
F545
020118
30141E
201301
C2B4
D213
020139
0125 D55607
0128 D2B4
012A C2l4
012C 020139
o12F
OIlI
0132
0114
0136
E555
13
92B4
F555
020139
SIIPORT
LINE
309
310
311
312
313
314
315
316
311
318
319
320
321
322
323
324
325
326
321
328
329
330
331
332
333
334
335
ill
331
338
339
340
341
342
343
01/01/80
l
PAGE
SOURCE
TXM B~TE 0:
-TXM STOP 0:
-i
TXM DATA 0:
-;
;
i
i
TRANSMIT 1:
-
OJNZ TXM_COUNT_O, TXM_DATA_O
SETB P3.2
CLR TXM_IN_PROGRESS_O
If bit count eguals I thru 9,
Transmit data tiits (8 total)
When bit count = D( transmit stop bit
Indicate transmisSlon is finishea and
JHP TRANSMIT_I
~~:~I !~~t n~~~n~~I~
HOV A, TXM REG 0
-RRCA
HOV P3.2, C
Transmit one bit at a time
through the carry !>it
~.J mll~¥T~i A
pin
Save what I s not been sent
Check next transmit pin
CHANNEL 1
JNB TXM IN PROGRESS 1, TRANSMIT 2 ; Similar to TRANSMIT_O
~l~-;~TART_BIT_l, -TXM_BYTE_I -
SETB TXM START BIT 1
JHP TRANSMIT_ai
TXM BYTE 1:
,TXM STOP 1:
-i
TXM DATA 1:
--
OJNZ TXM_COUNT_I, TXM_DATA_I
l>
OJ
SETB Pl.3
CLR TXM IN PROGRESS 1
JHP TRAlISMIT_ 2
-
....;..
HOV A, TXM REG 1
RRCA
-MOV P3.3, C
~ ~~M~¥T~~
A
CHANNEL 2
344
i
346
341
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
TRANSMIT 2:
-
M5;
,
TXM BYTE 2:
; TXM STOP 2:
-i
TXM DATA 2:
--
:::BTi~KSiMR~~~~~XHT~MXF
CLR P374
SETB TXM START BIT 2
JHP TXM_EXIT -
i Similar to TRANSMIT_O
--
DJNZ TXM_COUNT_2, TXM_DATA_2
SETB P3.4
CLR TXM IN PROGRESS 2
JHP TXJCEXIT
~~ ~, TXM_REG_2
HOV P3.4, C
HOV TXM REG 2, A
JHP TXICEXIT
270531-23
(
MCS-51 MACRO ASSEMBLER
*
LOC
OBJ
LINE
0139
013A
013C
OI3E
0140
0142
0144
0146
0148
OHA
C3
742C
25Eo
F5Eo
7402
35FD
F5Fo
DODO
ODED
32
364
365
366
367
368
369
370
014B
0140
OHF
0152
0154
0156
0158
015A
015C
COED
COOO
30980B
E599
C298
F599
DODO
ODED
32
0150
015F
0161
0163
C299
DODO
ODED
32
SWPORT
~OO
PAGE
SOURCE
TXH_EXIT:
CLR C
HOV A, 'FULL BIT LOW
~ge ~CA~~t;
3i -
Update coml'are value with
full bit tUIe = 22CH
HOV A, 'FULL BIT HIGH
AoDC A, CCAP3H HOV CCAP3H, A
POP PSW
POP ACC
RETI
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
01/01/80
,
SERIAL PORT INTERRUPT
; When a byte is received on the full-duplex serial port, it is then
; transmitted back to -a -dummy· terminal. This terminal checks that
the byte it transmitted to the PCA is the same value it receives back.
....
~
~
SERIAL PORT:
-
PUSH ACC
PUSH PSW
JNB RI, TXH
HOV A, SBUF
CLR RI
HOV SBUF, A
POP PSW
POP ACC
RETI
TXK:
CLR TI
POP PSW
POP ACC
RETI
,
OJ
"..
Check whether RI or TI
caused the interrupt
END
REGISTER BANK(S) USED: 0
ASSEMBLY COMPLETE, NO ERRORS FOUND
270531-24
inter
APPLICATION
NOTE
AP-415
July 1988
83C51FA/FB
PCA Cookbook
. . BETSY JONES
ECO APPLICATIONS ENGINEER
@ Intel Corporation, 1988
Order Number: 270609-001
2-244
inter
AP·415
This application note illustrates the different functions
of the Programmable Counter Array (PCA) which are
available on the 83C51FA and 83C51FB. Included are
cookbook samples of code in typical applications to
simplify the use of the PCA. Since all the examples are
written in assembly language, it is assumed the reader is
familiar with ASM51. For further information on these
products or ASM5l refer to the Embedded Controller
Handbook (Vol. I).
Each of the five modules can be programmed in any
one of the following modes:
- Rising and/or Falling Edge Capture
- Software Timer
- High Speed Output
- Watchdog Timer (Module 4 only)
- Pulse Width Modulator.
PCA OVERVIEW
All of these modes will be discussed later in detail.
However, let's first look at how to set up the PCA
timer and modules.
The major new feature on the 83C51FA and 83C51FB
is the Programmable Counter Array. The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages
include reduced software overhead and improVed accuracy.
The PCA consists of a dedicated timer/counter which
serves as the time base for an array of five compare/
capture modules. Figure I shows a block diagram of
the PCA. Notice that the PCA timer and modules are
all 16-bits. If an external event is associated with a
module, that function is shared with the corresponding
Port 1 pin. If the module is not using the port pin, the
pin can still be used for standard I/O.
PCA TIMER/COUNTER
The timer/counter for the PCA is a free-running 16-bit
timer consisting of registers CH and CL (the high and
low bytes of the count values). It is the only timer
which can service the PCA. The clock input can be
selected from the following four modes:
. oscillator frequency -;- 12 (Mode 0)
- oscillator frequency -;- 4 (Mode 1)
'- Timer 0 overflows (Mode 2)
- external input on P1.2 (Mode 3)
-
16 BITS EACH .....
MODULE 0
P1.3
MODULE 1
PIA
MODULE 2
P1.5
MODULE 3
P1.6
MODULE 4
Pl.7
-16BITS-PCA TIMER/COUNTER
270609-1
Figure 1. PCA Timer/Counter and Compare/Capture Modules
2-245
inter
AP-415
The table below summarizes the various clock inputs for each mode' at two common frequencies. In Mode 0, the
clock input is simply a machine cycle count, whereas in Mode 1 the input is clqcked three times faster. In Mode 2,
Timer 0 overflows are counted allowing for a range of slower inp~ts to the timer. And finally, if the input is external
the PCA timer counts I-to-O transitions with the maximum clock frequency equal to 1/. x oscillator frequency.
Table 1. PCA Timer/Counter Inputs
Clock Increments
PCA Timer/Counter Mode
12MHz
16 MHz
Mode 0: fosc 112
1 p.sec
0.75 p.sec
Mode 1: fosc 14
330 nsec
250 nsec
Mode 2*: Timer 0 Overflows
Timer 0 programmed in:
B-bitmode
16-bit mdoe
B-bit auto-reload
256 p.sec
65 msec
1 to 255 p.sec
192 p.sec
49 msec
0.75 to 191 p.sec
Mode 3: External Input MAX
0.66 p.sec
0.50 p.sec
"In Mode 2, the overflow interrupt for Timer 0 does not need to be enabled.
Special Function Register CMOD contains the Count Pulse Select bits (CPS! and CPSO) to specify the PCA timer
input. This register also contains the ECF bit which enables an interrupt when the counter overflows. In addition,
the user has the option of turning ofT the PCA timer during Idle Mode by setting the Counter Idle bit (CIDL). This
can further redl!ce power consumption by an additional 30%.
.
CMOD: Counter Mode Register
I
CIDL
I
WOTE
I
CPS1
Address = 009H
Not Bit Addressable
CPSO
ECF
Reset Value = OOXX XOOOB
NOTE:
The user should write Os to unimplemented bits. These bits may be used in future MeS-51 products to invoke new features,
and in that case the inactive value of the new bit will be O. When read, these bits must be treated as don't-cares.
Table 2 lists the values for CMOD in the four possible timer modes with and without the overflow interrupt enabled.
This list assumes that the PCA will be left running during Idle Mode.
Tabie 2. CMOD Values
CMODvalue
PCA Count Pulse Selected
without interrupt enabled
with interrupt enabled
Internal clock, Fosc/12
OOH
01 H
Internal clock, Foscl 4
02H
03H
Timer 0 overflow
04H
05 H
External clock at P1.2
06H
07H
2-246
AP-415
The CCON register shown below contains the Counter Run bit (CR) which turns the timer on or off. When the PCA
timer overflows, the Counter Overflow bit (CF) gets set. CCON also contains the five event flags for the PCA
modules. The purpose of these flags will be discussed in the next section.
CCON: Counter Control Register
I
CF
I
CR
I
CCF4
CCF3
CCF2
CCF1
Address = 008H
Bit Addressable
CCFO
Reset Value = OOXO OOOOB
The PCA timer registers (CH and CL) can be read and written to at any time. However, to read the full 16-bit timer
value simultaneously requires using one of the PCA modules in the capture mode and toggling a port pin in software.
More information on reading the PCA timer is provided in the section on the Capture Mode.
COMPARE/CAPTURE MODULES
Each of the five compare/capture modules has a mode register called CCAPMn (n = 0, 1,2,3,or 4) to select which
function it will perform. Note the ECCFn bit which enables an interrupt to occur when a module's event flag is set.
CCAPMn: Compare/Capture Mode Register
I
I
ECOMn
I
CAPPn
I
MATn
CAPNn
TOGn
PWMn
ECCFn
Reset Value = XOOO OOOOB
Address = OOAH (n = 0)
OOBH (n= 1)
OOCH (n=2)
OOOH (n=3)
OOEH (n=4)
Table 3 lists the CCAPMn values for each different mode with and without the PCA interrupt enabled; that is, the
interrupt is optional for all modes. However, some of the PCA modes require software servicing. For example, the
Capture modes need an interrupt so that back-to-back events can be recognized. Also, in most applications the
purpose of the Software Timer mode is to generate interrupts in software so it would be useless not to have the
interrupt enabled. The PWM mode, on the other hand, does not require CPU intervention so the interrupt is
normally not enabled.
Table 3. Compare/Capture Mode Values
CCAPMn Value
Module Function
Capture Positive only
without interrupt enabled
with interrupt enabled
20H
21 H
Capture Negative only
10H
11 H
Capture Pos. or Neg.
30H
31 H
Software Timer
48H
49H
High Speed Output
4CH
40H
Watchdog Timer
Pulse Width Modulator
48 or4C H
-
42H
43H
2-247
AP·415
It should be mentioned that a particular module can change modes within the program. For example, a module might be,used to sample incoming data. Initially it could be set up to capture a falling edge transition. Then the same
module can be reconfigured as a software timer to interrupt the CPU-at regular intervals and sample the pin.
Each module also has a pair of 8-bit compare/capture registers (CCAPnH, CCAPnL) associated with it. These
registers are used to store the time when a capture event occurred or when a compare event should occur. Remember, event times are based on the free-running PCA timer (CH and CL). For the PWM mode, the high byte register
CCAPnH controls the duty cycle of the waveform.
When an event occurs, a flag in CCON is set for the appropriate module. This register is bit addressable so that event
flags can be checked individually.
CCON: Counter Control Register
CF
I
CR
Address = 008H
Bit Addressable
I
CCF3
CCF4
1
CCF2
CCF1
CCFO
ResetValue = OOXO OOOOB
These five event flags plus the PCA timer overflow flag share an interrupt vector as shown below. These flags are not
cleared when the hardware vectors to the PCA interrupt address (OO33H) so that the user can determine which event
caused the interrupt. This also allows the user to defme the priority of servicing each module.
cr~
ccrn ~ PCA INTERRUPT
5
270609-2
Figure 2. PCA Interrupt
An additional bit was added to the Interrupt Enable (IE) register for tlie PCA interrupt. Similarly, a high priority bit
was added to the Interrupt Priority (IP) register.
IE: Interrupt Enable Register
I
EA
1
EC
1
ET2
ES
ET1
EX1
Address = OA8H
Bit Addressable
ETa
Reset Value
I=
EXO
0000 OOOOS
IP: Interrupt Priority Register
I
1
PPC
Address = OB8H
Sit Addressable
1
PT2
PS
PT1
PX1
PTa
PXO
Reset Value = XOOO OOOOB
Remember, each of the six possible sources for the PCA interrupt must be individually enabled as well-in the
CCAPMn register for the modules and in the CCON register for the timer.
2-248
inter
AP-415
CAPTURE MODE
Measuring Pulse Widths
Both positive and negative transitions can trigger a capture with the PCA. This allows the PCA flexibility to
measure periods, pulse widths, duty cycles, and phase
differences on up to five separate inputs. This section
gives examples of all these different applications.
To measure the pulse width of a signal, the PCA module must capture both rising and falling edges (see Figure 4). The module can be programmed to capture either edge if it is known which edge will occur first.
However, if this is not known, the user can select w'hich
edge will trigger the first capture by choosing the proper mode for the module.
Figure 3 shows how the PCA handles a capture event.
Using Module 0 for this example, the signal is input to
PJ.3. When a transition is detected on that pin, the 16bit value of the PCA timer (CH,CL) is loaded into the
capture registers (CCAPOH,CCAPOL). Module O's
event flag is set and an interrupt is flagged. The interrupt will then be generated if it has been properly enabled.
In the interrupt service routine, the l6-bit capture value
must be saved in RAM before the next event capture
occurs; a subsequent capture will write over the first
capture value. Also, since the hardware does not clear
the event flag, it must be cleared in software.
Listing 1 shows an example of measuring pulse widths.
(It's assumed the incoming signal matches the one in
Figure 4.) In the interrupt routine the first set of capture values are stored in RAM. After the second capture, a subtraction routine calculates the pulse width in
units of PCA timer ticks. Note that the subtraction
does not have to be completed in the interrupt service
routine. Also, this example assumes that the two capture events will occur within 216 counts of the PCA
timer, i.e. rollovers of the PCA timer are not counted.
~
t
t
The time it takes to service this interrupt routine determines the resolution of back-to-back events with the
same PCA module. To store two 8-bit registers and
clear the event flag takes at least 9 machine cycles. That
includes the call to the interrupt routine. At 12 MHz,
this routine would take less than 10 microseconds.
However, depending on the frequency and interrupt latency, the resolution will vary with each application.
CAPTURE 1
CAPTURE 2
270609-4
Time (Capture 2) - Time (Capture 1) = Pulse Width
Figure 4. Measuring Pulse Width
PCA TIMER
MODULE 0
PCA INTERRUPT
INTERRUPT
SERVICE
ROUTINE
EXIT
Figure 3. PCA Capture Mode (Module 0)
2-249
270609-3
AP-415
Listing 1. Measuring Pulse Widths
,
RAM locations to store capture values
DATA
30H
CAPTURE
PULSE_WIDTH
DATA
32H
FLAG
BIT
20H.0
ORG OOOOH
JMP PCA_INIT
ORG 0033H
JMP PCA~INTERRUPT
,
PCA-INIT:
MOV CMOD, #OOH
MOV CH, #OOH
MOV CL, #OOH
Initialize PCA timer
Input to timer
1/12 X Fosc
=
Initialize Module 0 in capture mode '
MOV CCAPMO, #21H
Capture positive edge first
for measuring pulse width
SETB EC
SETB EA
SETB CR
CLR FLAG
Enable PCA interrupt
Turn PCA timer on
clear test flag
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
Main program goes here
** ••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••
,
This example assumes Module 0 is the only PCA module
being used. If other modules are used, software must
check which module's event caused the interrupt.
PCA_INTERRUPT:
CLR CCFO
JB FLAG, SECOND_CAPTURE
FIRST_CAPTURE:
MOV CAPTURE, CCAPOL
MOV CAPTURE+l, CCAPOH
MOV CCAPMO, #llH
,
SETB FLAG
RETI
SECOND_CAPTURE:
PUSH ACC
PUSH PSW
CLR C
MOV A, CCAPOL
SUBB A, CAPTURE
MOV PULSE_WIDTH, A
MOV A, CCAPOH
SUBB A, CAPTURE+l
MOV PULSE_WIDTH+l, A
Clear Module O's event flag
Check if this is the first
capture or second
Save la-bit c'apture value
in RAM
Change module to now capture
falling edges
Signify 1st capture complete
la-bit subtract
la-bit result stored in
two a-bit RAM locations
,
MOV CCAPMO, #21H
CLR FLAG
POP PSW
POP ACC
RETI
Optional--needed if user wants to
measure next pulse width
2-250
AP-415
Measuring Periods
Measuring Frequencies
Measuring the period of a signal with the peA is similar to measuring the pulse width. The only difference
will be the trigger source for the capture mode. In Figure 5, rising edges are captured to calculate the period.
The code is identical to Listing I except that the capture mode should not be changed in the interrupt routine. The result of the subtraction will be the period.
Measuring a frequency with the peA capture mode
involves calculating a sample time for a known number
of samples. In Figure 6, the time between the first capture and the "Nth" capture equals the sample time T.
Listing 2 shows the code for N = 10 samples. It's assumed that the sample time is less than 216 counts of
the peA timer.
s-L..rL
j.-------.j
t
CAPTURE 1
~----------
t
CAPTURE 2
T
----------~
t
t
CAPTURE 1
CAPTURE N
270609-6
Time (Capture N) - Time (Capture 1) = T
N # of Samples
270609-5
Time (Capture 2) - Time (Capture 1) = Period
Figure 5. Measuring Period
Frequency
= T = Sample Time
Figure 6. Measuring Frequency
2-251
inter
AP-415
Listing 2. Measuring Frequencies
RAM locations to store capture values
DATA
CAPTURE
30H
DATA
PERIOD
32H
SAMPLE_COUNT
DATA
34H
FLAG
BIT
20H.0
ORG
JMP
ORG
JMP
OOOOH
PCA_INIT
0033H
PCA_INTERRUPT
PCA_INIT:
Initialization of PCA timer, Module 0, and interrupt is the
same as in Listing 1. Also need to initialize the sample
count.
=
MOV SAMPLE_COUNT, #lOD
; N 10 for this example
'
. *_._ ......... _................ _-_.
, __ ._ .... * •••••• _•••••• _•• -_ ••
...............
,
program goes here
-.............. .. -•..•....•..•• -........ ... ... ...... ........... _._Main........
;
_
_
_
This code assumes only Module 0 is being used.
PCA_INTERRUPT:
CLR CCFO
; Clear module O's event flag
JB FLAG, NEXT_CAPTURE
FIRST_CAPTURE:
MOV CAPTURE, CCAPOL
MOV CAPTURE+l, CCAPOH
SETB FLAG
RETI
NEXT_CAPTURE:
DJNZ SAMPLE_COUNT, EXIT
PUSH ACC
PUSH PSW
CLR C '
MOV A, CCAPOL
SUBB A, CAPTURE
MOV PERIOD, A
MOV A, CCAPOH
SUBB A, CAPTURE+l
MOV PERIOD+l, A
MOV ~AMPLE_COUNT. #lOD
CLR FLAG
POP PSW
POP ACC
EXIT:
RET I
Signify first capture complete
IS-bi t subtraction
Reload for next period
2-252
_
inter
AP-415
The user may instead want to measure frequency by
counting pulses for a known sample time. In this case,
one module is programmed in the capture mode to
count edges (either rising or falling), and a second module is programmed as a software timer to mark the
sample time. An example of a software timer is given
later. For information on resolution in measuring frequencies, refer to Article Reprint AR-517, "Using the
8051 Microcontroller with Resonant Transducers," in
the Embedded Controller Handbook.
Measuring Duty Cycles
To measure the duty cycle of an incoming signal, both
ri~ing and falling edges need to be captured. Then the
duty cycle must be calculated based on three capture
values as seen in Figure 7. The same initialization routine is used from the previous example. Only the peA
interrupt service routine is given in Listing 3.
~
t
t
t
CAPTURE 1 CAPTURE 2 CAPTURE 3
270609-7
pt;.:u;..;re;..;2o:.l_--:::T;;.im;;.e-,(,=C.:;aP
im;;.e;;.(:,:C,.:;a:::.
Tc:::..t.:;ur;.:e--:-:-1l
I
=
= pulse width = dutycyce
Time (Capture 3) - Time (Capture 1)
period
Figure 7. Measuring Duty Cycle
Listing 3. Measuring Duty Cycle
RAM locations to store capture
CAPTURE
DATA
PULSE_WIDTH
DATA
PERIOD
DATA
FLAG_I
BIT
FLAG_2
BIT
ORG
JMP
ORG
JMP
values
30H
32H
34H
20H.0
20H.I
OOOOH
PCA_INIT
0033H
PCA_INTERRUPT
PCA_INIT:
Initialization for PCA timer, module, and interrupt the same
as in Listing 1. Capture positive edge first, then either
edge.
....... ...
,..••••...••.•........• -
_ _..•....•..•.•............••.....•.•..•
;
Main program goes here
,•• *•• ****.***.* ••• *.*.*** •••• *•• ** ••• *****.*~.****.*** •••••••••••••••••••
,
,
; This code assumes only Module 0 is being used.
PCA_INTERRUPT:
CLR CCFO
Clear Module O's event flag
JB FLAG_I, SECOND_CAPTURE
FIRST_CAPTURE:
MOV CAPTURE, CCAPOL
MOV CAPTURE+I, CCAPOH
SETB FLAG_I
MOV CCAPMO, #31H
RETI
Signify first capture complete
Capture either edge now
2-253
inter
AP-415
Listing 3. Measuring Duty Cycle (Continued)
SECOND_CAPTURE:
PUSH ACC
PUSH PSW .
JBFLAG_2', THIRD_CAPTURE
CLR C
Calculate pulse width
MOV A, CCAPOL
rlS-bit subtract
SUBB A, CAPTURE
MOV PULSE_WIDTH, A
MOV A, CCAPOH
SUBB A, CAPTURE+I
MOV PULSE_WIDTH+I, A
SETB FLAG_2
Signify second capture complete
POP PSW
POP ACC
RETI
THIRD_CAPTURE:
CLR C
MOV A, CCAPOL
SUBB A, CAPTURE
MOV PERIOD, A
MOV A, CCAPOH
SUBB A, CAPTURE+I
MOV PERIOD+I, A
MOV CCAPMO, #21H
CLR FLAG_I
CLR FLAG_2
POP PSW
POP ACC
RETI
Calculate period
IS-bit subtract
Optional - reconfigure module to
capture positive edges 'for next
cycle
After the third capture, a 16-bit by 16-bit divide routine
needs to be executed. This routine is located in Appendix B. Due to its length, it's up te the user whether the
divide routine should be cdmpleted in the interrupt routine or be called as a subroutine .from the main program.
between twe or more signals. Fer this example, two
signals are input to Modules 0 and 1 as seen in Figure
8. Both modules are programmed to capture rising edges only. Listing 4 shows the code needed to measure the
difference between these two signals. This code does
not assume .one signal is leading or lagging the other.
Measuring Phase Differences
Because the PCA modules share the same time base,
the PCA is useful for measuring the phase difference
t.40DULE 0
--I
CAPTURE 1
MODULE 1
r"
U
L
CAPTURE 2
-
270609-8
ASS [Time (Capture 2) - Time (Capture 1)1 = Phase Difference
Figure 8. Measuring Phase Differences
2-254
AP-415
Listing 4. Measuring Phase Differences
RAM locations to store capture
CAPTURE_O
DATA
CAPTURE_l
DATA
DATA
PHASE
FLAG_O
BIT
FLAG_l
BIT
ORG
JMP
ORG
JMP
values
30H
32H
34H
20H.0
20H.l
OOOOH
PCA_INIT
0033H
PCA_INTERRUPT
PCA_INIT:
Same initialization for PCA timer, and interrupt as
in Listing 1. Initialize two PCA modules as follows:
,
MOV CCAPMO, #2lH
MOV CCAPMl, #2lH
Module 0 capture rising edges
Module 1 same
,.**************************************************************************************
;
Main program goes here
,.**************************************************************************************
; This code assumes only Modules 0 and 1 are being used.
PCA_INTERRUPT:
JB CCFO, MODULE_O
Determine which module's
JB CCFl, MODULE_l
event caused the interrupt
MODULE_O:
CLR CCFO
MOV CAPTURE_O, CCAPOL
MOV CAPTURE_O+l, CCAPOH
JB FLAG_I, CALCULATE_PHASE
SETB FLAG_O
RETI
Clear Module O's event flag
Save l6-bit capture value
If capture complete on
Module I, go to calculation
Signify capture on Module 0
2-255
inter
AP-415
LIsting 4. Measuring Phase Differences (Continued)
MODULE_l:
CLR CCF_l
MOV CAPTURE_l, CCAP1L
MOV CAPTURE_l+l, CCAP1H
JB FLAG_O, CALCULATE_PHASE
SETB FLAG_l
RET!
Clear Module l's event flag
If oapture oomplete on
; Module 0, go to oaloulation
; Signify oapture on Module 1
;
CALCULATE_PHASE:
PUSH ACC
PUSH PSW
CLR C
; This oaloulation does not
; have to be oompleted in the
; interrupt servioe routine
JB FLAG_O, MODO_LEADING
JB FLAG_l, MOD1_LEADING
;
MODO_LEADING:
MOV'A, CAPTURE_l
SUBB A, CAPTURE_O
MOV PHASE, A
MOV A, CAPTURE_l+l
SUBB A, CAPTURE_O+l
MOV PHASE+l, A
CLR FLAG_O
JMP EXIT
;
MOD;L_LEADING:
MOV A,CAPTURE_O
SUBB A, CAPTURE_l
MOV PHASE, A
MOV A, CAPTURE_O+l
SUBB A, CAPTURE_l+l
MOV PHASE+l, A
CLR FLAG_l
EXIT:
POP PSW
POP ACC
RETI
2-256
inter
AP-415
Readjng the PCA Timer
SOFTWARE TIMER
Some applications may require 'that the PCA timer be
read instantaneously as a real-time event. Since the timer consists of two 8-bit registers (CH,CL), it would normally take two MOV instructions to read the whole
timer. An invalid read could occur if the registers rolled
over in the middle of the two MOVs.
In most applications a software timer is used to trigger
interrupt routines which must occur at periodic intervals. Figure 9 shows the sequence of events for the Software Timer mode. The user preloads a l6-bit value in a
module's compare registers. When a match occurs between this compare value and the PCA timer, an event
flag is set and an interrupt is flagged. An interrupt is
then generated if it has been enabled.
However, with the capture mode a l6-bit timer value
can be loaded into the capture registers by toggling a
port pin. For example, configure Module 0 to capture
falling edges and initialize P1.3 to be high. Then when
the user wants to read the PCA timer, clear P1.3 and
the full l6-bit timer value will be saved in the capture
registers. It's still optional whether the user wants to
generate an interrupt with the capture.
Ifnecessary, a new l6-bit compare value can be loaded
into (CCAPOH, CCAPOL) during the interrupt routine. The user should be aware that the hardware temporarily disables the comparator function while these registers are being updated so that an invalid match will not
occur. That is, a write to the low byte (CCAPnO) dis-
ables the comparator while a write to the high byte
(CCAPOH) re-enables the comparator. For this reason,
user software must write to CCAPOL first, then
CCAPOH. The user may also want to hold off any interrupts from occurring while these registers are being
updated. This can easily be done by clearing the EA bit.
See the code example in Listing 5.
COMPARE MODE
In this mode, the l6-bit value of the PCA timer is compared with a l6-bit value pre-loaded in the module's
compare registers. The comparison occurs three times
per machine cycle in order to recognize the fastest possible clock input, i.e. 'I. x oscillator frequency. When
there is a match, one of three events can happen:
(1) an interrupt
- Software Timer mode
(2) toggle of a port pin - High Speed Output mode
(3) a reset
- Watchdog Timer mode.
Examples of each compare mode will follow.
CH
CL
~
COMPARATOR
it..
....._C_H..........._C_L.......
1I
,--C_H--L_CL......
COMPARATOR
PCA TIMER
MATCH
i
I PERIOD.
;'*** •••••••• **••• ****,.***...................... ,*............................................,**, ••••
DUTY_CYCLE_CALCULATION:
MOV A,PERIOD+1
CJNE A,PUlSE_WIDTH+1,NOT_EQUAl
MOV A,PERIOD
CJNE A,PUlSE_WIDTH,NOT_EQUAl
270609-35
2-283
inter
AP-415
EQUAL:
SETB C
MOV DUTY_CYCLE~
CLR OV
RET
NOT EQUAL:
- JNC CONTINUE
SETB OV
RET
CONTINUE:
MOV
MOV
MOV
R2,#8
DUTY_CYCLE~O
R3,1IO
TIMES_lWO:
MOV A,PULSE_WIDTH
RLC A
MOV PULSE_WIDTI'I,A
MOV A,PULSE_WIDTH+1
RLCA
MOV PULSE_WIDTH+1,A
MOV A,R3
RLC A
,",OV R3,A
COMPARE:
CJNE RS,IIO,DONE
MOV A,PULSE_WIDTH+1
CJNE A,PERIOD+1,DONE
MOV A,PULSE_WIDTH
CJNE A,PERIOD,DONE
DONE:
CPL C
BUILD_DUTY_CYCLE:
MOV A,DUTY_CYCLE
RLC A
MOV DUTY_CYCLE,A
JNB ACC.O,LOOP CONTROL
SUBTRACT:
MOV A,PULSE_WIDTH
SUBB A,PERIOD
MOV PULSE_WIDTH,A
MOV A,PULSE_WIDTH+1
SUBB A,PERIOD+1
MOV PULSE_WIDTH+1,A
MOV A,R3
SUBB A,IIO
MOV R3,A
LOOP_CONTROL:
DJNZ R2,TIMES_lWO
270609-36
2-284
inter
AP·415
FINAL TIMES TWO:
-MOV -A,PULSE_WIDTH
RLC A
MOV PULSE_WIDTH,A
MOV A,PULSE_WIDTH+l
RLC A
MOV PULSE_WIDTH+l,A
MOV A,R3
RLC A
MOV R3,A
FINAL_COMPARE:
CJNE R3,11O,FINAL_DONE
MOV A,PULSE_WIDTH+l
CJNE A,PERIOD+l,FINAL_DONE
MOV A,PULSE_WIDTH
CJNE A,PERIOD,FINAL_DONE
FINAL_DONE:
JC
CONVERT_TO_BCD
MOV A,DUTY_CYCLE
ADD A,1II1
MOV DUTY CYCLE,A
JNC CONVERT_TO_BCD
CLR OV
RET
CONVERT_TO_BCD:
MOV A,DUTY_CYCLE
MOV B,1II10
MUL AB
XCH A,B
SWAP A
MOV DUTY_CYCLE,A
MOV A,1II10
MUL AB
XCH A,B
ORL DUTY_CYCLE,A
MOV A,1II10
MUL AB
MOV A,B
CJNE A,III$,TEST
TEST: JBC CY,OUT
MOV A,DUTY_CYCLE
ADD A,1II1
DA
A
MOV DUTY_CYCLE,A
OUT: RET
END
270609-37
2-285
inter
Ap·415
APPENDIX C
Read accesses to these addresses will in general return
random data, and write accesses will have no effect.
A map of the Special Function Register (SFR) space is
shown in Table AI. Those registers which are new or
have new bits added for the 83C51FA and 83C51FB
have been boldfaced.
User software should not write Is to these unimplemented locations, since they may be used in future 8051
family products to invoke'new features. IJl that case the
reset or inactive values of the new bits will, always be 0,
and their active values will be 1.
Note that not all of the addresses are occupied. Unoccupied addresses are not implemented on the chip.
Table A1. Special Function Register Memory Map and Values After Reset
CH
CCAPOH
CCAP1H
CCAP2H
CCAP3H
CCAP4H
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
F8
FO *B
00000000
F7
CL
E8
FF
CCAPOL
CCAP1L
CCAP2L
CCAP3L
CCAP4L
EF
00000000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
EO • AGC
E7
00000000
08
CCON
CMOD
CCAPMO
OOXOOOOO OOXXXOOO XOOOOOOO
DO • PSW
00000000
C8 T2CON
T2MOD
RCAP2L
00000000 XXXXXXXO 00000000
CO
CCAPM1
XOOOOOOO
CCAPM2
XOOOOOOO
CCAPM3 , CCAPM4
XOOOOOOO XOOOOOOO
OF
07
RCAP2H
00000000
TL2
00000000
TH2
00000000
CF
C7
B8 'IP
SADEN
XOOOOOOO 00000000
BF
BO • P3
11111111
A8 'IE
SADDR
00000000 00000000
AO • P2
11111111
*
98 SCON ' • SBUF
00000000 xxxxxxxx
B7
AF
A7
9F
90 • P1
97
11111111
88 'TCON
'TMOD
'TL1
• TLO
• THO
• TH1
00000000 00000000 00000000 00000000 00000000 00000000
80 • PO
' SP
• DPL
• DPH
11111111 00000111 00000000 00000000
8F
'PCON ,. 87
OOXXOOOO
• = Found In the 8051 core (See 8051 Hardware Description In the Embedded Controller Handbook for explanajions of
these SFRs).
•• = See description of PCON SFR. Bit PCON.4 is not affected by reset.
X = Undefined.
2-286
intJ
AP-425
APPLICATION
NOTE·
September 1988
Small DC Motor Control
JAFAR MODARES
, ECO APPLICATIONS
@ Intel Corporation, 1988
Order Number: 270622-001
2-287
inter
AP·425
INTRODUCTION
This application note shows how an 83C51FA can be
used to efficiently control DC motors with minimum
hardware requirements. It also discusses software implementation and presents helpful techniques as well as
sample code needed to realize precision control of a
motor.
ing the polarity of the voltage applied to the ~otor.
Figure 1 shows a simplified symbolic rep.resentatlon ~f
a driver circuit which is capable of reversmg the polanty of the input to the motor.
There is also a brief overview of the new features of the
83C51FA. This new feature is called the Programmable
Counter Array (PCA) and is capable of delivering
Pulse Width Modulated signals (PWM) through designated I/O pins.
270622-1
It is assumed that the reader is familiar with the MCS-
51 architecture and its assembly language. For more
information about the 8051 architecture and the PCA .
refer to the Embedded Controller Handbook Volume 1
(order no. 210918-006).
This document will not discuss stepper motors or motor control algorithms.
DC MOTORS
DC motors are widely used in industrial and consumer
applications. In many cases, absolute precision in
movement is not an issue, but precise speed control is.
For example, a DC motor in a cassette player is expected to run at a constant speed. It does not have to run
for precise increments which are fractions of a tum and
stop exactly at a certain point.
However, some motor applications do require precise
positioning. Examples are high resolution plotters,
printers, disk drives, robotics, etc. Stepper motors are
frequently used in those applications. There are also
applications which require precise speed control along
with some position accuracy. Video recorders, compact
disk drives, high quality cassette recorders are examples
of this category.
By controlling DC motors accurately, they can overlap
many applications of stepper motors. The cost of the
control system depends on the accuracy of the encoder
and the speed of the processor.
The 83C51FA can control a DC motor accurately with
minimum hardware at a very low cost. The microcontroller as the brain of a system, can digitally control
the a~gular velocity of the motor, by monitoring the
feedback lines and driving the output lines. In addition
it can perform other tasks which may be needed in the
application.
Almost every application that uses· a DC motor requires it to reverse its direction of rotation or vary its
speed. Reversing the direction is simply done by chang-
Figure 1. Reversible Motor Driver Circuit
Varying the speed requires changing the voltage ~evel of
the input to the motor, and that means changmg the
input level to the motor driver. In a digitally-controlled
system, t4e analog signal to the driver must come from
some form of D/A converter. But adding a D/A converter to the circuit adds to the chip count, which
means more cost, higher power consumption, and reduced reliability of the system.
The other alternative is to vary the pulse width of a
digital signal input to the motor. By varying the pulse
width the average voltage delivered to the motor chang~
es and so does the speed of the motor. A digital circuit
that does this is called a Pulse Width Modulator
(PWM). The 83C51FA can be configured to have up to
5 on-board pulse width modulators ..
THE 83C51FA
The 83C51FA is an 8-bit microcontroller based on the
8051 architecture. It is an enhanced version of the
87C51 and incorporates many new features including
the Programmable Counter Array (PCA).
Included in the Programmable Counter Array is a 16bit free running timer and 5 separate modules.
The PCA timer has two 8-bit registers called CL (low
byte) and CH (high.byte), and is shared by all modules.
It can be programmed to take input from four different
sources. The inputs provide flexibility in choosing the
count rate of the timer. The maximum count rate is 4
MHz ('14 of the oscillator frequency).
Some of the port 1 pins are used to interface each module and the timer to the outside world. When the port
pins are not used by the PCA modules,- they may be
used as regular I/O pins.
The modules of the PCA can be programmed to perform in one of the following modes: capture mode,
2-288
intJ
AP-425
compare mode, high speed output mode, pulse width
modulator (PWM) mode, or watchdog timer mode
(only module 4).
Every module has an 8-bit mode register called
CCAPMn (Figure 2), and a l6-bit compare/capture
register called CCAPnL & CCAPnH, where n can be
any value from 0 to 4 inclusive. By setting the appropriate bits in the mode register you can program each
module to operate in one of the aforementioned modes.
PWM is one of the compare modes and is the only one
which uses only 8 bits of the capture/compare register.
The user writes a value (0 to FFH) into the high byte
(CCAPnH) of the selected module. This value is transferred into the lower byte of the same module and is
compared to the low byte of the PCA timer. While CL
< CCAPnL the output on the corresponding pin is a
logic O. When CL > CCAPnL, the output is a logic !.
In this application note we will see how a module can
be programmed to perform as a PWM to control the
speed and direction of a DC motor.
SETTING UP THE peA
CCAPMn
The 83CSIFA has several Special Function Registers
(SFRs) that are unknown to ASMSI versions before
2.4. The names of these SFRs must be defined by
DATA directive or be defined in a separate file and be
included at the time of compilation. Such a file has
already been created and is inclUded in the ASMS 1
package version 2.4.
ECOMn- Enables the comparator function. Must
be set for functions which require comparing of the compare/capture registers
with the 16-bit timer, i.e., software timer, high-speed output, watchdog timer,
and PWM.
CAPPn -
Capture on positive edge of signal.
CAPNn MATn -
Capture on negative edge of signal.
Find a match between the capture/
compare and 16-bit timer.
Toggle I/O pin upon a match between
capture/compare registers and 16-bit
timer.
TOGn -
PWMn -
ECCFn -
Two special function registers are dedicated to the PCA
timer to allow mode selection and control of the timer.
These registers are CCON and CMOD and are shown
in figure 3. CCON'contains the PCA timer ON/OFF
bit (CR), timer rollover flag (CF) and module flags
(CCFn). Module flags are used to determine which
module causes the PCA interrupt.
Generate PWM on I/O pin upon a
match between the low byte of capture/
compare and the low byte of PCA timer.
Enables compare/capture flag CCFn in
the CCON register to generate an interrupt.
CF
CR
CCF4
CCF3
Address GD8H
CCF2
I
CCFl
I
o.
CCFO
I
Reset Value = ooxa 0000 B
Bit Addressable
CCON
Figure 2. CCAPMn Register
CIDL
I
WDTE
I
CPSl
Reset Value
Address OD9H
When a module is programmed in capture mode, an
external signal on the corresponding port pin will cause
a capture of the current value of the 16-bit timer. By
setting bits CAPPn or CAPNn or both, the module can
be programmed to capture on the rising edge, falling,
edge, or either edge of the signal. If enabled, an interrupt is generated at the time of capture.
When module is to perform in one of the compare
modes (software timer, high speed output, watch dog
timer, PWM), the user loads the capture/compare registers with a calculated value, which is compared to the
contents of the 16-bit timer, and causes an event as
soon as the values match. It can also generate an interrupt.
CPSO
=
ECF
OOXX XOOO B
Not Bit Addressable
CMOD
Figure 3. CCON and CMOD Registers
First the clock source for the PCA timer must be defined. The 16 bit timer may have one of four sources for
its input. These sources are: osc freq/4, osc freq/12,
timer 0 overflow, and external clock.
Two bits in the CMOD register are dedicated to selecting one of the sources for the PCA timer input. They
are bits 1 and 2 of CMOD which are called CPSO and
CPS!. CMOD is not bit addressable, thus the value
2-289
AP-425
must be loaded as a byte. Figure 4 shows all the sources
and the corresponding values of CPSO and CPSl.
CPS1
CPSO
TIMER INPUT SOURCE
0
0
0
1
1
0
Internal clock, Fosc/12
Internal clock, Fosc/4
Timer 0 overflow
External clock (input on P1.2)
1
1
DUTY CYCLE CCAPnH
Figure 4. Timer Input Source
Next the appropriate module must be programmed as a
PWM. As it was noted earlier, the 8-bit mode register
for each module is called CCAPMn (see figure 2). Bit 1
of each register is calIed PWMn. This bit along with
ECOMn (bit 6 of the same register) must be set to program the module in the PWM mode. PWM is one of
the compare functions of the. PCA, and ECOMn enables the compare function. Thus, the hex value that
must be loaded into the appropriate CCAPMn register
is 42H.
Now that the module is programmed as a PWM, a
value must be loaded in the high byte of the compare
register to select the duty cycle. The value can be any
number from 0 to 255. In the 83C51FA loading 0 in the
CCAPnH will yield 100% duty cycle, and 255 (OFFh)
.will generate a 0.4% duty cycle. See figure' 5.
The next step is to start the PCA timer. The bit that
turns the timer on and off is called CR and is bit 6 of
MOV
MOV
MOV
SETB
CMOD,#06
CCAPM2,#42H
CCAP2H,#O
CR
OUTPUT WAVEfORM
100%
00
90%
25
~
50%
128
---u-LSl-
10%
230
~
0.4%
255
270622-2
Figure 5. Selected Duty Cycles and Waveforms
CCON register (Figure 3). Since this register is bit addressable, you can use bit instructions to turn the timer
on and off.
In the folIowing example module 2 has been selected to
provide a PWM signal to .a motor driver. An external
clock will be provided for the timer input, so the value
that needs to be loaded into CMOD is 06H.
HARDWARE REQUIREMENT
When using an 83C51FA, very little hardware is required to control a motor. The controlIer can interface
to the motor through a driver as shown in figure 6.
timer input external
put the module in PWM mode.
o provides 100% duty cycle (5V)
turn timer on
END
. 2-290
AP-425
PloD
DIRECTION
P!.4
SPEED
83C51FA
ON/OFF
P!.6
;3>
MOTOR
ASSEMBLY
FEEDBACK
270622-3
Figure 6. Simplified Circuit Diagram of a Closed Loop System
This configuration, a closed loop circuit, takes up only
three 1/0 pins. The line controlling direction can be a
regular port pin but the speed control line must be one
of the port I pins which corresponds to a PCA module
selected for PWM. Depending on how the feedback is
generated and processed, it could be connected to a
regular 1/0, an external interrupt, or a PCA module.
Feedback is discussed in more detail in the feedback
section of this application note.
Standard motor drivers are available in many current
and voltage ratings. One example is the L293 series
which can output up to I ampere per channel with a
supply voltage of 36 V. It has separate logic supply and
takes logical input "(0 or I) to enable or disable each
channel. There are four channels per device. The
L293D also includes clamping diodes needed for protecting the driver against the back EMF generated during the reversing of motor.
The diagram in Appendix A is an example of a DC
motor circuit which has been built and bench-tested.
NOISE CONSIDERATIONS
DRIVER CIRCUIT
Although some DC motors operate at 5 volts or less,
the 83C51FA can not supply the necessary current to
drive a motor directly. The minimum current requirements of any practical motor is higher than any microcontroller can supply. Depending on the size and ratings of the motor, a suitable driver must be selected to
take the control signal from the 83C51FA and deliver
the necessary voltage and current to the motor.
A motor draws its maximum current when it is fully
loaded and starts from a stand still condition. This factor must be taken into account when choosing a driver.
However, if the application requires reversing the motor, the current demand will even be higher. As the
motor's speed increases, it's power consumption decreases. Once the speed of a motor reaches a steady
state, the current depends on the load and the voltage
across the motor.
Motors generate enough electrical noise to upset the
performance of the con,troller. The source of the noise
could be from the switching of the driver circuits or the
motor itself. Whatever the cause of the noise may be, it
must be isolated or bypassed.
Isolating the microcontroller from the driver circuit is
helpful in keeping the noise limited.
Bypass capacitors help a great deal in suppressing the
noise. They must be added to the power and ground
(Figure 7 diagram a), on the driver circuit (diagram b),
on the motor terminals (diagram c), and on the
83C51FA (diagram d). The capacitors must be as close
to the component as possible. In fact the best location is
under the chip or on top of it if packaging allows. The
diagrams in figure 7 show the location and some typical
values for the bypass capacitors.
2-291
AP-425
DRIVER VOLTAGE
Vee
Tvee
.lcl
IC2
ISOp.F 16.8p.F
1.
LOGIC
1
I
C3
O.lp.F
(0) .
0.1 p.F =~
-:
83CS1FA
(d)
270622-4
Figure 7. Typical Locations and Values for Bypass Capacitors
OPEN LOOP & CLOSED LOOP
SYSTEMS
There are two types Qf motor control systems: open
'.
loop and closed loop.
In the open loop system the controller outputs a signal
to turn the motor on/off or to change the direction of
the rotation based on an input that does not come from
the motor. For example, the position of a manual or
timer switch becomes the input to the controller, which
varies the input to the motor. In another case, the controller may take input from data tables in the program
to run, vary the speed, reverse direction, or stop the
motor.
Closed loop systems can use one or more of the above
mentioned examples for the open loop system, plus at
least one feedback signal from the motor. The feedback
signal provides such information as speed, position,
and/or direction of motion.
Many applications require that a motor run -at a constant speed. The controller has to continuously make
adjustments to keep the speed within the limits. In
some cases the speed of the motor is synchronized to
another motor or moving part of the system.
Depending on the type of feedback signal, the
83C5lFA may have to use other modules of the PCA
along with other on-chip peripherals such as Timer/
Counters, Serial Port, and the interrupt system to precisely control a DC motor.
The example in die following section uses one PCA
module to generate PWM, and another module (in capture mode) to receive feedback from a DC motor.
FEEDBACK
The feedback comes from a sensing device which can
detect motion. The sensing device may be an optical
encoder, infrared detector, Hall effect sensor, etc. Depending on the application, one or more of the above
mentioned sensing devices may be suitable.
The optical sensors should be encapsulated for better
reliability. If they are not enclosed, factors such as ambient light, dust, and dirt can lessen their sensitivity.
Hall effect sensors are insensitive to any type of light.
They change logic levels going into and coming out of a
magnetic field. The sensing device is normally mounted
2-292
intJ
Ap·425
on some stationary part of the system and the magnet is
installed on the rotating part. The potential problem
with the Hall effect sensors are that if the gap between
the magnet and the sensing device is too big, the sensing device may not be affected by the magnetic field.
Also the number of magnets is limited which means
fewer feedback pulses will be provided.
Whatever the means of sensing, the result is a signal
which is fed to the controller. The 83C5lFA can use
the feedback signal to determine the speed and position
of the motor. Then it can make adjustments to increase
or decrease the speed, reverse the direction, or stop the
motor.
In the following example module 3 of PCA is set up to
perform in the capture mode. In this mode module 3
will receive feedback signals from a Hall effect transistor fixed behind a wheel which is mounted on the shaft
of a DC motor. Two magnets are embedded on this
wheel in equal distances from each other (180 degrees
apart). Every time that the Hall effect transistor passes
through the magnetic field, it generates a pulse.
The signal is input to Pl.6 which is the external interface for module 3 of the PCA. In this example, module
3 is programmed to capture on the rising edge of the
input signal. The time between the two captures corresponds to '/. of a revolution. Thus, two consecutive
captures can provide enough information to calculate
the speed of the motor as explained in the next paragraph. By storing the value of the capture registers each
time, and comparing it to its previous value, the controller can constantly measure and adjust the speed of
the motor. Using this method one can run a motor at a
precise speed, or synchronize it to another event.
In the PCA interrupt service routine, each capture value is stored in temporary locations to be used in a subtract operation. Subtracting the first capture from the
second one will yield a 16-bit result. The resultant value, which will be referred to as "Result" in the rest of
this document, is in PCA timer counts. An actual RPM
can be calculated from Result. Although the 83C5lFA
can do the calculation, it would be much faster to provide a lookup table within the code. The table will contain values which have been calculated for a possible
range of Results.
The following code is an example of how to measure
the period of a signal input to module 3 of the
83C5l FA. The diagram in figure 8 shows how the period corresponds to the rotation of the wheel. In the diagram "T" is the period and "t" is the time that the
magnet is passing in front of the Hall effect transistor.
----
~
~
000
I
HAll EFFECT
TRANSISTOR
I
I
~
~
2
3
I
~
4
itr
U
U
T
I'
'I
270622-5
Figure 8. The Output Waveform of the Half Effect Transistor as it goes Through the Magnetic Field
2-293
inter
AP-425
FLAG
BIT
HLBYTE_TMP
LO_BYTE_TMP
HI_BYTE_RESULT
LO_BYTE_RESULT
0
DATA
DATA
DATA
DATA
ORG
JMP
BEGIN
ORG
JMP
33H
PCA_ISR
MOV
MOV
MOV
·SETB
MOV
CLR
SETB
CMOD,#O
CCAPM3,#2lH
CCAP3H,#9AH
IP.6
IE,#OCOH
FLAG
CR
test flag
45H
46H
47H
48H
~OH
BEGIN:
SET PCA TIMER InPUT fOSC/12.
MODULE 3 IN POSITIVE CAPTURE MODE.
PWM AT 60 PERCENT DUTY CYCLE.
SET PCA INT. AT HIGH PRIORITY.
ENABLE PCA INTERRUPT.
TURN PCA TIMER ON.
PCLISR:
JB
SETB
MOV
MOV
CLR
RETI
FLAG,CAP_2
; FLAG BIT IS SET TO SIGNIFY 1st
FLAG
; CAPTURE COMPLETE.
HI_BYTE_TMP,CCAP3H; SAVE FOR NEXT CALCULATION.
LO_BYTE_TMP,CCAP3L
CCF3
; RESET PCA INT. FLAG MODULE 3
CLR
MOV
SUBB
MOV
MOV
SUBB
MOV
CLR
A,CCAP3L
A,LO_BYTE_TMP
LO_BYTE_RESULT,A
A,CCAP3H
A,HLBYTE_TMP
HI_BYTE_RESULT,A
IE.6
C
FOR SUBTRACT OPERATION.
SUBTRACT OLD CAPTURE FROM NEW CAPTURE.
SUBTRACTION RESULT OF LOW BYTE.
HIGH BYTE SUBTRACTION.
SUBTRACTION RESULT OF HIGH BYTE.
DISABLE PCA INTERRUPT.
In this example only one measurement is taken. That is why
the PCA interrupt is disabled in the above line of instruction.
RET_PCA:
CLR
RETI
END
CCF3
; RESET PCA INT. FLAG MODULE 3
SOFTWARE/CPU OVERHEAD
It takes the 83C51FA no more than 250 bytes of code
to control a DC motor. That is to run the motor at
various speeds, monitor the feedback, use electrical
braking, and even run it in steps. However, the CPU
time spent on the above tasks can add up to 70 to 75%
of the total time available (clock frequency 12 MHz).
The section of software which turns the motor on and
off, or sets the speed is very short. In fact, all of that
can be done in less than 30 instructions. Thus, in allopen loop system, the controller spends an insignificant
amount of time on controlling the motor, However, in a
closed loop system the controller has to continuously
monitor the speed and adjust it according to the program and the feedback.
The re&t of this section talks about electrical braking,
stepping a DC motor, and offers examples of code to
implement these techniques.
2-294
AP-425
ELECTRICAL BRAKING
Once a DC motor is running, it picks up momentum.
Turning ofT the voltage to the motor does not make it
stop immediately because the momentum will keep it
turning. After the voltage is shut ofT, the momentum
will gradually wear ofT due to friction. If the application
does not require an abrupt stop, then by removing the
driving voltage, the motor can be brought to a gradual
stop.
An abrupt stop may be essential to an application
where the motor must run a few turns and stop very
quickly at a predetermined point. This could be
achieved by electrical braking.
Electrical braking is done by reversing the direction of
the motor. In order to run in reverse direction, the motor has to stop first, at which time the driving voltage is
eliminated so that the motor does not start in the new
direction. Therefore the length of time that the reversing voltage is applied must be precisely calculated to
ensure a quick stop while not starting it in the reverse
direction.
There is no simple formula to calculate when to start,
and how long to maintain braking. It varies from motor
to motor and application to application. But it can be
perfected through trial and error.
In a closed loop system, the feedback can be used to
determine where or when to start braking and when to
discontinue.
During the electrical braking, or any time that the motor is being reversed, it draws its maximum current. To
a motor which is turning at any speed, reversing is a
heavy load. The current demand of a motor, when it
has been reversed,is much higher than when it has just
been powered on.
The following shows a ,code sample for electrical braking on a DC motor. The code is designed for the hardware shown in Appendix A. The subroutine DELAY
provides the period that the reverse voltage is applied to
the motor. The code for this subroutine is available in
the TIME DELAYS section of this document.
BEGIN:
MOV
MOV
SETB
CMOD,#O
CCAPM1,#42H
CR
DRIVE MOTOR CLOCKWISE
CLR
Pl.O
MOV
CCAP1H,#00
SET PCA TIMER INPUT fOSC/12.
SETTING THE MODULE TO PWM'MODE.
PCA TIMER RUN.
Pl.O AND THE PWM OF MODULE 1CONTROL THE SPEED AND DIRECTION.
00 IN THIS REGISTER PUTS OUT MAX PWM (LOGICAL 1)
CALL
STOP_MOTOR
STOP_MOTOR:
SETB'
MOV
CALL
CLR
RET
Pl.O
CCAP1H,#OFFH
DELAY
Pl.O
REVERSING THE MOTOR.
WAITING FOR 0.5 SECOND.
REDUCING VOLTAGE TO O.
RETURN FROM SUBROUTINE.
2-295
inter
AP-425
STEPPING A DC MOTOR
Using the 83C51FA, it is possible to run a simple DC
. motor in small steps. The resolution of the steps will be
as high as the resolution of the encoder. If this resolution is sufficient, here is a technique to run a DC motor
in steps.
Using a gear box to gear down the motor wiII increase
the resolution of steps. However, putting too much load
through the gears wiII cause sluggish starts and stops.
Electrical braking is used in order to stop the motor at
each step. Therefore, the routine that runs the motor in
steps will consist or turning it on with full force, waiting
for certain period, and stopping it as fast as possible.
The wait period depends on the number of steps per
revolution.
As the steps and the intervals between them become
smaller, the average current demand of the motor increases. This is· because the motor is operated at its
maximum torque condition every time it starts to rotate
and every time it is reversed for electrical braking.
The following code sample shows a continuous loop
which runs the motor in steps. The number of steps per,
revolution depends on the duration of the delay generated by DELAY subroutine. Subroutine WAIT pro- '
vides the time between the steps.
Subroutine DELAY is the period of time that the motor is kept in reverse. This period must be determined
through trial and error for each type of motor and system.
TIME DELAYS
While the 83C51FA is controlling a motor it must frequently wait for the motor to move to certain position
before it can proceed with the next task. For example,
in the case of electrical braking when the controller
reverses the polarity of voltage across the motor, depending on the type, size, and the speed ofthe motor, it
may have up to a second of CPU time before it will
tum the motor off.
The wait may be implemented in different ways. Any of
the Timer/Counters or unused PCA modules could be
utilized to provide accurate timing. The advantage in
using the timers is that while the timer is counting, the
processor can be taking care of some other tasks. When
the timer times out and generates an interrupt the processor will go back and continue servicing the motor.
If there are no timers or PCA modules available for this
purpose, a ,software timer maybe set up by decrementing some of the internal registers. In this method the
processor will be tied up counting up or down and will
not be able to do anything else. An example of such a
timer is:
LOOP:
CLR
MOV
PLO
CCAP1H,#0
SET DIRECTION CLOCKWISE
MAX PWM
The above instruction sets the motor running clookwise. The controller can
be dOing other tasks if need be. or just stay in a wait loop, then stop the
motor as shown below.
SETB
MOV
CALL
CLR
CALL
JMP
PLO
CCAP1H,#OFFH
DELAY
Pl.O
WAIT
LOOP
; REVERSING THE MOTOR.
" WAIT FOR IT TO STOP.
REDUCE VOLTAGE TO O.
TIME BEFORE NEXT STEP.
2·296
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AP-425
DELAY:
MOV
MOV
DELALLOOP:
DJNZ
DJNZ
RET
R4,#25
R5,#255
(decimal)
(decimal)
R5,DELALLOOP
R4,DELALLOOP
Subroutine DELAY provides approximately 6.4 ms
with a 12 MHz clock or 4.8 milliseconds with a 16
MHz clock. The length of this delay can be controlled
by loading smaller or larger values to R4 to vary from
260 microseconds up to 65 milliseconds at 12 MHz or
48 milliseconds at 16 MHz oscillator frequency. Larger
delays may be obtained by cascading another register
and creating an outer loop to this one.
ORG
JMP
OBH
TIMER_INTERRUPT_ROUTINE
CLR
MOV
PLO
CCAPlH,#O
Let us assume that it will take a motor 500 milliseconds
to stop from its CW rotation and we are going to use
Timer/Counter 0 to provide the wait period. Subroutine DELAY 1 will keep track of this timing. Module 1
of PCA is selected to provide the PWM.
SET DIRECTION CW
MAX PWM
Now the motor is running and the controller can do other tasks.
Some typical tasks are called in the following segment.
BUSLLOOP:
CALL
CALL
CALL
JNB
MONITOR_DISPLAY
SCAN_KELBOARD
SCAN_INPUT_LINES
STOP_FLAG, BUSY_LOOP
STOP_FLAG gets set by a feedback signal and denotes that the motor must
stop.
SETB
MOV
CALL
CLR
PLO
CCAPlH,#OFFH
DELAY
PLO
SETB
SETB
MOV
MOV
EA
ETO
TLO,#OD8H
THO,#5EH
REVERSING THE MOTOR
WAIT TILL MOTOR STOPS
REDUCE VOLTAGE TO 0
DELAY!:
enable timer 0 interrupt
2-297
intJ
Ap·425
SETB
MOV
TRO
R7,#8
timer 0 on
keep track of how many times
; timer 0 must rollover
continue' performing other tasks
MONITOR_LOOP:
CALL
CALL
CALL
JB
MONITOR_DISPLAY
SCAN_KEY-BOARD
SCAN_INPUT_LINES
TRO,MONITOR_LOOP
RET
TIMER_INTERRUPT_ROUTINE:
DJNZ
R7,FULL_COUNT
CLR
TRO
RETI
To implement a SOO milliseconds delay, timer 0 is used
here. In mode 1 timer 0 is a 16-bit timer which takes
6S.S35 milliseconds at 12 MHz to roll over. Dividing
SOO milliseconds to 6S.S3S shows that timer has to
overflow more than 7 times but less than 8 times. How
much more than 7 times? The following calculation
yields the initial load value of the timer.
500 + 65.535 = 7.2695 taking it backward
65.535 x 7 = 458.745 milliseconds
500 - 458.745 = 41.255 milliseconds or 41255
microseconds.
In hexadecimal it is A127H. The initial load value is
the complement of this value which is SED8H.
CONCLUSION
The 83C51FA with all its on-chip peripherals is a system on one chip. It can simplify the design of a control
board imd reduce the chip count. Up to 5 DC motors
can be controlled while doing other tasks such as monitoring feedback lines, human interfacing (scanning a
keyboard, displaying information), and communicating
with other processors. The MCS-51 powerful instruction set provides maximum flexibility with minimum
hardware.
With its onboard program memory capability, the need
for the external EPROM and address latch is eliminated. The 83C51FA can have up to 8K bytes of code and
the 83C51FB can have up to 16K bytes of code onboard.
This microcontroller can be used in industrial, commercial, and automotive applications.
2-298
infef
Ap-425
APPENDIX A
Figure A-I shows a symbolic view of the L293B ddver.
This driver has 4 channels but only two are shown here.
Note the inputs A and B and how they are related to
each other. You can input the PWM to either one of
the inputs and by toggling the other input start or stop
the motor. While running, the PWM input controls the
speed. Pin PIA corresponds to module I of the peA,
and pin Pl.O is used as a regular I/O pin.
Figure A-2 shows the schematic of the motor driver,
motor, feedback path, and the supporting components.
. L293B
...n.n...
PWM (P1.4)
Port Pln(P1.0)---F-4
AB
j-1.
~H--.....:=r-
~+--i~ When A =B, motor stops
('
Clockwise
~
off
When A .. B, motor runs
off
Counter Clockwise
Figure A-1. The L293B Motor Driver
2-299
270622-6
AP-425
J: vee
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270622-7
All diodes are the same and could be any of the 1N4000 series.
Figure A-2. Full Schematic of a Motor-Control System
2-300
AP-429
APPLICATION
NOTE
March 1989
Application Techniques for the
83C152 Global Serial Channel
in CSMA/CD Mode
BOB JOHNSON
Embedded Control Applications Engineering
© Intel Corporation, 1989
Order Number: 270720-001
2-301
inter
AP-429
INTRODUCTION
.The 83Cl52 is an 80C5IBH based microcontroller with
DMA- capabilities and a high speed, multi-protocol,
'synchronous serial communication interface called the
Global Serial Channel (GSC). The GSC uses packetized data frames that consist of a beginning of frame
(BOF) flag, address byte(s), data byte(s), a Cyclic Redundancy Check (CRe), and an End Of Frame (EOP)
flag. An example of this type of packet is shown in
Figure 1. Most 80Cl52 users will be familiar with
UARTs, another type of serial interface. Figures I and
2 compare the two types of frames. The UART uses
start and stop bits with a data byte between as shown in
Figure 2. .The 83Cl52 retains the standard MCS®-51
UART.
The 83Cl52 will be referred to as the "CI52" throughout this application note to refer to the device. This
:,J,~
I
application note deals with initializing and running the
GSC in CSMA/CD mode only. Carrier Sense Multiple
Access with Collision Detection (CSMA/CD) is a communication protocol that allows two or more stations to
share a common transmission medium by sensing when
the link is idle or busy (Carrier Sense). While in the
process ,of transmission, each station monitors its own
transmission to identify if and when 'a collision occurs.
When a collision occurs, each station involved in the
transmission executes a backoff algorithm and reattempts transmission (Collision Detection). This access
method allows all stations an equal chance to transmit
its own packet and thus is referred to as a "peer-topeer" type protocol (Multiple Access). Even in
CSMA/CD mode, the user has several variations that
can be implemented. Table I summarizes the various
CSMA/CD options available. Most of these variations
will be discussed in this application note.
?",I", X'-------r-,~-r;rr
BOF
'--_-v-_1~8,
8, 32, 64 BITS
I
16 BITS
DATA
,
EOF
I
16,32 BITS
I
ANY NUMBER OF OCTETS
2 BITS
270720-1
Figure 1. Packetized Frame
STOP
BIT
270720-2
Figure 2. UART Byte
2-302
infef
Ap·429
Table 1. CSMA/CD Variations Supported by C152
Options Supported by Hardware
CSMAlCD Parameter
Preamble
a·Bits
32-Bits
Acknowledgement
Hardware
Software
Backoff Algorithm
Normal
Alternate
CRC
16-Bit
32-Bit
Address Recognition
a-Bit
16-Bit
Address Masking
a-Bit
16-Bit
64-Bits
Deterministic
S/W Extendable
Jam Type
D.C.
CRC
GSC Servicing
CPU
DMA
Data Source (Transmitter)
External RAM
Internal RAM
SFR
Data Destination (Receiver)
External RAM
Internal RAM
SFR
GSC Interface
Direct
Buffers
Baud Rate
1.709 KPBS (minimum)
2.062 MPBS (maximum)
# Collisions Permitted
o to a
# of Slots (Deterministic Only)
1 to 63
Time Slot
1 to 256 BITs
IFS
2 to 256 BITs
In this application note initializing the GSC is covered
first. Starting, maintaining, and ending transmissions
and receptions will then be discussed. Included in these
sections will be how interrupts are generated, the software needed to respond to interrupts, and restarting the
process. There are four interrupts used in conjunction
with the GSC. They are: Transmit Valid, Transmit Error, Receive Valid, and Receive Error. A complete software example is shown in Appendix A. Included in the
software are comments describing what and why certain sections of code are needed.
Figures 3 and 4 are flow charts that show the entire
process of using the C152 GSC under CPU or DMA
control. Both flow charts begin with initialization
which is described in the next section. Each step in the
flow charts will be described. In general, the text combines CPU and DMA control of the GSC and discusses
pros and cons of each.
These flow charts were created from lab experiments
performed with the C152. The purpose of the lab experiments was to implement a CSMA/CD link, over
which data could be passed from one station to another.
As a source for data to transmit and a method to display the data received, two terminals were used. Connecting two terminals together would not normally be
encountered in an actual application. However, connecting two terminals together provided a convenient
configuration on which to develop the necessary software. Connecting two terminals also created a base
from which the user could implement many different
designs utilizing the s~ftware provided in Appendix A.
The final experiment consisted of two parts: 1) data
received by the UART to be transmitted by the GSC
and 2) data received by the GSC to be transmitted by
the UART. In both cases a terminal was connected to
the UART on each C152 and the GSC was under
DMA control. There were eight external 120 byte buffers available. Four buffers were used to store the data
received by the UART and four buffers used to store
the data received by the GSC.
As data is received from the UART each byte is examined, placed in an external buffer and a counter incremented. Each byte is examined to see if it equals an
ASCII "carriage return" (ODH). If a match occurs, the
program assumes it is the end of a line and the end of
the current huffer. Once a carriage return is detected, a
line feed is added and the byte count incremented. The
counter is then used to load the byte count register for
the appropriate DMA channel. Once a buffer is closed
it's flagged as having data available for the GSC to
transmit. If the next buffer was not filled with data
waiting to be transmitted by the GSC, it is made available for receiving the next line. Once the GSC transmits
the entire packet the buffer is flagged as empty and
available for storing new data from the UART.
When a packet is received by the GSC, the data is
placed in an external buffer. When the packet ends, the
2-303
inter
AP-429
number of bytes received is calculated. The current
buffer is marked to indicate that the data is ready for
output by the UART. The calculated byte count is used
to identify how many bytes the UART should send to
the terminal. When the UART sends the proper number of bytes, the buffer is made available so that the
GSC may store data in it.
This has all been subjected to limited testing in the lab
and verified to work with two terminals. The software
has only been developed to the point that the terminals
may display each other's outgoing messages and no farther. This means that some error conditions are not
resolved with the current version of the software. For
instance, if two terminals transmit data at approximately the same time, both messages may be displayed, even
if the received data occurs within the middle of a sentence being typed. For reasons such as this, the software and hardware presented should not be used for a
production product without thorough testing in 1;l!e actual application.
CPU Only
270720-3
Figure 3. GSC CPU Flow Chart
2-304
AP-429
N
RET!
270720-4
Figure 3. GSC CPU Flow Chart (Continued)
2·305
AP-429
270720-5
270720-6
Figure 3. GSC CPU Flow Chart (Continued)
2-306
AP-429
MAIN
PROGRAM
270720-7
Figure 4. GSC DMA Flow Chart
2-307
intJ
AP-429
REC VALID INT
REC ERROR INT
270720-8
Figure 4. GSC DMA Flow Chart (Continued)
2-308
inter
XMIT VALID INT
AP-429
G
RETI
270720-9
270720-10
Figure 4. GSC DMA Flow Chart (Continued)
2-309
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AP-429
GSC INITIALIZATION
During initialization, user software sets up the hardware in the GSC so that communication may begin and
institute the parameters specified by the protocol.' This
can further be sub-divided into two more sections. The
first deals with those items which will vary according to
the protocol being implemented, referred to as protocol
dependent. The second section deals with those items
that need to be accomplished in the same manner regardless of the protocol and are referred to as protocol
independent. Table 2 shows those items of initialization
which are protocol dependent. Once set up, the items in
Table 2 do not have to be repeated when starting a new
reception or transmission.
Table 2. Protocol Dependent Initialization
baud rate
preamble length
backoff mode (random or deterministic)
CRC
interframe space (IFS)
type of jamming signal used
slot time
addressing
enabling Hardware Based Acknowledge (HBA)
This section deals with those items which are part of
initialization which vary according to the protocol being implemented. These parameters will typically be
dictated by rules of the protocol or hardware environment. In addition, some parameters will vary according
to the software implemented by the programmer. For
instance, interframe space (IFS) is one of the parameters dependent on other software developed to implec
ment a protocol with the C152.
BADD RATE-When initializing the GSC baud rate
there are two major considerations. The first is that the
GSC baud rate can only be programmed in multiples of
118 the osciJIator frequency when using the internal
baud rate generator as shown in the formula given below. If a 1 MBPS rate is desired, the oscillator frequency must be 16 MHz or 8 MHz. This becomes less critical when the GSC baud rate is much lower than the
desired oscillator frequency.
GSC
baud rate
=
Fosc
(BAUD + 1) x 8
UART baud rate _
(Mode 3)
Table 2 introduces two new terms that previous
CSMA/CD users may not be familiar with; Hardware
Based Acknowledge (HBA) and Deterministic Collision Resolution (DCR). HBA is a method in which the
GSC receiver hardware will acknowledge the reception
of a valid frame and DCR is a collision resolution algorithm in which the user assigns a specific slot number
to each station on the link. HBA will be covered in its
own section, located later in this document. For a description on DCR or more information on HBA, please
refer to the 83CI52 Hardware Description in the 8-bit
Embedded Controller Handbook (order # 270645).
Table 3 shows items which are protocol independent.
All of the items in Table 3, except for determining how
the GSC is controlled, will need to be repeated after
each GSC operation, before a reception or transmission
starts again,
Table 3. Protocol Independent Initialization
INITIALIZATION
(PROTOCOL DEPENDENT)
(2 smod ) {Fosd
(256 - TH1) x 384
The second major consideration only matters if the
DART· is used. In this case, when deciding on GSC
baud rate and oscillator frequency the effect on the
DART baud rate must be understood. As shown in the
formula above, when using a timer in mode 3, baud
rates generated for the DART are in multiples of 11384
the oscillator frequency. This means that standard
DART baud rates such as 9600, 2400, 1200, etc. and
common GSC baud rates such as 2 MBPS, 1 MBPS,
and 640 KBPS, cannot be reached with any single oscillator frequency. This can be worked around with methods such as externally clocking the timers. Externally
clocking the GSC cannot be done when CSMA/CD is
selected. For instance, the maximum oscillator frequency that can be used to ~chieve a standard DART baud
rate of 9600 is 14.7456 MHz, which works out to a
maximum GSC baud rate of 1.8432 MBPS which can
be further divided down by multiples of 8. The program
example in Appendix A uses these values.
clearing the collision counter register
control of the GSC
initializing DMA (only if used)
initializing counters and pointers
enabling the receiver and receive interrupts
enabling the transmitter and transmit interrupts
2-310
AP-429
To select a desired baud rate, the Special Function Register BAUD is loaded with an appropriate number according to the previously given formula. For instance:
MOV BAUD,#O
;selects a baud rate
;of 1/8 the oscillator
;frequency
or:
MOV BAUD,#l
;selects a baud rate
;of 1/16 the oscillator
;frequency
at the other extreme:
MOV BAUD,#OFFH ;selects a baud rate
;of 1/2048 the
;oscillator frequency
;(7.2K @ 14.7456 MHz)
PREAMBLE LENGTH-A preamble serves four
functions in CSMA/CD mode: to provide synchronization for the following frame, to contain the Beginning
Of Frame flag (BOF), to let other stations on the link
know that the link is being used, and to provide a window where collisions may occur and automatically reattempt transmission (backofl). Figure S shows what an
eight-bit preamble would look like.
The ClS2 receiver will synchronize to the first transition and resynchronize on every following transition.
For this reason a minimum preamble length can be
used. On the ClS2 the minimum preamble length is 8bits. However, due to network topography, other devices used, or the protQcol being implemented, a larger
number of transitions may be required. In these cases
the ClS2 can be programmed for either a 32- or 64-bit
preamble.
To select an 8-bit preamble:
GMOD = XXXXXOlX
BACKOFF MODE-The CI52 has three types of
backoff modes: Normal Backoff, Alternate Backoff,
and Deterministic Backoff. Normal backoff and alternate backoff are very similar and the only difference
between them is when the slot timer begins counting
time slots.
In normal backoff each station randomly chooses a slot
based on the number of collisions that have previously
occurred. After the idle (EOF) is detected, the interframe space timer and slot time timer begin at the same
time. Since all devices are prevented from beginning a
transmission during the interframe space, that amount
of time is taken away from a device which has chosen
slot O. When a slot time is significantly larger than the
interframe space, this should pose no problem as slot 0
will still provide a window for the device to begin transmission. There is a problem when the interframe space
is larger than the slot time. In this case, if a device
chooses slot 0, it will not be allowed to transmit because
the interframe space has not yet expired. This decreases
efficiency of the backoff algorithm and reduces bandwidth. Normal backoff should be used when the slot
time is greater than the interframe space period.
In alternate backoff, after the idle is detected, only the
interframe space timer begins. When the interframe
space timer expires, the slot time timer begins. This
results in extending the total !jmount of time spent in
the backoff algorithm but preserves the entire amount
of time for each slot that may be selected. Alternate
backoff is recommended when the slot time is less than
or equal to the interframe space period.
The deterministic backoff mode is a new resolution
mode introduced by the CIS2. Deterministic backoff
utilizes peer-to-peer communication while in normal
transmission mode, and a prioritized or a deterministic
algorithm while performing the resolution. Deterministic backoff operates by following standard CSMA
rules when attempting to transmit a packet for the first
time. However, if a collision is detected each station is
To select a 32-bit preamble:
GMOD = XXXXXIOX
To select a 64-bit preamble:
GMOD = XXXXXIIX
tii~
~
~tii '
'.
h""
WAVEFORM
LOGIC
LEVEL
10101011
Figure 5. 8-Bit Preamble (also HBA Waveform)
2-311
270720-11
infef
AP-429
restricted to only transmit during its assigned slot. The
slot number is assigned by the user and up to 63 slots
are available. A more detailed description on deterministic backoff is in the 80CI52 Hardware Description
chapter in the 8-bitEmbedded Controller Handbook.
Deterministic backoff is recommended if there are 64
stations or less in a network and the user wishes to
remove the uncertainty that arises when using one of
the other two r~ndom resolution methods already described. Another reason for using deterministic resolution is if a user wishes to assign a priority to one station's messages over that of another station's during the
collision resolution period. The user should be aware
that most CSMA/CD protocols that already have standards associated with them preclude the use of deterministic backoff.
To select normal backoff:
OMOD = XOOXXXXX
MYSLOT = XOXXXXXX
To select alternate backoff:
OMOD = XIIXXXXX
MYSLOT = XOXXXXXX
To select deterministic backoff:
OMOD = XIIXXXXX
MYSLOT = XIXXXXXX
CRC-The C 152 offers a choice of two types of CRC.
One type of CRC is CRC-CClTT (16-bit) used in
HDLC (Reference I). The second CRC available is
named AUTODIN-II (32-bit) which is used in 802.3
(Reference 2). The following formulas give the CRC
generating polynomial of each.
CRC-CCITT
=
Xl6 + 'X12 + XS +
AUTODIN-II = X32 + X26 + X23 +
X22 + Xl6 + Xl2 +
Xll + X10 + X8 +
X7 + XS + X4 +
X2+X+I
INTERFRAME SPACE-The interframe space provides a period of time for the receiver and physical medium to fully recover from a previous reception and be
prepared to accept a new message. To fulfill these requirements the value programmed into IFS should be
greater than or equal to the "turn around" time pluS
round trip propagation time. "Turn around" time is the
amount of time it takes for a receiver to be re-enabled
after having just received a previous packet. Calculating worst case turn around time is very complicated
when the OSC is under CPU control. This is because
the Receive Done bit (RDN), which signifies the end of
a received packet, does not generate an interrupt. The
user is required to periodically poll Receive Done to
ascertain when incoming packets are complete. Since
the polling sequence is sometimes altered by interrupts,
these delays must also be taken into account when deciding what interframe space will be used. As an alternative, the user could choose to set-up a timer that will
periodically poll the receive done bit and give a more
reliable idea of what the turn around time will be. This
will require that the timer interrupt be assigned a higher priority than any of the other interrupts. Since the
RDN bit will be set approximately two bit times after
the last CRC bit is received, in some situations it is
possible to add a delay to a receive valid interrupt and
check Receive Done just prior to leaving the routine.
As a last resort a user could ignore the maximum response time and instead pick a number that works most
of the time. The only negative result of doing this is
that some frames may be missed. If acknowledgements
are used, that frame would be retransmitted. However,
if acknowledgements are not used, the data would be
lost forever.
The programming quantum for interframe space is in
bit times where a bit time is equal to Ilbaud rate. The
only hardware restrictions the CI52 places on interframe space is that the number programmed must be
even and the maximum value is 256 bit times. Other
than that, the user can decide what interframe space
value will be used. The interframe space should be the
same for all stations on any given network.
The selection of which CRC to use is normally dictated
by the protocol being implemented. When selecting a
CRC, the user should remember that the CRC length
also determines the jam time, which in tum will affect
the slot time.
To program the interframe space:
IFS = nnnnnnnO
To select the 16-bit CRC:
OMOD = XXXXOXXX
The following two examples show the actual code the
C152 will execute in response to a receive interrupt.
Only those portions of the code associated with servicing the interrupt are shown. Added to this software, on
the left edge, is the number of machine cycles it takes to
execute each instruction. With this extra information
the required interframe space can be calculated by totaling the number of machine cycles.
To select the 32-bit CRC:
OMOD = XXXXIXXX
where nnnnnnnO = number of bit times programmed
by the user.
2-312
inter
AP-429
The first example gives the flow used for a valid GSC
reception and the other example shows the steps taken
to service an invalid reception. These examples were
created by first implementing a· working prototype.
Once completed, the software used to service the appropriate interrupt was pulled out, selecting the worst case
(longest) flow. Finally, each step was sequentially
pieced together to demonstrate how the application
services an interrupt. These software fragments are taken from the program in Appendix A.
The total number of machine cycles it takes to service a
valid reception (59 cycles) or an invalid reception (115
cycles) is also given. As shown, an invalid reception
takes the longest amount of time to service. To 115
cycles we add maximum interrupt latency, which is 9
machine cycles. The total comes out to be 124 machine
cycles. It should be mentioned that the typical interrupt
latency in the Cl52 would be about 5 machine cycles.
A 9 machine cycle latency can only occur if the interrupt happens during an access to an interrupt register
followed by a multiply or divide instruction and assumes that the receive error interrupt is the only high
priority interrupt.
A bit time works out to be 8 oscillator periods
(BAUD = 0) in this example. To calculate the number
to load into IFS the following formula is used. "12"
comes about from the 12 oscillator periods that make
up a machine cycle.
IFS = 12 X (# of machine cycles to service the interrupt)
(# of oscillator periods per bit time)
This works out to be:
(12 x 124)/8 = 186
This number should have a guardband added in case
minor changes must be made in the routines. Since the
only other enabled interrupt is the UART, a small
guardband of 10 was used. The interframe space chosen
is 196.
2-313
AP·429
(# of
machine
cycles
LOC
002B
(2)
002B
(2)
(2)
(2)
(2)
(2)
0568
056A
056C
056E
0570
(2)
03BO
(2)
03F6
(2)
(2)
(2)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(2)
(2)
(2)
03F9
03FC
03FF
0402
0403
0405
0407
0408
040A
040C
040E
0411
0414
(2)
(2)
(2)
(2)
(2)
0432
0435
0438
043B
043E
(1)
(2)
(2)
(2)
(2)
(2)
(2)
'0572
0575
0577
0579
057B
057D
057F
LINE
358
359
020568
360
361
1680
C082
1682
1683
C083
COEO
1684
CODO
1685
7lBO
1688
1689
1031
207343 1064
1067
1168
20721E 1170
1172
1173
2074F6 1175
758200 1179
758303 1180'
C3
1184
7476
1186
95F2
1192
FO
1194
D275
1197
D272
1202
D273
1203
757981 1206
757803 1207
020432 1211
1212
1251
8579D2 1253
8578D3 1254
75F300 1258
75F278 1259
22
1261
1263
439301 1693
D2E9
1695
DODO
1697
DOEO
1698
D083
1699
D082
1700
32
1702
OBJ
SOURCE
ORG 2BH
GSC_REC_VALID:
JMP GSC_VALID_REC
GSC_VALID_REC:
PUSH DPL
PUSH DPH
PUSH ACC
PUSH PSW
CALL NEW_BUFFER2_IN
NEW_BUFFER2_IN:
JB GSC_IN_MSB,GSC_IN_2
GSC_IN_2D_2A:
JB GSC_IN_LSB,GSC_IN_2
GSC_IN_2D:
JB BUF2D_ACTIVE,BUFFER
MOV DPL,#LOW (BUF2C_ST
MOV DPH,#HIGH (BUF2C_S
CLR C
MOV A,#(MAX_LENGTH) SUBB A,BCRLl
MOVX @DPTR,A
SETB BUF2C_ACTIVE
SETB GSC_IN_LSB
SETB GSC_IN_MSB
MOV GSC_INPUT_LOW,#LOW
MOV GSC_INPUT_HIGH,#HI
JMP NEW_BUF2_IN_END
NEW_BUF2_IN_END:
MOV DARL1,GSC_INPUT_LO
MOV DARH1,GSC_INPUT_HI
MOV BCRH1,#0
MOV BCRL1,#MAX_LENGTH
RET
ORL DCON1,#01
SETB GREN
POP PSW
POP ACC
POP DPH
POP DPL
RETI
59 TOTAL CYCLES
Example 1. GSC Receive Valid Service Routine
2-314
AP-429
(# of
machine
cycles
LOC
0033
OBJ
(2)
0033
020580
(2)
(2)
(2)
(2)
0580
0582
0584
0586
C082
C083
COEO
CODO
(2)
0588
30EE07
(2)
0592
30EF07
(2)
(2)
(2)
059C
059F
05A1
30EC07
78E7
5175
(I)
(1)
0275
0276
D3
7F06
(1*6)
(1*6)
(1*6)
(1*6)
(2*6)
(2)
0278
0279
027B
027C
027D
027F
E6
3400
F6
18
DFF9
4001
(2)
0282
22
(2)
0281
22
(2)
05A3
0205AA
(2)
05AA
71BO
(2)
03BO
207343
(2)
03F6
20721E
LINE
362
363
364
365
1703
1705
1706
1707
1708
1735
1736
1737
1744
1745
1746
1753
1754
1756
1758
1759
560
562
564
565
566
568
570
572
574
576
578
588
589
591
592·
587
588
1760
1761
1767
1772
1773
1031
1063
1064
1168
1170
1171
SOURCE
ORG 33H
GSC_REC_ERROR:
JMP GSC_ERROR_REC
GSC_ERROR_REC:
PUSH DPL
PUSH DPH
PUSH ACC
PUSH PSW
RCABT_CHECK:
JNB RCABT,OVR_CHECK
OVR_CHECK:
JNB OVR,CRC_CHECK
CRC_CHECK:
JNB CRCE,AE_CHECK
MOV ERROR_POINTER,#CRC
CALL INCREMENT_COUNTER
INCREMENT_COUNTER:
SETB C
MOV R7,#6
INC_COUNT_LOOP:
MOV A,@ERROR_POINTER
ADDC A,#O
MOV @ERROR_POINTER,A·
DEC ERROR_POINTER
DJNZ R7,INC_COUNT_LOOP
JC COUNTER_OVERFLOW
COUNTER_OVERFLOW:
RET
RET
JMP REC_ERROR_COUNT_END
REC_ERROR_COUNT_END:
CALL NEW_BUFFER2_IN
NEW_BUFFER2_IN:
JB GSC_IN_MSB,GSC_IN_2
GSC_IN_2D_2A:
JB GSC_IN_LSB,GSC_IN_2
Example 2. GSC Receive Error Service Routine
2-315
AP-429
(# of
machine
cycles
LOC
OBJ
(2)
(2)
(2)
(1)
(1)
(1)
(2)
(1)
(1)
(1)
(2)
(2)
(2)
03F9
03FC
03FF
0402
0403
0405
0407
0408
040A
040C
040E
0411
0414
2074F6
758200
758303
C3
7476
.95F2
FO
D275
D272
D273
757981
757803
020432
(2)
(2)
(2)
(2)
(2)
0432
0435
0438
043B
043E
8579D2
8578D3
75F300
75F278
22
(2)
(1)
(2)
(2)
(2)
(2)
(2)
05AC
05AF
05Bl
05B3
05B5
05B7
05B9
439301
D2E9
DODO
DOEO
D083
D082
32
LINE
1172
1173
1175
1179
1180
1184
1186
1192
1194
1197
1202
1203
1206
1207
1211
1212
1251
1253
1254
1258
1259
1261
1262
1774
1776
1778
1779
1780
1781
1783
SOURCE
ORG 33H
GSC_IN_2D:
JB BUF2D_ACTIVE,BUFFER
'MOV DPL,#LOW (BUF2C_ST
MOV DPH,#HIGH (BUF2C_S
CLR C
MOV A,#(MAX_LENGTH) SUBB A,BCRLI
MOVX @DPTR,A
SETB BUF2C_ACTIVE
SETB GSC_IN_LSB
SETB GSC_IN_MSB
MOV GSC_INPUT_LOW,#LOW
MOV GSC_INPUT_HIGH,#HI
JMP NEW_BUF2_IN_ENP
NEW_BUF2_IN_END:
MOV DARLl,GSC_INPUT_LO
MOV DARHl,GSC_INPUT_HI
MOV BCRHl,#O
MOV BCRLl,#MAX_LENGTH
RET
,
ORL DCONl,#Ol
SETB GREN
POP PSW
POP ACC
POP DPH
POP DPL
RET I
115 TOTAL Cycles
Example 2. GSC Receive Error Service Routine (Continued)
JAMMING SIGNAL-The purpose of a jam is to insure all stations on link detect that a collision has
occurred and reject that frame. To meet this need, the
C152 offers two types of jamming signals. One type of
jam is the D.C. jam (Figure 6) and another type is
called the CRC (Figure 7) jam. A jam is forced by the
TxD pin after a collision is detected but after the preamble ends if the preamble is not yet complete. The
D.C. jam forces a constant logic "0" for a period of
time equal to the CRC length. The CRC jam takes the
CRC calculated up to the point when a collision occurs,
complements the CRC, and transmits that pattern. The
CRe jam should be used when A.C. coupling is used in
a
a network. AC. coupling normally implies that pulse
transformers or capacitors are used to connect to the
serial link. In these types of circuit interfaces, the D.C.
jam may not be passed through reliably. One drawback
of the CRC jam is that it does not always guarantee
that all stations on a link will detect the jamming signal
as there are no Manchester code violations inherent in
the waveform. The D.C. jam is recommended whenever
it can be used since this type of jam will always be
detected by forcing Manchester code violations. Some
protocols specify
specific type of jam signal that
should be used and the user will have to decide if the
Cl52 can fulfill- those requirements.
a
'"~
..
,
!:
~
,
D.C. JAM
,
J+-+++-+-I-+-+-+-+-I,-+-++-+':-+-I
270720-12
Figure 6. D.C. Jam
2-316
intJ
AP-429
...
:::l
;::
I::
'"
CRC JAM
CALCULATED CRC
:0: 1:0:0: 1:0: 1: 1:1:0:0: 1:0:0:0:0:
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
r
I
I
I
I
I
I
I
I
I
I
INVERTED CRC
:1:0: 1:1:0: 1:0:0:0: 1': 10: 1:1:1: 1
I
I
I
I
I
I
I
I
I
I
L
I
I
I
I
I
I
I
JAM WAVEFORM
270720-13
Figure 7. CRC Jam
When transmitting, the user must insert a destination
address in the frame to be transmitted. This is done by
loading the appropriate address as the first byte or two
bytes of data. If a source (sending) address is also to be
sent, the user must place that address into the proper
position within a packet according to the protocol being
implemented.
To select D.C. jam:
MYSLOT = lXXXXXXX
To select CRC jam:
MYSLOT = OXXXXXXX
SLOT TIME-In CSMA/CD networks a slot time
should be equal to or larger than the sum of round trip
propagation time plus maximum jam time. The slot
time is used in the backoff algorithm as a rescheduling
quantum. The slot time is programmed in bit times and
in the C152 can vary from 1 to 256.
To program the slot time:
SLOTTM = nnnnnnnn
ADDRESSING-When discussing the subject of addressing with respect to the C 152, the subject should be
broken down into three major topics. These topics are:
address length, assignment of addresses, and address
masking.
Address Length-The C152 gives a user a choice of
either 8 or 16 bits of address recognition. To select 8-bit
addressing the user must set the AL bit in GMOD to O.
Setting AL to 1 selects l6-bit addressing. Address recognition can be extended with software by examining
subsequent bytes for a match. The only part of the GSC
hardware that utilizes address length is the receiver.
The receiver uses address length to determine when an
incoming packet matches a user assigned address. Since
transmission of addresses is done under software control, the transmitter does not use the address length bit.
All bits following BOF are loaded into RFIFO, including address. The transmit circuitry is involved with addressing only if HBA is used. In this case, when HBA is
selected, the transmitter must know whether or not the
sending address was even or odd. Even addresses require an acknowledgement back and odd addresses do
not.
To select 8-bit addresses:
GMOD = XXXOXXXX
To select 16-bit addresses:
GMOD = XXXlXXXX
Address Assignment-When assigning an address to a
station, there are several factors to consider. To begin
with, there are four 8-bit address registers in the C 152:
ADRO, ADRl, ADR2, and ADR3. These registers are
initialized to 00 after a valid reset. For this reason it is
recommended that no assigned addresses should equal
O. Also, since there are four address registers, a user has
a minimum of two addresses which can be assigned to
each station when using 16-bit addressing or four addresses when using 8-bit addressing. Those registers not
used do not need to be initialized. When using 16-bit
addresses ADRl:ADRO form one 16-bit address and
ADR3:ADR2 form a second address. The C152 will
always recognize an address consisting of all Is, which
is considered a "broadcast" address. An address consisting of all Is should not be assigned to any individual
station.
2-317
There are many methods used to assign addresses.
Some suggestions are: reading of a switch, addresses
contained in actual program code, assignment by another node, or negotiated with the system. As mentioned earlier, if HBA is being used then the LSB of the
address must be 0 when acknowledgements are expect-
AP-429
ed. Since more than one address can be assigned per
station it is possible to use or not use HBA within the
same station. This would work by assigning one address
that would be even for when acknowledgements are required and another assigned address would be odd for
those occasions when acknowledgements are not needed.
To assign an 8-bit address:
ADRO
nnnnnnnn
=
and optionally:
ADRl
ADR2
ADR3
xxxxxxxx
yyyyyyyy
.zzzzzzzz
To assign a 16-bit address:
ADRO
.ADRl
nnnnnnnn (lower byte)
xxxxxxxx (upper byte)
=
and optionally:
ADR2
ADR3
yyyyyyyy (lower byte)
zzzzzzzz (upper byte)
=
where xxxxxxxx, yyyyyyyy, zzzzzzzz are addresses to
be assigned.
In this example there are 5 nodes (A, B, C, D, and E)
with up to' 4 common peripherals. The peripherals
are: terminals, keyboards, printers, and modems. Assuming 8-bit addressing, a specific address bit. is as- .
signed to each peripheral: bit I to terminals, bit 2 to
keyboards, bit 3 to printers, and bit 4 to modems.
Figure 8 shows how this addressing is mapped.
ADDRESS
I
I
BIT7
I
N.U.
BIT6
I
N.U.
I
BIT5
I
N.U.
I
I
BIT4
I
MODEM
I
BIT3
I
I
BIT2
.1
BIT1
I
KEYBOARD
PRINTER
I
TERMINAL
I
BITO
I
GROUP
ADDR
N.U. = NOT USED
Figure 8. Group Addressing Map
Bit 0 is used to differentiate between group addresses.
and individual addresses. If bit 0 = I, then the address is a group address, if bit 0 = 0, then the address
is an individual address. This also complies with the
HBA requirements if HBA is enabled. Table 4 defines
which stations have which peripherals..
The next step is to assign each station's address and
address mask, These are determined by the attached
peripherals. A I is 'placed in the address register bit
and address mask register bit if that station has an
appropriate device. A I in the address register is not
used since it is masked out, but will make it easier for
a person not familiar with this specific software to
follow the program.
Tab!e 4. Peripheral Assignment for Example 3
Station A:
Station B:
Station C:
Station D:
Station E:
Terminal, Keyboard
Printer, Modem
Terminal
Printer
Terminal, Keyboard, Printer, Modem
Address Mask
Address
BIT
A:
B:
C:
D:·
E:
I7 I6 I5 I4 I3 I2 I
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
1
0
0
0
1
1
1
0
1
0
1
I
0
I
1
1
1
1
1
EXAMPLE 3
2-318
I7 I6 I5 I4 I3 I2 I1 I
0
0
0
0
0
O.
0
0
0
0
0
0
0
·0
0
0
1
0
0
1
0
1
0
1
1
1
0
0
0
1
1
0
1
0
1
0
0
0
0
0
0
I
AP-429
Address Masking-The CI52 has two 8-bit address
mask registers named AMSKO and AMSKI. Bits in
AMSKO correspond to bits in ADRO and bits in
AMSKI correspond to bits in ADRI. Placing a I into
any bit position in AMSKn causes the corresponding
bit in ADRn to be disregarded when searching for an
address match.
An originating transmitter will expect and accept the
acknowledgment if:
To implement address masking:
AMSKO = nnnnnnnn
If a partial or corrupted preamble is received or the
preamble is not completed within the interframe space,
the NOACK bit is set by the station that originally
initiated transmission. HBA is a user selectable option
which must be enabled after a reset.
and optionally:
AMSKI = nnnnnnnn
where n = I for a "don't care address bit"
or n = 0 for a "do care address bit"
There are two main uses for the address masking capabilities of the C152. The first and simplest use is to
mask off all address bits. In this mode the CI52 will
receive all messages. This type of reception is called
"promiscuous" mode. The promiscuous mode could be
used where all traffic would be monitored by a supervisory node to determine traffic patterns or to classify
what information is being transferred between which
nodes.
A second use of. masking registers is to group various
nodes together. Typically, stations are grouped together
which have something in common, such as functions or
location. Another term used when discussing group addresses is "multi-cast" addressing. Example # 3 demonstrates how multi-cast addressing might be used.
Finally, to communicate with any station that has a
printer, the address 00001001 would be sent and stations B, D, and E would receive the data. There are
some limitations to using this type of scheme. Some of
the more obvious are: the number of groupings is limited to the number of address bits minus I, and it is not
possible to address those stations that have a combination of attached peripherals, e.g., those stations with
keyboards AND terminals. These problems can be
solved using more elaborate addressing schemes.
HBA-Hardware Based Acknowledge (HBA) is a
hardware implemented acknowledgment mechanism.
The acknowledgement consists of a standalone preamble. An example of a preamble is shown in Figure 5. An
acknowledgment will be returned by the receiver if:
• no hardware detectable errors are found in the
frame
• the address is an individual address (LSB = 0)
• the transmitter is enabled (TEN = I)
• HBA is set
• HBA is set
• the receiver is enabled (GREN = 1)
• the address sent out was an individual address
(LSB = 0)
The HBA method informs the original transmitter that
a packet was received with no detected errors which
saves the overhead and time that would normally be
required to send a software generated acknowledgment
for a valid reception. Some functions that other acknowledgment schemes implement yet are not encompassed when using HBA with a CI52 is to identify
packets which are out of sequ·ence or frames which are
of a wrong type.
To enable HBA:
RSTAT = XXXXXXXI
INITIALIZATION-PROTOCOL INDEPENDENT
Discussion so far has centered on those elements of initialization which will vary according to the protocol
being implemented. As such, the protocol in many cases will dictate what values to use for initialization. In
addition, there are some parameters set during initialization that will remain the same regardless of which
protocol is being implemented. There are also some parameters which may vary for reasons other than which
protocol is being used. These parameters are grouped
together to form the protocol independent initialization
functions. The following sections cover these elements
of initialization. The discussion of initialization parameters is complete when the text covering "Starting,
Maintaining, and Ending Transmissions" begins.
CLEARING COLLISION COUNTER-A transmission collision detect counter (TCDCNT) keeps track of
the number of collisions that have occurred. It does this
by shifting a I into the LSB for each collision that occurs during transmission of the preamble. When
TCDCNT overflows, the CI52 stops transmitting and
sets TCDT. Setting TCDT signals that too many collisions have occurred and can cause an interrupt. TCDT
also is set if a collision occurs after the GSC has accessed TFIFO. During normal transmission, TCDCNT
can be read by user software to determine the number
of collisions, if any, that have occurred. Before starting
the second and subsequent transmissions, it is possible
that TCDCNT already has bits shifted in from a previous transmission. This would cause TCDCNT to over-
2-319
AP-429
flow prematurely. In order to preserve the full bandwidth of 8 retransmissions, TCDCNT must be cleared
prior to beginning any new transmission.
To clear the collision counter:
TCDCNT = 0
CONTROL OF THE GSC-"Control of the GSC"
specifies how bytes are loaded into the transmitter
(TFIFO) and unloaded from the receiver (RFIFO). A
user has the choice of moving data to or from the GSC
under control of either user software or the DMA
channels.
CPU Control-CPU control is the simplest method of
servicing the GSC and allows the most control. The
major drawback to CPU control is that a significant
amount of time is spent moving data from the source to
the destination, incrementing pointers and counters,
checking flags, and determining when the end of data
occurs. In addition, how the GSC interrupts function
differs from when the GSC is under CPU control than
when the GSC is under DMA control. Under CPU
control, valid GSC interrupts occur when either RFNE
(Receive Fifo Not Empty) or TFNF (Transmit Fifo
Not Full) are set. The transmit error and most of the
receive error interrupts still function the same regardless of which type of control is used on the GSC. The
only difference in how receive error interrupts operate
is that the UR (UnderRun) bit for the receiver is operational when the GSC is under DMA control. UR is
disabled when under CPU control.
DMA Control-DMA control relieves the CPU of
much of the overhead associated with serving the GSC
and allows faster baud rates. However, the reader must
realize that more details about a "yet to be transmitted
packet" must be known to properly initialize the DMA
channels prior to starting a transmission. In some situations, especially at high baud rates, the user must take
into account DMA cycles that occur asynchronously
and without any user control or knowledge. This could
possibly disrupt other time critical tasks the CI52 is
performing. There may be no indication to a user that
other ongoing tasks are being interrupted by DMA cycles taking over the bus and momentarily stopping
CPU action.
When the DMA is used to service the GSC, the DMA
channels will also need to be initialized and the GSC
interrupts configured to operate in DMA mode. The
main advantages of using DMA control is time saved
and interrupts occur only when there is an error or
when the GSC operation (receive or transmit) is done.
This removes the necessity of continuously polling
RDN and TDN bits to determine when a GSC operation is complete.
One of the most important facts to remember when
deciding how to service the GSC is that unless the GSC
baud rate is relatively low compared to the CPU oscillator frequency, the only method that can keep up with
the receiver or transmitter is DMA control As a rule of
thumb, if a user is willing to use 100% of available
bandwidth of the CI52 and no other interrupts are enabled besides the GSC, the maximum baud rate works
out to be approximately 4.5% of the oscillator frequency. This is based on a 9 instruction cycle interrupt la- ,
tency, moving a byte of data, return from interrupt and
executing one more instruction before the next GSC
byte is transmitted or received. At an oscillator frequency of 16 MHz, this works out to 120K bits per
,second. There are many steps a user could take to increase the baud rate when the GSC is under CPU control as this scenario is only a simple situation using
worst case assumptions. Taking into account the
amount of time available for the CPU to service the
GSC as more tasks are required by the service routines
or the CPU would further lower the maximum baud
rate. For instance, if a user intended that GSC support
only took 10% of available CPU time, this would reduce the effective baud rate by a factor of ten, making
the maximum bit rate 12K. This 10% figure is an average over the period it takes to complete a frame. Situations might arise such that spurious GSC demand cycles would require much more than 10% of available
time for short intervals.
INITIALIZING DMA-Since CSMA/CD is selected,
it is by definition half-duplex. In half-duplex mode,
only one DMA channel is needed to service both transmitter and receiver. However, it is simpler and easier to
explain if both DMA channels are used. The following
text is written under an assumption that both DMA
channels will be used to service the GSC. Regardless of
whether the DMA channel is servicing the receiver or
transmitter, the DMA DONE interrupt generally
should not be enabled. Also, the DMA bit in TSTAT
must always be set. The GSC valid transmit and valid
receive interrupts occur when RDN or TDN is set.
This also eliminates a need to poll RDN or TDN to
determine when a reception or transmission has ended,
as is necessary when the GSC is under CPU control.
The DMA channel servicing the transmitter must have:
Destination Address ,: TFIFO (085H)
Increment Destination Address (IDA) = 0
Destination Address Space (DAS) = I
Demand Mode (DM) = I
Transfer Mode (TM) = 0
The source of data can be SFR space, internal RAM or
external RAM. The byte count must be equal to the
number of bytes, to be transmitted, as this determines
when a packet ends. TEN should be set befQre the
DMA GO bit. It takes one bit time after TEN is set
before the transmitter is enabled. The transmit valid
2-320
intJ
AP-429
interrupt should be enabled after TEN is set. Since
CSMA/CD is half duplex, it doesn't matter which
nMA channel services the receiver or transmitter, as
only one DMA channel will be active at any time.
The DMA channel servicing the receiver must have:
Source Address = RFIFO (OF4H)
ISA = 0
SAS = I
DM = I
TM = 0
The destination for data can be SFR space, internal
RAM or external RAM. The byte count must be equal
to or greater than the number of bytes to be received.
Setting the byte count to OFFFFH (64K) is one way of
covering all packet lengths. GREN should be set after
the DMA GO bit. The receive valid interrupt should be
enabled after G REN is set. It takes one bit time after
GREN is set before the receiver is enabled and for the
error bits and RDN to be cleared. Before GREN is set,
the user software should ensure that the RFIFO is
cleared. Setting GREN does not clear the receive FIFO
as stated in the hardware description.
INITIALIZING COUNTERS AND POINTERS:
Whether using DMA or CPU control, pointers will be
required to load the correct bytes for the transmitter
and to store received bytes in their proper location.
Counters are required when the GSC is under DMA
control in order to keep the DMA channel active during the reception of an entire frame and to identify
when a transmitted frame is to be ended. Counters are
optional if the CPU is used to service the GSC, although its usefulness might be questioned.
When the GSC is under DMA control, the data pointers used are destination address registers (DARLn and
DARHn) for the DMA channel responsible for the receiver and source address registers (SARLn and
SARHn) for the DMA channel servicing the transmitter. The counters used are byte count registers (BCRLn
and BCRHn) for the appropriate DMA channel.
The byte count for the transmitting DMA channel
must be known and loaded prior to beginning actual
transmission. Transmission begins when TEN and GO
are set. The reason the byte count must be known prior
to transmission is that when the counter reac/les 0, the
DMA stops loading data into TFIFO, and once TFIFO
is emptied the GSC assumes a transmitted packet is
complete. For the receiver the byte count can be set to
the frame length if known prior to starting reception or
the byte count can be set to a maximum frame packet
length that will ever be received. Another alternative is
to set the byte count equal to OFFFFH. This option
may be chosen if the length of received packets are
totally unknown. If OFFFFH is used, the user must
make sure that there is some method to accommodate
this many bytes. If maximum buffer size is a limiting
factor, then that would be used.
When the GSC is under CPU control, internal RAM is
typically used for pointers and counters. These pointers
and counters would be updated by software for each
byte that is received or transmitted. An interrupt is
generated as long as there is at least one byte in the
receive FIFO. An interrupt is also generated as long as
there is room for one byte in the transmit FIFO. It is in
the interrupt service routine that counters and pointers
are updated and data is transferred to or from the GSC
FIFOs. One advantage of CPU control is that the
length of received or transmitted packets need not be
known prior to the start of GSC activities. When the
GSC is under CPU control, user software determines
when a transmission has ended. For moving targets,
CPU control allows the user software to determine
where to store received data at the time it is transferred
to RFIFO.
So far only initialization of the GSC and DMA has
been explained. In order to use the GSC, the receiver,
transmitter, and associated interrupts need to be enabled. These are covered in the following section.
ENABLING RECEIVER AND RECEIVER INTERRUPTS-There are two receiver interrupt enable bits,
EGSRV (Receive Valid) and EGSRE (Receive Error)
and one bit to enable the receiver (GREN). The interrupts should always be enabled whenever the receiver is
enabled. Once this is done, a user can wait for interrupts to occur and then service the GSC receiver. The
conditions which will cause the CPU to vector to GSC
receiver interrupt service routines are described in the
8-Bit Embedded Controller Handbook.
In most CSMA/CD applications, GSC receivers will be
enabled all the time once the CI52 has been initialized.
The only time the receiver will not be enabled is when a
reception is completed or a receive error occurs. When
this happens, the GSC receiver hardware clears GREN,
which disables' the receiver. The receiver must then be
re-enabled by software before it is ready to accept a new
frame. One way to do.this when under DMA control is
to set the receiver enable bit (GREN) in the receiver
interrupt service routine. Similarly; the GSC receive interrupts should always be enabled and remain so except
for the period of time that it takes to service an interrupt.
Once set, the GSC receiver interrupt enable bits always
remain set unless cleared by user software. About the
only valid reason for clearing the receiver interrupt enable bits is so that certain sections of code will not be
disrupted by GSC activities. If the interrupts are disabled while the receiver is enabled, the amount of time
the interrupts are disabled should not exceed 24 bit
times. If the interrupts are disabled for a longer period
of time, the receive FIFO may be over written.
inter
AP-429
It is a good practice to enable the GSC receiver inter-
rupts prior to enabling the receiver when under CPU
control. Another alternative is to clear the EA bit while
enabling the GSC receiver and receiver interrupts.
However, this could increase interrupt latency. Ifsomething like this is not done, a higher priority interrupt
may alter the program flow immediately after the receiver is enabled and prior to enabling the interrupts.
This in turn could cause the receiver to overflow. When
the receiver is under DMA control the situation is different. First, the interrupts cannot be enabled before
the receiver because if RDN is set from a previous reception, the receive valid service routine will be invoked
but no reception. has yet taken place. The correct sequence when under DMA control would be to set the
DMA GO bit, enable the receiver, then enable the receiver interrupts. In this case the worst that could happen is a slow response to RDN getting set. Even this
can be worked around by making receive valid the only
high priority interrupt.
, To enable the receiver interrupt enable bits and the receiver this sequence should be followed:
IENl ;= XXXXXXll
RSTAT = XXXXXXIX
or if under DMA control:
DCONn = XXXXXXXI
RSTAT = XXXXXXIX
IENl = XXXXXXll
ENABLING TRANSMITTER AND TRANSMIT
INTERRUPTS-There are two transmit interrupt enable bits-EGSTV (Transmit Valid) and EGSTE
(Transmit Error) and one transmitter enable bit-TEN
(Transmitter ENable). The interrupts should always be
enabled whenever the transmitter is enabled. Once this
is done, a user can wait for interrupts to occur and then
service the GSC transmitter. Conditions which will
cause the CPU to vector to GSC transmit interrupt
service routines are described in the 8-Bit Embedded
Controller Handbook.
Compared with the receiver, opposite conditions exist
concerning when the transmitter is operational and the
sequence of enabling transmitter versus transmit interrupts. First, the transmitter and its interrupts are disabled all of the time except on those occasions when a
transmission is desired. The user's application deter~
mines when a transmission is needed. Status of the message, how full a buffer is, or how long since the last
message was sent are typical criteria used to judge when
a transmission will be started.
When a transmission is complete, the interrupts and the
transmitter should be disabled. This is particularly true
for the transmit valid interrupt as TFIFO will most
likely be empty and TFNF (Transmit FIFO Not Full)
will be set. TFNF = 1 is the source of transmit valid
interrupts when the GSC is serviced under CPU control.
The transmitter should be enabled before enabling the
transmitter interrupts. If the GSC is under CPU control and the interrupts are enabled first, TFIFO may be
loaded with data in response to TFNF being set. When
TEN is set, data already loaded into TFIFO would be
cleared. Consequently, data meant to be transmitted
would be lost. If the GSC is under DMA control, it is
possible that an interrupt would be generated in response to TDN being set from the previous transmission, yet no transmission has even started since the interrupts were enabled. If using the DMA channels to
service the transmitter, TEN must be set before the GO
bit for the DMA channel is set. If not, the DMA channels could load TFIFO with data, and when TEN is set
that data would be lost.
'
The correct sequence to enable the transmitter and its
interrupt enable bits is:
SETB TEN
SETB EGSTE
SETB EGSTV
odf under DMA control:
SETBTEN
SETB EGSTE
SETB EGSTV
ORL DCONn, #01
Once all initialization tasks shown so far are completed,
reception and transmission may commence. The process of starting, maintaining, and ending transmissions
or receptions is covered next.
2-322
inter
AP-429
If the transmitter is under CPU control the first byte is
STARTING, MAINTAINING, AND
ENDING TRANSMISSIONS
Prior to starting a transmission, the user will need to set
TEN. This enables the transmitter, resets TDN, clears
all transmit error bits and sets up TFIFO as if it were
empty (all bytes in TFIFO are lost) after a GSC bit
clock occurs. Once TEN is set, actual transmission begins when a byte is loaded into TFIFO. Figure 9 is a
block diagram of the GSC transmitter and shows how
it functions. Once a byte has entered TFIFO, transmission begins. The first step is for the GSC to determine if
the link is idle and interframe space has expired. Actually, this occurs continuously, even when not transmitting, but transmit circuitry checks to make sure these
conditions exist before transmitting. If these two conditions are not met, the C152 will wait until they are.
Once interframe space has expired, DEN is forced low
for one bit time prior to the GSC emitting a preamble
and BOF. About the time the BOF is output, a byte
from TFIFO is transferred to the shift register. As bits
are shifted out this register, they pass by the CRC generator, which updates the current CRC value. Bits then
enter the data encoder which forms them into Manchester coded waveforms and out TxD. If TFIFO is
empty when the shift register goes to grab another byte,
the GSC assumes it is the end of data. To complete a
frame, bits in the CRC generator are passed through
the data encoder and the EOF is appended. One part of
the block diagram in Figure 9 is the transmit control
sequencer. The transmit control sequencer's purpose is
to determine which state the transmitter is in such as
Idle, Preamble, Data, or CRC. To perform this function it has connections to all circuits in the transmitter.
These connections are not shown in order to make the
diagram easier to read.
loaded with user software. TFIFO should be filled and
counters and pointers updated before proceeding with
any other tasks required by the CPU. There is room for
up to three bytes in TFIFO. Before loading the first
byte, users should examine TDN to ensure that any
previous transmissions have completed. If TEN is set
before the end of a transmission, that transmission is
aborted without appending a CRC and EOF but the
interframe space will still be enforced before st;lrting
again. A user can identify when TFIFO is full by examining TFNF (Transmit Fifo Not Full). TFNF will always remain at a logic 1 as long as there is room for at
least one more byte in TFIFO. There is a one machine
cycle latency from when a byte is loaded into TFIFO
until TFNF is updated. Because of this latency, the
status of TFNF should not be checked immediately following the instruction that loaded TFIFO but should
be examined two or more instructions later. Whenever
TFNF is set; an interrupt will be generated if EGSTV is
set. In response to the interrupt, bytes should be loaded
into TFIFO until TFNF is cleared and update any
pointers or counters.
Once the user is through with transmitting bytes for the
current frame, the GSC transmit valid interrupt
(EGSTV) should be disabled. This is to prevent the
program flow from being interrupted by unnecessary
GSC demands as TFNF will remain set all the time.
The GSC transmit error interrupt (EGSTE) must remain enabled as transmit errors can still occur. While
under CPU control there is no interrupt associated with
transmit done (TDN) so a user must periodically poll
this bit to determine when actual transmission is complete. After the last byte in TFIFO is transmitted there
is a delay until TDN is set. This delay will be equal to
the CRC length plus approximately 1.5 bit times for the
EOF. The CRC is appended after the end of data by
GSC hardware.
270720-14
Figure 9. Transmitter Block Diagram
2-323
inter
AP-429
To start a transmission when the GSC is under DMA
control, users should first enable the transmitter by setting TEN, then set the GO bit for the appropriate
DMA channel. Before the GO bit is set users must
initialize the GSC and DMA. Thereafter, the DMA
loads the first byte that begins actual transmission and
keeps the transmit FIFO full until the end of transmission. In this ,case, transmission ends when the byte
count reaches 0, which means the length of the message
to be transmitted must be known before transmission
begins.
The DMA channel examines TFNF to determine when
the transmitter needs servicing. When a byte is'transferred into TFIFO, the DMA channel takes control of
the internal bus and the CPU is held ofT for one machine cycle. This is the only overhead associated with
the actual transmission when under DMA control. This
is significantly less than the overhead associated with
each byte that must be loaded by software when the
GSC is under CPU control. When the DMA is servicing the transmitter, at least one machine cycle occurs
between each.DMA load. This prevents the DMA from
hogging the internal bus when servicing the transmitter. It takes five machine cycles to load three bytes to
initially fill TFIFO. When transmission ends, TDN will
be set and when the GSC is under DMA control it is
the setting of TDN that begins the GSC interrupt service, routine.
The discussion so far assumes there are no errors during transmission of a frame. However, in CSMA/CD
there is always a possibility of an error occurring and
part of maintaining transmission is servicing those errors. In the C152 when an error is detected an error bit
is set. At the same time the error bit is set, TEN is
cleared which disables the transmitter. Types of errors
that can occur are: collision detection errors, (TCDT),
no acknowledgement errors (NOACK) (if HBA is enabled), and underrun errors (UR) (if the DMA channels are used to service the transmitter). After setting
the error bit, the C 152 jumps to the transmit error vector if EGSTE (Transmit Error enable) is set. Depending on the protocol implemented, a user may wish to
take some specific response to an error but in almost all
cases the transmitter will be re-enabled and the same
data retransmitted. This requires that counters and
pointers be initialized, the transmitter enabled, and
TFIFO filled. Another frequent action taken' is to log
the type of error for later analysis or to keep track of
specific trends. Once transmission is restarted, the same
flow is followed as before, as if no error occurred.
STARTING, MAINTAINING, AND
ENDING RECEPTIONS
In most applications, the receiver is always enabled and
reception begins when the first byte is loaded into
RFIFO. Figure 10 shows a block diagram of the, receiver.
As indicated in Figure 10, before the first byte is loaded
into RFIFO, the address is checked for a matching address assigned by ADRn. A user can disable address
recognition by writing all Is to the address mask regis~
teres), AMSKn. In this mode all frames with a valid
BOF will be received. When the first byte is loaded into
RFIFO, RFNE is set. If the address does match, there
is a delay of about 24 or 40 bit times from reception of
the first bit until a byte is loaded into RFIFO depending on which CRC is chosen. This is due to CRC strip
circuitry and the bits required to fill up the shift register.
RFiFO
270720-15
Figure 10. Receiver Block Diagram
2-324
inter
AP-429
When tlie GSC is being serviced by the CPU, an interrupt is generated when RFNE is set and if EGSRV is
enabled. The user typically responds'to-an interrupt by
removing one byte from RFIFO and storing it somewhere else. The user should check RFNE before leaving the interrupt service routine to see if more than one
byte was loaded in to RFIFO. While under CPU control, .there is no interrupt generated when reception is
complete although receive done (RDN) is set. When
RDN is set, the receiver.is disabled and user software
has to re-enable it. To determine when a frame has
ended, the user must periodically poll RDN. After a
frame has ended, the user will normally reinitialize
pointers, reset counters, and enable the receiver. RDN
will not be set when the last byte is transferred to
RFIFO because the EOF will not be recognized yet. It
takes approximately 1. 7 bit times of link inactivity for
the EOF to be recognized.
When the GSC is controlled by the DMA channels an
interrupt is generated when RDN is set for a valid reception. At this point all a user needs to do is to set the
source address registers, set the byte count, set the GO
bit, and enable the receiver. Whenever the GSC receiver is being serviced by the DMA channels, the GO bit
should be set before the receiver enable bit, GREN.
This is to ensure that the DMA channel is active whenever the receiver is enabled. If the receiver is enabled
before the DMA channel, it is possible that an interrupt
would alter the program flow. An interrupt could delay
setting the GO bit so that data is received while the
DMA channel is prevented from servicing the GSC.
Consequently, an overrun error occurs.
For the GSC receiver, as in the transmitter, an error is
always possible. Conditions that set the error bits are
the same regardless of how the receiver is being serviced. Possible errors are: receiver collision (RCABT),
CRC error (CRCE), overrun (OVR), and alignment error (AE).
The only type of error that user software can take actions to prevent is an overrun error. In this case, when
an overrun error occurs it is because the receiver could
not be serviced fast enough. Under DMA control, the
only way this could happen is if the other DMA channel prevented servicing the GSC by the DMA or the
user cleared the GO bit. Solutions to these problems are
to turn off the second DMA channel when receiving
and not mess around with the GO bit during reception.
To determine if the GSC is receiving a packet, the byte
count of the appropriate DMA channel can be examined. If the GSC is under CPU control and an overrun
occurs it is because there are too many other tasks the
CPU is doing or the baud rate is just too high for the
CPU to keep up. A solution to this problem is to either
cut back on the number of tasks the CPU must perform
while a packet is being received or to switch to DMA
control of the GSC.
In all other cases, about all the CI52 can do when a
receive error occurs is to log the type of error, discard
the data already received, and to re-enable the receiver
for the next packet. These actions would also be taken
for an overrun error.
SUMMARY
Hopefully, this application note has given the reader
some insight on how to set ·up the GSC parameters,
how to transmit or receive a packet, and how to respond to error conditions that may arise. The process of
obtaining data for transmission or what to do with data
received has been left open as much as possible as these
vary widely from application to application. In some
cases, all the data will be managed by another, more
powerful processor. In this situation, the user will have
to implement another interface between the main processor and the C I 52.
Although the whole process of using the CI52 may at
first, seem confusing and complicated, breaking down
this process into steps may make utilizing the CI52
much simpler. One suggestion of the steps to follow is:
I) INITIALIZATION
A) Baud rate
B) Preamble
C) Backoff
D) CRC
E) Interframe space
F) Jamming signal
G) Slot time
H) Addressing
I) Acknowledgment
1) Clearing the collision counter
K) Controlling the GSC
L). DMA initialization (if used)
M) Counter and pointer setup
N) Enabling the GSC
0) Enabling the interrupts
2) TRANSMITfING/RECEIVING PACKETS
A) Starting transmission/reception
B) Maintaining GSC operations
C) Ending transmission/reception
D) Responding to errors
These steps can be used as a checklist to ensure that the
minimum set of functions have been implemented that
will allow the GSC to be used in almost any application. The list also demonstrates- that the bulk of the
tasks the user must implement is in initializing the
GSC. Once initialization is accomplished, there is comparatively little work left to implement an application.
2-325
intJ
AP-429
APPENDIX A
SOFTWARE EXAMPLE
The following example demonstrates how the DMA
can be used to service the GSC in a specific environment. Figure II shows a diagram of the hardware used.
As shown, the DART is used as a source and destination for data transferred by .the GSC. Also shown in
Figure II are some DIP switches. These DIP switches
determine source and destination addresses. The
switches are read only once after a reset. The hardware
environme~t is shown for informational purposes only
and is not necessarily a real application that would be
implemented by a user. Even so, with some minor
changes, similar circuits might be used, requiring corresponding changes to be made in the software.
This program has been written with the assumption
that a terminal will be connected to the DART. As
such, only ASCII data" can be transferred and each
block of data is delineated by a carriage return (ODH)
and line feed (OAH). As data is received by the DART
it is stored in one of four rotating buffers. This data will
later be transmitted by the GSC to other C152s. Data
received by the GSC is stored in one of four different
rotating buffers. This data will be transmitted by the
DART to a terminal. IK of external data RAM is connected to the C152 to serve as storage buffers. Consequently, each buffer is one-eighth of available external
RAM, or 128 bytes. This provides up to one line of 120
characters for each buffer. Also, each buffer will store
additional information such as destination address,
source address, and message length. When a line of
characters is complete, a flag will be set to signify to the
GSC that'that buffer is to be transmitted. Conversely,
when a packet received by the GSC is complete, a flag
is set to identify that buffer'is to be output through the;
DART to a terminal. Whenever access to one buffer is
complete, the software manipulates pointers so the next
buffer is used. If all 4 buffers are full, data for that type"
of buffer is no longer accepted until another buffer is
available.
Note that this program uses both DMA channels, one
for the receiver and one for the transmitter on the GSC.
A program could have been written using only one
DMA channel. Dsing both channels has made the program· much simpler and shortened the time it takes to
change from transmitting to receiving.
2-326
inter
AP-429
P4
Vee
8XC152JA
X8
•
••••••••••••
•••••••••••
••••••••••
•••••••••
TxD
Vee
XB
RxD
GTxD
ALE
1KkB
RAM
PO
GRxD
P2
RD
WR
BXC152JA
TxD
GTxD
••••••••••••
•••••••••••
••••••••••
•••••••••
RxD·
GRxD
P4
ALE
Vee
lKkB
RAM
XB
PO
Vee
P2
RD
XB
WR
270720-16
Figure 11. Hardware Environment for Software Example
2-327
10/19/88
APPNOTI
MeS-51 MACRO ASSEMBLER
l
PAGE
DOS 3.30 (038-Nl MCS-5l MACRO ASSEMBLER, Y2.2
OBJECT MODULE PLACED IN APPNOTl.0BJ
ASSEMBLER INYOKED BY:
C:\ASM5l\ASM5l EXE APPNOTl.PGM
LOC
OB.!
LINE
I
2
0000
OOFC
0014
165
166
167
168
169
170
171
SOURCE
$XREF
$NOLlST
GSC_BAUD ..RATE
EQU
o
i
GSC baud rate
1. 5MBPs
LSC_BAUD.RATE
EQU
OFCH
i
LSC baud rate
9
i
14. 7456 MHz
0003
.number of bit times separatlng
; frames
BUFIA_51RT_ADDR EQU
003H
.buffer lA!s starting address for
• storing data (0
of b~tes.
i 1 = dest addr.
2 = ST'C addr)
BUFIB ..STRT_ADDR EQU
OB3H
.buffer IBis starting address for
• storing data eSOH
of b9tes.
BUFIC_STRT_ADDR EQU
103H
;buffer ie's starting address fqr
i storing data (100H_= .' of b\ltes.
; 101 = dest itddT', 102 = S1"C addr)
EQU
176
177
0083
17B
179
.81
180
181
I\)
~
00
0103
0183
IB2
183
184
185
IBb
IB7
IBB
190
02Bl
0381
0080
OOOD
OOOA
REG
198
199
200
201
202
203
204
205
206
207
20B
209
210
211
212
51"e
addr)
BUF2A_STRT_ADDR EOU
20lH
.buffer 2A's starting address for
istoring data (200H = • of b~tes)
BUF2B_S1RT_ADDR EOU
2BIH
;buffe~ 28'5 st.~ting address for
isto!ing data (280H ~ • of bVtes)
BUF2C_STRT_ADDR EQU
30lH
;buffer 2C's sta~ting
;sto~ing data (300H =
BUF2D_S1RT_ADDR EQU
3BIH
;buffe~ 2D's starting address fo~
JstoTing data (3BOH = • of b~tes)
STACK_OFFSET
EQU
80H
;start stack at
CR
EQU
ODH
iASCll equivalent for carriage
il"eturn
LINE~EED
EQU
OAI<
iASCII equivalent for line-feed_
ERROR_POINTER
EQU
RO
iRO holds the address that points
ito t~e next errol" location to
; incremeont
195
1910
197
82 =
.buffer 10's starting address for
.storing data (ISOH = • of bgtes.
; IBI = dest addr. 182 = src addr)
194
0301
dest addr.
IB3H
191
192
193
=
=.
=.
BUFID_STRT _ADDR EQU
189
0201
baud at
20
IFS_PERIOD
172
173
174
175
61'.
uppe~
add~ess
• of
128
.
l>
"U
....
~
for
b~tes)
b~tes
270720-17
MCS-51 MACRO ASSEMBLER
LOC
OD ...
0078
OOFF
LINE
213
214
215
216
217
218
219
APPNOTI
10/19/88
PAgE
l
2
SOURCE
MAX_LENGTH
Eau
120
imaximum length a
."
•
isee if buffer lC has something
ito transmit out GSC
-iB BUFID_ACTIVE.BUFFERI_START
isee if bu"er 1D has samething
;to transmit out Gst
-iB BUF2A_ACTIVE.DUFFER2_START
isee if buffer 2A has something
ito transmit out LSC
BUF2B~CTIVE.BUFFER2_START
isee if buf'er 28 has something
ito transmit out LSC
-iB BUF2C_ACTIVE.BUFFER2_START
isee if bu"er 2C has something
ito transmit out LSC
-is BUF2D_ACTIVE.BUFFER2_START
isee if buf'er 2D has something
ito transmit out LSC
-is
I I ""
N
CD
-iMP MAIN
B\lFFERl_START:
CALL NEW_BUFFER I_OUT
ithis routine should start a
itransmission i' a bu"er is Full
-iMP MAIN
~BUFFER2_START:
CALL NEW BUFFER2_0UT
,this routIne starts a tTansmission
270720-21
MCS-51 MACRO ASSEMBLER
LOC
APPNOTI
LINE
OBJ
433
434
435
43b
437
438
0134 BODC
0200
43q +1
=1
=1
=1
=1
=1
440
441
442
443
444
445
44b
447
448
44'1
450
45\
452
453
454
455
45b
457
45B
459
4bO
4bl
4b2
4103
4b4
4b5
4bb
4107
4108
410'1
470
471
472
473
474
475
4710
=1
477
=1
47B
47'1
480
481
4B2
4B3
484
485 +1
4810
487
0203 75B402
=1
=1
=1
=1
=1
020b 75A414
=\
=\
=\
020'1 75D400
=1
=1
0200 75'1400
=\
020C D2DB
=1
=1
020E 75C2B5
=\
=\
0211 7:1'12'1B
=1
=\
~
=1
0214 75B2F4
0217 75F300
021A 75F27B
021D 7593b9
0220 B57C'15
0223 757901
022b 757B02
0229 B579D2
022C 8578D3
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
022F DOlEI'
=1
0231 D2bF
=1
=1
=1
=1
0233 22
=1
0234 75BDFC
=1
=1
10/19/BB
PACE
(
10
SOURCE
lout ~h. LSC if one of the buffers
i1s full
JMP MAIN
ORG 200H
$INCLUDE (GSCINIT SRC)
GSC_INIT
MOV BAUD .• SSC_BAUD_RATE
MOV GI'tOD .• 02H
.lnlt For CSMA/CD,
. 16-b i t
eRe.
8-b
1
t
a-bit preamble.
addresses
MOV IFS •• IFS_PERIOD
,lnlt IFS 'or period between frames
MOV TCDCNT •• O
.clrar coll1610n counter
SETB DMA
. lnlt CSC Interrupts for DMA
MOV DARLO .• TFIFO
.DMAO WIll servIce TFIFO
MOV DCONO •• 10011000B
; lnlt DMAO Ill1th SFR as dest.
.as source.
MOV SARLI ••RFIFO
MOY BCRHI ••O
MOY BCRLI ••MAX_LENGTH
MOY DCONI •• 0110100IB
ext RAM
»
serial port demand mode
l'
.,..
.DMAl Will servIce RFIFO
I\)
CD
ilaad DHA bVte count with maximum
; mes.sage length
iinit DMAI ~ith . I t RAM as dest.
; SF~ as source. serial port demand
; mode, and set GO bi t.
MOY ADRO.GSC_SRC_ADDR
MOV GSC_INPUT_LOW •• LOW (BUF2A_S1RT~DDR)
MOV GSC_INPUT_HIGH ••HIGH (BUF2A_STRT_ADDR)
iinit GSC input address storage
MOV DARL1.GSC_INPUT_LOW
MOV DARHI.GSC_INPUT_HIGH
; init DHA destination address to
;match GSC input address storage
SETB GREN
ienable receiver
SETB FIRST_CSC_OUT
;set indicator that first
ihas not vet occurred
RET
$INCLUDE (LSCINIT.SRC)
LSC INIT:
-MOY TH1 ••LSC_BAUD_RATE
isetup timer! to
gene~ate
esc xmit
LSC baud
270720-22
MCS-51 MACRO ASSEMBLER
LOC
LINE
DB.!
0237 438920
023A 53892F
023D 759850
0240 D2BE.
0242 22
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
4BB
4B9
490
491·
492
493
494
495
496
497
498 +1
024G 53901F
0246 B5C07C
0249 439020
024C BSC07D
024F 22
'"Col~
.j::o
0250 D2CB
0252 D2C9
0254 D2AC
0256 D2CC
0258 D2AF
025A 22
025B 752FOO
025E 752EOO
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
-1
=1
=1
=1
-1
=1
=1
=1
=1
=1
=1
=1
=1
=1
0261 C26E
0263 757803
=1
=1
=1
=1
=1
=1
10119/BB
APPNOTl
499
500
501
502
503
504
505
506
507
SOB
509
510
511
512 +1
513
514
515
516
517
51B
519
520
521
522
523
524
525
526
527 +1
52B
529
530
531
532
533
534
535
536
537
538
539
540
.541
542
PAGE
l
7
SOURCE
DRL TMDD.IOOIOOOOOB
ANL TMDD.IOOIOIIIIB
MOV SCDN.IOIOIOOOOB
Jinit ti ••~l as a-bit auto-reload
isetup LSC as 8-bit UART and enable
I ~ec.iver
SETB TRI
Jsta~t
ti •• r to generate baud rate
RET
$INCLUDE (INITADDR SRCl
ADDRESS_DETERMIIIATIDN
ANL Pt •• JFH
iselect output 0 of '138
MOV GSC_SRC_ADDR.P4
.read GSe receiv.- address from
ORL PI.120H
iselect output 1 of '138
MOV GSC_DEST_ADDR.P4
.read QSC x.it address from DIP
; DIP ... i tch I I
i
switch .2
»
RET
$INCLUDE (ENAINT.SRC)
INTERRUPT_ENABLE:
SETB EGSRV
"0
J,.
I\)
;.nable GSC receive valid interrupt
SETB EGSRE
ienabl. GSC receive error interrupt
SETB ES
I
SETB EDl'lAI
ienable DKA! done interrupt
SETB Ell
senabl. interrupts
CO
enable LSC interrupt
RET
$INCLUDE (GENINIT.SRC)
GENERIC_INIT:
MOV BUFFERl_CONTRDL •• O
Jinsure all buffer 1 active bits
0, current input and output
Ibuffer = lA
i-
MOV BUFFER2_CONTRDL.IO
;in5U1'. all buffer 2 active bits
;= O. current input and output
CLR LSC_ACTIVE
iinsure LSC_ACTIVE = 0 before
istarting a reception
; buff.n"
MOV LSC_INPUT_LOW.ILOW I BUF1 A_STRT_ADDRI
=:
18
270720-23
I1CS-51 HACRO ASSEI1BLER
LOC
02109 757F02
02bC 7BCF
02bE OB
026F 7600
0271 BBFFFA
0274 22
0275 D3
ro
c.,
02710 7FOb
Co)
(]I
027B Eb
0279 3400
027B Flo
027C lB
0270 DFF9
027F 4001
02Bl~
LINE
DB....
021010 757Aoo
22
02B2 OB
-1
=1
=1
=1
=1
=1
=1
-I
=1
-I
=1
-I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
10119/B9
APPNOTI
543
544
545
546
547
548
549
550
551
552
553
554
555
PAgE
l
B
SOURCE
110V LSC_INPUT_HIgH. *HI9H CBUFIA_STRT.J\ODRI
load address pointe,"6 lIIith
; starting addT.s5 of bu"er lA
i
; but. count initialized to 2
; because destination and source
I10Y IN_BYTE_COUNT ••02
J
address 1If111 take fiT'st two bVtes
J
and counter is not tnc,.e.ented.
110V RO. *NEXT _LOCATION
COUNTER_CLEAR:
INC RO
5510
557
55B
559
Clear out .TrOT' counter
MOV eRO •• O
i
C..JNE RO. *OFFH. COUNTER_CLEAR
; loop unti 1 all count.rs
A
0
5100
:Sbl
RET
5102
563
564 ... 1
565
566
5107
.INCLUDE CCNTRINC. SRCI
I NCREI1ENT_COUNTER:
add 1 on first loop
SETB C
i
110V R7. *10
;. of b"tes in each counter field
.
»'U
56B
5109
570
571
572
,573
574
575
~
INC_COUNT_LOOP:
'"
CQ
I10V A. tlERRORJ'OINTER
; get bvte of counter
ACDC A ••O
5710
577
57B
579
580
5BI
I10Y eERRORJ'0INTER. A
DEC ERRDRJ'OINTER
O....NZ R7.INC_COUNT_LOOP
5B2
583
584
5B5
5Bb
587
5BB
5B9
5'10
591
5'12
5'13
594
595
5910
597
..JC COUNTER_OVERFLOW
loverflow if ~.r ... u lenerated. This
; ..,.s initiall" put in to stop the
I f10111 of the pragr •• if' anu of the
J .".,.0," count .... 5 Qve",'loilled \lftth the
i .xpact.tiDn that the usa'" IIIDuld
i .odiflJ the code to" dump the erTOT
Icount contents and ",a-initializ. the
J caunter locations.
RET
COUNTER_OVERFLOW:
INC ERRDR_POINTER
J
point to ,ub of counteT field
270720-24
MCS-51 MACRO ASSEMBLER
LOC
LINE
OBJ
02B3 7bFF
02B5 OS
02Bb 7bFF
02BB OB
02B9 7bFF
02BB OB
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
"I
I\J
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
en
=1
02BC 7bFF
02BE OB
02BF 7bFF
0291 OB
0292 7bFF
0294 BOFE
W
(.oJ
=1
10/19/98
APPNOTl
59B
599
MOV @ERROR_POINTER ••OFFH
i
1>01
1,02
-1,04
1,05
bOb
1,07
bOB
and
5. to ... .,
OFFH
Ipoint to next byte of coutn .... field
-INC ERROR_POINTER
MDV @ERROR_POINTER ••OFFH
;and sto,.. OFFH
INC ERROR-pOINTER
;pain~
MOV @ERROR_POINTER ••OFFH
; and .to,.. OFFH
1>03
to
nRI~
"'point to next
INC ERROR-POINTER
1,09
1,10
1,11
MDV @ERROR_POINTER ••OFFH
1,12
1,13
1,14
bib
/,17
biB
1,19
byte
0'
counte ... field
bV~.
0'
caunter Field
land stat'. OFFH
INC.ERROR-POINTER
ipoint to next bvte of counter Field
MDV @ERROR-P0INTER ••OFFH
land stoY'. OFFH
1,15
1.24
1.25
INC ERROR_POINTER
.point to next bVt. of counter field
MOV @ERROR_POINTER ••OFFH
• and stat'. OFFH
~P-
iif the e1'1"OT counters overflo. the
iprogl"am continue. to loop at this
; location until H/W resets the device.
1,21,
1,27
;******************************************************************************
,This section us.s • bit addTessable cont ... ol byte to determine _hieh buffers
b2B
1.29
Jare activ. (contains data 'or QSC to output), the last buffer used bV the LSC
; input, and the last buffer,used bg the QSC Dutput.
1,30
1,31
1,32
1,33
1,34
1,35
1,31,
1,37
I
=L
b3B
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1,39
.The control
b~te
1,49
1,50
1,51
1,52
"P
""
N
CD
is defined .5 '0110.5:
00
BUFFER IA
01 = BUFFER 18
10
BUFFER iC
11 = BUFFER ID
Q
_ _ _ 1_ _-
1
LAST BUFFER USED
BY QSC FOR OUTPUT
1,40
-b4B
:a-
_INCLUDE (BUFIMGT_SRCI
NEW_BUFFERI_IN:
=1
=1
=1
-I
=1
=1
=1
=1
=1
=1
=1
=1
1,41
1,42
1,43
1,44
1,45
1,41,
1,47
(
9
SOURCE
bOO
1,20
1,21
1,22
1,23 +1
PAgE
_1_,
LAST BUFFER USED
BY LSC FOR INPUT
,_'_
7'~B~IT~7~~I~B~I~T~b~'~B~I:T~5~I~B~IT~4~I~B~I~-3--'--B-I~-2--'--B-I~-I--'-B-I~-0---'
, ______ ' _____ 1_ _ _ _ ' ______ , _____ , ______ ' _____ 1_ _ _ _ '
I
~
I
I
!
:
:
:
BUFFER lC
BUFFER lA
ACTIVE
ACTIVE
LSC_IN_MSB
BUFFER IB
gSC_OUT _MBB
BUFFER ID
ACTIVE
ACTIVE
LSC_IN_MSB
QSC_OUT _LSB
BUFIA_ACT
BUFIC_ACT
'.
,
270720-25
MCS-51 MACRO ASSEM8LER
LOC
OBJ
0296 20794E
0299 207823
029C 207D43
029F 758200
02A2 758300
~
Ul
Ul
-...I
02M E57F
02A7 FO
02AB A3
02A9 E57D
02AB FO
02AC A3
02AD E57C
02AF FO
0280 027C
0282 C279
0284 0278
0286 757883
0289 757AOO
LINE
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
653
654
655
656
6~7
658
659
660
661
662
663
664
665
10/19/B8
APPNOTl
PAgE
l
10
SOURCE
8UFID_ACT
I
BUFID_ACT
**********************+*************** ... ********************************.******
JD LSC_IN_"SD. LSC_IN_ID_IA
· if LSC_IN_MSB =
1 (Ie OT' ID).
.then the next buffer to be used
.must be 10 or lA
~B
LSC_IN_L59.LSC_IN_IC
LSC IN_ID
blob
· 1f LSC_IN = 018 then next buffer
.for LSC to use 15 Ie
• If LSC_IN = OOB (onlq combination
.left) then next buffer to use 15
.18
61.7
bbB
101.9
1.70
1.71
1.72
1.73
1.74
675
1.71.
677
678
679
680
681
bB2
683
bB4
_1.85
686
6B7
6BB
6B9
690
1.91
692
693
694
695
696
1.97
69B
699
700
701
702
703
704
705
70b
707
J8 DUFIB_ACTIVE.BUFFERS_I_FULL
· l' bu'fer 10 IS actlve then the
.CSC has not ~et emptled It and
.all the buffers must be full
MOV DPL •• LOW I BUFIA_STRT_ADDRI - 3
r10V DPHi.HIGH (BUFIA_STRT __ADDR)
.setup DPTR to pOlnt at the
.beglnning of buffer lA (first b~te
.should contain number of b~tes
MOV A. IN_BYTE_COUNT
.load ace
110VX t!DPTR.A
Jstore b~~e count at first
,buffer 1A
INC DPTR
iDPTR now points to where the
~ith
b~te
:J>
count for HOVX
b~te
'P
0Iloo
of
N
CD
; destination address should be
110Y A.GSC_DEST_ADDR
;get stor.d destination address
I10YX t!DPTR. A
;store destination addr in XRA"
INC DPTR
iDPTR now points to where source
;addTess should be stoTed
I10Y A.GSC_SRC_ADDR
,get stored source address
MOYX t!DPTR.A
istore destination addr in XRAH
SETD-DUFIA_ACTIYE
; indicate that DUF1A has data to
.be output b~ the GSC and that the
.LSC has moved on to the nelt
; buffer
CLR LSC IN MSB
SET8 LSC_IN_LSS
iset flags to indicate that the
;current input buffer (for LSC)
iis 18
110Y LSC INPUT LOW •• LOW (SUFIS STRT ADDRI
MOY LSC=INPUT=HIGH ••HIGH (BUFIB_STRT_ADDRI
iload starting address of buffer
270720-26
MeS-51 MACRO ASSEMBLER
LOC
LINE
OBJ
~1
02BC 02032D
02BF 207E20
02C2 758280
02C5 758300
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
02CS E57F
02CA FO
02CB A3
~
IN
00
02CC E57D
02CE FO
02CF A3
02DO E57C
02D2 FO
02D3 D27D
02D5' C27S
02D7 D279
02D9 757B03
02DC 757AOI
02DF 02032D
D2E2 12032E
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
75S
759
760
761
762
10/19/88
APPNOTl
PAgE
l
11
SOURCE
,IB
JMP NEW_BUFI_IN_END
LSC_IN_IC'
JB'BUFIC_ACTIVE.BUFFERS_I_FULL
; i ' buffer
1e is active then the
iGSC has not vet emptied it and
ial1 the bu'fer~ must be full
MOV DPl ••LOW·(BUFIB_STRT_ADDRI - 3
MOV DPH •• HIGH (BUFIU_STRT_ADDR)
isetup DPTR to paint at the
.beginning of bu,'er is (first b~t.
• should contain nu_ber of bvtes
MeV A.IN_BYTE_COUNT
. load .cc
MOVX .DPTR.A
• store
INC DPTR
• DPTR
~ith
b~t.
bVte count for MOVX
count at first bvte of
.buffer IB
"O~
points to where the
• destination .ddre65 should be
MOV A.GSC_DEST_ADDR
.get stored destination.addres5
MOVX eDPTR,A
i
INC DPTR
iDPTR now paints to where aouree
;.ddress should be stored
KOV A,gSC_SRC-ADDR
.get
MDVX eDPTR. A
Jstore destination addr in XRAM
SETB BUFIB-ACTlVE
:J>
l'
t
store d.,tinatlon addr _in XRAM
sto~.d
sou~ce
CD
.dd~ess
indicate that BUF1C has data to
b. output bV the QSC and that the
LSC has moved on to the next
buffer
CLR LSC_IN_LSB
SETB LSC_IN_MSB
iset flags to indicate that the
;current input buffe~ (for LSC)
.is Ie
MeV LSC_INPUT_LDW ••LDW .
I\)
03bF 0203A6
0372 207MA
0375 307E37
0378 900100
037B EO
037C F5E2
037E 75E300
0381 A3
0382 8582A2
0385 8583A3
LINE
=1
=1
=1
=1
=1
=1
=1
=1
=1
~I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=i
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951 ~
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
10/19/88
APPNDTt
PAgE
l
15
SOURCE
buf~e~
not active then
ithe LSC has not vet filled it
JNB BUFIB_ACTIYE.NOTHING_FOR_GSC
· if
MOY DPTR.a'BUFIB_STRT_ADDRl -3
; load DPTR with address of byte
MaYX A.@DPTR
; get- b"te count fo1' buff.T' 18
MaV BCRLO.A
load D"A b"te count ~lth length
,oF message to tran5mlt~
MOY BCRHO._O
· Insure high byte count
18
IS
isince the QSC emptied it last
;th~t
holds bqte count for 18
I
0
· (should already be 0)
INC DPTR
. DPTR
MaV SARLO. OPL
MOV SARHO.DPH
.source address for. start of
no~
pOints at dest add,.
.data to send
SETB Gse OUT MSB
CLR
QscjiJT _LSD
JMP START_GSe_OUT
.indicate nelt output buffer
.he buffer Ie
~ill
-
)0
l'
.j:oo
· rQutlne that starts tran'smis510n
~
CO
GSC_OUT IC ID
JB GSC_OUT _LSB., GSe_OUT _10
gSC_OUT_IC:
ioutput buffer
iGSC_OUT = lIB
;if QSC_OUT
; is 1e
~ill
ba ID if
lOB then the buffer
JNB BUF le_ACTIYE. NOTHINGjOR_gSC
iif buffer 1e is not active then
; the LSC has not 'Jet filled it
isioc. the GSC emptied it last
MaV OPTR.a(BUFIC_5TRT_ADDRl -3
iload DPTR ~ith address of b~te
ithat holds b~te count For lC
HOVX A.@OPTR
iget bvte count
HOV BCRLO.A
.load DMA b~te count ~ith length
JoF message to transmit
HOV BCRHO •• O
; insure high byte count
; (should already be 0)
INC DPTR
iDPTR now pOints at dest addr
HOV SARLO.DPL
HOY 5ARHO.OPH
.source address for start of
fOT
buffer 1C
=0
270720-31
MCS-51 MACRO ASSEMBLER
LOC
03B8 D27B
038A D27A
038C 0203A6
038F 307FID
0392 900180
0395 EO
0396 F5E2
I\)
0398 75E300
W
-l>-
c.>
LINE
OBJ
039B A3
D39C 115S2A2
039F 8S83A3
03A2 C27B
03A4 C27A
03A6 D2D9
03A8 D2CD
03AA D2CD
03AC 439201
03AF 22
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1·
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
10/19/88
APPNOTI
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
lDIO
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035 +I
1036
1037
PAGE
(
16
SOURCE
; data to send
SETD IISC_OUT _MSB
SETD IISC _OUT _LSB
JIIP START_GSC_OUT
IISC_OUT 10:
,indicate next output
j be buffe ...
lD
buf'.~
Will
,routine that starts transmission
iif QSC_OUT
is 1D
=
I1B then the buffer
i
JNB BUF1D_ACTIVE.NOTHINII_FOR_IISC
.if buffe ... lD is not active then
ithe LSC has not ~et filled It
;since the GSC emptied it last
1I0V DPTR •• IBUFID_STRT_ADDR) -3
j
load DPTR with address of byte
.that holds byte count for ID
1I0VX A.I!DPTR
Jget bute count for buffer 10
MOV BCRLO.A
j
load DHA blJte count with length
.of message to transmit
MOV BCRHO •• O
; insure high byte count
; (should alreadv be 0)
INC DPTR
iDPTR now points at dest add ...
MDV SARLo.DPL
IIOV SARHO.DPH
CLR IISC_OUT_"SB
CLR IISC_OUT_LSD
0
:J>
l'
.1\00
I\)
CO
isource address for start of
idata to send
i
indicate next output buffer will
; be buffer lA
START _GSC_OUT:
;routine that starts transmission
SETB TEN
; enable QSC transmitt.,.
SETH EGSTV
ivnable GSC transmit valid (TON)
; interrupt
SETB EGSTE
;enable QSC transmit error int
ORL DCONO •• OI
istart DMA which starts data output
NIlTHINIIYOR_QSC:
RET
.INCLUDE IBUF2MGT.SRC)
NEW_BUFFER2_IN:
270720-32
MCS-51 MACRO ASSEMBLER
LOC
OBJ
=1
~I
-I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
I}l
w
t
=1
03BO 207343
03B3 20721E
03B6 20763'1
03B9 759200
03DC 759302
03BF C3
03CO 7476
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
. =1
=1
=1
10/19/9B
APPNOTl
LINE
SOURCE
103B
103'1
; •••••••••••• *****.*******.****** •••• **•••• **** ••• *** ••• **.**.***** •••••••• ***.
.This section uses a bit add~.5sabl. control byte-to determine ~hlCh buffe~s
1040
fare active (cont.ins data fDr LSC to Dutput).
1041
1042
1043
1044
1045
1046
1047
104B
104'1
1050
1051
i
l
17
the last buffer used b~ the LSC
for output. and -the last buffer used b, the esc for input
.The control
b~t.
is defined as fol1ow5:
00 = BUFFER 2A
01
BUFFER 2B
10
BUFFER 2C
II = DUFFER 20
LAST BUFFER USED
BY QSC FOR INPUT
1052
1053
1054
1055
1056
1057
105B
105'1
1060
1061
1062
1063
1064
1065
1066
1067
1069
106'1
1070
1071
1072
1073
1074
1075
1076
1077
1079
107'1
lOBO
1091
IOB2
1093
1094
109:1
1096
1097
1099
1099
1090
10'11
1092
PACIE
LAST BUFFER USED
BY LSC FOR OUTPUT
. ___ - . ___ . . n__ •. n._ •. n'T3iBI~2TiiI~llBl~O:
______ , ______ ' ______ 1 ______ 1______ 1 ______ 1 ______ 1______
:
:
:
:
:
:
:
:
BUFFER 2A
BUFFER 2C
ACTIVE
ACTIVE
LSC_OUT_MSB
QSC_IN_MSB
BUFFER 2B
BUFFER 20
ACTIIIE
ACTIVE
LSC_OUT_MSB
QSC_IN_LSB
BUF2A_ACT
BUF2C_ACT
BUF2D_ACT
»"0
....,
N
CI)
BUF2D_ACT
i********************************************·******** ****•••******.*******.***
JB QSC_IN_MSD.QSC_IN_2D_2A
JB 9SC_IN_LSB.QSC_IN_2C
sse_IN_2B:
JB BUF2B_ACTIIIE.BUFFERS_2-FULL
MOV DPL ••LOW (BUF2A_STRT _ADDR I MOV DPH ••HIGH IBUF2A_STRT_ADDRI
; if' QSC_IN_PfSB = 1 (2C or 2D),
;then the next buffeT to be used
i must be 2D DT 2A.
iif GSC_IN = OlB then next buffeT
;'or csc to use is 2C
= 008 (onllA combination
ileft) then next buffer to use is
,2B
; if eSC_IN
iif buffer 28 is active then the
iLSC has not vet emptied it and
Jail the buffers must be full
; setup DPTR to point at the
;beginning of buffer 2A (first bgte
;shDuld contain number of bgtes
CLR C
,f01" SUDD
MOil A•• (MAX_LENQTHI - 2
imaximum packet length and the
i initial value for BCRLI (-2
270720-33
MCS-SI MACRO ASSEMBLER
LOC
LINE
OBJ
~I
03C2 95F2
03C4 FO
=1
=1
=1
=1
=1
=1
~I
03CS 0277
03C7 C273
03C9 0272
03CB 757981
03CE 757802
0301 020432
I\)
W
.;..
c.n
0304 20751B
03D7 75B280
03DA 75B302
03DD C3
03DE 7476
03EO 95F2
03E2 FO
03E3 D276
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
~I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1093
1094
1095
1096
1097
109B
10QQ
1100
1101
1102
10/19/8B
APPNOTI
isubtracted because 'ITst 2 b~tes
~nd source
iare the destination
jadd'resse5
SUBB A.BCRLI
MOVX @DPTR.A
iload ace with byte count for MOVX
istore bVte count at first
11410
1147
b~te
of
ibuffer 2A_
SETS BUF2A_ACTIVE
CLR GSC IN MS8
SETS GSe_IN_LSD
; indicate that BUF2A has data to
ibe output b~ the LSC and that the
,ose has moved on to the next
; buffer
iset flags to lndlcate that the
icurrent Input buffer (for GSC)
. is 28
MOV GSC_INPUT_LOW •• LOW (BUF2B_STRT_ADDRI
MOV GSC_INPUT_HIGH •• HIGH (SUF2B_STRT_ADDRI
; load starting address of buffer
.~
,IMP NEW_BUF2_IN_END
l>
l'
~
~
GSC_IN_2C:
JB BUF2C_ACTIVE.BUFFERS_2_FULL
CD
; if buffe~ 2C is active then the
iLSC has not ~et emptied it and
ia11 the buffers must be full
MOV DPL •• LOW CBUF2B_STRT_ADDRI MOV DPH ••H[GH (BUF2B_STRT_ADDRI
CLR C
isetup DPTR to point at the
ibeginning of buffer 20 (first bVte
ishould contain number of b~tes
; fa,. SUBB
m.ximum packet length and the
initial value for BCRLI ( 2
subtracted because first 2 b~tes
are the destination and source
addres$es
MOV A•• (MAX_LENGTHI - 2
11310
1137
1138
1139
1140
1141
1142
1143
1144
1145
(
IB
SOURCE
1103
1104
1105
1106
1107
1I0B
1109
1110
1111
1112
1113
1114
1115
1116
1117
IIIB
1119
1120
1121
1122
1123
1124
1125
1126
1127
112B
1129
1130
1131
1132
1133
1134
1135
PAGE
load ace
SUSD A.DCRLI
i
MOVX @DPTR. A
istore
SETS BUF2B_ACTIVE
~ith
b~te
b~te
count at
count for MOVX
fir~t
b~te
of
; buffet' 2B
;indicate that BUF2B has data to
ibe output bV the LSC and that the
iQSC has moved on to the next
ibuffer
270720-34
MCS-51 MACRO ASSEMBLER
LOC
LINE
OBJ
03E5 C272
03E7 D273
03E9 757901
03EC 151B03
03EF 020432
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
~1
03F2 712E
03F4 BOBA
'I\)
*
03Fb 20121E
03F9 2074Fb
03FC 158200
03FF 15B303
0402 C3
0403 147b
0405 95F2
0407 FO
0408 D275
1148
1149
1150
1151
1152
1153
1154
1155
it5b
1157
115B
1159
1160
1161
=1
11b2
=1
=1
I1b3
=1
1164
=1
lIb5
11b6
=1
IIb7
=1
11b8
=1
11b9
=1
1170
=1
1111
=1
=,1
1172
1173
=1
1174
=1
=1
1175
111b
=1
=1
1177
1178
=1
1179
=1
1180
=1
1181
=1
11B2
=1
=1 1183
1184
=1
=1 ,11B5
,=1 1186
=1
1181
=1 1188
=1
1189
1190
=1
=1 1191
=1 1192
=1
1193
=1
1194
=1
1195
=1 119b
1197
=1
119B
=1
1199
=1
1200
=1
1201
=1
1202
=1
101l9/B8
APPNOTl
PAGE
l
19
SOURCE
CLR GSC_IN_LSB
SETa GSC_III_MBB
iset flags to Indicate that the
;CU~Tent input buffer (for GSC)
is 2C
I
MOV GSC_INPUT_LOW ••LOW IBUF2C_STRT_ADDRI
MOV GSC_INPUT_HIGH ••HIGH IBUF2C_STRT_ADDR)
; load starting address of bufFer
l2C
JMP NEW_BUF2_IN_END
BUFFERS_2YULL:
i of the buffers are full. the pgm
be locked 1" the GSC service
CALL IRET
~ill
rQutine in an "interl"upt In
progress" iIIode.
If th. DI'1A then
f~ •• 5 up • buFf.~.
the interrupt
routine cannDt clear the buffer
activ. bit until the interrupt
(EGSRV/EGSRE) is serviced
JMP NEW_BUFFER2_IN
; continue scanning active
sunti! one is freed up
buffl~rs
~
l'
"..
GSC_IN_2D_2A:
JB GSC_IN_LSI.GSC IN 2A
~
; if GSC_IN = 11 then next buffer
CQ
inext buffer is 2A
GSC_IN_2D:
JB BUF2D_ACT,IVE. BUFFERS_2_FULL
.i'
buFfe,. 2D is active then the
.LSC has not ,et emptied it and
iall the buffers must
MOV DPL ••LOW IBUF2C_STRT_ADDR) MOV DPH •• HIQH IBUF2C_STRT_ADDR)
~e
full
isetup OPTR to point at the
ibeg1nn1ng of buffeT 2C (first b~te
should con,tain number of bvtes
i
CLR C
MOV A•• lMAX_LENGTH) - 2
j
for SUBS
maximum packet length and th.
ini tial value fot" ICRL:l ( 2
subtract .. d because first 2 It"tes
are the d.stin~tio" and source
addresses
SUBB A.BCRLI
;loa. acc
MOVX @DPTR.A
istore b~t. count at fiTst
.buffeT 2C
SETB BUF2CJ\CTlVE
.indicate that BUF2C has data to
~ith
b~te
count
'01'
MOVX
b~te
of
270720-35 '
MeS-51 MACRO ASSEMBLER
LOC
OB.!
040A 0272
040C 0273
040E 757981
0411
7~7803
0414 020432
0417 207708
041A 758280
0410 758303
~
W
.j>.
-.,j
0420 C3
0421 7476
0423 95F2
0425 FO
0426 0274
0428 C272
042A C273
042C 757901
042F 757802
LINE
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
10/19/88
APPNOTI
PAGE
i
20
SOURCE
;be output bV the LSC and that the
iGSC has moved on to the next
;buffer
SETB IISC_IN_LSB
SETB GSC_IN_MSB
iset flags to Indicate that the
.current input buffer (for GSC)
; is 2D
MOV CSC INPUT LOW .• LOW IBUF2D STRT AODRI
MOV GSC-INPUT-HIGH .• HIGH (BUF2D STRT ADDR)
-;load starting address of bufFer
.20
.!MP NEW_BUF2_IN_ENO
CSC IN_2A
.!B BUF2A_ACTIVE.BUFFERS 2 FULL
. if buffer 2A is actIve then the
iLSC has not vet emptied it and
ial1 the buffers must be full
MOV OPL .•LOW IBUF2D STRT AOORI MOV DPH •• HIGH I BUF2D_STRT_AODRI
; setup DPTR to point at the
;beginning of buffer 20 (first byte
,should contain number of
CLR C
MOV A.aIMAX_LENGTHI - 2
;
fo~
~
b~te5
"D
I
~
SUBB
N
CO
maximum packet length and the
initial value for BeRLI ( 2
subtracted because first 2 bVtes
are the destination and source
add1"esses
SUBS A. BCRLI
;load ace with byte count for MOVX
HOVX ItOPTR. A
istore byte count at first byte of
ibuffer 2A
SETB SUF2D_ACTIVE
CLR CSC_IN_LSB
CLR CSC_IN_MSB
indicate that BUF2D has data to
be output bV the LSC and that the
GSC has moved on to the next
buffer
iset flags to indicate that the
icurrent input buffer (for GSC)
iis 2A
MOV CSC_INPUT_LOW.ILOW I BUF2A_STRT_AODRI
MOV GSC_INPUT_HIGH ••HIGH (BUF2A_STRT_ADORI
;load starting address of buffer.
;~
NEW_BUF2_IN_END:
270720-36
MCS-51 MACRO ASSEMBLER
LOC
0439 75F300
043B 75F278
043E 22
043F 306EO;]
0442 0204A9
0445 206EFA
I\)
W
"'"
(J)
LINE
OBJ
0432 8579D2
0435 8578D3
0448 20712B
044B 207014
044E 307758
0451 D26E
0453 900200
0456 EO
0457 F575
045'1 0575
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1258
125'1
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
'I
1272
=1
=1
,.1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
-I
=1
-I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1273
10/19/88
APPNOTI
t
21
SOURCE
MOV DARLI.GSC_INPUT_LOW
MOV DARHI.GSC_INPUT_HIGH
MaV BCRH 10 .0
MDV BCRL1, .'1AX_LENGTH
load DMA destination addres5
,regi.ters with starting address
,of current buffer area
i
,lo~d DMA
. length
b~te
count with packet
.
RET
NEW_BUFFER2_0UT:
JNB LSCJCTIVE. SECOND_lSC_.CHECK
.do not start anDth~r transmission
,If one ·15 In progress (Signified
.b~
LSC_ACTIVE = 1) but thiS
.should nRver happen
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
12'18
1299
1300
1301
1;]02
1303
1304
1305
1306
1307
1;]08
130'1
1310
1311
1312
PAGE
LSC_XMIT _IN_PROGRESS:
,IMP NOTHING_FOR_LSC
ida not start a new LSC Imlt if one
current IV in progress
; 15
SECOND_LSC_CHECK:
JB LSC_ACTIVE.LSC_XMIT_INjPROGRESS
isecond anI' in case interrupt
J>
ioccurs during prevIous test
JB LSC_OUT_tlSB.LSC_OUT_2C_2D
.if LSC_OUT_MSB = 1 then current
ibuffer is 2C Dr 2D
JB LSC_OUT_LSB.LSC~OUT_2B
; i ' LSC_OUT
LSC_OUT 2A:
; bu,fe ... i
5
; i ' LSC_OUT
,is 2A
= 018
N
CQ
then current
2B
~
OOB then the buffer
JNB BUF2A_ACTIVE.NOTHING_FOR_LSC
,if buffer 2A i5 not active then
ithe gSC has not ,et filled it
;since'the LSC emptied it last
SETB LSCJCTlVE
ishow'that LSC 15 in the process of
;doing a transmission
MOV DPTR •• (BUF2A_STRT_ADDRI -1
jload DPTR with addres~ of b,te
;that holds bute count far 2A
MOYX A••oPTR
;get bvte caunt for buffer 2A
MOY LSC_OUT_COUNTER.A
i load LSC blJ,te counter ~i th I.ength
;oF message to transmit
INC LSC_OUT_COUNTER
l'
,..
incremented because the counter
is first decremented before being
tested (D~NZ) when LSC begins to
output data
270720-37
MCS-51 MACRO ASSEMBLER
LOC
OB..I
0458 C271
045D 0270
04!!F 02049E
0462 307644
LINE
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
~1
0465 026E
0467 900280
046A EO
046B F575
I\l
~
041.0 0575
(C
046F D271
0471 C270
0473 02049E
0476 207014
0479 307520
047C 026E
047E 900300
0481 EO
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1313
1314
1315
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
13:18
1359
1360
1361
1362
1363
1364
1365
1366
1367
APPNOTI
10/19/88
PAGE
l
22
SOURCE
CLR LSC_OUT_MSB
SETB LSC_OUT_LSB
..IMP START_LSC_OUT
LSC_OUT_2B
..INS SUF2S_ACTIVE.NOTHING_FOR_LSC
• indicate next output
i be buff • .,. 2B
buffe~
~il1
;Toutine that starts transmission
iif LSC_OUT
.is 2B
018 thrn the buffer
iif buffer 28 is not active then
;the QSC has not qet filled i t
isincr the LSe emptied it last
SETS LSC_ACTIVE
ishow that LSC 15 in the process of
.doing a transmission
MOV DPTR .• CBUF2B_STRT_ADDR) -1
. load DPTR with address of bvte
.that holds b~te count for 28
MOVX A.I!OPTR
.get
MOV LSC_OUT_COUNTER.A
.load LSC bVte counter
b~t.
count for buffer 28
length
~ith
.of message to transmit
INC LSC_OUT_COUNTER
.
l>
• incremented because the counter
. 15 first decremented before being
"a
~
it.sted (D~NZ) when LSe begins to
ioutput data
SETB LSC_OUT_MSB
CLR LSC_OUT_LSS
iindicate next output
buffe~
N
CD
~ill
; be buffeT 2C
..IMP START_LSC_OUT
iroutine that starts transmission
LSC_OUT_2C_20:
..IB LSC_OUT_LSS.LSC OUT_20
LSC_0UT_2C:
..INB SUF2C_ACTIVE.NOTHING_FOR_LSC
;il LSC_OUT = lIB then current
;buffer is 2D
Jif LSC OUT iis 2C -
lOB then the buffer
iif buffer 2C is not active then
;the esc has not 'Jet '_illed it
sinc.e the LSC empt:ied it last
j
SETB LSC_ACTIVE
ishow that LSC is in the process of
;doing a transmission
MOV OPTR •• (BUF2C_STRT_AOOR) -I
iload DPTR with address of b~te
.that holds byte CQunt for 2C
flOYX A.I!OPTR
iget bvte count for bufFer
2C~
270720-38
MCS-51.MACRO ASSEMBLER
LOC
0482
F~75
0484 0575
0486 D271
0488 D270
048A 02049E
048D 30741'1
U'I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1390
1381
1382
1393
1384
1395
13BO
1387
1388
al
1389
0490 D26E
=1
=1
-1
0492900380
~1
1390
1391
1392
13'13
13'14
1395
1396
1397
1398
I}l
Co)
LINE
OB.!
o
0495 EO
0496 F575
al
=1
=1
=1
=1
=1
al
04'1B 0575
=-1
=1
al
04'1A C271
04'1C C270
04'1E A3
-1
=1
=1
=1
-1
=1
=1
'=1
~1
=1
~1
049F A3
04AO A3
04Al 8~8277
04A4 858376
=1
=1
=1
=1
=1
=1
=1
=1
10/19/88
APPNOTI
MOV LSC_OUT_COUNTER.A
INC LSC_OUT_COUNTER
SETB LSC_OUT_MSB
SETB LSC_CUT_LSB
.iMP START_LSC_OUT
LSC_OUT_2D:
141~
1416
1417
1418
141'1
1420
1421
1422
;laad LSC bvte counter
; 0'
~ith
length
tRess.g.· to transflli t
iincremented bec.use the-counter
,is first decremented before 'being
;tested (D~NZ) when-LSC begins to
;output data
,indicate neat output buffer will
;be buffer 2D
.routine
th~t
;if LSC_OUT
5t.1't5 transmission
liB then the
buffe~
; is 2D
.JN8
BUF2D_ACTIVE.NOTHING_FOR_LSC
is
iif buffer 2D
not active then
.the GSC has not yet filled it
isince the LSC emptied it last
SETB LSC_ACTIVE
isha. that LSC is 1n the-process of
idoing _ trans.issian
MeV DPTR •• IBUF2D_STRT_ADDRI -1
; load DPTR ~ith .dd~ ••• of bvte
.that holds bVt. count fD~ 2D
MOVX A.eDPTR
I
MeV LSC_OUT_COUNTER.A
'load LSC bvte counter ~ith length
iof .e.sage to trans.it
INC LSC_OUT _COUNTER
Jincr••• nted because the counter
iis first 4ecre •• nted b~fore being
l>
'P
~
CD
get bvt. count, fo,. buff:e,. 2A
.tested (DJNZ) when LSC begins to
ioutput data
CLR LSC_OUTJlSB
CLR LSC_OUT _LSB
140'1
1410
1411
1412
1413
1414
i
23
SOURCE
139'1
1400
1401
1402
1403
1404
1405
1406
1407
'1408
PAQE
START_LSC_OUT:
. INC DPTR
iindicate nelt output buffer _ill
ji be buffer 28 .
,routine that staTts transmission
,DPTR now points at the destination
iaddress that was received
INC DPTR
;DPTR no~ points at the source
,.ddTess that .as received
INC DPTR
iOPTR nD~ points at the 'irst data
;bvte received
lIOII LSC_OUTPUT _LOW. DPL
MOV LSC_OUTPUT_HIGH.DPH
•• ddTe5S far start af data far LSC
270720-39
MCS-51 MACRO ASSEMBLER
LOC
OB.1
04A7 D299
04A9 22
04AA
04AC
04AE
04BO
C082
C083
COEO
CODO
I\)
04B2 C2CB
~
0484 C2CD
c:.,
04B6 207Bi2
04B9 207A08
04BC 206F16
04BF C27F
04Cl 0204D5
LINE
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
='1
=1
=1
10/19/88
APPNDTI
1423
1424
1425
1426
1427
1428
1429
1430
1431
1432
1433
1434 +1
1435
1436
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
PAQE
(
24
SOURCE
; to send
SETB TI
;set interrupt flag to start
itransmltting ~hen main program Is
Jreturned to
NOTHINI:_FDR_LSC:
RET
.INCLUDE (XMITVAL.SRCI
I:SC_VALID_X"IT:
PUSH
PUSH
PUSH
PUSH
DPL
DPH
ACC
PSW
;SFRs to save before servicing
J
interTupt
,***************************.*****************************************
i
DISABLE TRANS"IT INTERRUPTS
J**********************************************************.**********
CLR EI:STV
lclear valid interrupt enable
CLR EGSTE
Jclear error interrupt enable
I I
CLEAR_ACTIVE_BUFFER:
.1B QSC_OUT_"SB.CLEAR_ACTIVE IB lC
.1B QSC_OUT_LSB.CLEAR_ACTIVE_IA
iif QSC_OUT_MSB = 1 then
iprevious used buffer for GSC
;Dutput must have been 18 or Ie
; if QSC OUT = 018 then active
;buffer-lA bit must be cleared
CLEAR_ACTlVE_ID:
.18
FIRST_GSC_OUT.END_CLEAR_ACTIVE~DUT
if this is first t1'ansmission.
do not clear buffer ID active
bit (this ma~ happen if all
four buffers are filled before
'iTst osc t~ansmis&ion)
CLR BUFID_ACTIVE
iif GSC OUT = 00, then last
;buffer-used is ID unles. first
i tTansmissiDn
.1"P END_CLEAR_ACTIVE_DUT
CLEAR-ftCTIVE_1A:
.
~
270720-40
~
~
~
~
MeS-51 MACRO ASSEItBLER
LOC
04C4 C27C
04C6 C26F
04C8 0204D5
04CB 207A05
04CE C27D
04DO 0204D5
I)J
04D3 C27E
~
I\)
04D5 712F
04D7 75D400
04DA
04DC
040E
04EO
LINE
OB.J
DODO
DOEO
D083
0082
04E2 32
=1
sl
=1
=1
=1
=1
=1
=1
-1
=1
sl
sl
sl
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
-1
=1
-1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
-1
10/19/88
APPNOTI
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513
1514
1515
1516
1517
1518
1519
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529 +l
1530
1531
1532
PAgE
i
25
SOURCE
CLR BUFIA_ACTlVE
Jif QSe_OUT ~ 01, then last
.buffer us.d is lA
CLR FIRST_QSC_OUT
Jcl •• r indicator tb.t shows
Ithe first QSC trans_iss ian
.has not vet occurred
.
END_CLEAR~CTIYE_DUT
.J1tP
CLEAR_ACTIVE_1S_1C:
.JB
QSC_DUT_LSB.CLEAR~TIVE_IC
if GSC_OUT = 118, then last;
ibuffer used is Ie
i
CLEAR_ACTIVE_IS:
CLR BUFIB_ACTIVE
.JMP
iif GaC_OUT
=
then last
10,
i
buffer used is- 18
J
1f QSC_OUT
END_CLEAR~TIVE_DUT
CLEAR~CTIVE_IC:
CLR BUFIC_ACTIVE
=
11,
»
then last
'P
ibuff.r us.d is 1C unle55
;'irst transmission
""
N
CD
END_CLEAR~TIVE_OUT:
'*********************************************************************
I
I
SEE IF NEXT BUFFER IS FULL DR INIT ADDRE8S FOR NEXT AYAIL BUFFER
WHEN IT IS FILLED
i*******************************************************************_.
CALL NEW_BUFFER1_DUT
'*********************************************************************
; RETURN TO ItAIN PROgRAM LOOP
'*********************************************************************
ItDY TCDCNT .410
PDP P5W
PDP ACC
PDP DPH
POP OPL
;clear collision counter
iSFRs that
~ere
saved
RETI
SINCLUDE IXftITERR.SRCI
QSC_ERRDR_XMIT:
J*********************************************************************
270720-41
MCS-51 MACRO ASSEMBLER
LOC
OB.J
=1
~1
04E3 5392FE
04E6
04E8
04EA
04EC
C082
C083
COEO
COOO
04EE 300005
04Fl 78FF
04F3 020500
04F6 300E05
~
(11
U)
04F9 7805
04FB 020500
04FE 780B
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
~1
0500 5175
0502 E52F
0504 540E
0506 040012
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
APPNO'T1
10119/88
LINE
SOURCE
1533
1534
1535
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586
1587
STOP DMA CHANNEL
i*********************************************************************
PAGE
l
26
i
ANL OCONO •• OFEH
iclear GO bIt
PUSH
PUSH
PUSH
PUSH
;SFRs to save before servIcing
DPL
DPH
ACC
PSW
i
interrupt
UR_ERROR:
.JNB
UR.NOAC~_ERROR
isee If error caused by
; ul'ldel'run
MOV
ERROR_POIN~ER
••UR_COUNTER
;load pointer with begInnIng
• address, of UR counter
..IMP GSC_ERROR_XMIT_END
NOAC~_ERROR :
.JNB
NOAC~.TCDT_ERROR
:to
isee if error caused by
i NOAC~
MOV ERROR_POINTER •• NOAC~_COUNTER
"U
I
~
1'1)
; load pointer with beginning
;sddress of NOACK counter
CD
.IMP GSC_ERROR_XMIT_END
TCOT _ERROR:
MOV ERROR_POINTER • .rCDT _COUNTER
iTCDT is onlV error left
GSC_ERROR_XMIT_END:
i
i
*********************************************************************
LDQ FAILURE
i*********************************************************************
CALL INCREMENT_COUNTER
i*************************************************************.**.****
iRE-INITIALIZE DMA
; **********************************************************.**********
MOV A.BUFFERI_CONTROL
ANL A•• OEH
imask off all b1tS except
; current buffer indicator
C..INE A•• 00.OUFFER1B_RELOAO
; 1f current buffer 15 not lA
.check for nelt buffer
270720-42
MeS-51 MACRO ASSEMBLER
LOC
LINE
08..1
0509 75A203
050C 75A300
=1
=1
Dl
050F 900000
0512 EO
0513 F5E2
0515 75E300
0518 020554
0518 840412
051E 75A283
0521' 75A300
I\J
~
C11
-1>0
0524 900080
0527 EO
0528 F5E2
052A 7SE300
052D 020554
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=i
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
0530 B40912
0533 75A203
0536 75A301
0539 9001.00
053C EO
053D F5E2
053F 75E300
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1588
1589
1590
1591
1592
1593
1594
1595
1596
1597
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
160~
1610
1611
16121613
1614
1615
1616
1617
1618
1619
1620
1621
1622
1623
1624
1625
1626
1627
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1.!.41
1642
10/19/88
APPNOTI
PAGE
l
27
SOURCE
MOV SARLO ••LOW (BUFIA_STRT_ADDR)
MeV SARHO ••HIGH (BUFIA_STRT_ADDR)
,~e-lnitial1Z&
50U~C.
pointer
ito BUFIA
MOV DPTR •• (BUF1A_STRT_ADDR) -3
; location that holds BUFIA
bljte count
J
MOVX A.eDPTR
MOV BCRLO.A
MOV BCRHO.IIO
.get b\lte count
ire-lnitlaille bVte counter
.wlth number of bVtes in BUFIA
..IMP START_RETRANSMIT
BUFFER 1 B_RELOAD ,
C.JNE A••04H.BUFFERIC_RELDAD
• If cu~rent buffe~ is not IB
icheck
fo~
next bu"er
MOV SARLO ••LOW (BUFIB_STRT_ADDR)
MDV SARHO ••HIGH (BUFIB_STRT_ADDR)
ire7initialize
; to BUFIS
sou~ce
pointer
MOV DPTR.II(BUFIB_STRT_ADDR) -3
; location that holds BUF1S
i b,,ite count
MDVX A.t!DPTR
iget bvte count
MeV BCRLO.A
MOV BCRHO. 110
):0
'V
t
fD
Jre-initialize bvte counter
;~ith number of bVtes in BUFIA
..IMP START_RETRANSMIT
BUFFERIC_RELOAD:
C.JNE A•• 08H.BUFFERID_RELDAD
iif current buffer is not Ie
;check for next buffer,
MOV SARLO.IILOW (BUFIC_STRT_ADDR)
MOV SARHO ••HIGH (BUFIC_STRT_ADDR)
ire-initialize source pointer
; to BUFIC
MOV DPTR •• (BUFIC_STRT_ADDR) -3
i
i
MeVX A. t!DPTR
MOV BeRLO.A
MOV BCRHO ••O
location that h-olds BUFIC
blJte count
.get bute count
ire-initialize byte counter
;with nUMber of bytes in BUFIA
270720-43
MCS-51 MACRO ASSEMBLER
LOC
OBJ
0542 020554
0545 75A283
0548 75A301
0549 900190
054E EO
054F F5E2
0:;51 75E300
I\)
to>
U1
U1
0554 750400
0557 0209
0559 30D9FO
055C 439201
055F
0561
0563
0565
DODO
DOEO
D083
D082
0567 32
=1
=1
=1
=1
LINE
SOURCE
1643
1644
1645
1646
BUFFERIO_RELOAD
~1
1647
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684
1685
1686
1687 +1
0568
056A
056C
056E
C082
C083
COEO
CODO
0570 7100
=1
=1
=1
=1
=1
=1
=1
=1
=1
~I
10/19/8e
APPNOTI
1688
1689
1690
1691
1692
1693
1694
PAGE
l
28
JMP START_RETRANSMIT
MOV SARLO.ILOW IBUFID STRT ADOR)
MOV SARHO ••HIGH IBUFID __STRT_ADDR)
.re-lnltlallze
5DU~C~
pDlnt~r
; to BUFIO
MOV DPTR .• CBUFID STRT_ADDRl -3
· location that holds BUF1D
,b'lt@ count
MOVX A.@DPTR
· get bgteo count
MOV BCRLO,A
MOV BCRHQ .• O
.reo-lnltlallze b~te counter
number of byt~5 in BUFIA
.~1th
START_RETRANSMIT
; ***.*****************************************************************
• ENABLE TRANSMITTER AND OMA CHANNEL
, .*********************4**********************************************
MOV TCOCNT •• O
l>
"P
ieteaT colliSIon counter
~
I\)
SETB TEN
JNB TEN.S
CD
wait until TEN is set (TEN
will not be set if a
transmissions eRe has not ~et
completed but TEN might be
cl.a~ed befo~e CRC completes)
ORL OCONO •• OI
.set GO bit
POP
POP
POP
POP
;SFRs that
PSW
ACC
DPH
DPL
~e~e
saved
RET!
SINCLUDE IRECVAL_SRC)
GSC _VAL 1 D_REC :
PUSH
PUSH
PUSH
PUSH
OPL
OPH
ACC
PSW
;SFRs to save before servlclng
• interrupt
1695
1696
1697
CALL NEW_BUFFER2_IN
· save bvte count. select next
• GSC input buffer. setup n("xt
270720-44
MCS-51 MACRO ASSEMBLER
LOC
0572 439301
0575 D2E9
0577
0579
0570
0570
LINE
OB'"
DODO
DOEO
0083
0082
057F 32
=1
1698
=1
1699
=1
1700
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1701
1702
1703
1704
1705
1706
1707
1708
1709
1710
=1
1711 +1
1712
=1
0580
0582
0584
0586
C082
C083
COEO
CODO
ro
W
(11
0)
0588 30EE07
058B 78F3
0580 5175
058F 0205AA
10/19/88
APPNOTI
PAGE
l
29
SOURCE
• destination address. and
isetup new b~te count
ORL DCONt. .01
;set GO bit for DMA
SETB GREN
; enab 1 e rec eo i ver
POP
POP
POP
POP
.SFRs that
PSW
ACC
DPH
DPL
we~e
saved
RfTl
_INCLUDE (R~CERR SRC)
GSC_ERROR_REC
1713
=1
1714
=1
=1
1715
1716
=1
1717
=1
=1
=1
=1
=1
=1
-I
=1
=1
=1
=1
=1
=1
171B
1719
1720
1721
1722
1723
1724
1725
1726
1727
1728
1729
1730
-=1
1731
=1
=1
-I
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745
'1746
1747
174B
1749
1750
1751
1752
PUSH
PUSH
PUSH
PUSH
DPL
DPH
ACC
PSW
.SFRs to savw before
. interrupt
~erviclng
.******* •• **** ••• *.****** •• ******.*****.* •••••••••••••• * ••• ******.*.*.
)10
lOC ERROR TYPE
l'
.** ••• ** ••••••••••••••••••••••• *** •••••••••• ***.******** •••••• ** ••••••
~
~
INC_ERROR_COUNT:
CD
;*.*****.*********** •• *************** ••• ***.**** ••• ******* ••**********
THIS ROUTINE INCREMENTS THE ERROR COUNT (UPTO 6 BYTES) FOR EACH TYPE
OF ERROR DETECTED BY HARDWARE
I
I
BECAUSE OTHER ERROR BITS MAY BE SET WHEN OVR IS SET. OVR MUST BE TESTED
BEFORE AE OR CRCE,
ALSO. IN MOST APPLICATIONS AN ABORT MAY ALSO CAUSE
AN ALIGNMENT ERROR OR CRC ERROR. AND AN ALIGNMENT ERROR MAY CAUSE A CRC
ERROR. THE FOLLOWING SEOUENCE OF CHECKING ERROR BITS SHOULD BE FOLLOWED
TO GET AN ACCURATE TALLY OF THE TYPES OF ERRORS THAT ARE OCCURRING
COMBINATION OF ERROR BITS I HAVE SEEN:
CRCE SET FOR BAD CRC
RCABT AND AE SET FOR RCABT (ALIGNMENT ERROR MAY ALSO EXIST)
AE AND CRCE SET FOR ALIGNMENT ERROR (CRC WAS BAD ALSO)
OVR. AE. CRCE AND RFNE SET FOR OVR (THOUGH CRC IS GOOD AND NO AE)
;****.*******.** •• ****** •••••• ** ••••*****•• ***************************
RCABT _CHECK:
"'NB RCABT.OVR_CHECK
is •• if .rror caused bU RCA8T
MOV ERROR-POINTER ••RCABT_COUNTER
CALL INCREMENT _COUNTER'
JMP REC_ERROR_COUNT_END
270720-45
MCS-51 MACRO ASSEMBLER
LOC
OB.J
0592 30EF07
0595 7BF9
0597 5175
OS99 0205AA
OS9C 30EC07
059F 7BE7
05AI 5175
05A3 0205AA
05A6 78ED
05A8 5175
2;
(11
--.I
05AA 71BO
05AC 4:39:301
05AF D2E9
05Bl
05B3
0585
0507
DODO
ODED
0083
0082
05B9 32
OSBA
05BC
05BE
05CO
C082
C083
COEO
CODO
05C2 30geOC
OSC5 120:;DD
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
APPNOTl
10/19/BB
LINE
SOURCE
1753
1754
1755
1756
1757
175B
17S9
1760
1761
1762
1763
1764
1765
1766
OVR_CHEC ... :
.JNB OVR.CRC_CHEC ...
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782
178:3
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793
1794 +1
1795
1796
1797
1798
1799
1800
1801
1802
1803
1804
1805
1806
1807
PAGE
--
30
I I
isee if error caused
b~
OVR
.see If error caused
b~
CReE
t
MOV ERROR_POINTER •• OVR_COUNTER
CALL INCREMENT_COUNTER
.JMP REC_ERROR_COUNT_END
CRC CHEC ... ·
-.JNB CRCE.AE_CHECK
MOV ERROR_POINTER .• CRCE_COUNTER
CALL INCREMENT_COUNTER
.JMP REC_ERROR_COUNT_END
AE CHECK
MOV ERROR_POINTER •• AE_COUNTER
,only error type
left
CALL INCREMENT_COUNTER
»
"U
REC ERROR_COUNT_END
.thls is not what I want to do prQbabl~.
I ma~ need to fool With current
;active bit, addressing. b~te count Dr who knows what????
CALL NEW_BUFFER2_IN
isav what this routine does
ORL DCON1 ••01
,set GO bit for OMA1
SETB GREN
ienable receiver
POP
POP
POP
POP
iSFRs that were saved
PSW
ACC
DPH
DPL
I
.".
N
CD
RET!
.INCLUDE (LSCSERV.SRC)
LSC_SERVICE:
PUSH
PUSH
PUSH
PUSH
DPL
DPH
ACC
PSW
iSFRs to save before servicing
i interrupt
.JNB R I. XMIT _LSC
; Jump to LSC transmit service
;routine if RI IS not set
CALL LSC_RECEIVE
, invoke LSC receiver server
270720-46
MCS-51 MACRO ASSEMBLER
LOC
OBJ
05C8
05eA
osce
OSCE
0000
OOEO
0083
0082
05DO 32
0501 1205FF
05D4
05D6
05D8
05DA
DODO
DOEO
D083
0082
050e 32
05DD C298
05DF 057F
I\)
W
01
(Xl
05EI 857B82
05E4 85711083
05E7 E599
05E9 FO
05EA 1103
05EB 85827B
05EE 85837110
05FI B4000A
05F4 057F
05F6 740A
05F8 FO
05F9 5196
LINE
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1.
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1808
1809
1810
1811
1812
1813
1814
1815
1816
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
.... 1
18~2
=1
1853
=1
1854
=1
=1
=1
=1
=1
=1
=1
=1
1855
1856
1857
1858
1859
1860
1861
1862
10/19/88
APPNOTI
PAGE
(
31
SOURCE
POP
POP
POP
POP
PSW
ACC
DPH
DPL
jSFRs that were saved
ireturn from interrupt
RETI
XMIT_LSC
CALL LSC_XMIT
; invoke LSC transmit server
POP
POP
POP
POP
i
PSW
Ace
DPH
DPl
RETI
SFRs' that lIIere savlIPd
ireturn from interrupt
LSC_RECEIUE:
CLR RI
JeleaT' receiver interrupt bit
INC IN_BVTE_COUNT
• increment RAM location that
;counts the number of b~te5
I input 't'om LSC
MOV OPL.LSC_INPUT_LOW
MOV OPH.LSC_INPUT_HIGH
MOil A.SBUF
~
"D
I
.1:10
I\)
U)
iget address where next bvte
ireceived bV LSC will be stored
Iget oldest bvte LSC has
Ireceived
MOVX II!OPTR.A
; store bvte in buffer
INC OPTR
iincrement buffer address
MOV LSC_INPUT_LOW.OPL
MOV LSC_INPUT_HIGH.DPH
,store incremented address
CJNE A•• CR.ENO_LSC_RECEIVE
,initialize for next buffer
iif last character t'eceived
iwas an ASCII carriage return
INC IN_BVTE_COUNT
; increment RAft location that
;counts the number of bvtes
; input from LSC
MOV A.ILINE-FEEO
;inse~t a line feed after the
ica1"raige return fo1" QSC to
i transmit
MOVX @OPTR. A
istore bvte in buffer
eALL NEW_BUFFER1_IN
isetup for next buffer if
270720-47
MCS-51 MACRO ASSEMBLER
LOC
05FB 757F02
05FE 22
OSFF D5750B
Ob02 120b2A
Ob05 C2bE
~
tTl
(0
LINE
OBJ
Ob07 C299
0609 22
ObOA BS77B2
ObOD B57bB3
Obl0 EO
Obi I F599
0613 A3
0614 858277
0617 858376
061A BOED
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
~I
=1
=1
=1
1863
1864
1865
18610
1867
IB6B
I 86'i
1870
IB71
IB72
1873
IB74
IB75
IB76
IB77
187B
IB79
IBBO
IB81
IBB2
IBB3
IBB4
IB85
IBB6
IBB7
IBBB
18B9
1890
IB91
IB92
IB93
IB94
IB95
IB9b
1897
189B
IB99
1900
1901
1902
1903
1904
1905
1906
1907
1908 +1
=1
=1
=1
=1
Oble
061E
0620
Ob22
COB2
C083
COEO
CODO
~I
=1
=1
=1
=1
1909
1910
1911
1912
1913
1914
1915
191b
1917
10/19/BB
APPNOTI
PACE
i
32
SOURCE
,linefeed received
MOV IN_BYTE_COUNT ••02
.2 needed for destination and
isource address ~hich da not
· Increment BYTE_COUNT when
· loaded
END_LSC_RECEIVE:
RET
LSC_XMIT.
DJNZ LSC_OUT_COUNTER.LSC_OUT_NEXT
,contlnue outputtIng
b~te5
.untll counter reaches 0
CALL CLR_ACTIVE_OUT
.clear active buffer bit for
· last buffer used
CLR LSC_ACTIVE
• IndIcate that LSC 15 no longer
.trYlng to xmit a packet
LSC_XMIT _END:
CLR TI
~
;clear LSC xmit interrupt b1t
'P
.j:o,
RET
I\)
CO
LSC_OUT_NEXT:
MOV DPL.LSC_OUTPUT_LOW
MOV DPH.LSC_OUTPUT_HIGH
i load DPTR with address of
.inext bVte to xmit
MOVX A.4!DPTR
iget next byte
MOV SBUF.A
; load byte into LSC xmitter
INC DPTR
; increment LSC input address
MOV LSC_OUTPUT_LOW.DPL
MOV LSC_OUTPUT_HIGH.DPH
; store incremented address
JMP LSC_XMIT_END
,return to main program
.INCLUDE (DMASERV SRC)
DMAI_SERVICE:
ito get to this point means that a
;message has been receIved which is
• longer than the maximum specified
; length - MAX_LENGTH (·120)
PUSH
PUSH
PUSH
PUSH
DPL
DPH
ACC
PSW
.SFRs to save before serVICIng
• Interrupt
270720-48
~CS-51
LOC
~ACRO
ASSEMBLER
LINE
OB,J
0624 7BEI
0626 5175
062B 8080
1926 +1
062A 207109
~I
062D 307003
0630 C277
I}J
CAl
0632 22
0>
0
0633 C274
0635 22
0636 207003
0639 C276
0638 22
063C C275
063E 22
=1
·'1
=1
=1
=1
=1
=1
=1
='l
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
1927
19;;>8
192"
1930
1931
1932
1933
1934
1935
1936
1937
193B
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
i949
1950
1951
1952
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963
1964
1965
1966
1967
1968
1969
PAGE'
l
33
SOURCE
=1 '191B
=1
191"
=1 ' 1920
1921
=1
=1
1922
=1
1923
1924
=1
=1
1925
=1
=1
=1
10/19/88
APPNOTl
MOV ERROR_POINTER .•LONG_COUNTER
CALt
INCRFMENT ,COUNTER
..IMP REC "ERROl' _COUNT END
.INCLUDE (LSCMGT SRC'
' Cl R. ACTIVE ,OUT
,JB LSC,OUT .MSD.CLR ACT .2D,2C
f LSC OUT Msa = lB. buffer
JII .. t emptl;cf must be 28 or 2C
· 1
CLR ACT_2A_2D
JND LSC_OUT_LSD.CLR_ACT_2D
·• emptted
I'
LSC_OUT = 009.
) s 2D
bufFer Just
· if LSC_OUT = 01B.
• e,.pti.d is 2A
bufFer Just
Cl R..:ACT_2A
CLR DUF2A_ACTIVE
l>
l'
....
RET
CLR_ACT _OlD:
I\)
CD
CLR BUF2D_ACTIVE
; LSC _OUT = OOB
RET
CLR_ACT_28 _OlC:
,JD LSC_OUT_LSB.CLR_ACT_2C
iif LSC_QUT = liB then buffe~
iJust e.ptedlmust be 2C
CLR_ACT 2D:
CLR
BUF2B~CTIVE
iif LSC_OUT = lOB, buffe~ Just
• emptied must be 29
RET
CLR_ACT_2C:
CLR BUF2C_ACTIVE
; LSC_OUT
liD
RET
END
270720-49
MCS-51 MACRO ASSEMBLER
10/1'1/BB
APPNOTl
PAGE
XREF SYMBOL TABLE LISTING
N A ME
J\)
W
~
AC
ACC
ADDRESS_DETERMINATION
ADRO
ADRI
ADR2
ADR3
AE_CHECK
AE_COUNTER
AE
AMSKO_
AMSKI
B_
BAUD
BCRHO_
BCRHI,
_ BCRLO_
BCRLl_
BKCFF
BUFIA_ACTIVE
BUFIA_STRT_ADDR_
BUFIB_ACTIVE .
nUFIB STRT ADDR.
BUFlC:::ACTIVE .
BUFIC_STRT_ADDR.
BUFID_ACTIVE .
BUFID_STRT_ADDR.
BUF2A_ACTIVE
BUF2A_STRT _ADDR.
BUF2B_ACTIVE .
BUF2B_STRT _ADDR.
BUF2C_ACTIVE
BUF2C_STRT_ADDR.
BUF2D_ACTIVE .
BUF2D_STRT _ADDR.
BUFFER I_CONTROL.
BUFFER I_START.
BUFFER I B_RELOAD.
BUFFER 1CJlELOAD.
BUFFERID_RELOAD.
BUFFER2_CONTRCL.
BUFFER2_START.
BUFFERS I FULL
BUFFERS:::2:::FULL
CLEAR ACTIVE lA_
CLEAR:::ACTIVE:::IB_IC
CLEAR_ACTlVE_IO
CLEAR_ACTlVE_IC
CLEAR ACTI VE I D_
CLEAR-ACTIVE-BUFFER
CLR_ACT _2A_2D
T V P E
NUMB
NUMB
C ADDR
NUMB:
NUMB
NUMB
NUMB
C ADDR
D ADDR
NUMB
NUMB
NUMB
NUMB
NUI'IB
NUMB
NUMB
NUMB
NUMB
NUMB
B ADDR
NUMB
B ADDR
NUMB
B ADDR
NUMB
B ADDR
NUMB
B ADDR
NUMB
B ADDR
NUMB
B ADDR
NUMB
B ADDR
NUMB
D ADDR
C ADDR
C ADDR
C ADDR
C ADDR
D ADDR
C ADDR
C ADDR
C ADDR
C ADDR
C ADDR
C ADDR
C ADDR
C ADDR
C ADDR
C ADDR
V A L UE
ODD6H
OOEOH
0243H
OO'1~H
00A5H
00B5H
00C5H
05A6H
OOI'DH
OOEDH
00D5H
00E5H
OOFOH
00'14H
00E3H
00F3H
00E2H
00F2H
00C4H
002FH_4
0003H
002FH.5
00B3H
002FH.6
0103H
002FH_ 7
0lB3H
002EH.7
020lH
002EH.6
0281H
002EH.5
030lH
002EH.4
0381H
002FH
012CH
051BH
0530H
0545H
002EH
0131H
02E2H
03F2H
04C4H
04CBH
04CEH
04D3H
04BCH
04B6H
062DH
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
--
cf
I
I
34
ATTRIBUTES AND REFERENCES
7611
1511 143'1 1523 1540 1681 16'12 1706 1716 17BB 17'1'1 IBO'1 1920 1'115
383 4'1'111
3'111 46'1
4311
4711
5211
1763 177111
22'1. 232 1772
15811
5711
62.
1611
38. 442
60. '110 '140 '176 1006 15'1'1 1620 1641 165'1
65. 460 1263
5'1. '107 '137 '173 1003 15'18 161'1 1640 1658
6411 461 10'17 1139 11'17 1237 1264
~III
2'1711'3003'176'169269'19 147'1
174. 542 543 672 673 863 964 '102 1599 159'1 15'13
2'14. 2'17 400 668 743 '12B 14'15
178. 705 706 71'1 720 '132 160'1 1610 1614
2'11. 2'14 403 715 BOB '164 1502
IB2. 752 753' 784 7B5 '16B 1630 1631 1635
2B8. 2'11 406 780 854 '1'14 1471
IB6. BI7 818 830 831 '1'18 1648 164'1 1653
316.31'1-40'1 1102 1220 12'13 1'13'1
1'10. 471 472 1084 108~ 1251 1252 1300
31'1.322,412 lOBO 1143 1322 1'157
1'13. IIII 1112 1125 1126 1329
32211 325 415 1121 1202 1357 1'164
1'16. 1152 1153 1184 1185 1364
325. 328 418 1180 1242 1386 1946
1'19_ 1211 1212 1224 1225 13'13
2BO_ 530 1580
3'17 400 403 406 423.
1585 1604.
1606 1625_
1627 1646_
283_ 535
40'1 412 415 41B 430.
66B 715 75'1. 780 826
1080-1121 115'1. IIBO 1220
1459 1477.
1454 1488_
14'13.
14'10 150011
1462.
1452.
1'132.
»"D
I
II
270720-50
~
N
CO
I'ICS-~I
N
~
I1ACRO ASSEI'IBLER
10/1'1/BB
APPNOTI
N A 1'1 E
T VP E
VAL UE
CLR_ACT_2A
CLR_ACT _2B.;2C.
CLR_ACT,:,2B
CLR_ACT_2C
CLR_ACT_2D
CLR_ACTIVE_OUT
COUNTER CLEAR.
COUNTER=OVERFLOW
CR
CRC CHECK
cRCE COUNTER
CRCECV
DARHO
DARHI.
DARLO.
DARLI.
OCONO.
DCONI
OI'lA
DI'IAI_DONE.
DI'IAI SERVICE
DPH. -
C
C
C
C
C
C
C
C
0630H
0636H
0639H
Ob3CH
Ob33H
062AH
026EH
02B2H
OOODH
05'1CH
00E7H
OOECH
0007H
A
A
A
A
A
A
A
A
A
A
A
A
A
NUMB
OOC3H
A
NUI'IB
NUI'IB
NUI1B
NUI1B
NUI1B
NUI'IB
C ADDR
C ADDR
NUI'IB
00D3H
OOC2H
00D2H
00'l2H
00'l3H
OODBH
0053H
OblCH
00B3H
A
A
A
A
A
A
A
A
A
NUI1B
00B2H
A
NUI'ID
NUI'IB
NUMB
NUI'IB
NUMB
NUI'IB
NUI'ID
C ADDR
C ADDR
REQ
OOAFH
OOCAH
OOCCH
OOC'lH
OOCBH
OOCDH
OOCBH
04D5H
OSFEH
RO
A
A
A
A
A
A
A
A
A
NUI'ID
NUI'IB
NUI'IB
OOACH
A
OOA'IH
A
DPL.
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR.
ADDR
ADDR
NUI'IB
C ADDR
D ADDR
NUMB
NUI'IB
~
EA .
EDI'IAO.
EDI'IAI.
ECSRE.
EGSRV.
EGSTE.
ECSTV.
END_CLEAR_ACTIVE OUT
END LSC RECEIVE.
ERROR_PO INTER.
ES
ETO.
ETI.
EXO.
EXI.
FO·
FIRST GSC OUT.
CENERIC INIT .
CI'IOD
QREN
QSC_BAUD_RATE.
GSC _DEST _ADDR.
CSC_ERROR_REC.
CSC_ERROR_XI'IIT_END
CS~_ERROR_Xl'IlT
CSC_IN_2A . . .
NUMB
NUMB
NUI'ID
B ADDR
C ADDR
NUMB
NUI'IB
NUI'IB
D ADDR
C ADDR
C ADDR
C ADDR
C ADDR
OOABH
A
OOABH
A
OOAAH
A
OODSH
A
002DH. 7 A
025BH
A
0084H
A
OOE'IH
A
OOOOH
007DH
0580H
0500H
04E3H
0417H
A
A
A
A
A
A
PAGE
l
3~
-ATTRIBUTES AND REFERENCES
1'137'
1'12'1 1'150.
1'155' .
1'152 1'162.
1'134 1'144'
IB79 1'I2n
55U 55'1
5B3 5'141
204. IB4B
1754 171>2.
232' 235 171.5
15'1' 1763
751
50.
55. 476 1259
4'11 453
541 475 125B
361 455 102B 1531. 167B
37. 464 1701 17B3
153. 451
375'
376 1'10'1'
I'll 673 720 7B5 B31 '116 '146 '1B2 1012 IOB5 1126 I1B5 1225 1422
143B 1524 153'1 IbB2 16'11 1707 1715 17B'I 17'1B IBID IB21 IB35 IB46
. IB'I4 1'104 1'114
IBI b72 71'1 7B4 B30 'lIS '145 '1Bl lOll 10B4 1125 I1B4 1224 1421
i437 1:12:1 1:l3B 16B3 16'10 170B 1714 17'10 17'17 IBll IB22 IB34 IB45
IB'I3 1'103 1'113
'141 523
1331
131' 521
134' 517
135. 515
1301 1021. 144'1
1321 1023 1447
1464 1475 14B6 14'1B 1507'
1848 1870.
209' 573 577 :17'1 5'16 5'1B bOO 602 604 1.06 bOB 610 1012 614 bib biB
154'1 155'1 1566 1747 1751. 171.5 1772 1'11'1
'15. ~1'1
»
13
"'"
~
CD
98'
'16'
'1'1'
'17'
77'
344. 341. 4BI 141.4 14B2
3'10 528.
34. 444
162' 47'1 1703 1785
166' 442
257. 21.0 508 1.85 732 7'17 B43
364 17121
1552 1562 15681
372 1530.
1175 121BI
270720-51
_.
I1CS-51 HACRO ASSEII8LER
t.>
en
U>
10/19/BB
N A II E
T Y P E
V A L U E
GSC_IN_2B.
GSC _I N.j!C.
GSC_IN_2D_2A
GSC_IN_20.
GSC_IN_LS8 .
GSC_IN_IISD
GSC_INIT .
GSC_INPUT _HIt~H
GSC_INPUT _LOW.
GSC_OUT _IA .
C
C
C
C
B
D
C
0386H
03D4H
03F6H
03F9H
002EH.2
002EH.3
0200H
007SH
0079H
033EH
03:18H
0372H
037SH
038FH
002FH.2
002FH.3
0033H
002BH
007CH
056SH
04AAH
004BH
0043H
00E8H
OOASH
0089H
OOBOH
OOCBH
0014H
00A4H
007FH
027BH
05_
0275H
0100H
OOB2H
0083H
02SOH
OODBH
OOFBH
032EH
OOBBH
008AH
OOOAH
OODFH
OOEIH
002DH.6
OOFCH
030DH
029CH
02BFH
02E7H
02EAH
002FH.0
002FH.l
QSC_OUT _18 .
I\J
APPNOTl
GSC_OUT _IC_1D.
GSC_OUT_IC
GSC _OUT _10 .
GSC_OUT ....LSD.
GSC.:..OUT_I1SD.
GSC_REC_ERROR.
GSC_REC_VALID.
GSC _SRC _ADOR .
GSC _VAL I 0 _REC.
GSC_VALIO_XIIIT
GSC _XII IT_ERROR
GSC_XIIIT_VALID
HABEN.
IE •
lEO.
lEI.
IENI .
IFS_PERIOO
IFS.
INJlYTE_COUNT.
INC_COUNT_LOOP
INC_ERROR_COUNT.
INCREIlENT_COUNTER.
INITIALIZATION .
INTO.
INTI .
INTERRUPT_ENABLE
IP
IPNI
IRET .
ITO.
IT!.
LINE_FEED.
LNI.
LONG _COUNTER
LSCjoCTIVE
LSC_DAUO_RATE.
LSC_IN_IA.
LSC_IN_1D.
LSC_IN_IC . .
LSC_IN_IO_IA
LSC_IN_ID.
LSC_IN_LSD
LSC_IN_I1SD
o
o
C
C
C
C
C
D
D
C
C
o
C
C
C
C
o
C
C
C
C
C
C
o
8
C
C
C
C
C
8
B
ADDR
ADDR
AODR
ADDR
ADDR
ADOR
ADDR
ADOR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADOR
ADDR
ADOR
ADOR
ADDR
ADDR
ADDR
ADOR
NUIIB
NUIIB
NutlD
NUtlD
NUIID
NutlD
NUIID
AODR
ADOR
ADOR
ADDR
ADDR
NUIIB
NUIID
ADDR
NUIIB
NUIIB
ADOR
NUIIB
NUIIB
Nutl8
NUII8
ADDR
ADOR
NutlB
ADOR
ADDR
ADDR
ADOR
AODR
ADOR
ADOR
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
P...c:E
36
I I
ATTRI8UTES AND REFERENCES
107/"
1073 1119.
1069 1173'
117B'
332. 336 1073 1108 1148 117~ 1207 1247
32B' 332 1069 1107 1149 120B 1248
386 4401
269. 273 472 476 1112 1153 1212 1252 1259
26B. 269 471 475 1111 1152 1211 1251 1258
8951
892 925.
889 9551
9611
957 9911
3041 30B B92 920 950 957 986 1016 1459 1490
300. 304 BS9 919 949 985 1015 1454
3631
3591
260' 263 469 503 &92 739 B04 850
360 16881
368 1435.
3711
3&7'
163.
27.
90'
.
l>
"U
ea.
531
1718 447
42. 447
249. 253 547 6n 724 789 835 1830 IB52 1865
5718 5BI
1725.
~5' 1574 1749 175B 1767 In4 1921
353 379.
114'
1131
393.513'
I I
28.
681
761 872. 1161
91.
89.
207. 185&
146'
235. 239 1919
3468 539 1271 1:!81 1297 1326 1361 1390 IBB2
16B' 487
775 824.
664_
661 7131
657 7731
7781
3121 316 661 702 748 775 813 B59
30BI 312 657 701 749 B14 B60
t
270720-52
01:0
....,
CD
MCS-SI MACRO ASSEMBLER
I\)
W
0)
.I:>
N A ME
T Y P E
LSC_INIT
LS!;_INPUT _HIGH
LSC_INPUT _LOW
LSC_OUT_2A
LSC_OUT_2B
LSC_OUT _2C_2D.
LSC_OUT_2C
LSC_OUT_2D
LSC _OUT _COUNTER
LSC_OUT _LSB
LSC_OUT _MSB
LSC_OUT _NEXT
LSC_OUTPUT _HIGH
LSC_OUTPUT _LOW
LSC_RECEIVE.
LSC SERVICE
LSC:::XMIT _END
LSC_XMIT_IN_PROGRESS
LSC_XMIT
MAIN
MAX_LENGTH
MYSLOT
NEW_BUF1_IN_END
NEW_BUF2_IN_END.
NEW_BUFFER I_IN
NEW_BUFFER I_OUT.
NEW_BUFFER2_IN
NEW_BUFFER2_0UT.
NEXT _LOCATION.
NOACK_COUNTER.
NOACK_ERROR.
NOACK.
NOTHING_FOR3SC .
NOTHING.fOR_LSC.
OUT_BYTE_COUNT
OV.
OVR_CHECK.
OVR COUNTER.
OVR:P.
PO
PI
POl
P3
P4
PCON
PDMAO.
PDMAI.
PGSRE.
PGSRV
PGSTE.
PGSTV.
PRBS
PS
C
D
D
C
C
C
C
C
D
B
B
C
D
D
C
C
C
C
C
C
psw
10/19/88
APPNOTI
C
C
C
C
C
C
D
D
C
C
C
D
C
D
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
NUMB
NUMB
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
NUMB
ADDR
ADDR
ADDR
NUMB
ADDR
ADDR
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
V A L U E
A
0234H
007AH
A
007BH
A
044EH
A
A
0462H
A
0476H
0479H
A
A
048DH
0075H
A
002EH 0 A
002EH. I A
'060AH
A
A
0076H
0077H
A
05DDH
A
A
05BAH
0607H
A
0442H
A
OSFFH
A
A
0112H
0078H
A
A
00F5H
032DH
A
0432H
A
A
0296H
A
032FH
03BOH
A
043FH
A
A'
OOCFH
.A
00D5H
A
04F6H
A
OODEH
03AFH
A
04A9H
A
007EH
A
A
OOD2H
0592H
A
OOF9H
A
A
OOEFH
OODOH
A
A
0080H
0090H
A
OOAOH
A
A
OOBOH
OOCOH
A
A
0087H
OOFAH
A
A
OOFCH
00F9H
A
A
OOFBH
A
OOFDH
OOFBH
A
00E4H
A
OOBCH
A
A
OODOH
PAGE
_.
37
I I
ATTRIBUTES AND REFERENCES
388486.
264. 268 543 706 753 81B B64 IB35 1846
263. 264 542 705 752 817 863 1834 1845
1290.
1287 1319.
128+ 1348.
1354.
1350 1383.
277. 1305 130B 1334 1337 1369 1372 1398 1401 1876
340. 344 1287 1314 1343,1350 1378 1407 1934 1952
336' 340 1284 1313 1342 1377 1406 1929
1876 1891_
274' 277 1422 1894 1904
273' 274 1421 1893 1903
1806 1826_
356 17951
1885. 1906
1276_ 1281
18\7 1874_
395_ 421 428 436
213. 461 1091 1132 1191 1231 1264
67_
710 757 822 868_
1116 1157 1216 1256'
624_ 770 1862
425 875. 1514
1036. 1170 1696 1781
432 1269_
2451 552
242. 245 1559
1546 1554_
147' 1556
882 898 928 964 994 1030.
·1277 1293 1322 1357 1386 1429.
253. 257
80.
1745 1753.
223. 226 1756
156' 1754
81.
10.
11' 501 :106
12.
131
48. 503 508
20_
141.
139.
142_
143_
138_
140.
61_
102.
14. 1440 1522 1541 1680 1693 1705 1717 17B7 IBOO IBOB 1B19 1916
cf
.
l>
-a
~
I\)
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270720-53
_.
~
CJ)
0"1
MCS-51 MACRO ASSEMBLER
APPNOTI
N A 1'1 E
T VP E
PTO.
PTI
PXO.
PXI
RB8
RCABT _CHECK
RCABT_COUNTER
RCABT
RD
RDN
REC_ERROR_COUNT_END
REN
RFIFO.
RFNE
RI
RSO
RSI.
RSTAT
RXD.
SARHO.
SARHI.
SARLO.
SARLI.
SBUF
SCDN
SECOND_LSC_CHECK
SECOND_TEN_CHECK
SLOTTM
S110.
51'11.
5112.
SP
STACK OFFSET
START:::GSC_OUT.
START_LSC_OUT.
START_RETRANSI1IT
START.
TO
TI
TOS.
TCDCNT
TCDT COUNTER
TCDT:::ERROR
TCDT
TCON
TDN.
TEN.
TFO.
TF1.
TFIFO.
TFNF
THO
THI
TI
TLO
C
D
C
C
C
C
C
C
C
D
C
NUMB
NUMB
NUMB
NUMB
NUMB
ADDR
ADDR
NUMB
NUMB
NUMB
ADDR
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
ADDR
ADDR
NUMB
NUI1B
NUMB
NUI1B
NUI1B
NUI1B
ADDR
ADDR
ADDR
ADDR
NUMB
NUI1B
NUMB
NUMB
ADDR
ADDR
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMB
NUMO
NUMB
NUMB
NUI1B
NUI1B
10/19/BB
V A L U E
00B9H
OOBBH
OOBBH
OOBAH
009AH
0588H
00F3H
OOEEH
00B7H
OOEBH
05AAH
009CH
00F4H
OOEAH
0098H
OOD3H
00D4H
OOEBH
OOBOH
00A3H
00B3H
OOA2H
00B2H
0099H
0098H
04451'1
0335H
00B4H
009FH
009EH
009DH
OOSIH
0080H
03A6H
049EH
0554H
OOOOH
ooB4H
00B5H
009BH
00D4H
OODBH
04FEH
OODCH
ooBBH
OODBH
00D9H
008DH
008FH
0085H
OODAH
ooeCH
ooeDH
0099H
008AH
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
PAOE
3B
I I
ATTRIBUTES AND REFERENCES
10511
10311
10611
10411
12411
174411
22611 229 1747
15711 1745
10911
16011
1751 1760 1769 177611 1923
12211
6611 458
16111
12611 1803 1828
7911
7811
6311
11611
4111 916 946 982 1012 1589 1610 1631 1649
4511
4011 915 945 981 1011 1588 1609 1630 1648
44. 4~8
3011 1838 1899
29. 492
1271 128011
877 SSSII
4611
11911
12011
12111
1711 3S1
20211 381
923 953 999 101911
1317 1346 1381 141011
1602 1623 1644 166211
35111
11211
11111
12311
5611 449 1520 1668
23911 242 1566
1556 156411
14911
21_
15011
1~2.
.
»
"C
II
877 BBb 1021 1670 1672
86_
8411
3511 453
151.
2511
2611 487
12511 1425 1887
23.
t
270720-54
"'"
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I1CS-51 ItACRO "'SSEl'lBLER
APPNOTl
N ... ME
T YP E
TL1.
THaD.
TRO.
TRl.
TRANSltISSION_IN PROORESS
TSTAT.
TXD.
UR_COUNTER
UR_ERROR
UR .
WR •
XMlT_LSC
NUItB
10/19/88
V ... L U E
ODeBH
NUIIB
00fWH
NUItB
008CH
OOBEH
033aH
OOD8H
OOBIH
OOFFH
04EEH
OODDH
OOB6H
05DIH
NImII
C ADDR
NUItB
NUIIB
o ADDR
C ADOR
NUIIB
NUMB
C ADOR
...
...
...
A
...
...
...
...
...
...
...
...
PAQE
(
39
....TTRIBUTES AND REFERENCES
24.
22. 489 490
87.
85. 495
BBl. B86
58.
115.
219. 223 1549
1544.
14811 1546
110•
1803 1815.
RECISTER BANKIS) USED: 0
A5SEltBLY COMPLETE. NO ERRORS FOUND
I\)
W
en
en
270720-55
l>
"0
I
~
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CO
inter
AP-429
APPENDIX B
TAKING CONTROL OF THE BACKOFF ALGORITHM
There is a method that allows the user to take control
of the backoff process. This method will only work
when normal or alternate backotT modes are selected. It
will not work in DCR mode. This method works by
loading TCDCNT with 80H. Then on the first collision, TCDCNT will overflow, aborting the transmission and causing a transmission error to occur. It is in
the error routine where the user takes control. Some of
the modifications that have been tested are:
1) Extending the number of retransmissions-this was
accomplished by counting the number of attempted
transmissions in a user implemented counter. When
the number of collisions grew too big, the transmissions were aborted and an error flag set.
2) Extending the number of time slots available-to
implement this, it was required that the time slots be
s\mulated using one of the timers. Then by reading
the PRBS mUltiple times and ANDing each read of
the PRBS with a masking register, the number of
time slots could be extended to randomly fall within
any range selected by the user. Once the slot time
was determined, the resulting value was multiplied
by the selected time slot with the appropriate value
loaded into the timer registers and the timer started.
When the timer expired, the transmission was re-attempted. For very large delays, multiple timer overflows were required and a loop counter used. This
also allowed time slots larger than 255 bit times to
be used.
Other modifications the user may wish to implement
would be to use some kind of token passing scheme
when collisions occur or instead of randomly assigning
slot times, assign pre-determined time slots to each station.
If the user decides to implement some kind of scheme
such as these there are several factors the user must be
aware of. These are:
1) When TCDCNT overflows, it will still contain either 0 or 1 and these many time slots must expire
before the GSC will begin transmissions·again. Even
if the transmitter is disabled and re-enabled the
GSC still goes through the standard backotT algorithm. This means the user should program the slot
time to 01 to minimize the amount of time until the
GSC hardware will allow another transmission to
begin.
2) Due to the amount of software required to implement any of these suggestions, most will not work at
the same speed the internal hardware is capable of.
For this reason, running at maximum baud rates
with minimum IFS will probably not work.
3) There is no real time indication to the user that the
GSC thinks it is in a backotT algorithm, if the GSC
is currently receiving data, or when a collision is
detected. These, and possibly other factors not apparent at the time this application note was written,
must be considered whenever the user tries to modify the hardware based backotT algorithm with software.
2-367
inter.
Ap·429
APPENDIX C
REFERENCES
1. ISO (1979) Data Communication-High-Level Data Link Control Procedures-Frame Structure, ISO 3309.
2. ANSI/IEEE (1985) Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and
Physical Layer Specifications, ANSI/IEEE Std 802.3.
2-368
AR-S17
It-! I IR,\N'i'\( IlfH"
m.I,'1H \rRI,\I.II.H'IH:01\IC\. \1)1
If I~ '0 ~. NOVI \tRI'R )11M"
U sing the 8051 Microcontroller with Resonant
Transducers
TOM WILLIAMSON
AbslraCI-HavinK to interface an anl.Dalf.nsduerr to. digUal conlrol
system thruuah an analolt-lo-diRiial connr1er repreSt'Dts an npensh'e
boltll'Dt4.'k in Ihe denlopment of many systems. Some Ifln!idurer
companies Irt addressinR Ihis problem b)' de~rlopina proprie'ar)' families
of resonant transducers.
Resonant transducers Iff oscin.ton whose frequency depends in some
known WI)' on the physical properl)' beina measured. The ,'eelrin'
output from Ihese devices is • train of fR •• nlula, pulses whosr repethion
ralt entodes lht \lalue of the measur.nd. Changes in the melsur.ad ClUse
Ihr frequ"ncy to shirl. The miC'rocontrolier deteels the frequency shill,
runs a uhdity chH'k on it, and connrts iI in soflwart 10 the mtasul'lnd
value.
This paper discusses software interfacina lechniques betwHn rHonan'
transducers Ind the 8051. Techniques for measuring frequency and
period are discussed and complred for rt'iOIUllon and interrogalion lime.
The 8051 Is caplble of performing these tasks in extremely shorl CPU
time. Requirements for obl.inina n-bU resolution in Ihe measurement are
discussed. It is determined that II is always raster 10 naluate the
me.surand 10 a Kinn level of resolution by measurina the period rather
than the frequency, even ir the measul1lnd is propol1lon.l to the
frequency other than 10 the period. Numerica'and software examples.rr
presenled to illustrate the concepts.
I. RF_SONANT TRANSDUCERS
M
OST sensing transducers are not directly compatible
with digital controllers. because they generate analog
signals. A few transducer companies are developing proprietary families of sensors which generate signals that are more
directly compatible with digital systems. These are not analog
sensors with built-in A-D conversion. but oscillators whose
frequency depends in some known way on the physical
propeny being measured.
The technology is applicable to vinually any type of
measurand: pressure. gas density. position. temperature.
force. etc. The sensor and microcontroller can operate from
the same supply voltage. so the sensor can in most cases
connect directly to a pan pin on the microcontroller.
The nominal reference frequency of the output signal from
these devices is in the range of 20 Hz-500 kHz. depending on
the design. A change in the measurand away from the
reference condition causes the frequency to shili by an amount
that is related to the change in the measurand value.
Transducers are available that have a full-scale frequency shift
of 2-1. The micrucontroller delccls the changc in frequency or
period and convens il in sotiware to Ihe measurand value.
II. CONNH'IIN(i
IH~
Dl"
N" I du
I I nump.rat(ll
Inrrpm .. nt
(Juntlll"nt
l'i
Clf
Intt'~t>r:.
the
dnd
fotm
11I.• ml!ratof'
;;• •
.11'1
t ,,)r
""., .... nomlnator .. IL'
pI
n
dpnomlnator
~o?
numpr.ltor
=
'.ht'I' q"
CJ ~I·H· qT.
-" I
numto .... tor
"';;: I numeoroiltor - df'nOllllnalor
"""-.'011•• 11.'
Fig I.
MOV
ADD
MOV
MOV
ADDC
MOV
CLR
MOVC
A divide algorithm.
A,#LOW(TABLE-601)
A,N'[J..O
DPL,A
A,#HIGH(TABLE - 601)
A,NLHI
DPH,A
A
A,@A+DPTR.
At this point the accumulator contains the 8-bit value of J.
It is perfectly reasonable to decide that a 599-byte look-up
table is unwieldy. lis advantages are speed and built-in error
correction. But a reasonably fast divide algorithm can be
written to this specific purpose, making use of a priori
knowledge about the sizes of the numbers that are involved in
the computation. It helps to know that in this example the
numerator is never going to be larger than 599 and the
denominator is always greater than the numerator.
A complete discussion of divide routines is beyond the
scope of this paper, but a suitable divide algorithm for this
specific application is shown in Fig. I. Reference [ II calls this
the Restoring- division algorithm. It is particularly well suite~
to the 8051, because" < " comparisons are greatly facilitated
by the 8051's CJNE (compare and jump if not equal)
instruction. CJNE A,B.rel. executes a relative jump if A does
not equal B. More importantly to this application, the
instruction sets the carry flag if A < B.
XI.
Since the clock signal is normally generated by a crystal
oscillator, the oscillator accuracy normally far exceeds the
quantizing error inherent in the finite (n-bit) resolution.
As was previously mentioned, interrupt response time does
not introduce an error into the measurement itself, but
variations in the interrupt response time can_ Interrupt
response time in the 8051 can vary from 3 to 8 machine cycles.
depending on what instruction is in progress at the time the
interrupt is generated. This would represent an error of ± 5
counts in the measured value of NT during a period
measurement. An error of ± 5 counts in NT does not
necessarily translate to ± 5 LSB's in the final result. but it
might still represent an error that exceeds the resolution.
In a direct frequency measurement variations in the interrupt response time would represent an error of ± 5 1'5 in the
sample time.
If these kh.ds of errors are unacceptable there are ways to
deal with them. In period measurements,' if the duty cycle of
the transducer is constant, the pulsewidth measurement
technique, previously described. can be used. Its advantage is
that it gates the timer off when the interrupt is generated.
rather than when the interrupt is responded to.
In other cases one can simply increase the sample time
above the minimum required to obtain the desired resolution.
For example, if the measurement requires 8-bit resolution. one
can design the software for an II-bit resolution and truncate
the result to 8 bits.
ACCURACY AND Rf.soLUTlON
The accuracy with which the 8051 will measure the
frequency or period of the tmnsducer signal depends on two
things: the accuracy of the clock oscillator and variations in
the interrupt response time.
REfERhNCES
III
llaviu rl al.• J)'Rirul Sy.'utms Wllh Algurilhm impiemrnlg/ion.
New Yurko Wiley. I~H.l.
270434-5
2-373
inter
ARTICLE
REPRINT
AR-526
ANALOO/DIGITAL PROCESSING WITH MICROCONTROLLERS
John Itatausky, Ira Horden, Lionel Smith
Application Engineers
Intel COfp.
5000 W. Williams Field Road
Chandler, AZ 85224
l-licrocontrollers
are
rapidly
becOMing
the
backbone
of silicon
computing syste... FfO. a technical
standpoint,
the
most
significant
attribute, aside from the inclusion of
RAM and
ROM,
that
segregates
a
microcontroller from a micfoprocessor
is I/O manipulation. In general, I/O
manipulation is an intimate part,of a
microcontroller's
architecture.
The
instruction set and architecture ofa
microcontroller
allows the CPU
to
directly control the I/O facilities on
the device. This is in difect contrast
to a microprocessor where the I/O is
essentiftlly a "sea~ of addresses anu it
is up to the hardwar'e des.igner to place
some type of I/O hardware in this I/O
·sea". It should be obvious that simply
adding ROM and RAM to a microprocessor
WILL NOT creale a microcontroller.
This intimate contact with I/O
gives the microcontroller a distinct
advantage over the microprocessor in
applications that are I/O intensive.
~icrocontrollers
can
test,
set,
complement, or clear I/O port pins much
faster than a microprocessor and they
can also make decisions, based on the
state of other hardware features, such
as timer/counters with equal speed.
This integration of I/O,
in
both
hardware
and
software
makes
the
microcontroller "ideal" for many types
of intelligent instrumentation.
4K ROM/EPROM - 8K ROM ON 8052
128 BYTES OF RAM - 256 ON THE 8052
2-16 BIT TIMER/COUNTERS - 3 ON THE 8052
FULL DUPLEX UART
5 VECTORED INTERRUPTS - 6 ON THE 8052
4 REGISTER BANKS
BIT MANIPULATION (BOOLEAN PROCESSOR)
32 DIRECTLY ADDRESSABLE I/O PINS
MULTIPLY AND PIVIDE INSTRUCTIONS
SUPpORTS 64K OR RAM AND ROM-128K TOTAL
'TABLE 1. A BREIF LISTING OF THE MCS-5l'S
FEATURE SET.
Intel's
MCS-5l
series
of
microcontrollers contain many features
that can be integrated directly into
many types of instruments. TABLE 1 is a
brief listing of these features. To
illustrate the power of the 8051 this
paper will elaborate on two techniques
for performing analog to digital (A to
D) conversion. Both of these examples
assume that some additional hardware is
attached to the I/O pins of the 8051.
S/A CONVERSION TECHNIQUES
Successive approximation analog ~o
digital conversion involves a "binary
search" of an unknowli voltage relative
to R "fixed" known ieference.
The
reference is selectively divided by
multiples of two until the desired
accuracy is reached, Figure 1 is' a
flowchart of a successive approximation
converter.
This
technique
usually
requires a digital to analog converter
to divide the reference voltage and a
voltage
comparator to
compare the
unknown
voltage
to ·the
"divided"
reference.
Digital
to
analog
converters and voltage comparators are
readily
available
and
relatively
inexpensive. A block diagram of an 8051
based A to D converter 'is shown in
Figure 2,.
Many industrial A to 0 converters
require 12 bits of accuracy. A 12 bit
converter provides good "dynamic range"
and is ~apable of resolving 1 part in
4096. If the applied input voltage
ranges from 0 to 10 Volts, a 12 bit
converter can resolve 2.4 millivolts
within this range.
The theoretical
accuracy of a 12 bit converter is .024'
+/- 1/2 least significant bit.
The power of the 8051 in this type
of application is best revealed by
examining the software
required to
implement the successive approximation
algorithm. The routine for the 8051 is
shown in Table 2.
The execution times given assume ,a
12 Mhz crystal. Compare this to the
following routine which is a 4 Mhz Z-80
2-374
AR-526
TABLE 2. SUCCESSIVE APPROXIMATION
ROUTINE FOR THE 8051.
INSTRUCTION
.
BYTES
TIME
; CLEAR PORT PINS
;
YES
MOV
ANL
OOKE
P1,10
P2,IOFOH
3
3
2
2
2
1
2
1
1
2
1
1
;
;START CONVERSION
Ll.
L2:
110
L3:
L4:
L5:
FIGURE I. sucaSSlfl APPIlOIIMTION
callY£RSIOII AlGOIUTtOI
L6:
L7:
•
•
0
.T
'1.
'1.1
'1.2
'1.
'1 •
LB.
'1.
liT 4
liT 5
'1.
In I
In 7
'1.
L9:
LID:
8
0
5
A
a
1
I
8
7
5
1
T
0
,
0
It.
PI.
PI.
Lll:
liT.
2
2
1
1
2
1
1
2
1
1
2
1
1
2
1
1
3
2
2
3
2
2
3
2
2
3
2
2
3
2
2
3
1
1
·2
1
1
2
1
1
2
2
1
2
1
1
2
L12: CONVERSION CCMPLETE
MAUll
--
3
2
2
3
2
2
3
2
2
3
2
2
3
2
2
3
2
,
liT'
liT 10
I
T
PI_I.
SETB
P2.3
P2.4,Ll
JNB
CLR
P2.3
"SETB
P2.2
JNB
P2.4,L2
CLR
P2.2
SETB
P2.1
P2.4,L3
JNB
CLR
P2.1
SETB
P2.0
P2.4,L4
JNB
CLR
P2.0
SETB
P1.7
JNB
P2.4,L5
CLR
P1.7
SETB
P1.6
JNB
P2.4,L6
CLR
P1.6
SETB
Pl.S
JNB
P2.4,L7
CLR
Pl.S
SETB
P1.4
JNB
P2.4,LB
CLR
P1.4
SETB
P1.3
JNB
P2.4,L9
Pl.3 ,
CLR
SETB
P1.2
JNB
P2.4,LlO
P1.2
CLR
SETB
P1.1
P2.4,Lll
JNB
CLR
, Pl.1
SETB
P1.0
JNB
P2.4,Ll2
CLR
P1.0
TOTAL
IIIr
90
HOTE: '1'lMIHG IS 'l'YPICAL
WORST CASE • 52 US
OST CUS • 40 US
MALOlII
ILOCIt 0 _ 01 _ 1 f t _"IIIATIOI • TO D _
2-375
46 US
intJ
AR-526
executing the same algorithm with the D
to A hardware attached to an I/O port
is shown in Table 3 (assume that all
bits on PORT3 are grounded, except the
comparator ihput).
timel. This
is because the Z-80's
memory oriented BIT instructions are
VERY slow, requiring between 3 and 5
microseconds with a 4 Mhz clockl
This is not to say that the Z-80
isn't a credible 8-bit processor. The
weakness is that decisions (i.e. JUMPS)
cannot be made directly on the state of
a given I/O pin. JUMP instructions, on
most processors, are made on the state
of the flags
after some type of
logical or arithmetic cperationl This
means that information must be moved to
an internal CPU
register before a
decision can be made. This -moving- of
information back and forth
between
internal registers and I/O makes the
microprocessor
quite
inefficient,
relative to the microcontroller when
I/O manipulation is involved.
Note
that with the 8051 algorithm never
-moves- data from one location
to
another - it directly sets,.. tests, and
clears bits. This characteristic gives
the
8051
its
distinct
execution
advantage.
TABLE 3. SUCCESSIVE APPROXIMATION
ROUTINE FOR THE Z-80.
INSTRUCTION
,,CLEAR PORT PINS
LD
OUT
OUT
A,O
(PORT1) ,A
(PORT2) ,A
,: START CONVERSION
A,08H
LD
OUT
IN
OR
IN
JP
AND
Ll: OR
OUT
IN
OR
IN
JP
AND
L2: OR
(PORT2) ,A
A, (PORT3)
A
A, (PORT2)
Z,Ll
OF7H
04H
(PORT2) ,A
A, (PORT3)
A
A, (PORT2)
Z,L2
OFBH
028
BYTES
TIME
2
2
2
1.75
2.75
2.75
2
2
2
1
2
3
2
2
2
2.
1
2
1.75
2.75
2.75
1.00
2.75
2.50
1.75
1.75
2.75
2.75
1.00
2.75
2.50
1.75
1.75
3
2
2
Another strength of the 8051 in
this type of· application, relates to
the fact that I/O port pins can be set,
cleared, complemented, and tested with
the same speed that a microprocessor
can act on it's internal registers.
Note that
the. 8051
takes only 1
microsecond to fetch an opcode and set
or· clear a port pin. A microprocessor
must first fetch and decode the opcode,
then place
the appropriate I/O or
memory address on the bus, then perfor~
the necessary operation. All of this
-communication- over the microprocessor
bus
significantly
slows down
the
microprocessor.
REPEAT BETWEEN Ll AND L2 10
MORE TIMES AND SB'!'/RESET THE
APPROPRIATE I/O BITS
DUAL SLOPE INTEGRATING CONVERTER
TOTAL
179
180 US
AGAIN TIMING IS TYPICAL
WORST CAST • 190.25 US
BEST CASE • 169.25 US
One . .y argue that by -aemory
. .pping- tbe I-80's I/O ports . tbe
execution tt.e
could
be
enhanced
because the u.er could take advantage
of the I-80's SB'!' and RESB'!' ae.ory BIT
instruction.. In reality, a few bYtes
of ae.ory are saved, but very little
Integrating A to D converters
operate by
an indirect method
of
converting a voltage to a time period,
then measuring the time period with a
counter. Integrating techniques
are
quite slow, relative to
successive
approximation, but they are capable of
providing very accurate measurements 5 1/2 or .ore decimal 4igits - if
proper analog tecbniques are employed.
Tbey also bave the added advantage of
allowing the integration period to be a
aultiple of 60 Ba (16.67 as) which can
eliainate inaccuracies caused by the
aver pre ..nt -power line-. Virtually
all digital volt_ters use so.. type of
integrating .tecbnique. rigure 3 is a
block diegr. . of a typical integrating
2-376
AR-526
A to D converter.
UITEGlATOI
INT£WTOA
INPuT
INPUT
-'--_'V'I
l£RO-Cil05S
OUTPUT
-.--.J
..........._v,
____
J
AEF£R[~C[
VOLTAGE
VOLTAGE
!
C Auro ZERO
C AuTO ZERO
FIGURE 3.
INTEGRATING A TO D CONvERTEA
FICURE tAo
Figures 4A, 4B, and 4C show the
three typical phases involved in the
dual
slope
tech~ique.
Figure
4A
illustrates the - auto-zero phase. In
this phase the integrating "loop" is
closed and the offset of the analog
integrator is accumlated in C auto
zero. In Figure 4B, the input switch is
closed and the integrator integrates
the input voltage for a fixed time
period Tl. In figure 4C, thp reference
switch is closed and the intEgrator
integrates the reference voltage until
the comparator senses a zero crossing
condition. The time it takes for this
phase to occur is directly proportional
to the amplitute of the input voltage.
Additional circuitry can be added to
determine the polarity of the input
voltage, then switch in a refarence of
oppsite
polarity,
but
the
basic
technique remains the same.
The 8051 is an ideal controller
for -an intelligent integrating A to D
system. The 16 bit timer/counters can
provide better than 4
1/2 decimal
digits of accuracy, the serial port can
be used to transmit the analog reading
to a printer or another processor, the
CPU can be interrupted by the 60 Hz
line
80 conversions
can start at
percise intervals, and software can be
used to calculate and save average,
peak, or RMS readings.
type
port
to D
used
~ERO-CjllOSS
:JUTPUT
REFERENCE
Another "nice" benefit of this
of converter is that very few I/O
pins are required to control the A
bardware, 80 opto-isolators can be
to completely isolate the 8051
2·377
AUTO ZERO PHASE
'"TEGRATOR
INPUT
• •,
___
J
"'oJ
!EitO-Ci'OSS
OUTPIjT
REfERENCE
vOLTAGE
I
FlGUR! .1.
C AUTO ZEIO
INPUT INTEGRATION 'HASE
I.TEGIITOI
-:-:r ~
IIIPUT
ZERO.. C20SS
OUTPUT
IEFtUNCE
.OLTAGE
I
flCUlE OC.
C AUTO ZERO
IEFtIEIICE IITEGIITION ""SE
inter
AR ..526
"digital
system" from
the ·analog
hardware. Opto-isolatorc
ptovide an
additional "bonus" in that they may
provide
logical level
shifting if
needed by the analog circuitry. Figure
5 shows how an 8051 might be connected
to the analog sub-system. In practice,
the analog switches
can be almost
anything ranging from CMOS to VFETs.
The code needed to generate the "basic·
integrating A to D.function is shown in
Table 4.
and hardware su~port tools include incircuit emulators, an assembler, and a
high
level
language,
PLM-5l.
Presently, the 8051 is available in 3
technology "flavors"- HMOS II, HMOSEPROM, ,and CHMOS, so depending on your
individual application, you can have it
your way.
Timer interrupts could be used so
that the CPU could be doing other
things while the conversion was in
process. Note that very little CPU time
is needed to perform the actual A to 0
function.
'
TABLE 4. SOFTI'lARE FOR INTEGRATING
A TO 0 CONVERTER
,
,,START PROGRAM
,
MOV
MOV
,
CLR
TRO
,TURN TIMER OFF
THO,fHIGH TAZ
TLO,ILOW TAZ
,LOAD AUTO ZERO
,TIME
ANL
SETB
SETB
JNB
Pl,lOFOH
Pl.2
TRO
TFO,$
,MAKE
,AUTO
,TURN
,LOOP
CLR
CLR
TRO
TFO
,TURN TIMER OFF '
,RESET TOV FLAG
MOV
MOV
THO,'HIGH INTT ,LOAD INTEGRATION
TLO,'LOW INTT ,TIME
SETB
SETB
JNB
Pl.2
Pl.l
TRO
TFO,$
,END AUTO ZERO
,START INTEGRATION
,START TIMER
,WAIT FOR OVERFLOW
CLR
Pl.l
,END INTEGRATION
CONCLUSION
This paper illustrated possible·
methods of using the 8051 in A to 0
"instrumentation"
types
of
applications. The power of the 8051's
microcontroller architecture relates to
the fact that logical "decisions" can
be made directly on the state of the
resident I/O hardware. This fact alone
gives the 8051 a distinct advantage in
"bit intensive" applications. Software
,
,
,
CLR
A/D INACTIVE
ZERO PHASE
TIMER ON
TIL OVERFLOW
r NOW, INTEGRATE THE REFERENCE
r
SETB Pl.O
I
,AT THIS POINT TIMER 0 HAS A VALUE OF
,TI'lO, THE TIMER IS EQUAL TO ZERO, WHEN
I IT OVERFLOWS AND IT WAS INCREMENTED
,TI'lICE DURING THE LAST TI'lO INSTRUCTIONS
I
ISOLATORS OR
LEVEL SHI FTERS
INOW, WAIT FOR ZERO CROSS
I
JNB
Pl.1
'1.2
8051
,,TURN THE TIMER OFF
CLR
"
FlIiIIRE 5.
"PICAI. 8051 COIITROI.LED AfW.OG SUI.SYSTEII,
Pl.3,$
I.
'1.3
TRO
,NOW, TIMER 0 - Vin + 3 COUNTS
2-378
ASIC Family Application Note
&. Article Reprint
3
inter
AP-413
APPLICATION
NOTE
. July 1988
Using Intel's ASIC Core Cell to
Expand the Capabilities of an·
80C51-Based System.
MATT TOWNSEND
CPO TECHNICAL MARKETING MANAGER
@ Intel Corporation, 1988
3-1
Order Number: 240230-001
intJ
AP-413
its addressing modes, clean bus interface, on-chip peripherals, and code efficient instruction set operations
make it well suited to processor-like applications as
well. For processor applications, a designer forgoes
many of the "single chip" features in favor of the high
performance CPU functions of this architecture.
INTRODUCTION
Intel's new ASIC family of microcontroller core cells
extends the capability of the MCS®-51 product, and
allows the ASIC designer more flexibility than the popular microcontroller product. This note will discuss
many of the new design possibilities inherent to the
80C51 cell-based controller. This family of cells is
available with a variety of RAM and ROM configurations.
Cell Name
ROM
UC5100
UC51 04
UC51 08
UC5116
UC5200
UC5204
UC5208
UC5216
No ROM
4KROM
8KROM
16K ROM
No ROM
4KROM
8KROM
16K ROM
In order to fit the MCS-51 family microcontrollers into
an economical forty lead DIP or forty-four lead PLCC
package, Intel designed the standard product with
many of the device's functions sharing pins. The microcontroller designer must compare necessary functions
against the economics and performance required for a
given design. If external memory or memory mapped
I/O is required, then the use of the port 0 function is
not available. If the memory address is beyond the 256 '
byte boundary defined by the ADO- 7 Bus then all or
part of the port 2 function is not available. Likewise,
using peripheral functions like the counter input pins,
serial I/O, and interrupts eliminates port 3 functions.
While the MCS-51 family is one of the most popular
microcontrollers ever introduced, this shared functionality hinders its use in many applications. For example,
a "fully loaded" MCS-51-based design would generally
leave only one 8-bit port (Port 1) for the application's
I/O requirements.
RAM
128 Bytes
128 Bytes
128 Bytes
128 Bytes
256 Bytes
256 Bytes
256 Bytes
256 Bytes
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
Other documentation will address Intel's ASIC design
environment (see reference section).
The 80C51-based ASIC cell is part of a family of cellbased functions based on popular Intel standard products. Members of the 82Cxx microprocessor support
peripheral family (SP8254, SP8237, SP8259, SP8284,
SP82284, SP8288 and 'SP82288) are also available as
library elements. The standard product ASIC cores are
supported by a library of over 150 logic cells, representing a broad range of SSI, MSI, and I/O functions. Another class of cell library elements is designated Special
Functions. These cells are predefined complex functions such as RAM, Serial I/O, AID Converter, and a
Voltage Comparator. The Special Function and general
logic element cells can also be used without a standard
product core in the ASIC design. Any of the available
80CSI-based cores can be integrated with logic complexities up to 5000 gates.
The standard cell version of the 80C51 provides the
designer with 116 signals for connection to application
specific logic. These signals represent the full function
set 'of the MCS-51 ,architecture and virtually eliminate
any design trade-offs required to implement an application. Notice from Figure 1 that all of the I/O ports are
separated from the other functions. In the design example, the I/O are separated into their respective inputs
and outputs, leaving 32 inputs and 32 outputs for port
counections into the application's logic. The most immediate impact of demultiplexing the I/O of the device
is that much of the logic required to complete an application is eliminated. For example, when separating the
address from the data on the AD-bus, an octal latch is
required. For an 80C51-based core application, the designer uses the AO- 7 bus directly, thus saving approximately 100 gates. The fact that the 80C51-based core
has so many connections available does not mean an
application will be forced into higher pin count packages. A 8OC51-based ASIC can implement many system functions more economically than a discrete implementation. The design example illustrates a system
with over 280 interconnects that can be integrated into
one ASIC device. This application note will illustrate
the less obvious ways in which the core can be used.
80C51-BASED ASIC CORE
Although the 80C51-based core is functionally identical
to the standard 80C5IBH microcontroller, its use as a
cell in the ASIC library allows more flexibility in system design and partitioning.
Fignre 1 depicts the difference between the standard
pinout of the MCS-51 family and the ASIC core.' In
order to understand the enhancements (in an applications sense) made to the core it is useful to compare its
connections to the pinout of the standard product.
, The illustrations shown iri this note are independent of
the workstation platform used to implement the design.
Intel provides the complete test vectors necessary to
test the 80C51-based ASIC core, which have been derived from the standard product 80C51 test vector set.
The MCS-51 family embodies a very powerful architecture. While it was intended'as a "single chip solution"
3-2
AP-413
Vcc
PI. 1
P1.3
Pl.6
PiI.ilADiI
PiI.l ADI
RXD
PiI.2AD2
SCLK
PiI.3AD3
TXD
PiI.4AD4
MODE0
PIl.6AD6
RST
PIl.7 AD7
RXD P3.0
TXD 1"3.1
OP3i1-37,
IP21l-27
INTIlL
PIl.5 AD5
Pl.7
IP30-37
INT1L
OP21l-27
Til
Tl
EA
WRL
ALE
RDL
INTO P3.2
INT! P3.3
T0 P3.4
EAL
PSENL
T! P3.5
ALE
WR P3.6
P2
IP10-17
BOC51
8ASED
ASIC
CORE
OP10-17
IP00-07
OP00-07
P2EXT
A0-A15
RD P3.7
XTAL2
RESET
XTALI
VSS
ERST
EAD81l-7
CLK
nCLK
TADBOE
AD80-7
240230-1
240230-2
Figure 1. Comparing 80C51 Pin Assignments to Core Connections
RECONSTRUCTION OF STANDARD
PRODUCT 1/0
When designing the 80C51-based ASIC core, Intel removed the pin multiplexers and I/O functions of the _
80C51, and restructured them as companion cells.
Companion cells allow the ASIC designer to reconfig-
3-3
ure the ASIC cell to function exactly like the standard
product. Alternatively, the designer can choose to reconstruct a subset of the standard product I/O or select
no reconstruction at all. Consult the references for
more information about the use and function of Intel's
companion cells.
AP-413
A system reset, in many designs, employs an active low
logic level. Since the 8OC51's reset requires an active
high level, there is usually an inverter in the path to the
microcontroller. It was mentioned earlier in this section
that ERST must be brought directly from .the core to a
package pin. This is not entirely true; the inclusion of
the inverter is allowed.
MULTIPLE SOURCES OF RESET
Key to the 80C51's core-isolation test method is the
ability to put the core into a condition that can verify
the processor without the user's logic affecting the test.
ERST is vital to controlling the ability to put the core
based ASIC into test mode. It must be brought directly
from the core to a package pin. Interface is via the
PRESET companion cell. Because a dedicated reset pin
may be restrictive in many applications, a second reset
connection, RESET, has been included.
1/0 EXPANSION WITH THE
80C51·BASED CORE
For the standard MCS-51 product, the need for I/O
expansion is often due to the need for external memory
and/or port expansion. The designer's. use of the onchip peripherals (eg. Serial I/O or Interrupts) often
leaves only Port 1 intact.
Including this second reset connection allows the designer to simplify the overall ASIC design. Many applications require two sources of reset, usually a poweron-clear with a watchdog timer. Previously, the designer was faced with "ORing" an RC time constant circuit
with the timer logic, resulting in an implementation
which was not straightforward or cost effective. Figure
2 shows an 80C51-based ASIC implementation.
BaCS1
WOT WATCHDOG TIMER WOT
ClK
OUT
WOT PRESET
BASED
ASIC
CORE
L....---:IJ'te--+----10PfIIfII-fII7
~-------------------------+-------~P2
RESET.
PRESET
UJ~---r!_-~---__'i------~~
INVN (OPTIONAL)
Figure 2. Multiple Sources of Reset for 80CS1-Based ASIC Core
3-4
240230-3
inter
AP·413
....!2.
XTAL1
...!.!!.
XTAL2
..2
PI7
PI6
PIS
PI4
PI3
PI2
PII
PI0
RST
8051
.1..! EA/VOO
~
...!.!.
RXO
TXO
-# INTI
iNT~
-#
~
...1i
TI
T0
P27
P26
P25
P24
P23
P22
P21
P20
P07
P06
P05
P04
P03
P02
P01
P00
~
~
~
~
~
~
~
~
~
~
~
g..
~
E;-
g..
~
32
33
34
35
36
37
38
39
27
28
29
30
07
06
05
04
31
32
33
34
03
02
01
00
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PA0
?
PC7
PC6
PC5
PC4
PSEN
30
ALE
16
ViR 17
Rii
8255
4
-t---2
~
o
F-74LS74
C CL Q ~
-k~
.;...
.L
~
~
&
~
~
~
~
r1i-
~
I
5
Rii
36
ViR
8
AI
9
AS
RST
4
2 0 PR Q 5
~
PC3
PC2
PCI
PC0
PR Q
¥a-
~
~
.!!.
~
74LS74
C CL Q ~
...! CS
PB7
PB6
PB5
PB4
PB3 ~
20
PB2
PBI
PB0 l=-
~
,g.
r#-
'if
rt8
I
240230-4
Figure 3. Simple MCS®·51 1/0 Expansion with 8255
Figure 3 depicts one case where the 80C51 can gain an
expanded set of 1/0 ports. In addition to requiring additional package pins, this implementation would require more power supply capacity and passive components (bypass capacitors) than would be necessary if the
1/0 expansion were to be included on-chip with the
microcontroller. Not only is PC board size decreased,
but the overall system reliability increases with the
ASIC solution. In addition, the 8255 port expander,
being a highly flexible device, requires software to configure the device to the application.
this example, decoding is very simple and the component count is minimal.
PTNO
OPn.nl--------~
aocsi
BASED
ASIC
CORE
PTI
IPn.nl---------<
The simplest way to add 1/0 ports with the core is by
way of a direct connection from the core's IP or OP
signals through 1/0 functions selected from the cell library and connected to package pins. See.Figure 4. In
240230-5
Figure 4. Direct Port Connections
to ASIC Package Pins
3-5
infef
AP·413
become a "bit bucket". Figure 5 shows an example with
one 8-bit input port, and one 8-bit output port, both
memory-mapped. Note that while the 8255 contains
three 8-bit ports, an ASIC can be implemented with the
exact amount of functionality desired.
This technique represents the most silicon and program
code efficient way to implement I/O with the core. Program code is composed of MOV operations rather than
the MOVX needed for any Memory mapped I/O implementations. Logical operations to the port (ANL,
ORL, XRL) can still be used. It is not necessary to
update or maintain indirect pointers. Since quasi-bidirectional cells are not used, it is not necessary to set a
"1" to the port in order to set these cells. Eliminating
MOVX and port setup operations could result in significant codespace savings.
Implementing the full function set of the 8255 would
result in an increased gate count (550 gates) included
on the 80C51-based ASIC. While 550 gates can easily
be included on the same silicon chip, implementing the
"exact functionality" version using elements from the
cell library would consume only 100 gates.
The drawback to the direct approach is that program
code written for the 80C51 using memory mapped I/O
is not directly transportable to the core design. In most
cases, however, implementing I/O expansion that allows code transportability is a simple task with a
80C51-based ASIC.
ON-CHIP CLOCK GENERATION
In many designs, the built-in crystal oscillator of the
80C51 is not utilized because the clock signal must be
used for other system functions. However, the clock to
the 80C51 still must be generated and driven into the
Xl/X2 pins. A clock generator is required somewhere
in the system and is also used to clock many of the
system functions surrounding the microcontroller.
Most support peripherals are designed to be configurable for many different operating conditions. This is certainly true for a device like. the 8255 as well; the port
signals can be programmed as inputs, outputs, or bidirectional. In most applications the peripheral's setup is
never changed after initialization. Port pins are set to
either input, output or I/O. The peripheral's configuration is most often "set up" with data fields sent to a
configuration or command register. This register is located at one of the peripheral's selectable addresses.
For a cell-based implementation where code transportability is required, recreating an 8255-like function is
straightforward. Since all setup information is written
to one register and setup is not required because the
port signal directions are fixed, that one register can
For 80C51-based ASIC designs, all clocking functions,
including the clock generator, can be brought on-chip.
The advantages to doing so include enhanced reliability
and a less costly, more noise free design. Clock generation is accomplished by the companion cell POSC (or
POSC2 for frequencies between 16 MHz and 38 MHz)
which can be used to drive the TICLK input connection to the core. The POSC output can be sent to user
defined logic configured to generate other necessary
INVTD
PTlx8
ADB0-7~---------------~----------------'----C
8-BIT'
INPUT PORT
80CS1
BASED
ASIC
CORE
8-BIT
OU.TPUT PORT
RDLI--......
A0~----t
WRLI-----....,
240230-6
Figure 5. I/O Mapped Like Figure 3's 8255
3-6
inter
AP-413
clocks in a system. Where the POSC cell fan out is high
and might cause concerns about clock edge skew, a cell
like BUF2 can be used. For systems where it is required
that the signal be brought off-chip (formerly off-board),
the on-chip generated clocks can be sent to output cells
and on to package pins. Figure 6 depicts generation
flexibility and clock source for a 80C51-based ASIC
design.
SHARING THE TEST BUS
In order for Automatic Test Equipment (ATE) to exercise the 80C5J-based ASIC, the bus EADB must be
brought directly to package pins. A specially designed
I/O cell, PADB, must be directly connected to the
EADB bus to ensure testability of the core as well as
the user's logic.
Figure 6 illustrates a design which requires a high frequency clock to operate on a section of user-defined
logic. For this, cell POSC2 is selected for the ASIC
design and is set to 24 MHz. In order to meet clock
specifications for the core, this 24 MHz master clock is
divided down in order to provide the required 12 MHz.
As discussed in the 80C51-based ASIC data sheet, the
ATE must be able to drive the core's clock directly. For
test modes, the ATE-generated clock is driven to the
core's TICLK connection.
Requiring the EADB bus to appear as package pins
does not impose any design restrictions on 80C51-based
ASICs designed to access external memory or peripherals. If your design does not call for the EADB to access
external memory peripherals, the EADB may be multiplexed with user I/O. Contact your Intel Technology
Center for the best implementation for your application.
Intel supplies all test programs required to completely
test the ASIC core cell. Designers are required to supply test vectors that exercise their unique logic only.
Note that signal P2 is shown being used for the application's clocks. It is sent to other logic in the ASIC and to
a package pin as well.
6 MHz TO
APPS LOGIC BUF2
6MHz
SYSTEM CLOCK
FFT
2:1 MUX
CLK
TICLK
BCCSI
BASED
ASIC
CORE
TEST
24MHz
TO APPS
LOGIC
PRESET
RESET
~----------------------------~ERST
240230-7
Figure 6. Integrating System Timing onto 80C51-Based ASIC
3-7
inter
AP·413
OBSERVING THE CONTENTS
OF THE PROGRAM COUNTER
BOC51
BASED
ASIC
CORE
The 80C51-based ASIC core connections AO-AI5 always display the contents of the program counter (except in the case of MOVX instructions.) This feature
allows another level of real time control by monitoring
instruction events within the core. By attaching comparator circuitry to the program counter contents, signals can be generated to depict events within the program. Figure 7 shows such a circuit.
PTNO
UC5116IN
UPPER BK
OF ROt.!
240230-9
Figure 7. Signal which Designates when
Program Execution is in Upper 8K ROM
The discussions in this note are not intended to be an
exhaustive s~mmary of the range of design possibilities
available to the ASIC designer. Rather, it is hoped that
it encourages the thought process toward even ·more
innovative uses.
input is required. The system must control peripherals
external to this main assembly, resulting in a requirement for address decoder selection.
Note that adequate bypass capacitors are required due
to the clock speeds and the high number of pin connections. (There are 272 pins, not including the WDT and
Oscillator Blocks.) A multilayer PCB is also required to
compensate for the amount of wires needed to connect
all the components.
The following is an e~ample of an actual system problem and how it was resolved using a 80C51-based
ASIC. The example utilizes many of the techniques discussed above.
Figure 9.depicts the 80C51-based ASIC solution for the
design in Figure 8. Note that all of the circuitry in
Figure 8 is included on a single ASIC chip. Rather than
use memory-mapped I/O, the design has been converted to use the core's direct ports. Note that the 8255
function has been removed and instead the UC5116
port connections are used. Some minor software chan~
es are required, and signals required to access otT-chip
program memory have been provided. This figure do~s
not show all test pin requirements; however, no additional package pins will be required. For this example,
the designer could begin production runs with an
EPROM. Once the application code stabilized, it could
be developed and submitted to Intel for incorporation
into the core. In this example, most of the high speed
signals are contained within the ASIC, making the
watchdog timer unnecessary. Ifneeded, the overall cost
of including it on the ASIC (=500 gates) makes the
functions relatively inexpensive to keep.
DESIGN EXAMPLE
Figure 8 shows a typical MCS-51-based design, which
includes a port expander, timer/counter chip, a high
speed event counter and a low-cost EPROM containing
stable code. In this application, the 8031 controls a system based on numerous timed events. Many high speed
clocks are involved, making for a potentially noisy environment, and a watchdog timer has. been included to
provide for soft recoveries if the microprocessor program flow is upset. The watchdog circuitry is shown as
a high level block.
The design must take an accurate sample of events designated at the EVENT input. The 16-bit count is read
and processed under a timed interrupt designated by
and generated from one of the 8254 Timers. The counter chain must be clocked at 24 MHz in order for
unique and accurate event samples to occur.
Overall system pin requirements have decreased as
well. This 80C51-based ASIC can be produced using a
68-pin' PLCC which may reduce the bypass capacitor
requirements as well as the need for a multilayer PCB.
Another 8254 counter is programmed for single-shot
mode to provide for a strobe window for some circuitry
external to the PCB assembly. An 8-bit parallel data
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Comparing the two solutions:
Component Count
REFERENCE DOCUMENTATION
Discrete
80C51-ASIC
-25
1
3
1
Minimum PCB Layers
System Reliability
Power Supply Current
Medium
High
-3A
-30 rnA
Order
Description
Number
231816 - Introduction to Cell-Based Design
83002 - Cell-Based Design-Daisy Environment
830000 - Cell-Based Design-Mentor Environment
210918 - Embedded Controller Handbook
270535 -Embedded Control Applications
l=-fl.
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FIGURE 5. TEST MODE STRATEGY
is written by the microprocessor using the
external buses, but reads are serialized in the
PISO. We decided that serial output was
acceptable in fIfO test mode, however, because the
fiFO has only 64 locations to test (versus 1024 in
the OPRAM), and the words a:e 18 bits long, which
would require 18 extra multIplexers. Thus, for
the fIfO data, we left well enough alone.
RAM TESTABILITY
RAM testability is a special case, because a
RAM is inherently fully testable provided its data
and address buses are access i b1e, a long with the
'necessary control signals. The difficulty here is
that the RAMs are embedded in functional blocks
which, especially in the FIFO, tends to disguise
the inherent RAM accessibility.
Inside the OPRAM, the lK x 8 RAM is read
directly by the microprocessor using the external"
data and address buses, so observability is no
. problem. Writes, however, occur from the SIPO
during serial reception. It would be particularly
painful to test a lK RAM using serial writes, so a
modification was necessary to improve RAM
controllability. In test mode, the address
multiplexer is held to the address bus by
overriding the select line, and a set of eight
extra multiplexers were added to the data
demultiplexer to allow bidirectional data flow
into and out of the RAM. Thus, the SIPO circuit
is completely bypassed in test mode.
The FIFO RAM is addressed by one of two
counters in the operating mode, which presents a
problem unless we are willing to accept sequential
test addressing, or at least a very complex
address setup procedure. The solution was to
override the address bus with a multiplexer fed by
input pin signals. The data bus presented the
same problem as the OPRAM, but in reverse: data
CONClUS,ION
This serial bus controller chip was designed
using ASIC techniques in a very s~ort ~ime,
resulting in a quick prototype chIp whIch o~r
automotive customer could use to evaluate hIs
system design in a timely manner. The inclusion
of testability circuits further shortened the
engineering debug ti~e as we~l as ~he
manufacturing test tIme. ThIS project
demonstrates that standard cell design is an
attractive fast-turnaround methodology, and that a
good testability strategy provides ad~itional
benefits which outweigh the extra desIgn effort.
ACKNOWLEDGEMENT
The authors would like to thank Graham Tubbs, for
guiding us through the maze of ASIC design tools,
Oinesh Maheshwari and Keith Steele, ~ho helped
prepare our final layout for processIng, and
Mukund Patel and Magdiel Galan who helped us test
and debug the final chip.
3-15
RUPITM Application Notes
4
APPLICATION
NOTE
AP-281
July 1986
UPI-4S2 Accelerates iAPX 286
Bus Performance
CHRISTOPHER SCOTT
TECHNICAL MARKETING ENGINEER
INTEL CORPORATION
© Intel Corporation, 1988
Order Number: 292018-001
4-1
intJ
AP-281
INTRODUCTION
HOST-UPI-452 FIFO SLAVE
INTERFACE
The UPI-452 targets the leading problem in peripheral
to host interfacing, the interface of a slow peripheral
with a fast Host or "bus utilization". The solution is
data buffering to reduce the delay and overhead of
transferring data between the Host microprocessor and
I/O subsystem. The Intel CMOS UPI-452 solves this
problem by combining a sophisticated programmable
FIFO buffer and a slave interface with an MSC-51
based microcontroller.
The UPI-452 FIFO acts as ·a buffer between the external Host 80286 and the internal CPU. The FIFO allows
the Host - peripheral interface to achieve maximum decoupling of the interface. Each of the two FIFO channels is fully user programmable. The FIFO buffer ensures that the respective CPU, Host or internal CPU,
receives data in the same order as transmitted. Three
slave bus interface handshake methods are supported
by the UPI-452; DMA, Interrupt and Polled.
The UPI-452 is Intel's newest Universal Peripheral Interface family member. The UPI-452 FIFO buffer enables Host-peripheral communications to be through
streams or bursts of data rather than by individual
bYtes. In addition the FIFO provides a means of embedding commands within a stream or block of data.
This enables the system designer to manage data and
commands to further off-load the Host.
The interface between the Host 80286 and the UPI-452
is accomplished with a minimum of signals. The 8 bit
data bus plus READ, WRITE, CS, and AO-2 provide
access to all of the externally addressable UPI-452 registers including the two FIFO channels. Interrupt and
DMA handshaking pins are tied directly to the interrupt controller and DMA controller respectively.
The UPI-452 interfaces to the iAPX 286 microprocessor as a standard Intel slave peripheral device. READ,
WRITE, CS and address lines from the Host are used
to access all of the Host addressable UPI-452 Special
Function Registers (SFR).
DMA transfers between the Host and UPI-452 are controlled by the Host processors DMA controller. In the
example shown in Figure 1, the Host DMA controller
is the 82258 Advanced DMA Controller. An internal
DMA transfer to or from the FIFO, as well as between
other internal elements, is controlled by the UPI-452
internal DMA processor. The internal DMA processor
can also transfer data between Input and Output FIFO
channels directly. The description that follows details
the UPI-452 interface from both the Host processor's
and the UPI-452's internal CPU perspective.
.
The UPI-452 combines an MSC-51 microcontroller,
with 256 bytes of on~chip RAM and 8K bytes of
EPROM/ROM, twice that of the 80C51, a two channel
DMA controller and a sophisticated 128 byte, two
.channel, bidirectional FIFO in a single device. The
UPI-452 retains all of the 8OC51 architecture, and is
fully compatible with.the MSC-51 instruction set.
.This application note is a description of an iAPX 286 to
UPI-452 slave interface. Included is a discussion of the
respective timings and design considerations. This ap- .
plication note is meant as a supplement to the UPI-452
Advance Data Sheet. The user should consult the data
sheet for additional details on the various UPI-452
functions and features.
UPI-452 iAPX 286 SYSTEM
CONFIGURATION
One of the unique features of the UPI-452 FIFO is its
ability to distinguish between commands and data embedded in the same data block. Both interrupts and
status flags are provided to support this operation in
either direction of data transfer. These flags and interrupts are triggered by the FIFO logic independent of,
and transparent to either the Host or internal CPUs.
Commands embedded in the data block, or stream, are
called Data Stream Commands.
Programmable FIFO channel Thresholds are another
unique feature of the UPI-452. The Thresholds provide
for interrupting the Host only when the Threshold
number of bytes can be read or written to the FIFO
buffer. This further decouples the Host UPI-452 interface by relieving the Host of polling the buffer to determine the number of bytes that can be read or written. It
also reduces the chances of overrun and underrun errors which must be processed.
The interface described in this application note is
shown in Figure I, iAPX 286 UPI-452 System Block
Diagram. The iAPX 286 system is configured in a local
bus architecture design. DMA between the Host and
the UPI-452 is supported by the 82258 Advanced
DMA Controller. The Host microprocessor accesses all
UPI-452 externally addressable registers through address decoding (see Table 3, UPI-452 External Address
Decoding). The timings and interface descriptions below are given in equation form with examples of specific calculations. The goal of this application note is a set
of interface analysis equations. These equations are the
tools a system designer can use to fully utilize the features of the UPI-452 to achieve maximum system performance.
The UPI~452 also provides a means of bypassing the
FIFO, in both directions, for an immediate interrupt of
either the Host or internal CPU. These commands are
called Immediate Commands. A complete description
of the internal FIFO logic operation is given in the
FIFO Data Structure section.
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AP-281
Host read/write access of the FIFO. The internal CPU
sets the Slave Control (SLCON) SFR FIFO DMA
Freeze/Normal Mode (FRZ) bit high (= 1) to activate
Normal Mode. Ths causes the Slave Status (SSTAT)
and Host Status (HSTAT) SFR FIFO DMA Freeze
Mode bits to be set to Normal Mode. Table 2, UPI-4S2
Initialization Event Sequence Example, shows a summary of the initialization events described above.
UPI-4S2 INITIALIZATION
The UPI-4S2 at power-on reset automatically performs
a minimum initialization of itself. The UPI-4S2 notifies
the Host that it is in the process of initialization by
setting a Host Status SFR bit. The user UPI-4S2 program must release the UPI-4S2 from initialization for
the FIFO to be accessible by the Host. This is the minimum Host to UPI-4S2 initialization sequence. All further initialization and configuration of the UPI-4S2, including the FIFO, is done by the internal CPU under
user program control. No interaction or programming
is required by the Host 80286 for UPI-4S2 initialization.
Table 1_ FIFO Special Function
Register Default Values
At power-on reset the UPI-4S2 automatically enters
FIFO DMA Freeze Mode by resetting the Slave Control (SLCON) SFR FIFO DMA Freeze/Normal Mode
bit to FIFO DMA Freeze Mode (FRZ = "0"). This
forces the Slave Status (SSTAT) and Host Status
(HSTAT) SFR FIFO DMA Freeze/Normal Mode bits
to FIFO DMA Freeze Mode In Progress. FIFO DMA
Freeze Mode allows the FIFO interface to be configured, by the internal CPU, while inhibiting Host access
to the FIFO.
SFR Name
Label
Channel Boundary Pointer
Output Channel Read Pointer
Output Channel Write Pointer
Input Channel Read Pointer
Input Channel Write Pointer
Input Threshold
Output Threshold
CBP
ORPR
OWPR
IRPR
IWPR
ITH
OTH
Reset
Value
40H/64D
40H/64D
40H/64D
OOH/OD
OOH/OD
OOH/OD
01H/1D
Table 2. UPI·452 Initialization
Event Sequence Example
Event Description
SFR/bit
Power-on Reset
The MODE SFR is forced to zero at reset. This disables, (tri-states) the DRQIN/INTRQIN, DRQOUT/
INTRQOUT and INTRQ output pins. INTRQ is inhibited from going active to reflect the fact that a Host
Status SFR bit, FIFO DMA Freeze Mode, is active. If
the MODE SFR INTRQ configure bit is enabled
( = 'I '), before the Slave Control and Host Status SFR
FIFO DMA Freeze/Normal Mode bit is set to Normal·
Mode, INTRQ will go active immediately.
UPI-4S2 forces FIFO DMA
SLCON FRZ = 0
Freeze Mode (Host access to
FIFO inhibited)
UPI-4S2 forces Slave Status and SSTAT SSTS = 0
HSTAT HST1 = 1
Host Status SFR to FIFO DMA
Freeze Mode In Progress
UPI-4S2 forces all SFRs,
including FIFO SFRs, to default
values.
The first action by the Host following reset is to read
the UPI-4S2 Host Status SFR Freeze/Normal Mode
bit to determine the status of the interface. This may be,
done in response to a UPI-4S2 INTRQ interrupt, or by
polling the Host Status SFR. Reading the Host Status
SFR resets the !NTRQ line low.
MODEMD4 = 1
• UPI-4S2 user program enables
INTRa, INTRa goes active, high
Any of the five FIFO interface SFRs, as well as a variety of additional features, may be programmed by the
internal CPU following reset. At power-on reset, the
five FIFO Special Function Registers are set to their
default values as listed in Table 1. All reserved location
bits are set to one, all other bits are set to zero in these
three SFRs. The FIFO SFRs listed in Table 1 can be
programmed only while the UPI-4S2 is in FIFO DMA
Freeze Mode. The balance of the UPI-4S2 SFRs default
values and descriptions are listed in the UPI-4S2 Advance Data Sheet in the Intel Microsystems Component Handbook Volume II and Microcontroller Handbook.
• UPI-4S2 user program initializes
any other SFRs; FIFO, Interrupts,
Timers/Counters, etc.
• Host READ's UPI-4S2 Host
Status (HSTAT) SFR to
determine interrupt source,
INTRa goes low
User program sets Slave Control SLCON FRZ = 1
SFR to Normal Mode (Host
access to FIFO enabled)
UPI-4S2 forces Slave and Host
Status SFRs bits to Normal
Operation
• Host polls Host Status SFR to
determine when it can access the
FIFO
- or• Host waits for UPI-452 Request
for Service interrupt to access
FIFO
The above sequence is the minimum UPI-4S2 internal
initialization required. The last initialization instruction
must always set the UPI-4S2 to Normal Mode. This
causes the UPI-4S2 to exit Freeze Mode and enables
• user option
4-4
SSTAT SST5 = 1
HSTAT HST1 = 0
AP-281
Commands can be used to structure or dispatch the
data by defining the start and end of data blocks or
packets, or how the data following a DSC is to be processed.
FIFO DATA STRUCTURES
Overview
A Data Stream Command (DSC) acts as an internal
service routine vector. The DSC generates an interrupt
to a service routine which reads the DSC. The DSC
byte acts as art address vector to a user defined service
routine. The address can be any program or data memory location with no restriction on the number of DSCs
or address boundaries.
The UPI-452 provides three means of communication
between the Host microprocessor and the UPI-452 in
either direction;
Data
Data Stream Commands
Immediate Commands
Data and Data Stream Commands (DSC) are transferred between the Host and UPI-452 through the UPI452 FIFO buffer. The third, Immediate Commands,
provides a means of bypassing the FIFO entirely. These
three data types are in addition to direct access by either Host or Internal CPU of dedicated Status and
Control Special Function Registers (SFR).
A Data Stream Command (DSC) can also be used to
clear data from the FIFO or "FLUSH" the FIFO. This
is done by appending a DSC to the end of a block of
data entered in the FIFO which is less than the programmed threshold number of bytes. The DSC will
cause an interrupt, if enabled, to the respective receiving CPU. This ensures that a less than Threshold number of bytes in the FIFO will be read. Two conditions
force a Request for Service interrupt, if enabled, to the
Host. The first is due to a Threshold number of bytes
having been written to the FIFO OUtput channel; the
second is if a DSC is written to the Output FIFO channel. If less than the Threshold number of bytes are written to the Output FIFO channel, the Host Status SFR
flag will not be set, and a Request for Service interrupt
will not be generated, if enabled. By appending a DSC
to end of the data block, the FIFO Request for Service
flag and/or interrupt will be generated.
The FIFO appears to both the Host 80286 and the internal CPU as 8 bits wide. Internally the FIFO is logically nine bits wide. The ninth bit indicates whether the
byte is a data or a Data Stream Command (DSC) byte;
o = data, 1 = DSC. The ninth bit is set by the FIFO
logic in response to the address specified when writing
to the FIFO by either Host or internal CPU. The FIFO
uses the ninth bit to condition the UPI-452 interrupts
and status flags as a byte is made available for a Host or
internal CPU read from the FIFO. Figures 2 and 3
show the structure of each FIFO channel and the logical ninth bit.
An example of a FIFO Flush application is a mass storage subsystem. The UPI-452 provides the system interface to a subsystem which supports tape and disk storage. The FIFO size is dynamically changed to provide
the maximum buffer size for the direction of transfer.
Large data blocks are the norm in this application. The
FIFO Flush provides a means of purging the FIFO of
the last bytes of a transfer. This guarantees that the
block, no matter what its size, will be transmitted out of
the FIFO.
It is important to note that both data and DSCs are
actually entered into the FIFO buffer (see Figures 2
and 3). External addressing of the FIFO determines the
state of the internal FIFO logic ninth bit. Table 3 shows
the UPI-452 External Address Decoding used by the
Host and the corresponding action. The internal CPU
interface to the FIFO is essentially identical to the external Host interface. Dedicated internal Special Function Registers provide the interface between the FIFO,
internal CPU and the internal two channel DMA processor. FIFO read and write operations by the Host and
internal CPU are interleaved by the UPI-452 so they
appear to be occurring simultaneously.
Immediate Commands allow more direct communication between the Host processor and the UPI-452 by
bypassing the FIFO in either direction. The Immediate
Command IN and OUT SFRs are two more unique
address locations externally and internally addressable.
Both 'DSCs and Immediate Commands have internal
interrupts and interrupt priorities associated with their
operation. The interrupts are enabled or disabled by
setting corresponding bits in the Slave Control
(SLCON), Interrupt Enable (IEC), Interrupt Priority
(IPC) and Interrupt Enable and Priority (IEP) SFRs. A
detailed description of each of these may be found in
the UPI-452 Advance Information Data Sheet.
The ninth bit provides a means of supporting two data
types within the FIFO buffer. This feature enables the
Host and .uPI-452 to transfer both commands and data
,while maintaining the decoupled interface a FIFO buffer provides. The logical ninth bit provides both a means
of embedding commands within a block of data and a
means for the internal CPU, or external Host, to discriminate between data and commands. Data or DSCs
may be written in any order desired. Data Stream
4-5
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AP·281
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292018-2
Figure 2. Input FIFO Channel Functional Diagram
4-6
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AP-281
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292018-3
Figure 3. Output FIFO Channel Functional Diagram
4-7
Ap·281
Table 3. UPI·452 External Address Decoding
DACK
CS
A2
A1
AO
1
1
1
0
X
X
X
No Operation
READ
No Operation
0
0
0
Data or DMA from
Output FIFO Channel
Data or DMA to
Input FIFO Channel
1
0
0
0
1
Data Stream Command
from Output FIFO
Channel
Data Stream Command
to Input FIFO
Channel
1
0
0
1
0
Host Status SFR
Read
Reserved
1
0
0
1
1
Host Control SFR
Read
Host Control SFR
Write
1
0
1
0
0
Immediate Command
SFR Read
Immediate Command
SFRWrite
1
0
0
1
1
Reserved
X
X
X
X
Reserved
X
DMA Data from
Output FIFO Channel
DMA Data to Input
FIFO Channel
Below is a detailed description of each FIFO channel's
operation, including the FIFO logic response to the
ninth bit, as a byte moves through the channel. The
description covers each of the three data types for each
channel. The details below provide a picture of the various FIFO features and operation. By understanding the
FIFO structure and operation the user can optimize the
interface to meet the requirements of an individual design.
WRITE
UPI·452 Internal Write to the FIFO
The internal CPU writes data and Data Stream Commands into the FIFO through the FIFO OUT (FOUT)
and Command OUT (COUT) SFRs. When a Threshold number of bytes has been written, the Host Status
SFR Output FIFO Request for Service bit is set and an
interrupt, if enabled, is generated to the Host. Either
the INTRQ or DRQOUT/INTRQOUT output pins
can be used for this interrupt as determined by the
MODE and Host Control (HCON) SFR setting. The
Host responds to the Request for Service interrupt by
reading the Host Status (HSTAT) SFR to determine
the source of the interrupt. The Host then reads the
Threshold number of bytes from the FIFO. The internal CPU may continue to write to the FIFO during the
Host read of the FIFO Output channel.
OUTPUT CHANNEL
This section covers the data path from the internal
CPU to the HOST. Data Stream Command or Immediate Command processing during Host DMA Operations is covered in the DMA section.
4-8
AP-281
Data Stream Commands may be written to the Output
FIFO channel at any time during a write of data bytes.
The write instruction need only specify the Command
Out (COUT) SFR in the direct register instruction
used. Immediate Commands may also be written at any
time to the Immediate Command OUT (IMOUT) SFR.
The Host reads Immediate Commands from the Immediate Command OUT (IMOUT).
The most efficient Host read operation of the FIFO
Output channel is through the use of Host DMA. The
UPI-452 fully s1,lpports external DMA handshaking.
The MODE and Host Control SFRs control the configuration of UPI-452 Host DMA handshake outputs. If
Host DMA is used the Threshold Request for Service
interrupt asserts the UPI-452 DMA Request
(DRQOUT) output. The Host DMA processor acknowledges with DACK which acts as a chip select of
the FIFO channels. The DMA transfer would stop
when either the threshold byte count had been read, as
programmed in the Host DMA processor, or when the
DRQOUT output is brought inactive by the UPI-4S2.
The internal CPU can determine the number of bytes to
write to the FIFO Output channel in one of three ways.
The first, and most efficient, is by utilizing the internal
DMA processor which will automatically manage the
writing of data to 'avoid Underrun or Overrun Errors.
The second is for the internal CPU to read the Output
FIFO channels Read and Write Pointers and compare
their values to determine the available space. The third
method for determining the available FIFO space is to
always write the programmed channel size number of
bytes to the Output FIFO. This method would use the
Overrun Error flag and interrupt to halt FIFO writing
whenever the available space was less than the channel
size. The interrupt service routine could read the channel pointers to determine or monitor the available channel space. The time required for the internal CPU to
write data to the Output FIFO channel is a function of
the individual instruction cycle time and the number of
bytes to be written.
INPUT CHANNEL
This section covers the data path from the HOST to the
internal CPU or internal DMA processor. The details
of Data Stream Command or Immediate Command
processing during internal DMA operations are covered in the DMA section below.
Host Write to the FIFO
Host Read from the FIFO
The Host reads data or Data Stream Commands (DSC)
from the FIFO in response to the Host Status
(HSTAT) SFR flags and interrupts, if enabled. All
Host read operations access the same UPI-452 internal
I/O Buffer Latch. At the end of the previous Host
FIFO read cycle a byte is loaded from the FIFO into
the I/O Buffer Latch and Host Status (HSTAT) SFR
bit 5 is set or cleared (I = DSC, 0 = data) to reflect
the state ofthe byte's FIFO ninth bit. If the FIFO ninth
bit is set (= I) indicating a DSC, an interrupt is generated to the external Host via INTRQ pin or
INTRQIN/INTRQOUT pins as determined by Host
Control (HCON) SFR bit 1. The Host then reads the
Host Status (HSTAT) SFR to determine the source of
the interrupt.
'
4-9
The Host writes data and Data Stream Commands into
the FIFO through the FIFO IN (FIN) and Command
IN (CIN) SFRs. When a Threshold number of bytes
has been read out of the Input FIFO channel by the
internal CPU, the Host Status SFR Input FIFO Request for Service bit is set and an interrupt, if enabled,
is generated to the Host. The Input FIFO Threshold
interrupt tells the Host that it may write the next block
of data into the FIFO. Either the INTRQ or DRQIN/
INTRQIN output pins can be used for this interrupt as
determined by the MODE and Host Control (HCON) .
SFR settings. The Host may continue to write to the
FIFO Input channel during the internal CPU read of
the FIFO. Data Stream Commands may be written to
the FIFO Input channel at any time during a write of
data bytes. Immediate Commands may also be written
at any time to the Immediate Command IN (IMIN)
SFR.
inter
Ap·281
The Host also has three methods for determining the
available FIFO space. Two are essentially identical to
that of the internal CPU. They involve reading the
FIFO Input channel pointers and using the Host Status
SFR Underrun and Overrun Error flags and Request
for Service interrupts these would generate, if enabled
in combination. The third involves using the UPI-452
Host DMA controller handshake signals and the programmed Input FIFO Threshold. The Host would receive a Request for Service interrupt when an Input
FIFO channel has a Theshold number of bytes able to
be written by the Host. The Host service routine would
then write the Threshold number of bytes to the FIFO.
If a Host DMA is used to write to the FIFO Input
channel, the Threshold Request for Service interrupt
could assert the UPI-452 DRQIN output. The Host
DMA processor would assert DACK and the FIFO
write would be completed by Host the DMA processor.
The DMA transfer would stop when either the Threshold byte count had been written or the DRQIN output
was removed by the UPI-452. Additional details on
Host and internal DMA operation is given below.
Internal Read of the FIFO
At the end of an internal CPU read cycle a byte is
loaded from the FIFO butTer into the FIFO IN/Command IN SFR and Slave Status (SSTAT) SFR bit 1 is
set or cleared (1 = data, 0 = DSC) to reflect the state
of the FIFO ninth bit. If the byte is a DSC, the FIFO
ninth bit is .set (= 1) and an interrupt is generated, if
enabled, to the Internal CPU. The internal CPU then
reads the Slave Status (SSTAT) SFR to determine the
source ofthe interrupt.
,
Immediate Commands· are written by the Host and
read by the internal CPU through the Immediate Com~
mand IN (IMIN) SFR. Once· written, an Immediate
Command sets the Slave Status (SSTAT) SFR flag bit
and generates an interrupt, if enabled, to the internal
CPU. In response to the interrupt the internal CPU
reads the Slave Status (SSTAT) SFR to determine the
source of the interrupt and service the Immediate Command.
FIFO INPUTIOUTPUT CHANNEL SIZE
Host
The Host does not have direct control of the FIFO
Input or Output channel sizes or configuration. The
Host can, however, issue Data Stream Commands or
Immediate Commands. to the UPI-452 instructing the
UPI-452 to reconfigure the FIFO interface by invoking
FIFO DMA Freeze Mode. The Data Stream Command or Immediate Command would be a vector to a
service routine which performs the specific reconfiguration.
UPI-452 Internal
The default power-on reset FIFO channel sizes are listed in the "Initialization" section and can be set only by
the internal CPU during FIFO DMA Freeze Mode.
The FIFO channel size is selected to achieve the optimum application performance. The entire 128 byte
FIFO can be allocated to either the. Input or Output
channel. In this case the other channel consists of a
single SFRj FIFO IN/Command IN or FIFO OUT/
Command OUT SFR. Figure 4 shows a FIFO division
with a portion devoted to each channel. Figure 5 shows
a FIFO configuration with all 128 bytes assigned to the
Output channel.
The FIFO channel Threshold feature allows the user to
match the FIFO channel size and the performance of
the interual and Host data transfer rates. The programmed Threshold provides an elasticity to the data
transfer operation. An· example is if the Host FIFO
HOST CPU
FIFO
INPUT
CHANNEL
CHANNEL
BOUNDRY ~I-----t
POINTER
FIFO
(CBP)
OUTPUT
CHANNEL
FIFO IN SFR
INTERNAL
CPU
FIFO OUT SFR
HOST CPU
292018-4
Figure 4. Full Duplex FIFO Operation
4-10
infef
AP-281
HOST CPU
CHANNEL
BOUNDRY ~
POINTER
(CBP)
FIFO
INPUT
CHANNEL
-+1
FIFO IN SFR
1-+
INTERNAL
CPU
I+-L
FIFO OUT SFR
I+-
!
HOST CPU
292018-5
Figure 5. Entire FIFO Assigned to Output Channel
data transfer rate is twice as fast as the inte~al FIFO
DMA data transfer rate. In this example the FIFO Input channel size is programmed to be 64 bytes and the
Input channel Threshold is programmed to be 20 bytes.
The Host writes the first 64 bytes to the Input FIFO.
When the internal DMA processor has read 20 bytes
the Threshold interrupt, or DMA request (DRQIN), is
generated to signal the Host to begin writing more data
to the Input FIFO channel. The internal DMA processor continues to read data from the Input channel as
the Host, or Host DMA processor, writes to the FIFO.
The Host can write 40 bytes to the FIFO Input chan~
nels in the time it takes for the internal DMA processor
to read 20 more bytes from it. This will keep both the
Host and internal DMA operating at their maximum
rates without forcing one to wait for the other.
this example the default 64 bytes per channel might be
adequate for both channels.
INTERRUPT RESPONSE TIMING
Interrupts enable the Host UPI-452 FIFO buffer interface and the internal CPU FIFO buffer interface to
operate with a minimum of overhead on the respective
CPU. Each CPU is "interrupted" to. service the FIFO
on an as needed basis only. In configuring the FIFO
buffer Thresholds and choosing the appropriate internal DMA Mode the user must take into account the
interrupt response time for both CPUs. These response
times will affect the DMA transfer rates for each channel. By choosing FIFO channel Thresholds which reflect both the respective DMA transfer rate and the
interrupt response time the user will achieve the maximum data throughput and system bus decoupling. This
in turn will mean the overall available system bus bandwidth will increase.
Two methods of managing the FIFO size are possible;
fixed and variable channel size. A fixed channel size is
one where the channel is configured at initialization
and remains unchanged throughout program execution.
In a variable FIFO channel size, the configuration is
changed dynamically to meet the data transmission requirements as needed. An example of a variable channel size application is the mass storage subsystem described earlier. To meet the demands of a large data
block transfer the FIFO size could be fully allocated to
the Input or Output channel as needed. The Thresholds
are also reprogrammed to match the respective data
transfer rates.
The following section describes the FIFO interrupt interface to the Host and internal CPU. It also describes
an analysis of sample interrupt response times for the
Host and UPI-452 internal cpu. These equations and
the example times shown are then used in the DMA
section to further analyze an optimum Host UPI-452
interface.
HOST
An example of a fixed channel size application might be
one which uses the UPI-452 to directly control a series
of stepper motors. The UPI-452 manages the motor
operation and status as required. This would include
pulse train, acceleration, deceleration and feedback.
The Host transmits motor commands to the UPI-452 in
blocks of 6-10 bytes. Each block of motor command
data is preceded by a command to the UPI-452 which
selects a specific motor. The UPI-452 transmits blocks
of data to the Host which provides motor and overall
system status. The data and embedded commands
structure, indiCating the specific motor, is the same. In
Interrupts to the Host processor are supported by the
three . UPI-452 output pins; INTRQ,· DRQIN/
INTRQIN and DRQOUT/INTRQOUT. INTRQ is a
general purpose Request For Service interrupt output.
DRQINIINTRQIN and DRQOUT/INRQOUT pins
are multiplexed to provide two special "Request for
Service" FIFO interrupt request lines when DMA is
disabled. A FIFO Input or Output channel Request for
Service interrupt is generated based upon the value programmed in the respective channel's Threshold SFRs;
Input Threshold (ITHR), and Output Threshold
4-11
AP-281
(OTHR) SFRs. Additional interrupts are provided for
FIFO Underrun and Overrun Errors, Data Stream
Commands, and Immediate Commands. Table 4 lis~s
the eight UPI-452 interrupt sources as they appear In
the HSTAT SFR to the Host ·processor.
To initiate the interrupt the UPI-452 activates the
INTRQ output. The interrupt acknowledge sequence
requires two bus cycles, 400 ns (10 MHz iAPX 286),
for the two INTA pulse sequence.
Equation 1. Host Interrupt Response Time
Table 4 UPI-452 to Host Interrupt Sources
HSTAT
SFR Bit
Interrupt Source
HST7
Output FIFO Underrun Error
HST6
Immediate Command Out SFR Status
HST5
Data Stream Command/Data at Output
FIFO Status
HST4
Output FIFO Request for Service Status
HST3
Input FIFO Overrun Error Condition
HST2
Immediate Comamnd In SFR Status
HST1
FIFO DMA Freeze/Normal Mode
Status
HSTO
Input FIFO Request for Service
The interrupt response time required by the Host" processor is application and system specific. In general, a
typical sequence of Host interrupt response events and
the approximate times associated with each are listed in
Equation 1.
The example assumes the hardware configuration
shown in Figure I, iAPX 286/UPI-452 Block Diagram,
with an 8259A Programmable Interrupt Controller.
The timing analysis in Equation 1 also assumes the following; no other interrupt is either in process or pending, nor is the 286 in a LOCK condition. The current
instruction completion time is 8 clock cycles (800 ns @
10 MHz), or 4 bus cycles. The interrupt service routine
first executes a PUSHA instruction, PUSH All General
Registers, to save all iAPX 286 internal registers. This
requires 19 clocks (or 2.0,""s @ 10 MHz), or 10 bus
cycles (rounded to complete bus cycle). The next service routine instruction reads the UPI-452 Host Status
SFR to determine the interrupt source~
It is important to note that any UPI-452 INTRQ interrupt service routine should ALWAYS mask for the
Freeze Mode bit first. This will insure that Freeze
Mode always has the highest priority. This will also
save the time required to mask for bits which are forced
inactive during Freeze Mode, before .checking the
Freeze Mode bit. Access to the FIFO channels by the
Host is inhibited during Freeze Mode. Freeze Mode is
covered in more detail below.
Action
Time
Bus
Cycles·
Current instruction execution
completion
800ns
INTA sequence
400 ns
Interrupt service routine (time
to host first READ of UPI-452) 2000 ns
10
Total Interrupt Response Time
16
2.3,""s
4
2
NOTE:
10 MHz iAPX 286 bus cycle, 200 ns each
UPI-4S2 Internal
The internal CPU FIFO interrupt interface is essentially identical to that of the Host to the FIFO. T~ree
internal interrupt sources support the FIFO operatIOn;
FIFO-Slave bus Interface Buffer, DMA Channel 0 and
DMA Channel 1 Requests. These interrupts provide a
maximum decoupling of the FIFO buffer and the internal CPU. The four different internal DMA Modes
available add flexibility to -the interface.
.
The FiFO-Slave Bus Interface interrupt response is
also similar to the Host response to an INTRQ Request
for Service interrupt. The internal CPU responds to the
interrupt by reading the Slave Status (SSTAT) SFR to
determine the source of the interrupt. 'This allows the
user to prioritize the Slav~ Status flag response to meet
the users application needs.
The internal interrupt response time is dependent on
the current instruction execution, whether the interrupt
is enabled, and the interrupt priority. In general, to finish execution of the current instruction, respond to the
interrupt request, push the Program Counter (PC) a~d
vector to the first instruction of the interrupt serVIce,
routine requires from 38 to 86 oscillator periods (2.38
to 5.38 ,""S @ 16 MHz). If the interrupt is due to an
Immediate Command or DSC, additional time is required to read the Immediate Command or DSC SFR
and vector to the appropriate service routine. This
means two service routines back to back. One service
routine to read the Slave Status (SSTAT) SFR to determine the source of the Request for Service interrupt,
and second the service routine pointed to by the Imme7
diate Command or DSC byte read from the respective
SFR.
4-12
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AP-281
Table 5. Host UPI·452
Data Transfer Performance
DMA
DMA is the fastest and most efficient way for the Host
or internal CPU to communicate with the FIFO buffer.
The UPI-452 provides support for both of these DMA
paths. The two DMA paths and operations are fully
independent of each other and can function simultaneously. While the Host DMA processor is performing
a DMA transfer to or from the FIFO, the UPI-452
internal DMA processor can be doing the same.
Below are descriptions of both the Host and internal
DMA operations. Both DMA paths can operate asynchronously and at different transfer rates. In order to
make the most of this simultaneous asynchronous operation it is necessary to calculate the two transfer rates
and accurately match their operations. Matching the
different transfer rates is done by a combination of accurately programmed FIFO channel size and channel
Thresholds. This provides the maximum Host and internal CPU to FIFO buffer interface decoupling. Below
is a description of each of the two DMA operations and
sample calculations for determining transfer rates. The
next section of this application note, "Interface Latency", details the considerations involved in analyzing effective transfer rates when the overhead associated with
each transfer is considered.
HOST FIFO DMA
DMA transfers between the Host and UPI-452 FIFO
buffer are controlled by the Host CPU's DMA controller, and is independent of the UPI-452's internal two
channel DMA processor. The UPI-452's internal DMA
processor supports data transfers between the UPI-452
internal RAM, external RAM (via the Local Expansion
Bus) and the various Special Function Registers including the FIFO Input and Output channel SFRs.
Processor &
Speed
8MHz
10 MHz
12.5 MHz
iAPX-286** 6 MHi
8MHz
10 MHz
iAPX-186*
Wait States:
DMA:
Back to Back
Two
Single
Cycle
READI
Cycle
WRITE's
0
0
1
0
1
2
N/A*
N/A*
N/A*
0
1
2
0
0
0
0
0
0
NOTES:
• iAPX 186 On-chip DMA processor is tWo cycle operation
only.
iAPX 286 assumes 82258 ADMA (or other DMA) running 286 bus cycles at 286 clock rate.
*.
In this application note system example, shown in Figure 1, DMA operation is assumed to be two bus cycle
I/O to memory or memory to I/O. Two cycle DMA
consists of a fetch bus cycle from the source and a store
bus cycle to the destination. The data is stored in the
DMA controller's registers before being sent to the destination. Single cycle DMA transfers involve a simultaneous fetch from the source and store to the destination. As the most common· method of I/O-memory
DMA operation, two cycle DMA transfers are the focus of this application note analysis. Equation 2 illustrates a calculation of the overall transfer rate between
the FIFO biIffer and external Host for a maximum
FIFO size transfer. The equation does not account for
the latency of initiating the DMA transfer.
Equation 2. Host FIFO DMA Transfer
Rate-Input or Output Channel
2
Cycle DMA Transfer-I/O (UPI-452) to System
Memory
FIFO channel size* (DMA READ/WRITE
FIFO time + DMA WRITE/READ Memory
Time)
128 bytes* (200 ns + 200 ns)
51.2 JLs
256 bus cycles'
The maximum DMA transfer rate is achieved by the
minimum DMA transfer cycle time to accomplish a
source to destination move. The minimum Host UPI452 FIFO DMA cycle time possible is determined by
the READ and WRITE pulse widths, UPI-452 command recovery times in relation to the DMA transfer
timing and DMA controller transfer mode used. Table
5 shows the relationship between the iAPX-286, iAPX186 and UPI-452 for various DMA as well as nonDMA byte by byte transfer modes versus processor frequencies.
NOTES:
*10 MHz iAPX 286, 200 ns bus cycles.
Host processor speed vs wait states required with UPI452 running at 16 MHz:
The UPI-452 design is optimized for high speed DMA
transfers between the Host and the FIFO buffer. The
4-13
inter
AP-281
UPI-452 internal FIFO buffer control logic provides
the necessary synchronization of the external Host
event and the internal CPU machine cycle during
UPI-452 RD/WR accesses. This internal synchronization is addressed by the TCC AC specification of the
UPI-452 shown in Figure 6. TCC is the time from the
leading or trailing edge of Ii UPI-452 RD/WR to the
same edge of the next UPI-452 RD/WR. The TCC
time is effectively another way of measuring the system
bus cycle time with reference to UPI-452 accesses.
The third handshake signal pin is DACK which is used
as a chip select during DMA data transfers. The UPI452 Host READ and WRITE input signals select the
respective Input and Output FIFO channel during
DMA transfers. The CS and address lines provide
DMA acknowledge for processors with onboard DMA
controllers which do not generate a DACK signal.
The iAPX 286 Block VO Instructions provide an alternative to two cycle DMA data transfers with approximately the same data rate. The String Input and Output instructions (INS & OUTS) when combined with
the Repeat (REP) prefix, modifies INS and OUTS to
provide a means of transferring blocks of data between
I/O and Memory. The data transfer rate using REP
INS/OUTS instructions is calc\llated in the same way
as two cycle DMA transfer times. Each. READ 'or
WRITE would be 200 ns in a 10 MHz iAPX 286 sys. tern. The maximum transfer rate possible is 2.5
MBytes/second. The Block I/O FIFO data transfer
calculation is the same as that shown in Equation 2 for
two cycle DMA data transfers including TCC timing
effects:
In the iAPX-286 10 MHz system depicted in this application note the bus cycle time is 200 ns. Alternate cycle
accesses of the UPI-452 during two cycle DMA operation yields a TCC time of 400 ns which is more than the
TCC minimum time of 375 ns. Back to back Host
UPI-452 READ/wRITE accesses may require wait
states as shown in Table 5. The difference between 10
MHz iAPX-186 and 10 MHz iAPX 286 required wait,
states is due to the number of clock cycles in the respective bus cycle timings. The four clocks in a 10 MHz
iAPX 186 bus cycle means a minimum TCC time of
400 ns versus 200 ns for a 10 MHz iAPX 286 with two
clock cycle zero wait state bus cycle.
FIFO Data Structure and Host DMA
DMA handshaking between the Host DMA controller
and the UPI-452,is supported by three pins on the UPI452;~IN/INTRQIN, ' DRQOUT/INTRQOUT
.and DACK. The DRQIN/INTRQIN and DRQOUT/
INTRQOUT outputs are two multiplexed DMA or interrupt request pins. The function of these pins is controlled by MODESFR bit 6 (MD6). DRQIN and
, DRQOUT provide a direct interface to the Host system
DMA controller (see Figure 1). In response to a
DRQIN or DRQOUT request, the Host DMA controller initiates control of the system. bus using HLD/
HLDA. The FIFO Input or Output channel transfer is
accomplished with a minimum of Host overhead and
system bus bandwidth.
During a Host DMA write to the FIFO, if a DSC is to
be written, the DMA transfer is stopped, the DSC is
written and the DMA restarted. During a Host DMA
read from the FIFO, if a DSC is loaded into the I/O
Buffer Latch the DMA request, DRQOUT, will be deactivated (see Figure 2 above). The Host Status
(HSTAT) SFR Data Stream Command bit is set and
the INTRQ interrupt output goes active, if enabled.
The Host responds to the interrupt as described above.
\ .....__-11
CS#
\
I
r--,-/~::_TC_C::::::::~l
/r----
RD#/WR# _ _ _ _-\{f4.
j
TRRjTWw ' :
TRV
---d
"'C>-------TCC
TRR/TW:
I,
.r
Symbol
Description
Var.Osc.
@16MHz
TCC
Command Cycle
Time
Command Recovery
Time
6· Tclcl
375 nsmin
75
75 nsmin
TRV
Figure 6. UPI-4S2 Command Cycle Timing
4-14
292018-6
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Ap·281
Once INTRQ is deactivated and the DSC has been read
by the Host, the DMA request, DRQOUT, is reasserted by the UPI-452. The DMA request then remains
active until the transfer is complete or another DSC is
loaded into the I/O Buffer Latch.
An Immediate Command written by the internal CPU
during a Host DMA FIFO transfer also causes the
Host Status flag and INTRQ to go active if enabled. In
this case the Immediate Command would not terminate
the DMA transfer unless terminated by the Host. The
INTRQ line remains active until the Host reads the
Host Status (HSTAT) SFR to determine the source of
the interrupt.
The net effect of a Data Stream Command (DSC) on
DMA data transfer rates is to add an additional factor
to the data transfer rate equation. This added factor is
shown in Equation 3. An Immediate Command has the
same effect on the data transfer rate if the Immediate
Command interrupt is recognized by the Host during a
DMA transfer. If the DMA transfer is completed before the Immediate Command interrupt is recognized,
the effect on the DMA transfer rate depends on whether the block being transmitted is larger than the FIFO
channel size. If the block is larger than the programmed FIFO channel size the transfer rate depends
on whether the Immediate Command flag or interrupt
is recognized between partial block transfers.
The FIFO configuration shown in Equation 3 is arbitrary since there is no way of predicting the size relative
to when a DSC would be loaded into the I/O Buffer
Latch. The Host DMA rate shown is for a UPI-452
(Memory Mapped or I/O) to 286 System Memory
transfer as described earlier. The equations do not ac- ,
count for the latency of intiating the DMA transfer.
Equation 3. Minimum host FIFO DMA Transfer
Rate Including Data Stream Command(s)
Minimum Host/FIFO DMA Transfer Rate wi DSC
FIFO size' Host DMA 2 cycle time transfer rate
+ iAPX 286 interrupt response time (Eq. # 1)
(32 bytes' (200 ns + 200 n8» + 2.3 JLs
15.1 JLs
75.5 bus cycles (@10 MHz iAPX286, 200 ns
bus cycle)
UPI-452 INTERNAL DMA PROCESSOR
The two identical internal DMA channels allow high
speed data transfers from one UPI-452 writable memory space to another. The following UPI-452 memory
spaces can be used with internal DMA channels:
Internal Data Memory (RAM)
External Data Memory (RAM)
Special Function Registers (SFR)
The FIFO can be accessed during internal DMA operations by specifying the FIFO IN (FIN) SFR as the
DMA Source Address (SAR) or the FIFO OUT
(FOUT) SFR as the Destination Address (DAR). Table 6 lists the four types of internal DMA transfers and
their respective timings.
Table 6. UPI·452 Internal DMA Controller Cycle Timings
Source
Destination
Internal Data
Mem.orSFR
Internal Data
Mem.orSFR
External Data
Mem.
'External Data
Memory
Internal Data
Mem.orSFR
External Data
Mem.
Internal Data
Mem.orSFR
External Data
Memory
Machine
Cycles"
@12MHz
@16MHz
1
1 JLs
750 ns
1
1 JL8
750 ns
1
1 JLs
750 ns
2
2 JLs
1.5 JLs
NOTES:
'External Data Memory DMA transfer applies to UPI-452 Local Bus only.
"MSC-51 Machine cycle = 12 clock cycles (TCLCL).
4-15
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AP-281
FIFO Data Structure and Internal DMA
INTERFACE LATENCY
The effect of Data Stream Commands and Immediate
Commands on the internal DMA transfers is essentially
the same as the effect on Host FIFO DMA transfers.
Recognition also depends upon the programmed DMA
Mode, the interrupts enabled, and their priorities. The
net internal effect is the same for each possible internal
case. The time required to respond to the Immediate or
Data Stream Command is a function of the instruction
time required. This must be calculated by the user
based on the instruction cycle time given in the MSC51 Instruction Set description in the Intel Microcontroller Handbook.
The interface latency is the time required to accommodate all of the overhead associated with an individual
data transfer. Data transfer rates between the Host system and UPI-452 FIFO, with a block size less than or
equal to the programmed FIFO channel size, are calculated using the Host system DMA rate. (see Host
DMA description above). In this case, the entire block
could be transferred in one operation. The total latency
is the time required to accomplish the block DMA
transfer, the interrupt response or poll of the Host
Status SFR response time, and the time required to initate the Host DMA processor.
It is important to note that the internal DMA processor
A DMA transfer between the Host and UPI-452 FIFO
with a block size greater than the programmed FIFO
channel size introduces additional overhead. This additional overhead is from three sources; first, is the time
to actually perform the DMA transfer. Second, the
overhead of initializing the DMA processor, third, the
handshaking between each FIFO block required to
transfer the entire data block. This could be time to
wait for the FIFO to be emptied and/or the interrupt
response time to restart the DMA transfer of the next
portion of the block. A fourth component may also be
the time required to respond to Underrun and Overrun
FIFO Errors.
modes and the internal FIFO logic work together to
automatically manage internal DMA transfers as data
moves into and out of the FIFO. The two most appropriate internal DMA processor modes for the FIFO are
FIFO Demand Mode and'FIFO Alternate Cycle Mode.
In FIFO Demand Mode, once the correct Slave Control and DMA Mode bits are set, the internal Input
FIFO channel DMA transfer occurs whenever the
Slave Control Input FIFO Request for Service flag is
set. The DMA transfer continues until' the flag is
cleared or when the Input FIFO Read Pointer SFR
(IRPR) equals zero. If data continues to be entered by
the Host, the internal DMA continues until an internal
interrupt of higher priority, if enabled, interrupts the
DMA transfer, the internal DMA byte count reaches
zero or until the Input FIFO Read Pointer equals zero.
A complete description of interrupts and DMA Modes
can be found in the UPI-452 Data Sheet.
Table 7 shows six typical FIFO Input/Output channel
sizes and the Host DMA transfers times for each. The'
timings shown reflect a 10 MHz system bus two cycle
I/O to Memory DMA transfer rate of 2.5 MBytes/second as shown in Equation 1. The times given would be
the same for iAPX 286 I/O block move instructions
REP INS and REP OUTS as described earlier.
DMAModes
Table 7. Host DMA FIFO Data Transfer Times
The internal DMA processor has four modes of operation. Each DMA channel is software programmable to,
operate in either Block Mode or Demand Mode. Demand Mode may be further programmed to operate in
Burst or Alternate Cycle Mode. BUIst Mode causes the
internal processor to halt its execution and dedicate its
resources exclusively to the DMA transfer. Alternate
Cycle Mode causes DMA cycles and instruction cycles
to occur alternately. A detailed description of each
DMA Mode can be found in the UPI-452 Data Sheet.
FIFO Size:
32
Full or Empty
% % % % %
Time
43
64
85
96
128 1 bytes
Fuller Empty
12.8 17.2 25.6 34.0 38.4 51.21
}Ls
Table 8 shows six typical FIFO Input/Output channel
sizes and the internal DMA processor data transfers
times for each. The timings shown are for a UPI-452
single cycle Burst Mode transfer at 16 Maz or 750 ns
per machine cycle in or out of the FIFO channels. The
4-16
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AP-281
machine cycle time is that of the MSC-51 CPU; 6
states, 2 XTAL2 clock cycles each or 12 clock cycles
per machine cycle. Details on the MSC-51 machine cycle timings and operation may be found in the Intel
Microcontroller Handbook.
Table 8. UPI-452 Internal DMA FIFO
Data Transfer Times
FIFO Size:
32
Full or Empty
% % % % %
~ime
43
64
85
I
96
128 bytes
Full or Empty
24.0 32.3 48.0 64.6 72.0 96.0
I
JLs
A larger than programmed FIFO channel size data
block'internal DMA transfer requires internal arbitration. The UPI-452 provides a variety of features which
support arbitration between the two, internal DMA
channels and the FIFO. An example is the internal
DMA processor FIFO Demand Mode described above.
FIFO Demand Mode DMA transfers occur continuously until the Slave Status Request for Service Flag is
deactivated. Demand Mode is especially useful for continuous data transfers requiring immediate attention.
FIFO Alternate Cycle Mode provides for interleaving
DMA transfers and instruction cycles to achieve a
maximum of software flexibility. Both internal DMA
channels can be used simultaneously to provide continuous transfer for both Input and Output FIFO channels.
Byte by byte transfers between the FIFO and internal
CPU timing is a function of t.he specific instruction cycle time. Of the 111 MCS-51 instructions, 64 require 12
clock cycles, 45 require 24 clock cycles and 2 require 48
clock cycles. Most instructions involving SFRs are 24
clock cycles except accumulator (for example, MOV
direct, A) or logical operations (ANL direct, A). Typical instruction and their timings are shown in Table 9.
Oscillator Period:
@
@
12 MHz
16 MHz
=
=
83.3 ns
62.5 ns
Table 9. Typical Instruction Cycle Timings
Instruction
MOV directt, A
MOV direct, direct
Oscillator
@12MHz @16MHz
Periods
12
24
1 JLs
2 JLs
750 ns
1.5 JLs
NOTE:
t Direct = 6-bit internal data locations address. This could
be an Internal Data RAM location (0-255) or a SFR [i.e., II
o port, control register. etc.]
Byte by byte FIFO data transfers introduce an additional overhead factor not found in internal DMA operations. This factor is the FIFO block size to be transferred; the number of empty locations in the Output
channel, or the number of bytes in the Input FIFO
channel. As described above in the FIFO Data Structure section, the block size would have to be determined by reading the channel read and write pointer
and calculating the space available. Another alternative
uses the FIFO Overrun and Underrun Error flags to
manage the transfers by accepting error flags. In either
case the instructions needed have a significant impact
on the internal FIFO data transfer rate latency equation.
A typical effective internal FIFO channel transfer rate
using internal DMA is shown in Equation 4. Equation
5 shows the latency using byte by byte transfers with an
arbitrary factor added for internal CPU block size calculation. These two equations contrast the effective
transfer rates when using internal DMA versus individual instructions to transfer 128 bytes. The effective
transfer rate is approximately four times as fast using
DMA versus using individual instructions (96 JLs with
DMA versus 492 JLs non-DMA).
Equation 4. Effective Internal FIFO
Transfer Time Using Internal DMA
Effective Internal FIFO Transfer Rate with DMA
FIFO channel size • Internal DMA Burst Mode
Single Cycle DMA Time
128 Bytes • 750 ns
96 JLs
Equation 5. Effective FIFO Transfer
Time Using Individual Instructions
Effective Internal FIFO Transfer Rate without DMA
FIFO channel size • Instruction Cycle Time +
Block size calculation Time
128 Bytes' (24 oscillator periods @ 16 MHz) +
20 instructions (24 oscillator period each
@ 16 MHz)
128 • 1.5 JLs + 300 JLs
492 JLs
FIFO DMA FREEZE MODE
INTERFACE
FIFO DMA Freeze Mode provides a means of locking
the Host out of the FIFO Input and Output channels.
FIFO DMA Freeze Mode can be invoked for a variety
of reasons, for example, to reconfigure the UPI-452 Local Expansion Bus, or change the baud rate on the serial channel. The primary reason the FIFO DMA Freeze
Mode is provided is to ensure that the Host does not
read from or write to the FIFO while the FIFO interface is being altered. ONLY the internal CPU has the
capability of altering the FIFO Special Function Registers, and these SFRs can ONLY be altered during
FIFO DMA Freeze Mode. FIFO DMA Freeze Mode
inhibits Host access of the FIFO while the internal
CPU reconfigures the FIFO.
4-17
inter
AP-281
FIFO DMA Freeze Mode should not be arbitrarily invoked while the UPI-452 is in normal operation. Because the external CPU runs asynchronously to the internal CPU, invoking freeze mode without first properly resolving the FIFO Host interface may have serious
consequences. Freeze Mode may be invoked only by
the internal CPU.
The internal CPU invokes Freeze Mode by setting bit 3
of the Slave Control SFR (SC3). This automatically
forces the Slave and Host Status SFR FIFO DMA
Freeze Mode to In Progress (SSTAT SST5 "7 0,
HSTAT SFR HSTI = 1). INTRQ goes active, if enabled by MODE SFR bit 4, whenever FIFO DMA
Freeze Mode is invoked to notify the Host. The Host
reads the Host Status SFR to determine the source of
the interrupt. INTRQ and the Slave and Host Status
FIFO DMA Freeze Mode bits are reset by the Host
READ of the Host Status SFR.
During FIFO DMA Freeze Mode the Host has access
to the Host Status and Control SFRs. All other Host
FIFO interface access is inhibited. Table 10 lists the
FIFO DMA Freeze Mode status of all slave bus interface Special Function Registers. The internal DMA
processor is disabled during FIFO DMA Freeze Mode
and the internal CPU has write access to all of the
FIFO control SFRs (Table 11).
If FIFO DMA Freeze Mode is invoked without stop-
ping the host, only the last two bytes of data written
into or read from the FIFO will be valid. The timing
diagram for disabling the FIFO module to the external
Host interface is illustrated in Figure 7. Due to this
synchronization sequence, the UPI-452 might not go
into FIFO D,MA Freeze Mode immediately after the
Slave Control SFR FIFO 7 DMA Freeze Mode bit
(SC3) is set = O. A special bit in the Slave Status SFR
(SST5) is provided to indicate the status of the FIFO
DMA Freeze Mode. The FIFO DMA Freeze Mode
INTRQ OR
DROIN/DROOUT
operations described in this section are only valid after
SST5 is cleared.
Either the Host or internal CPU can request FIFO
DMA Freeze Mode. The first step is to issue an Immediate Command indicating that FIFO DMA Freeze
Mode will be invoked. Upon receiving the Immediate
Command, the external CPU should compl~te servicing
all pending interrupts and DMA requests, then send an
Immediate Command back to the internal CPU acknowledging the FIFO DMA Freeze Mode request.
After issuing the first Immediate Command, the internal CPU should not perform any action on the FIFO
until FIFO DMA Freeze Mode is invoked. The handshaking is the same in reverse if the HOST CPU initiates FIFO DMA Freeze Mode.
After the slave bus interface is frozen, the internal CPU
can perform the operations listed below on the FIFO
Special Function Registers. These operations are allowed only during FIFO DMA Freeze Mode. Table 11
summarizes the characteristics of all the FIFO Special
Function Registers during Normal and FIFO DMA
Freeze Modes.
For FIFO
I. Changing the Channel Boundary
Reconfiguration
Pointer SFR.
2. Changing the Input and Output
Threshold SFR.
To Enhance the 3. Writing to the, read and write
testability
pointers of the Input and Output
FIFO's.
4. Writing to and reading the Host
Control SFRs.
5. Controlling some bits of Host and
Slave Status SFRs.
6. Reading the Immediate Command
Out SFR and Writing to the 1mm'ediate Command in SFR.
.J
RD#/WR#
INTRO
J ______ :__________________ _
:: : A FIFO RD/WR AnER
, • - • INTERFACE FREEZE IS
,
INVOKED WILL CAUSE'
HST3 OR HST7 TO BE SET
SC3
Hsn _ _ _ _ _ _ _ _ _ _ _ _ _...... SET
292018-7
NOTE:
Timing Diagram of disabling of FIFO Module-External Host Interface.
Figure 7. 'Disabling FIFO to Host Slave Interface Timing Diagram
4-18
inter
AP-281
The sequence of events for invoking FIFO DMA
Freeze Mode are listed in Figure 8.
4. The Immediate Command interrupt is responded to
immediately-highest priority-by Host and internal CPU.
1. Immediate Command to request FIFO DMA
Freeze Mode (interrupt)
5. Respective interrupt response times
a. Host (Equation 3 above) = approximately 1.6 jJ.s
b. Internal CPU is 86 oscillator periods or approximately 5.38 jJ.s worst case.
2. Host/internal CPU interrupt response/service
3. Host/internal CPU clear/service all pending
interrupts and FIFO data
4. Internal CPU sets Slave Control (SLCON)
FIFO DMA
Freeze Mode bit = 0, FIFO DMA Freeze
Mode, Host Status SF.R FIFO DMA Freeze
Mode Status bit = 1, INTRQ active (high)
5. Host READ Host Status SFR
Event
Immediate Command from Host
to UPI-452 to request FIFO DMA
, Freeze Mode (iAPX286 WRITE)
Time
0.30 jJ.s
Internal CPU interrupt response/
service
5.38 jJ.s
6. Internal CPU reconfigures FIFO SFRs
Internal CPU clears FIFO-128
bytes DMA
7. Internal CPU resets Slave Control (SLCON)
FIFO DMA
Internal CPU sets Slave Control
Freeze Mode bit
0.75 jJ.s
Immediate Command to HostFreeze Mode in progress Host
Immediate Command interrupt
response
2.3 jJ.s
"Freeze Mode bit = 1, Normal Mode, Host
Status FIFO DMA Freeze Mode Status bit =
o.
8. Internal CPU issues Immediate Command to
Host indicating that FIFO DMA Freeze Mode is
complete
Internal CPU reconfigures FIFO
SFRs
Channel Boundary Pointer SFR
Input Threshold SFR
Output Threshold SFR
or
Host polls Host Status SFR FIFO DMA Freeze
Mode bit to determine end of reconfiguration
Internal CPU resets Slave
Control (SLCON) Freeze Mode
bit = 1, Normal Mode, and
automatically resets Host Status
FIFO DMA Freeze Mode bit
Figure 8. Sequence of Events to Invoke
FIFO DMA Freeze Mode
EXAMPLE CONFIGURATION
Internal CPU writes Immediate
Command Out
An example of the time required to reconfigure the
FIFO 180 degrees, for example from 128 bytes Input to
128 bytes Output, is shown in Figure 9. The example
approximates the time based on several assumptions;
1. The FIFO Input channel is full-128 bytes of data
Host Immediate Command
interrupt service
Total Minimum Time to
Reconfigure FIFO
96.00 jJ.s
0.75 jJ.s
0.75 jJ.s
0.75 jJ.s
2.3 jJ.s
0.75 jJ.s
2.3 jJ.s
112.33 jJ.s
Figure 9. Sequence of Events to Invoke FIFO
DMA Freeze Mode and Timings
2. Output FIFO channel is empty-l byte
3. No Data Stream Commands in the FIFO.
4-19
intJ
AP-281
Table 10. Slave Bus Interface Status During FIFO DMA Freezer Mode
Interface Pins;
A1
AO
READ
WRITE
1
1
0
0
1
1
0
0
0
1
0
1
1
0
1
0
0
0
1
0
0
0
0
1
0
1
0
0
0
1
1
0
1
0
1
0
1
0
X
0
X
DACK
CS
A2
1
1
1
1
0
0
0
0
0
0
0
0
1
0
1
1
Operation In
Normal Mode
Status In
Freeze Mode
Read Host Status SFR
Operational
Read Host Control SFR
Operational
Write Host Control SFR
Disabled
Data or DMA data from
Output Channel
Data or DMA data to
Input Channel
Disabled
1
Data Stream Command
from
I
Output Channel
Disabled
1
0
Data Stream Command to
Input Channel
Disabled
0
0
1
Read Immediate Command
Out from Output Channel
Disabled
0
0
1
0
Write Immediate Command
In to Input Channel
Disabled
X
X
X
0
1
DMA Data from Output
Channel
Disabled
X
X
X
1
0
DMA Data to Input Channel
Disabled
Disabled
NOTE:
X = don't care
Table 11. FIFO SFR's Characteristics During FIFO DMA Freeze Mode
Label
Name
HCON
HSTAT
SLCON
SSTAT
IEP
. Host Control
Host Status
Slave Control
Slave Status
Interrupt Enable
& Priority
Mode Register
Input FIFO Write Pointer
Input FIFO Read Pointer
Output FIFO Write Pointer
Output FIFO Read Pointer
Channel Boundary Pointer
Immediate Command In
Immediate Command Out
FIFO IN
COMMAND IN
FIFO OUT
COMMAND OUT
Input FIFO Threshold
Other FIFO Threshold
MODE
IWPR
IRPR
OWPR
ORPR
CBP
IMIN
IMONT
FIN
CIN
FOUT
COUT
ITHR
OTHR
4-20
Normal
Operation
(SST5 = 1)
Freeze Mode
Operation
(SST5 = 0)
Not Accessible
Read Only
Read & Write
Read Only
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read Only'
Read Only
Read Only
Read Only
Read Only
Read Only
Read & Write
Read Only
Read Only
Read & Write
Read & Write
Read Only
Read Only
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read & Write
Read Only
Read Only
Read & Write
Read & Write
Read & Write
Read & Write
intJ
APPLICATION
NOTE
AP-283
September 1986
Flexibility in Frame Size with the
8044
PARVIZ KHODADADI
APPLICATIONS ENGINEER
© Intel Corporation, 1988
Order Number: 292019-001
4-21
inter
FLEXIBILITY IN FRAME SIZE WITH THE 8044
sumes that the reader is familiar with the 8044 data
sheet and the SDLC communications protocol.
1.0 INTRODUCTION
The 8044 is a serial communication microcontroller
known as the RUPI (Remote Universal Peripheral Interface). It merges the popular 8051 8-bit microcontroller with an intelligent, high performance HDLC/SDLC
serial communication controller called the Serial Interface Unit (SIU). The chip provides all features of the
microcontroller and supports the Synchronous Data
Link Control (SDLC) communications protocol.
1.1 Normal Operation
In Normal operation the on-chip CPU and the SIU
operate in parallel. The SIU handles the serial communication task while the CPU processes the contents of
the on-chip transmit and receiver buffer, services interrupt routines, or performs the local real time processing
tasks.
There are two methods of operation relating to frame
size:
1) Normal operation (limited frame size)
2) Expanded operation (unlimited frame size)
The 192 bytes of on-chip RAM serves as the interface
buffer between the CPU and the SIU, used by both as a
receive and transmit buffer. Some of the internal RAM
space is used as general purpose registers (e.g. RO-R7).
The remaining bytes may be divided into at least two
sections: one section for the transmit buffer and the
other section for the receive buffer. In some applications, the 192 byte internal RAM size imposes a limitation on the size of the information field of each frame
and, consequently, achieves less than optimal information throughput.
In Normal operation the internal 192 byte RAM is
used as the receive and transmit buffer. In this operation, the chip supports data rates up to 2.4 Mbps externally clocked and 375 Kbps self-clocked. For frame
sizes greater than 192 bytes, Expanded operation is required. In Expanded operation the ext~rnal RAM, in
conjunction with the internal RAM, IS used as ·the
transmit and receive buffer. In this operation, the chip
supports data rates up to 500 Kbps externally clocked
and 375 Kbps self-clocked. In both cases, the SIU handles many of the data link functions in hardware, and
the chip can be configured in either Auto or Flexible
mode.
.
Figure 1 illustrates the flow of data when internal
RAM is used as the receive and transmit buffer. The
on-chip CPU allocates a receive buffer in the internal
RAM and enables the SIU. A receiving SDLC frame is
processed by tlie SIU and the information bytes of the
frame, if any, are stored in the internal RAM. Th~n,
the SIU informs the CPU of the received bytes (Senal
Channel interrupt). For transmission, the CPU loads
the transmitting bytes into the internal RAM and enables the SIU. The SIU transmits the information bytes
in SDLC format.
The discussion that follows describes the operation of
the chip and the behavior of the serial interface unit.
Both Normal and Expanded operations will be further
explained with extra emphasis on Expanded operation
and its supporting software. Two examples of SDLC
communication systems will also be covered, where the
chip is used in Expanded operation. The discussion as-
I
TRANSMIT
FRAME: ._ r
III
A
C
----
----
I
rCS1
I
FCS2
II
r
SPECIAL
~UNCTION
REGTERS
t
t
OBFH
TRANSMIT
BurFER
~
-"
..
/
RECEIVE
FRAME:
I r IA IC I
----'"'-
t
RECEIVE
BUFFER
~
I
rCS1
I
FCS2
I I
F
GENERAL fpURPOSE
REGISTERS
~
OOH
NTERNAL RAM
292019-1
Figure 1. Transmission/Reception Data Flow Using Internal RAM
4-22
FLEXIBILITY IN FRAME SIZE WITH THE 8044
I rcsi I rCS2 I r I
TR~~;~~~ I r I A I c I
RECEIVE
I rcsi I rCS2 I F I ...._ _ _ _ _..... OOH
INTERNAL RAM
I
L~t."
EXTERNAL RAM
292019-2
Figure 2. Transmission/Reception Data Flow Using External RAM
1.2 Expanded Operation
In Expanded operation the on-chip CPU monitors the
state of the SIU, and moves data from/to external buffer to/from the internal RAM and registers while reception/transmission is taking place. If the CPU must
service an interrupt during transmission or reception of
a frame or transmit from internal RAM, the chip can
shift to Normal operation.
There is a special function register called SIUST, the
contents of which dictate the operation of the SIU.
Also, at data rates lower than 2.4 Mbps, one section of
the SIU, in fixed intervals during transmission and reception, is in the "standby" mode and performs no
function. The above two characteristics make it possible to program the CPU to move data to/from external
RAM and to force the SIU to repeat or skip some desired hardware tasks while transmission or reception is
taking place. With these modifications, external RAM
can be utilized as a transmit and receive buffer instead
of the internal RAM.
Figure 2 graphically shows the flow of data when external RAM is used. For reception, the receiving bytes are
loaded into the Receive Control Byte (RCB) register.
Then, the data in RCB is moved to external RAM and
the SIU is forced to load the next byte into the RCB
register - The chip believes it is .receiving a control byte
continuously. For transmission, Information bytes (1bytes) are loaded into a location in the internal RAM
and the chip is forced to transmit the contents of this
location repeatedly.
Discussion of expanded operation is continued in sections 4 and 5. First, however, sections 2 and 3 describe
fea~ures
of the 8044 which are necessary to further explain expanded operation.
2.0 THE SERIAL INTERFACE UNIT
2.1 Hardware Description
The Serial Interface Unit (SIU) of the RUPI, shown in
Figure 3, is divided functionally into a Bit Processor
(BIP) and a Byte Processor (BYP), each sharing some
common timing and control logic. The bit processor is
the interface between the SIU bus and the serial port
pins. It performs all functions necessary to transmit/receive a byte of data to/from the serial data line (shifting, NRZI coding, zero insertion/deletion, etc.). The
byte processor manipulates bytes of data to perform
message formatting, transmitting, and receiving functions. For example, moving bytes from/to the special
function registers to/from the bit processor.
The byte processor is controlled by a Finite-State Machine (FSM). For every receiving/transmitting byte,
the byte processor executes one state. It then jumps to
the next state or repeats the same state. These states
. will be explained in section 3. The status of the FSM is
kept in an 8-bit register called SIUST (SIU State Counter). This register is used to manipulate the behavior of
the byte processor.
As the name implies, the bit processor processes data
one bit at a time. The speed of the bit processor is a
function of the serial channel data rate. When one byte
of data is 'processed by the bit processor, a byte bounda-
4-23
inter
FLEXIBILITY IN FRAME SIZE WITH THE 8044
ry is reached. Each time a byte bc'undary is detected in
"the serial data stream, a burst of clock cycles (16 CPU
states) is generated for the byte processor to execute
one state of the state machine. When all the procedures
in the state are executed, a wait signal is asserted to
terminate the burst, and the byte processor waits for
the next byte boundary (standby mode). The lower the
data rate, the longer the byte processor will stay in the
standby mode.
2.2 Reception of Frames
Incoming data is NRZI decoded by the on-chip decoder. It is then passed through the zero insertion/deletion
(ZID) circuitry. The ZID not only performs zero insertion/deletion, but also detects flags and Go Aheads
(GA) in the data stream. The data bits are then loaded
"into the shift register (SR) which performs serial to parallel conversion. When 8 bits of data are collected in the
shift register, the bit processor triggers the byte processor to process the byte, and it proceeds to load the next
SPECIAL
FUNCTION
REGISTERS:
STAD TBl
RCB
TCB
RBl BCNT
RBS FIFOO
RFl FIF01
TBS FIF02
DUAL
PORT
RAM
block of data into the shift register. The serial data is
also shifted, through SR, to a 16-bit register" called
"FCS GEN/CHK" for CRC checking. The byte processor takes the received address and control bytes from
the SR shift register and moves them to the appropriate
registers. If the contents of the shift register is expected
to be an information byte, the byte processor" moves
them through a 3-byte FIFO to the internal RAM at a
starting location addressFd by the contents of the Receive Buffer Start (RBS) register.
2.3 Transmission of Frames
In the transmit mode, the byte processor relinquishes a
byte to the bit processor by moving it to a register
called RB (RAM buffer). The bit processor converts
the data to serial form through the shift register, performs zero bit insertion, NRZI encoding, and sends the
data to the serial port for transmission. Finally, the
contents of the FCS GEN/CHK and the closing flag
are routed to the serial port for transmission.
BYP
<'
CONTROL
SIGNALS,
IB
292019-3
Figure 3. SIU Block Diagram
4-24
inter
FLEXIBILITY IN FRAME SIZE WITH THE 8044
3.0 TRANSMIT AND RECEIVE
STATES
The simplified receive and transmit state diagrams are
shown in Figures 4 arid 5, respectively. The numbers on
the left of each state represent the contents of the
SIUST register when the byte processor is in the standby mode, and the instructions on the right of each state
represent the "state procedures" of that state. When the
byte processor executes these procedures the least three
significant bits of the SIUST register are being incremented while the other bits remain unchanged. The
byte processor will jump from one state to another
without going into the standby mode when a conditional jump procedure executed by the byte processor is
true.
3.1 Receive State Sequence
When an opening flag (7EH) is detected by the bit
processor, the byte processor is triggered to execute the
procedures of the FLAG state. In the FLAG state, the
byte processor loads the contents of the RBS register
into the Special RAM (SRAR) register. SRAR is the
pointer to the internal RAM. The byte processor decrements the contents of the Receive Buffer Length (RBL)
register and loads them into the DMA Count (DCNT)
register. The FCS GEN/CHK circuit is turned on to
monitor the serial data stream for Frame Check Sequence functions as per SDLC specifications.
Assuming there is an address field in the frame, con. tents of the SIUST register will then be changed to
08H, causing the byte processor to jump to the ADDRESS state and wait (standby) for the next byte
boundary. As ~oon as the bit processor moves the address byte into the SR shift register, a byte boundary is
achieved and the byte processor is triggered to execute
the procedures in the ADDRESS state.
In the ADDRESS state the received station address is
compared to the contents of the STAD register. If there
is no match, or the address is not the broadcast address
(FFH), reception will be aborted (SIUST = O!H). Otherwise, the byte processor jumps to the CONTROL
state (SIUST = 1OH) and goes into standby mode.
The byte processor jumps to the CONTROL state if
there exists a control field in the receiving frame. In
this state the control byte is moved to the RCB register
by the byte processor. Note that the only action taken
in this state is that a received byte, processed by the bit
processor, is moved to RCB. There is no other hardware task performed, and DCNT and SRAR are not
affected in this state.
The next two states, PUSH-! and PUSH-2, will be'executed if Frame check sequence (NFCS = 0) option is
selected. In these two states the first and second bytes
of the information field are pushed into the 3-byte
FIFO (FIFOO, FIFO!, FIF02) and the Receive Field
Length register (RFL) is set to zero. The 3-byte FIFO
is used as a pipeline to move received bytes into the
internal RAM. The FIFO prevents transfer of CRC
bytes and the closing flag to the receive buffer (Le.,
when the ending flag is received, the contents of FIFO
are FLAG, FCS!, and FCSO.) The three byte FIFO is
collapsed to one byte in No FCS mode.
In the DMA-LOOP state the byte processor pushes a
byte from SR to FIFOO, moves the contents of FIF02
to· the internal RAM addressed by the contents of
SRAR, increments the SRAR and RFL registers, and
decrements the DCNT register. If more information
bytes are expected, the byte processor repeats this state
on the next byte boundaries until DMA Buffer End
occurs. The DMA Buffer End occurs if SRAR reaches
OBFH (!92 decimal), DCNT reaches zero, or the RBP
bit of the STS register is set.
The BOY-LOOP state, the last state, is executed if
there is a buffer overrun. Buffer overrun occurs when
the number of information bytes received is larger than
the length of the receive buffer (RFL > RBL). This
state is executed until the closing flag is received.
At the end of reception, ithe FCS option is used, the
closing flag and the FCS bytes will remain in the 3-byte
FIFO. The contents of the RCB register are used to
update the NSNR (Receive/Send Count) register. The
SIU updates the STS register and sets the serial interrupt.
3.2 Tr~nsmit State Sequence
Setting the RTS bit puts the SIU in the transmit mode.
When the CTS pin goes active, the byte processor goes
into START-XMIT state. In this state the opening flag
is moved into the RAM Buffer (RB) register. The byte
processor jumps to the next state and goes into the
standby mode.
.
If the Pre-Frame Sync (PFS) option is selected, the
PFSI and PFS2 states will be executed to transmit the
two Pre-Frame Sync bytes (OOH or 55H). In these two
states the contents of the Pre-Frame Sync generator are
sent to the serial port while the Zero Insertion Circuit
(ZID) is turned off. ZID is turned back on automaticallyon the next byte boundary.
If the PFS option is not chosen, the byte processor
jumps to the FLAG state. In this state, the byte processor moves the contents of TBS into the SRAR register,
decrements TBL and moves the contents into the
DCNT register. The byte processor turns off the ZID
and turns on FCS GEN/CHK. The contents of FCS
GEN/CHK are not transmitted unless the NFCS bit is
4-25
inter
FLEXIBILITY IN FRAME SIZE WITH THE 8044
SIUST'
STATE
STATE PROCEDURE
1
01-1)
01-2)
01-3)
0104)
ADDRESS
)
08-1) SR-TMP
08-2) (STAO)-RB
08-3) IF RB.NE.TMP AND
FFH.NE.TMP THEN IDLE
08-4) IF NB=1 GOTO 10-2
(
CONTROL
J
10-1) SR-(RCB)
10-2) IF NrCS=1 GOTO 20-3
18H
(
PUSH-1
J
18-1) SR-(FIFOO)
18-2) PUSH
20H
(
PUSH-2
)
20-1)
20-2)
20-2)
20-4)
28H
(
DMA-LOOP
J
28-1) IF END OF I-FIELD,
THEN IDLE
28-2) (FIF02)-@SRAR
28-3) SR- (FIFOO)
28-4) INC. SRAR
28-5) PUSH
28-6) DEC. (DCNT)
28-7) INC. (RFL)
28-8) IF NOT DMA BUFFER END,
GOTO 28-1
28-9) RCB)- RB
01H
(
rLAG
. 08H
(
10H
!
!
(RBS)-SRAR
(RBL)-1 -(DeNT)
TURN ON rcs GEN/CHK
IF POINT TO POINT MODE,
GOTO 10-2
SR - (FIFOO)
PUSH
(RFL)--OOH
IF DMA BUFFER END,
GOTO 28-7
20-5) (RCB)-RB
.
"
30H
(
BOY-LOOP
)
30- 1)
30-2)
30-3)
,
30-4)
SET BOY ,BIT (SRS.3)
(RCB)-RB
IF NOT END OF I-FIELD,
GOTO 30-1
IDLE
292019-4
Figure 4. Receive State Diagram
set. If a frame with the address field is chosen, it moves
the contents of the STAD register into the RB register
for transmission. At the same time, the opening flag is
being transmitted by the 'bit processor.
In the ADDRESS (SIUST = AOH) and CONTROL
(SIUST = A8H) states, TCB and the first information
byte are loaded into, the RB register for transmission,
respectively. Note that in the CONTROL state, none of
the registers (e.g. DCNT, SRAR) are incremented, and
ZID and FCS GEN/CHK are not turned on or off.
The procedures in the DMA-LOOP state are similar to
the procedures of the DMA-LOOP in the receive state
diagram. The SRAR register pointer to the internal
RAM is incremented, and the DCNT register is decremented. The contents of DCNTreach zero when all the
information bytes from the transmit buffer are transmitted. A byte from RAM is moved to the RB register
for transmission. This state is executed on the following
b~te boundaries until all the information bytes are
transmitted.
The FCSI and the FCS2 states are executed to transmit
the Frame Check Sequence bytes generated by the FCS
generator, and the END-FLAG state is executed to
transmit the closing flag.
The XMIT-ACTION and the ABORT-ACTION
states are executed by the byte processor to synchronize
the SIU with the CPU clock. The XMIT-ACTION or
the ABORT-ACTION state is repeated until the byte
processor status is updated. At the end, the STS and the
TMOD registers are updated.
The two ABORT-SEQUENCE states (SIUST = EOH
and'SIUST = E8H) are executed only if transmission
is aborted by the CPU (RTS or TBF bit of the STS
register'is cleared) or by the serial data link (CTS signal
goes inactive or shut-off occurs in loop mode.)
4-26
intJ
FLEXIBILITY IN FRAME SIZE WITH THE 8044
SIUST
STATE
STATE PROCEDURE
87H
88H
90H
87-1) FLAG-R8
T
(
88-1) IF NO PFS (SMD.2=0),
GOTO 98-1
88-2) XMIT A PFS 8YTE
88-3) ZID OFF
PFS2
1
98H
FLAG
AOH
ADDRESS
)
90-1) XMIT A PFS 8YTE
90-2) ZID OFF
98-1)
98-2)
98-3)
98-4)
98-5)
(T8S)-SRAR
ZID OFF
(TBL)-1- (DCNT)
TURN ON FCS GEN/CHK
IF POINT TO POINT MODE,
GOTO A8-1
98-6) (STAD)- R8
AO-1) IF N8=1 GOTO A8-1
AO-2) IF AUTO MODE
CTRL-R8
AO-3) IF FLEXI8LE MODE
(TC8)-R8
A8H
A8-1) IF DMA 8UFFER END,
GOTO 80-3
A8-2) @SRAR-R8
80H
80-1) INC. SRAR
80-2) DEC. DCNT
80-3) IF DMA BUFFER END
AND NFCS=l,
GOTO CO-1
80-4) @SRAR-R8
BO-5) GOTO 80-1
88H
88-1) NO ACTION
COH
CO-1) FLAG-R8
C8H
END-FLAG
C8-1) ZID OFF
DOH
00-1) REPEAT THIS STATE TILL SIU
IS IN SYNC. WITH CPU, THEN
IDLE. ZID OFF
EOH
EO-1) NO ACTION
E8H'
E8-1) ZID OFF
FOH
A80RT-ACTION
FO-1) REPEAT THIS STATE TILL SIU
IS IN SYNC. WITH CPU, THEN
IDLE. ZID OFF
Figure 5, Transmit State Diagram
4-27
292019-6
inter
FLEXIBILITY IN FRAME SIZE WITH THE 8044
4.0 TRANSMISSION/RECEPTION OF
LONG FRAMES (EXPANDED
OPERATION)
In this application note, a frame whose information
field is more than 192 bytes (size of on-chip RAM) is
referred to as a long frame. The 8044 can access up to
64000 bytes of external RAM. Therefore, a long frame
can have up to 64000 information bytes.
4.1 Description
During transmission or reception of a frame, while the
bit processor is processing a byte, the byte processor,
after 16 CPU states, is in the standby mode, and the
internal registers and the internal bus are not used. The
period between each byte boundary, when the byte
processor is in the standby mode, can be used to move
data from external RAM to one of the byte processor
registers for transmission and vice versa for reception.
The contents of the SIUST register, which dictate the
state of the byte processor, can be monitored to recognize the beginning of each SDLC field and the consecutive byte boundaries.
4.2 SIU Registers
To write into the SIUST register, the data must be complemented. For example, if you intend to write 18H
into the SIUST register, you should write E7H to the
register. The data read from SIUST is, however, true
data (i.e. 18H).
Read and write accesses to the SIUST, STAD, DCNT,
RCB, RBL, RFL, TCB, TBL, TBS, and the 3-byte
FIFO registers are done on even and odd phases, respectively. Therefore, there is no bus contention when
the CPU is monitoring the registers (e.g. SIUST), and
SIU is simultaneously writing into them.
There is no need to change or reset the contents of any
SIU register while transmitting or receiving long
frames, unless the byte processor is forced to repeat a
state in which the contents of these registers are modified. Note that the SRAR register can not be accessed
.by the CPU; therefore, avoid repeating the DMALOOP states. If SRAR increments to 192, the SIU will
be interrupted and communication will be aborted.
4.3 Other Possibilities .
By writing into the SIUST register, the byte processor
can be forced to repeat or skip a specific state. As an
example, the SIU can be forced to repeatedly put the
received bytes into the RCB register. This is accomplished by writing E7H into the SIUST register when
the byte processor goes into the standby mode. The
byte processor, therefore, executes the CONTROL
state at the next byte boundary.
For transmission, the byte processor is put in the transmit mode. When transmission of a frame is initiated,
the user program calls a subroutine in which the state
of the byte processor is monitored by checking the contents of the SIUST register. When the byte processor
reaches a desired state and goes into standby, the CPU
loads the first byte of the internal RAM buffer with
data and moves the byte processor to the CONTROL
state. The routine is repeated for every byte. At the end,
the program returns from the subroutine, and the SIU
finishes its task (see application examples).
For reception, a software routine is executed to move
data to external RAM and to force the SIU to repeat
the CONTROL state. The CONTROL state is repeated
because, as shown in the receive state diagram, the only
action taken by the byte processor, in the CONTROL
state, is to move the contents of SR to the RCB register.
None of the registers (e.g. SRAR and DCNT) are incremented. A similar comment justifies the use of the
CONTROL· state for transmission. In the transmit
CONTROL state, contents of a location in the on-chip
RAM addressed by TBS is moved to RB for transmission.
The internal RAM, in conjunction with an external
buffer (RAM or FIFOs), can be used as a transmit and
receive buffer. In other words, Expanded and Normal
operation can be used together. For example, if a frame
with 300 Information bytes is received and only 255 of
them are moved to an external buffer, the remaining
bytes (45 bytes) will be loaded into the internal RAM
by the SIU (assuming RBL is set to 45 or more). The
contents of RFL indicate the number of bytes stored in
the internal RAM. For transmission, the contents of
the external buffer can be transmitted followed by the
contents of the internal buffer.
If the internal RAM is not used, contents of the RBL
register can be 0 and contents of the TBL register must
be set to 1. The contents of the TBS register can be any
location in the internal RAM.
The transmission and reception procedures for long
frames with no FCS are similar to those with FCS. The
exception is the contents of the SIUST register should
be compared with different values since the two FCS
states of the transmit and receive flow charts are
skipped by the byte processor.
If a frame format with no control byte is chosen, a
location in the RAM addressed by TBS should be used
for transmission as with control byte format. The FIFO
can be used for reception. The STAD register can be
used for t~ansmission if no zero insertion is required.
4-28
FLEXIBILITY IN FRAME SIZE WITH THE 8044
If the RUPI is used in Auto mode (see Section 5), it
will still respond to RR, RNR, REJ, and Unnumbered
Poll (UP) SDLC commands with RR or RNR automatically, without using any transmit routine. For example, if the on-chip CPU is busy performing some real
time operations, the SIU can transmit an information
frame from the internal buffer or transmit a supervisory
frame without the help of CPU (Normal operation).
4.4 Maximum Data Rate in Expanded
Operation
Assuming there is no zero-insertion/deletion, the bit
processor requires eight serial clock periods to process
one block of data. The byte processor, running on the
CPU clock, processes one byte of data in 16 CPU states
(one state of the state diagrams). Each CPU state is two
oscillator periods. At an oscillator frequency of
12 MHz, the CPU clock is.6 MHz, and 16 CPU states
is 2.7 /ks. At a 3 Mbit rate with no zero-insertion/deletion, there is exactly enough time to execute one state
per byie (i6 states at 6 MHz = 8 bits at 3M baud). In
other words, the standby time is zero.
Maximum data rate using this feature is limited primarily by the number of instructions needed to be executed
during the standby mode.
Transmission or reception of a frame can be timed out
so that the CPU will not hang up in the transmit or
receive procedures if a frame is aborted. Or, if the da~a
rate allows enough time (standby time is long enough),
the CPU can monitor the SIUST register for idle mode
(SIUST = OlH).
Figure 6 demonstrates portions of the timing relationship between the byte processor and the bit processor.
In each state, the actions taken by the processors, plus
the contents of the SIUST register, are shown. When
the byte processor is running, the contents of SIUST
are unknown. However, when it is in the standby mode,
its contents are determinable.
It is also possible to transmit multiple opening or closing flags by forcing the byte processor to repeat the
END-FLAG state.
The maximum data rate for transmitting and receiving
long frames depends on the number of instructions
needed to be executed during standby, and is propor-
STATE:
BIP:
ADDRESS
::x
X\._ _ _~GO_N_T_RO_L_ _ _--JXI.._ _ _ _P_U_SH_-_l_ _ _ _oJX PUSH-2
CRTL BYTE -
SR
BYP: ::XSR-TMPX STANDBY
SIUST:
?
X,,_ _ _
1s_t_I-_B_YT_E___
S_R_ _......JX ''__2_"_d_I_-_BYT_E___S_R_ _
X
SR -
10H
RCB:::X
STANDBY
X
SR -
ISH
?
FIFOO
?
>C
~
20H
292019-7
Sa. Reception
STATE: _ _ _
FLA_G_oJX,,_ _ _.;.;A;;;,;DD;;.;.R;,;;ES.;.,.S;...._ _~X,,_ _ _.....;C;.;;O;;.;N.;.;TR;.;;O.;;.L_______X"-_ _ __
>C
BIP: : : X_ _X_M_ITT_I_NG_FL_A_G_--JX\._ _X_M_ITT_IN_G_A_D_RS_BYT_E_ _..JX,,__
XM_I_TT_IN_G_C_R_T_L_BYT_E_....
BYP: ::XSTAD-RBX STANDBY
SIUST:
?
AOH
X
TCB -
RB
X
STANDBY
X
@SRAR -
ASH
?
Sb. Transmission
Figure S. Portions of the BIP/BYP Timing Relationship
4-29
?
RB ~
BOH
292019-8
inter
FLEXIBILITY IN FRAME SIZE WITH THE 8044
tional to the oscillator frequency. The time the byte
processor is in the standby mode, waiting for the bit
processor to deliver a processed byte, is at least equal to
eight serial clock periods minus 16 CPU states. If an
inserted zero is in the block of data, the bit processor
will process the byte in nine serial clock periods.
The equation for theoretical maximum data rate is given as:
(2TCLCL) x (16 states) + (# of instruction cycles) x
(12TCLCL) = (STOCY)
Equation (1)
Where: TCLCL is the oscillator period.
TOCY is the serial clock period.
5.2 Auto Mode
In the Auto mode, the 8044 can only be a secondary
station operating in the SOLC "Normal Response
Mode". The 8044 in Auto mode does not transmit messages unless it is polled by the primary.
For transmission of an information frame, the CPU allocates space for the transmit buffer, loads the buffer
with data, and sets the TBF bit. The SIU will transmit
the frame when it receives a valid poll-frame. A frame
whose poll bit of the control byte is set, is a poll-frame.
The poll bit causes the RTS bit to be set. If TBF were
not set the SIU would respond with Receive Not
Ready (RNR) SOLC command- if RBP = 1, or with
Receive Ready (RR) SOLC command if RBP = O.
After transmission RTS is cleared, and the CPU is not
interrupted.
At an oscillator frequency of 12 MHz and baud rate of
375 Kbps, about 18 instruction cycles can be executed
when the byte processor is in the standby mode. At a
9600 baud rate, there is time to execute about 830 instruction cycles-plenty of time to service a long interrupt routine or perform bit-manipulation or arithmetic
operations on the data while transmission or reception
is taking place.
For reception, the procedure is the same as that of
Flexible mode. In addition, the SIU sets the RTS bit if
the received frame is a poll-frame (causing an automatic response) and increments the NS and NR counts
accordingly.
5.0 MODES OF OPERATION
6.0 APPLICATION EXAMPLES
The 8044 has two modes: Flexible mode and Auto
mode. In Auto mode, the chip responds to many SOLC
commands and keeps track of frame sequence numbering automatically without on-chip CPU intervention.
In Flexible mode, communication tasks are under control of the on-chip CPU.
5.1 Flexible Mode
For transmission, the CPU allocates space for transmit
buffer by storing values for the starting location and
size of the transmit buffer in the TBS and the TBL
registers. It loads the buffer with data, sets the TBF and
the RTS bits in the STS register, and proceeds to perform other tasks. The SIU activates the RTS line.
When the CTS signal goes active, the SIU transmits the
frame. At the end of transmission, the SIU clears the
RTS bit and interrupts the CPU (SI set).
For reception, the CPU allocates space for receive buffer by loading the beginning address and length of the
receive buffer into the RBS and RBL registers, sets the
RBE bit, and proceeds to perform other tasks. The
SIU, upon detection of an opening flag, checks the next
received byte. If it matches the station address, it will
load the received control byte into RCB, and received
information bytes into the receive buffer. At the end of
reception, if the Frame Check Sequence (PCS) is correct, the SIU clears RBE and interrupts the CPU.
. Two application examples are given to provide additional details about the procedures used to transmit and
receive long frames. In the first application example,
procedures to construct receive and transmit software
routines for the point-to-point frame format are described. :rhe point-to-point frame has the information
field and the FCS field enclosed between two flags (see
Figure 7). In the second example software code'is generated for reception and transinission of the standard
SDLC frame. The SOLC frame has the pattern: flag,
address, control, information, FCS, flag.
The first example focuses on the construction of transmit and receive code which allow the chip to transmit
and receive long frames. The second example shows
how to make more use ofthe 8044 features, such as the
on-chip phase locked loop for clock recovery and automatic responses in the Auto mode to demonstrate the
capability of the 8044 to achieve high throughput when
Expanded operation is·used.
6.1 Point-to-Point Application
Example
A point-to-point communication system was developed
to receive and transmit long frames. The system. consists of. one primary and one secondary station. Although multiple secondary stations can be used in this
4-30
intJ
FLEXIBILITY IN FRAME SIZE WITH THE 8044
~
1
INFORMATION
BYTES
1
I'
FRAME CHECK
SEQUENCE
FLAG
Point·te-Point
F-I BYTE-FCS-F
FLAG
ADDRESS BYTE
PRIMARY
CONTROL BYTE
SECONDARY
F-255 I BYTES-FCS-F
... INFORMATION''''
'I'
BYTES
'I'
292019-10
Figure 8. Secondary Responses to Primary
Station Commands
FRAME CHECK
SEQUENCE
FLAG
Standard SDLC
2920t9-9
Figure 7. Point-to-Point and Standard SDLC
Frame Formats
system, one secondary is chosen to simplify the primary
station's software and focus on the long frame software
code. Both the primary and the secondary stations are
in Flexible mode and the external clock option is used
for the serial channel. The maximum data rate is
500 Kbps. The FCS bytes are generated and checked
automatically by both stations.
6.1.1 POLLING SEQUENCE
The polling sequence, shown in Figure 8, takes place
continuously between the primary and the' secondary
stations. The primary transmits a frame with one information byte to the secondary. The information byte is
used by the secondary as an address byte. The secondary checks the received byte, and if the address
matches, the secondary responds with a long frame. In
this example, the information field of the frame is chosen to be 255 bytes long. Since there is only one secondary station, the address always matches. Upon successful reception of the long frame, the primary transmits
another frame to the secondary station.
6.1.2 HARDWARE
The schematic of the secondary station is given in Figure 9. The circuit of the primary station is identical to
the secondary station with the exception of pin 11
(DATA) being connected to pin 14 (TO). In the primary station, the 8044 is interrupted when activity is
detected on the communication line by the on-chip timer (in counter mode). This is explained more later. The
serial clock to both stations is supplied by a pulse generator. The output of the pulse generator (not shown in
the diagram) is connected to pin 15 of the 8044s. Since
the two stations are located near each other (less than 4
feet), line drivers are not used.
The central processor of each station is the 8044. The
data link program is stored in a 2Kx8 EPROM
(2732A), and a 2Kx8 static RAM (AM9128) is used as
the external transmit and receive buffer. The RTS pin is
connected to the CTS pin. For simplicity, the stations
are assumed to be in the SDLC Normal Respond Mode
after Hardware reset.
6.1.3 PRIMARY STATION SOFTWARE
The assembly code for the primary station software is
listed in Appendix A. The primary software consists of
the main routine, the SIU interrupt routine, and the
receive interrupt routine. The receive interrupt routine
is executed when a long frame is being received.
In the flow charts that follow, all actions taken by the
SIU appear in squares, and actions taken by the on-chip
CPU appear in spheres.
4-31
~Rl
SWI
~
P,~~~HZ
h::~
1~~
18
X2
XI
9
....../
ADO
AOI
A02
RST
A03
A04
[
CTS
RTS
ADS
A06
A07
"
iFi
c
iii
ALE
!D
I/)
CD
N/C
8
:::I
.$>.
..
a.
,
II)
I\)
I/)
w'<
S'
g:
dJ []
SCLK
AO-7
8044
'";g
DATA
-!!.
15
11
31
~-
WR
TO
Rii
SCLK PSEN
DATA
EA
A8
A9
Al0
AM9128
8282
39
DO
DO
1
38
01
01
2
37
02
02
3
36
03
03
4
35
04
04
5
34
05
05
6
33
06
06
7
32
07
07
8
9
V
30
11
r-
010
000
011
001
012
002
013
003
014
004
015
DOS
016
017
006
007
19
AO
18
AI
17
A2
16
A3
15
A4
14
AS
13
A6
12
A7
AO
8
AI
7
A2
6
A3
5
A4
4
AS
3
A6
2
A7
1
A8
22
liE
A9
23
STS
Al0
21
17
20
r
29
21
A8
22
A9
23
Al0
24
All
AO
00
AI
A2
01
·02
A3
03
A4
04
AS
05
A6
06
A7
07
9
DO
10
01
11
02
13
03
14
04
15
05
16
06
17
07
!!
Al0
r
:::::j
WE
liE
CE
::D
A9
-<
Z
."
)0
i:
m
rn
2732A
A08-11
8
:::I
AI
7
I
A2
6
A3
5
A4
4
AS
3
A6
2
A7
AO
00
AI
01
A2
02
A3
03
A4
. AS
04
A6
06
A7
07
1
A8
22
A9
23
Al0
19
All
21
20
18
~
."
r
m
~
A8
19
16
AO
All
l
ADD-7.
05
9
DO
10
01
11
02
13
03
14
04
N
m
:E
:::::j
:t:
-I
:t:
15 ·05
m
16
06
17
07
!....
A8
A9
Al0
All
liE
CE
292019-11
....
FLEXIBILITY IN FRAME SIZE WITH THE 8044
Main Routine
First, the chip is initialized (see Figure 10). It is put in
Flexible mode, externally clocked, and "Flag-Information Field-FCS-Flag" frame format. Pre-Frame Sync
option (PFS = I) and automatic Frame Check Sequence generation/detection (NFCS = 0) are selected.
The on-chip transmit buffer starts at location 20H and
the transmit buffer length is set to I. This one byte
buffer contains the address of the secondary station.
There is no on-chip receive buffer since the long frame
being received is moved to the external buffer. The
RTS, TBF, and RBE bits are set simultaneously. Setting the RTS and TBF bits causes the SIU to transmit
the contents of the transmit buffer.
.
tasks. After reception of the long frame, the SIU interrupt routine is executed again. This time, RTS, TBF,
and RBE are set for another round of information exchange between the two stations.
SIU never interrupts while reception or transmission is
taking place. The SIU registers are updated and the SI
is set (serial interrupt) after the closing flag has been
received or transmitted. An SIU interrupt never occurs
if the receive interrupt routine or the transmit subroutine is being executed.
Setting the RBE bit of the STS register puts the RUPI
in the receive mode. However, the jump to the receive
interrupt routine occurs only when a frame appears on
the serial port. Incoming frames can be detected using
the Pre-Frame Sync. option and one of the CPU timers
in counter mode. The counter external pin (TO) is connected to the data line (pin II is tied to pin 14). Setting
the PFS (Pre-Frame Sync.) bit will guarantee 16 transitions before the opening flag of a flame.
=O. FRAME REeVED
292019-12
Main Program
Figure 10. Primary Station Flow Charts
SIU Interrupt Routine
After transmission of the frame, the SIU interrupts the
on-chip CPU (SI is set). In the SIU interrupt service
routine, counter 0 is initialized and turned on (see Figure 11). The .user program returns to perform other
292019-13
SIU Interrupt Routine
Figure 11. Primary Station Flow Charts
4-33
inter
FLEXIBILITY IN FRAME SIZE WITH THE 8044
The counter registers are initialized such that the counter interrupt occurs before-the opening flag of a frame.
When the PFS transitions appear on the data line, the
counter overflows and interrupts the cpu. The cpu
program jumps to the timer interrupt service routine
and executes the receive routine. In the receive routine,
the received frame is processed, and the information
bytes are moved to the external RAM. Note that the
maximum count rate of the 8051 counter is '12. of the
oscillator frequency. At 12 MHz, the data rate is limited to 500 Kbps.
Another method to detect a frame on the data line and
cause an interrupt is to use an external "Flag-Detect"
circuit to interrupt the CPU. The "Flag Detect" circuit
can be an 8-bit shift register plus some TTL chips. If
this option is used, the RUPI must operate in externally
'clocked mode because the clock is needed to shift the
incoming data into the shift register. With this option,
the maximum data rate is not limited by the maximum
count rate of the 8051 counter.
Receive Interrupt Routine
In Normal operation, the byte processor executes the
procedures of the FLAG state, jumps to the CONTROL state without going into the standby mode, and
executes 10-2 procedure of the state (see Figure 4). It
then jumps to the PUSH-I state and goes into the
standby mode. At the following byte boundaries, the
byte processor executes the PUSH-I, PUSH-2, ana
DMA-LOOP states, respectively. The receive interrupt
routine as shown in the flow chart of Figure 12 and
described below forces the byte processor to repeatedly
execute the CONTROL state before the PUSH-I state
is executed. The following is the step by step procedure
to receive long frames:
I) Turn off the CPU counter and save all the important registers. Jump to the receive interrupt routine,
execution of the instructions to save registers, and
initialization of the receive buffer pointer take place
while the Pre-Frame Sync bytes and the opening
flag are being received. This is about three data byte
'
periods (48 CPU cycles at 500 Kbps).
2) Monitor the SIUST register for standby in the
PUSH-I state (SIUST = 18H). When the SIUST
contents are 18H, the byte processor is waiting for
the first information byte. The bit processor has already recognized the flag and is processing the first
information byte.
3) In the'standby mode, move the byte processor into
the CONTROL state by writing "EFH" (complement of lOH) into the SIUST register. When the
next byte boundary occurs, the bit processor has
processed and moved a byte of data into the SR
register. The byte processor moves the contents of
SR into the RCB register, jumps to the PUSH-I
state (SIUST = 18H), and waits.
4) Monitor the SIUST register for standby in the
PUSH-I state. When the contents of SIUST becomes 18H, the contents of RCB are the first information byte of the information field.
5) While the byte processor is in the standby mode,
move the contents of RCB to an external RAM or
an 1/0 port.
6) Check for the end of the information field. The end
can be detected by knowing the number of bytes
transmitted, or by having a unique character at the
end of information field. The length of the information field can be loaded into' the first byte(s) received. The receive routine can load this byte into
the loop counter.
7) If the byte received is not the last information byte,
move the byte processor back' to standby in the
CONTROL state and repeat steps 4 through 6., Otherwise, return from the interrupt routine.
Upon returning from the receive interrupt routine, the
byte processor automatically executes the PUSH-I,
PUSH-2, and DMA-LOOP before it stops. This causes
the remaining information bytes (if any) to be stored in
the internal RAM at the starting location specified by
the contents of RBS register. At the end of the cycle,
the closing flag and the CRC bytes are left in the FIFO.
The RFL register will be incremented by the number of
bytes stored in the internal RAM. Then, the STS and
NSNR registers are updated, and an appropriate response is generated by the SIU.
The software to perform the above task is given in Table I. In this example, the number of instruction cycles
executed during standby is 12 cycles.
4-34
intJ
FLEXIBILITY IN FRAME SIZE WITH THE 8044
Receive Codes
•
REC:
WAIT1:
NEXTI:
WAIT2:
END
Cycles
•
•
•
•
•
CLR
MOV
CJNE
MOV
MOV
CJNE
MOV
MOVX
INC
DJNZ
RETI
TRO
A,#18H
A, SIUST , WAITl
SIUST,#OEFH ••••••••••••••••••••••• 2
A, #18H •••••••••••••••••••••••••••• 1
A,SIUST,WAIT2 •••••••••••••••••••••• 2
A ,RCB •••••••••••••••••••••••••••••• 1
@DPTR,A •••••••••••••••••••• , •••••• 2
DPTR ••••••••••••••••••••••••••••••• 2
R5,NEXTI ••••••••••••••••••••••••••• 2
12 Cycles
6.1.4 SECONDARY STATION SOFTWARE
The assembly code for the secondary station software is
given in Appendix A. The secondary station contains
the transmit subroutine which is called for transmission
of long frames.
Main Routine
As shown in the secondary station flow chart (Figure
13), the external transmit buffer (external RAM) is
loaded with the information data (FFR, FER, FOR,
... ) at starting location 200R. The; internal transmit
buffer (on chip RAM) starts at location 20R (TBS =
20R), and the transmit buffer length (TBL) is set to 1.
The on-chip CPU, in the transmit subroutine, moves
the information bytes from the external RAM to this
one byte buffer for transmission. The receive buffer
starts at location lOR and the receiver buffer length is
1. This buffer is used to buffer the frame transmitted by
the primary. The received byte is used as an address
byte.
The Secondary is configured like the Primary station. It
is put in Flexible mode, externally clocked, Point-topoint frame format. The PFS bit is set to transmit two
bytes before the first flag of a frame. The RBE bit is set
to put the chip in receive mode. Upon reception of a
valid frame, the SIU loads the received information
byte into the on-chip receive buffer and interrupts the
CPU.
SIU Interrupt Routine
292019-14
Receive Interrupt Routine
Figure 12. Primary Station Flow Charts
In the serial interrupt routine, the RBE bit is checked
(see Figure 14). Since RBE is clear, a frame has been
received. The received Information byte is compared
with the contents of the Station Address (STAD) register.
4-35
FLEXIBILITY IN FRAME SIZE WITH THE 8044
= I. rRAME XMITTED
ADDRESS NOT MATCHED
292019-15
292019-16
Main Program
SIU Interrupt
Figure 13. Secondary Station Flow Charts
Figure 14. Secondary Station Flow Charts
If they match, the secondary will call the transmit sub.
While the bit processor is transmitting the first PreFrame Sync byte, the byte processor executes the PFS2
state and jumps to the standby mode in the FLAG
state. The FLAG state is executed when the bit processor begins to transmit the second Pre-Frame Sync byte.
When the flag is being transmitted, the byte processor
executes the 98-1, 98-2, 98-3, and 98-4 procedures of
the FLAG state, and jumps to execute the AS-I procedure of tJte CONTROL state. When the opening flag is
transmitted, the contents of RB are the first information byte. (See transmit State diagram.)
routine to transmit the long frame. Upon returning
from the transmit subroutine, the RBE bit is set, and
program returns from the SIU interrupt. After transmission of the closing flag, SIU interrupt occurs again.
In the interrupt routine, th~ RBE is checked. Since the
RBE is set, the program returns from the SIU interrupt
routine and waits until another long frame is received.
If the secondary were in Auto mode, the chip must be
ready to execute the transmit routinc upon reception of
a poll-frame; otherwise, the chip automatically transmits the contents of the internal transmit buffer if the
TBF bit is set, or transmits a ,supervisory command
(RR or RNR) if TBF is clear.
Transmit Subroutine
In Normal operation the byte processor executes the
START-TRANSMIT state and jumps to the PFSI
state. While the bit processor is transmitting some unwanted bits, the byte processor executes the PFSI state
and jumps to the standby mode in the PFS2 state.
In the transmit subroutine (see Figure 15), the byte
prOcessor is forced to repeat the CONTROL state before the DMA-LOOP state. In the CONTROL state,
the contents of a RAM location addressed by the tBS
register are moved to the RB register. The following is
the step by step procedure to transmit long frames:
I) Put the chip in transmit mode by setting the RTS
and TBF bits.
'
2) Move an information byte from external RAM to a
location in the internal RA~ addressed by the contents of TBS.
4-36
FLEXIBILITY IN FRAME SIZE WITH THE 8044
3) Monitor the SIUST register for the standby mode in
the DMA-LOOP state (SIUST = BOH). When
SIUST is BOH, the opening flag has been transmitted, and the first information byte is being transmitted by the bit processor.
4) If there are more information bytes, move the byte
processor back to the CONTROL state, and repeat
steps 2 through 4. Otherwise, continue.
5) Move byte processor to the Standby mode in the
CONTROL state (SIUST = ASH) and return from
the subroutine.
The byte processor automatically executes the remaining states to send the FCS bytes and the closing flag.
After the completion of transmission, SIU updates the
STS and NSNR registers and interrupts the CPU.
If the contents of the TBL register were more than I,
the SIU transmits (TBL)-1 additional bytes from the
internal RAM at starting address (TBS) + 1 because it
executes the DMA-LOOP state (TBL)-I additional
times. The byte processor should not be programmed to
skip the DMA-LOOP state, because the transmission of
FCS bytes is enabled in this state.
The maximum baud rate that can be used with these
codes is calculated by adding the number of instruction
cycles executed, during the standby mode, between
each byte boundaries (see Table 2).
Using Equation I, the maximum data rate, based on the
transmit software, is 509 Kbps; However, the maximum count rate of the counter limits the data rate to
500 Kbps.
292019-17
Transmit Subroutine
Figure 15. Secondary Station Flow Charts
Table 2. Codes for Lon Frame Transmission
Transmit Codes
TRAN:
LOOP:
WAITl:
NEXTI:
•
•
•
MOV
MOV
SETB
SETB
MOVX
MOV
MOV
CJNE
INC
MOVX
MOV
DJNZ
MOV
RET
MOV
MOV
JMP
Cycles
•
•
•
DPTR, #200H
R5, #OFFH
TBF
RTS
A,@DPTR
@Rl,A
. A, #OBOH
A,SIUST,WAIT1 •••••••••••••••••••• 2
DPTR ••••••••••••••••••••••••••••• 2
A,@DPTR ••••••••••••••••••••••••• 2
@Rl,A ••••••••••••••••••••••••••• 1
R5,NEXTI ••••••••••••••••••••••••• 2
SIUST,#57H
SIUST, #57H •••••••••••••••••••••• 2
A,#OBOH ••••••••••••••••••••••••• 1
WAITl •••••••••••••••••••••••••••• 1
END
13 Cycles
4-37
FLEXIBILITY IN FRAME SIZE WITH THE 8044
secondary stations, and acknowledges a previously received frame simultaneously (see Figure 17). Both secondary stations, in Auto mode, detect the transmitted
frame and check its address byte. One of the secondary
stations receives the frame, stores the Information bytes
in an external RAM buffer, and transmits the same
data back to the primary; After reception of the frame,
the primary" polls and transmits a long frame to the
other secondary station which :will respond with the
same long frame.
6.2 Multidrop Application
Performance of long frame in addition to the features of
the S044 are described using a simple multidrop communication system in which three RUPIs, one as a
master and the other two as secondary stations, transmit and receive long frames alternately (see Figure 16).
All stations perform automatic zero bit insertion/deletion, NRZI decoding/encoding, Frame Check Sequence (FCS) generation/detection, and on-chip clock
recovery at a data rate of 375 Kbps.
6.2.2 HARDWARE
The primary and the secondary station's software code
is given in Appendix B. These programs, for simplicity,
assume only reception of information and supervisory
frames. It is also assumed that the frames are received
and transmitted in order. All stations use very simil!lf
transmit and receive routines. This code is written for
standard SDLC frames (see Figure 7).
The schematic of the secondary. station hardware is
shown in Figure IS. The primary station's hardware is
similar to the secondary station's hardware. The excep"
tlon is in secondary stations only, where the RTS signal
is inverted and tied to the interrupt 0" input pin (INTO).
In the primary station, RTS is tied to CTS. At each
station, software codes are stored in external EPROM
(2732A). Static RAM (2KxS) is used as external transmit/receive buffer. There is no hardware handshaking
done between the stations. The serial clock is extracted
from the data line using the on-chip phase locked loop.
6.2.1 POLLING SEQUENCE
The primary station, in Flexible mode, transmits a long
frame (for this example, 255 I-bytes), polls one of the
PRIMARY.
STATION
SECONDARY
STATION
SECONDARY
STATION
292019-18
Figure 16. SOLC Multidrop Application Example
PRIMARY
SECONDARY
SECONDARY
292019-19
FI!lure 17. Polling Sequence Between the Primary and Secon!fary Stations
4-38
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36
03
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4
DO
1
35
04
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34
05
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6
33
06
07
06
07
7
8
V~
30
WR
RO
010
000
011
001
012
002
013
003
014
004
015
005
016
006
017
007
19
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17
A2
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A5
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A7
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!!
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292019-20
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intJ
FLEXIBILITY IN FRAME SIZE WITH THE 8044
6.2.3 PRIMARY SOFTWARE
Main Routine
During initialization (see Figure 19), the 8044 is set to
Flexible mode, internally clocked at 375 Kbps, and
configured to handle standard SDLC frames. The onchip receive and transmit buffer starting addresses and
lengths are selected. The external transmit buffer is
chosen from physical location 2DOH to location 2FFH
(255 bytes). The external transmit buffer (external
RAM) is loaded with data (FFH, FEH, FDH, FCH,
... DOH). Timer 0 is put in counter mode and set to
priority 1. The counter register (TLO) is loaded such
that interrupt occurs after 8 transitions on the data line.
The Pre-Frame Sync option (setting bit 2 of the SMD
register) is selected to guarantee at least 16 transitions
before the opening flag of a frame.
The station address register (STAD) is loaded'with address of one of the secondary stations. The RTS, TBF,
and RBE bits of the STS register are simultaneously set
and a call to the transmit routine follows. The transmit
routine transmits the contents of the external transmit
buffer. At the end of transmission, RTS and TBF are
cleared by the SIU, and SIU interrupt occurs. In Flexible mode, SIU interrupt occurs after every transmission or reception of a frame.
SIU Interrupt Routine
In the SIU interrupt service routine (see Figure 20), SI
is cleared and the RBE bit is checked. If RBE is set, a
long frame has been transmitted. The first time through
the SIU interrupt service routine, the RBE test indicates a long frame has been transmitted to one of the
secondary stations. Therefore, the Counter is initialized
=1. FRAME XMITTED
,'--------r----------'/
1
292019-22
292019-21
Main Program
SIU Interrupt
Figure 19. Primary Station Flow Charts
Figure 20. Primary Station Flow Charts
4-40
FLEXIBILITY IN FRAME SIZE WITH THE 8044
and turned on. The program returns from the interrupt
routine before a frame appears on the communication
channel.
When a frame appears on the communication line,
counter interrupt occurs and the receive routine is executed to move the incoming bytes into the external
RAM. After reception of the frame and return from the
receive routine, SIU interrupt occurs again.
In the SIU interrupt routine, RBE is checked. Since the
RBE bit is clear, a frame has been received. Therefore,
the appropriate NS and NR counters are incremented
and loaded into the TCB register (two pairs of internal
RAM bytes keep track of NS and NR counts for the
two secondary stations). Transmission of a frame to the
next secondary station is enabled by setting the RTS
and the TBF bits. The chip is also put in receive mode
(RBE set), and a call to transmit routine is made. After
transmission, SIU interrupt occurs again, and the process continues.
The secondary is configured to transmit an Information
frame every time it is polled. The RTS pin is inverted
and tied to INTI pin. External interrupt I is enabled
and set to interrupt on low to high transition of the
RTS signal. This will cause an interrupt (EXI set) after
a frame is transmitted. In the interrupt routine the CTS
pin is cleared to prevent any automatic response from
the secondary. If the CTS pin were not disabled, the
secondary station would respond with a supervisory
frame (RNR) since the TBF is set to zero by the SIU
due to the acknowledge. In the SIU interrupt routine,
the CTS pin is cleared after the TBF bit is set. If this
option is not used, the primary should acknowledge the
previously received frame and poll for the next frame in
two separate transmissions.
SIU Interrupt Routine
When a frame is received, counter 0 interrupt occurs
and the receive routine is executed (see Figure 22). If
the incoming frame is addressed to the station, the information bytes are stored in extemal RAM; Otherwise, the program returns from the receive routine to
perform other tasks. At the end ofthe frame, SIU interrupt occurs. In Auto mode, SIU interrupt occurs whenever an Information frame or a supervisory frame is
received. Transmission will not cause an interrupt. In
the SIU interrupt service routine, the AM bit of the
STS is checked.
6.2.4 SECONDARY SOFTWARE
Main Routine
Both secondary stations have identical software (Appendix B). The only differences are the station addresses. Contents of the STAD register are 55H for one station and 44H for the other.
If AM bit is set, the interrupt is due to a frame whose
address did not match with the address of the station.
In this case, NFCS, AM, and the BOV bits are cleared,
the RBE bit is set, the counter 0 is initialized and
turned on, and program returns from the interrupt routine.
SET UP EXTERNAL AND INTERNAL
TRANSMIT AND RECEIVE BUffERS
If AM bit is not set, a valid frame has been received and
stored in the external RAM. TBF bit is set, CTS pin is
activated, counter 0 is disabled and a call to transmit
routine is made which transmits the contents of external transmit buffer. This frame also acknowledges the
reception of the previously received frame (NS and NR
are automatically incremented). Upon return from the
transmit routine RBE is set and counter 0 is turned on,
thereby putting the chip in the receive mode for another round of data exchange with the primary.
Note that, if the second station is in receive mode, and
the counter is enabled and turned on, the CPU will be
interrupted each time a frame is on the communication
channel. If the frame is not addressed to the secondary
station, the chip enters the receive routine, executes
only a few lines of code (address comparison) and returns to perform other tasks. This interrupt will not
occupy the CPU for more than two data byte periods
(43 microseconds· at 375 Kbps). At the end of the
frame, the BOV bit is set by the SIU, and the SIU
interrupt occurs. In the SIU interrupt service routine,
292019-23
Main Program
Figure 21. Secondary Station Flow Charts
\
During initialization, the chip is set to Auto mode,
standard SDLC frame, and internally clocked at
375 Kbps (see Figure 21). Internal buffer registers;
RBS, RBL, TBS, and TBL are initialized. The RBE bit
is set and the counter 0 is turned on.
4-41
inter
FLEXIBILITY IN FRAME SIZE WITH THE 8044
In the receive interrupt service routine (see Figure 23),
counter 0 is turned off, important registers are saved,
receive buffer starting address and receive buffer length
of the external RAM are set (do not confuse the external RAM settings with that of the internal RAM buffer.)
After reception of an opening flag, the byte processor
jumps to the ADDRESS state and waits until the bit
processor processes and moves the receiving address
byte to SR. Then, the byte processor is triggered to
execute the state. In the secondary stations, the CPU
monitors the SIUST register for the ADDRESS state
(SIUST = OSH). When the ADDRESS state is
reached, the byte processor is moved to the next state
(CONTROL state), and the ADDRESS state is
skipped. Therefore, when the address byte is moved to
SR, the byte processor executes the CONTROL state
rather than the ADDRESS state and then jumps to the
PUSH-! state. The execution of the CONTROL state
causes the contents of SR (the received address byte) to
be loaded into the RCB register.
=1. ADDRESS MATCH ED
The CPU checks the contents of RCB with the contents
of the STAD (Station Address) register. Ifthey match,
the receive routine continues to store the received Information bytes in the .external RAM buffer; Otherwise, the byte processor is moved to the very last state
(BOV-LOOP), and the program returns from the routine to perform other tasks. The byte processor executes
the BOV-LOOP state in each byte boundary until the
closing flag of the frame is reached. It then sets the
BOV bit and interrupts the CPU (serial interrupt SI
set). In the serial' interrupt routine the counter 0 is
turned back on,' and the station is reset back to the
~eceive mode (RBE set).
292019-24
SIU Interrupt
Figure 22. Secondary Station Flow Charts
the RBE bit is set and the counter is turned on which
put the chip back in the receive mode.
6.2.5 RECEIVE INTERRUPT ROUTINE
Assembly code for the receive interrupt routine can be
found in both primary and secondary software (Appendix B). The receive interrupt routine of the primary
station is very similar to that of the primary station in
example 1. In the following two sections the receive and
transmit routine of the secondary stations are discussed.
In Normal operation, in the ADDRESS state, the received address byte is automatically compared with the
station address. If they match, the byte processor executes the remaining states; otherwise, the byte processor goes into the idle mode (SIUST = O!H) and waits
for the opening flag of the next frame. In the expanded
operation, this state is skipped to avoid idle mode. If
the byte processor went into the idle mode, clocks
which run the byte processor would be turned off, and
the byte processor can not be moved to any other states
by the CPU. When the byte processor is .in idle mode,
counter 0 can not be turned on immediately because
counter interrupt occurs on the same frame, and program returns to the receive routine and stays there.
If the address byte matches the station address, the byte
processor is moved to the CONTROL state again. This
time, after execution of the CONTROL state the contents of RCB are the received control byte.
CPU investigates the type of received frame by checking the received control byte. If the receiving frame is
not an information frame (i.e. Supervisory frame), execution of receive routine will be terminated to free the
4-42
cf
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292019-25
FLEXIBILITY IN FRAME SIZE WITH THE 8044
CPU. In Auto mode, the SIU checks the control byte
and responds automatically in response to the supervisory frame.
After the control byte is received, it is saved in the
stack. The byte processor is moved to the CONTROL
state so that the next incoming byte will also be loaded
into the RCB register. The byte processor remains in
CONTROL state until a byte is processed by the bit
processor and moved to SR. The byte processor is then
triggered to move the contents of SR to the RCB register. The CPU monitors SIUST and waits until the first
Information byte is loaded into the RCB register.
When byte processor reaches the PUSH-l state (SIUST.
= ISH), RCB contains the first Information byte. The
byte is moved to external RAM (receive buffer), and
the byte processor is moved back to the CONTROL
state. The process continues until all of the Information
bytes are received. When all the Information bytes are
received, the program returns from the routine. The
byte processor automatically goes through the remaining states, updates the STS register, and interrupts the
CPU as it would in Normal operation.
6.2.6 TRANSMIT SUBROUTINE
The transmit subroutine codes can be found' in the primary and the secondary software (Appendix B). The
transmit subroutines of the Primary and secondary stations are identical. A call to transmit routine is made
when the RTS and TBF bits of the STS register are set.
In Auto mode, RTS is set automatically upon reception
of a poll-frame (poll bit of the control byte is set).
In the transmit routine (see Figure 15), the starting address and the transmit buffer length of the external
buffer are set. Then the CPU monitors the SIUST register for CONTROL state (SIUST = ASH). In the
CONTROL state the bit processor transmits the control byte, while the byte processor goes into the standby
mode after it has moved the contents of a location in
the internal RAM addressed by the contents of TransII!-it Buffer Start (TBS) register to the RB register.
While the control byte is being transmitted and the byte
processor is in standby, the CPU moves an Information
byte from external RAM to the internal RAM location
addressed by TBS. The byte processor is then moved to
CONTROL state. This will cause the byte processor, in
the next byte boundary, to move the contents of the
same location in the internal RAM to the RB register
(see transmit state diagram.)
,
When this byte is being transmitted, the byte processor
jumps to the DMA-LOOP state (SIUST = BOH) and
waits. When the DMA-LOOP state is reached (CPU
monitors SIUST for BOH), the CPU loads the next Information byte into the same location in the internal
RAM and moves the byte processor to the CONTROL
state before it gets to execute the DMA-LOOP state.
Note that the same location in the internal RAM is
used to transmit the subsequent Information bytes.
When all the Information bytes from the external
RAM are transmitted, the byte processor is free to go
through the remaining states so that it will transmit the
FCS bytes and the closing flag.
7.0 CONCLUSIONS
The RUPI, with addition of only a few bytes of code,
can accept and transmit large frames with S01l1e compromise in the maximum data rate. It can be used in
Auto or Flexible mode, with external or internal clocking, automatic CRC checking, and zero bit insertion/
deletion. In addition, almost all of the internal RAM is
available to be used as general purpose registers, or in
conjunction with the external RAM as transmit and
receive buffers.
All in all, this feature opens up new areas of applications for this device. Besides transmitting/receiving
long frames, it may now be possible to perform arithmetic operations or bit manipulation (e.g. data scrambling) while transmission or reception is taking place,
resulting in high throughput. Transmission of continuous flags and transmission with no zero insertion are
also possible.
In addition to unlimited frame size, an on-chip controller, automatic SDLC responses, full support of SDLC
protocol, 192 bytes of internal RAM, and the highest
data rate in self clocked mode compared to other chips
make this product very attractive.
4-44
inter
FLEXIBILITY IN FRAME SIZE WITH THE 8044
APPENDIX A
LISTING OF SOFTWARE MODULES
FOR APPLICATION EXAMPLE 1
$DEBUG NOMOD5l
$INCLUDE (REG44.PDF)
ASSEMBLY CODE FOR PRIMARY STATION (POINT TO POINT)
FLEXIBLE MODEl FCS OPTION
ORG
OOH
INIT
OBH
REC
23H
SIINT
SJHP
ORG
JMP
ORG
SJHP
LOCATIONS 00 THRU 26H ARE USED
BY INTERRUPT SERVICE ROUTINES.
VECTOR ADDRESS FOR TlMERO INT.
VECTOR ADDRESS FOR SIU INT.
i*************.****.*. INITIALIZATION ********************* ••• **
INIT:
DOT:
ORG
MOV
MOV
MOV
MOV
MOV
MOV
MOV
26H
SMD, '00000110B
TBS, '20H
TBL,'OlH
20H,#55H
THOD,#OOOOOll1B
IE,#lOOlOOlOB
STS,#11100000B
DOT
SJHP
EXT CLOCK 1 PFS=NB~l
INT TRANSMIT BUFFER START
INT TRANSMIT BUFFER LENGTH
STATION ADDRESS
COUNTER FUNCTION 1 MODE
EA=ll SI=ll ETO~l
TRANSMIT A FRAME
WAIT FOR AN INTERRUPT
SIU TRANSMITS THE PFS BYTES, THE OPENNING FLAG, THE CONTENTS
OF LOCATION 20H, THE CALCULATED FCS-BYTES, AND THE CLOSING
FLAG. AT THE END OF TRANSMISSION, SIU INTERRUPT OCCURS.
; *******.* •• *.
SERIAL CHANNEL INTERRUPT ROUTINE
****************
SIINT:
I
CLR
SI
JNB
RBE,RECVED
TRANSMITTED A FRAME ?
MOV
TLO,tOF8H
YES, INITIALIZE COUNTER REGISTER
MOV
DPTR,,200H
EXT RAM RECEIVE BUFFER START
MOV
R5,'OFFH
EXT RAM RECEIVE BUFFER LENGTH
SETB
TRO
TURN ON COUNTER 0
RETI
RETURN
WHEN A FRAME APPEARS ON THE SERIAL CHANNEL, COUNTER (RECEIVE)
INTERRUPT OCCURS. AFTER SERVICING THE INTERRUPT ROUTINE, SIU
INTERRUPT OCCURS.
RECVED: MOV
RETI
STS,#11100000B
292019-28
TRANSMIT A FRAME
RETURN
;** •• ************ RECEIVE INTERRUPT ROUTINE *************.******
REC:
WAITl:
NEXTI:
WAIT2:
END
CLR
MOV
CJNE
MOV
MOV
CJNE
MOV
MOVX
INC
DJNZ
RETI
TRO
A,U8H
A,SIUST,WAITI
SIUST,IOEFH
A,U8H
A, SIUST, WAIT2
A,Res
@DPTR,A
DPTR
R5,NEXTI
DISABLE THE COUNTER 0 INTERRUPT
PUSH-l STATE
MOVE BYP TO CONTROL STATE
PUSH-l STATE
MOVE RECEIVED BYTE INTO Ace.
MOVE DATA TO EXT. RAM
INCREMENT POINTER TO EXT RAM
LAST BYTE RECEIVED?
YES, RETURN
292019-29
4-45
FLEXIBILITY IN FRAME SIZE WITH THE 8044
$DEBUG NOMOD51
$INCLUDE (REG44.PDF)
ASSEMBLY CODE FOR SECONDARY STATION (POINT TO POINT)
.
FLEXIBLE MODEl FCS OPTION
ORG
SJMP
ORG
SJMP
OOH
INIT
23H
SIINT
,_A_A __ ••••••••• _ LOAD
ORG
INIT: MOV
MOV
LORAM: MOV
MOVX
INC
DJNZ
; VECTOR ADDRESS FOR SIU INT.
TRANSMIT BUFFER WITH DATA •••••••••••• _
26H
DPTR,1200H
R3,'OFFH
A,Rl
@DPTR,A
DPTR
Rl,LORAM
EXT RAM XMIT BUFFER START
EXT RAM XMIT BUFFER LENGHT
LOAD EXT BUFFER WITH FFH, FEH, •••
INCREIIEIIT POINTER
;············**·····rNITIALIZATION ••••••••••••• - •••••••••••••
DOT:
MOV
MOV
MOV
MOV
NOV
MOV
MOV
MOV
MOV
MOV
MOV
SJMP
SHO, 'OOOOOllOB
Rl,tlOH
TBS,Rl
TBL,'OlH
RBS,120H
RBL,'OlH
STAD,'55H
TeaN"OOH
1E,I10010QOOB
IP,'OFFH
STS, 'OlOOOOOOB
DOT
,.-._._-_....*.-
EXT CLOClC I
PFS~NBQl
INT RAM XMIT BUFFER START
INT RAM XMIT BUFFER LENGTH
INT RAM RECEIVE BUFFER START
INT RAM RECEIVE BUFFER LENGTH
STAD ADDRESS=55H
RESET TCON REGISTER
ENABLE SI INT. ;EA=l
ALL INTERRUPTS: PRIORITY 1
RBE=l, RECEIVE A FRAME.
HAlT FOR AN INTERRUPT
; sro INTERRUPT OCCURS AT THE END OF A RECEIVED FRAME OR
; A TRANSMITTED FRAME.
SIINT: CLR
JB
MOV
CJNE
ACALL
SERIAL CHANNEL INTERRUPT ROUTINE A._._._. ___ _
SI
RBE, RETRN
A,STAD
A,20H,HMACH
TRAN
292019-30
RECEIVED A FRAME?
YES
STATION ADDRESS MATCHED?
YES, CALL TRANSMIT SUBROUTINE
TRANSMIT SUBROUTINE IS CALLED TO TRANSMIT A LONG FRAME.
AFTER TRANSMISSION, SI IS SET. SIU INTERRRUPT IS SERVICED
AFTER THE CtIRRENT ROUTINE (SIINT) IS COMPLETED.
HMACH: SETB
RETRN: RETI
RBE
; _ 1 , RECEIVE A FRAME
; RETURN
;-_ •••• - •••• _.- TRANSMIT SUBROUTINE -_ •••• _--•• _•••• _.-. ______
TRAN:
NOV
MOV.
SETB
SETB
LOOP: MOV::
MOV
MOV
HAIT1: CJNE
INC
DJNZ
MOVX
MOV
MOV
RET
NEXTI: MOV
JMP
END
DPTR,'200H
RS,'OFFH
TBF
RTS
A,@DPTR
@Rl,A
A,tOBOH
A,SroST,HAITl
DPTR
R5,NEXTI
A,@DPTR
@Rl,A
SIUST,'57H
SIUST,'57H
LOOP
EXT RAM RECEIVE BUFFER START
EXT RAM RECEIVE BUFFER LENGTH
SET TRANSMIT BUFFER FULL
ENABLE XMISSION OF AN I-FRAME
HOVE THE 1ST I-BYTE I~~O ACC.
THEN, MOVE TO INT. RAM @ (TBS)
DNA-LOOP STATE
HAIT FOR XMISSION OF AN I-FRAME
INCREMENT POINTER TO EXT. RAM
ALL BYTES XMITTED?
YES, EXCEPT THE LAST BYTE.
MOVE DATA INTO INT. RAM @ (TBS)
MOVE BYP TO CONTROL STATE
THE SIU TRANSMITS THE FCS-BYTES
AND THE CLOSING FLAG.
RETURN
MOVE BYP TO CONTROL STATE (ABH) •
TRANSMIT THE NEXT BYTE
292019-31
4-46
FLEXIBILITY IN FRAME SIZE WITH THE 8044
APPENDIX B
LISTING OF SOFTWARE MODULES
FOR APPLICATION EXAMPLE 2
$DEBUG NOMOD51
$INCLUDE (REG44.PDF)
ASSEMBLY CODE FOR PRIMARY STATION (MULTIPOINT)
FLEXIBLE MODE; FCS OPTION
ORG
OOH
SJMP INIT
ORG
OBH
JMP
REC
ORG
23H
SJMP SIINT
LOCATIONS 00 THRU 26H ARE USED
BY INTERRUPT SERVICE ROUTINES.
VECTOR ADDRESS FOR TlMERO INT.
VECTOR ADDRESS FOR SIU INT.
;** ••• *********** LOAD TRANSMIT BUFFER WITH DATA
*** •••••••••
ORG
26H
INIT: MOV
DPTR,#200H
EXT RAM XMIT BUFFER START
MOV
R3,fOFFH
EXT RAM XMIT BUFFER LENGHT
LDRAM: MOV A,R3
MOVX @DPTR,A
LOAD BUFFER WITH FFH,FEH, ••• OO
INC
DPTR
INCREMENT POINTER
DJNZ R3 , LDRAM
; ••••••••••••••••••••• INITIALIZATION **t ••••••••••••••••••••
LOOP:
MOV
MOV
MOV
DEC
CJNE
RO,loBFH
A,jOOH
@RO,A
RO
RO,14oH,LOOP
PUT ZEROS INTO INT. RAM
FROM BFH TO 40H.
MOVE 0 INTO RAM,ADDRESSD BY RO
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
30H,#00H
31H, 'OOH
32H, 'OFFH
33H, 'OFFH
34H, 'OlH
SMD"11010100B
RBS,flOH
RBL, tOOH
R1,12oH
TBS,Rl
TBL, f01H
NSNR, tOOH
TMOD,'OOOOOlllB
TCON"OOH
IE,'10010010B
IP,'00000010B
TCB,#00010000B
STAD, #55H
STS"11100000B
NS COUNTER FOR STAD=55
NR COUNTER FOR STAI)oo55
NS COUNTER FOR STAD=44
NR COUNTER FOR STAD=44
PONITER TO SECONDARY STATIONS
INT. CLKED @ 375K; NRZI-1; PFS-1
INT. RAM RECEIVE BUFFER START-10H
INT. RAM RECEIVE BUFFER LENGTH-O
INT. RAM XMIT BUFFER START=20H
, 292019-32
INT. RAM XMIT BUFFER LENGTH=l
NS=NR=O
COUNTER FUNCTION, MODE 3
EA=l; SI=l; ETO=l
TIMER 0 INT. PRIORITY 1
I-FRAME W/POLL
ADDRESS BYTE=55H
RBE=TBF=RTS=l
TRANSMIT A LONG FRAME WITH POLL BIT SET, WAIT FOR A
RESPONSE.
ACALL TRAN
DOT:
SJMP
DOT
CALL TRANSMIT ROUTINE
WAIT FOR AN INTERRUPT
4-47
292019-33
intJ
FLEXIBILITY IN FRAME SIZE WITH THE 8044
; ••••••••••••• SERIAL INTERRUPT ROUTINE •• tt •••••••••••••••••
SIINT:
SKIP:
CLR
81
JB
RBE, RETI1RII
MOV
A,lteB
JB
ACC.O,GETI
MOV
A,'OlH
CJNE A,34H,SKIP
MOV
A,30H
INC
A
ANL
A, 'OOOOO111B
MOV
30H,A
MOV
A,3lH
INC
A
ANL
A, ,OOOOOl11B
MOV
31H,A
RL
.A
RL
A
RL
A
RL
A
ORL
A,30H
RL
A
ORL
A,'OOOlOOOOB
MOV
TeB,A
MOV
MOV
JHP
MOV
INC
ANL
MOV
MOV
INC
ANL
MOV
RL
RL
RL
RL
ORL
RL
ORL
MOV
STAD"SSH
34H,fOOH
GE'l'l:
A,32H
A
A, 'OOOOOl11B
32H,A
A,33H
A
A, ,OOOOOl11B
33H,A
A
A
A
A
A,33H
A
A, 'OOO10000B
TCB,A
CLEAR 81
RECEIVED A FRAME ?
YES, LOAD Ace WITH REC CNTRL BYTE
I IS IT AN I-FRAME ?
YES
MOVE NS INTO
INCREIIEN'l' NS
!!ASK 01lT THE
SAVE NS
KOVE NR INTO
INCREIIEN'l' NR
!!ASK OIlT THE
SAVE NR
SHIFT 4 BITS
ACC.
LEAST 3 SIG. BITS
ACC.
LEAST 3 8XG. BXTS
TO LEFT
HOVE NS COUll'l' TO ACC.
SHIFT 1 BIT TO LEFT
I SET THE POLL BXT
MOVE CONTROL BYTE XNTO TCB REG.
TCB: NR2,NR1,NRO,1,NS2,NS1,NSO,0
292019-34
MOVE NS INTO Ace.
INCREIIEN'l' NS.
MASK 01lT THE LEAST 3 SIG. BITS
SAVE NS
I lIOVE NR INTO Ace.
INCREM£N'l' NR
!!ASK 01lT THE LEAST 3 SIG. BITS
SAVE NR
SHIFT 4 BITS TO LEFT
HOVE NS COUll'l' TO ACC.
SHIFT 1 BIT TO LEFT
SET THE POLL BIT
MOVE CONTROL BYTE INTO TeB
TeB: NR2,NR1,NRO,1,NS2,HS1,NSO,O
MOV
STAD,#44H
MOV
34H,'OlH
MOV
STS,I11100000B
ENABLE TRANSMISSION
ACALL TRAN
CALL TRANSMIT ROIlTINE
RETI
RETI1RII: CLR
EA
DISABLE ALL INTERRUPTS
MOV
TLO,'OFBH
INTERRUPT AFTER 8 COUll'l'S
SETB mo
I TI1RII ON COUNTER 0
SETB EA
RETI
, •••••••••••••• RECEIVE INTERRUPT ROUTINE At.t •••••••••••••••
GETI:
REC:
WAIT1:
NEXTI:
WAIT2:
CLR
MOV
MOV
MOV
CJNE
PUSH
MOV
HOV
CJNE
MOV
MOVX
XNC
DJNZ
POP
RETI
TRO
DP'l'R,f400H
RS"OFFH
A,fl8H
A, SIUST. WAITl
RCB
SIUST, 'OEFH
A,U8H
A,SIUST,WAIT2
A,RCB
@DP'l'R,A
DP'l'R
RS,NEXTI
RCB
292019-35
'; TURN OFF COUll'l'ER 0
EXT. RAM RECEIVE BUFFER START.
EXT. RAM RECEIVE BUFFER LENGTH
PUSH-l STATE
WAIT FOR THE CONTROL BYTE
SAVE RECEIVE CONTROL BYTE
PUSH "BYP" INTO CONTROL STATE (lOH) •
PUSH-l STATE
WAIT FOR AN I-BYTE
MOVE RECEIVED I-BYTE INTO ACC.
MOVE DATA '1'0 EXT. RAM
INCREHENT P'l'R TO EXTERNAL RAM
IS IT THE LAST I-BYTE?
YES, RESTORE THE CONTENTS OF RCB
RETURN
;*t ••••••••••••••• TRANSMIT SUBROUTINE *****.*.**.*~*******.*
TRAN:
MOV
MOV
MOV
WAIT:
NXTII
CJNE
MOVX
MOV
INC
DJNZ
MOV
RET
MOV
MOV
JMP
END
DPTR,1200H
RS,'OFFH
A,'OA8H
A,SIUST,WAIT
A,@DP'l'R
@Rl,A
DP'l'R
RS,NXTI
SlUST,157H
SlUST, 'S7H
A,tOBOH
WAIT
EXT. RAM TRANSMIT BUFPER START
EXT. RAM TRANSMIT BUFFER LENGTH
CONTROL STATE
WAIT FOR CTRL BYTE XMISSION
MOVE DATA FROM EXT. RAM TO Ace.
MOVE DATA INTO INT. RAM @ (TBS)
INCREMBN'l' POINTER
IS IT THE LAST I-BYTE ?
NO. XMIT THE LAST I-BYTE
RETURN •
KEEP "BYP" IN CONTROL STATE (A8H) •
DMA-LOOP STATE
TRANSMIT THE NEXT BYTE
292019-36
4-48
FLEXIBILITY IN FRAME SIZE WITH THE 8044
$DEBUG NOMOD51
$INCLUDE (REG44.PDF)
; ASSEMBLY CODE FOR SECONDARY STATIONS (MULTIPOINT)
; AUTO MODE; FCS OPTION
ORG
SJHP
ORG
JHP
ORG
JHP
ORG
JHP
DOH
INIT
OBH
REC
13H
XINT1
23H
SIINT
'. VECTOR ADDRESS FOR TlMERO INT.
VECTOR ADDRESS FOR EXT. INT. 1
VECTOR ADDRESS FOR SIU INTERRUPT
;***. '* '* .. '*. * ••• ** * ** ·INITIALIZATION '* * * *. '* '* ** '* *. '* '* *•• '* '* ** .. '* *** *
INIT:
ORG
MOV
MOV
26H
SMD,#llOlOlOOB
STAD,#55H
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
MOV
RBS,flOH
RBL, HOOH
Ri,#20H
TBS,R1
TBL,f01H
NSNR,#OOH
TCON,#OOOOOlOOB
IE, #00010110B
IP,#OOOOOOlOB
THOD, #OOOOOllB
STS,#OlOOOOlOB
TLO,#OF8H
INT. CLKED @ 375K;NRZI=1;PFS=1
STATION ADDRESS; STAD=44H FOR THE
OTHER STATION
INT. RAM RECEIVE BUFFER START
INT. RAM RECEIVE BUFFER LENGTH
INT. RAM XHIT BUFFER START
INT. RAM XHIT BUFFER LENGTH
NS=NR=O
EXT. INT.: EDGE TRIGGERED
SI=l; ETO=l; EXO=l
TIMER 0: PRIORITY 1
COUNTER FUNCTION: MODE
RECEIVE I-FRAME.
SET COUNTER TO OVERFLOW
AFTER 8 COUNTS
SETB TRO
TURN ON COUNTER
SETB EA
ENABLE ALL INTERRUPTS
DOT:
SJHP DOT
; WAIT FOR AN INTERRUPT.
; CPU IS INTERRUPTED AT THE END OF RECEPTION (SI SET), AND AT.
; THE END OF LONG-FRAME TRANSMISSION (EXO SET).
;********* •••• **EXTERNAL
XINT1:
SETB
RETI
CLR
JB
CLR
MOV
MOV
SETB
SETB
RETI
*.*.* •••• *.****'It*Iir*Ii'.l*****:r.*
; DISABLE CTS PIN
; RETURN.
; *.*.*.********to
SIINT:
INTERRUPT
Pl. 7
292019-37
SERIAL INTERRUPT ROUTINE ••• ,;,.*.w************
51
AN,HOP
EA
STS,f01000010B
TLO,#OFSH
TRO
EA
;
ADDRESS HATCHED?
DISABLE ALL INTERRUPTS
RBE=l; NB=l
I
TURN ON COUNTER 0
ENABLE ALL INTERRUPTS
RETURN.
HOP:
JB
TBF,GETI
A FRAME TRANSMITTED?
SETB TBF
ENABLE TRANSMISSION OF I-FRAME
CLR
Pl.7
ENABLE CTS PIN
ACALL TRAN
CALL TRANSMIT ROUTINE
GETI:
JB
RBE,RETURN
A FRAME RECEIVED?
CLR
EA
DISABLE ALL INTERRUPTS
SETB RBE
PUT RUPI IN RECEIVE MODE
MOV
TLO,jOFSH
SETB TRO
TURN ON COUNTER 0
SETB EA
ENABLE ALL INTERRUPTS
RETURN: RETI
RETURN.
i*******·***··.*** TRANSMIT SUBROUTINE ******.*.********.* ••••
TRAN:
WAIT:
NXTI:
MOV
MOV
MOV
CJNE
MOVX
MOV
INC
IlJNZ
MOV
RET
MOV
MOV
JHP
DPTR,j200H
RS,JOFFH
A,IOASH
A,SIUST,WAIT
A,@DPTR
@Rl,A
DPTR
R5,NXTI
SIUST,'57H
SlUST,'57H
A, #OBOH
WAIT
EXT. RAM TRANSMIT BUFFER START
EXT. RAM TRANSMIT BUFFER LENGTH
CONTROL STATE
WAIT FOR CONTROL BYTE TRANSMISSION
MOVE DATA FROM EXT. RAN TO ACC.
MOVE DATA INTO INT. RAN AT @TBS
INCREMENT POINTER
IS IT THE,LAST I-BYTE?
XHIT THE LAST I-BYTE
RETURN.
KEEP "BYP" IN CONTROL STATE
DHA-LOOP STATE
TRANSMIT THE NEXT BYTE
4-49
292019-38
292019-39
inter
FLEXIBILITY IN FRAME SIZE WITH THE 8044
:*******··*RECErvE INTERRUPT ROUTINE ••••••••••••••••••••••••••
REC:
HOLD:
WAITl:
CLR
MOV
MOV
MOV
CJIIE
MOV
MOV
CJIIE
MOV
CJIIE
SJMP
WAIT2:
MOV
MOV
TRO
DPTR,t200H
RS"OFFK
A,t08H
A,SIUST,HOLD
SIUST, tOEFH
A,fl8H
A,SIUST,WAITl
A,RCB
A,STAD,WAIT2
WAIT3
RCB,fOOOlOOOOB
SIUST, tOCFH
RETI
WAIT3:
WAIT4:
MOV
MOV
CJNE
MOV
JB
WAITS:
PUSH
MOV
MOV
CJIIE
MOV
MOVX
INC
RTRN:
END
RETI
NEXTI:
DJNZ
POP
TORI! OFF COUNTER 0
EXT. RAM RECEIVE BUFFER START
I EXT. RAM RECEIVE BUFFER LENGTH
ADDRESS STATE
WAIT FOR ADDRESS BYTE
.MOVE "BYP" INTO CONTROL STATE
SKIP THE ADDRESS STATE
PUSH-l STATE
WAIT FOR TRE ADDRESS BYTE
MOVE THE RECEIVED ADDRESS BYTE TO ACC.
ADDRESS MATCHED?
YES.
MOVE INFO. CONTROL BYTE TO RCB
MOVE "BYP" INTO BOV-LOOP STATE
RETORII
B-IUST, 'OEFH
A,U8K
A,SIUST,WAIT4
A,RCB
ACC.O,RTRN
RCB
SIUST,'OEFH
A,U8H
A,SIUST,WAITS
A,RCB
@DPTR,A
DPTR
RS,NEXTI
RCB
MOVE "BYP" INTO CONTROL STATE
PUSH-l STATE
WAIT FOR THE CONTROL BYTE
I MOVE RECEIVE CONTROL BYTE INTO ACC.
IF NOT AN I -FRAME RETORI!
SAVE RECEIVE CONTROL BYTE
PUSH "BYP" INTO CONTROL STATE(lOH).
PUSH-l STATE
WAIT FOR AN I-BYTE
MOVE RECEIVED I-BYTE INTO ACC.
MOVE DATA TO EXT. RAM
INCREMENT PTR TO EXTERNAL RAM
IS IT THE LAST I-BYTE?
YES. RESTORE THE CONTENTS OF RCB
RETORI!
292019-40
4-50
80186/188 Application Notes
5
inter
AP-186
APPLICATION
NOTE
November 1988
Using the
80186/188/C186/C188
@ Intel Corporation, 1988
Order Number: 210973-006
5-1
..:.;
'. AP-186
in the data sheet. The second is to describe, through
examples, the use of the 80186 with other digital logic
such as memory.
1.0 INTRODUCTION
The 80186 microprocessor family holds the position of
industry standard among high integration microprocessors. VLSI technology incorporates the most commonly used peripheral functions with a 16-bit CPU on the
same silicon die to assure compatibility and high reliability (see Figure I). The 80186 reputation for flexibility and uncomplicated programming make it the first
choice microprocessor for such data control applications as local area network equipment, PC add-on
cards, terminals, disk storage subsystems, avionics, and
medical instrumentation.
The 80186 family actually consists of 4 devices: the
original 80186 and 80188, and the new 80C186 and
80CI88 microprocessors manufactured on Intel's
CHMOS III process. The 80188 and 8OC188 are 16-bit
microprocessors but have 8-bit external data buses. The
80C186 and 80C188 offer the advantage of increased
speed (up to 16 MHz) and important new features including a Refresh Control Unit, Power-Save Logic, and
ONCETM Mode (see Figure 2). For simplicity, this Ap
Note uses the name 80186 to refer collectively to all the
members of the 80186 family. Differences between individual processors are pointed out as necessary.
There are two purposes to this Application Note. The
first is to explairithe operation of the integrated 80186
peripheral .set with a degree of detail not possible
~D~T
Vee
,--
X1
INT3/1NTf
NIII
PROGRAIiMABlE
INTERRUPT
CONTROLLER
ClOCK
GENERATOR
..-
c:aNTROI.
i2
J~
~~
LOGIC
I~ f-
~
HOLD
HLDA
~
ADO·
AD15
.~
1
Ma::::::NT I
DIIA CONTROL
UNIT
1
. .lIT IOURCE
POINTERS
M":::TEc::"T
n .•'!n~~~::TION
1..,rrCOUIl1" REOfSTERI
~ItIGIITE"
CGlfTROL RECIIS1I:RS
1~
.
JI 7
~I
EXECUTION UNIT
1&-BIT
GENERAL
REGISTERS
fRY/BUSY
RESET
DRt'
1..." COUNT RlGtlTERI
AD
RES
DiQO
a
2
CHIP
SELECT
CONTROL
UNIT
1e·BIT ALU
7 ALE
A~,6;/~:·
PROGRAMMABlE
TIMERS
a
J~
RE_
~
~~...d
LOCK
JTM1UTI
.
'EGIIENT
01_
DEN +
TMR IN 1
',. '··~r
~t
BUS INTERFACE UNIT
DTIII
TIiRtOJ
•
1t
!lO·
TIIR OUT a
IN;"'
X2
GND
SRDYARDY-
flY'
INT2nNTAO
ClKOUT
'",'
MCSO·3
II
PCS
....!l
PCSO·4
iics
WR
BHE/S7
PCSiI
CS
~
LCS
-
210973-1
Figure 1.80186 Block Diagram
5-2
inter
AP-186
rD~l
Vee
-1-
GND
SO-
52
i~
DT/A
DEN +
...
TMR OUT 0
1
IN,TO
TMR IN 1
TMR1INOf
-,
T~RtOUT 1
DRt O
DRtl
~
Xl
X2
CLOCK
GENERATOR
POWERSAVE
CONTROL
.1
CONTROL
AEOISTEAS
POINTERS
MAXIMUM COUNT
REGISTER A
2•. 81!~I~~1'::TIOH
1..111 COUNT REGISTERS
11·811 COUNT REGISTERS
~
EXECUTION UNIT
REFRESH
CONTROL
UNIT
REGISTERS
r
A19/S6
CONTROL
REGISTERS
16-BIT
GENERAL
REGISTERS
~.,
I
l~TEST/BUSY
ALE
RD
RES
RESET
MCSO/PEREO
--5/
PCS
~
--6/
PCS
~
I I
••
t J
MCS1/ERROR
- MCS3INPS
WR
BHE
I
CHIP
SELECT·
CONTROL
UNIT
NUMERICS INTERFACE
~16~S3-
Jp
16-BIT ALU
I
~ r~
CONTROL REGISTERS
~------_&_-------
CONTROL
I
ADOAD15
1
:l1I·Bll SOURCE
4
:E~~::a I
"R~~'i.uEUd
HOLD
HLDA
0
2
CONTROL REGISTERS
J~
I
BUS INTERFACE UNIT
LOCK;
1
0
DMACONTROL
UNIT
IIA:~~~s~~::NT I
!It.
READY
LOGIC
f-
PROGRAMMABLE
TIMERS
PROGRAMMABLE
INTERRUPT
CONTROLLER
-t
:
l
INT3/INTf f
NMI
REGISTERS
SRDYAAD Y-
r
INT2/INTAO
CLKOUT
I
_
PCSO-4
LCS
UCS
MCS2
210973-A2
Figure 2. 80C186 Block Diagram
2.0 OVERVIEW OF THE 80186
FAMILY
registers, the instruction pointer, and immediate values
(see Figure 3). Any carry of this addition is ignored.
The result is a 20-bit physical address.
2.1 TheCPU
The 80186 has a 16-bit ALU which performs 8 or 16bit arithmetic and logical operations. It provides for
data movement among registers, memory and I/O
space. In addition, the CPU allows for high speed data
transfer from one area of memory to another using
string move instructions, and to or from an I/O port
and memory using block I/O instructions. Finally, the
CPU provides many conditional branch and control instructions.
The 80186 CPU shares a common base architecture
with the 8086, 8088, 80286, and 80386 processors. It is
completely object code compatible with the 8086/88.
This architecture features four 16-bit general purpose
registers (AX, BX, CX, DX) which may be used as
operands in most arithmetic operations in either 8- or
16-bit units. It also features four 16-bit pointer registers
(SI, DI, BP, SP) which may be used both in arithmetic
operations and in accessing memory based variables.
Four 16-bit segment registers (CS, DS, SS, ES) allow
simple memory partitioning to aid construction of modular programs. Finally, it has a 16-bit instruction pointer and a 16-bit status register.
In the 80186, as in the 8086, instruction fetching and
instruction execution are performed by separate units:
the bus interface unit and the execution unit, respectively. The 80186 also has a 6-byte prefetch queue as
does the 8086. The 80188 has a 4-byte prefetch queue
as does the 8088. As a program is excecuting, opcodes
are fetched from memory by the bus interface unit and
placed in this queue. Whenever the execution unit requires another opcode byte, it takes the byte out of the
queue. Effective processor throughput is increased by
Physical memory addresses are generated by the 80186
identically to the 8086. The 16-bit segment value is
shifted left 4 bits and then added to an offset value
which is derived from combinations of the pointer
5-3
inter
AP·186
I'
I'
SEGMENT ,VALUE
I
16 BITS
1
'1
1
2.4 Timers
1
I
1
1
I
1
I
I
+
OFFSET
PHYSICAL ADDRESS
I
I,
I
1
1
I
count which can terminate a series of DMA transfers
after a pre-programmed number of transfers.
'I
18 BITS
=
.1
20 BITS
The timer unit contains 3 independent 16-bit timer/
,counters. Two of them can count external events, provide waveforms based on either the CPU clock or an
extemal clock, or interrupt the CPU after a specified
count. The third timer/counter counts only CPU
clocks. After a programmable interval, it can interrupt
the CPU, provide a clock pulse to either or both of the
other timer/counters, or send a DMA request pulse to
the integrated DMA controller.
210973-2
2.5 Interrupt Controller
Figure 3. Physical Address
Generation in the 80186
The integrated interrnpt controller arbitrates interrupt
requests between all internal and external sources. It
can be'directly cascaded as the master to an external
8259A or 82C59A interrupt controller. In addition, it
'
can be configured as a slave controller.
adding this queue, since the bus interface unit may continue to fetch instructions while the execution unit exe·
c\ltes a long instruction. Then, when the CPU completes this instruction, it does not have to wait for another instruction to be fetched from memory.
2.6 Clock Generator
2.2 80186 CPU Enhancements
The on-board crystal oscillator can be used with a parallel resonant, fundamental mode crystal at 2X the desired CPU clock speed (i.e., 16 MHz for an 8 MHz
80186), or with an external oscillator also at 2X the
CPU -clock. The output of the oscillator is internally
divided by two to provide the 50% duty cycle CPU
clock from which all 80186 system timing is derived.
The CPU clock is externally available, and all timing
parameters are referenced to it.
Although the 80186 is completely object code compatible with the 8086, most of the 8086 instructions require
fewer clock cycles to execute on the 80186 than on the
8086 because of hardware enhancements in the bus interface unit and the execution unit. In addition, the
80186 has many new instructions which simplify assembly language programming, enhance the performance of high level language implementations, and reduce code size. The added instructions are described in
Appendix H of this Ap Note.
2.7 Chip Select and Ready
Generation Unit
2.3 DMA Unit
The 80186 includes integrated chip select logic which
can be used to enable memory or peripheral devices. Six
output lines are used for memory addressing and seven
output lines are used for peripheral addressing.
The 80186 includes a DMA unit which provides two
flexible DMA channels. This DMA unit will perform
transfers to or from any combination of I/O space and
memory space in either byte or word units. Every
DMA cycle requires two to four bus cycles, one or two
to fetch the data and one or two to deposit the data.
This allows word data to be located on odd boundaries,
or byte data to be moved from odd locations to even
, locations.
The memory chip select lines are split into 3 groups for
separately addressing the major memory areas in a,typical 80186 system: upper memory for reset ROM, lower
memory for interrupt vectors, and mid-range memory
for program memory. The size of each of these regions
is user programmable. The starting location and ending
location of lower memory and upper memory are fixed
at OOOOOH and FFFFFH respectively; the starting location of the mid.range memory is user programmable.
Each DMA channel maintains independent 20-bit
source and destination pointers. Each of these pointers
may independently address either I/O or memory'
space. After each DMA cycle, the pointers may be op-,
t1onally'mcremented, decremented, or maintained constant. Each DMA channel also maintains a transfer
Each of the seven peripheral select lines address one of
seven contiguous 128 byte blocks above a programmable base address., This base address can be located in
5-4
inter
AP-186
either memory or I/O space so that peripheral devices
may be I/O or memory mapped.
The beginning of a T state is signaled by a high to low
transition of the CPU clock. Each T state is divided
into two phases, phase I (or the low phase) and phase 2
(or the high phase) (see Figure 4).
Each of the programmed chip select areas has associated with it a set of programmable ready bits. These bits
allow a programmable number of wait states (0 to 3) to
be automatically inserted whenever an access is made
to the area of memory associated with the chip select
area. In addition, a bit determines whether the external
ready signals (ARDY and SRDy) will be used, or
whether they will be ignored (i.e., the bus cycle will
terminate even though a ready has not been returned on
the external pins). There are 5 total sets of ready bits
which allow independent ready generation for each of
upper memory, lower memory, mid-range memory, peripheral devices 0-3 and peripheral devices 4-6.
L
~~l~10j~
I
I
I
I
2.8 Integrated Peripheral Accessing
01
(LOW
PHASE)
I
I
I
I
02
(HIGH
PHASE)
I
I
I
I
210973-3
The integrated peripheral and chip select circuitry is
controlled by sets of 16-bit registers accessed using
standard input, output, or memory access instructions.
These peripheral control registers are all located within
a 256 byte block which can be placed in either memory
or I/O space. Because they are accessed exactly as if
they were external devices, no new instruction types are
required to access and control the integrated peripherals.
NOTES:
1. Falling edge of Tn.
2. Rising edge of Tn.
Figure 4. T-state In the 80186
Different types of bus activity occur for all of the
T-states (see Figure 5). Address generation information
occurs during Tl> data generation during T2, T3, Tw
and T 4. The beginning of a bus cycle is signaled by the
status lines of the processor going from a passive state
(all high) to an active state in the middle of the T-state
immediately before T\ (either a T4 or a Tj). Information concerning an impending bus cycle appears during
the T-state immediately before the fIrst T-state of the
cycle itself. Two different types of T4 and Tj can be
generated: one where the T state is immediately followed by a bus cycle, and one where the T state is
immediately followed by an idle T state.
3.0 USING THE 80186 FAMILY
3.1 Bus InterfaCing to the 80186
3.1.1 OVERVIEW
The 80186 bus structure is very similar to that of the
8086. It includes a multiplexed address/data bus, aJong
with various control and status lines (see Table I). Each
bus cycle requires a minimum of 4 CPU clock cycles
along with any number of wait states required to accommodate access limitations of external memory or
peripheral devices. The bus cycles initiated by the
80186 CPU are identical to the bus cycles intitiated by
the 80186 integrated DMA unit.
During the fIrst type of T4 or Tj, status information
concerning the impending bus cycle is generated for the
bus cycle immediately to follow. This information will
be available no later than tCHSV after the low-to-high
transition of the 80186 clock in the middle of the T
state. During the second type of T4 or Tj, the status
outputs remain inactive because no bus cycle will follow. The decision on which type T4 or Tj state to present is made at the beginning of the T-state preceding
the T4 or Tj state (see Figure 6). This determination has
an effect on bus latency (see Section 3.3.2).
Each clock cycle of the 80186 bus cycle is called a "Tn
state, and are numbered sequentially Tl> T2, T3, Tw
and T 4. Additional idle T states (Tj) can occur between
T4 and T\ when the processor requires no bus activity
(instruction fetches, memory writes, I/O reads, etc.).
.The ready signals control the number of wait states
(tw) inserted in each bus cycle. The maximum number
of wait states is unbounded.
5-5
AP-186
T,
T.
LINES
DATA
LINES
ADDRESSI
;----~~~~~ '-+---;----+T--..1
CONTROL
..,..----T----....,.,)
SIGNALS
(RD,WR)
210973-4
Figure 5. Example Bus Cycle of the 80186
Table 1.80186 Bus Signals
Function
Signal Name
address/ data
address/ status
co-processor control
local bus arbitration
local bus control
multi-master bus
ready (wait) interface
status information
ADO-AD15
A16/53-A19-56, SHE/57
TEST
HOLD, HLDA
ALE, RD, WR, DT /A, DEN
LOCK
5RDY,ARDY
SO-52
I
Tw
I
I
I
~
.
I
I
I.
I
r-1L.-.-..ArI~
CLOCK
OUT
STATUS
INFO
T.
Decision: No'bus activity required:
idle bus cycles will be inserted
I
I
I
-'::':':==-+..1
:;I~i
I
I
:
T3 0r
I
I
INACTIVE
STATUS
:
I
T,
T.
:
T.
:
Decision: Another bus cycle immediately
required-no idle bus cycles
I
I
CLOCK
OUT
STATUS
LINES
ACTIVE
STATUS
ACTIVE
STATUS
-==;.... . .
...1
210973-5
Figure 6. Active-Inactive Status Transitions in the 80186
5-6
intJ
AP-186
propagation delay. Note that the 80186 drives ALE
high one full clock phase earlier than the 8086 or the
82C88 bus controller, and keeps it high throughout the
8086 or 82C88 ALE high time (i.e., the 80186 ALE
pulse is wider).
3.1.2 PHYSICAL ADDRESS GENERATION
Physical addresses are generated by the 80186 during
T 1 of a bus cycle. Since the address and data lines are
multiplexed on the same set of pins, addresses must be
latched during T 1 if they are required to remain stable
for the duration of the bus cycle. To facilitate latching
of the physical address, the 80186 generates an active
high ALE (Address Latch Enable) signal which can be
directly connected to a transparent latch's strobe input.
A typical circuit for latching physical addresses is
shown in Figure 8. This circuit uses 3 transparent octal
non-inverting latches to demultiplex all 20 address bits
provided by the 80186/80188. Typically, the upper 4
address bits only select among various memory components or subsystems, so when the integrated chip selects
(see Section 8) are used, these upper bits need not be
latched. The worst case address generation time from
the beginning of TI (including address latch propagation time for the circuit is:
Figure 7 illustrates the physical address generation parameters of the 80186. Addresses are guaranteed valid
no greater than tCLA V after the beginning of T \> and
remain valid at least tCLAX after the end of T I. The
ALE signal is driven high in the middle of the T state
(either T4 or Tj) immediately preceding TI and is driven low in the middle ofT\> no sooner than tAVLL after
addresses become valid. This parameter (tAVLd is required to satisfy the address latch set-up times of address valid until strobe inactive. Addresses remain stable on the address/data bus at least tLLAX after ALE
goes inactive to satisfy address latch hold times.
tCLAV
Many memory or peripheral devices may not require
addresses to remain stable throughout a data transfer.
If a system is constructed wholly with these types of
devices, addresses need not be latched. In addition, two
of the peripheral chip select outputs of the 80186 may
be configured to provide latched A 1 and A2 outputs for
peripheral register selects in a system which does not
demultiplex the address/data bus.
T,OR
T.
+ tpD
T,
CLOCK
A16·
4
I
AlB
ALE --~
AO·AI9
LATCHED ADDRESS
SIGNALS
186 SIGNALS
OUT
r - - - STB
Of
----~.l:7j~~!:~~--
0
/4
/
A16·A19
210973-6
AD8·
NOTES:
8
A015
1.
2.
3.
4.
tCHLH: Clock high to ALE high
tCLAV: Clock low to address valid
tCHLL: Clock high to ALE low
tCLAx: Clock low to address invalid (address hold
from clock low)
5. tLLAX: ALE low to address invalid (address hold from
ALE)
6. tAVLL: Address valid to ALE low (address setup to
ALE)
r-
-
..--
ADO·
I
STB
/8
0
A6·A15
OE
6
I
AD7
ALE
STB
0
/8
/
AO·A7
f-- OE
Figure 7. Address Generation
Timing of the 80186
-::210973-7
Because ALE goes high before addresses become valid,
the delay through the address latches will be the propagation delay through the latch rather than the delay
from the latch strobe, which is typically longer than the
Figure B. Demultiplexing the Address Bus
of the 80186 Using Transparent Latches
5-7
AP-186
One more~al is generated by the 80186 to address
memory: BHE (Bus High Enable). This signal, along
with AO, is used to enable byte devices connected to
either or both halves (bytes) of the 16-bit data bus. Because AO is used only to enable deyices,onto the lower
half of the data bus, memory chip address inputs are
usually driven by address bits AI-AI9, not AO-AI9.
This provides 512K unique word addresses, or 1M
unique byte addresses. BHE is not present on the 8-bit
80188. All data transfers occur on the 8-bits of the data
bus.
When byte reads are made, the data returned on the
unused half of the data bus is ignored. When byte
writes are made, the data driven on the unused half of
the data bus is indeterminate.
3.1.4 80188/80C188 DATA BUS OPERATION
Because the 80188 and 80CI88 externally have only 8bit data buses, the above discussion about upper and
lower bytes ofthe data bus does not apply. No performance improvement will occur if word data is placed on
even boundaries in memory space. ~JI word accesses
require two bus cycles, the first to access to lower byte
of the word; the second to access the upper byte of the
word.
3.1.3 80186/80C186 DATA BUS OPERATION
Throughout T2, T3, Tw and T4 of a bus cycle the multiplexed address/data bus becomes a 16·bit data bus.
Data transfers on this bus may be either bytes or words.
All memory is byte addressable (see Figure 9).
Any 80188/80C188 access to the integrated peripherals
is performed 16 bits at a time, whether byte or word
addressing is used. If a byte operation is used, the external bus only indicates a single byte transfer even though
the word access takes place.
All bytes with even addresses (AO = 0) reside on the
lower 8 bits of the data bus, while all bytes with odd
addresses (AO = 1) reside on the upper 8 bits of the
data bus. Whenever an access is made to ,only the even
byte, AO is driven low, BHE is driven high, and the
data transfer occurs on DO-D7 of the data bus. Whenever an access is made to' only the odd byte, BHE is
driven low, AO is driven high, and the data transfer
Occurs on 08-015 of the data bus. Finally, if a word
access is performed to an even address, both AO and
BHE are driven low and the data transfer occurs on
00-015 of the data bus.
3.1.5 GENERAL DATA BUS OPERATION
Because of the bus drive capabilities of the 80186, additional buffering may not be required in many small systems. If data buffers are not used in the system, care
should be taken not to allow bus contention between
the 80186 and the devices directly connected to the
80186 data bus. Since the 80186 floats the address/data
bus before activating any command lines, the only requirement on a directly connected device is that it float
its output drivers after a read before the 80186 begins
to drive address information for the next bus cycle. The
,E!..rameter of interest here is the minimum time. from
RD inactive until addresses active for the next bus cycle (tRHAV)' If the memory or peripheral device cannot
disable its output drivers in this time, data buffers will
be required to prevent both the 80186 and the device
from driving these lines concurrently. This parameter is
unaffected by the addition of wait states. Data buffers
solve this problem because their output float times are
typically much faster than the 80186 required minimum.
Word accesses are made'to the addressed byte and to
the next higher numbered byte. If a word access is performed to an odd address, two byte accesses must be
performed, the first to access the odd byte at the first
word address on 08-015, the second to access the
even byte at the next sequential word address on 0007. For example, in Figure 9, byte 0 and byte, I can be
individually accessed in two separate bus cycles to byte
addresses 0 and I at word address O. They may also be
accessed together in a single bus cycle to word address
O. However, if a word access is made to address I, two
bus cycles will be required, the first to aCcess byte 1 at
word address 0 (note byte 0 will not be accessed), and
the second to access byte 2 at word address 2 (note byte
3 will not be accessed). This is why all word data
should ·be located at even addresses to maximize processor performance.
5-8
AP-186
80188 SIGNAL
DO-
D8·
D1S
data is being written from the processor, and is low
whenever data is being read into the processor. Unlike
the DEN signal, it may be directly connected to bus
buffers, since this signal does not usually enable the
output drivers of the buffer. An example data bus sub·
system supporting both buffered and unbuffered devices is shown in Figure 10. Note that the A side of the
buffer is connected to the 80186, the B side to the external device. The DT;R signal can directly drive the T
(transmit) signal of a typical buffer since it has the correct polarity.
CONNECTIONS
D7
210973-8
Figure 9. Physical Memory Byte/Word
Addressing In the 80186
3.1.6 CONTROL SIGNALS
The 80186 directl~vides the control signals RD,
WR, LOCK and TEST. In addition, the 80186 provides the status signals SO-S2 and S6 from which all
other required bus control signals can be generated.
If data buffers are required, the 80186 provides DEN
(Data ENable) and DT;R (Data TransmitIReceive)
signals to simplify buffer interfacing. The DEN and
DT;R signals are activated during all bus cycles.
The DEN signal is driven low whenever the processor
is either ready to receive data (during a read) or when
the processor is ready to send data (during a write). In
other words, DEN is low during any active bus cycle
when address information is not being generated on the
address/data pins. In most systems, the DEN signal
should not be directly connected to the OE input of
buffers, since unbuffered devices (or other buffers) may
be directly connected to the processor's address/data
pins. If DEN were directly connected to several buffers,
contention would occur during read cycles, as many
devices attempt to drive the processor bus. Rather, it
should be a factor (along with the chip selects for buffered devices) in generating the output enable.
3.1.6.1 RD and WR
The RD and WR signals strobe data to or from memory or I/O space. The RD signal is driven low at the
beginning of T 2, and is driven high at the beginning of
Ii..during all memory and I/O reads (see Figure 11).
RD will not'become active until the 80186 has ceased
driving address information on the address/data bus.
Data is sampled into the processor at the beginning of
T4. RD will not go inactive until the processor's data
hold time has been satisfied.
The DT;R signal' determines the direction of data
through the bi·directional buffers. It is high whenever
80181 SIGNALS
ADa·D1S
DEN
m:
8
A
~
B
OE
J
,L 8
Dl-D15
,--.. T
BUFFER
ADO·AD7
/8
BUFFERED
DATA
BUS
A
Oi!
B
,
/1
0.07
T
BUFFER
DT/R
/8
"/1
,
UNBUFFERED
DATA
BUS
}
Figure 10. Example 80186 Buffered/Unbuffered Data Bus
5-9
210973-9
inter
AP-186
Note that the 80186 does not provide separate I/O and
memory RD signals. If separate I/O read and memory
read signals are required, they can be synthesized using
the 82 signal'(which is low for all I/O ~ations and
high for all memory operations) and the RD signal (see
Figure 12). It should be noted that if this approach is
used, the 82 signal will require latching, since the 82
signal (like 80 and 81) goes to an inactive state well
before the beginning ofT4 (where RD goes inactive). If
82 was directly used for this purpose, the type of read
command (I/O or meinory) could change just before
T 4 as 82 goes to the inactive state (high). The status
.signals may be latched using ALE the same as the address signals (often using 'the sPare bits in the address
latches).
Often the lack of a separate I/O and memory RD signal is not important in ~ 80186 system. Each 80186
chip select signal
respond to accesses exclusively in
memory or I/O space. Thus, when a chip select is used,
the external device is enabled only during accesses to
the proper address in the proper space.
will
The WR signal is also driven low at the beginning ofT2
and driven high at the be~ing ofT4 (see Figure 13).
In similar fashion to the RD signal, the WR signal is
active for all memory and I/O writes. Again, separate
memory and I/O control lineS may be generated using
the latched 82 signal along with WR. More im~ant,
however, is the role of the active-going edge of WR. At
the time WR makes its high-to-Iow transition, valid
write data is not present on the data bus. This has consequences when using WR to enable such devices as
DRAMs since those devices require the data to be stable on the falling edge. In DRAM applications, the
problem is solved by the DRAM controller (an Intel
8207, for example).' For other applications which require valid data before the WR transition, place crosscoupled NAND gates between the CPU and the device
on the WR line (see Figure 14). The added gates delay
the active-going edge of WR to the device by one clock
phase, at which time valid data is driven on the bus by
the 80186.
210973-10
NOTES:
1. teLAZ: Clock low until address float
2. telRl: Clock low until RD active
3. tAZRL: Address float until RD active
4. tOVCl: Data vaiid until clock low (data input set-up time)
5. teLDX: Clock low unitl data invalid (data input hold time from clock)
6. tCLRH: Clock low until RD high
.
7. tRHAV: RD high until addresses valid
Figure 11. Read Cycle TimiQg of the 80186
LATCH
!&..READ
ALE
~-------------------~
:
•
. '
Although the amount of bus utilization will vary considerably from one program to another, a typical instruction mix on the 80186 will require greater bus utilization than the 8086. The 80186 executes most instructions in fewer clock cycles, thus requiring instructions from the queue at a faster rate. This also means
that the effect of wait states is more pronounced in an
80186 system than in an 8086 system. In all but a few
cases, however, the performance degradation incurred
by adding a wait state is less than might be expected
because instruction fetching and execution are performed by separate units.
3.2
Bus cycles occur sequentially, but do not necessarily
,come immediately one after another, that is the bus
may remain idle for several T states (TV between each
bus access initiated by the 80186. The reader should
recall that a separate unit, the bus interface unit, fetches
opcodes from memory, while the execution unit actually executes the pre-fetched instructions. The number of
clock cycles required to execute an 80186 instruction
vary from 2 clock cycles for a register to register move
to 67 clock cycles for an integer divide.
~
If a program contains many long instructions, program
execution will be CPU limited, that is, the instruction
queue will be constantly filled. Thus, the execution unit
does not need to wait for an instruction to be fetched. If
a program contains mainly short instructions (for example, data move instructions), the execution will be
. bus limited. Here, the execution unit will have to wait
often for an instruction to be fetched before it continues. Programs illustrating this effect and performance
degradation of each with the addition of wait states are
given in appendix G.
~xample
Memory Systems
3.2.1 2764 INTERFACE
With the above knowledge of the 80186 bus, various
memory interfaces may be generated. One of the simplest is the example EPROM interface shown in Figure
20.
:
~
.~
:
~
CLOCK~CD
~
. "
OUT_
BHOY
CD
MCSl
MeSO
]
8203
".J
SEL WR
AD·'
Al', WE
'SO
SACKJiU
17
A17-Al
AROY
J
r=u220
220
UPPER
BYTE\¥!
LOWER
BYTE\¥!
r--
I
r - - - XACK~
iftj
f
, 1)10.15
000-15
ADO·A015
:/
--
-
ORAlia
LATCH
DOD-7
O!
010-7
STS
-
......
LATCH
DOD-7
DE
010-7
STB
210973-26
,Figure 21. Example 8203/DRAM/80186 Interface
Since the 8203 is operating asynchronously to the
80186, the RDY output of the 8203 must be synchro·
nized to the 80186. The 80186 ARDY line provides the
necessary ready synchronization. The 8203 ready outputs operate in a normally not ready mode, that is, they
are only driven active when an 8203 cycle is being executed, and a refresh cycle is not being run. The 8203
SACK is presented to the 80186 only when the DRAM
is being accessed. Notice that the SACK output of the
8203 is used, rather than XACK. Shtce the 80186 will
insert at least one full CPU clock cycle between the
time RDY is sampled active and the time data mu~t be
present on the data bus, the XACK signal wonld insert
unnecessary additional wait states, since it does not indicate ready until valid data is available from the, ~em
ory.
DRAM refresh circuitry. In addition, it synchronizes
and arbitrates memory requests from two different
ports (e.g., an 80186 and a Multibus), allowing the two
ports to share memory. Finally, the 8207 provides a
simple interface to the 8206 error detection and correetion chip.
3.2.3 8207 DRAM INTERFACE
The simplest 8207 (and also the highest performance)
interface is shown in Figure 23. This shows the 80186
connected to an 8207 using the 8207 slow cycle, synchronous status interface. In this mode, the 8207 decodes the cycle to be run directly from the status lines
of the 80186. In ~dition, since the 8207 CLOCKIN is
driven by the CLKOUT ofthe 80186, any performance
degradation caused by required memory request synchronization between the 80186 and the 8207 is hot
present. Finally, the entire memory array driven by the
8207 may be selected using one or a group of the 801~6
memory chip selects, as in the 8203 interface above.
The 8207 advanced dual-port DRAM controller provides a high performance DRAM memory interface
specifically for 80186 microcomputer systems. This
controller provides all address multiplexing and
The 8207 AACK signal generates a synchronous ready
signal to the 80186 in the above interface. Since dynamic memory periodicll;lly requires refreshing, 80186 ac-
5-18
intJ
Ap·186
T,
186 ---i-~~
RD
8203 _ _ _ _ _ _ _~:__-,
RAS
8203
CAS
- - - i - - - - - ' i - - - - '......-;-,
RAM "",mm~mm~mm~mm~~~~~~~~~---t--~----__
DAn ~~~~~~~~~~~~~~~~~r--+~------LATCH ~mm~mm~mm~mm~~~~~~mm*"~~rr-~------
DAn
....+-........___
~~~~uw~~~uw~~~uw~~~~~
210973-27
NOTES:
1. tCLEL: Clock low until read low max
2. tCR: Command active until RAS max
3. tCC: Command active until CAS max
4. tCAC: Access time from CAS max
5. tISOU: Input to output delay max
6. tOVCL: Data valid to clock low (data in set up) min
Total Access Time = teLEL + tec + teAC + tlSOU
CD & ® are 80186 specs
® & @ are 8203 specs
@
is a DRAM spec
® is address latch spec
+ tOVCL
Figure 22. Example 8203 Access Time Calculation
801
care must be taken in design of the ready circuit such
that only one of the RDY lines is driven active. at a time
to prevent premature termination of the bus cycle.
7
CLKOUT
1-----.1
so
CLK
511-----.' iW
S2
+5
WR
3.3 HOLD/HLDA Interface
PCTC
PCTL
The 80186 employs a HOLD/HLDA bus exchange
protocol. This protocol allows other asynchronous bus
masters (i.e., ones which drive address, data, and control information on the bus) to gain control of the bus.
LMCS 1------.1
SRDY
3.3.1 HOLD RESPONSE
210973-28
Figure 23. 80186/8207/DRAM Interface
cess cycles may occur simultaneously with an 8207 generated refresh cycle. When this occurs, the 8207 will
hold the AACK line high until the processor initiated
access is run (note, the sense ofthis line is reversed with
respect to the 80186 SRDY input). This signal should
be factored with the DRAM (8207) select input and
used to drive the SRDY line of the 80186. Remember
that either SRDY and ARDY needs to be active for a·
bus cycle to be terminated. If asynchronous devices
(e.g., a Multibus interface) are connected to the ARDY
line with the 8207 connected to the SRDY line,
In the HOLD/HLDA protocol, a device requiring bus
control (e.g., an external DMA device) raises the
. HOLD line. In response to this HOLD request, the
80186 will raise its HLDA line after it has finished its
current bus activity. Wh~n the external device is fmished with the bus, it drops its bus HOLD request. The
80186 responds by dropping its HLDA line and resuming bus operation.
When the 80186 recognizes a bus hold by driving
HLDA high, it will float many of its signals (see Figure
24). ADO-AD1S and DEN are floated within
5-19
AP-186
tCLAZ after the same clock edge that HJd)A is driven
active. AI6-AI9, RD, WR, BHE, DT/R, and SO-S2
are floated within tCHCZ after the clock edge immediately before the clock edge on which HLDA comes
active.
T,
T,
HOLD
T,
ClOCK
T,
OUT
HLDA
----......;,,-------------1
HLDA
AD15-ADO
~
____~-+----J
~~--:'f-....:;:FL~O:::Ii.~:r__'f-___
DTlJf,Sii-ti, ____.;-.__J
Il6
NOTES:
1. tHVCL: Hold valid until clock low
2. tCLHAV: Clock low until HLDA active
----i--;f-'-~..."\.-..;FL=O~AT:...._;_---
+--+....
Im,WR,1HE,
210973-30
----.;-.---++-i-'
11.18-11.19, ___
I
I
I
I
~ ----~----~~~----~-----
Figure 25. 80186 Idle Bus Hold/HLDA Timing
the second signals the internal circuitry to initiate a bus
hold (see Figure 25).
.::
210973-29
Figure 24. Signal Float/HLDA
Timing of the 80186
Only the above mentioned signals are floated during
bus HOLD. Of the signals not floated by the 80186,
some have to do with peripheral functionality (e.g.,
TMR OUT). Many others either directly or indirectly
control bus devices. These signals are ALE and all the
chip select lines (UCS, LCS, MCSO-3, and PCSO-6).
3.3.2 HOLD/HLDA TIMING AND BUS LATENCY
The time required between HOLD going active and the
80186 driving HLDA active is known as bus latency.
Many factors affect bus latency, including synchronization delays, bus cycle times, locked transfer times and
interrupt acknowledge cycles.
The HOLD request line is internally synchronized by
the 80186, and may therefore be an asynchronous inc
put. To guarantee recognition on a particular clock
edge, it must satisfy setup and hold times to the falling
edge of the CPU clock. A full CPU clock cycle is required for synchronization (see Appendix B). If the bus
is idle, HLDA will follow HOLD by two CPU clock
cycles plus a small amount of setup and propagation
delay time. The first clock cyCle synchronizes the input;
Many factors influence the number of clock cycles between a HOLD request and a HLDA. These make bus
latency longer than the best case shown above. Perhaps
the most important factor is that the 80186 will not
relinquish the local bus until the bus is idle. The bus
can become idle only at the end of a bus cycle. The
80186 will normally insert no Tj states between T4 and
T 1 of the next bus cycle if it requires any bus activity
(e.g., instruction fetches or I/O reads). However, the
80186 may not have an immediate need for the bus
after a bus cycle, and will insert Tj states independent
of the HOLD input (see Section 3.1.1).
When the HOLD request is active, the 80186 will be
forced to proceed from T4 to Tj in order that the bus
may be relinquished. HOLD must go active 3 T-states
before the end of a bus cycle to force the 80186 to insert
idle T -states after T 4 (one to synchronize the request,
and one to signal the 80186 that T4 of the bus cycle will
be followed by idle T-states, see section 3.1.1). After the
bus cycle has ended, the bus hold will be immediately
acknowledged. If, however, the 80186 has already determined that an idle T-state will follow T4 of the current bus cycle, HOLD need go active only 2 T-states
before the end of a bus cycle to force the 80186 to
relinquish the bus. This is' because the external HOLD
request is not required to force the generation of idle
T-states. Figure 26 graphically portrays the scenarios
depicted above.
5-20
AP-186
T,OR
Tw
:'
T,
T,
CLOCK
OUT
HOLD
HLDA
210973-31
NOTES:
1. Decision: No additional internal bus cycles required, idle T-states will be inserted after T4
.
2. Greater than tHVCL
3. LessthantCLHAV
4. HOLD request internally synchronized
T.OR
:
Tw
:
T.
:
T1
CLOCK~l
I
I
I
,
OUT
,
HLDA
210973-32
NOTES:
1. Decision: Additional internal bus cycles required, no idle T-states will be inserted, HOLD not active soon enough to
force idle T-states
2. Greater than tl-\VCL: not required since it will not get recognized anyway
3. HOLD request Internally synchronized
T,O'
Tw
T.
T,
CLOCK
OUT
HOLD
HLDA ______________________________________________________- J
210973-33
NOTES:
1. HOLD request internally synchronized
2. Decision: HOLD request active, idle t-states will be inserted at end of current bus cycle
3. Greater than tHVCL
4. Less than tCLHAV
Figure 26_ HOLD/HLDA Timing In the 80186
An external HOLD has higher priority than both the
80186 CPU or integrated DMA unit. However, an external HOLD will not separate the two cycles needed to
perform a word access when the word accessed is located at an odd location (see Section 3.1.3). In addition, an
external HOLD will not separate the two-to-four bus
cycles required for the integrated DMA unit to perform
a transfer. Each of these factors will add to the bus
latency of the 80186.
80186 will not recognize external HOLDs (nor will it
recognize internal DMA bus requests). Locked transfers are programmed by preceding an instruction with
the LOCK prefix. String instructions may be locked.
Since string transfers may require thousands of bus cycles, bus latency time will suffer if they are locked.
The final factor affecting bus latency time is interrupt
acknowledge cycles. When an external interrupt controller is used, or if the integrated interrupt controller is
used in Slave mode (see Section 4.4.1) the 80186 will
run two interrupt acknowledge cycles back to back.
Another factor influencing bus latency time is locked
transfers. Whenever a locked transfer is occurring, the
5-21
inter
AP-186
tion 3.1.1). If'there are no bus cycles to be run by the
CPU, it will continue to float all lines until the last Ti
before it begins its first bus cycle after the HOLD.
These cycles are automatically "locked" and will never
be separated by bus HOLD. See Section 6.5 on interrupt acknowledge timing for more information concerning interrupt acknowledge timing.
A special mechanism exists on the 8OC186/80C188 to
provide for DRAM refreshing while the bus is in
HOLD. If the refresh control unit issues a request to
the integrated bus controller while HOLD is in effect,
the processor lowers HLDA. It is the responsibility of
the external bus master to release the bus by deasserting
HOLD so that the refresh cycle can take place (see
Figure 28). The external master can then reassume control of the bus subject to the usual requirements placed
on the HOLD input.
3•3•3 COMING OUT OF HOLD
°
When the HOLD input goes inactive, the processor
lowers its HLDA line in a single clock as shown in
Figure 27. If there is pending bus activity, only two ri
states will be inserted after HLDA goes inactive and
status information will go active during the last idle
state concerning the bus cycle about to be run (see Sec-
-
T,
T,
T.
HOLD --~
HLDA ----.l----~"\
ADO-AD15
DEN
--~~--~--;---t~;-l--
A18/53-A19/S8
iiD.WIi.BHE
-----+----!----+-~~r!----
DT/ii.ilii·li2
210973-34
NOTES:
1. HOLD internally synchronized
2. Greater than THVCL
3. Less than TCLHAV
4. Lines come out of float only if a bus cycle is pending
Figure 27. 80186 Coming out of Hold
=t3
TlI"ITI
CL:::
HLDA
ADD-AD15,
UER
A16IS3-A19JS6,
DT/R,SO-s2
1
CD
I
:
~
11
I
n
T4
T1
@
~~--~+LLL~~~~+W~
I
II--+------I---~>--+---+f'---
I
I
I
I
I
I
I
I Il---r----+---~_1--~
I
I Il __--+-__~-_+-'"0,*copy down previous level
trame',
BP:::: BP - 2; /"pointers*,
PUSH [BP];
BP:=templ;
PUSH BP;
,'put current level trame
pointer',
,'in the save area',
SP:=SP - disp;
,'create space on the
tor',
,'local variables',
5-78
stack
intJ
AP-186
Figure H-l shows the layout of the stack before and
after this operation.
This instruction requires two operands: the first value
(disp) specifies the number of bytes the local variables
of this routine require. This is an unsigned value and
can be as large as 65535. The second value (level) is an
unsigned value which specifies the level of the procedure. It can be as great as 255.
The' 80186 includes the LEAVE instruction to tear
down stack frames built up by the ENTER instruction.
As can be seen from the layout of the stack left by the
ENTER instruction, this involves only moving the contents of the BP register to the SP register, and popping
the old BP value from the stack.
Neither the ENTER nor the LEAVE instructions save
any of the 80186 general purpose registers. If they must
be saved, this must be done in addition to the ENTER
and the LEAVE. In addition, the LEAVE instruction
does not perform a return from a subroutine. If this is
desired, the LEAVE instruction must be explicitly followed by the RET instruction.
?
BP
~
AFTER
BEFORI:
sP-----~----------------~
BP___
OLDBP
-
1------1
OLD FRAME
PTAS.
CURRE~FRAME
SP---
_
LOCAL
VARIABLE
AREA
210973-99
Figure H-1. ENTER Instruction Stack Frame.
5-79
intJ
Ap·186
APPENDIX I
80186/80188 DIFF.ERENCES
The 80188 is exactly like the 80186, except it has an 8
bit external bus. It shares the same execution unit, timers, peripheral control block, interrupt controller, chip
select, and DMA logic. The differences between the
two caused by ,the narrower data bus are:
• The 80188 has a 4 byte prefetch queue, rather than
the 6 byte prefetch queue present on the 80186. The
reason for this is since the 80188 fetches opcodes
one byte at a time, the number of bus cycles required to fill the smaller queue of the 80188 is actually greater than the number of bus cycles required
to fill the queue of the 80186. As a result, a smaller
queue is required to prevent an inordinate number
of bus cycles being wasted by prefetching opcodes to
be discarded during a jump.
• AD8-AD15 on the 80186 are transformed to A8A15 on the 80188. Valid address information is
present on these lines throughout the bus cycle of
the 80188. Valid address information is not guaranteed on these lines during idle T states.
• BHE/S7 is always defined HIGH by the 80188,
since the upper half of the data bus is non-existent.
• The DMA controller of the 80188 only performs
byte transfers. The B/W bit in the DMA control
word is ignored.
• Execution times for many memory access instructions are increased because the memory access must
be funnelled through a narrower data bus. The
80188 also will be more bus limited than the 80186
(that is, the execution unit will be required to wait
for the opcode information to be fetched more often)
because the data bus is narrower. The execution
time within the processor, however, has not changed
between the 80186 and 80188.
Another important point is that the 80188 internally is
a 16-bit machine. This means that any access to the
integrated peripheral registers of the 80188 will be done
in 16-bit chunks, not in 8-bit chunks. All internal peripheral registers are still 16-bits wide, and only a single
read or write is required to access the registers. When a
word access is made to the internal registers, the BIU
will run two bus cycles externally.
Access to the control block may also be done with byte
operations. Internally the ful116-bits of the AX register
will be written, while externally, only one bus cycle will
be executed.
·5-80
inter
AP-186
APPENDIX J
80186/80C186 DIFFERENCES
There are two operating modes of the 80CI86 and
80C188: Compatible Mode and Enhanced Mode. In
Compatible Mode, the 80CI86 will function identically
to the 80186 with the following noted exceptions:
I) All non-initialized registers in the peripheral control
block will reset to a random value on power-up on
the 80C186. Non-Initialized registers consist of those
registers which are not used for control, i.e., address
pointers, max count, etc. For compatibility, all registers should be programmed before being used on existing 80186 applications as well as on new 80C 186
applications.
2) The ET (Esc/Trap) bit in the relocation register has
no effect in Compatible Mode. If an escape opcode is
executed, the 80CI86 will always trap to an interrupt vector type 7. The 80C186 does not support any
numerics operations when in Compatible Mode.
In Enhanced Mode, the 80CI86 provides additional
features not found on the 80186. There are newly defined registers to support these new features, and three
of the output pins of the 80CI86 change functionality.
The new registers and pin descriptions are covered in
Section 9.0.
The 80CI88 in Enhanced Mode functions similarly to
the 80C 186 except for numerics operation. It is not possible to interface a numerics coprocessor with the
80C188. Therefore, none of the MCS pins change functionality when invoking Enchanced Mode on the
80C188. Further, any attempted execution of an escape
opcode will result in a trap to interrupt vector type 7.
5-81
AP-186
APPENDIX K
DRAM ADDRESSING CONFIGURATIONS
FOR THE 80C186/80C188
80C186 DESIGNS
64Kx 1
16Kx4
256Kx 1
64Kx4
1M x 1
256Kx4
Row Address
(AO-AX)
Column Address
(AO-AX)
A1-AB
A1-AB
A1-A9
A1-AB
A1-A10
A1-A9
A9-A16
A9-A14
A10-A1B
A9-A16
A11-A19(+ Bank)
A10-A1B
(12BK Bytes)
(32K Bytes)
(512K Bytes)
(12BK Bytes)
(2M Bytes)
(512K Bytes)
80C188 DESIGNS
NOTE:
Address bit AO can be used in either RAS or CAS addresses, so long
as it is not included in any refresh address bits.
Row Address
(AO-AX)
64Kx 1
16Kx4
256Kx 1
64Kx4
1Mx 1
256Kx4
(64K Bytes)
(16K Bytes)
(256K Bytes)
(64K Bytes)
(1 M !3ytes)
(256K Bytes)
RAM Type
64Kx 1
16Kx4
256Kx 1
64Kx4
1M x 1
256Kx4
A1-A7, AO
A1-A7,AO
A1-AB,AO
A1-AB
A1-A9, AO
A1-A9
Column Address
(AO .. AX)
AB-A15
A!3-A13
A9-A17
AO,A9-A15
A10-A19
AO, A10-A17 .
RASAdd
CAS Add
Refresh Add
AO-A7
AO-A7
AO-AB
AO-A7
AO-A9
AO-AB
AO-A7
AO-A5
AO-AB
AO-A7
AO-A9
AO-AB
AO-A6
AO-A6
AO-A7
AO-A7
AO-AB
AO-AB
5-B2
inter
APPLICATION
NOTE
AP-258
February 1986
High Speed Numerics with the
80186/80188 and 8087
STEVE FARRER
APPLICATIONS ENGINEER
© Intel Corporation, 1987
5-83
Order Number: 231590-001
Ap·258
three, and four contain an overview of the integrated
circuits involved in the numerics configuration. Section
five discusses the interfacing aspects between the
80186/8 and the 8087, including the role of the 82188
Integrated Bus Controller and the operation of the integrated peripherals on the 80186/8 with the 8087. Section six compares the advantages of using an 8087 Numeric Data Coprocessor over software routines written
for the host processor as well as the advantage of using
an 80186/8 numerics system over an 8086/8088 numerics system.
1.0 INTRODUCTION
From their introduction in 1982, the highly integrated
16-bit 80186 and its 8-bit external bus version, the
80188, have been ideal processor choices for high-performance, low-cost embedded· control applications. The
integrated peripheral functions and enhanced 8086
CPU of the 80186 and 80188 allow for an easy upgrade
of older generation control applications to achieve
higher performance while lowering the overall system
cost through reduced board space, and a simplified production flow.
Except where noted, all future references to the 80186
will apply equally to the 80188.
More and more controller applications need even higher performance in numerics, yet still require the lowcost and small form factor of the 80186 and 80188. The
8087 Numerics Data Coprocessor satisfies this need as
an optional add-on component.
2.0 OVERVIEW OF THE 80186
The 80186 and 80188 are highly integrated microprocessors which effectively combine up to 20 of the most
common system components onto a single chip. The
80186 and 80188 processors are designed to provide
both higher performance and a more highly integated
solution to the total system.
The 8087 Numeric Data Coprocessor is interfaced to
the 80186·and 80188 through the 82188 IBC (Integrated Bus Co1)troller). The IBC provides a highly integrated interface solution which replaces the 8288 used in
8086-8087 systems. The IBC incorporates all the necessary bus control for the 8087 while also providing the
necessary logic t? support the interface between the
80186/8 and the 8087.
Higher integration results from integrating system peripherals onto the microprocessor. The peripherals consist of a clock generator, an interrupt controller, a
DMA controller, a counter/timer unit; a programmable wait state generator, programmable chip selects,
and a bus controller. (See Figure 1.)
This application note discusses the design considerations associated with using the 8087 Numeric Data Coprocessor with the 80186 and 80188. S¢ctions two,
INT3/INTA1"
INT2JJRTU
ClKOUT Vee G~D
,-----I-ORoo
DRal
HOLD
"LDA
lIES
RESET
CONTROL
REGISTERS
231590-1
Figure 1.8018618 Block Diagram
5-84
AP-258
Higher performance results from enhancements to both
general and specific areas of the 8086 CPU, including
faster effective address calculation, improvement in the
execution speed of many instructions, and the inclusion
of new instructions which are designed to produce optimum 80186 code.
The 80186 and 80188 are completely object code compatible with the 8086 and 8088. They have the same
basic register set, memory organization, and addressing
modes. The differences between the 80186 and 80188
'are the same as the differences between the 8086 and
8088: the 80186 has a 16-bit architecture and 16-bit bus
interface; the 80188 has a 16-bit internal architecture
and an 8-bit data bus interface. The instruction execution times of the two processors differ accordingly: for
each non-immediate 16-bit data read/write instruction,
4 additional clock cycles are' required by the 80188.
more general tasks. It supports the necessary data types
and operations and allows use of all the current hardware and software support for the 8086/8 and 80186/8
microprocessors. The fact that the 8087 is a coprocessor means it is capable of operating in parallel with the
host CPU, which greatly improves the processing power of the system.
The 8087 can increase the performance of floatingpoint calculations by 50 to 100 times, providing the
performance and precision required for small business
and graphics applications as well as scientific data processing.
The 8087 numeric coprocessor adds 68 floating-point
instructions and eight 80-bit floating-point registers to
the basic 8086 programming architecture. All the numeric instructions and data types of the 8087 are used
by the programmer in the same manner as the general
data types and instructions of the host.
3.0 NUMERICS OVERVIEW
3.1 The Benefits of Numeric
Coprocessing
The 8086/8 and 80186/8 are general purpose microprocessors, designed for a very wide range of applications. Typically, these applications need fast, efficient
data movement and ,general purpose control instructions. Arithmetic on data values tends to be simple in
these applications. The 8086/8 and 80186/8 fulfill these
needs in a low cost, effective manner.
However, some applications require extremely fast and
complex math functions which are not provided by a
general purpose processor. Such functions as square
root, sine, cosine, and logarithms are not directly available in a general purpose processor. Software routines
required to implement these functions tend to be slow
and not very accurate. Integer data types and their
arithmetic operations (i.e., add, subtract, multiply and
divide) which are directly available on general purpose
processors, still may not meet the needs for accuracy,
.
speed and ease of use.
Providing fast, accurate, complex math can be quite
complicated, requiring large areas of silicon on integrated circuits. A general data processor does not provide these features due to the extra cost burden that less
complex general applications must take on. For such
features, a special numeric data processor is required one which is easy to use and has a high level of support
in hardware and software.
-
3.2 Introduction to the 8087
The 8087 is a numeric data coprocessor which is capable of performing complex mathematical functions
while the host processor (i.e. the main CPU) performs
The numeric data formats and arithmetic operations
provided by the 8087 support the proposed IEEE Microprocessor Floating Point Standard. All of the proposed IEEE floating point standard algorithms, exception detection, exception handling, infinity arithmetic
and rounding controls are implemented. The IEEE
standard makes it easier to use floating point and helps
to avoid common problems that are inherent to floating
point.
3.3 Escape Instructions
The coprocessing capabilities of the 8087 are achieved
by monitoring the local bus of the host processor. Certain instructions within the 8086 assembly language
known as ESCAPE instructions are defined to be coprocessor instructions and" as such, are treated differently.
The coprocessor monitors program execution of the
host processor to detect the occurrence of an ESCAPE
instruction, The fetching of instructions is monitored
via the data bus and bus cycle status S2-S0, while the
execution of instructions is monitored via the queue
'
status lines QSO and QS 1.
All ESCAPE instructions start with the high-order 5bits of the instruction opcode being 11011. They have
two basic forms, the memory ,reference form and the
non-memory reference form. The non-memory form,
shown in Figure 2A, initiates some activity in the coprocessor using the nine available bits of the ESCAPE
i1istruction to indicate which function- to perform.
Memory referen'ce forms of the ESCAPE instruction,
shown in Figure 2B, allow the host to point outa memory operand to the coprocessor using any host memory
5-85
intJ
AP-258
115 114 113 112 111 110
1st byte
19
Ie
17
16
15
14 13 12
2nd byte
11
10
Figure 2A. Non-Memory Reference ESCAPE Instructions
addressing mode. Six bits are available in the memory
reference form to identify what to do with the memory
operand.
3.5 Coprocessor Response to Escape
Instructions
The 8087 performs basically three types of functions
when encountering an ESCAPE instruction: LOAD
(read from memory), STORE (write to memory), and
EXECUTE (perform one of the internal 8087 math
functions).
.
Memory reference forms of ESCAPE instructions are
identifieq by bits 7 and 6 of the byte following the ESCAPE opcode. These two bits are the MOD field of the
8086/8 or 80186/8 effective address calculation byte.
Together with the RIM field (bits 2 through 0), they
determine the addressing mode and how many subsequent bytes remain in the instruction.
When the host executes a memory reference ESCAPE
instruction intended to cause a read operation by the
8087, the host always reads the low-order word of any
8087 memory operand. The 8087 will save the address
and data read. To read any subsequent words of the
operand, the 8087 must become a local bus,master.
3.4 Host Response to Escape
Instructions
When the 8087 has the local bus, it increments the 20bit physical address it saved to address the remaining
words of the operand.
The host performs one of two possible actions when
encountering an ESCAPE instruction: do nothing (operation is internal to 8087) or calculate an effective address and read a word value beginning at that address
(required for all LOADS and STORES). The host ignores the value of the word read and hence the cycle is
referred to as a "Dummy Read Cycle." ESCAPE instructions do not change any registers in the host other
than advancing the IP. If there is no coprocessor or the
coprocessor ignores the ESCAPE instruction, the ESCAPE instruction is effectively a NOP to the host. Other than calculating a memory address and reading a
word of memory, the host makes no other assumptions
regarding coprocessor activity.
When the ESCAPE instruction is intended to cause a
write operation by the 8087, the 8087 will sa'le the address but ignore the data read. Eventually, it will get
control of the local bus and perform successive writes
incrementing the 20-bit address after each word until
the entire numeric variable has been written.
ESCAPE instructions intended to cause the execution
of a coprocessor calculation do not require any bus activity. Numeric calculations work off of an internal register stack which has been initialized using a LOAD
operation. The calculation takes place using one or two
of the stack positions specified by the ESCAPE instruction. The result of the operation is also placed in one of
the stack positions specified by the ESCAPE instruction. The result may then be returned to memory using
a STORE instruction, thus allowing the host processor
to access it.
The memory reference ESCAPE instructions have two
purposes: to identify a memory operand and, for certain
instructions, to transfer a word from memory to the
coprocessor.
MOD
RIM
10 I 0 I
115114113112111110 19
Is
17 16
MOD
11 11 10
15
14
13
12
II
I
11 10
I
I
11 11 10 11 11
I
10 1 d
I I I .
115 114 113 112 111 110 19
Is
17 16
MOD
10 I 0 I
RIM
15
14
13
12
II I I
I
I I I I
11 10 D15D14D13D12DllDl0 Dg De D7 D6 D5 D4 D3 D2 D1'Do
RIM
16-bit displacement
11 11 10 11 11
MOD
16-bit direct displacement
11
I I
I
II
B·bit displacement
I I I I I
10 D7 D6 D5 D4 D3 D2 Dl Do
RIM
I I
I
I
I
Figure 2B. Memory Reference ESCAPE Instruction Forms
5-86
inter
Ap·258
4.0 OVERVIEW OF THE 82188
INTEGRATED BUS CONTROLLER
ing when other bus masters supply their own bus control signals.
4.1 Introduction
4.3 Bus Arbitration
The 82188 Integrated Bus Controller (IBC) is a highly
integrated version of the 8288 Bus Controller. The IBC
provides command and control timing signals for bus
control and all of the necessary logic to interface the
80186 to the 8087.
The IBC also has the ability to convert bus arbitration
protocols ofRQ/GT to HOLD-HLDA. This allows the
82586 Local Area Network (LAN) Coprocessor, the
82730 Text Coprocessor, and other coprocessors using
the HOLD-HLDA protocol to be interfaced to the
8086/8 as well as allowing the 80186/8 to be interfaced
to the 8087. In addition to cOllverting arbitration protocols, the IBC makes it possible to arbitrate between two
bus masters using HOLD-HLDA with a third using
RQ/GT.
4.2 Bus Control Signals
The bus command and control signals consist of RD,
WR, DEN, DTIR, and ALE. The timings and levels
are driven following the latching of valid signals on the
status lines 80-82. When 80-82 change state from passive to active, the IBC begins cycling through a state
machine which drives the corresponding control and
command lines for the bus cycle. As with the 8288, an
address enable input (AEN) is present to allow tri-stat-
4.4 Interface Logic
In addition to all the bus control and arbitration features, the IBC provides logic to connect the queue
status to the 8087, a chip-select for the 8087, and the
necessary READY synchronization required between
the 8087 and the 80186/8.
5.0 DESIGNING THE SYSTEM
5.1 Circuit Schematics of the 80186/8-82888-8087 System
TO OPTIONAL
THIRD BUS MASTER
+
I
~0186
16MH
r::
...
SYS
SYS
HOLD HLDA
%~
-f
ADDRESS DATA BUS
HLDA
HOLD
MCSO
ARDY
Rii
HLDA
HOLD
CSIN
OSO
OSOI
OSl
OS1I
ALE
Sir--
52
sof-
BUSY
' - - INT
50-
r::
Si52 -----
CLK
RESET
ROY
OSO
OSl
8087-1
i-+STB
r-v'
so
CLK
RESET
SRO
74LS
373
"1:C:!.
=I
ADDRESS
=I
DATA
82188
DT/R
DEN
OSOO
OSlO
= rL...J,.,
~1Diil
r-v'
RQ/GTO
RO/GTl
iffi/GTO
iffi/GTl
-
L...J,.,
Sl
f-
COMMAND/CONTROL
-
SRDY
RESETOUT
CLOCKOUT
S2r---INTO
TEST
JI--
'\r
.'f'
.1'.
J.DY
S~DY
iiE
74LS
24S
~
ADDRESS DATA BUS
Figure 3. 80186/8-82188-8087 Circuit Diagram
5-87
231590-2
inter
Ap·258
Table 1. Queue Status Decoding
5.2 Queue Status
The 8087 tracks the instruction execution of the 80186
by keeping an internal instruction queue which is identical to the processor's instruction queue. Each time the
processor performs an instruction fetch, the 8087 latches the instruction into its own queue in parallel with the
processor. Each time the processor removes the first
byte of an instruction from the queue, the 8087 removes
the byte at the top of the 8087 queue and checks to see
if the byte is an ESCAPE prefix. If. it is, the 8087 decodes the following bytes in parallel with the processor
to determine which numeric instruction the bytes represent. If the first byte of the instruction is not an ESCAPE prefix, the 8087 discards it along with the subsequent bytes ofthe non-numeric instruction as the 80186
removes them from the queue for execution.
QS1
QSO
0
0
1
0
1
0
1
1
Queue Operation
No queue operation
First byte from queue
Subsequent byte from queue .
Reserved
Each time the 80186 begins decoding a new instruction,
the queue status lines indicate "first byte of instruction
taken from the queue". This signals the 8087 to check
, for an ESCAPE prefix. As the remaining bytes of the
instruction are removed, the queue status indicates
"subsequent byte removed from queue". The 8087 uses
this status to either continue decoding subsequent
bytes, if the first byte was an ESCAPE prefix, or to
discard the subsequent bytes if the first byte was not an
ESCAPE prefix.
The 8087 operates its internal instruction queue by
monitoring the two queue status lines from the CPU.
This status information is made available by the CPU
by placing it into queue status mode. This requires
strapping the RD pin on the 80186~ound. When
RD is tied to ground, ALE and WR become QSO
(Queue Status #0) and QSl (Queue Status # 1) respectively.
The QSO(ALE) and QSl(WR) pins of the 80186 are fed
directly to the 82188 where they are latched and delayed by one-half-clock. The delayed queue status from
the 82188 is then presented directly to the 8087.
The waveforms of the queue status signals are shown in
Figure 4. The critical timings are the setup time into
the 82188 from the 80186 and the setup and hold time
into the 8087 from the 82188. The calculations for an 8
MHz system are as follows:
.5TcLCL - TCHQSV (186 max)
.5(125 ns) - 35
;;::: TQIVCL (82188 min)
;;::: 15 ns
;setup to 82188
TCLCL - TCLQOV (82188 max)
(125 ns) - 50
;;::: TQVCL
;setup to 8087
;;:::10 ns
TCLQOV (82188 min)
5
;;::: TCLQX (8087 min)
;;::: 5 ns
elK - - \ . " "_ _ _
-¥ .
:J TCHQSV t
80186 QUEUE STATUS
INTO 82188
----------3
;hold to 8087
\
I
-I
:J TCHQSV t
I
Y
r
r
§
''11110---;.------
fQlVclSi
_ _ _ _ L~_C_lQ_O_V
_ _ _ _ __!-"'" TClQOV
_____________
82188 QUEUE STATUS
Z
INTO 8087 _ _ _ _ _ _ _ _ _ _ _ _ _ _.,...,
. c:=
~-------I_...J
TQVCL
•
TClQX
231590-3
Figure 4. Queue Status Timing
5-88
inter
AP-258
NOTE:
The hold time calculation is the same for both the
80186 and 8087.
5.3 Bus Control Signals
When the 80186 is in Queue Status mode, another component must generate the ALE, RD, and WR signals.
The 82188 provides these2ignals by monitorin~
CPU bus cycle status (SO-S2). Also provided are DEN
and DT/R: which may be used for extra drive capability
on the control bus. With the exception of ALE, all control signals on the 82188 are almost identical to their
corresponding 80186 control signals. This section discusses the differences between the 80186 and the 82188
control signals for the purpose of upgrading an 80186
design to an 80186-8087 design. For original 801868087 designs, there is no need to compare control signal
timings of the 82188 with the 80186.
These timings provide adequate setup and hold times
for a 74LS373 address latch.
T1
eLK
ALE
--1
ADDRESS
~
_____
~ VALID I~
t:SETUP-t-HOLD
5.3.1 ALE
:I
231590-4
Figure 5. Address Latch Timings
The ALE (Address Latch Enable) signal goes active
one clock phase earlier on the 80186 than on the 82188.
Timing of the ALE signal on the 82188 is closer to that
of the 8086 and 8288 bus controller because the bus
cycle status is used to generate the ALE pulse. ALE on
the 80186 goes active before the bus cycle status lines
are valid.
The inactive edge of ALE occurs in the same clock
phase for both the 80186 and the 82188. The setup and
hold times of the 80186 address relative to the 82188
ALE signal are shown in Figure 5 and are calculated
for an 8 MHz system as follows:
Setup Time
For 80186 = TAVCH (186 min) + TCHLL (82188 min)
=10+0=lOns.
For 8087 = 0.5 (TCLCU - TCLAV (8087 max) + TCHLL (82188 min)
= 0.5 (125) - 55 + 0 = 7.5
Hold Time
= 0.5 (TCLCL) - TCHLL (82188 max) + TCLAZ (186 min)
= 0.5 (125) - 30 + 10 = 42.5 ns.
5-89
inter
AP-258
T3
T2
T1
T4
ClK
80186
Ro
82188----------------~~~
RD AND WR
80186
WR
231590-5
TCLRL = TCLML = TcVCTV = 10 to 70 ns
TCLRH = TCLMH = III to 55 ns
TCVCTX = 5 to 55 ns
" Figure 6. Read and Write Timings
5.3.2 Read ,and Write
5.3.4 DT/Fi
The read and write signals of the 82188 have identical
timings to those of the 80186 with one exception: the
82188 WR inactive edge may not go inactive quite as
early as the 80186. This spec is, in fact, a tighter spec
than the 80186 WR timing and should make designs
easier. The timings for RD and WR are shown in Figure 6 for both the 80186 and the 82188.
The operation of the DT;R signal varies somewhat between the 80186 and the 82188. The 80186 DT/R: signal will remain in an active high state for all write cyc1es~d will default to a high state when the ~stem bus
is idle (i.e., no bus activity). The 80186 DT/R goes low
only for read cycles and does so only for the duration of
the bus cycle. At the end of the read cycle, assuming
the following cycle is a non-read, the DT/R: signal will
default back to a high state. Back-to-back read cycles
will result in the DT/R: sign~ remaining low ~til the
end of the last read cycle.
5.3.3 DEN
The DEN signal on the 82188 is identical to the DEN
signal on the 80186 but with a tighter timing specification. This makes designs easier with the 82188 and
makes upgrades from 80186 bus control to 82188 bus
control more straightforward. The timings for DEN on
both the 80186 and 82188 are shown in J.<:igure 7.
The DT/R: signal on the 82188 operates differently by
making transitions only at the start of a bus cycle. The
82188 DT;R signal has no default state and therefore
will remain in whichever state the previous bus cycle
required. The 82188 DT/R signal will only change
states'when the current bus cyCle requires a state different from the previous bus cycle.
T2
T1
T3
T4 "
ClK
80186
DEN
82188 DEN
231590-6
TCVCTV =
TCVOEX =
TCHDNV =
TCHDNX =
10 to 70 - clock edge to DEN active/inactive
10 to 70 - falling edge of T4 to DEN inactive
10 to 55 - rising edge of clock to DEN active
10 to 55 - clock edge to DEN inactive
Figure 7. Data Control Timings
5-90
infef
AP-258
T4
T1
T2
T3
T4
ClK
80186DT/R:::::::~~~~~'~L-____________________________________~ll:::::::
I
(READ)
~
80186
DT/R _ _ _ _..l./
(WRITE)
I~~L=O~W
\.
'-_ _
______________________________________
82188 DT/R - - - - - - - - - - - - - " ' \
If"
READ/WRITE - - - - - - - - - '
f I o - - - - - - - - - - - - - - - - - - (READ)
TCLOW
=
0 10 55
(WRITE)
ns.
231590-7
Figure 8. Data Transmit & Receive Timings
5.4 Chip Selects
5.4_1 INTRODUCTION
Chip-select circuitry is typically accomplished by using
a discrete decoder to decode two or more of the upper
address lines. When a valid address appears on the address bus, the decoder generates a valid chip-select.
With this method, any bus master capable of placing an
address on the system bus is able to generate a chip-select. An example of this is shown in Figure 9 where an
8086/8087 system uses a common decoder on the address bus. Note the decoder is able to operate regardless
of which processor is in control of the bus.
With high integration processors like the 80186 and
80188, the chip-select decoder is integrated onto the
processor chip. The integrated chip-selects on the
80186 enable direct processor connection to the chipenable pins on many memory devices, thus eliminating
an external decoder. But because the integrated chip-selects decode the 80186's internal bus, an external bus
master, such as the 8087, is unable to activate them.
The 82188 IBC solves this problem by supplying a
chip-select mechanism which may be activated by both
the host processor and a second processor.
5.4.2 CSI AND CSO OF THE 82188
The CSI (chip select in) and CSO (chip select out) pins
of the 82188 provide a way for a second bus master to
select memory while also making use of the 80186 integrated chip-selects. The CSI pin of the 82188 connects
directly to one of the 80186's chip-selects while CSO
connects to the memory device designated for the chipselects range. An example of this is shown in Figure 10.
ADDRESS
DECODER
ADDRESS
231590-8
Figure 9. Typical 8086/8087 System
231590-9
Figure 10. Typical 80186/82188/8087 System
5-91
intJ
AP-258
When the 80186 has control ofthe bus, the circuit acts
just as a buffer and the memory device gets selected as
if the circuit had not been there. Whenever CSI goes
.active, CSO goes active. When a second b~aster,c
such as the 8087, takes control of the bus, CSO goes
active and remains active until the 8087 passes control
back to the processor. At this time CSO is deactivated.
A functional block diagram of the CSI-CSO circuit is
shown in Figure 1L A grant pulse on the RQ/GTO line
gives. control to the 8087 and also causes the
8087CONTROL signal to go active, which in tum
causes CSO to go active. The 8087CONTROL signal
~ inactive when either a release is received on
RQ/GTO, indicating that the 8087 is relinquishing control to the main processor, or a grant is received on the
RQ/GTl line, indicating that the 8087 is relinquishing
control to a third processor. Both actions signify that
the 8087 is relinquishing the bus. If CSO goes ·inactive
because a third processor took control of the bus, then
CSO will go active again for the 8087 when a release
pulse is transmitted on the RQ/GTl line to the 8087.
This release pulse occurs as a result of SYSHLDA going inactive from the third processor.
5.4.3 SYSTEM DESIGN EXAMPLE
To provide the 8087 access to data' in low memory
through an integrated chip-select, the LCS pin should
be disconnected from the bank that it is currently selecting and fed directly into the 82188 CSI. The CSI
~ut should be connected .!£...!.he banks which the
LCS formerly selected.· The LCS will still select the
same banks because CSO goes active whenever CSI
goes active. But now the 8087, when taking control of .
the bus, may also select these banks.
Care must be taken in locating the 8087 data area because it must reside in the area in which the chip-select
is defined. If the 8087 generates an address outside of
the LCS range, the CSO will still go active, but the
address will erroneously select a part of the lower bank.
Note also that this chip-select limits the size of the 8087
data area to the maximum size memory which can be
selected with one chip-select. However, this does not
place a limit on instruction code size or non-8087 data
size. All 80186 and 8087 instructions are fetched by the
processor and therefore do not require that the 808.7 be
82188 IBC
=D8087 CONTROL
HOLD
HLDA
r--r---
RQ/GTO
ARBITRATION
LOGIC
SYSHOLD
SYSHLDA
Figure 11. 82188 Chip Select Circuitry
5-92
231590-10
AP-258
able to address them. Likewise, non-8087 data is never
accessed by the 8087 and therefore does not require an
8087 chip-select.
5.5 Wait State & Ready logic
The 8087 must accurately track every instruction fetch
the 80 186 performs so that each op-code may be read
from the system bus by the 8087 in parallel with the
processor. This means that for instruction code areas,
the 80 186 cannot use internally generated wait states.
All ready logic for these areas must be generated externally and sent into the ,82188. The 82188 then presents
a synchronous ready out (SRO) signal to both the
80186 and the 8087.
5.5.1 INTERNAL WAIT STATES WITH
INSTRUCTION FETCHES
If internal wait states are used by the processor with the
8087 at zero wait states, then the 8087 will latch opcodes using a four clock bus cycle while the processor is
using between five and seven clocks on each bus cycle.
If the wait states are truly necessary to latch valid data
from memory, then a four clock bus cycle will force the
8087 to latch invalid data. The invalid data may then be
possibly interpreted to be an ESCAPE prefix when, in
reality, it is not. The reverse may also hold true in that
the 8087 may not recognize an ESCAPE prefix when it
is fetched. These conditions could cause a system to
hang (i.e., cease to operate), or operate with erroneous
results.
If the memory is fast enough to allow latching of valid
data within a four clock bus cycle, then the 80186 internal wait states will not cause the system to hang. Both
processors will receive valid data during their respective bus cycles. The 8087 will finish its bus cycle earlier
than the processor, but this is of no consequence to
system operation. The 8087 will synchronize with the
processor using the status lines SO-S2 at the start of the
next instruction fetch.
Memory used for 8087 data is somewhat different.
Here, as in the case of code segment areas, the system
must rely on an external ready signal or else the memory must be fast enough to support zero wait state operation. Without an external ready signal, the 8087 will
always perform a four clock bus cycle which, when
used with slow memories, results in the latching of invalid data.
Internal wait states will not affect system operation for
data cycles performed by the 8087. In this case the 8087
has control of the bus and the two processors operate
independently.
One type of data cycle has not yet been considered.
Each time a numerics variable is accessed, the host
processor runs a "Dummy Read Cycle" in order to
calculate the operand address Jor the 8087. The 8087
latches the address and then takes control of the bus to
fetch any subsequent bytes which are necessary. If the
8087 variables are located at even addresses, then an
intern'ally generated wait state will not present any
problems to the system. If any numeric variables are
located at odd addresses, then the interface between the
host and coprocessor becomes asynchronous causing
erroneous results.
The erroneous results are due to the 80186 running two
back-to-back bus cycles with wait states while the 8087
runs two back-to-back bus cycles without wait states.
The start of the second bus cycle is completely uncoordinated between the two processors and the 8087 is unable to latch the correct address for subsequent transfers. For this reason, 8087 variables in a 80186 system
must always lie on even boundaries when using the internal wait state generator to access them.
Numeric variables in an 80188 system must never be in
a section of memory which uses the internal wait state
generator. The 80188 will always perform consecutive
bus cycles which would be equivalent to the 80186 performing an odd addressed "Dummy Read Cycle."
5.5.3 AUTOMATIC WAIT STATES AT RESET
5.5.2 INTERNAL WAIT STATES WITH DATA &
1/0 CYCLES
With the exception of "Dummy Read Cycles" and instruction fetches, all memory and I/O bus cycles executed by the host processor are ignored by the 8087.
Coprocessor synchronization is not required for untracked bus cycles and, therefore, internally generated
wait states do not affect system operation. All of the
I/O space and any part of memory used strictly for
data may use the internal wait state generator on the
80186.
The 80186 automatically inserts three wait states to the
predefined upper memory chip select range upon power
up and reset. This enables designers to use slow memories for system boot ROM if so desired. If slow ROM's
are chosen, then no further programming is necessary.
If fast ROM's are chosen, then the wait state logic may
simply be reprogrammed to the appropriate number of
wait states.
The automatic wait states have the possibility of presenting the same problem as described in section 5.5.1 if
5-93
AP-258
the boot ROM needs one or more wait states. Under
these conditions the 8087 would be forced to latch invalid opcodes and possibly mistake one for an ESCAPE
instruction.
If the boot ROM requires wait states, then some sort of
external ready logic is necessary. This allows both processors to run with the same number of wait states and
insures that they always receive valid data.
If the boot ROM does not require wait states, then
there is no need to design external ready logic for the
upper chip select region. But if 8087 code is present in
the upper memory chip select region, the situation described in section 3.4 regarding ','Dummy Read Cycles"
must be considered.
The 82188 solves this problem by inserting three wait
• states on the SRO line to the 8087 for the first 256 bus
cycles. By doing this the 82188 inserts the same number
of wait states to both processors keeping diem synchronized. The initialization code for the 80186 must program the upper memory chip select to look at external
ready and to insert zero wait states within these first
256 bus cycles. At the end of the 256 bus cycles, the
82188 stops inserting wait states and both processors
run at zero wait states.
5.5.4 EXTERNAL READY SYNCHRONIZATION
The 80186 and 8087 sample READY on different clock
edges. This implies that some sort of external synchronization is required to insure that both processors sample the same ready state. Without the synchronization,
it would be possible for the external signal to change
. state between samples. The 80186 may sample ready
high while the 8087 samples ready low. This would lead
to the two processors running different length bus cycles and possibly cause the system to hang.
The 82188 ,provides ready synchronization through the
ARDY and SRDY inputs. Once a valid transition is
recorded, the 82188 presents the results on the SRO
output and holds the output in that state until both
processors have had a chance to sample the signal.
5.6 BUS ARBITRATION
KNOWLEDGE protocol to' exchange control of the
bus with another processor. The 82188 supplies the
necessary conversion to interface RQ/GT to HOLD/
HLDA signals. The RQ/GT~nal of the 8087 connects directly to the 82188's RQ/GTO input while the
82188's HOLD and HLDA pins connect to the 80186's
HOLD and HLDA pins.
When the 8087 requires control of the bus, the 8087
sends a request on the RQ/GTO line to the 82188. The
82188 responds by sending a HOLD request to the
80186. When HLDA'is received back from the 80186,
the 82188 sends a grant back to the 8087 on the same
RQ/GTO line.
The 82188 also has provisions for adding a third busmaster to the system which uses HOLD/HLDA protocol. This is accomplished by ~inLthe 82188
SYSHOLD, SYSHLDA, and RQ/GTl signals.
The third processor requests the bus by pulling the
SYSHOLD line high. The 82188 will route (and translate if necessary) the requests to the current bus master.
If the 8087 has control, the 82188 will request control
via the RQ/GTl line which should be connected to the
8087's RQ/GTl line.
The 8087 will relinquish control by~tt3 off the bus
and sending a grant pulse on the RQ/GTI line. The
82188 responds by sending a SYSHLDA to the third
processor. The third processor lowers SYSHOLD when
it has finished on the bus. The 82188 routes this in the
form of a release pulse on the RQ/GTI line to the
8087. The 8087 then continues bus activity where it left
off. The maximum latency from SYSHOLD to
SYSHLDA is equal to the 80186 latency + 8087 latency + 82188 latency.
5.7 SPEED REQUIREMENTS
One of the most important timing specs associated with
the 80186-8087 interface is the speed at which the system should run. The 8087 was designed to operate with
a 33% duty cycle clock whereas the 80186 and 80188
were designed to operate with a 50% duty cycle clock.
In order to run both parts off the same clock, the 8087
must run at a slower speed than is typically implied by
its dash number in the 8086/88 family.
In order for the 8087 to read and write numeric data to
and from memory, it must have a means of taking control of the local bus. With the 8086/88,this is accomplished through a request-grant exchange protocol. The
80186, however, makes use of HOLD/HOLD AC-
!;i-94
inter
AP-258
onstrate the large increase in floating-point math performance provided by the 8087 and also the increase in
performance due to the enhanced 80186 and 80188 host
processors.
To determine the speed at which an 8087 may run
(with a 50% duty cycle clock), the minimum low and
high times of the 8087 must be examined. The maximum of these two minimum specs becomes the half-period of the 50% duty cycle system clock. For example,
the 8087-1 provides worst case spec compatibility with
the 80186 at system clock-speeds of up to 8 MHz. The
clock waveforms are shown in Figure 12 using 10 MHz
timings.
The 8086 results were measured on an Intellec® Series
III Microcomputer Development System with an
iSBC® 86/12 board and an iSBC 337 multimodule.
Typically, one wait state for memory read cycles and
two wait states for memory write cycles are experienced
in this environment.
The minimum clock low time spec (TCLCH) of the 10
MHz 8087 is 53 ns. The clock low time of an 8 MHz
80186 is specified to be:
%(TCLCU -
The 80186 and 80188 results were measurep on a prototype board which allowed zero wait state operation at
8 MHz. The benchmarks measured using the 8087
showed little sensitivity to wait states. Instructions executed on the 8087 tend to be long in comparison to the
amount of bus activity required and, therefore, are not
affected much by wait states.
7.5
Solving for TCLCL of the 80186 using TcicH of the
8087 yields the following:
%(TCLCU -
7.5
= TCLCH
(TCLCL)
=
TCLCL
= 121 ns
The benchmarks measured using the software emulator
are much more bus intensive and average from 10 to 15
percent performance degradation for one wait state.
+ 7.5)
2(TcLCH
All execution times shown here represent 8 MHz operation. The 8086 results were measured at 5 MHz and
extrapolated to achieve 8 MHz execution times.
The calculation shows minimum cycle time of the
80186 to be 121 ns. This time translates into a maximum frequency of 8.26 MHz.
6.2 Interest Rate Calculations
6.0 BENCHMARKS
Routines were written in FORTRAN-86 to calculate
the final value of a fund given the annual interest and
the present value. It is assumed that the interest will be
compounded daily, which requires the calculation of
the yearly effective rate. This value, which is the equivalent annual interest if the interest were compounded
daily, is determined by the following formula:
6.1 Introduction
The following benchmarks compare the overall system
performance of an 8086, 80188, and an 80186 in numeric applications. Results are shown for all three
processors in systems with the 8087 coprocessor and
in systems using an 8087 software einulator. Three
FORTRAN benchmark programs are used to dem-
yer = (1
+
(ir/np»**np - 1
~-------------100ns------------~
10t.1Hz--""""\.
8087 SPECS
33% DUTY CYCLE
CLOCK
I
"
I
\
"\
1 - - - - - - TCLCH - - - - - + I
MIN. LOW TIME
8MHz - - - ,
80186 SPECS
50% DUTY CYCLE
CLOCK
I
"
I
\. .
1------------------- TClCl
"'--
MINIMUM ------------------1
231590-11
Figure 12. Clock Cycle Timing
5-95
intJ
Ap·258
where:
6.3 Matrix Multiply Benchmark
Routine
yer is the yearly effective rate
ir is the annual interest rate
np is the number of compounding periods per
annum
Once the yer is determined, the filjal value of the fund
is determined by the formula:
A routine was written in FORTRAN-86 to compute
the product of two matrices using a simple row/column
inner-product method. Execution times were obtained
for the multiplication of 32 X 32 matrices using double
precision. The results of the benchma~k are shown in
Figure 14.
Iv = (1 +yer) • pv
where:
The results show the 8087 coprocessor systems performing from 23 to 31 times faster than the equivalent
software emulation program. Both the 80188/87 and
the 80186/87 systems outperform the 8086/87 system
by 34 to 75 percent. This difference is mainly attributed
to the fact that the matrix program largely consists of
effective address calculations used in array accessing.
The hardware effective address calculator of the 80186
and 80188 allow each array access to improve by as
much 'as three times the 8086 effective address calculation.
pv is the present value
fv is the future value
Results are obtained using single-precision, double-precision, and temporary real precision operands when:
ir is set to 10% (0.1)
np is set to 365 (for daily compounding)
pv is set to $2,000,000
THE RESULTS:
yer
Final Value
Single-Precision
(32-bit)
10.514%
$2,210,287.50
Double-Precision
(64-bit)
10.516%
$2,210,311.57
Temporary Real
Precision
10.516%
$2,210,311.57
6.4 Whetstone Benchmark Routine
The Whetstone benchmark program was developed by
Harry Curnow 'for the Central Computer Agency of the
British government. This benchmark has received high
visibility in the scientific community as a,measurement
of main frame computer performance. It is a "synthetic" program. That is, it does not solve a teal problem,
but rather contains a mix of FORTRAN statements
which reflect the frequency of such statements as me!losured in over 900 actual programs. The program computes a performance metric: "thousands of Whetstone
instructions per second (KIPS)."
The difference between the final single-precision and
double-precision values is $24.07; the difference in the
fmal value between the double-precision and the temporary real precision is 0.000062 cents. Since the 8087
performs all internal calculations on 80-bit floating
point numbers (temp real format), temporary real precision operations perform faster than single- or doubleprecision. No data conversions are required when loading or storing temporary real values in the 8087. Thus,
for business applications, the double-precision computing of the 8087 is essential for accurate results, and the
performance advantage of using the 8087 turns out to
be as much as 100 times the equivalent software emulation program.
Simple variable and array addressing, fixed- and floating- point arithmetic, subroutine calls and parameter
passing, and standard mathematical functions are performed in eleven separate modules or loops of a prescribed number of iterations.
Table 2 Interest Rate Benchmark Results
8087 Software Emulator
Single Precision
, 8087 Coprocessor
80188
8086
80186
80188
8086
80186
70.3 ms
62.8 ms
43.4 ms
.7,0 ms
.66ms
.61 ms
Double Precision
72.1 ms
62.9 ms
44.4 ms
.71 ms
.66ms' .61 ms
Temp Real Precision
72.6ms
63.0 ms
44.8 ms
.69ms
.65ms
.59ms
Average
71.7 ms
62.9ms
44.2 ms
.70ms
.66ms
.60ms
5-96
inter
Ap·258
The original coding of the Whetstone benchmark was
written in Algol-60 and used single-precision values. It
was rewritten in FORTRAN with single-precision values to exactly reflect the original intent. Another version was created using double-precision values. The results are shown in Table 3.
The results show the 8087 systems with the 80186 and
80188 outperforming the equivalent software emulation
by 60 to 83 times. Additionally, the 80186 coupled with
the 8087 outperformed the 8086/87 system by 22 percent.
110
..g
104.1
100
w
,."'"
89.7
-[]
90
Z
0:
..8~
~
0 0
--95.5
I'!
I'-"'""'
2.0
~
0:
o
r--
1.4
Z
;-1.0
0.9
r-
80188
-
1.0
8086
80186
80188/8087
8086/8087
80186/8087
231590-12
Figure 13_lnterest Rate Benchmark Results
41.1
40
..,.,
31.5
30
0
I'!
w
'"
e'"
0:
20
~
~
'"'"
z
00--23.6
"z
I'-"'""'
21.6
0:
;--
0
, 1.0
It-
-
1.0
.
;-u
=
.2
---
u
u
=
"'..;'"
"'-
PCS1
~
- ....or1:
a
L1.1
PXO
I CLEAR DIIA REQUEST
EXT INTO I PRIORITY
SETB
Cta
Cta
Pi. 2
Pl.3
Pl.4
, UPDATE STATUS WITH
,CONFIGURE-DONE EVENT
(STATUS=C5H IF E=O)
lEO
Cta
Cta
Pi. 0
SETB Pl.O
JB
P3.2,$
RETI
ILLEGAL BYTE COUNT
SET THE E STATUS BIT
IGNORE PENDING EXT INTO (IF ANY)
INTERRUPT THE SOlS6
WAIT TILL INTERRUPT IS ACICLK A J---'CA:::7:....._ _ _ _ _ _•
ACK
..:.R:.:E~SET:.:..-_-I
CLR
C
to BIU
B J---'A:::;Bl......_ _ _ _ _ _•
Biriary Counter
270520-B
Figure 8. Logic Representation of Refresh Address Counter
Bit
CDRAM:
Bits 0-8:
Bits 9-15:
15
I0
14
13
12
11
10
9
876
0
0
0
0
0
0
5
4
3
2
0
~ ~ ~ ~ ~ ~ ~ ~ ~I
CO-CB, define the number of CLKOUT cycles between each Refresh Request
o = 512, 1 = 1,2 = 2, ... These bits are set to 0 on RESET.
Reserved, should be written as 0 to maintain future compatibility, will always be read
~ack
as o.
Figure 9. CORAM Register Format
There are no limitations placed on the programming of
the MORAM register, but be aware that any chip select memory region that overlaps the address established by the MORAM register will be activated during
refresh bus cycles. Therefore, the register should be
programmed to correspond to the chip select address
that is activated for the dynamic memory partition:
Programming the Refresh Clock
Register
The CORAM register (Figure 9) is used to define the
rate at which refresh requests will be internally generated. The CORAM register is used to maintain the start-
ing value of a down counter, which decrements each
falling edge of CLKOUT. When the counter decrements to 1, a refresh request is generated and the counter is again loaded with the value contained in the
CORAM register. Initially, however, the contents of
the CORAM register is loaded into the down counter
when the enable bit in the EORAM register set. Thus,
if the CORAM register is changed, the new value will
take effect when either the down counter reaches 1 and
reloads itself, or whenever the E bit is written to a 1
(this is true whether the bit was previously set or not).
When the 80C186 is reset, the CORAM register is initialized to zero. A value of zero in the CORAM register is used to indicate the maximum count rate of 512
clocks.
.
5-141
'intJ
AB-31
RpERIOD (,..,S) • FREQ (MHz)
I=
I # Refresh Rows
+ (# Refresh Rows· % Overhead)
CORAM Register Valve
Rperiod = Maximum Refresh period specified by the DRAM manufacturer (time in microseconds).
FREQ = Operating Frequency at BOCIBS in megahertz.
#Refresh Rows = Total number of rows to be refreshed.
% Overhead = Derating factor that estimates the number of missed refresh requests (typically 1-5%).
Figure 10. Equation to Calculate Refresh Interval
Bit 15
14
lEO
13
12
11
10
9
876
0
0
0
0
0
~ ~ ~ ~ ~ ~ ~ ~ ~I
5
4
320
, Bits 0-8:
T0- T8, Refresh request down counter clock count. These 'bits are read only and represent the current value of
the counter. Any write operation to these bits is ignored. These bits are set to 0 on RESET or when the E bit is
cleared.
Bits 9-14: Reserved, should be Wrillen to as a 0 to maintain future compatibility, will always be read back as zero.
E, enables the operation of the refresh control unit. Selling the E bit will automatically load the Request Down
Bit 15:
Counter. Clearing the E bit stops refresh operation and clears the Down Counter.
Figure 11. EDRAM Register Format
The equation shown in Figure 10 can be used to determine the value of the CDRAM register needed to establish a desired refresh request ratl;. Note that the equation is based on the internal operating frequency of the
8OC186. Therefore, the request rate is effected by any
change in operating frequency. Modification of the operating frequency can occur in two ways: modifying the
input clock or entering power-save mode. There is no
upper limitation as to the frequency of refresh requests
(other than programming), but there is a lower limit.
This lower limit is based on the fact that the request
rate can be no faster than the time it takes to service the
request. Subsequently, the minimum programming value of the CDRAM register should be 18 (12H). It is
very doubtful that this will ever become a problem
when operating at normal frequencies, since the refresh
rate of most dynamic memories is well above this minimum programming value.
However, when making use of the power-save feature
of the 80C186, it is possible to lower the operating frequency such that it will prevent adequate refreshing
rates. When operating at 12.5 MHz, dividing the clock
by 16 results in a cycle time of 1.28 microseconds. Since
the minimum value of the CDRAM is 18, the minimum refresh rate is 23.04 microseconds. 23 microseconds is not fast enough to service most dynamic memories. Therefore, caution must be exercised when using
the power-save feature of the 80C186. When there is a
need to keep dynamic memory alive, the clock should
not be divided much below 2 MHz to avoid monopolizing the bus with refresh activity. If there is no desire to
keep memory alive during power-save operation, then
the refresh unit can simply be disabled during this time.
Programming the Refresh Enable
Register
The EDRAM register (Figure II) is used to enable and
disable the refresh control unit. Furthermore, reading
the register returns the current value of the down counter.
Setting the E bit enables the RCU and loads the value
of the CDRAM register into the down counter. Whenever the E bit is cleared, the refresh control unit is
disabled and the down counter is cleared. Disabling the
refresh control unit does not change the contents of the
refresh address counter (i.e. it is not cleared or initialized to any specific value). Thus, when the refresh unit
is again enabled, the address generated will continue
from where it left off. Resetting the 80CI86 automatically clears the E bit. There are no refresh bus cycles
during a reset.
The current value of the. down counter, as well as the
present state of the E bit can be examined whenever the
EDRAM register is read. Any unused bits will be returned as zero. Whenever the E bit is cleared, the TO
through T8 bits will be read as zero.
REFRESH CONTROL UNIT
OPERATION
Figure 12 illustrates the two major operational functions of the refresh control unit that are responsible for
initiating and controlling DRAM refresh bus cycles.
5-142
\,
inter
AB·31
Refresh Control Unit Operation
BIU
Re~resh
Bus Operation
Executed
~ _ • Evary
,
Clock.J.-
Continua
270520-10
270520-9
Figure 12. Flowchart of RCU Operation
The down counter is loaded (with the contents of the
CORAM register) on the falling edge of CLKOUT,
either when the EFRSH bit is set or whenever the
counter decrements to 1. Once loaded, the down counter will decrement every falling edge of CLKOUT. It
will continue to decrement as long as the EFRSH bit
remains set.
When the down counter fmally'decrements to 1, two
things will happen. First, a request is generated to the
BIU to run a refresh bus cycle. The request remains
active until the bus cycle is run. Second, the down
counter is reloaded with the value contained in the
CORAM register. At this time, the down counter will
again begin counting down every clock cycle, it does
not wait until the request has been serviced. This is
done to ensure that each refresh request occurs at the
correct interval. Otherwise, if the down counter only
started after the previous request were service, the time
between refresh requests would also be a function of
bus activity, which for the most part is unpredictable.
When the BIU services the refresh request, it will clear
the request and increment the refresh address.
80C188 Address Considerations
The physical address that is generated during a refresh
bus cycle is shown in Figure 7, and it applies to both
the 8OC186 and 8DC188. For the 8DC188, this means
.that, the lower address bit AD will not toggle during
refresh operation. Since the 8DC188 has an 8-bit external bus, AD is used as part of memory address decod-
ing. Whereas the 8DC186, with its 16-bit external bus,
uses AD (along with BHE) to select memory banks.
Therefore, when designing 8DC188 memory subsystems
it is important not to include AD as part of the ROW
address that is used as a refresh address. Appendix A
illustrates Memory Address Multiplexing Techniques
that can be applied to the 8DC186 and the 8DC188.
MISSING REFRESH REQUESTS
Under most operating conditions, the frequency of refresh requests is a small percentage of the bus bandwidth. Still, there are several conditions that may prevent a refresh request from being serviced before another request is generated. These conditions include:
1) LOCKED Bus Cycles
2) Long Bus accesses (wait states)
3) Bus HOLD
LOCKED Bus Cycles
Whenever the bus is LOCKED, the CPU maintains
control of the BIU and will not relinquish it until the
locked operation is complete. Therefore, internal operations like refresh and DMA are not allowed to execute
'until the LOCKED instruction has completed. Where
this presents the greatest problem is when an instruction such as a move string is executed, and is locked.
The move string instruction can take from several
clocks to hundreds of thousands of clocks to complete.
Obviously anything that takes longer than 512 clocks to
complete will always cause a refresh overflow.
5-143
. AB·31
Care should be taken not to generate long executing
.instructions that require bus accesses and are locked.
'The refresh request interval can be shortened to compensate for missing requests.
one clock period to allow the refresh bus cycle to be
run. If HOLD. is again asserted, the 80C186 will give
up the bus after the refresh bus cycle has been run
(provided there is not another refresh request generatljd
during that time).
Long Bus Accesses
The 80C186 does not provide any mechanism to abort
or terminate a bus access in the event ready is not returned within a specified amount of time (the 80C186
will infinitely wait for ready). Therefore, if a bus access
is in progress when a refresh request is generated, the
bus access must complete before the request will be
serviced.
Bus HOLD
Special consideration is given when a refresh request is
generated and the 80C186 is currently being held off
the bus due to a HOLD request.
When another bus master has control of the bus, the
HLDA signal is kept active as long as the HOLD input
remains active. If a refresh request is generated while
HOLD is active, the 8OC186 will remove (drive inactive) the HLDA signal to indicate to the other bus master that the8OC186 wishes to regain control of the bus
(see Figure 13). If, and only if, the HOLD input is
removed will the BIU begin to run the refresh bus cycle.
Therefore, it is the responsibility of the system designer
to ensure that the 8OC186 can regain the bus if a refresh
request is signaled. The sequence of HLDA going inactive while HOLD is active can be used to signal a pending refresh request. HOLD need only go inactive for
EFFECTS OF MISSING REFRESH
REQUESTS
If a refresh request has not' been serviced before another
request is generated, the new request is not recorded
and is lost. For instance, if the interval between refresh
request is 15 microseconds and one request is lost, then
the time between two requests will be 30 microseconds
when the next request is fmally serviced. In this example, missing one request will add 15 p.s to the total
refresh time. If it is anticipated that refresh requests
may be missed (due to programming or system operation), then the refresh request interval should be shortened to allow for missed requests.
Since the BIU is responsible for maintaining the refresh
address counter, missing a refresh requests does not imply that refresh addresses are skipped. In fact, an address can never be skipped unless a reset occurs.
CONCLUSION
The Internal Refresh Control Unit of the 80C186 and
80C188 helps solve three issues concerning DRAM refreshing: a way to generate periodic refresh requests; a
way to generate refresh addresses; a way to simplify
DRAM memory controllers. Once a memory controller
has been designed to handle the simple tasks of reading
and writing the task of refreshing has already been built
in.
5-144
inter
AB·31
HLDA _ _ _ _ _
@r"'~@
ooo...:l:::/
~
I®®
--1.
000 _ _ _ _ _ _ _ _ _ _ _
ooo-ooo~ooo _ _ _ _ __1~
Ref Active _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
..JJ®
'---
270520-11
NOTES:
1. System generates HOLD request.
2. HLDA is returned and 80C186 floats bus/control.
3. Refresh request is generated internal to 80C186.
4. 80C186 lowers (removes) HLDA to signal that it wants the bus back.
5. 80C186 waits until HOLD is lowered (removed) for at least 1 clock cycle (minimum HOLD setup and hold time) to
execute the refresh bus cycle. If HOLD is never lowered. the 80C186 will not take over the bus.
6. 80C186 runs the refresh bus cycle.
7. HOLD can be again asserted after the 1 clock duration.
8. The refresh request is cleared after the bus cycle has been executed.
9. If HOLD was again asserted. the 80C186 will immediately relinquish the bus back. If no HOLD occurred. normal CPU
operation will resume.
Figure 13. HOLD/HLDA Timing and Refresh Request
5-145
inter
APPENDIX A
TYPICAL DRAM ADDRESS GENERATION
CONSIDERATIONS FOR 80C186/80C188
80C186 DESIGNS
64Kx 1
16Kx4
256Kx 1
64Kx4
1Mx 1
256Kx4
(128K Bytes)
. (32K Bytes)
(512K Bytes)
(128K Bytes)
(2M Bytes)
(512K Bytes)
Row Address
(AO-AX)
Column Address
(AO-AX)
A1-A8
A1.·A8
A1-AS
A1-A8
A1-A10
A1-AS
AS-A16
AS-A14
A10-A18
AS-A16
A11-A1S(+ Bank)
A10-A18
80C188 DESIGNS
NOTE:
Address bit AO can be used in either RAS or CAS addresses, so long as it is not included in any refresh address
bits.
.
64Kx 1
16Kx4
256Kx 1
64Kx4
1Mx1
256Kx4
(64K Bytes)
(16K Bytes)
(256K Bytes)
(64K Bytes)
(1M Byte)
(256K Bytes)
Row Address
(AO-AX)
Column Address
(AO-AX)
A1-A7,AO
A1-A7,AO
. A1-A8, AO
A1-A8
A1-AS,AO
A1-AS
A8-A15
A8-A13
AS-A17
AO, AS-A15
A10-A1S
AO, A10-A17
RAM Type
RASAdd
CAS Add
Refresh Add
64Kx 1
16Kx4
256Kx 1
64Kx4
1Mx 1
256Kx4
AO-A7
AO-A7
AO-A8
AO-A7
AO-AS
AO-A8
AO-A7
AO-A5
AO-A8
AO-A7
AO-AS
AO-A8
AO-A6
AO-A6
AO-A7
AO-A7
AO-A8
AO-A8
5-146
inter
APPLICATION
BRIEF
AB-3S
December 1987
DRAM Refresh/Control with the
80186/80188
STEVE FARRER
APPLICATIONS ENGINEER
@ Intel Corporation, 1987
Order Number: 270524-001
5-147
intJ
AB-3S
all the chip selects so that READY goes active whenever all the memory chip selects are inactive (i.e. the cycle
is not in a valid memory region).
In many low-cost 80186/80188 designs, dynamic memory offers an excellent cost/performance advantage.
However, DRAM interfacing is often complicated by
the need to perform memory refreshing. This application brief describes how to use the Timer and DMA
functionality of the 80186/80188 to perform memory
refresh.
BUS OVERHEAD
The absolute maximum overhead can be calculated at a
given speed by taking the number of refresh cycles divided by the total number of bus cycles for a given
period of time. At 8 MHz these values can be calculated as follows:
THEORY OF OPERATION
Dynamic RAM refreshing is accomplished by strobing
a ROW address to every ROW of the DRAM within a
given period of time. One way to do this is to perform
periodic sequential reads to the DRAM using a DMA
controller and'a Timer. This can be achieved with the
80186/188 by Programming Timer 2 and one of the
DMA channels such that the timer generated one
DMA' cycle approximately every 15 micro-seconds.
Please note that this is a single row refresh method and
not a burst refresh. Single row refreshing reduces the
bus overhead considerably when compared to burst refreshing.
2 bus cycles
15.2 p.s / 500 ns
X 100
=
,
6.6% maximum overhead
In reality, the bus overhead associated with the DMA
cycles is much lower due to the instruction prefetch
queue. When a DMA cycle is requested by the timer for
a refresh cycle, -the Bus Interface Unit honors the request on the, next bus cycle boundary (with the exception of LOCKed bus cycles and odd aligned accesses).
Typically this time is idle time on the bus and the impact on the overall performance is extremely small. The
following table shows more realistic data which was
acquired by running 6 different benchmarks with and
without the DMA channel enabled to provide refresh
every 15.2/1s.
The control logic of the DRAM is such that a' RAS
(row address strobe) occurs on every memory read, regardless of the address. This is necessary because the
DMA channel is cycling through the entire 1 MByte
address space and the address of the refresh cycle does
not always fall within the range of the DRAM bank.
BENCHMARK RESULTS
Although the address may be outside the DRAM
range, the lower address bits continue to change and
'
roll over to provide the row address.
80186
80188
@
8 MHz
Minimum
Maximum
Average
1.3%
2.4%
5.9%
6.5%
2.5%
3.4%
The programs which showed the highest bus overhead
tended to be very bus intensive. Also note that at faster
frequencies the bus overhead becomes even less.
READY LOGIC WITH MEMORY
Since the DMA controller is cycling through the entire
I MByte address space, care must be taken to ensure
that a READY signal is available for all addresses. One
way to do this is to use only the internal wait state
generator for memory areas and to strap the SRDY and
ARDY pins HIGH. Whenever a refresh cycle occurs
outside of a predefined internal wait state area, the external ready pins, which are active HIGH, will complete the bus cycle.
DMA OPERATION
If it is necessary to use the external ready signals for
The DMA controller is programmed to be source synchronized with the TC (transfer count) bit cleared. This
ensures that the DMA controller never reaches a final
count. The source pointer continues to increment
through memory on every cycle. When FFFFFH is'
reached, the address rolls over to OOOOOH
certain memory regions, then it will be necessary to add
logic which will generate a ready signal whenever the
address of a refresh cycle falls where there is no memo- ,
ry. This can easily be accomplished by either decoding
a couple of high order address lines, or by AND-ing
The programming values for the DNA registers are
shown in Figure 1. The source pointer may be initialized to any location since the starting location of the
refresh is arbitrary.
5-148
inter
AB-3S
The value of the Transfer Count register is also arbitrary since the TC bit is not set. The DMA channel will
continue to run cycles upon request from Timer 2 even
after the Transfer Count register has reached zero.
Once zero is reached, the Transfer Count register will
roll over to FFFFH and continue to count down.
The destination pointer may be set to any available
memory or I/O location. This pointer must be set so
that it neither increments nor decrements. Otherwise,
the address of the deposit cycle would cycle through
memory or I/O doing writes which could possibly be
destructive. Thus the INC and DEC bits of the control
register should be cleared.
.-------SQURCE SYNCHRONIZED
,.-----ACCEPT TIMER REQUEST
PROGRAM AND START
+ I WORD TRANSFER
r----
,....-.....,....-.....
~,
543210
CAH
'-;---:'~-i-:rIT""""""'-'...!.r"...'_1......,' -+--1
CONTROL WORD
HIGH PRIORITY
DO NOT INTERRUPT
L..-_ _ _ _ _ _ _ _ DO NOT STOP ON TERMINAL COUNT
' - - - - - - - - - - - SOURCE MEMORY (INCREMENT)
' - - - - - - - - - - - - - DESTINATION I/o (NO INC/DEC)
L..-_ _ _
L..-_ _ _ _ _ _ _
=
15
=
87
~~~ I--"":'A":":VA":":I:-LA:-:B:":"L'='E":"I/~O~~~:-:::-::-'-'-II-+-- DESTINATION
15
C2H
r--___"'=__-
POINTER
87
......______J-..:-:=::-=c'-ll_+__ SOURCE POINTER
COH,.. . . . . . . . . . . . . .. .
270524-1
NOTES:
1. Locations of registers are relative to the base address of the peripheral control block. The offsets shown are for
ChannelO.
2. The byte/word bit is a don't ca,re in a B01BB system. In a B01B6 system this bit should be set to a 1 to represent word
transfers.
3. The transfer count register is located at offset CBH. It is not necessary to program this register.
Figure 1. DMA Registers
5-149
intJ
AS-3S
When setting the count value of the timer, keep in mind
the timer clock is· operating at 'one-fourth the CPU
clock frequency. Thus, the equation for setting the timer count is:
TIMER OPERATION
Timer 2 must be programmed to generate a DMA request every time a row 'must be refreshed. Since we are
not using a burst refresh, the refresh time is divided up
evenly among the number of rows. For a 2 ms refresh
DRAM with 128 rows, the time between rows equals
15;62 microseconds.
(CPU CLOUT FREQ) x (Time Between ROWS)
4
= COUNT_VALUE (decimal)
For an 8 MHz clock, programming the Maximum
Count Register to lEH provides a 15.2 ,""S refresh. This
programming is indicated in Figure 2.
,15
66H
87'
0
1111101 DON'T CARES 1010101011~ ~ IMODE/CONTROL WORD I
'-,...Jj
Ji'-----CONTINUOUS OPERATION
' - - - - - DO NOT ALTERNATE
'-------INTERNAL CLOCKING
,
' - - - - - - - - - - - - - - - - DO NOT INTERRUPT
' - - - - - - - - - - - - - - - START OPERATION
15
62H
87
0
10101010101010101010101111111110' ~ IMAX COUNT A REGISTER I
Figure 2. Timer 2 Registers programmed for a 15.2 ,""s Refresh at 8 MHz
5-150
270524-2
inter
AB-3S
er to the DRAM. This address consists of AO through
A7. The B address (A8 through A16) is selected when
MUX goes LOW. The system shown in Figure 3 represents that of an 80188 system.
EXAMPLE 1:
DRAM CONTROL WITH
A DELAY LINE
This is the most straight forward way of implementing
t~e RAS and CAS'logic. A RAS signal is generated by
either RD or WR going active while the address is
within the corresponding range. Normally the logic for
~S would also go active for a refresh cycle status, but
since this information is, not available on the
80186/80188, a RAS must be generated for every RD
and WR, regardless address.
For an 80186 system, the A address would start at AI.
The least significant address line AO along with BHE
would be used to decode WE into WEH and WEL
which will be shown in the second example. Also, the
186 DMA must be set to do word transfers so that the
address is incremented by 2 after each refresh cycle.
This is necessary to ensure Al increments by 1 every
refresh cycle.
The MUX signal is used to change from the RAS address to the CAS address after latching with RAS. This
is accomplished by using a delay line which generates a
MUX signal by a fixed number of nano-seconds after
RAS is generated. The important timing here is the
necessary ,hold time for the row address into the
DRAM.
CAS is generated in the same manner by delaying the
MUX signal a fixed number of nano-seconds. Typically
CAS goes inactive at the same time as RAS to ensure a
valid CAS precharge time before the next DRAM access. The 80186/188 chip selects are used to ensure that
CAS only goes active when the address falls within the
DRAM bank range, and to ensure that CAS does not
go active during I/O cycles.
The MUX signal is initially HIGH which sends the A
side (see Figure 3) Row address through the multiplex-
BOIBB
TDIRQ
r+1
"-
DMA
CONTROL
TIMER
COUNTER
...
-..
DATA
.
ADDRESS ....
74LS373
LATCH
15:0
~
74l.S157
MUX
A/B
l~LE
DYNAMIC
MEMORY
H
MUX
25ns
WE
BUS
CONTROL
WR
RD
1 __
:I
'--
~
IN
J
-I
BANK SELECT
CHIP
SELECTS
DELAY
LINE
~
CAS
RAS
270524-3
Figure 3. Using A Delay Line for DRAM Control
5-151
AB·35
EXAMPLE 2:
DRAM CONTROL WITH A PAL *
This design uses a PAL to generate all the control logic
for the DRAM array. Internal feedback is used on the
signals to control the timing and states of the RAS,
MUX and CAS signals.
This design uses 256k X 4 DRAMs. With minor changes to the PAL equations this design could just as easily
make use of 64k X 1, 64k X 4, or 256k X 1 DRAMs.
The RAS signal is generated off ALE going LOW, bus
cycle status active, and PRE~S being active. The
PRE_RAS signal is necessary to ensure that a RAS is
not accidentally generated when S2-S0 are becoming
valid and ALE has not yet gone HIGH in T4 phase 2.
PRE_RAS does not go active until ALE has gone
HIGH.
.
RAS is initiated for every memory read and write regardless of the bus cycle address. This ensures a row
refresh when the refresh address falls outside of the
DRAM bank and also a refresh to both banks simultaneously so that the frequency of the refresh can be set
for the number of rows in one bank of DRAM.
The UCS (Upper Chip Select) from the 80186/188 is
used to disable DRAM signals when the processor is
attempting to access upper memory control ROM.
Thus the portion of memory used by the UCS (maximum 256k) is unavailable in the upper DRAM. However, the RAS signal must still be allowed during UCS
access to ensure refreshing when the DMA refresh cycle occurs in the UCS region.
MUX is generated off T2 phase 1 and RAS active.
MUX will remain low until the current RAS signal
goes inactive during T3 phase 2.
CASO and CASI are generated off MUX being active
and T2 phase 2 of the bus cycle. CAS goes inactive at
the start of T4 phase 2.
ADDRESS
MULTIPLEXERS
Al-9 ....
LATCHED ..
ADDRESS ..
A1D-18 ,.
~
I
I
COL
T
--..§2
MUX
-----i!
RAS
---¥
(2) 256KX4
I
..
(2)256KX4
RASa
RASa
CASO
WEH
,.-;
I
. . . 015-8
CASO
~
~O
.... 07-0
r
I
A19
WR
~
~
~
DRAM ADDRESS (A8 -AO)
ROW
16L8 PAL
--l!£§.
~
~
(2) 256KX 4
(2)256KX4
RASl
CASl
WEH
. . . 015-8
HIGH BYTE
RASl
-,. CASl
WEL
. . . 07-0
LOW BYTE
CASl
PRE_RAS N•C•
WEH
WEL
LATCHED A19
- --+
... DATA <15:8>
"I
... DATA <7:0>
"I
270524-4
Figure 4. Using a PAL for DRAM Control
'PAL" is a registered trademark of Monolithic Memories.
5-152
AB-3S
TW
)
,
..H ..
II
~
I-TCLAV
STATUS
SO-S2
I1
)
ADDRESS
ALE
,
_ TCLCL
ADDRESS VALID
X
VALID DA A
(WRITE C LE)
!/uoIlJ11!/
I\~"\
.LJ!!J!U
\.\(1CHSV:J\.\.
"\~"\
/~/
STATUS VALID
/,(TOIJIYI
~\(Ta.Rl.:J\.\.
RD.WR
TCVCTV
TCVCTX
\.\91\"\
!/!/~!//.
I\.\.'ClruV!J\
~
X
lID
ROW
V///
~
N:lruV~
DRAM
ADDRESS
If
\
XII]
COLUMN
X
"\~"\
/
TOVCL
I:::::
~DATA~
RD DATA
I
270524-5
Figure 5.. Timing Diagram for PAL DRAM Controller
5-153
inter
AS-35
PAL EQUATIONS FOR 80186 SYSTEM
ALE • 52 • 51 * 50+
ALE' 52' 51' 50 +
ALE • S2 • S1 • 50 +
PRE RA5' 52 • 51 • 50 +
PRE RA5' 52 * 51 * SO +
PRE-RA5' 52 * 51 • SO
PRE RA5 * ALE 52 • 51 • SO +
PRE RA5' ALE 52 • 51 • 50 +
PRE_RAS' ALE 52 • 51 • 50 +
RA5' ClK
;IN5TRUCTION FETCH
;READ DATA/REFRE5H
;WRITEDATA
;KEEP PRE-RA5 VALID
; WHilE STATU5
;15 VALID
;IN5TRUCTION FETCH
;READ DATA/REFRESH
;WRITEDATA
;KEEP ACTIVE DURING T3A
RA5 • elK +
RA5' MUX
A19' MUX' ClK' RA5 +
CAS1 • RD +
CA51 'WR +
CAS1 • ClK
A19 *UC5 • MUX • ClK." RA5 +
CAS1 • RD +
CAS1 'WR +
CAS1 * ClK
WR*AO
WR' BHE
TIMING EQUATIONS
TClAV
TCHlH
TCHll
TCH5V
TCl5H
TClRl/TCVCTV
TClRH
TDVCl
8 MHz
10 MHz
55
35
35
55
65
70
55
20
50
30
30
45
50
56
44
15
The .following equations are with reference to given
clock edge. The edge in reference is indicated by the
= rising edge of T3
first element in the equation: T3
clock .J, T1 = falling edge of T1 clock.
.
t
DELAY 1
DELAY 2
DELAY 3
DELAY 4
DELAY 5
DELAY 6
DELAY 7
= T1
t
t
+ TCHll + (PAL DELAY)
= .J, T2 + (PAL DELAY)
= T2
+ (PAL DELAY)
= .J, T1 + (PAL DELAY)
=
=
=
.J, T3 + TCl5H + (PAL DELAY)
.J, T1 + TCLAV + (MUX DELAY)
.J, T2 + DELAY 2 + (MUX DELAY)
ACCESS TIME FROM RAS = 2.5 (TCLCL)-DELAY 1.
-TDVCL
ACCESS TIME FROM CAS
1.5 (TCLCL)-DELAY 3
-TDVCL
5-154
MCS® . . 96 Application Notes &
Article Reprint
.
6
inter
APPLICATION·
NOTE
AP-248
September 1987
Using The 8096
IRA HORDEN
MCO APPLICATIONS ENGINEER
© Intel Corporation, 1987
Order Number: 270061-002
6-1
AP-248
1.0 INTRODUCTION
2.0 8096 OVERVIEW
High speed digital signals are frequently encountered in
modem control applications. In addition, there is often
a requirement for high speed 16-bit and 32-bit precision
in calculations. The MCS®-96 product line, generically
referred to as the 8096, is designed to be used in applications which require high speed calculations and fast
I/O operations.
2.1. General Description
Unlike microprocessors, microcontrollers are generally
optimized for specific applications. Intel's 8048 was optimiz~ for general control tasks while the 8051 was
optimized for 8-bit math and single bit boolean operations. The 8096 has been designed for high speed/high
performance control applications. Because it has been
designed for these applications the 8096 architecture is
different from that of the 8048 or 8051.
The 8096 is a 16-bit microcontroller with dedicated
I/O subsystems and a complete set of 16-bit arithmetic
instructions including multiply and divide operations.
This Ap-note will briefly describe the 8096 in section 2,
and then give short examples of how to use each of its
key features in section 3. The concluding sections feature a few examples which make use of several chip
features simultaneously and some hardware connection
suggestions. Further information on the 8096 and its
use is available from the sources listed in the bibliography.
There are two major sections of the 8096; the CPU
section and the I/O section. Each of these sections can
be subdivided into functional blocks as shown in Figure
2-1.
YPD XTAL 1
XTAL 2
CLKOUT
--~-------- --------------,
P3 REG
CLOCK
GEN
a
ON-CHIP
ROM
A·BUS
Ei
ALE
INST. REG
iiiiE
iiO
Wii
RALU
READV
~--~====~==-1--RESET
DATA
YREF
ANGND
I
I
I
I
IL __________ _
POACH
p,
P2/ ALT. FUNCTIONS
HS1
HSO
270061-1
Figure 2-1. 8096 Block Diagram
6-2
inter
AP-248
In the lower 24 bytes of the register file are the registermapped I/O control locations, also called Special
Function Registers or SFRs. These registers are used to
control the on-chip I/O features. The remaining 232
bytes are general purpose RAM, the upper 16 of which
can be kept alive using a low current power-down
mode.
2.1.1. CPU SECTION
The CPU of the 8096 uses a 16-bit ALU which operates
on a 256-byte register file instead of an accumulator.
Any of the locations in the register file can be used for
sources or destinations for most of the instructions.
This is called a register to register architecture. Many
of the instructions can also use bytes or words from
anywhere in the 64K byte address space as operands. A
memory map is shown in Figure 2-2.
65535
16384
EXTERNAL MEMORY
OR
1/0
FFFFH
4DOOH
INTERNAL PROGRAM
STORAGE ROM
2080H
8320
8210
FACTORY TEST CODE
INTERRUPT
VECTORS
8192
8190
~
RESET
2012H
8
;
0
PORT 4
PORT 3
2000H
lFFEH
EXTERNAL MEMORY
OR
EXTERNAL MEMORY RESERVED
FOR USE BY INTEL DEVELOPMENT
SYSTEMS
(WHEN ACCESSED AS PROGRAM
MEMORY)
____________________
O
OOOOH
r----------------------,255
O
0100H
OOFFH
~
DO
1/0
INTERNAL RAM
REGISTER FILE
STACK POINTER
SPECIAL FUNCTION REGISTERS
(WHEN ACCESSED AS
DATA MEMORY)
~
256
255
270061-2
Figure 2-2. Memory Map
6-3
i~
AP-248
Figure 2-3 shows the layout of the register mapped
I/O. Some of these registers serve two functions, one if
they are read from and another if they are written
to. More information about the use of these registers is
included in the description of the features which they
control.
OFFH
255
POWER·DOWN
RAM
OFOH
OEFH
240
239
INTERNAL
REGISTER FILE
(RAM)
I6
1AJ
19H
18H
h
STACK POINTER
STACK POINTER
25
24
PWM_CONTROL
23
16H
IOS1
IOC1
22
15H
10SO
lOCO
21
14H
13H
12H
RESERVED
RESERVED
20
19
18
17H
11H
SP_STAT
SP_CON
17
10H
10 PORT 2
10 PORT 2
16
OFH
10 PORT 1
10 PORT 1
15
OEH
10 PORTO
BAUD_RATE
ODH
TIMER2 (HI)
OCH
TIMER2 (LO)
OBH
TIMER1 (HI)
OAH
TlMER1 (LO)
14
13
RESERVED
12
WATCHDOG
10
11
09H
INT_PENDING
INT_PENDING
08H
INT_MASK
INT_MASK
07H
SBUF (RX)
SBUF (TX)
7
06H
HSLSTATUS
HSO_COMMAND
6
05H
HSLTIME (HI)
HSO_TlME (HI)
5
04H
HSLTIME (LO)
HSO_TlME (LO)
03H
AD_RESULT (HI)
HSLMODE
02H
AD_RESULT (LO)
AD_COMMAND
01H
RO (HI)
RO (HI)
OOH
RO(LO)
RO (LO)
(WHEN READ)
(WHEN WRITTEN)
270061-3
Figure 2-3: SFR Layout
6-4
infef
AP-248
A symmetric set of byte and word operations make up
the majority of the 8096 instruction set. The assembly
language for the 8096 (ASM-96) uses a "B" suffix on a
mnemonic to indicate a byte operation, without this
suffix a word operation is indicated. Many of these operations can have one, two or three operands. An example of a one operand instruction would be:
2.1.2.110 FEATURES
Many of the I/O features on the 8096 are designed to
operate with little CPU intervention. A list of the major
I/O functions is shown in Figure 2·4. The Watchdog
Timer is an internal timer which can be used to reset
the system if the software fails to operate properly. The
Pulse· Width· Modulation (PWM) output can be used as
a rough D to A, a motor driver, or for many other
purposes. The A to D converter (ADC) has 8 multi·
plexed inputs and IO-bit resolution. The serial port has
several modes and its own baud rate generator. The
High Speed I/O section includes a 16-bit timer, a 16-bit
counter, a 4-input programmable edge detector, 4 software timers, and a 6·output programmable event generator. All of these features will be described in section
2.3.
NOT
Value1;
Value1:
=
1's complement (Value1)
A two operand instruction would have the form:
ADD
Value2,Value1;
Value2:
=
Value2
+
Value1
A three operand instruction might look like:
MUL
Value3,Value2,Value1;
Value3 :
=
Value2' Value1
The three operand instructions combined with the register to register architecture almost eliminate the necessity of using temporary registers. This results in a faster
processing time than machines that have equivalent instruction execution times, but use a standard architecture.
2.2. The Processor Section
2.2.1. OPERATIONS AND ADDRESSING MODES
The 8096 has 100 instructions, some of which operate
on bits, some on bytes, some on words and some on
longs (double words). All of the standard logical and
arithmetic functions are available for both byte and
word operations. Bit operations and long operations are
provided for some instructions. There are also flag manipulation instructions as well as jump and call instructions. A full set of conditional jumps has been included
to speed up testing for various conditions.
Long (32-bit) operations include shifts, normalize, and
multiply and divide. The word divide is a 32-bit by 16bit operation with a 16-bit quotient and 16-bit remainder. The word multiply is a word by word multiply
with a long result. Both of these operations can be done
in either the signed or unsigned mode. The direct unsigned modes of these instructions take only 6.5 microseconds. A normalize instruction and sticky bit flag
have been included in the instruction set to provide
hardware support for the software floating point package (FP AL-96).
Bit operations are provided by the Jump Bit and Jump
Not Bit instructions, as well as by immediate masking
of bytes. These bit operations can be performed on any
of the bytes in the register file or on any of the special
function registers. The fast bit manipulation of the
SFRs can provide rapid I/O operations.
Major 1/0 Functions
High Speed Input Unit
Provides Automatic Recording of Events
High Speed Output Unit
Provides Automatic Triggering of Events and Real-Time Interrupts
Pulse Width Modulation
Output to Drive Motors or Analog Circuits
A to D Converter
Provides Analog Input
Watchdog Timer
Resets 8096 if a Malfunction Occurs
Serial Port
Provides Synchronous or Asynchronous Link
Standard I/O Lines
Provide Interface to the External World when other Special Features
are not needed
Figure 2-4. Major 110 Functions
6-5
Ap·248
. Mnemonic
Oper-
Flags
Operation (Note 1)
ands
N
C
V
VT
ST
t
t
t
t
t
t
t
t
t
t
t
-
ADD/ADDB
2
D -
".
".
".
".
ADD/ADDB
3
".
".
".
".
,J.
".
".
".
".
".
".
".
".
".
".
".
,J.
".
".
".
D+A
ADDQ/ADDCB
2
D B+A
D +- D+A+C
SUB/SUBB
2
D -
SUB/SUBB
3
SUBC/SUBCB
2
D B-A
D-D-A+C-1
CMP/CMPB
2
D-A
".
".
".
".
MULIMULU
2
D,D + 2 -
DO A
-
3
D,D + 2 -
BOA
-
-
-
MULIMULU
MULB/MULUB
2
D,D + 1 -
DO A
-
-
MULB/MULUB
3
D,D + 1 -
BO A
-
-
DIVU
2
D -
(D, D + 2)/ A, D
-
remainder
-
-
DIVUB
2
D -
(D, D + 1)/A, D + 1 -
remainder
-
DIV
2
D -
(D, D + 2)/A, D + 2 -
remainder
-
DIVB
2
D -
(D,D + 1)/A,D + 1 -
remainder
-
-
AND/ANDB
2
D -
DandA
".
AND/ANDB'
3
D -
BandA
".
DorA
D (excl. or) A
D-A
OR/ORB
2
'XOR/XORB
2
D D -
LD/LDB
2
D-A
+2
ST/STB
2
A-D
LDBSE
2
LDBZE
2
D-A;D+1 SIGN(A)
D-A;D+1-0
PUSH
1
SP -
POP
1
A -
PUSHF
0
SP SP - 2; (SP) PSW OOOOH
SP-2;(SP) (SP);SP -
A
SP+2
PSW;
Notes
Z
-
".
".
-
?
?
".
0
0
".
0
0
".
".
0
0
".
".
0
0
-
-
-
-
-
-
-
-
-
-
-
0
0
-
-
-
-
?
?
?
?
-
2
3
-
2
-
3
-
-
-
-
-
.-
-
-
0
0
0
0
-
1-0
POPF
0
PSW -
".
".
".
".
".
".
1
PC -
PC + 11·bit offset
-
-
-
-
-
LJMP
1
PC -
PC + 16-bit offset
,-
-
PC (A)
SP ~ SP - 2; (SP) -E- PC;
PC PC + 11·bit offset
-
-
-
-
-
-
-
-
-
SP + 2;
1-".
-
BR (indirect)
1
SCALL
1
LCALL
1
SP PC -
SP - 2; (SP) PC;
PC + 16·bit offset
(SP);SP SP + 2
PC + B·bit offset (if taken)
JNC
1
~umpifC =
0
-
JE
1
JumpifZ = 1
-
RET
0
J (conditional)
1
PC PC -
JC
1
JumpifC = 1
3,4
3,4
-
SJMP
(SP); SP -
2
3
3
-
- -
-
2
-
-
-
-
-
-
-
-
5
5
5
5
5
5
5
5
Figure 2·5. Instruction Summary
NOTES:
1. If the mnemonic ends in "B", byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment rules for the required operand type. D and B are locations in the register file; A can be
located anywhere in memory.
2. D, D + 2 are consecutive WORDS in memory; D is DOUBLE·WORD aligned.
3. D, D + 1 are consecutive BYTES in memory; D is WORD aligned.
4. Changes a byte to a word.
5. Offset is a 2's complement number.
a
6·6
inter
Mnemonic
AP-248
Oper-
Flags
Operation (Note 1)
ands
Notes
Z
N
C
V
VT
ST
-
-
5
-
5
-
-
5
-
-
5
5'
-
5
JNE
1
JumpifZ = 0
-
JGE
1
Jump ifN = 0
-
-
-
JLT
1
Jump ifN = 1
-
-
-
JGT
1
Jump if N = 0 and Z = 0
-
-
JLE
1
-
-
-
JH
1
JNH
1
-
-
-
1
-
-
-
JV
-
-
-
-
5
JNV
1
=1
Jump if C = 1 and Z = 0
Jump if C = 0 or Z = 1
Jump if V = 1
Jump if V = 0
-
-
-
-
-
-
-
-
5
JVT
1
Jump if VT = 1; Clear VT
-
-
-
0
-
5
JNVT
1
-
-
-
0
JST
1
-
-
-
-
5
-
-
-
-
-
-
-
-
-
5
5,6
-
-
-
-
5,6
-
-
-
-
5
Jump if N = 1 or Z
JNST
1
= 0; Clear VT
Jump ifST = 1
JumpifST = 0
JBS
3
Jump if Specified Bit = 1
-
JBC
3
Jump if Specified Bit
=0
-
-
DJNZ
1
-
-
DEC/DECB
1
D +- D - 1; if D "" 0 then
PC +- PC + 8-bit offset
D+-D-1
NEG/NEGB
1
D+-O-D
INC/INCB
1
D+-D+1
EXT
1
D +- D; D + 2 +- Sign (D)
EXTB
NOT/NOTB
1
D +- D; D + 1 +- Sign (D)
1
D +- Logical Not (D)
CLR/CLRB
1
D+-O
SHLlSHLB/SHLL
2
C +- msb-----Isb +- 0
SHR/SHRB/SHRL
2
0-+ msb-----Isb -+ C
SHRA/SHRAB/SHRAL
2
msb -+ msb-----Isb -+ C
Jump if VT
-
'"
'"
'"
'"
'"
'"1
'"
'"
'" '" '"
'" '" '"
'" '"0 '"0
'" 0 0
'" 0 0
'"0 0 0
?
'" '"0
?
-
t
t
t
-
5
5
-
-
2
3
-
t
-
-
'"
-
7
7
7
SETC
0
C+-1
'"
'"- -'" '"1
CLRC
0
C+-O
-
CLRVT
0
VT +- 0
-
RST
0
PC +- 2080H
0
0
0
0
0
0
DI
Disable All Interrupts (I +- 0)
-
-
-
-
-
-
NOP
0
PC +- PC + 1
SKIP
0
PC+-PC+2
-
-
-
EI
0
0
-
-
-
'"
?
0
-
-
-
7
-
-
-
-
-
-
9
Enable All Interrupts (I +- 1)
=
NORML
2
Left Shift Till msb
TRAP
0
SP +- SP - 2; (SP) +- PC
PC +- (2010H)
1; D +- shift count
0
0
-
-
-
-
-
-
'"
-
-
-
'0
8
Figure 2-5. Instruction Summary (Continued)
NOTES:
1. If the mnemonic ends in "B", a byte operation is performed, otherwise a word operation is done. Operands D, B, and A
must conform to the alignment rules for the required operand type. D and B are locations in the register file; A can be
located anywhere in memory.
5. Offset is a 2's complement number.
6. Specified bit is one of the 2048 bits in the register file.
7. The "L" (Long) suffix indicates double-word operation.
8. Initiates a Reset by pulling RESET low. Software should re-initialize all the necessary registers with code starting at
2080H.
9. The assembler will not accept this mnemonic.
6-7
intJ
AP-248
One operand of most of the instructions can be used'
with anyone of six addressing modes. These modes
increase the flexibility and overal) execution speed of
the 8096. The addressing modes are: register-direct, immediate, indirect, indirect with auto-increment, and
long and short indexed.
mode. In this mode a 16-bit 2's complement value is
added to the contents of a word register to form the
address of the operand. By using the zero register as the
index, ASM96 (the assembler) can accept "direct" addressing to any location. The zero register is' located at
OOOOH and always has a value of zero. A short indexed
mode is also available to save some time and code. This
mode uses an 8-bit 2's complement number as the offset
instead of a 16-bit number.
The fastest instruction execution is gained by using either register direct or immediate addressing. Registerdirect addressing is similar to normal direct addressing,
except that only addresses in the register file or SFRs
can be addressed. The indexed mode is used to directly
address the remainder of.the 64K address space. Immediate addressing operates as would be expected, using
the data following the opcode as the operand.
2.2.2. ASSEMBLY LANGUAGE
The multiple addressing modes of the 8096 make it easy
to program in assembly language and provide an excellent interface to high level languages. The instructions
accepted by the assembler consist of mnemonics followed by either addresses or data. A list of the mnemonics and their functions are shown in Figure 2-5.
The addresses or data are given in different formats
depending on the addressing mode. These modes and
formats are shown in Figure 2-6. '
Both of the indirect addressing modes use the value in a
word register as the address of the operand. If the indirect auto-increment mode is used then the word register
is incremented by one after a byte access or by two after
a word access. This mode is particularly useful for accessing lookup tables.
Additional information on 8096 assembly language is
available in the MCS-96 Macro Assembler Users
Guide, listed in'the bibliography.
Access to any of the locations in the 64K address space
can be obtained by using the long indexed addressiI.lg
Mnem
Mnem
Mnem
Dest or Src1
Dest, Src1
Dest, Src1, Src2
; One operand direct
; Two operand direct
; Three operand direct
Mnem
Mnem
Mnem
#Src1
Dest, #Src1
Dest, Src1, #Src2
; One operand immediate
; Two operand immediate
; Three operand immediate
Mnem [addr]
Mnem [addr] +
Mnem Dest, [addr]
Mnem Dest, [addr] +
Mnem ,Dest, Src1, [addr]
Mnem Dest, Src1, [addr] +
;
;
;
;
;
;
Mnem
Mnem
; Two operand indexed (short or long)
; Three operand indexed (short or long)
Dest, offs [addr]
Dest, Src1, offs [addr]
One operand indirect
One operand indirect auto-increment
Two operand indirect
Two operand indirect auto-increment
Three operand indirect
Three operand indirect auto-increment
Where: "Mnem" is the instruction mnemonic
"Dest" is the destination register
"Src1", "Src2" are the source registers
"addr" is a register containing a value to be used in computing the address of an operand
"offs" is an offset used in computing the address of an operand
270061-83
Figure 2-6. Instruction Format
6-8
inter
AP-248
SOURCE
INTERRUPT
r - - - IOC1.1
EXTINT ~'O-------- EXTINT
ACH.7 - - 4
TI FLAG - - - , - - - - - - - - - SERIAL PORT
RIFLAG--.J
r--- HSO_COMMAND.4
~o---------
SOFTWARE TIMER
SOFTWARE TIMER 0 ~
SOFTWARE TIMER 1
SOFTWARE TIMER 2
SOFTWARE TIMER 3
RESET TIMER 2'
START AID CONVERSION'
H S I . O - - - - - - - - - - - HSI.O
r--- HS(l£OMMAND.4
ANY HSO OPERATION - - 0
~o--------- HIGH SPEED OUTPUTS
,.---IOC'.7
FIFO IS FULL ~ HSI DATA AVAILABLE
HOLDING REGISTER LOADED _ _
AID CONVERSION COMPLETE - - - - - - - - - - - A:D CONVERSION COMPLETE
,.---IOC1.2
I
"0'0----.--- TIMER OVERFLOW
TlMER2 OVERFLOW _ _ "lo
TIMER' OVERFLOW _ _
I
'Only when Inillated by the HSO unit.
L---IOC'.3
270061-4
Figure 2-7. Interrupt Sources
2.2.3. INTERRUPTS .
The flexibility of the instruction set is carried through
into the interrupt system. There are 20 different interrupt sources that can be used on the 8096. The 20
sources vector through 8 locations or interrupt vectors.
The vector names and their sources are shown in Figure 2-7, with their locations listed in Figure 2-8. Control of the interrupts is handled through the Interrup~
Pending Register (INT_PENDING), the Interrupt
Mask Register (INT_MASK), and the I bit in the
PSW (PSW.9). Figure 2-9 shows a block diagram of the
interrupt structure. The INT_PENDING register
contains bits which get set by hardware when an interrupt occurs. If the interrupt mask register bit for that
source is a 1 and PSW.9 = 1, a vector will.be taken to
the address listed in the interrupt vector table for that
Source
Software
Extint
Serial Port
Software Timers
HSLO
High Speed
Outputs
HSI Data
Available
AID Conversion
Complete
Timer Overflow
Vector
Location
Priority
(High
Byte)
(Low
Byte)
2011H
200FH
200DH
200BH
2009H
2007H
2010H
200EH
200CH
200AH
2008H
2006H
Not Applicable
7 (Highest)
6
5
4
3
2005H
2004H
2
2003H
2002H
1
2001H
2000H
o (Lowest)
Figure 2-8. Interrupt Vectors and Priorities
6-9
intJ
AP·248
source. When the vector is taken the INTJENDING
bit is cleared. If more than one bit is set in the INT_
PENDING register with the corresponding bit set in
the INT~ASK register, the Interrupt with the highest priority shown in Figure 2-8 will be executed.
The software can make the hardware interrupts work in
almost any fashion desired by having each routine run
with its own setup in the INT_MASK register. This
will be clearly seen in the examples in section 4 which
change the priority of the vectors in software. The
SOFTWARE
EXTINT
SERIAL PORT
TIMERS
HSI.O
HSO
AID CONV.
TIMER
OVERFLOW
o
TRANSITION
DETECTOR
INTERRUPT MASK REG.
1---'"
(PSW:9)
PRIORITY ENCODER
INTERRUPT
GENERATOR
D-BUS
CONTROL
UNIT
270061-5
Figure 2·9. Interrupt Structure Block Diagram
6-10
inter
AP-248
WHERE:
Z is the zero flag. It is set when the result of an operation is zero.
N is the negative flag. It is set to the algebraically correct sign of the result regardless of overflows.
V is the overflow flag. It is set if an overflow occurs.
VT is the overflow trap flag. It is set when the VT flag is set and cleared by JVT, JNVT. or CLRVT..
C is the carry flag. It is set if a carry was generated by the prior operation.
I is the global interrupt enable bit.
ST is the sticky bit. It is set during a right shift if a one was shifted into and then out of the carry flag.
INT_MASK is the interrupt mask register and contains bits which individually enable the 8 interrupt vectors.
Figure 2-10. The PSW Register
PSW (shown in Figure 2-10), stores the INT_MASK
register in its lower byte so that the mask register can
be pushed and popped along with the machine status
when moving in and out of routines. The action of
pushing flags clears the PSW which includes PSW.9,
the interrupt enable bit. Therefore, after a PUSHF instruction interrupts are disabled. In most cases an inter,
rupt service routine will have the basic structure shown
below.
INT
struction is executed to restore the old PSW. The RET
instruction is executed and the code returns to the desired location. Although the POPF instruction can enable the interrupts the next instruction will always execute. This prevents unnecessary building of the stack by
ensuring that the RET always executes before another
interrupt vector is taken.
2.3. On-Chip 110 Section
VECTOR:
PUSHF
LDB INT_MASK, #xxxxxxxxB
EI
;Insert service routine here
POPF
RET
The PUSHF instruction saves the PSW including the
old INT.-MASK register. The PSW, including the interrupt enable bit are left· cleared. If some interrupts
need to be enabled while the service routine runs, the
INT_MASK is loaded with a new value and interrupts are globally enabled before the service routine .
continues. At the end of the service routine a POPF in-
6-11
All of the on-chip I/O features of the 8096 can be accessed through the special function registers, as shown
in Figure 2-3. The advantage of using register-mapped
I/O is that these registers can be used as the sources or
destinations of CPU operations. There are seven major
I/O functions. Each one 'of these will be considered
with a section of code to exemplify its usage. The first
section covered will be the High Speed I/O, (HSIO),
subsystem. This section includes the High Speed Input
(HSI) unit, High Speed Output (HSO) unit, and the
Timer/Counter section.
2.3.1. TIMER/COUNTERS
The 8096 has two time bases, Timer 1 and Timer 2.
Timer 1 is a 16-bit free running timer which is incremented every 8 state times. (A state time is 3 oscillator
periods, or 0.25 microseconds with a 12 MHz crystal.)
inter
AP-248
2.0 "SCLOCK
HSI TRIGGER OPTIONS
LHITOLO
___--'r
HSI.O
HSI.l
HSI.2
HSI.3
TRIGGERED
INPUT«S)
CHANGE
DETECTOR
16
LO TO HI
20
FIFO
CURRENT
STATUS
t,
EVERY EIGHTH POSITIVE
TRANSITION
2700S1-S
• Pulse measurement with 2.0 Itsec resolution
• Input transitions lrigger the recording of the reference
Timer (IS·bit) and triggered input(s) (4-bit)
Figure 2-11. HSI Unit Block Diagram
Its value can be read at any time and used as a reference for both the HSI section and the HSO section.
Timer I can cause an interrupt when it overflows, and
cannot be modified or stopped without resetting the
entire chip. Timer 2 is really an event counter since it
uses an external clock source. Like Timer I, it is 16-bits
wide, can be read at any time, can be used with the
HSO section, and can generate an interrupt when it
overflows. Control of Timer 2 is limited to incrementing it and resetting it. Specific values can not be written
to it.
2.3.2. HSI
The HSI unit can be thought of as a message taker
which records the line which had an event and the time
at which the event occurred. Four types of events can
trigger the HSI unit, as shown in the HSI block diagram in Figure 2-11. The HSI unit can measure pulse
widths and record times of events with a 2
LOCATION 03H
Although the 8096 has only two timers, the timer flexibility is equal to a unit with many timers thanks to the
HSIO unit. The HSI enables one to measure times of
external events on up to four lines using Timer I as a
timer base. The HSO unit can schedule and execute
internal events and up to six external events based on
the values in either Timer I or Timer 2. The 8096 also
includes separate, dedicated timers for the baud rate
generator and watchdog timer.
HSI.O MODE
L----HSI.l MODE
' - - - - - - H S f . 2 MODE
L - - - - - - - - H S I . 3 MODE
2700S1-7
Where each 2-bit mode control field
defines one of 4 possible modes:
00
01
10
11
8 positive transitions
Each positive transttion
Each negative transition
Every transition (positive and negative)
Figure 2-12. HSI Mode Register
6-12
inter
AP-248
microsecond resolution. It can look for one of four
events on each of four lines simultaneously, based on
the information in the HSI Mode register, shown in
Figure 2-12. The information is then stored in a seven
level FIFO for later retrieval. Whenever the FIFO contains information, the earliest entry is placed in the
holding register. When the holding register is read, the
next valid piece of information is loaded into it. Interrupts can be generated by the HSI unit at the time the
holding register is loaded or when the FIFO has six or
more entries.
2.3.3. HSO
Just as the HSI can be thought of as a message taker,
the HSO can be thought of as a message sender. At
times determined by the software, the HSO sends mes-
6 3 0
I x I TID I I I
CHANNEL
I
c)'5 HSO.O - HSO.5
HSO.O AND HSO.1
HSO.2 AND HSO.3
80a SOFlWARE TIMERS
E
RESET TIMER 2
START AID CONVERSION
F
L-------------INTERRuPTmOINTERRUPT
L-_____________ SET/CLEAR
L-_________________ TIMER 2fTIMER 1
CHANNEL
270061-8
Figure 2-13. HSO Command Register
2.0 ItS CLOCK
CONTROL
LOGIC
HIGH SPEED OUTPUT CONTROLS
6 PINS
4 SOFlWARE TIMERS
2 INTERRUPTS
INITIATE AID CONVERSION
RESET TIMER 2
270061-9
Figure 2-14. HSO Block Diagram
"inter
Ap·248
sages to various devices to have thein tum on, tum off,
start processing, or reset. Since the programmed times
can be referenced to either Timer 1 or Timer 2, the
HSO makes the two timers look like many. For example, if several events have to occur at specific times, the
HSO unit can schedule all of the events based on a
single timer. The events that can be scheduled to occur
and the forrilat of the command written to the HSO
Command register are shown in Figure 2-13.
A CAM (Content Addressable Memory) file is the
main component of the HSO. This file stores up to
eight events which are pending to occur. Every state'
time one location of the CAM is compared with the
two timers. After 8 state times, (two microseconds with
a 12 MHz clock), the entire CAM has been searched
for time matches. If a match occurs the specified event
will be triggered and that location of the CAM will be
made available for another pending event. A block diagram of the HSO unit is shown in Figure 2-14.
The software timers listed in the figure are actually 4
software flags iii I/O Status Register 1 (lOS 1). These
flags can be set, and optionally cause an interrupt, at
any time based on Timer 1 or Timer 2. In most cases
these timers are used to trigger interrupt routineS which
must occur at regular intervals. A multitask process
can easily be set up using the software timers.
SP_ST~T
Controlling a device from a remote location is a simple
task that frequently requires additional hardware with
many processors. The 8096 has an on-chip serial port to
reduce the total number of chips required in the system.
SP_CON
(WRITE ONLy)
(READ ONLY)
lRB8~RPE J I
2.3.4. Serial Port
6
5
RI
TI
4
TB8
3 •
REN
I
~
2
PEN
I I I
1
M2
0
M1
J
L
M2,M1 SPECIFIES THE MODE;
0,0 = MODE 0
0.1 = MODE 1
1.0=MODE2
1.1 = MODE 3
~PEN
ENABLE THE PARITY FUNCTION (EVEN PARITY);
REN
ENABLES THE RECEI VE FUNCTION;
TB8
TI
PROGRAMS THE 9TH DATA BIT (IF NOT PARITY) ON
TRANSMISSION;
IS THE TRANSMIT INTERRUPT FLAG;
RI
IS THE RECEIVE INTE RRUPT FLAG;
RB8
RPE
IS THE 9TH DATA BIT RECEIVED (If NOT PARITY);
IS THE PARITY ERROR INDICATOR (IF PARITY ACTIVE).
270061-10
NOTE:
TI and RI are cleared when SP_CON is read.
Figure 2-15.. Serial Port Control/Status Register,
6-14
intJ
AP-248
Baud rates for all of the modes are controlled through
the ·Baud Rate register. This is a byte wide register
which is loaded sequentially with two bytes, and internally stores the value as a word. The least significant
byte is loaded to the register followed by the most significant. The most significant bit of the baud value determines the clock source for the baud rate generator. If
the bit is a one, the XTALI pin is used as the source, if
it is a zero, the T2 CLK pin is used. The formulas
shown in Figure 2-16 can be used to calculate the baud
rates. The variable UB" is used to represent the least
significant IS bits of the value loaded into the baud rate
register.
The serial port is similar to that on the MCS-Sl product line. It has one synchronous and three asynchronous modes. In the asynchronous modes baud rates of
up to 187.S Kbaud can be used, while in the synchronous'mode rates up to I.S Mbaud are available. The
chip has a baud rate generator which is independent of
Timer 1 and Timer 2, so using the serial port does not
take away any of the HSI, HSO or timer flexibility or
functionality.
Control of the serial port is provided through the
SPCON/SPSTAT (Serial Port CONtrol/Serial Port
STATus) register. This register, shown in Figure 2-1S,
has some bits which are read only and others which are
write only. Although the functionality of the port is
similar to that of the 80S 1, the names of sOIlte of the
modes and control bits are different. The way in which
the port is used from a software standpoint is also
slightly different since RI and TI are cleared after each
read of the register.
The baud rate register values for common baud rates
are shown in Figure 2-17. These values can be used
when XTALI is selected as the clock source for serial
modes other than Mode O. The percentage deviation
from theoretical is listed to help assess the reliability of
a given setup. In most cases a serial link will work if
there is less than a 2.S% difference between the baud
rates of the two systems. This is based on the assumption that 10 bits are transmitted per frame and the last
bit of the frame must be valid for at least six-eights of
the bit time. If the two systems deviate from theoretical
by 1.2S% in opposite directions the maximum tolerance of 2.S% will be reached. Therefore, caution must
be used when the baud. rate deviation approaches
1.2S% from theoretical. Note that an XTALl frequency of 11.0S92 MHz can be used with the table values
for 11 MHz to provide baud rates that have 0.0 percent
deviation from theoretical. In most applications, however, the accuracy available when using an 11 MHz
input frequency is sufficient.
The four modes of the serial port are referred to as
modes 0, 1, 2 and 3. Mode 0 is the synchronous mode,
, and is commonly used to interface to shift registers for
I/O expansion. In this mode the port outputs a pulse
train on the TXD pin and either transmits or receives
data on the RXD pin. Mode 1 is the standard asynchronous mode, 8 bits plus a stop and start bit are sent
or received. Modes 2 and 3 handle 9 bits plus a stop and
start bit. The difference between the two is, that in
Mode 2 the serial port interrupt will not be activated
unless the ninth data bit is a one; in Mode 3 the interrupt is activated whenever a byte is received. These two
modes are commonly used for interprocessor communi'cation.
Serial port Mode 1 is the easiest mode to use as there is
little to worry about except initialization and loading
and unloading SBUF, the Serial port BUFfer. If parity
is enabled, (i.e., PEN = I), 7 bits plus even parity are
used instead of S data bits. The parity calculation is
done in hardware for even parity. Modes 2 and 3 are
similar to Mode I, except that the ninth bit needs to be
controlled and read. It is also not possible to enable
parity in Mode 2. When parity is enabled in Mode 3 the
ninth bit becomes the parity bit. If parity is not enabled,
(i.e., PEN = 0), the TB8 bit controls the state of the
ninth transmitted bit. This bit must be set prior to each
transmission. On reception, if PEN = 0, the RBS bit
indicates the state of the ninth received bit. If parity is
enabled, (i.e., PEN = 1), the same bit is called RPE
(Receive Parity Error), and is used to indicate a parity
error.
Using XTAL 1:
M d O. Baud _ XTAL 1 frequency B
4'(B+1)
, '" 0
o e . Rate Other' Baud = XTAL 1 frequency
s. Rate
64'(B+1)
Using T2CLK:
M d ' Baud _ T2CLK frequency.
8
' 8 '" 0
o e O. Rate O h . 8aud _ T2CLK frequency.
16'8
,8 '" 0
t ers. Rate Note that 8 cannot equal 0, except when using
XTALlin other than mode 0.
Figure 2-16. Baud Rate Formulas
6-15
AP-248
Baud Rate
19.2K
9600
4800
2400
1200
300
19.2K
9600
4800
2400
1200
300
19.2K
9600
4800
2400
1200
300
XTAL 1 Frequency = 12.0 MHz
Baud Register Value
8009H
8013H
8026H
804DH
809BH
8270H
XTAL 1 Frequency'= 11.0 MHz
8008H
8011H
8023H
8047H
808EH
823CH
XTAL 1 Frequency = 10.0 MHz
8007H
800FH
8020H
8040H
8081H
8208H
Percent Error
+2.40
+2.40
-0.16
-0.16
-0.16
0.00
+0.54
+0.54
+0.54
+0.54
-0.16
+0.01
-1.70
-1.70
+1.38
-0.16
-0.16
+0.03
Figure 2-17. Baud Rate Values for 10, 11, 12 MHz
The software used to communicate between processors
is simplified by making use of Modes 2 and 3. In a basic
protocol the ninth bit is called the address bit. If it is set
high then the information in that byte is either the address of one, of the processors on the link, or a command for all the processors. If the bit is a zero, the byte
contains information for the processor or processors
previously addressed. In standby mode all processors
wait in Mode 2 for a byte with the address bit set.
When they receive that byte, the software determines if
the next message is for them. The processor that is to
receive the message switches to Mode 3 and receives
the information. Since this information is sent with the
ninth bit set to zero, none of the processors set to Mode
2 will be interrupted. By using this scheme the overall
CPU time required for the serial port is minimized.
A typical connection diagram for the multi-processor
mode is shown in Figure 2-18. This type of communicaton can be used to connect peripherals to a desk top
computer, the axis of a multi-axis machine, or any oth-'
er group of microcontrollers jointly performing a task.
6-16
AP-248
8018680286
MAIN SYSTEM
' -_ _""",,:~_ _ _'"
{
-CALCULATE COORDINATE TRANSFORMS
- DETERMINE VECTOR ENDPOINTS AND
TRAVEL TIMES
- PROVIDE USER INTERFACE
270061-11
Figure 2-18. Multiprocessor Communication
Mode 0, the synchronous mode, is typically used for
interfacing to shift registers for I/O expansion. The
software to control this mode involves the REN (Receiver ENable) bit, the clearing of the RI bit, and writing to SBUF. To transmit to a shift register, REN is set
to zero and SBUF is loaded with the information. The
information will be sent and then the TI flag will be set.
There are two ways to cause a reception to begin. The
first is by causing a rising edge to occur on the REN
bit, the second is by clearing RI with REN = 1. In
either case, RI is set again when the received byte is
available in SBUF.
input. When doing process control algorithms, it is frequently the changes in inputs that are required, not the
absolute accuracy of the value. For this reason, even if
the absolute accuracy of a lO-bit converter is the same
as that of an 8-bit converter, the lO·bit monotonic converter is 'much more useful.
Since most of the analog inputs which are monitored by
a microcontroller change very slowly relative to the 42
microsecond conversion time, it is acceptable to use a
capacitive filter on each input instead of a sample and
hold. The 8097 does not have an internal sample and
hold, so it is necessary to ensure that the input signal
does not change during the conversion time. The input
to the A/D must be between ANGND and VREF.
ANGND must be within a few millivolts of VSS and
VREF must be within a few tenths of a volt of vee.
2.3.5. A to D CONVERTER
Analog inputs are frequently required in a microcontroller application. The 8097 has a lO-bit A to D converter that can use anyone of eight input channels. The
conversions are done using the successive approximation method, and require 168 state times (42 microseconds with a 12 MHz clock.)
Using the A to D converter on the 8097 can be a very
low software overhead task because of the interrupt and
HSO unit structure. The A to D can be started by the
HSO unit at a preset time. When the conversion is complete it is possible to generate an interrupt. By using
these features the A to D can be run under complete
interrupt control. The A to D can also be directly
The results are guaranteed monotonic by design of the
converter. This means that if the analog input voltage
changes, even slightly, the digital value will either stay
the same or change in the same direction as the analog
6-17
Ap·248
AID Command Register
(LOCATION 02H)
I L
CHANNEL II SELECTS WHICH OF THE 8 ANALOG INPUT
~ CHANNELS IS TO BE CONVERTED TO DIGITAL FORM;
GO INDICATES WHEN THE CONVERSION IS TO BE
INITIATED (GO: 1 MEANS START NOW, GO: 0
MEANS THE CONVERSION IS TO BE INITIATED
BV THE HSO UNIT AT A SPECIFIED TIME).
270061-12
AID Result Register
(LOCATION 03H)
(LOCATION 02H)
AID CHANNEL NUMBER
~--- STATUS
o:
AID CURRENTLV IDLE
1 : CONVERSION IN PROCESS
'--------
AID RESULT:
LEAST SIGNIFICANT 2 BITS
MOST SIGNIFICANT BYTE
270061-13
Figure 2·19. A to D Result/Command Register
controlled by software flags which are located in the
Register, shown
in Figure 2-19.
AD~ESULT/AD_COMMAND
2.3.6. PWM REGISTER
Analog outputs are just as impo~nt as analog inputs
when connecting to a piece of equipment. True digital
to analog converters are difficult to make on a microprocessor because of all of the digital noise and the
necessity of providing an on chip, relatively high current, rail to rail driver. They also take up a fair amount
of silicon area which can be better used for other features. Th~ A to D converter does use a D to A, but the
currents Involved are very small.
For many applications an analog output signal can be
replaced by a Pulse Width Modulated (PWM) signal.
This signal can be easily generated in hardware, and
takes up much less silicon area than a true D to A. The
signal is a variable duty cycle, fixed frequency wavef?rm that can be integrated to provide an approximatIon to an analog output. The frequency is fixed at a
period o~ 64 microseconds for a 12 MHz clock speed.
~ontrollmg the PWM simply requires writing the deSIred duty cycle value (an 8·bit value) to the PWM
Register. Some typical output waveforms that can be
generated are shown in Figure 2-20.
Converting the PWM signal to an analog signal varies
in difficulty, depending upon the requirements of the
system. Some systems, such as motors or switching
power supplies actually require a PWM signal, not a
true analog one. For many other cases it is necessary
only to amplify the signal so that it switches rail.to-rail,
and then filter it. Switching rail·to-rail means that the
output of the amplifier will be a reference value when
the input is a logical one, and the output will
6-18
inter
Ap-248
be zero when the input is a logical zero. The filter can
be a simple RC network or an active filter. If a large
amount of current is needed a buffer is also required.
For low output currents, (less than 100 microamps or
so), the·circuit shown in Figure 2-21 can be used.
DUTY
CYCLE
The RC network determines how quiet the output is,
but the quieter the output, the slower it can change.
The design of high accuracy voltage followers and active filters is beyond the scope of this paper, however
many books on the subject are available.
PWM CONTROL
REGISTER VALUE
OUTPUT WAVEFORM
0%
00
HI
LO
10%
25
~~J1______~n~____~n~_____
50%
128
HI
LO
110%
230
HI
LO
19.8%
255
HI
LO
u
..J
u
270061-14
Figure 2-20. PWM Output Waveforms
Vee
* 1/2 VQ3001P
270'
PWM----~~~----.
__
----JV5·V1K~----~-----ANALOG
OUT
270061-15
'This resistor limits Rise Time to reduce spikes and high frequency noise.
Figure 2-21. PWM to Analog Conversion Circuitry
6-19
AP-248
els in this file are' different from those in the file
8096.1NC that is provided in the ASM-96 package.
3.0 BASIC SOFTWARE EXAMPLES
The examples in this section shOw how to use each I/O
feature individually. Examples of using more than one
feature at a time are described in section 4. All of the
examples in this ap-note are set up to be used as listed.
If run through ASM96 they will load and run on an
SBE-96. In order to insure that the programs work, the
stack pointer is initialized at the beginning of each program. If the programs are going to be used as modules
of other programs, the stack pointer initialization
should only be used at the beginning of the main program.
3.1. Using the 8096's Processing
Section
3.1.1. TABLE INTERPOLATION
A good way of increasing speed for many processing
tasks is to use table lookup with interpolation. This can
eliminate lengthy calculations in many algorithms. Frequently it is used in programs that generate sine waveforms, use exponents in calculations, or require some
non-linear function of a given input variable. Table
lookup can also be used without interpolation to determine the output state ofI/O devices for a given state of
a set of input devices. The procedure is also a good
example of 8096 code as it uses many of the software
features. Two ways of making a lookup table are described, one way uses more calculation time, the second
way uses more table space.
To avoid repetitive declarations the "include" file
"DEM096.INC", shown in Listing 3-1, is used. ASM96 will insert this file into the code file whenever the
directive "INCLUDE DEM096.INC" is used. The file
contains the definitions for the SFRs and other variables. The include statement has been placed in all of
the examples. It should be noted that some of the lab-
, ...........•..............................•......•..........•.......••...•.....
:
DBM096.INC -
DBFINITION OF $YMBOLIC NAMBS rOR THB
I/O REGISTERS or THB 8096
!, .............................................................................. .
ZBRO
AD COMMAND
AD-RBSOL'I" LO
AD-RESUL"-HI
HSI MODE HSO-TIME
HSI-TIMI
HSO-COMMAND
HBI-STATUS
SBUP
IN" MASK
IH'I"-PBNDING
SPCON
SPS'I'AT
MA'I'CHOOG
TIMBRl
TIMBR2
POR,.O
BAUD REG
POR,.I
POR,.2
lOCO
IOSO
IOC 1
10Sl
PIIM CONTROL
SP RSBG • t
BOU
BOU
BOU
BOU
BOU
BOU
BOU
BOU
BOU
BOU
BOU
BOU
BOU
BOU
SOU
IOU
SOU
IOU
BOU
BOU
BOU
BOU
BOU
BOU
BOU
BOU
BOU
OOh IIIORO
0281BYTI
R/II
II
02HI'8Y"l'B
R
R
OlRIBYTB
Ol8In,.!
OCR IIIORO
0481WORD
068 I BY,.!
06R I BY,.!
078, By,.B
0.8IBYTB
09".
BY"'.
,, R
,
I
118 I BYTB
llft,BYTB
OAH I BYTB
OAB IIIORO
OCHIIfORO
OSH I BYTB
If
II
If
R
R/If
R/II
R/If
If
OBH I BY,..
If
OFftln,.B
R/If
lOa,BYTB
R/II
lSHIBYTB
lSft,BY,.B
16HIBYTB
16H IBy,.B
178.BYTB
lIH Ilf0ltO
IfATCHOOG TIMSit
It
R'
It
If
,
It
I
I
I
R
I
If
If
R/If S,.ACK
,OINTBR
lCH
AX,
ox I
DSN
OSII
BX I D S i t '
eXI
OS"
AL
AH
BOU
BOU
AX
(AX+l)
I n,.s
IBY,.S
270061-16
, LIsting 3-1. Include File DEMO.96.INC
6-20
AP-248
In both methods the procedure is similar. Values of a
function are stored in memory for specific input values.
To compute the output function for an input that is not
listed, a linear approximation is made based on the
nearest inputs and nearest outputs. As an example, consider the table below.
To make the algorithm easier, (and therefore faster), it
is appropriate to limit the range and accuracy of the
function to only what is needed. It is also advantageous
to make the input step (Upper Input-Lower Input)
equal to a power of 2. This allows the substitution of
multiple right shifts for a divide operation, thus speeding up throughput. The 8096 allows multiple arithmetic
right shifts with a single instruction providing a very
fast divide if the divisor is a power of two.
If the input value was one of those listed then there
would be no problem. Unfortunately the real world is
never so kind. The input number will probably be 259
or something similar. If this is the case linear interpolation would provide a reasonable result. The formula is:
For the purpose of an example, a program with a 12-bit
output and an 8-bit input has been written. An input
step of 16 (2**4) was. selected. To cover the input range
17 words are needed, 255/16 + I word to handle values in the last 15 bytes of input range. Although only
12 bits are required for the output, the 16-bit architecture offers no penalty for using 16 instead of 12 bits.
Delta Out ~ UpperOutput·Lower Output '(Actual Input.Lower Input)
Upper Input·Lower Input
Actual Output ~ Lower Output + Delta Out
For the value of 259 the solution is:
900·400
500
Delta Out ~ 300-200 '(259-200) ~ 100 '59 ~ 5' 59 ~ 295
Actual Output
~
400 + 295
~
The program for this example, shown in Listing 3-2,
uses the definitions and equates from Listing 3-1, only
the additional equates and definitions are shown in the
code.
695
Input Value
100
200
300
400
Relative Table Address
0001H
0002H
0003H
0004H
$TITLE('INTERl.AJI'TI Interpolation routine I"l
J J '111;
8096 AsseMbly code fOr table lookup
I
$INCLUOE(:FlsDEH096.INC)
RSEG
at
interpolation
Include deao definitions
22"
IN
VALl
TABLE LOW;
TABLE:HIGH:
IN DIP,
IN-DIFB
TAB DIP,
OUT,
RESULT,
OUT_DIl'l
CSEG at
and
Table Value
100
400
900
1600
Input 'Value
I
Actual
I
Upper
,
Upper Output -
dab
daw
dow
dow
1
1
1
eq u
IN DIP
dow
daw
dew
dal
1
1
1
1
r
Delta Out
1
Input -
Lower
Input
Ibyte
Lover output
2080H
LD
SP,
1100R
270061-17
Listing 3-2. ASM-96 Code for Table Lookup Routine 1
6-21
infef
AP-248
AL,
AL,
AL,
LOB
lookr
SHRD
ANOB
IN
VAL
13.lllllllqa
,
J
,
Load teap with Actual Value
Divide the byte by 8
Insure At 1 • • word addre ••
Thi. eftectively divide. At by 2
80 AL - IN_VAL/I'
LOBZB
AX,
LO
TABLE_LOM,
At
I
Load
byte
lAX)
,
TABLB
(TABLB+2) lAX)
LD
,
I
SUB
AL
to
word
J TABLE HIGH 1. loaded with the
value
the table at table
location Ax+2
(The next value In the t~ble)
In
TAB_DIP, TABLE_HIGH, TABLB LOW
J TAB_DIP.TABLE_HIGH-TABLB_LOW
J
IN
I
Load
of
DIF8-leaat alqnlflcant
IN VAL
byte IN_DtFB to word
Output
SHRAL
I
OUT,
OUT
SRRA
OUT,
'4
I
ADDC
OUT,
•
Round
RESULT
,
Store OUT
OUT,
AT
Dew
Dew
Dew
Dew
Dew
TABLE_LOM
J
bita
-
Add output difference to output
generated with truncated IN VAL
as input
Round to 12-blt answer
up
if
Ca~rv
-
1
to RESULT
look
8R
tables
DIP,
difference
4
IN DIP
Input-difference-Table difference
Divide-by 16 (2··4)
ADD
cseg
AX
TABLE LOW Ie loaded with the'value
In the table at table location AX
2100R
000 OR,
5000R,
7BOOH,
50008,
2000H,
'AOOH,
7DOOR,
4800R,
HOOH.
4COOR
1200R',
7600H,
34008,
7800R
6DOOR
2200H
A cando.
J
function
1000H
END
270061-18
Listing 3-2. ASM-96 Code for Table Lookup Routine 1 (Continued)
lookup table. There are many applications where time
is critical and code space is overly abundant. In these
cases the code in' Listing 3-3 will work to the same
specifications as the previous example.
If the function is known at the time of writing the software it is also possible to calculate in 'advance the
change in the output function for a given change in the
input. This method can save a divide and a few other
instructions at the expense of doubling the size of the
$TITLE('INTER2.APT:
J,.r",
I
"r",
Interpol,tion
$INCLUDE(lrlIDBM09~.INC)
aBBG
at
routine
2')
8096 AsseMblv code fot table lookup and interpolation
Usin9 tabled values in place of division
J
Inelu~e
de.o
definit~on.
24H
IN VALl
TABLE LOWI
TABLE-INC:
IN DIP;
IN-DIPB
1
1
1
1
IN
OUT:
1
RESULT:
1
1
OU,._OI,.
,
,
DIP
J
1
Actual Input Value
Table value for function
Inere.ental change in function
Upper Input -"Lower Input
,
Delta Out
.byte
270061-19
Listing 3-3. ASM-96 Code For Table Lookup Routine 2
6-22
inter
AP-248
esse; at
look,
Z0800
LD
SP,
,100B
J
Initiali"e SP
LDB
SURa
,-
J
Load
AMDB
AL,
AL,
AL,
LDBIS
AX, AL
LD
TABLB_LOW,
ro VAL
]
Divide
file
•
-
VAL TABLS(AXI
Z
I TABLE LOW 1_ loaded with the value
in the value table at location AX
,
ANOB
IN_DIl'B,
LDBZB
IN_DIP,
MUL
OUT_DIP,
ADD
OUT,
OU'l'
SHR
OUT,
OUT,
'4
zero
OU'I',
RBSUL'I'
AT
reg.
00 AL
rN VAL/U
Load byte At: to VOE'd AX
IN_VAL,
'OPR
IN_oIPB
IN_DIP,
-
DIP,
TABLE
TABLB_LOW
TABLE INC 1. loaded with the
In the incre.ent table at
location AX
IN
Load
of
INC
I Output difference.
Input:dlfference-Incre.ental
I
value
DIPS-Iea.t significant. bits
IN VAL
byte IN_DIYS to word IN_Dlr
I
,
change
I
Add output difference to output
98nerated with truncated IN VAL
as input
Round to 12-blt anaver
Round up if Carry = 1
J
Store
I
B~Anch
I
look
cseg
top of
r¥cr~·et~.~~i:.r;r~i:t~~:OfL by
'1111111 OB
LD
ADDC
to
with Actual Value
the byte by
t •• p
OUT
to
to RESULT
-look:-
2100H
val_table:
DeW
Dew
Dew
Dew
Dew
inc
OOOOH,
5000H,
7BOOH,
5000H,
1000H
2000H,
6AOOH,
7DOOH,
4800H,
]400H,
7200R,
7600H,
34008,
fCOOR
7BOOH
6000H
22008
J
A
~ando.
function
table:
Dew
Dew
Dew
Dew
0200R,
OODOH,
00020H,
OrBEOR,
0140R,
0080H,
OPP908,
Or8908,
0180R,
0060R,
OPp708,
0110H
0030R
Opr008
DPBEOR,
OPBBOR
I Table of tncre.entll
I differences
END
270061-20
Listing 3-3. ASM-96 Code for Table Lookup Routine 2 (Continued)
By making use of the second lookup table, one word of
RAM was saved and 16 state times. In most cases this
time savings would not make much of a difference, but
when pushing the processor to the limit, microseconds
caD. make or break a design.
3.1.2. PL/M-96
Intel provides high level language support for most of
its micro processors and microcontrollers in the form of
PL!M. Specifically, PL/M refers to a family of languages, each similar in syntax, but specialized for the
device for which it generates code. The PL!M syntax is
similar to PL/l, and is easy to learn. PLM-96 is the
version of PL!M used for the 8096. It is very code
efficient as it was written specifically for the MCS-96
family. PLM-96 most closely resembles PLM-86, although it has bit and I/O functions similar to PLM-51.
One line of PL/M-code can take the place of many
lines of assembly code. This is advantageous to the programmer, since code can usually be written at a set
number of lines per hour, so the less lines of code that
need to be written, the faster the task can be completed.
If the first example of interpolation is considered, the
PLM-96 code would be written as shown in Listing 3-4.
Note that version 1.0 of PLM-96 does not support 32bit results of 16 by 16 multiplies, so the ASM-96 procedure "DMPY" is used. Procedure DMPY, shown in
Listing 3-5, must be assembled and linked with the
compiled PLM-96 program using RL-96, the relocator
and linker. The command line to be used is:
RL96 PLMEX1.0BJ, DMPY.OBJ, PLM96.LIB &
to PLMOUT.OBJ ROM (2080H-3FFFH)
6-23
AP-248
/.
LOO~-UP
PLM-96 CODE FOR TABLE
PLMEX:
DECLARE
IN VAL
INTBGER
INTEGER.
INTEGER
DECLARE OUT
INTEGBR
DECLARE
PUBLIC,
PUBLIC,
WORD,
DECLARE TABLE LOW
DECLARB TABLE:HIGH
DECLARE TABLE DIF
-
PUBLIC,
PUBLICr
PUBLIC,
PUBLIC,
PUBLIC,
PUBLIC,
INTEGER
RESULT
DECLARE OUT DIP
DECLARE TEMP
LONG IN'!'
WORO
DECLARE TABLBC171
OOOOH, 2000H,
5000H, 6AOOH,
78008, 7000H,
5000H, 4BOOH,
1000HI,
INTEGER
DA'!'A
34008, teaOR,
72008, 7800R,
7600H,
3400H,
*'
/* A randOM function
6DOOR,
22008,
DMPY,
END
*'
AND INTERPOLATION
DO,
PROCEDURE (A,B) LONGIH'!'
DECLARE (A,B) INTEGERr
DMPYr
BJtTERNALI
LOOP,
TEMP-SHR(IN VAL,.),
/* TEMP 1.
the .ost significant 4 bits of
TABLE LOW-TABLBCTEMPI,
/* If
TABLE:HIGH-TABLB(TEMP+l),
/ . The code would
/* do tvo shifts
-TEMp·
OUT_OIF-OHPYCTABLE_OIF,SIGNEDCIN_VAL AND
OUTmSARI(TABLB_LOW+OUT_DIF),4)J
/*
SAR
in
IF CARRY-O THEN
ELSE
RESULT-OUT,
RESULT-OUT+l,
waa
IN_VAL
replaced by ·SHR(tN VAt,t)·
work
but· the
8096 ;ould
116,
OPHII
pertor.s
this case
an arith.etic right shift,
4 places are< shifted
*/
/* U81ng the hardware flagB .uat be done
/* with care to ensure the flag is tested
/* in the desired inst[ucti~n sequence
GOTO LOOP,
I' BND OF PLH-96 CODE
6/
'/
'/
'I
'I
'I
'I
'/
END;
270061-21
Listing 3-4. PLM-96 Code For Table Lookup Routine 1
$TITLE('MULTeAPT:
16*16 multip\y
SP
procedure
for
PLM-96')
18HtW,ord
r seg
EXTRN
PLMRBG
Iiong
caeg
,
,
Multiply two integers
longint result 1n AX,
,
and return a
DX registers
, Load return address
J Load one operand
Load second. operand a~d 1ncre.ent SP
,
Return
to
PLM
code.
270061-22
Listing 3-5. 32-Bit Result Multiply Procedure For PLM-96
6-24
inter
AP-248
Using PLM, code requires less lines, is mu~h faster to
write, and easier to maintain, but may take slightly
longer to run. For this example, the assembly code generated by the PLM-96 compiler takes 56.75 microseconds to run instead of 30.75 microseconds. If PLM-96
performed the 32-bit result multiply instead of using
the ASM-96 routine the PLM code would take 41.5
microseconds to run. The actual code listings are
shown in Appendix A.
Frequently it is also desired to keep track of the number of events which have occurred, as well as how often
they are occurring. By using a software counter this
feature can be added to the above code. This code depends on the software responding to the change in line
state before the line changes again. If this cannot be
guaranteed then it may be necessary to use 2 HSI lines
for each incoming line. In this case one HSI line would
look for falling edges while the other looks for rising
edges. The code in Listing 3-7 includes both the counter
feature and the edge detect feature.
3.2. Using the 1/0 Section
The uses for this type .of routine are almost endless. In
instrumentation it can be used to determine frequency
on input lines, or perhaps baud rate for a self adjusting
serial port. Section 4.2 contains an example of making a
software serial port using the HSI unit. Interfacing to
some form of mechanically generated position information is a very frequent use of the HSI. The applications
in this category include motor control, precise positioning (print heads, disk drives, etc.), engine control and
3.2_1. USING THE HSI UNIT
One of the most frequent uses of the HSI is to measure
the time between events. This can be used for frequency
determination in lab instruments, or speed/acceleration
information when connected to pulse type encoders.
The code in Listing 3-6 can be used to determine the
high and low times of the signals on two lines. This
code can be easily expanded to 4 lines and can also be
modified to work as an interrupt routine.
$TITLE"PULSBaAPTz
Measuring pulses
usl ng
the
USI
un!
t'
J
$INCLUDEIDEM096.INCl
at
[seg
2BH
HIGH TIME a
LOW TIME:
PERIOD:
HI EDGEI
LO - EDGBI
dB"
dB"
dB ..
dB ..
dBW
-
at
0889
wal
t;
contini
20B08
LD
LOB
LOB
SP, '100B
lOCO, 'OOOOOOOlB
HSI_MODE, '000011118
ADD
JBS
JDC
PERIOD, HIGH TIMB, LON TIME
IOS1, 6, contin
J If rIPO 18 full
1091, "
walt
J Walt while no pulae Ie entered
LOB
LD
hBI
-
10:
- hi.
ST
SOD
DR
ST
SOB
BR
Enable
I
H51
J
8X,
HBI_TIMB
JDB
hal
,
BX.
LO
RSI
0
0 look tor
either edge
Load atatuB, Note that reading
RSI_TIME cl •• ra HSI_STATUS
r
Load the HSI_TIME
,
J
u. p If H S I .0 I a hi 9 h
BDGB
HIGH TIMS,
LO BDGB,
HI
BDGB
waitBX,
HI
BOGB
LON TIME,
w.lt
HI BDGB, LO_BDGB
BND
270061-23
Listing 3-6. Measuring Pulses Using The HSI Unit
6-25
AP-248
transmission control. The HSI unit is used extensively
in the example in section 4.3.
HSO line not change so quickly that it changes twice'
between consecutive reads of I/O Status Register 0,
(IOS0).
3.2.2. USING THE HSO UNIT
A very eye catching example can be made by having the
program output waveforms that vary over time. The
driver routine in Listing 3-10 can be linked to the above
program to provide this function. Linking is. accomplished using RL96, the relocatable linker for the 8096.
Information for using RL96 can be found in the
"MCS-96 Utilities Users Guide", listed in the bibliography. In order for the program to link, the register dec-
Although the HSO has many uses, the best example is
that of a multiple PWM output. This program, shown
in Listing 3-8, is simple enough to be easily understood,
yet it shows how to use the HSO for a' task which can
be complex. In order for this program to operate, another program needs to set up the on and off time variables for each line. The program also requires that a
$TITLE
C'BNNSI.APT.
BNNANCBD NSI
PULSE ROUTINB'I
$INCLUDBCDBN096.INCI
R5BG AT
2 BN
"rIMEa
LAST RISEI
LAST PALLa
NSI SO I
IosI BAIC I
-
PB.RIDDe
LON 'lIMBe
RIGH TIMEr
COUNT.
DBN
DSN
DSN
DSB
DSa
DSN
DSN
DSN
DSN
1
1
1
1
1
1
1
1
1
caeg
at
20BON
i nl t:
LD
SP,Il00R
LDa
IOCl,'OOlOOl018
r
•
waltl
LDB
LDB
N51 MODB,'lOOllOOlB
I OC '0 , • 00000 lllB
.r
,
I
•
.et hal.l -, bal.O +
Enable
bal 0,1
T2 CLOCK-T2CLI, T2RST-T2RST
Clear tlaer2
AND8
ORa
IOSl BAK,'OlllllllB
I05l::BAK,IOSl
Jac
JOS1_BAK,7,valt
,
•
,
r
Clear tOSl BAIC.l
Store into-teap to avoid clearing
other flag_ which •• y be needed
If hal 1& not triggered then
J
juap
ANDa
LD
.IRS
Jas
aR
a rlae;
-
•
DI •• ble 880.4,890.5, HSI tNT-fIrat,
Enable PWM,TXD,TIMBRl_ovivLOW_INT
SUB
SUB
LD
BR
- fall • SUB
SUB
LD
to valt
NSI SO,NSI STATUS,.OlOlOlOlB
,"IMI, HSI_TIME
R81 SO,O,II rill'"
H81-S0,2,.-fall
no_cnt
LOW 'lIMB, '11MB, LAST PALL
PBRIOD, TIMB,LAST RliB
LAST RISB, TIMB
-
increaent
HIGH TIME, TIME, LAST RISE
PERIOD, TIMB,LAST PALL
LAST_PALL, TIMB
-
inete.antl
INC
no
- cnt;
aR
wait
END
270061-24
Listing 3-7. Enhanced HSI Pulse Measurement Routine
6-26
AP-248
$TITLE
I
('HSOPWM.APTI
8096
EXAMPLE
Thi. proqram will provide 1
The input paraMeters passed
RSO
ON
Tl.eB are
N takes
POR
PWM
USO
OUTPUTS')
pine
0-2
ares
RSO on tl_e lor pin N
"SO off time for pin N
N
HSO=OFP_N
Where;
PROGRA"
PMM outputs on
~o
the progr ••
In
tl.erl
values
cycles
fro.
0
to
I J I J I I J I I , I JI I I I , I I J I I I I I I , . J I I I I I JI I J I I
]
r
I J I I I I I , I I I
r r
I I J J I I
$INCLUDEfDEM096.rNC)
RSEG
AT
288
uso
ON
0:
DSW
RSO-OrF 01
USa-ON I I
HSO-OP' 1
OLO-STAT,
NBW=STAT:
AT
eeoC)
2080H
LD
LD
LD
LD
LD
AN DB
KORa
JBS
NOP
SP.II008
HSO ON 0,
•
Set Inltlel value.
Note that tl_es .Ullt
to allow the routine
USO-OPF
1,
1280H
,
line chan"e.
OLD-STAi.
1050,
OLD:STAT,
IOPR
10SO,
6,
be
to
10n'9 enough
run after each
IOPR
I
,
walt
LoOp until
Is e .. pty
HSO
holding
For opperatlon with interrupts 'store a t a t , ' would
entry point of the routine.
Note t h a t . Dr or PUSHP .lght have to be added.
be
regiater
the
stat:
-
check
ANDB
NEN
CMPB
JB
OLO-STAT,
KORB
OLD_STAT,
NBW_STAT
JBC
JBS
OLD
0,
STAT,
1050,
10rli
,Store
atatuB of
I
h •• n't
0:
LDB
ADD
BR
If
atatus
STAT,
NI"=:5,.",.,. 0,
check
1
set_off
HSO COMMAND, 1001100008
HSO-TIME, TIMERI, HSO_OPF
r
Set 1150 for t t . e r l , set pin 0
"1'1 •• to set p i n · Tiaerl value
+ Till. for pin to be low
I
I
Set H50 for tlaerl, clear pin 0
Tl.e to clear pin ~ Tlaerl value
0
check_l
LDB
ADD
HSO COMMAND, 1000100008
HSO=TIME, TIMERI, HSO_ON
J BC
J as
OLD STAT,
NEW:STAT,
0
+ Tille for
set_on
changed
0:
off
'check
HSO
N8W_STAT
.. att
0:
set_on
set
,lOOH
Rso-orF 0, '400H
I, 1280H
RSO-ON
J
store
DSW
DSW
DSW
dab
dab
pin
to be high
1;
1:
LOB
ADD
BR
1,
1,
check
done
.et_olf_l
100110001B
HSO-TIME, TIMERI, HSO orr I
-
H50 COMMAND.
J
J
HSO COMMAND. 100010001B
HSO:TIME, TIMBal, HSO_ON
check done:
LDB
r
J
Set 880 tor tl •• rl,
Tl •• to cle.r ptn •
cl •• r pln I
Ti •• rl valu.
+ TI •• for pin to b. hlgh
J
I
8a
Set HSO for tt •• rl, •• t pin I
to eet pin - Tlaerl v.lue
Tlae
check_done
valt
r uee RBT If ·walt- la called froa
Store current atatu. and
valt for Interrupt fla9
another routine
BND
270061-25
Listing 3-8. Generating a PWM with the HSO
6-27
AP-248
quency twice that of the first one. A slightly different
driver routine could easily be the basis for a switching
power supply or a variable frequency/variable voltage
motor driver. The listing of the driver routine is shown
in Listing 3-10.
laration section (Le., the section between "RSEO" and
"eSEOn ) in Listing 3-8 must be changed to that in
Listing 3-9.
The driver routine simply changes the duty cycle of the
waveform and sets the second HSO output to a freNOTE:
Use
this
tLle
to
replace ,the declaration
the HSO PWM prograa
aectlon of
-,INCLUDE(DEH096.INC)- throuqh
froM
the line prlor to the
branch in the proqr ••
label ·wait-.
to a -RET-,
A180 change the
.
last
RSEG
D STA't1
extrn
extrn
extrn
extrn
DSB
extrn
public
OLD_STAT
OLD
aword
- -
HSO ON 0
RSO ON 1
HSO:TIME
TIMERl
SP
aword
,wotd
Iword
1
,
,
,
RSO OPF 0 .word
RSO - OFP - 1 =vord
RSO COMMAND Ibyte
IOSO
:byte
-
:word
STAT;
dab
NEW:S,.,.T I
dab
cseq
PUBLIC
wait
270061-26
Listing 3-9. Changes to Declarations for HSO Routine
$TITLEI'HSODRV.APT.
Driver Module for
MODULB
HSODRV
PUBLIC
PUBLIC
PUBLIC
PU BL IC
HSO PWM program')
MAlN, STACKSIIBI8)
HSO ON 0 , HSO OFP a
HSO-ON-l , H80-0PP"1
HSO-TIME , RSO"COMMAND
SP ; TIMERl , 1050 1
$INCLUDEIDEH09fi.INC)
t8eg
at
288
Ibyte
EXTRN
a.
HSO-Orr as
HSO ON
8S0-0N
II
HSO-Orr 11
count; cee9
at
4sb
valt
rentry
01
1 n 1 t 1.1
loopa
daw
dew
dew
2080H
EXTRN
stetl
dBW
LD
ANDB
XORB
SP, 1100H
OLD STAT, 1080, 10FB
OLD::STAT, 10PR
LD
CX.
LD
SUB
LD
AX, 11000H
BX, AX, CX
AX, ex
ST
ST
AX, H90_0N_O
BX, HSO_OrF_O
I
10100H
270061-27
listIng 3-10. Driver Module for HSO PWM Program
6-28
intJ
AP-248
SUR
SUR
ST
ST
AX,' )
CALL
WG
INC
CHP
ON E
ex
CX,
DR
1 n 1 t 1 II 1
OX,ll
AX, USO ON 1
ox, USO OPF 1
-
-
1t
IOOFOOU
loop
END
270061-28
Listing 3-10. Driver Module for HSO PWM Program (Continued)
Since the 8096 needs to keep track of events which often repeat at set intervals it is convenient to be able to
have Timer 2 act as a programmable modulo counter.
There are several ways of doing this. The first is to
program the HSO to reset Timer 2 when Timer 2
equals a set value. A software timer set to interrupt at
Timer 2 equals zero could be used to reload the CAM.
This software method takes up two locations in the
CAM and does not synchronize Timer 2 to the external
world.
Another option available is to use the HSI.l pin to
clock Timer 2. By using this approach it is possible to
use the HSI to measure the period of events on the
input to Timer 2. If both of the HSI pins are used
instead of the T2RST and T2CLK pins the HSIO unit
can keep track of speed and position of the rotating
device with very little software overhead. This type of
setup is ideal for a system like the one shown in Figure
3-1, and similar to the one used in section 4.3.
In this system a sequence of events is required based on
the position of the gear which represents any piece of
rotating machinery. Timer 2 holds the count of the
number of tooth edges passed since the index mark. By
using HSl.l as the input to Timer 2, instead of T2
CLK, it is possible to determine tooth count and time
information through the HSI. From this information
instantaneous velocity and acceleration can be calculated. Having the tooth edge count in Timer 2 means
To synchronize Timer 2 externally the T2 RST (Timer
2 ReSeT) pin can be used. In this way Timer 2 will get
reset on each rising edge of T2 RST. If it is desired to
have an interrupt generated and time recorded when
Timer 2 gets reset, the signal for its reset can be taken
from HSI.O instead of T2RST. The HSI.O pin has its
own interrupt vector which functions independently of
the HSI unit.
HSI.1 OR T2CLK
TIMER 2 HOLDS TOOTH COUNT
HSI MEASURES PULSE PERIOD
l-~----HSI.O OR T2RST
RESETS TIMER 2 AND/OR
CAUSES INTERRUPT
270061-29
Figure 3-1. Using the HSIO to Monitor Rotating Machinery
6-29
AP-248
transmits the same character. The code is set up so that
minor modifications could make it run on an interrupt
basis. Note that it is necessary to set up some flags as
initial conditions to get the routine to run properly. If it
was desired to send 7 bits of data plus parity instead of
8 bits of data the PEN bit would be set to a one. Interprocessor communication, as described in section 2.3.4,
can be set up by simply adding code to change RB8 and
the port mode to the listiQ,g below. The hardware
shown in Figure 3-2 can be used to convert the logic
level output of the 8096 to ± 12 or 15 volt levels to
connect to a CRT. This circuit has been found to work
with most RS-232 devices, although it does not conform to strict RS-232 specifications. If true RS-232
conformance is required then any standard RS-232
driver can be used.
that the HSO unit can be used to initiate the desired
tasks at the appropriate tooth count. The interrupt routine initiated by HSI.O can be used to perform any software task required every revolution. In this system, the
overhead which would normally require extensive software has been done with the hardware on the 8096,
thus making more software time available for control
programs.
3.2.3. USING THE SERIAL PORT IN MODE 1
Mode 1 of the serial port supports the basic asynchronous 8·bit protocol and is used to interface to most
CRTs and printers. The example in Listing 3·11 shows
a simple routine which receives a character and then
$TITLE('SP.APTI SERIAL PORT DEMO PROGRAM t
)
$INCLUOEIOEM096~I~CI
rseg
at ZIU
CHR:
dab
SPTEMP: dab
TEMPOs
dab
, TEMPI:
dab
ReV_FLAG.
caeg
caeg
dab
at 20UCH
at 20808
LO
SP, 'lOOH
LOB
IOC1. '00100000B
, Set '2.0 to
~XD
, Baud rate. input frequency I ('.-baud val)
• baud_val
• (Input frequency/'.) / baud rate
BAUD HIGH
BAUO=LOW
,
39 •
(12,000,000/'4),4.00 baud
equ
39
equ
equ'
Ilboud vol-ll/2S61 OR 10H
Ibaud.vol-ll MOD 256
LOB
LOB
BAUD RBG. 'BAUD LON
BAOO:RBG, IBAUO:HIGH
LOB
SPCqN, ,o10010018
,
, Set MS8 to 1
Bnable receiver, Hode 1
r The aerial port Is now initialized
seup, eHR
S'1'B
LOB
TEMPO. 'OOlOOOOOB
LOB
IN".MASK. 'OlOOOOOOB
r C1.ar .erla1 Port
r Set TI-te.p
r Enable Serial Port Interrupt
BI
loop:
BR
loop
J
Walt for a.rlal port interrupt
ser port inti
•
PUSHF
I'd agalnl
.
LOB
ORB
ANDB
JNB
SPT!MP, SPSTAT
.,EMPO, SPT!MP
• Thi. aectlon of code can be replaced
TEMPO, SP STAT-' when the
• .erlal port 71 and Rt bug8 are fixed
• vl th ·ORB
SPTEMP.'OllOOOOOB
r4_agatn
• Repeat until TI and RI are properly cleared
270061·30
Listing 3-11. Using the Serial Port in Mode 1
6-30
intJ
AP-248
get by tel
-
TEMPO, 6, put byte
JDe
STB
AN DB
TEMPO, .101111118
I eLR AI-temp
LOB
Rev _FLAG,
J
SOUP,
CUR
I If RI-te.p is not Bet
I Store byte
-
IOFFH
Set bit-received flag
put byte:
-
JDe
ANDB
Rev FLAG, 0, continue
continue
SOUP, CHR
TEMPO, '110111118
"NOB
CHA,
JBC
L08
TEMPO,S,
CHR,IODH
cir rey
LOB
CHR-; 10AH
8R
continue
CLRB
Rev _FLAG
CHPB
I
If TI vas
Send by to
I eLR
~I-
not set
tellp
I This aectlon of code appends
J an LP after a eR Is sent
,OIII1111B
JHE
I If receive flA9 Is cleared
I
clr reva
I Clear bit-received flag
continuel
POPF
RET
END
270061-31
Listing 3-11. Using the Serial Port in Mode 1 (Continued)
RXD
-
VCC
02,03
R2-R6
.....
= 1N914
= 1800 n
R3
VCC
-rR2
TXD
~
T1
2N2907
XMITDATA
R6
(TO RS232 PIN 3)
~
,
R4
RCV DATA
02
.... ,
RS
...-.
':::
~
C1
T2
2N2222
J~ 01
110 P
RCV DATA
(FROM RS232 PIN 2)
'---~
SIGNAL GROUND (RS232 PIN 7)
~
Figure 3-2. Serial Port Level Conversion
6-31
270061-32
intJ
AP-248
really make use of its full capabilities. The following
examples use some of the code blocks from the previous
section to show how several I/O features can be used
together to accomplish a practical task. Three examples
will be shown. The first is simply a combination of several of the section 3 examples run under an interrupt
system. Next, a software serial port using the HSIO
unit is described. The concluding example is one of interfacing the HSI unit to an optical encoder to control a
motor.
.
3.2.4. USING THE A TO D
The code in Listing 3-12 makes use of the software flags
to implement a non-interrupt driven routine which
scans A to D channels 0 through 3 and stores them as
words in RAM. An interrupt driven routine is shown in
section 4.1. When using the A to D it is important to
always read the value using the byte read commands,
and to give the converter 8 state times to start converting before reading the status bit. .
Since there is no sample and hold on the A to D converter it may be desirable to use an RC filter on each
input. A lOOn resistor in series with a 0.22 uf capacitor
to ground has been used successfully in the lab. This
circuit gives a time constant of around 22 microseconds
which should be long enough to get rid of most noise,
without overly slowing the A to D response time.
4.1. Simultaneous 1/0 Routines under
Interrupt Control
A four channel analog to PWM converter can easily be
made using the 8096. In the example in Listing 4 analog channels are read and 3 PWM waveforms are generated on the HSO lines and one on the PWM pin.
Each analog channel is used to set the duty cycle of its
associated output pin. The interrupt system keeps the
whole program humming, providing time for a background task which is simply a 32 bit software counter.
To show which routines are executing and in which
4.0 ADVANCED SOFTWARE
EXAMPLES
Using the 8096 for applications which consist only of
the brief examples in the previous section does not
$TITLE('ATOD.APT:
SCANNING THE
A TO
0
CHANNELS')
$INCLUDE(DEM096.INCI
RSEC
.t
28u
BL
DL
RESULT
TABLE:
EOU
EOU
8XIBYTE
DX1BYTE
.
d."
dB"
d."
d."
- i2..
-]
RESULT - 4.
-
RESULT
RESULT
RESULT
cseg
start:
n ex t,:
at
2080H
LO
SP,
C!.R
!!!
'lOOH
Set Stack
1.008
,
NOP
NOP
check:
J
Wait
I
Start
J
indicated
for' conversion
JOS
AD
LOB
AL,
AH,
AD_REBULT_LO
AD_RBSULT_HI
ADOB
LDBZE
CL,
BL,
OX,
DL
ST
AX,
RESULT
INCB
ANDB
BL
BLf
BR
nex t
Loa
RBSULT_LO,
Pointer
3,
check
,
to
Walt
conversion on channel
by BL register
start
while
A to
D is
busy
Load low order result
Load high order result
BL
'I'ABLB(DX}
,
•
Stoce
result
Incce.ent BL aodulo
lndexed
by BL-2
4
f038
END
270061-33
Listing 3-12. Scanning the A to D Channels
6-32
AP-248
order, Port 1 output pins are used to indicate the current status of each task. The actual code listing is included in Appendix B.
be waited between consecutive loads of the HSO. If this
is not done it is possible to overwrite the contents of the
CAM holding register. An AID interrupt is forced by
setting the bit in the Interrupt Pending register. This
causes the first AID interrupt to occur just after the
Interrupt Mask register is set and interrupts are enabled.
The initialization section, shown in Listing 4-1 a, clears
a few variables and then loads the first set of on and off
times to the HSO unit. Note that 8 state times must
Listing 4-1. Using Multiple 1/0 Devices
$TITLE
('8096
EXAMPLE
PROGRAM
POR
PHM
OUTPUTS
PWH
outputs
FROM
A TO
0
INPIJTS')
$PAGEWIDTH (110)
J
This
progrAm
and
on
The
PHM
",ill
the
values
; J III III II J I
r
provide
J
on
lisa
pins
0-2
PWH.
are
determined
by
the
input
I J I I I I 1 1 1 1 1 1 . , 1 1 1 1 1 1 1 1 1 J I"
r
to
the
Aln
converter.
II II I . J I J I I I I 1 I I I I I
$INCLUDE(OEH096.INC)
RSEC
AT
28U
DL
ON
EOU
DX,BYTI!!
TIME:
RESULT
PHH TIME I.
HSO-ON 01
HSO-ON-l:
D8W
D8W
D8W
H50:0N=2.
DSW
TABLE.
DSW
OS"
DSW
DSIi
RESULT 0:
RESULT-I:
RESULT-Z:
RESULT:):
NXT
ON T:
NXT-Ol"P
0;
NXT-OFY-l,
NXT-or'-2.
COUNT:
-
HSD_PERr
LAST
c8eg
AT
LOAD:
J
Channel
belnq
converted
DS8
2000H
start
Atod done lnt
start
HSO exec lnt
. DeW
DCIi
DCW
Dew
cseg
AT
start:
LD
SP,
CL.
DEC
AX
AX
JNE
wai t
wldt:
DSW
DSIi
,DSW
DSW
DSL
DSW
DSIi
DSW
I
Tlaer_ovf_lnt
I
H5I_data_lnt
2080H
1100H
I
Set
Stack
Polnte~
wal t approx. 0.2 8econds foc
S8E to finish co •• unlcatlona
CLR8
LD
LD
LD
LD
LD
PHM TIME
1,
1080H
USO-PER, -IIOOH
IISO-ON 0, 1040"
HSO-ON-i, ,OOOH
HSO=ON=2, ,OeOl1
270061-34
Listing 4-1a. Initializing the A to D to PWM Program
6-33
AP-248
LD.
LD
NOP
NOP
LD.
ADD
USO COMMAND, '001101108
HSO:TIME, NXT_ON_T
Set HSO for tl.erl,
with interrupt
aet pin
0,1
HSO COMMAND. '00100010.
HSO=TIME, NXT_ON_T
Set uso tor tl.erl,
without interrupt
set pin
2
ORO
LAST
LDB
LOAD, '000001118
tNT MASK, 1000010108
,Last loaded value WBS Bet all pins
,Bnable Rsa and AID interrupts
LDB
INT:PENDING,
J
Pake
I
Bet Pl.0
,
clear
'000010108
an
AID
and
uso
t nt'errupt
Et
loopl
ORB
ADD
portl,
COUNT.
ADDe
COUNT+2,zeto
'000000018
'01
ANDB
BR
Portl,
loop
.111111108
P1.0
270061-35
Listing 4-1a. Initializing the A to 0 to PWM program (Continued)
" " 1 1 1 ' , , I I I I J I " '"
, , , " , , " , , " " " " "1'"
,,," ""'111
1'" ",,'."11,'"
':1;""""""
USO
EXECUTED
INTERRUPT
",1"""1""",,,1
J 1111"'1" 11111111111'11"""
""" """""1""""".",11, ""l ",,11
I
uso exec tntl
PUSHF
ORB
pottl,
SUB
CMP
TMP,TIMERl, NXY ON T
TMP,ZERO
set_off_tlaes
JLT
set_on
tilles:
ADD
LDB
LD
NOP
NOP
LD.
LD
ORB
,
.000000108
Set pl.l
NXT ON T, HSO PER
HSO-COMMAND. 100110110B
HSO:TIME, NXT_ON_T
I
Set RSO fot
tillet!,
set pin
0,1
"SO COMMAND,
1001000108
HSO:TIME, NXT_ON_T
J
Set HSO for
tilletl,
set pin
2
LAST_LOAD.
I
Last
'000001118
loaded value vas
all
one a
Nov is as good a tl.e as
I to update the PMM teg
I
set
off
ti.e81
Joe
LAST_LOAD,
ADD
LD
NXT OFr 0, NXT ON T, HSO ON_O
HSO-COMMAND, .00010000B
I
HSO:TIME, NXT_OFF_O
NOP
ADD
LOB
LO
iSO-TIMB,
NOP
ADD
LOB
LO
NXT OPF 2, NXT ON T, HSO ON 2
RSO-COMMAND. ,00010010B HSO:TIME, NXT_OFF_2
ANDB
LAST LOAD,
LOB
check
~ny
0,
check_done
NXT OFr 1, NXT ON T,
USO ON 1
- I
USO-COMMAND, '000100018
N~T OPF 1
1111110009
I
La'st
Set HSO fot
tilletl,
clear
pin
Set RSO fol'
tillel'l,
clear
pin
Set usa fot
loaded
timerl,
value was
cleat
pin
2
alIOs
done:
ANDB
Portl,
'1~1111018
,
Clear
PI.l
PO PF
RET
270061-36
Listing 4-1b.lnterrupt Driven HSO Routine
6-34
intJ
AP-248
1, •• , ,","",,",,,,, """"1"1"",,,,1,,,"'111,"'" III ,,""""",,,,
A TO 0
COMPLETE
INTERRUPT
1II"".r""",.,.
11"""""" """,,"," ',JJII.""""""""""""" ,,,,,,""""",,
"II'JII,J"""
ATOD
done
-
intI
POSHP
ORB
J
Set
Pl.]
CNPB
AL,
LDBIB
next:
1000001008
ST
LOB
ADDB
no_rnd.
PottI,
, Load low order result
AL, AD RESULT LO,I11000000B
I Load high order reBult
AH, AD-RESULT-HI
DL, AD-NUM, AD NUH
J DL- AD_NUM -2
OX, DL, Store reBult Indexed by OX
AX, RESULT_TAaLE(DXI
AMOB
101000000B
JNH
no
CMPB
JE
AH;'OPPR
no rnd
rnd
I
INCB
AR-
LDB
AL,
CLRa
ST
AR
AX, ON_'rINB(DX)
INca
ANDa
AD HUN
ADDa
AD_COMMAND,
ANDB
POPP
RBT
PortI,
AU
AO:NUM,
Round
,
Don't
,
Align byte
1038
J
AD NUH,
up
lnere.ent
and
if needed
If AR-o,rH
change
Keep AD_NUM
'1000D
J
Start
to word
between 0 and J
conversion
on channel
I indicated by AD NUM register
,11111011B
r Cleat
Pl.2
-
BND
270061-37
Listing 4-1c.lnterrupt Driven A to D Routine
The HSO routine shown in Listing 4-1b is slightly different than the one in section 3, All of the HSO lines
tum on at the same time, only the tum-ofT-time is varied between lines. This action is what is most commonly required for multiple PWM outputs and simplifies
the software. A comparison is made between Timer 1
and the next HSO tum on time at the beginning of the
routine. If the next tum on time has passed, then the
on-times are loaded into the CAM, otherwise the ofT
times are loaded,
The maximum number of events in the CAM at any
given time is 7. This occurs when the first line to tum
ofT does so, causing the ofT-times for all of the lines to
be loaded. For two of the lines there will be an offiime,
an on-time, and the just loaded ofT-time. The other line
(the one that just turned oft) will have only the on-time
and the just loaded ofT-time.
AID conversions ar~ performed by the code in Listing
4-1c about every 60 microseconds, 42 for the conversion, the rest for overhead, The AID routine sets up the
HSO and PWM on and ofT times. Since the AID
has a ten bit output, the most significant 8 bits are
rounded up or down based on the least significant two
bits.
4.2. Software Serial Port Using the
HSIO Unit
There are many systems which require more than one
serial port, an example is a system which must communicate with other computers and have an additional
port for a local console, If the on-board UART is being
used as an inter-processor link, the HSIO unit can be
used to interface the 8096 to an additional asynchronous line.
Figure 4-1 shows the format of a standard lO-bit asynchronous frame. The start bit is used to synchronize the
receiver to the transmitter; at the leading edge of the
START bit the receiver must set up its timing logic to
sample the incoming line in the center of each bit. Following the start bit are the eight data bits which are
transmitted least significant bit first. The STOP bit is
set to the opposite state of the START bit to guar-
6-35
inter
Ap·248
STOP
270061-38
Figure 4·1. 10·bit Asynchronous Frame
antee that the leading edge of the START bit will cause
a transition on the line; it also provides for a dead time
on the line so that the receiver can maintain its syn·
chronization.
3. Transmit ISR. This routine runs as an ISR (interrupt
service routine) in response to an HSO interrupt in"
terrupt. Its function' is to serialize the data passed to
it by the interface routines.
4. Receive ISRs. There are two ISRs involved in the
receive process. One of them runs in response to an
HSI interrupt and is used to synchronize the receive
process at the leading edge of the start bit. The second receive.ISR runs in response to an HSO generat~
ed software timer interrupt, this routine is scheduled
to run at the center of each bit and is used to deseri7
alize the incoming data.
The remainder of this section will show how a full-duplex asynchronous port can be built frQm the HSIO
unit. There are four sections to this code:
1. Interface routines. These routines provide a procedural interface between the interrupt driven core of
the software serial port and the remainder of the application software.
'2. Initialization routine. This routine is called during
the initialization of the overall system and sets up the
various variables used by the software port.
VARIABLES NEEDEO BY
The routines share the set of variables that are shown in
Listing 4-2. These variables should be accessed only by
the routines which make up the software serial port.
THE SOFTWARB SBRIAL
PORT
(seg
reve atate:
[xrdy
(xaverrun
rip
-
reve b uf I
rcve _reg:
sa.ple ti.e
seri al
- out:
baud co un t
txd
- time,
I
I
,
dab
equ
equ
equ
d.b
dab
d ...
indicatea receive done
indicatea receive overflow
receive in progress flag
used to double buffer receive data
uaed to 'de8erlallze recelve
recorda last receive a •• ple tia.
d ... 1
Holda the output character+fr •• lng (atart
atop bits) for tran •• l t pr?Ce88.
Holda the perlod of one bit In units
of 71 ticke.
T,ranaltlon tias of last Txd bit that"wa.
sent to the CAM
for tea.t only
d ... 1
dB .. 1
dab 1
char:
COMMANDS
.ark coamand
space co •• and
sa_Ple_co •• and
ISSUED
equ
equ
equ
~O
~HB
and
RBO UNIT
OllOlOlb
OOlOlOlb
OOllOOOb
• tl.~rl,8et,lnt.rruPt on
, tt •• clrele,lnterrupt on
f
Boftware
tiaer
0
$eject
270061-39
Listing 4·2. Software Serial Port Declarations
6-36
infef
AP-248
The table also shows the declarations for the commands issued to the HSO unit. In this example HS1.2 is
used for receive data and HSO.5 is used for transmit
data, although other HSI and HSO lines could have
been used.
stored the START and STOP bits are added to the data
bits. The routine char-in is called when the application software requires a character from the port. The
data is returned in the ax register in conformance to
PLM 96 calling conventions. The routine csts can be
called to determine if a character is available at the port
before calling char_in. (If no character is available
char_in will wait indefinitely).
The interface routines are shown in Listing 4-3. Data is
passed to the port by pushing the eight-bit character
into the stack and calling char_out, which waits for
any in-process transmission to complete and stores the
character into the variable serial_out. As the data is
The initialization routine is shown in Listing 4-4. This
routine is called with the required baud rate in the
I
char outl
I Output character
"a 1 t
pop
pop
Idb
add
for x.l t
-CliP
cats
ext
software aerial
0'
wait for aerial out-O (I t "Ill be cleared by
the heo interrupt process)
put the tor.atted character 1 n aerial - out
[eturn to caller
aortal out,
walt for •• 1 t
bx,aerial_out
(ex I
(8X<>0)
if
port
the return address
output
the character f
add the start and atop bi to
to the char and leave aa 16 bit
I
I
I
°
I
-true-
c 1r
bbe
inc
the
b.,bx
bne
at
b,
csta:
I Returns
to
ex
bx
(bx'l),IOlh
I
I
char_in haa
a character.
ax
rcve_state,O,cata_exlt
ax
tl
,et
I
char in:
, Get a character
tro.
the software
aerial
I walt for
bbe
reve
-
at.te,O,char In
,-set up a
atate,'not(rxrdy)
pushf
andb
reve
Idbze
al,rcve_buf
popf
ret
I
leave
port
character
cri tical
the
critical
ready
re9ion
reglon
270061-40
Listing 4-3. Software Serial Port Interface Routines
setup serial port~
I Called on iyste.
pop
pop
Id
Id
dlvu
at
at
idb
bbe
add
idb
Id
clrb
cltb
clrb
call
br
reBet
to
lntlate
ex
bx
dx.I0007h
ax"OA120h
IX, bx
ax,baud count
O'.aerlaI out
locl,.OllOOOOOb
10aO,6,$
r
r
the
software
aerlal
port.
,
the return addreBs
the b~ud rate (In declaal)
dX'8K,-500,000 lalau.es 12 Mhz
,
calcul.te
•
clear
the baud count
•• r l . l
crystal)
(500,OOO/baudrate)
out
r Bn.ble H50.5 and Txd
I Walt for roo. In the HSO CAM
• and la.ue • MARK eo •• and.
txd tla.,tlaerl,20
h.o-eo •• and •••• rk· co •• and
hao-tla.,txd tla.reve_but
,clear out the receive variables
reve reg
reve-.tate
lnlt-recelve
J setup to detect a atart bit
(exlJ return
270061-41
Listing 4-4. Software Serial Port Initialization Routine
6-37
intJ
, AP-248
stack; it calculates the bit time from the baud rate and '
stores it in the variable baud_count in units of
TIMERI ticks, An HSO command is issued which will
initiate the transmit process and then the remainder of
the variables owned by the port are initialized. The routine init_receive is called to setup the HSI unit to look
for the leading edge of the START bit.
nificant bit is output and the register shifted right one
place. The framing information (START and STOP
bits) are appended to the actual data by the interface
routines. Note that this routine will be executed once
per bit time whether or not data is being transmitted. It
would be possible to use this routine for additional low
resolution timing functions with minimal overhead.,
The transmit process is shown in Listing 4-5. The HSO
unit is used to generate an output command to the
transmit pin once per bit time. If the serial_out register is zero a MARK (idle condition) is output. If the
serial_out register contains data then the least sig-
The receive process consists of an initialization routine
and two interrupt service routines, hsi_isr and
software_timer_isr. The listings of these routines are
shown in Listings 4-6a,4-6b, and 4-6c respectively. The
•
haG 1.,;
, Frelds the haa interrupti and perfor •• the a.rializ.tion of the data.
I Note, this routine would be lncorpora~ed Into the haG'service atrategy for
. actual .yat ••.
caeC)
dew
caaC)
pu.hl
odd
ClOp
be
ahr
be
Bend
an
r Set up vector
txd tia.,baud count
aeri.l out,O I If
character
1. done
sen4 a .ark
lend • • C'k
aerial out"t
Bend_8ark
, e l •• aend btt 0 of leria1 out and shift
,I.rtal_out left one place.
apace.
Idb
Id
br
Bend .arka
Idb
Id
haG co •• and,tepee. co ••• nd
haa-tia.,txd tia. hao:lal'_exithaG co •• and, •• ark co •• and
hao:tiae,tx4_tl •• -,
heo_ler exit.
popf
ret
$eject
270061-42
Listing 4-5. Software Serial Port Transmit Process
Listing 4-6. Receive Process
•
Inlt receivel
I
Carled to prepare
~
a atart bit.
Idb
Idb '
flush fifol
orb
bbc
14b
1d
andb
br
flush fifo 40ne.
Idb
ret
the aerial
input proceaa
locO.IOOOOOOOOb
hal __ ode"OOlOOOOOb
to find
leading edge of
disconnect change detector
negative edgee on HSI.2
10801 •• ve,loal
loal- •• ve,7,fluah fifo done
al,hel atatuB
ax,hal-ti..
, tra.h the
1081 .ive,Inot(80h)
I
clear bit
flush_fifo
locO.IOOOIOOOOb
the
rlfo entry
7.
connect HSI.2
to detector
270061-43
listing 4-6a. Software Serial Port Receive Initialization
6-38
inter
Ap-248
,
h
B
lis r :
Frelds
J
of
J
Note:
interrupts
the
START
this
frail
the R51
unit,
used
to detect
the
leading
edge
bi t
routine
would
be
incorporated
Into
the
USI
strategy
of
I
setup
the
interrupt
11.1,4 ,eil t h a i
10110,7,$ -
J
walt
ax,baud count
ax,II
-
I send out sample co.mand
I bit tillle
an
actual
system.
caeg
at
200Ch
de,",
hal_lsr
vector
caeg
push!
o.
pua h
al,hal statUIl
sample-time,hal
ldb
ld
bbc
bb.
ld
shr
add
ldb
at
ldb
ex 1 t
a •• ple
tl~e
for
(OOID
nso holding reg
in 1/2
tille,ax
hao co •• and,laample comlland
aample tille,haD time
locO,IOODOODOObI
disconnect
hs 1 :
pop
1n
hsl.2
from
change detector
ax
pop!
ret
270061-44
Listing 4-6b. Software Serial Port Start Bit Detect
software timer lacl
I
Flelds-the software
I
I
Note:
in an
cseg
dcw
at
cBeg
pushf
orb
andb
andb
bne
process
B to r t
bbc
call
br
atart OkE
orb
br
200ah
software
interrupt,
be
used
incorporated
timer_isr
iosl a.ve,ioa1
ioal-save,lnot(Olh)
O,rcve state,'Orch
process data
bi t,
hat atatuB,S,start ok
init receive
software_timer_exit
reve atate,trip
schedule_sample
process data.
bbs
ahrb
bbc
orb
datazero:
oddb
br
check
timer
this routine would
actual system.
,
Bet
to deserialize the IncommlRg data.
into the software timer stategy
I
setup vector
,
c1e,ar bit 0
All bita except
I
receive
in progress
reve atate,7,eheek atopbit
reve-reg,ll
hai BtatuB,S,datazero
reve_reg.,80h
I sot the new data
rcve state,IIOh
schedule_sample
I
rxrdy and overrun-O
flag
bit
increment bit count
stopbit:
Idb
orb
andb
call
br
hsi atatua,S,$
I DEBUG ONLY
reve buf,reve reg
rcve-state"rxrdy
reve-utate,I03h I Clear all but ready
init-receive
software_timer_exit
sa_plel
bbs
Idb
add
at
iosO,7,$
I wait for holding
hso co •• and,lsaaple co •• and
aaaple time,baud count
aamp1e:tl.e,hso_time
bbc
schedule
software
tiller
reg
and overrun bita
e.pty
exitE
popf
ret
270061-45
Listing 4-6c. Software Serial Port Data Reception
6-39
AP-248
start is detected by the hsi_isr which schedules a software timer interrupt in one-half of a bit time. This first
sample is used to verify that the START bit has not
ended prematurely (a protection against a noisy line).
The software timer service routine uses the variable
rcve_state to determine whether it should check for a
valid START bit, deserialize data, or check for a valid
STOP bit. When a complete character has been received it is moved to the receive buffer and in it_receive
is called to set up the receive process for the next character. This routine is also called when an error (e.g.,
invalid START bit) is detected.
Appendix C contains the complete listing of the routines and the simple loop which was used to initialize
them and verify their operation. The test was run for
several hours at 9600 baud with no apparent malfunction or the port.
4.3. Interfacing an Optical Encoder to
the HSI Unit
Optical encoders are among one of the more popular
devices used to determine position of rotating equipment. These devices output two pulse trains with edges
that occur from 2 to 4000 times a revolution.
Frequently there is a third line which generates one
pulse per revolution for indexing purposes. Figure 4-2
shows a six line encoder and typical waveforms. As can
be seen, the two waveforms provide the ability to determine both position and direction. Since a microcontrolleI" can perform real time calculations it is possible to
determine velocity and acceleration from the position
and time information.
Interfacing to the encoder can be an interesting problem, as it requires connecting mechanically generated
electrical signals to the HSI unit. The problems arise
because it is difficult to obtain the exact nature of the
signals under all conditions.
The equipment used in the lab was a Pittman 9400 series gearmotor with a 600 line optical encoder from
Vernitech. The encoder has to be carefully attached to
the shaft to minimize any runout or endplay. Fortunately, Pitmann has started marketing their motors
with ball bearings and optical encoders already installed. It is recommended that the encoder be mounted
to the motor using the exact specifications of the encod'er manufacturer and/or a good machine shop.
CLOCKWISE
PHASEA~
OPTICAL
CHOPPER
ENCODER
DISK
PHASEB~
COUNTERCLOCKWISE
PHASEA~
PHASEB~
270061-46
Inside track generates Phase A. Outside track generates Phase B.
Figure 4-2. Optical Encoder and Waveforms
6-40
intJ
AP-248
Digital filtering external to the 8096 is used on the encoder signals. The idealized signals coming from the
encoder and after the digital filter are shown in Figure
4-3. The circuitry connecting the encoder to the 8096
requires only two chips. A one-shot constructed of
XOR gates generates pulses on each edge of each signal. The pulses generated by Phase A are used to clock
the signal from Phase B and vice versa. The hardware is
shown in Figure 4-4. CMOS parts are used to reduce
loading on the encoder so that buffers are not needed.
Note that T2CLK is clocked on both edges of both
filtered phases.
If it is desired to determine when each edge occurs before filtering, the encoder outputs can be attached directly to the 8096. As these would be input signals, Port
o is the most likely choice for connection. It would not
be required to connect these lines to the HSI unit, as
the information on them would only be needed when
the motor is going very slowly.
The motor is driven using the PWM output pin for
power control and a port pin for direction control. The
8096 drives a 7438 which drives 2 opto-isolators. These
in turn drive two VFETs. A MOV (Metal Oxide Varistor, a type of transient absorber) is used to protect the
VFETs, and a capacitor filters the PWM to get the best
motor performance. Figure 4-5 shows the driver circuitry. To avoid noise getting into the 8096 system, the
± 15 volt power supply is isolated from the 8096 logic
power supply.
By using this method repetitive edges on a single phase
without an edge on the other phase will not be passed
on to the 8096. Repetitive edges on a phase can occur
when the motor is stopped and vibrates or when it is
. changing direction. The digital filtering technique causes a little more delay in the signal at slow speeds than
an analog filter would, but the simplicity trade off is
worthwhile. The net effect of digital filtering is losing
the ability to determine the first edge after a direction
change. This does not affect the count since the first
edge in both directions is lost.
This is the extent of the external circuitry required for
this example. All of the counting and direction detection are done by the 8096. There are two sections to the
example: driving the motor and interfacing to the encoder. The motor driver uses proportional control with
REVERSE
FORWARD
PHASE A
PHASE B
PHASE A'
PHASE B'
PHASE A'
-.JII.....__..
--------------------------------~.,
XOR PHASE B
270061-47
NOTES:
Phase A' is Phase A clocked by Phase 8
Phase 8' is Phase 8 clocked by Phase A
Figure 4-3. Filtered Encoder Waveforms
6-41
AP-248
some modifications and a braking algorithm. Since the
main point of this example is I/O interfacing, the motor driver will be briefly described at the end of this
section.
In order to interface to the encoder it is necessary to
know the types of waveforms that can be expected. The
motor was accelerated and decelerated many times using different maximum voltages. It was found that the
0
PHASE
A.
PHASE B'
HSIO,l
Q
D-nCLK
0
PHASE B
HS12.3
Q
PHASE A'
270061-48
Figure 4-4.,Schematic of Optical Encoder to 8096 Interface
+15V
75
P
= IR9533
HEXFET
.,+->-----'1---, 0
PWM
0.1 "F
(POWER)
OC2
HllAl
P2.7
'1/47438
N = IR533
HEXFET
-15V
270061-49
Figure 4-5. Motor Driver Circuitry
6-42
inter
AP-248
motor would decelerate smoothly until the time between encoder edges was around 100 microseconds. At
this point the motor would either continue to decelerate
slowly, or would suddenly stop and reverse. The latter
case is the one that was most problematic.
mode is indicated by the lower 2 bits of Port I, with the
following coding:
Description
P1.0 P1.1 Mode
HSI looks at every edge
0
0
0
1
0
1
HSI looks at Phase A edges only
1
Timer 2 used instead of HSI
0
2
(alternate form of above)
1
1
2
After a brief overview, each section of the program will
be described separately, with the complete listing included in the Appendix D. In order to make debugging
easier, as well as to provide insight into how the program is working, I/O port 1 is used to indicate the
program status. This information consists of which routine the program is in and under which mode it is operating. The main program sections are: Main loop, HSI
interrupt, Timer 2 check, and Motor drive. There are
also minor sections such as initialization, timer overflow handling, and software timer handling. Tying everything together is some overhead and glue. Where the
glue is not obvious it will be discussed, otherwise it can
be derived from the listings.
The example is easiest to see if mode 2 is described first,
followed by mode 1 then mode O. In mode 2 Timer 2 is
used to count edges on the incoming signal. A software
timer routine, which is actually run using HSO.O, uses
the Timer 2 value to update a LONG (32-bit) software
counter labeled POSITION. The HSO routine runs every 260 microseconds. The HSO.O interrupt is used instead of an actual software timer because of the ability
to easily unmask it while other software timer routines
are running.
In the code in Listing 4-7, the mode is first determined.
For the first pass ignore the code starting with the label
in_mode_I. Starting with in_mode_2 the counter is
incremented or decremented based on bit zero of DIRECT. If DIRECT.O = 0 the motor is going backward, if it is a I the motor is going forward. Next the
count difference is checked to see if it is slow enough to
go into mode 1. If not the routine returns to the code it
was running when the interrupt occurred.
The program is a main loop which does nothing except
serve as a place for the program to go when none of the
interrupt routines are being run. All of the processing is
done on an interrupt basis.
There are three basic software modes which are invoked depending on the speed of the motor. The modes
referred to as 0, 1 and 2, in order from slowest to fastest
operation. When the program is running the operating
11".,111"""""'" JIII,JI"""I""",,""" II JIII""',II'" "" ,,,",
SOPTWARE TIMER ROUTINE 0
NOW
USING HSO.O TO TRIGGER
IIIIII
",11 J
"",",""
eSEG AT
hBO exec 1 nt
-
I J ,.,,',111
II III1III1I
1"'1,1111 . , " , , , . " " , , . , . , " " " " , , , , , " " " , , " " " , , " " , , , "
2280H
I Check .ode -
I
Update
position
1n .ode
2
PUSHF
Idb
add
HSO COMMANO,I30H
HSO:TIMB,TIMBRl,HSOO dly
orb
Id
jb.
Tlaer
In .odell
Bub
cap
1h
•• t aodeO •
jbc
-
.ndb
Idb
Idb
br
portl,'OOlOOOOOB
J
Bet
tapl,TI.er 2,014 t2
t.p1,,2
end_."tO
,
Check count ,difference In
Port1.D.enCi .vtD
Portl •• lllliIOOB
J
If already in .04e 0
Clear P1.0, Pl.l (set .ode OJ
enable all HSI
2,TIMBR2
Pl.S
.
portl~1,ln_.04e2
IDe 0., 0101 0 10 18
tapl
laat .tat •• ero
end_ivtD
270061-50
Listing 4-7. Motor Control HSO.O Timer Routine
6-43
AP-248
1" __ 04e2:
Bub
Id
In_fwdt
In
rey:
chk
add
.ade
poaltlon+2,zero
chk_Jlode
sub
Bube
position,delta p
poaltion-+2,zero
sub
cmp
posl tion,delta
,
get
ti.er2
count difference
-
p
tJlpl,Tl.er 2,01d
tapIr'S
end_8wtO
t2
Cheek count difference In tJlpl
aet Model if count Is too low
count <- 5
I
model:
andb
orb
Idb
Id
Bub
hal
Portl"llllllOIB
PortI,'OQOaODOIS
IOCO"OOOOOlOlB-
zero,
lastl
I Clear PI.I,
r enable HSI
set
PI.O
0 and
(set mode
11
1
HSl -'lIMB
time,Tlmerl,mln hall
I set up BO (tlme-last2_tlae»mln_hsll on next aSI
t
Id
ZERO,
andb
orb
10sl bak,iOlllllllB
lost-bak,losl
losl:bak,7,cl,_hsl
J
old t2,TIMER 2
portl,'llOllIllB
r clear
1bs
end
2,t.r2 old
br
19 t
clr
p,timar
t.r2_o1d,tl~er_2
ftl,odet
-
Bet
delta
HSI
TIME
;
If
hsl
clear
is
bit
7
triggered
then clear
hsi
swtO:
Id
andb
Plw5
paPF
ret
270061-51
Listing 4-7. Motor Control HSO.O Timer Routine (Continued)
If the pulse rate is slow enough to go to mode 1, the
enable mode 0 after an edge" is received. This could
cause a problem if the last 2 edges on Phase A before
the encoder stops were too close to enable mode O. If
this happened, mode 0 would not be enabled until after
the encoder started again, resulting in missed edges on
Phase B. Using the HSO routine to switch from mode 1
to mode 0 eliminates this problem.
transition is made by enabling HSI.O and HSI.1. Both
of these lines are connected to the same encoder line,
with HSl.O looking for rising edges and HSl.l looking
for falling edges. The HSI_TIME register is read to
speed up clearing the HSI FIFO and the LASTI_
TIME value is set up so the mode 1 routine does not
immediately put the program into another mode. The
HSI FIFO is then cleared, the Timer 2 value used
throughout this routine is saved, and the routine returns.
Figure 4-6 shows a state diagram of how the mode
switching is done. As can be seen, there are two sources
for most of the mode decisions. This helps avoid problems such as the one mentioned above.
This routine still runs in" modes 0 and 1, but in an
abbreviated form. The section of code starting with the
label in_model checks to see if the pulses are coming
in so slowly that both HSI lines can be checked. If this
is the case then all of the HSIs are enabled and the
program returns. This routine is the secondary method
for going-from mode 1 to mode 0, the primary method
is by checking the time between edges during the HSI .
"routine, which will be described later.
The HSO routine will enable mode 0 from mode 1 if
two edges are not received every 260 microseconds. The
primary method, (under the HSI routine), can only
When either Mode 1 or Mode 0 is enabled the HSI
interrupt routine performs the counting of edges, while
the HSO routine only ensures that the correct mode is
running. The routines for modes 0 and 1 share the same
initialization and completion sections, with the main
body of code being different.
The initialization routine is similar to many HSI routines. The flags are checked to ensure that the HSI
FIFO data is valid, and then the FIFO is read. Next,
the main body of code (for either mode 0 or mode 1) is
6-44
inter
AP-248
270061-52
NOTES:
Mode 0: HSI Examines edges on Phase A and B
Mode 1: HSI Examines edges on Phase A only
Mode 2: TIMER 2 stores edgecount
Figure 4-6. Mode State Diagram
I , , 1 , I J J , , I J J J , , J J J , , J J J J J , , I I I I I J I , J I J , J J J J I I I J J , J J
IJIII
HSI DATA AVAILABLE INTERRUPT ROUTINE
JIII",III"""',""
J """"
"1"""'"
This routine keeps track of the current tiMe
The upper word of infor.atlon is provided by
nolt mode
CSBG 11'1' 2400H
br
1J
br
hal_data
intI
orb
andb
orb
jbe
get valuesl
Id
andb
Id
pUBhf
portl,'D100000DB
1081 blk"01111111B
lOBI-bak,loal
loBI:bak,1,no_intl
J J I I I I JJ J
r
rJ J
'JIII,rIIJIII
J I J I I I J J J I J
and
the
position of the aotor.
timer overflow routine.
J
used to save execution
vorst case loop
,
,
set Pl.6
Clear 10al bak.1
I
If
r
In .ode 1
no:lnt -
no_rntl:-
r
JIIII J 1 1 " , ' 1 ' I JIIII J I I I I , ' I " ' I I I
hal
is not tri9gered
time for
then
, :I u.p to no_int
tiaer 2,'I"I"£R2
hoi oO,HSI S'I'II'I'US,'0101010IB
ti.e,
HSI_TIMB
1 b.
11111111111, ••• " ,
II1II JIII •• , " ' . , 1
II1I1 '" " " ' 1 J •• I
load
INSER'I'
BODY
or
ROU'I'INE
laata;
no_cnt'
Id
br
tNr2 old, tiMer 2
1001-bok,'D11IIIIIB
IOBI-bak,loBI
ioal-bak,7,no int
get_values
-
andb
portl,flOlll1118
andb
orb
1 be
a9a1nl
no_inti
J
clr bit 7
I Clear Pl.6
.popf
ret
I
end of
,
Routine for .ode I
hal
data
Interrupt routine
follows
and
then
$EJEC'I'
270061-53
Listing 4-8. Motor Control HSI Data Available Routine
6-45
Ap·248
POSITION. The program then returns to the comple-
run. At the end time and count values are saved and the.
holding register is checked for another event. Listing 48 contains the initjalization and completion sections of
the HSI routine.
tion section of the routine.
There is a lot more code used in Mode 0 than in Mode
1, most of which is due to the mUltiple jump statements
that determine the current and previous state of the
HSI pins. In order to save execution time several blocks
of code are repeated as can be seen in Listing 4-10. The
first determination is that of which edge had occurred.
If a Phase A edge was detected the LAST1_TIME and
LAST2_TIME variables are updated so a reference to
the pulse frequency will be available. These are the
same variables used under Mode 1. A test is also made
to see if the edges are coming fast enough to warrant
being in Mode I, if they are, the switch is made. If the
last edge detected was on Phase B, the information is
used only to determine direction.
Listing 4-9 is the main body of the Mode 1 routine.
Before any calculations are done in Mode 1, the incoming pulse period is measured to see if it is too fast or too
slow for mode 1. The time period between two edges is
used so that the duty cycle of the waveform will not
affect mode switching. If it is determined that Mode 2
. should be set, Port 1.1 is set, all of the HSI lines are
disabled; and the HSI fifo is cleared. If Mode 0 is to be
set all of the HSI lines are enabled and the variable
LAST-.STAT is cleared. LAST_STAT = 0 is used as
a flag to indicate the first HSI interrupt in Mode 0 after
Mode 1. After the mode checking and setting are complete the incremental value in Timer 2 is used to update
I
Clip
.ndb
tapl,hal
ine
no_cnt
aode
1 HSI
routine
aO,'010100008
-
r Procedure
tiae:
seta
Id
Id
la.t2 ti •• ,l.atl
1 •• tl:tiae,tlae
8ub
tapl,tlae,1 •• t2
CliP
t. pi, • 1 n h. t 1
cheCk_aax_tiae
ih
Bet Mode 2:
orb
ldb
at_hal: Id
.ndb
orb
i b8
br
check •• x
clORe
aeta Mode
to pas.
the
1 also
teata
tl.e
Set Pl.l (In aode
Di.able all R5I
partl •• GDOOOOloa
IOCO"OOOOOOO'OB
sero,hal tl ••
1001 bok~'01111111B
,
eapty' the hal
I clear
losl-bak,7,at hal
done:'chk
-
,
If
2)
fifo
btt 1
lost-bat,losl
hall.
triggered then clear hat
ttael
Bub
cap
set lIode
whic~
tl.ea
tla.
tapl,tlae,1 •• t2 tiae
tapt,.ax_hall-
I .ax h a l · addition
, totil tia.
to atn_hat
for
0:
_ndb
Portl,ll1111100B
I clear
ldb
ldb
IOCO.'OIOIOlOIB
J
Pl.0,1
Bnable all
set Mode
0)
HSI
la!!t_etat,:etc
chk;
sub
ibc
dlrect,O,add_rev
add
adele
be
position,delta p
poaitlon+2,zero
load_Iaata
8ub
posltion,delta p
poaltlon+2,zero
load_lasts
delta
p,tt.ar
2,t.r2
old
J
get
tlaer2
count difference
odd_fwd:
add
rev;
Bubc
br
$eject
270061-54
Listing 4·9; Motor Control Mode 1 Routines
6-46
inter
AP-248
In
-
lIode
a_rIBI!:
0;
- lb.
lb.
lb.
lb.
no_cnt
Id
Id
1 •• t1-tla.,tl ••
• ub
tl • •
1 •• t2
c.p
I
-
lb.
lb.
e.pb
8_fall'
l •• t 8t8t,6,901n9 fwd
1 •• t-.tat,.,90Ing-rav
1 •• t-.tat,2,change dlr
1 •• t-.tat,aero
f i r s t tla.
inp_err
Id
Id
1 •• t2 tl •• ,l •• t1
1 •• t1-tll1.,tl ••
tlll.,I •• t2 tl ••
tIll. , . ' n hit
ClOp
firat
tiM. In .0deO
tl ••
tat_Btatl
j h
I OC 0 • I 000001018
lb.
j b.
cl8pb
I·
br
b_l'lBe:
jb8
laat
lb.
last-atat,2,golng-rev
laat-.tat,6,change dit
laat-stet,zero
first t l . .
c.pb
Ie
Btat,O,golng
change
lnp_err
jb.
last stat,2,golng fwd
last-stat,D,golng-rev
j b.
laat-stat,4,change dit
cllpb
je
br
laat-stet,zero
first tl.e
tl ••
in ,a0480
J
firat
tlae
In aodeO
,
first
tl •• 1n aodeO
-
lnp_err
5tb
hal
br
doni .. chk
sOrlest stat
J
add
delta
position
1
br
dt r:
notb
direct
dlrict,O,golng
gol n9
firat
tl.me:
e1' r
901nll)
,
lvd
br
Ibs
fl.rst
laat atat,.,901ng fvd
laat-atat,6,golng-rev
last-atat,a,change die
last-Btat,zero
flrat' tl ••
lnp_err
j b.
b_'al1.
Set Pl.0 (In .ode 1)
Bnable R51 0 and 1
'o(tl,'OOOOOOOI8
orb
Idb
statf;
lb.
fwd;
orb
Idb
add
addc
br
rev r
andb
Idb
• ub
8ubc
at
r
aodel-
IS.t
-
Set Pl.0 (In aode It
Inable HalO and 1
Portl,I000000018
IOCO,'OOOOOl018
br
• ub
1 np
t1ae
atatt;
I·
-
tl •• ,1 •• t1
,i •• t2 tl ••
tl •• ,aln hi,
tat_Btati'
h
jb.
tat
h •• -.O,6,b:rall
br
,eet lIodelorh
Idb
tat
hal 80,0,8 ria.
hal-sO , 2 , . - r a l l
ha'-.O,.,b-rll.
rev
PORT2.IOIOOOOOOB
dlre:ct,IOl
J
.et P2.'
I direction. forward
pOIII tion,IOI
poal tlon+2,zero
at_Btat
PORT2.IIOlll111B
direct,IOO
poaltlon"Dl
po.ltlon+2,lero
J
I
cl •• r '2.'
direction.
revers.
stet:
.tb
270061-55
Listing 4-10. Motor Control Mode 0 Routines
6-47
AP-248
After mode correctness is confirmed and the LASTx_
TIME values are updated the LASTJTAT (Last
Status) variable is used to determine the current direction of travel. The POSITION value is then updated in
the direction specified by the last two edges and the
status is stored. Note that the ,first time in Mode 0 after
being in Mode 1, the Mode I done_chk routine is used
to update'POSITION, instead of the routines going_
fwd and going_rev from the Mode 0 section of code.
The completion section of code is then executed.
is close enough to the desired location that the power to
it should be reversed, (i.e., enter the Braking mode). If
the motor is very close to the position or has slowed to
the point that is likely to turn around, the Hold_Position mode is entered.
The determination of which modes are selected under
what conditions was done empirically. All of the parameters used to determine the mode are kept in RAM
so they can be easily changed on the fly instead of by
re-assembling the program. The parameters in the listing have been selected to make the motor run, but have
not been optimized for speed or stability. A diagram of
the modes is shown in Figure 4-7.
Providing the PWM value to drive the motor is done by
a routine running under Software Timer 1. The first
section of code, shown in Listing 4"l1a, has to do with
calculating the position and timer errors. Listing 4-11b
shows the next section of code where the pow.er to be
supplied to the motor is calculated. First the direction
is checked and if the direction is reverse the absolute
value of the error is taken. If the error is greater than
64K counts, the PWM routine is loaded with the maximum value. The next check is made to see if the motor
In the Hold_Position mode power is eased onto the
motor to lock it into position. Since the motor could be
stopped in this mode, some integral control is needed,
as proportional control alone does not work well when
the error is small and the load is large. The BOOST
variable provides this integral control by increasing the
output a fixed amount every time period in which the
Listing 4-11. Motor Control Software Timer 1 Routine
J II ", "11,,,,11,',""
,,,"",,"
11," 1,',""""""""" II' """""11
JJIIII
SOPTWARE TIMBR ROUTINE 1
I I I1IIII , . ,
"'I",J".". """"""",.""""",111 """""""",,1 '" ,,,""" II
CSEG AT HOOH
pushf
orb
portl.110000000B
ldb
ldb
HSO
portl.?
J
let
,
enable HSI, TOY!,
I
Calculate
HSO
COMMAND.I]9~
add
USQ=~IME,TIMERl,8Wtl_dly
Id
Id
8ub
8ubo
lub
subc
time err+2.dea tiae+2
err+2,dea poa+2
tiai err,dea ttae,ttae
tlae-err+2,tr.e+2
pOI err,dea pos,posltlon
'tt • •
,
position error
poa
r valuea are Bet
poa:~rr+2,pisltlon+2
El
Bub
ld
Bub
ld
111"
,,,"I I
1111I
I I",
'"
II; II
t l . i delta,last tiae err,tia. err
laat:tiae_err,trae_err
poa delt_,lalt poa err,po. err
last_poa_err,pia_err
Tiae err. Desired tiae to finiah - current tla.
P08 err
• Desired position to finish - current position
Pos-delta
• Laat position error - Curent position error
Tt.i deli • • Laat ttae error - Current ti.e error
n~te that errors should qet ~.aller 80 deltas will be
positive for forward aotlon (tl •• la always forward)
270061-56
Listing 4-11a. Motor Control Software Position .Counter
6-48
inter
AP-248
chk_dl r:
cap
1ge
go
backward,
Id
pOB
Idb
j ne
pw.-dlr ,'DOh
poa-errt2,IOffffH
Id
b,
chk_brk
forward:
Idb
... x:
Chk
•
neg
e. p
go
pas erc+2,zero
go_forward
err
A09
VAL
.4.
pw.
dir.IOIH
ClOp
poa-err+2,zero
j e
chk:brk
Idb
b,
pw. pVt ,.alt pwr
chk:.anlty -
brk:
pOB err,poa pnt
hold pOllitlon
pOll
err,brk
Id_.8.
emp
jge
neg
delta:
chk
brake:
Hold
calc
pos:delta
j nh
hold_poBI tt on
Idb
pWII
Idb
nalb
Idb
tllp;dl\rect
delta, vel
pVt
pnt
out:
.. ul ub
I
velocity· POB delta/sa.ple
I
jllP
I
I
If braking apply power In opposite
direction of current aotlon
t fADS (veloel tV)
~
ti ••
vel:pnt
,aax brk
-
tm p
p",._dlr,t.p
pool tio",
j h
poeltlo"_error>brake_polnt
POB delta,zero
POB
elc
el'
DR
poaltlo"_erroretween output pulses the two mode solution can
be used. The software for the two mode version can be
easily extracted form the three mode version, so it will
not be presented.
5.0 HARDWARE EXAMPLE
5.1. EPROM Only Minimum System
The diagram in Figure 5-1 illustrates how to connect an
8096 in a minimum configuration system. Either 2764s
or 27128s can be used in the system. Note that the
lower EPROM contains the even bytes while the upper
6-52
inter
AP-248
C7
C6
33~F 1
J2
+SV
PF
12
3S
ROY
CLKOUT
NMI
BHE
13
37
38
WR
17
RD
+SV
'::"
14
ALE
TEST
INST
RD
18
ALE
15
EA
ADIS
114
+SV
AD14
VPD
AD13
VCC
AD12
RESET
AD11
~
~
lN4148
.01
AD10
42
":'
12
13
34
36
':'
AD9
10
39
60
11
Vss
33
32
31
30
29
28
27
2a
.loa
VSS
RESET
AD7
EXTINT
ADa
ADS
nCLK
T2RST
PWM
TXD
8096
AD4
AD3
AD2
ADI
ADO
25
24
23
22
21
20
11
18
ADO.lOIS
RXD
ACHO
67
68
VCC
ACHI
Pl.0
ACH2
P1.1
ACH3
P1.2
ACH4
P1.3
ACH5
P1.4
ACHe
P1.5
ACH7
Pl.6
+SV
Pl.7
65
VREF
HSO.O
HSO.l
HSO.2
HSO.3
59
58
57
58
55
48
47
41
50
.
49
43
270061-62
4K is mapped at 2000H. If the program being loaded is
16 Kbytes long the first half is loaded into the second
half of the 2764s and vice versa. A similar situation
exists when using 27128s.
one contains the odd bytes, and the addressing is not
fully decoded. This means that the addressing on a
2764 will be such that the lower 4K of each EPROM is
mapped at OOOOH and 4000H while the upper
6-53
inter·
AP-248
11
•
*
II
A015
..
AD1.
17
AD13
•3
A012
-
•
•
AD11
..010
7
ADI
3
~.
~
G
T
veeJ
DC
0If1!--.
D!I
Q6
Q6
05
05
DO
04
03
03
02
O'
O.
D'
GND
MAl.
27
H
PGM
MA' ..
MA13
2
A'3
A ••
MA'3
MA ••
MA ••
23
AlI
t
.... 11
IIA10
0
MAlO
5
MAl
MAl
MAl
MA7
07 16
.5
07
, Vee
Vee
Vee
••
•
••
••
IIA11
MAt
A01.
A'D
At
DC
03
.5 AI
3
A7
•
MAl
74LS373
vlJ
CC l'
A015
07
II
III
17
AD13
05
0.
,0'
AO
A6
I
A.
7
A3
e
A.
MA.
MAl
•
MA'
MA.
.0
VPP~
-i:
13
••
II
00 .0
eE
5
MA.
••
.5
DE
4012
AD11
A010
ADI
ADe
~
~
,.
T
A.
AO
vPP
GND
2764
27128
RD
vee
T
"
ALE
II
*
AlJ7
ADI
. A05
ADO
AD3
·.02
•
G
DC
II
DI
17
07
D6
..
.3
•
7
AD.
0
ADO
3
~
veeJ
19
07
.
MA7
Q6
'5
MAS
Q6
••
•
DS
OS
DO
03
O'
I
03
D2
O.
D'
GND
O'
•2
IIA1"
MA13
11.. ,2
MAO
MA.
IIA1'
..... 0
MA3
MA.
.....
ItOA.
MAl
MAO
MA7
MAl
74LS373
MAS
MAO
MAl
AD
= ADDRESS/DATA
MA'
MA.
... = MEIIORY AOORESS
Vee
'7 PGM
26 AI3
..'.
23
24
••,
•
0
0
7
•
t
'0
~
.1
AD7
A••
III II
17
All
00
..
ADI
ADS
AD.
A.O
03
15
AD3
At
02
'3
AIJ•
. AIJ'
O~
'2
AI
0.
A7
AO
00
eE 20
AS
DE
"
AO
ADO
r!L -:!=-
A3
A.
A.
AO
vpp--1 vpp
ADO-AD.. ~
07,
GND
2764
27128
~
270061-63
Figure 5-1 (2 of 2).
This circuit will allow most of the software presented in
this ap-note to be run. In a system designed for prototyping in the lab it may be desirable to buffer the I/O
ports to reduce the risk of burni~g out the chip during
experiIqentation. One may also want to enhance the
system by providing RC 'filters on the A to D inputs, a
precision VREF power supply, and additional RAM.
the usage of the lines can be restricted to inputs or
outputs on a port by port rather than line by line basjs.
The ports are reconstructed by using standarq memorymapped I/O techniques, (i.e., address decoders and
latches), at the appropriate addresses. If no external
RAM is being used in the system then the address decoding can be partial, resulting in less complex logic.
5.2. Port Reconstruction
The reconstructed I/O ports will work with the same
code as the on chip ports. The ofiIy difference will be
the propagation delay in the external circuitry. '
If it is desired to fully emulate a 8396 then I/O ports 3
and 4 must be reconstructed. It is easiest to do' this if
6-54
intJ
AP-248
6.0 CONCLUSION
7.0 BIBlOGRAPHY
An overview of the MCS-96 family has been presented
along with several simple examples and a few more
complex ones. The source code for all of these programs are available in the Insite Users Library using
order code AE-16. Additional information on the 8096
can be found in the Microcontroller Handbook and it is
recommended that this book be in your possession before attempting any work with the MCS-96 family of
products. Your local Intel sales office can assist you in
getting more information on the 8096 and its hardware
and software development tools.
6-55
1. MSC-96 Macro Assembler User's Guide, Intel Corporation, 1983.
Order number 122048-001.
2. Microcontroller Handbook (1985), Intel Corporation, 1984.
Order number 210918-002.
3. MSC-96 Utilities User's Guide, Intel Corporation,
1983.
Order number 122049-001.
4. PL/M-96 User's Guide, Intel Corporation, 1983.
Order number 122134-001.
l
SERIES-III MCS-96 MACRO A5SEMULER. VI 0
SOURCE FILE
F3 INTERI A96
F3' INTERI OBJ
OBJECT FILE
CONTROLS SPECIFIED IN INVOCATION COMMAND
ERR LOC
OBJECT
0022
...~
-I
III
ct>
01
m-
0022
0024
0026
0028
0028
002A
002C
002E
0030
tT
CD
r
0
0
~
C
"1:1-
2080
2080 AIOOO1l8
2084 B0221C
2087 18031C
208A 71FEIC
2080 ACICIC
2090 A31D002124
LINE
1
2
3
4
5
=1
=1
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
NOSB
SOURCE STATEMENT
$TITLE('INTERI A96. Interpolation routine I')
8096 AS5embl~ code for table loo~up and interpolation
• • i~. i ,
$INCLUDE(·FO.DEM096 INC)
; Include demo definItIons
Turn listing off for Include file
End of include file
$nollst
RSEG
aJ
~
en
at 22H
IN_VAL:
TABLE_LOW.
TABLE_HIGH:
IN_DIF.
IN_DIFB
TAB_DIF.
OUT:
RESULT:
OUT_DIF:
dsb
ds ..
ds ..
ds ..
e'lu
ds ..
ds ..
d5 ..
d51
o-
Actual Input Value
Upper Input -
IN_DIF
1
Lower Input
:byte
Upper Output -
LDIIII~r
Output
"T1"U
-I"U
~m
; Delta Out
CSEG at 2080H
look:
LD
SP. _100H
LOB
SHRB
ANDB
AL. IN_VAL
AL. _3
AL. _11111110B
Load temp ~ith Actual Value
Divide the byte by 8
l'
N
m><
01)
~~
Insure AL is a word address
b~
2
~
AX. AL
Load byte AL to .. ord AX
TABLE_LOW. TABLE [AX]
TABLE_LOW 15 loaded .. ith the value
in the table at table location AX
270061-64
J>
~Z
JJC
This effectively divides AL
so AL = IN_VAL/16
.
LDBZE
LD
en
O~
s::
"U
ren
m
~
2095 A310022126
2~9A 4824262A
209E 510F2228
20A2 AC2828
20A5 FE4C2A2830
20AA OE0430
....~
~
IT
iD
r
q>
0'1
--J
0
0
20AD 4424302C
20Bl OA042C
20B4 A4002C
20B7 C02E2C
:01"
C
'tI
20BA 27C8
'0
0
2100
:j"
2100
2108
2110
2118
2120
::!.
c:
CD
.e,
000000200034004C
005D006A00720078
007B007D0076006D
0050004B00340022
0010
2122
ASSEMBLY COMPLETED.
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
LO
TABLE_HIGH.
(TABLE+2) [AX]
location AX+2
(The ne.t value in the
TAB_DIF. TABLE_HIGH. TABLE_LOW
TAB_DIF=TABLE_HIGH-TABLE LOW
ANDB
IN_DIFB.
IN_DIF.
MUL
OUT_DIF.
IN_DIFB=least significant 4 bits
of IN_VAL
Load byte IN_DIFB to word IN_DIF
IN_VAL. 10FH
IN_DIFB
IN_DIF.
TAB_DIF
Output_difference =
Input_difference*Table_difference
i
no_inc:
t~bl.)
SUB
LDBZE
Divide by 16 (2**4)
SHRAL
OUT_DIF. 14
ADD
OUT. OUT_DIF.
SHRA
ADDC
OUT,
ST
OUT. RESULT
Store OUT to RESULT
BR
look
Branch -to "look.
OUT. 14
zero
cf
, TABLE_HIGH is loaded with the
value in the table at table
TABLE_LOW
Add output dlfference to output
generated wIth truncated IN_VAL
as input
Round to 12-blt answer
Round up if Carr~ =
)"'U
I
II
N
"'"
CD
cseg
AT 2100H
table:
DCW
OCW
DCW
DCW
DCW
OOOOH.
5000H.
7BOOH.
:lOOOH.
1000H
2000H. 3400H. 4COOH
6AOOH. 7200H. 7800H
7000H. 7600H. 6000H
4BOOH. 3400H. 2200H
, A random function
END
NO ERROR(S) FOUND.
270061-65
SER I ES-III MCS -96 MACHO ASSf 11IJl
UI,
VI
SOURCE FILE
F3 INTER2 A96
OBJECT FILE
F3 INTER2 OB,)
CONTROLS SPECIFIED IN INVOCATION COMMAND
ERR LOC
LINE
OBJECT
1
~1
=1
0024
?>
~
-t
III
q>
(11
<»
!l
CD
b0
!I
0024
0026
0028
002A
002A
002C
002E
0030
2080
2080 AI000118
2084 B0241C
2087 18031C
208A 71FEIC
208D ACICIC
2090 A31D002126
2095 A31D222128
2
3
4
5
6
7
55
56
_ 57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
l
0
NOSB
SOURCE STATEMENT
$TITLE( 'INTER2 A96- Interpolation rout.ne 2')
8096 Assembly code for table lookup and
InterpolatIon
USing tabled values In place of dIVISIon
";; i;;
$INCLUDEI.FO. DEM096. INC) ,
Include demo definitions
TUTn listing off for Include file
$nolist
End of include fiie
RSEG
at 24H
IN_VAL
TABLE_LOW:
TABLE_INC:
IN_DIF:
IN_DIFB
OUT:
RESULT:
OUT_DIF.
dsb
dsw
dsw
dsw
e'lu
dsw
dsw
dsl
Actual Input Value
Table value for function
Incremental change in functIon
Upper Input - Lower Input
1
IN_DIF
:byte
;a.
"P
, Delta Out
N
~
CD
CSEG at 2080H
look:
LD
SP. .IOOH
Initialize SP to top of-reg.
LDB
SHRB
ANDB
AL. IN_VAL
AL. .3
AL. .111111 lOB
LDBZE
AX,
Load temp with Actual Value
Divid~ the byte by 8
Insure AL is a word address
This ef~ectively divides AL by 2
so AL = IN,_VAL/16
Load byte AL to word AX
LD
TABLE_LOW, VAL_TABLECAXl
AL
.
TABLE_LOW
IS
"ie
loaded with the value
in the value table at locatIon AX
LD
TABLE_INC,
INC_TABLECAXl
TABLE INC IS loaded with the value
in the increment table at
location AX+2
270061-66
209A 510F242A
209E AC2A2A
20Al FE4C282A30
20A6 4426302C
20AA 08042C
20AO A4002C
2080 C02E2C
20B3 27CF
~
~
~
0-
ii'
en
~
b
o~
C
..,
'a
'0
o
:::J
3f::
(1)
.s
2100
2100
2100
2108
2110
2118
2120
2122
2122
212A
2132
213A
000000200034004C
0050006A00720078
0078007000760060
0050004B00340022
0010
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
0002400180011001
0000800060003000
200090FF70FFOOFF
EOFE90FEEOFEEOFE
2142
ASSEMBLY COMPLETED.
ANDB
IN_DIFB.
LDBZE
IN_DIF.
MUL
OUT_DIF.
IN_DIF.
no inc:
cseg
Output_difference
Input_difference*Incremental_change
ADD
OUT. OUT_DIF. TABLE_LOW
SHR
AODC
OUT. *4
OUT. zero
Add output difference to autput
generated with truncated IN_VAL
as input
Raund to 12-bit answer
Round up if Carry = 1
ST
OUT. RESULT
loak
Branch to "look:
BR
l
TABLE_INC
J
Store OUT to RESULT
II
AT 2100H
val_tab Ie:
OCW
OCW
DCW
DCW
OCW
inc_tab la:
114
Dew
115
116
117
OCW
DCW
OCW
118
119
IN_DIFB=least significant 4 bits
af IN_VAL
Laad bvte IN_DIFB to word IN_DIF
IN_VAL. *OFH
IN_DIFB
OOOOH.
5000H.
7BOOH.
5DOOH.
1000H
2000H. 3400H. 4COOH
6AOOH. 7200H. 7800H
7DOOH. 7600H. 6DOOH
4BOOH. 3400H. 2200H
i
A random function
»
"D
I
N
~
0200H.
0140H.
0180H.
0110H
ooaOH. 0060H. 0030H
OODOH.
00020H. OFF90H. OFF70H. OFFOOH
OFEEOH. OFE90H. OFEEOH. OFEEOH
CI:I
Table of incremental
differences
END
NO ERROR(S) FOUND.'
270061-67
l
SERIES-III PL/M-9b VI 0 COMPILATION OF' MODULE PLMEX
OBJECT MODULE PLACED IN .F3 PLMEXl.OBJ
COMPILER INVOKED BY.
PLM9b.8b 'F3 PLMEXI.P9b CODE
5-TITLEI'PLMEXI.
PLM-9b Example Code for Table Lookup')
1* PLM-9b CODE FOR TABLE LOOK-UP AND INTERPOLATION *1
PLMEX.
DECLARE'
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
DECLARE
2
3
4
5
~
~
'U
!iii:
ch
aI
~
o
b
7
8
9
a.
CD
=:
In
>C
'U
Dl
::J
1/1
II
12
13 .
14
0'
IN_VAL
TABLE LOW
TABLE-HIGH
TABLE:DIF
OUT
RESULT
OUT_DIF
TEMP
I
2
2
PUBLIC,
PUBLIC,
PUBLIC,
PUBLIC,
PUBLIC,
PUBLIC,
PUBLIC,
PUBLIC,
WORD
INTEGER
INTEGER
INTEGER
INTEGER
INTEGER
LONGINT
WORD
DECLARE TABLE(17)
OOOOH, 2000H,
5DOOH. bAOOH.
7BOOH. 7DOOH.
5DOOH. 4BOOH.
IOOOHI,
10
oo
~
DO,
INTEGER DATA
3'lOOH. 4COOH.
7200H. 7800H.
7600H. bDOOH.
3·l00H. 2200H.
1* A
T~ndQm
function */
)0
'P
iii)
.c.
CIt
DMPY:
PROCEDURE IA.BI LONGINT EXTERNAL,
DECLARE (A.BI INTEGER,
END DMPY,
LOOP.
TEMP=SHR I IN_VAL. 41,
1* TEMP is the most significant 4 bits of IN_VAL *1
::J
1* I f "TEMP" .. as replaced by "SHRIIN_VAL.41"
1* The code would work but the 809b would
1* do twa shifts
Ib
TABLE_LoW=TABLE(TEMPI,
TABLE_HIGH=TABLEITEI1P+II,
17
TABLE_DIF=TABLE_HIGH-TABLE_LoW'
18
OUT_DIF=DMPYITABLE_DIF.SIGNEDIIN_VAL AND OFHII lib,
19
OUT=SAR(ITABLE LOW+OUT DIFI.4I,
15
-
-
*1
*1
*1
1* SAR performs an arithmetic right shIft.
in this case 4 places are shifted
*1
270061-68
--
IF CARRY=O THEN RESULT=OUT,
ELSE RESUL T=OUT + 1,
20
22
1* Using the hardware flags must be done
1* with care to ensure the flag is tested
1* in the desired
23
II
GOTO LOOP,
1* END OF PLM-96 CODE
24
instruction sequence
*1
*1
*1
t
*1
END,
270061-69
PL/M-96 COMPILER
PLM-96 Example Code for Table Lookup
PLMEXI'
ASSEMBLY LISTING OF OBJECT CODE
:to
~
"G
r3:
AI00001B
R
AOOOI0
OB0410
R
R
002C
0030
4410101C
A31DOOOO02
R
;:;:
I'll
0035
A31D020004
R
'a
III
::J
003A
4B020406
R
O·
003E
0040
0045
0047
004A
004D
0050
CB06
410FOOOOIC
CBIC
EFOOOO
OE041C
AOIEOE
AOICOC
0053
0056
005B
005B
005E
0061
A00220
0620
64lC20
A41E22
OE0420
A0200B
0064
0067
0069
006B
BIFFIC
DB02
l11C
~
(I)
0
0
Co
CD
O'l
~
STATEMENT
::e
:r
LD
::J
'0
0
::!.
:i"
c
CD
.&
SP,IISTACK
LOOP:
TEMP, IN_VAL
TEMP,1I4H
STATEMENT
15
TMPO, TEMP, TEMP
ADD
TABLE_LOW,TABLE[TMPOl
LD
STATEMENT
16
TABLE_HIGH,TABLE+2H[TMPOl
LD
STATEMENT.
17
TABLE_DIF,TABLE_HIGH,TABLE_LOW
SUB
STATEMENT
IB
PUSH TABLE_DIF
TMPO,IN_VAL,IIOFH
AND
PUSH TMPO
CALL DMPY
SHRAL TMPO,1I4H
OUT_DIF+2H,TMP2
LD
OUT_DIF,TMPO
LD
STATEMENT
J9
TMP4,TABLE_LOW
LD
TMP4
EXT
TMP4,TMPO
ADD
ADDC TMP6,TMP2
SHRAL TMP4,1I4H
OUT,TMP4
LD
STATEMENT
20
TMPO,IIOFFH
LDB
BC
C!0003
CLRB TMPO
LD
SHR
R
>C
III
14
PLMEX.
0022
0022
0026
0026
0029
R
R
E
R
R
R
R
)0
"0
I
N
.j:o.
CD
@0003:
270061-70
006B
006E
981COO
0705
0070
0073
A0200A
2005
CMPB
BNE
R
0075
0075 A0080A
0078 '070A
007A
007A
LD
BR
@0001:
R
R
LD
INC
RESULT, OUT
RESULT
STATEMENT
23
BR
LOOP
STATEMENT
@OO02:
27AA
t
RO, TMPO
@OOOI
STATEMENT
21
RESULT,TMP4
@0002
STATEMENT
22
24
END
~
"0
r-
3:
cl>
Q)
0
0
a.
CD
~
MODULE INFORMATION:
CODE AREA SIZE
CONSTANT AREA SIZE
DATA AREA SIZE
STATIC REGS AREA SIZE
005AH
0022H
OOOOH
0012H
900
340
00
180
~
;:;:
% >C
l'
N
:::T
I\)
",
"'C
III
:s
!e.
0
:s
00
::J
""c:::J
CD
.9:
PL/M-96 COMPILER
PLMEXl
.co.
(XI
PLM-96 Example Code For Tdble Lookup
ASSEMBLY LISTING OF OBJECT CODE
OVERLAYABLE REGS AREA SIZE
MAXIMUM STACK SIZE
48 LINES READ
PL/M-96 COMPILATION
CO~iPLETE
OOOOH
0006H
o
00
60
WARNINGS.
o ERRORS
270061-71
MCS-96 MACRO ASSEMBLER
MULT APT'
SERIES-III MCS-96 MACRO ASSEMBLER,
VI.O
SOURCE FILE. : F3: MULT. A96
OBJECT FILE': : F3: MULT. OBJ
CONTROLS SPECIFIED IN INVOCATION COMMAND:
ERR LOC
0018
~I
0000
~I
0000
~
"U
OBJECT
I
CD
Q)
0
0
a.
III
::IE
C»
m
U)
:.
:r
m
>II
'0
AI
::I
Ul
o·::I
'0
0
::J
5"
c:
(l)
S
0000 CC04
0002 CCOO
0004 FE6EI900
E
E
E
0008 E304
OOOA
E
ASSEMBLV COMPLETED,
LINE
I
2
3
4
5
6
7
8
9
10
II
12
13
14
15
16
17
18
19
l
16*16 mult1ply procedure for PLM-96
NOSB
SOURCE STATEMENT
$TITLEC'MULT. APT: 16*16 multlply procedure for PLM-96
1
)
SP
EGU
18H: .. ord
EXTRN
PLMREG
: long
PUBLIC
DMPV
POP
POP
MUL
PLMREG+4
PLMREG
PLMREG, [SPl+
Load one operand
Load second operand and increment SP
BR
[PLMREG+41
,
rseg
c:seg
DMPV:
Multiply t .. o integers and return a
longint result in AX, DX registers
,
,
Load return address
.
»
"tI
I\)
Return to PLM code.
""'
CO
END
NO ERRORCS) FOUND.
270061-72
i
SERIES-III MCS-96 RELOCATOR AND LINKER. V2.0
CoPUright 1983 Intel Corporation
INPUT FILES: : F3: PLMEXL OBJ. : F3· MUloT. OBJ. PLM96 LIB
OUTPUT FILE: :F3:PLMOUT.OBJ
CONTROLS SPECIFIED IN INVOCATION COMMAND:
ROM (2080H-3FFFH)
INPUT MODULES INCLUDED:
·F3:PLMEXI OBJ(PLMEX)
12/25/84
·F3:MULT.OBJ(MULT)
12/25/84
PLM96.LIB(PLMREG)
11/02/83
1~
"a
i
~
SEGMENT MAP FOR :F3:PLMOUT.OBJ(PLMEX):
TYPE
**RESERVED*
*** GAP ***
It
:IE
cp
.~
;::;:
~
***
GAP
***
i::s
***
GAP
***
o::s
***
GAP
***
m
Ie
!!!.
g
a:
E
!
REG
REG
STACK
CODE
CODE
CODE
BASE
LENGTH
OOOOH
001AH
001CH
0024H
0036H
003CH
2080H
2083H
2084H
2100H
210AH
001AH
0002H
0OO8H
0012H
0006H
2044H
0003H
000lH
007CH
OOOAH
DEF6H
ALIGNMENT
MODULE NAME
ABSOLUTE
WORD
WORD
PLMREG,
PLMEX
ABSOLUTE
PLMEX
WORD
BYTE
PLMEX
MULT
---------
-----------
~
l'
N
.j:Io
CD
270061-73
l
SYMBOL TABLE FOR :F3:PLMOUT.OBJ(PLMEX).
ATTRIBUTES
VALUE
NAME
0024H
0026H
0028H
002AH
002CH
002EH
0030H
0034H
2l00H
OOlCH
003CH
lFC4H
PUBLICS·
IN_VAL
TABLE_LOW
TABLE_HIGH
TABLE_DIF
OUT
RESULT
OUT_DIF
TEMP
DMPY
PLMREG
MEMORY
?MEMORY_SIZE
----------
»
~
"tI
r:!:
I
REG
REG
REG
REG
REG
REG
REG
REG
CODE
REG
NULL
NULL
WORD
INTEGER
INTEGER
INTEGER
INTEGER
INTEGER
LONGINT
WORD
ENTRY
LONG
NULL.
NULL
CD
QI
MODULE: PLMEX
~
Q.
MODULE: MULT
CD
m
c»
01
MODULE: PLMREG
!.
:;:
m
>c
-g
:::I
III
o·
:::I
ao
:::J
g.
c:
(1)
.a
RL96 COMPLETED.
o
WARNING(S).
o
ERROR(S)
»
'tI
270061-74
~
CD
SERIES-III MCS-96 MACRO
SOURCE FILE'
F3,PULSE A96
OD~ECT FILE
,F3,PULSE OD~
CONTROLS SPECIFIED IN INVOCATION COMMAND
ERR LOC
LINE
OD~ECT
I
=1
=1
0028
0028
002A
~I
002C
002E
0030
~
"
:1
..
c
'en
a,
en
2080
iI:
CD
DI
I/)
C
CD
3
CD
::s
2080 AIOOO118
2084 010115
2087 1l10F03
208A 442A282C
208E 3EI603
2091 3716F6
2094 D0061C
2097 A00420
209A 391C09
2090 C03020
20AO 482E3028
20A4 27E4
20A6 C02E20
·a
VI 0
ASS~MDLER.
2
3
4
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
CL,'NOSD
SOURCE STATEMENT
5TITLE( 'PULSE A96 MeasurIng pulses uSIng the HSI unIt')
5INCLUDE(DEM096 INC)
Turn listing off for include file
End of Include file
Snolist
Tseg
at
28H
HIGH_TIME,
LOW_TIME:
PERIOD:
HI_EDGE'
LO_EDGE:
cseg
wai t:
at
dsw
dsw
dsw
dsw
dsw
2080H
):0
~
0Iloo
LO
LOB
LDD
SP, #IOOH
lOCO. #OOOOOOOIB
HSI_MODE, #000011111l
ADD
PERIOD, HIGH_TIME, LOW_TIME
1051, 6, contin
i
If FIFO is full
~BS
~IlC
contin: LDD
1051,
7,
wait
AL, HSI_STATUS
i
CD
Enable HSI 0
HSI 0 look for either edge
; Wait whIle no pulse is entered
Load status;
Note that reading
HSI_TIME clears HSI_STATUS
LD
ax. HSI_TIME
Load the HSI_TIME
~DS
AL,
~ump
hsi_Io: ST
SUB
IlR
hsi_h i:
ST
1, hsi_hi
if HSI,O is high
BX, LO,,:,EDGE
HIGH_TIME, LO_EDGE, HI_EDGE
walt
ax, HI_EIlGE
270061-75
20A9 48302E2A
20AD 27DB
20AF
ASSEMBLY COMPLETED.
88
89
90
91
SUB
BR
LOW_TIME.
(
HI_EDGE. LO_EDGE
wait
END
NO ERROR IS) FOUND.
270061-76
»
~
'tI
C
iii
CD
3:
CD
q>
Ol
--J
II..
~
00
:::l
S'
c:
CD
.s
II
l0-
"0
I
I\)
.&:10
Q)
SERIES'I I I MCS '''16 MACRO
A~,SI11D1
HL
VI
cl
(j
~3 ENHSI A"I6
SOURCE FlU.
UBJECT FILE
F3 ENIISI OU.!
CUN1FlOLS SPECIFIED IN INVIJCArlON COMMAND
ERR LOC
OIlJECl
0028
»
0028
002A
m
002E
!n
::::I
:::r
DI
::::I
()
CD
cp
(l)
00
12.
'tI
C
002C
002F
0030
0032
0034
0036
iii
2080
iii:
2080 AI000118
DI
2084 1112516
CD
CD
1/1
C
...CD
3
..
1D
::::I
2087 B19903
208A 1110715
2080 717F2F
2090 90162F
2093
~72FF7
2096 5155062E
209A A00428
LINE
1
2
3
~1
4
=1
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
N051l
SOURCE STATEMENT
STIflE ('ENHSI A96 ENHANCED HSI PULSE ROUTWE')
SINCLUOECOEM096 INC)
Turn listing off for
End of Include fIle
$nollst
Include file
RSEG AT 28H
TIME
LAST_RISE.
LAST_FALL'
HSI_SO
10SI_BAII:
PERIOD:
LOW_TIME:
HIGH_TIME:
COUNT
OSW
OSW
OSW
OSB
DSB
OSW
OSW
OSW
OSW
):0
'U
1
cseg
at
2080H
in i t:
LO
SP.III00H
LOB
IOC1.1I00IOOIOlll
LOB
LOO
HSI_MOOE.III0011001B
IOCO.IIOOOOOI1IB
ANOB
ORO
IOS1_BAII.IIOIII1111B
10SI_BAII. 1051
lIIal
t:
JBe
ANOB
LO
,IOS1_BAII.7 ... ait
I\)
-..:.
CI)
Disable HSO. 4.HSO 5. HSI_INT=f.rst.
Enable PWM. TXO. TIMERl __OVRFLOW_INT
set hsi. 1 -;
hsi. 0 +
Enable hSl 0,1
T2 CLOCII=T2CLII. T2RST=T2RST
Clear tlmer2
Clear IOSl_BAII.7
Store Into temp to avoid clearing
; other flags which may be needed
If hSl is not triggered then
Jump to walt
HSI_SO,HSI_STATUS.IIOI0I0101B
TIME. HSI_TIME
270061-77
2090 382E05
20AO 3A2EOF
20A3 20lA
20A5
20A9
20AD
20BO
482C2832
482A2830
A0282A
200B
20B2 482A2834
20B6 482C2830
20BA A0282C
»
~
m
:::I
::T
III
:::I
(')
CD
Co
"'IJ
20BD
20BD 0736
20BF 27CC
20Cl
ASSEMBLY COMPLETED'.
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
.IDS
JDS
DR
HSI_SO,O,a_rise
HSI_SO. 2. a_fall
no_cnt
a_rise:
SUB
SUB
LD
BR
LOW_TIME. TIME. LAST_FALL
PERIOD. TIME. LAST_RISE
LAST_RISE. TIME
a_fall:
SUB
SUB
LD
HIGH_TIME. TIME. LAST_RISE
PERIOD. TIME. LAST_FALL
LAST_FALL. TIME
l
increment
Increment:
no_cnt:
INC
BR
COUNT
wa1t
END
NO ERROR(S) FOUND.
270061-76 .
C
iii
CD
0)
a,
(0
5:
CD
III
1/1
C
;a
3
CD
3-
'§
;:;
:i"
c
(!l
,a,
:>
"0
I
I\)
~
CO
i
SERIES-III MCS-96 MACRO ASSEMBLER, Vl.O
SOURCE FILE: ·F3:HSODRV.A96
OBJECT FILE: :F3:HSODRV.OBJ
CONTROLS SPECIFIED IN INVOCATION COMMAND: NOSB
ERR LOC
~
iJl
OBJECT
0028
::e
iii:
en
..!.J
0
c:
-
0028
002A
002C
002E
0030
0
2080
Ie.
::I
O·
' :t
CD
:z:
0
2080
2081
2085
2089
FA
AI000118
510F1500
9:10FOO
208C
208C AI000122
2090 AlOOI01C
2094 48221C20
2098 A0221C
LINE
1
2
3
4
5
6
7
8
9
10
11
=1
12
=1
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
E
79
E
BO
81
82
83
84
B:I
86
B7
SOURCE STATEMENT
$TITLE('HSODRV.A96: Driver module for HSO PWM'program')
MODULE
HSODRV
PUBLIC
PUBLIC
PUBLIC
PUBLIC
MAIN, STACKSIZE(81
HSO_ON_O
HSO_OFF_O
HSO_ON_l
HSO_OFF_l
HSO TIME
HSD_COMMAND
SP • TIMERI • 1050
SINCLUDE(DEM096. INC)
$nolist
Turn listing off for include file
;, End of include file
rseg at 28H
EXTRN
OLD_STAT
HSO_ON_O:
HSO_OFF _0:
HSO_ON_l:
HSO_OFF_l:
count:
cseg
: byte
:J-
~
ds ..
ds ..
ds ..
00
ds ..
dsb
at 20BOK
strt:
EXTRN
wait
DI
LD
ANDB
XORB
SP. .100H
OLD_STAT. 10SO. .OFH
OLD_STAT. .OFH
LD
CX. .0100H
LD
SUB
LD
AX. .1000H
BX. AX'. CX
AX·. CX
: entrv
ini tia'l:
loop:
270061-79
209B C02B1C
209E C02A20
-20Al
20M
20A7
20AA
OB011C
OB0120
C02CIC
C02E20
20AD EFOOOO
20BO 0722
20B2 89000F22
20B6 07DB
20BB 27D2
EI
~
20BA
ASSEMBLY COMPLETED.
E
BB
B9
90
91
92
93
94
95
96
97
9B
99
100
101
102
103
104
ST
ST
AX. HSO_ON_O
BX. HSO_OFF_O
SHR
SHR
ST
ST
AX. 111
BX.lIl
AX. HSO_ON 1
BX. HSO_OFF _1
CALL
IAIait
INC
CMP
BNE
CX
CX. '1I00FOOH
loop
BR
Initial
(
END
NO ERRORIS) FOUND.
270061-80
3:
c:
til
S'
...::r
):0
"tI
I
CD
N
%
til
.!..J
W
:;:
(1)
:::t:
en
0
'0
0
;a
:i"
C
CD
£,
001F
OOIF BII000
0022 44000000
E
E
0026
0026 310113
0029 390209
R
R
002C
002C B13100
002F 44000000
0033 2007
0035
0035 BIII00
0038 44000000
003C
003C B00201
003F FO
0040
ASSEMBLY COMPLETED,
E
E
E
E
R
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
store_stat:
ANDB
CMPB
JE
XORB
NEW_STAT.
OLD_STAT.
1050. IIOFH
NEW_STAT
i
Store new status of HSD
I I
wait
OLO_STAT.
NEW_STAT
OLD_STAT.
NEW_51 AT.
O.
O.
t
chec k_O.
JBC
JllS
c h ec k 1
Jump
if OLD._STAT(O);NEW _STAT(O)
set _off_O
set_cn_O:
LD8
ADD
BR
HSO_COMMAND. 1*001100008
HSO_TIME. TIMER I. HSO_OFF 0
check I
-
Set HSO for tlmer!, set pin 0
Tlme to set pIn; Timer! value
+ Time for pin to be low
LOB
ADD
HSO_COMMAND. IIOOOIOOOOB
HSO_TIME. TIMERI. HSO_ON_O
Set HSO for timer!. clear pin 0
Tlme to clear pln = Timer! value
+ "rime for pIn to be hIgh
JBC
JBS
OLD_STAT.
NEW_STAT.
Jump
set_off _0:
check_I:
1.
1.
done
set_off I
check
if
OLD_STAT(I);NEW_STAT(I)
-
LOB
ADD
BR
set - off I:
LOB
ADD
HSO_COMMAND. IIOOIIOOOIB
·HSO_TIME, TIMER!. HSO_OFF
Set HSO for timer L
Time to set pin
=
set pin I
Timer1 value
II
thee k_done
HSO_COMMAND, 1I0001000lB
HSO_TIME, TIMERI. HSO_ON
-
Set HSO for timerl. clear pin I
Time to clear pin = Tlmer! value
OLD_STAT,
Store current status and
wait for interrupt flag
+ TIme for pin to be high
check_done;
LOB
NEW_STAT
RET
use "BR
.
»
"tI
set_on 1:
wait" if this routine is used with the driver
END
UO ERRORCS) FOUND.
270061-82
I\)
"..
;..
rn
m CD
~
.1>0
::!.
200C
200C 9C20
!!!.
2080
"......
20BO AIOOOllB
0
20B4 BI2016
0027
OOBO
0026
20B7 BI260E
20BA BIBOOE
LINE
I
2
3
4
=1
5
53
=1
54
55
56
57
5B
59
60
61
62
63
64
65
66
67
6B
69
70
NOSB
SOURCE STATEMENT
$TITLE( 'SP A96: SERIAL PORT DEMO PROGRAM')
UNCLUDE(DEM096. INC)
Snolist
rseg
at 2BH
CHR:
dsb
SPTEMP: dsb
TEMPO:
dsb
TEMPI:
dsb
RCV_FLAG:
cseg
cseg
dsb
at 200CH
DCW
71
72
73
74'
75
76
77
7B
79
BO
Bl
B2
B3
B4
B5
Turn listing off for include file
End of include file
)0
ser-port_int
l'
I\)
at 20BOH
LD
SP.
LOB
lOCI.
BAUD_HIGH
BAUD_LOW
LOB
LOB
, Set P2,0 to TXD
~00100000B
Baud rate
baud_val
baud_val
t
~100H
input frelluenc~ 1 (64*baud_val)
(input frelluenc~/64) 1 baud rate
,39
(12,000.000/64)/4BOO baud
ellu
39
ellu
ellu
«baud_val-l)/256) OR BOH
(baud_val-I) MOD 256
Set MSB to 1
BAUD_REG. IIBAUD._LOW
BAUD_REG. IIBAUD_,HIGH
270061-83
2080 014911
2090 C42807
2093 BI202A
209b 014008
2099 FO
209A 27FE
209C
99
209C F2
.,.
:"I
(I)
CD
:::!.
!!!.
m
.!.,J
(J1
"0
0
~
9
::J
C!:
::J
c::
·m
.s
8b
87
88
89
90
91
92
93
94
95
9b
97
98
2090
2090 001129
20AO 90292A
20A3 716029
20Ab 07F~
100
101
102
103
104
LOB
SPCON. .010010010
Enable receIver,
l
Mode
The serial port is now Initialized
loop:
STB
LOB
SBUF. CHR
TEMPO. .00100000B
LOB
EI
OR
INT_MAS~
• • 01000000B
loop
Clear serlal Port
Set TI-temp
Enable SerIal Port Interrupt
; Walt for serial port interrupt
seT_part_Int'
PUSHF
rd_agal n.
LOB
ORO
ANOO
JNE
10'
ThIS
SPTEMP. SPSTAT
TEMPO.
SPTEMP
settlon of
code can be replaced
• "'1 th "ORB
TEMPO. SP _STAT" ",hen the
serIal port TI and RI bugs ar~ Fixed
SPTEMP •• OIIOOOOOO
rd_agaln
Repeat until TI and RI are properly cleared
lOb
20A8
20A8
20AO
20AE
20BI
3b2A09
C42807
710F2A
0lFF2C
2004
2004
20B7
200A
2000
302CI8
352AI5
002807
710F2A
20CO
20C3
20Cb
20C8
717F28
990028
0705
BIOA28
20CB 2002
20CO
20CO 112C
20CF
20CF F3
2000 FO
2001
ASSEMBLY COMPLETED.
107
108
109
110
III
112
113
114
11:1
l1b
117
118
119
120
121
122
123
124
12'
12b
127
128
129
130
131
132
get_byte.
JOC
STO
ANOB
LOB
SOUF. CHR
TEMPO • • 101111110
RCV_FLAG. .OFFH
Store b~te
CLR RI-temp
Set bit-receIved fl.g
put_byte·
JOC
JOC
LOB
ANOO
ReV_FLAG, 0, continue
TEMPO, 5, continue
SBUF. CHR
TEMPO. UI0n 1110
If receive flag is cleared
If TI ",as not set
Send byte
CLR TI-t"mp
TEMPO,
6,
put_blJte
ANOB
CMPO
JNE
LOO
BR
CHR. .011111110
CHR •• OOH
CLRB
RCV_FLAG
If RI-temp
15
not set
»
"P
1\0)
t
; This section of code appends
an LF after a CR is sent
CIT_Tev
CHR. .OAH
continue
cIT_rev:
Clear bit-received flag
continue:
POPF
RET
ENO
NO ERROR IS) FOUND.
270061-84
(
SERIES-III MCS-96 MACRO ASSEMID_ER. VI 0
SOURCE FILE: :F3:ATOD A96
OBJECT FILE: :F3:ATOD.OBJ
CONTROLS SPECIFIED IN INVOCATION COMMAND: NOSB
ERR LOC
OBJECT
0028
0020
001E
m
:1-
m
0
-!.J
0028
0028
002A
002C
002E
0
°1
2080
0
~
II
2080 Al00011B
2084 0120
2086 55082002
208A FD
20B8 FD
208C 3B02FD
208F B0021C
2092 B0031D
2095 5420201E
2099 AC1E1E
209C C31E281C
20AO 1720
LINE
1
2
3
4
=1
52
=1
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Bl
B2
B3
B4
85
86
SOURCE STATEMENT
$TITLE('ATOD.A96: SCANNING THE A TO D CHANNELS')
$INCLUDECDEM096. INC)
$nolist·,
Turn listing off for include file
End of include file
RSEG
at
28H
BL
DL
EGU
EGU
RESULT_TABLE:
RESULT_l
RESULT_2
RESULT_3
RESULT_4
BX:BYTE
DX: BYTE
dsur'
dSId
dSId
ds ...
1·
l>
"P
N
cseg
at
20BOH
start:
LD
CLR
next:
AD08
check:
NOP
NDP
JBS
AO_RESULT_LO, 3, check
LDB
LOB
AL. AD_RESULT_LO
AH, AD_RESULT_HI.
Load low order result
Load high order result
ADDB
LDBZE
_ST
OL, BL, BL
OX, OL
AX, RESULT_TABLECOXJ
DL=BL*2
INCB
BL
~
Q)
Set Stack Pqinter
SP, *100H
. BX
AO_COMMAND,BL, *1000B
Start conversion on channel
indicated by BL register
Wait for conversion to start
I
Wait ... hile A to D is busy
Store result indexed by BL*2
Increment DL modulo 4
270061-85
AP-248
::t:
M
0
*' ...
j
"
~
III
C
·111
Q
..
Z
..J
1:
W
CD
CD
<
~m·
:D
:D
c:
"V
-I
Channef being converted
86
270061-87
o
oZ
-I
:D
or-
.
:.
"U
N
.&lIo
011
_.
2000
2000
2002
2004
2006
8020
ID21
8020
CC20
2080
2080
2084
2086
2088
~6
AIOOOl18
OIIC
051C
D7FC
208A 1144
208C
2090
2094
2098
209C
en
~
CO
87
88
89
90
91
92
93
94
95
AI800028
AIOOOl48
AI40002A
AI80002C
AICOO02E
20AO 4500010A38
20A5
20A8
20MI
20AC
20AD
20BO
1113606
A03804
FD
FD
812206
643804
20B3'
20116
20119
20BC
91074A
Bl0A08
810A09
FB
20llD
20CO
20C4
20C7
20CA
91010F
65010040
A40042
71FEOF
27FI
97
98
99
100
101
102
103
104
105
106
107
108
109
110
III
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
cseg
AT 2000H
DCW
DCW
DCW
DCW
start
Atod_done_int
start
HSO_p.xec_int
I I
Timer _ovf _i nt
t
HSI_data int
$E.JECT
cseg
5
tart:
UJalt:
loop:
AT 2080H
LD
CLR
DEC
.JNE
SP. IIIOOH
AX
AX
wait
CLRB
AD_NUM
LD
LD
LD
LD
LD
PWM TIME_I. 1I080H
HSO_PER. IIIOOH
HSO_ON_O. 1I040H
HSO_ON_I. *080H
HSO_ON_2. *OCOH
ADD
NXT_ON_T.
LDB
LD
NOP
NOP
LDB
ADD
HSO_COMMAND. *00110110B
HSO_TIME. NXT_ON_T
Set Stack Pointer
blait approx. O. 2 seconds foT'
SBE to finish communications
Timer!,
*100H
HSO_COMMAND. 1I00100010B
HSO_TIME. NXT_ON_T
•
•
Set HSO for timer!.
with interrupt
set pin 0,1
Set HSO for timerl.
without interrupt
set pin 2
ORB
LDB
LDIl
EI
LAST_LOAD. *OOOOOI1IB
INT_MASK. IIOOOOIOIOB
INT_PENDING. 1I000010l0B
Last ,loaded value .,as set all pins
Enable HSO and AID interrupts
Fake an AID and HSO interrupt
ORB
ADD
ADDC
ANDB
BR
Portl, 1I00000001B
COUNT. 1101
COUNT+2. zero
Portl. IIll111110B
loop
set PI.O
II
clear PI.O
$E.JECT
270061-88
):0
"tI
I
II)
.0.
CI
20CC
20CC F2
20CD 91020F
20DO 4B3BOA46
20D4 BB0046
20D7 DE19
20D9
20D9
20DC
20DF
20E2
20E3
20E4
20E7
644B3B
013606
A03B04
FD
FD
012206
A03B04
20EA 91074A
~
0
20ED 002B17
20FO 2026
20F2
20F2 304A23
20F5 ~42A3B3A '
20F9 011006
20FC A03A04
20FF
2100
2104
2107
FD
442C383C
011106
A03C04
210A
2100
210F
2112
FD
442E3B3E
011206
A03E04
2115 71FB4A
211B
211B 71FDOF
132
133
134
135
136
137
13B
139
140
141
142
143
144
145
146
147
14B
149
150
151
152
153
154
155
156
157
15B
159
160
161
162
163
164
165
166
167
16B
169
170
171
172
173
174
175
176
177
17B
179
IBO
IBI
• • • " . ; ; • • • " . I I . i •• ; ; . , ;
•• i . ; ; i f ; , ; "
."
" " . I i •• i ; ; .
,i,
f
••••••
HSO
II'
Ii i,
j
f'"
., •• , •• ; •••••
......., .. .
I i ••
•••
Of
i ; i ; " . , •• ;1, i i I I ; • • • i f ' ; i •• , .
to
EXECUTED
If;' . " . ; i. i ,;,.,; i
IN1ERRlIPI
II
;
j
.,.
l
. ..
I I •• , i
~
; ; ;
oj
ii"
, -'
;1;;
HSO exeC_Int.
PUSHF
ORO
Portl. .000000100
SUO
CMP
JLT
TMP.TIMERI. NXT~ON_T
TMP. ZERO
set_off_times
set on_t imes·
ADD
LDO
LD
NOP
NOP
LDO
LD
NXT_ON_T. HSO_PER
HSO_COMMAND • •001101100
HSO_TIME. NXT_ON_T
; Set pi 1
;
Set HSO for timerL
set pin 0.1
HSO_COMMAND. .00100010B
HSO_TIME. NXT_ON_T
Set HSO for timer1.
set pin 2
ORO
LAST_LOAD• •00000111B
Last loaded value was all ones
-LDD
PWM_CONTROL. PWM_TIME_l
BR
check_dane
Now is as good a time as
to update the PWM reg
~
an~
~
CD
set_off _times;
JBC
LAST_LOAD. O.
checl_done
ADD
LDO
LD
NXT_OFF_O. NXT_ON_T. HSO_ON_O
HSO_COMMAND • •000100000
HSO_TIME. NXT_OFF_O
Set HSO for timerl. clear pin 0
NOP
ADD
LDO
LD
NXT_OFF_l. NXT ON_T. HSO_ON_l
HSO_COMMAND • •000100010
HSO_TIME. NXT_OFF_l
Set HSO for timerl. clear pin
NOP
ADD
LDD
LD
NXT_OFF_2. NXT_ON~T. HSO_ON_2
HSO_COMMAND • •00010010B
HSO_TIME. NXT_OFF._2
ANDB
LAST_LOAD • • 11111000B
Last loaded value was aliOs
Portl • • 11111101B
Clear PI, 1
check_dDne:
ANDB
Set HSO for timerl. clear pin 2
270061-89
211B F3
211C FO
211D
211D F2
211E 91040F
m
~
2121
2125
212B
212C
212F
51C0021C
B0031D
5444441E
AC IEIE
C31E301C
2133
2136
213B
213B
213D
99401C
DI07
99FF1D
DF02
171D
213F BOIDIC
2142 IIID
2144 C31E2B1C
2148 1744
214A 710344
214D 55084402
2151 71FBOF
2154 F3
2155 FO
2156
ASSEMBLY COMPLETED.
182
183
184
IB5
lB6
lB7
lBB
lB9
190
191
192
193
194
195
196
197
19B
199
200
201
202
203
204
205
206
207
20B
209
210
211
212
213
214
215
216
217
218
219
220
221
cl
POPF
RET
$E.JECT
" ; , i , ; j ; ; i , ; j i j i i i i . ; ; i i . i j . j ; i , ; i •• j ; ; ; ; ; . I I , , ; ' ; ; ; ;1'
i , ; ; i ; ; l i ; i i; I i ;
A TO D COMPLETE INTERRUPT
"
iii ;i;;.i;; ;;.i;;;;;;;,,;; ii, ,;;,. ii; ii; ;;';I;".;j Ii
ATOD_done_int:
PUSHF
ORB
ANDB
LDB
ADDB
LDBZE
ST
AL.
AH.
DL.
DX.
AX.
CMPB
.JNH
CMPB
.JE
INCB
AL. #OIOOOOOOB
no_rnd: LDB
CLRB
ST
INCB
ANDB
neKt:
Portl. #OOOOOIOOB
i . , . ; ••
i
IJ
•••
; . j ; ; i oj
• j ; . i • • • , . j; I i oj
j
i;
; 1 . ; ' i , i , . i •• • , ; , ; i"
; Set PI 2
AD_RESULT_LO.#ll000000B
AD_RESULT_HI
AD_NUM. AD_NUM
DL
RESULT_TABLECDXJ
Store
no rnd
i
j,
Load low order result
Load high order result
DL; AD_NUM *2
r~sult
indeKed by DX
; Round up if needed
Don't increment If AH~OFFH
AH:-#OFFH
no_rnd
AH
~
l'
AL. AH
; Align byte and change to word
AH
AX. ON_TIMECDX]
AD NUM
AD::::NUM. #03H
""
CD
Keep AD_NUM between 0 and 3
ADDB
AD COMMAND. AD NUM.
ANDB
POPF
RET
Port!. IIllII10llB
-
N
-
#IOOOB
; Start conversion on channel
i
indIcated by AD_NUM register
; Clear PI. 2
END
NO ERROR (5) FOUND.
270061-90
l
SERIES-III MCS-96 MACRO ASSEMBLER. VI 0
SOURCE FILE: :F3.SWPORT.A96
OBJECT FILE: :F3:SWPORT.OBJ
CONTROLS SPECIFIED IN INVOCATION COMMAND:
ERR LOC
LINE
OBJECT
1
NOSB
SOURCE STATEMENT
$TITLEI'SWPORT.A96: SOFTWARE IMPLEMENTED ASYNCHRONOUS SERIAL PORT')
2
3
4
~
=1
=1
6
7
B
56
This module provides A 50ftwa~e implemented a5gnch~onous serial port
for the 8096.
HSD. ~ 15 used for transmit data.
HSI.2 is used for
receive data. Note: the choice of HSO.:5 and HSI.2 is arbitraru).
$INCLUDEIDEM096. INC)
Turn listing off for include file
$nolist
End of include file
en
o
~7
0000
en
<»
I\)
0000
0001
0001
0002
0004
0002
0003
0004
0006
OOOB
OOOA
oooe
0035
0015
001B
5B
59
60
61
62
63
64
65
66
67
6B.
- 69
70
71
72
73
74
75
76
77
7B
79
BO
B1
B2
B3
B4
B:5
B6
B7
:!I
:c»
VARIABLES NEEDED BY-THE SOFTWARE SERIAL PORT
T"seg
josl_save:"
Tcvo_state:
rn:rdtj
rnOverrun
rip
rcvD_buf:
t"eve_reg:
sample_time:
dsb
dsb
equ
equ
-equ
dsb
dsb
do..
serlal_out:
d ....
baud_count:
ds ..
txd_time:
ds ..
char:
d.b
»"
Used to save contents of iosl
1
2
4
1
1
1
::rJ"
indicates receive done
indicates receive overflow
i
receive in progress flag
used to double buffer receive data
used to deserialize receive
records last receive sample time
Holds the output character+framing (start and
J
stop bits) for transmit process.
Holds the pe~10d of one bit in units
of Tl ticks.
Transition time of last Txd bit that was
sent to the CAM
faT' t@st only
COMMANDS ISSUED TO THE HSO UNIT
mark_command
space_command
sample_command
SeJect
equ
equ
equ
011(>101b
0010l0lb
001'1000b
tirnerl.5et. interrupt on ~
timerl,clr,interrupt on 5
software timer 0
270061-91
mm
enz
me
::rJ-><
~n
o"
::rJ
-I
•l'
N
t
20BO
20BO
20BO
20B1
20B5
20B8
20BD
20BE
FA
A1F0001B
C9C012
EFOOOO
Bl6COB
FB
R
20BF.
BB
B9
90
91
92
93
94
95
96
97
9B
99
100
101
102
103
104
'10~
cp
~
OOOD
20BF B10DOC
2092
2092 ACOC1C
2095 C81C
2097 EF3000
209A
209D
209F
20Al
20AI
20A3
20A5
20A5
20AT
20A7
20AA
20AD
20AF
2002
2005
990DOC
D706
011-(;
R
R
R
R
071C
D7FC
170C
EF4400
9B001C
DFE3
EF4COO
DOICOC
27DB
R
R
R
R
106
107
lOB
109
110
111
112
113
114
115
116
117
118
119
120
121
122123
124
the program ~il1 initialize the
the software serial port and run a simple test to elcereile it.
di
.ld
push
call
ldb
ei
sp •• OfOh
.4BOO
5etup_5eTi~1-port
int_mask ••OU01100b
serial,
511ft,
hso, hsi
t"st1:
A simple test of the serial port routines.
While no characters are received an' incrementing pattern i5 sent to the
lier1..-1 output.
When a cha1'acteT is received tbe incrementing patt.ern
"Jumps" to the- character ".ceved and p-roceeds from the"e.
CR
1db
tRstlloop:
Idbze
push
call
e'lu
ODH
·char. KR
Carriage re-turn
ai, choar
);0
a.
'V
I
char _out
cmpb
bn"
clr
a.
inc
bne
ax
pause
incb.
char
call
cmpb
be
call
Idb·
br
cst.
al.O
test1100p
char ••CR
nopa,:,s.
N
.IIo-
m
Pause on Carriage return
pause:
nopause:
te.t2:
12~
126
127
128
129
130
131
(
cseg at 20aOh
reset lac:
Th.-a096 starts executing here on reset,
chaT ready?
loop i f not
char _in
char.al
testlloop
$eJect
270061-92
0000
0000
%
",.
0000
0002
0004
0008
OOOC
OOOF
0012
001:5
0018
CC22
CC20
Al07001E
A120AliC
8C201C
C0081C
C00600
81601b
3EI:5FO
0018
OOIF
0022
0025
0027
0029
0028
oo2E
44140AOA
813:50b
AOOA04
1102
1103
1101
EF4800
E322
R
R
R
R
R
R
R
0030
0030
0032.
0034
0037
003A
003A
0030
003F
0042
CC22
CC20
810121
b42020
88000b
07F8
C00620
E322
R
R
0044
0044
004b
0049
004B
004B
004C
OIIC
300102
071C
FO
R
132
133
134
135
13b
137
138
139
140
141
142
143
144
14:5
14b
147
148
149
1:50
151
1:52
153
1:54'
1,:5:5
15b
157
158
159
160
161
1'62
l,b3
164
165
16b
167
168
169
170
171,
172
173
174
175,
176'
177
178
179
180'
l
cseg
setup_spr,al_port,
Called on system reset to intiate the software serial port
pop
pop
Id
Id
tfivu
st
st
Idb
bbs
add
ldb
Id
clrb
clrb
clrb
call
br
CI
bl
dl.1I0007h
al.IIOA120h
ax,bl
the return address
the baud rate
(In deCimal)
dl:al:=500.000 (assumes 12 Mhz crystal)
calculate the baud count (SOO.OOO/baudrate)
ax. baud_count
O,serial_out
clear serial out
1ocl.IIOll00oo0b • Enable HSO,:5 and Txd
'10.0.6.$
i
Wait for room in the HSO CAM
and issue a MARK command.
txd time,timerl,20
hso:cammand,.mar'_command
hSD_time, tid_time
rcv __buf
clear out the receive variables
reve_reg
l'c:vR_state
1nlt_rIPcIP1vIP
SIPtup to detect a start bit
[CI]
return
~
$eJect
~
char _out·
Output character to the software serial port
pop
pop
Idb
add
",a 1 t_for xmlt:
cmp
",b,ne
st
br
ex,
b'l
(bl+l).IIOlh
b I. b I
se1'1al Qut.O
..a; t_for _"m; t
bx,serial _out
[c I ]
OJ
tbe return address
the character for output
add the start and stop bits
to the-char and leave as 16 b,t
wait for serial _out=O (it ..ill be cleared by
the hso interrupt process)
put the formatted character in serial_out
return to caller
csts:
Returns "true" (ax<::>O) if char_in has a character.
C
11'
bbc
inc
ests_elit:
ret
ax
l"cve_state, 0, ests __ex i t
ax
char _in:
270061-93
004C 3001FO
R
004F F2
0050
0053
0056
0057
71FEOI
AC021C
F3
FO
R
R
0058
2006
200b 5800
en
a,
01
0058
0058
0059
005C
005F
0061
00b4
006b
0066
0069
006C
006E
006E
0071
F2
b4080A
88000b
OFOO
08010b
OB08
B11506
AOOA04
200b
81350b
AOOA04
R
181
182
183
184
185
18b
187
188
189
190
191
192
193
194
195
196
197
198
199
200
G~t
bbe
pushf
andb
Idbze
popf
ret
SeJeet
hso isr
F;eldS the hso interrupts and performs the serializatIon of the data
Note: t~i5 routine would be Incorporated into the hso service strategy
for an actual system.
[seg
dew
203
204
be
R
20:5
202
209
210
211
shr
be
send_spac e:
Idb
Id
br
; Set up vee tor
hso_isT
tId_time, baud_count
serial_out/O
if character is done send a mark
s~nd_mark
serial_out,
tn
else send bit 0
send_mark
»
of serial_out and shift
'P
serial_out left one place.
N
.".
CD
h so_.c ommand •• 5 pac e _C ommand
hso_.time. txd_tlme
hSD iST'_exit
send_mark:
Idb
Id
212
R
at 2006h
cseg
pushf
add
emp
201
R
wait for character ready
rcve_state,O,char_ln
• set up a critical reglon
rcve_state,*not(rxrdy)
aI.rcve_buf
leave the critical region
i
R
R
206
207
208
(
a character from the software serial port
213
h~o_command,.maT'k_command
hso_time, tId_time
214
215
216
217
218
219
220
0074
0074 F3
0075 FO
0076
221
222
007b
0079
007C
007C
007F
0082
0085
223
224
810015
812003
901bOO
370008
BOOblC
A0041C
R
R
225
22b
227
228
229
230
hSD iST_elit:
popf
ret
.eJect
Inlt receive:
Called to prepare the serial Input process to find the leading edge of
a start hit
Idb
Idb
ioeO.1I0000000Qb
hsl_mod~.1100100000b
disconnect change detector
negative edgeG on HSI 2
f 1 ush_f i fo.
orb
bbe
Idb
Id
iost_save, iosl
iost_save. 7, flush._fifo_done
aL hSi_status
ax, hsi time
; traGh the fifo entry
270061-94
00C3
00C3
00C6
00C8
OOCA
OOCA
OOCD
OOCF
OOCF
0002
0005
0008
0000
0000
OODE
OOEO
OOEO
00E3
00E6
00E9
OOEC
OOEE
:h
--.j
OOFO
OOFO
00F3
00F6
00F9
350604
2FAE
2032
910401
2021
R
3F010E
180103
350603
918003
R
R
751001
2010
3506FD
B00302
910101
710301
2F68
200C
3F15FD
B11806
640804
C00404
OOFC
OOFC F3
OOFD FO
OOFE
ASSEMOLY COMPLETED.
R
R
R
R
R
R
R
281
282
2B3
284
285
286
287
2BB
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
30B
309
310
311
312
313
314
315
316
317
l
proces&_start_bit:
bbc
hsi_status,5, start_ok
call
tnit_receive
br
software_time~_exit
start_ok:
orb
br
rcve_state •• r1p
schedule_sample
set receive in progress flag
process_data:
bbs
shrb
bbc
orb
data zero:
addb
br
check_stopbit:
bbc
Idb
orb
andb
call
br
rcve_state,7.check_stopbit
rcve_reg,.l
hsi_status.5,datazero
rcve_reg •• BOh
; set the new data bit
rcve_state,#10h
increment bit count
schedule_samp Ie
hsi status.5.$
DEBUG ONLY
rcve_buf,rcve_reg
~cve_5tate,.rxrd~
rcve_state,_03h ; Clear all but ,ready and overrun bIts
init_Teceive
software_timeT_exit
~
;!!.c.
schedule_sample:
bbs
i050,7,$
; wait for holding reg empty
ldb
hso_command,#sample_command
add
sample_time,baud_count
st
CD
sample_time.hso_time
software_timer_exit:
popf
ret
end
NO ERROR(S) FOUND.
270061-96
l
SERIES-III MCS-96 MACRO ASSEMBLER. VI 0
SOURCE FILE. :F3:MOTCON.A96
OB.!ECT FILE. : F3: MOTCOI~. OB.!
CONTROLS SPECIFIED IN INVOCATION COMMAND:
ERR LOC
OB.!ECT
OOIE
003C
0069
m
00
0')
006E
OOFA
OOFA
OOFF
OOFF
0·080
04BO
0064
0010
0024.
0024.
0028
LINE
I
2
3
4
5
6
7
=1
8
=1
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
NOSS
SOURCE STATEMENT
$TITLE ('MOTCON.A96:
Motor Control Example Program')
USE WITH C-STEP
O~
late~
pa~ts
December 20,
1984
s:
$INCLUDE(DEM096. INC)
Sno11st
Turn listing off for include file
End of ~nclude file
;;, i;;;;;;;
Initial Values
min_h'sil_t
~
o
; min period for PHA edges In model before mode2
:z:I
e'lu
30
min_hsi_t
e'lU
2*min_hstl_t
; min period for PHA edges in medeO before model
0»
0."
max_hsil_t
e'lu
3*min_hsl1_t + min_hsil_t/2
Z'"
.; max period for PHA·edges in model before madeO
HSOO~dl~-PD~iod e'lu
5wtl..:..dlVJoriod _qu.
equ
swt2_dlv-pcriod
rnaxJower
max_brake
maximum_hold
equ
equ
equ
brakeJnt
posltionJnt
velocitv-pnt
equ
equ
equ
110
250
250·
Offh
Offh
080H
1200
delav for HSO timer 0 (timed count of pulses)
min peTiDd. ~OT ~ T2 clocks before mode 1
dela~
d~lay
for software timer 1
for software timer 2
oc
1)(
"'C
:z:I
oC)
100
16
:z:I
»
s:
RSEG at 024H
tmp:
timer _2:
-1 m
:z:IZ
dsl
dsl
270061-97
~
13
N
.1:10
c»
_.
002C
0030
0034
0038
003C
0040
0044
0048
en
CD
<0
004C
004E
0050
0052
0054
0056
0058
005A
005C
005E
0060
0062
0064
0066
0068
0069
006A
006B
-006C
0060
006E
006F
0070
0072
0074
0076
0078
007A
007C
007E
0080
0082
0084
0086
0100
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
'127
128
129
130
131
132
133
134
135
tm .. 2_Dld:
position:
des_pos.
pas_err
delta_p.
time.
des time:
time_err:
dsl
dsl
dsl
dsl
dsl
dsl
dol
dsl
II
cf
$E.JECT
last _t
Im@ .~err
last_pas_err.
pos_delta.
time_delta
Idst_pos.
lastl time:
last2_tlme.
boost:
tmpl :
Dut_p t ...
offset.
nxt_pos:
Tpwr:
old t2:
di .. ect:
pwm_dir:
dsw
dsw
dsw
dsw
dsw
dow
dow
dsw
dsw
dsw
dsw
dsw
dsw
dsw
dsb
dsb
dsb
dsb
d·sb
dsb
hsi sO:
last - stat:
pwmJwr:
iosl_bak:
TR_COL:
DSB
main_dl~:
dsb
rna.Jlllr:
dsw
dsw
dsw
dsw
dsw
dsw
dsw
dsw
dsw
dsw
dsw
dsw
max_b .. k:
max_hold:
vel _pnt:
b .. k_pnt:
pDs_pnt:
HSOO_dly:
swtl _dly:
swt2_d Iy:
min_hsi:
min_hsil:
max hul:
-
~
"U
l=.forward,
•
I\)
O=reverse
I I ""
~
;
COLLECT TRACE IF TR_COL=OO
dseg at 100H
270061-98
0100
0102
0104
cp
~
2000
2000
2002
2004
2006
2008
200A
200C
200E
0022
1020
0424
8022
1020
2022
1020
1020
2010
2010
2010
2010
2080
2080 AIFOOOl8
2084 DIFF17
2087
2089
2080
208F
2092
2095
1168
A170175C
055C
E068FD
88005C
02F6
2097 BIFFOF
209A DIFFIO
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
-183
184
185
mode_vie..,:
count_out:
err _view:
l
dsb
dsw
ds ..
$eJect
cseg
PINtI
PORT
FLAG USAGE
22
23
24
25
26
37
38
39
40
45
PI. 0
modeO 0
at
de ..
de ..
de ..
dew
de ..
de ..
dew
de ..
PI 1
PI 2
PI 3
PI. 4
PI. :5
PI. 6
Pl.7
P2. 6
P2. 7
o
model
mode2
or 0
o
software timer 2 routine enter/leave
Main' program toggle
HSI overflo .. toggle
software timer 0 routine enter/leave
hsi_int enter/leave
software timer 1 routine enter/leave
Input di1'ectlon (O=reverse. l=forward)
direetlon O=rev, l;::fwd
2000H
timer ovf _int
atod_done_int
hsi data tnt
hso=.xec:=int
hsi_O_int
~
2:
~
soft_tmr _int
ser _port_jnt
extern.l_int
CO
atod_done_int;
hsi_O_int;
seT _port_jnt:
external int:
cseg
at
2080H
init;
Id
Idb
sp.tlOFOH
pwm_control,AOFFH
elrb
Id
dec
dJnz
emp
Jyt
direct
tmpl.tl6000
tmpl
direet.$
tmpl, zero
ldb
portl. tlOFFH
port2.tlOffH
dela~;
Idb
;
wait about 3 seconds for motor
to come to a stop
; wait O. ~12 milliseconds
dela~
270061-99
2090 812516
20AO 71FeOF
20A3 019903
20A6 015715
20A9 A00400
20Ae 0140
20AE 0142
2080 0128
0>
iasl_bak.IOSI
iasl_baL ~, tmr lot_done
ti.me f 2
.
los1_bak •• ll011111B
,..~
clear bit :;
CD
tmr _1 nt_done·
popf
ret
; End of timer
int~TTupt
routine
266
267
268
269
270
271
272
273
274
275
276
2220
2220
2220
2221
2224
2224
2227
F2
901660
306003
71FE6D
222A
222A 316006
2220 71FD6D
277
278
279
280
281
282
283
284
285
,;,
i ; , ; ; ; i ; i ; ; ; i i ; ; ; ; ; i ; ; , i i ; i , ; ; ; ; ; ' ; ; ; , ; i ; ; ; i ; ; ; j ; ; i ; ; ; ; , i , ; ; ; ; •• , ; ; ; ; ; ;
SOFTWARE TIMER INTERRUPT SERVICE ROUTINE
i , ; ;;
;.;,; iii;
i,; ,;,;,; ; ; ; i ; ; ; ; ,;,; j;;,;;,; i,;;;,;;,; ;'; ;,; i , ; ; , ; ; ; , ; ; , ; ; ; , , ; , ; , ; , ; ; ; ; ; , ; ; , ; j;,;,;,; j,; ,;,; ,;
I
,;;
,;;
j i
i
CSEG AT 2220H
soft_tmr _int
pushf
orb
chk_swtO:
JbC
andb
cali
chk_5wtl:
Jbc
andb
iosl_bak.IOSI
1os1_bak.0.chk_swt1
1os1_bak •• l1111110B
swtO_expil"ed
Clear blt 0 - end swtO
los1_bak.1.chk_.wt2
iosl_bak •• llllll01B
Clear bi t
1
2700S1-A1
2230 EFCD03'
2233
2233
2236
2239
223C
223C
223F
326D06
71F06D
EF4401
346D03
71F760
2242
2242 F3
2243 FO
286
287
288
289
290
291
292
293
294
29:5
296
297
call
chk_swt2:
Jbc
andb
call
chk_swt3:
Jbc
andb
call
l
swtl_eXplred
!osl_bak.2.chk_swt3
iosl_bak •• 111110110
swt2_expired
1os1_bak.4. s~t_lnt_done
iosl_bak •• 111101110
swt3_expired
; Clear bit 2
Clear bIt 3
swt 1nt_done:
popf
ret
298
• END OF SOFTWARE TIMER INTERRUPT ROUTINE
299
2280
2280
m
tb
W
2280 F2
2281 013006
2284 447COA04
2288 91200F
2288 AOOC28
228E 390F18
2291
2291
229:5
2299
229B
2290
229E
22Al
22A4
22A7
486628:5C
890200:5C
D94C
300F49
71FCOF
01:5:51:5
00006B
203E
22A9
22A9 482C283C
22AD A0282C
22BO 306808
300
301
302
303
304
30:5
306
307
308
309
310
311
312
313
314
31:5
316
317
318
319
320
321
322
323
324
32:5
326
327
328
329
330
331
332
333
334
33:5
$eJect
•••••••••••••••••••••••••.••••••..••••••••..•••..•..•.••••.•••.•••.•••.• ; ••••
SOFTWARE TIMER ROUTINE ()
NOW USING HSO 0 TO TRIGGER
.;; •• ;;;; •••• ; •.• ;;.;; •••••••••• ; •.•.•.•.•......••.••••........•.•.•.••••••..
; ,i,;
I
CSEG AT 2280H
.
hSD_elCeC_lnt.
Check mode'-
Update position In mode 2
:J>
'tI
I
PUSHF
ldb
add
HSO_COMMANO •• 30H
HSO_TIME.TIMERI.H500_dly
orb
ld
Jbs
Portl, 1, io_mode2
portl •• 001000000
Timer_2.TIMER2
I\)
~
CD
set Pi.:5
in_model:
sub
cmp
Jh
set_mod"O:
Jbc
andb
ldb
ldb'
br
tmpl.Timer 2.old t2
tmpl •• 2
-
Check count difference in tmpl
end_swtO
Portl,O,end_swtO
Portl •• l1111100B
IOCO.IIOI0I0101B
last_stat. zero
end_swtO
if alread~ in mode a
Clear Pl,O. PI. I (set mode 0)
enable all HSI
in_mode2:
sub
Id
delta-p. tim"r_2. tmr2_old
tmr2_o1d. tim"r_2
Jbc
direct,O, in_rev
get timer2 count difference
270061-A2
2203 643C30
2206 A40032
2209 2006
22BO 683C30
220E A80032
22Cl
22Cl 4866285C
22C5 8905005C
22C9 D21C
22CO
22CB
22CE
22Dl
2204
2207
71FDOF
91010F
BI0515
A00400
48840A56
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
in_f .. d:
in_rev:
position+2, zero
chk_mode
sub
pos1tian.delta-p
'lube
position+2. zero
chk_mode:
sub
cmp
Jgt
set_model:
andb
orb
Idb
Id
sub
354
2200
220B A00400
220E 717F6D
cp
cg
22El 90166D
22E4 3F6DF4
22E7
22E7
22EA
22ED
22EE
A02866
71DFOF
F3
FO
2380
2380
2380 F2
2381 013A06
2384 44800A04
238891040F,
238B 89FF075E
238F DI04
2391 AIF0015E
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
l
pas1tion.delta~p
add
addc
br
tmpl.T1mer_2.ald_t2
tmp 1 •• 5
end_s .. tO
Check count difference in tmpl
set model if count 15 too low
count <- :t
Portl •• llllllOlB
i
Char PI. 1. s"t PI. 0 (s .. t mode 1)
Partl •• OOOOOOOIB
IOCO ••OOOOOIOIB
"nable HSI 0 and 1
' .. ra. HSI_TIME
Iastl_time,Tlmerl,min_hsil
set up so (tim,,-last2_tim,,»min hsil on next HSI
SE.JECT
c 1 r _hs 1.
Id
andb
orb
Jb s
end_s .. tO:
Id
andb
POPF
r"t
ZERO. HSI_TIME
iosl_bak •• Ollll111B
clear bit 7
~
iosl_bak.l0s1
iosl_bak,7.clr_hsl
If hsi is trlggered then clear hSl
old_t2. l'IMER_2
portl •• ll0llll10
clear P1.5
CII
; , i i ; i ; ; ; ; ; ; i ; ; ; ; , ; ; i i i i i ; ; i ; ; ; ; ; ; i i i ; ; ; ; ii i i ; ; ; ; i i i ; ; i i i i ; ; ; ••
SOFTWARE TIMER ROUTINE 2
iii;;;
.,.~
; i i ; ; i ' i ; ; i ; i i i , ; ; ; ; ; ; ; i i , ; ; ; ; ; i ; ; ; ; ; ; ; ; oj ; i ; ; " ; ; ;
;.o
i i , ; " , ij;:,
;i, ,j,;
ij
I
iii
i ; i ; i j i i i ; ; ; i i i ; : i i i i ; i to;:
CSEG AT 2380H
s .. t2_... pired:
pushf
ldb
add
arb
cmp
bnh
Id
hsa_cammand •• 3AH
hsa_time.t1merl.s .. t2_dl~
set s .. t_2
partl •• OOOOOlOOB
aut-ptr •• 7ffH
pul,.1ng
aut-ptr •• 1fOH
set -part 1. 2
270061-A3
2395
2395 306EOC
239B C25F32
2398 C25F30
239E C25F6B
23AI C25F6C
23A4
23A4 4B560A5C
23AB 8900185C
23AC 0104
23AE
23B2
23B2
23B5
23B6
65001056
71FBOF
F3
FO
m
tb
01
3B6
3B7
3BB
3B9
396
391
392
393
394
39:5
396
397
39B
399
400
401
402
403
404
40:5
406
407
40B
409
410
411
412
413
414
415
2400
2400 20CE
2402 20C7
2404
2405
240B
240B
240E
F2
91400F
717F60
901660
3760Fl
2411
2411 AOOC2B
2414 5155066A
241B A00440
241B 380FE2
241E
241E 3B6AOB
416
417
41B
419
420
421
422
423
424
425
426
427
42B
429
430
431
432
433
434
435
(
pulsing:
Jbc
tr_col.0.swt2_don"
st
st
position+2. [out_ptrl+
st
st
direct. [out_ptrl+
position high,
position low
position. [out_ptrJ+
pwm_pwr. [out_ptr]+
store B bytes
swt2_done:
sub
cmp
externall~
tmp 1, timert. lastt_time
tmpl.IIIBOOH
swt2_ret
Jnh
add
5wt2_ret:
andb
popf
ret
;
keep
(Timerl-lastl_tlme)<2000H
lastl_tlme.~1000H
portl.811111011D
;
clear pOTtl.2
$EJECT
;; j;,;i.
j
j,;i ,i,;
j
j;
i,.
i ; i i i " ; 1 i ••
j
):0
"C
i • • • " . I i i •• j • • • • • , . " , ; • • • • • • • • • II • • • • • •
HSI DATA AVAILABLE INTERRUPT ROUTINE
i,"-j;;; • • i ; i i
j. j
••
i ; ; ii i ,
j ; •• Ij
,i,
j;"
j II •• j
•• " ' "
II
I
i.,
I\)
j . , . , , . i , •• , • • • • • • • " .
""
CO
This routine keeps track of the current time and position of the motor
The upper word of information is provlded by the timer overflow routine
CSEG AT 2400H
br
br
no_inti:
now_mode 1:
hSl_data_lnt:
orb
andb
orb
Jb c
in_made
no_int
used to save executIon t1me for
worst case loop
pushf
portl •• OIOOOOOOB
iosl_bak •• OlllllIIB
s"t Pl. 6
Clear iosl_bak.7
iosl_bak, iosl
iosl_bak,7,no_intl
If hsi is not trigg"red then
Jump to no_int
get_values:
ld
andb
ld
tlmer _2. TIMER2
hsi_sO.H51_5TATU5 •• 0101010IB
time. H5I_TIME·
Jbs
portl,O,now_mode_l
In_mod"_O:
Jbs
;
Jump If in mode
h&i_SO, 0, a_rise
270061-A4
~
2421
2424
2427
242A
3A6A2C
3C6A40
3E6A5A
2094,
242C
242F
2432
2435
2438
A05658
A04056
685840
888240
0906
243A
2430
2440
2440
2443
2446
2449
244C
244E
91010F
BI0515
3E6B58
3C6B67
3A6B50
980068
OF46
27B2
2450
2453
2456
2459
245C
A05658
A04056
685840
888240
0906
245E 91010F
2461 BI0515
2464
2464
2467
246A
2460
2470
2472
3C6837
3E6B43
386B2C
980068
OF22
2057
2474
2477
247A
2470
2480
2482
386B27
3A6B33
3E6BIC
98006B
OFI2
2047
2484
2487
248A
2480
2490
3A6BI7
386B23
3C6BOC
98006B
OF02
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
Jbs
Jbs
Jbs
br
ld
ld
sub
cmp
Jh
; Sltt madelorb
ldb
tst_statr:
Jbs
Jbs
Jbs
cmpb
Je
br
a_"ise:
a_fall:
i
Id
ld
sub
cmp
Jh
I I(
hst - sO. 2. II_fall
h.t sO, 4, b_ri 5e·
hoi sO. 6. b_fall
no_cnt
last2_tlm., last I_tim.
Jasti_time. timetime.last2_tiftll.
tim., min_h!li
tst_statr
Set PI,O (in mode I)
Enllble HSI 0 and I
Portl •• OOOOOOOIB
IOCO •• 00000IOI8
lllst_stat.6. going_'wd
last_stat. 4, going_rev
last_stat.2.change_dir
last_stat. zero
first_time
no inti
first time in mod eO
last2_time, Jasti_time
lastl_time. time
time.last2_time
»
"U
time, mio_hsi
tst_statf
II
set modeI-
orb
Idb
SEJECT
tst_statf.
jbs
jbs
Jbs
cmpb
je
br
-
b rIse.
b - fall:
jb s
jbs
Jbs
cmpb
Je
br
Jbs
Jbs
Jbs
cmpb
Je
Portl •• OOOOOOOIB
IOCO •• OOOOOIOIB
Set PI 0 (In mode I )
Enable HSI 0 and I
last _stat,4. going_f~d
last_stat.6,golng_"ev
last_stat. O. change._dl"
last._stat. zero
first_time
no int
first time In modeO
-
last_stat.O. going_fwd
last_stat, 2, gOln'g_rev
last_stat,6,change_dir
last_stat, zero
first_time
i
first time in modeO
-
no int
last_stat. 2. going_fwd
last_stat,O,going_rev
last_stat, 4, change_dir
last_stat. zero
first_tim ..
first time in modeO
270061-A5
•
N
.0CD
_.
2492 2037
2494
2494 C461l6A
2497 2072
2499
2499 1268
2491l 3068PF
249E
249E
24AI
24A4
24A8
24AB
24AO
24AO
24BO
24B3
24B7
O'J
cO
--J
24BA
241lA
24110
24110
24CO
24C3
24C6
24C9
914010
1110168
65010030
A40032
2000
71BFI0
1110068
69010030
A80032
C461l6A
A0282C
7l7F60
901660
376002
2746
24CIl 71BFOF
24CE F3
24CF FO
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
503
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
br
stb
br
change_dir"
notb
Jb c
no - inc:
2400
2400 51506A5C
2404 07EA
2406
2406 A05658
2409 A04056
240C 4858405C
24EO 88845C
I I
hSI sO, last_stat
cf
add delta posItion
done_chk
direct
dlrect,O, going_rev
going_fwd:
orb
ldb
add
addc
br
gOing_rev:
andb
ldb
sub
subc
-
PORT2 •• 01000000B
dlrect,ttOl
position •• Ol
pos1t1on+2. zero
st stat
set P2 6
direction
PDRT2 •• IOII111IB
direct,ttOO
clear P2.6
directIon ~ reverse
forward
-
position.#Ol
positlon+2. zero
»
'"0
st stat:
stb
load lasts
ld
-
hsi sO. last_stat
andb
again.
orb
Jbc
br
get_values
no lnt-
andb
portl •• l011111IB
popf
ret
,.
N
tmr2_Qld, timeT_2
iost - bak •• 01111111B
iDS! - bak,los1
ios! bak.7.no int
no_cnt.
521
522
523
524
525·
526
527
528
529
530
531
532
533
534
535
no iot
first_time.
;
ell' bit 7
;
Clear PI 6
I I ""
!XI
-
end of hSl_data- Interrupt routine
Routine for mode I follows and then returns to "load lasts"
$EJECT
In_mode
1
mode I
fiSI
tmpll
Jne
no_cnt
Procedure which sets mode I also
sets tImes to pass the tests
c:mp_ tIme"
cmp I.
routine
hSl_ sO.IIOIOIOOOOB
andb
Id
ld
last2_time,lastl_ttme
lastl tIme. tIme
sub
cmp
tmpl, tIme. last2_time
tmp 1, min_hsi 1
-
270061-A6
24E3 D914
24E5
24E5
24E8
24EO
24EE
24Fl
24F4
24F7
91020F
010015
A00400
717F6D
90166D
3F6DF4
2012
24F9
24F9 4858405C
24FD 88865C
2500 DI09
2502
2502 71FCOF
2505 015515
2508 000068
Ol
~
2500
2500
250F
2512
2512
2515
2518
251A
251A
251D
2520
482C283C
306808
643C30
A40032
27A3
683C30
A80032
2798
2600
2600
2600 F2
2601 91800F
2604 BI0D08
2607 B13906
260A 447EOA04
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
:!84
58:!
Jh
l
chee k_max_t im.
set_moda_2:
mt_hsi:
orb
ldb
ld
andb
orb
Jbs
br
check_mill_time:
sub
cmp
Jnh
Portl •• 000000l0B
10CO •• 00000000B
zero.hsi_time
iosl_bAk.•• 01l11111B
Set PI 1 (in mode 21
Dlsable all HSI
empty the hsi fifo
i
clear bit 7
tasl_bak.10s1
jos1_bak. 7, mt_hsi
;
If hsi is triggered thenr clear hsi
done_chk
tmpl, time. last2_time
tmpl.max_hsil
max_hsi = addition to ml·n_hsi for
total time
dona_chk
set_made_O:
andb
ldb
ldb
Portl •• l111l100B
IOCO •• Ol0l0l0lB
last_stat. zero
clear Pl.0. 1 set mode 00
Enable dll HSI
done_ch k:
sub
Jbc
delta-p. timel"_2,tm1"2_o1d
dil"ect,Q,add_l"ev
add
addc
position.delta-p
position+2. ze1"O
br
load_lasts
;
»
get timer2 count1difference
'P
add_fwd:
N
.j:o,
OCI
add_rev:
sub
position.delta-p
subc
position+2,zero
br
load_lasts
$eJect
, . , ' i,,; ..... ,;",,;"
'"
•.• ,
j.,
,.".;1 """"
i •• oi i , . .
II
II II
oj
i •• , . , •• • , . ; . j
SOFTWARE TIMER ROUTINE 1
II;
" . , , . i I I " ; ' i , , , , i oi
" ; , , . , . , i ;, ••
i i I'"
II""
j.
.• " . , . i. Ii
;,;;i;; i".i""
••• " . " , . ; .
j,
CSEG AT 2600H
swtl_expired:
pushf
orb
portl.810000000B
ldb
int_mask ••000011010
ldb
add
HSO_COMMAND •• 39H
;
set port1.7
enable HSI.
Tovf. HSO
HSO_TIME.TIMER1.swtl_dl~
270061-A7
260E
2611
2614
2618
2610
261F
A0464A
A0363A
48404448
A8424A
4830343B
A8323A
2622 FO
2623 48484C52
2627 A0484C
262A 48384E50
262E A0384E
<»
tb
to
2631
2631 88003A
2634 0600
2636
2636
2638
263B
263F
.2641
033B
910069
89FFFF3A
070A
20()0
2643
2643 910169
2646 88003A
2649 OF05
2649 90706C
264E 2051
2650
2650 887A38
2653 011E
2655 887838
586
587
58B
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
60B
609
610
Id
Id
sub
5ubt
sub
subc
Cal~ulate
l
time & position error
values are set
tlme:err+2.t1me+2
_pos_eTr,des_postposition
pos_err+2,po5ition+2
EI
sub
Id
time_delta.last_time_err.time_err
last_time_err. time_err
sub
Id
pos_delta.last-pos_err.pos_err
last-pos_erT.pos_err
Time_err c Desired time to finish - current time
Pos_err
Desired position to finish - current pos1tlon
Pos_delta
Last positlon error - Curent pOSItion error
Time delta = Last time error - Current time error
n;te that eTrors should get smaller 50 deltas 'WIll be
positive for for~ard motion (tIme 15 always forward)
; ; ; ;;
iii;;
i;, ;;
i i i ij
;, ";
;; i ; i
.
:J>
chk_dir:
cmp
Jge
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
62B
629
630
631
632
633
time_err+2,des_time+2
pOi_err+2,des_pos+2
time err, des time. time
go_backward:
neg
Idb
cmp
Jne
br
'U
pos_err+2, zero
go_forward
N
~
OCI
pos_err
Pas_err
A9S VAL (pos_err)
pwm_dir •• OOh
pos_err+2 •• 0ffffH
Id_mal
chk_brk
go_forward:
Idb
cmp
Je
pwm_dir •• OlH
pos_err+2. zero
chk_brk
"E.JECT
Id_mal.
Idb
br
Chk_brk.
cmp
Jnh
cmp
pwm_pwr,max_pwr
chk_sanit~
PosItIon_Error now
ADS(pos_errl
p05_err'PQ5_pnt
hald-posltion
,posltl0"_error(posltion_control_polnt
pos_err. brk_pnt
270061-A8
2658 09FI
265A
265A
2650
265F
2661
2661
2664
880050
0602
0350
887650
0100
2666
2669
266C
266E
B0726C
B06824
1224
B02469
2671 2030
2673
2673
2677
2679
267B
2670
~
g
267F:
267F
2683
2686
2689
268B
2b8F
2692
2694
2696
2699
269B
269E
89020038
0906
0126
015A
201F
50FF7424
6C3824
880050
0709
650400SA
b45A26
2002
01SA
887426
0103
A07426
B0266C
2bAl
26Al 2000
26A3
26A3 B06C64
26A6 1264
26A8 38690A
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
6:53
6:54
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
Jh
Id_max
l
POSltlO"_erTor>brake_polnt
braking'
cmp
Jg e
ne9
chk_delta:
cmp
brake
pos_delta, zero
chk_delta
pas_delta
pos_delta,vel_pnt
velOCity
Jnh
hold_position
Jmp
Idb
Idb
notb
Idb
pwm_pWT. max_bTk
tmp. direct
tmp
pwm_d 1 r, tmp
br
Id_pwr
Hold_position
cmp
Jh
clr
clr
DR
calc_out:
mulub
mulu
cmp
Jne
add
add
br
no_bst: CIT
ck_max:
cmp
maled:
output:
Id
ldb
Jnh
if
=
pos_delta/sampJe_tlme
ABS(veloclty)
~
vel_pot
If braking apply power In Opposite
direction of current motion
position hold mode
pD5_err •• 02
1 c_out
tmp+2
boost
output
Col
if position error
<
2 then turn off power
J>
tmp,max_hold,*255
tmp" pos_err
pos del ta, leTO
no_bst
boost. 1104
tmp+2.boost
,
Tmp
pos_err
*
'P
N
max_hold
it
Boost. is integral control
TMP+2 = M5B(pos._err*max_hold)
ck_rnax
boost
tmp+2,max_hold
output
tmp+2.max_hold
pwm_pwT, tmp+2
chk_sanlt~:
br
Id_pwr
Idb
notb
Jb 5
rplLll',
;;
i.
$E.JECT
ldJl"'r.
rpwr.pwm_pWT
pwm_dir.0.p2fwd
270061-A9
26AB
26AC
26AF
2682
2683
2685
2686
2689
268C
FA
717FI0
806417
FB
200B
FA
91BOI0
806417
FB
26BO
26BO BB004A
26CO 0225
~
~
26C2
26C6
26CB
26CC
26CE
B9202962
OE06
AI002962
0142
26CE
2601
2604
2607
260A
2600
26EO
26E3
A26334
A26336
A26346
A26370
A07072
646034
A40036
4B30344E
26E7 717FOF
26EA F3
26E8 FO
2800
2800
2800
2B03
2806
2B09
2BOC
90166D
366009
71BF6D
9:i100F
EFF5FB
684
6B:5
6B6
6B7
6BB
689
690
691
692
693
694
695
696
697
69B
699
700
701
702
703
704
705
706
707
70B
709
710
p2b kwd:
p2fwd:
~ndb
port2 •• 0111111IB
Idb
EI
br
DI
orb
Idb
EI
pwm_controll~pwr
clear P2.7
pwrset
port2 •• 10000000B
set P2. 7
i
pwm_contTDl.rp~T
PWTSltt:
cmp
Jgt
;;;
timlt_el"1"+2, zero
do pas_table when .err is negative
nxt_pos •• <32+pos_tablel
gott_vals
nxtJlos •• po5_table
time+2
cmp
Jlt
Id
clr
g.t_vAl":
Id
Id
Id
Id
Id
-add
addc
sub
endJl:
;
endJl
endJl
br
711
712
713
714
715
716
717
71B
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prevent lockup
270061-80
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ASSEMBLY COMPLETED.
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END
NO ERROR(S) FOUND.
270061-81
intJ
AP-275
APPLICATION
NOTE
.
October 1988
An FFT Algorithm For MCS®-96
Products Including Supporting
Routines and Examples
IRA HORDEN
ECO APPLICATIONS ENGINEER
@ Intel Corporation, 1988
Order Number: 270189-002
6-103
AP-275
channel to a printer or terminal which displays the results. In the applications listed in the previous section,
the data from this FFT program would be used directly
by another program instead of being plotted. However,
the plotted results are used here to provide an example
of what the FFT does. There are four program modules
discussed in this application note:
1.0 INTRODUCTION
Intel's 8096 is a l6-bit microcontroller with processing
power sufficient to perform many tasks which were previously done by microprocessors or special building
block computers. A new field of applications is opened
by having this much power available on a single chip
controller.
The 8096 can be used to increase the performance of
existing designs based on 8051s or similar 8-bit controllers. In addition, it can be used for Digital Signal
Processing (DSP) applications, as well as matrix manipulations and other processing oriented tasks. One of
the tasks that can be performed is the calculation of a
Fast Fourier Transform (FFT). The algorithm used is
similar to that in many DSP and matrix manipulation
applications, so while it is directly applicable to a specific set of applicati.ons, it is indirectly applicable to
many more.
FFTs are most often used in determining what frequencies are present in an analog signal. By providing a tool
to identify specific waveforms by their frequency components, FFTs can be used to compare signals to one
another or to set patterns. This type of procedure is
used in speech detection and engine knock sensors.
FFTs also have uses in vision systems where they identify objects by comparing their outlines, and in radar
units to detect the dopier shift created by moving objects.
This application note discusses how FFTs can be calculated using Intel's MCS®-96 microcontrollers. A review of fourier analysis is presented, along with the specific code required for a 64 point real FFT. Throughout
this application note, it is assumed that the reader has a
working knowledge of the 8096. For those without this
backgromid the following two publications will be helpful:
1986 Microcontroller Handbook
Using the 8096, AP-248
These books are listed in the bibliography, along with
other good sources of information on the MCS-96
product family and on Fast Fourier Transforms.
2.0 PROGRAM OVERVIEW
This application note contains program modules 'which
are combined to create a program which performs an
FFT on an analog signal sampled by tlie on-board
ADC (Analog to Digital Converter) of the 8097. The
results of the FFT are then provided over the serial
FFTRUN - Runs a 64 point FFT on its data buffer. It
produces 32 14-bit complex output values
and 32 14-bit output magnitudes. A fast
square root routine and log conversion routine are included.
A2DCON - Fills one of two buffers with analog values
at a set sample rate. The sample time can
be as fast as 50 microseconds using
8x9xBH components.
PLOTSP - Plots the contents of a buffer to a serially
connected printer. Routines are provided
for console out and hexadecimal to decimal
conversion and printing.
FTMAIN - The main module which controls the other
modules.
Each of the modules will be described separately. In
order to better understand how the programs work together, a brief tutorial on FFTs will be presented first,
followed by descriptions of the programs in the order
listed above.
The final program uses 64 real data points, taken from
either a table or analog input 1. Each of the data points
is a 16-bit signed number. The processing takes 12.5
milliseconds when internal RAM is used as the data
space. If external RAM is used, 14 milliseconds are
required. Larger FFTs can be performed by slightly
modifying the programs. A 256-point FFT would take
approximately 65 milliseconds, and a 1024-point version would require about 300 milliseconds.
In the program presented, the analog sampling time is
set for 1 sample every 100 microseconds, providing the
64 samples in 6.4 milliseconds. The sampling time can
be reduced to around 60 microseconds per point by
changing a variable, and less than 50 microseconds by
using the 8x9xBH series of parts, since they have a 22
microsecond A to D conversion'time.
The programs are set up to be run in a sequence instead
of concurrently. This provides the fastest operation
if the sampling speed were reduced to the minimum
possible. For the fastest operation above about 80 microseconds a sample, the programs could be run concurrently, but this would require some minor modifications of the program. Figure I shows the timing of the
program as presented.
6-104
inter
AP-275
SAMPLE
.6.4ms
PROCESS
12-14ms
OUTPUT
SAMPLE
6.4ms
(3 ms MINIMUM)
270189-1
Figure 1. Timing of the FFT Program
These programs have run in the Intel Microcontroller
Operation Application's Lab and produced the results
presented in this application note. Since the programs
have not undergone any further testing, we cannot
guarantee them to be bug proof. We, therefore, recommend that they be thoroughly tested before being used
for other than demonstration purposes.
.
The main idea in Fourier analysis is that a function can
be expressed as a summation of sinusoidal functions of
different frequencies, phase angles, and magnitudes.
This idea is represented by the Fourier Integral:
H(f) =
f:
co
h(t) e -j2'1Tft dt
(1)
Where: H(t) is a function of frequency
h(t) is a function oftime
3.0 FOURIER TRANSFORMS
A Fourier Transform is a useful analytical tool that is
frequently ignored due to its mathematically oriented
derivations. This is unfortunate, since Fourier transforms can be used without fully understanding the
mathematics behind them. Of course, if one understands the theory behind these transforms, they become
much more powerful.
The majority of this application note deals with how a
Fast Fourier Transform (FFT) can be used for spectrum analysis. This procedure takes an input signal and
separates it into its frequency components. One can almost treat the FFT as a black box, which has as its
output, the frequency components and magnitudes of
the input signal, much like a spectrum analyzer.
From a mathematical standpoint, Fourier Transforms
change information in the time domain into the frequency domain. The theory behind the Fourier transform stems from Fourier analysis, also called frequency
analysis.
There are many books on the topic of Fourier analysis,
several of which are listed in the bibliography. In this
application note, only the pertinent formulas and uses
will be presented, not their derivations.
Since
e-j8 = COS 8 - jsIN8
H(f) =
f:
co
(2)
h(t) (cos (2'1Tft) - j sin (2'1Tft» dt (3)
Figure 2 shows a rectangular pulse and its Fourier
transform. Note that the results in the frequency domain are continuous rather than discrete. The horizontal axis in Figure 2a is frequency, while that of Figure
2b is time.
In a simplified case, the varying phase angles can be
removed, and the integral changed to a summation,
known as a Fourier Series. All periodic functions can
be described in this way. This series, as shown below,
can help provide a more graphical understanding of
Fourier analysis.
co
(t) = ao
y
2
+ ~
~
[an cos (2'1T nfot)
bn sin (2'1Tnfot)1
+
n= 1
for n = 1 to
Where fo
6-105
=
00
1
lo' the fundamental frequency.
(4)
AP-275
H(f) =
sin (27TTof)
27TTof
-TO
270189-3
270189-2
b.
a.
Figure 2. Rectangular Pulse and Its Fourier Transform
This formula can also be represented in complex form
as:
I.
quency term being summed. With rise and fall times of
10% of the period, the waveform generated by the first
3 terms is within 20% of ideal. At 7 terms it is within
10%, and at 20 terms it is within 5%. With a 5%
risetime, it is within 20% of ideal after 5 terms, 10%
after 13 terms and 5% after 32 terms. Figure 4 shows
the resultant waveforms after the summation of 7, 15
and 30 terms.
co
n=
an e j 27Tnfot
(5)
-00
The Fourier series for a square wave is
co
' " sin ((2k + 1) 27Tfot)
~
(2k+ 1)
Fourier analysis can be used on equation 4 to find the
coefficients an and bn- To make this process easier to
use' with a computer, a discrete form, rather than a
continuous one, must be used. The discrete Fourier
-transform, shown in Equation 7, is a good approximation to the continuous version. The closeness of the approximation depends on several conditions which will
be discussed later. The input to this transform is a set of
N equally spaced samples of a waveform taken over a
period of NT. The period NT is frequently referred to
as the "Sampling Window".
(6)
K=O
If these sinusoids are summed,' a square wave will be
formed. Figure 3 shows the graphical summation of the
first 3 terms of the series. Since the higher frequencies
contribute to the squareness of the waveform at the
corners, it is reasonable to compare only th,e flatness of
the top of the waveform. The sharpness or risetime of
the waveform can be determined by the highest fre-
1.0
/r'\ V/
0.8
1L
0.6
0.0
-0.2
-0.4
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I
0.4
0.2
V
"L
/
~
~ ~ ')
"V
/
/
t-\
Ir'i
I
o
"/2
Figure 3. Graphical Summation of Sinewaves
6-106
.
270189-4
AP-275
1.0
1\
0.8
;1'\
n.
r
'- v v IV
1'\
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0.6
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0.4
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r
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V
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IV
v
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V
V
o
7 TERMS SIN(X X 2..nfOI)/X
270169-5
1.0
~
0.8
IV
vv
v
vv
vv
.1
V
0.6
0.4
0.2
0.0
-0.2
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vv
-0.8
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AA A'"
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v~
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15 TERMS SIN(X X 2..nfOI)/X
270169-6
1.0
0.8
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0.6
-,
0.4
0.2
o
-0.2
-0.4
-0.6
-0.8
-1.0
la.
-.
.a
o
30 TERMS SIN(X X 2..nfOI)/X
Figure.4. Square Wave from Sinusoids
6-107
.
270169-7
inter
H (:T)
AP-275
=
I
the value of the input at the discrete times (t», the
Fourier Transform can be used to find the magnitUde
and phase shift of the signal at the frequencies (t).
h(kT)e- j2 'lTnk/N
k=O
n = 0,1, ... ,N-1
Wh~rc:
(7)
A spectrum analyzer can provide similar information
on an analog input signal by using analog filters to separate the frequency components. Regardless of its
source, the information on component frequencies of a
signal can be used to detect specific frequencies present
in a signal or to compare one signal to another. Many
lab experiments and product development tests can
make use of this type of information. Using these methods, the purity of signals can be measured, specific harmonics can be detected in mechanical equipment, and
noise bursts can be classified. All of this information
can be obtained while still treating the FFT process as a
black box.
H(t) is a function of frequency
h(t) is a function of time
T is the time span betweett samples
N is the number of samples in the window
n =0,1,2 ... N-I
This transform is used for many applications, including
Fourier Harmonic Analysis. This procedure uses the
transform to calculate the coefficients used in Equation
5. In order to do this, the factor T/NT must be added
to the transform as follows:
N-l
H
Consider the discrete transfo~ of a square wave as
shown in Figure 5. Note that the component magnitudes, as shown in the series of Equation 6, are shown
in a mirrored form in the transform. This will happen
whenever only real data is used as the FFT input, if
both real and imaginary data were used the output
would not be guaranteed to be symmetrical. For this
reason, there is duplicate information in the transform
for many applications. Later in this section a method to
make the most of this characteristic is discussed.
(~) =.2..- "" h(kT) e -j2'lTnk/N
NT
(NT)
£..i
k",O
n=O, 1,2,3, ... , N-1
(8)
The factor provides compensation for the number of
samples taken. Note that'the functions H(t) and h(t) are
complex variables, so the simplicity of the equation can
be misleading. Once the values of h(t) are known, (ie.
0.7
•
0.6
I
I
I
0.5
I
•:
0.4
I
0.3
~
THEORETICAL FOURIER SERIES COEFFICIENTS
I
I
I
REAL PART OF QISCRETE FOURIER TRANSFORM
I
I
I
50.2
11.
...
I
I
N=32
T=0.25
~
,
•
0.1
I
0.0
T
J
-0.1
_L
.
•
I
T
t
•
I
I
•
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•
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I
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I
I
•
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I
.
-0.2
0
2
4
6
8
10
12
14
16
18
20
22
24
26
28
0
.25
.50
.75
1.00
1.25
1.50
1.75
3031
n
I I
"v
-1.75 -1.50 -1.25 -1.00 -.75
-.50
-.25 -.125
FREQUENCY (n/NT)
270189-8
Figure 5. Discrete Transform of a Square Wave
6-108
intJ
AP-275
If one looks at Equation 8, it can be seen that the calculation of a discrete Fourier transform requires N
squared complex multiplications. If N is large, the calculation time can easily become unrealistic for real-time
applications. For example, if a complex multiplication
takes 40 microseconds, at N = 16, 10 milliseconds
would be used for calculation, while at N = 128, over
half a second would be needed. A Fast Fourier Transform is an algorithm which uses less multiplications,
and is therefore faster. To calculate the actual time savings, it is first necessary to understand how a FFT
works.
This reduces the calculations as several of the W terms
go to 1 and the highest power of W is N. All of W
values are complex, so most of the operations will have
to be complex operations. We will continue to use only
the W, X(n) and XO(k) symbols to represent these complex quantities.
The FFT algorithm we will use requires that N be an
integral power of 2. Other FFT algorithms do not have
this restriction, but they are more complex to understand and develop. Additionally, for the relatively small
values of N we are using this restriction should not
provide much of a problem. We will define EXPONENT ,as log base 2 of N. Therefore,
4.0 THE FFT ALGORITHM
N = 2EXPONENT
The FFT algorithm makes use of the periodic nature of
waveforms and some matrix algebra tricks to reduce
the number of calculations needed for a transform. A
more complete discussion of this is in Appendix A,
however, the areas that need to be understood to follow
the algorithm are presented here. This information
need not be read if the reader's intent is to use the
program and not to understand the mathematical process of the algorithm
.
To simplify notation the following substitutions are
made in Equation 8.
W=
k
=
The magic of the FFT, (as detailed in Appendix A),
involves factoring the matrix into EXPONENT matrices, each of which has all zeros except for a 1 and a
wnk term in each row. When these matrices are multiplied together the result is the same as that of the multiplication indicated in Equation 9, except that the rows
are interchanged and there are fewer non-trivial multiplications. To reorder the rows, and thus make the information useful, it is necessary to perform a procedure
called "Bit Reversal".
This process requires that N first be converted to a
binary number. The least significant bit (Isb) is swapped
with the most significant bit (msb). Then the next lsb is
swapped with the next msb, and so on until all bits have
been swapped once. For N = 8, 3 bits are used, and the
values for N and their bit reversals are shown below:
e-j21TIN
kT
n
n=NT
Number
Binary
Bit
Reversal
0
1
2
3
000
001
010
011
100
101
110
111
000
100
010
110
001
101
011
111
The resultant equation being
N-1
x(n) =
L
n(k)Wnk
(9)
k=O
Expressed as a matrix operation
[ ~1~: ]=[~~~! ~! . . ~~ ]
X(N-1)
WO W(N'-1) W2(N-1) ... W(N'-1)2
4
[
Xo(N~1)
A brief review of matrix properties can be found in
Appendix A. Because of the periodic nature of W the
following is true:
Wnk MOD N = Wnk
=
5
6
7
Xo(O)]
Xo(1)
Xo(2)
(10)
COS (27T nk/N) - j SIN (27Tnk/N)
DecimalBR
0
4
2
6
1
5
3
7
Recaii that the FFT of real data provides a mirrored
image output, but the FFT algorithm can accept inputs
with both real and imaginary components. Since the
inputs for harmonic analysis provided by a single A to
D are real, the FFT algorithm is doing a lot of calculations with one input term equal to zero. This is obviously not very efficient. More information for a given size
transform can be obtained by using a few more tricks.
W O = 1 therefore, if nk MOD N = 0 , Wnk = 1
6-109
AP-275
It is possible to perform the FFr of two real functions
at the same time by using the imaginary input values to
the FFr for the second real functipn. There is then a
post processing performed on the FFr results which
separate the FFrs of the two functions. Using a similar
procedure one can perform a transform on 2N real
samples using an N complex sample transform.
The procedure involves alternating the real sample values between the real and imaginary inputs to the FFr.
If, as in our example, the input to the FFr is a 2 by 32
array containing the complex values for 32 inputs, the
64 real samples would be loaded into it as follows:
N
00 01 02 03 04 05 06 07 ..... 30 31
REAL
0002 04 06 08 10 12 14 ..... 60 62
Where N is the number of complex samples (ie. 32 in
this case) T is the time between samples
This procedure is referred to as a pre-weave. In order to
derive the desired results, the FFr is run, and then a
post-weave operation is performed. The formula for the
,post-weave is shown below:
V ')
[A(n) A(N-n)l
".n [I(N) I(N - n)l "
""n
= - + - - + cos- - + - - -
2
N
. ".n [A(n) A(N - n)l
sInN" 2
- -2-
2
cos'N
2 -
1.0
A(N - n)]
-2-'
L\
I \ I \
I \ I \
II \I \
.6
I
II
5.0 USING THE FFT
+ I(N - n)l _
2
n =0,1, ... , N - 1
11\
0.8
2
A value of zero on the frequency scale corresponds to
the DC component of the waveform. Most signal analysis is done using Decibels (dB), the conversion is dB =
10 LOO-(Magnitude squared). Decibels are not used as
an absolute measure, instead signals are compared by
the difference in decibels. If the ratio between two signals is 1:2 "then there will be a 3 dB difference in their
power.
n = 0,1, ... , N - 1
X"(n) = [I(n) _ I(N - n)l _ sin "."n [I(n)
I
2
2
N
2
1Tn [A(n)
Note that the output is now one-sided instead of mirrored around the center frequency as it is in Figure 5:
The magnitUde of the signal at each frequency is calculated by taking the square root of the sum of the
squares. The magnitude can now be plotted against frequency, where the frequency steps are defined as:
n
NT n = 0, 1, 2, 3, ... , N-1
IMAGINARY 01 0305070911 13 15 ..... 61 63
2
Where R(n) is the real FFr output value
I(n) is the imaginary FFr output value
Xr(n) is the real post-weave output
Xi(n) is the imaginary post-weave output
(11)
There are several things to be aware of when using
FFrs, but with the proper cautions, the FFr output
can be used just like that of a spectrum analyzer. The
OdB
11\
I \
I \
I \
\
-'OdB
\
-20dB
0.4
.2
0
I
1\ I \
1\
I
I \ I \
\
Iv......... 1 \ V \ V ~
n-I
n
""\ V
V
L~
I \
""\ V
"'
/
/ 1\ / 1\ \
// t'\. I \ I \ / ,\
V \
I ~
/ !"\.
I
-30dS
n+1
n-l
270189-9
"n
n+1
270189-73
(a.) Relative Power of Windows {Side Lobes of
Side Bins Removed for Clarity).
(b.) 10 Log Relative Power of Windows (Side
Lobes of Side Bins Removed for Clarity).
Figure 6. Bin Windows
6-110
\
AP-275
first precaution is that the FFT is a discrete approximation to a continuous Fourier Transform, so the output
will seldom fit the theoretical values exactly, but it will
be very close.
Since the programs in this application note generate a
one-sided transform with N = 32, the frequency granularity is fairly course. Each of the frequency components output from the FFT is actually the sum of all
energy within a narrow band centered on that frequency. This band of sensitivity is referred to as a "bin".
The reported magnitude is the actual magnitude multiplied by the value of the bin window at the actual frequency. Figure 6 shows several bin windows. Note that
these windows overlap, so that a frequency midway between the two center frequencies will be reported as
energy split between both windows. Be careful not to
SAfolPLE
confuse the sampling window NT with bin windows or
with the windowing function.
Another area of caution is the relationship of the sampling window to the frequency of the waveform. For
the best accuracy, the window should cover an exact
multiple of the period of the waveform being analyzed.
If it covers less than one period, the results will be
invalid. Other variations from ideal will not produce
invalid results, just additional noise in the output.
If the sampling window does not cover an exact multiple of all of the frequency components of a waveform,
the FFT results will be noisy. The reason for this is the
sharp edge that the FFT sees when the edges of the
window cut off the input waveform. Figure 7 shows a
waveform that is an exact multiple of the window and
WAVEFORM THAT FFT OUTPUT REFLECTS
270189-10
Figure 7. Waveform is a Multiple of the Window
SAfolPLE
WAVEFORM THAT FFT OUTPUT REFLECTS
Figure 8. Waveform is Not a Multiple of the Window
6-111
270189-11
intJ
AP-275
the periodic waveform that the FFT output reflects. In
Figure 8, the waveform is not a mUltiple of the window
and the waveform that the FFT output reflects has discontinuities. These discontinuities contribute to. the
noise in an FFT output. This noise is called "spectral
leakage", or simply "leakage", since it is leakage between one frequency spectrum and another which is
caused by digitization of an analog process.
To reduce this leakage, a process called windowhig is
used. In this procedure the input data is multiplied by
specific values before being used in the FFT. The term
'~windowing" is used because these values act as a window through which the input data passes. If the input
window goes smoothly to zero at both endpoints of
the sampling window, there can be no discontinuities.
Figure 9 shows a Hanning window and its effect on the
input to an FFT. The Hanning window was named after its creator, Julius Von Hann, and is one of the most
commonly used windows. More information on windowing and the types of windows can be found in the
paper by Harris listed in the bibliography. As expected,
the results of the FFT are changed because of the input
windowing, but it is in a very predictable way.
Using the Hanning window results in bin windows
which are wider and lower in magnitude than normal,
as can be seen by comparing Figure 6 with Figure 10.
For an input frequency which is equal to the center
frequency ofa bin window, the attenuation will be 6 dB
on the. center frequency. Since the bin windows are
,
,......
.11
....... -..L\
II
:-..
/
....
V
III
,/
/1\
"-
,/
r'\.
"
j
r/
I
\./
""
I'(
V
V
V
'~
I \.
V
\/
V
'\
V
270189-13
(a). Original Signal and Hanning Window
270189-74
(b). Signal After Hanning Window
Figure 9. Effect of Hanning Window on FFT Input
1.0
Ode
0.0
-? f'..
/'
-fOdS
il
0.6
-20dB
I
0.'
........
L
0.2
/
0
./
L
/ r'\.
/ '\.
./
n-l
-30 dB
r---.... L I--....
,...; F-....
n
r'\.
"I'---
"!'o..
-40d9
I
I
II~ II
1\
I
I
I
I
n-l
n+l
\
II \
I
I
I
"-
Jr\
I
J
./ "-
\
1\
\
\
\
\
\
\
\
n
\
\
\
\
(" i\
n+l
270189-75
270189-12
(b.) 10 Log Power of Hanning Window (Side
Lobes of Side Bin Window Removed)
(a.) Relative Power of Hanning Window
Figure 10. Bin Windows after Using Hanning Input Window
6-112
\
AP-275
Matrix L
wider than normal, the input frequency will also have
energy which falls into the bins on either side of center.
These side bins will show a reading of 6 dB below the
center window. The disadvantage of this spreading is
far less than the advantage of removing leakage from
the FFT output.
Matrix L
X(k)
+
~·Wpl
+ --+ X(k)
·Wp2
X(k+N2)
+
--+ X(k+N2)
270189-15
A set of FFT output plots are included in the Appendix. These plots show the effect of windowing on various signals. There are examples of all of the cases described above. A brief discussion of the plots is also
presented.
Applications which can make use of this frequency
magnitude information include a wide range of signal
processing and detection tasks. Many of these tasks use
digital filtering and signature analysis to match signals
to a standard. This technique has been applied to antiknock sensors for automobile engines, object identification for vision systems, cardiac arrhythmia detectors,
noise separation and many other applications. The ability to do this on a single-chip computer opens a door to
new products which would have not been possible or
cost effective previously.
The next four sections of this application note cover the
operation of the programs on a line by line basis. Section 6 shows an implementation of the FFT algorithm
in BASIC. This code is used as a template to write the
ASM96 code in Section 7. Sections 8, 9, and 10 cover
the code sections which support the FFT module. After
all of the code sections are discussed, an overview of
how to use the program is presented in Section 1l.
6.0 BASIC PROGRAM FOR FFTS
The algorithm for this FFT is shown in the flowchart in
Figure 11 and the BASIC program in Listing l. There
are four sections to this program: initialization, preweaving, transform calculation, and post-weaving. The
flowchart is generalized, however, the BASIC program
has been optimized for assembly language conversion
with 64 real samples.
On the flowchart, the initialization and pre-weaving
sections are incorporated as "Read in Data". The data
to be read includes the raw data as well as the size of
the array and the scaling factor. The details for preweaving have been discussed earlier, and initialization
varies from computer to computer. LOOP COUNT
keeps track of which of the factored matrices are being
multiplied. SHIFT is the shift count which is used to
determine the power of W (as defined earlier) which
will be used in the loop.
Also Shown as:
X(k)]G
Wpl
Wp2
X(k+N2)
.
270189-16
OR
X1 (k)
= Xo (k + N2)*Wp1 + Xo(k)
X1(k+N2)
= Xo(k)*Wp2 + Xo{k+N2)
In general, the W factors are not the same. However,
for the case of this FFT algorithm, Wpl will always
equal (- Wp2). This is because of the way in which "p"
is calculated, and the fact that W(x) is a sinusoidal
function.
The inner loop in the flowchart is performed N2 times.
For LOOP = 1, N2=N!2 and if INCNT=N2 then
k = N2 and k + N2 = N, so the first loop is done and
parameters LOOP, N2, and SHIFT are updated. For
the first loop, all N!2 sets of calculations are performed
contiguously. As LOOP increases, the number of contiguous calculations are cut in half, until
LOOP = EXPONENT.
When LOOP = EXPONENT, N2= 1, the butterfly is
then performed on adjacent variables. Figure 12 shows
the butterfly arrangement for a calculation where
N=8, so that EXPONENT = 3.
The BASIC program follows this flowchart, but operations have been grouped to make it easier to convert it
to assembly language. Also not shown in the flowchart
are several divide by 2 operations. There are five in the
main section, one per loop. These provide the T /NT
factor in equation 8 for N = 32 (2 5 = 32). There is also
an extra divide by two in the post-weave section. It is
required to prevent overflows when performing the 16bit signed arithmetic in the ASM96 program. As a result of these operations, the input scale factor is ± 1 =
± 32767 and the output scaling is ± I = ± 16384.
Note, the maximum input values are ±O.99997.
For each loop N calculations are performed in sets of
two. Each calculation set is referred to as a butterfly
and has the following form:
6-113
AP-275
INNER
LOOP
=
TMi' wp• X(k + N2)
X(k + N2) = X(k) - TMP
X(k) = X(k) + TMP
NO
YES
270189-14
Figure 11. Flowchart of Basic Program
6-114
inter
100'
105 '
110
115
AP-275
THIS IS FFT13, FEBHUARY 4, 1986
, COPYRIGHT INTBL CORPORATION, 1986
, 8Y IRA HORDBN, MCO APPLICATIONS
120 '
126'
THIS PROGRAM PERFORMS A FAST FOURIER TRANSFORM ON 64 RBAL DATA POINTS
130 ' USING A 2N-POINTS WITH AN N-POINT TRANSFORM ALGORITHM. THB FIRST
135 ' SECTION OF THE PROGRAM PBRFORMS A STANDARD TRANSFORM ON DATA THAT HAS
140 ' BBBN INTBRLBA¥ED BETWEEN THI RIAL AND IMAGINARY INPUT VALUIS. THE
146 ' RESULTS OF THAT TRANSFORM ARE THEN POST-PROCESSED IN THB SBCOND SBCTION
150 ' OF THE PROGRAM TO PROVIDI THE 32 OUTPUT BUCKETS. THE OUTPUT VALUES ARI
155 ' MULTIPLIBD BY "M" TO MAKE IT BASY TO COMPARE WITH THE ASM-96 PROGRAM
160 '
165 INPUT "NAME OF LIST FILB"; LSTt
170 PRINT
175 OPEN LSTt FOR OUTPUT AS .1
180 '
, SBT UP VARIABLBS FOR BASIC
200
210 DIM XR(32),XI(32),WR(32),WI(32),8R(32)
, M=MULT. FACTOR FOR SCALING
220 M=16383'
' N=NUMBBR OF DATA POINTS
230 N=32 : N1=31 : N2=N/2
' 2**I=N
240 LOOP=l : 1=0 : BXPONENT=5 : SHIFT=IXPONRNT-l
: TPN=2*PI/N : PIN=PI/N
250 PI=3.141592654'
,
260
, RBAD IN CONSTANTS
270
280 rOR P=O TO 31
PN=P*TPN
RIAD BR(P)
WI(P)=-SIN(PN)
290 WR(P)=COS(PN)
300 NBIT P
310 '
, RBAD IN DATA
320 FOR 1=0 TO 31
RIAD XI(K)
330 RIAD XR(I)
350 NItXT I:
360 '
, INITIALIZATION OF LOOP
400
410 1=0
420 IF LOOP>IXPONBNT THBN 700
430 INCNT=O
, ACTUAL CALCULATIONS 81GIN HIRB
440
445 '
450 INCNT=INCNT+1
460 P=BR(INT(I/(2 A SRIFT»)
, WRP AND WIP ARI CONSTANTS BASBD ON
470 WRP=WR(P) : WIP=WI(P) : IN2=I+N2
, SINBS AND COSINIS or BIT RIVIRSID
480'TMPR= (WRP*XR(IN2) - WIP*XI(IN2»/2
, VALUBS OF I: SHIFTBD, RIGHT S TIMBS
490 TMPI= (WRP*XI(IN2) + WIP*XR(IN2»/2
500 TMPRl=XR(I)/2 : TMPIl=XI(K)/2
510 XR(I:+N2) = TMPR1 - TMPR
' TMPR, TMPI ARE THB REAL AND IMAGINARY
520 XI(I:+N2) = TMPI1 - TMPI
' RESULTS or A COMPLBX MULTIPLICATION
530 XR(I:)
TMPR1 + TMPR
540 XI(I) = TMPII + TMPI
560 '
550 I=K+1
570 IF INCNT(N2 TRBN GOTO 450
580 1=I+N2
' SINCB THB ARRAY IS PROCBSSBD 2. POINTS AT A TIMB,
590 IF I(NI TRIN GOTO 430
'ONLY N/2 LOOPS NEED TO BE MADE. ON EACH PASS,
'THB VALUR OF N2 CHANGRS AND SMALLIR CONSICUTIVI
800 LOOP=LOOP+1 : N2=N2/2
605 SHIrT=SHIFT-l
' SBCTIONS ARI PROCBSSBD.
810 OOTO 400
620 '
690 '
891 '
692 '
693 '
270189-1-7
Listing 1-BASIC FFT Program
6-115
inter
694
695
696
697
700
AP-275
•
•
•
•
• POST-PROCBSSING AND RBORDBRING BBGIN HBRB
710 •
720 FOR K = 0 TO 31
730 KPIN=K*PIN
740 XRBRK=XR(BR(K» : XIBRK=XI(BR(K»
• CONDBNSBD FOR BASB OF ASM PROGRAMMING
750 XRBRNK=XR(BR(N-K» : XIBRNK=KI(BR(N-K»
760' TI = (KIBRK+KIBRNK)/2
770 TR = (XRBRK-XRBRNK)/2
7·80 KRT= (XRBRK+XRBRNK)/4
790 IIT= (KIBRK-KIBRNK)/4
800 OUTR= XRT + TI*COS(KPIN)/2 - TR*SIN(KPIN)/2
810 OUTI= KIT - TI*SIN(KPIN)/2 - TR*COS(KPIN)/2
820 •
• THB ASM-96 PROGRAM USBS A TABLE LOOK-UP
830 MAGSQ = OUTR*OUT~+OUTI*OUTI
• ROUTINB TO CALCULATB SQUARB ROOTS
840 MAG = SQR(MAGSQ)
GOTO 900
845 IF MAGSQ*M < ·.5 THBN DBCIBBL=O
847 DBFACT=M/2/32767*M • MA2 / 64K
850 DBCIBBL=10*LOG(MAGSQ*DBFACT)
860 DBCIBBL=DBCIBBL * .434294481'
900
GO TO 930
910 PRINT '1. USING " •••••• "; X,
,to; HEX$(M*OUTR). HBX$(M*OUTI). HBX$(M*MAG)
920 PRINT '1. USING .. ,
930 • GOTO 950
fl.
K"
942 PRINT '1. USING
943 PRINT '1. USING " ••••• ; ••• to; OUTR.OUTI.MAG;
945 PRINT '1. USING ......... to; DBCIBEL;
"; M*OUTR. M*OUTI. M*MAG
947 PRINT '1. USING ".,.,..
950 NEXT K
960 •
970 IF LST$O"SCRN:" THBN PRINT fl. CHR$(l2)
999 BND
1000 BND
• DATA FOR BR(P) - BIT RBVBRSAL
1010
1020 DATA 0.16.8.24.4.20.12.28.2.18.10.26.6.22.14.30
1030 DATA 1.17.9.25.5.21.13.29.3.19.11.27.7.23.15.31
1040
• DATA FOR KR.XI
1050 DATA 2.2.2.2.2.2.2.2.2.2.2.2.2.2.2.2
1060 DATA 2.2.2.2.2.2.2.2.2.2.2.2.2.2.2.2
1070 DATA -2.-2.-2.-2.~2.-2.-2.-2.-2.-2.-2.-2.-2.-2.-2.~2
1080 DATA -2.-2.-2.-2.-2.-2.-2.-2.-2.-2.-2.-2.-2.-2.-2.-2
t",
270189-18
listing 1-BAS!C FFT Program (Continued)
6-116.
inter.
AP-275
Lines 165-175 set up the file for printing the data, this
can be SCRN:, LPTl:, or any other file.
X(O)
X(O)~X(O)
><:
X(I)~~-+"7X(I)
X(O)
X(I) - - - - : X(I)
X(2)
X(2)
X(2)
X(3)
X(3)
X(3) -
:><:
X(2)
Lines 700-810 perform the post-weave. This is not in
the flowchart, but can be found in Equation 11. Once
again, table look-ups are separated and additional variables are used for clarity. The variables BR(x) are the
bit reversal values of x.
X(3)
X(4)
X(4)~X(4)::::><: X(4)
XeS)
XeS)
XeS)
XeS)
XeS)
X(7)
X(7)
X(7) -
XeS) - - - - - - ' XeS)
:><:
The variables on line 470, TMPRI and TMPIl would
normally not be used in a BASIC program as more
than one operation can be performed on each line.
However, indirect table lookups always use a separate
line of assembly code, so separate lines have been used
here.
XeS)
X(7)
Line 830 calculates the magnitude of the harmonic
components.
270189-19
Figure 12. Butterflies with N = 8
Lines 200-310 set up the constants and calculate the
WP terms which are stored in the matrices WR(P) and
WI(p), for the real and imaginary component respectively.
Lines 320-350 read in the data, alternately placing it
into the real and imaginary arrays. The data is scaled
by 2 to make the data table simpler.
Lines 900-950 print the results of the calculations, with
line 900 determining if the print-out should be in hex or
decimal.
Lines 1000-1080 are the data for the bit reversal values
and input datapoints. The input waveform is one cycle
of a square-wave.
7.0 ASM96 PROGRAM FOR FFTS
Lines 410-430 initialize the loop and test for completion.
Lines 450-620 perform the FFr algorithm. Note that
all calculations are complex, with the suffixes "R" and
"I" indicating real and imaginary components respectively.
The BASIC program just presented has been used as an
outline for the ASM96 program shown in Listing 2.
There are many advantages to using the
BASIC program as a model, the main ones being debugging and testing. Since the BASIC program is so
similar in program flow to the ASM96 program, it's
possible to stop the ASM96 program at almost any
point and verify that the results are correct.
6-117
IIlS-96 MACRO ASSIIIIBLBR
FFT_IWN
02/18/86
l
PAGE
SBRIES-III 1I)S-96 MACRO ASSEllBLBR, Vl.O
SOIJlICII FILl: : F2: ITTIIIJII. A96
OII.JECT rILl: : F2: FFT1WN. OBJ
COImIOLS SPBCIFIBD IN IIIVOCA'rIOII CQftAIID: I!OSB
ERR LOC
0BJBC'r
L~
1
SOURCB STA'l'BMIIII'I'
......eleDCth(50)
2
3
FFT_RlIlI IClDULE
S'rACISIZE(6)
4
5
6
Intel Corporation, .January' 24, 1986
by Ir. RordeD, 1Il0 Applicationa .
7
Co
~
W
II
:::J
~
I\)
M
ca
a>
!rn
.....
CD
,
8
9
iI:
.....
0)
(XI
."
:!I
."
o
~
3
~
~
W
"
~
~
~
~
~
~
~
~
~
~
"~
~
~
~
~
~
M
$
'rhi. _ I e perfo... a fut fourier t ....... fono (FFT) on 64 real data
point. uain, • 2lf-point al,oritblo. !be al,oritba involves uainr a .tandard
FFT procedure for 32 real and 32 illaginary nUllbera. The real and 18ag1oary
arrays are fUled alternately with re.l data point., and the output of the
FFT i. run throUlb a poat"1)rocea.or. !be result i. a one .ided array with 32
output buckets. '!'he poet proce•• iDg inclw:te. • table lookup al,orithll for
takin, the .quara root of an UDairned 32-bi t nU.ber."
»
~......
All of the calculationa in the a10 FFT prOI(r8ll ere done usinr 16-bit
d,ned inte,era. !be _ _ value of any frequency _ t is therefore
+/- 3211:. (Note that a .quara wave of" +/-3211: baa a funcIImmItal , , - e n t
greater than +/- 40K). Wherever poaaible tables are used to Increaoe the
speed of _th operationa. !be ceaplete tranafo.... 1ocludlo, obtainin, the
absolute _itude of each frequency cOllPODent, executes in 12
.Uliseconda with internal variables. 14 _ with external •
U'I
!be pro_ requires two 32-word "input ........,.. with the .eaple values
; alternated betweeu the two. Theile .tart at XRIAL and. XDWJ. The resultant
; _itude will be placed in a 32__ rd array at FFT_OUT. Theae are aU
externally def10ed variabl... !be external COIIIItant SCALI_FACTOR i. used to
divide the output when averDliol will he uaed. Since the prnrraa &Vereg..
ita output, it i. _ . a r y to clear the array baaed at FFT_OUT before
callinr FFT_CALC to .tart the prnrraa.
!be prorrea _
originally written in BASIC for teatin, purpoaea. The
_ n t . include theae BASIC .t.t.....t. to Bake it eaier to follow the
.l,oritba.
$
~
tBJBCT
270189-33
MCS-96 MACRO ASSBMDLBI!
ERR
toe OBJECT
0000
C
~
~
IC
ten
s:
II)
G)
0>
......
......
I
(0
"'1'1
"'1'1
..
..
-I
'U
0
IC
II)
3
'0
0
a
:::J
c:
(D
0024
0024
0028
002C
0030
0034
0038
0030
0040
0044
0048
0030
0040
0040
0044
003C
003E
0040
0042
0044
004C
004B
0050
0052
0064
0056
0068
004B
0000
.s
Fi'T_RIIN
LINK
38
39
40
41
42
43
02/18/86
,BXTRN
oSBa
44
45
46
47
48
49
50
51
52
53
64
55
portl. zero, error
at 248
'lMPR:
'lMPI:
'lMPRl:
'lMPn:
XR'lMP:
XI'IMP:
clsl
clsl
clsl
clsl
clsl
clsl
clsl
clsl
clsl
clsl
XRRI[:
XRRN8:
KIRK:
XIRNB:
diff
aqrt
log
mctloc
56
57
58
59
60
61
62
63
64
equ
equ
equ
equ
aqu
equ
KBP
HIP
PIiR
equ
equ
equ
IIf_CNT
NDIV2
KPTH:
1IN2:
1
0040
TeIIpOrary
Taporary
Temporary
Taporary
TellPorary
Ta.porary
1
1
1
1
1
1
1
long
long
long
long
Table difference for ·square root
Square root
:word
: word
:word
xrrnk+2 : word
xirk
:word
Multiplication factor, Real
Multiplication factor, Imaginary
K for cou:ater *2 to index words
xrrk
xrrk+2.
xrmk
69
70
88FT CRT:
LOOP=CNT:
71
ptr
1m2
65
66
N_SllB_X:
67
RE:
RNB:
68
equ
72
DSEG
73
74
75
76
BlITDN
BlITDN
I'i'T_MODE
77
BlITDN
I'i'T_OUT
81
82
83
84
1
1
10 Log _itude 2
Next location in table
A
n divided by 2
(0
< n < N)
l>
'P
N
*2
.....
en
KPTH + NDIV2
N-II *2 to index worda
Bit reversed pointer -of KPTR
Bit reversed pointer of' N_SDB_K
1
1
1
1
1
: word
Pointer for square root table
1'i'T_MODE: _ e for I'i'T illPllt and graphing
XRBAL, XDWl: Base addresses for 32 16-bit Biped
entries for resl end imaginary numbers respectively.
FFT_OllT: Starting eddresa for 32 word array
~,XDWl
of
OUTR:
claw
OUTI:
clsw
PUBLIC OUTR,OUTI
register. Real
register, Imaginary
registerl, Real
registerl, r.aginary
data register t Re@l
data register. Iaaginery
1
1
xrrk
xrmk
xrmk
xirk
claw
daw
daw
clsw
claw
claw
dab
so
l
2
RSBG
78
79
0000
PAGE
SOURCB STATBMBNT
32
32
~tude
information.
Real cosponent of fft
IBaginary cosponent of NOvefono
$BJl!CT
270189-34
MCS-96 MACIiO ASS_LlR
ERR LOC
FFT_RUN
2280
r
0"
C!:
:::I
a::I
t
Ul
i!:
CD
al
Cf>
.......
I\)
0
"11
"11
,...
2280
2280 1100
2282 BIOIOO
2285
2286
2289
228C
..
~I
2290
2290 014.2
3
'0
0
3-
S"
c
~
'2298
2298 65020042
22A2
22A5
22A8
22AB
B
A04C40
085640
7lFB40
A341003840
2280 A34144393C
2285 A34186393B
22BA 44444C4B
85
86
87
88
89
90
91
82
93
94
95
98
97
98
B
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
11'1:
118
119
120
121
122
123
124
125
126
127
PAG!
i
3
asBG at 22808
PllBr.IC fft_cale
Starting point for FPT algorithm
BXTRN
Shift factor used to prevent overflow wheD averaging
fft output.
scale_factor
,
FFT CALC:
elrb
Idb
clrvt
ldb
Idb
Id'
99
BlOl58
BI0456
A1200044
2295 990558
2298 DA0220A3
'U
0
B
Fe.
2290
2290 950400
22930140
02/18/86
SOURCB STATBIIBNT
LINE
08.1l!CT
START FOURIBR CALCULATIONS'
400 'INITIALIZATION OF LOOP
error
;****
porti, toOOOOOOlb
Indication Only
loop_cnt;,.l
shft_cnt,t4
ndiv2,'32
410 8=0
OUT_LOOP:
xorb
elr
portl,toOOOOlOOB
kptr
CIIpb
loop_cnt,'5
bgt
tlIIIiI!AW
;
,,,,
420 IF LOOP
; 32=2....6
> RXP
****
Indication Only
]>
THEN 700
l'
N
....
(II
MID LOOP:
elr
in_CDt
IN LOOP:
add
iD_cnt,12
430 INCNT=O
440
460
Id
shr
andb
Id
pwr'tkptr
pwr,.hft_cnt
pwr,#111111l0B
pwr,brev(pwr]
'CALCULATIONS BEGIN IIBRB
450 INCNT=INCNT+l
P=BR(INT(K/(2~SRIFT»)
;; Calculate 1m1 tiplicatioD factora
470 WRP=1iR(P) : WIP=III(P)
&If:
ld
ld
add
KN2=K+N2
Wt"P,wr[pwr]
"ip,wi[pwr]
1m2, kptr, Ddiv2
$eject
270189-35
_.
IICS--96 MACRO ASSBMBLBR
ERR LOC
fFT_RlIN
ollJKcr
22BI FB4f4fOOO03C24
2205 FB4F4fOOO03B28
22CC 682A26
E
220F FB4f4fOOOO3C2O
22D6 FB4f4fOOO03B28
2200 642BU
B
B
B
riii'
C!:
::I
IQ
t
III
iii:
CD
en
0)
'TI
....
.... ."::!I
I
I\)
..
.
2280 DC55
2282
2217
22IA
22Bf
A34DOOO02O
OA012C
A340000030
OA0130
22F2 48262034
22f6 C34fOOO034
1
Ii
Ii
22m 4B2A3038
22FF C34fOOO038
E
3
2304 44262C34
2308 C340000034
B
'0
0
2300 442A3038
2311 C~0000038
B
c:
23160023
0
IQ
AI
a:i'
CD
.s
LINE
128
129
130
.131
132
133
134
136
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
02/18/86
PAGE
I
4
t
SOORCI STATBIIIINT
;; Complex IlUItiplication follows
II1II:
[b2j .
DlUl
DlUl
sub
tJlpr, wrp. xreal
tapi,wip,xilll8g[lm2]
tapr+2, tapi+2
aul
aul
add
taprl, wrp, xiIII8g[i,;,i j
tapi,wip,xreal[kn2]
tlapi+2, taprl+2
BVT
Id
ahra
Id
ahra
....
8RRl
480 _
(WIIP*XR(KN2) - WIPtXI(KN2ll/2
490 TMPI= (WllPtXI(KN2) + WIPtXR(KN2ll/2
using the high byte only of a sirnad multiply
provides aD effective divide by two
; Branch on error in complex IlUltiplication8
. taprl, xreal [kptr]
taprl,'l
tlapil,xilll8g[kptr]
tapil,n
Iitl
""
500 TMPRl=XR(K) /2
TMPIl=XI(K)/2
»"a
510 XR(BN2) = 'lMPR1 - TMPR
gr2:
~:
sub
st
xrtmp, tllprl. tmpr+2
xrtap, xreal[lm2]
sub
st
xttmp. tmpil. tmpi~2'
xitlap,xiaag[kn2]
add
st
xrbip. taprl. tmpr+2
xrtlap, xreal [kptr]
add
st
xitllp, tmpil. tapi~2'
xitap,xilll8g[kptr]
BVT
IRR2
I
520 XI(BN2) = TMPIl - TMPI
IIII
gx:
I I
I
530 XR(K) = TMPl!l + TMPR
540 XI(K) = TMPIl + TMPI
I
i Branch on error in complex additions
.eJect
270189-36
N
-.,
c.n
MCS-96 IIACIlO ASSBMBLBR
BRR LOC
FFl'_RIlII
OBJBCT
2318 66020040
231C 884442
231F 06022778
232364444C
c
~
~
CQ
i
~
~
en ."
k·~
NI
~
"~
:::l
3c:
(I)
.8:
2326 893BOO4O
232A D602276B
2328 1168
2330 01.0144
2333 1556
2335 2759
2337
2331.
2338
233B
810100
ro
810200
ro
B
B
LINK
166
166
167
168
169
170
171
172
173
174
115
176
117
178
179
180
181
182
183
184
185
186
187
188
189
190
191
02/18/86
SOIlllCB STATBMBIIT
ik:
,
add
kptr,'2
bIt
ClIP
ID_cut, Ddiv2
IN_LOOP
add
kptr,Ddiv2
ClIP
bIt
kptr,tI62
MID_LOOP
...
f.t.
510 IF INCIIT(1I2 TBBN GOTO 450
I."
580 K=K+N2
'ft'
590 IF Kil
xrtlq>+2, tJq>il+2
xrtlIp, tmpr1
xr~2,tmpr1+2
xrtIq>+2, outr[kptr]
""
.i:
I
7
Multiply will provide effective divide by 2
II"
1Ir:
PAGB
; i OUTR
= Real Output Values
810 0tr11= (XIT - TUSIIII'II(K)/2 - 1'II>ICOS1'II(K)f2)
tmpr1, tmpr, coafD[kptr]
tmpU, tapi, s1DfD[kptr]
xitmp, tmpil
xi~2,tmpil+2
xi tmp, tmpr1
xi~2,tmprl+2
xi~2,outi(kptr]
;; OUTI = Imaginary Output values
.
~
"U
IIII
GBT_MAG:
SeJsct
830 MAG =SQR(OIJTllj()OTR + OIlTUOIITI)
j ;
1d
Id
mpr, xrt.p+2
tmpi, xi tmp+2
11111
tlipr. tJIPr
aul
edd
edde
tllpi. tllpi
tmpr,tmpi
tmpr+2, tmpi +2
bbe
FFT_MODB,2,CALC_SQRT
I- I
Get Magnitude of Vector
tmpr = tmpi**2 + tmpr**2
270189-39
N
......
en
MCS-96 MACRO ASSIlMBLRR
ERR LOC
23F7
23F7
23F9
23FC
23FF
OBJECT
FIT_RUN
0156
OF5624
990F56
DA04
2401 0140
2403 202C
r
[
5'
\C
I\)
I
»
en
i!:
j\)
U'I
."
."
.
.
-I
'0
0
\C
Q)
3
00
;:!.
5'
c
CD
.e,
2405
2405 44585656
2409 AC274E
240C 444E4E4E
2410 65083A4E
2414 A24F40
2417 A24E44
241A 684044
241D AC263C
2420 6C443C
2423 OC083C
2426 843C40
2429 080540
242C A7570A3C40
2431
2431
2434
2437
243C
080040
A40040
674DOOO040
C34DOOO040
2441 2045
02/18/86
LINE
~
E
E
E
E
276
277
27B
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
PAGE
l
8
SOURCE STATEMENT
;;;i
***
Output = 512*lO*LOG(x)
***
CALCULATE 10 log magni tude""2
x=I,2.3 ... 64K
CALC LOG:
-
elI"
jle
shft cnt
tmpr: shft CDt
ahft_CDt,ilS
LOG_IN_RANGE
elI"
br
log
LOG_STORE
normi
cmpb
LOG IN RANGE:
- - add
Idbze
add
add
Id
Id
Jump if SHIIT_CNT
shft_CDt.shft_cnt,shft_Cllt
Dxtloc,log
nxtloc
= next
diff I tmpr+2
diff+ 1
~
mulu
diff ,nxtloc
shrl
add
.br
diff,#B
log,diff
10g,'5
addc
log I 10,_offset (shft_ cnt]
.
l>
log - log
nxtloc
* tmpr+2 /
'tJ
256
'"......
UI
i
j
Log (M*N)
log
~
log + diff/256
8192/32
= Log
* 20LOG(x)
~
256
* 20LOG(x)
add log of normalization factor
M + Log N
log,'SCALE FACTOR
.t
log,zero log,FFT OUT[kptrJ
log, FIT=OUT[kptrJ
BR
ENDL
add
15
Make shift_cnt a pointer
Idbze
addc
<~
ptr, tmpr+3
j Most significant byte is table pointer
ptr,ptr,ptr
;
ptr,# LOG_TABLE-256
j ptr= Table + offset
(offset=tmpr+3)
Use -256 since tmpr+3 i8 always >= 128
log, [ptrJ+
DxUoe, fptrJ
j j Linear Interpolation
sub
LOG STORE:
sbr
$eject
Nonaalize and get normalization factor
Divide to prevent overflow during
averaging of outputs
270189-40
/CS-96 MACRO ASSEMBLER
ERR
we
rrT_RIJIi
DBJIICT
2443
2443 0156
2445 0F5624
2448 D705
244A C04200
244D 2029
!:
!!L
3"
10
N
~
ii:
q>
~
I\)
C»
244F
244r AC274B
2462 444B4B4B
2466 65083948
245A A24r40
245D A24B44
2460 684044
c»
2463 AC263C
2466 6C443C
'TI
'TI
2469 AC3D3C
'V
0
246r 44565656
DI
2473 6F57C83940
CD
..
..
-t
10
3
C'0 5
a
::l
c:
CD
.s
B
2460 643040
2478
2478080042
247B A4OO42
247B 674DOOO042
2463 C34DOOO042
2488 6502004C
248C 69020060
2490 DF022BB4
LINI!
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
02/18/66
SOUIICII STATIIIIBNT
B
II
II
B
***
DOI'llI
tlipr. shft_cnt
Jue
SQRT_III_IWIGB
at
zero.sqrt+2
br
SQRT_sroJIB
Normalize and ,et 'normalization factor
Ju.p if t.pr > 0
SQRT III 1IAMlB:
-
-ldbze
add
add
ptr, t.pr+3
ptr,ptr,ptr
; Moat significant byte ia table poiDter
'
1d
1d
ptr,' SQ_TABLB-266
; ptr= Table + offset (offset=t.pr+3)
Us. -256 siDee t.pr+3 is a1wap >= 128
aqrt, [ptr]+
DXtlOC, [ptr]
;; Linear Interpolation
aub
DXtloc,.qrt
mct10c = sqrt - uext aqrt
1dbze
diff+1 = mctloc
au1u
diff, f:Iopr+2
diff, DXtlOC
1dbze
add
diff, diff+1
aqrt,diff
aqrt = sqrt + delta
add
IIhft_cut, ahft_cut, IIhft_CDt
.au
sqrt, tab_aqr[shft_cut]
* blpr+2 /
256
~
...~
(diff ( OrrB)
01
divide by Do.....li.ation factor
i; aulu acta . . divide .iDee if tab2=OI'lTFll
; i' sqrt would re.a.in eaaeutialy uuch.lmged
SQRT_S!ORB:
ahr
addc
add
at
354
355
356
357
358
359
360
361
362
363
CALCIILATB SQUAIIB ROOT
(
9
8hft.~cnt
c1r
348
349
350
361
352
363
***
CALC_SQRT:
PAGB
sqrt+2, tscALB_FACroR
sqrt.f-2. zero
aqrt+2,rrT_DUT[kptr]
aqrt+2,rrT_OUT[kptr]
;;;;
***
END
or
D1vide to prevent overflow duriDl'
averq1DII of output.
LOOP
***
960 BIT
BllDL:
sub
kptr,t2
D_aub_k,t2
bDe
1IIf_LOOP
add
J[
364
2494 FO
365
366
RBT
.eject
270189-41
~ _ ~~
ERR LOC
OB.l!!CT
3800
3800
m__
LIN!!
367
368
369
370
""""
SOURCE STATllMBHT
; $nolist
CSEG AT 3800&
I
BRBY:
; 2*bit reversal value
DCII
2*0,
2*2,
2*1,
2*3,
,
,
,_
w
'
_.
c(
Use 2k for tables
,
371
c:
SCD
In
1\)1
.....
Ui
!i:
~
OJ
,
."
."
....
-I
~
"rJ
o
CD
Dl
3
o
~
ao
:l
~
Co
~
3800
3810
3820
3830
0000200010003000
0400240014003400
0200220012003200
0600260016003600
3840
3~0
3850
3860
3870
3880
3890
38A0
3890
3000
0000OO0CF9182825
825AFl626D6AE270
FF7F617F897D7C7A
825A33511C47563C
000074F307B7080A
7BASOF9D93951E8F
01809F8077826485
7BASCDAEB4BBAAC3
0000
3002
3002
38D2
3882
38F2
3902
3912
3922
3932
3942
FF7F617F897D7C7A
825A33511C47563C'
000074F307E7D80A
7EASOF9D93951E8F
01809F6077826485
7EASCDAEE4B8AAC3
0000OO0CF9182825
825AFl626D6AE270
FF7F
3944
3944
3954
3964
3974
3984
FF7F897D41766D6A
000007B705CFE4B8
01807782BF899395
0000F918FB301C47
FF7F
3986
3986
3996
39A6
39B6
3ge6
000007B705CFE488
01807782BF699395
0000F918FB301C47
FF7F897D41766D6A
0000
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
~:
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
DeW
Dew
Dew
SINFN:
Dew
Dew
Dew
DCII
Dew
Dew
DCII
Dew
Dew
COSFN:
Dew
Dew
Dew
Dct/
Dew
Dew
Dew
Dct/
Dct/
WR:
Dct/
Dew
DCII
Dew
Dew
If!:
IJCII
Dew
DClf
Dew
Dct/
2*16,
2*18,
2*17,
2*19,
2*8,
2*10,
2*9,
2*11,
2*24,
2*26,
2*25,
2*27,
2*4,
2*6,
2*5,
2*1,
2*20,
2*22,
2*21,
2*23,
2*12,
2*14,
2*13,
2*15,
2*28
2*30
2*29
2*31
0,
3212,
6393,
9512,
23170, 25329, 27245, 28898,
32787, 32609, 32137, 31356,
23170, 20787, 18204, 15446,
0, -3212, -6393, -9512,
-23170, -25329, -27245, -28898,
-32767, -32609, -32137, -31356,
-23170, -20787, -18204, -15446,
0
12539, 15446, 18204, 20787
30273, 31356, 32137, 32609
30273, 28898, 27245, 25329
12539,
9512,
6393,
3212
-12539, -15446, -18204, -20787
-30273, -31356, -32137, -32609
-30273, -28998, -27245, -25329
-12539, -9512, -6393, -3212
32767, 32609, 32137, 31356,
23170, 20787, 18204, 15446,
0, -3212, -6393, -9512,
-23170, -25329, -27245, -28898,
-32767, -32609, -32137, -31356,
-23170, -20787, -18204, -15446,
0,
3212,
6393,
9512,
23170, 25329, 27245, 28898,
32767
30273, 28898, 27245, 25329
12539,
9512,
6393,
3212
-12539, -15446, -18204, -20787
-30273, -31356, -32137, -32609
-30273, -28898, -27245, -25329
-12539, -9512, -6393, -3212
12539, 15446, 18204, 20787
30273, 31356, 32137, 32609
II»
"U
I
I\)
til
,,"
WI! = COS(K*2PI/N)
32767, 32137, 30273, 27245, 23170, 18204, 12539,
6393
0, -6393, -12539, -18204, -23170, -27245, -30273, -32137
-32767, -32137, -30273, -27245, -23170, -18204, -12539, -6393
0,
6393, 12539, 18204, 23170, 27245, 30273, 32137
32767
;;;;
WI = -SIN(K*2PI/N)
-0, -6393, -12539, -18204, -23170, -27245, -30273, -32137
-32767, -32137, -30273, -27245, -23170, -18204, -12539, -6393
0,
6393, 12539, 18204, 23170, 27245, 30273, 32137
32787, 32137, 30273, 27245, 23170, 18204, 12539,
6393
0
$eject
270189-42
_.
MCS-96 MACRO ASSBMBLBH
BHH LOC
OBJBCT
3008
3008 FFrI'04B50080825A
3908 0010500BOOO8A805
!:
IIJ
3988 0001B50080005BOO
39F8 10000BOOO8000600
S'
IQ
N
I
»
en
:s::
CD
Q)
.. ...
q>
I\)
'11
'11
-I
'tI
I
II
446
447
t
SOUHCB STATBMBNT
tINK
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
PAG!
$eJect
270189-43
....
I\)
(It
--
MOS-96 MACRO ASSEMB18R
ERR LOC
OBJECT
3808
[
5'
ID
~
5:
CD
Q)
3B08
3810
3B28
3B38
3B48
3B58
3B68
3B78
3B88
3898
3BAB
3BB8
3BC8
3BD8
3BB8
3BF8
3C08
00002A024F047006
DAI0C312E914BA16
BD20A92292247826
C42F973166333335
063BC13F7A413043
954B3C4DDF4E8150
8458175AA85B365D
DE646066E0675D69
B370247294730275
OB7C6B7DCF7B2FBO
F28647889B89BDBA
70918892FF934595
8B9BC89C049B3B9F
4CA57BA6AFA7DEAB
89A1!BOAF07Bl2CB2
D6B7F4B811BA2DBB
A9CO
3COA
0>
"TI
,
"TI
i\j-i
CD
'lJ
~
iil
3
'§
::I
g.
C
CD
S
3COA 4F5A4A54454B3F48
JelA 252A20241AIB1518
3C2A
ASSEMBLY COMP18TED,
FFT_RIIN
LIN!!
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
02/18/86
PAGIl
t
12
SOURCB STATJ!/oII!NT
LOG_TAB18:
16384*lO*LOG(n/128)
Dew
Dew
Dew
554,
4835,
8873,
12695,
16321,
19772,
23063,
26208,
29220,
32110,
34887,
37560,
40136,
42622,
45024,
47348,
new
Dew
Dew
DCW
Dew
Dc\1
Dcrl
Dew
Dew
Dew
DC\!
DW
new
Dew
0,
4314,
8381,
12228,
15878,
19349,
22660,
25822,
2RR51,
31755,
34546,
37232,
39819,
42316,
44729,
47062,
49321
LOG_OFFSeT:
1103,
5353,
9362,
13158,
16762,
20191,
23464,
26592,
29588,
32463,
35227,
37887,
40452,
42927,
45319,
47633,
1648,
5866,
9848,
13619,
17200,
20609,
23862,
26973,
29954,
32815,
35565,
38213,
40766,
43230,
45612,
47917,
n= 128 ,129 ,130 ... 256
2190,
6376,
10330,
14076,
17635,
21024,
24259,
27353,
30318,
33165,
35902,
36537,
41079,
43533,
45905,
48200,
; 512*l0*LOG(2**(15-n»
; 512*l0*LOG(0.5)
2727,
8683,
10810,
14531,
18067,
21436,
24653,
27730,
30680,
33512,
36236,
38860,
41390,
43833,
46186,
48482,
3260,
7386,
11286,
14983,
18497,
21846,
25045,
28106,
31040,
33859,
36570,
39181,
41700,
44133,
46486,
48763,
3789
7885
11758
15432
18925
22254
25435
28479
31399
34203
36901
39501
42009
44431
46774
49042
n= 0,1,2,3 ... 15
n= 16,17,18 ... 31
:to
"tJ
I
Dew
DCW
I\)
23119, 21578, 20037, 18495, 16954, 15413, 13871, 12330
10789, 9248, 7706, 6165, 4624, 3083, 1541,
0
I I
END
NO ERROR(S) FOUND.
270189-44
......
en
AP-275
The BASIC program is used as comments in the
ASM96 program. Some of the variables in the ASM96
program have slightly different names than their counter-parts in the BASIC program. This was to make the.
comments fit into the ASM96 code. Highlights in this
section of code are a table driven square root routine
and log conversion routine which can easily be adapted
for use by any program.
Both the square root routine and the log conversion
routine use the 32-bit value in the variable TMPR. The
square root routine calculates the square root of that
value in the variable SQRT+2, a 16-bit variable. In
this program, the square root value is averaged and
stored in a table.
The log conversion routine divides the value in TMPR
by 65536 (2 16) and uses table lookup to provide the
common log. The result is a 16-bit number with the
value 512 • 10 Log (TMPR/65536) stored in the variable LOG. This calculation is used to present the results of the FFT in decibels instead of magnitude. With
an input of 63095, the output is 512*48 dB. The graph
program, (Section 10), prints the output value of the
plot as INPUT/512 dB.
overIayable, use caution when implementing this routine with others with overIayable registers.
Lines 116-124 calculate the power of W to be used.
Note that KPTR is always incremented by 2. The multiple right shift followed by the AND mask creates an
even address and the indirect look to the BR (Bit Reversal) table quickly calculates the power PWR.
Lines 130-138 perform the complex multiplications.
Since WIP and WRP range from - 32767 to + 32767,
the multiplication is easy to handle. The automatic divide by two which occurs when using the upper word
only of the 32-bit result is a feature in this case.
Lines 144-163 use right shifts for a fast divide, then add
or subtract the desired variables and store them in the
array. Note that the upper word of TMPR and TMPI
is used, and the same array is used for both the input
and output of the operations.
Lines 165-189 update the loop variables and then check
for errors· on the complex multiplications and additions. If there are no overflows at this time the data will
run smoothly' through the rest of the program.
The following descriptions of the ASM code point out
some of the highlights and not-so-obvious coding:
Lines 200-212 load variables with values based on the
bit reversed values of pointers.
Lines 1-104 initialize the code and declare variables.
The input and output arrays of the program are declared external. Note that many of the registers are
Lines 214-236 perform additions and subtractions to
prepare for the next set of formulas. Note that XITMP
and XRTMP are 32-bit values.
6-130
intJ
AP-275
Lines 240-260 perform mUltiplies and summations resulting in 32-bit variables. This saves a bit or two of
accuracy. The upper words are then stored as the results.
Lines 263-272 generate the squared magnitude of the
harmonic component as a 32-bit value.
Lines 278-310 calculate 10 Log (TMPR/65536). The
32-bit register TMPR is divided by 65536 so that the
output range would be reasonable.
First, the number is normalized. (It is shifted left until a
1 is in the most significant bit, the number of shifts
required is placed in SHFT_CNT.) If it had to be
shifted more than 15 times the output is set to zero.
Next, the most significant BYTE is used as a reference
for the look-up table, providing a 16-bit result. The next
most significant BYTE is then used to perform linear
interpolation between the referenced table value and
the one above it. The interpolated value is added to the
directly referenced one.
The 16-bit result of this table look-up and interpolation
is then added to the Log of the normalization factor,
which is also stored in a table. This table look-up approach works fast and only uses 290 bytes of table
space.
Lines 321-357 calculate the square root of the 32-bit
register TMPR using a table look-up approach.
First, the number is normalized. Next, the most significant BYTE is used as a reference for the look-up table,
providing a 16-bit result. The next most significant
BYTE is then used to perform linear interpolation between the referenced table value and the one above it.
The interpolated value is added to the directly referenced one.
The 16-bit result of this table look-up and interpolation
is then divided by the square root of the normalization
factor, which is also stored in a table. This table lookup approach works fast and only uses 320 bytes of table
space. The results are valid to near 14-bits, more than
enough for the FFT algorithm.
Lines 352-360 average the magnitude value, if multiple
passes are being performed, and then store the value in
the array. The loop-counters are incremented and the
process repeats itself.
This concludes the FFT routine. In order to use it, it
must be called from a main program. The details for
calling this routine are covered in the next section.
8.0 BACKGROUND CONTROL
PROGRAM
The main routine is shown in Listing 3. It begins with
declarations that can be used in almost any program.
Note that these are similar, but not identical, to other
8096 include files that have been published. Comments
on controlling the Analog to Digital converter routine
follow the declarations.
6-131
MOS-96 MACRO ASSBllBLER
FFT_MAIN_APNOTB
02/18/86
cl
PAGE
SERIES-III MOS-96 MACRO ASSBMBLER, Yl.O
SOURCB FILE: : F2: FnlAIN. A96
OBJECT FILE: :F2:FnlAIN.0B.1
CONTROLS SPECIFIBD IN INYOCATION CIMIWIO: YOSB
BRR Lac
OBJECT
LINE
1
SOURCE STATBMBNT
$pag..leugth(50)
2
3
4
5
6
7
FFT_fofAIN_APNOTB MODULI! MAIN, STACKSIZB(6)
Intel Corporation, January 24, 1986
by Ira Horden. f«X) Applications,
8
9
10
11
c:
1/1
c!:
:::l
ca
w
enl
.!.. iil:
f:S ~.
::D
oc
i
0000
0002
0002
0003,
0003
0004
0004
0006
0006
0007
0008
0009
0011
0011
OOOA
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
=1
'=1
=1
=1
=1
=1
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
This prograa perfOl'1lB an FFT on real data and plots' it on a printer.
It uses the progr811 modules A2DCON, PLOTSP, and FFTRUN. The adjustable
paraaetera of each of the progr81U are 8et by thia Jll8.in JIOduie.
$INCLUDE (:FO:DI!M096.INC)
;$no118t
;
; Include SrK definitions
Turn listing off for include file
l>
;*******************************************************************************
l'
N
.....
en
Copyright 1985, Intel Corporation October 28,1985
by Ira Horden, NCO ApplicatioDS
D1!f1096. INC - DEFINITION OF SYMBOLIC NAMBS FOR THE I/O REGISTERS OF THE 8096
;***l~***************************************************************************
ZERO
AD_ClMWID
AD IIflSULT LO
AD=RflSULT=HI
RBI !IODB
HSO-TIMB
RBI=TIMB
HSO ClMWID
RBI=STATUS
SBUF
INT_lIASK
INT_PBNOING
SPCOII
SPSTAT
IfATCIIDOG
EQU
EQU
EQU
EQU
BQO
EQU
EQU
EQU
EQU
BQU
EQU
BQU
EQU
EQU
EQU
DOh: lIORD
02H: BYTE
02H: BYTE
03H:BYTE
03H:BYTE
04H: lIORD
04H: lIORD
OSH: BYTE
OSH: BYTE
,078: BYTE
OSH: BYTE
098: BYTE
llH: BYTE
llH: BYTE OAH:BYTE
II/tI
"
Zero Register
A to D cOIIIIlIlDd register
LoW byte of reIIul t and channel
B
R
If
If
R
If
R
II/tI
II/tI
R/W
High byte of reaul t
Controls RBI trsnai tion detector
RBI tbe tag
RBO tbe tag
RBO.,.,....,d tag
RBI status register (reads fifo)
Serial port buffer
- Interrupt .ask register
W
Interrupt peDdin, re,ister
Serial port control register
Serial port status register
If
Watchdog tiller -
R
270189-45
MCS-96 MACRO ASSBMBLIR
I!RR LOC OBJECT
00001.
OOOC
00011
0001!
OOOF
0010
0015
0015
0016
0016
0017
0018
c
~
0000
00001.
::J
CQ
i:s::
III
q>
s·
-
c;j o
U)
ODIC
:II
c:
sCD·
11::!.
s·
ODIC
ODIE
0020
0022
ODIC
0010
0020
c.
CD
.9:
FFT_MAIK_APIIOTI!
LIKE
=1
42
=1
43
=1
44
=1
45
=1
46
=1
47
=1
48
=1
49
=1
50
=1
51
=1
52
=1
53
=1
54
=1
55
=1
56
=1
57
=1
58
=1
59
=1
60
=1
61
=1
62
=1
63
=1
64
=1
55
=1
66
=1
67
=1
68
=1
69
=1
70
=1
71
=1
72
=1
73
=1
74
=1
75
=1
76
=1
77
=1
78
79
60
02/18/86
SOURCII STATl!MBN"I'
TIMIIHI
IIQU
OAR: WORD
TIMB112
IIQU
OCR: WORD
PORTO
BQU
OEft:BYTE
BAUD_RBG
IIQU . DEft: BYTE
PORTI
EQU
om: BYTE
PORT2
BQU
10H: BYTE
lOCO
BQU
15H: BYTE
IOSO
EQU
15H: BYTE
lOCI
IIQU
16H: BYTE
IOSI
IIQU
16H: BYTE
PIII,,-COIlTllOL
BQU
17H:BYTE
SP
EQU
18H:WORD
BQU
IIQU
CH
LF
PUBLIC
PUBLIC
PUBLIC
PUBLIC
PUBLIC
R
Tillerl re,iater
R
Timer2 register
I/O port 0
Baud rate register
I/O port I
I/O port 2
I/O control register 0
I/O status register 0
1/0 control register 1
1/0 status regioter 1
PWM. control register
System stack pointer
R
11
Rill
Rill
W
R
W
R
W
R/W
PAGE
l
2
DOH
OAR
ZBRO,AD_C!MWID,AD_RBSULT_LO,AD_RBSULT_HI,B5I_MOOB,HSO_Tu.m,HSI_TIMI!
HSO_C!MWID
HSI_STATUS, sour, IN"I'_MASK, IN"I'_PIIKOIKG,KATCHDOG, TIMIIRI, TIMIIR2
OAUD RIIG, PORTO, PORTI, PORT2,SPSTAT,SPCON,IOCO, lOCI, 10SO, IOSI
PWMj:OIlTllOL, SP, CR, LF
~
"'C
RSI!G at ICR
All:
OSK
OX:
OSK
CX:
OSW
OSw
ox:
At
AR
OL
public
&x.
$list
EQU
EQU
BaU
•
N
-.J
Temp registers used in conformance
with PD1-96(tm) conventions.
All
(AII+l)
ox
(J1
: BYTE
: BYTE
: BYTE
bx. ex, dx. aI, ah. bi
Turn listing back aD
lind of include file
A20 UTILITY C!MWIDS/RIISPONSES FOR "CON"l'ROL_A20"
81
0007
.0010
0028
0001
82
busy
equ
7
83
84
con bO
equ
OOOlOOOOb; convert to BurFO
OOlOIOOOb; download OurFO
85
86
,----------
87
88
_"
AVR_NlJ!oI
equ
equ
as pAIRIIO SIGNED data
---------------------Nw::aber of times to average the waveform
AVR_NUM < 256
270189-46
I«:S-96 MAC\IO ASSBMBLBft
1l1li LOC
OBJBCT
0000
0100
0080
9100
FfT_MAIN_APlIOTB
02/18/86
LINB
501J1iCB STATBMBNT
89
equ
90
SCAL8]ACTOft
91
92
93
equ
94
PLOT_IlBS
95 - PLOT_IlBS_2
equ
96
equ
PLOT_'IAJ[
'¥1
98
o
(
PAGE
_ r of riihta shifts perfol'1lll!
For rrr routiDe
For A2D routine
For rrr routiDe
121
!
122
0200
0200
0200
0240
02C0
123
124
125
126
PlJBLIC DIST_BIDT_BASE, IRBAL, XDWl
OSlO AT 20011
127
PLOT IN:
128
FfTjiur:
129
Burro_BASIl:
BUrrI_BASE:
130
131
132
133
PlJBLIC
DSW
DSW
DBII
32
64
64
For FfT routi....
For A2D routiue
For A2D routine
Burro_BASE, BurrI_BASE, FfT_OU'l, PLOT_IN
$eject
270189-47
_.
MCS-96 MACRO ASSEMBLER
RRR LOC
FFT_MAIN_APHOTI!
LINK
OBJECT
2080
2080
2084
2089
2089
20SC
AI000018
ASOI00301C
R
BOICro
BOIDrA
C
20ar RFOOOO
!:t
2092
2092 BI0000
B
In
::I
CQ
R
Co)
I
il:
III
9'
......
U)
0'1
S"
lJ
0
...S"
a
a
C
CD
0
::J
2095
2098
209A
209r
20AS
20A7
BI0I02
0120
C321000200
65020020
89400020
DRF!
20A9300004
20AC 2819
20AR 2002
R
R
20BO 282F
c:
CD
S
20B2 310002
2085 2SCB
R
20B7 BFOOOO
20BA 980001
20BD D7FB
B
R
20Br R00205
R
2002 BFOOOO
B
2005 27CB
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
02/18/86
PAGR
cf
4
SOURCR STATBMI!NT
CSIG AT 2080R
RXTRN
EXTRN
EXTRN
LD
LD
SDR_WAIT:
For Plot Routine
For EFT routine
For A2D routine
SP,ISTACB
AX,3000H
aI, abe_wait
ah,abe_wsit
WAIT FOR SBB TO CLEAR SBRIAL PORT INTRRRllPTS
djnz
CALL
INIT_OUTPUT
Initialize serial port
djnz.
BEGIN:
INIT_OUTPUT, DRAW_GRAPH, CON_OIlT
rFT_CALC
A2D_BUFF_IlTIL
NBIi_TRANSFOIiICSRT:
Idb
ttt_mode,IOOOOB
Idb
clr
CLRRAM: at
add
cmp
bIt
C_load: bbc
CALL
br
-
Real data / Tabled datal
Windowed / Unwindowedot
1010g Mag"'2 / Magnituciet
256*db plot / Normal Plotot
avr_cnt,.avr_nus
zero, ff't_out{bx]
bx,#2
»
clear fit magnitude array
,
'tI
bX,ot64
CLlII!AM
fft_lIOde, 0 t do_tab
I I
Branch if real data is not used
LOAD_DATA
C_win
do_tab: CALL
TABLE_LOAD
ftt_DIOde, I. calc
CALC:
CALL
errtrp: cmpb
Jne
0
1
2
3
bx
C_win:
bbc
CALL
Bit
Bit
Bit
Bit
Branch if windOti'ing is not used
DO_WINIlOIi
rFT_CALC
error, zero
errtrp'
DJNZ
avr_cnt, LOAD_DATA
CALL
DRAW_GRAPB
DB
NBIi_TRANSFOIifoCSBT
repeat for AVR_NlM couuts
$eJect
270189-48
N
-.!
U1
MCS-96 MACRO ASSIiMBLEft
ERR LOC
FFT_MAIN_APROTB
OB.Tl!CT
2OC7
20C7 BI000F
20CA
20CA Bll000
20CD 910100
2000 A1320000
2004 EFOOOO
2007 3FOOm
i-I
CQ
200A
200A B12800
2000 BFOOOO
20BO FO
W
I
;:
III
q> :i"
-"
W
0>
lJ
0
S.
5"
(11
(5
0
;::!.
20Bl
20El
20B3
20B7
20BA
20BD
20n
20F7
20rn
20FF
2101
:;-
2102
(1)
2102
2112
2122
2132
2142
2152
2162
2172
c
.s
0120
AI02211C
A21D22
A21DIE
C321000022
C321COOOIB
65020020
89400020
DBB6
FO
FF7FFF7FFF7FFF7F
lF7FrF7FrF71FF7F
FF7FFF7FrF7FFF7F
FF7FFF7FlF7FrF7F
0180018001800180
01800180018001800180018001800180
0180018001800180
B
B
B
B
B
B
E
LINK
180
181
182
183
184
185
186
187
188
189
190
191192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
02/18/86
(
PAGB
SOUllCE STATl!MBNT
j------------------------------------------
LOAD_DATA:
LOAD DATA INTO RAM
iiij
;**** FOR INDICATION ONLY
Idb
portl.#OO
Idb
orb
Id
control_a2d.#COD_bO
control_a2d. tol
sample_period. #50
Set CODverter for bufferO
CALL
a2d buff util
control_&2d. busy 1$
Start the cODversion prOCMS
wait for all conversioDs to be done
SBT_A2D:
jbs
Down load:
Idb
CALL
RET
Convert chaDnel 1
100 us sample period
control_a2d ••dlDDP_bO-P_B
a2d_buff_util
download bO paired/signed
;-------------TABLE LOAD:
-
load:
clr
bx
ax,'DATAO
cx. (ax]+
Id
Id
Id
st
at
add
dx, [ax]+
cx,xreal[bx)
dx,x!.mag[bx)
bx , #2
ClIP
bx.'64
blt
Load tabled data for testing
l>
"P
N
.......
U1
LOAD
RET
DATAO:
DCW
DCW
Dew
DOW
Dew
DOW
Dew
DCW
; S~UARB IfA~B
32767,
32767,
32767,
32767,
-32767,
-32767,
-32767,
-32767,
32767,
32767,
32767,
32767,
-32767,
-32767,
-32767,
-32767.
32767,
32767,
32767,
32767,
-32767,
-32767,
-32767,
-32767,
32767,
32767,
32767,
32767,
-32767,
-32767,
-32767,
-32767,
32767,
32767,
32767,
32767,
-32767,
-32767,
-32767,
-32767.
32767,
32767,
32767,
32767,
-32767,
_-32767.
-32767,
-32767.
32767,
32767,
32767,
32767,
-32767,
-32767.
-32767,
-32767,
32767
32767
32767
32767
-32767
-32767
-32767
-32767
$eject
270189-49
MCS-96 MACRO ASSBMBLBR
IRR LOC
is·
ID
t
OJ
!!!.
::I
.!.. ::rJ
~ g
5-CD
'§
~
5i
So
2182
2182
2184
2186
2186
2188
2190
2197
21911
21Al
21A4
21AS
21A1
21B2
21B6
21BA
21BC
OBJI!CT
0120
0121
A32DBI211C
A32DC02120
R4r2F80001C24
R4r2FC0002028
OD0124
ODOl28
C32F800026
C32FC0002A
65040020
65020028
89400028
D7CA
1'0
21BI
2181
21CI
2101
2111
21R
2201
221B
2221
223B
000041'003801CI02
BrI26517711CD421
004045467C409352
4060787136757078
rF7FB07FC47H317D
406D99688E632B5E
0040BA3983336C2D
BFl2870IC90AlI'07
0000
rFT_MAIN_APIIOTII
LINK
223
224
225
226
227
228
228
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
02/18/86
PAGE
(
6
SOUReB STATBMBNT
Ix, WINDOW: - - - - - -
PSRFOIiM IlAHNING WINDOW
c1r
elr
wndptr
varptr
1d
1d
au1
aul
ohll
shll
at
at
lIX,bsnniDII(wndptrj
bx,bsnniDII+2(wndptrj
blprea1,IIX,xresl(varptrj
blpimlll, bx, xiBall( varptr j
blpreol, #1
blpiBall,#l
blpreal+2,xreal(varptrj
blpiBall+2,ximlll(varptrj
wndptr, #4
varptr.'2
varptr, t64
window
WiDdowiDII provides an -effective
divide by 2 because of tbe 1III1tiply
WINDOW:
add
add
alp
Joe
COIIPSDSate for the divide by 2
RBT
IlAHNING:
DeW
DeW
DeN
DeW
DeW
DOW
DeW
DeW
DeW
; Windowing f"UDction
0,
4799,
16384,
27968,
32767,
27968,
16384,
4799,
0
79,
5990,
17989,
29048,
32688,
26777,
14778,
3719,
315,
7281,
19580,
30006,
32452,
25486,
13187,
2761,
705,
8660,
21139,
30832,
32062,
24107,
11628,
1935,
1247,
10114,
22653,
31520,
31520,
22653,
10114,
1247,
1935,
11628,
24107,
32062,
30832,
21139,
8660,
705,
2761,
13187,
25486,
32452,
30006,
19580,
7281,
315,
.
»'tJ
3719
14778
26777
32688
29048
17989
5990
79
II
'eject
270189-50
N
.....
C11
_.
MCS-96 MACRO ASSIlMBLBR
BRR LOC
Oll.JBCT
3DOO
3DOO
3DOO
3DI0
3D20
3D30
3D40
3D50
3D60
3D70
..
r
iii"
S·
IQ
Co)
I
s::
II)
~
(.0)
CD
S·
XI
0
C
::r.
:::s
CD
'0
0
~
:::s
C
CD
.s
00003351897DB270
7BA574F31C477C7A
01BOOF9D08B7563C
7BA59F809395D8DA
000OCDAB77821B8F
825A8COC84888485
FF7FFI62F818AAC3
825A617F6D6A2825
3DBO
"
3D80
3090
3DAO
3DBO
3DCO
3000
3080
3DrD
0000F555617FCF66
05CFIF288270287C
7BA5B8F933519C7B
BF8946C92825C96D
01B029A174F33F4C
BF897C87AAC3IA1F
7BA528800F9038BD
05CF4B8C848533B8
3EOO
3EOO
3RlO
3820
3B30
3840
3850
3860
3B70
000OC63C0F5AAF48
5FDD7ClBCr4FC857
03C08FFB69398459
65AC4FD9451A9B4D
82A5r38C21F7B835
65ACCCAA58D5FDI5
03C09BA5OCBAB9F2
5FDD32AE67A97ADI
3BBO
3880
3E90
3EAD
3EBO
3Boo
3EDO
3BB0
3BFO
3FOO
0000FD04B40472FF
00045CFB74FA69FC
58FA55FD2403AI05
00046A051ADlAIFB
000003FB4CFB6B00
00FCA401BC058703
A805AB02DCrcsrrA
00FC96FAB6FB5F04
FFT_MAIN_APNOTB
LIN!!
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
2BO
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
287
298
299
300
301
02/18/86
I
PAGB
cf
SOURCE STATBMIlNT
CSBG AT 3D008
DATAl:
Dew
DCW
UCW
UCW"
Dew
UCW
DCW
DCW
DATA2:
new
Dew
Dew
new
Dew
Dew
Dew
DCW
DATA3:
new
new
new
Dew
new
Dew
new
Dew
DATA4:
new
Dew
Dew
Dew
new
new
new
Dew
DATA5:
; ADDITIONAL
; SIN!! 7.0 X
TABLES
FOR T1!STING
0, 20787, 32137, 28698, 12539, -9512,-27245,-32609
-23170, -3212, 18204, 31356, 30273, 15446, -6393,-25329
-32767,-25329, -6392, 15446, 30273, 31356, 18204, -3212
-23170,-32B09,-27245, -9512, 12539, 28898, 32137, 20787
-0, -20787 ,-32137, -28898,-12539, 9512, 27245, 32609
23170, 3212, -18204, -31356, -30273, -15446, 6393, 25329
32767, 25329, 6392, -15446, -30273, -31356, -18204, 3212
23170, 32609, 27245, 9512, -12539, -28890, -32137, -20787
; SIBB 7.5 X
0, 22005, 32609, 26319,
-12539, 11039, 28898, 31785,
-23170, -1608, 20787, 32412,
-30273,-14010, 9512, 28105,
-32767,-24279, -3212, 19519,
-30273, -3085?, -15446, 7952,
-23170,-32728,-25329, -4808,
-12539, -29521, -31355, -18845,
6393,-16846, -31356, -29621
18204, -4808,-25329,-32728
272g5, 7982,-15446,-30852
32137, 19519, -3212,-24279
32137, 28105, 9512,-14010
27245, 32412, 20787, -1608
18205, 31785, 28898, 11039
6393, 25319, 32609, 22005
l>
'U
I
II
; .707OSIBB 7. 5X
0, 15558, 23055, 18607,
-8865, 7B04, 20431, 22472,
-16381, -1137, 14697, 22916,
-21403, -9905, 6725, 19870,
-23166,-17165, -2271, 13800,
-21403,-21812, -10920, 5629,
-16381,-23138,-17908, -3399,
-8865,-20942,-22169,-11910,
4520, -11910,-22169, -20942
12870, -3399,-17908,-23138
19262, 5629, -10921, -21812
22721, 13800, -2271,-17165
22721, 19870, 6725, -9905
19262, 22916, 14696, -1137
12871, 22472, 20431, 7804
4520, 18607, 23055, 15557
; • 7070SIBB (l1x) /16
0, 1277, 1204, -142, -1338, -1119,
282, 1386
1024, -420, -1420, -919,
554, 1441,
804, -683
-1448, -683,
B04, 1441,
554, -919, -1420, -420
1024, 1366,
282, -1119, -1338, -142, 1204, 1277
-0, -1277, -1204,
142, 1338, 1119, -282, -1386
-1024,
420, 1420,
919, -554, -1441, -804,
683
1448,
683, -804, -1441, -554,
919, 1420,
420
-1024, -1386, -282, 1119, 1338,
142, -1204, -1277
; .701*(SIHB 7.5X + 1/16 SIBB llX)
270189-51
I\)
......
en
MCS-96 MACRO ASSBllBLlR
BRR LOC
3100
3rlO
3F20
3F30
3r40
3F60
3F60
3"0
OBJECT
000OC241C35E2148
5BE1081C434A3154
5BBAB5F8BD3C245F
55BOB9DE5FlB3F49
82A5F6B76DF27636
55A870ACE4DA9419
ABC54BABEBB61BBD
5FD9CIlA84DA6D9D5
3FBO
riii
ASSBMBLY COMPLETED,
FFT_MAIH_AP!IOTB
LINB
302
303
304
305
306
307
308
309
310
311
312
313
02/18/86
PAGE
l
8
SOURCB STATBIIBNT
DCII
DCII
DCII
DCII
DCII
DCII
DCII
DCII
0, 16834, 24259, 18455,
-7842, 7384, 19011, 21553,
-17829, -1819, 15501, 24356,
-20379, -8519, 7007, 18751,
-23166,-18442, -3475, 13942,
-22427,-21392, -9500, 5548,
-14933,-22456,-18712, -4840,
-9889,-22328,-22451,-10791,
3182,-13029,-21886,-19557
13425, -1958,-17103,-23821
19816, 4710,-12341,-22232
21383, 13558, -1067,-15888
24059, 20990, 6442,-11290
18708, 21475, 13892, -454
12317, 23391, 21851, 8225
5857, 18749, 21851, 14281
END
110 BRROR(S) FOUND.
270189-52
~
0)
~
~
3"
:II
c.l 0
(0
~
CD
9
g.
c:
~
~
l'
N
.....
U1
intJ
AP-275
SBRlBS-III MCS-96 RlLOCATOR AND LINKBR, V2.0
Copyright 1983 Intel Corpor"Uon
INPUT FILES: :F2:F'lMAIN.OBJ, :F2:FFTRUN.OBJ, :F2:PLOTSP.OBJ, :F2:A2DCON.OBJ
OUTPUT FILE: : F2: FFTOUT
CONTROLS SPBeIFliD IN INVOCATION C.
I
CAl
0
0
0
0
::::I
<
CD
~
.,
CD
:u
0
c
::!:
::::I
CD
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
A2D_Bufferin,_Utility
JROdule
atacksize(12)
Intel Corporation, J'uly 16. 1985
by Dave Ryan. Intel Applications Engineer
Tbis utility fills a memory buffer with AID conversion results. The
conver.toDS are done under interrupt control, and are initiated when
A2D BUFF Uti1 is called. The results of the coDversions are placed
in ;;:ne of two buffers I called BUfFO and BUFri.
This utility provides OptiODS for the selection of the buffer lengths. data
format. saple period. conversion channel and time base. The utility also
has a donwload routine that will load either buffer into B register file
buffer. Output formats can also be chosen for the downloaded buffer. The
data can be formatted as signed or unsigned linear or paried arrays.
.
l>
."
...,
J\)
RUN-TIM!! OPTIONS
(11
Rather than use the STACK to pass controls, this utility gets its directions
from 2 control words iD memory. The utility expects that itll control words
are valid at the time A2D_BUFF_Util is called and remain· valid throughout
AID interrupt executions and downloads. The control words are:
25
26
27
28
29
SBllPle Period
-
WORD
The tt.e between BBlllPlell in tbter counts
where the timer used has been specified
30
31
Control A2D
-
BYTE
Control info1'1l8tion for the utilit'y;
BIT'
32
33
0-2
34
3
4
5
35
36
37
38
39
40
41
6
7
Channel liulllber
Signed Result/Unsigned Result'
CODvert/DOWDload'
BUFFl/BUFFOf for coDversions
BUFFO/BUFF1' for downloads
Linear/Paired'
Converter BUSY/lOLl'
$BJl!CT
270189-54
MCS-96 MACIID ASSBMBLBR
SRR LOC
OBJJ!CT
A2D_BUFFBRDIG_UTILITY
LINB
42
43
44
45
46
47
48
49
50
51
r-
...
iii·
52
CD
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
:u
68
69
S·
ID
tl
:.-
...
0
C
0
0
q>
~
.j>.j>-
~
....
~
...
0
c
~
CD
00
3-
:r
c
CD
.s
'----
70
71
72
73
74
02/18/86
PAGE
(
2
SOUIICB STATBMBNT
The following i8 a table of equates that caD be used to amplify the
bit diddling requlreaenta. If you are not nmning conversions concurrently
with downloads, alwaye- LDB CODtrol_A2D with tbe following .,.,..,.,d than
ORB CODtrol_A2D with the channel oUllber you wish to convert if you are
starting a conversion.
ODce the utility is called, care.uat be taken when Control_A2d is'
aodified. You can cause downloada to occur while coDversions are running,
but you CSDDot start conversions during a download. To do this t ORB to the
control byte with the appropriate bits set. Do NOT change the BUFr bit or
the BUSY bit. Just set tbe downlosd bit and set tbe data fonoat bits to tbe
correct values.
The BUFF bit has opposite definitions for conversions and downloadll. This
allows conversions to be done into BurfO wbile downloads come frma BUFI'I. and
vice versa .
A2D UTILITY ClMWlDS
;coD_bO
icon_bI
dump_bO_l_u
dump_bl_l_u
dump_bO-"_u
dUllp_bl-,,_u
dump_bO_l_s
dUllp_bl_l_s
dump_bO-"_8
dUllp_bl-"_8
equ
equ
00010000&; COIIVert to BUFFO
0011oooob;"
BUFI'l
equ
01100000b
01000000&
00100000&
00000000&
01101000&
01001000&
00101000b
00001000b
equ
equ
equ
equ
equ
equ
equ
»
l.....
doomlosd BUFFO
as LlNBAR USIGNBD data
BUrrI"
"
BUFFO
doomlosd
..
"
PAIRED
BUrrI ..
BUFfO aa LINBAR SIGNBD
BUFrI"
"
BUFFO .. PAIRED
BUFFI ..
01
data
"
$eject
270189-55
MCS-96 MACRO ASSBMIlLBR
ERR toe
OBJECT
A2D_BUFFIIRING_DTILITY
LIIiB
75
76
77
78
79
02/18/86
PAGE
l
3
SOURCE STATllMBNT
ASSBllBLY-TIMB OPTIONS
The base addreases ad length of each conversion buffer and the destination
buffer are DECLARED BXnNal in this utility. Other options such 88 selection
of the timer used as a tillebase, the length of the buffer, and the effective
nUllber of bits in the reported reeult are set at as ...... ly ti... through use
of EQUates in this IIOdule.
80
81
82
83
c:
(I)
84
85
:J
86
87
=
!""
CQ
...
0
c
0
0
:J
Cf> <
.....
CD
.j>.
01
~
.,CD
::D
0
c
=
CD
BUFF_LENGTH
94
95
96
The nUllber of SAMPLES that each
; buffer IIIWJt hold. IIUIIt be >l and (256
Shift_count
The number of tilles
to be shifted right
position. Setting a
result in lo.t bits
97
98
99
100
101
102
103
:J
106
107
108
109
c
11>
.B
The starting address of BUFFO
The starting address of BUFFI
The starting eddress of the downloed
; target buffer.
, 91
92
93
00
:::l
BIJITO_BASE
BUFFl_BASB
DBST_BUFF_BASE
88
89
90
104
lOS
a
The following par.....tera need to be provided at as• .,.,ly or link time.
The buffer bases are declared BXTRHal by this utility, while the buffer
length shift count and RSO ~ds are BQUated.
llO
III
ll2
.
that the conversion result ls
from it. netural left justified
):0
'U
shift count greater than 6 will
to the rillht.
N
Rounding is NOT
......
en
done.
CLOCK
Specify as either TIMBRI or T2CLE.
This is the
tillebaae used for conversions.
,
Samples are stored as words in the buffers. The progrBJI stores
conversions linearly in BUFFO and BUFFI, and linearly or paired in the
destination buffer as selected. If the download is to be paired, the first
.8llple i8 placed in location DBST_BUFF_BASB, the second sllllple i. placed in
location (DBST BUFF BASE + BUFF LBNGTH), the third in (DSSr BUIT BASE + 2),
the fourth in (DEsr:BUFF_BASB +-2 + BUFF_LENGTH), etc.
-
SeJect
270189-56
1«:S-96 MAC1IO ASSBllBLBR
BRR LOC
OBJBCT
A2D _BUFFBRIHIl_ UTILITY
LINE
113
114
US
116
!Ii
3'
IC
cp
~
0>
0
0
0
0
~
ii
~
...CD
:D
0
c
3'
CD
'0
0
:3
3c
(1)
.s
U7
U8
U9
120
121
122
123
124
125
126
127
128
129
02/18/86
PAGE
l
4
SOURCB STATIIMBIIT
; NOTES ON BXBCUTION
When a utility call directs the initiatiOD of a set a'f A2D eonveraious. the
first coDversion i. besun at approx_tely one sapia t~ plus 50 atate
UJIeB frao when the utility ..... called. This a a _ thet DO iDterrupts are
present.
The couversiou busy bit is set approxiJoately 50 atate times after a call
to the utility, if the CODvert bit .... set iD the A2D_Coutrol byte. The
bwty bit is cleared after all CODVeraiou results bave beeu stored is the
reoult buffer deai_ted (Burro or BUFFl).
ralle great care is _ifyiDg the A2D_Coutrol byte to do a doomload while
; conversions are takin, place. You can never download 8 buffer that is
; beiDg COIlverted iDto. The results would he invalid.
$eject
270189-57
:..
l!.....
en
";:8-96 MACRO ASSBllBLBR
ERR toe
OBJECT
0000
!i-
s:
10
t0'
c
0
0
.....,
(l)
:!:j
:l
0040
0001
OOOA
DOOA
OODe
0000
0001'
0000
<
CD
~
CD
...
0020
:u
0
c
s-
CD
'§
::I
t:!:
::I
0000
0002
0004
0006
0008
C
CO
.e,
0009
0003
0004
0005
A20_BllI'I'BRING_UTILITY
LINE
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
169
160
161
162
163
164
165
166
167
168
169
(
5
RSBG
ElITRII BUFFO_BASB, BUFF1_BASB, DEST_BUFF_BASB
BXTIiIi ad_coo.and. ad_reeu1t_1o. ad_ratlult_hi
BXTRH hao_~d, hso_tille ••p
BUFF L8/1GT11
Shift Count
CLOCB-
EQU
EQU
EQU
64
1
TIMIIRI
eet up hso COIIIIlBIlds for correct tiMr
TIMIIRL
T2CLB
equ
equ
**********************************
OAK'
DeB
MASK
equ
(10h>ICLOCB)AHD (40h)
Start_A2D
equ
(OOOOllllb)OR(MASK)
;atart a2d baaed on tiJRer 1. no interrupt
HSO_O_LDw
equ
HSO_O_Bigh
equ
(OOOOOOOOti)OR(MASK)
-; make bao.O low based on timerl
DO
»
interrupt
l'
....
C1I
N
(00100000b)OR(MASK)
; make MO.O hi based on timerl no interrupt
*******************************************************
set up storage
adudteoopO:
DSW
aducteapQ:
aductemp1:
top of buffer:
s.."ple=count:
DSW
DSW
»SW
DSB
Control_A2D:
DSB
DFora
170
172
173
174
PAGE
SOURCE STATBMI!NT
1; temp register for download calls
1; temp registers for conversiOD calls
1
1
1
1; the byte that controls the utility execution
aqu
3
COD_Dwn equ
4
5
; Convert/Download.
; Buffl/Bu1'fO# for conversions
6
; Linear/Paired'
BO_B1
171
0006
0080
02/18/86
equ
,
Lin Par aqu
Busy
'equ,
Sl..,ad/Unsi..,edI
; BuffO{Bu1'fl# for downloads
10000000B
; Bit 8
.eject
270189-58
II:S-98 MACRO ASsmmLBR
BRR LOC
A2D_BllITIlRIIICI_UTILITr
OBJECT
LIMB
175·
176
.oOOA
02/18/86
SBllp1e_Period:
DSII
177
178
179
PAGE
l
6
SOURCB STATBMBNT
1; the word thet specifies the n...er of clock Ucla!
;. that elapse between each s8llPle
PUBLIC Control_AD, SapIa_Period
180
181
182
183
184
185
0000
il
0000
0000
0002
0004
tl
>
2002
190
01
2002 ACOO
191
182
193
194
CO
186
187
188
189
0
C»
195
0
198
:I
..... ~
I
.".
0)
R
(')
::I.
.,CD
:u
0
c
5'
CD
'0
a
~
::::J
c:
CD
.B
0000
197
198
199
0SIiG
Dsw
1; ..... overlayable tellp registers
tap set srcJtr:WORD
deat..l'tr:
DSII
1
loop_count:
Dsw
I
orc..l'tr:
CSlIG
at
PUBLIC
A2D_DOMB_ Vector
DCII
A2D_DONB_Vector
l>
CSlIG
."
Load_IISO_C_d MACRO
202
203
204
205
206
~
PUBLIC A2D_BDFF_Util
200
201
200Zh
var
c.n
IIBcro to load IISO
LDB
bso_ _d , _
LD
bao_tiM,educte.pO
BIIDM
.eJect
270189-59
IICS-96 MACRO ASSBMBLIlR
BRR LOC
A2D_BUFFERING_UTILITY
OBJl!CT
0000
0000 3C0962
0003
0003 AlOOOOOO
0007 350904
r
l
~I..~
,
0)
~
(0
OOOA
OOOA AI000000
OOOB
OOOB AI000002
0012 814004
0016 3B091D
R
211
B
R
B
B
222
H
223
224
226
0018 180104
0
0018
001B A20000
0018 C20200
0021 65400002
R
R
0025 A20000
0028 C20200
0028 69400002
R
R
H
002F B004B9
H
..
..
<
ID
...
ID
...
:II
0
C
S'
ID
'0
0
R
0032 280D
0034 Fa
227
228
229
230
231
232
233
234
236
JBS
Download:
LD
JBC
Control_A2D, COD_Dwn, Convert
arc-ptr ••BUFFI_BASB
Control_A2D, DO_Bl.
I.n
arcJltr,.BWFO_BASB
Set Data Format:
-
j
LD
destJ>tr, 'DBST_BUFF_BASB
LDB
loop_count,'BUlF_LBNGTH
JBS
Control_AZD. LiD_Par,
PAlR8O: SRRB
loop_count,'l
Paired_Data_loop:
to
adudtellPO, [ercJ>trJ+
ST
adudtellPO. [deatJ>trJ
ADD
deat_ptr.'BUFF_LIlNGTH
The pal~ data routine uses 1/2
as aany loops as the unpaired
ST
SUB
adudtellPO. [srcJ>trJ+
adudte.pO. [dsat_ptrJ+
deat J>tr. tBUFF_LIlNGTH
Move odd word,
Loop until done
239
RET
R
246
247
248
249
250
I
N
to
loop_count, Paired_Oats_loop
003B BOO4F7
»
-a
Move even word
Length = , of warda = 1/2 , of bytes
Convert Data
244
245
Choose linear or paired
Linear_data_loop
D.JNZ
243
0038 2801
0040 Fa
Set_DBtB_Forwat
CALL
R
R
; Select convert or download
Download BUFFO:
237
238
0036
0035 A20000
0038 C20200
(
7
SOURCE STATBI!BNT
236
240
241
242
PAGB
A2D_BUFF_Util:
226
:>
II
212
213
214
216
216
217
218
219
220
221
R
R
0
C
0
::I
LINE
207
208
209
210
02/18/86
""
UI
-
Linear_Data_loop:
to
adudtellPO. [orcJ>trJ+
ST
adudtellPO. [deatJ>trJ+
D.JNZ
loop_count, Linear_Data_loop
CALL
Convert_Data
Move data linearly
Loop until done
RET
.eject
270189-60
1IlS-96
IIACJII)
BRR LOC
ASSDmr.n
A2D_BUFI'BIIllIO_UTILITY
OII.JBCT
0041
0041 1.1400004
0045 AlOOOOOO
..
t..
c:
1/1
S·
fQ
0
C
(")
a
1
'0049 A20000
004C 71COOO
004r 330909
a
a
a
0052
'0052 691D7FOO
0056 OADI00
00592003
a
a
0058
005B 010100
a
ODSI
OD5B C2OOO0
0061 1004115
a
a
0
'fJ ::s
~
U1
....
0
i..
:D
0
C
=t
::s
CD
'0
0
a
::I
c
CD
.s
0064 FO
0065
0065 F2
0066 91SOP9
R
0069 B13F08
oose 1.1000006
0070 Al80OOO4
a
1
1
0074 350908
0077 1.1000006
0078 1.1800004
a
1
B
LIlIB
251
252
253
254
255
256
257
258
259
250
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
02/18/86
PAllB
I
8
l
SOURCB STATBMBNT
Convert_Data:
LIl
IJl
Again:
l.D
AllDB
JBC
Biped_Reault:
SUB
' 'SIIRA
Ba
; Ccmvert tbe, data in tbe delltinatiOD buffer
lOGP_cOUDt,IBUFF_LBIIO'lII
8rC..ptr,'DIST_Burr_BASB
aduclti!lllpO, [arc..ptrj
aduclti!lllpO,'llooOooOb
CODtrol_A2D, Drora, .UnaiIlDe'CReault
aduclti!lllpO, t7feOR
aduclteapO,lShift_Count
Replace_S_le
lIII.illll...·CReault:
SRR
aduclta.pO, 'Shift_Count
Replace_S_le:
ST
DJIIZ
adudt-a, [8rc..ptrj+
loop_COUDt, Again
;. Loop until dODe
:r'V
RBT
I
II
;; Prepare to Start Convel'llions
Convert:
PDSRF
Control_A2D, #Buay
LIlB
LIl
LIl
s_le_COUDt,'BUFF_LIII«lTR - 1
top_ot_buffer,tBUFFO_BABI
aductlOlPl,.(BUFFO_BABB + 2*BUFF_LBIIO'lIII
JBC
ccmtro1_A2D, BO_Bl, start_Converaiona
top_of_buffer,.BUFFl_BABB
aduct_l,.(Burrl_BASI + 2*BUFF_LBIIO'lII}
LD
LD
.eJect
set converter busy bit
ORB
270189-61
I\)
......
U1
MCS-96 MACRO ASSBMBLBR
ERR LOC
A2D_BUFF!iRlNG_OTILITY
OBJIICT
LIlli!
007F
007F 61070900
B
0083 440AOA02
R
290
291
292
293
294
02/18/86
PAGE
(
9
SOURCE STATBMBNT
Start_Conversion.:
295
296
AIIDB
ad_COIIIIIIand, CODtro1_A2D, #00000111b
ADD
aductempO,CLOCK,S_le_Period
297
; load channel nmaber
atart first conversion
ODe 88llP1e tble fra.
now
298
299
303
C
~I
:J
OOBD CCOO
R
ca
!I
C
0095 81020200
R
0099 640AD2
R
(')
m
....
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00A2 C800
~
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.,
gi
..
5'
CD
(')
0
:::l
Sf::
(1)
.s
R
304 .
305
306
310
311
312
313
314
316
316
320
321
Load_BSO_COIIIIIIIDd Start_A2D
start A2D at Time=aducteoopO
POP
get a copy of the psw
t""'l'
Load_BSO_C_d BSO_O_higb
Bet hao.O high at coDveraion
start tille for external SIB
OR
t""'l',#202h
enable a2d interrupts
ADD
aduct""'l'O,Semp1e]eriod
Load_BSO~C_d Start_A2D
atart second cODvertion one
8_1e time frOll the first
322
POSR
put paw back on stack
323
324
Load_BSO_COIIIIIIIDd BSO_0_1ow
teIIP
»
l'
.....
c.n
N
; lower haa.O for external SIB
328
OOM Fa
OOAD Fa
329
330
331
POPF
RBT
.eject
270189-62
MCS-96 MACRO ASSl!MBLBft
IIRR LOC
A2D_BUFFBRIIIIUITILITY
OBJECT
OOAC
OOAC
OOAl: 1"2
C
III
s·
CQ
....
-~
0
c
01
341
342
343
D.JlIZ
IIICB
OOBC
OOBF
OOC1
OOC2
R
344
345
345
347
ClIP
880406
DI"26
F3
FO
OOC3
OOC3 640&02
OOC6880406
R
OOCF 3OOBOB
R
CD
'0
0
:::J
sc:
(1)
B
8TH
8TH
AllDB
ad_result_10, [top_of_bufferJ+
ad_result_hi, [top_of_bufferJ+
ad_.,...,..d,Contro1_A2D,lIO0000111b
; load cbmme1 n _
340
00D9 DFOC
OODB F3
0000 FO
..s·
lJ
0
c:
l
10
AID INTIIIlRIJPT /IOUTINII
PusRF
R
R
00D2
00D2 FD
CD
-
00B7 B00809
OOBA 1708
..
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A2D DONI Vector:
II
B
II
R
0
I\)
PAOB
SOURCB 8TATBMII/iT
CSBG
00&0 C60600
ooBO C60600
00B3 51070900
0
cp <:::J
CD
-""
LINII
332
333
334
335
336
337
338
339
02/18/86
348
349
350
351
352
353
357
358
359
360
361
BB
POPF
RBT
S-.ple_ACain:
&OD
ClIP
_ap1e_COUDt, 8ap1e_ApiD
• _ap1e_count
top_of_buffer,aduete.p1
Top_of_buffers
Check top of buffer
aduetellpQ,8asp1e_Period
top_of_buffer,aducte.p1
Set next • .-ple tiae
Check top of buffer
for later JIIIIP
Load_BSO_C_ Start_A2D
JBC
nop
LDad_SSO_C_ BSO_O_Low
366
0083 DF02
00B5 F3
00116 FO
00B7
00117 717F09
OOBA F3
oon FO
OOIC
ASSBMBLY COMPLBTBD,
R
367
DB
Top_of_buffers
368 .
POPF
369
HIT
370
371
Make ElSO hieb:
372
Load_BSO_C-d BSO_O_Rieb
376
377
DB
Top_of_buffers
POpr
378
379
HIT
380
381
Top_of:.buffera:
382
AllDB
Control_A2D,.IIOT(Buay)
383
POPF
384
HIT
385
~
...,
Make_lISO_1ow:
362
ooDD
~
'U
aasp1e_COUDt,O, _ _SSO_Rieb
en
wait 8 states after SSO' load
Lo8d
for chaD", of SSO to triccer SIR
Load for chaD", of BSO to triBBer SIR
Clear cODverter BUSY bit
I!Im
NO BIIROII(S) FOIINII.
270189-63
inter
AP-275
The listing contains a fairly complete description of
what the program does. The block by block operations
are shown below:
Lines 1-198 describe the program, declare the variables
and set up equates. Several of these variables are declared as overhl.yable, so the user needs to be careful if
using this module for other than the FFT program.
Lines 205-210 declare a macro which is used to load the
HSO unit. This will be used repeatedly through the
code.
Lines 212-253 determine whether a conversion or
download has been requested. If a download has been
requested, the data is downloaded to the destination
array as either paired or linear data. Paired data has
been described earlier.
Lines 255-278 contain a subroutine which converts the
destination array to either signed or unsigned numbers.
The numbers are also shifted right to provide the desired full-scale value as requested by SHIFT_
COUNT.
Lines 279-334 initialize the conversion routine. HSO.O
is toggled with the start of each routine so that an external sample and hold can be used. The instructions in
lines 308,316, and 326 have been interweaved with the
Load_HSO_Commands to provide the required 8
state delays between HSO loadings. If this was not
done, NOPs would have been needed. It is easier to
understand the code if these lines are thought of as
being gathered at line 326.
Lines 337-353 are the actual AID interrupt routine.
The AID results are placed BYTE by BYTE on the
buffer, the AID is reloaded, and then the number of
samples taken is compared to the number needed. Note
that the AID command register needs to be reloaded
even if the channel does not change. INCB on line 348
is used to insure that the DJNZ falls through on the
next pass (if sample_count is not reset).
Lines 355-396 complete the routine. The HSO is set up
to trigger the next conversion and provide the HSO.O
toggle for an external sample and hold. Once again, the
time between consecutive loads of the HSO is 8 states
minimum. Note that this section of code has been optimized for speed by reducing branches to an absolute
minimum and duplicating code where needed.
This concludes the description of the A to D buffer
module. In the FFT program, this module is run, then
the FFT transform module, then the plot module. This
allows variables to be overlaid, saving RAM space. The
time cost for this is not bad, considering the printer is
the limiting factor in these conversions. If more RAM
was provided, and the FFT was run with its data in
external RAM, this module could be run simultaneously with the other modules.
10.0 DATA PLOTTING MODULE
The plot module is relatively straight-forward, and is
shown in Listing 5. After the declarations, which include overlayable registers, an initialization routine is
listed. This separately called routine sets up the serial
port on the 8096 to talk to the printer. In this case, the
port has to be set for 300 baud.
A console out routine follows. This routine can also be
called by any program, but it is used only by the plot
routine in this example. The write to port 1 is used to
trace the program flow. The character to be output is
passed to this routine on the stack. This conforms to
PLM-96 requirements.
Since all stack operations on the 8096 are 16-bits wide,
a multiple character feature has been added to the console out routine. If the high byte it receives is non-zero,
the ASCII character in that byte is printed after the
character in the low byte. If the high byte has a value
between 128 and 255, the character in the low byte is
repeated the number of times indicated by the least significant 7 bits of the high byte.
The print decimal number routine is next. It is called
with two words on the stack. The first word is the unsigned value to be printed. The second byte contains
information on the number of places to be printed and
zero and blank suppression. This routine is not overflow-proof. The user must declare a sufficient number
of places to be printed for all possible numbers.
The DRAW.:-GRAPH routine provides the plot. It
first sends a series of carriage return, line feeds
(CRLFs) to clear the printer and provides a margin on
the paper. Each row is started with the row number, 2
spaces, and a "+". Asterisks are then plotted until
Number of asterisks> FFT Value I PLOT_RES
Recall that PLOT~ES is a variable set by the main
program. When the number of asterisks hits the desired
value, the value of the line is printed. If the Decibel
mode is selected, the line value is divided by 512 and
printed in integer + decimal part form, followed by
"dB". If the number of asterisks reaches PLOT_
MAX, no value is printed. The next line is then started.
A line with only a "!" is printed before the next plot
line to provide a more aesthetic display on the printer.
If a CRT was used, this extra line would probably not
be wanted.
6-153
MCS-96 MACHO ASS_LIllI
PLOT_SERIAL
02/18/86
l
PAGE
SBRIES-III MCS-96 MACHO ASSBMBLIIII, VI. 0
SOUlICB FILl: : F2: PLOTSP. A96
OBJECT rILl: :F2:PIDTSP.OIIJ'
COIlTROLS SPBCIFIEO IN INVOCATION C
~
01
.j:>.
I
..
0"
21
0
~I
SOUllCl! STATEMIIIIT
$pafe1ength(50)
PIDT_SBRIAL IIODDLB STACKSIZB (6)
Intel Corporation, Decaber 12, 1985
by Ira Rarden, NCO Applicati01lll
pro....,.
Tbi.
produces a plot OIl aerially coDDeeted printer. Tbe
....iDi tude of each of the 32 input va1_ i. plotted borizoDtally, with ODe
"!" followed. by a linef'eed between each plot line. Bach plot line start.
wit" a "+" and the eDtire plot begins with 3 liDe feeds and euda with a fora
feecl. Tbe values to be plotted are 32 UlllJigaed words b . .ed at the exteraally
defiDed poiDter PIDT_IN.
').'he routiDe INIT_ODTPOT IIWIt be nm to Bet up the Berial port when the
Byat... iB turned 00. CON_OUT caD be used by a pro....,. to output to the
aerial port. DJIAII_GRAPII i. the routine thet automatically p10ta the data.
Sizing of the graph
CBD
.
):.
"U
I\)
.....
crt
be doue USiD, PIDT_RES, which determiuea how lIIBDy
ait. are needed for each dot, and PLOT MAX, wbich i8 the IIl8XiJIuII value the
prograa will be paased. Note thet (PLDT_MAX/PIDT_RES) deriDes the """,illNlll
nUliber of eolUJIDS the routine will print.
24
0000
0000
0024
0024
0028
002C
0021
0030
0032
25
26
27
28
29
DBO
30
OSBO at 248
BXTRN
BXTRN
apt.p:
ioeI, baud_reg, .peon, 8~tat, abuf, portl
zero, ax, bx, ex, dx, Fn_MODI
1
deb
value:
31
32
del
del
divisor:
xptr:
yptr:
xval:
IOLvaI:
33
34
35
36
dew
dew
dew
dew
1
1
1
1
1
1
~37
0000
38
OSBO
39
40
41
$eJect
IIXTRN
PLOT_IN
?70189-64
NCS-96 MACRO ASSBMBLBR
ERR LOC
PLOT_SERIAL
OBJBCT
LINE
42
43
2500
44
45
2500
2500 812000
E
0270
!s·
CD
I;
q> "a
...... §:
01
01
iii:
o
a.
c
iii
g>
a
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c
CD
.s
0082
006r
46
47
48
49
50
51
52
53
54
55
56
57
58
69
2503 B16roo
2506 Bl8200
E
E
2509 B14900
2500 B12000
E
60
R
61
02/18/86
(
PAGE
SOIJIICB STATBMBNT
CSEG at 2500H
PIIOClRAM I«lDULB BEGINS
PUBLIC INIT_OUTPUT, CON_OUT, DRAICGRAP8
EITIiN
PLOT_RES, PLOT_RES_2, PLOT_MAX
INIT_OUTPUT:
1db
INITIALIZB SERIAL PORT
ioc1,'00100000B
set p2.0 to txd
baud_val
equ
624
Baud_bil/h
baud_low
equ
equ
«baud_va1-l)/256) OR BOH
(baud_va1-1) I«lD 256
1db
1db
baud_re" #baud_low
baud_re" #baud_hil/h
1db
1db
BpcOD,I01001001b
spblp,'00100000B
624=300 baud (at l2 MHz)
set for XTAL1 clock
enable reciver .ode 1
8et TI-t.p
62
250r FO
63
64
65
»
RET
."
I
'eject
270189-65
I\)
.....
en
II:S-96
iw:Ro
ERR LOC
riii"
C!:
:::I
C
t
::J"
CD
"1J
...
....cp i5"
(]I
m 3:
0
CL
C
CD
00
a
:::I
C
CD
oS
ASSBMBLBR
PLOT_SERIAL
OB.lBCT
2810
28100000
25120000
2814 31"0110
2817 9B00pl
251A DF17
E
E
E
B
2810 900000
251F 3500FA
252211D1"00
2825 900000
E
2528
282B
2828
2530
B
B
B
B
BOOOOO
BOOlOO
1101
1171"00
B
R
R
LIIIB
66
f/1
68
69
70
71
72
73
74
75
76
77
78
79
SO
81
82
83
84
85
86
87
88
89
90
91
92
93
02/18/86
PAGE
l
3
SOIJ!iCB STATBMIINT
CONSOLE OUT IIOUTI/IB
Call with a word parameter on stack. The low byte has tbe ~r
to be sent. If tbe hiib byte has a value betweeu 81R and 8F1!R, tbe
character 10 repeated 1 to 128 times reepective1y. ODe repeat ......,s
that the character will be printed 2 times. tf tbe high byte contains
a value bet_ 1 and 7FR, tbe charater represented by that value will
be printed after the character in tbe low byte. If the high byte
contains a value of zero only the low byte will be printed.
CON_OUT:
ax
ex contains the calling adress
If bit 7 is Bet print one character
cmpb
dx
dx+ 1,7, onechr
dxf-l,zero
Je
onechr
if highbyte=O print one character
sptJap.spstat
aptap, 5, twochr
sptap,#11011111b
zero, spstet
wait for TI
pop
pop
jbs
twochr: orb
Jbc
aodb
orb
Idb
1db
clrb
aodb
abuf,dx
dx,dx+l
dx+l
dx,#07FR"
clear TI-tap
remove possible false Tl
l>
'P
N
......
Load second character
C1I
clear count byte
.....k IISB
94
2833 1701
2535 1171"01
2838 -900000
2538 3500FA
2538 11DroO
2541 900000
B
B
2544 800000
2547 BOOlBB
254A B300
B
B
R
R
B
B
B
95
96
97
98
99
100
101
102
103
104
onechr: inch
aodb
orb
jbc
aodb
orb
wait!:
dx+l
dx+l,#7FR
Bptmp,spstat
wait for TI
sptmp,5,waitl
sptap,#IlOlll11b
zero, spatet.
clear TI-tap
Il.JN2
sbuf,dx
dx+l,waitl
BR
[ax)
ldb
~ve
possible falae TI
Effectively a RBT
105
106
$eject
270189-66
MCS-96 MACRO ASSI!IIBLBR
JlRR LOC
C
(R
=:
::J
CD
I
::J'
CD
'tI
....., 0'
...
0)
01
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0
a.
C
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'0
0
PLOT_SERIAL
OBJECT
254C
2540 CCOO
254B CCOO
2550 ACOlOO
2553 ASOO962528
2558 CC24
255A
255A 0126
255C 8C2B24
255F 380017
2562980024
2565 D70F
2567
2567 310003
256A 38280C
2560 3AOO15
2570 AlFOOO24
2574 2003
LINE
107
108
109
E
B
E
E
E
B
B
B
::J
!:!:
::J
c
(1)
.s
2576910100
2579 65300024
257D 6l7FOO24
2581 C824
2583 2F8B
2585 A02624
2588 OlU
25& BDOA0028
2588 880028
2591 D7C7
2593
2593 B300
2596
2596 00OOO1000A006400
02/18/86
E
B
110
III
112
113
114
115
116
117
118
119
120
121
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123
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125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
B
PRINT
Call with two words
The second hu JIOde
MODE:
000
001
010
!xx
DECIMAL II1IIBER
ROUTINI!
on stack. The first is the value to be printed..
luf01"ll8.tioo in the low byte.
= supre.. all zeros
= priot all nUlllbara
= supreaa all zeros except righmost
= do not print leading blanks
The bigb byte of tha 2nd word = 2x tha nUllber of places to be printed
PRINT_IIIII:
POP
POP
Idbze
ld
pop
diY_loop:
ell'
diw
jbs
Send Decimal number to CON_OUT
ex
bx
bx i8 mode byte. bx+l ia diviaor pointer
dx,bx+l
divisor, di vtab [dx]
value
capb
value+2
value,divisor
bx,O,chr_ok
value, zero
jne
DOD_O
Val_O:
jbe
jba
protap: jba
ld
br
bx.I,prntsp
divisor, O. cbr_ok
bx.2 , CODt
0: orb
chr=ok: add
and
pusb
bx,4I000lB
value,t30b
va!ue.#71'h
DOD
value.#OFOR
145
146
147
ClIP
joe
div clone:
br
DIVTAB:
dew
; Jump if value
I\)
is non zero
-...I
UI
Value is zero
i Print space instead of 0
; If io rtghtmoat posi tioo print 0
Do DOt print apace if bit is set
OFOht30b = 20R = apace
; Set flag ao O's will be printed
; 30b+n=Ot09eaeii
send least 8i, seven bits. clear upper word
value
COD_out
value. value+2
coot:
.
»
'tI
divide ax,dx by divisor
print character regardless of value
chr_ok
Id
ell'
diw
150
151
152
153
(
4
SOllRCE STATI!IIBNT
call
148
149
PAGE
diviaor+2
divisor.IIO
divisor. zero
diY_loop
output ascii result (reault(9)
load value w1 tb r.ainder
next lower power of ten
[ex]
•
~er o'f' places for result
0, I, 10, 100, 1000, 10000
; divioor table - 10_
270189-67
_.
":S-96 MACIiIl ASSI!MBLIIR
BRR
r.oc:
25A2
25A2
25M
25A7
25M
25AC
!:
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:::.
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....., 0"
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OBJIICT
C90DOO
2F69
C90A82
2f64
C90000
25AI'
usr
25Bl
2583
25B5
2585
2588
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25BD
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0
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6500002B
8900002B
DlBA
204r
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B
LINE
154
155
158
157
158
159
160
161
162
163
164
165
166
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02/18/86
PAGII
I
5
t
SOtIRCB STATI!IIBliT
DIWUlIIAPII:
push
; Graph
IOcIh
call
COD_out
pUah
t820AB
CON_OUT
100
CON_out
call
push
call
clr
IIXT_ _: clr
puah
call
push
call
.. ,
Clear 3 U .....
xptr
"",,1
IOAODB
OOICOllT
toOB
CON_OUT
CIILl
au1
xval
push
push
'(OAOOR- or 001Ob)
call
PIIIIIT_NtII
push
pU8h
12020B
OO'COUT
t2BB
call
COD_out
1d
yptr,.PLOT_DS_2
call
-iDa routine
»
; auPres8 all zerOs except right:.o.t
."
II
PriDt 2 apac:ea
; +
1IlIi'_OOL:
PL01'_DS_2 = PLOT_DS/2
PLOT_US ia defiDed 7 liDes dowo
/!eXt coi_
cwp
yptr,PLOT_IN[xptr]
Jh
PRT_NtII
pU8h
12AB
OON_Oor
PRT_M1t:
; Pruit Mark
call
I!IC_CIIT:
add
cwp
JDh
br
.eject
yptr,IPLOT_DS
yptr,'PLOT_MAX
met_col
PLOT_US
PLOT_lUX
= D......... of iDputa per output poiDt
= 1IIIX!aD line leocth
IIlIrLN
270189-68
•
.....
CII
N
_.
IIlS-96 MACI!O ASSBMBLBR
BRH LOC
OIl.JBCT
258C
258C 8900002B
2510 D149
25F2 C92020
25r5 2Fl9
251'73BOOOB
C
UI
5"
CC
c.n
~
::r
2605
2605 A32DOOO02B
260A 08012B
260D AC2FOO
B
B
B
B
8
C
2610 B02B01
2611 1100
B
00
2621 6OB60300
2625370102
26280700
"tI
-
..... 0'
01
<0 s:::
I
CB2DOOOO
C9ODOA
2F49
2036
8
2610 C800
2612 C9020A
261521'35
2617 C92BOD
261A 2BF4
II)
0)
25FA
25FA
25rB
2601
2603
PLOT_SERIAL
0
Q,
iD
:::l
g.
C
(1)
.s
262A C800
262C C90106
262F 2FlB
2631 092000
2634 2BDA
2636096442
26392BD5
B
B
B
B
B
LINE
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
02/18/86
PAGE
I
6
t
SOURCB STATBMBNT
PNT_NlII:
If value is l~B then miD:bnDD needed
for a plot. do not print value
cmp
yptr,.PLOT_HBS_2
be
NXTLN
push
call
JBS
.2020R
con out
FFT)IODB,3,db_lDOde
print 2 .paces then value
nOnl_JIOde:
pusb
push
call
BR
PLOT_IN[xptrJ
'(OMOR or OOOOB)
1d
8M
yptr,p10t_in[xptrj
yptr,'l
Idbze
ax.yptr+l
push
push
call
push
ax
'(OMOR or 0010B)
PRINT_NlII
tZBR
call
COD_out
Idb
clrb
ax+l,yptr
ax
high byte of ax = fractional portion of
10LOG(x)
...lu
Jbc
inc
ax.#3B6B
ax+l. 7. Do_rod
dx
round value up
supreas all zeros
~~_NlM
db_aode:
no_rod: push
push
call
push
call
push
call
PLOT_IN = 512*10*LOO(x)
yptr=265
10LOG(x)
ax= 10LOO(x) = yptr/256
*
Print AX
aupreaB all but rightJloat zero
'1J
II
if ax=FFOOR then ax+2 now = 998 decilllal
dx
; dx=ax+2
'(600R or OOOlB)
Print_nB
tZOR
.pace
con out
t4264s
"dB"
.
l>
Decimal point
print all nUlllbera to three places
COD_out
.eject
270189-69
...,
II)
UI
K:S-96 MACRO ASS_LBR
ERR toe
OBJIICT
2638 C90DOA
2631 2BD0
2640 C90000
26432BCB
2645 C92086
2648 21CS
2641. C92100
264D 2IC1
Ii
=
:J
Q
r
'"4
2650 C9000A
2660 2IAI
2662 C9000C
:r
-
2667 FO
2668
GI
0
0730
6502002C
893II002C
02022758
2665 211.9
"
'f' 0.....
Ol
264F
2651
2655
2659
~
0
a.
c
iD
00
:J
g.
c:
EMO
"a
I
NO I!RROR(S) FOUNO.
270189-70
....,
....,
UI
Ap·275
At the end of the plot, a form feed is given to set the
printer up for the next graph. Our printer would frequently miss the character after a CRLF. To solve this
problem, a null (ASCII 0) is sent after every CRLF to
make sure the printer is ready for the next line. This
has been found to be a problem with many devices running at close to their maximum capacity, and the nulls
work well to solve it.
The program modules are set up to run one-at-a-time so
that the code would'be easy to understand. Additionally, the Plot routine takes so long relative to the other
sections, that it doesn't pay to try to overlap code sections. If this code were to be converted to run a process
instead of print a graph, it might be worthwhile to run
the 'FFT and the AID routines at the same time.
If the goal of a modified program is to have the highest
With the plot completed, the program begins to run
again by taking another set of A to D samples.
11.0 USING THE FFT PROGRAM
The. program can be used with either real or tabled
data. If real data is used, the signal is applied to analog
channel 1. The program as written performs AID samples at 100 microsecond intervals, collecting the 64
samples in 6.4 milliseconds. This sets the sampling window frequency at 156 Hz. If tabled data is used, 64
words of data should be placed in the location pointed
to by DATAO in the TABLE_LOAQ routine of the
Main Module.
Program control is specified by FFT_MODE which is
loaded in the main module. Also within the main module are settings which control the A to D buffer routine
and the Plot routine. The intention was to have only
one module to change and recompile to vary parame. ters in the entire program.
frequency sampling possible, it might be desirable to
streamline the AID section and run it without interruption. When the A to D routine was complete the
FFT routine could be started. The reasoning behind
this is that at the fastest AID speeds the processor will
be almost completely tied up processing the AID information and storing it away. Using an interrupt based
AID routine would slow things down.
A set of programs which will perform a FFT has been
presented in this application note. These programs are
available from the INSITE users library as program
CA-26. More importantly, dozens of programing examples have been made available, making it easier to get
started with the 8096. Examples of how to use the hardware on the 8096 have already appeared in AP-248,
"Using The 8096". These two applications notes form a
good base for the understanding of MCS-96 microcontroller based design.
6-161
inter
AP-275
12.0 APPENDIX A • MATRICES
Matrices are a convenient way to express groups of
equations. Consider the complex discrete Fourier
Transform in equation 9, with N = 4.
:j
Yn
=
I
X(k) wnk
n
X(O)
= 0, 1, 2, 3
X(1)
+ X(2) WO
+ X(3) WO
+ X(2) W3
+ X(3) W2
requiring 4 complex multiplications
& 4 complex additions
Noting that WO = - W2, 2 of the complex multiplications can be eliminated, with the following results
+ X(1) WO + X(2) WO +' X(3) WO
+ X(1) W1 + X(2) W2 + X(3) W3
+ X(1) W2 + X(2) W4 + X(3) W6
X(O) Wo + X(1) W3 + X(2) W6 + X(3) W9
= X(O) wo
= X(O) Wo
= X(O) Wo
=
X(O)
X(1)
k=O
This can be expanded to
Y(O)
Y(1)
Y(2)
. Y(3)
Multiplying the two rightmost matrices results in
X(O)
X(1)
+ X(2) WO
+ X(3) WO
X(O) - X(2) WO
X(1) - X(3) WO
requiring 2 complex multiplications
and 4 complex addi1ions
In matrix notation, this is shown as
[
.
Y(O)
Y(1)
Y(2)
Y(3)
1
[WO
wo
wo
wo
_
-
wo
W1
W2
W3
wo
W2
W4
W6
wo
W3
W6
W9
1[ 1
X(O)
X(1)
X(2)
X(3)
The first step to simplifying this is to reduce the center
matrix. Recalling that
WN = WNMODN and WO = 1
[ ] [i
1
1
1
W1 W2 W3
W2 wo W2
W3 W2 W1
][
In general, the FFT requires
N' EXPONENT
X(O)
X(1)
X(2)
X(3)
2
1
Y(O)
Y(2)
Y(1)
Y(3)
1[
_
-
WO
11 W2
0 0
0 0
0
0 00
1 W1
1 W3
1[
01
1
0
complex multiplications
and
N • EXPONENT complex additions
where
The square matrix can be factored into
[
Y(O) = (X(O) + X(2) WO) + WO (X(O) + ~(3) WO)
Y(2) = (X(O) + X(2) WO) - WO (X(1) + X(3) WO)
Y(1) = (X(O) - X(2) WO) + W1 (X(1) - X(3) WO)
Y(3) = (X(O) - X(2) WO) - W1 (X(1) - X(3) WO)
The number of complex multiplications required is 4, as
compared with 16 for the unfactored matrix.
The matrix can be reduced to have less non-trivial multiplications.
Y(O)
Y(1)
Y(2)
Y(3)
Since Wi = - W3, a similar result occurs when ,this'
vector is multiplied by the remaining square matrix.
The resulting equations are:
0
0
1 WO
0 WO
'1 [ X(O)
X(1)
0 W2 0
1 0 W2
X(2)
X(3)
1
EXPONENT
= LOg2 N
A standard.Fourier Transform requires
N2 complex multiplications
and
N(N -1) complex additions
For this equation to work, the Y(J) and Y(2) terms
need to be swapped, as shown above. This procedure is
a Bit Reversal, as described in the text.
6-162
inter
AP-275
13.0 APPENDIX B - PLOTS
The following plots are examples of output from the
FFT program. These plots were generated using tabled
data, but very similar plots have also been made using
the analog input module. Typically, a plot made using
the analog input module will not show quite as much
power at each frequency and will show a positive value
for the DC component. This is because it is difficult to
get exactly a full-scale analog input with no DC offset.
Plot 1 is a Magnitude plot of a square wave of period
NT.
Plot 2 is the same data plotted in dB. Note how the dB
plot enhances the difference in the small signal values at the high frequencies.
Plot 3 shows the windowed version of this data. Note,
that the widening of the bins due to windowing
shows energy in the even harmonics that is not
actually present. For data of this type a different
window other than Hanning would normally be
used. Many window types are available, the selection of which can be determined by the type of
data to be plotted.3
Plot 4 shows a sine wave of period NT17 or frequency 7/NT.
Plot S shows the same input with windowing. Note the
signal shown in bins 6 and 8.
Plot 6 shows a sine wave of period NT/7.S. Note the
noise caused by the discontinuity as discussed earlier.
Plot 7 uses windowing on the data used for plot 6. Note
the cleaner appearance.
Plot 8 shows a sine wave input of magnitude 0.707 and
period NT/7.S.
Plot 9 shows same input with windowing.
Plot 10 shows a sine wave of magnitude 0.707/16 and
period NT/ll.
Plot 11 shows the same input with windowing. Note
that there is no power shown in bins 10 and 12.
This is because at 6 dB down from 3 dB they are
nearly equal to zero.
Plot 12 uses the sum of the signals for plots 8 and 10 as
inputs. Note that the component at period NT/II
is almost hidden.
Plot 13 uses the same signal as plot 12 but applies windowing. Now the period component at NT/II can
easily be seen. The Hanning window workS well in
this case to separate the signal from the leakage. If
the signals were closer together the Hanning window may not have worked and another window
may have been needed.
6-163
AP-275
o
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
+
!**********************************************************~***********************
I
.
t**********,*****************
+I
.;.****************
!
20868
6978·
4214
!............ 3038
1••••••••• 2394
!! ........
I
!
1991
+
!*******
!
t
.;.******
!
1718
1524
+
!.....
I
1381
+I
...I *****
1274
!.....
1192
20 +
21
I
22 +
23 !****
I .
24 +
25
!
26 +
27
I
28 +
29
!
30 +
!....
1086
!....
1054
!....
1033
31
!....
1024
!
1131
- 270189-20
Plot 1-Magnltude Plot of Squarewave
6-164
AP-275
o
2
3
4
+
!****************************************************************************
I
--*-
+
!.....................................................
I
38.222 dB
28.706 dB
1************************************************.
24.327 dB
I
+
1******************************************21.487 dB
8
9
10
11
12
13
14
15
16
I
!.......................................
!....................................
17.815 dB
1
+
!.................................
16.538 dB
!
+
I
+*******************************
I
+
!**,***************************
I
IB +
17
!............................
19
20
21
1•••••••••••••••••••••••••••
22
23
+
!
+**************************
24
25
26
27
28
29
30
31
19.421 dB
1
+
I
!
!
+
15.499 dB
14.639 dB
13.940 dB
13.363 dB
12.908 dB
!.........................
12.554 dB
!.........................
12.296 dB
1
!
+
!************************
!
+
!........................
!
12.125 dB
12.043 dB
270189-21
Plot 2-Decibel Plot of Squarewave
6-165
intJ
AP-275
o
+************
6.105 dB
!****************************************************************
32.203 dB
2 !*********************************************************
28.678 dB
22.690 dB
3 !*********************************************
4 !******************************************
20.760 dB
5 !*************************************
18.308 dB
16.990 dB
6 !**********************************
7 !*******************************
15.460 dB
14.476 dB
8 1*****************************
9 !***************************
13.398 dB
10 !*************************
12.620 dB
11 1************************
11.795 dB
12 1**********************
11.175 dB
13 1*********************
10.507 dB
10.000 dB
14 1********************
15 !*******************
9.464 dB
9.039 dB
16 !******************
8.616 dB
17 !*****************
18 !*****************
8.281 dB
7.916 dB
19 !****************
20 !***.******.****
7.628 dB
21 !***************
7.347 dB
22 !**********.***
7.121 dB
23 !**************
6.889 dB
24 !*************
6.706 dB
25 !*************
6.542 dB
26 !*************
6.409 dB
27.!*************
6.265 dB
!************
6.191 dB
29 !************
6.094 dB
!
30 +************
6.082 dB
31 !***********1r
6.031 dB
I
!
270189-22
Plot.3-Plot of Squarewave with Window
6-166
intJ
o
AP-275
+
I
1 +
I
2 +
!
3 +
4
6
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
!
+
I
+
!
+
!.....................................................*.*****************
I
+
I
+
!
+
I
+
!
+
I
+
!
+
!
+
!
+
!
+
!
+
!
+
!
+
!
r+
!
I
+
+
!
+
I
+
!
I
27
+
28
29
r
I
r+
30
31
36.121 dB
+
I
270189-23
Plot 4-Sin (7.0X) without Window
6-167
inter
AP-275
o
+
!
+
!
2 +
I
3 +
I
4 +
!
5 +
6
7
8
9
!.**••••• * ••••• *** ••••• * •• ** •••• ** •••••••••••••• *
24 078 dB
!.. ** •• *•• *•• * •••••••••••• *••••• *.*.*••• *.*•••••••••••••:*•• *
I
+
II
+
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
'
30.101 dB
24.078 dB
!
I
10
12
13
-
+************************************************
I
+
I
+
!
+
!
+
I
+
!
+
!
!
+
!
+
!
+
!
+
!
+
!
+
i
+
!
+
!
+
!
+
I
+
!
t
t+
!
270189-24
Plot 5-5ln (7.0X) with Window
6-168
Ap·275
o
2
3
4
S
+*****************************
14.265 dB
14.444 dB
!..........* ••*...............
14.943 dB
!******************************
!................................
!********~**************************
15.865 dB
!.......................................
17.308 dB
19.569 dB
6
!***********************************************
23.421 dB
!****************************************************************.
8
+****************************************************************
I
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
.
!********************************************
32.441 dB
31. 971 dB
22.012 dB
!******************************-****
17.199 dB
13.943 dB
11.472 dB
9.483 dB
!............................
!.......................
!..... ** ....*.......
!................
7.819 dB
!.............
6.402 dB
!..........
5.164 dB
!........
4.090 dB
!......
3.152 dB
!*....
!! ..*
+..
i*!
2.308 dB
1.546 dB
0.901 dB
0.300 dB
+
!
+
!
+
I
+
!
+
I
+
I
t
t
+
I
270189-25
Plot &-Sin (7.5X) without Window
6-169
AP-275
o
+
I
+
!
2 +
I
3 +
I
4 +
I
5 +
14.706 dB
6 !*****************************
••
7 !*****************************************************
I
.
8 t*****·*********~*****·**·******·***·***·**~*****··~** ***.
14.694 dB
9 +*.************** •• ***********
!
10 +
*-
11
12
13
14
15
16
17
IB
19
20
21
22
23
24
25
26
27
28
29
30
31
28.671 dB
28.678 dB
!
t
+
I
+
I
+
!
+
I
+
I
+
I
+
I
+
I
+
!
t
+
I
+
I
+
!
+
I
+
!
+
I
+
I
t
t
t
270189-26
Plot 7-5ln (7.5X) with Window
6-170
AP-275
o
2
3
4
5
6
7
8
9
10
11
+**********************
!***********************
1........................
1**************************
11.242 dB
11.417 dB
11.936 dB
l.............................
12.846 dB
14.296 dB
1*********************************
16 . 561 dB
I
+******************** •• *******************
2~.409 dB
I
+************************ •• *********************************
1**********************************************************
I
.
+**************************************
18.994 dB
I
.
+********.*******************
14.187 dB
10.936 dB
8.472 dB
29.425 dB
28.959 dB
l......................
l.................
12
13 !*******.*****
6.468 dB
14 !****.*****
4.819 dB
3.382 dB
15 !*******
16 .!****
2.152 dB
I
17 +**
1.082 dB
!
18 +
!
19 +
I
20 +
!
21 +
!
22
23 +
!
24 +
!
25 +
I
26 +
I
27
28
29 +
r
r
r
30
31
I
+
I
+
I
270189-27
Plot 8-0.707;' Sin (7.5X) without Window
6-171
intJ
o
2
AP-275
+
I
+I
+
I
3
4
5
6
!********...............
8
!~**************************************************
I
9
.***********************
t
+
I
+
11.694 dB
7 !**************************************.*************
10
11
12
13
14
15
16
17
18
I
25.663 dB
25.667 dB
11.674 dB
t
+
I
+
I
+
I
t
+
!
I
+
t
+
I
19 +
I
20 +
I
21 +
!
22 +
I
23 +
I
24 +
!
2S +
I
26 +
!
27 +
!
28
t
29
30
31
t
t
r
270189-28
Plot 9-0.707 • Sin (7.5X) with Window
6-172
AP-275
o
+
1
+
1
+
I
4
5
+
!
+
1
+
1
+
1
+
I
8
t
+
10
11
12
13
I
+
1
+******************
I
9.031 dB
t
+
1
14.
15 +
1
16
17 +
1
18 +
1
19 +I
20 .j.
1
21 +
I
22 +
1
23 +
I·
24 +
1
25 +
1
26 +
I
27
28 +
1
29
r
t
t
t
30
31
t
t
270189-29
Plot 10-0.707/16. Sin (11X) without Window
6-173
AP-275
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
+
I
+
I
+
I
+
I
+
I
+
I
+
I
+
I
+
I
+
I
+
!... *••
I
+
I
+
I
+
I
+
I
+
!
+
!
+
!
+
!
+
I
+
I
+
!
+
I
+
!
+
!
+
I
+
!
+
!
+
I
+
I
+
I
3.008 dB
270189-30
" Plot 11-0.707/16 • Sin (11 X) with Window
6-174
AP-275
o
2
3
4
5
6
7
8
9
10
11
12
13
+**********************
11.242 dB
!***********************
11.425 dB
1************************
11.936 dB
1**************************
12.846 dB
!*****************************
14.296 dB
1*********************************
16.561 dB
1*****************************************
20.409 dB
1***********************************************************
1**********************************************************
1**************************************
19.000 dB
1****************************
14.187 dB
1**************************
13.105 dB
1*****************
8.472 dB
!*************
6.483 dB
14
15
16
1**********
18
t
29.425 dB
28.959 dB
4.819 dB
!*******
3.382 dB
!****
2.152 dB
!
17 +**
1.082 dB
19
!
r
20 +
!
21 +
I
22 +
I
23
24
25 +
!
26 +
!
27 +
!
28 +
I
29 +
r
r
30
31
I
t
t
270189-31
Plot 12-0.707 (Sin (7.5X)
+ 1/,6 Sin (11X» without Window
6-175
Ap·275
o
r
2
+
I
+
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
+
!
I
r+
!***********************
11.702 dB
I
.***************************************************
!***************************************************
11.674 dB
!***********************
!
+
!......
I
25.663 dB
25.667 dB
3,074 dB
+
!
+
!
+
!
r+
I
+
!
+
I
+
!
+
I
+
!
+
!
+
!
+
I
+
!
+
I
+
I
+
I
+
!
+
I
+
I
270189-32
Plot 13--0.707 (Sin (7.5X)
+ 1J.. Sin (11X» with Window
6-176
AP-275
BIBLIOGRAPHY
INTEL PUBLICATIONS
1. Boyet, Howard and Katz, Ron, The 16-Bit 8096:
Programming, Interfacing, Applications. 1985, Microprocessor Training Inc., New York, NY.
2. Brigham, E. Oran, The Fast Fourier Transform.
1974, Prentice-Hall, Inc., Englewood Cliffs, New
Jersey.
3. Harris, Fredric J., On the use of Windows for Harmonic Analysis with the Discrete Fourier Transform. Proceedings of the IEEE, Vol. 66, No.1, January 1978.
4. Weaver, H. Joseph, Applications of discrete and
continuous Fourier analysis. 1983, John Wiley. and
Sons, New York.
1. 1986 Microcontroller Handbook, Order Number
210918-004
2. Using the 8096, AP-248, Order Number 270061-001
3. MCS-96 Macro Assembler User's Guide, Order
Number 122048-001
4. MCS-96 Utilities User's Guide, Order Number
122049-001
6-177
inter
APPLICATION
AB-32
BRIEF
December 1987
Upgrade Path from 8096-90 to
8096BH to 80C196
Order Number: 270521-001
@ Intel Corporation, 1987
6-178
inter
AB·32
Converting applications that use'an 8X9X-90 to use an
8X9XBH requires consideration of a few of the BH
enhancements. Descriptions of each of the differences
between the -90 and the BH follow, along with a discussion of the implications of the change.
BHE and INST are latched: The bus control signals
BHE and INST are valid throughout the bus cycle on
8X9XBH devices. ON -90 devices, these signals need to
be latched on the falling edge of ALE.
Byte Read following RESET rising: The bus control
and bus width 'options of 8X9XBH devices are selected
by configuration of the chip immediately following the
rising edge of RESET. During the usual 10 state reset
sequence, BH parts will perform a byte read of location
20l8H to acquire configuration information prior to
fetching the first opcode at location 2080H. The 8X9X90 does not perform this read.
ALE is high while in reset: The ALE/ADV pin of the
8X9XBH is driven high while the RESET pin is held
low. On -90 devices, ALE is driven low while in RESET. Circuits which rely on the state of ALE while
RESET is low must be modified. The reset state of
ALE was changed to enable implementation of the
Chip Configuration Byte read from external memory
'
following the rising edge of RESET.
EA is latched on RESET rising: The 8X9XBH latches
the value of EA on the rising edge of RESET. On -90
devices, EA was not latched and could be changed
without placing the part in'RESET. This change was
necessary to enhance ROM/EPROM security: Circuits
that rely on EA not being latched must be modified.
AID speed increased: The 8X95BH and 8X97BH AID
converters complete conversion in 88 state times. On 90 devices with AID converters, a conversion takes 168
state times. This translates in an increased conversion
speed from 42J-Ls on -90 parts to 22J-Ls on BH parts
running at 12MHz. Software that relies upon the speed
of conversion for timing must be changed. It is also
recommended that MCS-96 software be written so as to
not be impacted by further changes in AID conversion
speed.
Sample/Hold on A/D: The 8X95BH and 8X97BH
have a sample/hold on the input of the AID converter.
8X9X-90 devices with A/D converters do not have
sample/hold circuitry. External analog circuitry which
also includes a samplelhold must provide a settled analog input within the first four state times of 8X9XBH
conversion.
Duplicate Fetches: The 8X9XBH bus controller was
made more aggressive when it comes to instruction
fetches in order to minimize the execution speed degra-
dation of using an 8-bit bus. As a result, instruction
fetches over a l6-bit bus sometimes occur when there is
no space in the prefetch queue to store the fetched opcodes. This requires another instruction fetch from the
same address when space in the prefetch queue opens
up.
To the external system, these occurrences appear as duplicate instruction fetches. An estimated 10 percent of
all instruction fetches will be "duplicates", while overall bus loading will be approximately 65 to 70 percent,
compared to an 8X9X-90 bus loading of-approximately
55 to 60 percent. Execution speed is not impacted by a
duplicate fetch.
Write Pulse Width: The 8X9XBH l6-bit bus write
pulse width is one Tosc longer than on the 8X9X-90,
thus allowing slower memories and peripherals to be
used. In order to widen the WR pulse width, the time
between the end of WR and the next ALE was reduced
by Tosc. Note that the signals WRL, WRH, and WR
with an 8-bit bus are still the same width as on -90
parts.
Vpp Replaces VBB: Vpp is the programming pin for
EPROM devices. Systems that have this connected
through a capacitor to ANGND (required on 8X9X-90
parts) do not need to change. ANGND must be held
nominally at the same potential as VSS, and Vpp must
NOT be connected to Vee. High voltage must NEVER
be placed on the Vpp pin of a ROM device.
While there is almost no reason to do so, an application
should not attempt to execute with the EA pin at logic
zero and Vee at 5.5 Voe on an 879XBH EPROM
device. Additionally, the design should always begin
the "out of RESET" code execution from the internal
EPROM, immediately after the power-on sequence.
Reserved location warning: Intel reserved addresses can
not be used by applications which use 8X9XBH internal ROM/EPROM. The data read from a reserved location is not guaranteed, and a write to any reserved
location could cause unpredictable results. When attempting to program Intel Reserved addresses, the data
must be OFFFFH to ensure a harmless result.
Intel Reserved locations, when mapped to external
memory, must be filled with OFFFFH to ensure compatibility with future parts.
A positive transition on NMI: The 8X9XBH does not
clear the Watchdog Timer. The 8X9X-90 does clear the
WDT on a positive transition of NMI, and both part
vector to, external address OOOOH.
The following is the latest information on upgrading a
NMOS 8096 to a CHMOS 80C196.
6-179
inter
AB-32
The chip which is the CHMOS 8096BH replacement is
designated the 80C196. The part can be configured to
be pin compatible with the 8096, but because of the
process change and other enhancements, it may not be
plug compatible in some designs. This is to say that you
will not be able to arbitrarily swap out a NMOS 8096
and replace it with the 80C196. However, if a few rules
are followed the changes required will be almost painless.
80C196 OVERVIEW
First, some background on the 80C196 is needed. The
opcode set is a: true superset of the 8096, but some enhancements have been made to the peripherals and timings. The crystal is divided by 2 on the 80C196, instead
of 3, as on the 8096. This means that the 8OC196 running at 8 MHz will have a 250 ns state time, Just like an
8096 running at 12 MHz.
An 8OC196 running at 8 MHz will emulate an 8096 at
12 MHz except that some of the instructions and peripherals will operate faster. The instructions which
will be speeded up include mul, div, interrupt, call, ret,
and jumps. The serial port will require a different baud
value and the A to D may not run at exactly the same
speed. This means that timing loops which measure instruction speed or A to D completion speed may have
to be modified. The bus timings, while not nanosecond
for nanosecond compatible, will work in most systems.
DESIGN GUIDELINES
1. Do not use undefined register areas for storage or
depend on them to return a specific value if it is not
stated in the Embedded Controller. Undefined registers and locations on this, or any other, part should
be considered off-limits and reserved for development systems, testing or future use.
2. Do not base timings loops on instruction execution
times, as some instructions may execute faster on the
80C.l96 than on the 8096, even when the 80CI96 is
slowed down to 8 MHz, its 8096 compatible rate.
Counter-type loops should be initialized with values
that can easily be changed at compile ti~e.
3. Do not base critical timings on interrupt responses,
A to D completions, flag settings, etc. This is for the
same reason as above; some of these responses may
be slightly different from those on the 8096. Timer 1
is provided for critical timings. With an 8 MHz crystal, it will increment every 2 microseconds, just as an
8096 running lit 12 MHz.
4. The serial port baud register values should be easily
changeable at compile time. Since the serial port is
now capable of running at a higher frequency, a different baud rate value will be needed.
5. The circuitry interfacing to the chip should be capable of interfacing to the 80C196. The I/O lines on
8OC196 will look a lot like those on the 8OC51.
6. The BHE/WRH signal in eight bit and write strobe
mode will go low for odd ~ transfers and high for
even byte transfers. The WR/WRL signal will go
low for odd byte transfers and high for even byte
transfers. Normally, the WR/WRL signal should go
low for odd and even byte trimsfers since transfers
are on the low byte of the data bus.
7. PUSH and POP operations addressed relative to the
stack pointer work differently on the 80C196 than on
the 8096. On the 8096, the address is calculated
based on the un-updated stack pointer value, on the
80C196, the address is calculated based on the updated value. The only operations effected are: PUSH .
xx [sp), PUSH [sp) , PUSH sp, POP xx [sp) , POP
[sp), POP sp.
8. The VPD pin on the 8X9X parts is now the CDE
(Clock Detect Enable) pin on the 8OC196. When tied
high, CDE enables a clock speed sensor and will reset the part if the Xtall frequency drops below a few
hundred KHz. While this is perfect for most production boardS, it may be desirable to have a jumper
option on this function for evaluation boards.
6-180
inter
APPLICATION
BRIEF
AB-33
December 1987
Memory Expansion for the 8096
DOUG YODER
ECO APPLICATIONS ENGINEER
@ Intel Corporation, 1987
Order Number: 270522-001
6-181
inter
AB-33
This Application Brief presents two examples of a paging scheme for the 8096, allowing either 256K bytes of
total memory, or 544K bytes of total memory. Both
systems utilize PORTI as the output for the upper address lines. Because Interrupt vectors, and other critical
sections of code must always be present, addresses
0-7FFFH always refer to the same main page. The
PORTI upper addresses only affect addresses 8000FFFFH, by slapping several 32K pages in and out.
amount of ROM and RAM was picked arbitrarily, and
could be reconfigured in various ways, however, this
may require slight modifications or additions to the decoder circuitry. This setup has a main page at addresses
0-7FFFH, and upper pages 1-7 at addresses 8000FFFFH. Note that upper page 0 is the same as the
main page. The WRL and WRH feature of the BH part
was used to allow for byte writes to RAM. If the -90
part were to be used, additional logic would be necessary to generate these signals from WR and BHE.
THE 256K SYSTEM
The RAM chips utilized were NEC uPD43256-15 32K
x 8 static rams with an access time of 1SOns. The
ROMs were Intel 27512 64K x 8 EPROMs with an
access time of 200ns. The decoder circuitry used was
entirely LS TTL. Using an 8097BH running at lOMHz,
there was ample time for address decoding and memory
access. Timing analysis showed that 12MHz operation
would also be accommodated easily. If slower memories are used, further analysis would be necessary. Also,
it would be possible to switch to S TTL to greatly decrease the decoding response time.
Hardware
The hardware for the 256K system (see Figures 4 & 5,
an example with 128K ROM and 128K RAM) utilizes
a 74LS157 quad 2 to 1 multiplexer. The enable pin of
the 74LS157 is tied to the inverted A15 signal, which is
the latched addr/data 15 (ADI5) signal from the 96. In
this way, when A15 is low, the 74LS157 is disabled and
all its outputs are low. Particularly, MA17 is low,
which selects the 27512 and deselects the rams. Also,
MA15 and MA16 are low, which guarantee that addresses 0-7FFFH of the 27512 are accessed.
When A15 is high, the 74LS157 is enabled to pass
MA15 - MA17 values. The bank select pin of the
74LS157 is connected to the INST pin of the 96. When
the INST pin is high, for a code access, INSTAlS INSTA17 (pORTI.O - PORTI.2) are used. When
INST is low, for a data read or write, DATAA15 DATAA17 (PORT1.3 - PORT 1.5) are used. This allows for the use of separate pages for code and data
w~thout having to change the upper address lines each
time. Also, it is possible to select a ROM page for a
data table, or load a RAM page with executable code
downloaded from another source. PORTI.6 and
PORTI.7 can still be us~d as I/O ports. If a -90 part
were used, the INST pin would need to be latched since
it is only valid during the address output oli the bus
pins.
This system was designed to get the maximum amount
of memory with a minimum amount of hardware. The
EPROM
LOCATION
US •
3FFFH
OH
MAIN
PAGE
LOW
OH
3FFFH
4000H
PAGE1
4000H
BYTES
7FFFH
8000H
PAGE2
LOW
BYTES
BFFFH
PAGE3
LOW
BYTES
FFFFH
BFFFH
COOOH
FFFFH
When using this system there are several things to keep
in mind when preparing the software.
Since ASM96 will only allow addresses from 0FFFFH, it is necessary to generate each page of code in
a separate file. These pages should not be linked together, but rather should each be used to program the proper section of the EPROM associated with that page.
The main page routine should be coded with addresses
from 0-7FFFH, and each of the upper pages should be
coded with addresses from 8ooo-FFFH. Because linking is not possible, each module should contain a table
of constants which defines the symbols used in other
modules. These values are easily obtained from the listing file, which can be created using zeros in the table
the first time. The addresses of the pages in a 27512
after splitting low and high bytes into 2 EPROMs are .
shown in Figure 1.
EPROM
LOCATION
U6
7FFFH
LOW
. Software
8000H
COOOH
RAM
LOCATION
U7
MAIN
PAGE
HIGH
3FFFH
OH
PAGE1
HIGH
BYTES
7FFFH
4000H
RAM.
LOCATION
U8
PAGE4
LOW
BYTES
3FFFH
OH
PAGES
LOW
BYTES
7FFFH
4000H
U9
PAGE2
HIGH
BYTES
OH
PAGE3
HIGH
BYTES
3FFFH
4000H
7FFFH
6-182
PAGES
HIGH
BYTES
U10
PAGE6
LOW
BYTES
3FFFH
PAGE7
LOW
BYTES
7FFFH
Figure 1. The Current System
PAGE4
HIGH
BYTES
OH
4000H
PAGE6
HIGH
BYTES
PAGE7
HIGH
BYTES
AB-33
EPROM
LOCATION
U5
OH
3FFFH
4000H
7FFFH
BOOOH
BFFFH
COOOH
FFFFH
EPROM
LOCATION
EPROM
LOCATION
U6
MAIN
PAGE
LOW
3FFFH
OH
PAGEl
LOW
BYTES
7FFFH
PAGE2
LOW
BYTES
BFFFH
PAGE3
LOW
BYTES
FFFFH
4000H
BOOOH
GOOCH
EPROM
LOCATION
UB
U7
MAIN
PAGE
HIGH
3FFFH
OH
PAGEl
HIGH
BYTES
7FFFH
PAGE2
HIGH
BYTES
BFFFH
PAGE3
HIGH
BYTES
FFFFH
4000H
BOOOH
COOOH
OH
PAGE4
LOW
BYTES
3FFFH
PAGE5
LOW
BYTES
7FFFH
PAGE6
LOW
BYTES
BFFFH
PAGE7
LOW
BYTES
FFFFH
4000H
BOOOH
COOOH
PAGE4
HIGH
BYTES
PAGE5
HIGH
BYTES
PAGE6
HIGH
BYTES
PAGE7
HIGH
BYTES
Figure 2. A System Using all EPROMS and no RAM
All changes to the upper instruction addresses of
PORT! must be made by code located in the main
page. A listing of subroutines for use in the main page,
and a listing of macros for use in all pages is provided.
By invoking one of these macros the programmer can
easily transfer from one page to another, or select a new
data page. The subroutines should not be called directly, they should be entered by using the appropriate
macro. The subroutines should be located at the addresses specified, otherwise the macros must be
changed as they are written to call an absolute address
in the main page. Also, any hardware changes may render the software inoperative.
Second, 27128 16K x 8 EPROMS have been added for
use as the main code page. In this system, the main
page is physically separate from upper page O. The
27128's are selected by A15 being low. The upper pages
of memory are selected when A15 is high which enables
the 74LS155 demultiplexer which is used for address
decoding. When the 74LS155 is disabled, its outputs
are all high, which 'disables all upper memories. The
74LS157 is enabled all the time, to speed up address
decoding, as its outputs do not matter when the
74LS155 is disabled.
Software
Because the WRL-WRH feature of the 96BH is used,
the correct Chip Configuration Register value of OFBH
must be loaded into the ROMs at address 2018H. This
is done in the main code file with the following statements:
All rules for the 256K system apply to the 544K system, except that the main page no longer overlaps page
O. However, because all of PORT 1 is now in use, different macros and subroutines must now be used. These
have been included also.
CSEG AT 2018H
CCR: DCB OFBH
THE INST PIN
;VALUE FOR CHIP
CONFIGURATION REGISTER
Finally, it is necessary to initialize the DATA address
at the start of the program this can be done using the
NEW_DATAJAGE MACRO.
The instruction pin has been verified to work correctly
on the 8X9X- 90, 8X9XBH, and the 80C196. The functionality of the INST pin is as follows.
Instruction Fetches
THE 544K SYSTEM
The INST pin is high during an external memory read
indicating the read is an instruction fetch. This includes
immediate data reads since the data is embedded in the
code.
Hardware
The hardware for the 544K system '(see Figures 6 & 7,
an example with 288K ROM and 256K RAM) has
some slight changes from the 256K system.
First, all pins of PORT 1 are now in use as address lines.
This allows for PORT! to select 16 pages of memory,
'
with a different address for instructions or data.
Data Reads and Writes
The INST is low during an external memory read or
write indicating the bus cycle is a data cycle. This
would be indirect and indexed instructions which are
directed at external memory.
6-183
AB-33
EPROM
LOCATION
U5
EPROM
LOCATION
US
OH
OH
3FFFH
'3FFFH
U7
OH
3FFFH
4000H
7FFFH
BOOOH
BFFFH
COOOH
FFFFH
PAGEO
LOW
BYTES
3FFFH
OH
PAGE1
LOW
BYTES
7FFFH
PAGE2
LOW
BYTES
BFFFH
PAGE3
LOW
BYTES
FFFFH
4000H
BOOOH
COOOH
RAM
LOCATION
U11
OH
3FFFH
4000H
7FFFH
3FFFH
OH
PAGE9
LOW
BYTES
7FFFH
4000H
3FFFH
4000H
7FFFH
PAGE12
LOW
BYTES
PAGE13
LOW
BYTES
3FFFH
OH
PAGE1
HIGH
BYTES
7FFFH
PAGE2
HIGH
BYTES
BFFFH
PAGE3
HIGH
BYTES
FFFFH
4000H
BOOOH
COOOH
OH
3FFFH
4000H
7FFFH
OH
PAGE4
LOW
BYTES
3FFFH
PAGE5
LOW
BYTES
7FFFH
PAGE6
LOW
BYTES
BFFFH
PAGE7
LOW
BYTES
FFFFH
4000H
BOOOH
COOOH
RAM
LOCATION
U13
OH
PAGEB
HIGH
BYTES
3FFFH
PAGE9 .
HIGH
BYTES
7FFFH
4000H
PAGE12
HIGH
BYTES
OH
3FFFH
PAGE13
HIGH
BYTES
4000H
7FFFH
PAGE10
LOW
BYTES
3FFFH
PAGE11
LOW
BYTES
7FFFH
OH
4000H
6-184
PAGE5
HIGH
BYTES
PAGES
HIGH
BYTES
PAGE7
HIGH
BYTES
PAGE10
HIGH
BYTES
PAGE11
HIGH
BYTES
U1B
OH
PAGE14
LOW
BYTES
3FFFH
PAGE15
LOW
BYTES
7FFFH
Figure 3. The 544K Memory Map
PAGE4
HIGH
BYTES
RAM
LOCATION
U14
U17
U16
U15
OH
PAGEO
HIGH
BYTES
RAM
LOCATION
U12
PAGEB
LOW
BYTES
EPROM
LOCATION
U10
EPROM
LOCATION
U9
UB
4000H
PAGE14
HIGH
BYTES
PAGE15
HIGH
BYTES
inter
AB-33
+5
~.
----~
-------
~
--------------------
--
'---
---------
VREF
PIIl.IIl/ACIIl
PIIl.I/ACI
PIIl.2/AC2
PIIl.3/AC3
PIIl.4/AC4
PIIl.5/ACS
PIIl.6/ACS
PIIl.7/AC7
ANGND
P2.IIl/TXD
P2.I/RXD
P2.2/EXI
P2.31T2C
P2.4/T2R
P2.S/PWH
P2.6
P2.7
HSD.1Il
HSD.I
HSD.2
HSD.3
HSO.S/I3
HSO.41I2
HSI.I
HSI.1Il
NHI
RESET
CLKOUT
XTALI
XTAL2
>.>
PI. III
PI.I
PI.2
PI.3
PI.4
PI.S
PI.6 ---«
PI.7 ---«
DATAAIS
INSTAlS
DATAAI6
INSTAI6
DATAAI7
INSTAI7
INSTAlS
INSTAI6
INSTAI7
DATAAI5
DATAAI6
DATAAI7
HAI7
R-=:- ~
U2
.
ADIIl
ADI
AD2
AD3
AD4
AD5
AD6
AD7
II
~E U3
3
4
7
B
13
14
17
IB
Dill
DI
D2
D3
D4
DS
D6
D7
r-!3.
_" 7 LSOO
....
~
74 LSOO
74LSOO
1
I
G
·1 AlB
2 IA
IY 4 HAIS
3 IB
5
2A
2Y 7 HAIS
6 2B
II 3A
1111 3B
3Y 9 HAI7
4A
4Y
13 4B
74LSI57
.• RAH23
• U2
rlt
EA
BUSWDTH
INST
Rii
BHEI WRH
READY ~
WRI WRL
ALEI ADV
ADIS
P4.7/B15
ADI4
P4.S/BI4
ADI3
P4.S/BI3
ADI2
P4.4/B12
ADII
P4.3/BII
AD IIII
P4.2/BIIIl
AD9
P4.I/B9
ADB
P4.IIl/BB
AD7
P3.7/B7
AD6
P3.6/B6
ADS
P3.5/B5
AD4
P3.4/B4
AD3
P3.3/B3
AD2
P3.2/B2
ADI
P3.IIBI
ADIIl
P3.IIl/BIIl
8X97BH
U2
4
II
0..0
0..0..
AIS
~
Ul
QIIl
QI
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
IS
16
19
HAIIl
HAl
HA2
HA3
HA4
HAS
HA6
HA7
2
5
6
9
12
IS
16
19
HAB
HA9
HA I III
HAIl
HAI2
HAI3
HAI4
AIS
RAHIIlI
RD
WRH
WRL
741_5373
I
11
~
ADB
AD9
AD I III
ADII
ADI2
ADI3
ADI4
ADIS
3
4
7
B
13
14
17
IB
~E U4
Dill
DI
D2
D3
D4
DS
D6
D7
QIIl
QI
Q2
Q3
Q4
Q5
Q6
Q7
74LS373
270522-1
NOTE:
All other connections should be made as specified in current Embedded Controller Handbook.
Figure 4. 128KROM
+ .128K RAM Memory
6-185
AB-33
MAl 10
2!.8.2 91 A0
MA3 8 Al
MA4 7 A2
A3
MAS
A4
MA6 ~
5 _ AS
.J:!BZ 4 A6
MA8 3 A7
MA9 25 A8
MAIIll 24 A9
MAll 21
21A12 23 AI0
MAI3 2 All
_MAI4 26 AI2
AI3
J::!B£ 27 Al4
~ AI5
MAl 10
MA2 9
MA3 8
MA4 7
_MAS ~
_MA6 5
_MA7 4
21 A8 3
MAg 25
MAI0 24
MAIl 21
MAI223
MAI3 2
MAI4 26
MAI5 27
MAI6 I
~
US
Wi ADIll
01 12 ADI
AD202 .J.3
IS AD3
03 16
AD4
04 17 AOS05 W8 AD606 19 AD7
07
. Olll
DE 22 RD
IT 20 MAI7
A0
Al
A2
A3
A4
AS
A6
A7
AS
A9
AIIll
,All
AI2
AI3
AI4
Al5
U6
II AD8
00 12
01 13 AD9
ADIIll
02
03 ~
ADI2
04 16
ADl3
OS 17
AD14
06 18
07 19 ADI5
~
DE 22 RD
IT 20 MAI7
I
27512
27512
270522-2
MAl
MA2
MA3
MA4
MAS
MA6
MA7
MA8
MA9
MAl0
MAil
MAI2
MAI3
MAI4
MAI5
10
9
8
7
6
5
4
3
25
24
21
23
2
26
I
32Kx8
U7
100
101
102
103
104
IDS
106
107
II
12
13
15
16
17
18
19
AD0
ADI
AD2
AD3
AD4
ADS
AD6
AD7
270522-3
MAl 10
MA2 9
MA3 8
MA4 7
MAS 6
MA6 5
_MA7 4
_MA8 3
_MA9 25
MAI0 24
MAil 21
21A12 23
.1!A13 '2
MAI426
MAI5 l'
=-J
1
A0 32Kx8
II AD0
Al
100 12
AD!
101 13 AD2
A2
A3
102 IS AD3
A4 .
103 16 AD4
AS
I04
ADS
A6
105 17
AD6
A7
106 18
107 19 AD7
A8
A9
AI0
All
\it ~
AI2
DE 22 RD
RAM23
AI3
L5 ~
AI4
uPD43256 .
U9
270522-4
270522-7
Figure 5. 128K ROM
+ 128K RAM Memory
6-186
inter
AB·33
;MACROS FOR 256K SYSTEM
;LONG_BRANCH IS INVOKED TO BRANCH FROM ONE PAGE TO ANOTHER.
;ADDRESS MUST HAVE A VALUE FROM 8000H TO FFFFH.
;NEW_PAGE CAN BE AN IMMEDIATE NUMBER OR A REGISTER NUMBER.
MACRO
LD
LDB
BR
ENDM
ADDRESS, NEW_PAGE
CODE_ADDRESS, #ADDRESS ;SET UP CODE_ADDRESS REGISTER
NEW_PAGE_NO, NEW_PAGE ;SET UP NEW_PAGE_NO REGISTER
7FFOH
;BRANCH TO I_P_BRANCH
;LONG_CALL IS INVOKED TO CALL A SUBROUTINE IN ANOTHER PAGE.
;ADDRESS MUST HAVE A VALUE FROM 8000H TO FFFFH.
;NEW_PAGE CAN BE AN IMMEDIATE NUMBER OR A REGISTER NUMBER.
MACRO
LD
LDB
CALL
ENDM
ADDRESS, NEW_PAGE
CODE_ADDRESS, #ADDRESS ;SET UP CODE_ADDRESS REGISTER
NEW_PAGE_NO, NEW_PAGE ;SET UP NEW_PAGE_NO REGISTER
7FCOH
;CALL I_P_CALL
;PUSH_OLD_DATAPAGE IS INVOKED TO INSTALL A NEW DATA PAGE AND SAVE
;THE OLD VALUE ON THE SYSTEM STACK.
;NEW_PAGE CAN BE AN IMMEDIATE NUMBER OR A REGISTER NUMBER.
PUSH_OLD_DAPAG MACRO
LDB
PUSH
LDB
ANDB
SHLB
ANDB
ORB
ENDM
NEW_PAGE
AL, PORTl
AX
AL, NEW_PAGE
AL, #OOOOOllIB
AL, #3
PORTI, #IIOOOIIIB
PORTI, AL
;GET OLD PAGE NUMBER •••
;STORE IT ON THE STACK
;GET NEW DATA PAGE NUMBER •••
;MASK IT •••
;SHIFT IT TO PROPER POSITION •••
;CLEAR THE OLD ONE •••
;AND LOAD IN NEW ONE
;POP_OLD_DATAPAGE IS INVOKED TO REINSTALL AN OLD DATA PAGE THAT WAS SAVED
JON THE SYSTEM STACK BY PUSH_OLD_DATAPAGE.
POP_OLD_DAPAG MACRO
POP
ANDB
ANDB
ORB
ENDM
AX
AL, #OOllIOOOB
PORTI, #IIOOOIIIB
PORTl, AL
;RECALL OLD PAGE NUMBER •••
;MASK OLD ONE FOR DATA PAGE •••
;CLEAR NEW DATA PAGE •••
;AND LOAD IN OLD ONE
;NEW_DATA_PAGE IS INVOKED TO INSTALL A NEW DATA PAGE.
;NEW_PAGE CAN BE AN IMMEDIATE NUMBER OR A REGISTER NUMBER.
NEW_DATA_PAGE
MACRO
LDB
ANDB
SHLB
ANDB
ORB
ENDM
NEW_PAGE
AL, NEW_PAGE
AL, #OOOOOlllB
AL #3
PORTI, #IIOOOIIIB
PORTl, AL
6-187
;GET NEW DATA PAGE NUMBER •••
;MASK IT •••
;SHIFT IT TO PROPER POSITION •••
;CLEAR THE OLD ONE •••
;AND LOAD -IN NEW ONE
intJ
AB-33
jSUBROUTINES FOR 256K SYSTEM
CSEG AT 7FCOH
jSUBROUTINE:
I_P_CALL
THIS SUBROUTINE ALLOWS FOR THE CALLING OF SUBROUTINES LOCATED IN
A DIFFERENT PAGE OF MEMORY.
,
PARAMETERS:
SUBROUTINES:
LP_CALL:
LP_RETURN:
CODE_ADDRESS, NEW_PAGE_NO
ANY THAT ARE REQUESTED.
LDB
PUSH
ANDB
ANDB
ORB
PUSH
BR
AL, PORTI
jGET OLD PAGE NUMBER •••
jSTORE IT ON THE STACK
PORTI, #IIIIIOOOB
jCLEAR OLD INST PAGE •••
NEW_PAGE_NO, #OOOOOIIIB jMASK NEW ONE •••
PORTI, NEW_PAGE_NO
jAND LOAD IT IN
#LP_RETURN
jSAVE RETURN ADDRESS •• ;
[CODE_ADDRESS]
jCALL REQUESTED ROUTINE
POP
ANDB
ANDB
ORB
RET
AX
AX
PORTI, #IIIIIOOOB
AL, #OOOOOlllB
PORTI, AL
jRECALL OLD PAGE NUMBER •••
jCLEAR NEW INST PAGE •••
jMASK OLD ONE •••
jAND LOAD IT IN
jRETURN TO CALLING ROUTINE
CSEG AT 7FFOH
jSUBROUTINE:
I_P_BRANCH
THIS SUBROUTINE AL~OWS FOR BRANCHING TO LOCATIONS IN A DIFFERENT
PAGE OF MEMORY.
PARAMETERS:
SUBROUTINES:
"
LP_BRANCH:
ANDB
ANDB
ORB
BR
CODE-ADDRESS, NEW_PAGE_NO
NONE
PORT I , #IIIIIOOOB
NEW_PAGE_NO #OOOOOIIIB
PORTI, NEW_PAGE_NO
[CODE_ADDRESS]
ROUTINE
6-188
jCLEAR OLD INST PAGE •••
jMASK NEW ONE •••
jAND LOAD IT IN
jBRANCH TO REQUESTED
AB·33
1111
1112
HA4
HAS
HA6
HA7
II
9
8
7
6
5
4
S
25
HAIH 24
HAil 21
HAI2 23
HAI3 2
1426
HAIS I
HAl
1112
HA3
HA4
HAS
HA6
HA7
HAS
HAg
HAle
11111
l1li12
HAI3
11114
HAIS
IH
9
8
7
6
5
4
S
HAl
AI DOd!
RI
R2
AS
R4
AS
AS
R7
R8
R9Ull
AlB
1011
101
102
103
104
lOS
106
107
All
VE
AI2
II:
RIS
"C5
AI4
uP04325B
AI D:xB
AI
1011
R2
101
AS
102
A4
103
AS
104
AS
A7
25
R8
24
R9 U12
lOS
106
107
21
RIB
23
All
2
DE
AI2
26
AIS
"C5
I
AI4
uP043258
w:
II
12
13
15
16
17
18
19
ROIl
ROI
R02
R03
R04
nos
ROB
R07
27 gR(
22
PAG11-9
1112
HA3
HA4
HAS
HAS
HA7
HAS
HA9
HAIH
HAil
HAI2
HAI3
HAI4
HAIS
HAl
II
12
13
15
16
17
18
19
ROIl
R09
ROIH
ROil
ROI2
ROI3
ROI4
ROIS
27 QIIiI
22
2B _ 9
1112
HA4
HAS
HAS
HA7
HAS
HA9
HAIl
HAil
HAI2
HAl!
HAI4
HAIS
II
9
8
7
B
5
4
3
AI D:xB
RI
R2
AS
R4
AS
AS
25
R7
24
21
23
2
26
I
R9
U13
AIH
AI
1011
101
102
103
104
105
106
107
w:
All
AI2
RI3
R4
II:
"C5
27gR(
22
2B PRGIII-Il
uP04325B
IH
9
B
7
B
5
4
3
R8 32KxII
1011
101
102
103
104
AI
R2
AS
A4
AS
AS
lOS
A7
25
R8
24
21
23
2
26
I
R9 U14
106
107
All
All
DE
AI2
"C5
AI3
RI4
uP043256
w:
IlR01i1
12
13
15
18
17
18
19
R09
ROIH
ROil
ROI2
ROI3
ROI4
ROIS
27 ~ I
22
2B PAGIII-Il
U2
SElA
SEL8
STR81
DATAl
HAl
1112
HA3
HA4
HA6
HA7
II
9
B
7
6
5
4
3
24
AI
II ROIl
DB 12 ROI
AI
A2
01
02
03
04
AS
A4
AS
AS
HAS
A7
HA9
R8
HRl8 25
R9
us
HAil 21
AIH
HAI2 23
All
HAl! 2
AI2
HAI4 2B
AI!
HAl
HA2
1113
HA4
HAS
HA6
74lS37!
Hlt7
HAS
HA9
HAIH
HAil
12
HAl!
HAI4
II
AI
9
AI
8
7
B
S
4
3
24
25
13
15
16
17
OS 18
06
19
07 I
VPP 22
lIE 27
I'l:R 21
a
R02
A03
R04
ADS
ROB
A07
AIS
27128
011
01
02
03
04
R2
AS
A4
AS
AS
A7
R8
05
R9 us
21
All
23
All
2
AI2
28
AI!
06
07
VPP
lIE
!'Gil
a
II
12
13
IS
16
17
IB
19
I
22
27
28
ROIl
A09
ROIl
11111
1I\t2
13
1114
11115
AIS
27128
270522-8
NOTE:
All other connections should be made as specified in current Embedded Controller Handbook.
Figure 6. 288K ROM -+ 256K RAM Memory
6-189
intJ
AB·33
IlAI
11A2
HR3
1lA4
HAS
HA6
!VI7
HAS
HA9
HAIB
HAil
HAI2
HAI3
"AU
I1AIs
IB
9
8
7
6
S
4
3
25
24
21
23
2
26
I
HAl
HA2
HA3
HR4
HAS
18
9
8
7
6
S
4
3
2S
24
21
23
2
26
I
HAS
HA7
I1A8
HA9
HAI9
HAil
HRI2
HAI3
HAI4
HAls
!VII
All 32Kx8
AI
A2
A3
A4
AS
A6
A7
R8
A9
AlB
All
AI2
AI3
AI'
Ul5
lOll
101
102
103
104
105
106
107
1'1
12
13
IS
16
17
18
19
HA4
HRS
HAS
HA7
27 iii![
uPD43256
II
12
13
IS
16
17
18
19
IJ2I
HAl
HAl
HR4
HAS
HAS
HA7
HAl
+S
AD8
R09
ROI8
ADII
AOl2
ROI3
ROI4
ADIS
27 iiRH
22
29 PAG12-13
All
9
RI
S
R2
7
R3
6
R4
5
4
3
25
liUS
HAll
HAI2
HAI3
HAI4
HAI5
HAI6
2.
21
23
2
HAll
HA9
HAIB
HAil
HAI2
HAI3
HAI4
HAIS
HRI6
+
I
Ul7
Ul8
256K RRM MEMORY
PRG4-7
IB
HR9
HAl
HA2
HA3
HA4
HAS
HA6
HA7
All 321::)(8
II AOB
lOB
A2
101 "iYiiDI
i3~
A3
102 IS AD3
A4
103
104 16 AD4
AS
17 ADS
AS
lOS
18 A06
A7
106 19 A07
107
R8
A9
AI9
27 iii![_
All
"lIE 22
AI2
ill': 29 PRGU-Is
AI3
13
AI.
uP0432s6
AB 32K.8
11 R08
Al
108
12 R09
A2
101
13 ROIB
A3
102
IS ROil
A4
103
104 16 ROI2
AS
17 ROI3
AS
lOS
AOI'
A7
106 18
19 AOIS
AS
107
A9
AlB
27 ilRii
All
"lIE 22
AI2
DE 2B PRG14-ls
AI3
13
AI4
uPD432s6
PRGB-3
IJ2I
HR2
26
IB
9
8
7
I1R5
6
HAS
5
~ 4
HAS
3
HA9 2S
"A19 24
HAil 21
HAI2 23
HAI3 2
HAI4 26
I1AIS I
288K ROM
_UHI
PAG12-13
PAG14-15
PAGB-I
PRG2-3
PA&4-5
PAG6-7
2S
24
21
23
2
HAl
HA2
HA3
11A4
Ul6
]
7
6
S
HAS
!VI9
!VIIB
HAil
11A12
!VII 3
IlAU
HAIS
"lIE 22
or
13 29 PAGI2-11l
AI! 32K.8
AI
lOll
A2
101
A3
102
A4
103
AS
104
A6
lOS
A7
106
AS
107
A9
AlB
All
"lIE
AI2
ill':
AI3
13
AU
uP043256
IB
HA2
9
""I1A3- 8 Al
ADB
AOI
R02
R03
R04
ADS
ADS
AD7
26
27
I
U7
AS
01
01
02
03
D.
R7
OS
R8
06
07
AS
A9
AlB
RII
AI2
AI3
RI4
RI5
II
9 AI
RI
S
7 A2
A3
6
A4
5
AS
4
AS
3
R7
25
All
24
R9
21
AlB
23
2 All
26 AI2
AI3
27
RI4
I
AI5
HAl
HA2
HR3
HA4
HAS
HAS
HA7
HAl
HR9
HAIH
HAil
HAI2
HRI3
HA14
HAI5
HAI6
DE 22
IT 2B PRGII-3
27512
U8
DB
01
02
03
04
05
06
07
11
12
13
IS
16
17
IB
19
HAl
HA2
HR3
HA4
ADB
A09
ROIl
ROll
ROI2
ROI3
ADI4
ROI5
HAS
HAS
HA7
HRB
HR9
HAIB
HAil
HAI2
HAU
HR14
HAI5
HAI6
DE 22
IT 2BPRGI~
ii5i'2-
IB AS
9
AI
8
.R2
7
R3
6 A4
5 AS
4
AS
3 A7
U9
OS
25
AS
2' A9
21
23
2
26
27
I
19
9
8
7
6
5
4
3
25
24
21
23
2
26
27
I
06
07
All
RlI
RI2
RI3
RI4
AIs
UH'l
+
AS
AS
DB
01
02
03
04
05
A7
R8
A9
RII
All
AI2
AI3
Rl4
AI5
06
07
Of
CE
256K RAM Memory
6-190
AOB
RDI
R02
R03
AD4
R05
A06
AD7
-
27512 .
Figure 7. 288K ROM
11
12
13
IS
16
17
IB
19
22
DE 21
PRG4-7
CE
27512
AB
RI
A2
A3
A4
DB
01
02
03
O.
11 ROB
R09
12
13
IS
16
17
IB
19
ROIB
ROil
ADI2
ADU
ADI4
ADl5
-
22
28 PAG~. __ .
270522-9
inter
AB-33
;MACROS FOR 544K SYSTEM
;LONG_BRANCH IS INVOKED TO BRANCH FROM ONE PAGE TO ANOTHER.
;ADDRESS MUST HAVE A VALUE FROM 8000H TO FFFFH.
;NEW_PAGE CAN BE AN IMMEDIATE NUMBER OR A REGISTER NUMBER.
MACRO
LD
LDB
BR
ENDM
ADDRESS, NEW_PAGE
CODE_ADDRESS, #ADDRESS ;SET UP CODE_ADDRESS REGISTER
NEW_PAGE_NO, NEW_PAGE ;SET UP NEW_PAGE_NO REGISTER
7FFOH
;BRANCH TO I_P_BRANCH
LONG_CALL IS INVOKED TO CALL A SUBROUTINE IN ANOTHER PAGE.
;ADDRESS MUST HAVE A VALUE FROM 8000H TO FFFFH.
;NEW_PAGE CAN BE AN IMMEDIATE NUMBER OR A REGISTER NUMBER.
MACRO ADDRESS, NEW_PAGE
LD
CODE_ADDRESS, #ADDRESS ;SET UP CODE_ADDRESS REGISTER
NEW_PAGE_NO, NEW_PAGE ;SET UP NEW_PAGE_NO REGISTER
LDB
7FCOH
;CALL I_P_CALL
CALL
ENDM
;PUSH_OLD_DATAPAGE IS INVOKED TO INSTALL A NEW DATA PAGE AND SAVE THE OLD
;VALUE ON THE SYSTEM STACK.
;NEW_PAGE CAN BE AN IMMEDIATE NUMBER OR A REGISTER NUMBER.
PUSH_OLD_DAPAG MACRO
LDB
PUSH
LDB
SHLB
.ANDB
ORB
ENDM
NEW_PAGE
AL, PORTl
AX
AL, NEW_PAGE
AL, #4
PORT1, #OOOOllllB
PORTl, AL
;GET OLD PAGE NUMBER •••
;STORE IT ON THE STACK
;GET NEW DATA PAGE NUMBER: ••
;SHIFT IT TO PROPER POSITION •••
;CLEAR THE OLD ONE •••
;AND LOAD IN NEW ONE
;POP_OLD_DATAPAGE IS INVOKED TO REINSTALL AN OLD DATA PAGE THAT WAS SAVED
;ON THE SYSTEM STACK BY PUSH_OLD_DATAPAGE.
POP_OLD_DAPAG MACRO
POP
AX
ANDB AL, #llllOOOOB
ANDB PORT1, #OOOOllllB
ORB
PORTl, AL
ENDM
;RECALL OLD PAGE NUMBER •••
;MASK OLD ONE FOR DATA PAGE •••
;CLEAR NEW DATA PAGE •••
;AND LOAD IN OLD ONE
;NEW_DATA_PAGE IS INVOKED TO INSTALL A NEW DATA PAGE.
;NEW_PAGE CAN BE AN IMMEDIATE NUMBER OR A REGISTER NUMBER.
NEW_DATA_PAGE
MACRO NEW_PAGE
AL, NEW_PAGE
LDB
SHLB AL, #4
ANDB
PORT1, #OOOOllllB
ORB
PORTl, AL
ENDM·
6-191
;GET NEW DATA PAGE NUMBER •••
;SHIFT IT TO PROPER POSITION •••
;CLEAR THE OLD ONE •••
;AND LOAD IN NEW ONE
intJ
AB-33
;SUBROUTINES FOR 544K SYSTEM
CSEG AT 7FCOH
;SUBROUTINE:
I_P_CALL
THIS SUBROUTINE ALLOWS FOR THE CALLING OF SUBROUTINES LOCATED IN
A DIFFERENT PAGE OF MEMORY.
PARAMETERS:
SUBROUTINES:
LP_RETURN:
CODE_ADDRESS, NEW_PAGE_NO
ANY THAT ARE REQUESTED.
LDB
PUSH
ANDB
ANDB
ORB
PUSH
BR
AL, PORTl
POP
ANDB
ANDB
ORB
RET
AX
;GET OLD PAGE NUMBER •••
;STORE IT ON THE STACK
PORTI, #llllOOOOB
;CLEAR OLD INST PAGE •••
NEW_PAGE_NO, #OOOOIIIIB ;MASK NEW ONE •••
PORTI, NEW_PAGE_NO
;AND LOAD IT IN
#LP_RETURN
;SAVE RETURN ADDRESS •••
[CODE_ADDRESS]
;CALL REQUESTED ROUTINE
AX
PORT I , #IIIIOOOOB
AL, #OOOOlllIB
PORTl, AL
;RECALL OLD PAGE NUMBER •••
;CLEAR NEW INST PAGE •••
:MASK OLD ONE •••
;AND LOAD IT IN
;RETURN TO CALLING ROUTINE
CSEG AT 7FFOH
;SUBROUTINE:
I_P_BRANCH
THIS SUBROUTINE ALLOWS FOR BRANCHING TO LOCATIONS IN A DIFFERENT
PAGE OF MEMORY.
PARAMETERS:
SUBROUTINES:
LP_BRANCH:
ANDB
ANDB.
ORB
BR
CODE_ADDRESS, NEW_PAGE_NO
NONE
PORTI, #IIIIOOOOB
NEW_PAGE_NO, #OOOOIIIIB
PORTI, NEW_PAGE_NO
[CODE_ADDRESS]
6-192
;CLEAR OLD INST PAGE •••
;MASK NEW ONE •••
;AND LOAD IT IN
;BRANCH TO REQUESTED ROUTINE
APPLICATION
BRIEF
AB-34
December 1987
Integer Square Root Routine for
the 8096
LIONEL SMITH
ECO APPLICATIONS ENGINEER
@ Intel Corporation, 1987
Order Number: 270523-001
6-193
intJ
AB-34
This Application Brief presents an example of calculating the square root of a 32-bit signed integer.
Theory
Newton showed that the square root can be calculated
by repeating the approximation:
Xnew = (R/Xold
+ Xold)/2 ; Xold
= Xnew
where: R is the radicand
Xold is the current approximation of the
square root
Xnew is the new approximation
until you get an answer you like. A common technique
for deciding whether or not you like the answer is to
loop on the approximation until Xnew stops changing.
If you are dealing with real (floating point) numbers
this technique can sometimes get you in trouble because
it's possible to hang up in the loop with Xnew alternating between two values. This is not the case with integers. As an example of how it all works, consider taking
the square root of 37 with an initial guess (Xold) of 1:
+
Xnew
=
(3711
Xnew
=
(37/19
+
Xnew
=
(37/10
+ 10)/2 =
Xnew = (3716
1)/2
=
19)/2
+ 6)/2
19; Xold
=
=
10; Xold
6; Xold
19
=
=
10
The largest positive integer you can represent with a
32-bit two's complement number is 07fff$ffiTh, or
2,147,483,647. The square root of this number is
Ob504h, or 46,340. The largest square root that we can
generate from a 32-bit radicand can be represented in
16-bits. If we are careful in picking our initial Xold we
can do all of the divisions with the 32 by 16 divide
instruction we have available. Picking the largest possible 16-bit number (0fllTh) will always work although it
may slow the calculation down by requiring too many
iterations to arrive at the correct result. The algorithm
below takes a slightly more intelligent approach. It uses
the normalize instruction to figure out how many leading zeros the 32-bit radicand has and picks an initial
Xold based on this information. If there are 16 or more
leading zeros then the radicand is less than 16 bits so an
initial Xold of 0fTh is chosen. If the radicand is more
than 16 bits then the initial Xold is calculated by shifting the value 0fllTh by half as many places as there were
leading zeros in tp.e radicand. To give credit where
credit is due, I first saw this 'trick" in the January 1986
issue of Dr. Dobbs's Journal in a I~tter from Michael
Barr of McGill University.
The routine was timed in a 12.0 Mhz 8096 as it calculated the square roots of all'positive 32-bit numbers, the
following numbers include the CALL and return sequence and were measured using Timer 1 of the 8096.
6
= 6; Xold = 6 - done!
Note that in integer arithmetic the remainder of a division is ignored and the square root of a number is
floored (i.e. the square root is the largest integer which,
when multiplied by itself, is less than or equal to the
radicand).
Practice
The only' significant problem in implementing the
square root calculation using this algorithm is that the
division of R by Xold could easily be a 32 by 32 divide
if R is a 32 bit integer. This is ok if you happen to have
a 32 by 32 divide instruction, but most 16-bit machines
(including the 8096) only provide a 32 by 16 divide.
However, a little bit of creative laziness will allow us to
squeeze by using the 32 by 16 bit divide on the 8096.
Minimum Execution Time:
24 microseconds
Maximum Execution Time:
236 microseconds
Average Execution Time:
102 microseconds
Comments
The program module which follows is part of a collection of routines which perform integer and real arithmetic on a software implemented tagged stack. The top
element of the stack is call TOS and is in fixed locations
in the register file. Since the square root operation only
involves TOS, further details of the stack structure are
not shown.
6-194
intJ
AB·34
MCS-96 MACRO ASSEMBLER
SQRT
DOS MCS-96 MACRO ASSEMBLER, Vl.l
SOURCE FILE: ROOT2.A96
OBJECT FILE: ROOT2.0BJ
CONTROLS SPECIFIED IN INVOCATION COMMAND: NOSB
ERR LOC OBJECT
LINE
SOURCE STATEMENT
05/12/86 10 :44 :30 PAGE
1
2
sqrt module
3
4
; 32 bit integer square root for the 8096
5
6
7
8
0019
public qstk.isqrt
extrn lntarr :entry
TOP+- SQUARE.ROOT (TOP)
Integer error routine
10
id stags for stack integer routines
isqrt.id
equ
19h
11
12
; error codes
13
0000
0001
0002
14
15
overflow
paramerr
16
invalid.input
equ
equ
equ
OOh
Olh
02h
17
OOlC
OOlC
OOlC
OOlD
OOlE
0020
0022,
0018
18
19
20
21
22
23
24
25
26
oseg at leh
=======
ax:
dsw 1
al equ ax:byte
ah equ (ax+l) :byte
dx:
dsw 1
ex:
dsw 1
bx:
dsw 1
sp
equ 18h :word
27
0030
0030
0030
0030
0032
0034
0034
28
29
30
31
32
qstk.reg:
dsl
33
next
34
35
36
tos.tag equ (qstk_reg+2) :word
tos_value:
dsl
1
oseg at 30h
=========
equ qstk_reg:word
37
0000
38
39
40
41
42
43
44
45
46
47
cseg
bl
macro param
bnc
param
endm
bhe macro param
param
be
endm
'eject
6-195
make sure of alignment
pointer to next element In the arg stack.
32 bit integer
1
inter
AB-34
MCS-96 MACRO ASSEMBLER
ERR LOC OBJECT
0000
0000
0020
0000 A0341C
0003 A036lE
0006 371F07
0009 C90119
OOOC EFOOOO
OOOF FO
0010
0010 OF221C
0013 DF3B
0015 991022
0018 DA06
OOlA AIFF0020
OOlE 200A
0020
0020 180122
0023 AIFFFF20
0027 082220
002A
002A A0341C
002D A0361E
0030 88201E
0035 8C201C
0038 88201C
003D
003F
0042
0045
0048
004A
004A
004D
0050
0050
0051
0122
641C20
A40022
OC0120
27EO
A02034
AOO036
FO
ASSEIIllLY COMPLETED.
SQRT
LIIiE
48
49
50
51
52
53
54
55
56
57
58
59
60
E
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
80
81
82
84
85
86
87
88
89
90
'.
91
92
93
94
05/12/86 10 :44 :30 PAGE
SOURCE STATEIlENT
cseg
qstk_isqrt:
Takes the square root of the long integer in TOS
TOS- Top of argument stack
!TOS - iSQRT(TOS)
Xold set cx
Id
ax,toB_value
Id
dx, (tos_value+2)
' (dx+l) , 7,qsi05
; i f (TOS < 0)
bbc
push
#(isqrt_id*256+paramerr)
call
interr
Call interr.
ret
Exit
qsi05:
normal ax, bx
qstk_isqrtO
be
cmpb
bX,#16
it (TOS < 2**16)
ble
qs110
Use Offh as first estimate.
Id
Xold, #Offh
qstk_isqrtloop
br
qs110:
shrb
bx,#l
else
Id
Xold, #Offfth
Base the first estimate on the
Xold, bx
shr
number ot leading zeroes in TOS.
qstk_isqrtloop;
Id
ax,tos ... valu8
do
dx, (tos_value+2)
Id
if (The divide w111 overflow)
cmp
dX,Xold
The loop is done.
qstk_isqrt_done
bhe
divu
ax,Xold
i f ( (ax=TOS/Xold) >= Xold)
The loop is done.
cmp
ax,Xold
qstk_isqrt_done'
bhe
clr
bx
Xold= (ax+Xold) /2
add
Xold,ax
bx,O
addc
shrl
Xold,#l
qstk_isqrtloop
; wh11e (The loop 1s not done)
br
'qstk_isqrt_done:
Id
tos_value,Xold
; TOS=OO :Xold
Id
(tos_va1ue+2),0
qstk_isqrtO:
ret
Exit
end
NO ERROR(S) FOUND.
6-196
2
inter
APPLICATION
NOTE
AP-406
December 1987
MCS®-96
Analog Acquisition Primer
DAVID P. RYAN
INTEL CORPORATION
® Intel Corporation, 1987
Order Number: 270365-001
6-197
inter
AP-406
with digital methods of processing analog signals. This
Application Note assists with the first task-understanding of an analog acquisition system.
THE MCS®-96 ANALOG ACQUISITION
PRIMER
Designers experienced with analog design, or' analog
acquisition systems, may find no revelations herein. To
those unfamiliar with analog acquisition systems, this
Ap Note provides a tutorial on the subject and will
serve as a handy reference.
INTRODUCTION
As technology advances, embedded control applications continue to reduce chip-count and demand microcontrollers with increased features to assist system-cost
reduction. Since every embedded control application interfaces with the physical world, and the physical world
is an analog process, it was inevitable that microcontrollers would include integrated analog acquisition capabilities.
Answering the limitless number of analog circuit design
questions is beyond the scope of this Ap Note. Suffice it
to say that the effort placed on the design of analog
circuits should increase with a decreasing error budget.
The first such integration of standard microcontroller
and AID converter occurred on Intel's 8022 in 1978."
This opened the door to cost reduction of high volume
applications that required analog inputs. The device fit
well into applications that needed processing of analog
data. But this chip, with its 8-bit CPU, could not perform in high-end applications requiring analog inputs,
or in applications that had computationally demanding
analog tasks.
With the introduction of the MCS®-96 family of 16-bit
microcontrollers in 1982, the combined CPU and AID
performance became available to greatly reduce the system cost of mid- and high-performance embedded control applications. These are applications which were
customarily implemented with 16-bit microprocessor
chip-sets teamed with analog acquisition chip sets.
There are less obvious avenues for system cost reduction when a 16-bit CPU is teamed with an on-chip analog acquisition system. For example, clOsed-loop servo
control had been implemented almost exclusively by
using analog methods. When an MCS-96 device is designed into such an application, it is not only replacing
a microcontroller or microprocessor, but it also replaces closed-loop analog circuitI"'j which never before
came in contact with the digital system.
To take full advantage of this new level of integration,
digital designers must become familiar with analog acquisition, and analog designers must become familiar
At a minimum, the applications literature of op-amp
manufacturers and analog design manuals are a good
place to start. Furthermore, the applications literature
of monolithic analog acquisition system manufacturers
should be consulted since the suggestions presented
therein are largely transportable to any AID system.
This Ap Note is organized in the following sections.
The components of an ,analog acquisition system and
the errors associated with each is first explained. Then,
interfacing suggestions and ideas for getting more reso~
lution are presented. Finally, a set of appendices
provides back-up information, a bibliography, actual
converter data and some program listings.
The definitions of terms us~, and the examples presented, are drawn from the body of applications literature publicly available on the components of an analog
acquisition system. There 'is usually no single meaning
for a particular term or specification used to describe
analog acquisition. However, there is, in most cases, a
generally accepted definition which is most often used.
To the extent possible, we have adopted the most used
definition. To avoid any ambiguity, Appendix A lists
the dictionary of terms as used to refer to the analog
acquisition systems of MCS-96 devices.
For any users of an MCS-96 analog acquisition system
(experienced or not), this document contains very useful information. It should be considered mandatory
reading in addition to the latest Embedded Controller
Handbook and MCS-96 data sheet for the actual device
in use prior to the actual design.
6-198
inter
AP-406
WHAT IS AN ANALOG ACQUISITION
SYSTEM?
An analog acquisition system is a collection of individual units which, when logically configured, form a system capable of converting an analog input to a digital
value.
The typical components of an Analog Acquisition Unit
(Figure I) include an, Analog-to-Digital Converter
(AID), a Sample-and-Hold (S/H) and an Analog Multiplexer (MUX). The AID converts the infinitely varying analog voltage present on the S/H into a digital
representation for use by the digital system. The S/H is
required so a "snapshot" of a changing analog input
can be stored for conversion by the AID. The MUX is
used to leverage the investment in the AID by allowing
a large number of isolated analog input channels to use
the same converter.
The conversion result of an MCS-96 device is a lO-bit
ratiometric representation of the input voltage. This
produces a stair-stepped transfer function when the
output code is plotted versus input voltage. See
Figure 2.
The resulting digital codes can be taken as simple ratiometric information, or they can be used to provide information about absolute voltages or rel,ative voltage
changes on the inputs. The more demanding the application is on the AID converter, the more important it
is to fully understand the converter's operation. For
simple applications, knowing the absolute error of the
converter is sufficient. However, controlling a closed
loop with analog inputs necessitates a detailed understanding of an AID converter's operation and errors.
scale error; differential non-linearity; and non-linearity.
These are "transfer function" errors related to the AID
converter. In addition, the S/H and MUX may induce
channel dissimilarities and sampling error (described
later).
Fortunately, one "Absolute Error" specification is
available which describes the sum total of all deviations
between the actual conversion process and an ideal converter. The various sub-components of error are, however, important in many applications. These error components are described in Appendix A and in the text
below where ideal and actual converters are compared.
AID Converter
There are at least three well-recognized methods for
converting an analog voltage to a digital value-flash,
dual slope and successive approximation.
Flash AIDs are the fastest, and most expensive converters for a given accuracy. Flash converters typically
resolve bits of the result in parallel to achieve fast conversions. Flash converter speeds are measured in tensof-nanoseconds.
Dual slope converters are the slowest, but most accurate. Dual slope conversion is rather insensitive to noise
on the input, but conversion times are measured in
milliseconds.
Successive approximation converters provide a balanced tradeoff between speed and accuracy. Successive
approximation conversion times are measured in tensof-microseconds, and converter implementations are
very economical for a given accuracy.
The errors inherent in an analog-to-digital conversion
process are many: quantizing error; zero offset; full-
MULTIPLEXER
SAMPLE/HOLD
ANALOG
TO
DIGITAL
CONVERTER
BUSY
• •
• •
• •
GO
270365-1
Figure 1. An Analog Acquisition System
6-199
inter
AP-406
7
I
fiNAL CODE TRANSITION OCCURS
WHEN THE APPLIED VOLTAGE IS
EQUAL TO (Vr.' - 1 1:/2 (LSB».
6
I
I
1-_ _- 0
r-------~
.. -,- -
5
~
I
I
ACTUAL CHARACTERISTIC Of
AN IDEAL AID CONVERTER
I
I
:
~
Q
--_.
-------t.
I
I
.
THE VOLTAGE CHANGE
BETWEEN ADJACENT CODE
TRANSITIONS (THE "CODE
WIDTH") IS
1 LSB.
I
.------_.
3
=
.-------.
2
r-------·
----II-'
I
fiRST CODE TRANsmON OCCURS
WHEN THE APPLIED VOLTAGE IS
EQUAL TO 112 LSB.
O~--~---.--------~-------.--------~-------.---------.---.----~------~
1/2
2
5
3
6
61/2
8
7
INPUT VOLTAGE(lSBs)
270365-2
Figure 2.\dea\ AID Characteristic
MCS796 converters use successive approximation. A
successive approximation conversion is performed by
comparing a sequence of reference voltages to the ana·
log input in a binary search for the reference voltage
that most closely matches the input. The 'I. full·scale
reference voltages is the tested first. This corresponds
to a IO-bit result where the most significant bit is zero,
and all other bits are ones (0111 1111 lIb). If the analog input is less than the test voltage, bit 10 of the result
is left a zero, and a new test voltage of 'I. full-scale
(00 11 1111 11 b) is tried. If this test voltage is lower
than the analog input, bit 9 of the result is set and bit 8
is cleared for the next test (01011111 lIb). This binary
search continues until 10 tests have occurred, at which
time the valid IO-bit conversion result reside,s in a register where it can be read by software.
The voltages used during the binary search are generated from an internal Digital-to-Analog Converter similar to Figure 3. The figure shows eight resistors being
used as a three-bit D' to A. The first resistor tap is taken
from the center of the first resistor to guarantee that a
zero input voltage will always output a zero code. Each
successive tap then provides a reference voltage
VREP/8 (one LSB) from the previous tap. When the
analog input is above the voltage of the seventh tap, the
AID will resolve to its full-scale value of 111 b. Therefore, an eighth tap is not needed, and the AID's 1lOb to
Illb code transition will occur when VANIN equals
VREP - 1 'I. LSB.
The first error seen in this process is unavoidable, and
results from the conversion of a continuous voltage to
6-200
AP-406
ANGND
270365-3
Figure 3. A Three-Bit D-to-A
an integer digital representation. This error is called
quantizing error, and is always ±0.5 LSB. Quantizing
error is the only error seen in a perfect AID converter,
and is obviously present in actual converters. Figure 2
shows the transfer function for an ideal 3-bit AID converter (i.e. the Ideal Characteristic).
Note that in Figure 2 the Ideal Characteristic possesses
unique qualities: it's first code transition occurs when
the input voltage is 0.5 LSB; it's full-scale code transition occurs when the input voltage equals the fullscale reference minus 1.5 LSB; and it's code widths are
all exactly one LSB. These qUalities result in a digitization without offset, full-scale or linearity errors. In other words, a perfect conversion.
Figure 4 shows an Actual Characteristic of a hypothetical 3-bit converter which is not perfect. When the Ideal
Characteristic is overlaid with the imperfect characteristic, the actual converter is seen to exhibit errors in the
location of the first and final code transitions and code
widths. The deviation of the first code transition from
ideal is called "zero offset". The deviation of the final
code transition from ideal is "full-scale error".
The deviation of the code widths from ideal causes two
types of errors. Differential Non-Linearity and NonLinearity. Differential Non- Linearity is a locallinearity error measure, whereas Non-Linearity is an overall
linearity error measure. For example, Figure 5a shows
a transfer function with a large differential non-linearity and a little non-linearity. In contrast, Figure 5b
shows a characteristic with small differential errors but
a large overall linearity error.
Differential Non-Linearity is the degree to which actual
code widths differ from the ideal width. Differential
Non-Linearity gives the user a measure of how much
the input voltage may have changed in order to produce a one count change in the conversion result.
If the absolute value of an input voltage is less important than the amount that the input changes, the differential non-linearity (DNL) specification of a converter
is very important. For example, if the differential nonlinearity of a converter is less than ± 05 LSB, a one
count change in the digital result means that the input
voltage changed at most 1.5 LSB (1 LSB ideal ± 0.5
LSB DNL). This is a much more accurate description
of the input voltage change than would be available if
the differential non-linearity of the converter was not
known.
6-201
inter
AP-406
r---y-----------------
7
I
I
--:
FULL SCALE ERROR
I
I
6
5
ABSOLUTE ERROR
2
_.
r-
I
I
I
I
I
I
r-'I"""------.......
I
I
--',I
I
I
O~--~~,-------._------r_------r_------r_------r_--r_--r_----__.
1/2
2
3
4
5
6
61/2
7
8
INPUT VOLTAGE (LSBs)
270365-4
Figure 4. Actual and Ideal Characteristics
,,
Q
Q
,
Large Non-Unearlty
Differential Errors are small
Overall Linearity Is good
(a)
(b)
270365-5
270365-6
Figure 5. TYDes of Linearity Errors
6-202
Ap·406
Non-Linearity is the worst case deviation of code transitions from the corresponding code transitions of the
Ideal Characteristic. Non- Linearity describes how
much Differential Non-Linearities could add to produce an overall maximum departure from a linear characteristic.
If the Differential Non-Linearity errors are large
enough, it is possible for an AID converter to miss
codes or exhibit non-monotonicity. Neither behavior is
desirable in a closed-loop system. A converter has no
missed codes if there exists for each output code a
unique input voltage range that produces that code
only. A converter is monotonic if every subsequent
code change represents an input voltage change in the
same direction. Figure 6a shows a converter with
missed codes. Figure 6b shows a non-monotonic converter.
Differential Non-Linearity and Non-Linearity are
quantified by measuring the Terminal Based Linearity
Errors. A Terminal Based Characteristic results when
an Actual Characteristic is shifted and scaled to eliminate zero offset and full-scale error (see Figure 7). The
Terminal Based Characteristic is similar to the Actual
Characteristic that would be seen if zero offset and fullscale error were externally trimmed away. In practice,
this is done by using input circuits which include gain
and offset trimming. (See the Application Hints section
for more details.)
An often overlooked characteristic of AID converters
is that code transitions do not really occur instantaneously at some finite set of input voltages. Specific
code transitions can be analyzed by doing repeated conversions around the transition point using a high accuracy input voltage. When this is done, we find that
there is actually a range of voltages around code transitions where both the lower and upper codes occur for
repeated conversions on the same input voltage.
Figure 8 shows this "repeatability" error. At the lower
end of the region of repeatability error the lower code is '
most prevalent, but the upper code will occur in a small
percentage of the conversion attempts. As the input
voltage increases slightly, a point is reached where both
lower and upper codes occur with 50 percent probability. As the input voltage moves slightly higher, the upper code occurs most often with the lower code showing up in a small percentage of conversions.
The repeatability error is due to the fundamental ability
of the comparator in the AID to resolve very similar
voltages. Random noise also contributes to repeatability errors. On MCS-96 devices, the width of the region
of repeatability error has been found to be typically 1
mY to 1.25 mY. Since this error is specified, all other
errors are specified assuming the code transitions occur
at the voltage where adjacent codes are equally likely.
Q=3
:~~
7
6
5
Q
4
3
2
-lr
REPEATABILITY
,\.50%
POINT
Q=O~~--~~--~-------
iLSB
liLSB
*SB
0
VIN
(a)
Missed Codes
270365-10
270365-7
Figure S'. Repeatability Error
7
6
The Multiplexer
5
Q
4
3
2
1
0
(b)
Non·Monotonic
270365-8
Figure 6. Undesirable Converter Operation
. 6-203
The eight channel multiplexer is implemented as a collection of eight MOS switches. Only one of eight can be
closed at any instant in time. Figure 1 shows the multiplexer with the switches acting as resistors when closed
and as small parasitic capacitors when open. The input
protection devices on the analog input pins are also
considered a part of the multiplexer.
AP-406
IDEAL FULL-SCALE CODE
TRANSITION
5
4
Q
3
k---j
NON-LINEARITY
2
ACTUAL FIRST TRANSIfION
IDEAL FIRST TRANSITION
O~....~-.~~==~==~==~------.------,-------.---.---.------~
1/2
2
4
3
5
6
INPUT VOLTAGE (LSBs)
61/2· 7
8
270365-9
Figure 7. Terminal Based Characteristic
The resistance of a closed switch is typically lK to 2K
ohms and the D.C. leakage due to the input protection
is typically 3 microamps maximum. Both values depend upon the process used and day-to-day fabrication
variations. The channel resistance and the D.C. leakage
can also vary from channel-to-channel on the same device. These variations can be seen in the conversion
process and are described by the channel- to-channel
matching specification.
externally cancel. Fortunately, multiplexer channels
typically match to within onc millivolt.
Channel-to-channel matching specifies the input voltage differences induced by mismatched elements of the
multiplexer. This error is quantified by measuring the
difference between the input voltages necessary to cause
the same code transition to occur through different
multiplexer channels under identical test conditions.
In addition to Break-Before-Make channel selection, an
analog multiplexer must be able to keep deselected
channels isolated from the selected channel. 'As shown
in Figure 1, there are parasitic capacitances coupling
every deselected channel to the. multiplexer output. The
quantification of coupling is called Off-Isolation. Offisolation is the multiplexer'S ability to attenuate signals
on deselected channels.
Matching errors are more complex than a simple voltage offset between channels, and thus are difficult to
A multiplexer that has the potential to short two inputs
together is not very attractive. To keep this from happening, the circuitry that selects the' active channel is
designed to guarantee that all channels are deselected
before a new channel is selected. Thus, the multiplexer
is said to be Break-Before-Make.
6-204"
AP-406
Sample-and-Hold
The sample-and-hold of an analog acquisition system
can be built using an analog switch and a sample capacitor. As with the multiplexer, there is also a parasitic
capacitance coupling the switch input to the sample
capacitor when the switch is open (Figure I).
v
The resistance of the sample-and-hold switch combines
with the series resistance of the multiplexer to impede
the current necessary to charge the sample capacitor.
For example, with a 5K ohm total input resistance
from the pin to the 2 pf sample capacitor, the RC time
constant is 10 nS (2 pf X 5K ohms).
During the one microsecond that the sample capacitor
is connected to the input, 100 time constants elapse
(I microsecond/lO nS). This means that the sample capacitor is 100 percent of the voltage on the input pin
(I-e -100), assuming a zero source impedance.
If a source impedance of 2K ohms is assumed, the RC
time constant of the sampling process would be 14nS
(7K ohms X 2 pt). Thus, 71.4 time constants would
pass in one microsecond resulting in the sample capacitor being charged to within 99.9 percent of its final
value. Source impedances above 2K ohms would begin
to degrade the conversion accuracy due to D.C. leakage
(described later).
Figure 9 shows the actual input voltage and the sampled voltage approaching the input voltage. Once the
sample-and-hold switch closes, the sample window begins. The sample window extends for four state times
and ends with the sample-and-hold switch opening on
MCS-96 devices (except 8X9X-90, which is8 state
times and has no sample-hold). Figure 9 also shows the
sample delay, which is the delay from the time a start
conversion signal is generated to the time a conversion
process begins.
It is important to understand the uncertainties associated with the timing of the sample-and-hold. Digital signal processing algorithms rely upon the "spectral purity" of the sampling process. If the sample window
jumps around with respect to the start conversion signal, or if the start conversion signal cannot be generated at precise times, consecutive samples of input data
will not be equally spaced in time (i.e. sampling will be
spectrally impure).
270365-11
Figure 9. Sample-and-Hold Voltage
To improve the spectral purity of the sampling in digital signal processing applications, sequential MCS-96
start conversion signals can be generated with less than
50 nanoseconds of jitter using the HSO unit. The sample delay and sample time are also a constant number
of state times to within 50 nanoseconds each.
Once the sample window closes, it is desired that all
further changes on any input channel be isolated from
the sample capacitor. The multiplexer's off-isolation is
responsible for isolating deselected channels, while the
sample-and-hold switch must attenuate changes on the
selected channel. This source of error is described as
Feedthrough. Feedthrough is quantified as the ability
ofthe sample-and-hold to reject unwanted signals on its
input.
Other factors that affect a real AID Converter system
include sensitivity to temperature. Temperature sensitivities are described by the change in typical specifications with a change in temperature.
The MCS®-96 Conversion Sequence
The MCS-96 Analog Acquisition System includes an
eight channel analog multiplexer, sample-and-hold circuit and lO-bit analog to digital converter (Figure 10).
An MCS-96 device can therefore select one of eight
analog inputs, sample-and-hold the input voltage and
convert the voltage into a digital value. Each conversion takes 22 microseconds (8097BH), including the
time required for the sample-hold (with XTALl = 12
MHz). The method of conversion is successive approximation.
6-205
inter
AP-406
VREf .
8 TO 1
ANALOG
MULTIPLEXER
SAMPLE
AND
HOLD
CHANNEL
START
CONVERSION
HSO COMMAND "f"
270365-33
NOTE:
1.
Sample and hold not on 8X9X-90 devices.
Figure 10. AID Converter Block Diagram
The conversion process is initiated by the execution of
HSO command OFH, or by writing a one to the GO
Bit in the AID Control Register. Either activity causes
a start conversion signal to be sent to AID control logic. If an HSO command was used, the conversion process will begin when Timer 1 increments. This aids
applications attempting to approach spectrally pure
sampling, since successive samples spaced by equal
Timer I delays will occur with a variance of about
±50 ns (assuming a stable clock on XTALl). However, conversion initiated by writing a one to the
ADCON register GO Bit will start within three state
times after the instruction has completed execution, resulting in a variance of about 0.75 /Ls (XTALI
12 MHz).
Once the AID unit receives a start conversion signal,
there is a one state time delay before sampling (sample
delay) while the successive approximation register is reset and the proper multiplexer channe(is selected. After the sample delay, the multiplexer output is cOnnected to the saniple capacitor and remains connected for
four state times (sample time). After this four state time
"sample window" closes, the input to the sample capacitor is disconnected from the multiplexer so that changes on the input pin will not alter the stored charge while
the conversion is in progress. The sample delay and
sample time uncertainties are each approximately ± 50
ns, independent of clock speed.
To perform the actual analog-to-digital conversion the
MCS-96 implements a successive approximation algorigthm. The converter hardware consists of a 256-resistor ladder, a comparator, coupling capacitors and a 10bit successivc approximation register (SAR) with logic
that guides the process. The resistor ladder provides 20
mV steps (VREF = 5.12V), while capacitive coupling is
used to create 5 mV steps within the 20 mV ladder
voltages. Therefore, 1024 internal reference voltages are
available for comparison against the analog input to
generate a 10- bit conversion result. Appendix B contains a detailed description of the method used to generate 1024 voltages from a 256-resistor chain.
The total number of state times required for a 10-bit
conversion varies from one MCS-96 version to the next.
Attempting to short-cycle the lO-bit conversion process
by reading AID results before the done bit is set may
work on some versions of MCS-96 devices, however it
is not recommended. Short-cycling is not tested, nor is
it guaranteed. Furthermore, it may not work on future
MCS-96 devices.
6-206
intJ
AP-406
APPLICATION HINTS
The analog signals that must be converted by an analog
acquisition system vary widely. The analog input may
arrive at the controller as a voltage or current. The
range may be 0 to 1 volt or ± 30 volts, or some other
arbitrary range. The input may be linear, logarithmic,
non- linear, or perturbated in some bizarre fashion. Although interfacing to such signals could be considered
an art form, some simple suggestions are contained in
this section.
Analog Inputs
The external interface circuitry to an analog input is
highly dependent upon the application, and can impact
converter characteristics. In the external circuit's design, important factors such as input pin leakage, sample capacitor size and multiplexer series resistance from
the input pin to the sample capacitor must be considered.
270365-31
Figure 11. Idealized AID Sampling Circuitry
VREF
01
ANALOG
FROM USER CIRCUIT>-....--~Iv--+-a INPUT PIN
02
ANGNO
270365-32
Figure 12. Suggested A/Qlnput Circuit
For the 8096BH, these factors are idealized in Figure
11. The external input circuit must be able to charge a
sample capacitor (Cs) through a series of resistance
(RI) to an accurate voltage given a D.C. leakage (Id.
On the 8096BH, Cs is around 2 pF, RI is around 5 K.o.
and IL is specified at 3 ,...A maximum. In determining
the source impedance RS, VBIAS is not important.
External circuits' with source impedances of I .K.o. or
less will be able to maintain an input voltage within a
tolerance of about ±0.61 LSB (1.0 K.o. X 3.0 ,...A =
3.0 mY) given the D.C. leakage. Source impedances
above 2 K.o. can result in an external error of at least
one LSB due to the voltage drop caused by the 3 ,...A
leakage. In addition, source impedances above 25 K.o.
may degrade converter accuracy as a result of the internal sample capacitor not 'being fully charged during the
1 ,...S (12 MHz clock) sample window.
Placing an external capacitor on each analog input will
reduce the sensitivity to noise, as the capacitor combines with source resistance in the external circuit to
form a low-pass filter. In practice, one should include a
small series resistance prior to an external low leakage
capacitor on the analog input pin and choose the largest
capacitor value practical, given the frequency of the
signal being converted. This provides a low-pass filter
on the input, while the resistor will also limit input
current during over-voltage conditions.
Figure 12 shows a simple analog interface circuit based
upon the discussion above. The circuit in the figure also
provides limited protection against over-voltage conditions on the analog input (limits to 2.6 rnA with 270.0.
(0.7/270)). The circuit induces leakage from the diodes,
which should be kept small.
The wide range of possible analog environ!l1ents that
must be interfaced to, or the existence of stringent accuracy requirements, makes the consideration of alternative input buffer configurations necessary. The most
popular input buffer is a single op-amp in the non- in. verting or inverting configurations of Figure 13.
In the npn-inverting circuit of Figure 13 (a), the analog
input is scaled by the buffer gain to output 5 volts when
the input is at its maximum positive input. When the
buffer input is 0 volts, the output will also be 0 volts.
In the inverting circuit of Figure 13 (b), a reference
equal to the maximum possible input voltage is placed
on the non-inverting input of the op-amp and the actual
analog input is placed on the inverting input. The output voltage of the buffer is then proportional to the
deviation of analog input from its maximum possible
value. For example, when the analog input equals
VMAX, the buffer output will equal 0 zero volts. When
the analog input equals its minimum value, the buffer
output equals 5 volts. The digital result from the AID
converter might, of course, have to be complemented
before being used.
The circuits of Figure 13 show only feedback resistors
that set the gain of the buffer. In practice, it will often
be necessary to include offset adjustments, gain irimming, temperature or frequency stability compensation,
or components to build an active filter.
Figure 14 depicts a generalized non-inverting input
buffer that offsets the analog input and scales the input
6-207
inter
AP·406
to a 5 volt range. The course offset is set by the ratio of
RBIGI and RBIG2, while offset fine tuning is done by
adjusting RTRIM. The course gain is set by the ratio of
RGI and RG2 while gain trimming is done with
RoTRIM·
>-........W\t1-£~ANALOG 'PIN
-= ANGND
>+-+JVl.fv-+-+JVl.fv-
A
LSDII:
1
double Inloftix. dxl
float xII. drl I:
{
dooble POI II :
return IxlOl + (dx(O) I 2.01 - 0.5
A
LSBI:
I
double
IIBIOU Ix.
drl
270365-A7
Listing C1. Error Formulas
6-221
inter
AP-406
flolt Ill. dlll;
(
, double pawn:
returD 11(0) • (dlIO) / 2.01 - 0.5
* LSI I ;
}
double typlse(l. dll
1100t III, dIll:
I
doable peI'l I :
r.turD (.IFef1 - (.,ow.I'ec I
(l.s * LSIJl);
double 11II'Se'l. dll
flOit III. dIll:
I
doable povo:
return ((1(FCf1 • (dllFCfI / Z.Oll I
doullle wl.el •• dl I
1100t III. dill:
I
double peI.n:
return ((rlFetl
I
t
- (1.5
* LSIIII:
(dllFeT) / 2.011 - (aov.a,ec - (l.5
* LSIIII:
lat xlbllrrorll. dr. dd. Itlrt. stop)
f10lt Irl. dlr). ddll:
unll9fted lDt Itlrt. stop:
'R~.I'ec
/* tra.UUon ablolute error */
(
double pawl). 'absO;
IDt 1, .orst;
for /I : .orlt : ltart; 1 C: Itop; Itt I
I
ddUl : xIII - {(doublel 1 • u.sl * LSI:
if ft.bl(ddUlI ) fabslddl,otltll I
fOrst: 1:
,
retarD "orst I:
lnt iilliiriOrdi(i, III. dd. start, itOPI 1* truutlOi ilIlOlute error
flOit II I. dill. ddIJ;
UDSIgnd lat stert. Itop:
"~ds
*/
{
double
IRt I,
double
tor /1
por(J. fibs II ;
fOut;
tI. tZ:
: fOrst: start; I C: stop; U+I
{
tl • 'III I
. {dllll I 2.01/ - (lldooblel I + 0.51 t LSI I;
tz : (rUI + (drill I 2.0)) - (((double, .1 + o,sl t LSII;
If Iflblltll ) labsltZ))
ddltl : tl: .
els. ddll) = tZ;
11 Ulbs(ddUJI ) fabllddl,orst III
,orst : I; .
retura (fOrlt):
I
270365-A8
Listing C1. Error Formulas (Continued)
6-222
inter
AP·406
,I
Int tbnonllnll, dl, dd, start, stopl
tb nonlin USing I only *1
float III. dIll. ddll:
unsigned Int start, stop:
I
Int I, lorst:
double POlO. typzoffll, typfsell. fabsll:
double oadj. qadj:
Old.! • typZOftll, dll:
qadj = 1.0 f I(tvpfsell, dr) - oadj) / Iistopll:
for
(1 •
,orst = start: I (= stop: 1++1
I
dd(l) = 11(1) - oad,1I I qadJ - ([(double) I + MJ
if (fabsldd(lJI ) fabs(ddl,orstJlI
,orst = I:
* LSI):
return I,orstl:
)
tnt tbnonl1lldl(l. dl, dd, start, stoP) 1* tb non lin uSing
float III. dl! J, ddlJ:
unsigned Int start, stop:
I
'
Int 1, ,orst:
double po'O, typ.olt/l, typl180, lab. 0 :
dooble oadJ, qad.l. tl, t2:
O&dj • typlOffil. dll:
qadJ • 1.0 + ((typfs'(I, drl - oadJJ /11.topll:
Listing C1. Error Formulas (Continued)
6-223
I
and dl *1
270365-A9
intJ
. Ap·406
for 11 • IOrst • ltart: 1 c· Itop; 1++1
(
*
t1 • 11[11 - Idlll) , 2.01 - oadJl q.dJ - I(ldoUblel I • o,sl
t2 = 11(1) t (dllIl , 2.0) - oadj I ' gadJ - IIldoublel I t O.S)
* UBI:
* WI:
if /f.bllUl ) f'.'lt21)
4411) • ti:
else d4{H = t2:
1f (flblidd[l11 ) t.blldd[rorstlll
rorat • I;
I
returD (rorat I:
)
,'*
lnt Idalil.dI. dd •• t.rt. atop I
flOit
xII.
dIll. dd[):
ullag I only *1
lat lurt. stop;
,I
lat 1. IOrst;
double polO. tabs II :
~l. Old,. qadj:
dOalll. typt.. lI. typlOtfO:
014.1 • typiOff (I, dll:
t ((typflell,
91d, • 1.0
dI. - oadjl 1 II.topll:
rorat •• tlrt:
If (Stlrt •• 01
(
4410J • 0.0;
for
(I
atart.. ;
I
• atart: 1
(=
stop; lUI
(
dd(1) • (1[11 - oadj)
* 9adJ
- (1[1 - 11 - oa4jl
* !JIdJ
- US:
it /fabsl44UII ) fabl(ddirorstlll,
IOrst • I;
retora Irorst I;
I
lnt zdnldzl,. CI, lid. stert, :tcpl
float II), dill. 44(1:
lnt Itart, atop;
/' DUn; : ==d d:
*'
(
lit I, IOrst:
double porll. fab.():
4oub.!e tl. t2:
doublll OIdj. gadj;
doBIIle
tYpioff II:
tr,f..",
OId,1 • typBoffll. dll;
!JIdJ, = 1.0 f lItyp... II, dll - OIdj) ,llltopll:
IOrst = .tart;
if 'atart,·· ,01
(
44[OJ • dl[OI I 2.0:
270365-80
listing C1. Error Formulas (Continued)
6-224
inter
AP-406
starlH:
I
for ii : start: t
(=
stop: 1++1
I
tl : Ix(1J - (dl(1) , 2.01 - oadJ) t gadj
-IX(1 - 11 + (dl(1 - IJ 12.0) - oadJI t Qad.1
- LSB:
t2 : (x[1) • (dx(IJ , Z.OI - oadj\ t gadj
-(1[1 - IJ - (dl[1 - 1) I 2.0) - oadjl * ~adj
- LSB:
.
if (fab.(tll ) fabs(t2)l
ddll) : tI:
else dd( 1) : t2:
If (fabsldd(111 ) tab.(ddl,orstJl)
,orst : I:
,
return (rorst):
'* Unds resolution
Int reslevels(I, drl
float I(). dIll:
In levels
*'
(
lot I. levels, D:
double po,ll:
levels = I:
n = Untl po'(Z. obits) - 1:
If «r(O) - (dIIOJ I 2.01 ) O.• OJ'
le,els,+ :
tor
(1 : I:
1f
I (n:
Itt I
«1/1 - 11 + (dl(l
- II , 2.011
( (1[1) - (dl[ll , 2.01 - tparl•• flne_step)1
levelstt:
return (levels I;
I
270365-81
Listing C1. Error Formulas (Continued)
6-225
infef
AP-406
APPENDIX D
SAMPLE CONVERTER DATA
The following pages include printouts describing the
performance of an 8097BH. The data shown is for one
device and is provided for illustrative purposes only.
Users should only rely upon data sheet specifications
for the exact device they are designing with.
VREF = 5.120 volts. Following Table D2 are several
error plots that describe Absolute Error, Terminalbased Non-Linearity, Differential Non-Linearity and
Repeatability for the test device code-by-code. The
y-axis in the plots is the error in volts for each code
transition, where code transitions make up the x-axis.
Table Dl summarizes many performance measures for
one converter at 25 C, 12 MHz, Vee = 5.00 volts and
Table 01. Sample Converter Data
=
Test ID
DOH
sN: 4130 (1022H)
T = 25.000000
Vee
5.000000, Avee
5.120000
Freq
12.000000
Chan.
3
States
188
Mode
OH
XO.15 1/28/87
Transition Characterization Parameter Listing
Large Step
0.001000 V
Small Step
0.000100 V
Endpoints when (1/100) are wrong
=
=
=
=
=
=
=
=
Center is 50 percent
Typical Offset Error
Maximum Offset Error
Maximum Offset Error
= -0.001923
= -0.002460
= -0.001385
-0.000566
= -0.001254
= -0.000120
=
Absolute Error (typ) 40 = 0.004157
Absolute Error (max) 40 = 0.004795
Absolute Error (min) 325 = 0.001111
Diff. Non. Lin. Error (max) 40 = 0.003747
Diff. Non. Lin. Error (min) FF = -0.001071
Term. Non. Lin. Error (max) 325 = -0.004102
Term. Non. Lin. Error (min) 40 = 0.002148
Maximum
ty Error 3Dl = 0.001875
Minimum Reliability Error 3A7 = 0.000974
Typical FS Error
Maximum FS Error
Minimum FS Error
Reliab~li
Resolution is 1024 levels.
6-226
inter
AP-406
nOSOIllte r:rror. SN ' 4(30
Ylax=
,11n=
-0.0052
+0 1_. ________ .________ 1_ _ _ _ _ .._ _ _ .
0:
I:
2:
J:
4:
5:
b:
7:
8:
9:
A:
B:
C:
D:
E:
F:
10:
II:
12:
13:
14:
IS:
16:
1'/:
IH:
19:
lAo
18:
IC:
10:
IE:
IF:
20:
21:
22:
23:
24:
7.5:
26:
27:
28:
29:
2~:
0.002460:
0.002214:
0.002257:
0.002171:
0.002597:
0.002201:
0.00~2
1
1
1
O.00233f~
, a
0.002172:
0.002579:
O.00213b:
0.002263:
0.002219:
0.0026~2:
0.002230:
0.002280:
0.002062:
0.002581:
0.002203:
0.002440:
0.002165:
0.002578:
0.002129:
0.002262:
0.002192:
0.002533:
0.002223:
0.002383:
0.002300:
0.00247:;:
0.002268:
0.002418:
0.001994:
0.002.741:
0.002392:
0.002516:
0.002392:
0.002713:
0.002588:
0.002612:
0.002299:
0.002687:
0.002580:
0.002613:
0.002424:
0.002787:
0.002487:
0.002733:
0.002246:
0.002865:
28:
2C:
2D:
2£:
2F:
30:
31: 0.002~34:
32: 0.002605:
33: 0.002155:
34: 0.002841:
270365-69
Absolute Error, SN = 4130
6-227
inter
Ap·406
inter
Ap·406
'Il:
11:
~.OOJZOJ:
G.uc.Jz:m:
'/3: 0.003201 :
7i: 0.003261 :
75: 0.002882:
16: 0.003161 :
1'/: 0.003112:
18: 0.003000:
1~: 0.002833:
lA: 0.002989:
18: 0.002932:
1C: 0.002924:
10: 0.002716:
1E: 0.002159:
1F: 0.002021:
80: 0.003422:
81: 0.003129:
82: 0.00~322:
8J: 0.003169:
84: 0.003202:
85: 0.002953:
&6: 0.0030&6:
8'/: 0.002891:
88: 0.003038:
89: 0.002446:
8A: 0.U02983:
88: 0.002623:
8e: 0.002813:
80: 0.002593:
8E: 0.002485:
OP: U.002415:
90: 0.002191 :
91: 0.002647:
92: 0.002012:
93: 0.002576:
94: 0.002662:
'IS: 0.002514:
96: 0.002111 :
'1'/: 0.002405:
98: 0.002593:
99: 0.002266:
9A: 0.002550:
98: 0.002340:
9C: 0.002412:
9D: 0.002118:
'It: 0.002303:
'IF: 0.001754:
AO: 0.002191:
AI: 0.001893:
Al: 0.002259:
AJ: 0.001986:
At: 0.002103:
AS: 0.001881:
A6: 0.002011:
A7: 0.001933:
A8: 0.002059:
A9: 0.001792:
AA: 0.001961:
A8: 0.001776:
AC: 0.001864:
270365-71
Absolute Error, SN = 4130 (Continued)
6-229
inter
AP-406
AD:
AI:
Af:
80:
II:
88:
0.001592:
0.001781:
0.001538:
0.001906:
0.001724:
0.001887:
0.001773:
0.001585:
0.001598:
0.001650:
0.001554:
0.001'115:
B9:
0.0015.~:
12:
"B3:
84,
85:
86:
87:
t
BA: 0.001653:
B8:
Be:
BD:
BE:
Bf:
CO:
Cl:
r.2:
el:
C4:
C5:
C6:
C7:
C8:
C9:
CAl
CB:
cc:
CD:
CE:
CF:
00:
DI:
02:
03:
O~:
D5:
06:
D7:
88:
D9:
DA:
PB:
DC:
DD:
DE:
OF:
£0:
E1:
E2:
13:
E4:
£5:
£6:
£7:
£8:
t
O,00147C:
0.001467:
0.001384:
0.001588:
0.001028:
0.003214:
0.0029U:
0.002966:
0.0027'19:
0.003087:
0.002717:
0.003096:
0.002806:
0.003030:
0.002796:
0.002642:
0.002885:
0.003040:
0.002719:
0.002878:
0.002742:
0.002845:
0,002546:
0.002790:
0.002395:
0.002848:
0.002487:
0.002768:
0.002700:
0.00l681:
0.002617:
0.002755:
0.0026U:
0.1102684:
0.002398:
0.002553:
0.002223:
0.002463:
0.001878:
0.002t39:
0.002206:
0.002083:
0.002055:
0.002288:
0.002144:
0.002356:
t
t
t
t
"t
t
t
270365-72
Absolute Error, SN
=
6-230
4130 (Continued)
intJ
AP-406
E9: 0.00U2S,
EA: 0.002263,
EB: 0.002IlJ,
•
*
Be: 0.002233,
ED, 0.0021'12:
EE: 0.002369,
RF: 0.002149:
FO, 0.002216,
F1, 0.001841:
F2, 0.002051:
Fl, 0.001935,Ft: 0.00196S:
FS: 0.001729:
Jl6: 0.oom9:
F7: 0.001899:
F8: 0.001S89:
F9: 0.001718:
FA: O.00193~:
FB: 0.001756:
FC: 0.001975:
FD: 0.001832:
FE: 0.001920:
FF: 0.001041:
100: 0.002291.
101: 0.002008:
102, 0.002296:
103: 0.001975,
104: 0.001946:
105: 0.001874,
tOr.. 0.001884,
107: 0.001817,
108: 0.00213~:
109: 0.001921 :
lOA: 0.002009:
lOB: 0.001832:
IOC: 0.001903:
100: 0.001694:
lOB: 0.001838:
10F: 0.001537:
110: 0.001681:
III: 0.001436:
112: 0.001730:
113: 0.001631:
114: 0.001636:
115: 0.001374:
116, 0.001550:
117: 0.001500:
118: 0.001~30:
119: O.OOlm:
HA: 0.001390:
llB: 0.001Z7l:
lie: 0.001321:
liD: 0.001074:
liE: 0.001268:
lIF: 0.0008ltl
120: 0.001401:
121: 0.001052:
122: 0.001193:
123: 0.001106:
124: 0.001253:
•
*
•
*
*
*
•
*
.*
*
*
*
*
*
Absolute Error, SN = 4130 (Continued)
6-231
*
*
*
27(}365-73
AP-406
125:
126:
121:
128:
129:
12A:
121:
12C:
128:
121:
12F:
130:
131:
132:
133:
134:
135:
136:
137:
138:
139:
13A:
138:
IX:
13D:
13£:
13F:
-140:
lUI
14?:
143:
Itt:
145:
Ub,
147:
148:
149:
HA:
I4B:
He:
I4D:
14£:
UP:
150:
lSI:
152:
1S3:
154:
155:
151>:
1~7:
158:
159:
15A:
158:
15C:
15D:
lSi:
ISF:
160:
0.000758:
0.000953:
0.000976:
0.001080:
0.000937:
0.001181:
0.001018:
0.000959:
0.000862:
0.000812:
0.000813:
0.000933:
0.000671:
0.000811:
0.000634:
0.000929:
-0.0006n:
0.000888:
0.000539:
0.00102·/:
a
a
t
t
t-
a
•t
.-at
•
0.000~50:
0.000749:
0.000809:
0.001032:
0.000788:
0.000963:
-0.000681:
0.002218:
0.002186:
0.002327:
0.002196:
0.002447:
0.002267:
0.002435:
0.002385:
0.002554:
0.002284:
0.002420:
0.002482:
0.002523:
0.002299:
0.002303:
0.002097:
0.002267:
0.002127:
0.002312:
0.002092:
0.002264:
0.00197&:
0.0020341
0.002084:
0.002235:
0.001959:
0.002071:
0.002048:
0.002104:
0.001998:
0.002110:
0.001935:
0.002075:
t
t
t
•
t
t
t
t
270365-74
Absolute Error, SN
=
6-232
4130 (Continued)
inter
AP-406
161:
162:
163:
164:
165:
166:
WI:
168:
169:
16A:
16B:
16C:
16n:
16£:
16F:
170:
171:
172:
173:
174:
]75:
176:
177:
178:
179:
17A:
17B:
17C:
17D:
17£:
I7F:
160:
181:
162:
163:
18t:
165:
186:
187:
188:
lR9:
16A:
lUB:
18C:
160:
18E:
16P:
190:
191:
192:
193:
194:
195:
196:
197:
196:
199:
19A:
19B:
19C:
0.001'155:
O.00IQ22:
0.001706:
0.001984:
O.OOURl:
0.001630:
0.001612:
0.001967:
0.001880:
0.002022:
0.001736:
0.00)073:
0.001595:
0.001620:
0.001649:
0.001770:
0.0014Q2:
0.001635:
0.00m2:
0.001725:
0.001534:
0.001601 :
0.001527:
0.001743:
0.001443:
0.001623:
0.001576:
0.001528:
0.001386:
0.001466:
0.00B57:
0.001971:
0.001741 :
0.001616:
0.001707:
0.001694:
0.001598:
0.001600:
O.00U96:
0.001771:
0.001478:
0.001654:
0.001591 :
0.001732:
0.001404:
0.001536:
0.001411 :
0.001811:
0.001467:
0.001372:
0.001370:
0.001323:
0.001306:
0.00H29:
0.001025:
0.001565:
0.001281 :
0.001465:
0.001323:
0.001540:
t
t
270365-75
Absolute Error, SN = 4130 (Continued)
6-233
AP-406
19b,
191,
19F,
lAO,
IAI,
tA2,
!A3,
lAt,
1A~,
'1A6,
lA7,
lA8,
lA9,
lA':
lAB:
lAC,
1AD,
IAR:
IAF:
IBO:
181:
182:
lBa:
IB4:
lBS:
186:
181:
188:
189:
114:
188:
lac:
IBO:
18E:
18F:
lCO:
ICI:
'le2:
IC3:
ICI:
ICS:
IC6:
le7:
1C8:
IC9:
leA:'
lca:
ICC:
ICD:
ICE:
ICF:
IDO,
101:
102:
103:
IDI:
105:
106:
107:
188:
0.001262'
0.001245,
0.001201,
0.001413,
0.001170,
0.001361:
0.001321,
0.001181,
0.000872,
0.001086:
0.001080,
0.001195,
0.001138:
0.001204:
0.001230:
0.001210:
0.000971:
0.001083:
0.001274,
0.001211:
0.001133:
0.001069:
0.001095:
•
•
•
t
•t
•t
•
•
0.00106~:
0.001081:
0.001124:
0.001019:
0.001010:
0.001081:
0.001183,
0.001291:
0.001124:
0.00100f>:
0.001016:
0.001061:
0.002"5,
0.0023581
0.002538:
0.002151:
0.002112:
0.002415:
0.002579:
0.0024:16:
0.002796:
0.002388:
0.002368:
0.002426:
0.002661:
0.002162:
0.002497:
0.002396:
0.002617:
0.002399:
0.002503:
0.002153:
0.002623:
0.002411:
0.002123:
0.002190:
0.002606:
•
•
•t
•t
t
•
•t
270365-76
Absolute Error, SN
=
6-234
4130 (Continued)
intJ
AP·406
ID9: 0.002351 :
0.002439:
lOB: 0.002382:
IDC: U.002426:
100: 0.002376:
IDE: 0.002H3:
lOP: O.002!>31:
lEO: 0.002583:
1£1: 0.002038:
112: 0.0023?l:
IE3: 0.002043:
1E4: 0.002350:
1£5: 0.002166:
116: 0.002351 :
187: 0.002363:
11:8: 0.00245~:
1£9: 0.002002:
lEA: 0.002299:
IEB: 0.002lf6:
lEe: 0.0022'19:
1£0: 0.002072:
1E£: 0.001960:
IEF: 0.002221 :
1PO: 0.002314:
IPI: 0.001940:
IP2: 0.002086:
lFl: 0.002310:
IF4: 0.002188:
IPS: 0.002075:
IF6: 0.002065:
IF7: 0.002267:
IF8: 0.002187:
IP9: 0.002002,
lFA: 0.002120:
IF8: 0.002133:
IFC: 0.002158,
IPD, 0.001937:
'IF£: 0.002079:
IFF: 0.001409:
200: 0.001819:
2ul: 0.001707:
202: 0.0019U5:
l03: 0.001557:
204: 0.001650,
l05: 0.001661:
206: 0.001683:
207: 0.001595:
208: 0.001535:
209: 0.0011'19:
20A: 0.001610,
208: 0.001454:
lOCI 0.001370:
ZOO: 0.001262:
20E: 0.001179:
lOF: 0.000983:
210: 0.001405:
211: 0.001014:
212: 0.001168:
213: 0.001193:
214: 0.001420:
10<1:
I
I
•
I
*
•
I
I
I
I
I
I'
I
I
I
I
I
I
I
I
•
*
*t
*t
t
*
t
t
270365-77
Absolute Error, SN = 4130 (Continued)
6-235
intJ
AP-406
215:
216:
217:
U8:
219:
2U:
1.18:
21e:
21D:
21£:
ZIP:
220:
221 :
222:
223:
224:
225:
226:'
221:
228:
229:
220\:
228:
22C:
22D:
221:
22P:
230:
l~l :
..
0.001162:
0.001323:
0.001268:
0.001296:
0.001147:
0.001036:
0.001170:
0.001551:
0.001065:
0.001216:
0.000666:
t.
t .
O.OOllOh
0.000988:
0.001207:
0.001066:
,0.001079.
0.001029:
0.000971:
0.000968.
0.001203:
0.000949:
0.001026:
a.OOIOM:
0.00lU8:
0.000887:
0.001149.
0.000738:
0.001214:
0.000920:
0.001203:
0.000978:
0.001203.'
0.001081:
0.001003:
0.001053:
0.001235:
0.000705:
0.001066:
0.000924:
0.001087:'
0.001000:
0.001006:
-0.000785:
0.002137:
0.001968:
0.002196:
0.002027:
0.002162:
0.001918:
0.002075:
0.001871:
0.002060:
0.002108:
0.002100:
0.002060:
0.002217:
t
t
.•
t
,
.'•
232:
233:
234:
235.
236:
237:
238:
239:
230\:
238:
2le:
2311:
231:
23P:
240:
m:
242:
243:
2U:
245:
246:
247:
248:
249:
2fA:
241:
24e:
2tD: 0.00203~:
24B: 0.00224~1
2U: 0.002190:
250: 0.002US:
•
t
t
t
t
t
•
270365-78
Absolute Error, SN
=
6-236
4130 (Continued)
AP-406
l~l:
0.002013:
252:
253:
254:
255:
256:
257:
258:
259:
25A:
258:
2!.r.:
25D:
0.0022~9:
2~E:
25P:
260:
261:
262:
263:
264:
265:
266:
2~'1:
2681
269:
26A:
268:
26C:
26D:
26£:
26F:
270:
211:
272:
273:
27(:
275:
276:
277:
278:
279:
27A:
271:
27C,
270:
271:
27f:
280:
281:
282,
283:
284:
285:
286:
287:
288:
289:
28A:
288:
28C:
0.002068:
0.002310:
0.002213:
0.0023IC:
0.002201:
0.002259:
0.002090:
0.001956:
0.002095:
0.002377:
0.002086:
0.002090:
0.001912:
0.002137:
0.001808:
0.002027.:
0.0019":
0.002053:
0.001856:
0.0020t2:
0.001940:
0.002020:
0.001762:
0.001820:
0.001?73:
0.001850:
0.001685:
0.001910:
0.00179(:
0.00m8:
0.001653:
0.001632:
0.0015(01
0.001677:
0.001356:
0.001582:
0.001630:
0.001505:
0.001403:
0.001464:
0.OOU02:
0.001620:
0.001106:
a.OOH37:
0.001276:
0.001913:
0.001950:
0.002095:
0.001620:
0•.0020%:
0.001850:
0.001951:
0.001836:
0.001726:
0.001690:
0.001743:
0.001775:
0.001551:
t
t
t
•
•
•
t
t
t
t
t
t
t
"
270365-79
Absolute Error, SN
=
6-237
4130 (Continued)
AP-406
28D:
281:
28F:
290.
291:
292:
293:
294:
2951
196:
297:
298:
299:
2%:
291:
29C1
29B:
29~:
29F.
ZAOI
2A1:
2A2:
U3:
U4:
US:
Z0\6.
U'l:
ZA8:
2A9:
UAI
lAB.
lAC:
lAB:
2A£:
UP:
210.
281:
Z8Z:
,283:
Z84:
liS:
286:
2B'I:
Z18:
Z19:
lIlA:
2B'1
ZBC:
ZBD:
ZI£:
1.8F:
ZCO:
2ci:
zez:
2C3:
ZCt,
ZC5:
2U:
aC7:
ZC8:
0.0016l.0:
0.001~99:
0.0015361
0.001558:
0.OOHZ31
o.oum:
0.0012SS:
0.001423:
O.OOllSl:
0.001336:
0.001311:
0.001308:
0.001125:
0.001060:
0.001131:
0.001Z09:
0.000856:
0.001095:
0.000190:
0.000988:
0.000839:
0.001122:
0.000913:
0.000971:
0.000710:
0.000819.
0.000801:
0.001102:
0.000120:
-0.000620:
0.000799:
0.000991:
0.000127:
0.000684:
0.000683:
0.000713:
-0.000782:
0.000601:
-0.00070':
0.00OM7:
-0.000815:
-0.000685:
-0.099716:
0.000688:
-O.OOO'lM:
-0.000661:
-0.000781:
0.000904:
0.000707:
0.000763:
0.000844:
0.0022":
0.001988:
0.002117:
0.0020051
0.002275:
O.OOZl831
0.002092:
0.00Z171:
0.002366:
t
t
-,
,
,
I
I
I
I
t
t
*
t
t
t·
t
t
t
Absolute Error, SN
=
6-238
4130 (Continued)
•
270365-80
inter
AP-406
2e9:
leA:
lCD:
0.002105:
0.002047:
0.002142:
lec: 0.002308:
lCD: 0.002226:
lCE:
2Cf:
200:
201:
202:
203:
2D4:
2D5:
206:
207:
208:
209:
20A:
208:
ZDC:
200:
2bE:
2DF:
2EO:
2£1:
2E2:
0.002106:
0.001931:
0.002296:
0.001963:
0.002106:
0.002014:
O.OOZl36:
0.001849:
0.002152:
0.002205:
0.002087:
0.001866:
0.002304:
0.002234:
0.002308:
0.001769:
0.002155:
0.002034:
0.001801:
0.001788:
0.001813:
•t
,
f
f
I
I
t
I
•
L£3: 0.001724:
2E4:
2E5:
2£6:
2£1:
2£8:
2£9:
2EA:
2£8:
2EC:
0.001537:
0.001622:
0.001797:
0.001799:
0.001720:
0.001537:
0.001715:
0.001385:
0.001687:
2BD: O.OOU64:
2EE:
0.001508:
UF: 0.001373:
2FU:
2FI:
2F2:
0.001488:
0.001379:
0.001508:
2E3: 0.001325:
2Fi: O.001J8~:
2P5:
7.F6:
2F7:
2F8:
2P9:
2FA:
lfD:
2FC,
lPD:
2PE:
2PF:
300:
30) :
302:
303:
0.001225:
0.001381:
0.001301:
O.OOH68:
0.001136:
0.001032,
0.000957:
0.001102:
t
~.001088,
..•
0.000999:
0.001571:
0.001484:
0.001278:
0.001463:
0.001298:
30.: 0.001282:
270365-81
Absolute Error, SN
=
4130 (Continued)
6-239
inter
AP-406
305:
J06:
307:
308:
JU9:
lOA:
30B:
30C:
30D:
30£:
30F:
310:
311:
312:
313:
314:
liS:
316:
317:
318:
319:
314:
JIB:
l1C:
31D:
31£:
llF:
320:
321:
322:
323:
324:
325:
326:
327:
328:
329:
32A:
328:
32e,
:120:
32E:
32F:
330,
331:
332:
333:
334:
J35:
33&:
337:
338:
339:
. 33A:
338:
3lC:
330:
33E:
l3F:
340:
t '
0.001267:
0.OUI311:
0.001154:
0.001373:
0.001001:
0.001208:
0.001134:
0.001258:
0.001135:
0.001168:
0.000971:
0.001021:
0.000689:
0.0009'10:
0.000857:
0.000944:
0.000651:
0.000'/94:
0.000744:
0.000790:
0.000702:
0.000724: '
0.000613:
0.000823:
0.000691 :
V.000789:
-0.000870:
-0.000695:
-0.000923:
-0.000784:
-0.000845:
-0.000707:
-0.001111:
-0.000776:
-0.0009'11:
-0.000893:
t
t
-0.0010~9:
-0.000888:
-0.00/001:
0.001505:
0.001350:
0.001438:
0.001358:
0.001612:
0.001368:
0.001645:
0.001482:
0.001753:
. 0.001664:
0.001732:
0.001582: ,
0.00161.1:
0.001472:
0.OOI4n:
0.001522:
0.001102:
0.001311:
0.001545:
0.001281:
0.002%0:
t
t
t'
270365-82
Absolute Error, SN
=
6-240
4130 (Continued)
inter
AP-406
341: 0,002109:
342: 0.00l828:
343: 0.002~42:
344: 0.002'/84:
345: 0.002119:
346: 0.002590:
347: 0.002811:
348: 0.003014:
349: 0.003003:
lU: 0.002713:
34B: 0.0027U:
34C: 0.003031:
340: 0.002672:
34E: 0.00285t:
34F: 0.0029061
350: 0.002960:
351: 0.002142:
352: 0.002836:
353: 0.002754:
354: 0.003072:
355: 0.002821:
356: 0.003011:
357: 0.003037:
358: 0.002763:
359: 0.002649:
35.\: 0.002595:
358: 0.002113:
J~: 0.002'/93:
350: 0.002419:
35£. 0.002709:
35F: 0.002716:
3&0: 0.002505:
361: 0.002437:
362: 0.002451:
363: 0.002320:
364: 0.002UB:
365: ·0.002264:
366: 0.002315:
;167: 0.002312:
368: 0.002421:
369: 0.002251:
364: 0.002330:
36B: 0.002212:
l6C: 0.002269:
360: 0.001925:
36£: 0.002158:
36F: 0.002229:
370: 0.002246:
J7l: 0.001929:
372: 0.002095:
313: 0.002046:
374: 0.002085:
315: 0.001816:
376: 0.001926:
311: 0.002039:
.378: 0.001961:
379: 0.001932:
31A: Q.002019:
318: 0.001950:
31C: 0.001922:
•
•
•
*
•
*
*t
*.
t
*
•
I
..
*t
'
*.
I
,,,
,,
I
,
I
270365-83
Absolute Error, SN
=
6-241
4130 (Continued)
intJ
AP-406
370,
31£:
:11F:
380:
381:
382:
383:
384:
385:
386:
387:
388:
389:
38A:
38B:
J8C:
380:
38£:
38F:
390:
39t:
392':
393:
394:
395:
396:
397:
398:
399:
39A:
398:
39C:
390:
3'1£:
39F,
0.001815,
0.001689:
0.002200:
0.00206':
0.00176':
0.00t910:
0.001945:
0.00l'113:
0.0018661
0.001889:
0.001800:
0.001'179:
0.001.454:
0.00158':
O.ODun:
0.001469:
0.001268:
0.001562:
0.001268:
O.OOt568:
0.000946:
0.ODH2l:
0.001232:
0.00lf99:
0.001255:
0.001087:
0.001265:
0.001421:
0.001169:
0.OD126'1:
0.0012n:
0.001440:
0.001153:
0.00H02:
0.001260:
3AO: 0.001363:
t
•
•
•
3AI: O.OOlUS:
342:
3A3:
3A4:
3A5:'
3A6:
3A7:
lA8:
3A9:
3U:
JAB:
3AC:
3ADI
0.001221:
0.0011551
0.001452:
0.001302:
0.001138:
0.001079:
0.001378:
0.001043:
0.001145:
0.001207:
0.001161:
0.001133:
3AB: 0.001137:
3AF:
3BO:
J81:
3821
383:
384:
385:
386:
387:
388:
0.001l7S:
0.001159:
0.000747:
0.000927:
0.000883:
0.OOJll1:
0.000784:
0.001002:
0.0010581
0.000907:
270365-84
Absolute Error, SN = 4130 (Continued)
6-242
AP-406
389.
3BA.
3aB.
lllC.
380.
liE:
J8'.
XO:
JC1:
JC2.
le3:
Xi.
3C5:
3C6:
3C7.
le8.
lt9:
leA:
•
0.OO075l.
O.OOO9U.
0.000972.
0.000949.
0.000972:
0.000996.
0.001226:
0.001%3:
0.001554.
0.00180i.
0.001950.
0.002170,
0.001896:
0.002087.
0.001877.
0.00ll83:
0.0020U:
0.002163:
0.00203b:
0.002131:
O.OOZOI1.
0.001908.
0.001909.
•
•
•
JCB.
3CC.
3CD.
lCI:
lC'.
300: o.oozm.
301. 0.002189.
302. 0.00198b:
3D3: 0.001811.
3M: 0.001939:
305. 0.001809.
306. 0.001920.
JD7. 0.001776:
300: 0.00206b:
309. 0.00116i.
3DA: 0.00187••
30B: 0.001881.
3DC: 0.00I9t2:
3DD. 0.001808.
3DE: 0.001838.
3DP. 0.001993.
3£0. 0;001739:
3EI. 0.001112.
312: 0.001616:
3£3, 0.001576.
3U. 0.001812.
3E5. 0.001652.
J£6. 0.001872.
3£7. 0.001730.
J£8. 0.001548.
3E9: 0.001693.
JEA. 0.001857.
J£B. 0.001638.
3EC. 0.001738.
JED: 0.001581:
JEI. O.ODIS79:
3£F. 0.001780.
lPO. 0.00U51:
3P1. O.OOlm.
3FZ. 0.0013fZ.
J.3. 0.00U39.
3Ft. 0.001508:
3F5. 0.001163.
3'6. O.OOI3U:
3P7: O.OOllfO:
J'8. 0.001373.
In. 0.001098.
3'A. 0.001106.
lFB. 0.OOI2iS.
3FC: 0.001320:
3'0. 0.00108••
lPE: 0.0012Sf:
JF'. 0.000000.
•
•
•
•
•
•
•
•
•
•
270365-85
270365-86
Absolute Error, SN
=:'
6-243
4130 (Continued)
inter
AP-406
_on. Lin. Error. SI • t130
'liD"
,
-0.0037,
0:
1:
2:
3:
4:
5:
6:
7:
8:
9:
AI
8:
c:
D:
I:
P:
10:
11:
12:
13:
14:
151
16:
17:
18:
19:
IA:
11:
lC:
10:
,IE:
IF:
20:
ll:
22:
231
24:
25:
ZI"
27:
28:
29:
2A:
21:
le:
2D:
21:
2F:
30:
31:
32:
33:
341
'----
-0.000000:
-0.000291:
-0.000256:
-0.000343:
0.000031:
-0.000266: .
-0.000134:
-0.000397:
0.000007:
-0.000386:
-0.000210:
-0.000256:
0.000075:
-0.000247:
-0.000194):
-0.000f68:
-0.0000001
-0.000330:
-0.000094:
-0.000320:
0.000040:
-0.000f09:
-0.000277:
-0.000349:
-0.000009:
-0.000270:
-0.000112:
-0.000296:
-0.0001Z4:
-0.000281:
-0.000132:
-0.000607:
0.000137:
-0.000162:
-0.000039:
-0.000215:
0.000104:
0.000028:
0.000000:
-0.000313:
0.000123:
-0.000085:
0.000056:
-0.00DIt3:
0.000217:
-0.000083:
0.000061:
-0.000276:
0.000290:
0.000008:
0.000078:
-0.000323:
11.000211:
• 0-
YlII-
,
0.0037
,
I I
*
I
I I
I,
,
,
,
,
,
,
,,,
,
,
,
I,
I
,I
I
I ,
I
*1
I
I
I
I,
I
I,
I
I,
I
,I
I ,
I ,
'*
,,I
I
II
,I
I ,
, I
*1
'*
* I
I I
,1*
I*
270365-30
Non. Lin. Error, SN = 4130
6-244
inter
AP-406
35:
36:
'37:
38:
39:
3r:
40.
fl.
42.
43.
H:
45:
'6:
47:
48:
49:
fA:
fB:
-U.000065:
0.000165:
-0.000106:
0.000409:
0.000186:
0.000398:
0.000166:
0.000368:
0.000287:
0.000513.
-0.000275:
0.00m7.
0.001651.
0.001983:
0.001184.
0.001994:
0.001478.
0.001922:
0.001617:
0.001910:
0.001616:
0.001833:
0.001621:
4e:
0.001812:
4D:
4E:
4F:
50:
51:
52:
53:
Sf:
55:
56:
57:
58:
59.
5A:
58:
5C:
SD.
SE:
SF.
60:
61.
62:
63:
M:
65:
66:
67.
68:
69.
6A:
6B:
6C.
60:
6E:
tiF.
101
0.00I!l85:
0.001771:
0.001392:
0.001900:
0.001682:
0.001571:
0.00U98:
0.001755:
0.001485:
0.0015":
0.001455:
0.00IM1:
0.001382.
0.001604.
0.00U89.
0.001650.
0.001323.
0.001536:
0.000952:
0.001437:
0.001163.
0.001365.
0.001156:
0.001275:
0.000971:
0.001141.
0.000923:
0.000960:
0.000603.
0.000797.
0.000806:
0.000928:
0.000589:
0.000793:
0.000592.
0.000798.
3A:
3B:
3C:
30:
3£:
*','
,
,, *
"
II •
I •
,
• I
I
I
I
I
I
I
I
I
,
I
I
I
I
,
I
I
I
*
I
II
I
I
•
,
I
I
•
*
•
*
.'
*,
270365-34
Non. Lin. Error, SN
= 4130 (Continued)
6-245
intJ
AP-406
'1\,
0.nOUU2:
72,
O.OOO~16,
13,
0.000531:
U.000616:
0.000216:
0.000493,
0.000393,
0.000330,
0.0001ll ,
0.000216:
0.000158,
0.000148:
-0.000060:
0.000081,
-0.000601:
0.000691 :
0.000H7:
0.000588:
0.000434:
0.000566:
0.000265:
0.000397:
0.000157,
0.0003%,
-0.0001%:
0.000339:
-0.000021:
0.000166:
-0.000104:
-0.000163:
-0.000285:
0.000089:
-0.000055:
0.000057:
-0.000129:
0.000025:
-0.000194:
-0.000048:
-0.000255:
-0.000119:
-0.000"5,
-0.000214:
-0.000376:
-0.000305:
-0.000650,
-0.000467:
-0.000%7:
-0.000481:
-0.000830:
-0.000416:
-0.000790:
'0.000574:
-0.000848:
-0.000709:
-0.000898:
-0.000774:
-0.000892:
-0;000768:
-0.000911,
-0.000824:
74,
15:
16:
11,
18,
'19,
"A:
78:
7C:
7D:
7£:
7P:
80:
81:
82,
83:
84:
8~:
86:
87,
8&,
89,
84:
8B:
8C:
8D,
8E:
8F:
90:
91:
92:
93:
94:
95:
96,
97,
98,
9Q:
9A:
98:
'It:
9D:
9R:
9F:
AO:
AI,
A2:
43:
At:
45:
A6:
47:
48:
49:
AA:
AI:
AC:
,
I
I
,,,.
I·
I •
I •
I '
.,
,
I·
I'
I
I
,,
,I •
.,
I •
I
I
I •
, I
"
,
t
'*
*'
'*
*'
*,
, *',
.*',,,,
*
,
,
,,
,,,
,,
,,
,,
I
I
I
270365-35
Non. Lin. Error, SN
= 4130 (Continued)
6-246
. inter
AP-406
AD,
AE,
AF:
SO,
B1,
H2:
83,
84:
85,
86:
B7:
B8:
89:
8A:
BB:
Be:
BD:
BE:
OF:
co:
Cl:
C2:
C3:
-0.001097,
-0.000960:
-0.001154,
-0.000787,
-0.001021,
-0.000909,
-0.0010U,
-0.001064:
-0.001152,
-0.0010S1:
-0.001199:
-0.001089:
-0.001260:
-0.00110t:
'0.001284:
-0.00IZ42:
-0.001376:
-0.001114:
-0.001735:
0.000398:
0.000097:
0.000248:
0.000109:
*
*
*
*
*t
't
, *
,*
C4:
0.000316:
,
t
C5:
C6:
Cl:
C8:
C9:
CA:
. CD:
CC:
CD:
CE:
CP:
DO:
DJ,
02:
D3:
Df:
05:
06:
07:
08:
09:
DA:
DB:
DC:
00:
DE:
DP:
EO:
-0.000054:
0.000322:
-0.000018:
0.000254:
0.000018:
-0.000086:
0.000005:
0.000208:
-0.000113:
0.000094:
-0.000093:
0.000058:
-0.000191:
-0.000049:
-0.0004f5:
0.000056:
-0.000306:
0.000023:
-0.000145:
-0.000116:
-0.000231:
-0.000044:
-0.000158:
-0.000168:
-0.000455:
-0.000301:
-0.000633:
-0.000324:
-0.000830:
-0.000421:
-0.000605:
-0.000729:
-0.000709:
-0.000527:
-0.000672:
-0.000462:
*',
*
£1:
E2:
E3:
Ee:
IS:
16:
£'/,
E8:
, *
*', *
*',*
*,
,*
*,
*',
,*
* ,
*,
*
*
270365-36
Non. Lin. Error, SN
= 4130 (Continued)
6-247
AP-406
£9: -U.000694:
EA: -O.0005~7:
BB: -0.000709:
. t
EC: -O.OOOMO:
ED: -0.000752:
BE: -o.ooom:
EF: -0.000728:
FO: -0.000612:
Fl: -0.000989:
F2: -0.000780:
F3: -0.0009":
U: -0.000868:
F5: -0.001156:
F6: -0.000807:
P7: -0.001038:
F8: -0.001200:
F9: -0.001222:
FA: -0.000956:
FB: -0.001087:
FC: -0.000919:
PDt -0.001063:
FB: -0.000977:
FF: -0.001857:
100: -0.000509:
101: -0.000"3:
102: -0.000b06:
103: -0.000828:
104: -0.000859:
105: -0.000982:
106: -0.000913:
101: -0.001042:
108: -0.000775:
109: -0.001040:
lOA: -0.000904:
. 108: -0.000982:
IOC: -0.000912:
100: -0.001113:
10£: -0.001030:
10Ft -0.001382:
UO: -0.001240:
111: -0.001386:
112: -0.001093:
113: -0.001244:
114: -0.001240:
115: -0.001503:
116: -0.001328:
117: -0.001480:
118: -0.001401:
U9: -0.001521:
lIA: -O.OOU94:
IlB: -0.001614:
11C: -0.001565:
liD: -0.0018U:
liE: -0.001621:
1lF: -0.002076:
120: -O.ooIMI:
121: -0.001841:
122: -0.001701:
123: -0.001790:
124: -0.0016":
•t
t
•
t
•
•t
270365-37
Non. Lin. Error, SN = 4130 (Continued)
6-248
AP-406
125:
126:
127:
128:
129:
12A:
128:
IlC:
12D:
12K:
12F:
130:
131:
132:
133:
134:
135:
136:
137:
138:
139:
13A:
138:
13C:
13D:
138:
13F:
140:
141:
141.:
143:
144:
145:
146:
147:
146:
lt9:
14A:
148:
14C:
140:
I4E:
14F:
150:
151:
152:
153:
J54:
ISS:
156:
157:
1~8:
159:
15A:
158:
15C:
150:
15E:
15F:
160:
-0.002140:
-0.0019~6:
-0.001915:
-0.001172:
-0.001961:
-O.OOl1H:
-0.001888:
-0.001946:
-0.002097:
-0.0020~8:
-0.002148:
-0.001960:
-0.002243:
-0.002054:
-0.002233:
-0.002039:
-0.002342:
-0.002083:
-0.002333:
-0.0018%:
-0.002125:
-0.002177:
-0.007.166:
-0.001897:
-0.002142:
-0.002018:
-0.00U90:
-0.000666:
-0.000100:
-0.000560:
-0.000692:
-0.000493:
-0.000724:
-0.000607:
-0.000659:
-0.000441:
-0.000112:
-0.000518:
-0.000511:
-0.000527:
-0.000753:
-0.000650:
-0.000857:
-0.000686:
-0.000880:
-0.000146:
-0.000911:
-0.000747:
-0.000986:
-0.000929:
-0.000931:
-0.000131:
-0.001008:
-0.000898:
-0.000912:
-0.000867:
-0.001075:
-0.000914:
-0.001140:
-0.001002:
270365-38
Non. Lin. Error, SN = 4130 (Continued)
6-249
inter
AP-406
161: -0.001273:
162: -0.001057:
163: -0.00127~:
164: -0.OOI0te:
16~: -0.001~2:
166:
167:
166:
169:
16A:
168:
16«::
16D:
161:
16F:
110:
171:
172:
113:
174:
115:
116:
177:
178:
179:
l1A:
178:
J7C:
170:
11£:
1":
180:
181:
182:
183:
184:
1851
186:
181:
188:
189:
18A:
18B:
18C:
18D:
18E:
18':
)qU:.
191:
192:
193:
194:
195:
196:
191:
198:
199:
19A:
19B:
lile:
-0.001155:
-0.001274:
-0.001100:
-0.001259:
-0.000966:
-0.001205:
-0.001110:
-O.00lf49:
-0.001315:
-0.0013471
-0.001218:
-0.001551:
-0.001365:
-0.001430:
-0.001328:
-0.001520:
-0.001455:
-0.001480:
-0.001315:
-0.001617:
-0.001338:
-0.00148t:
-O.OOlt86:
-0.001619:
t
t
t.
-0.001~0:
-0.001611:
-0.001098:
-0.0013791
-0.001306:
-0.001366:
-0.001230:
-0.001418:
-0.001377:
-0.001480:
-0.001309:
-0.001553:
-0.001378:
-0.00U931
-0.001353:
"0.001682:
-0.001502:
-0.001618:
-0.001229:
-0.001624:
-0.001671:
-0.001674:
-0.001672:
-0.001841:
-0.001669:
-0.00202.:
-0.001466:
-0.001871:
-0.001688:
-0.001182:
-0.OOI5I1i:
Non. Lin. Error, SN
=
4130 (Continued)
6-250
intJ
AP-406
190:
19£:
19F:
lAO:
lAI:
!A2:
IA3:
IU:
IA5:
1A6:
1A1:
U8:
IA9:
IAA:
lAB:
lAC:
lAD:
IA£:
JAF:
IBO:
lSI:
182:
183:
IBf:
185:
186:
187:
188:
189:
18A:
18B:
IBC:
IDD:
18£:
IBF:
ICO:
ICI:
le2:
IC3:
IC4:
ICS:
IC6:
IC7:
IC8:
IC9:
leA:
lCD:
ICC:
ICD:
ICE:
ICF:
lDO:
101:
102:
103:
lD4:
105:
106:
ID1:
108:
-0.OOI~45:
-O'.OOIBM:
-0.001909:
-0.001698:
-0.001943:
-0.001803:
-0.001894:
-0.001936:
-0.002146:
-0.001983:
-0.002040:
-0.00181'/:
-0.002035:
-0.001921:
-0.001896:
-0.001861:
-0.002108:
-0.001997:
-0.001807:
-0.001822:
-0.002051:
-0.001916:
-0.001991:
-0.001913:
-0.002108:
-0.002067:
-0.002013:
-0.002053:
-0.002113:
-0.001913:
-0.001950:
-0.001974:
-0.002IU:
-0.002055:
-0.0020fl:
-0.000629:
-0.OOOH7:
-0.000569:
-0.000101:
-0.000'97:
-0.000746:
-0.000533:
-U.000677:
-0.000fJ9:
-0.000728:
-0.000699:
-0.000643:
-0.000509:
-0.000159:
-0.000676:
-U.000618:
-0.000508:
-0.000178:
-0.000675:
-0.000126:
-0.000558:
-0.000768:
-0.0001bO:
-0.000645:
-0.000580:
*
*
270365-40
Non. Lin_ Error, SN
=
4130 (Continued)
6-251
AP-406
109:
IDA:
lDB:
IDe:
1001
ID£:
IDF:
1£0:
1£1:
lE2:
lE3:
1£4:
l£S:
116:
117:
lE8:
l£c/:
lEAl
18B:
lEe:
lED:
1££:
IBF:
If0:
IPl:
IF2:
1J13:
1Ft:
IF5:
IF6:
1F7:
IF8:
IP9:
IF41
1FB:
IFC:
IFD:
IFE:
II'F:
200:
201:
202:
203:
204:
20b:
206:
207:
208:
209:
20A:
20B:
zoc:
20D:
20B:
20F:
210:
211:
Z12:
213:
2U:
-0.000836:
-0.000750:
-0.000753:
-0.000715:
-0.000816:
-0.000'/01:
-0.0007141
-0.0006631
-0.001060:
-0.000828:
-0.001107:
-o.oooaOl:
-0.001037:
-0.000803:
-0.000843:
-0.000702:
-0.001156:
-0.000861:
-0.000965:
-0.000933:
-0.00IU2:
-0.001205:
-0.000995:
-0.000954:
-0.001179:
-0.001084:
-0.001061:
-0.001035:
-0.001099:
-O.OOllllr
-0.000960:
-0.000991:
-0.001178:
-0.001061:
-0.001099:
-0.001026:
-0.00IZ48:
-0.001157:
-0.001828:
-0.001360:
-0.001533:
-0.001386:
-0.001636:
-0.001536:
-0.001584:
-O.oOlm:
-0.001703:
-0.001714:
-0.002021:
-0.001592:
-0.001799:
-0.0018841
-0.0019941
-0.002028:
-0.002225:
-0.001805:
-O.OOZI37:
-0.001994:
-0.002071:
-0.001795:
..
t
t
•
t
270365-41
Non. Lin. Error, S~ = 4130 (Continued)
6-252
AP-406
215:
216,
211:
218:
219:
2lA:
2lB:
21C:
21D:
21E:
21P:
220:
221:
222:
223:
22.:
225:
226:
227:
228:
229:
-0.002104:
-0.00IQ'5:
-0.002001:
*
*
-0.001911:
-0.002115:
-0.002187:
-0.00210':
-0.001125:
-0.002212:
-0.002012:
-0.002564:
-0.002021:
-0.002294:
-0.002127:
-0.002269:
-0.002157:
-0.002308:
-0.002268:
-0.002372:
-0.002039:
-0.0023":
*
2U:· -0.002218:
22B:
22C:
22D:
221:
22F:
-0.00~463:
230:
231:
232:
233:
234:
235:
-0.002088:
-0.002333:
-0.002052:
-0.002328:
-0.002104:
-0.002278:
-0.002357:
-0.002259:
-0.002078:
-0.002559:
-0.002199:
-0.002343:
-0.U02181:
-0.002369:
-0.002265:
-0.002833:
-0.001181:
-0.001357:
-0.001130:
-0.001301:
-0.001167,
-0.001462:
-O.OOllS·/:
-0.OUW2:
-0.00122':
-0.001278:
-0.001181:
-0.001278:
-0.001023:
-0.001256:
-0.00Ia7:
-0.001204:
-0.000930:
2361
237:
238:
239:
23A:
238:
23C:
23D:
23£:
23F:
240:
241:
242:
243:
244:
245:
246,
247:
2.8:
249:
2fA:
248:
2fC:
2tD:
24E:
24P:
250:
*
-O.0022U:
-0.002179:
-0.002361:
-0.002101'
I
I
I
I
I
I
I
I
I
I
I
I
.I
I
I
I
I
I
I
I
*
*
t'
t
t
270365-42
Non. Lin. Error, SN
= 4130 (Continued)
6-253
intJ
AP-406
m,
252:
253:
2M:
255,
256:
,257:
258:
259:
2Si:
2511:
25C:
25D:
25E:
25F:
260:
261:
262:
263:
264:
265:
266:
267:
268:
269:
26A:
261:
26C:
260:
261:
26F:
270:
?,il;
272:
273:
274:
275:
276:
217:
278:
279:
27.:
27.:
27C:
278:
271:
27F:
280:
281:
282:
283:
284:
285:
286:
287:
2~:
289:
28.:
288.
28C:
-0_001283:
-0.001008:
-0.001281:
-0.000930: '
-0.001188:
-0.001039:
-0.001147:
-0.001096:
-0.001217:
-0.001302:
-0.0012H:
-0.0010114:
-0.001276:
-0.001213:
-0.001343:
-0.001229:
-0.001509:
-0.001297:
-0.OOH26:
-0.001318:
-0.001517:
-0.001282:
-0.00.,85:
-0.00i35?:
-0.001616:
-0.001509:
-0.001558:
-0.001582:
-0.001748:
-0.001524:
-0.001692:
-0.001589:
-0.001186:
-0.001108:
-0.001751:
-0.001716:
-0.001988:
-0.001813:
-0.001816:
-0.001943:
-0.002046:
-0.001936:
-0.002000:
-0.001783.
-0.002248:
-0.001869:
-0.002131:
-O.OOU96:
t
•
t
t
r
t
t
•
I
I
I
t
t
t
t
-o.oomo:
-0.00131":
-0.001792:
-0.001318:
-0.001615:
-0.0014&5:
-0.001632:
-0.001643.
-0.001730:
-0.001629:
-0.001698:
-0.001823:
t
t
270365-43
Non. Lin. Error, SN = 4,130 (Continued)
6-254
inter
AP-406
28B: -0.001855:
28E: -0.001118:
28P: -0.001942:
290: -0.00t871:
291: -0.002008:
292: -0.001945:
293: -o.ooms:
294: -0.001962:
295: -0.002235:
296: -0.002101:
297: -0.002178:
298: -0.002132:
299: -0.002366:
29A: -0.002433:
298: -0.002360:
29C: -0.002236:
29B: -0. 0025tl:
29E: -0.002403:
29P: -0.002609:
2AO: -0.002413:
ZAI: -0.002563:
2A2: -0.002381:
2A3: -0.002542:
214: -0.0024351
2A5: -0.002697:
2A6: -0.002530:
2A7: -0.002653:
?.A8: -0.002459:
2A9: -0.002742:
2AA: -0.002860:
2AB: -0.002666:
- 2AC: -0.002525:
2AD: -0.002741:
ZAB: -0.002'185:
ZAP: -0.002737:
280: -0.002709:
281: -0.003031:
2B2: -0.002823:
283: -0.002906:
2B4: -0.002780:
285: -0.0030J9:
286: -0.002941:
287: -0.002923:
288: -0.002794:
289: -0.002973:
2BA: -0.002872:
288: -0.0029t3:
2BC: -0.002!>84:
280: -0.002832:
28E, -0.002777,
28P, -0.002698:
2CO: -0.001295:
2Cl: -0.0015571
2C2: -0.001429:
2C3: -0.001542:
lC4: -0.001274:
*
*
*I
t
t
lC5: -0.001417:
2C6: -0.001409:
2C7: -0.001382:
2C8: -0.0011381
270365-44
Non. Lin. Error, SN
=
4130 (Continued)
6-255
intJ
AP-406
lCq,
2eA,
2C8,
2CC:
2CO:
lCE,
ZCP:
200,
201:
202:
203:
20C:
205:
206:
207:
208:
209:
lOA:
208:
2OC:
200:
2DB:
lOP:
2EO:
2SI:
2E2:
283:
2£4:
285:
2£6:
287:
2£8:
2E9:
2EA:
2E8:
2BC:
2ED:
2BB:
2EF:
2FO:
2n:
21'2:
2P3:
2Ft:
2F5:
2F6:
2P7:
2F8:
2F9:
2FA:
21'8:
2FC:
21'0:
2FK:
2PF:
300:
301:
302:
303:
30(:
-0.001450,
-0.001(09,
-0.001366,
-0.001201,
-0.001385:
-0. ooa06,
-0.001532:
-0.001166:
-0.001503:
-O.OOHIH
-0.001554:
-0.001334:
-0.001622:
-0.001370:
-0.001369:
-0.001438:
-0.001660:
-0.00132(:
-0.001395:
-0.001273:
-0.001813:
-0.00U28:
-0.001550:
-0.001685:
-0.001799:
-0.001725:.
-0.001766:
-0.001954:
-0.001920:
-0.001747:
-0.001796:
-0.001776:
-0.002011:
-0.001834:
i' .
-I
I
1
I
-0.00211~:
1
-0.001915:
-0.002089:
-0.002046:
-0.002132:
-0.002069:
-0.002229:
-0.002101:
-0.001.236:
-u.002177:
-0.002388:
-0.00226(:
-0.002315:
-0.002449:
-0.002533:
-0.002538:
-0.00256(:
-0.002411:
-0.002(86:
-0.002576:
-0.002006:
-0.00199(:
-0.002301:
-0.002168:
-0.002284:
I
I
t
t
1
·1
i
I
t
1
I
I
I
I
I
I
-0.002?~1:
270365-45
. Non. Lin. Error, SN
=
4130 (Continued)
6-256
AP·406
305:
306:
301:
308:
309:
30A:
30B:
30C:
JOD:
30B:
JOP:
310:
311:
312:
313:
314:
315:
316:
311:
318:
319:
3U:
31B:
lie:
310:
31E:
31F:
320:
321:
322:
323:
324:
325:
326:
321:
328:
329:
32A:
328:
32C:
32D:
32£:
32P:
330:
331:
332:
333:
334:
335:
336:
331:
338:
339:
33A:
338:
33C:
330:
331:
33F:
340:
-0.002U1:
-0.002269:
~0.002483:
-0.002265:
-0.002589:
-0.002383:
-0.002508:
-0.002336:
-0.002560:
-0.002428:
-0.002671:
-0.002528:
-0.002861:
-0.002612:
-0.002746:
-0.002710:
-0.002955:
-0.002813:
-0.002864:
-0.002770:
-0.002959:
-0.002688:
-0.002901:
-0.002742:
-0.002975:
-0.002B·18:
-0.003165:
-0.002991:
-0.003220:
-0.003083:
-0.003195:
-0.003109:
-0.003314:
-0.003130:
-0.003246:
-0.003301:
-0.003397:
-0.003241:.
-0.003362:
-0.002182:
-0.002338:
-0.002251:
-0.002332:
-0.001919:
-0.002225:
-0.002099:
-0.002164:
-0.001894:
-D.OO21M:
-0.002018:
-0.002019:
-0.001991:
-0.002182:
-0.002183:
-0.002134:
-0.002005:
-0.002338:
-0.002115:
-0.002380:
-0.000653:
t
t
270365-46
Non. Lin. Error, SN = 4130 (Continued)
6-257
AP-406
:ltl:
3.2:
343:
3ft:
3t5:
3f6:
3.7:
3f1l:
M91
3tA:
Mil
MC:
3fD:
341:
-0.001006:
-0.000888:
-0.001175:
-0. OOoeM:
-0.000951:
-0.001030:
-0.000951:
-0.000710:
-0.0006721
-0.000854:
-0.00093':
-0.00064111
-0.001008:
-0.000828:
MF:
-o.ooomi
350:
351:
352:
353:
354:
355:
3S6:
357:
358:
359:
35A:
358:
3SC:
350:
351:
35P:
360:
361:
362:
363:
364:
365:
366:
367:
368:
369:
36A:
361:
36C:
360:
361:
36f:
370:
371:
372:
373:
374:
375:
376:
377:
378:
379:
37A:
.371:
37C:
-0.00071':
-0.00099':
-0.0009011
-0.000985:
-0.000618:
-0.000920:
-0.000731:
-0.000707:
-0.000832:
-0.001017:
-0.001003:
-0.000976:
-0.000957:
-0.001273:
-0.000994:
-0.0010381
-0.001150:
-0.001320:
-0.001257:
-0.001390:
-0.001263:
-0.001498:
-0.001388:
-O.OOU53:
-0.001295:
-0.001fl6:
-0.001389:
-O.OOU98:
-0.001502:
-0.001797:
-0.001566:
-0.001596:
-0.001531:
-0.0017991
-0.001684:
-0.001735:
-0.00IM7:
-0.001857:
-0.001809:
-0.001697:
-0.0017701
-0.0019S6:
-0.001821:
-0.0018UI
-0.0018201
Non. Lin. Error, SN
•
•
•
•
..
•
•
•
•
•t
270365-47
= 4130 (Continued)
AP-406
J70:
318:
37F:
380:
381:
382:
383:
36t:
385:
3116:
387:
~88:
389:
38A:
38B:
38C:
38D:
38£:
38F:
390:
. 391:
392:
393:
394:
395:
396:
397:
398:
399:
39A:
39B:
39C:
390:
39£:
39F:
3AO:
3Al:
3A2:
3A3:
3A4:
3A5:
346:
3A7:
3A8:
3A9:
3AA:
3AB:
3AC:
3AO:
3AB:
3AF:
380:
3BI:
382:
383:
384:
385:
386:
387:
386:
-0.001979:
-0.002106:
-0.001597:
-0.00178t:
-0.002085:
-0.001840:
-0.001907:
-0.001890:
-0.001989:
-0.001867:
-0.001957:
-0.002029:
-0.002256:
-0.002177:
-0.002285:
-0.002294:
-0.002497:
-0.002204:
-0.002499:
-0.002201:
-0.002774:
-0.002398:
-0.002591:
-0.002325:
-0.002570:
-0.002590:
-0.0025J3:
-0.002409:
-0.002662:
-0.002513:
-0.002588:
-0.002345:
-0.002633:
-0.002485:
-0.002579:
-0.002427:
-0.002646:
-0.002572:
-0.002639:
-0.002393:
-0.002494:
-0.002609:
-0.002570:
-0.002522:
-0.002809:
-0.002658:
-0.002696:
-0.002645:
-0.002724:
-0.002721:
-0.002685:
-0.002752:
-0.003015:
-0.002837:
-0.002932:
-0.002689:
-0.003034:
-0.002817:
-0.002812:
-0.002965:
270365-48
Non. Lin. Error, SN
=
4130 (Continued)
6-259
AP-406
369:
3BA:
38B:
31e,
31D:
31E:
31f:
JeO:
Jel:
-O.0030'H:
-0.002884:
-0.002953:
-0.002818,
-0.002906:
-0.00218t:
-0.002605,
-0.001810,
-0.002229:
31:2: -0.001980.
3C3: -0.001986.
Jet: -0.001668:
JC5: -0.001943,
3C6: -0.001804.
3C1. -0.001915:
Je8: -0.001660.
31:9: -0.001761:
3C.1: -0.001633:
Je8: -0.001861.
3CC: -0.001768:
lCD, -0.001883:
JCE: -0.001943.
JeF. -0.0019":
300. -0.001195.
3DI: -0.001966.
302. -0.001921:
383: -0.002091:
304, -0.001910.
"3D5: -0.002102.
3»6: -0.001992:
3D?: -0.002131:
308: -0.00IM8,
309: -0.002102:
3DA: -0.001942:
3D8: -0.002081:
3De: -0.002028:
3DD: -0.0021\3,
3DE: -0.00203t:
3Df: -0.001931:
3EO: -0.002086:
3El: -0.00231t:
382: -0.002311:
3El: -0.002303:
314: -0.002068:
385: -0.002280:
386: -0.002111:
31'1: -0.002154:
318: -0.002338:
3E9: -0.0023":
3BA: -0.002181:
3EB: -0.002252:
31e, -0.002153:
3EO: -0.002361:
3R, -0.002264:
JEF: -0.002215:
3fO: -0.002U5:
3fl: -0.002536:
3f2: -0.002501:
3F3: -0.002561:
3Ft, -0.002"3,
3F5: -0.002690:
3F6: -0.OOl563:
3n: -0.002565,
3F8: -0.002533:
3F9: -0,002810:
JFA: -0.002753:
3f8: -0.002666:
3fC: -0.002592:
3FD: -0.002829:
3R: -0,002110:
"3FF: 0.000000:
•
•
•
•
•
•
•
•
•
•
•
".
270365-49
270365-50
Non. Lin. Error, SN
=
4130 (Continued)
6-260
intJ
AP-406
01[, Error. SM = 4130
Ylln=
-0,0026
?lar=
• 0 -
0.0026
1________________ , _________________-'
0: ~.OOOOOO:
I: '0.000297:
2: 0.000011:
3: -0.000081:
4: 0.000374:
~: -0.000291:
6: 0.000131:
7: -0.000263:
8: 0.00040~:
9: -0.000394:
A: 0.000I7~:
B: -0.000045:
e: 0.000331:
D: -0.000323:
E: 0.000046:
F: -0.000269:
10: 0.000467:
II: -0.000329:
12: 0.000235:
13: -0.000226:
H: 0.000361:
IS: -0.000450:
16: 0.000131:
17: -0.000011:
18: 0.000339:
19: -0.000261:
IA: 0.000158:
1B: -0.000184:
Ie: o.ooom:
10: '0.000156:
1K: 0.000U8:
t
,.
"1
1
,,,
, t
,,
I
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•
,
,,
,
It
1
,
IF: -O.OOOt7S:
20:
21:
22:
23:
24:
2S:
26:
27:
28:
29:
2A:
28:
2e:
2D:
2£:
2F:
30:
31:
32:
33:
34:
0.000745:
-0.000300:
0.000122:
-0.000115:
0.000319:
-0.000076:
'0.000021:
-0.000314:
0.000436:
-0.000208:
0.000141:
-0.000200:
0.000361:
-0.000301:
0.000144:
-0.000338:
0.000567:
-0.000282:
0.000069:
-0.000401:
0.000534:
, ,, '
1
"
,
., ,,,'
,
1
1
1'
I
I
,
,
"
I
270365-87
DNLError,SN = 4130
6-261
inter
AP-406
J~:
36:
31:
38:
39:
3A:
3B:
3C:
lD:
3£:
3P:
40:
U:
42:
fl:
tt:
15:
46:
f7:
f8:
f9:
fA:
4B:
4e:
40:
0:
4F:
50:
51:
52:
53:
54:
55:
56:
57:
58:
59:
SA:
SB:
sc:
5D:
5E:
5F:
bOo
61:
62:
&l:
64:
65:
66:
&7:
68:
69:
6A:
68:
6C:
60:
6£:
bP:
10:
I
-0.00027';:
0.000l31:
-0.000212:
I
I
O.OO~M&:
I
*
-0.000223:
0.0002U:
-0.000232:
0.000202:
-0.000081:
0.000225:
-0.000188:
0.002123:
-0.0004%:
0.000331:
-0.000199:
0.000210:
-0.000516:
0.000U3:
-0.00030f:
0.000292:
-0.00029f:
0.000211:
-0.000212:
0.000250:
-0.000286:
0.000185:
-0.000319:
0.000508:
-0.000218:
-0.000111:
-0.000012:
0.000256:
-0.000270: .
0.000109:
-0.000139:
0.000185:
-0.000258:
0.000221:
-0.000115:
0.000161:
-0.000321:
0.000212:
-0.000584:
0.000485:
-0.000274:
0.000201:
-0.000208:
0.000118:
-0.000304:
0.000110:
-0.000218:
0.000056:
-0.000176:
-0.000006:
0.000008:
0.000122:
-0.000339:
0.000203:
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DNL Error, SN
=
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4130 (Continued)
6-262
270365-88
inter
AP-406
"II: -0.U00351>:
72:
1~:
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76:
77:
78:
79:
7A:
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7r.:
7D:
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62:
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84:
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86:
87:
60:
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8A:
88:
8C:
80:
8£:
8F:
90:
91:
92:
93:
94:
95:
96:
97:
98:
99:
9A:
98:
9C:
90:
9£:
9F:
AU:
AI:
A2:
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AS:
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A7:
A8:
A9:
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0.000133:
-0.000038:
0.000076:
-O.OOOtOO:
0.000277:
-0.000100:
-0.00006);
-0.000218:
0.00010':
-0.000058:
-0.000009:
-0.000209:
O.OOOltl:
-0.000683:
0.001293:
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0.000131:
-0.000300:
0.000131:
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0.000239:
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0.000186:
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-0.000059:
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0.000374:
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0.000113:
-0.000187:
0.000154:
-0.000219:
O.000H5:
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0.000136:
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0.000230:
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O. 000070:
-0.000345:
0.000183:
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0.000485:
-0.000349:
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0.000215:
-0.000273:
0.000138:
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0.000123:
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0.000086:
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DNL Error, SN
=
4130 (Continued)
6-263
270365-89
inter
AP-406
AD:
AE:
AP:
80:
Bl:
B2:
B3:
B4:
B5:
16:
87:
88:
89:
M:
BB:
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10:
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0.000111:
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0.000100:
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0.000109:
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0.000156:
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0.000041:
-0.000134:
0.000202:
'-O.Ooo!llll:
0.002134:
-0.000301:
0.000150:
-0.000136:
0.000206:
-0.000371:
0.000377:
-0.000341:
0.000272:
-0.000235:
-0.000105:
0.000091:
0.000203:
-0.000322:
0.000207:
-0.000187:
0.000151:
-0.000250:
0.000142:
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0.000329:
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0.000029:
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DNL Error, SN
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= 4130 (Continued)
6-264
270365-90
inter
AP-406
£9:
EA:
ED:
Ee:
ED:
EE:
EF:
FO:
Fl:
F2:
F3:
F4:
F5:
F6:
F7:
Fa:
F9:
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100:
101:
102:
103:
104:
105:
106:
107:
108:
109:
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120:
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0.00013b:
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0.000195:
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0.000115:
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0.000208:
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0.000078:
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0.000348:
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0.000265:
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0.001348:
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0.000006:
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DNL Error, SN = 4130 (Continued)
6-265
270365-91
infef
AP-406
125:
121>:
127:
128:
129:
146:
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0.000193:
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156:
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158:
1591
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DNL Error, SN = 4130 (Continued)
6-266
270365-92
inter
AP-406
161:
162:
163:
164:
165:
166:
167:
168:
1&9:
16.\:
168:
16C:
16D:
16E:
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172:
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114:
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176:
171:
178:
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190:
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0.0000351
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0.000073:
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DNL Error, SN
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4130 (Continued)
6-267
270365-93
AP-406
19b: -0.000329:
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6-268
270365-94
AP·406
109:
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100:
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DNL Error, SN = 4130 (Continued)
6-269
inter
AP-406
215:
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233: -0.000276:
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238: -0.000143:
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231: 0.000104:
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DNL Error, SN = 4130 (Continued)
6-270
270365-96
AP-406
251:
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253:
254:
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256,
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II
I
21B: -0.000063:
286:
,
I,
It
I
211: 0.000035:
27C,
27D,
27£,
27;:
280:
281:
282,
283:
284,
285,
I
,,
I
0.000216,
-0.000465,
0.000379:
-0.000262:
0.000635:
I
,
t
I
I
I
-O.OOOOH:
,
I
0.000193,
-0.000476:
0.0004'14:
-0.000297,
0.000149,
-0.000166:
-0.000011:
-0.000087,
287,
288:
289:
28A: O.OOOIOli
I
I
I
I
I
II
I
28B: -0.000069:
I,
2ac: -0.000125:
• I
I
I
I
270365-97
DNL Error, SN
=
4130 (Continued)
6-271
AP-406.
28D: -0.000032:
28E: 0.000077:
, "I
I'
, I
I'
, I
28F: -0.00016':
290: 0.000010:
291: -0.000136:
292: 0.000062:
293: -0.000163:
294: 0.000166,
29~: -0.000213:
296, 0.000133:
297: -0.000076:
298, 0.00004~:
299, -0.000234,
29A: -0.000066:
29B: 0.000012:
29C: '0.000123:
290: -0.00030f:
291: 0.000131:
29F, -0.000206,
240: 0.000196:
2AI: -0.000150:
2A2: 0.000181:
2A3: -0.000160,
2U: 0.000106:
2A5: -0.000262:
2A6: 0.00016'/:
2A1: -0.000Il3:
2A8: 0.000193:
2A9: -0.000283:·
2A4: -0.000U1:
2A8: 0.000193:
2AC: 0.000140:
2AD: -0.000215:
~AH:
-O.OOOOH:
2AP:
2BO:
2BI:
282:
283:
21t:
285:
286:
2D'1:
288:
2B9:
2BA:
2BB:
2ac:
2110:
2B£:
28F:
ZCO:
2Cl:
0.000041:
0.000028:
-0.000322:
0.000207:
-0.000082:
0.00012S:
-0.000239:
0.000018:
0.000011:
0.000128:
-0.000119:
0.000101:
-0.000011:
0.000359:
-0.000248:
0.000054:
0.000019:
0.001402:
-0.000261,
I '
I
,'
"I'
I
*1
1*
, I
,
,
I •
I '
*1
"
I •
*',I '
'*
,
I '
I
I '
'I
I
I
I'
,
,' .
I'
I
2C2: 0.000121,
,
, I
2C3: -0.000113,
2ef: 0.000268:
2C5, -0.000143:
, I
2C6: 0.000007:
ZC7:
2C8:
0.000021:
0.000U3,
270365-98
DNL Error, SN = 4130 (Continued)
6-272
AP-406
2e9: -0.000312:
2eA: 0.000040:
2el: 0.000043:
2ec: 0.000164:
2CD: -0.000163:
2eE: -0.000021:
2CF: -0.000126:
200: 0.000365:
201: -0.000336:
202: 0.000091:
203: -0.000U3:
204: 0.000220:
205: -0.000288:
206: 0.000251:
201: 0.000001:
208: -0.000069:
209: -0.000222:
2DA: 0.000336:
208: -0.000071:
2OC: 0.000122:
200: -0.000540:
20E: 0.000384:
2DF: -0.000122:
2£0: -0.000l3f:
2BI: -O.OOOIU:
2H2: 0.000073:
2B3: -0.000040:
2£4: -0.000168:
215: 0.000033:
226: 0.000173:
2B7: -0.000049:
2E8: 0.000019:
2E9: -0.000234:
2EA: 0.000176:
2EB: -0.000281:
2Ee: 0.000200:
2BO: -0.000174:
2£B: 0.000042:
2EF: -0.000086:
2FO: 0.000063:
2F1: -0.000160:
2F2: 0.000127:
2F3: -0.000134:
2F4: 0.000058:
2F5: -0.000211:
2F61 0.000104:
2F7: -0.000031:
2i8: -0.000134:
2P9: -0.000083:
2FA: -0.000005:
2FB: -0. 000026:
2FC: 0.000093:
2FD: -0.000015:
2F£: -0.000090:
2FF: 0.000570:
300: 0.000011:
301: -0.000307:
3021 0.000133:
303: -0.0001l6:
J04: 0.000032:
DNL Error, SN
,
I'
I'
I
I
' I
I
I
I'
' I
I
I
I
,
,
, 'II
I
'I
I ' .
I
I
, I
, I
' I
I'
'I
I
I'
I
'I
,
,
I
I
I
I t
I
I'
'I
I'
' I
I '
' I
I'
I
I'
,
,
,
, I
'I
I'
'I
I
I
I'
' I
270365-99
= 4130 (Continued)
6-273
AP-406
JO~:
-0_000166:
0.000148:
-0.0002H:
0.000217:
-0.000323:
0.000205:
-0.000125:
0.000)72:
-0.000224:
0.000131:
-0.000246:
0.000148:
-0.000333:
0.000249:
-0.000134:
0.000035:
-O.0002U:
0.000141:
-0.0000Sl:
0.000094:
-0.000189:
0.000070:
-0.000012:
0.000153:
-0.000233:
0.000096:
-0.000286:
0.000173:
-0.000229:
0.000137:
-0.000112:
O. 000086:
325: -0.000205:
326: 0.000183:
327: -0.000116:
328: -0.0000~4:
329: -0.000096:
32A: 0.000149:
328: -O.OOOIU:
32C: 0.001180:
320: -0.000156:
32£: 0.000086:
32F: -0.000081:
330: 0.000352:
331: -0.000245:
332: 0.000125:
333: -0.000064:
334: 0.000270:
335: -O.OOOUO:
3.'11>: 0.000116:
337: -0.000001:
336: 0.000027:
339: -0.000190:
33A: -0.000001:
33B: 0.000048:
33C: 0.000126:
33D: -0.000332:
33R: 0.000222:
33F: -0.000265:
340: 0.001727:
• II
* I
306:
307:
306:
309:
30A:
30B:
30C:
30D:
30E:
JOF:
310:
311:
312:
313:
314:
315:
316:
ll7:
3J8:
319:
3Il:
31B:
lie:
310:
31E:
31F:
320:
321:
322:
323:
324:
i
*
*
*I
I *
I
I
I
• I
I •
I
I •
I
I
*I
,t
I
I
*1
1*
* I
1*
I
I
*
*
1*
I
I
*
* I
I *
*I
1*
• II
t
, I
*''I
I
*I
*
I
, I
1*
*1
I
I
I
*
I
I
I
*
*1
*
I
I·
I •
I
I
I
I
*
DNL Error, SN = 4130 (Continued)
6-274
270365-AO
inter
AP-406
341: -0.0003S2:
342: 0.000117:
343. -0.000287:
3ft: 0.000340:
345. -0.000116:
346: -0.000079:
Jt7: 0.000078:
348: 0.000241:
349: 0.000037:
lU: -0.00018\:
341: -0.000080:
341:: 0.000285:
3tO: -0.000360:
3tE: 0.000180:
34F: 0.000050:
350: 0.000002:
351: -0.000219:
352: 0.000092:
353: -0.000083:
354: 0.000366:
355: -0.000302:
356: 0.000188:
357: 0.000024:
350: -0.000125:
359: -0.000215:
35A: 0.000044:
lSI: 0.000026:
3SC: 0.000016:
350: -0.000315:
3SE: 0.000278:
3SP: -0.000044:
360: -0.000112:
361: -0.000169:
362: 0.000062!
363: -0.000132:
364: 0.000127:
365: -0.000235:
366: 0.000109:
367. -0.000064:
368: 0.000157:
369: -0.000121:
364: 0.000027:
368: -0.000109:
36C: -0.000004:
360: -0.000294:
361: 0.000231:
36F: -0.000030.
370: 0.000065:
371: -0.000268:
372: 0.000114:
373: -0.000050:
314: 0.00008'/:
375. -0.000210:
376: 0.000048:
377: 0.000111:
378: -0.000073:
379: -0.000186:
374: 0.000135:
378: -0.000020:
37C: 0.000020.
*
I
I
I
*I
*1
It
I
*
1*
I
*1
I
I
I •
1*
• I
1*
*1
I
I
I
*
*I
* I
1*
I
I
*1
*I
* I
1*
• I
I •
I
I *
*1
I
*I
•
*I
*
1*
I
I •
j.
*1
*
*
I
1*
I
*
I
I
*
*1
.*
DNL Error, SN = 4130 (Continued)
6-275
270365-Al
AP·406
31D:
37E:
37F:
380:
381:
3821
383:
384:
385:
386:
387:
388:
389:
J8A:
388:
38C:
380:
38£:
38P:
390:
391:
392:
393:
394:
395:
396:
397:
398:
399:
39A:
398:
39C:
39D:
391:
39F:
lAO:
3A1:
342:
3A3:
3U:
3A5:
3A~:
3A7:
3AS:
3A9:
3All
3AB:
3ACI
3AD:
3AI:
3AP:
380:
381:
382:
383:
384:
385:
386:
3871
3B8:
• I
-0.000158:
-0.000127:
0.UOO509:
-0.0001811
-0.000301:
0.0002":
-0.000066:
0.000016:
-0.000098:
0.000121:
-0.000090:
-0.000012:
-0.000226:
0.000078:
-0.000107:
-0.000009:
-0.000202:
0.000292:
-0.000294:
0.000298:
-0.000572:
0.000375:
-0.0001921
0.000265:
-0.000245:
-0.000019:
0.000076:
0.0001041
-0.000252:
0.000148:
-0.000015:
0.000243:
-0.000288:
0.000147:
-0.000093:
0.000151 :
-0.000219:
0.000074:
-0.000066:
0.0002451
-0.000101:
-O.OOOIH:
0.000038:
0.000041:
• I
I
* I
I
I
*1
*1
I•
'I
'I
* I
I'
*I
,
,
I
I
I
I
I
I
I
,
I
1*
I*
I
I*
*1
I
I
I*
'I
I*
•I
1*
'I
I ' .
, I
*I
1*
I'
I
~0.OOO286:
0.000150:
-0.000039:
0.0000521
·0.000079:
0.000003:
0.000036:
-0.000067:
-0.000262:
0.000178:
-0.0000951
0.0002421
-0.000344:
0.0002161
0.00000':
-0.000152:
I '
"I'
*1
*
It
"I
,
I
*1
I
I
I *
, I
270365-A2
DNL Error, SN
=
4130 (Continued)
6-276
Ap·406
,,
,'
389. -0.000106:
3&A: 0.000187.
3BB.
31C.
310:
3B£:
3BF:
:lCO:
3CI:
3C2:
:lC3:
lC4.
Je5:
3C6:
3C7:
lC8:
3C9.
-0.000069:
0.00007~.
,
-0.000028:
0.000122:
0.000178:
0.000735:
-0.000359:
0.000248:
-0.000005:
0.000318:
-0.000274:
0.000139:
-0.000111:
0.000254:
-0.000100:
31:~: 0.000127.
Jel. -0.000228:
3CC: 0.000093.
lCD: -o.ooom:
:lCB: -0.000060:
:lCP: -0.000000:
300: 0.000148.
3DI: -0.000111:
302: 0.00004~:
383: -0.000176:
304: 0.000126:
305: -0.0001311
386: 0.000109:
3D7: -o.ooom:
308: 0.000288:
389: -0.000253:
3DA: 0.000159:
3DI: -0.000145:
3OC: 0.000059:
3DD: -0.000085:
3DE: 0.000078:
3DF: 0.000103:
3EO. -0.00015~:
3EI: -0.000228:
3El: 0.000003:
313: 0.000008:
3Et: 0.000234:
315. -0.000211: '
311>: 0.000168:
31'1: -0.000043:
318: -0.000183.
3£9: -0.000005:
,
,,
,"
, ,"
"
, ,,'
,,
,,
",
,
, ,,'
,
"
I'
I'
I'
"I'
,
," "
3&A: 0.000162 •
.1EI. -0.000070,
3EC. 0.000098:
3ED: -0.000208:
3U: 0.000096:
3IF: 0.000049:
3PO; -0.000230:
3FI: -0.000091:
3F2: 0.000029.
3F3. -0.000054.
3,.: 0.000067:
3P5. -0.0001%,
3F6: 0.000126.
3F7: -0.000002:
3F8: 0.000031:
3P9: -0.000276,
3FA: 0.000056:
3F1, 0.000087:
3Fe: 0.000073.
3PD, -0.000237,
3FE: 0.000118.
3PF. 0.000000:
,
""
",
"
, ",
270365-A3
"
"
,""
"
DNL Error, SN = 4130 (Continued)
6-277
270365-M
AP-406
DJ Arrav. 51 = mo
YIln=
0.0C!107f:
0.00l175:
0.001175:
O.!IOll75:
+0 I
I
I
I
I
0.00127~:
I
~: 0.001075:
6: 0.00IP75:
71 0.001275:
8: 0.001275:
91 0.0011751
A: 0.001075:
I: 0,001075:
I
I
I
I
I
I
-0.0020
I
0:
1:
2:
3:
.:
c:
0.00127~:
YR.=
0.0020
I
• t
,
Di 0.001075:
II ~.001975:
P: 0.001175:
10: 0.001275:
11: 0.001115:
~2:
0.00117~:
.13: 1I.001~75:
14: 0.001175:
IS: 0.001175:
16: 0.001175:
17: o.OomS:
181 0.001l75:
19: 0.001075:
lA: 0.001075:
18: 0.001275:
lC: o.oom~:
ID: 0.001175:
11: 0.001175:
IF: 0.001275:
20: 0.0012751
21: 0.001175:
22: 0.001175:
23: 0.001275:
241 0.001275:
25: 0.001175:
26: 0.001275:
27: 0.001275:
28: 0.00l17~:
29: 0.001375:
U: 0.001275:
28: 0.0011751
2C: 0.001175:
21: 0.0011751
21: 0.001375:
U: 0.0010751
30: 0.001175:
31: 0.001075:
32: 0.001075:
33: 0.000975:
3.: 0.001275:
t
t
t
t
270365-51
Repeatability Error, SN = 4130
6-278
inter
Ap·406
35: 0.001175:
36: 0.001075:
37: 0.0012'15:
.~:
0.00101~:
39: 0.001275:
3A: 0.001275:
38: 0.001175:
3C: 0.001175:
3D: 0.0011'15:
3E: 0.001175:
3P: 0.001375:
40, 0.001275:
41: 0.001275:
42: 0.0010'15,
43: 0.001075,
tt: 0.001275,
45, 0.001175,
46, 0.001175:
47, 0.001075:
f8: 0.001175:
49: 0.001175:
4A: 0.001175:
4B: 0.001275:
fe: 0.001375:
40: 0.001075:
41: 0.001375:
fF: 0.001075:
50: 0.001175:
51: 0.001175:
52: 0.001115:
53: 0.000975:
54: 0.000975:
55: 0.001075:
56, 0.001175:
57: 0.001275:
58: 0.001215:
59: 0.001115:
5A: 0.001075:
58: 0.001015:
sc: 0.001275:
5D: 0.001075:
5E: 0.001175:
5F: 0.001175:
60: 0.000915:
61: 0.001015:
62: 0.001075:
63: 0.001275:
64: 0.001215:
65: 0.001075:
fill: 0.001115:
61: 0.001375:
68: 0.001075:
69: 0.001075:
6A: 0.001075:
68: 0.001175:
6C: 0.001175,
6D: 0.001175:
6£: 0.001175:
6F: 0.001075:
70: 0.001075:
.t
270365-52
Repeatability Error, SN = 4130 (Continued)
6-279
intJ
Ap·406
71: 0.001375:
12: 0.001175:
73: 0.001175:
7t: 0.001l7~:
75: 0.001175:
76: 0.001175:
77: 0.001275:
78: 0.001l75:
79: 0.00IZ75:
74: 0.001375:
78: 0.001375:
7C: 0.001375:
70: 0.001375:
7E: 0.001175:
7F: 0.001075:
80: 0.001275:
81: 0.001175:
82: 0.00IZ7~:
83: 0.001215:
84: 0.001075:
85: 0.001175:
86: 0.001175:
87: 0.001Z75:
88: 0.001075:
89: 0.001075:
8A: 0.001075:
88: 0.001075:
8C: 0.00I07~:
80: 0.001175:
8E: 0.001075:
8f: 0.001175:
90: 0.001l75:
91: 0.001175:
92: 0.0012'15:
93: 0.00U75:
94: 0.0010751
95: 0.001175:
96: 0.001275:
9'1: 0.001075:
98: 0.001175:
9'1: 0.001175:
,91.: 0.0011.75:
98: 0.OO1l7S:
9C: 0.001175:
90: 0.00IZ·15:
9E: 0.001275:
9F: 0.001175:
AD: 0.001075:
AI: 0.001175:
A2: 0.001075:
A3: 0.001275:
At: 0.001075:
AS: 0.OO1l75:
A6: 0.001275:
1.7: 0.001375:
1.8: 0.001375:
1.9: 0.001075:
AA: 0.001175:
AB: 0.001075:
AC: 0.001075:
270365-53
Repeatability Error, SN = 4130 (Continued)
6-280
AP-406
AD, 0.001075:
AB:
0.001l75:
AF:
0.00101~:
DO:
Bl:
B2:
B3:
84:
85:
B6:
81:
B8:
89:
BA:
BB:
0.001075:
0.001l15:
0.00Il15:
0.001275:
0.000915:
0.00\115:
0.001075:
0.001l15:
Be:
0.00107~:
0.00127~:
0.001215:
0.001l75:
0.001115:
BD: 0.001l7~:
BE: 0.001l1~:
DF: 0.001175:
co: 0.001275,
CI: 0.001275:
e2: 0.001015:
C3, 0.000915:
C4: 0.00117~:
C5: 0.001115:
C6: 0.001175:
C1, 0.001215:
C8: 0.001175:
C9, 0.001115:
CA, 0.001015:
CD: o.ooms:
CC: 0.00l2"l5:
CD: 0.001275:
CEo 0.001J7~:
CF: 0.001215:
DO: 0.001175:
01: 0.001075:
02: 0.001275:
03: 0.001275:
04: 0.001175:
05: 0.001175:
06: 0.001075:
07: 0.001275:
D6: 0.001175:
D9: 0.001275:
DA: 0.001115:
DB: 0.001175:
DC: 0.001275:
DO: 0.001275:
DE: 0.001275:
OF: 0.001275:
EO: 0.001115:
£1 : 0.000975:
E2: 0.001275:
E3: 0.001175:
£4: 0.001175:
£5: 0.001075:
Eb: 0.001175:
87: 0.001115:
E8: 0.001175:
270365-54
Repeatability Error, SN = 4130 (Continued)
6-281
intJ
AP-406
£9: 0.001315:
EA: 0.001175:
IB: 0.001175:
EC: 0.001075:
ED: 0.001375:
1£: 0.001375:
!iF: 0.001275:
FO: 0.001175:
Fl: 0.00m5:
F2: 0.001175:
F3: 0.001275:
F4: 0.00H7S:
PS: 0.001275:
F6: 0.001075:
F7: 0.001375:
F8: 0.00107S:
Fq: 0.001375:
FA: 0.00127S:
FB: 0.001175:
FC: 0.001275:
PO: 0.00127S:
FE: 0.001275:
FF: 0.001275:
100: 0.001075:
101: 0.001175:
102: 0.001275:
103: 0.001075:
104: 0.001075:
105: 0.001175:
106: 0.001175:
107: 0.001115:
108': 0.001215:
109: 0.001375:
IDA: 0.001275:
lOR: 0.001075:
10C: 0.001075:
100: 0.001175:
10E: 0.001l7S;
lOP: 0.00127S:
liD: 0.001215:
111: 0.0010151
112: 0.001015:
113: 0.00111S:
114: 0.00U15:
U5: 0.001175:
116: O.OOl\1S:
U'/: 0.001315:
118: 0.001275:
119: 0.001275:
llA: 0.00ll7~:
118: 0.001175:
I1C: 0.001175:
HD: 0.001175:
liE: 0.001175:
I1F: 0.001175:
120: 0.00127S:
121: 0.00117S:
122: 0.001115:
123: 0.001175:
12.: 0',001l1S:
t
t
270365-55
Repeatability Error, SN
=
6-282
4130 (Continued)
inter
AP-406
IZ5:
121>:
121:
128:
129:
12A:
128:
12C:
128:
o.onJl7~:
0.OO1l7~:
0.001275:
O.OOl07b:
0.001175:
0.001275:
0.001175:
0.001175:
0.001275:
UE: 0.001075:
12F: 0.001275:
130: 0.00117~:
lJl: 0.001175:
132: 0.001075:
133: 0.001075:
13': 0.001275:
135: 0.001275:
136: 0.001275:
137: 0.001075:
138: 0.001175:
139: 0.001275:
13A: 0.001175:
138: 0.001275:
lle: 0.0011751
13D: 0.001175:
138: 0.001275:
13F: 0.001075:
ltO: 0.001075:
HI: 0.001075:
HZ: 0.001075:
lt3: 0.001075:
Iff: O.OOU7S:
If5: 0.001275:
146: 0.001315:
141: 0.001375:
1f8: 0.001275:
1f9: 0.001275:
lU: 0.001275:
IfB: 0.001275:
IfC: 0.001375:
If0: 0.00137&:
IfE: 0.001175:
ifF: 0.001175:
lSOI 0.00U7S:
151: 0.001275:
152: 0.001375:
1531 0.001275:
154: 0.001275:
155: 0.001175:
l!i6: 0.001175:
157: 0.001Z7S:
158: 0.001175:
159: 0.0011'/5:
15A: 0.001115:158: 0.001275:
15C: 0.00111S:
ISD: 0.00Il75:
151:: 0.001275:
15F: 0.001375:
160: 0.0013'15:
270365-56
Repeatability Error, SN
=
6-283
4130 (Continued)
AP-406
161:
162:
163:
16.:
165:
166:
167:
168:
169:
IbA:
168:
16C:
16D:
16£:
16F:
110:
111:
172:
173:
11f:
175:
116:
117:
178:
119:
I1A:
178:
17C:
11D:
17F.:
I7F:
IRa:
181:
182:
163:
18f:
165:
186:
187:
168:
169:
18A:
168:
IRC:
18D:
18£:
18F:
190:
191:
192:
193:
19f:
195:
196:
197:
198:
199:
19A:
19B:
0.001275:
0.001115:
0.001175:
0.001215:
0.001175:
0.001175:
0.001315:
0.001375:
0.001415:
0.001115:
0.001075:
0.001215:
0.001215:
0.001175:
0.001115:
0.001215:
0.001215:
0.001175:
0.001175:
0.001275:
0.001215:
0.001275:
0.001115:
0.001275:
0.001215:
0.001015:
0.001275:
0.OO1l7S:
0.001275:
0.001015:
0.001215:
0.001275:
0.001315:
0.001315:
0.001215:
0.001315:
0.001215:
0.001075:
0.001075:
0.001275:
0.001175:
0.001175:
0.001275:
0.001275:
0.001215:
..
0.0011'/5:
0.001275:
0.001175:
0.001275:
0.001175:
0.001175:
0.001075.
0.001375:
0.0012'15:
0.001175:
0.0011'15:
0.001375:
0.001375:
0.001215:
19C: 0.001115:
270365-57
Repeatability Error, SN = 4130 (Continued)
6-284
inter
AP·406
190:
19£:
19F:
JAO:
1Al:
JA2:
IU:
IAt:
lAS:
JA6:
1A7:
lAB:
lA9:
tAi:
lAB:
lAC:
lAD:
IAR:
lAF:
lBO:
IBI:
IB2:
183:
184:
185:
181>:
187:
188:
IB9:
18A:
lBB:
IBC:
IBD:
181:
lBF:
ICO:
lCl:
lC2:
lC3:
le4:
lC5:
lC6:
le1:
IC6:
lC9:
ICA:
lCB:
ICC:
lCD:
ICE:
lCF:
100:
101:
102:
103:
104:
105:
106:
107:
106:
0.00Il15:
0.001275:
0.001275:
0.001275:
0.001275:
0.001375:
0.00lt15:
0.001275:
0.001015:
0.0011'15:
0.001275:
0.001115:
0.001375:
0.001275:
0.001275:
0.001175:
0.001175:
0.001175:
0.001175:
0.001075:
0.001315:
0.000915:
0.001175:
0.001075:
0.001375:
0.001375:
0.001175:
0.001175:
0.001375:
0.001l75:
0.001475:
0.001175:
0.001275:
0.00ll75:
0.001175:
0.001175:
0.001115:
0.001175:
0.001275:
0.001315:
0.001275:
0.001115:
0.001175:
0.001375:
0.001175:
0.001075:
0.001075:
0.001275:
0.001375:
0.001275:
0.001075:
0.001175:
0.001275:
0.001275:
0.001275:
0.001275:
0.001275:
0.001275:
0.001175:
0.001275:
270365-58
Repeatability Error, SN = 4130 (Continued)
6-285
inter
AP-406
109:
IDA:
1DB:
IDe:
IDD:
ID£:
18P:
lEO:
IE1:
112:
113:
lE4:
1£5:
116:
1£1:
118:
1191
lEA:
lE8:
1Eel
liD:
0.001275:
0.001275:
0.001175:
0.001175:
O.OOmf..
0.001175:
0.001375:
0.0013751
0.001075:
0.00127~:
0.001175:
0.001175:
0.0012·'5:
0.001175:
0.001275:
0.001175:
0.0011751
0.00U75:
0.001075:
0.001275:
0.001275:
lEE: 0.001115:
IIF:0.001275:
IFO: 0.001375:
IFI: 0.001075:
1F2: o.ooms:
1F3: 0.001574:
1Ft: 0.001275:
IP5: 0.001115:
IF6: 0.001175:
IF7: 0.001215:
1P8: 0.001175:
Ipg: 0.00m5:
IFA: O.001J75:
/FB: 0.001275:
1Fe: 0.001115:
IFD: 0.001175:
IFI: 0.0012751
IFF: 0.001275:
200: 0.001275:
201: 0.001375:
202: 0.001375:
203: 0.001175:
204: 0.001175:
205: 0.001275:
206: 0.001115:
207: 0.001375:
208: 0.001275:
209: 0.001175:
20A: 0.001175:
20B: 0.001275:
20C: 0.001275:
200: 0.001215:
201: 0.001175:
20P: 0.001175:
210: 0.001175:
211: 0.001115:
212: 0.001075:
213: 0.001275:
214: 0.001175:
270365-59
Repeatability Error, SN
=
6-286
4130 (Continued)
inter
AP-406
215: 0.001275:
216: 0.00127~:
211: 0.001275:
218: 0.001275:
219: 0.001375:
2U: 0.001175:
218: 0.001275:
ZIC: 0.001275:
210: 0.001215:
2IE: 0.001115:
21F: 0.001175:
220: 0.001375:
221: 0.001275:
222: 0.001375:
223: 0.001375:
224: 0.001175:
·225: 0.001375:
226: 0.001175:
227: 0.001375:
228: 0.001175:
229: 0.001275:
22A: 0.001l75:
228: 0.001275:
22C: 0.001275:
22D: 0.001175:
22£: 0.001115:
UF: 0.001075:
230: 0.001275:
231: 0.001175:
232: 0.001175:
233: 0.001275:
234: 0.001275:
235: 0.001375:
236: 0.001375:
237: 0.001275:
238: 0.001275:
239: 0.001175:
23A: 0.001115:
238: 0.001175:
23C: 0.0011'15:
230: 0.001375:
23£: 0.001175:
23F: 0.001275:
240: 0.001275:
241: 0.001275:
242: 0.001215:
243: 0.001275:
244: 0.001275:
245: 0.001375:
246: 0.001075:
247: 0.001175:
248: 0.001l75:
249: 0.001375:
l4A: 0.001175:
2U: 0.001275:
24C: 0.001075:
240: 0.001175:
24£: 0.001375:
24F: 0.0013'151
250: 0.001275:
270365-60
Repeatability Error, SN = 4130 (Continued)
6-287
AP-406
251:
252:
253:
25f:
'255:
256:
257:
258:
259:
25.:
258:
2SC:
250:
25&:
25F:
260:
261:
262:
263:
264:
265:
1.66:
267:
268:
269:
26&:
268:
26C:
260:
26&:
26F:
270:
271:
272:
273:
274:
215:
276:
7.77:
278:
279:
27A:
278:
27C:
27D:
278:
27F:
280:
281:
282:
283:
28t:
285:
286:
287:
288:
289:
28&:
28B:
20C:
0.001175:
0.001275:
0.001215:
0.001175:
0.001375:
0.001275:
0.001275:
0.001275:
0.001175:
0.001075:
0.001175:
0.001475:
0.001275:
0.~01275:
0.001175:
0.001275:
0.001175:
0.001175:
0.001275:
0.001275:
0.001275:
0.001175:
0.001375:
0.001275:
0.001275:
0.001175:
0.001l7~:
0.001375:
0.001375:
0.00137~:
0.001475:
0.001175:
0.001375:
0.001115:
0.001075:
0.001275:
0.001175:
0.001275:
0.001375:
0.001375:
0.001375:
0.001275:
0.001275:
0.001275:
0.001175:
0.001075:
0.001275:
0.001275:
0.001375:
0.00127~:
0.001275:
0.001275:
0.001375:
0.001275:
0.001375:
0.001175:
0.001275:
0.001175:
0.001375:
0.001175:
270365-61
Repeatability Error, SN = 4130 (Continued)
6-288
inter
AP-406
26D:
28B:
28P:
290:
291:
292:
293:
294:
295:
296:
297:
298:
299:
294:
29B:
29C:
29B:
29£:
29F:
2AO:
2A1:
2A2:
2A3:
2A4:
2A5:
2A6:
2A7:
2A8:
2A9:
lAA:
2AB:
2AC:
2AD:
2AB:
ZAP:
2BO:
2BI:
282:
2B3:
284:
285:
286:
287:
288:
289:
2B4:
21B:
2BC:
2BB:
2BE:
lBP:
2CO:
2CI:
2C2:
2C3:
2et:
2C5:
2C6:
0.001375:
0,001l7~:
0,001315:
0,001215:
0.001215:
0,001115:
0,001115:
0,001115:
0,001115:
0,00IZ15:
0,001315:
0,001275:
0,001375:
0,00U7S:
0,001315:
0,001275:
0.001175:
0,001375:
0,0011'15:
O.OOll7S:
0,001l75:
0,001315:
0.001275:
0.001115:
0,001175:
D.DOIl15:
0,001215:
0.001415:
0.001215:
0.001115:
0.001215:
0.001315:
0.001215:
0.001275:
0,001l15:
0.001175:
0.001l75:
0.00ll75:
0.001275:
0,0011%:
0,001215:
0,00ll75:
0,00IZ75:
0,001275:
0.001275:
0,001275:
0,001315:
0,001275:
0,001375:
0,001375:
0,001315:
0,001375:
0,001375:
0,001315:
0.001375:
0,001375:
0,OOH7S:
0,001275:
2C1: 0,001375:
2C8: 0,001275:
270365-62
Repeatability Error, SN'= 4130 (Continued)
6-289
infef
AP-406
lC9:
2CA:
2CB:
2CC:
lCO:
2eB:
2CF:
200:
·201:
202:
7.03:
204:
205:
206:
201:
208:
209:
20A:
20B:
2OC:
200:
2DE:
20F:
2EO:
ZE1:
282:
283:
2£4:
2£5:
2£6:
2E7:
2£8:
2E9:
2EA:
2ED:
2EC:
2ED:
2£E:
2iF:
lFG:
2Fl:
2F2:
2F3:
2F4,
2FS:
2F6:
2P7:
2F8:
2F9:
2FA:
2FB:
2FC:
2FD:
2FE:
2FF:
300:
301:
302:
303:
304:
0.001315:
0.001175:
0.001275:
0.001275:
0.001415:
0.001275:
0.001115:
0.00H15:
0.001115:
0.0012'/5:
0.001315:
0.001175:
0.001115:
0.001Z·/5:
0.001315:
0.001215:
0.001215:
0.001415:
0.001415:
0.001315:
0.001315:
0.001315:
0.001375:
0.001115:
0.001315:
0.001215:
0.001115:
0.001115:
0.001215:
0.001215:
0.001375:
0.001115:
0.001215:
0.001215:
0.001115:
0.001315:
0.001215:
0.001275:
0.001175:
0.001275:
0.001375:
0.001375:
0.001275:
0.001275,
0.001375:
0.001475:
0.001375:
0.001375:
0.001415:
0.001275:
0.001115:
0.001275:
0.001275:
0.001275:
0.001275:
0.001075:
0.001275:
0.001375:
0.001275:
0.001175:
t .
270365-63
Repeatability Error, SN = 4130 (Continued)
6-290
inter
Ap·406
:lOS.
JOb.
l07:
308:
309:
304:
308:
JOC:
300:
30E.
.10P:
310:
311:
312:
313:
314:
315:
316:
317:
318:
319:
31,\:
318:
31C:
310:
31E:
31F:
320:
321:
322:
323:
324:
325:
326:
32'1:
328:
329:
32A:
328:
32C:
320:
32£:
32F:
330:
331:
332:
333:
334:
335:
336:
337:
338:
339:
33'\:
338:
33C:
330:
331:
33F:
340:
0.OU1475.
0.001275.
1i-00l375:
0.001375:
0.001275:
0.001275:
0.001375:
0.001275:
0.001475:
0.001275.
0.001375:
0.001)75:
0.001175:
0.001275:
0.001275:
0.001375:
0.001275:
0.001275:
0.001275:
0.001175:
0.001375:
0.00127!"
0.001075:
0.001175:
0.001375:
0.001375:
0.001375:
0.001315,
0.001315:
0.001l1!!:
0.00Il75:
0.00117':
0.001575:
0.00127!"
0.00lf75:
0.001174:
0.001375:
0.001275:
0.001275:
0.0013'15:
()'001375:
0.001375:
0.001375:
0.001174:
0.001174:
0.001415:
0.001275:
0.001275:
0.001515:
0.001475:
0.001174:
0.0012'15:
0.001275:
0.001275:
0.001275:
0.001375:
0.001375:
0.001275:
0.001275:
0.001174:
270365-64
Repeatability Error, SN
=
6-291
4130 (Continued)
inter
Ap·406
31D:
371:
31P:
380:
381:
382:
383:
384:
.~5:
386:
387:
388:
389.
38A:
38B:
38C:
380:
38£:
l8P:
390:
391:
3q2:
393:
394:
395:
396:
397:
398:
399:
39A:
398:
3ge:
390:
39E:
39F:
3AO:
3A1:
3A2:
:M3:
3A4:
3A5:
3A6:
3A1:
3AB:
3A9:
3AA:
3AB:
JAC:
3AD:
:ME:
3AF:
3BO:
381:
312:
383:
3B4:
385:
386:
387:
388:
0.00131~:
0.00137~:
0.001315:
0.001475:
0.00lf75:
0.001275:
0.001475:
0.001375:
0.OOH75:
0.001275:
0.001275:
0.001375:
0.001174:
O.00121~:
0.001215:
0.001215:
0.001275:
0.001215:
0.001215:
0.001215:
0.GOl114:
0.nOI315:
0.001315:
0.0013'15:
0.001315:
0.0010'14:
0.001275:
0.001375:
0.001315:
0.001215:
0.001315:
0.001275:
0.001215:
0.001415:
0.001375:
0.001275:
0.001215:
0.001215:
0.001215:
0.001375:
0.001275:
0.001174:
0.000914:
0.001475:
0.001315:
0.001215:
0.001415:
0.001215:
0.001315:
0.001315:
0.001375:
0.0014'15:
0.001174:
0.0011":
0.001215:
0.001215:
0.001275:
0.001215:
0.001375:
0.001375:
t .
270365-66
Repeatability Error, SN = 4130 (Continued)
6-293
inter
AP-406
389: 0.001275:
3U: 0.001275:
~BB: 0.00In5.
3BC: 0.001275:
380: 0.001315:
3BE: 0.001114:
3BF: 0.001215:
leO: 0.001215:
3CI: 0.001114:
3C2: 0.00111.:
3C3: 0.001415:
3Ct: 0.001215:
3C5: 0.001215:
3C6: 0.001315:
3C7: 0.001114:
3C8: 0.001215:
3C'l: 0.001215:
leA: 0.001114:
3CJ: 0.001315:
3CC: 0.001375:
3CD: 0.001315:
leE: 0.001275:
3CP: 0.001215:
300: 0.001675:
3DI: 0.001815:
302: 0.001315:
303: 0.001375:
384: 0.00131&.
305: 0.oom5:
306: 0.001315:
301: 0.001375:
308: 0.001315:
309: 0.001215:
3Dl: 0.00111.:
308: 0.001475:
31e: 0.001f15:
300: 0.001315:
JOE: 0.001215:
30F, 0.001375:
3EO: 0.001174:
JEI: 0.001575:
312. 0.001375,
3E3: 0.001215:
3i1: 0.001275:
3£5: 0.001375:
3£b: 0.001415:
3£7: 0.001215:
3E8, 0.001215:
J£'j: 0.001515:
lEA: 0.001515:
3E8: 0.001215:
3Ee: 0.001215,
JEP: 0.001375:
3EE: 0.00iI1.:
J£F: 0.001f75:
3FO: 0.001275:
3FI: 0.001315:
3F2: 0.00117.:
3F3: 0.001(15:
3Ft: 0.001475:
3.5: O.OOl1U.
3F6. 0.001215.
3": 0.001275:
3n. 0.001275:
3f9: 0.001275.
3PA: 0.00117••
3F8. 0.001215:
3Ft: 0.001275.
3ah 0.001275.
3'•• 0.001375:
270365-67
270365-68
Repeatability Error, SN
=
6-294
4130 (Continued)
AP-406
APPENDIX E
BIBLIOGRAPHY
AID Processing with Microcontrollers, Katausky,
IEEE STD. 746-1984
Horden, Smith
Apfel, R., et. aI., "Signal-Processing Chips enrich telephone line- card Architecture". Electronics, May 5,
1982.
Analog Devices - Data-Acquisition Databook 1984,
Volume 1
Blahut, Richard E., "Fast algorithms for digital signal
processing", Addison Wesley Publishing Company,
Inc., 1985.
Boyes, ed. - Syncro and Resolver Conversion, 1980
Intel Application Note AP-124 - High-Speed Digital
Servos for Motor Control Using the 2920/21 Signal
Processor
Intel Application Note AP-125 - Designing Microcontroller Systems for Electrically Noisy Environments
Irwensen, J., "Calculated Quantization Noise of Single
- Integration Delta Modulation Coders" BSTJ Sept.
1969.
ITT Digital 2000 VLSI Digital TV System, MAA 2300
Audio AID Converter, Edition 1983/9.
Brown, Robert Grover, "Introduction to random signal
analysis and Kalman filtering". John Wiley \& Sons,
Inc., 1983.
MIL-M-38510/135 June 4, 1984
Burr-Brown Application Note, Testing of Analog-toDigital Converters
Modern Electronic Circuits Reference Manual
MIL-M-38510/135 May 6, 1985
NBS Staff Reports, May/June 1981 P.22/23
Burton and Dexter - Microprocessor Systems Handbook, 1977
Candy, J., et. al., "The Structure of Quantization Noise
from Sigma-Delta Modulation", IEEE Transaction on
Comm. Vol. Com. 29, No.9, Sept. 198i.
Sheingold, ed. - Analog-Digital Conversion Handbook,
1972
Sheingold, ed. - Analog-Digital Conversion Notes, 1977
Sheingold, ed. - Non-Linear Circuits Handbook, 1974
Candy, J., et. al., "Using Triangularly Weighted Interpolation to Get 13-Bit PCM from a Sigma-Delta Modulator", IEEE Transaction on Comm., Nov. 1976.
Sheingold, ed. - Transducer Interfacing Handbook,
1980
Electronic Analog-to-Digital
Pretzl, Handy
Seitzer,
Steele, R., "Delta Modulation Systems", Pentech Press
Limited, 1975.
Handbook of Electronic Calculations, Chapter 15, Analog-Digital Conversion
Taylor, Fred U., "Digital filter design handbook",
Marcel Dekker, Inc., 1983.
Harris Analog and Telecom Data Book
Terminology Related to the Perf of SIR, AID, D/A
Circuits, IEEE Transactions
Converters,
IEEE 162
6-295
· APPLICATION
NOTE
AP-428
May 1989
Distributed Motor Control
Using the 80C196KB
TIM SCHAFER
MICHAEL CHEVALIER
80C196KB APPLICATIONS
© Intel Corporation, 1989
Order Number: 270701-001
6-296
AP-428
1.0 INTRODUCTION
Distributed control of servo motors has a wide range of
applications including industrial control, factory automation and robotics. The tasks involved in controlling a
servo motor include position and velocity measurement, implementation of control algorithms, detection
of overrun and stress conditions, and communication
back to a central controller. The 80CI96KB high performance microcontroller provides a low cost solution
for handling these required control tasks.
The 80C196KB microcontroller is a highly integrated
and high performance member of the MCS®-96 family.
The part is available in ROM (83C196KB) and
EPROM (87C196KB) versions. A block diagram of the
80C196KB is shown in Figure 2. The availability of a
variety of on board peripherals such as timer/counters,
A/D, PWM, Serial Port and High Speed Input and
Output capture/compare timer subsystem provides for
a flexible architecture for control applications at a reasonable cost.
CURRENT
SENSING
FOR OVERRUN
CONDITIONS
COMMUNICATION
SOFTWARE FOR
DISTRIBUTED
CONTROL
270701-1
Figure 1. Control Tasks for Distributed Control of a Servo Motor
VREF
ANGND
CONTROL
SIGNALS
PORT 3
ADDR/
DATA
BUS
PORT 2 /
A/D PORT 0
HSI
HSO
270701-2
Figure 2. 80C196KB Block Diagram
6-297
inter
Ap·428
This application note describes several different methods for motor control using the on board peripherals of
the 80C196KB. Hardware and Software techniques are
addressed to generate PWMs for driving motors and to
measure position from the output of precision optical
encoders.
A Proportional, Integral and Differential (PID) algorithm controls both the position and velocity of the motor. The PID algorithm employs proportional, integral
and differential feedback to control the system characteristics of the motor. The motor can be moved either
manually or under the control of a velocity profile. The
mode used to position the motor is determined by commands received from a master controller.
Communication to the master controller was implemented using the onboard serial port of the 80C196KB.
The application of distributed control to position and
program a six axis robot arm using six separate motors
will be described. Each 80CI96KB motor controller
acts as a slave under control of the master. An IBM
PCTM was selected as the master controller for the robot. Turbo Prolog™ was used to develop the human
interface. A robot programming language and control
screen was produced to program movements of each
individual motor.
The motor control hardware, taking full advantage of
the peripheral features of the 80C196KB, will be discussed first. The control software will be discussed later.
2.0 HARDWARE
The hardware tasks required to control a servo motor
under the command of a centralized controller include
the following:
3) Detection of motor overrun conditions.
4) Communication from/to a master controller.
Two different hardware interface examples for controlling a servo motor are shown in Figures 3 and 4. The
first example controls one motor using TIMER2 and
the dedicated PWM unit on the 80CI96KB and would
best fit a high performance, high resolution application.
Example number 2 uses the HSI (High Speed Inputs)
and the HSO (High Speed Outputs) to control two motors. The second method can control up to four motors
by trading off some performance and resolution.
This section deals with the hardware and software requirements of acquiring position feedback from incremental shaft encoders and generating outputs to drive
DC servo motors. A current limiting circuit ,which is
useful in determining when the motor has stalled is also
presented. Current monitoring can also control the
torque to prevent the motor from crushing an object.
The closed loop digital control algorithms are discussed
in the software section.
2.1 Optical Encoders
Optical encoders can be used to measure the position of
rotating equipment. They provide a cost effective solution for digital position and velocity feedback to a microcontroller. Encoders produce two pulse trains which
give an incremental position count. Velocity and acceleration may be calculated by measuring the number of
counts in a given sample period. Or, in a slow speed
system, velocity and acceleration can be measured directly from the time between edges of the pulse train.
Acceleration and velocity ,calculations are discussed in
detail in the software section.
. I) Feedback of the motor position and direction.
2) Control of the motor speed and direction.
l _______~~DEF~P~HA~S~E~A~
T2CLK t
ENCODER PHASE B
T2UP/DN t-------UL~O~G~IC:...J.l.:.::=~..
1llll1i!16ji6111jA/D BUS
OPTICAL ENCODER
ACH0t--;::.;;;:~~~~~
P2.7
PWM
27C64
80C196KB
DC SERVO MOTOR
270701-3
Figure 3. Block Diagram of Motor Control Hardware using PWM and TIMER2
6-298
inter
AP-428
16
DATA
8
373
HSI.O
PO.O
HS1.1
PO.l
AID BUS
ACHO
P2.7
HSO.O
27C64
ACHI
P2.6
HSO.l
80C196KB
270701-4
Figure 4. Block Diagram of Motor Control Hardware using HSO and HSI
External logic for encoders is shown in Figure 6. Figure
7 shows a timing diagram of the circuit. Bold type denotes the input and desired output waveforms. The
phases from an encoder are mechanically produced
electrical signals. When the motor rotates slowly, the
phases inherently exhibit slow rise and fall times. The
four Schmitt triggers in the circuit protect against oscillation in the digital circuit due to these long rise and
fall times.
Pulse trains from an encoder can vary from two pulses
per revolution for low cost applications, to over 5000
pulses per revolution for high resolution requirements.
Figure 5 shows an eight line encoder along with the
associated waveforms. A small amount of external logic
and a few discrete components decode a position count
and a direction indication from phase A and phase B.
CLOCKWISE
PHASE A
----.fLSL
PHASEBSLjL
COUNTERCLOCKWISE
PHASEASLjL
PHASE B
----.fLSL
270701-5
Inside track generates Phase A and outside track generates Phase B
Figure 5. Eight Line Encoder
6-299
intJ
AP-428
L.--------------~~~_!£CU~P~/~D~N~D----l
>
U2
DIRECTION
U4 01-------
Ul = 74HC14
U2 = 74HC86
U3 = U4 = 74HC74
CL
270701-6
Figure 6. External Logic for Encoders
CLOCKWISE
COUNTERCLOCKWISE
PHASE A
u
ASHOT
PHASE B
u
u
u
u
11..________. .
BSHOTLJ
u
I
u
LfTlJ
I
u
CUP/ON
COUNT
UP/ON
270701-7
Figure 7. Timing Diagram for Logic Circuit
A simple one-shot is constructed with an RC circuit
and an XOR gate to generate a pulse on each edge of
each phase. ASHOT clocks phase Band BSHOT clocks
phase A. This technique of digital filtering insures repetitive edges on a single phase without an'edge on the
other phase are not passed on to the processor. Repetitive edges occur when the motor changes direction.
Further logic obtains a direction or UP/ON bit. Note
the first edge after a direction change is lost. A lost
edge does not affect the count since the first transition
is lost in both directions. Since an edge is lost in each
direction, the circuit has an absolute resolution of one
edge.
6-300
inter
AP-428
2.2 Interfacing to TIMER2
COUNT indicates an incremental position count on
both its rising and falling edge. TIMER2 on the
80C196KB is a 16 bit externaIly clocked up/down
counter clocked on the rising and falling edge of its
input signal. A one or zero on port pin 2.6 determines
whether TIMER2 counts up or down. By interfacing
an optical encoder to TIMER2 as shown in Figure 8,
an up/down counter is realized. No software intervention is required to keep track of position or direction
changes with the 16 bit TIMER2. The CPU is free to
concentrate on executing the control algorithm.
PHASE A
PHASE B
-
COUNT
DECODE
CIRCUIT
CONTROL ALGORITHM
T2CLK
270701-9
DIRECTION
P2.6
Figure 9. Control Algorithm for TIMER2
RPM, the edges are only clocked into TIMER2 at a
period of about 5 p.s.
80C196KB
270701-8
(6000 RIM)' (1/60 M/SEC)' (512 LINE)' (4 EDGES/LlNE)
204,800 edges per second
Figure 8. TIMER2 and Encoder
Interface Circuitry
For designs requiring greater resolution, a 32-bi~ up!
down counter may be realized with the same CIrcUIt
and minimal software overhead. TIMER2 can cause an
interrupt on an overflow condition. However, an overflow interrupt is not the safest way to implement a 32bit up/down counter. Repetitive overflow interrupts
could happen when the motor oscillates about a position where the LSW (Least Significant Word) is zero,
or TIMER2 keeps overflowing and underflowing. For
this method, the total software overhead required for a
32-bit up/down counter is dependent on the position
and set point of the motor and would be difficult to
predict.
A much better way to implement a 32-bit up/down
counter is shown in Figure 9. TIMER2 is only read at
the beginning of the control algorithm, or once a sample time. This does not present an acc~racy p.roblem for
a digital control algorithm. TIMER2 IS read mto a temporary register. The temporary value is then subtracted
from TIMER2, rather than c1earin? TIMER2, ensurin.g
no counts will be'missed. The 16-blt temporary value IS
sign extended to form a two's complement 32-bit value
and added to the old 32-bit position value to form the
current position value. This 32-bit up/down count.er
provides the accuracy needed for a control loop whl~e
keeping software overhead constant under all condItions.
A Pittman motor with a Hewlett Packard HEDS - 5310
512 line incremental shaft encoder was interfaced to
TIMER2. Even at a maximum shaft rotation of 6000
6-301
=
TIMER2 has a minimum transition period of once a
state time, or 167 ns @ 12 Mhz, in the fast increment
mode. Obviously, much higher resolutions and speeds
may be obtained.
2.3 Interfacing to .the HSI
The HSI can interface more than one motor to the
80C196KB. COUNT is input into an HSI pin which is
configured to recognize events on both the rising and
falling edge of its input signal. UP/DN is input to a
port pin to determine direction. Up ~o four motor~ can
be interfaced to the 80Cl96KB usmg the four mput
pins of the HSI. The disadvantage of using the HSI is
an ISR (Interrupt Service Routine) must be executed
on each edge. Considerable software overhead could occur if edges are clocked into the HSI faster than about
one every 150p.s.
Two Pittman motors with 2 line encoders were interfaced to the HSI to generate two 32-bit up/down counters as an example. With both motors turning at a maximum velocity of 6000 RPM, an edge will occur every
625p.s. The ISR in Figure 10 processes the edges from
the encoders and updates the position values and executes in about 15p.s @ 12 MHZ on the 80C196KB.
This still allows 97.6% (1 - 15/1250) of the total processing time to implement control algorithms and other
I/O functions.
inter
AP-428
iii;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;iii;;;;;;;
HSI INTERRUPT SERVICE ROUTINE
iii;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;iii;;;;;;;;;
hsi data int:
pushf
iosl bak,iosl
orb
iosl:bak,7,no_data
jbc
more in fifo:
- -andb iosl_bak,'Olllllllb
mot 4 cnt:
- - jbc
hsi status,O.mot 5 cnt
jbs portI,O,mot 4 up - mot_4-pos,l"1sub
subc mot_4-pos+2 ,.O
br
mot_5_cnt
mot 4 up:
- - add
mot_4-pos.fl
addc mot_4-pos+2,fO
mot 5 cnt:
- - jbc
hsi_status,4,test_aqain
jbs portl,l,mot 5 up
sub
mot_5-pos,11subc mot 5-pos+2,fO
br
test_aqain
mot 5 up:
- - add
mot 5-pos.fl
addc mot~S--pos+2,fO
test aqain:
ld
nop
nop
nop
nop
orb
iosl bak,iosl
jbs
iosl:bak,7,more_in_fifo
no data:'
popf
ret
;test for any data received
;test for count of motor 4
;test for up/dn bit
;decrement motor 4 position
;increment motor 4 position
;decrement motor 5 position
;increment motor 5 position
;read hsl time to step fifo
;wait 8 state times for
;holdinq reqister to be loaded
;make sure fifo is flushed
270701-10
Figure 10. HSllnterrupt Service Routine
The HSI approach does add flexibility. Since the HSI
records a TIMER I value with each transition, velocity
and acceleration can be calculated on every edge.
the VFETS was determined by the current specifications
of the motors. Heat sinks were used to protect the
VFE'fS. The VFE'fS are protected from voltage spikes by
the MOV, (Metal Oxide Varistor), a type of transient
absorber.
2.4 Driving a DC Servo Motor
Figure II shows the circuit used to drive the motors. A
digital output from the BOCI96KB is converted into an
analog signal capable of driving a DC servo motor.
POWER is a PWM output from the BOCI96KB. DIRECTION is a port bit which qualifies the + 15 or
-15 supply. A signal diagram is shown in Figure 12.
Isolation between the motor power supply and the digital supply is provided by the two optical isolators preventing any inductive glitches caused by the motor
turning on and off from effecting the digital circuit. The
optical isolators in turn drive the two VFE'fS. Size of
2.5 Using the Dedicated PWM Output
The PWM output unit on the BOCI96KB is an B bit
counter which increments every state time. The output
is driven high when the counter equals zero and driven
low when the counter matches the value in the PWM_
CONTROL register. Typical PWM waveforms are given in Figure 13. A prescaler can allow the PWM counter to increment every two state times. With a ·12 Mhz
crystal, the PWM has a fixed output frequency of 23.6
Khz, or 11.B Khz with the prescaler enabled.
6-302
AP-428
+15V
S
rP
o
PWM
(POWER)
0.1 }'F
o
5
-15V
270701-11
U3 = 7438
U4 = U5 = OC1Hl1Al
N = IR533 HEXFET
P = IR9533 HEXFET
M = Z47A7 MOV
Figure 11. Motor Drive Circuitry
POWER
DIRECTION _ _ _ _ _ _ _ _ _ _ _---',
+15
OUTPUT
-15
270701-12
Figure 12. Motor Drive Waveforms
Duty
Cycle
PWM
Register
0%
00
25%
64
50%
128
90%
230
99.6%
255
Output Waveform
270701-13
Figure 13. PWM Output Waveforms
6-303
inter
AP-428
The PWM unit along with pin 2.7 was used to drive
one motor at a fixed output frequency of 23.6 Khz. By
driving the motor at this frequency, motor whine in the
audible range was eliminated. Note that a 00 value in
the PWM register applies full power to the motor; the
desired 8 bit output value must be inverted before it is
loaded into the PWM_CONTROL register to obtain
the correct output.
2.6 Using the HSO to Generate PWMs
The HSO (High Speed Outputs) of the 80CI96KB can
generate up to four PWMs. The HSO triggers events at
specified times based on TIMERl or TIMER2. For the
specific purpose of generating PWMs, the event is driving an output pin high or low. HSO commands are
loaded onto the CAM, (Content Addressable Memory),
which specify the time and event to take place. The
CAM is eight positions deep. The HSO triggers the
event on a successful compare with the,associated timer.
The 80CI96KB can optionally lock commands onto
the CAM. This feature is very useful for generating
PWMs using TIMER2 as the time base. Figure 14
shows an example of two PWM outputs using locked
commands in the CAM. TIMER2 is clocked externally
at a frequency which determines the resolution of the
PWMs. TIMER2 can be clocked at a maximum frequency of once every eight state times (1.33,...s @ 12
Mhz) when used with the HSO. The RESET TIMER2
@ T4 command specifies the output frequency of the
PWMs. By changing the external TIMER2 clock frequency and the value of T4, the HSO can generate a
wide range of PWMs.
'
7
TO and TI specify when the output pins will be driven
low. By varying TO and TI, the duty cycle of the output
waveforms are changed. Both pins are driven high by
the same command at the same time TIMER2 is reset.
Since there are still four positions open in the CAM;
two more PWMs could be generated and one position
would still be left open in the CAM.
For this ap-note, two Pittman motors were controlled
using the HSO along with port pins 2.6 and 2.7. It was
desired to keep the output frequency the same as the
output frequency of the on-board PWM. To accomplish
this, TIMER2 was clocked every 8 state times and reset
when it reached 31 counts. This makes the output frequency 23.6 Khz @ 12 Mhz with 5 bits of resolution.
CLKOUT was externally divided by 16 and input into
TIMER2. Since TIMER2 counts on both the positive
and negative edge of its input signal, a square wave
with a 16 state period clocks TIMER2 every 8 state
times.
The ISR used to load commands onto the CAM is
shown in Figure IS. When the control algorithm determines an output has changed, a RESET TIMER2 command gets loaded onto the CAM to generate an interrupt. The interrupt vectors to this routine and updates
the CAM. To clear a locked entry from the CAM, the
entire CAM must be flushed by setting IOC2.7. Care
must be taken to reload all of the commands. This includes any commands not locked on the CAM.
TIMER21Jlfl
nnnnnnnnnnnnnnnr
------------------
6
5
HSO.1
4
3
RESET TIMER2
2
SET HSO.O & 1 HIGH
o
@
T4
@
HSO.O
T4
SET HSO.1 LOW
@
T1
SET HSO.O LOW
@
TO
LJ
U
'270701-14
HSOCAM
Figure 14. Two PWMs Using HSO Locked Entries
6-304
AP-428
timer2 reset:
-ldb
IOC2,#11000000b
Id
hso command,111001110b
ld
hso=time,t3l
nop
nop
hso command,~lllOOllOb
ldb
ld
hso=time,it31
;clear the CAM
;load reset timer2 command
;this command will set both
;hso lines for the PWM
;load mot_4~ower value
;if power is lfh, do not load
; this command, it will cancel
;with the set command
cmpb mot 4 power,i3l
je
check-4
Idb
hso command,#11000000b
ldbze hso_time,mot_4~ower
check_4:
;load mot_5~ower value
;if power is lfh, do not load
;this command, it will cancel
;with set command
cmpb mot_5~ower,lI3l
je
sanity check
ldb
hso command,#llOOOOOlb
ldbze hso=time,mot_4_power
sanity check:
-cmp
TlMER2,t32
;sanity check to make sure
jnh
sane
;TI~mR2 is not greater than 3:
clr
TlMER2
sane:
ldb
hso command,~39h
;reload software timer 1
add
swtl~eriod_bak,iswtl_dly~eriod
ld
hso_time,swtl~eriod_bak
ldb
port2,port2_bak
;load direction bits
popf
ret
270701-15
Figure 15. HSO Interrupt Service Routine
There is the potential for commands to be missed when
they are flushed and reloaded on the CAM. For example, an HSO command is loaded on the CAM to clear
HSO pin 3 when TIMER2 = 23 and the CAM is
flushed when TIMER2 = 22. A new HSO command is
then loaded onto the CAM to clear HSO.3 when
TIMER2 = 21. This command will not execute until
TIMER2 is cleared and counts back up to 21. Missed
commands are difficult to avoid without excessive software overhead. Software must take missed commands
into account and minimize the effects on the application.
The ISR in Figure 15, insures if an output edge is
missed for one period of TIMER2, the HSO pin will
remain high. A logical one applies no power to the motor. Also, at the end of the routine a sanity check makes
sure TIMER2 is not greater than 31.
6-305
2.7 Current Limiting
When a motor is stalled, or excessively loaded, it will
draw a lot of current. Current limiting can be used to
keep the motor from damaging itself, or anything in its
path. Several options exist to the user on what to do
about a high current condition. Less power could be
applied, or the motor could shut off entirely. This section only explains how to recognize a high current condition in a DC servo motor, not what to do about it.
Figure 16 shows a way to convert the current from the
motor into a voltage which can be read by the
80C196KB onboard AID converter. Again, an optoisolator keeps the motor and digital power supplies separate. When enough current flows through the optoisolator, the AID input voltage will drop down to
about.7 volts. The current to the opto-isolator is varied
by changing the values of the two resistors, Rl and R2
which split the current flow. By changing Rl and R2,
this circuit can be adjusted to work properly with different motors and load conditions.
intJ
AP-428
TO MOTOR
GROUND
4.7K
7
Vee
+----.AjD INPUT
R2=3K
DIGITAL GROUND
fROM MOTOR
270701-16
Figure 16. Current Sensing Circuitry
Motor startup current must be considered when testing
for a high current condition. When a motor is started, it
will draw a great deal of current. This current surge can
last for a few milliseconds. Software must decide if the
motor is drawing excessive current because it is stalled,
or just starting. The section of code in Figure 17 exe-
cutes during the control algorithm. The current must
be above ad~imit for 30 sample times before software
recognizes a high current condition. Of course, these
values must be adjusted up or down depending on the
motor and load cqnditions.
;do a current limit check
jbs
cmpb
jh
incb
cmpb
ad command,3,motor around
acf result hi, ad lImit
current of
ad countad=count,t30
;if AID still running, skip
;want to do 30h AID conversicr.s
;before acting because of ~oc~r
; startup' current
jne current_maybe_ok
;here is where the user inserts his code on what to do
;about a high current condition
current_ok:
clrb ad count
current maybe ok:
ldb ad_command,IOOOOlOOlb
motor around:
istart another aid conversion
270701-17
Figure 17. Current Sensing Software
6-306
inter
AP-428
r---------- .
._--------_ ..
Ir----------~
HSI INTERRUPT ROUTINE I
I POSITION CHANGES
I
FROM ENCODER. I
I HSO INTERRUPT ROUTINE I
PWM GENERATION
I
,,----------'"
TIMER2 SOFTWARE
POSITION MEASUREMENT
270701-18
Figure 18. Software Block Diagram
3.0 SOFTWARE
A block diagram of the software is shown in Figure 18.
The software consists of a main program for hardware
and software initialization of the 80CI96KB peripherals and programming of control tasks. The control
tasks include tracking the motor position and direction,
control of the motor speed and direction, detection of
overrun conditions and communication to the master
controller. After initialization is complete, the
80Cl96KB enters idle mode to preserve power while
not performing control tasks. Interrupt service routines
for the serial port, HSI, HSO and software timer perform the various control tasks.
The communication protocol to the main controller is
implemented in the serial receive and transmit routines.
Commands from the master controller move the motor
in one of two modes, manual or automatic, depending
on the command. The commands are listed in Figure
28.
Manual mode moves the motor clockwise or counterclockwise with a preset maximum control voltage applied. Manual mode commands include MOTOR UP,
MOTOR DOWN and STOP. The MOTOR UP and
MOTOR DOWN commands send the motor into manual mode. The motor continues to run in the desired
direction until a STOP command is issued from the
master controller. The STOP command loads the destination position with the current position and enters automatic mode.
6-307
Automatic mode positions the motor using either a position or velocity PID algorithm. The position PID algorithm is applied after reception of the STOP command or when the desired position is reached. The destination position can be changed by a POSITION command from the master controller.
The maximum motor velocity and the destination position are contained in the POSITION command. If the
maximum velocity is zero, a position PID is applied to
move the motor to the destination position. A non zero
maximum velocity will position the motor using a velocity PID algorithm. Position and velocity input to the
algorithms are calculated based on position input from
the encoder.
Position information for the PID algorithms can be
provided by using the High Speed Inputs or TIMER2.
The HSI interrupt routine processes the direction and
position information incoming from the encoder to provide current motor position. Alternatively, TIMER2
directly measures the position when used as an up/
down counter. Velocity information can be calculated
using the position information given a constant sampling rate. The position and velocity information are
used by the PID control algorithms.
The control algorithm uses a software timer interrupt
to generate the sampling rate of the control software.
The main portion of the software timer routine calculates the current position and velocity, senses the motor
AP-428
current for overrun conditions, calls the PID control
algorithm and generates the PWM control voltage to
the moior.
The speed of the motor can be controlled ,using the
PWM or the HSO. If the HSO is used, the HSO interrupt routine generates a PWM output to control the
voltage applied to the motor. Otherwise, the PWM unit
controls the voltage applied to the motor.
Each of the major software routines is covered in detail
in this section.
ENABLE PWM
ENABLE .TIMER 1 OVERFLOW INTERRUPT
SET T2CLK AS TIMER2 SOURCE
3.1 Main Initialization Routine
The main initialization routine executes immediately
following reset to initialize the 80C196KB peripherals
and enable the interrupt driven control tasks. A flow
chart for the main initialization routine is shown in
Figure 19. The constants and variables for the control
algorithms and software routines are loaded into register space for fast execution.
Next, the various penph,erals are programmed to handle the control tasks. The PWM for voltage control of
the servo motor is initialized. TIMER2 is programmed
as an up/down counter with T2CLK as the clock
source. The serial port is set to 19.2 Kbaud and programmed for mode 2 to receive incoming commands.
An AID conversion, is started to check for initial stress
conditions. Before the motor can be accurately positioned, an initial reference point must be established.
In order to find the reference point, an I/O port is
connected to a limit switch. The motor is driven in a
preset direction until the limit switch is activated. The
initial position is then loaded and position PID control
is applied to keep the motor stable. Position commands
from the master controller can now precisely position
the motor from the established reference point.
Finally, the software timer, timer overflow, receive and
transmit interrupt routines are enabled and the idle
mode is entered to conserve power. The routines will
execute as each individual interrupt control task requires servicing. Discussion of the control tasks of each
software routine is contained in the following sections.
3.2 Software Timer Interrupt Routine
The software timer interrupt service routine executes
every 500 J-Ls and determines the sampling rate of the
PID control algorithm. Figure 20 shows the flow chart
for the software timer interrupt routine. The routine
determines the operating mode, calculates the current
velocity and position and tests for overrun of preset
boundary conditions and stress conditions.
6-308
270701-19
Figure 19. Motor Initialization Routine
AP-428
270701-20
270701-21
Figure 20. Software Timer Interrupt Routine
An AID conversion compares the motor current to test
for a stress condition against a preset limit. Thirty conversions are done to average the motor current to prevent a false trigger due to a large current surge when
the motor starts up. If the preset limit indicating a
stress condition is exceeded, the motor is stopped.
6-309
The motor is also stopped if the current position exceeds the preset boundary limits. In the case of the
robot, the movement of joints are limited to prevent
positions which may cause stress conditions or damage,
the robot. The positioning of the robot is dependent on
the mode of operation.
inter
AP·428
A manual flag is tested to determine if the automatic or
manual mode should position the motor. The manual
mode moves the motor either up or down with a preset
maximum motor control voltage until a STOP command is issued. The automatic mode positions the motor using either the position PID for accurate positioning or the velocity PID for long positioning.
measured position. The integral term consists of the
integral of the position errors multiplied by an integral
constant. The differential term is the change in error
multiplied by a differential constant. The sum of the
terms is then scaled to provide a control voltage to the
motor. The system characteristics of the motor are
tuned by the selection of appropriate constants.
The software timer interrupt routine calculates and
stores the current position and velocity of the motor for
use by the appropriate PID algorithm. The current velocity is calculated given the sampling rate, the current
position and the previous position. The calculated velocity and position information is stored in the
80Cl96KB register space for use by the PID algorithm
software.
The settling time, steady state error and system stability
are impacted by the amount of proportional gain selected. To accurately control a small change in motor position, a large gain is desired. Faster system response is
attained by selecting a large gain but at the cost of
greater overshoot and longer settling time. The effect of
varying loads on the motor makes proportional control
in itself inadequate because of system instability and
large steady state error.
Recall that either a position PID or a velocity PID
control algorithm will be executed depending on the
maximum velocity value passed by the master controller. If the value is zero, a position PID is employed,
otherwise, the velocity profile is employed. The velocity
profile PID is ideal for large maneuvers while the position PID is better for shorter movements or maintaining the current position. The generated output from the
control algorithm is then loaded into the PWM control
register and a return is executed.
3.3 PIO Control Algorithm
The algorithm used to control the angular position and
velocity of the motor is a common PID algorithm. The
algorithIp. uses proportional, integral and differential
feedback to control the output to a motor. The PID
algorithm controls the important system characteristics
of the motor: settling time, steady state error, and system stability. Each term in the control algorithm affects
each system characteristic differently. A block diagram
of the PID algorithm is illustrated in Figure 21.
Application of integral feedback drives the steady state
error to zero by increasing the output in response to a
steady state error. The integral term increases as the
sum of the steady state error increases causing the error
to eventually be driven to zero. The integral term, although driving the steady state error to zero, can cause
overshoot and ringing if it is too large. This has the
undesirable affect of poorer system response. Applying
PI control works very well, however a faster system
response can be acheived by applying a PID algorithm.
System response can be improved by adding a differential term. Addition of this term improves the response
time by providing a output proportional to the rate of
change in error. When the motor has a large change in
error, the term produces a large output to the motor.
Therefore, the system responds faster to disturbances in
the system. Most of the system instability is caused by
too high of a differential constant. The size of the proportional, integral and differential constants provide
tradeoffs to the desired system characteristics.
Selection of the three gain constants is critical in providing fast system response with good system characteristics. A slightly modified PID algorithm controls
the motor which improves both the system response
and the system stability. Two modifications were made
to improve the control algorithm. First, the size of the
integral term was clamped to prevent instability caused
by an extremely large integral term which could occur
after a long time with large errors. Second, the integral
term was cleared when the error changed sign to further improve the system stability. The PID control algorithm is written in PL/M-96 for ease of development.
270701-22
Figure 21. Block Diagram of PID Algorithm
3.4 Position PIO Software
The PID algorithm consists of three terms: ·a proportional term, integral term and differential term. The
proportional term drives the motor with an output directly proportional to the error between the desired and
6-310
The software flow chart for the PID algorithm is shown
in Figure 22. Upon entering the routine, the position
AP-428
YES
YES
SET MOTOR DIRECTION CLOCKWISE
SET MOTOR DIRECTION COUNTER CLOCKWISE
NO
YES
CLEAR SUM_INTEGRAL
YES
YES
OUTPUT
SUM...:INTEGRAL
=_MAX-INTEGRAL
=(POS_ERRoKp + SUM_INTEGRAL ° KI + DI" _ERR ° Kd)
SCALER
YES
OUTPUT
=LIMIT
OUTPUT
=LIMIT
SET DIRECTION COUNTER CLOCKWISE
YES
270701-23
Figure 22. Position PIO Algorithm
6-311
AP-428
error is checked for a minimum value before applying
the position PID algorithm. If the minimum position
error is exceeded, the maximum PWM output is applied to move the motor a~ rapidly as possible.
Current position error is added to the integral sum.
Position error and integral sum are tested to clear the
integral sum if they are opposite in sign. This improves
the system stability by preventing the integral term
from applying a correction opposite to the desired output.
If the integral sum is greater than the maximum sum
allowed, the integral sum is clamped. This prevents the
integral sum from becoming too large if the error is
large for several samples. Differential error is then cal-'
culated from the current and previous position errors.
Output for the PID algorithm is calculated from the
proportional, integral and differential terms multiplied
by their individual gain constants. The output is then
scaled and tested for the preset PWM output limit. If
the limit is exceeded, the output to the PWM is set to
the maximjlm value. The appropriate motor'direction is
set depending on the sign of the output. The final output to the PWM control is ready and the software returns.
The parabolic profile is the most power efficient and
provides smooth acceleration and deceleration at the
end points. However, a large amount of processor time
is needed to calculate the profile in real time. The triangular profile provides ease of calculation versus the parabolic but generates a rough transition at the peak of
the profile. A trapezoidal profile provides energy efficiency, ease of calculation and relatively smooth acceleration and deceleration throughout the velocity profile. For these reasons, the trapezoidal profile was selected.
'
A trapezoidal profile consists of an acceleration period,
run period and deceleration period. The variables ACCEL_TIME, RUN_TIME and END_TIME represent the periods. Figure 23 shows the trapezoidal profile. Acceleration and deceleration rates for the motor
,are fixed according to the optimum values found
through testing. The master controller sends a position
command containing the maximum velocity
(MAX_VELOCITY) and the desired end position
(DES_POSITION). The DES~POSITION is equal
to the integral of the velocity profile (i.e., the final position can be determined by integrating the velocity, over
the period of the profile. Therefore, the
ACCEL_TIME, RUN_TIME and END_TIME
can be calculated based on the DES_POSITION,
ACCELERATION,
DECELERATION
and
MAX_VELOCITY.'
3.5 Velocity Profile
Positioning of a servo motor using only a position PID
algorithm wastes power and gives poor system performance when moving between two positions. A velocity
profile provides a smooth transition between two angular positions and improves the energy consumption of
the motor. Three different velocity profiles which can
be applied are trapezoidal, triangular and parabolic.
The destination position should be reached if the velocity profile was ideally tracked. However, a certain
amount of position error can be expected as the motor
travels from one point to another. This error is eliminated by applying the position PID at the end of the
velocity profile. This modified control algorithm has
both good motor performance and accurate angular positioning.
~I,~,------~~-----------------END_TiME----------------------------~
I----ACCEL_TIME -----.11--------- RUN_ TIME--------~
VELOCITY
, ACCELERATION
RUN
DECELERATION
MAXIMUM VELOCITY
TIME
270701-24
Figure 23. Trapezoidal Velocity Profile
6-312
AP-428
3.6 Trapezoidal Profile Calculation
The trapezoidal velocity profile is calculated when a
position command with a nonzero maximum velocity is
passed from the master controller. The master passes
the desired end position and the maximum velocity of
the motor. A reasonable acceleration (deceleration) rate
was found through experimentation to be I position
count/sampling rate (500 fLS). ACCEL_TIME,
RUN_TIME and END_TIME can be easily calculated given the relative acceleration rate of one, the end
position and the maximum velocity.
The acceleration and deceleration time is equal to the
maximum velocity since the acceleration/deceleration
rate is one. RUN_TIME is the difference between the
desired position and current position minus the distance covered during the acceleration and deceleration
times. END_TIME is the RUN_TIME added to two
times the ACCEL_TIME. With the velocity profile
calculated, the velocity PID algorithm will be applied
until the END_TIME is reached.
shows the velocity profile generation software. The
TIME variable is incremented every software timer interrupt at the sampling rate if it is less then the end
time (END_TIME) of the profile. Three different velocities are calculated during the profile. DES_VELOCITY equals the ACCELERATION multiplied by
the TIME until the ACCEL_TIME is reached. The
DES_VELOCITY equals the maxiumum velocity until' the RUN_TIME is exceeded. Once the
RUN_TIME is exceeded, the velocity is equal to the
ACCELERATION (same as deceleration rate) multiplied by the TIME-CUR~TIME. When the end of
the profile is reached (which is approximately the desired end position), the time equals the END_TIME
and the position PID controls the motor. If the maximum velocity passed by the master controller is zero,
the CURRENT_TIME is set to the END_TIME
and the position PID controls the motor.
The velocity control algorithm employs the PID algorithm. The algorithm is similar to the position algorithm used to control the position. The velocity control
algorithm is shown in Figure 25.
The velocity profile software generates the appropriate
velocity depending on the current time. Figure 24
~>-=---I DES_VELOCITY
DES_VELOCITY
=ACCELERATION· CURR_TIME
=ACCELERATION· (TIME-CURR_ TIME)
270701-25
Figure 24. Velocity Profile Generation Software
6-313
inter
AP-428
VELOCllY ALGORITHM
STORE VELOCllY ERRORS
DIFF_ERR
=(VEL
ERR-VEL ERR3 + 3*VEL ERRl-3*VELERR2)
SCALER
OUTPUT = PREY-OUTPUT + «VEL_ERR-VELERRl )*VKp + (VEL_ERR + VEL ERR 1)*VKI + DIFF_ERR*VKd»
SCALER
270701-26
Figure 25. Velocity Control Algorithm
3.7 Fast Execution of Control
Algorithms
Execution
Time
The high speed arithmetic operations capability, availability of three operand instructions and large register
space of the 80C196KB provide for fast execution of
control algorithms. The 80C196KB running at 12 Mhz
can execute a 16 X 16 Multiply in 2.3 JLs and 32/16
divide in 4.0 JLs. Three operand instructions operate on
two variables without modification and store the result
in the third variable. This eliminates the need for executing load and store operations as required by accumulator bound architectures. The large register space
can store all of the constants and variables for the control algorithm without the use of load and store operations. In addition, procedures do not need to pass parameters or store results since they can permanently
reside in register space.
A summary of the execution times for the main software routines is shown in Figure 26.
6-314
Software Timer Interrupt Routine
40 JLs
PIO Control Algorithms:
Velocity PIO (PL/M-961 ASM-96) 300 JLs/30 JLs
Position PIO (PL/M-961 ASM-96) 240 JLs/40 JLs
Velocity Profile Generation
71 JLs
HSI Interrupt Processing
22 JLs
HSO Generate PWM Routine
16 JLs
Receive Interrupt and Command
Processing
26 JLs
Transmit Interrupt Routine
11 JLs
Figure 26. Execution Times for
Main Software Routines
inter
AP-428
The HSI, HSO, Receive and Transmit Interrupt routines take a minimal amount of time. A majority of the
processing time is in executing the Software Timer interrupt routine and either the Velocity PID or Position
PID control algorithms.
PID Control Algorithms take a considerable amount of
'time since they are written in it high level language and
execute a number of thirty-two bit arithmetic opera-
VPID:
Id vel_err3,vel_err2
Id vel_err2,vel_errl
Id vel_errl,vel_err
sub vel_err,des_velocity.velocity
sub
mul
sub
add
tions. Thirty-two bit accuracy is not required since the
maximum position required to accurately track the motor is about twenty four bits. To optimize the control
algorithm for the accuracy required, the routines can be
written in assembly. A sample Position PID algorithm
is shown in Figure 27. The routine executes in about 30
/A-s by optimizing the control algorithm and minimizing
the number of 32-bit operations.
store velocity errors
calculate velocity error
temp,vel_errl.vel_err2
calculate differential error term
temp.#3
diff_err=(vel_err-vel_err3+3*vel_errl-3*vel_err2)
temp.vel_err3
temp,vel_err
Output=prev_output + «vel_err-vel_errl)*VKp+(Vel_err+Vel_errl)*Vki + diff_err*Vkd»/
;scaler
OUTPUT:
REVERSE:
FORWARD:
SCALEOUT:
EXIT:
calculate differential term
mul temp.Vkd
add temp2.vel_err.vel_errl
mul temp2.Vki
add temp.temp2
sub temp2.vel_err.vel_errl
mul temp2.Vkp
add'temp,temp2
div temp,scaler
add output.prev_output.temp
Id prev_output.output
div Out_scaler
jbc Out+3.7.forward
neg Out+2
Idb p2.#07fh
sjmp scaleout
Idb p2.#OFFh
calculate integral term
calculate proportional term
scale output
Scale 32 bit output to get 16 bit result
test output for direction
negate output
set direction down(p2.0=O)
set direction up(P2.0=1)
scale output for maximum pwm value
if Out > maximum pwm output
then clamp output to max pwm value
cmp Out.#Offh
jgt exit
Id Out.#Offh
Idb pwm.Out
ret
Figure 27. Position and Velocity PIO Assembly Routine
6-315
infef
Ap·428
add sum_int, pos_err
" sum position errors
div sum_int,decay
limit effect of old position errors
sub diff_err, pos_err
differential error = (pos_err - pos_errl)/2
div diff_err, #2
Out = Kp*pos.err + Ki*interr + Kd*differr
mul Out pos_err, Kp
OUTPUT:
Calculate proportional term
mul temp, Ki interr
Calculate integral term
add Out, temp
add integral term to Output
addc Out+2, temp+2
32 bit add to maintain full 32 bit accuracy
div Out, scaler
Scale output
jbc Out+3,7,forward
test output for direction
REVERSE: neg Out+2
negate output
ldb p2,#07fh
set direction down (P2.7=O)
sjmp scaleout
FORWARD: ldb Port2,#Offh
set direction up(P2.7=1)
SCALEOUT: cmp Out,#Offh
scale output for maximum pwm value
jgtexit
if Out > maximum pwm output
ld Out,#Offh
then limit output to maximum value
load pwm with Output 'value
EXIT:
ldb pwm, Out
ret
PID:
Figure 27. Position and Velocity PIO Assembly Routine (Continued)
2, the serial port interrupt will not occur. Each motor is
initially programmed for this mode to distinguish receiving a command versus a data byte. With the ninth
bit set, indicating a command byte has been received,
all the slaves interrupt and process the incoming byte.
The address of the motor being controlled is embedded
in the command byte. All processors will process the
command byte if the motor address matches.
4.0 Distributed Control
Distributed control of servo motors requires the passing
of commands and data from a master to a slave. The
master passes commands to report position, start and
stop the motor, or position the motor to an exact location using a position PID or velocity profile. The slave
needs to report current position and acknowledge incoming commands from the master. This protocol requires addressing of slaves and the distinction between
incoming commands and transmission of data. The
80Cl96KB serial port provides a multiprocessor communication mode for implementing the protocol.
The 80C196KB provides a ninth bit in Mode 2 and
Mode 3 that can assist communication between multiple processors. If the received ninth bit is zero in mode
A motor receiving a poll command from the master
,controller will enter mode 3. The polled motor then
receives the data bytes which are sent with the ninth bit
cleared. Therefore, only the processor receiving data
will interrupt for serial reception while the other processors await another command byte with the ninth bit
set. A list of available commands and the format for
each is shown in Figure 28.
6-316
AP-428
command byte is not for the motor. Since each motor
has a unique address, only the motor receiving the command will respond. Reception of a POSITION command will switch the serial port to mode 3.
Command Table
Command Code
01
Position
Operation
Position motor using either
position PID or Velocity
profile.
Poll
05
Polls motor for current
position.
Motor Up
08
Enters manual mode
turning motor clockwise.
Motor Down
09
Enters manual mode
turning motor counter
clockwise.
Stop
10
Exits manual mode setting
the desired position to the
current position.
Desired position and maximum velocity is sent by .the
master to each slave by a POSITION command. Received data for the position command is stored in a
buffer. After all data has been received,
MAX_VELOCITY and DES_POSITION is loaded
with the values stored in the buffer and the serial port is
switched back to mode 2.
Each command is then checked and appropriate action
taken depending on the received command. Commands
include POSITION, POLL, UP MOTOR, MOTOR
DOWN and STOP. The commands are summarized in
Figure 28.
4.2 Manual Positioning
Position Command
Command Position
01
The receive routine will check for one of three manual
commands: MOTOR UP, DOWN MOTOR or STOP.
A manual flag is used by the software determine if the
motor should be positioned using either a position or
velocity PID algorithm or by manual control. The motor up and motor down commands set the manual flag
which will cause the PWM control to be loaded with a
constant value during the software interrupt routine.
The direction port bit is set to the appropriate value
depending on whether the command is up or down.
The motor will continue to move up or down until a
STOP command is issued by the master controller or
the motor's preset limits are reached.
Maximum
Velocity
4 bytes
2 bytes
Poll Command
I Command I Position I
I 05 I 4 bytes I
Figure 28. Master Commands and Format
4.1 Receive Interrupt Service Routine
Communication between the 80Cl96KB and the main
controller is handled by the serial port routine. Figure
29 shows the flow for the receive interrupt service routine. Upon reception of a byte from the main controller,
a receive interrupt will occur. The RI bit is tested to
ensure a byte has been received. If a byte has not been
received, an error is generated and a return from the
routine is executed. After a valid reception, the ninth
bit is tested to determine if the incoming byte is a command byte or incoming data sent after reception of a
POSITION command.
-If the byte is a command byte, the motor address is
checked by each slave for its own address. The command byte is then echoed back to the master controller
by the appropriate slave. TlIe routine is exited if the
6-317
A stop command will reset the manual flag and set the
controller in automatic mode which employs the PID
algorithm. The destination position gets loaded with
the current position and a return from the receive interrupt is executed. The manual position mode is used by
the master controller to position the motor under keyboard or switch control. This is instead to precise position control of the motor by sending a position command.
4.3 Motor Positioning
Either position control or a velocity profile can be used
to position each motor. The maximum velocity information.stored in the POSITION command determines
the type of method employed. If the maximum velocity
value is nonzero, the velocity PID algorithm will be
applied to position the motor. If the maximum velocity
is zero, position control using the PID algorithm will
be used. This provides for two alternative methods for
positioning the motor.
infef
AP-428
Once a POSITION command is received, the processor
enters serial mode 3 to receive the incoming position
and maximum velocity information. The four bytes of
position data and two bytes of maximum velocity are
retrieved from a six byte storage buffer. A receive count
keeps track of the number of incoming bytes until all
bytes of the six byte frame have been received. If a
frame or overrun error occurs, the motor will shut off
imd a OFFH will be transmitted back to the master
controller to indicate an error condition has occurred.
Otherwise, an 88 is returned to indicate the valid transmission of position and maximum velocity. The manual
flag will be turned off and the appropriate PIO algorithm will be applied on the next software interrupt.
STORAGE(RECLCNT)
. DES_POS
4.4 Master Polling of Position
The master controller can poll each motor controller
for position with a poll command. After reception of
the poll command, a transmit buffer is loaded with four
bytes of position information. Each byte is then transmitted using the transmit interrupt routine.
The flowchart for the routine is shown in Figure 30.
The routine simply tests· the TI flag and continues to
transmit a byte from the buffer until the transmit count
goes to zero. After the count goes to zero, the transmission is complete and processing continues.
=RECEIVE BYTE
=STORAGE(O)
270701-29
Figure 29. Serial Port Receive Interrupt Routine
6-318
inter
Ap·428
PROGRAM SERIAL PORT
FOR MODE 3 TO
RECEIVE INCOMING
POSITION AND TIME DATA
NO
RECEIVE COUNT
=7
270701-30
Figure 29.• Serial Port Receive Interrupt Routine (Continued)
6-319
inter
AP-428
The software used to develop the human interface was
Turbo Prolog and the Tu~bo Prolog Toolbox. The human interface allowed for the programming and movement of the robot by individually controlling each joint
motor. The IBM PC controlled each axis of the robot
by passing commands serially.
RETURN
The IBM PC provides a flexible master controller for
positioning the robot. There are a large number of software languages for developing the control algorithms
and human interface of the master controller. Turbo
Prolog was selected for its low cost and ease of implementation. The control screen and robot programming
language were rapidly developed using the Turbo Prolog. The software and hardware implementation easily
provide for programming and controlling the robot
through a variety of repetitive tasks. A robot using this
control system could easily perform assembly or manufacturing, tasks as shown in Figure 31.
RETURN
270701-31
Figure 30. Serial Transmit Routine
5.0 DISTRIBUTED CONTROL OF
SIX AXIS ROBOT
5.1 Hardware Interface
A
A six axis robot demon~tration system was built using
distributed control of its six motors. The robot is a
RHINO XR-JTM prototype robot designed by
SANDHU Machine Design Inc. Robot motors were
replaced with similar models with high resolution encoders. The robot allows movement along six joints:
base, shoulder, elbow, wrist, hand and fingers., Each
joint is connected to a motor. The system used an IBM
PC acting as a master controller.
, The hardware interface to the robot is shown in Figure
32. Each major joint, elbow wrist, base and shoulder
were controlled with a single 80C196KB using the
PWM and TIMER2 as an up/down counter. The hand
and finger motors used the HSI to track position and
the HSO to generate PWM motor control voltages.
iilllllllHllr:JUmJ
'I
~
270701-32
,
"
Figure 31. Automated Assembly using Distributed Control
6-320
cl
RXD
PWM
TXD
AMP
ABASE
MOTOR
AMP
A
80C196KB
T2UPDN
T2ClK
~
"TI
.
(I)
(,)
RXD
~
TXD-
cD·
C
PWM
::r:J
g..
80C196KB
...
....
0
T2UPDN
C')
0
en
L __
T2CLK
::l
SHOULDER
MOTOR
r-
HSO.O
~
..
..:e
::I:
III
RXD
C.
(I)
m
0"
0
:I':"
.
ELBOW
MOTOR
80C196KB
RXD
T2UPDN
r----l
TXD
T2CLK
iii·
III
OJ
HSI.O
80C196KB
C
(D
I
.j>.
I\)
P1.0
PWM
TXD
III
»
"tI
HAND
MOTOR
RXD
TXD
W !2.
HSO.1
CLKOUT
80C196KB
3
'RXD
TXD
PWM
80C196KB
--q
~
AMP
FINGER
MOTOR
P1.1
T2
HSI.1
WRIST
MOTOR
T2UPDN
T2CLK
270701-33
inter
AP-428
Switches on the robot were fed into 80Cl96KB 1/0
ports to provide a reference position when each motor
starts up. Current sensing for each motor was fed back
to the analog channels to provide an indication of any
overrun or stress conditions. Limits were set for each
motor to prevent the robot joints from entering positions where obstacles or mechanical limitations were
reached.
The software front end developed only the basic features of robotic control to demonstrate the distributed
control of servo motors.
5.3 Control Screen for the Robot
The screen for the control of the robot is shown in
Figure 33. The screen displays a table of the position
and status of each motor, shows the function keys used
to execute commands or enter different modes and displays the keyboard keys for moving each robot joint up
or down. The software has various modes for positioning and programming the robot.
Each motor was given a unique. programming address
for communication back to the master controller. The
master controller sent commands with the address of
whichever joint motor needed to be positioned or
polled. The master 80Cl96KB communicated through
a UART to the IBM-PC.
5.4 Programmed Modes
5_2 Human Interface
To control the robot, the human interface provided a
variety of programming options.
The software features included:
Manual control via the keyboard
Editing robot command files
A Motor Control Command language
Table Display of motor position and status
Manual Programming mode
Table Positioning mode
Motor
The software provides for movement of the robot
through table entry, execution of include command
files or manually using the keyboard. The robot is positioned manually by entering the function key for manual mode and then pressing the predefined key for each
joint motor to move up or down. As each key is released, a STOP command is issued to each motor. The
motors are then polled and the current position updated in the table.
The table function allows for direct entry of the desired
position and maximum velocity to position the motor
when the table function key (Fl) is pressed. After the
Position
Maxval
Status
Base
12345
0
STOPPED
Shoulder
13457
0
STOPPED
Elbow
00282
0
STOPPED
Wrist
00383
0
STOPPED
Hand
11228
0
STOPPED
Fingers
18484
0
STOPPED
F1 F3 F5 F7 F9 -
Functions
Table
F2 Manual
F4 Edit
F6 Home
Fa F10 -
Send
Program
Include
DOS
Exit
Manual Keys
Base
Left
Right
1
2.
Shoulder
Up
Down
3
4
Elbow
Wrist
Up
Down
Up
Down
567
a
Figure 33. Robot Control Screen
6-322
Hand
Left
Right
9
0
Claw
Close Open
inter
AP-428
key is pressed, individual posltloning commands are
sent tb each motor. With maximum velocity set to zero,
the motor is positioned using a position PID. A nonzero maximum velocity would position the motor using
a velocity profile. The final method of positioning allowed for the sending of commands (MOTOR UP,
MOTOR DOWN, STOP, POSITION or POLL) to
each joint in the robot from an include file.
The include mode function key (F6) executes commands stored in a file. The command file can be entered
using an external editor or using the on board editor,
Turbo Prolog. A sample command file is shown in Figure 34. The command file allows for programming of
the robot through a sequence of programmed tasks.
The task of programming the robot is eased by' a manual program mode.
The manual program mode generates a command file
while manually positioning the robot. After pressing
the program key (F4), the program mode is entered and
the robot is moved by pressing the appropriate motion
key for each joint motor. When the robot stops, the
position of the robot is polled and translated into a
position command and stored in a file. As the programmed task is executed, each position of the robot
and the time delay between joint movements is recorded. When the task is complete, the file contains all the
stored position commands necessary to execute the programmed task. The file can be edited with by entering
the edit mode (FS) to fine tune the programmed task or
execute the command file directly. The manual program, command file execution and editing modes allow
for a variety of robotic tasks to be developed and tested
easily.
pos{3,4000,lO)
time (lO)
pos{l,lOOO,2)
time (20)
pos{O,14000,5)
6.0 CONCLUSION
Use of an 80Cl96KB in distributed control of servo
motors has been demonstrated with the effective utilization of the onboard peripherals and high speed math
capability of the 80C196KB. The high performance and
integration of the 80Cl96KB minimized the hardware
interface. The task of controlling the motor resided in
the 80C196KB with the control algorithm residing in
the master. With this approach, the centralized controller can be adapted to the performance requirements of
the system.
Although not implemented, a learn mode could be added to the robot to provide programming using AI techniques. The IBM PC and Turbo Prolog software provided the demonstration vehicle for testing the control
of the robot using distributed control. Use of artificial
intelligence programming to position the robot could be
incorporated with the Turbo Prolog package. The application of a vision system or a more complex control
algorithm could be realized without modification to the
hardware controlling the robot. A more cost effective
solution is obtained by replacing the IBM-PC with one
80C196KB or 80C186 acting as a master controller.
Repetitive tasks programmed using the robot command
language could be stored in tables in the master
80C196KB. The controller would send the stored commands to each motor and communicate, through a serial UART, to the rest of the manufacturing system. The
master 80C196KB controller would then report status
or receive commands. The choice of controller depends
on the needs of the system. Distributed control of servo
motors using the 80C196KB provides for maximum
flexibility in the selection of the control algorithm without modification to the hardware control modules.
move elbow to position 4000 with maximum velocity of 10
delay 10 seconds
move shoulder to pOSition 1000 with maximum velocity of 2
delay 20 seconds
move base to pOSition 14000 with maximum velocity of 5
Figure 34. Sample Robot Command File
6-323
AP-428
REFERENCES
I.
2.
3.
4.
Michael Brady, Robot Motion: Planning and Control (MIT Press, 1982).
C. S. G. Lee, Tutorial on Robotics (2nd edition) (IEEE Computer Society Press, 1989)
Electro Craft Corporation, "DC Motors Speed Controls Servo Systems", 1978.
Proceedings of Conferences on Applied Motion Control, University of Minnesota, J986.
6-324
ARTICLE
REPRINT
AR·515
Many applications have throughput time
requirements on the order of a few hundred
milliseconds, and don't require real-time image
analysis.
A Single-Chip
Image Processor
A.L. Pai and S.H. Lin, Arizona State University, and David P. Ryan, Intel Corporation
M
Ost of the research efforts on
image processing focus on ex·
panding the complexity and dimension of
image analysis. Unfortunately, this em·
phasis results in algorithms that are so
computationally intensive that expensive
special-purpose vector and pipeline processors are required to evaluate an image
fast enough to be considered "real-time."
Not all applications, however, have the
burdensome requirements of true real-life
image analysis. Specifically, applications
that have image throughput time requirements of greater than a few hundred milliseconds can use a lower cost, general-purpose microprocessor-based system. Applications that have even slower frame rates
are candidates for not only the use oflower
cost CPUs, but also allow for replacement
of video-rate flash AID converters with
slower, less expensive converters.
Addressing the most cost-sensitive applications, the design described herein
uses Intel's 16-bit microcontroller to implement a single-chip image processor.
The on-chip 10·bit AID converter of the
controller digitizes the image of a charge
injection device (CID) camera, while the
chip's 16-bit CPU executes a library of
standard vision algorithms and reports the
results by passing a few tokens over an onchip universal asynchronous receiver·
transmitter (UART).
SYSTEM OVERVIEW
A block diagram of the single-chip imSENSORS
June 1987
TERMINAL OR
COMMUNICATION LINK
DRIVERS
SerialUO
inte l®
8096
(12 MHz)
-
wa:
Clw
.9-b
;
a
Input Gray Level
(b) y
255
X
c5 0
o
={~ ~~;h~re
:
X
a
Input Gray Level
(e) Y•
255
{~ ~s~;;";e
In spatial filtering, the pixels adjacent to pixel (x,y) of image plane f are operated upon by
the filter mask operation h. The resulting value of this spatial convolution is used to compute
a replacement gray level intensity value at location (x,y) in the output image g. The following
formula is used:
g(x,y)
= h[f(x,y)] = [WI f(x -I, y'-I)
+ Wz f(x -l,y)
+ W3 f(x-l,y+l) + W4 f(x,y-I) + W5 f(x,y) + W6 f(x,y+l)
+ w7f(x+I,y-l) + wsf(x+l,y).+ w9f(x+I,y+I)]
Various types of filter masks can be used to perform different digital image enhancement
operations. Alow-pass filter uses neighborhood averaging to "smooth" the digital image to
remove noisy pixels_ A high-pass filter accentuates noisy pixels. A high-pass filter accentuates
the higher frequencies present in an image, thus "sharpening" its edges. Operators such as
the Sobel masks can be used to compute the gradient at each point in an image, thus producing a gradient edge-detected image.
Using such filtering methods, the boundaries of objects in an image can be isolated, thus permitting the computation of useful object parameters for object identification and c1assification_
(x-l,y-l)
W,
W,
(x-l,y)
(x-l,y+l)
Y
(x,y)
w.
(x,y-l)
~
(x+l,y-l)
w.
W.
(X,Y)
(x,y+l)
w"
Cx+l,y)
Digital Image f(x,y)
W.
Cx+l,y+l)
X
Ca) A 3 x 3 Pixel Window with
Cb) A 3 x 3 Neighborhood
Around Pixel Cx,y)
Spatial Mask coefficients Wi and
Conesponding Irliage Pixel Locations
Photo 4. A thresholded binary ima&e of the same
square.
7. Castleman, K.R Di&i14l lma&e Prooessin&, Pren-
tice Hall International, Englewood Cliffs, NJ,
1985.
8. Baxes, G_A. Digif41 lma&e Processin&-A Practical Primer, Prentice Hall International,
Englewood Cliffs, NJ, 1984.
/16
[. 1/8
1/8
l/1J
114
1/8
1/16
1
-1
[ -1
9
-J
-1
~1-2]1 ~1 o'~
0 0
1 2
0
1
-2 0
-1 2
2
1
-1
-1
-1
Ce) Sobel Gnadlent Masks
Cd) A High-Pas$ Filter Mask
L-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _....I
1/16
1/8
Ce) A Low-Pass Filter Mask
6-328
SENSORS
June 1987
AR·515
EXAMPLE SHAPE ANALYSIS OUTPUT
OBJECT
PERIMETER
AREA
P
A
C.O.M. COORDINATES
CX,CY
ENCLOSING RECTANGLE
XMA>
XMIN YMAX
RECTANGULARITY
YMIN
R=AO/A R
CIRCULARITY
C=p2/A
CIRCLE
301
m7
(62,68)
111
15
116
21
0.785
12.416
SQUARE
328
fJ3fil
(55,73)
97
14
115
32
1.0
15440
Table I. Example shape analysis output.
A.L. Pai is an Associate Professor and S.H. Lin IS a
Ph. f). candidate in the Computer SCience Dept., Col·
Size Parameters
lege of Engineering, AnzonJ State University, Tempe.
The horizontal and vertical extent of an object and its minimum enclosing rectangle are easily
computed by using the minimum and maximum line and sample numbers.
AZ 85281. David P. Ryan IS a Semor .·\pplicatlom
Engmeer for Intel Corp., 5000 W. Chandler Blvd.,
Chandler, AZ 85226.
The perimeter (circumferential distance) around an object boundary is obtainable from the
boundary chain code by using the formula:
P = NE + VZ No
where NE and No are the number of even and odd steps in the object boundary chain code.
The area of an object, which is a convenient measure of object size, is equal to the number
of picture elements inside and including its boundary, multiplied by the area of a single pixel.
Shape Parameters
In addition to size parameters, shape parameters can be used to distinguish objects. Some
shape parameters that are easily computed are described below.
The formula for computing the rectangularity R of an object is:
R = AO I AR
where Ao is the object area and AR is the area of its minimum enclosing rectangle. R ranges
from 0 to I, with a value of 1.0 for rectangular objects, n/4 (0.785) for circular objects, and
smaller values for slender, curved objects.
The aspect ratio, A, which is the ratio of width to length of the minimum enclosing rectangle
of an object, is used to distinguish slender objects from roughly square or circular objects.
One of the commonly used circularity measures is:
C = p2 I A
the ratio of the square of the object perimeter to its area, which reflects the complexity of
the object boundary. C has a minimum value of 4 n (lZ.56) for a circular object, while more
complex shapes have higher values.
Reprinted from Sensors, June 19117
Copyrlght© 1987 by Helmers Publishing, Inc.
174 Concord St., Peterborough NH 03458
All Rights ReselVed
SENSORS June 1987
6-329
MCS®.-96 Diagnostic Library
7
THE MCS®-96 DIAGNOSTICS
LIBRARY
Version X1.1
David Ryan
INTEL Corporation
October 1987
October 1987
Order Number: 270083-002
© Intel Corporation, 1987
7-1
1.0 INTRODUCTION
In the real time world of microcontroller applications, system failures can be dangerous,
and expensive. Preventing them, and understanding them when they occur, is very important to the reliability of any design~
The sources of a system upset are varied. But in general, the failure of a well designed
application occurs as a result of either some form of noise, or a hardware failure. The
8096 hardware provides methods of detecting and recovering from the transient noise
failures, while the MCS®-96 Diagnostics Library supplies software routines that can help
diagnose or detect a failure in system hardware.
Graceful recovery from noise induced failures is possible using the WATCHDOG TIMER.
While the 8096-based system is functioning as desired, the executing software periodically
resets the WATCHDOG with a special two-byte code. If the WATCHDOG is not reset,
at least every 16 ms (12 MHz system), a system reset occurs. The two-byte code is a
unique password which appears nowhere in the opcode map. This reduces the chance
that an erroneous WATCHDOG reset would occur after a system upset.
The 8096 RESET instruction provides another form of protection. Since the opcode for
a RESET is OffH, protection against the 8096 executing unimplemented external memory
is obtained by placing pull-ups on the system bus. The RESET opcode is also the value
in erased EPROMs. Therefore, any attempt to execute non-existent memory or an erased
EPROM location causes the 8096 to execute the RESET instruction. RESET causes the
8096 to reinitialize itself and provide an external pulse on the RESET pin to reinitialize
the system.
Even with the protection afforded by the 8096, a system is rarely complete without checks
for hardware failures, both internal and external to the microcontroller. These checks are
usually software routines that execute on power-up or periodically to verify that all parts
of the system are present and function correctly. The tests generally execute standard
check algorithms which are simply re-written in the host's assembiy language.
To eliminate the need for every designer of an 8096-based system to write such tests,
a collection of modular routines has been developed that any designer could easily
use in his system (General Diagnostics). In addition, a set of 8096 interrupt service
routines was developed for testing 8096 I/O units in a dedicated environment (The
Dynamic Stability Test). Both scts of programs are contained in the MCS-96
Diagnostics Library (DIAG96.LIB).
This libI1!IY is a collection of software modules that provide a number of ready-made
General Diagnostics and a specialized MCS-96 diagnostic known as the Dynamic Stability Test. The General Diagnostics implement frequently used standard test algorithms,
while the Dynamic Stability Test exercises ~ardware specific to the 8096.
The library can be considered a software "tool box" from which modules are selected
for a variety of run-time diagnostics or laboratory tasks, for example:
•
•
•
•
•
•
Include a few modules in other programs as a power-up test
Use a memory module to create a map of external memory
Use a few modules as a periodic system check
Develop a simple stand-alone tester
Build a custom test bed for bum-in, il!spection or reliability tests
Test new background code in an interrupt intensive environment
7-2
MCS®-96 Diagnostics Library
In addition to easing the development of a program that must perform standard diagnostics
or system checks, the library can be a learning tool. Using the proven source code in the
library, methods of interrupt management and on-chip peripheral handling can be reviewed
to further understand how to use the 8096.
These tests were developed by the 8096 Applications group for experimental use with
the 8096. With the programs in this library, the chip has been studied for its functional
and asygchronous characteristics.
The General Diagnostics should be useful to almost anyone designing an 8096 application. The Dynamic Stability Test will be useful to those experimenting with the 8096
in a test environment. Figure 1 shows the modules in the MCS-96 Diganostics Library.
1. 1 General Diagnostics
The General Purpose Diagnostics consist of 24 programs providing System, ALU and
Memory tests. Each of the tests can be called independently, and none require special
hardware or impose application limiting constraints.
Two Collected Test programs are also provided so that all tests may be called at once.
A third Collected Test program executes a selection of General Diagnostics that might
be reasonable to include in a typical system power-up.
Section 3 provides a detailed description of the General Diagnostics.
1.2 Dynamic Stability Test
The Dynamic Stability Test is an integrated set of II programs that provide the interrupt
service routines necessary to run all forms of MCS-96 110 concurrently while a user
written main task is executing. Virtually all of the chip is made to run simultaneously,
with the 110 units responding to asynchronous external events.
Unlike the General Diagnostics, the Dynamic Stability Test modules must all be linked
together, and must run in a specific external environment.
Section 4 provides a detailed description of the Dynamic Stability Test.
ALU
Tests
System
Tests
Memory
Tests
rALii02\ I"""i.iEMo2\
\~ ~~
'-~ VMtri03"\
~ '-rALuo.i"\ \~
rsYsii1"\
\~
'-----"
(D56A96 )
( D96FST) Collected
( D96P96) Tesls
(MEMOS')
CI"""""MEMo7\
MEM06 '\
'-("i.IEMoB\
C
(
GENERAL DIAGNOSTIC
TESTS
Figure 1. The MCS®-96 Diagnostic Library
7-3
MEM09)
MEMOA '\
I'"MEMoB"\
\~
(
MEMOD)
MCS@-96 Diagnostics Library
1.3 How To Use This Manual
This publication is meant to be a guide for those using any of the programs in the
MCS-96 Diagnostics Library. On a first pass the entire manual should be skimmed,
with more attention paid to Section 2 and the overview sections of Sections 3 & 4. For
the casual reader, the overview sections of each chapter should suffice.
'J
Section 2 contains an overview of the general calling conventions to use any test in
DIAG96.LIB. The section also describes DIAG96.LIB error reporting conventions and
presents some warnings to heed when using this library.
Section 3 describes the classes of General Diagnostics and each test in detail.
Section 4 describes the concept of Dynamic Stability and its implementation on the
8096. The section also contains an overview of the tests performed, a description of the
constraints placed upon the user-written background task, and detailed descriptions of
each interrupt service routine.
The Appendices contain error code and command file descriptions, and of demonstration
program listings. Source for the MCS-96 Diagnostics Library can be obtained from
Insite User's Program Library at the address below. The Insite Catalog order number is
AE-!7.
Insite User's Program Library
INTEL Corporation DV2-24
2402 W. Beardsley Road
Phoenix, Arizona 85027
With the first-hand knowledge that many problems result from not being able to uncover
information lodged in some dark comer of the user manual, information is repeated in
the sections where it is pertinent.
7-4
2.0 USING THE LIBRARY
To simplify use of the diagnostics, the tests were developed in a modular fashion and
collected in one linkable object file library (DIAG96.LIB). A modular program relies
upon only the parameters sent at its invocation and employs standard parameter passing
conventions to allow flexibility and uniformity of use. Collecting the modules into a
library eliminates the tedium of listing twenty or thirty file names when performing a
relocate/link on user developed code. When a program is linked to DIAG96.LIB, only
those modules referenced in the user program are drawn from the library for inclusion
in the output module.
Since PLM96 conventions were the ones chosen for this set of programs, the General
Diagnostics are invoked by following the conventions for a PLM96 typed procedure.
Parameters are placed on the STACK and the procedure activated via a function reference
or explicit CALL. When the test is complete, test data is returned in the special register
PLM$REG. The Dynamic Stability Test is not PLM96 compatible.
The next section describes the format of the test data that is returned by the diagnostics.
Following sections give an overview of how to use a General Diagnostics test, how to
use The Dynamic Stability Test, and what restrictions to keep in mind while using the
library.
2. 1 Reporting ConventiC?n
All DIAG96.LIB tests use the PLM$REG word locations ICH and IEH for returning
condition codes to the calling program. Within DIAG96.LIB, these locations are the
PUBLIC words EREG 1 and EREG2. When a test concludes without finding an error,
a zero is placed in the high byte of EREG 1. If the high byte of EREG I is non-zero,
then some unexpected condition occurred. The low byte of EREG 1 always contains the
module number of the returning test, and EREG2 contains a detail code if an error was
found. The complete listing of EREG 1 code meanings and EREG2 meanings is in
Appendices A & B.
All modules cease execution upon detection of the first error. The code describing which
error was detected CEREGI) follows the format described in Table 1.
Table 1. Error Reporting Format
EREG1 =
where;
and;
nnrnx Hex
nn = 00
= 01, ... ,08H
if no error was found
if an error was found, nn is the error code
rnx = OxH
= 1xH
= 2xH
= 3xH
= 4xH
= 6xH
= 7xH
= 8xH
= 9xH
=OAxH
= OBxH
= OCxH
= ODxH
= OExH
= OFxH
for Test =
SYSOx;
ALUOx;
MEMOx;
D96A96;
DSTISR;
DSTHSI;
DSTHSO;
DSTHIO;
DSTTOV;
DSTEXI;
DSTSER;
DSTA2D;
DSTSWT;
D96FST;
D96P96;
7-5
1.;; x.;; 03H
1.;;x.;;05H
1.;; x.;; ODH
x = 0
x = 0
x = 1
x = 0
x = 0
0.;; x ... 1
x = 0
x = 0
x = 0
0.;; x.;; 1
x = 0
x = 0
MCS®-96 Diagnostics Library
2.2 Using the General Diag'nostics
The General Diagnostics provide a large set of system, ALU and memory tests that can
be used in any combination, independent of system configuration or external circuitry ..
In addition to allowing for a wide flexibility in how a user's system is externally configured,
the tests place minimal requirements on memory maps and interrupt environment.
Except where noted, all tests are interruptible, and maintain Program Status Word and
Interrupt Mask integrity. The tests conform to PLM96 conventions, and require only runtime parameters to be passed for such specifics as memory test bounds and ALU test
duration. To obtain access to the general diagnostics, the user should declare the needed
module names EXTERNAL code segment symbols, and link to:
DIAG9S.LlB
The tests are invoked in assembly language by placing the proper parameters on the
STACK and CALLing the procedure. In PLM, the tests are run after a function reference
is made with the appropriate parameters. The following is an example of an ASM96 call
to a memory test:
PUSH
PUSH
CALL
CMPB
BNE
#4000h
#5000h
MEMOS
EAEG1 +1,0
Error_Found
The diagnostic module called performs a complementary address test on the byte
locations between 4000H and SOOOH inclusive. If an error. is found, the value returned
in the word EREG I will have a non-zero value as its high byte. Also in the case of an
error, the MEM06 memory test will place the address of the error in location EREG2.
The program D96A96, shown in Appendix D is a working ASM96 example that calls
every General Diagnostic Test.
The same memory test could be called in a PLM96 program as
folJ~ws:
Response = MEMOS(4000h,5000h);
IF Error$Codes.Number > 255 THEN CALL Error$Found;
Since the diagnostics return two words in the PLM$REG locations ICH and lEH, the
function MEM06 would be a PROCEDURE of type LONG. Error$Codes would have
to be declared a STRUCTURE AT Response; with the word elements Number and
Detail so that the error messages returned by the diagnostic can be stored. Number
would contain the EREG 1 value returned by the test, and Detail would contain EREG2.
Response would have to be DECLARED a double word. The program D96P96, shown
in Appendix D is a working PLM96 example that calls every General Diagnostic.
The action taken when an error is detected will depend upon the application. For example,
the following Error_Found (or Error$Found) routine would output the error codes to a
printer or terminal:
Error$Found:
Error_Found:
PUSHF
PUSH
#Message_Ptr_A
CALL
Send_String
PUSH
CALL
CALL
EAEG1
Send_Hex_Word
Send_CR_LF
PUSH
CALL
#Message_Ptr _B
Send_String
PROCEDURE;
DISABLE
CALL output (.Message$Ptr$A,
Error$Codes.Number);
CALL output (.Message$Ptr$B,
Error$Codes.Detail);
Self:
(Display continues on next page)
7-6
GOTO Self;
MCS®-96 Diagnostics Library
PUSH
CALL
CALL
EREG2
Send_Hex_ Word
Send_CR_LF
BR $
Message_Ptr_A:
DCB 27,'ERROR FOUND. Error Number = '
Message_Ptr_B:
DCB 22,'Error Detail Code is = '
In the Error_Found routine, it is assumed that the subroutines Send_String, Send_Hex
_Word, and Send_CR_LF transmit appropriate ASCII codes given the parameters
passed to them. Send_String is sent a pointer to a byte string in memory, the first byte
of which is the character count. Send_Hex_ Word converts the word put on the STACK
into the correct four ASCII code bytes and appends the ASCII code for H. Send_CR_
LF outputs the ASCII codes to cause a carriage return, followed by a line feed. The PLM
routine output would perform similar operations.
7-7
MCS@-96 Diagnostics Library
2.3 Using the Dynamic Stability Test
The Dynamic Stability Test consists of a set of 8096 interrupt service routines that
are designed to run while a user-supplied background task executes. The routines are
located in the object file library DST96.LIB, which is contained in the master library
DIAG96.LIB. To obtain access to the test, the user should invoke the batch file
DSTRL.BAT with the background task file name and directory parameters. For
example type:
DSTRL\SOURCE\BACK
Since the interrupt service routines test 8096 on-chip I/O devices, the part under test
must reside in a specified hardware environment. Two such environments are available
for use with the Dynamic Stability Test. The test may run in either a single chip mode,
or a cross-coupled two chip mode. Figures 2 and 3 show the connections required for
each configuration. In the single chip mode, output pins are connected to input pins on
the same 8096. In the dual chip mode, output pins of one 8096 are connected to the
input pins of the other (and vice versa).
To run the test, the user must supply a background task that CALLs an initialization
routine (DSTISR) with the specified parameters. After DSTISR returns, the interrupt
service routines will begin running. The background task can then perform any function
that conforms to the constraints discussed in Section 4. If the user does not wish to
write a special background task, one is provided in the module DSTUSR.
The following is an example CALL and a description of the parameters that must be
passed to the initialization module (DSTlSR).
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
CALL
I
DSTISR
The RAM starting and ending addresses form a memory map for the memory tests that
DSTISR runs. The internal RAM is always tested. The random seed is the starting point
for ALU tests that execute for as many number pairs as is specified in the random test
length parameter. Argument! and argument2 are the operands for a Multiply/Divide test.
The bit pattern parameter is used during a memory test of the internal RAM and the
xpemory segments specified.
Section 4 contains more detailed information on using the Dynamic Stability Test, while
the next section lists some general restrictions and assumptions that need to be understood to properly use any MC8-96 Diagnostic Library module.
7-8
MCS®-96 Diagnostics Library
2.4 Restrictions and Assumptions
Some general restrictions and assumptions need to be understoO<,l before any DIAG96.LIB
programs can be successfully used.
• Pay close attention to the warnings about STACK location in the test modules you
use. If you use any of the specialized internal register tests, make sure that the STACK
is located externally. Do not partition a region of memory that contains your STACK
in any memory test, unless you first move the STACK to an area you already tested.
• All General Diagnostics assume that the WATCHDOG TIMER is either being RESET
by an interrupt service routine created by the user, or that it was never enabled. Only
SYS02 ever locks out interrupts for a significant period of time. The amount of time
they are locked out depends upon the parameters passed.
• The Dynamic Stability Test takes care of the WATCHDOG TIMER within its interrupt
service routines. But, do not write to the WATCHDOG before CALLing the initialization subroutine.
• In any Dynamic Stability application, the user's Main Task should .not lock out interrupts for more than a' few instructions, as the CPU can get quite loaded down with
interrupt requests that are very time dependent.
7-9
3.0 . GENERAL DIAGNOSTICS
The 24 General Diagnostics included in DIAG96.LJB provide a good set of basic memory
and ALU confidence tests that can be easily linked to application programs.
The General Diagnostil;S allow for a wide flexibility in how a user's system is configured
with respect to memory maps and interrupt environment. Except where noted, all tests
are interruptible,. and maintain Program Status Word and interrupt mask integrity. The
tests conform to PLM96 conventions, and require only run-time par!\meters to be passed
for such specifics as memory test bounds and ALU test duration.
The tests are independent to allow specialized diagnostics to be developed as desired.
Use just the quick power-up test (SYS02) to verify operation, or use the module that
calls all General Diagnostics (D96A96) and let it rup continuously for months. A module
that performs th~ most common set of tests is lliso provided (D96FST).
The tests provided are of four classes: System Tests (SYSnn), ALU Tests (ALUnn),
Memory Tests (MEMnn), and Collected Tests (D96xxx). To use any of the modules,
from zero to ten parameters are PUSHed onto $e STACK and the test is CALLed. Results
are returned in the two word registers beginning at #lCH. The symbolic names for these
locations (EREG 1 and EREG2) are made PUBLIC if any DIAG9p.LIB module is linked.
They also may be referenced in PLM$REG for PLM96 programs ..
To obtain access to library modules, the user should declare the needed module names
EXTERNAL code segment symbols, and link to:
DIAG96.LlB
The next few pages contain a brief overview of each of the four classes of tests. Then,
tfIe actions of each test are described in more detail.
$ystem Tests
SYSnn
Common symbol definitions, storage reservations and two common routines are located
in SYSOL A reference to any DiAG96.LIB module will cause SYSOI to be linked.
SYS02 is meant to be called immediately after a RESET. It checks the special function
register status and stack pointer, program sta~s word and timer functionality. SYS03 is
a simple program counter test. It does not test the complete range of the counter, Ill1d
requires external RAM to execute.
SYS01: Common module
SYS02: RESET test
SYS03: Program counter exercise
ALU Tests
AL!Jnn
Five ALU modules are provided for checking ALU functionality. All report errors with
a code in EREGlIEREG2.
Addition and subtraction are exercised in ALUOL A special eight-word add and subtract
7-10
MCS®-96 Diagnostics Library
is executed to test each adder bit with all possible combinations of a bit operation with
and without carry-in.
Unsigned byte multiplication is verified by ALU02. This module simply executes all
possible unsigned byte multiplications. Although not elegant, the test is effective. It takes
six seconds.
A general test of the multiplication and division functions can be made with ALV03.
The module executes all possible combinations of signed and unsigned, byte and word,
two and three operand Multiplies and Divides using a specially selected table of numbers
as operands.
ALU04 extends the ALU03 test by generating pseudo-random test pairs. The user program
simply specifies a seed value for the random number generator, and the number of pairs
to generate.
ALUOS is the core module for multiply/divide tests. Both ALU03 and ALU04 call ALUOS.
The user can also call ALUOS by passing a pair of test arguments. The module executes
all possible combinations of signed and unsigned, byte and word, two and three operand
Multiplies and Divides using the arguments passed as operands.
ALU01:
ALU02:
ALU03:
AL!J04:
ALU05:
Table-driven Addition/Subtraction
MULUB (all possible arguments)
Table-driven Multiply/Divide
Pseudo-random Multiply/Divide
Multiply/Divide core module
Memory Tests
MEMnn
The DIAG96.LIB MEMnn modules provide tests for register space, external RAM, and
ROM. The algorithms used include: walking and galloping ones; walking and galloping
zeros; checkerboard patterns; complementary addressing; and checksum verification.
The register tests are in MEMO I-MEMOS , and MEMOC. With the exception ofMEM04,
the register tests save the contents of all internal registers except PLM$REG on the
STACK before testing, and restore the data when done. If a faulty location is found, its
address is reported. MEM04 is a utility which returns the number of bits set in a specified
operand.
The external RAM tests are located in MEM06-MEMOA, and MEMOD. They all return
a two-word code upon completion. The calling program must partition the RAM to be
tested before calling an external RAM test.
Table 2. Memory Tests
Algorithm
Complementary Address
Walking Ones
Walking OneS/Zeros
Galloping Ones
Galloping Ones/Zeros
Bit Counter
Checkerboard Pattern
User Specified Pattern
Checksum
Internal Registers
External RAM
MEM01
MEM06
MEMO?
MEM09
MEMOS
MEMOA
MEM02
MEM03
MEM04
MEM05
MEMOC
MEMOB
7-11
MEMOD
MEMOB
ROM
MEMOS
MCS@·96 Diagnostics Library
Collected Tests
D96xxx
The D96xxx set of modules collects together all, or several, of the General Diagnostics
and performs them according to the parameters passed. D96A96 is an ASM96 module
that calls all tests. D96P96 is a PLM96 module that calls all tests. D96FST is an ASM96
module that calls a logical selection of tests.
D96A96: All tests
I ASM96
D96P96: All tests
/ PLM96
D96FST: Selection of tests I ASM96
7-12
MCS®-96 Diagnostics Library
3.1 System Tests
Common Symbols (SYS01)
Brief Description:
This module contains the global symbol declarations and five utilities used by the General
Diagnostics.
Assembly Language Calling Sequence:
Get_Psw
CALL
or
Put_Psw
CALL
or
Get_Parms
CALL
or
Stack_Ram
CALL
or
CALL
Restore_Ram
Get_Psw Action:
=
USER_PSW : PSW
EREGI
:= 0
EREG2
: = Offffu
Put_Psw Action:
PSW :
= USER_PSW
Get_Parms Action:
PARM2 : = Last Parameter
put on the STACK
PARMI: = Next to last parameter
put on the STACK
USER_PSW : = PSW
EREG I
: = Offfu
EREG2
: = OOOOh
Stack_Ram Action:
Restore_Ram Action:
PUSH laH;
Ptr:= 20H
Do While Ptr< 100h;
PUSH [Ptr) +
End While;
Ptr: = Ofeh;
Do While Ptr> leh;
POP [Ptr);
Ptr: = Ptr-2;
End While;
POP laH;
Detailed Description:
A call to any General Diagnostic module will cause SYSOI to be linked. This module
contains the definition of 4 words of memory used by every module to report errors and
store temporary parameters. The STACK routioes are used by the internal register tests
to save and restore the data in the registers when called. It also INCLUDES an expanded
8096.1NC file to provide the PUBLIC declarations of commonly used symbols for the
special function registers and constants such as CR and LF.
Nearly all General Diagnostic modules use the routines in SYSOI to save the PSW when
called, restore the PSW when returning control to the calling routine, save parameters
from the STACK, and initialize the error registers.
7-13
MCS@·96 Diagnostics Library
System Power-up (SYS02)
Brief Description:
This test is a quick check of the Program Status Word, TIMERI, 10SO,IOSI and the
Interrupt Pending Register. It is meant to be called just after a RESET.
Assembly Language Calling Sequence:
CALL
SYS02
When Test Passes:
EREGI : = 0OO2h
EREG2 : = OOOOh
IT Test Fails:
EREGI : = 0102h on unexpected 10SO or 10SI EREGI : = 0202h if TIMER 1 does not change EREGI : = 0302h if Zero register failed
EREGI : = 0402h if PUSHFIPOPF failed
EREGI : = 0502h if Sticky bit failed
-
EREGI : = 0602h if Carry Flag failed
EREGI : = 0702h on an overflow flag error
-
EREGI : = 0802h if Int. Pending byte failed
-
EREG2 : = 10SO in low byte
10S1 in high byte
EREG2 : = TIMERI
EREG2 : = PSW at Failure
EREG2 : = erroneous value
found
EREG2 : = 3fffh if bit did not
set
: = OOOOh if bit did not
clear
EREG2 : = xxxxh
EREG2 : = 0002h if flags set
wrong
: = xxxxh flags cleared
. wrong
EREG2 : = offending Int. Pend.
value
Detailed Description:
This module verifies that TIMER I is changing, then attempts to change the value in the
ZERO register. Then, a set of PUSHFs and POPFs is done with test values to verify
correct action of these instructions. The carry, sticky and overflow bits in the program
status word are then tested. Finally, the Interrupt Pending register bits are tested for their
ability to be set and cleared. Any unexpected result is reported.
Any error found having to do with the PUSHF/POPF instructions or the PSW, ipcluding
Interrupt Pending, will cause interrupts to be disabled before, returning to the calling
module.
7-14
MCS®-96 Diagnostics Library
Program Counter (SYS03)
Brief Description:
This test writes code into a user selected partition of RAM and executes the code. Elapsed
time and special registers are checked for correctness.
Assembly Language Calling Sequence:
PUSH
PUSH
CALL
SYS03
When Test Passes:
If Test Fails:
EREG 1 : = 0003h
EREG2 : = OOOOh
EREGI : = O103h if test code returned early
EREG2 : = Early time
EREGI : = 0203h if test code returned late
EREG2 : = Late time
EREGI : = 0303h if count register is incorrect
EREG2 : = erroneous counter value
Detailed Description:
This module accepts starting and ending addresses for an external RAM partition, adjusts
the boundaries to be double word aligned, and writes three lines of code repeatedly into
the partition. The code that is written increments a counter then executes two NOPs every
12 state times. The last byte written into the RAM partition is a RET opcode.
After the RAM partition is adjusted and the code written into the RAM, the test puts a
return address on the STACK, stores TIMER I and CALLs the first byte of the RAM.
When the last byte of RAM is executed, program control returns to SYS03. TIMER! is
again stored. The test then compares the elapse,d time to the expected elapsed time. The
value remaining in the counter is also checked for correctness. Any deviations from
expected are reported.
Caution: Since interrupts are locked-out while the code in RAM is executing, partitioning
more than 4000h bytes of RAM for this test could cause a WATCHDOG TIMER overflow
if the watchdog was started before SYS03 is called.
7-15
MCS®-96 Diagnostics Library
3.2 ALU Tests
Add/Subtract (ALU01)
Brief DescriIJtion:
This routine adds then subtracts two carefully selected eight-word variables and verifies
the results.
'
Assembly Language Calling Sequence:
CALL
ALU01
When Test Passes:
If Test Fails:
EREGI := OOllh
EREG2 : = OOOOh
EREGI : = Ollih on an addition error
:= 0211h on a subtraction error
: = 03l1h on a flag error
EREG2 : = offending argument on error
Detailed Description:
Two eight~word operands are added together and the results verified. Then, the operands
are subtracted and verified. The operands were chosen to exercise every possible combination of two bits and a carry into each bit of the adder. Correctness of the result and
the resultant flags is verified.
The operands are:
05555AAAA5555AAAAFFFFOOOOAAAA5555H
+05555AAAAAAAA5555FFFFOO005555AAAAH
OAAAB555500000000FFFEOOOOFFFFFFFFH
05555AAAAAAAA5555FFFFOOOO5555AAAAH
- OAAAA5555AAAA55550000FFFF5555AAAAH
OAAAB 555500000000FFFEOOOOFFFFFFFFH
Some versions of SIM96 do not pass this test.
7-16-
MCS®-96 Diagnostics Library
MULUB (ALU02)
Brief Description:
This module simply tests the MULUB instruction for all possible combinations of byte
multipliers and multiplicands.
Assembly Language Calling Sequence:
CALL
ALU02
When Test Passes:
If Test Fails:
EREGI : = OOl2h
EREG2 : = OOOOh
EREG 1 : = 0112h on an error
EREG2 : = multiplier/multiplicand
Detailed Description:
This test executes all possible combinations of operands into the MULUB instruction.
Results are verified through a method of addition and subtraction as operands cycle. The
status of PSW flags is not verified in this routine.
Multiply/Divide Table (ALU03)
Brief Description:
This module sends a specially constructed table of operands through the general Multiply/
Divide Core test (ALU05).
Assembly Language Calling Sequence:
CALL
ALU03
When Test Passes:
If Test Fails:
EREGI := 0013h
EREG2 : = OOOOh
EREGI : = 0115h on a signed error
: = 0215h on an unsigned error
: = 0315h on a flag error
EREG2 : = offending argument on error
Detailed Description:
This test sends a table of operands through the Multiply/Divide Core test. The 18 operands
were selected to exercise all of the hardware multiply and divide control signals.
The operands are:
Arg.1,Arg.2
Arg.1,Arg.2
1D99H,
OFFFFH
9D99H,
5555H
OE266H, OAAAAH
1D99H,
5555H
9D99H, OAAAAH
OE266H, OFFFFH
0063H,
0055H
OOAAH
0066H,
0063H,
OOFFH
OFFFH,
9D99H
5555H,
OE266H
OAAAAH, 1D99H
5555H,
9D99H
OAAAAH, OE266H
OFFFFH,
0063H
0055H,
0066H
OOAAH,
0063H
Some versions of SIM96 wi\1 not pass this test.
7-17
MCS®-96 Diagnostics Library
Multiply/Divide Random (ALU04)
Brief Description:
This module is a pseudo-random number generator that sends pairs of arguments to the
Multiply/Divide Core test (ALU05).
Assembly Language Calling Sequence:
PUSH
PUSH
CALL
ALU04
When Test Passes:
If Test Fails:
EREGI : = OOl4h
EREG2 : = OOOOh
EREG 1 : = Oll5h on a signed error
: = 0215h on an unsigned error
: = 0315h on a flag error
EREG2 : = offending argument on error
Detailed Description:
This module first executes the table driven Multiply/Divide test (ALU03). Then, if passed,
pseudo-random argument pairs are generated and fed into the generalized Multiply/Divide
Test (ALU05). The parameters passed to ALU04 set the random number seed, and the
duration of the test.
There is no restriction on the values passed to the test. However, it must be noted that
all possible combinations of signed and unsigned, byte and word, two and three operand
Multiply/Divides are done at least twice for each pair of arguments sent to ALU05. Each
such test takes from 1 to 5 milliseconds depending upon the arguments. Therefore, if
large values for the count parameter are selected, the test will be long. For example,
lOOOh as a count will take about 12 seconds, depending upon the seed. NOTE: Some
versions of SIM96 will not pass this test.
The formula used to generate the number pairs is as follows:
X(n+1)= [(0101h + 0001 h) * X(n) + 0001 h) MOD Offffh
where X(O) = seed
7-18
MCS®-96 Diagnostics Library
Multiply/Divide Core (ALU05)
Brief Description:
This test perfonns a Divide/re-Multiply sequence for all possible combinations of two or
three operand, signed or unsigned, byte or word operations using the arguments passed
to it as operands. The results are verified.
Assembly Language Calling Sequence:
PUSH
PUSH
CALL
ALU05
When Test Passes:
If Test Fails:
EREGI : = OOl5h
EREG2 : = OOOOh
EREGI : = O1l5h on a signed error
: = 02l5h on an unsigned error
: = 03l5h on a flag error
EREG2 : = offending argument on error
Detailed Description:
This module takes arguments from a calling program and perfonns upon them all possible
combinations of byte or word, two or three operand, signed or unsigned multiplication
and division. Argument2 is used to create the high and low words for a word Divide,
and the low byte of Argumentl is used as the divisor in a byte Divide.
The test checks multiplication and division by first dividing one operand by the other,
then multiplying the quotient by the divisor and adding the remainder. If the result is the
original dividend, the operations were correct. However, the possibility of legitimate
division overflows must also be considered.
The test first perfonns a division and checks,flag status for correct indication of overflow
conditions. If there has been an overflow, the dividend is right shifted by one, the expected
result is updated, and the division is perfonned over. If a division by zero occurred, just
the expected result is corrected and the test is continued.
After a division and overflow checklfixup is complete, a re-multiplication occurs and the
result verified. Flag status is also verified. If the results are correct, the original operands
are reloaded into the test operand registers and the next Divide/re-Multiply combination
is begun.
All Divide/Multiply combinations are perfonned twice. Once with flags set upon entry,
and once with flags clear upon entry.
CALLing ALU03 will run a specially selected table of operands through this test. CALLing ALU04 will run a pseudo-random string of operands through this test.
7-19
MCS®-96 Diagnostics Library
3.3 Memory Tests
Complementary Address (MEM01)
(for registers)
Brief Description:
This module performs a complementary address test on the registers locations lab to
Offh.
Assembly Language Calling Sequence:
CALL
MEM01
When Test Passes:
If Test Fails:
EREGI : = 0021h
EREG2 : = OOOOh
EREGI : = Ol2lh
EREG2 : = address of the error
Detailed Description:
This module performs a simple address and integrity test on register locations lab-Offh.
The algorithm stores the value NOT(ADDRESS) in the location pointed to by ADDRESS
for the range, then loops through memory again to verify the contents.
Caution: If the STACK is partially internal, the STACK POINTER must be pointing at
least 260 bytes into external RAM at the time MEMOI is called. The STACK cannot be
entirely internal. The arithmetic flags in the PSW are undefined after execution of MEMO I.
7-20
MCS®-96 Diagnostics Library
Walking Ones/Zeros (MEM02)
(for registers)
Brief Description:
This module performs a Walking Ones and Zeros test on the internal registers lah-Offh.
Assembly Language Calling Sequence:
CALL
MEM02
When Test Passes:
If Test Fails:
EREG 1 : = 0022h
EREG 1 : = OOOOh
EREGI : = 0122h
EREG2 : = address of the error
Detailed Description:
This module performs a Walking Ones and Zeros test on the internal registers.
The Walking Ones memory test first loads zero in all locations to be tested. Then, ones
are placed in the first byte of memory, followed by a verification of all locations. Next,
the first location is zeroed and ones are loaded into the second location. All memory is
again verified. This process continues until all locations have been loaded with ones.
The Walking Zeros memory test works exactly like Walking Ones, except that a zero is
"walked" through memory filled with ones, instead of ones being walked through a
memory filled with zeros .
. Caution: If the STACK is partially internal, the STACK POINTER must be pointing at
lest 260 bytes into external RAM at the time MEM02 is called. The STACK cannot be
entirely internal. The arithmetic flags in the PSW are undefined after execution of MEM02.
7-21
MCS®-96 Diagnostics Library
Galloping Ones/Zeros (MEM03)
(for registers)
Brief Description:
This
modul~
performs a Galloping Ones and Zeros test on the internal registers lah-Offh.
Assembly Language Calling Sequence:
'CALL
MEM03
When Test Passes:
If Test Fails:
EREG 1 : = 0023h
EREG2 : = OOOOh
EREGI : = 0l23h
EREG2: = address of the error
Detailed Description:
This module performs a Galloping Ones and Zeros test on internal registers.
The Galloping Onys algorithm tests memory by first loading zeros into alliocati,ons. Then
ones are loaded into the first byte and all memory is verified. The verification is done
by alternating reads to the first location and locations through all memory. Next, ones
are placed in the second location without altering the first. Verification is again performed
by alternating reads to the second location and the rest of memory. This process continues
until all locations contain ones.
The Galloping Zeros test is similar to Galloping Ones, except that zeros slowly fill a
memory filled with ones. In Galloping Ones, ones slowly fill a memory filled with zeros.
Caution: If the STACK is partially internal, the STACK POINTER must be pointing at
least 260 bytes into external RAM at the time MEM03 is callyd. The STACK cannot be
entirely internal. The arithmetic flags in the PSW are undefined after execution of MEM03.
Bits Set (MEM04)
Brief Description:
This module returns the number of bits set in the parameter passed to the routine.
Assembly La..,guage Calling Sequence:
PUSH
CALL
test_value
MEM04
When All Bits Zero:
When One or More Bits Set:
EREGI : = 0024h
EREG2 : = OOOOh
EREGI := 0124h
EREG2 : = number of bits set
Detailed Description:
This module returns the number of bits that are set in the low byte of the parameter
passed to the test. Any addressing mode may be used to put a value on the STACK, but
the parameter on the STACK is treated as an immediate value.
7-22
MCS®-96 Diagnostics Library
Checkerboard Pattern (MEMOS)
(for registers)
Brief Description:
This module performs a Checkerboard Pattern test on the internal registers lah-Oftb.
Assembly Language Calling Sequence:
CALL
MEM05
When Test Passes:
If Test Fails:
EREGl : = 0025h
EREG2 : = OOOOh
EREGI : = 0125h
EREG2 : = address of the error
Detailed Description:
This module performs a checkerboard test on the internal registers. A checkerboard pattern
of ones and zeros is written into the physical rows and columns of the 8096 register
space. As the pattern is being written, it is repeatedly verified. After the entire pattern
is in place, the memory is verified again, complemented, and re-verified.
Caution: If the STACK is partially internal, the STACK POINTER must be pointing at
least 260 bytes into external RAM at the time MEM05 is called. The STACK cannot be
entirely internal. The arithmetic flags in the PSW are undefined after execution of MEM05.
Complementary Address (MEMOS)
Brief Description:
This module performs a complementary address test on the memory partitioned by user
supplied pointers.
.
Assembly Language Calling Sequence:
PUSH
PUSH
CALL
MEM06
When Test Passes:
If Test Fails:
EREG 1 : = 0026h
EREG2 : = OOOOh
EREGI : = 0126h
EREG2 : = offending address
Detailed Description:
This module performs a simple address and integrity test on RAM locations partitioned
by the parameters passed. The algorithm stores the value NOT(ADDRESS) in the location
pointed to by ADDRESS for the range, then loops through memory again to verify the
contents.
Caution: Do not partition RAM that contains valid STACK elements.
7-23
MCS@-96 Diagnostics Library
Walking Ones (MEM07)
Brief Description:
This module performs a Walking Ones Test on the memory partitioned by the user.
Assembly Language Calling Sequence:
PUSH
PUSH
CALL
MEM07
When Test Passes:
If Test Fails:
EREGI
0027h
EREG2 .- OOOOh
EREGI .- Ol27h
EREG2
offending address
Detailed Description:
This module performs a Walking Ones test on the memory partitioned by the calling
program. The Walking Ones memory test first loads zero in all locations to be tested.
Then, ones are placed in the first byte of memory, followed by a verification of all
locations. Next, the first location is zeroed and ones are loaded into the second location.
, All memory is again verified. This process continues until all locations have been loaded
with ones.
Caution: Do not partition RAM that holds valid elements of the STACK. And, execution
time increases non"linearly with memory partition widths.
Galloping Ones (MEMOS)
Brief Description:
This module performs a Galloping Ones test on memory partitioned by the calling
program.
Assembly Language Calling Sequence:
PUSH
PUSH
CALL
MEMOS
When Test Passes:
If Test Fails:
EREGI .- 0028h
EREG2
OOOOh
EREGI
Ol28h
EREG2 .- offending address
Detailed Description:
This module performs a Galloping Ones test on memory locations partitioned by the
calling program.
'
The Galloping Ones algorithm tests memory by first loading zeros into all locations. Then
ones are loaded into the first byte and all memory is verified. The verification is done
by alternating reads to, the first location and locations through all memory. Next, ones
are placed in the second location without altering the first. Verification is again performed.
by alternating reads to the second location and the rest of memory. This process continues
until all locations contain ones.
Caution: Do not partition locations that contain valid elements of the STACK. And,
execution time increases non-linearly with memory partition widths.
7-24
MCS®-96 Diagnostics Library
Walking Ones/Zeros (MEM09)
Brief Description:
This module performs a Walking Ones and Zeros test on the memory locations partitioned
by the calling program.
Assembly Language Calling Sequence:
PUSH
PUSH
CALL
MEM09
When Test Passes:
EREGl .- 0029h
·EREG2
OOOOh
If Test Fails:
EREGl .- Ol29h
EREG2
offending address
Detailed Description:
This module performs a Walking Ones and Zeros test on the memory partitioned by the
calling program.
The Walking Ones memory test first loads zero in all locations to be tested. Then, ones
are placed in the first byte of memory, followed by a verification of all locations. Next,
the first location is zeroed and ones are loaded into the second location. All memory is
again verified. This process continues until all locations have been loaded with ones.
The Walking Zeros memory test works exactly like Walking Ones, except that a zero is
"walked" through memory filled with ones, instead of ones being walked through a
memory filled with zeros.
Caution: Do not partition RAM that contains valid elements of the STACK. And,
execution time increases non-linearly with memory partition widths.
7-25
MCS®-96 Diagnostics Library
Galloping Ones/Zeros (MEMOA)
Brief Description:
This module performs a Galloping Ones and Zeros test on the memory locations partitioned
by the calling program.
Assembly Language Calling Sequence:
PUSH
PUSH
CALL
MEMOA
When Test Passes:
If Test Fails:
EREGI
002Ah
EREG2 .- OOOOh
EREGI := 012Ah
EREG2 : = offending address
Detailed Description:
This module performs a Galloping Ones and Zeros test on memQry partitioned by the
calling program.
The Galloping Ones algorithm tests memory by first loading zeros into all locations. Then
ones are loaded into the first byte and all memory is verified. The verification is done
by alternl!ting reads to the first location and locations through all memory. Next, ones
. are placed in the second location without altering the first. Verification is again performed
by alternating reads to ~he second location and the rest of memory. This process continues
until all locations contain ones.
The Galloping Zeros test is similar to Galloping Ones, except that zeros slowly fill a
memory filled with ones. In Galloping Ones, ones slowly fill a memory filled with zeros.
Caution: Do not partition RAM that contains valid elements of the STACK. And,
execution time incr~ases non-linearly with memory partition widths.
Checksum (MEMOB)
Brief Description:
This module calculates a i 6 bit checksum for the memory partition specified by the calling
program.
Assembly Language Calling Sequence:
PUSH
PUSH
.
MEMOB
CALL
Test Returns:
EREGI
EREG2 . -
012bh
16-bit checksum
Detailed Description:
This module performs a 16-bit checksum on the region of memory partitioned by the
calling program. RAM or ROM may be partitioned. The module is non-destructive to
RAM.
7-26
MCS®-96 Diagnostics Library
User Pattern (MEMOC)
(for registers)
Brief Description:
This module performs a Checkerboard Pattern test on the internal registers lah-Offh with
a user specified bit pattern.
Assembly Language Calling Sequence:
PUSH
CALL
MEMOC
When Test Passes:
If Test Fails:'
EREG 1 . EREG2 . -
EREGI
EREG2
002Ch
OOOOh
012Ch
address of the error
Detailed Description:
This module performs a checkerboard test on the internal registers with the bit pattern
specified by the calling program. The pattern is written into the physical rows and columns
of the 8096 register space. As the pattern is being written, it is repeatedly verified. After
the entire pattern is in place, the memory is verified again, complemented, and re-verified.
Caution: If the STACK is partially internal, the STACK POINTER must be pointing at
least 260 bytes into external RAM at the time MEMOC is called. The STACK cannot be
entirely internal. The arithmetic flags in the PSW are undefined after execution of
MEMOC.
User Pattern (MEMOD)
Brief Description:
This module performs a Checkerboard Pattern test on a specified region of memory with
a specified pattern of bits.
Assembly Language Calling Sequence:
PUSH
PUSH
PUSH
CALL
MEMOD
When Test Passes:
If Test Fails:
EREG 1 . EREG2 . -
EREGI : = 012dh
EREG2 : = offending address
002dh
OOOOh
Detailed Description:
This module performs a checkerboard test on a region of memory that is specified by the
calling program using a bit pattern which is also specified. First, the pattern is written
into memory. As the pattern is being written, it is repeatedly verified. After the entire
pattern is in place, the memory is verified again, complemented, and re-verified.
Caution: Do not partition RAM that contains valid elements of the STACK.
7-27
MCS@·96 Diagnostics Library
3.4 Collected Tests Modules
ALL Tests in ASM96 (D96A96)
Brief Description:
This ~odule causes every General Diagnostics test to execute.
Assembly Language Calling Sequence:
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
CALL
D96A96
When Tests All Pass:
When a Test Fails:
EREGI : = 0030h
EREG2 : = code checksum
EREG 1 : = test module error code
EREG2 : = test module detail code
Detailed Description:
This module calls all General Diagnostics using the parameters passed by the calling
program. The parameters needed by the test for proper execution specify two areas of
external RAM for memory tests, the ending address of code to be checksummed, the
seed and length of the random ALU test, two specific arguments to do the Multiply/
Divide Core test, and a bit pattern for memory tests.
Execution speed of this test is highly· dependent upon the memory partitions and the
length requested for the random ALU test. For example, partitioning lk and 8k regions
of memory, and calling for lOOOh random ALU tests, the test takes 3 hours to complete.
Testing smaller regions of memory (i.e. lk and lk) can reduce test time to a few minutes.
Caution: An external STACK must be used with this test, and it must be in a part of
memory outside that partitioned during the CALL.
7-28
MCS®-96 Diagnostics Library
ALL Tests in PLM96 (D96P96)
Brief Description:
This module causes every General Diagnostics test module to execute.
PLM96 Calling Sequence:
D96P96(RAM segment1 starting address,
RAM segment1 ending address,
RAM segment2 starting address,
RAM segment2 ending address,
random seed, random test length,
top of code address,
argument1 for Multiply/Divide Core test,
argument2 for Multiply/Divide Core test,
bit pattern for memory tests);
When All Tests Pass:
When a Test Fails:
PLMREG
. - OOFOh
PLMREG+2 := 16-bit checksum
PLMREG
. - module error code
PLMREG + 2 : = module detail code
Detailed Description:
This module calls all General Diagnostics using the parameters passed during invocation.
The parameters needed by the test for proper execution specify two areas of external
RAM for memory tests, the ending address of code to be checksummed, the seed and
length of the random ALU test, two specific arguments to do the Multiply/Divide Core
test, and a bit pattern for memory tests.
Execution speed of this test is highly dependent upon the memory partitions and the
length requested for the random ALU test. For example, partitioning lk and 8k regions
of memory, and calling for lOOOh random ALU tests, the test takes 3 hours to complete.
Testing smaller regions of memory (Le. lk and lk) can reduce test time to a few minutes.
In his program, the user will have to DECLARE D96P96 an external procedure of the
LONG type, with its parameters declared SLOW. The EREG 1 and EREG2 values reported
by library modules are placed in the long-word location at PLM$REG.
The DECLARations in D96P96 show how anyone General Diagnostic Module could be
called from a PLM96 program. Each needed module needs to be DECLAREd an external
procedure of the LONG type.
Caution: An external STACK must be used with this test, and it must be in a part of
memory outside that partitioned during the CALL.
7-29
MCS®-96 Diagnostics Library
Selected Tests in ASM (D96FST)
Brief Description:
This is an ASM module that invokes a selected set of General Diagnostic tests.
Assembly Language Calling Sequence:
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
CALL
,
D96FST
When Tests All Pass:
When a Test Fails:
EREGI
OOEOh
EREG2 . - code checksum
EREGI : = test module error code
EREG2 : = test module detail code
Detailed Desc,":iption:
This module calls the Power-up and Program Counter tests then all ALU tests. Then,
Complementary Address, Galloping Ones/Zeros and Checkerboard tests are run on the
internal registers. Finally, Complementary Address and specified pattern tests are done
on external memory and the program is checksummed.
The parameters needed by the test for proper execution specify two areas of external
RAM for memory tests, the ending address of code to be checksummed, the seed and
length of the random ALU test, two specific arguments to do the MultiplylDivide Core
test, and a bit pattern for memory tests.
Execution speed of this test is highly dependent upon the memory partitions and the
length requested for the random ALU test. For example, partitioning lk and 8k regions
of memory, and calling for lOOOh random ALU tests, the test takes about 20 seconds to
complete. Testing smaller regions of memory (i.e. lk and lk) can reduce test.time further.
Caution: An external STACK must be used with this test, and it must be in a.part of
memory outside that partitioned during the CALL.
7-30
4.0 THE DYNAMIC STABILITY TEST
The Dynamic Stability Test is a set of interrupt service routines designed to run over a
user's background task in either one stand alone 8097, or two 8097s that are crosscoupled. In the stand alone mode, the chip's output pins are hooked to its input pins.
In the dual chip mode, each controller's output pins are tied to the input pins of the
other. The minimum configuration for each mode are shown in Figures 2 and 3. See
Figure 11 for the circuit diagram of a board that can be jumpered for either
configuration.
What is Dynamic Stability?
A '~Dynamic Stability" test was developed to enable testing of the 8097 in an asynchronous environment. In the one chip mode, HSO events are synchronized with the HSI
PORT 1.0 1 - - -...
PORT 1.1
PORT 1.2
PORT 1.3
PORT 1.4
PORT 1.6
PORT 1.51--+-..1
PORT 1.7
TXO
RXD
HSI.O
HSI.l
HSI.2 I--t-t-,
HSI.3 1---+--+-1--,
PWM
EXTINT
8097
HSO.O
HSO.l
HSO.2 1 - - -.......
HSO.31----.......
+5 Vdc
OPTIONAL
T2CLK I--------f
T2RST
PORT 2.7 t-+--lXl--,
10k
VREF
10k
.1,..
10k
10k
t-;::I:::t=::1
ACH.O
ACH.l
ACH.2
ACH.3
ACH.4
ACH.5
....+---lACH.6
ACH.7
+SVdc
AGND
10k
Figure 2. 8097 Strapback Configuration Single Chip Mode
7-31
MCS@-96 Diagnostics Library
event capture logic. However, in the cross-coupled mode, HSO events generated by one
chip are captured in the HSI unit of another. As long as separate, non-syncronized clock
sources are used for each chip, the HSI line events will occur asynchronously to the chip.
To implement a test that could be either stand alone or co-resident without modification, the creation and verification of I/O events needed to be decoupled.. Thus the basic
structure of the Dynamic Stability Test takes the form of a set of I/O Producers causing
events that I/O Consumers verify. Figure 4 gives a macro vieW of the Producer/
Consumer relationship.
PORT 1.7
PORT 1.0
PORT 1.1
PORT 1.5
PORT 1.6
I
PORT 1.2
PORT 1.3
PORT 1.4
PORT 1.4
PORT 1.3
PORT 1.5
PORT 1.6
RXD
HSI.O
HSI.1
HSI.2
PORT 1.1
I
I
PORT 1.7
TXD
rr- h
HSI.3
PWM
PORT 1.2
PORT 1.0
TXD
I
RXD
J::
I
r- 1-1
HSO.O rHSO.1
EXTINT
HSO.2
HSO.3
r-I-
L t-t-
p
HSI.O
HSI.1
HSI.2
HSI.3
PWM
'-- HSO.O
C
HSO.1
EXTINT
HSO.2
HSO.3
8097
___ OPTIONAL _
8097
{Jlr
T2CLK
T2RST
PORT 2.7
~
~D
AGND
537.6 Khz
,,1/
.....
~/
"L..;..:.
I
ACH.O
Jlr1
537.6 Khz J
+5 Vdc
T2CLK
~
T2RST
PORT 2.7
ACH.O
ACH.1
ACH.2
ACH.1
ACH.2
ACH.3
ACH.3
ACH.4
ACH.5
ACH.4
ACH.6
ACH.7
ACH.6
ACH.7
ACH.5
VREF
VREF
AGND
.11"_*
+5Vde
10k
10k
10k
10k
10k
Figure 3. 8097 Strapback Configuration Dual Chip Mode
7-32
ri7
MCS®-96 Diagnostics Library
Figure 4. Producer/Consumer Relationship
What Does the Test Do?
Producer/Consumer exchanges were defined to test nearly all of the 8097 I/O capabilities
concurrently. Following initialization, the transactions described are carried out by the
set of interrupt service routines that make up the Dynamic Stability Test. The following
section describes the test initialization. Then the tests performed are briefly described in
the Producer/Consumer framework.
Initialization
To get the ball rolling, the background task must first CALL an initialization routine
(DSTISR). This routine clears memory, executes the Selected Tests program (D96FST)
from the General Diagnostics, and checks for the presence of an external clock on
T2CLK. The serial port is then initialized for internal or external baud rate generation
based on the presence of an external clock, and sign on messages are sent over the serial
channel.
After initial tests are complete, and just prior to initiation of the interrupt service routines,
a pulse is sent out on PORT1.3 that is used to synchronize controllers in the two chip
mode. (See Figure 5.) Remember that the objective of the Dynamic Stability Test is to
test the controllers asynchronously. Therefore, the synchronization is only done to insure
that neither controller starts testing before both are ready to begin.
When a controller is ready to synchronize, it places a 0 on the PORTl.3 pin and looks
for a 0 on its PORTI.4 pin. When a 0 is seen, the chip delays 600 microseconds, and
then PORTl.3 is set high. The chip then loops until PORTI.4 also goes high. Another
delay is inserted, and the tests begin. The worst skew between two controllers that can
SYNCHRONIZATION SEQUENCE IN THE DUAL CHIP MODE
Pl.3A
Pl.4B
Pl.4A
Pl.3B
Figure 5. Dual Chip Synchronization
7-33
MCS®-96 Diagnostics Library
occur using this method is 9 state times (2.25 JLS in a 12 Mhz system). However, the
skew should average between four and five state times. In any case, the parts will be far
from synchronized shortly after the tests begin. This is fine, as long as the tests begin
together.
In a one chip system, this process appears as a 600 microsecond pulse on PORT!.3.
(See Figure 6.) The tests begin 600 microseconds after the rising edge.
When synchronization is complete, the interrupt service routines are initialized, interrupts
are enabled, and control is returned to the background task. At this point, the testing
really begins.
Producers and Consumers
The Producer/Consumer exchanges on the 8097 are executed by the interrupt service
routines of the Dynamimc Stability Test. While some interrupt routines contain an
entire Producer or Consumer, some are spread through many routines. Figure 7 shows
on a broad level the transactions that occur during test execution. Short descriptions of
each Producer and Consumer follow, along with an indication of which interrupt routines
contain them.
Serial Producer eDSTSERe The Serial Producer constantly transmits a table of alphabetic and special characters, and test data which includes the current status of the test
and the REAL TIME since reset.
.
Serial Consumer eDSTSERe The Serial Consumer monitors the data coming over the
serial link to see if all the expected characters are transmitted correctly and in the correct
order. Transmission of the test data and the REAL TIME is checked by counting characters
between carriage returns.
Pilrtl Producer eDSTSWTe The Portl Producer outputs a series of values on Portl
that are contained in a table constructed to test all possible combinations of input and
output of ones and zeros. The test producer executes every 5000h TIMERI counts via
the expiration of Software Timer I.
Portl Consumer eDSTSWTe The Portl Consumer verifies the patterns appearing on
Portl using a table which contains the expected values. The check executes every 1000h
TIMERI counts via the expiration of Software Timer 2.
AID Producer eDSTSWTe The ND Producer continually starts ND conversions by
loading an HSO command to initiate an AID. The ND Producer executes every time
Software Timer 0 expires.
AID Consumer eDSTA2De The NO Consumer verifies the result of conversions initiated
by the ND Producer. It then changes the channel set for conversion and loads an HSO
command to cause a Software Timer 0 expiration.
SYNCHRONIZATION PULSE IN THE SINGLE CHIP MODE
:~~-------tr h~
Figure 6. Single Chip Sync Pulse
7-34
MCS®-96 Diagnostics Library
External Interrupt Producer oDSTHSOo The External Interrupt Producer causes rising
edges on HSO.l, which is tied to EXTINT. This Producer executes every time there has
been a falling edge on HSO.1.
External Interrupt Consumer oDSTEXIo The External Interrupt Consumer responds
to rising edges on EXTINT. It resets the WATCHDOG TIMER every execution and tests
the Test Status Words every 30h executions to see that all tests are running. This Consumer
also loads an HSO command to cause a falling edge on HSO.l
PWM Producer oDSTTOVo The PWM Producer executes every time there is a timer
overflow. In addition to changing the PWM period, it toggles an LED and checks for
unexpected T2CLK overflows. There is no PWM Consumer per se, but the PWM output
is tied to HSI.l which is configured to clock T2CLK. In this way T2CLK counts at a
known average rate, and is used by the test in a modulo count fashion to generate a real
• TRANSMITS
ALPHABET &
TEST DATA
• VERIFIES ORDER AND
ACCURACY OF TRANSMISSIONS
• PUTS TEST
VALUES ONTO
PORT 1
• VERIFIES STABILITY, ORDER
AND ACCURACY OF VALUES
ON PORT 1
• STARTS AID
CONVERSIONS
ON A RESISTOR
LADDER
• VERIFIES ACCURACY AND
ORDER OF CONVERSION
RESULTS. CHANGES THE
CHANNEL OF CONVERSION
• SCHEDULES
EXINT EVENTS
• RESETS THE WATCHDOG
TIMER, AND MONITORS
CORRECT EXECUTION OF
ALL OTHER TESTS
• CONTROLS THE
PULSE WIDTH
ONTHEPWM
PIN
• INCREMENTS T2CLK ON
EVERY EDGE
• CREATES A
STREAM OF
EVENTS ON
HSO.2AND
HSO.3
• VERIFIES THAT EVENTS
OCCUR AT RIGHT TIME
INTERVALS ON HSI.2
AND HSI.3
• SETS UPA
STORM OF
INTERRUPTS
(HSO, HSI, HSIO,
AID, SOFTWARE TIMER) THAT OCCUR
AT NEARLY THE SAME TIME
J HSO, HSI,HSIO, SWT}
\
INTERRUPTS
Figure 7. Producer/Consumer Overview
7-35
• VERIFIES THAT THE
REQUESTS WERE SERVED,
AND THAT THEY WERE
SERVED IN A TIMELY
MATTER
MCS@·96 Diagnostics Library
time clock. This module is also expandable to include tests that a user might want to
execute only periodically.
HSO Producer eDSTHSOe The High Speed Output Producer executes every time an
HSO event on HSO.2 or HSO.3 occurs. Varying pulse widths are created on the pins
using predetennined tables of values. The minimum pulse width is lOOOH; the maximum
is OCOOOH TIMERI counts.
HSI Consumer eDSTHSIe The high speed inputs are monitored by the High Speed
Input Consumer. The check executes every time an event occurs on HSI.2 or HSI.3. The
HSI Consumer verifies that the proper pulse widths appear on the pins, and that the series
of pulse widths is in the right order.
Interrupt BURST Producer eDSTSWT,DSTHIO,DSTHSO,DSTHSOe The previous
Producer/Consumer transactions either go between controllers in the dual-chip mode, or
stay within the same controller in the single-chip mode. However, there is one Dynamic
Stability Test that executes invisibly to a co-controller in the dual-chip mode. This test,
the Interrupt BURST Test, causes a flood of interrupts that almost fully load the 8097
with interrupt response requests.
I
The Interrupt BURST Producer causes a complex chain of events that eventually lead to
the updating of the REAL TIME Clock. Since the succession of events involves half of
the interrupt service routines, the whole process is described here for understanding.
The Big Picture - Each time the REAL TIME Clock is ready to be updated, a BURST
of interrupts is setup to occur as close together as possible. Figure 8 shows the sequence
of events that occur, their dependency on T2CLK and the commands written into the
HSO CAM. If you don't need any more detail, skip "The nitty-gritty".
The nitty-gritty - Every time an the AID Consumer finishes executing it sets up a
Software Timer 0 expiration for TIMERl = TIMERl + 2. While T2CLK is between
lOOh and 600h, the AID Producer (Software Timer 0) causes a new conversion with an
HSO command. If T2CLK is greater than 600h, then an HSO command is loaded to
cause a falling edge on HSO.O instead of causing an AID conversion to start. This begins
the BURST sequence.
The falling edge on HSO.O causes an HSO interrupt and an HSI interrupt, since HSO.O
is tied to HSI.O. The HSO interrupt loads commands to raise HSO.O at T2CLK= 1900h
and start an AID at T2CLK= 18ffh. The HSI interrupt loads no HSO commands.
When T2CLK= l8ffh an AID conversion is begun. When T2CLK= 1900h a rising edge
occurs on HSO.O causing T2CLK to be reset and HSO,HST and HSLO interrupt requests
to be made. At approximately the same time an AID conversion completes and the AID
Done interrupt request is made.
The HSO interrupt service causes no further events. The HSI interrupt service routing
loads an HSO command to cause a Software Timer 3 interrupt at T2CLK = Offh. The
AID Consumer loads an HSO command to cause a Software Timer 0 interrupt at
TIMERl = TIMER 1 + 2. When the AID Producer executes it loads a command to start
an AID conversion at T2CLK= lOOh. And the HSI.O interrupt service routine updates
the REAL TIME Clock (the real output from this whole mess).
The last interrupt that is serviced from this BURST is a Software Timer 3 expiration.
This is the BURST Checker. It verifies that all interrupts occurred within a reasonable
time ',Vindow, but causes no further events if all tests passed.
.
All these activities keep the HSO CAM almost fully loaded. So, to ensure that CAM
overwrites never occur, two precautions were taken. First, one CAM slot was allocated' .
to four of the tests that use the HSO unit, and two slots were allocated for shared use
by the Interrupt BURST process and the AID conversion process.
7-36
MCS®-96 Diagnostics Library
The second precaution was to confirm that either the CAM was not full or the HOLDING
REGISTER was empty (depending upon the test) before allowing any write to the CAM.
Figure 9 shows the HSO CAM loading over time, with T2CLK as the time base. External Interrupt, Portl, HSO.2 and HSO.3 events each are allocated the use of one CAM
slot all the time. While T2CLK is below 600h, but above IOOh, another CAM slot is
used by the AjD Done - Start AjD sequence. When T2CLK goes above 600h, two
slots are used by the Interrupt BURST process. The BURST events conclude when
T2CLK is reset and climbs to IOOh. At lOOh, the AjD Done - Start AjD sequence
being again.
SWTO
EXPIRE
{
IF T2CLK <600h
THEN
START AID }
CONVERSION
T1 = Tl + 200h
{
ELSE
INTERRUPT BURST
SEQUENCING
HSO.O
~
T2=T2+1
HSO
(HSO.O EVENl)
{
HSI.O
(HSI.O EVENl)
HSO.O
....r
HSI
(HSI.O EVENl)
HSO
(HSO.O EVENl)
T2 = 1900 H
{
START AID }
CONVERSION
T2 = 18H H
HSI
(HSI.O EVENl)
INITIALIZE
Figure 8. Interrupt BURST Sequencing
7-37
MCS®-96 Diagnostics Library
HSOCAM
EXTERNAL INTERRUPT EVENTS
PORT' PRODUCER EVENTS
..
PORT' CONSUMER EVENTS
...
..
HSO.2 EVENTS
I
SOFlWARE
~~!::ND
HSO.3 EVENTS
...
START AID
COMMAND
HSO.O ' " ' COMMAND
JI
START AID
COMMAND
WHILE
,00H '" T2CLK
< 600H
SOFlWARE TIMER 3
COMMAND
HSO.O
COMMAND
I
~=ARe
COMMAND
J
1
START AID
COMMAND
WHILE
T2CLK < 'OOH
OR
T2CLK" 600H
Figure 9. HSO CAM Loading
4.1 How to Use DST96
All program modules that are needed to run the Dynamic Stability Test are contained
in the DST96 Library (DST96.LIB). This Library is also a part of DIAG96.LIB. To use
the test, one or two 8097s must be configured as preyiously shown. A background task
for the Dynamic Stability interrupt service routines must also be provided and linked to
DIAG96.LIB. For those who don't wish to write a background task, one is provided
(DSTUSR). But, any code may be written which follows some simple rules.
The Software
The software constraints are relatively minor, but they do create incompatibility with
PLM96. All background tasks should be written in ASM96.
Minimally, the background task must load the, STACK POINTER, PUSH parameters,
CALL DSTISR, and go into a loop. Any other code may come after the CALL to DSTISR,
as long as:
., Interrupts are never disabled for more than a few instructions;
• No operations to or from special function registers occur (with the exception of reading
TIMER! or T2CLK), and
Other less grave limitations on the main task are that it:
• Be CSEGed at 2080h;
7-38
MCS®-96 Diagnostics Library
• Write only to EREG I, EREG2, OSEG registers from 40h to 5Cn, or external RAM,
(the OSEG is an RL96 technicality, once DSTISR returns control to the MAIN TASK,
locations 40h to 5Ch are not touched by the Tests); other registers can be read, but
not written to;
• Communicate to the outside world through Port3 and Port4, (these Ports are untouched
by the tests), or memory mapped I/O registers;
To provide the Dynamic Stability Test modules for linkage to your program, modify
the batch file DSTRL.BAT to suit your system with respect to memory mapping and
invoke the batch file with the appropriate background task filename. For example,
type:
DSTRL DSTUSR
The Hardware
The Dynamic Stability Test has been designed to allow flexibility in the way output
from the tests is used.
Minimally, no output device (printer, terminal) or function generators need to be attached
to the test. If the LED attached to Port 2.7 is not flashing, the test failed. However, no
other information may be gained.
To support a greater level of debugging (of the test code initially), the test was designed
to output status and error information to one 4800 and one 300 baud device. The baud
rates are derived from the function generators if present. Figure \0 shows how both
devices can be attached to the test.
With this configuration, the test outputs an initialization message to both devices, then
selects just the 4800 baud line for monitoring the Serial Port Producer/Consumer transactions. If an error is detected, the 300 baud line is selected for an error information
dump.
A diagram of the circuit used in developing the Dynamic StabiIty Test appears in Figure
11. It is sufficiently general purpose for use in either the single or double chip modes,
with or without printers or terminals attacht;d.
The circuit requires that the 8097 I/O signals be present on an SBE-96 compatible 50
pin connector. The circuit also assumes that the analog voltage reference is provided
through the cable. Therefore, if you are using the SBE-96, the jumpers to do this need
to be in place (jumper numbers vary with the SBE-96 version).
Figure 12 describes how to jumber the Dynamic Stability Test board for one or two
chip tests. Figure l3 shows the SBE-96 50 pin connector pinout. The following sections
describe in detail the actions of each interrupt service routine in implementing the
Producer/Consumer transactions.
P2.6
DEVICE SELECT
---4~--i
1141488
:)0----1
~----_~ TO 4800 BAUD DEVICE
DATA OUT
nD-----ir----~~-~
.......---- TO 300 BAUD DEVICE
L----......jL~:>-_,
1141489
DATA IN
RXD
-------.
0
~
8 ..
i'"
~~
:0
...
S
~
o-l
[!l.
..
rn
::;-
...
h
;0: . .
~I
:0'-
10
.".
10
,.,
~
Q
::I
:n
IJQ
.
=
10
a.
C
::I
J5
20
40
BO
Bo
100
120
140
1BO
1BO
200
220
240
260
280
300
320
340
"0
.. 0
400
.20
..0
480
.. 0
50 0
01
o,
os
07
01
011
01.
01.
017
01.
021
023
025
027
029
0',
033
O.S
037
0 ••
0.,
0 ..
045
047
0 ••
J2
J2
J1
J2
28-0
34-0
34
0- 28
PORT 1
0-
HSIO.o
16-0
35-0
0-35
0-16
EX11NT
31-0
42-0
0-42
0-31
H$IO.2
32-0
43 --0
0- 32
+l2YDC
FUNCTION
-
0-43
. ..
41
AID
CHANNELS
38--0
23-0
0-23
0-38
39-0
24-0
0-24
0-39
26--0
25--0
0-25
0-26
--
PWI'
POI\T2.8
T2ClK
45
48
1'-
: ~~:::
1~1
E5
10K
FUNCTION
GENERATOR
10K
+12VDC
10K
48
.5
~~~~~
:::::,
29--0
0-29
GENERATOR
KSIO.3 ::::::::
J1
:::: ~:,
-12VDC
PORT2.1
T2R$T
10K
15-0
18-0
21-0
0-15
0-1.
0-21
......
;:;
27 --0
0-21
30 --0
0-30
33 - 0
0-33
31-0
41 --0
44 - 0
47 --0
0-38
0-41
0-44
0--47
DIGITAL
50 --0
0-50
GROUNDS
,.;;.
......
...,.40
.11'1
10K
J2-2O
1--0
4-0
+12VDC
ANALOG
GROUNDS
0-1
0-4
7-0 0-7
10-0
13--0
0-10
~13
01
O.
O.
07
01
011
01'
015
017
01.
021
023
025
027
029
0.,
033
035
20
40
BO
Bo
100
120
140
160
1BO
200
220
2'0
260
2.0
300
320
340
"0
037
300
0 ..
0.,
0 ..
0 ..
047
0 ..
400
420
..0
480
,,0
20
8 ..
I~
!lrn
0:0
:0
J3
rn
@
,
\C
~
t:::I
5·
::I
C
a.
'",.,
~a
;0:"
~~
:0'-
20
J.
soo
Note: Connect Jl of this board to J3 of an 58E-96. For dual
chip operation, also connect J3 of a second SBE-96
to J2 on this bOard. Use the ju~r list In FlQure 4-11
for the mode used. The functJon generators are
two, or none may be used.
optional One,
("l
IJQ
J1
I
::
'"
..t:
.".
10
'<
MCS®-96 Diagnostics Library
Jumper Connections for Single Chip Mode
J1
;22-37
23-38
24-39
25 - 26
45 - 48
34 -28
35 -16
42-31
Also
43 - 32
E1 - E2
46 - 29
E3 - E4
1-4-7-10-13
15 -18 -21-27-30 -33 -36 - 41-44 -47- 50
Jumper Connections for Dual Chip Mode
J1-J2
22-37
23-38
24-39
25-26
42-31
43-32
15 -15
18 -18
21 -21
27-27
30-30
J1-J2
33-33
36-36
41 - 41
44-44
47-47
50-50
1 -1
9-9
2-2
8-8
6-6
11 -11
3-3
12-12
J1-J2
14 -14
4-4
5-5
7-7
10 -10
13 -13
J1
34-28
45-48
46-29
35-16
J2
34-28
45 -48
46-29
35 -16
J2-J1
22-37
23-38
24-39
25-26
42-31
43-32
Also
E2-E5
E1-E4
Figure 12. Dynamic Stability Board Jumper List
ANALOG GROUND
ANALOG CHANNEL 1
ANALOG CHANNEL 0
ANALOG GROUND
ANALOG CHANNEL 7
ANALOG CHANNEL 5
ANALOG GROUND
DIGITAL GROUND
RESET
RXD
DIGITAL GROUND
PORT 1.1
PORT 1.3
DIGITAL GROUND
HSl.l
HSO.4/HSI.2
DIGITAL GROUND
HSO.l
PORT 1.5
PORT 1.7
DIGITAL GROUND
HSO.3
PORT 2.7
DIGITAL GROUND
T2CLK
20
40
&0
So
100
120
140
160
lSo
200
220
240
2&0
2So
300
320
340
360
3So
400
420
440
460
480
500
01
03
05
07
09
011
013
015
017
019
021
023
025
027
029
031
033
035
037
039
041
043
045
047
049
ANALOG CHANNEL 3
ANALOG GROUND
ANALOG CHANNEL 2
ANALOG CHANNEL 6
ANALOG GROUND
ANALOG CHANNEL 4
ANALOG VREF
EXTERNAL INTERRUPT
DIGITAL GROUND
TXD
PORT 1.0
PORT 1.2
PORT 1.4
HSI.O
DIGITAL GROUND
HSO.5/HSI.3
HSO.O
DIGITAL GROUND
PORT 1.6
PORT 2.6
HSO.2
DIGITAL GROUND
PWMlPORT 2.5
T2RST
DIGITAL GROUND
J3
Figure 13. SBE-96 J3 Pinout
7-41
MCS®-96 Diagnostics Library
4.2 Test Module Descriptions
DST Initialization (DSTISR)
Brief Description:
This module is the invocation and initialization code for the Dynamic Stability Test.
Assembly Language Calling Sequence:
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
CALL
,
DSTISR
When All Tests Pass:
EREG 1 : = 0040h
EREG2 : = OOOOh
When a Test Fails:
EREGI
EREGI
EREGI
EREGI
...-
Ol40h
0240h
0340h
0440h
on abnormal RESET
if T2CLK won't change
if T2RST did not work
if lOCO. I did not work
EREG2
EREG2
EREG2
'EREG2
:= TIMER I
: = xxxxh
: = xxxxh
: = xxxxh
Detailed Description:
This module initializes the registers used by Dynamic Stability Test Modules, checks
to see if there is an external clock present, tests TICLK counting and reset functionality,
and outputs initialization messages to the two output devices. The selected tests module
(D96FST) from the General Diagnostics is also executed using the parameters specified.
When all initialization tests are passed, then a synchronization is performed to place the
two processors in a dual-chip mode test in close sync. The PORT! pins are used as to
perform the handshaking synchronization. After synchronization, all Dynamic Stability
Tests are activated and control is returned to the user program.
7-42
MCS®-96 Diagnostics Library
External Interrupts (DSTEXI)
Brief Description:
This module executes every time there is a rising edge on the EXTINT pin. The test
resets the WATCHDOG TIMER and verifies execution of all Dynamic Stability routines.
If Test Fails:
EREGI
EREG2
. = OlAOh if a test did not execute
Number of Shifts done
Detailed Description:
This routine executes every time there is a rising edge on the EXTINT pin, causing an
external interrupt. Each execution, the WATCHDOG TIMER is reset and an HSO command to clear the HSO.! pin in lOOOh TIMER! counts is loaded into the CAM. The
HSO routine that responds to that event will cause HSO.! to go high, thus causing another
vector to DSTEXI.
Every 30h executions of this module, the Test Status Words are NOTed and then
NORMaLized to see if any test did not execute. If any bit in the Test Status Words is
left set after being complemented, the NORML instruction will leave the most significant
bit set, indicating an error. If there was no error, the TSWORDs are cleared. The user
can change a mask in DSTEXI to enable checking of any of the currently spare bits in
TSWORD. The TSWORD bit map is as follows:
TSWORD2
EREG2
81T#
TSWORD1
EREG2
81T#
I
I
lDh
llh
12h
13h
14h
15h
16h
17h
lBh
19h
lAh
lBh
lCh
lDh
lEh
lFh
DFh
DEh
ODh
OCh
OBh
OAh
9
B
7
6
5
4
3
2
1
0
HJI.3
HJI.2
HJO.3
HS~.2 HS~.l HS~.O
I
HSI.O
SW
TIMERS
SOFTWARE TIMER 3IINTERRUPT BURST CONSUMER
SOFTWARE TIMER 21PORTl CONSUMER
I J
SOFTWARE TIMER l/PORTl PRODUCER
SOFTWARE TIMER DlAiD PRODUCER/BURST PRODUCER
AID CONSUMER
SERIAL PORT CONSUMER
SERIAL PORT PRODUCER
REAL TIME CLOCK
Figure 14. Test Status Word Bit Map
7-43
.
-
MCS®-96 Diagnostics Library
Serial Port (DSTSER)
Brief Description:
This module contains the Serial Port Consumer and Producer routines for the Dynamic
Stability Tests. It is executed on every Serial Interrupt.
If Test Fails:
EREGI .EREG2
EREGI .EREG2 .-
OlBOh if a bad character was received
actual received character
02BOh if an incorrect number of characters
came between carriage returns
actual count
Detailed Description:
This interrupt service routine executes every time there is a Serial Interrupt. The data
that is transmitted and checked by the test consists of first, the alphabet and some special
characters; second, the current REAL TIME; and finally, the bit representation of the
Test Status Words. The receiver verifies the alphabet and funny characters and counts
characters until a carriage return. The following is an example of what the output looks
like.
ABCDEFGHIJKLMNOPQRSTUVWXYZ*#%&[)@001 :23:59.61 111111011101111110001111
The code first checks for a Receive Done flag. If a receive just completed, the receive
buffer is emptied and checked for validity. If the received character is a carriage return,
then the count since the last c,arriage return is checked for correctness.
After the receive service has finished, or if there was no receive, DSTSER then checks
for the Transmit Done flag. If more transmits can be made, the'next data byte is loaded
into the transmit buffer. If the data is exhausted, a carriage return is sent, and the routine
is set to transmit the first data byte again.
7-44
MCS@-96 Diagnostics Library
Software Timers (DSTSWT)
Brief Description:
This module is executed every time a Software Timer Interrupt expires. The routine
includes the Portl Producer and Consumer, the AID producer, and the Interrupt Burst
control and verification code.
If a Test Fails:
EREGI
EREG2
EREGI
EREG2
EREGI
EREG2
EREGI
EREG2
EREGI
EREG2
EREGI
EREG2
EREGI
EREG2
.-
..-
OIDOh If an unexpected value is found on Port I
expected value in high byte, actual value in low byte
02DOh AID Done interrupt did not occur within BURST window
Time between AID done and Software Timer 0
03DOH REAL TIME update did not occur within BURST window
Time between REAL TIME update and Software Timer 0
04DOH HSO.O response did not occur within BURST window
Time between HSO.O interrupt and Software Timer 0
05DOH HSI(.O) response did not occur within BURST window
Time between HSI(.O) service and Software Timer 0
OlDlH Invalid T2CLK value reached
T2CLK found
02DIH Test reached an illegal Software Timer 0 state
the illegal case jump that was made
Detailed Description:
This module is called every time a Software Timer expires and causes and interrupt.
Software timers are used by the AID Done - AID Trigger Sequence, the Interrupt Burst
Sequence, and the Portl Producer and Portl Consumer.
When Software Timer 0 expires, a case jump is done on the BURST_STATE variable
to sequence the AID and interrupt BURST process to the appropriate state. Depending
upon the value of T2CLK and the state of the AID converter, either an AID conversion
is initiated or HSO.O is set to go low to begin the interrupt BURST events.
When Software Timer! expires, a new value is written to Portl from a table constructed
to test all combinations of input/output states on the quasi-bidirectional port pins. The
HSO CAM is also loaded with a command to cause Software Timerl to overflow again
in 5000h TIMER I counts.
When Software Timer 2 expires, Portl is read and compared to a table of expected entries.
If the value is correct, then an HSO command is loaded into the CAM to cause another
Software Timer 2 expiration in 1000h TIMERI counts. If the value is not correct, the
next entry in the Table is checked. If there is still no match, an error is reported. If there
is a match, the CAM loading occurs and Software Timer 3 is checked for expiration.
If Software Timer 3 has expired, then the flurry of BURST interrupts should have just
occurred. The routine checks to see that each event happened within a reasonable time
window. If the checks pass, then the routine exists with no further action.
7 . . A5
MCS@-96 Diagnostics Library
Real Time Clock (HSIO) (DSTHIO)
Brief Description:
This routine executes every time there is a rising edge on HSI.O and updates the real
time clock value.
When Module Executes:
REAL_TIME : = REAL_TIME
+ .204 seconds
Detailed Description:
This module is the HSI.O interrupt service routine. On each rising edge of HSI.O, the
value in the REAL TIME clock buffer is updated to reflect the passing of 1900h T2CLK
counts. Since the PWM output is tied to T2CLK, and the average time between edges
is 31.875 f.LS in a 12 MHz system, then 1900h T2CLK counts represents .204 seconds.
Execution of this module occurs during the interrupt BURST events. No action other
than updating the REAL TIME clock is taken in this routine.
High Speed Outputs (DSTHSO)
Brief Description:
This module manages the pulse width outputs on HSO.2 and HSO.3, and causes the
Manager test to execute.
Detailed Description:
Every time an HSO command is executed that has the Interrupt bit set, this program
executes. The routine manages the pulse widths on HSO lines two and three, and causes
the Manager module to execute at the right time.
When a falling edge has been caused on either HSO.2 or HSO.3, DSTHSO loads a
command into the CAM to cause" a rising edge on the same line at a time that gives the
line a low pulse width equal to a predetermined table value. Rising edges cause analogous
responses. The tables used cause low and high pulse widths that vary from 1000h and
OCOOOh. The length of the tables differ by one so that all combinations of low and high
table times occur.
When a falling edge was caused on HSO.I, the routine loads a command into the CAM
to cause a rising edge on the same line two TIMERI counts later. Since HSO.I is tied
to the EXTINT pin, rising edges cause the Manager Routine to execute.
7-46
MCS®-96 Diagnostics Library
High Speed Inputs (DSTHSI)
Brief Description:
This module does the verification of events on the HSI lines and initiates some interrupt
BURST events when appropriate.
If a Test Fails:
EREGI
EREG2
EREGI
EREG2
.-
016lh if a high pulse on HSl.2 had an unexpected width
difference between actual and expected pulse width
0261h if a low pulse on HSl.2 had an unexpected width
difference between actual and expected pulse width
0361h if a high pulse on HS1.3 had an unexpected width
EREGI
EREG2 .- difference between actual and expected pulse width
EREGI
EREG2
0461h if a low pulse on HSI.3 had an unexpected width
difference between actual and expected pulse width
0561h if the HSI unit indicated that an HSl.l event occurred
EREGI
EREG2 .- the time recorded in the FIFO
Detailed Description:
This module executes every time an event is loaded into the HSI Holding Register.
Verification of pulse widths on HSl.2 and HSl.3 is done from tables of expected values.
Any deviation is reported as an error.
If the test detects a negative transition on HSI.O, then commands are loaded into the
HSO CAM to start an ND at T2CLK = 18ffh and to set HSO.O high at T2CLK =
1900h. This results in an HSO, HSI, HSI.O and ND Done interrupt requests to occur at
approximately the same time - approaching a full demand on interrupt service.
When a rising edge on HSI.O is detected, an HSO command is loaded into the CAM to
cause a Software Timer 3 interrupt when T2CLK = lOOh. The Software Timer 3 interrupt
service will check to see that all burst events happened fast enough.
HSl.l events are disabled from the FIFO. Any event detected on this line is reported as
an error.
7-47
MCS®-96 Diagnostics Library
AID Conversion Complete (DSTA2D)
Brief Description:
This module executes every time an AID conv.:rsion is complete. The conversion result
is checked for correctness, the AID converter is setup to convert on the next channel
when initiated by an HSO command, and an HSO command to cause a Software Timer
o expiration is loaded.
If Test Fails:
EREGI . - OlCOh on a conversion error
EREG2
channel on which error occurred
Detailed Description:
This module executes every time an AID conversion is complete. The conversion result
is checked against a test table for correctness, and the AID converter is setup to convert
on the next channel when initiated by an HSO command. An HSO command to cause a
Software Timer O. expiration in 0002h TIMER I counts is loaded just prior to exiting the
module.
While T2CLK has a value between JOOh and 600h, AID conversions are initiated by the
Software Timer 0 Interrupt service routine. When T2CLK goes above 600h, an AID
conversion is initiated by the HSO.O interrupt service routine.
Given the possibility of additive error in 5% resistors, the conversion is tested to only
six bits of accuracy.
Timer Overflows (DSTTOV)
Brief Description:
This module toggles a port pin tied to an LED, manages the PWM output, performs some
simple tests, and is expandable to allow inclusion of user written tests.
If Test Fails:
EREGI . - 0190h if T2CLK had an overflow indication
T2CLK a the time the error was found
EREG2
Detailed Description:
This module executes every time TIMER I or T2CLK overflow. Only TIMER I overflows
are valid however, so T2CLK overflows are flagged as an error.· Each overflow, a new
period is loaded into the PWMCONTROL register from a table of pulse periods. If an
LED is connected, it will appear to slowly change in intensity. Port2.7 is also toggled
in this routine to light another LED.
This interrupt routine can be expanded with special tests that are to execute on a periodic
basis. Any of the spare bits in the Test Status Words can also be used by specialized
tests. They will be checked by the External Interrupt service routine with a simple change
in a bit mask.
7-48
MCS®-96 Diagnostics Library
Macro Module (DSTMAC)
Brief Description:
This module contains four macros used by the Dynamic Stability Test.
Assembly Language Invocation:
SPSTATUS
Temp_Register
or
SPWAIT
(RI,TI)
or
SR_ON_ERROR
Label
or
RESET_WATCHDOG
Detailed Description:
The SPSTATUS Macro is used to ORB the Serial Port Status Register to a temp register.
The Macro needs to be used to work around a bug in the 809x-90.
The SPWAIT Macro is used to cause program execution to halt and wait for an RI or
TI flag, depending upon which is specified.
The BR_ON_ERROR Macro tests the high byte of EREGl and jumps to the label if
the byte is not zero. This can be used every time a General Diagnostic completes since
the detection of any error will cause the high byte of EREG I to be non-zero.
The RESET_WATCHDOG Macro does just what it says. The WATCHDOG TIMER
is reset by writing the correct sequence to location OAh.
To access a DSTMAC macro, this module must be $INCLUDEd.
7-49
MCS®-96 Diagnostics Library
Error Procedure (DSTERR)
Brief Description:
This module is called if any error is detected in the Dynamic Stability Test. Information
about the error is output over the serial port, and the test is restarted.
Assembly Language Calling Sequence:
CALL
Error_Proc
Detailed Description:
This module is CALLed on detection of any error in the Dynamic Stability Test. When
CALLed, the procedure:
•
•
•
•
•
•
disables interrupts,
saves any rapidly changing values (TIMERI,T2CLK,HSO_STATUS, ... ),
waits for a serial transmit in progress to complete,
waits for the current serial receive to complete,
empties eight entries from the HSI_FIFO,
transmits an open loop sync sequence in case a co-controller is stuck in the sync
routine, and
• waits a few hundred milliseconds to ensure that a co-controller has also detected a
failure.
After these steps have been taken, the DSTERR de-selects the 4800 baud line, selects
the 300 baud line, and outputs error messages. These messages include the Error Code
(EREGI), the Detail Code (EREG2), the address of the line in the test which found the
error, and the REAL TIME since reset.
Following the error messages, the procedure dumps' the data contained in the registers
and the external error buffer out over the serial port to the 300 baud device.
Finally, a RST instruction followed by a branch to the RST instruction is executed. If
the WATCHDOG TIMER is externally disabled, the test will stay in this loop. If the
WATCHDOG TIMER is not disabled, the test chip will reset, and the Dynamic Stability
Test will reinitialize.
DST Example User Code (DSTUSR)
Brief Description:
This is an example program that initiates the Dynamic Stability Test and then executes
some General Diagnostics as a background task.
Detailed Description:
DSTUSR sends parameters defined at assembly time to the DST initialization routine
(DSTISR). When control returns to DSTUSR, the example repeatedly executes ALUO 1,
ALU02, ALU04, ALU05 and MEMOA. It takes two minutes (with the given memory
parameters) for the DSTUSR background task to cycle once while interrupts are running.
When creating a custom background task, using this example program as a template will
speed development.
7-50
APPENDICES
APPENDIX A • DIAG96.LlB Error Messages by EREG1 Code
APPENDIX B • DIAG96.LlB Error Messages by Module Name
APPENDIX C • Description of DIAG96.LlB Batch Files
APPENDIX D • Example Program Listings
D96A96
D96P96
-
7-51
D96FST
DSTUSR
APPENDIX A
DIAG96.LIB Error Messages by EREG1 Code
0000
No Message
EREG2 = Offffh
MODULE = SYS01 /Common Symbols
0002
All Tests Passed
EREG2 = 0000
MODULE = SYS02lSystem Power-up
0003
All Tests Passed
EREG2=0000
MODULE = SYS03/Program Counter
0011
All Tests Passed
EREG2=0000
MODULE = ALU01 /Add/Subtract
0012
All Tests Passed
EREG2=0000
MODULE = ALU02lMULUB
0013
All Tests Passed
EREG2=0000
MODULE = ALU03/Multiply/Divide Table
0014
All Tests Passed
EREG2=0000
MODULE = ALU04/Multiply/Divide Random
0015
All Tests Passed
EREG2 = 0000
MODULE = ALU05/Multiply/Divide Core
0021
All Tests Passed
EREG2=0000
MODULE = MEM01/Complementary Address (Registers)
0022
All Tests Passed
EREG2=0000
MODULE = MEM02lWaiking Ones/Zeros (Registers)
0023
All Tests Passed
EREG2 = 0000
MODULE = MEM03/Galloping Ones/Zeros (Registers)
0024
No bits were set i!l the byte tested
EREG2=0000
MODULE = MEM04/Bits Set
0025
All Tests Passed
EREG2=0000
MODULE =MEM05/Checkerboard Pattern (Registers)
0026
All Tests Passed
EREG2=0000
MODULE = MEM06/Complementary Address
7-52
MCS@-96 Diagnostics Library
0027
All Tests Passed
EREG2=0000
MODULE = MEM07IWaiking Ones
0028
All Tests Passed
EREG2=0000
MODULE = MEM08/Galloping Ones
0029
All Tests Passed
EREG2=0000
MODULE = MEM09IWaiking Ones/Zeros
002A
All Tests Passed
EREG2=0000
MODULE = MEMOAIGalioping Ones/Zeros
002C
All Tests Passed
EREG2 = 0000
MODULE = MEMOC/User Pattern (Registers)
002D
All Tests Passed
EREG2=0000
MODULE = MEMOD/User Pattern
0030
All Tests Passed, checksum is ready
EREG2 = 16-bit checksum
MODULE = D96A96/ALL Tests in ASM96
0040
Initialization completed satisfactorily
EREG2 = 0000
MODULE = DSTISR/DST Initialization
OOEO
All Tests Passed, checksum is over range specified
EREG = 16-bit checksum
MODULE = D96FST/Selected Tests in ASM
OOFO
All Tests Passed, checksum is ready
EREG2 = 16-bit checksum
MODULE = D96P96/ALL Tests in PLM96
0102
I/O Status Registers were unexpected
EREG2 = 10SO in low byte, IOS1 in high byte
MODULE = SYS02/System Power-up
0103
Test Code Returned Early
EREG2 = Early Time
MODULE = SYS03/Program Counter
0111
An Addition error occurred
EREG2=offending argument when the error occurred
MODULE=ALU01/Add/Subtract
0112
Incorrect multiplication result was detected
EREG2 = Multiplier/Multiplicand
MODULE = ALU02lMULUB
0115
A signed operation failed
EREG2=offending argument on error
MODULE = ALU03/Multiply/Divide Table
7-53
MCS®-96 Diagnostics Library
0115
A signed operation failed
EREG2 = offending argument on error
MODULE = ALU04/Multiply/Divide Random
0115
A signed operation failed
EREG2 = offending argument on error
MODULE = ALU05/Multiply/Divide Core
0121
A memory location failed
EREG2 = address of the error
MODULE=MEM01/Complementary Address (Registers)
0122
A memory location failed
EREG2 = address of the error
MODULE = MEM02lWaiking Ones/Zeros (Registers)
0123
A memory location failed
EREG2 = address of the error
MODULE = MEM03/Galloping Ones/Zeros (Registers)
0124
At least one bit was set in the byte tested
EREG2 = number of bits set
MODULE = MEM04/Bits Set
0125
A memory location failed
EREG2"" address of the error
MODULE = MEM05/Checkerboard Pattern (Registers)
0126
A memory location failed
EREG2 = address of error
MODULE = MEM06/Complementary' Address
0127
A memory location failed
EREG2 = address of the error
MODULE = MEM07/Walking Ones
0128
A memory location failed
EREG2 = address of the error
MODULE = MEM08/Galloping Ones
0129.
A memory location failed
EREG2 = address of the error
MODULE = MEM09/Walking Ones/Zero
012A
A memory location failed
EREG2 = address of the error
MODULE = MEMOA/Galloping Ones/Zeros
012B
16-bit Checksum is ready
EREG2 = 16-bit Checksum
MODULE = MEMOB/Checksum
012C
A memory location failed
EREG2 = address of the error
MODULE = MEMOC/User Pattern (Registers)
0120
A memory location failed
EREG2 = address of the error
MODULE = MEMOD/User Pattern
7-54
MCS®-96 Diagnostics Library
0140
An abnormal RESET occurred
EREG2 = TIMER1
MODULE = DSTISR/DST Initialization
0161
A high pulse on HSI.2 had an unexpected width
EREG2=difference between actual and expected pulse width
MODULE = DSTHSI/High Speed Inputs
0190
An overflow of T2CLK was indicated
EREG2=TIMER1
MODULE = DSTTOVlTimer Overflows
01 AO
One or more DST Module did not execute on time
EREG2=Number of SHIFTs done
MODULE = DSTEXI/External Interrupt (Supervisor)
01 BO
An unexpected serial character was received
EREG2 = Bad character received
MODULE = DSTSERISerial Port
01CO
An unexpected AID conversion result was found
EREG2 = Channel number of unexpected result
MODULE = DSTA2D/AID Conversion Complete
01 DO
Found unexpected value on PORT1
EREG2 = expected value in high byte, actual in low byte
MODULE = DSTSWT/Sof!ware Timers
01 D1
Invalid T2CLK value reached
EREG2=T2CLK
MODULE = DSTSWT/Sof!ware Timers
0202
TIMER1 did not change over time
EREG2=TIMER1
MODULE = SYS02/System Power-up
0203
Test Code Returned Late
EREG2=Late Time
MODULE = SYS03/Program Counter
0211
A Subtraction error occurred
EREG2=offending argument when the error occurred
MODULE = ALU01 IAdd/Subtract
0215
An unsigned operation failed
EREG2=offending argument on error
MODULE = ALU03/Muitiply/Divide Table
0215
An unsigned operation failed
EREG2=offending argument on error
MODULE = ALU04/~ultiply/Divide Random
0215
An unsigned operation failed
EREG2=offending argument on error
MODULE = ALU05/Muitiply/Divide Core
0240
T2CLK will not change
EREG2=xxxx
MODULE = DSTISR/DST Initialization
7-55
MCS®-96 Diagnostics Library
0261
A low pulse on HSI.2 had an unexpected width
EREG2 = difference between actual and expected pulse width
MODULE = DSTHSl/High Speed Inputs
02BO
A carriage return was received out of sequence
EREG2 = number of characters since a carriage return
MODULE = DSTSERISerial Port
02DO
AID Done did not occur within BURST window
EREG2 = Time between AID done and Software Timer 0
MODULE = DSTSWT/Software Timers
02D1
Test reached an illegal Software Timer 0 state
EREG2 = Illegal case jump made
MODULE = DSTSWT/Software rimers
0302
Zero Register was found to change
EREG2 = Program Status Word At Failure
MODULE = SYS02/System Power-up
0303
Counter Register contained unexpected value
EREG2 = Erroneous Counter Value
MODULE = SYS03/Program Counter
0311
A flag error occurred
EREG2 = offending argument when the error occurred
MODULE = ALU01/Add/Subtract
0315
A flag error occurred
EREG2=offending argument on error
MODULE = ALU03/Muitiply/Divide Table
{)315
A flag error occurred
EREG2 = offending argument on error
MODULE = ALU04/Muitiply/Divide Random
0315
A flag error occurred
EREG2 = offending argument on error
MODULE = ALU05/Muitiply/Divide Core
0340
T2RST pin would not RESET T2CLK .
EREG2=xxxx
MODULE = DSTISR/DST Initialization
0361
A high pulse on HSI.3 had an unexpected width
EREG2 = difference between actual and expected pulse width
MODULE = DSTHSl/High Speed Inputs
0391
Illegal Opcode
03DO
REAL TIME update did not occur within BURST window
EREG2 = Time between REAL TIME update and Software Timer 0
MODULE = DSTSWT/Software Timers
0402
PUSHF or POPF failed
EREG2 = Erroneous PUSHed or POPed value found
MODULE = SYS02lSystem Power-up
7-56
MCS®-96 Diagnostics Library
0440
IOCO.1 would not RESET T2CLK
EREG2=xxxx
MODULE = DSTISR/DST Initialization
0461
A low pulse on HSI.3 had an unexpected width
EREG2 = difference between actual and expected pulse width
MODULE = DSTHSIlHigh Speed Inputs
0400
HSO.O response did not occur within BURST window
EREG2 = Time between HSO.O update and Software Timer 0
MODULE = DSTSWT/Software Timers
0502
Sticky Bit would not set
EREG2=3fffh
MODULE = SYS02/System Power-up
0502
Sticky Bit would not clear
EREG2=0000
MODULE = SYS02/System Power-up
0561
HSI unit indicated an HSI.1 event occurred
EREG2=Time recorded in HSI FIFO
MODULE = DSTHSl/High Speed Inputs
0500
HSI(.O) response did not occur within BURST window
EREG2=Time between HSI(.O) service and Software Timer 0
MODULE = DSTSWT/Software Timers
0602
Carry Flag Test Failed
EREG2=xxxx
MODULE = SYS02/System Power-up
0702
Overflow flags would not set correctly
EREG2=0002h
MODULE = SYS02/System Power-up
0702
Overflow flags would not clear correctly
EREG2=xxxx
MODULE = SYS02/System Power-up
0802
Interrupt Pending Register failed read/write test
EREG2 = offending Interrupt Pending by1e
MODULE = SYS02lSystem Power-up
xx91
(user defined}
EREG2 = (user defined}
MODULE = DSTTOVlTimer Overflows
7-57
·. APPENDix B
DIAG96.LIB Error Messages by Module Name
ALUOl
Add/Subtract
0011 All Tests Passed
EREG2 = 0000
0111 An Addition error occurred
EREG2 = offending argument when the error occurred
0211 A Subtraction error occurred
EREG2 = offending argument when the error occurred
0311 A flag error occurred
EREG2 = offending argument when the error occurred
ALU02
MULUB
.
0012 All Tests Passed
EREG2= 0000
0112 Incorrect multiplication result was detected
. EREG2 = Multiplier/Multiplicand
ALU03
Multiply/Divide Table
0013 All Tests Passed
EREG2 = 0000
0115 A signed operation failed
EREG2 = offending argument on error
0215 An unsigned operation failed
EREG2 = offending argument on error
0315 A flag error occurred
EREG2 = offending argument on error
ALU04
Multiply/Divide Random
0014 All Tests Passed
EREG2 = 0000
0115 A signed operation failed
EREG2 = offending argument on error
0215 An unsigned operation failed
EREG2 = offending argument on error
0315 A flag error occurred
EREG2 = offending argument on error
ALU05
Multiply/Divide Core
0015 All Tests Passed
EREG2 = 0000
0115 A signed operation failed
EREG2 = offending argument on error
0215 An unsigned operation failed
EREG2 = offending argument on error
0315 A flag error occurred
EREG2 = offending argument on error
7-58
MCS®-96 Diagnostics Library
D96A96
All Tests in ASM96
0030 All Tests Passed, checksum is ready
EREG2 = 16-bit checksum
D96FST
Selected Tests in ASM
OOEO All Tests Passed, checksum is over range specified
EREG2 = 16-bit checksum
D96P96
ALL Tests in PLM96
OOFO All Tests Passed, checksum is ready
EREG2 = 16-bit checksum
DSTA2D
AID Conversion Complete
01 CO An unexpected AID conversion result was found
EREG2 = Channel number of unexpected result
DSTEX1
External Interrupt (Supervisor)
01AO One or more DST Module did not execute on time
EREG2 = Number of SHIFTs done
DSTHSI
High Speed Inputs
0161 A high pulse on HSI.2 had an unexpected width
EREG2 = difference between actual and expected pulse width
0261 A low pulse on HSI.2 had an unexpected width
EREG2 = difference between actual and expected pulse width
0361 A high pulse on HSI.3 had an unexpected width
EREG2 = difference between actual and expected pulse width
0461 A low pulse on HSI.3 had an unexpected width
EREG2 = difference between actual and expected pulse width
0561 HSI unit indicated an HSI.1 event occurred
EREG2 = Time recorded in HSI FIFO
DSTISR
DST Initialization
0040 Initialization completed satisfactorily
EREG2 = 0000
0140 An abnormal RESET occurred
EREG2 = TIMER1
0240 T2CLK will not change
EREG2 = xxxx
0340 T2RST pin would not RESET T2CLK
EREG2 = xxxx
0440 IOCO.1 would not RESET T2CLK
EREG2 = xxxx
DSTSER
Serial Port
0180 An unexpected serial character was received
EREG2 = 8ad character received
0280 A carriage return was received out of sequence
EREG2 = number of characters since a carriage return
7-59
~CS®-96
OSTSWT
Diagnostics Library,
Software Timers
01 DO Found unexpected value on PORT1
EREG2 = expected value in high byte, actual in low byte
01 01 Invalid T2CLK value reached
EREG2 = T2CLK
0200 'NO Done did not occur within BURST window
EREG2 = Time between NO done and Software Timer 0
, 0201 Test reached an illegal Software Timer 0 state
EREG2 = Illegal case jump made
0300 REAL TIME update did not occur within BURST window
EREG2 = Time between REAL TIME update and Software Timer 0
0400 HSO.O response did not occur within BURST window
EREG2 = Time between HSO.O update and Software Timer 0
0500 HSI(.O) response did not occur within BURST window
EREG2 = Time between HSI(.O) service and Software Timer 0
OSTTOV'
Timer Overflows
0190 An overflow of T2CLK was indicated
EREG2 = TIMER1
xx91 (user defined)
EREG2 = (user defined)
MEM01
Complementary Address (Registers)
0021 All Tests Passed
EREG2 = 0000
0121 A memory location failed
EREG2 = address of the error
MEM02
Walking OneslZeros (Registers)
0022 All Tests Passed
EREG2 = 0000
0122 A memory location failed
EREG2 = address of the error
MEM03
Galloping Ones/Zeros (Registers)
0023 All Tests Passed
EREG2 = 0000
0123 A memory location failed
EREG2 = address of the error
MEM04
Bits Set
0024 No bits were set in the byte tested
EREG2 = 0000
0124 At least one bit was set in the byte tested
EREG2 = number of bits set
7-60
MCS®-96 Diagnostics Library
MEM05
Checkerboard Pattern (Registers)
0025 All Tests Passed
EREG2 = 0000
0125 A memory location failed
EREG2 = address of the error
MEM06
Complementary Address
0026 All Tests Passed
EREG2 = 0000
0126 A memory location failed
EREG2 = address of error
MEM07
Walking Ones
0027 All Tests Passed
EREG2 = 0000
0127 A memory location failed
EREG2 = address of the error
MEM08
Galloping Ones
0028 All Tests Passed
EREG2 = 0000
0128 A memory location failed
EREG2 = address of the error
MEM09
Walking Ones/Zeros
0029 All Tests Passed
EREG2 = 0000
0129 A memory location failed
EREG2 = address of the error
MEMOA
Galloping Ones/Zeros
002A All Tests Passed
EREG2 = 0000
012A A memory location failed
EREG2 = address of the error
MEMOB
Checksum
012B 16-bit Checksum is ready
. EREG2 = 16-bit Checksum
MEMOC
User Pattern (Registers)
002C All Tests Passed
EREG2 = 0000
012C A memory location failed
EREG2 = address of the error
MEMOO
User Pattern
0020 All Tests Passed
EREG2 = 0000
0120 A memory location failed
EREG2 = address of the error
7-61
MCS®-96 Diagnostics Library
SYS01
Common Symbols
0000 No Message
EREG2 = Offffh
SYS02
System Power-up
0002 All Tests Passed
EREG2 = OOOOh
0102 I/O Status Registers were unexpected
EREG2 = 10SO in low byte, IOS1 in high' byte
0202 TIMER1 did not change over time
EREG2 = TIMER1
0302 Zero Register was found to change
EREG2 = Program Status Word At Failure
0402 PUSHF or POPF failed
EREG2 = Erroneous PUSHed or POPed value found
0502 Sticky Bit would not set
EREG2 = 3fffh
0502 Sticky Bit would not clear
EREG2 = 0000
0602 Carry Flag Test Failed
EREG2 = xxxx
0702 Overflow flags would not set correctly
EREG2 = 0002h
0702 Overflow flags would not clear correctly
EREG2 = xxxx
0802 Interrupt Pending Register failed read/write test
EREG2 = offending Interrupt Pending byte
SYS03
Program Counter
0003 All Tests Passed
EREG2 = 0000
0103 Test Code Returned Early
EREG2 = Early Time
0203 Test Code Returned Late
EREG2 = Late Time
0303 Counter Register contained unexpected value
EREG2 = Erroneous Counter Value
7-62
APPENDIX C
DESCRIPTION OF DIAG96.LlB BATCH FILES
The batch files that come with the library will help speed the process of either linking
to the library as is, or revising library programs to suit custom purposes.
Some batch files require a parameter that provides the extension less name of a user
definable variable file to be included in the action of the batch file.
All DIAG96.LIB batch files assume that both the source and destination files reside in
the same directory. Given the size of the library, and the fact that all of the files will
not fit on one floppy disk, the command files will need to be edited if the user's system
is not equipped with a hard disk.
INSTAL. BAT - Used to install the library on a hard disk system. To install the library,
create a directory called \ DIAG96 under the main directory, insert disk I into drive
a: and type:
a:Instal
DST360K .BAT & DSTl2MEG.BAT- CAUTION: THEE BATCH FILES WILL
FORMAT AND DESTROY ALL INFORMATION ON THE FLOPPIES USED.
These command files were created to make the DIAG96.LIB disk set. DST360K was
created for use with 360K floppy disks and requires three diskettes. DSTl2MEG was
created for use with 1.2M disks and only needs two diskettes. The batch files will prompt
you to change disks. MAKE SURE TO ENTER THE CORRECT DISK DRIVE
WHEN INVOKING THESE BATCH FILES. ALSO MAKE SURE TO INCLUDE
THE DRIVE ID IN THE COMMAND LINE. THESE BATCH FILES FIRST
FORMAT THE DISK, AND WE ALL KNOW WHAT WHEN DOS DEFAULTS
TO THE HARD DISK!!!!!!!!!!
For example:
DSTI2MEG a:
SCRUB.BAT- CAUTION: THIS FILE DELETES FILES USING WILDCARDS.
All Diagnostic Library related files are delected for the \ DIAG96 directory. SYS??
and MEM?? wildcards are used, so be forewarned. This batch file does not delete itself!!!!
To invoke this batch file, type:
Scrub
D96ASM.BAT - Assembles all General Diagnostic modules including the PLM
compilation of D96P96.P96. To invoke the batch file, get in the \ DIAG96 directory
and type:
D96ASM
DSTASM. BAT - Assembles all Dynamic Stability Test modules. To invoke the batch
file, get in \ DIAG96 directory and type:
DSTASM
D96LP •BAT - Copies all General Diagnostic list files to a printer. Invocation must
include a device where the printer resides. For example:
D96LP lptl
DSTLP . BAT - Copies all Dynamic Stability Test modules to a printer. Invocation
must include a device where the printer resides. For example:
DSTLP.BAT Iptl
LPONLY • BAT - Executes D96LP.BAT and DSTLP.BAT. Invocation must include
a device where the printer resides. For example:
LPONLY lptl
7-63
MCS®-96 Diagnostics Library
D96LIB.BAT - Deletes the current DIAG96.LIB collection. Also creates a new library
of the same name using the files resident in the \ DIAG96 directory bearing the General
Diagnostics names. The DST96.LIB is not altered, and is included in the new
DIAG96.LIB. To invoke the batch file, get in the \ DIAG96 directory and type:
D96LIB
DSTLIB.BAT- Deletes the current DST96.LIB collection. Also creates a new library
of the same name using the files resident in the \ DIAG96 directory bearing the
Dynamic Stability Test names. Since DST96.LIB is included in DIAG96.LIB,
DIAG96.LIB is recreated by an invocation of D96LIB.BAT. To invoke this batch file,
get in the \ DIAG96 directory and type:
DSTLIB
DSTRL.BAT - This batch file is of most interest to Dynamic Stability Test users. It
links a specified main task to the library. This file makes assumptions about the hardware
memory implementation that may not be correct. Therefore minor changes may need
to be made to the DSTRL.BAT RL96 invocation statement. A file name without extension must be provided and that file must reside in the \ DIAG96 directory. The batch
file assumes that the extension of the object file to be linked to the library is .OBJ. For
example:
DSTRL Example_task
BLASTP • BAT - This batch file assembles the specified input file, then executes
D96ASM.BAT, DSTASM.BAT, LPONLY.BAT, DSTLIB.BAT, and DSTRL.BAT.
Then, the listfile output of the user's assembly and the print file of the linkage are
copied to the printer specified. The batch file assumes that the input .file is in the
\ DIAG96 directory and has a .A96 extension. For example:
BLASTP Example_ lptl
BLASTN . BAT - This batch file executes all assemblies, compliations, and linkages
executed in BLASTP.BAT, but no copies are sent to the printer. The batch file assumes
that the input file is in the \ DIAG96 directory and has a .A96 extension. For example:
BLASTN Example_task
REGEN •BAT - Used to regenerate the library when only one module has changed.
Specify the module that has changed when invoking this batch file. For example:
REGEN ALU03
MAKPLM.BAT - Used to make an impostor PLM96.LIB. The library created in not
a real PLM96.LIB, and will not work with PLM programs. However, it is what is needed
to use DIAG96.LIB. To invoke this batch file, get in the \ DIAG96 director and type:
MAKPLM
MAKBH.BAT - Used to modify the library to run in an 8X9XBH. The 8X9XBH
fails a flag test because of the - 90 bug relating to the Z flag on add and subtract with
carry is inadvertantly verified by a library test. To invoke this batch file, get in the
.\ DIAG96 directory and type:
MAKBH
D96RL.BAT - A generalized command that links target modules to DIAG96.LIB. It
is intended for used when only' the General Diagnostics are being used. Provide the
target object file name and the directory in which it resides. For example:
D96RL \ SOURCE \ Example_
7-64
SERIES-III MCS-96 MACRO ASSEMBLER. Vl.9
m
><
3
"0
i"
SOURCE FILE: :F5:D96A96.A96
OBJECT FILE: :F5:D96A96.0BJ
CONTROLS SPECIFIED IN INVOCATION COMMAND: NOGEN DEBUG
ERR LOC
OBJECT
LINE
1
2
3
4
5
6
7
8
9
H'
11
12
13
14
15
16
17
18
19
2121
21
22
23
24
25
26
27
28
29
3121
31
""I
I
0)
0'1
32
9999
3121121121
=1
=1
=1
=1
33
34
35
36
37
38
39
4121
41
42
43
44
45
46
41
48
49
5121
~l
D)
SOURCE STATEMENT
;***************************************************** ***********~*******
ALL TESTS ASM96
MODULE STACKSIZE(2121)
;******************************************************************* 0030
in order to run this module. the STACK must be ALL external. and the
data ram partitioned for memory test must not include ANY of the STACK
(3
ca
...
D)
3
r
To call this module
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
CALL
."
#
#
#
#
i
i
#
#
#
#
D96A96
~
::J
ca
(I)
»
"tJ
"tJ
m
Z
C
Remember. this test will take a long time if large memory reqions are
partitioned. or if a large number of cycles of random test numbers is
requested. For example. with 8Kbytes of Ram in each reqion the test
executes in 3 hours.
><
C
It is suggested that for large memory tests. that the complimentary
address test be done on the whole region at once. Then. the more
: ,exhaustive tests done on each memory' chip in the system.
;***************************************************** *************~**.*
rseg
extrn sp,ereql.ereq2
cseg at 3999h
extrn sysI2l1.sys92.sys93.alu91.alu92.alu93.alu94.alu95
extrn mem01.mem92.mem03.mem94.mem95.mem96.mem07.mem08
extrn mem99.meml2la.mem9b.mem9c.mem9d
cCO
PUBLIC D96A96
$eject
$inc1ude (:f3:dstmac.inc)
en
:provides the macro BR ON Error
:*************************************************************************
:DST Macros
INCLUDE FILE :********************************************
:*************************************************************************
»
CO
en
ERR LOC
OBJECT
0000
0000 EF0000
E
000A EF0000
E
0014 EF0000
~
I
0)
0)
E
001E EF0000
E
0028 CB000C
002B CB000C
002E EF0000
E
E
E
0038 CB0006
003B CB0006
003E EF0000
0048 EF0000
0052 EF0000
005C EF0000
0066 C800
0068 EF0000
0072 EF0000
007C CB0014
007F CB0014
0082 FoF0"'00
E
E
E
E
E
E
E
E
E
F:
E
E
LINE
104
105
106
107
11218
109
110
114
115
116
11'1
121
122
123
124
128
129
130
131
135
136
137
138
139
140
144
145
146
147
148
149
153
154
155
156
160
161
162
163
167
168
169
170
174
175
176
177
178
182
183
184
185
189
190
191
192
193
SOURCE STATEMENT
D96A96.
CALIJ sys02
BR_ON_ERR
rCAI.L the System Power Up TestError Found
CALL alu01
BR ON ERR
rCALL the Add/Subtract test
Error Found
CALL alu02
BR ON ERR
rCALL the MULUB test
Error Found
CALL a-lu03
BR_ON_ERR
PUSH
PUSHCALL alu04
BR-ON ERR
PUSH
PUSH
CALL alu05
BR ON ERR
rCALL the Multiply/Divide Table
rdriven test
Error Found
0ch[sp]
0ch[sp]
Error Found
06h[sp]
06h[sp]
rCALL a Complementary Address test
ron the internal reaisters
Error Found
CALL mem02
BR ON ERR
rCALL a Walking Is/0s test on
rthe internal registers
Error Found
CALL mem03
BR ON ERR
PUSH
CALL mem04
BR ON ERR
rCALL a Galloping Is/0s test on
rthe internal re9isters
Error_Found
zero
PUSH
PUSH
CALL mem06
rPUSH a zero
:CALL the Bits Set Test
Error_Found
CALL mem05
BR ON ERR
rCALL a Checkerboard Pattern test
:for internal registers
Error Found
14h[sp]
14h[sp]
~
n
\Il
@)
~
\:!
rPUSH an argument
rPUSH another argument
rCALL the Multiply/Divide Core Test
Error_Found
CALL memlH
BR ON ERR
r-PUSH a random seed
rPUSH the number of tests desired
rCALL the Multiply/Divide Random test
PUSH the start address
and the end address of a RAM area
and CALL a Complementary Address tesl
=
=
0
'"g.
(IQ
'"
~
.,
.,=
'<
ERR LaC
OBJECT
l!Jil8C CBI!J1!J11!J
ilI!J8F CB01!J1i1
1!J1!J92 EFI!JI!JI!JI!J
01!J9C CBI!JI!J14
1!J1!J9F CBilI!J14
£)I!JA2 EF00I!JiI
00AC CBI!JI!J10
I!JI!JM' CB0011!J
I!JI!JB2 EFill!Jl!J1iI
I!JIlBC CB01i114
01i1BF CBilI!J14
0I!JC2 EFI!J001!J
E
E
E
E
E
E
E
E
E
E
E
E
LINE
194
198
199
2i1I!J
21!J1
202
21!J3
21!J7
21!J8
21!J9
2Hl
211
212
216
217
218
219
221!J
221
225
226
227
228
229
2311
.......
I
(J)
.......
0i1CC CB0010
il0CF CBI!JI!J10
0I!JD2 EFI!J001!J
E
E
E
I!J.0DC CBI!J014
1!J0DF CB01!J14
0I!JE2 EFI!J1!J01!J
E
E
E
l!JilEC CBI!JI!J10
0I!JEF CB0010
I!JI!JF2 EF001!J1!J
E
E
E
I!JI!JFC CB01!J14
I!JI!JFF CB0014
I!JlI!J2 EFI!J01!J0
E
E
E
1!J10C CB0011!J
I!Jll!JF CBI!J011!J
0112 EF01!J1!J1!J
E
E
E
234
235
236
237
238
239
241!J
244
245
246
247
248
249
253
254
255
256
257
258
259
263
264
265
266
267
268
272
273
274
275
276
277
SOURCE STATEMENT
BR ON ERR
Error Found
PUSH
PUSH
CALL memI!J6
BR ON ERR,
PUSH
PUSH
CALL mem07
BR ON ERR
PUSH
PUSH
CALL memI!J7
BR ON ERR
PUSH
PUSH
CALL memI!J8
BR ON ERR
1i1h[sp]
1l!Jh[sp]
PUSH a second start and end address '
and repeat the
Complementary Address test
Error Found
14h[sp]
14h[sp]
PUSH a start address
PUSH an endinq address
CALL a lla1king Ones test
Error Found
1l!Jh[sp]
Hlh[sp]
PUSH the start and end address
for another section of RAM
and repeat the lla1king Ones test
Error Found
14h[sp]
14h[sp]
PUSH a start address
PUSH an endinq address
CALL a Gallopinq Ones test
is:
I"l
rIl
@
I
'-C>
~
Error 'Found
t::1
;.
IJQ
PUSH
PUSH
CALL mem08
BR ON ERR
-
-
PUSH
PUSH
CALL memI!J9
BR ON ERR
PUSH
PUSH
CALL memI!J9
BR-ON ERR
PUSH
PUSH
CALL meml!Ja
BR ON ERR
PUSH
PUSH
CAI"L mem0a
1l!Jh[sp]
10h[sp]
PUSH a second start and end address
for another region of RAM and
CALL the Galloping Ones test again
Error Found
=
0
'"g.
'"
....t:
...
...
0>
14h[sp]
14h[sp]
PUSH the start and end address of
a region of RAM
CALL the Ilalking Is/l!Js test
Error Found
1l!Jh[sp]
10h[sp]
PUSH the start and end address of
another region of RAM
CALL the waiking IS/0s test again
Error" Found
14h[sp]
14h[sp]
PUSH the start and end address of
a reqion of RAM
CALL a Galloping Is/l!Js test
Error Found
10h[sp]
lI'Ih[sp]
PUSH the start and end address of
another rea ion of RAM
CALI" the Galloping Is/l!Js test again
'
0
5'
""=
0
'"
'"
~
i'r
.=~.
'<
SERIES-III PL!M-96 VI.0 COMPILATION OF MODULE ALLDIAG96TESTS
OBJECT MODULE PLACED IN :F2:D96P96.0BJ
COMPILER INVOKED BY: PLM96.86 :F2:D96P96.P96 CODE DEBUG
AIl$Diaq96$Tests:
I
DO~
-...j
I
-...j
0
2
3
1
2
SYS02: PROCEDURE mlORD
END SYS02~
4
5
£>
1
2
2
SYS03: PROCEDURE ( parmI. parm2) D.IORD EXTERNAL ~
DECI,ARE
(parmI. parm2) ~lORD~
END SYS03~
7
8
I
2
ALU0I: PROCEDURE DHORD EXTERNAL;END ALU0I~
9
10
I
2
ALU02: PROCEDURE mmRD
END ALU02~
11
12
1
2
ALU03: PROCEDURE ml0RD EXTERNAL:
END ALU03~
13
14
15
I
2
2
ALU04: PROCEDURE (parmI.parm2) DWORD EXTERNAL:
DECLARE
(parmI. parm2) ~lORD:
END ALU04:
16
17
18
1
2
2
ALU05: PROCEDURE (parmI.parm2) DWORD EXTERNAL:
DECLARE
(parmI.parm2) WORD:
END ALU05:
19
20
1
2
MEM0l: PROCEDURE DWORD EXTERNAL:
END MEI~0I:
21
22
2
MEM02: PROCEDURE DWORD EXTERNAL:
END MEM02~
23
24
I
2
MEM03: PROCEDURE DWORD EXTERNAL:
END MEM03:
25
26
27
1
2
2
MEM04: PROCEDURE (parml) mlORD EXTERNAL:
DECLARE
(parmI) HORD:
END MEM04~
28
29
I
2
MEM05: PROCEDURE DWORD EXTERNAL:
END MEM05~
30
31
32
1
MEM06: PROCEDURE (parm!.parm2) Dl/ORD EXTERNAL:
DECLARE
(parml.parm2) HORD:
END MEM06:
33
34
35
1
2
2
1
2
2
EXTERNAL~
EXTERNAL~
MEMI17: PROCEDURE (parml.parm2) DWORD EXTERNAL:
(parmI.parm2) WORD~
DECLARE
END ~IEM07~
~
I":l
r.n
\"'
\Q
~
~
(JQ
=
0
~
n'
'"t:
t:I"
...
10
'
-...s
I
-...s
.....
\C
CI\
.r
I:'
255 THEN GOTO end$tests:
61
62
2
2
reslllt=AI,UlH:
IF error$codes. number > 255 THEN Go'ro end$tests:
£.4
65
2
2
reslllt=ALU02:
IF error$codes.nllmber > 255 THEN GOTO end$tests:
67
68
2
2
resllIt=AI.U03:
IF error$codes.number > 255 THEN GOTO end$tests:
711
2
reslllt=AI.U04 (4 7efH,100011):
=
C>
~
;;.
'"!:
.,...
.,
.,
'<
71
2
IF error$codes.nurnber > 255 THEN GOTO-end$tests:
73
74
2
2
resu1t=ALU~5(argument1,argument2):
76
77
2
2
79
2
2
resu1t=MEM~2:
8~
82
83
2
2
resu1t=MEM~3:
85
86
2
2
IF error$codes.nurnber > 255 THEN GOTO end$tests:
88
89
2
2
IF error$codes.nurnber > 255 THEN GOTO end$tests:
91
92
2
2
94
95
~-
I
2
2
IF error$codes.nurnber > 255 THEN GOTO end$tests:
resu1t=MEM~1:
IF error$codes.nurnber > 255 THEN GOTO end$tests:
IF error$codes.nurnber > 255 THEN GOTO end$tests:
IF error$codes.nurnber > 255 THEN GOTO end$tests:
resu1t=MEM~4(~):
resu1t=MEM~5:
resu1t=MEM~6(ram1$start,rarn1$stop):
IF error$codes.nurnber > 255 THEN GOTO end$tests:
resu1t=MEM~6(ram2$start,rarn2$stop):
IF -error$codes.nurnber > 255 THEN GOTO end$tests:
resu1t=MEM~7(rarn1$start,rarn1$stop):
97
98
2
2
1~~
2
2
resu1t=MEM~7(rarn2$start,rarn2$stop):
101
103
104
2
2
resu1t=MEM~8(rarn1$start,rarn1$stop):
106
107
2
2
resu1t=MEM08(rarn2$start,rarn2$stop):
IF error$codes.nurnber > 255 THEN GOTO end$tests:
109
110
2
2
resu1t=MEM09(rarn1$start,raM1$stop):
IF error$codes.nurnber > 255 THEN GOTO end$tests:
112
113
2
2
resu1t=MEM09(rarn2$start,rarn2$stop):
IF error$codes.nurnber > 255 THEN GOTO end$tests:
115
]16
2
2
IF error$codes.nurnber > 255 THEN GOTO end$tests:
118
119
2
2
resu1t=MEM0A(rarn2$start,rarn2$stop):
IF error$codes.nurnber > 255 THEN GOTO end$tests:
121
122
2
2
resu1t=MEM0C(bit$pattern):
IF error$codes.nurnber > 255 THEN GOTO end$tests:
124
125
2
2
resu1t=MEM00(rarn1$start,rarn1$stop,bit$pattern):
IF error$codes.nurnber > 255 THEN GOTO end$tests:
127
2
resu1t=MEM00(rarn2$start.rarn2$stop.bit$pattern):
IF error$codes.nurnber > 255 THEN GOTO end$tests:
~
~
IF error$codes.nurnber > 255 THEN GOTO end$tests:
IF error$codes.nurnber > 255 THEN GOTO end$tests:
~
~
00
@
~
~
0
~
~
=
=
~
~
~
~
~
~
~
~
~
resu1t=MEM~A(rarn1$start,rarn1$stop):
128
2
IF error$codes.number > 255 THEN GOTO end$tests;
130
131
2
2
resu1t=SYS03(ram1$start.ram1$stop);
IF error$cooes.number > 255 THEN GOTO eno$tests;
133
134
2
2
resu1t=SYS03(ram2$start.ram2$stop);
IF error$codes.number > 255 THEN GOTO end$tests;
136
2
resu1t=MEM0B(20S0h.top$of$code);
137
2
error$codes.number=00f0h;
~
I"l
fFJ
,
@
\C
=--
~
-...I
I
-...I
(.,)
138
139
140
end$tests:
2
RETURN
result:
END D96P96;
END Al1$Diag96$Tests;
0;-
IJQ
=
'"nQ;
'"~
Q
...
or
~
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STATEMENT
~
I
"'"'""
56
D96P96:
~~~9
1111119
11902
C809
A91890
E
E
9005
0098
9~"1B
EF9009
AI!I1E02
A01C90
E
R
R
090E
9912
89FF0090
D102
R
0914
2226
9016
0916
0919
991C
EF9099
A91E02
A91C99
E
R
R
091F
0023
89FF9990
D102
R
0925
2215
PUSH
LD
?FRAMEIl1
?FRAMEIH • SP
STATEMENT
58
CALL SYS92
LD
RESULT+2H.TMP2
LD
RESULT.TMP9
STATEMENT
59
CMP
ERRORCODES.#0FFH
@9991
BNH
STATEMENT
60
BR
ENDTESTS
61
STATEHENT
@0001:
9927
0027
002A
992D
EF0999
A01E02
AIHC09
E
R
R
0930
9034
89FF0000
D102
R
0936
2294
CALL
LD
LD
ALU91
RESULT+2H.TMP2
RESULT.TMP9
STATEMENT
62
ERRORCODE_S. #OFFH
CMP
@9992
BNH
STATEMENT
63
BR
ENDTESTS
STATt:MENT
64
@9002:
0038
0938
093B
003E
EF0900
A91E92
A91C99
E
R
R
0941
0945
89FF9900
D102
R
0947
21F3
C9EF47
C99010
EFI:J900
A01E92
AIHC09
AI,U02
RESULT+2H.TMP2
RESULT.TMP0
65
STATEMENT
ERRORCODES.t0FFH
CMP
BNH
@9093
66
STATEMENT
BR
ENDTESTS
STATEMENT
67
CALL
LD
LD
0958
"05C
89FF0009
D102
005E
21DC
CALL
LD
LD
ALU93
RESULT+2H.TMP2
RESULT.TMP9
68
STATEMENT
CMP
ERRORCODES.t0FFH
@9904
BNH
STATEMENT
69
BR
ENDTESTS
STATEMENT
70
@9994,
ER
R
R
("'l
1Jl
@)
,c
~
@0003:
0949
9949
094C
004F
0952
9055
::
#47EFH
#1000H
ALU04
RESULT+2H.TMP2
RESllLT.TMP0
LD
STATEMENT
71
ERRORCODES.#0FFH
C'IP
IlNII
@0005
STATt:MENT
72
BR
END1'ESTR
STATt:MENT
73
PUSH
PUSH
CALL
LD
Si!
DO
IIQ
0
.,=
g.
.,
~
..
DO
'<
-...J
I
-...J
CJ1
0060
0060
0063
00(;6
0069
006C
CB0008
C80006
EF0000
A01E02
A01C00
E
E
E
R
R
006F
0073
89FF0000
D102
R
0075
21C5
0077
0077
01<17A
007D
Er'0000
A01E02
A01C0e
E
R
R
0080
0084
89Fr'0000
R
0!l86
21B4
@0005:
PUSH
PUSH
CALL
LD
LD
ARGUMENT1[?FRAME01]
ARGUMENT2[?FRAME01]
ALU05
RESULT+2H.TMP2
RESULT.TMP0
STATEMENT
74
r
CMP
ERRORCODES.i0FFH
8NH
@0006
STATEMENT
75
8R
ENDTESTS
76
STATEMENT
@0006:
CALL
LD
LD
MEM01
RESULT+2H.TMP2
RESULT.TMPe
STATEMENT
77
CMP
ERRORCODEs.#eFFH
@0007
BNH
STATEMENT
78
BR
ENDTESTS
STATEMENT
79
D1e2
0088
91388
0e8B
0e8E
EF00ee
A01Ee2
A91C01:l
E
R
R
CALL
LD
LD
MEM92
RESULT+2H.TMP2
RESULT.TMP9
STATEMENT
813
91391
9095
89FFe9ge
D192
R
CMP
BNH
01397
21A3
ERRORCODES.ieFFH
@e008
STATEMENT
81
ENDTESTS
STATEMENT
82
0099
01399
@ee97:
@ee98:
e09C
009F
E
R
R
00A2
00A6
89FF0e00
D102
R
e0A8
2192
eeAA
eeM
ei:lAC
00AF
i:li:lB2
C80i:1
Er'00ee
A01E02
MHC00
01385
00B9
89FFe000
D102
l1i:1B8
217F
00BD
00BD
00C0
EFoe00
A0H:02
CALL
LD
LD
MEM03
RESULT+2H.TMP2
RESULT.TMPe
STATEMENT
83
CMP
ERRORCODEs.#eFFH
BNH
@e0e9
STATEMENT
84
BR
ENDTESTS
STATEMENT
85
@ee09:
PUSH
CALL
LD
LD
Re
MEH04
RESULT+2H.TMP2
RESULT.TMP0
STATEMENT
86
ERRORCODES.i0FFH
CMP
@00eA
BNH
STATEMENT
87
BR
ENDTESTS
STATEMENT
88
E
R
R
R
@i:l00A:
E
R
("'l
rJl
BR
Er'eeee
MIlE02
A01cee
a:
CAr.L
I.D
MEM05
IlESULT+2H.TMP2
€I
I
IC
=~
II>
""=
0
'"0".
t>
'"t:
..
r::r
II>
'<
.......
I
.......
(J)
01lC3
AIlICfl0
R
LO
00C6
IlIlCA
89FF01l00
0102
R
CMP
BNH
01lCC
216E
BR
00CE
00CE
01101
01104
11007
01l0A
CB01l16
CB0014
EFfiJ01l1l
AIlIEIl2
AIlICIlIl
E
E
E
R
R
11000
01lEI
89FFIlllllll
01112
R
IlllE3
2157
1l0E5
01lE5
1l0E8
IlIlEB
00EE
IlflFl
CBIlll12
CBIllllll
EFIlllflll
AIlIEfl2
All 1 CIlIl
E
E
E
R
R
IlllF4
fiJ1lE'8
89FFIlllllll
0102
R
01lFA
2140
01lFC
fl0FC
01WF
11102
01115
01118
CB0016
CBIlll14
EF01l00
A01E02
AIlIC00
E
E
E
R
R
011lB
!llflF'
89FFflllllfl
0102
R
0111
2129
Illi3
0113
11116
0119
IlllC
01H'
CB01l12
CB0010
EF0000
A01EIl2
A01C00
E
E
E
R
R
0122
0126
89FF0001l
0102
R
fl128
2112
012A
RESULT.TMPIl
STATEMENT
89
ERRORCOOES.#0FFH
@1l01lB
STATEMENT
91l
ENOTESTS
STATEMENT
91
@00IlB:
PUSH
PUSH
CALL
LO
LO
RAMlSTART[?FRAME01]
RAMlSTOP[?FRAME01]
MEMIl6
RESULT+2H.TMP2
RESULT.TMPIl
STATEMENT
92
CMP
ERRORCOOES.#IlFFH
llNH
@IlIlIlC
STATEMENT
93
BR
ENOTESTS
STATEMENT
94
@IlIlIlC:
PUSH
PUSH
CALL
LO
LO
RAM2START[?FRAMElll]
RAM2STOP[?FRAMElll]
MEM06
RESULT+2H.TMP2
RESULT.TMPIl'
95
STATt:MENT
CMP
ERRORCOOES.#IlFFH
BNH
@001l0
96
STATEMENT
BR
ENOTESTS
STATEMENT
97
@01l1l0:
PUSH
PUSH
CALL
LO
LO
RAmSTART[?FRAME01]
RAM1STOP[?FRAME01]
MEM07
RESULT+2H.TMP2
RESULT.TMP0
STATEMENT
98
CMP
ERRORCOOES.#0FFH
BNH
@000E
STATEMENT
99
BR
ENOTESTS
STATEMENT
100
@000E:
PUSH
PUSH
CALL
LO
LO
RAM2START[?FRAMElll]
RAM2STOP[?FRAME01]
ME~107
RESULT+2H.TMP2
RESULT.TMP0
STATEMENT
101
CMP
ERRORCOOES.#0FFH
BNH
@fl01lF
STATEMENT
Hl2
BR
ENnTESTS
STATt:MENT
103
@IHlIJF:
=:t"'l
rn
@I
I
IC
0\
t;;
;.
(JQ
=
Q
~
;:;.
'"
t::
CI"
....
'<
-...j
I
-...j
-...j
012A
'H2D
0130
0133
0136
CB0016
CB0014
EF0000
A01E02
A01C00
E
E
E
R
R
0139
013D
89FF0000
DI02
R
013F
20FB
0141
0141
0144
0147
014A
014D
CB0012
CB0010
EF0000
AOIE02
AOIC00
E
E
E
R
R
0150
0154
89~'FOOOO
R
D102
0156
20E4
0158
0158
015B
015E
0161
0164
CB0016
CB0014
EF0000
A01E02
AOIC00
PUSH
PUSH
CALL
I.D
LD
RAMlSTART[?FRAME01]
RAMlSTOP[?FRAME01]
~IEM08
RESULT+2H. nlP2
RESULT. T~IP0
STATEMENT
104
CMP
ERRORCODES.#OFFH
BNH
@0010
STATEMENT
105
BR
ENDTESTS
STATEIIENT
106
@0010:
PUSH
PUSH
CALL
LD
LD
RAM2START[?FRAMEOl]
RAM2STOP[ ?FRAHEOl]
~IEM08
RESULT+2H.TMP2
RESUL'r. TMPO
STATEMENT
107
CMP
ERRORCODES.#OFFH
BNH
@0011
STATEMENT
108
BR
ENDTESTS
STATEMP.NT
109
@O'lJll:
0167
016B
89FF0000
D102
016D
20CD
E
E
E
R
R
PUSH
PUSH,
CALL
LD
LD
RAMlSTART[?FRAMEOl]
RAMlSTOP[?FRAMEOl]
MEM09
RESULT+2H.TMP2
RESULT.TMPO
STATEMENT
110
CMP
P.RRORCODES.#0FFH
BNH
@0012
STATEMENT
111
BR
ENDTESTS
STATEMENT
11-2
R
016F
016F
0172
0175
0178
017B
CB0012
CB00HJ
EF0000
A01E02
A01C00
E
E
E
R
R
017E
0182
89FF0000
D102
R
0184
20B6
0186
101B6
0189
l118C
l11BF'
0192
CBOO16
CB0014
EFl1000
A01E02
A01C00
E
E
E
R
R
0195
0199
89FFI0000
DHI2
H
@0012:
PUSH
PUSH
CALL
I.D
LD
RAM2START[?FRAME01]
RAM2STOP[?FRAME01]
MEM09
RESULT+2H.TMP2
RESULT.TMPO
STATEMENT
113
CMP
ERRORCODES.#OFFH
BNH
@0013
STATEMENT
114
BR
ENDTESTS
STATEMENT
115
@0013:
PUSH
PUSH
CALL
LD
LD
RAIIlSTART[ ?FRAMEl11]
RAM1STOP[?FRAMEOl]
MEMOA
RESULT+211.TMP2
Rl:~SULT. nlPo
STATEllENT
116
CMP
ERRORCODES.#OFF'H
RNH
@0014
3:
("'l
'JJ
\"l
~
0,
t::I
S"
IJC
=
0
Ul
;:;"
Ul
...t:..
..
~
'<
lH9H
-..j
I
-..j
00
21l9F
BR
STATEMENT
ENOTESTS
STATEMENT
117
118
@1l014:
0190
lH90
IHA0
IllA3
IllA6
0lA9
CBIlll12
CHIllllll
EFIl01l1l
A0lEIl2
AillCIl0
E
E
E
R
R
ilIAC
IllB0
89FF01l1l1l
011112
R
IllB2
211188
01B4
0lB4
1l1B7
!llBA
1l1HO
CH01l1l4
EFIlIlIlIl
AlHEIl2
A!llCIl0
E
E
R
R
0lC0
(llC4
89~'F001l!l
R
01!l2
1l1C6
2074
0lCS
1l1CS
01CB
1l1CE
0101
111104
!l107
CBIl016
CBIl014
CB!l1l04
EFIl01l1l
AIl1EIl2
A0lCIl0
E
E
E
E
R
R
olOA
R
Ill0E
89FF1l0!l0
011112
0lE0
21l5A
RAM2START[?FRAMElll]
RAM2STOP[?FRAMElll]
ME MilA
RESULT+2H.TMP2
I.D
RESULT.TMPliI
STATEMENT
119
CMP
ERRORCOOES.#IlFFH
@01H5
BNH
STATEMENT
12111
BR
ENOTESTS
STATEMENT
121
PUSH
PUSH
CALL
LO
@1l1l15:
BITPATTERN[?FRAMElll]
MEMIlC
RESULT+2H.TMP2
RESULT.TMPIl
STATEMENT
122
ERRORCOOES.#IlFFH
CMP
BNH
@1l1l16
STATEMENT
123
BR
ENOTESTS
STATEMENT
124
PUSH
CALL
LO
LO
@1l016:
IcHE2
IllE2 CBIl0l2
IllE5 CBIl1l11l
illES . CBIl01l4
(llEH EF000111
!llEE AIl1EIl2
01Fl AIl1CIl0
0lF4
!llFS
S9FF0!l1l0
011112
0lFA
2040
0H'C
!llFC
IHFF
11121112
CBIlll16
CB0014
EF01l00
RAM1START[?FRAME01]
RAMISTOP[?FRAMEIl1]
BITPATTERN[?FRAMElll]
MEM00
RESULT+2H'. TMP2
RESULT.TMP0
STATEMENT
125
ERRORCOOES.#IlFFH
CMP
'HNII
@1l017
126
STATEMENT
ENOTESTS
BR
127
STATEMENT
PUSH
PUSH
PUSH
CALL
LO
LO
@1l0l7:
PUSH
PUSH
PUSH
CALL
LO
LO
RAM2START[?FRAMElll]
RAM2STOP[?FRAME0l]
BITPATTERN[?FRAME0l]
MEM00
RESULT+2H.TMP2
RESULT.TMPIl
12S
STATEMENT,
ERRORCOOES.#IlFFII
CMP
@lllllS
BNH
STATEMENT
129
ENOTESTS
BR
13111
STATEMENT
E
E
E
E
R
R
R
@1l1l1S:
E
E
E
PUSH
PUSH
CALL
RAM1START[?FRAMElll]
RAM1STOP[?FRAME0l]
SYSIl3
::
("'l
rn
@J
I
~
C\
~
(JQ
=
Q
til
C;
n
til
......
!::
10
.......
"'235
"'208
A31E32
MJlC33
R
R
32"'B
"'23F'
89FF'331'W
D132
R
3211
2329
0213
3213
3216
3219
321C
321F
CB3012
CB33Hl
EF3333
A31E32
A31C33
E
E
E
R
R
3222
3226
89FF3033
D132
R
RESULT+2H,TMP2
RESULT,TMP3
STATEMENT
131
CMP
ERRORCODES.#3FFH
BNH
@3319
STATEMENT
132
BR
ENDTESTS
STATEMENT
133
@3319.
0228
2312
--oJ
1!122A
"'22A
022D
"'233
0233
3236
C98323
CB030A
EF0033
A31E32
A"'lC03
E
E
R
R
--oJ
CD
3239
ADF333
R
323C
023C
023F
3242
3244
3247
324B
A3321E
A3031C
CC30
A21822
65163318
E322
R
R
E
I
LD
LD
PUSH
PUSH
CALL
LD
LD
RA/12START[?FRAME31]
RAM2STOP[?FRAME31]
SYS03
RESULT+2t1.TMP2
RESULT,TMP3
STATEMENT
134
CMP
F.RRORCODES,#3FFH
_ BNH
@331A
STATEMENT
135
BR
ENDTESTS
STATEMENT
136
@331A.
#2380H
TOPOFCODE[?FRAME31]
MEM3B
RESULT+2H,TMP2
RESULT,TMP3
STATEMENT
137
:
LDBZE ERRORCODES,#3F3t1
STATEMENT
138
ENDTESTS.
LD
TMP2.RESULT+2H
LD
TMP3,RESULT
POP
?FRAME31
LD
TMP6,[SP]
ADD
SP, U6H
BR
[TMP6]
STATEMENT
139
STATEMENT
140
END
PUSH
PUSH
CALL
LD
LD
MODULE INFORMATION.
CODE AREA SIZE
CONSTANT AREA SIZE
DATA AREA SIZE
STATIC REGS AREA SIZE
OVERLAYA8LE REGS ARF.A SIZE
MAXIMUM STACK SIZE
183 LINES READ
PL/M-96 CmlPILATION CmIPLETE.
024DH
0333H
3033H
3"'34H
0033H'
3"'3AH
o
589D
3D
3D
4D
3D
10D
~IARNINGS.
'" ERRORfi
::
I"l
[JJ
~
\C
'"
t:I
;.
(IQ
=
c:>
~
(;'
fIl
.,.t:..
..
=
'<
MCS-96 MACRO ASSEMBLER
SELECTED TESTS ASM96
SERIES-III MCS-96 MACRO ASSEMBLER, Vl.0
SOURCE FILE: :F5:D96FST.A96
OBJECT FILE: :F5:D96FST.OBJ
CONTROLS SPECIFIED IN INVOCATION COMMAND: NOGEN DEBUG
ERR LOC
OBJECT
LINE
SOURCE STATEMENT
1
2
:************************************************************************
3
Selected Tests ASM96
4
:******************************************************************* 0031
MODULE
STACKSIZE(20)
5
6
7
13
LJ
Hl
11
12
13
14
15
16
17
--..j
I
SYMBOL TABLE LISTING
-------------------N A ME
--.I
I
CO
./:>-
ALUUl
ALUU2
ALUU3
ALU04
ALUU5
BR ON ERR
D96FST.
EREGl
EREG2
ERROR FOUND
~IACRO-TEMP .
MEMUl
MEMU2
MEMU3
MEM04
MEMU5
r1EMU6
MEM07
MEMU8
VALUE
"U0UH
"0D5H
mJ00H
~lEM09
MEMUA
MEM0B
MEMUC
MEM0D
RESET HATCHDOG.
RI.
SELECTED_JESTS_ASM96.
SP.
SP STAT
SPSTATUS.
SPIIAIT.
SYSUl
SYS02
SYSU3
TI.
ZERO.
ASSEMBLY COMPLETED,
0006H
0005H
NO ERROR(S) FOUND.
ATTRIBUTES
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
MACRO
CODE REL PUBLIC ENTRY
REG EXTERNAL
REG EXTERNAL
CODE REL ENTRY
REG REL BYTE
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAJJ
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
MACRO
NULJJ ABS
MODULE STACKSIZE(20)
REG EXTERNAL
REG EXTERNAL
MACRO
MACRO
CODE EXTERNAL
CODE EXTERNAL
CODE EXTERNAL
NULL ABS
REG EXTERNAL
a:::
('"l
[Jl
~
\0
C\
1:1
;.
.
""0=
:-.
'"r:>
'"t;
<:3"
...
...
'<
~
MCS-96 MACRO ASSEMBLER
DSTUSR
SERIES-III MCS-96 MACRO ASSEMBLER. Vl.0
SOURCE FILE: :F2:DSTUSR.A96
OBJECT FILE: :F2:DSTUSR.OBJ
CONTROLS SPECIFIED IN INVOCATION COMMAND: GEN DEBUG
ERR LOC
OBJECT
LINE
1
2
3
SOURCE STATEMENT
;***********************************************************************
DSTUSR
MODULE
main.stacksize{2)
~***************************************************** ******************
4
~
0040
0040
0040
6
-,
8
9
0000
oseg at 40h
User Registers: DSB
'temp
set
10
11
lch
User Reqisters:1I0RD
rseq
EXTRN sp.zero.timerl.eregl
12
13
14
15
16
17
18
19
20
21
0100
0100
4200
-...J
4200
I
DSEGI:
DSB
::n
;to ensure that the STACK does not qet
located in an area of RAM that wiil be
dseg at 100h
700h
memory tested. reserve those regions
as data segments.
[JJ
\'l
~
dseg at 4200h
DSEG2:
DSB
a-,
1::1
S·
ao
le00h
=
<>
n
(Xl
U1
~
~j
~080
~4
ri'
cseg,at 2080h
'"t""
25
~6
~080 AIFFliJ040
2084 E040FD
2087 A1000000
E
27
28
29
30
31
32
::;:
...
extrn
~lu04.alu01.alu02.mem0~.mem0a.error-proc.alu05
EXTRN DSTISR
LD
DJNZ
temp. #0ffh
temp.$
LD
sp.#STACK
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
PUSH
CALL
#l00h
#7ffh
#4200h
#5fffh
#47efh
#HHl0h
t3fffh
#9d42h
t77Bch
#5a5ah
DSTISR
....,e:
wait for sbe96 NMls to stop
33
208B
208E
2091
2094
2097
209A
2090
20M
20A3
20A6
20A9
C90001
C9FF07
C90042
C9FF5F
C9EF47
C90010
C9FF3F
C9429D
C98C77
C95A5A
EF0000
34
35
36
37
38
39
40
41
42
43
E
44
E
45
46
47
48
49
50
51
20AC
20AC C98080
20AF C90080
2082 EF0000
;RAM segmentl start address
;RAM seamentl end
a~dress
;RAM seqment2 start address
;RAM segment2 end
address
;random seed
;random test lenath
;top of code address
;an argument for mul/div test
;anoth~r aroument for mul/div test
:bit pattern for memory test
;CALL the Dynamic Stability Test
; initialization routine
....j
c:
(J)
Main Task:
push
push
call
c(J)
JJ
#8080h
#8000h
alu05
use the multiply/divide core
test on the arauments
ERR LOC OBJECT
20B5 980001
20BB OF022074
E
LINE
52
53
SOURCE STATEMENT
cmpb
eregl+l.zero
bne
error found
IJE
ISJMP
20BC
20BF
20C2
20C5
2£1C8
C90080
C98080
EF£I£l00
98£1£101
OF£l22064
20CC
20CF
2002
2005
2008
C90080
C90080
EF0000
980001
0756
200A
2000
20E0
20E3
20E6
C9B080
C90080
EF0000
980£101
0748
E
E
E
E
E
E
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
.
18080h and 18000h in all
; combinations
~+4
error found
push
push
call
cmpb
I
bne
IJE
$+4
ISJMP
combinations
IB000h
t8080h
alu05
ereql+l,zero
error found
error found
push
push
call
cmpb
bne
#8000h
18000h
alu05
eregl+l.zero
error_found
push
push
call
cmpb
bne
i8£180h
#8000h
alu05
eregl+l.zero
error found
push
push
Call
cmpb
bne
#l00h
#7ffh
mem0a
eregl+l.zero
error found
push
push
call
cmpb
bne
timerl
I 200£1h
alu04
eregl+lh,zero
error found
;send a timerl based seed to the
;'random number based multiply/divide
; test and let it run for a string
; of 2000h argument pairs
-
call
cmpb
bne
alu01
eregl+1h.zero
error found
;perform the add/subtract test
push
push
Call
cmpb
bne
#4200h
15fffh
Mem06
eregl+l.zero
error found
perform a Comple.mentary address test
on a larg~ section of RAM
call
cmpb
bne
alu02
eregl+lh.zero
error found
perform the MULUB test
push
push
call
cmpb
bne
timerl
t2£100h
alu04
eregl+1h.zero
error found
send another timer1 based seed to
the random number based mu1tip1y/
divide ,test
:::
@
l"
\C
CI\
72
......
I
ClO
Ol
20E8
20EB
20EE
20Fl
201:'4
C900'1Jl
C9FF07
EF00£10
980001
073A
20F6
20FB
20FB
20FE
2101
C800
C90020
EF0000
980001
0720
2103 EF0000
2106 980001
2109 0725
21"'B
210E
2111
2114
2117
C90042
C9FF5F
EF0000
980001
0717
E
E
E
E
E
E
E
E
E
2119 EF0000
211C 980001
211F 070F
E
E
2121
2123
2126
2129
212C
E
C800
C90020
EF0000
980001
0702
E
E
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
perform a ~alloping Is/0s test
on a small section of RAM
~
;.
~
0
'"g.
'"
t"'
...
6l
~
'
A(0..31]
Figure 2: Available In a 132-pln PGA, the 80960KB sparts
32 address/data lines and 6 signals that directly contral the
bus, resulting in a simple Interface. Several pins handle
reset, bus master arbitration, bad system access, and
clocking. This processor's ability to address large amounts
of Inexpensive memory proves to be a major plus.
and the other counter from the word address bits, LAD(2:3),
which must be incremented for each subsystem word access (except DRAMs with internal counters). These2-bit counters can fit
easily into one 16R6D PAL.
The address word up-counter generates the word-addressing
bits, A(2:3), forthe address bus. Loaded with LAD(2:3), this
counter can start on any word address boundary, counting up until the burst access is finished or until it reaches a 16-byte boundary. Because bursts cannot cross 16-byte boundaries, the up. counter does not wrap around. If a burst is a two-word access that
starts at word address 1, then the word address counter initializes
at I, counts to 2, then stops.
If a burst is four words and starts on a word address other than
on a 16-byte boundary, the 80960Iq3 will issue an access with the
size bits set so that the access cannot cross 16-byte boundaries.
Then it will issue another access, with appropriate size bits to
finish the original burst request. The system clock aM READY
signals enable the word address and burst size counters. By issuing the appropriate size bits to maintain the 16-byte boundary
condition, the 80960KB intelligent bus interface helps simplify
the burst control design.
Where memory subsystems (Figure 4) are concerned, a
language like PostScript requires 350 to 450 Kbytes; 512 Kbytes,
plus some initialization code, will be sufficient, and four 27010s
will do the job. Because these have a 200-nsec access time, it's
necessary to use 2-2-2-2 wah-state timing-two being the
number of wait states necessary lOr each data cycle in a lOur-word
burst access.
Holding Fonts in Flash .
By holding font information in flash memory devices (e.g., the
28F25632K x 8), fonts can be modified or updated very quickly. The nonvolatile flash is similar to EPROM except that to update the memory, the 80960KB simply writes a command to the
control register, then starts writing new data. The 8F256's
170-nsec access translates into 3-3-3-3 wait-state timing. The
fonts are accessed, then cached in faster memory by the PDL
driver. Three signals control this device: FSHSELU, RDU, and
WRU.
Because two font descriptions fit into 128 Kbytes, 32-bit
memory s·ubsystems can be configured from only four flash
devices. The most common fonts require about 50 Kbytesl
typeface. Software can simply add new fonts by writing the new
font descriptions to flash.
8-20
ADVANCED les
The 80960KB's bus performs well with 100-nsec DRAMs,
and taking advantage of nibble-mode DRAMs is quite easy
because the bus accommodates a four-word burst. The first word
takes up the J()()-nsec access time; however, subsequent words
only take 25 nsec. Two wait states on the first access allow the
DRAM row and column decoders to be set up. Subsequent accesses require only the cycling of CAS, which increments the internal column address counter and enables the output drivers.
The result: accesses with 2-0-0-0 wait states.
Ifan access occurs during a refresh sequence, the READY
generator simply inserts wait states until the refresh is completed.
The DRAM control generates the DRAM READY signal,
DRAMRDYH, which is then ORed into the 80960KB's READY
signal.
Eight-bit peripherals connect easily to the 80960KB (Figure
5). Although they are slow in comparison, wait states can be inserted to allow for the long access times. The 80960KB's byteload and byte-store instructions make it quite easy to write 8-bit
device drivers. A store byte to the 82510 serial port controller will
place the 8-bit value on the 80960KB's AD bus during the data
cycle. Data is then held on the bus until the READY Hsignal
returns, indicating the end of the access. The 82510 simply requires that the lower 8 bits of the data bus be tied directly to its
data pins. The 82510 uses the same read and write signals as the
rest ofthe system. The READY generation logic controls the
number of wait states inserted, and the decode logic generates the
<
~
DO
01
02
03
04
05
06
07
CS
A2
AO
Al
A2
~.ro
M
~
Controlling a 3D-page/min Print Engine
The print-engine interface (Figure 6) for the 80960KB-based
design interrnce box is also straightforward. It consists of several
logical blocks: MDLY (margin delay), PECTL (print-engine
control), PRNCR (print-engine control register), FIFO (64
RESET
10SEl#
WR#
~
82510 chip select, IOSELH.
The 80960KB initiates serial communication with the 82510.
When the 82510 receives data, an interrupt is generated. The
80960KB reads the data and places it into memory. To work with
other kinds of ports (e.g., Centronics), the port should be assigned a location in memory, the chip select and data lines supplied, and the appropriate number of wait states generated.
OB[O .31)
OB[0..31)
A[0..31)
Some POLs take advantage
of the 4-MWhetstone
floating-point capabilities
of the 80960KB, which
adds to performance.
A [0 ..31)
I,
RO
WR
elK/Xl
III ,.:=
.------
rNT
Rl/SClK
RXO
CIS
DUT2fX2
TXD
RTS
DTRITB
DSRlTA/DUro
DCDJIClKlOUT1
QIT]
rI
r-
OSA#
OTR#
RTS#
TXD
~
-
-==
-
lA
2A
2B
3A
3B
4A
4B
12V
~
1Y
2Y
P---
3Y~
p----
4Y
DTR
CIS
TXD#
RTS
I-lA~
DSR
3.3K
-~
R)fOIl'
RXD
1Y
crs.
2Y'
OSA#
3Y
--<
4Y
lRC
2Ar-2RC
3A
3RC
I-I--
t:;/
CONNECTOR OB9
GND
4~~
Figure 5: Using an 82510 serial controller, eight-bit
peripherals readily connect to the 80960KB. The
80960KB's byte-load and byte-store instructions make it
quite easy to write 8-bit device drivers.
8-21
ADVANCED les
To update flash, it must be erased, then written, a word at a
time. To accomplish this, one command erases the memory, then
another indicates that a data write will follow; data is then written. Since the flash is accessed in 4-byte-wide words, data can be
updated each write cycle. Flash memory adds the simplicity of
downloading new fonts to the convenience of nonvolatility at
power-down.
Because the controller board handles standard 300-dotiinch
8'h" x II" pages, a one-page bit-map requires no more than I
Mbyte of memory. With memory for two buffers, the 80960KB
can continue processing the next page while the print engine
works on the first. Font caching also places demands on memory,
requiring about 128 Kbytes. This amount allows the PDL interpreter to cache previously constructed fonts in the faster memory.
Font caching and bit-map buffering help improve perfurrnance by
reducing the delays caused by slow memory and the print-engine
interface.
As far as the DRAMs are concerned, a standard control
scheme is appropriate. A DRAM controller takes care of three
functions: RASiCAS cycling, address multiplexing, and refresh
timing. A 22VIOB PAL can perform the RASiCAS cycling for
single and mUltiple reads and writes. It also supplies the control
signals for the address multiplexer. The refresh logic, a counter
implemented in a PAL, signals the 22VIOB that a refresh cycle is
needed; at the end of the current access the control logic starts the
refresh sequence.
Main memory consists of 4 Mbytes ofl-Mbit x I-bit DRAMs.
Since no banking is required, only one set of control signals
needs to be generated. To provide 1 Mword of memory, 32 parts
are needed. Bytes or short words are accessed when the four
CAS signals are asserted by the byte enables, LBE# (0:3). One
CAS signal can be assigned to each byte in the 32-bit word.
RUN ONE CYCLE
NO
RUN ONE CYCLE
INCREMENT LAD (2:3)
DECREMENT LAD (0:1)
Figure 3: Burst buses need not complicate system design.
Two tasks are required to control a burst bus. One tracks
words remaining in the burst access; the second increments
the address for each word accessed in the burst.
EPROM
A(0..31)
A (0•.31)
AI~31J
EPRSEL#
EPASEL#
DB 10. 31J
RON
FLASH EPROM
AID.31J
WR#
I
~
FSHSEL#
DRAM
ORAM CONTROL
AI2 .. 22]
LBE#(D..3)
<
LBE#ID..3J
L.....-- ~ WR.
RAMSEL#
CLK2
CLK.25
RD.
RAMSELN
CLK2
CLK.2S
ORAMRDY#
DRAMRDY#
<
DBID..31J
WRN
RD.
FSHSELN
DRADRI~.91
RAS#
WE.
CAS#(0 .. 3)
DRADRID.9J
DBID.31J
RAS#
WE#
CAS#(D.. 3)
DB (0•.31)
Figure 4: The cost of fonts. A language like PostScript reo
quires 350 to 450 Kbytes; 512 Kbytes, plussome initializa·
tion code, is adequate for this design. Holding font data in
flash memory allows quick updates.
8-22
ADVANCED les
generates control signals for the address latches and data
transceivers. With the exception of an inverter for ALE, no glue
logic is needed for these signals.
The bus control block implements the chip-select logic and
generates the READY signal as well as controlling the
80960KB's burst bus. Bus logic increments the address during a
burst access and keeps track of the number of words in the current
burst access. It can be implemented in PALs.
Enough EPROM to hold a PDL is contained in the memory
block. The block also includes DRAM for page buffering and
font caching, as well as flash EPROM to hold the fonts; DRAM
control is another part of this logic. The I/O port logic block consists of an RS-232 serial port and an 82510 serial controller. The
port drives one DB9 serial connector.
The print engine interface is generic, specified at 30
pages/min; it is relatively straightforward to change the design to
fit a specific print engine. An 80960KB interrupt controls the
print-engine interface. The logic shown for the interrupt control
is a simple 32-bit, 64-word-deep I/O buffer, and could just as well
be a 16- or 8-bit printer port with a simple change of80960KB
code. A single-chip printer controller, such as the WD65CIO, can
also be designed into an 80960KB or 80960KA system as
memory-mapped I/o.
Currently, the 80960KB comes in a PGA package with 132
pins. Thirty-two address/data lines and six signals directly control the bus, resulting in a simple interface. Four byte enables indicate valid bytes in the 32-bit data word; interrupts are signaled
The 80960KB yields a
high-density, ultrafast
BITBlT routine at
59 Mbits/sec.
via four pins on the 80960KB. Several miscellaneous pins
(Figure 2) handle reset, bus master arbitration, bad s}stem access, and clocking. All of the control signals for the address/data
bus are open-drain signals and require external pull-ups.
Burst buses often complicate a system design. However, by
reducing burst accesses to a maximum of four words per access
and supplying the control signals necessary for burst control, the
80960KB holds down the amount of external control.
The Burst Bus
Two tasks are necessary to control a burst bus, as shown by the
flowchart in Figure 3. One keeps track of the words remaining in
the burst access; the second increments the address for each word
accessed in the burst. All that's needed for each of these tasks is a
single 2-bit counter. Load one counter from the size bits,
LAD(O:I), which indicate how many words are to be accessed,
10
,
lr
r
CPU
DB[0 .. 31)
A[2 .. 31)
DB[0.. 31)
A[2 ..31)
BUS CONTROL
:
AD[0 .. 3)
AD[0.. 3)
W'R#
ADS#
DEN#
BE#[0.. 3)
W'R#
ADS#
DEN#
BE#[0 ..3)
READV#
INTl
RESET
INT2
ClK2
READV#
A(2:3)
10SEl#
1
INTI
RD#
WR#
L
f-
f---<
FSHSEl#
DRAMRDV #
I--
RAMSEL#
PRINT ENGINE
DB[0.. 31)
WR#
RD# .
PRCREN#
SI
r-r---r---I-r----
lBE#[0 .. 3)
r-+
I
RRCREN#
SI
EPRSEl#
ClK
J
SClK
RESET
10SEl#
RD#
WR#
DB[0 .. 7)
A[2 ..4)
A[2:31)
RD#
WR#
~
INT2
~
CLK2
; - RESET
LBE#[0.. 3)
ClK
EPRSEl#
RAMSEl#
FSHSEl#
DRAMRDV#
ClK2
ClK.2S
CLOCK
MEMORV
ClK2
RESET
ClK
SClK
ClK 25
Figure 1: The print engine controller contains CPU, clock
generator and reset, bus control, memory, 110 ports, and
the print engine. The CPU and control logic consist of the
a0960KB, pull-ups for the open-drain signals, address
latches, and data transceivers. The a0960KB has a 2O-MHz
clock and 53.3-Mbyte/sec burst-bus data rates.
8-23
AR557
A Programmer's View of the 80960 Architecture
S. McGeady
Intel Corporation, Hillsboro, OR
2.2. Fundamental Data Types. Accesses to memory on the 960
can be 8, f6, 32.64,96, or 128 bits wide, representing the byte,
short, word, longword, tripleword, and quadword types, respectively.
ABSTRACT
Intel Corporation's new' 80960 processor
Integrates many archHectural features normally found
in RISC processors with others found in more traditional archHectures. The resuH is a processor providing high performance while presenting few difficulties
for either applications or compiler writers. This paper
discusses the programming model of the 960. including aspects of the instruction set and the register
architecture. Techniques for effective use of the 960
from both assembly language and high-level
languages are discussed, including the subroutine calling sequence designed for the architecture.
The byte, short, and word data types come in integer
(Signed) and ordinal varieties, The Id (load) and st (store)
operations for bytes and shorts come in each variety, where
integer loads Sign-extend the most significant bit of the source
memory location and ordinal loads do not. Word and wider loads
and stores merely copy the sign bit in the normal way, since no
sign-extension is required.
Byte ordering within words is little-endian, meaning that the
least significant bytes of a word are stored at the lowestnumbered address. This is like the DEC VAX' and Intel 386' processors, but unlike the IBM 360 and Motorola 68000 processors.
Future implementations will allow either little-endian or bigendian external memory references.
1. Introduction
All current and planned future implementations on the 960
support non-alig~ed memory a,ccesses, though memory access
is fastest when accesses are aligned to nalural boundaries, i.e.
words to 32-bit boundaries, doubles to 64-bit boundaries, and triples and quads to 128-bH boundaries.
Software engineers interested in the programming model of
a processor include application developers, who are primarily
interested in the high-level language (HLL) programming model;
operating system or kernel developers. who must concern themselves with both the assembly-language programming model and
the' fault, interrupt, and system-control aspects of the processor;
and compiler-writers, who concem themselves with code generation, optimization, and runtime system issues. Compiler and OS
developers attempt to insulate the application developer from as
, many of the details of the architecture as possible. This paper
will be of principle interest to those writing assembly-language
programs and compiler code-generations or run-time systems for
the 960, though a knowledge of the underlying architecture will
also be useful for those programming only in a high-level
language.
2.3. Register Set. The 960 has a thirty-two general registers
and four floating-point registers available to the compiler wrHer
(Fig. 1). The general registers are each 32 bits wide. Twentyeight of these registers have no predefined function, allowing the
compiler great freedom in allocating user procedure-local variables and temporaries into these registers. The remaining four of
the 960's 32 general registers are used by the call and rei
instructions lor stack-pointer, Irame-pointer. previous-frame
pointer, and return-instruction pointer.
The 960 general registers are divided into two sections: global registers, gO .. g15, and local registers, 1O..r15. The global
registers act like processor registers on any machine, and are
affected by instructions only when explicit)' used as operands.
The local registers are accessible to instructions in exactly the
same way as the global registers, but the call instruction provides the called procedure a new set of these registers that,
unlike Berkeley RISC [PatSeqB1]. do not overlap with the previous set. The rei instruction recovers the previous register set lor
the calling procedure,
2. The 960 Archltectuie
This section provides an overview oi the 960 architecture.
More detail may be found in [Myers88] and a reference manual is
available [PRM88].
2.1. Flat Address Space. An engineer developing code in Pascal, C, Ada, or most other Algol-like HLLs will see an extremely
simple and straightforward programming model, much like other
32-bit archHectures of long standing. The 960 provides a large (4
gigabyte) flat physical address space, with no segments or other
limHations on memory addressing. All addresses used by the
archHecture are 32 bHs wide. In implementations that include
memory management hardware (currently the 80960MC) standard virtual-memory paging support is supplied. and the virtual
address space for each process is also a full 32 bHs wide.
The 960 implements a special cache (64 registers in the
KA, KB. and MC implementations, up to 192 in a future implementation) for registers containing procedure-local variables,
allowing last procedure call and return. A call instruction causes
a new set of 16 local registers to be provided for the called procedure, while the previous procedure's registers are retained in
the register cache. Only when the cache is full are registers
• VAX is a trademark. of Digital Equipment Corporation. 386 is a trademark of Intel Corporation.
The 960 stack may begin at any address in memory, and
grows toward higher addresses.
Order Number: 270808-001
CH2686-4/89/0000/00Q4$Ol.OO © 1989 IEEE
8-24
I
I
CONTEHTSOF
GLOBAL ANO
flOAT NG·POINT
REGISTERS
PRfSERVED
ACIIOSS
PROCEOl"RE
.•
:~f,'~~~: ?g:~~~~~L V:E
l
GLOBAL
REGISTERS
I
I
BOUNDARIES
'
960 instructions are formed from four basic formats (Fig. 2):
REG (register) instructions, that form all basic computational
instructions, CTRL (control) instructions, including branches and
calls, MEM (memory) instructions, the load and store instructions, and COBR (compare-and-branch instructions), a highdensity instruction mentioned below.
I
~
FRAME POINTER IfP}
f, 0
J
FLOATING· POINT
AVAILABLE FOR GENERAL USE
L,P •
I'",,
, REGISTERS
---'
PRE .... IOUS FUME POINTER tPFPl
STACIC POINTER (S'I
RETURN INSTRUCTION POINTER (RIP)
II
,
I'
o ~\
I
l
I
!
NEWSETO~
LOCAL
lOCAL
REGISTERS
REGISTERS
A. .. LOC.A'''EO
REGISTERS r4 TtlRQUGH ,1 S
fOA.EA''''
AVAILABLE FOR GENERAL USE
PI:tOCEOUR[
IL - '
"
J
Fig 2. 960 Instruction FormalS.
REG instructions typically take three operands: two source
registers and a destination register. Either of the source
operands may alternatively be a literalin the range 0.. 31.
Fig 1. The 960 Register Set
ArithmetiC instructions come in ordinal (unsigned) and
integer (signed) varieties. These differ in treatment of the most
significant bit of the operands, and in the generation of integer
overflow faults. Languages such as C that do not define program
behaviour on integer overflow typically disable integer overflow
fault detection. Languages such as Ada that require integer over·
flow detection may enable it and do not require additional instructions to check for overflow.
spilled to memory, to locations previously allocated on the stack.
This reduces stack accesses due to register spilling during procedure calls to a minimum. Our research (as well as [Ditz82])
shows that most HLL programs tend to OSCillate. in a small range
of call depths. The register cacheing allows these procedures to
execute with far fewer accesses to externat memory. This
dramatically improves processor performance. especially with
moderate·speed memory systems typically found in embedded
systems.
The 960 instruction set atso allows access to an additionat
32 special function regi5ter5. In future implementations, these
registers will provide access to on·chip peripherals and other
special execution units.
2.5. fnteger Artthmetic Cant rots. The 960 allows detection of
overflow during integer arithmetic operations. The integer versions of the arithmetic instructions (addt, subl, mUll, dlvl, etc)
may trigger this fault, while the ordinal instructions (addo, subo,
mula, diva, etc) never .trigger the fault. The integer overflow trap
may be prevented by seHing the integer overflow mask in the
Arithmetic Controls register. An Integer Zero-Divide Fault is also
provided.
2.4. RISC Core Instruction Set. Other than the load (Id). store
(st). and a few special-purpose instructions, all instructions in the
960 operate on the general register set. The core inslructions of
the 960 are:
Arithmetic
and Logical
add
cmp
subtract
test
multiply
shift
divide
rotate
modulo
boolean-op
Control
branch
branch-link
call
return
2.6. Condttion Codes. Most 960 instruction do not set or use
fhe condiiion codes. In general, only the cmp instructions (and
the extended compare instructions discussed betow) set the con·
dition codes. The condition codes are conlained in Ihe arithmetic
controls registers (accessible via the special modac instruction),
and are encoded into three bits. Thus, eight masks provide the
standard conditions:
Data
Movement
move
load
store
CC
000
001
010
011
Branch, Test, and
Condition
never
src1 > src2
src1 == src2
src1 >= src2
Fault Conditions
Condition
CC
100 src1 < src2
101
src1 != src2
110 src1 <= src2
111
always
The conditional fault instructions also rely on these bits,
and the test instructions set their operand register to 1 H the
requested condition is true, and 0 if it is false.
Boolean Operations
and
notand
andnot
or
notor
ornot
xor
nor
xnor
not
nand
alterbit
setbit clrbit
notbit
The 960 differs from many processors in that the floatingpoint unit uses the same condition codes (and conditional branch
instructions) as the integer unit. The floating-point compare
instructions (cmpr, cmprl) set the condition bits in the manner
8-25
described above, except that the never condition indicates that
the operands of the compare are unordered, i.e., either operand
is an invalid floating-point number such as a NaN. The always
condition indicates the ordered.condition.
2.7. Extended Instructions. In addition to the core instructions,
the 960 implements a set of extended instructions to increase
code density, exploit fine-grain parallelism in the' microarchitecture, and provide needed functions for embedded applications
Extended Instructions
extract bits
compare-and-branch
modify bits
compare-and-increment
atomic add
compare-and-decrement
atomic modify
conditional-compare
2.9. IEEE-754 Floating-Point. The 960KB implementation
includes an on-chip lIoating-point unit. The FPU is fully IEEE
754-1985 compatible, and supports 32-bit (rea~, 54-bit (long
rea~, and SO-bit (extended rea~ precisions. The on-board FPU
supports NaN (Not-a-Number), Infinities, Signed Zero. and
Denormalized representations, and appropriate (maskable) faults
when operations generate NaNs, Infinities, or Denormalized.
The FPU also implements four additional BO-bit wide floatingpoint registers, though lIoating-point instructions may .also
operate on the general registers in groups of 1 (real), 2 (long
real), or 3 (extended)'.
scanbit
spanbit
synchronous move
synchronous load
Floating-Point Instructions
compare
add
binary log
natural log
subtract
copysign
multiply
square root classify
divide
sine
scale
move
cosine
round
modulo
tangent
truncate
remainder arctangent
exponent
The compare-and-branch and compare-and-increment or
-decrement instructions exist to improve instruction densily by
combining typically adjacent instructions when the delay Slot
between them cannot be filled. This brings the average code
density of 960 programs to within 15-25% of that of a VAX, compared to 40% or worse for other RISC processors JDitzS7J. In
addition, the conditional-compare instructions are used by the
960 Ada compiler for range checks, e.g:
cmpi
concmpi
faullne
rO,14
rO,30
Each 01 these instructions can operation on real, long real.
or extended preCision numbers. The classify instruction determines whether a value is a valid lIoating·point number. or a NaN.
Infinity, and/or denormalized, and the sign of the number. The
copyslgn operation can be used to provide an absolute value. A
full set of conversion instruction are provided that convert
between integer and floating-point formats, either using the
rounding-mode in effect or truncating.
# see if rO is in the range 14 .. 30
# fault if it is
The concmpl instruction acts as a no-op If the result of the previous cmp was "less than". This allows Simple range checks
without conditional branch instructions (and the concomitant
pipeline breaks). The atomic and synchronous instruclions are
important additions for multiprocessor systems.
The 960 FPU can be programmed to fault when it detects
de normalized operands, so full IEEE·754 denormalized-number
support can be implemented. If normalizing mode is on, denormalized numbers are normalized and the operation proceeds
without a fault.
2.S. Addressing Modes. The 960's load and store instructions
provide both the simple, high-pertormance addreSsing modes
(Fig. 3) normally found in RISC processors, and more complex
addressing modes fo.' improved code density and to beller exploit
fine-grained parallelism in the microarchitecture.
HLL Code
x =global;
x = 'p;
x = local;
x = s->mos;
x = p[i];
x = as[i]->mos;
Assembler Code
Id -9lobal,gO
Id (r6),gO
Id 80(fp),gO
Id 12(rB),gO
Id (r6)[r4'4].gO
Id 12(r9)[r4'16],gO
2.10. Floating-point Arithmetic Controls. If the HLL or its runtime library supports them, the 960 FPU can provide the following
(maskable) flags: lIoating underflow, overflow, zero-divide, and
inexact. The FPU may be set t6 round up, down, to zero, or to
nearest. and milY be set in normalizing mode, where denormalized numbers are valid. or non-normalizing mode, where denormalized operands cause a reserved-encoding fault.
Addressing Mode
12 or 32-bit address
register-indirect
register-indirect + offset
register-indirect + offset
Indexed indirect
indexed indirect + offset
The runtime system for C programs typically disables
integer overflow, floating underflow, overflow, and inexact faults.
and sets the FPU to·round-to-nearest and into normalizing mode.
The runtime system for Ada programs typically enables all faults
and translates them into NUMERIC_ERROR.
3. Subroutine Calling Sequence
Fig. 3. 950 Memory Addressing Modes'
No specific calling sequence is mandated or enforced by
the 960 architecture. While the call and ret instructions perform
pre-delined operations on the stack and Irame-pointers,
language designers are free to use the bal branch-and-link
instruction to implement,any desired subroutine linkage or calling
sequence. A sophisticated compiler might dispense with a standard calling sequence altogether, tuning each call to the needs of
the calling and called procedures.
Sophisticaled addressing modes on the 960 not only
improve code density, but they allow the implementation to compute tM effective address of the instruction in parallel with the
execution of subsequent instructions. In addition, in each of the.
above examples, the instruction could have been Idl (load long),
Idt (load triple), or Idq (load quad), to burst 2, ~, or 4 four words
from memory. The instruction 'Idq 12(r9)[r4'16]' would take 6to
11 inslructions to implement on most other RISC processors.
However, Intel has defined a common calling sequence for
its C and Ada compilers for the 960. This allows implementation
of less sophisticated compilers. assemblers, and debugging
tools. Nevertheless, the calling sequence was designed to place
an absolute minimum overhead on simple. commonly-called procedures with few paramete(s, and only slightly more overhead on
rarely-used variable-argument-list procedures and procedures
1 The lable assumes the follOWing data declarabons.
Int global, Int array[101.
100(1
I
=
Inllocal, Int i, In!·p &array,
slrucl (
a,b,c,d, shan
char
float
g.
Int
B,f,
mos,
2 The load and store Irlpleword functions are provided lor feadlng and stonng
extended-precIsion "aatlng-polnl values to and from memory
I' .•• [5).
8-26
across the call (the called routine must not modily them, or must
save and restore them if they are to be used)_ Register g12 is
always preserved across calls, A globally-optimizing compiler for
the 960 could use these registers to hold global constants and
pointers to global data structures,
with large numbers 01 parameters. Intel's 960 software support
tools, as well as those supplied lor the 960 by most third parties,
expect and support Ihis calling sequence.
Reg
gO
g1
g2
g3
g4
gS
g6
g7
g8
g9
g10
g11
g12
g13
g14
Ip
Primary Use
parameter 0
parameler 1
Secondary Use
return word 0
return word 1
return word 2
return word 3
P?
If more than lour words ollunction return value is required,
(as in a C function returning a structure) the calling routine must
supply a pointer to an area (presumably on the stack) in which
the return value is written, II a structure return is needed, a
pointer is supplied in register g13, otherwise that register may be
used as a temporary,
Imp
This linkage convention allows very fast calls with little or
no memory traffic to both leal and non-leaf procedures. A typical
non-leaf procedure prologue is:
Imp
parameter 6
parameter 7
Imp
unasslgnod
parameler8
parameter 9
parameter 10
parameter 11
Imp
unassigned
unassigned
unassigned
unassigned
structure return ptr
argument blk ptr
Irame pointer
P
P
P
P
P
_faa:
The lirst instruction (Ida - load effective address) adjusts the
stack pointer to make room for local (non-register) variables such
as arrays and structures. The second instruction copies the
incoming lour parameters from global registers gO .. g3 to local
registers r4 ..r7. Here they will be preserved by the register
cache across calls within the procedure. Any procedure can
return without adjusting the stack or incurring other overhead by
using the ret inslruction.
leal return addr
P - preserved across calls
p' - preS8fV'Bd If nor usod as parameter
Fig, 4, Global Register Usage Conventions
3,3, Support for Argument Blocks, In our examination of many
of C and Ada programs, we discovered that over 98% 01 all procedures were called with 6 or lewer parameters [Weic84]
([Pat8S] also reports this). However, if more than eight words of
parameters are required, four additional words may be placed in
g8 .. g11, and their vatues, like g4.. g7 are indeterminate upon
return of the called procedure. II more than 12 words of parameters are required, register g14 is used to point to an argument
block on the calling procedure'S stack. Registers gO .. g11 contain
the first twelve words of parameters, and the argument block
contains any remaining parameters, following an empty area 01
twelve words into which the called procedure may copy the
parameters passed in the registers. If no argument block is allocated lor a procedure, g14 must be set to zero. In practice, procedures with more than 12 words 01 parameters are so rare that
g14 is set in a program's initialization code and seldom changed.
Existing'compilers typically use the register as a constant zero.
3,1, Parameters In Global Registers, The global registers
gO .. g14 are used lor passing parameters and olher values
between procedures As shown in Fig. 4, registers gO through
g7 are used lor the lirst eight words 01 parameters to a procedure. Values are placed into increasing-numbered registers
left-to-nght, and are aligned within the register set according to
their size, possibly leaving holes A parameter shorter than one
word is placed in a single register, two-woro parameters (e.g.
double-precision Iloats) are placed in an even-numbered register
and the following register, and three and four-word parameters
(e g. extended-precision floats) are placed in gO, g4, or g8.
Thus, Instructions may use parameters directly Irom their registers withoul extracting and aligning them.
Fig 5 shows a C code fragment, and the calling
procedure's interface code_
3,4, Variable Length Argument Lists, The C programming
language allows procedures to be called with a variable number
of arguments. In versions of C before the ANSI X3J11 standardization effort, the calling procedure typically did not know whether
a called procedure was a variable-argument-list (varargs). procedure. The 960 calling sequence supports this model, allowing
properly-written C programs to be ported without change. The
calling procedure lollows the rules outlined above, placing
parameters in registers until they are eXhausted, and then allocating an argument block. The called procedure, however, does
not know how many arguments where passed to it and ot what
type these arguments might be. We rejected the notion of providing an argument count to every procedure, as that would
involve undue overhead, and would not solve the type problem.
Int a, b[10];.
a = loo(a, 1, Y, &b[O]);
mov
Idconst
Idconst
Ida
call
mov
r3,gO
1,g1
120,g2
Ox40(fp),g3
_faa
gO,r3
Ida
96(sp),sp
# adjust stack
gO,r4
# save parameters
movq
r remainder of procedure "
ret
# local "a"
#1
#'x'
# base ol"b"
Fig, 5, Standard Subroutine Linkage Example
Register g14 inlorms the called procedure whether the
caller allocated an argument block. II it did, the varargs procedure can simply copy gO .. g11 to the stack with three stq (store
quad-word) instructions, leaving user code to increment through
them. If g14 is set to zero, the caller did not allocate an argument block, and the varargs routine allocates one for itsell and
copies the parameters into it in the same way. The compiler generates special code in the prologue to varargs routines to do this:
3,2, Return Values In Global Registers, The calling procedure
receives any return value shorter than lour words in gO .. g3 when
the called routine returns, allowing integral values, single, double,
or extended-precision floating-point values, or small structures to
be returned without wntlng to memory. The calling procedure
must assume that the values in gO .. g7 are losl across a procedure call (except lor those that contain the lunction return
value, rt any). though global registers g8 .. g11 are preserved
8-27
-printl:
'w123:
3.7. Trace Controls and Debugging
cmpobne
g14,O,.W123
Idconst
64,r15
addo
sp,r15,sp
Ida
32(sp),g14
slq
g8,32(fp)
sfq
g4,16(g14)
gO,(g14)
stq
must save g8 .. g11 separately in case .,
they were used as parameters .,
stq
g8,48(g14)
Many prccessors are implemented for workstations or enduser compuler systems with native operaling systems and programming environments. The 960 adds to its architecture a standard set of debugging features that allow simple debugging
without a native operating system.
r
r
r
3.8. Trace Controls The 960 implements a series of trace controls (Fig. 7) that allow the user to implement a full runtime
debugger as part of a simple monitor implementing the trace fault
handler.
remainder of procedure·'
. The overhead imposed on varargs routines is minor, and
linkage to the preponderance of procedures consists only of a
few mov instructions and a call.
3.5. Branch·and·Llnk Optimizations. Procedures that do not
require a stack frame or a set of local registers may be optimized
to avoid the allocation of the frame or use of the register cache.
Such procedures typically call no other procedures and are called
leaf procedures, since they reside at the "leaves' of the call-tree.
Entering leaf procedures wHhout creating a new frame makes
beller use of the 960 register cache and can improve perfor·
mance in call-intensive programs.
The 960 archHecture provides the bal instruction, which
branches to the operand address, leaving the address of the subsequent instruction (the return instruction pointer) in a named
register. Such a subroutine would return by branching to the
address contained in this register.
The 960 compilers generate the callI (caIVjump) pseudo-op
in place of the standard call instruction, which allows the linker to
determine if separately-compiled modules contain leafprocedures and promote the call instruction at the call-site to a
bal instruction. Fig. 6 shows the entry to a leaf procedure that
can also be called in the standard way.
III
.
'~!'!'!!{E(/L,,~~~"~:
~
I
L..:=.u."'CHnACl""CO(
OUT1tA(EMODI
_nUl .. TltA(l MODI
---'lunUIN
i'
TUCI MODE
--.--su,nVISOIlTA.AUMOOI
UIA"I'OI,.TTU,UMOO(
1:1~~~:~:-;:~I",:"INT
l~~~~~~~~~~UTVINr
'llunUIN
EV,PoI'
....rliAU
crEV(NT
SU""VlSOIUACEIVIt4r
•• L.... 'OIHT'... UEII(NT
Flg.7. 960 Debug Trace Controls
The call and return traces allow monitoring of procedure
entry and exH, while branch tracing may be used to monitor
branch-and-link procedure entries and other branches. The prereturn trace is useful for capturing cOhtrol immediately before the
return from a procedure in order to examine its stack trame. The
instruction trace mode faults on the execution of every instruction, allowing single-stepping. Monitors provided by Intel support
each of these modes, offering single-stepping, dynamiC instruction trace with disassembly. Current implementations of the 960
also include two instruction address breakpoint registers that
allow the setting of breakpoints in ROM.
.Ieafproc
rell:
"l
Ida
rell,g14
# call entry
mov g14,g13 # bal entry
mov O,g14
r remainder of procedure·'
bx
(g13)
ret
3.9. System Programming
Implementors of operating systems must also concern
themselves with the behaviour Of interrupts and faults.
3.10. Interrupts. The 960 incorporates a 32-priority, 248-vector
interrupt controller on-chip, eliminating the need for off-chip circuitry to handle interrupts. The interrupt table, the location of which
is defined at power-up or reinitialization, cOntains the addresses
of the handlers for various interrupts. Also, the first 36 bytes of
the interrupt table record the status of all pending interrupts: and
all priorities that have pending interrupts.
Fig. 6 Leaf Procedure Definition
3.6. Linkage Conventions for other Languages. The 960 calling convention can be used for C, Ada, Pascal, Fortran, and
most other HLLs. Languages with more complex scoping rules
than C are sometimes required to pass a static link as an invisible first (or last) parameter to procedures in enclQsed scopes that
reterence variables in an enclosing scope. The 960 Ada compiler recognizes these cases and passes the static link only to
those procedures that require H.
Fortran compilers that implement copy-in/copy-out parameter passing (as opposed to the more common pass-by-reference
model) have no problem with SUBROUTINE calls, but FUNCTION calls will require eHher reference parameters or use of the
structure' return facility. In Ada, functions do not have Inlout
parameters, so this is not an issue. Handling unconstrained
results in Ada is not contemplated by this linkage convention, but
is managed by the 960 Ada compiler in a way that does not
violate the convention.
Languages that need not use a standard control stack, or
wish to implement a dramatically different calling convention may
use branch-and-link exclusively, with a vestigial runtime stack for
interrupt and fault handling.
When an interrupt is received, if it is of a higher priority than
other executing or pending interrupts (if any), the processor
switches to an independent interrupt stack, saves the arithmelic
controls register (containing the condition codes), the process
controls register (containing the previously current priority), and
the interrupt procedure is called as though from a call instruction,
using the handler address in the interrupt table. Since the call
instruction automatically allocates a new set of local registers
from the register cache, the interrupted procedure's local variables need not be explicitly saved. Other than the need to save
the global registers if they are used, the interrupt service routine
is like any other routine, and return from interrupt is effected with
the standard ret instruction. The state of the processor, including
the previously active priority, is restored when the interrupt
returns.
Operating system routines may post software-generated
interrupts by using the atomic modify (atmod) instruction to
8-28
cnange values In Ihe pendlng-inlerrupls field 01 Ihe inlerrupt
table.
Id
muli
addo
subo
3.11. Faults. When the processor detects an exceptional condition (including "planned" exceptional conditions like trace/debug
faults), a fault is raised. Faults are categorized into trace laults,
Invalid operation faults, aflthmetic faults, floating-point laults, bad
(memory) access laults, and several processor consistency
faults. Most faults have one or more sub-t,pes thai are indicated
when the lault is signaled.
Ox400(rO),gO
g4,g5,g6
rO,16,rO
gO,rO,r1
# these
# execute
# concurrently
# waits for load
Ftg. B. CPU/Bus Parallelism
Because the 960 hardware detects resource conflicts,
software WIll always operate as expected without the insertion of
null operations, and without software tools to detect and remove
these conflicts.
A system-wide fault table contains addresses of fault
handlers lor each type of lault. As with inlerrupts, a tault handler
IS entered as though it had been calted by Ihe normal call
Instruction Unlike interrupts, however, lault handlers execute on
the user stack, rather than on a separale inlerrupt stack, allowing
the fault handler simple access to process state information
there When a fault occurs, a fault record is saved in Ihe fault
handle(s stack frame, recording the type and subtype of Ihe
laull the address 01 the faulting Instruction, the saved arithmetic
and process controls, and sufficient data to restart the instruction
(a resumption record).
Future implementations of the 960 will exploit even more
parallelism - a memory operation, an integer operation, and a
branch may be dIspatched simultaneously and executed in parallel. Careful balancing of memory operations (including tda
instructions, that can pertorm a limited set of arithmetic operations) with integer operations can enhance the pertormance of
future implementations, allowing average 2 instrucfion per clock
execution rates from on-chip instruction cache.
5. Conclusion
For faults that are fatal errors, a fault handler need merely
modify the return Instruction pointer In the previous stack frame
(that of the faulting procedure) and return. II it is desired that the
operands of tM faulting Instruction be modified and the instruction re-executed, the handler must examine the faulting instruction, determine the precise cause of the fault, and modify the
operands accordingly.
3.12, PreCise, Imprecise, and parallet Faults Because the 960
architecture altows instructions to execute in parallel, multiple
faults can occur simultaneously, possibly one or more cycles
after the dispatch of the faulting instruction. II this behaviour
must be aVOided, the 960 provides the NIF (No Imprecise Faults)
flag, that prevents parallel execution of instructions that might
generate impreCise faults. However, under normal Clfcumstances, if multiple faults occur simultaneously, the 960
writes a record for each fault into the stack frame, and calls a
sper.ial parallel fault handler (fault type 0). The parallel fault
handler may then dispatch individual fault handlers as appropnate.
The 960 processor was designed with more than one
implementatIon in mind. Many features of the 960 are present to
support implementations that provide fine-grained parallelism at
the instruction level, allowing aggregate native instruction rates in
excess of twice the processor clock rate. At the same time, the
960 provides an architecture that is easy to.learn and to use, and
that does not require sophisticated software tools to exploit. The
960 combines the practical aspects of RISC techniques
developed in recent years with more traditional mainframe techniques such as register scoreboarding and parallel instruction
execution. The calling sequence designed for the 960 allows
enough flexibility to make fast calls to simple non-leaf and leaf
procedures, and yet does not cause undue complication in
development tools. ProviSIons have been made to. support
sophisticated optimizing compilers and other tools as that technology becomes more mature.
6. References
For languages such as Ada that require that all potential
faults be signaled at certain places in a procedure (i.e. when an
exception handler is being changed), the syncf (synchronize
faults) Instruction is provided ThiS instruction stalls until all
parallel instruction execution units have completed and reported
any faulls. The 960 Ada compiler emits this instruction at the end
of an exception frame.
[Ditz82]
D. Ditzel & H. McLellan, "The C Machine Stack
Cache: RegIster Allocation for Free", Proceedings
Symposium on Architectural Support for Programming Languages and Operaling Systems, March
1982.
[Ditz87]
D. Ditzel & H. McLellan, "Design Tradeoffs to Support
the C Programming Language in the CRISP
Microprocessor", Proceedings 2nd International
Conference on Architectural Support for Programming Languages and Operating Systems, October
1987.
4. Parallel Instruction Optimizations
The 960, like other modern processors, supports pipelined
Instruction execution. This allows decode and dispatch operations for current instructions to be overlapped with execution of
previous instructions. However, the 960 has a fully interlocked
[IEEE754] IEEE, ANSI/IEEE Std. 754-1985: IEEE Standard for
Btnary Floallng-Polnt Arithmetic", 1985.
pipeline, ensuring object-code compatibility between current and
future implementations. Unlike many other RISC processor~,
there is no need to insert null operations before or after certain
operations such as loads or branches. The 960 also implements
register scoreboarding, ensuring that adjacent Instructions that
might be executed in parallel or overlapped do not attempt to use
a Single resource at the same time or out of order.
[Myers88] G. Myers & D. Budde, The 60960 Microprocessor
Architecture, WIley Interscience, New York, NY,
1988.
[PRM960] 60960KB Programmer's Reference Manuat, Intel
Corporation, Santa Clara, CA, 1988.
[Patl85]
Because of the instruction pipeline careful ordering of
instructions can improve code pertormance. The result of a Id
Instruction may not be avaIlable for several cycles after the
instructIon is issued, depending on the speed of the memory system. By scoreboarding the destination register of the load, the
960 is able to safely continue to execute instructIons follOWing the
load, effectIvely overlapping· these instructions with the data fetch
(FIg. 8)
D. Patlerson, "Reduced Instruction Set Computers,"
CACM, v28n1, January 1985.
[PatSeq81] D. Patterson & C. Sequin, "RISC I: A Reduced
Instruction Set VLSI Computer." Proceedings 8th
Internafional Symposium on Computer Architecture,
May 1981.
[Weic84]
8-29
R. Weicker, "Dhrystone: A Synthetic Systems Programming Benchmark", CACM, v27n10, October
1984.
General Microcontroller
Application Notes
9
intJ
APPLICATION
NOTE
AP-125
February 1982
Designing Microcontroller
Systems for Electrically
Noisy Environments
TOM WILLIAMSON
MCO APPLICATIONS ENGINEER
© Intel Corporation, 1989
Order Number: 210313-002
9-1
intJ
AP-125
Digital circuits are often thought of as being immune to
noise problems, but really they're not. Noises in digital
systems produce software upsets: program jumps to apparently random locations in memory. Noise-induced
glitches in the signal lines can cause such problems, but
the supply voltage is more sensitive to glitches than the
signal lines.
Types and Sources of Electrical Noise
The name given to electrical noises other than those
that are inherent in the circuit components (such as
thermal noise) is EMI: electromagnetic interference.
Motors, power switches, fluorescent lights, electrostatic
discharges,' etc., are sources of EMI. There is a veritable
alphabet soup of EMI types, and these are briefly described below.
Severe noise conditions, those involving electrostatic
discharges, or as found in automotive environments,
can do permanent damage to the hardware: Electrostatic discharges can blow a crater in the silicon. In the
,automotive environment, in ordinary operation, the
"12V" power line can shown + and -400V transients.
SUPPLY LINE TRANSIENTS
Anything that switches heavy current loads onto or off
of AC or DC power lines will cause large transients in
these power lines. Switching an electric typewriter on
or off, for example, can put a lOOOV spike onto the AC
power lines.
This Application Note describes some electrical noises
and noise environments. Design considerations, along
the lines of PCB layout, power supply distribution and
decoupling, and shielding and grounding techniques,
that may help minimize noise susceptibility are reviewed. Special attention is given to the automotive and
ESD environments.
The basic mechanism behind supply li"e transients is
shown in Figure 1. The battery represents any power
source, AC or DC. The coils represent the line inductance between the power source and the switchable
loads Rl and R2. Ifboth loads are drawing current, the
line current flowing through the line inductance, establishes a magnetic field of some value. Then, when one
of the loads is switched off, the field due to that component of the line current collapses, generating transient
voltages, v = L(di/dt), which try to maintain the current at its original level. That's called an "inductive
kick." Because of contact bounce, transients are generated whether the switch is being opened or closed, but
they're worse when the switch is being opened.
Symptoms of Noise Problems
Noise problems are not usually encountered during the
development phase of a microcontroller system. This is
because benches rarely simulate the system's intended
environment. Noise problems tend not to show up until
the system is installed and operating in its intended en, vironment. Then, after a few minutes or hours of normal operation the system finds itself someplace out in
left field. Inputs are ignored and outputs are gibberish.
The system may respond to a reset, or it may have to be
turned off physically and then back on again, at which
point it commences operating as though nothing had
happened. There may be an obvious cause, such as an
electrostatic discharge from somebody's finger to a keyboard or the upset occurs every time a copier machine
is turned on or off. Or there may be no obvious cause,
and nothing the operator can do will make the upset
repeat itself. But a few minutes, or a few hours, or a few
days later it happens again.
An inductive kick of one type or another is involved in
most line transients, including those found in the automotive environment. Other mechanisms for line transients exist, involving noise pickup on the lines. The
noise voltages are then conducted to a susceptible circuit right along with the power.
EMP AND RFI
Anything that produces arcs or sparks will radiate electromagnetic pulses (EMP) or radio-frequency interference (RFI).
One symptom of electrical noise problems is random-'
ness, both in the occurrence of the problem and in what
,the system does in its failure. All operational upsets
that occur at seemingly random intervals are not necessarily caused by noise in the system. Marginal VCC,
inadequate decoupling, rarely encountered software
conditions, or timing coincidences can produce upsets
that seem to occur randomly. On the other hand, some
noise sources can produce upsets downright periodically. Nevertheless, the more difficult it is to characterize
an upset as to cause and effect, the more likely it is to
be a noise problem.
v R1
R2
210313-1
Figure 1. Supply Line Transients
9-2
AP-125
the classical "ground loop." By extension, the term is
used to refer to any unwanted (and often unexpected)
'
currents in a ground line.
Spark discharges have probably caused more software
upsets in digital equipment than any other single noise
source. The upsetting mechanism is the EMP produced
by the spark. The EMP induces transients in the circuit, which are what actually cause the upset.
"Radiated" and "Conducted" Noise
Arcs and sparks occur in automotive ignition systems,
electric motors, switches, static discharges, etc. Electric
motors that have commutator bars produce an arc as
the brushes pass from one bar to the next. DC motors
and the "universal" (AC/DC) motors that are used to
power hand tools are the kinds that have commutator
bars. In switches, the same inductive kick that puts
transients on the supply lines will cause an opening or
closing switch to throw a spark.
Radiated noise is noise that arrives at the victim circuit
in the form of electromagnetic radiation, such as EMP
and RFI. It causes trouble by inducing extraneous voltages in the circuit. Conducted noise is noise that arrives
at the victim circuit already in the form of an extraneous voltage, typically via the AC or DC power lines.
One defends against radiated noise by care in designing
layouts and the use of effective shielding techniques.
One defends against conducted noise with filters and
ESD
Electrostatic discharge (ESD) is the spark that occurs
when a person picks up a static charge from walking
across a carpet, and then discharges it into a keyboard,
or whatever else can be touched. Walking across a carpet in a dry climate, a person can accumulate a static
voltage of 35kV. The current pulse from an electrostatic discharge has an extremely fast risetime - typically,
4A/ns. Figure 2 shows ESD waveforms that have been
observed by some investigators of ESD phenomena.
80
- - EXPERIMENTAL
- - - - CALCULATED
60
Ul
"-
~
z
;:: 40
zw
a:
a:
It is enlightening to calculate the L(dildt) voltage required to drive an ESD current pulse through a couple
of inches of straight wire. Two inches of straight wire
has about 50 nH of inductance. That's not very much,
but using 50 nH for L and 4A/ns for dildt gives an
L(dildt) drop of about 200V. Recent observations by
W.M. King suggest even faster risetimes (Figure 2b)
and the occurrence of multiple discharges during a single discharge event.
::l
U
20
o
10
20
30
40
50
60
70
80
90
100 110 120
TIME IN NANOSECONDS
210313-2
(a)
Obviously, ESD-sensitivity needs to be considered in
the design of equipment that is going to be subjected to
it, such as office equipment.
GROUND NOISE
Vert: 5 AmpS/Div
Time: 5 nSec:/Div
Currents in ground lines are another source of noise.
These can be 60 Hz currents from the power lines, or
RF hash, or crosstalk from other signals that are sharing this particular wire as a signal return line. Noise in
the ground lines is often referred to as a "ground loop"
problem. The basic concept of the ground loop is
shown in Figure 3. The problem is that true
earth-ground is not really at the same potential in all
locations. If the two ends of a wire are earth-grounded,
at different locations, the voltage difference between the
two "ground" points can drive significant currents (several amperes) through the wire. Consider the wire to be
part of a loop which contains, in addition to the wire, a
voltage source that represents the difference in potential between the two ground points, and you have
Displayed:
Ip: 40 Amps
Tr.1 nSec
500V
210313-3
(b)
Figure 2. Waveforms of Electrostatic
Discharge Currents From a
Hand-Held Metallic Object
9-3
inter
AP-125
suppressors, although layouts and grounding techniques are important here, too.
of the program to some random location in memory.
The person who has to iron out such problems is tempted to say the program counter went crazy. There is
usually no damage to the hardware, and normal operation can resume as soon as the EMI has passed or the
source is de-activated. Resuming normal operation usually requires manual or automatic reset, and possibly
re-entering of lost information.
Simulating the Environment
Addressing noise problems after the design of a system
has been completed is an expensive proposition. The ill
will generated by failures in the field is not cheap either.
It's cheaper in the long run to invest a little time and
money in learning about noise and noise simulation
equipment, so that controlled tests can be made on the
bench as the design is developing.
Electrostatic discharges from operating personnel can
cause not only software upsets, but also permanent
("hard") damage to the system. For this to happen the
system doesn't even have to be in operation. Sometimes
the permanent damage is latent, meaning the initial
damage 'may be marginal and require further aggravation through operating stress and time before permanent failure takes place. Sometimes too the damage is
hidden.
Simulating the intended noise environment is a twostep process: First you have to recognize what the noise
environment is, that is, you have to know what kinds of
electrical noises are present, and which of them are going to cause trouble. Don't ignore this first step, because it's important. If you invest in an induction coil
spark generator just because your application is automotive, you'll be straining at the gnat and swallowing
the camel. Spark plug noise is the least of your worries
in that environment.
One ESD-related failure mechanism that has been identified has to do with the bias voltage on the substrate of
the chip. On some CPU chips the substrate is held at
- 2.5V by a phase-shift oscillator working into a capacitor/diode clamping circuit. This is called a "charge
pump" in chip-design circles. If the substrate wanders
too far in either direction, program read errors are noted. Some designs have been known to allow electrostatic discharge currents to flow directly into port pins of
an 8048. The resulting damage to the oxide causes an
increase in leakage current, which loads down the
charge pump, reducing the substrate voltage to a marginal or unacceptable level. The system is then unreliable or completely inoperative until the CPU chip is
replaced. But if the CPU chip was subjected to a discharge spark once, it will eventually happen again.
The second step is to generate the electrical noise in a
controlled manner. This is usually more difficult than
first imagined; one first imagines the simulation in
terms of a waveform generator and a few spare parts,
and then finds that a wideband power amplifier with a
200V dynamic range is also required. A good source of
information on who supplies what noise-simulating
equipment is the 1981 "ITEM" Directory and Design
Guide (Reference 6).
Types of Failures and Failure
Mechanisms
A major problem that EMI can cause in digital systems
is intermittent operational malfunction. These software
upsets occur when the system is in operation at the time
an EMI source is activated, and are usually characterized by a loss of information or a jump in the execution
I
Chips that have a grounded substrate, such as the 8748,
can sometimes sustain some oxide damage without actually becoming inoperative. In this case the damage is
present, and the increased leakage current is noted;
however, since the substrate voltage retains its design
value, the damage is largely hidden.
ATB
-GROUND LOOP-
'..POTENTIAL DIFFERENCE
BETWEEN A AND B
210313-4
Figure 3_ What a Ground Loop Is
9-4
infef
AP-125
It must therefore be recognized that connecting port
to minimize the generation of noise voltages in the circuit. These methods involve grounding, shielding, and
wiring techniques that are directed toward the mechanisms by which noise voltages are generated in the circuit. We'll also discuss methods of decoupling. Then
we'll look at some schemes for making a graceful recovery from upsets that occur in spite of preventive measures. Lastly, we'll take another look at two special
problem areas: electrostatic discharges and the automotive environment.
pins unprotected to a keyboard or to anything else that
is subject to electrostatic discharges, makes an extremely dangerous configuration. It doesn't make any difference what CPU chip is being used, or who makes it. If
it connects unprotected to a keyboard, it will eventually
be destroyed. Designing for an ESD-environment will
be discussed further on.
We might note here that MOS chips are not the only
components that are susceptible to permanent ESD
damage. Bipolar and linear chips can also be damaged
in this way. PN junctions are subject to a hard failure
mechanism called thermal secondary breakdown, in
which a current spike, such as from an electrostatic
discharge, causes microscopically localized spots in the
junction to approach melt temperatures. Low power
TTL chips are subject to this type of damage, as are
op-amps. Op-amps, in addition, often carryon-chip
MOS capacitors which are -directly across an external
pin combination, and these are susceptible to dielectric
breakdown.
Current Loops
The first thing most people learn about electricity is
that current won't flow unless it can flow in a closed
loop. This simple fact is sometimes temporarily forgotten by the overworked engineer who has spent the past
several years mastering the intricacies of the DO loop,
the timing loop, the feedback loop, and maybe even the
ground loop. The simple current loop probably owes its
apparent demise to the invention of the ground symbol.
By a stroke of the pen one avoids having to draw the
return paths of most of the current loops in the circuit.
Then "ground" turns into an infinite current sink, so
that any current that flows into it is gone and forgotten.
Forgotten it may be, but it's not gone. It must return to
its source, so that its path will by all the laws of nature
form a closed loop.
We return now to the subject of software upsets. Noise
transients can upset the chip through any pin, even an
output pin, because every pin on the chip connects to
the substrate through a pn junction. However, the most
vulnerable pin is probably the VCC line, since it has
direct access to all parts of the chip: every register, gate,
flip-flop and buffer.
The physical geometry of a given current loop is the
key to why it generates EMI, why it's susceptible to
EMI, and,how to shield it. Specifically, it's the area of
the loop that matters.
The menu of possible upset mechanisms is quite
lengthy. A transient on the substrate at the wrong time
will generally cause a program read error. A false level
at a control input can cause an extraneous or misdirected opcode fetch. A disturbance on the supply line can
flip a bit in the program counter or instruction register.
A short interruption or reversal of polarity on the supply line can actually turn the processor off, but not long
enough for the power-up reset capacitor to discharge.
Thus when the transient ends, the chip starts up again
without a reset.
Any flow of current generates a magnetic field whose
intensity varies inversely to the distance from the wire
that carries the current. Two parallel wires conducting
currents + I and - I (as in signal feed and return lines)
would generate a nonzero magnetic field near the wires,
where the distance from a given point to one wire is
noticeably different from the distance to the other wire,
but farther away (relative to the wire spacing), where
the distances from a given point to either wire are about
the same, the fields from both wires tend to cancel out.
Thus, maintaining proximity between feed and return
paths is an important way to minimize their interference with other signals. The way to maintain their
proximity is essentially to minimize their loop area.
And, because the mutual inductance .from current loop
A to current loop B is the same as the mutual inductance from current loop B to current loop A, a circuit
that doesn't radiate interference doesn't receive it either.
A common failure mode is for the processor to lock
itself into a tight loop .. Here it may be executing the
data in a table, or the program counter may have
jumped a notch, so that the processor is now executing
operands instead of opcodes, or it may be trying to
fetch opcodes from a nonexistent external program
memory.
It should be emphasized that mechanisms for upsets
have to do with the arrival of noise-induced transients
at the pins of the chips, rather than with the generation
of noise pulses within the chip itself, that is, it's not the
chip that is picking up noise, it's the circuit.
Thus, from the standpoint of reducing both generation
of EMI and susceptibility to EMI, the hard rule is to
keep loop areas small. To say that loop areas should be
minimized is the same as saying the circuit inductance
The Game Plan
Prevention is usually cheaper than suppression, so first
we'll consider some preventive methods that might help
9-5
inter
AP-125
Another application of the Faraday shield is in the electrostatically shielded transformer. Here, a conducting
foil is laid between the primary and secondary coils so
as to intercept the capacitive coupling between them. If
a system is being upset by AC line transients, this type
of transformer may provide the fix. To be effective in
this application, the shield must be connected to the
greenwire ground.
should be minimized. Inductance is by definition the
constant of proportionality between current and the
magnetic field it produces: = LI. Holding the feed
and return wires close together so as to promote field
cancellation can be described either as minimizing the
loop area or as minimizing L. It's the same thing.
Shielding
SHIELDING AGAINST INDUCTIVE COUPLING
There are three basic kinds of shields: shielding against
capacitive coupling, shielding against inductive coupling, and RF shielding. Capacitive coupling is electric
field coupling, so shielding against it amounts to shielding against electric fields. As will be seen, this is relatively easy. Inductive coupling is magnetic field coupling, so shielding against it is shielding against magnetic fields. This is a little more difficult. Strangely
enough, this type of shielding does not in general involve the use of magnetic materials. RF shielding, the
classical "metallic barrier" against all sorts of electromagnetic fields, is what most people picture when they
think about shielding. Its effectiveness depends partly
on the selection of the shielding material, but mostly, as
it turns out, on the treatment of its seams and the geometry of its openings.
With inductive coupling, the physical mechanism involved is a magnetic flux density B from some external
interference source that links with a current loop in the
victim circuit, and generates a voltage in the loop in
accordance with Lenz's law: v = - NA(dB/dt), where
in this case N = 1 and A is the area of the current loop
in the victim circuit.
There are two aspects to defending a circuit against
inductive pickup. One aspect is to try to minimize the
offensive fields at their source. This is done by minimizing the area of the current loop at the source so as to
promote field cancellation, as described in the section
on current loops. The other aspect is to minimize the
inductive pickup in the victim circuit by minimizing the
area of that current loop, since, from Lenz's law, the
induced voltage is proportional to this area. So the two
aspects really involve the same corrective action: minimize the areas of the current loops. In other words,
minimizing the offensiveness of a circuit inherently
minimizes its susceptibility.
SHIELDING AGAINST CAPACITIVE COUPLING
Capacitive coupling involves the passage of interfering
signals through mutual or stray capacitances that aren't
shown on the circuit diagram, but which the experienced engineer knows are there. Capacitive coupling to
one's body is what would cause an unstable oscillator to
change its frequency when the person reaches his hand
over the circuit, for example. More importantly, in a
digital system it causes crosstalk in multi-wire cables.
C.
NOISE
SOURCE
The way to block capacitive coupling is to enclose the
circuit or conductor you want to protect in a metal
shield. That's called an electrostatic or Faraday shield.
If coverage is 100%, the shield does not have to be
grounded, but it usually is, to ensure that circuit-toshield capacitances go to signal reference ground rather
than act as feedback and crosstalk elements. Besides,
from a mechanical point of view, grounding it is almost
inevitable.
L.
----11--~
VICTIM
CKT
I
210313-5
(a) Capacitive Coupling
/FARADAY SHIELD
NOISE
SOURCE
A grounded Faraday shield can be used to break capacitive coupling between a noisy circuit and a victim cir-'
cuit, as shown in Figure 4. Figure 4a shows two circuits
capacitively coupled through the stray capacitance between them. In Figure 4b the stray capacitance is intercepted by a grounded Faraday shield, so that interference currents are shunted to ground. For example, a
grounded plane can be inserted between PCBs (printed
circuit boards) to eliminate most of the capacitive coupling between them.
-11-- --11-
I
VICTIM
CKT
I
-:;.:
210313-6
(b) Electrostatic Shielding
Figure 4. Use of Faraday Shield
9-6
AP-125
V.
I
I~-----------------_
I
I
-I
_L,CURRENTLOOP~~~~~/
- - - / ' " CURRENT LOOP
210313-7
,----
\
Figure 5. External to the Shield, = 0
-=
.... ..--'
(/
~~
210313-8
(a) Shield Has No Effect
Shielding against inductive coupling means nothing
more nor less than controlling the dimensions of the
current loops in the circuit. We must look at four examples of this type of "shielding": the coaxial cable, the
twisted pair, the ground plane, and the gridded-ground
PCB layout.
I
I
I
Vs
~ ___ )
The Coaxial Cable-Figure 5 shows a coaxial cable
carrying a current I from a signal source to a receiving
load. The shield carries the same current as the center
conductor. Outside the shield, the magnetic field produced by + I flowing in the center conductor is cancelled by the field produced by - I flowing in the
shield. To the extent that the cable is ideal in producing
zero external magnetic field, it is immune to inductive
pickUp from external sources. The cable adds effectively zero area to the loop. This is true only if the shield
carries the same current as the center conductor.
----
HIGH· FREQUENCY
CURRENT PATH
-
R
:I
(-----\-------------1
I
L __ _
\
/
I
I
'- - ~ ~
~~
'-.. LOW·FREQUENCY
CURRENT PATH
210313-9
(b) Two Return Paths
Figure 6. Use of Coaxial Cable
minimum loop area. Hence, for higher frequencies the
shield carries virtually the same current as the center
conductor, and is therefore effective against both generation and reception of EMI.
In the real world, both the signal source and the receiving load are likely to have one end connected to a common signal ground. In that case, should the cable be
grounded at one end, both ends, or neither end? The
answer is that it should be grounded at both ends. Figure 6a shows the situation when the cable shield is
grounded at only one end. In that case the current loop
runs down the center conductor of the cable, then back
through the common ground connection. The loop area
is not well defined. The shield not only does not carry
the same current as the center conductor, but it doesn't
carry any current at all. There is no field cancellation at
all. The shield has no effect whatsoever on either the
generation of EMI or susceptibility to EM!. (It is, however, still effective as an electrostatic shield, or at least
it would be if the shield coverage were 100%.)
Note that we have now introduced the famous "ground
loop" problem, as shown in Figure 7a. Fortunately, a
digital system has some built-in immunity to moderate
ground loop noise. In a noisy environment, however,
one can break the ground loop, and still maintain the
shielding effectiveness of the coaxial cable, by inserting
an optical coupler, as shown in Figure 7b. What the
optical coupler does, basically, is allow us to re-define
the signal source as being ungrounded, so that that end
of the cable need not be grounded, and still lets the
shield carry the same current as the center conductor.
Obviously, if the signal source weren't grounded in the
first place, the optical coupler wouldn't be needed.
Figure 6b shows the situation when the cable is grounded at both ends. Does the shield carryall of the return
current, or only a portion of it on account of the shunting effect of the common ground connection? The answer to that question depends on the frequency content
of the signal. In general, the current loop will follow the
path of least impedance. At low frequencies, 0 Hz to
several kHz, where the inductive reactance is insignificant, the current will follow the path of least resistance.
Above a few kHz, where inductive reactance predominates, the current will follow the path of least inductance. The path of least inductance is the path of
The Twisted Pair-A cheaper way to minimize loop
area is to run the feed and return wires right next to
each other. This isn't as effective as a coaxial cable in
minimizing loop area. An ideal coaxial cable adds zero
area to the loop, whereas merely keeping the feed and
return wires next to each other is bound to add a finite
area.
However, two things work to make this cheaper method almost as good as a coaxial cable. First, real coaxial
cables are not ideal. If the shield current isn't evenly
distributed around the center conductor at every cross-
9-7
inter
AP-125
POTENTIAL DIFFERENCE
BETWEEN THE TWO
GROUND POINTS
210313-10
(a) The Ground Loop
IOPTICAL COUPLER
.....--!..-...,
v.
J '--'\
+5V
_____________________ JI
------,--------------,
'CURRENT LOOP
:
II
I
R
l' ___ )
I
I
210313-11
(b) Breaking the Ground Loop
Figure 7. Use of Optical Coupler
section of the cable· (it isn't), then field cancellation external to the shield is incomplete. If field cancellation is
incomplete, then the effective area added to the loop by
the cable isn't zero. Secori9, in the cheaper method the
feed and return ~ires can be twisted together. This not
only maintains their proxiinity, but the noise picked up
in one twist tends to cancel out the noise picked up in
the next twist down the line. Thus the "twisted pair"
turns out to be about as good a shield against inductive
coupling as coaxial cable is ..
The twisted pair does not, however, provide electrostatic shielding (i.e., shielding against capacitive coupling).
Another operational difference between them is that
the coaxial cable works better at higher frequencies.
This is primarily" because the twisted pair adds more
capacitive loading to the signal source than the coaxial
cable does. The twisted pair is normally considered useful up to only abou,t 1 MHz, as opposed to near a GHz
for the coaxial cable.
Thus, if the feed path for a given signal zigzags its way
across the PCB, the return path for this signal is free to
zigzag right along beneath it on the ground plane, in
such a configuration as to minimize the energy stored
in the magnetic fleld produced by this current loop.
Minimal maglletic flux means minimal effective loop
area and minimal susceptibility to inductive coupling.
The Gridded-Ground PCB Layout-The next best
thing to a ground plane is to layout the ground traces
on a PCB in the form of a grid structure, as shown in
. Figure 8. Laying horizontal traces on one side of the
board and vertical traces on the other side allows the
passage of signal and power traces. Wherever vertical '
and horizontal ground traces cross, they must be connected by a feed-through.
Have we not created here a network of "ground loops"?
Yes, in the literal sense of the word, but loops in the
grourid layout on a PCB are not to be feared. Such
inoffensive little loops have never caused as much noise
pickup as their avoidance has. Trying 'to avoid innocent
little loops in the ground layout, PCB designers have
forced current loops into geometries that could swallow
a whale. That is exactly the wrong thing to do,
The Ground Plane-The best way to minimize loop
areas when many curre~t loops are involved is to use a
ground plane. A ground plane is a conducting surface
that is to serve as a return conductor for all the current
loops in the circuit. Normally, it would be one or more
layers of a multilayer PCB. All ground points in the
circuit go not to a grounded trace on the PCB, but
directly to the ground plane. This leaves each current
loop in the circuit free to complete itself in whatever
configuration yields minimum loop area (for frequencies wherein the ground path impedance is primarily
inductive).
The gridded ground structure works almost as well as
the ground plane, as far as minimizing loop area is concerned. For a given current loop, the primary return
path may have to zig once in a while where its feed path
zags, but you still get a mathematically optimal dis-
9-8
AP-125
against RF interference from a whip antenna. A gridded-ground structure would be less effective.
In the near field of a loop antenna, the E/H ratio is
lower than 377n, which means it's mainly an H-field
generator. Any current loop is a loop antenna. Interference from a loop antenna would be by magnetic field
coupling, which is basically the same as inductive coupling. Methods to protect a circuit from inductive coupling, such as a gridded-ground structure, would be effective against RF interference from a loop antenna. A
Faraday shield would be less effective.
~ DIP
l""""".;;l
0 DECOUPLING
CAPACITOR
_
GROUND
e-
A more difficult case of RF interference, near field or
far field, may require a genuine metallic RF shield. The
idea behind RF shielding is that time-varying EMI
fields induce currents in the shielding material. The induced currents dissipate energy iii two ways: PR losses
in the shielding material and radiation losses as they reradiate their own EM fields. The energy for both of
these mechanisms is drawn from the impinging EMI
fields. Hence the EMI is weakened as it penetrates the
shield.
ELECTROLYTIC
CAPACITOR
210313-12
Figure 8. PCB with Gridded Ground
tribution of currents in the grid structure, such that the
current loop produces less magnetic flux than if the
return path were restrained to follow any single given
ground trace. The key to attaining minimum loop areas
for all the current loops together is to let the ground
currents distribute themselves around the entire area of
the board as freely as possible. They want to minimize
their own magnetic field. Just let them.
More formally, the PR losses are referred to as absorption loss, and the re-radiation is called reflection loss.
As it turns out, absorption loss is the primary shielding
mechanism for H-fields, and reflection loss is the primary shielding mechanism for E-fields. Reflection loss,
being a surface phenomenon, is pretty much independent of the thickness of the shielding material. Both
loss mechanisms, however, are dependent on the frequency (w) of the impinging EM! field, and on the
permeability (fJ.) and conductivity (0") of the shielding
material. These loss mechanisms vary approximately as
follows:
RF SHIELDING
A time-varying electric field generates a time-varying
magnetic field, and vice versa. Far from the source of a
time-varying EM field, the ratio of the amplitudes of
the electric and magnetic fields is always 377fl.. Up
close to the source of the fields, however, this ratio can
be quite different, and dependent on the nature of the
source. Where the ratio is near 377n is called the far
field, and where the ratio is significantly different from
377n is called the near field. The ratio itself is called
the wave impedance, E/H.
reflection loss to an E-field (in dB) - log.!!...
wfJ.
absorption loss to an H-field (in dB) - t~wO"fJ.
where t is the thickness of the shielding material.
The first expression indicates that E-field shielding is
more effective if the shield material is highly conductive, and less effective if the shield if ferromagnetic, and
that low-frequency fields are easier to b,lock than highfrequency fields. This is shown in Figure 9.
, The near field goes out about 1/6 of a wavelength from
the source. At 1 MHz this is about 150 feet, and at 10
MHz it's about 15 feet. That means if an EMI source is
in the same room with the victim circuit, it's likely to
be a near field problem. The reason this matters is that
in the near field an RF interference problem could be
almost entirely due to E-field coupling or H-field coupling, and that could influence the choice of an RF
shield or whether an RF shield will help at all.
iii 150
~
..
II:
125
en
100
0
oJ
In the near field of a whip antenna, the E/H ratio is
higher than 377n, which means it's mainly an E-field
generator. A wire-wrap post can be a whip antenna.
Interference from a whip antenna would be by electric
field coupling, which is basically capacitive coupling.
Methods to protect a circuit from capacitive coupling,
such as a Faraday shield, would be effective
z
75
~
50
25
0
"'
oJ
U.
W
II:
0
0.01
0,1
1.0
10
100
1000
10.000
FREQUENCY (KILOHERTZ)
210313-13,
Figure 9. E-Field Shielding
9-9
inter
AP-125
In.---------~r_------r_~------~
300~-----------------------------~
1
.. j
150
PLANE WAVE
250
,,
'
i!: 200
,,
,,
t;
$
,
150
---- ----1-"
,,
Cl
z
.
REFLECTION
9,100
:E
..
~
25
I:!
I
0.01
10
10'
103
104
.10'
10'
"",
501
------0.1
1.0
10
~~~~~~ABSORPTION
100
1000
10.000
FREQUENCY (KILOHERTZ)
10'
FREQUENCY (HERTZ)
210313-15
210313-14
Figure 10. H·Field Shielding
Figure 11. E· and H·Field Shielding
Copper and aluminum both have the same permeability, but copper is slightly more conductive, and so provides slightly greater reflection loss to an E-field. Steel'
is less effective for two reasons. First, it has a somewhat
elevated permeability due to its iron content, and second, as tends to be the case. with magnetic materials, it
is less conductive.
rents must be allowed to flow freely. If they have to
detour around slots and holes, as shown in Figure 12,
the shield loses much of its effectiveness.
As can be seen in Figure 12, the severity of the detour
has less to do with the area of the hole than it does with
the geometry of the hole. Comparing Figure 12c with
12d shows that a long narrow discontinuity such as a
seam can cause more RF leakage than a line of holes
with larger total area. A person who is responsible for
designing or selecting rack or chassis enclosures for an
EMI environment needs to be familiar with the techniques that are available for maintaining electrical continuity across seams. Information on these techniques is
available in the references.
On the other hand, according to the expression for absorption loss to an H-field, H-field shielding is more
effective at higher frequencies and with shield material
that has both high conductivity and high permeability.
In practice, however, selecting steel for its high permeability involves some compromise in conductivity. But
the increase in permeability more than makes up for the
decrease in conductivity, as can be seen in Figure 10.
This figure also shows the effect of shield thickness.
Grounds
A composite of E-field and H-field shielding is shown
in Figure II. However; this type of data is meaningful
only in the far field. In the near field the EM!. could be
90% H-field, in which case the reflection loss is irrelevant. It would be advisable then to beef up the absorption loss, at the expense of reflection loss, by choosing
steel. A better conductor than steel might be less expensive, but quite ineffective.
There are two kinds of grounds: earth-ground and signal ground. The earth is not an equipotential surface, so
earth ground potential varies. That and its other electrical properties are not conducive to its use as a return
conduc,tor in a circuit. However, circuits are often connected to earth ground for protection against shock
hazards. The other kind of ground, signal ground, is an
arbitrarily selected reference node in a circuit--the
node with respect to which other node voltages in the
circuit are measured.
, A different shielding mechanism that can be taken advantage of for low frequency magnetic fields is the ability of a high permeability material such as mumetal to
divert the field by presenting a very low reluctance path
to the magnetic flux. Above a few kHz, however, the
permeability of such materials is the same as steel.
SAFETY GROUND
In actual fact the selection of a shielding material turns
out to be less important than the presence of seams,
joints and holes in the physical structure of the enclosure. The shielding mechanisms are related to the induction of currents in the shield material,but the cur- ,
The standard 3-wire single-phase AC power distribution system is represented in Figure 13. The white wire
is earth-grounded at the service entrance. If a load circuit has a metal enclosure or chassis, and if the black
wire develops a short to the enclosure, there will be a
shock hazard to operating personnel, unless the enclosure itself is earth-grounded. If the enclosure is earth-
9-10
inter
AP-125
__ INDUCED
SHIELD
CURRENTS
- -SECTION OF
SHIELD
(a)
(b)
(e)
(d)
210313-16
Figure 12. Effect of Shield Discontinuity on Magnetically Induced Shield Current
grounded, a short results in a blown fmle rather than a
"hot" enclosure. The earth-ground connection to the
enclosure is called a safety ground. The advantage of
the 3-wire power system is that it distributes a safety
ground along with the power.
SIGNAL GROUND
Note that the safety-ground wire carries no current,
except in case of a fault, so that at least for low frequencies it's at earth-ground potential along its entire
length. The white wire, on the other hand, may be sev- .
eral volts off ground, due to the IR drop along its
length.
SERVICE
. (ENTRANCE
,,-------,
I
I
I
(
BLACK
I
I
I
I
I
I
I
I
I
I
The series connection is pretty common because it's
simple and economical. It's the noisiest of the three,
however, due to common ground impedance coupling
between the circuits. When several circuits share a
ground wire, currents from one circuit, flowing through
the finite impedance of the common ground line, cause
variations in the ground potential of the other circuits.
Given that the currents in a digital system tend to be
spiked, and that the common impedance is mainly inductive reactance, the variations could be bad enough
to cause bit errors in high current or particularly noisy
situations.
METAL
ENCLOSURE
;'"--------,
I
I
I
LOAD
CKT
WHITE
Signal ground is a single point in a circuit that is designated to be the reference node for the circuit. Commonly, wires that connect to this single point are also referred to as "signal ground." In some circles "power
supply common" or PSC is the preferred terminology
for these conductors. In any case, the manner in which
these wires connect to the actual reference point is the
basis of distinction among three kinds of signal-ground
wiring methods: series, parallel, and multipoint. These
methods are shown in Figure 14.
:
I
I
I
I
---)
GREEN
1, ___ -
EARTH-GROUND
The parallel connection eliminates common ground im~
pedance problems, but uses a lot of wire. Other disadvantages are that the impedance of the individuaJ
ground lines can be very high, and the ground lines
themselves can become sources of EM!.
210313-17
Figure 13. Single-Phase Power Distribution
9-11
inter
AP-125
In the mUltipoint system, ground impedance is minimized by usiq.g a ground plane with the various circuits
connected to it by very short ground leads. This type of
connection would be used mainly in RF circuits above
10 MHz.
NOISY
AND HIGH
CURRENT
SIGNAL
GROUND
HARDWARE
GROUND
PRACTICAL GROUNDING
A combination of series and parallel ground-wiring
methods can be used to trade off economic and the
various electrical considerations. The idea is to run series connections for circuits that have similar noise
properties, and connect them at a single reference
point, as in the parallel method, as shown in Figure 15.
In Figure 15, "noisy signal ground" connects to things
like motors and relays. Hardware ground is the safety
ground connection to chassis, racks, and cabinets. It's a
mistake to use the hardware ground as a return path for
signal currents because it's fairly noisy (for example,
it's the hardware. ground that receives an ESD spark)
and tends to have high resistance due to joints and
seams.
\ GROUND LINE
REF. POINT
210313-18
Series Connection
GREEN-WIRE
GROUND
210313-21
Figure 15. Parallel Connection
of Series Grounds
Screws and bolts don't always make good electrical
connections because of galvanic action, corrosion, and
dirt. These kinds of connections may work well at first,
and then cause mysterious maladies as the system ages.
Figure 16 illustrates a grounding system for a 9-track
digital tape recorder, showing.an application of the series/parallel ground-wiring method.
Figure 17 shows a similar. separation of grounds at the
PCB level. Currents in multiplexed LED displays tend
to put a lot of noise on the ground and supply lines
because of the constant switching and changing involved in the scanning process. The segment driver
ground is relatively quiet, since it doesn't conduct the
LED currents. Tho digit driver ground is noisier, and
should be provided with a separate path to the PCB
ground terminal, even if the PCB ground layout is gridded. The LED feed and return current paths should be
laid out on opposite sides of the board like parallel flat
conductors.
Figure 18 shows right and wrong ways to make ground
connections in racks. Note that the safety ground connections from panel to rack are made through ground
straps, not panel screws. Rack 1 correctly connects signal ground to rack ground only at the single reference
point. Rack 2 incorrectly connects signal ground to
rack ground at two points, creating a ground loop
around points 1, 2, 3, 4, 1.
210313-.19
Parallel Connection
Breaking the "electronics ground" connection to point
1 eliminates the ground loop, but leaves signal ground
in rack 2 sharing a ground impedance with the relatively noisy hardware ground to the reference point; in fact,
it may end up using hardware ground as a return path
for signal and power supply currents. This will probably cause more problems than the ground loop.
BRAIDED CABLE
REF. POINT
210313-20
Multipoint Connection
Figure 14. Three Ways to Wire the Grounds
Ground impedance problems can be virtually eliminated by using braided cable. The reduction in impedance
is due to skin effect: At higher frequencies the current
tends to flow along the surface of a conductor rather
9-12
inter
AP-125
-------------,- - - - - - - - -9 "READ"
AMPLIFIERS
9 "WRITE" CIRCUITS
L----!----:i--'--"""l _________________ J
SIGNAL GROUNDS
GREEN-WIRE
GROUND
210313-22
Figure 16. Ground System in a 9-Track Digital Recorder
CONTROL FUNCTIONS
CONTROLLER
'-------~------~+-~-GROUND
210313-23
Figure 17. Separate Ground for Multiplexed LED Display
9-13
infef
Ap·125
RACK 2
RACK 1
P:6~~~Y ~='_ _ _ _ _ _ _ _ _ _ _ _-I-ELECTRONICS GROUND
GROUND
GREEN-WIRE GROUND
210313-24
Figure 18. Electronic Circuits Mounted in Equipment Racks Should Have Separate Ground
Connections. Rack 1 Shows Correct Grounding, Rack 2 Shows Incorrect Grounding.
than uniformly through its bulk_ While this effect tends
to increase the impedance of a given conductor, it also
indicates the way to minimize impedance, and that is to
manipulate the shape of the cross-section so as to provide more surface area. For its bulk, braided cable is
almost pure surface.
Power Supply Distribution and
Decoupling
The main consideration for power supply distribution
lines is, as for signal lines, to minimize the areas of the
current loops. But the power supply lines take on an
importance that no signal line has when one considers
the fact that these lines have access to every PC board
in the system. The very extensiveness of the supply current loops makes it difficult to keep loop areas small.
And, a noisc glitch on a supply line is a glitch delivered
to every board in the system.
The power supply provides low-frequency current to
the load, but the inductance of the board-to-board and
chip-to-chip distribution network makes it difficult for
the power supply to maintain VCC specs on the chip
while providing the current spikes that a digital system
requires. In addition, the power supply current loop is a
very large one, which means there will be a lot of noise
pick-Up. Figure 19a shows a load circuit trying to draw
current spikes from a supply voltage through the line
impedance. To the VCC waveform shown in that figure
. should be added the inductive pick-up associated with a
large loop area.
Adding a decoupling capacitor solves two problems:
The capacitor acts as a nearby source of charge to supply the current spikes through a smaller line impedance, and it defines a much smaller loop area for the
higher frequency components of EM!. This is illustrated in Figure 19b, which shows the capacitor supplying
the current spike, during which VCC drops from SV by
the amount, indicated in the figure. Between current
spikes the capacitor recovers through the line impedance.
One should resist the temptation to add a resistor or an
inductor to the decoupler so as to form a genuine RC or
LC low-pass filter because that slows down the speed
with which the decoupler cap can be refreshed. Good
filtering and good decoupling are not necessarily the
same thing.
The current loop for the higher frequency currents,
then, is· defined by the decoupling cap and the load
circuit, rather than by the power supply and the load
circuit. For the decoupling cap to be able to provide the
current spikes required by the load, the inductance of
this current loop must be kept small, which is the same
as saying the loop area must be kept small. This is also
the requirement for minimizing inductive pick-up in
the loop ..
There are two kinds of decoupling caps: board decou-'
piers and chip decouplers. A board decoupler will normally be a io to 100 /A-F electrolytic capacitor placed
near to where the power supply enters the PC board,
but its placement is relatively non-critical. The purpose
of the board decoupler is to refresh the charge on the
chip decouplers. The' chip decouplers are what actually
provide the current spikes to the chips. A chip decoupier will normally be a 0.1 to 1 /A-F ceramic capacitor
placed near the chip and connected to the chip by
traces that minimize the area of the loop formed by the
cap and the chip. If a chip decoupler is not properly
placed on the boarel, it will be ineffective as a decoupler
9-14
inter
AP-125
•!
!
vc::c
I:
-.J\
~T
-"-
A
==~~======~====~--.
1
~I
vcc:
- - - - - - - - - - - - - - - - - - - - - - - - - -__ 1
210313-25
210313-26
(a) Drawing Current Spikes
through the Line Impedance
(b) Drawing Current Spikes
from a Decoupling Capacitor
Figure 19. What a Decoupling Capacitor Does
and will serve only to increase the cost of the board.
Good and bad placement of decoupling capacitors are
illustrated in Figure 20.
Power distribution traces on the PC board need to be
laid out so as to obtain minimal area (minimal inductance) in the loops formed by each chip and its decoupier, and by the chip decouplers and the board decoupier. One way to accomplish this goal is to use a power
plane. A power plane is the same as a ground plane, but
at VCC potential. More economically, a power grid
similar to the ground grid previously discussed (Figure
8) can be used. Actually, if the chip decoupling loops
are small, other aspects of the power layout are less
critical. In other words, power planes and power gridding aren't needed, but power traces should be laid in
the closest possible proximity to ground traces, preferThere must be a very low induclance between decoupling capacitor
and the IC.
Poo,Plac8menl
~
LOGICIC
C
Better Placement
VCC
GND
210313-27
The decreased area of loop between capacitor & IC decreases
inductance.
Figure 20. Placement of Decoupling CapaCitors
ably so that each power trace is on the direct opposite
side of the board from a ground trace.
.
Special-purpose power supply distribution buses which
mount on the PCB are available. The buses use a parallel flat conductor configuration, one conductor being a
VCC line and the other a ground line. Used in conjunction with a gridded ground layout, they not only provide a low-inductance distribution system, but can
themselves form part of the ground grid, thus facilitating the PCB layout. The buses are available with and
without enhanced bus capacitance, under the names
MinilBus® and Q/PAC® from Rogers Corp. (5750 E.
McKellips, Mesa, AZ 85205).
SELECTING THE VALUE OF THE
DECOUPLING CAP
The effectiveness of the decoupling cap has a lot to do
with the way the power and ground traces connect this
capacitor to the chip. In fact, the area formed by this
loop is more important than the value of the capacitance. Then, given that the area of this loop is indeed
minimal, it can generally be said that the larger the
value of the decoupling cap, the more. effective it is, if
the cap has a mica, ceramic, glass, or polystyrene dielectric.
It's often said, and not altogether accurately, that the
chip decoupler shouldn't have too large a value. There
are two reasons for this statement. One is that some
capacitors, because of the nature of their dielectrics,
tend to become inductive or lossy at higher frequencies.
This is true of electrolytic capacitors, but mica, glass,
9-15
AP-125
ceramic, and polystyrene dielectrics work well to several hundred MHz. The other reason cited for not using
too large a capacitance has to do with lead inductance.
The capacitor with its lead inductance forms a series
LC circuit. Below the frequency of series resonance, the
net impedance of the combination is capacitive. Above
that frequency, the net impedance is inductive. Thus a
decoupling capacitor is capacitive only below the frequency of series resonance. The frequency is given by
1
fo = 21T,f[C
where C is the decoupling capacitance and L is the lead
inductance between the capacitor and the chip. On a
PC board this inductance is determined by the layout,
and is the same whether the capacitor dropped into the
PCB holes is O.DOI p.F or I p.F. Thus, increasing the
capacitance lowers the series resonant frequency. In
fact, according to the resonant frequency formula, increasing C by a factor of 100 lowers the resonant frequency by a factor of 10.
Figures quoted on the series resonant frequency of a
0.01 p.F capacitor run from 10 to 15 MHz, depending
on the, lelld length. If thf::se numbers were accurate, a
1 p.F capacitor in the same position on the board would
, have a resonant frequency of 1.0 to 1.5 MHz, and as a
decoupler would do more harm than good. However,
the numbers are based on a presumed inductance of a
given length of wire (the lead length). It should be'noted thl!ot a "length of wire" has no inductance at all,
strictly speaking. Only a complete current loop has inductance, and the inductance 'depends on the geometry
of the loop. Figures quoted on the inductance of a
length of wire are based on a presumably "very large"
loop area, such that the magnetic field produced by the
return current has no cancellation effect on the field
produced by the current in the given length of wire.
Such a loop geometry is not and should not be the case
with the decoupling loop.
Figure 21 shows VCC waveforms, measured between
pins 40 and 20 (VCC and VSS) of an 8751 CPU, for
several conditions of decoupling on a PC board that has
a decoupling loop area slightly larger than necessary.
These photographs show the effects of increasing the
decoupling capacitance and decreasing the area of the
decoupling loop. The indications are that a I p.F capacitor is better than a 0.1 p.F capacitor, which in turn is
better than nothing, a~d that the board should have
been laid out with more attention paid to the area of the
decoupling loop.
Figure 21e was obtained using a special-purpose experimental capacitor designed by Rogers Corp. (Q-Pac Division, Mesa, AZ) for use as a decoupler. It consists of
two parallel plates, the le!lgth of a 4O-pin DIP, separated by a ceramic dielectric. Sandwiched between the
CPU chip and the PCB (or between the CPU socket
and the PCB), it makes connection to pins 40 and 20,
forming a leadless decoupling capacitor. It is obviously
a configuration of minimal inductance. Unfortunately,
the particular sample tested had only 0.07 p.F of capacitance and so was unable to prevent the 1 MHz ripple
as effectively as the configuration of Figure 2Id. It
seems apparent, though, that with more capacitance
this part will alleviate a lot of decoupling problel)1s.
THE CASE FOR ON-BOARD VOLTAGE
REGULATION
To complicate matters, supply line glitches aren't always picked up in the distribution networks, but can
come from the power supply circuit itself. In that case;
a well-designed distribution network faithfully delivers
the glitch throughout the system. The VCC glitch in
Figure 22 was found to be coming from within a bench
power supply in response to the EMP produced by an
induction coil spark generator that was being used at
Intel during a study of noise sensitivity. The VCC
glitch is about 400 mV high and some 20 p.s in duration. Normal board decoupling techniques were ineffective in removing it, but adding an on-board vQltage regulator chip did the job.
Thus, a good case can be made in favor of using a
voltage regulator chip on each PCB, instead of doing all
the voltage regulation at the supply circuit. This eases
requirements on the heat-sinking at the supply circuit,
and alleviates much of the distribution and board decoupling headaches. However, it also brings in the possibility that different boards would be operating at
slightly different VCC levels due to tolerance in the
regulator chips; this then leads to slightly different logic
levels from board to board. The implications of that
may vary from nothing to latch-up, depending on what
kinds of chips are on the boards, and how they react to
an input "high" that is perhaps OAV higher than local
VCC.
Recovering Gracefully from a Software .
Upset
Even when one follows all the best guidelines for designing for a noisy environment, it's always possible for
a 'noise transient to occur which exceeds the circuit's
immunity level. In that case, one can strive at least for a
graceful recovery.
Graceful recovery schemes involve additional hardware
and/or software which is supposed to return the system
to a normal operating mode after a software upset has
occurred. Two decisions have to be made: How to recognize when an upset has occurred, and what to do
about it.
9-16
AP-125
PIN 40
PIN 40
ALE
ALE
210313-28
(a) No Dec6upling Cap
PIN 40
PIN40
ALE
ALE
5~V
210313-30
(d) 1.0 p.F Decoupler Stretched Directly
from Pin 40 to Pin 20, under the Socket.
(This prevents the 1 MHz ripple, but there's
no reduction in higher frequency components.
Further increases in capacitance
effected no further improvement.)
PIN 40
soar
__ _
210313-31
(c) 0.1 p.F Decoupler Stretched Directly
from Pin 40 to Pin 20, under the Socket.
(The difference between this and 21b is
due only to the change in loop geometry.
Also shown is the upward slope of a ripple
in VCC. The ripple frequency is
1 MHz, the same as ALE.)
ALE
I
5V _~
i
SV
210313-32
(e) Special-Purpose Decoupling Cap
under Development by Rogers Corp.
(Further discussion in text.)
Figure 21. Noise on VCC Line
9-17
AP-125
. SPARK PROBE
50mV (TRIGGER)
Vcc'
500mV
210313-33
Figure 22. EMP-Induced Glitch
If the designer· knows what kinds and combin~tions of
outputs can legally be generated by the system, he can
use gates to recognize and flag the occurrence of an
illegal state of affairs. The flag can then trigger a jump
to a recovery routine which then may check or re-ini-.
tialize data, perhaps output an error message, or generate a simple reset.
The most reliable scheme is to use a so-called watchdog
circuit. Here the CPU is p.rogrammed to generate a
periodic signal as long as the system is executing instructions in an expected manner. The periodic signal is
then used to hold off a circuit that will trigger a jump to
a recovery routine. The periodic' signal needs to be ACcoupled to the trigger circuit so that a "stuck-at" fault
won't continue to hold offtl).e trigger. Then, if the processor locks up someplace, the periodic signal is lost and
the watchdog triggers a reset.
In practice, it may be convenient to drive the watchdog
circuit with a signal which is being generated anyway
by the systetn. One needs to be careful, however, that
an upset does in fact discontinue that signal. Specifically, for example, one could use one of the digit drive
signals going to a multiplexed display. But display
scanning is often handled in response to a timer-interrupt, which may continue operating even though the
main program is in a failure mode. Even so, with a little
extra software, the signal can be' used to control the
watchdog (see Reference 8 on this).
Simpler schemes can work weIl for simpler systems.
For example, if a CPU isn't doing anything but scanning and decoding a keyboard, there's little to lose and
much to gain by simply resetting it periodically with an
astable multivibrator. It only takes about 13 j.l.s (at 6
MHz) to reset an 8048 if the clock oscillator is already
running.
A zer~cost measure is simply to fiIl all unused program memory with NOPs and JMPs to a recovery rou·
tine. The effectiveness of this method is increased by
writing the program in segments that are separated by
NOPs and JMPs. It's still possible, of course, to get
hung up in a data table or something. But you get a lot
of protection, for the cost.
Further discussion of graceful recovery schemes can be
found in Reference 13.
Special Problem Areas
ESD
MOS chips have some built-in protection against a static charge build-up on the pins, as would occur during
normal handling, but there's no protection against the
kinds of current levels and rise times that occur in a
genuine electrostatic spark. These kinds of discharges
can blow a crater in the silicon.
.
It must be recognized that connecting CPU pins unprotected to a keyboard or to anything else that is subject
to electrostatic discharges makes an extremely fragile
configuration. Buffering the~ is the very least one can
do. But buffering docsn't completely solve the problem,
because then the buffer chips will sustain the damage
(even TTL); therefore, one might consider mounting
the buffer chips in sockets for ease of replacement:
Transient suppressors, such as the TranZorbs® made
by General Semiconductor Industries (Tempe, AZ),
may in .the long run provide the cheapest protection if
their "zero inductance" structure is used. The structure
and circuit application are shown in Figure 23.
The suppressor element is a pn junction that operates
like a Zener diode. Back-to-back units are available for
AC operation. The element is more or less an open
circuit at normal system voltage (the standoff voltage
rating for the device), and conducts like a Zener diode
at the clamping voltage.
The lead inductance in the conventional transient suppressor package makes the conventional package essen9-18
inter
AP-125
PULSE DIGITAL
A
Hh--;----tB
FUNCTIONAL
1-i-=F:,--;--jC DECODER
1-1-++--,....,..-1 D
L ____ I
COMMON
210313-34
Palenl Pending
(a)
210313-35
(b)
Figure 23. "Zero-Inductance" Structure and Use in Circuit
tially useless for protection against ESD pulses, owing
to the fast rise of these pulses. The "zero inductance"
units are available singly in a 4-pin DIP, and in arrays
of four to a 16-pin DIP for PCB level protection. In
that application they should 1;>e mounted in close proximity to the chips they protect.
In addition, metal enclosures or frames or parts that
can receive an ESD spark should be connected by
braided cable to the green-wire ground. Because of the
ground impedance, ESD current shouldn't be allowed
to flow through any signal ground, even if the chips are
protected by transient suppressors. A 35 kV ESD spark
can always spare a few hundred volts to drive a fast
current pulse down a signal ground line if it can't find a
braided caple to follow. Think how delighted your 8048
will be to find its VSS pin 250V higher than VCC for a
few lOs of nanoseconds.
THE AUTOMOTIVE ENVIRONMENT
The automobile presents an extremely hostile environment for electronic systems. There are several parts to
it:
1. Temperature extremes from -40°C to + 125°C (under the hood) or + 85°C (in the passenger compartment)
2. Electromagnetic pulses from the ignition system
3. Supply line transients that will knock your socks off
One needs to take a long, careful look at the temperature extremes. The allowable storage temperature range
for most Intel MaS chips is -65°C to + 150°C, although some chips have a maximum storage temperature rating of + 125°C. In operation (or "under bias,"
as the data sheets say) the allowable ambient temperature range depends on the product grade, as follows:
Grade
Commercial
Industrial
Automotive
Military
Ambient Temperature
Min
Max
0
-40
-40
-55
70
+85
+ 110
+125
The different product grades are actually the same
chip, but tested according to different standards. Thus,
a given commercial-grade chip might actually pass military temperature requirements, but not have been tested for it. (Of course, there are other differences in grading requirements having to do with packaging, burn-in,
traceability, etc.)
In any case, it's apparent that commercial-grade chips
can't be used safely in automotive applications, not
e)len in the passenger compartment. Industrial-grade
chips can be used in the passenger compartment, and
automotive or military chips are required in under-thehood applications.
Ignition noise, CB radios, and that sort of thing are
probably the least of your worries. In a poorly designed
system, or in one that has not been adequately tested
for the automotive environment, this type of EMI
might cause a few software upsets, but not destroy
chips.
The major problem, and the one that seems to come as
the biggest surprise to most people, is the line transients. Regrettably, the 12V battery is not actually the
source of power when the car is running. The charging
system is, and it's not very clean. The only time the
battery is the real source of power is when the car is
first being started, and in that condition the battery
terminals may be delivering about 5V or 6V. As follows
is a brief description of the major idiosyncracies of the
"12V" automotive power line.
9-19
inter
AP-125
60
50
iii
~
ENGINE SPEED 3000 RPM
ALTERNATOR LOAD 55 AMPERES
40
~
~ 3D
5
~ 20
10
O+---r-~r-~--~---r---r--'---'---.---'
o
~
~
~
~
~
~
~
~
~
~
TIME (MILLISECONDS)
210313-36
Figure 24. Typical Load Dump Transients
• An abrupt reduction in the alternator load causes a
positive voltage transient called "load dump." In a
load dump transient the line voltage rises to 20V or
30V in a few JLs, then decays exponentially with a
time constant of about 100 JLs, as shown in Figure
24. Much higher peak voltages and longer decay
times have also been reported. The worst case load
dump is caused by disconnecting a low battery from
the alternator circuit while the alternator is running.
Normally this would happen intermittently when
the battery terminal connections are defective.
• When the ignition is-turned off, as the field excitation - decays, the line voltage can go to between
-40Vand -100V for 100 JLs or more.
• Miscellaneous solenoid ,switching transients, such as
the one. shown in Figure 25, can drive the line to +
Or - 200V to 400V for several JLs.
• Mutual coupling between unshielded wires in long
harnesses can induce l00V and 200V transients in
unprotected circuits.
What all this adds up to is that people in the business of
building systems for automotive applications need a
comprehensive testing program. An SAE guideline
which describes the automotive environment is available to designers: SAE 11211, "Recommended Environmental Practices for Electronic Equipment Design,"
1980 SAE Handbook, Part 1, pp. 22.80-22.96.
Some suggestions for protecting circuitry are shown in
Figure 26. A transient suppressor is placed in front of
the regulator chip to protect it. Since the rise times in
these transients are not like those in ESD pulses, lead
inductance is less critical and conventional devices can
be used. The regulator itself is pretty much of a necessity, since a load dump transient is simply not going to be
removed by any conventional LC or RC filter.
o SEC.
1
OVOLTS -
-100 VOLTS/DIV
10 p s/OlV
---
210313-37
Figure 25; Transient Created by De-energizing an Air Conditioning Clutch Solenoid
9-20
intJ
AP-125
AUTOMOTIVE ON BOARD COMPUTER
ACCESSORY
o---rnl"'-.--l. . .
-12V
_-'\NI---I----.~ TO ~ PROCESSOR
"¥
l15V
DISTANCE
MEASURING COIL
,-o-----------~~~~--~TO~PROCESSOR
5V
210313-38
Figure 26. Use of Transient Suppressors in Automotive Applications
Special I/O interfacing is also required, because of the
need for high tolerance to voltage transients, input
noise, input/output isolation, etc. In addition, switches
that are being monitored or driven by these buffers are
usually referenced to chassis ground instead of signal
ground, and in a car there can be many volts difference
between the two. I/O interfacing is discussed in Reference 2.
The EMC Education committee has available a video
tape: "Introduction to EMC-A Video Training
Tape," by Henry 'Ott. Don White Consultants offers a
series of training courses on many different aspects of
electromagnetic compatibility. Most organizations that
sponsor EMC courses also offer in-plant presentations.
Parting Thoughts
The main sources of information for this Application
Note were the references by Ott and by White. Reference 5 is probably the finest treatment currently available on the subject. The other references provided specific information as cited in the text.
Courses and seminars on the subject of electromagnetic
interference are given regularly throughout the year.
Information on these can be obtained from:
IEEE Electromagnetic Compatibility Society
EMC Education Committee
345 East 47th Street
New York, NY 10017
Don White Consultants, Inc.
International Training Centre
P.O. Box p
Gainesville, VA 22065
Phone: (703) 347-0030
9-21
AP-125
REFERENCES
1. Clark, O.M., "Electrostatic Discharge Protection
Using Silicon Transient Suppressors," Proceedings of
the Electrical Overstress/Electrostatic Discharge Symposium. Reliability Analysis Center, Rome Air Development Center, 1979;
2. Kearney, M; Shreve, J.; and Vincent, W., "Microprocessor Based Systems in the Automobile: Custom
Integrated Circuits Provide an Effective Interface,"
Electronic Engine Management and Driveline Control
Systems, SAE Publication SP~481, 810160, pp. 93-102.
3. King, W.M. and Reynolds, D., "Personnel Electrostatic Discharge: Impulse Waveforms Resulting From
ESD of Humans Directly and Through Small HandHeld Metallic Objects Intervening in the Discharge
Path," Proceedings of the IEEE Symposium on Electromagnetic Compatibility. pp. 577-590, Aug. 1981.
4. Ott, H., "Digital Circuit Grounding and Interconnection," Proceedings of the IEEE Symposium on Electromagnetic Compatibiqty. pp. 292-297, Aug: 1981.
,5. Ott, H., Noise Reduction Techniques in Electronic
Systems. New York: Wiley, 1976.
7. SAE 11211, "Recommended Environmental Practices for Electronic Equipment Design," 1980 SAE
Handbook. Part 1, pp. 22.80-22.96.
8. Smith, L., "A Watchdog Circuit for Microcomputer Based Systems," Digital Design. pp. 78, 79, Nov.
1979.
9. TranZorb Quick Reference Guide. General Semiconductor Industries, P.O. Box 3078, Tempe, AZ
85281.
10. Tucker, T.J., "Spark Initiation Requirements of a
Secondary Explosive," Annals of the New York Academy of Sciences. Vol 152, Article I, pp. 643-653, 1968.
11. White, D., Electromagnetic Interference and Compatibility. VoL 3: EMI Control Methods and Techniques.
Don White Consultants, 1973.
12. White, D., EMI Control in the Design of Printed
Circuit Boards lmd Backplanes. Don White Consultants, 1981.
13. Yarkoni, B. and Wharton, J., "Designing Reliable
Software for Automotive Applications," SAE Transactions, 790237, July)979.
.
\
6. 1981 Interfe~ence' Technology Engineers' Master
(ITEM) Directory and Design Guide. R. and B. Enterprises, P.O. Box 328, Plymouth Meeting, PA 19426:'
9-22
inter
AP-155
APPLICATION
NOTE
June 1983
Oscillators
for Microcontrollers
TOM WILLIAMSON
MICROCONTROLLER
TECHNICAL MARKETING
@
Intel Corporation, 1988
9-23
Order Number: 230659-001
intJ
AP-155
INTRODUCTION
Intel's microcontroller families (MCS®-48, MCS®-51,
and iACX-96) contain a circuit that is commonly referred to as the "on-chip oscillator". The on-chip circuitry is not itself an oscillator, of course, but an amplifier that is suitable for use as the' amplifier part of a
feedback oscillator. The data sheets and Microcontoller
Handbook show how the on-chip amplifier and several
off-chip components can be used to design a working
oscillator. With proper selection of off-chip components, these oscillator circuits will perform better than
almost any other type of clock oscillator, and by almost
any criterion of excellence. The suggested circuits are
simple, economical, stable, and reliable.
We offer assistance to our customers in selecting suitable off-chip components to work with the on-chip oscillator circuitry. It should be noted, however, that Intel cannot assume the responsibility of writing specifications for the off-chip components of the complete oscillator circuit, nor of guaranteeing the performance of
the finished design in production, anymore than a transistor manufacturer, whose data sheets show a number
of suggested amplifier circuits, can assume responsibility for the operation, in production, of any of them.
This Application Note is intended to provide such assistance in the design of oscillator circuits for microcontroller systems. Its purpose is to describe in a practical manner how oscillators work, how crystals and ceramic resonators work (and thus how to spec them),
and what the on-chip amplifier looks like electronically
and what its operating characteristics are. A BASIC
program is provided in Appendix II to ,assist the designer in determining the effects of changing individual
parameters. Suggestions are provided for establishing a
pre-production test program.
FEEDBACK OSCILLATORS
Loop Gain
Figure 1 shows an amplifier whose output line goes into
some passive network. If the input signal to the amplifier is VI, then the output signal from the amplifer is v2
= AVI and the output signal from the passive network
is v3 = /3v2 = /3Avl. Thus /3A is the overall gain
from terminal 1 to terminal 3.
We are often asked why we don't publish a list of required crystal or ceramic resonator specifications, and
recommend values for the other off-chip components.
This has been done in the past, but sometimes with
corisequences that were not intended.
Suppose we 'suggest a maximum crystal resistance of 30
ohms for some given frequency. Then your crystal supplier tells you the 30-ohm'crystals are going to cost
twice as much as 50-ohm crystals. Fearing that Intel
will not "guarantee operation" with 50-ohm crsytals,
you order the expensive ones. In fact, Intel guarantees
only what is embodied within an Intel product. Besides,
there is no reason why 50-ohm crystals couldn't be
used, if the other off-chip components are suitably adjusted.
Should we recommend values for the other off-chip
components? Should we do it for 50-ohm crystals or 30ohm crystals? With respect to what should we optimize
their selection? Should we minimize start-up time or
maximize frequency stability? In many applications,
neither start-up time nor frequency stability are particularly critical, and our "recommendations" are only restricting your system to unnecessary tolerances. It all
depends on the application.
Although we will neither "specify" nor "recommend"
specific off-chip components, we do offer assistance in
these tasks. Intel application engineers are available to
provide whatever technical assistance may be needed or
desired by our customers in designing with Intel products.
230659-1
Figure 1. Factors in Loop Gain
Now connect terminal 1 to terminal 3, so that the signal path forms a loop: 1 to 2 to 3, which is also 1. Now
we have a feedback loop, and the gain factor /3A is
called the loop gain.
Gain factors are complex numbers. That means they
have a magnitude and a phase angle, both of which
vary with frequency. When writing a complex number,
one must specify both quantities, magnitude and angle.
A number whose magnitude is 3, and whose angle is '45
degrees is commonly written this way; 3L45°. The number 1 is, in complex number notation, lLO°, while -I is
lLI80°.
By closing the feedback loop in Figure 1, we force the
equality
This equation has two solutions:
1) 'lJ1 = 0;
2)
9-24
~A
= UO'.
intJ
AP-155
In a given circuit, either or both of the solutions may be
in effect. In the first solution the circuit is quiescent (no
output signal). If you're trying to make an oscillator, a
no-signal condition is unacceptable. There are ways to
guarantee that the second solution is the one that will
be in effect, and that the quiescent condition will be
excluded.
In order for the loop gain to have zero phase angle it is
necessary that the feedback element Zr have a positive
reactance. That is, it must be inductive. Then, the frequency at which the phase angle is zero is approximately the frequency at which
+1
Xf=-
wC
How Feedback Oscillators Work
A feedback oscillator amplifies its own noise and feeds
it back to itself in exactly the right phase, at the oscillation frequency, to build up and reinforce the desired
oscillations. Its ability to do that depends on its loop
gain. First, oscillations can occur only at the frequency
for which the loop gain has a phase angle of 0 degrees.
Second build-up of oscillations will occur only if the
loop gain exceeds 1 at the frequency. Build-up continues until nonlinearities in the circuit reduce the average
value of the loop gain to exactly 1.
Start-up characteristics depend on the small-signal
properties of the circuit, specifically, the small-signal
loop gain. Steady-state characteristics of the oscillator
depend on the'large-signal properties of the circuit,
such as the transfer curve (output voltage vs. input
voltage) of the amplifier, and the clamping effect of the
input protection devices. These things will be discussed
more fully further on. First we will look at the basic
operation of the particular oscillator circuit, called the
"positive reactance" oscillator.
The Positive Reactance Oscillator
Figure 2 shows the configuration of the positive reactance oscillator. The inverting amplifier, working into
the impedance of the feedback network, produces an
output signal that is nominally 180 degrees out of phase
with its input. The feedback network must provide an
additional 180 degrees phase shift, such that the overall
loop gain has zero (or 360) degrees phase shift at the
oscillation frequency.
where Xr is the reactance of Zr (the total Zr being Rr +
jXr, and C is the series combination of CXt and CX2.
C =
CXl CX2
CX1'+ CX2
In other words, Zr and C form a parallel resonant circuit.
If Zr is an inductor, then Xr = wL, and the frequency
at which the loop gain has zero phase is the frequency
at which
1
wL=-
wC
or
1
w = J[C
Normally, Zr is not an inductor, but it must still have a
positive reactance in order for the circuit to oscillate.
There are some piezoelectric devices on the market that
show a positive reactance, and provide a more stable
oscillation frequency than an inductor will. Quartz
crystals can be used where the oscillation frequency is
critical, and lower cost ceramic resonators can be used
where the frequency is less critical.
When the feedback element is a piezoelectric device,
this circuit configuration is called a Pierce oscillator.
The advantage of piezoelectric resonators lies in their
property of providing a wide range of positive reactance
values over a very narrow range of frequencies. The
reactance will equal 1/wC at some frequency within
this range, so the oscillation frequency will be within
the same range. Typically, the width of this range is
z"
ex.
230659-2
Figure 2. Positive Reactance Oscillator
9-25
AP-155
only 0.3% of the nominal frequency of a quartz crystal,
and about 3% of the nominal frequency of a ceramic
resonator. With relatively little design effort, frequency
accuracies of 0.03% or better can be obtained with
quartz crystals, and 0.3% or better with ceramic resonators.
QUARTZ CRYSTALS
The crystal resonator is a thin slice of quartz sandwiched between two electrodes. Electrically, the device
looks pretty much like a S' or 6 pF capacitor, except
that over certain ranges of frequencies the crystal has a
positive (i.e., inductive) reactance.
The ranges of positive reactance originate in the piezoelectric property of quartz: Squeezing the crystal generates an internal E-field. The effect is reversible: Applying an AC E-field, causes the crystal to vibrate. At certain vibrational frequencies there is a mechanical resonance. As the E-field frequency approaches a frequency
of mechanical resonance, the measured reactance of the
crystal becomes positive, as shown in Figure 3.
FREQUENCY
w
z
~o
0
0
'"
Crystal Parameters
Equivalent Circuit
Figure 4 shows an equivalent circuit that is used to
represent the crystal for circuit analysis.
The R,-L,-C, branch is called the motivational arm of
the crystal. The values of these parameters derive from
the mechanical properties of the crystal and are constant for a given mode of vibration. Typical values for
various nominal frequencies are shown in Table 1.
SPURIOUS
RESPONSES
-
JX
To assure that an oscillator starts in the desired mode
on power-up, something must be done to suppress the
loop gain in the undesired frequency ranges. The crystal itself provides some protection against unwanted
modes of oscillation; too much resistance in that mode,
for example. Additionally, junction capacitances in the
amplifying devices tend to reduce the gain at higher
frequencies, and thus may discriminate against unwanted modes. In some cases a circuit fix is necessary, such
as inserting a trap, a phase shifter, or ferrite beads to
kill oscillations in unwanted modes.
/
--'-IIO~I-
\
-r-b
W
II:
XeD
-JX
FUNDAMENTAL
/
-
SYMBOL
FIFTH MECHANICAL
OVERTONE
EQUIVALENT CIRCUIT
230659-4
THIRD MECHANICAL
OVERTONE
Figure 4. Quartz Crystal: Symbol and
Equivalent Circuit
230659-3
Figure 3. Crystal Reactance vs. Frequency
Typically there are several ranges of frequencies wherein the reactance of the crystal is positive. Each range
corresponds to a different mode of vibration in the crystal. The main resonsances are the so-called fundamental response and the third and fifth overtone responses.
Co is called the shunt capacitance of the crystal. This is
the capacitance of the crystal's electrodes and the mechanical holder. If one were to measure the reactance of
the crystal at a freuqency far removed from a resonance
frequency, it is the reactance of this capacitance that
'would be measured. It's normally 3 to 7 pF.
Table 1. Typical Crystal Parameters
The overtone responses shouldn't be confused with the
harmonics of the fundamental. They're not harmonics,
but different vibrational modes. They're not in general
at exact integer mUltiples of the fundamental frequency.
There will also be "spurious" responses, occurring typically a few hundred KHz above each main response.
9-26
Frequency
MHz
R1
ohms
L1
mH
C1
pF
2
100
520
0.012
4.608
36
117
0.010
2.9
11.25
19
8.38
0.024
5.4
,Co
pF
'4
intJ
AP-155
The series resonant frequency of the crystal is the frequency at which LI and CI are in resonance. This frequency is given by
.
the antiresonant frequency of the parallel combination
of the crystal and CL. This frequency is given by
1
1
f =--5
21T~L1C1
fa =
At this frequency the impedance of the crystal is R I in
parallel with the reactance of Co. For most purposes,
this impedance is taken to be just R I, since the reactance of Co is so much larger than RI.
::-21T-~r.L=1""C""1';;(C""L=+~C~0);=;/~(C<=1=+~C""L=:+=C""o""")
These frequency formulas are derived (in Appendix A)
from the equivalent circuit of the crystal, using the assumptions that the Q of the crystal is extremely high,
and that the circuit external to the crystal has no effect
on the frequency other than to provide the load capacitance CL. The latter assumption is not precisely true,
but it is close enough for present purposes.
Load Capacitance
A crystal oscillator circuit such as the one shown in
Figure 2 (redrawn in Figure 5) operates at the frequency for which the crystal is antiresonant (ie, parallel-resonant) with the total capacitance across the crystal terminals external to the crystal. This total capacitance
external to the crystal is called the load capacitance.
"Series" vs. "Parallel" Crystals
There is no such thing as a "series cut" crystal as opposed to a "parallel cut" crystal. There are different
cuts of crystal, having to do with the parameters of its
motional arm in various frequency ranges, but there is
no special cut for series or parallel operation.
As shown in Figure 5, the load capacitance is given by
The crystal manufacturer needs to know the value of
CL in order to adjust the crystal to the specified frequency.
cL
An oscillator is series resonant if the oscillation frequency is fs of the crystal. To operate the crystal at fs,
the amplifier has to be noninverting. When buying a
crystal for such an oscillator, one does not specify a
load capacitance. Rather, one specifies the loading condition as "series."
If a "series" crystal is put into an oscillator that has an
inverting amplifier, it will oscillate in parallel resonance
with the load capacitance presented to the crystal by
the oscillator circuit, at a frequency slightly above fs. In
fact, at approximately
r--------------------l I
! ----------~);~---------- ~
I
C.,
Cx>
I
lLI ____________________
'j
:t
)
i
JI
"::"
This frequency would typically be about 0.02% above
fs·
CRYSTAL
I---------~~---------~
II
R,
L,
C,
I
I
J
IL ___________________
" I
230659-6
Figure 5. Load Capacit.ance
The adjustment involves putting the crystal in series
with the specified CL, and then "trimming" the crystal
to obtain resonance of the series combination of the
crystal and CL at the specified frequency. Because of
the high Q of the crystal, the resonant frequency of the
series combination of the crystal and CL is the same as
Equivalent Series Resistance
The "series resistance" often listed on quartz crystal
data sheets is the real part of the crystal impedance at
the crystal's calibration frequency. This will be Rl if
the calibration frequency is the series resonant frequency of the crystal. If the crystal is calibrated for parallel
resonance with a load capacitance CL, the equivalent
series resistance will be
ESR = R1 ( 1
+ Co)2
CL
The crystal manufacturer measures this resistance at
the calibration frequency during the same operation in
which the crystal is adjusted to. the calibration frequency.
9-27
intJ
AP-155
Frequency Tolerance
Frequency tolerance as discussed here is not a requirement on the crystal, but on the complete oscillator.
There are two types of frequency tolerances on oscillators: frequency acccuracy and frequency stability. 'Frequency accuracy refers to the oscillator's ability to run
at an exact specified frequency. Frequency stability refers to the constancy of the oscillation frequency.
Frequency accuracy requires mainly that the osciJIator
circuit present to the crystal the same load capacitance
that it was adjusted for. Frequency stability requires
mainly that the load capacitance be constant.
In a positive reactance osciJIator, if one assumes the
peak voltage across the crystal to be something in the
neighborhood of Vee, the power dissipation can be approximated as
This formula is derived in Appendix A. In a 5V system,
P rarely evaluates to more than a milliwatt. Crystals
with a standard 1 or 2 mW drive level rating can be
used in most digital systems.
MT - Sl R3.S8M
In most digital applications the accuracy and stability
requirements on the oscillator are so wide that it makes
very little difference what load capacitance the crystal
was adjusted to, or what load capacitance the circuit
actually presents to the crystal. For example, if a crystal was calibrated to a load capacitance of 25 pF, and is
used in a circuit whose actual load capacitance is 50 pF,
the frequency error on,that account would be less than
0.01%.
100000
10
o
In a positive reactance oscillator, the crystal only needs
to be in the intended response mode for the oscillator to
satisfy a 0.5% or better frequency tolerance. That's because for any load capacitance the oscillation frequency
is certain to be between the crystal's resonant and antiresonant frequencies.
'
Phase shifts that take place within the amplifier part of
the oscillator will also affect frequency accuracy and
stability. These phase shifts can normally be modeled as
an "output capacitance" that, in the positive reactance
oscillator, parallels CX2. The predictability and constancy of this output capacitance over temperature and
device sample will be the limiting factor in determining
the tolerances that the circuit is capable of holding.
Drive Level
Drive level refers to the power dissipation in the crystal. There are two reasons for specifying it. One is that
the parameters in the equivalent circuit are somewhat
dependent on the drive level at which the crystal is
calibrated. The other is that if the application circuit
exceeds the test drive level by too much, the crystal
may be damaged. Note that the terms "test drive level"
and "rated drive level" both refer to the drive level at
which the crystal is calibrated. Normally, in a microcontroller system, neither the frequency tolerances nor
the power levels justify much concern for this specification. Some crystal manufacturers don't even require it
for microprocessor crystals.
2000
4000
6000
8000 10000
FREQUENCY (KHz)
230659-7
Figure 6. Ceramic Resonator Impedance vs.
Frequency (Test Data Supplied by NTK
Technical Ceramics)
CERAMIC RESONATORS
Ceramic resonators operate on the same basic principl~s as a quartz crsytal. Like quartz crsytals, they are
piezoelectric, have a reactance versus frequency curve
similar to a crystal's, and an equivalent circuit that
looks just like a crystal's (with different parameter values, however).
The frequency tolerance of a ceramic resonator is about
two orders of magnitude wider than a crystal's, but the
ceramic is somewhat_cheaper than a crystal. It may be
noted for comparison that quartz crystals with relaxed
tolerances cost about twice as much as ceramic resonators. For purposes of clocking a microcontroller, the
frequency tolerance is often relatively noncritical, and
the economic consideration becomes the dominant factor.
Figure 6 shows a graph of impedance magnitude versus
frequency for a 3.58 MHz ceramic resonator. (Note
that Figure 6 is a graph of IZrI versus frequency, where
9-28
inter
AP-155
as Figure 3 is a graph of Xr versus frequency.) A number of spurious responses are apparent in Figure 6. The
manufacturers state that spurious responses are more
prevalent in the lower frequency resonators (kHz
. range) than in the higher frequency units (MHz range).
For our purposes only the MHz range ceramics need to
be considered.
frequency and the chip you want it to work with.
They'll supply the resonators, a circuit diagram showing the positions and values of other external components that may be required and a guarantee that the
circuit will work properly at the specified frequency .
OSCILLATOR DESIGN
CONSIDERATIONS
----11011-- - SYMBOL
EQUIVALENT CIRCUIT
230659-8
Figure 7. Ceramic Resonator: Symbol and
Equivalent Circuit
Figure 7 shows the symbol and equivalent circuit for
the ceramic resonator, both of which are the same as
for the crystal. The parameters have different values,
however, as listed in Table 2.
Designers of microcontroller systems have a number of
options to choose from for clocking the system. The
main decision is whether to use the "on-chip" oscillator
or an external oscillator. If the choice is to use the onchip oscillator, what kinds of external components are
needed to make it operate as advertised? If the choice is
to use an external oscillator, what type of oscillator
should it be?
The decisions have to be based on both economic and
technical requirements. In this section we'll discuss
some of the factors that should be considered.
XTALI
l-~-"-'--l------'
~
CT
Table 2. Typical Ceramic Parameters
Frequency
MHz
3.58
6.0
8.0
11.0
R1
ohms
7
8
7
10
L1
mH
0.113
0.094
0.092
0.057
C1
pF
19.6
8.3
4.6
3.9
c X•
Co
pF
140
60
40
30
Note that the motional arm of the ceramic resonator
tends to have less resistance than the quartz crystal and
also a vastly reduced L!fC! ratio. This results in the
motional arm having a Q (given by (l/R!) ~L!fC!) that
is typically two orders of magnitude lower than that of
. a quartz crystal. The lower Q makes for a faster startup
of the oscilaltor and for a less closely controlled frequency (meaning that circuitry external to the resonator will have more influence on the frequency than with
a quartz crystal).
Another major difference is that the shunt capacitance
of the ceramic resonator is an order of magnitude higher than Co of the quartz crystal and more dependent on
the frequency of the resonator.
CD
XTAL2
~
y
______
230659-9
Figure 8. Using the "On-Chip" Oscillator
On-Chip Oscillators
In most cases, the on-chip amplifier with the appropriate external components provides the most economical
solution to the clocking problem. Exceptions may arise
in severe environments when frequency tolerances are
tighter than about 0.01 %.
The external components that need to be added are a
positive reactance "(normally a crystal or ceramic resonator) and the two capacitors CX! and CX2, as shown
in Figure 8.
Crystal Specifications
The implications of these differences are not all obvious, but some will be indicated in the section on Oscillator Calculations.
Specifications for an appropriate crystal are not very
critical, unless the frequency is. Any fundamental-mode
crystal of medium or better quality can be used.
Specifications for Ceramic Resonators
Ceramic resonators are easier to specify than quartz
crystals. All the vendor wants to know is the desired
9-29
inter
AP-155
We are often asked what maximum crystal resistance
should be specified. The best answer to this question is
the lower the better, but use what's available. The crystal resistance will have some effect on start-up time and
steady-state amplitude, but not so much that it can't be
compensated for by appropriate selection of the capacitances CX! and CX2.
Similar questions are asked about specifications of load
capacitance and shunt capacitance: The best advice we
can give is to understand what these parameters mean
and how they affect the operation of the circuit (that
being the purpose of this Application Note), and then
decide for yourself if such specifications are meaningful
in your application or not. Normally, they're not, unless your frequency tolerances are tighter than about
0.1%.
Part of the problem is that crystal manufacturers are
accustomed to talking "ppm" tolerances with radio engineers and simply won't take your order until you've
filled out their list, of specifications. It will help if you
define your actual frequencY tolerance requirements,
both for yourself and to the crystal manufacturer.
Don't pay for 0.003% crystals if your actual frequency
tolerance is 1%.
Oscillation Frequency
The oscillation frequency is determined 99.S% by the
crystal and up to about O.S% by the circuit external to
the crystal. The on-chip amplifier has little effect on the
frequency, which is as it should be, since the amplifier
parameters are temperature and process dependent.
The influence of the on-chip amplifier on the frequency
is by means of its input and output (pin-to-ground) capacitances, which parallel CX! and CX2, and the
XTALI-to-XTAL2 (pin-to-pin) capacitance, which
parallcIs thc cristal. Thc input and pin-to-pL"1 capacitances are about 7 pF each. Internal phase deviations
from the nominal 180' can be modeled as an olltput
capacitance of 2S to 30 pF. These deviations from the
ideal have less effect in the positive reactance oscillator
(with ,the inverting amplifer) than in a comparable series resonant oscillator (with the noninverting amplifier) for two reasons: first, the effect of the output capacitance is lessened, if not swamped, by the off-chip capacitor; secondly, the positive reactance oscillator is less
sensitive, frequency-wise, to such phase errors.
tor is being used, and also on application-specific requirements on start-up time and frequency tolerance.,
Start-up time is. sometimes more critical in microcontroller systems than frequency stability, because of various reset and initialization requirements.
Less commonly, accuracy of the oscillator frequency is
also critical, for example, when the oscillator is being
used as a time base. As a general rule, fast start-up and
stable frequency tend to pull the osciJIator design in
opposite directions.
Considerations of both start"up time and frequency stability over temperature suggest that CX! and CX2
should be about equal and at least 20 pF. (But they
don't have to be either.) Increasing the value of these
capacitances above some 40 or SO pF improves frequency stability. It also tends to increase the start-up time.
There is a maximum value (several hundred pF, depending on the value of R! of the quartz or ceramic
resonator) above which the oscillator won't start up at
all.
If the on-chip. amplifier is a simple inverter, such as in
the 80SI, the user can select values for Cx! and CX2
between some 20 and 100 pF, depending on whether
start-up time or frequency stability is the more critical
parameter in a specific application. If the on-chip amplifier is a Schmitt Trigger, such as in the 8048, smaller
values of CX! must be used (S to 30 pF), in order to
prevent the osciJIator from running in a relaxation
mode.
Later sections in this Application Note will discuss the
effects of varying CX! and CX2 (as well as other par~
eters), and will have more to say on their selection.
Placement of Components
Noise glitches arriving at XTALI or XTAL2 pins at
the wrong time can cause a miscount in the internal
cIock-generating circuitry. These kinds of glitches can
be produced through capacitive coupling between the
oscillator components and PCB traces carrying digital
signals with fast rise and fall times. For this reason, the
oscillator components should be mounted close to the
chip and have short, direct traces to the XTALI,
XTAL2, and VSS pins.
Clocking Other Chips
Selection of CX1 and CX2
There are times when it would be desirable to use the
on-chip oscillator to cIock other chips in the system.
Optimal vallies for the capacitors CX! and CX2 depend
on whether a quartz crystal or ceramic resona-
9-30
inter
AP-155
This can be done if an appropriate buffer is used. A
TTL buffer puts too much load on the on-chip amplifier for reliable start-up. A CMOS buffer (such as the
74HC04) can be used, if it's fast enough and if its VIH
and VIL specs are compatible with the available signal
amplitudes. Circuits such as shown in Figure 9 might
also be considered for these types of applications.
vcc
lK
CLOCK
OUT
11K
::i-......-'IN""1'-t--I XTAL2
Clock-related signals are available at the TO pin in the
MCS-48 products, at ALE in the MCS-48 and MCS-51
lines, and the iACX-96 controllers provide a CLKOUT
signal.
t - - - i l - -....- i XTALI
230659-10
A) DRIVING FROM XTAL2
vcc
lK
CLOCK
OUT
n~
C
':"
X2
External Oscillators
XTAL2
When technical requirements dictate the use of an external oscillator, the external drive requirements for the
microcontroller, as published in the data sheet, must be
carefully noted. The logic levels are not in general TTLcompatible. And each controller has its idiosyncracies
in this regard. The 8048, for example, requires that
both XTALl and XTAL2 be driven. The 8051 can be
driven that way, but the data sheet suggest the simpler
method of grounding XTALI and driving XTAL2. For
this method, the driving source must be capable of sinking some current when XTAL2 is being driven low.
0
XTALI
CXI
230659-11
B) DRIVING FROM XTAL 1
Figure 9. Using the On-Chip Oscillator
to Drive Other Chips
For the external oscillator itself, there are basically two
choices: ready-made and home-grown.
9-31
inter
AP-155
Frequency Tolerance: ± 0.1 % Overall O·C- 700C
TTL Crystal Clock Oscillator
The HS-l00, HS-200, & HS-500 all-metal package series of oscillators are TTL compatible & fit a DIP
layout. Standard electrical specifications are shown
below. Variations are available for special applications.
Frequency Range: HS-l00--3.5 MHz to 30 MHz
HS-200--225 KHz to 3.5 MHz
HS-500-25 MHz to 60 MHz
Hermetically Sealed Package
Mass spectrometer leak rate max.
1 X 10- 8 atmos. cc/sec. of helium
-
-
'.
Output Waveform
'I-
-,r.-
-F=t
----
::.... ----
~
60% Max
~~
- - - - ---2.4 VDC
---
___
----1,4
vec
_ ___ 0,4 VDC
--VOL
,ovec
230659-12
INPUT'
HS-100
Supply Voltage
(Vcel
Supply Current
(Icel max.
HS-200
HS-500
3.5 MHz-20 MHz
20 + MHz-30 MHz
225 KHz-4.0 MHz
25 MHz-60 MHz
5V ±10%
5V ±10%
5V ±10%
5V ±10%
30mA
40mA
85mA
50mA
HS-200
HS-500
OUTPUT
HS-100
VOH (Logic "1 ")
VOL (Logic "0")
Symmetry
TR, TF (Rise &
Fall Time)
Output Short
Circuit Current
Output Load
3.5 MHz-20 MHz
20 + MHz-30 MHz
225 KHz-4.0 MHz
25 MHz-60 MHz
+2.4Vmin.l
+O.4V max. 3
60/40%5
+2.7Vmin.2
+0.5Vmax.4
60/40%5
+2.4V min. 1
+O.4V max. 3
55/45%5
+2.7Vmin.2
+0.5Vmax. 4
60/40%5
< 10 ns6
< 5.ns6
< 15 ns6
< 5 ns6
18 mA min.
1 to 10 TTL Loads7
40 mA min.
1 to 10 TTL Loads8
18 mA min.
1 to 10 TTL Loads7
40mAmin.
1 to 10 TTL Loads8
CONDITIONS
110 source = - 400 /LA max.
210 source = -1.0 mA max.
310 sink = 16.0 mA max.
410 sink = 20.00 mA max.
5Vo = 1.4V
6(0.4V to 2.4V)
71.6 mA per load
82.0 mA per load
Figure 10. Pre-Packaged Oscillator Data"
,"Reprinted with the permission of @Midland·Ross Corporation 1982.
9-32
inter
AP-155
Prepackaged oscillators are available from most crystal
manufacturers, and have the advantage that the system
designer can treat the oscillator as a black box whose
performance is guaranteed by people who carry many
years of experience in designing and building oscillators. Figure 10 shows a typical data sheet for some
prepackaged oscillators. Oscillators are also available
with complementary outputs.
The feedback resistance has to be quite low, however,
since it must conduct current sourced by the input pin
without allowing the DC input voltage to get too far
above the DC output voltage. For biasing purposes, the
feedback resistance should not exceed a few k-ohms.
But shunting the crystal with such a low resistance does
not encourage start-up.
If the oscillator is to drive the microcontroller directly,
lK
one will want to make a careful !!omparison between
the external drive requirements in the microcontroller
data sheet and the oscillator's output logic levels and
test conditions.
lK
1.
01 1"
74LS04
OUTPUT
If oscillator stability is less critical than cost, the user
may prefer to go with an in-house design. Not without
some precautions, however.
o
It's easy to design oscillators that work. Almost all of
them do work, even if the designer isn't too clear on
why. The key point here is that almost all of them
work. The problems begin when the system goes into
production, and marginal units commence malfunctioning in the field. Most digital designers, after all, are
not very adept at designing oscillators for production.
Rx
(SEVERAL kn)
230659-13
A) TTL OSCILLATOR
lMII
74C04
OUTPUT
Oscillator design is somewhat of a black art, with the
quality of the finished product being very dependent on
the designer's experience and intuition. For that reason
the most important consideration in any design is to
have an adequate preproduction test program. Preproduction tests are discussed later in this Application
Note. Here we will discuss some of the design options
and take a look at some commonly used configurations.
Gate Oscillators versus Discrete
Devices
Digital systems designers are understandably reluctant
to get involved with discrete devices and their peculiarities (biasing techniques, etc.). Besides, the component
count for these circuits tends to be quite a bit higher
than what a digital designer is used to seeing for that
amount of functionality. Nevertheless, if there are unusual requirements on the accuracy and'stability of the
clock frequency, it should be noted that discrete device
oscillators can be tailored to suit the exact needs of the
application and perfected to a level that would be difficult for a gate oscillator to approach.
In most cases, when an external oscillator is needed, the
designer tends to rely on some form of a gate oscillator.
A TTL inverter with a resistor connecting the output to
the input makes a suitable inverting amplifier. The resistor holds the inverter in the transition region between logical high and low, so that at least for start-up
purposes the inverter is a linear amplifier.
o
Rx
(SEVERAL kn)
230659-14
B) CMOS OSCILLATOR
Figure 11. Commonly Used Gate Oscillators
Consequently, the configuration in Figure IIA might
be suggested. By breaking Rr into two parts and ACgrounding the midpoint, one achieves the DC feedback
required to hold the inverter in its active region, but
without the negative signal feedback that is in effect
telling the circuit not to oscillate. However, this biasing
scheme will increase the start-up time, and relaxationtype oscillations are also possible.
A CMOS inverter, such as the 74HC04, might work
better in this application, since a larger Rr can be used
to hold the inverter in its linear region.
Logic gates tend to have a fairly low output resistance,
which destabilizes the oscillator. For that reason a resistor Rx is often added to the feedback network, as
shown in Figures llA and B. At higher frequencies a
20 or 30 pF capacitor is sometimes used in the Rx position, to compensate for some of the internal propagation delay.
Reference 1 contains an excellent discussion of gate oscillators, and a number of design examples.
9-33
inter
AP-155
Fundamental versus Overtone Operation
1K
It's easier to design an oscillator circuit to operate in
the resonator's fundamental response mode than to design one for overtone operation. A quartz crystal whose
fundamental response mode covers the desired frequency can be obtained up to some 30 MHz. For frequencies
above that, the crystal might be used in an overtone
mode.
Several problems arise in the design of an overtone oscillator. One is to stop the circuit from oscillating in the
fundamental mode, which is what it would really rather
do, for a number of reasons, involving both the amplifying device and the crystal. An additional problem with
overtone operation is an increased tendency to spurious
oscillations. That is because the R 1 of various spurious
modes is likely to be about the same as R1 of the intended overtone response. It may be necessary, as suggested in Reference 1, to specify a "spurious-to-mainresponse" resistance ratio to avoid the possibility of
trouble.
Overtone oscillators are not to be taken lightly. One
would be well advised to consult with an engineer who
is knowledgeable in the subject during the design phase
of such a circuit.
Series versus Parallel Operation
Series resonant oscillators use noninverting amplifiers.
To make a noninverting amplifier out of logic gates
requires that two inverters be used, as shown in Figure
12.
1K
B,I-----"
230659-15
Figure 12. "Series Resonant" Gate Oscillator
Positive reactance oscillators ("parallel resonant") use
inverting amplifiers. A single logic inverter can be used
for the amplifier, as in Figure 11. The amplifier's phase
shift is less critical, compared to a series resonant circuit, and since only one inverter is involved there's less
phase error anyway. The oscillation frequency is effectively bounded by the resonant and antiresonant frequencies of the crystal itself. In addition, the feedback
network includes capacitors that parallel the input and
output terminals of the amplifier, thus reducing the effect of unpredictable capacitances at these points.
MORE ABOUT USING THE "ON-CHIP"
OSCILLATORS
In this section we will describe the on-chip inverters on
selected microcontrollers in some detail, and discuss
criteria for selecting components to work with them.
Future data sheets will supplement this discussion with
updates and information pertinent to the use of each
chip's oscillator circuitry.
.
This type of circuit tends to be inaccurate and unstable
in frequency over variations in temperature and Vee. It
has a tendency to oscillate at overtones, and to oscillate
throl!gh Co of the crystal or some stray capacitance
rather than as controlled by the mechanical resonance
of the crystal.
The demon in series resonant oscillators is the phase
shift in the amplifier. The series resonant oscillator
wants more than just a "noninverting" amplifier-it
wants a zero phase-shift amplifier. Multistage noninverting amplifiers tend to have a considerably lagging
phase shift, such that the crystal reactance must be capacitive in order to bring the total phase shift around
the feedback loop back up to O. In this mode, a "12
MHz" crystal may be running at 8 or 9 MHz. One can
put a capacitor in series with the crystal to relieve the
crystal of having to produce all of the required phase
shift, and bring the oscillation frequency closer to fs.
However, to further complicate the situation, the amplifier's phase shift is strongly dependent on frequency,
temperature, VCC, and device sample.
Oscillator Calculations
Oscillator design, though aided by theory, is still largely
an empirical exercise. The circuit is inherently nonlinear, and the normal analysis parameters vary with instantaneous voltage. In addition, when dealing with the
on-chip circuitry, we have FETs being used as resistors,
resistors being used as interconnects, distributed delays,
input protection devices, parasitic junctions, and processing variations.
Consequently, oscillator calculations are never very
precise. They can be useful, however, if they will at
least indicate the effects of variations in the circuit parameters on start-up time, oscillation frequency, and
steady-state amplitude. Start-up time,' for example, can
be taken as an indication of start-up reliability. If preproduction tests indicate a possible start-up problem, a
relatively inexperienced designer can at least be made
aware of what parameter may be causing the marginality, and what direction to go in to fix it.
9-34
AP-155
VCC
PHASE
100·.1:---_ _
50·
F, MHz
~+------+------~------;-~
4.607
XTAL2
XTAL1
230659-16
A) BOB1-Type Circuit Configuration during Start-Up.
(Excludes Input Protection Devices.)
~
MAGNITUDE
20
15
r------------,
~ r---------,I II
z, ..............JI
l
I
_...,..;
Ro
I I
I
I
I
I
I
I
10
I
II
R,
I:
_J
I
L_
I c..
4.609
-50·
Z'-......rI
I
L._
F, MHz
I
I
---t,
CXt
I
---;I
L.
I _____________ ..JI
O+-____-+______
i
4.606
1
4.607
~~--~~~
4.608
1-1kHz-J
4.609
230659-18
Figure 14. Loop Gain versus Frequency
(4.608 MHz Crystal)
230659-17
B) AC-Equlvalent of (A)
The gain of the feedback network is
Figure 13. Oscillator Circuit Model Used
in Start-Up Calculations
The analysis used here is mathematically straightforward but algebraically intractable. That means it's relatively easy to understand and program into a computer,
but it will not yield a neat formula that gives, say,
steady-state amplitude as a function of this or that .list
of parameters. A listing of a BASIC program that Implements the analysis will be found in Appendix II.
When the circuit is first powered up, and before the
oscillations have commenced (and if the oscillations/ail
to commence), the oscillator can be treated as a small
signal linear amplifier with feedback. In that case, standard small-signal analysis techniques can be used to
determine start-up characteristics. The circuit model
used in this analysis is shown in Figure 13.
The circuit approximates that there are no high-frequency effects within the amplifier itslef, such that. its
high-frequency behavior is dominated by the load Impedance ZL. This is a reasonable app.roximation for s~n
gle-stage amplifiers of the type used m 805 I-type deVICes: Then the gain of the amplifier as a function of frequency is
Zi
{3=--
Zi
+ ZI
And the loop gain is
Zi
AvZL
{3A=--X--Zi + ZI ZL + Ro
The impedances ZL, Zr, and Zj are defined in Figure
13B.
Figure 14 shows the way the loop gain thus calculated
(using typical 805 I-type parameters and a 4.60~ MHz
crystal) varies with frequency. The frequency ?f ~nterest
is the one for which the phase of the loop gam IS zero.
The accepted criterion for start-up is that the magnitude of the loop gain must exceed unity at this frequency. This is the frequency at which the circuit is in resonance. It corresponds very closely with the antiresonant
frequency of the motional arm of the crystal in parallel
with CL.
Figure IS shows the way the loop gain varies with frequency when the parameters of a 3.58 MHz cera.mic
resonator are used in place of a crystal (the amphfier
parameters being typical 8051, as in Figure 14). Note
the different frequency scales.
9-35
inter
AP·155
...
~
PHASE
X
s-pllne
-I
"
X
230659-20
A) Poles In Ihe Left-Half Plane: f(l) - e- at sin (",I + 9)
-50'
s-pllne
J...
X
+1 "
X
230659-21
B) Poles In Ihe Righi-Half Plane: f(l) - e+ at sin (",I + 9)
f\f\f\f\f\~
VV VlJ'
230659-19
230659-22
Figure 15. Loop Gain versus Frequency
(3.58 MHz Ceramic)
Start-Up Characteristics
It is common, in studies of feedback systems, to exam-
ine the behavior of the closed loop gain as a function of
complex frequency s = 0" + jw; specifically, to determine the location of its poles in the complex. plane. A
pole is a point on the complex plane where the gain
function goes to infinity. Knowledge of its location can
be used to predict the response of the system to an
input disturbance.
The way that the response function depends on the iocation of the poles is shown in Figure 16. Poles in the
left-half plane cause the response function to take the
form of a damped sinusoid. Poles in the right-half plane
cause the response function to take the form of an exponentially growing sinusoid.·In general,
v(t) - ea1 sin (wt + 6)
where a is the real part of the pole frequency. Thus if
the pole is in the right-half plane, a is positive and ti).e
sinusoid grows. If the pole is in the left-half plane, a is
negative and the sinusoid is damped.
The same type of analysis can usefuJly be applied to
oscillators. In this case, however, rather than trying to
ensure that the poles are in the .left-half plane, we
would seek to ensure that they're in the right-half plane.
An exponentially growing· sinusoid is exactly what is
wanted from an oscillator that has just been powered
up.
.
C) Poles Ihe J", Axis: f(l) - sin (",I
+ 9)
Figure 16. Do You Know Where Your
Poles Are Tonight?
The gain function of interest in oscillators is 1/(1 {3A). Its poles are at the complex frequencies where {3A
= lLO", because that value of {3A causes the gain function to go to infinity. The oscillator will start up if the
real part of the pole frequency is positive. More jmportantly, the rate at which it starts up is indicated by how
much greater than 0 the real part of the pole frequency
is.
The circuit in Figure 13B can be used to find the pole
frcqucncics of the oscillator gain function. All that
needs to be done is evaluate the impedances at complex
frequencies 0" + jw rather than just at w, and find the
value of 0" + jw for which {3A = lLO°.. The larger that
value of 0" is, the faster the oscillator will start up.
Of course, other things besides pole frequencies, things
like the VCC rise time, are at work in determining the
start-up time. But to the extend that the pole frequencies do affect start-up time, we can obtain results like
those in Figures 17 and 18.
To obtain these figures the pole frequencies were computed for various values of capacitance Cx from
XTALl and XTAL2 to ground (thus eX! = CX2 =
Cx). Then a "time constant" for start-up was calculat1
ed as Ts = - where 0" is the real part of the pole fre0"
quency (rad/sec), and this time constant is plotted versus Cx.
9-36
AP-155
As previously mentioned, start-up time can be taken as
an indication of start-up reliability. Start-up problems
are normally associated with Cx I and CX2 being too
small or too large for a given resonator. If the parameters of the resonator are known, curves such as in Figure 17 or 18 can be generated to define acceptable
ranges of values for these capacitors .
Ta. MILLISECONDS
.5
.4
.3
.2
.1
Cx• pF
10
30
50
70
--
t
~
III
I
!= ~
\
1\.
90
-
110
As the oscillations grow in amplitude, they reach a level at which they undergo severe clipping within the amplifier, in effect reducing the amplifier gain. As the amplifier gain decreases, the poles move towards the jw
axis. In steady-state, the poles are on the jw axis and
the amplitude of the oscillations is constant.
230659-23
T•• ,.SEC
C
50
30
......,
•
Cx-pF
10
OL--+__-+__
40
230659-24
60
80
~
__
100
__-+___
140
160
+-~
120
-
vcc:
I
X2:
I
n' .
,
III""""
X2:
-~
I
A short time constant means faster start-up. A long
time constant means slow start-up. Observations of actual start-ups are shown in the figures. Figure 17 is for
a typical 8051 with a 4.608 MHz crystal supplied by
Standard Crystal Corp., and Figure 18 is for a typical
8051 with a 3.58 MHz ceramic resonator supplied by
NTK Technical Ceramics, Ltd.
u!
n'
X2:
IIIIIIII
•
- --
230659-27
L..;.J
Ii
I.
~I
I
("I
It can be seen in Figure 17 that, for this crystal, values
of Cx between 30 and 50 pF minimize start-up time,
but that the exact value in this range is not particularly
important, even if the start-up time itself is critical.
--
I
... . . .. i...
alii
230659-25
Figure 17. Oscillator Start-Up (4.608 MHz Crystal
from Standard Crystal Corp.)
&...; :.I
/'
I
1:')
-
230659-26
•
- --
2 30659-28
Figure 18. Oscillator Start-Up (3.58 MHz Ceramic
Resonator from NTK Technical Ceramics)
9-37
inter
AP-155
VOLTS
o
1c~.
-=
XTAL2
8051
XTALI
C.
•
2
20 40 60
80 100 120 140
·160 180 200 220
-1
Ca-pF
-2
230659-29
A) Signal Levels at XTAL 1
VOLTS
• .xperlmenlal
point.
• •
VOL II XTAL2
o~~++-.~~~~~~
20 40
80
80 100 120 140 180 180 200 220
-1
230659-30
S,) Signal Levels at XTAL2
Figure 19. Calculated and Experimental SteadyState Amplitudes vs. Bulk Capacitance from
XTAL 1 and XTAL2 to Ground
Steady~State
Characteristics
Steady-state analysis is greatly complicated by the fact
that we are dealing with large signals and nonlinear
circuit response. The circuit parameters vary with instantaneous voltage, and a number of clamping and
clipping mechanisms come into play. Analyses that
take all these things into account are too complicated to
be of general use, and analyses that don't take them
into account are too inaccurate to justify the effort.
There is a steady-state analysis in Appendix B that
takes some of the complications into account and ignores others. Figure 19 shows the way the steady-state
amplitudes thus calculated (using typical 8051 parameters and a 4.608 'MHz crystal) vary with equal bulk
capacitance placed from XTAL1 and XTAL2 to
ground. Experimental results are shown for comparison.
The waveform at XTAL1 is a fairly clean sinusoid. Its
negative peak is normally somewhat below zero, at a
level which is determined mainly by the input protection circuitry at XTAL 1.
The input protection circuitry consists of an ohmic resistor and an enhancement-mode FET with the gate
and source connected to ground (VSS), as shown in
Figure 20 for the 8051, and in Figure 21 for the 8048.
Its function is to limit the positive voltage at the gate of
the input PET to the avalanche voltage of the drain
junction. If the input pin is driven below VSS, the drain ,
and source of the protection FET interchange roles, so
its gate is connected to what is now the drain. In this
condition the device resembles a diode with the anode
connected to VSS.
There is a parasitic pn junction between the ohmic resistor and the substrate. In the ROM parts (8015,8048,
etc.) the substrate is held at approximately - 3V by the
on-chip back-bias generator. In the EPROM parts
(8751, 8748, etc.) the substrate is connected to VSS.
The effect of the input protection circuitry on the oscillator is that if the XTALl signal goes negative, its nega~
tive peak is clamped to - VDS of the protection FET in
the ROM parts, and to about -0.5V in the EPROM
parts. These negative voltages on XTAL1 are in this
application self-limiting and nondestructive.
The clamping action does, however, raise the DC level
at XTALI, which in tum tends to reduce the positive
peak at XTAL2. The waveform at XTAL2 resembles a
sinusoid riding on a DC level, and whose negative
peaks are clipped off at zero.
Since it's normally the XTAL2 signal that drives the
internal clocking circuitry, the question naturally arises
as to how large this signal must be to reliably do its job.
In fact, the XTAL2 signal doesn't have, to meet the
same VIH and VIL specifications that an external driver would have to. That's because as long as the oscillator is working, the on-chip amplifier is driving itself
through its own O-to-I transition region, which is very
nearly the same as the 0-to-1 transition region in the
internal buffer that follows the oscillator. If some processing variations move the transition level higher or
lower, the on-chip amplifier tends to compensate for it
by the fact that its own transition level is correspondingly higher or lower: (In the 8096, it's the XTAL1
signal that drives the internal clocking circuitry, but the
same concept applies.)
The main concern about the XTAL2 signal amplitude
is an indication of the general health of tile oscillator.
An amplitude of less than about 2.SV peak-to-peak indicates that start-up problems could develop in some
units (with low gain) with some crystals (with high,RI)'
The remedy is to either adjust the values of CXI and/or
CX2 or use a crystal with a lower R I.
The amplitudes at XTALl and XTAL2 can be adjusted
by changing the ratio of the capacitors from XTALl
and XTAL2 to ground. Increasing the XTAL2 capaci~
tance, for example, decreases the amplitude at XTAL2
and increases the amplitude at XTALl by about the
same amount. Decreasing both caps increases both amplitudes.
9-38
AP-155
used than those which minimize start-up time. Larger
values than those can be used in applications where
increased frequency stability is desired, at some sacrifice in start-up time.
Pin Capacitance
Internal pin-to-ground and pin-to-pin capacitances at
XTALl and XTAL2 will have some effect on the oscillator. These capacitances are normally taken to be in
the range of 5 to 10 pF, but they are extremely difficult
to evaluate. Any measurement of one such capacitance
will necessarily include effects from the others. One advantage of the positive reactance oscillator is that the
. pin-to-ground capacitances are paralleled by external
bulk capacitors, so a precise determination of their value is unnecessary. We would suggest that there is little
justification for more precision than to assign them a
value of 7 pF (XTALl-to-ground and XTALl-toXTAL2). This value is probably not in error by more
than 3 or 4 pF.
.
Standard Crystal Corp. (Reference 8) studied the use of
their crystals with the MCS-51 family using skew sample supplied by Intel. They suggest putting 30 pF capacitors from XTALl and XTAL2 to ground, if the
crystal is specified as described in Reference 8. They
noted that in that configuration and with crystals thus
specified, the frequency accuracy was ± 0.01 % and the
frequency stability was ±0.005%, and that a frequency
accuracy of ±0.005% could be obtained by substituting a 25 pF fixed cap in parallel with a 5-20 pF trimmer for one of the 30 pF caps.
The XTAL2-to-ground capacitance is not entirely "pin
capacitance," but more like an "equivalent output capacitance" of some 25 to 30 pF, having to include the
effect of internal phase delays. This value will vary to
some extent with temperature, processing, and frequency.
MCS-51 skew samples have also been supplied to a
number of ceramic resonator manufacturers for characterization with their products. These companies should
be contacted for application information on their products. In general, however, ceramics tend to want somewhat larger values for CX! and CX2 than quartz crystals do. As shown in Figure 18, they start up a lot faster
that way.
MCS®-51 Oscillator
In some application the actual frequency tolerance required is only I % or so, the user being concerned mainly that the circuit will oscillate. In that case, CX! and
CX2 can be selected rather freely in the range of 20 to
80 pF.
The on-chip amplifier on the HMOS MCS-51 family is
shown in Figure 20. The drain load and feedback "resistors" are seen to be field-effect transistors. The drain
load FET, RD, is typically equivalent to about IK to 3
K-ohms. As an amplifier, the low frequency voltage
gain is normally between -10 and - 20, and the output resistance is effectively RD.
As you can see, "best" values for these components and
their tolerances are strongly dependent on the application and its requirements. In any case, their suitability
should be verified by environmental testing before the
design is submitted to production.
vec
MCS®-48 Oscillator
TO INTERNAL
CIRCUITRY
The NMOS and HMOS MCS-48 oscillator is shown in
Figure 21. It differs from the 8051 in that its inverting
VCC
XTAL2
230659-31
TO INTERNAL
CIRCUITRY
Figure 20. MCS®-51 Oscillator Amplifier
The 80151 oscillator is normally used with equal bulk
capacitors placed externally from XTALI to ground
and from XTAL2 to ground. To determine a reasonable value of capacitance to use in these positions, given
a crystal of ceramic resonator of known parameters,
one can use the BASIC analysis in Appendix II to generate curves such as in Figures 17 and 18. This procedure will define a range of values that will minimize
start-up time. We don't suggest that smaller values be
XTAL2
230659-32
Figure 21. MCS®-48 Oscillator Amplifier
9-39
inter
AP-155
more slowly, but it eventually takes over and dominates
the operation of the cirucit. This is shown in Figure
23A.
~hY.tere.l.
SV
.2V
L-_ _-+_ _-+_ _ _ _
LTP
v,
Due to processing variations, some units seem to have a
harder time coming out of the relaxation mode, particularly at low temperatures. In some cases the resonator
oscillations may fail entirely, and leave the device in the
relaxation mode. Most units will stick in the relaxation
mode at any temperature if CX! is larger than about 50
pF. Therefore, Cx! should be chosen with some care,
particularly if the system must operate at lower temperatures.
UTP
230659-33
Figure 22. Schmitt Trigger Characteristic
amplifier is a Schmitt Trigger. This configuration was
chosen to prevent crosstalk from the TO pin, which is
adjacent to the XTALl pin.
All Schmitt Trigger circuits exhibit a hysteresis effect,
as shown in Figure 22. The hysteresis is what makes it
less sensitive to noise. The same hysteresis allows any
Schl11itt Trigger to be used as a relaxation oscillator.
All you have to do is connect a resistor from output to
input, and a capacitor from input to ground, and the
circuit oscillates in a relaxation mode as follows.
If the Schmitt Trigger output is at a logic high, the
capacitor commences charging through the feedback
resistor. When the capacitor voltage reaches the upper
trigger point (UTP), the Schmitt Trigger output
switches to a logic low and the capacitor commences
discharging through the same resistor. When the capacitor voltage reaches the lower trigger point (LTP), the
Schmitt Trigger output switches to a logic high again,
and the sequence repeats. The oscillation frequency is
determined by the RC time constant and the hysteresis
voltage, UTP-LTP.
The 8048 can oscillate in this mode. It has an internal
feedback resistor. All that's needed is an external capacitor from XTALI to ground. In fact, if a smaller
external feedback resistor is added, an 8048 system
could be designed to run in this mode. Do it at your own
risk! This mode of operation is not tested, specified,
documented, or encouraged in any way by Intel for the
8048. Future steppings of the device might have a different type of inverting amplifier (one more like the
8051). The CHMOS members of the MCS-48 family do
not use a Schmitt Trigger as the inverting amplifier.
Relaxation oscillations in the 8048 must be avoided,
and this is the major objective in selecting the off-chip
components needed to complete the oscillator circuit.
When an 8048 is powered up, if VCC has a short rise
time, the relaxation mode starts first. The frequency is
normally about 50 KHz. The resonator mode builds
One method that has proven effective in all units to
-40·C is to put 5 pF from XTALl to ground and 20
pF from XTAL2 to ground. Unfortunately, while this
method does discourage the relaxation mode, it is not
an optimal choice for the resonator mode. For one
thing, it does not swamp the pin capacitance. Also, it
makes for a rather high signal level at XTALl (8 or 9
volts peak-to-peak).
The question arises as to whether that level of signal at
XTLAI might damage the chip. Not to worry. The
negative peaks are self-limiting and nondestructive. The
positive peaks could conceivably damage the oxide, but
in fact, NMOS chips (eg, 8048) and HMOS chips (eg,
8048H) are tested. to a much higher \2 AND VO=5 AND VI':2 THEN ~ETURN
13700
vo
13800
13900
14000
14100
14200
IF VO:>5 THEN VO = 5
IF VO<.2 THEN VO = .2
IF IC7I:>2 AND VO:>2 THEN VO = 5
RETURN
REM
14300 REM
14400
14500
141>00
14700
14800
14900
15000
15100
15200
15300
15400
15500
151>00
-IO-VI +
D
1~
.*•••••••••••••••••••• **** •••••••••••••••••••••••••••••• **** ••
REM
REM
DEFINE CIRCUIT PARAMETERS
REM
INPUT" RI 10HMS) ", RI
INPUT " Ll IHENRn", LI
INPUT" Cl IPF)", X
C1 • X-IE-10!
1
INPUT" CO IPF)",X
CO
X*IE-12
INPUT" CXTALI IPF)", X
CX = X-1E-12
INPUT" CXTAL2 (PF)", X
CV = X*IE-12
=
230659-45
9-49
inter
1~700
15800
15900
16000
16100
16200
16300
16400
16500
16600
16700
16800
16'100
,17000
17100
17200
17300
17400
17500
17600
17700
17800
17900
18000
18100
18200
18300
18400
18500
18600
18700
18800
18900
19000
19100
19200
19300
19400
19500
19600
19700
19800
19900
20000
20100
20200
20300
20400
20500
20600
20700
20800
20900
21000
21100
21200
21300
21400
21500
21600
21700
21800
21900
22000
22100
22200
22300
22400
22500
22600
22700
22800
22900
23000
23100
23200
23300
23400
Ap·155
INPUT" GAIN FACTOR MAGNITUDE". AVtI
INPUT" AMP F~EDBACK RESISTANCE (K-OHMS)".X
RX = ~*IOOOtl
INPUT" AMP OUTPUT RESISTANCE (K-OHMS)". X
RO = X*IOOOtl
REM
REM
REM
LtSt CURRENT PARAMETER VALUES
GOSUB 17100
RETURN
REf1
REf1
REM
***********~ •• ******.*~****~*4*4*.~*****.***.********* ********
REf1
LIST CURHENT PARAMETER. VALUES
RE''i
REM
PRINT
RI
". R I." OHMS"
PRINT "CURRENT PARAMETER VALUES
LI = ".CSNGCLI)." HENRV"
PRINT
2
CI
".CSNG(CI*IE+12)." PF"
PRINT"
3
4
CO
". CSNGCCO*IE+12)." PF"
PRINT"
PRINT
5 CXTALI '= ". CSNG(CX*IE+12)." PF"
6
CXTAL2 = ".CSNG(CY*IE+12)." PF"
PRINT "
AMPLIFIER GAIN MAGNITUDE
".AVtI
PRINT
7
PRINT"
FEEDBAC~ RESISTANCE = ". CSNG(RX* 001)." K-OHMS"
8.
OUTPUT RESISTANCE = ".CSNG(RO*.OOI)." K-OHMS"
PRINT "
'I
PRINT
PRINT "TO CHANGE A PARAMETER VALUE. TYPE CPARAM NO ). (NEW VALUE) "
PRINT "OTHERWISE. TVPE 0.0 "
INPUT N'l..X
IF N'l.=O THEN RETURN
IF N'l.=1 THEN Rl
X
IF N'l.=2 THEN L1
X
IF N'l.=3 THEN CI
X*IE-12
IF N'l.=4 THEN CO
X*lE-12
IF N'l.=5 THEN ex
X*lE-12
IF N'l.=6 THEN CV
X*lE-12
IF N'l.=7 THEN AVtI = X
IF N'l.=8 THEN RX
X-1000'
IF N'l.=9 THEN RO = X*IOOO'
GOTO 17400
REM
REM
REM **************************************************************
REM
REM
REM
REM
REM
REM
REM
XI =
RE
XE =
REM
REM
REM
RF =
XF
REM
REM
REM
RI ,=
XI =
REM
REM
REM
RL =
XL ..
REM
REM
REM
REM
ARtI
=
=
CIRCUIT ANALYSIS
This routln.
Crystal
calculate~
l~pedance
the loop gain at compl •• frequency SO+JFB.
RE + JXE
FNXL(FG.LI) + FNXC(SO.FG.CIl
FNRP«Rl+FNRL(SO.LI)+FNRC(SO.FO.CI».XI.FNRC(sO.FO.CO).FNXC(sG.FO.CO»
FNXP«RI+FNRL(sO.LI)+FNRC(sQ.FG.CI».XI.FNRC(sO.FO.CO).FNXC(sO.FO.CO»
2,
RF + JXF
(RE+JXE): :(ampllfler feedback
resistance)
FNRP(RX.O.RE.XE)
FNXP(RX.O.RE,XE)
3.
Input
lmpedanc~.
lmpedance of CXTALI
RI + JXI
II
FNRC (SO. FO. C")
FNXC (SO. FO. C ,< )
4
Load
Impedance
ZL =
(Impedance of CX'TAL2): :[(RF+RI)+J(XF+XI))
FNRP( (RF+RI), (XF+X I). FNRC (SQ, Ft]. CY>. FNXC (SQ. FO. CY»
FNXP«IlF+RI . (XF+Xll.FNRC(SQ,r·(J,Cy),F'NXC(SO.FO.CY»
5
Ampll'leT gain
A =
-AV*ZL/IZL~PO)
+ JAtlmaglna,.y~
::: A.reali
AI_ =
-AV_~FNXP(RL,XLJ
CPU.RL),'L)
REM
REM
REM
6
Feedbat~
ratIo
~~~ta~
IRJ+J~J)!r(RF.Rll.j(XF+XI)]
Birt!'al'
..,.
JBClmaqlndry)
230659-46
9-50
intJ
23500
23600
23700
23800
23900
24000
24100
24200
24300
24400
24500
24600
24700
24800
24900
25000
25100
25200
25300
25400
25500
25600
25700
25800
25900
26000
26100
AP-155
REM
BI'll = FNRRCRI,XI, IRI+RF), (XI+XF)l
Bill = FNXR(RI. XI, IRI+RF1. (X/+XF»
REM
REM 7 Ampllfler galn 11, magnItude/phase form
REM
A = FNZMCARII,AIII)
AP = FNZPCARII,AI~)
REM
REM 8
(beta) In magnitude/phase form BP+JBI
REM
a = FNZM(BRII,BI~)
3P = FNZp(aRII,BI~)
REM
REM 9 Loop galn G = (BR+JBI).rAR+JAI)
REM
~ G(real) + JG(lmaglnar~)
REI1
GR = FNRM(ARII,AIII,BRII,BIII)
GI = FNXMCARII, AIII,BRII, Bill)
REM
REM 10 Loop 931n 1n magnitud9/phase form
REM
AL = FNZMtGR,GI)
AO = FNZP(GR"GI)
RETURN
REM
REM
AR+JAI
A at AP de-grees
B at BP degrees
AL at AQ degrees
26200 REM *.**********.~* •• ****.***.*.~*********************************
26300
26400
26500
26600
26700
26800
26900
27000
27100
27200
27300
27400
27500
27600
27700
REM
REM
REM
PRINT
PRINT
PRINT"
PRINT"
PRINT "
PRINT"
PRINT"
PRINT"
PRINT"
RETURN
REM
REM
27800 REM
27900
28000
28100
28200
28300
28400
28500
28600
28700
28800
28900
29000
29100
29200
29300
29400'
29500
29600
29700
29800
29900
30000
30100
30200
30300
30400
30500
30600
30700
30800
30900
31000
31100
31200
PRINT CIRCUIT ANALYSIS RESULTS
FREOUENCY = ",SO," + J",FCl," HZ"
XTAL IMPEDANCE = ",FNZMCRE,XE)," OHMS AT ",FNZPCRE,XE)," DEGREES"
(RE = ",CSNGCRE)," OHMS)"
CXE = ", CSNG CXE)," OHMS)"
LOAD IMPEDANCE
",FNZM(RL, XL!. " OHMS AT ".FNZP(RL.XL)," DEGREES"
AMPLIFIER GAIN = ",A." AT ",AP," DEGREES"
FEEDBACK "ATIO = ",B," AT ",BP," DEGREES"
LOOP GAIN = ".AL," AT ",AQ," DEGREES"
**************************************************************
REM
REM
SEARCH FOR FREOUENCY tS+JF)
REM
AT WHICH LOOP GAIN HAS ZERO PHASE ANGLE
REM
REM Th1S routine searches for the frequency at which the Imagina~y pa~t
REM of the loop gain IS zero T~e algorithm 15 as follo~s.
REM
1. Calculate the sign of the Imaginary pa~t of the loop gain CGI),
REM
2. Increment the frequency
REM
3. Calculate the sIgn of GI at the Incremented frequency.
REM
4. If the sign of GI has not changed. go back to 2
REM
5. If the sign of GJ has c~anged. and this frequency is ~ithin
REM
1Hz of the prevIous Sign-change. eXlt the routine
REM
6. OtherWise. diVide the frequencl:I increment by -10.
REM
7, Go back to 2
REM The ~outine 15 entered wIth the starting frequency SQ+JFO and
REM starting Increment DS+JDF already defined b~ the calling p~og~am.
REM In actual use either OS or OF IS zero. so the routine searches fo~
REM a GI=O pOInt by IncrementIng eIther 50 O~ FQ While holdIng the other
REM constant. It return~ control to t~e calling program ~ith the
REM incremented part of the frequer.cy being Within 1Hz of the actual
REM GI=O pOlnt
REM
REM I. CALCULATE THE SIGN OF THE 1I1AGINARY PART OF THE LOOP GAIN CGI),
REM
GOSUa 20200
GOSUa 26600
IF GI=O THEN RETL'RN
SX7. = INTtSGNCGI»
IF SX7.=+l THEN 05
-DS
REM IREVERSAL OF DS FOR GI:O 15 FOR THE POLE-SEARCH ROUTINE)
REM \
REM 2
INCREMENT THE FREOUENCY
REM
SP = SO
230659-47
9-51
inter
31300
31400
31500
31600
31700
31800
31900
32000
32100
32200
32300
32400
32500
32600
32700
32800
32900
33000
33100
33200
33300
33400
33500
33600
33700
33800
33900
34000
34100
34200
34300
34400
AP·155
FP = FCl
SCl = SQ + DS
FCl ~ FCl + DF
REM
REM 3 C.'LCI.'LIITF. THE SIGN OF GI AT THE INCREMENTED FREQUENCY
REM
GOSUe 20200
GOSUe 26600
IF INT(SGN(GIII~0 THEN RETURN
REM
REM 4
IF THE SIGN OF GI HAS Nor CHANGED. GO BACK TO 2
REM
IF SXY.+INT(SGN(GI) 1=0 THEN PRINT ELSE 31400
SX7. = -SXY.
.
REM
REM :;
IF THE SIGN OF GI HAS CHANGED. AND IF THIS FREGUENCY IS WITHIN
REM
1HZ QF 1~E PREVH!t'5 S!GN-CHANGE. AND !F G! !S NEGATIVE; THEN
EXIT TH~. POUTINF.
------{
DATA IN
-.----~
292048-1
Figure 1. Every microcontroller memory acccess requires two cycles.
9-56
AP·318
WHY A PORT EXPANDER?
ler. System reliability and performance are degraded.
Design and manufacturing are more complicated.
Single-chip microcontroller solutions are quickly giving
way to multiple-chip, high-end solutions. Embedded
control applications often require more program memory than the microcontroller's on-chip memory. Sometimes, code flexibility is needed. The 87C75PF's 32K
byte EPROM dwarfs any microcontroller's on-chip
memory.
Intel's high-performance 87C75PF Port Expander
doesn't compromise designers' goals to create reliable,
minimum chip systems. Its single chip, no-glue interface simplifies design and manufacturing while increasing performance and reliability - in the smallest possible board space.
In the near future, microcontroller chip-sets - controller and peripheral - will make up most embedded control applications. The controller will contain features
that must be coupled closely to its CPU. The peripheral
chip will provide memory and I/O functions.
Controller and peripheral-chip costs will be more balanced. The chips will share complexity, which equates
to cost. Two smaller, less complex chips will cost less
than one huge controller chip, resulting in lower total
system cost.
Typically, adding external functions to microcontrollers requires many chips and substantial board space.
Address latches, memory, port recovery, and glue chips
require far more space than a single-chip microcontrol-
A TYPICAL SYSTEM
Intel's 8051 microcontroller architecture is the most
widely used. Many variations are available with enhanced I/O features and various amounts of memory.
Intel's 80C3l is a nOll-ROM, CHMOS version of the
8051. It will help illustrate the 87C75PF's benefits over
typical multiple-chip uC solutions.
Figure 2 shows a typical expanded microcontroller system. Whenever memory-mapped devices are connected
to a microcontrolIer, two 8-bit ports lose their I/O
functions to become address and data pins. Figure 2
shows port-reconstruction devices, a 256K-bit
EPROM, and glue chips that make up an embedded
control system. Nineteen chips are required!
,
RSTI
~--P~S~EN~'------C>~----o,rr
PSEN~~~~-----------------,
Pl.D-Pt.?
BOC31
PORT 2
ALE
~==~~[L~
t----'=+--------+
P3.4
P3.5
PORT 0
K===:j]~ill~
P3.6/WR
P3.7/Rii
Pl.0-Pl.?
292048-2
Figure 2. Many discrete chips provide EPROM and port expansion.
9-57
AP-318
Examples in this application- note show how the
87C75PF works with various microcontrollers. An
805l/87C75PF system that takes advantage of highlevel compiled languages and an in-system programmable example will also be shown.
SYSTEM PERFORMANCE
Every system component influences performance. Performance encompasses" speed, system noise, and power
consumption. A typical expanded-mode controller application uses many chips to increase memory and recover 10st'I/O. Figure 3 shows an improved, but more
expensive, alternative to the system in Figure 2. "Glue"
chips between the controller and peripherals delay address signals. To optimize system speed, fast, expensive
glue chips, memory, and peripheral devices are required.
.
SYSTEM INTEGRATION
Intuitively we all recognize the benefit of system integration - chip-count is reduced.
Just as important are:
Multiple-chip solutions consume significant power and
inject noise into a system. A beefed-up, well regulated
power supply will relieve symptoms; but adds significantly to cost, board size, and weight.
•
•
•
•
•
•
•
•
THE 87C75PF SOLUTION
Figure 4 shows the same system using the 87C75PF a two chip solution!
small board size with few layers
increased performance
decreased design time
optimized software development
reduced inventory
less incoming inspection
increased system reliability
simplified manufacturing.
Cost is a prime consideration. The itemized cost of discrete components is only one parameter. Until the benefits listed above are quantified, realistic system costs
can't be determined. Hardware design and software development time are significant up-front expenses. Multiple-chip systems incur substantial inventory, incom- .
ing inspection, testing, manufacturing, board size, and
rework costs.
The 87C75PF furnishes a no-glue interface to 8051based systems and all other Intel-architecture embedded controllers. The Port Expander's flexible, user-programmable memory map and alterable control signals
simplify 8051, 8096, and 80188 connections.
CONTROL BUS
(f)a::
(f)W
WO
PORT1
0:::0
00
Ow
«0
PORT2
80C31
A8-A15
(f)
82C55A
(/):1:
Wu
PORTO
PORT3
0:::1-
0«
0-1
«
292048 -3
Figure 3. A simplified multiple-chip system.
9-58
inter
AP-318
Relocatable EPROM
The EPROM has 262,144 bits organized as 32K 8-bit
words. Its access time determines the device's speed
rating. The 32K-byte EPROM occupies half of the program memory (or EPROM) plane. The EPROM block
can be located in either the lower or upper half of the
EPROM plane to accommodate various microcontroller architectures.
80C31
Dual or Single Memory Planes
292048-4
Figure 4. A "no-glue", two chip 87C75PF system.
Reliability also has significant value - to you and your
customers. Customers demand products that work
properly - forever. Reworked products waste time and
money, increase the cost of every unit you ship, and
ruin your company's reputation. The best way to increase reliability is to eliminate system components.
Simplified manufacturing saves time and money while
increasing reliability. One factory-tested, integratedfunction chip is much easier to place on a circuit board
and is far more reliable than myriad discrete chips. Every solder joint is a possible failure point. A single chip
reduces potential failure points from hundreds to a few.
87C75PF ARCHITECTURE
The 87C75PF Port Expander's features include:
•
•
•
•
•
•
•
•
•
•
Two 8-bit I/O ports
32K X 8 EPROM
Two 64K-byte memory planes
Special Function Registers
Device-configuration registers
"No-glue" controller interface
Low-power, Low-noise CHMOSII-E
Quick-Pulse Programming™ Algorithm
In-system programmability
40-Pin CERDIP, 44-Lead PLCC packages
8051-family microcOli.trollers have two external memory planes - program and data. 8096-, 80188-, and
68xx-family microcontrollers have only one programl
data plane. The 87C75PF's user-configurable doubleand single-plane modes work with any 8-bit microcontroller architecture.
Relocatable SFRs
The 87C75PF has five special function registers:
•
•
•
•
•
Port 1 latch
Port 2 latch
Port 1 Pin
Port 2 pin
Plane select.
Port-latch registers allow the microcontroller to change
port-pin output levels. The microcontroller can read
the port latches to recall the last value written. A microcontroller can determine external pin levels by reading the port-pin locations.
During programming, the plane select register determines whether the EPROM array or the configuration
registers are being programmed. More special function
register details are dess;ribed later in this application
note.
Device Reconfiguration
Non-volatile (EPROM cell) device-configuration registers configure the 87C75PF for microcontroller compatibility. Programmable configuration registers can:
•
•
•
•
•
Two'Ports
The 87C75PF has two 8-bit bi-directional 1/0 ports.
Port 1 has open-drain outputs and port 2 has quasi-bidirectional (resistor pull-up) outputs. Each port is individually addressable with separate port-latch and portpin addresses. Typical of quasi-bi-directional ports,
they are always in output mode but can be used as
inputs by simply writing logic "Is" to their latches.
9-59
relocate the EPROM array in the memory map
relocate the SFRs in the memory map
combine the EPROM and SFR planes
change the reset pin's active polarity
insert transistor pull-ups'on port pins.
inter
AP-318
In its default configuration', the 87C75PF is compatible
with the 8051 's two-plane architecture. It is easily reconfigured for single-plane 8096 architecture. Remapping the memory planes makes the device compatible
with 80188 and 68xx architectures.
Various microcontrollers have different reset input levels. The 8051 's reset is active-high while the 8096's is
active-low. The 80188 has an active-low reset input and
active-high synchronous reset output. The Port Expander's configurable reset polarity can work with activehigh or active-low microcontrollers.
, Quick·Pulse Programming
Intel's microcontroller, peripheral, and EPROM products employ the industry's fastest, most reliable QuickPulse PrVpp/RST
CE
,.,
WR/PGM
:;( :;( :;(
A15
PL7
A14
Pl.6
A13
PL5
A12
Pl.4
All
P1.3
A1D
P1.2
A9
P1.l
AS
Pl.D
AD7
ALE
AD6
P2.7
AD5
P2.6
AD4
P2.5
AD3
P2.4
AD2
P2.3
ADl
P2.2
ADD
P2.l
PSEN
P2.D
-t
III
""a..
.......
0..
It! >
•
~,
0
ul~
>u
3:
": "! II"!
a: a: a:
Pl.4
A12
RD
GND
I~
Vl
Vee
All
PL3
A1D
P1.2
A9
P1.l
AS
PloD
GND
GND
N.C.
RD
AD7
ALE
AD6
P2.7
AD5
P2.6
AD4
P2.5
,.,
0
WRITE TO
LATCH
RESET
PIN
OUTPUT
CONTROL
0 1
::IE-'
U-'
=>
0..
P1.x
PIN
CONTROL
292048-10
Figure 10. Port 1 is Open-Drain (default) or programmable for active (CMOS) pull-ups.
9-64
inter
AP-318
READ
PIN
READ
LATCH
CLR.S
INTERNAL
DATA BUS
P2.x
LATCH
WRITE TO
LATCH
PIN
OUTPUT
CONTROL
RESET
P2.x
PIN
CONTROL
PULSED
PULL-UP.
292048-11
Figure 11. Port 2 is Quasi-bi-dlrectional (default) or programmable for active (CMOS) pull-ups.
dressable registers. Two planes are external - program
(EPROM) and data (RAM) memory. The instruction
type drives internal and external read, write, and bus
signals that select individual planes. An 8051 controller
requires non-volatile boot-up memory, internal or ex-
ternal, at the bottom of its program memory plane. The
87C75PF's two-plane external-memory architecture
(see Figure 12) matches the 8051's architecture.
EPROM defaults to the EPROM plane's low-memory
and SFRs default to the SFR plane's high-memory.
FFFFh ,...-_ _ _ _-,
~
003B h
0033 h
0028 h
0023 h
0018 h
0013 h
0008 h
0003 h
0000 h
!""OTHER INT. VECTORS '"I""
PCA
TF2 Be EXF2
RI &: TI
TFI
IEl
TFO
lEO
RESET
RESET Be
INTERRUPT
VECTORS
PROGRAM
MEMORY
64K BYTES
\
-j..J
PSEN
DATA
MEMORY
64K BYTES
OOOOh .....-r-""""I~....
iUi-1 LWR
292048-12
Figure 12. The 8051's two-plane memory has reset and vector addresses in low program-memory.
9-65
AP-318
8096-family controllers 'are typically used with a single
64K-byte external memory plane (Figure 13). Like the
8051, reset and vector addresses are in low memory.
The 87C75PF has an optional single-plane configuration that complements 8096 architecture. The
EPROM, located in low memory, is combined with the
SFR plane.
Intel's 80188 microprocessor is used primarily in highend embedded-control applications. Adding ports and
memory makes the 80188 one of the most powerful
microcontrollers available. The 87C75PF provides
much of this hardware in a single package. The 80188
has a single memory plane. Unlike 8051 and 8096 controllers, its boot-up address is at the top of its 1M-byte
address space (Figure 14). The 87C75PF can be configured for a no-glue 80188 interface.
The 87C75PF's flexibility simplifies hardware interfacing with many other microcontrollers. A 68xx controller, for example, has boot-up vectors at the top of its
64K-byte single-plane memory space. The Port Expander's memory map can be configured, much like that
used by the 80188 (Figure 14), to accommodate 68xx
controllers.
FFFFFh
r------.,
FFFFh
1------.. .
RESET ADDRESS
FFFFOh
EXTERNAL MEMORY
OR I/O
OOOOOh ' -_ _ _ _ _......
292048-14
4000h
Figure 14. The 80188 boots up at the top of its
,1M-byte address space.
INTERNAL PROGRAM
STORAGE ROM/EPROM
OR
EXTERNAL MEMORY
2080h
RESERVED
2030h
Default Configuration
SECURITY KEY
2020h
RESERVED
201Ch
SELF JUMP OPCODE
201Ah
RESERVED
2019h
CHIP CONFIGURATION BYTE
2018h
RESERVED
2012h
INTERRUPT VECTORS
2000h
PORT 4
lFFFh
PORT 3
lFFEh
Ultraviolet light exposure will erase the 87C75PF's
EPROM array and non-volatile configuration registers.
The EPROM, SFRs, and other user-configurable options' default to:
.
• two memory planes - EPROM and SFR
• EPROM at OOOOh-7FFFh
• SFR block at F800h-FFFFh
• reset (RST) active-high
• port 1 open drain
• port 2 quasi-bi-directional.
EXTERNAL MEMORY
OR I/O
0100h
INTERNAL RAM
REGISTER FILE
STACK POINTER
SPECIAL FUNCTION REGISTERS
(WHEN ACCESSED AS DATA MEMORY)
OOOOh
-
RD
L-
WR
292048-13
Figure 13. The 8096 has a single memory plane.
9-66
inter
AP-318
gramming CLR.6, PIC, and/or CLR.5, P2C (see Figure 15), inserts active pull-up transistors in port output
buffers. These transistors supply higher current and
faster switching than open drain or quasi-bi-directional
outputs.
Changing the Reset Polarity
8051-family microcontrollers have active high reset inputs. 8096, 68xx, 80188, and special 8051-architecture
controllers have active-low resets. The 80188 also has
an active-high synchronous reset output.
Moving the EPROM
The Port 'Expander's alterable reset input (RST) can
match any microcontroller. When erased, the
87C75PF's RST is active-high. Programming the configuration plane's control level register bit CLR.7
changes RST to active-low (see Figure 15).
The 87C75PF's EPROM can be relocated to the upper
half of its 64K-byte memory map. When erased, the
EPROM is correctly positioned in low memory for
8051- and 8096-family controllers. Programining the
configuration plane's EPROM Location bit, ELR.7
(Figure 16), moves the EPROM to high memory for
80188 and 68xx compatibility.
Changing Port Output Drive
If port 1 and/or port 2 are used only as outputs, it may
be preferable to have CMOS-type output levels. Pro-
r--------
I,
I
I
I
IL~EL-II
CLR
RESET
-II
1
Port 1
Port 2
CMSOS
I CMSOS
I
CLR.7 = RESET LEVEL
o = Active-Low
1 = Active-High (Default)
CLRo6==c~g:T 1 CMOS DRIVE
1 = Open Drain (Default)
CLR.S = PORT 2 CMOS DRIVE
0= CMOS
1 = QUQsl-bl-dlrectiono! (Default)
THESE BITS ARE DON'T CARE
4
I RSTL I PIC I P2C I
--- --- ---
X
3
I
X
2
I
-j
1
I
X
°
X
17ffDh
----1--1 1", I I
1 1 1 -: '" : a. ' 'CO ::---_~\:
Non-volalile
+
+
+
+
+
+
+
+
+
I I I I I
292048-15
Figure 15. The Control Level Register (CLR) determines the reset pin's polarity and CMOS port drive.
9-67
intJ
AP-318
and program-plane addresses. For example, look-up tables stored in the same EPROM as program instructions require PSEN to be asserted. However, a compiler
interprets look-up table instructions as data fetches. It
assigns code that asserts RD instead of PSEN. A typical hardwa~olution uses an AND gate to combine
PSEN and RD. This forms one memory plane that is
accessed by either signal. Programming the 87C75PF's
OVLP bit provides this "AND" function.
Double- and Single-plane
Configurations
The 87C75PF has two operating-mode memory-planes
- EPROM and SFR. These planes share identical
memory addresses. The EPROM plane is selected when
PSEN ~TTL-low. The SFR plane is selected when
either RD or WR is TTL-low. 8051 microcontrollers
use PSEN, RD, and WR to select two external memory
planes. 8096 controllers have only RD and WR; some
versions have an "INST" output that allows external
circuitry to determine when instructions are being issued. Most other microcontrollers provide read and
write signals that control only one memory plane.
This bit also permits the SFRs to overlap the EPROM
array. This allows multiple Port Expanders to be used
in single-plane applications. For example, two Port Expanders can be used in an 8096 system (see Figure 22).
Normally, two 87C75PFs' 64K EPROM bytes consume the entire address space leaving no room for'port
addresses or external RAM. When ELR.6 = "0" and
the device's 2K-byte SFR block overlaps its EPROM
array, 2K EPROM bytes are sacrificed to make room
for the SFRs and external RAM. Under these conditions, the 87C75PF remains in a high impedance state
during any access to the 2K-byte SFR-block except for
the five valid SFR addresses (see Figure 9).
Programming the 87C75PF's overlap bit, OVLP
(ELR.6), converts the device from dual-plane to single~e (see Figure 16). When ELR.6 = "0", PSEN and
RD are internally combined. Both memory planes are
active if either is TTL-low.
8051 applications that use code compiled from highlevel languages find this especially useful. Some highlevel languages canlt distinguish between data-plane
ELR.7
= EPROM LOCATION
o = HIgh Memory
I!
1 = Low Memory '(Default)
ELR.6
=SFR/EPROM OVERLAP
o = Overlap
1 = No Overlap (Default)
I LOCATE I Overlap I
I
EP:OM
ELR
I
I
I
THESE B,ITS ARE DON'T CARE
6
I
I
5
4
2
~
1
0
I I I I I ,
--- --- --- --,,
EL
OVLP
"re'l I I
X
X
7FFOh
+
3
+
+
:::I,~,I~.ul
I
+
X
X
X
rr~1
+
+ +
ELR
X
---.\
!~t"'--- --"LLL
Non-volatile
Reglstor (ELR)
7FF7h
,
+
III I
I
17FFEh
,
+
-
I~~
0OO7h
-- ---
.
Intellgent
Wr/flors,
292046-16
Figure 16. The EPROM Location, Register determines the EPROM's memory-map location
9-68
AP·318
memory, 8000h-FFFFh). Programming SFRLR to
OOOOOxxx moves the SFRs to the bottom of memory,
OOOOh-07FFh. Figure 17 shows the SFRLR and its bit
definitions.
Moving the SFR Block
The 2K-byte SFR block's default location is F800hFFFFh in the SFR plane. This location is fine for 8051
and 8096 applications. However, 80188 and 68xx-family controllers have boot-up and vector addresses in this
address range; EPROM should be located here.
Programming the Configuratio,n Plane
The 87C75PF data sheet describes detailed programming requirements. PROM programming equipment
makes device reconfiguration easy. Down-loading
EPROM code (from OOOOh to 7FFFh) to the programmer is the same as for any 256K PROM device. The
programmer allows editing of CLR, ELR, and SFRLR
codes to reconfigure the device. Once programming
commences, the EPROM array and the configuration
registers are programmed automatically.
The SFR block can be moved to any 2K-byte deviceaddress boundary. The SFR location register's
(SFRLR) five bits determine the SFR-block's most-sig.nificant address bits. When erased, these bits are all
"Is", placing the SFRs at lllllxxx xxxxxxxxb or
F800h-FFFFh. Programming the SFRLR to OIIllxxx,
for example, relocates the SFR-block to 7800h-7FFFh
Gust below the EPROM array when it's at the top of
I,-
Defines SFR
2K - byte Boundary
--j-
THESE BITS ARE
DON'T CARE
1
76543210
SFRLRI
A~ -'_ A14
I
A 13
I
A12
I
I
All
------ ------
X
X
17FFFh
X
''
f~ ---1- -""I ,~" I':~: ~~~ :~.)
Non-volatile
"
''' 1
7FFOh
+
1
1 1 I
+
+
+
: " : ill
+ +
+
:
+
II I I I
- - -
+
I'''~
0007h
..
..
.. :'I~t~lIg~~t::
.:.: Identifiers ...
292048-17
Figure 17. The SFRLR determines the 2K·byte SFR block's base address.
9-69
inter
Ap·318
+
87C75PF APPLICATIONS
80C31
Now that you're familiar with how the Port Expander
is organized and reconfigured, this section highlights
some application examples. You'll see how the
87C75PF connects to 8051, 8096, 80188, and 68xx microcontrollers. Also shown are more sophisticated applications that use multiple Port Expanders and one'
that allows the microcon~roller to program its own Port
Expander. All of the applications illustrated show microcontrollerlPort Expander interfaces, memory maps,
and configuration register (CLR, ELR, SFRLR) values.
8051-family controllers usually operate in two-plane
mode. To use external program memory (EPROML exclusively, the controller's external access pin, EA, is
tied to ground. Port 2 supplies upper addresses, AgA15. Port 0 becomes the multiplexed lower-address/
data bus, AD..JL..AD7' PSEN is the program memory
read strobe. WR and RD (port pins P3.6 and P3.7)
control external RAM and other read/write devices.
RST is active-high on most 80S1-family microcontrollers. Some special-purpose '51-based controllers have
active-low resets.
87C75PF
Figure 18 shows a typical 80C31 + 87C75PF no-glue
application. The 87C75PF's EPROM, SFR, and control-signal default-settings are already configured. Programming the large XX place holders shown in the
CLR register enables CMOS port drive .
......- - - . . , ffffh .......,·-::S~fR::-s-..,
f800h 1-""';;;';';';;;""-1
P2.7
Pl.7
P2.6
Pl.6
P2.S
A13
Pl.S
P2.4
A12
Pl.4
P2.3
All
Pl.3
P2.2
Al0
Pl.2
P2.1
A9
80C31
P3.S
A14
P2.0
A8
PO.7
AD7
PO.6
AD6
po.s
ADS
PO.4
AD4
PO.3
AD3
PO.2
AD2
PO.l
ADI
PO.O
ADO
8000h
87C75PF
.: EPROM
(default) :
ALE
P3.6jWR
P3.7/RO
L...;,_____..............
EPROM
PLANE
OOOOh L..._ _ _......
SFR
PLANE
292048-18
CLR
= 1XXxxxxxb
ELR
= 11 xxxxxxb
SFRLR = 11111xxxb
Figure 18. The ~7C75PF's no-glue interface takes advantage of the 80C31's two-plane memory map.'
9-70
intJ
80C31
AP-318
Figure 19 shows two Port Expanders in an 80C31 system. Port Expander 1's EPROM is in its default lowmemory location (OOOOh-7FFFh). Its SFR block is
moved to FOOOh, out of Port Expander 2's SFR range
(F800h). Port Expander 2's EPROM is moved to highmemory (8000h-FFFFh). Each device's configuration
register values are shown below the memory map. This
configuration provides 16 additional I/O pins, 64K
EPROM bytes, and leaves 60K for RAM and other
memory-mapped devices .
+ Two 87C75PFs
High-end applications, such as telecommunications, require sizable program memories and numerous I/O
ports. Many of these applications use 80S I-family microcontroIIers. Two 87C7SPF Port Expanders supply
added I/O while furnishing EPROM - without using
"glue" devices!
.....- - - . . , FFFFh
SFR 2
~~gg~
SFR 1
EPROM
o
I----oool 8000h
EPROM
CD
L-_ _ _.J OOOOh L-_ _ _.J
EPROM
SFR
PLANE
PLANE
CLR2
= 1XXxxxxxb
ELR2
= 01 xxxxxxb
SFRLR2 = 11111xxxb
= 1XXxxxxxb
CLR1
ELR1
= 11xxxxxxb
SFRLR1 = 11110xxxb
292048-19
Figure 19. Two 87C75PFs provide 16 1/0 pins, 64K EPROM bytes, and room for 6DK of RAM.
9-71
inter
AP-318
High-level Language 80C31
87C75PF
+
The typical solution forces the system to o~te in single-plane mode by combining PSEN and RD with an
AND gate. If either signal is TTL-low, the AND gate's
output drives a common external-memory read signal.
A compiler can now assign its typical "read from data
memory" instruction.
The 80S l's two-plane flexibility challenges hardware
and software engineers' creativity. Its two planes logically separate program and data planes to create l28Kbytes of memory in a 64K address space. However,
many applications have' look-up tables in non-volatile
memory, usually in the same EPROM that contains
program code. Unique assembly-language instructions
drive hardware signals, PSEN, RD, and WR, to determine which plane is active.
The Port Expander has this "AND" function built in.
Programming the configuration plane~verlap bit,
ELR.6" internally combines PSEN and RD; if either is
at TTL-low EPROM or SFR data, depending on the
address, is read. Figure 20 shows a typical high-levellanguage application.
Some compiled, high-level programming languages,
however, have a hard time dealing with two-plane
memories. They can't determine which 8051 instruction to use when look-up tables occupy the program
~e. They usually assign an instruction that activates
RD, rather than PSEN.
Programming this bit also allows the SFR-block to
overlap the EPROM in single-plane applications. If,
and only if, these blocks overlap, 2K EPROM bytes are
sacrificed to make room for the SFR block. The "8096
+ two 87C7SPFs" section illustrates this.
1
·.srRs
- --
-
80C31
A13
P2.4
A12
P2.3
All
P2.2
Al0
P2.1
A9
P2.0
AS
PO.7
AD7
PO.6
AD6
PO.S
PO.4
P3.S
A14
P2.S
ADS
~
-
------
P2.7
P2.6
P1.7
rrrrh
raOOh
---
---;- -
-
aOOOh
87C75PF
AD4
PO.3
AD3
PO.2
AD2
PO.l
EPROM
PO.O
(default)
ALE
P3.6/WR
P3.7/RO
....._ _ _-'" OOOOh
Tr-ir-l-'>',- PSENi
EPROM/
SFR
PLANE
\.L-t>==~'-- Riii
CLR
= 1XXxxxxxb
ELR
= 10xxxxxxb
SFRLR = 11111xxxb 292048-20
Figure 20. Programming ELR.6 combines PSEN and RD to form a single memory plane.
9-72
intJ
8096
+
AP-318
87C75PF
8096-family 16-bit microcontrollers can also operate in
8-bit mode. These high performance controllers manage applications that are 1/0 intensive and, as a result,
require large EPROM arrays. The 87C7SPF expands
the I/O 'Yhile providing the EPROM.
The 8096 accesses a 64K-byte single-plane memory. Its
memory map is similar to the 80SI's. External EPROM
is required at its low-memory boot-up location (2080h).
The 87C7SPF's EPROM and SFRs are appropriately
located.
The 8096's reset input (RES) is active-low. Programming the Port Expander's reset level configuration bit,
RSTL (CLR.7), makes RST's polarity active-low.
The 87C7SPF is converted to single-plane mode by either tying PSEN and RD to the 8096's RD pin or by
programming ELR.6, the overlap bit. If the latter option is chosen, the unused input, PSEN or RD, should
be tied to Vee. Figure 21 shows a "no-glue" 8096 +
87C75PF application.
rrrfh
faOOh
SFRs
PO.6
HSll
-
HSOS/HSI3
HS04/HSI2
a-BIT MODE
P4.7
AIS
P4.6
A14
P4.S
A13
P4.4
A12
P4.3
A11
P4.2
Al0
P4.1
A9
P4.0
AS
P3.7
AD7
P3.6
ADS
P3.S
ADS
P3.4
AD.
P3.3
AD3
P3.2
AD2
P3.1
ADI
P3.D
ADO
BOOOh
87C75Pf
OOOOh
EPROM/
SFR
PLANE
292048-22
CLR
= OXXxxxxxb
ELR
= 1o/, xxxxxxb
SFRLR = 11111xxxb
INST
iffi
ViR
iiHE
ANGND
vss
vss
-
-- - -- ----
EPROM
(default)
ALE
CLKOUT
-
-- --
PD.7
80C196
80968H
8098
-
GND
EA
292048-21
Figure 21. The 87C75PF is also the no-glue Port Expander for 8096 systems.
9-73
AP-318
8096
+ Two 87C75PFs
Single-plane 8096 applications can use two Port Expanders. Figure 22 shows this no-glue, three-chip system.
Port Expander I has its EPROM in default low-memory. Its SFR block is mapped over its EPROM; location
7800h is arbitrarily chosen. Programming Ollllxxxb
into SFRLR moves the SFR block. Programming
ELR.6 (to "0") overlaps the EPROM and SFR planes;
one plane is formed. This bit also tells the Port Expander that its SFRs are intentionally mapped over its
, EPROM. The device sacrifices 2K EPROM bytes to
make room for the SFR block. Any ac\!ess to this 2K-
byte block, except v~id port and PSR addresses, places
the external data bus in a high impedance state. External RAM can occupy the 2K-byte space.
Port Expander 2 is also reconfigured. Its EPROM is
moved to high-memory by programming ELR.7. Its
SFR block must overlap its EPROM array; 8000h is
arbitrarily chosen. Port Expander 2's overlap bit,
ELR.6, is programmed to form a single plane and to
tell the device that its SFRs are intentionally mapped
over its EPROM, like Port Expander 1. This configuration supplies four additional 8-bit ports, 60K EPROM
bytes, and sti11leaves 4K bytes free for RAM.
EPROM
CD
BBOOh
BDOOh
7800h
SFR 2
SF'R 1
. EPROM
80C196
8096BH
8098
CD
8-BIT MODE
0000"
EPROM/
SFR
PLANE
292048-24
CLR2
= OXXxxxxxb
ELR2
= OOxxxxxxb
SFRLR2 = 10000xxxb
CLKOUT
ANGND
vss
vss
EA
CLR1
= OXXxxxxxb
ELR1
= 10xxxxxxb
SFRLR1 = 01111xxxb
292048-23
Figure 22: Two 87C75PFs add 161/0 pins, 60K EPROM bytes, and leave room for 4K of RAM.
9-74
AP-318
80C188
+ 87C75PF
EPROM-block addresses, (P7800h is shown). Pro-ramming the over1~it, ELR.6, or tying PSEN and RD to
the 80CI88's RD combines the EPROM and SPR
planes. The processor's UCS, connected to the
87C75PP's CE, selects the Port Expander in the upper
address range. The 80CI88's reset input, RES, is active
low. Programming the 87C75PP's RSTL bit, CLR.7,
converts RST to active-low. the 80Cl88 also has an
active-high synchronous reset output. This output can
be connected to the 87C75PP's RST without reconfiguring RST's polarity.
The 80CI88 found its niche in high-end embedded control applications. This CPU, when combined with
RAM and the Port Expander, becomes a powerful embedded controller. Its 1M-byte address range accommodates several Port Expanders and large amounts of
RAM. Although the 80CI88 has two planes, memory
and I/O, the Port Expander works best in the memory
plane. Pigure 23 shows a simple 80CI88 + 87C75PP
system.
80Cl88 systems usually have larger RAM arrays than
typical microcontroller applications. Pigure 23 shows
the simple RAM interface. The RAM does not contain
its own address latches, so an 8-bit latch must be used
to capture addresses Ao-A7.
The 80CI88 boots up at address PPPPOh. The
87C75PP's EPROM array is moved to its high memory
(8000h-PPPPh) by programming ELR.7. The SPR
block must be moved to lower memory outside of
FFFFFh , . . . . . - - - -
usc
CE
Vpp/
Vee
RST
'15
AI.
ill
RESET
A13
EPROM
A12
OCS3
A11
"CS2
AlO
t.4CSI
AS
"CSO
A8
PCS4
A07
PCS3
ADS
PCS2
ADS
pes!
peso
Tt.cROUTO
A01
ADO
TMR IN 0
ALE
ORQI
S7
S2
-------
AD2
TI.4R IN 1
OROO
FBOOOh I--"'SF"'.,--l
F780ah I-~=-I
A03
Tt.4R OUT I
+--
87C75PF
AD.
80C188
PSEN
--
iffi
"--
--------
WR/PGt;i
so
LOCK
LCS
HlOA
CE
Vee
A15
FOOOOh I - - - - l
A14
All
,.~
A12
"EPROM
AlO
AS
SFR
A8
PLANE
SRAM
CLKOUT
,.~
292048-26
A11
CLR
= o/iXXxxxxxb
ELR
= OOAxxxxxxb
SFRLR = 01111xxxb
A7
A6
AS
A.
A3
A2
Al
AD
LATCH
292048-25
Figure 23. The Port Expander and SRAM make the 80C188 a powerful embedded controller.
9-75"
AP-318
68xx
+
A15 is logic-high during vector accesses. Second, read
and write controls are functions of R/W and E (clock
output). Combinational logic must convert R/W and E
to industry-standard RD and WR signals.
87C75PF
The microcomputer industry's peripheral- and memory-interface standard dictates chip-enable, output-enable, and write-enable polarities. All' are active-low.
The 87C75PF conforms to .this industry standard.
The 87C75PF's memory map can be reconfigured and
its two memory planes combined to simplify 68xx interfaces. Its RST polarity can match a 68xx's active-low
reset. All that's required to complete the interface is to
condition R/W and E to RD and WR. Figure 24 shows
a 68xx + 87C75PF system and its memory map.
Like Intel controllers, 68xx-family microcontrollers use
multiplexed address/data pins. However, they differ in
two significant ways. First, 68xx controllers have highmemory reset- and interrupt-vector addresses. Address
FFFFh
EPROM "
P9.7
68xx
P9.6
AIS
A14
P9.S
A13
P9.4
A12
P9.3
All
P9.2
Al0
P9.1
A9
P9.0
PC.7
AS
AD7
PC.6
ADS
PC.S
ADS
PC.4
AD4
PC.3
AD3
PC.2
PC.l
AD2
CE
Vppl
RST
8DOOh
7800h
SFRs
-
-
---
------ - --- -I
87C75PF
ADI
OOOOh I
292048-27
EPROM/
SFR
PLANE
292048-28
= OXXxxxxxb
CLR
ELR
= Oo/1xxxxxxb
SFRLR = 01111xxxb ,
Figure 24. One NAND-gate package interfaces the 87C75PF to 68xx controllers.
9-76
inter
AP-318
With EPROM and configuration register contents
loaded, the programmer automatically programs the
EPROM array and non-volatile registers. The programmer can also read a programmed master device's
EPROM array and configuration registers and program duplicates without further editing. Contact Data
I/O or your programmer vendor for further details.
PROGRAMMING
EPROM and Configuration Registers
PROM programming equipment makes the 87C75PF
as easy to program as EPROM-version microcontrollers and standard EPROMs. Optimized programming
equipment that utilizes the Quick-Pulse ProgrammingTM algorithm can program the 87C75PF in less
than four seconds.
80C51 In-system Programming
Factory programmed and field updated applications
use in-system and board-programming techniques.
Board programming equipment supplies voltages, addresses, data, and pertinent control signals to the
board's edge-card connector.
Data I/O's model 29B (version Y06), with Unipak-2B
module (version 16, family/pin code = 112/107) and
87C75PF cartridge, supports the 87C75PF. It has a
straightforward programming procedure. Assembled
code is transferred to programmer RAM addresses
OOOOh-7FFFh. Configuration registers (CLR = 7FFDh,
ELR = 7FFEh, and SFRLR = 7FFFh) are loaded into
programmer RAM addresses 8oo0H, 8oolh, and
8002h. Configuration register contents can be entered
manually using the programmer's edit command.
In-system programming, on the other hand, allows a
resident ROM- or EPROM-type microcontroller to
program the system's off-chip non-volatile memory. A
small amount of the microcontroller's ROM or
EPROM contains code that controls its serial communications channel and knows how to program external
EPROM.
RESET
FFFFh
FBOOh
4
r
L
~+12V
+12V
Vpp
+5V
rl
y
O
I
2
XTAL
TxD
EACONT
ALECONT
PGMON
ALE
Vee ~
ALEp
ALEXh
--~
ALE
Vee Vppl
RST
A15
Pl.7
P1.6
P2.6
A14
P1.6
Pl.5
P2.5
A13
P1.5
P1.4
P2.4
A12
P1.4
Pl.3
P2.3
All
Pl.3
P1.2
P2.2
Al0
P1.2
Pl.l
P2.1
A9
Pl.l
Pl.0
P2.0
AB
P1.0
PO.7
A07
PO.6
AD6
PO.5
ADS
P3.0
PO.4
AD4
P3.1
PO.3
AD3
P2.7
P3.2
PO.2
AD2
P2.6
P3.3
PO.l
ADI
P2.5
P3.4
PO.O
ADO
P2.4
ALE
ALE
P2.3
PSEN
P2.2
Rii
P2.1
P3.5
P3.6!WR
PSEN
r---'
P3.7/Rii
Vss
----
~
I+-
Wii/PGM
GND
V
V
BOOOh
I+-
~
I+I+EPROM
(default)
87C75PF
P2.0
I+I+-
292048-29
-
-
----
--
---
----
-
--
-
--
----
- -- -- --
~
I+~
I+-
--
-
chl
P2.7
80C51
. 87C51
-
- ----- --
ALEc
Pl.7
EA
RxD
RST Vee
r
---
-
+5V
PGMON
SFRs
-
ODODh
EPROM
PLANE
CLR
ELR
SFRLR
=
=
=
SFR
PLANE
292048-30
1XXxxxxxb
11xXxxxxb
11111xxxb
NOTE: Port 0 requires pull-ups when used as an 1/0 port.
Figure 25. A simple circuit allows the microcontroller to program the 87C75PF in-system.
9-77
inter
AP-318
Multiple-application modules can be customized using
in-system programming. For'example, a generic control.
module can be built, installed in a variety of end products, and customized for different tasks at the end of
the production sequence.
Figure 25 shows a simple 80C51-based in-system-programmable module. The microcontroller's on-chip
ROM or EPROM contains the communication and
programming algorithms. Port pins P3.0 and P3.1 provide the serial communication link. P3.2 (EACONT)
controls the EA pin. When high (which occurs at reset
or when "I" is written to it), internal program memory
supplies code. When low, external EPROM supplies
code. P3.4 (ALECONT) controls the ALE latching signal during programming. P3.5 (PGMON) controls programming and operating-mode Vpp and Vee voltages.
P3.6, which is the WR signal during normal operation,
serves as th~ogram pulse strobe, PGM, during programming. RD, P3.7, or PSEN can be used to verify
programmed data whenever Vpp is at its programming
voltage.
Figure 26 shows the program and latch control circuit.
5 volt and 12 volt supplies are connected to this circuit
at all times. Inverter 74'06a allows 12 volts to pass into
the DC/DC converter and the LM317 voltage regulators only when system power is on. PGMON is high
after reset or when P3.5 contains a "I." PGMON controls inverter 74'06b which turns Vpp on or off. Inverter 74'06c keeps Vcc at 5 volts until programming commences. When PGMON goes low, these inverters turn
off allowing Vpp and Vee voltages to attain their programming levels. The variable resistors adjust Vpp and
Vee read- and program-voltages. Vee read voltage is
5.0V and its program voltage is 6.25V. Vpp read voltage is off, so it doesn't interfere with the 87C75PF's
reset, and its program voltage is 12.75V.
PGMON also controls the ALE circuit.' When
PGMON is high, the microcontroller's ALE value
passes to the 87C75PF's ALE pin. When PGMON is
low, the microcontroller's ALECONT controls ALE.
p----------------------------------.
DC/DC
IN
+12V . -....- - . -....
I-~,..-._~,..-.
OUT
CONV.
__•
Vpp TO EPROM
READ MODE
PROGRAM
220
= OFF
=12.7SV
0.1 p.F
Vex:, READ
ADJUST
-I.c;:>o-~f
PGMON tr---I-----........
.........-
.....- -.........--9 GND
lK
i..-_ _...-":::::"'-....
1--4.....- - 4.....--e Vee TO EPROM
READ MODE = S.OV
PROGRAM
ALECONT
10----'
ALEp
=6.2SV
.--------+-------1
ALEx
.---------------1
----------------------------------.
292048-31
Figure 26. A mic~ocontroller can use this circuit to control programming voltages and ALE.
9-78
AP-318
6) Verify the programmed data. When the 87C75PF's
Vpp is at 12.75V, its PSEN and RD pins are internally combined. The "MOVC A,@A+ DPTR" instruction uses the PSEN pin to read EPROM data
(or the "MOVX A,@DPTR" instruction uses the
RD pin).
The microcontroller's ADO-7 and AS-15 (ports 0 and
2) connect to the 87C75PF's ADo-7 and AS-15 pins.
The controller's program-memory read signal, PSEN,
controls the 87C75PF's output-enable, PSEN.
During programming, the controller brings EACONT
high and PGMON low. This allows it to operate from
internal code, enables programming voltages on the
87C75PF's Vpp and Vee pins, and switches ALE control from the controller's ALE to its ALECONT. It
then inputs data over its serial channel. With ALECONT high, an address is placed' on ports 0 and 2.
When ALECONT is brought low, the 87C75PF internally latches the address. Data read from the serial port
is written to port O. Port 0 must have pull-up resistors
when used in its I/O port mode. The Port Expander
now has both address and data information. The controller needs only to bring its WR pin low to program
data into the addressed location.
The in-system programming sequence is summarized
below.
I) Set EACONT="I". Code is now supplied from the
controller's internal program memory.
7) Repeat this sequence until all EPROM data is programmed and verified.
8) When programming is complete, de-assert PGMON
and ALECONT. When EACONT="O", code execution commences from the 87C75PF. Code duplication at identical internal and external memory locations allows uninterrupted paging between these
two memory spaces.
When 6.25V is applied to the 87C75PF's Vee during
programming, its port outputs, when "I", will be close
to 6.25V. Careful system design should ensure that microcontroller and other device inputs can handle this
elevated voltage. Writing "Os" to all port pins before
Vee receives 6.25V will prevent damage to external
devices.
2) Assert PGMON. This switches Vpp and Vee to
their program voltages and allows the controller to
manually control ALE via ALECONT. ALECONT
and WR are high.
3) Down-load address and data information via Port
3's serial channel. Ports 0 and 2 serve as I/O ports,
so place the 16-bit address on them. Bring ALECONT low to latch the address into the 87C75PF.
SUMMARY
4) Write data information to port O.
5) Bring WR low to program data into the 87C75PF.
See the 87C75PF data sheet for the programming
algorithm and timing requirements.
Intel's 87C75PF Port Expander puts port functions,
EPROM, and "glue" into a single package. Chip count
and board size are dramatically reduced. System performance is optimized. Reliability is assured. Design
time is shortened. Manufacturing is simplified. Device
inventory is reduced.
System demands push single-chip microcontroller designs to their limits. Complex applications are I/O intensive and use lots of EPROM. Traditional solutions
use discrete chips - EPROM, address latches, address
decoders, I/O port chips, and "glue" logic - to get
more memory and expand, or recover, I/O.
Miniaturized system designs that weren't possible before, can now come to life, thanks to the 87C75PF.
9-79
inter
APPLICATION
NOTE
AP-315
July.1988
Latched EPROMs Simplify
MicrocQntrolier Designs
TERRY KENDALL
MICROCONTROLLER PERIPHERALS
@ Intel Corporation. 1988
.
9·80
Order Number: 292045·001
inter
AP-315
practical to put this much memory on the microcontroller die; chip price becomes prohibitive. Most controllers have an expansion mode that allows external
memory to be added.
INTRODUCTION
Board Space. Simplified design. Reliability. Manufacturability. Performance. Cost. Designers balance these
requirements in every project, especially in microcontroller applications.
Higher density is not the only reason to go "off-chip"
for memory. Many systems are designed to be generic
modules. For example, one engine control module can
be designed for an entire line of car models. During a
final manufacturing step the module can be custom
programmed for any particular vehicle. ROM-version
controllers don't lend themselves to this application.
EPROM memory allows any application to be customized - at any step in the manufacturing process.
This application note will show how Intel's latched
EPROMs minimize board space ~nd cost, simplify design and manufacturing, and increase performance and
reliability in microcontroller systems.
A few years ago an embedded control system consisted
of many discrete components. A general purpose microprocessor was combined with memories, timers,
counters, I/O expanders, address decoders, latches, and
assorted glue chips to make a basic control system.
Then came the microcontroller. These functions, and
many more, are now combined into a single chip.
But, using off-chip memory shouldn't detract from the
designer's goal to achieve a minimum-chip system.
Latched EPROMs provide microcontroller memory expansion without adding "glue" chips.
Today, engineers are stretching the limits of microcontroller features. Controller manufacturers are stuffing
as many functions and as much memory as die and
package can accommodate. Microcontrollers typically
have EPROM (or ROM) densities of 4K or 8K bytes;
some advanced controllers even have 16K. Still, more is
required.
THE MULTIPLEXED BUS
To achieve small board space, embedded control systems require not only minimum chip count but chips
that occupy small footprints. Embedded controllers
achieve this by using multiplexed address/data buses.
An 8051 controller, for example, shares its lower eight
address pins with its 8-bit data.
Microcontroller applications are now moving back to
multiple chip solutions. 32K-byte EPROMs are common in many medium and high-end systems. It is not
EV,ery memory access requires two cycles - one for
address, one for data (see Figure 1). The controller
~ADDRESS CYCLE
DATA CYCLE
\
ALE
\
A8-A15
)(
ADO-AD7
)(
/
)(
ADDRESS VALID
ADDRESS VALID
DATA IN
i-~
mm" " ' ~
292045-1
Figure 1. Every microcontroller memory access requires two cycles.
9-81
AP·315
places a 16-bit address on the bus during the first cycle.
It holds the upper eight bits constant throughout the
access. It presents the lower address byte just long
enough for an external latch to capture it. The latch
and controller's upper bus supply the address to external devices for the remainder of the memory access.
The controller uses its multiplexed lower address/data
pins to transmit or receive data during the data cycle.
As well as minimizing the controller's pin count, the
multiplexed bus requires fewer board traces.
MICROCONTROLLER MEMORY
INTERFACE
A typical microcontroller/memory interface is shown
in Figure 2. Eight-bit controllers require at least one 8bit address latch; Sixteen-bit controllers require two. In
an 8-bit system, the controller's A8-IS address pins are
connected directly to the EPROM's upper address pins.
Address/data pins ADO-7 are connected to the
EPROM's DO-7 data pins and to the address latch's
inputs. The latch's outputs drive the EPROM's AO-7
address inputs. The controller's address-latch-enable,
ALE, controls the latch. Figure 2a shows this memory
interface.
Before latched EPROMs, adding external memory to
microcontrollers consumed excess board space. Address latches plus EPROM required more space than
the controller itself. The address latch consumes significant board space and system power, degrades system
reliability and EPROM performance, and complicates
design and manufacturing.
Figure 2b shows a simplified system that uses a latched
EPROM. All of the controller's bus signals connect directly to the latched EPROM. It's easy to see that design time (and manufacturing) are simplified. Performance is improved because latch propagation delay is
non-existent. System reliability is assured - one factory-tested, integrated memory device is inherently more
reliable than several discrete components.
Intel's high-performance latched EPROMs don't compromise designers' goals to produce minimum chip systems. The address latching function is built into the
EPROM chip. The no-glue controller-EPROM interface simplifies design and manufacturing while increasing performance and reliability - in the smallest possible board space.
A8-A15
ALE:t-....,..----t
. A7l Standard
EPROM
"c
AD
r
- 7- - - - I
L--OO
- _O
L----.::.:....::.:...---Ioo
R i i l - - - - - - - - - - + l . OE
292045-2
a) A minimum·chip system using a standard EPROM.
RiiI----+lOE
292045-3
b) A latched EPROM simplifies the system.
Figure 2. Typical microcontroller/memory systems are improved with latched EPROMs.
9-82
inter
AP-315
Discrete latch chips, like the 74HCT573, have large
output drivers. This allows them to drive many devices
on a system's address bus. Unfortunately, large output
drivers consume considerable power. Typical microcontroller applications are minimum-chip systems. Discrete address latches unnecessarily waste system power
with their large drive capability. Intel's latched
EPROMs use very little power because their built-in
latches drive only internal address lines. Integrated address latches allow "no-glue" interfacing to 8-bit and
l6-bit microcontrollers.
board component is subject to failure. A discrete latch
requires twenty additional PC-board solder joints each a potential failure point. Failures decrease as part
count (elimination of latches) goes down.
Every board trace and component node is a source (or
receptor) of system noise. Noise can degrade performance and compromise data integrity. EPROM performance requires rock-steady address inputs. When
EPROM output buffers turn on, address input buffers
are affected. A small ground reference fluctuation
changes the threshold voltage of input buffer transistors. This can effectively change the EPROM's address
in mid-access; data integrity is compromised.
SYSTEM INTEGRITY
An address latch and associated board traces require
about .75 inches 2 . This doesn't sound like much, but
compared to the EPROM's 1.2 in 2 and the controller's
1.5 in 2 it amounts to 22% of a system's board space.
Latched EPROMs are virtually immune to ground-reference shifts. Current surge caused by switching output
buffers may affect the EPROM's address inputs, but
the internally latched address remains steady; noise
isn't transferred to address decoders. Access time and
data integrity are optimized.
Not only does a latched EPROM produce a more "elegant" design, but system reliability is improved. Every
I--- ADDRESS CYCLE
DATA CYCLE
"-
ALE
<.:>
f
,
z
':i
;::
j
""~
o
~
o
AB-A15
)
ADO-AD7
)
'--y-
--
ADDRESS VALID
""':i'-'
ADDRESS VALID
tLatch
Delay
J
tOecoder Delay
<.:>
z
':i
;::
cr
DATA IN
I-tOE -
...... ,
t ACC
tCE
I
I
rLatch &: tOe coder are 0
for Latched EPROMs
i\." \ \\ \\ \
~
-tOF--
jlff
-- -
::Ii
0
'""'"0
""""
AO-A7
~
LATCHED ADDRESS VALID
0
z
;!
C/)
00-07
)( DATA PINS SEE VALID ADDRESS
DATA OUT
~
292045-4
Figure 3. Propagation delays can be significant when standard EPROMs are used in uC systems.
Latched EPROMs eliminate these delays.
9-83
inter
AP-315
SYSTEM PERFORMANCE
ARCHITECTURE COMPATIBILITY
Latched EPROMs improve system performance. Discrete latches have inherent propagation delays. In a
pure CMOS system, this delay is significant; a
74HCT373 latch delay is 45ns at automotive and military temperatures. A 16MHz 80C31 microcontr~ller,
for example, provides 207ns for EPROM access time.
A 45ns latch delay degrades this access time to 162ns.
An EPROM rated at 160ns or faster must be used.
Figure 3 shows the timing delays inherent in discrete
component solutions.
Intel's latched EPROMs have separate address and
data pins. All address inputs contain latches. This simplifies 16-bit microcontroller interfacing. Pin layout is
virtually identical to standard EPROMs. Upgradecompatible circuit board designs are simplified. In 8-bit
multiplexed address/data systems, EPROM pins AO-7
are connected directly to corresponding DO-7 pins. In
16-bit multiplexed systems, low-byte EPROM data pins
DO-7 are connected to address lines AO-7 while highbyte EPROM data pins DO-7 are connected to address
lines AS-IS. See Figures 7 and 9 for typical 8-bit and
16-bit system examples.
If a latched EPROM is used, no external latch delay
occurs. A 200ns latched EPROM can be used. Access
time parameters include internal latch propagation delays. Slower, less expensive latched EPROMs do the
same job as fast EPROMs and discrete latches.
THE LATCHED EPROM FAMILY
Intel's growing family of latched EPROMs includes the
87C64, 87C257, and 68C257. Ceramic DIP and PLCC
package pinouts are shown in Figures 4 and 5. This
application note shows how latched EPROMs simplify
microcontroller system designs.
// /
87C64
87C257
68C257
\....,/
Vpp
ALE/Vpp
ALE/Vpp
[ 1
A12
,1.12
A12
[ 2
27
A7
A7
A7
[ 3
26
A6
A6
A6
[ 4
A5
A5
A5
[ 5
A4
A4
A4
[ 6.
A3
A3
A3
[ 7
28
J
J
J
A2
A2
A2
AI
AI
AI
[ 9
P
24 P
23 P
22 P
21 P
20 P
AO
AO
AO
[ 10
19
00
00
00
[ 11
01
01
01
[ 12
02
02
02
[ 13
GND
GND
GND
25
[ 8
[
P
P
17 P
16 P
15 P
18
14
""
Vcc
A14
~~
Vee
A14
Vee
PGM
A13
A13
N.C.
A8
A8
A8
A9
A9
A9
All
All
All
OE
OE
OE
Al0
Al0
Al0
CE
CE
ALE/CE
07
07
07
06
06
06
05
05
05
04
04
04
03
03
03
292045-5
Figure 4_ 28-pin ceramic DIP latched-EPROM pinouj:s
9-84
intJ
AP-315
87C64
A7
87C257
A7
A7
68C257
A12
Vpp
DU
A12
ALE/
Vpp
DU
A12
ALE/
DU
Vpp
vee
vee
vee
PGM
NC
A14
A13
A14
A13
nnnnnnn
4
A6 A6 A6
A5 A5 A5
A4
A4 A4
A3 A3 A3
3
2
E
32
31
30
0
5
[
[
1
29
6
28
7
27
8
26
A2 A2 A2
[
9
25
A1
[
10
24
11
23
12
22
13
21
A1
A1
AD AD AD
NC NC NC
00 00 00
[
[
[
14
15
16
17
18
19
20
J
0
0
0
0
J
:5
0
A8 A8 A8
A9 A9 A9
A11 A11 A11
NC NC NC
OE OE OE
A10 A10 A10
CE CE ALE/
CE
07 07 07
06 06 06
UUUUUUU
01
02
GND
DU
03
04
05
01
02
GND
DU
03
04
05
01
02
GND
DU
03
04
05
292045-6
Figure 5. 32-Lead PLCC latched-EPROM pinouts.
9-85
intJ
AP·315
87C64
The 87C64 is a 64K-bit EPROM organized as '81928bit words. Integrated address latches make the 87C64
EPROM unique. This device is functionally identical to
two 74HCT573 latches and a 27C64 EPROM (see Figure 6). However, with latches included, the 87C64 conserves:
•
•
•
•
•
•
•
•
Vpp
+5V
vPP
Vee
87C64
+5V
PGM
Vee
:I:
u
chip count
system performance
board space
power consumption
system cost
inventory
design time
incoming inspection
~3
All
AIO
A9
A8
13",
~~<>
c(
G
CE
ALE/CE
Ai
A6
AS
A4
A3
In discrete component solutions, separate latches are
used with a 27C64 EPROM. Even when the EPROM
is in standby mode, the latches are always active, consuming full power. The 87C64 achieves low standby
power in a novel way. It has a combined ALE/CE signal. When this signal is TTL-high, both the EPROM
and the internal latches are placed in low-power standby mode. Whim ALE/CE is TTL-low, the latches activate, address information is latched, address decoding
begins, and the EPROM is ready to present data at its
outputs.
N.C.
AI2
All
AIO
A9
A8
27C64
EPROM
G
A2
AI
AO
~-+------------~
._------------
s::g ~_~:g S £5 g
292045-7
The 87C64 easily connects to an 80C31 microcontroller. EPROM data pins are connected to its Ao-7 ad-
Figure 6. 87C64 Functional Diagram.
9-86
inter
AP-315
dress pins, which in turn connect to the controller's
ADo-7 pins. ALE/CE must be generated by the processor's ALE signal, as shown in Figure 7. When ALE is
high, a new address can flow into the device's latch.
The address is latched when ALE goes low. EPROM
data is present on ADo_7 when OE goes low.
Using Multiple 87C64s
If mUltiple chips are used in a low power system, address lines and the ALE signal are combined via an
address decoder as shown in Figure 8. Connecting the
ALE signal to the address decoder is important because
the 87C64's ALE/CE input must toggle high-to-low
each time the address changes.
The EPROM contains system operating code. The microcontroller typically accesses sequential addresses as
it executes instructions. Upper address lines are used to
decode memory blocks, but they usually don't change
when sequential addresses are generated. This'means
that the outputs of an address decoder connected to
these lines will not toggle as sequential addresses
change. The address decoder shown in Figure 8 is gated
by ALE to provide the latching signal at the 87C64's
ALE/CE input.
+5V
+5V
i
:==:
vee
-
....-.
'"
0
"-
~
~
-
:==:
:==: '"'"
:==:
:==: -
SOC31
JJ,C
~.O
PO.7
ALE
PSEN
ALE/Vpp
'"
0
"-
!..!..!...
-
~
AI2
AIl
AIO
A9
AS
A07
A06
A05
A04
A03
'--
1 XTAL 2 Vss
EA
-
1-/01-:
+ 5Ve>-j(
?
T
PGM Vpp
I
Vee
DE
PO.6
PO.5
I- PO.4
0
"- PO.3
A02
PO.2
AOI
PO.l
ADO
PO.O
0
l-
RST
P2.6
P2.5
0 P2.4
"P2.3
P2.2
P2.1
N
I-
I>:
+---to
ALE
~EN
P2.7 ~
-
+---to
+---to
I
T T
~7
L
N.C.
AI2
All
AID
A9
AS
A7
A6
A5
A4
A3
A2
Al
AO
DO
01
02
03
04
05
06
07
S7C64
EPROM
GNO
V
Figure 7. The 87C64 easily connects to the 80C31.
9-87
292045-8
intJ
AP-315
292045-9
Figure 8. Multiple latched-EPROMs are controlled by the address decoder.
87C64s in 16-bit Systems
The 87C64 is an ideal memory for word-wide systems.
Two devices provide low-byte and high-byte data. Figure 9 shows an 8096 system that uses two 87C64s.
Microcontroller address/data lines ADI_13 are connected to address inputs Ao-12 on both EPROMs. Address/data line ADo is normally used to select low-byte
data in read/write memories; This line need not,be connected to read-only (EPROM) memories. In order to
operate from external EPROM mapped at low-memory, the 8096's EA pin must be tied to ground.
The low-byte EPROM's DO_7'outputs are connected to
the controller's ADO_ 7 lines. The high-byte EPROM's
DO-7 ou!E!!!s are connected to lines ADS-Is. The controller's RD and ALE lines ar~onnected directly to
both EPROMs' OE and ALE/CE inputs.
In-System Programming
EPROMs are not just read-only memories, they're
user-programmable. That's the reason EPROMs are
the preferred non-volatile memory. EPROMs are usually programmed in PROM programming equipment.
In-system programming, however, is becoming popular
in applications that require factory programming or
field updates.
In-system programming allows the resident microcontroller to program the system's EPROM. A small
amount of the microcontroller's ROM or EPROM can
contain code that knows how to down-load data over
its serial channel and program an 87C64.
In-system programming allows a multi-use module to
be customized for different applications. For example, a
generic robot-control module can be built, installed in
several locations, and customized for any particular job
on an assembly line.
9-88
infef
AP-315
ADI5~~-------------------------------------,
CONTROL
+5V
B096
BOC196
S'c
+5V
292045-10
Figure 9. Two 87C64s provide a no-glue EPROM solution for word-wide systems.
.-----.v
pp
1-'-'---,
PROGRAM
I< LATCH
CONTROL
CIRCUIT
VCC
BOC51
or
B7C51
S'C
o
I;;
o
..
292045-11
Figure 10. A simple in-system programmable module.
9-89
AP-315
and 74'06c keep Vpp an~t 5 volts until programming is initiated. When VPPON goes low, these inverters turn off allowing Vpp and Vee voltages to go to
their programming levels. Vpp and Vee read- and program-voltages are adjusted by the variable resistors
shown. Vee read voltage should be S.OV and its program voltage should be 6.2SV. VPP read voltage should
be S.OV and its program voltage should be 12.7SV.
Figure 10 shows a simple 80CSI-based in-system programmable module. The microcontroller's on-board
ROM or EPROM memory contains the communication and programming algorithms. Port pins P3.0 and
P3.l provide the serial ~mmunication link. P3.2
(EACONT) controls the EA pin. When high (which
occurs at reset and when "I" is written to P3.2), code
operates from internal memory. When low, external
EPROM supplies code. P3.3 (ALECONT) controls the
ALE latching signal during programming. P3.4
(PGMCONT) controls the 87C64's PGM (program
pulse) pin. P3.S (VPPON) controls the Vpp and Vee
programming and operating voltages.
VPPON also controls the ALE circuit. When VPPON
is high, the microcontroller's ALE value passes
through to the 87C64's ALE/CE pin. When VPPON is
low, ALE/CE can be controlled by the microcontroller's ALECONT signal during programming.
Figure II shows the program and latch control circuit.
The 5 volt and 12 volt supplies are connected to this
circuit at all times. Inverter 74'06a allows 12 volts to
pass into the DC/DC converter and the LM317 voltage
regulators only when 5 volts is applied. VPPON is high
at reset or when P3.S contains a "I." Inverters 74'06b
The microcontroller's Ao-12 outputs are connected to
the 87C64's Ao-12 pins. The EPROM's 00-7 are connected to the controller's ADo_ 7 pins. The controller's
program-memory read signal, PSEN, controls the
87C64's output-enable, OE.
2N2907
I
147K
--0
1--.....- ......
+12Vo--~h.
"'----'
vpp TO EPROM
I
=
Read Mode 5.0V
Program Mode 12.7SV
=
+5Vo-......~O...
t-+-....--t-..-00 GND
1----<1_-.....- - 0 Vee TO EPROM
1----'
Read Mode = 5.0V
Program Mode
ALECONTo--------+---~~-~r_~
=6.25V
I,
JC>--¢ ALE/CE
ALE
0---------------1
292045-12
Figure 11. Program- and latch-control circuit for in-system programming.
9-90
AP-315
During programming, the controller brings EACONT
high and VPPON low. This allows it to operate from
internal code, enables programming voltages on the
87C64's Vpp and Vee pins, and switches ALE/CE
control from the controller's ALE to its ALECONT.
It then inputs data over its serial channel. With
ALECONT high, an address is placed on ports 0 and 2.
When ALECONT is brought low, the 87C64 internally
latches the address. Data read from the serial port is
then written to port O. The 87C64 now has both address and data information. The controller needs only
to bring PGMCONT low to program data into the addressed location.
87C257
The 87C257 is a 256K-bit EPROM organized as 32768
8-bit words. It also contains the equivalent of two
74HCT573 address latches. All address inputs are
latched. Figure 12 shows the 87C257's block diagram.
To serve high-performance 8-bit microcontrollers, the
87C257 has separate ALE and CE inputs. The 87C257
is pin compatible with the 27C256 (see Figure 4).
The ALE/VPP input serves as the latch enable during
read mode and as the high voltage input during programming. When ALE is high, address information on
pins AO_l4....!!OWS through -.!!!.e latches to the input decoders. If CE is asserted (CE = Vrd, the EPROM is
in its active mode which allows address decoding to
begin immediately. If CE is high, the 87C257 is in
stand-by mode, but addresses can still be latched. The
address latches retain present address-pin values when
ALE goes low (ALE = Vrd.
The in-system programming sequence is summarized
below.
I) Assert EACONT. Code is now supplied from the
uController's internal program memory.
2) Assert VPPON. This switches Vpp and Vee to their
program voltages and allows the controller to manually control ALE via ALECONT. PGMCONT and
ALECONT are high.
3) Input address and data information from Port 3's
serial channel. Ports 0 and 2 serve as I/O ports.
Place the address on ports 0 and 2. Bring
ALECONT low to latch the address into the 87C64.
4) Write data information to port O.
5) Bring PGMCONT low to program data into the
87C64. See the 87C64 data sheet for the proper programming algorithm and timing requirements.
6) Verify the programmed data. Use the "MOVC
A,@A+DPTR" instruction to read EPROM data.
The configuration shown in Figure 10 allows the
87C64 to be read at any 8K-byte boundary. This
allows the controller to operate using its internal
low-memory code and still verify external EPROM
mapped at the same locations.
7) Repeat this sequence until all EPROM data bytes
are programmed and verified.
8) When programming is complete, VPPON,
PGMCONT, and ALECONT should be de-asserted.
When EACONT = "0", code execution will commence from the 87C64. Duplication of code at identical internal and external memory locations will allow uninterrupted paging between these two memory spaces (see application note AP-284 "Using PageAddressed EPROMs" for further details).
+5V
S7C257
crlr----------------------Vee
A14
A13
A12
All
A10
A9
AS
A14
A13
A12
All
A10
A9
AS
ALE/Vpp-t'---.----t Vpp
G
A7
A6
A5
A4
A3
A2
'Al
AO
Or
GND
27C256
EPROM
A7
A6
A5
A4
A3
A2
Al
AD
Or.....L-------'
Care should be taken during system design to ensure
that microcontroller and other device inputs can handle
elevated voltages supplied by the EPROM during programming. When 6.25V is applied to the 87C64's Veo
its outputs, when "1", will be close to 6.25V.
...... 1D.n...,.....,N_O
OQOCQQQC
292045-13
Figure 12. 87C257 functional diagram.
9-91
AP-315
87C257
+
80C31
The 87C2S7 interfaces to 805 I-family microcontrollers
without "glue" chips. Figure 13 shows a simple
80C31/87C257 system. Note that all 8051-family controllers have similar interfaces. The 80C31's port 0
serves as the multiplexed low-order address/data bus
when used in expanded memory mode; port 2 is the
high-address bus.
Port 0 pins connect directly to the 87C2S7's Ao- 7 and
DO-7 pins. Port' 2 pins are connected to the 87C2S7's
AS-14 and CE pins. Since the 87C2S7 fills the lower
half of the 80C31's program-memory map (OOOOh 7FFFh), address line A15 (P2.7) can be connj!cted to
the 87C257's CE input. The EPROM is selected whenever A15 is low.
The controller's PSEN output is the program (or instruction) memory read-strobe. This pin is connected to
the 87C2S7's output enable pin, OE.
The 80C31's ALE controls an external address latch.
When ALE is high, the controller's port 0 and port 2
pins present address information. When low, addresses
AO-7 are externally latched. The external latch then
supplies the low-address to external memory devices.
Since the 87C257 has its own latch, the 80C3l 's ALE is
connected to the 87C2S7's ALE/VPP (the 87C257's
Vpp function is internally disabled in read mode.
The 80C31's EA (External Access) pin must be connected to ground when accessing external program
memory between addresses OOOOh and OFFFh (the upper address boundary may vary depending on the 8051 .
version used).
+5V
+5V
'j
r
Vee
-
::::
::::
~
0-
'"0
+---+
+---+
+---+
+---+ +---+
+---+
+---+
li
RST
+ SvO-/f
ALE
ALE/Vpp
PSEN
SOC3l
J-'C
cr
A14
A13
A12
All
Al0
A9
~.O
A07
PO.7
AOS
PO.S
AOS
PO.5
0
A04
0- PO.4
A03
0
Q. PO.3
A02
PO.2
AOl
PO.l
AOO
AS
A7
AS
A5
A4
'"
S7C257
EPROM
A3
A2
Al
~.O
1 XTAL 2 VSS
Vee
OE
~EN
A15
P2.7
A14
P2.S
N
A13
0- P2.S
A12
0 P2.4
Q.
All
P2.3
Al0
P2.2
A9
P2.1
AS
'"
Q.
::::
+--+
:::: J
ALE
L
EA
'---:'
AO
00
01
H[]t-.
02
T T.
04
03
05
OS
~7
07
.
GNO
.~
292045-14
Figure 13. A "no-glue" 80C31/87C257 system.
9-92
intJ
AP-315
Two 87C257s
Figure !4 shows two 87C257s in an 80C3! system.
Each 87C257 connects to the 80C3! just as it did in the
87C257 + 80C3! example shown in Figure 13. The
only difference is the inverter between A IS and the second 87C257's CEo This inverter allows the second
87C257 to be selected when AI5 is high - addresses
8000h - FFFFh.
+ 80C31
8051-family controllers are unique in that two 64Kbyte memory spaces can be addressed. These controllers have separate PSEN and RD signals that access
program memory (ROM or EPROM) and data memory (RAM and peripheral devices). All system devices
see the controller's !6-bit address. Depending on the
instruction type, either PSEN or RD is asserted. Although two devices can be memory mapped at identical
locations, PSEN and RD determine which will present
data.
+5V
Vee
+5V
BOC31
B7C257
EPROM
B7C257
EPROM
~C
(OOOOh -7FFFh)
(BOOOh - FFFFh)
o-f f-+-wIr-4-......-+..J
292045-15
Figure 14. A maximum function, but minimum chip, 80C31 system.
9-93
inter
AP-315
+ 8096
Two 87C257s completely fill the 80C3l's program
memory space. 64K bytes are still available in the data
memory space. A system that requires 64K-bytes of
EPROM is probably performing complex 1/0 tasks.
These tasks usually require more RAM than the microcontroller contains. Also, since the 80C31 loses two 8bit 1/0 ports when accessing external memory, port
reconstruction is desirable.
1/0 ports; a powerful CPU, and many other high-per-
The 8155 shown in Figure 14 recovers the lost ports
(plus 6 additional port pins) and supplies 256 bytes of
RAM. In addition, it provides a 14-bit counter/timer.
Connected as shown, the 8155's RAM is mapped at
locations OOOOh - OOFFh. Ports and timer addresses
are mapped at 0100h - 0IFFh. Since the 8155 is not
fully decoded, shadow addresses occur at 512-byte
boundaries.
Figure 15 shows a no-glue 8096/87C257 interface. The
8096's EA (External Access) and Buswidth pins are
tied to ground. This tells the controller that programmemory accesses are from external EPROM and that
the external data bus is 8 bits wide.
The system shown in Figure 14 consists of a high performance microcontroller, 64K-bytes of EPROM: 256
bytes of RAM (in addition to the uC's RAM), 36 1/0
port pins, and an additional timer/counter. The only
"glue" device in this system is the inverter, which can
be made from one transistor and a resistor.
87C257
Intel's 8096-family microcontrollers contain six 8-bit
formance features. 8096BH, 8098, and 80C196 versions
also have 8-bit external bus modes that simplify interfaces to 8-bit memories and peripherals. When used in
expanded mode, ports 3 and 4 supply the multiplexed
addressldata bus.
Port 3 supplies multiplexed address/data information.
Its pins are connected to the 87C257's AO-7 and DO-7
pins. Port 4 supplies addresses AS-15. Its pins are connected to AS-14 and CEo The EPROM is selected
whenever AI5 is low (addresses OOOOh - 7FFFh),
which encompasses the 8096's boot-up and vector locations. RD and ALE are connected to the 87C257's OE
and ALE/VPP pins.
+5V
I
11111111111
.1-I--
:i
:~
'1-I--
:~
I--
:~
'1--
:~
:1=
J
J
I
CONTROL
I'
RO
~:7
P4.6
...
)
;=
:- )
:~
:~
P4.5
... P4.4
'"
~ P4.3
Ii:
~
ALE
P4.2
8098
90C196
8096BH
lAC
(8-BIT MODE)
P4.1
~.O
P3.7
P3.6
'"
Ii:
0
:1=
Il-
P3.5
P3.4
P3.3
+--
P3.2
~
+--
~.O
Vee
P3.1
RST
1 XTAL 2 Vss BW
ALE
ALE/Vpp
RO
Vee
OE
CE
A15
A14
,
A13
A14
A13
A12
A12
A11
A11
A10
A10
A9
A9
A8
A8
A07
A7
A06
A6
A05
A5
A04
A4
A03
87C257
EPROM
A3
A02
A2
A01
A1
ADO
AO
L- DO
' - - 01
EA
02
+5V
03
"t1
1\
-
04
05
06
, 7
07
GNO
V
Figure 15. An 87C257 enhances the powerful 8096.
9-94
292045-16
AP-315
68C257
+SV
The microcomputer industry has a standard for memory and peripheral interfaces which dictates chip-enable
and output-enable polarities. Customers using nonstandard-bus controllers asked Intel to provide a "noglue" EPROM for their applications - the 68C257.
----.
CE-;------1
"""""=
Vee
A14
A13
A12
All
Al0
A9
AS
Like Intel controllers, 68xx-family uCs use multiplexed
address/data pins. However, they differ in two significant ways. First, 68xx controllers use high-memory addresses for reset- and interrupt-vectors. Since A 15 is
high during vector accesses, it can't be connected directly to a standard EPROM's CE - an inverter is
required. Second, read and write controls are functions
of R/W and E (clock output). Fortunately, EPROMs
don't require combinational logic to decode R/W and
E. The active-high E output can sim...£!y be inverted before connecting it to an EPROM's OE input.
AlE/Vpp~-----1~---I
27C2S6
EPROM
A7
AS
AS
A4
A3
A2
Al
AO
The 32K-byte 68C257 EPROM's inputs contain latches, just like the 87C257. The 68C257 also internally
inverts CE and OE. Figure 16 shows the 68C257's
block diagram. Figure 17 shows a no-glue 68C257/
68xx interface.
OE~--~-:-:-I
292045-17
Figure 16. 68C257 functional diagram.
9-95
AP-315
+sV
+sV
r
r
+--+
+--+
+--+
+--+
+--+
-
::::
~
..... E
Als
PC.7
A14
PC.6
u
A13
I- PC.S
A12
0 PC.4
0..
All
PC.3
Al0
PC.2
A9
PC.l
AB
~.O
A07
PB.7
A06
PB.6
ADS
PB.s
II>
I- PB.4 A04
A03
0
0.. PB.3
A02
PB.2
AOl
PB.l
ADO
'"0
'"
0..
--
::::
:::: -
VCC
AS
0
l-
..-.....
..-.....
~
VCC
6BXX
}JoC
«
l-
'"
'"0
0..
+--+
~.O
RESET EXTAL
XTAL VSS
-
HilI-<
+SV
II
h
T T
V
L
ALE/Vpp
OE
CE
A14
A13
A12
All
Al0
A9
AB
A7
A6
AS
6BC2s7
EPROM
A4
A3
A2
Al
AO
DO
01
02
03
04
05
06
07
GNO
V
292045-18
Figure 17. The 68C257 is the "no-glue" EPROM for alternate-architecture micrcontrollers.
SUMMARY
The best system design is small in size, easy to manufacture, highly reliable, and cost effective. Components
that simplify the design process add even more value to
the system.
Intel's latched EPROMs reduce chip count and board
space, enhance performance, increase reliability, minimize design time, and simplify microcontroJler systems.
Latched EPROMs are available in popular 64K- and
256K-bit densities, and a version is available that will
provide a "no-glue" interface to virtually any microcontroller architecture.
9-96
inter
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5850 T.G. Lee Blvd.
SUite 340
Tel: (508) 692-3222
1WX: 710-343-6333
FAX: (508) 692-7867
MICHIGAN
tlntal Corp.
7071 Orchard Lake Road
Suite 100
West Bloomfield 48322
Tel: (313) 851-8096
FAX: (313) 851-8770
MINNESOTA
Intel Corp.
5540 Centerview Or.
Suite 2t5
Raleigh 27606
Tel: (9t9) 851-9537
FAX: (919) 851-8974
OHIO
UTAH
tlntel Corp.
428 East 6400 South
Oayton 45414
Tel: (513) 890-5350
1WX: 810-450-2528
FAX: (513) 890-8658
tlntal Corp.""
25700 Science Park Dr.
Suite 100
Beachwood 44122
CALIFORNIA
OMando 32822
Tel: (407) 240-8000
FAX: (407) 240-8097
Tel: (612 83!;-6722
1WX: 91 -576-2867
FAX: (612) 831-6497
Intel Corp.
MISSOURI
6801 N. Broadway
Suite 115
1~~1 ~~~. City Expressway
Oklahoma City 73162
Tel: (405) 848-8086
FAX: (405) 840-9819
tlntel Corp.
Intel Corp.
21515 Vanowan Street
11300 4th Street North
Suite 116
Suite 170
Canoga Park 91303
Tel: (818) 704-8500
FAX: (818) 340-1144
51. Petersburg 33716
Tel: (813) 577-2413
FAX: (813) 578-1607
tlntel Corp.
GEORGIA
2250 E. Imperial Highway
Suite 218
EI Segundo 90245
Tel: (213) 640-6040
FAX: (213) 640-7133
~nJ~6o
tPioneer Electronics
tHamiitonJAvnet Electronics
1 Keystone Ave., Bldg. 36
Tel: (516) 921-8700
'TWX: 510-221-2184
Cherry Hill 08003
Tel: (609) 424-0110
'TWX: 710-940-0262
tPioneer Electronics
840 Fairport Park
Fairport 14450
tHamiiton/Avnet Electronics
10 Industrial
Fairfield 07006
Tel: (201) 575-5300
'TWX: 710-734-4388
tMTI Systems Sales
37 Kulick Rd.
Fairfield 07006
Tel: (201) 227-5552
tPioneer Electronics
45 Route 46
Pinebrook 07058
Tel: (201) 575-3510
'TWX: 710-734-4382
~o~~~~s;~~:n~~s~~~t 11797
Tel: (716) 381-7070
'TWX: 510-253-7001
NORTH CAROLINA
tArrow ElectroniCS, Inc.
5240 Greensdairy Road
Raleigh 27604
Tel: (919) 876-3132
'TWX: 510-928-1856
tHamiiton/Avnet Electronics
3510 Spring Forest Drive
Raleigh 27604
Tel: (919) 878-0819
tPioneer Electronics
18260 Kramer
Austin 78758
Zenlronics
Bay No.1
3300 14th Avenue N.E.
Tel: (918) 252-7297
tHamllton/Avnet Electronics
Tel: (512) 835-4000
TWX: 910-874-1323
Calgary T2A 6J4
Tel: (403) 272-1021
OREGON
tPloneer Electronics
13710 Omega Road
Dallas 75234
12121 E. 51.1 S1., Suile 102A
Tulsa 74146
tAlmac Electronics Corp.
1885 N.W. 169th Place
Beaverton 97005
Tel: (503) 629-8090
'TWX: 910-467-8746
tHamilton/Avnet ElectroniCS
6024 S.W. Jean Road
Bldg. C, Surte 10
Lake Oswego 97034
Tel: (503) 635-7848
'TWX: 910-455-8179
Wyle Distribution Group
5250 N.E. Elam Young Parkway
Suite 600
Hrllsboro 97124
Tel: (503) 640-6000
'f1IVX: 910-460-2203
Tel: (412) 856-7000
2800 Liberty Ave.
Pittsburgh 15238
Tel: (412) 281-4150
Charlotte 28210
'TWX: 810-621-0366
Pioneer Electronics
259 Kappa Drive
Prttsburgh 15238
OHIO
Tel: (412) 782-2300
'TWX: 710-795-3122
Albuquerque 87123
Hamilton/Avnet Electronics
2524 Baylor Drive S.E.
Albuquerque 87106
Tel: (505) 765-1500
'TWX: 910-989-0614
NEW YORK
Arrow Electronics, Inc.
7620 McEwen Road
Centerville 45459
Tel: (513) 435-5563
'TWX: 810-459-161 I
tArrow Electronics, Inc.
6238 Cochran Road
Solon 44139
Tel: (216) 248-3990
'TWX: 810-427-9409
tPioneer{Technologies Group, Inc.
Delaware Valley
261 Gibralter Road
Horsham 19044
Tel: (215) 674-4000
MANITOBA
Tel: (214) 235-9953
¥{!r(~~4~ ~g~_10:5~
UTAH
Arrow ElectroniCS
1946 Parkway Blvd.
Tel: (801) 972-2800
'TWX: 910-925-4018
Wyle Distributron Group
1325 West 2200 South
Suite E
West Valley 84119
Tel: (206) 643-9992
'TWX: 910-444-2067
Tel: (416) 451-9600
'TWX: 06-976-78
tArrow ElectronIcs, Inc.
10899 Kmghurst
Suite 100
Houston 77099
Wyle Distribution Group
333 Metro Park
Rochester 14623
Tel: (716) 475-9130
'TWX: 510-253-5470
~:r(5~ ~f~~t9900
'TWX: 810-459-1622
tPioneer ElectroniCS
4800 E. 131st Street
Cleveland 44105
Tel: (713) 530-4700
'TWX: 910-880-4439
Tel: (206) 643-3950
15385 N.E. 90th Sireet
Redmond 98052
Tel: (206) 881-1150
WISCONSIN
tArrow Electronics, Inc.
2227 W. Braker Lane
Arrow ElectroniCS, Inc.
200 N. Patrick Blvd., Ste. 100
Austin 78758
Tel: (512) 835-4180
Brookileld 53005
Tel: (414) 767-6600
tZentronics
155 Colonnade Road
Unit 17
Nepean K2E 7K1
Tel: (6'13) 226-8840
Zentronics
60-1313 Border SI.
Winnipeg R3H 0/4
Tel: (204) 694-7957
QUEBEC
tArrow Electronics Inc.
4050 Jean Talon Quest
Montreal H4P 1W1
Tel: (514) 735-5511
TWX: 910-874-1348
lWX: 910·262-1193
'TWX: 05-25590
tHamilton/Avnet Electronics
1807 W. Braker Lane
Austin 78758
Hamilton/Avnet Electronics
2975 Moorfand Road
New Berlin 53151
Arrow Electronics, Inc.
500 Avenue St-Jean Baptiste
Suite 280 .
Quebec G2E 5R9
Tel: (512) 837-8911
'TWX: 910-874-1319
tHamiiton/Avnet Electronics
2111 W. Walnut Hill Lane
Tel: (414) 784-4510
'TWX: 910-262-1182
Tel: (418) 871-7500
FAX: 418-871-6816
Hamilton/Avnet Electronics
2795 Halpern
St. Laurent H2E 7K1
'TWX: 910-860-5929
ALBERTA
'TWX: 610-421-3731
HamiitonJAvnet Electronics
Arrow Electronics, Inc.
tHamilton/Avnet ElectroniCS
4850 Wright Rd., Suite 190
1211 E. 51st SI., Suile 101
Tulsa 74146
Tel: (918) 252-7537
Stafford 77477
Tel: (713) 240-7733
'TWX: 910-881-5523
Zentronics
B17McCaffrey
St. Laurent H4T 1M3
'TWX: 810-422-2211
Tel: (315) 437-0288
'TWX: 710-541- I 560
OKLAHOMA
Tel: (516) 621-6200
Tel: (214) 380-6464
'TWX: 05-349-71
CANADA
tHamilton/Avnet Electronics
103 Twin Oaks Drive
Syracuse 13206
tMTI Systems Sales
38 Harbor Park Drive
Port Washington 11050
Tel: (613) 226-1700
tHamiltonJAvnet Electronics
14212 N.E. 21st Street
Bellevue 98005
Hamilton/Avnet Electronics
4588 Emery Industrial Pkwy.
Warrensville Heights 44128
tHamiiton/Avnet Electronics
tHamiiton/Avnet Electronics
190 Colonnade Road South
Nepean K2E 715
tZentronlcs
8 Tilbury Court
Brampton L6T 3T4
'TWX: 810-450-2531
tPioneer Electronics
4433 Interpolnt Boulevard
Tel: (416) 277-0484
Ken198032
Tel: (206) 575-4420
Arrow Electronics, Inc.
20 Oser Avenue
Hauppauge 11788
~\5Jf~~t~~~
Tel: (416) 677-7432
TEXAS
~;t~~~-~~~
Tel: (614) 882-7004
tHamilton/Avnet Electronics
6845 Rexwood Road
Units 3-4-5
Mississauga L4T lR2
Arrow Electronics, Inc.
19540 68th Ave. South
'TWX: 910-443-2469
777 Brooksedge Blvd.
Tel: (416) 673-7769
'TWX: 06-218213
'TWX: 510-665-6778
'TWX: 910-860-5377
Westerville 43081
Arrow Electronics, Inc.
1093 Meyerside
Mississauga LST 1M4
Hamilton/Avnet Electronics
6845 Rexwood Rd., Unit 6
Mississauga L4T 1R2
~:r(5~ ~:~~-6733
tHamiiton/Avnet Electronics
Tel: (613) 226-6903
WASHINGTON
tAl mac Electronics Corp.
14360 S.E. Eastgate Way
Bellevue 98007
tArrow Electronics, Inc.
3220 Commander Drive
Carrollton 75006
Hamilton/Avnet
933 Motor Parkway
Hauppauge 11788
ONTARIO
Arrow Electronics, Inc.
36 Antares Dr.
Nepean K2E 7W5
'TWX: 610-492-8867
tHamiiton/Avnet Electronics
954 Senate Drive
Tel: (216) 349-5100
'TWX: 810-427-9452
Zentronics
60-1313 Border Unit 60
Tel: (801) 974-9953
tArrow ElectroniCS, Inc.
3375 Brighton Henrietta
Townline Rd.
Rochester 14623
Tel: (516) 231-1000
'TWX: 510-227-6623
Tel: (604) 273-5575
'TWX: 04-5077-89
Wyle Distribution Group
1810 GreenVIlle Avenue
Richardson 75081
tHamiltonJAvnet Electronics
1585 West 2100 South
Salt Lake City 84119
NEW MEXICO
Tel: (505) 292-3360
Tel: (713) 988-5555
'TWX: 910-881-1606
Tel: (801) 973-6913
Alliance Electronics Inc.
'TWX: 910-989-1151
Zentronics
108-11400 Bridgeport Road
Richmond V6X 1T2
Salt Lake City 84119
~k~~e:~[;~t~~~~O~\~~ ~f~~.P. Inc.
Tel: (919) 527-8188
Tel: (604) 437-6667
tPioneer Electronics
5853 Point West Drive
Houston 77036
PENNSYLVANIA
Hamilton/Avnet Electronics
11030 Cochlli S.E.
Tel: (214) 386-7300
'TWX: 910-850-5563
Arrow Electronics, Inc.
650 Seco Road
Monroevrlle 15146
'TWX: 510-928-1836
BRITISH COLUMBIA
tHamiiton/Avnet Electronics
105·2550 Boundary
BurmaJay V5M 3Z3
Tel: (216) 587-3600
tMicrocomputer System Technical Distributor Center
~~I~~2~~~~O-6111
2816 21s1 Streel N.E.
Calgary T2E 6Z3
Tel: (403) 230-3586
'TWX: 03-827-642
Tel: (514) 335-1000
Tel: (514) 737-9700
'TWX: 05-827-535
EUROPEAN SALES OFFICES
DENMARK
Intel Denmark AlS
Glentevej 61, 3rc:! Floor
2400 Copenhagen NV
m~:(t~5~~1) 19 80 33
WEST GERMANY
ISRAEL
NDRWAY
SWITZERLAND
Intel Semiconductor GmbH*
Intel Semiconductor Ltd.1II:
Atidim Industrial Park-Neve Sharet
P.O. Box 43202
Tel·AvIv 61430
Tel: (972) 03-498080
TLX: 371215
Intel Norway NS
2013 SkJetten
Tel: (47) (6) 842420
TLX: 78018
Intel Semiconductor A.G.
ZUerichstrasse
8185 Winkel-RueH bei Zuerich
Tel: (41) 01/860 62 62
TLX: 825977
ITALY
SPAIN
UNITED KINGDOM
Intel Corporation ltalia S.p.A.1II:
Mllanofiori Palazzo E
Intel Iberia SA
Zurbaran,28
28010 Madrid
Tel: (34) (1) 308.25.52
TLX: 46880
SWindon, ~iltshire SN3 1RJ
Tel: (44) (0793) 696000
TLX: 444447/8
Dornacher Strasse 1
8016 Feldkirchen bel MUenchen
Tel: (49) 089190992·0
TLX: 5·23177
Intel Semiconductor GmbH
Hohenzollern Strasse 5
3000 Hannover 1
Tel: (49) 0511/344081
TLX: 9-23625
FINLAND
Intel Finland QY
Ruosilantie 2
00390 Helsinki
Tel: (358) 0 544 644
Tl.X: 123332
Intel Semiconductor GmbH
Abraham Uncaln Strasse 16-18
FRANCE
Intel Corporation S.A.R.L.
1. Rue Edison-B? 303
78054 St. Quentin-en- Yvelines
Cedex
Tel: (33) (1) 30 57 70 00
TLX: 699016
6200 Wiesbaden
Tel: (49) 06121/7605.()
TLX: 4·186183
Intel Semiconductor GmbH
Zetlachring 10A
7000 Stuttgart 80
Tel: (49) 0711/7287-280
TLX: 7-254826
20090 Assago
Milano
+~: (~~1 ~~
89200950
Hvamveien 4-PO Box 92
NETHERLANDS
SWEDEN
Intel Semiconductor B.V,·
Postbus 84130
3099 CC Rotterdam
Tel: (31) 10.407.11.11
TLX: 22283
Intel Sweden A.B.'"
~~~~~,ff.0ratlon (UK) Ltd. *
Dalvagen 24
17136 Solna
Tel: (46) 8 734 01 00
TLX: 12261
EUROPEAN DISTRIBUTORS/REPRESENTATIVES
AUSTRIA
Bacher Electronics G.m.b.H.
Rotenmuehlgasse 26
1120Wien
Tel: (43) (0222) 83 56 46
TLX: 31532
BELGIUM
Inelco Belgium S.A.
Av. des Croix de Guerra 94
1120 Bruxelles
?lo~ga~~~:rnlaan, 94
Tel: (32) (02) 216 01 60
TLX: 64475 or 22090
DENMARK
ITT-Multikomponent
Naverland 29
2600 Glostrup
Tel: (45) (0) 245 66 45
TLX: 33355
Tekelec-Airtronic
Cite des Bruyeres
Rue Carle Vemet - BP 2
92310 Sevres
Tel: (33) (1) 45 34 75 35
TLX: 204552
Lasl Elettronica S.pA
V. Ie Fulvlo Testl, 126
20092 Cinlsello Balsamo (MI)
Tel: (39) 02/2440012
Tl.X: 352040
ITT Multikomponent GmbH
PosHach 1265
Bahnhofstrasse 44
7141 Moegllngen
Tel: (49) 07141/4879
TLX: 7264472
Telcom S.r.l.
Via M. Civilali 75
20148 Milano
Tel: (39) 02/4049046
TLX: 335654
.
OV Flntronic AS
Melkonkatu 24A
00210 Helsinki
Tel: (358) (0) 6926022
TLX: 124224
Metrologle GmbH
Meglingerstrasse 49
8000 Muenchen 71
Tel: (49) 089/78042.()
TLX: 5213189
Proelectton Vertrlebs GmbH
Max Planck Strasse 1-3
6072 Dreieich
Tel: (49) 06103/30434·3
TLX: 417903
IRELAND
~I;~ag~~~c~t~ark
Jermyn-Generim
60, rue des Gemeaux
SIIIc580
94653 Rungis cedex
Tel: (33) (1) 49 78 49 78
TLX: 261585
Glenageary
Co. Dublin
Tel: (21) (353) (Ot) 85 63 25
TLX: 31584
Metrologle
Tour d'Asnleres
4, avo Laurenl~Cely
92606 Asnieres Cedex
Tel: (33) (1) 47 90 62 40
TLX: 611448
Eastronlcs Ltd.
11 Rozanis Street
P.O.B.39300
Tel-Aviv 61392
Tel: (972) 03-475151
TLX:33638
*Field Application Location
ISRAEL
Dttram
Avenlda Miguel Bombarda, 133
1000 Usboa
•
Tel: (35) (1) 54 53 13
TLX: 14182
SPAIN
TLX: 311351
Electronic 2000 AG
Stahlgruberring 12
8000 Muenchen 82
Tel: (49) 089/42001-0
TLX: 522561
-FINLAND
Almex
Zone industrielle d'Antony
48, rue de l'Aubeplne
BP 102
92164 Antony cedex
:::~i~gbbU746 66 21 12
~~g~~~j~31
WEST GERMANY
Jermyn GmbH
1m Dachsstueck 9
6250 limburg
Tel: (49) 06431/508·0
TLX: 415257-0
FRANCE
ITALY
Intest
Divislone m Industries GmbH
Vlale Mtlanofiori
Palazzo E/5
ATD Electronica, S.A.
Plaza Ciudad de Viena, 6
28040 Madrid
• Tel: (34) (1) 23440 00
TLX: 42477
ITT-SESA
~~roMJla~e~t"gel.
21-3
Tel: (34) (1) 419 09 57
TLX: 2746t
Metrologla Iberica. SA.
etra. de Fuencarral, n.80
28100 Alcobendas (Madrid)
Tel: (34) (1) 653 8611
ITT Multicomponents
Viale Milanofiorl E/5
~~~~~8~~j~31
TLX: 311351
SWEDEN
Silverstar
Via Dei Gracchi 20
20146 Milano
Tel: (39) 02/49961.
TLX: 332189
Nordlsk Elektronlk AB
Torshamnsgatan 39
Box 36
164 93 Kista
Tel: (46) 08·03 46 30
TLX: 10547
NETHERLANDS
Koning en Hartman Elektrotechniek
B.V.
Energieweg 1
2627 AP Delft
Tel: (31) (0) 151609906
TLX: 38250
SWITZERLAND
NORWAY
TURKEY
Nordisk Elektronikk (Norge)
Postboks 123
Smedsvingen 4
1364 Hvalstad
Tel: (47) (02) 84 62 10
Tl.X: 77546
PORTUGAL
ATD Portugal LDA
Rua Dos Lusiados, 5 Sala B
1300 Usboa
Tel: (35) (1) 64 80 91
Tl.X: 61562
NS
Industrade A.G.
Hertislrasse 31
8304 Wallisellen
Tel: (41) (01) 8328111
TLX: 56788
EMPA Electronic
Lindwurmstrasse 9SA
8000 Muenchen 2
Tel: (49) 089/53 SO 570
TLX: 528573
~~~~~e~:b:~~:ms
Western Road
Bracknell RG121RW
Tel: (44) (0344) 55333
Tl.X: 847201
Jermyn
Vestry Estate
OHord Road
Sevenoaks
Kent TN14 5EU
Tel: (44) (0732) 450144
TLX: 95142'
MMD
Unit 8 SouthvIew Park
Caversham
Readln~ .
Berkshire RG4 OAF
Tel: (44) (0734) 481666
TLX: 846669
Rapid Silicon
Rapid House
Denmark Street
High Wycombe
. BuckinijhamShlre HP11 2ER
+~: (~~7~~94) 442266
Rapid Systems
Rapid House
Denmark Street
High Wycombe
Buckinghamshire HP11 2ER
Tel: (44) (0494) 450244
TLX: 837931
YUGOSLAVIA
H.R. Microelectronics Corp.
2005 de la Cruz Blvd., Ste. 223
Santa Clara. CA 95050
U.S.A.
Tel: (1) (408) 988·0286
TLX: 387452
Rapido Electronic Components
UNITED KINGDOM
S.p.a.
Accent Electronic Components Ltd. Via C. Beccaria. 8
34133 Trieste
Jubilee House, Jubilee Road
Letchworth. Herts SG6 HL
. ltalla
Tel: (44) (0462) 686666
Tel: (39) 040/360555
TLX: 826293
TLX: 480461
INTERNATIONAL SALES OFFICES
AUSTRALIA
INDIA
Intel Australia Pty. Ltd.'"
Spectrum BUlIdint
Intel Asia Electronics, Inc.
~~~:sa~:;t~EI 200~
6
4/2, Samrah Plaza
BRAZIL
8t. Mark's Road
Bangalore 560001
Tel: 011-91·8t2·215065
TLX: 9538452875 DCBV
FAX: 091-812-215067
Intel Semicondutores do Brazil LTDA
Av. Paulista. 1159-CJS 404/405
JAPAN
Tel: 612-957-2744
FAX: 612-923-2632
01311 - Sao Paulo· 5.P.
Tel: 55·11-287-5899
TLX: 39111531461SDB
FAX: 55-11-287-5119
• CHINA/HONG KONG
Intel PRC Corporation
15/F, Office 1, Citic Bldg.
Jlan Guo Men Wal Street
Beijing, PRC
Tel: (1) 500-4850
TLX: 22947 INTEL CN
FAX: (1) 500-2953
Intel Semiconductor Ud.'"
1OIF East Tower
Bond Center
Queensway, Central
Hong Kong
Tel: (5) 8444-555
TLX: 63869 ISHLHK HX
FAX: (5) 8681-989
Intel Japan K.K
5-6 Takodai, Tsukuba·shi
Ibara!
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