1991_Fujitsu_Dynamic_RAM_Products 1991 Fujitsu Dynamic RAM Products

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Dynamic RAM Products
1991 Data Book

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NMOS DRAMs
CMOS DRAMs
Application-Specific DRAMs
Quality and Reliability
Ordering and Package Information
Sales Information
Appendices - Design Information

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cP

FUJITSU

Dynamic RAM Products
1991
Data
Book

Fujitsu Umited
Tokyo, Japan
Fujitsu Microelectronics, Inc.
Son Jose, California, U.S.A.
Fujitsu Mikroelektronik GmbH
Frankfurt, Germany
Fujitsu Microelectronics Asia PTE Umited
Singapore

Copyrighl© 1991 Fujitsu Microelectronics, Inc., San Jose, California
All Rights Reserved.
Circuit diagrams using Fujitsu products are included to illustrate typical semiconductor applications. Information sufficient lor
construction purposes may not be shown.
The information contained in this document has been carefully checked and is believed to be reliable. However, Fujitsu
Microelectronics, Inc. assumes no responsibility for inaccuracies.
The information conveyed in this document does not convey any Ncense under the copyrights, patent rights or trademarks
claimed and owned by Fujitsu Limited, its subsidiaries, or Fujitsu Microelectronics, Inc.
Fujitsu Microelectronics, Inc. reserves the right to change products or specifications without notice.
No pan of this publication may be copied or reproduced in any form or by any means, or transferred to any third party without prior
written consent of Fujitsu Microelectronics, Inc.
This document is published by the Publications Department Fujitsu Microelectronics, Inc.,
3S45 North First Street San Jose, California, U.S.A. 95134-1804; U.S.A.
Printed in the U.S.A.
Edition 1.0

PREFACE
This data book contains the latest product information for Fujitsu's line of DRAM les. This year's edition,
however, does not include a section for DRAM modules. Both DRAM and SRAM modules are now in a
Modules Data Book which you can obtain from your nearest Fujitsu Sales Office or Sales Rep. (See the
Sales Information listing in this book.)
In addition to the collection of DRAM data sheets, you will find valuable information on ordering and
expanded packaging descriptions, both in the Order Information section.
The Design Information section contains two new technical papers. The 3D Stacked Capacitor Cell for
Mega Bit DRAM is a reprint of a technical paper from the Fujitsu Scientific and Technical Journal. We
are pleased to be able to include an article from this highly respected journal. The second new paper is
The Soft Error Rate for 4M DRAM Devices, a significant article on these new DRAM devices.
If you are interested in obtaining other Fujitsu product information, you will find the publications listing on
the following pages quite useful. Once again, call one of our sales offices to obtain a copy of any of the
documents.

"'

FUJITSU PRODUCT PUBLICATIONS
The following is a list of the product publications available from Fujitsu. Call your nearest Fujitsu Sales Office or Sales
Representative to order any document(s) you need. (See the Sales Information section for phone numbers.)

MEMORY PRODUCTS
Dynamic RAM Products Data Book

Contains product data sheets for NMOS and CMOS DRAMs,
including 1M and 4M devices, and MOS application-specific
RAMs.

Static RAM Products Data Book

Contains product data sheets for high-speed CMOS and
BiCMOS SRAMs, low-power CMOS SRAMs and applicationspecific SRAMs.

ECl RAM Products Data Book

Contains product data sheets for ECl and TTl bipolar ECl
RAMs, BiCMOS ECl RAMs, and application-specific RAMS
including self-timed RAMs (STRAMs).

Programmable Memory Products Data
Book

Contains product data sheets for programmable ROMs (including
registered and wide-temperature range PROMs); CMOS maskprogrammable ROMS, OTP ROMs, erasable PROMs, and EEPROMs; NMOS erasable PROMs and non-volatile RAMs.

Memory Modules Data Book

Contains product data sheets for CMOS DRAM modules (including high density and low profile) and CMOS SRAM modules.

Memory Card Products Data Book

Contains product data sheets and programming information for
68-pin JEIDA and PCMCIA standard memory cards and connectors and for 38-pin memory cards.

Power Transistor Products Data Book

Contains product data sheets for RETs, Darlington arrays, and
FETs.

Linear Products Data Book

Contains product data sheets for op amps, comparators, automotive audio amps, power supply controls, motor drivers, disk drivers, and converters (AID, DIA, AID-D/A, and FN).

Linear Products Selector Guide

Presents an overview of linear products.

Telecommunication Devices Data Book

Contains product data sheets for bipolar prescalers and VCOs,
CMOS PlLs, BiCMOS single-d1ip PlLs and Prescalers,
CODECs, CMOS telephone ICs, and cellular mobile radio ICs.

Telecommunication Devices Selector
Guide

Presents an overview of telecommunication products and piezoelectric devices.

Interface and Logic Products Selector
Guide

Presents an overview of logic and interface devices.

CMOS 4-bit Microcontrollers Data Book,
Vol. I

Contains product information, including the development tool for
the MB8850 and MB88200 families of 4-bit microcontrollers.

CMOS 4-bit Microcontrollers Data Book,
Vol. II

Contains product information, including the development tool for
the MB88500 family of 4-bit microcontrollers.

CMOS 4-bit Microcontrollers Selector
Guide

Presents an overview of the MB88500 (high end), MB8850 (midrange), and MB88200 (low end) families of 4-bit microcontrollers.

Iv

FUJITSU PRODUCT PUBLICATIONS (Continued)
ASIC PRODUCTS
CMOS Channeled Gate Arrays Data Book
and Design Evaluation Guide

Contains product information for UHB Series High Drive CMOS
Gate Arrays and CG10 Series High Drive CMOS Gate Arrays.

CMOS Channelless Gate Arrays Data
Book and Design Evaluation Guide

Contains product information for AU Series CMOS Series Gate
Arrays and CG21 Series CMOS Gate Arrays.

CMOS Standard Cell Data Book and
Design Evaluation Guide

Contains product information for AU Series Standard Cells.

ASIC CMOS Products Selector Guide

Presents an overview of CMOS channeled and channelless gate
arrays and standard cell products.

BiCMOS Gate Arrays Data Book and
Design Evaluation Guide

Contains product information for BC Series BiCMOS Gate
Arrays and BC-H Series BiCMOS Gate Arrays.

ECl Gate Arrays Data Book and Design
Evaluation Guide

Contains product information for ET Series ECl Gate Arrays, H
Series ECl Gate Arrays, Ultra-High Performance ECl Gate
Arrays, and VH Series ECl Gate Arrays.

ASIC Bipolar Products Selector Guide

Presents an overview of BiCMOS and ECl gate array products.

ASIC SOFTWARE
The ASIC Gallery (catalog)

Discusses the trend in ASICs: migration from using gates as
primitives to using lSI and even VlSI macros as design elements.

The ASIC Design Environment (catalog)

Provides an overview of the third-party tools that work in concert
with Fujitsu's proprietary tools, ViewCADTM, BankCADTM,
ZephCAD, and FAME. Also included are product profiles explaining how the third-party tools fit within the design framework.

ViewCAD User's Guide

Provides a basic understanding of Fujitsu's proprietary CAD/CAE
system, ViewCAD. This book provides information necessary to
design, test, simulate, and analyze circuits using Fujitsu's unit cell
libraries for AU, UHB, CG10, CG21, and CG31 CMOS technologies.

ViewCAD Installation Guide

Explains how to install Fujitsu's proprietary CAD/CAE system,
ViewCAD.

CMOS ASIC Reference Manual for
Validation

Provides a basic understanding of the Valid System on the Sun
platform as it interfaces with Fujitsu programs to build circuits
using Fujitsu's unit cell libraries for AU and UHB CMOS technologies.

FAME User's Guide

Provides a basic understanding of the Fujitsu ASIC Management
Environment (FAME) software as it interfaces with third-party
tools (Sun or PC) to build circuits using Fujitsu's unit cell libraries.

FAME Reference Manual

Provides installation and directory information for the Fujitsu
ASIC Management Environment (FAME) software, which uses
third-party tools (Sun or PC) to build circuits using Fujitsu's unit
cell libraries.

Synopsys User's Guide

Provides a basic understanding of the Synopsys® system as it
interfaces with Fujitsu programs to build circuits using Fujitsu's
unit cell libraries.

v

FUJITSU PRODUCT PUBLICATIONS (Continued)
ASIC SOFTWARE (Continued)
Verilog-XL User's Guide

Provides a basic understanding of the Verilog-XL® system as it
interfaces with Fujitsu programs to build circuits using Fujitsu's
unit cell libraries.

Future Publications

For Fujitsu Microelectronics, Inc.:
Master Product GuidelCatalog (1991)

Presents an overview of the entire range of products offered by
Fujitsu Microelectronics.

For Memory Products:
Hybrid Products (1991)

Presents Fujitsu's hybrid products and discusses thick- and thin-film
capabilities.

For ASIC Software:
ASIC Design Environment
Data Book (1991)

Provides detailed information about the ASIC Design Methodology
at Fujitsu. It contains an overview of the third-party tools that work
in concert with Fujitsu's proprietary tools, ViewCAD, BankCAD,
ZephCAD, and FAME. Also included are product profiles explaining
how the third-party tools fit within the design framework.

ASICOpen™ Catalog (1991)

Provides a small-scale ASIC Design Methodology at Fujitsu. It
explains the design processes between two third-party tools, Synopsys and Verilog-XL, and Fujitsu's proprietary tools, ViewCAD,
BankCAD, and ZephCAD.

Synopsys® is a registered trademark of Synopsys, Inc.
Verilog-XL® is a registered trademark of Cadence Design Systems, Inc.
ViewCAOTI. and BankCAOTM are trademarks of Fujitsu Umited.
ASICOpenTi• is a trademark of Fujitsu Microelectronics, Inc.
vi

Contents and Alphanumeric Product List
DRAM PRODUCTS
Introduction -

DRAM Products .......................................... xi

Section 1 - NMOS DRAMs -

At a Glance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Section 2 - CMOS DRAMs -

1-1

262144 x 1 bit DRAM ......................... 1-3
262144 x 1 bit DRAM ........................ 1-25
262144 x 1 bit DRAM ........................ 1-45
262144 x 1 bit DRAM ........................ 1-69
65536 x 4 bits DRAM ......................... 1-93

MB81256-1 0/-121-15
MB81256-80
MB81257-10/-121-15
MB81257-80
MB81464-10/-121-15

At a Glance. . . . . . . . . . . . . . . . . . . . . . . . . . . ..

MB81C1 000-70/-80/-1 0/-12
MB81C1000-70U-80U-10U-12L
MB81C1000A-60/-70/-80/-10
MB81C1000A-70U-80U-10L
MB81 C1 001-70/-80/-1 0/-12
MB81C1001-70U-80U-10U-12L
MB81 C1 001 A-60/-70/-80/-1 0
MB81C1001A-70U-80U-10L
MB81 C4256-70/-80/-1 0/-12
MB81C4256-70U-80U-10U-12L
MB81 C4256A-60/-70/-80/-10
MB81C4256A-70U-80U-10L
MB8141 00-80/-1 0/-12
MB814100-80U-10U-12L
MB814101-80/-10/-12
MB814101-80U-10U-12L
MB814400-80/-10/-12
MB814400-80U-10U-12L

Section 3 - MOS Application-Specific RAMs MB81461-121-15
MB81461B-121-15
MB81C1501

Section 4 - Quality and Reliability -

2-1,2-2

1048576 x 1 bit Fast Page Mode DRAM ........... 2-3
1048576 x 1 bit Fast Page Mode Low Power DRAM 2-25
1048576 x 1 bit Fast Page Mode DRAM .......... 2-47
1048576 x 1 bit Fast Page Mode Low Power DRAM 2-71
1048576 x 1 bit Nibble Mode DRAM ............. 2-95
1048576 x 1 bit Nibble Mode Low Power DRAM .. 2-117
1048576 x 1 bit Nibble Mode DRAM ............ 2-139
1048576 x 1 bit Nibble Mode Low Power DRAM .. 2-163
262144 x 4 bits Fast Page Mode DRAM ......... 2-187
262144 x 4 bits Fast Page Mode Low Power DRAM 2-211
262144 x 4 bits Fast Page Mode DRAM ......... 2-235
262144 x 4 bits Fast Page Mode Low Power DRAM 2-261
4M x 1 bit Fast Page Mode DRAM ............. 2-287
4M x 1 bit Fast Page Mode Low Power DRAM ... 2-307
4M x 1 bit Nibble Mode DRAM ................ 2-309
4M x 1 bit Nibble Mode Low Power DRAM ...... 2-329
1M x 4 bits Fast Page Mode DRAM ............ 2-331
1M x 4 bits Fast Page Mode Low Power DRAM .. 2-353

At a Glance .....................

3-1

NMOS 65536 x 4 bits Dual-Port DRAM ............ 3-3
NMOS 65536 x 4 bits Dual-Port DRAM ........... 3-35
CMOS 293760 x 4 bits Triple-Port DRAM ......... 3-67

At a Glance .........................

4-1

Quality Control at Fujitsu ................................................... 4-3
Quality Control Processes at Fujitsu .......................................... 4-4

vii

Contents and Alphanumeric Product List (Continued)
DRAM PRODUCTS
Section 5 - Ordering and Package Information - At a Glance . ..................

5-1

Product Marking ..........................................•.............. 5-3
Ordering Code (Part Number) ............................................... 5-3
Package Codes - Plastic .................................................. 5-4
Package Codes - Ceramic ................................................. 5-5

Section 6 - Sales Information - At a Glance . ............................. 6-1
Introduction to Fujitsu ..................................................... 6-3
Fujitsu Limited (Japan) ................................................. 6-3
Fujitsu Microelectronics, Inc. (U.S.A.) ...................................... 6-4
Fujitsu Electronics Devices Europe ......•................................ 6-6
Fujitsu Microelectronics Asia PTE Ltd. (Singapore) ........................... 6-8
Integrated Circuits Corporate Headquarters - Worldwide .......................... 6-9
FMI Sales Offices for North and South America ................................ 6-10
FMI Representatives- USA ............................................... 6-11
FMI Representatives - Canada ............................................. 6-13
FMI Representatives - Mexico ............................................. 6-13
FMI Representatives - Puerto Rico ......................................... 6-13
FMI Distributors - USA ................................................... 6-14
FMI Distributors - Canada ................................................ 6-18
FMG Sales Offices for Europe, FML and FM IL ................................. 6-19
FMG Distributors - Europe, FML and FMIL ................................... 6-20
FMAP Sales Offices for Asia, Australia, and Oceania ............................ 6-22
FMAP Representatives - Asia and Austraila .................................. 6-23
FMAP Distributors - Asia ................................................. 6-24

Section 7 - Appendices - Design Information -At a Glance . ................
Appendix 1. Application Note:
Appendix 2. Application Note:
Appendix 3. Technical Paper:

viii

7-1

Various Features of Fujitsu DRAMs ............... 7-3
The Soft Error Rate for 4M DRAM Devices ........ 7-27
3D Stacked Capacitor Cell for Mega Bit DRAM ..... 7-35

Contents and Alphanumeric Product List

(Continued)

DRAM PRODUCTS

Alphanumeric List of Fujitsu Part Numbers
MB81256-10/-121-15 ............. 1-3
MB81256-80 .................. 1-25
MB81257-10/-121-15 ............ 1-45
MB81257-80 .................. 1-69
MB81461-121-15 ................ 3-3
MB81461B-121-15 .............. 3-35
MB81464-10/-121-15 ............ 1-93
MB814100-80/-10/-12 ..........
MB814100-80U-10U-12L .......
MB814101-80/-10/-12 ..........
MB814101-80U-10U-12L .......
MB814400-80/-10/-12 ..........
MB814400-80U-10U-12L .......

2-287
2-307
2-309
2-329
2-331
2-353

MB81C1000-70/-80/-10/-12 ........ 2-3
MB81C1000-70U-80U-10U-12L ... 2-25
MB81C1000A-60/-70/-80/-10 ..... 2-47
MB81C1000A-70U-80U-10L ...... 2-71
MB81C1001-70/-80/-10/-12 ....... 2-95
MB81C1001-70U-80U-10U-12L .. 2-117
MB81C1001A-60/-70/-80/-10 .... 2-139
MB81C1001A-70U-80U-10L ..... 2-163
MB81C1501 ................... 3-67
MB81C4256-70/-80/-10/-12 ......
MB81C4256-70U-80U-10U-12L ..
MB81C4256A-60170/-80/-10 .....
MB81C4256A-70U-80U-10L .....

2-187
2-211
2-235
2-261

Ix

x

Introduction

Page

TItle

xIII

Fujitsu's Dynamic RAMs

xi

Introduction

xii

Dynamic RAM Data Book

Fujitsu's Dynamic RAM Products
Introduction

Fujitsu manufactures a wide range of integrated circuits that
includes linear products, microprocessors,
telecommunications circuits, ASICs, high-speed ECl logic,
power components (consisting of both discrete transistors
and transistor arrays), and both static and dynamic RAMs.
An extensive line of memory products includes volatile and
non-volatile CMOS and ECl devices.
Fujitsu's Dynamic RAM product line offers devices for use in
a wide range of applications. These memories are
manufactured to meet the high standard of quality and
reliability that is found in all Fujitsu products.
This data book includes product information on all of Fujitsu's
currently available DRAM products.
NMOS and CMOS DRAMs

Fujitsu manufactures a complete family of leading technology
dynamic random access memories for the data processing,
telecom, and industrial markets. This family consists of the
highest density devices currently available with a broad
selection of organizations, access modes, and packages.
Application-Specific DRAMs

Fujitsu offers a family of multi-port dynamic random access
memories tailored for video imaging and graphics
applications. These devices adhere to JEDEC standards
where applicable and are available in the popular packages.

xiii

xlv

Section 1

NMOS DRAMs -

At a Glance

Page

Device

Maximum
Access
Time (ns)

1-3

MB81256-10
-12
-15

100
120
150

262144 bits
(262144 x 1)

16-pin
16-pin
18-pin
18-pad

Plastic
Ceramic
Plastic
Ceramic

DIP,ZIP
DIP
PLCC
LCC

1-25

MB81256-80

80

262144 bits
(262144 x 1)

16-pin
16-pin
18-pin

Plastic
Ceramic
Plastic

DIP,ZIP
DIP
PLCC

1-45

MB81257-10
-12
-15

100
120
150

262144 bits
(262144 x 1)

16-pin
16-pin
18-pin
18-pad

Plastic
Ceramic
Plastic
Ceramic

DIP,ZIP
DIP
PLCC
LCC

1-.09

MB81257-80

80

262144 bits
(262144 x 1)

16-pin
16-pin
18-pin

Plastic
Ceramic
Plastic

DIP,ZIP
DIP
PLCC

1-93

MB81464-12
-15

120
150

262144 bits
(65536 x 4)

18-pin
18-pin
20-pin

Plastic
Ceramic
Plastic

DIP, PLCC
DIP
ZIP

Capacity

Package
Options

1-1

NMOS DRAMs

1·2

Dynamic RAM Data Book

cO

February 1990
Edition 5.0

FUJITSU

DATA SHEET

MB81256-101-121-15
MOS 262, 144 BIT DYNAMIC RANDOM ACCESS MEMORY
262,144 Bit Dynamic Random Access Memory
The Fujitsu MB81256 is a fully decoded, dynamic NMOS random access
memory organized as 262,144 one-bit words. The design is optimized for high speed,
high performance applications such as mainframe memory, buffer memory, peripheral
storage, and environments where low power dissipation and a compact layout are
required.
Multiplexed row and column address inputs permit the MB81256to be housed in
standard 16-pin DIP and ZIP packages or an 18-pin PLCC package. Pinouts conform
to JEDEC-approved pinouts. Additionally, the MB81256 offers new functional
enhancements that make it more versatile than previous dynamic RAMs. tmS-beforeroffi" refresh provides an on-chip refresh capability that is upwardly compatible with the
MB8266A. The MB81256 also features page mode which allows high speed random
access of up to 512 bits of data within the same row.
The MB81256 is fabricated using silicon gate NMOS and Fujitsu's advanced
Triple-layer Polysilicon process. This process, coupled with single-transistor memory
storage cells, permits maximum circuit density and minimal chip size. DynamiC
circuitry is used in the design, including the sense amplifiers. Clock timing
requirements are noncritical, and power supply tolerance is very Wide. All inputs are
TTL compatible.

·

• 262,144 x 1 RAM organization
:,c:~:uTriple Poly NMOS, single

• 256 refresh cydes every 4 ms

• Row Access lime
100 ns max. 1MB 81256- 10
120 ns max. MB 81256-12
150nsmax. MB81256-15

• High speed Read-whilB-Write cyde
• IAR, tWCR. toHR, IRwo ere eliminated
• Output unlatched ~e end allows
twcHIimensionai chip select
• Common I/O capability using
Ealiy Write operation
• On-dlip latches lor Addresses and
Date-in
• Standard 16-Pin Plastic Packages:
DI!JMB81256-XXPI
ZIP MB81256-XXPSZ)
Stan
IS-Pin Plastic PaCkage:
PLCC(MB81256-XXPV)
Standard 16-Pin Ceramic Packeges:
DIUMB81256-XXC) SeemWeid
DIP MB81256-XXZ) Cerdip
Stan
18-Pad Ceramic Package:
LCC (MB81256-XXTV)

1

• Cycle lime
200 ns min. 1MB 81256-10)
22Onsmin. MB81256-12!
260 ns min. MB 81256-15
• Page Cycle TlIIle
100 nsmax. (MB81256-101
120 ns max. (MB 81256-12)
145 ns max. (MB 81256-15)
• Single +5 V Supply, ±10% tolerance
• LowPower
385 mW max. 1MB 81256-10
358mWmax. MB81256-12
314 mW max. MB81256-15
25 mW max. (standby)

1

PLASTIC PACKAGE
DlP-16P-M03

PLASTIC PACKAGE
LCC-18P-M04

tI

.~~=:nIY,

PLASTIC PACKAGE
ZIP-16P-M01
DIP·16C·A03:
Dlp·16C·A04:
Dlp·16C-C04:
LCC·18C·F04:

See Page 17
See Page 18
See Page 19
See Page 24

PIN ASSIGNMENT

Absolute Maximum Ratings
Param_
Voltage al any pin relatiw 10 Vss
Voltage of Vee supply relative 10 Vss
Storage Temperature
Power Dissipation
Short Circuit Output Current
_ :

I

Ceramic

I

Plastic

Symbol

Value

VIN. VOUT

-110 +7

V

Vee

-110 +7

V

TSlO

-5510 +150

°c

UnlI
[1~6

DOUT
~I!i A6
TOP VIEW p_4 NC
"3 A3

[lj

-5510 +125
Po

1.0

-

50

A4

:8 ~ 9-:;O~li~
AI \ A1AS

Vee

W
mA

Permanent device damage may occur if absolute maximum ratings ere exceeded.
Functional operation shoUld be restricted 10 Ihe conditions as detailed in the operation
sections of this data sheet Exposure to absolute maximum rating conditions fOr extended periods may effect devICe reliability.

Pin assignment for ZIP: See Page 21
ThII _ _ cIraIIIryto_f1elnpoa l1li_
_ d u o to high ....lcvalageoor _ _ .
II acMud Ihat normal pnIC8IOIon& be _
to avoid appII_

_.1

01 any W>Itago high.. \han maximum _

voIagoo .. thll high

Irq>odanoo ci"aJ1t.

Ccpjright@ 11180 by FWITSU LIMITED and Fujillu MIc....IodJonIco.1nc.

1-3

MB81256-10
MB81256-12
MB81256-15

Fig. 1 - MB 81256 BLOCK DIAGRAM

CAS

--~--------t-LJ---q

r

r1---_--11

1

L-/

CLOCK GEN.

NO.2

+
INTERNAL
ADDRESS
COUNTER

AO-

:~=

nL

~

~------------~

1

SENSE AMPS
110 GATING

r-...L...'-l----4...J

1
L... A
"..,/
,If"

~i3J ~ _
iii~8

C».J_

OATA
IN
BUFF.

COLUMN
DECODER

f-------

-DIN

I

A

~j===========~t "
DATA
OUT
BUFF.

A 3-

r--DOUT

262,144 BIT
STORAGE CELL

--Vee

-Vss

CAPACITANCE

(TA = 25°C)

Parameter

Symbol

Typ

Max

Unit

Input Capacitance Ao to As, DIN

CIN1

7

pF

Input Capacitance RAS, CAS, WE

CIN2

10

pF

COUT

7

pF

Output Capacitance DouT

1-4

MB81256-10
MB81256-12
MB81256-15

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Symbol

Parameter

Min

Typ

Max

Unit

Vcc

4.5

5.0

5.5

V

Vss

0

0

0

V

Input High Voltage, all inputs

V 1H

2.4

6.5

V

Input Low Voltage, all inputs

V 1L

-2.0

0.8

V

Supply Voltage

Operating
Temperature

O°C to +70°C

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Value
Parameter

Symbol

Unit
Min

OPERATING CURRENT"
Average Power Supply Current
(RAS, CAS cycling; tRc = Min.)

REFRESH CURRENT I"
Average Power Supply Current
(RAS cycling, CAS = V 1H ; t RC = Min.)
PAGE MODE CURRENT"
Average Power Supply Current
(RAS = V 1L , CAS cycling; t pc = Min.)
REFRESH CURRENT 2"
Average Power Supply Current
(CAS·before.RAS; tRc = Min.)

65

Icc1

MB 81256·15

STANDBY CURRENT
Standby Power Supply Current
(RAS, CAS=V 1H )

4.5

5.5

Icc3

MB 81256·15

mA

50

MB 81256·10

35
30

Icc4

MB 81256·15

25

MB 81256·10

65

MB 81256·12

mA

60

MB 81256·10

MB81256·12

mA

57
Icc2

MB 81256·12

Max
70

MB 81256·10
MB 81256·12

Typ

60

Iccs

MB 81256·15

mA

mA

55

INPUT LEAKAGE CURRENT any input (V 1N = OV to
5.5V, Vcc = 5.5V, Vss = OV, all other pins not under test = OV)

II(L)

-10

10

/lA

OUTPUT LEAKAGE CURRENT (Data is disabled,
V OUT = OV to 5.5V)

lOlL)

-10

10

/lA

OUTPUT LEVEL Output Low Voltage (lOL = 4.2 mAl

VOL

0.4

V

OUTPUT LEVEL Output high Voltage (lOH = -5.0 mAl

V OH

NOTE

2.4

Icc is depended on output loading and cycle rates. Specified values are obtained with the output open.

V

1-5

MB81256-10
MB81256-12
MB81256-15

AC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Parameter

IIiID!J

MB 81256·10

MB 81256·12

MB 81256·15

Min

Min

Min

Symbol

Unit
Max

Max

Time between Refresh

tREF

Random Read/Write Cycle Time

t Rc

200

220

260

Read·Write Cycle Time

t RWC

200

220

260

Access Time from RAS

11111

t RAC

Access Time from CAS

mill

t CAC

Output Buffer Turn off Delay

tOFF

Transition Time
RAS Precharge Time
RAS Pulse Width

4

4

100

4

60

ms
ns
ns

150

120

50

Max

ns

75

ns

0

25

0

30

ns

3

50

3

50

ns

0

25

tT

3

50

tRP

85

tRAS

105

RAS Hold Time

tRSH

55

CAS Pulsp Width

tCAS

55

CAS Hold Time

tCSH

105

tRCO

20

CAS to RAS Set Up Time

tCRS

10

10

10

ns

Row Address Set Up Time

t ASR

0

0

0

ns

Row Address Hold Time

tRAH

10

12

15

ns
ns

RASto CAS Delay Time

I iii

90
100000

120

100
100000

60

100000

120
50

22

ns
100000

75

60
100000

150

75

100000

150
60

25

ns
ns
ns
ns

75

ns

Column Address Set Up Time

tAsc

0

0

0

Column Address Hold Time

tCAH

15

20

25

ns

Read Command Set Up Time

tRcs

0

0

0

ns

Read Command Hold Time Referenced
to CAS

iii

tRCH

0

0

0

ns

Read Command Hold Time Referenced
to RAS

iii

tRRH

20

20

20

ns

Write Command Set Up Time

III

twcs

0

0

0

ns

Write Command Pulse Width

twp

15

20

25

ns

Write Command Hold Time

t WCH

15

20

25

ns

Write Command to RAS Lead Time

t RWL

35

40

45

ns

tCWL

35

40

45

ns

tos

0

0

0

ns

tOH

15

20

25

ns

t cwo

15

20

25

ns

Refresh Set Up Time for CAS Referenced
to RAS (CAS·before·RAS cycle)

t FCS

20

20

20

ns

Refresh Hold Time for CAS Referenced to RAS
(CAS·before·RAS cycle)

t FCH

20

25

30

ns

Write Command to CAS Lead Time
Data In Set Up Time
Data In Hold Time
CAS to WE Delay

1-6

1111111-'

III

MB81256-10
MB81256-12
MB81256-15

..

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)
Parameter

Symbol

MB 81256·10

MB 81256·12

MB 81256·15

Min

Min

Min

Max

Max

Unit

Max

CAS Precharge Time (CAS·before·RAS cycle)

tCPR

20

25

30

ns

RAS Precharge to CAS Active Time
(Refresh cycles)

t RPC

20

20

20

ns

Page Mode Read/Write Cycle Time

tpc

100

120

145

ns
ns
ns

Page Mode Read·Write Cycle· Time
Page Mode CAS Precharge Time
Refresh Counter Test Cycle Time
Refresh Counter Test RAS Pulse Width
Refresh Counter Test CAS Precharge Time

...
..

tpRWC

100

120

145

tcp

40

50

60

t RTC

330

375

430

230

265

t TRAS
t CPT

50

10000

10000

60

320
70

ns
10000

ns
ns

Notes:

II An

initial pause of 200 /JS is required after power·up.
And then several cycle (to which any 8 cycle to per·
form refresh are adequate) are required before proper
device operation is achieved.
If internal refresh counter is to be effective, a mini·
mum of 8 CAS before RAS refresh cycles are required.

I
BI
I

AC characteristics assume tT = 5 ns.
V'H (min) and V'L (max) are refrence levels for mea·
suring timing of input signals. Also, transition times
are measured between V'H (min) and V'L (max.).
Assumes that tRco ~ tRCO (max.) If tRCO is greater
than the maximum recommended value shown in this

table, tRAC will increase by the amount that tRCO
exceeds the value shown.

II
I

Assumes that tRco ~ tRCO (max.).
Measured with a load equivalent to 2 TTL loads and
100 pF.

I

I

Operation within the tRCO (max) limit insures that
t RAC (max) can be met. tRCO (max) is specified as a
reference point only; if tRCO is greater than the
specified tRCO (max) limit, then access time is con·
trolled exclusively by t CAC .
tRco (min) = tRAH (min) + 2tT (tT = 5ns) + tAsc
(min).

I Either tRRH or tRCH must be satisfied for a read cycle.
II twcs and t cwo are not restrictive operating para·
meters. They are included in the data sheet as elec·
trical characteristics only. If twcs ~ twcs (min),
the cycle is an early write cycle and the data out pin
will remain open circuit (high impedance) throughout
entire cycle.
If t cwo ~ tcwo (min) the cycle is a read·write cycle
and data out will contain data read from the selected
cell. If neither of the above sets of conditions is satis·
fied the condition of the data out is indeterminate.

II Test mode cycle only.

1-7

MB81256-10
MB81256-12
MB81256-15

Read Cycle
~------------------tRC-------------------------i
~---------------tRAS--------------__~

tCSH
'____-r--------tRsHI--------~
VIH- --~:Ir_;_t--------y--,. ~-----tCASI-------I

r-:-Ir-----------

VIL-

ADDRESSES

VIHVIL _ '

~:: - <,t;1~~i/:tt-,':c.:_':_"_________ L~C:----tC-A-C------__t
DOUT

I::

VOH~~V~A~L~I~D~-~~_________
VOL ,----------------HIGH-Z--------------(J
DATA
.1-

E:I Don't Cere

Write Cycle (Early Write)

VIH-

VIL-~~~~_

VOH
DOUT
VOL -

1-8

_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HIGH_Z _ _ _ _ _ _ _ _ _ _ _ _ _ __

D

Don't Cere

MB81256-10
MB81256-12
MB81256-15

Read-Write/Read-Modify-Write Cycle

RAS

V'HV'ltCSH

tRSH

,----~~--------------tCAS--------------~

CAS

V'HV'l-

ADDRESSES

~:::

WE

V'HV'l-

DOUT

VOHVOl-

D'N

V'H- __
____________________________
----------------------------------~\t
~ALID
V'l-

DATA

I·t------tRAC---I.:'t~O.
SHIIID<~'to"'--H

----"r

~~

~'~ATA

________________
~----------------

~

o

Don't Car.

Page Mode Read Cycle
~------------------------tRAS,--------------------------1

RAS

V'H-

~====~SH:=======~::==~~====::~~
teAs

CAS

V'HV'l-

ADDRESSES

V'HV'l-

DOUT

VOHVOltACH

iNE

J@

l--tRCS

V'H ------~--------~r_~--------~II~--------------cr--V'l-

o

Don'teare

F?d V.lid Data
1-9

MB81256-10
MB81256-12
MB81256-15

Page Mode Write Cycle

ADDRESSES

V1H -

VIL-------~;t:t4=::~--------~++::::~~------~~--~~~;,:~~----------------

VOH-_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ HIGH_Z _ _ _ _ _ _ _ _ _ _ _ _ _ __

VOL

D

Don't Care

Page Mode Read-Write Cycle

RAS

VIH V1L-

CAS

VIW
VIL -

VIH ADDRESSES V IL

WE

VIH VIL-

DOUT

Vow
VOL-

DIN

VIW
VIL-

o
1-10

Don'teare

MB81256-10
MB81256-12
MB81256-15

R"AS-only Refresh cycle
NOTE: WE, DIN = Don't care, As

= V IH

or V IL

~----------------tRC------------------1
V 1H -

RAS

V1L -

f-------tRP-------I

VtH-

ADDRESSES
lAo to A71

VILVIH-

CAS

V 1L -

V OH DOUT

V OL -

D

Don'teare

CAS-before-RAS Refresh Cycle

NOTE: Address, WE, DIN = Don't care

f---------------tRC-------------~

RAS

CAS

DOUT

V IH V IL-

,-____________~

~-------tRAS'-----~

~----------_w

VIHV 1L -

V OH V OL -

J>------------------------H IGH-Z---------------------------

o

Don'teara

1-11

MB81256-10
MB81256-12
MB81256-15

Hidden Refresh Cvele

RAs

V'HV'L-

CAS

V'HV'L-

ADDRESSES

WE IRead)

V1HV 1L-

DOUT

WE (Read·Write)

V 1H-

V'L-

COon'tea,.

~befor&-RAS

RAS

Ref.... h Counter Test Cycle

VIHV 1L-

CAS

ADDRESSES

WfIReadl

DOUT

WEIWrite)

D,N

V 1H-

V1L-

VIHV 1L-

VOL-

V 1HVIL-

V,
V 1L-

D
1-12

Don't C.,.

MB81256-10
MB81256-12
MB81256-15

DESCRIPTION
Simple Timing Requirement
The MB B1256 has improved circuitry
that eases timing requirements for high
speed access operations. The MB 81256
can operate under the condition of
tRCO (max) = t CAC thus providing
optimal timing for address multiplexing.
In addition, the MB 81256 has the
minimal hold time of Address (tCAH l.
WE" (tWCH) and DIN (to H ). The
MB 81256 provides higher through·
put in inter-leaved memory system
applications. Fujitsu has made timing
requirements that are referenced to
RAS nonrestrictive and deleted them
from the data sheet, these include tAR,
t WCR , tOHR and tRWO· As a result,
the hold times of the Column Address,
DIN and WE as well as t cwo (CAS to
WE Delay) are not ristricted by tRco.
Address Inputs:
A total of eighteen binary input address
bits are required to decode any 1 of
262,144 cell locations with in the
MB 81256. Nine row-address bits are
established on the input pins (Ao
to As) and are latched with the Row
Address Strobe (RAS). Nine columnaddress bits are established on the input
pins and are latched with the Column
Address Strobe (CAS). All row addresses must be stable on or before the
falling edge of RAS. CAS is internally
inhibited (or "gated") by RAS to
permit triggering of CAS as soon as the
Row Address Hold Time (t RAH) specification has been satisfied and the
address inputs have been changed from
row-addresses to column-address.

CAS, 0 IN is strobed by CAS, and the
set-up and hold times are referenced to
CAS. In a read-write cycle, WE can be
delayed after CAS has been low and
CAS to WE Delay Time (tcwo) has
been satisfied. Thus DIN is strobed by
WE, and set-up and hold times are
referenced to Wi:.
Data Output:
The output buffer is three-state TTL
compatible with a fan-out of two
standard TTL loads. Data out is the
same polarity as data-in. The output is
in a high impedance state until CAS is
brought low. In a read cycle, or readwrite cycle, the output is valid after
t RAC from transition of RAS when
tRCO (max) is satisfi~ after t CAc
from transition of CAS when the
transition occurs after t~ (max).
Data remain valid until CAS is returned to a high level. In a write cycle
the identical sequence occurs, but data
is not valid.

Fast Read-While-Write cycle
The MB 81256 has a fast read while
write cycle which is achieved by precise
control of the three-state output buffer
as well as by the simplified timings
described in the previous section.
The output buffer is controlled by the
state of WE" when CAS goes low. When
WE" is low during CAS transition to low,
the MB 81256 goes into the early write
mode in which the output floats and the
common I/O bus can be used on the
system level. Whereas, when WE goes
low after tcwo following CAS transition to low, the MB 81256 goes into the
delayed write mode. The output then
Write Enable:
contains the data from the cell selected
The read mode or write mode is selected
and the data from DIN is written into
with the M input. A high on WE
the cell selected. Therefore, a very fast
selects read mode; low selects write
read write cycle (tRWC = t RC ) is
mode. The data input is disable when possible with the MB 81256.
read mode is selected.
Data input:
Data is written into the MB B1256 during a write or read-write cycle. The later
falling edge of WE or CAS is a strobe for
the Data In (DIN) register. In a write
cycle, if WE is brought low before

Page Mode:
Page-mode operation permits strobing
the row-address into the MB 81256
while maintaining RAS at a low throughout all successive memory operations
in which the row-address doesn't change. Thus the power dissipated by the

falling edge of RAS is saved. Access and
cycle times are decreased because the
time normally required to strobe a new
row address is eliminated.
Refresh:
Refresh of the dynamic memory cells is
accomplished by performing a memory
cycle at each of the 256 row-addresses
(Ao to A7) at least every 4ms. The
MB 81256 offers the follOWing 3 types
of refresh.
RAS-only Refresh;
RAS-only refresh avoids any output
during refresh because the output
buffer is in the high impedance state
unless CAS is brought low.
Strobing each of 256 row-addresses
(Ao to A7) with RAS will cause all bits
in each row to be refreshed. Further
RAS-only refresh results in a substantial
reduction in power dissipation. During
RAS-only refresh cycle, either V IH or
V IL is permitted to As.
CAS-before-RAS Refresh;
CAS-before-RAS refreshing available on
the MB 81256 offers an alternate
refresh method. If CAS is held "low"
for the specified period (tFCS) before
RAS goes to "low", on-ehip refresh
control clock generators and the refresh
address counter are enabled, and an
internal refresh operation takes place.
After the refresh operation is performed, the refresh address counter is
automatically incremented in preparation for the next CAS-before-RAS
refresh operation.
Hidden Refresh;
A hidden refresh cycle may takes place
while maintaining the latest valid data
at the output by extending CAS active
time.
For the MB 81256 a hidden refresh is
a CAS-before-RAS refresh cycle. The
internal refresh address counters provide the refresh addresses, as ina normal
CAS-before-RAS refresh cycle.
CAS-before-~ Refresh Counter Test
Cycle:
A special timing sequence using CAS-

1-13

MB81256-1 0
MB81256-12
MB81256-15

before-RAS counter test cycle provides
a convenient method of verifying the
functionality of the CAS-before-RAS
refresh activated circuitry_
After the CAS-befor-RAS refresh operation, if CAS goes to high and then
goes to low again while RAS is held low,
the read and write operations are
enabled.
This is shown in the CAS-before- RAS
counter test cycle timing diagram.
A memory cell address (consisting of a
row address (9 bits) and column address
(9 bits) to be accessed can be defined
as follows:
*A ROW ADDRESS - Bits Ao to A7

are defined by the refresh counter.
The bit As is set high internally.
*A COLUMN ADDRESS - All the bits
Ao to Ae are defined by latching
levels on Ao to Ae at the second
falling edge of CAS.

(3)
(4)

Suggested CAS-before-RAS Counter
Test Procedure
The timing as shown ,in the CAS-beforeIfAS Counter Test cycles is used for
the following operations:
(1) Initialize the internal refresh address counter by using eight CASbefore-RAS refresh cycles.
(2) Throughout the test, use the same

(5)
(6)

column address, and keep RAS
high.
Write "low" to all 256 row address on the same column address
by using normal early write cycles.
Read "low" written in step 3) and
check, and simultaneously write
"high" to the same address by using
internal refresh counter test readwrite cycles. This step is repeated
256 times, with the addresses being
generated by internal refresh address counter.
Read "high" written in step 4) and
check ,by using normal read cycle
for all 256 locations.
Complement the test pattern and
repeat step 3), 4) and 5).

Fig_ 2 - CURRENT WAVEFORM (VCC=5.5V, TA = 25°C)

RAS/CAS Cycle

Hidden Refresh Cycle

Page Mode Cycle

RA5-only Refresh Cycle

RAS --"
CAS

«
E
u

160
120

2

80
40

-

A
\

A

~J

/"r-f--

~

\
\
\
,
/'
\ 1\,./ ~
Ilia ~
rIAl
AI
V
'v
~v \ 'r-I
\..
\..
J
I\..
1\.1
IJU L
U N
I'-.< "
SOns/Division

1·14

~

I-

MB81256-10
MB81256-12
MB81256-15

TYPICAL CHARACTERISTICS CURVES
Fig. 3 - NORMALIZED ACCESS TIME
vsSUPPLY VOLTAGE
w

::;;
j:::

gj

U

~
o
w
N

::;

..:
~
o
z

o

«
If

.s<
Iz
w
a:
a:

::>

w

.......

o

«

~

w

/

0.8
-20
0
20
40
60
80 100
T A. AMBIENT TEMPERATURE (oC)

Fig. 5 - OPERATING CURRENT
vsCYCLE RATE

Fig. 6 - OPERATING CURRENT
vs SUPPL Y VOLTAGE

60

ve~=5.5J
50 r- =25°C

/~

TA

/

40

V

/V

30

/

20
10
0

<
.s
IZ

so
70

T)25°C

I

r- tRe=200ns

w

a:
a:

~

60

::>
u

"z

50

j:

..:
a:

w

40

V ""

V

/"

a.

/

0

U

2

30
20

4
2
3
5
litRe. CYCLE RATE (MHz)

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE (V)

Fig. 7 - OPERATING CURRENT
vs AMBIENT TEMPERATURE

Fig. 8 - STANDBY CURRENT
vs SUPPL Y VOLTAGE

<
.s

T)25°C
5

I-

60~~---+---r--~--+-~
5Of-~---+--~--~--+-~

4of---;f--t---t----+---+---I

Q.

o

0.9

4.0
5.0
6.0
Vee SUPPLY VOLTAGE (V)

j:

o

..:

~

./

V

If

z

~

1.0

./

o

.sI-

a

~

::;

<
w
~

1. 1

z

0

2

8..:
o

O.S

Q.

0

1.2

w

0.9

j:

..:
a:

en

"-i'-

1.0

u

"z

:;;

~

f'...

1. 1

Ve~=5.0J

w

TA!25°C
1.2

w

Fig. 4 - NORMALIZED ACCESS TIME
vs AMBIENT TEMPERAUTRE

30f-~r--t---t----+---+---I

z
w
a:
a:

::>
u

>ID
o
z
..:
t;;
N
u

4
3
2

1

2

~ 20

-~2~0~0~~20~~4~0--~6~0--±SO~~100
T A. AMBIENT TEMPERATURE (oC)

4.0
5.0
6.0
Vee, SUPPLY VOLTAGE (V)

1-15

MB81256-10
MB81256-12
MB81256-15

Fig. 10 - REFRESH CURRENT 1
vs CYCLE RATE

Fig. 9 - STANDBY CURRENT
vs AMBIENT TEMPERATURE

.s...
zw
II:
II:

6

>ID
o

3

~

2

Z

N
u

;;(

.s

50

w

40

...z

4

:>
(J

60

VC~=5.5J

;;(

--

t--

II:
II:

:>

r--

u

::t

'"w

II:

LL
W

1

OJ
u

80

...

70

w

60

;;(

I

.s...

T)250 C
-tRc=200ns

zw

Z

(J

'"

II:
LL

II:

ex:

50
40

II:

..... .,.........

...........

I!)

:~

30
20

;;(
Z
w

~

:>

.E
4~

5~

~O

~

30

",..,

20
10

V

o

V

/

Fig.14-REFRESH CURRENT 2
vsCYCLE RATE

60

I

I

;;(

tPc=l00ns
5 0r- TA =25°C

40

60

.s

50

w

40

...'"z

II:
II:

~yJ5.5J
TA=25°C

:>

llJ
f

20

(J

~~

~~

::t

'"w

II:

IL

30
20

W

II:

.,;,

0

o

u

V
./

V

/

.V

10

.E
4.0

5.0

6.0

Vcc. SUPPLY VOLTAGE (V)

1-16

40

Fig. 13 - PAGE MODE CURRENT
vs SUPPLY VOLTAGE

30

~

A

2
4
6
8
10
l/tpc. CYCLE RATE (MHz)

~

.E

I .!

ycc=5~5V
50 f- T
=25 C

Vcc. SUPPLY VOLTAGE (V)

(J

o:;;

w

o

o
:;;

w

V

.E

.s...

60

(J

W

OJ
u

1
2
3
4
5
l/tRC. CYCLE RATE (MHz)

:>

:>
::t

,/

Fig. 12 - PAGE MODE CURRENT
vsCYCLE RATE

Fig. 11 - REFRESH CURRENT 1
vs SUPPLY VOLTAGE

w

V

10
0

0
20
40
60
80 100
TA. AMBIENT TEMPERATURE (oC)

II:
II:

20

/

/"

.E
-20

;;(

30

II:

.E

.s

f-VJ5.sJ
TA =25°C

0

1
2
345
l/tRC. CYCLE RATE (MHz)

MB81256-10
MB81256-12
MB81256-15

«
E
N

so

T)250C

70

f60

~-

u

50

v>W
",

V"'"

V>

w

a:

40

a:

..;
u

./

,,/"

%

w":
a:f-

0-'
00

..:>
~~
>0..

1.0

..:
l:

;;
6.0
5.0
4.0
Vee. SUPPLY VOLTAGE IV)

Fig. 17 - ADDRESS AND DATA INPUT
VOLTAGE vs AMBIENT TEMPERATURE

Fig. 18 - RAS. CAS AND WE INPUT
VOL TAGE vs SUPPLY VOLTAGE

3.0

3.0

Ve~=5.0J

TA=125°C

I~
o

~~

2.0

VIHIMin.l

w..:
~~

00

..:>
':'f-

;;ir

VILIMax.l

~ ~
I u..:

2. 0

I a:~~~0
.>

--- VIHI~in.l

f-

VILIMax.l

-'f-

-;; ir

1.0

1.0

Oz

OZ

z-

z..:

..:
I

I

-;;

;;

o

20
0
20
40
60
80
100
T A • AMBIENT TEMPERATURE 1°C)

Fig. 19 - RAS. CAS AND WE INPUT
VOLTAGE vs AMBIENT TEMPERATURE
3.0

I~

..s

Z..:~

IV>
w 2.0
":Cl

VIH Min.l

Iv>-'
.

V>
V>

f-

w

":0

>~ 1.0

VILIMax.l

Oz
Z-

u
u

..:
U


-'f-

f-

.~ ~IMax.l

4.0
5.0
6.0
Vee. SUPPLY VOLTAGE IV)

~
o
o

~~

10-

Z

30
20

V> w
V>Cl

-

,....

o~

~

..:

2.0

V>Cl

::::>

u..
w

T)25°C

o

r- tRe=200ns

..:~

a:
a:

l:

3.0

..:
f..:

I

Z

w

Fig. 16 - ADDRESS AND DATA INPUT
VOL TAGE vs SUPPL Y VOLTAGE

Fig. 15 - REFRESH CURRENT 2
vs SUPPL Y VOLTAGE

--

f--

-

~ r-

100 200 300 400 500
C L • LOAD CAPACITANCE IpF)

1-17

MB81256-10
MB81256-12
MB81256-15

Fig. 21 - OUTPUT CURRENT
vsOUTPUT VOLTAGE

1

~ 250

T A 25°C

!

/

IZ

w 200

U

II:
II:

:J

u 150

I:J
I:J

100

j

50

0.

0

.2

I
V

kt:
~

r--

Fig. 22 - OUTPUT CURRENT
vs OUTPUT VOLTAGE
~

!

I-

~

Vcc =4.5V-

~

1

T A 25°C
-125

II:
II:

::>

c:J

II

-100
-75

I-

::>

l=
::>

o
:i:
o

>->
.J-

"'w
o.CJ

~~
0.J
00

»

:[371 11 1 1
f-T A =25°C

>-~

1

15

RAS=CAS=VSS

.J E

0.0.1-

:JZ

v>w

.11:
011:

2::>

u

F

10
5

0

t

V

>->
.J -

o.w
o.CJ

iil.~
u.J

»uO

RAs=oo=lcc

I

O,I VIH -

I

'\ ~

1
2
3
4
5
VOH. OUTPUT VOLTAGE (V)

:ffi
o

~>

CJ

-2

,,0

-3

::»

i\.\

Fig. 24 - SUBSTRATE VOLTAGE
DURING POWER UP

1

~~
V>.J

'\.'i\

-25

w

11:I-w

"",CC=5.5V

JCCi4.5V

o

V>

50p.s/Division

1-18

J

I"

-50

1
2
3
4
5
VOL. OUTPUT VOLTAGE (V)

Fig. 23 - CURRENT WAVEFORM
DURING POWER UP

["-.

-

\

I I I I

TA =25°C

l\..
"'-..

:J'
SOilS/Division

MB81256-10
MB81256-12
MB81256-15

PACKAGE DIMENSIONS
Standard 16·pin Ceramic DIP (Suffix: -C)

DIP·16C·A03

16·LEAD CERAMIC (METAL SEAL)DUAL IN·LINE PACKAGE
(CASE No.: DIP·16C·AD3)

W

·20015.08IMAX

.134±.014
(3.40±O.36)

.100±.OlD
(2.S4±O.25)

.032±.012
10.81±0.301
.700(17.78)REF

.047~:~6~(1.20~~:~~)

© 1988 FUJITSU LIMITED 016035S-3C

Dimensions in

inches (millimeters)

1-19

MB81256-10
MB81256-12
MB81256-15

PACKAGE DIMENSIONS
Standard 16-pin Ceramic DIP (Suffix: -C)

DIP-16C-A04

16-LEAD CERAMIC (METAL SEAL) DUAL IN-LINE PACKAGE
(CASE No.: DIP-16C-A04)

_-__ ~l 00t09
~~Tf

0

.300'.010

_=:l!:::=j=~:;:';!I7J.251
.0431 I .09ITVP
1.4 PLCSI

U

.2ooI5.08IMAX

.134'.014
13.40.0.361
.100'.010
12.54'0.251

Cl1988 FUJITSU LIMITED D16044S·2C

1-20

.035 •.015
10.89.0.361

Dimensions in
inches (millimeters)

MB81256-10
MB81256-12
MB81256-15

PACKAGE DIMENSIONS
Standard 16-pin Ceramic DIP (Suffix: -Z)

DIP-16C-C04

16-LEAD CERAMIC (CERDIP) DUAL IN-LINE PACKAGE
(CASE No. : Dlp·16C-C04)

.100:1;.010

(2.54' 0.251

.018~:~~:
(O.46~g:~~)
@1988 FUJITSU LIMITED 016032S-4C

Dimensions in
inch" (millimeters)

1-21

MB81256-10
MB81256-12
MB81256-15

PACKAGE DIMENSIONS
Standard 16-pin Plastic DIP (Suffix: -PI
16-LEAD PLASTIC DUAL IN-LINE PACKAGE
(CASE No.: DIP-16P-M031
r-766+·008 (1945+0.20)~
r"1' -.012 . -0.30 n,

Ir-,

rll

.050 (1.27)

.100 (2.54)

MAX

TYP

-++----'7'=
Dimensions in
inches (millimeters)

40 1988 FUJITSU LIMITED D16000S-3C

Standard 18-pin Plastic LCC (Suffix: -POI
til-LEAD PLASTIC LEADED CHIP CARRIER
(CASE No_: LCC-t8P-M041
.322±.OO5
(8.18±O.131

~
(7.2 i')~1!8i )

i'

.025(0.64) MIN

F~

P-

p-

INDEXl

--+-!!~

b

(12.45±O.OB)

itJJ
~~

.00410.,011

1

.t:::~~
:I

.468± .020
111.89.0.511

l!;;;;;;~

R.030tO.75)TYP
150(3.81)

.026(0.66)

I

TVP

@:
40 1980 FUJITSU LIMITED C180198-1C

1-22

l.EADNo.

Dlmenlionlin
Inch.. (mIIl!"8lOI1I)

MB81256-10
MB81256-12
MB81256-15

PACKAGE DIMENSIONS
Standard 16-pin Plastic ZIP (Suffix: -PSZ)
PIN ASSIGNMENT

LEAD
No.1

16

ZIP-16P-M01

16 LEAD PLASTIC ZIGZAG-IN-LINE PACKAGE
(CASE No.: ZIP-16P-M01)
008
+020
.803 +
-:012120.40 -0:30)

.I

I

INDEX

~
.020±.004
10.50±0.10)

.312±.013
17.93±0.33)

'- I-

?~--

.010±.002
(0.25±0.05)

I

.05011.27)
TYP
LEAD

.t

.260±.010
16.60±0. 25)

d
II

I 12± 008
12.85±0.20)

.118(3.00) MIN

--.l
. I 0012.54) TYP
IROW SPACE)

NO.~

ULtlr----..-O------0---,o.,...........,o....----.or-~-......--.

OUUUU_
IBOTTOM VIEW)

@
Dimensions in

. 1 _ FUJITSU LIMITED ZleoolS~

inches (millimetres)

1-23

MB81256·10
.MB81256·12
MB81256·15

PACKAGE DIMENSIONS
Standard l8-pad Ceramic LCC (Suffix: -TV)

LCC-18C-F04

l8-PAD CERAMIC (FRIT SEAL) LEADLESS CHIP CARRIER
(CASE No_: LCC-18C-F04)
.070(1.78)

PIN NO.1 INDEX

\
b

n
.48502.32)
.50002.70)

TYP

.280(7.11)
.295(7.49)

*Shape of Pin 1 index: Subject to change without notice

1·24

1.115(2.92)

TYP

MAX

Dimension in
inches (millimetersl.

00

February 1990
Edition 2.0

DATA SHEET

FUJITSU

MB81256-BO
MOS 262, 144 BIT DYNAMIC RANDOM ACCESS MEMORY
262,144 Bit Dynamic Random Access Memory
The Fujitsu MB81256 is a fully decoded, dynamic NMOS random access
memory organized as 262,144 one-bit words. The design is optimized for high speed,
high performance applications such as mainframe memory, buffer memory, peripheral
storage, and environments where low power dissipation and a compact layout are
required.
Mu~iplexed row and column address inputs permn the MB81256 to be housed in
standard 16-pin DIP and ZIP packages or an 18-pin PLCC package. Pinouts conform
to the JEDEC-approved pinouts. AddHionally, the MB81256 offers new functional
enhancements that make more versatile than previous dynamic RAMs. ~-before­
RJffi" refresh provides an on-chip refresh capability that is upwardly compatible with the
MB8266A. The MB81256 also features page mode which allows high speed random
access of up to 512 bHs of data within the same row.
The MB81256 is fabricated using silicon gate NMOS and FujHsu's advanced
Triple-layer Polysilicon process. This process, coupled wHh single-transistor memory
storage cells, permHs maximum circuH density and minimal chip size. Dynamic
circuHry is used in the design, including the sense amplifiers. Clock timing
requirements are noncrHical, and power supply tolerance is very wide. All inputs are
TTL compatible.

n

• 262,144 x 1 RAM organization
• Silico"1late. Triple Poly NMOS.
single Iransistor cell
• Row Access Time (tR/lC1
80 ns max. (MB 812:;6-80)
• Random Cycle Time (tRC)
175 ns min. (MB 81256-80)
• Page Mode Cycle Time (!Pc)
100 ns max. (MB 81256-80)
• Single..s V Supply. ±10% tolerance
• Low Power
385 mWmax. (MB81256-80)
25 mW max. (standby)
• 256 refresh cycles every 4 ms
• ~-before-ltlIS. ltlIS-only.
Hidden refresh capability

Absolute Maximum Ratings
Parameter

• High speed Read·white-Write cycle
• tAR. tWCR. toHR. tmw are eliminated
• Output unlatched ~cle end allows
twCKiimensional chiP select
• Common VO capability using
Early Write oparation
• On-chip latches for Addresses and
Data-in
• Standard IS-Pin Plastic Packages:
DIP (MB81256-XXP)
ZIP (MB81256-XXPSZ)
Standard IS-Pin Plastic PaCkage:
PLCC(MB81256-XXPV)
Standard 16-Pin Ceramic Package:
DIP (MB81256-XXC)

Symbol

Value

VIN. Your

-1 to +7

Voltage of Vcc supply relative to Vss

Vcc

-1 to +7

V

TSTG

-55 to +150

°c

I
I

Ceramic
Plastic

PLASTIC PACKAGE

LCC·18P·M04

PLASTIC PACKAGE
ZIP·16P·M01

DIP-16C-A03: See Page 17
DIP-16C-A04: See Page 18

PIN ASSIGNMENT

(See Note)

Voltage at any pin relatiw to Vss

Storage Temperature

..

PLASTIC PACKAGE
DIP·16P.M03

Unit
V

o
1 6 °otn

-55 to +125

Power Dissipation

Po

1.0

W

Short Circuit Output Current

-

50

rnA
Pin assignment for ZIP: See Page 22

_:

Permanent device damage may occur if absolute maximum ratings are exceeded.
Functional operation should be reslricted to the conditions as detailed in the oparation
sections of this data sheet Exposure to absolute maximum rating conditions for extended periods may affect devlC9 reliability.

This devIoe contains circuitry to protect the Inputs against
dM1age due to tigh static voltages or electric fields_ However. II:
Is acMsed that normal precautions be takan to avoid application
01 any IIOI1ago higher than maximum rated Vollag98 10 this high
In.,edance circuit.

Copjrlght © 1990 by FUJITSU LIMITED Mel Fujlblu M_ronk:o.lnc.

1-25

MB81256-80

Fig. 1 - MB 81256 BLOCK DIAGRAM

AS

AS

1

.-----

-

=~~"
-

r-rv'

AS

=u

CAPACITANCE

CLOCK GEN.
NO.2

WRITE
CLOCK
GEN.

-

DATA
IN
BUFF

-

•

--=)

COLUMN
DECODER

I

SENSE AMPS
1/0 GATING

j

-

:1:_

..... u.J

iii~8
0l..J_

j

a:

r-:1:_
f-U;:
-f-O

"'«a:

0l..J_

...

I

"

{ ;.-

r---~

~

r-,;

'----

w
Cl

0

U

DATA
OUT
BUFF

-

DOUT

262,144 BIT
STORAGE CELL

w
Cl

;:
0

a:

-Vee

_r---Vss

(TA = 25°C)

Parameter

Typ

Max

Unit

CIN1

7

pF

Input Capacitance RAS. CAS. WE

C IN2

10

pF

Output Capacitance

COUT

7

pF

Input Capacitance Ao to As.

1-26

I

I---

INTERNAL
ADDRESS
COUNTER

~

-~

I

M-J
REFRESH
CONTROL
CLOCK

-

CLOCK GEN.
NO.1

I

DOUT

Symbol
DIN

MB81256-80

RECOMMENDED OPERATING CONDITIONS
(Referenced to Vss)
Parameter

Symbol

Min

Typ

Max

Vcc

4.5

5.0

5.5

V

Vss

0

0

0

V

Input High Voltage, all inputs

V IH

2.4

6.5

V

Input Low Voltage, all inputs

V IL

-2.0

0.8

V

Supply Voltage

Operating
Temperature

Unit

..

O°C to +70°C

DC CHARACTERISTICS
(Recommended operating conditions unless otherwise noted.)
Value
Parameter

Symbol

Unit
Min

OPERATING CURRENT"
Average Power Supply Current
(RAS, CAS cycling; t RC ~ Min.)

Typ

Max

ICCl

70

rnA

Icc2

4.5

rnA

MB 81256-80

Icc3

60

rnA

PAGE MODE CURRENT"
Average Power Supply Current
(RAS ~ V IL , CAS cycling; tpc ~ Min.)

MB81256·80

Icc4

35

rnA

REFRESH CURRENT 2"
Average Power Supply Current
(CAS·before·RAS; tRC ~ Min.)

MB 81256·80

Icc5

65

rnA

MB 81256·80

STANDBY CURRENT
Standby Power Supply Current (RAS, CAS
REFRESH CURRENT 1"
Average Power Supply Current
(RAS cycling, CAS ~ V IH ; t RC

~

~

V IH )

Min.)

INPUT LEAKAGE CURRENT any input
(V IN ~ OV to 5.5V, Vcc ~ 4.5V to 5.5V, Vss
all other pins not under test ~ OV)

~

OV,

II(L)

-10

10

/lA

OUTPUT LEAKAGE CURRENT
(Data is disabled, V OUT ~ OV to 5.5V)

IO(L)

-10

10

/lA

OUTPUT LEVEL
Output Low Voltage (I OL

VOL

0.4

V

~

4.2mA)

OUTPUT LEVEL
Output High Voltage (loH ~ -5.0mA)

V OH

2.4

V

NOTE": Icc is depended on output loading and cycle rates. Specified values are obtained with the output open.

1-27

MB81256-80

AC CHARACTERISTICS

--

(Recommended operating conditions unless otherwise noted.)
Parameter
Time between Refresh
Random Read/Write Cycle Time
Read-Write Cycle Time
Access Time from RAS
Access Time from CAS

III!!
III!!

Value
Symbol

Min

Max

4

tREF
t RC

175

t RWC

180

Unit
ms
ns
ns

t RAC

80

ns

t CAC

45

ns

tOFF

0

25

ns

Transition Time

tT

3

50

ns

RAS Precharge Time

tRP

80

RAS Pulse Width

tRAs

85

RAS Hold Time

tRSH

50

CAS Pulse Width

tCAS

50

CAS Hold Time

tCSH

85

Output Buffer Turn off Delay

fH)

ns

100000

ns
ns

100000

ns
ns

tRco

20

CAS to RAS Set Up Time

tCRS

10

ns

Row Address Set Up Time

tASR

0

ns

Row Address Hold Time

tRAH

10

ns

Column Address Set Up Time

t ASC

0

ns

Column Address Hold Time

tCAH

15

ns

Read Command Set Up Time

t RCS

0

ns

Ii]

tRCH

0

ns

m

tRRH

20

ns

twcs

0

ns

Write Command Pulse Width

twp

15

ns

Write Command Hold Time

tWCH

15

ns
ns

RAS to CAS Delay Time

Read Command Hold Time Referenced to CAS
Read Command Hold Time Referenced to RAS
Write Command Set Up Time

1m

35

ns

tRWL

35

Write Command to CAS lead Time

tcwL

35

ns

Data In Set Up Time

tos

0

ns

Data In Hold Time

tOH

15

ns

tcwo

15

ns

Refresh Set Up Time for CAS Referenced to RAS
(CAS-before-RAS cycle)

tFCS

20

ns

Refresh Hold Time for CAS Referenced to RAS
(CAS-before-RAS cycle)

tFCH

20

ns

Write Command to RAS lead Time

CAS to WE Delay

1·28

111'11111-

1m

MB81256-80

AC CHARACTERISTICS

(Recommended operating conditions unless otherwise noted.)
Value
Parameter

Imm!.I

CAS Precharge Time (CAS-before-RAS cycle)

Symbol

Unit
Min

Max

t CPR

20

ns

RAS Precharge to CAS Active Time (Refresh cycles)

tRPC

20

ns

Page Mode Read/Write Cycle Time

tpc

100

ns

Page Mode Read-Write Cycle Time

t pRWC

100

ns

Page Mode CAS Precharge Time

tcp

40

ns

Refresh Counter Test Cycle Time

III

t RTC

330

Refresh Counter Test RAS Pulse Width

III

tTRAS

230

Refresh Counter Test CAS Precharge Time

III

t CPT

50

..

ms
10000

ns
ns

Notes:

D An

initial pause of 200 IlS is required after power-up.
And then several cycle (to which any 8 cycle to per·
form refresh are adequate) are required before proper
device operation is achieved.
If internal refresh counter is to be effective, a minimum of 8 CAS before !'lAS refresh cycles are required.

II
II

AC characteristics assume tT

=

5 ns.

V'H (min) and V'L (max) are refrence levels for measuring timing of input signals. Also, transition times
are measured between V'H (min) and V'L (max.).

I

Assumes that t RCD ~ t RCD (max.) If t RCD is greater
than the maximum recommended value shown in this
table, t RAC will increase by the amount that tRCD
exceeds the value shown.

II

Assumes that t RCD ~ tRCD (max.).

II Operation

within the t RcD (max) limit insures that
t RAC (max) can be met. t RCD (max) is specified as a
reference point only; if tRCD is greater than the
specified t RCD (max) limit, then access time is controlled exclusively by tCAc.

mt RCD

(min)

=

tRAH (min) + 2tT (t T

=

5ns) + t ASC

(min).

m

Either tRRH or t RCH must be satisfied for a read cycle.
and tcwD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If twcs ~ twcs (min),
the cycle is an early write cycle and the data out pin
will remain open circuit (high impedance) throughout
entire cycle.
If tCWD ~ tCWD (min) the cycle is a read-write cycle
and data out will contain data read from the selected
cell. If neither of the above sets of conditions is satisfied the condition of the data out is indeterminate .

III twcs

mMeasured with a load equivalent to 2 TTL loads and
100 pF.
•

Test mode cycle only.

1-29

MB81256-80

Read Cycle
~------------------tRC------------------------~

r-----------------t RAS-----------------j
RAS

VIHV 1L -

CAS

VIH- ------~~--------T_~ ~----tCAS-----, r-~Y---------------VIL -

J-~-----tRsHI-------_t"~

VIH-

ADDRESSES

VIL -

VIH
VIL-

WE

!---tCAC
r-------------tRAC:------------~

VOH-

DOUT

VOL

Ir--""V"'A-L'""ID:--......,,[

------------------ HIGH·Z ----------------